Patent Description:
Usage of various types of display devices, such as a liquid crystal display (LCD) device, and an organic light emitting diode (OLED) display device has become increasingly important with the widespread development of multimedia.

The OLED display device displays an image by using the OLED to generate light by variously configuring the image in accordance with a recombination of electrons and holes throughout a display area of the display device. Advantages of the OLED display device include fast response speed, high luminance and a large viewing angle, and low power Examples of known displays are provided in <CIT>, in <CIT>, and in <CIT>.

Thus far, resolution of some of the above-described display devices has included <NUM> Ultra High Definition (UHD), while <NUM> Ultra High Definition (<NUM> UHD) is under development. UHD refers to a resolution of <NUM>,<NUM> x <NUM>,<NUM> pixels, and <NUM> UHD refers to a resolution of <NUM>,<NUM> x <NUM>,<NUM> pixels.

Aspects of the disclosure provide a display device capable of realizing a high-resolution OLED display device in accordance with principles of the above-discussed UHD that minimizes a thickness of the display device and does so while maximizing the efficiency of manufacturing the same.

The invention concerns a display device as defined in claim <NUM>. The substantial equal average distance especially means that the distance is at least substantially the same and may be different for example by only a specific percentage, for example of maximum ten percent, or five percent or less. That is, the upper surface of the second conductive layer may be at least substantially on the same level from the substrate as the upper surface of the second insulating layer.

The upper surface of the second insulating layer extends from the upper surface of the second conductive layer in a thickness direction. In other words, at an boundary area, the second insulating layer overlaps the upper surface of the second conductive layer, for example due to a boundary surface between the two layers that is inclined with respect to the upper and/or lower surfaces of the two layers.

The second insulating layer may be disposed around the second conductive layer, and a sidewall of the second conductive layer may contact a sidewall of the second insulating layer.

An angle between the sidewall of the second conductive layer and a lower surface of the second conductive layer may be an acute angle, and an angle between the sidewall of the second insulating layer and a lower surface of the second insulating layer may be an obtuse angle.

The first electrode and the second conductive layer may be in direct contact with each other.

A thickness of the second conductive layer may be the same as a thickness of the second insulating layer.

A thickness of the second insulating layer may be smaller than a thickness of the first insulating layer.

The substrate may include a display area and a non-display area,.

The display device may further comprise a plurality of data lines disposed over the display area and the non-display area and a plurality of connection lines disposed in the display area, the plurality of connection lines being respectively connected to the plurality of data lines.

The display device may further comprise a third conductive layer disposed especially in electrical connection with the first conductive layer and the second conductive layer, wherein the second conductive layer may include the connection lines, and the first conductive layer may include the data lines.

The display device may further comprise a third insulating layer disposed on the second insulating layer and especially adjacent to the third conductive layer, wherein an average distance between an upper surface of the third conductive layer and the surface of the substrate is substantially equal to an average distance between an upper surface of the third insulating layer and the surface of the substrate. The substantial equal average distance especially means that the distance is at least substantially the same and may be different for example by only a specific percentage, for example of maximum ten percent, or five percent or less. That is, the upper surface of the third insulating layer may be at least substantially on the same level from the substrate as the upper surface of the third insulating layer.

The third insulating layer may include an organic insulating material.

The effects of the present disclosure are not limited to the above-described effects and other effects which are not described herein will become apparent to those skilled in the art from the following description. The meaning of the term "average distance" as described before also applies to the embodiments described in connection with the figures.

The above and other aspects and features of the disclosure will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings, in which:.

Aspects of the embodiments will now be described more fully hereinafter with reference to the accompanying drawings. Although aspects of the disclosure may be modified in various manners and have additional embodiments, embodiments are illustrated in the accompanying drawings and will be mainly described in the specification.

Some of the parts which are not associated with the description may not be provided in order to describe various embodiments and like reference numerals refer to like elements throughout the specification.

Further, in the specification, the phrase "in a plan view" means when an object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a cross-section taken by vertically cutting an object portion is viewed from the side. Additionally, the terms "overlap" or "overlapped" mean that a first object may be above or below or to a side of a second object, and vice versa.

When a layer, region, substrate, or area, is referred to as being "on" another layer, region, substrate, or area, it may be directly on the other film, region, substrate, or area, or intervening regions, substrates, or areas, may be present therebetween. Conversely, when a layer, region, substrate, or area, is referred to as being "directly on" another layer, region, substrate, or area, intervening layers, regions, substrates, or areas, may be absent therebetween. Further when a layer, region, substrate, or area, is referred to as being "below" another layer, region, substrate, or area, it may be directly below the other layer, region, substrate, or area, or intervening layers, regions, substrates, or areas, may be present therebetween. Conversely, when a layer, region, substrate, or area, is referred to as being "directly below" another layer, region, substrate, or area, intervening layers, regions, substrates, or areas, may be absent therebetween. Further, "over" or "on" may include positioning on or below an object and does not necessarily imply a direction based upon gravity.

The spatially relative terms "below", "beneath", "lower", "above", "upper", or the like, may be used herein for ease of description to describe the relations between one element or component and another element or component as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, in the case where a device illustrated in the drawing is turned over, the device positioned "below" or "beneath" another device may be placed "above" another device. Accordingly, the illustrative term "below" may include both the lower and upper positions. The device may also be oriented in other directions and thus the spatially relative terms may be interpreted differently depending on the orientations.

Throughout the specification, when an element is referred to as being "connected" to another element, the element may be "directly connected" to another element, or "electrically connected" to another element with one or more intervening elements interposed therebetween. It will be further understood that when the terms "comprises," "comprising," "includes" and/or "including" are used in this specification, they or it may specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and/or any combination thereof.

It will be understood that, although the terms "first," "second," "third," or the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element or for the convenience of description and explanation thereof. For example, when "a first element" is discussed in the description, it may be termed "a second element" or "a third element," and "a second element" and "a third element" may be termed in a similar manner without departing from the teachings herein.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this invention pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an ideal or excessively formal sense unless clearly defined in the specification.

<FIG> is a perspective view of a display device according to an embodiment. <FIG> is a plan view showing a manufacturing state of the display device of <FIG>.

Referring to <FIG> and <FIG>, the display device <NUM> may display an image. For example, the display device <NUM> may be an organic light emitting display (OLED), a liquid crystal display (LCD), a plasma display (PDP), a field emission display (FED), an electrophoretic display (EPD) or the like. Hereinafter, an organic light emitting diode (OLED) display device as the display device <NUM> will be described as an example, but the disclosure is not limited thereto.

The display device <NUM> may be applied to various products such as televisions, laptop computers, monitors, billboards and the Internet of Things as well as portable electronic devices such as mobile phones, smart phones, tablet personal computers (tablet PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems and ultra mobile PCs (UMPCs).

The display device <NUM> may include a main display surface <NUM> and sub-display surfaces <NUM> to <NUM>.

The main display surface <NUM> may have a substantially planar shape and may be located on one plane of the display device <NUM>. The main display surface <NUM> may have the largest area (or size) among the main display surface <NUM> and the sub-display surfaces <NUM> to <NUM>. For example, the main display surface <NUM> may be located on an upper surface of the display device <NUM>. The main display surface <NUM> may have a planar shape such as a polygonal shape such as a rectangular shape, a circular shape or an elliptical shape.

The sub-display surfaces <NUM> to <NUM> may be disposed on a plane different from the plane where the main display surface <NUM> is disposed. Each of the sub-display surfaces <NUM> to <NUM> may have an area smaller than the area of the main display surface <NUM>, and the sub-display surfaces <NUM> to <NUM> may be disposed on different planes. The sub-display surfaces <NUM> to <NUM> may be connected to the sides of the main display surface <NUM>, respectively, and may be bent from the main display surface <NUM> (or from the sides of the main display surface <NUM>).

For example, when the main display surface <NUM> has a rectangular shape, the display device <NUM> includes first to fourth sub-display surfaces <NUM> to <NUM>, and the first to fourth sub-display surfaces <NUM> to <NUM> may be connected to the four sides of the rectangle, respectively.

The first sub-display surface <NUM> may be connected to a first long side of the main display surface <NUM>, and may be bent in a vertical direction from the main display surface <NUM> to constitute a left side surface of the display device <NUM>. Similarly, the second sub-display surface <NUM> may be connected to a second long side of the main display surface <NUM>, and may be bent in the vertical direction from the main display surface <NUM> to form a right side surface of the display device <NUM>. The third sub-display surface <NUM> may be connected to a first short side of the main display surface <NUM> to form an upper side surface of the display device <NUM>, and the fourth sub-display surface <NUM> may be connected to a second short side of the main display surface <NUM> to form a lower side surface of the display device <NUM>.

The display device <NUM> may be a three-dimensional multi-surface display device that displays a screen on an upper surface and side surfaces of the display device <NUM>. Although <FIG> illustrates that a lower surface of the display device <NUM> does not include a display surface, this is merely exemplary, and the disclosure is not limited thereto. For example, the display device <NUM> may further include a lower surface which displays an image.

The display device <NUM> may include a display area DA and a non-display area NDA. The display area is an area which displays an image, and may include a pixel PX which is a light emitting unit for displaying an image. The non-display area is an area which does not display an image, and may not include the pixel PX. The pixel PX will be described later with reference to <FIG>.

The display area DA may include a main display area DA0 and first to fourth sub-display areas DA1 to DA4.

The main display area DA0 may be disposed on the main display surface <NUM>. For example, the main display surface <NUM> may include only the main display area DA0. The first sub-display area DA1 may be disposed on the first sub-display surface <NUM>, and the first sub-display area DA1 may be connected to the main display area DA0. Similarly, the second to fourth sub-display areas DA2 to DA4 are respectively disposed on the second to fourth sub-display surfaces <NUM> to <NUM>, and each of the second to fourth sub-display areas DA2 to DA4 may be connected to the main display area DA0.

The non-display area NDA may be disposed along the edge of the display area DA (or the outermost edge of the main display surface <NUM> and the sub-display surfaces <NUM> to <NUM>). A driving wiring, a driving circuit, and the like may be disposed in the non-display area NDA. The non-display area NDA may include, but is not limited to, a black matrix for blocking light leakage, decoration ink, and the like.

The non-display area NDA may include first to fourth non-display areas NDA1 to NDA4 (or first to fourth sub-non-display areas). The first non-display area NDA1 may be located on the first sub-display surface <NUM>. Similarly, the second to fourth non-display areas NDA2 to NDA4 may be disposed on the second to fourth sub-display surfaces <NUM> to <NUM>, respectively.

The non-display area NDA (or display device <NUM>) may include first to fourth corner wings <NUM> to <NUM> (i.e., corner portions, corner regions, corner wing regions). Each of the first to fourth corner wings <NUM> to <NUM> may be disposed adjacent to a corner (i.e., a portion where two sides meet) of the main display surface <NUM>. The first to fourth corner wings <NUM> to <NUM> may be substantially identical to each other except for their positions. Hereinafter, common features of the first to fourth corner wings <NUM> to <NUM> will be described with reference to the first corner wing <NUM>.

The first corner wing <NUM> may provide a space for passing or arranging data lines. When the first sub-display surface <NUM> and the fourth sub-display surface <NUM> are bent, the first corner wing <NUM> may be folded inward (i.e., in a direction toward the center of gravity of the display device <NUM>). For example, the first corner wing <NUM> may be folded along a folding line <NUM> such that one end (i.e., a first portion adjacent to the first sub-display surface <NUM>) of the first corner wing <NUM> and the other end (i.e., a second portion adjacent to the fourth sub-display surface <NUM>) of the first corner wing <NUM> may face each other. One end and the other end of the first corner wing <NUM> may be in contact with each other or may be coupled through a coupling layer or the like.

Since the first corner wing <NUM> is folded inward when folding the first sub-display surface <NUM> and the fourth sub-display surface <NUM>, the first corner wing <NUM> may not be exposed to the outside. Similarly, the second corner wing <NUM>, the third corner wing <NUM> and the fourth corner wing <NUM> may not be exposed to the outside. Accordingly, the first to fourth corner wings <NUM> to <NUM> may be included in the non-display area NDA.

The non-display area NDA may further include a driving area <NUM>, and the driving area <NUM> may be connected to at least one of the first to fourth sub-display surfaces <NUM> to <NUM>. For example, the driving area <NUM> may be connected to one side of the fourth sub-display surface <NUM> (e.g., the lower side of the fourth sub-display surface <NUM>).

As shown in <FIG>, when the fourth sub-display surface <NUM> is bent vertically with respect to the main display surface <NUM>, the driving area <NUM> may be further bent with respect to the fourth sub-display surface <NUM> (i.e., bent at an angle of <NUM>° with respect to the main display surface <NUM>), and disposed below the main display surface <NUM> in a thickness direction of the main display surface <NUM>. The driving area <NUM> may overlap the main display surface <NUM> and be parallel to the main display surface <NUM>.

The display device <NUM> may include a driving chip <NUM> (or a pad portion in which a driving chip is disposed and electrically connected to the driving chip), and the driving chip <NUM> may be disposed in the driving area <NUM>. The driving chip <NUM> may generate a driving signal necessary for driving the pixel PX and provide it to the display area DA (or the pixel PX). For example, the driving chip <NUM> may generate a data signal that determines the light emission luminance of the pixel PX. For example, the driving chip <NUM> may provide the data signal to the pixel PX through a driving wiring formed in the driving area and a data wiring formed on the main display surface <NUM> and one or more of the sub-display surfaces <NUM> to <NUM>, as described later.

Hereinafter, a configuration of the pixel of the display device will be described in detail.

<FIG> is a schematic cross-sectional view showing an example of the display device of <FIG>.

Referring to <FIG>, the display device <NUM> may include a substrate <NUM>, a buffer layer <NUM>, a semiconductor layer <NUM>, a first insulating layer <NUM>, a first gate conductive layer <NUM>, a second insulating layer <NUM>, a second gate conductive layer <NUM>, a third insulating layer <NUM>, a first source/drain conductive layer <NUM>, a fourth insulating layer <NUM>, a second source/drain conductive layer <NUM>, a fifth insulating layer <NUM>, a first electrode layer <NUM>, a light emitting element layer, and a second electrode layer <NUM>. Thin film transistors may be formed in a region ranging from the semiconductor layer <NUM> to the second gate conductive layer <NUM>, and thus the region ranging from the semiconductor layer <NUM> to the second gate conductive layer <NUM> may be collectively referred to as a driving element layer. The numbering of the insulating layers may be different, when describing the present invention. Especially, when regarding the first to third insulating <NUM>, <NUM>, <NUM> as minor important and not of specific relevance for the present invention, the fourth insulating layer <NUM> may be termed as first insulating layer, fifth insulating layer <NUM> may be termed as second insulating layer, and the sixth insulating layer <NUM> may be termed as third insulating layer.

The substrate <NUM> may support the respective layers disposed thereon. The substrate <NUM> may be made of an insulating material. The substrate <NUM> may be made of an inorganic material such as glass or quartz, or may be made of an organic material such as polyimide. The substrate <NUM> may be a rigid substrate or a flexible substrate.

The buffer layer <NUM> may be disposed on the substrate <NUM>. The buffer layer <NUM> may prevent diffusion of impurity ions, prevent penetration of moisture or external air, and perform a surface planarization function. The buffer layer <NUM> may include silicon nitride, silicon oxide, silicon oxynitride, or the like. The buffer layer <NUM> may be omitted depending on the type of the substrate <NUM>, manufacturing considerations, and the like.

The semiconductor layer <NUM> may be disposed on the buffer layer <NUM>. The semiconductor layer <NUM> may include first and second semiconductor patterns 105_1 and 105_2, and the first and second semiconductor patterns 105_1 and 105_2 may constitute channels of transistors. For example, the first semiconductor pattern 105_1 may form a channel of a driving transistor, and the second semiconductor pattern 105_2 may form a channel of a switching transistor.

The semiconductor layer <NUM> may include polycrystalline silicon. In the semiconductor layer <NUM>, a portion (e.g., source and drain regions) connected to a source electrode and a drain electrode of the thin film transistor may be doped with impurity ions (e.g., p-type impurity ions). A trivalent dopant such as boron (B) may be used as the p-type impurity ions. The semiconductor layer <NUM> may include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor such as ITZO or IGZO instead of the polycrystalline silicon.

The first insulating layer <NUM> may be disposed on the semiconductor layer <NUM>. The first insulating layer <NUM> may be a gate insulating layer having a gate insulating function.

The first gate conductive layer <NUM> may be disposed on the first insulating layer <NUM>. The first gate conductive layer <NUM> may include first and second gate conductive patterns 110_1 and 110_2. The first and second gate conductive patterns 110_1 and 110_2 may include gate electrodes of transistors, respectively. For example, the first gate conductive pattern 110_1 may include a gate electrode of the driving transistor, and the second gate conductive pattern 110_2 may include a gate electrode of the switching transistor.

The first gate conductive layer <NUM> may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu).

The second insulating layer <NUM> may be disposed on the first gate conductive layer <NUM>. The second insulating layer <NUM> may be an interlayer insulating layer.

The second gate conductive layer <NUM> may be disposed on the second insulating layer <NUM>. The second gate conductive layer <NUM> may include materials exemplified as the constituent materials of the first gate conductive layer <NUM>.

The second gate conductive layer <NUM> may include a third gate conductive pattern <NUM>. The third gate conductive pattern <NUM> may include a second electrode of a sustain capacitor. The third gate conductive pattern <NUM> may overlap the first gate conductive pattern 110_1 with the second insulating layer <NUM> interposed therebetween to form a capacitor. The third gate conductive pattern <NUM> may include materials exemplified as the constituent materials of the first gate conductive layer <NUM>.

The third insulating layer <NUM> may be disposed on the second gate conductive layer <NUM>.

The first source/drain conductive layer <NUM> may be disposed on the third insulating layer <NUM>.

The first source/drain conductive layer <NUM> may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The first source/drain conductive layer <NUM> may be a single layer or a multilayer. For example, the first source/drain conductive layer <NUM> have a stacked structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, or Ti/Cu.

The first source/drain conductive layer <NUM> may include a first source electrode <NUM> and a first drain electrode <NUM> of the driving transistor, a second source electrode <NUM> and a second drain electrode <NUM> of the switching transistor, a data wiring <NUM> and a first power supply wiring <NUM>.

The first source electrode <NUM> may be in contact with the first semiconductor pattern 105_1 through a contact hole passing through the second insulating layer <NUM> and the third insulating layer <NUM> to expose one end of the first semiconductor pattern 105_1.

Further, the first drain electrode <NUM> may be in contact with the first semiconductor pattern 105_1 through a contact hole passing through the second insulating layer <NUM> and the third insulating layer <NUM> to expose the other end of the first semiconductor pattern 105_1.

Further, the second source electrode <NUM> may be in contact with the second semiconductor pattern 105_2 through a contact hole passing through the second insulating layer <NUM> and the third insulating layer <NUM> to expose one end of the second semiconductor pattern 105_2.

Further, the second drain electrode <NUM> may be in contact with the second semiconductor pattern 105_2 through a contact hole passing through the second insulating layer <NUM> and the third insulating layer <NUM> to expose the other end of the second semiconductor pattern 105_2.

The fourth insulating layer <NUM> may be disposed on the first source/drain conductive layer <NUM>, and the second source/drain conductive layer <NUM> may be disposed on the fourth insulating layer <NUM>. The second source/drain conductive layer <NUM> may include a metal forming the first source/drain conductive layer <NUM>.

The second source/drain conductive layer <NUM> may include a first connection electrode <NUM>. The first connection electrode <NUM> may be disposed to overlap the first source electrode <NUM> in plan view. The first connection electrode <NUM> may be electrically connected to the source electrode <NUM> of the driving transistor through a contact hole passing through the fourth insulating layer <NUM>.

The upper surface of the first connection electrode <NUM> may be in contact with the lower surface of an anode electrode <NUM>. The lower surface of the first connection electrode <NUM> may be in contact with the upper surface of the fourth insulating layer <NUM>. The side surface of the first connection electrode <NUM> may be disposed between the upper surface and the lower surface of the first connection electrode <NUM>.

The fifth insulating layer <NUM> may be disposed on the second source/drain conductive layer <NUM>. The fifth insulating layer <NUM> may include an organic insulating material.

The upper surface of the fifth insulating layer <NUM> may be in contact with the lower surface of the anode electrode <NUM>, and the lower surface of the fifth insulating layer <NUM> may be in contact with the upper surface of the fourth insulating layer <NUM>. Further, the fifth insulating layer <NUM> may surround the first connection electrode <NUM>, and the side surface of the first connection electrode <NUM> may be in contact with the side surface of the fifth insulating layer <NUM>. The side surface of the first connection electrode <NUM> may have an inclination of an acute angle, and the sidewall of the fifth insulating layer <NUM>, which is in contact with the side surface of the first connection electrode <NUM>, may have an inclination of an obtuse angle. In other words, the side surface of the first connection electrode <NUM> may be inclined at an acute angle between the side surface of the first connection electrode <NUM> and a lower surface of the first connection electrode <NUM>, and the sidewall of the fifth insulating layer <NUM> may be inclined at an obtuse angle between the sidewall of the fifth insulating layer <NUM> and a lower surface of the fifth insulating layer <NUM>.

The thickness of the first connection electrode <NUM> and the thickness of the fifth insulating layer <NUM> may be substantially equal to each other. As used herein, the term substantially may mean as imparting a deviation of the associated parameter that is five percent or less therefrom. For example, the one of the aforementioned thicknesses may deviate from the other thereof by five percent or less and still be considered to be substantially equal to the other thickness. Other percentages may also be applicable as the aforementioned is merely exemplary. The thickness of the first connection electrode <NUM> may be measured without the electrical connecting part connecting the first connection electrode <NUM> electrically to the source electrode <NUM>, that is, without the part within the contact hole passing through the fourth insulating layer <NUM>. The thickness thus refers only to the head portion of the first connection electrode <NUM> as shown in <FIG>, that is, the portion positioned above the fourth insulating layer <NUM>.

The upper surface of the first connection electrode <NUM> and the upper surface of the fifth insulating layer <NUM> may be disposed at the same level from the substrate <NUM>. For example, such disposition of the respective upper surfaces at the same level from the surface of the substrate <NUM> may mean that the distance from the surface of the substrate <NUM> to each upper surface is substantially the same. That is, the average distance from the upper surface of the first connection electrode <NUM> to the upper surface of the substrate <NUM> may be substantially equal to the average distance from the upper surface of the fifth insulating layer <NUM> to the upper surface of the substrate <NUM>. As a result, the upper surface of the first connection electrode <NUM> may extend to meet portions of the upper surface of the fifth insulating layer <NUM> and extend with those upper surface portions of the fifth insulating layer <NUM>, such that the upper surface of the first connection electrode <NUM> and the upper surface of the fifth insulating layer <NUM> are disposed in a common plane, i.e., are coplanar.

The average distance from the upper surface of the first connection electrode <NUM> to the upper surface of the fourth insulating layer <NUM> may be substantially equal to the average distance from the upper surface of the fifth insulating layer <NUM> to the upper surface of the fourth insulating layer <NUM>.

The term, average distance, may be understood as that distance which includes an intervening space between two parts, e.g., the first connection electrode <NUM> and the fourth insulating layer <NUM>. That is, the average distance may include and may account for all surface contouring, material thicknesses, and material deposition forming the aforementioned two parts, as well as that of any intervening part or parts between the two parts. As such, the average distance may describe a relative distance that accurately reflects the relationship among the two parts irrespective of their constructions and the constructions of one or more parts intervening therebetween.

The first connection electrode <NUM> and the fifth insulating layer <NUM> may not overlap each other in the thickness direction. There may be an exceptional area to such non-overlapping between the first connection electrode <NUM> and the fifth insulating layer <NUM> in the thickness direction. For example, the exceptional area may include an area where the inclined side surfaces of the first connection electrode <NUM> are in contact with the inclined sidewalls of the fifth insulating layer <NUM>. In other words, the side surfaces of the first connection electrode <NUM> and the sidewalls of the fifth insulating layer <NUM> may overlap each other in the thickness direction.

The side surface of the first connection electrode <NUM> may not be in contact with the anode electrode <NUM>. The upper surface of the first connection electrode <NUM> may not be in contact with the fifth insulating layer <NUM>.

The thickness of the first connection electrode <NUM> may be larger than the thickness of the fifth insulating layer <NUM>.

The average distance from the upper surface of the first connection electrode <NUM> to the upper surface of the substrate <NUM> may be larger than the average distance from the upper surface of the fifth insulating layer <NUM> to the upper surface of the substrate <NUM>.

The average distance from the upper surface of the first connection electrode <NUM> to the upper surface of the fourth insulating layer <NUM> may be larger than the average distance from the upper surface of the fifth insulating layer <NUM> to the upper surface of the fourth insulating layer <NUM>.

The side surface of the first connection electrode <NUM> may be partially in contact with the anode electrode <NUM>. The upper surface of the first connection electrode <NUM> may not be in contact with the fifth insulating layer <NUM>.

The thickness of the fifth insulating layer <NUM> may be smaller than the thickness of the second insulating layer <NUM>, the third insulating layer <NUM> and/or the fourth insulating layer <NUM>.

The surface roughness of the upper surface of the fifth insulating layer <NUM> may be larger than the surface roughness of the upper surface of the second insulating layer <NUM>, the third insulating layer <NUM> and/or the fourth insulating layer <NUM>.

Further, the surface roughness of the upper surface of the fifth insulating layer <NUM> may be larger than the surface roughness of the upper surface of the first connection electrode <NUM>.

The surface roughness of the upper surface of the first connection electrode <NUM> may be larger than the surface roughness of the side surface of the first connection electrode <NUM>.

The first electrode layer <NUM> may be disposed on the fifth insulating layer <NUM>. The first electrode layer <NUM> may include the anode electrode <NUM> of the light emitting element OLED. The anode electrode <NUM> may be in direct contact with the first connection electrode <NUM>.

The anode electrode <NUM> may have a uniform thickness. That is, the average distance (as defined before) or the distance from the upper surface of the anode electrode <NUM> to the upper surface of the fifth insulating layer <NUM> may be substantially the same as the average distance or the distance from the upper surface of the anode electrode <NUM> to the upper surface of the first connection electrode <NUM>. That is, the anode electrode <NUM> may be in direct contact with the first connection electrode <NUM> without a separate contact hole. Accordingly, since a contact pad region may be omitted, an area of the pixel PX may be optimized as high resolution thereof may also be achieved.

The light emitting element layer may be disposed on the first electrode layer <NUM>, and the light emitting element layer may include a pixel defining layer <NUM> and an organic light emitting layer EL.

The pixel defining layer <NUM> may be disposed on the anode electrode <NUM> along the edge of the anode electrode <NUM>, and may include an opening exposing the anode electrode <NUM>. The opening may overlap a region where the anode electrode <NUM> and the first connection electrode <NUM> are in contact with each other.

The organic light emitting layer EL may be disposed in the opening of the pixel defining layer <NUM>. The organic light emitting layer EL may include an organic light emitting layer, a hole injecting/transporting layer, and an electron injecting/transporting layer. The organic light emitting layer EL may overlap a region where the anode electrode <NUM> and the first connection electrode <NUM> are in contact with each other.

The second electrode layer <NUM> may be disposed on the organic light emitting layer EL and the pixel defining layer <NUM>. A cathode electrode <NUM> of the light emitting element OLED may be disposed in the second electrode layer <NUM>. The cathode electrode <NUM> may be a common electrode disposed over the entire display area of the display device <NUM>.

As described above, in the display device <NUM>, the anode electrode <NUM> and the first connection electrode <NUM> may be in direct contact with each other without a separate contact hole. Accordingly, since the contact pad region may be omitted, the area of the pixel PX may be optimized as high resolution may also be easily achieved. In addition, by omitting the contact hole forming process, it is possible to reduce the number of hole forming masks, thereby reducing a cost associated with simplifying the manufacturing process of a pixel PX.

Further, since the anode electrode <NUM> and the organic light emitting layer EL are formed flat with a uniform thickness, the display quality for an image be further improved.

<FIG> is a plan view of a display device according to another embodiment. <FIG> is a schematic cross-sectional view taken along line V-V' of <FIG>. <FIG> is a schematic cross-sectional view showing a pixel of the display device of <FIG>.

Referring to <FIG>, a display device 1_1 according to the embodiment may include a data wiring <NUM>, a connection wiring <NUM> and a driving wiring <NUM>.

Meanwhile, the arrangement of the data wiring <NUM>, the connection wiring <NUM> and the drive wiring <NUM> may be symmetrical with respect to a reference axis (not shown) extending in a first direction W1 and passing through the center of the area of the display device 1_1. Hereinafter, the data wiring <NUM>, the connection wiring <NUM> and the drive wiring <NUM>, which are relatively adjacent to the first sub-display surface <NUM>, will be mainly described.

The data wiring <NUM> may include data lines D1 to Dm (where m is an integer of <NUM> or more).

The data lines D1 to Dm may extend in the first direction W1 and may be sequentially arranged at specific intervals along a second direction W2. Each of the data lines D1 to Dm may extend across the display area DA in the first direction W1. Here, among the data lines D1 to Dm, first to k-th data lines may be disposed on one display surface (where k is a positive integer equal to or greater than <NUM> but less than m). Hereinafter, an instance in which k is <NUM> and m is greater than <NUM> will be described as an example.

The connection wiring <NUM> may electrically connect a portion of the data wiring <NUM> and a portion of the drive wiring <NUM>. The connection wiring <NUM> may be disposed on a layer different from the layer where the data wiring <NUM> is disposed, and the connection wiring <NUM> may be insulated from the data wiring <NUM> through an insulating layer, which will be described later with reference to <FIG>.

The connection wiring <NUM> may include first to kth connection lines DM1 to DMk corresponding to the first to mth data lines D1 to Dm. When k is <NUM>, the connection wiring <NUM> may include the first to seventh connection lines DM1 to DM7. The connection lines DM1 to DM7 may correspond to the data lines D1 to D7 disposed on the first sub-display surface <NUM>, respectively.

The connection lines DM1 to DMk may extend from the fourth non-display area NDA4 (e.g., a lower portion of the fourth non-display area NDA4) of the fourth sub-display surface <NUM> to one end (e.g., the first corner wing <NUM> and a lower portion of the first non-display area NDA1 of the first sub-display surface <NUM>) of the corresponding data wiring <NUM> via the display area DA. The connection lines DM1 to DMk may be separated from each other at predetermined intervals of spacing. The interval of spacing between each of the connection lines DM1 to DMk may be equal to the interval of spacing between each of the data lines D1 to Dm.

Further, the connection lines DM1 to DMk may extend from the fourth non-display area NDA4 (e.g., a lower portion of the fourth non-display area NDA4) of the fourth sub-display surface <NUM> in the first direction W1 (e.g., upward), extend to change the direction to the second direction W2 (e.g., leftward) in the display area DA, and extend to one end (i.e., a lower portion of the first non-display area NDA1 of the first sub-display surface <NUM>) of the corresponding data wiring <NUM> in a region adjacent to or intersecting with the corresponding data wiring <NUM>.

Each of the connection lines DM1 to DMk may include a first portion extending from the fourth non-display area NDA4 in the first direction W1, a second portion extending from one end of the first portion in the second direction W2, and a third portion extending from one end of the second portion in the first direction W1 (or a direction opposite to the first direction W1).

As shown in <FIG>, the first portion of each of the connection lines DM1 to DMk may overlap one of the data lines D1 to Dm in the display area DA in plan view. For example, the first portion of the first connection line DM1 may overlap the eighth data line D8, and the first portion of the seventh connection line DM7 may overlap the fourteenth data line D14. However, this is merely exemplary, and the disclosure is not limited thereto. For example, the first portion of each of the first to seventh connection lines DM1 to DM7 may not overlap the first to mth data lines D1 to Dm in the display area DA in plan view.

Further, as shown in <FIG>, the third portion of each of the connection lines DM1 to DMk may be disposed to overlap one of the data lines D1 to Dm in plan view. For example, the third portion of the first connection line DM1 may overlap the seventh data line D7, and the third portion of the second connection line DM2 may overlap the sixth data line D6.

Meanwhile, although <FIG> illustrates that the connection wiring <NUM> is bent at a right angle, the disclosure is not limited thereto.

The connection lines <NUM> do not intersect each other in plan view and, thus, may be disposed to bypass other connection lines relatively adjacent to the first corner wing <NUM>. For example, the first connection line DM1 may be disposed to bypass the second connection line DM2. That is, as the connection line <NUM> may be disposed closer to the corner wing (e.g., the first corner wing <NUM>), the connection line <NUM> may be bent at a position closer to the driving area <NUM>, and as the connection line <NUM> may be disposed further away from the corner wing, the connection line <NUM> may be bent at a position further separated from the driving area <NUM>.

As the connection line relatively separated from the first corner wing <NUM> may be disposed to bypass other connection lines relatively adjacent to the first corner wing <NUM>, the connection lines <NUM> may have different lengths. For example, the length of the second connection line DM2 may be longer than the length of the first connection line DM1. That is, the length of the (i+<NUM>)th connection line DMi+<NUM> may be longer than the length of the ith connection line DMi (where i is a positive integer).

The connection lines <NUM> may be directly connected one-to-one to the data lines <NUM>, respectively, through contact holes CNT (i.e., contact holes CNT formed in the non-display area NDA) formed in the second corner wing <NUM> and the lower portion of the first non-display area NDA1. For example, the first connection line DM1 may be electrically connected to the seventh data line D7, and the seventh connection line DM7 may be electrically connected to the first data line D1. That is, the ith connection line DMi may be electrically connected to the (k+<NUM>-i)th data line DMk+<NUM>-i.

For example, as shown in <FIG>, the sixth data line D6 may be disposed on the third insulating layer <NUM>, the second to fourth connection lines DM2 to DM4 may be disposed on the fourth insulating layer <NUM>, and the second to fourth connection lines DM2 to DM4 may be insulated from the sixth data line D6 by the fourth insulating layer <NUM>. The second connection line DM2 may extend to one end of the sixth data line D6 and may be electrically connected to the sixth data line D6 through the contact hole CNT passing through the fourth insulating layer <NUM> to expose one end of the sixth data line D6.

The driving wiring <NUM> may include driving lines 61a to 67a and 61b to 67b (or pad wirings and pad connection wirings), and the driving lines 61a to 67a and 61b to 67b may extend from the driving chip <NUM> (or a pad portion on which the driving chip <NUM> is disposed) to the fourth non-display area NDA4 (or a tangent line of the fourth sub-display surface <NUM> and the driving area <NUM>) of the fourth sub-display surface <NUM>.

The driving lines 61a to 67a and 61b to 67b may be divided into a first driving wiring group 60a and a second driving wiring group 60b.

The driving lines 61a to 67a included in the first driving wiring group 60a may be disposed on a layer different from the layer on which the driving lines 61b to 67b included in the second driving wiring group 60b may be disposed. The driving lines 61a to 67a included in the first driving wiring group 60a may intersect the driving lines 61b to 67b included in the second driving wiring group 60b in plan view. The driving lines 61a to 67a included in the first driving wiring group 60a may be insulated from the driving lines 61b to 67b included in the second driving wiring group 60b through a separate insulating layer.

The driving lines 61a to 67a included in the first driving wiring group 60a may be electrically connected to the data lines D1 to D7 disposed on the first sub-display surface <NUM> through the connection lines DM1 to DM7, respectively. The driving lines 61b to 67b included in the second driving wiring group 60b may be electrically connected to the data lines D8 to D14 disposed on the main display surface <NUM>, respectively.

As described above, the display device <NUM> may include the connection wiring <NUM> disposed in an area including the display area DA, and an image signal may be provided from the driving chip <NUM> to the data lines D1 to Dm disposed on the first sub-display surface <NUM> (and the second sub-display surface <NUM>) through the connection wiring <NUM>. Thus, a dead space which may be required to directly connect the data wiring <NUM> disposed on the first sub-display surface <NUM> (and the second sub-display surface <NUM>) to the driving wiring <NUM> may be unnecessary. In other words, no dead space is necessitated to connect the data wiring <NUM> to the driving wiring <NUM> since the image signal from the driving chip <NUM> may be provided to the data wiring <NUM> (or the data lines D1 to Dm) through the connection wiring <NUM> (or the connection lines DM1 to DM7). As a result, overall dead space of the display device <NUM> may be reduced or its increase may be prevented.

Further, by forming the contact hole CNT electrically connecting the data wiring <NUM> to the connection wiring <NUM> in the non-display area NDA, it is possible to prevent the interference of the contact hole CNT with respect to the pixel PX (or a constitutive signal provided to the pixel PX). Therefore, the display quality of the display device <NUM> may be improved.

The pixel configuration of the above-described display device 1_1 will be described in more detail below. The display device 1_1 of <FIG> may be substantially the same as or similar to the display device <NUM> of <FIG> other than aspects of the second source/drain conductive layer <NUM>, a third source/drain conductive layer <NUM>, the fifth insulating layer <NUM> and a sixth insulating layer <NUM>.

The second source/drain conductive layer <NUM> may include the connection wiring <NUM> (i.e., the connection wiring <NUM> described with reference to <FIG>). The connection wiring <NUM> may be disposed to overlap the data wiring <NUM> in plan view.

A fifth insulating layer <NUM>' may be disposed on the second source/drain conductive layer <NUM>, and the third source/drain conductive layer <NUM> may be disposed on the fifth insulating layer <NUM>'. The third source/drain conductive layer <NUM> may include a metal constituting the first source/drain conductive layer <NUM> and/or the second source/drain conductive layer <NUM>.

The third source/drain conductive layer <NUM> may include a second connection electrode <NUM>. The second connection electrode <NUM> may be disposed to overlap the first connection electrode <NUM> in plan view. The second connection electrode <NUM> may be in contact with the first connection electrode <NUM> through the contact hole passing through the fifth insulating layer <NUM>', and may be electrically connected to the first source electrode <NUM> of the driving transistor.

The upper surface of the second connection electrode <NUM> may be in contact with the lower surface of the anode electrode <NUM>. The lower surface of the second connection electrode <NUM> may be in contact with the upper surface of the fifth insulating layer <NUM>'. The side surface of the second connection electrode <NUM> may be disposed between the upper surface and the lower surface of the second connection electrode <NUM>.

The sixth insulating layer <NUM> may be disposed on the third source/drain conductive layer <NUM>. The sixth insulating layer <NUM> may include an organic insulating material.

The upper surface of the sixth insulating layer <NUM> may be in contact with the lower surface of the anode electrode <NUM>, and the lower surface of the sixth insulating layer <NUM> may be in contact with the upper surface of the fifth insulating layer <NUM>'. Further, the sixth insulating layer <NUM> may be disposed around or to surround the second connection electrode <NUM>, and the side surface of the second connection electrode <NUM> may be in contact with the side surface of the sixth insulating layer <NUM>. The side surface of the second connection electrode <NUM> may have an inclination of an acute angle, and the sidewall of the sixth insulating layer <NUM>, which is in contact with the side surface of the second connection electrode <NUM>, may have an inclination of an obtuse angle. In other words, the side surface of the second connection electrode <NUM> may be inclined at an acute angle between the side surface of the second connection electrode <NUM> and a lower surface of the second connection electrode <NUM>, and the sidewall of the sixth insulating layer <NUM> may be inclined at an obtuse angle between the sidewall of the sixth insulating layer <NUM> and a lower surface of the sixth insulating layer <NUM>.

The thickness of the second connection electrode <NUM> and the thickness of the sixth insulating layer <NUM> may be substantially equal to each other. The thickness of the second connection electrode <NUM> may be measured without the electrical connecting part connecting the second connection electrode <NUM> electrically to the first connecting electrode <NUM>, that is, without the part within the contact hole passing through the fifth insulating layer <NUM>'. The thickness thus refers only to the head portion of the second connection electrode <NUM> as shown in <FIG>, that is, the portion positioned above the fifth insulating layer <NUM>'.

The upper surface of the second connection electrode <NUM> and the upper surface of the sixth insulating layer <NUM> may be disposed at the same level from the substrate <NUM>. That is, the average distance from the upper surface of the second connection electrode <NUM> to the upper surface of the substrate <NUM> may be substantially equal to the average distance from the upper surface of the sixth insulating layer <NUM> to the upper surface of the substrate <NUM>.

The average distance from the upper surface of the second connection electrode <NUM> to the upper surface of the fifth insulating layer <NUM>' may be substantially equal to the average distance from the upper surface of the sixth insulating layer <NUM> to the upper surface of the fifth insulating layer <NUM>'.

The second connection electrode <NUM> and the sixth insulating layer <NUM> may not overlap each other in the thickness direction.

However, the disclosure is not limited thereto, and the thickness of the second connection electrode <NUM> may be greater than the thickness of the sixth insulating layer <NUM>.

For example, average distance from the upper surface of the second connection electrode <NUM> to the upper surface of the substrate <NUM> may be larger than the average distance from the upper surface of the sixth insulating layer <NUM> to the upper surface of the substrate <NUM>.

Further, the average distance from the upper surface of the second connection electrode <NUM> to the upper surface of the fifth insulating layer <NUM>' may be larger than the average distance from the upper surface of the sixth insulating layer <NUM> to the upper surface of the fifth insulating layer <NUM>'.

Further, the thickness of the sixth insulating layer <NUM> may be smaller than the thickness of the second insulating layer <NUM>, the third insulating layer <NUM>, the fourth insulating layer <NUM> and/or the fifth insulating layer <NUM>.

The surface roughness of the upper surface of the sixth insulating layer <NUM> may be larger than the surface roughness of the upper surface of the second insulating layer <NUM>, the third insulating layer <NUM>, the fourth insulating layer <NUM> and/or the fifth insulating layer <NUM>.

Further, the surface roughness of the upper surface of the sixth insulating layer <NUM> may be larger than the surface roughness of the upper surface of the second connection electrode <NUM>.

The surface roughness of the upper surface of the second connection electrode <NUM> may be larger than the surface roughness of the side surface of the second connection electrode <NUM>.

The first electrode layer <NUM> may be disposed on the sixth insulating layer <NUM>. The first electrode layer <NUM> may include the anode electrode <NUM> of the light emitting device OLED. The anode electrode <NUM> may be in direct contact with the second connection electrode <NUM>.

One surface of the sixth insulating layer <NUM> may be in contact with the lower surface of the anode electrode <NUM>.

The average distance from the upper surface of the anode electrode <NUM> to the upper surface of the sixth insulating layer <NUM> may be substantially the same as the average distance from the upper surface of the anode electrode <NUM> to the upper surface of the second connection electrode <NUM>. That is, the anode electrode <NUM> may be in direct contact with the second connection electrode <NUM> without a separate contact hole.

The contact area between the anode electrode <NUM> and the second connection electrode <NUM> may be larger than the contact area between the sixth insulating layer <NUM> and the second connection electrode <NUM>.

Although not shown in the drawings, the driving lines (i.e., driving lines connected to the connection wiring <NUM>) included in the first driving wiring group 60a may be disposed on the second gate conductive layer <NUM>, and the driving lines (i.e., driving lines directly connected to the data lines) included in the second driving wiring group 60b may be disposed on the first gate conductive layer <NUM>.

In the display device 1_1, the anode electrode <NUM> and the second connection electrode <NUM> may be in direct contact with each other without a separate contact hole. Thus, it may possible to realize high resolution by omitting the contact pad region and to simplify the manufacturing process by omitting the contact hole forming process, as described above.

<FIG> is a cross-sectional view showing a pixel of a display device according to still another embodiment.

Referring to <FIG>, a display device 1_2 according to the embodiment differs from the embodiment of <FIG> in that a second connection electrode <NUM>' may be in contact with the first connection electrode <NUM> without a separate contact hole.

The upper surface of the second connection electrode <NUM>' may be in contact with the lower surface of the anode electrode <NUM>, and the lower surface of the second connection electrode <NUM>' may be in direct contact with the upper surface of the first connection electrode <NUM> and the upper surface of the fifth insulating layer <NUM>.

The upper surface of a sixth insulating layer <NUM>' may be in contact with the lower surface of the anode electrode <NUM>, and the lower surface of the sixth insulating layer <NUM>' may be in contact with the upper surface of the fifth insulating layer <NUM>.

The thickness of the sixth insulating layer <NUM>' may be the same as the thickness of the second connection electrode <NUM>'.

The average distance from the upper surface of the sixth insulating layer <NUM>' to the upper surface of the fifth insulating layer <NUM> may be substantially the same as the average distance from the upper surface of the second connection electrode <NUM>' to the upper surface of the first connection electrode <NUM>.

Further, the average distance from the upper surface of the sixth insulating layer <NUM>' to the upper surface of the fifth insulating layer <NUM> may be substantially the same as the average distance from the upper surface of the second connection electrode <NUM>' to the upper surface of the fifth insulating layer <NUM>.

The upper surface of the first connection electrode <NUM> may be in contact with the lower surface of the second connection electrode <NUM>', and the lower surface of the first connection electrode <NUM> may be in contact with the upper surface of the fourth insulating layer <NUM>.

The upper surface of the connection wiring <NUM> may be in contact with the lower surface of the fifth insulating layer <NUM>', and the lower surface of the connection wiring <NUM> may be in contact with the upper surface of the fourth insulating layer <NUM>.

The thickness of the first connection electrode <NUM> and the connection wiring <NUM> may be the same as the thickness of the fifth insulating layer <NUM>'. The thickness of the first connection electrode <NUM> may be measured without the electrical connecting part connecting the first connection electrode <NUM> electrically to the source electrode <NUM>, that is, without the part within the contact hole passing through the fourth insulating layer <NUM>. The thickness thus refers only to the head portion of the first connection electrode <NUM> as shown in <FIG>, that is, the portion positioned above the fourth insulating layer <NUM>.

The average distance from the upper surface of the fifth insulating layer <NUM> to the upper surface of the fourth insulating layer <NUM> may be substantially the same as the average distance from the upper surface of the first connection electrode <NUM> to the upper surface of the fourth insulating layer <NUM>.

The average distance from the upper surface of the fifth insulating layer <NUM> to the upper surface of the fourth insulating layer <NUM> may be substantially the same as the average distance from the upper surface of the connection wiring <NUM> to the upper surface of the fourth insulating layer <NUM>.

The thickness of the anode electrode <NUM> may be uniform.

The average distance from the upper surface of the anode electrode <NUM> to the upper surface of the fifth insulating layer <NUM> may be substantially the same as the average distance from the upper surface of the anode electrode <NUM> to the upper surface of the first connection electrode <NUM>.

The contact area between the anode electrode <NUM> and the second connection electrode <NUM>' may be larger than the contact area between the sixth insulating layer <NUM>' and the second connection electrode <NUM>'.

The thickness of the sixth insulating layer <NUM>' and/or the fifth insulating layer <NUM> may be smaller than the thickness of the fourth insulating layer <NUM>, the third insulating layer <NUM> and/or the second insulating layer <NUM>.

The surface roughness of the upper surface of the sixth insulating layer <NUM>' and the fifth insulating layer <NUM> may be larger than the surface roughness of the upper surface of the fourth insulating layer <NUM>, the third insulating layer <NUM> and/or the second insulating layer <NUM>.

The surface roughness of the upper surface of the sixth insulating layer <NUM>' and the fifth insulating layer <NUM> may be larger than the surface roughness of the upper surface of the first connection electrode <NUM> and the second connection electrode <NUM>'.

The surface roughness of the upper surface of the first connection electrode <NUM> and the second connection electrode <NUM>' may be larger than the surface roughness of the side surface of the first connection electrode <NUM> and the second connection electrode <NUM>'.

In the display device 1_2, the anode electrode <NUM> and the second connection electrode <NUM>' may be in direct contact with each other without a separate contact hole, and the second connection electrode <NUM>' and the first connection electrode <NUM> may be in direct contact with each other without a separate contact hole. Accordingly, the thickness of the display device 1_2 may be reduced by a size of a contact hole as described above, and thus the flexibility of the display device 1_2 can be increased due to the reduction in thickness. It may also be possible to realize a high resolution of the display device 1_2 by omitting the contact pad region and to simplify the manufacturing process, as described similarly above with respect to the discussed embodiments.

A method of manufacturing a display device according to an embodiment is provided below with respect to, for example, the display device of <FIG>.

<FIG> are schematic cross-sectional views showing the steps of a method of manufacturing a display device.

Referring to <FIG>, the method of manufacturing a display device according to an embodiment includes forming, on a substrate <NUM>, a buffer layer <NUM>, a semiconductor layer 105_1 and 105_2, a first insulating layer <NUM>, a first gate conductive layer 110_1 and 110_2, a second insulating layer <NUM>, a second gate conductive layer <NUM>, a third insulating layer <NUM>, a first source/drain conductive layer <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>, a fourth insulating layer <NUM>, and a second source/drain conductive layer <NUM>.

Specifically, the buffer layer <NUM> may be formed of a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a multilayer thereof. The buffer layer <NUM> may be formed by chemical vapor deposition.

A semiconductor pattern 105_1 and a second semiconductor pattern 105_2 may be formed by depositing a semiconductor film on one surface of the buffer layer <NUM> and then patterning the semiconductor film by an etching process using a photoresist pattern.

The first insulating layer <NUM> may be formed of a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a multilayer film thereof on the semiconductor layer 105_1 and 105_2. The first insulating layer <NUM> may be formed by chemical vapor deposition.

A first gate conductive pattern 110_1 and a second gate conductive pattern 110_2 may be formed by depositing a first gate conductive film on the first insulating layer <NUM> and then patterning the first gate conductive film.

The second insulating layer <NUM> may be formed of a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a multilayer film thereof on the first gate conductive layer 110_1 and 110_2. The second insulating layer <NUM> may be formed by chemical vapor deposition.

A third gate conductive pattern <NUM> may be formed by depositing a second gate conductive film on one surface of the second insulating layer <NUM> and then patterning the second gate conductive film.

The third insulating layer <NUM> may be formed of a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a multilayer film thereof on the second gate conductive layer <NUM>. The third insulating layer <NUM> may be formed by chemical vapor deposition.

A first source electrode <NUM>, a first drain electrode <NUM>, a second source electrode <NUM>, a second drain electrode <NUM>, a data wiring <NUM> and a first power supply wiring <NUM> may be formed by depositing a first source/drain conductive film on one surface of the third insulating layer <NUM> and then patterning the first source/drain conductive film.

The fourth insulating layer <NUM> may be formed of a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a multilayer film thereof on the first source/drain conductive layer <NUM>. The fourth insulating layer <NUM> may be formed by chemical vapor deposition.

A first connection electrode <NUM> may be formed by depositing a second source/drain conductive film on one surface of the fourth insulating layer <NUM> and then patterning the second source/drain conductive film.

Referring to <FIG>, a fifth insulating film 175_1 may be formed on the first source/drain conductive layer <NUM>. The fifth insulating film 175_1 may be formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin and the like.

Referring to <FIG>, the surface of the first connection electrode <NUM> and the fifth insulating film 175_1 may be planarized by a chemical mechanical polishing (CMP) process to form a fifth insulating layer <NUM>. Since a difference in leveling between the first connection electrode <NUM> and the fifth insulating layer <NUM> can be removed by the polishing process, it may be possible to prevent reflection of external light due to the difference, thereby improving the display quality of an image to be displayed.

Referring to <FIG>, an anode electrode <NUM> is formed on the fifth insulating layer <NUM>. The anode electrode <NUM> may be formed of a metal material, having high reflectivity, such as a stacked structure (Ti/Al/Ti) of aluminum (Al) and titanium (Ti), a stacked structure (ITO/Al/ITO) of Al and ITO, an APC alloy, a stacked structure (ITO/APC/ITO) of an APC alloy and ITO, or the like.

Since the anode electrode <NUM> may be in direct contact with the first connection electrode <NUM>, a separate contact hole forming process may be omitted. Therefore, a number of masks otherwise associated with providing a contact hole to enable contact between the first connection electrode <NUM> and the anode electrode <NUM> may be reduced. Thus, a cost and complexity of a manufacturing process may likewise be reduced.

Since the anode electrode <NUM> may be deposited on the planarized surface of the first connection electrode <NUM> and the fifth insulating layer <NUM>, the anode electrode <NUM> may be formed with a uniform thickness, thereby further improving the display quality of an image to be displayed.

Referring to <FIG>, a pixel defining layer <NUM>, an organic light emitting layer EL and a cathode electrode <NUM> may be formed on the anode electrode <NUM> to complete a display device such as that shown in <FIG>.

The pixel defining layer <NUM> may be formed so as to partially cover the anode electrode <NUM>, and thus to partition the pixels PX. The pixel defining layer <NUM> may be formed by forming an organic layer containing at least one organic material selected from the group consisting of benzocyclobutene (BCB), polyimide (PI), polyamide (PA), acrylic resin and phenol resin, and then patterning the organic layer through an exposure and development process.

The cathode electrode <NUM> may be formed of a transparent conductive material (TCO) such as ITO or IZO that can transmit light or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag.

Claim 1:
A display device (<NUM>) comprising:
a substrate (<NUM>);
a first conductive layer (<NUM>) disposed on the substrate (<NUM>);
a first insulating layer (<NUM>) disposed on the first conductive layer (<NUM>),
the first insulating layer (<NUM>) including a contact hole exposing the first conductive layer (<NUM>);
a second conductive layer (<NUM>) disposed on the first insulating layer (<NUM>) and electrically connected to the first conductive layer (<NUM>) through the contact hole;
a second insulating layer (<NUM>) disposed on the first insulating layer (<NUM>) and on the same layer as at least a portion of the second conductive layer (<NUM>);
a first electrode (<NUM>) disposed on the second insulating layer (<NUM>) and the second conductive layer (<NUM>),
the first electrode (<NUM>) being electrically connected to the second conductive layer (<NUM>);
a light emitting layer (EL) disposed on the first electrode (<NUM>); and
a second electrode (<NUM>) disposed on the light emitting layer (EL),
wherein an average distance between an upper surface of the second conductive layer (<NUM>) and a surface of the substrate (<NUM>) is substantially equal to an average distance between an upper surface of the second insulating layer (<NUM>) and the surface of the substrate (<NUM>);
wherein
a portion of a lower surface of the second conductive layer (<NUM>) is disposed on an upper surface of the first insulating layer (<NUM>), and
first electrode (<NUM>) and the light emitting layer (EL) are formed flat with a uniform thickness, characterized in that
the second insulating layer (<NUM>) overlaps the upper surface of the second conductive layer (<NUM>) at a boundary area therebetween.