Patent Description:
Integrated circuits frequently generate undesired heat in some active components. It is sometimes desired to remove the heat through a heat sink or other passive structure. It is sometimes desired to divert the heat from thermally sensitive components in the integrated circuit. Managing excess heat in integrated circuits has become increasingly problematic. <CIT> discloses thermal management structures in microelectronic devices.

According to the invention, there is provided an integrated circuit according to claim <NUM> and a method of forming an integrated circuit according to claim <NUM>. Additional aspects are specified in the dependent claims.

In described examples, an integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region has a plurality of interconnect levels. The integrated circuit includes a thermal routing structure in the interconnect region. The thermal routing structure extends over a portion, but not all, of the integrated circuit in the interconnect region. The thermal routing structure includes a cohered nanoparticle film in which adjacent nanoparticles cohere to each other. The thermal routing structure has a thermal conductivity higher than dielectric material touching the thermal routing structure. The cohered nanoparticle film is formed by a method which includes an additive process.

The drawings are not drawn to scale. Example embodiments are not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, some illustrated acts or events are optional.

This description may use terms such as "top," "bottom," "front," "back," "over," "above," "under," "below," and such. These terms should not be construed as limiting the position or orientation of a structure or element, but provide spatial relationship between structures or elements.

In this description, the term "instant top surface" of an integrated circuit refers to the top surface of the integrated circuit, which exists at the particular step being described. The instant top surface may change from step to step in the formation of the integrated circuit.

In this description, the term "lateral" refers to a direction parallel to a plane of an instant top surface of the integrated circuit, and the term "vertical" refers to a direction perpendicular to the plane of the instant top surface of the integrated circuit.

<FIG> and <FIG> are cross sections of an example integrated circuit containing a thermal routing structure according to an embodiment. Referring to <FIG>, the integrated circuit <NUM> includes a substrate <NUM> including a semiconductor material <NUM> such as silicon, silicon germanium or silicon carbide. Alternatively, the semiconductor material <NUM> may be a type III-V semiconductor such as gallium nitride or gallium arsenide. Other semiconductor materials are within the scope of this example. The integrated circuit <NUM> further includes an interconnect region <NUM> disposed above the substrate <NUM>. Heat-generating components <NUM> of the integrated circuit <NUM>, depicted in <FIG> as metal oxide semiconductor (MOS) transistors, are disposed in the substrate <NUM>, possibly extending into the interconnect region <NUM>, proximate to a boundary <NUM> between the substrate <NUM> and the interconnect region <NUM>. Other manifestations of the heat-generating components <NUM>, such as bipolar junction transistors, junction field effect transistors (JFETs), resistors, and silicon controlled rectifiers (SCRs) are within the scope of this example. In this example, the integrated circuit <NUM> may also include thermally sensitive components <NUM>, depicted in <FIG> as MOS transistors. Other manifestations of the thermally sensitive components <NUM> are within the scope of this example. The components <NUM> and <NUM> may be laterally separated by field oxide <NUM> at the boundary <NUM> between the substrate <NUM> and the interconnect region <NUM>. For example, the field oxide <NUM> may have a shallow trench isolation (STI) structure as depicted in <FIG>, or may have a localized oxidation of silicon (LOCOS) structure.

The interconnect region <NUM> may include contacts <NUM>, interconnects <NUM> and vias <NUM> disposed in a dielectric layer stack <NUM>. The contacts <NUM> make electrical connections to the heat-generating components <NUM> and the thermally sensitive components <NUM>. The interconnects <NUM> are disposed in a plurality of interconnect levels. The interconnects <NUM> in a first interconnect level make electrical connections to the contacts <NUM>. The vias <NUM> are disposed between successive interconnect levels and make electrical connections to the interconnects. A top surface <NUM> of the interconnect region <NUM> is located at a surface of the interconnect region <NUM> opposite to the boundary <NUM> between the substrate <NUM> and the interconnect region <NUM>. The interconnects <NUM> may include aluminum interconnects, damascene copper interconnects, and/or plated copper interconnects. An aluminum interconnect may include an aluminum layer with a few percent silicon, titanium, and/or copper, possibly on an adhesion layer including titanium, and possibly with an anti-reflection layer of titanium nitride on the aluminum layer. A damascene copper interconnect may include copper on a barrier layer of tantalum and/or tantalum nitride, disposed in a trench in the dielectric layer stack <NUM>. A plated copper interconnect may include an adhesion layer at a bottom of the interconnect, and may have a barrier layer disposed on the sides of the interconnect. Bond pad structures <NUM> may be disposed over the top surface <NUM> of the interconnect region <NUM>, and may be electrically coupled to the interconnects <NUM>. A protective overcoat <NUM> may be disposed over the top surface <NUM> of the interconnect region <NUM>. The protective overcoat <NUM> may include one or more layers of dielectric material, such as silicon dioxide, silicon nitride, silicon oxide nitride, and/or polyimide.

A thermal routing structure <NUM> is disposed in the interconnect region <NUM>, extending over a portion, but not all, of the integrated circuit <NUM> in the interconnect region <NUM>. The thermal routing structure <NUM> has a higher thermal conductivity than dielectric material in the interconnect region <NUM> that touches the thermal routing structure <NUM>. Thermal conductivity is a property of a material, and may be expressed in units of watts / meter °C. The thermal routing structure <NUM> includes a cohered nanoparticle film <NUM> including primarily nanoparticles <NUM>, shown in more detail in <FIG>. Adjacent nanoparticles <NUM> cohere to each other. There may be inorganic functional molecules, such as silane-based molecules including silicon and oxygen, on surfaces of the nanoparticles <NUM>. The thermal routing structure <NUM> is substantially free of an organic binder material such as adhesive or polymer. The thermal routing structure <NUM> may extend from an area over the heat-generating components <NUM> to a heat removal region <NUM> of the integrated circuit <NUM>, as shown in <FIG>. The thermal routing structure <NUM> may be located outside an area over the thermally sensitive components <NUM>, as shown in <FIG>, thus configured to advantageously divert heat from the heat-generating components <NUM> away from the thermally sensitive components <NUM> during operation of the integrated circuit <NUM>.

In a version of this example as depicted in <FIG> and <FIG>, thermal routing structure <NUM> may be electrically non-conductive, and examples of the nanoparticles <NUM> may include nanoparticles of aluminum oxide, diamond, hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The thermal routing structure <NUM> may touch the contacts <NUM>, the interconnects <NUM>, and/or the vias <NUM> without risking undesired electrical shunts, enabling more complete coverage of the area over the heat-generating components <NUM> and in the heat removal region <NUM>, to advantageously collect more heat from the heat-generating components <NUM>, and more efficiently deliver the heat to the heat removal region <NUM>.

In another version of this example, the thermal routing structure <NUM> may be electrically conductive. In such a version, examples of the nanoparticles <NUM> may include nanoparticles of metal, graphene, graphene embedded in metal, graphite, graphitic carbon, and/or carbon nanotubes. Electrically conductive versions of the thermal routing structure <NUM> may be separated from the contacts <NUM>, the interconnects <NUM>, and the vias <NUM>.

In a further version of this example, the nanoparticles <NUM> may include nanoparticles that include metal, and the thermal routing structure <NUM> may include a layer of graphitic material on the cohered nanoparticle film <NUM>. In such a version, examples of the nanoparticles <NUM> may include nanoparticles of copper, nickel, palladium, platinum, iridium, rhodium, cerium, osmium, molybdenum, and/or gold. In such a version, the thermal routing structure <NUM> is electrically conductive, and hence may be separated from the contacts <NUM>, the interconnects <NUM>, and the vias <NUM>.

An optional planarization layer <NUM> may be disposed laterally adjacent to the thermal routing structure <NUM> to provide a substantially level surface for subsequent layers of the dielectric layer stack <NUM> and subsequent interconnect levels. The planarization layer <NUM> may have a thickness comparable to a thickness of the thermal routing structure <NUM>. The planarization layer <NUM> may have a thermal conductivity comparable to a thermal conductivity of the dielectric layer stack <NUM>, which is significantly less than the thermal conductivity of the thermal routing structure <NUM>. The planarization layer <NUM> may include dielectric materials such as silicon dioxide and may have a granular structure.

<FIG> depict an example method of forming an integrated circuit with a thermal routing structure according to an embodiment. Referring to <FIG>, the integrated circuit <NUM> is formed on a substrate <NUM> which includes a semiconductor material <NUM>. For example, the substrate <NUM> may be a semiconductor wafer. The semiconductor material <NUM> may be a type IV semiconductor such as silicon, silicon germanium or silicon carbide. Alternatively, the semiconductor material <NUM> may be a type III-V semiconductor such as gallium nitride or gallium arsenide. Other semiconductor materials are within the scope of this example.

Components are formed in the semiconductor material <NUM>, such as heat-generating components <NUM> and thermally sensitive components <NUM>. The components may include MOS transistors, bipolar junction transistors, JFETs, resistors, SCRs, diodes and/or other components. Field oxide <NUM> may be formed in the substrate <NUM> to laterally separate the components. The field oxide <NUM> may be formed by an STI process or alternatively by a LOCOS process.

An interconnect region <NUM> is formed over the substrate <NUM>. <FIG> shows the interconnect region <NUM> at a stage partway through completion. The interconnect region <NUM> may be formed as a series of dielectric layers to form a dielectric layer stack <NUM>, with interconnect elements formed in each of the dielectric layers. A pre-metal dielectric (PMD) layer of the dielectric layer stack <NUM> may be formed directly over the substrate <NUM>, and contacts <NUM> may be subsequently formed through the PMD layer to make electrical connections to the components, including the heat-generating components <NUM> and the thermally sensitive components <NUM>. A first intra-metal dielectric (IMD) layer is formed as part of the dielectric layer stack <NUM>. Interconnects <NUM> in a first interconnect level in the first IMD layer are formed over the PMD layer and the contacts <NUM>. The interconnects <NUM> in the first interconnect level make electrical connections to the contacts <NUM>. A portion of a first inter-level dielectric (ILD) layer may be formed over the first IMD layer and first interconnect level, as part of the dielectric layer stack <NUM>.

Forming the thermal routing structure of this example begins with forming a nanoparticle ink film <NUM> of a nanoparticle ink <NUM> by an additive process <NUM> over an instant top surface of the interconnect region <NUM>. In this description, an additive process disposes the nanoparticles in a desired area and does not dispose the nanoparticles outside of the desired area, so a final desired shape of the nanoparticles is produced without needing to remove a portion of the dispensed nanoparticles. Additive processes may enable forming films in desired areas without photolithographic processes and subsequent etch processes, thus advantageously reducing fabrication cost and complexity. The nanoparticle ink <NUM> includes the nanoparticles and a carrier fluid. For example, the nanoparticle ink <NUM> may be an ink, a slurry, or a sol gel. The nanoparticles may include materials described for the nanoparticles <NUM> in reference to <FIG> and <FIG>. There may be inorganic functional molecules, such as molecules including silicon and oxygen, on surfaces of the nanoparticles. A composition of the nanoparticle ink <NUM> may be selected to provide a desired adhesion to the integrated circuit <NUM>. The nanoparticle ink <NUM> is dispensed onto the integrated circuit <NUM> in an area for the subsequently-formed thermal routing structure, and is not dispensed over the entire instant top surface of the interconnect region <NUM>. One or more layers of a dielectric isolation layer may optionally be formed on the instant top surface before forming the nanoparticle ink film <NUM>. For example, the additive process <NUM> may include a discrete droplet process, sometimes referred to as an inkjet process, using a discrete droplet dispensing apparatus <NUM>. The discrete droplet dispensing apparatus <NUM> may be configured so that the integrated circuit <NUM> and the discrete droplet dispensing apparatus <NUM> may be moved laterally with respect to each other to provide a desired dispensing pattern for the nanoparticle ink film <NUM>. The discrete droplet dispensing apparatus <NUM> may have a plurality of dispensing ports which may be independently activated in parallel to provide a desired throughput for the additive process <NUM>. In an alternative version of this example, the additive process <NUM> may include a continuous extrusion process, a direct laser transfer process, an electrostatic deposition process, or an electrochemical deposition process.

In a version of this example in which the thermal routing structure is formed at a higher position in the interconnect region <NUM>, vias may be formed in the first ILD, making electrical connections to the interconnects <NUM> in the first interconnect level. Additional IMD layers with interconnects in sequential interconnect levels, and additional ILD layers with vias, may be formed in the interconnect region <NUM>, before formation of the thermal routing structure.

Referring to <FIG>, the nanoparticle ink film <NUM> of <FIG> is heated by a bake process <NUM> to remove at least a portion of a volatile material from the nanoparticle ink film <NUM> to form a nanoparticle film <NUM> which includes primarily nanoparticles. The first bake process <NUM> may be a radiant heat process, such as using an incandescent light source <NUM> as indicated schematically in <FIG>, or infrared light emitting diodes (IR LEDs). Alternatively, the bake process <NUM> may be a hot plate process which heats the nanoparticle ink film <NUM> through the substrate <NUM>. The bake process <NUM> may be performed in a partial vacuum, or in an ambient with a continuous flow of gas at low pressure, to enhance removal of the volatile material.

Referring to <FIG>, the nanoparticle film <NUM> of <FIG> is heated by a cohesion inducing process <NUM> so that adjacent nanoparticles cohere to each other, to form a cohered nanoparticle film <NUM>. The temperature required for the nanoparticles to cohere to each other is a function of the size of the nanoparticles. Smaller nanoparticles may be heated at lower temperatures than larger nanoparticles to attain a desired cohesion of the nanoparticles. The nanoparticles may be selected to enable cohesion at a temperature compatible with the integrated circuit components and structures. Cohesion may occur by a process that includes a physical mechanism involving diffusion of atoms between the adjacent nanoparticles. Cohesion may also occur by a process that includes a chemical mechanism involving reaction of atoms between the adjacent nanoparticles. The cohesion inducing process <NUM> may include heating by a scanning laser apparatus <NUM> as depicted schematically in <FIG>. The scanning laser apparatus <NUM> may be configured to provide heat to substantially only the nanoparticle film <NUM> and not provide heat to portions of the integrated circuit <NUM> laterally adjacent to the nanoparticle film <NUM>, advantageously reducing a total heat load on the components <NUM> and <NUM>.

In one variation of this example, the cohesion inducing process <NUM> may include a flash heating process, which applies radiant energy for <NUM> microsecond to <NUM> microseconds. In another variation, the cohesion inducing process <NUM> may include a spike heating process, which applies radiant energy for <NUM> milliseconds to <NUM> seconds. In an alternative version of this example, the bake process <NUM> described in reference to <FIG> may be combined with the cohesion inducing process <NUM>, wherein thermal power applied to the nanoparticle film <NUM> of <FIG> is ramped to first remove the volatile material, followed by inducing cohesion of the nanoparticles. Other methods of inducing cohesion between the nanoparticles are within the scope of this example.

The cohered nanoparticle film <NUM> may provide the thermal routing structure <NUM>. Alternatively, the steps described in reference to <FIG> may be repeated to form a second cohered nanoparticle film, that in combination with the cohered nanoparticle film <NUM>, provides the thermal routing structure <NUM> with a desired thickness. Some parameters of the process steps, such as bake time and temperature, may be adjusted to accommodate more than one cohered nanoparticle film in the thermal routing structure <NUM>.

Referring to <FIG>, a planarization layer, similar to the planarization layer <NUM> described in reference to <FIG>, may optionally be formed that is laterally adjacent to the thermal routing structure <NUM>, to provide a substantially level surface which facilitates formation of subsequent layers of the interconnect region <NUM>. The planarization layer may be formed by any of various methods; this example discloses forming the planarization layer using an additive process. Formation of the planarization layer begins with forming a slurry layer <NUM> by an additive process <NUM> on the instant top surface of the interconnect region <NUM> laterally adjacent to the thermal routing structure <NUM>. The slurry layer <NUM> may include dielectric grains dispersed in an aqueous fluid or possibly an organic binder precursor fluid. The additive process <NUM> may use a continuous dispensing apparatus <NUM> as depicted schematically in <FIG>, or may use another additive apparatus such as a discrete droplet dispenser. The slurry layer <NUM> may be dispensed onto substantially all of the instant top surface of the interconnect region <NUM> that is not covered by the thermal routing structure <NUM>.

Referring to <FIG>, the slurry layer <NUM> is heated by a slurry bake process <NUM> to remove at least a portion of a volatile material from the slurry layer <NUM>. The slurry bake process <NUM> may be a radiant heat process using an incandescent source <NUM>, as indicated in <FIG>, or may be a hot plate bake process, a forced air bake process, or a combination thereof.

Referring to <FIG>, the slurry layer <NUM> of <FIG> is cured to form the planarization layer <NUM>. The slurry layer <NUM> may be cured by a heat process <NUM> using a heat lamp <NUM>, as indicated in <FIG>, or by exposure to ultraviolet radiation to polymerize an organic precursor in the slurry layer <NUM>.

Formation of the interconnect region <NUM> continues with formation of dielectric layers of the dielectric layer stack <NUM> and formation of vias. The vias may be formed through the thermal routing structure <NUM>, and through the planarization layer <NUM> if present, with appropriate adjustments to etch process for forming via holes.

<FIG> depict another example method of forming an integrated circuit with a thermal routing structure according to an embodiment. Referring to <FIG>, the integrated circuit <NUM> is formed on a substrate <NUM> which includes a semiconductor material <NUM>. Components are formed in the semiconductor material <NUM>, proximate to a top surface <NUM> of the substrate <NUM>. The components of this example may include a first set of components <NUM> and a second set of components <NUM>, wherein the first set of components <NUM> is spatially separated from the second set of components <NUM>, and wherein the first set of components <NUM> and the second set of components <NUM> benefit from sharing a same thermal environment. The first set of components <NUM> and the second set of components <NUM> may be matching components of an analog circuit. Matching components are designed to have substantially equal performance parameters, such as drive current and threshold. Because these performance parameters are affected by temperature, reducing a temperature difference between matching components may advantageously reduce differences in the performance parameters. The components <NUM> and <NUM> may include MOS transistors, bipolar junction transistors, JFETs, resistors, SCRs, diodes and/or other components. Field oxide <NUM> may be formed in the substrate <NUM> to laterally separate the components. The field oxide <NUM> may be formed by an STI process or alternatively by a LOCOS process.

An interconnect region <NUM> is formed over the substrate <NUM>. <FIG> shows the interconnect region <NUM> at a stage partway through completion. The interconnect region <NUM> may be formed as a series of dielectric layers, such as a PMD layer, and alternating IMD layers and ILD layers, to form a dielectric layer stack <NUM>, with interconnect elements such as contacts <NUM>, interconnects <NUM>, and vias <NUM> formed in the dielectric layers.

Forming the thermal routing structure of this example may begin with optionally forming a dielectric isolation layer <NUM> over an instant top surface of the interconnect region <NUM>. The dielectric isolation layer <NUM> may electrically isolate the interconnects <NUM> from the subsequently formed thermal routing structure. For example, the dielectric isolation layer <NUM> may include silicon dioxide-based dielectric material. The dielectric isolation layer <NUM> may be formed by a plasma enhanced chemical vapor deposition (PECVD) process using tetraethyl orthosilicate (TEOS), or spin coating the integrated circuit <NUM> with hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ) followed by baking and annealing. The dielectric isolation layer <NUM> may be configured as a blanket layer or may be patterned. In one version of this example, a patterned manifestation of the dielectric isolation layer <NUM> may be formed of electrically non-conductive nanoparticles having a high thermal conductivity, which may advantageously increase an overall thermal conductivity of the thermal routing structure. In an alternative version of this example, in which no interconnects <NUM> are exposed at the instant top surface of the interconnect region, forming the dielectric isolation layer may be omitted.

A nanoparticle ink film <NUM> of a nanoparticle ink <NUM> is formed on an instant top surface of the interconnect region <NUM>. The nanoparticle ink film <NUM> is formed by an additive process <NUM>. In this example, the nanoparticle ink <NUM> may include electrically conductive nanoparticles and a carrier fluid. The nanoparticle ink <NUM> is dispensed onto the integrated circuit <NUM> in an area for the subsequently-formed thermal routing structure, and is not dispensed over the entire instant top surface of the interconnect region <NUM>. The nanoparticle ink <NUM> may be omitted outside of areas for subsequently formed vias, so as to leave via openings <NUM> in the nanoparticle ink film <NUM>, to avoid the electrically conductive nanoparticles touching the subsequently formed vias. The additive process <NUM> may use a continuous micro-extrusion dispensing apparatus <NUM>, as indicted schematically in <FIG>. The continuous micro-extrusion dispensing apparatus <NUM> may be configured so that the integrated circuit <NUM> and the continuous micro-extrusion dispensing apparatus <NUM> may be moved laterally with respect to each other to provide a desired dispensing pattern for the nanoparticle ink film <NUM>.

Referring to <FIG>, the nanoparticle ink film <NUM> of <FIG> is heated by a bake process <NUM> to remove at least a portion of a volatile material from the nanoparticle ink film <NUM> to form a nanoparticle film <NUM> which includes primarily nanoparticles. The bake process <NUM> may be a hot plate process using a hot plate <NUM> disposed under the substrate <NUM>, as depicted in <FIG>. Alternatively, the bake process <NUM> may be a radiant heat process, as described in reference to <FIG>. The bake process <NUM> may be performed in a partial vacuum, or in an ambient with a continuous flow of gas at low pressure, to enhance removal of the volatile material.

Referring to <FIG>, the nanoparticle film <NUM> of <FIG> is heated by a cohesion inducing process <NUM> so that adjacent nanoparticles cohere to each other, to form a cohered nanoparticle film <NUM>. The cohesion inducing process <NUM> may include a flash heating process using a flash lamp <NUM>, as depicted schematically in <FIG>. Other methods of inducing cohesion between the nanoparticles are within the scope of this example. The cohered nanoparticle film <NUM> may provide substantially all of the thermal routing structure <NUM>. Alternatively, additional cohered nanoparticle films may be formed to combine with the cohered nanoparticle film <NUM> to provide the thermal routing structure <NUM>.

<FIG> and <FIG> are cross sections of another example integrated circuit containing a thermal routing structure according to an embodiment. Referring to <FIG>, the integrated circuit <NUM> includes a substrate <NUM> including a semiconductor material <NUM>. The integrated circuit <NUM> further includes an interconnect region <NUM> disposed above the substrate <NUM>. In this example, a first set of components <NUM> and a second set of components <NUM> are disposed in the substrate <NUM> and the interconnect region <NUM>, proximate to a boundary <NUM> between the substrate <NUM> and the interconnect region <NUM>. In this example, the first set of components <NUM> and the second set of components <NUM> may be matching components whose performance benefits from having similar thermal environments. The integrated circuit <NUM> may further include thermally sensitive components <NUM> whose performance improves as a temperature decreases. The components <NUM>, <NUM> and <NUM> are depicted in <FIG> as MOS transistors, but other manifestations (such as bipolar junction transistors, JFETs, resistors, and SCRs) are within the scope of this example. The components <NUM>, <NUM> and <NUM> may be laterally separated by field oxide <NUM> at the boundary <NUM> between the substrate <NUM> and the interconnect region <NUM>.

The interconnect region <NUM> may include contacts <NUM>, interconnects <NUM> and vias <NUM> disposed in a dielectric layer stack <NUM>. A top surface <NUM> of the interconnect region <NUM> is located at a surface of the interconnect region <NUM> opposite to the boundary <NUM> between the substrate <NUM> and the interconnect region <NUM>. Bond pad structures <NUM> may be disposed over the top surface <NUM> of the interconnect region <NUM>, and are electrically coupled to the interconnects <NUM>. A protective overcoat <NUM> may be disposed over the top surface <NUM> of the interconnect region <NUM>. The bond pad structures <NUM> may extend through the protective overcoat <NUM>.

A thermal routing structure <NUM> is disposed in the interconnect region <NUM>, extending over a portion, but not all, of the integrated circuit <NUM> in the interconnect region <NUM>. In this example, the thermal routing structure <NUM> includes a cohered nanoparticle film <NUM> including nanoparticles <NUM> which include metal, and a layer of graphitic material <NUM> disposed on the cohered nanoparticle film <NUM>, shown in detail in <FIG>. For example, the nanoparticles <NUM> may include copper, nickel, palladium, platinum, iridium, rhodium, cerium, osmium, molybdenum, and/or gold. The layer of graphitic material <NUM> may include graphite, graphitic carbon, graphene, carbon nanotubes or the like.

A dielectric isolation layer <NUM> may optionally be disposed under the thermal routing structure <NUM>. The dielectric isolation layer <NUM> may electrically isolate the layer of cohered nanoparticle film <NUM> from underlying interconnects <NUM>. In this example, the thermal routing structure <NUM> may extend over the first set of components <NUM> and the second set of components <NUM>, and may extend away the thermally sensitive components <NUM>, as shown in <FIG>. Thus, the thermal routing structure <NUM> may provide a more closely matched thermal environment for the first set of components <NUM> and the second set of components <NUM> and thereby improve their performance, while advantageously diverting heat from the first set of components <NUM> and the second set of components <NUM> away from the thermally sensitive components <NUM>.

<FIG> depict another example method of forming an integrated circuit with a thermal routing structure according to an embodiment. Referring to <FIG>, the integrated circuit <NUM> is formed on a substrate <NUM> which includes a semiconductor material <NUM>. Components (such as heat-generating components <NUM>, thermally sensitive components <NUM> and matching components <NUM>) are formed in the semiconductor material <NUM> proximate to a top surface <NUM> of the substrate <NUM>. The top surface <NUM> of the substrate <NUM> is also a boundary between the substrate <NUM> and the interconnect region <NUM>. Field oxide <NUM> may be formed in the substrate <NUM> to laterally separate the components <NUM>, <NUM> and <NUM>. An interconnect region <NUM> is formed over the substrate <NUM>. The interconnect region <NUM> may be formed to have a dielectric layer stack <NUM>, with interconnect elements such as contacts <NUM>, interconnects <NUM>, and vias <NUM> formed in the dielectric layer stack <NUM>.

A dielectric isolation layer, not shown in <FIG>, may optionally be formed in an area for the thermal routing structure. The dielectric isolation layer may be formed by any of various methods, such as described in reference to the dielectric isolation layer <NUM> of <FIG>. A nanoparticle ink film <NUM> containing nanoparticles which include metal is formed by an additive process <NUM> over an instant top surface of the interconnect region <NUM>, on the dielectric isolation layer, if present. The nanoparticles may include the metals described in reference to <FIG> and <FIG>, or other metal suitable as a catalyst for subsequent growth of graphitic material. The nanoparticle ink film <NUM> is formed in an area for the subsequently-formed thermal routing structure, and is not formed over an entire instant top surface of the interconnect region <NUM>. The additive process <NUM> may include a direct laser transfer process which uses a pulsed laser <NUM> to transfer small pieces of nanoparticle ink <NUM> of a source layer <NUM> containing the nanoparticles to the integrated circuit <NUM>, as depicted in <FIG>. The source layer <NUM> is attached to a backing layer <NUM>. The combined source layer <NUM> and backing layer <NUM> are sometimes referred to as a ribbon. The pulsed laser <NUM>, the source layer <NUM> and backing layer <NUM>, and the integrated circuit <NUM> may be moved relative to each other to form the nanoparticle ink film <NUM> in a desired area. Other methods of forming the nanoparticle ink film <NUM> are within the scope of this example.

Referring to <FIG>, the nanoparticle ink film <NUM> of <FIG> may be heated by a bake process <NUM> to remove at least a portion of a volatile material from the nanoparticle ink film <NUM> to form a nanoparticle film <NUM> which includes primarily nanoparticles. The bake process <NUM> may be a radiant heat process using IR LEDs <NUM> as depicted schematically in <FIG>. Using the IR LEDs <NUM> may enable application of the radiant heat to substantially only an area containing the nanoparticle ink film <NUM> while not applying the radiant heat to areas of the integrated circuit <NUM> outside of the nanoparticle ink film <NUM>, advantageously reducing a heat load on the components <NUM>, <NUM>, and <NUM>. Alternatively, the bake process <NUM> may include a radiant heat process using an incandescent source, or may include a hot plate process.

Referring to <FIG>, the nanoparticle film <NUM> of <FIG> is heated by a cohesion inducing process <NUM> so that adjacent nanoparticles cohere to each other, to form a cohered nanoparticle film <NUM>. The cohesion inducing process <NUM> may include a spike heating process using an incandescent lamp <NUM>, as depicted schematically in <FIG>. The spike heating process heats the nanoparticle film <NUM> for a time duration, such as for <NUM> millisecond to <NUM> milliseconds, to advantageously limit heating of the components <NUM>, <NUM> and <NUM>. Other methods of inducing cohesion between the nanoparticles are within the scope of this example.

Referring to <FIG>, a layer of graphitic material <NUM> is selectively formed on the cohered nanoparticle film <NUM> by a graphitic material PECVD process. In the graphitic material PECVD process, the substrate <NUM> is disposed on a wafer chuck <NUM> and is heated by the wafer chuck <NUM>, such as to a temperature of <NUM> to <NUM>. A carbon-containing reagent gas, denoted in <FIG> as "CARBON REAGENT GAS" is flowed over the integrated circuit <NUM> and radio frequency (RF) power, denoted in <FIG> as "RF POWER" is applied to the carbon-containing reagent gas to generate carbon radicals above the integrated circuit <NUM>. The carbon-containing reagent gas may include methane, straight chain alkanes such as ethane, propane and/or butane, alcohols such as ethanol, and/or cyclic hydrocarbons such as cyclobutane or benzene. Additional gases, such as hydrogen, argon and/or oxygen, may be flowed over the the integrated circuit <NUM>. The nanoparticles in the cohered nanoparticle film <NUM> catalyze the carbon radicals to react to form the graphitic material <NUM>, so that a first layer of the layer of graphitic material <NUM> is formed selectively on the cohered nanoparticle film <NUM>. Subsequent layers of the graphitic material <NUM> are formed selectively on the previously formed layers of graphitic material <NUM>, so that the layer of graphitic material <NUM> is formed selectively on the cohered nanoparticle film <NUM>, and the graphitic material <NUM> is not formed on the integrated circuit <NUM> outside of the cohered nanoparticle film <NUM>. The combined cohered nanoparticle film <NUM> and the layer of graphitic material <NUM> provide the thermal routing structure <NUM>.

<FIG> is a cross section of an example integrated circuit which includes a combined thermal routing structure according to an embodiment. The integrated circuit <NUM> includes a substrate <NUM> including a semiconductor material <NUM>. The integrated circuit <NUM> further includes an interconnect region <NUM> disposed above the substrate <NUM>. Heat-generating components <NUM> are disposed in the substrate <NUM> and the interconnect region <NUM>, proximate to a boundary <NUM> between the substrate <NUM> and the interconnect region <NUM>. For example, the components <NUM> may be MOS transistors, bipolar junction transistors, JFETs, resistors, and/or SCRs. The components <NUM> may be laterally separated by field oxide <NUM> at the boundary <NUM> between the substrate <NUM> and the interconnect region <NUM>. The interconnect region <NUM> may include contacts <NUM>, interconnects <NUM> and vias <NUM> disposed in a dielectric layer stack <NUM>. Some of the interconnects <NUM> are disposed in a top interconnect level <NUM> which is located proximate to a top surface <NUM> of the interconnect region <NUM>. The top surface <NUM> of the interconnect region <NUM> is located opposite from the boundary <NUM> between the substrate <NUM> and the interconnect region <NUM>. Bond pad structures <NUM> are disposed over the top surface <NUM> of the interconnect region <NUM>, and are electrically coupled to the interconnects <NUM> in the top interconnect level <NUM>. A protective overcoat <NUM> is disposed over the top surface <NUM> of the interconnect region <NUM>.

In this example, the integrated circuit <NUM> is assembled using wire bonds <NUM> on some of the bond pad structures <NUM>. The integrated circuit <NUM> is packaged by encapsulation in an encapsulation material <NUM>. The encapsulation material <NUM>, such as an epoxy, is disposed over the protective overcoat <NUM> and the bond pad structures <NUM>.

The integrated circuit <NUM> of this example includes the combined thermal routing structure <NUM>, which extends from inside the substrate <NUM> through the interconnect region <NUM>, and through the organic polymer encapsulation material <NUM>. The combined thermal routing structure <NUM> includes a thermal routing structure <NUM> disposed in the interconnect region <NUM> according to any of the examples herein. The combined thermal routing structure <NUM> may conduct heat generated by the components <NUM> to a heat removal apparatus, such as a heat sink, located outside of a package containing the integrated circuit <NUM>, which may advantageously reduce an operating temperature of the components <NUM>.

The combined thermal routing structure <NUM> may include deep trench thermal routing structures <NUM> disposed in the substrate <NUM> and extending to the boundary <NUM> between the substrate <NUM> and the interconnect region <NUM>. The deep trench thermal routing structures <NUM> may surround a portion of the components <NUM> and may be connected to each other at locations out of the plane of <FIG>. The deep trench thermal routing structures <NUM> may have structures and may be formed, such as described in Patent Application No. <CIT>.

The combined thermal routing structure <NUM> may include high thermal conductivity vias <NUM> disposed in the interconnect region <NUM>. The high thermal conductivity vias <NUM> may surround a portion of the components <NUM> and may be connected to each other at locations out of the plane of <FIG>. The high thermal conductivity vias <NUM> may have structures and may be formed, such as described in Patent Application No. <CIT>.

The combined thermal routing structure <NUM> may include a top level thermal conductivity structure <NUM> disposed above the top interconnect level <NUM>. The top level thermal conductivity structure <NUM> may have a structure and may be formed, such as described in Patent Application No. <CIT>.

The combined thermal routing structure <NUM> may include high thermal conductivity through-package conduits <NUM> disposed through the encapsulation material <NUM> to the integrated circuit <NUM>. The high thermal conductivity through-package conduits <NUM> may have structures and may be formed, such as described in Patent Application No. <CIT>.

The integrated circuit <NUM> may further include graphitic material vias <NUM> which are electrically coupled to the components <NUM>. The graphitic material vias <NUM> may conduct heat generated by the components <NUM> away from the substrate, possibly to the combined thermal routing structure <NUM>, which may advantageously reduce an operating temperature of the components <NUM>. The graphitic material vias <NUM> may have structures and may be formed, such as described in Patent Application No. <CIT>.

Claim 1:
An integrated circuit, comprising:
a substrate comprising a semiconductor material;
an interconnect region disposed above the substrate, comprising
a dielectric layer stack comprising dielectric material;
contacts disposed in the dielectric layer stack;
interconnects disposed in the dielectric layer stack; and
vias disposed in the dielectric layer stack;
a heat generating component disposed in the substrate and the interconnect region, proximate to a boundary between the substrate and the interconnect region; and
a thermal routing structure disposed in the interconnect region, the thermal routing structure thermally coupled to the heat-generating component, the thermal routing structure includes a cohered nanoparticle film comprising nanoparticles substantially free of an organic binder material, a graphitic material adjacent to a portion of the cohered nanoparticle film, and wherein a thermal conductivity of the thermal routing structure is higher than a thermal conductivity of dielectric material contacting the thermal routing structure; and
a dielectric isolation layer adjacent to the thermal routing structure and over a first surface of the interconnect region, the dielectric isolation layer comprising electrically non-conductive nanoparticles having a high thermal conductivity, and the dielectric isolation layer electrically isolating the interconnects from the thermal routing structure.