Patent Description:
Quad Flat No-leads (QFN) packages are commonly used for discrete devices due to the small footprint and the small package height.

An example of a semiconductor device <NUM> comprising a QFN package is shown in <FIG>. The device <NUM> includes a lead frame <NUM> upon which is mounted a semiconductor substrate <NUM>. A contact <NUM> on a surface of the substrate <NUM> allows an electrical connection to be formed with a first part of the lead frame <NUM> (e.g. by soldering). Another contact <NUM> is located on a surface of the substrate <NUM> opposite the surface on which the contact <NUM> is located. The contact <NUM> is electrically connected to another part of the lead frame using bond wire <NUM>. The device <NUM> also includes an encapsulant <NUM> for protecting the features of the substrate <NUM> and lead frame <NUM>. Parts <NUM> and <NUM> of the lead frame <NUM> are exposed at one side of the package <NUM> (i.e. they are not covered by the encapsulant <NUM>). These parts <NUM> and <NUM> of the lead frame <NUM> provide external electrical connections for the device <NUM>. For instance, the parts <NUM> and <NUM> of the lead frame <NUM> can be mounted on a carrier such as a printed circuit board (e.g. by soldering).

QFN packages have rather low heat capacity and heat conductivity, which can make then unsuitable for devices that dissipate a lot of power (such as like transient voltage suppression (TVS) protection devices). QFN packages can also add to the on-resistance of the device due to the bond wire that is used. Moreover, the thickness of QFN packages cannot be reduced significantly because lead-frame thickness, die thickness and bond wire loop height all add to the total thickness.

Devices such as transient voltage suppression (TVS) protection devices are used for protecting integrated circuits (ICs) against electrical overstress. In use, these devices are connected between an external input and the input of an IC, and can operate to drain unwanted, oftentimes large, currents to ground or another rail so that any internally provided protection of the IC is not overstressed and damaged.

The heat caused by the current within the protection device can limit the robustness of the device. The temperature within the protection device is dependent on factors such as the dissipated power, the thermal capacity of the device and the thermal resistance of the device.

TVS protection devices may include semiconductor diodes. In such a device, a pn junction may be provided near a first surface of a semiconductor substrate. In such devices, the main part of the heat created by the stress current occurs at the pn junction. On the other hand, the surface of the substrate is usually the part of the substrate that is most sensitive to heat (due to the presence of a metal contact on the surface, which can melt if the temperature in the device is too great). A second contact of the diode is usually provided on a second of the substrate. In such devices, heat diffusion from the pn junction to cooler parts of the device is highly asymmetrical because the pn junction is located near one of the surfaces of the substrate.

One kind of package for a semiconductor device involves the use of a clip bond. The clip replaces the bond wire in <FIG>. The bottom of the substrate is soldered or glued to a lead frame finger, and a metal clip is soldered or glued to the top contact of the substrate and to a second lead frame finger. The two lead frame fingers serve as electrical contacts that can be soldered to a carrier such as a printed circuit board (PCB). However, a device using this approach may suffer from limitations associated with heat caused by stress pulses. For instance, the limited thickness of the clip limits its thermal capacity of the clip. The multiple solder or glue points can also limit thermal conduction away from the substrate. Lead frame materials are also not optimized for thermal resistance.

In another kind of package, known as the chip scale package, two contacts may be located on a common surface of the substrate. The substrate can be soldered top-down onto a carrier such as a PCB. The connections between the substrate and the carrier have limited thermal capacity. A further major disadvantage of the CSP is that current flow within the substrate flows in a lateral direction (between the two contacts on the top side). This can lead to current crowding and local heating, which can strongly reduce the robustness of the device.

Semiconductor devices comprising semiconductor substrates in contact with electrically conductive heat sinks are known e.g. from <CIT>,<CIT>, <CIT>, or <CIT>.

The subject-matter of the present invention is defined by the subject-matter of independent claims <NUM> and <NUM>.

The provision of an electrically conductive heat sink, upon a first surface of which the first surface of the substrate is mounted for electrical and thermal conduction, may improve heat dissipation within the device compared to known devices. This may allow the device to handle larger currents, for instance during stress pulses associated with spikes in the current passing through the device. Also, since the heat sink is electrically conductive, it may allow an electrical connection to the first contact to be made. The dual function of the heat sink may allow a compact package to be provided.

The carrier may, for instance, be a printed circuit board (PCB). The second surface of the substrate and the electrically conductive heat sink may both be mountable on the surface of the carrier. This can allow for secure mounting of the device on the carrier, and in some embodiments can also allow the heat sink to form an electrical connection between the surface of the carrier and the first contact of the substrate and the carrier.

In one embodiment, the electrically conductive heat sink includes a first portion that extends substantially parallel to a plane containing the first surface of the substrate, wherein the first portion comprises said first surface of the electrically conductive heat sink. The first portion of the electrically conductive heat sink may thus provide a secure platform for receiving the semiconductor substrate. In some examples, first portion may be dimensioned so as to receive more than one substrate of the kind described herein.

The heat sink also includes a second portion that extends away from the first portion for mounting the electrically conductive heat sink on the surface of the carrier. In some examples, the second portion may extend in a direction substantially perpendicular to the plane parallel to which the first portion extends. The second portion may include one or more contacts for electrically connecting the heat sink to one or more corresponding contacts on the surface of the carrier. As noted above, the electrically conductive heat sink may in some embodiments provide for an electrical connection between the surface of the carrier and the first contact of the substrate and the carrier. The heat sink includes one or more further portions such as the second portion, to allow mounting and/or electrical connection of the heat sink at multiple locations on the surface of the carrier.

In some embodiments, the semiconductor device includes at least one further semiconductor substrate. The or each semiconductor substrate includes a pn-junction diode. Where multiple substrates are provided, the component (such as a pn-junction diode) provided within each semiconductor substrate may be electrically connected in parallel with the component(s) provided within the other substrate(s) for increasing the capacity of the device. Alternatively, the components may be connected in series so as to provide a bidirectional device. Alternatively, the components may be independent and may be connected to different contacts, such creating a multi-pin device, the final schematic defined by the connections on the carrier.

In one embodiment, the device includes a second semiconductor substrate that includes a first contact located on a first surface of the second substrate, and a second contact located on a second surface of the second substrate. The first surface of the second substrate may be mounted on the first surface of the heat sink for electrical and thermal conduction between the heat sink and the substrate via the first contact. The second surface of the second substrate may be mountable on the surface of the carrier. The heat sink may electrically interconnect the first contact of each semiconductor substrate, for current flow between the substrates. The heat sink in embodiments of this kind may be left electrically floating in the sense that it is not connected to an external voltage such as ground. In one such example, the components (e.g. pn-junction diodes) within each semiconductor substrate may be connected in series so as to provide a bidirectional device as noted above.

The electrically conductive heat sink may be coated with an electrically conductive layer. The electrically conductive layer may be NiPdAu. This layer can act as a wetting layer to improve the solderability of the surface of the heat sink.

The electrically conductive heat sink may be metallic. For instance, the electrically conductive heat sink may comprise copper.

In some embodiments, an encapsulant covers the or each semiconductor substrate while leaving the second contact of the or each substrate exposed. The encapsulant may provide protection for the substrate(s) (for example, for the edges of the substrate(s)), while allowing electrical connections to be made to the device using the second contact of the or each substrate. In one arrangement, the device comprises a chip scale package including the heat sink, one or more substrates and the encapsulant.

In some embodiments, solder or an electrically conductive glue is used to attach the first contact of the or each substrate to the first surface of the heat sink.

In some embodiments, the device is mounted on the surface of the carrier.

According to the invention, the substrate includes an active region located adjacent one of the surfaces of the substrate. The active region is a region of the substrate containing a pn junction. In use, the active region of the substrate may be more susceptible to heating, particularly during stress pulses. For purposes of this disclosure, the term "active surface" is used to refer to the surface of the substrate which is closest to the active region of the substrate. For purposes of this disclosure, the surface of the substrate opposite the active surface is referred to the "passive surface". The active and passive surfaces may, for example, be a major surface and a backside of the substrate, respectively.

According to the invention, the first surface is an active surface of the substrate, while the second surface is a passive surface of the substrate. Accordingly, the active surface of the substrate is mounted on the first surface of the heat sink. In this way, the region of the substrate that is more susceptible to heating may be placed closest to the heat sink, which may enhance the ability of the heat sink to protect the device against overheating, particularly during stress pulses.

In some embodiments, the device is a transient voltage suppression (TVS) diode. Problems relating to heat dissipation are known to limit the operation of known kinds of TVS diodes to handle stress pulses. A TVS diode according to an embodiment of this invention may be able to handle larger stress pulses owing to the action of the heat sink to allow heat caused by the stress pulses to be dissipated. The first surface of the substrate in such examples is the active surface (which, in the case of a TVS diode, is the surface closest to the pn junction of the diode). The second surface is a passive surface of the substrate. As noted above, this orientation of the substrate may enhance the ability of the heat sink to protect the TVS diode against overheating during stress pulses.

Certain examples can also include devices such as MOS transistors. In such examples, that are not covered by the present invention, the first surface of the substrate may be the passive surface of the substrate (which in the case of a device including a MOS transistor, is the surface furthest from the channel of the transistor). In devices of this kind, this orientation of the substrate may reduce on-resistance, since the contacts of the transistor may be mounted directly to the carrier, and since no bond wires are required.

It is envisaged that in some examples the second surface may have multiple contacts located thereon. For instance, this may allow a device including a MOS transistor of the kind noted above to be implemented.

According to another aspect of the invention, there is provided a method of making a plurality of semiconductor devices of the kind described above, as defined by claim <NUM>. Inter alia, this method includes providing an electrically conductive member having a first surface. The method also includes providing a plurality of semiconductor substrates, each substrate including a first contact located on a first surface of the substrate, and a second contact located on a second surface of the substrate. The method further includes mounting the first surface of each substrate on the first surface of the electrically conductive member for electrical and thermal conduction between the electrically conductive member and the substrate via the first contact. The method also includes dicing the electrically conductive member to form said plurality of devices. A respective portion of the electrically conductive member in each device forms an electrically conductive heat sink of the device.

In one embodiment, after mounting the first surface of each substrate on the first surface of the electrically conductive member and before dicing the electrically conductive member, the method includes encapsulating the plurality of semiconductor substrates while leaving the second contact of each substrate exposed.

Embodiments of the present invention will be described hereinafter, by way of example only, with reference to the accompanying drawings in which like reference signs relate to like elements and in which:.

Embodiments of the present invention are described in the following with reference to the accompanying drawings.

Embodiments of this invention provide a semiconductor device. The semiconductor device includes an electrically conductive heat sink that has a first surface. The device also includes a semiconductor substrate that has a first surface and a second surface. The second surface of the substrate is typically a surface of the substrate that is on an opposite side of the substrate to the first surface. A first contact is located on the first surface of the substrate and the second contact is located on the second surface of the substrate. Accordingly, embodiments of this invention may incorporate a semiconductor device having two terminals, such as a semiconductor diode, for example, a pn junction diode or more particularly a transient voltage suppression (TVS) protection device.

The first surface of the substrate is mounted on a first surface of the heat sink. The mounting of the substrate on the first surface of the heat sink can allow for good electrical and thermal conduction between the heat sink and the substrate via the first contact. Accordingly, as described in more detail below, the heat sink can allow heat to be dissipated from the substrate.

In some semiconductor devices, such as in a diode based TVS protection devices, heat caused by surge pulses within the device is concentrated at a pn junction of the device. The pn junction in such a device may be located near to the first surface of the substrate (the first surface is an active surface of the device), whereby the mounting of the substrate on the heat sink at the first surface can enhance the ability of the heat sink to conduct heat away from the critical region of the device.

The heat sink can allow heat generated during a stress pulse to be dissipated to a carrier upon which the device may be mounted and/or to the surrounding atmosphere.

The heat sink, which is electrically conductive, also acts as an electrical connection to the substrate via the first contact. The dual role of the heat sink for conducting both heat and current can allow a relatively compact device to be implemented.

The second surface of the substrate can be mountable on a surface of a carrier. The carrier may, for instance, be a printed circuit board (PCB). This can allow the second contact that is provided on the second surface of the substrate to be electrically connected to a corresponding contact that is located on the surface of the carrier. As described in more detail below, the electrically conductive heat sink may also be electrically connectable to a corresponding contact on the surface of the carrier. In other examples, the electrically conductive heat sink can allow contacts to be completed to other features of the device such as one or more other semiconductor substrates (e.g. for forming a bidirectional device as described in relation to <FIG>).

<FIG> shows a semiconductor device. The device <NUM> includes an electrically conductive heat sink <NUM>. The electrically conductive heat sink <NUM> may be metallic. For instance, the electrically conductive heat sink <NUM> may comprise a metal such as copper. As will be described in more detail below, the heat sink <NUM> may be provided with an outer coating.

The device <NUM> also includes a semiconductor substrate <NUM> which may, for example, be a silicon substrate. The semiconductor substrate <NUM> includes a first surface <NUM> and a second surface <NUM>. In this arrangement, the substrate <NUM> includes a semiconductor region <NUM> located adjacent the first surface <NUM>. The semiconductor region <NUM> can form a pn junction at an interface between the semiconductor region <NUM> and the underlying substrate. Accordingly, in this arrangement, the device may comprise a pn junction diode for implementing a diode such as a TVS diode.

In this example, the pn junction at an interface between the semiconductor region <NUM> and the underlying substrate forms an active region of the device. This active region is closer to the first surface <NUM> of the substrate than it is to the second surface <NUM> of the substrate. Accordingly, in this example, the first surface <NUM> is an active surface of the device <NUM>, while the second surface <NUM> is a passive surface of the device.

In this arrangement, a first contact <NUM> is provided on the first surface <NUM> of the substrate <NUM>. The first contact <NUM> can provide a connection to a first side of the pn junction. The device <NUM> can also include a second contact <NUM> that is located on the second surface <NUM> of the substrate <NUM>. The second contact <NUM> can provide a connection to a second side of the pn junction. Accordingly, in this arrangement, the device <NUM> is a two terminal device.

The electrically conductive heat sink <NUM> includes a first surface <NUM>. The first surface <NUM> of the substrate is mounted on the first surface <NUM> of the heat sink for electrical and thermal conduction between the heat sink <NUM> and the substrate <NUM> via the first contact <NUM>. Since, in this example, the first surface <NUM> is an active surface of the device <NUM>, the orientation of the substrate <NUM> may enhance the ability of the heat sink <NUM> to disperse heat away from the region of the device (typically the pn junction) that is most susceptible to overheating. It is envisaged that in other examples first surface may be a passive surface of the substrate <NUM>. This alternative orientation of the substrate <NUM> may allow the active surface of the substrate to be mounted directly on the surface of the carrier (e.g. to reduce on-resistance).

The first surface <NUM> may be planar. The first surface <NUM> may be located on a first portion <NUM> of the heat sink <NUM> that extends substantially parallel to a plane containing the first surface <NUM> of the substrate <NUM> to allow convenient mounting of the substrate <NUM> on the heat sink <NUM>. Note that the provision of the first surface <NUM> can allow for a contact region between the heat sink <NUM> and the first contact <NUM> to have a relatively large surface area for good electrical and thermal conduction between the substrate <NUM> and the heat sink <NUM> via the first contact <NUM>. As shown in <FIG>, the connection between the first contact <NUM> and the first surface <NUM> of the heat sink <NUM> can include a substance <NUM> such as solder or an electrically conductive glue.

In this arrangement, the heat sink <NUM> also includes a second portion <NUM>. The second portion <NUM> extends away from the first portion <NUM> for mounting the electrically conductive heat sink <NUM> on the surface <NUM> of the carrier. In some arrangements, the second portion <NUM> of the heat sink <NUM> can extend in a direction substantially orthogonal to the plane of the first surface <NUM> of the substrate <NUM>. For instance, as shown in <FIG>, the second portion <NUM> extends down from the first portion <NUM> past an edge of the substrate <NUM> for mounting on the surface <NUM> of the carrier <NUM>. The mounting of the heat sink <NUM> on the surface <NUM> of the carrier <NUM> can be implemented at an end of the second portion <NUM> distal the first portion <NUM>. The mounting may be a mechanical mounting. In this arrangement however, in this example, the second portion <NUM> includes an electrical contact <NUM> to allow the electrically conductive heat sink <NUM> to form an electrical connection to the carrier <NUM>. For instance, an electrical contact <NUM> can be provided at a surface <NUM> of the second portion <NUM> located at an end of the second portion <NUM> distal the first portion <NUM>. In the example of <FIG>, the surface <NUM> of the second portion <NUM> is substantially coplanar the second surface <NUM> of the substrate <NUM>, such that the contact <NUM> is substantially coplanar the second contact <NUM> of the substrate <NUM>. This arrangement can allow for convenient mounting of the device <NUM> on a carrier <NUM> having a substantially planar surface.

<FIG> shows the device <NUM> of <FIG> mounted on a surface <NUM> of a carrier <NUM>. Note that when the device <NUM> is mounted on the carrier <NUM>, the first surface <NUM> of the heat sink <NUM> faces downward toward the surface <NUM> of the carrier <NUM>. Although not essential, this arrangement can allow for convenient placement of the substrate <NUM> between the first surface <NUM> and the surface <NUM>, particularly where the first surface <NUM> and the surface <NUM> are substantially parallel. As mentioned above, the surface <NUM> of the carrier <NUM> is, in this example substantially planar. As shown in <FIG>, the connection between the second contact <NUM> of the substrate <NUM> and the surface <NUM> of the carrier <NUM> may include a substance <NUM> such as solder or an electrically conductive glue. Similarly, the connection between the contact <NUM> of the second portion <NUM> of the heat sink <NUM> and surface <NUM> of the carrier <NUM> may include a substance <NUM> such as solder or an electrically conductive glue.

From <FIG> and <FIG>, it may be appreciated that the device <NUM> can form a compact construction in which the heat sink can provide an electrical connection between the first contact <NUM> of the substrate <NUM> and the surface <NUM> of the carrier.

<FIG> shows a semiconductor device <NUM> in accordance with an embodiment of this invention. In this embodiment, the thermally conductive heat sing <NUM> includes a further portion <NUM> that may be similar in construction to the second portion <NUM> described above in relation to <FIG> and <FIG>. The further portion <NUM> extends away from the first portion <NUM> for mounting the electrically conductive heat sink <NUM> on the surface of a carrier. The mounting may be a simple mechanical mounting and/or may allow a further electrical connection to be made between the heat sink <NUM> and a corresponding contact on the surface of the carrier. In the present example, the connection formed by the further portion <NUM> includes an electrical contact <NUM> located on a surface <NUM> of the further portion <NUM> that is at an end of the further portion <NUM> distal the first portion <NUM>. The configuration of the further portion <NUM> in this example is therefore similar to that of the second portion <NUM> of the heat sink <NUM>, although the further portion <NUM> is provided at a different location within the device <NUM>. In the example of <FIG>, the second portion <NUM> and the further portion <NUM> each extend down either side or edge of the substrate <NUM> in a direction away from the first portion <NUM>.

The provision of the further portion <NUM> in <FIG> can improve the robustness of the mechanical and/or electrical connection of the heat sink <NUM> to the surface of a carrier. Note that the provision of two contacts (either of the contacts <NUM> and <NUM>) in the embodiment of <FIG> can lower the contact resistance of the device. Also, since the heat sink <NUM> is mounted in multiple locations, the ability of the heat sink <NUM> to dissipate heat generated within the device <NUM> (for instance, during a stress pulse) away from the device <NUM> into a carrier upon which the device <NUM> may be mounted.

It is envisaged that more than two portions such as the second portion <NUM> and the further portion <NUM> described above in relation to <FIG> may be provided.

<FIG> shows a semiconductor device. The device <NUM> is similar to the device described above in relation to <FIG> and <FIG>. However, in this example, the device <NUM> includes two semiconductor substrates <NUM>. Both substrates <NUM> may be similar in configuration to the semiconductor substrates described above. Both semiconductor substrates <NUM> may thus have a first surface <NUM> that is mounted to a first surface <NUM> of the heat sink <NUM>. It is envisaged that more than two substrates <NUM> may be provided in this manner. The first surface <NUM> may be suitably dimensioned in order to receive each substrate <NUM>. The device in <FIG> can allow the pn junction diodes formed within each substrate <NUM> to be connected in parallel, increasing the capacity of the device <NUM>.

In common with the arrangements described above, the device <NUM> in the example of <FIG> includes a second portion <NUM> that forms an electrical connection to the surface of a carrier at a contact <NUM> provided on a surface <NUM> located at an end of the second portion <NUM> distal the first portion <NUM>. The second surfaces <NUM> of the substrates <NUM> may each be coplanar the surface <NUM> of the second portion <NUM>, to allow for convenient mounting of the device <NUM> on a carrier having a planar surface. It is envisaged that, as described above in relation to <FIG>, embodiments including multiple substrates may also include one or more further portions of the kind <NUM> shown in <FIG>.

<FIG> shows a semiconductor device <NUM>. The arrangement in <FIG> has a configuration that is similar to that described in relation to <FIG>, except that the second portion <NUM> of the heat sink <NUM> is located in between the substrates <NUM>, whereas in the example of <FIG>, the second portion <NUM> of the heat sink <NUM> extends down past an edge one of the substrates <NUM>. Because the second portion <NUM> in <FIG> is located equidistant the two substrates <NUM>, electrical and thermal conduction between the two substrates <NUM> and the second portion <NUM> of the heat sink <NUM> may be more balanced than in the example of <FIG>, in which one of the substrates <NUM> is further away from the second portion <NUM> than the other.

<FIG> shows a semiconductor device <NUM>. In this arrangement, the device <NUM> includes two semiconductor substrates <NUM> that may both be configured similarly to those described above. Both semiconductor substrates <NUM> may be mounted on a first surface <NUM> of a first portion <NUM> of the heat sink <NUM>. In this arrangement, the heat sink <NUM> does not necessarily include a second portion <NUM> of the kind described above. Where such a second portion is provided, the second portion may provide for mechanical mounting of the device <NUM> on the surface of the carrier, but would not include an electrical contact for forming an electrical connection.

In the arrangement of <FIG>, the device <NUM> is a bidirectional device including two pn junction diodes, one diode being located in each of the two semiconductor substrates <NUM>. The first diode may be connected to the surface of a carrier at the contact <NUM> of one of the substrates <NUM> and the second diode may be connected to the surface of the carrier at the contact <NUM> of the other substrate <NUM>. In this arrangement, the two diodes formed within the separate substrates <NUM> are connected together by the electrically conductive heat sink <NUM>. In particular, the electrical contacts <NUM> on the first surfaces <NUM> of each substrate <NUM> are electrically connected to the first surface <NUM> of the electrically conductive heat sink <NUM>. As noted above, the electrical connection between each first contact <NUM> and the surface <NUM> may include a substance such as solder or an electrically conductive glue.

In the arrangement, of <FIG>, the heat sink <NUM> can again perform a dual function: (i) to electrically interconnect the two diodes in the separate substrates <NUM> via their respective contacts <NUM>, and (ii) to act as a heat sink for draining heat away from the substrates <NUM>, for instance, during a stress pulse within the device <NUM>.

It is envisaged that in a device according to an arrangement in which two or more substrates are provided (for instance, see <FIG> and <FIG>), where some or all of those substrates have an active surface and a passive surface, those substrates may all be mounted with a common orientation (i.e. all of the substrates may be oriented such that their active surface is mounted on the first surface of the heat sink or such that their passive surface is mounted on the first surface of the heat sink). It is also envisaged that the substrates may be mounted in a mixture of orientations (i.e. some may be oriented such that their active surface is mounted on the first surface of the heat sink and some may be oriented such that their passive surface is mounted on the first surface of the heat sink). The orientation of the substrates may, for instance, be chosen according to the device type that they implement (e.g. diode, MOS transistor.

<FIG> shows a semiconductor device <NUM>. The device <NUM> is similar to that described above in relation to <FIG>. However, an encapsulant <NUM> is provided. The encapsulant covers the (or, where multiple substrates are provided, each) substrate <NUM> while leaving the second contact <NUM> of the (or each) substrate <NUM> exposed. The encapsulant <NUM> can thus provide mechanical protection for the substrate <NUM>. For instance the encapsulant <NUM> can protect the edges of the substrate <NUM> from mechanical damage. In some arrangements, the encapsulant <NUM> can also cover parts of the surface <NUM> that do not form a connection with the (or each) substrate <NUM>. In the arrangement of <FIG>, the encapsulant <NUM> is located in a region defined by the first surface <NUM> and an edge of the second portion <NUM> of the heat sink <NUM>. Any suitable encapsulant of the kind known in the art may be used.

<FIG> shows another view of a semiconductor device <NUM>. The arrangement in <FIG> is similar to that described above in relation to <FIG>. <FIG> shows the configuration of the encapsulant <NUM> to surround the substrate <NUM> while leaving the contact <NUM> of the substrate <NUM> exposed for electrical connection to the surface of a carrier. Note that <FIG> also illustrates that the encapsulant <NUM> leaves the surface <NUM> of the second portion <NUM> of the heat sink <NUM> exposed for connection in a similar manner.

<FIG> show semiconductor devices <NUM>. The arrangements in <FIG> are similar to those described above in relation to <FIG>, although the differences will be noted below.

In <FIG> it can be seen that the substrate of the device <NUM> is dimensioned differently to that shown in <FIG>. The heat sink <NUM> may receive substrates of various dimensions in accordance with design requirements.

The device <NUM> may include a protective portion <NUM>. The protective portion <NUM> may comprise a layer of material, which may be located on a surface of the heat sink <NUM>. For instance, as shown in <FIG>, the protective portion <NUM> may be provided on an outer surface of the heat sink opposite the first surface of the heat sink <NUM>. This may provide mechanical and electrical protection for an upper surface of the device <NUM> when the device <NUM> is mounted on a carrier. The protective portion <NUM> may comprise a plastics material. In some arrangements, the protective portion <NUM> comprises the same material as that used to the form the encapsulant <NUM>. A protective portion of this kind may also be included in any of the other arrangements described herein.

In <FIG>, two semiconductor substrates are provided. Unlike the arrangement in <FIG>, the substrates <NUM> in the arrangement of <FIG> are located side by side at a common distance away from the second portion <NUM> of the heat sink <NUM>. The arrangement, of <FIG> illustrate that the first surface <NUM> of the heat sink <NUM> may be dimensioned to receive any suitable number of substrates in accordance with design requirements.

The embodiments of <FIG> also show that the heat sink <NUM> may be provided with an electrically conductive layer <NUM> on its outer surface. For instance, the electrically conductive layer <NUM> may comprise a substance such as NiPdAu. This layer can act as a wetting layer to improve the solderability of the surface of the heat sink.

<FIG> shows a graph relating to package thicknesses that can be implemented. The thickness of a package (along a direction substantially parallel to the surface normal of the semiconductor substrate(s) provided in the package) is limited by the thickness of the first portion <NUM> of the heat sink <NUM>, by the thickness of the semiconductor substrate <NUM> itself and by any connections that are provided between the substrate(s) <NUM> and the heat sink <NUM>. As mentioned previously, devices need not incorporate bond wires, allowing them to achieve lower package thicknesses than devices of the kind shown in <FIG>. As can be seen from <FIG>, arrangements can be used to form packages having a thickness as small as <NUM> (for a semiconductor substrate thickness of <NUM>).

<FIG> show an example method of making a semiconductor device. In this embodiment, the method can allow a plurality of devices to be made.

In a first step, shown in <FIG>, the method involves providing an electrically conductive member <NUM> having a first surface <NUM>. The electrically conductive member will subsequently be divided into a plurality of portions as explained below, each portion of which will form an electrically conductive heat sink of the kind described above in relation to the earlier arrangements.

The electrically conductive member <NUM> can be suitably dimensioned and provided with features for forming the various parts of the heat sinks (e.g. the first and second portions <NUM>, <NUM> as well as any further portions) after dicing. The method can also include providing a substance <NUM> at locations on the surface <NUM> of the electrically conductive member <NUM> at which substrates <NUM> are to be placed. The substance <NUM> may, as noted above, comprise a solder or an electrically conductive glue. The substrates <NUM> may be placed at regular intervals onto the surface <NUM> at locations corresponding to the positions of the substance <NUM> using a picker <NUM> as shown in <FIG>, to reach the arrangement shown in <FIG>.

The method includes providing a plurality of such semiconductor substrates <NUM>, where each semiconductor substrate is of the kind described above in relation to the earlier arrangements.

Once the substrates <NUM> have been mounted onto the electrically conductive member <NUM> such that a first surface of each substrate is mounted on the surface <NUM>, an encapsulant <NUM> can be used to fill the space around the substrates <NUM> resulting in the arrangement shown in <FIG>. Note that the encapsulant <NUM> leaves the second contact of each substrate <NUM> exposed as noted above. Thereafter, the electrically conductive member <NUM> can be diced as indicated by the dotted lines in <FIG>. Each individual die produced by this dicing step can form a semiconductor device of the kind described above.

Embodiments of this invention can be used to implement a transient voltage suppression (TVS) diode. Transient voltage suppression diodes may typically need to handle large currents in order to drain unwanted current to ground or another rail during a stress pulse. Accordingly, embodiments of this invention are suited to the implementation of TVS diodes, since the electrically conductive heat sink can effectively dissipate heat generated by the stress pulse within the device, thereby allowing the TVS diode to handle larger currents during a stress pulse without overheating.

Although arrangements have been described in relation to a device including a pn junction diode (for instance for implementing a TVS diode), it is envisaged that the arrangement of the heat sink with one or more semiconductor substrates mounted thereon may also be used to implement other devices, e.g. MOS transistors.

Accordingly, there has been described a semiconductor device and a method of making the same. The device includes an electrically conductive heat sink having a first surface. The device also includes a semiconductor substrate. The device further includes a first contact located on a first surface of the substrate. The device also includes a second contact located on a second surface of the substrate. The first surface of the substrate is mounted on the first surface of the heat sink for electrical and thermal conduction between the heat sink and the substrate via the first contact. The second surface of the substrate is mountable on a surface of a carrier.

Claim 1:
A semiconductor device (<NUM>) comprising:
an electrically conductive heat sink (<NUM>) having a first surface (<NUM>);
a semiconductor substrate (<NUM>);
a first contact (<NUM>) located on a first surface (<NUM>) of the substrate (<NUM>), and
a second contact (<NUM>) located on a second surface (<NUM>) of the substrate (<NUM>),
wherein the substrate (<NUM>) includes a semiconductor region (<NUM>) located adjacent to the first surface (<NUM>), the semiconductor region (<NUM>) forming a pn junction at an interface between the semiconductor region (<NUM>) and the substrate (<NUM>),
wherein the first surface (<NUM>) of the substrate is mounted on the first surface (<NUM>) of the heat sink (<NUM>) for electrical and thermal conduction between the heat sink (<NUM>) and the substrate (<NUM>) via the first contact (<NUM>),
wherein the second surface (<NUM>) of the substrate (<NUM>) is configured and arranged to be mountable on a surface of a carrier,
wherein the pn junction located at the interface between the semiconductor region (<NUM>) and the substrate (<NUM>) forms an active region, the active region being located closer to the first surface (<NUM>) of the substrate (<NUM>) than the second surface (<NUM>), forming an active surface on the first surface (<NUM>) and a passive surface on the second surface (<NUM>), and
wherein the electrically conductive heat sink (<NUM>) comprises:
a first portion (<NUM>) extending substantially parallel to a plane containing the first surface (<NUM>) of the substrate, wherein the first portion comprises said first surface (<NUM>) of the electrically conductive heat sink (<NUM>),
a second portion (<NUM>) extending away from the first portion (<NUM>) of the electrically conductive heat sink (<NUM>) for mounting the electrically conductive heat sink (<NUM>) on the surface of the carrier; and
at least one further portion (<NUM>) extending away from the first portion (<NUM>) of the electrically conductive heat sink (<NUM>) for mounting the electrically conductive heat sink (<NUM>) on the surface of the carrier.