Patent Description:
In some biopolymer sensing technologies (see e.g., <NPL>)), long-chain biopolymers such as, e.g., DNA may be characterized by using a semiconductor device based on a field-effect transistor (FET), such as, e.g., a metal oxide semiconductor FET (MOSFET), comprising a drain region, a source region, a channel region, and an opening through the channel region allowing the biopolymer to pass. Such devices are now gaining credibility with respect to DNA sensing.

The voltage potential applied across the drain and source regions creates a gradient that causes the biopolymer to move through the opening. In case of, e.g., a DNA or RNA strand, the sequence of bases may induce charges, which can form a conducting channel in the semiconductor channel region between the drain and source regions, resulting in a current variation that can be detected by, e.g., a current meter. Each different type of bases A, C, G, and T (in case of a DNA strand) may induce a current having a particular magnitude and waveform representative of the respective type of bases. Thus, by studying the current variation as the sample passes through the opening, the sequence of bases can be detected.

Some of these technologies rely on an opening having a highly controlled size and shape. Depending on the type of biopolymer strand to be sensed, the opening is sometimes preferably configured to have a diameter small enough to allow only one stand to pass through the opening at any given time. DNA sequencing, for example, may be performed using an opening having a width within a nanoscale range, such as within the range of about <NUM> to about <NUM> such as an opening having a diameter of <NUM>. Forming such small openings is technically challenging, especially in terms of alignment.

Typically, as mask to mask overlay meet values down to <NUM> (using <NUM> lithography), obtaining the desired position of a nanopore seems to be only feasible by defining the hole position on the same mask designing the active area of the nanowire. However, the state-of-the-art of the <NUM> lithography does not allow resolving the print of a narrow hole into a narrow nanowire. Progress in Deep UV lithograph might finally make this doable but at a costly effort.

Efforts to find an alternative solution can be found in <CIT> where a method for forming a nanopore is described which comprises the steps of:.

In this method, an etch mask (the pillar) is positioned by self-alignment in the lateral direction of the fin structure, thereby enabling the formation of a semiconductor structure having an opening or pore laterally centred in the fin structure. However, there is still room for improvement over this patent application with respect to the positioning of other elements of a nanopore transistor such as the channel, the source, and the drain. Considering the accuracy demanded to have an operational device, using a new mask to position source, drain, and channel associated with the transistor after the nanopore is created is not realistic.

There is therefore a need in the art for methods overcoming one or more of the problems described above.

It is an object of the present invention to provide good nanopore transistors for biosensing as well as methods for producing the same.

It is an advantage of embodiments of the present invention that they enable a nanopore to be correctly formed on such a fin.

It is an advantage of embodiments of the present invention that they allow for an improved definition and positioning of the nanopore compared to etching the nanopore in a single lithographic step.

It is an advantage of embodiments of the present invention that they enable a nanopore to be correctly aligned on a fin having a width close to the width of the nanopore. In the multiple patterning process used in step a. , the position of the nanopore is aligned in a width direction, or lateral direction of the fin and aligned in a length direction of the fin.

It is an advantage of embodiments of the present invention that they enable the formation of a nanopore that is self-aligned in the lateral direction of the fin. It is an advantage of embodiments of the present invention that they allow a particularly good lateral alignment of the nanopore, thereby allowing for a particularly high ratio between the nanopore width and the fin width. A reduced fin width, or a reduced cross-section of the fin, is advantageous in that it may reduce the drive current during the operation of the device.

It is an advantage of embodiments of the present invention that a nanopore and a transistor can be co-fabricated without additional lithography process, in such a way that associated source and drain regions around the nanopore are self-aligned.

It is an advantage of embodiments of the present invention that the size of the nanopore can be easily adapted to accommodate and/or target different biosensing applications without added patterning complexity.

It is an advantage of embodiments of the present invention that they allow the formation of nanopore transistors having a nanopore small enough to be used for sensing polymers such as, e.g., DNA or RNA strands. Embodiments of the present invention are particularly useful for biosensing applications and especially for massive parallel biosensing applications such as DNA sequencing.

It is an advantage of embodiments of the present invention, that only a limited number of masks are required (typically two) to achieve an excellent positioning of a nanopore in the center for the transistor and channel width, and at equidistance of both the source and the drain by a self-aligning integration process.

It is an advantage of embodiments of the present invention that they use standard semiconductor manufacturing steps, thereby enabling the mass production of nanopore transistors at low cost.

It is an advantage of embodiments of the present invention that it is compatible with allowing fluidic access to the nanopore, thereby making the resulting devices compatible with sequencing applications.

In a first aspect, the present invention relates to a method for forming a nanopore transistor for biosensing, comprising:.

characterized in that the method further comprises:.

Two main embodiments are therefore described in the first aspect. In the first main embodiment (depicted in <FIG>), step d. is performed after step b. and preferably after step c. Performing step d. after step c. is advantageous because it allows having a high thermal budget for the formation of the gate dielectric without affecting the doping. In the second main embodiment (depicted in <FIG>), step d. is performed between step a. and step a. This embodiment is advantageous because it requires fewer steps than the first main embodiment. Both main embodiments, share most advantages of the present invention (correctly formed nanopore of adaptable size with good positioning on a fin, source and drain regions that are self-aligned with the nanopore, a limited number of masks, and a low-cost production).

In a second aspect, the present invention relates to a nanopore transistor for biosensing, formed by a method according to any one of the preceding claims.

In embodiments, the nanopore transistor for biosensing may comprise a fin structure comprising a semiconductor layer having:.

wherein the nanopore is centred with respect to the source and the drain so that the distance Ds along the top surface between the nanopore and the source is within <NUM> of the distance Dd along the top surface between the nanopore and the drain.

In embodiments, the nanopore is centred with respect to the width W so that the distances d1 and d2 between each longitudinal side and the nanopore are within <NUM> of one another.

In embodiments, the ratio between a width of the nanopore, measured in the plane of the top surface of the fin and along the width W of the fin, and the width W of the top surface of the fin may be from <NUM> to <NUM>.

Although there has been constant improvement, change, and evolution of devices in this field, the present concepts are believed to represent substantial new and novel improvements, including departures from prior practices, resulting in the provision of more efficient, stable, and reliable devices of this nature.

The above and other characteristics, features, and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention.

Furthermore, the terms first, second, third, and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner.

Moreover, the terms top, bottom, over, under, and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions.

It is thus to be interpreted as specifying the presence of the stated features, integers, steps, or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. The term "comprising" therefore covers the situation where only the stated features are present (and can therefore always be replaced by "consisting of" in order to restrict the scope to said stated features) and the situation where these features and one or more other features are present. The word "comprising" according to the invention therefore also includes as one embodiment that no further components are present.

Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

The following terms are provided solely to aid in the understanding of the invention.

As used herein, a pillar refers to a structure extending in the vertical direction, e.g., a direction normal to a major surface of the substrate. The pillar may also be referred to as a post, a dot, or mask feature that can be used as a sacrificial structure for forming the aperture through which the nanopore is etched.

As used herein, the term vertical (for instance with reference to a direction or a plane or the pillar) denotes a geometrical axis being parallel to a stacking direction of the layers of the fin structure, e.g., a direction normal to a major surface to the substrate. Correspondingly, a vertical axis may be perpendicular to a main plane of extension or a main surface of the substrate or a coplanar surface of a layer formed thereon, such as the bottom layer or the top layer. Terms such as above and under as used herein may accordingly refer to opposite directions along the vertical axis, with respect to a reference. As herein, the term horizontal denotes a horizontal axis being perpendicular to the vertical axis. In embodiments where the device resulting from the method includes a substrate supporting the afore-mentioned layers forming the fin structure, a 'vertical direction/plane may be understood as a direction/plane being perpendicular to a main plane of extension or a main surface of the substrate. Correspondingly, a 'horizontal' direction/plane may be understood as a direction parallel to a main plane of extension or a main surface of the substrate.

The terms fin or fin-structure as used herein may refer to a fin-shaped feature having a length and width extension in the horizontal direction and a height extension in the vertical direction. The width direction may also be referred to as a lateral direction of the fin. The fin-shaped features may be formed using standard fin-based processes, in which for example the stacked structure of the bottom layer and the top layer may be provided with trenches defining and separating the fins.

The term nanopore as used herein refers to an opening or channel extending in, and preferably through, the fin. Preferably, the nanopore extends at least through the semiconductor layer comprised in the fin. The prefix nano refers to the fact that a diameter, or width, or cross-sectional size of the pore may be from <NUM> to <NUM>. Preferably, the width of the nanopore is from <NUM> to <NUM>, more preferably from <NUM> to <NUM>, yet more preferably from <NUM> to <NUM>.

In a first aspect, the present invention relates to a method for forming a nanopore transistor for biosensing (<NUM>), comprising steps a. <FIG> and <FIG> depict two main embodiments of the method. We now refer to <FIG> where intermediates formed during step a. are depicted, and to <FIG> where the main steps involved in step a. are represented in a flowchart. comprises forming (S40) an aperture (<NUM>) in a filler material (<NUM>) by:.

We now refer to <FIG> where an intermediate formed during step b. is depicted. of the method is performed after step a. , preferably directly after step a. It comprises forming (S50, <FIG>) a nanopore (<NUM>) in the bottom semiconductor layer (<NUM>) by etching through the aperture (<NUM>).

We now refer to <FIG> wherein an exemplary embodiment is depicted where the method further comprises a step c. after step b. , of lining (S54) the nanopore with a gate dielectric material (<NUM>), thereby forming a gate dielectric. By forming a gate dielectric, the size of the nanopore may be advantageously reduced. The gate dielectric material is preferably an oxide, more preferably silicon oxide, yet more preferably a silicon oxide obtained by thermal oxidation.

In embodiments, between step b. and step c. , a step b'. of cleaning the inner sides of the nanopore may be performed to facilitate step c. We now refer to <FIG> where intermediates formed during step d. in a first main embodiment are depicted, to <FIG> where the main steps involved in that embodiment are presented in a flowchart, to <FIG> where an intermediate formed during step d. in a second main embodiment is depicted, and to <FIG> where the main steps involved in the second main embodiments are represented in a flowchart. comprises forming (<FIG> or <FIG>) a source (<NUM>) and a drain (<NUM>) by either:.

In embodiments, a step e. (S100, <FIG> and <FIG>). of removing the spacer material is performed. In preferred embodiments, the spacer material and the sealing material are the same, and the steps (S90) of <NUM>) removing the sealing material in in step d. ii and <NUM>) removing the spacer material in step e. are performed simultaneously.

By employing a pillar structure formed of a top layer and a bottom layer, and cutting the top layer into a pillar structure, the pillar structure can be used as a sacrificial structure for forming an etch aperture that is self-aligned in the lateral direction of the fin.

In embodiments, the device resulting from the method may include a substrate supporting the afore-mentioned layers forming the fin structure. In such embodiments, the semiconductor fin of step a. may be supported by a substrate. When the substrate is present, step b. may comprise forming the nanopore also in the substrate.

In embodiments, the nanopore may have a width of from <NUM> to <NUM>, preferably from <NUM> to <NUM>, more preferably from <NUM> to <NUM>. These widths are advantageous as they allow the sensing of biopolymers such as DNA and RNA strands. The nanopore is arranged in a channel region present between the drain region and the source region of the fin. The channel region becomes an actual channel as the sensed molecule passes through the opening. The distance D between the source and the drain regions corresponds to the length of the channel and may for instance be from <NUM> to <NUM>. The present method is, however, also applicable to longer and shorter channels.

In embodiments, the length extension of the nanopore may be oriented in the vertical direction, i.e., perpendicularly to the top surface of the bottom semiconductor layer.

In embodiments, a cross-section of the nanopore taken perpendicularly to the length extension thereof may be of any shape. Preferably, the width of the cross-section measured in the plane of the top surface of the bottom semiconductor layer is within <NUM>%, preferably <NUM>%, more preferably <NUM>% of the length of the cross-section measured in said plane. Most preferably, the width and the length of the cross-section are the same, such as in the case of a square or circular cross-section.

The nanopore may in one example have a substantially uniform diameter, or cross section, along its length (measured perpendicularly to the top surface of the bottom semiconductor layer). However, other configurations are also possible. In an embodiment, the nanopore may have a tapered or funnel-shaped profile, e.g., a diameter that decreases towards the bottom or base of the fin. Such a gradually reduced opening size may allow for an improved control of the flow through the opening, preferably such that only one sample strand at a time is guided through the opening. The tapered profile may, for example, be obtained by a wet etching process, such as potassium hydroxide (KOH) etching, resulting in a V-shaped profile along the (<NUM>) planes (in case of Si). Such a profile may comprise a facet of <NUM>° to the silicon surface. Other examples include reactive ion etching (RIE), which may be sequenced with sidewall passivation, using for example polymerization, to achieve the desired cross-sectional profile of the opening.

We now refer to <FIG> where an exemplary structure (<NUM>) resulting from step a. is depicted. In embodiments, step a. may comprise forming the fin structure by a lithography comprising a dry etching step. The fin structure (<NUM>) comprises a bottom semiconductor layer (<NUM>) and a top layer (<NUM>). The width of the fin may for instance be from <NUM> to <NUM> but the present method is applicable to wider or narrower fins. In embodiments, the fin structure has a bottom semiconductor layer (<NUM>) having a top surface having two longitudinal parallel sides separated by a width of from <NUM> to <NUM>. A reduced fin width, or a reduced cross-section of the fin, is advantageous in that it may reduce the drive current during the operation of the device.

In embodiments, the nanopore may be centred with respect to the width so that the distances d1 and d2 between each longitudinal side (<NUM>, <NUM>) and the nanopore are within <NUM> of one another, preferably within <NUM> of one another.

In embodiments, the distances along the top surface of the bottom semiconductor layer between each longitudinal side and the nanopore are from <NUM> to <NUM>, and are within <NUM>, preferably within <NUM> of one another.

In embodiments, the ratio between the width of the nanopore (measured at the top surface of the bottom semiconductor layer) and the width (W) of the top surface of the bottom semiconductor layer of the fin may be from <NUM> to <NUM>, preferably from <NUM> to <NUM>, more preferably from <NUM> to <NUM>, yet more preferably from <NUM> to <NUM>. A high ratio is advantageous because it allows the use of a smaller fin width, which in turn reduces the drive current during the operation of the device.

In embodiments, the bottom semiconductor layer, of which the resulting fin may be formed, may for example be formed of silicon, such as the top silicon layer of a silicon on insulation (SOI) substrate.

In embodiments, the top layer may comprise a mask material. For instance, the mask material may be Si<NUM>N<NUM>.

In embodiments (not depicted), the top layer may comprise a first mask material and a second mask material, different from the first mask material, and arranged on top of the first mask material, wherein the first material is an etch stop material protecting the bottom layer during etching of the second mask material. This allows for a better process control of the top layer patterning, resulting in a reduced risk of etch-back of the bottom layer during the pillar formation. Hence, a method is obtained which is compatible with a bottom layer having a reduced thickness.

In embodiments, the first mask material may be formed of SiO<NUM>, Si<NUM>N<NUM>, SiOC, and silicon oxynitride (SiON), and wherein the second mask material is selected from amorphous silicon (a-Si), TiN, SiO<NUM>, Si<NUM>N<NUM>, SiOC, and silicon oxynitride (SiON). Preferably, the first mask material and the second mask material are selected so as to achieve an etch selectivity between the mask layers, thereby enabling an etch stopping effect of the double mask. Such combinations may for example be a first mask material of SiO<NUM> combined with a second mask material of a-Si. This is particularly advantageous when the bottom layer, forming the fin, is formed of Si, since the intermediate first mask material of SiO<NUM> allows for the pillar pattern to be transferred into the second mask material without damaging or etching back the underlying Si fin.

We now refer to <FIG> where an exemplary structure resulting from step a. is depicted. This structure comprises a pillar (<NUM>) and may for instance be formed by self-aligning (S22) the pillar on the bottom layer using a line mask (<NUM>) intersecting the fin structure, as depicted in <FIG> for an exemplary embodiment. In other words, a line mask may be used to form the top layer of the fin structure into the pillar. The line mask may extend in a direction intersecting the length direction of the fin, such as, for example, orthogonal to the length direction of the fin, such that the region in which the line mask overlaps the material of the top layer defines the etch mask used when cutting the top layer into the pillar. The resulting pillar may thus be self-aligned in the lateral direction on the fin, whereas the lengthwise position may be determined by the lithographic process forming the line mask.

In embodiments, the line mask may have a width which is within <NUM>%, preferably <NUM>%, more preferably <NUM>%, yet more preferably <NUM>% of the width of the fin structure it intersects. Most preferably the width of the line mask is the same as the width of the fin structure it intersects. This has the advantage of forming a pillar that has equal lateral dimensions, thereby enabling the formation of a nanopore having equal lateral dimensions (e.g., having a square or circular cross-section).

To form the pillar (<NUM>), the top layer (<NUM>) may be etched selectively with respect to the bottom semiconductor layer. In the case of a bottom Si layer and a top Si<NUM>N<NUM> layer, this step can be performed by a suitable ion etching technique.

After the line mask is removed, the resulting structure is a fin having the top layer present only at the intersections of the two lithography patterns, thereby forming a pillar. The height of the resulting pillar is equal to the thickness of the top layer and typically ranges from the thickness of the semiconductor layer (<NUM>) and three time the thickness of the semiconductor layer (<NUM>), while one of its two lateral dimensions equals the width of the nanowire while the other of its two lateral dimensions equals the width of the line mask.

We now refer to <FIG> where an exemplary structure resulting from step a. is depicted. In embodiments, the filler material (<NUM>) may be selected such that an etch selectivity to the pillar material is achieved. The filler material may for example be SiO<NUM> or Si<NUM>N<NUM>. Preferably, the filler material is SiO<NUM>.

may comprise a first sub-step (see <FIG>) of embedding the pillar in the filler material in such a way that all the pillar surfaces are covered, followed by a second sub-step (see <FIG>) of removing a top portion of the filler material so as to expose the top surface of the pillar. In embodiments, the first sub-step may result in a thickness of filler material equal to at least <NUM>% of the height of the pillar. The second sub-step can, for example, be performed by chemical mechanical planarization. In the resulting structure, the top surface of the pillar and the top surface of the filler are co-planar.

We now refer to <FIG> where an exemplary structure resulting from step a. is depicted. Removing the pillar can, for instance, be performed by etching the pillar selectively with respect to the filler.

We now refer to <FIG> where an exemplary structure resulting from step a. is depicted.

of lining the aperture (<NUM>) with a spacer material (<NUM>) reduces a size of the aperture.

The spacer material may, for example, be provided in an atomic layer deposition (ALD) process or by oxidation (e.g., thermal or anodic) of the sidewalls of the aperture. Oxidation has the advantage of enabling the size of the opening to be monitored during the oxidation process Adding the spacer material allows for the size of the resulting nanopore to be reduced to a desired size, such as down to a width as small as <NUM>. The spacer material may, for example, be silicon dioxide (SiO<NUM>), silicon nitride (Si<NUM>N<NUM>), silicon oxycarbide (SiOC), or a metal such as titanium nitride (TiN), tantalum nitride (TaN) or aluminum nitride (AIN). Preferably, the filler material (<NUM>) is silicon dioxide.

We now refer to <FIG> where an exemplary embodiment is depicted, wherein the step (S60) of filling the aperture during step d. comprises overfilling the aperture (<NUM>) with a sealing material (<NUM>) so that the sealing material (<NUM>) covers part of the filler material (<NUM>).

In embodiments, the sealing material may be Si<NUM>N<NUM>.

We now refer to <FIG> wherein overfilling the aperture is followed by removing a top portion (<NUM>) of the sealing material (<NUM>) until it no longer covers any filler material.

In embodiments, removing the top portion may be performed by a wet etch, a chemical mechanical planarization, or a combination of both.

We now refer to <FIG> where the step (S70) of removing the filler material in step d. is depicted for an exemplary embodiment of the present invention. The resulting structure has the bottom semiconductor layer exposed around the post.

We now refer to <FIG> where the doping step (S80) in step d. is depicted for an exemplary embodiment of the present invention. In embodiments, the ion implantation in the bottom semiconductor layer may form a source and a drain separated by <NUM> to <NUM>. In embodiments, the nanopore is centred with respect to the source and the drain so that the distance, along the top surface of the bottom semiconductor layer, between the nanopore and the source is within <NUM>, preferably within <NUM>, of the distance along the top surface between the nanopore and the drain. In embodiments, the distance along the top surface of the bottom semiconductor layer between the nanopore and the source and between the nanopore and the drain is from <NUM> to <NUM> and these distances are within <NUM>, preferably <NUM> of one another.

We now refer to <FIG> depicting the result of an embodiment of the method further comprising a step c'. , after the step (S70) of removing the filler material and before the doping step (S80), of forming spacers around the post, wherein the doping step (S80) comprises using the post and the spacers as a mask. This is advantageous when implantation is wished farther from the nanopore or when a multi-implant scheme is desired as is sometimes the case in CMOS technologies.

In embodiments, the method may further comprise a step d'. , after step d. , of exposing the bottom semiconductor layer to heat so as to activate dopants introduced in step d.

In embodiments, steps (S80) of removing the sealing material and step e. may be performed together by simultaneously exposing the sealing material and the spacer material to a same etching liquid. The resulting structure is depicted in <FIG> and <FIG>. It has a nanopore (<NUM>) which is self-aligned with respect to the channel width W, the source (<NUM>), and the drain (<NUM>) of the transistor (<NUM>).

We now refer to <FIG> which depicts an exemplary embodiment wherein step d. is performed between step a. and step a. In the example of <FIG>, a dielectric spacer, e.g., SiO<NUM>, is formed around the post.

We now refer to <FIG> which depicts an exemplary embodiment wherein step b. is performed by etching through the bottom silicon layer (<NUM>), and if present through the first mask material (<NUM>) (which is the case in <FIG>), by using an etchant capable to etch the bottom silicon layer (and if present the first mask material) selectively with respect to the filler material. The etching method used may, for example, be reactive ion etching.

In embodiments, step b. may be performed after step a. and before step d. and the sealing material may be the same as the spacer material. For example, both the sealing material and the spacer material may be silicon nitride.

In a second aspect, the present invention relates to a nanopore transistor for biosensing, formed by a method according to any one of the preceding claims. We now refer to <FIG> and <FIG>.

In embodiments, the nanopore transistor for biosensing (<NUM>) may comprise a fin structure (<NUM>) comprising a semiconductor layer (<NUM>) having:.

To the best of the inventor's knowledge, such a nanopore transistor, with such precision in the placement of the nanopore, could not have been made before the present invention. Such a device can be produced with high consistency in the nanopore placement precision and devices of high sensitivity can be obtained showing a high signal to noise ratio.

In embodiments, the width of the nanopore measured in the plane of the top surface may be from <NUM> to <NUM>, preferably from <NUM> to <NUM>, more preferably from <NUM> to <NUM>.

In embodiments, the distances along the top surface between each longitudinal side and the nanopore are within <NUM> of one another.

In embodiments, the distances along the top surface between each longitudinal side and the nanopore are from <NUM> to <NUM> and are within <NUM>, preferably within <NUM> of one another.

In embodiments, the distance along the top surface between the nanopore and the source is within <NUM> of the distance along the top surface between the nanopore and the drain.

In embodiments, the distance Ds along the top surface between the nanopore and the source and the distance Dd between the nanopore and the drain is from <NUM> to <NUM> and these distances are within <NUM>, preferably <NUM> of one another.

In embodiments, the ratio between the width of the nanopore (measured in the plane of the top surface of the fin and along the width of the fin) and the width (W) of the top surface of the fin may be from <NUM> to <NUM>, preferably from <NUM> to <NUM>, more preferably from <NUM> to <NUM>, yet more preferably from <NUM> to <NUM>. A high ratio is advantageous because it allows the use of a smaller fin width, which in turn reduces the drive current during the operation of the device.

Any feature of the second aspect may be as correspondingly described in the first aspect.

Claim 1:
Method for forming a nanopore transistor for biosensing (<NUM>), comprising:
a. forming (S40) an aperture (<NUM>) in a filler material (<NUM>) by:
i. providing (S10) a fin structure (<NUM>) comprising at least a bottom semiconductor layer (<NUM>) and a top layer (<NUM>);
ii. pattering (S20) the top layer (<NUM>) to form a pillar (<NUM>);
iii. laterally embedding (S30) the pillar (<NUM>) in a filler material (<NUM>);
iv. forming (S40) an aperture (<NUM>) in the filler material (<NUM>) by removing the pillar (<NUM>);
v. lining (S42) the aperture (<NUM>) with a spacer material (<NUM>), thereby reducing a size of the aperture (<NUM>);
characterized in that the method further comprises:
b. forming (S50) a nanopore (<NUM>) in the bottom semiconductor layer (<NUM>) by etching through the aperture (<NUM>);
c. lining (S54) the nanopore (<NUM>) with a gate dielectric material (<NUM>), thereby forming a gate dielectric;
d. Forming a source (<NUM>) and a drain (<NUM>) by either:
i. Between steps a.ii. and a.iii., doping the bottom semiconductor layer (<NUM>) by ion implantation using the pillar (<NUM>) as a mask, or
ii. After step b.,
- filling (S60) the aperture (<NUM>) with a sealing material (<NUM>) so that the sealing material (<NUM>) is coplanar with the filler material (<NUM>), thereby forming a post (<NUM>) comprising the sealing material (<NUM>) and the spacer material (<NUM>);
- removing (S70) the filler material (<NUM>) selectively with respect to the post (<NUM>), thereby exposing a part (<NUM>) of the bottom semiconductor layer (<NUM>);
- doping (S80) the bottom semiconductor layer (<NUM>) by ion implantation by using the post (<NUM>) as a mask; and
- removing (S90) the sealing material (<NUM>).