Patent Description:
The use of embedded radar systems in industrial and automotive applications is evolving rapidly. For example, embedded radar systems are useful in a number of applications associated with a vehicle such as adaptive cruise control, collision warning, blind spot warning, lane change assist, parking assist and rear collision warning. Further, embedded radar systems are useful in industrial or security applications, such as tracking movement inside a house or building under surveillance and maneuvering a robot in a factory or warehouse. In such usages, accuracy of obj ect detection and tracking is important. <CIT> discloses adaptive mismatch compensators and methods for mismatch compensation. <CIT> discloses a beam forming device using frequency-dependent calibration.

A FMCW radar system according to the invention is defined in claim <NUM>. A method of operation of a FMCW radar system according to the invention is defined in claim <NUM>.

Specific embodiments are described in detail with reference to the accompanying drawings. Like elements in the various drawings are denoted by like reference numerals for consistency.

In frequency modulated continuous wave (FMCW) radar systems with multiple receive channels and multiple transmit channels, differences in radio frequency (RF) trace lengths in the receive channels and the transmit channels can cause routing delay mismatches that lead to errors in beamforming and in object angle estimation performed using digital signal data from the receive channels. In FMCW radar systems, differences in RF trace lengths are equivalent to differences in intermediate frequency (IF) offsets. Thus, frequency shifting can be used to compensate for the different routing delays between transmit channels and between receive channels caused by the trace length differences. Some approaches for using frequency shifting to correct routing delay mismatches between transmit channels and between receive channels are described in Patent Publication No. <CIT>.

In some embodiments, digital frequency shifting is implemented in the digital baseband of a radar system to compensate for routing delay mismatches between receive channels. The use of digital frequency shifting to compensate for routing delay mismatches between the receive channels removes the differences in the IF offsets but does not correct for any intermediate frequency (IF) filtering mismatches, i.e., mismatches in the analog baseband filter responses experienced by the IF signals in the receive channels because of the different IF frequency offsets. In some embodiments, digital compensation filters, which may be referred to as IF response mismatch compensation filters herein, are applied in addition to the digital frequency shifting to correct the IF filter response mismatches. In some embodiments, digital matching filters, which may be referred to as IQ matching filters herein, are employed before the routing delay IF response mismatch compensation to compensate for mismatches of the in-phase (I) and quadrature (Q) arms of filters in the analog basebands in each receive channel. In some embodiments, self-calibration of parameters for the digital frequency shifting and/or digital IF response mismatch compensation filters and/or digital IQ matching filters is also provided.

<FIG>, <FIG>, and <FIG> are block diagrams of an example FMCW radar system <NUM> configured to perform digital compensation for routing delay mismatches between receive channels and to perform automatic calibration of parameter values used for the digital compensation. <FIG> illustrates the top level architecture of the radar system <NUM>, <FIG> illustrates an example FMCW radar transceiver integrated circuit (IC) suitable for use in the radar system <NUM>, and <FIG> provides a more detailed view of the configuration of the radar transceiver IC for digital correction of routing delay mismatches and automatic calibration of the parameter values used by the digital correction.

Referring to <FIG>, the example FMCW radar system <NUM> illustrated is suitable for use in an embedded application such as in a vehicle. The radar system <NUM> includes a radar transceiver IC <NUM>, a processing unit <NUM>, and a network interface <NUM>. The radar transceiver IC <NUM> is coupled to the processing unit <NUM> via a high speed serial interface. As further described in reference to <FIG>, the radar transceiver IC <NUM> includes functionality to generate multiple digital intermediate frequency (IF) signals (alternatively referred to as dechirped signals, beat signals, or raw radar signals) that are provided to the processing unit <NUM> via the high speed serial interface.

The processing unit <NUM> includes functionality to perform radar signal processing, i.e., to process the received radar signals to determine various parameters, such as distance, velocity, and angle of any detected objects. The processing unit <NUM> may also include functionality to perform postprocessing of the information about the detected objects, such as tracking objects, determining rate and direction of movement, etc..

The processing unit <NUM> may include any suitable processor or combination of processors as needed for the processing throughput of the application using the radar data. For example, the processing unit <NUM> may include a digital signal processor (DSP), a microcontroller (MCU), an SOC combining both DSP and MCU processing, or a field programmable gate array (FPGA) and a DSP.

The processing unit <NUM> provides control information as needed to one or more electronic control units in the vehicle via the network interface <NUM>. Electronic control unit (ECU) is a generic term for any embedded system in a vehicle that controls one or more the electrical system or subsystems in the vehicle. For example, types of ECU include electronic/engine control module (ECM), powertrain control module (PCM), transmission control module (TCM), brake control module (BCM or EBCM), central control module (CCM), central timing module (CTM), general electronic module (GEM), body control module (BCM), and suspension control module (SCM).

The network interface <NUM> may implement any suitable protocol, such as the controller area network (CAN) protocol, the FlexRay protocol, or Ethernet protocol.

Referring to <FIG>, the radar transceiver IC <NUM> may include multiple transmit channels <NUM> for transmitting FMCW signals and multiple receive channels <NUM> for receiving the reflected transmitted signals. Any suitable number of receive channels and transmit channels may be used in embodiments. Further, the number of receive channels and the number of transmit channels may not be the same. For example, an embodiment of the radar transceiver IC <NUM> may have two transmit channels and four receive channels.

A transmit channel includes a suitable transmitter and antenna. A receive channel includes a suitable receiver and antenna. Further, each of the receive channels <NUM> are identical and include a low-noise amplifier (LNA) <NUM>, <NUM> to amplify the received radio frequency (RF) signal, a mixer <NUM>, <NUM> to mix the transmitted, i.e., local oscillator (LO), signal with the received RF signal to generate an intermediate frequency (IF) signal, a baseband bandpass filter <NUM>, <NUM> for filtering the IF signal, a variable gain amplifier (VGA) <NUM>, <NUM> for amplifying the filtered IF signal, and an analog-to-digital converter (ADC) <NUM>, <NUM> for converting the analog IF signal to a digital IF signal. The bandpass filter, VGA, and ADC of a receive channel may be collectively referred to as the analog baseband, the baseband chain or the baseband filter chain. Further, the bandpass filter and VGA may be collectively referred to as an IF amplifier (IFA). Also, the bandpass filter may be referred to as the IF filter herein.

The receive channels <NUM> are coupled to the digital front end (DFE) component <NUM> to provide the digital IF signals to the DFE <NUM>. The DFE <NUM>, which may also be referred to as the digital baseband, may include functionality to perform decimation filtering on the digital IF signals to reduce the data transfer rate. The DFE <NUM> may also perform other operations on the digital IF signals, e.g., DC offset removal, digital compensation of non-idealities in the receive channels, such as inter-RX gain imbalance non-ideality and inter-RX phase imbalance non-ideality.

As further described in reference to <FIG>, in some embodiments, the DFE <NUM> also includes mismatch compensation circuitry to compensate for routing delay mismatches and IF filter response mismatches in the receive channels <NUM>. As further described in reference to <FIG>, in some embodiments, the mismatch compensation circuitry of the DFE <NUM> includes circuitry to correct mismatches between the in-phase (I) and quadrature (Q) channels of the IF filters in each receive channel. These mismatches may be referred to as IQ filter mismatches or IQ filter imbalances.

The DFE <NUM> is coupled to the high speed serial interface (I/F) <NUM> to transfer the digital IF signals (after processing in the DFE <NUM>) to the processing unit <NUM> when the radar transceiver IC <NUM> is operated in normal mode. The DFE <NUM> is also coupled to the control module <NUM> to transfer digital calibration signals to the control module <NUM> when the radar transceiver IC <NUM> is operated in calibration mode.

The serial peripheral interface (SPI) <NUM> provides an interface for communication with the processing unit <NUM>. For example, the processing unit <NUM> may use the SPI <NUM> to send control information, e.g., timing and frequencies of chirps, output power level, triggering of monitoring functions, etc., to the control module <NUM>. The radar transceiver IC <NUM> may use the SPI <NUM>, such as to send test data to the processing unit <NUM>.

The control module <NUM> includes functionality to control the operation of the radar transceiver IC <NUM> in normal mode and in calibration mode. For example, the control module <NUM> may include a buffer to store output samples of the DFE <NUM>, an FFT (fast Fourier transform) engine to compute spectral information of the buffer contents, and a microcontroller that executes firmware to control the operation of the radar transceiver IC <NUM>. In some embodiments, the control module <NUM> includes functionality to determine parameter values for the mismatch compensation circuitry in the DFE <NUM> when the radar transceiver IC <NUM> is operated in calibration mode. Embodiments of the mismatch compensation circuitry of the DFE <NUM> are described in reference to <FIG> and <FIG> and operation of the control module <NUM> in calibration mode to determine the parameter values is described in reference to the method of <FIG>.

The programmable timing engine <NUM> includes functionality to receive chirp parameter values for a sequence of chirps in a radar frame from the control module <NUM> and to generate chirp control signals that control the transmission and reception of the chirps in a frame based on the parameter values. For example, the chirp parameters are defined by the radar system architecture and may include a transmitter enable parameter for indicating which transmitters to enable, a chirp frequency start value, a chirp frequency slope, an analog-to-digital (ADC) sampling time, a ramp end time, a transmitter start time, etc..

The radio frequency synthesizer (SYNTH) <NUM> includes functionality to generate FMCW signals for transmission based on chirp control signals from the timing engine <NUM>. In some embodiments, the SYNTH <NUM> includes a phase locked loop (PLL) with a voltage controlled oscillator (VCO).

The clock multiplier <NUM> increases the frequency of the transmission signal (LO signal) to the LO frequency of the mixers <NUM>, <NUM>. The clean-up PLL (phase locked loop) <NUM> operates to increase the frequency of the signal of an external low frequency reference clock (not shown) to the frequency of the SYNTH <NUM> and to filter the reference clock phase noise out of the clock signal.

Referring to <FIG>, an embodiment of the radar transceiver IC <NUM> of <FIG> configured for compensation of routing delay mismatches and IF filter response mismatches of the receive channels <NUM> is illustrated. As further described hereinbelow, the digital compensation in the receive channels <NUM> is performed using circuitry in the DFE <NUM>, i.e., the digital baseband. For simplicity of explanation, the depicted embodiment has four receive channels and two transmit channels. In other embodiments, the number of receive channels and/or the number of transmit channels may differ.

The two transmit channels each incorporate a signal power amplifier chain of a pre-power amplifier (PPA) <NUM>, <NUM> coupled to the SYNTH <NUM> to receive the FMCW signal, a programmable shifter <NUM>, <NUM> coupled to the PPA <NUM>, <NUM> to receive the amplified signal, and a power amplifier (PA) <NUM>, <NUM> coupled to the shifter <NUM>, <NUM> to receive the shifted signal. In some embodiments, the shifter <NUM>, <NUM> may be programmed for both frequency and phase shifting. Accordingly, the output signal of a shifter <NUM>, <NUM> may have a frequency equal to the input frequency plus a programmable offset frequency and a phase equal to the input phase plus a programmable offset phase. A transmit antenna in each transmit channel is coupled to the respective PA <NUM>, <NUM> to receive the amplified shifted signal for transmission.

In some embodiments, the radar transceiver IC <NUM> may be configured to correct routing delay mismatches between the transmit channels <NUM>. Some suitable approaches for correction of routing delay mismatches in transmit channels are described in the above-cited Patent Publication No. <CIT>.

To perform the digital correction of routing delay mismatches and IF filter response mismatches of the receive channels <NUM>, the DFE <NUM> includes mismatch compensation circuitry that includes, for each receive channel <NUM>, a frequency shifter and a digital IF response mismatch compensation filter <NUM>, <NUM>, <NUM>, <NUM> coupled to respective frequency shifters to receive the signal output by the respective frequency shifter. In the depicted embodiment, each frequency shifter includes a digital mixer <NUM>, <NUM>, <NUM>, <NUM> coupled to the respective ADC of the respective receive channel to receive the digital IF signal and a programmable digital frequency generator <NUM>, <NUM>, <NUM>, <NUM> coupled to the digital mixer <NUM>, <NUM>, <NUM>, <NUM> to provide a shift signal of the needed frequency and phase to shift the frequency of the digital IF signal as needed to correct the routing delay mismatch in the respective receive channel. Each digital mixer <NUM>, <NUM>, <NUM>, <NUM> multiplies the received digital IF signal and the shift signal from the respective frequency generator <NUM>, <NUM>, <NUM>, <NUM> to generate a digital IF signal modified to compensate for the routing delay mismatch of the respective receive channel.

Generally, a digital frequency generator is a component that produces a complex digital signal based on input values for one or more of the following parameters: desired tone frequency ftone, desired tone phase φ, desired tone amplitude A, and sampling frequency Fs. The resulting signal is given by <MAT>.

In various embodiments, the input parameters to the frequency generators <NUM>, <NUM>, <NUM>, <NUM> are the desired phase and frequency of the output signal, i.e., the phase and frequency values that will compensate for the effect of any routing delay mismatch in the respective receive channel when mixed with digital IF signal. The sampling frequency Fs is usually known a priori, and is fixed, for a fixed ADC sampling rate and for a fixed position of the digital mixer in the DFE. The amplitude A is also usually known a priori.

In some embodiments, the values of the phase and frequency parameters for the frequency generators <NUM>, <NUM>, <NUM>, <NUM> are determined by factory calibration using a calibration mode of the radar transceiver IC <NUM>. In some embodiments, the values of the phase and frequency parameters may be tuned during operation of the radar system <NUM> using the calibration mode. Calibration to determine the initial values of the phase and frequency parameters and to tune these values during operation of the radar system <NUM> is described in reference to the method of <FIG>. In some embodiments, the values of the phase and frequency parameters may be directly programmed based on knowledge of the routing delay mismatches.

The digital IF response mismatch compensation filters <NUM>, <NUM>, <NUM>, <NUM> operate to compensate for any IF filter response mismatch remaining after the removal of the frequency offsets by the frequency shifting of the digital IF signals. The IF response mismatch compensation filters <NUM>, <NUM>, <NUM>, <NUM> may be implemented as complex coefficient digital infinite impulse response (IIR) filters, with programmable coefficients that can be determined by calibration. The technique is initially described assuming a simple first order high pass filter (HPF) that models the desired IF filter response. With good over-sampling, the bilinear transform faithfully translates the desired analog HPF H(s) response to an equivalent digital HPF H(z) response according to: <MAT> where G is the in-band gain of the HPF, Fs is the digital sampling rate, ωc is the HPF corner frequency expressed in radians per second, rc, the value of which is directly determined by ωc and Fs, is the equivalent digital filter pole, s is the complex frequency of the s-transform, z is the complex frequency of the z-transform, and α is a scale factor used to ensure the same in-band gain level G as the original analog response, i.e., <MAT>. The HPF corner frequency, which is also known as the 3dB corner frequency or cut-off frequency or pole frequency, is given by fc = <MAT>. A tone at frequency fc will be attenuated by 3dB compared to an in-band tone. This is true of a first order pole.

The following description assumes that the IF filter responses on the in-phase (I) and quadrature (Q) arms of each receive channel are matched and thus a single IF filter response for each receive channel can be assumed. The actual IF filter response for a particular receive channel may be different from the desired IF filter response because of errors in the in-band gain and the cut-off frequency, and may be given by <MAT> where the use of ~ as an accent in Hactual (z) indicates values that are potentially different from corresponding values of the desired response H(z).

Assuming that the digital frequency shift applied in a particular receive channel to compensate for routing delay mismatch is -fo, the effective equivalent filter response for the receive channel becomes <MAT> where <MAT> and <MAT> The digital IF response mismatch compensation filter in the receive channel operates to transform Hactual(z) to a close approximation of the desired H(z). More specifically, in some embodiments, the digital IF response mismatch compensation filter implements a complex-coefficient digital IIR filter Gcamp(z) that transforms Hactual(z) to a close approximation of the desired H(z).

As illustrated by the pole zero plots of H(z) and Hactual(z) in <FIG>, the frequency shift manifests as a rotation of the pole-zero plot. Ideally, the digital IF response mismatch compensation filter would implement Hcomp(z) to transform Hactual(z) to the desired H(z) according to: <MAT> where <MAT> is the gain mismatch factor, resulting in, as illustrated in the pole zero plots of <FIG>, the removal of the rotated pole-zero pair and restoration of the original pole-zero pair. However, this ideal compensation filter is unstable because of the pole on the unit circle.

The digital IF response mismatch compensation filter can implement an approximate and stable compensation filter Gcomp(z) with the following response <MAT> As illustrated in the pole zero plots of <FIG>, the use of this approximate compensation filter results in a pole very close to the unit circle, leaving a narrow "residual notch" at -ω<NUM>, which is acceptable as the residual notch at -ω<NUM> is completely out of band because the IF signal in FMCW radar is one-sided. The frequency shift direction for routing delay IF response mismatch compensation can be chosen such that the post-compensation notch component appears out of band.

More specifically, the effective, i.e., compensated, response Heff(z) is given by <MAT> The result is a close approximation of the desired response, except for the notch. The notch can be made as narrow as desired by pushing the value of r<NUM> closer to <NUM> at the cost of increased implementation complexity.

In various embodiments, the input parameters to each of the digital IF response mismatch compensation filters <NUM>, <NUM>, <NUM>, <NUM> are the gain mismatch factor γ̃, the digital pole <MAT>, and the digital frequency shift parameter ω<NUM>. Notably, r<NUM> is a design parameter, and rc is known because the desired response is known. In some embodiments, the values of the input parameters γ̃, <MAT>, and ω<NUM> for the IF response mismatch compensation filters may be directly programmed based on knowledge of the routing delay mismatches. In some embodiments, the values of the input parameters γ̃, <MAT>, and ω<NUM> for the digital IF response mismatch compensation filters <NUM>, <NUM>, <NUM>, <NUM> may be determined by factory calibration using a calibration mode of the radar transceiver IC <NUM>. In some embodiments, the values of these parameters may be tuned during operation of the radar system <NUM> using the calibration mode. Calibration to determine the initial values of these parameters and to tune these values during operation of the radar system <NUM> is described in reference to the method of <FIG>.

The digital IF response mismatch compensation filters <NUM>, <NUM>, <NUM>, <NUM> are programmed assuming that the analog IF filters in each of the receive channels are calibrated to have matching responses in the I and Q channels. In some embodiments, the filter responses for the I and Q channels in each receive channel are locally well matched, i.e., for a given receive channel, the filter responses for the I and Q channels match, but a global mismatch may exist in filter responses across the receive channels. For example, in such embodiments, the local filter response match may be due to the physical proximity of the filters and/or "filter trimming" performed using a calibration signal generator and programmable CTRIM and RTRIM controls. Any global mismatch in filter responses across receive channels may be corrected in the digital IF response mismatch compensation filters by letting the parameters γ̃ and <MAT> be different for different receive channels.

As mentioned hereinabove, in some embodiments, the DFE <NUM> includes functionality to compensate for the IQ filter response mismatches before routing delay mismatch compensation. More specifically, as shown in the example of <FIG>, an embodiment of the DFE <NUM> includes, for each receive channel <NUM>, a digital IQ matching filter <NUM>, <NUM>, <NUM>, <NUM> coupled between respective ADCs and digital mixers <NUM>, <NUM>, <NUM>, <NUM>. The digital IQ matching filters <NUM>, <NUM>, <NUM>, <NUM> operate to correct the IQ filter imbalances in respective receive channels before the frequency shifted signal is generated by the respective digital mixers <NUM>, <NUM>, <NUM>, <NUM>.

The IQ matching filters <NUM>, <NUM>, <NUM>, <NUM> may be implemented as separate pole-zero relocating real coefficient digital IIR filters on the I and Q arms of each receive channel with programmable coefficients (parameters) that can be determined by calibration. As with the description of the digital IF response mismatch compensation filters, a simple first order HPF that models the desired IF filter response is assumed. As mentioned hereinabove, with good over-sampling, the bilinear transform translates the desired analog HPF H(s) response to an equivalent digital HPF H(z) response according to: <MAT>.

Assuming an IQ filter imbalance, i.e., a mismatched corner frequency and in-band gain between IF Filters on the I and Q channels of a particular receive channel, the effective equivalent filter responses in the I and Q channels are given by <MAT> <MAT> where <MAT>.

Let <MAT> and <MAT> denote the gain mismatch factors for the I and the Q channels, respectively. Here, as before, the ~ accents indicate that the values are potentially different from those corresponding to the desired response H(z). The digital IQ matching filter associated with this receive channel operates to transform Hactual,I(z) and Hactual,Q(z) to a common Hactual(Z).

In an example embodiment, the digital IQ matching filter for a particular receive channel implements a filter Gmatch,I(Z) on the I channel alone, but does not perform any filtering on the Q channel, using the following response: <MAT> This causes the I channel response to be transformed to <MAT> which results in a common effective filter response for the I and Q channels of the particular receive channel, given by <MAT> In such an embodiment, the effective IF filter parameters for the receive channel under consideration become α̃ = α̃Q and r̃c = r̃c,Q.

In other embodiments, the IQ matching filter is implemented using a filter on the Q channel alone, with the I channel left as-is. In such embodiments, the effective IF filter parameters for the receive channel under consideration become α̃ = α̃I and r̃c = r̃c,I. The fact that the resultant Hactual(z) for the receive channel is potentially different from the desired H(z) (because, potentially, α̃ ≠ α and r̃c ≠ rc), and could be different across receive channels, is then addressed using the digital IF response mismatch compensation filter as described earlier.

In various embodiments, the input parameters to each of the digital IQ matching filters are the gain mismatch factors γ̃I , γ̃Q and the digital poles <MAT>. Also, the effective gain mismatch factor γ̃, and the digital pole <MAT> parameter values for the digital IF response mismatch compensation filters <NUM>, <NUM>, <NUM>, <NUM> are determined by the corresponding γ̃I , γ̃Q and <MAT>, as described hereinabove. In some embodiments, the values of the input parameters γ̃I , γ̃Q and <MAT> are determined by factory calibration using a calibration mode of the radar transceiver IC <NUM>. In some embodiments, the values of these parameters may be tuned during operation of the radar system <NUM> using the calibration mode. Calibration to determine the initial values of these parameters and to tune these values during operation of the radar system <NUM> is described in reference to the method of <FIG>.

<FIG> are flow diagrams of a method for calibrating frequency shifters and compensation filters used for digital compensation for routing delay mismatches and IF filter response mismatches in an FMCW radar system such as that of <FIG>. <FIG> is a flow diagram of the calibration flow and <FIG> are flow diagrams of specific aspects of the calibration. Portions of the depicted method may be performed during factory calibration using a reflector at a known position and angle. Further, in some embodiments, the depicted method may be used during operation of the radar system for recalibration if a reflector at a known position and angle is present, e.g., a vehicle bumper. In such embodiments, the method may be performed periodically, e.g., every few seconds, to compensate for potential changes in the receive channels during operation, e.g., for ambient temperature change induced residual imbalances such as expansion/contraction of metal traces or antenna responses. For example, how often the method is performed during operation of the radar system may depend on the particular application of the system.

The method of <FIG> is described in reference to the radar system <NUM> of <FIG>. To perform the method of an FMCW radar system, the radar system <NUM> is placed in calibration mode by the control module <NUM>. Referring first to <FIG>, initially the control module <NUM> determines <NUM> the gain mismatch factors and the digital poles for each IF response mismatch compensation filter. Determination of the values of these parameters is described hereinbelow in reference to <FIG>. The control module <NUM> then determines <NUM> the frequency offsets for the frequency shifters and the frequency shift parameters for the IF response mismatch compensation filters. Determination of the values of these parameters is described hereinbelow in reference to <FIG>. The control module <NUM> then programs <NUM> the frequency generators <NUM>, <NUM>, <NUM>, <NUM> and the digital match compensation filters <NUM>, <NUM>, <NUM>, <NUM> using the computed parameters. The control module <NUM> then determines <NUM> the phase offsets for the frequency shifters. Determination of the values of these parameters is described hereinbelow in reference to <FIG>. The control module <NUM> then programs <NUM> the frequency shifters with the phase offsets.

<FIG> is a flow diagram illustrating determination of gain mismatch factors and digital poles for the digital IF response mismatch compensation filters according to step <NUM> of <FIG>. To perform the depicted steps, the frequency shifters and the digital IF response mismatch compensation filters are disabled, bypassed, or programmed to have no effect. Initially, the control module <NUM>, using a programmable IF calibration signal generator, causes a calibration tone to be fed <NUM> into each IF filter being calibrated. The calibration signal should have a frequency that is well in-band and far away from the corner frequency. For example, for an HPF, the frequency will be significantly away from the expected HPF corner frequency, e.g., the HPF corner frequency is <NUM> and the frequency of the calibration tone is <NUM>. In some embodiments, the calibration tone is fed directly from the calibration signal generator to the IF filter. In some embodiments, the mixer in the analog baseband is disabled to avoid a spurious signal from the mixer output during calibration.

Digital calibration signals are generated <NUM> in the I and Q arms of each receive channel and the control module <NUM> computes the value of the gain mismatch factor γ̃ for each IF response mismatch compensation filter. More specifically, for each digital calibration signal, the control module <NUM> performs an FFT (separately on the I and Q arms of each receive channel), and measures the magnitude (absolute value) of the frequency component corresponding to the in-band calibration tone. For each IF filter, this magnitude, ρ̃in, is proportional to the IF filter gain, α̃, and is compared to the expected magnitude, ρin (which is known based on the expected IF filter gain α) to obtain the value of the gain mismatch factor γ̃ according to: <MAT>.

The control module <NUM>, again using the programmable IF calibration signal generator, causes another calibration tone to be fed <NUM> into each IF filter. This calibration signal should be at a frequency fcalib close to the desired IF filter corner frequency fc (so as to not be considered in-band). Digital calibration signals are generated <NUM> in the I and Q arms of each receive channel and the control module <NUM> performs an FFT (separately on the I and Q arms of each receive channel), and measures the magnitude (absolute value) of the frequency component corresponding to the calibration tone. For each IF filter, this magnitude, ρ̃calib, along with the magnitude of the in-band calibration tone measured earlier, ρ̃in, is used to compute the IF filter corner frequency f̃c through the following approximate relation (assuming the example first order HPF): <MAT> The above equation is a quadratic equation in (<NUM>/f̃c) and can be solved to compute f̃c.

After the filter corner frequencies f̃c are computed, the control module <NUM> then computes <NUM> the values of the corresponding digital filter poles <MAT> for each IF response mismatch compensation filter based on the respective ω̃c = <NUM>πf̃c according to: <MAT>.

<FIG> is a flow diagram illustrating determination of the frequency offsets and frequency shift parameters according to step <NUM> of <FIG>. Initially, the control module <NUM> causes the generation of at least one chirp that is transmitted <NUM> by one of the transmit channels <NUM>. The chirp bandwidth, slope, etc., may be chosen based on criteria such as the specific application of the radar system, the expected range of variation in trace-lengths, etc..

The reflected signal from the known reflector is received <NUM> in all receive channels <NUM> and a digital calibration signal is generated <NUM> in each receive channel. The control module <NUM> then computes <NUM> frequency offsets for the frequency generators <NUM>, <NUM>, <NUM>, <NUM> and frequency shift parameters for the compensation filters <NUM>, <NUM>, <NUM>, <NUM> based on the digital calibration signals. In some embodiments, the frequency shifters and IF response mismatch compensation filters in the DFE <NUM> are bypassed, and the digital calibration signals are provided directly to the control module <NUM>. In some embodiments, the frequency shifters and IF response mismatch compensation filters are programmed (or disabled) to have no effect on the digital calibration signals.

To compute the frequency offsets, one of the receive channels <NUM> is designated as a reference receive channel and frequency offsets for the frequency generators in the other receive channels are computed relative to the reference receive channel. The frequency of the digital calibration signal in the reference receive channel and each non-reference receive channel RXi is computed, i.e., fRXi is computed, where i indicates a particular receiver. The frequency may be computed, such as by performing a fast Fourier transform (FFT) on the digital calibration signal, and identifying the location of the peak in terms of an FFT bin index (interpolating between bin locations, if needed, to get a fractional part for the bin index). The frequency is determined given the sampling rate of the FFT input, the FFT size, and the location of the peak (as a bin index).

Assuming that RX1 is the reference receive channel, frequency corrections that need to be applied to each of the other receive channels i to compensate for routing delay mismatch with the reference receive channel are computed based on the values of fRX<NUM> and fRXi. Accordingly, the frequency shift needed between the reference receive channel RX1 and a non-reference receive channel RXi is computed as fRX<NUM> - fRXi.

The frequency shift parameters ω<NUM>,i for the IF response mismatch compensation filters corresponding to the receive channels RXi are then computed based on the frequency offsets determined for these receive channels. For the reference receive channel, the compensation filter will not have any frequency-shift based (e-jω0) modification, i.e., ω<NUM> is <NUM> for the reference receive channel.

For each non-reference receive channel RXi, a frequency shift -f<NUM>,i corresponding to the offset in the frequency of the IF signal from the non-reference receive channel with respect to the frequency of the IF signal from the reference channel is applied to correct the routing delay mismatch between the two channels. Specifically, for each non-reference receive channel RXi, <MAT> No frequency shift is applied to the reference receive channel RXi, thus f<NUM>,<NUM> = <NUM>. The value of ω<NUM>,i may be computed by <MAT>.

<FIG> is a flow diagram illustrating determination of the phase offsets according to step <NUM> of <FIG>. Initially, the control module <NUM> causes the generation of at least one chirp that is transmitted <NUM> by one of the transmit channels <NUM>. The reflected signal from the known reflector is received <NUM> in all receive channels <NUM> and a digital calibration signal is generated <NUM> in each receive channel. The control module <NUM> then computes <NUM> phase offsets for the frequency generators <NUM>, <NUM>, <NUM>, <NUM> based on the digital calibration signals. In this instance, the digital calibration signals received by the control module <NUM> are processed by respective frequency shifters and digital mismatch filters. The frequency shifter for the reference receive channel may be disabled, bypassed, or programmed to have no effect.

The phase of the digital calibration signal in the reference receive channel RX1 and in each receive channel RXi is computed, i.e., θRXi is computed, where i indicates a particular receiver. For example, the phase may be computed by performing a fast Fourier transform (FFT) on the digital calibration signal, and identifying the location of the peak in terms of an FFT bin index (interpolating between bin locations, if needed, to get a fractional part for the bin index), and determining the phase angle of the peak.

The phase corrections that need to be applied to each of the non-reference receive channels i to compensate for routing delay mismatch with the reference receive channel are computed based on the values of θRX<NUM>, θRXi, and ΔθRXi1. Given that the frequencies of the signals are identical after the frequency shifts are applied, in the absence of any routing delay mismatch induced phase offsets, the θRXi are related to θRXi through a known formula. Generally, the relation of the θRXi to θRXi has the form <MAT> where ΔθRXi1 is known a priori for a known angular position of the calibration reflector and the structure of the antenna array. Thus the phase offset for each of the non-reference receive channels may be computed as θRXi + ΔθRXi1 - θRXi.

The method of <FIG> assumes that the analog IF filters in the receive channels are calibrated to have matching responses in the I and Q channels. As mentioned hereinabove, in some embodiments, a digital IQ matching filter is used to remove the IQ filter mismatches. In such embodiments, the method of <FIG> is modified to include determination of parameters for the digital IQ matching filters <NUM>, <NUM>, <NUM>, <NUM> and programming of these filters. More specifically, step <NUM> of <FIG> will include determination of the parameters for the digital IQ matching filters and will also include programming the digital IQ matching filters according to these parameters before step <NUM>. Further, the flow of <FIG> will include determination of the parameters for the digital IQ matching filters <NUM>, <NUM>, <NUM>, <NUM>. If the responses of the IF filters in the I and Q channels of a receive channel are not matched, the flow of <FIG> will provide: the needed parameter values for the IQ matching filters; and values for the gain mismatch factors and digital poles.

<FIG> is a flow diagram of a method for digital compensation for routing delay mismatches and IF filter response mismatches in receive channels of an FMCW radar system such as that of <FIG>. The depicted method may be performed for each frame of radar chirps. The depicted method assumes that the frequency shifters and the digital IF response mismatch compensation filters have been suitably programmed. The parameter values for the shifters and the compensation filters may be determined, such as using self-calibration according to the method of <FIG>. Further, the depicted method of an FMCW radar system is described in reference to the radar system <NUM> of <FIG>.

Initially, the control module <NUM> causes the generation <NUM> of transmission signals for a frame of chirps. The reflected signals are received <NUM> in each of the receive channels and a digital IF signal is generated <NUM> in each receive channel. The frequency shifter corresponding to each receive channel except the reference receive channel applies <NUM> a frequency shift to the respective digital IF signal to generate a frequency shifted IF signal. As described in reference to <FIG>, one of the receive channels is treated as a reference receive channel that is used as the basis for determining the frequency shift parameters for the other receive channels and, thus, no frequency shifting is applied to the digital IF signal generated in the reference receive channel.

The digital IF response mismatch compensation filter component corresponding to each receive channel that generates a frequency shifted IF signal then applies <NUM> a compensation filter to the respective digital IF signal output by the respective frequency shifter. Also, the digital IF response mismatch compensation filter component corresponding to the reference receive channel applies a compensation filter to the respective digital IF signal. The resulting digital IF signals are then output <NUM> for further processing.

The method of <FIG> has been described assuming that the analog IF filters in the receive channels are calibrated to have matching responses in the I and Q channels. As mentioned hereinabove, in some embodiments, a digital IQ matching filter is used to remove the IQ filter mismatches. Thus, in some embodiments of the method of <FIG>, a digital IQ matching filter corresponding to each receive channel is applied to the respective digital IF signal before the frequency shifting of step <NUM>.

Embodiments have been described herein in which the radar system is an embedded radar system in a vehicle. Embodiments are possible for other applications of embedded radar systems, e.g., surveillance and security applications, maneuvering a robot in a factory or warehouse, etc..

In another example, embodiments have been described herein in which the digital baseband includes a frequency generator for each receive channel. In other embodiments, the frequency generation is performed by one or more frequency generation components configurable to provide the needed frequency shift signal to multiple digital mixers. For example, in some such embodiments, one such frequency generation component may be used to provide the needed frequency shift signals to all the digital mixers.

In another example, embodiments have been described herein assuming a single radar transceiver IC in the radar system. In other embodiments, the radar system includes more than one radar transceiver IC and in which the described digital compensation of routing delay mismatches is performed across receive channels in two or more radar transceiver ICs.

In another example, the digital IF signals pass through one or more decimation filtering stages in the digital baseband before the digital compensation is applied.

In another example, the compensation filters are for a low pass filter (LPF) and for more complex transfer functions, e.g., for instances in which the analog base band includes multiple HPFs and/or LPFs.

In another example, embodiments have been described herein in which the determination of the IQ matching filter, frequency shifting and/or compensation filtering parameters is performed by a control component on a radar transceiver IC. In other embodiments, the parameter determination is performed off-chip by another processor.

In another example, embodiments have been described herein in which the digital baseband includes a frequency shifter and a digital IF response mismatch compensation filter for each receive channel. In other embodiments, the digital baseband does not include such components for the reference receive channel. The IF response mismatch compensation filter for a reference receive channel may be omitted if the response of the reference receive channel is the "desired response" for all the other channels.

In another example, embodiments have been described herein in which digital frequency shifting is performed before IF response mismatch compensation filtering. In other embodiments, the order of the digital frequency shifting and the IF response mismatch compensation filtering is swapped. In such embodiments, for the HPF example used throughout, when the compensation filter is applied before the frequency shifting, the filter takes the form <MAT>.

In another example, embodiments have been described herein in which the DFE includes both frequency shifters and digital IF response mismatch compensation filters. In other embodiments, the digital IF response mismatch compensation filters are not present or are not used, e.g., embodiments in which the filter responses across receive channels are well matched by design and the required frequency shifts for routing delay matching are small enough to allow the IF filter response mismatch due to the frequency offsets to be ignored.

In another example, embodiments have been described herein in which the DFE includes both frequency shifters and digital IF response mismatch compensation filters. In other embodiments, the frequency shifters are not present or are not used, e.g., embodiments in which the RF trace lengths are well matched, but IF filter responses of the receive channels are not matched, such as due to spatial variations of circuit component values or variation across radar ICs in a multi-IC configuration.

In another example, embodiments are described herein in which f̃c is directly computed based on an approximate relation between the measured magnitude ratio and the filter cut-off. In other embodiments, f̃c is determined differently. For example, an iterative technique may be used in which an initial calibration tone that is close to the expected corner frequency is fed to the IF filters and, for each IF filter, the filter gain is measured at that frequency. The calibration tone frequency is then iteratively moved in a direction such that the ratio of the "well in-band" magnitude and the "magnitude at the current frequency" moves closer and closer to 3dB.

In another example, embodiments have been described herein in which the LO signal output by the SYNTH is provided to PPAs in the transmit channels and to the mixers in the receive channels. In other embodiments, an LO distribution network is used. Generally, an LO distribution network is a tree of cells that communicates the LO signal to the mixers of the receive channels and the shifters of the transmit channel. For example, the cells may be wires or amplifiers such as the PPAs or frequency multipliers or frequency dividers.

In another example, embodiments have been described herein in which a clock multiplier is used. In other embodiments, the multiplier is not needed because the SYNTH operates at the LO frequency rather than a lower frequency.

In another example, embodiments have been described herein in which the transmission signal generation circuitry is assumed to include a radio frequency synthesizer. In other embodiments, this circuitry includes an open loop oscillator (radio frequency oscillator) plus a digital-to-analog converter (DAC) or other suitable transmission signal generation circuitry.

Although method steps may be presented and described herein in a sequential manner, one or more of the steps shown in the drawings and described herein may be performed concurrently, may be combined, and/or may be performed in a different order than the order shown in the drawings and/or described herein. Accordingly, embodiments are not limited to the specific ordering of steps shown in the drawings and/or described herein.

Claim 1:
A FMCW radar system (<NUM>) comprising:
a receive channel (<NUM>) configured to receive a reflected signal and to generate a first digital intermediate frequency, IF, signal based on the reflected signal;
a reference receive channel (<NUM>) configured to receive the reflected signal and to generate a second digital IF signal based on the reflected signal; and
digital mismatch compensation circuitry (<NUM>) coupled to the receive channel and the reference receive channel to receive the first digital IF signal and the second digital IF signal, the digital mismatch compensation circuitry configured to process the first digital IF signal and the second digital IF signal to compensate for mismatches between the receive channel (<NUM>) and the reference receive channel (<NUM>), wherein the digital mismatch compensation circuitry includes:
a frequency shifter (<NUM>,<NUM>;<NUM>,<NUM>;<NUM>,<NUM>;<NUM>,<NUM>) configured to shift a frequency and phase of the first digital IF signal to correct a routing delay mismatch between the receive channel (<NUM>) and the reference receive channel (<NUM>).