Patent Description:
Chip packages that include stacked semiconductor chips or dies can provide significantly higher performance in comparison to conventional individually packaged chips that are connected to a printed circuit board. These chip packages also provide certain advantages, such as the ability: to use different processes on different chips in the stack, to combine higher density logic and memory, and to transfer data using less power. For example, a stack of chips that implements a dynamic random access memory (DRAM) can use a high-metal-layer-count, high-performance logic process in a base chip to implement input/output (I/O) and controller functions, and a set of lower metal-layer-count, DRAM-specialized processed chips can be used for the rest of the stack. In this way the combined set of chips may have better performance and lower cost than: a single chip that includes I/O and controller functions manufactured using the DRAM process; a single chip that includes memory circuits manufactured using a logic process; and/or attempting to use a single process to make both logic and memory physical structures.

However, it can be difficult to assemble chip packages that include stacked semiconductor chips. In particular, existing assembly techniques may be time-consuming and may have low yields (which may increase the cost of the chip package). For example, in many existing assembly techniques the total vertical position error over the stack of semiconductor chips is the sum of the vertical position errors associated with each of the semiconductor chips. Consequently, the total vertical position error for stacks that include multiple semiconductor chips can become prohibitively large. This may result in tight manufacturing tolerances to reduce the individual vertical position errors (which can increase the cost of the semiconductor dies) and/or may constrain the number of semiconductor chips that can be assembled in a stack (which may limit performance).

<CIT> describes an assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terraced at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a housing having another stepped terrace. This other stepped terrace may include a sequence of steps in the vertical direction, which are offset from each other in the horizontal direction. Furthermore, the housing may be configured to mate with the set of semiconductor dies such that the set of semiconductor dies are arranged in the stack in the vertical direction. ; For example, the other stepped terrace may approximately be a mirror image of the stepped terrace.

Hence, what is needed is a technique for assembling a stack of chips without the problems described above.

The claimed invention is set out in the appended claims.

Note that like reference numerals refer to corresponding parts throughout the drawings. Moreover, multiple instances of the same part are designated by a common prefix separated from an instance number by a dash.

An assembly component and a method for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package includes a ramp component positioned on one side of the vertical stack, which is approximately parallel to a direction along the stepped terrace. This chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

By facilitating assembly of the chip package, the assembly component and the assembly techniques may enable low-cost, high-throughput manufacturing of a high-performance chip package (such as a chip package with high-bandwidth interconnects). In particular, this assembly component may facilitate reduced mechanical errors during assembly of the chip package, and a chip package that is more tolerant of mechanical variations in sizes and positions of components in the chip package. For example, the set of semiconductor dies may be assembled in the chip package with a total vertical position error over the stack that is less than the vertical position errors (which are sometimes referred to as 'vertical errors') associated with the semiconductor dies and the adhesive layers between the semiconductor dies. This may be achieved by independently referencing the assembly tool that positions each semiconductor die in the chip package to the assembly component (instead of mechanically referencing a given semiconductor die in the stack to an immediately preceding semiconductor die during assembly). Thus, the assembly component and the associated assembly technique may prevent the individual vertical position errors from being compounded.

<FIG> presents a block diagram illustrating a top view of an assembly component <NUM> (which is sometimes referred to as a 'manufacturing fixture') that is used to position and secure semiconductor dies (or chips) during assembly of a chip package (such as chip package <NUM> in <FIG> and <FIG>, which is sometimes referred to as a 'ramp-stack chip package'). This assembly component includes a pair of stepped terraces <NUM>, which may be fabricated using a grinding mill. These stepped terraces are on either side of a ramp-stack chip package that is being assembled. Moreover, a given stepped terrace (such as stepped terrace <NUM>-<NUM>) includes a sequence of steps <NUM> in a vertical direction <NUM> (<FIG>). Note that each step after step <NUM>-<NUM> is offset in a horizontal direction <NUM> by an associated one of offset values <NUM> from an immediately preceding step in the sequence of steps <NUM>. Furthermore, offset values <NUM> may each have approximately a constant value for the sequence of steps <NUM> or may vary over the sequence of steps <NUM> (i.e., the offset values for different steps <NUM> in the pair of stepped terraces <NUM> may be different).

Additionally, as shown in <FIG>, which presents a block diagram illustrating a side view of assembly component <NUM>, vertical displacements <NUM> associated with the sequence of steps <NUM> (other than those for step <NUM>-<NUM> or step <NUM>-N) may each have approximately a constant value or may vary over the sequence of steps <NUM> (i.e., the vertical displacements for different steps <NUM> in stepped terraces <NUM> may be different).

As shown in <FIG>, which presents a block diagram illustrating a side view of assembly of the chip package using this assembly component, the pair of stepped terraces are configured to mate with an assembly tool <NUM> that positions a set of semiconductor dies <NUM> (e.g., <NUM> semiconductor dies <NUM>) such that the set of semiconductor dies <NUM> are arranged in a stack <NUM> in vertical direction <NUM>. Note that vertical direction <NUM> is substantially perpendicular to semiconductor die <NUM>-<NUM> in stack <NUM> (and, thus, with horizontal direction <NUM>). Additionally, each semiconductor die, after semiconductor die <NUM>-<NUM>, may be offset in horizontal direction <NUM> by an associated one of offset values <NUM> from an immediately preceding semiconductor die in stack <NUM>, thereby defining the stepped terrace at one side of stack <NUM>. These offset values may have approximately a constant value for the set of semiconductor dies <NUM> or may vary over the set of semiconductor dies <NUM> (i.e., the offset values for different steps in stepped terrace <NUM>-<NUM> may be different).

During assembly of the chip package, while the pair of stepped terraces constrains a vertical position of assembly tool <NUM> that is mated with a given pair of steps <NUM> (<FIG> and <FIG>), assembly tool <NUM> is mechanically coupled to a top surface of the given semiconductor die (for example, the given semiconductor die may be held in place using a vacuum) and a bottom surface of the given semiconductor die is mechanically coupled to the chip package (for example, using an adhesive, such as a glue). Unlike existing assembly techniques in which the bottom surface of the given semiconductor die is used as a reference, by using the top surface as a reference this assembly technique may be less sensitive to variations in the thicknesses of semiconductor dies <NUM> (such as variations in thickness <NUM> associated with uneven thinning) that can result in position errors in stack <NUM>. In particular, a given pair of steps in the pair of stepped terraces and the top surface ensure that the bottom surface of the given semiconductor die is in the correct position.

Note that the given semiconductor die may include solder pads and bumps on the top surface. Consequently, it may not be possible to assemble the chip package by placing semiconductor dies <NUM> face down on stack <NUM> (even though this arrangement would also be less sensitive to thickness variations of semiconductor dies <NUM>) because this could damage the solder pads and bumps. Instead, assembly tool <NUM> may pick up the given semiconductor die in a region of the top surface other than where the solder pads and the bumps are located. In addition, assembly tool <NUM> ensures that the given semiconductor die does not touch the pair of stepped terraces. In particular, assembly tool <NUM> overhangs semiconductor dies <NUM> on one or more edges. These so-called 'wings' (such as wing <NUM>-<NUM>) are rigid structures that can be placed against the steps in the pair of stepped terraces. These steps act as rigid stops that control the position of assembly tool <NUM> and, thus, the top surface of the given semiconductor die. This is illustrated in <FIG>, which presents a drawing illustrating a front view of the assembly process for chip package <NUM> according to the claimed invention. In <FIG>, note that there may be intentional gaps between semiconductor dies <NUM> that are filled with adhesive layers <NUM> (such as a glue), and which may be able to tolerate variation in the thickness of semiconductor dies <NUM> so that it does not affect the final placement accuracy or position error. However, this assembly technique may be sensitive to a thickness of semiconductor die <NUM>-<NUM> in stack <NUM> because this semiconductor die may rest on a fixture that holds the pair of stepped terraces. One solution for this challenge is to use a 'dummy' die for semiconductor die <NUM>-<NUM>, which would allow the first position in stack <NUM> to be sacrificed without wasting real semiconductor dies <NUM> in stack <NUM>. In this case, the total height of stack <NUM> may be adjusted so that stack <NUM> includes the same number of real semiconductor dies <NUM>.

As additional semiconductor dies <NUM> are placed, assembly tool <NUM> moves up and back along each of the pair of stepped terraces, each time resting on a new set of co-planar steps with the offset in the horizontal direction. Before placing a semiconductor die in stack <NUM>, an adhesive layer may be deposited on the top surface of the preceding semiconductor die in stack <NUM>. Note that, in contrast with existing assembly techniques, these adhesive layers may only need to be set once when assembling the chip package.

As shown in <FIG>, which presents a block diagram illustrating a side view of assembled chip package <NUM> not falling within the scope of the claimed invention, assembly component <NUM> (<FIG> and <FIG>) may facilitate assembly of chip package <NUM> in which high-bandwidth ramp component <NUM> is rigidly mechanically and electrically coupled to semiconductor dies <NUM>, thereby facilitating communication between semiconductor dies <NUM> and supplying power to semiconductor dies <NUM>; ramp component <NUM> is positioned on one side of stack <NUM> (<FIG>) and ramp component <NUM> is approximately parallel to a direction <NUM> (at angle <NUM>) along stepped terrace <NUM>-<NUM> (<FIG>), which is between horizontal direction <NUM> and vertical direction <NUM>.

Referring back to <FIG>, to facilitate the assembly the pair of stepped terraces may approximately be a mirror image of stepped terrace <NUM>-<NUM>. Furthermore, a given semiconductor die in the set of semiconductor dies <NUM> may have a nominal thickness <NUM>, and a vertical displacement of a given step in a sequence of steps <NUM> (<FIG> and <FIG>) may be larger than nominal thickness <NUM> (or it may be larger than a maximum thickness of any of semiconductor dies <NUM>). However, note that the thickness of at least some of semiconductor dies <NUM> in stack <NUM> may be different (for example, the thicknesses may vary over stack <NUM>).

Vertical displacements <NUM> (<FIG>) may each be <NUM> versus nominal thickness <NUM> of <NUM> ± <NUM>. (However, thickness <NUM> may be between <NUM> and <NUM>, such as <NUM>. ) This additional vertical displacement relative to thickness <NUM> may allow the adhesive in adhesive layers <NUM> to spread during assembly. Note that for nominal thickness <NUM> of <NUM>, angle <NUM> (<FIG>) may be between <NUM> and <NUM>°. In general, nominal thickness <NUM> depends, in part, on the number of semiconductor dies <NUM> in stack <NUM>. Furthermore, note that a nominal thickness <NUM> of adhesive layers <NUM> may be <NUM>. However, the thickness of adhesive layers <NUM> may vary along vertical direction <NUM> in stack <NUM>. (Note that adhesive layers <NUM> may provide tolerance for vertical position errors in stack <NUM>.

Additionally, the offset value at a given step in the pair of stepped terraces <NUM> (<FIG> and <FIG>) may be the same as or larger than the associated offset value in stepped terrace <NUM>-<NUM>. In general, offset values <NUM> (<FIG> and <FIG>) and offset values <NUM> may be determined based on direction <NUM> (or angle <NUM>) in <FIG> and a nominal thickness of solder (such as solder ball <NUM> in <FIG>) used to rigidly mechanically couple ramp component <NUM> (<FIG>) to set of semiconductor dies <NUM>. Note that the thickness of the solder may be approximately constant over the stack or may vary over the stack (i.e., along vertical direction <NUM>).

Because assembly component <NUM> (<FIG> and <FIG>) reduces the sensitivity of the chip package to variations of thicknesses of semiconductor dies <NUM> (such as thickness <NUM>), assembly component <NUM> (<FIG> and <FIG>) may facilitate assembly of the set of semiconductor dies <NUM> with an accumulated position error over the set of semiconductor dies <NUM> in vertical direction <NUM> (i.e., an accumulated position error in the vertical positions of semiconductor dies over the stack <NUM>) that is less than a sum of vertical errors associated with the set of semiconductor dies <NUM> and adhesive layers <NUM> (such as an epoxy or glue that cures in <NUM> at <NUM> C) between the semiconductor dies <NUM>. For example, the accumulated vertical position error may be associated with: thickness variation of the semiconductor dies <NUM>, thickness variation of adhesive layers <NUM>, and/or thickness variation of an optional heat-spreading material <NUM> (such as pressed graphite fibers) in at least some of adhesive layers <NUM>. The accumulated vertical position error may be a couple of microns (such as less than <NUM>), and may be as small as <NUM>. The vertical position error of a given semiconductor die is ±<NUM> to <NUM>. This may be accomplished by using the assembly tool (which may be coupled to a pick-and-place machine) to assemble chip package <NUM> (<FIG>) in conjunction with optical alignment markers (such as fiducial markers) on assembly component <NUM> in <FIG> and <FIG> and/or semiconductor dies <NUM>. Alternatively or additionally, assembly component <NUM> in <FIG> and <FIG> includes mechanical stops, such as mechanical stops fabricated using polyimide, and the assembly tool may be pushed up against these mechanical stops during assembly of chip package <NUM> in <FIG>, thereby facilitating desired tolerances in horizontal direction <NUM> and/or vertical direction <NUM>.

The position errors are further reduced by leveling the assembly tool relative to assembly component <NUM> (<FIG> and <FIG>) using a local positioning system that provides vertical and/or horizontal references. Additionally, there may be a third stepped terrace that is in the same plane as the pair of stepped terraces <NUM>, but which is offset horizontally from the pair of stepped terraces <NUM>. In conjunction with the pair of stepped terraces <NUM>, this third stepped terrace may provide a three-point plane on which the assembly tool rests and which the assembly tool can use as a reference when self-leveling, thereby improving the position accuracy of semiconductor dies <NUM> when ramp-stack chip package <NUM> in <FIG> is assembled.

Referring back to <FIG>, note that in order to accommodate mechanical alignment errors in vertical direction <NUM>, the height and pitch of the solder bumps or pads (such as solder pad <NUM>-<NUM> and/or solder pad <NUM>-<NUM>) and/or solder ball <NUM> may vary between at least some of semiconductor dies <NUM> along vertical direction <NUM>. For example, distance <NUM> (i.e., the position of solder pad <NUM>-<NUM> relative to a center of a saw lane for semiconductor die <NUM>-<NUM>) may be <NUM> and solder pads <NUM> may each have an <NUM> width. Furthermore, the solder balls (such as solder ball <NUM>) may have a diameter of <NUM> prior to reflowing or melting, and an approximate thickness between <NUM> and <NUM> after melting. Two or more rows of solder balls may rigidly couple ramp component <NUM> to a given semiconductor die.

<FIG> presents a block diagram illustrating a top view of assembled chip package <NUM> not falling within the scope of the claimed invention in which stack <NUM> (<FIG>) includes four semiconductor dies <NUM>. This view of chip package <NUM> illustrates that solder pads <NUM> may have non-rectangular shapes. For example, solder pads <NUM> may have oblong shapes, such as those that are <NUM> wide and <NUM> long. These solder-pad shapes on semiconductor dies <NUM> and/or ramp component <NUM> may tolerate some horizontal and/or vertical position errors.

In some embodiments, the solder pads can be moved to an edge of ramp component <NUM>. This may facilitate a perpendicular orientation (i.e., angle <NUM> in <FIG> may be <NUM>°). This configuration may facilitate a memory module in which contacts or pads associated with input/output (I/O) signal lines and power lines are at the edge of the ramp component (instead of down the 'spine'). In this way, a number of diffusion layers in the ramp component may be reduced. For example, there may be <NUM> contacts or pads along an edge of ramp component <NUM> in this memory module.

By allowing the stacking process during assembly of chip package <NUM> to be referenced to assembly component <NUM> in <FIG> and <FIG> (as opposed to the immediately preceding semiconductor die in stack <NUM> in <FIG>), this assembly component can effectively reduce horizontal and/or vertical position errors associated with mechanical variations in the sizes and thicknesses of components in chip package <NUM>. For example, vertical position errors of semiconductor dies <NUM> may each be less than ±<NUM>. Thus, assembly component <NUM> in <FIG> and <FIG> may facilitate highly accurate and high-yield assembly of chip package <NUM>. Furthermore, because this assembly component also facilitates the use of high-volume and low-cost manufacturing techniques (such as a pick-and-place machine), it can greatly reduce the cost of chip package <NUM>.

In addition, the ability to assemble low-cost, high-yield chip packages may facilitate high-performance devices. For example, a ramp-stack chip package (such as chip package <NUM>) may be included in a dual in-line memory module. For example, there may be up to <NUM> memory devices (such as dynamic random access memory or another type of memory-storage device) in the ramp-stack chip package. If needed, 'bad' or faulty memory devices can be disabled. Thus, <NUM> memory devices (out of <NUM>) may be used. Furthermore, this configuration may expose the full bandwidth of the memory devices in the memory module, such that there is little or no latency delay in accessing any of the memory devices.

Alternatively, the dual in-line memory module may include multiple fields that each can include a ramp-stack chip package. For example, there may be four ramp-stack chip packages (each of which include nine memory devices) in a dual in-line memory module.

One or more of these dual in-line memory modules (which can include one or more ramp-stack chip packages) may be coupled to a processor. For example, the processor may be coupled to the one or more dual in-line memory modules using capacitive proximity communication (PxC) of capacitively coupled signals. In turn, the processor may be mounted on a substrate using C4 solder balls.

The assembly tool has tilt compliance and the ability to move vertically, while not allowing motion in the plane of the semiconductor dies. Alternatively, a ball joint (such as a hard sphere on the end of a rod that is seated in a cup) may be used. This ball joint may provide a joint that allows for some rotation about all three rotation axes, but does not allow translation. For the assembly tool, the rod may be the mounting shaft that attaches to a pick-and-place machine, and the cup may be placed inside the pick surface so that the pivot point is as close as possible to the semiconductor die. This arrangement may allow the surface of the pick-and-place machine to tilt to meet the assembly tool, but it may not support translation. Note that the ball joint may not have any compliance in the vertical direction. However, the ball joint may allow rotation along all three rotational axes, so that the assembly tool can rotate about the mounting shaft. Yet another possibility is a spherical bearing, which is similar to the ball joint, except that instead of trapping a ball inside a small cup on the surface of the pick-and-place machine, the entire surface of the pick-and-place machine may be inside a larger spherical surface. This spherical surface may be included inside an even larger spherical surface, which may allow the two spherical surfaces to rotate relative to each other. As with the ball joint, the spherical bearing allows for the desired rotation along all three rotational axes but not the undesired translation of the assembly tool.

<FIG> presents a flow diagram illustrating a method <NUM> for assembling a chip package using assembly component <NUM> (<FIG> and <FIG>) according to the claimed invention. During this method, an adhesive is applied to a top surface of a semiconductor die in a ramp-stack chip package in which the set of semiconductor dies is arranged in a vertical stack (operation <NUM>), where the given semiconductor die in the vertical stack is offset from an adjacent semiconductor die in a plane of a set of semiconductor dies to define a stepped terrace. Then, using an assembly tool, a second semiconductor die is picked up on a top surface of the second semiconductor die (operation <NUM>). Next, a bottom surface of the second semiconductor die is placed on the adhesive on the top surface of the semiconductor die while a vertical position of an assembly tool is constrained by a given step in the assembly component having a pair of stepped terraces that are arranged on either side of the ramp-stack chip package (operation <NUM>), where steps in the pair of stepped terraces provide vertical reference positions.

There may be additional or fewer operations. For example, the stack may be assembled in pieces that include a subset of the semiconductor dies, which are subsequently combined into a full stack. Moreover, a ramp component may be rigidly mechanically coupled to the semiconductor die and the second semiconductor die, where the ramp component is positioned on one side of the vertical stack, and where the ramp component is approximately parallel to a direction along the stepped terrace, which is between a horizontal direction and a vertical direction.

Furthermore, rigidly mechanically coupling the ramp component to the semiconductor die and the second semiconductor die may involve melting solder on: the ramp component and/or the semiconductor die and the second semiconductor die. When reflowing the solder, the ramp component may be placed on the stack or vice versa. This may allow the weight of the ramp component (or the stack of semiconductor dies) to help overcome the surface tension of the solder.

Note that, when rigidly mechanically coupling the ramp component to the semiconductor die and the second semiconductor die, a compressive force may be applied in the vertical direction. This may ensure that the assembled chip package has a desired height. A compressive force may be applied along a normal to the ramp component. Either of these compressive forces may improve heat transfer within the stack, for example, by filling or reducing gaps between components in the chip package.

Additionally, the order of the operations in <FIG> may be changed, and/or two or more operations may be combined into a single operation.

Note that assembly component <NUM> (<FIG> and <FIG>) and chip package <NUM> (<FIG> and <FIG>) may include fewer components or additional components. For example, there may be breaks defined in a stack of semiconductor dies in a ramp-stack chip package, such as by not including solder pads for one or more of the semiconductor dies on the ramp component. Moreover, although these devices and systems are illustrated as having a number of discrete items, these are intended to be functional descriptions of the various features that may be present rather than structural schematics. Consequently, two or more components may be combined into a single component and/or a position of one or more components may be changed.

In <FIG> and <FIG> ramp component <NUM> may be a passive component, such as a plastic substrate with metal traces to electrically couple to semiconductor dies <NUM>. For example, ramp component <NUM> may be fabricated using injection-molded plastic. Alternatively, ramp component <NUM> may be another semiconductor die with lithographically defined wires or signal lines. Where ramp component <NUM> includes a semiconductor die, active devices, such as limit amplifiers, may be included to reduce crosstalk between the signal lines. Additionally, crosstalk may be reduced in either an active or a passive ramp component <NUM> using differential signaling.

Ramp component <NUM> may include transistors and wires that shuttle data and power signals among semiconductor dies <NUM> via solder balls (such as solder ball <NUM>). For example, ramp component <NUM> may include high-voltage signals. These signals may be stepped down for use on semiconductor dies <NUM> using: a step-down regulator (such as a capacitor-to-capacitor step-down regulator), as well as capacitor and/or inductor discrete components to couple to semiconductor dies <NUM>.

Additionally, ramp component <NUM> may include a buffer or logic chip for memory, and/or I/O connectors to external device(s) and/or system(s). For example, the I/O connectors may include one or more: ball bonds, wire bonds, edge connectors and/or PxC connectors for coupling to external devices. These I/O connectors may be on a back surface of ramp component <NUM>, and ramp component <NUM> may include one or more through-silicon vias (TSVs) that couple the I/O connectors to solder pads, such as solder pad <NUM>-<NUM>.

Ramp component <NUM> and semiconductor dies <NUM> in chip package <NUM> are mounted on an optional substrate (such as a printed circuit board or a semiconductor die). This optional substrate may include: ball bonds, wire bonds, edge connectors and/or PxC connectors for coupling to external devices. If these I/O connectors are on a back surface of the optional substrate, the optional substrate may include one or more TSVs.

While solder balls are used as an illustration of the electrical and mechanical coupling of ramp component <NUM> and semiconductor dies <NUM>, these components may be electrically and/or mechanically coupled using other techniques, such as: micro-springs, microspheres (in a ball-in-pit configuration described below), and/or an anisotropic film (such as an anisotropic elastomer film, which is sometimes referred to as an 'anisotropic conductive film').

Where components in chip packages communicate with PxC of electromagnetically coupled signals (such as PxC between: ramp component <NUM> and semiconductor dies <NUM>, ramp component <NUM> and an external device, ramp component <NUM> and optional substrate, optional substrate and semiconductor dies <NUM> and/or optional substrate and the external device), the PxC may include: communication of capacitively coupled signals (which is referred to as 'electrical proximity communication'), communication of optically coupled signals (which is referred to as 'optical proximity communication'), communication of electromagnetically coupled signals (which is referred to as 'electromagnetic proximity communication'), communication of inductively coupled signals, and/or communication of conductively coupled signals.

In general, the impedance of the resulting electrical contacts may be conductive and/or capacitive, i.e., may have a complex impedance that includes an in-phase component and/or an out-of-phase component. Regardless of the electrical contact mechanism (such as solder, micro-springs, an anisotropic layer, etc.), if the impedance associated with the contacts is conductive, conventional transmit and receive I/O circuits may be used in components in chip package <NUM>. However, for contacts having a complex (and, possibly, variable) impedance, the transmit and receive I/O circuits may be as described in <CIT>, entitled "Receive Circuit for Connectors with Variable Complex Impedance," by Robert J. Drost et al. , filed on April <NUM>, <NUM>.

Note that packaging techniques that allow some rework are more cost-effective when faced with lower semiconductor-die yields or high expense to test extensively before packaging and assembly. Therefore, where the mechanical and/or electrical coupling between semiconductor dies <NUM> and ramp component <NUM> are remateable, the yield of chip package <NUM> may be increased by allowing rework (such as replacing a bad chip that is identified during assembly, testing or burn-in). In this regard, remateable mechanical or electrical coupling should be understood to be mechanical or electrical coupling that can be established and broken repeatedly (i.e., two or more times) without requiring rework or heating (such as with solder). The remateable mechanical or electrical coupling may involve male and female components designed to couple to each other (such as components that snap together).

While <FIG> and <FIG> illustrate a particular configuration of chip package <NUM>, a number of techniques and configurations may be used to implement mechanical alignment and assembly with or without using assembly component <NUM> (<FIG> and <FIG>). For example, semiconductor dies <NUM> and/or ramp component <NUM> may be positioned relative to each other using a ball-in-pit alignment technique (and, more generally, a positive-feature-in-negative-feature alignment technique). In particular, balls may be positioned into etch pits to relatively align components, such as semiconductor dies <NUM> in stack <NUM> (<FIG>). Other examples of positive features include hemisphere-shaped bumps. However, any combination of mechanically locking positive and negative surface features on components in chip package <NUM> may be used to align and/or assemble chip package <NUM>.

Referring to <FIG>, as noted previously optional heat-spreading material <NUM> (and, more generally, an intermediate material between semiconductor dies <NUM> that has a high thermal conductivity) may help remove heat generated during operation of circuits on one or more semiconductor dies <NUM> and/or ramp component <NUM> (<FIG> and <FIG>). This thermal management may include any of the following thermal paths: a first thermal path in a plane of semiconductor dies <NUM>; a second thermal path in a plane of adhesive layers <NUM>; and/or a third thermal path in a plane of optional heat-spreading material <NUM>. In particular, the thermal flux associated with these thermal paths may be managed independently of each other via thermal coupling at an edge of the chip package. Note that this thermal management may include the use of: phase change cooling, immersion cooling, and/or a cold plate. Also note that the thermal flux associated with the first thermal path that diffuses through the cross-sectional area at the edge of the chip package is a function of nominal thickness <NUM>. Thus, the thermal management may be different in chip packages with larger or smaller nominal thicknesses of semiconductor dies <NUM>.

Claim 1:
An assembly component, comprising:
a pair of stepped terraces (<NUM>-<NUM>, <NUM>-<NUM>), for arrangement on either side of a ramp-stack chip package (<NUM>) that is being assembled, having a vertical stack of steps in which a given step is offset from an adjacent step in a plane of the steps to define the pair of stepped terraces,
wherein the steps in the pair of stepped terraces (<NUM>-<NUM>, <NUM>-<NUM>) are configured to provide vertical reference positions for assembly of the ramp-stack chip package (<NUM>) to constrain vertical positions of an assembly tool (<NUM>) during assembly of the ramp-stack chip package (<NUM>);
wherein the assembly tool (<NUM>) is configured to, during the assembly of a ramp-stack chip package (<NUM>), be mechanically coupled to a top surface of a given semiconductor die of a set of semiconductor dies (<NUM>) in a ramp-stack chip package arranged in a vertical stack in which the given semiconductor die is offset from an adjacent semiconductor die in a plane of the set of semiconductor dies to define a stepped terrace, and in which a bottom surface of the given semiconductor die is mechanically coupled to the ramp-stack chip package; and
wherein the assembly tool (<NUM>) comprises one or more rigid wings (<NUM>-<NUM>, <NUM>-<NUM>) placed against the steps in the pair of stepped terraces (<NUM>-<NUM>, <NUM>-<NUM>), wherein the one or more rigid wings (<NUM>-<NUM>, <NUM>-<NUM>) overhang the given semiconductor die on one or more edges of the given semiconductor die such that the assembly tool (<NUM>) is suitable for constraining the vertical position of the top surface of the given semiconductor die by the steps in the pair of stepped terraces (<NUM>-<NUM>, <NUM>-<NUM>).