Patent Description:
The invention provides a memory arrangement for a fluid ejection die according to claim <NUM>, a fluid ejection die according to claim <NUM> and a fluid cartridge according to claim <NUM>.

The following detailed description references the figures, wherein:.

Memory banks may be used in a fluid ejection die, such as a print head, to store various information related to the fluid ejection die, such as identification information, serial numbers, security information, feature enhancement information, and the like. Since a memory bank includes a plurality of memory units, in order to read or write data to a memory unit in the memory bank, the memory unit is to be selected prior to the reading or writing operation. As the memory units are arranged in rows and columns, a memory unit can be selected by selecting the row and column in which the memory unit is disposed. The row and the column corresponding to the memory unit may be selected by providing a set of select signals, such as a row select signal, which is applied to the row corresponding to the memory unit, and a column select signal, which is applied to the column corresponding to the memory unit.

In cases where a large amount of data is to be stored, several memory banks may be used. In such a case, in order to access a memory unit for reading or writing, in addition to selecting the row and column corresponding to the memory unit, the memory bank corresponding to the memory unit is also to be selected. Accordingly, a bank select signal is also provided to the memory bank corresponding to the memory unit to be selected.

The various select signals may be generated by one or more registers. Thus, the selection of a memory unit may be performed by one or more registers, which generate the row select signal to select a row of a memory unit, the column select signal to select a column of the memory unit, and a bank select signal to select the bank in which the memory unit is present.

The present invention relates to aspects of accessing memory units in a memory bank. Implementations of the present invention provide an efficient layout that minimizes the amount of space consumed, for example, in a fluid ejection die, for implementing the various select registers.

In accordance with an example implementation of the present subject a bank select transistor is provided common to a plurality of memory units present in a memory bank. The plurality of memory units in the memory bank are arranged in the form of a matrix having a plurality of rows and columns. The bank select transistor facilitates accessing a memory unit of the plurality of memory units in the memory bank based on a bank select signal, which may be provided by a select register.

In accordance with an example implementation of the present invention, a plurality of memory banks is provided in a device, such as a fluid ejection die. Each memory bank is provided with a plurality of memory units and a bank select transistor common to the plurality of memory units. The bank select transistor in a memory bank receives the bank select signal for facilitating access to a memory unit in the memory bank. The bank select transistor may be connected to each memory unit through a row select transistor and a column select transistor connected to the memory unit, and can facilitate access to a memory unit of the plurality of memory units upon receiving the bank select signal.

Since the bank select transistor is common to a plurality of memory units in the memory bank, the access of the plurality of memory units can be controlled using a single bank select signal, which is provided to the bank select transistor. Further, by provisioning a single bank select transistor commonly to a plurality of memory units in the memory bank, instead of provisioning one bank select transistor per memory unit, the present invention considerably reduces the number of transistors to be provisioned in a memory bank to facilitate access to the memory units. This reduces the size of the device employing the memory banks. Therefore, the aspects of the present invention can be used in space constrained devices, such as print heads, for storing a large amount of data in a limited amount of space. The reduction in the number of transistors provisioned also enables having more memory units and memory banks in the device, thereby increasing the number of functions performed by the device.

The following description refers to the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the following description to refer to the same or similar parts. While several examples are described in the description, modifications, adaptations, and other implementations are possible. Accordingly, the following detailed description does not limit the disclosed examples. Instead, the proper scope of the disclosed examples may be defined by the appended claims.

Example implementations of the present invention are described with regard to memory banks used in fluid ejection dies, such as print heads. Although not described, it will be understood that the implementations of the present invention can be used with other types of fluid ejection dies where a memory unit in one of several memory banks is to be accessed.

<FIG> illustrates a fluid ejection die <NUM>, according to an example implementation of the present invention. Example of the fluid ejection die <NUM> includes, but not limited to, a print head, such as a thermal inkjet (TIJ) print head and a piezoelectric inkjet print head. The fluid ejection die <NUM> ejects drops of fluid, such as ink and liquid toner, through a plurality of orifices or nozzles <NUM> toward a print medium (not shown in <FIG>), so as to print onto the print medium. The print medium can be any type of suitable sheet material, such as paper, card stock, fabric, and the like. Typically, the nozzles <NUM> are arranged in one or more columns or arrays such that properly sequenced ejection of fluid from the nozzles causes characters, symbols, and/or other graphics or images to be printed upon print medium.

The memory bank <NUM> also includes a plurality of memory units <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n, collectively referred to as memory units <NUM>. The memory units <NUM> are arranged in the memory bank <NUM> in the form of a matrix having a plurality of rows and columns.

Each of the memory units <NUM> is capable of storing data. The data that can be stored in a memory unit may be, for example, one bit of data, i.e., logic '<NUM>' or logic '<NUM>'. Further, the data stored in the memory unit can be retrieved. In other words, each memory unit can be written to or read from. A memory unit can be accessed for writing data or reading data. In order to facilitate accessing a memory unit of the memory units <NUM>, the fluid ejection die <NUM> includes a bank select transistor <NUM>. Although the bank select transistor <NUM> is shown to be disposed outside of the memory bank <NUM>, in an implementation, the bank select transistor <NUM> is disposed within the memory bank <NUM>.

The bank select transistor <NUM> is common to the memory units <NUM>. The bank select transistor <NUM> can be made common to the memory units <NUM> by connecting the bank select transistor <NUM> with each memory unit of the memory units <NUM>. Here, the bank select transistor <NUM> is shown connected to the memory units <NUM> through arrows to indicate that the bank select transistor <NUM> can be connected to the memory units <NUM> either directly or indirectly. The connection of the bank select transistor <NUM> with the memory units <NUM> is explained with reference to <FIG>. The bank select transistor <NUM> receives a bank select signal <NUM>. Based on the bank select signal <NUM>, the bank select transistor <NUM> facilitates accessing memory units in the memory bank <NUM>.

In an implementation, the memory units <NUM> are electrically programmable read only memory (EM) memory units. The term "EM memory unit", as used in the present specification, is to be broadly understood as any programmable read-only memory that retains its data when its power supply is switched off. In an example, the EM is an erasable programmable read only memory (EPROM). In another example, the EM is an electrically erasable programmable read only memory (EEPROM).

Although <FIG> illustrates a single memory bank <NUM> in the fluid ejection die <NUM>, the fluid ejection die <NUM> can include a plurality of memory banks. Accordingly, each memory bank can have a corresponding bank select transistor, which is common to a plurality of memory units in that memory bank.

The bank select transistor <NUM> receives the bank select signal <NUM> from a bank select register (not shown in <FIG>), which generates the bank select signal <NUM> based on the memory bank from which a memory unit is to be accessed. Each memory unit can also have a row select transistor and a column select transistor (both not shown in <FIG>) associated with it. A memory unit can be accessed when the row select transistor and the column select transistor connected to it receives a row select signal and a column select signal, respectively, and the bank select transistor <NUM> receives the bank select signal <NUM>. By providing a common bank select transistor <NUM> for the plurality of memory units <NUM>, instead of providing a separate bank select transistor corresponding to each memory unit, considerable space saving is achieved in the fluid ejection die <NUM>.

The above described implementations will be explained in greater detail with reference to the subsequent paragraphs.

<FIG> illustrates a fluid cartridge <NUM>, according to an example implementation of the present invention. The fluid cartridge <NUM> is more generally a fluid-jet precision-dispensing device or fluid ejector structure that precisely dispenses fluid, such as ink and liquid toner. In an example, the fluid cartridge <NUM> may be a print cartridge, such as a single color ink cartridge for a fluid-jet printer.

While the present description describes generally an inkjet-printing cartridge that ejects ink onto media, examples of the present specification may not be limited to inkjet printing cartridges alone. In general, examples of the present specification pertain to any type of fluid-jet precision-dispensing or ejection devices that dispense a fluid. The term fluid is meant to be broadly interpreted as any substance that deforms under an applied force. Examples of fluids, therefore, include liquids and gases. A fluid-jet precision- dispensing device is a device in which printing, or dispensing, of the fluid in question is achieved by precisely printing or dispensing in accurately specified locations, with or without making a particular image on that which is being printed or dispensed on. Thus, for purposes of explanation, a print cartridge or ink cartridge will be described. However, it will be understood that any type of fluid cartridge may be used with the principles described herein.

In an implementation, the fluid cartridge <NUM> includes a fluid reservoir <NUM> to store a fluid, such as ink and liquid toner, and a fluid ejection die <NUM>, such as the fluid ejection die <NUM>, that is coupled to the fluid reservoir <NUM>. When the fluid cartridge <NUM> is a print cartridge, the fluid stored in the fluid reservoir <NUM> may be referred to as a print material, and the fluid reservoir <NUM> may be referred to as a print material reservoir. The fluid stored in the fluid reservoir <NUM> can flow to the fluid ejection die <NUM>, which ejects drops of the fluid through a plurality of nozzles <NUM> toward a print medium.

In an example, the fluid ejection die <NUM> includes a plurality of EM banks <NUM>-<NUM>,. , <NUM>-n, collectively referred to as EM banks <NUM>. An EM bank refers to any combination of any number of matrices of EM memory units. The EM banks <NUM> can be used to store various information about a device on which they are used. For example, if the fluid ejection die <NUM> is a print head, the information stored, may be, identification information, such as identification of the print head, type of ink cartridge, and kind of ink contained in the ink cartridge, serial numbers, security information, feature enhancement information, and the like. Based on the information stored in the EM banks <NUM>, a printer controller (not shown in <FIG>) in the printer (not shown in <FIG>) that includes the fluid ejection die <NUM> may take one or more actions, such as altering printing routines to maintain image quality.

Each EM bank includes a matrix of plurality of EM memory units. A matrix of memory units refers to an arrangement of memory units in a plurality of rows and columns. For instance, the EM bank <NUM>-<NUM> includes EM memory units <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n in the form of a matrix. Similarly, the EM bank <NUM>-n includes EM memory units <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n in the form of a matrix.

In an example, an EM bank includes <NUM> memory units. In an example, a matrix of memory units includes memory units arranged in eight rows and eight columns, i.e., the matrix of memory units is an <NUM> X <NUM> arrangement of memory units. In another example, the matrix of memory units is an <NUM> X <NUM> arrangement of memory units, i.e., having memory units arranged in eight rows and four columns. In yet other examples, other arrangements, such as <NUM> X <NUM>, <NUM> X <NUM>, and the like may be used.

In addition to the matrix of plurality of EM memory units, each EM bank also includes a bank select transistor. For instance, the EM bank <NUM>-<NUM> includes a bank select transistor <NUM> and the EM bank <NUM>-n includes a bank select transistor <NUM>. The bank select transistor in an EM bank is common to the plurality of EM memory units. In order to make the bank select transistor common to the plurality of EM memory units, the bank select transistor may be connected to each memory unit of the plurality of EM memory units. For instance, referring to <FIG>, the bank select transistor <NUM> can be connected to each EM memory unit, i.e., to EM memory unit <NUM>-<NUM>, EM memory unit <NUM>-<NUM>,. , EM memory unit <NUM>-n, of the EM memory units <NUM>. The connection of the bank select transistor with the plurality of EM memory units is explained with reference to <FIG>.

Each bank select transistor includes a gate terminal. The gate terminal can be used to receive a bank select signal, which is a signal used to select a particular EM bank. When the bank select transistor receives the bank select signal at its gate terminal, the bank select transistor turns on. Since the bank select transistor is common to the matrix of plurality of EM memory units, the turning on of the bank select transistor facilitates accessing an EM memory unit in the matrix for reading or writing.

Therefore, referring back to <FIG>, when the bank select transistor <NUM> receives a bank select signal <NUM> at its gate terminal, accessing the EM memory units <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n is facilitated. Similarly, when the bank select transistor <NUM> receives the bank select signal <NUM> at its gate terminal, accessing the EM memory units <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n is facilitated. The bank select transistors in the different EM banks may receive the bank select signal <NUM> at different points of time, so that, at any point of time, access to the EM memory units in a single EM bank alone is facilitated. The generation of the bank select signal is explained with reference to <FIG>. In an implementation, the bank select transistor <NUM> is connected to each EM memory unit through a row select transistor and a column select transistor connected to the EM memory unit.

<FIG> illustrates a print cartridge <NUM>, according to an example implementation of the present invention. The print cartridge <NUM> may be similar to the fluid cartridge <NUM>. A component of the print cartridge <NUM> that corresponds to a component of the fluid cartridge <NUM> is denoted by a reference numeral that is <NUM> greater than the corresponding component of the fluid cartridge <NUM>. For example, the nozzles <NUM> in the print cartridge <NUM> correspond to nozzles <NUM> in the fluid cartridge <NUM>. Similar to the fluid cartridge <NUM>, the print cartridge <NUM> also may include n EM banks. However, a single EM bank <NUM>-<NUM> is shown for clarity. Similarly, the EM bank <NUM>-<NUM> includes EM memory units in a plurality of rows and columns, although a single column of EM memory units is shown.

The EM unit <NUM>-<NUM> is connected to the bank select transistor <NUM> through a column select transistor <NUM> and a row select transistor <NUM>. Similarly, the EM unit <NUM>-m is connected to the bank select transistor <NUM> through a column select transistor <NUM> and a row select transistor <NUM>. The connection of the bank select transistor to a matrix of a plurality of EM memory units in a memory bank, through row select and column select transistors, is explained with reference to <FIG>. A matrix of a plurality of EM memory units may be interchangeably referred to as a matrix of EM memory units.

<FIG> illustrates connection of a bank select transistor <NUM> to a matrix <NUM> of EM memory units in a memory bank <NUM>, according to an example implementation of the present invention. The matrix <NUM> of EM memory units includes a plurality of EM memory units <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-m, <NUM>-n, collectively referred to as EM memory units <NUM>. Although the matrix <NUM> of EM memory units is shown to include EM memory units in <NUM> rows and <NUM> columns, it is to be understood that a matrix may include any number of rows and columns of EM memory units. In an example, the matrix <NUM> is an <NUM> X <NUM> matrix of EM memory units.

The EM memory unit <NUM>-<NUM> includes a floating gate transistor <NUM>. A drain terminal of the floating gate transistor <NUM> is connected to one terminal of a resistor <NUM>. The other terminal of the resistor <NUM> is connected to an identification (ID) line <NUM>, through which the floating gate transistor <NUM> can be accessed for reading or writing. A source terminal of the floating gate transistor <NUM> is connected to a drain terminal of a column select transistor <NUM>. A source terminal of the column select transistor <NUM> is connected to a drain terminal of a row select transistor <NUM>. In this manner, the floating gate transistor <NUM>, the column select transistor <NUM>, and the row select transistor <NUM> are connected together. Such a connection of the floating gate transistor <NUM>, the column select transistor <NUM>, and the row select transistor <NUM> may be referred to as a series connection. Further, a source terminal of the row select transistor <NUM> is connected to a drain terminal of the bank select transistor <NUM>. This way, the bank select transistor <NUM> is connected to the EM memory unit <NUM>-<NUM>. Such a connection of the bank select transistor <NUM> with the EM memory unit <NUM>-<NUM> (through the column select transistor <NUM> and the row select transistor <NUM>) may be referred to as a series connection. A source terminal of the bank select transistor <NUM> may be connected to a reference voltage, for example, ground <NUM>.

The floating gate transistor <NUM>, the column select transistor <NUM>, and the row select transistor <NUM> can be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). In an example, the floating gate transistor <NUM>, the column select transistor <NUM>, and the row select transistor <NUM> are N-type (NMOS) devices. In other examples, the floating gate transistor <NUM>, the column select transistor <NUM>, and the row select transistor <NUM> are PMOS devices or CMOS devices. In an implementation, the bank select transistor <NUM> is a MOSFET, and may be an NMOS device.

In an implementation, each EM memory unit includes a corresponding column select transistor. In other words, a floating gate transistor in an EM memory unit is connected to a column select transistor dedicated to the EM memory unit. For instance, the column select transistor <NUM> is dedicated to the EM memory unit <NUM>-<NUM>, and is not connected to any floating gate transistor other than the floating gate transistor <NUM>. However, a row select transistor is common to all EM memory units in a particular row of the matrix of EM memory units. In other words, a row select transistor corresponds to a row of a matrix of EM memory units. Referring to <FIG>, the row select transistor <NUM> corresponds to the first row of EM memory units in the matrix <NUM>. Therefore, the row select transistor <NUM> is connected to each column select transistor in the first row of the matrix <NUM>. Although the row select transistor is shown to correspond to an entire row of EM memory units, while the column select transistor corresponds to one EM memory unit, in an implementation, the column select transistor can correspond to an entire column of EM memory units, while the row select transistor corresponds to one EM memory unit. In another implementation, each EM memory unit may have a row select transistor and column select transistor corresponding to it.

The other EM memory units <NUM>-<NUM>,. , <NUM>-m, <NUM>-n may be identical to the EM memory unit <NUM>-<NUM>, and include similar components and connections as the EM memory unit <NUM>-<NUM>. Therefore, the source terminal of the floating gate transistor of each EM memory unit is connected to the drain terminal of the column select transistor corresponding to that EM memory unit, and the source terminal of the column select transistor is connected to the drain terminal of the row select transistor corresponding to the row having that EM memory unit. Further, the source terminal of the row select transistor corresponding to each row in the matrix <NUM> is connected to the drain terminal of the bank select transistor <NUM>. This way, the bank select transistor <NUM> is connected with each EM memory unit in the matrix <NUM> of EM memory units. In other words, such a connection enables making the bank select transistor <NUM> common to the plurality of EM memory units <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n in the matrix <NUM>.

Although providing a common bank select transistor to a matrix of EM memory units is illustrated with the help of a series connection of the bank select transistor with the other transistors in the matrix, it will be understood that any other method of making the bank select transistor a common one to the matrix may be used.

The floating gate transistor <NUM> includes two gate terminals that are separated from one another by an oxide layer, which acts as a dielectric. One of the gates is called a floating gate and the other is called a control gate. The floating gate's link to the ID line <NUM> is through the control gate. When the gate terminals of all of the floating gate transistor <NUM>, the column select transistor <NUM>, and the row select transistor <NUM> are open, i.e., not supplied with a voltage signal, the EM memory unit <NUM>-<NUM> stores no data, giving it a value of logic '<NUM>' (low resistance state). In such a case, the floating gate has no charge, which causes the threshold voltage of the EM memory unit <NUM>-<NUM> to be low. In other words, in this case, the EM memory unit <NUM>-<NUM> stores a value of logic '<NUM>'.

To change the value stored in the EM memory unit <NUM>-<NUM> to logic "I' (high resistance state), the column select transistor <NUM> and the row select transistor <NUM> are to be turned on by applying a voltage signal at their respective gate terminals. Thereafter, a programming voltage is to be applied to the control gate and drain terminal of the floating gate transistor <NUM>. The programming voltage may be applied through the ID line <NUM>. The programming voltage draws excited electrons to the floating gate, thereby increasing the threshold voltage. The excited electrons are pushed through and trapped on the other side of the thin oxide layer, giving it a negative charge. These negatively charged electrons act as a barrier between the control gate and the floating gate, thereby changing the value stored to the high resistance state, i.e., logic '<NUM>'. The application of the programming voltage to change the value stored is referred to as writing data.

In order to read the value stored in the EM memory unit <NUM>-<NUM>, first, the column select transistor <NUM> and the row select transistor <NUM> are to be turned on. Thereafter, the threshold voltage of the EM memory unit <NUM>-<NUM> can be sensed. If the threshold voltage is low, for example, below a threshold level, the EM memory unit <NUM>-<NUM> is said to have a value of logic '<NUM>'. If the threshold voltage is high (i.e., above the threshold level), the EM memory unit <NUM>-<NUM> is said to have a value of logic '<NUM>'. The threshold voltage may be sensed using the ID line <NUM>. Since the ID line <NUM> is connected to all the EM memory units in the matrix <NUM>, all the EM memory units can be written to and read from through the ID line <NUM>.

As mentioned earlier, the turning on of the column select transistor <NUM> and the row select transistor <NUM> can be achieved by supplying voltage signals at their respective gate terminals. The voltage signal applied at the gate terminal of the column select transistor <NUM> is referred to as a column select signal <NUM> and the voltage signal applied at the gate terminal of the row select transistor <NUM> is referred to as a row select signal <NUM>. In an implementation, the gate terminals of all column select transistors in a single column of the matrix <NUM> are connected together, so that the column select signal <NUM> for that column can turn on all column select transistors in that column. For example, the gate terminal of the column select transistor <NUM> and the gate terminal of the column select transistor <NUM>, corresponding to the EM memory unit <NUM>-m, is connected together, as both EM memory units <NUM>-<NUM> and <NUM>-m are on the first column of the matrix <NUM>.

As explained earlier, the bank select transistor <NUM> is connected to all the row select transistors in the matrix <NUM>. Therefore, in order to write data to or read data from an EM memory unit in the matrix <NUM>, the bank select transistor <NUM> is to be turned on by providing the bank select signal <NUM> to the bank select transistor <NUM>. Further, in order to prevent data being written to or read from any EM memory unit in the matrix <NUM>, the bank select signal <NUM> may not be provided to the bank select transistor <NUM>. In short, the accessing of an EM memory unit in the matrix <NUM> can be controlled by providing and not providing the bank select signal <NUM> to the bank select transistor <NUM>.

The provision of bank select transistor <NUM> as a common one to all the EM memory units in the matrix <NUM>, instead of connection of an individual bank select transistor in each EM memory unit, enables reducing the size of the matrix <NUM>, and consequently, the EM bank <NUM>. In an example, provisioning a common bank select transistor for a plurality of EM memory units enables disposing <NUM> EM memory units in a space that could have accommodated <NUM> EM memory units if each EM memory unit had a dedicated bank select transistor. Thus, the present invention enables accommodating more number of EM memory units in a limited space. Therefore, the print head utilizing the techniques of the present invention can accommodate a large number of EM memory units, even if it has limited space availability.

<FIG> illustrates the layout of an EM bank <NUM>, according to an example implementation of the present invention. As explained earlier, the EM bank <NUM> can include a matrix of EM memory units <NUM>-<NUM>, <NUM>-<NUM>,.

The EM memory unit <NUM>-<NUM> includes a floating gate transistor <NUM> to store a bit of data. The floating gate transistor <NUM> is surrounded by a column select transistor <NUM>. Further, a row select transistor <NUM> is disposed around the column select transistor <NUM>. As explained earlier, in this implementation, since the row select transistor <NUM> corresponds to the entire row having the EM memory unit <NUM>-<NUM>, the row select transistor <NUM> surrounds all the column select transistors in in the row having the EM memory unit <NUM>-<NUM>. Further, as explained earlier, the gate terminals of all column select transistors in one column of matrix of EM memory units are connected together. Such a connection is illustrated by a jumper <NUM>, which connects the gate terminal of the column select transistor <NUM> with a column select transistor <NUM> in the same column and next row.

A bank select transistor <NUM> is disposed around the matrix of the EM memory units <NUM>-<NUM>, <NUM>-<NUM>,. Such a placement of the bank select transistor <NUM> facilitates connecting it commonly to all the row select transistors in the matrix. Further, such a placement enables provisioning a large-sized transistor as the bank select transistor <NUM>. The large size of the bank select transistor <NUM> ensures that it has a small resistance. Further, the large size also enables the bank select transistor <NUM> to have a high fringe capacitance. The high fringe capacitance improves the charging efficiency of the bank select transistor <NUM>, which, in turn, increases voltage at the gate terminal (Vg) of the bank select transistor <NUM>. A higher Vg reduces the resistance of the bank select transistor <NUM>. Therefore, the additional resistance introduced in each EM memory unit due to the connection of the bank select transistor <NUM> is minimal. In other words, the overall series turn-on resistance (Ron) of an EM memory unit is small. The small value of Ron increases the programming efficiency of the EM memory unit. In other words, since Ron is small, a significant portion of the programming voltage applied to the EM memory unit is used to program the floating gate transistor in the EM memory unit.

In an implementation, the EM memory units at a same height and separated widthwise (for example, <NUM>-<NUM> and <NUM>-<NUM>) form a row of EM memory units and the EM memory units that are vertically dispersed, i.e., one below another (for example, <NUM>-<NUM> and <NUM>-i) form a column of EM memory units. Such an arrangement of the EM memory units may be referred to as a vertical column orientation, as the columns are vertical in orientation. However, in another implementation, the EM memory units at the same height form a column of the matrix and the EM memory units one below another form a row of the matrix. In other words, a row select transistor corresponding to a row can be disposed around all the EM memory units one below another, and the gate terminals of all the column select transistors at the same height can be connected together. Such an arrangement of the EM memory units may be referred to as a horizontal column orientation.

Although <FIG> illustrates a single matrix of EM memory units in the memory bank <NUM>, however, a memory bank may include a plurality of matrices of EM memory units. A memory bank may include a plurality of matrices of EM memory units if a die, for example, a print head die, on which the memory bank is to be accommodated does not have sufficient dimensions to accommodate all EM memory units of the memory bank as a single matrix. For instance, if the EM bank <NUM>, which has EM memory units in the vertical column orientation, is to include <NUM> EM memory units, they can be arranged as a single <NUM> X <NUM> matrix of EM memory units if the print head die has sufficient length to accommodate eight rows of EM memory units and sufficient width to accommodate eight columns of EM memory units. However, if the print head die does not have sufficient width to accommodate eight columns of EM memory units, but has sufficient length to include sixteen rows of EM memory units, the <NUM> EM memory units in the memory bank may be arranged as two <NUM> X <NUM> matrices of EM memory units one below another. Similarly, if an EM bank has a horizontal column orientation and is to include <NUM> EM memory units, and if the print head die does not have sufficient width to accommodate eight rows of EM memory units, but has sufficient length to include sixteen columns of EM memory units, the <NUM> EM memory units in the memory bank may be arranged as two <NUM> X <NUM> matrices of EM memory units one below another. Such arrangements of the EM banks having a plurality of matrices with different number of rows and columns to account for a limited width of the die is known as a slim EM layout, as these arrangements enable provisioning a 'slimmer' EM bank. On the other hand, the arrangement of the EM banks having a single matrix having the same number of rows and columns, such as an <NUM> X <NUM> matrix, may be referred to as a wide EM layout. The available length and width on the fluid ejection die to accommodate EM memory units is known as available silicon (Si) real estate of a device. In an example, an EM bank having horizontally oriented EM memory units arranged as two <NUM> X <NUM> matrices one below another has a length of <NUM> and a width of <NUM>. In another example, an EM bank of the wide EM layout having one <NUM> X <NUM> matrix arranged has a length of <NUM> and a width of <NUM>. The arrangement of a plurality of matrices of EM memory units in an EM bank is explained with reference to <FIG>.

<FIG> illustrates an EM bank <NUM> having a plurality of matrices <NUM>, <NUM> of EM memory units, according to an example implementation of the present invention. The matrix <NUM> of EM memory units and the matrix <NUM> of EM memory units may be referred to as a first matrix of EM memory units and second matrix of EM memory units, respectively. The EM memory units in the first matrix <NUM> of EM memory units may be referred to as a first plurality of EM memory units. Similarly, the EM memory units in the second matrix <NUM> of EM memory units may be referred to as a second plurality of EM memory units. Although the first matrix <NUM> and the second matrix <NUM> are shown to include EM memory units in two rows and one column, however, the matrix <NUM> and the second matrix <NUM> may include any number of rows and columns of EM memory units. For example, the first matrix <NUM> and the second matrix <NUM> may each include eight rows and four columns (<NUM> X <NUM>) of EM memory units in vertical column orientation. In another example, the first matrix <NUM> and the second matrix <NUM> may each include four rows and eight columns (<NUM> X <NUM>) of EM memory units in horizontal column orientation. In an implementation, the first matrix <NUM> and the second matrix <NUM> include the same number of rows of EM memory units and also the same number of columns of EM memory units.

Although the first matrix <NUM> and the second matrix <NUM> of EM memory units are shown to be arranged side-by-side in the memory bank <NUM>, however, in an implementation, the second matrix <NUM> may be arranged below the first matrix <NUM>. For example, the first matrix <NUM> and the second matrix <NUM> may be <NUM> X <NUM> matrices of vertical column orientation or <NUM> X <NUM> matrices of horizontal column orientation arranged one below another. As mentioned earlier, such an arrangement of the first matrix <NUM> and the second matrix <NUM> of the EM memory units enables accommodating the memory bank <NUM> on a fluid ejection die, such as a print head, having lesser width.

In an implementation, each matrix in the EM bank <NUM> includes a dedicated bank select transistor. In other words, a separate bank select transistor is connected to the plurality of row select transistors present in a single matrix alone. Referring back to <FIG>, a bank select transistor <NUM>, also referred to as a first bank select transistor, is connected commonly to the row select transistors in the first matrix <NUM> alone, while a second bank select transistor <NUM> is connected to the row select transistors in the second matrix <NUM> alone. It will be understood that, if the EM bank <NUM> includes additional matrices of EM memory units, the memory bank <NUM> can include a separate bank select transistor for each additional matrix of EM memory units. For example, if the EM bank <NUM> includes four <NUM> X <NUM> matrices of EM memory units, the EM bank <NUM> can include four bank select transistors, each connected to the row select transistors in one matrix.

As illustrated in <FIG>, the gate terminals of the first bank select transistor <NUM> and the second bank select transistor <NUM> are connected together, so that they can receive the bank select signal <NUM> simultaneously. Therefore, the turn-on of both the first bank select transistor <NUM> and the second bank select transistor <NUM> are controlled together based on the bank select signal <NUM>. The provisioning of a separate bank select transistor for each matrix of EM memory units and their connecting their gate terminals together enables utilizing the techniques of the present invention in slim EM layout as well. Therefore, the techniques of the present invention can be utilized in print heads having fluid ejection dies of lesser width. Further, since the bank select transistors of the plurality of matrices are connected together, the effective size of the bank select transistor increases. This further increases the fringe capacitance, thereby increasing Vg and reducing resistance. In an example, when the matrix of EM memory units is an <NUM> X <NUM> matrix, the bank select transistor <NUM> has a width-to-length (W/L) ratio of <NUM>/<NUM>. In an example, when the matrix of EM memory units is an <NUM> X <NUM> matrix, the bank select transistor <NUM> has a width-to-length (W/L) ratio of <NUM>/<NUM>.

When the first bank select transistor <NUM> and the second bank select transistor <NUM> are supplied with the bank select signal <NUM>, data can be read from or written to an EM memory unit in the first matrix <NUM> or the second matrix <NUM>, provided the row select transistor corresponding to the row of that EM memory unit and the column select transistor corresponding to that EM memory unit are turned on by providing row select signal and column select signal to their respective gate terminals. For example, in order to write data to the EM memory unit <NUM>-<NUM> or to read data from it, column select signal <NUM> is to be applied to the gate terminal of the column select transistor <NUM> and the row select signal <NUM> is to be applied to the gate terminal of the row select transistor <NUM>. The column select signal <NUM>, the row select signal <NUM>, and the bank select signal <NUM> may be generated by registers. In an implementation, the column select signal <NUM> is generated by a column select register, the row select signal <NUM> is generated by a row select register, and the bank select signal <NUM> is generated by a bank select register.

<FIG> illustrates a column select register <NUM>, a row select register <NUM>, and a bank select register <NUM> for generation of column select signal, row select signal, and bank select signal respectively, according to an example implementation of the present invention. Each of the column select register <NUM>, the row select register <NUM>, and the bank select register <NUM> may be a shift register, for example, a serial-in parallel-out shift register. If the column select register <NUM>, the row select register <NUM>, and the bank select register <NUM> are shift registers, they may be interchangeably referred to as the column select shift register <NUM>, the row select shift register <NUM>, and the bank select shift register <NUM> respectively. Further, the column select shift register <NUM>, the row select shift register <NUM>, and the bank select shift register <NUM> may be collectively referred to as select shift registers. The select shift registers are connected to several memory banks in the device, for example print head memory device, that accommodates the memory banks. For example, the select shift registers are connected to memory banks <NUM>-<NUM>, <NUM>-<NUM>,.

In an implementation, each of the select shift registers includes a cascade of flip-flop circuits with two stable states sharing a common time clock. Each flip-flop circuit can be connected to the data input of the next flip-flop in the cascade, resulting in a circuit that shifts a stored bit array by shifting in the data received at its input and shifting out the last bit in the array at each transition of a clock input. Each flip-flop circuit of a select shift register may be referred to as a stage. The select shift registers can include any number of stages. In an example, each of the select shift registers includes eight stages.

As mentioned earlier, the column select shift register <NUM> generates a column select signal, which can be used to select all EM memory units in a single column of a matrix of EM memory units. For this, as explained earlier, the gate terminals of column select transistors of all EM memory units in a single column are connected together. Therefore, when the column select signal is provided to a given column of a matrix of EM memory units, the column select transistors in all EM memory units in the column are turned on.

The column select shift register <NUM> can provide column select signals to different columns of EM memory units at different points of time, so that at any point a single column of EM memory units is selected. Since the column select shift register <NUM> is connected to several EM banks <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n (collectively referred to as EM banks <NUM>), the column select signal for a given column is provided to the corresponding column in all the EM banks <NUM>. For instance, a column select signal to select EM memory units in the first column of matrix of EM memory units is provided to the first column of each of the several EM banks <NUM>.

In an implementation, the column select signal for each column of a matrix of EM memory units is generated by a different stage of the column select shift register <NUM>. Therefore, the number of stages in the column select shift register <NUM> may be same as the number of columns in the matrices of EM memory units. Further, if each EM bank has more than one matrix of EM memory units having more columns than rows, for example, two <NUM> X <NUM> matrices of EM memory units, the column select signal for a given column is provided to the corresponding column in all the matrices. Similarly, if each EM bank has more than one matrix having more rows than columns, the number of stages in the column select shift register <NUM> may be a sum of the number of columns in each of the matrix. For example, if the EM bank has two <NUM> X <NUM> matrices of EM memory units, the column select shift register <NUM> includes eight (<NUM>+<NUM>) stages, so that all eight columns can be provided with different column select signals.

The row select shift register <NUM> generates a row select signal, which can be used to select all EM memory units in a single row of a matrix of EM memory units. For this, the row select signal can be provided at the gate terminal of the row select transistor corresponding to a row of EM memory units. The row select shift register <NUM> can provide row select signal to different rows of EM memory units at different points of time, so that at any point of time, a single row of EM memory units is selected. Since the row select shift register <NUM> is connected to several EM banks <NUM>, the row select signal for a given row is provided to the corresponding row in all the EM banks <NUM>. For instance, a row select signal to select EM memory units in the second row of matrix of EM memory units is provided to the second row of each of the several EM banks <NUM>.

In an implementation, the row select signal for each row of a matrix of EM memory units is generated by a different stage of the row select shift register <NUM>. Therefore, the number of stages in the row select shift register <NUM> may be same as the number of rows in the matrices of EM memory units. Further, if each EM bank has more than one matrix of EM memory units having more rows than columns, for example, two <NUM> X <NUM> matrices of EM memory units, the row select signal for a given row can be provided to the corresponding row in all the matrices. Similarly, if each EM bank has more than one matrix of EM memory units having more columns than rows, the number of stages in the row select shift register <NUM> may be a sum of the number of rows in each of the matrix. For example, if the EM bank has two <NUM> X <NUM> matrices of EM memory units, the row select shift register <NUM> includes eight (<NUM>+<NUM>) stages, so that all eight rows can be provided with different row select signals.

In an example, each EM bank includes one EM bank having EM memory units in eight rows and eight columns. In another example, each EM bank includes two matrices, each having EM memory units in eight rows and four columns. In a further example, each EM bank includes two matrices, each having EM memory units in four rows and eight columns. In accordance with all the three examples, both the column select shift register <NUM> and the row select shift register <NUM> include eight stages each.

The bank select shift register <NUM> can generate bank select signals at different points of time for different EM banks. The bank select signal can be provided to a bank select transistor in an EM bank. For example, the bank select signal for the EM bank <NUM>-<NUM> is provided to the bank select transistor <NUM>. If each bank has more than one bank select transistor, the bank select signal can be provided to all the bank select transistors in that bank by connecting their respective gate terminals together. In an implementation, the bank select shift register <NUM> includes as many stages as the number of EM banks it is connected to. In other words, the bank select shift register <NUM> includes 'n' stages, for providing bank select signals to the n different EM banks.

As explained earlier, in order to access an EM memory unit in an EM bank for reading or writing, the row select transistor corresponding to the row of the EM memory unit and the column select transistor corresponding to the EM memory unit are to be turned on by supplying the row select signal and the column select signal to their respective gate terminals and the bank select transistor in that EM bank is to be turned on by providing the bank select signal at its gate terminal. For this, the column select shift register <NUM>, the row select shift register <NUM>, and the bank select shift register <NUM> can generate column select signal, row select signal, and bank select signal corresponding to the EM memory unit. Consider an example scenario in which the EM memory unit in the second row and third column in the second EM bank, i.e., <NUM>-<NUM> is to be accessed for writing data into it. In this scenario, the second stage of the row select shift register <NUM> provides the row select signal for the second row, the third stage of the column select shift register <NUM> provides the column select signal for the third column, and the second stage of the bank select shift register <NUM> generates the bank select signal for the second EM bank <NUM>-<NUM>. In this manner, using the combination of the select shift registers, any EM memory unit in any row, column, and EM bank can be accessed.

As mentioned earlier, the bank select signal to different EM banks can be provided by different stages of the bank select shift register <NUM>.

<FIG> illustrates first stage <NUM> of the bank select shift register <NUM> providing the bank select signal to the EM bank <NUM>-<NUM>, according to an example implementation of the present invention. It will be understood that the bank select shift register includes other stages for providing bank select signals to other EM banks.

As illustrated in <FIG>, the first stage <NUM> of the bank select shift register <NUM> includes a plurality of transistors <NUM>-<NUM>. The transistors can be, for example, N-channel field effect transistors (FET). As illustrated, the gate and drain terminals of transistor <NUM> receive a clock signal S1. The source terminal of the transistor <NUM> is coupled to a node Yo. The gate and drain terminals of transistor <NUM> receive a clock signal S3. The source terminal of the transistor <NUM> is coupled to a node Y, which, in turn, is connected to the gate terminal of the bank select transistor <NUM>. The drain terminals of transistors <NUM> and <NUM> are coupled to the nodes Y0 and Y, respectively. The gate terminal of the transistor <NUM> receives a clock signal S2 and the gate terminal of the transistor <NUM> receives a clock signal S4. The source terminals of the transistors <NUM> and <NUM> are coupled to the drain terminals of transistors <NUM> and <NUM>, respectively. The source terminals of the transistors <NUM> and <NUM> are coupled to a reference voltage, such as ground. The gate terminal of the transistor <NUM> may be coupled to the output of a decoder circuit (not shown in <FIG>). The transistors corresponding to the transistor <NUM> in the subsequent stages of the bank select shift register <NUM> may be coupled to the output of their respective previous stages. For example, the transistor corresponding to the transistor <NUM> in the second stage may be coupled to the node Y.

The clock signals S1 through S4 are each a periodic sequence of pulses with sequential phase offset such that the pulse on S2 occurs after the pulse on S1, the pulse on S3 occurs after the pulse on S2, and so on.

Claim 1:
A memory arrangement for a fluid ejection die, the fluid ejection die comprising:
a plurality of nozzles (<NUM>, <NUM>, <NUM>) to eject drops of fluid, the memory arrangement comprising:
a memory bank (<NUM>) having a first plurality of memory units (<NUM>-<NUM>, ..., <NUM>-M) arranged in the form of a first matrix (<NUM>), the first matrix (<NUM>) having a plurality of rows and a plurality of columns; and
a first bank select transistor (<NUM>) common to the first plurality of memory units (<NUM>-<NUM>, ..., <NUM>-M), wherein the first bank select transistor (<NUM>) is configured for facilitating access to a memory unit of the first plurality of memory units (<NUM>-<NUM>, ..., <NUM>-M) based on a single bank select signal (<NUM>) provided to the first bank select transistor (<NUM>);
wherein the memory bank (<NUM>) comprises a second plurality of memory units (<NUM>-<NUM>, ..., <NUM>-N) arranged in the form of a second matrix (<NUM>), wherein the system comprises a second bank select transistor (<NUM>) common to the second plurality of memory units (<NUM>-<NUM>, ..., <NUM>-N), and wherein the second bank select transistor (<NUM>) is configured for receiving the single bank select signal (<NUM>) to facilitate accessing a memory unit of the second plurality of memory units (<NUM>-<NUM>, ..., <NUM>-N) based on the single bank select signal (<NUM>) provided to the second bank select transistor (<NUM>),
characterized by the first bank select transistor (<NUM>) being connected to each memory unit of the first plurality of memory units (<NUM>-<NUM>, ..., <NUM>-M) through a corresponding row select transistor (<NUM>; <NUM>; <NUM>) and a corresponding column select transistor (<NUM>; <NUM>; <NUM>); and
the second bank select transistor (<NUM>) being connected to each memory unit of the second plurality of memory units (<NUM>-<NUM>, ..., <NUM>-N) through a corresponding row select transistor (<NUM>; <NUM>; <NUM>) and a corresponding column select transistor (<NUM>; <NUM>; <NUM>).