Patent Description:
<CIT> describes an organic EL display including: a plurality of first electrodes provided in a display region on a drive substrate, the plurality of first electrodes each including a laminated film having two or more layers; an organic layer provided on the plurality of first electrodes and including a light emitting layer; an electrode pad provided in a peripheral region around the display region; and a second electrode provided on the organic layer as well as the electrode pad, wherein the laminated film includes a first conductive film functioning as a reflective film, and a second conductive film provided below the first conductive film, and having a reflectance lower than that of the first conductive film, and the electrode pad corresponds to a part of the laminated film, and includes a conductive film made of a material same as that of the second conductive film.

<CIT> describes a display apparatus and a fabricating method thereof. The display apparatus includes a substrate, a light emitting diode, a first bump, a first insulating layer and a second insulating layer. The light emitting diode has a first surface and a second surface opposite each other, wherein the first surface faces the substrate. The light emitting diode is bonded to the substrate through the first bump. The first insulating layer is disposed on a periphery of the first bump and the light emitting diode, and contacts the first bump and the first surface. The second insulating layer is disposed on the substrate and surrounds at least a portion of the first insulating layer.

Electronic devices are generally used in daily life. With the development of electronic devices, the requirements for the quality and functions of electronic devices are increased. Electronic devices still do not meet user's requirements in various aspects for now. For example, there are still some reliability or yields problems of electronic devices. Therefore, how to continuously improve the reliability or yields of electronic devices has become an issue.

This in mind, the present disclosure aims at providing an electronic device having improved reliability or yields. In the electronic device of this disclosure, the conductive layer (such as a top surface of the conductive layer) under the bonding pad and connected to the bonding pad may include a plurality of recesses or through holes. When the temperature rises, the recesses or through holes can provide extra space for the expansion of the conductive layer, thereby reducing peeling or warping between layers under the bonding pad.

This is achieved by an electronic device according to the independent claims. The dependent claims pertain to corresponding further developments and improvements.

As will be seen more clearly from the detailed description following below, an electronic device is provided by the present disclosure. The electronic device includes a substrate, a dielectric layer, a driving layer, an organic layer and a light emitting unit. The driving layer is disposed on the substrate. The driving layer includes a thin film transistor, and the thin film transistor includes a drain, a source and a gate. The organic layer is disposed on the driving layer. The organic layer includes a connecting hole and a through hole portion, and the through hole portion includes a through hole. The light emitting unit is disposed on the organic layer. The dielectric layer is disposed between the gate and the organic layer. The light emitting unit is disposed on the organic layer and electrically connected to the driving layer by a bonding pad. A ratio of an area of the through hole portion overlapped with the bonding pad to an area of the bonding pad is greater than or equal to <NUM> and less than or equal to <NUM> in a top view direction of the electronic device. The light emitting unit includes a conductive pad electrically connected to the bonding pad, the light emitting unit overlaps the bonding pad, and the conductive pad overlaps the bonding pad in the top view direction. A portion of the drain is exposed by the connecting hole. A portion of an upper surface of the dielectric layer is exposed by the through hole, wherein the upper surface of the dielectric layer is disposed far away from the substrate in the top view direction.

In the following, the disclosure is further illustrated by way of example, taking reference to the accompanying drawings.

It is noted that <FIG> and <FIG> show a cross-sectional schematic diagram illustrating an electronic device not forming part of the claimed invention.

The present disclosure may be understood by reference to the following detailed description, taken in conjunction with the drawings as described below. It is noted that, for purposes of illustrative clarity and being easily understood by the readers, various drawings of this disclosure show a portion of the electronic device, and certain elements in various drawings may not be drawn to scale. In addition, the number and dimension of each element shown in drawings are for illustrative and are not intended to limit the scope of the present disclosure.

Certain terms are used throughout the description and following claims to refer to particular elements. As one skilled in the art will understand, electronic equipment manufacturers may refer to an element by different names. This document does not intend to distinguish between elements that differ in name but not function. In the following description and in the claims, the terms "include", "comprise" and "have" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to.

It will be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element or layer, or intervening elements or layers may be presented. In contrast, when an element is referred to as being "directly on" another element or layer, there are no intervening elements or layers presented. On the other hand, when an element or layer is referred to as being "on" another element or layer, the two elements or layers are in an up-down relationship in a top view direction. The element or layer can be located "on" or "below" the other element or layer, and the up-down relationship depends on orientation of the electronic device.

It will be understood that when an element or layer is referred to as being "connected to" another element or layer, it may be directly connected to the other element or layer, or intervening elements or layers may be presented. In contrast, when an element is referred to as being "directly connected to" another element or layer, there are no intervening elements or layers presented. On the other hand, when an element is referred to as being "coupled to" another element, the element can be directly connected to the another element, or the element can be indirectly connected (such as electrically connected) to the another element by one or a plurality of elements.

The term "about", "substantially", "equal", or "same" generally refers to falling within <NUM>% of a given value or range, or to falling within <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, or <NUM>% of a given value or range.

Although terms such as first, second, third, etc., may be used to describe diverse constituent elements, such constituent elements are not limited by the terms. The terms are used only to discriminate a constituent element from other constituent elements in the specification. The claims may not use the same terms, but instead may use the terms first, second, third, etc. with respect to the order in which an element is claimed. Accordingly, in the following description, a first constituent element may be a second constituent element in a claim.

It should be noted that the technical features in different embodiments described in the following can be replaced, recombined, or mixed with one another to constitute another embodiment. The scope of protection is defined by the appended set of claims.

An electronic device of the present disclosure may include a display device, an antenna device, a sensing device, a lighting device, a tiled device, other appropriate device, or the combinations of the above-mentioned devices, but not limited thereto. The electronic device may be a bendable or flexible electronic device. In an embodiment, the electronic device may include a display medium and/or a light emitting unit. For example, the electronic device can include a liquid crystal layer or a light emitting diode (LED). The light emitting diode may be organic light emitting diode (OLED) or inorganic light emitting diode, for example, mini LED, micro LED, quantum dot, quantum dot LED (QLED or QDLED), fluorescence, phosphor, other suitable materials, or the combinations of the above-mentioned materials may be used, but not limited thereto. Hereinafter, it is illustrative of an example that the electronic device is the display device, but not limited thereto.

Please refer to <FIG> and <FIG>, <FIG> is a schematic diagram illustrating an electronic device according to a first embodiment of the present disclosure, and <FIG> is a cross-sectional schematic diagram illustrating a structure taken along the line A-A' of <FIG>. An electronic device <NUM> includes a substrate <NUM>, a driving layer <NUM>, an organic layer <NUM> (also known as a planarization layer) and a light emitting unit <NUM>. In some embodiments, the driving layer <NUM> is disposed on the substrate <NUM>, and the organic layer <NUM> is disposed on the driving layer <NUM> and includes a through hole portion <NUM>. The light emitting unit <NUM> is disposed on the organic layer <NUM>, and the light emitting unit <NUM> is electrically connected to the driving layer <NUM> by a bonding pad (such as a bonding pad <NUM> or a bonding pad <NUM>). The light emitting unit <NUM> can be arranged in a matrix or other ways (e.g. pentile arrangement), but not limited thereto. In some embodiments, the light emitting unit <NUM> may include a light emitting diode (not shown in the figure). A light converting material (not shown in the figure) may be disposed on the light emitting diode, and the light converting material may for example include quantum dot (QD) material, fluorescence material, color filter (CF) material, phosphor material, other suitable light converting materials, or the combinations of the above-mentioned materials, but not limited thereto. In some embodiments (not shown in the figure), the light converting material may for example cover the light emitting diode. In some embodiments, a plurality of layers (such as a conductive layer and/or an insulating layer) may be disposed between the light emitting unit <NUM> and the substrate <NUM>, but not limited thereto.

In addition, thin film transistors, integrated circuits, circuits, conductive pads, conductive lines or other electronic components may be disposed on the substrate <NUM>. The substrate <NUM> may include rigid substrate, flexible substrate or the combinations of the above-mentioned substrates, but not limited thereto. In some embodiments, the substrate <NUM> may include foldable substrate or deformable substrate, but not limited thereto. In some embodiments, the material of the substrate <NUM> may include glass, quartz, organic polymer, plastic, metal, ceramic, other suitable materials, or the combinations of the above-mentioned materials, but not limited thereto. If the material of the substrate <NUM> includes organic polymer, the organic polymer may for example include polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), or the combinations of the above-mentioned materials, but not limited thereto.

Please refer to <FIG>. The driving layer <NUM> may include a buffer layer <NUM> disposed adjacent to the substrate <NUM>. The driving layer <NUM> includes a thin film transistor. The material of the buffer layer <NUM> may include silicon oxide, silicon nitride, other suitable materials or the combinations of the above-mentioned materials, but not limited thereto. The thin film transistor <NUM> (or the thin film transistor <NUM>) includes a semiconductor layer <NUM> (e.g. including a drain region 108D and a source region <NUM>). The material of the semiconductor layer <NUM> may include polycrystalline silicon, amorphous silicon (e.g. low-temperature poly-silicon) or metal oxide semiconductor (e.g. indium gallium zinc oxide), but not limited thereto. The material of the semiconductor layer <NUM> of the thin film transistor <NUM> and the material of the semiconductor layer <NUM> of the thin film transistor <NUM> can be the same, and also can be different.

In addition, a gate insulating layer <NUM> is disposed on the semiconductor layer <NUM>, and a conductive layer <NUM> is disposed on the gate insulating layer <NUM>, but not limited thereto. As shown in <FIG>, the conductive layer <NUM> can be used to form a gate <NUM> of the thin film transistor <NUM> (or the thin film transistor <NUM>). In other words, the gate <NUM> can be a portion of the conductive layer <NUM>. In addition, a dielectric layer <NUM> and a conductive layer <NUM> are disposed on the conductive layer <NUM> sequentially. These layers can be adjusted according to different requests. The conductive layer <NUM> can be used to form a data line, a source <NUM> and/or a drain 116D of the thin film transistor <NUM>(or the thin film transistor <NUM>). In other words, the source <NUM> and/or the drain 116D may be a portion/portions of the conductive layer <NUM>, but not limited thereto. In some embodiments, the material of the conductive layer <NUM> and the conductive layer <NUM> may include metallic materials, transparent conductive materials, or combinations thereof, but not limited thereto.

In the present embodiment, the thin film transistors in <FIG> are top gate thin film transistors for example, but not limited thereto. In other embodiments, the thin film transistors may include bottom gate thin film transistors, dual gate thin film transistors (also referred to as double gate thin film transistors), but not limited thereto.

Please refer to <FIG>, the electronic device <NUM> may further include a conductive layer <NUM> and an insulating layer <NUM> disposed on the organic layer <NUM>. It is noticed that in the present embodiment, the driving layer <NUM> may be defined by layers between the substrate <NUM> and the conductive layer <NUM> (such as the source <NUM> and the drain 116D). The driving layer <NUM> may include the conductive layer <NUM> but may not include the substrate <NUM>. In the claimed invention, the organic layer <NUM> includes at least one connecting hole <NUM> and at least one through hole portion <NUM>, and the through hole portion <NUM> includes at least one through hole. In other words, in a top view direction V of the electronic device (such as a normal direction of the substrate <NUM>), all the through holes <NUM> overlapped with the bonding pad <NUM> (or the bonding pad <NUM>) are referred to as the through hole portion <NUM>. In addition, in the top view direction V of the electronic device, the connecting hole <NUM> is overlapped with the thin film transistor <NUM> (such as being overlapped with the drain 116D), and a portion of the drain 116D is exposed by the connecting hole <NUM>, such that the conductive layer <NUM> can be electrically connected to the thin film transistor <NUM> through the connecting hole <NUM>. In the claimed invention, a portion of a surface of the dielectric layer <NUM> is exposed by the through hole <NUM>.

In some embodiments, the conductive layer <NUM> may have a conductive portion <NUM> and a conductive portion <NUM>. The conductive portion <NUM> and the conductive portion <NUM> can be separated from each other. In other words, the conductive portion <NUM> and the conductive portion <NUM> may not be directly connected, but not limited thereto. In some embodiments, the conductive portion <NUM> and/or the conductive portion <NUM> may be correspondingly disposed on the through hole portion <NUM>, and at least a portion of the conductive portion <NUM> and/or the conductive portion <NUM> may be disposed in the through hole <NUM>.

In some embodiments, a portion of the conductive portion <NUM> may be extended to a position on the connecting hole <NUM> and extended into the connecting hole <NUM>, such that the conductive layer <NUM> may be electrically connected to the thin film transistor <NUM>(such as the drain 116D) through the connecting hole <NUM>. In some embodiments, the portion of the drain 116D exposed by the connecting hole <NUM> may contact the conductive portion <NUM>. In other words, the conductive layer <NUM> may contact the driving layer <NUM>, but not limited thereto. In some embodiments, the portion of the surface of the dielectric layer <NUM> exposed by the through hole <NUM> may contact the conductive portion <NUM> and/or the conductive portion <NUM> of the conductive layer <NUM>, but not limited thereto.

Please refer to <FIG>, in some embodiments, the insulating layer <NUM> may include a plurality of openings that can be used to expose portions of a surface of the conductive layer <NUM>. In addition, the electronic device <NUM> may further include a conductive layer <NUM> disposed on the conductive layer <NUM>. The conductive layer <NUM> includes the bonding pad <NUM> and the bonding pad <NUM> disposed between the light emitting unit <NUM> and the conductive layer <NUM>. The bonding pad <NUM> and the bonding pad <NUM> are respectively disposed on two openings of the insulating layer <NUM>, and a portion of the bonding pad <NUM> and/or a portion of the bonding pad <NUM> can be filled or disposed in the corresponding opening of the insulating layer <NUM>. The bonding pad <NUM> and/or the bonding pad <NUM> may be electrically connected to the conductive layer <NUM> through the openings of the insulating layer <NUM>. For example, the bonding pad <NUM> and/or the bonding pad <NUM> may contact portions of the surface of the conductive layer <NUM> through the openings of the insulating layer <NUM>, but not limited thereto. In some embodiments, in the top view direction V of the electronic device <NUM>, the bonding pad <NUM> and the bonding pad <NUM> are overlapped with the through hole portion <NUM>. In some embodiments, a portion of the conductive portion <NUM> may be disposed in the through hole portion <NUM> (such as the through holes <NUM>) overlapped with the bonding pad <NUM>, and a portion of the conductive portion <NUM> may be disposed in the through hole portion <NUM> (such as the through holes <NUM>) overlapped with the bonding pad <NUM>.

In some embodiments, the material of the conductive layer <NUM> may include molybdenum (Mo), copper (Cu), the combination of the above-mentioned materials, or other suitable metals or conductive materials, but not limited thereto. In some embodiments, the material of the conductive layer <NUM> may include nickel (Ni), gold (Au), the combination of the above-mentioned materials, or other suitable metals or conductive materials, but not limited thereto.

As shown in <FIG> the conductive layer <NUM> (the bonding pad <NUM> and/or the bonding pad <NUM>) may be form by deposition process (such as physical vapor deposition or chemical vapor deposition), but not limited thereto. As shown in <FIG>, a plurality of recesses 124R (also referred to as first recesses) may be form on a portion of the top surface of the conductive layer <NUM> located above the through holes <NUM>. In other words, the conductive layer <NUM> may include the plurality of recesses 124R. In some embodiments, a portion of the bonding pad <NUM> and/or a portion of the bonding pad <NUM> may be disposed in the plurality of recesses 124R. In some embodiments, a plurality of recesses 128R (also referred to as second recesses) may be formed on the top surface of the bonding pad <NUM> and/or the bonding pad <NUM> located above the recesses 124R. In some embodiments, at least a portion of the plurality of second recesses 128R are overlapped with at least a portion of the plurality of first recesses 124R, but not limited thereto.

It is noticed that the plurality of recesses may not be formed on the top surface of a conductive layer (referring to the conductive layer <NUM>) in the conventional electronic device. Therefore, the conductive layer <NUM> of the conventional electronic device may be expanded due to heat when the temperature is high, such that the conductive layer <NUM> and some adjacent layers may be warped because there is no enough space for the conductive layer <NUM> to expand. Some layers under the bonding pad <NUM> and/or the bonding pad <NUM> may further be peeling. For example, the organic layer <NUM> may be peeling from the insulating layer <NUM> (or inorganic material layer) under the bonding pad, but not limited thereto. Alternatively, the conductive layer <NUM> and the organic layer <NUM> under the bonding pad may be peeling from each other. In addition, the substrate under the bonding pad may crack under the influence of thermal expansion and contraction of the conductive layer <NUM>. However, in one of the embodiments of the present disclosure (as shown in <FIG>), the plurality of through holes <NUM> are disposed in the organic layer <NUM>, the plurality of recesses 124R may be formed on the top surface of the conductive layer <NUM> above the through holes <NUM>. When the temperature is high, the space formed by the recesses 124R (such as the notches formed by the recess 124R) may provide space for heat expansion of the conductive layer <NUM>. The peeling and warping between different layers can be reduced. Similarly, the plurality of recesses 128R of the top surfaces of the bonding pad <NUM> and the bonding pad <NUM> also have the above-mentioned function.

Please refer to <FIG> and <FIG> is a schematic diagram in the top view direction illustrating the bonding pad and the through hole portion under the bonding pad according to the first embodiment of the present disclosure. The structure in the B-B' area in <FIG> corresponds to the B-B' line in <FIG>. Other components and layers are omitted to emphasize the relationship between the bonding pad and the through hole portion. Taking the bonding pad <NUM> for example in <FIG>, a plurality of through holes <NUM> are disposed under the bonding pad <NUM>. In the top view direction V of the electronic device, the bonding pad <NUM> is overlapped with at least a portion of the through holes <NUM>. In other embodiments, the through holes <NUM> of the organic layer <NUM> may have different arrangement for different requirements. In addition, in the top view direction V of the electronic device <NUM>, an area of the bonding pad (such as the bonding pad <NUM> or the bonding pad <NUM>) is A, an area of the through hole portion <NUM> overlapped with the bonding pad (such as a total area of the plurality of the through holes <NUM>) is B. A ratio (B/A) of the area of the through hole portion <NUM> overlapped with the bonding pad (B) to the area of the bonding pad (A) is greater than and equal to <NUM> and less than and equal to <NUM>. In some embodiments, the ratio (B/A) may be greater than and equal to <NUM> and less than and equal to <NUM>, but not limited thereto. In some embodiments, the ratio (B/A) may be greater than and equal to <NUM> and less than and equal to <NUM>, but not limited thereto. In some embodiments, the ratio (B/A) may be greater than and equal to <NUM> and less than and equal to <NUM>, but not limited thereto. It is noticed that the area of the through hole <NUM> may be measured by the bottom area of the through hole <NUM> (such as a surface adjacent to the substrate <NUM>). In addition, in the top view direction V, the shape of the through hole <NUM> may be circular, rectangular, polygonal, a shape with curved edges, irregular shape, or the combinations of the above-mentioned shapes, but not limited thereto.

Please refer to <FIG>, a conductive pad <NUM> of the light emitting unit <NUM> is electrically connected to the bonding pad <NUM> or the bonding pad <NUM> through a solder <NUM>. The solder may be disposed between the bonding pad <NUM> (or the bonding pad <NUM>) and the light emitting unit <NUM>. The light emitting unit <NUM> includes two conductive pads <NUM> (such as two pins of the light emitting unit <NUM>). The solder <NUM> may be disposed between the bonding pad <NUM>(or the bonding pad <NUM>) and the conductive pad <NUM>. The light emitting unit <NUM> may be connected or electrically connected to the bonding pad <NUM> (and/or the bonding pad <NUM>) through the solder <NUM>. In some embodiments, the material of the conductive layer <NUM> may have good adhesion with the material of the solder <NUM> or the conductive layer <NUM>. In some embodiments, the bonding pad <NUM> and/or the bonding pad <NUM> may be disposed between the light emitting unit <NUM> (such as the conductive pads <NUM>) and the conductive layer <NUM>. The light emitting unit <NUM> may be electrically connected to the driving layer <NUM> through the bonding pad <NUM> (or the bonding pad <NUM>) and the conductive layer <NUM>, but not limited thereto. In some embodiments, the material of the conductive pad <NUM> and the solder <NUM> may include metal or other suitable conductive materials, but not limited thereto.

Hereinafter, other embodiments of the present disclosure will be described in detail. For simplification, the same components are labeled with the same reference numbers. In order to emphasize the difference between the different embodiments, the difference between the different embodiments will be describe in detail below, and the same technical features will not be repeated.

Please refer to <FIG> is a schematic diagram illustrating a through hole portion under a bonding pad according to a second embodiment of the present disclosure. The difference between the second embodiment and the first embodiment (<FIG>) is that the through holes <NUM> in different rows or columns may be disposed misaligned, but not limited thereto. It is noticed that, the shape and the dimension of the through hole <NUM> and the gap between the through holes <NUM> may be changed or adjusted according to different requirements, and different through holes <NUM> may be adjusted irregularly.

Please refer to <FIG> is a schematic diagram illustrating a through hole portion under a bonding pad according to a third embodiment of the present disclosure. The difference between the third embodiment and the first embodiment (<FIG>) is that the through hole portion <NUM> under the bonding pad <NUM> (and/or the bonding pad <NUM>) may include a through hole <NUM> in the present embodiment. In the top view direction V, the shape of the through hole <NUM> is different from the shape of the through hole <NUM> in <FIG>. In the present embodiment, the area of the through hole <NUM> may be greater than the area of the through hole <NUM> in the first embodiment, but not limited thereto. As shown in <FIG>, in the top view direction V, the organic layer <NUM> includes a sidewall SW. For example, the sidewall SW surrounds the through hole <NUM>. In addition, the sidewall SW may include a plurality of sub-sidewall. Taking <FIG> as an example, the sidewall SW may include two sub-sidewalls SW1 and two sub-sidewalls SW2, and the sub-sidewall SW1 and the sub-sidewall SW2 are connected to each other to form the sidewall SW. In some embodiments, the shape of the sub-sidewall SW1 may be wave-shaped, and the shape of the sub-sidewall SW2 may be straight, but not limited thereto. In some embodiments, the sub-sidewall SW1 and/or the sub-sidewall SW2 may have different shapes (such as curve, straight line, zigzag, or irregular shape) for different requirements, and the sub-sidewall SW1 and/or the sub-sidewall SW2 may have the same shape or have different shapes.

Please refer to <FIG> is a schematic diagram illustrating a through hole portion and a signal line under a bonding pad according to a fourth embodiment of the present disclosure. For convenience of illustration, only the through hole <NUM> of the through hole portion <NUM> of the organic layer <NUM> and a signal line <NUM> are shown in <FIG>, and other components and layers are omitted in <FIG>. The difference between the fourth embodiment and the third embodiment is the driving layer <NUM> in the present embodiment (referring to <FIG>) may further include at least one signal line <NUM>. In the top view direction V of the electronic device <NUM>, the signal line <NUM> may be overlapped with the through hole portion <NUM> (such as the through hole <NUM>). In some embodiments, the signal line <NUM> may be formed by the conductive layer <NUM>, and the signal line <NUM> may be a scan line, but not limited thereto. In some embodiments, the signal line <NUM> may be formed by the conductive layer <NUM>, and the signal line <NUM> may be a data line, but not limited thereto. In some embodiments, the signal line <NUM> may be formed by other conductive layers, and the signal line <NUM> may be a power line or other signal lines. In some embodiments, at least one insulating layer (such as a dielectric layer) may be disposed between the signal line <NUM> and the through hole <NUM> to reduce the electrical connection between the signal line <NUM> and the conductive layer <NUM> disposed in the through hole <NUM>.

As shown in <FIG>, the signal line <NUM> may be extended along a direction (such as a direction D1), but not limited thereto. In addition, the sub-sidewall SW1 may be substantially extended along another direction (such as a direction D2 different from the direction D1), and the sub-sidewall SW2 may be extended along the direction (such as the direction D1), but not limited thereto. The direction D1 is different from the direction D2. For example, the direction D1 and the direction D2 are perpendicular, but not limited thereto. In some embodiments, the extension direction of the sub-sidewall SW2 and the extension direction of the signal line <NUM> may not be parallel. In some embodiments, the extension direction of the sub-sidewall SW1 and the extension direction of the signal line <NUM> may not be perpendicular. In some embodiments, two side edges of the signal line <NUM> may intersect the sub-sidewall SW1 of the organic layer <NUM> at two intersection points X. An extension line CL is substantially drawn by connecting the two intersection points X, and the extension line CL may be extended along a direction D3. The direction D3 may have an angle θ with the extension direction of the signal line <NUM> (such as the direction D1. In some embodiments, the angle (such as the angle θ) between the sidewall SW (such as the sub-sidewall SW1) and the signal line <NUM> may not be a right angle, but not limited thereto. For example, the angle θ may be greater than or equal to <NUM> degree and less than or equal to <NUM> degree, but not limited thereto. Since a portion of the conductive layer <NUM> is disposed in the through holes <NUM> of the organic layer <NUM>, a stress (created by the expansion and contraction from the conductive layer <NUM>) applying to the signal line <NUM> under the conductive layer <NUM> can be reduced to prevent the signal line <NUM> from being break when the angle θ between the sidewall SW (such as the sub-sidewall SW1 of the organic layer <NUM>) and the signal line <NUM> is not a right angle, but not limited thereto.

It is noticed that the through hole <NUM> and the signal line <NUM> in <FIG> are simplified for illustration, the through hole <NUM> may be overlapped with more or less signal lines <NUM>, and the dimensions of the through hole <NUM> and the signal line <NUM> may be adjusted according to different requirements. In other embodiments, the signal line <NUM> may be formed wider, and the angle (such as the angle θ) between the sidewall SW (such as the sub-sidewall SW1) and the signal line <NUM> may selectively be a right angle or not to be a right angle.

Please refer to <FIG> and <FIG>, <FIG> is a cross-sectional schematic diagram illustrating an electronic device according to a fifth embodiment of the present disclosure, <FIG> is a schematic diagram illustrating a through hole portion and a signal line under a bonding pad according to the fifth embodiment of the present disclosure, and the structure in the C-C' area in <FIG> corresponds to the C-C' line in <FIG>. The difference between the fifth embodiment and the first embodiment is that the driving layer <NUM> in the present embodiment may include at least one signal line <NUM> (as shown in <FIG>), and the signal line <NUM> may be overlapped with the through hole portion <NUM> (such as a plurality of the through holes <NUM>) (as shown in <FIG> and <FIG>) in the top view direction V of the electronic device <NUM>. In <FIG>, the signal line <NUM> (such as a scan line) may be formed by the conductive layer <NUM>, the signal line <NUM> may be disposed between the gate insulating layer <NUM> and the dielectric layer <NUM>, but not limited thereto.

Please refer to <FIG>, the electronic device <NUM> further includes a dielectric layer <NUM> disposed between the dielectric layer <NUM> and the organic layer <NUM>, but not limited thereto. The material of the dielectric layer <NUM> may include organic insulating materials, inorganic insulating materials, or other suitable insulating materials, but not limited thereto. The connecting hole <NUM> of the through hole portion <NUM> may penetrate the organic layer <NUM> and the dielectric layer <NUM> to expose a portion of the surface of the drain 116D, such that the conductive portion <NUM> of the conductive layer <NUM> can be electrically connected to the drain 116D through the connecting hole <NUM>, but not limited thereto. In some embodiments, the through hole <NUM> penetrates the organic layer <NUM>, and the through hole <NUM> does not penetrate the dielectric layer <NUM>. In some embodiments (not shown in the figure), the signal line <NUM> (such as a data line) may be formed by the conductive layer <NUM>, and the signal line <NUM> may be disposed between the dielectric layer <NUM> and the dielectric layer <NUM>, but not limited thereto.

Claim 1:
An electronic device (<NUM>), comprising
a substrate (<NUM>);
a driving layer (<NUM>) disposed on the substrate (<NUM>), wherein the driving layer (<NUM>) comprises a thin film transistor (<NUM>), and the thin film transistor (<NUM>) comprises a drain (116D), a source (<NUM>) and a gate (<NUM>);
an organic layer (<NUM>) disposed on the driving layer (<NUM>), the organic layer (<NUM>) comprising a connecting hole (<NUM>) and a through hole portion (<NUM>), wherein the through hole portion (<NUM>) comprises a through hole (<NUM>);
a dielectric layer (<NUM>) disposed between the gate (<NUM>) and the organic layer (<NUM>); and
a light emitting unit (<NUM>) disposed on the organic layer (<NUM>), the light emitting unit (<NUM>) being electrically connected to the driving layer (<NUM>) by a bonding pad (<NUM>, <NUM>);
wherein a portion of the drain (116D) is exposed by the connecting hole (<NUM>) and a portion of an upper surface of the dielectric layer (<NUM>) is exposed by the through hole (<NUM>), wherein the upper surface of the dielectric layer (<NUM>) is disposed far away from the substrate (<NUM>) in a top view direction (V),
wherein a ratio of an area of the through hole portion (<NUM>) overlapped with the bonding pad (<NUM>, <NUM>) to an area of the bonding pad (<NUM>, <NUM>) is greater than or equal to <NUM> and less than or equal to <NUM> in the top view direction (V) of the electronic device (<NUM>),
wherein the light emitting unit (<NUM>) comprises a conductive pad (<NUM>) electrically connected to the bonding pad (<NUM>, <NUM>), the light emitting unit (<NUM>) overlaps the bonding pad (<NUM>, <NUM>) in the top view direction (V), and the conductive pad (<NUM>) overlaps the bonding pad (<NUM>, <NUM>) in the top view direction (V).