Patent Description:
In digital circuits, a transistor is a switch which ideally: a) passes zero current when it is off; b) supplies large current flow when it is on; and c) switches instantly between the on and off states. Unfortunately, a transistor is not ideal as constructed in an integrated circuit and tends to leak current even when it is off. Current that leaks through, or out of, the device tends to drain the battery that supplies power to the device. For many years, integrated circuit transistor performance was improved by shrinking critical dimensions to increase switching speed. However, as dimensions of silicon-based transistors continue to shrink, maintaining control of various electrical characteristics, including off-state leakage, becomes increasingly more challenging, while performance benefits derived from shrinking the device dimensions have become less significant. It is therefore advantageous, in general, to reduce leakage current in the transistor by alternative means, including changes in materials and device geometry.

Integrated circuits typically incorporate FETs in which current flows through a semiconducting channel between a source and a drain, in response to a voltage applied to a gate. A traditional planar (<NUM>-D) transistor structure is shown in <FIG> and described below in greater detail. To provide better control of the current flow, FinFET transistors, sometimes called 3D transistors, have been developed, such as the one shown in <FIG>. A FinFET is an electronic switching device in which the planar semiconducting channel of a traditional FET is replaced by a semiconducting fin that extends outward, normal to the substrate surface. In such a device, the gate, which controls current flow in the fin, wraps around three sides of the fin so as to influence the current flow from three surfaces instead of one. The improved control achieved with a FinFET design results in faster switching performance and reduced current leakage.

Intel described this type of transistor in an announcement on May <NUM>, <NUM>, calling it by various names including a 3D transistor, a <NUM>-D Tri-Gate transistor, or a FinFET. (See, for example, the article titled "<NPL>; see also <CIT>; <CIT>; <CIT>; <CIT>; and <CIT>).

An array of semiconducting fins is shown in <FIG>. Typically, an array of multiple transistors can be formed by conformally depositing a common gate over an array of fins. Furthermore, an array of multi-gate transistors can be formed by conformally depositing multiple common gates over the array of fins. Such a FinFET array having three gates between source and drain regions is known as a tri-gate transistor.

Prior to the development of FinFETs, strained silicon transistors were developed to increase control of the mobility of charge carriers in the semiconducting channel. Introducing compressive strain into the transistor materials tends to increase charge mobility, resulting in a faster switching response to changes in voltage applied to the gate. Strain can be introduced, for example, by replacing bulk silicon in the source and drain regions, or in the channel itself, with epitaxially-grown silicon compounds. The term epitaxy refers to a controlled process of crystal growth in which a new, epitaxial, layer of a crystal is
grown from the surface of a bulk crystal, while maintaining the same crystal structure of the underlying bulk crystal.

Despite improvements provided by three dimensional structures and strained silicon materials, transistors continue to suffer certain types of performance degradation as device dimensions shrink into the range of <NUM> - <NUM> nanometers. These include, in particular, leakage of charge between the semiconducting channel and the substrate.

<CIT> discloses a method of manufacturing a semiconductor device structure, such as a FinFET device structure. A method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. An etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure.

<NPL>, discloses a CMOS device architecture called silicon on nothing. The SON process allows the buried dielectric (which may be an oxide but also an air gap) to be fabricated locally in dedicated parts of the chip. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device.

<CIT> discloses a SiGe-based bulk integration scheme for generating FinFET devices on a bulk Si substrate in which a simple etch, mask, ion implant set of sequences have been added to accomplish good junction isolation while maintaining the low capacitance benefits of FinFETs.

<CIT> discloses an integrated circuit device including a substrate. An epitaxial pattern is on the substrate and has a pair of impurity diffusion regions formed therein and a pair of void regions formed therein that are disposed between the pair of impurity diffusion regions and the substrate. Respective ones of the pair of impurity diffusion regions at least partially overlap respective ones of the pair of void regions. A gate electrode is on the epitaxial pattern between respective ones of the pair of impurity diffusion regions.

<CIT> discloses a FinFET device fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

<CIT> discloses there is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.

<CIT> discloses methods which include providing a single crystal silicon substrate having a device pattern formed on a portion of the substrate where the device pattern has a protrusion, forming a protection layer on a portion of the protrusion, and forming an oxide insulation layer between the protrusion and the substrate using a thermal oxidation process. Structures formed by such methods; and partial silicon-on-insulator structures comprising a single crystal silicon substrate having an device pattern disposed on a surface thereof where the device pattern includes a non-SOI region and an SOI region having a protrusion, and an oxide insulation layer disposed in the device pattern where a portion of the insulation layer is disposed under the protrusion such that the protrusion is isolated from the single crystal substrate, and where the non-SOI region is not isolated from the single crystal structure.

<CIT> discloses a semiconductor apparatus including: a support substrate made of a semiconductor; an insulating layer provided on the support substrate and having a first and a second openings; a semiconductor fin having a channel section, a first and second buried regions, a source section and a drain section; a gate insulating film covering a side face of the channel section; and a gate electrode opposed to the side face of the channel section across the gate insulating film. The channel section is provided upright on the insulating layer between the first and the second openings. The first and the second buried regions are provided in the first and the second openings on both sides of the channel section. The source-drain sections are provided on the first and the second buried regions and connected to the channel section.

<CIT> discloses an integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width.

<CIT> discloses a method comprising: providing a substrate comprising a first sacrificial gate over a shallow trench region and a diffused body; depositing a barrier layer on the shallow trench region, the diffused body, and the first sacrificial gate; eroding the barrier layer to expose the first sacrificial gate; etching the first sacrificial gate to form a recess in the barrier layer; depositing a dielectric layer in the recess; forming a multi-fin mask over the diffused body; etching the diffused body to form a plurality of multi-gate fins; forming isolation regions adjacent to the plurality of multi-gate fins; and forming a gate stack over the isolation regions and the plurality of multi-gate fins.

<CIT> discloses methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

According to one embodiment as described herein, channel-to-substrate leakage in a FinFET device is prevented by isolating the channel, which is the fin, from the substrate by inserting an insulating layer between the channel and the substrate. The insulating layer isolates the fin from the substrate both physically and electrically, thus preventing current leakage between the fin and the substrate. Theoretically, when there is no leakage, the device is either all on or all off.

Unlike conventional FinFET fabrication processes in which fins are formed by depositing and etching the fin material, the process described herein grows an array of fins epitaxially from the silicon surface, in the spaces between insulating columns that are pre-arranged in an array. The insulating columns provide localized insulation between adjacent fins. If the fins contain two different materials, the lower material can be easily removed, while leaving the upper material, thus yielding an interdigitated array of insulating columns and having semiconducting fins suspended above the silicon surface. A resulting gap underneath the remaining upper fin material can then be filled in with oxide if desired to better support the fins and aid to isolate the array of fin channels from the substrate.

In the drawings, identical reference numbers identify similar elements. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter may be practiced without these specific details. In some instances, well-known structures and methods of semiconductor processing comprising embodiments of the subject matter disclosed herein have not been described in detail to avoid obscuring the descriptions of other aspects of the present disclosure.

Unless the context requires otherwise, throughout the specification and claims that follow, the word "comprise" and variations thereof, such as "comprises" and "comprising" are to be construed in an open, inclusive sense, that is, as "including, but not limited to.

Reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects of the present disclosure.

Reference throughout the specification to insulating materials can include various materials other than those used to illustrate specific embodiments of the transistor devices presented. The term "epitaxial silicon compounds" should not be construed narrowly to limit an epitaxially grown structure to Si, SiGe, or SiC, for example, but rather, the term "epitaxial silicon compounds" is broadly construed to cover any compounds that can be grown epitaxially from a silicon substrate.

Specific embodiments are described herein with reference to examples of FinFET structures that have been produced. The FinFET structures are also referred to as <NUM>-D transistors in some publications or alternatively as tri-gate or multi-gate structures. The use of the term FinFET or fin transistor as used herein includes all structures of this type and is meant in the broad sense of which a 3D transistor or tri-gate transistor is a subset. The present disclosure and the reference to certain materials, dimensions, and the details and ordering of processing steps are exemplary and should not be limited to those shown.

In the figures, identical reference numbers identify similar features or elements. The sizes and relative positions of the features in the figures are not necessarily drawn to scale.

<FIG> shows a conventional planar transistor <NUM> built on a silicon substrate <NUM>. Parts of the conventional planar transistor include an active region <NUM>, a source <NUM>, a drain <NUM>, a planar conducting channel <NUM>, and a gate <NUM>. A gate dielectric, not shown, electrically isolates the channel from the gate, as is well known in the art. The active region <NUM> occupies an upper layer of the substrate that may be doped with impurities to create a well having a net negative or net positive charge. When the conventional planar transistor <NUM> is on, current flows from the source <NUM> to the drain <NUM>, through the planar conducting channel <NUM>. Current flow in the planar conducting channel is controlled by the gate <NUM> by application of a gate voltage. An electric field associated with the gate voltage has the effect of turning on the conventional planar transistor <NUM> if the gate voltage exceeds a certain threshold. If the applied gate voltage drops below the threshold voltage, the conventional planar transistor <NUM> shuts off and current ceases to flow from the source <NUM> to the drain <NUM>. Because the gate <NUM> can only influence the planar conducting channel <NUM> from one side (i.e., from the top of the planar conducting channel <NUM>), charge leakage into the silicon substrate <NUM> tends to occur at the channel/substrate junction.

<FIG> shows a conventional FinFET device <NUM> built on the silicon substrate <NUM>. Analogous to the device shown in <FIG>, parts of the conventional FinFET device <NUM> include an active region <NUM>, a source <NUM>, a drain <NUM>, a conducting fin channel <NUM>, and a wrap-around gate <NUM>. The active region <NUM> of the conventional FinFET device <NUM> may be doped with impurities to create a well having a net negative or net positive charge. When the conventional FinFET device <NUM> is on, current flows from the source <NUM> to the drain <NUM>, through the tall, conducting fin channel <NUM>, under control of the wrap-around gate <NUM>. Application of a voltage having a value that exceeds a certain threshold voltage value turns the conventional FinFET device <NUM> on. If the applied voltage drops below the threshold voltage value, the conventional FinFET device <NUM> shuts off and current ceases to flow from the source <NUM> to the drain <NUM>. Because the wrap-around gate <NUM> influences the conducting fin channel <NUM> from three sides, improved control of the conduction properties of the conducting fin channel <NUM> is achieved. Such improved control causes leakage of charge from the conducting fin channel <NUM> to the silicon substrate <NUM> to be reduced, although not eliminated. Because the current-carrying capacity of the fin channel <NUM> is much greater than that of the planar conducting channel <NUM>, the switching characteristics of the conventional FinFET device <NUM> are also improved over those of the conventional planar transistor <NUM>.

<FIG> shows an array of epitaxially grown semiconducting fins. Fins <NUM> for this type of transistor can be constructed in <NUM> technology and smaller. For example, the width of fin <NUM> may be in the range of <NUM>-<NUM>, the height <NUM> in the range of <NUM>-<NUM>, with a range of <NUM>-<NUM> preferred. The space <NUM> between the fins <NUM> can be in the same range as the width of the fins, for example, <NUM>-<NUM>.

The pitch <NUM> of the fins, namely, distance from the center of one fin <NUM> to the center of the next fin <NUM>, which is also the distance from the center of one space <NUM> to the center of the next space <NUM>, will generally be in the range of <NUM>-<NUM> for a <NUM> fin and is usually double the width of a fin <NUM>. Thus, for a fin width of <NUM>, a pitch <NUM> of <NUM> is preferred, but pitches in the range of <NUM>-<NUM> may also be used. The cycle of the fins <NUM> of these general dimensions and smaller are used for the various embodiments of the invention as will now be explained with respect to <FIG>. As semiconductor processes advance, the dimensions can also change to match available technology. For example, the fins may be in the range of <NUM>-<NUM> in width and have heights that are in the range of <NUM>-<NUM>, depending on the desired design characteristic and the geometries available.

<FIG> is a high-level flow diagram describing basic actions in a fabrication process <NUM> for an isolated channel FinFET device designed to prevent channel-to-substrate leakage. At <NUM>, an interdigitated structure of bi-layer fins and insulating columns is formed on a silicon substrate. At <NUM>, a conformal gate is deposited. At <NUM>, the entire interdigitated structure is removed from the source/drain regions while the structure remains in the gate region. At <NUM>, in the gate region, a lower portion of the bi-layer fins is replaced with an insulator, thus electrically isolating the interdigitated structure from the substrate. At <NUM>, an epitaxial raised source/drain is formed.

<FIG> is a more detailed flow diagram describing in more detail fabrication process <NUM> for the isolated channel FinFET device. At <NUM>, an active region is demarcated by forming a pair of insulating trenches in the silicon substrate. The insulating trenches form an electrical barrier between the active region where the FinFET device will be formed, and neighboring regions. At <NUM>, the trenches are filled with an insulating material, for example, a silicon oxide, and the nitride hard mask that was used to form the trenches is patterned to form an array of insulating columns. At <NUM>, spaces defined by the array of insulating columns are filled by epitaxial growth of various silicon compounds, to form an array of bi-layer fin channels. Each bi-layer fin channel includes a lower layer and an upper layer. At <NUM>, a conformal gate is deposited. At <NUM>, the interdigitated structure is removed from the source/drain region, but not from the gate region. During part of the removal process <NUM>, the lower layer of the fin channels in the gate region is also removed to create a void between the substrate and the upper layer of the fin channels. Because this lower layer is used as a temporary place holder, it is referred to as a sacrificial layer. At <NUM>, the void is filled with an insulating material, e.g., a silicon oxide. At <NUM>, an epitaxial raised source/drain is formed.

With reference to <FIG> below, each set of figures shows one of the process steps from <FIG> in more detail by presenting a more detailed sequence of process steps and a corresponding side view that results upon completion of that sequence of steps.

<FIG> illustrate the step <NUM> in greater detail, in which an active region is demarcated by forming a pair of insulating trenches in a silicon substrate. <FIG> shows a sequence of process steps, including the steps <NUM>, <NUM>, <NUM>, and <NUM>, that can be carried out to form the trench structure <NUM> shown in <FIG>. The trench structure <NUM> includes an N-doped substrate <NUM>, a P-doped substrate <NUM>, trenches <NUM> (three shown), a pad oxide layer <NUM>, and a silicon nitride layer <NUM>.

At <NUM>, doped wells are formed in the silicon substrate to facilitate formation of NMOS and PMOS devices. PMOS devices are typically formed in an N-well that is doped with a material having an excess of electrons (e.g., Group V elements such as phosphorous or arsenic). NMOS devices are typically formed in a P-well that is doped with a material lacking valence electrons (e.g., a Group III element, typically boron).

At <NUM>, the pad oxide layer <NUM> is grown by a standard technique, for example, exposing the silicon to an oxygen-rich environment at high temperature for thermal oxidation of the silicon. The pad oxide layer <NUM> is a thin insulating layer used to passivate the silicon surface. Removal of a native oxide layer on the silicon surface can precede the growth of the pad oxide layer <NUM>.

At <NUM>, the silicon nitride layer <NUM> is deposited by a standard technique, for example, chemical vapor deposition (CVD), plasma vapor deposition (PVD), or the like. The silicon nitride layer <NUM> can then be patterned using conventional optical lithography and etch processes. Because conventional optical lithography is well-known to those skilled in the art of semiconductor processing, it is not explicitly shown in the figures, but will be described briefly. Conventional optical lithography entails spinning on a photoresist, exposing portions of the photoresist to ultraviolet light through a patterned mask, and developing away the unexposed portions of the photoresist, thereby transferring the mask pattern to the photoresist. The photoresist mask can then be used to etch the mask pattern into one or more underlying layers. Typically, a photoresist mask can be used if the subsequent etch is relatively shallow, because photoresist is likely to be consumed during the etch process.

At <NUM>, the silicon nitride layer <NUM> is patterned and etched, for example, using a directed (anisotropic) plasma etch, also referred to as a reactive ion etch (RIE) process. Following the RIE etch, a standard wet chemical cleaning process can be used to remove residual photoresist. The silicon nitride layer <NUM> can then, in turn, be used as a hard mask for etching the trenches <NUM> in the substrate. As is well known to those skilled in the art, such a nitride hard mask technique is desirable when etching deep structures that require a longer etch time, because the nitride hard mask can withstand the etch process more reliably than a photoresist can. The trenches <NUM> extend into the silicon substrate, well below the active region, in order to provide effective electrical isolation from neighboring regions that may contain other devices. After the trenches <NUM> are etched, the silicon nitride layer <NUM> is left in place.

<FIG> illustrate the step <NUM> in greater detail, in which the trenches <NUM> are filled with an insulating material and an array of insulating columns is formed on the surface of the silicon substrate. <FIG> shows a sequence of process steps, including the steps <NUM>, <NUM>, <NUM>, and <NUM> that can be carried out to form the column structure <NUM> shown in <FIG>. The column structure <NUM> includes filled trenches <NUM> and insulating columns <NUM>.

At <NUM>, the trenches <NUM> can be filled with an insulating material such as a silicon dioxide, for example, using a standard deposition method (e.g., CVD). The filled trenches <NUM> extend above the silicon surface to approximately the top of the silicon nitride layer <NUM>.

At <NUM>, after the trenches are filled, chemical-mechanical planarization (CMP) can be performed to planarize the oxide in the filled trenches <NUM>, using the silicon nitride layer <NUM> as a polish stop layer. This technique results in the oxide trench fill and silicon nitride layer <NUM> being at a substantially equivalent height.

At <NUM>, the silicon nitride layer <NUM> is patterned again, using conventional optical lithography and etch processes as described above to produce the array of insulating columns <NUM> shown in <FIG>. When etching the silicon nitride insulating columns <NUM>, the pad oxide <NUM> can serve as an etch stop layer.

At <NUM>, an epitaxial pre-cleaning step (e.g., a hydrofluoric acid (HF) clean) can be performed to remove the pad oxide <NUM> between the nitride columns, and to prepare the underlying silicon as a nucleation surface for epitaxial growth.

<FIG> illustrate the step <NUM> in greater detail, in which spaces defined by the array of insulating columns <NUM> can be filled by epitaxial growth of various silicon compounds. Such epitaxial growth forms an array of bi-layer fins <NUM>, wherein each fin <NUM> will selectively electrically coupling a source to a drain. The bi-layer fins <NUM> are aligned substantially parallel to the filled trenches <NUM>. <FIG> shows a sequence of process steps including the steps <NUM>, <NUM>, and <NUM> that can be carried out to form the interdigitated structure <NUM> shown in <FIG>. The interdigitated structure <NUM> includes the insulating columns <NUM> and the bi-layer fins <NUM>, including upper layers <NUM> and lower layers <NUM>.

At <NUM>, the lower layers <NUM> of the bi-layer fins <NUM> can be formed by epitaxial growth of a semiconducting material. Epitaxial silicon compounds used for the lower layer <NUM> can be, for example, silicon germanium (SiGe) in which the germanium content is within the range of about <NUM>% to about <NUM>%.

At <NUM>, the upper layers <NUM> of the bi-layer fins <NUM> are desirably epitaxial silicon compounds such as, for example, silicon, SiGe, or silicon carbide (SiC). The SiGe used for the upper layers <NUM> of the bi-layer fins <NUM> can be a different composition than that used for the lower layer <NUM>. For example, the upper layers <NUM> can contain <NUM> to about <NUM>% germanium. The lower fin layer <NUM> will be made of a material that is selectively etchable with respect to the upper fin layer <NUM>. For example, pure silicon is selectively etchable with respect to a SiGe layer that is <NUM>%-<NUM>% germanium. Similarly, a lower layer <NUM> of SiGe having <NUM>% Ge is selectively etchable with respect to an upper layer <NUM> of SiGe that is in the range of <NUM>%-<NUM>% germanium. Similarly, an upper layer <NUM> that contains some carbon, such as an SiC or an SiGeC layer permits the lower layer <NUM> to be selectively etched that contains no carbon, such as Si or SiGe. A choice of epitaxial SiGe and SiC as materials making up the bi-layer fin <NUM> can produce more strain in the fin channel than is typically produced using conventional methods. Thus, each of the bi-layer fins <NUM> is formed between a pair of insulating columns, which provide localized isolation.

At <NUM>, following epitaxial growth of the bi-layer fins <NUM>, a nitride etch back step can be performed in which at least a top portion of the array of insulating columns <NUM> is removed, for example, using a phosphoric acid (H<NUM>PO<NUM>) nitride removal process that is selective to both oxide and to the epitaxially grown silicon compounds. It is desirable to etch back the nitride layer, to at least half the height of upper layer <NUM> and in some cases, to be only <NUM>%-<NUM>% along the height of the upper layer <NUM>. It is preferred to not completely remove the nitride layer since it will provide structural support to the fin <NUM> when the lower fin <NUM> is removed.

<FIG> illustrate the step <NUM> in greater detail, in which a conformal gate is deposited, overlying the interdigitated structure <NUM>. <FIG> shows a detailed sequence of process steps, including the steps <NUM>, <NUM>, and <NUM> that can be carried out to form the conformal gate structure <NUM> shown in <FIG>. The conformal gate structure <NUM> includes a gate dielectric <NUM>, a gate <NUM>, and a silicon nitride hard mask <NUM>.

At <NUM>, the gate dielectric <NUM> can be conformally deposited over the interdigitated structure <NUM>. Composition of the gate dielectric <NUM> can be silicon dioxide, having a dielectric constant of about <NUM>, or, more desirably, the gate dielectric can be a high dielectric constant (high K) material having a dielectric constant in the range of about <NUM> - <NUM> or higher. Such high dielectric constant materials include, for example, hafnium oxides and hafnium silicates. The gate dielectric <NUM> can be deposited using, for example, a thermal growth process or a CVD process.

At <NUM>, the gate <NUM> can be deposited. Composition of a bulk gate material forming the gate <NUM> may include a work function metal alloy, for example, tantalum nitride (TaN), titanium nitride (TiN), or titanium aluminum (TiAl). A conventional metal deposition process can be used to deposit the gate <NUM>, such as CVD, PVD, an electroplating process, or an electro-less plating process. Alternatively, a conventional polysilicon gate <NUM> can be deposited at <NUM>. The gate dielectric <NUM> and the gate <NUM>, together, wrap around the bi-layer fins <NUM> so that they are at least partially contiguous to three sides of each semiconducting fin. The gate <NUM> thus is operable to control current flow within the semiconducting fin in response to an applied voltage.

At <NUM>, the silicon nitride hard mask <NUM> can be deposited using conventional deposition methods. The silicon nitride hard mask <NUM> can be used to mask the conformal gate structure <NUM> and the underlying interdigitated structure <NUM> so these structures remain unaffected by subsequent processing steps intended for the source and drain regions.

<FIG> illustrate the conformal gate structure <NUM> in greater detail. <FIG> is a reproduction of <FIG>, i.e., <FIG> is a side view of the FinFET device in the gate region, along a cut line A - A', as shown in the perspective view <NUM> presented in <FIG> is a side view of the FinFET device in the source/drain regions, along a cut line B - B', as shown in the perspective view <NUM> presented in <FIG>. Because the conformal gate is not deposited over the source/drain regions, <FIG> shows the same interdigitated structure <NUM> that appears in <FIG>, prior to depositing the conformal gate structure <NUM> along A - A'.

In <FIG>, <FIG> and <FIG>, the nitride columns <NUM> are not shown at all locations to avoid obscuring the layers <NUM> and <NUM> of the fins <NUM>. Rather, only one nitride column <NUM> is shown on the far left. Also, the <FIG>, <FIG> and <FIG> are at an enlarged spacing scale and show only two of the fins <NUM> and <NUM>, again for clarity and to avoid blocking some of the features.

<FIG> illustrate the step <NUM> in greater detail, in which the interdigitated structure is removed from the source/drain regions and a void is formed between each fin and the substrate in the gate region. <FIG> shows a sequence of process steps, including the steps <NUM>, <NUM>, <NUM>, and <NUM> that can be carried out to form voids <NUM> in place of the lower fin layer <NUM> within the conformal gate structure <NUM> (<FIG>), and the fin-less structure <NUM> in the source/drain regions (<FIG>). A perspective view <NUM> of the fin-less structure <NUM> is visible in <FIG>.

At <NUM>, a conventional spacer is deposited on both sides of the conformal gate structure <NUM>. (The spacer does not appear in either one of the side views, because it lies between the cut lines A - A' and B - B'. ) A sidewall spacer of this type is known in the art and therefore would be understood.

At <NUM>, the array of insulating columns <NUM> is then removed from the source/drain regions only, by masking the gate regions and the etching. Alternatively an anisotropic etch that is a plasma etch (RIE) process can be used to remove SiN with high selectivity to oxide and silicon using the gate as an etch mask.

At <NUM>, the upper layers <NUM> of the bi-layer fin channels are removed in the source/drain regions. Removal of the upper layers <NUM> of the fin channels can be achieved by using a timed, anisotropic plasma etch process (RIE). Selectivity to the lower layers <NUM> is not critical, because the entire interdigitated structure in the source/drain regions is sacrificial.

At <NUM>, the lower layers <NUM> of the bi-layer fin channels are removed from both the source/drain regions (<FIG>) and also at the gate regions (<FIG>) to form voids <NUM> in the gate region. The voids <NUM> provide an insulating layer between the upper layers <NUM> and the substrate. The voids <NUM> can be formed using a non-plasma chemical vapor etch process. Such a process is substantially isotropic. To achieve a desired selectivity to the upper layers <NUM> in the gate region, the vapor chemistry used may include hydrochloric acid (HCL). In such a process, selectivity to the upper layers <NUM> in the gate region may vary based on factors including temperature and pressure of the chemical vapor etch, and relative germanium concentrations of the epitaxial upper and lower layers <NUM> and <NUM>, respectively. Although the lower layers <NUM> of the bi-layer fins <NUM> in the gate regions are covered, and therefore they are not accessible from above, the lower layers <NUM> will be undercut laterally by the chemical vapor etchant without disturbing surrounding structures because the HCL etch can be formulated so as to be selective to oxide, nitride, and certain compositions of epitaxial silicon compounds. As previously stated, the compound for the lower layer <NUM> is selected to permit epitaxial growth from the substrate <NUM> to grow layer <NUM> as single crystal and to be selectively etchable with respect to layer <NUM>.

<FIG> illustrate the steps <NUM> and <NUM> in greater detail, in which the voids <NUM> are filled in the gate region and an epitaxial raised source and drain are formed. <FIG> shows a sequence of process steps, including the steps <NUM>, <NUM>, and <NUM>, that can be carried out to form a completed fin structure <NUM> in the gate region (<FIG>) and a completed epitaxial raised source/drain structure <NUM> (<FIG>). A perspective view <NUM> of the finished isolated channel FinFET device is shown in <FIG>.

With reference to <FIG> and <FIG>, at <NUM>, the voids <NUM> can be filled with an insulating material, for example, an oxide <NUM>, to substantially block electric charge leakage between the semiconducting fins and the substrate. The oxide <NUM> provides a more structurally stable substrate insulating layer than the voids <NUM>. The oxide <NUM> can be formed by thermal growth from the silicon substrate surface by exposure to an oxygenated environment at high temperature.

At <NUM>, the remaining pad oxide <NUM> can be etched away using an isotropic, top-down directed oxide etch process that is selective to the silicon nitride hard mask <NUM>. Thus, the pad oxide <NUM> can be removed in the exposed source/drain regions (<FIG>) while the gate region remains unaffected (<FIG>).

At <NUM>, a pre-clean can be performed to remove residual oxide, including native oxide, from the silicon surface <NUM> to prepare the silicon surface <NUM> for epitaxial growth.

At <NUM>, a raised source/drain <NUM> can be grown epitaxially from the silicon surface <NUM>, directly after the pre-clean. The presence of pristine <NUM> crystalline structure at the silicon surface <NUM> tends to facilitate epitaxial growth. There are many possible choices for the composition of the epitaxial raised source/drain <NUM>, for example, epitaxial silicon, an in-situ-doped epitaxial SiGe layer, or an implanted epitaxial SiC layer, among others. Formation of the raised source/drain structure <NUM> completes the isolated channel FinFET device.

The various embodiments described above can be combined to provide further embodiments.

It will be appreciated that, although specific embodiments of the present disclosure are described herein for purposes of illustration, various modifications may be made without departing from the scope of the present disclosure. Accordingly, the present disclosure is not limited except as by the appended claims.

Claim 1:
A method of forming a fin field-effect transistor on a silicon substrate (<NUM>, <NUM>), the method comprising:
forming an interdigitated structure within an active region of the silicon substrate, the interdigitated structure including an array of insulating columns (<NUM>) interdigitated with an array of semiconducting fins (<NUM>), each semiconductor fin of the array of semiconducting fins (<NUM>) having a lower portion (<NUM>) and an upper portion (<NUM>), wherein the lower portion (<NUM>) is selectively etchable with respect to the upper portion (<NUM>);
depositing a conformal gate (<NUM>) overlying the semiconducting fins (<NUM>), the conformal gate being at least partially contiguous to three sides of each semiconducting fin (<NUM>);
outside the conformal gate (<NUM>), removing the interdigitated structure to expose the silicon substrate (<NUM>, <NUM>);
selectively etching and replacing the lower portion (<NUM>) of each semiconducting fin (<NUM>) with an insulating material (<NUM>) to electrically isolate from the silicon substrate (<NUM>, <NUM>) the remaining upper portion (<NUM>) of the semiconducting fin (<NUM>); and
growing an epitaxial source and drain (<NUM>) from the silicon substrate (<NUM>, <NUM>),
wherein the conformal gate (<NUM>) is configured such that a voltage operatively applied to the gate (<NUM>) influences a current flow within the semiconducting fin (<NUM>).