Patent Description:
The present disclosure relates to a display device, and more particularly, to a stretchable display device including a protection layer that protects pixels.

Display devices employed by the monitor of a computer, a TV, a mobile phone or the like include an organic light emitting display (OLED) that emits light by itself, and a liquid crystal display (LCD) that requires a separate light source.

As the display devices have been increasingly applied to diverse fields such as a computer monitor, a TV, and a personal mobile device, display devices having a large active area and a reduced volume and weight have been studied.

Recently, a display device in which display elements, lines, etc. are formed on a flexible substrate made of flexible plastic and which can be stretched in a specific direction and manufactured in various shapes has attracted attention as a next-generation display device. <CIT> describes a stretchable display device. The stretchable display device includes: a lower substrate comprising a plurality of first areas on which a plurality of sub-pixels is defined and spaced apart from one another, a plurality of second areas in which a plurality of connection lines connecting between adjacent ones of the first areas is disposed, and a plurality of third areas other than the first areas and the second areas; a plurality of additional sub-pixels disposed in the third areas, respectively; and a plurality of piezoelectric patterns electrically connected to the additional sub-pixels, respectively. The stretchable display device can suppress deterioration of image quality when it is stretched. <CIT> describes a stretchable display device which includes a flexible substrate. A plurality of first substrates and a plurality of second substrates are disposed on the substrate. The plurality of first substrates are spaced from each other and the plurality of second substrates, and the plurality of second substrates are spaced from each other. A plurality of connection supports are coupled to the plurality of first and second substrates. Connection lines extend on the plurality of connection supports to form an electrical connection between the plurality of first substrates and the plurality of second substrates. A distance between one of the plurality of second substrates and a corresponding outer one of the plurality of first substrates is greater than a distance between the plurality of first substrates to reduce stress on the plurality of second substrates during bending or stretching of the display device.

An object to be achieved by the present disclosure is to provide a display device which is not damaged even when stretched repeatedly.

Another object to be achieved by the present disclosure is to provide a display device in which light extraction efficiency can be improved.

Yet another object to be achieved by the present disclosure is to provide a display device in which misalignment of light emitting diodes can be suppressed.

Objects of the present disclosure are not limited to the above-mentioned objects, and other objects, which are not mentioned above, can be clearly understood by those skilled in the art from the following descriptions.

The objects are solved by the features of independent claim <NUM>.

According to the present invention, the display device includes: a stretchable lower substrate and a plurality of first substrates disposed on the lower substrate. The display device also includes a plurality of second substrates connecting first substrates adjacent to each other among the plurality of first substrates. The display device further includes a plurality of pixels disposed on the plurality of first substrates. The display device also includes a plurality of connection lines disposed on the plurality of second substrates and connecting the plurality of pixels. The display device further includes a protection layer disposed on each of the plurality of pixels, wherein the protection layer includes a plurality of patterns each having a triangular cross-section.

According to another aspect of the present disclosure, the display device includes: a ductile substrate that is reversibly expandable and contractible, a plurality of rigid substrates disposed to be spaced apart from each other on the ductile substrate, a plurality of pixels disposed on the plurality of rigid substrates, a plurality of connection lines disposed on the plurality of rigid substrates and connecting the plurality of pixels, a protection layer covering the plurality of pixels and a plurality of tips of the protection layer disposed outside the connection lines.

Other detailed matters of the exemplary embodiments are included in the detailed description and the drawings. The following optional features can be combined with any one of the above mentioned aspect alone or in combination.

In one or more preferred embodiments, the plurality of connection lines may be extended on the plurality of first substrates.

In one or more preferred embodiments, the protection layer may overlap the plurality of connection lines.

In one or more preferred embodiments, the plurality of connection lines may extend on the plurality of first substrates.

In one or more preferred embodiments, the protection layer may not overlap the plurality of connection lines.

In one or more preferred embodiments, the plurality of pixels may include an LED that emits light and/or a bank defining the plurality of pixels.

In one or more preferred embodiments, the display device may include an upper substrate that is stretchable and may be disposed on the protection layer.

In one or more preferred embodiments, there is a contact area between the protection layer and the upper substrate.

The contact areas are smaller than a contact area between the protection layer and the LED and the bank.

In one or more preferred embodiments, there is no step difference between an upper surface of the LED and an upper surface of the bank.

In other words, the height of the upper surface of the LED and an upper surface of the bank may be the same.

In one or more preferred embodiments, there may be a step difference between an upper surface of the LED and an upper surface of the bank.

In one or more preferred embodiments, the display device may further comprise a plurality of protrusions disposed on at least two sides of the plurality of pixels.

In one or more preferred embodiments, the plurality of protrusions may be an embossed pattern protruding from the protection layer and/or may be in contact with a side surface of the LED.

In one or more preferred embodiments, the plurality of tips may not overlap the plurality of connection lines.

In one or more preferred embodiments, the protection layer may include a plurality of prism patterns or a plurality of regular tetrahedral patterns.

In one or more preferred embodiments, the display device may further comprise a plurality of protrusions protruding downwards from the protection layer.

In one or more preferred embodiments, the plurality of protrusions may be in contact with an LED included in each of the plurality of pixels.

According to the present disclosure, when a display device is repeatedly stretched, a light emitting diode (LED) is not damaged. Thus, stretching reliability can be improved.

According to the present disclosure, light extraction efficiency is increased. Thus, the luminance of the display device can be improved.

According to the present disclosure, the LED can be transferred more precisely. Thus, the yield of the transfer process can be improved.

The advantages and features of the present disclosure, and methods for accomplishing the same will be more clearly understood from exemplary embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following exemplary embodiments but may be implemented in various different forms. The exemplary embodiments are provided only to complete disclosure of the present disclosure and to fully provide a person with ordinary skill in the art to which the present disclosure pertains with the category of the present disclosure, and the present disclosure will be defined by the appended claims.

The shapes, dimensions, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Further, in the following description of the present disclosure, a detailed explanation of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. The terms such as "including," "having," and "consist of' used herein are generally intended to allow other components to be added unless the terms are used with the term "only". Any references to singular may include plural unless expressly stated otherwise.

When an element or layer is referred to as being "on" another element or layer, it may be directly on the other element or layer, or intervening elements or layers may be present.

Throughout the whole specification, the same reference numerals denote the same elements.

Since the dimensions and thickness of each component illustrated in the drawings are represented for convenience in explanation, the present disclosure is not necessarily limited to the illustrated dimensions and thickness of each component.

The features of various embodiments of the present disclosure can be partially or entirely coupled to or combined with each other and can be interlocked and operated in technically various ways, and the embodiments can be carried out independently of or in association with each other.

Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

A display device is capable of displaying an image even when bent or stretched and may be referred to as a stretchable display device. The display device may have higher flexibility than conventional typical display devices and may have stretchability. Thus, the display device can be freely deformed by a user's manipulation such as bending or stretching of the display device. For example, when the user seizes an end of the display device and pulls the display device, the display device may be stretched in a direction of being pulled by the user. When the user places the display device on an uneven external surface, the display device may be bent along the shape of the external surface of a wall surface. Also, when force applied by the user is removed, the display device can be restored to its original shape.

<FIG> is an exploded perspective view of a display device according to an exemplary embodiment of the present disclosure. Referring to <FIG>, a display device <NUM> includes a lower substrate <NUM>, an upper substrate <NUM>, a plurality of first substrates <NUM>, a plurality of second substrates <NUM>, a plurality of third substrates <NUM>, <NUM> and a printed circuit board <NUM>. Also, the display device <NUM> includes a plurality of pixels PX, a gate driver GD and a data driver DD.

The lower substrate <NUM> is a substrate for supporting and protecting various components of the display device <NUM>. Further, the upper substrate <NUM> is a substrate for covering and protecting various components of the display device <NUM>.

Each of the lower substrate <NUM> and the upper substrate <NUM> is a ductile substrate. It is made of a bendable or stretchable insulating material. For example, each of the lower substrate <NUM> and the upper substrate <NUM> may be made of silicone rubber such as polydimethylsiloxane (PDMS) and an elastomer such as polyurethane (PU), polytetrafluoroethylene (PTFE) or the like. Each of the lower substrate <NUM> and the upper substrate <NUM> may have flexible properties. Further, the lower substrate <NUM> and the upper substrate <NUM> may be made of the same material, but are not limited thereto and could be made of different materials.

Each of the lower substrate <NUM> and the upper substrate <NUM> is a ductile substrate and may be reversibly expandable and contractible. Thus, the lower substrate <NUM> may also be referred to as a lower ductile substrate or a first ductile substrate.

The upper substrate <NUM> may also be referred to as an upper ductile substrate or a second ductile substrate.

The lower substrate <NUM> and the upper substrate <NUM> may have a modulus of elasticity in the range of several to hundreds of MPa.

The lower substrate <NUM> and the upper substrate <NUM> may have a ductile breaking rate of <NUM>% or more. Herein, the ductile breaking rate refers to an extension distance when an object to be stretched is broken or cracked.

The lower substrate may have a thickness of <NUM> to <NUM>, but is not limited thereto.

The lower substrate <NUM> may have an active area AA and a non-active area NA surrounding the active area AA.

The active area AA is an area where an image is displayed on the display device <NUM>. The plurality of pixels PX is disposed in the active area AA.

Each pixel PX may include a display element and various driving elements for driving the display element. The various driving elements may refer to at least one thin film transistor (TFT) and a capacitor, but are not limited thereto. Each of the plurality of pixels PX may be connected to various lines. For example, each of the plurality of pixels PX may be connected to various lines such as a gate line, a data line, a high-potential power line, a low-potential power line and a reference voltage line.

A protection layer may be disposed on each of the pixels PX to protect each pixel PX.

The non-active area NA is an area where an image is not displayed. The non-active area NA may be an area disposed adjacent to the active area AA and at least partly or fully surrounding the active area AA, but is not limited thereto. The non-active area NA is an area of the lower substrate <NUM> except the active area AA. It may be transformed and separated in various shapes. In the non-active area NA, driving elements for driving the plurality of pixels PX disposed in the active area AA may be disposed. In the non-active area NA, the gate driver GD including on ero more chips may be disposed. Further, in the non-active area NA, a plurality of pads connected to the gate driver GD and/or the data driver DD may be disposed. Each of the pads may be connected to one or more of the plurality of pixels PX disposed in the active area AA.

On the lower substrate <NUM>, the plurality of first substrates <NUM>, the plurality of second substrates <NUM> and the plurality of third substrates <NUM>, <NUM> are disposed.

The plurality of first substrates <NUM> is disposed in the active area AA of the lower substrate <NUM>, and the plurality of pixels PX is disposed on the plurality of first substrates <NUM>. So, each of the plurality of first substrates <NUM> may include one or more pixels PX. Further, the plurality of third substrates <NUM>, <NUM> is disposed in the non-active area NA of the lower substrate <NUM>. The gate driver GD and/or the plurality of pads are formed on the plurality of third substrates <NUM>, <NUM>.

As shown in <FIG>, the gate driver GD may be mounted on a third substrate <NUM> located on one side of an X-axis direction of the active area AA among the plurality of third substrates <NUM>, <NUM>. The gate driver GD may be formed on the third substrate <NUM> in a gate in panel (GIP) manner when various components on a first substrate <NUM> are fabricated. Accordingly, various circuit components constituting the gate driver GD, such as various transistors, capacitors, lines and the like, may be disposed on the plurality of third substrates <NUM>, <NUM>. However, the present disclosure is not limited thereto. The gate driver GD may be mounted in a chip on film (COF) manner. Also, the plurality of third substrates <NUM>, <NUM> may be disposed in the non-active area NA located on the other side of the X-axis direction of the active area AA. The gate drivers GD may also be mounted on the plurality of third substrates <NUM>, <NUM> located on the other side of the X-axis direction of the active area AA.

Referring to <FIG>, the plurality of third substrates <NUM>, <NUM> may be greater in size than the plurality of first substrates <NUM>. Specifically, each of the plurality of third substrates <NUM>, <NUM> may be greater in size than each of the plurality of first substrates <NUM>. As described above, the gate driver GD may be disposed on each of the plurality of third substrates <NUM>, <NUM>. For example, one stage of the gate driver GD may be disposed on each of the plurality of third substrates <NUM>, <NUM>. Accordingly, the area of various circuit components constituting one stage of the gate driver GD is relatively greater than the area of a first substrate <NUM> on which a pixel PX is disposed. Therefore, each of the plurality of third substrates <NUM>, <NUM> may be greater in size than each of the plurality of first substrates <NUM>.

<FIG> illustrates that the plurality of third substrates <NUM> is disposed on one side of a Y-axis direction and third substrates <NUM> one side of the X-axis direction in the non-active area NA. However, the present disclosure is not limited thereto. The plurality of third substrates <NUM>, <NUM> may be disposed in any portion of the non-active area NA. Also, <FIG> illustrates that each of the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM> has a quadrangular shape. However, the present disclosure is not limited thereto. Each of the plurality of first substrates <NUM> and/or the plurality of third substrates <NUM>, <NUM> may have various shapes.

Each of the plurality of second substrates <NUM> connects first substrates <NUM> adjacent to each other, third substrates <NUM> adjacent to each other, or a first substrate <NUM> and a third substrate <NUM>, <NUM> adjacent to each other. Thus, each of the plurality of second substrates <NUM> may also be referred to as a connection substrate. That is, the plurality of second substrates <NUM> is disposed between the plurality of first substrates <NUM>, between the plurality of third substrates <NUM>, <NUM>, or between the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM>.

The distance between the adjacent first substrates <NUM> may be larger or the same than the dimension of the first substrate <NUM> in the same direction X or Y.

Referring to <FIG>, the plurality of second substrates <NUM> has a curved shape. For example, the plurality of second substrates <NUM> may have a sine wave shape. However, the shape of the plurality of second substrates <NUM> is not limited thereto. The plurality of second substrates <NUM> may have various shapes. For example, the plurality of second substrates <NUM> may be extended in a zigzag manner, or a plurality of diamond-shaped substrates may be extended by being connected to each other at their vertices. The number and shape of the plurality of second substrates <NUM> shown in <FIG> are provided by way of example. The number and shape of the plurality of second substrates <NUM> may vary depending on the design.

The plurality of first substrates <NUM>, the plurality of second substrates <NUM> and the plurality of third substrates <NUM>, <NUM> are rigid substrates. That is, the plurality of first substrates <NUM>, the plurality of second substrates <NUM> and the plurality of third substrates <NUM>, <NUM> are more rigid than the lower substrate <NUM> and/or the upper substrate. The plurality of first substrates <NUM>, the plurality of second substrates <NUM> and the plurality of third substrates <NUM>, <NUM> may be higher in modulus of elasticity than the lower substrate <NUM>. The modulus of elasticity is a parameter showing the ratio of deformation of a substrate caused by a stress applied to the substrate, and when the modulus of elasticity is relatively high, the hardness may be relatively high. Thus, a first substrate <NUM>, a second substrate <NUM> and a third substrate <NUM> may also be referred to as a first rigid substrate, a second rigid substrate and a third rigid substrate, respectively. The modulus of elasticity of the plurality of first substrates <NUM>, the plurality of second substrates <NUM> and the plurality of third substrates <NUM>, <NUM> may be <NUM> times or more higher than that of the lower substrate <NUM>, but is not limited thereto.

The plurality of first substrates <NUM>, the plurality of second substrates <NUM> and the plurality of third substrates <NUM>, <NUM> which are rigid substrates may be made of a plastic material having less flexibility than the lower substrate <NUM>. For example, the plurality of first substrates <NUM>, the plurality of second substrates <NUM> and the plurality of third substrates <NUM>, <NUM> may be made of polyimide (PI), polyacrylate, polyacetate or the like. Here, the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM> may be made of the same material, but are not limited thereto. The plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM> may also be made of different materials from each other.

In some exemplary embodiments, the lower substrate <NUM> may be defined as including a plurality of first lower patterns and a second lower pattern. The plurality of first lower patterns may be disposed in an area of the lower substrate <NUM> which overlaps the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM>. Also, the second lower pattern may be disposed in an area excluding the area where the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM> are disposed. Otherwise, the second lower pattern may be disposed in the entire area of the display device <NUM>.

In this case, the plurality of first lower patterns may have a higher modulus of elasticity than the second lower pattern. For example, the plurality of first lower patterns may be made of the same material as the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM>. Also, the second lower pattern may be made of a material having a lower modulus of elasticity than the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM>. Thus, the first and the second lower patterns might be used to reinforce the substrate or to adapt the flexibility of the substrate.

That is, the first lower patterns may be made of polyimide (PI), polyacrylate, polyacetate or the like. The second lower pattern may be made of silicone rubber such as polydimethylsiloxane (PDMS) and an elastomer such as polyurethane (PU), polytetrafluoroethylene (PTFE) or the like.

The gate driver GD is a component for supplying a gate voltage to the plurality of pixels PX disposed in the active area AA. The gate driver GD includes a plurality of stages formed on the plurality of third substrates <NUM>, <NUM>. The stages of the gate driver GD may be electrically connected to each other. Therefore, a gate voltage output from one stage may be transferred to another stage. Also, each stage may sequentially supply a gate voltage to the plurality of pixels PX connected to the stage.

A power supply may be connected to the gate driver GD and may supply a gate driving voltage and a gate clock voltage to the gate driver GD. Further, the power supply may be connected to the plurality of pixels PX and may supply a pixel driving voltage to each of the plurality of pixels PX. That is, the power supply may also be formed on the plurality of third substrates <NUM>, <NUM>. The power supply may be formed adjacent to the gate driver GD on an outer substrate (not illustarted). Furthermore, power supplies formed on the plurality of third substrates <NUM>, <NUM> may be electrically connected to each other. That is, a plurality of power supplies formed on the plurality of third substrates <NUM>, <NUM> may be connected by a gate power connection line and a pixel power connection line. Thus, each of the plurality of power supplies may supply a gate driving voltage, a gate clock voltage and a pixel driving voltage.

The printed circuit board <NUM> is configured to transfer a signal and voltage for driving a display element from a controller to the display element. Thus, the printed circuit board <NUM> may also be referred to as a driving substrate. On the printed circuit board <NUM>, the controller such as an IC chip, a circuit or the like may be mounted. Further, on the printed circuit board <NUM>, a memory, a processor or the like may also be mounted. The printed circuit board <NUM> provided in the display device <NUM> may include a stretchable area and a non-stretchable area to secure stretchability. Also, on the non-stretchable area, an IC chip, a circuit, a memory, a processor or the like may be mounted. Further, in the stretchable area, lines electrically connected to the IC chip, the circuit, the memory and the processor may be disposed. Furthermore, the printed circuit board <NUM> may be bonded to the plurality of pads of the plurality of third substrates <NUM>, <NUM> disposed in the non-active area NA.

The data driver DD is a component that supplies a data voltage to the plurality of pixels PX disposed in the active area AA. The data driver DD may be configured as an IC chip and thus may also be referred to as a data integrated circuit (D-IC). Also, the data driver DD may be provided in the non-stretchable area of the printed circuit board <NUM>. That is, the data driver DD may be mounted on the printed circuit board <NUM> in a chip on board (COB) manner. Further, the data driver DD supplies a data voltage or the like to each of the plurality of pixels PX disposed in the active area AA through the plurality of pads disposed on the plurality of third substrates <NUM>, <NUM>. <FIG> illustrates that the data driver DD is mounted in the COB manner. However, the present disclosure is not limited thereto. The data driver DD may be mounted in the COF manner, the COG manner or a tape carrier package (TCP) manner.

Also, <FIG> illustrates that a third substrate <NUM> is disposed in the non-active area AA on an upper side of the active area AA so as to correspond to a first substrate <NUM> disposed on a row in the active area AA. Further, <FIG> illustrates that a data driver DD is disposed on the printed circuit board <NUM> being connected to a third substrate <NUM>. However, the present disclosure is not limited thereto. That is, a third substrate <NUM> and a data driver DD may be disposed so as to correspond to first substrates <NUM> disposed on a plurality of rows.

Hereinafter, the active area AA of the display device <NUM> according to an exemplary embodiment of the present disclosure will be described in more detail with reference to <FIG> and <FIG>.

<FIG> is an enlarged plan view of an active area of the display device according to an exemplary embodiment of the present disclosure. <FIG> is a schematic cross-sectional view as taken along a line III-III' of <FIG>. For the convenience of description, <FIG> will also be referred to hereinafter.

Referring to <FIG> and <FIG>, the plurality of first substrates <NUM> is disposed on the lower substrate <NUM> in the active area AA. The plurality of first substrates <NUM> is disposed to be spaced apart from each other on the lower substrate <NUM>. For example, the plurality of first substrates <NUM> may be disposed in a matrix form on the lower substrate <NUM> as shown in <FIG>, but is not limited thereto.

Referring to <FIG> and <FIG>, a pixel including a plurality of sub-pixels SPX is disposed on the first substrate <NUM>. Also, each of the sub-pixels SPX may include an LED <NUM>, which is a display element and a driving transistor <NUM> and a switching transistor <NUM> for driving the LED <NUM>. However, a display element in each sub-pixel SPX is not limited to the LED and may be an organic light emitting diode. Further, the plurality of sub-pixels SPX may include a red sub-pixel, a green sub-pixel and a blue sub-pixel, but is not limited thereto. The plurality of sub-pixels SPX may include various color pixels as needed (e.g. white color).

The plurality of sub-pixels SPX may be connected to a plurality of connection lines <NUM>. The plurality of sub-pixels SPX may be electrically connected to first connection lines <NUM> extended in the X-axis direction. Also, the plurality of sub-pixels SPX may be electrically connected to second connection lines <NUM> extended in the Y-axis direction.

Further, a protection layer <NUM> is disposed on the pixel PX including the plurality of sub-pixels SPX to cover the pixel PX including the plurality of sub-pixels SPX. Specifically, as shown in <FIG>, the protection layer <NUM> overlaps the plurality of sub-pixels SPX and may also overlap the plurality of connection lines <NUM> extended on the first substrate <NUM>. Furthermore, a shape of the protection layer <NUM> is illustrated as a quadrangular pattern which is the same as a shape of the first substrate <NUM>, but is not limited thereto. The protection layer <NUM> may have various shapes on the first substrate <NUM>.

Hereinafter, a cross-sectional structure of the display area will be described in detail with reference to <FIG>.

Referring to <FIG>, a plurality of inorganic insulating layers is disposed on the plurality of first substrates <NUM>. For example, the plurality of inorganic insulating layers may include a buffer layer <NUM>, a gate insulating layer <NUM>, a first interlayer insulating layer <NUM>, a second interlayer insulating layer <NUM> and a passivation layer <NUM>. However, the present disclosure is not limited thereto. Various inorganic insulating layers may be disposed on the plurality of first substrates <NUM>. One or more of the buffer layer <NUM>, the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM> and the passivation layer <NUM> may be omitted.

Specifically, the buffer layer <NUM> is disposed on the plurality of first substrates <NUM>. The buffer layer <NUM> is formed on the plurality of first substrates <NUM> to protect various components of the display device <NUM> against permeation of moisture (H<NUM>O) and oxygen (O<NUM>) from the outside of the lower substrate <NUM> and the plurality of first substrates <NUM>. The buffer layer <NUM> may be made of an insulating material. For example, the buffer layer <NUM> may be formed as a single layer or a plurality of layers of at least one of silicon nitride (SiNx), silicon oxide (SiOx) and silicon oxynitride (SiON). However, the buffer layer <NUM> may be omitted depending on the structure or characteristics of the display device <NUM>.

In this case, the buffer layer <NUM> may be formed only in an area where the buffer layer <NUM> overlaps the plurality of first substrates <NUM> and/or the plurality of third substrates <NUM>, <NUM>. As described above, the buffer layer <NUM> may be made of an inorganic material. Thus, the buffer layer <NUM> may be easily damaged, such as easily cracked, while the display device <NUM> is stretched. Therefore, the buffer layer <NUM> may not be formed in areas between the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM>. The buffer layer <NUM> may be patterned into the shapes of the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM> and formed only on upper portions of the plurality of first substrates <NUM> and/or the plurality of third substrates <NUM>, <NUM>. Accordingly, in the display device <NUM> according to an exemplary embodiment of the present disclosure, the buffer layer <NUM> is formed only in the area where the buffer layer <NUM> overlaps the plurality of first substrates <NUM> and/or the plurality of third substrates <NUM>, <NUM> which are rigid substrates. Thus, it is possible to suppress damage to the buffer layer <NUM> even when the display device <NUM> is deformed, such as bent or stretched. the buffer layer <NUM> is formed only in the area of the rigid first and/or third substrates <NUM>, <NUM>.

Referring to <FIG>, the switching transistor <NUM> including a gate electrode <NUM>, an active layer <NUM>, a source electrode <NUM> and a drain electrode <NUM> is formed on the buffer layer <NUM>. Also, the driving transistor <NUM> including a gate electrode <NUM>, an active layer <NUM>, a source electrode and a drain electrode <NUM> is formed on the buffer layer <NUM>.

Referring to <FIG>, the active layer <NUM> of the switching transistor <NUM> and the active layer <NUM> of the driving transistor <NUM> are disposed on the buffer layer <NUM>. For example, each of the active layer <NUM> of the switching transistor <NUM> and the active layer <NUM> of the driving transistor <NUM> may be made of an oxide semiconductor. Alternatively, each of the active layer <NUM> of the switching transistor <NUM> and the active layer <NUM> of the driving transistor <NUM> may be made of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), an organic semiconductor or the like.

The gate insulating layer <NUM> is disposed on the active layer <NUM> of the switching transistor <NUM> and the active layer <NUM> of the driving transistor <NUM>. The gate insulating layer <NUM> is configured to electrically insulate the gate electrode <NUM> of the switching transistor <NUM> from the active layer <NUM> of the switching transistor <NUM> and electrically insulate the gate electrode <NUM> of the driving transistor <NUM> from the active layer <NUM> of the driving transistor <NUM>. Further, the gate insulating layer <NUM> may be made of an insulating material. For example, the gate insulating layer <NUM> may be formed as a single inorganic layer or a plurality of inorganic layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

The gate electrode <NUM> of the switching transistor <NUM> and the gate electrode <NUM> of the driving transistor <NUM> are disposed on the gate insulating layer <NUM>. The gate electrode <NUM> of the switching transistor <NUM> and the gate electrode <NUM> of the driving transistor <NUM> are disposed to be spaced apart from each other on the gate insulating layer <NUM>. Further, the gate electrode <NUM> of the switching transistor <NUM> overlaps the active layer <NUM> of the switching transistor <NUM>. The gate electrode <NUM> of the driving transistor <NUM> overlaps the active layer <NUM> of the driving transistor <NUM>.

Each of the gate electrode <NUM> of the switching transistor <NUM> and the gate electrode <NUM> of the driving transistor <NUM> may be made of any one of various metal materials, for example, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). Alternatively, each of the gate electrode <NUM> of the switching transistor <NUM> and the gate electrode <NUM> of the driving transistor <NUM> may be made of an alloy of two or more of them, or a plurality of layer thereof, but is not limited thereto.

The first interlayer insulating layer <NUM> is disposed on the gate electrode <NUM> of the switching transistor <NUM> and the gate electrode <NUM> of the driving transistor <NUM>. The first interlayer insulating layer <NUM> insulates the gate electrode <NUM> of the driving transistor <NUM> from an intermediate metal layer IM. The first interlayer insulating layer <NUM> may also be made of an inorganic material like the buffer layer <NUM>. For example, the first interlayer insulating layer <NUM> may be formed as a single inorganic layer or a plurality of inorganic layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

The intermediate metal layer IM is disposed on the first interlayer insulating layer <NUM>. Further, the intermediate metal layer IM overlaps the gate electrode <NUM> of the driving transistor <NUM>. Thus, a storage capacitor is formed in an area where the intermediate metal layer IM overlaps the gate electrode <NUM> of the driving transistor <NUM>. Specifically, the gate electrode <NUM> of the driving transistor <NUM>, the first interlayer insulating layer <NUM> and the intermediate metal layer IM form the storage capacitor. However, the position of the intermediate metal layer IM is not limited thereto. The intermediate metal layer IM may overlap another electrode to form a storage capacitor in various ways.

The intermediate metal layer IM may be made of any one of various metal materials, for example, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). Alternatively, the intermediate metal layer IM may be made of an alloy of two or more of them, or a plurality of layer thereof, but is not limited thereto.

The second interlayer insulating layer <NUM> is disposed on the intermediate metal layer IM. The second interlayer insulating layer <NUM> insulates the gate electrode <NUM> of the switching transistor <NUM> from the source electrode <NUM> and the drain electrode <NUM> of the switching transistor <NUM>. Also, the second interlayer insulating layer <NUM> insulates the intermediate metal layer IM from the source electrode and the drain electrode <NUM> of the driving transistor <NUM>. The second interlayer insulating layer <NUM> may also be made of an inorganic material like the buffer layer <NUM>. For example, the first interlayer insulating layer <NUM> may be formed as a single inorganic layer or a plurality of inorganic layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

The source electrode <NUM> and the drain electrode <NUM> of the switching transistor <NUM> are disposed on the second interlayer insulating layer <NUM>. Also, the source electrode and the drain electrode <NUM> of the driving transistor <NUM> are disposed on the second interlayer insulating layer <NUM>. The source electrode <NUM> and the drain electrode <NUM> of the switching transistor <NUM> are disposed to be spaced apart from each other on the same layer. Although <FIG> does not illustrate the source electrode of the driving transistor <NUM>, the source electrode and the drain electrode <NUM> of the driving transistor <NUM> are also disposed to be spaced apart from each other on the same layer. In the switching transistor <NUM>, the source electrode <NUM> and the drain electrode <NUM> may be electrically connected to the active layer <NUM> to be in contact with the active layer <NUM>. Also, in the driving transistor <NUM>, the source electrode and the drain electrode <NUM> may be electrically connected to the active layer <NUM> to be in contact with the active layer <NUM>. Further, the drain electrode <NUM> of the switching transistor <NUM> may be electrically connected to the gate electrode <NUM> of the driving transistor <NUM> to be in contact with the gate electrode <NUM> of the driving transistor <NUM>.

The source electrode <NUM> and the drain electrodes <NUM> and <NUM> may be made of any one of various metal materials, for example, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). Alternatively, the source electrode <NUM> and the drain electrodes <NUM> and <NUM> may be made of an alloy of two or more of them, or a plurality of layer thereof, but are not limited thereto.

In the present disclosure, the driving transistor <NUM> has been described as having a coplanar structure, but various types of transistor having a staggered structure or the like may also be used.

Although not shown in <FIG>, a gate pad and a data pad may be disposed on the second interlayer insulating layer <NUM>. The gate pad serves to transfer a gate voltage to the plurality of sub-pixels SPX. The gate voltage may be transferred from the gate pad to the gate electrode <NUM> of the switching transistor <NUM> through a gate line formed on the first substrate <NUM>. The data pad serves to transfer a data voltage to the plurality of sub-pixels SPX. The data voltage may be transferred from the data pad to the source electrode <NUM> of the switching transistor <NUM> through a data line formed on the first substrate <NUM>. The gate pad and the data pad may be made of the same material as the source electrode <NUM> and the drain electrodes <NUM> and <NUM>, but are not limited thereto.

Referring to <FIG>, the passivation layer <NUM> is formed on the switching transistor <NUM> and the driving transistor <NUM>. That is, the passivation layer <NUM> covers the switching transistor <NUM> and the driving transistor <NUM> to protect the switching transistor <NUM> and the driving transistor <NUM> against permeation of moisture and oxygen. The passivation layer <NUM> may be made of an inorganic material and formed as a single layer or a plurality of layers, but is not limited thereto.

Any or all of the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM> and the passivation layer <NUM> may be patterned and formed only in an area where they overlap the plurality of first substrates <NUM>. The gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM> and the passivation layer <NUM> may also be made of an inorganic material like the buffer layer <NUM>. Thus, the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM> and the passivation layer <NUM> may be easily damaged, such as easily cracked, while the display device <NUM> is stretched. Therefore, the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM> and the passivation layer <NUM> may not be formed in areas between the plurality of first substrates <NUM> or outside of the first substrates <NUM>. The gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM> and the passivation layer <NUM> may be patterned into the shapes of the plurality of first substrates <NUM> and formed only on upper portions of the plurality of first substrates <NUM>.

A planarization layer <NUM> is formed on the passivation layer <NUM>. The planarization layer <NUM> serves to flatten upper portions of the switching transistor <NUM> and the driving transistor <NUM>. The planarization layer <NUM> may be formed as a single layer or a plurality of layers and may be made of an organic material. Thus, the planarization layer <NUM> may also be referred to as an organic insulating layer. For example, the planarization layer <NUM> may be made of an acrylic organic material, but is not limited thereto.

Referring to <FIG>, the planarization layer <NUM> is disposed on the plurality of first substrates <NUM> so as to cover upper surfaces and side surfaces of the buffer layer <NUM>, the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM> and the passivation layer <NUM>. Further, the planarization layer <NUM> surrounds the buffer layer <NUM>, the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM> and the passivation layer <NUM> together with the plurality of first substrates <NUM>. Specifically, the planarization layer <NUM> may be disposed to cover an upper surface and a side surface of the passivation layer <NUM>, a side surface of the first interlayer insulating layer <NUM>, a side surface of the second interlayer insulating layer <NUM>, a side surface of the gate insulating layer <NUM>, a side surface of the buffer layer <NUM> and a part of upper surfaces of the plurality of first substrates <NUM>. Thus, the planarization layer <NUM> may compensate for steps between the side surfaces of the buffer layer <NUM>, the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM> and the passivation layer <NUM>. Also, the planarization layer <NUM> may enhance adhesion strength between the planarization layer <NUM> and the connection lines <NUM> disposed on a side surface of the planarization layer <NUM>.

Referring to <FIG>, an incline angle of the side surface of the planarization layer <NUM> may be smaller than those of the side surfaces of the buffer layer <NUM>, the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, the second interlayer insulating layer <NUM> and the passivation layer <NUM>. For example, the side surface of the planarization layer <NUM> may have a smaller incline than the side surface of the passivation layer <NUM>, the side surface of the first interlayer insulating layer <NUM>, the side surface of the second interlayer insulating layer <NUM>, the side surface of the gate insulating layer <NUM> and the side surface of the buffer layer <NUM>. Thus, the connection lines <NUM> in contact with the side surface of the planarization layer <NUM> are disposed to have a small incline. Therefore, when the display device <NUM> is stretched, a stress generated in the connection lines <NUM> can be reduced. Also, it is possible to suppress cracks in the connection lines <NUM> or peeling of the connection lines <NUM> from the side surface of the planarization layer <NUM>.

Referring to <FIG> and <FIG>, the connection lines <NUM> refer to lines that electrically connect the pads disposed on the plurality of first substrates <NUM>. The connection lines <NUM> are disposed on the plurality of second substrates <NUM>. Also, the connection lines <NUM> may also be connected on the plurality of first substrates <NUM> to be electrically connected to the pads disposed on the plurality of first substrates <NUM>. The pads disposed on the first substrates <NUM> refer to the gate and data pads.

The connection lines <NUM> include the first connection lines <NUM> and the second connection lines <NUM>. The first connection lines <NUM> and the second connection lines <NUM> are disposed between the plurality of first substrates <NUM>. Specifically, the first connection lines <NUM> refer to lines extended in the X-axis direction between the plurality of first substrates <NUM> among the connection lines <NUM>. The second connection lines <NUM> refer to lines extended in the Y-axis direction between the plurality of first substrates <NUM> among the connection lines <NUM>.

The connection lines <NUM> may be made of a metal material such as copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo). Otherwise, the connection lines <NUM> may have a laminated structure of metal materials such as copper/molybdenum-titanium (Cu/MoTi), titanium/aluminum/titanium (Ti/Al/Ti) or the like, but are not limited thereto.

In a general display device, various lines such as a plurality of gate lines and a plurality of data lines are extended in straight lines and are disposed between a plurality of sub-pixels. Also, the plurality of sub-pixels is connected to a single signal line. Therefore, in the general display device, various lines such as a gate line, a data line, a high-potential power line and a reference voltage line are continuously extended on a substrate from one side to the other side of an organic light emitting display device.

Unlike this, in the display device <NUM> according to an exemplary embodiment of the present disclosure, various lines such, as a gate line, a data line, a high-potential power line and a reference voltage line which are formed in straight lines and considered to be used in the general organic light emitting display device, are disposed only on the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM>. That is, in the display device <NUM> according to an exemplary embodiment of the present disclosure, lines formed in straight lines are disposed only on the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM>.

In the display device <NUM> according to an exemplary embodiment of the present disclosure, the pads on two adjacent first substrates <NUM> or two adjacent third substrate <NUM> may be connected by the connection lines <NUM> to connect discontinuous lines on the first substrates <NUM> or the third substrates <NUM>. That is, the connection lines <NUM> electrically connect the pads on the two adjacent first substrates <NUM>, the two adjacent third substrate <NUM> and the first substrate <NUM> and the third substrate <NUM> adjacent to each other. Therefore, the display device <NUM> according to an exemplary embodiment of the present disclosure may include the plurality of connection lines <NUM> to electrically connect various lines, such as a gate line, a data line, a high-potential power line and a reference voltage line, between the plurality of first substrates <NUM>, between the plurality of third substrates <NUM>, <NUM> and between the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM>. For example, gate lines may be disposed on the plurality of first substrates <NUM> disposed adjacent to each other in the X-axis direction. Also, the gate pads may be disposed on both ends of the gate lines. In this case, a plurality of gate pads on the plurality of first substrates <NUM> disposed adjacent to each other in the X-axis direction may be connected to each other by the first connection lines <NUM> serving as the gate lines. Therefore, the gate lines disposed on the plurality of first substrates <NUM> and the first connection lines <NUM> disposed on the third substrates <NUM> may serve as a single gate line. Further, lines, such as a light emission signal line, a low-potential power line and a high-potential power line which are extended in the X-axis direction among all of various lines that can be included in the display device <NUM>, may also be electrically connected by the first connection lines <NUM> as described above.

Referring to <FIG> and <FIG>, the first connection lines <NUM> may connect pads on two first substrates <NUM> disposed side by side among the pads on the plurality of first substrates <NUM> disposed adjacent to each other in the X-axis direction. Each first connection line <NUM> may serve as a gate line, a light emission signal line, a high-potential power line, or a low-potential power line, but is not limited thereto. For example, the first connection lines <NUM> may serve as gate lines and electrically connect the gate pads on the two first substrates <NUM> disposed side by side in the X-axis direction. Therefore, as described above, the gate pads on the plurality of first substrates <NUM> disposed in the X-axis direction may be connected by the first connection lines <NUM> serving as the gate lines. A single gate voltage may be transferred to the gate pads.

The second connection lines <NUM> may connect the pads on two first substrates <NUM> disposed side by side among the pads on the plurality of first substrates <NUM> disposed adjacent to each other in the Y-axis direction. Each second connection line <NUM> may serve as a data line, a high-potential power line, a low-potential power line or a reference voltage line, but is not limited thereto. For example, the second connection lines <NUM> may serve as data lines and electrically connect data lines on two first substrates <NUM> disposed side by side in the Y-axis direction. Therefore, as described above, internal lines on the plurality of first substrates <NUM> disposed in the Y-axis direction may be connected by a plurality of second connection lines <NUM> serving as the data lines. A single data voltage may be transferred to the data lines.

Referring to <FIG>, the connection lines <NUM> may further include third connection lines that connect the pads on the plurality of first substrates <NUM> and the plurality of third substrates <NUM>, <NUM> or connect pads on two third substrates <NUM> disposed side by side among the pads on the plurality of third substrates <NUM>, <NUM> disposed adjacent to each other in the Y-axis direction.

As shown in <FIG>, each first connection line <NUM> may be in contact with an upper surface and the side surface of the planarization layer <NUM> disposed on the first substrate <NUM> and may be extended to an upper surface of the second substrate <NUM>. Also, each second connection line <NUM> may be in contact with the upper surface and the side surface of the planarization layer <NUM> disposed on the first substrate <NUM> and may be extended to the upper surface of the second substrate <NUM>.

Referring to <FIG>, a bank <NUM> is formed on a connection pad PD, the connection lines <NUM> and the planarization layer <NUM>. The bank <NUM> is a component to distinguish or separate adjacent sub-pixels SPX. The bank <NUM> is disposed to cover at least a part of the connection pad PD, the connection lines <NUM> and the planarization layer <NUM>. The bank <NUM> may be made of an insulating material. Further, the bank <NUM> may contain a black material. Since the bank <NUM> contains a black material, the bank <NUM> serves to hide lines which are visible through the active area AA. The bank <NUM> may be made of, for example, a transparent carbon-based mixture. Specifically, the bank <NUM> may contain carbon black, but is not limited thereto. The bank <NUM> may also be made of a transparent insulating material. Further, although <FIG> illustrates that the bank <NUM> has the same height as the LED <NUM>, the present disclosure is not limited thereto. The bank <NUM> may have a lower height than the LED <NUM>.

Referring to <FIG>, the LED <NUM> is disposed on the connection pad PD and the first connection lines <NUM>. The LED <NUM> includes an n-type layer <NUM>, an active layer <NUM>, a p-type layer <NUM>, an n-electrode <NUM> and a p-electrode <NUM>. The LED <NUM> of the display device <NUM> according to an exemplary embodiment of the present disclosure has a flip-chip structure in which the n-electrode <NUM> and the p-electrode <NUM> are formed on one surface thereof.

The n-type layer <NUM> may be formed by injecting n-type impurities into gallium nitride (GaN) having excellent crystallinity. The n-type layer <NUM> may be disposed on a separate base substrate which is made of a light emitting material.

The active layer <NUM> is disposed on the n-type layer <NUM>. The active layer <NUM> is a light emitting layer that emits light in the LED <NUM> and may be made of a nitride semiconductor, for example, indium gallium nitride (InGaN). The p-type layer <NUM> is disposed on the active layer <NUM>. The p-type layer <NUM> may be formed by injecting p-type impurities into gallium nitride (GaN).

As described above, the LED <NUM> according to an exemplary embodiment of the present disclosure is manufactured by sequentially laminating the n-type layer <NUM>, the active layer <NUM>, and the p-type layer <NUM>, and then, etching a predetermined area of the layers to thereby form the n-electrode <NUM> and the p-electrode <NUM>. In this case, the predetermined area is a space to separate the n-electrode <NUM> and the p-electrode <NUM> from each other and is etched to expose a part of the n-type layer <NUM>. In other words, a surface of the LED <NUM> on which the n-electrode <NUM> and the p-electrode <NUM> are to be disposed may not be flat and may have different levels of height.

The n-electrode <NUM> is disposed on the etched area, and the n-electrode <NUM> may be made of a conductive material. Further, the p-electrode <NUM> is disposed on a non-etched area, and the p-electrode <NUM> may also be made of a conductive material. For example, the n-electrode <NUM> is be disposed on the n-type layer <NUM> which is exposed by etching and the p-electrode <NUM> is disposed on the p-type layer <NUM>. The p-electrode <NUM> may be made of the same material as the n-electrode <NUM>.

An adhesive layer AD is disposed on upper surfaces of the connection pad PD and the first connection lines <NUM> and between the connection pad PD and the first connection lines <NUM>. Thus, the LED <NUM> can be bonded onto the connection pad PD and the first connection lines <NUM>. In this case, the n-electrode <NUM> may be disposed on the first connection lines <NUM> and the p-electrode <NUM> may be disposed on the connection pad PD.

The adhesive layer AD may be a conductive adhesive layer formed by dispersing conductive balls in an insulating base member. Thus, when heat or pressure is applied to the adhesive layer AD, the conductive balls are electrically connected to have conductive properties in a portion of the adhesive layer AD to which heat or pressure is applied. An area of the adhesive layer AD to which pressure is not applied may have insulating properties. For example, the n-electrode <NUM> is electrically connected to the first connection lines <NUM> through the adhesive layer AD, and the p-electrode <NUM> is electrically connected to the connection pad PD through the adhesive layer AD. After applying the adhesive layer AD to upper surfaces of the first connection lines <NUM> and the connection pad PD by an inkjet method or the like, the LED <NUM> may be transferred onto the adhesive layer AD. Then, the LED <NUM> may be pressed and heated to thereby electrically connect the connection pad PD to the p-electrode <NUM> and the first connection lines <NUM> to the n-electrode <NUM>. However, other portions of the adhesive layer AD excluding a portion of the adhesive layer AD between the n-electrode <NUM> and first connection lines <NUM> and a portion of the adhesive layer AD between the p-electrode <NUM> and the connection pad PD have insulating properties. Meanwhile, the adhesive layer AD may be separately disposed on each of the connection pad PD and the first connection lines <NUM>.

Further, the connection pad PD is electrically connected to the drain electrode <NUM> of the driving transistor <NUM> and receives a driving voltage for driving the LED <NUM> from the driving transistor <NUM>. Furthermore, a low-potential driving voltage for driving the LED <NUM> is applied to the first connection lines <NUM>. Thus, when the display device <NUM> is turned on, different levels of voltage applied to each of the connection pad PD and the first connection lines <NUM> are transferred to the n-electrode <NUM> and the p-electrode <NUM>. Accordingly, the LED <NUM> emits light.

Referring to <FIG>, the protection layer <NUM> is disposed on the bank <NUM> and the LED <NUM>.

The protection layer <NUM> covers the LED <NUM> and protects the LED <NUM>. Specifically, the protection layer <NUM> includes a plurality of prism patterns and/or a plurality of regular tetrahedral patterns. That is, the protection layer <NUM> includes a plurality of patterns, preferably each having a triangular cross-section. In other words, a plurality of triangular patterns is disposed in a row in a cross-sectional view of the protection layer <NUM>.

Further, the protection layer <NUM> may be formed as an organic insulating layer. More specifically, the protection layer <NUM> may be made of an acrylic organic material, but is not limited thereto. For example, the protection layer <NUM> may be formed as a single inorganic layer or a plurality of inorganic layers of silicon nitride (SiNx), silicon oxide (SiOx) and silicon oxynitride (SiON). Alternatively, the protection layer <NUM> may be formed as a multilayer in which an organic layer and an inorganic layer are laminated.

Thus, an upper surface of the protection layer <NUM> has a smaller contact area than a lower surface of the protection layer <NUM>. Therefore, a contact area between the upper surface of the protection layer <NUM> and the upper substrate <NUM> is smaller than a contact area between the lower surface of the protection layer <NUM> and the LED <NUM> and the bank <NUM>.

Accordingly, when the display device <NUM> is stretched, a stretching stress applied to the upper substrate <NUM> is not all transferred to the protection layer <NUM>. Due to the protection layer <NUM> including a plurality of patterns each having a triangular cross-section, a stretching stress transferred to the protection layer <NUM> can be eliminated. Thus, a stretching stress applied to the LED <NUM> can be reduced.

Accordingly, even when the display device <NUM> according to an exemplary embodiment of the present disclosure is repeatedly stretched, it is possible to suppress damage to the LED <NUM>. Thus, the stretching reliability of the display device <NUM> can be improved.

Thus, by providing a layer between LED <NUM> and the upper substrate <NUM>, which further supports a bending less or no damages are caused during bending of the display device. The layer preventing the damages has different contact areas at its upper and lower side, thereby reducing the risk of cracks during bending.

Also, since the protection layer <NUM> includes the plurality of patterns each having a triangular cross-section, the extraction efficiency of light emitted to above the LED <NUM> can be increased. Thus, the luminance of the display device <NUM> according to an exemplary embodiment of the present disclosure can be improved. Further, a driving current required for the display device <NUM> according to an exemplary embodiment of the present disclosure to implement a uniform luminance can be reduced. Accordingly, it is possible to reduce power consumption of the display device <NUM> according to an exemplary embodiment of the present disclosure.

Further, the upper substrate <NUM> is disposed on the protection layer <NUM>.

The upper substrate <NUM> serves to support and/or cover various components disposed under the upper substrate <NUM>. Specifically, the upper substrate <NUM> may be formed by coating and hardening a material forming the upper substrate <NUM> on the lower substrate <NUM> and the first substrates <NUM>. Thus, the upper substrate <NUM> may be disposed to be in contact with the lower substrate <NUM>, the first substrates <NUM>, the second substrate <NUM> and the connection lines <NUM>.

The upper substrate <NUM> may be made of the same material as the lower substrate <NUM>. For example, the upper substrate <NUM> may be made of silicone rubber such as polydimethylsiloxane (PDMS) and an elastomer such as polyurethane (PU), and polytetrafluoroethylene (PTFE) or the like. Thus, the upper substrate <NUM> may have flexibility. However, the materials of the upper substrate <NUM> are not limited thereto.

Meanwhile, although not shown in <FIG>, a polarizing layer may also be disposed on the upper substrate <NUM>. The polarizing layer polarizes light incident from the outside of the display device <NUM> and reduces reflection of external light. Further, instead of the polarizing layer, other optical films or the like may be disposed on the upper substrate <NUM>.

Also, a filling layer <NUM> may be disposed on a front surface of the lower substrate <NUM> to fill a space between the upper substrate <NUM> and components disposed on the lower substrate <NUM>. The filling layer may be made of a curable adhesive. Specifically, a material of the filling layer may be coated on the front surface of the lower substrate <NUM> and then cured to form the filling layer. Thus, a filling layer <NUM> may be disposed between the upper substrate <NUM> and the components disposed on the lower substrate <NUM>.

<FIG> is a circuit diagram of a sub-pixel of the display device according to an exemplary embodiment of the present disclosure.

Hereinafter, for the convenience of description, a structure and an operation when a sub-pixel SPX of the display device according to an exemplary embodiment of the present disclosure is a pixel circuit of 2T (transistor) 1C (capacitor) will be described. However, the present disclosure is not limited thereto.

Referring to <FIG> and <FIG>, in the display device according to an exemplary embodiment of the present disclosure, each sub-pixel SPX may include a switching transistor <NUM>, a driving transistor <NUM>, a storage capacitor C and an LED <NUM>.

The switching transistor <NUM> applies a data signal DATA supplied through the second connection lines <NUM> to the driving transistor <NUM> and the storage capacitor C in response to a gate signal SCAN supplied through the first connection lines <NUM>.

The gate electrode <NUM> of the switching transistor <NUM> is electrically connected to the first connection lines <NUM>. Also, the source electrode <NUM> of the switching transistor <NUM> is connected to the second connection lines <NUM>. Further, the drain electrode <NUM> of the switching transistor <NUM> is connected to the gate electrode <NUM> of the driving transistor <NUM>.

The driving transistor <NUM> may operate to enable a driving current according to a high-potential power VDD supplied through the first connection lines <NUM> and the data voltage DATA supplied through the second connection lines <NUM> to flow in response to the data voltage DATA stored in the storage capacitor C.

Further, the gate electrode <NUM> of the driving transistor <NUM> is electrically connected to the drain electrode <NUM> of the switching transistor <NUM>. Furthermore, the source electrode of the driving transistor <NUM> is connected to the first connection lines <NUM>. Moreover, the drain electrode <NUM> of the driving transistor <NUM> is connected to the LED <NUM>.

The LED <NUM> may operate to emit light according to a driving current formed by the driving transistor <NUM>. Also, as described above, the n-electrode <NUM> of the LED <NUM> may be connected to the first connection lines <NUM> and thus may be applied with a low-potential power VSS. Further, the p-electrode <NUM> of the LED <NUM> may be connected to the drain electrode <NUM> of the driving transistor <NUM> and thus may be applied with a driving voltage corresponding to the driving current.

Each sub-pixel SPX of the display device according to an exemplary embodiment of the present disclosure is configured to have a 2T1C structure including the switching transistor <NUM>, the driving transistor <NUM>, the storage capacitor C and the LED <NUM> as an example. However, when a compensation circuit is added, each sub-pixel SPX may be configured in various ways, such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C or 7T2C.

As described above, the display device according to an exemplary embodiment of the present disclosure may include a plurality of sub-pixels on a first substrate which is a rigid substrate. Each of the plurality of sub-pixels SPX may include a switching transistor, a driving transistor, a storage capacitor and an LED.

Therefore, the display device according to an exemplary embodiment of the present disclosure can be stretched due to a lower substrate. Also, each first substrate includes a pixel circuit having a 2T1C structure. Thus, it is possible to emit light depending on a data voltage at each gate timing.

Hereinafter, a display device <NUM> according to another exemplary embodiment of the present disclosure will be described in detail. The display device <NUM> according to another exemplary embodiment of the present disclosure is different from the display device <NUM> according to an exemplary embodiment of the present disclosure only in terms of the placement of a protection layer. Accordingly, a detailed description of the same parts as those of the display device <NUM> according to an exemplary embodiment of the present disclosure will be omitted, and the above-described difference will be described in detail.

<FIG> is an enlarged plan view of an active area of a display device according to another exemplary embodiment of the present disclosure. <FIG> is a schematic cross-sectional view as taken along a line VI-VI' of <FIG>.

As shown in <FIG>, in the display device <NUM> according to another exemplary embodiment of the present disclosure, a protection layer <NUM> is disposed on a pixel including a plurality of sub-pixels SPX to cover the pixel including the plurality of sub-pixels SPX. Specifically, the protection layer <NUM> may overlap the plurality of sub-pixels SPX, but may not overlap the plurality of connection lines <NUM> extended on the first substrate <NUM>. Thus, the protection layer <NUM> may have a shape including tips each disposed between the plurality of connection lines <NUM>.

The protection layer <NUM> covers the LED <NUM> and protects the LED <NUM>. Specifically, an upper surface of the protection layer <NUM> may be in contact with the upper substrate <NUM>, and a lower surface of the protection layer <NUM> may be in contact with the bank <NUM> and the LED <NUM>. That is, the protection layer <NUM> may fill a space between the upper substrate <NUM> and the bank <NUM> and the LED <NUM>.

That is, in the display device <NUM> according to another exemplary embodiment of the present disclosure, the tips, which are parts of the protection layer <NUM>, may be disposed between the plurality of connection lines <NUM>. Thus, when the LED <NUM> is transferred in the display device <NUM> according to another exemplary embodiment of the present disclosure, the LED <NUM> may be aligned based on the tips of the protection layer <NUM>. Therefore, it is possible to more precisely transfer the LED <NUM> in the display device <NUM> according to another exemplary embodiment of the present disclosure. Thus, the yield of the transfer process can be improved.

Hereinafter, a display device <NUM> according to yet another exemplary embodiment of the present disclosure will be described in detail. The display device <NUM> according to yet another exemplary embodiment of the present disclosure is different from the display device <NUM> according to an exemplary embodiment of the present disclosure only in terms of the placement of a protection layer. Accordingly, a detailed description of the same parts as those of the display device <NUM> according to an exemplary embodiment of the present disclosure will be omitted, and the above-described difference will be described in detail.

<FIG> is an enlarged plan view of an active area of a display device according to yet another exemplary embodiment of the present disclosure. <FIG> is a schematic cross-sectional view as taken along a line VIII-VIII' of <FIG>.

As shown in <FIG>, in the display device <NUM> according to yet another exemplary embodiment of the present disclosure, a protection layer <NUM> is disposed on a pixel including a plurality of sub-pixels SPX to cover the pixel including the plurality of sub-pixels SPX. Specifically, the protection layer <NUM> may overlap the plurality of sub-pixels SPX, but may not overlap the plurality of connection lines <NUM> extended on the first substrate <NUM>. Thus, the protection layer <NUM> may have a shape including tips each disposed between the plurality of connection lines <NUM>.

Also, a plurality of protrusions <NUM> may be disposed on the sides of the plurality of sub-pixels SPX. As shown in <FIG>, the plurality of protrusions <NUM> may be disposed on all the four sides of the plurality of sub-pixels SPX, but is not limited thereto. The plurality of protrusions <NUM> may be disposed on at least two of the four sides of the plurality of sub-pixels SPX. For example, the plurality of protrusions <NUM> may be disposed on the upper and lower sides along the Y-axis of the plurality of sub-pixels SPX. Alternatively, the plurality of protrusions <NUM> may be disposed on the left and right sides along the X-axis of the plurality of sub-pixels SPX.

The protection layer <NUM> covers the LED <NUM> and protects the LED <NUM>. Specifically, an upper surface of the protection layer <NUM> may be in contact with the upper substrate <NUM>, and a lower surface of the protection layer <NUM> may be in contact with the bank <NUM> and the LED <NUM>. That is, the protection layer <NUM> may fill a space between the upper substrate and the bank <NUM> and the LED <NUM>.

Further, the plurality of protrusions <NUM> may be an embossed pattern protruding downwards from the protection layer <NUM>. Thus, the plurality of protrusions <NUM> may be in contact with a side surface of the LED <NUM> disposed under the protection layer <NUM>. Also, the plurality of protrusions <NUM> may be in contact with a side surface of the bank <NUM> disposed under the protection layer <NUM>.

More specifically, referring to <FIG>, the plurality of protrusions <NUM> may be disposed between the LED <NUM> and the bank <NUM> disposed under the protection layer <NUM> and may be in contact with the LED <NUM> and the bank <NUM>.

However, the present disclosure is not limited thereto. The plurality of protrusions <NUM> may be in contact with only a side surface of the LED <NUM> disposed under the protection layer <NUM>, but may not be in contact with a side surface of the bank <NUM>.

Further, the protection layer <NUM> and all of the plurality of protrusions <NUM> may be formed as an organic insulating layer. More specifically, the protection layer <NUM> and all of the plurality of protrusions <NUM> may be made of an acrylic organic material, but is not limited thereto. For example, the protection layer <NUM> may be formed as a single inorganic layer or a plurality of inorganic layers of silicon nitride (SiNx), silicon oxide (SiOx) and silicon oxynitride (SiON). Alternatively, the protection layer <NUM> may be formed as a multilayer in which an organic layer and an inorganic layer are laminated.

That is, in the display device <NUM> according to yet another exemplary embodiment of the present disclosure, the tips, which are parts of the protection layer <NUM>, may be disposed between the plurality of connection lines <NUM>. Thus, when the LED <NUM> is transferred in the display device <NUM> according to yet another exemplary embodiment of the present disclosure, the LED <NUM> may be aligned based on the tips of the protection layer <NUM>. Therefore, it is possible to more precisely transfer the LED <NUM> in the display device <NUM> according to yet another exemplary embodiment of the present disclosure. Thus, the yield of the transfer process can be improved.

Further, in the display device <NUM> according to yet another exemplary embodiment of the present disclosure, the plurality of protrusions <NUM> protruding downwards from the protection layer <NUM> may be disposed on both sides of the LED <NUM>. Thus, due to the plurality of protrusions <NUM>, the LED may not be misaligned and can be disposed in an accurate area. Furthermore, even when the LED is bonded to the connection pad PD, the LED can be aligned based on the plurality of protrusions <NUM>. Therefore, in the display device <NUM> according to yet another exemplary embodiment of the present disclosure, the yield of a process of bonding the LED <NUM> can be improved.

Hereinafter, a display device <NUM> according to still another exemplary embodiment of the present disclosure will be described in detail. The display device <NUM> according to still another exemplary embodiment of the present disclosure is different from the display device <NUM> according to an exemplary embodiment of the present disclosure only in terms of the placement of the protection layer <NUM>. Accordingly, a detailed description of the same parts as those of the display device <NUM> according to an exemplary embodiment of the present disclosure will be omitted, and the above-described difference will be described in detail.

<FIG> is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure.

As shown in <FIG>, in the display device <NUM> according to still another exemplary embodiment of the present disclosure, a bank <NUM> may have a lower height than the LED <NUM>.

Further, a protection layer <NUM> overlaps the plurality of sub-pixels SPX and may also overlap the plurality of connection lines <NUM> extended on the first substrate <NUM>. Furthermore, a shape of the protection layer <NUM> may have a quadrangular pattern which is the same as a shape of the first substrate <NUM>, but is not limited thereto. The protection layer <NUM> may have various shapes on the first substrate <NUM>.

Also, the protection layer <NUM> is disposed on the bank <NUM> and the LED <NUM>.

The protection layer <NUM> covers the LED <NUM> and protects the LED <NUM>. Specifically, an upper surface of the protection layer <NUM> may be in contact with the upper substrate <NUM>, and a lower surface of the protection layer <NUM> may be in contact with the bank <NUM> and the LED <NUM>.

However, the bank <NUM> may have a lower height than the LED <NUM> as described above, and, thus, there is a step difference between an upper surface of the bank <NUM> and an upper surface of the LED <NUM>. Therefore, the protection layer <NUM> is in contact with the upper surface of the bank <NUM> and the upper surface of the LED <NUM> between which there is a step difference. Accordingly, the protection layer <NUM> may have a shape like a blanket covering the entire pixel including a plurality of sub-pixels.

As shown in <FIG>, a separation space which cannot be covered by the protection layer <NUM> may be formed at a side surface of the bank <NUM> and a side surface of the LED <NUM>. However, the present disclosure is not limited thereto. The protection layer <NUM> may be conformally formed along the side surface of the bank <NUM> and the side surface of the LED <NUM>.

That is, in the display device <NUM> according to still another exemplary embodiment of the present disclosure, the protection layer <NUM> may be formed covering the entire surface of a pixel including a plurality of pixels. Thus, even when the display device <NUM> according to still another exemplary embodiment of the present disclosure is stretched, the LED <NUM> can be more firmly fixed by the protection layer <NUM>. Therefore, even though the display device <NUM> according to still another exemplary embodiment of the present disclosure is repeatedly stretched, the LED <NUM> can be stably bonded. Thus, the stretching reliability of the display device <NUM> according to still another exemplary embodiment of the present disclosure can be improved.

Claim 1:
A display device (<NUM>), comprising:
a stretchable lower substrate (<NUM>);
a plurality of first substrates (<NUM>) disposed on the lower substrate (<NUM>);
a plurality of second substrates (<NUM>) between the plurality of adjacent first substrates (<NUM>);
a plurality of pixels (PX) disposed on the plurality of first substrates (<NUM>);
a plurality of connection lines (<NUM>, <NUM>, <NUM>) disposed on the plurality of second substrates (<NUM>) for connecting the plurality of pixels (PX) on adjacent first substrates (<NUM>); and
a protection layer (<NUM>; <NUM>; <NUM>; <NUM>) disposed on each of the plurality of pixels (PX),
characterised in that
the protection layer (<NUM>; <NUM>; <NUM>; <NUM>) includes a plurality of patterns each having a triangular cross-section.