Patent Description:
An attacker can attempt voltage tampering of an integrated circuit by manipulating the supply voltage provided to the integrated circuit to levels that are outside normal operating parameters. The manipulated supply voltage may cause circuitry in the integrated circuit to violate timing requirements, for example, causing a timing failure if the logic slow down caused by a reduced supply voltage is more than the reduction in the frequency of a clock signal. If security functions fail in response to the voltage tampering, security logic may be compromised, potentially allowing content to be stolen from a secure region of the integrated circuit. Examples of circuits and methods to detect changes in a voltage value can be found in the patent documents <CIT> and <CIT>.

Canary circuits and early versions of tunable replica circuits for voltage-delay monitoring typically present extensive calibration requirements prior to use, require a large number of fuses for tuning, and have challenging manual calibration specifications. These types of sensors may require complex critical-path delay-tuning or a manual alignment across PVT (process, voltage and temperature). Therefore, it would be desirable to provide fully-digital, compact, and intelligent sensors with reduced calibration requirements to enable silicon high-volume manufacturing (HVM). In this regard, this object is achieved by the detection circuit defined in the independent claim <NUM> and the method defined in the independent claim <NUM>. Further embodiments are defined in the corresponding dependent claims. The description and drawings also present non-claimed embodiments, examples, aspects, and implementations for the better understanding of the claimed embodiments defined in the appended claims.

According to some embodiments, an in-situ self-aligning, timing margin monitor (TMM) sensor circuit provides hardware-based security and timing margin reduction in an integrated circuit. The TMM sensor circuit can be used as a voltage and/or security detection circuit using auto-alignment functionality. The TMM sensor circuit enables continuous supply voltage droop/overshoot monitoring and provides a digital code of the sampled supply voltage every clock cycle, with the ability to track the supply voltage fluctuations in real-time. The TMM sensor circuit allows for threshold-based voltage attack detection, logging and recovery, and provides substantial benefits over existing on-die voltage sensing circuits. The TMM sensor circuit may, for example, be implemented with a small number of logic gate circuits (e.g., less than <NUM> logic gates), which reduces sensing area overhead. The TMM sensor circuit can be used for distributed sensing for many types of integrated circuits. The TMM sensor circuit can be implemented in both programmable logic and/or non-programmable logic circuitry.

According to some embodiments disclosed herein, a voltage attack in an integrated circuit die can be detected using a timing margin monitor (TMM) circuit that includes a tunable delay circuit, a time-to-digital converter circuit, and a control circuit that operates from the same supply voltage as the logic circuitry being monitored and protected. The tunable delay circuit delays a delayed signal relative to a divided clock signal. The tunable delay circuit receives the supply voltage. The control circuit causes adjustments to a delay provided by the tunable delay circuit to the delayed signal in response to an enable signal. The time-to-digital converter circuit generates a digital code based on the delayed signal that is proportional to the supply voltage in each clock cycle. In an aligned state, the control circuit compares the digital code to upper and lower threshold voltages in each clock cycle, and the results of the comparisons are used to generate droop and overshoot alarm signals. The control circuit asserts the droop alarm signal or the overshoot alarm signal when the supply voltage is outside a range defined by the upper and lower threshold voltages.

<FIG> illustrates an example of a timing margin monitor (TMM) circuit <NUM>, according to an embodiment. TMM circuit <NUM> may also be referred to herein as a voltage detection circuit. As shown in Figure (<FIG>, TMM circuit <NUM> includes finite state machine (FSM) controller circuit <NUM>, delay configuration circuit <NUM>, tunable delay circuit <NUM>, time-to-digital converter (TDC) circuit <NUM>, <NUM>'s counter circuit <NUM>, flip-flop circuit <NUM>, and inverter circuit <NUM>. TMM circuit <NUM> may be formed in any type of integrated circuit (IC) die, such as a programmable logic IC (e.g., a field programmable gate array (FPGA)), a microprocessor IC, a graphics processing unit IC, a memory IC, or an application specific IC (ASIC). TMM circuit <NUM> can, for example, be synthesized as a system-in-package (SIP) using intrinsic FPGA primitives (e.g., programmable logic circuits) allowing for dynamic creation of on-die distributed sensing networks. The TMM circuit <NUM> can, for example, include hard intellectual property (IP) blocks, soft IP blocks, or a combination thereof, in an FPGA.

FSM controller circuit <NUM> and delay configuration circuit <NUM> function as a delay control circuit that controls the adjustable delay of tunable delay circuit <NUM>, as described in detail below. As shown in <FIG>, a reset signal RESET, a calibration enable signal CALEN, threshold control signals THRS, and signals ALNVAL are provided to inputs of finite state machine (FSM) controller circuit <NUM>. Signals BINCD generated by <NUM>'s counter circuit <NUM> are provided to additional inputs of FSM controller circuit <NUM>.

FSM controller circuit <NUM> generates output signals STATE that indicate the current state of a finite state machine (FSM) in the FSM controller circuit <NUM>. FSM controller circuit <NUM> adjusts the current state of the FSM based on the input signals provided to FSM controller circuit <NUM>, as described in further detail below with respect to <FIG>. The STATE signals are provided to inputs of delay configuration circuit <NUM>. Delay configuration circuit <NUM> generates delay code tuning signals DCT based on the state of the FSM as indicated by the STATE signals. The delay code tuning signals DCT may include one or more signals (bits). Delay configuration circuit <NUM> may include an encoder that generates encoded delay code tuning signals DCT based on the state indicated by the STATE signals. The encoder may, as specific examples that are not intended to be limiting, encode the delay code tuning signals DCT as a binary code, a thermometer code, a Gray code, or a one-hot code.

The flip-flop (FF) circuit <NUM> and the inverter <NUM> are coupled together in a loop to form a clock divide-by-two frequency divider circuit. The output (Q) of FF circuit <NUM> couples to an input of inverter circuit <NUM>, while an output of inverter circuit <NUM> couples to an input (D) of FF circuit <NUM>. FF circuit <NUM> receives a supply voltage VCC. A periodic clock signal CLK is provided to a clock input of flip-flop (FF) circuit <NUM>. Inverter circuit <NUM> inverts a divided clock signal DVCLK received at its input to generate an inverted divided clock signal DVCLKB at its output. The inverted divided clock signal DVCLKB is provided to the D input of FF circuit <NUM>. FF circuit <NUM> generates the divided clock signal DVCLK at its Q output by capturing the value of inverted divided clock signal DVCLKB in response to clock signal CLK. The divided clock signal DVCLK has half the frequency of clock signal CLK.

The delay code tuning signals DCT are provided to control inputs of tunable delay circuit <NUM>. The divided clock signal DVCLK is provided to another input of tunable delay circuit <NUM>. Tunable delay circuit <NUM> is an adjustable delay circuit. Tunable delay circuit <NUM> generates a delayed periodic (clock) digital output signal DLY by delaying the rising and falling edges in the divided clock signal DVCLK. The delay that the tunable delay circuit <NUM> provides to the delayed output signal DLY relative to divided clock signal DVCLK is set based on the value of the delay code tuning signals DCT. Tunable delay circuit <NUM> adjusts the delay provided to delayed signal DLY relative to divided clock signal DVCLK based on changes in the value of the delay code tuning signals DCT. Tunable delay circuit <NUM> may, for example, include a delay chain of adjustable delay cells that are powered by the supply voltage VCC.

Tunable delay circuit <NUM> may, for example, be a replica circuit that replicates the delay in some other part of the same integrated circuit (IC). The tunable delay circuit <NUM> may, for example, replicate the delay in a data path in the IC and be in physical proximity to the data path. According to a more specific example, the data path that is replicated by delay circuit <NUM> may be the critical timing path in logic circuitry that is being monitored by TMM circuit <NUM>. The logic circuitry, including the data path, receives the same supply voltage VCC as TMM circuit <NUM>. The tunable delay circuit <NUM> may, for example, replicate the delay in the data path by containing the same types of logic gates coupled in the same order as the data path, or by using different types of logic gates that are selected to replicate the delay of the data path.

As shown in <FIG>, the delayed signal DLY generated by tunable delay circuit <NUM> is provided to an input of time-to-digital converter (TDC) circuit <NUM>. The divided clock signal DVCLK generated by FF circuit <NUM> and the clock signal CLK are provided to additional inputs of TDC circuit <NUM>. TDC circuit <NUM> converts the delay that is provided by tunable delay circuit <NUM> to delayed signal DLY relative to divided clock signal DVCLK to a multi-bit digital thermometer output code C[<NUM>:<NUM>]. TDC circuit <NUM> changes the value of output code C[<NUM>:<NUM>] in response to each change that tunable delay circuit <NUM> makes to the delay of delayed signal DLY relative to divided clock signal DVCLK based on a change in signals DCT. TDC circuit <NUM> is also coupled to receive supply voltage VCC to monitor any anomalies in supply voltage VCC. Such anomalies may include droop in supply voltage VCC that is caused by a voltage attack. TDC circuit <NUM> changes the value of the digital thermometer code C[<NUM>:<NUM>] in proportion to changes in supply voltage VCC. For example, the value of code C[<NUM>:<NUM>] may decrease in each clock cycle of CLK in response to droop in supply voltage VCC.

<FIG> illustrates details of an example of the time-to-digital converter (TDC) circuit <NUM> of <FIG>, according to an embodiment. In the embodiment of <FIG>, TDC circuit <NUM> includes <NUM> inverter circuits <NUM>, <NUM> flip-flop circuits <NUM>, <NUM> inverter circuits <NUM>, <NUM> multiplexer circuits <NUM>, and <NUM> logic AND gate circuits <NUM>. In <FIG>, inverter circuits 201A-201D, flip-flop circuits 202A-202D, inverter circuits 203A-203D, multiplexer circuits 204A-204D, and logic AND gate circuits 205A-205D are shown as examples. However, TDC circuit <NUM> may have any number (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.) of inverter circuits <NUM>, flip-flop circuits <NUM>, inverter circuits <NUM>, multiplexer circuits <NUM>, and logic AND gate circuits <NUM>. In general, the number of flip-flop circuits <NUM>, inverters <NUM>, and multiplexers <NUM> is equal (or substantially equal) to the number of inverters <NUM>.

The TDC circuit <NUM> includes a delay chain formed by the inverter circuits <NUM> that function as delay cells coupled in series. The input signal to the first inverter circuit 201A in the delay chain is the delayed signal DLY. Each of the inverter circuits <NUM> is coupled to receive supply voltage VCC. As such, the propagation delay of each inverter circuit <NUM> directly relates to the supply voltage VCC. As the supply voltage VCC decreases, the propagation delay of inverter circuits <NUM> increases. As the supply voltage VCC increases, the propagation delay of inverter circuits <NUM> decreases. The delay cells <NUM> can be any suitable digital or process-scalable delay cells. While an inverter is a simple form of an inversion delay cell, other circuits such as NAND gates, NOR gates, inverting multiplexers etc. can be configured and used as inversion delay cells. These inversion delay cells can be standard cells from a standard-cell library.

In various embodiments, flip-flop (FF) circuits <NUM> function as sequential circuits. Any suitable flip-flop design can be used for implementing FF circuits <NUM>. The input D of each flip-flop circuit <NUM> couples to an output of one of inverter circuits <NUM>. Each flip-flop circuit <NUM> receives the clock signal CLK at its clock input as a sampling clock signal. CLK has twice the frequency of the frequency divided clock signal DVCLK. One input of each multiplexer circuit <NUM> is coupled to receive an output signal q at a Q output of one of the FF circuits <NUM>, as shown in <FIG>. The <NUM> FF circuits <NUM> of <FIG> generate <NUM> output signals q[<NUM>], q[<NUM>],. q[<NUM>], and q[<NUM>]. Flip-flop circuits <NUM> sample the output signals of respective ones of the inverters <NUM> at their D inputs on every rising (or every falling) edge of clock signal CLK. For an odd cycle, the high-phase of the divided clock signal DVCLK passes through the delay chain <NUM>, and for an even cycle, the low-phase of the divided clock signal DVCLK passes through the delay chain <NUM>. To generate consistent output codes every cycle of clock signal CLK, regardless of the phase of clock signal DVCLK passed to the delay chain <NUM>, TDC circuit <NUM> uses polarity inversion of an output code C every other clock cycle. In some embodiments, multiplexer circuits <NUM> controlled by divided clock signal DVCLK at their select inputs implement polarity inversion of the code C every other clock cycle.

Inverter circuits <NUM> may be simple inverters or any other digital inversion logic such as NAND gates, NOR gates, etc. configured as inverters. Each of the multiplexer circuits <NUM> is controllable by clock signal DVCLK at its select input. For example, when DVCLK is high, the signal at the multiplexer <NUM> data input '<NUM>' is provided as output Cm, and when DVCLK is low, the signal at the multiplexer <NUM> input '<NUM>' is provided as output Cm. Each of the multiplexer circuits <NUM> receives alternating signals at its '<NUM>' and <NUM>' inputs from the respective inverter <NUM> and from the respective flip-flop <NUM>. For example, the first multiplexer 204A receives signal Cf[<NUM>] (which is an inversion of signal q[<NUM>]) from inverter 203A at its input '<NUM>' and signal q[<NUM>] (which is logically equivalent to the inversion of Cf[<NUM>]) at its input '<NUM>'. The second multiplexer circuit 204B receives signal Cf[<NUM>] (which is equivalent to signal q[<NUM>]) at its input '<NUM>' and an inversion of signal q[<NUM>] (which is logically equivalent to the inversion of signal Cf[<NUM>]) at its input '<NUM>'. Clock signal DVCLK causes multiplexers <NUM> to select signals Cf[<NUM>:<NUM>] as output signals Cm[<NUM>:<NUM>] when DVCLK is <NUM>, and the inversions of signals Cf[<NUM>:<NUM>] as output signals Cm[<NUM>:<NUM>] when DVCLK is <NUM>. The multiplexers <NUM> and the inverters <NUM> cause the output code Cm[<NUM>:<NUM>] to be a thermometer code.

AND logic gate circuits <NUM> function as bubble suppression circuitry in TDC circuit <NUM>. The inputs of each AND logic gate circuit <NUM> receive the output signal Cm of one or two of the multiplexers <NUM>, as shown in <FIG>. The first AND logic gate circuit 205A receives a hard-wired logic '<NUM>' value at its first input and signal Cm[<NUM>] at its second input. The second AND logic gate circuit 205B receives signal Cm[<NUM>] at its first input and signal Cm[<NUM>] at its second input, and so on. As such, any flip-flop metastability-induced bubble in the code Cm[<NUM>] through Cm[<NUM>], is suppressed by bubble suppression logic gates <NUM>. While AND logic gates <NUM> are shown in <FIG>, the AND logic gate circuits <NUM> can be implemented as NAND logic gates. In the example of <FIG>, TDC circuit <NUM> has <NUM> AND logic gate circuits <NUM>, which is the same number of the delay cells <NUM>. The AND logic gate circuits <NUM> generate an output thermometer code C[<NUM>:<NUM>] that is transmitted on parallel signal lines (i.e., a <NUM>-bit code).

TDC circuit <NUM> has a fast response time of one clock cycle latency by passing a pulse of DVCLK every clock cycle and inverting the polarity of the intermediate code (e.g., Cf[<NUM>:<NUM>]) every other clock cycle using multiplexers <NUM> and inverters <NUM>. TDC circuit <NUM> is accurate by sampling the supply voltage VCC for a full clock cycle, providing improved droop detection resolution. TDC circuit <NUM> generates code C[<NUM>:<NUM>] with a <NUM> clock cycle latency (rather than <NUM> clock cycles), effectively doubling the throughput of the sensor compared to traditional TDCs that require an implicit reset cycle between consecutive samples.

Referring again to <FIG>, the output thermometer code C[<NUM>:<NUM>] generated by TDC circuit <NUM> is transmitted to inputs of <NUM>'s counter circuit <NUM>. <NUM>'s counter circuit <NUM> may be, for example, an adder circuit. <NUM>'s counter circuit <NUM> converts the thermometer code C[<NUM>:<NUM>] to a binary code BINCD at its outputs. <NUM>'s counter circuit <NUM> causes the binary value of binary code BINCD to equal the number of <NUM> in thermometer code C[<NUM>:<NUM>]. The binary code BINCD is provided to inputs of FSM controller circuit <NUM> and to outputs of TMM circuit <NUM>.

Further details of an example of the operation of the TMM circuit <NUM> are now discussed in the context of <FIG>, <FIG>, and <FIG>. Timing margin monitor (TMM) circuit <NUM> detects a change in the supply voltage VCC above an upper threshold voltage or below a lower threshold voltage. The upper and lower threshold voltages are defined by the threshold control signals THRS. <FIG> is a flow chart that illustrates examples of operations that the TMM circuit <NUM> may perform to monitor the supply voltage VCC, according to an embodiment. <FIG> is a state diagram that illustrates the states of a finite state machine (FSM) in the FSM controller circuit <NUM> and the progression between the states, according to an embodiment.

The supply voltage detection process disclosed herein with respect to <FIG> is ideally performed during quiescent conditions of the IC when the supply voltage VCC is stable (e.g., after reset and before workload execution in the IC). Performing supply voltage detection during quiescent conditions ensures that consistent values are determined for the binary code indicated by signals BINCD.

In an exemplary embodiment of TMM circuit <NUM>, circuits <NUM>-<NUM> initially set tunable delay circuit <NUM> to its minimum delay value and then increase the delay of tunable delay circuit <NUM>. The minimum delay value of tunable delay circuit <NUM> is the minimum delay that circuit <NUM> can provide to delayed signal DLY relative to divided clock signal DVCLK.

Referring to <FIG> and <FIG>, the RESET signal is initially asserted, and the CALEN signal is initially de-asserted, causing the FSM controller circuit <NUM> to be in an unaligned state (<NUM>) <NUM> (shown in <FIG>) and in reset. In operation <NUM> shown in <FIG>, the RESET signal is de-asserted (e.g., transitions to a logic low state). In response to the RESET signal being de-asserted, FSM controller circuit <NUM> is no longer in reset. In operation <NUM> shown in <FIG>, FSM controller circuit <NUM> and delay configuration circuit <NUM> set the tunable delay circuit <NUM> to its minimum delay value. TDC circuit <NUM> may, for example, generate all <NUM> in thermometer code C[<NUM>:<NUM>] in response to the minimum delay value of tunable delay circuit <NUM>. Also, FSM controller circuit <NUM> receives the threshold control signals THRS that indicate the values of the upper and lower threshold voltages, and FSM controller circuit <NUM> receives ALNVAL signals. Signals ALNVAL indicate an alignment value for the binary code indicated by signals BINCD. The ALNVAL signals may, for example, be provided as an N-bit binary code. The alignment value indicated by signals ALNVAL may equal any of the possible values of the BINCD signals. The threshold control signals THRS may, for example, be generated based on user input or retrieved from storage.

In operation <NUM> shown in <FIG>, the CALEN signal is asserted (e.g., transitions to a logic high state). In response to the CALEN signal being asserted, the FSM controller circuit <NUM> transitions from the unaligned state <NUM> to the delay line enabled state (<NUM>) <NUM>, as shown in <FIG>. In operation <NUM>, the FSM controller circuit <NUM> adjusts the value of the STATE signals to indicate to delay configuration circuit <NUM> that the FSM is in the delay line enabled state <NUM>. In the delay line enabled state <NUM>, FSM controller circuit <NUM> and delay configuration circuit <NUM> perform a self-alignment loop to calibrate the delay of tunable delay circuit <NUM>, as shown in <FIG>.

In decision operation <NUM> shown in <FIG>, FSM controller circuit <NUM> determines if the binary code indicated by signals BINCD equals the alignment value indicated by signals ALNVAL. As an example, FSM controller circuit <NUM> may include a comparator circuit that compares the binary code indicated by signals BINCD to the alignment value indicated by signals ALNVAL to determine if these two values are equal in operation <NUM>. If FSM controller circuit <NUM> determines that the binary code indicated by signals BINCD does not equal the alignment value indicated by signals ALNVAL in decision operation <NUM>, FSM controller circuit <NUM> and delay configuration circuit <NUM> increase the delay that the tunable delay circuit <NUM> provides to signal DLY relative to divided clock signal DVCLK, in operation <NUM> shown in <FIG>. As an example, the delay configuration circuit <NUM> may adjust the value of the delay code tuning signals DCT in operation <NUM> in response to the STATE signals indicating that the finite state machine (FSM) is in the delay line enabled state <NUM>. In response to the adjustment in the value of the delay code tuning signals DCT provided by delay configuration circuit <NUM> in operation <NUM>, tunable delay circuit <NUM> increases the delay provided to signal DLY relative to clock signal DVCLK. As a more specific example, the delay configuration circuit <NUM> may contain a counter circuit that increases a count value in operation <NUM> in response to the STATE signals indicating that the FSM is in the delay line enabled state <NUM>. In this example, the delay configuration circuit <NUM> may provide the count value in the delay code tuning signals DCT.

During the self-alignment loop of <FIG>, the FSM controller circuit <NUM> continuously, or at intervals, determines if the CALEN signal is still asserted in operation <NUM>. If the CALEN signal is de-asserted, or if the RESET signal is asserted, during the self-alignment loop, the FSM in FSM controller circuit <NUM> returns to the unaligned state <NUM> in operation <NUM>, and the self-alignment loop terminates.

Also, during the self-alignment loop, the FSM controller circuit <NUM> continuously, or at intervals, determines in decision operation <NUM> if the binary code indicated by signals BINCD equals the alignment value indicated by signals ALNVAL. As long as the binary code indicated by signals BINCD does not equal the alignment value indicated by signals ALNVAL, the FSM in FSM controller circuit <NUM> remains in state <NUM>, and the delay configuration circuit <NUM> continues to increase the delay that the tunable delay circuit <NUM> provides to signal DLY relative to divided clock signal DVCLK in additional iterations of operation <NUM>.

In response to each increase that tunable delay circuit <NUM> provides to the delay of signal DLY relative to divided clock signal DVCLK, TDC circuit <NUM> decreases the number of <NUM> in thermometer code C[<NUM>:<NUM>], and <NUM>'s counter circuit <NUM> decreases the binary value of signals BINCD. As the delay provided to signal DLY increases, the period of clock signal CLK remains constant, if there are no changes in the supply voltage VCC and the temperature of the IC. After FSM controller circuit <NUM> has detected that the binary value of signals BINCD equals the alignment value indicated by signals ALNVAL in operation <NUM>, FSM controller circuit <NUM> and delay configuration circuit <NUM> maintain the value of the delay code tuning signals DCT constant. In response to the value of signals DCT being constant, tunable delay circuit <NUM> causes the delay provided to signal DLY to remain constant. In response to the delay provided to signal DLY remaining constant, TDC <NUM> and <NUM>'s counter circuit <NUM> cause the binary value of signals BINCD to remain constant.

In response to FSM controller circuit <NUM> determining that the binary value indicated by signals BINCD equals the alignment value indicated by signals ALNVAL, FSM controller circuit <NUM> transitions from the delay line enabled state <NUM> to the aligned state <NUM>. During the transition to the aligned state <NUM>, FSM controller circuit <NUM> performs <NUM> NO-OPs (no operations) <NUM>-<NUM> as a filter for any combinational glitches from tunable delay circuit <NUM> and to prevent any false positives in the circuitry of <FIG> after the self-alignment loop. After the tunable delay circuit <NUM> has settled after the <NUM> NO-OPs <NUM>-<NUM>, FSM controller circuit <NUM> enters the aligned state <NUM> in operation <NUM> indicating that TMM circuit <NUM> is aligned, and FSM controller circuit <NUM> asserts an ALIGNED output signal indicating the alignment of TMM circuit <NUM>, as shown in <FIG>. In the aligned state <NUM>, FSM controller circuit <NUM> outputs a value in the STATE signals that indicates that TMM circuit <NUM> is ready for use.

TMM circuit <NUM> returns to the unaligned state <NUM> in response to the CALEN signal being de-asserted or the RESET signal being asserted, as shown in <FIG>. If PVT (process, voltage and temperature) conditions change in the IC (e.g. supply voltage VCC changes), the FSM controller circuit <NUM> and TDC circuit <NUM> quickly re-align to a new supply voltage VCC by toggling the CALEN signal, and voltage fluctuations around the new supply voltage VCC are monitored. The minimum and maximum threshold voltages indicated by threshold control signals THRS can be adjusted accordingly.

In the aligned state <NUM>, TMM circuit <NUM> can detect variations in the supply voltage VCC that are outside a voltage range defined by threshold control signals THRS. TMM circuit <NUM> can detect an overshoot in the supply voltage VCC and an undershoot in the supply voltage VCC in the aligned state <NUM>. The threshold control signals THRS provided to FSM controller circuit <NUM> indicate an upper threshold voltage UTH and a lower threshold voltage LTH that define the voltage range. The upper threshold voltage UTH corresponds to a binary value that is greater than the alignment value indicated by signals ALNVAL. The lower threshold voltage LTH corresponds to a binary value that is less than the alignment value ALNVAL. In the aligned state <NUM>, one or more comparator circuits in FSM controller circuit <NUM> compare the binary code indicated by signals BINCD to the binary values of the upper threshold voltage UTH and the lower threshold voltage LTH indicated by control signals THRS. In the aligned state <NUM>, FSM controller circuit <NUM> asserts an OVERSHOOT signal in response to supply voltage VCC (as indicated by signals BINCD) increasing above the upper threshold voltage UTH. In the aligned state <NUM>, FSM controller circuit <NUM> asserts a DROOP signal in response to supply voltage VCC (as indicated by signals BINCD) decreasing below the lower threshold voltage LTH. <FIG> illustrates an example of how the supply voltage VCC can vary relative to the upper threshold voltage UTH and the lower threshold voltage LTH in the aligned state <NUM>, according to an embodiment. In the example of <FIG>, the upper threshold voltage UTH is <NUM> volts, the nominal supply voltage VCC is <NUM> volts, and the lower threshold voltage LTH is <NUM> volts. Time is shown in nanoseconds (ns).

When the supply voltage VCC moves outside the voltage range defined by the upper and lower threshold voltages UTH and LTH, the delay of tunable delay circuit <NUM> has increased or decreased by an amount sufficient to exceed a timing margin. When TMM circuit <NUM> is operating in the aligned state <NUM>, the change in the binary value of signals BINCD that is caused by VCC moving outside the voltage range functions as an alarm that indicates to FSM controller circuit <NUM> (and possibly other circuitry in the IC) that a voltage attack on the supply voltage VCC may have occurred in the IC. In an embodiment, TMM circuit <NUM> may generate the alarm in the OVERSHOOT signal or in the DROOP signal quickly, for example, within <NUM> clock cycle (of CLK) of the timing margin being exceeded. The binary code indicated by signals BINCD indicates the extent of the timing violation (or available slack) for margin recovery.

The digital code indicated by the delay code tuning signals DCT at the alignment value is dependent on the process, the voltage, and the temperature (PVT) of the IC. For this reason, the digital code indicated by the delay code tuning signals DCT at the alignment value is a valuable reference point for security uses, such as power optimization and energy recovery using dynamic voltage-frequency scaling. When a TMM circuit <NUM> is embedded inside an integrated circuit (IC) die, the tunable delay circuit <NUM> tracks the PVT conditions of the IC during operation of the IC. Transient voltage and temperature changes in the IC, if any, may be indicated by changes in the delay of tunable delay circuit <NUM>. Multiple instances of TMM circuit <NUM> can be created to implement a network of compact voltage sensors in an IC to diagnose the conditions of the supply voltage power grid in the IC, to indicate voltage faults in the IC, and to flag voltage attacks on the IC for making the IC more secure. TMM circuit <NUM> can also be used to maximize the supply voltage VCC, for dynamic timing margin and energy reduction, and to improve silicon energy efficiency in a dynamic, workload dependent manner. In some embodiments, the delay code tuning signals DCT can be used to sort integrated circuit dies after fabrication based on their speed using frequency driven silicon binning.

The self-alignment loop in operations <NUM>-<NUM> enables a compact, low-power TMM sensor circuit <NUM> that has a short TDC chain (e.g. <NUM>-bit or <NUM>-bit TDC circuit) and that saves valuable clock power compared to previously known TDC designs. TMM <NUM> eliminates the need to overprovision the TDC with bits that are unneeded for the self-alignment loop. The self-alignment loop allows the TDC <NUM> to monitor transitions around the alignment value that are useful for a variety of purposes, such as supply voltage detection and timing monitoring.

According to some embodiments, processing circuitry can process the data indicated by the binary code BINCD in real-time using pattern recognition with signal template matching to identify patterns in the data that indicate anomalies in the supply voltage on a power grid in the integrated circuit. The processing circuitry can attempt to pattern match the data indicated by code BINCD with known signal templates to determine if the supply voltage contains any anomalies.

According to other embodiments, the time-to-digital converter (TDC) circuit <NUM> partitions the digital code C[<NUM>:<NUM>] into multiple segments (e.g., <NUM> code segments each having <NUM>-bits). The FSM controller circuit <NUM> and the delay configuration circuit <NUM> can align any of the segments of the digital code C[<NUM>:<NUM>] to the alignment value indicated by signals ALNVAL.

In addition to being used for hardware security, the TMM circuit <NUM> can also be used for timing margin detection. After auto-alignment and calibration of TMM circuit <NUM>, fluctuations in the output digital code BINCD are PVT dependent and provide a reference point for security uses, power optimization, timing margin detection, and energy recovery using dynamic voltage-frequency scaling (DVFS) and silicon binning. When a distributed sensing network of TMM circuits <NUM> is embedded inside an integrated circuit (IC), the tunable delay circuit <NUM> tracks PVT conditions in the IC during operation. Transient voltage and temperature changes, if any, are reflected in the output signal DLY of tunable delay circuit <NUM> and in signals BINCD. The resulting magnitude of signals BINCD indicate if there are positive or negative supply voltage or timing margin changes and serves as an indicator of the extent of a timing violation (or available slack) for timing margin recovery related to clock signal DVCLK. After alignment to a clock edge, the code indicated by signals BINCD is indicative of the timing of the leading and trailing edges of the divided clock signal DVCLK and can be used for closed-loop power and timing management (e.g., using an on-board or on-die power management unit) for the detection of supply voltage and timing margin changes.

A detailed example of the tunable delay circuit <NUM> in TMM circuit <NUM> is disclosed herein with respect to <FIG> and <FIG>. The exemplary tunable delay circuit <NUM> shown in <FIG> is provided for illustrative purposes and is not intended to be limiting. Many other types of adjustable delay circuits may be used to implement the tunable delay circuit <NUM> of <FIG>.

<FIG> illustrates an example of the tunable delay circuit <NUM> of <FIG>, according to an embodiment. In the exemplary embodiment of <FIG>, tunable delay circuit <NUM> is an adjustable replica delay chain circuit. The tunable delay circuit <NUM> of <FIG> is a symmetric and linearized delay circuit that includes a bi-directional, folded, telescopic delay chain of adjustable delay cell circuits. In the embodiment of <FIG>, tunable delay circuit <NUM> includes <NUM> delay cell circuits <NUM>-<NUM> coupled in a folded, bidirectional delay chain configuration. Although <NUM> delay cell circuits <NUM>-<NUM> are shown in the example of <FIG>, it should be understood that tunable delay circuit <NUM> of <FIG> can have any number of delay cell circuits needed to match any specific latency requirements.

As another specific example, tunable delay circuit <NUM> may have <NUM> delay cell circuits that are coupled in a bidirectional, folded delay chain, as with the embodiment of <FIG>. In some embodiments, the delay cell circuits <NUM>-<NUM> are fully synthesizable and can be built using native standard library cells on any process node. A faster delay cell circuit allows for a finer resolution in capturing voltage changes. Each of the delay cell circuits in tunable delay circuit <NUM> receives the same supply voltage VCC, as shown in <FIG>.

In the embodiment of <FIG>, the divided clock signal DVCLK is provided to an input of delay cell circuit <NUM>, and the delayed output signal DLY is generated at an output of delay cell circuit <NUM>. Each of the delay cell circuits <NUM>-<NUM> has a data-forward circuit and a data-return circuit that are controlled by the delay code tuning signals DCT generated by the delay configuration circuit <NUM> of <FIG>. One or more of the data-forward circuits in the delay cell circuits <NUM>-<NUM> propagate the rising and falling edges received in the DVCLK signal along a first delay path through the delay chain. One or more of the data-return circuits in the delay cell circuits <NUM>-<NUM> propagate the rising and falling edges received from the last data-forward circuit coupled in the delay chain along a second delay path through the delay chain to the output in signal DLY.

The digital code of the delay code tuning signals DCT determines how many of the delay cell circuits <NUM>-<NUM> are coupled in the delay chain that propagates rising and falling edges received from clock signal DVCLK to the output in signal DLY. The delay configuration circuit <NUM> adjusts the value of the delay code tuning signals DCT to couple more or less of the delay cell circuits <NUM>-<NUM> into the delay chain that couples the input at clock signal DVCLK to the output at signal DLY. For example, an increase in the value of the delay code tuning signals DCT may cause delay circuit <NUM> to couple more of delay cell circuits <NUM>-<NUM> into the delay chain, increasing the delay provided to signal DLY relative to clock signal DVCLK. As another example, a decrease in the value of the delay code tuning signals DCT may cause delay circuit <NUM> to couple fewer of the delay cell circuits <NUM>-<NUM> into the delay chain, decreasing the delay provided to signal DLY relative to clock signal DVCLK.

The value of the delay code tuning signals DCT determines the last delay cell circuit coupled in the delay chain. The last delay cell circuit coupled in the delay chain passes the delayed signal in the first delay path to the second delay path through its data-forward and data-return circuits, decoupling subsequent delay cell circuits from the delay chain, as discussed in further detail below.

The tunable delay circuit <NUM> of <FIG> has <NUM> possible delay settings that are configured by the delay code tuning signals DCT. When signals DCT configure tunable delay circuit <NUM> to have the minimum delay setting, delay cell circuit <NUM> is the only delay cell circuit coupled in the delay chain, and transitions in clock signal DVCLK propagate through the data-forward and data-return circuits in delay cell circuit <NUM> back to the output as delayed signal DLY without passing through any of the other delay cell circuits <NUM>-<NUM>.

When signals DCT configure tunable delay circuit <NUM> to have the second smallest delay setting, delay cell circuits <NUM> and <NUM> are the only delay cell circuits coupled in the delay chain. With the second smallest delay setting, transitions in clock signal DVCLK propagate through the data-forward circuit in delay cell circuit <NUM>, then to delay cell circuit <NUM> as signal D1, then through the data-forward and data-return circuits in delay cell circuit <NUM>, then back to delay cell circuit <NUM> as signal D14, and then through the data-return circuit in delay cell circuit <NUM> to the output as signal DLY.

When signals DCT configure tunable delay circuit <NUM> to have the third smallest delay setting, delay cell circuits <NUM>-<NUM> are the only delay cell circuits coupled in the delay chain. With the third smallest delay setting, transitions in clock signal DVCLK propagate through the data-forward circuit in delay cell circuit <NUM>, then to delay cell circuit <NUM> as signal D1, then through the data-forward circuit in delay cell circuit <NUM>, then to delay cell circuit <NUM> as signal D2, then through the data-forward and data-return circuits in delay cell circuit <NUM>, then back to delay cell circuit <NUM> as signal D13, then through the data-return circuit in delay cell circuit <NUM>, then back to delay cell circuit <NUM> as signal D14, and finally through the data-return circuit in delay cell circuit <NUM> to the output as signal DLY.

When signals DCT configure tunable delay circuit <NUM> to have the maximum delay setting, all <NUM> of the delay cell circuits <NUM>-<NUM> are coupled in the delay chain. With the maximum delay setting, transitions in clock signal DVCLK propagate through the data-forward circuits in delay cell circuits <NUM>-<NUM> to signal D7, passing between the delay cell circuits as signals D1-D7 along the first delay path, as shown in <FIG>. The transitions in signal D7 then propagate through the data-forward and data-return circuits in delay cell circuit <NUM> to signal D8. The transitions in signal D8 then propagate back through the data-return circuits in delay cell circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> to delayed signal DLY, passing between the delay cell circuits as signals D8-D14 along the second delay path, as shown in <FIG>.

<FIG> illustrates an example of a delay cell circuit <NUM>, according to an embodiment. Delay cell circuit <NUM> of <FIG> is an example of each of the delay cell circuits <NUM>-<NUM> in the tunable delay circuit <NUM> of <FIG>. Delay cell circuit <NUM> includes two <NUM>-to-<NUM> multiplexer circuits <NUM> and <NUM>. The A data input of each of the multiplexer circuits <NUM>-<NUM> is coupled to the left input DIL of delay cell circuit <NUM>. The B data input of each of the multiplexer circuits <NUM>-<NUM> is coupled to the right input DIR of the delay cell circuit <NUM>. The output of multiplexer circuit <NUM> is coupled to the left output DOL of the delay cell circuit <NUM>. The output of multiplexer circuit <NUM> is coupled to the right output DOR of the delay cell circuit <NUM>. The inputs DIL and DIR and the outputs DOR and DOL of each of the delay cell circuits <NUM>-<NUM> shown in <FIG> correspond to the DIL and DIR inputs and the DOR and DOL outputs of delay cell circuit <NUM>, respectively. The select input S of multiplexer circuit <NUM> is coupled to receive a first one DCT1 of the delay code tuning signals DCT. The select input S of multiplexer circuit <NUM> is coupled to receive a second one DCT2 of the delay code tuning signals DCT.

In order to configure the delay cell circuit <NUM> to be the last delay cell circuit coupled in the delay chain, the delay code tuning signal DCT1 is set to a logic state that causes multiplexer circuit <NUM> to pass the signal transitions received at input DIL to output DOL. For example, as described above, delay cell circuit <NUM> is the last delay cell circuit coupled in the delay chain when tunable delay circuit <NUM> has the maximum delay setting, and delay cell circuit <NUM> is the last delay cell circuit coupled in the delay chain when tunable delay circuit <NUM> has the minimum delay setting.

In order to configure the delay cell circuit <NUM> to be one of the delay cell circuits coupled in the delay chain other than the last delay cell circuit coupled in the delay chain, the delay code tuning signal DCT2 is set to a logic state that causes multiplexer <NUM> to pass the signal transitions received at input DIL to output DOR, and the delay code tuning signal DCT1 is set to a logic state that causes multiplexer <NUM> to pass the signal transitions received at input DIR to output DOL. When delay cell circuit <NUM> is in this configuration, multiplexer <NUM> is the data-forward circuit, and multiplexer <NUM> is the data-return circuit. Thus, delay cell circuit <NUM> is configurable to implement each of the delay cell circuits <NUM>-<NUM> of <FIG> for each of the <NUM> configurable delay settings of tunable delay circuit <NUM>.

<FIG> illustrates a top down view of an example of a portion <NUM> of an integrated circuit (IC) die that includes TMM circuits, according to an embodiment. Portion <NUM> of the IC die includes <NUM> TMM circuits <NUM>-<NUM> in the example of <FIG>. In other embodiments, an IC die may have any number of TMM circuits. TMM circuit <NUM> of <FIG> is an example of each of the <NUM> TMM circuits <NUM>-<NUM>. TMM circuits <NUM>-<NUM> detect voltage attacks on one or more supply voltages in the IC and indicate the occurrence of a voltage attack in the OVERSHOOT and DROOP signals as described above with respect to <FIG>, before the voltage attack leads to a timing failure that may compromise security functions in the IC die. TMM circuits <NUM>-<NUM> may also detect changes in the supply voltage that occur for other reasons and changes in the temperature of the IC die.

An illustrative programmable logic integrated circuit (IC) <NUM> that may include one or more TMM circuits <NUM> is shown in <FIG>. As shown in <FIG>, programmable logic integrated circuit <NUM> may have input-output circuitry <NUM> for driving signals off of IC <NUM> and for receiving signals from other devices via input-output pads <NUM>. Interconnection resources <NUM> such as global, regional, and local vertical and horizontal conductive lines and buses may be used to route signals on IC <NUM>. Interconnection resources <NUM> include fixed interconnects (conductive lines) and programmable interconnects (i.e., programmable connections between respective fixed interconnects). Programmable logic circuitry <NUM> may include combinational and sequential logic circuitry. The programmable logic <NUM> may be configured to perform custom logic functions.

Claim 1:
A detection circuit (<NUM>) comprising:
a tunable delay circuit (<NUM>) configured to generate a delayed signal (DLY) in response to an input signal, wherein the tunable delay circuit is configured to receive a supply voltage (VCC);
a control circuit (<NUM>, <NUM>) configured to adjust a delay provided by the tunable delay circuit to the delayed signal relative to the input signal; and
a time-to-digital converter circuit (<NUM>) configured to convert the delay provided by the tunable delay circuit to the delayed signal to a digital code,
wherein the time-to-digital converter circuit (<NUM>) is also configured to receive the supply voltage (VCC),
wherein the time-to-digital converter circuit (<NUM>) is configured to change the value of the digital code in proportion to changes in the supply voltage (VCC),
wherein the control circuit is configured to cause the tunable delay circuit to maintain its delay setting constant in response to a value of the digital code reaching an alignment value (ALNVAL), and
wherein the control circuit is configured to detect changes in the supply voltage, while the delay setting of the tunable delay circuit is maintained constant, based on changes in the digital code.