Patent Description:
Embodiments of the disclosure belong to the field of semiconductors and particularly relate to a semiconductor structure and a manufacturing method thereof, a memory chip and an electronic device.

A semiconductor structure includes a plurality of memory cells, and the memory cells need to be connected to a peripheral circuit to execute a storage function. The higher the integration level of the semiconductor structure is, the greater the number of the memory cells capable of being accommodated in the semiconductor structure is, and the more excellent the performance of the semiconductor structure is. However, many spaces in the current semiconductor structure are wasted. Further, due to the limitation from physical properties, the volume of the memory cell has reached the scaling limit, and due to the limitation from process factors, it is also difficult to increase the number of stacked layers of the memory cell.

Therefore, it is an urgent need of a semiconductor structure with a new architecture to improve the integration level of the semiconductor structure. Background may be found in <CIT> and <CIT>.

Embodiments of the disclosure provide a semiconductor structure and a manufacturing method thereof, a memory chip and an electronic device, which at least contributes to improving the integration level of the semiconductor structure.

The present invention is defined in appended independent claims <NUM>, <NUM>, <NUM> and <NUM> to which reference should be made.

It is apparent that the accompanying drawings described below are merely some embodiments of the disclosure, and other drawings can be obtained by those of ordinary skill in the art according to these accompanying drawings without creative efforts.

<FIG> is a top view of a semiconductor structure. <FIG> is an enlarged drawing of a staircase in a dotted circle in <FIG> is a section view of <FIG> in the direction A-A1. Referring to <FIG>, the semiconductor structure includes a memory cell area <NUM> and a staircase area <NUM>. There are multiple layers of memory cells in the memory cell area <NUM>. There are multiple staircases in the staircase area <NUM>, and the staircases and the memory cells are arranged in one-to-one correspondence. A connecting layer (not shown in the drawing) can be arranged in the staircase, a leading wire post <NUM> can be arranged on the staircase, and the leading wire post <NUM> are electrically contacted with the memory cell through the connecting layer in the staircase, so as to lead out the memory cell, so that it is convenient to connect the memory cell to a peripheral circuit. However, with increase of stacked layers of the memory cells, the area occupied by the staircase area <NUM> will be larger and larger. For example, if there are totally <NUM> layers of memory cells, correspondingly, <NUM> staircases are needed, and the lower the staircase is, the larger the area is. If the area of the topmost staircase is <NUM>. <NUM><NUM>, the area of the bottommost staircase is <NUM>*<NUM>. <NUM>= <NUM><NUM>. Referring to <FIG>, the connecting layer below each staircase only provides support and electric connection, so that the bottom space is wasted. Therefore, the integration level of the semiconductor structure needs to be further improved.

The embodiments of the disclosure provide a semiconductor structure. In such semiconductor structure, the plurality of leading wire posts and the plurality of horizontal signal lines are arranged along the third direction, and the leading wire posts and the horizontal signal lines are connected; alternatively, the plurality of leading wire posts extend along the second direction, and orthographic projections of the plurality of leading wire posts on the surface of the substrate are at least partially overlapped with orthographic projections of the horizontal signal lines on the surface of the substrate. That is, the leading wire posts and the horizontal signal lines are directly connected in a parallel manner or an alternative manner. Therefore, it is unnecessary to connect the leading wire posts to the horizontal signal lines through a connection layer in the staircase area, so that the space utilization ratio in the semiconductor structure is improved, thereby improving the integration level of the semiconductor structure.

The embodiments of the disclosure will be described below in detail in combination with the drawings. However, those of ordinary skill in the art may understand that many technical details are provided to better understand the disclosure in the embodiments of the disclosure. However, the technical solutions claimed by the disclosure may also be implemented even though there are no these technical details and various changes and modifications based on the following embodiments.

As shown in <FIG>, an embodiment of the disclosure provide a semiconductor structure. The semiconductor structure includes: a substrate (not shown in the drawings), on which a stacked structure is provided, the stacked structure includes a plurality of memory cell groups TC0 arranged in the first direction X, and each of the memory cell groups TC0 includes multiple layers of memory cells TC arranged in a second direction Z, and the stacked structure further includes a plurality of horizontal signal lines <NUM> arranged in the second direction Z, and each of the horizontal signal lines <NUM> is contacted with one layer of the memory cells TC; and a plurality of leading wire posts <NUM> arranged in a first direction X, the plurality of leading wire posts <NUM> and the plurality of horizontal signal lines <NUM> are arranged along a third direction Y, and the leading wire posts <NUM> are contacted with the horizontal signal lines <NUM>.

That is, the edge of the orthographic projection of the leading wire post <NUM> on the surface of the substrate is in contact with the edge of the orthographic projection of the horizontal signal line <NUM> on the surface of the substrate. In other words, at least part of side walls of the leading wire post <NUM> is directly contacted with a side wall of the horizontal signal line <NUM>, and it is unnecessary to connect indirectly through the connection layer of the staircase area, so that the numbers of the connection layers and the staircases may be decreased, thereby facilitating to improve the integration level of the semiconductor structure.

The semiconductor structure will be described below in detail in combination with the drawings.

It is to be noted first that <FIG> are partial top views. For a more intuitive purpose, <FIG> do not illustrate a structure for isolating and supporting the leading wire post <NUM> in the semiconductor structure. <FIG> illustrates the structure for isolating and supporting the leading wire post <NUM>.

Referring to <FIG>, each horizontal signal line <NUM> is at least contacted with one leading wire post <NUM>. That is, each horizontal signal line <NUM> may be directly contacted with the leading wire post <NUM>, so as to be led out by the leading wire post <NUM>. Therefore, it may be unnecessary to arrange the staircase area independently, so that the space utilization ratio of the semiconductor structure can be improved to a great extent, and it contributes to simplifying the production process.

Exemplarily, referring to <FIG>, the plurality of horizontal signal lines <NUM> are contacted with the plurality of leading wire posts <NUM> in one-to-one correspondence. That is, each horizontal signal line <NUM> is contacted with one leading wire post <NUM>, so as to reduce the connection positions between the horizontal signal lines <NUM> and the leading wire posts <NUM>, and make the production process simpler. In some other embodiments, referring to <FIG>, one horizontal signal line <NUM> may also be contacted with the plurality of leading wire posts <NUM>, so that the contact regions between the horizontal signal line <NUM> and the leading wire posts <NUM> may be increased, and the contact resistance is reduced.

Referring to <FIG>, the leading wire posts <NUM> extend along the second direction Z. That is, the plurality of leading wire posts <NUM> are parallel one another, and the extension directions of the leading wire posts <NUM> are the same as the stacking direction of the memory cells TC, which contributes to simplifying the process and improving the uniformity of the semiconductor structure. Exemplarily, the stacking direction of the memory cells TC is the second direction Z which is perpendicular to the surface of the substrate.

Referring to <FIG>, it is to be noted that with respect to the leading wire post <NUM> contacted with the horizontal signal line <NUM> of the non-top layer, the leading wire post <NUM> may be arranged adjacent to multiple layers of horizontal signal lines <NUM>. It may be known based on a leading function of the leading wire posts <NUM> that, each leading wire post <NUM> is only connected to one horizontal signal line <NUM>, rather than two horizontal signal lines <NUM> at the same time. Otherwise, signal disturbance occurs. In order to facilitate understanding, the horizontal signal line <NUM> connected to the leading wire post <NUM> is called as the horizontal signal line <NUM> of the corresponding layer. The leading wire post <NUM> is arranged to be insulated from horizontal signal lines <NUM>, except the horizontal signal line <NUM> of the corresponding layer. In addition, the leading wire post <NUM> is divided into a contact portion <NUM> and an extension portion <NUM> arranged in a stacked manner. The contact portion <NUM> and the horizontal signal line <NUM> of the corresponding layer are arranged in the same layer and are connect to each other. The extension portion <NUM> is arranged adjacent to the horizontal signal line <NUM> above the corresponding layer, but insulated from the horizontal signal line.

Correspondingly, referring to <FIG>, the stacked structure may further include a dielectric layer <NUM>. The dielectric layer <NUM> is at least located on a side wall of the leading wire post <NUM> facing the horizontal signal line <NUM> above the corresponding layer, and the lower surface of the dielectric layer <NUM> is higher than the horizontal signal line <NUM> connected to the leading wire post <NUM>. That is, the dielectric layer <NUM> is used for isolating the leading wire post <NUM> from the horizontal signal lines <NUM> out of the corresponding layer, so as to avoid incorrect electrical connections. Specifically, the dielectric layer <NUM> may encircle the side walls of the extension portion <NUM> of the leading wire post <NUM>. A material of the dielectric layer <NUM> may be a material with a low dielectric constant, such as silicon nitride or silicon oxide.

In some embodiments, referring to <FIG>, the leading wire posts <NUM> connected to different horizontal signal lines <NUM> are different in length in the second direction Z, and the bottoms of the leading wire posts <NUM> are contacted with the horizontal signal lines <NUM>. Exemplarily, the leading wire post <NUM> connected to the horizontal signal line <NUM> of the top layer is the shortest in the second direction Z, and the leading wire post <NUM> connected to the horizontal signal line <NUM> of the bottom layer is the shortest in the second direction Z, which contributes to saving the material, so as to further reduce the production cost, and further contributes to simplifying the production process. In some other embodiments, the leading wire posts <NUM> may be same in length, but the leading wire posts <NUM> are only connected to the horizontal signal lines <NUM> of the corresponding layer and are arranged to be insulated from the horizontal signal lines <NUM> above and below the corresponding layer.

In order to increase the contact region between the leading wire post <NUM> and the horizontal signal line <NUM> to decrease the contact resistance, the bottom surface of the leading wire post <NUM> may be aligned with the bottom surface of the horizontal signal line <NUM> of the corresponding layer; alternatively, the bottom surface of the leading wire post <NUM> may be slightly lower than the bottom surface of the horizontal signal line <NUM> of the corresponding layer. In some other embodiments, the bottom surface of the leading wire post <NUM> may be higher than the bottom surface of the horizontal signal line <NUM> of the corresponding layer, but lower than the top surface of the horizontal signal line <NUM> of the corresponding layer.

In some embodiments, referring to <FIG>, the adjacent leading wire posts <NUM> are arranged at an equal spacing in the first direction X. That is, the spacing between the adjacent leading wire posts <NUM> is the same, so that the uniformity of the semiconductor structure is improved.

Referring to <FIG>, the leading wire posts <NUM> may be arranged in the order of the length magnitude in the second direction Z. In some other embodiments, referring to <FIG>, the lengths of the leading wire posts <NUM> may not be increased or decreased progressively but alternative in length, so that a large parasitic capacitance is prevented from being generated between the longer leading wire posts <NUM>.

In some other embodiments, referring to <FIG>, a spacing between the adjacent leading wire posts <NUM> is in proportion to an area of a directly facing region. It is to be noted that the area of the directly facing region between the adjacent leading wire posts <NUM> is in proportion to the magnitude of the parasitic capacitance. Therefore, in a case that the area of the directly facing region between the adjacent leading wire posts <NUM> is large, the spacing between the leading wire posts may be correspondingly increased to reduce the parasitic capacitance.

In some embodiments, referring to <FIG>, the stacked structure further includes multiple etching barrier layers <NUM> arranged in the second direction Z, and each etching barrier layer <NUM> is contacted with a bottom surface of at least one leading wire post <NUM>. Specifically, a method for forming the leading wire post <NUM> includes: forming a through hole <NUM> (referring to <FIG>) in one side of the horizontal signal line <NUM> by adopting an etching process, and depositing a conductive material in the through hole <NUM> to form the leading wire post <NUM>. Therefore, the position of the through hole <NUM> decides the position of the leading wire post <NUM>. The etching barrier layer <NUM> may stop etching to realize a self-aligning function, so as to avoid the problem of over-etching or insufficient etching of the through hole <NUM>. That is to say, the etching barrier layers <NUM> and isolation layers <NUM> are alternatively arranged in the second direction Z, the etching barrier layer <NUM> directly faces a gap between the two adjacent horizontal signal lines <NUM>, the isolation layer <NUM> and the horizontal signal line <NUM> are arranged in the same layer, and the etch selectivity ratio of the isolation layer <NUM> to the etching barrier layer <NUM> is large. Exemplarily, a material of the isolation layer <NUM> may be silicon oxide, and a material of the etching barrier layer <NUM> may be silicon nitride. In addition, the etching barrier layer <NUM> may also provide an isolating function.

In some other embodiments, referring to <FIG>, only the isolation layer <NUM> may be arranged on one side of the horizontal signal line <NUM>, and no etching barrier layer <NUM> is arranged. Correspondingly, in the process of forming the through hole <NUM>, the depth of the through hole <NUM> is controlled by means of an etching time. Therefore, only one etching agent may be used, thereby simplifying the manufacturing process.

Referring to <FIG> and <FIG>, the memory cell TC includes a channel region <NUM> and source/drain doped regions <NUM> arranged in the third direction Y, and the source/drain doped regions <NUM> are located on two sides of the channel region <NUM>. That is, the memory cell TC at least includes a transistor T. The memory cell TC further includes a capacitor C. The transistor T and the capacitor C are arranged in the third direction Y. Exemplarily, in a Dynamic Random Access Memory (DRAM), the memory cell TC includes a transistor T and a capacitor C. In some other non-inventive embodiments, the memory cell TC may only include the transistor T. For example, in a Static Random-Access Memory (SRAM), the memory cell TC is composed of six transistors T. For another example, a Capacitorless Double Gate Quantum Well Single Transistor (1T DRAM), the memory cell TC is composed of one dual gate transistor T.

Referring to <FIG>, the stacked structure further includes perpendicular signal lines <NUM> extending along the second direction Z and contacted with multiple layers of memory cells TC of the same memory cell group TC0. One of the horizontal signal line <NUM> and the perpendicular signal line <NUM> is a bit line (BL), and the other of the horizontal signal line <NUM> and the perpendicular signal line <NUM> is a word line (WL). The BL is contacted with the source/drain doped region <NUM>, and the WL is contacted with the channel region <NUM>. The source/drain doped region <NUM> contacted with the BL is called as the first source/drain doped region <NUM>, and the source/drain doped region <NUM> arranged spaced from the BL is called as the second source/drain doped region <NUM>.

Position relationships between the horizontal signal lines <NUM> and the leading wire posts <NUM> will be described below in detail in two situations: the horizontal signal lines are BLs and the horizontal signal lines are WLs.

In a case that the horizontal signal lines <NUM> are BLs, the horizontal signal lines <NUM> and the leading wire posts <NUM> mainly have the following several position relationships.

In example <NUM>, referring to <FIG>, the leading wire post <NUM> and the memory cell TC are respectively located on two opposite sides of the horizontal signal line <NUM> arranged in the third direction Y, that is, the leading wire post <NUM> is located on the side of the horizontal signal line <NUM> away from the memory cell TC. Therefore, it may be more flexible to set arrangement positions and dimensions of the leading wire posts <NUM>.

Specifically, referring to <FIG>, in some embodiments, the leading wire post <NUM> directly faces the memory cell group TC0 in the third direction Y, which contributes to improving the uniformity of position arrangement. In some other embodiments, referring to <FIG>, the leading wire posts <NUM> and the memory cell groups TC0 are arranged alternatively in the first direction X, that is, the leading wire post <NUM> directly faces the space between adjacent memory cell groups TC0. In some other embodiments, referring to <FIG>, the leading wire post <NUM> is arranged simultaneously opposite the memory cell group TC0 and the space between the adjacent memory cell groups TC0. In some other embodiments, referring to <FIG>, a part of leading wire posts <NUM> directly faces the space between adjacent memory cells TC0, and part of leading wire posts <NUM> directly faces the memory cell group TC0.

Continuously referring to <FIG>, in order to reduce the parasitic capacitance between the adjacent leading wire posts <NUM>, the gap between the adjacent leading wire posts <NUM> may be arranged opposite at least one memory cell group TC0. In addition, referring to <FIG>, in order to increase the uniformity of the semiconductor structure, the spacings between the adjacent leading wire posts <NUM> may be the same. In addition, referring to <FIG>, the spacings between the adjacent leading wire posts <NUM> may be adjusted according to different areas of the directly facing regions, so as to balance the parasitic capacitance among different leading wire posts <NUM>.

In some embodiments, referring to <FIG>, the width of the leading wire post <NUM> in the first direction X is equal to the width of the memory cell group TC0, so that it contributes to unifying characteristic sizes of different structures, so as to simplify the production process. In some other embodiments, referring to <FIG>, the width of the leading wire post <NUM> in the first direction X is greater than the width of the memory cell group TC0, so that it contributes to increasing the contact region between the leading wire post <NUM> and the horizontal signal line <NUM> of the corresponding layer, so as to reduce the contact resistance.

In addition, the width of the leading wire post <NUM> in the first direction X may be greater than or equal to the spacing between adjacent memory cell groups TC0. Such arrangement contributes to increasing the contact region between the leading wire post <NUM> and the horizontal signal line <NUM> of the corresponding layer, so as to reduce the contact resistance.

In addition, referring to <FIG>, the width of the leading wire post <NUM> in the first direction X is greater than the width of the leading wire post <NUM> in the third direction Y. It is to be noted that the horizontal signal line <NUM> has a long length in the first direction X, and thus the leading wire post <NUM> has an enough accommodation space in the first direction X. In order to improve the utilization ratio of a semiconductor space while increasing the cross sectional areas of the leading wire posts <NUM>, the leading wire posts <NUM> may be arranged in the first direction X and the third direction Y with certain width differences.

In example <NUM>, referring to <FIG>, the leading wire post <NUM> and the memory cell TC are located on the same side of the horizontal signal line <NUM>. That is, the leading wire post <NUM> is located between adjacent memory cell groups TC0. Therefore, it contributes to making full use of the space position in the stacked structure, thereby improving the space utilization ratio.

Continuously referring to <FIG>, in order to reduce the parasitic capacitance between adjacent leading wire posts <NUM>, the adjacent leading wire posts <NUM> may be spaced by at least two memory cell groups TC0. In addition, referring to <FIG>, in order to increase the uniformity of the semiconductor structure, the number of the memory cell groups TC0 spaced between the adjacent leading wire posts <NUM> may be the same. In addition, referring to <FIG>, the number of the memory cell groups TC0 spaced between the adjacent leading wire posts <NUM> may be adjusted according to different areas of the directly facing regions, so as to balance the parasitic capacitance among different leading wire posts <NUM>.

In some embodiments, referring to <FIG>, the width of the leading wire post <NUM> in the third direction Y is greater than the width of the leading wire post <NUM> in the first direction X. Therefore, not only can the spacing between the adjacent memory cell groups TC0 be reduced, so as to reduce the area occupied by the stacked structure on the surface of the substrate, but also the cross sectional area of the leading wire post <NUM> can be increased, so as to reduce the contact resistance of the leading wire post <NUM>. In some other embodiments, the width of the leading wire post <NUM> in the third direction Y may be equal to the width of the leading wire post <NUM> in the first direction X.

It is to be noted that the example <NUM> and example <NUM> may be combined, that is, part of leading wire posts <NUM> is located on one side of the horizontal signal line <NUM> and the other part of leading wire posts <NUM> is located on the other side of the horizontal signal line <NUM>.

In some embodiments, referring to <FIG>, there is one memory cell in each layer of the memory cell group TC0. In another embodiment, referring to <FIG>, there are two memory cells TC in each layer of the memory cell group TC0, and two memory cells TC are respectively located in two opposite sides of the horizontal signal line <NUM> arranged in the third direction Y. Since the number of the memory cells TC in the memory cell group TC0 is increased, the storage capacity of the semiconductor is correspondingly enhanced.

In some embodiments, referring to <FIG>, part of leading wire posts <NUM> may be located between adjacent memory cells TC0 of a stacked structure, and part of leading wire posts <NUM> may be located between adjacent memory cells TC0 of another stacked structure. That is, a plurality of leading wire posts <NUM> are located on two different sides of the horizontal signal line <NUM>. For example, adjacent leading wire posts <NUM> are located on different sides of the horizontal signal line <NUM>. In other words, two adjacent leading wire posts <NUM> are staggered in the first direction X, so that the parasitic capacitance may be reduced.

In some other embodiments, referring to <FIG>, all the leading wire posts <NUM> are located on the same side of the horizontal signal line <NUM>, so that it contributes to improving the uniformity of the arrangement mode of the leading wire posts <NUM>, so as to simplify the manufacturing process of the semiconductor.

It is to be noted that in some embodiments, one leading wire post <NUM> may only be used for leading out one horizontal signal line <NUM> of one stacked structure. In some other embodiments, one leading wire post <NUM> may be shared by two stacked structures. Specifically, referring to <FIG>, <FIG> is a top view, and <FIG> is a section view of <FIG> in the third direction Y. The horizontal signal lines <NUM> of two adjacent stacked structures are arranged opposite. The leading wire post <NUM> is located between the horizontal signal lines <NUM> of the adjacent stacked structures, and the horizontal signal lines <NUM> of the same layer of the adjacent stacked structures are electrically connected through at least one leading wire post <NUM>. Since the leading wire post <NUM> may be shared by two stacked structures, the number of the leading wire posts <NUM> may be decreased, so that it contributes to reducing the volume of the semiconductor structure.

It is to be noted that although the horizontal signal lines <NUM> of two stacked structures are electrically connected, the memory cells TC corresponding to the horizontal signal lines <NUM> are still controlled by different WLs, and therefore, the memory cells TC of the two stacked structures can still be controlled independently.

In a case that the horizontal signal lines <NUM> are WLs, the horizontal signal lines <NUM> and the leading wire posts mainly have the following several position relationships.

First, it is to be noted that there are various position relationships between the WL and the channel region <NUM>. For example, the WL may cover the entire channel region <NUM>. Alternatively, the WL(s) may be contacted with the top surface and/or the bottom surface of the channel region <NUM>. If the WL covers the entire channel region <NUM>, the area of the side wall of the WL is larger. Since the side wall of the WL is contacted with a side wall of the leading wire post <NUM>, the larger area of the side wall of the WL is beneficial to increasing the contact region between the WL and the leading wire post <NUM>, thereby reducing the contact resistance. In a case that the WLs are located on the top surface and the bottom surface of the channel region <NUM>, in order to increase the contact regions, the leading wire posts <NUM> may be simultaneously contacted with the WLs on the top surface and the bottom surface of the channel region <NUM>.

In some other embodiments, referring to <FIG>, all the leading wire posts <NUM> are located on the same side of the horizontal signal line <NUM>, so that it contributes to improving the uniformity of the arrangement of the leading wire posts <NUM>, so as to simplify the manufacturing process of the semiconductor. Exemplarily, referring to <FIG>, all the leading wire posts <NUM> are located on the side of the horizontal signal line <NUM> close to the first source/drain doped region <NUM>. Referring to <FIG>, all the leading wire posts <NUM> are located on the side of the horizontal signal line <NUM> close to the second source/drain doped region <NUM>.

Referring to <FIG>, in order to reduce the parasitic capacitance, the adjacent leading wire posts <NUM> may be spaced at least by two memory cell groups TC0. In addition, referring to <FIG>, in order to increase the uniformity of the semiconductor structure, the number of memory cell groups TC0 between the adjacent leading wire posts <NUM> may be the same. Alternatively, referring to <FIG>, the number of the memory cell groups TC0 spaced between the adjacent leading wire posts <NUM> may be adjusted according to different areas of the directly facing regions, so as to balance the parasitic capacitance among different leading wire posts <NUM>.

In some other embodiments, referring to <FIG>, part of leading wire posts <NUM> may be located on one side of the horizontal signal line <NUM> and part of leading wire posts <NUM> may be located on the other side of the horizontal signal line <NUM>. Exemplarily, adjacent leading wire posts <NUM> are located on different sides of the horizontal signal line <NUM>, that is, the leading wire posts <NUM> may be staggered in the first direction X, so that the parasitic capacitance is reduced.

In an embodiment of the disclosure, the plurality of leading wire posts <NUM> and the plurality of horizontal signal lines are arranged along the third direction Y, and the leading wire posts <NUM> are connected to the horizontal signal lines <NUM>. That is, an edge of the orthographic projection of the leading wire posts <NUM> on the surface of the substrate is in contact with an edge of the orthographic projection of the horizontal signal line <NUM> on the surface of the substrate. Since the leading wire posts <NUM> are directly connected to the horizontal signal lines <NUM>, the numbers of the connection layers and the staircases may be decreased, thereby improving the integration level of the semiconductor structure.

As shown in <FIG>, another embodiment of the disclosure provides a semiconductor structure. The semiconductor structure is substantially same as the semiconductor structure in the aforementioned embodiments. The main difference lies in that orthographic projections of the plurality of leading wire posts <NUM> of the semiconductor structure on the surface of the substrate are at least partially overlapped with orthographic projections of the horizontal signal lines <NUM> on the surface of the substrate. Parts of the semiconductor structure same as or similar to the semiconductor structure in the aforementioned embodiments refer to detailed description in the aforementioned embodiments, which is not elaborated herein.

The semiconductor structure includes: a substrate (not shown in the drawings), on which a stacked structure is provided, and the stacked structure includes a plurality of memory cell groups TC0 arranged in the first direction X, and each of the memory cell groups TC0 includes multiple layers of memory cells TC arranged in the second direction Z, and the stacked structure further includes a plurality of horizontal signal lines <NUM> arranged in the second direction Z, and each of the horizontal signal lines <NUM> is contacted with one layer of the memory cells TC; a plurality of leading wire posts <NUM> arranged in the first direction X and extending along the second direction Z, and orthographic projections of the plurality of leading wire posts <NUM> on the surface of the substrate are at least partially overlapped with orthographic projections of the horizontal signal lines <NUM> on the surface of the substrate, and the leading wire posts <NUM> are connected to the horizontal signal lines <NUM>.

That is, the leading wire posts <NUM> are directly connected to the horizontal signal lines <NUM> in an alternative manner by at least utilizing the space positions of part of the horizontal signal lines <NUM>, so that it contributes to reducing the number of staircases or it is no longer to arrange a staircase area independently, thereby improving the integration level of the semiconductor structure.

Referring to <FIG>, the leading wire post <NUM> is located on the top surface of the horizontal signal line <NUM> of the corresponding layer, and the bottom surface of the leading wire post <NUM> is contacted with the top surface of the horizontal signal line <NUM> of the corresponding layer. In some other embodiments, the bottom of the leading wire post <NUM> may be embedded into the horizontal signal line <NUM> of the corresponding layer; alternatively, the bottom of the leading wire post <NUM> may penetrate through the horizontal signal line <NUM> of the corresponding layer, that is, the side wall of the leading wire post <NUM> may also be contacted with the horizontal signal line <NUM> of the corresponding layer.

Referring to <FIG>, <FIG>, <FIG> and <FIG>, at least one leading wire post <NUM> penetrates through at least one horizontal signal line <NUM>, that is, at least one of the leading wire posts <NUM> is connected to the horizontal signal line <NUM> of the non-top layer. It is to be noted that the leading wire post <NUM> connected to the horizontal signal line <NUM> of the non-top layer needs to occupy, besides the space position of the horizontal signal line <NUM> of the corresponding layer, the space position of the horizontal signal line <NUM> above the corresponding layer. Therefore, the leading wire post <NUM> will penetrate through the horizontal signal line <NUM> located above the corresponding layer. Referring to <FIG>, with respect to the leading wire post <NUM> connected to the horizontal signal line <NUM> of the top layer, the leading wire post <NUM> does not need to penetrate through the horizontal signal lines <NUM> out of the corresponding layer.

It is to be noted that the leading wire post <NUM> penetrates through the horizontal signal line <NUM> located above the corresponding layer <NUM>, but the horizontal signal line <NUM> above the corresponding layer is not truncated completely.

Specifically, referring to <FIG>, the horizontal signal line <NUM> includes a contact region <NUM> and an exposed region <NUM> arranged in the third direction Y; the leading wire post <NUM> is connected to the contact region <NUM>, and the exposed region <NUM> is exposed; and the third direction Y is perpendicular to the second direction Z and parallel to the surface of the substrate. That is to say, the leading wire post <NUM> is contacted with the contact region <NUM> of the horizontal signal line <NUM> of the corresponding layer and penetrates through the contact region <NUM> of the horizontal signal line <NUM> located above the corresponding layer, and the exposed regions <NUM> of all the horizontal signal lines <NUM> are exposed. Although the horizontal signal line <NUM> above the corresponding layer is penetrated, the horizontal signal line <NUM> will not be completely truncated since the exposed regions <NUM> are reserved, and the horizontal signal line <NUM> may still be contacted with the memory cell TC of the same layer.

In some embodiments, referring to <FIG> illustrates a partial enlarged drawing of the horizontal signal line <NUM> of the corresponding layer and the leading wire post <NUM> in <FIG>. The exposed regions <NUM> are located on two opposite sides of the contact region <NUM>. The orthographic projection of the leading wire post <NUM> on the surface of the substrate is overlapped with the orthographic projection of the contact region <NUM> on the surface of the substrate. That is to say, the contact region <NUM> is located in a center position of the horizontal signal line <NUM>, the leading wire post <NUM> is connected to the center of the horizontal signal line <NUM> of the corresponding layer and penetrates through the center of the horizontal signal line <NUM> located above the corresponding layer, the exposed regions <NUM> of the horizontal signal line <NUM> are not truncated, and the horizontal signal line <NUM> may still be contacted with the memory cells TC of the same layer.

In some other embodiments, referring to <FIG>, <FIG> illustrates a partial enlarged drawing of the horizontal signal line <NUM> of the corresponding layer and the leading wire post <NUM> in <FIG>, <FIG> illustrates a partial enlarged drawing of the horizontal signal line <NUM> of the corresponding layer and the leading wire post <NUM> in <FIG>, and <FIG> is a top view of the semiconductor structure shown in <FIG>. The horizontal signal line <NUM> has two opposite sides arranged in the third direction Y, the exposed region <NUM> is located on one of the two opposite sides, and the contact region <NUM> is located on the other of the two opposite sides. That is, the leading wire post <NUM> is contacted with one side of the horizontal signal line <NUM> of the corresponding layer and the other side of the horizontal signal line <NUM> is exposed, the leading wire post <NUM> penetrates through one side of the horizontal signal line <NUM> above the corresponding layer, and the other side of the horizontal signal line <NUM> above the corresponding layer is not penetrated.

In an example, referring to <FIG>, the orthographic projection of the leading wire post <NUM> on the surface of the substrate is overlapped with the orthographic projection of the exposed region <NUM> on the surface of the substrate. That is, in the direction parallel to the substrate, the leading wire post <NUM> utilizes the space position of the horizontal signal line <NUM> and does not exceed the horizontal signal line <NUM>, so that it contributes to improving the compact degree between the leading wire post <NUM> and the horizontal signal line <NUM>, so as to improve the space utilization ratio.

In another example, referring to <FIG>, the leading wire post <NUM> is protruded relative to the contact region <NUM>. That is, the leading wire post <NUM> is protruded relative to one side of the horizontal signal line <NUM>. That is to say, only part of the bottom surface of the leading wire post <NUM> is in contact connection with the contact region <NUM>. Protruding arrangement may reduce the area of the horizontal signal line <NUM> above the corresponding layer penetrated by the leading wire post <NUM>, so that the resistance of the horizontal signal line <NUM> above the corresponding layer is reduced. Meanwhile, it may further guarantee that the leading wire post <NUM> has a large cross sectional area, so that the resistance of the leading wire post <NUM> is reduced.

It is to be noted that in some embodiments, the horizontal signal line <NUM> may be strip-like, that is, the orthographic projection of the horizontal signal line <NUM> on the surface of the substrate is rectangular. In some other embodiments, the horizontal signal line <NUM> may include a main body portion and a protrusion portion connected with each other. The main body portion is strip-like, and the protrusion portion may be in shapes such as square or zigzag, that is, the length of the protrusion portion in the first direction X is smaller than the length of the main body portion in the first direction X. The main body portion and the protrusion portion may be arranged in the third direction Y. The main body portion is contacted with the memory cell group TC0, and the protrusion portion is contacted with the leading wire post <NUM>. Exemplarily, the bottom surface of the leading wire post <NUM> is contacted with the top surface of the protrusion portion of the corresponding layer, and therefore, the leading wire post <NUM> may not need to penetrate through the main body portion above the corresponding layer, so that it contributes to reducing the resistance of the horizontal signal line <NUM> above the corresponding layer.

Referring to <FIG>, the memory cell TC includes the channel region <NUM> and source/drain doped regions <NUM> arranged in the third direction Y, and the source/drain doped regions <NUM> are located on two sides of the channel region <NUM>. That is, the memory cell TC at least includes the transistor T. In some other embodiments, the memory cell TC may further include the capacitor C, and the transistor T and the capacitor C are arranged in the third direction Y. The source/drain doped regions <NUM> may include the first source/drain doped region <NUM> and the second source/drain doped region <NUM>, the first source/drain doped region <NUM> may be contacted with the BL, and the second source/drain doped region <NUM> may be located on the side of the channel region <NUM> away from the first source/drain doped region <NUM>.

The stacked structure also includes perpendicular signal lines <NUM> extending along the second direction Z and connected to multiple layers of memory cells TC in the same memory cell group TC0. One of the horizontal signal line <NUM> and the perpendicular signal line <NUM> is a BL, and the other of the horizontal signal line <NUM> and the perpendicular signal line <NUM> is a WL. The BL is contacted with the source/drain doped region <NUM>, and the WL is contacted with the channel region <NUM>.

In example <NUM>, referring to <FIG>, the leading wire post <NUM> directly faces the memory cell group TC0 in the third direction Y. Therefore, it contributes to improving the uniformity of position arrangement.

In example <NUM>, referring to <FIG>, the leading wire posts <NUM> and the memory cell groups TC are arranged alternatively in the first direction X. That is, the leading wire post <NUM> may directly face the space between adjacent memory cell groups TC0.

In example <NUM>, referring to <FIG>, the leading wire post <NUM> is arranged simultaneously opposite the memory cell group TC0 and the space between the adjacent memory cell groups TC0.

It is to be noted that in the case that the horizontal signal line <NUM> is the BL, in order to prevent the leading wire post <NUM> from cutting off the connection between the horizontal signal line <NUM> above the corresponding layer and the memory cell TC, the exposed region <NUM> may be located on the side close to the memory cell TC, and the contact region <NUM> may be located on the side away from the memory cell TC; alternatively, the exposed regions <NUM> may be located on two opposite sides of the contact region <NUM>.

In some embodiment, referring to <FIG>, there are two memory cells TC in each layer of the memory cell group TC0, and the two memory cells TC are respectively located in two opposite sides of the horizontal signal line <NUM> arranged in the third direction Y. In such case, one leading wire post <NUM> leads out more memory cells TC through the horizontal signal line <NUM>, thereby facilitating to improve the integration level of the semiconductor structure.

In a case that the horizontal signal lines <NUM> are the WLs, the horizontal signal lines <NUM> and the leading wire posts <NUM> mainly have the following several position relationships.

In example <NUM>, referring to <FIG>, the leading wire post <NUM> is located between adjacent memory cell groups TC0, that is, the leading wire post <NUM> and the channel region <NUM> are staggered, so that the leading wire post <NUM> may be prevented from truncating the memory cell TC located above the corresponding layer, thereby reducing the number of the invalid memory cells TC.

In example <NUM>, referring to <FIG>, the orthographic projection of the leading wire post <NUM> on the surface of the substrate is overlapped with the orthographic projection of the channel region <NUM> on the surface of the substrate. That is, the leading wire post <NUM> may lead out the horizontal signal line <NUM> by utilizing the position of the channel region <NUM>, so that it contributes to reducing the spacing between adjacent memory cell groups TC0, so as to improve the compact degree of the memory cell groups TC0, thereby improving the failure rate of the semiconductor structure.

In another embodiment of the disclosure, edges of the orthographic projection of the leading wire posts <NUM> on the surface of the substrate and the orthographic projection of the horizontal signal line <NUM> on the surface of the substrate are overlapped. That is, the leading wire post <NUM> may be directly connected to the horizontal signal line <NUM> by utilizing the space of the horizontal signal line <NUM> itself, and thus the numbers of the connection layers and the staircases may be decreased, thereby improving the integration level of the semiconductor structure.

As shown in <FIG>, another embodiment of the disclosure provides a method for manufacturing a semiconductor structure. It is to be noted that in order to conveniently describe and clearly illustrate operations of the method for manufacturing a semiconductor structure, <FIG> all are partial schematic structural diagrams of the semiconductor structure. The method for manufacturing a semiconductor structure provided by an embodiment of the disclosure will be described below in detail in combination with the drawings.

A substrate is provided. A stacked structure is formed on the substrate, the stacked structure includes a plurality of memory cell groups TC0 arranged in a first direction X, and each of the memory cell groups TC0 includes multiple layers of memory cells TC arranged in a second direction Z. The stacked structure further includes a plurality of horizontal signal lines <NUM> arranged in the second direction Z, and each of the horizontal signal lines <NUM> is contacted with one layer of the memory cells TC.

Exemplarily, the memory cell TC may include the transistor T and the capacitor C. Specifically, the operation of forming the transistor T may include the following operations. Multiple spaced active layers are formed, and each of the active layers includes a plurality of active structures. The active structure is doped, so as to form the source/drain doped regions <NUM> and the channel region <NUM>. A gate dielectric layer <NUM> is formed on the surface of the channel region <NUM>. That is to say, the memory cell TC includes the channel region <NUM> and the source/drain doped regions <NUM> arranged in the third direction Y, and the source/drain doped regions <NUM> are located on two sides of the channel region <NUM>; and the third direction Y is parallel to the surface of the substrate. In addition, it is necessary to form the insulating layer <NUM> between the transistors T of adjacent layers, so as to isolate the adjacent transistors T. The operation of forming the capacitor C may include the following operations. A capacitor supporting layer and a capacitor hole located in the capacitor supporting layer are formed. A lower electrode is formed on the inner wall of the capacitor hole, a capacitor dielectric layer <NUM> is formed on the surface of the lower electrode, and an upper electrode is formed on the surface of the capacitor dielectric layer <NUM>. The lower electrode, the capacitor dielectric layer <NUM> and the upper electrode form the capacitor C.

A plurality of leading wire posts <NUM> arranged in the first direction X are formed. The plurality of leading wire posts <NUM> and the plurality of horizontal signal lines are arranged along the third direction Y, and the leading wire posts <NUM> are connected to the horizontal signal lines <NUM>.

The method for forming the leading wire post <NUM> will be described below in detail.

It is to be noted first that the plurality of horizontal signal lines <NUM> include the first to Nth horizontal signal lines successively arranged in the second direction Z, N being a positive integer greater than <NUM>. The first horizontal signal line is located in the top layer, and the Nth horizontal signal line is located in the bottom layer.

Referring to <FIG>, the through hole <NUM> is formed. The through hole <NUM> includes the first through hole to the Nth through hole, a side wall of the first horizontal signal line is exposed by the first through hole, and side walls of the first horizontal signal line to the Nth horizontal signal line are exposed by the Nth through hole.

Taking the horizontal signal line <NUM> being a BL as an example, the operations of forming the through hole <NUM> will be described in detail.

Referring to <FIG>, an isolation structure is formed on the side wall of the horizontal signal line <NUM>. In some embodiments, the isolation structure may include an etching barrier layer <NUM> and an isolation layer <NUM> arranged alternately. The isolation layer <NUM> and the horizontal signal line <NUM> are arranged in the same layer, and the etching barrier layer <NUM> is arranged directly opposite the insulating layer <NUM> between the adjacent horizontal signal lines <NUM> (referring to <FIG>). In some other embodiments, the isolation structure may only include the isolation layer <NUM>, and the isolation layer <NUM> covers the side walls of the horizontal signal line <NUM> and the insulating layer <NUM>.

Continuously referring to <FIG>, a mask layer <NUM> is formed. The mask layer <NUM> has N openings <NUM>, N being a positive integer greater than <NUM>. The openings <NUM> are located on one side of the horizontal signal line <NUM>. Exemplarily, the mask layer <NUM> may be a photoresist layer, and the photoresist layer is photoetched to form the openings <NUM>. Alternatively, the mask layer <NUM> may be a hard mask layer <NUM> and a photoresist layer arranged in a stacked manner, and after the photoresist layer is photoetched, the hard mask layer <NUM> is etched, so as to form the openings <NUM>.

Referring to <FIG>, the isolation layer <NUM> of the top layer is etched along the openings <NUM> until the etching barrier layer <NUM> of the top layer is exposed, so as to form a plurality of first sub-through holes <NUM>. The first sub-through holes <NUM> expose side walls of the first horizontal signal line, and one of the first sub-through holes <NUM> serves as the first through hole <NUM>.

Referring to <FIG>, a sacrificial layer <NUM> filling the first sub-through holes <NUM> is formed. Exemplarily, a material with a low dielectric constant, such as silicon oxide, is deposited in the first sub-through holes <NUM> to serve as the sacrificial layer <NUM>.

Continuously referring to <FIG>, the mask layer <NUM> is patterned to enable the mask layer <NUM> to have (N-<NUM>) openings <NUM>. Specifically, the photoresist layer may be spin-coated again and photoetched, to form the openings <NUM>.

Referring to <FIG>, the sacrificial layer <NUM> and the isolation layer <NUM> of the second layer are etched along the openings <NUM> to form (N-<NUM>) second sub-through holes <NUM>. One of the second sub-through holes <NUM> serves as a second through hole <NUM>.

Referring to <FIG>, the operations of forming the sacrificial layer <NUM>, patterning the mask layer <NUM> and etching are repeated untill the side wall of the Nth horizontal signal line <NUM> is exposed, that is, the top surface of the Nth etching barrier layer is exposed.

Based on <FIG>, the through holes <NUM> may be formed, and the through holes <NUM> include the first through hole <NUM> to the Nth through hole <NUM>. Exemplarily, referring to <FIG>, the first through hole <NUM>, the second through hole <NUM>, the third through hole <NUM>, the fourth through hole <NUM> and the fifth through hole <NUM> may be formed. It is to be noted that in the first direction X, depths of the first through hole <NUM>, the second through hole <NUM>, the third through hole <NUM>, the fourth through hole <NUM> and the fifth through hole <NUM> successively arranged are increased in sequence. In other embodiments, in the first direction X, depths of the first through hole <NUM>, the second through hole <NUM>, the third through hole <NUM>, the fourth through hole <NUM> and the fifth through hole <NUM> successively arranged may not be progressively increased or decreased, but the through holes are formed alternatively in depth, so as to avoid too large parasitic capacitance between the leading wire posts <NUM> with large depths among the subsequently formed leading wire posts <NUM>.

It is to be noted that in a case that the horizontal signal line <NUM> is the WL, the operations of forming the through holes <NUM> are similar to the aforementioned operations, and the main difference lies in that the insulating layer <NUM> between the adjacent memory cell groups TC0 is etched to form the through holes <NUM>. Other operations about forming the mask layer <NUM> and the sacrificial layer <NUM> may refer to the above detailed description.

Referring to <FIG>, the first contact portion to the Nth contact portion are respectively formed at the bottoms of the first through hole <NUM> to the Nth through hole, the first contact portion to the Nth contact portion are respectively arranged in the same layers as the first horizontal signal line to the Nth horizontal signal line <NUM>, and the contact portion <NUM> covers the side wall of the first horizontal signal <NUM> of the corresponding layer.

Continuously referring to <FIG>, after the contact portion <NUM> is formed, the dielectric layer <NUM> is formed on the side wall of the through hole <NUM>. Exemplarily, an initial dielectric layer is formed on the side wall of the through hole <NUM> and the surface of the contact portion <NUM> through a chemical vapor deposition process. The initial dielectric layer on the surface of the contact portion <NUM> is removed, and the initial dielectric layer located on the side wall of the through hole <NUM> serves as the dielectric layer <NUM>.

Continuously referring to <FIG>, an extension portion <NUM> filling the through hole <NUM> is formed, and the contact portion <NUM> and the extension portion <NUM> form the leading wire post <NUM>. Exemplarily, metals such as copper, aluminum, titanium or tungsten are deposited in the through hole <NUM> as the leading wire post <NUM>.

It is to be noted that the abovementioned method for forming the leading wire post <NUM> is merely exemplary description but is not limited thereto. The method for forming the leading wire post <NUM> may be adjusted according to a specific structure of the leading wire post <NUM>.

As shown in <FIG>, another embodiment of the disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure is substantially same as the aforementioned method for manufacturing a semiconductor structure, and same or similar parts refer to detailed description in the aforementioned embodiments. In order to conveniently describe and clearly illustrate operations of the method for manufacturing a semiconductor, <FIG> all are partial schematic structural diagrams of the semiconductor structure. The method for manufacturing a semiconductor structure will be described below in detail in combination with the drawings.

The method about forming the stacked structure may refer to detailed description of the aforementioned embodiments.

Referring to <FIG>, the plurality of leading wire posts <NUM> arranged in the first direction and X and extending along the second direction Z are formed. Orthographic projections of the plurality of leading wire posts <NUM> on the surface of the substrate are at least partially overlapped with orthographic projections of the horizontal signal lines <NUM> on the surface of the substrate, and the leading wire posts <NUM> are connected to the horizontal signal lines <NUM>.

The method for manufacturing the leading wire posts <NUM> will be described below in detail.

Referring to <FIG>, the through holes <NUM> are formed, and the through holes <NUM> include the first through hole <NUM> to the Nth through hole. The top surface of the first horizontal signal line is exposed by the first through hole <NUM>; the Nth through hole penetrates through the first horizontal signal line to the (N-<NUM>)th horizontal signal line, and exposes the top surface of the Nth horizontal signal line.

The operations of forming the through hole <NUM> are substantially same as the operations in the aforementioned embodiments, and the main difference lies in that the through hole <NUM> penetrates through one or more horizontal signal lines <NUM>, and therefore, it is necessary to etch the one or more horizontal signal lines <NUM>. In addition, in a case that the leading wire post <NUM> utilizes the position of the memory cell group TC0, it is further necessary to etch the channel region <NUM> and the insulating layer <NUM> located between memory cells TC of the upper layer and memory cells TC of the lower layer when the through hole <NUM> is formed; and in a case that the leading wire post <NUM> utilizes the position between the adjacent memory cell groups TC0, it is further necessary to etch the insulating layer <NUM> between adjacent memory cells TC when the through hole <NUM> is formed. Other operations about forming the mask layer <NUM> and the sacrificial layer <NUM> may refer to detailed description of the aforementioned embodiments.

Referring to <FIG>, the dielectric layer <NUM> is formed on the side wall of the through hole <NUM>. Specifically, an initial dielectric layer is formed on the inner walls of the through hole <NUM>. The initial dielectric layer located on the bottom wall of the through hole <NUM> is removed to expose the horizontal signal line <NUM> of the corresponding layer, and the initial dielectric layer located on the side wall of the through hole <NUM> serves as the dielectric layer <NUM>. The leading wire post <NUM> filling the through hole <NUM> is formed, and the bottom surface of the leading wire post <NUM> is electrically connected to the horizontal signal line <NUM>.

In the embodiments of the disclosure, the horizontal signal line <NUM> is etched to form the through hole <NUM>, and the dielectric layer <NUM> and the leading wire post <NUM> filling the through hole <NUM> are formed. Therefore, the leading wire post <NUM> may be electrically connected to the horizontal signal line <NUM> directly by utilizing the spatial position of the horizontal signal line <NUM>, so that the number of the staircases may be reduced or the independent staircase area is not formed, thereby improving the integration level of the semiconductor structure.

The embodiments of the disclosure further provide a memory chip, including the semiconductor structure provided by the aforementioned embodiments.

The memory chip is a memory part for storing programs and various data information. Exemplarily, the memory chip may be a random access memory chip or a read-only memory chip. For example, the random access memory chip may include a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM). The integration level of the aforementioned semiconductor structure is high, which contributes to realizing microminiaturization of the memory chip.

The embodiments of the disclosure further provide an electronic device, including the memory chip provided by the aforementioned embodiments.

Exemplarily, the electronic device may be a device such as a television, a computer, a mobile phone or a tablet computer. The electronic device may include a circuit board and a package structure, and the memory chip may be welded to the circuit board and protected by the package structure. In addition, the electronic device may further include a power supply for providing an operating voltage to the memory chip.

In the description of the specification, the description with reference to the terms "some embodiments", "exemplarily", and the like means that specific features, structures, materials, or features described in combination with the embodiments or examples are included in at least one embodiment or example of the disclosure. In the description, schematic expressions of the terms do not have to mean same embodiments or exemplary embodiments. Furthermore, specific features, structures, materials or characteristics described can be combined in any one or more embodiments or exemplary embodiments in proper manners. In addition, those skilled in the art can integrate or combine, without mutual contradiction, different embodiments or exemplary embodiments and integrate or combine features of different embodiments or exemplary embodiments described in the description.

Claim 1:
A semiconductor structure, comprising:
a substrate, on which a stacked structure is provided, wherein
the stacked structure comprises a plurality of memory cell groups (TCO) arranged in a first direction, each of the memory cell groups (TCO) comprising multiple layers of memory cells (TC) arranged in a second direction, and the stacked structure further comprises a plurality of horizontal signal lines (<NUM>) arranged in the second direction, each of the horizontal signal lines (<NUM>) being in contact with one layer of the memory cells (TC), wherein each memory cell (TC) comprises a transistor and a capacitor; and
a plurality of leading wire posts (<NUM>) arranged in the first direction, wherein the plurality of leading wire posts (<NUM>) and the plurality of horizontal signal lines (<NUM>) are arranged along a third direction, and the leading wire posts (<NUM>) are connected to the horizontal signal lines (<NUM>),
characterized in that
the plurality of leading wire posts (<NUM>) and the plurality of memory cell groups (TCO) are located on two opposite sides of the plurality of horizontal signal lines (<NUM>) respectively;
wherein the plurality of leading wire posts (<NUM>) and the plurality of memory cell groups (TCO) are directly opposite in the third direction; or the plurality of leading wire posts (<NUM>) and the plurality of memory cell groups (TCO) are arranged alternatively in the first direction.