Patent Description:
In computing applications, random-access memory (RAM) typically provides higher speed access but less total storage capacity than primary storage (e.g., hard drive storage or solid-state drive (SSD) storage). One key difference between RAM and the primary storage including NAND memory for SSD is that RAM is a byte-addressable device and accessed with memory-semantic LOAD(READ) and STORE(WRITE) commands while storage is block-addressable device and accessed with block storage protocols such Small Computer System Interface (SCSI) and Non-Volatile Memory express (NVMe). Dynamic RAM (DRAM) is a type of RAM and often used in digital electronics to provide affordable, high-speed, and high-capacity memory. A dual-inline memory module (DIMM) form factor is typically used to attach a DRAM module to a motherboard. In some examples, DRAM DIMM devices use single-port single-ended high-speed signals for attachment to a memory controller or central processing unit (CPU) with an integrated DRAM controller. A typical DRAM DIMM includes a memory module that houses multiple DRAM devices. As processing speed continue to increase, the demand for larger and faster access to DRAM will continue to increase. As different applications may have different memory capacity requirements, it is desirable that the memory capacity of a compute node or server could be changed on-demand dynamically without changing the DIMMs, such as to provide composable computing.

<CIT> discloses an apparatus including a non-volatile memory module for insertion into a rack implemented modular computer. The non-volatile memory module includes a plurality of memory controllers. The non-volatile memory includes respective non-volatile random access memory coupled to each of the memory controllers. The non-volatile memory module includes a switch circuit to circuit switch incoming requests and outgoing responses between the rack's backplane and the plurality of memory controllers. The incoming requests are sent by one or more CPU modules of the rack implemented modular computer. The outgoing responses are sent to the one or more CPU modules.

It is an object of various embodiments to provide an efficient architecture and methodology for implementing a dual-port RAM module to provide improved memory capacity composability, expansion and sharing. In particular, this dual-port RAM module uses high-speed SerDes (e.g., <NUM> NRZ, <NUM> PAM4, etc.) based redundant access ports for connection to multiple CPUs or compute nodes, where each access port may access part or all of the module's memory capacity under software configuration. This provides improved memory capacity composability and expansion through memory sharing and provides improved memory access performance and reliability. The Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

According to a first aspect of the present disclosure, there is provided a dual-port memory module device operable to access computer memory, the device comprising: a plurality of memory media chips providing random access memory (RAM) capacity; and a dual-port memory controller application specific integrated circuit (ASIC) operable to allocate a first portion of the RAM capacity to a first computing host and a second portion of the RAM capacity to a second computing host, the dual-port memory controller ASIC including: a first interface port coupled to a first computing host; a second interface port coupled to a second computing host; and a plurality of memory interface channels operable to configure, read data from, and write data to the plurality of memory media chips.

The device further includes a management port operable to receive module configuration and management data from a configuration management server, the allocation of the a first portion of the RAM capacity and the second portion of the RAM capacity is based on the received module configuration and management data.

In an embodiment of the dual-port memory module device according to the first aspect as such, the plurality of memory media chips includes at least one of DRAM, SRAM, HBM, STT-MRAM, or PCM.

In an embodiment of the dual-port memory module device according to the first aspect as such, the device further includes a protocol agnostic multi-lane connector operable to: couple the first interface port to the first computing host; couple the second interface port to the second computing host; and couple the management port to the configuration management server.

In an embodiment of the dual-port memory module device according to the first aspect as such, the protocol agnostic multi-lane connector includes an SF-TA-<NUM> compliant PCB connector.

In an embodiment of the dual-port memory module device according to the first aspect as such, the first computing host accesses the first portion of the RAM capacity and the second computing host accesses the second portion of the RAM capacity with memory-semantic LOAD(READ) and STORE(WRITE) commands.

In an embodiment of the dual-port memory module device according to the first aspect as such, the first interface port and the second interface port each include a Serial and Deserializer (SerDes) port consisting of a plurality of differential lanes for memory access protocol communication.

In an embodiment of the dual-port memory module device according to the first aspect as such, the first interface port and the second interface port each may include an optional differential clock input.

In an embodiment of the dual-port memory module device according to the first aspect as such, the dual-port memory controller ASIC is further operable to configure the memory media chips for access by the first computing host and the second computing host.

In an embodiment of the dual-port memory module device according to the first aspect as such, the device further includes a serial presence detect device, wherein: the dual-port memory controller ASIC reads a memory media configuration from the serial presence detect device; and the configuration of the memory media chips is based on the memory media configuration.

In an embodiment of the dual-port memory module device according to the first aspect as such, the memory media configuration includes at least one of a memory media type, a memory media capacity, a memory media speed, or a number of memory media chips.

In an embodiment of the dual-port memory module device according to the first aspect as such, the dual-port memory controller ASIC is further operable to: store memory usage allocation data that indicates the allocation of the first portion of the RAM capacity to the first computing host and the allocation of the second portion of the RAM capacity to the second computing host; and in response to a device power cycle or reset event: retrieve the memory usage allocation data; and restore the allocation of the first portion of the RAM capacity to the first computing host and the second portion of the RAM capacity to the second computing host to provide a persistent configuration in response to the device power cycle or reset event.

According to a second aspect of the present disclosure, there is provided a dual-port memory module method operable to receiving a module configuration request at a management port of a dual-port memory controller application specific integrated circuit (ASIC) of a dual-port memory module coupled by a first port to a first computing host and coupled by a second port to a second computing host; and allocating, in response to receiving the module configuration request, a first portion of RAM capacity to the first computing host and a second portion of the RAM capacity to the second computing host.

The method further includes receiving a module configuration and management data from a configuration management server via a management port at the dual-port memory controller ASIC, the allocation of the first portion of the RAM capacity to the first computing host and the second portion of the RAM capacity to the second computing host is based on the received module configuration and management data.

In an embodiment of the dual-port memory module method according to the second aspect as such, the plurality of memory media chips includes at least one of DRAM, SRAM, HBM, STT-MRAM, or PCM.

In an embodiment of the dual-port memory module method according to the second aspect as such, the dual-port memory controller ASIC further includes a protocol agnostic multi-lane connector operable to: couple the first interface port to the first computing host; couple the second interface port to the second computing host; and couple the management port to the configuration management server.

In an embodiment of the dual-port memory module method according to the second aspect as such, the protocol agnostic multi-lane connector includes an SF-TA-<NUM> compliant PCB connector.

In an embodiment of the dual-port memory module method according to the second aspect as such, the first computing host accesses the first portion of the RAM capacity and the second computing host accesses the second portion of the RAM capacity with memory-semantics LOAD(READ) and STORE(WRITE) commands.

In an embodiment of the dual-port memory module method according to the second aspect as such, the method further includes receiving data on a Serial and Deserializer (SerDes) port consisting of a plurality of differential memory lanes for access protocol communication.

In an embodiment of the dual-port memory module method according to the second aspect as such, the method further includes receiving a differential clock input on the first interface port and the second interface port.

In an embodiment of the dual-port memory module method according to the second aspect as such, the method further includes configuring, at the dual-port memory controller ASIC, the memory media chips for access by the first computing host and the second computing host.

In an embodiment of the dual-port memory module method according to the second aspect as such, the method further includes reading, at the dual-port memory controller ASIC, a memory media configuration from a serial presence detect device, the configuration of the memory media chips is based on the memory media configuration. In an eleventh embodiment of the dual-port memory module method according to the second aspect as such, the memory media configuration includes at least one of a memory media type, a memory media capacity, a memory media speed, or a number of memory media chips.

In an embodiment of the dual-port memory module method according to the second aspect as such, the method further includes storing memory usage allocation data that indicates the allocation of the first portion of the RAM capacity to the first computing host and the allocation of the second portion of the RAM capacity to the second computing host; and in response to a device power cycle or reset event: retrieving the memory usage allocation data; and restoring the allocation of the first portion of the RAM capacity to the first computing host and the second portion of the RAM capacity to the second computing host to provide a persistent configuration in response to the device power cycle or reset event.

Any one of the foregoing examples may be combined with any one or more of the other foregoing examples to create a new embodiment in accordance with the present disclosure.

In the following description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments which may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments, and it is to be understood that other embodiments may be utilized, and that structural, logical, mechanical, and electrical changes may be made. The following description of example embodiments is, therefore, not to be taken in a limited sense.

The functions or algorithms described herein may be implemented in software in an embodiment. The software may comprise computer-executable instructions stored on computer-readable media or computer-readable storage device such as one or more non-transitory memories or other type of hardware-based storage devices, either local or networked. Further, such functions correspond to modules, which may be software, hardware, firmware, or any combination thereof. Multiple functions may be performed in one or more modules as desired, and the embodiments described are merely examples. The software may be executed on a digital signal processor, application-specific integrated circuit (ASIC), a microprocessor, or other type of processor operating on a computer system, such as a personal computer, server or other computer system, turning such computer system into a specifically programmed machine.

Machine-readable non-transitory media, such as computer-readable non-transitory media, includes all types of computer readable media, including magnetic storage media, optical storage media, and solid state storage media and specifically excludes signals. The software can be installed in and sold with the devices that handle memory allocation as taught herein. Alternatively, the software can be obtained and loaded into such devices, including obtaining the software via a disc medium or from any manner of network or distribution system, including, for example, from a server owned by the software creator or from a server not owned but used by the software creator. The software can be stored on a server for distribution over the Internet, for example.

As used herein, the term "memory module" refers to a printed circuit board assembly (PCBA) with memory control integrated circuits and memory media chips are mounted on a printed circuit board (PCB). A dual in-line memory module (DIMM) has separate contacts on each side of the PCB. Memory modules may have a <NUM>-bit data path, a <NUM>-bit data path or use another data path size. Different memory modules may have different numbers of pins (e.g., <NUM> pins, <NUM> pins, <NUM> pins, <NUM> pins, or <NUM> pins) and operate at different voltages (e.g., <NUM> V, <NUM> V, <NUM> V, <NUM> V, <NUM> V, or <NUM> V).

A host computer reads data from a memory module by providing an address to read from and a read command signal on input pins of the memory module. The memory module responds by providing the read data on output pins of the memory module. The host computer writes data to a memory module by providing an address to write to and a data value on input pins of the memory module. In case of a differential DIMM with a SerDes interface to the host, the access command and data are encapsulated into a packet transferred over the SerDes interface.

A dual-channel memory module operates as two independent channels for accessing memory. Each channel has its own set of input and output pins. Additionally, the memory chips on the dual-channel memory module are divided between the two channels physically. Thus, data written using one channel cannot be read using the other channel. Nor can the distribution of the memory between the channels be altered after manufacturing.

As described herein, a dual-port memory module provides two sets of input and output pins, but the memory capacity of the dual-port memory module is divided between the ports by a dual-port memory controller ASIC. Accordingly, the allocation of the memory capacity of the memory module to each port can be changed after manufacturing. By comparison with dual-channel memory modules, dual-port memory modules provide greater flexibility, allowing more efficient use of computing resources and enabling composable memory for composable computing. The term "multi-port memory module" encompasses memory modules with more than one port (e.g., the two ports of a dual-port memory module, three ports of a tri-port memory module, four ports of a quad-port memory module, and so on).

As used herein, the term "memory media chip" refers to the byte-addressable memory integrated circuits of a memory module for data storage. Memory media chip includes DRAM, storage class memory (SCM), magnetic RAM (MRAM), spin-transfer torque MRAM (STT-MRAM), among others. DRAM includes single data rate (SDR) DRAM, double data rate (DDR) DRAM, and synchronous DRAM (SDRAM), among others.

Signaling to and from a memory module may be provided using differential signaling or single-ended signaling. With single-ended signaling, a single pin is used to transmit each signal. The voltage of each pin is compared to the ground voltage to determine if the signal is a zero or a one. For example, if the voltage on the pin is at least a threshold above the ground voltage, the signal is a logical one and if the voltage does not meet the threshold, the signal is a logical zero. With differential signaling, two pins are used to transmit each signal. The voltage of one pin is compared to the other to determine if the signal is a zero or a one. For example, if the two pins are within a threshold voltage of each other, the signal is a logical zero and if the difference exceeds the threshold, the signal is a logical one.

As used herein, the term "communication lane" refers to a pair of data transfer connections, one for input and one for output. With differential signaling, each communication lane of a memory module uses four pins, two for the input differential signal and two for the output differential signal.

One way to increase the data transfer rate of memory modules is to increase the number of communication lanes, allowing more data to be sent or received in parallel on each clock cycle. However, reducing the size of pins increases cross-talk and increasing the number of pins without reducing their size increases the size of the memory module, neither of which is desirable.

Another way to increase the data transfer rate of memory modules is to increase the operating clock frequency, allowing more data to be transferred per lane per second. The clock frequency for communication between the computing host and the memory module can be increased by a factor and the number of lanes divided by the same factor, keeping the data transfer rate the same while reducing the number of pins on the memory module. A SerDes is implemented on each side of the connection to convert data signals between wide data (e.g., <NUM> lanes) at a lower frequency (e.g., <NUM>) and narrow data (e.g., <NUM> lanes) at a higher frequency (e.g., <NUM>). Thus, the data from multiple lanes (eight, in this example) is "serialized" and output sequentially onto one lane. On the other side of the connection, sequentially received data is "deserialized" and output in parallel on multiple lanes (also eight, in this example). More complex coding schemes, such as 8B/10B, 64B/65B or 128B/129B than signal multiplexing, may be used in some embodiments.

<FIG> illustrates an example of DRAM DIMM system <NUM>. The system <NUM> includes a DRAM DIMM <NUM> which includes a register clock driver (RCD) <NUM> and number of DRAM devices <NUM>, such as eighteen or thirty-six DRAM devices for error correction code (ECC) DIMM. A DRAM DIMM <NUM> may be attached to a DIMM socket <NUM>, such as to connect the DRAM DIMM <NUM> to a host (a central processing unit (CPU) or a SoC or a DRAM controller). A DRAM DIMM <NUM> uses single-port single-ended high-speed signals for attachment toa host. DRAM data rates have been evolving from <NUM> megatransfers per second (MT/s) in DDR1 in <NUM> to <NUM> MT/s DDR5 defined by JEDEC in <NUM>.

<FIG> illustrate example DIMM configurations <NUM>. The DIMM configurations <NUM> include unregistered DIMM (UDIMM) <NUM>, where the command, address, data, and clock signals of DRAM chips <NUM> are connected to a host directly without being registered or regenerated. The DIMM configurations <NUM> include a registered DIMM (RDIMM) <NUM>, where the command and address signals between the host and DRAM chips <NUM> are buffered with registers and the clock signal is regenerated with a phase locked loop (PLL), but the data signals are not buffered and connected to the host directly. The DIMM configurations <NUM> include a load-reduced DIMM (LRDIMM) <NUM>, where the command, address and data signals between the Host and DRAM chips <NUM> are buffered with registers, and the clock signal is regenerated with a PLL.

<FIG> illustrate an example dual-channel DDR5 DIMM <NUM> defined by JEDEC DRAM standard committee. The dual-channel DIMM <NUM> includes a generalized dual-channel DIMM <NUM>, which includes an independent communication channel A <NUM> and another independent communication channel B <NUM>. The dual-channel DIMM <NUM> includes an RDIMM <NUM>, which includes an independent RDIMM communication channel A <NUM> and another independent RDIMM communication channel B <NUM>. The dual-channel DIMM <NUM> includes an LRDIMM <NUM>, which includes an independent LRDIMM communication channel A <NUM> and another independent LRDIMM communication channel B <NUM>.

<FIG> illustrate an example double data rate (DDR) throughput comparison <NUM>. The DDR throughput comparison <NUM> includes a DDR comparison table <NUM>, which compares features of various types of DDR memory. As shown in the table, a <NUM>-pin DDR4 DIMM includes UDIMM, RDIMM, and LRDIMM, uses one <NUM>+<NUM> bits channel per DIMM for data rate up to 3200MT/s. A <NUM>-pin DDR5 DIMM includes RDIMM and LRDIMM, but splits into two independent <NUM>+<NUM> bits channels for data rate up to 6400MT/s. The data transfer rate for these DDR4 and DDR5 SDRAM DIMMs with a host may be increased by using a differential Serializer and Deserializer (SerDes) communication interface. As shown in memory capacity improvement graph <NUM>, memory density increases as memory progresses from DDR to DDR5. As shown in memory interface improvement graph <NUM>, transfer rates increase as memory progresses from DDR to DDR5.

<FIG> illustrates a differential DIMM <NUM> such as the one specified and implemented by OpenPower. The differential DIMM <NUM> includes a differential DIMM controller ASIC <NUM> that receives command, address, data, and clock signals from a host CPU via a SerDes interface <NUM> on a host interface connector <NUM> to a host computer. The differential DIMM controller <NUM> receives host memory access commands from the SerDes interface and provides memory access to DRAM chips <NUM>. The differential DIMM <NUM> may use differential SerDes to provide increased speed between the CPU and DIMM <NUM>. A DIMM form factor may include a <NUM> X8 differential open memory interface (OMI) DDIMM, which may include an <NUM>-pin connector that uses <NUM> differential pairs for 8x25G SerDes and leaves <NUM> pins (e.g., <NUM> differential pairs) for other functions.

<FIG> illustrate example connectors <NUM> for differential DIMMs and related information. The connector <NUM> is based on Storage Networking Industry Association (SNIA) protocols, such the SNIA small form factor (SFF) technology affiliate (TA) <NUM> protocol. A SNIA-SFF-TA-<NUM> table <NUM> shows the features of various connector configurations. The connectors may include various connector configurations, such as vertical connectors <NUM>, right-angle connectors <NUM>, or edge connectors <NUM>. A SNIA-SFF-TA-<NUM> ecosystem <NUM> shows the relationships between the SFF form factors <NUM>, differential memory <NUM>, and the Gen-Z form factors <NUM>.

<FIG> illustrates an example DIMM evolution <NUM>. The DIMM progression <NUM> includes a Joint Electron Device Engineering Council (JEDEC) DDR4 DIMM <NUM>, which provides a <NUM>-bit channel with single-ended parallel signaling, providing throughput of up to 3200MT/s. The JEDEC DDR4 DIMM <NUM> is followed by a JEDEC DDR5 DIMM <NUM>, which provides dual <NUM>-bit channels with single-ended parallel signaling, providing up to 6400MT/s. The JEDEC DDR5 DIMM <NUM> may be followed by a JEDEC-proposed DDR5 DIMM <NUM>, which provides dual <NUM>-bit channels with differential SerDes signaling, providing greater than <NUM> gigatransfers per second (GT/s). As used herein, "high-speed differential signaling" is used to refer to signaling providing 25GT/s or greater An alternate path for the DIMM progression <NUM> follows the JEDEC DDR4 DIMM <NUM> with an OMI DIMM <NUM> defined by OpenPower with differential SerDes signaling, which may also provide greater than 25GT/s. This OMI DIMM <NUM> may use eight 25Gbps SerDes channels to interface with a host. The DIMM progression <NUM> includes a next generation (NG) DIMM <NUM>, which may provide a throughput of 112GT/s or greater, and it is expected that the disclosed dual-port memory module would be one of the NG DIMM form-factors to enable composable memory for composable computing.

<FIG> illustrates an example composable infrastructure architecture <NUM> in which the disclosure may be used a building block to enable composable memory. The composable infrastructure architecture <NUM> includes a pool of multiple compute devices <NUM>, <NUM>, and <NUM>, which connect through an interconnector fabric <NUM> to various resource pools, such as a memory pool <NUM>, a storage pool <NUM>, or an accelerator pool <NUM>. Resources within the various resource pools <NUM>, <NUM> and <NUM> may be allocated to a compute device in the compute pool on demand under composer server software control to form application-optimized servers thus enable composable computing. Because added access latency for the storage pool <NUM> and the accelerator pool <NUM> are comparable with CPU instruction execution time (e.g., nanoseconds), the interconnector fabric <NUM> may provide sufficient access speeds for the storage pool <NUM> and the accelerator pool <NUM>. In previous configurations, a cache or memory local to a CPU had to be large enough to offset fabric-added latency. The composable infrastructure architecture <NUM> provides improved performance with CPUs with large capacity on-package HBM memory as described in <FIG> and <FIG> such that the memory pool <NUM> does not need to reside on each of the multiple compute devices <NUM>, <NUM>, and <NUM>. To further reduce the interconnect latency, a dedicated interconnect fabric may be used between the compute pool and the memory pool <NUM>.

<FIG> illustrate an example of currently doable (or feasible) composable server architecture <NUM> on the right compared to the current mainstream server design <NUM> on the left. The current mainstream server architecture <NUM> includes memory, storage, and accelerators attached to a CPU <NUM>'s corresponding DDR4/DDR5 memory and PCIe interfaces locally. The composable server architecture <NUM> includes a Compute pool <NUM>, Storage pool <NUM> and Accelerator pool <NUM> interconnected with Fabric <NUM>. In contrast with the CPU-directly-attached server design <NUM>, the Compute pool <NUM> in the composable server architecture <NUM> is connected via an interconnector fabric <NUM> to a storage pool <NUM> and an accelerator pool <NUM>. The composable server architecture <NUM> provides a fabric-related latency that is relatively small compared to access time required by the storage pool <NUM> or the accelerator pool <NUM>. In various embodiments, the interconnector fabric <NUM> may be remote direct memory access (RDMA) over Converged Ethernet (RoCE) fabric on <NUM>/<NUM>/100GE, or other high speed interconnect fabric.

<FIG> illustrates an example high bandwidth memory (HBM) architecture <NUM>. The HBM architecture <NUM> includes an HBM stack <NUM>, where HBM stack <NUM> uses three-dimensional integrated circuit (3D IC) packaging to stack multiple DDR DRAM dies <NUM> vertically over a logic die layer <NUM>. The HBM stack <NUM> is connected through an interposer <NUM> to a package substrate <NUM>. The HBM stack <NUM> is also connected through the interposer <NUM> to a CPU/GPU/SoC <NUM>.

<FIG> illustrates an example HBM performance table <NUM>. The HBM performance table <NUM> provides a comparison among various HBM configurations, including HBM1, HMB2, HMB2E, and HBM3. The HBM architecture <NUM> shown in <FIG> may use HBM2E, which may provide 16GB-24GB capacity and bandwidth greater than 400GB/s per stack.

<FIG> illustrates an example HBM progression <NUM>. The HBM progression <NUM> includes a chronological progression <NUM>, which shows a progression from a baseline in <NUM> to a projected 4x with a <NUM> HBM stack projected for <NUM> from TSMC. The HBM progression <NUM> includes a performance table <NUM> for various HBM configurations. As can be seen in performance table <NUM>, a configuration with <NUM> HBM stacks on the package where each stack provides 64GB running at <NUM>. 4Gbps may provide up to 768GB and 9830TB/s. The capacity and performance provided by HBM memory co-packaged with CPU enables decoupling the DRAM DIMMs from Compute nodes, forming a memory pool interconnected with the compute nodes over an Interconnect Fabric, and then allocating the DRAM capacity to a requesting Compute node for on-demand expansion. This delivers composable memory for composable computing, which is the target application of the disclosed dual-port memory module.

<FIG> illustrates an example of envisioned Processor Module <NUM> with co-packaged HBM as system memory that may be available around the time frame of <NUM>-<NUM>. The envisioned Processor Module <NUM> includes a processor die <NUM> and a plurality co-packaged HBM stacks <NUM> and high-speed differential memory expansion channels or configurable multiprotocol ports <NUM> for memory expansion to DRAM, SCM, MRAM, or other RAM on the disclosed dual-port memory modules for composable memory. The processor module <NUM> could also include ports <NUM> for cache-coherent symmetric multiprocessing (SMP), Compute Express Link (CXL), Peripheral Component Interconnect Express (PCIe), or additional configurable multiprotocol ports. The processor module <NUM> could also include integrated ethernet interfaces <NUM>, optional dedicated PCIe ports <NUM>, and miscellaneous interfaces <NUM> (e.g., USB, Serial Peripheral Interface).

<FIG> illustrates an application example of the disclosed dual-port memory module in a cache-coherent dual-socket compute node architecture <NUM>. The cache-coherent dual-socket compute node architecture <NUM> includes a first CPU <NUM> connected to a second CPU <NUM>, which use a cache-coherence interconnect <NUM> to maintain cache coherency protocol control messages and use the dedicated SerDes interface to access the memory on the disclosed dual-port memory modules <NUM> which has one SerDes port <NUM> to each of the two CPUs. The disclosed dual-port memory module <NUM> is attached to the CPUs via connector <NUM> which could be but not limited to an SFF-TA-<NUM> compliant connector.

<FIG> illustrates an application example of two server nodes composable memory architecture <NUM> in which one or more the disclosed dual-port memory modules are shared by the two server nodes on the same PCB and the memory capacity of the disclosed dual-port memory module(s) could be allocated to either server node on-demand. The composable memory architecture <NUM> includes a first server node <NUM> connected to a second server node <NUM>. Each of the first server node <NUM> and the second server node <NUM> may include respective processors, boot ROM and management, an interface port, and a network port. The composable memory architecture <NUM> includes one or more dual-port memory expansion modules <NUM>, which may provide shared access to DRAM, SCM, MRAM, or other RAM on the port memory expansion module <NUM>. This composable memory architecture <NUM> provides a direct access path from the first server node <NUM> and the second server node <NUM> to the dual-port memory expansion module <NUM> using SerDes links <NUM> and SFF-TA-<NUM> connectors <NUM> and the memory capacity of the dual-port memory module <NUM> could be allocated to either server node on-demand to deliver composable memory capacity between server nodes via dual-port differential memory module <NUM>.

<FIG> illustrates another application example of the disclosed dual-port memory module for composable memory architecture <NUM>. The composable memory architecture <NUM> includes a compute node pool <NUM> connected through a redundant interconnect fabric <NUM> to a memory pool <NUM>. The memory pool <NUM> includes multiple disclosed dual-port memory modules <NUM> aggregated with two Interconnect ASICs <NUM> and installed on a dual-port memory board <NUM>. In one application scenario, each of the dual-port memory modules <NUM> includes two high-speed SerDes-based redundant access ports connected to one or two compute nodes within the compute node pool <NUM> once at a time via the two Interconnect ASICs and the memory capacity of dual-port memory module <NUM> is allocated to the compute nodes connected to one of its two ports, which provides access to part or all of the memory with each of the dual-port memory modules <NUM>. In another application scenario, all of the disclosed dual-port memory modules <NUM> in the memory pool <NUM> are shared by all or some of the compute nodes in the compute pool <NUM> with two redundant access paths. This composable memory architecture <NUM> provides memory capacity composability, expansion and sharing, which improves memory access performance enhancement. The details of the composable memory architecture <NUM> is out of the scope of this disclosure.

<FIG> illustrates an example of the disclosed dual-port differential memory module <NUM> in which embodiments of the disclosure may be implemented. The disclosed dual-port memory module <NUM> consists of a dual-port memory controller ASIC <NUM>, a plurality of memory media chips <NUM> connected to the controller ASIC <NUM> over the N-Channel memory interface <NUM>, a SPD attached and accessed by controller ASIC <NUM>, as well as other components such as power circuits, clock distribution circuits, and a PCB <NUM> on which all the devices are mounted on. In an embodiment, the PCB <NUM> also implements an SNIA-SFF-TA-<NUM> compliant PCB connector for the host and management interfaces. In an embodiment, the dual-port differential memory module <NUM> includes a first data access port <NUM> and a second data access port <NUM>, which may be used to provide data access for up to two hosts directly. The first data access port <NUM> and the second data access port <NUM> each consists of one or multiple SerDes lanes, such as using two, four, eight, or more SerDes lanes. In an embodiment, each of the first data access port <NUM> and the second data access port <NUM> has a differential clock input. The first data access port <NUM> and the second data access port <NUM> are connected to the Port <NUM> and Port <NUM> of the dual-port memory controller ASIC <NUM> respectively.

The dual-port differential memory module <NUM> includes a lower speed management port <NUM> for communications with a management or composer server for module initialization, configuration, monitoring, memory capacity allocation and address mapping management, but the detailed management command and message formats are out of the scope of this disclosure. The management port <NUM> is connected to the management port of the dual-port memory controller ASIC <NUM>. The management port <NUM> may communicate using a server message block (SMB) protocol, an Inter-Integrated Circuit (I2C/I3C) protocol, a Controller Area Network (CAN) bus protocol, an Ethernet protocol or other networking protocols. The management port <NUM> may be used to configure part or all of the memory within the dual-port differential memory module <NUM> to be accessible to hosts via either the first data access port <NUM> or the second data access port <NUM>. This configurations of memory capacity allocation and address mapping between the address present on the ports and the address of the memory chips may be persistent across a power cycle or reset event of the dual-port differential memory module <NUM>, such as by storing and retrieving the memory capacity allocation and address mapping configurations.

The first data access port <NUM> and the second data access port <NUM> is implemented on a common dual-port memory controller application specific integrated circuit (ASIC) <NUM>. The dual-port memory controller ASIC <NUM> may include a memory media chip interface <NUM> consisting of N memory media interface channels <NUM> for connection to a plurality of memory media chips <NUM>. The value of N could be any positive integer but is typically <NUM> or <NUM> to support ECC memory module just as DDR4 and DDR5 DIMMs. The memory media chip interface <NUM> could be single-ended JEDEC DDR4, DDR5, or any other future single-ended or differential memory media chip interface.

The dual-port memory controller ASIC <NUM> may perform necessary memory initiation and configuration operations according to the populated memory chips <NUM> without requiring intervention from any host. In an embodiment, the configuration operations include configuring based on memory configuration information, which may include populated memory media chip type, capacity, configuration, speed, and the number of the memory chips populated on each memory interface channel. The dual-port memory controller ASIC <NUM> may retrieve memory configuration information from an on-module, such as a serial presence detect (SPD) device. These configuration operations may prepare the dual-port differential memory module <NUM> ready to be accessed by a host over either of the first data access port <NUM> or the second data access port <NUM> if the memory capacity has been allocated to and the data access port is enabled by the management or composer server over module's management interface. The dual-port memory controller ASIC <NUM> allocates the requested amount of memory capacity to the first data access port <NUM> and the second data access port <NUM> and sets the proper address mapping between the data access port memory address and the address of the memory media chips <NUM> according to the instructions it receives from the management or composer server over the management port. The dual-port memory controller ASIC <NUM> also enables or disables the first data access port <NUM> or the second data access port <NUM> according to the instructions it receives from the management or composer server over the management port, and once disabled the corresponding data access port will not respond to any host request received. A host accesses the dual-port memory module's memory capacity with memory-semantic LOAD(READ) and STORE(WRITE) memory access commands through the first data access port <NUM> or the second data access port <NUM> to which it is connected to. The communication protocol over which the hosts' memory access commands are transported could be CXL, Gen-Z, OpenCAPI, PCIe, or emerging memory-semantic protocols.

In an embodiment, the form-factor, electrical interface, and data access protocol of the dual-port differential memory module <NUM> are selected to be memory media agnostic. This memory agnostic architecture enables various types of memory to be used (e.g., DRAM, SCM, MRAM/STT-MRAM) for the memory chips <NUM>.

<FIG> is a flow diagram of features of an embodiment of an example method <NUM> of a dual-port memory module (e.g., the dual-channel DIMM <NUM> of <FIG>). In operation <NUM>, upon a power-on or reset event, the dual-port memory controller ASIC initializes and configures the dual-port memory module based on the module and memory media chip information read from the SPD. In operation <NUM>, the dual-port memory controller ASIC determines if the module memory capacity has been allocated to the data access port(s), and the corresponding data access port(s) is enabled from previously saved configurations in SPD or other persistent memory locations inside or outside the dual-port memory controller ASIC.

In operation <NUM>, if the data access port (i.e., host) has not been allocated memory capacity and enabled, then the dual-port memory controller waits for and receives commands from the management or composer server over the management interface and allocates memory capacity to and enable one or more data access ports.

In operation <NUM>, once one or more data access ports are configured and enabled, the dual-port memory controller ASIC will service the requests from one or more hosts received over the data access ports. In operation <NUM>, the dual-port memory controller ASIC determines whether the request received from the host includes a read request or a write request.

Responsive to determining the request includes a read request, in operation <NUM>, the dual-port memory controller ASIC services the host read request by reading the data from the designated memory location of the memory media chips and returning the read data to the requesting host over the data access port to which the requesting host is connected. Subsequently, method <NUM> includes returning to operation <NUM> to service the next host-request. Responsive to determining the request includes a write request, in operation <NUM>, the dual-port memory controller ASIC services the host write request by writing the data from the host to the designated memory location of the memory media chips and acknowledging the requesting host the completion of the write request. Subsequently, method <NUM> includes returning to operation <NUM> to service the next host-request.

<FIG> shows an example embodiment of a computing system <NUM> for implementing embodiments of the disclosure. The computing system <NUM> can include a processor <NUM> and a memory <NUM> that communicate with each other, and with other components, via a bus <NUM>. The bus <NUM> can include any of several types of bus structures including, but not limited to, a memory bus, a memory controller, a peripheral bus, a local bus, and any combinations thereof, using any of a variety of bus architectures.

The memory <NUM> can include various components (e.g., machine-readable media such as computer-readable media) including, but not limited to, a random-access memory component, a read only component, and any combinations thereof. In an example, a Basic input/output system <NUM> (BIOS), including routines that help to transfer information between elements within computing system <NUM>, such as during start-up, can be stored in the memory <NUM>. The memory <NUM> can also include (e.g., stored on one or more machine-readable media) instructions (e.g., software) <NUM> embodying any one or more of the aspects and/or methodologies of the present disclosure. In another example, the memory <NUM> can further include any number of program modules including, but not limited to, an operating system, one or more application programs, other program modules, program data, and any combinations thereof.

The computing system <NUM> can also include a storage device <NUM>. Examples of a storage device, for example the storage device <NUM>, can include, but are not limited to, a hard disk drive, a magnetic disk drive, an optical disc drive in combination with an optical medium, a solid-state memory device, and any combinations thereof. The storage device <NUM> can be connected to the bus <NUM> by an appropriate interface (not shown). Example interfaces include, but are not limited to, SCSI, advanced technology attachment (ATA), serial ATA, universal serial bus (USB), IEEE <NUM> (FIREWIRE), and any combinations thereof. In an example, the storage device <NUM>, or one or more components thereof, can be removably interfaced with the computing system <NUM>, for example, via an external port connector (not shown). Particularly, the storage device <NUM> and an associated machine-readable medium <NUM> can provide nonvolatile and/or volatile storage of machine-readable instructions, data structures, program modules, and/or other data for the computing system <NUM>. In an example, the software <NUM> can reside, completely or partially, within the machine-readable medium <NUM>. In another example, the software <NUM> can reside, completely or partially, within the processor <NUM>.

Computing system <NUM> can also include an input device <NUM>. In one example, a user of the computing system <NUM> can enter commands and/or other information into the computing system <NUM> via the input device <NUM>. Examples of the input device <NUM> include, but are not limited to, an alpha-numeric input device (e.g., a keyboard), a pointing device, a joystick, a gamepad, an audio input device (e.g., a microphone, a voice response system, etc.), a cursor control device (e.g., a mouse), a touchpad, an optical scanner, a video capture device (e.g., a still camera, a video camera), a touchscreen, and any combinations thereof. The input device <NUM> can be interfaced to the bus <NUM> via any of a variety of interfaces (not shown) including, but not limited to, a serial interface, a parallel interface, a game port, a USB interface, a FIREWIRE interface, a direct interface to the bus <NUM>, and any combinations thereof. The input device <NUM> can include a touch screen interface that can be a part of or separate from a display <NUM>, discussed further below. The input device <NUM> can be utilized as a user selection device for selecting one or more graphical representations in a graphical interface as described above.

A user can also input commands and/or other information to the computing system <NUM> via the storage device <NUM> (e.g., a removable disk drive, a flash drive, etc.) and/or a network interface device <NUM>. A network interface device, such as the network interface device <NUM>, can be utilized for connecting the computing system <NUM> to one or more of a variety of networks, such as a network <NUM>, and one or more remote devices <NUM> connected thereto. Examples of a network interface device include, but are not limited to, a network interface card (e.g., a mobile network interface card, a LAN card), a modem, and any combination thereof. Examples of a network include, but are not limited to, a wide area network (e.g., the Internet, an enterprise network), a local area network (e.g., a network associated with an office, a building, a campus or other relatively small geographic space), a telephone network, a data network associated with a telephone/voice provider (e.g., a mobile communications provider data and/or voice network), a direct connection between two computing devices, and any combinations thereof. A network, such as the network <NUM>, can employ a wired and/or a wireless mode of communication. In general, any network topology can be used. Information (e.g., data, the software <NUM>, etc.) can be communicated to and/or from the computing system <NUM> via the network interface device <NUM>.

The computing system <NUM> can further include a video display adapter <NUM> for communicating a displayable image to a display device, such as the display <NUM>. Examples of a display device include, but are not limited to, a liquid crystal display (LCD), a cathode ray tube (CRT), a plasma display, a light emitting diode (LED) display, and any combinations thereof. The video display adapter <NUM> and the display <NUM> can be utilized in combination with the processor <NUM> to provide graphical representations of aspects of the present disclosure. In addition to a display device, the computing system <NUM> can include one or more other peripheral output devices including, but not limited to, an audio speaker, a printer, and any combinations thereof. Such peripheral output devices can be connected to the bus <NUM> via a peripheral interface <NUM>. Examples of a peripheral interface include, but are not limited to, a serial port, a USB connection, a FIREWIRE connection, a parallel connection, and any combinations thereof.

The present subject matter may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Indeed, the subject matter is intended to cover alternatives, modifications, and equivalents of these embodiments, which are included within the scope of the subject matter. Furthermore, in the detailed description of the present subject matter, numerous specific details are set forth to provide a thorough understanding of the present subject matter. However, it will be clear to those of ordinary skill in the art that the present subject matter may be practiced without such specific details.

Machine-readable storage media, such as computer-readable storage media (medium), exclude (excludes) propagated signals per se, can be accessed by a computer and/or processor(s), and include(s) volatile and nonvolatile internal and/or external media that is removable and/or non-removable. For a computer, the various types of storage media accommodate the storage of data in any suitable digital format. Other types of computer-readable medium can be employed such as zip drives, solid state drives, magnetic tape, flash memory cards, flash drives, cartridges, and the like, for storing computer-executable instructions for performing the novel methods (acts) of the disclosed architecture.

The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the disclosure. For purposes of this document, each process associated with the disclosed technology may be performed continuously and by one or more computing devices. Each step in a process may be performed by the same or different computing devices as those used in other steps, and each step need not necessarily be performed by a single computing device.

Claim 1:
A dual-port memory module device (<NUM>) operable to access computer memory, the device comprising:
a plurality of memory media chips (<NUM>) providing random access memory, RAM, capacity;
a dual-port memory controller application specific integrated circuit, ASIC (<NUM>), operable to allocate a first portion of the RAM capacity to a first computing host and a second portion of the RAM capacity to a second computing host, the dual-port memory controller ASIC (<NUM>) including:
a first interface port (<NUM>) coupled to the first computing host;
a second interface port (<NUM>) coupled to the second computing host; and
a plurality of memory interface channels (<NUM>) operable to configure, read data from, and write data to the plurality of memory media chips (<NUM>), and characterized in that
the device further comprising:
a management port (<NUM>) operable to receive module configuration and management data from a configuration management or composer server, wherein the allocation of the first portion of the RAM capacity and the second portion of the RAM capacity is based on the received module configuration and management data.