Patent Description:
Ultrasound devices may be used to perform diagnostic imaging and/or treatment, using sound waves with frequencies that are higher with respect to those audible to humans. Ultrasound imaging may be used to see internal soft tissue body structures, for example to find a source of disease or to exclude any pathology. When pulses of ultrasound are transmitted into tissue (e.g., by using an ultrasound imaging device), sound waves are reflected off the tissue, with different tissues reflecting varying degrees of sound. These reflected sound waves may then be recorded and displayed as an ultrasound image to the operator. The strength (amplitude) of the sound signal and the time it takes for the wave to travel through the body provide information used to produce the ultrasound image. Many different types of images can be formed using ultrasound devices, including real-time images. For example, images can be generated that show two-dimensional cross-sections of tissue, blood flow, motion of tissue over time, the location of blood, the presence of specific molecules, the stiffness of tissue, or the anatomy of a three-dimensional region.

<CIT> discloses a packaging structure and a packaging method for a fingerprint identification chip. The packaging structure comprises a first re-wiring layer comprising a first face and an opposite second face; a metal lead electrically connected to the first face of the first re-wiring layer; the fingerprint identification chip, wherein the front face of the fingerprint identification chipis provided with a first metal convex block, and the back face of the fingerprint identification chip is fixed on the first face of the first re-wiring layer; a packaging material layer, covering the finger print identification chip; a second re-wiring layer, wherein the second re-wiring layer, is formed on the surface of the packaging material layer, and the second re-wiring layer is electrically connected with the metal lead and the first metal convex block; and a second metal convex block, wherein the second metal convex block is formed on the second face of the first re-wiring layer. The packaging structure is capable of packaging the fingerprint identification chip by using the fan-out type, and has the characteristics of low cost, small thickness and high yield rate. The metal lead which passes through the packaging material layer is prefabricated in the packaging structure, a silicon piercing process in high cost is not needed, and the process difficulty and cost are greatly reduced.

An apparatus according to the invention is defined in claim <NUM>.

Various aspects and embodiments will be described with reference to the following exemplary and non-limiting figures. Items appearing in multiple figures are indicated by the same or a similar reference number in all the figures in which they appear.

Conventional ultrasound systems are large, complex, and expensive systems that are typically only purchased by large medical facilities with significant financial resources. Recently, cheaper, portable, and less complex ultrasound imaging devices have been introduced. Such imaging devices may include ultrasonic transducers monolithically integrated onto a single semiconductor die to form a monolithic ultrasound device. Aspects of such ultrasound-on-a chip devices are described in <CIT> (and assigned to the assignee of the instant application), which is incorporated by reference herein in its entirety.

The inventors have recognized features that may be helpful for packaging such ultrasound-on-a-chip devices compared with other packaging methods such as wirebonding. In particular, the inventors have recognized that integrated fan-out (InFO) packaging and interposer layers augmented with metal pillars may provide benefits for packaging ultrasound-on-a-chip devices. Example benefits include lower parasitic inductance and resistance, higher efficiency, less heating, higher packaging throughput, and improved packaging reliability. Additionally, such packaging may enable devices to have smaller sensor heads, which may be helpful for ultrasound imaging applications such as cardiac applications where it may be desirable for the sensor head to fit between ribs. Also, such packaging may enable devices to have thinner lenses, which may increase signal intensity.

It should be appreciated that the embodiments described herein may be implemented in any of numerous ways. Examples of specific implementations are provided below for illustrative purposes only. It should be appreciated that these embodiments and the features/capabilities provided may be used individually, all together, or in any combination of two or more, as aspects of the technology described herein are not limited in this respect.

<FIG> illustrate cross-sections of various structures during packaging of an ultrasound-on-a-chip device using one process, in accordance with certain embodiments described herein. <FIG> illustrates a release layer <NUM> coupled to a carrier substrate <NUM>, and an insulating layer <NUM> coupled to the release layer <NUM>. The carrier substrate <NUM> may include, for example, glass. The release layer <NUM> may include, for example, light-to-heat-conversion (LTHC) coating material. The insulating material <NUM> may include, for example, a polymer that can be patterned with light exposure and developed, such as polyimide, polybenzoxazole (PBO), or benzocyclobutene (BCB).

In <FIG>, a metal layer <NUM> is formed on the insulating layer <NUM>. The metal layer <NUM> may be formed, for example, using physical vapor deposition (PVD) or sputtering. The metal layer <NUM> may include, for example, copper, or in some embodiments, the metal layer <NUM> may include two layers, such as a titanium layer coupled to the insulating layer <NUM> and a copper layer coupled to the titanium layer.

In <FIG>, a resist layer <NUM> is formed on the metal layer <NUM>. For example, the resist layer <NUM> may include photoresist.

In <FIG>, openings are formed in the resist layer <NUM>. For example, light exposure through a lithography mask followed by development may create openings in portions of the resist layer <NUM> that were exposed to light through the mask.

In <FIG>, metal pillars <NUM> are formed in the openings in the resist layer <NUM> using electroplating. The metal layer <NUM> may serve as a seed layer for the electroplating. The metal pillars <NUM> may include the same material as the metal layer <NUM>, such as copper. It should be appreciated that while four metal pillars <NUM> are shown, there may be more metal pillars <NUM> (e.g., tens or hundreds) arranged two-dimensionally.

In <FIG>, the resist layer <NUM> is removed. For example, a resist stripper may be used to remove the resist layer <NUM>. Portions of the metal layer <NUM> that were previously under unexposed portions of the resist layer <NUM> are also removed. For example, an anisotropic etch may be used to remove the metal layer <NUM>, in which the metal layer <NUM> is etched faster than the metal pillars <NUM>.

<FIG> illustrates an ultrasound-on-a-chip <NUM> coupled to an insulating layer <NUM>.

In <FIG>, openings are created in the insulating layer <NUM> (e.g., using photolithography).

In <FIG>, a resist layer <NUM> is formed on the insulating layer <NUM>.

In <FIG>, openings are created in the resist layer <NUM> (e.g., using photolithography), where the openings created in the resist layer <NUM> extend into the openings created in the insulating layer <NUM>.

In <FIG>, metal contacts <NUM> are formed within the openings in the resist layer <NUM> and the insulating layer <NUM>. For example, the metal contacts <NUM> may be formed by electroplating, and may include copper or a copper alloy. In some embodiments, an under-bump metallurgy layer (not shown in <FIG>) may be formed between the metal contacts <NUM> and the ultrasound-on-a-chip <NUM>.

In <FIG>, the resist layer <NUM> is removed (e.g., using a resist stripper).

In <FIG>, further insulating material is added to the insulating layer <NUM> to cover the metal contacts <NUM>.

In <FIG>, a die-attach film (DAF) <NUM> is coupled to the insulating layer <NUM>.

In <FIG>, the ultrasound-on-a-chip <NUM> is coupled to the die-attached film <NUM>.

In <FIG>, encapsulation <NUM> is formed to encapsulate the ultrasound-on-a-chip <NUM>, the insulating layer <NUM>, the die-attach film <NUM>, and the metal pillars <NUM>. The encapsulation <NUM> may include a molding compound, a molding underfill, an epoxy, or a resin. The top surface of the encapsulation <NUM> extends above the top surfaces of the insulating layer <NUM> and the metal pillars <NUM>.

In <FIG>, the top surfaces of the encapsulating <NUM> and the insulating layer <NUM> are planarized until the top surfaces of the top surfaces of the metal pillars <NUM> and the metal contacts <NUM> are exposed. For example, chemical mechanical planarization (CMP) may be used for the planarization.

In <FIG>, additional insulating material is added to the insulating layer <NUM>, such that the insulating layer <NUM> covers the top surfaces of the metal contacts <NUM> and the metal pillars <NUM>.

In <FIG>, openings are created in the insulating layer <NUM> above the metal contacts <NUM> and the metal pillars <NUM>. For example, photolithography may be used to create the openings.

In <FIG>, redistribution lines (RDL) <NUM> are formed in the openings in the insulating layer <NUM> and on the insulating layer <NUM>. As shown, the RDL <NUM> may electrically connect certain of the metal contacts <NUM> to certain of the metal pillars <NUM>. The RDL <NUM> may include metal traces and vias, may be formed using electroplating (including formation of a seed layer not shown), and may include metal such as aluminum, copper, tungsten, and/or alloys of these metals. The RDL <NUM> may include multiple layers of metal traces and vias.

In <FIG>, additional insulating material is added to the insulating layer <NUM> to cover the top surface of the RDL <NUM>.

In <FIG>, the carrier substrate <NUM> and the release layer <NUM> are detached from the insulating layer <NUM>. For example, projecting light (e.g., ultraviolet or laser) onto the release layer <NUM> may decompose the release layer <NUM>, causing the release layer <NUM> and the carrier substrate <NUM> to detach from the insulating layer <NUM>. The surface of the insulating layer <NUM> may also be cleaned to remove any residue. The structure of <FIG> is flipped over to arrive at the orientation of <FIG>.

In <FIG>, openings are created in the insulating layer <NUM>.

In <FIG>, solder balls <NUM> are placed in the openings in the insulating layer <NUM>. In some embodiments, the solder balls <NUM> may be formed by electroplating. In some embodiments, other forms of electrical connectors (e.g., metal pillars) may be formed in the openings. In some embodiments, an under-bump metallurgy layer (not shown in <FIG>) may be formed between the solder balls <NUM> and the metal pillars <NUM>.

<FIG> illustrates a release layer <NUM> coupled to a carrier substrate <NUM>, an insulating layer <NUM> coupled to the release layer <NUM>, and an interposer layer <NUM> coupled to the insulating layer <NUM>. The interposer layer <NUM> may include, for example, aluminum nitride.

In <FIG>, openings are formed in the interposer layer <NUM>. For example, laser drilling may be used to form the openings.

In <FIG>, a metal layer <NUM> is formed on the interposer layer <NUM>. The metal layer <NUM> may be formed, for example, using sputtering. The metal layer <NUM> may include, for example, copper, or in some embodiments, the metal layer <NUM> may include two layers, such as a titanium layer coupled to the interposer layer <NUM> and a copper layer coupled to the titanium layer.

In <FIG>, metal pillars <NUM> are formed in the openings in the resist layer <NUM> using electroplating. The metal layer <NUM> may serve as a seed layer for the electroplating. The metal pillars <NUM> may include the same material as the metal layer <NUM>, such as copper. It should be appreciated that in addition to serving as electrical routing, the metal pillars <NUM> may also help to strengthen the interposer layer <NUM>, which may be brittle.

In <FIG>, a resist layer <NUM> is formed on the metal layer <NUM> and the metal pillars <NUM>.

In <FIG>, the resist layer <NUM> is patterned (e.g., using photolithography) to block the top surfaces of the metal pillars <NUM>.

In <FIG>, non-blocked portions of the metal layer <NUM> are etched to electrically isolate the metal pillars <NUM>. In some embodiments, instead of or in addition to using photolithography to block the metal pillars <NUM>, a timed etch or an anisotropic etch may be used.

In <FIG>, the resist layer <NUM> is removed (e.g., using resist stripper).

In <FIG>, the carrier substrate <NUM> and the release layer <NUM> are detached from the insulating layer <NUM>.

In <FIG>, openings are created in the insulating later <NUM>.

In <FIG>, solder balls <NUM> are placed in the openings in the insulating layer <NUM>.

In <FIG>, a thermal adhesive layer <NUM> is coupled to the interposer layer <NUM>. In some embodiments, the thermal adhesive layer <NUM> may include a silver-containing epoxy. The solder balls <NUM> are coupled to a printer circuit board (PCB) <NUM>. In some embodiments, surface-mount technology (SMT) or flip-chip soldering may be used to couple the solder balls <NUM> to the PCB <NUM>. An underfill (e.g., epoxy) layer <NUM> is formed between the insulating layer <NUM> and the PCB <NUM>.

In <FIG>, the solder balls <NUM> are coupled to the metal pillars <NUM>. The metal pillars <NUM> are aligned with the metal pillars <NUM>. In some embodiments, surface-mount technology (SMT) or flip-chip soldering may be used to couple the solder balls <NUM> to the metal pillars <NUM>. In the final structure, the interposer may provide electrical routing between the ultrasound-on-a-chip <NUM> and the PCB <NUM>, as well as a heatsink for the ultrasound-on-a-chip <NUM>.

<FIG> illustrate cross-sections of various structures during packaging of an ultrasound-on-a-chip device using another process, in accordance with certain embodiments described herein. <FIG> illustrates the structure of <FIG>.

In <FIG>, the metal pillars <NUM> are extended upwards using electroplating. As can be seen, the metal pillars <NUM> extend beyond the top surface of the interposer layer <NUM>.

In <FIG>, the ultrasound-on-a-chip <NUM> is coupled to the interposer layer <NUM> through the die-attach film <NUM>.

In <FIG>, further insulating material is added to the insulating layer <NUM>. The encapsulation <NUM> is formed to encapsulate the ultrasound-on-a-chip <NUM>, the insulating layer <NUM>, the die-attach film <NUM>, and the metal pillars <NUM>, similar to in <FIG>. The RDL <NUM> is formed, similar to in <FIG>.

In <FIG>, the carrier substrate <NUM> and the release layer <NUM> are detached from the insulating layer <NUM>, the solder balls <NUM> are formed on the metal pillars <NUM>, the solder balls <NUM> are coupled to the PCB <NUM>, and an underfill layer <NUM> is formed between the insulating layer <NUM> and the PCB <NUM>, similar to in <FIG>.

Compared with the process of <FIG>, the process of <FIG> may enable the ultrasound-on-a-chip <NUM> to be bound to the interposer layer <NUM> in a semiconductor foundry, where process control, quality, and yield may be high. Additionally, while the process of <FIG> may require simultaneous bonding of the solder balls <NUM> to the metal pillars <NUM> and bonding of the insulating layer <NUM> to the thermal adhesive <NUM>, the process of <FIG> may eliminate the thermal adhesive layer <NUM>.

<FIG> illustrates an example process <NUM> for packaging an ultrasound-on-a-chip, in accordance with certain embodiments described herein. In act <NUM>, an interposer layer containing metal pillars is coupled to a printed circuit board. Act <NUM> may correspond to the step illustrated in <FIG>. In act <NUM>, the interposer layer is coupled to a packaged ultrasound-on-a-chip containing metal pillars. Act <NUM> may correspond to the step illustrated in <FIG>. The interposer layer may be coupled to the packaged ultrasound-on-a-chip through a thermal adhesive layer.

<FIG> illustrates an example process <NUM> for packaging an ultrasound-on-a-chip, in accordance with certain embodiments described herein. In act <NUM>, metal pillars are formed in an interposer layer. Act <NUM> may correspond to the steps illustrated in <FIG>. In act <NUM>, the interposer layer is coupled to an ultrasound-on-a-chip. Act <NUM> may correspond to the step illustrated in <FIG>. In act <NUM>, a redistribution layer is formed on the packaged ultrasound-on-a-chip. Act <NUM> may correspond to the step illustrated in <FIG>.

Various aspects of the present disclosure may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

As used herein, reference to a numerical value being between two endpoints should be understood to encompass the situation in which the numerical value can assume either of the endpoints. For example, stating that a characteristic has a value between A and B, or between approximately A and B, should be understood to mean that the indicated range is inclusive of the endpoints A and B unless otherwise noted.

The terms "approximately" and "about" may be used to mean within ±<NUM>% of a target value in some embodiments, within ±<NUM>% of a target value in some embodiments, within ±<NUM>% of a target value in some embodiments, and yet within ±<NUM>% of a target value in some embodiments. The terms "approximately" and "about" may include the target value.

Claim 1:
An apparatus comprising:
an ultrasound-on-a-chip(<NUM>) comprising a top surface and a bottom surface;
an interposer layer (<NUM>) comprising a top surface and a bottom surface; and
a redistribution layer;
wherein:
the top surface of the ultrasound-on-a-chip device is coupled to the redistribution layer;
the bottom surface of the ultrasound-on-a chip device is coupled to the top surface of the interposer layer; and
the interposer layer provides a heatsink for the ultrasound-on-a-chip.