Patent Description:
While programming a nonvolatile semiconductor memory cell array, e.g., a stacked-gate memory cell in which each memory cell has a floating gate and a control gate, in order to "inject" electrons onto the floating gate, accelerated electrons traveling in a depletion region must collide with impurities or lattice imperfections in the substrate to generate momentum in a direction toward the floating gate. Further, only those electrons having sufficient velocity in the direction of the floating gate to overcome the energy barrier at the silicon-oxide interface (i.e., substrate-gate oxide interface) plus the potential change across the floating gate oxide will be injected onto the floating gate. As a result, only a small percentage of electrons (e.g., on the order of one in one million) from the programming current in the depletion region will have sufficient energy to be injected onto the floating gate.

In addition, programming electrons often experience an electric field in the depletion region that is unfavorable in the direction of the floating gate. The electric field accelerates the electrons in various directions away from the floating gate. As a result, only a small percentage of electrons from the programming current will have sufficient energy to overcome the unfavorable electric field and be injected onto the floating gate.

<CIT> discloses an array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.

Accordingly, there is a need to improve the programming efficiency of nonvolatile memory cells, such as NOR memory cells. Such methods and devices optionally complement or replace conventional methods and devices for programming, erasing, and reading data in nonvolatile memory cells. Such methods and devices improve the programming efficiency of nonvolatile memory cells by disposing a first portion of a vertically-oriented floating gate inside a trench in the substrate, which puts the floating gate in the path of the electron current during programming. Having a portion of the floating gate disposed in the path of the programming current allows electrons to be accelerated in the direction of the path in which they are already traveling, which thereby causes more electrons (e.g., a large proportion of the electrons in the programming current) to have proper momentum orientation (sometimes referred to herein as "sufficient energy") to be injected onto the floating gate.

Such methods and devices further improve the programming efficiency of nonvolatile memory cells by disposing a second portion of a vertically-oriented floating gate outside of the trench and adjacent to an insulation layer that is wide enough to sustain, without dielectric breakdown in the substrate, a favorable electric field in the direction of the floating gate, attracting electrons in the programming current to the surface of the substrate, thereby further keeping the electrons on a trajectory that leads to the floating gate, which further causes more electrons (e.g., a large proportion of the electrons in the programming current) to have sufficient energy for injection onto the floating gate.

In accordance with some embodiments, an electrically erasable programmable nonvolatile memory cell, sometimes called a NOR memory cell, includes a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, the trench region having a bottom portion and a sidewall portion adjacent a trench in the semiconductor substrate. The memory cell further includes a channel region between the first substrate region and the bottom portion of the trench region, the channel region having a first channel portion adjacent to the first substrate region, a second channel portion adjacent to the first channel portion and the trench region, and a third channel portion adjacent to the second channel portion and including the sidewall portion of the trench region. For the purposes of this disclosure, "channel region" and "channel portion" are used to describe an area or a path through which electrons flow in certain circumstances. The memory cell further includes an electrically conductive control gate insulated from and disposed over the first channel portion but not over the second and third channel portion, and an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region. The floating gate includes a first floating gate portion disposed inside the trench, and a second floating gate portion longer than the first floating gate portion, disposed above the trench and extending away from the trench. The second floating gate portion is electrically connected to the first floating gate portion on a first end and has a tip on a second end. Optionally, a first portion of the tip has a smaller cross section than a second portion of the tip. The memory cell further includes an insulation region disposed over the second channel portion between the control gate and the second floating gate portion, and an electrically conductive source line electrically connected to the trench region, the source line extending away from the substrate (e.g., away from the bottom of the trench) and forming a first capacitive coupling with the floating gate. The memory cell further includes a dielectric layer between the floating gate and the source line, and an electrically conductive erase gate insulated from and disposed over the tip of the second floating gate portion.

For a better understanding of the various described embodiments, reference should be made to the Description of Embodiments below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the figures.

It will also be understood that, although the terms first, second, etc. are, in some instances, used herein to describe various elements, these elements should not be limited by these terms. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, without departing from the scope of the various described embodiments. The first contact and the second contact are both contacts, but they are not the same contact, unless the context clearly indicates otherwise.

The terminology used in the description of the various described embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various described embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the term "if" is, optionally, construed to mean "when," or "upon," or "in response to determining," or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" is, optionally, construed to mean "upon determining," or "in accordance with a determination that," or "in response to determining" or "upon detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]," depending on the context.

Attention is now directed toward embodiments of an electrically erasable programmable nonvolatile memory cell, sometimes called a NOR memory cell or split-gate NOR memory cell, in accordance with some embodiments. <FIG> is a cross section of a pair of memory cells <NUM>, <NUM>. The memory cells mirror each other, with a memory cell formed on each side of, and including, a shared source line <NUM>. In the interest of brevity, the remainder of this disclosure references only one memory cell, memory cell <NUM>. However, it is appreciated that neighboring memory cell <NUM> has corresponding features and behaves similarly under similar circumstances. Additionally, cutouts <NUM> and <NUM> in <FIG> are illustrated in <FIG> and <FIG>, respectively, for clarity. Features shared through <FIG> are similarly numbered, and some are not further discussed for purposes of brevity.

In some embodiments, memory cell <NUM> includes a semiconductor substrate <NUM> having a first substrate region <NUM> (sometimes called a drain region) and a trench region <NUM>. In some embodiments, the first substrate region <NUM> serves as a drain, although it is appreciated that the source and drain of a transistor can be switched during operation. Furthermore, in some embodiments, the drain includes substrate region <NUM> as well as substrate region <NUM>, where region <NUM> is a shallower doped region (e.g., a moderately N-doped region in a P doped substrate) than region <NUM>. Trench region <NUM> of substrate <NUM> comprises a bottom portion, adjacent to trench bottom <NUM>, and a sidewall portion, adjacent to trench sidewall <NUM>. Memory cell <NUM> further includes a channel region comprising a first channel portion <NUM>, a second channel portion <NUM>, and a third channel portion <NUM>. In some embodiments, first channel portion <NUM> is disposed adjacent to drain region <NUM>. In some embodiments, second channel portion <NUM> is disposed between the first channel portion <NUM> and the sidewall portion of trench region <NUM> (adjacent to trench sidewall <NUM>). In some embodiments, third channel portion <NUM> is disposed adjacent to second channel portion <NUM> and comprises the sidewall portion of trench region <NUM> (adjacent to trench sidewall <NUM>) and a portion of the bottom portion of trench region <NUM> (adjacent to a portion of trench bottom <NUM>). Substrate <NUM> further includes a horizontal surface <NUM>, disposed over the drain region <NUM> and extending in a lateral direction towards the sidewall portion of trench region <NUM>. In some embodiments, at least a portion of surface <NUM> is a silicon-oxide interface (e.g., between a silicon substrate and an oxide-based insulation region). For the purposes of this disclosure, the term "trench" describes a region from which substrate material has been removed, and thus an absence of substrate material, while the terms "trench region," "bottom portion," and "sidewall portion" describe regions of the substrate adjacent to a trench.

In some embodiments, memory cell <NUM> further includes an electrically conductive control gate <NUM> insulated from and disposed over at least a portion of the first channel portion <NUM>, an electrically conductive floating gate <NUM> insulated from the bottom portion (adjacent trench bottom <NUM>) and sidewall portion (adjacent trench sidewall <NUM>) of trench region <NUM>, and an insulation region <NUM> (sometimes referred to as a gate separation insulation region, or an oxide layer) disposed over at least a portion of the second channel portion <NUM> between control gate <NUM> and floating gate <NUM>.

It is noted that while control gate <NUM> is disposed over first channel portion <NUM>, control gate <NUM> is not disposed over second channel portion <NUM> and third channel portion <NUM>. As a result, when an inversion layer is formed in a portion of first channel portion <NUM> underneath a portion of control gate <NUM> due to an appropriate read mode control voltage or programming mode control voltage being applied to control gate <NUM>, at least a portion of second channel portion <NUM> does not include an inversion layer. In other words, while the inversion layer in first channel portion <NUM> may, in some circumstances or in some embodiments, extend partially into second channel portion <NUM>, that inversion layer does not extend into other portions of second channel portion <NUM>. In some embodiments, second channel portion <NUM> has a lateral dimension, corresponding to the distance between first channel portion <NUM> and third channel portion <NUM>. In some embodiments, for devices implemented in deep submicron technology nodes, the distance between first and third channel portions <NUM> and <NUM> is between <NUM> and <NUM> nanometers.

In some embodiments, floating gate <NUM> includes a first floating gate portion <NUM> disposed inside the trench, and a second floating gate portion <NUM> disposed above the trench and extending away from the trench. In some embodiments, second floating gate portion <NUM> is longer than first floating gate portion <NUM>. In some embodiments, second floating gate portion <NUM> has a first end <NUM> at which second floating gate portion <NUM> is electrically connected to first floating gate portion <NUM>. In some embodiments, second floating gate portion <NUM> has a second end <NUM> including a tip (see <FIG>) with a first tip portion <NUM> and a second tip portion <NUM>. In some embodiments, the first tip portion <NUM> has a smaller cross section than the second tip portion <NUM>. Second end <NUM> is sometimes herein called a pointed tip, and the ratio of the cross section of first tip portion <NUM> to the cross section of second tip portion <NUM> is sometimes used as a measure of the sharpness of the pointed tip.

In some embodiments, the memory cell <NUM> further includes an electrically conductive source line <NUM> electrically connected to the bottom portion of trench region <NUM> through trench bottom <NUM>. Source line <NUM> extends away from the substrate. In some embodiments, source line <NUM> includes a first source line portion <NUM> disposed at least partially inside the trench and electrically connected to the bottom portion of trench region <NUM>, and a second source line portion <NUM> disposed above the first source line portion <NUM>. In some embodiments, at least a portion of second source line portion <NUM> is disposed outside the trench. In some embodiments, first source line portion <NUM> is relatively lightly doped (e.g., n- polysilicon), and the second source line portion <NUM> is more heavily doped (e.g., n+ polysilicon). In some embodiments, first source line portion <NUM> is lightly doped polysilicon that has been converted into single crystal silicon.

In some embodiments, memory cell <NUM> further includes a dielectric layer <NUM> between at least a portion of the floating gate <NUM> and at least a portion of the source line <NUM>. In some embodiments, dielectric layer <NUM> is a "thin" dielectric layer, so as to provide a strong capacitive coupling between floating gate <NUM> and source line <NUM>. In some embodiments, dielectric layer <NUM> comprises a combination of oxide and nitride, or other high dielectric constant material. In some embodiments, dielectric layer <NUM> has a combined total thickness between <NUM> and <NUM>.

In some embodiments, memory cell <NUM> further includes an insulation layer <NUM> between at least a portion of the floating gate <NUM> and at least a portion of trench sidewall <NUM>. In some embodiments, insulation layer <NUM> comprises a combination of oxide and nitride, or other high dielectric constant material. In some embodiments, compared with a conventional silicon oxide layer, insulation layer <NUM> provides a lower interface energy barrier (sometimes called an energy barrier height) for hot electrons to overcome in order to be injected into the floating gate <NUM>. In some embodiments, the low interface energy barrier provided by the dielectric material of insulation layer <NUM> is less than <NUM> eV (electron volts), and in some embodiments is less than <NUM> eV, or less than <NUM> eV.

In some embodiments, memory cell <NUM> further includes an electrically conductive erase gate <NUM> insulated from and disposed over the top of the second floating gate portion <NUM>. Erase gate <NUM> is insulated from the second floating gate portion <NUM> by an insulation layer <NUM>, sometimes called an erase gate insulation region, disposed between the erase gate and the second floating gate portion. In some embodiments, erase gate <NUM> is further disposed over at least a portion of the source line <NUM>. In some embodiments, the capacitive coupling between floating gate <NUM> and erase gate <NUM> is much weaker than the capacitive coupling between floating gate <NUM> and source line <NUM>, which is beneficial for efficiently and quickly erasing the memory cell (explained in more detail below). In some embodiments, the capacitive coupling between the floating gate and the source line is greater than the capacitive coupling between the floating gate and the erase gate by a ratio of at least <NUM> to <NUM> (i.e., the capacitive coupling ratio is at least <NUM> to <NUM>), and in some embodiments the capacitive coupling ratio, of the capacitive coupling between the floating gate and the source line to the capacitive coupling between the floating gate and the erase gate, is at least <NUM> to <NUM>, or <NUM> to <NUM>, or <NUM> to <NUM>. The strong capacitive coupling between the floating gate and the source line (compared to the capacitive coupling between the floating gate and the erase gate) is caused by the proximity of the floating gate to the source line, as well as the large surface area of the vertical face of the floating gate that is in close proximity to the source line.

In some embodiments, similar capacitive coupling ratios exist for the floating gate and the source line versus the floating gate and the control gate. More specifically, in some embodiments, the capacitive coupling between the floating gate and the source line is greater than the capacitive coupling between the floating gate and the control gate by a ratio of at least <NUM> to <NUM> (i.e., the capacitive coupling ratio is at least <NUM> to <NUM>), and in some embodiments the capacitive coupling ratio, of the floating gate - source line capacitive coupling to the floating gate - control gate capacitive coupling, is at least <NUM> to <NUM>, or <NUM> to <NUM>, or <NUM> to <NUM>.

In some embodiments, conductive elements of the memory cell <NUM> (e.g., control gate <NUM>, floating gate <NUM>, source line <NUM>, and/or erase gate <NUM>) are constructed of appropriately doped polysilicon. It is appreciated that "polysilicon" refers to any appropriate conductive material, formed at least in part from silicon or metal material, that can be used to form the conductive elements of nonvolatile memory cells. In addition, in accordance with some embodiments, insulation elements of the memory cell <NUM> (e.g., insulation regions <NUM> and <NUM>) are constructed of silicon dioxide, silicon nitride, and/or any appropriate insulator that can be used to form the insulation elements of nonvolatile memory cells.

Attention is now drawn to the channel portions of memory cell <NUM>, as illustrated in <FIG>. In some embodiments, first and second channel portions <NUM> and <NUM> form a continuous channel region extending from drain region <NUM> to the sidewall portion of trench region <NUM>, in the lateral direction. Additionally, first and second channel portions <NUM> and <NUM> extend in the vertical direction to include substrate surface <NUM>. In some embodiments, first and second channel portions <NUM> and <NUM> are adjacent to each other or overlap with each other, and in some embodiments, the first channel portion <NUM> overlaps with the drain region <NUM>. In some embodiments, third channel portion <NUM> extends from the substrate surface <NUM> to the bottom portion of trench region <NUM> (adjacent to a portion of trench bottom <NUM>), and is adjacent the sidewall portion of trench region <NUM> (adjacent to trench sidewall <NUM>). In some embodiments, third channel portion <NUM> is adjacent to or overlaps with second channel portion <NUM>, forming a continuous channel region from drain region <NUM> to the portion of trench region <NUM> that is adjacent the trench bottom <NUM> and underneath source line <NUM> (see channel portion <NUM> in <FIG>). In some embodiments, the continuous channel region formed by portions <NUM>, <NUM>, and <NUM> is non-coplanar, as the sidewall portion of channel portion <NUM> (adjacent to trench sidewall <NUM>) extends substantially perpendicular to the lateral direction in which channel portions <NUM> and <NUM> extend, and the bottom portion of channel portion <NUM> (adjacent to trench bottom <NUM>) extends substantially perpendicular to the direction of the sidewall portion of channel portion <NUM>. In some embodiments, "substantially perpendicular" means an angle within a range of <NUM> to <NUM> degrees.

Operation of the memory cell <NUM> in accordance with some embodiments will now be described. <FIG> is a flow chart illustrating an operation flow <NUM> for a memory cell <NUM> in accordance with some embodiments. Operation flow <NUM> begins at step <NUM>, at which a memory controller proceeds to either erase memory cell <NUM> (e.g., while erasing a row of memory cells including memory cell <NUM>) (step <NUM>), program a memory cell <NUM> that has previously been erased (step <NUM>), or read from a memory cell <NUM> that has previously been programmed or erased (step <NUM>). In some embodiments, operation flow <NUM> includes concurrent erase and program operations on different memory cells, and in some embodiments, operation flow <NUM> includes concurrent erase and read operations on different memory cells.

To erase a row of memory cells including a memory cell <NUM> (step <NUM>) in accordance with some embodiments, a first bias potential (e.g., ground potential) is applied to both the control gate <NUM> and the source line <NUM>, and a second bias potential (e.g., a positive potential) is applied to the erase gate <NUM>. Typically, a difference between the second bias potential and the first bias potential is no greater than <NUM> volts. Since the floating gate <NUM> is highly capacitively coupled to the source line <NUM>, the floating gate potential is pulled down to, or held at, a potential just above the ground potential, also herein simply called "ground" or "circuit ground. " As a nonlimiting example, for a capacitance ratio of <NUM>/<NUM> (i.e., the floating gate to source line capacitance is ten times the floating gate to erase gate capacitance), if the erase gate potential changes from 0V to 10V (e.g., to start an erase operation) and the source line potential is maintained at 0V, the 10V change in potential in the erase gate causes a change in the floating gate potential of less than 1V.

The difference in potentials between the floating gate and erase gate causes electrons to leave the floating gate. More specifically, electrons on the floating gate <NUM> are induced through the Fowler-Nordheim tunneling mechanism (or equivalents thereof) to tunnel from the upper portion <NUM> of the floating gate (e.g., primarily from pointed tip <NUM>), through the insulation layer <NUM>, and onto the erase gate <NUM>, leaving the floating gate <NUM> positively charged. Tunneling of electrons through insulation layer <NUM>, from tip <NUM> of floating gate <NUM> to erase gate <NUM>, is enhanced by the sharpness of tip <NUM>. While traditional memory cells may have required 14V or higher for erasing, currently disclosed embodiments require application of no greater than 10V to erase gate <NUM> (e.g., the voltage applied to erase gate <NUM>, relative to the voltage applied to control gate <NUM> and source line <NUM>, is no greater than +10V), and even less (e.g., 8V) in some embodiments. In addition to the capacitance ratio, the pointed tip <NUM> of the floating gate <NUM> also contributes to the lower erase voltage. In particular, the pointed tip <NUM> of floating gate <NUM> facilitates the formation of a tightly focused electric field between floating gate <NUM> and erase gate <NUM>, which in turn facilitates electron tunneling through insulation layer <NUM>, thereby allowing the use of lower erase voltages for any given thickness of insulation layer <NUM>. For example, if a planar floating gate without a pointed tip normally requires an insulation thickness (layer <NUM>) of less than <NUM> angstroms, having a pointed tip <NUM> allows the insulation thickness to be up to <NUM> angstroms and still permit tunneling when only 10V is applied to the erase gate.

For programming the memory cell (step <NUM>) in accordance with some embodiments, attention is first directed to <FIG>, which illustrates another view (190a) of cutout <NUM> from <FIG> during a programming operation. Features shared with <FIG> are similarly numbered, and some are not further discussed for purposes of brevity. Additional features depicted in <FIG> include a weak inversion layer <NUM>, electric field lines 310a-d emanating from a portion of the floating gate disposed above the trench, electric field lines 310e-h emanating from a portion of the floating gate disposed inside the trench, a first depletion region <NUM>, a second depletion region <NUM>, a trench inversion layer <NUM>, and a direction of electron flow <NUM>. As is known in the art, electrons are attracted to positive voltage potentials, and are therefore pulled in directions opposite to the field line directions depicted in the figure.

To program the memory cell in accordance with some embodiments, the first bias potential (e.g., ground potential) is applied to the erase gate <NUM>, and a fifth bias potential (e.g., a low voltage such as 0V, or a voltage between 0V and <NUM> V) is applied to drain region <NUM>/<NUM>. A positive voltage level in the vicinity of the threshold voltage of the MOS structure (e.g., on the order of <NUM> to <NUM>. 7V above the voltage potential of the drain region) is applied to control gate <NUM>. The voltages applied to drain region <NUM>/<NUM> and control gate <NUM> form a first depletion region <NUM> around the drain region <NUM>/<NUM> and channel portion <NUM> (<FIG>) of substrate <NUM>. Further, a sixth bias potential higher than the fifth bias potential is applied to the control gate <NUM>, and a seventh bias potential (e.g., a positive high voltage, for example on the order of 4V to 6V), higher than the sixth bias potential is applied to the source line <NUM>.

The sixth bias potential applied to control gate <NUM> causes a weak inversion layer <NUM> to form in the substrate <NUM>, connected to drain region <NUM>/<NUM> and having a pinch off point <NUM> located underneath control gate <NUM>. Inversion layer <NUM> has a voltage close to that of drain region <NUM>/<NUM>, as the very low sub-threshold current between the drain region and the pinch off point <NUM> causes only a very small voltage drop between the drain region and the pinch off point <NUM>.

Applying the seventh bias potential (as noted above, a positive high voltage, e.g., on the order of 4V to 6V) to source line <NUM> causes a voltage of the floating gate <NUM> to rise in accordance with the seventh bias potential due to capacitive coupling between the source line and the floating gate, thereby causing electrons in a channel region of the substrate to gain energy and to be injected onto the floating gate. Because floating gate <NUM> is highly capacitively coupled to the source line <NUM>, the voltage transition, e.g., from 0V to 4V, on source line <NUM> causes the voltage of floating gate <NUM> to increase proportionately to the voltage increase on source line <NUM>. For example, in some embodiments, the voltage of the floating gate increases by at least <NUM> percent of the change in voltage on source line <NUM>. The positive charges on floating gate <NUM> (e.g., due to floating gate <NUM> having previously been erased, plus the increase in voltage due to capacitive coupling with source line <NUM>) in conjunction with the high voltage on source line <NUM> forms a second depletion region <NUM> (sometimes referred to herein as a deep depletion region) around the trench region <NUM> of substrate <NUM>. Deep depletion region <NUM> has a larger depletion width than depletion region <NUM> due to the relatively higher voltage on source line <NUM>. The larger depletion region <NUM> pushes pinch off point <NUM> toward the drain region <NUM>/<NUM>, causing inversion layer <NUM> to be pinched off underneath control gate <NUM>. The positive charges on floating gate <NUM> (e.g., due to floating gate <NUM> having previously been erased) further forms an inversion layer <NUM> surrounding the trench (channel portion <NUM>, <FIG>). Inversion layer <NUM> has a voltage close to that of the source line, which is substantially higher than the voltage of inversion layer <NUM> (having a voltage close to that of the drain region). This difference in voltages between inversion layers <NUM> and <NUM> causes a voltage drop between inversion layer <NUM> and inversion layer <NUM>. The voltage drop occurs in depletion region <NUM>, and the resulting electric field due to the voltage drop is represented by field line <NUM> (in channel region <NUM>, <FIG>).

The voltage on floating gate <NUM> is influenced by the positive charges on floating gate <NUM> (e.g., due to a previous erase operation), as well as the high voltage applied to source line <NUM> (due to the capacitive coupling between the floating gate and the source line). Accordingly, the voltage on floating gate <NUM> is substantially higher than the voltage on control gate <NUM>, resulting in an electric field between the two, represented by field lines 310a-h in <FIG>. In some embodiments, insulation region <NUM> is wide enough in the lateral direction that the distance between control gate <NUM> and floating gate <NUM> causes portions of the electric field between control gate <NUM> and floating gate <NUM>, represented by field lines 310c-d in <FIG>, to be directed towards the substrate surface <NUM>. Specifically, for some portions of the floating gate <NUM> (e.g., portions that are closer to the surface <NUM> than the control gate <NUM>), the adjacent electric field is directed downward towards the surface <NUM> due to the close proximity of charges in second channel portion <NUM> to floating gate <NUM>.

At the beginning of a programming operation, a stream of electrons (sometimes called the programming current) from drain region <NUM>/<NUM> flows through inversion layer <NUM>, moving randomly but having a net drift velocity in the direction represented by electron flow <NUM>. The electrons traverse inversion layer <NUM> and proceed to pinch off point <NUM>. The insulation region <NUM> disposed over the second channel portion <NUM>, a control gate potential, and a source line potential are configured during a program operation to enable electrons to travel underneath a horizontal surface of the substrate (e.g., the horizontal surface of the substrate <NUM> separating insulation region <NUM> from second channel portion <NUM>) in the lateral direction in the second channel portion <NUM>.

After leaving pinch off point <NUM>, electrons in the programming current are accelerated through depletion region <NUM> (channel portion <NUM>, <FIG>) in the direction of electron flow <NUM> by the electric field represented by field lines 310c-f and <NUM>. The accelerated electrons are referred to herein as hot electrons. The hot electrons traveling in electron flow <NUM> through depletion region <NUM> are influenced by an electric field favorable to a substantially lateral trajectory perpendicular to the trench sidewall <NUM> and located just below substrate surface <NUM> (referred to herein as a "head-on" trajectory, since electrons in the electron flow <NUM> collide with the sidewall <NUM> head on). Stated another way, the electric field represented by field line <NUM> attracts hot electrons in the programming current toward floating gate <NUM>, while the electric field represented by field lines 310c-d prevents, or substantially reduces the portion of, hot electrons in the programming current from flowing downward into substrate <NUM>, keeping the hot electrons on a head-on trajectory close to surface <NUM>.

As the hot electrons in the programming current travel through depletion region <NUM> toward trench sidewall <NUM>, some of those electrons with sufficient energy proceed to break through the substrate surface at sidewall <NUM> and enter insulation layer <NUM>, located between floating gate <NUM> and trench sidewall <NUM>. In some embodiments, an electron has sufficient energy to enter insulation layer <NUM> when its energy is higher than the energy barrier height at the interface between the silicon of substrate <NUM> and the dielectric material of insulation layer <NUM>. After breaking into insulation layer <NUM>, electrons are attracted by the electric field represented by field line 310e and injected onto floating gate <NUM>.

Unlike prior art programming mechanisms, electrons in depletion region <NUM> do not require scattering to create a momentum component in the direction of floating gate <NUM>. In fact, scattering is undesirable since it causes electrons in electron flow <NUM> to lose energy and change direction, which reduces the likelihood they will have sufficient energy to enter insulation layer <NUM> and be injected onto floating gate <NUM>. Thus, in the programming mechanism of presently disclosed embodiments, electrons leaving inversion layer <NUM> (in channel region <NUM>) are accelerated through depletion region <NUM> (in channel region <NUM>). The electrons traveling in a head-on trajectory toward floating gate <NUM> with sufficient breakthrough energy to enter insulation layer <NUM> are ultimately injected onto floating gate <NUM>. Even electrons in electron flow <NUM> that are scattered upward (toward surface <NUM>), sideways, or slightly downward (away from surface <NUM>) will still be injected onto floating gate <NUM> as long as they have sufficient energy to overcome the interface energy barrier. This head-on injection mechanism results in an increased proportion of electrons with sufficient breakthrough energy, which results in increased programming efficiency. Such improved program efficiency results in almost all of the high energy electrons in electron flow <NUM> being injected onto floating gate <NUM>.

The injection of electrons onto floating gate <NUM>, sometimes herein called the gate current, continues until either the programming voltages on source region <NUM> and control gate <NUM> are removed, or the voltage on floating gate <NUM> is so reduced by the electrons injected onto floating gate <NUM> that electrons in electron flow <NUM> no longer have sufficient energy to traverse insulation layer <NUM>. Stated another way, the reduced voltage of the floating gate no longer sustains the generation of hot electrons. At this point, a "programmed state" for the floating gate is reached. In some embodiments, the gate current during programming is in the range of 10nA to 100nA, and in some embodiments, the programmed state is reached in 10ns to 100ns.

Finally, to read a selected memory cell (step <NUM>) in accordance with some embodiments, the first bias potential (e.g., a ground potential) is applied to the source line <NUM>. A fourth bias potential (e.g., a read voltage (e.g., <NUM> to 3V)) is applied to the drain region <NUM>, and a third bias potential, sometimes called the read potential (e.g., a positive voltage (e.g., approximately <NUM> to 3V, depending upon the power supply voltage of the device supported by the given technology node)) is applied to the control gate <NUM>.

If the floating gate <NUM> is positively charged (i.e., the floating gate is discharged of electrons, for example because the memory cell <NUM> has been erased and not subsequently programmed), then the third channel portion <NUM> is turned on by the formation of an inversion layer <NUM>. When the control gate <NUM> is raised to the read potential, the first channel portion <NUM> is turned on by the formation of a strong inversion layer <NUM> in the substrate region below the control gate. In the second channel portion, the two depletion regions overlap with an electric field below the substrate surface <NUM> pointing from drain region <NUM>/<NUM> toward floating gate <NUM>. As a result, the entire channel region, including channel portions <NUM>, <NUM>, and <NUM>, favor an electron current in the direction of drain region <NUM>/<NUM>. Accordingly, electrons flow from source line <NUM> (through the trench region <NUM> of the substrate, adjacent source line <NUM>) to the drain region <NUM>/<NUM> through inversion layer <NUM> in channel portion <NUM>, depletion region <NUM> in channel portion <NUM>, and inversion layer <NUM> in channel portion <NUM>. When the resulting electrical current (sometimes called the read current) is sensed, using circuitry in the memory device not shown, the memory cell is sensed to be in the "<NUM>" state or, equivalently, the "erased" state.

On the other hand, if the floating gate <NUM> is negatively charged, then no inversion layer forms in trench region <NUM> of the substrate. Consequently, the third channel portion <NUM> is either weakly turned on or entirely shut off and the width of depletion region <NUM> is reduced compared to the width of depletion region <NUM> when the floating gate <NUM> is positively charged (e.g., as a result of an erase operation). Further, the decreased width of depletion region <NUM> causes the depletion regions <NUM> and <NUM> to no longer overlap. Due to the gap in depletion regions, at least a portion of second channel portion <NUM> is not in a depletion region. As a result, even when control gate <NUM> and the drain region <NUM> are raised to the read potential, little or no current (sometimes called the read current) flows between source line <NUM> and drain region <NUM>. In this case, either the read current is very small compared to that of the "<NUM>" state, or there is no read current at all. In this manner, the memory cell is sensed to be in the "<NUM>" state or, equivalently, in the "programmed" state.

In some embodiments, a ground potential is applied to the drain regions <NUM>, source regions <NUM>, and control gates <NUM> for non-selected columns and rows so that only the selected memory cell(s) is (are) read.

Attention is now directed to <FIG>, which illustrates a plan view of a memory cell array <NUM> in accordance with some embodiments. In some embodiments, bit lines <NUM> interconnect with drain regions <NUM>. Control lines <NUM> and nitride masks <NUM> (removed in the manufacturing process) define the source lines, floating gates, and control gates, and extend across both the active regions <NUM> and the isolation regions <NUM>. The source lines <NUM> electrically connect to the source regions for each row of paired memory cells. The floating gates are disposed in trenches in the active regions <NUM> underneath the erase lines <NUM>.

Attention is now directed to <FIG>, which illustrate a process for manufacturing a memory cell in accordance with some embodiments. A process in accordance with some embodiments begins in <FIG>, which shows a cross-section view of silicon substrate <NUM> and an oxide layer <NUM>, above which nitride <NUM> is deposited. A number of isolation trenches have already been removed from substrate <NUM>, and the right hand portion of <FIG> shows a region, with oxide layer <NUM>, that has been prepared for memory cell formation. <FIG> is another cross-section view, orthogonal to the cross-section view of <FIG>, along the bit-line direction (see <FIG>). Next, as illustrated in <FIG>, the nitride layer <NUM> is etched, leaving a nitride mask with portions <NUM> and <NUM>.

Next, as illustrated in <FIG>, a trench is etched through the oxide and silicon layers, between nitride mask portions <NUM> and <NUM>. In some embodiments, the etching is performed by reactive ion etching ("RIE"). After the etching, a dielectric material <NUM> (e.g., high temperature oxide, referred to as "HTO") is deposited above the oxide layer, and doped polysilicon is deposited above the HTO. The polysilicon (sometimes herein called "poly") is etched using RIE in order to produce two separate floating gates <NUM> and <NUM>. Next, as illustrated in <FIG>, after the processing steps of floating gate separation masking and etching, leftover poly is also isotropically etched from areas <NUM> and <NUM>. Next, as illustrated in <FIG>, a dielectric layer is deposited and then anisotropically etched using RIE, forming coupling dielectric regions <NUM> and <NUM>. The oxide at areas <NUM>, <NUM>, and <NUM> is etched away after such processing steps.

Next, as illustrated in <FIG>, to form a source line <NUM> (see <FIG>) in accordance with some embodiments, lightly doped amorphous silicon <NUM> is first deposited and then converted into single crystal silicon using a solid phase epitaxy ("SPE") process. An N-type dopant (e.g., arsenic or phosphorus) is then implanted and thermally driven in to form a heavily doped N+ layer <NUM> above the lightly doped silicon in the trench. An isotropic poly etch is then performed to remove the excess silicon outside the trench as shown in <FIG> to form the top of the source line <NUM>. In other embodiments, processing steps in <FIG> are accomplished as follows: layers <NUM> and <NUM> are formed by first performing an epitaxial silicon growth step to selectively grow the N- single crystal silicon <NUM> at the trench bottom, followed by the deposition of heavily doped polysilicon <NUM>. The excess polysilicon <NUM> outside the trench is isotropically etched away to form the top of the source line <NUM>. As can be seen from the description of how source line <NUM> is formed, source line <NUM> and floating gate <NUM>, are self-aligned due to the use of floating gates <NUM>, <NUM> and coupling dielectric regions <NUM> and <NUM> to define the vertical boundaries of source line <NUM>.

Next, as illustrated in <FIG>, a controlled amount of oxide is etched from the top and sides of the nitride mask portions <NUM> and <NUM>, along with the exposed oxide covering the tip portions <NUM>, <NUM> of the floating gates <NUM>, <NUM>. Then, a thin oxide layer <NUM> is thermally grown so as to protect the floating gate tips <NUM>, <NUM> and the top of the source line silicon. This thermal oxide layer <NUM> growing step also sharpens the tips <NUM>, <NUM> of the floating gates <NUM>, <NUM>.

Next, as illustrated in <FIG>, the oxide layer <NUM> (see <FIG>) is etched using RIE. During the etch, nitride masks <NUM>, <NUM> and another mask (not shown) protect floating gate tips <NUM>, <NUM> and source line <NUM>. Oxide regions 504a and 504b remain after the etch. In some embodiments, the RIE etch conditions are adjusted in order to minimize damage caused to the silicon <NUM>. Next, as illustrated in <FIG>, a thin oxide layer <NUM> is grown above the silicon surface <NUM> in order to remediate damage to the silicon surface caused by the RIE process for etching oxide layer <NUM>. In some embodiments, the oxidation also further sharpens the tips of the floating gates. Next, the nitride is stripped off of top of oxide regions 504a and 504b. Next, as illustrated in <FIG>, HTO <NUM> is deposited over the memory cell area in order to serve as a tunneling dielectric. In some embodiments, a thickness of the HTO is <NUM>-<NUM> angstroms. In other embodiments, a thickness of the HTO is up to <NUM> angstroms. In some embodiments, a mask is used to protect the floating gate tips, while HTO <NUM> is isotropically etched to remove excess oxide, for example along the sidewalls of oxide regions 504a, 504b. In some embodiments, oxide is anisotropically etched to remove oxide from areas <NUM> and <NUM> to prepare for formation of the control gates. Next, gate oxide is grown over areas <NUM> and <NUM>, and poly is deposited, covering the entire memory array area including the gate oxide in regions <NUM> and <NUM>. The poly is then masked and etched to form control gates <NUM>, <NUM>, as shown in <FIG>. In some embodiments, the same masking and etching steps used to form control gates <NUM>, <NUM> are also used to define the erase gate <NUM>, while in other embodiments erase gate <NUM> is formed using separate making and etching steps from those used to form control gates <NUM>, <NUM>.

Finally, lightly doped drain regions <NUM>, <NUM> (e.g., drain regions adjacent control gates <NUM>, <NUM>) and drain regions <NUM>, <NUM> are formed using processing steps well known in the semiconductor industry to form drain regions that include lightly doped drain (LDD) sub-regions adjacent neighboring transistor gates and more heavily doped drain sub-regions not adjacent the neighboring transistor gates, one example of which is described in <CIT>, followed by contact formation and the subsequent metallization and other steps to complete the device manufacturing.

Claim 1:
An electrically erasable programmable nonvolatile memory cell (<NUM>) comprising:
a semiconductor substrate (<NUM>) having a first substrate region (<NUM>) and a trench region (<NUM>) apart from the first substrate region in a lateral direction, the trench region comprising a bottom portion and a sidewall portion adjacent a trench in the semiconductor substrate;
a channel region between the first substrate region and the bottom portion of the trench region, the channel region having:
a first channel portion (<NUM>) adjacent to the first substrate region;
a second channel portion (<NUM>) adjacent to the first channel portion and the trench region; and
a third channel portion (<NUM>) adjacent to the second channel portion and comprising the sidewall portion of the trench region;
an electrically conductive control gate (<NUM>) insulated from and disposed over the first channel portion but not over the second and third channel portions;
an electrically conductive floating gate (<NUM>) insulated from the bottom and sidewall portions of the trench region, the floating gate having:
a first floating gate portion (<NUM>) disposed inside the trench; and
a second floating gate portion (<NUM>) longer than the first floating gate portion, disposed above the trench and extending away from the trench, the second floating gate portion being electrically connected to the first floating gate portion on a first end (<NUM>) and having a tip on a second end (<NUM>);
an insulation region (<NUM>) disposed over the second channel portion between the control gate and the second floating gate portion;
an electrically conductive source line (<NUM>) electrically connected to the trench region, the source line extending away from the substrate and forming a first capacitive coupling with the floating gate;
a dielectric layer (<NUM>) between the floating gate and the source line; and
an electrically conductive erase gate (<NUM>) insulated from and disposed over the tip of the second floating gate portion.