Patent Description:
The performance of a power supply usually gradually declines after being used for a time duration. The most common degradation behaviors include poorer efficiency, reduced hold-up time, larger voltage ripple, etc. The most important reason for the performance degradation of the power supply is often related to the aging of the capacitors in the power supply (capacitance attenuation). Generally speaking, users do not know the aging condition of the capacitors in the power supply. Users often replace the power supply only after the function of the power supply is completely lost. However, the operation of the power supply has already gone through a long period of performance degradation before the function of the power supply is completely lost, so that the user has to pay more additional energy costs. If the user may know about the current capacitor aging information of the power supply in real time, the user may use the aging information to evaluate whether to replace the power supply preventively, so as to avoid unnecessary energy waste and equipment abnormalities. <CIT> discloses a power conversion apparatus including a primary-side circuit, a bulk capacitor, a conversion circuit, and a master control circuit. The primary-side circuit is adapted to rectify and boost an alternating-current power and output primary-side output. The bulk capacitor is connected in parallel to two output ends of the primary-side output. The conversion circuit is configured to receive the primary-side output passing through the bulk capacitor and convert the primary-side output into secondary-side output. The master control circuit detects an electric power state of the alternating-current power, obtains a time interval, a power of the secondary-side output corresponding to the time interval, and two of the capacitor voltages corresponding to the start and the end of the time interval when the electric power state is power-off, and selectively outputs an abnormal signal according to the time interval, the power, the capacitor voltages, and a threshold.

The present invention is provided in the appended claims. More specifically, the invention provides calculation circuits according to claims <NUM> and <NUM>, power supplies according to claims <NUM> and <NUM>, and methods according to claims <NUM> and <NUM>.

The following disclosure serves a better understanding of the present invention. The disclosure provides a power supply, a calculation circuit, and a capacitor aging detection method thereof, so as to generate information about current capacitor aging in real time.

In an embodiment of the disclosure, the calculation circuit includes an output current detection circuit, an output voltage detection circuit, and a processor. The output current detection circuit is coupled to a power conversion circuit to detect an output current of the power conversion circuit. The output voltage detection circuit is coupled to the power conversion circuit to detect an output capacitor voltage of an output capacitor of the power conversion circuit. The processor is coupled to the output current detection circuit and the output voltage detection circuit. The processor uses the output current and the output capacitor voltage to calculate output power of the power conversion circuit. The processor uses the output capacitor voltage, the output power, and first time information to calculate the current output capacitor value of the power conversion circuit, and triggers a notification based on the current output capacitor value.

In an embodiment of the disclosure, the power supply includes the power conversion circuit and the calculation circuit. The power conversion circuit is used to convert an input voltage into an output voltage to obtain output power. The calculation circuit is coupled to the power conversion circuit to measure a capacitor voltage, output power, and time information of the power conversion circuit. The calculation circuit uses the capacitor voltage, the output power, and the time information to calculate a current capacitor value of the power conversion circuit, and triggers a notification based on the current capacitor value.

In an embodiment of the disclosure, the above-mentioned capacitor aging detection method includes the following operation. A capacitor voltage, output power, and time information of the power conversion circuit is measured. The power conversion circuit is used to convert an input voltage into an output voltage to obtain output power. The capacitor voltage, the output power, and the time information are used to calculate a current capacitor value of the power conversion circuit. A notification is triggered based on the current capacitor value.

In an embodiment of the disclosure, the calculation circuit includes an input voltage detection circuit, an output voltage detection circuit, and a processor. An input voltage detection circuit is coupled to the power conversion circuit to detect an input capacitor voltage of the power conversion circuit. An output voltage detection circuit is coupled to the power conversion circuit to detect an output capacitor voltage of the power conversion circuit. The processor is coupled to the input voltage detection circuit and the output voltage detection circuit. The processor uses the input capacitor voltage and the output capacitor voltage to calculate current hold-up time. The processor triggers a notification based on the current hold-up time.

In an embodiment of the disclosure, the power supply includes the power conversion circuit and the calculation circuit. The power conversion circuit is used to convert an input voltage into an output voltage to obtain output power. The calculation circuit is coupled to the power conversion circuit and used to measure the input capacitor voltage and the output capacitor voltage of the power conversion circuit. The calculation circuit uses the input capacitor voltage and the output capacitor voltage to calculate the current hold-up time of the power conversion circuit, and triggers a notification based on the current hold-up time.

In an embodiment of the disclosure, the capacitor aging detection method includes the following operation. An input capacitor voltage and an output capacitor voltage of the power conversion circuit is measured. The input capacitor voltage and output capacitor voltage are used to calculate a current hold-up time of the power conversion circuit. A notification is triggered based on the current hold-up time.

Based on the above, the power supply according to the embodiments of the disclosure may generate information about capacitor aging (such as the current capacitor value or the current hold-up time of the power conversion circuit) in real time. In some embodiments, the calculation circuit may notify/provide the current capacitor aging information to the system circuit outside the power supply, so the user may refer to the capacitor aging information to decide whether to replace the power supply. In other embodiments, the calculation circuit may decide whether to send a warning based on the information about the current capacitor aging (notify/provide the capacitor aging warning to the system circuit outside the power supply), thereby the system circuit notifies the user to replace the power supply. According to the invention, in each embodiment, a step down in the voltage of an input capacitor is detected to determine that power-off to a power conversion circuit occurs, and it is further detected that an input current flowing via a power switch to the input capacitor turns to zero to determine that power-off occurs due to the switch being turned off.

Therefore, users may self-assess whether to replace the power supply preventively based on the information about the current capacitor aging, so as to avoid unnecessary energy waste and equipment abnormalities.

In order to make the above-mentioned features and advantages of the disclosure comprehensible, embodiments accompanied with drawings are described in detail below.

The term "coupled (or connected)" as used throughout this specification (including the scope of the application) may refer to any direct or indirect means of connection. For example, if it is described in the specification that a first device is coupled (or connected) to a second device, it should be construed that the first device may be directly connected to the second device, or the first device may be indirectly connected to the second device through another device or some type of connecting means. Terms "first," "second" and the like mentioned in the full text (including the scope of the patent application) of the description of this application are used only to name the elements or to distinguish different embodiments or scopes and are not intended to limit the upper or lower limit of the number of the elements, nor is it intended to limit the order of the elements. In addition, wherever possible, elements/components/steps with the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numerals or use the same terminology in different embodiments may refer to relevant descriptions of each other.

<FIG> is a circuit block schematic diagram of a power supply <NUM> according to an embodiment of the disclosure. The power supply <NUM> shown in <FIG> includes a power conversion circuit <NUM> and a calculation circuit <NUM>. The power conversion circuit <NUM> may convert the input voltage VIN (input power Pin) into an output voltage to obtain an output power Po, in order to supply power to other circuits (e.g., the system circuit <NUM> shown in <FIG>). The calculation circuit <NUM> is coupled to the power conversion circuit <NUM>. The calculation circuit <NUM> may monitor the electrical characteristics of the power conversion circuit <NUM> to generate current aging information (e.g., current capacitor value and/or current hold-up time) about the capacitance of the power conversion circuit <NUM> in real time. In some embodiments, the calculation circuit <NUM> may notify/provide the information about the current capacitor aging to the system circuit <NUM> outside the power supply <NUM>, so the user may refer to the capacitor aging information to decide whether to replace the power supply <NUM>. In other embodiments, the calculation circuit <NUM> may decide whether to send a warning based on the information about the current capacitor aging (notify/provide the capacitor aging warning to the system circuit <NUM> outside the power supply <NUM>), thereby the system circuit <NUM> notifies the user to replace the power supply <NUM>. Therefore, users may self-assess whether to replace the power supply <NUM> preventively based on the information about the current capacitor aging, so as to avoid unnecessary energy waste and equipment abnormalities.

<FIG> is a schematic flowchart of a capacitor aging detection method according to an embodiment of the disclosure. Referring to <FIG>, in step S210, the calculation circuit <NUM> may measure the capacitor voltage, the output power Po, and the time information of the power conversion circuit <NUM>. The specific measurement examples of the capacitor voltage and the output power Po are described below. It should be emphasized that the specific measurement methods of the capacitor voltage and the output power Po are not limited to the following content.

<FIG> is a circuit block schematic diagram of a power conversion circuit <NUM> and a calculation circuit <NUM> according to an embodiment of the disclosure. For the power conversion circuit <NUM> and the calculation circuit <NUM> shown in <FIG>, reference may be made to the relevant descriptions of the power conversion circuit <NUM> and the calculation circuit <NUM> shown in <FIG>, so details are not repeated herein. In the embodiment shown in <FIG>, the power conversion circuit <NUM> includes an input capacitor <NUM>, a power converter <NUM>, and an output capacitor <NUM>. The input capacitor <NUM> receives the input voltage VIN through the power switch <NUM>, in which the power switch <NUM> is controlled by the processor <NUM> of the calculation circuit <NUM>. Here, the voltage of the input capacitor <NUM> is referred to as an input capacitor voltage Vein, and the voltage of the output capacitor <NUM> is referred to as an output capacitor voltage VCo. When the power switch <NUM> is turned on, the input capacitor voltage VCin of the input capacitor <NUM> is equal to the input voltage VIN. When the power switch <NUM> is turned off, the input capacitor voltage VCin steps down in response to the input voltage VIN being powered off.

<FIG> is a waveform schematic diagram of an input current IIN, an input capacitor voltage VCin, and an output capacitor voltage VCo according to an embodiment of the disclosure. The horizontal axis shown in <FIG> represents time, and the vertical axis respectively represents current (corresponding to input current IIN) and voltage (corresponding to input capacitor voltage VCin and output capacitor voltage VCo). Referring to <FIG> and <FIG>, when it is detected that the input current IIN is <NUM>, it is determined that a power-off occurs. Further, when the voltage detection circuit detects that the input voltage VIN drops to the step-down threshold, it is determined that the power-off occurs. The input current IIN (input voltage VIN) is powered off at time point t<NUM>. According to actual application scenarios, the "input current IIN (input voltage VIN) is powered off" may include that the power source (not shown) of the power supply <NUM> stops providing the input power Pin, and/or the power switch <NUM> is turned off. When the power switch <NUM> is turned off, or when the power source stops providing the input power Pin, the input capacitor voltage VCin and the output capacitor voltage VCo of the power conversion circuit <NUM> are stepped down in response to the input current IIN (input voltage VIN) being powered off, as shown in <FIG>.

The power converter <NUM> is coupled between the input capacitor VIN and the output capacitor <NUM>. The power converter <NUM> may convert the input capacitor voltage VCin into the output capacitor voltage VCo for the output capacitor <NUM>. The performance degradation of the power conversion circuit <NUM> is often related to the aging (capacitance attenuation) of the input capacitor <NUM> and/or the output capacitor <NUM>. Based on actual design and application, the capacitor voltage in step S210 includes at least one of the input capacitor voltage VCin and the output capacitor voltage VCo. Based on this, the calculation circuit <NUM> may generate capacitor aging information (such as the current capacitor value of the input capacitor <NUM> and/or the output capacitor <NUM>) in real time.

In the embodiment shown in <FIG>, the calculation circuit <NUM> includes a processor <NUM>, an input current detection circuit <NUM>, an input voltage detection circuit <NUM>, an output current detection circuit <NUM>, and an output voltage detection circuit <NUM>. The input current detection circuit <NUM> is coupled to the power conversion circuit <NUM> to detect an input current of the power conversion circuit <NUM>. The input voltage detection circuit <NUM> is coupled to the power conversion circuit <NUM> to detect an input capacitor voltage VCin of the input capacitor <NUM> of the power conversion circuit <NUM>. The output current detection circuit <NUM> is coupled to the power conversion circuit <NUM> to detect an output current of the power conversion circuit <NUM>. The output voltage detection circuit <NUM> is coupled to the power conversion circuit <NUM> to detect an output capacitor voltage VCo of the output capacitor <NUM> of the power conversion circuit <NUM>. The processor <NUM> is coupled to the input current detection circuit <NUM>, the input voltage detection circuit <NUM>, the output current detection circuit <NUM>, and the output voltage detection circuit <NUM>. Therefore, the processor <NUM> may measure the capacitor voltage (the input capacitor voltage VCin and/or the output capacitor voltage VCo) of the power conversion circuit <NUM> in step S210. In addition, the processor <NUM> may use the output current and the output capacitor voltage VCo of the power conversion circuit <NUM> to calculate the output power Po in step S210. The processor <NUM> may use the output capacitor voltage VCo, the output power Po, and the first time information to calculate the current output capacitor value of the output capacitor <NUM> of the power conversion circuit <NUM> in step S220, and/or the processor <NUM> may use the input capacitor voltage VCin, the output power Po, and the second time information to calculate the current input capacitor value of the input capacitor <NUM> of the power conversion circuit <NUM> in step S220. The processor <NUM> may trigger a notification based on the current input capacitor value and/or the current output capacitor value in step S230.

Based on actual design/application, in some embodiments, the time information in step S210 includes the time duration from time point t<NUM> to time point t<NUM> shown in <FIG>, and/or the time duration from time point t<NUM> to time point t<NUM> shown in <FIG>. The time point t<NUM> is a power-off time point when the input current IIN (input voltage VIN) of the power conversion circuit <NUM> is powered off (i.e., the input current IIN turns to <NUM> or it is determined that the input voltage VIN starts to decline), the time point t<NUM> is a step-down start time point when the output capacitor voltage VCo of the power conversion circuit <NUM> is stepped down in response to the input current IIN (input voltage VIN) being powered off, and the time point t<NUM> is a step-down threshold time point when the output capacitor voltage VCo steps down to a certain threshold level (e.g., the voltage level Vb shown in <FIG>). The voltage level Vb may be a voltage value set based on actual design. The processor <NUM> may use the capacitor voltage (input capacitor voltage VCin and output capacitor voltage VCo) to measure the time information (the time duration from time point t<NUM> to time point t<NUM> and/or the time duration from time point t<NUM> to time point t<NUM> shown in <FIG>) in step S210.

In step S220, the processor <NUM> of the calculation circuit <NUM> may use the capacitor voltage, the output power Po and the time information to calculate the current capacitor value of the power conversion circuit <NUM>. Based on actual design/application, in some embodiments, the current capacitor value includes the current input capacitor value (the capacitor value of the input capacitor <NUM> of the power conversion circuit <NUM>) and/or the current output capacitor value (the capacitor value of the output capacitor <NUM> of the power conversion circuit <NUM>). The specific calculation example of the current capacitor value is described below. It should be emphasized that, in other embodiments, the specific calculation methods of the current capacitor value are not limited to the following content.

In some embodiments, the current capacitor value includes a current input capacitor value Cin of the input capacitor <NUM> of the power conversion circuit <NUM>. The processor <NUM> may calculate Cin = <NUM>*Po*( t<NUM> - t<NUM>) / (V<NUM><NUM> - V<NUM><NUM>) in step S220, where Po is the output power of the power conversion circuit <NUM>, (t<NUM> - t<NUM>) is the time duration from time point t<NUM> to time point t<NUM> shown in <FIG>, V<NUM> is the voltage level of the input capacitor voltage VCin at time point t<NUM>, and V<NUM> is the voltage level of the input capacitor voltage VCin at time point t<NUM>.

In some embodiments, the current capacitor value includes the current output capacitor value Cout of the output capacitor <NUM> of the power conversion circuit <NUM>. The processor <NUM> may calculate Cout =<NUM>*Po*(t<NUM>- t<NUM>)/(Va<NUM>- Vb<NUM>) in step S220, where Po is the output power of the power conversion circuit <NUM>, (t<NUM> - t<NUM>) is the time duration from time point t<NUM> to time point t<NUM> shown in <FIG>, Va is the voltage level of the output capacitor voltage VCo at time point t<NUM>, and Vb is the voltage level (threshold level of the hold-up time) of the output capacitor voltage VCo at time point t<NUM>. In other embodiments, the voltage level V<NUM> may be a voltage value set based on an actual design, and the voltage level of the time point t<NUM> and the corresponding output capacitor voltage VCo are decided by stepping down the input capacitor voltage VCin to the voltage level V<NUM>, the disclosure is not limited thereto.

Referring to <FIG>, in step S230, the calculation circuit <NUM> may trigger a notification based on the current capacitor value (the current input capacitor value Cin and/or the current output capacitor value Cout). For example, in some embodiments, the processor <NUM> of the calculation circuit <NUM> may notify/transmit the current capacitor value to the system circuit <NUM> outside the power supply <NUM>. At this time, the system circuit <NUM> may present the current capacitor value in real time, so the user may refer to the current capacitor value to decide whether to replace the power supply <NUM> (or the power conversion circuit <NUM>). In some other embodiments, the processor <NUM> of the calculation circuit <NUM> may calculate the capacitance attentuation rate based on an initial capacitor value Cinitial and the current capacitor value Cnow (current input capacitor value Cin and/or current output capacitor value Cout), and notify/transmit the capacitance attenuation rate corresponding to the current output capacitor value Cout to the system circuit <NUM>, so that the user may refer to the capacitance attenuation rate to decide whether to replace the power supply <NUM> (or power conversion circuit <NUM>).

In some other embodiments, the processor <NUM> of the calculation circuit <NUM> may decide whether to issue a warning to notify the system circuit <NUM> outside the power supply <NUM> based on the current capacitor value Cnow (current input capacitor value Cin and/or current output capacitor value Cout), so that the system circuit <NUM> notifies the user to replace the power supply <NUM> (or power conversion circuit <NUM>). In yet some other embodiments, the processor <NUM> of the calculation circuit <NUM> may calculate the capacitance attenuation rate based on an initial capacitor value Cinitial and the current capacitor value Cnow (current input capacitor value Cin and/or current output capacitor value Cout), and decide whether to send a warning to the system circuit <NUM> based on the capacitance attennuation rate corresponding to the current capacitor value Cnow, so that the system circuit <NUM> notifies the user to replace the power supply <NUM> (or power conversion circuit <NUM>).

The initial capacitor value Cinitial may be decided according to actual design. For example, the processor <NUM> of the calculation circuit <NUM> may calculate the capacitance attenuation rate (Cnow/Cinitial)*<NUM>%, and store (update) the calculated current capacitor value Cnow and the capacitance attenuation rate in the non-volatile memory. The processor <NUM> of the calculation circuit <NUM> may check whether the stored capacitance attenuation rate is lower than a certain attenuation rate threshold value (e.g., <NUM>% or other values) at every boot-up. When the capacitance attenuation rate is lower than the attenuation rate threshold value, the processor <NUM> of the calculation circuit <NUM> may send a warning to the system circuit <NUM>. At this time, the system circuit <NUM> may notify the user to replace the power supply <NUM> (or the power conversion circuit <NUM>) based on the warning from the calculation circuit <NUM> in real time.

<FIG> is a schematic flowchart of a capacitor aging detection method according to another embodiment of the disclosure. Referring to <FIG> and <FIG>, in step S510, the processor <NUM> of the calculation circuit <NUM> may measure the input capacitor voltage Vein and the output capacitor voltage VCo of the power conversion circuit <NUM>. <FIG> is a waveform schematic diagram of an input current IIN, an input capacitor voltage VCin, and an output capacitor voltage VCo according to an embodiment of the disclosure. The horizontal axis shown in <FIG> represents time, and the vertical axis respectively represents current (corresponding to input current IIN) and voltage (corresponding to input capacitor voltage VCin and output capacitor voltage VCo). Referring to <FIG> and <FIG>, when it is detected that the input current IIN is <NUM>, it is determined that a power-off occurs. In other embodiments, when the voltage detection circuit detects that the input voltage VIN drops to the step-down threshold, it is determined that the power-off occurs. The input current IIN (input voltage VIN) is powered off at time point t<NUM>. When the power switch <NUM> is turned off, or when the power source (not shown) of the power supply <NUM> stops providing the input power Pin, the input capacitor voltage VCin and the output capacitor voltage VCo of the power conversion circuit <NUM> are stepped down in response to the input current IIN (input voltage VIN) being powered off, as shown in <FIG>.

In step S520, the processor <NUM> of the calculation circuit <NUM> may use the input capacitor voltage VCin and the output capacitor voltage VCo to calculate the current hold-up time of the power conversion circuit <NUM>. For example, the time point t<NUM> shown in <FIG> is a power-off time point when the input capacitor voltage VCin is stepped down in response to the input current IIN (input voltage VIN) of the power conversion circuit <NUM> being powered off, and the time point t<NUM> shown in <FIG> is a step-down threshold time point when the output capacitor voltage VCo is stepped down to a certain threshold level (e.g., the voltage level Vb shown in <FIG>) in response to the input current IIN (input voltage VIN) being powered off. The processor <NUM> may use the input capacitor voltage VCin and the output capacitor voltage VCo to measure the current hold-up time thu (the time duration from time point t<NUM> to time point t<NUM>) in step S520. For example, the processor <NUM> may calculate thu = t<NUM> - t<NUM>.

In step S530, the processor <NUM> of the calculation circuit <NUM> may trigger a notification based on the current hold-up time. For example, in some embodiments, the calculation circuit <NUM> may notify/transmit the current hold-up time to the system circuit <NUM> outside the power supply <NUM>. At this time, the system circuit <NUM> may present the current hold-up time in real time, so the user may refer to the current hold-up time to decide whether to replace the power supply <NUM> (or the power conversion circuit <NUM>).

In some other embodiments, the processor <NUM> of the calculation circuit <NUM> may decide whether to issue a warning to notify the system circuit <NUM> outside the power supply <NUM> based on the current hold-up time. For example, the processor <NUM> of the calculation circuit <NUM> may store (update) the calculated current hold-up time in the non-volatile memory. The processor <NUM> of the calculation circuit <NUM> may check whether the stored current hold-up time is lower than a certain hold-up time threshold value at every boot-up. When the current hold-up time is lower than the hold-up time threshold value, the processor <NUM> of the calculation circuit <NUM> may send a warning to the system circuit <NUM>. At this time, the system circuit <NUM> may notify the user to replace the power supply <NUM> (or the power conversion circuit <NUM>) based on the warning from the calculation circuit <NUM> in real time.

<FIG> is a schematic flowchart of a capacitor aging detection method according to yet another embodiment of the disclosure. Referring to <FIG> and <FIG>, in step S705, the processor <NUM> of the calculation circuit <NUM> may measure the input current of the power conversion circuit <NUM> and determine whether the input current is less than or equal to zero. When the input current is less than or equal to <NUM> (the determination result of step S705 is "Yes", i.e., the input voltage VIN is powered off), the processor <NUM> of the calculation circuit <NUM> may proceed to step S710 to sample the input capacitor voltage VCin, the time point t<NUM>, and the output power Po. In step S715, the processor <NUM> of the calculation circuit <NUM> may determine whether the input capacitor voltage VCin is less than or equal to the voltage level V<NUM>. When the input capacitor voltage VCin is less than or equal to the voltage level V<NUM> (the determination result of step S715 is "Yes"), the processor <NUM> of the calculation circuit <NUM> may proceed to step S720 to sample the input capacitor voltage VCin and the time point t<NUM>.

In step S725, the processor <NUM> of the calculation circuit <NUM> may sample the output capacitor voltage VCo. In step S730, the processor <NUM> of the calculation circuit <NUM> may determine whether the output capacitor voltage Vco is less than or equal to the voltage level Vb. When the output capacitor voltage Vco is less than or equal to the voltage level Vb (the determination result of step S730 is "Yes"), the processor <NUM> of the calculation circuit <NUM> may proceed to step S735 to sample the output capacitor voltage Vco and the time point t<NUM>. In step S740, the processor <NUM> of the calculation circuit <NUM> may calculate the current input capacitor Cin, the current output capacitor Cout, and the capacitance attenuation rate. In step S745, the calculation circuit <NUM> may calculate the current hold-up time.

In step S750, the processor <NUM> of the calculation circuit <NUM> may determine whether the capacitance attenuation rate is less than the attenuation rate threshold value, and/or determine whether the current hold-up time is less than the hold-up time threshold value. When the capacitance attenuation rate is not less than the attenuation rate threshold value and the current hold-up time is not less than the hold-up time threshold value (the determination result of step S750 is "No"), the processor <NUM> of the calculation circuit <NUM> may end the capacitor aging detection procedure shown in <FIG> and return to the main procedure. When the capacitance attenuation rate is less than the attenuation rate threshold value or the current hold-up time is less than the hold-up time threshold value (the determination result of step S750 is "Yes"), the processor <NUM> of the calculation circuit <NUM> may proceed to step S755 to determine that the capacitor of the power conversion circuit <NUM> has aged. In step S760, the processor <NUM> of the calculation circuit <NUM> may send a warning to notify the system circuit <NUM> outside the power supply <NUM>, and then end the capacitance aging detection procedure shown in <FIG> and return to the main procedure. At this time, the system circuit <NUM> may notify the user to replace the power supply <NUM> (or the power conversion circuit <NUM>) based on the warning from the calculation circuit <NUM> in real time.

According to different design requirements, in some embodiments, the system circuit <NUM>, the calculation circuit <NUM>, and/or the processor <NUM> may be implemented by a hardware circuit. In other embodiments, the system circuit <NUM>, the calculation circuit <NUM>, and/or the processor <NUM> may be implemented by firmware, software (i.e., a program), or a combination of the two. In some other embodiments, the system circuit <NUM>, the calculation circuit <NUM>, and/or the processor <NUM> may be implemented by a combination of hardware, firmware, and software.

In terms of hardware, the above-mentioned system circuit <NUM>, calculation circuit <NUM>, and/or processor <NUM> may be implemented as a logic circuit on an integrated circuit. For example, the above-mentioned related functions of the system circuit <NUM>, calculation circuit <NUM>, and/or processor <NUM> may be implemented in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASIC), digital signal processor (DSP), field programmable gate array (FPGA), and/or various logic blocks, modules, and circuits in other processing units. The above-mentioned related functions of the system circuit <NUM>, calculation circuit <NUM>, and/or processor <NUM> may be implemented as hardware circuits by using hardware description languages (e.g., Verilog HDL or VHDL), or other suitable programming languages, such as various logic blocks, modules, and circuits in integrated circuits.

In terms of software and/or firmware, the above-mentioned related functions of the system circuit <NUM>, calculation circuit <NUM>, and/or processor <NUM> may be implemented as programming codes. For example, the system circuit <NUM>, calculation circuit <NUM>, and/or processor <NUM> may be implemented using general programming languages (e.g., C, C++, or assembly language) or other suitable programming languages. The programming code may be recorded/stored in a "non-transitory computer readable medium". In some embodiments, the non-transitory computer readable medium includes, for example, a semiconductor memory and/or a storage device. The semiconductor memory includes a memory card, a read only memory (ROM), a flash memory, a programmable logic circuit, or other semiconductor memories. The storage device includes a tape, a disk, a hard disk drive (HDD), a solid-state drive (SSD), or other storage devices. An electronic device (e.g., a central processing unit (CPU), a controller, a microcontroller, or a microprocessor) may read and execute the programming code from the non-transitory computer readable medium, thereby achieving related functions of the system circuit <NUM>, calculation circuit <NUM>, and/or processor <NUM>.

Claim 1:
A calculation circuit (<NUM>), comprising:
an output current detection circuit (<NUM>), coupled to a power conversion circuit (<NUM>) to detect an output current of the power conversion circuit (<NUM>);
an output voltage detection circuit (<NUM>), coupled to the power conversion circuit (<NUM>) to detect an output capacitor voltage (VCo) of an output capacitor (<NUM>) of the power conversion circuit (<NUM>);
a processor (<NUM>), coupled to the output current detection circuit (<NUM>) and the output voltage detection circuit (<NUM>), calculating output power (Po) of the power conversion circuit (<NUM>) by using the output current and the output capacitor voltage (VCo), wherein the processor (<NUM>) calculates a current output capacitor value (Cout) of the power conversion circuit (<NUM>) by using the output capacitor voltage (VCo), the output power (Po), and first time information, and triggers a notification based on the current output capacitor value (Cout);
an input voltage detection circuit (<NUM>), coupled to the processor (<NUM>) and coupling to the power conversion circuit (<NUM>) to detect an input capacitor voltage (VCin) of an input capacitor (<NUM>) of the power conversion circuit (<NUM>), wherein, when the input voltage detection circuit (<NUM>) detects that the input capacitor voltage (VCin) steps down, it is determined that a power-off occurs;
characterized in further comprising
an input current detection circuit (<NUM>), coupled to the processor (<NUM>) and coupling to the power conversion circuit (<NUM>) to detect an input current (IIN) flowing through a power switch (<NUM>) of the power conversion circuit (<NUM>) to the input capacitor (<NUM>) of the power conversion circuit (<NUM>), wherein, when the input current detection circuit (<NUM>) detects that the input current (IIN) turns to <NUM>, due to the power switch (<NUM>) being turned off, it is determined that a power-off occurs.