Patent Description:
An ever-growing demand in wireless communication systems is higher efficiency to reduce operational and system costs. In a wireless communication system transmitter, the radio frequency (RF) power amplifier is one the most power consuming elements, and often the transmitter RF power amplifier has the highest impact on total power dissipated. Accordingly, amplifier and transmitter designers strive to develop RF power amplifiers with reduced power consumption and power loss, while maintaining or improving efficiency and RF bandwidth.

<NPL>, discloses the design and layout of a two stage SiGe E-band power amplifier using a stacked transformer for output power combination. The amplifier design is based in differential CE stages with capacitive cross coupling to increase the gain as well as the stability by reducing the effective differential base-collector capacitance. A low loss power combining stacked transformer with single turn inductors is also disclosed, in which the performance supersedes an alternative design with a symmetrical transformer tree. The stacked transformer is significantly easier to design at <NUM> than a two-turn <NUM>:<NUM> transformer, and has the additional advantage of providing power combination of two output stages. "<NPL>, discloses a two-stage <NUM>-GHz stacked-FET power amplifier implemented in <NUM>-nm SOI CMOS. Dual supply operation is disclosed which supports high gain, power and efficiency in the two-stage design. The amplifier exhibits greater than <NUM> dBm saturated output power with <NUM> dB peak power gain and achieves a record peak PAE of <NUM>%. The PAE remains above <NUM>% from <NUM> to <NUM>. <CIT> discloses a high frequency circuit in which the potential of a source terminal of a transistor is fixed; a load is connected to a drain terminal of the transistor; and an input signal is received by a gate terminal of the transistor. A series circuit including an inductor and a capacitor connected in series is provided between a connection point of the drain terminal of the transistor and the load and an output terminal of a high-frequency circuit. A bandpass filter having a prescribed characteristic is configured by an output equivalent circuit expressing an output impedance oftl1e transistor, the load, and the series circuit. <CIT> discloses a multiple-stage amplifier including a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die. <CIT> discloses an example of an improved tunable inter-stage matching circuit for a power amplifier module comprising a driver amplifier cascade connected to an power amplifier via the tunable inter-stage matching circuit;.

<NPL>, discloses an RF PA with a low-voltage driver having a low output impedance and being cascade connected to a high voltage output stage having a low input impedance.

An embodiment of an amplifier in accordance with claim <NUM> includes a driver stage amplifier transistor and a final stage amplifier transistor integrated in a semiconductor die. The driver stage amplifier transistor has a driver stage input, a driver stage output, and an output impedance, and the driver stage amplifier transistor is configured to operate using a first bias voltage at the driver stage output. The final stage amplifier transistor has a final stage input, a final stage output, and an input impedance, where the final stage input is electrically coupled to the driver stage output. The final stage amplifier transistor is configured to operate using a second bias voltage at the final stage output, and the second bias voltage is at least twice as large as the first bias voltage.

The driver stage amplifier transistor has an output impedance, the final stage amplifier transistor has an input impedance, and a ratio of the output impedance of the driver stage amplifier transistor to the input impedance of the final stage amplifier transistor input is less than <NUM>:<NUM>. The amplifier further includes an interstage impedance matching circuit electrically coupled between the driver stage output and the final stage input, and the interstage impedance matching circuit is configured to perform an impedance transformation from the output impedance of the driver stage amplifier transistor to the input impedance of the final stage amplifier. According to a further embodiment, the output impedance of the driver stage amplifier is less than <NUM> ohms, and the second impedance is less than <NUM> ohms. According to yet another further embodiment, the driver stage amplifier transistor is characterized by a first drain-source on resistance, and the final stage amplifier transistor is characterized by a second drain-source on resistance that is greater than the first drain-source resistance. According to yet another further embodiment, the driver stage amplifier transistor is characterized by a first breakdown voltage, and the final stage amplifier transistor is characterized by a second breakdown voltage that is at least <NUM> percent higher than the first breakdown voltage. According to yet another further embodiment, the driver stage amplifier transistor is characterized by a first power density, and the final stage amplifier transistor is characterized by a second power density that is at least <NUM> percent greater than the first power density. According to yet another further embodiment, the semiconductor die is a silicon-based die, the driver amplifier transistor is a first laterally-diffused metal oxide semiconductor (LDMOS) field effect transistor (FET), and the final stage amplifier is a second LDMOS FET. According to yet another further embodiment, the driver stage amplifier transistor has a first transistor finger that includes a first gate structure with a first sidewall, a first drain region, and a first drift region extending from the first sidewall to the first drain region, and where the driver stage amplifier transistor is characterized by a first drain-source on resistance, and the final stage amplifier transistor has a second transistor finger that includes a second gate structure with a second sidewall, a second drain region, and a second drift region extending from the second sidewall to the second drain region, where the final stage amplifier transistor is characterized by a second drain-source on resistance that is greater than the first drain-source resistance. According to yet another further embodiment, the first drift region and the second drift region have one or more different characteristics selected from different doping levels, different drift region widths, different drift region depths, and different drift region lengths. According to yet another further embodiment, the first drift region has a first length between the first sidewall and the first drain region, and the second drift region has a second length between the second sidewall and the second drain region, where the second length is at least <NUM> percent larger than the first length.

Another embodiment of an amplifier includes a driver stage field effect transistor (FET) and a final stage FET integrated in a semiconductor die. the driver stage FET has a driver stage input, a driver stage output, and an output impedance, and the driver stage amplifier transistor is characterized by a first breakdown voltage. The final stage FET has a final stage input, a final stage output, and an input impedance, and the final stage amplifier transistor is characterized by a second breakdown voltage that is at least <NUM> percent higher than the first breakdown voltage. The amplifier further includes an interstage impedance matching circuit electrically coupled between the driver stage output and the final stage input, where the interstage impedance matching circuit is configured to perform an impedance transformation from the output impedance of the driver stage amplifier transistor to the input impedance of the final stage amplifier.

According to the invention, a ratio of the output impedance to the input impedance is less than <NUM>:<NUM>. According to another further embodiment, the output impedance of the driver stage FET is less than <NUM> ohms, and the input impedance of the final stage FET is less than <NUM> ohms. According to yet another further embodiment, the driver stage FET is characterized by a first power density, and the final stage FET is characterized by a second power density that is at least <NUM> percent greater than the first power density. According to yet another further embodiment, the driver stage FET is characterized by a first drain-source on resistance, and the final stage FET is characterized by a second drain-source on resistance that is greater than the first drain-source on resistance. According to yet another further embodiment, the amplifier further includes an amplifier substrate, and a power amplifier module coupled to the amplifier substrate, where the power amplifier module includes the semiconductor die in which the driver stage FET and the final stage FET are integrated, a first connector coupled to the substrate and configured to receive a first bias voltage, a second connector coupled to the substrate and configured to receive a second bias voltage, a first conductive path coupled between the first connector and the driver stage output, and a second conductive path coupled between the second connector and the final stage output. According to yet another further embodiment, the amplifier further includes a pre-amplifier module coupled to the substrate, and a third conductive path coupled between the first connector and the pre-amplifier module.

An embodiment in accordance with claim <NUM> of a method of operating an amplifier that includes a driver stage amplifier transistor and a final stage amplifier transistor coupled in series and integrated in a semiconductor die, includes the steps of providing an output of the driver stage amplifier transistor with a first bias voltage, and providing an output of the final stage amplifier transistor with a second bias voltage, where the second bias voltage is at least twice the first bias voltage. According to a further embodiment, the first bias voltage is less than <NUM> volts, and the second bias voltage is greater than <NUM> volts. According to another further embodiment, the driver stage amplifier transistor and the final stage amplifier transistor are embodied in a power amplifier module coupled to a substrate, the amplifier further includes a pre-amplifier module coupled to the substrate, and the method further includes providing the pre-amplifier module with the first bias voltage.

Disclosed herein are embodiments of an RF power amplifier architecture that includes a low voltage driver stage (e.g., <NUM> volts (V)) and a high voltage final stage (e.g., <NUM>-<NUM> V), where "low voltage driver stage" means a power amplifier transistor that is configured to operate with a relatively low output bias voltage (e.g., drain bias voltage), and "high voltage final stage" means a power amplifier transistor that is configured to operate with a relatively high output bias voltage (e.g., drain bias voltage). Compared with conventional, two-stage amplifiers that bias the outputs of both their driver and final stages with the same relatively high voltage (e.g., a voltage of <NUM> V or more), the RF power amplifier architectures disclosed herein may have several potential advantages.

For example, given the relatively low output bias voltage, the low voltage driver stage embodiments disclosed herein may be designed to have a significantly lower output impedance (e.g., Z<NUM>, or the impedance looking into the drain of the driver stage transistor) than a conventional high voltage driver stage that has its output biased with a higher voltage (e.g., <NUM> V or more). For example, an embodiment of a low voltage driver stage may have an output impedance of less than <NUM> ohms, whereas a conventional high voltage driver stage may have an output impedance of <NUM> ohms or more. Given that the input impedance of the final stage (e.g., Z<NUM>, or the impedance looking into the gate of the final stage transistor) may be just a few ohms (e.g., <NUM>-<NUM> ohms or less), it is apparent that an embodiment of an interstage impedance matching network between the low voltage driver stage output and the high voltage final stage input may be characterized by a significantly reduced impedance transformation ratio (i.e., a ratio of the output impedance of the driver stage to the input impedance of the final stage), when compared with the impedance transformation ratio than would be required for a conventional two-stage amplifier. For example, for a conventional two-stage power amplifier, a <NUM> V driver stage may require an impedance transformation ratio on the order of <NUM>: <NUM> to <NUM>:<NUM> (e.g., from about <NUM>-<NUM> ohms Z<NUM> to about <NUM> ohms Z<NUM>), while an embodiment of a low voltage driver stage may only require an impedance transformation ratio of less than <NUM>:<NUM> (e.g., on the order of <NUM>:<NUM> to <NUM>:<NUM>, corresponding to an impedance transformation ratio from about <NUM>-<NUM> ohms Z<NUM> to about <NUM> ohms Z<NUM>).

As only a relatively low impedance transformation ratio is needed, an interstage impedance matching network for the various embodiments may be relatively simple (e.g., fewer impedance matching stages and passive components). Accordingly, the interstage impedance matching network losses may be significantly reduced (e.g., by <NUM> decibels (dB) or more) during operation, when compared with the losses incurred by conventional, two-stage amplifiers.

Assuming a <NUM> dB interstage match loss reduction, for example, the required output power from the low voltage driver stage also may be reduced by 3dB. Accordingly, the direct current (DC) power consumption of an embodiment of a low voltage driver stage also may be reduced, in comparison with a conventional, high voltage driver stage. In other words, the DC power consumption of embodiments of a low voltage driver stage discussed herein may be significantly less than the DC power consumption of conventional driver stages. Essentially, with relatively few matching stages and components, the power dissipated in an embodiment of an interstage matching network is significantly reduced, when compared with conventional, two-stage power amplifiers, further contributing to an efficiency boost.

Further, for wireless infrastructure applications, power amplifiers typically are required to operate at an average power of about <NUM>-<NUM> dB back off from peak power. While the final stage operates at back off, the driver stage operates at far back off, but typically with low efficiency. As a result, the DC power consumption reduction achieved using an embodiment of the inventive subject matter actually may be multiples of the driver output power, which leads to significant overall line-up efficiency improvement. Further still, implementation of a relatively simple interstage impedance matching network, in accordance with the various embodiments, may result in a wider RF bandwidth than is achievable using conventional, two-stage amplifiers.

The driver and final stage transistors can be integrally formed on a single semiconductor substrate (e.g., both the driver and final stages are silicon-based transistors integrated in a single semiconductor chip), with the driver stage transistor customized for low voltage operation, and the final stage transistor customized for high voltage operation. Accordingly, a more integrated line-up may be achieved, which makes for a cost-effective and high-throughput solution that is attractive and suitable for massive multiple-input/multiple-output (MIMO) applications.

Furthermore, embodiments of the invention may leverage the use of a standardly available, low voltage power supply (e.g., a <NUM> V supply), which also may be used to power other RF subsystems of an RF transmitter or transceiver (e.g., a transmitter power amplifier pre-driver, a transmit/receive switch, a duplexer, and/or a receiver low noise amplifier). Therefore, the low voltage power supply may not present a unique requirement that would have otherwise added system cost.

<FIG> is a schematic circuit diagram of a power amplifier circuit <NUM> that includes a low voltage driver stage and a high voltage final stage, and <FIG> is a top view of a two-stage power amplifier integrated circuit (IC) <NUM> that embodies the power amplifier circuit <NUM> of <FIG>, in accordance with various example embodiments. For clarity and brevity, <FIG> and <FIG> will be described together, below.

As best illustrated in <FIG>, many of the components of IC <NUM> that correspond to components of circuit <NUM> may be coupled to or integrally-formed with a single semiconductor die <NUM>, which is mounted to a mounting surface of a host substrate <NUM>. For example, as will be described in more detail in conjunction with <FIG>, the host substrate <NUM> may be a small printed circuit board (PCB), although the host substrate <NUM> alternatively may be a conductive package flange or other suitable substrate. As will also be described in more detail in conjunction with <FIG>, the host substrate <NUM> may include an embedded, electrically and thermally conductive coin <NUM> or thermal vias, which is/are configured to provide a ground reference voltage and to function as a heat sink, and the semiconductor die <NUM> may be mounted to the conductive coin <NUM> or thermal vias.

Power amplifier circuit <NUM> and power amplifier IC <NUM> each include an RF input <NUM>, <NUM>, an input impedance matching circuit <NUM>, <NUM>, a driver stage transistor <NUM>, <NUM>, an interstage impedance matching circuit <NUM>, <NUM>, a final stage transistor <NUM>, <NUM>, first and second input (gate) bias circuits <NUM>, <NUM>, <NUM>, <NUM>, first and second output (drain) bias circuits <NUM>, <NUM>, <NUM>, <NUM>, and an RF output <NUM>, <NUM>, in an embodiment. It should be noted that, in the embodiment of <FIG>, the second output (drain) bias circuit <NUM> actually is implemented off chip (i.e., circuit <NUM> is electrically coupled to, but not integrally formed with IC <NUM>). In an alternate embodiment, the second output (drain) bias circuit <NUM> may be implemented on-chip, similar to the implementations of bias circuits <NUM>, <NUM>, and <NUM>.

RF input <NUM>, <NUM> and RF output <NUM>, <NUM> each may include a conductor, which is configured to enable the circuit <NUM> and IC <NUM> to be electrically coupled with external circuitry (not shown). For example, as depicted in <FIG>, the RF input <NUM> includes a conductive bondpad, which is exposed at the top surface of the die <NUM>, and which is configured for attachment of a set of one or more wirebonds (e.g., wirebond array <NUM>, <FIG>). Conversely, the RF output <NUM> is electrically coupled to (or is a same conductive structure as) an output/drain terminal <NUM> of the final stage transistor <NUM>, which also may be a conductive bondpad that is exposed at the top surface of the die <NUM>. The first set of wirebonds <NUM> is configured to convey an input RF signal from external circuitry (e.g., pre-amplifier <NUM>, <FIG>) to the RF input <NUM>, and the second set of wirebonds <NUM> is configured to convey an output RF signal from the RF output <NUM> to external circuitry (e.g., duplexer <NUM>, <FIG>).

The input impedance matching circuit <NUM>, <NUM> is electrically coupled between the RF input <NUM>, <NUM> and an input/gate terminal <NUM>, <NUM> of driver stage transistor <NUM>, <NUM>. Further, interstage impedance matching circuit <NUM>, <NUM> is electrically coupled between an output/drain terminal <NUM>, <NUM> of the driver stage transistor <NUM>, <NUM> and an input/gate terminal <NUM>, <NUM> of final stage transistor <NUM>, <NUM>. An output/drain terminal <NUM>, <NUM> of the final stage transistor <NUM>, <NUM> is electrically coupled to (or is a same conductive structure as) the RF output <NUM>, <NUM>.

Each transistor <NUM>, <NUM>, <NUM>, <NUM> is characterized by input and output impedances, with the output impedance of transistor <NUM>, <NUM> (Z<NUM>) and the input impedance of transistor <NUM>, <NUM> (Z<NUM>) being most relevant to the inventive subject matter, as will be discussed below in detail. The input and interstage impedance matching circuits <NUM>, <NUM> each are configured to perform a desired impedance transformation to, from, or between the input and output impedances of transistors <NUM>, <NUM>, <NUM>, <NUM>.

For example, the input impedance matching circuit <NUM>, <NUM> is configured to raise the impedance of circuit <NUM> or IC <NUM> to a higher (e.g., intermediate or higher) impedance level (e.g., in a range from about <NUM> to about <NUM> Ohms or higher). According to an embodiment, input impedance matching circuit <NUM>, <NUM> includes a shunt inductive element <NUM>, <NUM> and a series capacitance <NUM>, <NUM>. The shunt inductive element <NUM>, <NUM> has a first terminal electrically coupled to the RF input <NUM>, <NUM>, and a second terminal electrically coupled to a ground reference node (e.g., to conductive layer <NUM>, <FIG>, <FIG>, with through substrate vias (TSVs) or through doped sinker regions). The series capacitance <NUM>, <NUM> has a first terminal (or electrode) electrically coupled to the RF input <NUM>, <NUM>, and a second terminal (or electrode) electrically coupled to the input/gate terminal <NUM>, <NUM> of transistor <NUM>, <NUM>. According to an embodiment, inductive element <NUM>, <NUM> may have an inductance value in a range between about <NUM> nanohenries (nH) to about <NUM> nH, and capacitance <NUM>, <NUM> may have a capacitance value in a range between about <NUM> picofarads (pF) to about <NUM> pF, although each of these components may have component values lower or higher than the above-given ranges, as well.

The interstage impedance matching circuit <NUM>, <NUM> is configured to match the output impedance (Z1) of driver stage transistor <NUM>, <NUM> to the input impedance (Z2) of final stage transistor <NUM>, <NUM>. According to an embodiment, the interstage impedance matching circuit <NUM>, <NUM> includes a series inductive element <NUM>, <NUM>, a series capacitance <NUM>, <NUM>, and a shunt inductive element <NUM>, <NUM>. The series inductive element <NUM>, <NUM> and the series capacitance <NUM>, <NUM> are coupled in series with each other between the output/drain terminal <NUM>, <NUM> of the driver stage transistor <NUM>, <NUM> and the input/gate terminal <NUM>, <NUM> of the final stage transistor <NUM>, <NUM>, with an intermediate node <NUM> between the two series-coupled components. More particularly, the series inductive element <NUM>, <NUM> has a first terminal electrically coupled to the output/drain terminal <NUM>, <NUM> of the driver stage transistor <NUM>, <NUM>, and a second terminal electrically coupled to the intermediate node <NUM>, and the series capacitance <NUM>, <NUM> has a first terminal (or electrode) electrically coupled to the intermediate node <NUM>, and a second terminal (or electrode) electrically coupled to the input/gate terminal <NUM>, <NUM> of the final stage transistor <NUM>, <NUM>. The shunt inductive element <NUM>, <NUM> has a first terminal electrically coupled to the intermediate node <NUM>, and a second terminal electrically coupled to a ground reference node (e.g., through capacitance <NUM>, <NUM>). According to an embodiment, inductive element <NUM>, <NUM> may have an inductance value in a range between about <NUM> nH to about <NUM> nH, capacitance <NUM>, <NUM> may have a capacitance value in a range between about <NUM> pF to about <NUM> pF, and inductive element <NUM>, <NUM> may have an inductance value in a range between about <NUM> nH to about <NUM> nH, although each of these components may have component values lower or higher than the above-given ranges, as well.

As illustrated in <FIG>, inductive elements <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and capacitances <NUM>, <NUM>, <NUM>, <NUM> may be integrally formed in semiconductor die <NUM>. For example, inductive elements <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may be implemented as spiral inductors that are formed from patterned conductive portions of the build-up layers of die <NUM> (e.g., layers <NUM>, <FIG>, <FIG>), and capacitances <NUM>, <NUM>, <NUM>, <NUM> may be implemented as metal-insulator-metal (MIM) capacitors that are formed in the build-up layers of die <NUM>. In alternate embodiments, some or all of the inductive elements <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and capacitances <NUM>, <NUM>, <NUM>, <NUM> may be implemented as surface-mount, "chip" components, which are physically coupled to the top surface of die <NUM>, and electrically coupled through bondpads or other contacts (not shown) exposed at the top surface of die <NUM>. Further, in other alternate embodiments, some or all of the inductive elements <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may be implemented as wirebonds.

Driver stage and final stage transistors <NUM>, <NUM>, <NUM>, <NUM> are the primary active components of circuit <NUM> and IC <NUM>. Each of the transistors <NUM>, <NUM>, <NUM>, <NUM> is configured to amplify an RF signal conducted through the transistor <NUM>, <NUM>, <NUM>, <NUM>. As used herein, the term "transistor" means a field effect transistor (FET) or another type of suitable transistor. For example, a "FET" may be a metal-oxide-semiconductor FET (MOSFET), a laterally-diffused MOSFET (LDMOS FET), an enhancement-mode or depletion-mode high electron mobility transistor (HEMT), or another type of FET. The description herein refers to each transistor as including an input terminal (or control terminal) and two current-conducting terminals. For example, using terminology associated with FETs, an "input terminal" refers to a gate terminal of a transistor, and first and second current-conducting terminals refer to drain and source terminals (or vice versa) of a transistor.

Driver stage transistor <NUM>, <NUM> includes an input terminal <NUM> (e.g., a gate terminal <NUM>), a first current conducting terminal <NUM> (e.g., an "output" or drain terminal <NUM>), and a second current conducting terminal <NUM> (e.g., a source terminal, not shown in <FIG>). Similarly, final stage transistor <NUM>, <NUM> includes an input terminal <NUM> (e.g., a gate terminal <NUM>), a first current conducting terminal <NUM> (e.g., output/drain terminal <NUM>), and a second current conducting terminal <NUM> (e.g., a source terminal, not shown in <FIG>).

In a specific embodiment, each transistor <NUM>, <NUM>, <NUM>, <NUM> includes an active area disposed between its input/gate terminals <NUM>, <NUM>, <NUM>, <NUM> and output/drain terminals <NUM>, <NUM>, <NUM>, <NUM>. As best shown in <FIG>, the active areas of transistors <NUM>, <NUM> each include a plurality of elongated, parallel-aligned, and interdigitated drain regions (e.g., multiple, parallel-aligned instances of drain region <NUM>, <NUM>, <FIG>, <FIG>) and source regions (e.g., multiple, parallel-aligned instances of source region <NUM>, <NUM>, <FIG>, <FIG>), where each drain region and each source region is a doped semiconductor region formed in a base semiconductor substrate (e.g., substrate <NUM>, <FIG>).

A variably-conductive channel region and a drain drift region (e.g., drift regions <NUM>, <NUM>, <FIG>, <FIG>) are present between adjacent source regions and drain regions. Conductive (e.g., polysilicon or metal) gate structures (e.g., gate structures <NUM>, <NUM>, <FIG>, <FIG>) extend over and along the elongated channel regions. The gate structures of transistor <NUM> are electrically coupled together with a first gate manifold, and the gate structures of transistor <NUM> are electrically coupled together with a second gate manifold. Each of the gate manifolds of transistors <NUM>, <NUM> are closely electrically coupled to their respective input/gate terminals <NUM>, <NUM>. Similarly, the drain regions of transistor <NUM> are electrically coupled together with first drain manifold, and the drain regions of transistor <NUM> are electrically coupled together with second drain manifold. Each of the drain manifolds of transistors <NUM>, <NUM> are closely electrically coupled to their respective output/drain terminals <NUM>, <NUM>. Due to their elongated shapes, each set of adjacent drain and source regions, along with a gate structure (e.g., gate structures <NUM>, <NUM>, <FIG>, <FIG>) overlying a channel region between the adjacent drain and source regions, may be referred to as a "transistor finger. " Each transistor <NUM>, <NUM>, <NUM>, <NUM> includes a plurality of parallel transistor fingers within the active area of the transistor.

In various embodiments, amplifier circuit <NUM> and amplifier IC <NUM> each include DC bias circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, which are configured to provide DC bias voltages to the input/gate terminals <NUM>, <NUM>, <NUM>, <NUM> and output/drain terminals <NUM>, <NUM>, <NUM>, <NUM> of transistors <NUM>, <NUM>, <NUM>, <NUM>. Each of the input DC bias circuits <NUM>, <NUM>, <NUM>, <NUM> is configured as a "shunt inductance" (or shunt-L) circuit, which includes an inductive element <NUM>, <NUM>, <NUM>, <NUM> and a capacitor <NUM>, <NUM>, <NUM>, <NUM> connected in series between a transistor input/gate terminal <NUM>, <NUM>, <NUM>, <NUM> and a ground reference voltage, with an intermediate node or contact <NUM>, <NUM>, <NUM>, <NUM> between each inductor/capacitor pair. Similarly, each of the output DC bias circuits <NUM>, <NUM>, <NUM>, <NUM> is configured as a "shunt inductance" (or shunt-L) circuit, which includes an inductive element <NUM>, <NUM>, <NUM>, <NUM> and a capacitor <NUM>, <NUM>, <NUM>, <NUM> connected in series between a transistor output/drain terminal <NUM>, <NUM>, <NUM>, <NUM> and a ground reference voltage, with an intermediate node or contact <NUM>, <NUM>, <NUM>, <NUM> between each inductor/capacitor pair. According to an embodiment, contacts <NUM>, <NUM>, <NUM> (corresponding to nodes <NUM>-<NUM>) are implemented as conductive bondpads, which are exposed at the top surface of die <NUM>, and which are configured for attachment of one or more wirebonds. Conversely, contact <NUM> (corresponding to node <NUM>) is implemented as a portion of a patterned conductive layer on the top surface of substrate <NUM>, and which also is configured for attachment of one or more wirebonds (e.g., wirebonds <NUM>, <FIG>).

According to an embodiment, inductive elements <NUM>, <NUM>, <NUM> and capacitors <NUM>, <NUM>, <NUM> are integrally formed in semiconductor die <NUM>. For example, each of inductors <NUM>, <NUM>, <NUM> may be implemented as a spiral inductor that is formed from patterned conductive portions of the build-up layers of die <NUM> (e.g., layers <NUM>, <FIG>, <FIG>), and each of capacitors <NUM>, <NUM>, <NUM> may be implemented as a metal-insulator-metal (MIM) capacitor that is formed in the build-up layers of die <NUM>. In alternate embodiments, some or all of the inductive elements <NUM>, <NUM>, <NUM> and capacitors <NUM>, <NUM>, <NUM> may be implemented as surface-mount, "chip" components, which are physically coupled to the top surface of die <NUM> or substrate <NUM>, and electrically coupled through bondpads or other contacts (not shown) exposed at the top surface of die <NUM> or substrate <NUM>. Further, in other alternate embodiments, some or all of the inductive elements <NUM>, <NUM>, <NUM> may be implemented as wirebonds. For example, in the embodiment of <FIG>, inductive element <NUM> is implemented as a set of wirebonds that are electrically coupled between the output/drain terminal <NUM> of final stage transistor <NUM> and contact <NUM>, and capacitor <NUM> is implemented as a chip capacitor that is coupled to the top surface of substrate <NUM>.

As illustrated in <FIG>, the output/drain terminal <NUM> is configured to enable multiple wirebond arrays <NUM>, <NUM> to be coupled to the output/drain terminal <NUM> with angularly offset (e.g., perpendicular) orientations. More specifically, the output/drain terminal <NUM> has an elongated first conductive bondpad <NUM> to which wirebond array <NUM> is connected, and an elongated second conductive bondpad <NUM> (or "sidepad") to which wirebond array <NUM> is connected. For reasons that will be apparent in the discussion of <FIG>, the output/drain terminal <NUM> also may include an elongated third conductive bondpad <NUM> (or "sidepad") to which another wirebond array may be connected. In any event, the second and third conductive sidepads <NUM>, <NUM> may be coupled or connected to opposite ends of the elongated first conductive bondpad <NUM>, and the second and third conductive sidepads <NUM>, <NUM> may have their longest dimensions oriented perpendicularly to the longest dimension of the first conductive bondpad, in an embodiment.

According to an embodiment, each of capacitors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> has a sufficiently high capacitance value (e.g., greater than about <NUM> pF) to ensure that each node/contact <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> corresponds to an RF low-impedance point (e.g., an "RF cold point" or a "pseudo-RF cold point"). In other words, each node/contact <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> represents a low impedance point in the circuit for RF signals. This ensures that minimal RF signal energy is lost through the bias circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>.

To provide bias voltages to the input/gate terminals <NUM>, <NUM>, <NUM>, <NUM> and output/drain terminals <NUM>, <NUM>, <NUM>, <NUM> of the transistors <NUM>, <NUM>, <NUM>, <NUM>, an external gate or drain DC bias voltage supply <NUM>, <NUM>, <NUM>, <NUM> (not shown in <FIG>) is connected to each node/contact <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>. More specifically, a driver stage gate supply <NUM> is connected to node/contact <NUM>, <NUM> to provide a DC bias voltage to the input/gate terminal <NUM>, <NUM> of driver stage transistor <NUM>, <NUM>, a driver stage drain supply <NUM> is connected to node/contact <NUM>, <NUM> to provide a DC bias voltage to the output/drain <NUM>, <NUM> of driver stage transistor <NUM>, <NUM>, a final stage gate supply <NUM> is connected to node/contact <NUM>, <NUM> to provide a DC bias voltage to the input/gate terminal <NUM>, <NUM> of final stage transistor <NUM>, <NUM>, and a final stage drain supply <NUM> is connected to node/contact <NUM>, <NUM> to provide a DC bias voltage to the output/drain terminal <NUM>, <NUM> of final stage transistor <NUM>, <NUM>. The driver stage and final stage gate supplies <NUM>, <NUM> each may provide a DC gate bias voltage in a range of about <NUM> V to about <NUM> V, although the DC gate bias voltages may be lower or higher, as well.

According to an embodiment, the driver stage and final stage drain supplies <NUM>, <NUM> provide substantially different DC drain bias voltages to transistors <NUM>, <NUM> and <NUM>, <NUM>, respectively. More particularly, the driver stage drain supply <NUM> provides a significantly lower DC drain bias voltage to node/contact <NUM>, <NUM> (and thus to the output/drain <NUM>, <NUM> of driver transistor <NUM>, <NUM>) than the DC drain bias voltage that is provided by the final stage drain supply <NUM> to node/contact <NUM>, <NUM> (and thus to the output/drain terminal <NUM>, <NUM> of final stage transistor <NUM>, <NUM>). Accordingly, the driver stage drain supply <NUM> may be referred to as a driver stage low voltage (LV) supply, and the driver stage transistor <NUM>, <NUM> may be referred to as a low voltage driver stage, whereas the final stage drain supply <NUM> may be referred to as a final stage high voltage (HV) supply, and the final stage transistor <NUM>, <NUM> may be referred to as a high voltage final stage.

In a particular embodiment, the driver stage drain supply <NUM> provides a DC bias voltage of less than about <NUM> V, and in a more particular embodiment, the driver stage drain supply <NUM> provides a DC bias voltage of about <NUM> V. As will be described in more detail in conjunction with <FIG>, later, the driver stage drain supply <NUM> preferably supplies a DC bias voltage that can also be utilized by other circuitry in an RF system (e.g., by a pre-amplifier <NUM>, duplexer <NUM>, and/or low noise amplifier (LNA) <NUM> of a transmitter or transceiver <NUM>, <FIG>). For example, the driver stage drain supply <NUM> may be a commercial, off-the-shelf (or standard) power supply, although the driver stage drain supply <NUM> may be a custom power supply, as well. Conversely, in a particular embodiment, the final stage drain supply <NUM> provides a DC bias voltage of at least twice as large as the DC bias voltage of the driver stage drain supply <NUM>. For example, the final stage drain supply <NUM> may provide a DC bias voltage greater than about <NUM> V (e.g., in a range of <NUM>-<NUM> V or higher). In various embodiments, the ratio of the DC bias voltage provided by final stage drain supply <NUM> to the DC bias voltage provided by driver stage drain supply <NUM> is greater than <NUM> (e.g., in a range between <NUM> and <NUM>). In a more specific embodiment, the ratio is between about <NUM> and about <NUM> when the DC bias voltage provided by final stage drain supply <NUM> is about <NUM>-<NUM> V, and the DC bias voltage provided by driver stage drain supply <NUM> is about <NUM> V.

According to an embodiment, the driver stage transistor <NUM>, <NUM> and the final stage transistor <NUM>, <NUM> are configured differently from each other in order to operate efficiently with the relatively low and relatively high DC drain bias voltages, respectively. Essentially, the driver stage transistor <NUM>, <NUM> is configured to have a significantly lower power density and a significantly lower drain-source "on" resistance (RDSon) (i.e., the total resistance between the drain terminal <NUM> and source terminal <NUM> when the transistor <NUM>, <NUM> is fully on) than the final stage transistor <NUM>, <NUM>. For example, the driver stage transistor <NUM>, <NUM> may have a power density in a range of about <NUM> watts per millimeter (W/mm) to about <NUM> W/mm, whereas the final stage transistor <NUM>, <NUM> may have a power density in a range of about <NUM> W/mm to about <NUM> W/mm (e.g., the power density of the final stage transistor <NUM>, <NUM> is at least <NUM> percent greater than (i.e., <NUM> times) the power density of the driver stage transistor <NUM>, <NUM>, and potentially up to or greater than <NUM> times the power density of the driver stage transistor <NUM>, <NUM>). Further, the driver stage transistor <NUM>, <NUM> may have an RDSon in a range of about <NUM> ohm-mm to about <NUM> ohm-mm, whereas the final stage transistor <NUM>, <NUM> may have an RDSon in a range of about <NUM> ohm-mm to about <NUM> ohm-mm (e.g., the RDSon of the final stage transistor <NUM>, <NUM> is greater than, and in some cases up to three times greater than the RDSon of the driver stage transistor <NUM>, <NUM>).

Because the driver stage transistor <NUM>, <NUM> is configured to operate with a relatively low DC drain bias voltage, the driver stage transistor <NUM>, <NUM> may be configured to have performance optimized (e.g. lower on resistance (RDSon)). To accomplish this optimization, the driver stage transistor <NUM>, <NUM> may be designed to have a significantly lower breakdown voltage than the final stage transistor <NUM>, <NUM>. Although the difference in breakdown voltages may be accomplished in a number of ways, according to a particular embodiment, the difference may be achieved by configuring the driver stage transistor <NUM>, <NUM> with a significantly shorter drift region between the gate and the drain within each transistor finger. To illustrate, <FIG> and <FIG> depict cross-sectional, side views of portions of the driver amplifier transistor <NUM> and the final stage amplifier transistor <NUM> of <FIG>, in accordance with an embodiment. More specifically, each of <FIG> and <FIG> depict a cross-sectional, side view through a single transistor finger within the driver amplifier transistor <NUM> (<FIG>) and the final stage amplifier transistor <NUM> (<FIG>), respectively.

Both the driver amplifier transistor <NUM> (<FIG>) and the final stage amplifier transistor <NUM> (<FIG>) are integrally formed with the semiconductor die <NUM>. More specifically, the semiconductor die <NUM> includes a base semiconductor substrate <NUM>, and a plurality of build-up layers <NUM> over a top surface <NUM> of the base semiconductor substrate <NUM> (only a lower portion of the build-up layers <NUM> are shown in <FIG> and <FIG> to avoid unnecessary detail). In a particular example embodiment, the base semiconductor substrate <NUM> is a high-resistivity silicon substrate (e.g., a silicon substrate having bulk resistivity in a range of about <NUM> ohm/centimeter (cm) to about <NUM>,<NUM> ohm/cm or greater). Alternatively, the base semiconductor substrate may be a semi-insulating gallium arsenide (GaAs) substrate (e.g., a GaAs substrate having bulk resistivity up to <NUM><NUM> ohm/cm), or another suitable high-resistivity substrate. In still other alternate embodiments, the base semiconductor substrate may be any of multiple variants of a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate (e.g., to accommodate, for example, GaN epitaxial layers grown on SiC), or other III-V semiconductor substrates. An advantage to the use of a high-resistivity substrate is that such a substrate may enable various on-die circuitry to exhibit relatively low losses, when compared with amplifier dies that do not utilize a high-resistivity substrate. In other embodiments, however, a lower resistivity (or more conductive) substrate may be used.

In an embodiment in which substrate <NUM> is a high-resistivity substrate, conductive paths may be made between the top surface <NUM> of the substrate <NUM> and a conductive backside contact <NUM> on the bottom surface of the substrate <NUM> using through substrate vias (TSVs, not shown). Alternatively, for lower resistivity (or more conductive) substrates, conductive paths between the top surface <NUM> and the backside contact <NUM> may be made, at least in part, using low resistivity sinker regions. In any event, the backside contact <NUM> may be connected to a ground (e.g., to coin <NUM> or thermal vias, <FIG>), when die <NUM> is integrated into a larger electrical system, and the TSVs (or sinker regions) may be used to electrically connect the source regions <NUM>, <NUM> and other components (e.g., inductor <NUM> and capacitors <NUM>, <NUM>, <NUM>, <FIG>) to ground.

Each transistor <NUM>, <NUM> includes gate structure <NUM>, <NUM> supported by a top surface <NUM> of the semiconductor substrate <NUM>, along with doped source regions <NUM>, <NUM> and drain regions <NUM>, <NUM> (or more generally "current-carrying regions") extending from the top surface <NUM> into the substrate <NUM> on either side of the gate structure <NUM>, <NUM>. Each source region <NUM>, <NUM> and drain region <NUM>, <NUM>, or portions thereof, may have a dopant concentration at a level sufficient to establish ohmic contacts with electrodes or interconnects <NUM>, <NUM> and <NUM>, <NUM>.

According to an embodiment, each source region <NUM>, <NUM> may be disposed along or aligned with a first sidewall <NUM>, <NUM> of the gate structure <NUM>, <NUM>. Further, each drain region <NUM>, <NUM> may be laterally separated across the surface <NUM> of the substrate <NUM> from a second, opposite sidewall <NUM>, <NUM> of the gate structure <NUM>, <NUM>, and a drift region <NUM>, <NUM> extends laterally from each drain region <NUM>, <NUM> to each gate structure <NUM>, <NUM>.

Each transistor <NUM>, <NUM> also includes a well or diffused region <NUM>, <NUM> in the semiconductor substrate <NUM> under the gate structure <NUM>, <NUM>. During operation, a channel or channel region is formed in the well region <NUM>, <NUM> at a surface <NUM> of the semiconductor substrate <NUM> via application of a DC bias voltage (e.g., supplied by driver stage LV drain supply <NUM> or final stage HV drain supply <NUM>, <FIG>) to a conductive portion of the gate structure <NUM>, <NUM>. As discussed previously, during operation, the drain region <NUM> of the driver stage transistor <NUM> is biased at a significantly lower bias voltage than the bias voltage applied to the drain region <NUM> of the final stage transistor <NUM>.

The die <NUM> may include one or more passivation layers <NUM> covering the surface <NUM>. One or more shield plate(s) <NUM>, <NUM>, <NUM> may be disposed between adjacent dielectric or passivation layers <NUM>. As indicated in <FIG> and <FIG>, the configuration of the shield plates <NUM>, <NUM>, <NUM> may be different for the driver stage transistor <NUM> (which includes only a single shield plate <NUM>) and the final stage transistor <NUM> (which includes two shield plates <NUM>, <NUM>). In any event, the shield plate(s) <NUM>, <NUM>, <NUM> may help protect the gate dielectric from damage or degradation arising from charge carriers accelerated under the electric field arising from the drain-source voltage (i.e., "hot carriers"). The shield plate(s) <NUM>, <NUM>, <NUM> may also help to reduce the maximum electric field in the drift region <NUM>, <NUM>. The shield plate(s) <NUM>, <NUM>, <NUM> may be grounded or otherwise biased to deter injection of such hot carriers into the oxide or other dielectric material under the gate structure <NUM>, <NUM> and/or the oxide or other dielectric material over the drift region <NUM>, <NUM>.

According to an embodiment, the length <NUM> of the drift region <NUM> in driver stage transistor <NUM> (i.e., the dimension from sidewall <NUM> of gate <NUM> to the drain region <NUM>) is significantly shorter than the length <NUM> of the drift region <NUM> in final stage transistor <NUM> (i.e., the dimension from sidewall <NUM> of gate <NUM> to the drain region <NUM>), which results in a significantly lower RDSon and breakdown voltage for the driver stage transistor <NUM>, in comparison with the RDSon and breakdown voltage of the final stage transistor <NUM>. In some embodiments, for example, the length <NUM> of the drift region <NUM> in driver stage transistor <NUM> may be in a range of about <NUM> microns to about <NUM> microns (e.g., about <NUM> microns), whereas the length <NUM> of the drift region <NUM> in final stage transistor <NUM> may be in a range of about <NUM> microns to about <NUM> microns (e.g., about <NUM> microns). In other words, the length <NUM> of the drift region <NUM> in the final stage transistor <NUM> is at least <NUM> percent larger than the length <NUM> of the drift region <NUM> in the driver stage transistor <NUM> (e.g., in a first range from about <NUM> percent to about <NUM> percent larger, or in a second range from about <NUM> percent to about <NUM> percent larger). It should be noted that the lengths <NUM>, <NUM> may be smaller or larger than the above-given ranges, as well. Essentially, establishing a significantly shorter length <NUM> for the drift region <NUM> in the driver stage transistor <NUM> in comparison to the length <NUM> of the drift region <NUM> in the final stage transistor <NUM> causes the driver stage transistor <NUM> to have a significantly lower (e.g., at least about <NUM>-<NUM> percent lower) RDSon than the RDSon of the final stage transistor <NUM>, and causes the driver stage transistor <NUM> to have a significantly lower (e.g., at least about <NUM>-<NUM> percent lower) breakdown voltage than the breakdown voltage of the final stage transistor <NUM>. Said another way, the breakdown voltage of the final stage transistor <NUM> may be significantly higher (e.g., at least about <NUM>-<NUM> percent higher) than the breakdown voltage of the driver stage transistor <NUM>. For example, the breakdown voltage of the driver stage transistor <NUM> may be in a range of about <NUM> V to about <NUM> V (e.g., about <NUM> V), and the breakdown voltage of the final stage transistor <NUM> may be in a range of about <NUM> V to about <NUM> V (e.g., about <NUM> V).

In addition to having a lower RDSon, the lower power density of the driver stage transistor <NUM>, <NUM> enables the driver stage transistor <NUM> to be designed with more transistor fingers, per unit width (horizontal dimension in <FIG>), than the final stage transistor <NUM>. By providing more transistor fingers per unit width in the driver stage transistor <NUM>, the RDSon of the driver stage transistor <NUM> may be reduced even further, with respect to the RDSon of the final stage transistor <NUM> without consuming significant additional die area. In an embodiment, the reduced RDSon of the driver stage transistor <NUM> allows the frequency response and efficiency of the driver stage transistor <NUM> to be optimized for the lower voltage operation of the driver stage transistor <NUM>.

Although, in the above-described embodiment, breakdown voltage and RDSon differences are achieved, at least in part, by implementing a drift region <NUM> with a shorter length <NUM> in the driver stage transistor <NUM> than the length <NUM> of the drift region <NUM> that is implemented in the final stage transistor <NUM>, the breakdown voltage and RDSon differences may be accomplished in other ways, as well. For example, breakdown voltage and RDSon differences could be achieved, as well, by using various combinations of different doping levels, different drift region widths (dimension into the page in <FIG>, <FIG>), different drift region depths (vertical dimension in <FIG>, <FIG>), different drift region lengths, and/or by configuring other characteristics of the driver stage transistor <NUM> and the final stage transistor <NUM> differently. In other words, drift regions <NUM>, <NUM> have one or more different characteristics selected from different doping levels, different drift region widths, different drift region depths, and different drift region lengths.

Referring again to <FIG> and <FIG>, and given the characteristics of the driver and final stage transistors <NUM>, <NUM>, <NUM>, <NUM> described above and the relatively low output bias voltage provided to the driver stage transistor <NUM>, <NUM>, the low voltage driver transistor <NUM>, <NUM> may have a significantly lower output impedance (e.g., Z<NUM>, or the impedance looking into the drain of the driver stage transistor <NUM>, <NUM>) than a conventional high voltage driver transistor (e.g., in a conventional system in which the driver transistor has its output biased with a higher voltage, such as <NUM> V or more). For example, an embodiment of a low voltage driver stage transistor <NUM>, <NUM> may have an output impedance of less than <NUM> ohms (e.g., from <NUM>-<NUM> ohms), whereas a conventional high voltage driver stage may have an output impedance of <NUM>-<NUM> ohms or more. In contrast, the input impedance of the final stage transistor <NUM>, <NUM> (e.g., Z<NUM>, or the impedance looking into the gate of the final stage transistor <NUM>, <NUM>) may be just a few ohms (e.g., from <NUM>-<NUM> ohms). Thus, in an embodiment, the output impedance of the low voltage driver stage transistor <NUM>, <NUM>, Z<NUM> (e.g., less than about <NUM> ohms) may match the input impedance Z<NUM> of the final stage transistor <NUM>, <NUM> (e.g., between about <NUM> ohm and <NUM> ohms), facilitating low transformation ratio, easy-to-realize impedance matching between the output of the low voltage driver stage transistor <NUM>, <NUM> and the input of the final stage transistor <NUM>, <NUM>.

As discussed previously, circuit <NUM> and IC <NUM> each include an interstage impedance matching network <NUM>, <NUM>, which is electrically coupled between the output/drain <NUM>, <NUM> of the low voltage driver stage transistor <NUM>, <NUM> and the input/gate terminal <NUM>, <NUM> of the high voltage final stage transistor <NUM>, <NUM>, where the interstage impedance matching network <NUM>, <NUM> is configured to match the output impedance (Z<NUM>) of driver stage transistor <NUM>, <NUM> to the input impedance (Z<NUM>) of final stage transistor <NUM>, <NUM>. Because the driver stage transistor <NUM>, <NUM> has a significantly lower output impedance (Z<NUM>) than a conventional driver stage transistor, as discussed above, the interstage impedance matching network <NUM>, <NUM> may be characterized by a significantly reduced impedance transformation ratio, when compared with the impedance transformation ratio than would be required for a conventional two-stage amplifier. For example, for a conventional two-stage power amplifier, a <NUM> V driver stage may require an impedance transformation ratio around <NUM>: <NUM> to <NUM>:<NUM> (e.g., from about <NUM>-<NUM> ohms Z<NUM> to about <NUM> ohms Z<NUM>), while an embodiment of a low voltage driver stage may only require an impedance transformation ratio of less than about <NUM>:<NUM> (e.g., a ratio between about <NUM>:<NUM> and about <NUM>:<NUM>, corresponding to an impedance transformation ratio from about <NUM>-<NUM> ohms Z<NUM> to about <NUM> ohms Z<NUM>). Because a relatively low impedance transformation ratio may be warranted when implementing an embodiment of the inventive subject matter, the circuit topology of the interstage impedance matching network <NUM>, <NUM> may be relatively simple (e.g., fewer impedance matching stages and/or passive components), when compared with an interstage impedance matching network for a conventional amplifier, in which a relatively high impedance transformation is needed. Accordingly, losses incurred through the interstage impedance matching network <NUM>, <NUM> may be significantly reduced (e.g., by <NUM> dB or more) during operation, when compared with the losses incurred through an interstage impedance matching network of a conventional, two-stage amplifier.

Although transistors <NUM>, <NUM> and various elements of the input and interstage impedance matching circuits <NUM>, <NUM> are shown as singular components, the depiction is for the purpose of case of explanation only. Those of skill in the art would understand, based on the description herein, that transistors <NUM>, <NUM> and/or certain elements of the input impedance matching circuit <NUM> and the interstage impedance matching circuit <NUM> each may be implemented as multiple components (e.g., connected in parallel or in series with each other).

The RF amplifier circuit <NUM> and IC <NUM> of <FIG> and <FIG> may be utilized as a single-path amplifier, which receives an RF signal at RF input <NUM>, <NUM>, amplifies the signal through transistors <NUM>, <NUM>, <NUM>, <NUM>, and produces an amplified RF signal at RF output <NUM>, <NUM>. Alternatively, multiple instances of the RF amplifier circuit <NUM> or IC <NUM> may be utilized to provide a multiple-path amplifier, such as a Doherty power amplifier or another type of multi-path amplifier circuit.

For example, <FIG> is a simplified schematic diagram of a Doherty power amplifier <NUM>, which may include two instances of RF amplifier circuit <NUM> or IC <NUM>, in accordance with an example embodiment. Doherty amplifier <NUM> includes an input node <NUM>, an output node <NUM>, a power divider <NUM> (or splitter), a main amplifier path <NUM> with a two-stage main amplifier <NUM> (including driver stage amplifier <NUM> and final stage amplifier <NUM>), a peaking amplifier path <NUM> with a two-stage peaking amplifier <NUM> (including driver stage amplifier <NUM> and final stage amplifier <NUM>), and a combining node <NUM>. A load <NUM> may be coupled to the combining node <NUM> (e.g., through an impedance transformer, not shown) to receive an amplified RF signal from amplifier <NUM>.

Power divider <NUM> is configured to divide the power of an input RF signal received at input node <NUM> into main and peaking portions of the input signal. The main input signal is provided to the main amplifier path <NUM> at power divider output <NUM>, and the peaking input signal is provided to the peaking amplifier path <NUM> at power divider output <NUM>. During operation in a full-power mode when both the main and peaking amplifier paths <NUM>, <NUM> are supplying current to the load <NUM>, the power divider <NUM> divides the input signal power between the amplifier paths <NUM>, <NUM>. For example, the power divider <NUM> may divide the power equally, such that roughly one half of the input signal power is provided to each path <NUM>, <NUM> (e.g., for a symmetric Doherty amplifier configuration). Alternatively, the power divider <NUM> may divide the power unequally (e.g., for an asymmetric Doherty amplifier configuration). Essentially, the power divider <NUM> divides an input RF signal supplied at the input node <NUM>, and the divided signals are separately amplified along the main and peaking amplifier paths <NUM>, <NUM>. The amplified signals are then combined in phase at the combining node <NUM>.

The amplifier <NUM> is designed so that phase coherency between the main and peaking amplifier paths <NUM>, <NUM> is maintained across a frequency band of interest to ensure that the amplified main and peaking signals arrive in phase at the combining node <NUM>, and thus to ensure proper Doherty amplifier operation. More specifically, Doherty amplifier <NUM> has a "non-inverted" load network configuration. In the non-inverted configuration, the input circuit is configured so that an input signal supplied to the peaking amplifier path <NUM> is delayed by <NUM> degrees with respect to the input signal supplied to the main amplifier path <NUM> at the center frequency of operation, f<NUM>, of the amplifier <NUM>. To ensure that the main and peaking input RF signals are supplied to the main and peaking amplifier paths <NUM>, <NUM> with about <NUM> degrees of phase difference, as is fundamental to proper Doherty amplifier operation, phase delay element <NUM> applies about <NUM> degrees of phase delay to the peaking input signal (i.e., the signal produced at power divider output <NUM>). For example, phase delay element <NUM> may include a quarter wave transmission line, or another suitable type of delay element with an electrical length of about <NUM> degrees.

The <NUM> degree phase delay difference at the inputs to the main and peaking amplifier paths <NUM>, <NUM> is applied to compensate for a <NUM> degree phase delay applied to the signal between the output of main amplifier <NUM> and the combining node <NUM>. This is achieved through an additional delay element <NUM> between the output of the main amplifier <NUM> and the combining node <NUM>. The additional delay element <NUM> also may be configured to perform an impedance inversion, and therefore element <NUM> may be referred to as a "phase delay and impedance inversion" element or structure.

Each of the main amplifier path <NUM> and the peaking amplifier path <NUM> includes an input impedance matching network <NUM>, <NUM> (input MNm and input MNp) and a multiple-stage power amplifier <NUM>, <NUM> (e.g., an instance of amplifier <NUM> implemented using amplifier IC <NUM>, <FIG>, <FIG>) coupled in series. The input impedance matching networks <NUM>, <NUM> may be implemented between the power divider outputs <NUM>, <NUM> and the inputs of the main and peaking amplifiers <NUM>, <NUM> (e.g., the gates of the main and peaking driver stage amplifiers <NUM>, <NUM>). In each case, the matching networks <NUM>, <NUM>, may be used to incrementally increase the circuit impedance toward the load impedance and source impedance. All or portions of the input impedance matching networks <NUM>, <NUM> may be integrated with the IC (e.g., IC <NUM>, <FIG>) that includes the main and/or peaking amplifiers <NUM>, <NUM>. For example, the input impedance matching networks <NUM>, <NUM> may be integrally formed with the IC, as is the case with input impedance matching network <NUM> (<FIG>). Alternatively, all or portions of the input impedance matching networks <NUM>, <NUM> may be implemented on a PCB or other substrate to which the IC is mounted.

The multiple-stage power amplifiers <NUM>, <NUM> (e.g., an instance of amplifier <NUM> implemented using amplifier IC <NUM>, <FIG>, <FIG>) are configured to amplify RF signals conducted through the main and peaking amplifier paths <NUM>, <NUM>. According to various embodiments, the main and peaking driver stage amplifiers <NUM>, <NUM> and final stage amplifiers <NUM>, <NUM> each may be implemented, for example, using a field effect transistor (e.g., FETs <NUM>, <NUM>, <FIG>). As discussed in detail above, each driver stage amplifier <NUM>, <NUM>, or more particularly the FET corresponding to each driver stage amplifier <NUM>, <NUM>, may be configured to operate with a relatively low output bias voltage (e.g., drain bias voltage). To provide the relatively-low output bias voltage to the driver stage amplifiers <NUM>, <NUM>, Doherty amplifier <NUM> includes a driver stage low voltage (LV) drain supply <NUM> (e.g., driver stage LV drain supply <NUM>, <FIG>), which provides the output bias voltages to the driver stage amplifiers. As discussed previously, the driver stage LV drain supply <NUM> may be configured to provide a DC bias voltage of less than about <NUM> V to the driver stage amplifiers <NUM>, <NUM>, and in a more particular embodiment, the driver stage LV drain supply <NUM> may be configured to provide a DC bias voltage of about <NUM> V to the driver stage amplifiers <NUM>, <NUM>.

Conversely, each final stage amplifier <NUM>, <NUM>, or more particularly the FET corresponding to each final stage amplifier <NUM>, <NUM>, may be configured to operate with a relatively high output bias voltage (e.g., drain bias voltage). To provide the relatively-high output bias voltage to the final stage amplifiers <NUM>, <NUM>, Doherty amplifier <NUM> includes a final stage high voltage (HV) drain supply <NUM> (e.g., final stage HV drain supply <NUM>, <FIG>), which provides the output bias voltages to the final stage amplifiers. As discussed previously, the final stage HV drain supply <NUM> may be configured to provide a DC bias voltage of <NUM> V or higher to the final stage amplifiers <NUM>, <NUM>, and in a more particular embodiment, the final stage HV drain supply <NUM> may be configured to provide a DC bias voltage of in a range of <NUM>-<NUM> V or higher to the final stage amplifiers <NUM>, <NUM>.

During operation of Doherty amplifier <NUM>, the main amplifier <NUM> is biased to operate in class AB mode, and the peaking amplifier <NUM> is biased to operate in class C mode. At low power levels, where the power of the input signal at node <NUM> is lower than the turn-on threshold level of peaking amplifier <NUM>, the amplifier <NUM> operates in a low-power (or back-off) mode in which the main amplifier <NUM> is the only amplifier supplying current to the load <NUM>. When the power of the input signal exceeds a threshold level of the peaking amplifier <NUM>, the amplifier <NUM> operates in a high-power mode in which the main amplifier <NUM> and the peaking amplifier <NUM> both supply current to the load <NUM>. At this point, the peaking amplifier <NUM> provides active load modulation at combining node <NUM>, allowing the current of the main amplifier <NUM> to continue to increase linearly.

Referring also to <FIG>, in an embodiment, the main amplifier <NUM> may be implemented using a first instance of power amplifier IC <NUM>, where driver stage transistor <NUM> corresponds to driver stage amplifier <NUM>, and final stage transistor <NUM> corresponds to final stage amplifier <NUM>. Similarly, the peaking amplifier <NUM> may be implemented using a second instance of power amplifier IC <NUM>, where driver stage transistor <NUM> corresponds to driver stage amplifier <NUM>, and final stage transistor <NUM> corresponds to final stage amplifier <NUM>.

Actual implementations of Doherty amplifier <NUM>, or portions thereof, may be implemented in discrete, packaged power amplifier modules and devices. For example, <FIG> is a top view of a Doherty amplifier module <NUM>, in accordance with an example embodiment, in which first and second amplifier die <NUM>, <NUM> (e.g., two instances of amplifier die <NUM>, <FIG>) are used to provide the main and peaking amplifiers of a Doherty amplifier.

Doherty amplifier module <NUM> includes a substrate <NUM>, a power splitter <NUM> (e.g., power splitter <NUM>, <FIG>), a main amplifier die <NUM> (e.g., corresponding to main amplifier <NUM>, <FIG>), a peaking amplifier die <NUM> (e.g., corresponding to peaking amplifier <NUM>, <FIG>), a phase delay and impedance inversion structure <NUM> (e.g., phase delay and impedance inversion structure <NUM>, <FIG>), and various other circuit elements, which will be discussed in more detail below. According to an embodiment, with the possible exception of the configurations of the RF output terminals <NUM>, <NUM>, the main amplifier die <NUM> and the peaking amplifier die <NUM> may be structurally identical to each other, and to the amplifier IC <NUM> discussed in detail in conjunction with <FIG>.

The Doherty amplifier module <NUM> may be implemented as a land grid array (LGA) module, for example. Accordingly, the substrate <NUM> has a component mounting surface <NUM> and a land surface (not numbered) that is on an opposite side of the substrate <NUM> from the component mounting surface <NUM>. Conductive landing pads <NUM>-<NUM> of the LGA are exposed at the land surface, and are electrically connected through the substrate <NUM> to overlying conductive features (e.g., contacts <NUM>, <NUM>, <NUM>, and so on). Although module <NUM> is depicted as an LGA module, module <NUM> alternatively may be packaged as a pin grid array module, a quad flat no leads (QFN) module, or another type of package. Either way, the component mounting surface <NUM> and the components mounted to that surface <NUM> optionally may be covered with an encapsulant material to produce a surface-mount device (e.g., power amplifier device <NUM>, <FIG>) that is suitable for incorporation into a larger electrical system (e.g., transceiver module <NUM>, <FIG>). In an alternate embodiment, the components mounted to surface <NUM> could be contained within an air cavity, which is defined by various structures (not illustrated) overlying the mounting surface <NUM>.

The power splitter <NUM>, which is coupled to the mounting surface <NUM>, includes an input terminal <NUM> (e.g., input <NUM>, <FIG>) and two output terminals <NUM>, <NUM> (e.g., outputs <NUM>, <NUM>, <FIG>). The input terminal <NUM> is electrically coupled through wirebonds and conductive contact <NUM> to landing pad <NUM>, which is configured to receive an input RF signal. The output terminals <NUM>, <NUM> are electrically coupled (e.g., through additional wirebonds) to main and peaking amplifier paths, respectively. The power splitter <NUM> is configured to split the power of the input RF signal received through input terminal <NUM> into first and second RF signals (e.g., main and peaking signals), which are produced at the output terminals <NUM>, <NUM>. In addition, the power splitter <NUM> may include one or more phase shift elements configured to impart about a <NUM>-degree phase difference between the first and second RF signals provided at output terminals <NUM>, <NUM> (e.g., to implement the phase shift applied by phase delay element <NUM>, <FIG>).

The first RF signal produced at output terminal <NUM> is amplified through a main amplifier path. The main amplifier path includes an input circuit <NUM>, a main amplifier die <NUM> (e.g., an instance of IC <NUM>, <FIG>), and a phase delay and impedance inversion structure <NUM> (e.g., phase delay and impedance inversion element <NUM>, <FIG>). The input circuit <NUM> is configured to provide proper impedance matching between the first power splitter output <NUM> and the input to the main amplifier die <NUM>. The input circuit <NUM> is electrically coupled (e.g., with wirebonds <NUM>, which correspond to wirebonds <NUM>, <FIG>) to an RF input terminal <NUM> (e.g., RF input <NUM>, <FIG>) of the main amplifier die <NUM>, in order to provide an RF signal for amplification to the main amplifier die <NUM>.

The main amplifier die <NUM> embodies a two-stage amplifier which may be substantially similar to the two-stage amplifier embodied in amplifier IC <NUM>. For the purpose of brevity, the details of amplifier IC <NUM> discussed in conjunction with <FIG> are not repeated here, but they are intended to apply also to main amplifier die <NUM>. Briefly, the electrical components of main amplifier die <NUM> include the RF input terminal <NUM>, an input matching network (e.g., input matching network <NUM>, <FIG>), a driver stage transistor (e.g., driver stage transistor <NUM>, <FIG>), an interstage matching network (e.g., interstage matching network <NUM>, <FIG>), an output or final stage transistor (e.g., final stage transistor <NUM>, <FIG>), and an RF output terminal <NUM> (e.g., RF output terminal <NUM>, <FIG>). The driver and final stage transistors are coupled in series between the input and output terminals <NUM>, <NUM>. The driver stage transistor is configured to apply a relatively low gain to the main signal, and the final stage transistor is configured to apply a relatively high gain to the main signal after preliminary amplification by the driver stage transistor.

According to an embodiment, the main amplifier die <NUM> also includes a first DC bias circuit <NUM> (e.g., bias circuit <NUM>, <FIG>), which receives a relatively low bias voltage through a conductive landing pad <NUM> and a bondpad on the die <NUM> (e.g., bondpad <NUM>, <FIG>). The first DC bias circuit <NUM> conveys the relatively low DC bias voltage from the landing pad <NUM> to the output (e.g., drain terminal) of the driver stage transistor, as discussed in detail above in conjunction with <FIG>.

A second DC bias circuit <NUM> (e.g., bias circuit <NUM>, <FIG>) is implemented off chip, in an embodiment, and the second DC bias circuit <NUM> receives a relatively high DC bias voltage through a landing pad <NUM>. The second DC bias circuit <NUM> may include a conductive contact <NUM> (e.g., contact <NUM>, <FIG>) on the mounting surface <NUM>, and wirebonds <NUM>, which electrically couple the contact <NUM> with the RF output terminal <NUM> (thus electrically connecting landing pad <NUM> and the output of the final stage transistor of the main amplifier die <NUM>). The second DC bias circuit <NUM> conveys the relatively high bias voltage from the landing pad <NUM> to the output (e.g., drain terminal) of the final stage transistor, as discussed in detail above in conjunction with <FIG>. Besides the drain bias circuits <NUM>, <NUM>, module <NUM> also may include additional main amplifier bias circuits to provide gate bias voltages to the driver and final stage transistors of the main amplifier die <NUM>.

As discussed in conjunction with <FIG>, each of the first DC bias circuit <NUM> and the second DC bias circuit <NUM> may be configured as a shunt-L circuit, where each includes an inductive element and a capacitor connected in series between a transistor output and a ground reference voltage, with an intermediate node or contact between each inductor/capacitor pair. The inductor/capacitor pair associated with DC bias circuit <NUM> may be integrally formed with die <NUM>, and the inductor/capacitor pair associated with DC bias circuit <NUM> may include wirebonds <NUM>, contact <NUM>, and capacitor <NUM>. A first terminal (or electrode) of capacitor <NUM> is coupled to contact <NUM>, and a second terminal of capacitor <NUM> may be coupled to a ground reference through landing pad <NUM>.

An amplified main signal is produced by the main amplifier die <NUM> at the RF output terminal <NUM>. The amplified main signal is conveyed through the phase delay and impedance inversion structure <NUM> to the RF output terminal <NUM> of the peaking amplifier die <NUM>. More specifically, the phase delay and impedance inversion structure <NUM> includes a series combination of a first wirebond array <NUM>, an inverter line <NUM> connected to the substrate <NUM>, and a second wirebond array <NUM>. The phase delay and impedance inversion structure <NUM> has an electrical length of about <NUM> degrees, in an embodiment.

As will be discussed in more detail below, the output terminal <NUM> of the peaking amplifier die <NUM> functions as the combining node <NUM> (e.g., combining node <NUM>, <FIG>) of the Doherty amplifier, and the phase delay and impedance inversion structure <NUM> functions to phase align the amplified RF main signal with an amplified RF peaking signal produced by the peaking amplifier die <NUM>.

Moving back to the power splitter <NUM>, the second RF signal produced at output terminal <NUM> is amplified through the peaking amplifier path. The peaking amplifier path includes an input circuit <NUM>, and a peaking amplifier die <NUM> (e.g., an instance of IC <NUM>, <FIG>). The input circuit <NUM> is configured to provide proper impedance matching between the second power splitter output <NUM> and the input to the peaking amplifier die <NUM>. The input circuit <NUM> is electrically coupled (e.g., with wirebonds <NUM>, which correspond to wirebonds <NUM>, <FIG>) to an RF input terminal <NUM> (e.g., RF input <NUM>, <FIG>) of the peaking amplifier die <NUM>, in order to provide an RF signal for amplification to the peaking amplifier die <NUM>.

The peaking amplifier die <NUM> embodies a two-stage amplifier, which may be substantially similar to the two-stage amplifier embodied in amplifier IC <NUM>. For the purpose of brevity, the details of amplifier IC <NUM> discussed in conjunction with <FIG> are not repeated here, but they are intended to apply also to peaking amplifier die <NUM>. Briefly, the electrical components of peaking amplifier die <NUM> include the RF input terminal <NUM>, an input matching network (e.g., input matching network <NUM>, <FIG>), a driver stage transistor (e.g., driver stage transistor <NUM>, <FIG>), an interstage matching network (e.g., interstage matching network <NUM>, <FIG>), an output or final stage transistor (e.g., final stage transistor <NUM>, <FIG>), and an RF output terminal <NUM> (e.g., output/drain terminal <NUM>, <FIG>).

The driver and final stage transistors are coupled in series between the input and output terminals <NUM>, <NUM>. The driver stage transistor is configured to apply a relatively low gain to the peaking signal, and the final stage transistor is configured to apply a relatively high gain to the peaking signal after preliminary amplification by the driver stage transistor.

According to an embodiment, the peaking amplifier die <NUM> also includes a first DC bias circuit <NUM> (e.g., bias circuit <NUM>, <FIG>), which receives a relatively low bias voltage through a conductive landing pad <NUM> and a bondpad on the die <NUM> (e.g., bondpad <NUM>, <FIG>). The first DC bias circuit <NUM> conveys the relatively low DC bias voltage from the landing pad <NUM> to the output (e.g., drain terminal) of the driver stage transistor, as discussed in detail above in conjunction with <FIG>.

A second DC bias circuit <NUM> (e.g., bias circuit <NUM>, <FIG>) is implemented off chip, in an embodiment, and the second DC bias circuit <NUM> receives a relatively high DC bias voltage through a landing pad <NUM>. The second DC bias circuit <NUM> may include a conductive contact <NUM> (e.g., contact <NUM>, <FIG>) on the mounting surface <NUM>, and wirebonds <NUM>, which electrically couple the contact <NUM> with the RF output terminal <NUM> (thus electrically connecting landing pad <NUM> and the output of the final stage transistor of the peaking amplifier die <NUM>). The second DC bias circuit <NUM> conveys the relatively high bias voltage from the landing pad <NUM> to the output (e.g., drain terminal) of the final stage transistor, as discussed in detail above in conjunction with <FIG>. Besides the drain bias circuits <NUM>, <NUM>, module <NUM> also may include additional peaking amplifier bias circuits to provide gate bias voltages to the driver and final stage transistors of the peaking amplifier die <NUM>.

An amplified peaking signal is produced by the peaking amplifier die <NUM> at the RF output terminal <NUM>. In an embodiment, and as mentioned above, the RF output terminal <NUM> also receives the amplified main signal through the phase delay and impedance inversion structure <NUM>, and the RF output terminal <NUM> functions as a combining node <NUM> (e.g., combining node <NUM>, <FIG>) at which the amplified main signal is combined, in phase, with the amplified peaking signal.

According to an embodiment, the RF output terminal <NUM> (and thus combining node <NUM>) is electrically coupled to a conductive output transformer line <NUM> at the mounting surface <NUM> with wirebond array <NUM>. An output impedance matching network <NUM> and/or a decoupling capacitor <NUM> may be coupled along output transformer line <NUM>, in an embodiment. The output impedance matching network <NUM> functions to present the proper load impedance to combining node <NUM>. Although the detail is not shown in <FIG>, the output impedance matching network <NUM> may include various discrete and/or integrated components (e.g., capacitors, inductors, and/or resistors) to provide the desired impedance matching. Ultimately, the output transformer line <NUM> is electrically coupled through the substrate <NUM> to conductive landing pad <NUM>. Landing pad <NUM> functions as the RF output node for the module <NUM>.

An embodiment of a module (e.g., Doherty amplifier module <NUM>, <FIG>) or another device or module that includes one or more instances of amplifier <NUM> and/or amplifier IC <NUM> may be further integrated into a larger electrical system. For example the Doherty amplifier module <NUM> (or another amplifier device that includes an embodiment of an amplifier die) may be included in a transmitter lineup of an RF transmitter or an RF transceiver.

For example, <FIG> is a perspective view of a transceiver module <NUM>, in accordance with an example embodiment. Essentially, the transceiver module <NUM> houses a transmitter lineup and a receiver lineup. The components of transceiver module <NUM> are mounted on (or coupled to) a system substrate <NUM>, which may be, for example, a multi-layer PCB or other type of substrate.

The transmitter lineup includes an RF transmit (TX) input connector <NUM>, a pre-amplifier device <NUM>, a power amplifier device <NUM>, a duplexer <NUM> (e.g., a circulator, in the illustrated embodiment), and an RF transmit-out/receive-in (TX out/RX in) connector <NUM> coupled in series. The RF transmit input connector <NUM> is configured to be coupled to an external RF signal source, such as a transmit processor (not illustrated), which produces an analog, modulated RF transmit signal that is to be amplified and transmitted to a remote receiver. The RF transmit input connector <NUM> receives the RF transmit signal from the RF signal source, and conveys the signal to a first substrate transmission line between the RF transmit input connector <NUM> and the pre-amplifier device <NUM>. The pre-amplifier device <NUM> functions as a first amplification stage, which applies a first gain to the RF transmit signal. The pre-amplified RF transmit signal is then conveyed through a second substrate transmission line between the pre-amplifier device <NUM> and the power amplifier device <NUM>.

For example, the power amplifier device <NUM> may be a Doherty amplifier module (e.g., Doherty amplifier module <NUM>, <FIG>), although the power amplifier device <NUM> alternatively may include a single-path amplifier, or another type of amplifier. In any event, the power amplifier device <NUM> includes at least one amplifier with a low voltage driver stage amplifier (e.g., driver stage transistor <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>, <FIG>) and a high voltage final stage amplifier (e.g., final stage transistor <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>, <FIG>).

The power amplifier device <NUM> functions as a final amplification stage, which applies additional gain to the RF transmit signal, and the amplified RF transmit signal is then conveyed through a third substrate transmission line between the power amplifier device <NUM> and the duplexer <NUM>. The duplexer <NUM> is used to isolate the transmitter and receiver. In various embodiments, the duplexer <NUM> may include a circulator (as illustrated), an active transmit/receive switch, or another type of duplexer. In any event, the duplexer <NUM> conveys the amplified RF transmit signal to a fourth substrate transmission line between the duplexer <NUM> and the RF transmit-out/receive-in connector <NUM>.

The RF transmit-out/receive-in connector <NUM> is configured to be coupled to a load, such as an antenna, which functions to communicate the amplified RF transmit signal to the remote receiver (e.g., to radiate the amplified RF transmit signal over the air interface). The RF transmit-out/receive-in connector <NUM> also functions to receive an RF receive signal from the load (e.g., from an antenna, and ultimately from a remote transmitter), and to convey the RF receive signal to the receiver lineup.

The receiver lineup includes the RF transmit-out/receive-in connector <NUM>, the duplexer <NUM>, a low noise amplifier (LNA) device <NUM>, and an RF receive (RX) output connector <NUM> coupled in series. Upon receiving an RF receive signal from the load (e.g., an antenna), the RF transmit-out/receive-in connector <NUM> conveys the RF receive signal to the duplexer <NUM> through the fourth substrate transmission line. The duplexer <NUM> then conveys the RF receive signal over a fifth substrate transmission line to the LNA device <NUM>. The LNA device <NUM> amplifies the RF receive signal, and conveys the amplified RF receive signal to a sixth substrate transmission line between the LNA device <NUM> and the RF receive output connector <NUM>. The RF receive output connector <NUM> is configured to be coupled to a receive processor (not illustrated), which processes (e.g., demodulates, converts to digital, and otherwise processes) the RF receive signal.

In addition to the above-described circuitry, the transceiver module <NUM> also includes a low voltage power supply connector <NUM>, a high voltage power supply connector <NUM>, and potentially additional power supply connectors (not discussed below). The low voltage power supply connector <NUM> and the high voltage power supply connector <NUM> are configured to be coupled to a low voltage power supply (e.g., driver stage LV drain supply <NUM>, <NUM>, <FIG>, <FIG>) and a high voltage power supply (e.g., final stage HV drain supply <NUM>, <NUM>, <FIG>, <FIG>), respectively. As described previously, the low voltage power supply (not illustrated) may supply a relatively low DC voltage (e.g., less than <NUM> V, such as <NUM> V, or another relatively low voltage), and the high voltage power supply (not illustrated) may supply a relatively high DC voltage (e.g., <NUM>-<NUM> V, or another relatively high voltage).

The low voltage power supply connector <NUM> is coupled to low voltage substrate conductors <NUM>, which conduct the low voltage DC power received through the low voltage power supply connector <NUM> to the pre-amplifier <NUM>, the amplifier module <NUM>, and the LNA <NUM>, in an embodiment. Essentially, the low voltage substrate conductors <NUM> form a portion of a conductive path between the low voltage power supply connector <NUM> and the pre-amplifier <NUM>, the amplifier module <NUM> (and more specifically, the outputs/drains of the driver stage amplifier transistor(s) included in the amplifier module <NUM>), and the LNA <NUM>. Accordingly, the transceiver module <NUM> is configured so that the pre-amplifier <NUM>, the amplifier module <NUM>, and the LNA <NUM> may utilize the same low voltage power supply for operation. When duplexer <NUM> is implemented as an active device (e.g., an active transmit/receive switch), duplexer <NUM> also may receive and utilize the low voltage DC power for its operations. In the amplifier module <NUM> (e.g., amplifier module <NUM>, <FIG>), contacts coupled to the low voltage substrate conductors <NUM> (e.g., contacts <NUM>, <NUM>, <FIG>) convey the low voltage DC power through bias circuits (e.g., bias circuits <NUM>, <NUM>, <FIG>) to the output/drain terminals (e.g., terminals <NUM>, <NUM>, <FIG>, <FIG>, not numbered in <FIG>) of the driver stage transistors (e.g., transistors <NUM>, <NUM>, <FIG>, <FIG>, not numbered in <FIG>).

The high voltage power supply connector <NUM> is coupled to high voltage substrate conductors <NUM>, which conduct the high voltage DC power received through the high voltage power supply connector <NUM> to the amplifier module <NUM>. Essentially, the high voltage substrate conductors <NUM> form a portion of a conductive path between the high voltage power supply connector <NUM> and the amplifier module <NUM> (and more specifically, the outputs/drains of the final stage amplifier transistor(s) included in the amplifier module <NUM>). In the amplifier module <NUM> (e.g., amplifier module <NUM>, <FIG>), contacts coupled to the high voltage substrate conductors <NUM> (e.g., contacts <NUM>, <NUM>, <FIG>) convey the high voltage DC power through bias circuits (e.g., bias circuits <NUM>, <NUM>, <FIG>) to the output/drain terminals (e.g., terminals <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>, <FIG>) of the final stage transistors (e.g., transistors <NUM>, <NUM>, <FIG>, <FIG>, not numbered in <FIG>).

As indicated above, embodiments of the inventive subject matter may leverage the use of a single low voltage power supply (e.g., a standardly available <NUM> V supply) to power multiple RF subsystems of an RF transmitter or transceiver (e.g., pre-amplifier module <NUM>, power amplifier module <NUM>, duplexer <NUM>, and/or a LNA module <NUM>). Accordingly, system costs associated with unique power supplies for some or all of these subsystems may be avoided.

<FIG> is a flowchart of a method for operating an amplifier with a low voltage driver stage amplifier and a high voltage final stage amplifier, in accordance with an example embodiment. The method may be performed, for example, using various embodiments of a power amplifier (e.g., amplifiers <NUM>, <NUM>, <FIG>, <FIG>), a Doherty amplifier or an amplifier module (e.g., amplifier <NUM> and module <NUM>, <FIG>, <FIG>), and/or a transmitter or transceiver (e.g., as embodied in transceiver module <NUM>, <FIG>).

The method may begin, in step <NUM>, by providing a relatively low DC voltage (e.g., under <NUM> V, such as about <NUM> V) to bias the output(s) (e.g., drain terminal(s)) of the driver amplifier stage(s)/transistor(s) (e.g., stages/transistors <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>) of a multi-stage power amplifier or amplifier module (e.g., amplifier <NUM>, <NUM>, <NUM>, or module <NUM>, <NUM>, <FIG>, <FIG>, <FIG>). Step <NUM> also may include providing the relatively low DC voltage to additional components of a transmitter or transceiver system (e.g., transceiver module <NUM>, <FIG>). For example, as discussed previously, the relatively low DC voltage may be provided also to a pre-amplifier (e.g., pre-amplifier module <NUM>, <FIG>), a duplexer, an LNA (e.g., LNA <NUM>, <FIG>), and/or other system components that are configured to operate using the same relatively low DC voltage that is supplied to the driver amplifier stage(s)/transistor(s). When the additional components are included in a single module (e.g., transceiver module <NUM>, <FIG>), for example, a first DC voltage supply configured to supply the relatively low DC voltage may be coupled to a first power supply connector of the module (e.g., connector <NUM>, <FIG>), and conductors (e.g., conductors <NUM>, <FIG>) may be used to convey the DC voltage to an amplifier module (e.g., module <NUM>, <FIG>) that includes the driver amplifier stage(s)/transistor(s) and to the additional components.

In step <NUM>, a relatively high DC voltage (e.g., about <NUM>-<NUM> V or higher) is provided to bias the output(s) (e.g., drain terminal(s)) of the final amplifier stage(s) )/transistor(s) (e.g., stages/transistors <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>) of a multi-stage power amplifier or amplifier module (e.g., amplifier <NUM>, <NUM>, <NUM>, or module <NUM>, <NUM>, <FIG>, <FIG>, <FIG>). When the final amplifier stage(s) )/transistor(s) are included in a module (e.g., transceiver module <NUM>, <FIG>), for example, a second DC voltage supply configured to supply the relatively high DC voltage may be coupled to a second power supply connector of the module (e.g., connector <NUM>, <FIG>), and conductors (e.g., conductors <NUM>, <FIG>) may be used to convey the DC voltage to an amplifier module (e.g., module <NUM>, <FIG>) that includes the final amplifier stage(s)/transistor(s). Additional bias voltages (e.g., input/gate bias voltages) also may be provided through additional connector(s) and conductor(s).

In step <NUM>, an RF signal is then provided (e.g., through input <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <FIG>, <FIG>, <FIG>) to the pre-amplifier (e.g., pre-amplifier <NUM>, <FIG>), when included, and to the power amplifier (e.g., amplifier <NUM>, <NUM>, <NUM>, or module <NUM>, <NUM>, <FIG>, <FIG>, <FIG>), which proceed to amplify the received RF signal. In step <NUM>, the amplified RF signal is then provided to a load (e.g., to an antenna or other load), and the method ends.

An amplifier includes a driver stage amplifier transistor and a final stage amplifier transistor, which are integrated in a semiconductor die. The driver stage amplifier transistor has a driver stage input, a driver stage output, and an output impedance, and the driver stage amplifier transistor is configured to operate using a first bias voltage at the driver stage output. The final stage amplifier transistor has a final stage input, a final stage output, and an input impedance. The final stage input is electrically coupled to the driver stage output. The final stage amplifier transistor is configured to operate using a second bias voltage at the final stage output, and the second bias voltage is at least twice as large as the first bias voltage.

The preceding detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.

The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms "first", "second" and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.

As used herein, a "node" means any internal or external reference point, connection point, junction, signal line, conductive element, or the like, at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes may be realized by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even though received or output at a common node).

Claim 1:
An amplifier (<NUM>, <NUM>) comprising:
a driver stage amplifier transistor (<NUM>, <NUM>) integrated in a semiconductor die (<NUM>) and having a driver stage input terminal (<NUM>, <NUM>), a driver stage output terminal (<NUM>, <NUM>), and an output impedance (z1), wherein the driver stage amplifier transistor is configured to operate using a first bias voltage at the driver stage output terminal (<NUM>, <NUM>); and
a final stage amplifier transistor (<NUM>, <NUM>) integrated in the semiconductor die (<NUM>) and having a final stage input terminal (<NUM>, <NUM>), a final stage output terminal (<NUM>, <NUM>), and an input impedance (z2), wherein the final stage input terminal (<NUM>, <NUM>) is electrically coupled to the driver stage output terminal (<NUM>, <NUM>), and the final stage amplifier transistor (<NUM>, <NUM>) is configured to operate using a second bias voltage at the final stage output (<NUM>, <NUM>), and the second bias voltage is at least twice as large as the first bias voltage, wherein:
a ratio of the output impedance (z1) of the driver stage amplifier transistor (<NUM>, <NUM>) to the input impedance (z2) of the final stage amplifier transistor (<NUM>, <NUM>) input is less than <NUM>:<NUM>; and
the amplifier further includes an interstage impedance matching circuit (<NUM>, <NUM>) electrically coupled between the driver stage output terminal (<NUM>, <NUM>) and the final stage input terminal (<NUM>, <NUM>), wherein the interstage impedance matching circuit (<NUM>, <NUM>) is configured to perform an impedance transformation from the output impedance (z1) of the driver stage amplifier transistor (<NUM>, <NUM>) to the input impedance of the final stage amplifier transistor (<NUM>, <NUM>).