Patent Description:
The drift region in a MOSFET is a relatively high resistivity layer grown by epitaxial (epi) technology, and is designed to achieve particular values for electrical characteristics such as breakdown voltage and on-state resistance. For medium voltage (e.g., <NUM> V) to high voltage (e.g., <NUM> V) devices, the major portion of the on-state resistance comes from drift region resistance. For example, for a <NUM> V device, an analysis shows that <NUM> percent of the total on-state resistance is due to drift region resistance, while only six percent is due to channel resistance, five percent is due to package resistance, and one percent is due to substrate resistance. Consequently, reducing drift region resistance can make a significant contribution to reducing the total on-state resistance.

However, while a reduction in resistivity in the drift region of the epitaxial layer can positively affect RDS(on), conventionally such a reduction means that breakdown voltage would be expected to be negatively affected as noted above.

Accordingly, a semiconductor device (e.g., MOSFET) that provides reduced resistivity in the drift region and hence lower on-state resistance, but does not negatively impact breakdown voltage, would be valuable.

US Patent <CIT> discloses a field effect-controllable semiconductor component having a drain zone of the first conductivity type and also at least one gate electrode which is composed of polycrystalline silicon and is insulated from the drain zone. A source region of the second conductivity type is introduced in the drain zone. In addition, there is formed in the drain zone a trench structure, which reach from the surface of the epitaxial layer down into the substrate layer. An additional field plate made of polysilicon and embedded in an oxide layer is introduced in the trench structure. The thickness of the oxide surrounding the field plate increases down in a direction towards the drain.

<CIT> discloses a semiconductor device that contains a vertical MOS transistor with instances of a vertical RESURF trench on opposite sides of a vertical drift region. The vertical RESURF trench contains a dielectric trench liner on sidewalls, and a lower field plate and an upper field plate above the lower field plate. The dielectric trench liner between the lower field plate and the vertical drift region is thicker than between the upper field plate and the vertical drift region. A gate is disposed over the vertical drift region and is separate from the upper field plate. The upper field plate and the lower field plate are electrically coupled to a source electrode of the vertical MOS transistor.

Published International patent application <CIT> discloses a power semiconductor device that includes a drift region of first conductivity type therein and first and second trenches in the substrate. The first and second trenches have first and second opposing sidewalls, respectively, that define a mesa therebetween into which the drift region extends. An electrically insulating region having tapered sidewalls is also provided in each of the trenches. The tapered thickness of each of the electrically insulating regions enhances the degree of uniformity of the electric field along the sidewalls of the trenches and in the mesa and allows the power device to support higher blocking voltages despite a high concentration of dopants in the drift region.

Published US patent application <CIT> discloses a semiconductor device having a semiconductor layer having an opening formed therein, a first insulating layer disposed on a bottom surface of the opening and on a sidewall of the opening, a second insulating layer disposed on the sidewall of the opening above the first insulating layer, the second insulating layer being thinner than the first insulating layer, a field plate electrode disposed on the first insulating layer and the second insulating layer and having a recess extending from an upper surface of the field plate electrode towards the bottom surface of the opening, and a first layer disposed in the recess and including a material that is different from a material of the field plate electrode.

Published German patent application <CIT> discloses a MOSFET having a semiconducting body with first and second main surfaces, a device structure comprising a body, a source and a gate are formed on the first main surface. The MOSFET also comprises a drain region formed on the second main surface. The MOSFET further comprises a drift region extending between first main surface and the drain region. Furthermore, auxiliary electrodes connected to a source electrode are formed inside trenches extending through the drift region and reaching the drain region. A dielectric layer is provided in the aforementioned trenches between said auxiliary electrodes and the drift region. The dielectric layer has a non-uniform thickness. The drift region comprises a highly doped region at the first main surface and a lowly doped region underneath said highly doped region.

in overview, embodiments according to the present invention pertain to semiconductor devices, such as but not limited to power MOSFETs including but not limited to dual trench MOSFETs, that have non-uniform oxide layers lining the trenches that are connected to the source electrode. Such devices will have lower resistivity in the drift region and lower on-state resistance but will have the same or about the same breakdown voltage as conventional but otherwise comparable MOSFETs.

More specifically, in an embodiment of the invention as defined in claim <NUM>, a semiconductor device includes an epitaxial layer disposed adjacent to the substrate layer and trenches formed in the epitaxial layer. An oxide layer lines the sidewalls of each of the trenches. The trenches are filled with a material such as polysilicon that is connected to a source electrode. The oxide layer has a non-uniform thickness along the sidewalls of each trench. The thickness of the oxide layer at a first distance from the bottom of a trench is less than the thickness of the oxide layer at the bottom, and the thickness of the oxide layer at a second distance from the bottom (greater than the first distance) is less than the thickness of the oxide layer at the first distance. In embodiments according to the invention, the oxide layer is thinnest at or near the top of the trench, and is thicker toward the bottom of the trench.

In the embodiment, the epitaxial layer has a non-uniform dopant concentration. The dopant concentration varies according to the thickness of the oxide layer. The dopant concentration is higher where the oxide layer is thinner and lower where the oxide layer is thicker. Thus, in the above example, the dopant concentration at the first distance is less than the dopant concentration at the second distance.

Non-uniform oxide layer thicknesses in the trenches in embodiments according to the present invention provide the opportunity to improve charge balance in the drift region in the epitaxial layer by tailoring the dopant concentration in the epitaxial layer according to the thickness of the oxide layer, resulting in reduced (improved) on-state resistance at the same breakdown voltage.

These and other objects and advantages of embodiments according to the present invention will be recognized by one skilled in the art after having read the following detailed description, which are illustrated in the various drawing figures.

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Like numbers denote like elements throughout the drawings and specification. The figures may not be drawn to scale.

In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one skilled in the art that the present invention may be practiced without these specific details or with equivalents thereof. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations for fabricating semiconductor devices. These descriptions and representations are the means used by those skilled in the art of semiconductor device fabrication to most effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present application, discussions utilizing terms such as "forming," "performing," "producing," "depositing," "etching," "adding," "removing" or the like, refer to actions and processes (e.g., process <NUM> of <FIG>) of semiconductor device fabrication.

It is understood that the figures are not necessarily drawn to scale, and only portions of the devices and structures depicted, as well as the various layers that form those structures, are shown. For simplicity of discussion and illustration, the process is described for one or two devices or structures, although in actuality more than one or two devices or structures may be formed.

The term "channel" is used herein in the accepted manner. That is, current moves within a MOSFET in a channel, from the source connection to the drain connection. A channel can be made of either n-type or p-type semiconductor material; accordingly, a MOSFET is specified as either an n-channel or p-channel device. The disclosure is presented in the context of an n-channel device; however, embodiments according to the present invention are not so limited. That is, the features described herein can be utilized in a p-channel device. The disclosure can be readily mapped to a p-channel device by substituting, in the discussion, n-type dopant and materials for corresponding p-type dopant and materials, and vice versa.

As used herein, the letter "n" refers to an n-type dopant and the letter "p" refers to a p-type dopant. A plus sign "+" or a minus sign "-" is used to represent, respectively, a relatively high or relatively low concentration of the dopant. For example, "n+" would indicate a higher concentration of n-type dopant than "n," which would indicate a higher concentration of n-type dopant than "n-.

In general, the term "trench" is used in the art to refer to an empty trench that is formed in, for example, an epitaxial (epi) layer, and is also often used to refer to a trench that is partially or completely filled with one or more materials. The term "trench structure" may be used herein at times to distinguish a filled or partially filled trench from an empty or unfilled trench. At other times, the manner in which these terms are being used will be evident from the context of the surrounding discussion.

<FIG> is an example of a cross-sectional view of a portion of a semiconductor device <NUM>. In the example of <FIG>, the device <NUM> includes an epitaxial layer <NUM> (e.g., an n-type epitaxial layer) formed over and adjacent to a substrate layer <NUM>. The device <NUM> also includes a first trench structure <NUM> formed in a first trench <NUM> that is formed in the epitaxial layer <NUM>, and also includes a second trench structure <NUM> formed in a second trench <NUM> formed in the epitaxial layer.

The trench <NUM> is lined with an oxide layer <NUM>, and the trench <NUM> is lined with an oxide layer <NUM>. The oxide layers <NUM> and <NUM> may be referred to as shield oxides. The oxide layer <NUM> lines the bottom and sidewalls of the trench <NUM>, and the oxide layer <NUM> lines the bottom and sidewalls of the trench <NUM>.

In the <FIG>, the volumes within the oxide layers <NUM> and <NUM> are filled with material to form the trench structures <NUM> and <NUM>, respectively. The material is a polysilicon material. The material in the trench structures <NUM> and <NUM> is connected to a source electrode <NUM>. Accordingly, the trench structures <NUM> and <NUM> may be referred to as source trenches.

Significantly, the oxide layers <NUM> and <NUM> have non-uniform thicknesses along the sidewalls of the trenches <NUM> and <NUM>. For example, in the <FIG>, the thickness x1 of the oxide layer <NUM> at a first distance d1 from the bottom of the trench structure <NUM> is less than the thickness of the oxide layer at the bottom, and the thickness x2 of the oxide layer at a second distance d2 from the bottom (the second distance greater than the first distance) is less than the thickness of the oxide layer at the first distance. The thickness of the oxide layer <NUM> can be similarly described.

In the <FIG>, the oxide layers <NUM> and <NUM> get thinner as a function of distance from the bottoms of the trenches <NUM> and <NUM>. In other words, in the <FIG>, the thickness of the oxide layer <NUM> is not constant or uniform between the distance d1 and the distance d2 or from d2 to the top of the trench <NUM>. The thickness of the oxide layer <NUM> can be similarly described.

The thickness of the oxide layer <NUM> decreases linearly between the distances d1 and d2. That is, the thickness of the oxide layer <NUM> can essentially be represented using a straight line drawn from d1 to d2. The thickness of the oxide layer <NUM> can continue to decrease linearly beyond the distance d2 as shown in the example of <FIG>. The thickness of the oxide layer <NUM> can be similarly described.

However, the thicknesses of the oxide layers do not necessarily have to decrease linearly as the distance from the bottom of the trench increases. The oxide layers can have different profiles (cross-sections). In general, the oxide layers are thinnest at or near the top of a trench, and are thicker toward the bottom of the trench.

In the example of <FIG>, a structure or device is formed between (adjacent to) the trench structures <NUM> and <NUM>. The structure/device includes a trench <NUM> filled with material (e.g., oxide and polysilicon), body regions <NUM> and <NUM> (e.g., p-type body regions), and source regions <NUM> and <NUM> (e.g., n-type source regions). In an embodiment, the material in the trench <NUM> is shielded (insulated) from the source electrode <NUM> by a dielectric region <NUM>. While a particular type of structure/device between the trench structures <NUM> and <NUM> is shown in <FIG> and in other figures below (e.g., <FIG>, <FIG>, and <FIG>), structure/devices are not so limited. For example, the structure/device may be a type of Schottky device or insulated-gate bipolar transistor (IGBT) instead of the type of structure/device shown in the figures.

In embodiments according to the present invention, the design of the epitaxial layer <NUM> is tailored to complement the non-uniform thicknesses of the oxide layers <NUM> and <NUM>. More specifically, the epitaxial layer <NUM> has a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layers. Thus, non-uniform oxide layer thicknesses in the trenches in embodiments according to the present invention provide the opportunity to tune the dopant concentration and improve charge balance in the drift region (the region in the epitaxial layer between the trench structures <NUM> and <NUM> and under the body regions <NUM> and <NUM>), in order to reduce resistivity in the drift region and thereby reduce (and improve) the total on-state resistance. Importantly, in embodiments according to the present invention, on-state resistance can be reduced without affecting breakdown voltage.

<FIG> is an example of a cross-sectional view of a portion of a semiconductor device <NUM> in an embodiment according to the present invention, in which the dopant concentration varies according to the thickness of the oxide layers. In the example of <FIG>, the epitaxial layer <NUM> includes three sub-layers or regions <NUM>, <NUM>, and <NUM>. In an embodiment, each of the sub-layers <NUM>, <NUM>, and <NUM> extend across the entire distance between the adjacent trench structures <NUM> and <NUM>.

In the example of <FIG>. , the region <NUM> corresponds to (neighbors, or is adjacent to) the bottom portions of the trench structures <NUM> and <NUM>, the region <NUM> corresponds to the distance d1, and the region <NUM> corresponds to the distance d2. The term "corresponds to," as used above and hereinafter, means that the region <NUM> overlaps the bottom of the trench structures <NUM> and <NUM>, the region <NUM> overlaps portions of the oxide layers <NUM> and <NUM> that have a thickness that is greater than the thickness x2, and that the region <NUM> overlaps portions of the oxide layers <NUM> and <NUM> that have a thickness that is less than the thickness x1.

In the example of <FIG>, the dopant concentration (e.g., n-) in the region <NUM> is less than the dopant concentration (e.g., n) in the region <NUM>, and the dopant concentration in the region <NUM> is less than the dopant concentration (e.g., n+) in the region <NUM>. However, examples useful for understanding the invention are not so limited. That is, the dopant concentration does not necessarily have to decrease with depth as just described. In general, the dopant concentration is higher where the oxide layer is thinner, and lower where the oxide layer is thicker. Thus, the relative dopant concentrations in different regions of the epitaxial layer <NUM> can be less than, equal to, or greater than one another depending on the corresponding thickness of the oxide layers <NUM> and <NUM>. While three dopant concentration levels/regions are described in <FIG> and in other figures below (e.g., <FIG> and <FIG>), the present invention is not so limited; there can be more than three dopant concentration levels/regions.

According to an analysis of a conventional device versus the device <NUM>, the conventional device has a breakdown voltage of <NUM> V and an on-state resistance of <NUM> micro-ohms (mΩ), while the device <NUM> has a breakdown voltage of <NUM> V and an on-state resistance of <NUM> mΩ. Thus, embodiments according to the invention can improve on-state resistance by <NUM> percent with the same breakdown voltage relative to a conventional device.

<FIG> is an example of a cross-sectional view of a portion of a semiconductor device <NUM> in an embodiment according to the present invention. In the example of <FIG>, the oxide layers <NUM> and <NUM> are stepped. More specifically, for example, the oxide layer <NUM> has a uniform first thickness x1 from a point A that is above the bottom of the trench structure <NUM> to a first distance d1, a uniform second thickness x2 from the distance d1 to a second distance d2, a uniform third thickness x3 from the distance d2 to a third distance d3, and a uniform fourth thickness x4 from the distance d3 to the top surface of the trench structure <NUM>, where x1 is greater than x2, which is greater than x3, which is greater than x4. There can be more than the number of steps shown in <FIG>. The distances d1, d2, d3, and d4 may or may not be equal. The thickness of the oxide layer <NUM> can be similarly described.

Like the example of <FIG>, the device <NUM> has non-uniform dopant concentrations in the epitaxial layer as shown in <FIG>.

Features of the devices of <FIG>, <FIG>, and <FIG> can be combined. Specifically, with reference to <FIG>, one, some or all of the uniformly thick portions of the oxide layers <NUM> and <NUM> can instead be decreasing (e.g., decreasing linearly) with distance from the bottom of the trench structure <NUM>. For example, the thickness of the portion of the oxide layer <NUM> across the length of the distance d1 can decrease as distance from the bottom increases; for example, the thickness in that portion can decrease linearly from x1 to x2 across the distance d1. Similarly, the thickness of each of the other portions of the oxide layer <NUM> either can be uniform or can decrease (e.g., decrease linearly) as the distance from the bottom increases. The thickness of the oxide layer <NUM> can be similarly described.

Also, the rate of change (e.g., the slope) of one portion can be different from that of another portion. For example, the thickness of the oxide layer <NUM> may decrease across the distance d2, and also may decrease linearly across the distance d3, but the rate at which the thickness decreases across d2 may be different than the rate at which the thickness decreases across d3.

<FIG> is an example of a cross-sectional view of a portion of a semiconductor device <NUM> useful for understanding the present invention. In the example of <FIG>, there is only a single step. More specifically, for example, the oxide layer <NUM> has a uniform first thickness x1 from a point A that is above the bottom of the trench structure <NUM> to a first distance d1, and a uniform second thickness x2 from d1 to a second distance d2, where x1 is greater than x2. The thickness of the oxide layer <NUM> can be similarly described.

Like the examples above, the device <NUM> can have non-uniform dopant concentration in the epitaxial layer as shown in <FIG>. Also, features described above can be combined with the features of the device <NUM>. Specifically, one or both of the uniformly thick portions of the oxide layers <NUM> and <NUM> can instead be decreasing (e.g., linearly decreasing) with distance from the bottom of the trench structure <NUM>. For example, the thickness of the portion of the oxide layer <NUM> along the length of the distance d1 can decrease as the distance from the bottom increases; for example, the thickness in that portion can decrease linearly from x1 to x2 across the distance d1. The thickness of the oxide layer <NUM> can be similarly described.

Thus, in general and with reference to <FIG>, an oxide layer lines the bottom and the first and second sidewalls of the trench <NUM>. The oxide layer, in essence, includes at least: a first portion <NUM> that spans the bottom of the trench <NUM> from one sidewall to the other; a second portion <NUM> that extends from the boundary of the first portion along a sidewall up to a certain height; and a third portion <NUM> that extends from the boundary of the second portion along the sidewall. The oxide layer has a first thickness (e.g., x1) in the second portion <NUM> and a second thickness (e.g., x2) in the third portion <NUM>, where the second thickness is less than the first thickness. The first thickness x1 does not necessarily extend along the entire length of the second portion <NUM>; that is, the thickness of the second portion <NUM> is not necessarily uniform, but can decrease as distance from the bottom of the trench <NUM> increases. The second thickness x2 can be similarly described.

Furthermore, the epitaxial layer includes a first region <NUM> neighboring the first portion <NUM> of the oxide layer, a second region <NUM> neighboring the second portion <NUM> of the oxide layer, and a third region <NUM> neighboring the third portion <NUM> of the oxide layer. The first region <NUM> has a first dopant concentration, the second region <NUM> has a second dopant concentration, and the third region <NUM> has a third dopant concentration. The third dopant concentration (e.g., n+) is greater than the second dopant concentration (e.g., n), and the second dopant concentration is greater than the first dopant concentration (e.g., n-).

<FIG> is a flowchart <NUM> of a method for fabricating a device according to an embodiment according to the present invention and according to a non claimed example useful for understanding the present invention. Operations described as separate blocks may be combined and performed in the same process step (that is, in the same time interval, after the preceding process step and before the next process step). Also, the operations may be performed in a different order than the order in which they are described below. Furthermore, fabrication processes and steps may be performed along with the processes and steps discussed herein; that is, there may be a number of process steps before, in between, and/or after the steps shown and described herein. Importantly, embodiments according to the present invention can be implemented in conjunction with these other (perhaps conventional) processes and steps without significantly perturbing them. Generally speaking, embodiments according to the present invention can replace portions of a conventional process without significantly affecting peripheral processes and steps. Also, <FIG> is discussed in the context of a single trench and trench structure; however, multiple trenches and trench structures can be fabricated in parallel.

In block <NUM> of <FIG>, and with reference to <FIG>, a trench <NUM> is etched in an epitaxial layer <NUM> that was formed over a substrate <NUM>. In an embodiment, the trench <NUM> is etched through an oxide hard mask or some other masking material like silicon nitride or photoresist. The masking material is then removed.

In block <NUM> of <FIG>, with reference to <FIG>, an oxide layer <NUM> is deposited or grown across the bottom and along the sidewalls of the trench <NUM> and also over the upper surface of the epitaxial layer <NUM>. The thickness of the oxide layer <NUM> is determined by the required breakdown voltage ratings. For example, the thickness of the oxide layer <NUM> is about <NUM> micrometers (µm) for a device rated at <NUM> V. In an example useful for understanding the present invention, the oxide layer <NUM> has a uniform thickness along the sidewalls of the trench <NUM> as shown in the example of <FIG>. In an embodiment of the invention, the oxide layer <NUM> has a non-uniform thickness; that is, the thickness of the oxide layer is thicker toward the bottom of the trench <NUM> and gets thinner as the distance from the bottom of the trench increases. In the latter embodiment, the thickness of the oxide layer <NUM> decreases linearly as the distance from the bottom of the trench <NUM> increases.

In block <NUM> of <FIG>, with reference to <FIG>, the trench <NUM> is filled to a specified depth with a material <NUM> such as doped polysilicon. In an embodiment, the material <NUM> is deposited past the specified depth, and then etched back to the specified depth. Instead of depositing doped polysilicon, polysilicon can be deposited and then doped by a well-known method using POCl<NUM> (phosphorus oxychloride) or phosphorus implantation and drive-in.

In block <NUM> of <FIG>, with reference to <FIG>, the oxide layer <NUM> is etched back to a specified depth (e.g., the distance d1, measured from the bottom of the trench <NUM>). In essence, the material <NUM> masks the lower portion <NUM> of the oxide layer <NUM>, so that the lower portion of the oxide layer is not etched back. In an embodiment, only some of the oxide layer <NUM> is removed in the upper portion <NUM>. As a result, the thickness x2 of the upper portion <NUM> of the oxide layer <NUM> is less than the thickness x1 of the lower portion <NUM> of the oxide layer.

In block <NUM> of <FIG>, with reference to <FIG>, the operations of blocks <NUM> and/or <NUM> are repeated to achieve a desired profile for the oxide layer <NUM>. <FIG> shows that the operations of the block <NUM> may be optional. However, according to the invention they are not optional.

More specifically, some or all of the remaining volume of the trench <NUM> is filled with the same material <NUM> that was deposited in block <NUM> above. If only some of the remaining volume is filled similar to the operation of block <NUM> above, the exposed portion of the oxide layer <NUM> can be etched back again to further thin that portion of the oxide layer, similar to the operation of block <NUM>.

In general, before the trench <NUM> is completely filled with the material <NUM>, the operations of blocks <NUM> and <NUM> can be repeated as many times as necessary to achieve a desired profile (cross-section) for the oxide layer <NUM>. For example, the operations of blocks <NUM> and <NUM> can be performed three times to achieve the profile in the example of <FIG>. According to an example useful for understanding the invention, if only a single step in the thickness of the oxide layer <NUM> is to be formed (e.g., as in the example of <FIG>), then the remaining volume of the trench <NUM> is filled after the oxide layer is etched back a single time in block <NUM>.

Once the trench <NUM> is completely filled, excess material can be removed using, for example, CMP (chemical mechanical planarization or polishing) so that the top surface of material in the trench <NUM> (the filler material <NUM> and the oxide layer <NUM>) is flush with adjacent surfaces.

In block <NUM> of <FIG>, with reference to <FIG>, in an embodiment, dopant is added to the epitaxial layer <NUM> in one or more process steps, to increase the concentration of dopant in some regions of the epitaxial layer relative to other regions of the epitaxial layer, as described above. In an embodiment, additional dopant is driven into the regions of the epitaxial layer <NUM> corresponding to the regions <NUM> and <NUM>, to increase their dopant concentration relative to the region <NUM>. Then, additional dopant is again driven into the region <NUM>, to increase its dopant concentration relative to the region <NUM>.

However, examples useful for understanding the invention are not limited to the example of <FIG>. In general, as previously described herein, dopant is added to the epitaxial layer <NUM> to produce a non-uniform concentration of dopant in the epitaxial layer, where the concentration varies according to the thickness of the oxide layer <NUM>. More specifically, the dopant concentration may be higher in a region of the epitaxial layer <NUM> adjacent to a thinner portion of the oxide layer <NUM>, and the dopant concentration may be lower in a region of the epitaxial layer adjacent to a thicker portion of the oxide layer.

Also, the various dopant concentrations in the epitaxial layer <NUM> can be introduced at any point before, after, or while the other operations included in the flowchart <NUM> are performed. For example, the epitaxial layer <NUM> can be doped before the trench <NUM> is etched; that is, the trench can be etched in an epitaxial layer that has already been doped.

In block <NUM> of <FIG>, with reference to <FIG>, a device or structure is formed in the region <NUM> adjacent to the trench <NUM>. A second trench <NUM> (e.g., a gate trench) that is shallower than the trench <NUM> is formed, an oxide layer (not shown) is grown inside the second trench, a material (e.g., polysilicon) is added inside the second trench, excess material is removed using CMP for example, the body regions <NUM> and <NUM> are formed, and the source regions <NUM> and <NUM> are formed.

In block <NUM> of <FIG>, with reference to <FIG>, openings to the source regions <NUM> and <NUM> are formed, a dielectric region <NUM> is formed over the trench structure that includes the trench <NUM>, and a metal layer is deposited to form the source electrode <NUM> in contact with the material <NUM> in the source trenches as well as the body regions <NUM> and <NUM> and the source regions <NUM> and <NUM>.

Embodiments of semiconductor devices and of methods of fabricating the semiconductor devices are thus described. In these embodiments, semiconductor devices, such as but not limited to power MOSFETs including but not limited to dual trench MOSFETs, have non-uniform oxide layers lining the trenches that are connected to the source electrode. Such devices will have lower resistivity in the drift region and lower on-state resistance but will have the same or about the same breakdown voltage relative to conventional devices.

Claim 1:
A semiconductor device (<NUM>, <NUM>, <NUM>), comprising:
a substrate layer (<NUM>);
an epitaxial layer (<NUM>) adjacent to the substrate layer;
a first trench structure (<NUM>) having a bottom and sidewalls, the first trench structure formed in the epitaxial layer, wherein the first trench structure further comprises filler material in electrical contact with and connecting to a source electrode (<NUM>); and
an oxide layer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) that lines the bottom and the sidewalls, the oxide layer having a non-uniform thickness along the sidewalls, wherein the thickness (x1) of the oxide layer at a first distance (d1) from the bottom is less than the thickness of the oxide layer at the bottom, wherein the thickness (x2) of the oxide layer at a second distance (d2) from the bottom, greater than the first distance, is less than the thickness of the oxide layer at the first distance,
wherein the epitaxial layer has a non-uniform dopant concentration, wherein the non-uniform dopant concentration varies according to the thickness of the oxide layer adjacent thereto, whereby a region (<NUM>) of the epitaxial layer at the bottom has a first dopant concentration, wherein a region (<NUM>) of the epitaxial layer at a depth corresponding to the first distance has a second dopant concentration, and wherein a region (<NUM>) of the epitaxial layer at a depth corresponding to the second distance has a third dopant concentration, and
wherein the third dopant concentration is greater than the second dopant concentration, and the second dopant concentration is greater than the first dopant concentration.