Patent Description:
Among the chalcogenide materials, two categories are currently studied for being used in electronic devices and more particularly in the manufacturing of switching devices and memories. In particular, a distinction is made between electron switching materials without memory effect (OTS materials) and phase change materials. Both materials can be used in thin film in the electronic integrated devices.

An OTS material toggles between an "on" and "off" state depending on the amount of voltage potential applied across the cell. The state of the ovonic threshold switch changes when a voltage through the ovonic threshold switch exceeds a threshold voltage. Once the threshold voltage is reached, the "on" state is triggered and the ovonic threshold switch is in a substantially conductive state. If the current or voltage potential drops below the threshold value, the ovonic threshold switch returns to the "off" state.

Phase-change materials are materials which can switch, under the effect of heat, between a crystalline phase and an amorphous phase. Since the electric resistance of an amorphous material is significantly greater than the electric resistance of a crystalline material, such a phenomenon may be useful to define two memory states, differentiated by the resistance measured through the phase-change material. The most common phase-change materials used in phase change memories are alloys made up of germanium, of antimony, and of tellurium.

Ovonic threshold switches would be useful as selecting devices thanks to their driving current capabilities in "on" state and current ratio between "on" and "off" states. However, ovonic threshold switches suffer of current overshoot at switching. Documents <CIT>, <CIT>, <CIT> and <CIT> disclose examples of electronic devices using OTS materials and/or phase change materials.

There is a need for improvement of existing integrated switching cells containing an Ovonic Threshold Switch.

One embodiment aims at overcoming all or some of the drawbacks of existing switching cells in integrated devices.

The invention is defined by enclosed independent device claim <NUM>.

According to an embodiment, the electronic cell comprises a memory layer between the first electrode and the ovonic threshold switch layer.

According to an embodiment, the electronic cell comprises a barrier layer between the memory layer and the ovonic threshold switch layer.

According to an embodiment, the memory layer is made of a phase change material.

According to an embodiment, the memory layer is a resistive random-access memory.

According to an embodiment, the memory layer is a magneto-resistive random-access memory.

According to an embodiment, the L-shaped cross-section of the resistor is self aligned with the shape of the ovonic threshold switch layer.

One embodiment provides an array comprising several cells as described, wherein the cells are connected to word lines by their resistor and to bit lines by their first electrode.

For the sake of clarity, only the operations and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail. In particular, electric connections between switching cells organized in array, and selection circuits have not been detailed, the disclosed embodiments being compatible with existing switch arrays or memory array and the corresponding addressing circuitry.

Unless specified otherwise, the expressions "around", "approximately", "substantially" and "in the order of" signify within <NUM> %, and preferably within <NUM> %.

The disclosed embodiments aim at overcoming all or part of the drawbacks of the conventional Ovonic Threshold Switch regarding the voltage snap-back, which occurs after thresholding the OTS and which causes current overshoots. The disclosed therefore provide a resistive element, electrically in series with the OTS to absorb these overshoots. More particularly, the disclosed embodiments provide a solution, which allows the integration, with an OTS cell, of a series connected resistor without requiring additional surface area.

<FIG> illustrates two simplified cross-section views (A) and (B) of an embodiment of an Ovonic Threshold Switching cell <NUM> not forming part of the invention.

The representation of <FIG> represents only one cell or OTS, but it should be noted that the switching cell of the present disclosure is part of a large number of integrated switching cells manufactured using thin film layers of chalcogenide materials, semiconductive materials, resistive materials, insulating materials, conductive materials, etc..

For sake of simplification, reference is made to layers to designate the corresponding elements of a stack forming the switching cell. It should however be understood that the corresponding layers correspond, in practice, to thin films deposited and etched to form individual switching elements separated by insulating trenches and arranged, for example in arrays. The terminals or electrodes of each switching cell may be interconnected, for example in lines and in columns, by corresponding layers of the stack.

A cell <NUM> comprises a resistor <NUM> or resistive element having a fixed resistance value, an ovonic threshold switch layer <NUM> or OTS layer, a top electrode <NUM> and a conductive layer <NUM>, connected to the top electrode <NUM>. The OTS layer <NUM> is located between the resistor <NUM> and the top electrode <NUM>.

The OTS layer <NUM> has the property to have a significant decrease of resistivity when the voltage applied between the conductive layer <NUM> and the resistor <NUM> exceeds a threshold voltage VTH. This decrease (or increase) triggered by the voltage which is applied between the top and the bottom of the layer allows to consider the layer as forming a switch between an "off" state and an "on" state. If the voltage applied to OTS layer <NUM> is lower than the threshold VTH of the OTS layer <NUM>, then the OTS layer <NUM> remains in the "off" or highly resistive state. In such a state, only a leakage current flows through the cell <NUM>. If a voltage higher than the threshold VTH is applied, then the OTS layer <NUM> switches to the "on" state and operates in a relatively low resistive state. In the "on" state, a current flows through the cell <NUM>. The threshold voltage VTH of the OTS layer <NUM> is, for example, inclusively between <NUM>,<NUM> V to <NUM> V.

The OTS layer <NUM> is, for example, made of a chalcogenide material, for example, chosen within the flowing list: germanium (Ge), tellurium (Te), selenium (Se), tungsten (W), antimony (Sb), arsenic (As), indium (In), sulfur (S) or any combination or alloy of these materials. The OTS layer <NUM> is made of a material the phase (crystallin) of which does not change upon the application of energy.

The OTS layer <NUM> has, for example, a thickness inclusively between <NUM> and <NUM>, preferably, between <NUM> and <NUM>.

Examples of ovonic materials adapted to form OTS layer <NUM> can be found in <CIT>.

The top electrode <NUM> typically forms an electrode (to be connected to the bit line) of the cell <NUM> while the resistor <NUM> forms another electrode (to be connected to the word line) of the cell <NUM>.

The top electrode <NUM> is connected to the conductive layer <NUM>. The conductive layers <NUM> form the bit lines. The top electrode <NUM> and the conductive layer <NUM> are, for example, in direct contact. The conductive layer <NUM> is, for example, connected to the top electrode <NUM> through a conductive via smaller than the top electrode <NUM> and made, for example, of tungsten.

The conductive layer <NUM> has, for example, the same width as, or a larger width than, one of the dimensions of the top electrode <NUM>.

Each cell comprises one OTS layer <NUM> and one top electrode <NUM>, which are separated from the OTS layers <NUM> and the top electrodes <NUM> of the adjacent cells by an insulating layer, not shown. Each OTS layer <NUM> is "fully confined", which means that the OTS layer <NUM> of each cell is separated from the OTS layers <NUM> of the adjacent cells by insulating material. The OTS layer <NUM> and the top electrode <NUM> have, for example, a parallelepipedal shape having, for example, for both layers the same width and the same length.

The resistor <NUM> has an L-shaped cross-section. The resistor <NUM> has then a horizontal portion <NUM> and a vertical portion <NUM>. The resistor <NUM> is, for example, surrounded by an insulating layer, not shown. The thickness of this insulating layer is such that the upper surface of the vertical portion <NUM> of the resistor <NUM> is coplanar with the upper surface of the insulating layer. The resistor <NUM> is, for example, in contact with the OTS layer <NUM>.

The top electrode <NUM> and the resistor <NUM> are, for example, made of any refractory metal and/or refractory metal nitride, such as carbon (C), carbon nitride ((CN)n), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (W<NUM>N, WN, WN<NUM>), tungsten carbon nitride, tungsten silicon nitride, tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride, tantalum tungsten, or any combination or alloy of these materials. The top electrode <NUM> and the resistor <NUM> are, for example, made of the same materials. The top electrode <NUM> and the resistor <NUM> are, for example, made of two different materials.

The top electrode <NUM> and the conductive layer <NUM> may be made of the same conductive material or of different conductive materials. The conductive layer <NUM> is, for example, made of copper.

The examples of <FIG> and <FIG> as well as the embodiments of <FIG> and <FIG> are shown in space following an orthogonal spatial system XYZ in which the axis Z is orthogonal to the top face of the conductive layer <NUM> of the cell <NUM>.

In the embodiment of view (A) and view (B), the top conductive layer <NUM> extends horizontally along the direction X. In the example of view (A), the vertical portion <NUM> of the resistor <NUM> is preferably centered with respect to the cell <NUM> and extends vertically along the direction Y. In the example of view (B), the vertical portion <NUM> of the resistor <NUM> is preferably centered with respect to the cell <NUM> and extends vertically along the direction X.

The difference between views (A) and (B) of <FIG> is therefore the orientation of the L-shaped resistor. View (A) is called a "self-aligned wall" cell architecture, in which the resistor <NUM> width is equal to the conductive layer <NUM> width. In view (A), the resistor <NUM> and the conductive layer <NUM> are, for example, formed using the same masking layer and in the same direction.

View (B) corresponds to a use of the "self-aligned wall technology" in a different way, in which the width of resistor <NUM> is not equal to the width of the conductive layer <NUM>. In view (B), the resistor <NUM>, the OTS layer <NUM> and the top electrode <NUM> are, for example, formed using the same masking layer as the one used to form the conductive layer <NUM> but oriented in the perpendicular direction compared to the direction of the conductive layer <NUM>. The cell architecture of view (B) allows to integrate a resistor <NUM> into an OTS device with no area penalty at the cost of one not critical additional mask and few additional process steps.

In both view (A) and view (B), the interconnection (not shown) of the foots <NUM> of the resistors <NUM> is perpendicular to the interconnection of the conductive layers <NUM>. In other words, if the conductive layer <NUM> is organized in columns, the bottom electrode is organized in rows.

An advantage of the present embodiments is that the resistor <NUM> is not external to the cell <NUM> but is integrated to cell <NUM>.

<FIG> illustrates two simplified cross-section views (A) and (B) of an embodiment of an Ovonic Threshold Switching cell <NUM> according to the invention.

The cell <NUM> illustrated in <FIG> is similar to the cell <NUM> illustrated in <FIG> with the difference that the cell <NUM> comprises a local bottom electrode <NUM>. The bottom electrode <NUM> is, for example, located below the OTS layer <NUM>, that means that the bottom electrode <NUM> is located between the resistor <NUM> and the OTS layer <NUM>. The bottom electrode <NUM> extends, for example, below the entire surface of the OTS layer <NUM>, that means that the bottom electrode <NUM> has the same length and the same width than the length and the width of the OTS layer <NUM>. The resistor <NUM> is, for example, in contact with the bottom electrode <NUM> which is in contact with the OTS layer <NUM>.

The local bottom electrode <NUM> provides a uniformization of the electrical current flow in all the surface of the OTS layer <NUM>.

The bottom electrode <NUM> is, for example, made of any conductive material, such as carbon (C) or carbon nitride ((CN)n). The bottom electrode <NUM> is, for example, not made of a metal or a combination of metals.

The bottom electrode <NUM> has, for example, a thickness inclusively between <NUM> and <NUM> and preferably, between <NUM> and <NUM>.

In the example of view (A), the vertical portion <NUM> of the resistor <NUM> is preferably centered with respect to the cell <NUM> and extends vertically along the direction Y.

In the example of view (B), the vertical portion <NUM> of the resistor <NUM> is preferably centered with respect to the cell <NUM> and extends vertically along the direction X.

The provision of a resistor <NUM> integrated with an OTS cell offer new integration opportunities for various devices. In particular, this allows the integration of a switch with a memory cell at no cost of additional area.

<FIG> illustrates a cross-section view of memory cell <NUM> not forming part of the invention.

<FIG> illustrates a cross-section view of another embodiment of a memory cell <NUM> according to the invention.

The memory cell <NUM> illustrated in <FIG> and the memory cell <NUM> illustrated in <FIG> are respectively similar to the cell <NUM> illustrated in the view (B) of <FIG> and the cell <NUM> illustrated in the view (B) of <FIG> with the difference that memory cells <NUM>, <NUM> comprise a memory layer <NUM>. The memory layer <NUM> is located above the OTS layer <NUM> and between the OTS layer <NUM> and the top electrode <NUM>.

When the voltage applied to the cell is higher than a threshold voltage (VTH) of the OTS layer <NUM>, an electrical current may flow through the OTS layer <NUM> and the memory layer <NUM> in the memory cell <NUM>, <NUM> and may result in changing the resistivity of the layer <NUM>. This change may alter the memory state of the layer <NUM>, thus altering the electrical characteristic of the memory cell <NUM>, <NUM>.

The high resistive state may be associated with a "reset" state or a logic "<NUM>" value, while a low resistive state may be associated with a "set" state, or a logic "<NUM>" value.

According to <FIG>, the memory cells <NUM>, <NUM> comprise a barrier layer <NUM> between the memory layer <NUM> and the OTS layer <NUM>.

The memory layer <NUM> may be made of a phase change material (PCM) that switches from a high resistance state, generally amorphous, to a low resistance state, generally crystalline, upon the application of energy such as heat, light, voltage potential, or electrical current. The phase change material may be switched from completely amorphous to completely crystalline or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline. In the case that the memory layer <NUM> is a PCM layer, the resistor <NUM> is, for example, a heating compound. The memory layer <NUM> is, for example, made of any phase change materials such as phase change chalcogenides. For example, the memory layer <NUM> is made of germanium, antimony, tellurium, or any alloy of all or some of these compounds.

The memory layer <NUM> may also be a resistive random-access memory (RRAM) layer. The memory layer <NUM> is, for example, made of one or more dielectric material in which a conduction path is formed upon the application of a relatively high voltage. The memory layer <NUM> is, more precisely made of chalcogenides (such as the alloy Ge<NUM>Sb<NUM>Te<NUM> or the alloy AgInSbTe), binary transition metal oxides (such as nickel oxide and titanium dioxide), perovskites (such as Sr(Zr)TiO<NUM> and Pr<NUM>Ca<NUM>MnO<NUM>), solid-state electrolytes (such as germanium monosulfide, germanium selenide, silicium oxide, copper sulfide), organic charge-transfer complexes (such as CuTCNQ), organic donor-acceptor systems (such as Al AIDCN), and/or two dimensional insulating materials like hexagonal boron nitride.

The memory layer <NUM> may also be a magneto-resistive random-access memory (MRAM) layer, that means that the electric resistance of the layer <NUM> changes upon the application of an electron current. The memory layer <NUM> is formed from two ferromagnetic layers, each of which can hold a magnetization, separated by a thin insulating layer. One of the two ferromagnetic layers, called "fixed layer", has a fixed magnetization direction and acts as an electron spin polarizer. The other ferromagnetic layer, called "free layer", has a direction that can be flipped by a relatively high programming current. The magnetization direction of the free layer can be reversed by reversing the direction of the programming current.

The memory layer <NUM> extends, for example, on the entire surface of the OTS layer <NUM>, that means that the memory layer <NUM> has the same length and the same width than the length and the width of the OTS layer <NUM>. The memory layer <NUM> has, for example, a thickness inclusively between <NUM> and <NUM>, preferably, between <NUM> and <NUM>.

The barrier layer <NUM> is, for example, a layer that limits the diffusion of the memory layer <NUM> into the OTS layer <NUM> and vice versa. The barrier layer <NUM> is, for example, used to limit the mix of the material of the memory layer <NUM> and the material of the OTS layer <NUM>.

The barrier layer <NUM> is, for example, made of any conductive material and/or diffusion material, such as carbon (C) and carbon nitride ((CN)n). The barrier layer <NUM> is, for example, not made of a metal because of the diffusion of metal material in the OTS layer <NUM>.

The barrier layer <NUM> extends, for example, upper the entire surface of the OTS layer <NUM>, that means that the barrier layer <NUM> has the same length and the same width than the length and the width of the OTS layer <NUM> and the memory layer <NUM>. The barrier layer <NUM> has, for example, a thickness inclusively between <NUM> and <NUM>, preferably, between <NUM> and <NUM>.

In the example of <FIG>, the vertical portion <NUM> of the resistor <NUM> is preferably centered with respect to the memory cell <NUM> and extends vertically along the direction X. In another example, the vertical portion <NUM> of the resistor <NUM> is preferably centered with respect to the memory cell <NUM> and extends vertically along the direction Y.

In the embodiment of <FIG>, the vertical portion <NUM> of the resistor <NUM> is preferably centered with respect to the memory cell <NUM> and extends vertically along the direction X. In another embodiment, the vertical portion <NUM> of the resistor <NUM> is preferably centered with respect to the memory cell <NUM> and extends vertically along the direction Y.

<FIG> illustrates a simplified schematic view of an array of memory cells <NUM>.

The array of memory cells <NUM> comprises a plurality of memory cells such as the memory cells <NUM> illustrated in <FIG>.

The memory cells <NUM> are, in <FIG>, positioned between a plurality of bit lines <NUM> and word lines <NUM>. In <FIG>, bit lines <NUM> are illustrated with verticals lines and word lines <NUM> are illustrated with horizontal lines.

Each memory cell <NUM> includes the resistor <NUM>, the OTS layer <NUM> (or OTS compound) and the memory layer <NUM> (or modular resistivity compound). According to an embodiment, each memory cell <NUM> is connected to a bit line <NUM> made of the conductive layer <NUM>, by the top electrode <NUM> and is connected to a word line <NUM> by the resistor <NUM>.

The array of memory cells <NUM> has been illustrated with memory cells <NUM>, however, the array of memory cells <NUM> can be easily adapted to the cell <NUM>, <NUM> or to the memory cell <NUM>.

<FIG> illustrate, by schematic views, steps of a manufacturing process of the array of memory cells <NUM> illustrated in <FIG>.

First, active areas are formed, using a mask <NUM> (<FIG>), for example, following a first direction, in order to create the word lines (<NUM>, <FIG>). Some contacts <NUM>, are then formed on top of the active areas (<FIG>).

For example, resistors <NUM> are formed, through a mask <NUM> (<FIG>), for example, following a second direction, orthogonal to the first direction. After the formation of the resistor <NUM>, the OTS layer <NUM> and the top electrode <NUM> are formed. The top electrode <NUM>, the OTS layer <NUM> and the resistor <NUM> are then patterned using the "self-aligned wall" technology with the mask <NUM>. After the deposition of an insulating layer and its removing with chemical mechanical polishing in order to expose the top electrode, the conductive layer <NUM> is deposited in order to form the bit lines (<NUM>, <FIG>).

For example, the conductive layer <NUM>, the top electrode <NUM> and the OTS layer <NUM> are formed with the mask <NUM>. The conductive layer <NUM> forms the bit lines (<NUM>, <FIG>).

The masks are temporary masks, which are positioned for the concerned steps and which are then removed as it is usual in microelectronic industry.

An advantage of including a resistor <NUM> in each cell of the array is that it permits to limit an overshoot of current which typically appears during threshold and which disturbs the cell.

Another advantage of the present application is that it increases the lifetime of the cell.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily occur to those skilled in the art.

Claim 1:
An electronic cell (<NUM>; <NUM>; <NUM>; <NUM>) comprising an integrated stack having successively, vertically:
- a first electrode (<NUM>);
- an ovonic threshold switch layer (<NUM>);
- a second electrode (<NUM>) connected to the ovonic threshold switch layer (<NUM>) and in contact with the ovonic threshold switch layer (<NUM>); and
- a fixed resistor (<NUM>) connected to the second electrode (<NUM>) and in direct contact with the second electrode (<NUM>),
wherein the fixed resistor (<NUM>) has a L-shaped cross-section and has a horizontal portion (<NUM>) and a vertical portion (<NUM>),
characterised in that the vertical portion (<NUM>) is located between the horizontal portion (<NUM>) and the second electrode (<NUM>).