Patent Description:
Group III nitride semiconductors, including AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, AlInGaN and the like are important semiconductor materials. Due to their advantages like direct band gap, wide forbidden band and high breakdown electric field intensity, Group III nitride semiconductors represented by GaN have broad application prospects in the fields of light-emitting devices, power electronics and radio frequency devices. <CIT> discloses a gallium nitride (GaN) circuit device, and transistors or transistor layers that include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel.

Unlike conventional non-polar semiconductor materials such as Si, Group III nitride semiconductors have polarity. In other words, they are polar semiconductor materials. Polar semiconductors have many unique properties. Particularly importantly, fixed polarized charges are present at a surface of the polar semiconductor or at an interface of two different polar semiconductors. These fixed polarized charges may attract movable electrons or hole carriers and thus form the two-dimensional electron gas (2DEG) or the two-dimensional hole gas (2DHG). The generation of 2DEG or 2DHG neither requires an additional electric field, nor depends on a doping effect in the semiconductor. It is spontaneously generated. The 2DEG or 2DHG at the interface of the polar semiconductors may have a high surface charge density. Meanwhile, without doping, the 2DEG or the 2DHG has high mobility because of reduction of ion scattering effect and so on that the 2DEG or the 2DHG is usually subjected to undertake. The high density of the surface charge and high mobility enable the 2DEG or 2DHG spontaneously generated at those interfaces to have good conductivity and high response speed.

In combination with inherent advantages of the nitride semiconductor such as high breakdown electric field and so on, the 2DEG or 2DHG may be used to manufacture high mobility transistors. Their performances in high energy, high voltage or high frequency applications are significantly better than those traditional Si or GaAs devices. However, existing structures have many defects, which seriously restricts their application ranges.

Subject-matter falling outside the scope of the claims may be disclosed but is not according to the invention.

This disclosure relates to a semiconductor device, comprising: a blocking layer of insulating material formed on a substrate; a groove formed through the blocking layer and into the substrate, the groove having vertical sidewalls; a first channel layer positioned within the groove; a first barrier layer positioned within the groove, wherein a first heterojunction having a vertical interface is included between the first channel layer and the first barrier layer and 2DEG or 2DHG is formed in the first heterojunction; a first electrode being electrically connected with 2DEG or 2DHG of the first heterojunction; and a second electrode being electrically connected with 2DEG or 2DHG of the first heterojunction; wherein the blocking layer embraces the first electrode and the second electrode making the first electrode and the second electrode separated from the substrate, and wherein one of the following applies.

In the semiconductor device as described in the above, the first channel layer and the first barrier layer are two kinds of nitride semiconductor with different forbidden band widths.

The semiconductor device as described in the above further comprises a substrate positioned under the groove.

In the semiconductor device as described in the above, at least a part of a sidewall of the groove is a part of the substrate.

In the semiconductor device as described in the above, at least a part of the sidewall of the groove is a (<NUM>) plane of Si, a (<NUM>) plane of sapphire Al2O3, a (<NUM>) or (<NUM>-<NUM>) plane of SiC, or a (<NUM>) or (<NUM>-<NUM>) plane of intrinsic GaN.

In the semiconductor device as described in the above, the substrate is Si.

In the semiconductor device as described in the above, a nucleation layer is included in the groove.

The semiconductor device as described in the above further comprises a first separating layer formed between the bottom of the groove and the first channel layer.

The semiconductor device as described in the above further comprises a second separating layer formed between the bottom of the groove and the first barrier layer.

The semiconductor device as described in the above further comprises a gate insulating layer positioned between the third electrode and the first heterojunction.

The semiconductor device as described in the above further comprises a second channel layer and a second barrier layer, wherein a second heterojunction having a vertical interface is included between the second channel layer and the second barrier layer and 2DEG or 2DHG is formed in the second heterojunction.

The semiconductor device as described in the above further comprises a screening layer between the first channel layer/the first barrier layer and the second channel layer/the second barrier layer.

The semiconductor device as described in the above further comprises a spacing layer formed on the bottom of the groove under the screening layer, the spacing layer extends horizontally.

The semiconductor device as described in the above with the first electrode being electrically connected with 2DEGs or 2DHGs of the first heterojunction and the second heterojunction; and the semiconductor device further comprises the second electrode being electrically connected with 2DEGs or 2DHGs of the first heterojunction and the second heterojunction; wherein one of the first electrode and the second electrode is in Schottky contact and the other is in ohmic contract.

the first electrode being electrically connected with 2DEGs or 2DHGs of the first heterojunction and the second heterojunction; the second electrode being electrically connected with 2DEGs or 2DHGs of the first heterojunction and the second heterojunction; and a third electrode between the first electrode and the second electrode, configured to control current intensity between the first electrode and the second electrode.

In another aspect of the present disclosure, it provides a method of manufacturing a semiconductor device, comprising forming a blocking layer of insulating material on a substrate; forming a first groove through the blocking layer and into the substrate, the first groove having vertical sidewalls; forming a first channel layer within the first groove by horizontal growth; forming a second groove in the substrate, the second groove having a side of the first channel layer exposed; and forming a first barrier layer within the second groove by horizontal growth, wherein a first heterojunction having a vertical interface is included between the first channel layer and the first barrier layer and 2DEG or 2DHG is formed in the first heterojunction; the method further comprising one of the following.

wherein the first electrode and the second electrode are formed such that the blocking layer embraces the first electrode and the second electrode, making the first electrode and the second electrode separated from the substrate.

The method as described in the above further comprises forming a first separating layer on the bottom of the first groove.

The method as described in the above further comprises forming a second separating layer on the bottom of the second groove.

The method as described in the above further comprises forming a first spacing layer on a sidewall of the first groove.

The method as described in the above further comprises forming a second spacing layer on a sidewall of the second groove.

The method as described in the above further comprises forming a gate insulating layer between the first heterojunction and the third electrode before forming the third electrode.

The method as described in the above further comprises forming a third groove through the blocking layer and into the substrate; forming a second channel layer within the third groove by horizontal growth, forming a fourth groove through the blocking layer and into the substrate, the fourth groove having a side of the second channel layer exposed; and forming a second barrier layer within the fourth groove by horizontal growth, wherein a second heterojunction having a vertical interface is included between the second channel layer and the second barrier layer and 2DEG or 2DHG is formed in the second heterojunction.

The method as described in the above further comprises forming a screening layer between the first channel layer/the first barrier layer and the second channel layer/the second barrier layer.

The method as described in the above further comprises forming a spacing layer on the bottom of the groove under the screening layer, wherein the spacing layer extends horizontally.

The method as described in the above further comprises forming the first electrode being electrically connected with 2DEGs or 2DHGs of the first heterojunction and the second heterojunction; and forming the second electrode being electrically connected with 2DEGs or 2DHGs of the first heterojunction and the second heterojunction; wherein one of the first electrode and the second electrode is in Schottky contact and the other is in ohmic contract.

The method as described in the above further comprises forming the first electrode being electrically connected with 2DEGs or 2DHGs of the first heterojunction and the second heterojunction; forming the second electrode being electrically connected with 2DEGs or 2DHGs of the first heterojunction and the second heterojunction; and forming a third electrode between the first electrode and the second electrode, configured to control current intensity between the first electrode and the second electrode.

In order that the objects, technical solutions and advantages of the embodiments of the present disclosure will become clearer, technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. All the other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts will fall within the scope of the present disclosure.

In the following detailed description, reference may be made to various drawings which constitute a part of the present application and serve to explain the present application. In the drawings, similar reference signs denote substantially similar components in different figures. The individual specific embodiments of the present application will be described in sufficient detail below to enable those of ordinary knowledge and skills in the art to carry out the technical solutions of the present application. It is understood that other embodiments may be utilized, or structural, logical or electrical changes may be made to the embodiments of the present application.

The present disclosure provides a semiconductor device.

<FIG> is a top view of a single-channel HEMT according to an embodiment of the present disclosure; and <FIG> is a sectional view of a single-channel HEMT according to an embodiment of the present disclosure, which shows the sectional view at the position along the dot dash line A-A. The semiconductor device <NUM> comprises a groove <NUM>. As shown in <FIG>, the groove <NUM> presents a rectangle shape. As shown in <FIG>, the groove <NUM> extends from top to bottom, producing internal room. As shown in the figures, a channel layer 103A and a barrier layer 104A extending along the vertical direction are included in the groove <NUM>. A vertical interface <NUM> is formed between the channel layer 103A and the barrier layer 104A. Because the channel layer 103A and the barrier layer 104A have different energy band gaps, a heterojunction having a vertical interface <NUM> is formed within the groove <NUM>. A vertical two-dimensional electron gas 2DEG 105A is formed in the heterojunction.

In some embodiments, the groove <NUM> may present other shapes like a triangle or circle at the surface of the semiconductor device <NUM>. In some embodiments, after some specific processes (for example removal of the substrate), the groove <NUM> may extend from one side of the semiconductor device <NUM> to the other side thereof, which generating a passthrough structure. Those changes are also within scope of the present disclosure.

The devices having the groove structure related to the present disclosure have the following advantages: a device which is difficult to be implemented with ordinary methods may be formed by forming a groove structure according to requirements of a practical device to meet the requirements and then forming the device step by step within the groove structure. For example, it is easy to form a low ratio of width to height by epitaxial growth in the art, such as growing a thin film on a plane. However, it is often very difficult to form a high ratio of width to height. As an example, in case the vertical height is big and the width is small in the structure in <FIG>, it is very difficult to be accomplished by traditional epitaxial growth. As shown with some embodiments of the present disclosure, such structure is easy to realize by the groove structure provided by the present disclosure.

In some embodiments, the ratio of width to height of the channel layer and the barrier layer of the semiconductor device of the present disclosure may be <NUM>:<NUM>, <NUM>:<NUM>, or <NUM>:<NUM>. For example, the width of both of the bottom of the channel layer 103A and the barrier layer 104A is <NUM> (micro meter), the height of the channel layer 103A and the barrier layer 104A may be <NUM>, <NUM>, or <NUM>. In practice, after defined by the groove, any desire ratio of width to height can be realized by means of the groove.

In some embodiments, the groove <NUM> is formed in a substrate <NUM>. For example, the substate <NUM> is etched to form the groove <NUM>. The lattice of the exposed surface of the substrate <NUM> has hexagonal symmetry such that the nitride semiconductor crystal can be epitaxially grown later. For example, the exposed vertical surface of the substrate <NUM> may be a (<NUM>) plane of Si, a (<NUM>) plane of sapphire Al<NUM>O<NUM>, a (<NUM>-<NUM>), or (<NUM>) plane of SiC, or a (<NUM>-<NUM>), or (<NUM>) plane of intrinsic GaN. Further, the corresponding substrate may be a Si substrate, a sapphire Al<NUM>O<NUM> substrate, a SiC substrate, or an intrinsic GaN substrate.

The widths of the channel layer 103A and the barrier layer 104A may be adjusted according to practical requirements. In the channel layer 103A, 2DEG 105A is formed adjacent to the vertical interface <NUM> between the channel layer 103A and the barrier layer 104A.

In some embodiments, the channel layer 103A and the barrier layer 104A is lower than the groove <NUM>. In some specific applications, the channel layer 103A and the barrier layer 104A may extend higher than the groove <NUM> although it is difficult to control the growth of the channel layer 103A and the barrier layer 104A without the definition of the groove <NUM>. The height outside of the groove <NUM> is limited even if the channel layer 103A and the barrier layer 104A have been higher than the groove <NUM>.

In ordinary growth conditions, the surface of the channel layer and the barrier layer on the Si (<NUM>) and Al<NUM>O<NUM> (<NUM>) is also (<NUM>) plane. That is, the direction from the Si and Al<NUM>O<NUM> substrate to the channel layer and the barrier layer is <<NUM>> crystal orientation. With such crystal orientation, there is 2DEG in the channel layer adjacent to the interface between the channel layer and the barrier layer. On opposite, there is 2DHG in the channel layer adjacent to the interface between the channel layer and the barrier layer in <<NUM>-<NUM>> crystal orientation.

In some embodiments, HEMT <NUM> further comprises a nucleation layer 102A. The nucleation layer 102A is formed on the vertical surface of the substrate <NUM>. In some embodiments, the nucleation layer 102A may be AlN. Because of shadowing of the channel layer, the nucleation layer 102A is invisible in <FIG>. The position of the nucleation layer 102A is shown schematically in <FIG> to facilitate the understanding.

In some embodiments, HEMT <NUM> further comprises a buffer layer (not shown). The buffer layer is formed on the nucleation layer 102A. For example, the buffer layer may be in structure of one layer or multiple layers, including one or more of AlN, GaN, AlGaN, InGaN, AlInGaN.

In some embodiments, the semiconductor device <NUM> comprises a first electrode <NUM> and a second electrode <NUM>. The first electrode <NUM> and a second electrode <NUM> are electrically connected with 2DEG 105A. For example, one of the first electrode <NUM> and the second electrode <NUM> is in ohmic contact with the channel layer 103A and/or the barrier layer 104A; the other is in Schottky contact with the channel layer 103A and/or the barrier layer 104A, and thereby forming a Schottky diode.

The HEMT <NUM> further comprises a third electrode <NUM>. The third electrode <NUM>, provided between the first electrode <NUM> and the second electrode <NUM>, is also called the gate electrode and controls current intensity in the channel area between the first electrode <NUM> and the second electrode <NUM>, forming the HEMT structure. As shown in <FIG>, the height of the third electrode <NUM> is not lower than that of 2DEG 105A to realize control of current channel between the first electrode <NUM> and the second electrode <NUM>. Preferably, in case the first electrode <NUM> as a drain is connected to the high voltage, the third electrode may be positioned between the first electrode <NUM> and the second electrode <NUM> and be more adjacent to the second electrode <NUM> (a source). This arrangement increases the distance between the drain and the gate, which can effectively enhance withstanding voltage of the semiconductor device <NUM>.

The voltage of the third electrode <NUM> may control the depth of the heterojunction formed by the channel layer-the barrier layer, control the density of surface charge of the 2DEG in the potential well, and further control the working current between the first electrode <NUM> and the second electrode <NUM>. In some embodiments, a gate insulating layer <NUM> is included outside of the barrier layer 104A. The third electrode <NUM> is contacted with the gate insulating layer <NUM> and is not directly contacted with the barrier layer 104A.

<FIG> shows an arrangement of the three electrodes of the HEMT <NUM>. The first electrode <NUM> and the second electrode <NUM> are located at almost the same position within the scope of the groove <NUM> in the above of the channel layer 103A and/or the barrier layer 104A. The gate insulating layer <NUM> is included outside of the barrier layer 104A. The third electrode <NUM> is set outside of the gate insulating layer <NUM>. The third electrode <NUM> is also within the groove <NUM>. In this way, the wafer area occupied can be decreased and the integrity can be enhanced. Further, all three electrodes are positioned on the upper surface of the device, which will facilitate the wiring thereafter and integrity. In some embodiments, the gate insulating layer <NUM> covers the third electrode <NUM>, which can make the substate <NUM> separated and facilitate simplification of manufacturing processes.

In another aspect, as shown in <FIG>, the groove <NUM> may be very deep, which further forms very high 2DEG 105A. The HEMT made in this way can easily have higher power because the conductive current between the source and the drain is bigger in the condition that the distance between the electrodes are not changed.

In some embodiments, on the sidewall of the groove <NUM>, a separating layer (not shown) may be included between the substrate <NUM> and the channel layer 103A. It may embrace the channel layer 103A and its material may be insulating materials such as SiO<NUM>, etc. The separating layer makes the channel layer 103A separated from the substate <NUM>, which can avoid influence of the substrate <NUM> to the performance of the device and is obviously helpful to enhance the withstanding voltage and to reduce the dark current.

In some embodiments, on the bottom of the groove <NUM>, a separating layer 115A is included between the substrate <NUM> and the channel layer 103A. The separating layer 115A extends horizontally and its material may be insulating materials such as SiO<NUM>, etc. The separating layer 115A makes the channel layer 103A separated from the substate <NUM>, which can avoid influence of the substrate <NUM> to the performance of the device and is obviously helpful to enhance the withstanding voltage and to reduce the dark current.

In some embodiments, on the bottom of the groove <NUM>, a separating layer 112A is included between the substrate <NUM> and the barrier layer 104A. The separating layer 112A extends horizontally and its material may be insulating materials such as SiO<NUM>, etc. The separating layer 112A makes the barrier layer 104A separated from the substate <NUM>, which can avoid influence of the substrate <NUM> to the performance of the device and is obviously helpful to enhance the withstanding voltage and to reduce the dark current.

In order to enhance capacity of voltage withstanding of the device <NUM> and reduce the influence of the substate <NUM>, an upper part of the sidewall of the groove, which embraces externally the channel layers 103A and 103B or a part of the same, is a blocking layer <NUM> of non substrate material. Its material is an insulating material, such as SiO<NUM>, etc. As shown in <FIG> and <FIG>, all of the surface of the substrate is covered by the blocking layer <NUM>. The groove <NUM> is formed by partially removing the blocking layer <NUM>. Therefore, the blocking layer <NUM> embraces the groove <NUM> and a part of the same becomes the sidewall of the groove <NUM>. In an example falling outside the scope of the claims, the sidewalls of the groove <NUM> are all made by the blocking layer <NUM>. According to the invention, the blocking layer <NUM> embraces the first electrode <NUM> and the second electrode <NUM> and makes the first electrode <NUM> and the second electrode <NUM> separated from the substrate <NUM>. For example, a part of the substrate which embraces the first electrode <NUM> and/or the second electrode <NUM> are removed and then the blocking layer <NUM> is deposited. The blocking layer <NUM> can avoid influence of the substrate <NUM> to the performance of the device. Meanwhile, it also provides protection to the semiconductor device <NUM> and increase durability of the device.

According to an embodiment of the present disclosure, the substrate <NUM> can be the Si substrate with low costs and matured manufacturing processes. Because of the Si substrate, a nucleation layer 102A with material of AlN is introduced. Preferably, a buffer layer 103A is also introduced to alleviate influence of the lattice difference. The buffer layer <NUM> may be one or more of AlN, GaN, AlGaN, InGaN, AlInGaN. The channel layer 103A may be GaN and the barrier layer 104A may be AlGaN. In some embodiments, the material of the screening layer <NUM>, the blocking layer <NUM>, the separating layer 112A and the separating layer 115A may be at least one kind of insulating material such as oxide of silicon, oxide of silicon nitride, silicon nitride, with one or multiple layers structure.

The present disclosure has a number of advantages like high figurability. In the growth of traditional processes, crystal is likely to grow vertically, which makes it difficult to produce some specific size ratios or structures. After introduction of the grooves, the crystal will grow along the shape of grooves. Therefore, the technical solution of the present disclosure can form the device structure with relatively high ratio of height to width which is difficult to be produced by ordinary processes. Moreover, the manufacturing processes is more simplified. The structure with relatively high ratio of height to width may realize higher density of vertical channels on the flat size, reduce resistance of the device, and improve performance of the device.

In the other aspect, it is very difficult to make a semiconductor structure grown completely vertically and it is possible to present multiple growth surfaces because of no limitation to the crystal growth. The structure of the present disclosure may keep continuous growth on one surface and improve electrical performance of the device. The growth of a traditional device usually be done from bottom to top in the vertical direction. The structure of the present disclosure grows horizontally. A plurality of device may be formed in the same groove, which not only reduce manufacturing costs and save manufacturing working time but also significantly improve integrity on the flat size of the substrate. Further, in some embodiments, the electrodes are in the plane structure and on the top of the device, which facilitate the arrangement and lining. The structure of the present disclosure may be applied in many kinds of semiconductor devices, for example HEMTs, HHMTs, Schottky diodes, etc. The scope of application is wide.

As shown in some embodiments, the Si substrate with low costs and matured processes may be used in the present disclosure and its capability of voltage withstanding is close to a high electron mobility transistor with the intrinsic GaN substrate. Next, the contact area between the semiconductor device and the Si substrate is relatively small and it is not easy to have the problem of epitaxial layer fracturing which is likely to occur in traditional horizontal devices. Therefore, the cost of the semiconductor device of the present disclosure is lower.

As known to persons having ordinary skills in the art, the above description only exemplarily shows the structure of high electron mobility transistor. There are many other structures or improvements, changes, or modifications on those structures for the devices related to the present disclosure to provide different properties or functions. Those structures and improvements, changes, or modifications on them are within the scope of technical concept of the present disclosure and may be also applied in the technical solutions of the present disclosure.

In some embodiments, the semiconductor device shown in <FIG> and <FIG> is a HEMT. The similar structure can also be used to form a HHMT having 2DHG.

<FIG> is a top view of a single-channel HHMT according to an embodiment of the present disclosure; and <FIG> is a sectional view of a single-channel HHMT according to an embodiment of the present disclosure, which shows the interface along the line B-B. The structures which are similar to those in <FIG> and <FIG> are not repeated herein.

As shown in the figures, the semiconductor device <NUM> comprises a groove <NUM>. A vertical interface <NUM> is formed between a channel layer 203A and a barrier layer 204A, which produces a heterojunction structure wherein a vertical two-dimensional hole gas 2DHG 206A is formed within the channel layer 203A adjacent to the vertical interface <NUM>.

Different from the embodiment shown in <FIG> and <FIG>, a nucleation layer 202A is positioned within the groove <NUM> between the channel layer 203A and the barrier layer 204A. The direction of crystal growth of the channel layer 203A and the barrier layer 204A can be seen from the nucleation layer 202A, and thereby it can be determined that it is 2DHG therebetween. In some embodiments, it can determine whether it is 2DEG or 2DHG between the channel layer and the barrier layer according to the crystal growth direction although there is no nucleation layer 202A.

In some embodiments, a first groove is formed by etching the substrate and the channel layer 203A is formed within the first groove. Then, a second groove is formed by etching the substrate on the right of the first groove and the right side of the channel layer 203A is exposed. The barrier layer 204A is formed within the second groove. The vertical interface <NUM> is included between the channel layer 203A and the barrier layer 204A, and thereby forming a heterojunction. Both of the first groove and the second groove are parts of the groove <NUM>.

In some embodiments, on the sidewall of the groove <NUM>, a separating layer 212A is included between the substrate <NUM> and the channel layer 203A. On the bottom of the groove <NUM>, a separating layer 215A is included between the substrate <NUM> and the channel layer 103A; and on the bottom of the groove <NUM>, a separating layer 213A is included between the substrate <NUM> and the barrier layer 204A.

In some embodiments, the HHMT <NUM> comprises a first electrode <NUM>, a second electrode <NUM>, and a third electrode <NUM>. The first electrode <NUM> and the second electrode <NUM> are the source and drain of the HHMT. Both are within the scope of the groove <NUM> and on the channel layer 203A and/or the barrier layer 204A. The third electrode is the gate and is positioned outside of the barrier layer 204A. It extends downwardly entering into the groove <NUM>. The third electrode <NUM> is generally not lower than the 2DHG 206A to effectively control the current intensity between the first electrode <NUM> and the second electrode <NUM>. As shown in <FIG>, the electrodes <NUM> and <NUM> are formed on the same side of the nucleation layer 202A. Because the nucleation layer 202A has certain height and width, it makes 2DHG 206A nearby disappeared and 2DHG 206A on the top diminished and further makes the current intensity between the electrodes <NUM> and <NUM> weakened. In some embodiments, the electrodes <NUM> and <NUM> are formed on two sides of the nucleation layer 202A, which may improve the withstanding voltage of the device for the grooves having the same lengths.

In some embodiments, the electrodes <NUM> and <NUM> are positioned on the top of the channel layer 203A and/or the barrier layer 204A, which may save the manufacturing working time and cost. In some embodiments, the electrodes <NUM> and <NUM> may extend downwardly entering into the groove <NUM>, like the third electrode <NUM>. This may increase the contact area between the electrodes <NUM> and <NUM> and the 2DHG 206A and improve conductive capacity. Similar structures may also be applied in other semiconductor devices and are also within protection scope of this application.

In some embodiments, the HHMT <NUM> further comprises a screening layer <NUM>. The screening layer <NUM> may occupy the right of the barrier layer 204A. It extends downwardly and covers the sidewall the barrier layer 204A within the groove <NUM>, which provides protection of the internal channel layer 203A and the barrier layer 204A. In some embodiments, the gate electrode <NUM> is formed within the screening layer <NUM> and is enveloped in the screening layer <NUM>. Thus, the screening layer <NUM> can be regarded as a gate insulating layer. In some embodiments, the material of the screening layer <NUM> may be insulating materials such as SiN, SiO<NUM>, etc. The screening layer <NUM> is helpful to reduce drain current collapse and maintain 2DEG or 2DHG produced by polarity properties. Meanwhile, the screening layer <NUM> can also reduce a leak current of the gate, avoid cracking during the temperature decrease after growth of the barrier layer <NUM> and increase ohmic contacts of the source and drain and breakdown voltage.

In some embodiments, the HHMT <NUM> further comprises a blocking layer <NUM>, which is formed as the sidewall of the groove <NUM> or a part of the same. It embraces one or both of the first electrode <NUM> and the second electrode <NUM>. The blocking layer <NUM> makes the first electrode <NUM> and the second electrode <NUM> separated from the substrate <NUM> and facilitate improvement of withstanding voltage of the HHMT <NUM>.

Based on the above, the present disclosure provides a preferable structure which has two-side 2DEG or 2DHG and has bigger contact area and higher power.

<FIG> is a top view of a dual-channel HEMT according to an embodiment of the present disclosure; and <FIG> is a sectional view of a dual-channel HEMT according to an embodiment of the present disclosure. The HEMT <NUM> shown in <FIG> may be considered a combination of two semiconductor device <NUM> shown as <FIG> and <FIG>. The parts thereof similar to the above structure are not repeated therein.

As shown in the figures, the HEMT <NUM> is within the groove <NUM> and comprises channel layers 303A and 303B and barrier layers 304A and 304B. Further, two vertical interfaces <NUM> and <NUM> are formed and thereby two heterojunctions are respectively formed. In the channel layer 303A and 303B adjacent to the barrier layers 304A and 304B, the 2DEGs 305A and 305B are formed. On the top of the channel layer 303A and 303B and/or the barrier layers 304A and 304B, a first electrode <NUM> and a second electrode <NUM> electrically connected to both of the 2DEG 305A and 305B are formed. The third electrode (gate electrode) <NUM> is formed between the barrier layers 304A and 304B, wherein the gate electrode <NUM> is configured to control the current intensity between the first electrode <NUM> and the second electrode <NUM>. In some embodiments, the nucleation layers 302A and 302B are included in the groove <NUM>.

As shown in <FIG>, the HEMT <NUM> includes two conductive channels, i.e. 2DEG 305A and 305B. The advantage of this arrangement is that the increased conductive channel may magnify conductive current and have higher power. Furthermore, in comparison with the single conductive channel, the dual conductive channels have better performance of voltage withstanding and heat resistance. Further, the electrodes having the same properties in the dual conductive channels may be share and it is not necessary to respectively form the two electrodes. This arrangement can save room and significantly save manufacturing working time and cost.

In some embodiments, this structure further comprises a screening layer <NUM> positioned between the barrier layers 304A and 304B. The screening layer <NUM> extends vertically into the groove <NUM> and its material may be insulating materials such as SiO<NUM>, etc. The screening layer <NUM> makes the devices on the two sides separated, especially improves insulation between the 2DEG 305A and 305B. It further makes capacities of enhancing the withstanding voltage and reducing the dark current significantly improved. In addition, existence of the screening layer <NUM> facilitates forming of the electrodes on the top. Because of insulation of the screening layer <NUM>, the gate electrode may be formed in the screening layer <NUM>, which makes the screening layer <NUM> as the gate insulating layer. In addition, the screening layer <NUM> can also avoid cracking during the temperature decrease after growth of the barrier layers 304A and 304B and increase ohmic contacts of the source and drain and breakdown voltage.

In some embodiments, within the groove <NUM>, first separating layers 315A and 315B are included between the channel layers 303A and 303B and the substrate <NUM> and extend horizontally. second separating layers 312A and 312B are included between the barrier layers 304A and 304B and the substrate <NUM> and extend horizontally. A spacing layer <NUM> is included between the screening layer <NUM> and the substrate <NUM> and also extends horizontally.

In some embodiments, as shown in <FIG>, it further comprises a fourth electrode <NUM> positioned on the channel layers 303A and 303B and/or the barrier layers 304A and 304B and electrically connected to 2DEG 305A and 305B together and a fifth electrode <NUM> positioned between the first electrode <NUM> and the fourth electrode <NUM> and controlling the current intensity between the first electrode <NUM> and the fourth electrode <NUM>. That is, another HEMT structure is formed in the same manner on one side of the HEMT <NUM>.

The two HEMT structures are within the same groove <NUM> and both may share the nucleation layer 302A and 302B and the first electrode <NUM>. In some embodiments, a plurality of HEMT structures may be included in the same groove <NUM>. The advantage is that it may save manufacturing cost and working time. Further, because of the distance between the devices become smaller, it allows higher integrity and improvement of usage of the substrate.

As the embodiment shown in <FIG> and <FIG>, the present disclosure may comprise dual-channel HHMT. Or, in condition that there are only two electrodes in the above structure which are respectively in ohmic and Schottky contacts with the 2DEG and/or 2DHG, a dual-channel Schottky diode may be formed. Those similar structures and functions are not described in details herein.

<FIG> is a top view of arrangement of multiple dual-channel HEMTs according to an embodiment of the present disclosure. When a plurality of structures as shown in <FIG> and <FIG> are formed on the substrate, the arrangement of respective devices are shown as <FIG>.

<FIG> and <FIG> are schematic diagrams of a dual-channel HHMT according to an embodiment of the present disclosure, wherein the structures as same as or similar to those in <FIG> and <FIG> are not repeated. In the embodiment of <FIG> and <FIG>, barrier layers 404A and 404B are respectively formed on the same sides of nucleation layers 402A and 402B outside of channel layers. The 2DHG 404A and 404B are formed in the channel layers adjacent to the barrier layers. Then, a first electrode and a second electrode connected to the 2DHG 404A and 404B are formed and thereby the HHMT is formed. The positions of the nucleation layers 402A and 402B in <FIG> are different from those in <FIG>. The former ones are positioned in the groove between the barrier layers and the channel layers, and the latter ones are positioned between the sidewalls of the groove and the channel layers away from the barriers. The position difference of the nucleation layers represents difference directions of crystal growths and also represents it is 2DEG or 2DHG formed therebetween. As understood by persons having ordinary skills in the art, the nucleation layer is not necessary in some embodiments of the present disclosure. However, whether it is 2DEG or 2DHG can also be determined according to the direction of crystal growth. In some embodiments, the electrode <NUM> is longer than the nucleation layers 402A and 402B, which can ensure adequate contact between the electrode <NUM> and the 2DHG.

In some embodiments, the semiconductor device of the present disclosure may include both 2DEG and 2DHG, wherein the 2DEG and 2DHG may be together formed in the same semiconductor device or independently formed in the semiconductor devices having respective functions. <FIG> is a schematic diagram of a semiconductor device having both 2DEG and 2DHG according to an embodiment of the present disclosure. As shown in <FIG>, a plurality of grooves <NUM>-<NUM> are formed in the substrate. Taking the semiconductor device in the groove <NUM> as an example, within the groove <NUM>, 2DEG <NUM> and 2DHG <NUM> are respectively formed on the two vertical interfaces adjacent to the barrier layer <NUM>. <FIG> only presents a part of structures of the channel layers <NUM> and the barrier layer <NUM>. Other structures in the above may also be applied in the embodiment of the <FIG>.

The present disclosure also provides a manufacturing method of the semiconductor device. The manufacturing method of the semiconductor device of the present disclosure is described below by those of manufacturing a dual-channel HEMT as an example.

<FIG> are flowchart diagrams of a method of manufacturing a dual-channel HEMT according to an embodiment of the present disclosure; wherein <FIG> are top views of the method of manufacturing a dual-channel HEMT according to an embodiment of the present disclosure and <FIG> are sectional views of the method of manufacturing a dual-channel HEMT according to an embodiment of the present disclosure. In this embodiment, the Si substrate is used as an example for manufacturing the device. As understood by persons skilled in the art, other substrates such as intrinsic GaN, Al<NUM>O<NUM> (sapphire), SiC and so on may also be used to realize similar structures.

As shown in the figures, the manufacturing method <NUM> of the HEMT comprises: at the step <NUM>, providing the Si substrate <NUM> as shown in <FIG>.

At the step <NUM>, a blocking layer <NUM> is formed on the substrate <NUM> as shown in <FIG>. The blocking layer <NUM> is formed on the substrate <NUM> by growth of SiO<NUM> with oxidation technology and it covers the whole substrate <NUM>. There are other methods to obtain the substrate covered by silicon oxide in the art. Those methods can also be applied herein.

At the step <NUM>, a plurality of first grooves are formed on the substrate as shown in <FIG>. The blocking layer <NUM> and the substrate thereunder are etched to form a plurality of grooves <NUM> having vertical surfaces and arranged horizontally, wherein the vertical surfaces <NUM> and <NUM> of the substrate within the groove <NUM> are (<NUM>) planes of the Si substrate.

In some embodiments, the number of the grooves set on the same substrate may be decided according to requirements of integrity and voltage withstanding. It is described herein with the example of <NUM> grooves. The shapes and sizes of the grooves may be pre-configured according to the practical requirements in the method related to the present disclosure. For example, when manufacturing of a semiconductor device with relatively big ratio of height to width, the depths of the grooves may be also big.

At the step <NUM>, a protection layer is formed on the surfaces of the grooves and the substrate as shown in <FIG>. In some embodiments, a SiN protection layer <NUM> is formed on the substrate <NUM> with LPCVD technology and the like. The surfaces of the substrate <NUM> and the grooves <NUM> are covered.

At the step <NUM>, a protection layer on the bottom of the grooves are patterned as shown in <FIG>. Only the protection layer formed by SiN on the vertical surfaces <NUM> and <NUM> are retained and the Si substrates <NUM> on the bottoms of the grooves <NUM> are exposed. The protection layers still cover the vertical surfaces <NUM> and <NUM> of the substrate of the substrate grooves <NUM>.

At the step <NUM>, first separating layers are formed within the grooves as shown in <FIG>. The separating layers <NUM> cover the bottoms of the grooves <NUM>. In some embodiments, the first separating layers are formed on the substrate <NUM> by growth of SiO<NUM> with oxidation technology. Because of protection layers <NUM> covering the vertical surfaces <NUM> and <NUM> of the substrate <NUM>, there is almost no separating layers <NUM> grown on the vertical surfaces <NUM> and <NUM> of the substrate <NUM>.

At the step <NUM>, the protection layers on the sidewall of the grooves are removed as shown in <FIG>. A mask is covered on the top of the blocking layer <NUM> above the substrate <NUM> and then the protection layers <NUM> on the sidewall of the grooves <NUM> are etched by the photoetching technology. After etching, the vertical surfaces <NUM> and <NUM> of the substrate <NUM> are exposed. There are other methods to remove the protection layer and expose the vertical surface of the substrate in the art. Those methods can also be applied herein.

At the step <NUM>, spacing layers are formed on the sidewalls of the grooves as shown in <FIG>. In some embodiments, the spacing layers <NUM> of SiO<NUM> are formed on the sidewalls of the grooves <NUM> by the oxidation technology. In some embodiments, the first separating layers <NUM> is thicker than the spacing layer <NUM>.

At the step <NUM>, a mask is covered on the insulating layers as shown in <FIG>. The mask <NUM> is applied to cover the blocking layer <NUM>. The mask holes <NUM> are set on the mask <NUM>. The mask holes <NUM> make the parts of the spacing layers <NUM> on the sidewall of the grooves <NUM> exposed.

At the step <NUM>, parts of the protection layers on the sidewall of the grooves <NUM> are etched through the mask holes <NUM> and parts of the substrate vertical surfaces of the groove <NUM> are exposed, and then the mask is removed as shown in <FIG>. In some embodiments, the separating layers <NUM> on the vertical surface <NUM> and <NUM> in the neighboring grooves are respectively etched by the photoetching, making the vertical surface <NUM> and <NUM> in the neighboring grooves exposed.

In some embodiments, the shapes and positions of the mask holes <NUM> may be changed according to practical requirements. In this embodiment, the vertical surfaces adjacent to each other in the neighboring grooves are selected to be exposed in order to generate the dual-channel HEMT.

As understood by persons skilled in the art, there are other technologies to form the blocking layers <NUM>, the separating layers <NUM>, and the separating layers <NUM> and make the vertical surfaces of the substrate exposed at the same time. For example, the grooves having specific shapes may be formed at first on the substrate. Then, the blocking layers <NUM>, the separating layers <NUM>, and the separating layers <NUM> are formed by oxidation. The parts of the blocking layers <NUM> are then covered by a mask. The separating layers <NUM> on the vertical surfaces of the substrate are etched by photoetching, which makes the vertical surfaces of the substrate exposed.

At the step <NUM>, the nucleation layers are formed on the vertical surfaces as shown in <FIG>. The nucleation layers <NUM> are formed on the exposed vertical surfaces <NUM> and <NUM> of the substrate <NUM>. For the Si substrate, the AlN is used in the nucleation layers <NUM> due to the melt-back effect of Ga atoms. As is known to persons skilled in the art, GaN can be directly nucleated at Al<NUM>O<NUM> (sapphire), SiC or intrinsic GaN, but crystal quality control is difficult. Therefore, the nucleation layers <NUM> in general are introduced processes. In some cases, the nucleation layers <NUM> such as low temperature GaN or AlN in step <NUM> may not be necessary to introduce.

The capacity of regional selective growth of AlN is weak. As a result, there may be some growth in the blocking layers <NUM>, the separating layers <NUM> and the separating layers <NUM>, which will have an adverse effect on the semiconductor devices. In some embodiments, the wafer can be taken out after AlN is grown. The AlN nucleation layer on the vertical surface can be retained by etching with anisotropy, while the AlN in other places can be removed, for example, by dry etching using vertical downward ion bombardment. Since the AlN on the vertical surfaces are less bombarded by ions and the AlN on other surfaces is more bombarded, only AlN on the vertical surface preserved can be achieved.

In some embodiments, the desire to remove AlN from the blocking layers <NUM>, the separating layers <NUM> and the separating layers <NUM> may also lead to aeration of corrosive gases, such as chlorine or chlorinated gas, during the formation of the nucleation layer. Due to the amorphous or polycrystalline structure of the blocking layers <NUM>, the separating layers <NUM> and the separating layers <NUM>, AlN is more difficult to nucleate at the blocking layers <NUM>, the separating layers <NUM> and the separating layers <NUM> in a chlorine atmosphere. In addition, even if AlN attachment appears in the blocking layers <NUM>, the separating layers <NUM> and the separating layers <NUM>, the AlN attached to the blocking layers <NUM>, the separating layers <NUM> and the separating layers <NUM> are also amorphous or polycrystalline. The chlorine gas has a strong corrosive effect on them and the AlN attached will be etched away by chlorine gas. The AlN of the nucleation layer is a single crystal structure, which is weakly corroded by chlorine. The AlN of the nucleation layer can grow well under the chlorine atmosphere. Therefore, this method can also realize the selective growth of the nucleated layer.

In some embodiments, if the ratio of height to width is very big, the depth of the grooves <NUM> will also increase correspondingly, which might lead to the high nucleation layers <NUM>. Because there are likely defects between the Si substrate and the GaN, it is better to form the nucleation layers <NUM> with small heights. For example, in the condition of <FIG>, a sacrificial layer such as metal, polycrystalline silicon, or silicon nitride, etc., may be formed on the bottom of the grooves <NUM>. Then, the protection layers such as silicon oxide are formed on the rest parts of the sidewalls of the grooves <NUM>. Then, the sacrificial layers are removed by isotropic etching and the parts of the sidewalls of the grooves <NUM> which are originally covered by the sacrificial layers are exposed, i.e. the vertical surfaces of the substrate. Next, the nucleation layers <NUM> are formed on the vertical surfaces of the substrate. Accordingly, the nucleation layers <NUM> with small heights are obtained, which can ensure crystal quality, improve capability of voltage withstanding, and reduce influence caused by crystal defects.

At the step <NUM>, the channel layers are formed within the grooves as shown in <FIG>. The channel layers <NUM> are formed on the nucleation layers <NUM> by epitaxial growth. As to the epitaxial growth, it is difficult to control the horizontal growth. Therefore, it is hard to keep a semiconductor structure growing completely vertically because of occurrence of multiple growth surfaces. The structure related to the present disclosure can keep continuous growth on the same surface and the electrical properties of the device can be improved. The growth in traditional devices is usually in the vertical direction from bottom to top. The structure related to the present disclosure is grown horizontally, which makes the device smoother.

In some embodiments, it may include the step of forming the buffer layers on the nucleation layers before the step of <NUM>. The buffer layers are formed by epitaxial growth on nucleation layer <NUM>. As mentioned in the above, the buffer layers are not necessary in the structure of some semiconductor devices of the present disclosure. In essence, the buffer layers and the channel layers are very similar in nature and can even be the same material. In other words, the basic structures are the channel layers/channel supply layers, and there can be the buffer layers between the channel layers and the nucleation layers.

At the step <NUM>, the second grooves are formed between two neighboring grooves as shown in <FIG>. The blocking layers <NUM> and the substrate <NUM> thereunder between neighboring grooves are etched to form the second grooves <NUM>. In some embodiments, the length of the grooves <NUM> are bigger than that of the grooves <NUM>, referring to <FIG>.

At the step <NUM>, the second separating layers are formed on the bottom of the second grooves as shown in <FIG>. In some embodiments, the screening layers <NUM> are formed on the bottom of the second grooves <NUM> by oxidation technology.

At the step <NUM>, the blocking layers and separating layers on the sidewall of the second grooves are etched and the vertical surfaces of the two sides of the channel layers are exposed as shown in <FIG>. The blocking layers <NUM> and the separating layers <NUM> on the sidewall of the second grooves <NUM> are etched by etching technology, which makes the two sides of the channel layers <NUM> in the second grooves <NUM> are exposed. The blocking layers <NUM> and the separating layers <NUM> on the bottom of the second grooves <NUM> between the second grooves and the substrate <NUM> are retained during the etching.

At the step <NUM>, the barrier layers are formed within the second grooves as shown in <FIG>. The barrier layers <NUM> are formed within the second grooves <NUM>. In some embodiments, the barrier layers <NUM> grown may fill the second grooves <NUM> and then the screening layers may be formed by etching third grooves. In a preferable embodiment, it is selected to epitaxially grow the two barrier layers from the channel layers at both sides of the second grooves <NUM> and retain the room between the two barriers so as to save the processes and avoid destruction of unnecessary etching to the crystal structure.

At the step <NUM>, the screening layers are formed between the two barrier layers as shown in <FIG>. For example, the screening layers <NUM> are formed within the grooves <NUM> by deposition. In this way, considering both neighboring two first groove and second groove, they consist of a bigger groove together, similar to the groove <NUM> in <FIG> and <FIG>. Most structures of the semiconductor device of the present disclosure are located in this bigger groove.

In some embodiments, the second grooves <NUM> are longer than the first grooves <NUM>. Because of results of selective growth of the barrier layers, the barrier layers will not fill the areas at the two ends of the second grooves <NUM> longer than the first grooves <NUM>. Therefore, the "T" shaped rooms will be formed at the two ends of the barrier layers. When forming the screening layers <NUM> in step <NUM>, the screening layer <NUM> will fill the "T" shaped rooms at the two ends of the barrier layers. In some embodiments, the "T" shaped screening layers embrace the sides of the barrier layers and make it further separated from the substrate. Such structures of the screening layers <NUM> can facilitate not only arrangement of electrodes but also separation of the electrodes from the substrate, which improves the performance of the semiconductor device.

At the step <NUM>, the mask covers, and the mask holes are left at the positions of the electrodes as shown in <FIG>. The mask <NUM> covers on the blocking layers <NUM>. The mask holes <NUM> are set on the mask <NUM>. The first electrodes, the second electrodes and the third electrodes may all be defined in this step. The first electrodes and the second electrodes may be electrically connected with the 2DEG at the two sides. In an embodiment, the third electrodes between the first electrodes and the second electrodes are positioned within the screening layers <NUM>. In this way, the screening layers <NUM> may be regarded as the gate insulating layers of the third electrodes.

At the step <NUM>, the first electrodes, the second electrodes and the third electrodes are formed as shown in <FIG>. At first, the screening layers <NUM> under the positions of the third electrodes are etched and the etching depth is not lower than the height of the 2DEG. The first electrode <NUM> is formed at the position of the first electrode, the second electrode <NUM> is formed at the position of the second electrode using electrode deposition methods and the first electrode <NUM> and the second electrode <NUM> are made to be electrically connected with the two 2DEG <NUM>. The third electrode <NUM> is formed at the position of the third electrode and the height of the third electrode <NUM> is not smaller than that of the 2DEG such that the third electrode can effectively control the current intensity between the first electrode <NUM> and the second electrode <NUM>. In some embodiments, the materials of the first electrode <NUM>, the second electrode <NUM>, and the third electrode <NUM> are not the same and three electrodes are respectively made in two phrases.

In some embodiments, the step <NUM> also comprises forming the fourth electrode <NUM> and the fifth electrode <NUM>. At the same time when forming the first electrode <NUM> and the second electrode <NUM>, the fourth electrode may be formed. At the same time when forming the third electrode <NUM>, the fifth electrode may be formed. In some embodiments, the first electrode <NUM>, the second electrode <NUM>, the third electrode <NUM>, the fourth electrode <NUM>, and the fifth electrode <NUM> can be formed at the same time to simply the processes.

In some embodiments, the electrode deposition methods may be electron beam evaporation physical deposition, chemical vapor deposition, atom layer deposition, or electrochemical deposition. The electrode material is usually metal. In some embodiments, it will also be deposition on the top surface besides the bottom during the electrode deposition. The undesired metal layers on the top surface may be removed by etching.

As shown in the structure of <FIG>, the capability of voltage withstanding of the semiconductor device is improved as the blocking layer <NUM> covers the top surface of the substrate <NUM>. To further improve the performance of the semiconductor device, the electrode parts may be modified. As to one or more of the electrodes <NUM>, <NUM>, and <NUM>, for example the second electrode <NUM> and the fourth electrode <NUM> which is usually used as the source, at the step <NUM>, the blocking layers and the substrate thereunder is etched to keep the electrodes away from the substrate and then the passivating protection layers of SiO<NUM> and so on may be formed by passivation. In another embodiments, all the substrate which are the sidewalls of the grooves may be removed and then the sidewalls of the grooves are formed again by passivating protection layers. This can further diminish the influence of the substrate sidewalls. In another embodiments, the substrate under the bottom of the grooves may be removed. The removal of the substrate under the bottom of the grooves from the final products will further improve the performance of the products.

The manufacturing method of the device related to the present disclosure, by limitation of the grooves, may form the device structures for example big ratio of height to width which are difficult to be realized by common manufacturing processes and the manufacturing flowchart are simpler. Furthermore, in some embodiments of the present disclosure, the method of the present disclosure may be implemented with the Si substrate with low cost and matured manufacturing processes, which makes the method of the present disclosure advantageous on the cost.

<FIG> is a schematic diagram of a Schottky diode according to an embodiment of the present disclosure, wherein structures which are the same as or similar to those shown in <FIG> and <FIG> are not repeated. There are not the first, second, and third electrodes in the embodiment of <FIG>. They are the cathodes 607A and 607B the anode <NUM>, wherein the cathodes 607A and 607B are connected to the 2DEG in ohmic contact and the anode <NUM> is connected to the 2DEG in Schottky contact.

In some embodiments, the cathodes 607A and 607B are provided on the barrier layers and are connected to the 2DEG in ohmic contact. The anode <NUM> is provided on the barrier layers or the screening layer connected to the 2DEG in Schottky contact. The ohmic contact between the cathodes 607A and 607B and the 2DEG are conductive in dual directions. The Schottky contact between the anode <NUM> and the 2DEG is conductive in single direction. Therefore, there is also single direction conductivity between the cathode 607A and the anode <NUM> and between the cathode 607B and the anode <NUM>. That is, the current can only flow from the anode <NUM> to the cathodes 607A and 607B.

The above structure is only exemplarily description of the technical solution of the present disclosure. In some embodiments, more semiconductor devices can be included in the same groove, providing higher integrity solution.

<FIG> is a schematic diagram of a long-groove HEMT according to an embodiment of the present disclosure. As shown in <FIG>, the channel layers 703A and 703B, the barrier layers 704A and 704B, <NUM> nucleation layers 702A-702D, <NUM> gate electrodes <NUM>, <NUM>, <NUM> and <NUM>, <NUM> source electrodes <NUM>, <NUM>, and <NUM>, and <NUM> drain electrodes <NUM> and <NUM> are included in a long groove <NUM>. In comparison with the structure of <FIG>, the long groove <NUM> in the long-groove HEMT of <FIG> is longer, and therefore it has longer channel layers, barrier layers, and 2DEG. It can be considered that the structure of <FIG> is formed by "jointing" of two structures of <FIG>. Four HEMT <NUM> of <FIG> are included in a long groove of <FIG>. The structure of <FIG> can save on-wafer area, significantly improve usage rate of the Si wafer, and further enhance structural integrity.

<FIG> is a schematic diagram of long grooves on a Si wafer according to an embodiment of the present disclosure. As shown in the figure, there are a plurality of long grooves <NUM> on the wafer <NUM>, wherein the long grooves <NUM> are arranged in parallel. One or more kinds of desire semiconductor devices are formed in every long grooves <NUM> by the methods described in the above, which can make the wafer used adequately.

Claim 1:
A semiconductor device (<NUM>), comprising:
a blocking layer (<NUM>) of insulating material formed on a substrate (<NUM>);
a groove (<NUM>) formed through the blocking layer (<NUM>) and into the substrate (<NUM>), the groove (<NUM>) having vertical sidewalls;
a first channel layer (103A) positioned within the groove (<NUM>); and
a first barrier layer (104A) positioned within the groove (<NUM>), wherein a first heterojunction having a vertical interface (<NUM>) is included between the first channel layer (103A) and the first barrier layer (104A) and 2DEG (105A) or 2DHG is formed in the first heterojunction.
a first electrode (<NUM>) being electrically connected with 2DEG or 2DHG of the first heterojunction; and
a second electrode (<NUM>) being electrically connected with 2DEG or 2DHG of the first heterojunction;
wherein the blocking layer (<NUM>) embraces the first electrode (<NUM>) and the second electrode (<NUM>) making the first electrode (<NUM>) and the second electrode (<NUM>) separated from the substrate (<NUM>), and
wherein one of the following applies:
i. one of the first electrode (<NUM>) and the second electrode (<NUM>) is in Schottky contact and the other is in ohmic contract, or
ii. the device further comprises a third electrode (<NUM>) between the first electrode (<NUM>) and the second electrode (<NUM>), configured to control current intensity between the first electrode (<NUM>) and the second electrode (<NUM>).