Patent Description:
Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices, which typically has the advantage of keeping stored data even when the device is not connected to an electrical source. <CIT> relates to substrates, assemblies, and techniques to enable a dual pedestal for a memory. <CIT> discloses a semiconductor device having a magnetic storage element. <CIT> discloses a memory cell. <CIT> relates to an integrated circuit structure including a memory element. <CIT> relates to a patterning technique of an MRAM device where an MTJ material layer placed on an IMD layer is structured by etching.

The aforementioned MR effect has also been used in magnetic field sensor areas including but not limited to for example electronic compass components used in global positioning system (GPS) of cellular phones for providing information regarding moving location to users. Currently, various magnetic field sensor technologies such as anisotropic magnetoresistance (AMR) sensors, GMR sensors, magnetic tunneling junction (MTJ) sensors have been widely developed in the market. Nevertheless, most of these products still pose numerous shortcomings such as high chip area, high cost, high power consumption, limited sensibility, and easily affected by temperature variation and how to come up with an improved device to resolve these issues has become an important task in this field.

The invention provides a method for fabricating a semiconductor device and a semiconductor device as recited in the independent claims.

Referring to <FIG> illustrate a method for fabricating a semiconductor device, or more specifically a MRAM device according to an embodiment of the present invention. As shown in <FIG>, a substrate <NUM> made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si-Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs), and a MRAM region <NUM> and a logic region (not shown) are defined on the substrate <NUM>. Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and an interlayer dielectric (ILD) layer <NUM> could also be formed on top of the substrate <NUM>. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate <NUM>, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain region, spacer, epitaxial layer, and contact etch stop layer (CESL). The ILD layer <NUM> could be formed on the substrate <NUM> to cover the MOS transistors, and a plurality of contact plugs could be formed in the ILD layer <NUM> to electrically connect to the gate structure and/or source/drain region of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

Next, an inter-metal dielectric (IMD) layer <NUM> is formed on the ILD layer <NUM>, at least a metal interconnection <NUM> is formed in the IMD layer <NUM> to electrically connect the aforementioned contact plugs, and a stop layer <NUM> is formed on the surface of the IMD layer <NUM> and metal interconnection <NUM>. In this embodiment, the stop layer <NUM> could include nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or combination thereof, the metal interconnection <NUM> preferably includes a trench conductor, and the metal interconnection <NUM> could be formed in the IMD layer <NUM> according to a single damascene process or dual damascene process. For instance, the metal interconnection <NUM> could further include a barrier layer <NUM> and a metal layer <NUM>, in which the barrier layer <NUM> could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer <NUM> could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. In this embodiment, the metal layer <NUM> preferably includes copper, the IMD layer <NUM> preferably includes an ultra low-k (ULK) dielectric layer including but not limited to for example porous material or silicon oxycarbide (SiOC), and the stop layer <NUM> preferably includes SiCN.

Next, as shown in <FIG>, a pattern transfer process is conducted to remove part of the stop layer <NUM> for forming an opening <NUM> exposing the top surface of the metal interconnection <NUM> underneath.

Next, as shown in <FIG>, an electromigration enhancing layer <NUM> is formed on the stop layer <NUM> and filling the opening <NUM> completely. According to the invention, the electromigration enhancing layer <NUM> is formed to improve the electromigration effect between the metal interconnection <NUM> underneath and the metal interconnection formed on top of the electromigration enhancing layer <NUM> afterwards such that collapse of the metal interconnection formed afterwards as a result of loss of copper atoms in the metal interconnection <NUM> could be prevented. According to the invention, the electromigration enhancing layer <NUM> includes tantalum (Ta), tantalum nitride (TaN), titanium, (Ti), titanium nitride (TiN), or combination thereof and most preferably include Ti and TiN at the same time.

Next, as shown in <FIG>, a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the electromigration enhancing layer <NUM> and even part of the stop layer <NUM> so that the top surfaces of the remaining electromigration enhancing layer <NUM> and stop layer <NUM> are coplanar. Next, an IMD layer <NUM> is formed on the surface of the stop layer <NUM> and electromigration enhancing layer <NUM> and metal interconnections <NUM>, <NUM> are formed in the IMD layer <NUM> to electrically connect the electromigration enhancing layer <NUM>. In this embodiment, each of the metal interconnections <NUM>, <NUM> could include a via conductor and the metal interconnections <NUM>, <NUM> could be formed in the IMD layer <NUM> according to a single damascene process or dual damascene process. For instance, each of the metal interconnection <NUM>, <NUM> could further include a barrier layer <NUM> and a metal layer <NUM>, in which the barrier layer <NUM> could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer <NUM> could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP).

Next, as shown in <FIG>, a MTJ stack (not shown) or stack structure is formed on the metal interconnections <NUM>, <NUM> and IMD layer <NUM>. In this embodiment, the formation of the MTJ stack could be accomplished by sequentially depositing a bottom electrode <NUM>, a pinned layer <NUM>, a barrier layer <NUM>, a free layer <NUM>, and a top electrode <NUM> on the IMD layer <NUM>. In this embodiment, the bottom electrode <NUM> and the top electrode <NUM> are preferably made of conductive material including but not limited to for example Ta, Pt, Cu, Au, Al, or combination thereof. The pinned layer <NUM> could be made of antiferromagnetic (AFM) material including but not limited to for example ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), or combination thereof, in which the pinned layer <NUM> is formed to fix or limit the direction of magnetic moment of adjacent layers. The barrier layer <NUM> could be made of insulating material including but not limited to for example oxides such as aluminum oxide (AlOx) or magnesium oxide (MgO). The free layer <NUM> could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), in which the magnetized direction of the free layer <NUM> could be altered freely depending on the influence of outside magnetic field.

Next, one or more etching process are conducted to remove part of the MTJ stack to form MTJs <NUM>, <NUM> on the metal interconnections <NUM>, <NUM>, in which bottom electrodes <NUM> are disposed under the MTJs <NUM>, <NUM> while top electrodes <NUM> are disposed on top of the MTJs <NUM>, <NUM>. It should be noted that a reactive ion etching (RIE) process and/or an ion beam etching (IBE) process could be conducted to remove part of the MTJ stack and even part of the IMD layer <NUM> for forming the MTJs <NUM>, <NUM>. Due to the characteristics of the IBE process, the top surface of the remaining IMD layer <NUM> is slightly lower than the top surface of the metal interconnections <NUM>, <NUM> after the IBE process and the top surface of the IMD layer <NUM> also reveals a curve or an arc. Next, a cap layer <NUM> is formed on the MTJs <NUM>, <NUM> and covering the surface of the IMD layer <NUM>, an IMD layer <NUM> is formed on the cap layer <NUM>, and one or more photo-etching process is conducted to remove part of the IMD layer <NUM> and part of the cap layer <NUM> to form contact holes (not shown) exposing the top electrodes <NUM>. Next, conductive materials are deposited into the contact holes and planarizing process such as CMP is conducted to form metal interconnections <NUM>, <NUM> connecting the top electrodes <NUM> underneath. Next, another stop layer <NUM> is formed on the IMD layer <NUM> and covering the metal interconnections <NUM>, <NUM>.

In this embodiment, the stop layer <NUM> preferably includes silicon nitride, but could also include other dielectric material including but not limited to for example silicon oxide, silicon oxynitride (SiON), or SiCN depending on the demand of the product. The stop layers <NUM>, <NUM> could include same or different materials while both stop layers <NUM>, <NUM> could include nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), and most preferably SiCN. Similar to the aforementioned metal interconnections, the metal interconnections <NUM>, <NUM> could be formed in the IMD layer <NUM> according to a single damascene process or dual damascene process. For instance, each of the metal interconnection <NUM>, <NUM> could further include a barrier layer <NUM> and a metal layer <NUM>, in which the barrier layer <NUM> could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer <NUM> could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

Referring again to <FIG> further illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown in <FIG>, the semiconductor device includes at least a metal interconnection <NUM> disposed on the substrate <NUM>, an electromigration enhancing layer <NUM> disposed on the surface of the metal interconnection <NUM>, a stop layer <NUM> surrounding the electromigration enhancing layer <NUM>, metal interconnections <NUM>, <NUM> disposed on the electromigration enhancing layer <NUM>, an IMD layer <NUM> surrounding the metal interconnections <NUM>, <NUM>, an MTJ <NUM> disposed on the metal interconnection <NUM>, and another MTJ <NUM> disposed on the metal interconnection <NUM>.

In this embodiment, the top surface of the electromigration enhancing layer <NUM> is even with the top surface of the stop layer <NUM>, the metal interconnections <NUM>, <NUM> and the metal interconnection <NUM> are preferably made of different materials, the metal interconnections <NUM>, <NUM> and the electromigration enhancing layer <NUM> are preferably made of different materials, and the metal interconnection <NUM> and the electromigration enhancing layer <NUM> are also made of different materials. Specifically, the metal layer <NUM> in the metal interconnection <NUM> preferably includes copper, the metal layer <NUM> in the metal interconnections <NUM>, <NUM> preferably include tungsten, and the electromigration enhancing layer <NUM> includes tantalum (Ta), tantalum nitride (TaN), titanium, (Ti), titanium nitride (TiN), or a combination thereof and most preferably includes Ti and TiN at the same time. It should be noted that even though the width of the electromigration enhancing layer <NUM> is less than the width of the metal interconnection <NUM>, according to another embodiment of the present invention it would also be desirable to adjust the width of the electromigration enhancing layer <NUM> by extending the edges of the electromigration enhancing layer <NUM> toward left and/or right so that the electromigration enhancing layer <NUM> could be extended to cover the metal interconnection <NUM> and the IMD layer <NUM> on either one side or both sides. In other words, the width of the electromigration enhancing layer <NUM> could be less than, equal to, or greater than the width of the metal interconnection <NUM>, which are all within the scope of the present invention.

Referring to <FIG> illustrates a structural view of a semiconductor device according to another embodiment of the present invention. As shown in <FIG>, in contrast to the pattern transfer process conducted in <FIG> of removing part of the stop layer <NUM> to form only a single opening <NUM> exposing the metal interconnection <NUM>, it would be desirable to adjust the number and position of the openings formed during the aforementioned pattern transfer process conducted in <FIG> by forming two openings such as a first opening (not shown) and a second opening (not shown) exposing the surface of the metal interconnection <NUM>. Next, processes conducted in <FIG> are carried out to form an electromigration enhancing layer <NUM> on the stop layer <NUM> and filling the two openings and then conduct a planarizing process such as CMP to remove part of the electromigration enhancing layer <NUM> for forming a first electromigration layer <NUM> and a second electromigration layer <NUM> in the stop layer <NUM> such that the top surface of the first electromigration enhancing layer <NUM> and the second electromigration layer <NUM> are even with the top surface of the stop layer <NUM>. Next, MTJs <NUM>, <NUM> are formed on the metal interconnections <NUM>, <NUM>, a cap layer <NUM> and IMD layer <NUM> are formed to cover the MTJs <NUM>, <NUM>, metal interconnections <NUM>, <NUM> are formed in the IMD layer <NUM> to electrically connect the top electrodes <NUM> disposed on each of the MTJs <NUM>, <NUM>, and another stop layer <NUM> is formed on the IMD layer <NUM> and the metal interconnections <NUM>, <NUM>.

In contrast to the aforementioned embodiment of forming a single electromigration enhancing layer <NUM> in the stop layer <NUM>, the pattern transfer process conducted in this embodiment preferably forms two patterned electromigration enhancing layer including the first electromigration enhancing layer <NUM> and the second electromigration layer <NUM> in the stop layer <NUM>, in which the first electromigration enhancing layer <NUM> and the second electromigration layer <NUM> are electrically connected or even directly contacting the metal interconnections <NUM>, <NUM> directly under the MTJs <NUM>, <NUM> while the top surfaces of the first electromigration enhancing layer <NUM>, the second electromigration layer <NUM>, and the stop layer <NUM> are coplanar. Similar, the widths of each of the patterned electromigration enhancing layers <NUM> could be adjusted to be less than, equal to, or greater than the width of the MTJs on top. For instance, the width of the first electromigration enhancing layer <NUM> could be less than, equal to, or greater than the width of the MTJ <NUM> and the width of the second electromigration enhancing layer <NUM> could be less than, equal to, or greater than the width of the MTJ <NUM>.

Referring to <FIG> illustrate a method for fabricating a semiconductor device, or more specifically a MRAM device according to an embodiment not covered by the claimed invention. For simplicity purpose, elements from the aforementioned embodiments are labeled with same numberings. As shown in <FIG>, a substrate <NUM> made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si-Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs), and a MRAM region <NUM> and a logic region (not shown) are defined on the substrate <NUM>.

Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and an interlayer dielectric (ILD) layer <NUM> could also be formed on top of the substrate <NUM>. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate <NUM>, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain region, spacer, epitaxial layer, and contact etch stop layer (CESL). The ILD layer <NUM> could be formed on the substrate <NUM> to cover the MOS transistors, and a plurality of contact plugs could be formed in the ILD layer <NUM> to electrically connect to the gate structure and/or source/drain region of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

Next, an inter-metal dielectric (IMD) layer <NUM> is formed on the ILD layer <NUM>, at least a metal interconnection <NUM> is formed in the IMD layer <NUM> to electrically connect the aforementioned contact plugs, and an electromigration enhancing layer <NUM> is formed on the surface of the IMD layer <NUM> and metal interconnection <NUM>. In this embodiment, the metal interconnection <NUM> preferably includes a trench conductor and the metal interconnection <NUM> could be formed in the IMD layer <NUM> according to a single damascene process or dual damascene process. For instance, the metal interconnection <NUM> could further include a barrier layer <NUM> and a metal layer <NUM>, in which the barrier layer <NUM> could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer <NUM> could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. In this embodiment, the metal layer <NUM> preferably includes copper and the IMD layer <NUM> preferably includes an ultra low-k (ULK) dielectric layer including but not limited to for example porous material or silicon oxycarbide (SiOC).

Next as shown in <FIG>, a photo-etching process is conducted to pattern the electromigration enhancing layer <NUM> by using a patterned mask to remove part of the electromigration enhancing layer <NUM> on the surface of the IMD layer <NUM> so that the remaining of the electromigration enhancing layer <NUM> still covers the entire surface of the metal interconnection <NUM>. Next, an IMD layer <NUM> is formed on the surface of the electromigration enhancing layer <NUM> and IMD layer <NUM> and metal interconnections <NUM>, <NUM> are formed in the IMD layer <NUM> to electrically connect or directly contacting the electromigration enhancing layer <NUM>. In this embodiment, each of the metal interconnections <NUM>, <NUM> could include a via conductor and the metal interconnections <NUM>, <NUM> could be formed in the IMD layer <NUM> according to a single damascene process or dual damascene process. For instance, each of the metal interconnection <NUM>, <NUM> could further include a barrier layer <NUM> and a metal layer <NUM>, in which the barrier layer <NUM> could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer <NUM> could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP).

Next, as shown in <FIG>, processes conducted in <FIG> are carried out to form MTJs <NUM>, <NUM> on the metal interconnections <NUM>, <NUM>, a cap layer <NUM> and an IMD layer <NUM> on the MTJs <NUM>, <NUM>, metal interconnections <NUM>, <NUM> in the IMD layer <NUM> to electrically connect the MTJs <NUM>, <NUM>, and a stop layer <NUM> on the IMD layer <NUM> and the metal interconnections <NUM>, <NUM>. In contrast to surrounding the electromigration enhancing layer <NUM> with a stop layer <NUM> as the top surfaces of the electromigration enhancing layer <NUM> and stop layer <NUM> are coplanar in the aforementioned embodiment, no stop layer is formed around the electromigration enhancing layer <NUM> in this embodiment as the electromigration enhancing layer <NUM> is surrounded by an IMD layer instead. It should also be noted that even though the width or sidewalls of the electromigration layer <NUM> in this embodiment are aligned with edges or sidewalls of the metal interconnection <NUM> underneath, according to other embodiment of the present invention it would also be desirable to adjust the width of the electromigration enhancing layer <NUM> so that the width of the electromigration enhancing layer <NUM> could be less than the width of the metal interconnection <NUM> or extended toward left and right to cover the metal interconnection <NUM> and the IMD layer <NUM> on either one side or both sides, which are all within the scope of the present invention.

In current fabrication of MRAM units especially during the connection between metal interconnections such as the metal interconnections <NUM>, <NUM> in the aforementioned embodiments that are made of tungsten (W) directly under MTJ arrays and metal interconnections such as the metal interconnection <NUM> on even lower level that are made of copper (Cu), collapse of tungsten metal interconnections <NUM>, <NUM> is often observed due to copper loss from metal interconnection <NUM> underneath. To resolve this issue the present invention employs a damascene process approach to form an electromigration enhancing layer made of Ta, TaN, Ti, TiN, or combination thereof on the copper metal interconnection for improving electromigration effect between the lower copper metal interconnection <NUM> and upper tungsten metal interconnections <NUM>, <NUM> so that collapse of the tungsten metal interconnections <NUM>, <NUM> could be prevented.

Claim 1:
A method for fabricating a semiconductor device, comprising:
forming a first inter-metal dielectric, IMD, layer (<NUM>) on a substrate (<NUM>); forming a first metal interconnection (<NUM>) in the first IMD layer (<NUM>);
forming a stop layer (<NUM>) on the first IMD layer (<NUM>);
forming a first opening (<NUM>) in the stop layer (<NUM>) to expose a portion the first metal interconnection (<NUM>);
forming an electromigration enhancing layer (<NUM>) in the first opening (<NUM>), wherein the electromigration enhancing layer (<NUM>) comprises Ta, TaN, Ti, and/or TiN, and top surfaces of the electromigration enhancing layer (<NUM>) and the stop layer (<NUM>) are coplanar;
forming a second IMD layer (<NUM>) on the stop layer (<NUM>) and the electromigration enhancing layer (<NUM>);
forming a second metal interconnection (<NUM>) and a third metal interconnection (<NUM>) in the second IMD layer (<NUM>) and on the electromigration enhancing layer (<NUM>);
forming a magnetic tunneling junction, MTJ, stack on the second IMD layer (<NUM>); and
etching the MTJ stack to form a first MTJ (<NUM>) on the second metal interconnection (<NUM>) and a second MTJ (<NUM>) on the third metal interconnection (<NUM>), characterized in that the second IMD layer (<NUM>) exposed from the first MTJ and second MTJ has a recessed curved top surface that is lower than top surfaces of the second metal interconnection (<NUM>) and the third metal interconnection (<NUM>).