Patent Description:
The present invention relates to non-volatile memory devices.

Currently, non-volatile memory devices formed on the planar surface of a semiconductor substrate are well known. See for example <CIT>, <CIT>, <CIT>, <CIT>, <CIT> and <CIT>. Each of these patents discloses a split gate non-volatile memory cell, where the source and drain regions are formed at the surface of the substrate, so that the channel region extending between the source and drain regions extends along the surface of the substrate. The conductivity of the channel region is controlled by a floating gate and a second gate (e.g. a word line gate) disposed over and insulated from the channel region of the substrate.

In an effort to increase the number of memory cells that can be formed in a given area of the substrate surface, trenches can be formed into the surface of the substrate, where a pair of memory cells are formed inside the trench. See for example, <CIT>, <CIT> and <CIT>. With these configurations, the source region is formed underneath the trench, whereby the channel region extends along the sidewall of the trench and the surface of the substrate (i.e. the channel region is not linear). By burying a pair of floating gates in each trench, the overall size of the memory cells as a function of substrate surface area space is reduced. Also, by burying two floating gates in each trench, pairs of memory cells sharing each trench also meant a reduction in surface area space occupied by each pair of memory cells.

There is a need to further reduce the size of pairs of memory cells as a function of substrate surface area space, so that more memory cells can be formed in any give surface area unit of the substrate.

<CIT> discloses an array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.

<CIT> discloses that the cell and the array are formed in a semiconductor substrate having a plurality of separated trenches wherein a flat surface is formed between respective trenches. The respective trenches have sidewalls and bottom walls. The respective memory cells have floating gates for storing charge. The cell has separated source/drain regions, and a channel which has two portions is formed between the regions. One side of the source/drain regions is situated on the bottom wall of the trench. The floating gate covers a first area of the channel, and is separated from the sidewall of the trench. A gate electrode controls the conductivity of the channel in a second area in the flat surface of the substrate. The other side of the source/drain regions is situated on the flat surface of the substrate. An independently controllable control gate is situated in the trench isolated from the floating gate, and capacitively coupled with the floating gate.

The aforementioned problems and needs are addressed by a twin bit memory cell that includes a semiconductor substrate having an upper surface, first and second trenches formed into the upper surface and spaced apart from each other, first and second floating gates of conductive material disposed in the first trench spaced apart from each other and insulated from the substrate, third and fourth floating gates of conductive material disposed in the second trench spaced apart from each other and insulated from the substrate, a first erase gate of conductive material disposed over and insulated from the first and second floating gates, a second erase gate of conductive material disposed over and insulated from the third and fourth floating gates, a word line gate of conductive material disposed over and insulated from a portion of the upper surface that is between the first and second trenches, a first source region formed in the substrate under the first trench, a second source region formed in the substrate under the second trench, a first control gate of conductive material disposed in the first trench, and between and insulated from the first and second floating gates, and a second control gate of conductive material disposed in the second trench, and between and insulated from the third and fourth floating gates. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

A method of forming a twin bit memory cell, includes forming first and second trenches into an upper surface of a semiconductor substrate, wherein the first and second trenches are spaced apart from each other, forming first and second floating gates of conductive material in the first trench spaced apart from each other and insulated from the substrate, forming third and fourth floating gates of conductive material in the second trench spaced apart from each other and insulated from the substrate, forming a first erase gate of conductive material over and insulated from the first and second floating gates, forming a second erase gate of conductive material over and insulated from the third and fourth floating gates, forming a word line gate of conductive material over and insulated from a portion of the upper surface that is between the first and second trenches, forming a first source region in the substrate under the first trench, forming a second source region in the substrate under the second trench, forming a first control gate of conductive material in the first trench, and between and insulated from the first and second floating gates, and forming a second control gate of conductive material in the second trench, and between and insulated from the third and fourth floating gates. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.

The present invention solves the above mentioned needs by forming two separate trenches into the surface of the substrate for a twin bit memory cell, and forming two floating gates in each trench.

The formation of a twin bit memory cell starts with a semiconductor substrate <NUM>. While only one is shown and described, it should be understood that an array of such twin bit memory cells would be formed on the same substrate <NUM> end to end. An oxide layer <NUM> is formed on the substrate. A nitride layer <NUM> is formed on the oxide layer <NUM>, and an oxide layer <NUM> is formed on the nitride layer <NUM>. The resulting structure is shown in <FIG>. A photolithography masking process is then formed to etch through the oxide layer <NUM>, nitride layer <NUM>, oxide layer <NUM> and into the substrate <NUM>, forming a pair of spaced apart trenches <NUM>. The masking step includes forming a layer of photo resist on the oxide layer <NUM>, and selectively exposing portions of the photo resist. Selected portions of the photo resist are removed, leaving portions of the oxide layer <NUM> exposed. One or more etches are performed to remove the exposed portions of the oxide layer <NUM>, and the underlying portions of the nitride layer <NUM>, oxide layer <NUM> and substrate <NUM>. The resulting structure is shown in <FIG> (after removal of the photo resist).

An oxide etch is used remove oxide layer <NUM>, and an oxide formation step is performed (e.g., thermal oxidation) to form oxide layer <NUM> on the exposed silicon substrate surfaces of trenches <NUM>, as shown in <FIG>. An implantation process is performed to form a source region <NUM> (i.e. a region having a second conductivity type different than the first conductivity type of the substrate) in the substrate portion underneath each trench <NUM>. A layer of polysilicon <NUM> is then deposited over the structure, filling each trench <NUM> with polysilicon <NUM>, as shown in <FIG>. The portions of polysilicon <NUM> above the surface of the substrate are removed (e.g., by CMP and etch back), leaving blocks of poly <NUM> in the substrate portion of trenches <NUM>. The upper surfaces of poly blocks <NUM> can be even with the upper surface of the substrate, or the etch back can be adjusted so that the upper surfaces of poly blocks <NUM> are above the substrate surface (i.e., the poly blocks <NUM> have an upper portion extending above the level of the substrate), or below the substrate surface (i.e., the poly blocks do not fully fill the portion of the trenches formed in the substrate). Preferably, the upper surfaces of the poly blocks <NUM> are substantially even with the substrate surface as shown in <FIG>.

Oxide spacers <NUM> are formed along the nitride sidewalls of trenches <NUM> by depositing a layer of oxide, following by an oxide etch, leaving spacers <NUM> of the oxide, as shown in <FIG>. Formation of spacers is well known in the art, and includes forming a conformal layer of material over a structure, followed by an etch that removes the material except for those portions along vertically oriented structural features. An oxide formation step (e.g., thermal oxidation) is then used to form a layer of oxide <NUM> on the exposed upper surfaces of poly blocks <NUM>. A polysilicon layer is formed over the structure, and partially removed (e.g., CMP and etch back), leaving blocks of polysilicon <NUM> disposed on oxide layer <NUM> and between spacers <NUM>, as shown in <FIG>. Nitride <NUM> is then removed by a nitride etch, as shown in <FIG>. A layer of polysilicon is formed over the structure, which is partially removed by CMP, leaving poly blocks <NUM> disposed between the back sides of spacers <NUM> (i.e., spacers <NUM> are disposed between poly blocks <NUM> and <NUM>). A word line <NUM> and word line contacts <NUM> are formed (e.g. of a metal material) to electrically connect the poly blocks <NUM> together. The final structure is shown in <FIG>.

As shown in <FIG>, the twin bit memory cell includes a pair of floating gates <NUM> in trenches <NUM> and are insulated from the substrate by oxide <NUM>. The upper surfaces of the floating gates are preferably even with the upper surface of substrate <NUM>, but could extend above the height of the substrate upper surface, or be disposed below the surface of the substrate, if desired. An erase gate <NUM> is disposed over and insulated from each of the floating gates <NUM>. A word line gate <NUM> is disposed between the erase gates <NUM>, and is disposed over and insulated from the substrate. The twin bit memory cell also includes a channel region <NUM> of the substrate that extends from the source region <NUM> under one of the floating gates <NUM>, along a sidewall of that trench <NUM>, along the surface of the substrate, along a sidewall of the other trench <NUM>, and to the source region <NUM> under the other floating gate <NUM>. The conductivity of the portions of the channel region along the trenches are controlled by the floating gates <NUM>. The conductivity of the portion of the channel region along the surface of the substrate <NUM> is controlled by the word line gate <NUM>. Programming of the floating gates is enhanced because the horizontal portion of the channel region is aimed at the floating gate, which enhances hot electron injection. Miniaturization of the twin bit memory cell pair is achieved because each trench contains only a single floating gate, where the dimensions of the floating gate are dictated by the trench dimensions, the channel region is folded to extend downwardly into the substrate instead of extending entirely along the substrate surface, and no drain region is required, reducing cell height and cell lateral dimensions.

The twin bit memory cell can store a bit of information in each floating gate. The cell operation is as follows. To program the right hand floating gate, the erase gates <NUM> are both placed at a positive voltage, such as <NUM> volts, which is coupled to the floating gates <NUM>. The word line gate <NUM> is placed at a positive voltage, such as <NUM> volt, to turn on the underlying channel region portion. A positive voltage is placed on the right hand source region <NUM>, and a current of around <NUM>µA is supplied to the left hand source region <NUM>. Electrons from the left hand source region <NUM> will travel along the channel region portion adjacent the left hand floating gate (which is turned on by the coupled positive voltage from the left hand erase gate), along the channel region portion under the word line gate <NUM>, until the electrons see the positive voltage coupled onto the right hand floating gate, where some electrons are deposited onto the right hand floating gate through hot electron injection. Programming the left hand floating gate is performed the same way, but reversing the voltages and current. To erase the floating gates (i.e., remove electrons therefrom), a high voltage (e.g., <NUM> volts) is applied to the erase gates <NUM>, where electrons tunnel from the floating gates to the erase gates via Fowler-Nordheim tunneling. To read the right hand floating gate, a positive voltage (e.g., Vcc) is applied to the word line gate <NUM> to turn on that portion of the channel region. A positive voltage is applied to the left hand erase gate <NUM> (which is coupled to the left hand floating gate to turn on that portion of the channel region). A positive voltage is applied to the left hand source region (e.g., <NUM> - <NUM> volt). A small positive voltage is supplied to the right hand erase gate, which is coupled to the right hand floating gate. This coupled voltage is high enough to turn on the channel region adjacent the right hand floating gate only if the floating is erased of electrons. Current is supplied to the right hand source region. If current flows along the channel region, then the right hand floating gate is read to be in its erased state. If low or no current flows along the channel region, then the right hand floating gate is read to be in its programmed state. Reading the left hand floating gate is performed the same way, but reversing the voltages and current. These operations are performed without the need for a third source/drain region between the floating gates using multiple channel regions, and instead are performed using a single continuous channel region extending from one source region to another source region.

<FIG> illustrate the formation of another embodiment not part of the present invention. The formation of this embodiment starts with the same structure shown in <FIG>, except no source regions <NUM> are formed under the trenches, as shown in <FIG>. Nitride <NUM> is removed by nitride etch. Source regions <NUM> are then formed by photolithographic and implantation steps into the surface portion of the substrate adjacent alternate pairs of floating gates <NUM>, as shown in <FIG>. A layer of polysilicon is formed over the structure, which is partially removed by CMP, leaving poly blocks <NUM> disposed between the back sides of spacers <NUM> (i.e., spacers <NUM> are disposed between poly blocks <NUM> and <NUM>). A word line <NUM> and word line contacts <NUM> are formed (e.g. of a metal material) to electrically connect the poly blocks <NUM> together. The final structure is shown in <FIG>.

As shown in <FIG>, the twin bit memory cell is similar to that of <FIG>, except the source regions <NUM> are formed at the substrate surface, instead of being disposed underneath the floating gates. The channel regions <NUM> still extend along the trenches and substrate surface. Therefore the twin bit memory cell is programmed, erased and read in a manner similar to that described with respect to <FIG>.

<FIG> illustrates an optional modification to the second embodiment. The twin bit memory cell is the same as that shown in <FIG>, except that the poly block and oxide layer over the source region <NUM> is removed. A bit line contact <NUM> is formed that extends between and electrically connects the source regions <NUM> to a conductive bit line <NUM>.

<FIG> illustrate the formation of a device according to the invention. The formation starts with the same structure shown in <FIG>, except without the formation of the source regions, as shown in <FIG>. An anisotropic poly etch is performed to remove the exposed portions of poly blocks <NUM> between spacers <NUM>, leaving two separate poly blocks <NUM> in each trench. An implantation process is then performed to form a source region <NUM> under each trench, as shown in <FIG>. An insulation layer <NUM> is formed over the structure, as shown in <FIG>. Preferably, insulation layer <NUM> is an ONO layer, meaning it has oxide, nitride, oxide sublayers. A poly deposition and etch process (e.g., CMP and etch back) is performed to form poly blocks <NUM> in the bottom of trenches <NUM>, as shown in <FIG>. Oxide is deposited over the structure, followed by CMP oxide removal, which fills the trenches with oxide <NUM>, as shown in <FIG>. An oxide etch is performed to remove the oxide in the top portions of the trenches, to expose the top portions of poly blocks <NUM>, as shown in <FIG>. An oxide deposition and etch is used to form oxide layer <NUM> and oxide spacer <NUM> over each of the exposed portions of poly blocks <NUM>, as shown in <FIG>. Nitride layer <NUM> is removed by nitride etch. A poly deposition and CMP is performed to form poly blocks <NUM> over poly blocks <NUM>, and poly blocks <NUM> on oxide <NUM> over the substrate surface. A word line <NUM> and word line contacts <NUM> are formed (e.g. of a metal material) to electrically connect the poly blocks <NUM> together. The final structure is shown in <FIG>.

As shown in <FIG>, each trench includes two floating gates <NUM>, each one being for a different twin bit memory cell. Poly block <NUM> serves as a control gate disposed in the trench and between floating gates of different twin bit memory cells. The erase gate is disposed over the floating gates in each trench, with a lower narrower portion that extends into the trench, and a wider upper portion that extends up and over the floating gates, so that the erase gate wraps around the upper edges of the floating gates for enhanced Fowler Nordheim tunneling efficiency. The channel region <NUM> extends between source regions <NUM>, along the trench sidewalls and along the substrate surface. Cell size is reduced by forming the floating gates in trenches with non-linear channel regions, by not having a separate drain region, and operating the memory cell as a twin bit cell as opposed to two separately operating memory cells.

The twin bit memory cell of the invention operates similarly to the other two embodiments described above. To program the right hand floating gate, the erase gates <NUM> are both placed at a positive voltage, such as <NUM> volts, which are coupled to the floating gates <NUM>. The word line gate <NUM> is placed at a positive voltage, such as <NUM> volt, to turn on the underlying channel region portion. A positive voltage is applied to the left hand control gate <NUM>, which is coupled to the left hand floating gate to turn on that portion of the channel region. A positive voltage is placed on the right hand source region <NUM>, and a current of around <NUM>µA is supplied to the left hand source region <NUM>. A positive voltage may be applied to the right hand control gate. Electrons from the left hand source region <NUM> will travel along the channel region portion adjacent the left hand floating gate (which is turned on by the coupled positive voltage to the left hand floating gate), along the channel region portion under the word line gate <NUM>, until they see the positive voltage coupled onto the right hand floating gate from the erase gate and/or control gate, where some electrons are deposited on the right hand floating gate through hot electron injection. Programming the left hand floating gate is performed the same way, but reversing the voltages and current. To erase the floating gates (i.e., remove electrons therefrom), a high voltage (e.g., <NUM> volts) is applied to the erase gates <NUM>, where electrons tunnel from the floating gates to the erase gates via Fowler-Nordheim tunneling. To read the right hand floating gate, a positive voltage (e.g., Vcc) is applied to the word line gate <NUM>. A positive voltage is applied to the left hand erase gate <NUM> and/or left hand control gate <NUM> (which is coupled to the left hand floating gate to turn on that portion of the channel region). A positive voltage is applied to the left hand source region (e.g., <NUM> - <NUM> volt). A small positive voltage is supplied to the right hand erase gate and/or right hand control gate, which is coupled to the right hand floating gate. This voltage is high enough to turn on the channel region adjacent the right hand floating gate only if the floating is erased of electrons. Current is supplied to the right hand source region. If current flows along the channel region, then the right hand floating gate is read to be in its erased state. If low or no current flows along the channel region, then the right hand floating gate is read to be in its programmed state. Reading the left hand floating gate is performed the same way, but reversing the voltages and current.

<FIG> is the schematic diagram of an array of the twin bit memory cells of <FIG>, <FIG> and <FIG>. The operational voltages and currents for such an array is illustrated in Table <NUM> below.

<FIG> is the schematic diagram of an array of the twin bit memory cells of <FIG>. The operational voltages and currents for such an array is illustrated in Table <NUM> below.

It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of any claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the memory cell configurations of the present invention. Single layers of material could be formed as multiple layers of such or similar materials, and vice versa. Lastly, the terms "forming" and "formed" as used herein shall include material deposition, material growth, or any other technique in providing the material as disclosed or claimed.

Claim 1:
A twin bit memory cell, comprising:
a semiconductor substrate (<NUM>) having an upper surface;
first and second trenches (<NUM>) formed into the upper surface and spaced apart from each other;
first and second floating gates (<NUM>) of conductive material disposed in the first trench spaced apart from each other and insulated from the substrate;
third and fourth floating gates (<NUM>) of conductive material disposed in the second trench spaced apart from each other and insulated from the substrate;
a first erase gate (<NUM>) of conductive material disposed over and insulated from the first and second floating gates;
a second erase gate (<NUM>) of conductive material disposed over and insulated from the third and fourth floating gates;
a word line gate (<NUM>) of conductive material disposed over and insulated from a portion of the upper surface that is between the first and second trenches;
a first source region (<NUM>) formed in the substrate under the first trench;
a second source region (<NUM>) formed in the substrate under the second trench;
a first control gate (<NUM>) of conductive material disposed in the first trench, and between and insulated from the first and second floating gates;
a second control gate (<NUM>) of conductive material disposed in the second trench, and between and insulated from the third and fourth floating gates;
wherein a continuous channel region (<NUM>) of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.