Patent Description:
A charge-trapping material can be used in non-volatile memory devices to store a charge which represents a data state. The charge-trapping material can be arranged vertically in a three-dimensional (3D) stacked memory structure. One example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture which comprises a stack of alternating conductive and dielectric layers. A memory hole is formed in the stack and a NAND string is then formed by filling the memory hole with materials including a charge-trapping layer to create a vertical column of memory cells. A straight NAND string extends in one memory hole. Control gates of the memory cells are provided by the conductive layers.

Some non-volatile memory devices are used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two ranges of threshold voltages that correspond to two data states: an erased state (e.g., data "<NUM>") and a programmed state (e.g., data "<NUM>"). Such a device is referred to as a binary or two-state device.

A multi-state (or multi-level) non-volatile memory is implemented by identifying multiple, distinct allowed ranges of threshold voltages. Each distinct rang of threshold voltages corresponds to a data state assigned a predetermined value for the set of data bits. The specific relationship between the data programmed into the memory cell and the ranges of threshold voltages depends upon the data encoding scheme adopted for the memory cells. For example, <CIT> and <CIT> both describe various data encoding schemes for multi-state flash memory cells. Although multi-state non-volatile memory can store more data than binary non-volatile memory, the process for programming and verifying the programming can take longer for multi-state non-volatile memory.

<CIT>, over which the independent claim is characterised, discloses apparatuses with vertical strings of memory cells and support circuitry.

<CIT> discloses a three-dimensional semiconductor memory device.

<CIT> discloses a metal replacement process for low resistance source contacts in 3D NAND.

<CIT> discloses a semiconductor memory device having insulation patterns and cell gate patterns.

Like-numbered elements refer to common components in the different figures.

According to one aspect a method of fabricating a monolithic three dimensional memory structure is provided as claimed in claim <NUM>.

The following discussion provides details of one example of a suitable structure for a memory device that can implement the proposed technology.

<FIG> is a perspective view of a three dimensional (3D) stacked non-volatile memory device <NUM>, which includes a substrate <NUM>. On and above substrate <NUM> are example blocks BLK0 and BLK1 of memory cells (non-volatile storage elements). Also on substrate <NUM> is peripheral area <NUM> with support circuits for use by blocks BLK0 and BLK1. Substrate <NUM> also can carry circuits under the blocks, along with one or more lower metal layers which are patterned in conductive paths to carry signals of the circuits.

Blocks BLK0 and BLK1 are formed in an intermediate region <NUM> of memory device <NUM>. In an upper region <NUM> of memory device <NUM>, one or more upper metal layers are patterned in conductive paths to carry signals of the circuits. Each of blocks BLK0 and BLK1 includes a stacked area of memory cells, where alternating levels of the stack represent word lines. Although two blocks BLK0 and BLK1 are depicted as an example, additional blocks can be used, extending in the x- and/or y-directions.

In one example implementation, the length of the plane in the x-direction, represents a direction in which signal paths for word lines extend (a word line or SGD line direction), and the width of the plane in the y-direction, represents a direction in which signal paths for bit lines extend (a bit line direction). The z-direction represents a height of the memory device.

<FIG> is a functional block diagram of an example memory device <NUM>, which is an example of the 3D stacked non-volatile memory device <NUM> of <FIG>. The components depicted in <FIG> are electrical circuits. Memory device <NUM> includes one or more memory die <NUM>. Each memory die <NUM> includes a three dimensional memory structure <NUM> of memory cells (such as, for example, a 3D array of memory cells), control circuitry <NUM>, and read/write circuits <NUM>. In other embodiments, a two dimensional array of memory cells can be used.

Memory structure <NUM> is addressable by word lines via a row decoder <NUM> and by bit lines via a column decoder <NUM>. Read/write circuits <NUM> include multiple sense blocks SB1, SB2,. , SBp (sensing circuitry) and allow a page of memory cells to be read or programmed in parallel. In some systems, a controller <NUM> is included in the same memory device <NUM> (e.g., a removable storage card) as the one or more memory die <NUM>. However, in other systems, controller <NUM> can be separated from memory die <NUM>.

In some embodiments, one controller <NUM> will communicate with multiple memory die <NUM>. In other embodiments, each memory die <NUM> has its own controller. Commands and data are transferred between a host <NUM> and controller <NUM> via a data bus <NUM>, and between controller <NUM> and the one or more memory die <NUM> via lines <NUM>. In one embodiment, memory die <NUM> includes a set of input and/or output (I/O) pins that connect to lines <NUM>.

Memory structure <NUM> may include one or more arrays of memory cells including a 3D array. Memory structure <NUM> may include a monolithic three dimensional memory structure in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates. Memory structure <NUM> may include any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. Memory structure <NUM> may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

Control circuitry <NUM> cooperates with read/write circuits <NUM> to perform memory operations (e.g., erase, program, read, and others) on memory structure <NUM>, and includes a state machine <NUM>, an on-chip address decoder <NUM>, and a power control module <NUM>. State machine <NUM> provides chip-level control of memory operations. Code and parameter storage <NUM> may be provided for storing operational parameters and software. In one embodiment, state machine <NUM> is programmable by the software stored in code and parameter storage <NUM>. In other embodiments, state machine <NUM> does not use software and is completely implemented in hardware (e.g., electronic circuits).

On-chip address decoder <NUM> provides an address interface between addresses used by host <NUM> or memory controller <NUM> to the hardware address used by decoders <NUM> and <NUM>. Power control module <NUM> controls the power and voltages supplied to the word lines and bit lines during memory operations. Power control module <NUM> can include drivers for word line layers (discussed below) in a 3D configuration, select transistors (e.g., SGS and SGD transistors, described below) and source lines. Power control module <NUM> may include charge pumps for creating voltages. Sense blocks SB1, SB2,. , SBp include bit line drivers. An SGS transistor is a select gate transistor at a source end of a NAND string, and an SGD transistor is a select gate transistor at a drain end of a NAND string.

Any one or any combination of control circuitry <NUM>, state machine <NUM>, decoders <NUM>/<NUM>/<NUM>, code and parameter storage <NUM>, power control module <NUM>, sense blocks SB1, SB2,. , SBp, read/write circuits <NUM>, and controller <NUM> can be considered one or more control circuits that performs the functions described herein.

The (on-chip or off-chip) controller <NUM> may include storage devices (memory) such as ROM 214a and RAM 214b and a processor 214c. Storage devices ROM 214a and RAM 214b include code such as a set of instructions, and processor 214c is operable to execute the set of instructions to provide the functionality described herein. Alternatively or additionally, processor 214c can access code from a storage device in memory structure <NUM>, such as a reserved area of memory cells connected to one or more word lines.

Multiple memory elements in memory structure <NUM> may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND flash memory) typically contain memory elements connected in series. A NAND string is an example of a set of series-connected memory cells and select gate transistors.

A NAND flash memory array may be configured so that the array is composed of multiple NAND strings of which a NAND string is composed of multiple memory cells sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory cells may be otherwise configured.

The memory cells may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations, or in structures not considered arrays.

A three dimensional memory array is arranged so that memory cells occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the z direction is substantially perpendicular and the x and y directions are substantially parallel to the major surface of the sub strate).

As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory cells. The vertical columns may be arranged in a two dimensional configuration, e.g., in an x-y plane, resulting in a three dimensional arrangement of memory cells, with memory cells on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.

By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level and other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.

A person of ordinary skill in the art will recognize that this technology is not limited to a single specific memory structure, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.

<FIG> is a block diagram depicting software modules for programming one or more processors in controller <NUM> of <FIG>. <FIG> depicts read module <NUM>, programming module <NUM>, and erase module <NUM> being stored in ROM 214a. These software modules also can be stored in RAM or memory die <NUM>. Read module <NUM> includes software that programs processor(s) 214c to perform read operations. Programming module <NUM> includes software that programs processor(s) 214c to perform programming operations (including verification of programming). Erase module <NUM> includes software that programs processor(s) 214c to perform erase operations. Based on the software, controller <NUM> instructs memory die <NUM> to perform memory operations.

<FIG> is a block diagram depicting software modules for programming state machine <NUM> of <FIG> (or other processor on memory die <NUM>). <FIG> depicts read module <NUM>, programming module <NUM>, and erase module <NUM> being stored in code and parameter storage <NUM>. These software modules can also be stored in RAM or in memory structure <NUM> of <FIG>. Read module <NUM> includes software that programs state machine <NUM> to perform read operations. Programming module <NUM> includes software that programs state machine <NUM> to perform programming operations (including verification of programming). Erase module <NUM> includes software that programs state machine <NUM> to perform erase operations. Alternatively, state machine <NUM> (which is an electronic circuit) can be completely implemented with hardware so that no software is needed to perform these functions.

<FIG> is a block diagram explaining one example organization of memory structure <NUM>, which is divided into two planes <NUM> and <NUM>. Each plane is then divided into M blocks. In one example, each plane has about <NUM> blocks. However, different numbers of blocks and planes can also be used.

<FIG> depict an example 3D NAND structure. <FIG> is a block diagram depicting a top view of a portion of one block from memory structure <NUM>. The portion of the block depicted in <FIG> corresponds to portion <NUM> in block <NUM> of <FIG>. The block depicted in <FIG> extends in the direction of arrow <NUM> and in the direction of arrow <NUM>. In one embodiment, the memory array will have <NUM> layers. Other embodiments have less than or more than <NUM> layers. However, <FIG> only shows the top layer.

<FIG> depicts a plurality of circles that represent the vertical columns. Each of the vertical columns include multiple select transistors and multiple memory cells. In one embodiment, each vertical column implements a NAND string. More details of the vertical columns are provided below. Because the block depicted in <FIG> extends in the direction of arrow <NUM> and in the direction of arrow <NUM>, the block includes more vertical columns than depicted in <FIG>.

<FIG> also depicts a set of bit lines <NUM>. <FIG> shows twenty four bit lines because only a portion of the block is depicted. In other embodiments, more than twenty four bit lines are connected to vertical columns of the block. Each of the circles representing vertical columns has an "x" to indicate its connection to one bit line.

The block depicted in <FIG> includes a set of local interconnects <NUM>, <NUM>, <NUM>, <NUM> and <NUM> that connect the various layers to a source line below the vertical columns. Local interconnects <NUM>, <NUM>, <NUM>, <NUM> and <NUM> also serve to divide each layer of the block into four regions. For example, the top layer depicted in <FIG> is divided into regions <NUM>, <NUM>, <NUM> and <NUM>.

In the layers of the block that implement memory cells, the four regions are referred to as word line fingers that are separated by the local interconnects. In one embodiment, the word line fingers on a common level of a block connect together at the end of the block to form a single word line. In another embodiment, the word line fingers on the same level are not connected together.

In one example implementation, a bit line only connects to one vertical column in each of regions <NUM>, <NUM>, <NUM> and <NUM>. In that implementation, each block has sixteen rows of active columns and each bit line connects to four rows in each block. In one embodiment, all of four rows connected to a common bit line are connected to the same word line (via different word line fingers on the same level that are connected together). Therefore, the system uses the source select lines and the drain select lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase).

Although <FIG> shows each region having four rows of vertical columns, four regions and sixteen rows of vertical columns in a block, those exact numbers are an example implementation. Other embodiments may include more or less regions per block, more or less rows of vertical columns per region and more or less rows of vertical columns per block.

<FIG> also shows the vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the vertical columns are not staggered.

<FIG> depicts a portion of an embodiment of three dimensional memory structure <NUM> showing a cross-sectional view along line AA of <FIG>. This cross-sectional view cuts through vertical columns <NUM> and <NUM> and region <NUM> (see <FIG>). The structure of <FIG> includes two drain select layers (SGD1 and SGD1), two source select layers (SGS1 and SGS2), four dummy word line layers (DWLL1a, DWLL1b, DWLL2a and DWLL2b), and thirty two word line layers (WLL0-WLL31) for connecting to data memory cells. Other embodiments can implement more or less than two drain select layers, more or less than two source select layers, more or less than four dummy word line layers, and more or less than thirty two word line layers.

Vertical columns <NUM> and <NUM> are depicted protruding through the drain select layers, source select layers, dummy word line layers and word line layers. In one embodiment, each of vertical columns <NUM> and <NUM> comprises a NAND string. Vertical columns <NUM> and <NUM> and the layers listed below are disposed above substrate <NUM>, an insulating film <NUM> on substrate <NUM>, and a source line SL on insulating film <NUM>. Vertical column <NUM> is connected to Bit Line <NUM> via connector <NUM>. Local interconnects <NUM> and <NUM> are also depicted.

For ease of reference, drain select layers (SGD1 and SGD1), source select layers (SGS1 and SGS2), dummy word line layers (DWLL1a, DWLL1b, DWLL2a and DWLL2b), and word line layers (WLL0-WLL31) collectively are referred to as the conductive layers. In one embodiment, the conductive layers are made from a combination of TiN and Tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as Tungsten or metal silicide. In some embodiments, different conductive layers can be formed from different materials.

Between conductive layers are dielectric layers DL0-DL19. For example, dielectric layers DL10 is above word line layer WLL26 and below word line layer WLL27. In one embodiment, the dielectric layers are made from SiO<NUM>. In other embodiments, other dielectric materials can be used to form the dielectric layers.

The word line layer WLL0-WLL31 connect to memory cells (also called data memory cells). Dummy word line layers DWLL1a, DWLL1b, DWLL2a and DWLL2b connect to dummy memory cells. A dummy memory cell, also referred to as a non-data memory cell, does not store user data, whereas a data memory cell is eligible to store user data. Thus, data memory cells may be programmed. Drain select layers SGD1 and SGD1 are used to electrically connect and disconnect NAND strings from bit lines. Source select layers SGS1 and SGS2 are used to electrically connect and disconnect NAND strings from the source line SL.

<FIG> depicts a perspective view of the conductive layers (SGD1, SGD1, SGS1, SGS2, DWLL1a, DWLL1b, DWLL2a, DWLL2b, and WLL0-WLL31) for the block that is partially depicted in <FIG>. As mentioned above with respect to <FIG>, local interconnects <NUM>, <NUM>, <NUM>, <NUM> and <NUM> break up each conductive layers into four regions. For example, drain select gate layer SGD1 (the top layer) is divided into regions <NUM>, <NUM>, <NUM> and <NUM>. Similarly, word line layer WLL31 is divided into regions <NUM>, <NUM>, <NUM> and <NUM>. For word line layers (WLL0-WLL31), the regions are referred to as word line fingers; for example, word line layer WLL31 is divided into word line fingers <NUM>, <NUM>, <NUM> and <NUM>.

<FIG> depicts a cross sectional view of region <NUM> of <FIG> that includes a portion of vertical column <NUM>. In one embodiment, the vertical columns are round and include four layers. In other embodiments, however, more or less than four layers can be included and other shapes can be used. In one embodiment, vertical column <NUM> includes an inner core layer <NUM> that is made of a dielectric, such as SiO<NUM>. Other materials can also be used. Surrounding inner core <NUM> is vertical polysilicon channel <NUM>. Materials other than polysilicon can also be used. Note that vertical polysilicon channel <NUM> connects to the bit line. Surrounding vertical polysilicon channel <NUM> is a tunneling dielectric <NUM>. In one embodiment, tunneling dielectric <NUM> has an oxide-nitride-oxide (ONO) structure. Surrounding tunneling dielectric <NUM> is charge trapping layer <NUM>, such as (for example) a specially formulated silicon nitride that increases trap density.

<FIG> depicts dielectric layers DLL11, DLL12, DLL13, DLL14 and DLL15, as well as word line layers WLL27, WLL28, WLL29, WLL30, and WLL31. Each of the word line layers includes a word line region <NUM> surrounded by an aluminum oxide layer <NUM>, which is surrounded by a blocking oxide (SiOz) layer <NUM>. The physical interaction of the word line layers with the vertical column forms the memory cells. Thus, a memory cell, in one embodiment, comprises vertical polysilicon channel <NUM>, tunneling dielectric <NUM>, charge trapping layer <NUM>, blocking oxide layer <NUM>, aluminum oxide layer <NUM> and word line region <NUM>.

For example, word line layer WLL31 and a portion of vertical column <NUM> comprise a memory cell MC1. Word line layer WLL30 and a portion of vertical column <NUM> comprise a memory cell MC2. Word line layer WLL29 and a portion of vertical column <NUM> comprise a memory cell MC3. Word line layer WLL28 and a portion of vertical column <NUM> comprise a memory cell MC4. Word line layer WLL27 and a portion of vertical column <NUM> comprise a memory cell MC5. In other architectures, a memory cell may have a different structure; however, the memory cell would still be the storage unit.

When a memory cell is programmed, electrons are stored in a portion of charge trapping layer <NUM> which is associated with the memory cell. These electrons are drawn into charge trapping layer <NUM> from vertical polysilicon channel <NUM>, through tunneling layer <NUM>, in response to an appropriate voltage on word line region <NUM>. The threshold voltage (Vth) of a memory cell is increased in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel or holes recombine with electrons.

Referring again to <FIG>, each of vertical columns <NUM> and <NUM> is a NAND string disposed above and coupled via source select layers SGS1 and SGS2 to a source line SL. In particular, bottom portions of the NAND strings are in electrical contact with source line SL, and the configuration depicted in <FIG> is sometimes referred to as a bottom source line contact configuration. As the height of vertical columns <NUM> and <NUM> increases with technology scaling, implementing memory structures with a bottom source configuration, such as depicted in <FIG> becomes technically challenging. In particular, etching the bottom portion of each memory hole becomes increasingly difficult as the memory hole aspect ratio increases.

<FIG> are cross-sectional views of an embodiment of a three-dimensional stacked non-volatile memory structure <NUM> that includes an array of NAND strings, including NAND strings <NUM>, <NUM>, <NUM> and <NUM> disposed above a substrate <NUM>. Each of NAND strings <NUM>, <NUM>, <NUM> and <NUM> has a corresponding drain end 502d, 504d, 506d and 508d, respectively, at a top of the stack, and a corresponding source end <NUM>, <NUM>, <NUM> and <NUM>, respectively, at a bottom of the stack.

NAND strings <NUM>, <NUM>, <NUM> and <NUM> include conductive layers (SGD, WLL0-WLL4, and SGS) and dielectric layers (DL0-DL7). Each of NAND strings <NUM>, <NUM>, <NUM> and <NUM> also has a corresponding vertical polysilicon channel 502c, 504c, 506c and 508c, respectively. Portions of each vertical polysilicon channel 502c, 504c, 506c and 508c are surrounded by a corresponding outer layer 502o, 504ο, 506o and 508o, respectively, which may include one or more layers, such as tunneling dielectric <NUM> and charge trapping layer <NUM> of <FIG>. To simplify the drawings, each of outer layers 502o, 504ο, 506o and 508o is depicted as a single layer.

Each of NAND strings <NUM>, <NUM>, <NUM> and <NUM> includes a corresponding region 502r, 504r, 506r and 508r, respectively, in which outer layers 502o, 504ο, 506o and 508o, respectively, have been removed from vertical polysilicon channels 502c, 504c, 506c and 508c, respectively. In regions 502r, 504r, 506r and 508r, vertical polysilicon channels 502c, 504c, 506c and 508c, respectively have peripheral exteriors 502w, 504w, 506w and 508w, respectively. In an embodiment, regions 502r, 504r, 506r and 508r, are located at a distance d above a lower end of NAND strings <NUM>, <NUM>, <NUM> and <NUM>, respectively. Distance d may be between about <NUM> angstroms and about <NUM> angstroms, although other distances may be used.

A dielectric material layer <NUM>, such as SiO<NUM>, is disposed on substrate <NUM>, and a source line <NUM>, such as tungsten, is disposed on dielectric material layer <NUM>. A memory hole extends through the stack of alternating conductive and dielectric layers. In an embodiment, the memory hole also extends through source line <NUM>. A NAND string is then formed by filling the memory hole with materials including a charge-trapping layer to create a vertical column of memory cells. A straight NAND string extends in one memory hole.

Peripheral exteriors 502w, 504w, 506w and 508w of vertical polysilicon channels 502c, 504c, 506c and 508c, respectively, in regions 502r, 504r, 506r and 508r, respectively, above a lower end of the NAND strings are in physical and electrical contact with source line <NUM>. In this regard, the configuration of memory structure <NUM> depicted in <FIG> is sometimes referred to as a side source line contact configuration because source line <NUM> contacts peripheral exteriors of the vertical polysilicon channels of the NAND strings. As used herein, source line <NUM> is also referred to as side source line <NUM> to indicate that side source line <NUM> electrically contacts peripheral exteriors 502w, 504w, 506w and 508w of vertical polysilicon channels 502c, 504c, 506c and 508c respectively.

As described above, outer layers 502o, 504ο, 506o and 508o must be removed from regions 502r, 504r, 506r and 508r, respectively, of NAND strings <NUM>, <NUM>, <NUM> and <NUM>, respectively, leaving peripheral exteriors 502w, 504w, 506w and 508w of vertical polysilicon channels 502c, 504c, 506c and 508c, respectively, in contact with side source line <NUM>. Without the additional structural support provided by outer layers 502o, 504ο, 506o and 508ο, the structure of NAND strings <NUM>, <NUM>, <NUM> and <NUM> could be unstable during the processing steps used to fabricate memory structure <NUM>.

To avoid this potential instability, in an embodiment memory structure <NUM> includes one or more mechanical support elements disposed adjacent the array of NAND strings of memory structure <NUM>. In an embodiment, memory structure <NUM> includes a first set of mechanical support elements 516a0, 516a1,. , 516a5 disposed at a first region <NUM> of memory structure <NUM>, a second set of mechanical support elements 516b0, 516b1,. , 516b5 disposed at a second region 518r of memory structure <NUM>, and a third mechanical support element 516c disposed at a third region <NUM> of memory structure <NUM>. In an embodiment, third mechanical support structure 516c is a single element. In other embodiments, third mechanical support structure 516c may include multiple elements. More or fewer than three sets of mechanical support elements may be used.

In an embodiment, first region <NUM> may be a first peripheral region of the array of NAND strings of memory structure <NUM>, second region 518r may be a second peripheral region of the array of NAND strings of memory structure <NUM>, and third region <NUM> may be a central region of the array of NAND strings of memory structure <NUM>. Persons of ordinary skill in the art will understand that mechanical support elements may be disposed at more or fewer than three regions of the array of NAND strings of memory structure <NUM>.

In an embodiment, each of mechanical support elements 516a0 516a1,. , 516a5 and mechanical support elements 516b0, 516b1,. , 516b5 has a cylindrical shape. Persons of ordinary skill in the art will understand that mechanical support elements 516a0, 516a1,. , 516a5 and mechanical support elements 516b0, 516b1,. , 516b5 may have shapes other than cylindrical. In addition, although twelve mechanical support elements 516a0, 516a1,. , 516a5 and mechanical support elements 516b0, 516b1,. , 516b5 are shown in <FIG>, more or fewer than twelve mechanical support elements may be used.

In an embodiment, each of mechanical support elements 516a0, 516a1,. , 516a5, 516b0, 516b1,. , 516b5, and 516c is polysilicon surrounded by a dielectric layer <NUM>, such as Al<NUM>O<NUM>, which electrically isolates the mechanical support element material from side source line <NUM> and substrate <NUM>. Other materials may be used for mechanical support elements 516a0, 516a1,. , 516a5, 516b0, 516b1,. , 516b5, and 516c, and other dielectric materials may be used for dielectric layer <NUM>.

In an embodiment, mechanical support elements 516a0, 516al,. , 516a5, 516b0, 516b <NUM> ,. , 516b <NUM>, and 516c are disposed on substrate <NUM> and extend to a height substantially equal to a height of top surface of side source line <NUM>. In embodiments, each of mechanical support elements 516a0, 516al,. , 516a5, 516b0, 516b <NUM> ,. , 516b5, and 516c has a height h between about <NUM> angstroms and about <NUM> angstroms, although other heights may be used. In embodiments, each of mechanical support elements 516a0, 516al,. , 516a5, 516b0, and 516b <NUM> ,. , 516b5 has a width w1 between about <NUM> angstroms and about <NUM> angstroms, although other widths may be used. In embodiments, mechanical support element 516c has a width w2 between about <NUM> angstroms and about <NUM> angstroms, although other widths may be used.

In an embodiment, memory structure <NUM> also may include vertical slot conductors <NUM>, disposed on mechanical support elements 516a0, 516al,. , 516a5, 516b0, and 516b <NUM> ,. In an embodiment, vertical slot conductors <NUM> are tungsten, although other materials may be used. A dielectric liner <NUM>, such as AI2O3, isolates vertical slot conductors <NUM> from Other materials may be used for dielectric liner <NUM>. Vertical slot conductors <NUM> are electrically coupled to side source line <NUM>, and provide a low-resistance electrical contact to side source line <NUM>.

<FIG> depict a method according to the claimed invention of forming a three- dimensional stacked non-volatile memory structure, such as memory structure <NUM> of <FIG>. With reference to <FIG>, substrate <NUM> is shown as having already undergone several processing steps. Substrate <NUM> may be any suitable substrate such as a silicon, germanium, silicon-germanium, undoped, doped, bulk, silicon-on-insulator (SOI) or other substrate with or without additional circuitry. For example, substrate <NUM> may include one or more n-well or p-well regions (not shown). Isolation layer <NUM> is formed above substrate <NUM>. In some embodiments, isolation layer <NUM> may be a layer of silicon dioxide, silicon nitride, silicon oxynitride or any other suitable insulating layer.

Following formation of isolation layer <NUM>, a first dielectric layer <NUM> is formed over isolation layer <NUM>. First dielectric layer <NUM> may include any suitable dielectric material formed by any suitable method (e.g., CVD, PVD, etc.). In an embodiment, first dielectric layer <NUM> may comprise between about <NUM> angstroms and about <NUM> angstroms of AI2O3. Other dielectric materials and/or thicknesses may be used. In some embodiments, an adhesion layer (not shown), such as titanium nitride or other similar adhesion layer material, may be disposed between isolation layer <NUM> and first dielectric layer <NUM>.

Following formation of first dielectric layer <NUM>, a layer of sacrificial material layer <NUM> is formed over first dielectric layer <NUM>. Sacrificial material layer <NUM> may include any suitable sacrificial material layer formed by any suitable method (e.g., CVD, PVD, etc.). Sacrificial material layer <NUM> may be a semiconductor material, such as silicon, such as amorphous silicon or polysilicon, or another semiconductor material, such as a group IV semiconductor, including silicon-germanium and germanium. Preferably, sacrificial material layer <NUM> comprises intrinsic or undoped (if the as-deposited material inherently has a low p-type or n-type conductivity) semiconductor material, such as intrinsic or undoped polysilicon or amorphous silicon. However, p-type or n-type doped semiconductor materials, such as lightly or heavily doped materials may also be used if desired. In an embodiment, sacrificial material layer <NUM> may comprise between about <NUM> angstroms and about <NUM> angstroms of polysilicon. Other sacrificial material and/or thicknesses may be used.

Next, sacrificial material layer <NUM>, first dielectric layer <NUM> and isolation layer <NUM> are patterned and etched, resulting in the structure shown in <FIG>. For example, sacrificial material layer <NUM>, first dielectric layer <NUM> and isolation layer <NUM> are patterned and etched using conventional lithography techniques, with a soft or hard mask, and wet or dry etch processing. In an embodiment, sacrificial material layer <NUM>, first dielectric layer <NUM> and isolation layer <NUM> are patterned and etched to form trench <NUM> and cavities <NUM>. In an embodiment, cavities <NUM> have a cylindrical shape, although other shapes may be used. In an embodiment, trench <NUM> has a width wt of between about <NUM> angstroms and about <NUM> angstroms, and cavities <NUM> each have a diameter dc of between about <NUM> angstroms and about <NUM> angstroms, although other diameters may be used.

A second dielectric material layer <NUM> is conformally formed in trench <NUM> and cavities <NUM>. For example, between about <NUM> angstroms and about <NUM> angstroms of Al<NUM>O<NUM> may be deposited, resulting in the structure shown in <FIG>. Other dielectric materials such as silicon nitride, silicon oxynitride, high K dielectrics, etc., and/or other dielectric material layer thicknesses may be used.

A polysilicon layer <NUM> is formed over substrate <NUM> to fill trench <NUM> and cavities <NUM>. For example, between about <NUM> angstroms and about <NUM> angstroms of polysilicon may be deposited on the substrate <NUM>, resulting in the structure shown in <FIG>. Other materials such as silicon nitride, silicon oxynitride, and/or other dielectric materials and/or polymers with different thicknesses may be used.

Next, a chemical mechanical polishing or an etchback process is used to form a planar surface, and an etch stop layer <NUM> is formed over substrate <NUM>, resulting in the structure shown in <FIG>. Etch stop layer <NUM> may include any suitable etch stop layer formed by any suitable method (e.g., CVD, PVD, etc.). In an embodiment, etch stop layer <NUM> may comprise between about <NUM> angstroms and about <NUM> angstroms of Al<NUM>O<NUM>. Other etch stop layer materials and/or thicknesses may be used.

Alternating layers of third dielectric material layer <NUM> and fourth dielectric material layer <NUM> are formed over substrate <NUM>, resulting in the structure shown in <FIG> In an embodiment, third dielectric material layer <NUM> may be between about <NUM> angstroms and about <NUM> angstroms of SiO<NUM>, and fourth dielectric material layer <NUM> may be between about <NUM> angstroms and about <NUM> angstroms of Si<NUM>N<NUM>. Other dielectric materials and/or thicknesses may be used.

Memory holes <NUM> are formed that extend through alternating layers of third dielectric material layer <NUM> and fourth dielectric material layer <NUM>, etch stop layer <NUM>, sacrificial material layer <NUM>, first dielectric layer <NUM>, isolation layer <NUM> and substrate <NUM>, and material layers are formed on interior sidewalls and bottom surfaces of memory holes <NUM>. Memory holes <NUM> may have a diameter of between about <NUM> angstroms and about <NUM> angstroms, and a height of between about <NUM> angstroms and about <NUM> angstroms. Other diameters and heights may be used.

NAND strings are formed in each of memory holes <NUM>, with each NAND string including an outer layer <NUM>, which may include one or more layers (not shown), such as tunneling dielectric <NUM> and charge trapping layer <NUM> of <FIG>, a vertical polysilicon channel <NUM> disposed on outer layer <NUM>, and a dielectric core <NUM>, such as SiO<NUM> or other dielectric material, resulting in the structure shown in <FIG>. Outer layer <NUM> may have a thickness of between about <NUM> angstroms and about <NUM> angstroms, vertical polysilicon channel <NUM> may have a thickness of between about <NUM> angstroms and about <NUM> angstroms, and dielectric core <NUM> may have a diameter of between about <NUM> angstroms and about <NUM> angstroms, although other values may be used. In an embodiment, outer layer <NUM> has an oxide-nitride-oxide (ONO) structure, and may include an exterior charge trapping layer, such as a specially formulated silicon nitride that increases trap density.

Next, third dielectric material layers <NUM> and fourth dielectric material layers <NUM> are patterned and etched, resulting in the structure shown in <FIG>. For example, third dielectric material layers <NUM> and fourth dielectric material layers <NUM> are patterned and etched using conventional lithography techniques, with a soft or hard mask, and wet or dry etch processing. In an embodiment, third dielectric material layers <NUM> and fourth dielectric material layers <NUM> are patterned and etched to form slots <NUM>. In an embodiment, slots <NUM> terminate on etch stop layer <NUM>. In an embodiment, slots <NUM> has a width ws of between about <NUM> angstroms and about <NUM> angstroms, although other widths may be used.

Next, an etch is performed to remove fourth dielectric material layers <NUM> to form cavities <NUM>, which are lined with barrier and seeding material layers <NUM>, and conductive word line layers <NUM>, such as tungsten, are formed on barrier and seeding material layers <NUM>. Barrier and seeding material layers <NUM> and conductive word line layers <NUM> are etched back, resulting in the structure shown in <FIG>.

A fifth dielectric material layer <NUM>, an oxide material layer <NUM> and a sixth dielectric material layer <NUM> are conformally formed in slots <NUM>, resulting in the structure shown in <FIG>. For example, fifth dielectric material layer <NUM> may be between about <NUM> angstroms and about <NUM> angstroms of Al<NUM>O<NUM>, oxide material layer <NUM> may be between about <NUM> angstroms and about <NUM> angstroms of SiO<NUM>, and sixth dielectric material layer <NUM> may be between about <NUM> angstroms and about <NUM> angstroms of Al<NUM>O<NUM>. Other materials and/or other material layer thicknesses may be used.

A reactive ion etch process in performed to etch fifth dielectric material layer <NUM>, oxide material layer <NUM>, sixth dielectric material layer <NUM> and etch stop layer <NUM> in slots <NUM>, resulting in the structure shown in <FIG>. As a result of the etch, voids <NUM> are formed above sacrificial material layer <NUM>.

Next, sacrificial material layer <NUM> is removed via voids <NUM>, resulting in the structure shown in <FIG>. Regions <NUM> remain in the spaces formerly occupied by sacrificial material layer <NUM>.

Next, portions of outer layers <NUM> of the NAND strings formed in memory holes <NUM> are removed in regions <NUM>, leaving peripheral exteriors of vertical polysilicon channels <NUM> exposed. In the process or removing portions of outer layers <NUM>, oxide material layer <NUM> also is removed from slots <NUM>, resulting in the structure shown in <FIG>.

Finally, a conductive material, such as tungsten is deposited over substrate <NUM>, filling slots <NUM> to form vertical slot conductors <NUM> and filling regions <NUM> to form side source line <NUM>, resulting in the structure shown in <FIG>. As is visible in <FIG>, peripheral exteriors of vertical polysilicon channels <NUM> are in physical and electrical contact with side source line <NUM>. In addition, vertical slot conductors <NUM> are electrically coupled to side source line <NUM>, and provide a low-resistance electrical contact to side source line <NUM>.

According to one aspect the present invention provides a method of fabricating a monolithic three dimensional memory structure as claimed in claim <NUM>.

In one embodiment the method includes forming a plurality of NAND strings of memory cells in memory holes which extend through the source line and the alternating word line and dielectric layers, each memory cell including a control gate formed by one of the word line layers, and forming the mechanical support element on the substrate adjacent the plurality of NAND strings.

According to one embodiment the method results in a three-dimensional stacked non-volatile memory structure that includes a source line disposed above a substrate, a stack disposed above the substrate, the stack comprising alternating word line and dielectric layers, a plurality of NAND strings of memory cells formed in memory holes which extend through alternating word line and dielectric layers, each NAND string comprising a vertical channel having peripheral exterior above a bottom end of the NAND string in contact with the source line, and a mechanical support element disposed on the substrate adjacent the plurality of NAND strings.

For purposes of this document, it should be noted that the dimensions of the various features depicted in the figures may not necessarily be drawn to scale.

For purposes of this document, reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more others parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly or indirectly connected so that they can communicate electronic signals between them.

For purposes of this document, the term "based on" may be read as "based at least in part on.

For purposes of this document, without additional context, use of numerical terms such as a "first" object, a "second" object, and a "third" object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects.

For purposes of this document, the term "set" of objects may refer to a "set" of one or more of the objects.

Claim 1:
A method of fabricating a monolithic three dimensional memory structure, the method comprising:
forming a stack of alternating word line (<NUM>) and dielectric layers (<NUM>) above a substrate (<NUM>);
forming a source line (<NUM>) above the substrate (<NUM>) and under the stack of alternating word line (<NUM>) and dielectric layers (<NUM>);
forming a memory hole (<NUM>) extending through the alternating word line (<NUM>) and dielectric layers (<NUM>) and the source line (<NUM>); and
forming a mechanical support element (<NUM>) on the substrate adjacent (<NUM>) to the memory hole (<NUM>), the stack of alternating word line (<NUM>) and dielectric layers (<NUM>) being above the mechanical support element (<NUM>);
forming an outer layer (<NUM>) in the memory hole (<NUM>);
forming a vertical channel (<NUM>) on the outer layer (<NUM>) in the memory hole (<NUM>); and
characterised in that the method further comprises:
selectively removing a portion of the outer layer (<NUM>) to expose a peripheral exterior of the vertical channel (<NUM>); and
forming the source line (<NUM>) in contact with the exposed peripheral exterior of the vertical channel (<NUM>).