Patent Description:
Patent document <CIT> proposes a processor based control system including a receiving device which receives external data, which is passed to an intelligent multichannel DMA controller working in cooperation with a host processor to store received data in system memory. The receiving device interrupts the DMA controller signaling that there is no more data to move. The DMA controller then interrogates the receiving device to determine the disposition of a received data packet. Particularly, the DMA controller determines whether the received packet is a good packet, a null packet, or a packet containing an error. By this construction, the number of interrupts which must be handled by the host processor are greatly reduced.

Patent document <CIT> proposes a data transfer controller of IEEE1394 with first buses <NUM>, <NUM> and <NUM>, second buses <NUM> and <NUM>, third buses <NUM>-<NUM> and a forth bus <NUM> electrically connected to the application of a poststage, a CPU <NUM>, a PHY chip and a RAM <NUM>. A mediation circuit <NUM> performs mediation for establishing a data route between one of the first, second and third buses and the forth bus. DMACs <NUM>, <NUM>, <NUM> and <NUM> for transferring the data without the intervention of the CPU <NUM> and FIFOs <NUM>, <NUM> and <NUM> for phase adjustment are provided and the stage number of the FIFO is made equal to or less than three. The RAM is separated into a header area and a data area and the header area and the data area are separated into areas for reception and for transmission. By using TAG, the header of a reception packet is written in the header area and the data are written in the data area. The header is read from the header area, the data are read from the data area and a transmission packet is assembled.

Patent document <CIT> proposes a computing node operable to perform data operations between multiple computing nodes, the computing node comprising a processor, a data mapping engine (DME) configured to generate data transformation and mapping information for a defined data operation received from the processor and a direct memory access (DMA) controller configured to initiate the defined data operation between the multiple computing nodes. The defined data operation includes manipulating data stored in one or more source memory locations in accordance with the data transformation and mapping information, and providing manipulated data for storage in one or more target memory locations.

Patent document <CIT> proposes methods, apparatus, systems, and articles of manufacture to transmit and/or receive data streams with a network interface controller. An example apparatus includes a direct memory access engine to fetch a descriptor for a data transmission from system memory and determine a time to generate an interrupt based on the descriptor; a scheduler to trigger the interrupt when the time occurs, the interrupt to cause an application to sample data and store the sampled data as a payload data structure into the system memory; the direct memory access engine to access the payload data structure from the system memory; and the scheduler to cause transmission of the payload data structure.

<CIT> proposes a data processing apparatus including a processor and a direct memory access (DMA) controller coupled to the processor, the DMA controller including a control circuit that controls a DMA transfer of data, an error detection circuit that performs an error detection on the data based on a character assigned in association with the data to output a result of the error detection to the control circuit, and a diagnosis circuit that disconnects between the control circuit and the error detection circuit to diagnose an operation of the error detection circuit and provide a diagnosis result to the processor.

Patent document <CIT> proposes a computer program product, system, and method for determining when to throttle interrupts to limit interrupt processing to an interrupt processing time. Upon receiving interrupts from the hardware device, a determination is made as to whether a number of received interrupts exceeds an interrupt threshold during a interrupt tracking time period. If so, an interrupt throttling state is set to a first value indicating to only process interrupts during an interrupt processing time period. Interrupts from the hardware device are processed during the interrupt time period when the interrupt throttling state is set to the first value. Interrupts received from the hardware are masked during a processing of a scan loop of operations while the interrupt throttling has the first value and the interrupt processing time period has expired, wherein the masked interrupts are not processed while processing the scan loop of operations.

When a sensor transfers sensor data to a computing system such as a microcontroller unit (MCU), the computing system configures a DMA engine to move the entire sensor data from a receive buffer to an internal memory of the computing system. For further processing of the sensor data, the computing system needs to validate the sensor data and extract the payload from the sensor data. This may cause a high baseload on the computing system. Hence, there may be a demand for DMA with improved sensor data processing.

Preferred embodiments are as set out by the dependent claims.

When two elements A and B are combined using an "or", this is to be understood as disclosing all possible combinations, i.e., only A, only B as well as A and B, unless expressly defined otherwise in the individual case.

<FIG> illustrates a block diagram of an example of a DMA system <NUM>. DMA refers to a type of memory access used for computing systems, such as, MCUs, handheld devices, appliances, laptop computers, desktop computers, mainframes, distributed computer systems, datacenters, cloud server, or wearables. DMA may be characterized as direct insofar as it may allow data transfer independently of further processing circuitry, e.g., a superordinated processing circuitry with regard to the DMA system <NUM>. In other words: DMA may allow data transfers on behalf of the further processing circuitry. The DMA system <NUM> may transfer data, e.g., from a peripheral device to a main system memory of a computing system.

The DMA system <NUM> and the further processing circuitry may, e.g., be part of one and the same computing system (e.g., third-party DMA) or be integrated into separated computing systems transferring data with each other via DMA (e.g., bus mastering). The DMA system <NUM> may, e.g., be integrated into a semiconductor die peripheral to the further processing circuitry. The DMA system <NUM> may include software and hardware configured to generate memory addresses and perform memory read or write cycles. It may include hardware registers, such as an address register, a control register, a status register, and a byte count register.

The DMA system <NUM> comprises input interface circuitry <NUM> configured to receive a data packet <NUM> of a sensor from a source memory <NUM>. The sensor may be any device for sensing any physical, chemical, or biological quantity, e.g., an inductive, optical, or magnetic sensor. The sensor may convert acquired measurands into measurement data and request a data transfer to the source memory <NUM>. The source memory <NUM> may be a data buffer of an I/O interface (sensor interface) between a computing system comprising the DMA system <NUM> and the sensor.

The data packet <NUM> may be a portion of data generated by the sensor, e.g., based on data acquisition. The data packet <NUM> may refer to, e.g., a self-contained data unit with a well-defined length or a data stream with an initially unknown length. The data packet <NUM> may comprise payload and overhead (overhead bits). While payload may indicate the actual intended information, e.g., measurement data of the sensor, overhead may be additional data, e.g., useful for transmission or classification of the data packet <NUM>. The overhead may comprise metadata, a destination address, a source address, a header, a footer, error detection code, a protocol identifier, a packet length, status data, or alike. The data packet <NUM> may be a sequence of data frames arranged in a certain order, e.g., chronologically. The payload may be fragmented into said data frames which in turn are encapsulated into the data packet <NUM>. An example of a structure (format) of a data packet is explained with reference to <FIG>.

The data packet <NUM> and the data frame may refer to bundles of data in different abstraction layers of a communication protocol. On a physical layer of the communication protocol, the reception of the data packet <NUM> may correspond to a transmission of bits, bytes, or of any other units of digital information over a physical medium. For instance, the physical layer may perform the transmission of the digital information by converting it into signals, such as electrical, radio, or optical signals, and mediating them via the physical medium.

The input interface circuitry <NUM> may receive the data packet <NUM> using any software and hardware components, e.g., wire, optical fiber, etc. For instance, the input interface circuitry <NUM> may receive the data packet <NUM> via a DMA channel. When receiving the data packet <NUM>, the input interface circuitry <NUM> may read the data packet <NUM> from the source memory <NUM> and write it into a temporary data register internal to the DMA system <NUM>. The DMA system <NUM> may, e.g., be capable of performing dual-cycle data transfers (fetch-and-deposit transfers). The DMA system <NUM> may receive (and send) the data packet <NUM> based on any DMA transfer mode, e.g., single, block, or demand mode. The DMA system <NUM> may have a certain configuration which defines, e.g., the DMA transfer mode, a communication protocol used for the data transfer, or a network address of the source memory <NUM>.

The DMA system <NUM> further comprises processing circuitry <NUM> communicatively coupled to the input interface circuitry <NUM> and to an output interface circuitry <NUM>. The processing circuitry <NUM> is configured to determine whether the data packet <NUM> comprises a synchronized data frame.

The processing circuitry <NUM> may be any electronic circuit for processing the data packet <NUM>. The processing circuitry <NUM> is to be distinguished from a further processing circuitry, e.g., a central processing circuitry (CPU) of the computing system (e.g. an MCU), for which the DMA system <NUM> performs a memory transfer of the data packet <NUM>.

The processing circuitry <NUM> determines whether the data packet <NUM> comprises a synchronized data frame based on any synchronization method (or synchronization scheme), e.g., time gap synchronization, start and end flag synchronization, or packet length indication. The synchronization method may allow the processing circuitry <NUM> to detect a frame border of a data frame in the data packet <NUM>. The synchronization method may be defined by a communication protocol jointly used by the receiving input interface circuitry <NUM> and a sender of the data packet <NUM> (e.g., an I/O interface to the sensor). In some examples, the processing circuitry <NUM> is configured to detect synchronization data in the data packet <NUM> and determine whether the data packet <NUM> comprises a synchronized data frame based on the synchronization data. The synchronization data (synchronization signal, frame alignment signal) may be, e.g., a distinctive bit, byte or sync word in an overhead of the data packet <NUM>. The synchronization data may indicate a beginning and/or end of a data frame in the data packet <NUM>. For instance, if the processing circuitry <NUM> detects synchronization data indicating a beginning of a data frame (e.g., start flag), then, the following data elements of the data packet <NUM> may be deemed as a synchronized data frame. The number of the following data elements counted as the synchronized data frame may be defined by the communication protocol, information given by a header of the synchronized data frame or correspond to all data elements between detected frame borders. The processing circuitry <NUM> may store a header of the synchronized data frame in a status register of the DMA system or at a defined memory address of a destination memory.

The processing circuitry <NUM> is further configured to, if it is determined that the data packet comprises a synchronized data frame, extract a payload <NUM> of the synchronized data frame. The DMA system <NUM> further comprises output interface circuitry <NUM> configured to send the payload <NUM> or data derived from the payload <NUM> to a destination memory <NUM>. The destination memory <NUM> may be any data storage device for retaining data. The destination memory <NUM> may be internal memory (main memory) of a further processing circuitry for which the DMA system <NUM> operates data transfers. The destination memory <NUM> may in alternative examples be external to the DMA system <NUM>.

The payload <NUM> may comprise raw data recorded by the sensor or preprocessed data from the sensor. Depending on the communication protocol used, the processing circuitry <NUM> may extract the payload <NUM> of the synchronized data frame based on a frame length of the synchronized data frame. The frame length may be, e.g., predefined or determined by the processing circuitry <NUM> based on at least one of the synchronization data (e.g., indicating a start and end flag of a data frame) and a header of the synchronized data (e.g., the header may comprise frame information data indicating the frame length).

The payload <NUM> may be considered aligned sensor data since the processing circuitry <NUM> checks for synchronization before extracting the payload <NUM>. The DMA system <NUM> may, therefore, offload a processor (a further processing circuitry) external to the DMA system <NUM> from initial validation and pre-processing of sensor data.

Extraction of the payload <NUM> may refer to a retrieval, import, or collection of the payload <NUM> by intermediately storing it in the DMA system <NUM>, e.g., for further data processing or migration. For instance, the DMA system <NUM> may store the payload <NUM> in an internal data buffer temporarily. The extraction of the payload <NUM> may, in some examples, include imposing a data structure on the payload <NUM> (which may initially be unstructured or poorly structured), (re-)formatting the payload <NUM> or performing data transformation of the payload <NUM>. In some examples, the processing circuitry <NUM> is configured to change a data structure of the payload <NUM>, e.g., reorder or rearrange individual data elements of the payload <NUM>. The output interface circuitry <NUM> may be configured to send the payload <NUM> with the changed data structure to the destination memory <NUM>. For example, the processing circuitry <NUM> may change the data structure of the payload <NUM> by assigning a respective destination address to data elements (e.g., bits or bytes) of the payload <NUM>, i.e., indexing the data elements, based on a certain assignment pattern. The assignment pattern may correspond to predefined requirements matching an application of the DMA system <NUM>.

For instance, the processing circuitry <NUM> may be configured to change the data structure of the payload <NUM> based on a matrix transposition (a detailed example is described below with reference to <FIG>) or a bit-reversal permutation (a detailed example is described below with reference to <FIG>). For a matrix transposition, the processing circuitry <NUM> may transpose data elements of the payload <NUM> representing a matrix, yielding a diagonally flipped representation of the matrix. For a bit-reversal permutation, the processing circuitry <NUM> may reverse an original indexing of the data elements of the payload <NUM>. In some examples, the processing circuitry <NUM> may be configured to change the data structure of the payload <NUM> into a circular buffer structure (a detailed example is described below with reference to <FIG>). The processing circuitry <NUM> may increment an index of data elements of the payload <NUM> such that - after a fixed number of data elements - the "oldest" data element is overwritten and is used as new starting point for incrementation of the index, i.e., an end-to-end connected, fixed-size buffer is emulated.

The processing circuitry <NUM> is further configured to determine whether the data packet <NUM> comprises invalid data and, if it is determined that the data packet <NUM> comprises invalid data, discard the invalid data. In other words: The DMA system <NUM> may disregard, delete or overwrite the invalid data stored in its internal memory and may solely send the payload <NUM>, data derived thereof, or other data deemed as valid to the destination memory <NUM>. The DMA system <NUM> thus, comprises logic for deciding whether the data packet <NUM> comprises invalid data and determining which parts of the data packet <NUM> are invalid data. The processing circuitry <NUM> may rate overhead or misaligned data of the data packet <NUM> as invalid. For instance, the processing circuitry <NUM> is configured to determine whether the data packet <NUM> comprises invalid data by determining whether the data packet <NUM> comprises data between the synchronized data frame and a second synchronized data frame. The second synchronized data frame may be a data frame of the data packet <NUM> following the synchronized data frame. If it is determined that the data packet <NUM> comprises data between the synchronized data frame and the second synchronized data frame, the processing circuitry <NUM> discards the data between the synchronized data frame and the second synchronized data, i.e., rate the said data, e.g., including overhead or a misaligned data frame, as invalid.

The processing circuitry <NUM> is configured to determine whether the data packet <NUM> comprises invalid data by determining whether the data packet <NUM> comprises data preceding the synchronized data frame and, if it is determined that the data packet <NUM> comprises data preceding the synchronized data frame, discard the data preceding the synchronized data frame. In case, the data packet <NUM> comprises several synchronized data frames, the synchronized data frame may be first with respect to an order of the data packet <NUM>. In other words: Parts of the data packet <NUM> which are between a start of the data packet <NUM> and a first synchronized data frame, i.e., data from start of the data packet <NUM> until first synchronized data frame is detected, may be rejected.

Depending on the structure of the data packet <NUM>, the data packet <NUM> may include further relevant information in its overhead such as status data indicating a status of the sensor, sensor configuration data indicating a configuration of the sensor, DMA configuration data indicating a desired configuration of the DMA system <NUM>, or information data indicating an action to be triggered. This relevant information may be processed by the DMA system <NUM> for offloading a further processing circuitry external to the DMA system <NUM>. In some examples, the data packet <NUM> may include at least one flag for triggering an action of the DMA system <NUM> or the further processing circuitry. For instance, if the sensor is a radar sensor for object detection, the data packet <NUM> may include a detection bit, e.g., in its header, wherein the detection bit may be set during preprocessing by the sensor if an object is detected. The DMA system <NUM> may extract the flag and execute the associated action or transfer the flag to the further processing circuitry.

For example, the data packet <NUM> may comprise sensor configuration data in a header of the synchronized data frame. The processing circuitry <NUM> may be further configured to extract the sensor configuration data from the header of the synchronized data frame. The output interface circuitry <NUM> may be configured to send the sensor configuration data to the destination memory <NUM>. The output interface circuitry <NUM> may write the sensor configuration data into a defined memory area of the destination memory <NUM>.

In some examples, the data packet <NUM> may comprise DMA configuration data indicating a desired configuration of the DMA system <NUM>. The processing circuitry <NUM> may be configured to configure the DMA system <NUM> based on the DMA configuration data. For instance, the processing circuitry <NUM> may change a transfer mode or priority of the DMA system <NUM> as indicated in the DMA configuration data. If the data packet <NUM> comprises information data in a header of the synchronized data frame, the processing circuitry <NUM> may be configured to detect the information data and process the information data, e.g., to trigger an action of the DMA system <NUM>.

If the data packet <NUM> comprises status data indicating a status of the sensor, the processing circuitry <NUM> may be configured to determine whether the data packet <NUM> comprises invalid data by determining whether the data packet <NUM> comprises data between the status data and the synchronized data frame. If it is determined that the data packet <NUM> comprises data between the status data and the synchronized data frame, the processing circuitry <NUM> may be configured to discard the data between the status data and the synchronized data frame. Alternatively or additionally, the processing circuitry <NUM> may be configured to determine whether the data packet <NUM> comprises invalid data by determining whether the status data indicate an error of the sensor. If it is determined that the status data indicates an error of the sensor, the processing circuitry <NUM> may be configured to discard data of the data packet <NUM> following (e.g., directly subsequent to) the status data. The status data may additionally be stored in a status register of the DMA system <NUM> in parallel.

In cases that the processing circuitry <NUM> is configured to determine whether the status data indicate an error of the sensor, the output interface circuitry <NUM> may be further configured to, if it is determined that the status data indicates an error of the sensor, send an interrupt command to the further processing circuitry external to the DMA system <NUM>. An interrupt command may be a request for the further processing circuitry to interrupt currently executing code for processing the error of the sensor in a timely manner. If the request is accepted, the further processing circuitry may suspend its current activities and execute an interrupt handler or interrupt service routine to deal with the error of the sensor. Alternatively or additionally, the processing circuitry <NUM> may be configured to process the error of the sensor, e.g., by stopping the current data transfer (DMA transaction), reconfiguring the DMA system <NUM> and/or starting a new data transfer.

In summary, data of the data packet <NUM> may be counted as invalid and may be dropped by the DMA system <NUM> in the following cases:.

The DMA system <NUM> may be considered a "magnified DMA system" which may perform common DMA tasks, such as transfer of sensor data from a source memory <NUM> to a destination memory <NUM>, and, e.g., in parallel, may synchronize data frames of the sensor data, discard misaligned data (invalid data), extract payload <NUM> from aligned data (synchronized data frame), and/or reorganize a data structure of the payload <NUM> without an involvement of an associated processor external to the DMA system <NUM> (further processing circuitry). Unlike a conventional DMA system which basically moves a received data packet to the destination memory without further processing of the data packer, DMA system <NUM> may additionally offload the processor by taking on further tasks such as sensor status detection, frame synchronization and data discard, e.g., in case of an error. These further tasks may conventionally be executed by the processor in a software routine causing a baseload on the processor. Thus, the DMA system <NUM> may eliminate this baseload by deploying enhanced and specialized DMA functions.

The DMA system <NUM> may increase a maximum data transfer speed in a computing system combining the DMA system <NUM> and a processor, thus, the DMA system <NUM> may be useful for highspeed data acquisition. The DMA system <NUM> may decrease latency in servicing a data acquisition device since the dedicated hardware of the DMA system <NUM> responds more quickly compared to an interrupt, and a time interval for transferring the data is shorter. Besides, the DMA system <NUM> may reduce an amount of temporary storage (source memory) required for an I/O device.

<FIG> illustrates a block diagram of another example of a DMA system <NUM>. The DMA system <NUM> comprises input interface circuitry <NUM> (source transfer engine) configured to receive a data packet of a sensor from a source memory. The DMA system <NUM> may be integrated into a computing system and perform data transfers on behalf of an MCU of the computing system. The input interface circuitry <NUM> may receive the data packet via a serial communication bus from a serial peripheral interface (SPI) to the sensor.

The DMA system <NUM> further comprises a source address generator <NUM>. The source address generator <NUM> is a software tool for determining a source address of the source memory from which the source transfer engine <NUM> may fetch the data packet. The source address may be a reference to a specific memory location in the source memory.

The DMA system <NUM> further comprises processing circuitry <NUM> (data peeling logic) configured to determine whether the data packet comprises a synchronized data frame. The processing circuitry <NUM> is further configured to, if it is determined that the data packet comprises a synchronized data frame, extract a payload of the synchronized data frame. In other words: The processing circuitry <NUM> may execute data peeling on the fetched data packet and extract meaningful sensor data (payload). For instance, the processing circuitry <NUM> may detect a command phase, data phase, and synchronization data of the data packet and pull out valid sensor data. The processing circuitry <NUM> may check a sensor status of the sensor based on the command phase. If an error is detected in the sensor status, the processing circuitry <NUM> may issue an interrupt command to the MCU.

The processing circuitry <NUM> may process the fetched data packet framewise. In each frame, the processing circuitry <NUM> may determine whether synchronization data (e.g., a start flag) is present. If it is determined that synchronization data is present, the processing circuitry <NUM> may deem following data, e.g., within a predefined frame length, as valid. The processing circuitry <NUM> may store the payload of the valid data in an internal data buffer <NUM> temporarily. The processing circuitry <NUM> may further process the payload, yielding data derived from the payload.

The DMA system <NUM> further comprises output interface circuitry <NUM> (destination transfer engine) configured to send the payload or data derived from the payload to a destination memory.

The DMA system <NUM> may combine common DMA tasks with a synchronization of data frames of the sensor data, a discard of misaligned data, and extraction of payload from aligned data, and/or a reorganization of a data structure of the payload without an involvement of an associated processor external to the DMA system <NUM> (further processing circuitry). The DMA system <NUM> may increase a maximum data transfer speed in a computing system combining the DMA system <NUM> and the processor, thus, the DMA system <NUM> may be useful for highspeed data acquisition. The DMA system <NUM> may decrease latency in servicing a data acquisition device since the dedicated hardware of the DMA system <NUM> responds more quickly compared to an interrupt, and a time interval for transferring the data is shorter. Besides, the DMA system <NUM> may reduce an amount of temporary storage (source memory) required for an I/O device.

<FIG> illustrates a block diagram of an example of a processing circuitry <NUM> of a DMA system according to examples described herein, such as DMA system <NUM> or <NUM>. The processing circuitry <NUM> is configured to determine whether a data packet received by the DMA system comprises a synchronized data frame. The processing circuitry <NUM> is further configured to, if it is determined that the data packet comprises a synchronized data frame, extract a payload of the synchronized data frame.

The processing circuitry <NUM> comprises hardware and/or software to execute a first function <NUM> (command phase detection). The first function <NUM> may allow the processing circuitry <NUM> to distinguish between a command phase and a data phase of the data packet. The command phase may comprise status data indicating a status of a sensor (from which the data packet originated). The processing circuitry <NUM> further comprises hardware and/or software to execute a second function <NUM> (frame synchronization detection). The second function <NUM> may allow the processing circuitry <NUM> to detect synchronization data used for framing of the data packet, i.e., for determining whether the data packet comprises a synchronized data frame. The processing circuitry <NUM> comprises hardware and/or software to execute a third function <NUM> (payload extraction). The third function <NUM> may allow the processing circuitry <NUM> to extract the payload of a synchronized data frame.

The processing circuitry <NUM> comprises three output channels <NUM>, <NUM>, and <NUM>. The processing circuitry <NUM> may output the status of the sensor via the first channel <NUM>. The processing circuitry <NUM> may output the data packet via the second channel <NUM> and output an indication of validity of the data packet via the third channel <NUM>.

<FIG> illustrates a structure of an example of a data packet <NUM>. For instance, a sensor may generate sensor data and transfer it to a computing system via an I/O interface, e.g., SPI, for further processing. The raw or initially processed sensor data is encapsulated into the data packet <NUM>. The computing system may fetch the data packet <NUM> via a DMA system according to examples described herein, such as DMA system <NUM> or <NUM>. The DMA system may receive the data packet <NUM> from a source memory (at the I/O interface).

The data packet <NUM> may deploy a vendor-defined protocol defining the structure of the data packet <NUM>. The data packet <NUM> comprises, at its start, a command phase <NUM> comprising status data <NUM> of the sensor. The data packet <NUM> further comprises, subsequent to the command phase <NUM>, a data phase <NUM> which is divided into N data frames, such as data frame <NUM>-<NUM> and <NUM>-N. Each data frame comprises, at its start, a header <NUM> and, subsequent to the header, payload <NUM> (sensor data). The header <NUM> comprises synchronization data <NUM> (synchronization signals) and information data <NUM> (frame information). The header <NUM> may further comprise sensor configuration data, DMA configuration data, or alike.

The DMA system determines whether the data frame <NUM>-<NUM> is a synchronized data frame based on the synchronization data <NUM>, for instance. If the data frame <NUM>-<NUM> is deemed as synchronized data frame, the DMA system extracts the payload <NUM> from the data frame <NUM>-<NUM>. The DMA system then, sends the payload <NUM> or data derived from the payload <NUM> to a destination memory, e.g., for further processing such as FFT (Fast Fourier Transformation), CFAR (Constant False Alarm Rate) detection, or neural network detection/classification (in case the sensor is a radar sensor).

<FIG> illustrate examples of data <NUM> derived from payload <NUM>. For instance, a DMA system according to examples described herein, such as DMA system <NUM> or <NUM>, is configured to extract the payload <NUM> from a data packet of a sensor. Depending on the application, the DMA system may restructure the payload <NUM>, yielding the data <NUM> derived from the payload <NUM>, to match requirements of further processing circuitry receiving the data <NUM> derived from the payload <NUM>. Therefore, the DMA system may be configured to change the data structure of the payload <NUM>, e.g., based on a matrix transposition (<FIG>), a bit-reversal permutation (<FIG>), or change the data structure of the payload <NUM> into a circular buffer structure (<FIG>). The DMA system may change the data structure of the payload <NUM>, e.g., using a chained descriptor.

In <FIG>, the payload <NUM> in its initial data structure represents a matrix. The further processing circuitry may require the payload <NUM> to be reordered based on a matrix transposition, resulting in a transposed matrix. For example, if the payload <NUM> in its initial data structure is formatted as [chirps][tx][samples][rx], the DMA system may reorder the data elements of the payload <NUM> to obtain the format of [rx][chirps][tx][samples]. The DMA system may calculate a destination address according to the required matrix transposition and transfer the restructured data <NUM> (data derived from the payload) to a destination memory.

In <FIG>, data elements of the payload <NUM> - in its initial data structure - are ordered according to a source address of each of the data elements, i.e., the payload <NUM> is a sequence of the data elements ordered by their respective source address. The further processing circuitry may require the payload <NUM> to be prepared for subsequent FFT algorithms. For example, a radar sensor may execute range FFT on data generated by its antenna. The resulting FFT data, i.e., the payload <NUM>, may be used by the further processing circuitry for Doppler FFT processing. So, it may be useful to reshuffle the payload <NUM> before buffer fly-computation. Therefore, the DMA system may calculate a respective destination address for each of the data elements based on bit-reversal permutation.

In some examples, the DMA system may be configured to change the data structure of the payload <NUM> by cascading a matrix transposition and a bit-reversal permutation.

In <FIG>, the DMA system changes the (initial) data structure of the payload <NUM> (not shown in <FIG>) into a circular buffer structure. The DMA system may assign a respective destination address to each of the data elements of the payload <NUM> such that the data <NUM> derived from the payload <NUM> emulates an end-to-end connected, fixed-size buffer. This may especially advantageous if the payload <NUM> comprises audio data, e.g., from a silicon microphone, which initially exhibits a linear data structure. The audio data may be required to be sliced into short frames with overlapping parts between the frames. Therefore, the DMA system may prepare the audio data for slicing by sequentially writing data elements of the payload <NUM> into the destination memory from the start of the emulated circular buffer and wrap back to the start address when a predefined boundary of the circular buffer is reached. This may facilitate fetching the frames from the destination memory for the further processing circuitry.

<FIG> illustrates an example of a system <NUM> for processing sensor data. The system <NUM> may be, e.g., a computing system. The system <NUM> comprises a DMA system <NUM> according to examples described herein, such as DMA system <NUM> or <NUM>. The system <NUM> further comprises the source memory <NUM> from which the DMA system <NUM> may receive a data packet of a sensor. The source memory <NUM> may be an SPI receive buffer. In some examples, the system <NUM> comprises a sensor interface configured to receive the data packet from the sensor via a synchronous serial communication bus. The source memory <NUM> may be coupled to the sensor interface and configured to receive the data packet from the sensor interface.

The system <NUM> further comprises further processing circuitry <NUM> external to the DMA system <NUM>. Processing circuitry of the DMA system <NUM> is configured to extract the payload from the data packet without involvement of the further processing circuitry <NUM>. The further processing circuitry <NUM> may control an engine of the DMA system <NUM>.

The system <NUM> further comprises the destination memory <NUM> to which the DMA system <NUM> sends a payload or data derived from the payload. The destination memory <NUM> may be an internal memory of the computing system. The further processing circuitry <NUM> is coupled to the destination memory <NUM>, i.e., the further processing circuitry <NUM> may have access to the payload or the data derived from the payload. The further processing circuitry <NUM> is configured to read the payload or the data derived from the payload from the destination memory <NUM>.

The further processing circuitry <NUM> is further configured to process the payload or the data derived from the payload, e.g., in order to perform a specific function matching an application of the system <NUM> such as gesture recognition or presence detection. In some examples, the payload comprises radar data, and the further processing circuitry <NUM> is configured to perform radar processing on the payload or the data derived from the payload. In cases, the DMA system <NUM> stores additional data such as information data, sensor configuration data, or DMA configuration data of the data packet in the destination memory <NUM>, the further processing circuitry <NUM> may fetch the additional data and process it. For instance, the further processing circuitry <NUM> may retrieve a desired DMA configuration from the DMA configuration data. Then, the further processing circuitry <NUM> may configure the DMA system <NUM> according to the desired DMA configuration.

The DMA system <NUM> may, in some examples, process status data of the data packet and, if the status data indicates an error of the sensor, send an interrupt command to the further processing circuitry <NUM>. The further processing circuitry <NUM> may prioritize processing the interrupt command over other processing activities of the further processing circuitry <NUM>. The further processing circuitry <NUM> may process the interrupt command by, e.g., stopping a data transfer of the DMA system <NUM>, resuming the data transfer, reconfiguring the DMA system <NUM>, starting an error handling of the sensor, or alike.

In some examples, the data packet may comprise status data indicating a status of the sensor. The processing circuitry of the DMA system <NUM> may be configured to determine whether the status data indicate an error of the sensor. The output interface circuitry of the DMA system <NUM> may be configured to, if it is determined that the status data indicates an error of the sensor, send an interrupt command to the further processing circuitry <NUM>. The further processing circuitry <NUM> may be configured to process the interrupt command, e.g., by stopping current processing of the further processing circuitry <NUM>, saving a current state of the further processing circuitry <NUM>, executing an interrupt handler, executing an interrupt service routine to solve an error of the sensor, stopping a current data transfer of the DMA system <NUM>, reconfiguring the DMA system <NUM> and/or starting a new data transfer of the DMA system <NUM>.

The system <NUM> may combine common DMA tasks of the DMA system <NUM> with a synchronization of data frames of the sensor data, a discard of misaligned data, and extraction of payload from aligned data, and/or a reorganization of a data structure of the payload without an involvement of the further processing circuitry <NUM>. The system <NUM> may increase a maximum data transfer speed in a computing system combining the DMA system <NUM> and the further processing circuitry <NUM>, thus, the system <NUM> may be useful for highspeed data acquisition. The system <NUM> may decrease latency in servicing a data acquisition device since the dedicated hardware of the DMA system <NUM> responds more quickly compared to an interrupt, and a time interval for transferring the data is shorter. Besides, the system <NUM> may reduce an amount of source memory <NUM> required for an I/O device.

<FIG> illustrates a flowchart of an example of a method <NUM> for DMA. The method <NUM> comprises receiving <NUM> a data packet of a sensor from a source memory. The method <NUM> further comprises determining <NUM> whether the data packet comprises a synchronized data frame and, if it is determined that the data packet comprises a synchronized data frame, extracting <NUM> a payload of the synchronized data frame. The method <NUM> further comprises sending <NUM> the payload or data derived from the payload to a destination memory.

More details and aspects of the method <NUM> are explained in connection with the proposed technique or one or more examples described above, e.g., with reference to <FIG> and <FIG>.

The method <NUM> may comprise one or more additional optional features corresponding to one or more aspects of the proposed technique, or one or more examples described above.

Methods, such as method <NUM>, and apparatuses, such as DMA system <NUM> or system <NUM>, disclosed herein may increase a maximum data transfer speed for sensor data processing. The methods and apparatuses may decrease latency in servicing a data acquisition device and reduce an amount of temporary storage required for a sensor interface.

Claim 1:
A direct memory access, DMA, system (<NUM>), comprising:
input interface circuitry (<NUM>) configured to receive a data packet (<NUM>) of a sensor from a source memory (<NUM>);
processing circuitry (<NUM>) configured to:
determine whether the data packet (<NUM>) comprises a synchronized data frame based on a synchronization scheme;
if it is determined that the data packet (<NUM>) comprises a synchronized data frame, extract a payload (<NUM>) of the synchronized data frame;
determine whether the data packet (<NUM>) comprises invalid data by determining whether the data packet (<NUM>) comprises data between the synchronized data frame and a second synchronized data frame following the synchronized data frame or by determining whether the data packet (<NUM>) comprises data between a start of the data packet and the synchronized data frame; and
if it is determined that the data packet (<NUM>) comprises invalid data, discard the invalid data; and
output interface circuitry (<NUM>) configured to solely send the payload (<NUM>) or data derived from the payload (<NUM>) to a destination memory (<NUM>).