Patent Description:
Dies may be stacked in a three-dimensional arrangement as part of various microelectronic packaging schemes. This can include stacking a layer of one or more dies on a larger base die, stacking multiple dies in a vertical arrangement, and various combinations of both. Dies may also be stacked on wafers or wafers may be stacked on other wafers prior to singulation. The dies or wafers may be bonded in a stacked arrangement using various bonding techniques, including using direct dielectric bonding, non-adhesive techniques, such as a ZiBond® direct bonding technique or a DBI® hybrid bonding technique, both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc. ), a subsidiary of Xperi Corp (see for example, <CIT>, <CIT> and <CIT>).

When bonding stacked dies using a direct bonding technique, it is desirable that the surfaces of the dies to be bonded be extremely flat and smooth. For instance, the surfaces should have a very low variance in surface topology, such that the surfaces can be closely mated to form a lasting bond. It is also desirable that the surfaces be clean and free from impurities, particles, and/or other residue. The presence of undesirable particles for instance, can cause the bond to be defective or unreliable at the location of the particles. For instance, some particles and residues remaining on bonding surfaces can result in voids at the bonding interfaces between the stacked dies. If the voids are substantially smaller than the metallic electrical interconnect size, they may be acceptable. However, particles that cause bonding defects in sizes that are close to or exceed the electrical interconnect size often cannot be tolerated, since they can negatively impact the electrical conductivity of the interconnect.

Since semiconductor wafers (e.g., silicon wafers, for example) are brittle, it is common for defects or particles to be created at the edges of dies as they are singulated. As an example, silicon can crack during cutting, forming loose particles. Mechanical cutting or sawing often leaves a rough edge and can also leave particles or shards of silicon on or near the edges of cut dies. In addition, mechanical saw dicing typically transfers materials from the dicing sheet to the side wall and edge of the singulated dies. Laser cutting can also leave particles on the surface or edge of the dies. Various processes can be used to clean the surfaces of the dies after cutting. However, the processes can often leave some particles at the periphery of the die or at an edge wall of the die. Even when die surfaces are polished, shards may still be present on the edges or sidewalls of the dies. The loose particles and shards left behind can be problematic to forming reliable bonds. Additionally, these loose or partially loose particles may re-contaminate the bonding surfaces of interest or the bonding tool, etc. in subsequent operations.

An example of a method for forming a microelectronic system is disclosed in <CIT>, whereby semiconductor dies are singulated from a semiconductor wafer by placing the semiconductor wafer onto a carrier tape, forming singulation lines through the semiconductor wafer, and reducing the presence of residual contaminates on the semiconductor wafer.

According to the present invention, there is provided a method for forming a microelectronic system according to claim <NUM>.

For this discussion, the devices and systems illustrated in the figures are shown as having a multiplicity of components.

Various embodiments and techniques can be used to process singulated semiconductor die components in preparation for bonding. The embodiments comprise techniques to remedy the accumulation of defects found on dies, and includes removing, dissolving or etching particles at the edges of dies to provide a smooth bonding surface. The dies comprise a semiconductor.

A method for forming a microelectronic system includes singulating a plurality of semiconductor die components from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material are removed from edges of the plurality of semiconductor die components. Additionally, one or more of the plurality of semiconductor die components are bonded to a prepared bonding surface, via the substantially planar surface.

The particles and shards of material are removed by etching the edges of the plurality of semiconductor die components. The edges of the plurality of semiconductor die components may be etched while the plurality of semiconductor die components are on a dicing carrier (such as a dicing sheet, dicing tape, etc.). Additionally, the edges of the plurality of semiconductor die components may be etched using a chemical etchant. In an implementation, the chemical etchant can comprise hydrofluoric acid and nitric acid with Benzotriazole (BTA) or other chemicals that inhibit Cu dissolution in the etchant. Further, the edges of the plurality of semiconductor die components may be etched using a plasma etch. The edges of the plurality of semiconductor die components are etched to reduce a thickness of the plurality of semiconductor die components such that a space is created at one or more of the edges of each of the plurality of semiconductor die components. The semiconductor die components may include an oxide layer as the substantially planar surface, and the etching may include removing at least a portion of the oxide layer at the edges of the plurality of semiconductor die components. Still yet, the substantially planar surface of the plurality of semiconductor die components may be etched. The substantially planar surface may be etched to a preselected depth or for a preselected duration.

A protective coating may be applied to the substantially planar surface of the plurality of semiconductor die components prior to etching to protect the substantially planar surface from the etchant.

The plurality of semiconductor die components may be heated after singulating to cause the protective coating to recede from a periphery of the plurality of semiconductor die components. Additionally, the periphery of the plurality of semiconductor die components may be etched to a preselected depth. Further, the plurality of semiconductor die components may include a dielectric layer over a base semiconductor layer. Additionally, the periphery of the plurality of semiconductor die components may be etched to remove the dielectric layer and expose the base semiconductor layer at the periphery of the plurality of semiconductor die components.

The one or more of the plurality of semiconductor die components may be bonded by either a direct bonding technique without adhesive or a metal to metal diffusion bond.

Particles and shards of material may be removed from a sidewall of the plurality of semiconductor die components, wherein the particles and shards are removed from the sidewall by etching the sidewall of the plurality of semiconductor die components.

In one embodiment, after a singulation step, particles and shards of material may be removed from a sidewall of a die by means of ultrasonic or megasonic radiation in one or more an alkaline fluids. Following the particle removal, the sidewall of the die may be further etched to remove portions of the sidewall and portions of a planar dielectric layer of the die.

Some of the disclosed processes may be illustrated using block flow diagrams, including graphical flow diagrams and/or textual flow diagrams. Furthermore, the disclosed processes can be implemented in any suitable manufacturing or processing apparatus or system, along with any hardware, software, firmware, or a combination thereof, without departing from the scope of the subject matter described herein.

Implementations are explained in more detail below using a plurality of examples. Although various implementations and examples are discussed here and below.

<FIG> is a profile view showing defects on a top surface of a die. As shown, a first die <NUM> is shown without any defects. In contrast, a second die <NUM> is shown with defects <NUM>. Of course, it is to be appreciated that defects <NUM> may occur on any surface, sidewall, and/or edge of the first die <NUM> and/or second die <NUM>.

The first die <NUM> and/or the second die <NUM> may be singulated from and/or removed from wafers, such as GaAs, diamond coated substrates, silicon carbide, silicon oxide, Silicon Nitride, silicon wafers, Lithium Niobate, Lithium Tantalate, flat panels, glasses, ceramics, circuit boards, packages, an interposer, structures with or without an embedded metallic layer, conductive interconnects <NUM>, device or devices, etc. Defects <NUM> may include particles and/or shards and may result from die cutting, dicing, and/or singulating the first die <NUM> and/or the second die <NUM>. For example, mechanical cutting (i.e. sawing) of the first die <NUM> and/or the second die <NUM> may cause defects such as particles <NUM>, particularly at the edges and/or sidewalls. Additionally, when the first die <NUM> and/or the second die <NUM> is cut (even using a laser), the first die <NUM> and/or the second die <NUM> may crack and/or generate particles <NUM> (such as silicon oxide particles). Further, after polishing the first die <NUM> and/or the second die <NUM>, shards of particles <NUM> may still be present on the edges and/or sidewalls of the first die <NUM> and/or the second die <NUM>.

<FIG> is a profile view showing a section of bonded dies with defects such as particles <NUM>. As shown, with defects <NUM> present at a portion of the bonding surface of the second die <NUM>, the first die <NUM> cannot be fully bonded to the second die <NUM>. This is shown by the gap <NUM> (or void) found between the first die <NUM> and the second die <NUM>. This gap <NUM> may be intolerable if the integrity of the bond is compromised, or if the gap <NUM> is large enough to negatively impact the electrical conductivity of mating electrical interconnects <NUM> if present at the bonding surfaces of the dies <NUM> and <NUM>. As discussed above, although the defects <NUM> may be found on the bonding surface of the second die <NUM>, additional or other defects (such as particles) may be found along another surface and/or sidewall of the first die <NUM> and/or the second die <NUM>.

<FIG> is a profile view showing a section of intimately bonded dies without defects. As shown, the first die <NUM> is fully and completely bonded to the second die <NUM>. Any conductive interconnects <NUM> at the surfaces of the dies <NUM> and <NUM> are bonded as well, with reliable electrical conductivity between the interconnects <NUM>. <FIG> shows the first die <NUM> and the second die <NUM> after each has been properly prepared for bonding. For example, the edges and sidewalls of the first die <NUM> and/or the second die <NUM> may be cleaned and etched to remove particles and shards of silicon. The edges of the first die <NUM> and/or the second die <NUM> may be etched with a dry (plasma) etch and/or wet (chemical) etch while the first die <NUM> and/or the second die <NUM> are still on a carrier (e.g., a dicing sheet or tape, grip ring, etc.) after singulation. A protective coating may be applied to the bonding surface of the first die <NUM> and/or the second die <NUM> to protect the surface during the singulation and etching. In one example, the surface and sidewalls of the first die <NUM> and/or the second die <NUM> may be etched, while, in another example, the etching may be limited to the sidewalls of the first die <NUM> and/or the second die <NUM>. It is noted that the interconnects <NUM> are shown simplistically and not to scale. For example, the interconnects <NUM> may comprise one or more layers that together form the interconnect <NUM>. Moreover, the interconnects <NUM> may extend partially or completely through either or both dies <NUM> and <NUM> or may even be provided only at or along the surface(s) of the dies <NUM> and <NUM> as a pattern of traces interconnecting devices within the die(s) <NUM> and <NUM>.

<FIG> illustrates an example process <NUM> of processing stacked dies useful for understanding the present invention. At (A), a substrate <NUM> (which may be a silicon wafer) may include a bonding layer <NUM>, which may comprise an insulator or dielectric layer, such as an oxide, or a hybrid bonding layer, e.g., a combination of insulative material (such as oxide) and electrically conductive interconnect layers. This bonding layer <NUM> may be formed on one or both sides of the substrate <NUM>. Layer(s) <NUM> may be protected by a first protective layer <NUM> and/or a second protective layer <NUM>. Alternatively, the substrate <NUM> may be exposed and/or have any number of protective layers.

At (B), the substrate <NUM> may be singulated on a carrier <NUM>, into a plurality of singulated dies <NUM>. The carrier <NUM> may include a processing sheet, a dicing sheet or tape, grip ring, etc. Additionally, the substrate <NUM> may be singulated using saw dicing, wet etch or dry etch or laser methods or combinations of thereof. The singulated dies <NUM> may have a substantially planar surface.

At (C), the singulated dies <NUM> may be exposed to ultra-violet light (UV) (for example, to cure the adhesive layer on the tape used as a carrier <NUM> for the substrate <NUM>, to reduce the adhesion between the die <NUM> surface contacting the tape, or the like). Additionally, the carrier <NUM> may be stretched while the singulated dies <NUM> are on the carrier <NUM>, in preparation for cleaning and further processing the singulated dies <NUM>. Further processing includes reducing the thickness of the singulated dies <NUM>, for example.

At (D), the singulated dies <NUM> may be cleaned and the sidewalls of the singulated dies <NUM> may be etched. For example, the cleaning may remove one or more protective layers, including the protective layer <NUM> and/or the protective layer <NUM>. The etching may dissolve silicon oxide, silicon nitride, and/or silicon to eliminate the particles and/or shards. Chemical etchants <NUM>, including acids, may be used to etch the periphery of the surface of the dies <NUM>, including the bonding layer <NUM>, and may also be used to etch the sidewalls of the singulated dies <NUM>. In an example where the surface and/or sidewalls of the singulated dies <NUM> are etched (for silicon dies <NUM>, for instance), the etchant <NUM> may comprise a chemical mixture of hydrofluoric acid and a suitable oxidizing agent, for example nitric acid. In some applications, a wet etchant may be comprised of a mixture of buffered hydrofluoric acid and a suitable organic acid in combination with an oxidizing agent. In other applications, a suitable metal complexing agent may be added to the etching solution to protect the metals on the die <NUM> bonding surface from the etchant. In one example, a metal complexing or passivating agent may be comprised of molecules with triazole moieties, for example Benzotriazole (BTA), or the like. The BTA may protect copper on the surface of the singulated dies <NUM> from corrosion or dissolution by the etching solution.

After etching the surface (and sidewalls) of the die <NUM> and stripping off the protective layer <NUM> and/or <NUM>, the complexing agent is cleaned off of the bonding surface of the die <NUM>. As an alternative to a wet etch, the sidewalls of the die <NUM> may also be cleaned using dry etch methods, including using plasma processing similar to processes used in etching silicon. After a dry sidewall etching step, the protective layer <NUM> can be stripped from the bonding surface of the sidewalls of the die <NUM>. Cleaning the protective layer <NUM> may also include cleaning any organic material residues resulting from the dry etching. The organic residue on the side wall of the processed die <NUM> may be left intact. Strongly adhering side wall organic residue may minimize subsequent particles shedding from the die <NUM>.

Additionally, cleaning and/or further processing of the singulated dies <NUM> may occur on a spin fixture <NUM> (or the like). The chemical etchant <NUM> is sprayed onto the diced wafer surface and forms a thin layer over the top surface of the dies <NUM> and fills the gaps between the dies <NUM>. In one embodiment, etching the sidewalls of the singulated dies <NUM> may cause defects on the sidewalls of the dies <NUM> to be removed.

The sidewalls of the dies <NUM> may be selectively coated to coat to the sidewalls and any particles and/or shards that may be present on the sidewalls. For example, a selective coating <NUM> may be applied to the sidewalls, using a spin coating process, an electrocoating process, or the like. The particles and/or shards are coated to the sidewalls with the coating <NUM> to adhere the particles and/or shards to the sidewalls, preventing the particles and/or shards from contaminating other areas of the dies <NUM>, including the bonding surfaces of the dies <NUM>. The coating layer <NUM> comprises a material such as a glass, a boron doped glass, a phosphorus doped glass, or the like, that adheres to the silicon of the sidewalls, and won't generally adhere to any other surfaces.

The coating layer <NUM> comprises a layer that is approximately <NUM> or less, that traps the particles and shards to the sidewalls of the dies <NUM>, and prevents their shedding off the sidewalls. The coating layer <NUM> may be heat cured to the dies <NUM> for stabilization, for a predefined duration at a predefined temperature (e.g., approximately <NUM> degrees C, or the like). While the coating layer <NUM> can be added after cleaning the dies <NUM> as discussed, the coating layer <NUM> may be deposited to the sidewalls at other steps in the process <NUM>.

At (E), the singulated dies <NUM> may undergo plasma processes (such as ashing, for example) to remove any residue of the protective layer <NUM>. At (F), the singulated dies <NUM> may be cleaned to remove any residues or particles of debris resulting from step (E). At (G), the singulated dies <NUM> (including one or both of the oxide layers <NUM>) may be plasma-activated (surface activation) to prepare the singulated dies <NUM> for direct bonding. At (H), the plasma-activated singulated dies <NUM> may be cleaned. At (I), one or more of the singulated dies <NUM> are bonded to a prepared surface of a second substrate <NUM>. In particular, a bonding layer <NUM> (e.g., an oxide or dielectric layer with or without conductive layers) of the singulated dies <NUM> may be bonded directly to the prepared surface of the second substrate <NUM>. The singulated dies <NUM> (via the bonding layer <NUM>) may be bonded to the second substrate <NUM> using a ZIBOND® direct bonding, or DBI® hybrid bonding, technique, or the like, wherein the singulated dies <NUM> are directly bonded (and, in some instances, electrically connected) to portions of the surface of the second substrate <NUM> without the use of adhesives.

In various implementations, the substrate <NUM> may comprise another prepared surface of a silicon wafer, GaAs, diamond coated substrate, silicon carbide, silicon oxide, Silicon Nitride, Lithium Niobate, Lithium Tantalate, flat panel, glass, ceramic, circuit board, package, an interposer, a structure with or without an embedded device or devices, and so forth. The prepared substrate <NUM> comprises the surface of another die <NUM> or another bonded die <NUM>, as discussed further below.

<FIG> illustrates an example process <NUM> of processing stacked dies, according to an embodiment. As described hereinabove, steps (A) - (D) of process <NUM> function in a manner consistent with steps (A) - (D) of process <NUM>. This includes etching the surface and periphery of the dies <NUM> (in a same or separate process step) to remove particles and shards of silicon or oxide from the surface and periphery of the dies <NUM>.

Optionally, in an embodiment, the sidewalls of the dies <NUM> may be selectively coated to coat to the sidewalls and any particles and/or shards that may be present on the sidewalls, as described above. For example, a selective coating <NUM> may be applied to the sidewalls, using a spin coating process, an electrocoating process, or the like. The particles and/or shards are coated to the sidewalls with the coating <NUM> to adhere the particles and/or shards to the sidewalls, preventing the particles and/or shards from contaminating other areas of the dies <NUM>, including the bonding surfaces of the dies <NUM>. In various embodiments, the coating layer <NUM> comprises a material such as a glass, a boron doped glass, a phosphorus doped glass, or the like, that adheres to the silicon of the sidewalls, and won't generally adhere to any other surfaces.

In various embodiments, the coating layer <NUM> comprises a layer that is approximately <NUM> or less, that traps the particles and shards to the sidewalls of the dies <NUM>, and prevents their shedding off the sidewalls. The coating layer <NUM> may be heat cured to the dies <NUM> for stabilization, for a predefined duration at a predefined temperature (e.g., approximately <NUM> degrees C, or the like). While the coating layer <NUM> can be added after cleaning the dies <NUM> as discussed, in various embodiments, the coating layer <NUM> may be deposited to the sidewalls at other steps in the process <NUM>.

With continuing reference to process <NUM>, at (E), the singulated dies <NUM> may be transferred to a spin fixture <NUM> (or the like) and processed/cleaned while on a single carrier, such as the spin plate <NUM> or the like, for all of the described process steps (including singulation, in some embodiments). Alternately, the singulated dies <NUM> can be transferred between different carriers (such as spin plate <NUM>) for one or more processes at each station. At (F), the singulated dies <NUM> may undergo plasma treatment to remove any residue of the protective layer <NUM> (in a similar manner to step (E) of process <NUM>) while still on the spin plate <NUM>.

At (G), the singulated dies <NUM> may be cleaned to remove the residue resulting from the plasma process at (F). At (H), the singulated dies <NUM> may be plasma-activated (surface activation) to prepare the singulated dies <NUM> (including the bonding layer(s) <NUM>) for direct bonding. At (I), the plasma-activated singulated dies <NUM> may be cleaned.

At (J), one or more of the singulated dies <NUM> are bonded to the prepared surface of a second substrate <NUM>. In particular, a bonding layer <NUM> (e.g., an oxide or dielectric layer with or without conductive layers) may be bonded to the prepared surface of the second substrate <NUM>. In one embodiment, the singulated dies <NUM> (via the oxide layer <NUM>) may be directly bonded to the second substrate <NUM> using a ZIBOND® direct bonding, or DBI® hybrid bonding, technique, or the like (e.g., without adhesive or an intervening layer).

At (K), one or more additional singulated dies <NUM>, prepared similarly to the singulated dies <NUM> (e.g., the dies <NUM> may also be singulated from the substrate <NUM>), may be bonded to the exposed second surface of one or more of the singulated dies <NUM>, forming one or more die stacks. In particular, a bonding layer <NUM> (e.g., an oxide or dielectric layer with or without conductive layers) of the singulated dies <NUM> may be directly bonded to the second surface of the singulated dies <NUM>, which has also been prepared for bonding. Preparation for bonding can include one or more cleaning, surface planarizing, and plasma treating process steps as desired. The second surface (including the periphery) of the dies <NUM> is etched to remove undesirable particles and shards, etc..

Additional singulated dies <NUM> may be added in like manner to form die stacks with a desired quantity of die layers. In some embodiments, the singulated dies <NUM> and the second substrate <NUM> may be thermally treated after bonding, with additional thermal treatment after each layer of the singulated dies <NUM> is added. Alternately, the singulated dies <NUM>, the singulated dies <NUM>, and the second substrate <NUM> are thermally treated once several or all layers of the stacked dies (<NUM>, <NUM>) are in place and bonded.

<FIG> illustrates another example process <NUM> of processing stacked dies, according to an embodiment. At (A), a resist layer <NUM> is coated on the singulated dies <NUM>, which include a bonding layer <NUM> (e.g., an insulating or dielectric layer with or without conductive layers or structures) and a substrate region <NUM> (e.g., silicon). In an implementation, the resist layer <NUM> may be patterned, for example to expose the periphery of the singulated dies <NUM> while protecting the rest of the surface of the singulated dies <NUM>. In various embodiments, the singulated dies <NUM> may be singulated using dicing and/or scribing.

At (B), the exposed edges and sidewalls of the singulated dies <NUM> may be cleaned and etched, resulting in an undercut or recess at the periphery of the singulated dies <NUM>. For example, the rough-cut edges of the singulated dies <NUM> may be smoothed by the etching. Additionally, the periphery of the singulated dies <NUM> is recessed to have a reduced overall thickness of the singulated dies <NUM> at the periphery, creating a space at the edges of the singulated dies <NUM>. For instance, the singulated dies <NUM> with the bonding layer <NUM> (e.g., dielectric, oxide, etc.) on the substrate <NUM> (e.g. silicon) may be etched to remove some of the oxide of the bonding layer <NUM> at the periphery of the singulated dies <NUM>, and part of the silicon of the substrate <NUM> as well. The etching causes the dielectric oxide of the bonding layer <NUM> to recess back from the edge of the singulated dies <NUM>, exposing the silicon of the substrate <NUM> below in the recess. In one embodiment, the space formed by the recess may allow for some tolerance to the bonding surfaces during direct bonding, to improve the reliability of the direct bonding technique and to remove stress from the bond.

In one embodiment, the singulated dies <NUM> may be processed at a raised temperature (e.g., <NUM> degrees C) such that the resist layer <NUM> disposed on the oxide layer <NUM> flows and pulls back from the edges of the singulated dies <NUM>. When the edges of the singulated dies <NUM> are etched, the exposed portion of the oxide layer <NUM> may be removed. Additionally, some of the silicon of the substrate <NUM> is removed, depending on the duration and the formulary used for the etching. For example, the longer the duration, the greater the amount of substrate <NUM> may be removed. In some cases, the dielectric oxide layer <NUM> may have a sloped profile as a result of the etching of the singulated dies <NUM>. This sloped profile may extend into the substrate <NUM> (e.g. silicon), if the etching is performed to a depth of the substrate <NUM>.

In some embodiments, the process of etching back the dielectric layer <NUM> may be performed using a lithographic method in combination with dry etching wet etching or both as needed. For example, the surface of the die <NUM> may be patterned, and unwanted portions of the dielectric layer <NUM> removed by dry etching methods, and any unwanted exposed conductive features removed by wet etch methods, for instance. In other applications, it may be preferable to remove unwanted dielectric and conductive portions in one operation. In one example, a wet etchant containing halide ions, for example, buffered hydrofluoric acid and formularies containing hydrogen peroxide or nitric acid (or the like) that can oxidize the conductive features, may be applied to the surface of the dies <NUM> to remove the unwanted dielectric and conductive features. After the removal of the unwanted dielectric and conductive features, a protective layer may be applied for singulation operations.

At (C), the resist layer <NUM> may be removed from the surface of the singulated dies <NUM>. Additionally, at (D), the singulated dies <NUM> may be cleaned.

At (E) and (F), the singulated dies <NUM> are bonded to a second substrate <NUM> (such as another die <NUM> or <NUM>, the second substrate <NUM>, or the like) that has been prepared for bonding as discussed above. In one embodiment, the singulated dies <NUM> may be bonded to a prepared surface of the substrate <NUM> using a ZIBOND® or hybrid DBI® technique, or the like (e.g., without adhesive or an intervening layer). In the illustration of <FIG> at (E) and (F), only the die <NUM> is shown with an oxide layer <NUM>. However, in some embodiments, both of the components to be bonded (e.g., the die <NUM>, die <NUM>, or the substrate <NUM>) may include an oxide region (such as oxide layer <NUM>, for example) at the bonding surface. In other words, the components are bonded at respective oxide regions. In some applications, the dielectric or oxide layer <NUM> of the die <NUM> and the prepared surface of the substrate <NUM> may include conductive features (not shown). The dielectric portions of the prepared surface of the die <NUM> and the substrate <NUM> can be bonded initially at lower temperatures. Any conductive features can be joined at higher temperatures between <NUM> to <NUM>. In other applications, the dielectric portion and conductive feature bonding are formed at the same temperature.

In an implementation shown at (E), as a result of the etching of step (D), the edges of the oxide layer <NUM> of the singulated dies <NUM> may include an undercut <NUM>. In the implementation, the singulated dies <NUM> may include an undercut <NUM> at a periphery of the singulated dies <NUM>, such that an area of the oxide layer <NUM> is less than an area of a footprint of the substrate <NUM> and/or the substrate <NUM>. Additionally, or alternately, in an implementation shown at (F), as a result of the etching of step (D), the edges of the substrate <NUM> and the substrate <NUM> may include an undercut <NUM>. In this implementation, the singulated dies <NUM> may include an undercut <NUM> at a periphery of the singulated dies <NUM>, such that an area of the oxide layer <NUM> is greater than an area of a footprint of the substrate <NUM> and/or the substrate <NUM>. In the implementations, substrate <NUM> and substrate <NUM> may correspond with a first and second bonded microelectronic components, respectively.

According to various embodiments, edge or sidewall etching techniques described herein may provide a reduction of the complexity and cost of direct bond processes for high volume manufacturing of the singulated dies <NUM>. Additionally, removal of dicing particles and shards from a periphery and/or edges of the singulated dies <NUM> may reduce process-related defects in wafer-to-wafer, die-to-wafer, die-to-die, and die-to-system packaging. Further, stress may be reduced in packaged singulated dies <NUM> stacked in three-dimensional arrangements by rounding the edges of the stacked singulated dies <NUM>. The techniques described herein may also result in fewer die processing steps, higher manufacturing through-put, and improved profit margin for ZiBond® and direct bond interconnect (DBI®) manufactured devices. Other advantages of the disclosed techniques will also be apparent to those having skill in the art.

<FIG> is a profile view of a portion of an example die <NUM> with a recessed bonding layer <NUM> (e.g., insulating or dielectric layer with or without conductive layers), according to an embodiment. Additionally, <FIG> is a magnified view of the profile view of the die <NUM> with a recessed bonding layer <NUM> (e.g., oxide region). As shown, the die <NUM> may include the bonding layer <NUM> that is recessed back from the substrate <NUM>. The profile view of <FIG> may correspond with the profile view shown in step (D) of <FIG>, for example. Additionally, <FIG> includes a recess on one side of the bonding layer <NUM>, however, as shown in step (D) of <FIG> and at <FIG>, the recess may be also located on both (or other) sides of the bonding layer <NUM>.

In particular, the sloped profile <NUM> of the oxide layer <NUM> may extend into the substrate <NUM> due to etching (for example, as described with reference to step (D) of <FIG>). Additionally, the sloped profile <NUM> may provide clearance at the perimeter of the substrate <NUM> such that a close and intimate bond may be achieved between, for example, the singulated dies <NUM> and a prepared surface of the second substrate <NUM> (or the like), even in the presence of any particles at the perimeter of the substrate <NUM>.

For instance this is illustrated in <FIG>, wherein an example die <NUM> is shown bonded to another example die <NUM>', forming an example die stack or example microelectronic assembly <NUM> (or the like). As shown in the illustration of <FIG>, the bonding layer <NUM>, which includes an insulating or dielectric material such as oxide and may also include one or more conductive layers or structures <NUM>, is directly bonded to the bonding layer <NUM>', which also includes an insulating or dielectric material such as oxide and may also include one or more conductive layers or structures <NUM>'. Conductive features <NUM> and <NUM>' may extend only into respective bonding layers <NUM> and <NUM>' or may extend partially or entirely through dies <NUM> and <NUM>'. The recess at the bonding layer <NUM> and the recess at the bonding layer <NUM>' (if present) form a gap <NUM> at the periphery of the assembly <NUM>, where the die <NUM> is bonded to the die <NUM>'. In various embodiments, the gap <NUM> may be of such size that any particles <NUM> remaining in the gap <NUM> may not hinder the formation of a close and intimate bond between the bonding surfaces <NUM> and <NUM>', including close and electrically conductive reliable bonds between conductive structures <NUM> and <NUM>'. In various embodiments, the gap <NUM> may be filled as desired, for instance with an encapsulant, a dielectric material, an underfill material, or the like. In other embodiments, the gap <NUM> may remain unfilled, or may be filled with other inert or active materials as desired. Similar profiles as shown in <FIG> may be created on the backsides of dies <NUM> and <NUM>' and more than two dies may be stacked together.

<FIG> is a flow diagram <NUM> illustrating example processes for processing stacked dies, according to an embodiment. At <NUM>, the process includes singulating a plurality of semiconductor die components (such as the singulated dies <NUM> or the singulated dies <NUM>, for example) from a wafer component (such as the substrate <NUM>, for example). In an embodiment, each of the semiconductor die components has a substantially planar surface. In another embodiment, the process includes depositing a protective coating (such as the protective coating <NUM>, for example) over the substantially planar surface of the semiconductor die components (either before or after singulation).

In one embodiment, the process includes heating the plurality of semiconductor die components, after singulating, to cause the protective coating (such as the protective coating <NUM>) to recede from a periphery of the plurality of semiconductor die components. Additionally, the periphery of the plurality of semiconductor die components and/or the substantially planar surface of the plurality of semiconductor die components may be etched to a preselected depth.

Alternatively, the plurality of semiconductor die components may include a dielectric layer over a base semiconductor layer. Additionally, the dielectric layer may have a substantially planar surface and as described above, the dielectric layer may include one or more conductive features. In one embodiment, the process includes etching the periphery of the plurality of semiconductor die components such that at least a portion of the dielectric layer is removed and the base semiconductor layer at the periphery of the plurality of semiconductor die components is exposed.

At <NUM>, the process includes removing the particles and shards of material from the edges the plurality of semiconductor die components. Alternatively, the particles and shards may be removed from the sidewalls of the plurality of semiconductor die components. In one embodiment, the particles and shards may be removed by etching the edges and/or sidewalls of the plurality of semiconductor die components. Optionally, the etching of the edges and/or sidewalls occurs while the plurality of semiconductor die components are on a dicing carrier. Additionally, the etching may use plasma etch and/or a chemical etchant comprising hydrofluoric acid and nitric acid with Benzotriazole (BTA). In an alternative implementation, a protective coating (such as the protective coating <NUM>) may be applied to the substantially planar surface of the plurality of semiconductor die components to protect the substantially planar surface from an etchant.

At <NUM>, the process includes bonding the one or more of the plurality of semiconductor die components to a prepared bonding surface, via the substantially planar surface. For example, the bonding may occur by a direct bond using a ZIBOND® or DBI® bonding technique, or the like, without adhesive or an intervening layer. The bonding may include electrically coupling opposing conductive features at the bonding surfaces of the die(s) and the prepared bonding surface.

The disclosed processes described herein are illustrated using block flow diagrams. Furthermore, the disclosed processes can be implemented in any suitable manufacturing or processing apparatus or system, along with any hardware, software, firmware, or a combination thereof, without departing from the scope of the subject matter described herein.

Claim 1:
A method for forming a microelectronic system, comprising:
singulating (<NUM>) a plurality of semiconductor die components (<NUM>, <NUM>') from a wafer component (<NUM>, <NUM>') comprising a base semiconductor layer;
the semiconductor die components each having a planar surface;
prior to bonding, removing (<NUM>) particles and shards of material (<NUM>) from edges of the plurality of semiconductor die components; and
bonding (<NUM>) one or more of the plurality of semiconductor die components to a prepared bonding surface (<NUM>, <NUM>') via the planar surface; said removing particles and shards comprising:
etching the edges of the plurality of semiconductor die components to reduce a thickness of the plurality of semiconductor die components at a periphery of the plurality of semiconductor die components such that an undercut or recess (<NUM>) in the base semiconductor layer is created at one or more of the edges of each of the plurality of semiconductor die components.