Patent Description:
Patent Document <NUM> discloses a semiconductor device that includes a gate pad, a gate connection wiring made of polysilicon, and a gate metal wiring that is formed on the gate connection wiring and that is continuous integrally with the gate pad. When a voltage is applied to the gate pad, electric power is supplied to a MOSFET formed in an active region through the gate metal wiring and the gate connection wiring.

Document <CIT> discloses a vertical MOS devices with a built-in series polysilicon resistor located between the gate finger connected to the gate electrodes in the active cells and the gate bonding pad and disposed partially below the gate bonding pad. Document <CIT> discloses a field effect type semiconductor device in which a gate series resistor is formed and arranged between the gate wire electrode and the gate bonding pad. The resistor is a polysilicon resistor.

Document <CIT>relates to an MIS type field effector transistor, wherein a gate electrode is formed in an interlayer insulating film and is drawn outside by a gate lead electrode. A gate bonding pad is formed in a part of the electrode. A gate series resistor, made of the same material as that of the gate electrode and having a resistivity different from the gate electrode, is formed between the gate lead electrode and the gate bonding pad.

Document <CIT>) discloses a field effect semiconductor device with a quadrangular gate bonding pad and with a gate series resistors formed and arranged between the gate electrode and the gate bonding pad adjacent to the four corners of the gate bonding pad. The resistors are polysilicon resistors.

Practically, there is a case in which a module having a plurality of semiconductor devices (chips) connected together in parallel is used. The module is provided with gate terminals that are collectively and electrically connected to a gate of each chip. A control voltage is applied to these gate terminals, and, as a result, a voltage is simultaneously applied to the gate of each built-in chip, so that a switching operation is performed.

However, in the thus arranged module, a problem resides in the fact that a noise is liable to occur when the module is in an ON state. This is caused by the fact that variations in gate resistance exist among a plurality of chips and the fact that an electric current concentrates on a chip having relatively low gate resistance in the beginning of ON-controlling. Additionally, variations in gate resistance are caused by variations in processing accuracy (etching size, etc.) when chips are manufactured, and therefore it is difficult to remove these variations.

On the other hand, it is permissible to provide each chip with external gate resistance that has a resistance value larger than the gate resistance in each chip, and yet another problem arises in the fact that the module becomes complicated in structure and it becomes difficult to perform the assembly of the parts.

Therefore, it is an object of the present invention to provide a semiconductor device that has a simple structure and that is capable of reducing the occurrence of a noise even if a plurality of semiconductor devices are connected together in parallel and are simultaneously used.

The invention relates to a semiconductor device according to claim <NUM>. This device includes a SiC semiconductor layer, a plurality of cells that are formed in the SiC semiconductor layer and that are subjected to ON/OFF control by means of a predetermined control voltage, a control electrode that faces a channel region of the cells in which a channel is formed when turned on, a control pad that is exposed at a topmost surface for electric connection with an outside and that is physically separated from the control electrode and is electrically connected to the control electrode, and a built-in resistor that is disposed below the control pad and that is made of polysilicon electrically connecting the control pad and the control electrode together.

According to this arrangement, a polysilicon resistance (built-in resistor) is interposed between the control pad and the cell. In a resistance value (control resistance) obtained by totalizing the resistance value of the control electrode and the resistance value of the built-in resistor, it is possible to make the resistance value of the built-in resistor dominant by adjusting the resistance value of the built-in resistor. Therefore, even when a plurality of semiconductor devices among which a variation exists in the resistance value of the control electrode are used by being connected in parallel with each other, the resistance value of the built-in resistor is set to be larger than this variation, thus making it possible to limit the flow of an electric current into a semiconductor device in which the resistance value of the control electrode is relatively low. As a result, it is possible to reduce the occurrence of a noise when the semiconductor devices are used.

Moreover, polysilicon of which the built-in resistor is made is a material in which the resistance value can be easily controlled by, for example, the implantation of impurities, and its processing has been established by a conventional semiconductor manufacturing technique. Therefore, when the built-in resistor of the present invention is introduced, it is also possible to avoid the complication of the structure of the semiconductor device itself and of the structure of a module provided with this semiconductor device.

In one preferred embodiment of the present invention, the control pad is formed independently while a periphery of the control pad is surrounded by a space, and the built-in resistor is disposed in a region below the control pad with an interlayer film between the built-in resistor and the control pad.

According to this arrangement, it is possible to limit the flow-in of a gate current below the control pad, i.e., at an entrance portion of a current path that leads from the outside to the transistor cells. This makes it possible to prevent a rush current from flowing only to specific transistor cells. As a result, it is possible to reduce a variation in switching speed among the transistor cells.

The built-in resistor may be selectively disposed in a region below the control pad, and the interlayer film may be buried in a first region that is included in the region below the control pad and in which the built-in resistor is not disposed.

Preferably, in that case, the semiconductor device additionally includes an insulating film disposed between the built-in resistor and the SiC semiconductor layer, and a film made of an extension portion of the insulating film is disposed between the interlayer film and the SiC semiconductor layer in the first region.

According to this arrangement, it is possible to enlarge a distance between the SiC semiconductor layer and the control pad (i.e., the thickness of the insulating film) in the first region in which the built-in resistor is not disposed, and hence is possible to reduce the capacity therebetween.

In one preferred embodiment of the present invention, in the SiC semiconductor layer, an impurity region that has a concentration of <NUM>×<NUM><NUM>cm-<NUM> or less is selectively formed in a region facing the built-in resistor with the insulating film between the region and the built-in resistor.

According to this arrangement, the concentration of the impurity region facing the built-in resistor is <NUM>×<NUM><NUM>cm-<NUM> or less, and therefore it is possible to excellently restrain the insulation breakdown of the insulating film. Preferably, in that case, the SiC semiconductor layer is an n type SiC semiconductor layer, and the semiconductor layer has a p- type region of <NUM>×<NUM><NUM>cm-<NUM> or less in a region facing the built-in resistor with an insulating film therebetween. It is more difficult for the p- type region to store carriers than for the n type region, and therefore it is also possible to reduce the capacity between the built-in resistor and the p- type region, both of which face each other with the gate insulating film therebetween.

According to the present invention, a wire region to which a bonding wire is connected is selectively formed on a surface of the control pad, and the built-in resistor is selectively disposed in a region that avoids the wire region when planarly viewed from a normal direction of the SiC semiconductor layer.

According to this arrangement, when a bonding wire is joined, it is possible to restrain the built-in resistor from being damaged by a shock, such as ultrasonic waves, or from being destroyed thereby.

Preferably, in that case, the built-in resistor is disposed below a peripheral edge of the control pad, and the wire region is formed at a middle of the control pad surrounded by the peripheral edge.

In one preferred embodiment of the present invention, a contact via is formed that passes through the interlayer film and by which the control pad and the built-in resistor are electrically connected together.

According to this arrangement, in processing in which the position of the contact via is changed along the surface of the SiC semiconductor layer or in processing in which a via diameter is changed, it is possible to easily adjust a resistance value to which the built-in resistor contributes in a current path that leads from the outside to the transistor cells. Moreover, in these processing operations, it is only necessary to use a mask matched to distance design or to via diameter design when the contact via is formed, and therefore it is also possible to prevent the manufacturing process from becoming complicated.

In one preferred embodiment of the present invention, the plurality of built-in resistors are arranged so as to be symmetrical to each other when planarly viewed from the normal direction of the SiC semiconductor layer.

According to this arrangement, it is possible to prevent a rush current from flowing only to specific transistor cells, and therefore it is possible to reduce a variation in switching speed among the transistor cells.

Preferably, the control electrode is made of p type polysilicon for the reason that the threshold value of a SiC device is raised, and, in more detail, preferably, the control electrode includes B (boron) as a p type impurity.

B (boron) -containing polysilicon has a larger resistivity value than P (phosphorus)-containing polysilicon that is generally used in a Si semiconductor device. Therefore, boron-containing polysilicon (built-in resistor) can manage with a smaller area than phosphorus-containing polysilicon even when the same resistance value is realized. Therefore, it is possible to reduce the occupation area of the built-in resistor on the SiC semiconductor layer, and therefore it is possible to achieve the effective use of space.

A resistance value of the built-in resistor may be <NUM>Ω to <NUM>Ω.

A resistance value obtained by totalizing the resistance value of the control electrode and the resistance value of the built-in resistor may be <NUM>Ω to <NUM>Ω.

In one preferred embodiment of the present invention, sheet resistance of the built-in resistor is <NUM>Ω/□ or more.

In practical use, if the sheet resistance of the built-in resistor is <NUM>Ω/□ or more, it is possible to easily make the resistance value of the entire built-in resistor larger than a variation in the resistance value among a plurality of semiconductor devices without enlarging the area of the built-in resistor. As a result, it is possible to lessen the area of a region sacrificed for the built-in resistor among regions on the SiC semiconductor layer, and therefore other elements are subject to a less influence on the layout of those elements.

In one preferred embodiment of the present invention, a size of the built-in resistor is below <NUM><NUM> for every built-in resistor when planarly viewed from the normal direction of the SiC semiconductor layer.

In practical use, if the size of the built-in resistor is <NUM><NUM> or less, it is possible to reduce the area of a region sacrificed for the built-in resistor among regions of a SiC semiconductor layer, thus making it possible to realize space-saving.

In one preferred embodiment of the present invention, the built-in resistor is <NUM> or less in thickness.

It is possible to easily make the resistance value of the entire built-in resistor larger than a variation in the resistance value among a plurality of semiconductor devices by setting the thickness of the built-in resistor at <NUM> or less. On the contrary, if the built-in resistor is too thick, the built-in resistor is less-than-desirable, because its resistance value becomes too small.

According to the present invention, the semiconductor device additionally includes a finger that is disposed on a topmost surface of the semiconductor device in the same way as the control pad and that extends from the control pad so as to partition a predetermined region, and the plurality of cells are arranged in a region partitioned by the finger, and the built-in resistor connects the control pad and the finger together.

Thus, the feature of the present invention is excellently applicable also to a device having a form in which the finger extends from the control pad.

In one preferred embodiment of the present invention, the finger is made of a metal wiring. The finger is made of a metal wiring that is lower in resistance than polysilicon, and, as a result, it is possible to supply a control current to a cell that is comparatively distant from the control pad in a short time.

In one preferred embodiment of the present invention, the metal wiring is made of Al. Al is easily processed, and therefore it is possible to facilitate a process for forming the finger.

In one preferred embodiment of the present invention, the metal wiring is made of AlCu. According to this arrangement, this makes it possible to render power cycle tolerance higher than when the finger is an Al wiring.

In one preferred embodiment of the present invention, the metal wiring is made of Cu. According to this arrangement, it is possible to render resistivity lower than when the finger is an Al wiring or an AlCu wiring.

The cell may form a MOSFET cell, and the control pad may include a gate pad to apply a gate voltage to the MOSFET cell. In that case, the MOSFET cell may include a planar gate structure or may include a trench gate structure. Additionally, the cell may form an IGBT cell, and the control pad may include a gate pad to apply a gate voltage to the IGBT cell.

A second semiconductor device according to the present invention includes a SiC semiconductor layer, a control pad exposed at a topmost surface for electric connection with an outside, a finger that extends from the control pad so as to partition a predetermined region and that is electrically connected to the control pad, a plurality of cells that are arranged in a region partitioned by the finger in the SiC semiconductor layer and that are subjected to ON/OFF control by means of a control voltage from the control pad, a control electrode that faces a channel region of the cells in which a channel is formed when turned on, and a built-in resistor that is disposed below the control pad and the finger and that connects the control pad and the finger together, the built-in resistor being made of a material that has a resistance value equal to or larger than the finger. In that case, the built-in resistor may be made of a metal. This corresponds to an embodiment not being part of the invention.

A third semiconductor device according to the present invention includes a SiC semiconductor layer, a plurality of cells that are formed in the SiC semiconductor layer and that are subjected to ON/OFF control by means of a predetermined control voltage, a control electrode that faces a channel region of the cells in which a channel is formed when turned on, a control pad that is exposed at a topmost surface for electric connection with an outside and that is physically separated from the control electrode and is electrically connected to the control electrode, and a built-in resistor that is made of polysilicon electrically connecting the control pad and the control electrode together.

The aforementioned or other objects, features, and effects of the present invention will be clarified by the following description of preferred embodiments given below with reference to the accompanying drawings.

Preferred embodiments of the present invention will be hereinafter described in detail with reference to the accompanying drawings.

<FIG> is a schematic plan view of a semiconductor device <NUM> according to one preferred embodiment of the present invention. In <FIG>, for clarification, some elements that are not exposed at the topmost surface of the semiconductor device <NUM> in being actually viewed planarly are shown by the solid line.

The semiconductor device <NUM> is a semiconductor device that employs SiC and that is formed in, for example, a quadrangular chip shape when its topmost surface is planarly viewed from a normal direction (hereinafter, referred to simply as "when viewed planarly").

A terminal region <NUM> that surrounds an active region <NUM> and an active region <NUM> is set in the semiconductor device <NUM>. Although the active region <NUM> is formed in a substantially quadrangular shape when viewed planarly in an inner region of the semiconductor device <NUM> in the present preferred embodiment, no particular limitations are imposed on its shape. A guard ring (not shown) may be formed between the active region <NUM> and the terminal region <NUM> in order to improve the withstanding pressure of the semiconductor device <NUM>.

A gate metal <NUM>, a source metal <NUM>, which are examples of a control pad of the present invention, and a gate finger <NUM>, which is an example of a finger of the present invention, are formed in the active region <NUM>. In such a manner as to cover these elements, a passivation film <NUM> is formed on the topmost surface of the semiconductor device <NUM>. Openings <NUM> and <NUM> by which a part of the gate metal <NUM> and a part of the source metal <NUM> are exposed as a gate pad <NUM> and as a source pad <NUM>, respectively, are formed in the passivation film <NUM>. On the other hand, the gate finger <NUM> is wholly covered with the passivation film <NUM>.

The gate metal <NUM>, the gate finger <NUM>, and the source metal <NUM> are made of a metal wiring such as Al (aluminum), AlCu (aluminum-copper alloy), or Cu (copper).

The gate finger <NUM> is made of a metal wiring that is lower in resistance than polysilicon, and, as a result, it is possible to supply a gate current to a transistor cell <NUM> (see <FIG>) that is comparatively distant from the gate metal <NUM> (in a far position) in a short time. If Al is used, it is possible to facilitate a process for forming these wirings, because Al is excellent in processability (i.e., is tractable). On the other hand, the use of AlCu makes it possible to render power cycle tolerance higher than when Al is used, and makes it possible to improve the junction strength of a bonding wire with respect to the gate pad <NUM>. If Cu is used, it is possible to advantageously render resistivity lower than Al and AlCu.

The gate metal <NUM> is selectively formed at a part of a peripheral edge of the active region <NUM> (near the boundary with the terminal region <NUM>). The gate finger <NUM> branches and extends from the formation position of the gate pad <NUM> in a direction along the peripheral edge of the active region <NUM> and in a direction toward the inside of the active region <NUM>. As a result, in the active region <NUM>, cell regions <NUM> and <NUM> are formed in parts partitioned by a plurality of gate fingers <NUM> that extend in mutually different directions with the gate metal <NUM> therebetween, and are formed in a region outside the gate finger <NUM>.

More specifically, according to the present invention, the gate metal <NUM> is formed in a quadrangular shape when viewed planarly, and is selectively disposed at the middle of a side <NUM> of the active region <NUM>. The other sides except the side <NUM> (at which the gate metal <NUM> is disposed) of the active region <NUM> are a side <NUM>, which is opposite to the side <NUM>, and sides <NUM> and <NUM>, which are each continuous with both ends of the sides <NUM> and <NUM>.

The gate finger <NUM> includes a pad peripheral portion <NUM> that surrounds the periphery of the gate metal <NUM> with a gap therebetween and first and second fingers <NUM> and <NUM> that extend from the pad peripheral portion <NUM> in a direction along the side <NUM> of the active region <NUM> and in a direction perpendicular to the side <NUM>, respectively.

The pad peripheral portion <NUM> is formed in a quadrangular annular shape along the periphery of the gate metal <NUM> when viewed planarly.

The first finger <NUM> is formed as a pair along the side <NUM> in a direction toward the side <NUM> and in a direction toward the side <NUM> opposite to the side <NUM> with respect to the pad peripheral portion <NUM>.

The second finger <NUM> includes a linear main portion <NUM> that crosses the active region <NUM> up to the side <NUM> in a direction perpendicular to the first finger <NUM> and a plurality of branch portions <NUM> that are connected integrally with the main portion <NUM> and that extend from the connected places along the first finger <NUM>. Although the branch portions <NUM> are connected to two places, i.e., to a forward end of the main portion <NUM> and to a halfway portion of the main portion <NUM> and are formed as two pairs in total in the present preferred embodiment, no particular limitations are imposed on this number.

In this way, cell regions <NUM> and <NUM> are defined by the first finger <NUM> and the second finger <NUM> (the main portion <NUM> and the branch portion <NUM>) in the active region <NUM>. In the present preferred embodiment, one inner cell region <NUM> is formed at each corner of the intersection portions formed by the main portion <NUM> and the central branch portion <NUM> of the second finger <NUM>, and hence four inner cell regions <NUM> in total are formed. Additionally, an annular outer cell region <NUM> is formed along the peripheral edge of the active region <NUM> between the peripheral edge of the active region <NUM> and the gate finger <NUM>.

The source metal <NUM> is formed so as to cover the inner and outer cell regions <NUM> and <NUM> substantially wholly. Four openings <NUM> in total are formed in the passivation film <NUM> such that one of the single source pads <NUM> is disposed in one of the inner cell regions <NUM>.

Additionally, a concave portion <NUM> that follows the shape of the gate metal <NUM> is formed in the source metal <NUM>. The gate metal <NUM> is disposed on the inward side of the active region <NUM> with respect to the first finger <NUM> in a setback manner, and hence the concave portion <NUM> is a hollow formed in order to avoid this gate metal <NUM>.

<FIG> is an enlarged view of a region surrounded by the alternate long and short dash line II of <FIG>. In other words, <FIG> is a view in which the gate pad <NUM> of the semiconductor device <NUM> and a region therenear are enlarged. In <FIG>, for clarification, some elements that are not exposed at the topmost surface of the semiconductor device <NUM> in being actually viewed planarly are shown by the solid line.

As shown in <FIG>, a plurality of transistor cells <NUM> are arranged in the inner and outer cell regions <NUM> and <NUM> partitioned by the gate finger <NUM> (the pad peripheral portion <NUM>, the first finger <NUM>, and the second finger <NUM>).

In the present preferred embodiment, in each of the inner and outer cell regions <NUM> and <NUM>, the transistor cells <NUM> are arranged in a matrix manner when viewed planarly. Near the gate finger <NUM>, the transistor cells <NUM> are lined up in accordance with the shape of the gate finger <NUM>. For example, the transistor cells <NUM> are bent and lined up in accordance with the shape of the corner portion of the pad peripheral portion <NUM>, and are linearly lined up in accordance with the shape of the main portion <NUM> of the second linear finger <NUM>. The source metal <NUM> is formed so as to cover these transistor cells <NUM>.

In <FIG>, for clarification, only one part of the plurality of transistor cells <NUM> covered with the source metal <NUM> is shown. Additionally, the arrangement manner of the transistor cells <NUM> is not limited to the matrix manner, and may be, for example, a stripe manner or a zigzag manner. Still additionally, the planar shape of each of the transistor cells <NUM> is not limited to the quadrangular shape, and may be, for example, a circular, triangular, or hexagonal shape.

A gate electrode <NUM> that is an example of a control electrode of the present invention is formed between the transistor cells <NUM> adjoining each other. The gate electrodes <NUM> are each disposed between the transistor cells <NUM> arranged in a matrix manner in the inner and outer cell regions <NUM> and <NUM>, and are formed in a grid-shaped manner as a whole when viewed planarly. On the other hand, this gate electrode <NUM> is formed not only in the inner and outer cell regions <NUM> and <NUM> but also in a region in which the gate finger <NUM> is disposed, and its parts below the gate finger <NUM> are brought into contact with the gate finger <NUM>.

In the present preferred embodiment, parts of the gate electrode <NUM> are formed in regions below the first finger <NUM> and the second finger <NUM>, and face the first finger <NUM> and the second finger <NUM> so as to serve as contact portions, respectively. In <FIG>, for clarification, the parts of the gate electrode <NUM> formed in the regions therebelow are shown as those in hatched regions. As a result, the gate electrodes <NUM> in the mutually adjoining inner cell regions <NUM> are continuous with each other through the gate electrode <NUM> that crosses the second finger <NUM> therebelow. The continuous manner of the gate electrode <NUM> is applied to a relationship between the inner and outer cell regions <NUM> and <NUM> adjoining the gate metal <NUM> in the same way as above. In other words, the gate electrodes <NUM> in these regions are continuous with each other through the gate electrode <NUM> that crosses the first finger <NUM> therebelow.

The first finger <NUM> and the second finger <NUM> are respectively connected to the gate electrodes <NUM> disposed in a region therebelow by means of the gate contact <NUM>. The gate contact <NUM> is formed linearly along each longitudinal direction in a finger middle with an interval from each side edge of the first and second fingers <NUM> and <NUM>.

Additionally, according to the present invention, a plurality of built-in resistors <NUM> are disposed below the gate metal <NUM>. Preferably, the built-in resistors <NUM> are arranged to be symmetric by disposing the built-in resistors <NUM> at positions mutually substantially equally distant from the planarly shaped gravity center position of the gate metal <NUM>. In the present preferred embodiment, the built-in resistors <NUM> are disposed such that one built-in resistor <NUM> is provided at each corner portion of the gate metal <NUM> equally distant from the gravity center G of the gate metal <NUM> having a quadrangular shape when viewed planarly. As a result, symmetry is given to the four built-in resistors <NUM>.

The pattern of this symmetry is variously designable, and, for example, two built-in resistors <NUM> may be disposed at two corner portions, respectively, of the gate metal <NUM> that have an opposite-corner relationship, or two built-in resistors <NUM> may be disposed at two sides, respectively, of the gate metal <NUM> that have an opposite-side relationship so as to face each other. Additionally, for example, if the gate metal <NUM> is circular when viewed planarly, two built-in resistors <NUM> may be disposed at both ends, respectively, of the diameter of the gate metal <NUM>, and if the gate metal <NUM> is triangular when viewed planarly, three built-in resistors <NUM> may be disposed at three corner portions, respectively, of the gate metal <NUM>.

Each built-in resistor <NUM> is formed so as to cross and straddle an annular gap region <NUM> between the gate metal <NUM> and the gate finger <NUM> (pad peripheral portion <NUM>). As a result, the built-in resistor <NUM> faces both the gate metal <NUM> and the gate finger <NUM>. The gate metal <NUM> and the gate finger <NUM> (pad peripheral portion <NUM>) are each connected to the built-in resistor <NUM> disposed in a region therebelow by means of a pad-side contact <NUM> and a cell-side contact <NUM> each of which is an example of a contact via of the present invention.

In the present preferred embodiment, four built-in resistors <NUM> extend from below each peripheral edge <NUM> of two sides of the gate metal <NUM> that have an opposite-side relationship in the outside direction perpendicular to these sides, and reach a part below the pad peripheral portion <NUM>. Each built-in resistor <NUM> is formed in a quadrangular shape when viewed planarly, and has a size of, for example, <NUM>□ (<NUM> × <NUM>) or less. In practical use, if the size of the built-in resistor <NUM> is <NUM>□ or less for every built-in resistor, it is possible to reduce the area of a region sacrificed for the built-in resistor among regions of a SiC epitaxial layer <NUM> (see <FIG>), thus making it possible to realize space-saving.

Additionally, the pad-side contact <NUM> and the cell-side contact <NUM> are each formed in a linear shape parallel to each other along the side of the gate metal <NUM> and the side of the pad peripheral portion <NUM>.

The built-in resistor <NUM> is disposed below the peripheral edge <NUM> of the gate metal <NUM> excluding the middle thereof, and a region above the region in which the built-in resistor <NUM> is disposed is covered with the passivation film <NUM>, and, as a result, the gate pad <NUM> serving as a wire region of the present invention surrounded by the built-in resistors <NUM> is secured at the middle of the gate metal <NUM>. The gate pad <NUM> is a region to which a bonding wire is connected.

In other words, in the present embodiment according to the present invention, each corner portion of the gate metal <NUM> at which the built-in resistor <NUM> is disposed is selectively covered with the passivation film <NUM>, and the other parts of the gate metal <NUM> are exposed from the opening <NUM>. As a result, the gate pad <NUM>, which has a quadrangular shape when viewed planarly and which has corner portions each of which is concaved inwardly, is exposed at the topmost surface of the semiconductor device <NUM>. A region above the region in which the built-in resistor <NUM> is disposed is covered with the passivation film <NUM> in this way, and therefore when a bonding wire is joined, it is possible to prevent the bonding wire from being erroneously joined to a part that overlaps with the built-in resistor <NUM> in the gate metal <NUM>. As a result, when a bonding wire is joined, it is possible to restrain the built-in resistor <NUM> from being damaged by a shock, such as ultrasonic waves, or from being destroyed thereby.

<FIG> are enlarged views of a region surrounded by the alternate long and two short dashes line III of <FIG>, and <FIG> is a plan view, and <FIG> is a cross-sectional view when the semiconductor device <NUM> is cut by the cutting-plane line IIIB-IIIB of <FIG>. In <FIG>, for clarification, there is a case in which the reduced scale of each component differs from that in <FIG> and that in <FIG>, and, likewise, there is a case in which the reduced scale of each component differs between <FIG>. Additionally, in <FIG>, for clarification, some elements that are not exposed at the topmost surface of the semiconductor device <NUM> when actually viewed planarly are shown by the solid line.

Next, a more detailed arrangement of the built-in resistor <NUM> and a neighboring region thereof will be described along with a cross-sectional structure of the semiconductor device <NUM>.

The semiconductor device <NUM> includes a SiC substrate <NUM> and a SiC epitaxial layer <NUM>. The SiC epitaxial layer <NUM> is stacked on the SiC substrate <NUM>, and this layered structure is shown as an example of the SiC semiconductor layer of the present invention.

The SiC substrate <NUM> and the SiC epitaxial layer <NUM> are n+ type SiC and n- type SiC, respectively. The impurity concentration of the n+ type SiC substrate <NUM> is, for example, <NUM> × <NUM><NUM>cm-<NUM> to <NUM> × <NUM><NUM>cm-<NUM>. On the other hand, the impurity concentration of the n- type SiC epitaxial layer <NUM> is, for example, <NUM> × <NUM><NUM>cm-<NUM> to <NUM> × <NUM><NUM>cm-<NUM>. For example, N (nitrogen), P (phosphorus), As (arsenic), etc., can be used as n type impurities (hereinafter, same as above).

In the inner cell region <NUM>, a plurality of transistor cells <NUM> are formed on a surface portion of the SiC epitaxial layer <NUM>. The transistor cells <NUM> include a p- type body region <NUM>, an n+ type source region <NUM> selectively formed in the inner region with an interval from the peripheral edge of the p- type body region <NUM>, and a p+ type body contact region <NUM> selectively formed in the inner region with an interval from the peripheral edge of the n+ type source region <NUM>. The n- type part of the SiC epitaxial layer <NUM> serves as a shared drain region among the transistor cells <NUM>.

As shown in <FIG>, an n+ type source region <NUM> is formed so as to surround the p+ type body contact region <NUM> except the transistor cells <NUM> along the pad peripheral portion <NUM> (gate finger <NUM>) when viewed planarly, and, furthermore, a p- type body region <NUM> is formed so as to surround the n+ type source region <NUM>. In the p- type body region <NUM>, an annular region that surrounds the n+ type source region <NUM> is a channel region <NUM> in which a channel is formed when the semiconductor device <NUM> is brought into an ON state. The transistor cells <NUM> of the outer cell region <NUM> are arranged in the same way although those are not shown in <FIG>.

On the other hand, in the transistor cells <NUM> along the pad peripheral portion <NUM>(gate finger <NUM>), the p- type body region <NUM> and the p+ type body contact region <NUM> are electrically connected to a p- type region <NUM> and a p+ type region <NUM> described below, respectively.

The impurity concentration of the p- type body region <NUM> is, for example, <NUM> × <NUM><NUM>cm-<NUM> to <NUM> × <NUM><NUM>cm-<NUM>, and the impurity concentration of the n+ type source region <NUM> is, for example, <NUM> × <NUM><NUM>cm-<NUM> to <NUM> × <NUM><NUM>cm-<NUM>, and the impurity concentration of the p+ type body contact region <NUM> is, for example, <NUM> × <NUM><NUM>cm-<NUM> to <NUM> × <NUM><NUM>cm-<NUM>.

In order to form these regions <NUM> to <NUM>, the p- type body region <NUM> is formed by ion implantation, for example, into the surface portion of the SiC epitaxial layer <NUM>. Thereafter, the n+ type source region <NUM> and the p+ type body contact region <NUM> are formed by applying the ion implantation of n type impurities and p type impurities, in this order, into a surface portion of the p- type body region <NUM>. As a result, the transistor cells <NUM> composed of regions <NUM> to <NUM> are formed. For example, B (boron), Al (aluminum), etc., can be used as p type impurities (hereinafter, same as above).

A p- type region <NUM> is formed in the surface portion of the SiC epitaxial layer <NUM> in regions other than the inner and outer cell regions <NUM> and <NUM> in the active region <NUM>, i.e., in regions below the gate metal <NUM>, the gate finger <NUM>, and the gap region <NUM>. A p+ type region <NUM> is formed in a surface portion of the p- type region <NUM>.

The p+ type region <NUM> is formed in the substantially whole area of regions below the gate metal <NUM> etc., so as to selectively expose the p- type part of the p- type region <NUM> at the SiC surface in a region of the SiC epitaxial layer <NUM> facing the built-in resistor <NUM> and so as to selectively expose its own p+ type part at the SiC surface in regions other than that region of the SiC epitaxial layer <NUM>. In other words, the gate metal <NUM> and the gate finger <NUM> face the p- type part in a region in which the built-in resistor <NUM> is disposed, and face the p+ type part in most regions other than the region in which the built-in resistor <NUM> is disposed. The p+ type region <NUM> and the p- type region <NUM> are each formed so as to extend to below the source metal <NUM>, and are connected integrally with the p+ type body contact region <NUM> and the p- type body region <NUM> below the source metal <NUM> (in the present preferred embodiment, in parts outside the source pad <NUM>), respectively. In <FIG>, the p+ type body contact region <NUM> and the p+ type region <NUM> of the transistor cells <NUM> along the pad peripheral portion <NUM> (gate finger <NUM>) are shown as hatched regions. In practical use, the p+ type body contact region <NUM> is fixed at ground potential along with the source metal <NUM>, so that the p+ type region <NUM> becomes <NUM> V and is stabilized. Therefore, it is preferable to allow most parts of the gate metal <NUM> and the gate finger <NUM> to face the p+ type region <NUM> as in the present preferred embodiment.

The p+ type region <NUM> and the p- type region <NUM> are each formed through the same process as the p+ type body contact region <NUM> and the p- type body region <NUM> respectively, and its impurity concentration and its depth are also the same.

A gate insulating film <NUM> that is an example of an insulating film of the present invention is formed on the surface of the SiC epitaxial layer <NUM>. The gate insulating film <NUM> is made of an insulating material, such as silicon oxide, and is, for example, <NUM> to <NUM> in thickness. The gate insulating film <NUM> is a shared insulating film to insulate the gate electrode <NUM> and the built-in resistor <NUM> from the SiC epitaxial layer <NUM>.

The gate electrode <NUM> and the built-in resistor <NUM> are formed on the gate insulating film <NUM>. The gate electrode <NUM> is formed so as to face the channel region <NUM> of each transistor cell <NUM> with the gate insulating film <NUM> therebetween. On the other hand, the built-in resistor <NUM> is formed so as to face the exposed p- type part of the p- type region <NUM> with the gate insulating film <NUM> therebetween.

Both the gate electrode <NUM> and the built-in resistor <NUM> are made of p type polysilicon, and may be formed through the same process. In the present preferred embodiment, the gate electrode <NUM> and the built-in resistor <NUM> include B (boron) as a p type impurity. B (boron)-containing polysilicon has a larger resistivity value than P (phosphorus)-containing polysilicon that is generally used in a Si semiconductor device. Therefore, boron-containing polysilicon (built-in resistor <NUM>) can manage with a smaller area than phosphorus-containing polysilicon even when the same resistance value is realized. Therefore, it is possible to reduce the occupation area of the built-in resistor <NUM> on the SiC epitaxial layer <NUM>, and therefore it is possible to achieve the effective use of space.

The concentration of p type impurities included in polysilicon is appropriately changeable in accordance with the design resistance value of the gate electrode <NUM> and the design resistance value of the built-in resistor <NUM>, respectively. This concentration is set so that the sheet resistance of the built-in resistor <NUM> is <NUM>Ω/□ or more in the present preferred embodiment. In practical use, if the sheet resistance of the built-in resistor <NUM> is <NUM>Ω/□ or more, it is possible to easily make the resistance value of the entire built-in resistor <NUM> larger than a variation in the resistance value among a plurality of semiconductor devices <NUM> without enlarging the area of the built-in resistor <NUM>. For example, if a variation in the resistance value is <NUM>Ω to <NUM>Ω, it is possible to set the resistance value of the built-in resistor <NUM> at <NUM>Ω to <NUM>Ω in a state in which the area is small. As a result, it is possible to lessen the area of a region sacrificed for the built-in resistor <NUM> among regions on the SiC epitaxial layer <NUM>, and therefore other elements are subject to a less influence on the layout of those elements. Preferably, in this case, a resistance value obtained by totalizing the resistance value of the gate electrode <NUM> and the resistance value of the built-in resistor <NUM> is <NUM>Ω to <NUM>Ω.

Preferably, the gate electrode <NUM> and the built-in resistor <NUM> are <NUM> or less in thickness. It is possible to easily make the resistance value of the entire built-in resistor <NUM> larger than a variation in the resistance value among a plurality of semiconductor devices <NUM> by setting the thickness of the built-in resistor <NUM> at <NUM> or less. On the contrary, if the built-in resistor <NUM> is too thick, the built-in resistor <NUM> is less-than-desirable, because its resistance value becomes too small.

An interlayer film <NUM> is formed on the gate insulating film <NUM> so as to cover the gate electrode <NUM> and the built-in resistor <NUM>. The interlayer film <NUM> is made of an insulating material, such as silicon oxide, and is, for example, <NUM> to <NUM> in thickness.

Additionally, the interlayer film <NUM> is formed so as to enter a region (first region) in which the gate electrode <NUM> and the built-in resistor <NUM> are not disposed among the regions on the gate insulating film <NUM>. This makes it possible to enlarge a distance between the SiC epitaxial layer <NUM> and the gate metal <NUM> (i.e., the thickness T of the insulating film) in the region in which the built-in resistor <NUM> is not disposed, and hence makes it possible to reduce the capacity therebetween.

The pad-side contact <NUM> and the cell-side contact <NUM> are formed so as to pass through the interlayer film <NUM>. The pad-side contact <NUM> and the cell-side contact <NUM> are each made of a metal via formed integrally with the gate metal <NUM> and the gate finger <NUM> (pad peripheral portion <NUM>).

A source contact <NUM> to take contact from the source metal <NUM> with respect to the n+ type source region <NUM> and the p+ type body contact region <NUM> is formed so as to pass through the interlayer film <NUM>. The source contact <NUM> is made of a metal via formed integrally with the source metal <NUM>.

The gate metal <NUM>, the gate finger <NUM>, and the source metal <NUM> are formed and spaced out on the interlayer film <NUM>.

Then, the passivation film <NUM> is formed on the interlayer film <NUM> so as to cover the gate metal <NUM>, the gate finger <NUM>, and the source metal <NUM>. The openings <NUM> and <NUM> by which parts of the gate metal <NUM> and the source metal <NUM> are exposed are formed in the passivation film <NUM>.

As described above, according to the semiconductor device <NUM>, a polysilicon resistance (built-in resistor <NUM>) is interposed between the gate metal <NUM> and the gate finger <NUM> (pad peripheral portion <NUM>) as shown in <FIG>. In other words, the built-in resistor <NUM> is interposed in the halfway place of a current path that leads from the outside to the transistor cells <NUM>.

In a resistance value (gate resistance) obtained by totalizing the resistance value of the gate electrode <NUM> and the resistance value of the built-in resistor <NUM>, it is possible to make the resistance value of the built-in resistor <NUM> dominant by adjusting the resistance value of the built-in resistor <NUM>. Therefore, even when a plurality of semiconductor devices <NUM> among which a variation exists in the resistance value of the gate electrode <NUM> are used by being connected in parallel with each other, the resistance value of the built-in resistor <NUM> is set to be larger than this variation, thus making it possible to limit the flow of an electric current into a semiconductor device <NUM> in which the resistance value of the gate electrode <NUM> is relatively low. As a result, it is possible to reduce the occurrence of a noise when the semiconductor devices <NUM> are used.

Moreover, polysilicon of which the built-in resistor <NUM> is made is a material in which the resistance value can be easily controlled by, for example, the implantation of impurities, and its processing has been established by a conventional semiconductor manufacturing technique. Therefore, when the built-in resistor <NUM> is introduced, it is also possible to avoid the complication of the structure of the semiconductor device <NUM> itself and of the structure of a module provided with this semiconductor device <NUM>.

The built-in resistor <NUM> is smaller in processing size than the gate electrode <NUM> although there is a case in which a variation in dimension and thickness is caused by a variation in processing accuracy (etching size etc.) when a semiconductor device <NUM> is manufactured as in the same way as in the gate electrode <NUM>. Therefore, in the built-in resistor <NUM>, such a variation hardly causes the occurrence of a noise.

Additionally, the built-in resistor <NUM> is connected to the gate metal <NUM> below the gate metal <NUM>, and therefore it is possible to limit the flow-in of a gate current at an entrance portion of a current path that leads from the outside to the transistor cells <NUM>. This makes it possible to prevent a rush current from flowing only to specific transistor cells <NUM>.

For example, in <FIG>, let it be supposed that the built-in resistor <NUM> is formed at a halfway portion of the first finger <NUM> or of the second finger <NUM> of the gate finger <NUM> as a detour of the finger <NUM> or <NUM>. In this case, there is a case in which a rush current flows from the fingers <NUM> and <NUM> to the gate electrode <NUM> through the gate contact <NUM> on the side closer to the gate metal <NUM> than the built-in resistor <NUM> before reaching the built-in resistor <NUM>. On the other hand, if a gate current can be limited at an entrance portion of a current path as in the present preferred embodiment, it is possible to reduce a variation in switching speed among the transistor cells <NUM>.

Additionally, the built-in resistors <NUM> are symmetrically disposed as shown in <FIG>. This feature also makes it possible to reduce a variation in switching speed among the transistor cells <NUM>.

Additionally, in the SiC epitaxial layer <NUM>, a region facing the built-in resistor <NUM> is the p- type region <NUM> that has an impurity concentration of <NUM> × <NUM><NUM>cm-<NUM> or less as shown in <FIG>. Therefore, it is possible to excellently restrain the insulation breakdown of the gate insulating film <NUM>. Additionally, it is more difficult for the p- type region to store carriers than for the n type region, and therefore it is also possible to reduce the capacity between the built-in resistor <NUM> and the p- type region <NUM> both of which face each other with the gate insulating film <NUM> therebetween.

Additionally, as shown in <FIG>, the gate metal <NUM> and the built-in resistor <NUM> are connected together by means of the pad-side contact <NUM> made of a metal via. Therefore, in processing in which the position of the pad-side contact <NUM> is changed along the surface of the SiC epitaxial layer <NUM> or in processing in which a via diameter is changed, it is possible to easily adjust a resistance value to which the built-in resistor <NUM> contributes in a current path that leads from the outside to the transistor cells <NUM>.

It is possible to easily shorten the distance from the contact position with respect to the built-in resistor <NUM> to the pad peripheral portion <NUM> so as to be changed from D1 to D2, for example, merely by bringing it closer to the pad peripheral portion <NUM> than the pad-side contact <NUM> like the pad-side contact <NUM> shown by the broken line in <FIG>. This makes it possible to lessen the resistance value of the built-in resistor <NUM>. On the contrary, it is possible to enlarge the resistance value of the built-in resistor <NUM> by distancing it from the pad peripheral portion <NUM>. Additionally, it is possible to enlarge the resistance value of a current path to the built-in resistor <NUM> merely by making the via diameter smaller than the pad-side contact <NUM> like the pad-side contact <NUM> shown by the broken line in <FIG>. On the contrary, it is possible to lessen the resistance value of the path by making the via diameter larger.

Moreover, in these processing operations, it is only necessary to use a mask matched to distance design or to via diameter design when the pad-side contact <NUM> (via) is formed, and therefore it is also possible to prevent the manufacturing process from becoming complicated.

Although the preferred embodiment of the present invention has been described as above, the present invention can be embodied in other modes.

For example, although the transistor cell <NUM> is a MOSFET cell having a planar gate structure as described in the aforementioned preferred embodiment, the transistor cell <NUM> may be a MOSFET cell having a trench gate structure as shown in <FIG>. In this case, the gate electrode <NUM> is buried in a gate trench <NUM> formed between the transistor cells <NUM> through the gate insulating film <NUM>.

Additionally, the transistor cell <NUM> may be an IGBT cell having a planar gate structure or a trench gate structure. In this case, it is recommended to use a p+ type SiC substrate <NUM> instead of the n+ type SiC substrate <NUM>.

Additionally, the built-in resistor <NUM> is not required to be embedded in the interlayer film <NUM> below the gate metal <NUM>, and, for example, a polysilicon wiring by which the gate metal <NUM> and the gate finger <NUM> are connected together may be formed on the surface of the interlayer film <NUM> so as to serve as a built-in resistor of the present invention.

Additionally, in an embodiment not being part of the present invention, instead of polysilicon, a material having a resistance value that is equal to or larger than that of the gate metal <NUM> and that of the gate finger <NUM> (for example, a metal wiring of Al (aluminum), AlCu (aluminum-copper alloy), Cu (copper), etc.) may be used as a material of the built-in resistor <NUM>. Even if the built-in resistor <NUM> is a metal, it is possible to lengthen the distance between the gate metal <NUM> and the gate finger <NUM>, and therefore it is possible to enlarge a resistance value obtained by totalizing the resistance value of the gate electrode <NUM> and the resistance value of the built-in resistor <NUM>.

Additionally, in an embodiment not being part of the present invention, the built-in resistor <NUM> is not required to be formed below the gate metal <NUM>, and may be formed below, for example, the gate finger <NUM>.

Additionally, the built-in resistor <NUM> is linear along a part of the peripheral edge <NUM> of the gate metal <NUM>, or, in an embodiment not being part of the present invention, may be annular along the entire periphery of the peripheral edge <NUM> of the gate metal <NUM>.

Additionally, an arrangement in which the conductivity type of each semiconductor part of the aforementioned semiconductor device <NUM> is reversed may be employed. For example, in the semiconductor device <NUM>, the p type part may be an n type, and the n type part may be a p type.

<FIG> is an electric circuit diagram showing an electric circuit of a module to which the semiconductor device according to one preferred embodiment of the present invention is applied.

A module <NUM> includes a plurality of semiconductor devices (chips) <NUM> to <NUM>, a drain terminal <NUM>, a source terminal <NUM>, and a gate terminal <NUM>. Each semiconductor device <NUM> to <NUM> is formed of the semiconductor device <NUM> shown in <FIG>. Each semiconductor device <NUM> to <NUM> may be formed of the semiconductor device shown in <FIG>. The semiconductor devices <NUM> to <NUM> are connected together in parallel.

Each semiconductor device <NUM> to <NUM> includes a plurality of transistor cells <NUM> (see <FIG>, <FIG>) connected together in parallel and four built-in resistors <NUM> (see <FIG>, <FIG>) connected together in parallel. In <FIG>, the transistor cells <NUM> connected together in parallel are represented as one transistor cell Tr, and the four built-in resistors <NUM> connected together in parallel are represented as one resistor R.

The gate electrode of each semiconductor device <NUM> to <NUM> is connected to the gate terminal <NUM> of the module <NUM> through the built-in resistor R contained therein. The drain electrode of each semiconductor device <NUM> to <NUM> is connected to the drain terminal <NUM> of the module <NUM>. The source electrode of each semiconductor device <NUM> to <NUM> is connected to the source terminal <NUM> of the module <NUM>.

In this module <NUM>, a built-in resistor R having a resistance value that is larger than the gate resistance in each semiconductor device <NUM> to <NUM> is contained in each semiconductor device <NUM> to <NUM>. Therefore, in this module <NUM>, the structure of the module becomes simpler than when an external gate resistance having a resistance value larger than the gate resistance in each semiconductor device <NUM> to <NUM> is provided in each semiconductor device <NUM> to <NUM>.

Claim 1:
A semiconductor device comprising:
a SiC semiconductor layer (<NUM>, <NUM>);
a plurality of cells (<NUM>) that are formed in the SiC semiconductor layer (<NUM>, <NUM>) and that are subjected to ON/OFF control by means of a predetermined control voltage;
a control electrode (<NUM>) that faces a channel region (<NUM>) of the cells (<NUM>) in which a channel is formed when turned on;
a control pad (<NUM>) that is exposed at a topmost surface for electric connection with an outside, the control pad (<NUM>) being physically separated from the control electrode (<NUM>) and being electrically connected to the control electrode (<NUM>);
built-in resistors (<NUM>) that are disposed below the control pad and that are made of polysilicon, the built-in resistors electrically connecting the control pad and the control electrode together; and
a finger (<NUM>) disposed on a surface of the SiC semiconductor layer (<NUM>,<NUM>) in the same way as the control pad (<NUM>) and that extends from the control pad (<NUM>) so as to partition a predetermined region,
wherein the plurality of cells (<NUM>) are arranged in a region partitioned by the finger (<NUM>),
each of the built-in resistors (<NUM>) connects the control pad (<NUM>) and the finger (<NUM>) together,
a wire region (<NUM>) selectively formed on a surface of the control pad (<NUM>) for connecting a wire,
each of the built-in resistors (<NUM>) is linear along a part of the peripheral edge of the control pad (<NUM>), wherein the part of the peripheral edge of the control pad (<NUM>) is disposed at a corner portion of the control pad (<NUM>), wherein the corner portion of the control pad (<NUM>) avoids the wire region (<NUM>) when planarly viewed from a normal direction of the SiC semiconductor layer,
each of the built-in resistors (<NUM>) is formed so as to cross and straddle a gap region (<NUM>) between the control pad (<NUM>) and the finger (<NUM>),
the built-in resistors (<NUM>) are disposed selectively in a region below the control pad (<NUM>), and
the built-in resistors (<NUM>) are arranged to be symmetric by disposing the built-in resistors (<NUM>) at positions mutually substantially equally distant from the planarly shaped gravity center position of the control pad (<NUM>).