Patent Description:
An image display device, which reproduces various pieces of information on a screen, is a core technology of the information and communication age, and is being developed in the direction of becoming thinner, lighter, and having higher performance. Thus, a flat panel display device capable of reducing the disadvantageous weight and volume of a cathode ray tube (CRT) is in the spotlight.

Examples of such a flat panel display device include a liquid crystal display (LCD) device, a plasma display panel (PDP), an organic light-emitting display (OLED) device, and an electrophoretic display (ED) device.

As the development of personal electronic devices becomes more active, the flat panel display device is being developed in order to realize a product having excellent portability and/or wearability. As such, a display device capable of realizing low power consumption is required in order to be applied to a portable or wearable device. However, there is a difficulty in realizing low power consumption with the technologies related to display devices developed to date.

<CIT> discloses a flexible display configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.

<CIT> discloses an electronic device display having an array of pixel circuits.

<CIT> discloses a flexible display device with a reduced bezel.

<CIT> discloses an organic light emitting display.

<CIT> discloses a flexible display substrate, a flexible organic light emitting display device, and a method of manufacturing the same.

<CIT> discloses a flexible organic light emitting diode display having an edge bending structure.

<CIT> discloses a flexible display device to reduce a width of a bezel.

The present invention concerns a display device as defined in claim <NUM>.

Accordingly, the present disclosure is directed to a display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

The present disclosure has been provided to solve the problems described above, and an object of the present disclosure is to provide a display device capable of realizing low power consumption.

Additional advantages, objects, and features of the disclosure will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the disclosure. The objectives and other advantages of the disclosure may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these objects and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, the present disclosure may realize low power consumption since a first thin-film transistor having a polycrystalline semiconductor layer and a second thin-film transistor having an oxide semiconductor layer are disposed in an active area. In addition, an opening formed in a bending area is formed to have the same depth as at least one of a plurality of contact holes formed in at least one inorganic insulation layer, which is disposed in the active area, and source and drain electrodes of the second thin-film transistor and source and drain electrodes of the first thin-film transistor, which are disposed below the oxide semiconductor layer, are formed in the same plane using the same material, which may simplify the manufacturing process of a display device. The opening is in the inorganic insulation layer and exposes a signal link and a substrate in the bending area.

It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.

Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings.

<FIG> is a plan view illustrating a display device according to the present disclosure, and <FIG> is a cross-sectional view illustrating the display device according to the present disclosure.

The display device, illustrated in <FIG> and <FIG>, includes a display panel <NUM>, a scan-driving unit <NUM>, and a data-driving unit <NUM>.

The display panel <NUM> is divided into an active area AA provided on a substrate <NUM> and a non-active area NA disposed around the active area AA. The substrate <NUM> is formed of a flexible plastic material so as to be bendable. For example, the substrate <NUM> is formed of polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyestersulfone (PES), polyacrylate (PAR), polysulfone (PSF), circlic-olefin copolymer (COC), or the like.

The active area AA displays an image using unit pixels arranged in a matrix form. The unit pixel may include red (R), green (G), and blue (B) subpixels, or may include red (R), green (G), blue (B), and white (W) subpixels. In one example, red (R), green (G), and blue (B) subpixels may be arranged along the same virtual horizontal line, as illustrated in <FIG>. In another example, red (R), green (G), and blue (B) subpixels may be spaced apart from each other to have a virtual triangular structure, as illustrated in <FIG>.

Each subpixel includes at least one of a thin-film transistor having an oxide semiconductor layer or a thin-film transistor having a polycrystalline semiconductor layer. The thin-film transistor having the oxide semiconductor layer and the thin-film transistor having the polycrystalline semiconductor layer have electron mobility higher than that of a thin-film transistor having an amorphous semiconductor layer, and enable realization of high resolution and low electric power.

At least one of the data-driving unit <NUM> or the scan-driving unit <NUM> may be disposed in the non-active area NA.

The scan-driving unit <NUM> drives scan lines of the display panel <NUM>. The scan-driving unit <NUM> is formed using at least one of the thin-film transistor having the oxide semiconductor layer or the thin-film transistor having the polycrystalline semiconductor layer. Here, the thin-film transistor of the scan-driving unit <NUM> is formed simultaneously with at least one thin-film transistor which is disposed in each subpixel of the active area AA, through the same process.

The data-driving unit <NUM> drives data lines of the display panel <NUM>. The data-driving unit <NUM> may be mounted in a chip form on the substrate <NUM>, or may be mounted in a chip form on a signal transmission film <NUM>, so as to be attached to the non-active area NA of the display panel <NUM>. A plurality of signal pads PAD are disposed in the non-active area NA, as illustrated in <FIG> and <FIG>, in order to be electrically connected to the signal transmission film <NUM>. Driving signals, generated in the data-driving unit <NUM>, the scan-driving unit <NUM>, a power supply unit (not illustrated), and a timing controller (not illustrated), are supplied to signal lines disposed in the active area AA through the signal pads PAD.

The non-active area NA includes a bending area BA, by which the display panel <NUM> is bendable or foldable. The bending area BA is an area that is bent in order to position a non-display area, including the signal pads PAD, the scan-driving unit <NUM>, and the data-driving unit <NUM>, on the rear surface of the active area AA. The bending area BA, as illustrated in <FIG>, is disposed in an upper portion of the non-active area NA between the active area AA and the data-driving unit <NUM>. Alternatively, the bending area BA may be disposed in at least one of an upper, lower, left, or right portion of the non-active area NA. Thereby, on the entire screen of the display device, the area occupied by the active area AA is maximized and the area occupied by the non-active area NA is minimized.

Signal links LK are disposed in the bending area BA to interconnect the signal pads PAD and the signal lines disposed in the active area AA. When the signal links LK are formed in straight lines along the bending direction BD, the greatest bending stress may be applied to the signal links LK, causing cracks or a short-circuit thereof. Therefore, in the present invention, the area of each signal link LK is increased in the direction crossing the bending direction BD so as to minimize bending stress. To this end, the signal links LK may be shaped to have a zigzag form or a sinusoidal form, as illustrated in <FIG>, or may take the form of a plurality of diamonds that have an empty central area and are connected to each other in a line form, as illustrated in <FIG>.

As illustrated in <FIG>, at least one opening <NUM> is formed in the bending area BA so as to enable easy bending of the bending area BA. The opening <NUM> is formed by removing a plurality of inorganic insulation layers <NUM> disposed in the bending area BA, so that the signal links LK are formed on the substrate <NUM>. Specifically, when the substrate <NUM> undergoes bending, continuous bending stress is applied to the inorganic insulation layers <NUM> disposed in the bending area BA. Since the inorganic insulation layers <NUM> have elasticity lower than that of an organic insulation material, cracks may be easily formed in the inorganic insulation layers <NUM>. The cracks formed in the inorganic insulation layers <NUM> spread to the active area AA along the inorganic insulation layers <NUM>, thus causing a line defect and an element driving defect. Therefore, the inorganic insulation layers <NUM> are removed from the bending area BA, and at least one planarization layer <NUM> is formed in the bending area BA using an organic insulation material having elasticity higher than that of the inorganic insulation layers <NUM>. The planarization layer <NUM> may serve to alleviate bending stress caused upon bending of the substrate <NUM>, thereby preventing the formation of cracks. The opening <NUM> in the bending area BA is formed through the same mask process as at least one contact hole, among a plurality of contact holes disposed in the active area AA, which may simplify the structure of the display device and the manufacturing process thereof.

The display device, which may simplify the structure and the manufacturing process thereof as described above, may be applied to a display device that requires thin-film transistors, such as a liquid crystal display device or an organic light-emitting display device. Hereinafter, an embodiment of the present disclosure in which the display device, which may simplify the structure and the manufacturing process, is applied to an organic light-emitting display device, will be described.

Each subpixel SP of the organic light-emitting display device, as illustrated in <FIG> and <FIG>, includes a pixel-driving circuit and a light-emitting element <NUM> connected to the pixel-driving circuit.

The pixel-driving circuit may have a 2T1C structure including two thin-film transistors ST and DT and a single storage capacitor Cst, as illustrated in <FIG>, or may have a 4T1C structure including four thin-film transistors ST1, ST2, ST3 and DT and a single storage capacitor Cst, as illustrated in <FIG>. Here, the pixel-driving circuit is not limited to the structures of <FIG> and <FIG>, and any of various other pixel-driving circuits may be used.

The storage capacitor Cst of the pixel-driving circuit illustrated in <FIG> is located between and connected to a gate node Ng and a source node Ns to maintain a constant voltage between the gate node Ng and the source node Ns. A driving transistor DT includes a gate electrode connected to the gate node Ng, a drain electrode connected to a drain node Nd, and a source electrode connected to the light-emitting element <NUM>. The driving transistor DT controls the magnitude of driving current depending on the voltage between the gate node Ng and the source node Ns. A switching transistor ST includes a gate electrode connected to a scan line SL, a drain electrode connected to a data line DL, and a source electrode connected to the gate node Ng. The switching transistor ST is turned on in response to a scan control signal SC from the scan line SL, and supplies a data voltage Vdata from the data line DL to the gate node Ng. The light-emitting element <NUM> is located between and connected to the source node Ns, which is connected to the source electrode of the driving transistor DT, and a low-potential supply line <NUM> to emit light based on driving current.

The pixel-driving circuit illustrated in <FIG> has substantially the same configuration as the pixel-driving circuit illustrated in <FIG>, except that a drain electrode of a first switching transistor ST1 connected to the data line DL is connected to the source node Ns and that the pixel-driving circuit further includes second and third switching transistors ST2 and ST3. Thus, a detailed description related to the same configuration will be omitted.

The first switching transistor ST1 illustrated in <FIG> and <FIG> includes a gate electrode <NUM> connected to a first scan line SL1, a drain electrode <NUM> connected to the source node Ns, a source electrode <NUM> connected to the data line DL, and a semiconductor layer <NUM> forming a channel between the source and drain electrodes <NUM> and <NUM>. The first switching transistor ST1 is turned on in response to a scan control signal SC1 from the first scan line SL1, and supplies the data voltage Vdata from the data line DL to the source node Ns.

The second switching transistor ST2 includes a gate electrode GE connected to a second scan line SL2, a drain electrode DE connected to a reference line RL, a source electrode SE connected to the gate node Ng, and a semiconductor layer ACT forming a channel between the source and drain electrodes SE and DE. The second switching transistor ST2 is turned on in response to a scan control signal SC2 from the second scan line SL2, and supplies a reference voltage Vref from the reference line RL to the gate node Ng.

The third switching transistor ST3 includes a gate electrode GE connected to an emission control line EL, a drain electrode DE connected to the drain node Nd, a source electrode SE connected to a high-potential supply line <NUM>, and a semiconductor layer ACT forming a channel between the source and drain electrodes SE and DE. The third switching transistor ST3 is turned on in response to an emission control signal EM from the emission control line EL, and supplies a high-potential voltage VDD from the high-potential supply line <NUM> to the drain node Nd.

Each of the high-potential supply line <NUM> and the low-potential supply line <NUM>, included in the pixel-driving circuit described above, is formed to have a mesh shape so as to be shared by at least two subpixels. To this end, the high-potential supply line <NUM> includes first and second high-potential supply lines 172a and 172b crossing each other, and the low-potential supply line <NUM> includes first and second low-potential supply lines 162a and 162b crossing each other.

Each of the second high-potential supply line 172b and the second low-potential supply line 162b is disposed parallel to the data line DL, and is formed in a number of one for at least two subpixels. In other words, one second high-potential supply line 172b and one second low-potential supply line 162b may connect to at least two subpixels. The second high-potential supply line 172b and the second low-potential supply line 162b may be disposed parallel to each other, as illustrated in <FIG> and <FIG>, or may be disposed parallel to each other in the vertical direction so as to overlap each other, as illustrated in <FIG>.

The first high-potential supply line 172a is electrically connected to the second high-potential supply line(s) 172b, and is disposed parallel to the scan line SL. The first high-potential supply line 172a is branched from the second high-potential supply line 172b so as to cross the second high-potential supply line 172b. Thereby, the first high-potential supply line 172a may compensate for the resistance of the second high-potential supply line 172b, thereby minimizing the voltage drop (IR drop) of the high-potential supply line <NUM>.

The first low-potential supply line 162a is electrically connected to the second low-potential supply line(s) 162b, and is disposed parallel to the scan line SL. The first low-potential supply line 162a is branched from the second low-potential supply line 162b so as to cross the second low-potential supply line 162b. Thereby, the first low-potential supply line 162a may compensate for the resistance of the second low-potential supply line 162b, thereby minimizing the voltage drop (IR drop) of the low-potential supply line <NUM>.

Since the high-potential supply line <NUM> and the low-potential supply line <NUM> described above are formed to have a mesh shape, the number of second high-potential supply lines 172b and the number of second low-potential supply lines 162b, which are disposed in the vertical direction, may be reduced, and a greater number of subpixels may be disposed in proportion to a reduced number of the second high-potential supply lines 172b and to a reduced number of second low-potential supply lines 162b, which results in an increased aperture ratio and resolution.

One of the plurality of transistors included in the pixel-driving circuit described above includes a polycrystalline semiconductor layer, and the other transistor includes an oxide semiconductor layer.

For example, as illustrated in <FIG>, the switching transistor ST of the pixel-driving circuit illustrated in <FIG> is configured as a first thin-film transistor <NUM> having a polycrystalline semiconductor layer <NUM>, and the driving transistor DT is configured as a second thin-film transistor <NUM> having an oxide semiconductor layer <NUM>. Then, each of the first and third switching transistors ST1 and ST3 of the pixel-driving circuit illustrated in <FIG> and <FIG> is configured as the first thin-film transistor <NUM> having the polycrystalline semiconductor layer <NUM>, and each of the second switching transistor ST2 and the driving transistor DT is configured as the second thin-film transistor <NUM> having the oxide semiconductor layer <NUM>. As such, the present disclosure may reduce power consumption by using the second thin-film transistor <NUM> having the oxide semiconductor layer <NUM> as the driving transistor DT of each subpixel and using the first thin-film transistor <NUM> having the polycrystalline semiconductor layer <NUM> as the switching transistor ST of each subpixel.

The first thin-film transistor <NUM> illustrated in <FIG> and <FIG> includes the polycrystalline semiconductor layer <NUM>, a first gate electrode <NUM>, a first source electrode <NUM>, and a first drain electrode <NUM>.

The polycrystalline semiconductor layer <NUM> is formed on a lower buffer layer <NUM>. The polycrystalline semiconductor layer <NUM> includes a channel area, a source area, and a drain area. The channel area overlaps the first gate electrode <NUM> with a lower gate insulation layer <NUM> interposed therebetween, so that the channel area is formed between the first source electrode <NUM> and the first drain electrode <NUM>. The source area is electrically connected to the first source electrode <NUM> through a first source contact hole <NUM>. The drain area is electrically connected to the first drain electrode <NUM> through a first drain contact hole 160D. Since the polycrystalline semiconductor layer <NUM> has mobility higher than that of an amorphous semiconductor layer and the oxide semiconductor layer <NUM>, and exhibits low power consumption and high reliability, the polycrystalline semiconductor layer <NUM> is suitable for application to the scan-driving unit <NUM>, which drives the switching transistor ST and the scan line SL of each subpixel. A multilayered buffer layer <NUM> and the lower buffer layer <NUM> are disposed between the polycrystalline semiconductor layer <NUM> and the substrate <NUM>. The multilayered buffer layer <NUM> delays the diffusion of moisture and/or oxygen introduced into the substrate <NUM>. The multilayered buffer layer <NUM> is formed by alternately stacking a silicon nitride (SiNx) and a silicon oxide (SiOx) at least one time. The lower buffer layer <NUM> functions to protect the polycrystalline semiconductor layer <NUM> and to block various kinds of defective materials introduced from the substrate <NUM>. The lower buffer layer <NUM> may be formed of a-Si (amorphous silicon), a silicon nitride (SiNx), a silicon oxide (SiOx), or the like.

The first gate electrode <NUM> is formed on the lower gate insulation layer <NUM>. The first gate electrode <NUM> overlaps the channel area of the polycrystalline semiconductor layer <NUM> with the lower gate insulation layer <NUM> interposed therebetween. The first gate electrode <NUM> may be formed in a single layer or in multiple layers using the same material as a lower storage electrode <NUM>, for example, one of molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, without being limited thereto.

First and second lower interlayer insulation layers <NUM> and <NUM> located on the polycrystalline semiconductor layer <NUM> are configured as inorganic layers having a higher content of hydrogen than that in an upper interlayer insulation layer <NUM>. For example, the first and second lower interlayer insulation layers <NUM> and <NUM> are formed of a silicon nitride (SiNx) through a deposition process using NH<NUM> gas, and the upper interlayer insulation layer <NUM> is formed of a silicon oxide (SiOx). Hydrogen atoms included in the first and second lower interlayer insulation layers <NUM> and <NUM> are diffused to the polycrystalline semiconductor layer <NUM> during a hydrogenation process so that pores in the polycrystalline semiconductor layer <NUM> are filled with hydrogen. Thereby, the polycrystalline semiconductor layer <NUM> may be stabilized, which may prevent deterioration in the characteristics of the first thin-film transistor <NUM>.

The first source and first drain electrodes <NUM> and <NUM> are disposed below the oxide semiconductor layer <NUM>. The first source electrode <NUM> is connected to the source area of the polycrystalline semiconductor layer <NUM> through the first source contact hole <NUM>, which is formed in the first and second lower interlayer insulation layers <NUM> and <NUM>. The first drain electrode <NUM> is disposed so as to face the first source electrode <NUM>, and is connected to the drain area of the polycrystalline semiconductor layer <NUM> through the first drain contact hole 160D, which is formed in the lower gate insulation layer <NUM> and the first and second lower interlayer insulation layers <NUM> and <NUM>. Since the first source and first drain electrodes <NUM> and <NUM> are formed in the same plane as a storage supply line <NUM> using the same material as the storage supply line <NUM>, the first source and first drain electrodes <NUM> and <NUM> may be formed simultaneously with the storage supply line <NUM> through the same mask process.

After activation and hydrogenation processes of the polycrystalline semiconductor layer <NUM> of the first thin-film transistor <NUM>, the oxide semiconductor layer <NUM> of the second thin-film transistor <NUM> is formed. That is, the oxide semiconductor layer <NUM> is located on the polycrystalline semiconductor layer <NUM>. Thereby, since the oxide semiconductor layer <NUM> is not exposed to a high-temperature atmosphere in the activation and hydrogenation processes of the polycrystalline semiconductor layer <NUM>, it is possible to prevent damage to the oxide semiconductor layer <NUM>, which results in increased reliability.

The second thin-film transistor <NUM> is disposed on the second lower interlayer insulation layer <NUM> so as to be spaced apart from the first thin-film transistor <NUM>. The second thin-film transistor <NUM> includes a second gate electrode <NUM>, the oxide semiconductor layer <NUM>, a second source electrode <NUM>, and a second drain electrode <NUM>.

The second gate electrode <NUM> overlaps the oxide semiconductor layer <NUM> with an upper gate insulation pattern <NUM> interposed therebetween. The second gate electrode <NUM> is formed on the upper gate insulation pattern <NUM>, which is the same plane as the first low-potential supply line 162a, using the same material as the first low-potential supply line 162a. Thereby, the second gate electrode <NUM> and the first low-potential supply line 162a may be formed through the same mask process, which may reduce the number of mask processes.

The oxide semiconductor layer <NUM> is formed on an upper buffer layer <NUM> so as to overlap the second gate electrode <NUM>, thereby forming a channel between the second source and second drain electrodes <NUM> and <NUM>. The oxide semiconductor layer <NUM> is formed of an oxide including at least one metal selected from among the group consisting of Zn, Cd, Ga, In, Sn, Hf, and Zr. Since the second thin-film transistor <NUM> including the oxide semiconductor layer <NUM> has lower leakage current than the first thin-film transistor <NUM> including the polycrystalline semiconductor layer <NUM>, the second thin-film transistor <NUM> may be applied to the switching transistor ST and the driving transistor DT, which keep a short on-time and a long off-time.

The upper interlayer insulation layer <NUM> and the upper buffer layer <NUM>, which are close to the top and the bottom of the oxide semiconductor layer <NUM>, are configured as inorganic layers having a lower content of hydrogen than that in the lower interlayer insulation layers <NUM> and <NUM>. For example, the upper interlayer insulation layer <NUM> and the upper buffer layer <NUM> are formed of a silicon oxide (SiOx), and the lower interlayer insulation layers <NUM> and <NUM> are formed of a silicon nitride (SiNx). Thereby, it is possible to prevent hydrogen atoms in the lower interlayer insulation layers <NUM> and <NUM> and hydrogen atoms in the polycrystalline semiconductor layer <NUM> from being diffused to the oxide semiconductor layer <NUM> during a thermal treatment process of the oxide semiconductor layer <NUM>.

The second source and second drain electrodes <NUM> and <NUM> are disposed below the oxide semiconductor layer <NUM>. The second source and second drain electrodes <NUM> and <NUM> may be formed in a single layer or in multiple layers on the second lower interlayer insulation layer <NUM> using one of molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, without being limited thereto.

The second source electrode <NUM> is exposed through a second source contact hole <NUM> formed in the upper buffer layer <NUM>, and is connected to a source area of the oxide semiconductor layer <NUM>. The second drain electrode <NUM> is exposed through a second drain contact hole 110D formed in the upper buffer layer <NUM>, and is connected to a drain area of the oxide semiconductor layer <NUM>. The second source and second drain electrodes <NUM> and <NUM> are formed so as to face each other with a channel area of the oxide semiconductor layer <NUM>.

The storage capacitor Cst or <NUM>, as illustrated in <FIG>, is formed in a manner such that the lower storage electrode <NUM> and a upper storage electrode <NUM> overlap each other with the first lower interlayer insulation layer <NUM> interposed therebetween.

The lower storage electrode <NUM> is connected to one of the second gate electrode <NUM> of the driving transistor DT and the second source electrode <NUM> of the driving transistor DT. The lower storage electrode <NUM> is formed on the lower gate insulation layer <NUM> so as to overlap the oxide semiconductor layer <NUM> with a width similar to that of the oxide semiconductor layer <NUM>, thereby preventing external light from being incident on the oxide semiconductor layer <NUM>. The lower storage electrode <NUM> is located on the lower gate insulation layer <NUM> and is formed on the same layer as the first gate electrode <NUM> using the same material as the first gate electrode <NUM>.

The upper storage electrode <NUM> is connected to the other one of the second gate electrode <NUM> of the driving transistor DT and the second source electrode <NUM> of the driving transistor DT via the storage supply line <NUM>. The upper storage electrode <NUM> is formed on the first lower interlayer insulation layer <NUM> so as to overlap the oxide semiconductor layer <NUM> with a width similar to that of the oxide semiconductor layer <NUM>, thereby preventing external light from being incident on the oxide semiconductor layer <NUM>. The upper storage electrode <NUM> is located on the same layer as the first high-potential supply line 172a using the same material as the first high-potential supply line 172a. The upper storage electrode <NUM> is exposed through a storage contact hole <NUM> formed in the second lower interlayer insulation layer <NUM>, and is connected to the storage supply line <NUM>.

The first lower interlayer insulation layer <NUM>, disposed between the lower storage electrode <NUM> and the upper storage electrode <NUM>, is formed of an inorganic insulation material such as SiOx or SiNx. The first lower interlayer insulation layer <NUM> may be formed of SiNx having a dielectric constant higher than that of SiOx. Thereby, the lower storage electrode <NUM> and the upper storage electrode <NUM> overlap each other, with the first lower interlayer insulation layer <NUM>, which is formed of SiNx having a high dielectric constant, therebetween, which causes an increase in the capacitance of the storage capacitor Cst that is proportional to the dielectric constant.

The light-emitting element <NUM> includes an anode electrode <NUM> connected to the second source electrode <NUM>, at least one emission stack <NUM> formed on the anode electrode <NUM>, and a cathode electrode <NUM> formed on the emission stack <NUM>.

The anode electrode <NUM> is connected to a pixel connection electrode <NUM>, which is exposed through a second pixel contact hole <NUM> formed in a second planarization layer <NUM>. Here, the pixel connection electrode <NUM> is connected to the oxide semiconductor layer <NUM>, which is exposed through the first pixel contact hole <NUM> formed in the first planarization layer <NUM> and the upper interlayer insulation layer <NUM>.

The anode electrode <NUM> is formed to have a multilayered structure including a transparent conductive layer and an opaque conductive layer having high reflection efficiency. The transparent conductive layer is formed of a material having a relatively large work function value, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The opaque conductive layer is formed in a single layer or in multiple layers using Al, Ag, Cu, Pb, Mo, Ti, or an alloy thereof. For example, the anode electrode <NUM> may be formed in a manner such that a transparent conductive layer, an opaque conductive layer, and a transparent conductive layer are sequentially stacked, or may be formed in a manner such that a transparent conductive layer and an opaque conductive layer are sequentially stacked. The anode electrode <NUM> is disposed on the second planarization layer <NUM> so as to overlap not only a light-emitting area provided by a bank <NUM> but also a circuit area in which the first and second thin-film transistors <NUM> and <NUM> and the storage capacitor (Cst) <NUM> are disposed, which increases a light-emitting area.

The emission stack <NUM> is formed by stacking a hole-related layer, an organic emission layer, and an electron-related layer on the anode electrode <NUM> in this order or in reverse order. Alternatively, the emission stack <NUM> may include first and second emission stacks, which face each other with a charge generation layer interposed therebetween. In this case, the organic emission layer of one of the first and second emission stacks generates blue light and the organic emission layer of the other one of the first and second emission stacks generates yellow-green light, whereby white light is generated by the first and second emission stacks. When the white light generated in the emission stack <NUM> is incident on a color filter (not illustrated), which is located on the emission stack <NUM>, a color image may be formed. Alternatively, a color image may be formed without a separate color filter when each emission stack <NUM> generates colored light corresponding to each subpixel. That is, the emission stack <NUM> of a red (R) subpixel may generate red light, the emission stack <NUM> of a green (G) subpixel may generate green light, and the emission stack <NUM> of a blue (B) subpixel may generate blue light.

The bank <NUM> is formed so as to expose the anode electrode <NUM> of each subpixel. The bank <NUM> may be formed of an opaque material (e.g. black carbon) in order to prevent optical interference between adjacent subpixels. In this case, the bank <NUM> includes a light-blocking material containing at least one of a color pigment or organic black carbon.

The cathode electrode <NUM> is formed on the upper surface and the side surface of the emission stack <NUM> so as to face the anode electrode <NUM> with the emission stack <NUM> interposed therebetween. When the cathode electrode <NUM> is applied to a top-emission-type organic light-emitting display device, it is formed of a transparent conductive layer, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

The cathode electrode <NUM> is electrically connected to the low-potential supply line <NUM>. The low-potential supply line <NUM>, as illustrated in <FIG> and <FIG>, include the first and second low-potential supply lines 162a and 162b crossing each other. The first low-potential supply line 162a, as illustrated in <FIG>, is formed on the upper gate insulation pattern <NUM>, which is the same layer as the second gate electrode <NUM>, using the same material as the second gate electrode <NUM>. The second low-potential supply line 162b is formed on the first planarization layer <NUM>, which is the same layer as the pixel connection electrode <NUM>, using the same material as the pixel connection electrode <NUM>. The second low-potential supply line 162b is electrically connected to the first low-potential supply line 162a, which is exposed through a first line contact hole <NUM> formed in the upper interlayer insulation layer <NUM> and the first planarization layer <NUM>.

The high-potential supply line <NUM>, which supplies a high-potential voltage VDD higher than a low-potential voltage VSS supplied through the low-potential supply line <NUM>, as illustrated in <FIG> and <FIG>, include the first and second high-potential supply lines 172a and 172b. The first high-potential supply line 172a, as illustrated in <FIG>, is formed on the first lower interlayer insulation layer <NUM>, which is the same layer as the upper storage electrode <NUM>, using the same material as the upper storage electrode <NUM>. The second high-potential supply line 172b is formed on the second lower interlayer insulation layer <NUM>, which is the same layer as the second source and second drain electrodes <NUM> and <NUM>, using the same material as the second source and second drain electrodes <NUM> and <NUM>. The second high-potential supply line 172b is electrically connected to the first high-potential supply line 172a, which is exposed through a second line contact hole <NUM> formed in the second lower interlayer insulation layer <NUM>.

Here, the second low-potential supply line 162b and the second high-potential supply line 172b vertically overlap each other with the upper buffer layer <NUM>, the upper interlayer insulation layer <NUM>, and the first planarization layer <NUM> interposed therebetween. In this case, even if micro-bubbles are formed in the first planarization layer <NUM> during a coating process of the first planarization layer <NUM> formed of an organic insulation material, the second low-potential supply line 162b and the second high-potential supply line 172b are electrically insulated from each other by the upper buffer layer <NUM> formed of an inorganic insulation material and the upper interlayer insulation layer <NUM>, which are disposed between the second low-potential supply line 162b and the second high-potential supply line 172b. Thus, it is possible to prevent a short-circuit between the second low-potential supply line 162b and the second high-potential supply line 172b by the upper buffer layer <NUM> and the upper interlayer insulation layer <NUM>.

A signal link <NUM>, which is connected to at least one of the low-potential supply line <NUM>, the high-potential supply line <NUM>, the data line DL, the scan line SL, the reference line RL, or the emission control line EL, is formed so as to traverse the bending area BA in which first and second openings <NUM> and <NUM> are located. The first opening <NUM> is formed so as to expose the side surface of each of the multilayered buffer layer <NUM>, the lower buffer layer <NUM>, the lower gate insulation layer <NUM>, and the first and second lower interlayer insulation layers <NUM> and <NUM>. The first opening <NUM> is formed through the same mask process as the first source contact hole <NUM> and the first drain contact hole 160D. Thus, the first opening <NUM> may be formed to have a depth d1, which is equal to or greater than that of at least one of the first source contact hole <NUM> or the first drain contact hole 160D. The second opening <NUM> exposes the side surface of the upper interlayer insulation layer <NUM>, and thus has a second depth D2, which is smaller than the first depth d1. The second opening <NUM> is formed through the same mask process as the first pixel contact hole <NUM> formed in the upper interlayer insulation layer <NUM>. Thus, the second opening <NUM> has the same depth d2 as the first pixel contact hole <NUM> formed in the upper interlayer insulation layer <NUM>.

The signal link <NUM>, as illustrated in <FIG>, may be formed together with the pixel connection electrode <NUM> through the same mask process as the pixel connection electrode <NUM>. In this case, the signal link <NUM> is formed in the same plane as the pixel connection electrode <NUM>, i.e. on the first planarization layer <NUM>, using the same material as the pixel connection electrode <NUM>. The second planarization layer <NUM> may be disposed on the signal link <NUM> so as to cover the signal link <NUM> formed on the first planarization layer <NUM>. Alternatively, an encapsulation film or an inorganic encapsulation layer, which takes the form of an encapsulation stack including inorganic and organic encapsulation layers, is disposed without the second planarization layer <NUM>. The signal link <NUM>, as illustrated in <FIG>, may be formed together with the source and drain electrodes <NUM>, <NUM>, <NUM> and <NUM> through the same mask process as the source and drain electrodes <NUM>, <NUM>, <NUM> and <NUM>. In this case, the signal link <NUM> is formed in the same plane as the source and drain electrodes <NUM>, <NUM>, <NUM> and <NUM>, i.e. on the second lower interlayer insulation layer <NUM> using the same material as the source and drain electrodes <NUM>, <NUM>, <NUM> and <NUM>, and is also formed on the substrate <NUM> so as to come into contact with the substrate <NUM>. At least one of the first or second planarization layer <NUM> or <NUM> may be disposed on the signal link <NUM>, or an encapsulation film or an inorganic encapsulation layer, which takes the form of an encapsulation stack including inorganic and organic encapsulation layers, is disposed without the first and second planarization layers <NUM> and <NUM>, so as to cover the signal link <NUM> formed on the second lower interlayer insulation layer <NUM> and the substrate <NUM>. As illustrated in <FIG>, the signal link <NUM> is formed on the side surfaces of the multilayered buffer layer <NUM>, the lower buffer layer <NUM>, the lower gate insulation layer <NUM>, and the first and second lower interlayer insulation layers <NUM> and <NUM>, which are exposed by the first opening <NUM>, on the side surface of the upper interlayer insulation layer <NUM> exposed by the second opening <NUM>, and on the upper surface of the second lower interlayer insulation layer <NUM>, and therefore, is formed in a stepped shape. At least one moisture-blocking hole (not illustrated) may be formed in the first and second planarization layers <NUM> and <NUM> in the bending area BA. The moisture-blocking hole is formed in at least one of a position between the signal links <NUM> or a position above the signal links <NUM>. The moisture-blocking hole prevents moisture from the outside from being introduced into the active area AA through at least one of the first or second planarization layer <NUM> or <NUM>, which is disposed on the signal links <NUM>.

The signal links <NUM> are disposed on the substrate <NUM>, which is exposed by the first opening <NUM>, in the bending area BA, and at least one of the first or second planarization layer <NUM> or <NUM> is disposed on the signal links <NUM>. Thereby, the multilayered buffer layer <NUM>, the lower buffer layer <NUM>, the lower gate insulation layer <NUM>, the first and second lower interlayer insulation layers <NUM> and <NUM>, and the upper interlayer insulation layer <NUM> are removed through the first and second openings <NUM> and <NUM> in the bending area BA. That is, when a plurality of inorganic insulation layers <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM>, which cause cracks, are removed from the bending area BA, the substrate <NUM> may be easily bent without generation of cracks. The signal links <NUM>, as illustrated in <FIG>, may be disposed on the multilayered buffer layer <NUM>. Here, when the multilayered buffer layer <NUM>, disposed between the signal links <NUM>, is removed so as to secure easy bending without generation of cracks, a trench <NUM> is formed between the signal links <NUM> so as to expose the substrate <NUM>. An inspection line (not illustrated), which is used during an inspection process, is formed to have the same structure as one of the signal links <NUM> illustrated in <FIG>.

The first opening <NUM> is formed in the bending area by removing the organic insulation layers disposed below the upper buffer layer <NUM>, i.e. the multilayered buffer layer <NUM>, the lower buffer layer <NUM>, the lower gate insulation layer <NUM>, and the first and second lower interlayer insulation layers <NUM> and <NUM>. Thereby, since the depth of the first opening <NUM> of the present disclosure is smaller than that in a comparative example in which the first opening is formed by removing the inorganic insulation layers disposed below the first planarization layer <NUM>, the side surfaces of the inorganic insulation layers <NUM>, <NUM>, <NUM>, <NUM> and <NUM>, which are exposed by the first opening <NUM>, have a gentle inclination angle. Thereby, the step coverage of the signal links <NUM> formed on the side surfaces of the inorganic insulation layers <NUM>, <NUM>, <NUM>, <NUM> and <NUM>, which are exposed by the first opening <NUM>, as well as inspection lines (not illustrated) disposed in the non-active area NA is improved. Accordingly, it is possible to prevent the residue or open defects of the signal links <NUM> and the inspection lines when the signal links <NUM> and the inspection lines are formed on the side surfaces of the inorganic insulation layers <NUM>, <NUM>, <NUM>, <NUM> and <NUM> in the bending area BA.

<FIG> are cross-sectional views for explaining a method of manufacturing the organic light-emitting display device illustrated in <FIG>.

Referring to <FIG>, the multilayered buffer layer <NUM>, the lower buffer layer <NUM>, and the polycrystalline semiconductor layer <NUM> are sequentially formed on the substrate <NUM>.

Specifically, the multilayered buffer layer <NUM> is formed on the substrate <NUM> by alternately stacking SiOx and SiNx at least one time. Subsequently, the lower buffer layer <NUM> is formed by depositing SiOx or SiNx over the entire surface of the multilayered buffer layer <NUM>. Subsequently, a thin amorphous silicon layer is formed on the substrate <NUM> having the lower buffer layer <NUM> formed thereon by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), for example. Subsequently, a thin polycrystalline silicon layer is formed by crystallizing the thin amorphous silicon layer. Subsequently, the polycrystalline semiconductor layer <NUM> is formed by patterning the thin polycrystalline silicon layer through a photolithography process and an etching process using the thin polycrystalline silicon layer as a first mask.

Referring to <FIG>, the lower gate insulation layer <NUM> is formed on the substrate <NUM> having the polycrystalline semiconductor layer <NUM> formed thereon, and the first gate electrode <NUM> and the lower storage electrode <NUM> are formed on the gate insulation layer <NUM>.

Specifically, the lower gate insulation layer <NUM> is formed by depositing an inorganic insulation material such as SiOx or SiNx over the entire surface of the substrate <NUM> having the polycrystalline semiconductor layer <NUM> formed thereon. Subsequently, after a first conductive layer is deposited over the entire surface of the lower gate insulation layer <NUM>, the first conductive layer is patterned through a photolithography process and an etching process using a second mask, so that the first gate electrode <NUM> and the lower storage electrode <NUM> are formed. Subsequently, when the polycrystalline semiconductor layer <NUM> is doped with a dopant through a doping process using the first gate electrode <NUM> as a mask, source and drain areas are formed so as not to overlap the first gate electrode <NUM>, and a channel area is formed so as to overlap the first gate electrode <NUM>.

Referring to <FIG>, at least one first lower interlayer insulation layer <NUM> is formed on the substrate <NUM> having the first gate electrode <NUM> and the lower storage electrode <NUM> formed thereon, and the upper storage electrode <NUM> and the first high-potential supply line 172a are formed on the first lower interlayer insulation layer <NUM>.

Specifically, the first lower interlayer insulation layer <NUM> is formed by depositing an inorganic insulation material such as SiOx or SiNx over the entire surface of the substrate <NUM> having the first gate electrode <NUM> and the lower storage electrode <NUM> formed thereon. Subsequently, after a second conductive layer is deposited over the entire surface of the first lower interlayer insulation layer <NUM>, the second conductive layer is patterned through a photolithography process and an etching process using a third mask, so that the upper storage electrode <NUM> and the first high-potential supply line 172a are formed.

Referring to <FIG>, at least one second lower interlayer insulation layer <NUM> is formed on the substrate <NUM> having the upper storage electrode <NUM> and the first high-potential supply line 172a formed thereon, and the first source and first drain contact holes <NUM> and 160D, the storage contact hole <NUM>, the second line contact hole <NUM>, and the first opening <NUM> are formed.

Specifically, the second lower interlayer insulation layer <NUM> is formed by depositing an inorganic insulation material such as SiOx or SiNx over the entire surface of the substrate <NUM> having the upper storage electrode <NUM> and the first high-potential supply line 172a formed thereon. Subsequently, the multilayered buffer layer <NUM>, the lower buffer layer <NUM>, the lower gate insulation layer <NUM>, the first lower interlayer insulation layer <NUM>, and the second lower interlayer insulation layer <NUM> are selectively patterned through a photolithography process and an etching process using a fourth mask. Thereby, the first source and first drain contact holes <NUM> and 160D, the storage contact hole <NUM>, and the second line contact hole <NUM> are formed, and the first opening <NUM> is formed in the bending area BA. At this time, the first source and first drain contact holes <NUM> and 160D are formed so as to penetrate the lower gate insulation layer <NUM>, the first lower interlayer insulation layer <NUM>, and the second lower interlayer insulation layer <NUM>, and the storage contact hole <NUM> and the second line contact hole <NUM> are formed so as to penetrate the second lower interlayer insulation layer <NUM>. The first opening <NUM> is formed so as to penetrate the multilayered buffer layer <NUM>, the lower buffer layer <NUM>, the lower gate insulation layer <NUM>, the first lower interlayer insulation layer <NUM>, and the second lower interlayer insulation layer <NUM>.

Referring to <FIG>, the first and second source electrodes <NUM> and <NUM>, the first and second drain electrodes <NUM> and <NUM>, the storage supply line <NUM>, and the second high-potential supply line 172b are formed on the substrate <NUM> having therein the first source and first drain contact holes <NUM> and 160D, the storage contact hole <NUM>, the second line contact hole <NUM>, and the first opening <NUM>.

Specifically, a third conductive layer is deposited using Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof over the entire surface of the substrate <NUM> having therein the first source and first drain contact holes <NUM> and 160D, the storage contact hole <NUM>, the second line contact hole <NUM>, and the first opening <NUM>. Subsequently, when the third conductive layer is patterned through a photolithography process and an etching process using a fifth mask, the first and second source electrodes <NUM> and <NUM>, the first and second drain electrodes <NUM> and <NUM>, the storage supply line <NUM>, and the second high-potential supply line 172b are formed.

Referring to <FIG>, the upper buffer layer <NUM> having therein the second source and second drain contact holes <NUM> and 110D is formed on the substrate <NUM> having the first and second source electrodes <NUM> and <NUM>, the first and second drain electrodes <NUM> and <NUM>, the storage supply line <NUM>, and the second high-potential supply line 172b formed thereon.

Specifically, the upper buffer layer <NUM> is formed by depositing an inorganic insulation material such as SiNx or SiOx over the entire surface of the substrate <NUM> having the first and second source electrodes <NUM> and <NUM>, the first and second drain electrodes <NUM> and <NUM>, the storage supply line <NUM>, and the second high-potential supply line 172b formed thereon. Subsequently, when the upper buffer layer <NUM> is patterned through a photolithography process and an etching process using a sixth mask, the second source and second drain contact holes <NUM> and 110D are formed.

Referring to <FIG>, the oxide semiconductor layer <NUM> is formed on the substrate <NUM> having the upper buffer layer <NUM> formed thereon.

Specifically, after the oxide semiconductor layer <NUM> is deposited over the entire surface of the substrate <NUM> having the upper buffer layer <NUM>, which includes the second source and second drain contact holes <NUM> and 110D, formed thereon, the oxide semiconductor layer <NUM> is patterned through a photolithography process and an etching process using a seventh mask, so that the oxide semiconductor layer <NUM> is completely formed.

Referring to <FIG>, the upper gate insulation pattern <NUM>, the second gate electrode <NUM>, and the first low-potential supply line 162a are formed on the substrate <NUM> having the oxide semiconductor layer <NUM> formed thereon.

Specifically, an upper gate insulation layer is formed on the substrate <NUM> having the oxide semiconductor layer <NUM> formed thereon, and a fourth conductive layer is formed by deposition such as sputtering. The upper gate insulation layer is formed using an inorganic insulation material such as SiOx or SiNx. The fourth conductive layer may be formed in a single layer using a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof, or may be formed in multiple layers using the same. Subsequently, the fourth conductive layer and the upper gate insulation layer are patterned at the same time through a photolithography process and an etching process using an eighth mask, so that each of the second gate electrode <NUM> and the first low-potential supply line 162a and the upper gate insulation pattern <NUM> thereunder are formed so as to have the same pattern. At this time, when the upper gate insulation layer is subjected to dry etching, the oxide semiconductor layer <NUM>, which does not overlap the second gate electrode <NUM>, is exposed to plasma, and oxygen in the oxide semiconductor layer <NUM> exposed to plasma is removed via reaction with plasma gas. Thereby, the oxide semiconductor layer <NUM>, which does not overlap the second gate electrode <NUM>, becomes a conductor, and is formed into source and drain areas.

Referring to <FIG>, the upper interlayer insulation layer <NUM> having therein the second opening <NUM>, the first pixel contact hole <NUM>, and the first line contact hole <NUM> is formed on the substrate <NUM> having the upper gate insulation pattern <NUM>, the second gate electrode <NUM>, and the first low-potential supply line 162a formed thereon.

Specifically, the upper interlayer insulation layer <NUM> is formed by depositing an inorganic insulation material such as SiOx or SiNx over the entire surface of the substrate <NUM> having the upper gate insulation pattern <NUM>, the second gate electrode <NUM> and the first low-potential supply line 162a formed thereon. Subsequently, the upper interlayer insulation layer <NUM> is patterned through a photolithography process and an etching process using a ninth mask, so that the first pixel contact hole <NUM>, the first line contact hole <NUM>, and the second opening <NUM> are formed. At this time, the first pixel contact hole <NUM> is formed so as to penetrate the upper interlayer insulation layer <NUM>, thereby exposing the source area of the oxide semiconductor layer <NUM>. The first line contact hole <NUM> is formed so as to penetrate the upper interlayer insulation layer <NUM>, thereby exposing the first low-potential supply line 162a. The second opening <NUM> exposes the substrate <NUM> in the bezel area BA when the upper interlayer insulation layer <NUM> is removed from the bezel area BA.

Referring to <FIG>, the first planarization layer <NUM> is formed on the substrate <NUM> having the upper interlayer insulation layer <NUM> formed thereon.

Specifically, when an organic insulation material such as an acryl-based resin is deposited over the entire surface of the substrate <NUM> having the upper interlayer insulation layer <NUM> formed thereon, the first planarization layer <NUM> is formed. Subsequently, the first planarization layer <NUM> is patterned through a photolithography process using a tenth mask, so that the first pixel contact hole <NUM> and the first line contact hole <NUM> are formed so as to penetrate the first planarization layer <NUM>.

Referring to <FIG>, the pixel connection electrode <NUM>, the second low-potential supply line 162b, and the signal link <NUM> are formed on the substrate <NUM> having the first planarization layer <NUM> formed thereon.

Specifically, a fifth conductive layer is deposited using Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof over the entire surface of the substrate <NUM> having the first planarization layer <NUM> formed thereon. Subsequently, the fifth conductive layer is patterned through a photolithography process and an etching process using an eleventh mask, the pixel connection electrode <NUM>, the second low-potential supply line 162b, and the signal link <NUM> are formed.

Referring to <FIG>, the second planarization layer <NUM> having therein the second pixel contact hole <NUM> is formed on the substrate <NUM> having the pixel connection electrode <NUM>, the second low-potential supply line 162b, and the signal link <NUM> formed thereon.

Specifically, the second planarization layer <NUM> is formed by depositing an organic insulation material such as an acryl-based resin over the entire surface of the substrate <NUM> having the pixel connection electrode <NUM>, the second low-potential supply line 162b, and the signal link <NUM> formed thereon. Subsequently, the second planarization layer <NUM> is patterned through a photolithography process using a twelfth mask, the second pixel contact hole <NUM> is formed.

Referring to <FIG>, the anode electrode <NUM> is formed on the substrate <NUM> having the second planarization layer <NUM>, which includes the second pixel contact hole <NUM>, formed therein.

Specifically, a sixth conductive layer is deposited over the entire surface of the substrate <NUM> having the second planarization layer <NUM>, in which the second pixel contact hole <NUM> is formed, formed thereon. The sixth conductive layer is formed using a transparent conductive layer and an opaque conductive layer. Subsequently, the sixth conductive layer is patterned through a photolithography process and an etching process using a thirteenth mask, so that the anode electrode <NUM> is formed.

Referring to <FIG>, the bank <NUM>, the organic emission stack <NUM>, and the cathode electrode <NUM> are sequentially formed on the substrate <NUM> having the anode electrode <NUM> formed thereon.

Specifically, after a bank photosensitive layer is applied to the entire surface of the substrate <NUM> having the anode electrode <NUM> formed thereon, the bank photosensitive layer is patterned through a photolithography process using a fourteenth mask, so that the bank <NUM> is formed. Subsequently, the emission stack <NUM> and the cathode electrode <NUM> are sequentially formed in the active area AA, excluding the non-active area NA, through a deposition process using a shadow mask.

As described above, in the present disclosure, the first opening <NUM> in the bending area BA and the first source and first drain contact holes <NUM> and 160D are formed through the same single mask process, the second opening <NUM> in the bending area BA and the second source and second drain contact holes <NUM> and 110D are formed through the same single mask process, and the first source and first drain electrodes <NUM> and <NUM> and the second source and second drain electrodes <NUM> and <NUM> are formed through the same single mask process, whereby it is possible to reduce the number of mask processes by at least three compared to the related art. Thereby, the organic light-emitting display device according to the present disclosure may simplify the structure and the manufacturing process thereof as a result of reducing the number of mask processes compared to the related art, which may improve productivity.

As is apparent from the above description, according to the present disclosure, a second thin-film transistor having an oxide semiconductor layer is used as a driving transistor of each subpixel and a first thin-film transistor having a polycrystalline semiconductor layer is used as a switching element of each subpixel, which may reduce power consumption. In addition, according to the present disclosure, since an opening in a bending area and a plurality of contact holes in an active area are formed through the same mask process, a signal link in the bending area is disposed on a substrate. Thereby, the present disclosure may simplify the structure of a display device and the manufacturing process thereof, which may improve productivity.

Claim 1:
A display device comprising:
a substrate (<NUM>) comprising an active area (AA) and a bending area (BA);
a first thin-film transistor (<NUM>) disposed in the active area and comprising a first semiconductor layer (<NUM>);
a second thin-film transistor (<NUM>) disposed in the active area and comprising a second semiconductor layer (<NUM>);
a plurality of contact holes (<NUM>, 160D, <NUM>, 110D, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) formed in at least one inorganic insulation layer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) disposed in the active area;
a first opening (<NUM>) and a second opening (<NUM>) in the at least one inorganic insulation layer and located in the bending area, the first opening having a same or greater depth (d1) as at least one of a first source contact hole (<NUM>) or a first drain contact hole (160D) of the plurality of contact holes and exposing a respective side surface of each of a multilayered buffer layer (<NUM>), a lower buffer layer (<NUM>), a lower gate insulation layer (<NUM>) and first and second lower interlayer insulation layers (<NUM>, <NUM>) of the at least one inorganic insulation layer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), the second opening exposing a side surface of an upper interlayer insulation layer (<NUM>) of the at least one inorganic insulation layer and having a second depth (d2) smaller than the first depth and the same as a first pixel contact hole (<NUM>), of the plurality of contact holes, formed in the upper interlayer insulation layer;
a signal link (LK, <NUM>) connected to a signal line, the signal line being disposed in the active area, the signal link being disposed in the bending area; and
a first planarization layer (<NUM>, <NUM>) formed of an organic insulation material in the bending area and contacting the respective side surface of each of the multilayered buffer layer, the lower buffer layer, the lower gate insulation layer, the first and second lower interlayer insulation layers and the upper interlayer insulation layer.