Patent Description:
A display apparatus is an apparatus for visually displaying data. Such a display apparatus includes a substrate partitioned into a display area and a non-display area. A plurality of pixels are disposed on the substrate in the display area, and a plurality of pads and the like are disposed on the substrate in the non-display area. A flexible film (COF Film) or the like on which a driving circuit or the like is mounted is coupled to the plurality of pads to transmit a driving signal to the pixels.

The flexible film may include a plurality of leads coupled to the plurality of pads, and each lead may be bonded to pads separated from each other. The bonding may be performed by an ultrasonic bonding process.

However, when an adhesion portion attached to the pad of the flexible film is not formed to have a sufficient area, adhesion between the flexible film and the non-display area on which the pad is disposed may be weak.

<CIT> discloses a display device that includes: a substrate including a display area positioned on a first surface and displaying an image and a peripheral area positioned around the display area; a first pad portion disposed on a second surface of the substrate as a surface opposite to the first surface of the substrate; a plurality of through-holes disposed on the peripheral area and penetrating the substrate; a plurality of connection wires disposed on the peripheral area and connecting the display area and the first pad portion through the plurality of through-holes; and a printed circuit board including a second pad portion coupled with the first pad portion.

<CIT> discloses a flexible display device that comprises a substrate having a flat portion and a curved portion, wherein a pixel array is provided in the flat portion and a pad portion connected to the pixel array is provided in the curved portion; and an encapsulation layer provided on the substrate to cover the pixel array, wherein the encapsulation layer comprises a terminal portion; an Integrated Circuit (IC) portion having at least one driving IC; and a lead portion having leads which connect the terminal portion and the driving IC portion, and wherein the curved portion of the substrate is bent so that thepad portion and the terminal portion are in contact with each other.

<CIT> discloses a display apparatus may include a display panel and a plurality of flexible printed circuit boards connected to the display panel. The display panel may include first regions arranged in a first direction and may include a plurality of first alignment marks, which are respectively provided on the first regions and are arranged in the first direction. Each of the flexible printed circuit boards may include a plurality of second alignment marks arranged in the first direction and overlapped with the first alignment marks, an insulating layer spaced apart from the second alignment marks in a second direction crossing the first direction, and a plurality of supplementary alignment marks spaced apart from the second alignment marks by a first distance in the second direction, the supplementary alignment marks being openings defined in the insulating layer.

<CIT> discloses a built-in camera module having a circuit board capable of simplifying a circuit board bonding process of the built-in camera module and a circuit board used therein.

An object of the present invention is directed to providing a display apparatus as set out in claim <NUM>. Additional features are set out in claims <NUM> to <NUM>.

Specific matters of other embodiments are included in the detailed description and the drawings.

According to exemplary embodiments of the present invention, it is possible to provide a display apparatus that can increase adhesion between a display panel and a flexible printed circuit film.

Effects according to the present invention are not limited by the contents illustrated above, and more various effects are included in the present specification.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in different forms. That is, the present invention is defined only by the scope of the claims.

When an element or layer are referred to as "above" or "on" another element or layer, this includes not only directly on another element or layer but also another layer or element intervening therebetween. On the other hand, when an element is referred to as "directly on" or " directly above," this indicates that there is not another intervening element or layer therebetween.

The same reference numerals are used for the same or similar parts throughout the specification.

<FIG> is a plan layout view of a display apparatus according to an exemplary embodiment, and <FIG> is a plan layout view of first and second circuit boards of <FIG>.

A display apparatus <NUM> is an apparatus for displaying a moving picture or a still image, and the display apparatus may be used as a display screen of various products such as a television, a laptop, a monitor, a billboard, an Internet of Things device, and the like as well as a portable electronic device such as a mobile phone, a smart phone, a tablet PC (personal computer), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an e-book reader, a portable multimedia player (PMP), a navigation device, an ultra-mobile PC (UMPC), and the like.

Referring to <FIG>, the display apparatus <NUM> may include a display panel <NUM> displaying an image, a panel lower sheet <NUM> disposed below the display panel <NUM>, a first circuit board <NUM> connected to the display panel <NUM>, and a second circuit board <NUM> connected to the first circuit board <NUM> and attached to a lower surface of the panel lower sheet <NUM>.

As the display panel <NUM>, for example, an organic light-emitting display panel may be applied. In the following exemplary embodiment, it is illustrated that the organic light-emitting display panel is applied as the display panel <NUM>, but the present invention is not limited thereto, and other types of display panels, such as a liquid crystal display (LCD), a quantum dot organic light-emitting display panel (QD-OLED), a quantum dot liquid crystal display (QD-LCD), a quantum nano light-emitting display panel (QNED), and a micro LED, may be applied.

The display panel <NUM> includes a display area DA for displaying an image and a non-display area NA disposed around the display area DA. The display area DA may have a rectangular shape with right-angled corners on a plane or a rectangular shape with rounded corners. The display area DA may have a short side and a long side. The short side of the display area DA may be a side extending in a first direction DR1. The long side of the display area DA may be a side extending in a second direction DR2. However, a planar shape of the display area DA is not limited to the rectangular shape, and may be a circular shape, an elliptical shape, or other various shapes. The non-display area NA may be disposed adjacent to both short sides and both long sides of the display area DA. In this case, the non-display area NA may surround all sides of the display area DA to form an edge of the display area DA. However, the present invention is not limited thereto, and the non-display area NA may be disposed adjacent to only both short sides or both long sides of the display area DA.

The non-display area NA may further include a panel pad area P_PA on one side of the display panel <NUM> in the second direction DR2. The display panel <NUM> may include at least one panel pad terminal (see 'P_PE' in <FIG>) and a dummy pad terminal (see 'D_PE' in <FIG>). The panel pad terminal P_PE and the dummy pad terminal D_PE may be disposed in the panel pad area P_PA.

The first circuit board <NUM> may be disposed on an upper surface of the panel pad area P_PA of the display panel <NUM>. The first circuit board <NUM> may be connected to the upper surface of the panel pad area P_PA.

The first circuit board <NUM> may include a first circuit area CA1 attached to the panel pad area P_PA, a second circuit area CA2 to be attached to the second circuit board <NUM> to be described later, and a third circuit area CA3 disposed between the first circuit area CA1 and the second circuit area CA2. The first circuit area CA1 may overlap the panel pad area P_PA in a thickness direction. The second circuit area CA2 may overlap a circuit pad area C_PA of the second circuit board <NUM> to be described later in the thickness direction.

The first circuit board <NUM> may include lead terminals (see 'LE1' and 'LE2' in <FIG>) and a dummy lead terminal (see 'D_LE' in <FIG>). As described later, a lead terminal LE may include a first lead terminal LE1 disposed in the first circuit area CA1 and a second lead terminal LE2 disposed in the second circuit area CA2.

The first circuit board <NUM> may include a data driving integrated circuit <NUM> disposed on one surface of the first circuit board <NUM>. The data driving integrated circuit <NUM> may be implemented as a data driving chip and may be attached to the display panel through the first circuit board <NUM> by applying a chip on film (COF) method. However, the present invention is not limited thereto, and the data driving integrated circuit <NUM> may be attached to a plastic substrate or a glass substrate by a chip on plastic (COP) or chip on glass (COG) method.

The second circuit board <NUM> may be disposed on the second circuit area CA2 of the first circuit board <NUM>. In the drawing, it is illustrated that the second circuit board <NUM> is disposed on the other surface of the first circuit board <NUM>, but the present invention is not limited thereto, and the second circuit board <NUM> may also be disposed on one surface of the first circuit board <NUM>.

The second circuit board <NUM> may include the circuit pad area C_PA attached to the second circuit area CA2 of the first circuit board <NUM>. The second circuit board <NUM> may include circuit pad terminals (not shown) disposed in the circuit pad area C_PA.

Hereinafter, configurations of the display panel <NUM>, the panel lower sheet <NUM>, the first circuit board <NUM>, and the second circuit board <NUM> will be described.

<FIG> is a cross-sectional view taken along a second direction of the display apparatus of <FIG>, and <FIG> is another cross-sectional view of the display apparatus.

<FIG> and <FIG> show cross-sectional shapes of one pixel area and the panel pad area P_PA of <FIG>. Further, <FIG> and <FIG> illustrate the first circuit board <NUM> and the second circuit board <NUM> disposed on the panel pad area P_PA. <FIG> shows a state in which the panel pad terminal P_PE and the first lead terminal LE1 which will be described later are coupled to each other in the panel pad area P_PA. In <FIG>, the description of <FIG> may be applied as it is, except that the dummy pad terminal D_PE and the dummy lead terminal D_LE, which will be described later, are coupled in the panel pad area P_PA.

Referring to <FIG> and <FIG>, the display panel <NUM> may include a base substrate <NUM>, a plurality of conductive layers, a plurality of insulating layers insulating the conductive layers, organic layers EL, and the like.

The base substrate <NUM> is disposed over the display area DA and the non-display area NA. The base substrate <NUM> may function to support various elements disposed thereon. In an exemplary embodiment, the base substrate <NUM> may be a rigid substrate including a rigid material such as soft glass, quartz, and the like. However, the present invention is not limited thereto, and the base substrate <NUM> may be a semi-flexible substrate or a flexible substrate including some flexible materials. In this case, the base substrate <NUM> may include polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cycloolefin polymer (COP), or the like.

A buffer layer <NUM> may be disposed on the base substrate <NUM>. The buffer layer <NUM> may prevent penetration of moisture and oxygen from the outside via the base substrate <NUM>. In addition, the buffer layer <NUM> may planarize a surface of the base substrate <NUM>. As one exemplary embodiment, the buffer layer <NUM> may include any one of a silicon nitride (SiNx) film, a silicon oxide (SiO<NUM>) film, and a silicon oxynitride (SiOxNy) film.

A semiconductor layer <NUM> may be disposed on the buffer layer <NUM>. The semiconductor layer <NUM> forms a channel of a thin film transistor. The semiconductor layer <NUM> may be disposed in each pixel of the display area DA and, in some cases, may also be disposed in the non-display area NA. The semiconductor layer <NUM> may include a source/drain region and an active region. The semiconductor layer <NUM> may include polycrystalline silicon.

A first insulating layer <NUM> may be disposed on the semiconductor layer <NUM>. The first insulating layer <NUM> may be disposed over the entire surface of the base substrate <NUM>. The first insulating layer <NUM> may be a gate insulating film having a gate insulating function. The first insulating layer <NUM> may include a silicon compound, a metal oxide, or the like. For example, the first insulating layer <NUM> may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These may be used alone or in combination with each other.

A first conductive layer <NUM> may be disposed on the first insulating layer <NUM>. In an exemplary embodiment, the first conductive layer <NUM> may include a gate electrode <NUM> of a thin film transistor TFT, a first electrode <NUM> of a storage capacitor Cst, and a first pad electrode <NUM>. The first conductive layer <NUM> may include a metal material. The first conductive layer <NUM> may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer <NUM> may be a single film or a stacked film made of the above-described materials.

A second insulating layer <NUM> may be disposed on the first conductive layer <NUM>. The second insulating layer <NUM> may insulate the first conductive layer <NUM> and a second conductive layer <NUM>. The second insulating layer <NUM> may be selected from the illustrated materials of the first insulating layer <NUM>.

The second conductive layer <NUM> may be disposed on the second insulating layer <NUM>. The second conductive layer <NUM> may include a second electrode <NUM> of the storage capacitor Cst. A material of the second conductive layer <NUM> may be selected from the illustrated materials of the first conductive layer <NUM> described above. The first electrode <NUM> of the storage capacitor Cst and the second electrode <NUM> of the storage capacitor Cst may form a capacitor through the second insulating layer <NUM>.

A third insulating layer <NUM> may be disposed on the second conductive layer <NUM>. The third insulating layer <NUM> may include the illustrated material of the first insulating layer <NUM> described above.

A third conductive layer <NUM> may be disposed on the third insulating layer <NUM>. The third conductive layer <NUM> may include a source electrode <NUM>, a drain electrode <NUM>, a power supply voltage electrode <NUM>, and a second pad electrode <NUM>. The third conductive layer <NUM> may include the illustrated material of the first conductive layer <NUM> described above. The third conductive layer <NUM> may be a single film made of the above-described materials. The present invention is not limited thereto, and the third conductive layer <NUM> may be a stacked film. For example, the third conductive layer <NUM> may be formed in a stacked structure of Ti/Al /Ti, Mo/Al/Mo, Mo/AlGe/Mo, Ti/Cu, or the like.

The second pad electrode <NUM> may be disposed on an upper surface of the first pad electrode <NUM> corresponding in the thickness direction. The first pad electrode <NUM> and the second pad electrode <NUM> overlapping in the thickness direction may constitute the panel pad terminal P_PE and the dummy pad terminal D_PE. A width of the second pad electrode <NUM> in the second direction DR2 may be smaller than a width of the first pad electrode <NUM> in the second direction DR2. At least one side surface of the first pad electrode <NUM> may protrude outward further than at least one side surface of the second pad electrode <NUM>. The panel pad terminal P_PE and the dummy pad terminal D_PE will be described later.

Meanwhile, as described above, the third insulating layer <NUM> is disposed on the second conductive layer <NUM>, and structures disposed on the second conductive layer <NUM> including the third insulating layer <NUM> in the panel pad area P_PA may be omitted or removed. Accordingly, the omitted or removed structures may expose the panel pad terminal P_PE and the dummy pad terminal D_PE disposed in the panel pad area P_PA.

As described later, the first lead terminal LE1 may be coupled to the exposed panel pad terminal P_PE and the dummy lead terminal D_LE may be coupled to the exposed dummy pad terminal D_PE. In an exemplary embodiment, the first lead terminal LE1 may be directly coupled to the panel pad terminal P_PE by ultrasonic bonding without any configuration or layer between the first lead terminal LE1 and the panel pad terminal P_PE. The dummy lead terminal D_LE may also be directly coupled to the dummy pad terminal D_PE by the ultrasonic bonding without any configuration or layer between the dummy pad terminal D_PE and the dummy lead terminal D_LE.

A first via layer <NUM> may be disposed on the third conductive layer <NUM>. The first via layer <NUM> may contain an organic insulating material such as acrylic resin (polyacrylic resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

A fourth conductive layer <NUM> may be disposed on the first via layer <NUM>. The fourth conductive layer <NUM> may include power supply voltage lines <NUM> and <NUM> and a connection electrode <NUM>. The power supply voltage line <NUM> may be electrically connected to the source electrode <NUM> of the thin film transistor TFT via a contact hole passing through the first via layer <NUM>. The connection electrode <NUM> may be electrically connected to the drain electrode <NUM> of the thin film transistor TFT via a contact hole passing through the first via layer <NUM>. The power supply voltage line <NUM> may be electrically connected to the power supply voltage electrode <NUM> via a contact hole passing through the first via layer <NUM>.

The fourth conductive layer <NUM> may contain at least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), and molybdenum (Mo). The fourth conductive layer <NUM> may be a single film, but the present invention is not limited thereto, and the fourth conductive layer <NUM> may be formed as a multilayer film. For example, the fourth conductive layer <NUM> may be formed in a stacked structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Ti/Cu, or the like.

A second via layer <NUM> is disposed on the fourth conductive layer <NUM>. The second via layer <NUM> may contain the illustrated material of the first via layer <NUM> described above. The second via layer <NUM> may contain an organic insulating material such as acrylic resin (polyacrylic resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

An anode ANO is disposed on the second via layer <NUM>. The anode ANO may be electrically connected to the connection electrode <NUM> via a contact hole passing through the second via layer <NUM>.

A pixel defining layer PDL may be disposed on the anode ANO. The pixel defining layer PDL may include an opening exposing the anode ANO. The pixel defining layer PDL may be made of an organic insulating material or an inorganic insulating material. In an exemplary embodiment, the pixel defining layer PDL may contain a material such as a photoresist, polyimide resin, acrylic resin (polyacrylic resin), a silicone compound, polyacrylic resin, or the like.

The organic layer EL may be disposed on an upper surface of the anode ANO and in the opening of the pixel defining layer PDL. A cathode CAT is disposed on the organic layer EL and the pixel defining layer PDL. The cathode CAT may be a common electrode disposed over a plurality of pixels.

A thin film encapsulation layer <NUM> is disposed on the cathode CAT. The thin film encapsulation layer <NUM> may cover an organic light-emitting diode OLED. The thin film encapsulation layer <NUM> may be a stacked film in which an inorganic film and an organic film are alternately stacked. For example, the thin film encapsulation layer <NUM> may include a first inorganic film <NUM>, an organic film <NUM>, and a second inorganic film <NUM> that are sequentially stacked.

The panel pad terminal P_PE and the dummy pad terminal D_PE may be disposed in the panel pad area P_PA described above. The panel pad terminal P_PE may have a structure in which the second pad electrode <NUM> is stacked on the first pad electrode <NUM>.

In addition, the panel pad terminal P_PE may be formed of one first pad electrode <NUM> and one second pad electrode <NUM>. A planar shape of the panel pad electrode P_PE may be determined according to a profile protruding outward from a planar view point.

In an exemplary embodiment, the first pad electrode <NUM> and the second pad electrode <NUM> have a shape in which all side surfaces are tapered, and the side surfaces of the second pad electrode <NUM> and the first pad electrode <NUM> may be aligned. In this case, a lower surface of the first pad electrode <NUM> may protrude outward from a lower surface of the second pad electrode <NUM> so that the planar shape of the panel pad terminal P_PE may be determined by an outer profile of the first pad electrode <NUM>.

However, the present invention is not limited thereto, and the side surfaces of the first pad electrode <NUM> and the second pad electrode <NUM> may not be the tapered shape, and the side surface of the second pad electrode <NUM> may be positioned inside the side surface of the first pad electrode <NUM>, or the side surface of the second pad electrode <NUM> may be positioned to protrude outward from the side surface of the first pad electrode <NUM>. In this case, since the planar shape of the panel pad electrode P_PE is determined according to the profile protruding outward in the plan view, the planar shape may also be variously modified.

However, the present invention is not limited thereto, and the stacked structure and the shape of the panel pad terminal P_PE may be modified differently. For example, the first pad electrode <NUM> may include a plurality of patterns, and the second pad electrode <NUM> disposed on the first pad electrode <NUM> may have surface irregularities by reflecting a step difference of the pattern.

As another example, the second insulating layer <NUM> may be extended and disposed between the first pad electrode <NUM> and the second pad electrode <NUM>. The second insulating layer <NUM> may include a plurality of contact holes. In other words, the second insulating layer <NUM> may be regarded as including a plurality of insulating patterns. Even in this case, the second pad electrode <NUM> disposed on the second insulating layer <NUM> may have surface irregularities by reflecting a surface level difference caused by the insulating pattern of the second insulating layer.

As still another example, a third pad electrode may be further included between the first pad electrode <NUM> and the second pad electrode <NUM>. The third pad electrode may be included in the second conductive layer <NUM>.

In addition, the first pad electrode <NUM> may be composed of the second conductive layer <NUM>, and the second pad electrode <NUM> may be composed of the fourth conductive layer <NUM>.

As shown in <FIG>, the dummy pad terminal D_PE may also have the same stacked structure as the panel pad terminal P_PE, but the present invention is not limited thereto. The dummy pad electrode D_PE may be formed only with the first pad electrode <NUM>, and may be formed only with the second pad electrode <NUM>.

As described above, the first circuit board <NUM> may be disposed on the panel pad area P_PA of the display panel <NUM>. One end of the first circuit board <NUM> is attached to the panel pad area P_PA and is bent to surround one side surface of the base substrate <NUM> so that the other end of the first circuit board <NUM> may be disposed to overlap the lower surface of the panel lower sheet <NUM>. The first circuit board <NUM> may include a base film <NUM> and various elements disposed on one surface of the base film <NUM>.

The other end of the first circuit board <NUM> may be connected to the second circuit board <NUM>. The second circuit board <NUM> may be attached to the lower surface of the panel lower sheet <NUM>.

<FIG> and <FIG> are referenced to describe the panel pad area P_PA and the circuit area CA.

<FIG> is a plan layout view of first and second circuit boards of <FIG>, and <FIG> is a cross-sectional view taken along line V-V' of <FIG>.

Referring to <FIG> and <FIG>, the panel pad terminal P_PE and the dummy pad terminal D_PE may be disposed on the panel pad area P_PA. The display panel <NUM> may further include a panel alignment mark P_AM. The panel alignment mark P_AM is disposed in the panel pad area P_PA. The display panel <NUM> may further include a first signal line L1 connecting the panel pad terminal P_PE to the display area DA.

In addition, the first lead terminal LE may be disposed on the first circuit area CA1, and the second lead terminal LE2 may be disposed on the second circuit area CA2. The first circuit board <NUM> may further include a lead alignment mark L_AM. The lead alignment mark L_AM is disposed in the first circuit area CA. The first circuit board <NUM> may further include the data driving integrated circuit <NUM> in the third circuit area CA3. The first circuit board <NUM> may further include a second signal line L2 connecting the first lead terminal LE1 and the data driving integrated circuit <NUM> and a third signal line L3 connecting the terminal P_PE and the second lead terminal LE2 and the data driving integrated circuit <NUM>.

The panel pad terminal P_PE may be disposed in a central portion of the panel pad area P_PA. The panel pad terminal P_PE may be electrically connected to at least one transistor TR (not shown) disposed in the display area DA via the first signal line L1.

The panel pad terminal P_PE may include a long side and a short side. The long side may be a side extending in the second direction DR2, and the short side may be a side extending in the first direction DR1, but the present invention is not limited thereto. The planar shape of the panel pad terminal P_PE may be a rectangular shape, but the present invention is not limited thereto, and the planar shape may be a square shape.

The panel alignment mark P_AM may include a first panel alignment mark P_AM1 and a second panel alignment mark P_AM2 disposed to be spaced apart from each other with the panel pad terminal P_PE therebetween.

The panel alignment mark P_AM may be disposed on both sides of the panel pad terminal P_PE, respectively, and may mark the panel pad terminal P_PE. In addition, the panel alignment mark P_AM may be disposed to overlap the lead alignment mark L_AM in the thickness direction. The panel alignment mark P_AM may align such that the panel pad terminal P_PE and the first lead terminal LE1 correspond to each other in the thickness direction together with the lead alignment mark L_AM.

The panel alignment mark P_AM may have a stacked structure that is the same as or similar to that of the panel pad terminal P_PE. However, the present invention is not limited thereto, and the panel alignment mark P_AM may be formed only with the first pad electrode <NUM> or may be formed only with the second pad electrode <NUM>. In addition, the panel alignment mark P_AM may be made of a conductive material different from that of each of the first pad electrode <NUM> and the second pad electrode <NUM>.

In the drawing, it is illustrated that the panel alignment mark P_AM has a shape including a reference plane extending in the first direction DR1 and a protruding surface protruding from the reference plane in the second direction DR2, but the present invention is not limited thereto, and the panel alignment mark P_AM may have various shapes.

Unlike the panel pad terminal P_PE, the panel alignment mark P_AM is not electrically connected to at least one transistor TR disposed in the display area DA. That is, the panel alignment mark P_AM may be floated.

In the drawing, one first panel alignment mark P_AM1 and one second panel alignment mark P_AM2 are shown, but the present invention is not limited thereto, and the number of each of the first and second panel alignment marks P_AM1 and P_AM2 may be two or more.

The dummy pad terminal D_PE may be disposed adjacent to a long side of the base substrate <NUM> (an edge of the base substrate <NUM>). The dummy pad terminal D_PE may be disposed to be spaced apart from the panel pad terminal P_PE with the panel alignment mark P_AM therebetween.

The dummy pad terminal D_PE may have substantially the same planar shape as the panel pad terminal P_PE described above, but the present invention is not limited thereto.

In the drawing, three first dummy pad terminals D_PE1 and three second dummy pad terminals D_PE2 are shown, but the present invention is not limited thereto, and the number of each of the first and second dummy pad terminals D_PE1 and D_PE2 may be two, or four or more.

Unlike the panel pad terminal P_PE, the dummy pad terminal D_PE is not electrically connected to at least one transistor TR disposed in the display area DA. That is, the dummy pad terminal D_PE is floated.

The first lead terminal LE1 may be disposed in a central portion of the first circuit area CA1. The first lead terminal LE1 may be electrically connected to the data driving integrated circuit <NUM> via the second signal line L2.

The first lead terminal LE1 may include a metal material. The first lead terminal LE1 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first lead terminal LE1 may be a single film or a stacked film made of the above-described materials. In an exemplary embodiment, the materials included in the first lead terminal LE1 may be different from materials included in the panel pad terminal P_PE coupled to the first lead terminal LE1. For example, the first lead terminal LE1 may include silver (Ag), gold (Au), or copper (Cu), and the panel pad terminal P_PE may include Ti/Al/Ti, Mo/Al/Mo, and Mo/AlGe/Mo, or Ti/Cu.

The second lead terminal LE2 may be disposed in a central portion of the second circuit area CA2. The second lead terminal LE2 may be electrically connected to the data driving integrated circuit <NUM> via the third signal line L3.

The second lead terminal LE2 may include the illustrated material as the first lead terminal LE1 described above.

The first and second lead terminals LE1 and LE2 may have substantially the same planar shape as the panel pad terminal P_PE described above. However, planar sizes of the lead terminals LE1 and LE2 may be smaller than the planar size of the panel pad terminal P_PE.

The lead alignment mark L_AM may include first to fourth lead alignment marks L_AM1-L_AM4. The first and second lead alignment marks L_AM1 and L_AM2 may be disposed to be spaced apart from each other with the first lead terminal LE1 therebetween. The third and fourth lead alignment marks L_AM3 and L_AM4 may be disposed to be spaced apart from each other with the second lead terminal LE2 therebetween.

The first and second lead alignment marks L_AM1 and L_AM2 may be disposed on both sides of the first lead terminal LE1, respectively, and may mark the first lead terminal LE1. In addition, the first and second lead alignment marks L_AM1 and L_AM2 may be disposed to overlap the panel alignment mark P_AM in the thickness direction as described above and may align the first lead terminal LE1 to correspond to the panel pad terminal P_PE in the thickness direction.

The third and fourth lead alignment marks L_AM3 and L_AM4 may be disposed on both sides of the second lead terminal LE2, respectively, and may mark the second lead terminal LE2.

The lead alignment mark L_AM may have a stacked structure that is the same as or similar to that of the first lead terminal LE1, and may be made of the same material.

In the drawing, the lead alignment mark L_AM may have the same shape as the panel alignment mark P_AM described above.

However, the present invention is not limited thereto, and the lead alignment mark L_AM may have a shape different from that of the panel alignment mark P_AM. However, even in this case, the lead alignment mark L_AM may have a shape to be aligned with the panel alignment mark P_AM. For example, the lead alignment mark L_AM may have the shape such that the lead alignment mark L_AM is aligned with at least one side of the panel alignment mark P_AM in the thickness direction.

In the drawing, the number of each of the first to fourth lead alignment marks L_AM1 to L_AM4 is shown as one, but the present invention is not limited thereto, and there may be two or more.

Unlike the lead terminal LE, the lead alignment mark L_AM is not electrically connected to the data driving integrated circuit <NUM>. That is, the lead alignment mark L_AM may be floated.

The dummy lead terminal D_LE may be disposed adjacent to a long side of the base substrate <NUM> (an edge of the base substrate <NUM>). The dummy lead terminal D_LE may include a first dummy lead terminal D_LE1 disposed between the first lead alignment mark L_AM1 and one long side of the base substrate <NUM> and a second dummy lead terminal D_LE2 disposed between the second lead alignment mark L_AM2 and the other long side of the base substrate <NUM>. The dummy lead terminal D_LE may be disposed to be spaced apart from the first lead terminal LE1 with the lead alignment mark L_AM therebetween.

The dummy lead terminal D_LE may have substantially the same planar shape as the lead terminal LE described above, but the present invention is not limited thereto.

In the drawing, three first dummy lead terminals D_LE1 and three second dummy lead terminals D_LE2 are shown, but the present invention is not limited thereto, and the number of each of the first and second dummy lead terminals D_LE1 and D_LE2 may be two, or four or more.

Unlike the first lead terminal LE1, the dummy lead terminal D_LE is not electrically connected to the data driving integrated circuit <NUM>. That is, the dummy lead terminal D_LE may be floated.

Referring to <FIG>, as described above, the first lead terminal LE1 may be directly coupled to the panel pad terminals P_PE without any configuration or layer between the panel pad terminals P_PE in a central portion of the first circuit board <NUM>.

The dummy lead terminals D_LE1 and D_LE2 may be directly coupled to the dummy pad terminals D_PE1 and D_PE2 without any configuration or layer with the dummy pad terminals D_PE1 and D_PE2 at an edge portion of the first circuit board <NUM>.

Further, the lead alignment marks L_AM1 and L_AM2 may be directly coupled to the panel alignment marks P_AM1 and P_AM2 without any configuration or layer in a region between the dummy lead terminals D_LE1 and D_LE2 and the first lead terminal LE1.

The panel pad terminal P_PE and the first lead terminal LE1, the dummy lead terminals D_LE1 and D_LE2, and the dummy pad terminals D_PE1 and D_PE2 may be directly coupled by ultrasonic bonding.

Referring again to <FIG>, the ultrasonic bonding may be performed by an ultrasonic apparatus <NUM>.

As shown in <FIG>, the ultrasonic apparatus <NUM> may include a vibration generating unit <NUM>, a vibration unit <NUM> connected to the vibration generating unit <NUM>, a pressing unit <NUM> that amplifies a vibration amplitude of the vibration unit <NUM>, and a vibration transmitting unit <NUM> connected to the vibration unit <NUM>.

The vibration generating unit <NUM> may convert electrical energy into vibration energy. The vibration unit <NUM> may vibrate with the vibration energy converted by the vibration generating unit <NUM>. The vibration unit <NUM> may vibrate while having a constant vibration direction and a predetermined amplitude. The amplitude of the vibration unit <NUM> may be amplified in a direction parallel to the vibration direction by the pressing unit <NUM> connected to the vibration unit <NUM>. The vibration transmitting unit <NUM> may transmit a vibration of the vibration unit <NUM> to an ultrasonic bonding object. A support unit <NUM> may fix upper and lower surfaces of the vibration unit <NUM> to suppress the vibration from moving the vibration unit <NUM> and the vibration transmitting unit <NUM> up and down.

In an exemplary embodiment, the ultrasonic apparatus <NUM> is in contact with the other surface of the first circuit board <NUM> and maintains a constant pressurized state downward so that the vibration transmitting unit <NUM> efficiently transmits the vibration to the first circuit board <NUM>. In this case, as shown in <FIG>, the vibration transmitting unit <NUM> of the ultrasonic apparatus <NUM> may perform the ultrasonic bonding while overlapping the entire area of the first circuit board <NUM> disposed thereunder.

The ultrasonic apparatus <NUM> may vibrate the first lead terminal LE1 in the vibration direction while vibrating in a predetermined vibration direction. However, in this case, the panel pad terminal P_PE may vibrate slightly in the vibration direction due to the vibration transmitted through the first lead terminal LE1, but a vibration amplitude thereof may be insignificant. Therefore, the vibration amplitude of the vibration transmitting unit <NUM> in the vibration direction may be regarded as substantially the same as a distance that the first lead terminal LE1 moves on the panel pad terminal P_PE in the vibration direction. In an exemplary embodiment, the vibration direction may be the second direction DR2. That is, the vibration direction may be a direction in which long sides of the panel pad terminal P_PE and the first lead terminal LE1 extend.

When the first lead terminal LE1 is ultrasonically vibrated on one surface of the panel pad terminal P_PE, a predetermined frictional force is generated at an interface between one surface of the panel pad terminal P_PE and one surface of the first lead terminal LE1, and frictional heat may be generated by the frictional force. When the frictional heat is sufficient to melt a material forming the panel pad terminal P_PE and the first lead terminal LE1, a panel melting region 144b, which is adjacent to the first lead terminal LE1, of the panel pad terminal P_PE and a lead melting region LE1b, which is adjacent to the panel pad terminal P_PE, of the first lead terminal LE1 may be melted. That is, the panel pad terminal P_PE may include a panel non-melting region 144a and the panel melting region 144b. In addition, the first lead terminal L_PE may include a lead non-melting region LE1a and the lead melting region LE1b.

The panel non-melting region 144a may be a region including only a material included in the panel pad terminal P_PE. The lead non-melting region LE1a may be a region including only a material included in the first lead terminal LE1.

The panel melting region 144b may be a region in which the material included in the first lead terminal LE1 is diffused to mix the material of the panel pad terminal P_PE and the material of the first lead terminal LE1, and the lead melting region LE1b may be a region in which the material included in the panel pad terminal P_PE is diffused to mix the material of the first lead terminal LE1 and the material of the panel pad terminal P_PE. For example, when the first lead terminal LE1 includes silver (Ag), gold (Au), or copper (Cu), and the panel pad terminal P_PE includes Ti/Al/Ti, the panel melting region 144b may be a region in which Ti and/or Al of the panel pad terminal P_PE and silver (Ag), gold (Au), or copper (Cu) of the first lead terminal LE1 are mixed. In addition, the lead melting region LE1b may be a region in which silver (Ag), gold (Au), or copper (Cu) of the first lead terminal LE1 and Ti and/or Al of the panel pad terminal P_PE are mixed.

In the panel melting region 144b and the lead melting region LE1b, the panel pad terminal P_PE and the first lead terminal LE1 may be coupled while undergoing solidification.

An interface between the panel pad terminal P_PE and the first lead terminal LE1, that is, an interface between the panel melting region 144b and the lead melting region LE1b may have a non-flat shape.

When the ultrasonic bonding is not particularly related to the panel pad terminal P_PE and the first lead terminal LE1, it may be similarly applied to the dummy pad terminal D_PE and the dummy lead terminal D_LE as well as the panel alignment mark P_AM and the lead alignment mark L_AM.

Referring again to <FIG>, the panel pad terminal P_PE may have a first pad thickness TP1, and the first lead terminal LE1 may have a first lead thickness TL1. In addition, the dummy pad terminal D_PE may have a second pad thickness TP2, and the dummy lead terminal D_LE may have a second lead thickness TL2.

Accordingly, a separation distance from the first insulating layer <NUM> may be maintained to be substantially the same in the central portion and the edge portion of the first circuit board <NUM>. In other words, one surface of the first circuit board <NUM> and the first insulating layer <NUM> may have a first separation distance D1 at the central portion of the first circuit board <NUM>, and one surface of the first circuit board <NUM> and the first insulating layer <NUM> may have a second separation distance D2 at the edge portion.

As described above, the ultrasonic bonding between the first circuit board <NUM> and the panel pad area P_PA of the display panel <NUM> may be performed between the entire first circuit board <NUM> and the panel pad area P_PA overlapping the first circuit board <NUM>. When the ultrasonic bonding is performed, the ultrasonic apparatus <NUM> vibrates the first circuit board <NUM> in a long side direction while pressing the entire first circuit board <NUM>.

However, the first circuit board <NUM> may sag in a downward third direction DR3 from a region in which the pad terminal PE and the lead terminal LE are not disposed and do not correspond in the thickness direction (in particular, an edge portion of the panel pad area P_PA). Since the ultrasonic apparatus <NUM> presses downward, when the first circuit board <NUM> sags downward from the region, corners of a surface of a region around the boundary may be collapsed or deformed by excessive force and/or stress due to the pressing at the boundary between the central portion and the edge portion of the first circuit board <NUM>. The dummy pad electrode D_PE and the dummy lead electrode D_LE according to an exemplary embodiment may be disposed to overlap in an edge region of the first circuit board <NUM> and may be formed so that the sum of the thicknesses thereof is the same as the sum of the thicknesses of the panel pad electrode P_PE and the first lead electrode LE1 to flatten the first circuit board <NUM> as a whole. Accordingly, it is possible to prevent or at least alleviate a phenomenon in which excessive force and/or stress is concentrated in a specific region by a sagging phenomenon of a specific region of the first circuit board <NUM> during ultrasonic bonding.

In addition, when the dummy pad electrode D_PE and the dummy lead electrode D_LE are disposed to overlap each other at the edge portion of the first circuit board <NUM> and ultrasonic bonding is performed, a bonding force between the first circuit board <NUM> and the panel pad area P_PA may be increased as a whole to improve the bonding reliability.

Hereinafter, a display apparatus according to another exemplary embodiment will be described. The same configurations as those of the embodiment already described will be referred to as the same reference numerals in the following embodiment, and description thereof will be omitted or simplified.

<FIG> is a plan view showing a state in which one panel pad terminal and a lead terminal according to another exemplary embodiment are bonded.

<FIG> is a cross-sectional view taken along line VII-VII' of <FIG>.

In another exemplary embodiment according to <FIG> and <FIG>, when ultrasonically bonding a first lead terminal LE1 and a panel pad terminal P_PE, and a dummy lead terminal D_LE and a dummy pad terminal D_PE, the pad terminals P_PE and D_PE may have a region BR bonded to the lead terminals LE1 and D_LE and a region NBR not bonded thereto. In addition, it is illustrated that the dummy pad terminal D_PE may include a region BR bonded to the dummy lead terminal D_LE and a region BR not bonded thereto. Hereinafter, the dummy lead terminal D_LE and the dummy pad terminal D_PE will be mainly described, but the same content may be applied to the relationship between the first lead terminal LE1 and the panel pad terminal P_PE.

In detail, when ultrasonically bonding the dummy lead terminal D_LE and the dummy pad terminal D_PE, the pad terminals P_PE and D_PE may have the region BR bonded to the lead terminals LE1 and D_LE and the region NBR not bonded thereto.

The bonding region BR and the non-bonding region NBR may be a region of one surface of the dummy pad terminal D_PE to which the dummy lead terminal D_LE rubs. As shown in <FIG>, the bonding region BR may be substantially the same as a width of one surface of the dummy lead terminal D_LE. However, the present invention is not limited thereto, and the bonding region BR may further protrude outward from one surface of the dummy lead terminal D_LE to be larger than a width of the dummy lead terminal D_LE.

The non-bonding region NBR is a region adjacent to both ends of the bonding region BR, and is rubbed by the dummy lead terminal D_LE, but may be a region in which the dummy lead terminal D_LE and/or the dummy pad terminal D_PE are not melted.

During an ultrasonic bonding process, the bonding region BR and one surface of the bonding region BR of the dummy pad terminal D_PE are rubbed by the dummy lead terminal D_LE vibrating in the second direction DR2 from above, and when the dummy pad terminal D_PE is repeatedly rubbed in a constant vibration direction, scratches may be formed in at least some regions.

While the ultrasonic bonding process is performed, the scratches of the bonding region BR may be at least filled or covered by the dummy lead terminal D_LE and/or the dummy pad terminal D_PE, which are partially melted in the bonding region BR.

However, even though the ultrasonic bonding process is performed, a scratch SC of the non-bonding region NBR may not be filled or covered because the dummy lead terminal D_LE and the dummy pad terminal D_PE may not be melted with each other or at least not sufficiently melted to be bonded to each other. Accordingly, even though the number of the scratches SC of one surface of the non-bonding region NBR of the dummy pad terminal D_PE is greater than or equal to that of one surface of the bonding region BR, the degree of digging in the thickness direction may be large. Therefore, a surface roughness R1 of the one surface of the non-bonding region NBR of the dummy pad terminal D_PE may be greater than a surface roughness R2 of the one surface of the bonding region BR.

<FIG> is a plan layout view of first and second circuit boards according to another exemplary embodiment, and <FIG> is a cross-sectional view of a display panel according to another exemplary embodiment.

Referring to <FIG> and <FIG>, a display apparatus <NUM> according to the exemplary embodiment is different from the display apparatus <NUM> according to an exemplary embodiment in that a dummy pad terminal D_PE_1 and a dummy lead terminal D_LE_1 have a cylindrical pattern shape.

In more detail, the dummy pad terminal D_PE_1 and the dummy lead terminal D_LE_1 may have the cylindrical pattern shape. In a conductive layer including the dummy pad terminal D_PE_1 and the dummy lead terminal D_LE_1, a plurality of dummy pad terminals D_PE_1 and dummy lead terminals D_LE_1 may be formed by a photoresist process, and when the dummy pad terminal D_PE_1 and the dummy lead terminal D_LE_1 have the cylindrical pattern shape, such an additional process is not required, and thus the process may be simplified.

In addition, when the dummy pad terminal D_PE_1 and the dummy lead terminal D_LE_1 have the cylindrical pattern shape, a contact area between the dummy pad terminal D_PE_1 and the dummy lead terminal D_LE_1 is increased during the ultrasonic bonding so that the bonding force in the corresponding region may be increased as compared to when having the patterned terminals.

<FIG> is a plan layout view of first and second circuit boards according to an example which is not according to the claims, and <FIG> is a cross-sectional view of a display panel according to another example which is not according to the claims.

Referring to <FIG> and <FIG>, a display apparatus <NUM> according to an example which is not according to the claims is different from that according to an exemplary embodiment in that a dummy pad terminal D_PE_2 and a dummy lead terminal D_LE_2 have a long side in a second direction DR2 and a short side in a first direction DR1.

In more detail, in the display apparatus <NUM> according to the example, the dummy pad terminal D_PE_2 and the dummy lead terminal D_LE_2 may have the long side in the second direction DR2 and the short side in the first direction DR1.

In addition, the dummy pad terminal D_PE_2 according to the exemplary embodiment may include a first sub-panel terminal D_PE1_2a overlapping a panel alignment mark P_AM in the first direction DR1, and second and third sub-panel terminals D_PE_2b and D_PE1_2c overlapping the panel alignment mark P_AM in the second direction. Although only one first sub-panel terminal D_PE1_2a is illustrated in the drawing, the present invention is not limited thereto, and the first sub-panel terminal D_PE1_2a may include a plurality of first sub-panel terminals D_PE1 _2a separated from each other in the second direction DR2.

Similarly, the dummy lead terminal D_LE_2 may include a first sub dummy lead terminal D_LE1_2a overlapping a lead alignment mark L_AM in the first direction DR1, and second and third sub dummy lead terminals D_LE_2b and D_LE1_2c overlapping the lead alignment mark L_AM in the second direction DR2. Although only one first sub dummy lead terminal D_LE1a_2 is illustrated in the drawing, the present invention is not limited thereto, and the first sub dummy lead terminal D_LE1a_2 may include a plurality of first sub dummy lead terminals D_LE1a_2 separated from each other in the second direction DR2.

In the dummy pad terminal D_PE_2 and the dummy lead terminal D_LE_2 according to the example which is not according to the claims, a bonding force between a display panel 100_2 and a first circuit board 200_2 may be increased in an edge region of the base substrate <NUM>, and in addition, the bonding force between the display panel 100_2 and the first circuit board 200_2 may be increased even in a region overlapping the panel and lead alignment marks P_AM and L_AM in the second direction DR2.

<FIG> is a plan layout view of first and second circuit boards according to yet another exemplary embodiment, and <FIG> is a cross-sectional view of a display panel according to yet another exemplary embodiment.

Referring to <FIG> and <FIG>, a display apparatus <NUM> according to the exemplary embodiment is different from the display apparatus <NUM> according to an exemplary embodiment in that positions of a panel alignment mark P_AM and a dummy pad terminal D_PE, and a lead alignment mark L_AM and a dummy lead terminal D_LE are exchanged.

In more detail, the panel alignment mark P_AM according to the exemplary embodiment may be positioned at an edge region of the base substrate <NUM>, and the dummy pad terminal D_PE may be disposed between the panel alignment mark P_AM and the panel pad terminal P_PE.

Similarly, the lead alignment mark L_AM may be positioned at the edge region of the base substrate <NUM>, and the dummy lead terminal D_LE may be disposed between the lead alignment mark L_AM and the first lead terminal LE1.

According to the exemplary embodiment, the dummy pad terminal D_PE may be disposed adjacent to the panel pad terminal P_PE, and the dummy lead terminal D_LE may be disposed adjacent to the first lead terminal LE1.

Referring to <FIG> and <FIG>, a display apparatus <NUM> according to the exemplary embodiment is different from the display apparatus <NUM> according to an exemplary embodiment in that a dummy pad terminal D_PE_4 overlapping a panel alignment mark P_AM in a second direction DR2 and having a long side in the second direction DR2 is disposed above and/or below the panel alignment mark P_AM in the second direction DR2, and a dummy lead terminal D_LE_4 overlapping a lead alignment mark L_AM in the second direction DR2 and having a long side in the second direction DR2 is disposed above and/or below the lead alignment mark L_AM in the second direction DR2.

In more detail, the dummy pad terminal D_PE_4 according to the exemplary embodiment may further include dummy pad terminals D_PE_4a and D_PE_4b overlapping the panel alignment mark P_AM in the second direction DR2, having a long side in the second direction DR2, and disposed above and/or below the panel alignment mark P_AM in the second direction DR2 as well as the dummy pad terminal D_PE according to an exemplary embodiment.

Similarly, the dummy lead terminal D_LE_4 may further include dummy lead terminals D_LE_4a and D_LE_4b overlapping the lead alignment mark L_AM in the second direction DR2, having a long side in the second direction DR2, and disposed above and/or below the lead alignment mark L_AM in the second direction DR2 as well as the dummy lead terminal D_LE according to an exemplary embodiment.

<FIG> is a plan layout view of first and second circuit boards according to yet another exemplary embodiment, and <FIG> is a cross-sectional view of a display apparatus according to yet another exemplary embodiment.

Referring to <FIG> and <FIG>, a first circuit board 300_5 according to the exemplary embodiment is different from the display apparatus <NUM> according to an exemplary embodiment in that dummy lead terminals D_LE3 and D_LE4 are further included in a second circuit area CA2, and a second circuit board 400_1 further includes a circuit alignment mark C_AM and a dummy circuit pad terminal D_C_PE on one surface of a base circuit board <NUM>.

The shape and material of the third dummy lead terminal D_LE3 and the fourth dummy lead terminal D_LE4 are substantially the same as those of the dummy lead terminal D_LE1 according to an exemplary embodiment.

A circuit pad terminal C_PE may be selected from the illustrated materials of the panel pad terminal P_PE.

The circuit pad terminal C_PE may be disposed at a central portion of a circuit pad region C_PA. Although not shown in the drawings, the circuit pad terminal C_PE may be electrically connected to a control unit included in the second circuit board 400_1.

The circuit pad terminal C_PE may have substantially the same planar shape as the panel pad terminal P_PE described above. However, planar sizes of the lead terminals LE1 and LE2 may be smaller than a planar size of the circuit pad terminal C_PE.

The circuit alignment mark C_AM may include first and second circuit alignment marks C_AM. The circuit alignment marks C_AM may be disposed to be spaced apart from each other with the circuit pad terminal C_PE therebetween.

The circuit alignment marks C_AM may be disposed on both sides of the circuit pad terminal C_PE and may mark the circuit pad terminal C_PE. In addition, the circuit alignment mark C_AM may be disposed to overlap the lead alignment mark L_AM in a thickness direction and may align the second lead terminal LE2 to correspond to the circuit pad terminal C_PE in the thickness direction.

The circuit alignment mark C_AM may have a stacked structure that is the same as or similar to that of the circuit pad terminal C_PE and may be made of the same material.

In the drawings, the circuit alignment mark C_AM may have the same shape as the lead alignment mark L_AM described above. However, the present invention is not limited thereto, and the circuit alignment mark C_AM may have a shape different from that of the lead alignment mark L_AM. However, even in this case, the circuit alignment mark C_AM may have a shape so as to be aligned with the lead alignment mark L_AM.

Although one first circuit alignment mark C_AM1 and one second circuit alignment mark C_AM2 are illustrated in the drawing, the present invention is not limited thereto and there may be two or more.

Unlike the circuit pad terminal C_PE, the circuit alignment mark C_AM may be floated.

The dummy circuit pad terminal D_C_PE may be disposed adjacent to a long side of a circuit base substrate <NUM> (an edge of the circuit base substrate <NUM>). The dummy circuit pad terminal D_C_PE may include a first dummy circuit pad terminal D_C_PE1 disposed between the first circuit alignment mark C_AM1 and one long side of the circuit base substrate <NUM> and a second dummy circuit pad terminal D_C_PE2 disposed between the second circuit alignment mark C_AM2 and the other long side of the circuit base substrate <NUM>. The dummy circuit pad terminal D_C_PE may be disposed to be spaced apart from the circuit pad terminal C_PE with the circuit alignment mark C_AM therebetween.

The dummy circuit pad terminal D_C_PE may have substantially the same planar shape as the circuit pad terminal C_PE described above, but the present invention is not limited thereto.

Although three first dummy circuit pad terminals D_C_PE1 and three second dummy circuit pad terminals D_C_PE2 are shown in the drawing, the present invention is not limited thereto, and the number of each of the first and second dummy circuit pad terminals D_C_PE1 and D_C_PE2 may be two, or four or more.

Unlike the circuit pad terminal D_C_PE, the dummy circuit pad terminal D_C_PE may be floated.

Claim 1:
A display apparatus comprising:
a display panel (<NUM>) including a display area (DA) and a pad area (PA) disposed at one side of the display area (DA); and
a circuit board (<NUM>) attached to the pad area (PA),
wherein the pad area (PA) includes at least one signal pad terminal (P_PE) electrically connected to a first signal line (L1) passing through the display area (DA), and
the circuit board (<NUM>) includes a signal lead terminal (LE) connected to the signal pad terminal (P_PE),
characterized in that the pad area (PA) further includes at least one dummy pad terminal (D_PE) which is floated and not electrically connected to any signal line, and
the circuit board (<NUM>) further includes a dummy lead terminal (D_LE) connected to the dummy pad terminal (D_PE),
wherein a planar size of the dummy pad terminal (D_PE) is larger than a planar size of the dummy lead terminal (D_LE).