Patent Description:
A power module is used to supply a high voltage and current in order to drive a motor in a hybrid vehicle or an electric vehicle.

A double-sided cooling power module among the power modules has substrates installed on and below a semiconductor chip, respectively, and has heat sinks provided on the outsides of the substrates, respectively. The use of the double-sided cooling power module tends to be gradually increased because the double-sided cooling power module has more excellent cooling performance than a cross-section cooling power module having a heat sink provided on one side thereof.

The double-sided cooling power module that is used in an electric vehicle, etc. generates high heat due to a high voltage and vibration during driving because a power semiconductor chip made of silicon carbide (SiC), gallium nitride (GaN), etc. is mounted between the two substrates. In order to solve such a problem, it is important to satisfy both high strength and high heat dissipation characteristics. Additional prior art is known from the patent literature. For example, <CIT> and <CIT> disclose the usage of DBC substrate structures in fields of power modules. Further power modules are disclosed by <CIT> and <CIT>. Additionally, <CIT>, <CIT> and <CIT> form additional prior art together with <CIT> and <CIT>.

An object of the present disclosure is to provide a power module which has high strength and high heat dissipation characteristics and has an excellent bonding characteristic and which can reduce a volume by minimizing a current path and can improve efficiency and performance, and a method of manufacturing the same.

Furthermore, an object of the present disclosure is to provide a power module which protects a semiconductor chip and can enhance heat dissipation efficiency by constantly maintaining an interval between ceramic substrates in the ceramic substrates having an upper and lower duplex structure, and a method of manufacturing the same.

Furthermore, an object of the present disclosure is to provide a power module which enables an electrical connection between ceramic substrates and can increase heat dissipation efficiency because the power module is disposed between the ceramic substrates and is directly bonded to an electrode pattern between the ceramic substrates in the ceramic substrates having an upper and lower duplex structure, and a method of manufacturing the same.

Furthermore, an object of the present disclosure is to provide a power module which can improve bonding reliability of a spacer that maintains an interval between a lower ceramic substrate and an upper ceramic substrate and improve a thermal or mechanical impact on the ceramic substrates attributable to the bonding, and a method of manufacturing the same.

According to a characteristic of the present disclosure for achieving the aforementioned objects, a power module of the present disclosure includes a lower ceramic substrate, an upper ceramic substrate disposed over the lower ceramic substrate in a way to be spaced apart from the lower ceramic substrate and configured to have a semiconductor chip mounted on a lower surface of the upper ceramic substrate, a spacer configured to have one end bonded to the lower ceramic substrate and have the other end opposite to the one end bonded to the upper ceramic substrate, a first bonding layer configured to bond the one end of the spacer to the lower ceramic substrate, and a second bonding layer configured to bond the other end of the spacer to the upper ceramic substrate. Further features are defined by the independent claims.

The spacer includes one or more of an insulating spacer and a conductive spacer.

The insulating spacer is formed of one kind selected from Al<NUM>O<NUM>, ZTA, Si<NUM>N<NUM>, and AlN or an alloy in which two or more of the Al<NUM>O<NUM>, ZTA, Si<NUM>N<NUM>, and AlN are mixed.

The conductive spacer may be one selected from a Cu layer, a Mo layer, and a CuMo alloy layer or may have a structure in which two or more of the Cu layer, the Mo layer, and the CuMo alloy layer are mixed.

The first bonding layer may be made of a solder.

The second bonding layer may be made of a solder.

The second bonding layer may be made of an Ag paste.

The Ag paste may include Ag nano powder of <NUM> to <NUM> weight% and a binder of <NUM> to <NUM> weight%.

The second bonding layer may include one selected from Ti, Ag, Cu, and AgCu or an alloy in which two or more of the Ti, Ag, Cu, and AgCu are mixed.

A method of manufacturing a power module includes preparing the lower ceramic substrate, preparing the upper ceramic substrate, preparing a spacer, forming a first bonding layer at one end of the spacer, bonding the one end of the spacer to an upper surface of the lower ceramic substrate through the medium of the first bonding layer, forming a second bonding layer at the other end of the spacer, and bonding the upper ceramic substrate to the other end of the spacer through the medium of the second bonding layer.

The forming of the first bonding layer at the one end of the spacer includes forming, at the one end of the spacer, three layers: a Ti layer, an Ag layer and a Cu layer, by using any one of methods comprising sputtering, paste printing, foil attachment, and filler attachment. The bonding of the one end of the spacer to the upper surface of the lower ceramic substrate through the medium of the first bonding layer may include brazing-bonding the one end of the spacer to the upper surface of the lower ceramic substrate at a temperature of <NUM> to <NUM>.

The forming of the first bonding layer at the one end of the spacer may include forming the first bonding layer by coating a solder on the one end of the spacer. The bonding of the one end of the spacer to the upper surface of the lower ceramic substrate through the medium of the first bonding layer may include performing soldering at <NUM> to <NUM>.

The forming of the second bonding layer at the other end of the spacer may include forming the second bonding layer by coating a solder on the other end of the spacer. The bonding of the upper ceramic substrate to the other end of the spacer through the medium of the second bonding layer may include performing soldering at <NUM> to <NUM>.

The forming of the second bonding layer at the other end of the spacer may include forming the second bonding layer by printing or coating an Ag paste on the other end of the spacer. The bonding of the upper ceramic substrate to the other end of the spacer through the medium of the second bonding layer may include performing sintering at <NUM> to <NUM>.

The forming of the second bonding layer at the other end of the spacer may include forming, at the other end of the spacer, one layer or two or more layers selected from a Ti layer, an Ag layer, a Cu layer, and an AgCu layer by using any one of methods comprising sputtering, paste printing, foil attachment, and filler attachment. The bonding of the upper ceramic substrate to the other end of the spacer through the medium of the second bonding layer may include brazing-bonding the upper ceramic substrate to the other end of the spacer at a temperature of <NUM> to <NUM>.

The bonding of the upper ceramic substrate to the other end of the spacer through the medium of the second bonding layer may be performed simultaneously with the bonding of the one end of the spacer to the upper surface of the lower ceramic substrate through the medium of the first bonding layer.

The preparing of the spacer may include preparing one or more of an insulating spacer and a conductive spacer.

A spacer formed of one kind selected from Al<NUM>O<NUM>, ZTA, Si<NUM>N<NUM>, and AlN or an alloy in which two or more of the Al<NUM>O<NUM>, ZTA, Si<NUM>N<NUM>, and AlN are mixed may be prepared as the insulating spacer.

A three-layer structure spacer of Cu-CuMo-Cu in which Cu has been brazing-bonded to upper and lower surfaces of CuMo may be prepared as the conductive spacer.

The present disclosure has effects in that it has high strength and high heat dissipation characteristics and has an excellent bonding characteristic, can reduce a volume by minimizing a current path, and can improve efficiency and performance due to optimization for high-speed switching.

Furthermore, the present disclosure has effects in that it can protect the semiconductor chip disposed between the upper ceramic substrate and the lower ceramic substrate and can enhance heat dissipation efficiency because an interval between the lower ceramic substrate and the upper ceramic substrate is constantly maintained by disposing the insulating spacer between the lower ceramic substrate and the upper ceramic substrate.

Furthermore, the present disclosure has effects in that bonding reliability is excellent because the insulating spacer is brazing-bonded to the lower ceramic substrate and is heated, pressurized, and bonded to the upper ceramic substrate, the semiconductor chip can be stably protected because an interval between the lower ceramic substrate and the upper ceramic substrate is constantly maintained, and thus the lifespan and performance of the power module can be improved.

Furthermore, the present disclosure has effects in that it can prevent an electrical loss in a power transfer path and can enhance heat dissipation efficiency because an interval between the lower ceramic substrate and the upper ceramic substrate is constantly maintained, by directly bonding one end and the other end of the conductive spacer to the lower ceramic substrate and the upper ceramic substrate and disposing the conductive spacer between the lower ceramic substrate and the upper ceramic substrate.

Furthermore, the present disclosure has an effect in that it can enhance heat dissipation efficiency because heat generated from the semiconductor chip is rapidly transferred to the lower ceramic substrate or the upper ceramic substrate by allowing one end of the conductive spacer to be brazing-bonded to the lower ceramic substrate and the other end thereof to be bonded to the upper ceramic substrate by the Ag paste.

Furthermore, the present disclosure has effects in that bonding reliability is excellent because the conductive spacer can be brazing-bonded to the lower ceramic substrate and can be heated, pressurized, and bonded to the upper ceramic substrate and the semiconductor chip can be stably protected because an interval between the lower ceramic substrate and the upper ceramic substrate is constantly maintained.

Furthermore, according to the present disclosure, the spacer may be bonded between the lower ceramic substrate and the upper ceramic substrate through one brazing bonding process, or the spacer may be bonded between the lower ceramic substrate and the upper ceramic substrate through one brazing bonding process and a sintering process using the solder or the Ag paste.

Accordingly, the present disclosure has effects in that it can enhance bonding reliability because at least one surface of the spacer is brazing-bonded, can improve a thermal impact on the ceramic substrate because only one brazing process is performed, and can prevent the breakage of or damage to the ceramic substrate by improving a mechanical impact on the ceramic substrate because the solder is bonded without being pressurized in a sintering process.

Furthermore, the present disclosure has an effect in that it can stably protect the semiconductor chip by improving electrical insulating and heat dissipation efficiency because the spacer is stably bonded between the lower ceramic substrate and the upper ceramic substrate and thus an interval between the lower ceramic substrate and the upper ceramic substrate is constantly maintained.

Alternatively, the present disclosure has an effect in that it can improve a thermal or mechanical impact on the ceramic substrate attributable to bonding by improving bonding reliability of the insulating spacer through a brazing bonding process or a soldering process, but improving the bonding reliability without being pressurized upon bonding.

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

<FIG> is a perspective view of a power module according to an embodiment of the present disclosure. <FIG> is an exploded perspective view of the power module according to an embodiment of the present disclosure.

As illustrated in <FIG> and <FIG>, the power module <NUM> according to an embodiment of the present disclosure is an electronic part having a package form, which is formed by accommodating, in a housing <NUM>, various components that form the power module. The power module <NUM> is formed in a form in which substrates and elements are disposed and protected within the housing <NUM>.

The power module <NUM> may include multiple substrates and multiple semiconductor chips. The power module <NUM> according to an embodiment includes the housing <NUM>, a lower ceramic substrate <NUM>, an upper ceramic substrate <NUM>, a PCB substrate <NUM>, and a heat sink <NUM>.

An empty space that is opened up and down is formed at the center of the housing <NUM>. First terminals <NUM> and a second terminal <NUM> are disposed on both sides of the housing <NUM>. The heat sink <NUM>, the lower ceramic substrate <NUM>, the upper ceramic substrate <NUM>, and the PCB substrate <NUM> are sequentially stacked in the empty space at the center of the housing <NUM> at regular intervals. Support bolts <NUM> for connecting external terminals are fastened to the first terminals <NUM> and the second terminal <NUM> on both sides of the housing <NUM>. The first terminals <NUM> and the second terminal <NUM> are used as the input and output stages of a power source.

As illustrated in <FIG>, in the power module <NUM>, the lower ceramic substrate <NUM>, the upper ceramic substrate <NUM>, and the PCB substrate <NUM> are sequentially accommodated in the empty space at the center of the housing <NUM>. Specifically, the heat sink <NUM> is disposed at the lower surface of the housing <NUM>. The lower ceramic substrate <NUM> is attached to the upper surface of the heat sink <NUM>. The upper ceramic substrate <NUM> is disposed over the lower ceramic substrate <NUM> at a regular interval. The PCB substrate <NUM> is disposed over the upper ceramic substrate <NUM> at a regular interval.

The state in which the PCB substrate <NUM> has been disposed in the housing <NUM> may be fixed by guide grooves <NUM> and <NUM> formed at an edge of the PCB substrate <NUM> in a way to be concaved and a guide rib <NUM> and a locking projection <NUM> that are formed in the housing <NUM> in a way to correspond to the guide grooves <NUM> and <NUM>. The multiple guide grooves <NUM> and <NUM> are formed to enclose the edge of the PCB substrate <NUM> according to an embodiment. The guide rib <NUM> formed on the inner surface of the housing <NUM> is guided through some guide grooves <NUM> of the multiple guide grooves <NUM> and <NUM>. The locking projection <NUM> formed on the inner surface of the housing <NUM> passes through the remaining some guide grooves <NUM> of the multiple guide grooves <NUM> and <NUM>, and is hung thereto.

Alternatively, the state in which the heat sink <NUM>, the lower ceramic substrate <NUM>, and the upper ceramic substrate <NUM> are accommodated in the empty space at the center of the housing <NUM> and the PCB substrate <NUM> is disposed at the upper surface thereof may also be fixed by a fastening bolt (not illustrated). However, fixing the PCB substrate <NUM> to the housing <NUM> through the guide groove and the locking projection structure reduces an assembly time and has a simple assembly process compared to a case in which the PCB substrate <NUM> is fixed to the housing <NUM> by the fastening bolt.

Fastening holes <NUM> are formed at four corners of the housing <NUM>. The fastening holes <NUM> communicate with the communication holes <NUM> formed in the heat sink <NUM>. Fixing bolts <NUM> are fastened to penetrate the fastening holes <NUM> and the communication holes <NUM>. The ends of the fixing bolts <NUM> that have penetrated the fastening holes <NUM> and the communication holes <NUM> may be fastened to fixing holes of a fixing jig to be disposed at the lower surface of the heat sink <NUM>.

Bus bars <NUM> are connected to the first terminals <NUM> and the second terminal <NUM>. The bus bars <NUM> connect the first terminals <NUM> and the second terminal <NUM> to the upper ceramic substrate <NUM>. Three bus bars <NUM> are provided. One of the bus bars <NUM> connects a + terminal, among the first terminals <NUM>, to a first electrode pattern a of the upper ceramic substrate <NUM>, and another of the bus bars <NUM> connects a - terminal, among the first terminals <NUM>, to a third electrode pattern c. The remainder of the bus bars <NUM> connects the second terminal <NUM> to a second electrode pattern b. For the first electrode pattern a, the second electrode pattern b, and the third electrode pattern c, reference is made to <FIG> and <FIG> to be described later.

<FIG> is a side cross-sectional view of the power module according to an embodiment of the present disclosure.

As illustrated in <FIG>, the power module <NUM> is a duplex structure of the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. A semiconductor chip G is disposed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The semiconductor chip G may be any one of a gallium nitride (GaN) chip, a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET), and a high electric mobility transistor (HEMT), but the GaN chip is preferably used as the semiconductor chip G. The gallium nitride (GaN) chip G is a semiconductor chip that functions as a high power (<NUM> A) switch and a high-speed (~<NUM>) switch. The GaN chip has advantages in that it is more resistant to heat than the existing silicon-based semiconductor chip and can also reduce the size of the chip.

Each of the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> is formed of a ceramic substrate including a ceramic base and a metal layer brazing-bonded to at least one surface of the ceramic base so that heat dissipation efficiency of heat generated from the semiconductor chip G can be increased.

The ceramic base may be any one of alumina (Al<NUM>O<NUM>), AlN, SiN, and Si<NUM>N<NUM>, for example. The metal layer is a metal foil brazing-bonded to a surface of the ceramic base, and is formed in the form of an electrode pattern on which the semiconductor chip G is mounted and an electrode pattern on which a driving element is mounted. For example, the metal layer is formed in the form of an electrode pattern in an area on which a semiconductor chip or a peripheral part will be mounted. The metal foil is an aluminum foil or a copper foil, for example. The metal foil is sintered on the ceramic base at <NUM> to <NUM> and brazing-bonded to the ceramic base, for example. Such a ceramic substrate is called an AMB substrate. An embodiment is described by taking the AMB substrate as an example, but may apply a DBC substrate, a TPC substrate, or a DBA substrate. However, in terms of durability and heat dissipation efficiency, the AMB substrate is most appropriate. For the reason, the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> are AMB substrates, for example.

The PCB substrate <NUM> is disposed over the upper ceramic substrate <NUM>. That is, the power module <NUM> is constituted with a three-layer structure of the lower ceramic substrate <NUM>, the upper ceramic substrate <NUM>, and the PCB substrate <NUM>. Heat dissipation efficiency is increased by disposing the semiconductor chip G for control for high power between the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM>. Damage to the PCB substrate <NUM> attributable to heat which occurs in the semiconductor chip G is prevented by disposing the PCB substrate <NUM> for control for low power at the top of the power module <NUM>. The lower ceramic substrate <NUM>, the upper ceramic substrate <NUM>, and the PCB substrate <NUM> may be connected or fixed by pins.

The heat sink <NUM> is disposed under the lower ceramic substrate <NUM>. The heat sink <NUM> is for discharging heat that is generated from the semiconductor chip G. The heat sink <NUM> is formed in a quadrangle plate shape having a predetermined thickness. The heat sink <NUM> is formed to have an area corresponding to the housing <NUM>, and may be formed of a copper or aluminum material in order to increase heat dissipation efficiency.

Hereinafter, characteristics for each component of the power module of the present disclosure are more specifically described. In a drawing that describes the characteristics for each component of the power module, there is a portion that has been expressed by enlarging or exaggerating the drawing in order to highlight the characteristics of each component. Accordingly, a portion that is not partially identical with some of the basic drawing illustrated in <FIG> may be present.

<FIG> is a perspective view illustrating a housing according to an embodiment of the present disclosure.

As illustrated in <FIG>, the housing <NUM> has an empty space formed at the center thereof, and has the first terminals <NUM> and the second terminal <NUM> disposed at both ends thereof. The housing <NUM> may have the first terminals <NUM> and the second terminal <NUM> formed at both ends thereof by using an insert injection method in a way to be integrally fixed thereto.

In the existing power module, a connection pin is applied to the housing through insert injection in order to connect isolated circuits. In contrast, in the present embodiment, the housing <NUM> has a shape that is manufactured by excluding the connection pin upon manufacturing. This improves flexibility for torsion moment of the power module by simplifying a shape of the power module because the connection pin is not disposed within the housing <NUM>.

The housing <NUM> has the fastening holes <NUM> formed at the four corners thereof. The fastening holes <NUM> communicate with the communication holes <NUM> formed in the heat sink <NUM>. The first terminals <NUM> and the second terminal <NUM> have support holes <NUM> formed therein. The support bolts <NUM> for connecting the first terminals <NUM> and the second terminal <NUM> to external terminals, such as a motor, are fastened to support bolts <NUM> (refer to <FIG>).

The housing <NUM> is formed of an insulating material. The housing <NUM> may be formed of an insulating material so that heat generated from the semiconductor chip G is not delivered to the PCB substrate <NUM> over the housing <NUM>, through the housing <NUM>.

Alternatively, a heat dissipation plastic material may be applied to the housing <NUM>. The heat dissipation plastic material may be applied to the housing <NUM> so that heat generated from the semiconductor chip G can be discharged to the outside through the housing <NUM>. For example, the housing <NUM> may be formed of engineering plastics. The engineering plastics has high heat resistance, excellent strength, chemical resistance, and wear resistance, and may be used for a long time at <NUM> or more. The engineering plastics may be made of one material among polyamide, polycarbonate, polyester, and modified polyphenylene oxide.

The semiconductor chip G performs a repetitive operation as a switch. Accordingly, the housing <NUM> is subjected to stress attributable to a high temperature and a temperature change, but the engineering plastics is relatively stable with respect to a high temperature and a temperature change and is excellent in a heat dissipation characteristic compared to common plastics because the engineering plastics has excellent high temperature stability.

In an embodiment, the housing <NUM> may have been manufactured by applying a terminal made of aluminum or copper to the engineering plastic material through insert injection. The housing <NUM> made of the engineering plastic material discharges heat to the outside by propagating heat. The housing <NUM> may more increase thermal conductivity than a common engineering plastic material and may become light-weight and high heat dissipation engineering plastics, compared to aluminum by filling resin with a high heat conductivity filler.

Alternatively, the housing <NUM> may have a heat dissipation characteristic by coating a graphene heat dissipation coating material on the inside or outside of engineering plastics or high strength plastic material.

<FIG> is a perspective view illustrating a lower ceramic substrate according to an embodiment of the present disclosure.

As illustrated in <FIG> and <FIG>, the lower ceramic substrate <NUM> is attached to the upper surface of the heat sink <NUM>. Specifically, the lower ceramic substrate <NUM> is disposed between the semiconductor chip G and the heat sink <NUM>. The lower ceramic substrate <NUM> plays a role to deliver, to the heat sink <NUM>, heat generated from the semiconductor chip G and to prevent a short by insulating the semiconductor chip G and the heat sink <NUM>.

The lower ceramic substrate <NUM> may be soldered and bonded to the upper surface of the heat sink <NUM>. The heat sink <NUM> is formed to have an area corresponding to the housing <NUM>, and may be formed of a copper material in order to increase heat dissipation efficiency. SnAg, SnAgCu, etc. may be used as a solder for the soldering and bonding.

<FIG> is a diagram illustrating the upper surface and the lower surface of the lower ceramic substrate according to an embodiment of the present disclosure.

As illustrated in <FIG>, the lower ceramic substrate <NUM> includes a ceramic base <NUM> and metal layers <NUM> and <NUM> brazing-bonded to the upper surface and the lower surface of the ceramic base <NUM>. In the lower ceramic substrate <NUM>, the ceramic base <NUM> may have a thickness of <NUM>, and each of the metal layers <NUM> and <NUM> formed at the upper surface and the lower surface of the ceramic base <NUM> may have a thickness of <NUM>, for example.

The metal layer <NUM> at the upper surface 200a of the lower ceramic substrate <NUM> may be an electrode pattern on which a driving element is mounted. The driving element mounted on the lower ceramic substrate <NUM> may be an NTC temperature sensor <NUM>. The NTC temperature sensor <NUM> is mounted on the upper surface of the lower ceramic substrate <NUM>. The NTC temperature sensor <NUM> is for providing information on a temperature within the power module attributable to heat generated from the semiconductor chip G. The metal layer <NUM> at the lower surface 200b of the lower ceramic substrate <NUM> may be formed on the entire lower surface of the lower ceramic substrate <NUM> in order to facilitate the delivery of heat to the heat sink <NUM>.

An insulating spacer <NUM> is bonded to the lower ceramic substrate <NUM>. The insulating spacer <NUM> is bonded to the upper surface of the lower ceramic substrate <NUM>, and defines an isolation distance between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

The insulating spacer <NUM> defines the isolation distance between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, thereby increasing heat dissipation efficiency of heat generated from the semiconductor chip G mounted on the lower surface of the upper ceramic substrate <NUM> and preventing an electrical shock, such as a short, by preventing interference between the semiconductor chips G.

The multiple insulating spacers <NUM> are bonded at predetermined intervals by enclosing an edge at the upper surface of the lower ceramic substrate <NUM>. An interval between the insulating spacers <NUM> is used as a space for increasing heat dissipation efficiency. In the drawing, the insulating spacers <NUM> are disposed to enclose the edge of the lower ceramic substrate <NUM>. For example, eight insulating spacers <NUM> are disposed at regular intervals.

The insulating spacers <NUM> are integrally bonded to the lower ceramic substrate <NUM>. The insulating spacers <NUM> may be applied for the purpose of checking the alignment of the upper ceramic substrate <NUM> when the upper ceramic substrate <NUM> is disposed over the lower ceramic substrate <NUM>. In the state in which the insulating spacers <NUM> have been bonded to the lower ceramic substrate <NUM>, when the upper ceramic substrate <NUM> on which the semiconductor chip G has been mounted is disposed over the lower ceramic substrate <NUM>, the insulating spacers <NUM> may be applied for the purpose of checking the alignment of the upper ceramic substrate <NUM>. Furthermore, the insulating spacers <NUM> contribute to preventing the bending of the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> by supporting the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

The insulating spacers <NUM> may be formed of a ceramic material in order to insulate a chip mounted on the lower ceramic substrate <NUM> and a chip mounted on the upper ceramic substrate <NUM> and a part. For example, the insulating spacers may be formed of one kind selected among Al<NUM>O<NUM>, ZTA, Si<NUM>N<NUM>, and AlN or a mixed alloy of two or more of them. Al<NUM>O<NUM>, ZTA, Si<NUM>N<NUM>, and AlN are insulating materials having excellent mechanical strength and heat-resisting properties.

The insulating spacers <NUM> are brazing-bonded to the lower ceramic substrate <NUM>. The insulating spacers <NUM> are brazing-bonded to the lower ceramic substrate <NUM> because the substrate may be broken due to thermal and mechanical shocks upon soldering or pressurization sintering if the insulating spacers <NUM> are soldered and bonded to the lower ceramic substrate <NUM>. A brazing bonding layer including an AgCu layer and a Ti layer may be used for the brazing bonding. Heat treatment for the brazing may be performed at <NUM> to <NUM>. After the brazing, the insulating spacers <NUM> are integrally formed with the metal layer <NUM> of the lower ceramic substrate <NUM>. The thickness of the brazing bonding layer is <NUM> to <NUM>, which is thin to the extent that the height of the insulating spacers is not affected and has high bonding strength.

A conductive spacer <NUM> is installed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The conductive spacer <NUM> may perform an electrical connection between electrode patterns instead of a connection pin in a substrate having an upper and lower duplex structure. The conductive spacer <NUM> can increase bonding strength and improve electrical characteristics by directly connecting the substrates, while preventing an electrical loss and shot. The conductive spacer <NUM> may have one end bonded to the electrode pattern of the lower ceramic substrate <NUM> by using a brazing bonding method. Furthermore, the conductive spacer <NUM> may have the other end opposite to the one end bonded to the electrode pattern of the upper ceramic substrate <NUM> by using a brazing bonding method or a soldering bonding method. The conductive spacer <NUM> may be a Cu or Cu+CuMo alloy.

<FIG> is a perspective view illustrating an upper ceramic substrate according to an embodiment of the present disclosure. <FIG> is a diagram illustrating the upper surface and the lower surface of the upper ceramic substrate according to an embodiment of the present disclosure.

As illustrated in <FIG>, the upper ceramic substrate <NUM> is disposed over the lower ceramic substrate <NUM>.

The upper ceramic substrate <NUM> is an intermediate substrate having a stack structure. The upper ceramic substrate <NUM> has the semiconductor chip G mounted on a lower surface thereof and a high side circuit and a low side circuit for high-speed switching constructed on the lower surface.

The upper ceramic substrate <NUM> includes a ceramic base <NUM> and metal layers <NUM> and <NUM> brazing-bonded to the upper surface and the lower surface of the ceramic base <NUM>. In the upper ceramic substrate <NUM>, the ceramic base has a thickness of <NUM>, and each of electrode patterns of the upper surface 300a and the lower surface 300b of the ceramic base has a thickness of <NUM>, for example. The ceramic substrate is not twisted upon brazing only when the patterns at the upper surface and the lower surface thereof have the same thickness.

The electrode patterns that are formed by the metal layer <NUM> at the upper surface of the upper ceramic substrate <NUM> are divided into the first electrode pattern a, the second electrode pattern b, and the third electrode pattern c. The electrode patterns that are formed by the metal layer <NUM> at the lower surface of the upper ceramic substrate <NUM> correspond to the electrode patterns that are formed by the metal layer <NUM> at the upper surface of the upper ceramic substrate <NUM>. Dividing the electrode patterns at the upper surface of the upper ceramic substrate <NUM> into the first electrode pattern a, the second electrode pattern b, and the third electrode pattern c is for division into a high side circuit and a low side circuit for high-speed switching.

The semiconductor chip G is provided at the lower surface 300b of the upper ceramic substrate <NUM> in a flip chip form by an adhesive layer, such as a solder or an Ag paste. As the semiconductor chip G is provided in the flip chip form at the lower surface of the upper ceramic substrate <NUM>, an inductance value can be lowered as much as possible because wire bonding is omitted. Accordingly, heat dissipation performance can also be improved.

As illustrated in <FIG>, the semiconductor chip G may be connected in parallel by two for high-speed switching. Two semiconductor chips G are disposed at a location at which the first electrode pattern a and the second electrode pattern b, among the electrode patterns of the upper ceramic substrate <NUM>, are connected. The remaining two semiconductor chips G are disposed in parallel at a location at which the second electrode pattern b and the third electrode pattern c are connected. For example, the capacity of one semiconductor chip G is <NUM> A. Accordingly, the capacity of two semiconductor chips G become <NUM> A by connecting the two semiconductor chips G in parallel. The semiconductor chip G is a GaN chip.

The purpose of the power module using the semiconductor chip G is for high-speed switching. For the high-speed switching, it is important to connect the gate drive IC terminal and a gate terminal of the semiconductor chip G at a very short distance. Accordingly, a connection distance between the gate drive IC and the gate terminal is minimized by connecting the semiconductor chips G in parallel. Furthermore, in order for the semiconductor chip G to switch at high speed, it is important for the gate terminal and source terminal of the semiconductor chip G to maintain the same interval. To this end, the gate terminal and the source terminal may be disposed so that a connection pin is connected to the middle between the semiconductor chip G and the semiconductor chips G. A problem occurs if the gate terminal and the source terminal do not maintain the same interval or the length of a pattern is changed.

The gate terminal is a terminal that turns on/off the semiconductor chip G by using a low voltage. The gate terminal may be connected to the PCB substrate <NUM> through the connection pin. The source terminal is a terminal to and from which a high current is input and output. The semiconductor chip G includes a drain terminal. The source terminal and the drain terminal may change the directions of currents thereof by being divided into an N type and a P type. The source terminal and the drain terminal are responsible for the input and output of a current through the first electrode pattern a, the second electrode pattern b, and the third electrode pattern c, that is, the electrode patterns on which the semiconductor chip G is mounted. The source terminal and the drain terminal are connected to the first terminal <NUM> and the second terminal <NUM> in <FIG>, which are responsible for the input and output of a power source.

Referring to <FIG> and <FIG>, the first terminal <NUM> illustrated in <FIG> includes a + terminal and a - terminal. A power source that is introduced into the + terminal of the first terminal <NUM> is output to the second terminal <NUM> through the first electrode pattern a of the upper ceramic substrate <NUM> illustrated in <FIG>, the semiconductor chip G disposed between the first electrode pattern a and the second electrode pattern b, and the second electrode pattern b. Furthermore, a power source introduced into the second terminal <NUM> illustrated in <FIG> is output to the - terminal of the first terminal <NUM> through the second electrode pattern b illustrated in <FIG>, the semiconductor chip G disposed between the second electrode pattern b and the third electrode pattern c, and the third electrode pattern c. For example, a power that is introduced from the first terminal <NUM> and output to the second terminal <NUM> through the semiconductor chip G becomes a high side. A power source that is introduced from the second terminal <NUM> and output to the first terminal <NUM> through the semiconductor chip G becomes a low side.

As illustrated in <FIG>, the upper ceramic substrate <NUM> may have a cutting part <NUM> formed at a portion corresponding to the NTC temperature sensor <NUM>. The NTC temperature sensor <NUM> is mounted on the upper surface of the lower ceramic substrate <NUM>. The NTC temperature sensor <NUM> is for providing information on a temperature within the power module, which is attributable to heat generated from the semiconductor chip G. However, interference occurs between the NTC temperature sensor <NUM> and the upper ceramic substrate <NUM> because the thickness of the NTC temperature sensor <NUM> is greater than an interval between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. In order to solve such a problem, the cutting part <NUM> is formed by cutting a portion of the upper ceramic substrate <NUM> that interferes with the NTC temperature sensor <NUM>.

A silicon fluid or epoxy for molding may be injected into the space between the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM> through the cutting part <NUM>. In order to insulate the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM>, the silicon fluid or the epoxy needs to be injected. In order to inject the silicon fluid or the epoxy into the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM>, the cutting part <NUM> may be formed by cutting one surface of the upper ceramic substrate <NUM>. The cutting part <NUM> is formed at a location corresponding to the NTC temperature sensor <NUM>, and can also prevent interference between the upper ceramic substrate <NUM> and the NTC temperature sensor <NUM>. The silicon fluid or the epoxy may be filled into the space between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> and the space between the upper ceramic substrate <NUM> and the PCB substrate <NUM> for the purposes of protecting the semiconductor chip G, reducing vibration, and insulation.

A through hole <NUM> is formed in the upper ceramic substrate <NUM>. The through hole <NUM> is for connecting the semiconductor chip G mounted on the upper ceramic substrate <NUM> and a driving element mounted on the PCB substrate <NUM> at the shortest distance and connecting the NTC temperature sensor <NUM> mounted on the lower ceramic substrate <NUM> and a driving element mounted on the PCB substrate <NUM> at the shortest distance in an upper and lower duplex substrate structure.

Eight through holes <NUM> are formed at locations at which the semiconductor chip is installed by two. Two through holes <NUM> are installed at a location at which the NTC temperature sensor is installed. A total of ten through holes <NUM> may be formed. Furthermore, multiple through holes <NUM> may be formed at portions of the upper ceramic substrate <NUM> in which the first electrode pattern a and the third electrode pattern c have been formed.

The multiple through holes <NUM> formed in the first electrode pattern a enable a current that is introduced into the first electrode pattern a at the upper surface of the upper ceramic substrate <NUM> to move to the first electrode pattern a formed at the lower surface of the upper ceramic substrate <NUM> and to be introduced into the semiconductor chip G. The multiple through holes <NUM> formed in the third electrode pattern c enable a current that is introduced into the semiconductor chip G to move to the third electrode pattern c at the upper surface of the upper ceramic substrate <NUM> through the third electrode pattern c at the lower surface of the upper ceramic substrate <NUM>.

The diameter of the through hole <NUM> may be <NUM> to <NUM>. A connection pin is installed in the through hole <NUM>, and is connected to the electrode pattern of the PCB substrate, which may be connected to a driving element mounted on the PCB substrate <NUM> through the through hole <NUM>. In the upper and lower duplex substrate structure, the connection between the electrode patterns through the through hole <NUM> and the connection pin installed in the through hole <NUM> can contribute to improving restrictions according to the size of the power module by removing various output losses through the shortest distance connection.

A plurality of via holes <NUM> may be formed in the electrode pattern of the upper ceramic substrate <NUM>. The via holes <NUM> may be processed to be at least <NUM>% or more compared to the area of the substrate. It has been described that the area of the via holes <NUM> is applied as being at least <NUM>% or more compared to the area of the substrate, for example, but the present disclosure is not limited thereto and the area of the via holes <NUM> may be processed to be <NUM>% or less compared to the area of the substrate.

For example, <NUM> via holes may be formed in the first electrode pattern a, <NUM> via holes may be formed in the second electrode pattern b, and <NUM> via holes may be formed in the third electrode pattern c. The plurality of via holes <NUM> formed in each of the electrode patterns is for high current electrification and a high current distribution. If the electrode pattern at the upper surface of the upper ceramic substrate <NUM> and the electrode pattern at the lower surface of the upper ceramic substrate <NUM> become conductive to each other in one slot form, a problem, such as a short or overheating, may occur because a high current flows into only one side.

The via hole <NUM> is filled with a conductive substance. The conductive substance may be Ag or an Ag alloy. The Ag alloy may be an Ag-Pd paste. The conductive substance that is filled into the via hole <NUM> electrically connects the electrode pattern at the upper surface of the upper ceramic substrate <NUM> and the electrode pattern at the lower surface of the upper ceramic substrate <NUM>. The via hole <NUM> may be formed by laser processing. The via hole <NUM> may be seen in the enlarged view of <FIG>.

<FIG> is a plan view of a PCB substrate according to an embodiment of the present disclosure.

As illustrated in <FIG>, a driving element for switching the semiconductor chip G or switching a GaN chip (a semiconductor chip) by using information detected by the NTC temperature sensor (reference numeral <NUM> in <FIG>) is mounted on the PCB substrate <NUM>. The driving element includes a gate drive IC.

A capacitor <NUM> is mounted on the upper surface of the PCB substrate <NUM>. The capacitor <NUM> is mounted on the upper surface of the PCB substrate <NUM>, that is, a location between the semiconductor chip G disposed to connect the first electrode pattern a and second electrode pattern b of the upper ceramic substrate <NUM> and the semiconductor chips G is disposed to connect the second electrode pattern b and third electrode pattern c of the upper ceramic substrate <NUM>.

When the capacitor <NUM> is mounted on the upper surface of the PCB substrate <NUM>, that is, the location between the semiconductor chips G, it is more advantageous in high-speed switching because the semiconductor chip G and a drive IC circuit can be connected at the shortest distance by using a connection pin (reference numeral <NUM> in <FIG>). For example, ten capacitors <NUM> may be connected in parallel in order to satisfy the capacity thereof. In order to secure <NUM> µF or more for a decoupling use at the input stage of the capacitors, the capacity needs to be secured by connecting ten high-voltage capacitors. A relation equation is checked in 56µF/630V×5ea= <NUM> µF. The gate drive IC circuit includes a high side gate drive IC and a low side gate drive IC.

<FIG> is a perspective view illustrating the state in which pin connections have been coupled to the upper ceramic substrate according to an embodiment of the present disclosure.

As illustrated in <FIG>, a connection pin <NUM> is inserted into the through hole (reference numeral <NUM> in <FIG>) formed at a location adj acent to the semiconductor chip G in the upper ceramic substrate <NUM>. The connection pin <NUM> inserted into the through hole <NUM> formed at the location adjacent to the semiconductor chip G may be inserted into a through hole <NUM> formed at a location corresponding to the PCB substrate (reference numeral <NUM> in <FIG>), and may connect the gate terminal on which the semiconductor chip G is mounted and the electrode pattern of the PCB substrate <NUM>.

Furthermore, the connection pin <NUM> is inserted into the through hole <NUM> formed at a location adjacent to the NTC temperature sensor <NUM> in the upper ceramic substrate <NUM>. The connection pin <NUM> inserted into the through hole <NUM> formed at the location adjacent to the NTC temperature sensor <NUM> may be inserted into the through hole <NUM> formed at a location corresponding to the PCB substrate <NUM>, and may connect a terminal of the NTC temperature sensor <NUM> and the electrode pattern of the PCB substrate <NUM>.

Furthermore, the connection pin <NUM> is inserted into the multiple through holes <NUM> that are formed in a row in the first electrode pattern a and third electrode inserted into the through hole <NUM> formed at the location adjacent to the semiconductor chip G may be inserted into a through hole <NUM> formed at a location corresponding to the PCB substrate (reference numeral <NUM> in <FIG>), and may connect the gate terminal on which the semiconductor chip G is mounted and the electrode pattern of the PCB substrate <NUM>.

Furthermore, the connection pin <NUM> is inserted into the multiple through holes <NUM> that are formed in a row in the first electrode pattern a and third electrode pattern c of the upper ceramic substrate <NUM>. The connection pin <NUM> inserted into the multiple through holes <NUM> formed in the first electrode pattern a and the third electrode pattern c may be inserted into the through hole <NUM> formed at the location corresponding to the PCB substrate <NUM>, and may connect the semiconductor chip G to the capacitor <NUM> of the PCB substrate <NUM>.

The connection pin <NUM> removes various output losses and enables high speed switching by connecting the semiconductor chip G mounted on the upper ceramic substrate <NUM> to the driving element mounted on the PCB substrate <NUM> at the shortest distance.

<FIG> is a cross-sectional view illustrating a form in which spacers have been applied between the upper ceramic substrate and the lower ceramic substrate as an embodiment of the present disclosure.

As illustrated in <FIG>, the upper ceramic substrate <NUM> is disposed over the lower ceramic substrate <NUM>. The semiconductor chip G is mounted on the lower surface of the upper ceramic substrate <NUM>. The spacers <NUM> and <NUM> are installed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

The semiconductor chip G is bonded to the lower surface of the upper ceramic substrate <NUM> through flip chip bonding. The flip chip bonding is advantageous for high-speed switching because an electrical loss and load attributable to resistance on a power transfer path are improved by shortening the power transfer path. A surface electrode of an upper surface of the semiconductor chip G may be bonded to the upper ceramic substrate <NUM> by a bonding layer <NUM>, and a lower surface of the semiconductor chip G may be bonded to the lower ceramic substrate <NUM> by a bonding layer <NUM>. The bonding layer <NUM> may be made of a solder, and the bonding layer <NUM> may be made of a solder or an Ag paste.

A Si, SiC, or GaN chip may be used as the semiconductor chip G. An AMB substrate may be used as the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM> in order to enhance heat dissipation efficiency of heat that is generated from the semiconductor chip G. The AMB substrate of the embodiment is a ceramic substrate including the ceramic bases <NUM> and <NUM> and metal layers <NUM>, <NUM> and <NUM>, <NUM> that are brazing-bonded to upper and lower surfaces of the ceramic bases <NUM> and <NUM>.

The heat sink <NUM> is bonded to the lower surface of the lower ceramic substrate <NUM> through the medium of an attachment layer <NUM>. The lower ceramic substrate <NUM> is adjacent to the semiconductor chip G, and it transfers heat that is generated from the semiconductor chip G to the heat sink <NUM> and prevents a short circuit by insulating the semiconductor chip G and the heat sink <NUM>. The attachment layer <NUM> may be made of a solder or an Ag paste.

The spacers <NUM> and <NUM> may be disposed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> in order to maintain an interval between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The spacers <NUM> and <NUM> are bonded to the upper surface of the lower ceramic substrate <NUM>, and regulate an isolation distance between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

The spacers <NUM> and <NUM> enhance heat dissipation efficiency of heat that is generated from the semiconductor chip G disposed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, by regulating the isolation distance between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The spacers <NUM> and <NUM> may include the insulating spacer <NUM> and the conductive spacer <NUM>.

The insulating spacer <NUM> is a non-conductive spacer. The insulating spacers <NUM> are used to constantly maintain the interval between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

The insulating spacer <NUM> may be bonded on the upper surface of the lower ceramic substrate <NUM> at regular intervals in a plural number, and may constantly maintain the interval between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The insulating spacer <NUM> contributes to the improvement of the lifespan of the power module and the improvement of performance thereof by protecting the semiconductor chip G against weight, an impact, etc. and preventing a short circuit, etc. by insulating the surroundings of the semiconductor chip G. The insulating spacer <NUM> may be bonded to the upper surface of the lower ceramic substrate <NUM> in a plural number by surrounding edges of the upper surface of the lower ceramic substrate <NUM>.

The insulating spacer <NUM> is made of a ceramic material. The insulating spacer <NUM> may be formed of one kind selected from Al<NUM>O<NUM>, ZTA, Si<NUM>N<NUM>, and AlN or may be formed of an alloy in which two or more of Al<NUM>O<NUM>, ZTA, Si<NUM>N<NUM>, and AlN are mixed.

One end of the insulating spacer <NUM> is brazing-bonded to the upper surface of the lower ceramic substrate <NUM>. A first bonding layer <NUM> that brazing-bonds one end of the insulating spacer <NUM> to the lower ceramic substrate <NUM> may be included. The first bonding layer <NUM> comprises Ag, Cu, The Ag, Cu, has high thermal conductivity, and facilitates the discharge of heat by transferring, to the lower ceramic substrate <NUM>, heat that is generated from the semiconductor chip G.

The first bonding layer <NUM> may be formed to a thickness of <NUM> µm to <NUM> µm. The first bonding layer <NUM> is formed of a thin film having a multi-layer structure comprising an Ag layer and a Cu layer formed on the Ag layer. The thickness of the Ag layer may be <NUM> µm, and the thickness of the Cu layer may be <NUM> µm. The first bonding layer <NUM> may be formed at one end of the insulating spacer <NUM> by using a method, such as the printing of an Ag paste or the attachment of a thin film foil, and may be brazing-bonded to the upper surface of the lower ceramic substrate <NUM>.

The first bonding layer <NUM> further includes Ti. Ti has good wettability, and increases adhesive power with one selected from Ag, Cu, and AgCu and the lower ceramic substrate <NUM>. Ti is formed at one end of the insulating spacer <NUM> by sputtering. The brazing bonding may be performed at <NUM> to <NUM>. The first bonding layer <NUM> has a thickness of <NUM> to <NUM>, which is thin and has high bonding strength to the extent that the height of the insulating spacer <NUM> is not influenced.

After one end of the insulating spacer <NUM> is brazing-bonded to the lower ceramic substrate <NUM>, the other end thereof is bonded to the upper ceramic substrate <NUM> by a second bonding layer <NUM>.

The second bonding layer <NUM> is made of a solder or an Ag paste. If one end and the other end of the insulating spacer <NUM> are brazing-bonded to the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, brazing processes need to be performed twice. Furthermore, if the brazing process is performed twice, the bending of the lower ceramic substrate <NUM> may occur. Accordingly, the other end of the insulating spacer <NUM> is bonded to the upper ceramic substrate <NUM> by the solder or the Ag paste.

The solder may be made of an SnPb-series, SnAg-series, SnAgCu-series, or Cu-series solder paste that has high bonding strength and excellent high-temperature reliability.

The Ag paste has higher high-temperature reliability and higher thermal conductivity than the solder. It is preferred that the Ag paste includes Ag powder of <NUM> to <NUM> weight% and a binder of <NUM> to <NUM> weight% so that thermal conductivity is high. It is preferred that the Ag powder is nano particles. The Ag powder of the nano particles has high bonding density due to a high surface area and high thermal conductivity.

The second bonding layer <NUM> may be formed at the other end of the insulating spacer <NUM> by using a method, such as the printing of an Ag paste or the attachment of a thin film foil, and may be heated, pressurized, and bonded to the lower surface of the upper ceramic substrate <NUM>. The heating, pressurization, and bonding using the solder may be performed at about <NUM>. The heating, pressurization, and bonding using the Ag paste may be performed at about <NUM>.

The conductive spacer <NUM> is an interconnection spacer CQC. The conductive spacer <NUM> is used if the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> are electrified. The conductive spacer <NUM> may be formed in a conductive metal block form or may be formed in a block form in which conductive metal has been coated on an external surface of an injected matter.

One end of the conductive spacer <NUM> is bonded to the lower ceramic substrate <NUM>, and the other end opposite to the one end of the conductive spacer <NUM> is bonded to the upper ceramic substrate <NUM>. The conductive spacer <NUM> is disposed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, and it directly electrically connects the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> and maintains an interval between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The conductive spacer <NUM> can increase bonding strength and improve electrical characteristics by directly connecting the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

One or more conductive spacers <NUM> may be disposed at locations adjacent to the semiconductor chip G, and can reduce a parallel burden between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

The conductive spacer <NUM> may be one selected from a Cu layer, a Mo layer, or a CuMo alloy layer or a structure in which two or more of the Cu layer, the Mo layer, and the CuMo alloy layer are mixed. For example, the conductive spacer may be a three-layer structure of Cu-CuMo-Cu. The three-layer structure of Cu-CuMo-Cu is advantageous for heat dissipation due to high thermal conductivity, and can stably maintain the interval between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> at a high temperature because the three-layer structure has a low coefficient of thermal expansion. One end of the conductive spacer <NUM> is brazing-bonded to the upper surface of the lower ceramic substrate <NUM>.

One end of the conductive spacer <NUM> may include a first bonding layer <NUM> that is brazing-bonded to the lower ceramic substrate <NUM>.

The first bonding layer <NUM> comprises Ag, Cu, The Ag, Cu, facilitate the discharge of heat by transferring, to the lower ceramic substrate <NUM>, heat that is generated from the semiconductor chip G because the Ag, Cu, and AgCu alloy have high thermal conductivity.

The first bonding layer <NUM> may be formed to a thickness of <NUM> µm to <NUM> µm. The first bonding layer <NUM> is formed of a thin film having a multi-layer structure comprising an Ag layer and a Cu layer formed on the Ag layer. The thickness of the Ag layer may be <NUM> µm, and the thickness of the Cu layer may be <NUM> µm. The first bonding layer <NUM> may be formed at one end of the conductive spacer <NUM> by using a method, such as the printing of a paste or the attachment of a thin film foil, and may be brazing-bonded to the upper surface of the lower ceramic substrate <NUM>.

The first bonding layer <NUM> further includes Ti. Ti has good wettability, and increases adhesive power between one selected from Ag, Cu, and AgCu, and the lower ceramic substrate <NUM>. The brazing bonding may be performed at <NUM> to <NUM>. The first bonding layer <NUM> has a thickness of <NUM> to <NUM>, which is thin and has high bonding strength to the extent that the height of the conductive spacer <NUM> is not influenced.

After one end of the conductive spacer <NUM> is brazing-bonded to the lower ceramic substrate <NUM>, the other end thereof is bonded to the upper ceramic substrate <NUM> by a second bonding layer <NUM>.

The second bonding layer <NUM> is made of a solder or an Ag paste. If one end and the other end of the conductive spacer <NUM> are brazing-bonded to the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, brazing processes need to be performed twice. Furthermore, if the brazing process is performed twice, the bending of the lower ceramic substrate <NUM> may occur. Accordingly, the other end of the conductive spacer <NUM> is bonded to the upper ceramic substrate <NUM> by the solder or the Ag paste.

The Ag paste has more excellent high-temperature reliability and higher thermal conductivity than the solder. It is preferred that the Ag paste includes Ag powder of <NUM> to <NUM> weight% and a binder of <NUM> to <NUM> weight% so that thermal conductivity is high. It is preferred that the Ag powder is nano particles. The Ag powder of the nano particles has high bonding density and high thermal conductivity due to a high surface area.

The second bonding layer <NUM> may be formed at the other end of the conductive spacer <NUM> by using a method, such as the printing of a paste or the attachment of a thin film foil, and may be heated, pressurized, and bonded to the lower surface of the upper ceramic substrate <NUM>. The heating, pressurization, and bonding using the solder may be performed at about <NUM>, and the heating, pressurization, and bonding using the Ag paste may be performed at about <NUM>.

<FIG> is a cross-sectional view for describing a form in which spacers are bonded between the upper ceramic substrate and the lower ceramic substrate as an embodiment of the present disclosure.

As illustrated in <FIG>, the first bonding layers <NUM> and <NUM> are formed at one ends of the insulating spacer <NUM> and the conductive spacer <NUM>, and the insulating spacer <NUM> and the conductive spacer <NUM> are brazing-bonded to the upper surface of the lower ceramic substrate <NUM> through the medium of the first bonding layers <NUM> and <NUM>. The first bonding layers <NUM> and <NUM> include the Ti layer, the Ag layer, and the Cu layer, and a boundary between the Ti layer, the Ag layer, and the Cu layer may be ambiguous after the brazing bonding. The brazing bonding may be performed at <NUM> to <NUM>.

Next, the second bonding layers <NUM> and <NUM> are formed at the other ends of the insulating spacer <NUM> and the conductive spacer <NUM> that have been brazing-bonded to the lower ceramic substrate <NUM>. The second bonding layers <NUM> and <NUM> may be a solder or an Ag paste.

When the second bonding layers <NUM> and <NUM> are formed at the other ends of the insulating spacer <NUM> and the conductive spacer <NUM>, the upper ceramic substrate <NUM> is disposed over the lower ceramic substrate <NUM>.

Next, the upper ceramic substrate <NUM> is pressurized and heated in the direction of the lower ceramic substrate <NUM>. The heating, pressurization, and bonding using the solder may be performed at about <NUM>, and the heating, pressurization, and bonding using the Ag paste may be performed at about <NUM>. Accordingly, the upper ceramic substrate <NUM> is bonded to the other ends of the insulating spacer <NUM> and the conductive spacer <NUM>, and the upper ceramic substrate <NUM> is disposed over the lower ceramic substrate <NUM> in a way to be spaced apart from the lower ceramic substrate <NUM>.

The insulating spacer <NUM> and the conductive spacer <NUM> that are installed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> protect the semiconductor chip G and prevent a short circuit. Furthermore, the conductive spacer <NUM> prevents an electrical loss and enhances heat dissipation efficiency by directly connecting the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

The aforementioned embodiment has been described as an example in which both the insulating spacer <NUM> and the conductive spacer <NUM> are installed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, but only the insulating spacer <NUM> or the conductive spacer <NUM> may be installed therebetween, if necessary. Furthermore, the structure of the first bonding layers <NUM> and <NUM> and the conductive spacer <NUM> illustrated in <FIG> merely illustrates an example, and the structure of the first bonding layers <NUM> and <NUM> and the conductive spacer <NUM> is not limited to the structure illustrated in <FIG>.

<FIG> is a cross-sectional view illustrating a form in which an insulating spacer has been applied between the upper ceramic substrate and the lower ceramic substrate as a first modified example according to an embodiment of the present disclosure.

As illustrated in <FIG>, only the insulating spacer <NUM> may be installed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The insulating spacer <NUM> can protect the semiconductor chip G against an external load and impact and prevent a short circuit, etc. through surrounding electrical insulation, by constantly maintaining an interval between the ceramic substrates <NUM> and <NUM> in the ceramic substrates <NUM> and <NUM> having an upper and lower duplex structure.

<FIG> is a cross-sectional view illustrating a form in which only the conductive spacer has been applied between the upper ceramic substrate and the lower ceramic substrate as a second modified example according to an embodiment of the present disclosure.

As illustrated in <FIG>, only the conductive spacer <NUM> may be installed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The conductive spacer <NUM> enables an electrical connection between the ceramic substrates and can improve heat dissipation efficiency because the conductive spacer <NUM> is directly bonded to the electrode patterns between the ceramic substrates <NUM> and <NUM> in the ceramic substrates <NUM> and <NUM> having an upper and lower duplex structure.

<FIG> is a cross-sectional view illustrating a form in which a non-conductive spacer and a conductive spacer have been applied between the upper ceramic substrate and the lower ceramic substrate as a third modified example according to an embodiment of the present disclosure. <FIG> has been exaggeratedly expressed unlike in actual components in order to describe a form in which the non-conductive spacer and the conductive spacer are bonded between the upper ceramic substrate and the lower ceramic substrate.

As illustrated in <FIG>, the insulating spacer <NUM> may be made of a ceramic material, and the conductive spacer <NUM> may be a Cu or Cu+CuMo alloy.

One ends of the insulating spacer <NUM> and the conductive spacer <NUM> are brazing-bonded to the upper surface of the lower ceramic substrate <NUM>, and the other ends thereof are bonded to the lower surface of the upper ceramic substrate <NUM> through the medium of the second bonding layers <NUM> and <NUM>.

The insulating spacer <NUM> is bonded along an edge of the lower ceramic substrate <NUM> at a regular interval in a plural number so that the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> maintain a regular interval in parallel. The conductive spacer <NUM> is disposed in a plural number at locations adjacent to the semiconductor chip G, thus reducing a parallel burden between the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM>.

The second bonding layers <NUM> and <NUM> are high-heat dissipation bonding layers. The high-heat dissipation bonding layer is made of a conductive high-heat dissipation paste, and facilitates, into the upper ceramic substrate <NUM>, the diffusion of heat that is generated from the semiconductor chip G. Heat dissipation efficiency can be enhanced because heat that is generated from the semiconductor chip G is easily diffused into the upper ceramic substrate <NUM> through the second bonding layers <NUM> and <NUM>.

The other ends of the insulating spacer <NUM> and the conductive spacer <NUM> may be brazing-bonded to the upper ceramic substrate <NUM>. However, since the bending of the ceramic substrate may occur upon double brazing, it is preferred that the other ends of the insulating spacer <NUM> and the conductive spacer <NUM> are heated, pressurized, and bonded to the upper ceramic substrate <NUM> by the second bonding layers <NUM> and <NUM>.

The conductive high-heat dissipation paste that forms the second bonding layers <NUM> and <NUM> may be an Ag paste. It is preferred that the Ag paste is an Ag sintering paste including Ag powder of <NUM> to <NUM> weight% and a binder of <NUM> to <NUM> weight%. The Ag paste may have increased thermal conductivity by increasing the content of Ag powder. The Ag sintering paste is sintered in a range of <NUM> to <NUM>, and it can have bonding stiffness and high heat conductivity by increasing bonding density, and has conductivity.

Meanwhile, a surface electrode of an upper surface of the semiconductor chip G is bonded to the upper ceramic substrate <NUM> by the bonding layer <NUM>. A lower surface of the semiconductor chip G is bonded to the lower ceramic substrate <NUM> by the bonding layer <NUM>.

The bonding layer <NUM> may be made of a solder. An SnPb-series, SnAg-series, SnAgCu-series, or Cu-series solder paste having high bonding strength and excellent high-temperature reliability may be used as the solder.

The bonding layer <NUM> may be made of a solder or an Ag paste. The Ag paste may be a high heat-dissipation Ag paste. The Ag paste has more excellent high-temperature reliability and higher thermal conductivity than the solder. An Ag nano powder paste may be used as the Ag paste in order to further increase thermal conductivity. The Ag nano powder paste has high bonding density and high thermal conductivity due to a high surface area. Alternatively, an Ag sintering paste including Ag powder of <NUM> to <NUM> weight% and a binder of <NUM> to <NUM> weight% may be used as the Ag paste.

If the high heat-dissipation Ag paste is applied to the second bonding layers <NUM> and <NUM> that bond the insulating spacer <NUM> and the conductive spacer <NUM> to the upper ceramic substrate <NUM> and to the bonding layer <NUM> that bonds the semiconductor chip G to the lower ceramic substrate <NUM>, heat dissipation efficiency can be enhanced by facilitating, into the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM>, the diffusion of heat that is generated from the semiconductor chip G.

The heat sink <NUM> is bonded to the lower surface of the lower ceramic substrate <NUM>. An attachment layer <NUM> that bonds the lower surface of the lower ceramic substrate <NUM> and the upper surface of the heat sink <NUM> may be further included. The attachment layer <NUM> may be made of a solder or an Ag paste.

An SnPb-series, SnAg-series, SnAgCu-series, or Cu-series solder paste having high bonding strength and excellent high-temperature reliability may be used as the solder. The Ag paste has more excellent high-temperature reliability and higher thermal conductivity than the solder. An Ag nano paste may be used as the Ag paste in order to further enhance thermal conductivity.

The lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> may include a structure in which the metal layers <NUM>, <NUM> and <NUM>, <NUM> are formed on the upper and lower surfaces of the ceramic bases <NUM> and <NUM> and the ceramic bases <NUM> and <NUM>. The metal layers <NUM> and <NUM> of the lower ceramic substrate <NUM> and the metal layers <NUM> and <NUM> of the upper ceramic substrate <NUM> may be made of metal that has electrical conductivity and high thermal conductivity, and may be made of copper or a copper alloy material, for example. The heat sink <NUM> may be made of metal having high heat dissipation efficiency, and may be made of copper, a copper alloy, or an aluminum material, for example.

<FIG> is a cross-sectional view for describing a form in which a non-conductive spacer and a conductive spacer are bonded between the upper ceramic substrate and the lower ceramic substrate as a third modified example according to an embodiment of the present disclosure. <FIG> has been exaggeratedly expressed unlike in actual components in order to describe a form in which the non-conductive spacer and the conductive spacer are bonded between the upper ceramic substrate and the lower ceramic substrate.

As illustrated in <FIG>, according to the present disclosure, after the lower ceramic substrate <NUM> is bonded to the heat sink <NUM> and the insulating spacer <NUM> and the conductive spacer <NUM> are brazing-bonded to the lower ceramic substrate <NUM>, the upper ceramic substrate <NUM> to which the semiconductor chip G has been bonded is disposed over the lower ceramic substrate <NUM>. In this state, after the second bonding layers <NUM> and <NUM> are formed at the other ends of the insulating spacer <NUM> and the conductive spacer <NUM> bonded to the lower ceramic substrate <NUM> and the bonding layer <NUM> is formed on the lower surface of the semiconductor chip G bonded to the upper ceramic substrate <NUM>, the upper ceramic substrate <NUM> may be fixed to the lower ceramic substrate <NUM> in a way to be spaced apart from the lower ceramic substrate <NUM> by pressurizing and heating the upper ceramic substrate <NUM> toward the direction of the lower ceramic substrate <NUM>.

According to the present disclosure, the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM> may have insulation or electrical conductivity by applying the insulating spacer <NUM> or the conductive spacer <NUM> to the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM>.

If the conductive spacer <NUM> is applied between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> may have a conductive high-heat dissipation characteristic by applying the Ag paste to the second bonding layers <NUM> and <NUM> and the bonding layer <NUM>. Alternatively, if the insulating spacer <NUM> is applied between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> may have a high-heat dissipation characteristic by applying the Ag paste to the second bonding layers <NUM> and <NUM> and the bonding layer <NUM>. Alternatively, if the insulating spacer <NUM> is applied between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, the Ag paste may be applied to the second bonding layers <NUM> and <NUM> and the solder may be applied to the bonding layer <NUM>.

The pressurization and bonding using the solder may be performed at about <NUM>, and the pressurization and bonding using the Ag paste may be performed at <NUM> or more.

Meanwhile, a method of manufacturing a power module, which can improve the reliability of bonding of the spacer to the lower ceramic substrate and the upper ceramic substrate and improve a thermal or mechanical impact on the ceramic substrate attributable to the bonding is described.

As illustrated in <FIG>, the method of manufacturing a power module may include a step of preparing the lower ceramic substrate, a step of preparing the upper ceramic substrate, a step of preparing spacers, a step of forming the first bonding layers <NUM> and <NUM> at one ends of the spacers <NUM> and <NUM>, a step of bonding one ends of the spacers <NUM> and <NUM> to the upper surface of the lower ceramic substrate <NUM> through the medium of the first bonding layers <NUM> and <NUM>, a step of forming the second bonding layers <NUM> and <NUM> at the other ends of the spacers <NUM> and <NUM>, and a step of bonding the upper ceramic substrate <NUM> to the other ends of the spacers <NUM> and <NUM> through the medium of the second bonding layers <NUM> and <NUM>.

In the step of preparing the lower ceramic substrate, a ceramic substrate in which the metal layers <NUM> and <NUM> have been brazing-bonded to at least one surface of the ceramic base <NUM> is prepared. For example, the AMB substrate may be prepared. The metal layers <NUM> and <NUM> may be copper foils. In the step of preparing spacers, the insulating spacer <NUM> and the conductive spacer <NUM> may be prepared.

A spacer that is formed of one kind selected from Al<NUM>O<NUM>, ZTA, Si<NUM>N<NUM>, and AlN or an alloy in which two or more of Al<NUM>O<NUM>, ZTA, Si<NUM>N<NUM>, and AlN are mixed may be prepared as the insulating spacer <NUM>. A three-layer structure spacer of Cu-CuMo-Cu in which Cu has been brazing-bonded to upper and lower surfaces of CuMo or a three-layer structure spacer of Cu-Mo-Cu in which Cu has been brazing-bonded to upper and lower surfaces of Mo may be prepared as the conductive spacer <NUM>.

In the step of preparing the upper ceramic substrate, a ceramic substrate in which the metal layers <NUM> and <NUM> have been brazing-bonded to at least one surface of the ceramic base <NUM> is prepared. For example, the AMB substrate may be prepared. The metal layers <NUM> and <NUM> may be copper foils.

In the step of forming the first bonding layers at one ends of the spacers, a Ti layer, an Ag layer, and a Cu layer, are formed at one ends of the spacers <NUM> and <NUM> by using any one of methods including sputtering, paste printing, foil attachment, and filler attachment. For example, the first bonding layers <NUM> and <NUM> each constituted with a Ti layer-Ag layer-Cu layer may be formed at one ends of the spacers <NUM> and <NUM> by forming the Ti layer at one ends of the spacers <NUM> and <NUM> as a seed layer and forming the Ag layer and the Cu layer on the Ti layer by using a sputtering method.

In the step of bonding one ends of the spacers to the upper surface of the lower ceramic substrate through the medium of the first bonding layers, one ends of the spacers may be brazing-bonded to the upper surface of the lower ceramic substrate at a temperature of <NUM> to <NUM>. It is preferred that the brazing bonding is performed in a vacuum or inert atmosphere. The temperature of <NUM> to <NUM> is a temperature at which the first bonding layers <NUM> and <NUM> are melted and the ceramic substrate is not melted.

In the step of forming the second bonding layers at the other ends of the spacers, the second bonding layers <NUM> and <NUM> may be formed by coating the solders at the other ends of the spacers <NUM> and <NUM>. In this case, in the step of bonding the upper ceramic substrate <NUM> to the other ends of the spacers <NUM> and <NUM> through the medium of the second bonding layers <NUM> and <NUM>, soldering may be performed at <NUM> to <NUM>. The solder may be made of an SnPb-series, SnAg-series, SnAgCu-series, or Cu-series solder paste.

Alternatively, in the step of forming the second bonding layers at the other ends of the spacers, the second bonding layers <NUM> and <NUM> may be formed by printing or coating the Ag paste on the other ends of the spacers <NUM> and <NUM>. In this case, in the step of bonding the upper ceramic substrate to the other ends of the spacers through the medium of the second bonding layers, sintering may be performed at <NUM> to <NUM>. The Ag paste has a good bonding property due to its high sintering density. It is preferred that Ag in the Ag paste is nano powder. Ag of <NUM>% or more is included in a total weight of the Ag paste in order to effectively improve bonding strength.

In the case of the embodiment illustrated in <FIG>, since one ends of the spacers <NUM> and <NUM> are brazing-bonded to the lower ceramic substrate <NUM>, the spacers <NUM> and <NUM> can be firmly bonded to the lower ceramic substrate <NUM>. Furthermore, the upper ceramic substrate <NUM> can be easily aligned because the upper ceramic substrate <NUM> is bonded to the other ends of the spacers <NUM> and <NUM> in the state in which one ends of the spacers <NUM> and <NUM> have been firmly bonded to the lower ceramic substrate <NUM>.

Furthermore, the spacers <NUM> and <NUM> can be bonded to the upper ceramic substrate <NUM> through one brazing and one soldering or sintering because the other ends of the spacers <NUM> and <NUM> are bonded to the upper ceramic substrate <NUM> by using the solder or the Ag paste. According to the embodiment, the breakage of the substrate attributable to a mechanical thermal impact can be prevented because brazing is not performed twice and pressurization and sintering are not performed. The breakage of the ceramic substrate attributable to heat can be prevented because soldering or sintering is performed in a range of <NUM> to <NUM> by using the solder or the nano powder Ag paste. Brazing twice may result in the bending and breakage of the substrate.

<FIG> is a cross-sectional view for describing a form in which spacers are bonded between the upper ceramic substrate and the lower ceramic substrate as another embodiment of the present disclosure.

As illustrated in <FIG>, in the step of forming the first bonding layers <NUM> and <NUM> at one ends of the spacers <NUM> and <NUM>, a Ti layer, an Ag layer, a Cu layer, are formed at one ends of the spacers <NUM> and <NUM> by using any one of methods including sputtering, paste printing, foil attachment, and filler attachment. For example, the first bonding layers <NUM> and <NUM> each constituted with a Ti layer-Ag layer-Cu layer may be formed at one ends of the spacers <NUM> and <NUM> by forming the Ti layer at one ends of the spacers <NUM> and <NUM> as a seed layer by using a sputtering method and forming the Ag layer and the Cu layer on the Ti layer by using a sputtering method.

Furthermore, in the step of forming second bonding layers <NUM>' and <NUM>' at the other ends of the spacers <NUM> and <NUM>, one layer or two or more layers selected from a Ti layer, an Ag layer, a Cu layer, and an AgCu layer may be formed at the other ends of the spacers <NUM> and <NUM> by using any one of methods including sputtering, paste printing, foil attachment, and filler attachment. For example, the first bonding layers <NUM> and <NUM> each constituted with a Ti layer-Ag layer-Cu layer may be formed at one ends of the spacers <NUM> and <NUM> by forming the Ti layer at the other ends of the spacers <NUM> and <NUM> as a seed layer by using a sputtering method and forming the Ag layer and the Cu layer on the Ti layer by using a sputtering method.

The step of bonding one ends of the spacers <NUM> and <NUM> to the upper surface of the lower ceramic substrate <NUM> through the medium of the first bonding layers <NUM> and <NUM> and the step of bonding the upper ceramic substrate <NUM> to the other ends of the spacers <NUM> and <NUM> through the medium of the second bonding layers <NUM>' and <NUM>' may be simultaneously performed, and may include performing brazing bonding at a temperature of <NUM> to <NUM>.

Another embodiment illustrated in <FIG> can contribute to increasing the reliability of a power module product due to excellent bonding reliability because one ends and the other ends of the spacers <NUM> and <NUM> are brazing-bonded to the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, respectively.

Furthermore, since the spacers <NUM> and <NUM> are bonded between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> through one brazing process, there is an advantage in that a thermal or mechanical impact on the ceramic substrate can be improved because a brazing process is simplified as one time, a resulting process time is reduced, and exposure to a high temperature environment for bonding is minimized.

<FIG> is a cross-sectional view for describing a form in which an insulating spacer is bonded between the upper ceramic substrate and the lower ceramic substrate as still another embodiment of the present disclosure.

As illustrated in <FIG>, electrical insulation and heat dissipation efficiency can be increased by disposing the insulating spacer <NUM> in the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

In this case, a method of manufacturing a power module, which can improve a thermal or mechanical impact on the ceramic substrate attributable to the bonding of the insulating spacer <NUM> to the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> and can improve bonding reliability, is described.

The method of manufacturing a power module is different in a step of forming the first bonding layers <NUM> and <NUM>' at one end of the insulating spacer <NUM>, a step of forming the second bonding layers <NUM> and <NUM>' at the other end of the insulating spacer <NUM>, and a step of bonding the second bonding layers <NUM> and <NUM>', compared to the aforementioned embodiment.

In the step of forming the first bonding layers <NUM> and <NUM>' at one end of the insulating spacer <NUM>, a Ti layer, an Ag layer, a Cu layer, are formed at one end of the insulating spacer <NUM> by using any one of methods including sputtering, paste printing, foil attachment, and filler attachment.

In the step of forming the second bonding layers <NUM> and <NUM>' at the other end of the insulating spacer <NUM>, one layer or two or more layers selected from a Ti layer, an Ag layer, a Cu layer, and an AgCu layer may be formed at the other end of the insulating spacer <NUM> by using any one of methods including sputtering, paste printing, foil attachment, and filler attachment. For example, each of the first bonding layer <NUM> and the second bonding layer <NUM>' may be constituted with a Ti layer-Ag layer-Cu layer, and a boundary between the Ti layer, the Ag layer, and the Cu layer may be ambiguous after bonding.

The step of bonding one end of the insulating spacer <NUM> to the upper surface of the lower ceramic substrate <NUM> through the medium of the first bonding layer <NUM> and the step of bonding the upper ceramic substrate <NUM> to the other end of the insulating spacer <NUM> through the medium of the second bonding layer <NUM>' may be simultaneously performed, and the bonding is brazing bonding at a temperature of <NUM> to <NUM>.

<FIG> is a cross-sectional view for describing a form in which the insulating spacer is bonded between the upper ceramic substrate and the lower ceramic substrate as still another embodiment of the present disclosure.

As illustrated in <FIG>, in a step of forming the first bonding layer <NUM>' at one end of the insulating spacer <NUM>, the first bonding layer <NUM>' may be formed by coating a solder on one end of the insulating spacer <NUM>. Furthermore, in a step of forming the second bonding layer <NUM> at the other end of the insulating spacer <NUM>, the second bonding layer <NUM> may be formed by coating a solder on the other end of the insulating spacer <NUM>. The solder may be made of an SnPb-series, SnAg-series, SnAgCu-series, or Cu-series solder paste.

Furthermore, in a step of bonding one end of the insulating spacer <NUM> to the upper surface of the lower ceramic substrate <NUM> through the medium of the first bonding layer <NUM>' and a step of bonding the upper ceramic substrate <NUM> to the other end of the insulating spacer <NUM> through the medium of the second bonding layer <NUM>, soldering may be performed at <NUM> to <NUM>.

As described above, one end and the other end of the insulating spacer <NUM> may be brazing-bonded to the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. Alternatively, one end and the other end of the insulating spacer <NUM> may be soldering-bonded to the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

Claim 1:
A power module (<NUM>) comprising:
a lower ceramic substrate (<NUM>);
an upper ceramic substrate (<NUM>) disposed over the lower ceramic substrate (<NUM>) in a way to be spaced apart from the lower ceramic substrate (<NUM>) and configured to have a semiconductor chip (G) mounted on a lower surface of the upper ceramic substrate (<NUM>);
a spacer configured to have one end bonded to the lower ceramic substrate (<NUM>) and have the other end opposite to the one end bonded to the upper ceramic substrate (<NUM>);
a first bonding layer (<NUM>, <NUM>) configured to bond the one end of the spacer to the lower ceramic substrate (<NUM>); and
a second bonding layer (<NUM>, <NUM>) configured to bond the other end of the spacer to the upper ceramic substrate (<NUM>),
wherein the first bonding layer (<NUM>, <NUM>) is formed of a thin film having a three-layer structure consisting of Ti layer, Ag layer, and Cu layer.