Patent Description:
An image sensor is a semiconductor device for converting an optical image into electrical signals. As computer and communication industries have been developed, high-performance image sensors have been increasingly demanded in various fields such as a digital camera, a camcorder, a personal communication system (PCS), a game console, a security camera, and a medical micro camera. Image sensors may be categorized as any one of charge coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. CIS is short for the CMOS image sensor. The CIS may include a plurality of pixels arranged two-dimensionally. Each of the pixels may include a photodiode (PD). The photodiode may convert incident light into an electrical signal. The plurality of pixels may be defined by a deep device isolation pattern disposed therebetween. Document <CIT> shows an example of an image sensor according to the prior art.

Embodiments of the inventive concepts may provide an image sensor capable of improving charge transfer characteristics of a unit pixel.

Embodiments of the inventive concepts may also provide an image sensor capable of increasing a charge storage capacity (or full well capacity) of a unit pixel.

In an aspect, an image sensor may include a substrate including a pixel region, the substrate extending in a first direction and a second direction intersecting the first direction; a first photoelectric conversion region and a second photoelectric conversion region which are disposed in the pixel region of the substrate and are adjacent to each other in a first direction; a deep device isolation pattern penetrating the substrate in a third direction perpendicular to the first direction and the second direction, and surrounding the pixel region, the deep device isolation pattern comprising first extensions extending in the second direction between the first photoelectric conversion region and the second photoelectric conversion region, and the first extensions spaced apart from each other in the second direction; a plurality of first transfer gate electrodes disposed on the pixel region of the substrate and vertically overlapping with the first photoelectric conversion region in the third direction; and a plurality of second transfer gate electrodes disposed on the pixel region of the substrate and vertically overlapping with the second photoelectric conversion region in the third direction. The first photoelectric conversion region may extend in the second direction under the plurality of first transfer gate electrodes.

In an aspect, an image sensor may include a substrate having a first surface and a second surface which are opposite to each other, the substrate comprising a pixel region, the substrate extending in a first direction and a second direction intersecting the first direction; a deep device isolation pattern penetrating the substrate in a third direction perpendicular to the first direction and the second direction, the deep device isolation pattern surrounding the pixel region along the first direction and the second direction; a first photoelectric conversion region and a second photoelectric conversion region which are disposed in the pixel region of the substrate and are adjacent to each other in the first direction, the deep device isolation pattern comprising first extensions extending in the second direction between the first photoelectric conversion region and the second photoelectric conversion region, and the first extensions spaced apart from each other in the second direction; a plurality of first transfer gate electrodes disposed on the pixel region of the substrate and on the first photoelectric conversion region; and a plurality of second transfer gate electrodes disposed on the pixel region of the substrate and on the second photoelectric conversion region. The first photoelectric conversion region may extend in the second direction from a side of one of the first extensions to a side of another of the first extensions. The second photoelectric conversion region may extend in the second direction from another side of the one of the first extensions to another side of the another of the first extensions.

Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings.

<FIG> is a block diagram schematically illustrating an image sensor according to some embodiments of the inventive concepts.

Referring to <FIG>, an image sensor may include an active pixel sensor array <NUM>, a row decoder <NUM>, a row driver <NUM>, a column decoder <NUM>, a timing generator <NUM>, a correlated double sampler (CDS) <NUM>, an analog-to-digital converter (ADC) <NUM>, and an input/output (I/O) buffer <NUM>.

The active pixel sensor array <NUM> may include a plurality of pixels arranged two-dimensionally and may convert optical signals into electrical signals. A pixel, or unit pixel refers to a sensor element of an image sensor, and may refer to a smallest addressable light-sensing element of the image sensor. The active pixel sensor array <NUM> may be driven by a plurality of driving signals (e.g., a pixel selection signal, a reset signal, and a charge transfer signal) provided from the row driver <NUM>. In addition, the electrical signals converted by the active pixel sensor array <NUM> may be provided to the correlated double sampler <NUM>.

The row driver <NUM> may provide the plurality of driving signals for driving the plurality of pixels to the active pixel sensor array <NUM> in response to signals decoded in the row decoder <NUM>. When the pixels are arranged in a matrix form, the driving signals may be provided in the unit of row of the matrix form.

The timing generator <NUM> may provide timing signals and control signals to the row decoder <NUM> and the column decoder <NUM>.

The correlated double sampler (CDS) <NUM> may receive electrical signals generated from the active pixel sensor array <NUM> and may hold and sample the received electrical signals. The correlated double sampler <NUM> may doubly sample a specific noise level and a signal level of the electrical signal and may output a difference level corresponding to a difference between the noise level and the signal level.

The analog-to-digital converter (ADC) <NUM> may convert an analog signal, which corresponds to the difference level outputted from the correlated double sampler <NUM>, into a digital signal and may output the digital signal.

The I/O buffer <NUM> may latch the digital signals and may sequentially output the latched signals to an image signal processing unit (not shown) in response to signals decoded in the column decoder <NUM>.

<FIG> is a circuit diagram illustrating a unit pixel of an image sensor according to some embodiments of the inventive concepts.

Referring to <FIG> and <FIG>, the active pixel sensor array <NUM> may include a plurality of pixels PX, and the pixels PX may be arranged in a matrix form. Each of the pixels PX may include a first photoelectric conversion element PD1, a second photoelectric conversion element PD2, a first transfer transistor TX1, a second transfer transistor TX2, and logic transistors RX, SX and DX. The logic transistors RX, SX and DX may include a reset transistor RX, a selection transistor SX, and a drive transistor DX. The first transfer transistor TX1, the second transfer transistor TX2, the reset transistor RX and the selection transistor SX may include a first transfer gate TG1, a second transfer gate TG2, a reset gate RG and a selection gate SG, respectively. Each of the pixels PX may further include a floating diffusion region FD.

The first and second photoelectric conversion elements PD1 and PD2 may generate and accumulate photocharges (or charges) in proportion to the amount of light incident from the outside. The first and second photoelectric conversion elements PD1 and PD2 may be photodiodes, each of which includes a P-type dopant region and an N-type dopant region. The first transfer transistor TX1 may transfer charges generated from the first photoelectric conversion element PD1 into the floating diffusion region FD, and the second transfer transistor TX2 may transfer charges generated from the second photoelectric conversion element PD2 into the floating diffusion region FD.

The floating diffusion region FD may receive charges generated from the first and second photoelectric conversion elements PD1 and PD2 and may cumulatively store the received charges. The drive transistor DX may be controlled according to the amount of charges accumulated in the floating diffusion region FD.

The reset transistor RX may periodically reset the charges accumulated in the floating diffusion region FD. A drain electrode of the reset transistor RX may be connected to the floating diffusion region FD, and a source electrode of the reset transistor RX may be connected to a power voltage VDD. When the reset transistor RX is turned-on, the power voltage VDD connected to the source electrode of the reset transistor RX may be applied to the floating diffusion region FD. Thus, when the reset transistor RX is turned-on, the charges accumulated in the floating diffusion region FD may be discharged to reset the floating diffusion region FD. It will be understood that when an element is referred to as being "connected" or "coupled" to or "on" another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or as "contacting" or "in contact with" another element, there are no intervening elements present at the point of contact.

The drive transistor DX may function as a source follower buffer amplifier. The drive transistor DX may amplify a potential change in the floating diffusion region FD and may output the amplified potential change to an output line Vout.

The selection transistor SX may select the pixels PX to be read in the unit of row. When the selection transistor SX is turned-on, the power voltage VDD may be applied to a drain electrode of the drive transistor DX.

The pixel PX including two photoelectric conversion elements PD <NUM> and PD2 and five transistors TX1, TX2, RX, DX and SX is illustrated as an example in <FIG>, but embodiments of the inventive concepts are not limited thereto. In certain embodiments, the reset transistor RX, the drive transistor DX and/or the selection transistor SX may be shared by adjacent pixels PX. Thus, an integration density of the image sensor may be improved.

<FIG> is a plan view illustrating an image sensor according to some embodiments of the inventive concepts, and <FIG> is a plan view in which some components of <FIG> are omitted. <FIG> and <FIG> are cross-sectional views taken along lines A-A' and B-B' of <FIG>, respectively.

Referring to <FIG>, <FIG>, <FIG> and <FIG>, an image sensor may include a photoelectric conversion layer <NUM>, an interconnection layer <NUM>, and a light transmitting layer <NUM>. The light transmitting layer <NUM> may also be referred to as an optical conversion layer or an optical processing layer. The photoelectric conversion layer <NUM> may be disposed between the interconnection layer <NUM> and the light transmitting layer <NUM>.

The photoelectric conversion layer <NUM> may include a substrate <NUM>, and the substrate <NUM> may include a plurality of pixel regions PXR. The substrate <NUM> may be a semiconductor substrate (e.g., a silicon substrate, a germanium substrate, a silicon-germanium substrate, a group II-VI compound semiconductor substrate, or a group III-V compound semiconductor substrate) or a silicon-on-insulator (SOI) substrate. The substrate <NUM> may have a first surface 100a and a second surface 100b, which are opposite to each other. The plurality of pixel regions PXR may be two-dimensionally arranged in a first direction D1 and a second direction D2, which are parallel to the first surface 100a of the substrate <NUM>. The first direction D1 and the second direction D2 may intersect each other.

The photoelectric conversion layer <NUM> may further include a deep device isolation pattern <NUM> which penetrates the substrate <NUM> and is disposed between the plurality of pixel regions PXR. The deep device isolation pattern <NUM> may penetrate the substrate <NUM> in a third direction D3 perpendicular to the first surface 100a of the substrate <NUM>. The deep device isolation pattern <NUM> may extend from the first surface 100a of the substrate <NUM> toward the second surface 100b of the substrate <NUM>. The first surface 100a of the substrate <NUM> may expose a top surface 150U of the deep device isolation pattern <NUM>, and the second surface 100b of the substrate <NUM> may expose a bottom surface <NUM> of the deep device isolation pattern <NUM>. The top surface 150U of the deep device isolation pattern <NUM> may be substantially coplanar with the first surface 100a of the substrate <NUM>, and the bottom surface <NUM> of the deep device isolation pattern <NUM> may be substantially coplanar with the second surface 100b of the substrate <NUM>. The deep device isolation pattern <NUM> may prevent cross-talk between the pixel regions PXR adjacent to each other. Terms such as "same," "equal," "planar," or "coplanar," as used herein encompass identicality or near identicality including variations that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.

The deep device isolation pattern <NUM> may surround each of the plurality of pixel regions PXR when viewed in a plan view. The deep device isolation pattern <NUM> may extend in the first direction D1 and the second direction D2 to surround each of the pixel regions PXR. The deep device isolation pattern <NUM> may include first extensions 150P1 extending into each of the pixel regions PXR along the second direction D2. The first extensions 150P1 may be spaced apart from each other in the second direction D2 in each of the pixel regions PXR. A length L1, in the second direction D2, of each of the first extensions 150P1 may be greater than a distance DS1 in the second direction D2 between the first extensions 150P1. For example, the first extensions 150P1 may be spaced apart from each other in the second direction D2 in each of the pixel regions PXR by the distance DS1.

The deep device isolation pattern <NUM> may include a semiconductor pattern <NUM> and <NUM> penetrating at least a portion of the substrate <NUM>, a filling insulation pattern <NUM> on the semiconductor pattern <NUM> and <NUM>, and a side insulating pattern <NUM> disposed between the semiconductor pattern <NUM> and <NUM> and the substrate <NUM>. The side insulating pattern <NUM> may extend from a side surface of the semiconductor pattern <NUM> and <NUM> onto a side surface of the filling insulation pattern <NUM>. The semiconductor pattern <NUM> and <NUM> may include a first semiconductor pattern <NUM> penetrating at least a portion of the substrate <NUM>, and a second semiconductor pattern <NUM> between the first semiconductor pattern <NUM> and the side insulating pattern <NUM>. The first semiconductor pattern <NUM> may cover a topmost surface of the second semiconductor pattern <NUM> and may be in contact with the side insulating pattern <NUM>. The filling insulation pattern <NUM> may be disposed on the first semiconductor pattern <NUM>. The first semiconductor pattern <NUM> may extend between the filling insulation pattern <NUM> and the second semiconductor pattern <NUM> and may be in contact with the side insulating pattern <NUM>.

Each of the first semiconductor pattern <NUM> and the second semiconductor pattern <NUM> may include a semiconductor material doped with dopants. The dopants may have a P-type or an N-type. For example, each of the first semiconductor pattern <NUM> and the second semiconductor pattern <NUM> may include poly-silicon doped with boron. For example, each of the side insulating pattern <NUM> and the filling insulation pattern <NUM> may include or may be formed of silicon oxide, silicon nitride, and/or silicon oxynitride.

A first photoelectric conversion region 110a and a second photoelectric conversion region 110b may be disposed in each of the pixel regions PXR and may be adjacent to each other in the first direction D1 in each of the pixel regions PXR. The first extensions 150P1 of the deep device isolation pattern <NUM> may be disposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. The first extensions 150P1 may extend in the second direction D2 between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b and may be spaced apart from each other in the second direction D2. The first photoelectric conversion region 110a may extend in the second direction D2 at one side of the first extensions 150P1, and the second photoelectric conversion region 110b may extend in the second direction D2 at another side of the first extensions 150P1. For example, the first photoelectric conversion region 110a may continuously extend in the second direction D2 from one side of one of the first extensions 150P1 to one side of another of the first extensions 150P1, and the second photoelectric conversion region 110b may continuously extend in the second direction D2 from another side of the one of the first extensions 150P1 to another side of the other of the first extensions 150P1.

The substrate <NUM> may have a first conductivity type, and the first and second photoelectric conversion regions 110a and 110b may be regions doped with dopants having a second conductivity type different from the first conductivity type. For example, the first conductivity type and the second conductivity type may be a P-type and an N-type, respectively. In this case, the dopants having the second conductivity type may include N-type dopants such as phosphorus, arsenic, bismuth, and/or antimony. Each of the first and second photoelectric conversion regions 110a and 110b may form a PN junction with the substrate <NUM> to constitute a photodiode. For example, the first photoelectric conversion region 110a may form the PN junction with the substrate <NUM> to constitute the first photodiode (PD1 of <FIG>), and the second photoelectric conversion region 110b may form the PN junction with the substrate <NUM> to constitute the second photodiode (PD2 of <FIG>). Each of the pixel regions PXR may correspond to the unit pixel (PX of <FIG>) including the first photodiode (PD1 of <FIG>) and the second photodiode (PD2 of <FIG>). In some embodiments, the semiconductor pattern <NUM> and <NUM> of the deep device isolation pattern <NUM> may include a semiconductor material doped with dopants having the first conductivity type (e.g., P-type dopants).

A shallow device isolation pattern <NUM> may be disposed adjacent to the first surface 100a of the substrate <NUM>. Each of the plurality of pixel regions PXR may include active patterns ACT defined by the shallow device isolation pattern <NUM>. For example, the shallow device isolation pattern <NUM> may include or may be formed of at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The active patterns ACT may be spaced apart from each other in each of the pixel regions PXR, and the shallow device isolation pattern <NUM> may be disposed between the active patterns ACT. The deep device isolation pattern <NUM> may penetrate the shallow device isolation pattern <NUM> and may extend into the substrate <NUM>. Each of the first extensions 150P1 of the deep device isolation pattern <NUM> may penetrate the shallow device isolation pattern <NUM> and may extend into each of the pixel regions PXR. A first set of the active patterns ACT may vertically overlap with the first photoelectric conversion region 110a (e.g., in the third direction D3), and a second set of the active patterns ACT may vertically overlap with the second photoelectric conversion region 110b (e.g., in the third direction D3). Each of the first extensions 150P1 may extend between corresponding active patterns ACT of the active patterns ACT.

The filling insulation pattern <NUM> of the deep device isolation pattern <NUM> may be disposed in the shallow device isolation pattern <NUM>. The filling insulation pattern <NUM> may penetrate the shallow device isolation pattern <NUM> and may be in contact with the semiconductor pattern <NUM> and <NUM>. For example, the filling insulation pattern <NUM> may penetrate the shallow device isolation pattern <NUM> and may contact the first semiconductor pattern <NUM>. The side insulating pattern <NUM> of the deep device isolation pattern <NUM> may extend between the shallow device isolation pattern <NUM> and the filling insulation pattern <NUM>.

A plurality of first transfer gate electrodes TG1, a first floating diffusion region FD1, a plurality of second transfer gate electrodes TG2 and a second floating diffusion region FD2 may be disposed on each of the pixel regions PXR and may be disposed adjacent to the first surface 100a of the substrate <NUM>. The first transfer gate electrodes TG1 and the first floating diffusion region FD1 may be disposed on a corresponding active pattern ACT of the active patterns ACT and may vertically overlap with the first photoelectric conversion region 110a (e.g., in the third direction D3). The first photoelectric conversion region 110a may continuously extend in the second direction D2 under the first transfer gate electrodes TG1 and the first floating diffusion region FD1. The second transfer gate electrodes TG2 and the second floating diffusion region FD2 may be disposed on a corresponding active pattern ACT of the active patterns ACT and may vertically overlap with the second photoelectric conversion region 110b (e.g., in the third direction D3). The second photoelectric conversion region 110b may continuously extend in the second direction D2 under the second transfer gate electrodes TG2 and the second floating diffusion region FD2. Spatially relative terms, such as "under," "below," "lower," "above," "upper" and the like, may be used herein for ease of description to describe positional relationships, such as illustrated in the figures, e.g. It will be understood that the spatially relative terms encompass different orientations of the device in addition to the orientation depicted in the figures.

The first floating diffusion region FD1 and the second floating diffusion region FD2 may be spaced apart from each other in the first direction D1 with one of the first extensions 150P1 of the deep device isolation pattern <NUM> interposed therebetween. The first transfer gate electrodes TG1 may be disposed adjacent to the first floating diffusion region FD1, and the second transfer gate electrodes TG2 may be disposed adjacent to the second floating diffusion region FD2. In some embodiments, the second transfer gate electrodes TG2 may be spaced apart from the first transfer gate electrodes TG1 in the first direction D1 with the one of the first extensions 150P1 interposed therebetween.

A lower portion of each of the first transfer gate electrodes TG1 may extend into the substrate <NUM> (e.g., in the third direction D3) toward the first photoelectric conversion region 110a, and an upper portion of each of the first transfer gate electrodes TG1 may protrude above a top surface of the corresponding active pattern ACT (i.e., the first surface 100a of the substrate <NUM>). A lower portion of each of the second transfer gate electrodes TG2 may extend into the substrate <NUM> (e.g., in the third direction D3) toward the second photoelectric conversion region 110b, and an upper portion of each of the second transfer gate electrodes TG2 may protrude above a top surface of the corresponding active pattern ACT (i.e., the first surface 100a of the substrate <NUM>). The first floating diffusion region FD1 and the second floating diffusion region FD2 may be regions doped with dopants (e.g., N-type dopants) having the second conductivity type different from the first conductivity type of the substrate <NUM>.

The first transfer gate electrodes TG1 and the first floating diffusion region FD <NUM> may constitute the first transfer transistor TX1 of <FIG>. The second transfer gate electrodes TG2 and the second floating diffusion region FD2 may constitute the second transfer transistor TX2 of <FIG>.

A first gate dielectric pattern GI1 may be disposed between each of the first transfer gate electrodes TG1 and the substrate <NUM> (i.e., the corresponding active pattern ACT), and a second gate dielectric pattern GI2 may be disposed between each of the second transfer gate electrodes TG2 and the substrate <NUM> (i.e., the corresponding active pattern ACT).

A plurality of gate electrodes GE and source/drain regions SD may be disposed on each of the pixel regions PXR and may be disposed adjacent to the first surface 100a of the substrate <NUM>. The gate electrodes GE and the source/drain regions SD may be disposed on corresponding active patterns ACT of the active patterns ACT and may vertically overlap with the first photoelectric conversion region 110a or the second photoelectric conversion region 110b (e.g., in the third direction D3). For example, the source/drain regions SD may be regions doped with dopants (e.g., N-type dopants) having the second conductivity type different from the first conductivity type of the substrate <NUM>. The gate electrodes GE and the source/drain regions SD may constitute the drive transistor DX, the selection transistor SX and the reset transistor RX of <FIG>. A gate dielectric pattern GI may be disposed between each of the gate electrodes GE and the substrate <NUM> (i.e., the corresponding active pattern ACT).

The interconnection layer <NUM> may be disposed on the first surface 100a of the substrate <NUM>. The interconnection layer <NUM> may include a first interlayer insulating layer <NUM> and a second interlayer insulating layer <NUM>, which are sequentially stacked on the first surface 100a of the substrate <NUM>. The first interlayer insulating layer <NUM> may be disposed on the first surface 100a of the substrate <NUM> to cover the first and second transfer gate electrodes TG1 and TG2 and the gate electrodes GE. The interconnection layer <NUM> may further include contact plugs <NUM> connected to the first and second transfer gate electrodes TG1 and TG2, the gate electrodes GE, the first and second floating diffusion regions FD1 and FD2 and the source/drain regions SD, and conductive lines <NUM> connected to the contact plugs <NUM>. The contact plugs <NUM> may penetrate the first interlayer insulating layer <NUM> so as to be connected to the first and second transfer gate electrodes TG1 and TG2, the gate electrodes GE, the first and second floating diffusion regions FD1 and FD2, and the source/drain regions SD. The conductive lines <NUM> may be disposed in the second interlayer insulating layer <NUM>. At least some of the contact plugs <NUM> may extend into the second interlayer insulating layer <NUM> so as to be connected to the conductive lines <NUM>. The first interlayer insulating layer <NUM> and the second interlayer insulating layer <NUM> may include an insulating material, and the contact plugs <NUM> and the conductive lines <NUM> may include a conductive material.

The light transmitting layer <NUM> may be disposed on the second surface 100b of the substrate <NUM>. The light transmitting layer <NUM> may include a color filter array <NUM> and a micro lens array <NUM>, which are disposed on the second surface 100b of the substrate <NUM>. The color filter array <NUM> may be disposed between the second surface 100b of the substrate <NUM> and the micro lens array <NUM>. The light transmitting layer <NUM> may concentrate and filter light incident from the outside and may provide the light to the photoelectric conversion layer <NUM>.

The color filter array <NUM> may include a plurality of color filters <NUM> disposed on the plurality of pixel regions PXR, respectively. Each of the color filters <NUM> may be disposed on each of the pixel regions PXR and may vertically overlap with the first and second photoelectric conversion regions 110a and 110b of each of the pixel regions PXR (e.g., in the third direction D3). The micro lens array <NUM> may include a plurality of micro lenses <NUM> disposed on the plurality of color filters <NUM>, respectively. Each of the micro lenses <NUM> may be disposed on each of the pixel regions PXR and may vertically overlap with the first and second photoelectric conversion regions 110a and 110b of each of the pixel regions PXR (e.g., in the third direction D3).

An anti-reflection layer <NUM> may be disposed between the second surface 100b of the substrate <NUM> and the color filter array <NUM>. The anti-reflection layer <NUM> may prevent reflection of light incident to the second surface 100b of the substrate <NUM> to allow the light to smoothly reach the first and second photoelectric conversion regions 110a and 110b. A first insulating layer <NUM> may be disposed between the anti-reflection layer <NUM> and the color filter array <NUM>, and a second insulating layer <NUM> may be disposed between the color filter array <NUM> and the micro lens array <NUM>.

According to embodiments of the inventive concepts, each of the pixel regions PXR may include the first photoelectric conversion region 110a and the second photoelectric conversion region 110b which are adjacent to each other in the first direction D1, and the deep device isolation pattern <NUM> may include the first extensions 150P1 disposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. In this case, each of the pixel regions PXR may include two photodiodes formed by the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, and thus a charge storage capacity (or full well capacity) of each of the pixel regions PXR may be increased. In addition, the plurality of first transfer gate electrodes TG1 may be disposed on the first photoelectric conversion region 110a to electrically connect the first photoelectric conversion region 110a to the first floating diffusion region FD1, and the plurality of second transfer gate electrodes TG2 may be disposed on the second photoelectric conversion region 110b to electrically connect the second photoelectric conversion region 110b to the second floating diffusion region FD2. Since at least two first transfer gate electrodes TG1 are disposed on the first photoelectric conversion region 110a and at least two second transfer gate electrodes TG2 are disposed on the second photoelectric conversion region 110b, charge transfer characteristics of each of the pixel regions PXR may be improved.

As a result, it is possible to provide the image sensor capable of improving the charge transfer characteristics and the charge storage capacity (or full well capacity) of the unit pixel.

<FIG> is a plan view illustrating an image sensor according to some embodiments of the inventive concepts, and <FIG> is a plan view in which some components of <FIG> are omitted. <FIG>, <FIG>, <FIG> and <FIG> are cross-sectional views taken along lines A-A', B-B', C-C' and D-D' of <FIG>, respectively. Hereinafter, differences between the present embodiments and the above embodiments of <FIG>, <FIG>, <FIG> and <FIG> will be mainly described for the purpose of ease and convenience in explanation.

Referring to <FIG>, <FIG> and <FIG>, the deep device isolation pattern <NUM> may further include second extensions 150P2 extending into each of the pixel regions PXR in the first direction D1. The second extensions 150P2 may be spaced apart from each other in the first direction D1 in each of the pixel regions PXR. A length L2, in the first direction D1, of each of the second extensions 150P2 may be equal to or less than the length L1, in the second direction D2, of each of the first extensions 150P1.

One of the second extensions 150P2 may extend into the first photoelectric conversion region 110a in the first direction D1, and another of the second extensions 150P2 may extend into the second photoelectric conversion region 110b in an opposite direction to the first direction D1. The one of the second extensions 150P2 may be disposed between a first portion 110a1 and a second portion 110a2 of the first photoelectric conversion region 110a, and the other of the second extensions 150P2 may be disposed between a third portion 110b1 and a fourth portion 110b2 of the second photoelectric conversion region 110b. The first photoelectric conversion region 110a may continuously extend in the second direction D2 between the second extensions 150P2. For example, the first portion 110a1 and the second portion 110a2 of the first photoelectric conversion region 110a may be continuously connected to each other between the second extensions 150P2. The second photoelectric conversion region 110b may continuously extend in the second direction D2 between the second extensions 150P2. For example, the third portion 110b1 and the fourth portion 110b2 of the second photoelectric conversion region 110b may be continuously connected to each other between the second extensions 150P2.

The active patterns ACT may be spaced apart from each other in each of the pixel regions PXR, and the shallow device isolation pattern <NUM> may be disposed between the active patterns ACT. The deep device isolation pattern <NUM> may penetrate the shallow device isolation pattern <NUM> and may extend into the substrate <NUM>. Each of the first extensions 150P1 of the deep device isolation pattern <NUM> may penetrate the shallow device isolation pattern <NUM> and may extend into each of the pixel regions PXR, and each of the second extensions 150P2 of the deep device isolation pattern <NUM> may penetrate the shallow device isolation pattern <NUM> and may extend into each of the pixel regions PXR. At least one of the active patterns ACT may be disposed between the first extensions 150P1 and between the second extensions 150P2. The other active patterns ACT may vertically overlap with the first portion 110a1 and the second portion 110a2 of the first photoelectric conversion region 110a and the third portion 110b1 and the fourth portion 110b2 of the second photoelectric conversion region 110b (e.g., in the third direction D3), respectively.

A plurality of first transfer gate electrodes TG1, a floating diffusion region FD and a plurality of second transfer gate electrodes TG2 may be disposed on each of the pixel regions PXR and may be disposed adjacent to the first surface 100a of the substrate <NUM>. The floating diffusion region FD may be disposed in a corresponding active pattern ACT between the first extensions 150P1 and between the second extensions 150P2. The first transfer gate electrodes TG1 and the second transfer gate electrodes TG2 may be disposed adjacent to the floating diffusion region FD and may be disposed on the corresponding active pattern ACT.

The first transfer gate electrodes TG1 may vertically overlap with the first photoelectric conversion region 110a (e.g., in the third direction D3). One of the first transfer gate electrodes TG1 may vertically overlap with the first portion 110a1 of the first photoelectric conversion region 110a (e.g., in the third direction D3) and may electrically connect the first portion 110a1 of the first photoelectric conversion region 110a to the floating diffusion region FD. Another of the first transfer gate electrodes TG1 may vertically overlap with the second portion 110a2 of the first photoelectric conversion region 110a (e.g., in the third direction D3) and may electrically connect the second portion 110a2 of the first photoelectric conversion region 110a to the floating diffusion region FD. The first transfer gate electrodes TG1 and the floating diffusion region FD may constitute the first transfer transistor TX1 of <FIG>. The first portion 110a1 and the second portion 110a2 of the first photoelectric conversion region 110a may be continuously connected to each other in the second direction D2 under the first transfer gate electrodes TG1. For example, the first photoelectric conversion region 110a may continuously extend in the second direction D2 under the first transfer gate electrodes TG1.

The second transfer gate electrodes TG2 may vertically overlap with the second photoelectric conversion region 110b (e.g., in the third direction D3). One of the second transfer gate electrodes TG2 may vertically overlap with the third portion 110b1 of the second photoelectric conversion region 110b (e.g., in the third direction D3) and may electrically connect the third portion 110b1 of the second photoelectric conversion region 110b to the floating diffusion region FD. Another of the second transfer gate electrodes TG2 may vertically overlap with the fourth portion 110b2 of the second photoelectric conversion region 110b (e.g., in the third direction D3) and may electrically connect the fourth portion 110b2 of the second photoelectric conversion region 110b to the floating diffusion region FD. The second transfer gate electrodes TG2 and the floating diffusion region FD may constitute the second transfer transistor TX2 of <FIG>. The third portion 110b1 and the fourth portion 110b2 of the second photoelectric conversion region 110b may be continuously connected to each other in the second direction D2 under the second transfer gate electrodes TG2. For example, the second photoelectric conversion region 110b may continuously extend in the second direction D2 under the second transfer gate electrodes TG2.

Except for the above differences, other components and/or features of the image sensor according to the present embodiments may be substantially the same as corresponding components and/or features of the image sensor described with reference to <FIG>, <FIG>, <FIG> and <FIG>.

According to the present embodiments, each of the pixel regions PXR may include the first photoelectric conversion region 110a and the second photoelectric conversion region 110b which are adjacent to each other in the first direction D1, and the deep device isolation pattern <NUM> may include the first extensions 150P1 disposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, and the second extensions 150P2 extending into the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, respectively. In this case, each of the pixel regions PXR may include four photodiodes formed by the first portion 110a1 and the second portion 110a2 of the first photoelectric conversion region 110a and the third portion 110b1 and the fourth portion 110b2 of the second photoelectric conversion region 110b, and thus a charge storage capacity (or full well capacity) of each of the pixel regions PXR may be increased. In addition, the plurality of first transfer gate electrodes TG1 may be disposed on the first photoelectric conversion region 110a to electrically connect the first photoelectric conversion region 110a to the floating diffusion region FD, and the plurality of second transfer gate electrodes TG2 may be disposed on the second photoelectric conversion region 110b to electrically connect the second photoelectric conversion region 110b to the floating diffusion region FD. Since at least two first transfer gate electrodes TG1 are disposed on the first photoelectric conversion region 110a and at least two second transfer gate electrodes TG2 are disposed on the second photoelectric conversion region 110b, charge transfer characteristics of each of the pixel regions PXR may be improved.

<FIG> is a plan view illustrating an image sensor according to some embodiments of the inventive concepts, and <FIG> is a plan view in which some components of <FIG> are omitted. <FIG> is a cross-sectional view taken along a line C-C' of <FIG>. Cross-sectional views taken along lines A-A', B-B' and D-D' of <FIG> are substantially the same as <FIG>, <FIG> and <FIG>, respectively. Hereinafter, differences between the present embodiments and the above embodiments of <FIG>, <FIG> and <FIG> will be mainly described for the purpose of ease and convenience in explanation.

Referring to <FIG>, <FIG> and <FIG>, the first transfer gate electrodes TG1 may vertically overlap with the first photoelectric conversion region 110a (e.g., in the third direction D3). Each of the first transfer gate electrodes TG1 may electrically connect the first photoelectric conversion region 110a to the floating diffusion region FD. In some embodiments, three first transfer gate electrodes TG1 may be disposed on the first photoelectric conversion region 110a and may electrically connect the first photoelectric conversion region 110a to the floating diffusion region FD. The first transfer gate electrodes TG1 and the floating diffusion region FD may constitute the first transfer transistor TX1 of <FIG>. The first photoelectric conversion region 110a may continuously extend in the second direction D2 under the first transfer gate electrodes TG1.

The second transfer gate electrodes TG2 may vertically overlap with the second photoelectric conversion region 110b (e.g., in the third direction D3). Each of the second transfer gate electrodes TG2 may electrically connect the second photoelectric conversion region 110b to the floating diffusion region FD. In some embodiments, three second transfer gate electrodes TG2 may be disposed on the second photoelectric conversion region 110b and may electrically connect the second photoelectric conversion region 110b to the floating diffusion region FD. The second transfer gate electrodes TG2 and the floating diffusion region FD may constitute the second transfer transistor TX2 of <FIG>. The second photoelectric conversion region 110b may continuously extend in the second direction D2 under the second transfer gate electrodes TG2.

Except for the above differences, other components and/or features of the image sensor according to the present embodiments may be substantially the same as corresponding components and/or features of the image sensor described with reference to <FIG>, <FIG> and <FIG>.

<FIG> and <FIG> are cross-sectional views corresponding to the line C-C' of <FIG> to illustrate image sensors according to some embodiments of the inventive concepts.

Referring to <FIG>, <FIG> and <FIG>, a lower portion of each of the first transfer gate electrodes TG1 may extend into the substrate <NUM> toward the first photoelectric conversion region 110a, and an upper portion of each of the first transfer gate electrodes TG1 may protrude above a top surface of a corresponding active pattern ACT (i.e., the first surface 100a of the substrate <NUM>). In some embodiments, the upper portions of adjacent first transfer gate electrodes TG1 of the first transfer gate electrodes TG1 may be connected to each other. For example, as illustrated in <FIG>, the upper portion of one of the first transfer gate electrodes TG1 may be spaced apart from the upper portions of the other first transfer gate electrodes TG1, and the upper portions of the other first transfer gate electrodes TG1 may be connected to each other. In certain embodiments, as illustrated in <FIG>, the upper portions of all of the first transfer gate electrodes TG1 may be connected to each other.

A lower portion of each of the second transfer gate electrodes TG2 may extend into the substrate <NUM> toward the second photoelectric conversion region 110b, and an upper portion of each of the second transfer gate electrodes TG2 may protrude above a top surface of a corresponding active pattern ACT (i.e., the first surface 100a of the substrate <NUM>). In some embodiments, the upper portions of adjacent second transfer gate electrodes TG2 of the second transfer gate electrodes TG2 may be connected to each other. For example, similarly to <FIG>, the upper portion of one of the second transfer gate electrodes TG2 may be spaced apart from the upper portions of the other second transfer gate electrodes TG2, and the upper portions of the other second transfer gate electrodes TG2 may be connected to each other. In certain embodiments, similarly to <FIG>, the upper portions of all of the second transfer gate electrodes TG2 may be connected to each other.

Referring to <FIG>, <FIG> and <FIG>, the first transfer gate electrodes TG1 may vertically overlap with the first photoelectric conversion region 110a (e.g., in the third direction D3). Each of the first transfer gate electrodes TG1 may electrically connect the first photoelectric conversion region 110a to the floating diffusion region FD. In some embodiments, four first transfer gate electrodes TG1 may be disposed on the first photoelectric conversion region 110a and may electrically connect the first photoelectric conversion region 110a to the floating diffusion region FD. The first transfer gate electrodes TG1 and the floating diffusion region FD may constitute the first transfer transistor TX1 of <FIG>. The first photoelectric conversion region 110a may continuously extend in the second direction D2 under the first transfer gate electrodes TG1.

The second transfer gate electrodes TG2 may vertically overlap with the second photoelectric conversion region 110b (e.g., in the third direction D3). Each of the second transfer gate electrodes TG2 may electrically connect the second photoelectric conversion region 110b to the floating diffusion region FD. In some embodiments, four second transfer gate electrodes TG2 may be disposed on the second photoelectric conversion region 110b and may electrically connect the second photoelectric conversion region 110b to the floating diffusion region FD. The second transfer gate electrodes TG2 and the floating diffusion region FD may constitute the second transfer transistor TX2 of <FIG>. The second photoelectric conversion region 110b may continuously extend in the second direction D2 under the second transfer gate electrodes TG2.

Referring to <FIG>, <FIG> and <FIG>, a lower portion of each of the first transfer gate electrodes TG1 may extend into the substrate <NUM> toward the first photoelectric conversion region 110a, and an upper portion of each of the first transfer gate electrodes TG1 may protrude above a top surface of a corresponding active pattern ACT (i.e., the first surface 100a of the substrate <NUM>). In some embodiments, the upper portions of adjacent first transfer gate electrodes TG1 of the first transfer gate electrodes TG1 may be connected to each other. For example, as illustrated in <FIG>, the upper portions of a pair of first transfer gate electrodes TG1 of the first transfer gate electrodes TG1 may be connected to each other, and the upper portions of another pair of first transfer gate electrodes TG1 of the first transfer gate electrodes TG1 may be connected to each other. The upper portions of the pair of first transfer gate electrodes TG1 may be spaced apart from the upper portions of the other pair of first transfer gate electrodes TG1. In certain embodiments, as illustrated in <FIG>, the upper portions of all of the first transfer gate electrodes TG1 may be connected to each other.

A lower portion of each of the second transfer gate electrodes TG2 may extend into the substrate <NUM> toward the second photoelectric conversion region 110b, and an upper portion of each of the second transfer gate electrodes TG2 may protrude above a top surface of the corresponding active pattern ACT (i.e., the first surface 100a of the substrate <NUM>). In some embodiments, the upper portions of adjacent second transfer gate electrodes TG2 of the second transfer gate electrodes TG2 may be connected to each other. For example, similarly to <FIG>, the upper portions of a pair of second transfer gate electrodes TG2 of the second transfer gate electrodes TG2 may be connected to each other, and the upper portions of another pair of second transfer gate electrodes TG2 of the second transfer gate electrodes TG2 may be connected to each other. The upper portions of the pair of second transfer gate electrodes TG2 may be spaced apart from the upper portions of the other pair of second transfer gate electrodes TG2. In certain embodiments, similarly to <FIG>, the upper portions of all of the second transfer gate electrodes TG2 may be connected to each other.

<FIG> are cross-sectional views corresponding to the line A-A' of <FIG> to illustrate a method of manufacturing an image sensor according to some embodiments of the inventive concepts. <FIG> are cross-sectional views corresponding to the line B-B' of <FIG> to illustrate a method of manufacturing an image sensor according to some embodiments of the inventive concepts. Hereinafter, the descriptions to the same features as mentioned with reference to <FIG>, <FIG>, <FIG> and <FIG> will be omitted for the purpose of ease and convenience in explanation.

Referring to <FIG>, <FIG>, <FIG> and <FIG>, a substrate <NUM> having first and second surfaces 100a and 100b opposite to each other may be provided. The substrate <NUM> may have a first conductivity type (e.g., a P-type). A first trench T1 may be formed adjacent to the first surface 100a of the substrate <NUM>. The formation of the first trench T1 may include forming a first mask pattern <NUM> on the first surface 100a of the substrate <NUM>, and etching the substrate <NUM> using the first mask pattern <NUM> as an etch mask. The first trench T1 may define active patterns ACT in the substrate <NUM>.

A device isolation layer <NUM> may be formed on the first surface 100a of the substrate <NUM>. The device isolation layer <NUM> may cover the first mask pattern <NUM> and may fill the first trench T1. For example, the device isolation layer <NUM> may include or may be formed of a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer.

A second trench T2 may be formed in the substrate <NUM>. The formation of the second trench T2 may include forming a second mask pattern (not shown) defining a region, in which the second trench T2 will be formed, on the device isolation layer <NUM>, and etching the device isolation layer <NUM> and the substrate <NUM> using the second mask pattern as an etch mask.

The second trench T2 may define a plurality of pixel regions PXR in the substrate <NUM>. The plurality of pixel regions PXR may be arranged in the first direction D1 and the second direction D2. The second trench T2 may surround each of the pixel regions PXR when viewed in a plan view. The second trench T2 may extend in the first direction D1 and the second direction D2 to surround each of the pixel regions PXR. Each of the plurality of pixel regions PXR may include the active patterns ACT defined by the first trench T1. The second trench T2 may include first extension trenches ET1 extending into each of the pixel regions PXR. The first extension trenches ET1 may extend in the second direction D2 in each of the pixel regions PXR and may be spaced apart from each other in the second direction D2 in each of the pixel regions PXR. In some embodiments, as described with reference to <FIG>, the second trench T2 may further include second extension trenches extending into each of the pixel regions PXR. The second extension trenches may extend in the first direction D1 in each of the pixel regions PXR and may be spaced apart from each other in the first direction D <NUM> in each of the pixel regions PXR.

Referring to <FIG>, <FIG>, <FIG> and <FIG>, a deep device isolation pattern <NUM> may be formed to fill the second trench T2. The deep device isolation pattern <NUM> may include a side insulating pattern <NUM> conformally covering an inner surface of the second trench T2, a semiconductor pattern <NUM> and <NUM> filling a lower portion of the second trench T2, and a filling insulation pattern <NUM> filling a remaining portion of the second trench T2 on the semiconductor pattern <NUM> and <NUM>. The semiconductor pattern <NUM> and <NUM> may include a first semiconductor pattern <NUM> filling a portion of the second trench T2, and a second semiconductor pattern <NUM> between the first semiconductor pattern <NUM> and the side insulating pattern <NUM>. The deep device isolation pattern <NUM> may include first extensions 150P1 filling the first extension trenches ET1. In some embodiments, the deep device isolation pattern <NUM> may further include second extensions 150P2 filling the second extension trenches, as described with reference to <FIG>.

For example, the formation of the deep device isolation pattern <NUM> may include forming a side insulating layer conformally covering the inner surface of the second trench T2 on the device isolation layer <NUM>, forming a second semiconductor layer filling a portion of the second trench T2 on the side insulating layer, anisotropically etching the second semiconductor layer to form the second semiconductor pattern <NUM>, forming a first semiconductor layer filling the second trench T2 on the second semiconductor pattern <NUM>, etching the first semiconductor layer by an etch-back process to form the first semiconductor pattern <NUM>, forming a filling insulation layer filling a remaining portion of the second trench T2, and planarizing the filling insulation layer and the side insulating layer to form the filling insulation pattern <NUM> and the side insulating pattern <NUM>. For example, the formation of the second semiconductor pattern <NUM> may further include injecting dopants having the first conductivity type (e.g., P-type dopants) into the second semiconductor pattern <NUM>. The planarization process for forming the filling insulation pattern <NUM> and the side insulating pattern <NUM> may include planarizing the filling insulation layer, the side insulating layer and the device isolation layer <NUM> to expose the first surface 100a of the substrate <NUM>. By the planarization process, the first mask pattern <NUM> may be removed and a shallow device isolation pattern <NUM> filling the first trench T1 may be formed.

A first photoelectric conversion region 110a and a second photoelectric conversion region 110b may be formed in each of the pixel regions PXR. The first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be adjacent to each other in the first direction D1 in each of the pixel regions PXR. The first extensions 150P1 of the deep device isolation pattern <NUM> may be disposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. The first extensions 150P1 may extend in the second direction D2 between the first and second photoelectric conversion regions 110a and 110b and may be spaced apart from each other in the second direction D2 between the first and second photoelectric conversion regions 110a and 110b. In some embodiments, as described with reference to <FIG> and <FIG>, the second extensions 150P2 of the deep device isolation pattern <NUM> may extend into the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, respectively. Each of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may continuously extend in the second direction D2 between the second extensions 150P2.

For example, the formation of the first and second photoelectric conversion regions 110a and 110b may include injecting dopants having a second conductivity type (e.g., an N-type) different from the first conductivity type (e.g., a P-type) into the substrate <NUM>.

A thinning process may be performed on the second surface 100b of the substrate <NUM>, and portions of the substrate <NUM> and the deep device isolation pattern <NUM> may be removed by the thinning process. For example, the thinning process may include grinding or polishing and/or anisotropically and/or isotropically etching the second surface 100b of the substrate <NUM>. A lower portion of the deep device isolation pattern <NUM> may be removed by the thinning process, and a bottom surface <NUM> of the deep device isolation pattern <NUM> may be substantially coplanar with the second surface 100b of the substrate <NUM>.

Referring to <FIG>, <FIG>, <FIG> and <FIG>, a plurality of first transfer gate electrodes TG1, a first floating diffusion region FD1, a plurality of second transfer gate electrodes TG2 and a second floating diffusion region FD2 may be formed on each of the pixel regions PXR and may be formed adjacent to the first surface 100a of the substrate <NUM>. The first transfer gate electrodes TG1 and the first floating diffusion region FD1 may be formed on a corresponding active pattern ACT of the active patterns ACT and may vertically overlap with the first photoelectric conversion region 110a (e.g., in the third direction D3). The second transfer gate electrodes TG2 and the second floating diffusion region FD2 may be formed on a corresponding active pattern ACT of the active patterns ACT and may vertically overlap with the second photoelectric conversion region 110b (e.g., in the third direction D3). In some embodiments, as described with reference to <FIG> and <FIG>, the floating diffusion region FD may be formed on a corresponding active pattern ACT between the first extensions 150P1 of the deep device isolation pattern <NUM> and between the second extensions 150P2 of the deep device isolation pattern <NUM>, a plurality of first transfer gate electrodes TG1 may be formed to vertically overlap with the first photoelectric conversion region 110a (e.g., in the third direction D3), and a plurality of second transfer gate electrodes TG2 may be formed to vertically overlap with the second photoelectric conversion region 110b (e.g., in the third direction D3).

A lower portion of each of the first and second transfer gate electrodes TG1 and TG2 may penetrate the corresponding active pattern ACT and may extend into the substrate <NUM>. An upper portion of each of the first and second transfer gate electrodes TG1 and TG2 may protrude above a top surface of the corresponding active pattern ACT (i.e., the first surface 100a of the substrate <NUM>). The first and second floating diffusion regions FD1 and FD2 (or the floating diffusion region FD) may be formed by injecting dopants (e.g., N-type dopants) having a second conductivity type different from the first conductivity type of the substrate <NUM> into the corresponding active pattern ACT.

A first gate dielectric pattern GI1 may be formed between each of the first transfer gate electrodes TG1 and the substrate <NUM> (i.e., the corresponding active pattern ACT), and a second gate dielectric pattern GI2 may be formed between each of the second transfer gate electrodes TG2 and the substrate <NUM> (i.e., the corresponding active pattern ACT).

A plurality of gate electrodes GE and source/drain regions SD may be formed on each of the pixel regions PXR and may be formed adjacent to the first surface 100a of the substrate <NUM>. The gate electrodes GE and the source/drain regions SD may be formed on corresponding active patterns ACT and may vertically overlap with the first photoelectric conversion region 110a or the second photoelectric conversion region 110b (e.g., in the third direction D3). The source/drain regions SD may be formed by injecting dopants (e.g., N-type dopants) having the second conductivity type into the corresponding active patterns ACT. A gate dielectric pattern GI may be formed between each of the gate electrodes GE and the substrate <NUM> (i.e., the corresponding active pattern ACT).

A first interlayer insulating layer <NUM> may be formed on the first surface 100a of the substrate <NUM> and may cover the first and second transfer gate electrodes TG1 and TG2 and the gate electrodes GE. A first set of contact plugs <NUM> may be formed in the first interlayer insulating layer <NUM> and may penetrate the first interlayer insulating layer <NUM> so as to be connected to the first and second floating diffusion regions FD1 and FD2 (or the floating diffusion region FD) and the source/drain regions SD. A second interlayer insulating layer <NUM> may be formed on the first interlayer insulating layer <NUM>. A second set of contact plugs <NUM> and conductive lines <NUM> may be formed in the second interlayer insulating layer <NUM>. The second set of contact plugs <NUM> may penetrate the first interlayer insulating layer <NUM> and the second interlayer insulating layer <NUM> so as to be connected to the first and second transfer gate electrodes TG1 and TG2 and the gate electrodes GE. The conductive lines <NUM> may be connected to the contact plugs <NUM>.

Referring again to <FIG>, <FIG>, <FIG> and <FIG>, an anti-reflection layer <NUM> and a first insulating layer <NUM> may be sequentially formed on the second surface 100b of the substrate <NUM>. A color filter array <NUM> may be formed on the first insulating layer <NUM>. The color filter array <NUM> may include a plurality of color filters <NUM>, and the plurality of color filters <NUM> may be disposed on the plurality of pixel regions PXR, respectively. Each of the plurality of color filters <NUM> may be formed to vertically overlap with the first and second photoelectric conversion regions 110a and 110b of each of the pixel regions PXR (e.g., in the third direction D3).

A second insulating layer <NUM> may be formed on the color filter array <NUM>, and a micro lens array <NUM> may be formed on the second insulating layer <NUM>. The micro lens array <NUM> may include a plurality of micro lenses <NUM> disposed on the plurality of color filters <NUM>, respectively. Each of the plurality of micro lenses <NUM> may be formed to vertically overlap with the first and second photoelectric conversion regions 110a and 110b of each of the pixel regions PXR (e.g., in the third direction D3).

<FIG> is a plan view illustrating an image sensor according to some embodiments of the inventive concepts, and <FIG> is a cross-sectional view taken along a line I-I' of <FIG>. Hereinafter, differences between the present embodiments and the above embodiments of <FIG>, <FIG>, <FIG> and <FIG> will be mainly described for the purpose of ease and convenience in explanation.

Referring to <FIG> and <FIG>, an image sensor may include a substrate <NUM> including a pixel array region AR, an optical black region OB and a pad region PR, an interconnection layer <NUM> on a first surface 100a of the substrate <NUM>, a base substrate <NUM> on the interconnection layer <NUM>, and a light transmitting layer <NUM> on a second surface 100b of the substrate <NUM>. The interconnection layer <NUM> may be disposed between the first surface 100a of the substrate <NUM> and the base substrate <NUM>. The interconnection layer <NUM> may include an upper interconnection layer <NUM> adjacent to the first surface 100a of the substrate <NUM>, and a lower interconnection layer <NUM> between the upper interconnection layer <NUM> and the base substrate <NUM>. The pixel array region AR may include a plurality of pixel regions PXR, and a deep device isolation pattern <NUM> disposed therebetween. The pixel array region AR may be substantially the same as at least one of the image sensors described with reference to <FIG>.

A first connection structure <NUM>, a first contact <NUM> and a bulk color filter <NUM> may be disposed on the optical black region OB of the substrate <NUM>. The first connection structure <NUM> may include a first light blocking pattern <NUM>, a first separation pattern <NUM>, and a first capping pattern <NUM>. The first light blocking pattern <NUM> may be disposed on the second surface 100b of the substrate <NUM>. The first light blocking pattern <NUM> may cover the first insulating layer <NUM> and may conformally cover an inner surface of each of a third trench TR3 and a fourth trench TR4. The first light blocking pattern <NUM> may penetrate the photoelectric conversion layer <NUM> and the upper interconnection layer <NUM>. The first light blocking pattern <NUM> may be connected to the semiconductor pattern <NUM> and <NUM> of the deep device isolation pattern <NUM> of the photoelectric conversion layer <NUM> and may be connected to interconnection lines (or conductive lines) in the upper interconnection layer <NUM> and the lower interconnection layer <NUM>. Thus, the first connection structure <NUM> may electrically connect the photoelectric conversion layer <NUM> and the interconnection layer <NUM>. The first light blocking pattern <NUM> may include a metal material (e.g., tungsten). The first light blocking pattern <NUM> may block light incident to the optical black region OB.

The first contact <NUM> may fill a remaining portion of the third trench TR3. The first contact <NUM> may include a metal material (e.g., aluminum). The first contact <NUM> may be connected to the semiconductor pattern <NUM> and <NUM> of the deep device isolation pattern <NUM>. A bias may be applied to the semiconductor pattern <NUM> and <NUM> through the first contact <NUM>. The first separation pattern <NUM> may fill a remaining portion of the fourth trench TR4. The first separation pattern <NUM> may penetrate the photoelectric conversion layer <NUM> and may penetrate a portion of the interconnection layer <NUM>. The first separation pattern <NUM> may include an insulating material. The first capping pattern <NUM> may be disposed on the first separation pattern <NUM>. The first capping pattern <NUM> may include the same material as the filling insulation pattern <NUM> of the deep device isolation pattern <NUM>.

The bulk color filter <NUM> may be disposed on the first connection structure <NUM> and the first contact <NUM>. The bulk color filter <NUM> may cover the first connection structure <NUM> and the first contact <NUM>. A first protective layer <NUM> may be disposed on the bulk color filter <NUM> to seal or encapsulate the bulk color filter <NUM>.

An additional photoelectric conversion region <NUM>' and a dummy region <NUM> may be provided in corresponding pixel regions PXR of the optical black region OB. The additional photoelectric conversion region <NUM>' may be a region doped with dopants (e.g., N-type dopants) having a second conductivity type different from the first conductivity type of the substrate <NUM>. The additional photoelectric conversion region <NUM>' may have a structure similar to that of photoelectric conversion regions <NUM> (e.g., the first and second photoelectric conversion regions 110a and 110b) in the plurality of pixel regions PXR of the pixel array region AR but may not perform the same operation (i.e., the operation of receiving light to generate an electrical signal) as the photoelectric conversion regions <NUM>. The dummy region <NUM> may not be doped with dopants.

A second connection structure <NUM>, a second contact <NUM> and a second protective layer <NUM> may be disposed on the pad region PR of the substrate <NUM>. The second connection structure <NUM> may include a second light blocking pattern <NUM>, a second separation pattern <NUM>, and a second capping pattern <NUM>.

The second light blocking pattern <NUM> may be disposed on the second surface 100b of the substrate <NUM>. The second light blocking pattern <NUM> may cover the first insulating layer <NUM> and may conformally cover an inner surface of each of a fifth trench TR5 and a sixth trench TR6. The second light blocking pattern <NUM> may penetrate the photoelectric conversion layer <NUM> and the upper interconnection layer <NUM>. The second light blocking pattern <NUM> may be connected to interconnection lines (or conductive lines) provided in the lower interconnection layer <NUM>. Thus, the second connection structure <NUM> may electrically connect the photoelectric conversion layer <NUM> and the interconnection layer <NUM>. The second light blocking pattern <NUM> may include a metal material (e.g., tungsten). The second light blocking pattern <NUM> may block light incident to the pad region PR.

The second contact <NUM> may fill a remaining portion of the fifth trench TR5. The second contact <NUM> may include a metal material (e.g., aluminum). The second contact <NUM> may function as an electrical connection path between the image sensor and an external device. The second separation pattern <NUM> may fill a remaining portion of the sixth trench TR6. The second separation pattern <NUM> may penetrate the photoelectric conversion layer <NUM> and may penetrate a portion of the interconnection layer <NUM>. The second separation pattern <NUM> may include an insulating material. The second capping pattern <NUM> may be disposed on the second separation pattern <NUM>. The second capping pattern <NUM> may include the same material as the filling insulation pattern <NUM> of the deep device isolation pattern <NUM>. The second protective layer <NUM> may cover the second connection structure <NUM>.

A current applied through the second contact <NUM> may flow into the semiconductor pattern <NUM> and <NUM> of the deep device isolation pattern <NUM> through the second light blocking pattern <NUM>, the interconnection lines of the interconnection layer <NUM> and the first light blocking pattern <NUM>. Electrical signals generated from the photoelectric conversion regions <NUM> (e.g., the first and second photoelectric conversion regions 110a and 110b) in the plurality of pixel regions PXR of the pixel array region AR may be transferred to the external device through the interconnection lines of the interconnection layer <NUM>, the second light blocking pattern <NUM> and the second contact <NUM>.

According to embodiments of the inventive concepts, each of the pixel regions may include the first photoelectric conversion region and the second photoelectric conversion region which are adjacent to each other, and the deep device isolation pattern may include the first extensions extending between the first photoelectric conversion region and the second photoelectric conversion region, and the second extensions extending into the first photoelectric conversion region and the second photoelectric conversion region, respectively. In this case, each of the pixel regions may include a plurality of photodiodes, and thus the charge storage capacity (or full well capacity) of each of the pixel regions may be increased. In addition, the plurality of first transfer gate electrodes may be disposed on the first photoelectric conversion region, and the plurality of second transfer gate electrodes may be disposed on the second photoelectric conversion region. Thus, the charge transfer characteristics of each of the pixel regions may be improved.

Claim 1:
An image sensor comprising:
a substrate (<NUM>) including a pixel region (PXR), the substrate extending in a first direction (D1) and a second direction (D2) intersecting the first direction (D1);
a first photoelectric conversion region (110a) and a second photoelectric conversion region (110b) which are disposed in the pixel region (PXR) of the substrate (<NUM>) and are adjacent to each other in the first direction (D1);
a deep device isolation pattern (<NUM>) penetrating the substrate in a third direction (D3) perpendicular to the first direction (D1) and the second direction (D2), and surrounding the pixel region (PXR), the deep device isolation pattern (<NUM>) comprising first extensions (150P1) extending in the second direction (D2) between the first photoelectric conversion region (110a) and the second photoelectric conversion region (110b), and the first extensions (150P1) spaced apart from each other in the second direction (D2);
a plurality of first transfer gate electrodes (TG1) disposed on the pixel region (PXR) of the substrate (<NUM>) and vertically overlapping with the first photoelectric conversion region (110a) in the third direction (D3); and
a plurality of second transfer gate electrodes (TG2) disposed on the pixel region (PXR) of the substrate (<NUM>) and vertically overlapping with the second photoelectric conversion region (100b) in the third direction (D3),
wherein the first photoelectric conversion region (110a) extends in the second direction (D2) under the plurality of first transfer gate electrodes (TG1).