Patent Description:
Transition encoding is used in many signal processing applications where large amounts of data is transmitted over a channel to a receiving end. It is particularly useful in signals that have embedded therein a clock signal within the data signal. One example application of transition encoding is in large panel displays such as televisions. As the sizes of the televisions become large, the signals have to travel over a longer distance. However, one of the consequences of transmitting signals over a long distance is the signal loss. Thus, more efficient techniques for signal processing to minimize loss and transmit more data over a shorter duration are desired.

<CIT> discloses a method of encoding a stream of data elements which involves splitting the stream of data elements into a first stream and a second stream; encoding the first stream to produce a first encoded stream; performing a constellation mapping using a combination of the first encoded stream and a third stream which is based on the second stream. This involves defining a signal constellation; defining a plurality of co-sets within the constellation such that a minimum distance between constellation points within each co-set is larger than a minimum distance between any constellation points within the signal constellation; performing said constellation mapping by using the first encoded stream to identify a sequence of co-sets of said plurality of co-sets, and by using the third stream to identify a sequence of constellation points within respective co-sets of the sequence of co-sets identified by said first encoded stream.

<CIT> discloses that for some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. The disclosure provides a modulator that can reduce latency for applications such as <NUM>/<NUM> communication over copper cables or single-mode optical fiber (SMF). The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the disclosure provides a demodulator that is complementary to the modulator.

<CIT> discloses encoding PAM4 or PAM8 symbols to have a power spectral density (PSD) similar to the PSD of a standard 8b10b Non-Return-to-Zero stream. In one embodiment, a transmitter includes first and second 8b10b encoders that receive first and second streams split from an original byte stream. The first and second 8b10b encoders output first and second 8b10b streams, respectively. The first and second 8b10b streams are fed into a <NUM>-bit combiner that performs a linear combination of the first and second 8b10b streams. And a <NUM>-level Pulse Amplitude Modulation encoder (PAM4 encoder) converts the linear combination of each two bits, received from the combiner, into a PAM4 symbol. Wherein the resulting stream of PAM4 symbols has PSD similar to the PSD of the standard 8b10b non-return-to-zero stream.

According to various embodiments of the present disclosure, a system is described.

According to other embodiments of the present disclosure, a method is described.

The above and other features of the invention are set out in the claims.

A more complete understanding of embodiments of the invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.

Unless otherwise noted, like reference numerals denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof will not be repeated.

Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings. The present invention, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present invention to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of the present invention may not be described.

Non-return-to-zero (NRZ) is a coding scheme that utilizes a digital signal that changes between two voltage levels, for example -1V and +1V. In this example, -1V may be represented by a symbol such as a binary <NUM> and +1V may be represented by a binary <NUM>. Accordingly, the NRZ coded data signal may include a series of symbols made up of ones and zeros.

Transition encoding is a coding scheme that takes input data and outputs encoded data that has limited run-lengths (e.g., limited runs of consecutive <NUM> values and limited runs of consecutive <NUM> values). In other words, transition encoding encodes the input data such that the output data includes at least one "transition" (e.g., where the data transitions or changes from a <NUM> to a <NUM> or from a <NUM> to a <NUM>), thereby generating a limited run-length data stream. Some transition encoding schemes utilize a key to transform input data. For example, an encoder may add a key (e.g., a transition key) to a string of data signals and the data signals may be encoded based on the key. Thus, when a decoder receives the transition encoded data signals, the decoder may utilize the key to decode the data signals.

<FIG> illustrates an example of a coded data signal that is transition encoded according to various embodiments of the present disclosure. According to an embodiment, a key (e.g., KEY1) may be generated for every certain number of bits of data (e.g., DATA1-DATA31). In the illustrative example shown in <FIG>, a unique key may be generated for every <NUM> sets of <NUM>-bits of data. In some embodiments, the key may also comprise <NUM>-bits, and an exclusive OR (XOR) operation may be performed on the key and each set of the <NUM> sets of data. In other words, the <NUM>-bit key and the <NUM>-bit data (e.g., the first set DATA1 of the <NUM> sets of data) may be XOR'd to generate transition encoded data. Another XOR operation may be performed with the same key and the second set DATA2 of the <NUM> sets of data, and so on until each of the <NUM> sets of data are XOR'd with the same key. Accordingly, <NUM>-bits (i.e., <NUM> sets x <NUM>-bits) of transition encoded data may be generated based on the key, and the key may be inserted into the stream of data for transmission. In the example of <FIG>, the key precedes the data bits.

The same process may be repeated for the next <NUM> sets of data (of <NUM>-bits each), whereby another unique key (e.g., KEY2) may be generated and this key may be XOR'd with each set of the next <NUM> sets of data to generate another transition encoded data stream. Accordingly, the data stream includes a total of <NUM>-bits, of which <NUM>-bits are transition encoded data bits and <NUM>-bits are key bits, thus resulting with an overhead of about <NUM>%. It should be noted that while the above example is described using a key that comprises <NUM>-bits and a data stream that comprises <NUM> sets of data, in other embodiments, the key may comprise more or less number of bits and the data stream may comprise more or less number of sets. Accordingly, such transition encoding techniques may be used in high speed serial links such as, for example, in a television display. Thus, more efficient techniques for transmitting data is desired to reduce signal loss over lossy channels.

A pulse-amplitude modulation <NUM>-level (PAM4) is a coding scheme that takes a digital signal that changes between four voltage levels, for example, -3V, -1V, +1V, and +3V. Because there are four levels in a PAM4 coding scheme, more data may be transmitted over a channel in a given period of time compared to an NRZ coding scheme. For example, because there are four voltage levels, each voltage level may be represented by <NUM>-bits (e.g., <NUM>, <NUM>, <NUM>, <NUM>) instead of <NUM>-bit as in the case of an NRZ coding scheme that only uses two voltage levels.

<FIG> illustrates possible transitions in a PAM4 coded signal that can transition between the four distinct voltage levels. Thus, by applying a transition encoding scheme to the PAM4 coded signal in a similar manner to the transition encoding for an NRZ coded signal as previously described with reference to <FIG>, a more efficient encoding scheme may be achieved.

By considering the possible transitions in a PAM4 coded signal, the transitions may be described in terms of a major transition, where the voltage transitions from the highest voltage level to the lowest voltage level or vice versa (e.g., from +3V to -3V, or -3V to +3V); a minor transition, where the voltage transitions to the next higher or the next lower voltage level (e.g., from +3V to +1V, +1V to +3V, +1V to -1V, -1V to +1V, -1V to -3V, -3V to -1V); or an intermediate transition, where the voltage transition is greater than a minor transition but less than a major transition (e.g., from +3V to -1V, -1V to +3V, +1V to -3V, -3V to +1V). Among the <NUM> different possible transitions in a PAM4 coding scheme, only four of the minor transitions do not pass through the zero threshold during the transition. Therefore, an encoding scheme that provides periodic major transitions or intermediate transitions may result in a signal that is detectable with a slicer that monitors the zero threshold (e.g., a crossing slicer). Accordingly, costs associated with adding a slicer configured to monitor for minor transitions to a receiver may be avoided, resulting in a relatively less expensive receiver.

Embodiments of the present disclosure are directed to encoding techniques that provide transitions that cross the zero threshold (e.g., a major transition or an intermediate transition) so that a clock recovery process that targets such transitions in a data signal may extract a clock signal from the data signal. It is noted that while the example PAM4 transition voltages illustrated in <FIG> are shown as -3V, -1V, +1V, and +3V, actual transition voltages may be replaced with any other four distinct transition voltage levels such as, for example, -5V, -2V, +2V, and +5V; or +1V, +2V, +3V, and +4V.

<FIG> shows the eight possible transitions of a PAM4 coding scheme that cross the zero threshold. According to an embodiment, each voltage level (e.g., -3V, -1V, +1V, and +3V) may be assigned a <NUM>-bit binary symbol, for example, the +3V level may be assigned the symbol <NUM>, the +1V level may be assigned the symbol <NUM>, the -1V level may be assigned the symbol <NUM>, and the -3V level may be assigned the symbol <NUM>. Accordingly, when the data signal transitions from one level to another level and crosses the zero threshold, the most significant bit (MSB) of the <NUM>-bit code always changes. In other words, when the voltage level transitions, for example, from +3V to -1V, the <NUM>-bit code changes from <NUM> to <NUM>, wherein the MSB changes from <NUM> to <NUM>. Similarly, when the voltage level transitions from -3V to +3V, the <NUM>-bit code changes from <NUM> to <NUM>, wherein the MSB changes from <NUM> to <NUM>. Accordingly, every transition illustrated in <FIG> crosses the zero threshold and experiences a change in the MSB of the <NUM>-bit symbol.

<FIG> illustrates the possible transitions shown in <FIG>, separated into different categories. For purposes of this disclosure, a type <NUM> transition is a transition where the voltage level transitions from one positive voltage level to its corresponding negative voltage level, or from one negative voltage level to its corresponding positive voltage level. For example, the voltage level may transition from +3V to -3V, -3V to +3V, +1V to -1V, or -1V to +1V. A type <NUM> transition is a transition where the polarity of the voltage level does not change, and therefore the transition does not cross the zero threshold. For example, the voltage level may transition from +3V to +1V, +1V to +3V, -3V to -1V, or -1V to -3V. A type <NUM> transition is a transition where the voltage level transitions from one positive voltage level to another negative voltage level, or from one negative voltage level to another positive voltage level. For example, the voltage level may transition from +3V to -1V, -1V to +3V, -3V to +1V, or +1V to -3V.

Accordingly, every transition of the type <NUM> and type <NUM> categories experiences a change in the MSB of the <NUM>-bit code, whereas the transitions of the type <NUM> category maintain the same MSB of the <NUM>-bit code. Accordingly, if transition encoding is applied to the MSB of the <NUM>-bit code to provide transitions in the MSB, transitions that cross the zero threshold will occur. A transmitter that provides such transitions may be used in conjunction with a receiver that includes one or more slicers to monitor the 0V threshold and may not include slicers that monitor other thresholds. Thus, the disclosed transmitter may be compatible with relatively less complex receivers. In some embodiments, the LSB of the <NUM>-bit code may be ignored. Yet, in other embodiments, the transition encoding of the MSB may be applied to the LSB of the <NUM>-bit code for error detection, which will be described in more detail later with reference to <FIG>.

<FIG> is a block diagram of an example encoder <NUM> for implementing the PAM4 transition encoding scheme according to various embodiments of the present disclosure. The encoder <NUM> includes two transition encoders <NUM> and <NUM> in parallel, wherein each transition encoder <NUM>, <NUM> is configured to apply transition encoding to an input data signal, and output an NRZ data stream. In some embodiments, the output NRZ data stream also includes a key as described earlier. The NRZ data stream may be then be converted to a PAM4 data stream by a PAM4 transmitter <NUM> for transmission to a receiver.

According to an embodiment, a first data signal <NUM> is provided to a first transition encoder <NUM>. The first transition encoder <NUM> applies transition encoding to the first data signal <NUM> and generates a first stream of first bits <NUM>. Run lengths of repeated values are limited in the first stream of first bits <NUM> by the transition encoding, which in turn, assures that a transition occurs and therefore crosses the 0V threshold. In some embodiments, the first stream of first bits <NUM> may include just a stream of NRZ coded data bits, while in other embodiments, the first stream of first bits <NUM> may include data bits and transition coding data (TCD) key bits.

In the illustrated embodiment, the first stream of first bits <NUM> includes <NUM> bits of overhead (e.g., key bits) for every <NUM> bits of data, however other encoding efficiencies are possible. In some illustrative examples, the first transition encoder <NUM> packetizes the first data signal <NUM> into packets that each include <NUM> sets of <NUM>-bit data. The first transition encoder <NUM> may then identify a <NUM>-bit key for a transformation that when applied to the <NUM> sets results in <NUM><NUM>-bit transformed sets that have at least one transition (e.g., the <NUM> transformed sets do not include <NUM> or <NUM>). The <NUM><NUM>-bit transformed sets and the <NUM>-bit key may be output by the first transition encoder <NUM> as part of the first stream of first bits <NUM>. Therefore, a packet in the first stream of first bits <NUM> may include <NUM>-bits total of which <NUM>-bits is data and <NUM>-bits is overhead. While the first transition encoder <NUM> is described as generating <NUM> bit packets with <NUM> data bits and <NUM> key bits, it should be noted that the encoder <NUM> may generate packets of different sizes, packets that include sets (e.g., words) of different sizes, keys of different sizes, or a combination thereof. Further, it should be noted that while a packet-based transition encoding scheme is described above, the first transition encoder <NUM> may operate according to a stream-based transition encoding scheme or other type of transition encoding scheme.

In some embodiments, the encoder <NUM> further includes a second transition encoder <NUM>. A second data signal <NUM> is provided to the second transition encoder <NUM>, and the second transition encoder <NUM> applies the transition encoding to the second data signal <NUM> and generates a second stream of second bits <NUM>. In some embodiments, the second stream of second bits <NUM> may also be NRZ coded bits. The second transition encoder <NUM> may implement any type of transition encoding scheme, as described above with reference to the first transition encoder <NUM>. In the illustrated example, the second stream of second bits <NUM> includes <NUM> overhead bits (e.g., key bits) for every <NUM> bits of data in the second data signal <NUM>, but other efficiencies are possible. In some embodiments, the first data signal <NUM> and the second data signal <NUM> may be the same data signal. In other embodiments, the first data signal <NUM> and the second data signal <NUM> may be different signals.

In some embodiments, the first transition encoder <NUM> takes the first data signal <NUM>, which may be, for example, a <NUM> Gbps signal, and generates a first stream of first bits <NUM> that includes encoded data bits. In some embodiments, the first stream of first bits <NUM> may also include the key. The second transition encoder <NUM> takes the second data signal <NUM>, which may also be, for example, a <NUM> Gbps signal, and generates a second stream of second bits <NUM> that includes encoded data bits. In some embodiments, the second stream of second bits <NUM> may also include another key. For purposes of explaining the example embodiments, the key for the first stream of first bits <NUM> may be assumed to be <NUM> and the key for the second stream of second bits <NUM> may be assumed to be <NUM>, by way of example only. Accordingly, such encoding schemes that use keys may limit the run lengths of both the data bits and the selected keys.

According to an embodiment of the present disclosure, the first stream of first bits <NUM> and the second stream of second bits <NUM> with limited run lengths are provided in parallel to a PAM4 transmitter <NUM>. The PAM4 transmitter <NUM> converts the first stream of first bits <NUM> and the second stream of second bits <NUM> from an NRZ coding scheme to a PAM4 coding scheme comprising four voltage levels. Moreover, the first stream of first bits <NUM> is converted to become the MSB of the PAM4 symbol and the second stream of second bits <NUM> is converted to become the least significant bit (LSB) of the PAM4 symbol. For example, if the key for the first stream of first bits <NUM> is <NUM> and the key for the second stream of second bits <NUM> is <NUM>, then the PAM4 transmitter <NUM> generates PAM4 symbols <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, which correspond to voltage levels - 1V, +1V, +3V, -1V, +3V, and +3V based on the example four voltage levels. Because the transition encoding of the first data signal <NUM> by the first transition encoder <NUM> limits run-lengths in the MSBs of symbols transmitted by the PAM4 transmitter <NUM>, voltage transitions that cross 0V are provided in output of the PAM4 transmitter <NUM>. These voltage transitions may not depend on whether LSBs of output of the PAM4 transmitter <NUM> change. Therefore, some embodiments may reduce costs and/or complexity of a transmitter by removing the second transition encoder <NUM> and replacing it with a simpler block such as a bit generator. It should be noted that the same process described in the above example, of converting the key bits from NRZ to PAM4, may be applied to convert the data bits from NRZ to PAM4.

In some embodiments, the converted PAM4 symbols are transmitted to a receiver, for example, in a television display. Accordingly, by encoding two <NUM> Gbps digital signals in parallel, a single <NUM> Gbps PAM4 signal may be generated.

<FIG> is a block diagram of an example encoder <NUM> that does not include a second transition encoder, according to an embodiment of the present disclosure. The elements of the encoder <NUM> in <FIG> that are the same as the elements in the encoder <NUM> of <FIG> will not be described again. Instead, only the differences will be described.

According to some embodiments, the second transition encoder <NUM> of <FIG> may be replaced by, for example, a bit generator <NUM> that pads the second data signal <NUM> with a number of bits equivalent to the number of overhead bits added by the first transition encoder <NUM>. The actual value of the bits used for padding the second data signal <NUM> is not important and therefore may be all zeros (<NUM>), all ones (<NUM>), or other random values as long as the number of padding bits is the same as the number of overhead bits added by the first transition encoder <NUM>. This is because the second stream of second bits <NUM> correspond to the LSB of the PAM4 symbols, and therefore may be ignored. It should be noted that the bit generator <NUM> merely inserts the padding bits to the second data signal <NUM> and does not change the bits of the second data signal <NUM> as with the first transition encoder <NUM> used for the first data signal <NUM>. Therefore, by inserting all zeros, all ones, or random values, an encoder may be eliminated from being used with the second data signal <NUM> and may be replaced with a simpler, less complex bit generator <NUM>, thereby reducing the cost of the transmitter, while maintaining alignment between the outputs of the first transition encoder <NUM> and the bit generator <NUM>. As described above, the PAM4 transmitter <NUM> is configured to convert the first stream of first bits <NUM> into the MSB of output PAM4 symbols and transmit the PAM4 symbols to a receiver. Because run-lengths are limited in the MSBs by the first transition encoder <NUM>, transitions that cross 0V may occur in output of the PAM4 transmitter <NUM>.

In some embodiments, the key generated by the first transition encoder <NUM> may be duplicated and inserted in to the second data signal <NUM> to generate a second stream of second bits <NUM> that merely includes the same key as the key for the first stream of first bits <NUM>. In other words, the data bits of the second data signal <NUM> are not changed or transition encoded, but rather the key is merely inserted to pad the second stream of second bits <NUM>. Accordingly, the alignment of the first stream of first bits <NUM> and the second stream of second bits <NUM> may be maintained. By duplicating the key generated by the first transition encoder <NUM> and inserting it into the second data signal <NUM>, error detection of the key may be performed. For example, in some embodiments, when the PAM4 transmitter <NUM> receives the first stream of first bits <NUM> and the second stream of second bits <NUM> and detects that the overhead bits for each stream are not the same, then an error may be present in the data stream and the PAM4 transmitter <NUM> may not transmit the signal to the receiver. In other embodiments, the receiver may be configured to detect the error and therefore reject the incoming data when it detects that the data stream includes errors.

Yet in other embodiments, the first transition encoder <NUM> may generate a <NUM>-bit key and perform transition encoding on the first data signal <NUM>, but instead of inserting all <NUM>-bits into the first stream of first bits <NUM>, it may insert only a portion of the <NUM>-bits (e.g., <NUM>-bits) into the first stream of first bits <NUM>. The <NUM> additional bits (out of the total of <NUM>-bits generated) may be inserted as padding bits to the second stream of second bits <NUM>, thereby reducing the overall length of the bits from <NUM> bits to <NUM> bits in each of the first stream of first bits <NUM> and the second stream of second bits <NUM>. In this case, only <NUM> bits out of <NUM> bits are the overhead, thereby reducing the percentage of overhead bits in each stream.

In some embodiments, the receiver may be configured to take the <NUM> overhead bits from the LSB of the PAM4 symbols and reassemble the key for the MSB of the PAM4 symbols. Accordingly, the efficiency may be improved. It is noted that the embodiments of the present disclosure are described by referencing specific examples, such as a data signal having <NUM> sets of <NUM>-bit data, a key that is <NUM> bits, etc. However, such specific examples are provided merely as means to explain the various embodiments of the present disclosure and are not intended to be limited. Instead, other variations may be envisaged by those having ordinary skill in the art. For example, the data may be in packets or the data may be streams of data, each of the data sets may be <NUM>-bits, <NUM>-bits, or n-bits in length, and/or the key may be <NUM> bits or m-bits in length. Therefore, the percentage of the overhead bits may also vary.

<FIG> is a flow chart of a method <NUM> for performing transition encoding compatible PAM4 encoding, according to various embodiments of the present disclosure. In some embodiments, first input bits may be received by a first encoder. For example, the first input bits may be high speed (e.g., <NUM> Gbps) packets of data bits or it may be a stream of data bits. The first encoder may be a transition encoder that is configured to encode the received first input bits to generate a first stream of first bits based on the first input bits (<NUM>). In some embodiments, the first stream of first bits may be generated by the first encoder by applying transition encoding to the first input bits. In some embodiments, second inputs bits may be received by a bit generator. In some embodiments, the bit generator may be an encoder such as a transition encoder. Yet, in other embodiments, the bit generator may simply be a device that generates additional bits. Accordingly, the bit generator may generate a second stream of second bits based on the second input bits (<NUM>). For example, the bit generator may generate padding bits (e.g., bits where the value of the bits are not important) that are inserted or added to the second input bits. In some embodiments, the number of padding bits generated by the bit generator may be equivalent to the number of key bits generated by the first encoder (as described earlier with reference to <FIG>). In some embodiments, a PAM4 transmitter may be configured to generate PAM4 symbols based at least on the first stream of first bits received by the PAM4 transmitter from the first encoder (<NUM>). For example, in some embodiments, the first stream of first bits may correspond to the MSB of the generated PAM4 symbols. In some embodiments, the PAM4 symbols may be generated based further on the second stream of second bits. In this case, the second stream of second bits may correspond to the LSB of the generated PAM4 symbols. Accordingly, input NRZ data bits may be transition encoded and then transformed into PAM4 symbols to improve efficiencies in high speed serial links.

It will be understood that, although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the scope of the present invention.

Spatially relative terms, such as "beneath," "below," "lower," "under," "above," "upper," and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated <NUM> degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the present invention. It will be further understood that the terms "comprises," "comprising," "includes," and "including," when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Further, the use of "may" when describing embodiments of the present invention refers to "one or more embodiments of the present invention. " As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

The electronic or electric devices and/or any other relevant devices or components according to embodiments of the present invention described herein may be implemented utilizing any suitable hardware, firmware (e.g. an application-specific integrated circuit), software, or a combination of software, firmware, and/or hardware. For example, the various components of these devices may be formed on one integrated circuit (IC) chip or on separate IC chips. Further, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate. Further, the various components of these devices may be a process or thread, running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, flash drive, or the like. Also, a person of skill in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the scope of the claims.

Claim 1:
A method (<NUM>) comprising:
generating (<NUM>), by a first encoder (<NUM>), a first stream of first bits (<NUM>) based on first input bits (<NUM>) provided to the first encoder (<NUM>), wherein the generating the first stream of first bits (<NUM>) comprises applying transition encoding to the first input bits (<NUM>);
generating (<NUM>), by a bit generator (<NUM>), a second stream of second bits (<NUM>) based on second input bits (<NUM>) provided to the bit generator (<NUM>); and
generating (<NUM>), by a PAM4 transmitter (<NUM>), PAM4 symbols based at least on the first stream of first bits (<NUM>) received by the PAM4 transmitter (<NUM>);
wherein the first stream of first bits (<NUM>) correspond to most significant bits of the PAM4 symbols generated by the PAM4 transmitter (<NUM>).