Patent Description:
In the related art, a synchronous type solid-state imaging device that synchronizes a synchronous signal such as a vertical synchronizing signal and images image data (frame) has been used in an imaging apparatus or the like. This typical synchronous type solid-state imaging device acquires the image data only for each period of the synchronizing signal (e.g., <NUM>/<NUM> sec). It becomes therefore difficult to correspond to the case that faster processing is needed in the field with respect to traffic, a robot, or the like. Accordingly, an asynchronous type solid-state imaging device including an address event detection circuit arranged for each pixel has been proposed (for example, see Patent Literature <NUM>). The address event detection circuit detects in real time as an address event that an amount of light of the pixel exceeds a threshold for each pixel address. <CIT> discloses a first semiconductor substrate on which light is incident; a second semiconductor substrate that is layered on a surface located on the opposite side of a surface on which side the light is incident on the first semiconductor substrate; n-number of first photoelectric conversion elements that are disposed on the first semiconductor substrate at a certain interval, and that each generate a first charge signal obtained through photoelectric conversion of the incident light; n-number of first retrieval circuits that are disposed on the first semiconductor substrate in a corresponding manner with the respective n-number of first photoelectric conversion elements, that each accumulate the first charge signal generated by a corresponding one of the first photoelectric conversion elements, and that each output, as a first pixel signal, a signal voltage in accordance with the accumulated first charge signal; a drive circuit that successively drives each of the n-number of first retrieval circuits and causes each thereof to output the first pixel signal; m-number of second photoelectric conversion elements that are disposed on the second semiconductor substrate or the first semiconductor substrate at a certain interval, and that each generate a second charge signal obtained through photoelectric conversion of the incident light; and m-number of second retrieval circuits that each successively output a second pixel signal representing a change in, among the m-number of second photoelectric conversion elements, the second charge signal generated by a corresponding one of the second photoelectric conversion elements, wherein each of the m-number of second retrieval circuits has: a detection circuit that detects a temporal change in the second charge signal generated by the corresponding one of the second photoelectric conversion elements and that outputs, when a change exceeding a predetermined threshold is detected, an event signal representing the direction of the change; and a pixel signal generation circuit that is disposed on the second semiconductor substrate and that outputs a second pixel signal obtained by adding, to the event signal, address information representing the position where the corresponding one of the second photoelectric conversion elements is disposed, wherein n is a natural number equal to or larger than <NUM> and m is a natural number equal to or larger than <NUM>.

<CIT> discloses a pixel circuit and an operating method thereof, comprising - a front-end circuit (<NUM>) comprising a single photodiode (PD) and having an output (<NUM>), said front-end circuit (<NUM>) being configured for delivering on said output a photoreceptor signal derived from a light exposure of said single photodiode (PD); - a transient detector circuit (<NUM>) configured for detecting a change in said photoreceptor signal delivered on said output (<NUM>); - an exposure measurement circuit (<NUM>) configured for measuring said photoreceptor signal delivered on said output (<NUM>) upon detection by the transient detector circuit (<NUM>) of a change in the photoreceptor signal. The invention also relates to an image sensor comprising a plurality of pixel circuits.

The above-described asynchronous type solid-state imaging device can generate and output data much faster than the synchronous type solid-state imaging device. Thus, it is possible to perform fast image recognition processing on a human or an obstacle and improve safety in the traffic field, for example. However, the address event detection circuit has a circuit scale larger than that of a pixel circuit of the synchronous type. If such a circuit is arranged for each pixel, there is a problem that a mounting area may increase as compared that that of the synchronous type.

The present technology is made in view of the above-mentioned circumstances, and it is an object of the present technology to reduce a mounting area in a solid-state imaging device that detects an address event.

According to a first aspect, the present disclosure provides a solid-state imaging device according to independent claim <NUM>. Further aspects of the present disclosure are set forth in the dependent claims, the drawings and the following description.

The present technology can exhibit an excellent effect that a mounting area is reduced in a solid-state imaging device that detects an address event. It should be noted that the effects described here are not necessarily limitative and may be any of effects described in the present disclosure.

Unless explicitly indicated as "embodiments according to the claimed invention", any embodiment or examples in the description may include some but not all features as literally defined in the claims and are present for illustration purposes only.

Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. A description will be given in the following order.

<FIG> is a block diagram depicting one configuration example of an imaging apparatus <NUM> according to a first embodiment of the present technology. The imaging apparatus <NUM> includes an imaging lens <NUM>, a solid-state imaging device <NUM>, a recording section <NUM>, and a control section <NUM>. As the imaging apparatus <NUM>, a camera mounted to an industrial robot, a vehicle-mounted camera, or the like is assumed.

The imaging lens <NUM> collects incident light toward the solid-state imaging device <NUM>. The solid-state imaging device <NUM> photoelectrically converts the incident light and images image data. The solid-state imaging device <NUM> executes predetermined single processing such as image recognition processing on the image data imaged and outputs the data processed to the recording section <NUM> via a signal line <NUM>.

The recording section <NUM> records the data from the solid-state imaging device <NUM>. The control section <NUM> controls the solid-state imaging device <NUM> and allows the image data to be imaged.

<FIG> is a view depicting an example of a lamination structure of the solid-state imaging device <NUM> according to the first embodiment of the present technology. The solid-state imaging device <NUM> includes a detection chip <NUM> and a light receiving chip <NUM> laminated on the detection chip <NUM>. These chips are electrically connected through a connection section such as a via. Incidentally, the chips may be connected by a Cu-Cu bonding or a bump other than the via. Note that the light receiving chip <NUM> is an example of the claimed first chip and the detection chip <NUM> is an example of the claimed second chip.

<FIG> is an example of a plan view of the light receiving chip <NUM> according to the first embodiment of the present technology. The light receiving chip <NUM> includes a light receiving section <NUM> and via arrangement sections <NUM>, <NUM>, and <NUM>.

Vias being connected to the detection chip <NUM> are arranged in the via arrangement sections <NUM>, <NUM>, and <NUM>. In addition, a plurality of photodiodes <NUM> is arrayed in a two-dimensional lattice on the light receiving section <NUM>. Each photodiode <NUM> photoelectrically converts the incident light and generates a photocurrent. A pixel address specified by a row address and a column address is assigned to each photodiode <NUM>, which is treated as a pixel.

<FIG> is an example of a plan view of the detection chip <NUM> according to the first embodiment of the present technology. The detection chip <NUM> includes via arrangement sections <NUM>, <NUM>, and <NUM>, a signal processing circuit <NUM>, a row drive circuit <NUM>, a column drive circuit <NUM>, and an address event detection section <NUM>. Vias being connected to the light receiving chip <NUM> are arranged in the via arrangement sections <NUM>, <NUM>, and <NUM>.

The address event detection section <NUM> generates a detection signal from the photocurrent of each of the plurality of photodiodes <NUM> and outputs the detection signal to the signal processing circuit <NUM>. The detection signal is a <NUM>-bit signal showing whether or not it detects as an address event that an amount of incident light exceeds a predetermined threshold.

The row drive circuit <NUM> selects the row address and allows the detection signal corresponding to the row address to be output to the address event detection section <NUM>.

The column drive circuit <NUM> selects the column address and allows the detection signal corresponding to the column address to be output to the address event detection section <NUM>.

The signal processing circuit <NUM> executes predetermined signal processing on the detection signal from the address event detection section <NUM>. The signal processing circuit <NUM> arrays the detection signal in a two-dimensional lattice as the pixel signal and acquires the image data including <NUM>-bit information for each pixel. Then, the signal processing circuit <NUM> executes the signal processing such as the image recognition processing on the image data.

<FIG> is an example of a plan view of the address event detection section <NUM> according to the first embodiment of the present technology. A plurality of address event detection circuits <NUM> is arrayed on the address event detection section <NUM> in a two-dimensional lattice. Each pixel address is assigned to each address event detection circuits <NUM> and each pixel and each photodiode <NUM> having the same address are connected.

An address event detection circuit <NUM> quantizes a voltage signal corresponding to the photocurrent from the corresponding photodiode <NUM> and outputs the voltage signal as the detection signal.

<FIG> is a block diagram depicting one configuration example of the address event detection circuit <NUM> according to the claimed invention. The address event detection circuit <NUM> includes a current voltage conversion circuit <NUM>, a buffer <NUM>, a subtractor <NUM>, a quantizer <NUM>, and a transfer circuit <NUM>.

The current voltage conversion circuit <NUM> converts the photocurrent from the corresponding photodiode <NUM> into the voltage signal. The current voltage conversion circuit <NUM> feeds the voltage signal to the buffer <NUM>.

The buffer <NUM> corrects the voltage signal from the current voltage conversion circuit <NUM>. The buffer <NUM> outputs a corrected voltage signal to the subtractor <NUM>.

The subtractor <NUM> lowers a level of the voltage signal from the buffer <NUM> in accordance with a row drive signal from the row drive circuit <NUM>. The subtractor <NUM> feeds a lowered voltage signal to the quantizer <NUM>.

The quantizer <NUM> quantizes the voltage signal from the subtractor <NUM> to a digital signal and outputs the digital signal to the transfer circuit <NUM> as the detection signal.

The transfer circuit <NUM> transfers the detection signal from the quantizer <NUM> to the signal processing circuit <NUM> in accordance with a column drive signal from the column drive circuit <NUM>.

<FIG> is a circuit diagram depicting one configuration example of the current voltage conversion circuit <NUM> not according to the claimed invention. The current voltage conversion circuit <NUM> includes N-type transistors <NUM> and <NUM>, and a P-type transistor <NUM>. As each of the transistors, a MOS (Metal-Oxide-Semiconductor) transistor is used, for example.

A source of the N-type transistor <NUM> is connected to a cathode of the photodiode <NUM> and a drain is connected to a power source terminal. The P-type transistor <NUM> and the N-type transistor <NUM> are connected in series between the power source terminal and a ground terminal. In addition, a connection point of the P-type transistor <NUM> and the N-type transistor <NUM> is connected to a gate of the N-type transistor <NUM> and an input terminal of the buffer <NUM>. In addition, a predetermined bias voltage Vbias1 is applied to a gate of the P-type transistor <NUM>.

Drains of the N-type transistors <NUM> and <NUM> are connected to a power source side and such a circuit is called as a source follower. By the two source followers connected in a loop shape, the photocurrent from the photodiode <NUM> is converted into the voltage signal. In addition, the P-type transistor <NUM> feeds a constant current to the N-type transistor <NUM>.

In addition, a ground of the light receiving chip <NUM> and a ground of the detection chip <NUM> are separated each other as an interference countermeasure.

<FIG> is a circuit diagram depicting one configuration example of the subtractor <NUM> and the quantizer <NUM> according to the claimed invention. The subtractor <NUM> includes capacitors <NUM> and <NUM>, an inverter <NUM>, and a switch <NUM>. In addition, the quantizer <NUM> includes a comparator <NUM>.

One end of the capacitor <NUM> is connected to an output terminal of the buffer <NUM> and the other end is connected to the input terminal of the inverter <NUM>. The capacitor <NUM> is connected to the inverter <NUM> in parallel. The switch <NUM> opens and closes a path connecting the both ends of the capacitor <NUM> in accordance with the row drive signal.

The inverter <NUM> inverts the voltage signal input via the capacitor <NUM>. The inverter <NUM> outputs an inverted signal to a noninverted input terminal (+) of the comparator <NUM>.

When the switch <NUM> is turned on, a voltage signal Vinit is input to a buffer <NUM> side of the capacitor <NUM> and the opposite side becomes a virtual ground terminal. A potential of the virtual ground terminal is set to zero for convenience. At this time, when a capacity of the capacitor <NUM> is set to C1, a potential Qinit accumulated on the capacitor <NUM> is represented by the following equation. On the other hand, the both ends of the capacitor <NUM> is short-circuited and an accumulated charge will be zero. [Eq. <NUM>] <MAT>.

Next, where it considers that the switch <NUM> is turned off and the voltage of the buffer <NUM> side of the capacitor <NUM> is changed to be Vafter, a charge Qafter accumulated on the capacitor <NUM> is represented by the following equation. [Eq. <NUM>] <MAT>.

On the other hand, when an output voltage is set to Vout, a charge Q2 accumulated on the capacitor <NUM> is represented by the following equation. [Eq. <NUM>] <MAT>.

At this time, since a total charge amount of the capacitors <NUM> and <NUM> is not changed, the following equation holds. [Eq. <NUM>] <MAT>.

When the equations <NUM> to <NUM> are substituted in the equation <NUM>, which is transformed, the following equation is provided. [Eq. <NUM>] <MAT>.

The equation <NUM> represents a subtraction operation of the voltage signal. A gain of a subtracted result will be C1/C2. Generally, it is desirable to maximize the gain and to design the C1 to be large and the C2 to be small. On the other hand, if the C2 is too small, kTC noise is increased and noise characteristics may be deteriorated. Therefore, a capacity C2 is reduced within the limit of allowable noise. In addition, the address event detection circuit <NUM> including the subtractor <NUM> is loaded for each pixel and the capacities C1 and C2 have thus a surface area limitation. By taking this into consideration, the C1 is set to have a value of <NUM> to <NUM> femtofarads (fF) and the C2 is set to have a value of <NUM> to <NUM> femtofarads (fF).

The comparator <NUM> compares the voltage signal from the subtractor <NUM> with the predetermined threshold voltage Vth applied to the inverted input terminal (-). The comparator <NUM> outputs a signal showing a compared result to the transfer circuit <NUM> as the detection signal.

In a synchronous type solid-state imaging device that images by synchronizing with a vertical synchronizing signal, a simple pixel circuit including a photodiode and three or four transistors is arranged for each pixel. In contrast, in an asynchronous type solid-state imaging device <NUM>, as shown in <FIG>, a pixel circuit including the photodiode <NUM> and the address event detection circuit <NUM>, which is more complex than that of the synchronous type is arranged for each pixel. Accordingly, if the both of the photodiode <NUM> and the address event detection circuit <NUM> is arranged on the same chip, a mounting area will be wider than that of synchronous type. Therefore, in the solid-state imaging device <NUM>, the photodiode <NUM> and the address event detection circuit <NUM> are dispersedly arranged on the light receiving chip <NUM> and the detection chip <NUM> laminated, to thereby reducing the mounting area.

In this way, according to the first embodiment of the present technology, since the photodiode <NUM> is arranged on the light receiving chip <NUM> and the address event detection circuit <NUM> is arranged on the detection chip <NUM>, the mounting area can be reduced as compared with the case that these are mounted on the same chip.

In the above-described first embodiment, the entire current voltage conversion circuit <NUM> is arranged on the detection chip <NUM>, which may increase a circuit scale of the circuit within the detection chip <NUM> along with an increase in the number of pixels. The solid-state imaging device <NUM> according to a modification of the first embodiment is different from that according to the first embodiment in that a part of the circuit of the current voltage conversion circuit <NUM> is arranged on the light receiving chip <NUM>.

<FIG> is a circuit diagram depicting an example of a circuit arranged on each of the light receiving chip <NUM> and the detection chip <NUM> according to the claimed invention. As illustrated in <FIG>, the light receiving chip <NUM> further includes the N-type transistors <NUM> and <NUM> in addition to the photodiode <NUM>. On the other hand, the detection chip <NUM> includes a P-type transistor <NUM> and later stage circuits.

By arranging the N-type transistors <NUM> and <NUM> on the light receiving chip <NUM>, the circuit scale of the detection chip <NUM> can be reduced for the transistors. In addition, as the light receiving chip <NUM> includes only the N-type transistors, the number of process steps of forming the transistors as compared with the case that both of the N-type transistor and the P-type transistor are used. Thus, manufacturing costs of the light receiving chip <NUM> can be reduced.

In this way, according to the modification of the first embodiment of the present technology, since the N-type transistors <NUM> and <NUM> are arranged on the light receiving chip <NUM>, the manufacturing costs and the circuit scale of the detection chip <NUM> can be reduced.

In the above-described first embodiment, the entire current voltage conversion circuit <NUM> is arranged on the detection chip <NUM>, which may increase the circuit scale of the circuit within the detection chip <NUM> along with the increase in the number of pixels. The solid-state imaging device <NUM> according to a second embodiment is different from that according to the first embodiment in that the current voltage conversion circuit <NUM> and the buffer <NUM> within the address event detection circuit <NUM> may be arranged on the light receiving chip <NUM>.

<FIG> is a circuit diagram depicting an example of a circuit arranged on each of the light receiving chip <NUM> and the detection chip <NUM> according to the second embodiment of the present technology. The light receiving chip <NUM> according to the second embodiment further includes the current voltage conversion circuit <NUM> and the buffer <NUM> in addition to the photodiode <NUM>. On the other hand, the detection chip <NUM> includes circuits later than the subtractor <NUM>.

In this way, according to the second embodiment of the present technology, since the current voltage conversion circuit <NUM> and the buffer <NUM> are arranged on the light receiving chip <NUM>, the circuit scale of the detection chip <NUM> can be reduced as compared with the case that these are arranged on the detection chip.

In the above-described second embodiment, the entire subtractor <NUM> is arranged on the detection chip <NUM>, which may increase the circuit scale of the circuit within the detection chip <NUM> along with the increase in the number of pixels. The solid-state imaging device <NUM> according to a first modification of the second embodiment is different from that according to the second embodiment in that a part of the subtractor <NUM> is arranged on the light receiving chip <NUM>.

<FIG> is a circuit diagram depicting an example of a circuit arranged on each of the light receiving chip <NUM> and the detection chip <NUM> according to the first modification of the second embodiment of the present technology.

The capacitor <NUM> within the subtractor <NUM> is arranged on the light receiving chip <NUM>. Note that the capacitor <NUM> is an example of the claimed first capacitor.

On the other hand, the inverter <NUM>, the capacitor <NUM>, and the switch <NUM> within the subtractor <NUM> are arranged on the detection chip <NUM>. Note that the inverter <NUM> is an example of the claimed inverter and the capacitor <NUM> is an example of the claimed second capacitor.

The capacitor such as the capacitors <NUM> and <NUM> generally needs a larger mounting area as compared with the transistor, the diode, or the like. The capacitor <NUM> and capacitor <NUM> are dispersedly arranged on the light receiving chip <NUM> and the detection chip <NUM> laminated, to thereby reducing the mounting area of the whole of the circuit.

In this way, according to the first modification of the second embodiment of the present technology, since the capacitor <NUM> is arranged on the light receiving chip <NUM> and the capacitor <NUM> is arranged on the detection chip <NUM>, the mounting area can be reduced as compared with the case that these are mounted on the same chip.

In the above-described second embodiment, the subtractor <NUM> and the quantizer <NUM> are arranged on the detection chip <NUM>, which may increase the circuit scale of the circuit within the detection chip <NUM> along with the increase in the number of pixels. The solid-state imaging device <NUM> according to the second modification of the second embodiment is different from that according to the second embodiment in that the subtractor <NUM> and the quantizer <NUM> are arranged on the light receiving chip <NUM>.

<FIG> is a circuit diagram depicting an example of a circuit arranged on each of the light receiving chip <NUM> and the detection chip <NUM> according to a second modification of the second embodiment of the present technology. The second modification of the second embodiment of the present technology is different from that according to the second embodiment in that the light receiving chip <NUM> further includes the subtractor <NUM> and the quantizer <NUM> in addition to the photodiode <NUM>, the current voltage conversion circuit <NUM>, and the buffer <NUM>. On the other hand, the detection chip <NUM> includes the transfer circuit <NUM> and the signal processing circuit <NUM>.

In this way, according to the modification of the second embodiment of the present technology, since the subtractor <NUM> and the quantizer <NUM> are arranged on the light receiving chip <NUM>, the circuit scale of the detection chip <NUM> can be reduced as compared with the case that these are mounted on the detection chip <NUM>.

In the above-described first embodiment, the current voltage conversion circuit <NUM> including the N-type transistors <NUM> and <NUM> and the P-type transistor <NUM> is arrayed within the address event detection section <NUM> for each pixel. However, it may increase the circuit scale of the address event detection section <NUM> along with the increase in the number of pixels. The solid-state imaging device <NUM> according to a third embodiment is different from that according to the first embodiment in that only the N-type transistor <NUM> is arranged on the current voltage conversion circuit <NUM>.

<FIG> is a circuit diagram depicting one configuration example of the current voltage conversion circuit <NUM> according to the third embodiment of the present technology. The third embodiment is different from the first embodiment in that only the N-type transistor <NUM> is arranged on the current voltage conversion circuit <NUM>. The gate and a drain of the N-type transistor <NUM> are commonly connected to the power source terminal and the source is connected to the cathode of the photodiode <NUM>. In addition, a connection point of the N-type transistor <NUM> and the photodiode <NUM> is connected to the input terminal of the buffer <NUM>.

Note that also in the third embodiment, the circuits up to the buffer <NUM> can be arranged on the receiving chip <NUM> similar to the second embodiment. In addition, also in the third embodiment, the circuits up to the capacitor <NUM> can be arranged on the light receiving chip <NUM> similar to the first modification of the second embodiment. Furthermore, also in the third embodiment, the circuits up to the quantizer <NUM> can be arranged on the light receiving chip <NUM> similar to the second modification of the second embodiment.

In this way, according to the third embodiment of the present technology, since only the N-type transistor <NUM> is arranged on the current voltage conversion circuit <NUM>, the circuit scale of the current voltage conversion circuit <NUM> can be reduced as compared with the case that three transistors are arranged.

In the above-described first embodiment, the current voltage conversion circuit <NUM> including the N-type transistors <NUM> and <NUM> and the P-type transistor <NUM> is arrayed within the address event detection section <NUM> for each pixel. However, it may increase the circuit scale of the address event detection section <NUM> along with the increase in the number of pixels. The solid-state imaging device <NUM> according to a fourth embodiment is different from that according to the first embodiment in that only the diode is arranged on the current voltage conversion circuit <NUM>.

<FIG> is a circuit diagram depicting one configuration example of the current voltage conversion circuit <NUM> according to the fourth embodiment of the present technology. Only the diode <NUM> is arranged on the current voltage conversion circuit <NUM> according to the fourth embodiment. A cathode of the diode <NUM> is connected to the power source terminal and an anode is connected to the cathode of the photodiode <NUM>. In addition, a connection point of the diode <NUM> and the photodiode <NUM> is connected to the input terminal of the buffer <NUM>.

Note that also in the fourth embodiment, the circuits up to the buffer <NUM> can be arranged on the receiving chip <NUM> similar to the second embodiment. In addition, also in the fourth embodiment, the circuits up to the capacitor <NUM> can be arranged on the light receiving chip <NUM> similar to the first modification of the second embodiment. Furthermore, also in the fourth embodiment, the circuits up to the quantizer <NUM> can be arranged on the light receiving chip <NUM> similar to the second modification of the second embodiment.

In this way, according to the fourth embodiment of the present technology, since only the diode <NUM> is arranged on the current voltage conversion circuit <NUM>, the circuit scale of the current voltage conversion circuit <NUM> can be reduced as compared with the case that the three transistors are arranged.

In the above-described first embodiment, a source follower circuit is arranged on the current voltage conversion circuit <NUM>. In general, the source follower circuit has less good frequency characteristics. Accordingly, when low frequency noise is generated, the noise may not be sufficiently suppressed. The current voltage conversion circuit <NUM> according to a fifth embodiment is different from that according to the first embodiment in that a gate ground circuit is arranged to suppress the low frequency noise.

<FIG> is a circuit diagram depicting one configuration example of the current voltage conversion circuit <NUM> according to the fifth embodiment of the present technology. A constant bias voltage Vbias2 is applied to the gate of the N-type transistor <NUM> according to the fifth embodiment, the drain is connected to the cathode of the photodiode <NUM>, and the source is connected to the connection point of the P-type transistor <NUM> and the N-type transistor <NUM>. Such a gate of the N-type transistor <NUM> is alternately grounded and such a circuit is called as a gate ground circuit. By arranging the gate ground circuit, a closed loop gain is increased and the low frequency noise can be suppressed.

Note that also in the fifth embodiment, the circuits up to the buffer <NUM> can be arranged on the receiving chip <NUM> similar to the second embodiment. In addition, also in the fifth embodiment, the circuits up to the capacitor <NUM> can be arranged on the light receiving chip <NUM> similar to the first modification of the second embodiment. Furthermore, also in the fifth embodiment, the circuits up to the quantizer <NUM> can be arranged on the light receiving chip <NUM> similar to the second modification of the second embodiment.

In this way, according to the fifth embodiment of the present technology, since the gate ground circuit is arranged within the current voltage conversion circuit <NUM>, the low frequency noise can be suppressed as compared with the case that the source follower circuit is arranged.

In the above-described first embodiment, one loop circuit is arranged on the current voltage conversion circuit <NUM>. Only with the one loop circuit, a conversion gain may be insufficient when a current is converted into a voltage. A sixth embodiment is different from the first embodiment in that dual stage loop circuits are arranged on the current voltage conversion circuit <NUM>.

<FIG> is a circuit diagram depicting one configuration example of the current voltage conversion circuit <NUM> according to the sixth embodiment of the present technology. The sixth embodiment is different from the first embodiment in that the current voltage conversion circuit <NUM> further includes N-type transistors <NUM> and <NUM>. As each of the transistors, the MOS transistor is used, for example.

The N-type transistors <NUM> and <NUM> are connected in series between the power source terminal and the photodiode <NUM> and the P-type transistor <NUM> and the N-type transistors <NUM> and <NUM> are connected in series between the power source terminal and the ground terminal. In addition, the gate of the N-type transistor <NUM> is connected to a connection point of the N-type transistors <NUM> and <NUM> and a gate of the N-type transistor <NUM> is connected to a connection point of the P-type transistor <NUM> and the N-type transistor <NUM>.

On the other hand, the gate of the N-type transistor <NUM> is connected to the connection point of the photodiode <NUM> and the N-type transistor <NUM> similar to the first embodiment. A gate of the N-type transistor <NUM> is connected to the connection point of the N-type transistors <NUM> and <NUM>. In addition, the connection point of the P-type transistor <NUM> and the N-type transistor <NUM> is connected to the buffer <NUM>.

Note that the N-type transistors <NUM> and <NUM> are examples of the claimed first N-type transistor and the N-type transistors <NUM> and <NUM> are examples of the second N-type transistor.

As described above, since the loop circuit including the N-type transistors <NUM> and <NUM> and the loop circuit including the N-type transistor <NUM> and <NUM> are connected in a two-stage configuration, the conversion gain becomes twice as compared with only a single loop circuit.

In this way, according to the sixth embodiment of the present technology, since the dual stage loop circuits are arranged on the current voltage conversion circuit <NUM>, the conversion gain can be allowed to increase as compared with only the single loop circuit.

In the above-described first embodiment, the circuits within the solid-state imaging device <NUM> are dispersedly arranged on the two chips. The mounting areas of the circuits within the solid-state imaging device <NUM> may be increased along with the increase in the number of pixels. The solid-state imaging device <NUM> according to a seventh embodiment is different from that according to the first embodiment in that the circuits are dispersedly arranged on three chips.

<FIG> a view depicting an example of a lamination structure of the solid-state imaging device <NUM> according to the seventh embodiment of the present technology. The seventh embodiment is different from the first embodiment in that the solid-state imaging device <NUM> further includes a signal processing chip <NUM> in addition to the light receiving chip <NUM> and the detection chip <NUM>. These chips are laminated.

<FIG> is an example of a plan view of the detection chip <NUM> according to the seventh embodiment of the present technology. The seventh embodiment is different from the first embodiment in that the detection chip <NUM> does not include the row drive circuit <NUM>, the column drive circuit <NUM>, and the signal processing circuit <NUM>. In addition, via arrangement sections <NUM> and <NUM> are arranged in place of the via arrangement sections <NUM>, <NUM>, and <NUM>. Note that the seventh embodiment is similar to the first embodiment except that the via arrangement sections <NUM>, <NUM>, and <NUM> are not arranged on the light receiving chip <NUM>.

<FIG> is an example of a plan view of the signal processing chip <NUM> according to the seventh embodiment of the present technology. The row drive circuit <NUM>, the column drive circuit <NUM>, and the signal processing circuit <NUM> are arranged on the signal processing chip <NUM>.

In this way, since the circuits within the solid-state imaging device <NUM> are dispersedly arranged into three of the light receiving chip <NUM>, the detection chip <NUM>, and the signal processing chip <NUM> and arranged according to the seventh embodiment of the present technology, the mounting area can be further reduced as compared with the case that they are dispersedly arranged into the two.

In the above-described first embodiment, the address event detection circuit <NUM> is arranged on the detection chip <NUM> for each pixel, which may increase the circuit scale of the detection chip <NUM> along with the increase in the number of pixels. The solid-state imaging device <NUM> according to an eighth embodiment is different from that according to the first embodiment in that a plurality of pixels shares one address event detection circuit <NUM>.

<FIG> is an example of a plan view of the light receiving chip <NUM> according to the eighth embodiment of the present technology. The light receiving chip <NUM> according to the eighth embodiment is different from that according to the first embodiment in that a plurality of pixel blocks <NUM> is arrayed in a two-dimensional lattice on the light receiving section <NUM>. A plurality of (for example, four) photodiodes <NUM> is arranged on each pixel block <NUM>. Each pixel address is assigned to each photodiode <NUM>, which are handled as the pixels.

<FIG> is an example of a plan view of the address event detection section <NUM> according to the eighth embodiment of the present technology. A multiplexer <NUM> and the address event detection circuit <NUM> are arranged for each pixel block <NUM> in the address event detection section <NUM> in the eighth embodiment.

The multiplexer <NUM> selects any of the photocurrents from the corresponding plurality of photodiodes <NUM> and feeds the photocurrent to the address event detection circuit <NUM>. The multiplexer <NUM> is controlled, for example, by the row drive circuit <NUM>. The address event detection circuit <NUM> is connected to the corresponding photodiode <NUM> via the multiplexer <NUM>.

In this way, according to the eighth embodiment of the present technology, since a plurality of pixels in the pixel block <NUM> shares one address event detection circuit <NUM>, the circuit scale per pixel can be reduced as compared with the case that the plurality of pixels does not share.

In the above-described eighth embodiment, the multiplexer <NUM> and the address event detection circuit <NUM> are arranged for each pixel on the detection chip <NUM>, which may increase the circuit scale of the detection chip <NUM> along with the increase in the number of pixels. The solid-state imaging device <NUM> according to a modification of the eighth embodiment is different from that according to the first embodiment in that each multiplexer <NUM> is arranged on the light receiving chip <NUM>.

<FIG> is an example of a plan view of the light receiving chip <NUM> according to a modification of the eighth embodiment of the present technology. The light receiving chip <NUM> according to the modification of the eighth embodiment is different from that according to the eighth embodiment in that the multiplexer <NUM> is further arranged on the pixel block <NUM>.

In this way, according to the modification of the eighth embodiment of the present technology, since each multiplexer <NUM> is arranged on the light receiving chip <NUM>, the circuit scale per pixel can be reduced as compared with the case that each multiplexer <NUM> is arranged on the detection chip <NUM>.

In the above-described first embodiment, the circuits are arranged on the light receiving chip <NUM> and the detection chip <NUM>, respectively. By the operation of the circuits, electromagnetic noise may be generated. The solid-state imaging device <NUM> according to a ninth embodiment is different from that according to the above-described first embodiment in that shields are arranged between the light receiving chip <NUM> and the detection chip <NUM>.

<FIG> is a circuit diagram depicting an example of an arrangement position of the shields according to the ninth embodiment of the present technology. The light receiving chip <NUM> according to the ninth embodiment is different from that according to the first embodiment in that the current voltage conversion circuit <NUM> and the buffer <NUM> are further arranged in addition to the photodiode <NUM>. On the other hand, the subtractor <NUM> and the quantizer <NUM> are arranged on the detection chip <NUM>.

In addition, shields <NUM>, <NUM>, and <NUM> are arranged between the light receiving chip <NUM> and the detection chip <NUM>. The shields <NUM> and <NUM> are arranged directly under the photodiode <NUM> with a light receiving chip <NUM> side being upward. The shield <NUM> is arranged directly under the current voltage conversion circuit <NUM>. In addition, the buffer <NUM> and the subtractor <NUM> are connected by the Cu-Cu bonding. And, the shield <NUM> is arranged directly under the buffer <NUM> and a signal line that connects the buffer <NUM> and the subtractor <NUM> is wired through the shield <NUM>. As each of the shields <NUM>, <NUM>, and <NUM>, an electromagnetic shield is used, for example.

Note that, in the ninth embodiment, the photodiode <NUM>, the current voltage conversion circuit <NUM>, and the buffer <NUM> are arranged on the light receiving chip <NUM>, but it is not limited to this configuration. Similar to the first embodiment, only the photodiode <NUM> may be arranged on the light receiving chip <NUM>. In addition, the arrangement may be similar to those of the first modification and the second modification of the second embodiment.

In this way, since the shields <NUM> to <NUM> are arranged between the light receiving chip <NUM> and the detection chip <NUM> according to the ninth embodiment of the present technology, the electromagnetic noise may be prevented from generating.

In the above-described first embodiment, the solid-state imaging device <NUM> images image data including the detection signal. It is not possible to measure a distance from the image data to an object. Example methods of measuring the distance include a method of using a stereo image and a ToF (Time of Flight) method. These methods need to add a camera apart from the imaging lens <NUM> and the solid-state imaging device <NUM>. Thus, in the configuration that the distance is measured by these methods, the number of components and the costs may be increased. The solid-state imaging device <NUM> according to a tenth embodiment is different from that according to the first embodiment in that the distance is measured with each phase difference pixel by using an image plane phase difference method.

<FIG> is an example of a plan view of the light receiving chip <NUM> according to the tenth embodiment of the present technology. The light receiving chip <NUM> according to the tenth embodiment is different from that according to the first embodiment in that a plurality of normal pixels <NUM> and a plurality pairs of phase difference pixels <NUM> are arranged within the light receiving section <NUM>. The normal pixel <NUM> is a pixel for generating the image data. On the other hand, the phase difference pixel <NUM> is a pixel for determining a phase difference between two images.

<FIG> is a circuit diagram depicting one configuration example of the normal pixel <NUM> and the phase difference pixel <NUM> according to the tenth embodiment of the present technology. <FIG> is a circuit diagram depicting one configuration example of the normal pixel <NUM> and <FIG> is a circuit diagram depicting one configuration example of the phase difference pixel <NUM>.

The photodiode <NUM>, the current voltage conversion circuit <NUM>, and the buffer <NUM> are arranged on the normal pixel <NUM>. In addition, the shield <NUM> is arranged directly under the buffer <NUM>. Note that the shields <NUM> and <NUM> may further arranged similar to the ninth embodiment.

On the other hand, the photodiode <NUM>, the current voltage conversion circuit <NUM>, and the buffer <NUM> are arranged on the phase difference pixel <NUM>. The photodiode <NUM>, the current voltage conversion circuit <NUM>, and the buffer <NUM> are configured similar to the photodiode <NUM>, the current voltage conversion circuit <NUM>, and the buffer <NUM>. Note that a part of the photodiode <NUM> is light-shielded with a light shield section <NUM>. In addition, the light-shielded part of one of the pair of the phase difference pixels <NUM> is different from that of the other.

The signal processing circuit <NUM> determines a phase difference from a detection signal from the plurality pairs of phase difference pixels <NUM> and measures the difference from the phase difference. The measured distance is used for an AF (Auto Focus) and the like.

In this way, in the tenth embodiment of the present technology, since the plurality pairs of phase difference pixels <NUM> are arranged, the solid-state imaging device <NUM> can measure the distance toward the object on the basis of the detection signal of each pixel.

In the above-described first embodiment, the current voltage conversion circuit <NUM> is arranged on the detection chip <NUM> for each pixel, which may increase the circuit scale and the mounting area of the detection chip <NUM> along with the increase in the number of pixels. The solid-state imaging device <NUM> according to an eleventh embodiment is different from that according to the first embodiment in that the plurality of pixels shares one current voltage conversion circuit <NUM>.

<FIG> is an example of a plan view of the light receiving chip <NUM> according to the eleventh embodiment of the present technology. The light receiving chip <NUM> according to the eleventh embodiment is different from that according to the first embodiment in that a plurality of pixel blocks <NUM> is arrayed in a two-dimensional lattice within the light receiving section <NUM>.

A plurality of (such as two) photodiodes <NUM>, a multiplexer <NUM>, a current voltage conversion circuit <NUM>, and a buffer <NUM> is arranged on each pixel block <NUM>. The multiplexer <NUM> selects any of photocurrents from the respective plurality of photodiodes <NUM> and feeds the photocurrent to the current voltage conversion circuit <NUM>.

<FIG> is a circuit diagram depicting an example of an arrangement position of a shield according to the eleventh embodiment of the present technology. As shown in <FIG>, the shield <NUM> is arranged directly under the buffer <NUM>. Note that the shields <NUM> and <NUM> may be further arranged similar to the ninth embodiment.

In this way, according to the eleventh embodiment of the present technology, since the plurality of pixels in the pixel block <NUM> shares one current voltage conversion circuit <NUM>, the circuit scale per pixel can be reduced as compared with the case that the plurality of pixels does not share.

In the above-described first embodiment, the solid-state imaging device <NUM> compares the voltage signal with one threshold voltage and generates a <NUM>-bit detection signal for each pixel. However, since only <NUM>-bit information is generated for each pixel, it results in the image data having a poor image quality as compared with the case that a plurality of bits is generated for each pixel. The solid-state imaging device <NUM> according to a twelfth embodiment is different from that according to the first embodiment in that the detection signal of the plurality of bits is generated for each pixel by comparing the voltage signal with the plurality of threshold voltages.

<FIG> is a circuit diagram depicting one configuration example of the buffer <NUM>, the subtractor <NUM>, and the quantizer <NUM> according to the twelfth embodiment of the present technology.

The buffer <NUM> includes N-type transistors <NUM> and <NUM>. The subtractor <NUM> includes capacitors <NUM> and <NUM> and N-type transistors <NUM> to <NUM>. The quantizer <NUM> includes N-type transistors <NUM> to <NUM>. As each of the transistors in the circuit, the MOS transistor is used, for example.

The N-type transistors <NUM> and <NUM> are connected in series between the power source terminal and the ground terminal. In addition, a predetermined bias voltage Vbias3 is applied to a gate of the N-type transistor <NUM> and a gate of the N-type transistor <NUM> is connected to the current voltage conversion circuit <NUM>. A connection point of the N-type transistors <NUM> and <NUM> is connected to one end of the capacitor <NUM>.

In addition, N-type transistors <NUM> and <NUM> are connected in series between the power source terminal and the ground terminal. A predetermined bias voltage Vbias4 is applied to a gate of the N-type transistor <NUM>. The other end of the capacitor <NUM> is connected to a gate of the N-type transistor <NUM>. One end of the capacitor <NUM> is connected to the gate of the N-type transistor <NUM> and the other end is input to a connection point of the N-type transistor <NUM> and <NUM>. A source and a drain of the N-type transistor <NUM> are connected to both ends of the capacitor <NUM> and the row drive signal from the row drive circuit <NUM> is input to the gate. The N-type transistor <NUM> functions as the switch <NUM> illustrated in <FIG>.

In addition, N-type transistors <NUM> and <NUM> are connected in series between the power source terminal and the ground terminal. The N-type transistors <NUM> and <NUM> are also connected in series between the power source terminal and the ground terminal. In addition, gates of the N-type transistors <NUM> and <NUM> are connected to a connection point of the N-type transistors <NUM> and <NUM>. A threshold voltage Vth1 is input to a gate of the N-type transistor <NUM> and a threshold voltage Vth2 lower than the Vth1 is input to a gate of the N-type transistor <NUM>. A <NUM>-bit detection signal at a positive side (+) is output from the connection point of the N-type transistor <NUM> and <NUM> and a <NUM>-bit detection signal at a negative side (-) is output from the connection point of the N-type transistor <NUM> and <NUM>.

With the above-described configuration, the quantizer <NUM> compares the voltage signal with the two threshold voltages and generates the detection signal of <NUM> bits. Accordingly, the solid-state imaging device <NUM> can generate the image data including <NUM>-bit information for each pixel.

In this way, according to the twelfth embodiment of the present technology, since the solid-state imaging device <NUM> compares the voltage signal with the plurality of threshold voltages and generates the detection signal of the plurality of bits for each pixel, the image quality of the image data can be improved as compared with the case that the <NUM>-bit detection signal is generated for each pixel.

The technology of the present disclosure (the present technology) can be applied to a variety of products. For example, the technology of the present disclosure may be realized as a device included in any type of a mobile body such as an automobile, an electric automobile, a hybrid electric automobile, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, and the like.

The vehicle control system <NUM> includes a plurality of electronic control units connected to each other via a communication network <NUM>. In the example depicted in <FIG>, the vehicle control system <NUM> includes a driving system control unit <NUM>, a body system control unit <NUM>, an outside-vehicle information detecting unit <NUM>, an in-vehicle information detecting unit <NUM>, and an integrated control unit <NUM>. In addition, a microcomputer <NUM>, a sound/image output section <NUM>, and a vehicle-mounted network interface (I/F) <NUM> are illustrated as a functional configuration of the integrated control unit <NUM>.

The outside-vehicle information detecting unit <NUM> detects information about the outside of the vehicle including the vehicle control system <NUM>. For example, the outside-vehicle information detecting unit <NUM> is connected with an imaging section <NUM>. The outside-vehicle information detecting unit <NUM> makes the imaging section <NUM> image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit <NUM> may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section <NUM> is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section <NUM> can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section <NUM> may be visible light, or may be invisible light such as infrared rays or the like.

In addition, the microcomputer <NUM> can output a control command to the body system control unit <NUM> on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit <NUM>.

The sound/image output section <NUM> transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of <FIG>, an audio speaker <NUM>, a display section <NUM>, and an instrument panel <NUM> are illustrated as the output device. The display section <NUM> may, for example, include at least one of an on-board display and a head-up display.

The imaging sections <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle <NUM> as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section <NUM> provided to the front nose and the imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle <NUM>. The imaging sections <NUM> and <NUM> provided to the sideview mirrors obtain mainly an image of the sides of the vehicle <NUM>. The imaging section <NUM> provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle <NUM>. The imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, <FIG> depicts an example of photographing ranges of the imaging sections <NUM> to <NUM>. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the front nose. Imaging ranges <NUM> and <NUM> respectively represent the imaging ranges of the imaging sections <NUM> and <NUM> provided to the sideview mirrors. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the rear bumper or the back door. A bird's-eye image of the vehicle <NUM> as viewed from above is obtained by superimposing image data imaged by the imaging sections <NUM> to <NUM>, for example.

At least one of the imaging sections <NUM> to <NUM> may have a function of obtaining distance information. For example, at least one of the imaging sections <NUM> to <NUM> may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer <NUM> can determine a distance to each three-dimensional object within the imaging ranges <NUM> to <NUM> and a temporal change in the distance (relative speed with respect to the vehicle <NUM>) on the basis of the distance information obtained from the imaging sections <NUM> to <NUM>, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle <NUM> and which travels in substantially the same direction as the vehicle <NUM> at a predetermined speed (for example, equal to or more than <NUM>/hour). Further, the microcomputer <NUM> can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

As above, an example of the vehicle control system to which the technology according to the present disclosure is applicable has been described. The technology according to the present disclosure is applicable to the imaging section <NUM> of the above-described configurations. Specifically, the imaging apparatus <NUM> of <FIG> is applicable to the imaging section <NUM> of <FIG>. By applying the technology according to the present disclosure to the imaging section <NUM>, the mounting area of the circuit can be reduced and the imaging section <NUM> can be smaller.

Claim 1:
A solid-state imaging device (<NUM>) comprising:
a photodiode (<NUM>);
a current voltage conversion circuit (<NUM>) which receives a photocurrent from the photodiode and outputs a voltage;
a buffer (<NUM>) which receives the voltage output from the current voltage converter and outputs a buffered voltage;
a subtractor (<NUM>) comprising a first capacitor (<NUM>), an inverter (<NUM>), a second capacitor (<NUM>) and a switch (<NUM>), wherein one end of the first capacitor (<NUM>) is coupled to the output of the buffer (<NUM>), the other end of the first capacitor (<NUM>) is coupled to the input of the inverter (<NUM>), wherein one end of the second capacitor (<NUM>) is coupled to the input of the inverter (<NUM>), the other end of the second capacitor (<NUM>) is coupled to the output of the inverter (<NUM>), wherein the switch (<NUM>) is in parallel to the second capacitor (<NUM>) selectively connecting the input of the inverter (<NUM>) with the output of the inverter (<NUM>), wherein the voltage output of the inverter (<NUM>) is the voltage output from the subtractor (<NUM>);
a quantizer (<NUM>) coupled to the output of the subtractor (<NUM>), the quantizer comprising a comparator (<NUM>) being configured to output an event detection signal based on a comparison of a reference voltage and a voltage output from the subtractor (<NUM>);
a transfer circuit (<NUM>) receiving the event detection signal from the quantizer (<NUM>);
wherein the current voltage conversion circuit (<NUM>) includes:
a first transistor (<NUM>) being an n-type transistor, a gate of the first transistor (<NUM>) coupled to the photodiode (<NUM>),
a second transistor (<NUM>) being an n-type transistor, a source of the second transistor (<NUM>) coupled to the photodiode (<NUM>), and
a third transistor (<NUM>) being a p-type transistor, a drain of the third transistor (<NUM>) coupled to a drain of the first transistor (<NUM>) and a gate of the second transistor (<NUM>),
the voltage at the drain of the first transistor (<NUM>) and the drain of the third transistor (<NUM>) being the voltage output from the current voltage converter (<NUM>),, wherein the solid-state imaging device (<NUM>) further comprises a first chip (<NUM>) including the photodiode (<NUM>), the first transistor (<NUM>) and the second transistor (<NUM>), and a second chip (<NUM>) stacked to the first chip (<NUM>) including the third transistor (<NUM>).