Patent Description:
Self-luminous displays, such as organic light emitting diode (organic light emitting diode, OLED) displays, have attracted extensive attention and have been greatly developed for a long time due to advantages such as self-luminescence, fast reaction, high brightness, and lightness. However, in an existing self-luminous display, due to large leakage currents of some transistors in a pixel circuit, power consumption is relatively high in a scenario of low-frequency driving, for example, in a standby state. As a result, a standby time of a device is reduced. The document <CIT> shows a pixel display, especially comprising an array substrate, and a preparation method thereof. The document <CIT> shows a transistor array panel and a display device including the same.

Embodiments of this application provide a display and an electronic device, to improve a problem of large power consumption of a self-luminous display under low-frequency driving.

To achieve the foregoing objective, this application uses the following technical solutions. According to a first aspect of an embodiment of this application, a display is provided. The display includes a plurality of sub pixels, a substrate, a light-emitting device, a pixel circuit, and an isolation portion. The light-emitting device, the pixel circuit, and the isolation portion are disposed on the substrate. The pixel circuit and the light-emitting device are coupled, and are located in the sub pixel. The pixel circuit includes a first transistor and a second transistor. An active layer of the first transistor includes polycrystalline silicon, and an active layer of the second transistor includes a semiconductor oxide. In addition, the isolation portion includes an isolation base and an isolation retaining wall surrounding the isolation base. The active layer of the second transistor is disposed in a groove formed by the isolation retaining wall and the isolation base. The isolation portion is configured at least to block hydrogen ions in the active layer of the first transistor from being diffused into the active layer of the second transistor.

It can be learned from the foregoing description that, the first transistor is a polycrystalline silicon thin-film transistor, and the second transistor is an oxide thin-film transistor. The isolation portion is composed of the isolation retaining wall and the isolation base. The isolation retaining wall and the isolation base form a groove. Moreover, the active layer of the second transistor is disposed in the groove formed by the isolation retaining wall and the isolation base, and the active layer of the first transistor is disposed outside the groove formed by the isolation retaining wall and the isolation base. Therefore, the isolation portion may be configured to block the hydrogen ions in the active layer of the first transistor from being diffused into the active layer of the second transistor, thereby avoiding a failure of the oxide thin-film transistor after the hydrogen ions in the low-temperature polycrystalline silicon thin-film transistor are diffused into the active layer of the oxide thin-film transistor. In this case, the pixel circuit includes the low-temperature polycrystalline silicon thin-film transistor, and also includes the oxide thin-film transistor. Moreover, the oxide thin-film transistor has a lower off-state current as compared with the low-temperature polycrystalline silicon thin-film transistor. Therefore, during low-frequency driving, power consumption can be reduced, and therefore a standby time can be increased.

Optionally, the display further includes a first gate insulation layer, a first passivation layer, a second passivation layer, and a second gate insulation layer that are sequentially located on the substrate. Materials constituting the first passivation layer include silicon nitride, and materials constituting the second passivation layer include silicon oxide. In addition, the first gate insulation layer is located between the active layer of the first transistor and a first gate, and the active layer of the first transistor is close to the substrate. Moreover, the first gate of the first gate insulation layer is covered by the first passivation layer and the second passivation layer.

In this case, the isolation retaining wall at least penetrates the first gate insulation layer and the first passivation layer, and at least a portion of the second gate insulation layer is located in the isolation retaining wall. In addition, the second gate insulation layer is located between the active layer of the second transistor and a second gate, and the active layer of the second transistor is close to the substrate.

In this way, the isolation retaining wall not only blocks the hydrogen ions in the active layer of the first transistor, but also blocks hydrogen ions in the silicon nitride of the first passivation layer from being diffused into the active layer of the second transistor, thereby avoiding damage caused by the hydrogen ions to the active layer of the second transistor. In addition, the isolation retaining wall at least disconnects the first gate insulation layer from the first passivation layer. Therefore, stress concentration due to an excessively large area of an inorganic oxide material can be avoided. In this way, an internal fracture is avoided when the display is bent.

Optionally, the isolation retaining wall further penetrates the second passivation layer. In this case, the isolation retaining wall penetrates the first gate insulation layer, the first passivation layer, and the second passivation layer. The isolation retaining wall is higher than that in the foregoing solution, and therefore can better block the hydrogen ions in the active layer of the first transistor and the hydrogen ions in the silicon nitride of the first passivation layer from being diffused into the active layer of the second transistor.

According to the claimed invention, the display further includes a common electrode layer. The common electrode layer is located on a side, of the first transistor and the second transistor, that is close to the substrate. A first pole of the first transistor or the second transistor is coupled to the common electrode layer. On this basis, first, the common electrode layer is located on the side, of the first transistor and the second transistor, that is close to the substrate, and is not at a same layer with a source/drain (S/D). Therefore, voltage drop (IR drop) can be reduced, thereby avoiding crosstalk of a data line. In addition, layout space of the data line is reduced, and resolution is improved. Second, the common electrode layer is not located at a position of an upper laminated layer. In this case, a thickness of the laminated layer can be reduced, thereby facilitating continuous bending of the display.

In addition, the isolation base and the common electrode layer are at a same layer, made of a same material, and integrally formed. In this way, a fabrication process can be simplified. The isolation base is formed by using a same mask while the common electrode layer is fabricated.

Optionally, the common electrode layer includes a metal layer, or includes a metal layer and a surface oxide material layer stacked with the metal layer. In this case, a vertical projection, of the active layer of the first transistor, on the substrate is within a range of a vertical projection, of the common electrode layer, on the substrate. Moreover, a vertical projection, of the active layer of the second transistor, on the substrate is within the range of the vertical projection, of the common electrode layer, on the substrate. In this way, the common electrode layer can shelter the active layer of the first transistor and the active layer of the second transistor from being damaged by ambient light, laser lift off (laser lift off, LLO), and other processes during processing. In addition, the common electrode layer is made of a metal material, and therefore can shield entry of an external electric field and electrostatic discharge (electro-static discharge, ESD), thereby improving stability of the light-emitting device.

Optionally, the first transistor further includes a third gate. The third gate is located on a side that is of the first gate of the first transistor and that is close to the substrate, and the first gate in the first transistor is insulated from the third gate. In addition, the third gate of the first transistor is at a same layer and made of a same material as the common electrode layer, and is insulated from the common electrode layer. On this basis, the third gate may be formed by using a same mask while the common electrode layer is fabricated, and therefore a process is simplified. In addition, as compared with a single gate, a driving capability of a transistor can be improved through two gates.

Optionally, the second transistor further includes a fourth gate. The fourth gate is located on a side that is of the second gate of the second transistor and that is close to the substrate, and the second gate in the second transistor is insulated from the fourth gate. In addition, the fourth gate of the second transistor is at a same layer and made of a same material as the common electrode layer, and is insulated from the common electrode layer. On this basis, the fourth gate may be formed by using a same mask while the common electrode layer is fabricated, and therefore a process is simplified. In addition, as compared with a single gate, a driving capability of a transistor can be improved through two gates.

Optionally, materials constituting the substrate include an organic material. In this case, the display further includes a first barrier layer, a first stress relief layer, and a second barrier layer that are sequentially located on the substrate. The active layer of the first transistor is located on a surface of a side that is of the second barrier layer and that is away from the substrate. In addition, the common electrode layer is located between the first barrier layer and the first stress relief layer, and is connected to the first barrier layer and the first stress relief layer. In this case, the common electrode layer can provide a function of supporting the display. For a flexible display, stress on a panel of the display can be made uniform, thereby implementing a continuous bending effect. In addition, a problem of film deformation and scattered bright spots during a production process is improved.

Optionally, the display may further include a first via. The first via sequentially penetrates the first stress relief layer, the second barrier layer, the first gate insulation layer, and the first passivation layer. In addition, a first end of the first via is coupled to the common electrode layer, and a second end of the first via is coupled to the first pole of the first transistor or the second transistor. The first via includes a first metal conductive layer, and the isolation retaining wall and the first metal conductive layer are at a same layer and made of a same material. In this case, the first metal conductive layer may be formed by using a same mask while the isolation retaining wall is fabricated, and therefore a process is simplified.

Optionally, the display further includes a second via. A first end of the second via is coupled to the second end of the first via, and a second end of the second via is coupled to the first pole of the first transistor or the second transistor. In addition, the first via includes a second metal conductive layer, and the second metal conductive layer and the first pole of the first transistor are at a same layer and made of a same material. In this case, the second metal conductive layer may also be formed by using a same mask while the first pole of the first transistor is fabricated, and therefore a process is simplified. In addition, coupling with the common electrode layer can be implemented by connecting the first via to the second via, and this can reduce process difficulty.

Optionally, materials constituting the substrate include an organic material. The display further includes a first barrier layer, a connection layer, and a first stress relief layer that are sequentially located on the substrate. The connection layer is configured to connect the first barrier layer to the first stress relief layer. In addition, the common electrode layer is located between the substrate and the first barrier layer, and is connected to the substrate and the first barrier layer. Alternatively, the display further includes a second barrier layer that is located on a side that is of the first stress relief layer and that is away from the substrate, and the active layer of the first transistor is located on a surface of a side that is of the second barrier layer and that is away from the substrate. The common electrode layer is located between the first stress relief layer and the second barrier layer, and is connected to the first stress relief layer and the second barrier layer. In this case, the common electrode layer can also provide a function of supporting the display. For a flexible display, stress on a panel of the display can be made uniform, thereby implementing a continuous bending effect. In addition, a problem of film deformation and scattered bright spots during a production process is improved.

Optionally, in the isolation retaining wall, the active layer of the second transistor is insulated from the isolation base, and the second barrier layer is disposed on an outer surface that is of the isolation retaining wall and that is away from the active layer of the second transistor.

In this way, first, the active layer of the second transistor may be separated from the isolation base, to avoid electrical connection. Second, a thickness of the second barrier layer is usually much greater than thicknesses of the second passivation layer and the second gate insulation layer. Therefore, when the second barrier layer is disposed on the outer surface that is of the isolation retaining wall and that is away from the active layer of the second transistor, the active layer of the second transistor can be located in the isolation portion, and can be lower than the active layer of the first transistor.

Optionally, materials constituting the substrate include an inorganic material. The display further includes a buffer layer located on the substrate. The common electrode layer is located between the substrate and the buffer layer, and is connected to the substrate and the buffer layer. In addition, the active layer of the second transistor is insulated from the isolation base, and the buffer layer is disposed on an outer surface that is of the isolation retaining wall and that is away from the active layer of the second transistor. On this basis, for a display whose substrate materials include an inorganic material, the common electrode layer may also be used to provide functions of sheltering the active layer of the first transistor and the active layer of the second transistor from being damaged by external light, laser lift off (laser lift off, LLO), and other processes, and shielding entry of an external electric field and electrostatic discharge (electro-static discharge, ESD). In addition, a thickness of the buffer layer is usually much greater than thicknesses of the second passivation layer and the second gate insulation layer. Therefore, when the buffer layer is disposed on the outer surface that is of the isolation retaining wall and that is away from the active layer of the second transistor, the active layer of the second transistor can be located in the isolation portion, and can be lower than the active layer of the first transistor.

Optionally, the pixel circuit further includes a storage capacitor, and the storage capacitor includes a first electrode and a second electrode that are insulated. The first electrode is located on a surface of a side that is of the first gate insulation layer and that is away from the substrate, and first electrode and a gate of the first transistor are at a same layer and made of a same material. In addition, the second electrode is located on a surface of a side that is of the second passivation layer and that is away from the substrate; the second electrode is coupled to the first transistor; and the second electrode and a gate of the second transistor are at a same layer and made of a same material. In this case, the first electrode and the second electrode of the storage capacitor may be fabricated separately by using a same mask while the gate of the first transistor and the gate of the second transistor are fabricated, and therefore a process is simplified.

Optionally, the display further includes a third passivation layer that covers the second gate insulation layer, and the storage capacitor further includes a third electrode. The third electrode is located on a surface of a side that is of the third passivation layer and that is away from the substrate, and covers the second electrode. The third electrode and a first pole of the first transistor are at a same layer and made of a same material. In addition, the display further includes a third via that penetrates the second electrode, and the third electrode is coupled to the first electrode through the third via. On this basis, first, the third passivation layer can block hydrogen ions in the air from being diffused into the active layer of the second transistor during a production process, thereby avoiding damage to the active layer of the second transistor. Second, the foregoing structure can increase a relative area of the capacitor, thereby enhancing an energy storage effect of the capacitor.

Optionally, the first transistor is coupled to the light-emitting device. The first transistor is configured to supply a driving current to the light-emitting device, to quickly turn on the light-emitting device.

According to a second aspect of an embodiment of this application, an electronic device is provided. The electronic device includes any display described above. The electronic device has the same technical effects as the display provided in the foregoing embodiment.

<NUM>: electronic device; <NUM>: display module; <NUM>: middle frame; <NUM>: rear cover; <NUM>: display; <NUM>: pixel circuit; <NUM>: light-emitting part; <NUM>: sub pixel; s: source; d: drain; g: gate; AL: active layer; GL: gate line; Td: driving transistor; Tc: switching transistor; <NUM>: pixel definition layer; <NUM>: anode; <NUM>: light: emitting layer; <NUM>: cathode; <NUM>: hollow-out structure; <NUM>: second pole of a first transistor; <NUM>: first gate; <NUM>: active layer of the first transistor; <NUM>: substrate; <NUM>: first transistor; <NUM>: second transistor; <NUM>: second gate; <NUM>: third passivation layer; <NUM>: second gate insulation layer; <NUM>: second passivation layer; <NUM>: first passivation layer; <NUM>: first gate insulation layer; <NUM>: active layer of the second transistor; <NUM>: isolation retaining wall; <NUM>: isolation base; <NUM>: isolation portion; <NUM>: first barrier layer; <NUM>: first stress relief layer; <NUM>: second barrier layer; <NUM>: groove; <NUM>: first via; <NUM>: second via; <NUM>: first metal conductive layer; <NUM>: second metal conductive layer; <NUM>: common electrode layer; A: first electrode; B: second electrode; E: first end of the first via; F: first end of the second via; Cst: storage capacitor; C: third electrode; D: third via; <NUM>: third gate; <NUM>: fourth gate; <NUM>: connection layer; <NUM>: buffer layer.

The following describes the technical solutions in embodiments of this application with reference to the accompanying drawings in embodiments of this application. Apparently, the described embodiments are merely some rather than all of embodiments of this application.

The following terms "first" and "second" are merely intended for a purpose of description, and shall not be understood as an indication or implication of relative importance or implicit indication of a quantity of indicated technical features. Therefore, a feature limited by "first", "second", or the like may explicitly or implicitly include one or more features. In the descriptions of this application, unless otherwise stated, "a plurality of" means two or more than two.

In addition, in this application, directional terms such as "up" and "down" may include but are not limited to directions of schematically placed components in relative accompanying drawings. It should be understood that these directional terms may be relative concepts. The directional terms are used for relative description and clarification, and may vary correspondingly based on a change in a direction in which the component is placed in the accompanying drawings.

In this application, the term "connection" should be understood in a broad sense unless otherwise expressly specified and limited. For example, the "connection" may be a fixed connection, may be a detachable connection, may be an integral connection; may be a direct connection, or may be an indirect connection implemented by using a medium. In addition, the term "coupling" may be a manner of implementing an electrical connection for signal transmission. The "coupling" may be a direct electrical connection, or may be an indirect electrical connection through an intermediate medium.

An embodiment of this application provides an electronic device. The electronic device includes an electronic product such as a mobile phone (mobile phone), a tablet computer (pad), a computer, a smart wearable product (for example, a smartwatch or a smart band), a set-top box, a media player, a portable electronic device, a virtual reality (virtual reality, VR) terminal device, or an augmented reality (augmented reality, AR) terminal device. A specific form of the electronic device is not particularly limited in this embodiment of this application.

For ease of description, an example in which an electronic device <NUM> is a mobile phone shown in <FIG> is used below. In this case, the electronic device <NUM> mainly includes a display module <NUM>, a middle frame <NUM>, and a rear cover <NUM>. The middle frame <NUM> is located between the display module <NUM> and the rear cover <NUM>. The display module <NUM> and the rear cover <NUM> are separately connected to the middle frame <NUM>. An accommodating cavity formed between the rear cover <NUM> and the middle frame <NUM> is configured to accommodate electronic components such as a battery and a camera (which are not shown in <FIG>), and a printed circuit board (printed circuit board, PCB) shown in <FIG>.

For any electronic device <NUM> described above, the display module <NUM> in the electronic device <NUM> may include a display <NUM> shown in <FIG>. The display <NUM> may include a plurality of sub pixels (sub pixels) <NUM> arranged in rows and columns. A pixel circuit <NUM> and a light-emitting device <NUM> are located in the sub pixel <NUM>. The pixel circuit <NUM> drives the light-emitting device <NUM> to emit light, so that each sub pixel <NUM> in the display <NUM> can be displayed according to a preset gray scale.

For example, the light-emitting device <NUM> may be an organic light-emitting diode (organic light-emitting diode, OLED), a micro light-emitting diode (micro light-emitting diode, mirco LED), or a mini light-emitting diode (mini light-emitting diode, mini LED). For ease of description, descriptions are made below by using an example in which the light-emitting device <NUM> is an OLED.

In some embodiments of this application, the pixel circuit <NUM> may include a plurality of transistors and at least one capacitor. The transistor may be a thin-film transistor (thin film transistor, TFT).

Any one of the foregoing transistors may include a gate (gate, g), an active layer (active layer, AL), a first pole and a second pole is, which is, for example, a drain (drain, d) that are shown in <FIG> (a cross-sectional view of the transistor). For example, the first pole is a source (source, s), and the second pole is a drain (drain, d). Alternatively, the first pole of the transistor may be the drain d, and the second pole may be the source s. This is not limited in this application. For ease of description, the following provides descriptions by using an example in which the first pole of the transistor is the source s and the second pole is the drain d.

The active layer AL is made of a semiconductor material. When the transistor can be turned on by using a voltage applied to the gate g of the transistor, the active layer AL is converted from an insulator into a conductor, so that the source s and the drain g of the transistor are coupled. When the transistor cannot be turned on by using a voltage applied to the gate g of the transistor, the active layer AL is in an insulated state, and the source s of the transistor is disconnected from the drain d thereof.

Performance of the transistor varies with different materials constituting the active layer of the transistor. For example, when the material constituting the active layer of the transistor is polycrystalline silicon (for example, low temperature polycrystalline silicon, low temperature polysilicon, LTPS), due to high electron mobility of the polycrystalline silicon transistor, the polycrystalline silicon transistor is usually applied to a case with a high switching frequency (for example, the electronic device <NUM> is in an on state), to improve switching efficiency. It should be noted that the low temperature polycrystalline silicon is polycrystalline silicon deposited in an environment with a low temperature (for example, a temperature lower than <NUM>).

Alternatively, for another example, when the material constituting the active layer of the transistor is a semiconductor oxide (for example, an amorphous indium gallium zinc oxide, or an indium gallium zinc oxide, IGZO), because the semiconductor oxide transistor has lower electron mobility than a polycrystalline silicon transistor, but has an extremely low off-state current, the semiconductor oxide transistor is usually applied to a case with a low switching frequency (for example, the electronic device <NUM> is in a standby state), and may be configured to reduce a leakage current, thereby reducing power consumption. Hereinafter, for ease of description, a transistor whose active layer is made of polycrystalline silicon is referred to as a first transistor, and a transistor whose active layer is made of a semiconductor oxide is referred to as a second transistor.

On this basis, to enable the pixel circuit <NUM> to be turned on quickly under high-frequency driving (for example, the electronic device <NUM> is in the on state), and to reduce power consumption under low-frequency driving (for example, the electronic device <NUM> is in the standby state), the pixel circuit <NUM> includes at least one first transistor and at least one second transistor that are described above. For example, as shown in <FIG>, the pixel circuit <NUM> may include a driving transistor Td, a switching transistor Tc, and a capacitor Cst. In this case, the pixel circuit <NUM> has a 2T1C structure. "2T" indicates that there are two transistors and "1C" indicates that there is one storage capacitor.

The switching transistor Tc is configured to stay in an on state under control of a gate line (GL), so as to write a data voltage Vdata in a gate g of the driving transistor Td and the storage capacitor Cst. The storage capacitor Cst may maintain a gate voltage of the driving transistor Td, so that the gate voltage of the driving transistor Td can be stabilized within one image frame. In this case, the driving transistor Td can generate a driving current based on the data voltage Vdata, so that the light-emitting device <NUM> can emit light based on the driving current.

In some embodiments of this application, the driving transistor Td in <FIG> may be the first transistor. For example, an active layer of the driving transistor Td is made of LTPS. In addition, the switching transistor Tc may be the second transistor. For example, an active layer of the switching transistor is made of IGZO. In this case, because the driving transistor Td (that is, the first transistor) has high electron mobility, the light-emitting device <NUM> can be quickly turned on when the first transistor is connected to the light-emitting device <NUM>. Moreover, because an off-state current of the second transistor is extremely low, when the second transistor is used as the switching transistor Tc to control on or off of a circuit, a leakage current can be reduced, thereby reducing power consumption and increasing a standby time of the device.

Alternatively, in some other embodiments of this application, the driving transistor Td in <FIG> may be the second transistor. For example, an active layer of the driving transistor Td is made of IGZO. In addition, the switching transistor Tc may be the first transistor. For example, an active layer of the switching transistor Tc is made of LTPS.

In addition, manners for disposing the active layer of the transistor in the pixel circuit are described above by using an example in which the pixel circuit <NUM> has a 2T1C structure. In some other embodiments of this application, to eliminate impact of a threshold voltage (Vth) of the driving transistor Td on luminance of the light-emitting device <NUM> and improve uniformity of the luminance of the light-emitting device, a compensation and initialization module may be added to the pixel circuit. In this case, a quantity of the switching transistors may be increased. For example, the pixel circuit has a 7T1C or an 8T1C structure. In this application, other structures of the pixel circuit <NUM> are not described in detail, provided that it can be ensured that the pixel circuit <NUM> has at least one first transistor (for example, the active layer is made of LTPS) and at least one second transistor (for example, the active layer is made of IGZO). For ease of description, the following provides descriptions by using an example in which the pixel circuit <NUM> has a 2T1C structure and the driving transistor Td in the pixel circuit <NUM> is the first transistor (for example, the active layer is made of LTPS), and the switching transistor Tc is the second transistor (for example, the active layer is made of IGZO).

The following details a structure of the display <NUM> having the pixel circuit <NUM>, that is, the pixel circuit <NUM> includes a first transistor (for example, the active layer is made of LTPS) and a second transistor (for example, the active layer is made of IGZO).

As shown in <FIG> (a sectional view obtained by cutting along the dashed line O-O in <FIG>), the display <NUM> may include a substrate <NUM>, and a first transistor (for example, an active layer is made of LTPS) <NUM> and a second transistor (for example, an active layer is made of IGZO) <NUM> that are disposed on the substrate <NUM>.

In this embodiment of this application, materials constituting the substrate <NUM> may include a rigid material, for example, at least one of glass, sapphire, or a metal material. Alternatively, materials constituting the substrate <NUM> may include a flexible material, such as a macromolecular polymer material.

The first transistor <NUM> serves as the driving transistor Td shown in <FIG>. A second pole, for example, a drain d, of the first transistor <NUM> may be coupled to an anode <NUM> (anode) of the light-emitting device <NUM>. Therefore, as shown in <FIG>, the anode <NUM> of the light-emitting device <NUM> is in contact with the second pole <NUM>, for example, the drain d, of the first transistor <NUM>. In addition, the light-emitting device <NUM> further includes a light-emitting layer <NUM> and a cathode <NUM> that are sequentially located above the anode <NUM>. In addition, the display <NUM> further includes a pixel definition layer (pixel definition layer, PDL) <NUM>. The pixel definition layer <NUM> has a plurality of hollow-out structures <NUM>. One light-emitting device <NUM> may be disposed in a hollow-out structure <NUM>.

It can be learned from the foregoing description that, the first transistor <NUM> includes a gate, a first pole (for example, a source s), a second pole (for example, a drain d), and an active layer AL. In some embodiments of this application, as shown in <FIG>, a first gate insulation layer <NUM> (for example, a silicon oxide SiOx layer) is disposed between a first gate <NUM> and an active layer <NUM> of the first transistor <NUM>. Moreover, the first gate <NUM> is disposed farther from the substrate <NUM> than the first gate insulation layer <NUM>. Therefore, in <FIG>, the first transistor <NUM> is a top-gate transistor. In addition, a first passivation layer <NUM>, a second passivation layer <NUM>, and a second gate insulation layer <NUM> sequentially cover the first gate <NUM>. Materials constituting the first passivation layer <NUM> include silicon nitride (SiNx), and materials constituting the second passivation layer <NUM> include silicon oxide (SiOx).

Similarly, the second gate insulation layer <NUM> is disposed between an active layer <NUM> and a second gate <NUM> of the second transistor <NUM>, and the active layer <NUM> of the second transistor <NUM> is close to the substrate <NUM>. Therefore, the second transistor <NUM> is also a top-gate transistor.

Materials constituting the first gate <NUM> and the second gate <NUM> may be metal materials such as molybdenum (Mo), titanium/aluminum/titanium alloy (Ti/Al/Ti), molybdenum/aluminum/molybdenum alloy (Mo/Al/Mo), and titanium (Ti).

It can be learned from the foregoing description that, the active layer <NUM> of the first transistor <NUM> is made of polycrystalline silicon. To improve electrical performance of the first transistor <NUM>, usually, hydrogen ions are used to fill unsaturated bonds or dangling bonds in the polycrystalline silicon of the active layer <NUM> of the first transistor <NUM> by using a hydrogenation process (for example, a solid-state diffusion method, where silicon nitride (that is, the first passivation layer <NUM>) is used as a hydrogenation source, and the hydrogen ions are diffused into the active layer <NUM> at a high temperature). In this way, a quantity of unstable states in the polycrystalline silicon is reduced, thereby improving electron mobility and improving threshold voltage uniformity.

Moreover, the active layer <NUM> of the second transistor <NUM> is made of a semiconductor oxide, and the active layer <NUM> of the second transistor <NUM> may be damaged by hydrogen ions. Therefore a width of a forbidden band of the active layer <NUM> of the second transistor <NUM> is reduced or even becomes invalid. Therefore, to prevent the hydrogen ions in the first transistor <NUM> from being diffused into the active layer <NUM> of the second transistor <NUM>, in the embodiments of this application, the display <NUM> may further include an isolation portion <NUM> disposed on the substrate <NUM>.

As shown in <FIG>, the isolation portion <NUM> may include an isolation base <NUM> and an isolation retaining wall <NUM> surrounding the isolation base <NUM>. The isolation retaining wall <NUM> penetrates at least the first gate insulation layer <NUM> and the first passivation layer <NUM>, and at least a portion of the second gate insulation layer <NUM> is located in the isolation retaining wall <NUM>. The active layer <NUM> of the second transistor <NUM> is located on a side that is of the second gate insulation layer <NUM> and that is close to the substrate <NUM>. Therefore, the active layer <NUM> of the second transistor <NUM> is disposed in a groove formed by the isolation retaining wall <NUM> and the isolation base <NUM>. However, it can be learned from the foregoing description that, the active layer <NUM> of the first transistor <NUM> adjacent to the second transistor <NUM> is disposed outside the groove formed by the isolation retaining wall <NUM> and the isolation base <NUM>. In this way, in one aspect, the isolation retaining wall <NUM> can block hydrogen ions in the active layer <NUM> of the first transistor <NUM> from being diffused into the active layer <NUM> of the second transistor <NUM>. Moreover, when the active layer <NUM> of the first transistor <NUM> is hydrogenated by using a solid-state diffusion method (for example, silicon nitride (that is, the first passivation layer <NUM>) is used as a hydrogenation source, and the hydrogen ions are diffused into the active layer <NUM> at a high temperature), the first passivation layer <NUM> also has a relatively high content of hydrogen ions. In this case, the isolation retaining wall <NUM> can further block hydrogen ions in the silicon nitride of the first passivation layer <NUM> from being diffused into the active layer <NUM> of the second transistor <NUM>. In this way, the active layer <NUM> of the second transistor <NUM> is prevented from being damaged by the hydrogen ions. In this way, when the pixel circuit <NUM> includes both an LTPS transistor and an IGZO transistor, because the IGZO transistor has an extremely low off-state current as compared with the LTPS transistor, power consumption can be reduced during low-frequency driving (for example, when the pixel circuit <NUM> is applied to a display of a mobile phone, <NUM> driving can be implemented, and power consumption can be reduced by <NUM>% as compared with a device in which the pixel circuit <NUM> uses LTPS only), and a standby time can be increased (for example, when the pixel circuit <NUM> is applied to a wearable product, an ultra-long standby time of for one month can be implemented).

In another aspect, the isolation retaining wall <NUM> disconnects at least the first gate insulation layer <NUM> (for example, SiOx) from the first passivation layer <NUM> (SiNx). Therefore, stress concentration due to an excessively large area of an inorganic nitrogen oxide material can be avoided. In this way, a problem of an internal fracture is avoided when the display is bent.

In addition, in some embodiments of this application, the display <NUM> may further include a third passivation layer <NUM> that covers the second gate insulation layer <NUM>. Materials constituting the third passivation layer <NUM> may include silicon oxide (SiOx). The third passivation layer <NUM> covers a surface of the second transistor <NUM>, and the second gate <NUM> is located on a side that is of the active layer <NUM> of the second transistor <NUM> and that is away from the substrate <NUM>. Therefore, the third passivation layer <NUM> and the second gate <NUM> may be further configured to block hydrogen ions in the air from being diffused into the active layer <NUM> of the second transistor <NUM> during a production process, thereby avoiding damage to the active layer <NUM> of the second transistor <NUM>.

The structure of the display <NUM> having the foregoing isolation portion <NUM> is described below by using examples.

In this example, the display <NUM> is a flexible display. As shown in <FIG>, the materials constituting the substrate <NUM> include an organic material, such as polyimide (polyimide, PI). The display <NUM> further includes a first barrier layer <NUM> (for example, silicon oxide, SiOx), a first stress relief layer <NUM> (for example, PI), and a second barrier layer <NUM> (for example, silicon oxide, SiOx) that are sequentially located on the substrate <NUM>.

In some embodiments of this application, a process of fabricating the display <NUM> having a structure of the isolation portion <NUM> is as follows.

First, as shown in <FIG>, the first barrier layer <NUM> is formed on the substrate <NUM> through chemical vapor deposition (chemical vapor deposition, CVD), and then the isolation base <NUM> is formed on a surface of the first barrier layer <NUM> through physical vapor deposition (physical vapor deposition, PVD).

Subsequently, the first stress relief layer <NUM> is coated on the isolation base <NUM> by using a coating process, and then the second barrier layer <NUM> is formed, by using a CVD process, on the substrate on which the first stress relief layer <NUM> is fabricated. It should be noted that the isolation base <NUM> may be disposed on any layer between the substrate <NUM> and the second barrier layer <NUM>. For ease of description, in this example, the isolation base <NUM> is disposed between the first barrier layer <NUM> and the first stress relief layer <NUM>.

Subsequently, the active layer <NUM> of the first transistor <NUM> is formed on a surface of a side that is of the second barrier layer <NUM> and that is away from the substrate <NUM>. Afterwards, the active layer <NUM> of the first transistor <NUM> is covered by the first gate insulation layer <NUM>, and then the first gate <NUM> is formed, by using a PVD process, on a surface of a side that is of the first gate insulation layer <NUM> and that is away from the substrate <NUM>. Then, the first passivation layer <NUM> is covered on the first gate <NUM>.

In this case, as shown in <FIG>, a groove <NUM> may be formed on one side (for example, the right side) of the first transistor <NUM> by using a dry etching process. A fully transparent mask may be first used to etch a position on a side that is of the first stress relief layer <NUM> and that is away from the substrate <NUM>. Subsequently, a semitransparent mask is used, so that the first stress relief layer <NUM> in the groove <NUM> is retained, and a position at which the isolation retaining wall <NUM> is located is etched. The isolation retaining wall <NUM> communicates with the isolation substrate <NUM>. Subsequently, the isolation retaining wall <NUM> is formed on a side wall of the groove <NUM> by using the PVD process, so that the isolation retaining wall <NUM> is electrically connected to the isolation base <NUM>.

It should be noted that a material constituting the isolation portion <NUM> may be titanium/aluminum/titanium (Ti/A/Ti), molybdenum/aluminum/molybdenum (Mo/Al/Mo), molybdenum (Mo), copper (Cu), or the like. Materials of the isolation base <NUM> and the isolation retaining wall <NUM> may be the same or may be different.

Because the material constituting the isolation base <NUM> is a metal material, as shown in <FIG>, the active layer <NUM> of the second transistor <NUM> needs to be isolated from the isolation base <NUM> by using at least one insulation layer. In some embodiments of this application, as shown in <FIG>, the second passivation layer <NUM> and the first stress relief layer <NUM> are disposed between the active layer <NUM> of the second transistor <NUM> and the isolation base <NUM>. Therefore, as shown in <FIG>, during forming of the groove <NUM>, when an electrical connection between the isolation retaining wall <NUM> and the isolation base <NUM> is ensured, at least a portion of each of the second barrier layer <NUM>, the first gate insulation layer <NUM>, and the first passivation layer <NUM> that are located at a bottom of the groove <NUM> may be etched, so that the active layer <NUM> is insulated from the isolation base <NUM> by using the second passivation layer <NUM> and the first stress relief layer <NUM>.

It should also be noted that, when the groove <NUM> is formed on one side (for example, the right side) of the first transistor <NUM> by using the dry etching process, and when the active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM>, the second barrier layer <NUM> further needs to be disposed on an outer surface that is of the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM> (as shown in <FIG>). Because a thickness of the second barrier layer <NUM> is usually greater than thicknesses of the first passivation layer <NUM> and the second passivation layer <NUM>, when the second barrier layer <NUM> is disposed on the outer surface that is of the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>, the active layer <NUM> of the second transistor <NUM> may be made lower than the active layer <NUM> of the first transistor <NUM>, thereby better blocking hydrogen ions from being diffused into the active layer <NUM> of the second transistor <NUM>. Alternatively, a first thickness of a portion, of the second barrier layer <NUM>, that is located on the isolation retaining wall <NUM> and that is close to the active layer <NUM> of the second transistor <NUM> may be made less than a second thickness of a portion, of the second barrier layer <NUM>, that is located on the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>. The thickness is a length in a direction in which the second barrier layer <NUM> grows when the second barrier layer <NUM> is deposited on the substrate <NUM>. In this case, a size of the first thickness may be adjusted, so that the active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM>, and the active layer <NUM> of the second transistor <NUM> is lower than the active layer <NUM> of the first transistor <NUM>, thereby better blocking hydrogen ions from being diffused into the active layer <NUM> of the second transistor <NUM>.

Subsequently, as shown in <FIG>, the second passivation layer <NUM> and the second gate insulation layer <NUM> are sequentially formed, by using the CVD process, on a surface of a side that is of the first passivation layer <NUM> and that is away from the substrate <NUM>. In this case, a portion of the second passivation layer <NUM> and a portion of the second gate insulation layer <NUM> are located in the isolation retaining wall <NUM>. Afterwards, the active layer <NUM> and the second gate <NUM> of the second transistor <NUM> are respectively formed on two sides of the second gate insulation layer <NUM> by using a same process as that for the first transistor <NUM>.

Then, a third passivation layer <NUM> is formed, by using the CVD process, on a surface of a side that is of the second gate insulation layer <NUM> and that is away from the substrate <NUM>. Subsequently, a source s and a drain d are respectively formed, by using the PVD process, at two ends of each of the active layer <NUM> of the first transistor <NUM> and the active layer <NUM> of the second transistor <NUM>.

In addition, in <FIG>, to ensure that the active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM>, the second passivation layer <NUM> and the first stress relief layer <NUM> are disposed between the active layer <NUM> of the second transistor <NUM> and the isolation base <NUM>. In some other embodiments of this application, as shown in <FIG>, only the second passivation layer <NUM> may be disposed between the active layer <NUM> of the second transistor <NUM> and the isolation base <NUM>. Therefore, when the groove <NUM> is formed, at least a portion of each of the second barrier layer <NUM>, the first gate insulation layer <NUM>, the first passivation layer <NUM>, and the first stress relief layer <NUM> that are located at the bottom of the groove <NUM> may be etched, so that the active layer <NUM> is insulated from the isolation base <NUM> by using the second passivation layer <NUM>. In this case, the second barrier layer <NUM> is disposed on the outer surface that is of the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>. It should be noted that in this example, other fabrication processes are as described above, and details are not described herein again.

To ensure that the active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM>, in some other embodiments of this application, as shown in <FIG>, the first stress relief layer <NUM>, the second passivation layer <NUM>, and a portion of the second barrier layer <NUM> may be disposed between the active layer <NUM> of the second transistor <NUM> and the isolation base <NUM> (compared with the solution described in <FIG>, a portion of the second barrier layer <NUM> is additionally disposed between the active layer <NUM> of the second transistor <NUM> and the isolation base <NUM>). Therefore, when the groove <NUM> is formed, at least a portion of each of the second barrier layer <NUM>, the first gate insulation layer <NUM>, and the first passivation layer <NUM> that are located at the bottom of the groove <NUM> may be etched, where the second barrier layer <NUM> at the bottom of the groove <NUM> is partially etched, so that the active layer <NUM> is insulated from the isolation base <NUM> by using the first stress relief layer <NUM>, the second passivation layer <NUM>, and a portion of the second barrier layer <NUM>. In this case, regarding the second barrier layer <NUM>, a first thickness of a portion, of the second barrier layer <NUM>, that is located on the isolation retaining wall <NUM> and that is close to the active layer <NUM> of the second transistor <NUM> is less than a second thickness of a portion, of the second barrier layer <NUM>, that is located on the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>. It should be noted that in this example, other fabrication processes are as described above, and details are not described herein again.

In some other embodiments of this application, as shown in <FIG>, the isolation retaining wall <NUM> may further penetrate the second passivation layer <NUM>. In this case, a process of fabricating the display <NUM> having the structure of the isolation portion <NUM> is as follows.

The first barrier layer <NUM>, the first stress relief layer <NUM>, the second barrier layer <NUM>, the active layer <NUM> of the first transistor <NUM>, the first gate insulation layer <NUM>, the first passivation layer <NUM>, and the second passivation layer <NUM> are sequentially fabricated on the substrate <NUM>. Fabrication processes of the foregoing layers are as described above, and are not described herein again. Subsequently, on the substrate on which the second passivation layer <NUM> is formed, the groove <NUM> is formed on one side (for example, the right side) of the first transistor <NUM> by using the dry etching process.

It can be learned from the foregoing description that, to determine which layer needs to be etched in the groove <NUM>, at least the following condition needs to be satisfied: the active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM>, and the second barrier layer <NUM> is disposed on the outer surface that is of the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>; or the active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM>, and a first thickness of a portion, of the second barrier layer <NUM>, that is located on the isolation retaining wall <NUM> and that is close to the active layer <NUM> of the second transistor <NUM> is less than a second thickness of a portion, of the second barrier layer <NUM>, that is located on the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>. A size of the first thickness may be adjusted, so that the active layer <NUM> of the second transistor <NUM> is lower than the active layer <NUM> of the first transistor <NUM>.

In <FIG>, for example, when the groove <NUM> is formed, at least a portion of each of the second barrier layer <NUM>, the first gate insulation layer <NUM>, the first passivation layer <NUM>, and the second passivation layer <NUM> that are located at the bottom of the groove <NUM> may be etched. In this case, the active layer <NUM> is insulated from the isolation base <NUM> by using the first stress relief layer <NUM>, and the second barrier layer <NUM> is disposed on the outer surface that is of the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>, as described above. Other disposing manners are as described above, and details are not be described herein again.

Subsequently, the second gate insulation layer <NUM> is formed, by using the CVD process, on a surface of a side that is of the second passivation layer <NUM> and that is away from the substrate <NUM>. In this case, a portion of the second gate insulation layer <NUM> is located in the isolation retaining wall <NUM>. Other processes are as described above, and details are not described herein again.

For ease of description, the following provides descriptions by using an example in which the isolation retaining wall <NUM> penetrates the first gate insulation layer <NUM> and the first passivation layer <NUM>.

As shown in <FIG>, when the driving transistor Td is turned on, a current path is formed between a first voltage VDD and a second voltage VSS, so that a driving current generated by the driving transistor Td can flow into the light-emitting device <NUM>, to drive the light-emitting device <NUM> to emit light. In this case, to supply the first voltage VDD to the pixel circuit <NUM> in each sub pixel <NUM>, the display further includes a common electrode layer <NUM>, as shown in <FIG>. The common electrode layer <NUM> can be coupled to a source s of the driving transistor Td in each pixel circuit <NUM>, so as to supply the first voltage VDD to each pixel circuit <NUM>.

Manners for disposing the common electrode layer <NUM> are described below in detail.

In this example, as shown in <FIG>, the common electrode layer <NUM> may be disposed between the first barrier layer <NUM> and the first stress relief layer <NUM>. It can be learned from the foregoing description that, the isolation base <NUM> in the isolation portion <NUM> is located between the first barrier layer <NUM> and the first stress relief layer <NUM>, and the isolation base <NUM> is made of a metal material. Therefore, to simplify a fabrication process, the isolation base <NUM> and the common electrode layer <NUM> is disposed at a same layer and made of a same material, and is integrally formed. In this way, fabrication of the common electrode layer <NUM> may be completed while the isolation substrate <NUM> is fabricated.

It should be noted that "a same layer" refers to a layer structure formed by first forming a film layer for forming a particular pattern through a same film forming process (for example, a coating process), and then by using a same mask (mask) through a single patterning process. Based on different particular patterns, a same patterning process may include a plurality of exposure, development, or etching processes. Moreover, the particular patterns in the formed layer structure may be continuous or discontinuous, and these particular patterns may also have different heights or different thicknesses.

Therefore, as shown in <FIG>, the display <NUM> further includes the common electrode layer <NUM>. The common electrode layer <NUM> is located between the first barrier layer <NUM> and the first stress relief layer <NUM>, and is connected to the first barrier layer <NUM> and the first stress relief layer <NUM>.

The common electrode layer <NUM> includes a metal layer, or the common electrode layer <NUM> includes a metal layer and a surface oxide material layer stacked with the metal layer. For example, the common electrode layer <NUM> includes titanium/aluminum/titanium (Ti/Al/Ti), molybdenum/nickel/copper (Mo/Ni/Cu), copper (Cu), stainless steel (SUS), indium tin oxide (ITO), and a surface oxide layer including the Ti/Al/Ti, the Mo/Ni/Cu, the Cu, the SUS, and the ITO.

To implement the coupling between the common electrode layer <NUM> and the source s of the driving transistor Td (that is, the first transistor <NUM> or the second transistor <NUM>, where the first transistor is used as an example in <FIG>), the display <NUM> may further include a first via <NUM> and a second via <NUM>. In some embodiments of this application, the first via <NUM> successively penetrates the first stress relief layer <NUM>, the second barrier layer <NUM>, the first gate insulation layer <NUM>, and the first passivation layer <NUM>. Moreover, a first end E of the first via <NUM> is coupled to the common electrode layer <NUM>, and a second end (that is, an end opposite to the end E) of the first via <NUM> is coupled to the first pole (not shown in the figure) of the first transistor <NUM> or the second transistor <NUM>. In addition, the first via <NUM> may include a first metal conductive layer <NUM>, and the first metal conductive layer <NUM> and the isolation retaining wall <NUM> are at a same layer and made of a same material.

In addition, a first end F of the second via <NUM> is coupled to the second end (that is, the end opposite to the end E) of the first via hole <NUM>, and a second end (that is, an end opposite to the end F) of the second via <NUM> is coupled the first pole (not shown in the figure) of the first transistor <NUM> or the second transistor <NUM>. In addition, the second via <NUM> may include a second metal conductive layer <NUM>, and the second metal conductive layer <NUM> and the first pole of the first transistor <NUM> are at the same layer and made of a same material.

It should be noted that a material constituting the first metal conductive layer <NUM> may be titanium/aluminum/titanium (Ti/Al/Ti), molybdenum/aluminum/molybdenum (Mo/Al/Mo), molybdenum (Mo), copper (Cu), or the like. The first metal conductive layer <NUM> and the isolation retaining wall <NUM> penetrate same film layers (for example, the first stress relief layer <NUM>, the second barrier layer <NUM>, the first gate insulation layer <NUM>, and the first passivation layer <NUM>). Therefore, the first metal conductive layer <NUM> and the isolation retaining wall <NUM> may be at a same layer and made of a same material. In this way, the first metal conductive layer <NUM> may be formed by using a same mask while the isolation retaining wall <NUM> is fabricated, and therefore a process is simplified.

In addition, a material constituting the second metal conductive layer <NUM> may be titanium/aluminum/titanium (Ti/Al/Ti), copper (Cu), molybdenum/nickel/copper (Mo/Ni/Cu), molybdenum/aluminum/molybdenum (Mo/Al/Mo), or another material. The second metal conductive layer <NUM> and the first pole (or the second pole) of the first transistor <NUM> penetrate same film layers (for example, the second passivation layer <NUM>, the second gate insulation layer <NUM>, and the third passivation layer <NUM>). Therefore, the second metal conductive layer <NUM> and first pole (or the second pole) of the first transistor <NUM> may be at a same layer and made of a same material. In this way, the second metal conductive layer <NUM> may be formed by using a same mask while the first pole (or the second pole) of the first transistor <NUM> is fabricated, and therefore a process is simplified.

Subsequently, process difficulty can be reduced by classifying vias into the first via <NUM> and the second via <NUM>.

It can be learned from the foregoing description that, in the embodiments of this application, the common electrode layer <NUM> is disposed on a side that is of the transistor TFT and that is close to the substrate <NUM>, and is not at a same layer with the source/drain (S/D). In this way, voltage drop (IR drop) can be reduced, thereby avoiding crosstalk of a data line. In addition, layout space of the data line is reduced, and resolution is improved. Moreover, the common electrode layer <NUM> is not located at a position of an upper laminated layer. In this case, a thickness of the laminated layer can be reduced, thereby facilitating continuous bending of the display. Further, because the common electrode layer <NUM> is made of a metal material and is electrically connected to the first pole of the first transistor <NUM>, an external electric field and electrostatic discharge (electro-static discharge, ESD) can be shielded from entering the display <NUM>, thereby improving stability of the light-emitting device <NUM>. Subsequently, because the rigidity of the metal material is greater than that of an inorganic material or an organic material, when the common electrode layer <NUM> is added on the substrate <NUM>, the common electrode layer <NUM> can provide a function of supporting the display. For a flexible display, stress on a panel of the display can be made uniform, thereby implementing a continuous bending effect. In addition, a problem of film deformation and scattered bright spots during a production process is improved. Finally, the common electrode layer <NUM> may further shelter the active layer <NUM> of the first transistor <NUM> and the active layer <NUM> of the second transistor <NUM> from being damaged by ambient light, laser lift off (laser lift off, LLO), and other processes during processing.

To shelter the active layer <NUM> of the first transistor <NUM> and the active layer <NUM> of the second transistor <NUM>, the common electrode layer <NUM> may have a shape of a thin film layer that covers the entire substrate <NUM>, or may be a thin film layer having a hollow-out pattern. The hollow-out pattern may include a grid-like pattern, a mesh-like pattern, and the like. However, when the common electrode layer <NUM> has a hollow-out pattern, at least the following needs to be satisfied: a vertical projection, of the active layer <NUM> of the first transistor <NUM>, on the substrate <NUM> is within a range of a vertical projection, of the common electrode layer <NUM>, on the substrate <NUM>; and a vertical projection, of the active layer <NUM> of the second transistor <NUM>, on the substrate <NUM> is within the range of the vertical projection, of the common electrode layer <NUM>, on the substrate <NUM>.

It can be learned from <FIG> that, the display <NUM> may further include a storage capacitor Cst, to maintain the gate voltage of the driving transistor Td (that is, the first transistor <NUM>), so that the gate voltage of the driving transistor Td (that is, the first transistor <NUM>) can be stabilized in one image frame. Therefore, in some embodiments of this application, as shown in <FIG>, the storage capacitor Cst may further include a first electrode A and a second electrode B that are insulated. The first electrode A is located on the surface of the side that is of the first gate insulation layer <NUM> and that is away from the substrate <NUM>. The first electrode A and the gate <NUM> of the first transistor <NUM> are at a same layer and made of a same material. In addition, the second electrode B is located on the surface of the side that is of the second passivation layer <NUM> and that is away from the substrate <NUM>; the second electrode B is coupled to the first transistor <NUM>; and the second electrode B and the gate <NUM> of the second transistor <NUM> are at a same layer and made of a same material. In this case, the second electrode B is an upper plate of the storage capacitor Cst, and the first electrode A is a lower plate of the storage capacitor.

Therefore, the first electrode A and the second electrode B of the storage capacitor Cst may be fabricated separately by using a same mask while the first gate <NUM> of the first transistor <NUM> and the second gate <NUM> of the second transistor <NUM> are fabricated, and therefore a process is simplified.

It should be noted that, positions of the first electrode A and the second electrode B of the storage capacitor Cst are not limited in this application. The first electrode A and the second electrode B may be disposed at different laminated layers based on a requirement (for example, the first electrode A may be disposed on the first gate insulation layer <NUM>, and is at a same layer and made of a same material as the active layer <NUM> of the first transistor <NUM>), provided that the first electrode A and the second electrode B are not at a same laminated layer.

Alternatively, in some other embodiments of this application, as shown in <FIG>, the storage capacitor Cst may include a first electrode A, a second electrode B, and a third electrode C located between the first electrode A and the second electrode B. The third electrode C is located on a surface of a side that is of the third passivation layer <NUM> and that is away from the substrate <NUM>, and covers the second electrode B. The third electrode C and the first pole of the first transistor <NUM> are at a same layer and made of a same material. The display <NUM> further includes a third via D that penetrates the second electrode B, and the third electrode C is coupled to the first electrode A through the third via D. In this case, the third electrode C is electrically connected to the first electrode A, and is equivalent to a pole of the storage capacitance Cst. Moreover, the second electrode B is equivalent to the other pole of the storage capacitance Cst. Compared with the solution described above (the solution in which the storage capacitor Cst includes only the first electrode A and the second electrode B), a relative area of the two poles of the storage capacitor Cst is increased. In this way, an energy storage effect of the storage capacitor Cst is enhanced. Similarly, positions of the first electrode A and the second electrode B in the storage capacitor Cst are not limited in this application. The first electrode A and the second electrode B may be disposed at different laminated layers based on a requirement, provided that the first electrode A and the second electrode B are not at a same laminated layer.

The foregoing descriptions are provided by using an example in which the first transistor <NUM> and the second transistor <NUM> each belongs to a top-gate type. In some other embodiments of this application, the first transistor <NUM> may alternatively have a double-gate structure. In this case, as shown in <FIG>, in addition to the first gate <NUM>, the first transistor <NUM> further includes a third gate <NUM>.

In this case, the third gate <NUM> is at a same layer and made of a same material as the common electrode layer <NUM>, and is insulated from the common electrode layer <NUM>. The third gate <NUM> is located on a side that is of the first gate <NUM> of the first transistor <NUM> and that is close to the substrate <NUM>, and the first gate <NUM> in the first transistor <NUM> is insulated from the third gate <NUM>. On this basis, the third gate <NUM> may be formed by using a same mask while the common electrode layer <NUM> is fabricated, and therefore a process is simplified. In addition, as compared with a single gate, a driving capability of the first transistor <NUM> can be improved through two gates.

In some other embodiments of this application, the second transistor <NUM> may also have a double-gate structure. In this case, as shown in <FIG>, in addition to the first gate <NUM>, the second transistor <NUM> further includes a fourth gate <NUM>. In this case, the fourth gate <NUM> is at a same layer and made of a same material as the common electrode layer <NUM>, and is insulated from the common electrode layer <NUM>. The fourth gate <NUM> is located on a side that is of the second gate <NUM> of the second transistor <NUM> and that is close to the substrate <NUM>, and the second gate <NUM> in the second transistor <NUM> is insulated from the fourth gate <NUM>. On this basis, the second gate may be formed by using a same mask while the common electrode layer is fabricated, and therefore a process is simplified. In addition, as compared with a single gate, a driving capability of the second transistor <NUM> can be improved through two gates.

It should be noted that <FIG> is described by using an example in which the first transistor <NUM> has a double-gate structure and the second transistor <NUM> has a top-gate structure, and <FIG> is described by using an example in which the first transistor <NUM> has a top-gate structure and the second transistor <NUM> has a double-gate structure. In some other embodiments of this application, both the first transistor <NUM> and the second transistor <NUM> may have a double-gate structure. This is not limited in this application.

This example is the same as Example <NUM> in that the display <NUM> is a flexible display. As shown in <FIG>, the materials constituting the substrate <NUM> include an organic material. The display <NUM> further includes a first barrier layer <NUM>, a first stress relief layer <NUM>, and a second barrier layer <NUM> that are sequentially located on the substrate <NUM>. The active layer <NUM> of the first transistor <NUM> is located on a surface of a side that is of the second barrier layer <NUM> and that is away from the substrate <NUM>. Different from Example <NUM>, there is a connection layer <NUM> between the first barrier layer <NUM> and the first stress relief layer <NUM>. The connection layer <NUM> is configured to increase an adhesion force between the first barrier layer <NUM> and the first stress relief layer <NUM>.

In this example, a common electrode layer <NUM> is located between the substrate <NUM> and the first barrier layer <NUM>, and is connected to the substrate <NUM> and the first barrier layer <NUM>. It can be learned from the foregoing description that, the common electrode layer <NUM> and the isolation base <NUM> may be at a same layer and made of a same material. Therefore, as shown in <FIG>, the isolation base <NUM> is also located between the substrate <NUM> and the first barrier layer <NUM>.

In this case, the isolation retaining wall <NUM> may penetrate the first passivation layer <NUM> to the first barrier layer <NUM>, and may be electrically connected to the common electrode layer <NUM>. The active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM> by using the first barrier layer <NUM>, the connection layer <NUM>, the first stress relief layer <NUM>, and the second passivation layer <NUM>. In this case, the second barrier layer <NUM> is disposed on an outer surface that is of the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>.

It should be noted that, disposing of an insulation layer between the active layer <NUM> of the second transistor <NUM> and the isolation base <NUM> is not limited in this application, provided that the following is satisfied: the active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM>, and the second barrier layer <NUM> is disposed on the outer surface that is of the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>; or the active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM>, and a first thickness of a portion, of the second barrier layer <NUM>, that is located on the isolation retaining wall <NUM> and that is close to the active layer <NUM> of the second transistor <NUM> is less than a second thickness of a portion, of the second barrier layer <NUM>, that is located on the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>. A size of the first thickness may be adjusted, so that the active layer <NUM> of the second transistor <NUM> is lower than the active layer <NUM> of the first transistor <NUM>. A specific disposing method is as described above, and details are not described herein again.

In this example, the isolation retaining wall <NUM> may further penetrate the second passivation layer <NUM>. A method for disposing the isolation retaining wall <NUM> is as described above, and details are not described herein again. In addition, manners for disposing the first transistor <NUM>, the second transistor <NUM>, and the storage capacitor Cst are as described above, and details are not described herein again.

This example is the same as Example <NUM> in that the display <NUM> is a flexible display. As shown in <FIG>, the materials constituting the substrate <NUM> include an organic material. The display <NUM> includes a first barrier layer <NUM>, a first stress relief layer <NUM>, and a second barrier layer <NUM> that are sequentially located on the substrate <NUM>. The active layer <NUM> of the first transistor <NUM> is located on a surface of a side that is of the second barrier layer <NUM> and that is away from the substrate <NUM>. Different from Example <NUM>, there is a connection layer <NUM> between the first barrier layer <NUM> and the first stress relief layer <NUM>. The connection layer <NUM> is configured to increase an adhesion force between the first barrier layer <NUM> and the first stress relief layer <NUM>.

In this example, a common electrode layer <NUM> is located between the stress relief layer <NUM> and the second barrier layer <NUM>, and is connected to the first stress relief layer <NUM> and the second barrier layer <NUM>. It can be learned from the foregoing description that, the common electrode layer <NUM> and the isolation base <NUM> may be at a same layer and made of a same material. Therefore, as shown in <FIG>, the isolation base <NUM> is also located between the first stress relief layer <NUM> and the second barrier layer <NUM>.

In this case, the isolation retaining wall <NUM> may penetrate the first passivation layer <NUM> to the first barrier layer <NUM>, and may be electrically connected to the common electrode layer <NUM>. The active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM> by using the second passivation layer <NUM>. In this case, the second barrier layer <NUM> is disposed on an outer surface that is of the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>.

This example is different from Example <NUM>. In this example, the display <NUM> is a rigid display. As shown in <FIG>, the materials constituting the substrate <NUM> include an inorganic material, and the display <NUM> further includes a buffer layer <NUM> located on the substrate <NUM>.

In this example, a common electrode layer <NUM> is located between the substrate <NUM> and the buffer layer <NUM>, and is connected to the substrate <NUM> and the buffer layer <NUM>. It can be learned from the foregoing description that, the common electrode layer <NUM> and the isolation base <NUM> may be at a same layer and made of a same material. Therefore, as shown in <FIG>, the isolation base <NUM> is also located between the substrate <NUM> and the buffer layer <NUM>.

In this case, the isolation retaining wall <NUM> may penetrate the first passivation layer <NUM> to the first barrier layer <NUM>, and may be electrically connected to the common electrode layer <NUM>. The active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM> by using the second passivation layer <NUM>.

It should be noted that, disposing of an insulation layer between the active layer <NUM> of the second transistor <NUM> and the isolation base <NUM> is not limited in this application, provided that the following is satisfied: the active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM>, and the buffer layer <NUM> is disposed on an outer surface that is of the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>; or the active layer <NUM> of the second transistor <NUM> is insulated from the isolation base <NUM>, and a first thickness of a portion, of the buffer layer <NUM>, that is located on the isolation retaining wall <NUM> and that is close to the active layer <NUM> of the second transistor <NUM> is less than a second thickness of a portion, of the buffer layer <NUM>, that is located on the isolation retaining wall <NUM> and that is away from the active layer <NUM> of the second transistor <NUM>. The thickness is a length in a direction in which the buffer layer <NUM> grows when the buffer layer <NUM> is deposited on the substrate <NUM>. A size of the first thickness may be adjusted, so that the active layer <NUM> of the second transistor <NUM> is lower than the active layer <NUM> of the first transistor <NUM>. A specific disposing method is as described above, and details are not described herein again.

Claim 1:
A display (<NUM>), wherein the display (<NUM>) comprises a plurality of sub pixels (<NUM>), and comprises:
a substrate (<NUM>);
a light-emitting device (<NUM>), disposed on the substrate (<NUM>) and located in the sub pixel (<NUM>);
a pixel circuit (<NUM>), disposed on the substrate (<NUM>) and located in the sub pixel (<NUM>), wherein the pixel circuit (<NUM>) and the light-emitting device (<NUM>) are coupled, the pixel circuit (<NUM>) comprises a first transistor (<NUM>) and a second transistor (<NUM>), an active layer of the first transistor (<NUM>) comprises polycrystalline silicon, and an active layer of the second transistor (<NUM>) comprises semiconductor oxide; and
an isolation portion (<NUM>), disposed on the substrate (<NUM>) and located in the sub pixel (<NUM>), wherein the isolation portion (<NUM>) comprises an isolation base (<NUM>) and an isolation retaining wall (<NUM>) surrounding the isolation base (<NUM>), the active layer of the second transistor (<NUM>) is disposed in a groove (<NUM>) formed by the isolation retaining wall (<NUM>) and the isolation base (<NUM>), and the isolation portion (<NUM>) is configured at least to block hydrogen ions in the active layer of the first transistor (<NUM>) from being diffused into the active layer of the second transistor (<NUM>),
wherein the display (<NUM>) further comprises a common electrode layer (<NUM>), the common electrode layer (<NUM>) is located on a side that is of the first transistor (<NUM>) and the second transistor (<NUM>) and that is close to the substrate (<NUM>), and a first pole of the first transistor (<NUM>) or the second transistor (<NUM>) is coupled to the common electrode layer (<NUM>); and
the isolation base (<NUM>) and the common electrode layer (<NUM>) are at a same layer, made of a same material, and integrally formed.