Patent Description:
A multiplexer is a device that receives multiple input signals, selects one of the input signals, and provides that input signal as an output signal. The multiplexer selects the input signal based on a selection signal, which the multiplexer receives from a controller. For example, if the multiplexer receives a low voltage signal, or a logical <NUM>, as a selection signal, then the multiplexer selects and provides a first input signal. If the multiplexer receives a high voltage signal, or a logical <NUM>, as a selection signal, then the multiplexer selects and provides a second input signal. <CIT> refers to a high isolation electronic switch for selectively switching an output line between first and second input lines. <CIT> refers to a differential multiplexer for maximizing an amplitude of a differential output signal. <CIT> refers to an analog signal switch circuit for selecting a first or second analog output state. <CIT> refers to a synchronous data serialization circuit. <CIT> refers to a XFP transceiver that includes CDR bypass functionality.

Further embodiments are set out in the appended dependent claims.

In a non-claimed example, the disclosure includes a multiplexer comprising: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. In some embodiments, the first buffer further comprises a first logical output coupled to the output circuit; the first selection input comprises a second selection input and a third selection input, wherein the first logical input is a differential first logical input comprising a second logical input and a third logical input, and wherein the first logical output is a differential first logical output comprising a second logical output and a third logical output; the first buffer further comprises: a voltage source; a first transistor coupled to the voltage source and the second selection input; a second transistor coupled to the second selection input and the first ground; a third transistor coupled to the second selection input, the first ground, and the third logical output; and a fourth transistor coupled to the second selection input, the first ground, and the second logical output; the first transistor is a p-type metal-oxide-semiconductor (PMOS) transistor, and wherein the second transistor, the third transistor, and the fourth transistor are n-type metal-oxide-semiconductors (NMOSs); the multiplexer further comprises: a second buffer that is a mirror image of the first buffer and is coupled to the output circuit; the multiplexer further comprises: a second buffer coupled to the output circuit and comprising: a second selection input configured to receive a second selection signal; a second logical input configured to receive a second logical input signal; and a second ground; the multiplexer is further configured to: couple the second logical input to the multiplexer output when the second selection signal is the first value; couple the second logical input to the second ground when the second selection signal is the second value; the first ground and the second ground are the same; the multiplexer output is a differential multiplexer output comprising a first multiplexer output and a second multiplexer output; the output circuit further comprises: a first logical input coupled to the first buffer; a second logical input coupled to the first buffer; a third logical input; a fourth logical input; a current source; and a second ground coupled to the current source; the output circuit further comprises: a first transistor directly coupled to the first multiplexer output and the current source; a second transistor directly coupled to the second multiplexer output and the current source; a third transistor directly coupled to the first multiplexer output and the current source; and a fourth transistor directly coupled to the second multiplexer output and the current source; the first transistor, the second transistor, the third transistor, and the fourth transistor are n-type metal-oxide-semiconductor (NMOS) transistors.

In another non-claimed example, the disclosure includes an apparatus comprising: a bypass mode path configured to provide a first signal; a re-timer mode path comprising a clock and data recovery (CDR) component configured to provide a re-timed signal based on the first signal; and a multiplexer coupled to the bypass mode path and the re-timer mode path and configured to: receive a selection signal; select the first signal and couple the re-timed signal to a ground when the selection signal is a first value; and select the re-timed signal and couple the first signal to the ground when the selection signal is a second value. In some embodiments, the multiplexer comprises a first buffer configured to: pass the first signal when the selection signal is the first value; and couple the first signal to a ground when the selection signal is the second value; the multiplexer further comprises a second buffer configured to: couple the re-timed signal to the ground when selection signal is the first value; and pass the re-timed signal when the selection signal is the second value.

In yet another non-claimed example, the disclosure includes a method comprising: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value. In some embodiments, the method further comprises: passing the first logical input signal through a first buffer and an output circuit when the selection signal is the first value; and coupling the first logical input signal to the ground through the first buffer when the selection signal is the second value; the method further comprises: receiving a second logical input signal; coupling a second logical input to the ground when the selection signal is the first value; and coupling the second logical input to the multiplexer output when the selection signal is the second value; the method further comprises: coupling the second logical input signal to the ground through a second buffer when the selection signal is the first value; and passing the second logical input signal through the second buffer and the output circuit when the selection signal is the second value.

It should be understood at the outset that, although an illustrative implementation of one or more embodiments are provided below, the disclosed systems and/or methods may be implemented using any number of techniques, whether currently known or in existence.

A multiplexer, for instance a multiplexer operating at a bit rate at or above <NUM> gigabits per second (Gb/s), may experience performance degradation. Specifically, even though the multiplexer has an unselected input signal and a selected input signal, the unselected input signal may interference with the selected input signal and cause the multiplexer to experience jitter at its output. Jitter is defined as a deviation from periodicity, typically in relation to a reference clock. It is therefore desirable to reduce or eliminate, and therefore immunize multiplexers from, such interference.

Disclosed herein are embodiments for interference-immunized multiplexers. The disclosed multiplexers comprise a first buffer circuit, a second buffer circuit, and an output circuit coupled to the first buffer circuit and the second buffer circuit. The first buffer circuit and the second buffer circuit replace single transistors that exist in other multiplexers. Those single transistors receive selection signals and are coupled in series to corresponding differential inputs and a corresponding output. Instead, the first buffer circuit and the second buffer circuit either provide differential output signals when they are selected by a selection signal or do not provide the differential output signals when they are not selected by the selection signal. In the latter case, outputs of the first buffer circuit and the second buffer circuit are tied to ground. As a result, the disclosed multiplexers are substantially or completely immunized from unselected input signal interference. In addition, such immunization enables the disclosed multiplexers to operate at relatively lower supply voltages.

<FIG> is an abstracted schematic diagram of a multiplexer <NUM> according to an embodiment of the disclosure. The multiplexer <NUM> comprises a first buffer <NUM>, a second buffer <NUM>, and an output circuit <NUM> coupled to the first buffer <NUM> and the second buffer <NUM>. The first buffer <NUM> comprises logical inputs VINPO and VINMO, and the second buffer <NUM> comprises logical inputs VINP1 and VINM1. The multiplexer <NUM> and its components are described more fully below.

<FIG> is a schematic diagram of a buffer <NUM> according to an embodiment of the disclosure. The buffer <NUM> may implement the first buffer <NUM>. The buffer <NUM> comprises a source voltage <NUM>; transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> (<NUM>-<NUM>); a current source <NUM>; inductors <NUM>, <NUM>; resistors <NUM>, <NUM>; and a ground <NUM>, all connected as shown in <FIG>. In addition, the buffer <NUM> comprises two selection inputs SELP; logical inputs VINPO, VINMO; and logical outputs VINP0', VINMO'.

The source voltage <NUM> provides any suitable voltage. For instance, the source voltage <NUM> provides a voltage of about <NUM> volts (V) or less. The buffer <NUM> may not have its own power source on its chip. In that case, the source voltage <NUM> is a connection to an actual source voltage. The current source <NUM> provides any suitable constant current. For instance, the current source <NUM> provides a current of about <NUM> milliamps (mA) or less.

The inductors <NUM>, <NUM> compensate for or reduce parasitic capacitance in the buffer <NUM>, thereby extending an operational bandwidth of the buffer <NUM>. The inductors <NUM>, <NUM> provide any suitable inductance values. For instance, the inductors <NUM>, <NUM> provide inductance values between about <NUM> picohenries (pH) and about <NUM> pH.

The resistors <NUM>, <NUM> provide a load for the buffer <NUM>. The resistors <NUM>, <NUM> provide any suitable resistance values. For instance, the resistors <NUM>, <NUM> provide resistive values between about <NUM> ohms (Ω) and about <NUM>Ω. The transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> comprise both a p-type enhancement mode transistor <NUM> and n-type enhancement mode transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> (<NUM>-<NUM>).

<FIG> is a schematic diagram of the p-type enhancement mode transistor <NUM> in <FIG>. The transistor <NUM> is a p-type metal-oxide-semiconductor field-effect transistor (MOSFET), or PMOS. The transistor <NUM> comprises a gate <NUM>, a source <NUM>, and a drain <NUM>. When the gate <NUM> receives a logical <NUM>, the transistor <NUM> is "turned on," meaning that the source <NUM> and the drain <NUM> electrically couple to each other to allow a current to flow between them. When the gate <NUM> receives a logical <NUM>, the transistor <NUM> is "turned off," meaning that the source <NUM> and the drain <NUM> do not electrically couple to each other to allow a current to flow between them. Thus, the transistor <NUM> acts as an open circuit between the source <NUM> and the drain <NUM>.

<FIG> is a schematic diagram of the n-type enhancement mode transistors <NUM>-<NUM> in <FIG>. The transistors <NUM>-<NUM> are n-type MOSFETs, or NMOSs. The transistors <NUM>-<NUM> comprise a gate <NUM>, a drain <NUM>, and a source <NUM>. When the gate <NUM> receives a logical <NUM>, the transistors <NUM>-<NUM> are turned off, meaning that the drain <NUM> and the source <NUM> do not electrically couple to each other to allow a current to flow between them. Thus, the transistors <NUM>-<NUM> act as an open circuit between the drain <NUM> and the source <NUM>. When the gate <NUM> receives a logical <NUM>, the transistors <NUM>-<NUM> are turned on, meaning that the drain <NUM> and the source <NUM> electrically couple to each other to allow a current to flow between them.

Returning to <FIG>, in operation when the selection inputs SELP receive a selection signal that is a logical <NUM>, the transistor <NUM> is turned on and couples the source voltage <NUM> to the transistors <NUM>, <NUM>. In addition, the transistors <NUM>, <NUM>, <NUM> (<NUM>-<NUM>) are turned off and uncouple from the ground <NUM>. As an example, the buffer <NUM> receives a differential logical input signal, specifically a logical high input signal at the logical input VINPO and a logical low input signal at the logical input VINMO. In that case, the transistor <NUM> is turned on, so the logical output VINMO', which is connected to the drain of the transistor <NUM>, receives a voltage that is about equivalent to the voltage from the source voltage <NUM> minus a voltage drop across the resistor <NUM>. The total voltage approximates a logical low signal. Thus, the logical output VINMO' provides a logical low output signal. At the same time, the transistor <NUM> is turned off, so the logical output VINP0', which is connected to the drain of the transistor <NUM>, receives a voltage of about the source voltage <NUM>. That voltage approximates a logical high signal. Thus, the logical output VINP0' provides a logical high output signal. Together, the logical low output signal at VINMO' and the logical high output signal at VINP0' form a differential logical output signal.

When the selection inputs SELP receive a selection signal that is a logical <NUM>, the transistor <NUM> is turned off and uncouples the source voltage <NUM> from the transistors <NUM>, <NUM>, the drains of which are connected to the logical outputs VINMO', VINP0', respectively. At the same time, the transistors <NUM>-<NUM> are turned on and couple the logical outputs VINP0', VINMO' to the ground <NUM>. Thus, the logical outputs VINP0', VINMO' provide logical low output signals. As can be seen, based on the selection inputs SELP, the buffer <NUM> either provides a differential logical output signal or provides no signal at all.

Table <NUM> is a simplified logic table for the buffer <NUM>.

Table <NUM> is simplified in that logical values are not listed in every cell. For instance, when the selection signal at the selection inputs SELP is <NUM>, the logical output VINP0' provides whatever logical input signal the logical input VINMO receives, and the logical output VINMO' provides whatever logical input signal the logical input VINPO receives. When the selection signal at the selection inputs SELP is <NUM>, the logical outputs VINP0', VINMO' provide logical low output signals.

As mentioned above, the buffer <NUM> may implement the first buffer <NUM>. In addition, a mirror image of the buffer <NUM> may implement the second buffer <NUM>. However, the mirror image comprises two selection inputs SELM; logical inputs VINP1, VINM1; and logical outputs VINP1 ', VINM1'. Thus, if the selection inputs SELP drive the first buffer <NUM>, then the selection inputs SELM drive the second buffer <NUM>. Likewise, if the selection inputs SELM drive the first buffer <NUM>, then the selection inputs SELP drive the second buffer <NUM>.

<FIG> is a detailed schematic diagram of the output circuit <NUM> in <FIG>. The output circuit <NUM> comprises a source voltage <NUM> similar to the source voltage <NUM>; inductors <NUM>, <NUM> similar to the inductors <NUM>, <NUM>; resistors <NUM>, <NUM> similar to the resistors <NUM>, <NUM>; transistors <NUM>, <NUM>, <NUM>, <NUM> (<NUM>-<NUM>) similar to the transistors <NUM>-<NUM>; a current source <NUM> similar to the current source <NUM>; and a ground <NUM> similar to the ground <NUM>. In addition, the output circuit <NUM> comprises logical inputs VINPO", VINMO", VINP1", VINM1" and multiplexer outputs VOUTP, VOUTM. The logical inputs VINPO", VINMO", VINP1", VINM1" correspond to the logical outputs VINP0', VINMO', VINP1', VINM1', respectively, from the first buffer <NUM> and the second buffer <NUM>.

The transistors <NUM>-<NUM> are directly coupled to the current source. The transistors <NUM>, <NUM> are directly coupled to each other; the logical inputs VINPO", VINMO", respectively; and the multiplexer outputs VOUTM, VOUTP, respectively. The transistors <NUM>, <NUM> are directly coupled to each other; the logical inputs VINP1", VINM1", respectively; and the multiplexer outputs VOUTM, VOUTP, respectively.

In operation, in a first example, the output circuit <NUM> receives no differential logical output signal from the second buffer <NUM>, but does receive a differential logical output signal from the first buffer <NUM>. Specifically, the output circuit <NUM> receives a logical low input signal at the logical input VINP0" and a logical high input signal at the logical input VINMO". In that case, the transistor <NUM> is turned off, so the multiplexer output VOUTM, which is connected to the drain of the transistor <NUM>, receives a voltage of about the source voltage <NUM>. That voltage approximates a logical high signal. Thus, the multiplexer output VOUTM provides a logical high output signal. At the same time, the transistor <NUM> is turned on, so the multiplexer output VOUTP, which is connected to the drain of the transistor <NUM>, receives a voltage that is equivalent to the voltage from the source voltage <NUM> minus a voltage drop across the resistor <NUM>. The total voltage approximates a logical low signal. Thus, the multiplexer output VOUTP provides a logical low output signal.

In a second example, the output circuit <NUM> receives no differential logical output signal from the first buffer <NUM>, but does receive a differential logical output signal from the second buffer <NUM>. Specifically, the output circuit <NUM> receives a logical low input signal at the logical input VINM1" and a logical high input signal at the logical input VINP1". In that case, the transistor <NUM> is turned off, so the multiplexer output VOUTP, which is connected to the drain of the transistor <NUM>, receives a voltage of about the source voltage <NUM>. That voltage approximates a logical high signal. Thus, the multiplexer output VOUTP provides a logical high output signal. At the same time, the transistor <NUM> is turned on, so the multiplexer output VOUTM, which is connected to the drain of the transistor <NUM>, receives a voltage that is equivalent to the voltage from the source voltage <NUM> minus a voltage drop across the resistor <NUM>. The total voltage approximates a logical low signal. Thus, the multiplexer output VOUTM provides a logical low output signal.

Table <NUM> is a simplified logic table for the output circuit <NUM>.

Table <NUM> is simplified in that logical values are not listed in every cell. For instance, when the logical inputs VINP0", VINM0" receive a differential logical output signal from the first buffer <NUM> and the logical inputs VINP <NUM>", VINM1" do not receive a differential logical output signal from the second buffer <NUM>, the multiplexer output VOUTP provides whatever logical input signal the logical input VINPO receives and the multiplexer output VOUTM provides whatever logical input signal the logical input VINM0 receives. When the logical inputs VINP1", VINM1" receive a differential logical output signal from the second buffer <NUM> and the logical inputs VINP0", VINM0" do not receive a differential logical output signal from the first buffer <NUM>, the multiplexer output VOUTP provides whatever logical input signal the logical input VINP1 receives and the multiplexer output VOUTM provides whatever logical input signal the logical input VINM1 receives.

As can be seen, at any given time, the output circuit <NUM> receives a differential logical output signal either from the first buffer <NUM> or the second buffer <NUM>. However, the output circuit <NUM> does not receive a first differential logical output signal from the first buffer <NUM> and a second differential logical output signal from the second buffer <NUM> at the same time. As a result, the output circuit <NUM> is immunized from the first differential logical output signal interfering with the second differential logical output signal. In addition, such immunization enables the source voltages <NUM>, <NUM> in the multiplexer <NUM> to operate at relatively lower voltages.

<FIG> is a detailed schematic diagram of the multiplexer <NUM> in <FIG>. Like <FIG>, <FIG> shows the first buffer <NUM>, the second buffer <NUM>, and the output circuit <NUM>. The buffers <NUM> and <NUM> are similar to or the same as the buffer <NUM> of <FIG>, and the circuit <NUM> is the same as the output circuit <NUM> of <FIG>. Accordingly, the operation described therefore applies here in <FIG>. In addition, unlike <FIG>, <FIG> also shows each component of the first buffer <NUM>, the second buffer <NUM>, and the output circuit <NUM>. For instance, <FIG> shows that the logical output VINP0' of the first buffer <NUM> couples to the logical input VINP0" of the output circuit <NUM>, the logical output VINM0' of the first buffer <NUM> couples to the logical input VINMO" of the output circuit <NUM>, the logical output VINP1' of the second buffer <NUM> couples to the logical input VINP1" of the output circuit <NUM>, and the logical output VINM1' of the second buffer <NUM> couples to the logical input VINM1 " of the output circuit <NUM>.

Table <NUM> is a simplified logic table for the multiplexer <NUM>. Table <NUM> combines the logic of both Table <NUM> and Table <NUM>.

Table <NUM> is simplified in that logical values are not listed in every cell. For instance, when the selection signal at the selection inputs SELP is <NUM> and the selection signal at the selection inputs SELM is <NUM>, the multiplexer output VOUTP provides whatever logical input signal the logical input VINP0 receives and the multiplexer output VOUTM provides whatever logical input signal the logical input VINM0 receives. When the selection signal at the selection inputs SELP is <NUM> and the selection signal at the selection inputs SELM is <NUM>, the multiplexer output VOUTP provides whatever logical input signal the logical input VINP1 receives and the multiplexer output VOUTM provides whatever logical input signal the logical input VINM1 receives.

In a first embodiment, the multiplexer <NUM> receives a logical high input signal from another component, then the multiplexer <NUM> uses inverter logic to provide a logical low input signal in order to form a differential input signal, meaning a signal having two voltage levels with respect to ground. The multiplexer <NUM> may do so for both logical input signals and selection signals. In a second embodiment, the multiplexer <NUM> receives differential logical input signals and differential selection signals form another component. In a third embodiment, the multiplexer <NUM> receives and provides single-ended signals, meaning signals having one voltage level with respect to ground.

<FIG> is a schematic diagram of an optical transceiver <NUM> according to an embodiment of the disclosure. The transceiver <NUM> comprises an optical-to-electrical (O-E) converter <NUM>, an amplifier <NUM>, a bypass mode path <NUM>, a re-timer mode path <NUM>, a clock and data recovery (CDR) component <NUM>, the multiplexer <NUM>, and an electrical-to-optical (E-O) converter <NUM>. The components of the transceiver <NUM> may be arranged as shown or in any other suitable manner.

The O-E converter <NUM> receives an optical input signal and converts the optical input signal to an electrical input signal. The amplifier <NUM> receives and amplifies the electrical input signal to produce an amplified signal. The amplified signal then follows both the bypass mode path <NUM> to the multiplexer <NUM> and the re-timer mode path <NUM> to the CDR component <NUM>.

The CDR component <NUM> receives the amplified signal and recovers data from the amplified signal. For instance, if the amplified signal comprises clock data, then the CDR component <NUM> recovers the clock data from the amplified signal with or without a local clock signal. The CDR component <NUM> then re-times the amplified signal with the recovered clock data to produce and re-timed signal to the multiplexer <NUM>.

The multiplexer <NUM> is referred to as a two-to-one (<NUM>:<NUM>) multiplexer because it receives two input signals, namely the amplified signal and the re-timed signal, and it provides one output signal, namely the electrical output signal. The multiplexer <NUM> functions as described above. Specifically, when the selection input SELP receives a selection signal that is a <NUM> and the selection input SELM receives a selection signal that is a <NUM>, the multiplexer <NUM> provides the amplified signal to the E-O converter <NUM> and couples the re-timed signal to ground. In other words, only the bypass mode path <NUM> provides a signal to the E-O converter <NUM> through the multiplexer <NUM>. When the selection input SELP receives a selection signal that is a <NUM> and the selection input SELM receives a selection signal that is a <NUM>, the multiplexer <NUM> provides the re-timed signal and couples the amplified signal to ground. In other words, only the re-timer mode path <NUM> provides a signal to the E-O converter <NUM> through the multiplexer <NUM>. Finally, the E-O converter <NUM> converts, depending on what the multiplexer <NUM> provides, either the amplified signal or the re-timed signal to an optical output signal.

The multiplexer <NUM> may switch back and forth between the bypass mode path <NUM> and the re-timer mode path <NUM> at a high data rate. Typically, this would introduce jitter. However, the multiplexer <NUM> either provides a signal from the bypass mode path <NUM> while coupling the re-timer mode path <NUM> to ground or provides a signal from the re-timer mode path <NUM> while coupling the bypass mode path <NUM> to ground. Thus, the multiplexer <NUM> eliminates or substantially eliminates such jitter.

<FIG> shows the multiplexer <NUM> in the context of a function that selects either an amplified signal or a re-timed signal. However, the multiplexer <NUM> may perform a function that selects between more than two input signals. If there are more than two input signals, then the multiplexer may provide a corresponding number of buffers <NUM>. For instance, to implement a <NUM>:<NUM> multiplexer, the multiplexer <NUM> may provide four of the buffers <NUM>. In addition, <FIG> shows the multiplexer <NUM> in the context of optical signals. However, the multiplexer <NUM> may be a part of purely electrical components or systems.

<FIG> is a flowchart illustrating a method <NUM> of signal selection according to an embodiment of the disclosure. The multiplexer <NUM> may implement the method <NUM>. At step <NUM>, a selection signal and a logical input signal are received. For instance, the selection inputs SELP receive a selection signal and the logical inputs VINPO, VINMO receive a logical input signal. At step <NUM>, the logical inputs are coupled to multiplexer outputs when the selection signal is a first value. For instance, the logical inputs VINP0, VINM0 are coupled to the multiplexer outputs VOUTP, VOUTM when the selection signal is <NUM>. At step <NUM>, the logical inputs are coupled to a ground when the selection signal is a second value. For instance, the logical inputs VINP0, VINM0 are coupled to the ground <NUM> when the selection signal is <NUM>.

The multiplexer <NUM> may implement the method <NUM> in the transceiver <NUM> as described above. In that case, the multiplexer <NUM> may switch back and forth between the bypass mode path <NUM> and the re-timer mode path <NUM> at a high data rate. Furthermore, the multiplexer <NUM> may eliminate or substantially eliminate jitter while doing so as also described above.

<FIG> is a schematic diagram of a device <NUM> according to an embodiment of the disclosure. The device <NUM> is suitable for implementing the disclosed embodiments as described below. The device <NUM> comprises ingress ports <NUM> and receiver units (Rx) <NUM> for receiving data; a processor, logic unit, or central processing unit (CPU) <NUM> to process the data; transmitter units (Tx) <NUM> and egress ports <NUM> for transmitting the data; and a memory <NUM> for storing the data. The device <NUM> may also comprise O-E components and E-O components coupled to the ingress ports <NUM>, the receiver units <NUM>, the transmitter units <NUM>, and the egress ports <NUM> for egress or ingress of optical or electrical signals.

The processor <NUM> is implemented by hardware and software. The processor <NUM> may be implemented as one or more CPU chips, cores (e.g., as a multi-core processor), field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and digital signal processors (DSPs). The processor <NUM> is in communication with the ingress ports <NUM>, receiver units <NUM>, transmitter units <NUM>, egress ports <NUM>, and memory <NUM>. The processor <NUM> is coupled to a multiplexer <NUM>. The multiplexer <NUM> implements the disclosed embodiments described above. For instance, the multiplexer <NUM> implements the multiplexer <NUM> and receiving selection signals from the processor <NUM>. The inclusion of the multiplexer <NUM> therefore provides a substantial improvement to the functionality of the device <NUM> and effects a transformation of the device <NUM> to a different state.

The memory <NUM> comprises one or more disks, tape drives, and solid-state drives and may be used as an over-flow data storage device, to store programs when such programs are selected for execution, and to store instructions and data that are read during program execution. The memory <NUM> may be volatile and non-volatile and may be read-only memory (ROM), random-access memory (RAM), ternary content-addressable memory (TCAM), and static random-access memory (SRAM).

One embodiment of the invention comprises an apparatus that includes bypass means to for creating a bypass mode path configured to provide a first signal. The apparatus further includes re-timer means for creating a a re-timer mode path comprising a clock and data recovery (CDR) component means configured to provide a re-timed signal based on the first signal. Finally the apparatus includes a multiplexer means coupled to the bypass mode path and the re-timer mode path and configured to:.

A first component is directly coupled to a second component when there are no intervening components, except for a line, a trace, or other media, between the first component and the second component. The first component is indirectly coupled to the second component when there are intervening components between the first component and the second component. The termed "coupled" and its derivatives includes both directly coupled and indirectly coupled. The use of the term "about" means a range including ±<NUM>% of the subsequent number, unless otherwise stated. While several embodiments have been provided in the present disclosure, it may be understood that the disclosed systems and methods might be embodied in many other specific forms without departing from the scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented.

Claim 1:
A multiplexer (<NUM>) comprising:
an output circuit (<NUM>) comprising multiplexer outputs (VOUTM, VOUTP) configured as a differential output;
a first buffer (<NUM>, <NUM>) coupled to the output circuit (<NUM>) and comprising:
a first selection input (SELP) configured to receive a first logical selection signal; two first logical inputs (VINP0, VINM0) configured as a differential input and to receive a first logical input signal; and
a first ground,
wherein the first buffer (<NUM>) comprises two first logical outputs (VINP0', VINMO') configured as a differential output and coupled to the output circuit (<NUM>),
a second buffer (<NUM>) that is a mirror image of the first buffer and is coupled to the output circuit (<NUM>), and comprises:
a second selection input (SELM) configured to receive a second logical selection signal;
two second logical inputs (VINP1, VINM1) configured as a differential input and to receive a second logical input signal;
two second logical outputs (VINP1', VINM1') configured as a differential output and coupled to the output circuit (<NUM>); and
a second ground,
wherein the multiplexer (<NUM>) is configured to:
couple the first logical inputs (VINP0, VINM0) to the multiplexer outputs (VOUTM, VOUTP) when the first logical selection signal is a first value,
couple the first logical inputs (VINP0, VINM0) to the first ground when the first logical selection signal is a second value,
couple the second logical inputs (VINP1, VINM1) to the multiplexer outputs (VOUTM, VOUTP) when the second logical selection signal is a first value; and
couple the second logical inputs (VINP1, VINM1) to the second ground when the second logical selection signal is a second value.