Patent Description:
The operational rate of memory devices, including the data rate of a memory device, has been increasing over time. As a side effect of the increase in speed of a memory device, data errors due to distortion may increase. For example, inter-symbol interference between transmitted data whereby previously received data influences the currently received data may occur (e.g., previously received data affects and interferes with subsequently received data). One manner to correct for this interference is through the use of a decision feedback equalizer (DFE) circuit, which may be programmed to offset (i.e., undo, mitigate, or offset) the effect of the channel on the transmitted data.

Additionally, correcting distortions in the transmitted signals continues to be important. However, conventional distortion correction techniques may not adequately correct the distortions of the signal. A DFE circuit may require the generation of certain input bias levels, yet conventional generation of these bias levels may be impacted by changes across processes, voltages and temperatures (PVT) and may not generate input bias levels with a high level of precision across a wide range of PVT conditions. Errors that result from bias levels generated with a lack of tolerance for PVT conditions can cause additional distortions to the final data, thus reducing the reliability of data transmitted within the memory devices.

Document <CIT> discloses a signaling system and includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path.

Various aspects of this disclosure may better be understood upon reading the following detailed description and upon reference to the drawings in which:.

Using a decision feedback equalizer (DFE) of a memory device to perform distortion correction techniques may be valuable, for example, to correctly compensate for distortions in the received data of the memory device. This insures that accurate values are being stored in the memory of the memory device. The DFE may use previous bit data to create corrective values to compensate for distortion resulted from the previous bit data. For example, the most recent previous bit may have more of a distortion effect on the current bit than a bit transmitted several data points before, causing the corrective values to be different between the two bits. With these levels to correct for, the DFE may operate to correct the distortion of the transmitted bit.

In some embodiments, the DFE may require the use of bias levels in order to precisely generate the distortion correction factors to sufficiently equalize a channel. As the bias levels may work to directly or indirectly remove distortion from data, increasing the reliability of the bias levels may increase the reliability that the distortion was removed from the data after it was processed by the DFE. Thus, increased precision in bias level generation may increase precision in channel equalization.

As such, a system and/or method to generate bias levels with a high level of precision may be desirable. Further, impacts to the system due to changes in processes, voltages, and temperatures (PVT) that may occur at different operating conditions may be reduced so that the system and/or method may generate bias levels with a high level of precision under various operating conditions. Thus, circuitry to emulate a receiver coupled to a feedback loop may be utilized to generate suitable bias levels based on a desired correction factor level. After supplying a reference signal and the reference signal with the desired correction factor level included therein to the receiver, the outputs of the receiver from each signal may be compared. The result of the comparison may route back to the receiver as a feedback signal and may be utilized to adjust the outputs until they are approximately equal. The feedback signal used to generate the approximately equal outputs may then be applied as a bias level suitable to generate the desired correction factor in a DFE. Thus, the circuitry may operate to determine the feedback signal (e.g., a bias level) that may suitably adjust the reference signal to match the reference signal with the added correction factor, which in turn, may result in a desired correction in the DFE.

Turning now to the figures, <FIG> is a simplified block diagram illustrating certain features of a memory device <NUM>. Specifically, the block diagram of <FIG> is a functional block diagram illustrating certain functionality of the memory device <NUM>. In accordance with one embodiment, the memory device <NUM> may be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of DDR5 SDRAM allow for reduced power consumption, more bandwidth and more storage capacity compared to prior generations of DDR SDRAM.

The memory device <NUM>, may include a number of memory banks <NUM>. The memory banks <NUM> may be DDR5 SDRAM memory banks, for instance. The memory banks <NUM> may be provided on one or more chips (e.g., SDRAM chips) that are arranged on dual inline memory modules (DIMMS). Each DIMM may include a number of SDRAM memory chips (e.g., x8 or x16 memory chips), as will be appreciated. Each SDRAM memory chip may include one or more memory banks <NUM>. The memory device <NUM> represents a portion of a single memory chip (e.g., SDRAM chip) having a number of memory banks <NUM>. For DDR5, the memory banks <NUM> may be further arranged to form bank groups. For instance, for an <NUM> gigabit (Gb) DDR5 SDRAM, the memory chip may include <NUM> memory banks <NUM>, arranged into <NUM> bank groups, each bank group including <NUM> memory banks. For a <NUM> GB DDR5 SDRAM, the memory chip may include <NUM> memory banks <NUM>, arranged into <NUM> bank groups, each bank group including <NUM> memory banks, for instance. Various other configurations, organization and sizes of the memory banks <NUM> on the memory device <NUM> may be utilized depending on the application and design of the overall system.

The memory device <NUM> may include a command interface <NUM> and an input/output (I/O) interface <NUM> configured to exchange (e.g., receive and transmit) signals with external devices. The command interface <NUM> is configured to provide a number of signals (e.g., signals <NUM>) from an external device (not shown), such as a processor or controller. The processor or controller may provide various signals <NUM> to the memory device <NUM> to facilitate the transmission and receipt of data to be written to or read from the memory device <NUM>.

As will be appreciated, the command interface <NUM> may include a number of circuits, such as a clock input circuit <NUM> and a command address input circuit <NUM>, for instance, to ensure proper handling of the signals <NUM>. The command interface <NUM> may receive one or more clock signals from an external device. Generally, double data rate (DDR) memory utilizes a differential pair of system clock signals, referred to herein as the true clock signal (Clk_t/) and the complementary clock signal (Clk_c). The positive clock edge for DDR refers to the point where the rising true clock signal Clk_t/ crosses the falling complementary clock signal Clk_c, while the negative clock edge indicates that transition of the falling true clock signal Clk_t and the rising of the complementary clock signal Clk_c. Commands (e.g., read command, write command, etc.) are typically entered on the positive edges of the clock signal and data is transmitted or received on both the positive and negative clock edges.

The clock input circuit <NUM> receives the true clock signal (Clk_t/) and the complementary clock signal (Clk_c) and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator <NUM>, such as a delay locked loop (DLL) circuit. The internal clock generator <NUM> generates a phase controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase controlled internal clock signal LCLK is supplied to the I/O interface <NUM>, for instance, and is used as a timing signal for determining an output timing of read data.

The internal clock signal CLK may also be provided to various other components within the memory device <NUM> and may be used to generate various additional internal clock signals. For instance, the internal clock signal CLK may be provided to a command decoder <NUM>. The command decoder <NUM> may receive command signals from the command bus <NUM> and may decode the command signals to provide various internal commands. For instance, the command decoder <NUM> may provide command signals to the internal clock generator <NUM> over the bus <NUM> to coordinate generation of the phase controlled internal clock signal LCLK. The phase controlled internal clock signal LCLK may be used to clock data through the I/O interface <NUM>, for instance.

Further, the command decoder <NUM> may decode commands, such as read commands, write commands, mode-register set commands, activate commands, etc., and provide access to a particular memory bank <NUM> corresponding to the command, via the bus path <NUM>. As will be appreciated, the memory device <NUM> may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory banks <NUM>. In one embodiment, each memory bank <NUM> includes a bank control block <NUM> which provides the necessary decoding (e.g., row decoder and column decoder), as well as other features, such as timing control and data control, to facilitate the execution of commands to and from the memory banks <NUM>. Collectively, the memory banks <NUM> and the bank control blocks <NUM> may be referred to as a memory array <NUM>.

The memory device <NUM> executes operations, such as read commands and write commands, based on the command/address signals received from an external device, such as a processor. In one embodiment, the command/address bus may be a <NUM>-bit bus to accommodate the command/address signals (CA<<NUM>:<NUM>>). The command/address signals are clocked to the command interface <NUM> using the clock signals (Clk_t/ and Clk_c). The command interface may include a command address input circuit <NUM> which is configured to receive and transmit the commands to provide access to the memory banks <NUM>, through the command decoder <NUM>, for instance. In addition, the command interface <NUM> may receive a chip select signal (CS_n). The CS_n signal enables the memory device <NUM> to process commands on the incoming CA<<NUM>:<NUM>> bus. Access to specific banks <NUM> within the memory device <NUM> is encoded on the CA<<NUM>:<NUM>> bus with the commands.

In addition, the command interface <NUM> may be configured to receive a number of other command signals. For instance, a command/address on die termination (CA_ODT) signal may be provided to facilitate proper impedance matching within the memory device <NUM>. A reset command (RESET_n) may be used to reset the command interface <NUM>, status registers, state machines and the like, during power-up for instance. The command interface <NUM> may also receive a command/address invert (CAI) signal which may be provided to invert the state of command/address signals CA<<NUM>:<NUM>> on the command/address bus, for instance, depending on the command/address routing for the particular memory device <NUM>. A mirror (MIR) signal may also be provided to facilitate a mirror function. The MIR signal may be used to multiplex signals so that they can be swapped for enabling certain routing of signals to the memory device <NUM>, based on the configuration of multiple memory devices in a particular application. Various signals to facilitate testing of the memory device <NUM>, such as the test enable (TEN) signal, may be provided, as well. For instance, the TEN signal may be used to place the memory device <NUM> into a test mode for connectivity testing.

The command interface <NUM> may also be used to provide an alert signal (ALERT_n) to the system processor or controller for certain errors that may be detected. For instance, an alert signal (ALERT_n) may be transmitted from the memory device <NUM> if a cyclic redundancy check (CRC) error is detected. Other alert signals may also be generated. Further, the bus and pin for transmitting the alert signal (ALERT_n) from the memory device <NUM> may be used as an input pin during certain operations, such as the connectivity test mode executed using the TEN signal, as described above.

Data may be sent to and from the memory device <NUM>, utilizing the command and clocking signals discussed above, by transmitting and receiving data signals <NUM> through the I/O interface <NUM>. More specifically, the data may be sent to or retrieved from the memory banks <NUM> over the data bus <NUM>, which includes a plurality of bi-directional data buses. Data I/O signals, generally referred to as DQ signals, are generally transmitted and received in one or more bi-directional data busses. For certain memory devices, such as a DDR5 SDRAM memory device, the I/O signals may be divided into upper and lower bytes. For instance, for an x16 memory device, the I/O signals may be divided into upper and lower I/O signals (e.g., DQ<<NUM>:<NUM>> and DQ<<NUM>:<NUM>>) corresponding to upper and lower bytes of the data signals, for instance.

To allow for higher data rates within the memory device <NUM>, certain memory devices, such as DDR memory devices may utilize data strobe signals, generally referred to as DQS signals. The DQS signals are driven by the external processor or controller sending the data (e.g., for a write command) or by the memory device <NUM> (e.g., for a read command). For read commands, the DQS signals are effectively additional data output (DQ) signals with a predetermined pattern. For write commands, the DQS signals are used as clock signals to capture the corresponding input data. As with the clock signals (Clk_t/ and Clk_c), the data strobe (DQS) signals may be provided as a differential pair of data strobe signals (DQS_t/ and DQS_c) to provide differential pair signaling during reads and writes. For certain memory devices, such as a DDR5 SDRAM memory device, the differential pairs of DQS signals may be divided into upper and lower data strobe signals (e.g., UDQS_t/ and UDQS_c; LDQS_t/ and LDQS_c) corresponding to upper and lower bytes of data sent to and from the memory device <NUM>, for instance.

An impedance (ZQ) calibration signal may also be provided to the memory device <NUM> through the I/O interface <NUM>. The ZQ calibration signal may be provided to a reference pin and used to tune output drivers and ODT values by adjusting pull-up and pulldown resistors of the memory device <NUM> across changes in process, voltage and temperature (PVT) values. Because PVT characteristics may impact the ZQ resistor values, the ZQ calibration signal may be provided to the ZQ reference pin to be used to adjust the resistance to calibrate the input impedance to known values. As will be appreciated, a precision resistor is generally coupled between the ZQ pin on the memory device <NUM> and GND/VSS external to the memory device <NUM>. This resistor acts as a reference for adjusting internal ODT and drive strength of the IO pins.

In addition, a loopback signal (LOOPBACK) may be provided to the memory device <NUM> through the I/O interface <NUM>. The loopback signal may be used during a test or debugging phase to set the memory device <NUM> into a mode wherein signals are looped back through the memory device <NUM> through the same pin. For instance, the loopback signal may be used to set the memory device <NUM> to test the data output of the memory device <NUM>. Loopback may include both a data and a strobe or possibly just a data pin. This is generally intended to be used to monitor the data captured by the memory device <NUM> at the I/O interface <NUM>.

As will be appreciated, various other components such as power supply circuits (for receiving external VDD and VSS signals), mode registers (to define various modes of programmable operations and configurations), read/write amplifiers (to amplify signals during read/write operations), temperature sensors (for sensing temperatures of the memory device <NUM>), etc., may also be incorporated into the memory system <NUM>. Accordingly, it should be understood that the block diagram of <FIG> is only provided to highlight certain functional features of the memory device <NUM> to aid in the subsequent detailed description.

In some embodiments, the memory device <NUM> may be disposed in (physically integrated into or otherwise connected to) a host device or otherwise coupled to a host device. The host device may include any one of a desktop computer, laptop computer, pager, cellular phone, personal organizer, portable audio player, control circuit, camera, etc. The host device may also be a network node, such as a router, a server, or a client (e.g., one of the previously-described types of computers). The host device may be some other sort of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. (The terms used to describe these various examples of systems, like many of the other terms used herein, may share some referents and, as such, should not be construed narrowly in virtue of the other items listed.

The host device may, thus, be a processor-based device, which may include a processor, such as a microprocessor, that controls the processing of system functions and requests in the host. Further, any host processor may comprise a plurality of processors that share system control. The host processor may be coupled directly or indirectly to additional system elements of the host, such that the host processor controls the operation of the host by executing instructions that may be stored within the host or external to the host.

As discussed above, data may be written to and read from the memory device <NUM>, for example, by the host whereby the memory device <NUM> operates as volatile memory, such as Double Data Rate DRAM (e.g., DDR5 SDRAM). The host may, in some embodiments, also include separate non-volatile memory, such as read-only memory (ROM), PC-RAM, silicon-oxide-nitride-oxide-silicon (SONOS) memory, metal-oxide-nitride-oxidesilicon (MONOS) memory, polysilicon floating gate based memory, and/or other types of flash memory of various architectures (e.g., NAND memory, NOR memory, etc.) as well as other types of memory devices (e.g., storage), such as solid state drives (SSD's), MultimediaMediaCards (MMC's), SecureDigital (SD) cards, CompactFlash (CF) cards, or any other suitable device. Further, it should be appreciated that the host may include one or more external interfaces, such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Small Computer System Interface (SCSI), IEEE <NUM> (Firewire), or any other suitable interface as well as one or more input devices to allow a user to input data into the host, for example, buttons, switching elements, a keyboard, a light pen, a stylus, a mouse, and/or a voice recognition system, for instance. The host may optionally also include an output device, such as a display coupled to the processor and a network interface device, such as a Network Interface Card (NIC), for interfacing with a network, such as the Internet. As will be appreciated, the host may include many other components, depending on the application of the host.

The host may operate to transfer data to the memory device <NUM> for storage and may read data from the memory device <NUM> to perform various operations at the host. Accordingly, to facilitate these data transmissions, in some embodiments, the I/O interface <NUM> may include a data transceiver <NUM> that operates to receive and transmit DQ signals to and from the I/O interface <NUM>.

<FIG> illustrates the I/O interface <NUM> of the memory device <NUM> generally and, more specifically, the data transceiver <NUM>. As illustrated, the data transceiver <NUM> of the I/O interface <NUM> may include a DQ connector <NUM>, a DQ transceiver <NUM>, and a serializer/deserializer <NUM>. It should be noted that in some embodiments, multiple data transceivers <NUM> may be utilized that each single data transceiver <NUM> may be utilized in connection with a respective one of each of upper and lower I/O signals (e.g., DQ<<NUM>:<NUM>> and DQ<<NUM>:<NUM>>) corresponding to upper and lower bytes of the data signals, for instance. Thus, the I/O interface <NUM> may include a plurality of data transceivers <NUM>, each corresponding to one or more I/O signals (e.g., inclusive of a respective DQ connector <NUM>, DQ transceiver <NUM>, and serializer/deserializer <NUM>).

The DQ connector <NUM> may be, for example a pin, pad, combination thereof, or another type of interface that operates to receive DQ signals, for example, for transmission of data to the memory array <NUM> as part of a data write operation. Additionally, the DQ connector <NUM> may operate to transmit DQ signals from the memory device <NUM>, for example, to transmit data from the memory array <NUM> as part of a data read operation. To facilitate these data reads/writes, a DQ transceiver <NUM> is present in data transceiver <NUM>. In some embodiments, for example, the DQ transceiver <NUM> may receive a clock signal generated by the internal clock generator <NUM> as a timing signal for determining an output timing of a data read operation from the memory array <NUM>. The clock signal transmitted by the internal clock generator <NUM> may be based upon one or more clocking signals received by the memory device <NUM> at clock connector <NUM> (e.g., a pin, pad, the combination thereof, etc.) and routed to the internal clock generator <NUM> via the clock input circuit <NUM>. Thus, the DQ transceiver <NUM> may receive a clock signal generated by the internal clock generator <NUM> as a timing signal for determining an output timing of a data read operation from the memory array <NUM>.

The DQ transceiver <NUM> of <FIG> may also, for example, receive one or more DQS signals to operate in strobe data mode as part of a data write operation. The DQS signals may be received at a DQS connector <NUM> (e.g., a pin, pad, the combination thereof, etc.) and routed to the DQ transceiver <NUM> via a DQS transceiver <NUM> that operates to control a data strobe mode via selective transmission of the DQS signals to the DQ transceiver <NUM>. Thus, the DQ transceiver <NUM> may receive DQS signals to control a data write operation from the memory array <NUM>.

As noted above, the data transceiver <NUM> may operate in modes to facilitate the transfers of the data to and from the memory device <NUM> (e.g., to and from the memory array <NUM>). For example, to allow for higher data rates within the memory device <NUM>, a data strobe mode in which DQS signals are utilized, may occur. The DQS signals may be driven by an external processor or controller sending the data (e.g., for a write command) as received by the DQS connector <NUM> (e.g., a pin, pad, the combination thereof, etc.). In some embodiments, the DQS signals are used as clock signals to capture the corresponding input data.

In addition, as illustrated in <FIG>, the data transceiver <NUM> also includes a serializer/deserializer <NUM> that operates to translate serial data bits (e.g., a serial bit stream) into a parallel data bits (e.g., a parallel bit stream) for transmission along data bus <NUM> during data write operations of the memory device <NUM>. Likewise, the serializer/deserializer <NUM> operates to translate parallel data bits (e.g., a parallel bit stream) into serial data bits (e.g., a serial bit stream) during read operations of the memory device <NUM>. In this manner, the serializer/deserializer <NUM> operates to translate data received from, for example, a host device having a serial format into a parallel format suitable for storage in the memory array <NUM>. Likewise, the serializer/deserializer <NUM> operates to translate data received from, for example, the memory array <NUM> having a parallel format into a serial format suitable for transmission to a host device.

<FIG> illustrates the data transceiver <NUM> as including the DQ connector <NUM> coupled to data transfer bus <NUM>, a DQ receiver <NUM>, a DQ transmitter <NUM> (which in combination with the DQ receiver <NUM> forms the DQ transceiver <NUM>), a deserializer <NUM>, and a serializer <NUM> (which in combination with the deserializer <NUM> forms the serializer/deserializer <NUM>). In operation, the host (e.g., a host processor or other memory device described above) may operate to transmit data in a serial form across data transfer bus <NUM> to the data transceiver <NUM> as part of a data write operation to the memory device <NUM>. This data is received at the DQ connector <NUM> and transmitted to the DQ receiver <NUM>. The DQ receiver <NUM>, for example, may perform one or more operations on the data (e.g., amplification, driving of the data signals, etc.) and/or may operate as a latch for the data until reception of a respective DQS signal that operates to coordinate (e.g., control) the transmission of the data to the deserializer <NUM>. As part of a data write operation, the deserializer <NUM> may operate to convert (e.g., translate) data from a format (e.g., a serial form) in which it is transmitted along data transfer bus <NUM> into a format (e.g., a parallel form) used for transmission of the data to the memory array <NUM> for storage therein.

Likewise, during a read operation (e.g., reading data from the memory array <NUM> and transmitting the read data to the host via the data transfer bus <NUM>), the serializer <NUM> may receive data read from the memory array in one format (e.g., a parallel form) used by the memory array and may convert (e.g., translate) the received data into a second format (e.g., a serial form) so that the data may be compatible with one or more of the data transfer bus <NUM> and/or the host. The converted data may be transmitted from the serializer <NUM> to the DQ transmitter <NUM>, whereby one or more operations on the data (e.g., de-amplification, driving of the data signals, etc.) may occur. Additionally, the DQ transmitter <NUM> may operate as a latch for the received data until reception of a respective clock signal, for example, from the internal clock generator <NUM>, that operates to coordinate (e.g., control) the transmission of the data to the DQ connector <NUM> for transmission along the data transfer bus <NUM> to one or more components of the host.

In some embodiments, the data received at the DQ connector <NUM> may be distorted. For example, data received at the DQ connector <NUM> may be affected by intersymbol interference (ISI) in which previously received data interferes with subsequently received data. For example, due to increased data volume being transmitted across the data transfer bus <NUM> to the DQ connector <NUM>, the data received at the DQ connector <NUM> may be distorted relative to the data transmitted by the host. One technique to mitigate (e.g., offset or cancel) this distortion and to effectively reverse the effects of ISI is to apply an equalization operation to the data. <FIG> illustrates an embodiment of the data transceiver <NUM> inclusive of an equalizer that may be used in this equalization operation.

<FIG> illustrates one embodiment of the data transceiver <NUM> inclusive of an equalizer, in particular, a decision feedback equalizer (DFE) <NUM>. As illustrated, the DFE <NUM> is a multi-tap (e.g., four-tap) DFE <NUM>. However, less or more than four taps may be utilized in conjunction with the DFE <NUM>. Likewise, the DFE <NUM> may be disposed separate from or internal to the deserializer <NUM> or the DQ receiver <NUM>. In operation, a binary output (e.g., from a latch or decision-making slicer) is captured in one or more data latches or data registers. In the present embodiment, these data latches or data registers may be disposed in the deserializer <NUM> and the values stored therein may be latched or transmitted along paths <NUM>, <NUM>, <NUM>, and <NUM>.

When a data bit is received at the DQ receiver <NUM>, it may be identified as being transmitted from the host as bit "n" and may be received at a time to as distorted bit n (e.g., bit n having been distorted by ISI). The most recent bit received prior to distorted bit n being received at the DQ receiver <NUM>, e.g., received at time of t-<NUM> that immediately precedes time of to, may be identified as n-<NUM> and is illustrated as being transmitted from a data latch or data register along path <NUM>. The second most recent bit received prior to distorted bit n being received at the DQ receiver <NUM>, e.g., received at time of t-<NUM> that immediately precedes time of ti, may be identified as n-<NUM> and is illustrated as being transmitted from a data latch or data register along path <NUM>. The third most recent bit received prior to distorted bit n being received at the DQ receiver <NUM>, e.g., received at time of t-<NUM> that immediately precedes time of t-<NUM>, may be identified as n-<NUM> and is illustrated as being transmitted from a data latch or data register along path <NUM>. The fourth most recent bit received prior to distorted bit n being received at the DQ receiver <NUM>, e.g., received at time of t-<NUM> that immediately precedes time of t-<NUM>, may be identified as n-<NUM> and is illustrated as being transmitted from a data latch or data register along path <NUM>. Bits n-<NUM>, n-<NUM>, n-<NUM>, and n-<NUM> may be considered the group of bits that interfere with received distorted bit n (e.g., bits n-<NUM>, n-<NUM>, n-<NUM>, and n-<NUM> cause ISI to host transmitted bit n) and the DFE <NUM> may operate to offset the distortion caused by the group of bits n-<NUM>, n-<NUM>, n-<NUM>, and n-<NUM> on host transmitted bit n.

Thus, the values latched or transmitted along paths <NUM>, <NUM>, <NUM>, and <NUM> may correspond, respectively, to the most recent previous data values (e.g., preceding bits n-<NUM>, n2, n-<NUM>, and n-<NUM>) transmitted from the DQ receiver <NUM> to be stored in memory array <NUM>. These previously transmitted bits are fed back along paths <NUM>, <NUM>, <NUM>, and <NUM> to the DFE <NUM>, which operates to generate weighted taps (e.g., voltages) that may be added to or subtracted from the received input signal (e.g., data received from the DQ connector <NUM>, such as distorted bit n) by means of a summer (e.g., a summing amplifier). In other embodiments, the weighted taps (e.g., voltages) may be combined with an initial reference value to generate an offset that corresponds to or mitigates the distortion of the received data (e.g., mitigates the distortion of distorted bit n). In some embodiments, taps are weighted to reflect that the most recent previously received data (e.g., bit n-<NUM>) may have a stronger influence on the distortion of the received data (e.g., distorted bit n) than bits received at earlier times (e.g., bits n-<NUM>. n-<NUM>, and n-<NUM>). The DFE <NUM> may operate to generate magnitudes and polarities for taps (e.g., voltages) due to each previous bit to collectively offset the distortion caused by those previously received bits.

For example, for the present embodiment, each of previously received bits n-<NUM>, n-<NUM>, n-<NUM>, and n-<NUM> could have had one of two values (e.g., a binary <NUM> or <NUM>), which was transmitted to the deserializer <NUM> for transmission to the memory array <NUM> and, additionally, latched or saved in a register for subsequent transmission along respective paths <NUM>, <NUM>, <NUM>, and <NUM>. In the illustrated embodiment, this leads to sixteen (e.g., <NUM><NUM>) possible binary combinations (e.g., <NUM>, <NUM>, <NUM>,. , <NUM>, or <NUM>) for the group of bits n-<NUM>, n-<NUM>, n-<NUM>, and n-<NUM>. The DFE <NUM> operates to select and/or generate corresponding tap values for whichever of the aforementioned sixteen combinations are determined to be present (e.g., based on the received values along paths <NUM>, <NUM>, <NUM>, and <NUM>) to be used to adjust either the input value received from the DQ connector <NUM> (e.g., distorted bit n) or to modify a reference value that is subsequently applied to the input value received from the DQ connector <NUM> (e.g., distorted bit n) so as to cancel the ISI distortion from the previous bits in the data stream (e.g., the group of bits n-<NUM>, n-<NUM>, n-<NUM>, and n-<NUM>).

Use of distortion correction (e.g., a DFE <NUM>) may be beneficial such that data transmitted from the DQ connector <NUM> is correctly represented in the memory array <NUM> without distortion. Accordingly, it may be useful to store the previous bit data to use in the distortion correction. As illustrated in the block diagram of <FIG>, a distortion correction circuit <NUM> may be included as part of the DQ receiver <NUM> but may not be required to be physically located there (e.g., the distortion correction circuit <NUM> may instead be coupled to the DQ receiver <NUM>). In some embodiments, the distortion correction circuit <NUM> may be operated to provide previously transmitted bit data to correct a distorted bit <NUM> (e.g., bit having been distorted by ISI and/or system distortions) transmitted via a channel <NUM> (e.g., connection, transmission line, and/or conductive material).

The distorted bit <NUM> may be transmitted to an amplifying device <NUM> (e.g., variable gain amplifier) from a channel <NUM>. The distorted bit <NUM> may be transmitted from the amplifying device <NUM> to the DFE <NUM>, illustrated as having a single weighted tap <NUM>. The distorted bit <NUM> may be transmitted simultaneously with a DQ reference signal <NUM> to the DFE <NUM>. The DQ reference signal <NUM> may represent a threshold value (e.g., a voltage level) for determination if the transmitted bit received by the DQ connection <NUM> was a logical low (e.g., <NUM>) or a logical high (e.g., <NUM>).

The DFE <NUM> may be operated to correct the distortion from the distorted bit <NUM> using the tap weighted with previous bit data (e.g., n-<NUM> bit data). Data (e.g., logical <NUM> or logical <NUM>) for an n-<NUM> bit may be transmitted through the path <NUM>. The magnitudes and polarities of the single weighted tap <NUM> may offset the total distortion caused by the n-<NUM> bit via summer circuit <NUM>, which operates as a current summer that applies current to the distorted bit <NUM> to offset for distortion caused by the n-<NUM> bit. For example, if the received bit at the DQ connection <NUM> is determined to be below the DQ reference signal <NUM>, the received bit <NUM> is transmitted to the memory array <NUM> as a logical low. The magnitude and polarity of the weighted tap <NUM> may be able to correct the distorted bit <NUM> and the DQ reference signal <NUM>.

A modified version of the distorted bit <NUM> and a modified version of the DQ reference signal <NUM> may be transmitted to a data latch <NUM>. A corrected bit <NUM> may be generated via the data latch <NUM> and transmitted from the data latch <NUM> to the deserializer <NUM>, which may occur on the rising edge of the DQS signal <NUM>. In other embodiments, variations of the clocking scheme may be followed to be inclusive of additional or alternative methods of data transmission. The value for the new n-<NUM> bit may be stored, for example, in the deserializer <NUM> for transmission along the path <NUM> when the corrected bit <NUM> is received in the deserializer <NUM>. The distortion correction circuitry associated with the DFE <NUM> and the amplifying device <NUM> may be described in greater detail below.

<FIG> illustrates a circuit diagram of a portion of the DFE <NUM> of <FIG> that may negate distortions associated with the distorted bit <NUM>. Data bits may be received at a first input <NUM> and a second input <NUM> to the summer circuit <NUM>. The first input <NUM> and the second input <NUM> may be communicatively coupled to a device that may be enabled or disabled (e.g., coupled to supply a gate signal to the field effect transistors <NUM> and <NUM>). The distorted bit <NUM> may be received by the first input <NUM> and the DQ reference signal <NUM> may be received by the second input <NUM>. In this manner, two of the field effect transistors <NUM> and <NUM> may be controlled by the distorted bit <NUM> and the DQ reference signal <NUM>.

The weighted tap <NUM> and its inverse value (e.g., inverse weighted tap <NUM>) may be transmitted to the outputs <NUM> and <NUM> to correct the distortion in the distorted bit <NUM>. A logical high for the n-<NUM> bit is transmitted through the path <NUM>. In this case, the n-<NUM> bit may be implemented to generate the weighted tap <NUM> and the inverse weighted tap <NUM> as a control signal for two field effect transistors <NUM> and <NUM> enabling the contribution of the weighted tap values <NUM> and <NUM> to the outputs <NUM> and <NUM>.

The weighted tap values <NUM> and <NUM> may allow for current to be applied to outputs <NUM> and <NUM>, whereby the current supplied is controlled through a controllable source <NUM> (e.g., a current source <NUM> controlled by a digital to analog (DAC) converter <NUM>). The outputs <NUM> and <NUM> may be modified values of one or more of the DQ reference signal <NUM> and the distorted bit <NUM> and may be transmitted to the data latch <NUM> (e.g., a regenerative latch or slicer that generates a binary output). The corrected bit <NUM> may be generated via the data latch <NUM> based on the outputs <NUM> and <NUM> and may be transmitted to the deserializer <NUM> on the rising edge of the DQS signal <NUM>. The n-<NUM> bit information stored for transmission along the path <NUM> in the deserializer <NUM> may be updated with the corrected bit <NUM> for future distortion corrections.

In some applications, the corrected bit <NUM> may need to have a greater level of precision of adjustment than the weighted taps <NUM> and <NUM> may otherwise provide. <FIG> illustrates a block diagram of a distortion correction circuit <NUM> that may receive four bits of previous data (e.g., n-<NUM> bit data, n-<NUM> bit data, n-<NUM> bit data, and n-<NUM> bit data) to create four weighted taps <NUM>, <NUM>, <NUM>, and <NUM> to perform a more precise distortion correction to the distorted bit <NUM>. In a similar manner to the distortion correction circuit <NUM>, the distorted bit <NUM> may be transmitted to the amplifying device <NUM> via the channel <NUM>. The DQ reference signal <NUM> may also be transmitted to the amplifying device <NUM>.

From the amplifying device <NUM>, the distorted bit <NUM> and the DQ reference signal <NUM> may be transmitted to the DFE <NUM>. Bit data for the previous bits may be transmitted through the paths <NUM>, <NUM>, <NUM>, and <NUM>. The DFE <NUM> may be operated to correct the distortion from the distorted bit <NUM> using the four weighted taps <NUM>, <NUM>, <NUM>, and <NUM> created from the bit data for the four previous bits. The DFE <NUM> may be operated to generate magnitudes and polarities for each of the weighted taps <NUM>, <NUM>, <NUM>, and <NUM> for each of the previous bits transmitted along paths <NUM>, <NUM>, <NUM>, and <NUM> which may be designed to offset the total distortion to the distorted bit <NUM> caused by the previously received bits.

One or more of a modified version of the distorted bit <NUM> and a modified version of the DQ reference signal <NUM> may be transmitted to the data latch <NUM>. The corrected bit <NUM> may be transmitted to the deserializer <NUM> on the rising edge of the DQS signal <NUM> from the data latch <NUM>. The deserializer <NUM> may be updated with the values for the n-<NUM> bit, n-<NUM> bit, n-<NUM> bit, and the n-<NUM> bit and the values may be stored for transmission along the paths <NUM>, <NUM>, <NUM>, and <NUM>. The distortion correction circuitry associated with the DFE <NUM> may be described in greater detail below.

<FIG> illustrates a circuit diagram of a portion of the DFE <NUM> of <FIG> that may negate distortions. As additionally illustrated in <FIG>, the DFE <NUM> may receive a logical high or low for the n-<NUM> bit, the n-<NUM> bit, the n-<NUM> bit, or the n-<NUM> bit, or any combination therein through the data transmitted on paths <NUM>, <NUM>, <NUM>, and <NUM>. In this case, data transmitted along the paths <NUM>, <NUM>, <NUM>, and <NUM> may be implemented to generate the weighted taps <NUM>, <NUM>, <NUM>, and <NUM> and the inverse weighted taps <NUM>, <NUM>, <NUM>, and <NUM> as control signals for the field effect transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> to control outputs therefrom transmitted to the outputs <NUM> and <NUM>. The field effect transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may be selectively and controllably activated to reflect one of the sixteen (e.g., <NUM>) different possible binary states represented by the various combinations of previously corrected bits (e.g., <NUM>, <NUM>, <NUM>,.

The weighted tap <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> values may be applied to the outputs <NUM> and <NUM>, whereby the current supplied is controlled through the controllable source <NUM> and additional controllable sources <NUM>, <NUM>, and <NUM> (e.g., each having a respective current source <NUM>, <NUM>, <NUM>, and <NUM> controlled by a DAC <NUM>, <NUM>, <NUM>, <NUM>). The outputs <NUM> and <NUM> may be transmitted to the data latch <NUM>. The corrected bit <NUM> may be generated via the data latch <NUM> based upon the outputs <NUM> and <NUM> and may be transmitted to the deserializer <NUM> on the rising edge of the DQS signal <NUM>. The n-<NUM> bit, the n2 bit, the n-<NUM> bit, and the n-<NUM> bit information stored for transmission along the paths <NUM>, <NUM>, <NUM>, and <NUM> in the deserializer <NUM> may be updated with the corrected bit <NUM> (e.g., n-<NUM> bit will update to reflect n-<NUM> data, n-<NUM> bit will update to reflect n-<NUM> data, n-<NUM> data will update to reflect n-<NUM> data, and n-<NUM> data will update with the newly corrected bit) for future distortion corrections.

In some embodiments, the DAC <NUM> may alter and/or control the current contribution of the controllable source <NUM> and additional DACs <NUM>, <NUM>, and <NUM> may alter and/or control the current contribution of the additional controllable sources <NUM>, <NUM>, and <NUM> by controlling the respective current sources <NUM>, <NUM>, <NUM>, and <NUM>. In such embodiments, the DACs <NUM>, <NUM>, <NUM>, and <NUM> may include a fixed circuit capable of supplying a specified output (e.g., voltage) to the current sources <NUM>, <NUM>, <NUM>, and <NUM>. As such, the DACs <NUM>, <NUM>, <NUM>, and <NUM> may supply the same outputs to inputs of the respective current sources <NUM>, <NUM>, <NUM>, and <NUM> regardless of variations in PVT conditions (e.g., variations in operating temperatures outside standard operating conditions). In other embodiments, the DACs <NUM>, <NUM>, <NUM>, and <NUM> may generate outputs that change as a result of PVT conditions, however, the changes outputs may not always vary in a suitable and/or controllable manner. That is, for a given set of PVT conditions, there may not exist a direct relationship between the outputs of the DACs <NUM>, <NUM>, <NUM>, and <NUM> and the outputs of the current sources <NUM>, <NUM>, <NUM>, and <NUM> (e.g., the resulting outputs of the controllable sources <NUM>, <NUM>, <NUM>, and <NUM>). As such, even if the outputs of the DACs <NUM>, <NUM>, <NUM>, and <NUM> and the resulting outputs of the current sources <NUM>, <NUM>, <NUM>, and <NUM> are both influenced by PVT conditions, as the PVT conditions change, the DAC output required to suitably control a controllable source so that it contributes a suitable current from a respective weighted tap (e.g., <NUM>, <NUM>, <NUM>, <NUM>) to accurately reflect conditions affecting the DFE <NUM> may also change. For example, to modify the current of the outputs <NUM> and <NUM> by a specified current for a set of PVT conditions, the controllable source <NUM> may utilize a first input level received from the DAC <NUM>. To modify the current of the outputs <NUM> and <NUM> by the same specified current for a different set of PVT conditions, a second input level at the controllable source <NUM> from the DAC <NUM> may be suitable. Thus, the DACs <NUM>, <NUM>, <NUM>, and <NUM> may provide fixed outputs and/or outputs incapable of adjusting suitably across varying PVT conditions to adjust the outputs of the current sources <NUM>, <NUM>, <NUM>, and <NUM> so that the controllable sources <NUM>, <NUM>, <NUM>, and <NUM> correctly operate to compensate for varying conditions affecting the DFE <NUM>.

Accordingly, <FIG> illustrates a bias generator <NUM> that may generate PVT tolerant bias levels to suitably adjust the controllable sources <NUM>, <NUM>, <NUM>, and <NUM> of <FIG>, regardless of the PVT conditions. That is, in place of the DACs <NUM>, <NUM>, <NUM>, and <NUM> illustrated in <FIG>, an output of the bias generator <NUM> may be communicatively coupled to, for example, the input of the current sources <NUM>, <NUM>, <NUM>, and <NUM> to control the output thereof and, accordingly, the output of the controllable sources <NUM>, <NUM>, <NUM>, and <NUM>.

In some embodiments, the bias generator <NUM> may accept two inputs, DQ reference signal <NUM> and a modified DQ reference signal <NUM> and may output a bias level NBias <NUM> suitable to control the controllable source <NUM>. The input DQ reference signal <NUM> may represent the same signal DQ reference signal <NUM> input to the DFE <NUM> in <FIG>. That is, DQ reference signal <NUM> may represent a threshold value (e.g., a voltage level) for determination if a bit received by the bias generator <NUM> was a logical low (e.g., <NUM>) or a logical high (e.g., <NUM>). The second input, modified DQ reference signal <NUM> may represent the combination of a correction factor "X" (e.g., <NUM> mV) added to the DQ reference signal <NUM>. The correction factor X may represent a level of correction (e.g., distortion removal) to result in a desired output for the controllable source <NUM>, <NUM>, <NUM>, and <NUM>. That is, to adjust the data (e.g., a bit) on the data channel by a certain amount (e.g., 5mv) to, for example, generate corrected bit <NUM>, the correction factor X may match this amount. As such, the correction factor X may adjust the outputs <NUM> and <NUM> of the summer circuit <NUM> by some level multiplied by a gain (e.g., Gain*X), as the outputs <NUM> and <NUM> may have additional gain applied by, for example, an amplifying device <NUM>. Further, in some embodiments, the desired level of correction contributed by each weighted tap <NUM>, <NUM>, <NUM>, and <NUM> in the summer circuit <NUM> may be programmed and/or adjusted by a user in order to suitably calibrate the memory device <NUM>. That is, each weighted tap <NUM>, <NUM>, <NUM>, and <NUM> may be set to adequately remove distortion from the data channel, and because the correction applied to the outputs <NUM> and <NUM> may depend on a combination of the weighted taps <NUM>, <NUM>, <NUM>, and <NUM> and the controllable sources <NUM>, <NUM>, <NUM>, and <NUM>, the correction factor X may also be based on a programmed and/or user adjusted value.

Although the desired level of correction may be received as part of an input (e.g., correction factor X) to the bias generator <NUM>, at any set of PVT conditions, the suitable bias level (e.g., NBias <NUM>) for the bias generator <NUM> to input to the current source <NUM>, <NUM>, <NUM>, or <NUM> in order to generate a suitable amount of current correction may not be known.

That is, there may not exist a direct and/or well-defined relationship between the bias level NBias <NUM> output by the bias generator <NUM> and the resulting current generated by the controllable source <NUM>. As a result, there may also not exist a direct and/or well-defined relationship between the bias level NBias <NUM> and the correction applied by the summer circuit <NUM>. Thus, in some embodiments, to determine the suitable bias level NBias <NUM> output, the bias generator <NUM> may first receive the desired correction level (e.g., correction factor X) as an input and determine the bias level NBias <NUM> resulting from this correction level, as will be described further.

In such embodiments, the DQ reference signal <NUM> and the modified DQ reference signal <NUM> may be applied to a receiver <NUM> emulating the DQ receiver <NUM>, as further described below. That is, the correction factor X may be applied to the receiver <NUM> so that the behavior resulting from applying the correction factor X to the DQ receiver <NUM> may be determined. As such, the receiver <NUM> may output signals OutF <NUM> and Out <NUM> that may correspond to the input signals modified DQ reference signal <NUM> and DQ reference signal <NUM>, as adjusted to the behavior of the DQ receiver <NUM>.

The outputs of the receiver <NUM> (e.g., OutF <NUM> and Out <NUM>) feed into an operational amplifier (op-amp) <NUM>, which is a differential amplifier. The op-amp <NUM> may determine the difference between OutF <NUM> and Out <NUM> and multiply this difference by a gain before outputting the result, bias level NBias <NUM>. The resulting bias level NBias <NUM> may feedback into the receiver <NUM> so that the Out <NUM> and/or OutF <NUM> signals may be adjusted until they are nearly equal (e.g., until the op-amp <NUM> stabilizes the value of the bias level NBias <NUM>). As such, the bias generator <NUM> may work to determine a suitable bias level NBias <NUM>. That is, after applying a correction factor X to DQ reference signal <NUM> (e.g., modified DQ reference signal <NUM>), the results (e.g., OutF <NUM> and Out <NUM>) of the receiver <NUM> may be compared (e.g., by the opamp <NUM>) and subsequently adjusted to determine the bias level NBias <NUM> value required to equalize OutF <NUM> and Out <NUM>. Thus, the stabilized bias level NBias <NUM> may represent a suitable bias level for the receiver <NUM> to correct the DQ reference signal <NUM> to the modified DQ reference signal <NUM> (e.g., for Out <NUM> to equal OutF <NUM>), or to implement the desired correction level.

Because the bias generator <NUM> may emulate a set of PVT conditions of the DQ receiver <NUM> in the receiver <NUM> and may use bias level NBias <NUM> in a feedback loop, bias level NBias <NUM> may stabilize at a bias level suitable to control one of the current sources <NUM>, <NUM>, <NUM>, and <NUM> to which it is coupled to control the output thereof and, accordingly, the output of the controllable sources <NUM>, <NUM>, <NUM>, and <NUM> in connection with the PVT conditions. As the PVT conditions change, the bias level NBias <NUM> may stabilize at a different bias level that is suitable to control the controllable source <NUM> at the updated PVT conditions. Further, the value of bias level NBias <NUM> may stabilize when the outputs (e.g., OutF <NUM> and Out <NUM>) are nearly equal as a result of limitations of op-amps (e.g., op-amp <NUM>). As such, an op-amp with high gain may be used to decrease the error (e.g., reduce the difference) between the final outputs (e.g., OutF <NUM> and Out <NUM>). Further, with high gain, the small difference between the nearly equal OutF <NUM> and Out <NUM> may be multiplied number into a detectable bias level NBias <NUM> that may suitably control the controllable source <NUM> so that the appropriate current correction may be made in the summer circuit <NUM>.

Turning now to <FIG>, a more detailed embodiment of the receiver <NUM> is provided. While the embodiment is referred to as a receiver, it should be noted that receiver <NUM> receives data signals generated internal to memory device <NUM> and may be used to emulate the operation conditions, including PVT conditions, of other receivers (e.g., DQ receiver <NUM>). In the illustrated embodiment, the DQ receiver <NUM> is emulated, and more specifically, the summer circuit <NUM> of the DQ receiver <NUM> is emulated. While not shown in the illustrated embodiment, in some embodiments, the receiver <NUM> may additionally contain an amplifying device to emulate the amplifying device <NUM> that the DQ receiver <NUM> may contain.

In the illustrated embodiment, similar to the summer circuit <NUM>, the receiver <NUM> may adjust the outputs <NUM> and/or <NUM> of the circuit. The receiver may receive the DQ reference signal <NUM> at a first input <NUM> and the modified DQ reference signal <NUM> at a second input <NUM>. The first input <NUM> and the second input <NUM> may enable or disable to the field effect transistors <NUM> and <NUM> (e.g., may supply a gate signal to the field effect transistors <NUM> and <NUM>). In this manner, the field effect transistors <NUM> and <NUM> may be controlled by the DQ reference signal <NUM> and the modified DQ reference signal <NUM>.

A controllable source <NUM> coupled to a pair of field effect transistors <NUM> and <NUM> may apply current to the outputs Out <NUM> and OutF <NUM> under the control of the bias level NBias <NUM>. The outputs Out <NUM> and OutF <NUM> may represent modified values of the DQ reference signal <NUM> and the modified DQ reference signal <NUM>, respectively. As such, in some embodiments, because the modified DQ reference signal <NUM> is greater than DQ reference signal <NUM> (e.g., by correction factor X mV) the output OutF <NUM> corresponding to the modified DQ reference signal <NUM> may be greater than Out <NUM>. Thus, the receiver <NUM> may use a resistive load <NUM> to pull the Out <NUM> signal up (e.g., higher) to a value closer to the value of OutF <NUM>. In the case that the value of Out <NUM> is greater than the value of OutF <NUM>, the receiver <NUM> may use bias level NBias <NUM> to pull the Out <NUM> signal down (e.g., lower) to bring a value closer to the value of OutF <NUM>. The resulting values of Out <NUM> and OutF <NUM> may then feed into the op-amp <NUM>, as illustrated in <FIG>, where the most recent difference between Out <NUM> and OutF <NUM> may be determined to generate a resulting NBias <NUM> value. As the NBias <NUM> may feedback into the receiver <NUM>, the difference between the Out <NUM> and OutF <NUM> values may continuously update. Further, the difference between the Out <NUM> and OutF <NUM> values may continuously dictate the manner in which the receiver <NUM> adjusts the Out <NUM> signal via bias level NBias <NUM> and/or the resistive load <NUM>.

With the foregoing in mind, <FIG> illustrates a flow chart of a method <NUM> for generating the suitable bias level NBias <NUM> to control the controllable source <NUM>, regardless of the PVT conditions, in accordance with embodiments described herein. Although the following description of the method <NUM> is described in a particular order, which represents a particular embodiment, it should be noted that the method <NUM> may be performed in any suitable order, and steps may be added or omitted.

At block <NUM>, the bias generator <NUM> may receive input signals, the DQ reference signal <NUM> and the modified DQ reference signal <NUM> at receiver <NUM>. As illustrated in <FIG>, in some embodiments, these input signals may be received at a first input <NUM> and a second input <NUM> in the receiver <NUM>. At block <NUM>, the receiver <NUM> may then generate outputs Out <NUM> and OutF <NUM> based on the input signals (e.g., the DQ reference signal <NUM> and the modified DQ reference signal <NUM>) and the feedback bias level NBias <NUM>. As discussed earlier, block <NUM> may involve pulling Out <NUM> up or down using the resistive load <NUM> or bias level NBias <NUM>, respectively. Further, pulling Out <NUM> up or down and the level at which the value of Out <NUM> is modified may depend on bias level NBias <NUM>, which may control the current contribution of the controllable source <NUM>. The signals output from the receiver <NUM> (e.g., Out <NUM> and OutF <NUM>) may then feed into an op-amp <NUM> at block <NUM> (illustrated in <FIG>). At block <NUM>, the op-amp <NUM> may generate the bias level NBias <NUM>, according to the equation <MAT> where the Gain term may represent a large number determined by the operating characteristics of the op-amp <NUM> used. In some embodiments, this calculation may occur concurrently with block <NUM>, where the values of Out <NUM> and OutF <NUM> are compared in the equation above to calculate bias level NBias <NUM>. At block <NUM>, if Out <NUM> and OutF <NUM> are approximately equal (e.g., the op-amp <NUM> has stabilized the bias level NBias <NUM> and/or the difference between Out <NUM> and OutF <NUM> is indistinguishable to the op-amp <NUM>, given its operating capabilities), then the bias level NBias <NUM> may be used to control the controllable source <NUM>. With the control of the stabilized bias level NBias <NUM>, the controllable source <NUM> may, at block <NUM>, generate a suitable correction in the summer circuit <NUM>. In some embodiments, at block <NUM>, if Out <NUM> and OutF <NUM> are not approximately equal, the opamp <NUM> may, at block <NUM> adjust the value of bias level NBias <NUM> to reduce the difference between Out <NUM> and OutF <NUM>. The NBias <NUM> adjusted at block <NUM> may then feedback into the receiver <NUM>. As a result, at block <NUM>, the receiver <NUM> may receive the adjusted bias level NBias <NUM> and may regenerate the outputs Out <NUM> and OutF <NUM> based on the adjusted bias level NBias <NUM> and the input signals DQ reference signal <NUM> and the modified DQ reference signal <NUM> and may continue through method <NUM> to generate a suitable Nbias <NUM> to control the controllable source <NUM>.

Further, while bias level NBias <NUM> has been described as either being fed back at from block <NUM> to the receiver <NUM> or used to control the controllable source <NUM> depending on the result of the comparison at block <NUM>, to one skilled in the art, it should be understood that these actions may occur simultaneously. Further, these bias level NBias <NUM> actions may occur regardless of the result of the comparison at block <NUM>. That is, in the illustrated embodiment of <FIG>, the bias generator <NUM> may not contain any circuitry and/or logic to gate bias level NBias <NUM> as it is output to the controllable source <NUM> and/or as it is fed back into the receiver <NUM>. As such, the receiver <NUM> and the controllable source <NUM> may continuously receive bias level NBias <NUM>, regardless of the difference between Out <NUM> and OutF. That is, receiver <NUM> and controllable source <NUM> may continue to receive bias level NBias <NUM> regardless of whether bias level NBias <NUM> has stabilized or not. However, in some embodiments, the op-amp <NUM> may stabilize bias level NBias <NUM> before the summer circuit <NUM> is ready to use bias level NBias <NUM>. That is, the DQS receiver <NUM> and/or the memory device <NUM> may include an initialization procedure that may include certain delays to allow their systems to power on and calibrate (e.g., stabilize) certain values (e.g., bias level NBias <NUM>) adequately before they may be used.

In some embodiments, tap corrections in conjunction with the summer circuits <NUM> described above utilize differential pairs of transistors that create imbalance in the summer proportional to a set value. The imbalance may be, for example, created by a pulldown transistor enabled on only one side of the differential pair of transistors based on the sign of correction required. However, in some embodiments, as the common-mode signal (e.g., a common-mode current) of the summer circuits <NUM> changes across operation conditions, the impact of the analog value set by the respective a controllable sources (e.g., the current sources controlled by the DACs <NUM>, <NUM>, <NUM>, and <NUM>) may not remain constant i.e. the tap response from the summer circuit <NUM> becomes non-linear. Accordingly, in some embodiments, a push-pull summer approach that adds and subtracts current in predetermined amounts (e.g., in equal measure) may be utilized to maintain a consistent average commonmode signal, which allows the tap response to be much more linear. For example, as illustrated in <FIG>, a push-pull summer <NUM> (e.g., a push-pull summation circuit) may be utilized to accomplish DFE correction. The push-pull summer <NUM> includes pull circuitry <NUM> and push circuitry <NUM> to add and subtract current from the summer in order to maintain a constant average common-mode signal. In some embodiments, the push-pull summer <NUM> may subtract current in equal amounts, however it might also be useful to subtract in unequal amounts if that results in a more linear tap response.

Accordingly, <FIG> illustrates a circuit diagram of a portion of the DFE <NUM> of <FIG> that may negate distortions via use of the push-pull summer <NUM> in place of summer circuit <NUM>. The push-pull summer <NUM> contains pull circuitry <NUM> and push circuitry <NUM>. The pull circuitry <NUM> operates generally similarly to what was described above with respect to <FIG>. However, the push-pull summer <NUM> utilizes both of the pull circuitry <NUM> and push circuitry <NUM> to adjust current in predetermined amounts (e.g., in equal measure) and may be utilized to maintain a consistent average common-mode signal, which allows the tap response to be much more linear. A DFE <NUM> having the push-pull summer <NUM> of <FIG> may receive a logical high or low for the n-<NUM> bit, the n-<NUM> bit, the n-<NUM> bit, or the n-<NUM> bit, or any combination therein through the data transmitted on paths <NUM>, <NUM>, <NUM>, and <NUM>. In this case, data transmitted along the paths <NUM>, <NUM>, <NUM>, and <NUM> may be implemented to generate the weighted taps <NUM>, <NUM>, <NUM>, and <NUM> and the inverse weighted taps <NUM>, <NUM>, <NUM>, <NUM> as control signals for the field effect transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> as well as for the control signals for the field effect transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> to control outputs therefrom transmitted to the outputs <NUM>, <NUM>. Field effect transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are part of the pull circuitry <NUM>, while field effect transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are part of the push circuitry <NUM>. The field effect transistors <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> of the push-pull summer <NUM> may be selectively and controllably activated to reflect one of the sixteen (e.g., <NUM><NUM>) different possible binary states represented by the various combinations of previously corrected bits (e.g., <NUM>, <NUM>, <NUM>.

The weighted taps <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> values may be applied to the outputs <NUM> and <NUM>, whereby the current supplied is controlled through the controllable source <NUM> and additional controllable sources <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> (e.g., a current source controlled by a respective bias generator <NUM>). Alternatively, each bias generator <NUM> could be replaced by a DAC, such as any one of DAC <NUM>, <NUM>, <NUM>, and <NUM> of <FIG>. The outputs <NUM> and <NUM> may be transmitted to a data latch, such as data latch <NUM>. The controllable sources <NUM> and <NUM> may both supply current to the same weighted taps <NUM> and <NUM>, however this may be supplied through different circuits (i.e., <NUM> supplies current to the pull circuitry <NUM> and <NUM> supplies current to the push circuitry <NUM>), whereby the supplied currents may have equal or unequal values depending on the linear response of the DFE <NUM>. The push-pull summer <NUM> may operate to add and subtract the supplied currents in equal measure from the differential nodes (e.g., the connection points with the outputs <NUM> and <NUM> of the pull circuitry <NUM> and push circuitry <NUM>) in order to maintain constant average common-mode signal. This may allow for the various tap responses to have improved linearity.

For example, if the pull circuitry <NUM> operates alone (e.g., if the push circuitry <NUM> is not present), the DFE <NUM> may operate as described generally with respect to <FIG>. That is, weighted tap <NUM> and its inverse value (e.g., inverse weighted tap <NUM>) may be transmitted to the outputs <NUM> and <NUM> to correct the distortion in the distorted bit <NUM>. A logical high for the n-<NUM> bit is transmitted through the path <NUM>. In this case, the n-<NUM> bit may be implemented to generate the weighted tap <NUM> and the inverse weighted tap <NUM> as a control signal for two field effect transistors <NUM> and <NUM> enabling the contribution of the weighted tap values <NUM> and <NUM> to the outputs <NUM> and <NUM>. For example, if the correction due to the n-<NUM> bit is, for example, <NUM> mV, if the pull circuitry <NUM> operates alone (e.g., if the push circuitry <NUM> is not present), all of the correction to be applied with respect to weighted tap <NUM> and its inverse value (e.g., inverse weighted tap <NUM>) comes from the differential pair of field effect transistors <NUM> and <NUM>. However, by using the pull circuitry <NUM> in conjunction with the push circuitry <NUM>, if the correction due to the n-<NUM> bit is, for example, <NUM> mV, the pull circuitry <NUM> may operate to effect 25mV of correction to be applied from the differential pair of field effect transistors <NUM> and <NUM> and 25mV of correction to be applied from the differential pair of field effect transistors <NUM> and <NUM>.

Additionally, non-equal values may instead be applied in pull circuitry <NUM> in conjunction with the push circuitry <NUM>. For example, a <NUM>% correction may be applied from a differential pair of field effect transistors in the pull circuitry <NUM> and a <NUM>% correction may be applied from a differential pair of field effect transistors in the push circuitry <NUM> corresponding to the differential pair of field effect transistors in the pull circuitry <NUM>, a <NUM>% correction may be applied from a differential pair of field effect transistors in the pull circuitry <NUM> and a <NUM>% correction may be applied from a differential pair of field effect transistors in the push circuitry <NUM> corresponding to the differential pair of field effect transistors in the pull circuitry <NUM>, a <NUM>% correction may be applied from a differential pair of field effect transistors in the pull circuitry <NUM> and a <NUM>% correction may be applied from a differential pair of field effect transistors in the push circuitry <NUM> corresponding to the differential pair of field effect transistors in the pull circuitry <NUM>, a <NUM>% correction may be applied from a differential pair of field effect transistors in the pull circuitry <NUM> and a <NUM>% correction may be applied from a differential pair of field effect transistors in the push circuitry <NUM> corresponding to the differential pair of field effect transistors in the pull circuitry <NUM>, or additional ratios may be utilized as desired to maintain consistency of the common-mode signal generated by the DFE <NUM>. Similarly, equal ratio or differing ratio values for currents may be applied to controllable sources <NUM> and <NUM>, controllable sources <NUM> and <NUM>, and controllable sources <NUM> and <NUM>. The corrected bit <NUM> may be generated via the data latch <NUM> based upon the outputs <NUM> and <NUM> and may be transmitted to the deserializer <NUM> on the rising edge of the DQS signal <NUM>. The n-<NUM> bit, the n-<NUM> bit, the n-<NUM> bit, and the n-<NUM> bit information stored for transmission along the paths <NUM>, <NUM>, <NUM>, and <NUM> in the deserializer <NUM> may be updated with the corrected bit <NUM> (e.g., n-<NUM> bit will update to reflect n3 data, n-<NUM> bit will update to reflect n-<NUM> data, n-<NUM> data will update to reflect n-<NUM> data, and n-<NUM> data will update with the newly corrected bit) for future distortion corrections.

The bias generators <NUM> may supply PVT tolerant outputs to control the controllable sources (e.g., controllable sources <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>) in the push-pull summer <NUM>. Further, because the push-pull summer may incorporate pull circuitry <NUM> and push circuitry <NUM>, the control of a controllable source in the pull circuitry <NUM> may coordinate with a control of a corresponding controllable source in the push circuitry <NUM> in order to set a suitable correction contribution from each controllable source. That is for example, a control for the controllable source <NUM> may coordinate with a control of the controllable source <NUM> so that the pull circuitry <NUM> and the push circuitry <NUM> may each apply a suitable correction to the distorted bit <NUM>. As such, in some embodiments, a mirrored-output bias generator <NUM> in place of the bias generators <NUM> or DACs such as DAC <NUM> may be used to generate PVT tolerant outputs to suitably adjust a corresponding pair of controllable sources (e.g., controllable source <NUM> and controllable source <NUM>) in the pull circuitry <NUM> and push circuitry <NUM>.

Turning to <FIG>, the mirrored-output bias generator <NUM> may include a pair of mirrored output bias levels (e.g., bias level NBias <NUM> and bias level PBias <NUM>) that may mirror each other. That is, in some embodiments, bias level PBias <NUM> may represent a bias level suitable to cause a P-type metal-oxide-semiconductor field effect transistor (PMOS) to generate the same amount of current (e.g., <NUM> microamperes) that the mirrored bias level NBias <NUM> may cause an N-type metal-oxide-semiconductor field effect transistor (NMOS) to generate. The mirrored bias levels (e.g., bias level NBias <NUM> and bias level PBias <NUM>) may thus control a controllable source in the pull circuitry <NUM> and the push circuitry <NUM>, respectively, of the push-pull summer <NUM>. Thus, the mirrored-output bias generator <NUM> may generate PVT tolerant outputs (e.g., bias level NBias <NUM> and bias level PBias <NUM>) that may cause a pair of controllable sources across push circuitry <NUM> and pull-circuitry <NUM> in a pushpull summer <NUM> (e.g., controllable source <NUM> and controllable source <NUM>) to effect suitable correction to the output signals <NUM> and <NUM>.

In order to generate the mirrored bias levels (e.g., bias level NBias <NUM> and bias level PBias <NUM>), the mirrored-output bias generator <NUM> may contain additional structures and connectivity when compared to the bias generator <NUM> of <FIG>. In some embodiments, for example, the op-amp <NUM> of mirrored-output bias generator <NUM> may connect to a current mirror <NUM> instead of directly outputting to the controllable source <NUM>. The current mirror <NUM> may receive the bias level NBias <NUM> as an input and output the equivalent bias level signal for a PMOS (e.g., PBias <NUM>) from a diode connected field effect transistor <NUM>. The current mirror <NUM> may also receive enable signals (e.g., En <NUM> and EnF <NUM>) as inputs to activate (e.g., enable) the current mirror <NUM>. In some embodiments, the enable signals (e.g., En <NUM> and EnF <NUM>) may be set to maintain the current mirror <NUM> in an active state while the DQ receiver <NUM> is powered on. That is, the current mirror <NUM> may continue to function while the circuits within the DQ receiver <NUM> receive power.

Further, in some embodiments, the bias level PBias <NUM> generated by the current mirror <NUM> may feedback into a receiver <NUM>. As such, in addition to receiving the DQ reference signal <NUM> and the modified DQ reference signal <NUM> as inputs, the receiver <NUM> may receive two feedback signals (e.g., bias level NBias <NUM> and bias level PBias <NUM>). Thus, though the receiver <NUM> may output Out <NUM> and OutF <NUM> to the op-amp <NUM>, the receiver <NUM> may generate its outputs (e.g., Out <NUM> and OutF <NUM>) in a different manner than receiver <NUM> in order to handle the bias level PBias <NUM> feedback signal, in addition to the bias level NBias <NUM> feedback signal.

Turning now to <FIG>, an embodiment of the receiver <NUM> may be illustrated. The receiver <NUM> may include the components of the receiver <NUM> with an additional controllable source <NUM> coupled to an additional pair of field effect transistors <NUM> and <NUM> that may apply current to the outputs Out <NUM> and OutF <NUM> in combination with the current applied by the controllable source <NUM> and the pair of field effect transistors <NUM> and <NUM>. Further, the operation of the receiver <NUM> may resemble that of the receiver <NUM>. While receiver <NUM> may modulate an output signal (e.g., Out <NUM>) of the input signal (e.g., the DQ reference signal <NUM>) according to the value of bias level NBias <NUM>, the receiver <NUM> may modulate the values of both Out <NUM> and OutF <NUM>, according to both bias level NBias <NUM> and bias level PBias <NUM>. In some embodiments, for example, because the modified DQ reference signal <NUM> is greater than the DQ reference signal (e.g., by X mV) the output OutF <NUM> corresponding to the modified DQ reference signal <NUM> may be higher than Out <NUM>. With the additional controllable source <NUM> coupled to the additional pair of field effect transistors <NUM> and <NUM> included in the structure of the receiver <NUM>, additionally or in the alternative of using the resistive load <NUM> to pull up the value of Out <NUM>, the bias level PBias <NUM> may drive the additional controllable source <NUM> to bring the value of OutF <NUM> down (e.g., lower) closer to Out <NUM>. In the case that the value of Out <NUM> is greater than the value of OutF <NUM>, the controllable source <NUM> may pull Out <NUM> down (e.g., lower) to bring its value closer to OutF <NUM>. Additionally or alternatively, the resistive load <NUM> may pull OutF <NUM> up (e.g., higher) to bring its value closer to Out <NUM>. The resulting values of Out <NUM> and OutF <NUM> may then be fed into the op-amp <NUM>, as illustrated in <FIG>, and the most recent difference between Out <NUM> and OutF <NUM> may be used to calculate a resulting bias level NBias <NUM> value, according to the same method used in the receiver <NUM>.

Thus, a method to generate the mirrored bias levels of bias level NBias <NUM> and bias level PBias <NUM> with the mirrored-output bias generator <NUM> may generally follow the method <NUM> that may generate bias level NBias <NUM> from the bias generator <NUM>. That is, each of the blocks and/or paths (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>) in the illustrated embodiment of the method <NUM> in <FIG> may be performed with slight modifications in the method to generate the mirrored bias levels (e.g., bias level NBias <NUM> and bias level PBias <NUM>). That is, in place of exclusively using bias level NBias <NUM> as a feedback value for the receiver <NUM> to calculate Out <NUM> and OutF <NUM> at block <NUM>, both bias level NBias <NUM> and bias level PBias <NUM> may be used by the receiver <NUM> to calculate Out <NUM> and OutF <NUM>. Further, after bias level NBias <NUM> is generated at block <NUM>, the current mirror <NUM> may generate its mirrored signal, bias level PBias <NUM>. Bias level PBias <NUM> may feedback to the receiver <NUM> and/or control a controllable source (e.g., controllable source <NUM>) in the push circuitry <NUM> of the push-pull summer <NUM>, based on the comparison of Out <NUM> and OutF <NUM>, as described in block <NUM> and block <NUM>. Bias level NBias <NUM> may also feedback to receiver <NUM> and/or control a controllable source (e.g., controllable source <NUM>) in the pull circuitry <NUM> of the push-pull summer <NUM>, as described in block <NUM>. Thus, using the bias level NBias <NUM> and bias level PBias <NUM> as feedback in its receiver <NUM>, the mirrored-output bias generator <NUM> may generate PVT tolerant outputs (e.g., bias level NBias <NUM> and bias level PBias <NUM>) that may cause a pair of controllable sources across push circuitry <NUM> and pull-circuitry <NUM> in a push-pull summer <NUM> (e.g., controllable source <NUM> and controllable source <NUM>) to effect suitable correction to the output signals <NUM> and <NUM>.

Turning now to <FIG>, an example of a circuit that may increase the processing speed of distortion correction is illustrated. The distortion correction circuit <NUM> which may be capable of processing four data bits at a four bit distortion correction level, and includes four distortion correction circuits <NUM>, <NUM>, <NUM>, and <NUM> which are similar to the distortion correction circuit <NUM> described in <FIG> with modification to the inputs between the duplications, but no amplifying device <NUM> (although a similar circuit could instead include the amplifying device <NUM>). Furthermore, the summers <NUM>, <NUM>, <NUM>, and <NUM> may operate as described in <FIG>. The four distortion circuits <NUM>, <NUM>, <NUM>, and <NUM> are referred to as a first circuit <NUM>, a second circuit <NUM>, a third circuit <NUM>, and a fourth circuit <NUM>. The method of rolling the distorted bit <NUM> received may be followed. As such, the distorted bit <NUM> may be received by the first circuit <NUM>, the second distorted bit <NUM> may be received by the second circuit <NUM>, the third distorted bit <NUM> may be received by the third circuit <NUM>, a fourth distorted bit <NUM> may be received by the fourth circuit <NUM>, and a fifth distorted bit may be rolled back to be received by the first circuit once the first iteration of the distortion correction is complete.

In some embodiments, a first bit stream may be transmitted to the channel <NUM> at t=<NUM>. Enough time may not have passed between the transmission of an n-<NUM> bit prior in time to the distorted bit <NUM> (e.g., the "n bit") to allow for calculation of the distortion contribution of the n-<NUM> bit to the distorted bit <NUM>. If this occurs, one solution may be to wait for the n-<NUM> bit information to complete transmitting to the deserializer <NUM> so it may be used in the distortion calculation. However, another technique may alternatively be applied.

At a time t=<NUM> (after time t=<NUM>), the distorted bit <NUM> may have been received by the channel <NUM> and DFE calculations thereon may have begun while a second distorted bit n+<NUM> is received by the channel <NUM>, such that enough time may have passed to allow for the n1 bit to be known to the deserializer <NUM> (e.g., stored therein), but the n-<NUM> corrected bit may not yet have been applied to aid in the correction determination of the value of the distorted bit <NUM>. At a third time t=<NUM> (after time t=<NUM>), a third distorted bit n+<NUM> may be received at the channel <NUM>, however, not enough time may have passed for the distorted bit <NUM> to become the corrected bit <NUM> and to be received in the deserializer <NUM> as information to correct the distortion of the second distorted bit <NUM>. Thus, as with the distorted bit <NUM> received at t=<NUM>, the distortion calculation must wait until the corrected bit <NUM> is received in the deserializer <NUM> and transmitted for distortion correction of the second distorted bit n+<NUM>. There may exist a more time efficient solution than waiting for correction of the distorted bits <NUM>, n+<NUM>, and n+<NUM>, etc. without performing any additional processes during the waiting time.

Indeed, it may be desired to compensate for limited transmission bandwidth at the DQ receiver <NUM>. The solution may lie in adding duplicates of the equalizers to allow for rapid computing of distortion correction values. In some embodiments, to increase bandwidth at the DQ receiver <NUM>, duplicate equalizers (e.g., at least two of the DFE <NUM> utilizing the push-pull summer <NUM> in place of summer circuit <NUM>) may be utilized. One embodiment implementing duplicate equalizers is illustrated in <FIG>, with distortion correction circuit <NUM> utilizing DFE <NUM>, DFE <NUM>, DFE <NUM>, and DFE <NUM> (e.g., as equalizers that may allow for rapid computing of distortion correction values that each operate with the push-pull summer <NUM> in place of summer circuit <NUM> of <FIG>). While duplication of four equalizers are illustrated to compensate for transmission bandwidth limitations, it should be appreciated that two, three, five or more equalizers may be implemented in a manner similar to that described herein with respect to the four equalizers illustrated in <FIG>.

As illustrated, the distortion correction circuit <NUM> may be capable of processing four data bits each at a four bit distortion correction level via the DFE <NUM>, DFE <NUM>, DFE <NUM>, and DFE <NUM>, which are similar to the DFE <NUM> described in <FIG> with the push-pull summer <NUM>, <NUM>, <NUM>, and <NUM> used respectively in place of summer circuit <NUM>, as described above with respect to <FIG>. In this manner, the summer circuits <NUM>, <NUM>, <NUM>, and <NUM> of <FIG> may operate in the manner described above with respect to the push-pull summation circuit of <FIG>.

To compensate for limited transmission bandwidth, a method of rolling distorted bits of a received bit stream between the DFE <NUM>, DFE <NUM>, DFE <NUM>, and DFE <NUM> may be followed as a method of alleviating a backup of distorted bits resulting from limited transmission bandwidth. In this way, as the distorted bit <NUM> of a received bit stream is being processed in the DFE <NUM> in a first iteration of distortion correction, a second distorted bit <NUM> may be received in the DFE <NUM> to start a second iteration of distortion correction. This allows the second iteration of distortion correction to occur while the first iteration of distortion correction is completing. Likewise, as the second distorted bit <NUM> of the received bit stream is being processed in the DFE <NUM> in a second iteration of distortion correction (which may coincide with the first distorted bit <NUM> being processed in the DFE <NUM> in a first iteration of distortion correction), a third distorted bit <NUM> may be received in the DFE <NUM> to start a third iteration of distortion correction. Similarly, as the third distorted bit <NUM> of the received bit stream is being processed in the DFE <NUM> in a third iteration of distortion correction (which may coincide with the second distorted bit <NUM> being processed in the DFE <NUM> in a second iteration of distortion correction or may coincide with the second distorted bit <NUM> being processed in the DFE <NUM> in a second iteration of distortion correction and the distorted bit <NUM> being processed in the DFE <NUM> in a first iteration of distortion correction), a fourth distorted bit <NUM> may be received in the DFE <NUM> to start a fourth iteration of distortion correction.

In some embodiments, the first iteration of distortion correction may be completed before a fifth distorted bit is received via the channel <NUM>, which allows the fifth distorted bit to be rolled back to the DFE <NUM> for a fifth of distortion correction. Likewise, the second iteration of distortion correction may be completed before a sixth distorted bit is received via the channel <NUM>, which allows the sixth distorted bit to be rolled back to the DFE <NUM> for a sixth distortion correction, and so forth. In this manner, the DFE <NUM>, DFE <NUM>, DFE <NUM>, and DFE <NUM> may be utilized in conjunction with a rolling DFE correction technique. That is, the distorted bit <NUM> of a bit stream received from channel <NUM> may be received by the DFE <NUM>, a second distorted bit <NUM> of the bit stream may be received by the DFE <NUM>, a third distorted bit <NUM> of the bit stream may be received by the DFE <NUM>, a fourth distorted bit <NUM> of the bit stream may be received by the DFE <NUM>, and a fifth distorted bit may be rolled back to be received by the DFE <NUM> once the first iteration of the distortion correction is complete.

To elaborate further, the DFE <NUM> may receive the distorted bit <NUM> and the voltage correction signal <NUM> (for example, without having been or having been amplified by amplifier <NUM>) and may process the distorted bit <NUM> using the method described above with respect to the distortion correction circuit <NUM> of <FIG> having the push-pull summer <NUM>, using the previous bit or weighted tap data transmitted along the paths <NUM>, <NUM>, <NUM>, and <NUM> (e.g., from the n-<NUM> bit, n-<NUM> bit, the n-<NUM> bit, and the n-<NUM> bit inputs) to calculate the values applied via the push-pull summer <NUM>. It may be important to note that the previous bits may be stored for transmission along the paths <NUM>, <NUM>, <NUM>, and <NUM> in any order as long as during the distortion correction, the proper previous bit order is observed (e.g., n-<NUM> bit as the most significant bit and the n-<NUM> bit as the least significant bit). Once generated, the corrected bit <NUM> of the data latch <NUM> may be transmitted on the rising edge of the DQS signal <NUM> to the deserializer <NUM> to update, for example, the n-<NUM> bit location of the deserializer <NUM>.

Additionally, as illustrated, the inputs used for the final decision of the corrected bit <NUM> for the DFE <NUM> may be different from the inputs for the DFE <NUM>. DFE <NUM> may receive a second distorted bit <NUM> and may processing it after the distorted bit <NUM> is received (e.g., while distorted bit <NUM> is having its distortion corrected in the DFE <NUM>). The method described above with respect to the distortion correction circuit <NUM> having the pushpull summer <NUM>, using the previous bit or weighted tap data transmitted along the paths <NUM>, <NUM>, <NUM>, and <NUM> (e.g., from the n-<NUM> bit, n-<NUM> bit, the n-<NUM> bit, and the n-<NUM> bit inputs) to calculate the values applied via the push-pull summer <NUM> may be used in processing of the second distorted bit <NUM>. However, as illustrated, the previous bit or weighted tap data transmitted along the paths <NUM>, <NUM>, <NUM>, and <NUM> may be shifted with respect to the inputs to the DFE <NUM> to take into account that the distorted bit <NUM> corrected into corrected bit <NUM> by the DFE <NUM> becomes the n-<NUM> bit value for the DFE <NUM>. Once generated, the corrected bit <NUM> of the data latch <NUM> may be transmitted on the rising edge of the DQS signal <NUM> to the deserializer <NUM> to update, for example, the n-<NUM> bit location of the deserializer <NUM> (e.g., moving the corrected bit <NUM> from the DFE <NUM> to the n-<NUM> bit location).

Likewise, the inputs used for the final decision of the corrected bit <NUM> for the DFE <NUM> may be different from the inputs for the DFE <NUM> and DFE <NUM>. DFE <NUM> may receive a third distorted bit <NUM> and may processing it after the distorted bits <NUM> and <NUM> are received (e.g., while distorted bits <NUM> and <NUM> are having their distortion corrected in the DFE <NUM> and DFE <NUM>, respectively). The method described above with respect to the distortion correction circuit <NUM> having the push-pull summer <NUM>, using the previous bit or weighted tap data transmitted along the paths <NUM>, <NUM>, <NUM>, and <NUM> (e.g., from the n-<NUM> bit, n-<NUM> bit, the n-<NUM> bit, and the n-<NUM> bit inputs) to calculate the values applied via the push-pull summer <NUM> may be used in processing of the third distorted bit <NUM>. However, as illustrated, the previous bit or weighted tap data transmitted along the paths <NUM>, <NUM>, <NUM>, and <NUM> may be shifted with respect to the inputs to the DFE <NUM> and the DFE <NUM> to take into account that the distorted bits <NUM> and <NUM> corrected into respective corrected bits <NUM> by the DFE <NUM> and DFE <NUM> become the n-<NUM> bit value and the n-<NUM> bit value for the DFE <NUM>. Once generated, the corrected bit <NUM> of the data latch <NUM> may be transmitted on the rising edge of the DQS signal <NUM> to the deserializer <NUM> to update, for example, the n-<NUM> bit location of the deserializer <NUM> (e.g., moving the corrected bit <NUM> from the DFE <NUM> to the n-<NUM> bit location and moving the corrected bit <NUM> from the DFE <NUM> to the n-<NUM> bit location).

Similarly, the inputs used for the final decision of the corrected bit <NUM> for the DFE <NUM> may be different from the inputs for the DFE <NUM>, the DFE <NUM>, and the DFE <NUM>. DFE <NUM> may receive a fourth distorted bit <NUM> and may processing it after the distorted bits <NUM>, <NUM>, and <NUM> are received (e.g., while distorted bits <NUM>, <NUM>, and <NUM> are having their distortion corrected in the DFE <NUM>, <NUM>, and <NUM>, respectively). The method described above with respect to the distortion correction circuit <NUM> having the push-pull summer <NUM>, using the previous bit or weighted tap data transmitted along the paths <NUM>, <NUM>, <NUM>, and <NUM> (e.g., from the n-<NUM> bit, n-<NUM> bit, the n-<NUM> bit, and the n-<NUM> bit inputs) to calculate the values applied via the push-pull summer <NUM> may be used in processing of the fourth distorted bit <NUM>. However, as illustrated, the previous bit or weighted tap data transmitted along the paths <NUM>, <NUM>, <NUM>, and <NUM> may be shifted with respect to the inputs to the DFE <NUM>, <NUM>, and <NUM> to take into account that the distorted bits <NUM>, <NUM>, and <NUM> corrected into respective corrected bits <NUM> by the DFE <NUM>, <NUM>, and <NUM> become the n-<NUM> bit value, the n-<NUM> bit value, and the n-<NUM> bit value for the DFE <NUM>. Once generated, the corrected bit <NUM> of the data latch <NUM> may be transmitted on the rising edge of the DQS signal <NUM> to the deserializer <NUM> to update, for example, the n-<NUM> bit location of the deserializer <NUM> (e.g., moving the corrected bit <NUM> from the DFE <NUM> to the n-<NUM> bit location and moving the corrected bit <NUM> from the DFE <NUM> to the n-<NUM> bit location, and moving the corrected bit <NUM> from the DFE <NUM> to the n-<NUM> bit location).

The outputs <NUM> from the data latches <NUM>, <NUM>, <NUM>, and <NUM> from the DFE <NUM>, <NUM>, <NUM>, and <NUM> may be sent to the deserializer <NUM> at the conclusion of each final decision on the corrected bit <NUM>. As noted above, in the deserializer <NUM>, the n-<NUM> bit, the n-<NUM> bit, the n-<NUM> bit, and the n-<NUM> bit may be used to update the data stored in the deserializer <NUM> for transmission along the paths <NUM>-<NUM> in accordance with the corrected bit <NUM> data (e.g., the corrected bit <NUM> from the each of the DFE <NUM>, <NUM>, <NUM>, and <NUM> shifted as a new corrected bit <NUM> is received). It may be noted that this rolling method of DFE correction may allow for greater throughput of the bit stream received while still allowing for distortion correction of the received bits of the bit stream. While the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure as defined by the following appended claims.

Claim 1:
A device, comprising:
a receiver (<NUM>) comprising:
a first input configured to receive a reference signal (<NUM>);
a second input configured to receive a modified reference signal (<NUM>) comprising a combination of a correction factor added to the reference signal (<NUM>); and
a third input configured to receive a feedback signal (<NUM>), wherein the receiver is configured to generate a set of output signals (<NUM>, <NUM>) based on the reference signal, the modified reference signal, and the feedback signal, wherein the set of output signals comprises a first output signal (<NUM>) and a second output signal (<NUM>), wherein the first output signal (<NUM>) and the second output signal (<NUM>) represent modified values of the reference signal (<NUM>) and the modified reference signal (<NUM>), respectively; wherein the receiver (<NUM>) is configured to modify the reference signal (<NUM>) and the modified reference signal (<NUM>) under the control of the feedback signal (<NUM>);
a differential amplifier (<NUM>) comprising:
a fourth input configured to receive the first output signal (<NUM>) of the set of output signals from the receiver;
a fifth input configured to receive the second output signal (<NUM>) of the set of output signals from the receiver, wherein the differential amplifier is configured to generate the feedback signal based on the first output signal and the second output signal by determining a difference between the first and second output signals and multiplying the difference by a gain to obtain the feedback signal; and
a first output coupled to:
the third input of the receiver; and
an adjustment circuit (<NUM>) of a decision feedback equalizer (<NUM>) configured to transmit adjustment signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream,
wherein the first output is configured to transmit the feedback signal to the third input and the adjustment circuit as a processes voltages and temperatures, PVT, tolerant bias level to suitably adjust the adjustment circuit of the decision feedback equalizer.