Patent Description:
A master or central module communicates with the satellite or slave modules using a communication interface on the automobile's Controller Area Network (CAN) bus. The central module addresses each satellite module for data related to gaining entry access to the car so that the central module can determine whether to grant entry access to the car or allow the driver to start driving the car after gaining access. In order to triangulate the signals received from the satellite modules and determine the location of the key fob, the central module must know the location of each satellite module sending data to it. The central module is able to determine which satellite module it is receiving data from based on the bus address of the satellite module sending the data because the central module knows the sequence order of satellite bus address assignment. In this way, the central module correlates the communication bus address to the location of the satellite in the automobile. Rather than having a unique printed circuit board for each satellite module with the bus address hard-wired or hard-coded in, it would be advantageous to system designers to have a single hardware board design with a single software program for all the satellite modules. This avoids the added inventory cost and manufacturing complexity of multiple SKUs or part numbers and allows any of the satellite modules to be installed in any of the locations. Therefore, it is not possible to assign the bus address to the satellite module prior to installation. Since the hardware and software of the satellite nodes are all identical and unaddressed at the time of installation into the automobile, a scheme is required for the central module to assign a unique CAN bus address to each satellite module after the modules are installed in the automobile. This process of assigning a unique address to each satellite module is referred to as auto addressing.

Presently, assignment of network bus addresses to satellite modules in automobiles is accomplished using a dedicated Local Interconnect Network (LIN) bus with the satellites daisy-chained on the bus. A second network interface is then used for communication of access-related data. The central module sends an address to the first satellite over the LIN bus, and then the first satellite will send an address received from the central module to the second satellite using the LIN bus. This process continues until all the satellite modules have been addressed. This scheme requires two LIN physical layers (PHYs) per satellite module as well as one for the master or central module. On the satellite modules, one LIN PHY is for receiving data and one for transmitting data. The LIN PHYs are only used for the auto-addressing operation, not for standard data communications which is done on the CAN bus or a different network bus. A typical automobile might have <NUM> satellite modules. This means that <NUM> LIN PHYs must be added to the system just for auto addressing, increasing system cost and complexity. A need arises for a simpler and more cost effective method for assigning network bus addresses to satellite modules in automobiles without the need for LIN PHYs dedicated to auto addressing modules on the network bus. <CIT> discloses an automatic address assignment for communication bus. <CIT> discloses identifying and configuring multiple smart devices on a can bus.

This Summary is provided to introduce the disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided.

Disclosed embodiments describe a scheme for auto addressing satellite modules on a communication bus, such as CAN, without the need for a separate bus, such as LIN, with transceivers in each module dedicated to the auto addressing function. In one disclosed embodiment, a nominal <NUM> volt battery level signal is daisy-chained to the satellite modules in order to sequentially wake each of the satellite module alerting it to listen to the CAN bus to receive its address assignment. Once addressed, the newly addressed satellite module then sends an acknowledgment signal back on the communication bus to the central module and sends a <NUM> volt battery voltage level wake signal to the next satellite module in the sequence.

Disclosed embodiments include using an n-channel MOSFET as a low side switch to deliver the auto address wake signal, which is preferably a pulse-width-modulated signal for improved noise immunity. Disclosed embodiments also include a voltage divider circuit to step down the auto address wake signal from battery voltage level to levels acceptable for a microcontroller input. This circuit also includes current limiting resistors for short circuit and battery load dump surge protection.

Additionally, disclosed embodiments include a mechanism for detecting shorts and open circuits in the satellite modules or associated wiring by alerting when a satellite module fails to report it has received its auto address wake signal. The central module will know the location of the satellite module indicating a fault because the address the central module is assigning will always be assigned to the satellite module at a given known location.

Details of one or more implementations of the present disclosure are set forth in the accompanying drawings and the description below. The figures are not drawn to scale and they are provided merely to illustrate the disclosure. Specific details, relationships, and methods are set forth to provide an understanding of the disclosure. Other features and advantages may be apparent from the description and drawings, and from the claims.

CAN is a specialized internal communications network that interconnects components inside a vehicle serial bus standard designed to allow microcontrollers and devices to communicate with each other in applications without a host computer. Two or more nodes are required on the CAN network to communicate. The nodes are connected to each other through a two-wire serial bus. Each node requires a central processing unit to interpret the messages it receives and what messages it wants to transmit, a CAN controller which is often integrated into the processing unit, and a CAN transceiver. Each node is able to send and receive messages, but not simultaneously. A message or frame consists primarily of the identifier (address) and up to eight data bytes. A cyclic redundancy check (CRC), acknowledge slot (ACK) and other overhead are also part of the message.

The CAN bus was originally designed for automobiles, but is used in numerous other contexts as well, such as aviation and navigation, elevators and escalators, industrial and building automation and medical equipment. The present invention is applicable to all CAN bus applications involving multiple slave or satellite nodes. Additionally, this invention also may be used with any serial communication bus system having a central or master unit and one or more slave or satellite units, such as LIN bus.

<FIG> illustrates a system diagram of a communication bus auto-addressing scheme. The system includes a central module <NUM> that serves as the master on the CAN bus <NUM>. Satellite modules, which are located at various known positions throughout the automobile, are configured as slaves on the communication bus.

<FIG> shows a system with a central module and six satellite modules. However, there could be more or less than six satellite modules depending upon system requirements. The satellite modules are daisy-chained together via input and output signals wherein the output signal of one satellite module is the input signal for the next satellite module. They also share a common bus data connection along with the central module, which could be a CAN bus, LIN bus, or another type of serial communication bus. For purposes of illustration, an embodiment with CAN bus will be shown here.

The first satellite module is shown as <NUM> in the figure and is connected to the central module <NUM> along with each of the other satellite modules via the communication bus <NUM>. The first satellite module <NUM> is also connected to the central module <NUM> and to the second satellite module <NUM> via input and output lines. The second satellite module <NUM> is connected to the first satellite module <NUM> and to the third satellite module <NUM> via input and output lines. Satellite modules <NUM>, <NUM>, and <NUM> are denoted in the figure as <NUM>, <NUM>, and <NUM>, respectively. Data communication on the communication bus <NUM> is bidirectional meaning that each module can send to and receive from the other modules on the bus. Each node is able to send and receive messages, but not simultaneously. There is an arbitration method in the CAN bus standard to handle collisions on the bus. To enable communication, each node on the bus must be assigned an address and will ignore bus communication unless it is sent to its address.

The bus addresses on the communication bus are assigned to each satellite module sequentially and in a known order. The central module is programmed to know the location where each module is installed. The satellite modules are daisy-chained in a preset known order, so that each time a bus address is assigned to a satellite module, the location of the satellite module is known by where it is in the daisy-chain order. In this way, a particular bus address will always correspond to a known satellite module whose location is known. Therefore, the satellite module bus address can always be used to correlate to the exact location of the satellite module. This is necessary for being able to triangulate the signals from multiple satellite modules to determine the approximate location of a PEPS key holder. This is also useful for determining the location of faulty wiring or a faulty satellite module in the event where a particular satellite module with a known bus address fails to acknowledge to the central module that it has been successfully addressed.

<FIG> shows a state diagram for an example embodiment of an auto addressing scheme <NUM> for satellite modules according to an aspect of the present disclosure. The auto addressing scheme <NUM> begins with power up <NUM>. At power up <NUM>, each of the satellite modules is in the default address state <NUM> during which its communication bus response <NUM> to data on the bus is to ignore all messages and data on the communication bus. Each satellite module <NUM>-<NUM> ignores all data on the communication bus because it does not yet have an address assigned to it, so the satellite modules cannot determine if the data on the bus is intended for it. Therefore, it ignores the data until it is later awakened by a signal that a valid address for that module is on the bus ready to be received.

Immediately following power up <NUM>, the central module <NUM> from <FIG> sends a signal <NUM> using its low side switch to the first satellite module <NUM> indicating that the central module is ready to assign a communication bus address to it. The signal <NUM> could be in the form of a single pulse, a series of pulses, a pulse-width-modulated signal, or any other series of patterned pulses which a microcontroller in the satellite module being addressed compares to the expected signal and validates. Since this signal <NUM> is not sent via the communication bus, but is instead a separate signal sent only to the first satellite module <NUM>, the other satellite modules <NUM>-<NUM> do not receive signal <NUM> from the central module <NUM>.

Upon receiving the signal <NUM> that the central module is ready to send the first address, the satellite module <NUM> enters the address assignment state <NUM> and waits for the central module <NUM> to send an address. The bus response <NUM> of satellite module <NUM> is now to ignore all messages on the communication bus except for the address assignment message. At this time, the remaining satellite modules <NUM>-<NUM> remain in the default address state <NUM> and their communication bus response <NUM> remains to ignore all messages and data on the communication bus.

The central module <NUM> then sends an address assignment message for satellite module <NUM> via the communication bus. Since satellite module <NUM> is the only module on the bus waiting to receive an address assignment, it assigns the received address to itself while the other satellite modules continue to ignore the message on the bus.

After assigning itself the received address, satellite module <NUM> exits the address assignment state <NUM> and sends an acknowledgment message back to the central module via the communication bus notifying the central module that it has received its address. The satellite module <NUM> is now in the addressed state <NUM> and its communication bus response <NUM> to data on the bus is to respond to all communication bus messages where the bus address matches its assigned address. A similar process then begins for addressing the second satellite module.

Next, satellite module <NUM> then uses its low side switch to send a signal <NUM> to the next satellite module <NUM> indicating that a communication bus address is ready to be assigned to satellite module <NUM>. Satellite module <NUM> then enters the address assignment state <NUM> and waits for the central module <NUM> to send an address. The bus response <NUM> of satellite module <NUM> is now to ignore all messages on the communication bus except for the address assignment message. At this point, satellite modules <NUM>-<NUM> remain in the default address state <NUM> and their communication bus response <NUM> continues to be ignore all messages and data on the communication bus, and satellite module <NUM> will only respond to messages that have its assigned address.

The central module <NUM> then sends an address assignment message for satellite module <NUM> via the communication bus. Satellite module <NUM> has been addressed and can see that this message is not being sent to its address, so it ignores the message. Satellite modules <NUM>-<NUM> are still in the default address state, so they continue to ignore all data on the communication bus. Since satellite module <NUM> is the only module on the bus waiting to receive an address assignment, it assigns the address on the communication bus to itself while each of the other satellite modules ignores the data on the bus.

After assigning itself the address, satellite module <NUM> exits the address assignment state <NUM> and sends an acknowledgment message back to the central module via the communication bus notifying the central module that it has received its address. The satellite module <NUM> is now in the addressed state <NUM> and its communication bus response <NUM> to data on the bus is to respond to all communication bus messages where the address matches its assigned address. The same process is repeated until all satellite modules have their address assigned.

Once the last satellite module has been addressed, there will be no satellite module to receive the address assignment signal, and the process will end. Though <FIG> shows a system with six satellite modules, the process of <FIG> can be used with any number of satellite modules two or greater.

There may be an instance <NUM> where a satellite module receives an address assignment message and already has a valid address assignment. This can occur in situations where for instance, that particular satellite module has previously been in the system and was already assigned a bus address. The bus address may have been stored in static memory, allowing the satellite module to retain its address. If this occurs, that satellite module will send an acknowledgment message back to the central module indicating that it has a valid bus address and will send an address assignment message to the next satellite module in the chain.

<FIG> shows an example embodiment of a circuit diagram illustrating the interconnection between the central module and the satellite modules. For the sake of simplicity, only two satellite modules are shown in the figure, but there could also be any greater number of satellite modules in the system.

In accordance with various embodiments, a central module <NUM> is shown coupled to a first satellite module <NUM> by general purpose input/output (GPIO), and satellite module <NUM> is also coupled to satellite module <NUM> by GPIO. Additionally, central unit <NUM>, satellite module <NUM> and satellite module <NUM> are interconnected via a common bus, which is shown as a CAN bus, but could also be LIN bus or another type of serial communication bus.

The central module <NUM> includes a battery voltage input <NUM> coupled to the anode of diode <NUM> which protects the system against back surges on the battery line and the reversal of battery polarity. The cathode of diode <NUM> is coupled to the input of a power converter <NUM>, a communications physical layer (Comm PHY) <NUM>, and to the drain of an n-channel metal oxide semiconductor field effect transistor (MOSFET) <NUM>, which is the low side switch for the central module <NUM>. The coupling between the cathode of diode <NUM> and the drain of low side switch <NUM> could be direct or through a resistor. A n-channel MOSFET is only one example of a switch that can be used for the low side switch. Other types of switches could be used in other embodiments.

The Comm PHY <NUM> is coupled to MCU <NUM> which has a GPIO <NUM> that is coupled to the gate of low side switch <NUM>. The source of low side switch <NUM> is coupled to ground. The Comm PHY <NUM> is also coupled to microcontroller unit (MCU) <NUM> and to the Comm PHY <NUM> of the first satellite module <NUM> through the communications bus (Comm Bus) <NUM> and communicates with each of them bidirectionally. The drain of the low side switch <NUM> of the central module <NUM> is resistively coupled to the gate of the low side switch <NUM> of the first satellite module <NUM>.

The first satellite module <NUM> includes a battery voltage input <NUM> coupled to the anode of diode <NUM> which protects the module against back surges on the battery line and the reversal of battery polarity. The cathode of diode <NUM> is coupled to a communications physical layer (Comm PHY) <NUM> which is coupled to and provides the input for a power converter <NUM> which provides power for MCU <NUM>. In an alternative embodiment, the power converter <NUM> may receive an input from the cathode of diode <NUM>.

The Comm PHY <NUM> is coupled to MCU <NUM> which has a GPIO <NUM> that is coupled to the gate of low side switch <NUM>. The source of low side switch <NUM> is coupled to ground and the drain is resistively coupled to the cathode of diode <NUM>. The Comm PHY <NUM> is also coupled to MCU <NUM> and to the Comm PHY <NUM> of the second satellite module <NUM> through the Comm Bus <NUM> and communicates with each of them bidirectionally. The drain of low side switch <NUM> of the first satellite module <NUM> is resistively coupled to the gate of low side switch <NUM> of the second satellite module <NUM>.

The second satellite module <NUM> is an identical design to the first satellite module <NUM> with Comm PHY <NUM>, MCU <NUM>, power converter <NUM>, low side switch <NUM> and diode <NUM>. For simplicity, only two satellite modules are shown in the figure, but there may be more than two satellite modules in the system which would also be of the identical design and would be daisy-chained in like manner with the drain of each low side switch resistively coupled to the gate of the low side switch of the next satellite module.

At power up, satellite modules <NUM> and <NUM> are in the default address state <NUM> and will ignore all messages and data on the communication bus because they do not yet have an address assigned to them. Since the satellite module cannot determine if the data on the bus is intended for it, it ignores all data. When power is applied to the central module at the battery voltage node <NUM>, the MCU <NUM> and Comm PHY <NUM> go through their initiation routines.

Auto addressing of the satellite modules begins with MCU <NUM> outputting a pulse or series of pulses through a general purpose output node <NUM> which is coupled to the gate of low side switch <NUM>. In one embodiment, the series of pulses is a pulse-width-modulated (PWM) pattern for improved noise immunity. The drain of the low side switch <NUM> receives the battery supply voltage input from the cathode of diode <NUM> and the source is coupled to ground. With no input to the gate of low side switch <NUM>, the voltage at <NUM> is near the upper rail, and when the voltage at the gate of low side switch <NUM> is high, the voltage at <NUM> is near ground.

A PWM pattern is sent from MCU <NUM> causing the output <NUM> of low side switch <NUM> to send a PWM pattern to satellite <NUM>, where a voltage divider made up of resistors <NUM> and <NUM> step the battery voltage down to a level tolerable to MCU <NUM> which receives the pattern at its GPIO. Once MCU <NUM> validates that it has received the correct pattern, satellite module <NUM> enters the address assignment state <NUM> and begins listening to the communication bus through its Comm PHY <NUM> which is receiving messages sent from the central module <NUM> through its Comm PHY <NUM> on the communication bus <NUM>.

The central module <NUM> is constantly sending data over the communication bus <NUM> to a default ID with the new address for the satellite node. Once satellite module <NUM> has received the address, it enters the addressed state <NUM> and sends an acknowledge message back to the central module MCU <NUM> via the communication bus <NUM> causing the central module to increment to the next address in its predetermined pattern. Satellite module <NUM> then continues the process by sending a signal to satellite module <NUM> to begin its auto addressing.

A PWM pattern is sent from MCU <NUM> causing the output <NUM> of low side switch <NUM> to send a PWM pattern to satellite <NUM>, where a voltage divider made up of resistors <NUM> and <NUM> step the battery voltage down to a level tolerable to MCU <NUM> which receives the pattern. Once MCU <NUM> validates that it has received the correct pattern, satellite module <NUM> enters the address assignment state <NUM> and begins listening to the communication bus through its Comm PHY <NUM> which is receiving messages sent from the central module <NUM> through its Comm PHY <NUM> on the communication bus <NUM>.

The central module <NUM> is constantly sending data over the communication bus <NUM> to a default ID with the new address for the satellite module. Once satellite module <NUM> has received the address, it enters the addressed state <NUM> and sends an acknowledge message back to the central module MCU <NUM> via the communication bus <NUM>. If there are more satellite modules to be addressed, then the process will repeat with low side switch <NUM> sending a PWM pattern to the next satellite module and the central module sending the next address to the default ID via the communication bus. This process will continue until all satellite modules have been addressed.

An added benefit of this auto addressing scheme is that it allows shorts and ground faults in satellite modules to be detected and be reported by the central module as the auto addressing process occurs. Occurrences of opens and shorts are particularly prevalent in automobiles where an increased rate of wiring harness issues may occur. If there is a short to ground or to battery on the auto-addressing line, the central module will never receive the acknowledge message from the satellite module that is being addressed. The central module will be able to report the approximate area where the fault occurred because it knows which satellite module failed to send a proper acknowledgment signal, and it further knows the location of the faulty satellite module because the address the central module is assigning will always be assigned to the satellite module in a specific known location of the vehicle. This report can be sent, for instance, to external circuitry or to a central processing unit to determine what action to take.

In the case where a satellite module needs to be replaced, the auto addressing scheme can be run to address the replaced module. The only difference in this situation is that the majority of satellite modules will already have a communications bus address. If a satellite module already has an address when the auto address process is run, it will send an acknowledge signal back to the central module and the process continue. In this situation where the satellite module that already has an address receives the auto address signal, <NUM> or <NUM> in <FIG>, the satellite module will just send the acknowledge message back to the central module via the communications bus and put out its own auto address signal to trigger the next satellite module to enter the address assignment state.

A potential issue that should be addressed is the ability of the circuit to survive shorts to power and ground. Automobiles inherently have an increased rate of issues with shorts due to increased failures in wiring harnesses. This problem is handled in existing solutions by the LIN bus because ground and power fault protection is built into the LIN specification as a requirement to be LIN <NUM> compliant. However, if CAN bus or another type of serial bus is used for communication, there is a need to ensure survivability of the circuit if a short to power or ground occurs.

This can be handled by a current limiting protection circuit incorporated as part of a voltage divider circuit to step down the voltage of the battery level auto-addressing signal to a voltage that is tolerable to an MCU input. A typical input voltage for an MCU could be <NUM> V. However, other implementations could provide for an input to the MCU at 5V or <NUM>. The design must take into account the wide range of automobile battery operating voltages from <NUM>-<NUM> V and potential load dump conditions of up to 40V.

<FIG> shows a schematic of the voltage divider circuit. Resistor <NUM> is coupled to the battery supply node, to resistor <NUM> and to the drain of low side switch <NUM> of a satellite module that will be sending an auto address signal. The other side of resistor <NUM> is coupled to resistor <NUM> on the next satellite module that will be receiving the auto address signal. The other side of <NUM> is coupled to R420 and R418.

The resistor values of <NUM>, <NUM> and <NUM> should be large enough to reduce the current delivered to the satellite MCU general purpose input in a worst case load dump condition to within its maximum rated limit. The ratios of the resistors should be chosen to limit the maximum voltage seen at the satellite MCU general purpose input to within its rated limit. The values and ratings of resistors <NUM>, <NUM> and <NUM> should be chosen to handle the current and power present at worst case load dump condition. Resistor <NUM> can be a much smaller value than resistor <NUM> and resistor <NUM> if desired to simplify the voltage divider calculation. Resistor <NUM> can be approximately the same value as resistor <NUM>.

In one embodiment, typical values chosen for resistor <NUM> and resistor <NUM> could <NUM> Kohm each, while typical values of resistor <NUM> and resistor <NUM> could be chosen as <NUM> Mohm and <NUM> Kohm, respectively. With these values, the voltage at the satellite MCU general purpose input would be substantially equal to <NUM> V when the battery voltage is <NUM> V, and would be substantially equal to <NUM> V when the battery voltage is at <NUM> V.

In the case of a short to battery, resistor <NUM> will be required to protect low side switch <NUM> if it is turned on. If this occurs, current will flow through <NUM>, then from drain to source of low side switch <NUM> to ground. Since the on resistance of <NUM> will be very low, the short circuit current flow will be the battery voltage divided by the value of resistor <NUM>.

There should be little risk for damaging circuits if a short to ground occurs provided that the resistor values are chosen properly. If low side switch <NUM> turns on, resistor <NUM> will protect <NUM> by limiting the current that flows through <NUM> to within its rated limits.

The terms "substantially the same," "substantially equal," and "approximately the same" purport to describe a quantitative relationship between two objects. This quantitative relationship may prefer the two objects to be equal by design but with the anticipation that a certain amount of variations can be introduced by the fabrication process. In one aspect, a first resistor may have a first resistance that is substantially equal to a second resistance of the second resistor where the first and second resistors are purported to have the same resistance, yet the fabrication process introduces slight variations between the first resistance and the second resistance. Thus, the first resistance can be substantially equal to the second resistance even when the fabricated first and second resistors demonstrate slight difference in resistance. This slight difference may be within <NUM>% of the design target. In another aspect, a first resistor may have a first resistance that is substantially equal to a second resistance of a second resistor where the process variations are known a priori, such that the first resistance and the second resistance can be preset at slightly different values to account for the known process variations. Thus, the first resistance can be substantially equal to the second resistance even when the design values of the first and second resistance are preset to include a slight difference to account for the known process variations. This slight difference may be within <NUM>% of the design target.

Claim 1:
An apparatus for auto addressing nodes on a communication bus comprising:
a central module (<NUM>) including:
a central power converter (<NUM>);
a central module microcontroller unit, MCU, (<NUM>) having a general purpose input and output, GPIO, a central module communication bus physical layer, PHY, (<NUM>) coupled to a communication bus (<NUM>) and to the central module MCU (<NUM>), and a central module low side power switch (<NUM>) whose input is coupled to the GPIO of the central module MCU (<NUM>), the apparatus further comprising:
a first satellite module (<NUM>) comprised of a first power converter (<NUM>), a first satellite MCU (<NUM>) having a GPIO with an input (<NUM>) resistively coupled to the output of the central module low side power switch (<NUM>), a first satellite communication bus PHY (<NUM>) coupled to the communication bus (<NUM>) and to the first satellite MCU (<NUM>), and a first satellite low side power switch (<NUM>) whose input is coupled to the GPIO of the first satellite MCU (<NUM>),
wherein the central module MCU (<NUM>) is configured to, by means of the central module low side power switch (<NUM>), send a first wake pulse to the input (<NUM>) of the first satellite module (<NUM>), and after sending the first wake pulse, configured to send a first address on the communication bus (<NUM>) to the first satellite module (<NUM>), and configured to assign the first address to the first satellite module (<NUM>); and
a second satellite module (<NUM>) comprised of a second power converter (<NUM>), a second satellite MCU (<NUM>) having a GPIO with an input (<NUM>) resistively coupled to the output of the first satellite low side power switch (<NUM>), a second satellite communication bus PHY (<NUM>) coupled to the communication bus (<NUM>) and to the second satellite MCU (<NUM>), wherein the first satellite MCU (<NUM>) is configured to, by means of the first satellite low side power switch (<NUM>), send a second wake pulse to the input (<NUM>) of the second satellite module (<NUM>), and after sending the second wake pulse, the central module MCU (<NUM>) is configured to send a second address on the communication bus (<NUM>) to the second satellite module (<NUM>), and assign the second address to the second satellite module (<NUM>).