Patent Description:
Energy consumption in most digital integrated circuits is highly dependent on the supply voltage that powers the integrated circuits and on the frequency of the clock that controls the switching of the integrated circuits. Today's integrated circuits are able to operate over a wide dynamic range of both supply voltage and frequency, which can result in a widely varying range of energy efficiencies. In particular, the best energy efficiencies in digital CMOS silicon may be achieved around the "near-threshold voltage" (NTV) regime with an optimum supply voltage and frequency and a distinct minimum energy point (MEP), where energy efficiencies can be <NUM>-10x better than nominal supply operation. The optimum voltage and MEP can vary widely across workload activity and with process and temperature variations. Non-linear integrated voltage regulator (IVR) efficiencies can further shift MEP and optimum voltage, as the energy consumed by the entire system is taken into account. Finding a truly optimal MEP can make a significant difference in the energy consumed by the system. Current techniques fail to do so in an efficient manner. Techniques for efficiently adapting a supply voltage are known from <NPL>, or from <NPL>.

In various embodiments, a processor is configured with a minimum energy point (MEP) control circuit to determine and track a MEP of the processor and/or its constituent components, including one or more cores or other processing circuits. To enable efficient tracking of MEP over a lifetime of the processor at high speed and low impact, embodiments leverage an efficient sensor-driven energy computation technique to arrive at the MEP. As such, embodiments may determine and track MEP for the processor with high speed and low complexity, in contrast to conventional one point (at a time) sweep-based energy computing methods, which perform many update iterations to processor operating voltage and operating frequency, in an effort to identify an MEP for a given workload.

With embodiments herein, sensor-driven and heuristic techniques provide fast real-time MEP tracking, resulting in simplified relative-computational computations, with reduced overhead. As a result, embodiments may realize better MEP tracking, as the techniques herein enable a determination of an updated MEP point substantially faster as compared to a recursive/expensive search, when operating conditions of a processor change. Stated another way, a conventional (e.g., dynamic voltage frequency scaling (DVFS)) technique to identify a MEP, with multiple voltage and frequency updates, can be replaced in embodiments with intelligent and direct computational hardware to predict MEP and update operation directly to this operating point in a single step, improving performance.

In embodiments, a MEP controller may leverage sensor-driven data and heuristics to quickly compute and relock to a new optimal MEP point, using one or more pre-characterized (and per-die programmable) lookup tables (LUTs). With embodiments, the MEP may be determined in a relative manner as compared to a computationally expensive absolute MEP tracking method to intelligently adjust an optimum MEP.

Although the following embodiments are described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or processors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to any particular type of computer systems. That is, disclosed embodiments can be used in many different system types, ranging from server computers (e.g., tower, rack, blade, micro-server and so forth), communications systems, storage systems, desktop computers of any configuration, laptop, notebook, and tablet computers (including <NUM>:<NUM> tablets, phablets and so forth), and may be also used in other devices, such as handheld devices, systems on chip (SoCs), and embedded applications. Some examples of handheld devices include cellular phones such as smartphones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may typically include a microcontroller, a digital signal processor (DSP), network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, wearable devices, or any other system that can perform the functions and operations taught below. More so, embodiments may be implemented in mobile terminals having standard voice functionality such as mobile phones, smartphones and phablets, and/or in non-mobile terminals without a standard wireless voice function communication capability, such as many wearables, tablets, notebooks, desktops, micro-servers, servers and so forth. Moreover, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will become readily apparent in the description below, the embodiments of methods, apparatuses, and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) are vital to a 'green technology' future, such as for power conservation and energy efficiency in products that encompass a large portion of the US economy.

Referring now to <FIG>, shown is a block diagram of a portion of a system in accordance with an embodiment. As shown in <FIG>, system <NUM> may include various components, including a processor <NUM> which as shown is a multicore processor. Processor <NUM> may be coupled to a power supply <NUM> via an external voltage regulator <NUM>, which may perform a first voltage conversion to provide a primary regulated voltage to processor <NUM>.

As seen, processor <NUM> may be a single die processor including multiple cores <NUM>a-<NUM>n. In addition, each core may be associated with an integrated voltage regulator (IVR) <NUM>a-<NUM>n which receives the primary regulated voltage and generates an operating voltage to be provided to one or more agents of the processor associated with the IVR. Accordingly, an IVR implementation may be provided to allow for fine-grained control of voltage and thus power and performance of each individual core. As such, each core can operate at an independent voltage and frequency, enabling great flexibility and affording wide opportunities for balancing power consumption with performance. In some embodiments, the use of multiple IVRs enables the grouping of components into separate power planes, such that power is regulated and supplied by the IVR to only those components in the group. During power management, a given power plane of one IVR may be powered down or off when the processor is placed into a certain low power state, while another power plane of another IVR remains active, or fully powered.

Still referring to <FIG>, additional components may be present within the processor including an input/output interface <NUM>, another interface <NUM>, and an integrated memory controller <NUM>. As seen, each of these components may be powered by another integrated voltage regulator <NUM>x. In one embodiment, interface <NUM> may be enable operation for an Intel®. Quick Path Interconnect (QPI) interconnect, which provides for point-to-point (PtP) links in a cache coherent protocol that includes multiple layers including a physical layer, a link layer and a protocol layer. In turn, interface <NUM> may communicate via a Peripheral Component Interconnect Express (PCIe™) protocol.

Also shown is a power control unit (PCU) <NUM>, which may include hardware, software and/or firmware to perform power management operations with regard to processor <NUM>. As seen, PCU <NUM> provides control information to external voltage regulator <NUM> via a digital interface to cause the voltage regulator to generate the appropriate regulated voltage. PCU <NUM> also provides control information to IVRs <NUM> via another digital interface to control the operating voltage generated (or to cause a corresponding IVR to be disabled in a low power mode). In various embodiments, PCU <NUM> may include a variety of power management logic units to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or management power management source or system software).

Furthermore, while <FIG> shows an implementation in which PCU <NUM> is a separate processing engine (which may be implemented as a microcontroller), understand that in some cases in addition to or instead of a dedicated power controller, each core may include or be associated with a power control agent to more autonomously control power consumption independently. In some cases a hierarchical power management architecture may be provided, with PCU <NUM> in communication with corresponding power management agents associated with each of cores <NUM>.

One power management logic included in PCU <NUM> may be a MEP controller that is configured to readily and efficiently identify a MEP operating point based at least in part on dynamic processor conditions including changes in thermal information and/or activity information. Still further, the MEP controller may determine an initial MEP operating point based at least in part on a sweep of a plurality of operating voltage and operating frequency points and a process variation of the processor. Thereafter, the MEP controller may identify an appropriate update to the MEP operating point based at least in part on one or more of activity tracking information and temperature tracking information, as described herein.

While not shown for ease of illustration, understand that additional components may be present within processor <NUM> such as additional control circuitry, and other components such as internal memories, e.g., one or more levels of a cache memory hierarchy and so forth. Furthermore, while shown in the implementation of <FIG> with an integrated voltage regulator, embodiments are not so limited.

Note that the power management techniques described herein may be independent of and complementary to an operating system (OS)-based power management (OSPM) mechanism. According to one example OSPM technique, a processor can operate at various performance states or levels, so-called P-states, namely from P0 to PN. In general, the P1 performance state may correspond to the highest guaranteed performance state that can be requested by an OS. Embodiments described herein may enable dynamic changes to the guaranteed frequency of the P1 performance state, based on a variety of inputs and processor operating parameters. In addition to this P1 state, the OS can further request a higher performance state, namely a P0 state. This P0 state may thus be an opportunistic or turbo mode state in which, when power and/or thermal budget is available, processor hardware can configure the processor or at least portions thereof to operate at a higher than guaranteed frequency. In many implementations a processor can include multiple so-called bin frequencies above the P1 guaranteed maximum frequency, exceeding to a maximum peak frequency of the particular processor, as fused or otherwise written into the processor during manufacture. In addition, according to one OSPM mechanism, a processor can operate at various power states or levels. With regard to power states, an OSPM mechanism may specify different power consumption states, generally referred to as C-states, C0, C1 to Cn states. When a core is active, it runs at a C0 state, and when the core is idle it may be placed in a core low power state, also called a core non-zero C-state (e.g., C1-C6 states), with each C-state being at a lower power consumption level (such that C6 is a deeper low power state than C1, and so forth).

Understand that many different types of power management techniques may be used individually or in combination in different embodiments. As representative examples, a power controller may control the processor to be power managed by some form of dynamic voltage frequency scaling (DVFS) in which an operating voltage and/or operating frequency of one or more cores or other processor logic may be dynamically controlled to reduce power consumption in certain situations. In an example, DVFS may be performed using Enhanced Intel SpeedStep™ technology available from Intel Corporation, Santa Clara, Calif. , to provide optimal performance at a lowest power consumption level. In another example, DVFS may be performed using Intel TurboBoost™ technology to enable one or more cores or other compute engines to operate at a higher than guaranteed operating frequency based on conditions (e.g., workload and availability).

Another power management technique that may be used in certain examples is dynamic swapping of workloads between different compute engines. For example, the processor may include asymmetric cores or other processing engines that operate at different power consumption levels, such that in a power constrained situation, one or more workloads can be dynamically switched to execute on a lower power core or other compute engine. Another exemplary power management technique is hardware duty cycling (HDC), which may cause cores and/or other compute engines to be periodically enabled and disabled according to a duty cycle, such that one or more cores may be made inactive during an inactive period of the duty cycle and made active during an active period of the duty cycle. Although described with these particular examples, understand that many other power management techniques may be used in particular embodiments.

Embodiments can be implemented in processors for various markets including server processors, desktop processors, mobile processors and so forth. Referring now to <FIG>, shown is a block diagram of a processor in accordance with an embodiment. As shown in <FIG>, processor <NUM> may be a multicore processor including a plurality of cores <NUM>a-<NUM>n. In one embodiment, each such core may be of an independent power domain and can be configured to enter and exit active states and/or maximum performance states based on workload. The various cores may be coupled via an interconnect <NUM> to a system agent <NUM> that includes various components. As seen, system agent <NUM> may include a shared cache <NUM> which may be a last level cache. In addition, the system agent may include an integrated memory controller <NUM> to communicate with a system memory (not shown in <FIG>), e.g., via a memory bus. System agent <NUM> also includes various interfaces <NUM> and a power control unit <NUM>, which may include logic to perform the power management techniques described herein. In the embodiment shown, power control unit <NUM> includes a MEP controller <NUM> that may determine an initial MEP point for processor <NUM>. In addition, MEP controller <NUM> may dynamically determine one or more updates to the MEP operating point based at least in part on activity tracking information and/or temperature tracking information as described herein. In addition, at appropriate age-related time durations, MEP controller <NUM> may determine an updated optimum MEP performance state.

In addition, by interfaces 250a-250n, connection can be made to various off-chip components such as peripheral devices, mass storage and so forth. While shown with this particular implementation in the embodiment of <FIG>, the scope of the present invention is not limited in this regard.

Referring now to <FIG>, shown is a block diagram of a multi-domain processor in accordance with another embodiment of the present invention. As shown in the embodiment of <FIG>, processor <NUM> includes multiple domains. Specifically, a core domain <NUM> can include a plurality of cores <NUM><NUM>-<NUM>n, a graphics domain <NUM> can include one or more graphics engines, and a system agent domain <NUM> may further be present. In some embodiments, system agent domain <NUM> may execute at an independent frequency than the core domain and may remain powered on at all times to handle power control events and power management such that domains <NUM> and <NUM> can be controlled to dynamically enter into and exit high power and low power states. Each of domains <NUM> and <NUM> may operate at different voltage and/or power. Note that while only shown with three domains, understand the scope of the present invention is not limited in this regard and additional domains can be present in other embodiments. For example, multiple core domains may be present each including at least one core.

In general, each core <NUM> may further include low level caches in addition to various execution units and additional processing elements. In turn, the various cores may be coupled to each other and to a shared cache memory formed of a plurality of units of a last level cache (LLC) <NUM><NUM>-<NUM>n. In various embodiments, LLC <NUM> may be shared amongst the cores and the graphics engine, as well as various media processing circuitry. As seen, a ring interconnect <NUM> thus couples the cores together, and provides interconnection between the cores, graphics domain <NUM> and system agent circuitry <NUM>. In one embodiment, interconnect <NUM> can be part of the core domain. However in other embodiments the ring interconnect can be of its own domain.

As further seen, system agent domain <NUM> may include display controller <NUM> which may provide control of and an interface to an associated display. As further seen, system agent domain <NUM> may include a power control unit <NUM> which can include logic to perform the power management techniques described herein. In the embodiment shown, power control unit <NUM> includes a MEP controller <NUM>, which may determine initial and updated MEP operating points based on some or all of process variation information, activity tracking information and temperature tracking information, using a heuristic-based approach to leverage information in one or more lookup tables, as described herein.

As further seen in <FIG>, processor <NUM> can further include an integrated memory controller (IMC) <NUM> that can provide for an interface to a system memory, such as a dynamic random access memory (DRAM). Multiple interfaces <NUM><NUM>-<NUM>n may be present to enable interconnection between the processor and other circuitry. For example, in one embodiment at least one direct media interface (DMI) interface may be provided as well as one or more PCIe™ interfaces. Still further, to provide for communications between other agents such as additional processors or other circuitry, one or more QPI interfaces may also be provided. Although shown at this high level in the embodiment of <FIG>, understand the scope of the present invention is not limited in this regard.

Referring to <FIG>, an embodiment of a processor including multiple cores is illustrated. Processor <NUM> includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SoC), or other device to execute code. Processor <NUM>, in one embodiment, includes at least two cores -- cores <NUM> and <NUM>, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor <NUM> may include any number of processing elements that may be symmetric or asymmetric.

In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.

A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.

Physical processor <NUM>, as illustrated in <FIG>, includes two cores, cores <NUM> and <NUM>. Here, cores <NUM> and <NUM> are considered symmetric cores, i.e., cores with the same configurations, functional units, and/or logic. In another embodiment, core <NUM> includes an out-of-order processor core, while core <NUM> includes an in-order processor core. However, cores <NUM> and <NUM> may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native instruction set architecture (ISA), a core adapted to execute a translated ISA, a co-designed core, or other known core. Yet to further the discussion, the functional units illustrated in core <NUM> are described in further detail below, as the units in core <NUM> operate in a similar manner.

As depicted, core <NUM> includes two hardware threads 401a and 401b, which may also be referred to as hardware thread slots 401a and 401b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor <NUM> as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 401a, a second thread is associated with architecture state registers 401b, a third thread may be associated with architecture state registers 402a, and a fourth thread may be associated with architecture state registers 402b. Here, each of the architecture state registers (401a, 401b, 402a, and 402b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 401a are replicated in architecture state registers 401b, so individual architecture states/contexts are capable of being stored for logical processor 401a and logical processor 401b. In core <NUM>, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block <NUM> may also be replicated for threads 401a and 401b. Some resources, such as re-order buffers in reorder/retirement unit <NUM>, ILTB <NUM>, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB <NUM>, execution unit(s) <NUM>, and portions of out-of-order unit <NUM> are potentially fully shared.

Processor <NUM> often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In <FIG>, an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core <NUM> includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer <NUM> to predict branches to be executed/taken and an instruction-translation buffer (I-TLB) <NUM> to store address translation entries for instructions.

Core <NUM> further includes decode module <NUM> coupled to fetch unit <NUM> to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 401a, 401b, respectively. Usually core <NUM> is associated with a first ISA, which defines/specifies instructions executable on processor <NUM>. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic <NUM> includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, decoders <NUM>, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders <NUM>, the architecture or core <NUM> takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions.

In one example, allocator and renamer block <NUM> includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 401a and 401b are potentially capable of out-of-order execution, where allocator and renamer block <NUM> also reserves other resources, such as reorder buffers to track instruction results. Unit <NUM> may also include a register renamer to rename program/instruction reference registers to other registers internal to processor <NUM>. Reorder/retirement unit <NUM> includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.

Scheduler and execution unit(s) block <NUM>, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

Lower level data cache and data translation buffer (D-TLB) <NUM> are coupled to execution unit(s) <NUM>. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.

Here, cores <NUM> and <NUM> share access to higher-level or further-out cache <NUM>, which is to cache recently fetched elements. Note that higher-level or further-out refers to cache levels increasing or getting further away from the execution unit(s). In one embodiment, higher-level cache <NUM> is a last-level data cache - last cache in the memory hierarchy on processor <NUM> - such as a second or third level data cache. However, higher level cache <NUM> is not so limited, as it may be associated with or includes an instruction cache. A trace cache - a type of instruction cache - instead may be coupled after decoder <NUM> to store recently decoded traces.

In the depicted configuration, processor <NUM> also includes bus interface module <NUM> and a power controller <NUM>, which may perform power management in accordance with an embodiment. In this scenario, bus interface <NUM> is to communicate with devices external to processor <NUM>, such as system memory and other components.

A memory controller <NUM> may interface with other devices such as one or many memories. In an example, bus interface <NUM> includes a ring interconnect with a memory controller for interfacing with a memory and a graphics controller for interfacing with a graphics processor. In an SoC environment, even more devices, such as a network interface, coprocessors, memory, graphics processor, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.

Referring now to <FIG>, shown is a block diagram of a micro-architecture of a processor core in accordance with one embodiment. As shown in <FIG>, processor core <NUM> may be a multi-stage pipelined out-of-order processor. Core <NUM> may operate at various voltages based on a received operating voltage, which may be received from an integrated voltage regulator or external voltage regulator.

As seen in <FIG>, core <NUM> includes front end units <NUM>, which may be used to fetch instructions to be executed and prepare them for use later in the processor pipeline. For example, front end units <NUM> may include a fetch unit <NUM>, an instruction cache <NUM>, and an instruction decoder <NUM>. In some implementations, front end units <NUM> may further include a trace cache, along with microcode storage as well as a micro-operation storage. Fetch unit <NUM> may fetch macro-instructions, e.g., from memory or instruction cache <NUM>, and feed them to instruction decoder <NUM> to decode them into primitives, i.e., micro-operations for execution by the processor.

Coupled between front end units <NUM> and execution units <NUM> is an out-of-order (OOO) engine <NUM> that may be used to receive the micro-instructions and prepare them for execution. More specifically OOO engine <NUM> may include various buffers to re-order micro-instruction flow and allocate various resources needed for execution, as well as to provide renaming of logical registers onto storage locations within various register files such as register file <NUM> and extended register file <NUM>. Register file <NUM> may include separate register files for integer and floating point operations. Extended register file <NUM> may provide storage for vector-sized units, e.g., <NUM> or <NUM> bits per register. For purposes of configuration, control, and additional operations, a set of machine specific registers (MSRs) <NUM> may also be present and accessible to various logic within core <NUM> (and external to the core).

Various resources may be present in execution units <NUM>, including, for example, various integer, floating point, and single instruction multiple data (SIMD) logic units, among other specialized hardware. For example, such execution units may include one or more arithmetic logic units (ALUs) <NUM> and one or more vector execution units <NUM>, among other such execution units.

Results from the execution units may be provided to retirement logic, namely a reorder buffer (ROB) <NUM>. More specifically, ROB <NUM> may include various arrays and logic to receive information associated with instructions that are executed. This information is then examined by ROB <NUM> to determine whether the instructions can be validly retired and result data committed to the architectural state of the processor, or whether one or more exceptions occurred that prevent a proper retirement of the instructions. Of course, ROB <NUM> may handle other operations associated with retirement.

As shown in <FIG>, ROB <NUM> is coupled to a cache <NUM> which, in one embodiment may be a low level cache (e.g., an L1 cache) although the scope of the present invention is not limited in this regard. Also, execution units <NUM> can be directly coupled to cache <NUM>. From cache <NUM>, data communication may occur with higher level caches, system memory and so forth. While shown with this high level in the embodiment of <FIG>, understand the scope of the present invention is not limited in this regard. For example, while the implementation of <FIG> is with regard to an out-of-order machine such as of an Intel® x86 instruction set architecture (ISA), the scope of the present invention is not limited in this regard. That is, other embodiments may be implemented in an in-order processor, a reduced instruction set computing (RISC) processor such as an ARM-based processor, or a processor of another type of ISA that can emulate instructions and operations of a different ISA via an emulation engine and associated logic circuitry.

Referring now to <FIG>, shown is a block diagram of a micro-architecture of a processor core in accordance with another embodiment. In the embodiment of <FIG>, core <NUM> may be a low power core of a different micro-architecture, such as an Intel®. Atom™-based processor having a relatively limited pipeline depth designed to reduce power consumption. As seen, core <NUM> includes an instruction cache <NUM> coupled to provide instructions to an instruction decoder <NUM>. A branch predictor <NUM> may be coupled to instruction cache <NUM>. Note that instruction cache <NUM> may further be coupled to another level of a cache memory, such as an L2 cache (not shown for ease of illustration in <FIG>). In turn, instruction decoder <NUM> provides decoded instructions to an issue queue <NUM> for storage and delivery to a given execution pipeline. A microcode ROM <NUM> is coupled to instruction decoder <NUM>.

A floating point pipeline <NUM> includes a floating point register file <NUM> which may include a plurality of architectural registers of a given bit with such as <NUM>, <NUM> or <NUM> bits. Pipeline <NUM> includes a floating point scheduler <NUM> to schedule instructions for execution on one of multiple execution units of the pipeline. In the embodiment shown, such execution units include an ALU <NUM>, a shuffle unit <NUM>, and a floating point adder <NUM>. In turn, results generated in these execution units may be provided back to buffers and/or registers of register file <NUM>. Of course understand while shown with these few example execution units, additional or different floating point execution units may be present in another embodiment.

An integer pipeline <NUM> also may be provided. In the embodiment shown, pipeline <NUM> includes an integer register file <NUM> which may include a plurality of architectural registers of a given bit with such as <NUM> or <NUM> bits. Pipeline <NUM> includes an integer scheduler <NUM> to schedule instructions for execution on one of multiple execution units of the pipeline. In the embodiment shown, such execution units include an ALU <NUM>, a shifter unit <NUM>, and a jump execution unit <NUM>. In turn, results generated in these execution units may be provided back to buffers and/or registers of register file <NUM>. Of course understand while shown with these few example execution units, additional or different integer execution units may be present in another embodiment.

A memory execution scheduler <NUM> may schedule memory operations for execution in an address generation unit <NUM>, which is also coupled to a TLB <NUM>. As seen, these structures may couple to a data cache <NUM>, which may be a L0 and/or L1 data cache that in turn couples to additional levels of a cache memory hierarchy, including an L2 cache memory.

To provide support for out-of-order execution, an allocator/renamer <NUM> may be provided, in addition to a reorder buffer <NUM>, which is configured to reorder instructions executed out of order for retirement in order. Although shown with this particular pipeline architecture in the illustration of <FIG>, understand that many variations and alternatives are possible.

Note that in a processor having asymmetric cores, such as in accordance with the micro-architectures of <FIG> and <FIG>, workloads may be dynamically swapped between the cores for power management reasons, as these cores, although having different pipeline designs and depths, may be of the same or related ISA. Such dynamic core swapping may be performed in a manner transparent to a user application (and possibly kernel also).

Referring to <FIG>, shown is a block diagram of a micro-architecture of a processor core in accordance with yet another embodiment. As illustrated in <FIG>, a core <NUM> may include a multi-staged in-order pipeline to execute at very low power consumption levels. As one such example, processor <NUM> may have a micro-architecture in accordance with an ARM Cortex A53 design available from ARM Holdings, LTD. , Sunnyvale, Calif. In an implementation, an <NUM>-stage pipeline may be provided that is configured to execute both <NUM>-bit and <NUM>-bit code. Core <NUM> includes a fetch unit <NUM> that is configured to fetch instructions and provide them to a decode unit <NUM>, which may decode the instructions, e.g., macro-instructions of a given ISA such as an ARMv8 ISA. Note further that a queue <NUM> may couple to decode unit <NUM> to store decoded instructions. Decoded instructions are provided to an issue logic <NUM>, where the decoded instructions may be issued to a given one of multiple execution units.

With further reference to <FIG>, issue logic <NUM> may issue instructions to one of multiple execution units. In the embodiment shown, these execution units include an integer unit <NUM>, a multiply unit <NUM>, a floating point/vector unit <NUM>, a dual issue unit <NUM>, and a load/store unit <NUM>. The results of these different execution units may be provided to a writeback unit <NUM>. Understand that while a single writeback unit is shown for ease of illustration, in some implementations separate writeback units may be associated with each of the execution units. Furthermore, understand that while each of the units and logic shown in <FIG> is represented at a high level, a particular implementation may include more or different structures. A processor designed using one or more cores having a pipeline as in <FIG> may be implemented in many different end products, extending from mobile devices to server systems.

Referring to <FIG>, shown is a block diagram of a micro-architecture of a processor core in accordance with a still further embodiment. As illustrated in <FIG>, a core <NUM> may include a multi-stage multi-issue out-of-order pipeline to execute at very high performance levels (which may occur at higher power consumption levels than core <NUM> of <FIG>). As one such example, processor <NUM> may have a microarchitecture in accordance with an ARM Cortex A57 design. In an implementation, a <NUM> (or greater)-stage pipeline may be provided that is configured to execute both <NUM>-bit and <NUM>-bit code. In addition, the pipeline may provide for <NUM> (or greater)-wide and <NUM> (or greater)-issue operation. Core <NUM> includes a fetch unit <NUM> that is configured to fetch instructions and provide them to a decoder/renamer/dispatcher <NUM>, which may decode the instructions, e.g., macro-instructions of an ARMv8 instruction set architecture, rename register references within the instructions, and dispatch the instructions (eventually) to a selected execution unit. Decoded instructions may be stored in a queue <NUM>. Note that while a single queue structure is shown for ease of illustration in <FIG>, understand that separate queues may be provided for each of the multiple different types of execution units.

Also shown in <FIG> is an issue logic <NUM> from which decoded instructions stored in queue <NUM> may be issued to a selected execution unit. Issue logic <NUM> also may be implemented in a particular embodiment with a separate issue logic for each of the multiple different types of execution units to which issue logic <NUM> couples.

Decoded instructions may be issued to a given one of multiple execution units. In the embodiment shown, these execution units include one or more integer units <NUM>, a multiply unit <NUM>, a floating point/vector unit <NUM>, a branch unit <NUM>, and a load/store unit <NUM>. In an embodiment, floating point/vector unit <NUM> may be configured to handle SIMD or vector data of <NUM> or <NUM> bits. Still further, floating point/vector execution unit <NUM> may perform IEEE-<NUM> double precision floating-point operations. The results of these different execution units may be provided to a writeback unit <NUM>. Note that in some implementations separate writeback units may be associated with each of the execution units. Furthermore, understand that while each of the units and logic shown in <FIG> is represented at a high level, a particular implementation may include more or different structures.

Note that in a processor having asymmetric cores, such as in accordance with the micro-architectures of <FIG> and <FIG>, workloads may be dynamically swapped for power management reasons, as these cores, although having different pipeline designs and depths, may be of the same or related ISA. Such dynamic core swapping may be performed in a manner transparent to a user application (and possibly kernel also).

A processor designed using one or more cores having pipelines as in any one or more of <FIG> may be implemented in many different end products, extending from mobile devices to server systems. Referring now to <FIG>, shown is a block diagram of a processor in accordance with another embodiment. In the embodiment of <FIG>, processor <NUM> may be a SoC including multiple domains, each of which may be controlled to operate at an independent operating voltage and operating frequency. As a specific illustrative example, processor <NUM> may be an Intel® Architecture Core™-based processor such as an i3, i5, i7 or another such processor available from Intel Corporation. However, other low power processors such as available from Advanced Micro Devices, Inc. (AMD) of Sunnyvale, Calif. , an ARM-based design from ARM Holdings, Ltd. or licensee thereof or a MIPS-based design from MIPS Technologies, Inc. of Sunnyvale, Calif. , or their licensees or adopters may instead be present in other embodiments such as an Apple A7 processor, a Qualcomm Snapdragon processor, or Texas Instruments OMAP processor. Such SoC may be used in a low power system such as a smartphone, tablet computer, phablet computer, Ultrabook™ computer or other portable computing device or connected device.

In the high level view shown in <FIG>, processor <NUM> includes a plurality of core units <NUM><NUM>-<NUM>n. Each core unit may include one or more processor cores, one or more cache memories and other circuitry. Each core unit <NUM> may support one or more instructions sets (e.g., an x86 instruction set (with some extensions that have been added with newer versions); a MIPS instruction set; an ARM instruction set (with optional additional extensions such as NEON)) or other instruction set or combinations thereof. Note that some of the core units may be heterogeneous resources (e.g., of a different design). In addition, each such core may be coupled to a cache memory (not shown) which in an embodiment may be a shared level (L2) cache memory. A non-volatile storage <NUM> may be used to store various program and other data. For example, this storage may be used to store at least portions of microcode, boot information such as a BIOS, other system software or so forth.

Each core unit <NUM> may also include an interface such as a bus interface unit to enable interconnection to additional circuitry of the processor. In an embodiment, each core unit <NUM> couples to a coherent fabric that may act as a primary cache coherent on-die interconnect that in turn couples to a memory controller <NUM>. In turn, memory controller <NUM> controls communications with a memory such as a DRAM (not shown for ease of illustration in <FIG>).

In addition to core units, additional processing engines are present within the processor, including at least one graphics unit <NUM> which may include one or more graphics processing units (GPUs) to perform graphics processing as well as to possibly execute general purpose operations on the graphics processor (so-called GPGPU operation). In addition, at least one image signal processor <NUM> may be present. Signal processor <NUM> may be configured to process incoming image data received from one or more capture devices, either internal to the SoC or off-chip.

Other accelerators also may be present. In the illustration of <FIG>, a video coder <NUM> may perform coding operations including encoding and decoding for video information, e.g., providing hardware acceleration support for high definition video content. A display controller <NUM> further may be provided to accelerate display operations including providing support for internal and external displays of a system. In addition, a security processor <NUM> may be present to perform security operations such as secure boot operations, various cryptography operations and so forth.

Each of the units may have its power consumption controlled via a power manager <NUM>, which may include control logic to perform the various power management techniques described herein.

In some embodiments, SoC <NUM> may further include a non-coherent fabric coupled to the coherent fabric to which various peripheral devices may couple. One or more interfaces 960a-960d enable communication with one or more off-chip devices. Such communications may be via a variety of communication protocols such as PCIe™ GPIO, USB, I<NUM>C, UART, MIPI, SDIO, DDR, SPI, HDMI, among other types of communication protocols. Although shown at this high level in the embodiment of <FIG>, understand the scope of the present invention is not limited in this regard.

Referring now to <FIG>, shown is a block diagram of a representative SoC. In the embodiment shown, SoC <NUM> may be a multi-core SoC configured for low power operation to be optimized for incorporation into a smartphone or other low power device such as a tablet computer or other portable computing device. As an example, SoC <NUM> may be implemented using asymmetric or different types of cores, such as combinations of higher power and/or low power cores, e.g., out-of-order cores and in-order cores. In different embodiments, these cores may be based on an Intel® Architecture™ core design or an ARM architecture design. In yet other embodiments, a mix of Intel® and ARM cores may be implemented in a given SoC.

As seen in <FIG>, SoC <NUM> includes a first core domain <NUM> having a plurality of first cores <NUM><NUM>-<NUM><NUM>. In an example, these cores may be low power cores such as in-order cores. In one embodiment these first cores may be implemented as ARM Cortex A53 cores. In turn, these cores couple to a cache memory <NUM> of core domain <NUM>. In addition, SoC <NUM> includes a second core domain <NUM>. In the illustration of <FIG>, second core domain <NUM> has a plurality of second cores <NUM><NUM>-<NUM><NUM>. In an example, these cores may be higher power-consuming cores than first cores <NUM>. In an embodiment, the second cores may be out-of-order cores, which may be implemented as ARM Cortex A57 cores. In turn, these cores couple to a cache memory <NUM> of core domain <NUM>. Note that while the example shown in <FIG> includes <NUM> cores in each domain, understand that more or fewer cores may be present in a given domain in other examples.

With further reference to <FIG>, a graphics domain <NUM> also is provided, which may include one or more graphics processing units (GPUs) configured to independently execute graphics workloads, e.g., provided by one or more cores of core domains <NUM> and <NUM>. As an example, GPU domain <NUM> may be used to provide display support for a variety of screen sizes, in addition to providing graphics and display rendering operations.

As seen, the various domains couple to a coherent interconnect <NUM>, which in an embodiment may be a cache coherent interconnect fabric that in turn couples to an integrated memory controller <NUM>. Coherent interconnect <NUM> may include a shared cache memory, such as an L3 cache, in some examples. In an embodiment, memory controller <NUM> may be a direct memory controller to provide for multiple channels of communication with an off-chip memory, such as multiple channels of a DRAM (not shown for ease of illustration in <FIG>).

In different examples, the number of the core domains may vary. For example, for a low power SoC suitable for incorporation into a mobile computing device, a limited number of core domains such as shown in <FIG> may be present. Still further, in such low power SoCs, core domain <NUM> including higher power cores may have fewer numbers of such cores. For example, in one implementation two cores <NUM> may be provided to enable operation at reduced power consumption levels. In addition, the different core domains may also be coupled to an interrupt controller to enable dynamic swapping of workloads between the different domains.

In yet other embodiments, a greater number of core domains, as well as additional optional IP logic may be present, in that an SoC can be scaled to higher performance (and power) levels for incorporation into other computing devices, such as desktops, servers, high performance computing systems, base stations forth. As one such example, <NUM> core domains each having a given number of out-of-order cores may be provided. Still further, in addition to optional GPU support (which as an example may take the form of a GPGPU), one or more accelerators to provide optimized hardware support for particular functions (e.g. web serving, network processing, switching or so forth) also may be provided. In addition, an input/output interface may be present to couple such accelerators to off-chip components.

Referring now to <FIG>, shown is a block diagram of another example SoC. In the embodiment of <FIG>, SoC <NUM> may include various circuitry to enable high performance for multimedia applications, communications and other functions. As such, SoC <NUM> is suitable for incorporation into a wide variety of portable and other devices, such as smartphones, tablet computers, smart TVs and so forth. In the example shown, SoC <NUM> includes a central processor unit (CPU) domain <NUM>. In an embodiment, a plurality of individual processor cores may be present in CPU domain <NUM>. As one example, CPU domain <NUM> may be a quad core processor having <NUM> multithreaded cores. Such processors may be homogeneous or heterogeneous processors, e.g., a mix of low power and high power processor cores.

In turn, a GPU domain <NUM> is provided to perform advanced graphics processing in one or more GPUs to handle graphics and compute APIs. A DSP unit <NUM> may provide one or more low power DSPs for handling low-power multimedia applications such as music playback, audio/video and so forth, in addition to advanced calculations that may occur during execution of multimedia instructions. In turn, a communication unit <NUM> may include various components to provide connectivity via various wireless protocols, such as cellular communications (including <NUM>/<NUM> LTE), wireless local area protocols such as Bluetooth™, IEEE <NUM>, and so forth.

Still further, a multimedia processor <NUM> may be used to perform capture and playback of high definition video and audio content, including processing of user gestures. A sensor unit <NUM> may include a plurality of sensors and/or a sensor controller to interface to various off-chip sensors present in a given platform. An image signal processor <NUM> may be provided with one or more separate ISPs to perform image processing with regard to captured content from one or more cameras of a platform, including still and video cameras.

A display processor <NUM> may provide support for connection to a high definition display of a given pixel density, including the ability to wirelessly communicate content for playback on such display. Still further, a location unit <NUM> may include a GPS receiver with support for multiple GPS constellations to provide applications highly accurate positioning information obtained using as such GPS receiver. Understand that while shown with this particular set of components in the example of <FIG>, many variations and alternatives are possible.

Referring now to <FIG>, shown is a block diagram of an example system with which embodiments can be used. As seen, system <NUM> may be a smartphone or other wireless communicator. A baseband processor <NUM> is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor <NUM> is coupled to an application processor <NUM>, which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps. Application processor <NUM> may further be configured to perform a variety of other computing operations for the device and perform the power management techniques described herein.

In turn, application processor <NUM> can couple to a user interface/display <NUM>, e.g., a touch screen display. In addition, application processor <NUM> may couple to a memory system including a non-volatile memory, namely a flash memory <NUM> and a system memory, namely a dynamic random access memory (DRAM) <NUM>. As further seen, application processor <NUM> further couples to a capture device <NUM> such as one or more image capture devices that can record video and/or still images.

Still referring to <FIG>, a universal integrated circuit card (UICC) <NUM> comprising a subscriber identity module and possibly a secure storage and cryptoprocessor is also coupled to application processor <NUM>. System <NUM> may further include a security processor <NUM> that may couple to application processor <NUM>. A plurality of sensors <NUM> may couple to application processor <NUM> to enable input of a variety of sensed information such as accelerometer and other environmental information. An audio output device <NUM> may provide an interface to output sound, e.g., in the form of voice communications, played or streaming audio data and so forth.

As further illustrated, a near field communication (NFC) contactless interface <NUM> is provided that communicates in a NFC near field via an NFC antenna <NUM>. While separate antennae are shown in <FIG>, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionality.

A PMIC <NUM> couples to application processor <NUM> to perform platform level power management. To this end, PMIC <NUM> may issue power management requests to application processor <NUM> to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC <NUM> may also control the power level of other components of system <NUM>.

To enable communications to be transmitted and received, various circuitry may be coupled between baseband processor <NUM> and an antenna <NUM>. Specifically, a radio frequency (RF) transceiver <NUM> and a wireless local area network (WLAN) transceiver <NUM> may be present. In general, RF transceiver <NUM> may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as <NUM> or <NUM> wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor <NUM> may be present. Other wireless communications such as receipt or transmission of radio signals, e.g., AM/FM and other signals may also be provided. In addition, via WLAN transceiver <NUM>, local wireless communications can also be realized.

Referring now to <FIG>, shown is a block diagram of another example system with which embodiments may be used. In the illustration of <FIG>, system <NUM> may be mobile low-power system such as a tablet computer, <NUM>:<NUM> tablet, phablet or other convertible or standalone tablet system. As illustrated, a SoC <NUM> is present and may be configured to operate as an application processor for the device and perform the power management techniques described herein.

A variety of devices may couple to SoC <NUM>. In the illustration shown, a memory subsystem includes a flash memory <NUM> and a DRAM <NUM> coupled to SoC <NUM>. In addition, a touch panel <NUM> is coupled to the SoC <NUM> to provide display capability and user input via touch, including provision of a virtual keyboard on a display of touch panel <NUM>. To provide wired network connectivity, SoC <NUM> couples to an Ethernet interface <NUM>. A peripheral hub <NUM> is coupled to SoC <NUM> to enable interfacing with various peripheral devices, such as may be coupled to system <NUM> by any of various ports or other connectors.

In addition to internal power management circuitry and functionality within SoC <NUM>, a PMIC <NUM> is coupled to SoC <NUM> to provide platform-based power management, e.g., based on whether the system is powered by a battery <NUM> or AC power via an AC adapter <NUM>. In addition to this power source-based power management, PMIC <NUM> may further perform platform power management activities based on environmental and usage conditions. Still further, PMIC <NUM> may communicate control and status information to SoC <NUM> to cause various power management actions within SoC <NUM>.

Still referring to <FIG>, to provide for wireless capabilities, a WLAN unit <NUM> is coupled to SoC <NUM> and in turn to an antenna <NUM>. In various implementations, WLAN unit <NUM> may provide for communication according to one or more wireless protocols.

As further illustrated, a plurality of sensors <NUM> may couple to SoC <NUM>. These sensors may include various accelerometer, environmental and other sensors, including user gesture sensors. Finally, an audio codec <NUM> is coupled to SoC <NUM> to provide an interface to an audio output device <NUM>. Of course understand that while shown with this particular implementation in <FIG>, many variations and alternatives are possible.

Referring now to <FIG>, shown is a block diagram of a representative computer system such as notebook, Ultrabook™ or other small form factor system. A processor <NUM>, in one embodiment, includes a microprocessor, multi-core processor, multithreaded processor, an ultra low voltage processor, an embedded processor, or other known processing element. In the illustrated implementation, processor <NUM> acts as a main processing unit and central hub for communication with many of the various components of the system <NUM>. As one example, processor <NUM> is implemented as a SoC.

Processor <NUM>, in one embodiment, communicates with a system memory <NUM>. As an illustrative example, the system memory <NUM> is implemented via multiple memory devices or modules to provide for a given amount of system memory.

To provide for persistent storage of information such as data, applications, one or more operating systems and so forth, a mass storage <NUM> may also couple to processor <NUM>. In various embodiments, to enable a thinner and lighter system design as well as to improve system responsiveness, this mass storage may be implemented via a SSD or the mass storage may primarily be implemented using a hard disk drive (HDD) with a smaller amount of SSD storage to act as a SSD cache to enable non-volatile storage of context state and other such information during power down events so that a fast power up can occur on re-initiation of system activities. Also shown in <FIG>, a flash device <NUM> may be coupled to processor <NUM>, e.g., via a serial peripheral interface (SPI). This flash device may provide for non-volatile storage of system software, including a basic input/output software (BIOS) as well as other firmware of the system.

Various input/output (I/O) devices may be present within system <NUM>. Specifically shown in the embodiment of <FIG> is a display <NUM> which may be a high definition LCD or LED panel that further provides for a touch screen <NUM>. In one embodiment, display <NUM> may be coupled to processor <NUM> via a display interconnect that can be implemented as a high performance graphics interconnect. Touch screen <NUM> may be coupled to processor <NUM> via another interconnect, which in an embodiment can be an I<NUM>C interconnect. As further shown in <FIG>, in addition to touch screen <NUM>, user input by way of touch can also occur via a touch pad <NUM> which may be configured within the chassis and may also be coupled to the same I<NUM>C interconnect as touch screen <NUM>.

For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to processor <NUM> in different manners. Certain inertial and environmental sensors may couple to processor <NUM> through a sensor hub <NUM>, e.g., via an I2C interconnect. In the embodiment shown in <FIG>, these sensors may include an accelerometer <NUM>, an ambient light sensor (ALS) <NUM>, a compass <NUM> and a gyroscope <NUM>. Other environmental sensors may include one or more thermal sensors <NUM> which in some embodiments couple to processor <NUM> via a system management bus (SMBus) bus.

Also seen in <FIG>, various peripheral devices may couple to processor <NUM> via a low pin count (LPC) interconnect. In the embodiment shown, various components can be coupled through an embedded controller <NUM>. Such components can include a keyboard <NUM> (e.g., coupled via a PS2 interface), a fan <NUM>, and a thermal sensor <NUM>. In some embodiments, touch pad <NUM> may also couple to EC <NUM> via a PS2 interface. In addition, a security processor such as a trusted platform module (TPM) <NUM> may also couple to processor <NUM> via this LPC interconnect.

System <NUM> can communicate with external devices in a variety of manners, including wirelessly. In the embodiment shown in <FIG>, various wireless modules, each of which can correspond to a radio configured for a particular wireless communication protocol, are present. One manner for wireless communication in a short range such as a near field may be via a NFC unit <NUM> which may communicate, in one embodiment with processor <NUM> via an SMBus. Note that via this NFC unit <NUM>, devices in close proximity to each other can communicate.

As further seen in <FIG>, additional wireless units can include other short range wireless engines including a WLAN unit <NUM> and a Bluetooth unit <NUM>. Using WLAN unit <NUM>, Wi-Fi™ communications can be realized, while via Bluetooth unit <NUM>, short range Bluetooth™ communications can occur. These units may communicate with processor <NUM> via a given link.

In addition, wireless wide area communications, e.g., according to a cellular or other wireless wide area protocol, can occur via a WWAN unit <NUM> which in turn may couple to a subscriber identity module (SIM) <NUM>. In addition, to enable receipt and use of location information, a GPS module <NUM> may also be present. Note that in the embodiment shown in <FIG>, WWAN unit <NUM> and an integrated capture device such as a camera module <NUM> may communicate via a given link.

An integrated camera module <NUM> can be incorporated in the lid. To provide for audio inputs and outputs, an audio processor can be implemented via a digital signal processor (DSP) <NUM>, which may couple to processor <NUM> via a high definition audio (HDA) link. Similarly, DSP <NUM> may communicate with an integrated coder/decoder (CODEC) and amplifier <NUM> that in turn may couple to output speakers <NUM> which may be implemented within the chassis. Similarly, amplifier and CODEC <NUM> can be coupled to receive audio inputs from a microphone <NUM> which in an embodiment can be implemented via dual array microphones (such as a digital microphone array) to provide for high quality audio inputs to enable voice-activated control of various operations within the system. Note also that audio outputs can be provided from amplifier/CODEC <NUM> to a headphone jack <NUM>. Although shown with these particular components in the embodiment of <FIG>, understand the scope of the present invention is not limited in this regard.

Embodiments may be implemented in many different system types. Referring now to <FIG>, shown is a block diagram of a system in accordance with an embodiment of the present invention. As shown in <FIG>, multiprocessor system <NUM> is a point-to-point interconnect system, and includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. As shown in <FIG>, each of processors <NUM> and <NUM> may be multicore processors, including first and second processor cores (i.e., processors 1574a and 1574b and processor cores 1584a and 1584b), although potentially many more cores may be present in the processors. In addition, each of processors <NUM> and <NUM> also may include a graphics processor unit (GPU) <NUM>, <NUM> to perform graphics operations. Each of the processors can include a PCU <NUM>, <NUM> to perform processor-based power management. In the embodiment of <FIG>, processors <NUM>, <NUM> may include MEP controllers <NUM>, <NUM>, adapted separately from PCUs <NUM>, <NUM>, to perform MEP-based determinations and provide initial and updated MEP values to the corresponding PCUs, to enable the PCU to enhance its functionality to perform energy control in addition to power control, as described herein.

Still referring to <FIG>, first processor <NUM> further includes a memory controller hub (MCH) <NUM> and point-to-point (P-P) interfaces <NUM> and <NUM>. Similarly, second processor <NUM> includes a MCH <NUM> and P-P interfaces <NUM> and <NUM>. As shown in <FIG>, MCH's <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of system memory (e.g., DRAM) locally attached to the respective processors. First processor <NUM> and second processor <NUM> may be coupled to a chipset <NUM> via P-P interconnects <NUM> and <NUM>, respectively. As shown in <FIG>, chipset <NUM> includes P-P interfaces <NUM> and <NUM>.

Furthermore, chipset <NUM> includes an interface <NUM> to couple chipset <NUM> with a high performance graphics engine <NUM>, by a P-P interconnect <NUM>. In turn, chipset <NUM> may be coupled to a first bus <NUM> via an interface <NUM>. As shown in <FIG>, various input/output (I/O) devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. Various devices may be coupled to second bus <NUM> including, for example, a keyboard/mouse <NUM>, communication devices <NUM> and a data storage unit <NUM> such as a disk drive or other mass storage device which may include code <NUM>, in one embodiment. Further, an audio I/O <NUM> may be coupled to second bus <NUM>. Embodiments can be incorporated into other types of systems including mobile devices such as a smart cellular telephone, tablet computer, netbook, Ultrabook™, or so forth.

<FIG> is a block diagram illustrating an IP core development system <NUM> that may be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system <NUM> may be used to generate modular, reusable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SoC integrated circuit). A design facility <NUM> can generate a software simulation <NUM> of an IP core design in a high level programming language (e.g., C/C++). The software simulation <NUM> can be used to design, test, and verify the behavior of the IP core. A register transfer level (RTL) design can then be created or synthesized from the simulation model. The RTL design <NUM> is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals. In addition to an RTL design <NUM>, lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary.

The RTL design <NUM> or equivalent may be further synthesized by the design facility into a hardware model <NUM>, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a third party fabrication facility <NUM> using non-volatile memory <NUM> (e.g., hard disk, flash memory, or any non-volatile storage medium). Alternately, the IP core design may be transmitted (e.g., via the Internet) over a wired connection <NUM> or wireless connection <NUM>. The fabrication facility <NUM> may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

Referring now to <FIG>, shown is a flow diagram of a method in accordance with an embodiment. More specifically, method <NUM> of <FIG> is a method for determining optimal minimum energy points (MEPs) in a processor in accordance with an embodiment. As such, method <NUM> may be performed by hardware circuitry, firmware, software and/or combinations thereof. For example, at least portions of method <NUM> may be performed by a MEP controller of a processor, such as may be implemented in a power controller of the processor.

As illustrated, method <NUM> begins by performing a sweep of voltage and frequency to identify an initial optimum voltage (block <NUM>). Such operation may occur initially upon a first initialization of the processor, e.g., when configured in a given computing platform, either during manufacturing testing and/or in the field. More specifically, this optimum voltage may correspond to a minimum energy point for the processor, based upon this sweep of voltage and frequency. For example, a power controller may cause the processor to operate at a set of different operating points each having a given operating voltage and operating frequency. Based on sensor information an energy calculation (e.g., an energy per operation value) can be obtained during operation at these different operating points, from which the MEP can be identified. And within this MEP, an initial optimum voltage is identified. Next, at block <NUM>, this initial optimum voltage may be stored in a configuration storage, e.g., present in a configuration register of a power controller. Note that at this point, with an initial optimum voltage and optimal frequency corresponding to a MEP, a processor may begin or continue normal operation.

Thus as further illustrated in <FIG>, at block <NUM> during such normal operation, temperature tracking information and activity tracking information may be received in the MEP controller. In an embodiment, temperature tracking information may be based on thermal information from a plurality of thermal sensors that may be adapted in the processor. And the activity tracking information may, in an embodiment, be based at least in part on activity counter information regarding various micro-architectural activities of the processor, including bandwidth information, cache operation, instructions per cycle information, among many other types of micro-architectural activity information.

Still with reference to <FIG>, it is determined whether a change in either of these different types of tracking information exceeds a corresponding threshold (diamond <NUM>). If not, control passes back to block <NUM> where additional tracking information may be received, e.g., for a next evaluation interval. Note that in different embodiments this evaluation interval may be according to a given timer, e.g., operating at a given clock rate. In other cases, this evaluation interval may be according to an event-based trigger, by an asynchronous change in operating condition that exceeds a threshold.

In any event, if it is determined that a change in at least one of these different types of tracking information exceeds a given threshold, control passes to block <NUM>. At block <NUM> the temperature tracking information and/or the activity tracking information (e.g., one or both that exceeds a corresponding threshold) may be processed. For example, this tracking information may be encoded into a corresponding step value based at least in part on the level of the tracking information. And from such step values, further processing may be performed to determine an optimal step value.

Next, control passes to block <NUM> where a voltage-frequency table may be accessed using the determined optimal step value. More specifically, based upon this optimal step value, a given entry of the voltage-frequency table may be accessed to obtain an optimum minimum energy point operating point. This MEP point may correspond to an operating voltage and frequency for this new optimum MEP. While shown not shown for ease of illustration in <FIG>, understand that an update to the configuration storage to store the new optimum voltage can occur. Still further, understand that the power controller may control the processor to operate at this new optimum MEP.

Still with reference to <FIG>, next may be determined whether an age-related timer has expired (diamond <NUM>). Understand that this age-related timer may correspond to a relatively long time duration, e.g., on the order of months, semi-annually, annually or so forth. This is so, as such a relatively long time duration may cause age-related deterioration of the processor, such that it is possible that the initial optimum voltage is no longer the correct voltage corresponding to a minimum energy point. Stated another way, this relatively long time duration is a process-sensitive time duration at which process-based degradation may occur. Thus if it is determined that such age-related timer expires, control passes back to block <NUM> discussed above, where a full sweep may be performed. Otherwise, continued temperature and activity tracking may occur beginning at block <NUM>. Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

Referring now to <FIG>, shown is a flow diagram of a method in accordance with the claimed embodiment. More specifically, method <NUM> of <FIG> is more detailed method for performing tracking to determine appropriate update to a MEP. As such, method <NUM> may be performed by hardware circuitry, firmware, software and/or combinations thereof. At least portions of method <NUM> are performed by a MEP controller.

As illustrated, method <NUM> begins by receiving temperature tracking information and activity tracking information (block <NUM>), such as discussed above. Next, control passes to block <NUM> where this tracking information is compared to prior values of the tracking information. For example, the temperature tracking information may be compared to an immediately previous value of the temperature tracking information. Or in other cases, a moving average may be maintained to reflect a history of the tracking information (and to provide a filtering and/or hysteresis control technique). Similar options exist for the activity tracking information, and any other tracking information that may be used in particular embodiments. Note further that with history data, machine learning-based pattern matching algorithms may be used to analysis the history data to identify appropriate MEP values.

Still with reference to <FIG>, next at diamond <NUM> it is determined whether the change in tracking information exceeds a given threshold. A first threshold is associated with the temperature tracking information, such that if the change exceeds this threshold, the determination at diamond <NUM> is positive for the temperature tracking information. And similarly, a second threshold is associated with the activity tracking information, such that if the change exceeds this threshold, the determination at diamond <NUM> is positive for the activity tracking information. If the change(s) are determined not to exceed any such threshold, no further operation occurs for this evaluation interval, and continued tracking is performed, beginning at block <NUM>.

With further reference to <FIG>, instead if it is determined that a change in at least one of the values of the tracking information exceeds a threshold level, control passes to block <NUM>. At block <NUM>, the change of the threshold-exceeding tracking information is encoded. More specifically, this change in tracking information is encoded into a step value. In an embodiment, this step value may be determined, e.g., with reference to a lookup table, in which an entry having a particular step value can be accessed using the amount of the change. For example, with regard to temperature, a temperature change of approximately <NUM> may be encoded into a step value of N equals <NUM>. Similarly, an activity level change of, e.g., 2x, may map into a step value change of M equals <NUM>. Of course many other example encodings are possible.

Still referring to <FIG>, at block <NUM> an optimal step value is calculated based on these one more step values. In a particular embodiment, an addition operation may be performed between the step values (e.g., N and M) to obtain the optimal step value.

At block <NUM>, a voltage-frequency table is accessed using the determined optimal step value to obtain an optimum MEP operating point. Next at block <NUM> at least one voltage regulator of the processor is controlled using the optimum MEP operating point. More specifically, the obtained operating voltage value can be provided to one or more voltage regulators to cause them to operate to output an operating voltage at this optimal operating voltage level. Similarly, at block <NUM>, at least one clock generator of the processor is controlled using the optimum MEP operating point. More specifically, the obtained operating frequency value can be provided to one or more clock generators to cause them to operate to output a clock signal at this optimal operating frequency level.

Referring now to <FIG>, shown is a graphical illustration of energy consumption with relation to operating voltage. For a given workload, there is an optimal operating voltage (Vopt) that corresponds to a MEP. As shown in <FIG>, for different workloads, the energy consumed reaches a MEP at Vopt, typically in the near-threshold voltage (NTV) region with <NUM>-5x better energy efficiency as compared to higher operation points. From either direction (along the X-axis) at other operating voltages for the same workload, increased energy occurs. And as shown, Vopt for different workloads (representative workloads curves are present at curves <NUM>, <NUM>, <NUM> and <NUM>) can shift by hundreds of millivolts with workload activity as the processor cycles through various sleep modes. In addition, MEP and Vopt can also change with operating conditions (e.g., due to variations in process, voltage and temperature (PVT)). As such, embodiments may provide a measure of MEP tracking and adjustment to reduce energy consumption, illustrated in <FIG> with increasing activity (as moving towards the left along the X-axis).

As described herein, to reach the MEP, a power controller causes one or voltage regulators to generate an operating voltage at the determined MEP level. In addition, the PMU further causes one or more clock generators to generate one or more clock signals at the corresponding determined operating frequency of the MEP. Over a typical workload interval, energy per operation (Eop) calculations may be computed as follows:<MAT> where, Vin equals input voltage, Fmax equals maximum frequency, T = <NUM>/Fmax ; and where, power (P) = Vin*Iin_avg, and Iin_avg is the average current consumed over the workload interval (T) and may be provided via current telemetry.

In a sweep operation, which may be performed at initialization of a processor to determine an initial MEP, and very infrequently to update this MEP to account for aging of the processor, a series of operations are performed. More specifically, Table <NUM> below illustrates a recursive sweep operation to determine an MEP. As shown, a MEP controller may compute the Eop at a plurality of points using Equation [<NUM>] to determine an optimum voltage (VOPT). This MEP curve traversal may take some undesirable length of time, since the V/F sweep can consume substantial time due to repeated clock frequency and voltage change delays in an incremental manner.

As described above, embodiments may minimally perform this sweep-based determination of MEP. Instead, after an initial MEP is determined according to a sweep such as performed in accordance with Table <NUM> above, embodiments may implement a faster parametric, sensor-based approach to run-time MEP tracking across PVT and workload conditions, with each variable being an input model parameter M.

Referring now to <FIG>, shown is a set of representative simulated MEP curves for changes in workload activity. As seen, diagram <NUM> illustrates a difference in Vopt for different workloads. For example, for a given workload x, Vopt may be at approximately <NUM> volts for a first workload curve <NUM>. For a 16x increase in workload, as illustrated at curve <NUM>, Vopt may be at <NUM> volts. And finally, for a reduction in workload by 16x, Vopt may be at <NUM> volts, as shown in curve <NUM>. As seen, a workload-based switching activity factor (α) is the single largest contributor to MEP optimum shift, with larger activity moving towards lower MEP values (and vice versa). In embodiments, powers of <NUM> can be used as activity steps, however any other multiple can be used.

Referring now to <FIG>, shown are example illustrations of change in MEP versus temperature (shown at diagram <NUM>) and change in MEP with regard to change in activity (illustrated at diagram <NUM>). As shown in diagram <NUM>, when varying die temperature and keeping all other parameters constant, there is a positive slope, with the MEP voltage shifting higher with higher temperatures. In this example, there is a representative slope of 10mV for each <NUM> degree Centigrade change. Of course, understand that other slopes are possible. In general, increased leakage from increased temperature can shift the MEP VOPT to a higher optimum value (and vice versa).

As shown in diagram <NUM> with a log-scale (for the X-axis), there is a negative slope for increasing workload changes, such that higher activity results in lower MEP V/F values. In this example, there is a change of 50mV MEP voltage for approximately every <NUM>. 5x change in workload induced vector switching activity. With these considerations from <FIG>, for a given process, VOPT changes are deterministic, depending on the temperature (T) and activity factor (α). More specifically, it can be seen that VOPT is proportional to (a*Temp + b*Alpha), where "a" and "b" slope parameters. Note that these values may be characterized by pre-silicon and/or post-silicon data. And as shown, the slopes a, b are in opposite directions (+ for a, minus (-) for b).

Referring now to <FIG>, shown is a block diagram of a MEP controller in accordance with an embodiment. As shown in <FIG>, controller <NUM> may be implemented as a hardware circuit. In one implementation, MEP controller <NUM> may be implemented within a power controller of a processor, such as a PCU. In other embodiments understand that the MEP controller may be implemented as a separate hardware circuit that provides output information in the form of a MEP performance state (e.g., including an optimal operating voltage and optimal operating frequency) to a power controller. In still other embodiments, understand that the various constituent components of MEP controller <NUM> may be distributed, with certain information being provided to MEP control circuitry and in turn additional information being output to, e.g., a power controller.

As illustrated in <FIG>, MEP controller <NUM> includes a process-temperature tracker <NUM>. In embodiments, process-temperature tracker <NUM> may receive incoming thermal information, e.g., in the form of temperature values from one or more temperature sensors adapted throughout the processor. In an embodiment, temperature may be determined using a calibrated ring oscillator or similar circuitry. Process-temperature tracker <NUM> may process the incoming thermal information to provide a temperature change (a change in temperature (δT). To this end, process-temperature tracker <NUM> may maintain information regarding prior temperature information received to provide this change in temperature, which may be performed on an evaluation cycle-by-evaluation cycle basis. In other cases, tracker <NUM> may maintain a moving average to filter or smooth out instantaneous variations. In any event, tracker <NUM> outputs this change in thermal tracking information to a MEP controller <NUM>. In addition, process-temperature tracker <NUM> may include a processor sensor which may be implemented using a ring oscillator to detect whether the silicon is of, e.g., a typical, slow or fast variation. Such sensor may provide a reference to set an initial MEP value. More specifically, a MEP controller may use this process variation, along with voltage/frequency sweep information to determine the initial MEP value.

As further shown, MEP controller <NUM> also includes an activity monitor <NUM>. In some cases, note that activity monitor <NUM> may receive incoming microarchitectural monitoring information, e.g., from a performance monitoring unit (PMU) of the processor. In an embodiment, activity factor estimation can be determined using micro-architectural and performance counters for switching events occurring at instruction level, e.g., cache hits, cache miss, loads, fused multiply add (FMA) retires, instruction retires, etc. A measure of activity can be inferred from these counters. As such, it is possible for monitor <NUM> to be implemented in the PMU itself. Activity monitor <NUM> may maintain information regarding prior activity information to provide this change in temperature, which may be performed on an evaluation cycle-by-evaluation cycle basis. In other cases, activity monitor <NUM> may maintain a moving average to filter or smooth out instantaneous variations. In any event, activity monitor <NUM> outputs this change in activity tracking information to MEP controller <NUM>.

Note that process-temperature tracker <NUM> and activity monitor <NUM> may operate during runtime to provide information that may be used to adjust optimal voltage during runtime based on workload and/or temperature of the processor. Thus in the embodiment of <FIG>, trackers <NUM>, <NUM> may perform rapid VOPT adjustment during run time, based on data from process, temperature and activity monitors/sensors. Note that in different embodiments, the sensors and MEP controller can be on-die or off-die.

Still further, understand that a sweeping-type MEP determination also may be performed, e.g., one time upon initialization of the processor. In addition, at process-sensitive time durations (which may be on the order of months, years or so forth), this sweep operation may be performed to determine an updated optimum MEP. As such as further illustrated in <FIG>, a power management integrated circuit (PMIC) current telemetry circuit <NUM> also may be present. Telemetry circuit <NUM> may be implemented within integrated voltage regulator circuitry of the processor. In other cases, telemetry circuit <NUM> may be separate from such voltage regulator, but in either case receives current sensing information from the voltage regulator. Telemetry circuit <NUM> may provide power data that can be used to compute energy (e.g., according to Equation <NUM> above) for one-time MEP tracking to obtain VOPT. In other embodiments, this sweep tracking may be avoided where a prior value is preloaded. Based on this information, current telemetry information may be provided to MEP controller <NUM>.

In various embodiments, MEP controller <NUM> may perform both a computation of long-term MEPs, as well as real time adjustment to such MEP values, using information from process-temperature tracker <NUM> and activity monitor <NUM>. As such, MEP control circuit <NUM> may perform calculations based on the change in tracking information received from process-temperature tracker <NUM> and activity monitor <NUM>. Based on the computations, access to a lookup table <NUM> may occur to determine an optimal MEP performance state. This optimal MEP performance state may be output to power control circuitry to control operating voltage and/or operating frequency of one or more cores or other processing circuits. Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

Referring now to <FIG>, shown is a block diagram of a MEP controller in accordance with another embodiment. In the embodiment of <FIG>, an environment <NUM> is shown with further detail that illustrates operations performed based on receipt of thermal tracking information and activity tracking information from corresponding process-temperature tracker <NUM> and activity monitor <NUM>.

As illustrated in <FIG>, a MEP controller <NUM> includes corresponding comparator and threshold circuitry <NUM>, <NUM> to receive the incoming change in tracking information and compare it to corresponding thresholds, which in embodiments may be programmable thresholds. In an embodiment, MEP controller <NUM> may periodically compare (and threshold) temperature and activity factor digital codes from corresponding sensors. When it is determined that the change in tracking information exceeds the corresponding threshold, the change in tracking information values (δT and δα) are provided to corresponding difference encoders <NUM>, <NUM>. Encoders <NUM>, <NUM> may encode maximum difference values (e.g., δT, δα) into discrete steps. In embodiments herein, these difference encoders may include or be coupled to one or more tracking tables to output a corresponding step value (n and/or m) based on the level of the change in tracking information. For example, in an embodiment one or more LUTs may be populated with a realistic range of pre-characterized temperature change (δT) and workload shift (δα) data. In one embodiment, a linear model may be used with activity triggers for every 2X change in workload and/or <NUM> change in temperature.

As further illustrated in <FIG>, these step values are provided to a computation circuit <NUM>, which may process these values to determine an optimal step value. In one embodiment, computation circuit <NUM> may compute this optimal step value according to: δT-δα. More particularly, a sum operation may be performed on the step values corresponding to the tracking changes. In an embodiment, computation circuit <NUM> may compute a sum (or difference) of (δT - δα), based on the temperature and activity sensor data, and may be implemented as a low overhead digital adder/subtraction circuit. Computation circuit <NUM>, in an embodiment, may also receive telemetry information from a voltage regulator, which may provide information regarding current consumption.

As further illustrated, MEP controller <NUM> includes a lookup table memory <NUM>, which includes a plurality of entries each including a voltage value and a frequency value. MEP controller <NUM> may access a given entry of memory <NUM> using the optimal step value to output an optimum MEP performance state (including an optimal operating voltage and an optimal operating frequency). In one particular example, for a +<NUM>, -4X activity change, values of δT = +<NUM>, δα = -<NUM> may be generated, giving <NUM>-(-<NUM>) = <NUM> steps (<NUM> + steps from activity, and <NUM> positive step from temperature). Here, 50mV = <NUM> step, and <NUM> change = <NUM> step. So the new VOPT is <NUM>. 2V (an original value) + <NUM> V, resulting in <NUM>. Note that in an embodiment, the optimal step value may be converted into a memory address to access LUT <NUM>, which provides the final/optimal MEP point (V, F) setting to be used to set operating voltage and frequency for one or more domains of the processor.

In embodiments, MEP controller <NUM> may provide this information to a power controller that in turn may control one or more voltage regulators and/or one or more clock generation circuits to output one or more operating voltages and/or one or more clock signals at the given operating frequency. Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

Embodiments thus may realize a dramatic reduction in computation and speed by effectively using sensor data and heuristics to intelligently adjust the optimum MEP in a relative manner, as compared to an expensive absolute MEP tracking technique. Understand that while this example uses trigger steps of <NUM> and 2x workload changes, the extent of discrete steps/action may differ. And with embodiments, per-die and/or per-process skew silicon adjustments may be realized by way of LUT information determined during manufacture. In other cases, silicon-aging sensors may be used to obtain age-based deterioration information to automatically adjust for long-term MEP shifts.

Table <NUM> below illustrates an example a pre-characterized lookup table for determining activity-based step changes. Understand that a similar table may be used for determining temperature-based changes, where resulting step values can be summed as discussed above to obtain an optimal step value that may be used to access a voltage-frequency table.

With embodiments, dynamic computation of energy consumption is performed, which is a more apt metric for extending battery life as compared to conventional power monitoring-based techniques. Stated another way, minimum power consumption modes do not necessarily translate into minimum energy modes. Embodiments thus provide sensor-driven, fast real-time MEP tracking and re-locking, eliminating the need for slower voltage/frequency-based sweep techniques, with low hardware cost. Note that in some cases, at least portions of the operations performed by a MEP controller may be implemented within other hardware, firmware and/or software, e.g., of a power controller.

Note that the terms "circuit" and "circuitry" are used interchangeably herein. As used herein, these terms and the term "logic" are used to refer to alone or in any combination, analog circuitry, digital circuitry, hard wired circuitry, programmable circuitry, processor circuitry, microcontroller circuitry, hardware logic circuitry, state machine circuitry and/or any other type of physical hardware component. Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein.

Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. Embodiments also may be implemented in data and may be stored on a non-transitory storage medium, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform one or more operations. Still further embodiments may be implemented in a computer readable storage medium including information that, when manufactured into a SoC or other processor, is to configure the SoC or other processor to perform one or more operations. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

Claim 1:
A processor comprising:
at least one core to execute instructions;
at least one temperature sensor to output temperature tracking information regarding the processor;
an activity monitor to monitor activity of the processor and to output activity tracking information based at least in part thereon;
a minimum energy point ,MEP, controller coupled to the at least one temperature sensor and the activity monitor, the MEP controller to:
compare the temperature tracking information to prior temperature tracking information;
determine whether a change in temperature tracking information exceeds a given first threshold;
if the change in temperature tracking information exceeds the given first threshold, encode the change in temperature tracking information into a first step value based on the level of the change in temperature tracking information;
compare the activity tracking information to prior activity tracking information;
determine whether a change in activating tracking information exceeds a given second threshold;
if the change in activity tracking information exceeds the given second threshold, encode the change in activity tracking information into a second step value based on the level of the change in activity tracking information;
compute a step value based on the first step value and the second step value;
determine a MEP performance state based on the computed step value by accessing a look up table comprising a plurality of entries each configured to store an operating voltage and an operating frequency; and
a power controller coupled to the MEP controller, the power controller configured to cause a voltage regulator of the processor to output a first operating voltage according to the MEP performance state and to cause a clock generation circuit of the processor to output a clock signal at a first operating frequency according to the MEP performance state.