Patent Description:
In some examples, a switch comprises first and second drain-extended transistors of a first type, third and fourth drain-extended transistors of a second type, a switch input coupled between drains of the first and third drain-extended transistors, a switch output coupled between drains of the second and fourth drain-extended transistors, and a control input. The control input is coupled to gates of the first and second drain-extended transistors, a first switch coupled to sources of the first and second drain-extended transistors, a second switch coupled between a voltage supply and gates of the third and fourth drain-extended transistors, and a third switch coupled between the voltage supply and sources of the third and fourth drain-extended transistors. The control input comprises a fifth drain-extended transistor coupled between the sources of the third and fourth drain-extended transistors and the gates of the third and fourth drain-extended transistors.

Due to a combination of technological, business, and practical factors, as semiconductor device dimensions decrease in size, they are increasingly limited in the voltages they can support. For example, the <NUM> process in some instances is able to support a maximum of <NUM> V, meaning that a component (e.g., a transistor) within a circuit manufactured using the <NUM> process is likely to encounter reliability problems if voltages across the component (e.g., across a gate oxide) are in excess of <NUM> V.

Some devices manufactured using relatively small process technologies (e.g., <NUM>) contain other components that require relatively high voltages. For example, a <NUM> process device capable of supporting <NUM> V may include a processor that requires switches capable of supporting relatively high <NUM> V inputs and outputs. Existing devices that include such switches are often unreliable because the relatively high voltages (e.g., <NUM> V) present at the switch inputs and outputs are carried to other nodes in the device where such high voltages are unsuitable. In some cases, the circuit design may be such that the high voltages are boosted even further (e.g., by a voltage supply rail) into the range of <NUM> V or higher, and these boosted voltages are applied to nodes in the device where they can cause significant damage and reliability problems.

Accordingly, this disclosure describes a switch that can accommodate high-voltage inputs and outputs without damaging or rendering unreliable the switch itself or other components in small, low-voltage process technology devices. The switch includes a pair of n-type drain-extended transistors and a pair of p-type drain-extended transistors. A drain-extended transistor is a transistor that has an implant in the drain allowing a large voltage drop across the drain boundary. Relative to other transistors, drain-extended transistor devices can handle much higher voltages across drain-to-gate, drain-to-bulk, and drain-to-source (although, without further modification, they may be held to the same process limitation of, for example, <NUM>. 8V across gate-to-source, gate-to-bulk, or source-to-bulk). The drains of the drain-extended transistors are coupled to the switch input and output so they can withstand high input and output voltages without reliability problems.

The switch includes a control input that turns the switch on and off. When the switch is off, the pairs of n-type and p-type drain-extended transistors are off and do not provide a pathway between the switch input and output. When the switch is on, the pairs of n-type and p-type drain-extended transistors provide pathways between the switch input and output, depending on the voltage provided at the switch input. For a first input voltage range, the pair of n-type drain-extended transistors provides a pathway from the switch input to the switch output. For a second input voltage range, the pair of p-type drain-extended transistors provides a pathway from the switch input to the switch output.

The n-type drain-extended transistors are controlled to be on and off using the control input and the input voltage provided at the switch input. Conversely, the p-type drain-extended transistors are controlled to be on and off using the input voltage provided at the switch input and circuitry within the switch that maintains a voltage at the p-type transistor gates that is adequately low relative to the sources of the p-type transistor gates so the p-type transistor gates are turned on. Various examples of the switch and systems implementing the switch are now described with reference to the drawings. As described below, the architecture of the switch precludes transistors within the switch from receiving a voltage across any two transistor terminals (e.g., gate to source, gate to drain, gate to bulk, source to drain, source to bulk, drain to bulk) that exceeds voltage levels appropriate for the process technology used (e.g., <NUM> V for <NUM> process technology), except for drains in drain-extended transistors (e.g., extended drain to source, extended drain to gate, extended drain to bulk), which may withstand high voltages (e.g., <NUM> V in <NUM> process technology). In this manner, the switch is capable of receiving and providing relatively high voltages in relatively small process technologies while mitigating the reliability challenges described above.

<FIG> is a conceptual block diagram of a switch <NUM>, in accordance with various examples. The switch <NUM> may be implemented in any suitable circuit, such as an analog circuit (e.g., analog signal chain) in a system-on-chip (SOC). The switch <NUM> may be a relatively high voltage switch (e.g., capable of receiving and providing <NUM> V or more) implemented in a circuit, device, or system manufactured using a relatively small process technology, such as <NUM>, that uses relatively low maximum voltage levels (e.g., <NUM> V). The switch <NUM> mitigates the reliability challenges described above by not providing inappropriately high voltages to the various nodes of the switch <NUM>. For example, the switch <NUM> may include drain-extended transistors that are capable of withstanding relatively high voltages from drain to source, drain to gate, and drain to bulk, and thus the switch <NUM> may enable drains of such drain-extended transistors to encounter such high voltages. Conversely, the switch <NUM> may avoid applying such high voltages from, e.g., gate to source, gate to bulk, or source to bulk, as well as drain to source, drain to gate, and drain to bulk in non-drain extended transistors.

In examples, the switch <NUM> includes a switching circuit <NUM>, which, in turn, includes transistors <NUM>, <NUM>, <NUM>, and <NUM>. Various components of the switch <NUM>, such as the transistors <NUM>, <NUM>, <NUM>, and <NUM>, are shown as blocks to indicate that those components may be of any suitable type, size, arrangement, etc. For example, the transistor <NUM> may be a field effect transistor (FET) or other type of transistor, be an n-type or p-type FET, have any of a variety of sizes and connections to adjacent circuitry, etc. In examples, the transistors <NUM> and <NUM> are of the same type (e.g., both are n-type FETs), and the transistors <NUM> and <NUM> are of the same type (e.g., both are p-type FETs). In examples, the transistors <NUM>, <NUM>, <NUM>, and <NUM> are drain-extended transistors, with the drains of the transistors <NUM> and <NUM> directly coupled to a switch input <NUM>, and with the drains of the transistors <NUM> and <NUM> directly coupled to a switch output <NUM>.

The switch <NUM> receives input voltages on the switch input <NUM> and provides output voltages on the switch output <NUM>. Because the transistors <NUM> and <NUM> have extended drains coupled directly to the switch input <NUM>, relatively high input voltages do not damage or render unreliable the transistors <NUM> and <NUM>. Similarly, because the transistors <NUM> and <NUM> have extended drains coupled directly to the switch output <NUM>, relatively high output voltages do not damage or render unreliable the transistors <NUM> and <NUM>. The switch output and inputs are interchangeable.

The transistors <NUM> and <NUM> are coupled to each other by way of a node <NUM>. For example, the node <NUM> is coupled to gates of the transistors <NUM> and <NUM>. The transistors <NUM> and <NUM> are coupled to each other by way of a node <NUM>. For example, the node <NUM> is coupled to gates of the transistors <NUM> and <NUM>. The transistors <NUM> and <NUM> (e.g., sources of the transistors <NUM> and <NUM>) may also be coupled to each other by way of node <NUM>, and the transistors <NUM> and <NUM> (e.g., sources of the transistors <NUM> and <NUM>) may be coupled to each other by way of node <NUM>.

The switching circuit <NUM> operates to regulate the provision of the input voltage on switch input <NUM> to the switch output <NUM>. For example, if the switch <NUM> is controlled to be in an off state (as described below), the transistors of the switching circuit <NUM> are all off (e.g., in cutoff mode), and thus the input voltage on switch input <NUM> has no pathway to the switch output <NUM>. Thus, the switch <NUM> is off. Similarly, for example, if the switch <NUM> is controlled to be in an on state (as described below), the transistors of the switching circuit <NUM> are selectively controlled to be on (e.g., in a linear or saturation mode), and thus the input voltage on switch input <NUM> has a pathway to the switch output <NUM>. The transistors in the switching circuit <NUM> are controlled in part by the input voltage on the switch input <NUM>, and thus the pairs of transistors that are on and that are off also depend on the input voltage on the switch input <NUM>. When the switch <NUM> is in an on state, depending on the voltage level at switch input <NUM>, the pair of transistors <NUM>, <NUM> may be on while the pair of transistors <NUM>, <NUM> is off, or the pair of transistors <NUM>, <NUM> may be off while the pair of transistors <NUM>, <NUM> is on, or all of the transistors <NUM>, <NUM>, <NUM> and <NUM> may be on. In some examples, the pair of transistors <NUM>, <NUM> is on and the pair of transistors <NUM>, <NUM> is off when the input voltage on the switch input <NUM> is in a first range (e.g., <NUM> V to <NUM> V), and the pair of transistors <NUM>, <NUM> is off and the pair of transistors <NUM>, <NUM> is on when the input voltage on the switch input <NUM> is in a second range (e.g., <NUM> V to <NUM> V). In some examples, there may be an overlap between the two ranges, such as in the range <NUM> V to <NUM> V, where both pairs of transistors are on. These ranges may be controlled at least in part by selecting transistors with specific threshold voltages. When the switch <NUM> is in the on state, for proper functionality of the switch <NUM>, the voltage drop across the drain-to-source of the transistors <NUM> and <NUM>, across the drain-to-source of the transistors <NUM> and <NUM>, or across the drain-to-source of all of these transistors must be very small. This enforces a constraint on the voltage requirement in the gate node of the devices (e.g., nodes <NUM> and <NUM>). To ensure proper device reliability, the voltage difference between nodes <NUM> and <NUM> and nodes <NUM> and <NUM> is maintained below the process limit of <NUM>. 8V, even when the voltages on switch inputs/outputs <NUM>, <NUM> and nodes <NUM>, <NUM> can be higher than <NUM>. Because the channel formed in a transistor, such as a FET, depends on the voltage across particular terminals of the transistor (e.g., gate and source), the input voltage at the switch input <NUM> is not the sole determinant of the range in which the two different pairs of transistors are turned on or off. In particular, the voltages at the gates of the transistors in the switching circuit <NUM>, in tandem with the voltages at the sources of these transistors, determine the gate to source voltages across the transistors and, thus, whether the transistors are turned on or turned off. When the switch <NUM> is on, the gate voltages of the transistors <NUM> and <NUM> are determined by a control input <NUM>, and the gate voltages of the transistors <NUM> and <NUM> are maintained at a fixed level below the source voltages of the transistors <NUM> and <NUM> by circuitry <NUM>. Specifically, the circuitry <NUM> maintains the voltage provided at node <NUM> on the gates of the transistors <NUM> and <NUM> a predefined amount lower than the voltages at the sources of the transistors <NUM> and <NUM>, thereby keeping the transistors <NUM> and <NUM> turned on until the voltage at the sources of the transistors <NUM> and <NUM> drops so low that the voltage provided by the circuitry <NUM> on node <NUM> is at ground. The node <NUM> saturates at ground, thereby defining the lowest source voltage that will cause transistors <NUM> and <NUM> to be on. The circuitry <NUM> may be adjusted such that the voltage that the circuitry <NUM> provides at node <NUM> is not so low relative to the voltage on the sources of the transistors <NUM>, <NUM> that the gate to source voltage is inappropriately high and causes the reliability problems described above.

The switch <NUM> also includes switches (e.g., transistors) <NUM>, <NUM>, <NUM>, and <NUM>. These switches are controlled by a control signal at control input <NUM>. When the control signal at control input <NUM> is in a first state, the switches <NUM>, <NUM>, and <NUM> open and the switch <NUM> closes. Conversely, when the control signal at control input <NUM> is in a second state, the switches <NUM>, <NUM>, and <NUM> close and the switch <NUM> opens. Closing the switches <NUM>, <NUM>, and <NUM> and opening the switch <NUM> causes the switch <NUM> to be in an off state, because the closed switches <NUM>, <NUM> cause a high voltage from a voltage supply <NUM> to be provided to both the gates and sources of the transistors <NUM>, <NUM>, thereby keeping the transistors <NUM>, <NUM> off and denying the input voltage on the switch input <NUM> a pathway to the switch output <NUM>. In addition, because the gates and sources of the transistors <NUM>, <NUM> are pulled up to approximately the same voltages, the gate to source voltage across each of the transistors <NUM>, <NUM> is kept low enough to mitigate any reliability problems that could otherwise arise. Further, when the switch <NUM> is closed, the gates and sources of the transistors <NUM>, <NUM> are pulled low to ground <NUM>, thereby turning off the transistors <NUM>, <NUM> and denying the input voltage on the switch input <NUM> a pathway to the switch output <NUM>. Because the input voltage on the switch input <NUM> has no pathway to the switch output <NUM>, the switch <NUM> is off. In this scenario, the state of the switch <NUM> is not relevant to whether the switch <NUM> is on or off.

When the control signal on control input <NUM> is in such a state that the switches <NUM>, <NUM>, and <NUM> are open, the input voltage on switch input <NUM>, the voltage of the control signal applied to node <NUM>, and the voltage provided by circuitry <NUM> to node <NUM> together control the operation of the transistors in the switching circuit <NUM>, as described above. Further, the switch <NUM> is closed, enabling bias current source <NUM> to provide current through the circuitry <NUM>, which, in turn, enables circuitry <NUM> to step down the input voltage from switch input <NUM> to a target voltage on node <NUM>. Accordingly, when the control signal on control input <NUM> causes the switches <NUM>, <NUM>, and <NUM> to open and switch <NUM> to close, the switch <NUM> is on.

The switch <NUM> also includes a bias current source <NUM> coupled to the circuitry <NUM>. The bias current source <NUM> maintains a constant flow of current through a transistor in the circuitry <NUM>, thereby maintaining a channel in that transistor and keeping it on. By keeping that transistor on, the transistor is protected from relatively high voltages from gate to bulk that may cause damage or reliability challenges. The circuitry <NUM> may include additional components as described below.

<FIG> is a schematic circuit diagram of the switch <NUM>, in accordance with various examples. The switch <NUM> is not limited in scope to the example of <FIG>. <FIG> is a simplified view of the circuit diagram of <FIG> with certain open switches illustrated as open circuits and certain closed switches illustrated as closed circuits. <FIG> and <FIG> are thus described in parallel. The example switch <NUM> of <FIG> includes drain-extended transistors <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. The pair of transistors <NUM> and <NUM> are n-type FETs, and the pair of transistors <NUM> and <NUM> are p-type FETs. The drains of the transistors <NUM> and <NUM> are coupled to the switch input <NUM>. The drains of the transistors <NUM> and <NUM> are coupled to the switch output <NUM>. The gates of the transistors <NUM> and <NUM> are coupled to each other at node <NUM>, and the gates of the transistors <NUM> and <NUM> are coupled to each other at node <NUM>. Control input <NUM> is coupled to node <NUM> and to switch <NUM> as a control for switch <NUM>. Switch <NUM> is coupled between node <NUM> and ground <NUM>.

The bulk and source of the transistor <NUM> are coupled together. The bulk and source of the transistor <NUM> are coupled together. These bulk connections are established because p-type FETs (e.g., transistors <NUM>, <NUM>) have parasitic diodes between the source and bulk terminals and between the drain and bulk terminals. To ensure that no current flows through these diodes, the bulk voltage must be greater than or equal to the source and drain voltages. By connecting the bulk and source terminals, the bulk and source terminal voltages are made equal, and because the source voltage is always greater than or equal to the drain voltage, the bulk voltage is likewise greater than or equal to the drain voltage. The sources of the transistors <NUM>, <NUM> are coupled to node <NUM>. Node <NUM> is coupled to switch <NUM>, which, in turn, is coupled to voltage supply <NUM>. Node <NUM> is coupled to switch <NUM>, which, in turn, is coupled to voltage supply <NUM>. The switches <NUM> and <NUM> are coupled to and controlled by control input <NUM>.

An example circuitry <NUM> includes a drain-extended transistor <NUM> (e.g., an n-type FET). A gate of the transistor <NUM> is coupled to node <NUM>. A drain of the transistor <NUM> is coupled to the voltage supply <NUM>. A source of the transistor <NUM> is coupled to a node <NUM>. The node <NUM> is coupled to a resistor <NUM>, which is coupled to a node <NUM>. A switch <NUM> is coupled between the node <NUM> and node <NUM>, and the switch <NUM> is controlled by control input <NUM>. Node <NUM> is coupled to a bias current source <NUM> (e.g., <NUM> micro amps), and the bias current source <NUM> is coupled to the switch <NUM>. The control input <NUM> controls the switch <NUM>. The switch <NUM> is coupled to the ground <NUM>. The bias current source <NUM> (e.g., <NUM> micro amps) is coupled to the node <NUM> and to ground <NUM>.

In operation, when the control input <NUM> is driven low, the switch <NUM> is off, because the switches <NUM>, <NUM>, and <NUM> are closed. Closing the switches <NUM>, <NUM> pulls up nodes <NUM> and <NUM>, which results in the gates and sources of the transistors <NUM>, <NUM> having approximately equal voltages. Consequently, the gate to source voltage across each of the transistors <NUM>, <NUM> is approximately zero, and, in any event, inadequate to turn on the transistors <NUM>, <NUM>. Thus, the input voltage on the switch input <NUM> is unable to reach the switch output <NUM> by way of the transistors <NUM>, <NUM>. Furthermore, when the control input <NUM> is driven low, the switch <NUM> is closed and node <NUM> is pulled to ground <NUM>. Pulling node <NUM> to ground <NUM> results in the sources of transistors <NUM>, <NUM> being pulled to ground <NUM>. Furthermore, when the control input <NUM> is driven low, the node <NUM> and gates of the transistors <NUM>, <NUM> are also low. Thus, the gate to source voltage on each of the transistors <NUM>, <NUM> is inadequate to turn on the transistors <NUM>, <NUM>. Consequently, the input voltage on switch input <NUM> does not have a path to the switch output <NUM> by way of the transistors <NUM>, <NUM>. The switch <NUM> is thus considered to be off.

When the control input <NUM> is driven high, the switch <NUM> is on, and the switches <NUM>, <NUM>, and <NUM> are open. Consequently, node <NUM> is not coupled to ground <NUM>, node <NUM> is not coupled to voltage supply <NUM>, and node <NUM> is not coupled to voltage supply <NUM>. As a result, the voltages on nodes <NUM> and <NUM> are determined by the input voltage on switch input <NUM>. The voltage on node <NUM> is equal to the lesser of the voltage on switch input <NUM> and the voltage on node <NUM>, minus the threshold voltage of transistor <NUM>, and the voltage on node <NUM> is equal to the greater of the voltage on switch input <NUM> and the absolute value of the threshold voltage of transistor <NUM>. The voltage on the gate of transistor <NUM> is the voltage on control input <NUM> (e.g., <NUM> V), and the voltage on the source of transistor <NUM> is the input voltage on switch input <NUM>. So long as the input voltage on switch input <NUM> is low enough that the gate to source voltage across transistor <NUM> is greater than the threshold voltage of transistor <NUM>, transistor <NUM> is on. The same rationale applies to transistor <NUM>. Thus, there is an input voltage range over which the transistors <NUM> and <NUM> are on. In some examples, this range is approximately <NUM> V to <NUM> V, as <NUM> V on node <NUM> minus a threshold voltage of <NUM> V is <NUM> V. Other voltage ranges are contemplated and included in the scope of this disclosure.

Continuing with the examples in which the input voltage range over which the pair of transistors <NUM>, <NUM> are on is <NUM> V to <NUM> V, the transistors <NUM> and <NUM> are unable to stay on for input voltages above this input voltage range. Consequently, the transistors <NUM> and <NUM> do not provide a pathway between the switch input <NUM> and switch output <NUM> above this input voltage range. The transistors <NUM> and <NUM> are useful to provide a pathway between the switch input <NUM> and switch output <NUM> for input voltages above the range of <NUM> V to <NUM> V. To turn on the transistors <NUM> and <NUM>, an appropriate gate to source voltage should be present across the transistors <NUM> and <NUM>. If the transistors <NUM> and <NUM> are p-type FETs, the source voltage should exceed the gate voltage by the threshold voltage of the transistors <NUM> and <NUM>. To achieve such a gate to source voltage, the circuitry <NUM>-and more specifically, the transistor <NUM> and resistor <NUM>-steps down the voltages present at the sources of the transistors <NUM>, <NUM> (e.g., on node <NUM>) and provides the stepped-down voltage to the gates of the transistors <NUM>, <NUM> on node <NUM>. In an example, the transistor <NUM> reduces the input voltage on node <NUM> by a threshold voltage of the transistor <NUM>, and the resistor <NUM> reduces the voltage provided by the transistor <NUM> (e.g., by the product of the current flowing through the resistor <NUM> and the resistance of the resistor <NUM>) to produce the voltage that is applied to the gates of the transistors <NUM>, <NUM> on node <NUM>. In this manner, the circuitry <NUM> keeps the transistors <NUM>, <NUM> on regardless of how high the input voltage on switch input <NUM> goes. However, the voltage on node <NUM> saturates at ground, meaning that the voltage on node <NUM> does not drop below <NUM> V. Thus, the lowest input voltage at which the circuitry <NUM> can keep the transistors <NUM>, <NUM> on is <NUM> V plus the voltage drop across the resistor <NUM> plus the threshold voltage of the transistor <NUM>. In examples, the input voltage range over which the transistors <NUM>, <NUM> remain on is from approximately <NUM> V to <NUM> V, although the range may vary depending on the current flowing through the resistor <NUM>, the resistance of the resistor <NUM>, the threshold voltage of the transistor <NUM>, and potentially other factors, such as additional circuitry that may be included in the circuitry <NUM>.

When the switch is on as described above, the switches <NUM> and <NUM>-unlike the switches <NUM>, <NUM>, and <NUM>-are closed. Closing the switch <NUM> provides a pathway for the voltage formed by the circuitry <NUM> to be provided to the node <NUM>. Closing the switch <NUM> causes the bias current source <NUM> to be introduced into the circuit. The current provided by the bias current source <NUM> flows through the resistor <NUM> and affects the voltage drop across the resistor <NUM>, and, hence, the voltage applied on node <NUM> to control the transistors <NUM>, <NUM>. As described above, the bias current source <NUM> (e.g., <NUM> micro amps) maintains a channel in the transistor <NUM> regardless of the gate to source voltage across the transistor <NUM>, thereby maintaining the integrity of the transistor <NUM> when high voltages are applied to the transistor <NUM> (e.g., gate to bulk).

<FIG> is a schematic circuit diagram of the switch <NUM>, in accordance with various examples. The example switch <NUM> of <FIG> is non-limiting and differs from the switch <NUM> of <FIG> by replacing the resistor <NUM> and the switch <NUM> with a single transistor <NUM> (e.g., a p-type FET). The transistor <NUM> replaces the functionality of the switch <NUM> because the gate of the transistor <NUM> is coupled to the drain of the transistor <NUM>, such that the gate and drain voltages are pulled up to the voltage supply <NUM> when the switch <NUM> is closed and the switch <NUM> is off. The voltage at the source of transistor <NUM> is pulled up to the voltage supply <NUM> by way of the switch <NUM>, except that it is stepped down by a threshold voltage of the transistor <NUM>. Thus, the source voltage of the transistor <NUM> is less than the gate voltage of the transistor <NUM>, and so the transistor <NUM> is off (e.g., open circuit). When the switch <NUM> is on, the voltage on node <NUM> is at least a threshold voltage less than the voltage on node <NUM>, and thus the gate to source voltage of transistor <NUM> is adequately low to cause the transistor <NUM> to be on. When the switch <NUM> is on, the transistor <NUM> behaves as a resistor, e.g., the resistor <NUM> of <FIG>. In some examples, the circuit of <FIG> may be modified to omit the current source <NUM> and to couple the source of transistor <NUM> to the bulk of transistor <NUM>. In some examples, each of the n-type FETs in the circuit of <FIG> may be replaced by p-type FETs, and each of the p-type FETs in the circuit of <FIG> may be replaced by n-type FETs, such that a source follower-based boost circuit is coupled to the n-type FET pair instead of to the p-type FET pair as is the case in <FIG>. In yet other examples, a source-follower based-boost circuit such as that coupled to the p-type FET pair in <FIG> may be coupled to both the p-type FET pair and the n-type FET pair, with the transistor types in the boost circuit selected as described above (e.g., relative to the source-follower-based boost circuit coupled to the p-type FET pair shown in <FIG>, the p-type FETs are replaced by n-type FETs and n-type FETs are replaced by p-type FETs in the boost circuit that is coupled to the n-type FET pair). <FIG> is a simplified view of the circuit diagram of <FIG>, with certain open switches shown as open circuits and with certain closed switches shown as closed circuits.

<FIG> is a schematic circuit diagram of the switch <NUM>, in accordance with various examples. More specifically, <FIG> shows example components (e.g., transistors) that may be used to implement the switches <NUM>, <NUM>, <NUM>, and <NUM> of <FIG> and the bias current source <NUM> of <FIG>, as well as various other components that are useful to implement the switch <NUM>. For example, the switch <NUM> of <FIG> may include a pair of transistors <NUM> and <NUM>. The transistor <NUM> may be a p-type FET and the transistor <NUM> may be a p-type drain-extended FET. A source of the transistor <NUM> is coupled to the voltage supply <NUM>, and a drain of the transistor <NUM> is coupled to a source of the transistor <NUM>. A drain of the transistor <NUM> is coupled to node <NUM>. For example, the switch <NUM> of <FIG> may include a pair of transistors <NUM> and <NUM>. The transistor <NUM> may be a p-type FET and the transistor <NUM> may be a p-type drain-extended FET. A source of the transistor <NUM> is coupled to the voltage supply <NUM>, and a drain of the transistor <NUM> is coupled to a source of the transistor <NUM>. A drain of the transistor <NUM> is coupled to node <NUM>. In some examples, only one of the transistors <NUM>, <NUM> of the switch <NUM> is included and the other is omitted as it is useful for mitigating current leakage. In some examples, only one of the transistors <NUM>, <NUM> of the switch <NUM> is included and the other is omitted as it is useful for mitigating current leakage. In some examples, the drain-extended transistors <NUM>, <NUM> are included and the non-drain-extended transistors <NUM>, <NUM> are omitted. Control input <NUM> is coupled to the gates of the transistors <NUM>, <NUM>, <NUM>, and <NUM>.

In examples, the bias current source <NUM> includes a transistor <NUM> coupled to a resistor <NUM>. In examples, the transistor <NUM> is an n-type drain-extended FET having a source that is coupled to the resistor <NUM>. Together, the transistor <NUM> and the resistor <NUM> are sized appropriately to produce a target bias current (e.g., <NUM> micro amps). In examples, a bias voltage supply is coupled to a gate of the transistor <NUM> to control the transistor <NUM>, for example, to keep the transistor <NUM> on.

In examples, the switch <NUM> includes a transistor <NUM>, such as an n-type FET. The transistor <NUM> may have a drain coupled to the resistor <NUM> and a source coupled to ground <NUM>. The gate of the transistor <NUM> is coupled to control input <NUM>.

In examples, the switch <NUM> includes a transistor <NUM>, such as a p-type FET having a source coupled to the node <NUM> and a drain coupled to the source of transistor <NUM>. The gate of the transistor <NUM> is coupled to the node <NUM>, and the bulk of the transistor <NUM> is coupled to the source of the transistor <NUM> and the bulk of the transistor <NUM>. The transistor <NUM> has a larger threshold voltage than transistor <NUM>, such that the sub-threshold leakage current of the transistor <NUM> is less than that of transistor <NUM>. Further, the switch output <NUM> may reach relatively low voltage levels (e.g., <NUM> V), and transistor <NUM> is a drain-extended transistor that protects the drain of transistor <NUM>, which may not be able to tolerate <NUM> V. Accordingly, the transistor <NUM> is able to mitigate leakage current.

In examples, the switch <NUM> includes a transistor <NUM>, such as an n-type drain-extended FET having a drain coupled to switch output <NUM>. The switch <NUM> also includes a transistor <NUM>, such as an n-type FET having a drain coupled to a source of the transistor <NUM> and a source coupled to ground <NUM>. The transistors <NUM>, <NUM> mitigate leakage current and may be controlled by any suitable circuitry or logic <NUM>. Specifically, the transistor <NUM> has a larger threshold voltage than transistor <NUM>, such that the sub-threshold leakage current of the transistor <NUM> is less than that of transistor <NUM>. In addition, the switch output <NUM> may reach relatively high voltage levels (e.g., <NUM> V), and transistor <NUM> is a drain-extended transistor that protects the drain of transistor <NUM>, which may not be able to tolerate <NUM> V.

The switch <NUM> includes a transistor <NUM>, such as an n-type drain-extended FET. The transistor <NUM> includes a drain coupled to the node <NUM> and a source coupled to ground <NUM>.

The operation of the switch <NUM> as shown in <FIG> is similar to that described above with reference to <FIG>. Thus, the operation of the switch <NUM> is not repeated here. <FIG> is a schematic circuit diagram of the example switch <NUM> of <FIG> in an on state, in accordance with various examples. <FIG> is a schematic circuit diagram of the example switch <NUM> of <FIG> in an off state, in accordance with various examples.

<FIG> is a set of graphs <NUM>, <NUM>, and <NUM> depicting voltages at various nodes in an example switch <NUM> as a function of time, in accordance with various examples. Each of the graphs <NUM>, <NUM>, and <NUM> includes time (in nanoseconds (ns)) on the x-axis and voltage on the y-axis. Graph <NUM> includes curves <NUM>, <NUM>, and <NUM>, where curve <NUM> depicts the voltage over time on the node <NUM>, curve <NUM> depicts the voltage over time on the node <NUM>, and curve <NUM> depicts the voltage over time on the node <NUM>. In graph <NUM>, curve <NUM> depicts the voltage over time on the switch input <NUM>, and curve <NUM> depicts the voltage over time on the switch output <NUM>. In graph <NUM>, both of the curves <NUM> and <NUM> depict the voltage over time for control input <NUM> as the control input <NUM> is applied to various transistors in the switch <NUM>. As curves <NUM> and <NUM> depict, in some examples, the control input <NUM> may be implemented using different voltage ranges. For example, although the control input <NUM> may be high, different voltages may be used to implement a high signal, such as <NUM> V (curve <NUM>) and <NUM> V (curve <NUM>). Conversely, although the control input <NUM> may be low, different voltages may be used to implement a low signal on different transistors, such as <NUM> V (curve <NUM>) and <NUM> V (curve <NUM>).

The behavior of the curves is now described. Curves <NUM> and <NUM> depict the turning on and off of the switch <NUM>. Curves <NUM> and <NUM> behave in parallel, meaning that both curves <NUM> and <NUM> are high at the same time and are low at the same time. Curves <NUM> and <NUM> depict the switch <NUM> being off from <NUM> ns to <NUM> ns, on from <NUM> ns to <NUM> ns, off from <NUM> ns to <NUM> ns, on from <NUM> ns to <NUM> ns, and off from <NUM> ns to <NUM> ns. As curve <NUM> shows when compared to curves <NUM> and <NUM>, whenever the switch <NUM> is off, the output voltage on switch output <NUM> is <NUM> V. As the time frame <NUM> ns to <NUM> ns shows, even when the switch <NUM> is on (as curves <NUM> and <NUM> depict), the output voltage on switch output <NUM> (curve <NUM>) remains <NUM> V because the input voltage on switch input <NUM> (curve <NUM>) is <NUM> V. The only time period depicted in <FIG> during which the output voltage (curve <NUM>) rises above <NUM> V is when the switch <NUM> is on (curves <NUM> and <NUM>) and the input voltage is high (curve <NUM>), except that the output voltage (curve <NUM>) remains high for a short time (approximately <NUM> nanoseconds) after the switch <NUM> (curves <NUM> and <NUM>) is turned off. Specifically, when the switch <NUM> turns off at <NUM> ns, the output node of the switch <NUM> is in a high impedance state in which the output voltage is held by the residual capacitance of the output node. This time period is <NUM> ns to <NUM> ns.

Curves <NUM>, <NUM>, and <NUM> depict the behavior of voltages that are useful to achieve the output voltage curve <NUM>. As the switch <NUM> is turned on, the switches <NUM> and <NUM> are opened, and thus the voltages on nodes <NUM> (curve <NUM>) and <NUM> (curve <NUM>) begin to fall in the <NUM> ns to <NUM> ns time frame. Because the voltage on node <NUM> relies on the voltage on nodes <NUM> and <NUM>, the curve <NUM> also follows curves <NUM> and <NUM>, as shown. While the switch <NUM> is on and no input voltage is provided to the switch <NUM>, the output voltage of the switch <NUM> remains low (curve <NUM>) and the voltages on the nodes <NUM>, <NUM>, and <NUM> also remain low (curves <NUM>, <NUM>, and <NUM> from approximately <NUM> ns to <NUM> ns). When the switch <NUM> is turned off at <NUM> ns, the switches <NUM>, <NUM> are closed, and the nodes <NUM>, <NUM>, and <NUM> are pulled up to the voltage supply <NUM>, as curves <NUM>, <NUM>, and <NUM> show at <NUM> ns. While the switch <NUM> remains off, the curves <NUM>, <NUM>, and <NUM> remain high, as the time frame <NUM> ns-<NUM> ns shows. At <NUM> ns, the switch <NUM> is turned on (curves <NUM>, <NUM>) and a high input voltage (curve <NUM>) is provided to the switch <NUM>. Consequently, the switches <NUM>, <NUM> open, and thus the nodes <NUM>, <NUM>, and <NUM> are no longer pulled up to the voltage supply <NUM>. However, the voltages on nodes <NUM>, <NUM>, and <NUM> do not drop as low as they did in the <NUM> ns to <NUM> ns time frame. Instead, they drop only slightly, as they are now pulled up by the input voltage to the switch <NUM> at switch input <NUM>. Curves <NUM> and <NUM> show this behavior. Curve <NUM> decreases lower than curves <NUM> and <NUM>, because the voltage on node <NUM> (curve <NUM>) is stepped down by the transistors <NUM>, <NUM> as described above. As the difference between the curves <NUM>, <NUM> increases, the transistors <NUM>, <NUM> turn on, and the output voltage provided on the switch output <NUM> (curve <NUM>) increases, as shown. The operation shown in <FIG> is primarily dependent on the transistors <NUM>, <NUM> to provide a pathway from the switch input <NUM> to the switch output <NUM>, because the input voltage on switch input <NUM> is relatively high (approximately <NUM> V). Had the input voltage been in a lower range (e.g., <NUM> V), the transistors <NUM>, <NUM> may have been turned on and provided a pathway between the switch input <NUM> and the switch output <NUM>, as described in detail above.

<FIG> is a block diagram of a semiconductor package <NUM> covering a system-on-chip (SOC) having an analog signal chain coupled to a switch, in accordance with various examples. <FIG> is a top-down view of the package <NUM>. <FIG> shows semiconductor package <NUM> as a dual-inline, gullwing style package, but the scope of disclosure includes any suitable type of package, such as ball grid array (BGA) packages, quad flat no lead (QFN) packages, etc. In examples, the package <NUM> includes a die (or chip) <NUM>. The die <NUM> may be coupled to a die pad using a die attach material, for example. The die <NUM> includes circuitry formed in and on an active surface of the die <NUM>, such as an analog signal chain <NUM>. The analog signal chain <NUM> includes various analog circuits that are configured to perform one or more tasks. The analog signal chain <NUM> is coupled to a switch <NUM>. For example, the switch <NUM> is any example of the switch <NUM> described herein. The analog signal chain <NUM> is coupled to a bond pad <NUM> by way of a conductive member <NUM>, such as a metal trace, via the switch <NUM>. A bond wire <NUM> is coupled to the bond pad <NUM> (e.g., by way of a solder ball) and to a pin <NUM>. The pin <NUM> is exposed to an exterior of the package <NUM> and may be useful to conduct signals to and from the die <NUM>. A mold compound <NUM> covers the die <NUM>, the contents of the die <NUM>, and the bond wire <NUM>.

The term "couple" is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

A device that is "configured to" perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.

While certain components may be described herein as being of a particular process technology, these components may be exchanged for components of other process technologies. Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

Claim 1:
A switch, comprising:
a switch input (<NUM>);
a switch output (<NUM>);
a first pair of drain-extended transistors (<NUM>, <NUM>) of a first conduction type connected in series and coupled to the switch input (<NUM>) and the switch output (<NUM>), the first pair of drain-extended transistors (<NUM>, <NUM>) configured to provide a voltage from the switch input (<NUM>) to the switch output responsive to the switch being on and the voltage being in a first range;
a second pair of drain-extended transistors (<NUM>, <NUM>) of a different conduction type than the first conduction type connected in series and coupled to the switch input (<NUM>) and the switch output (<NUM>), the second pair of drain-extended transistors (<NUM>, <NUM>) configured to provide a voltage from the switch input (<NUM>) to the switch output (<NUM>) responsive to the switch being on and the voltage being in a second range different from the first range;
a transistor coupled between sources and gates of the second pair of drain-extended transistors (<NUM>, <NUM>), the transistor configured to provide a gate voltage on the gates of the second pair of drain-extended transistors (<NUM>, <NUM>) that is a fixed amount less than a voltage on the switch input (<NUM>); and
a control input coupled to:
gates of the first pair of drain-extended transistors (<NUM>, <NUM>);
a first switch (<NUM>) coupled to sources of the first pair of drain-extended transistors (<NUM>, <NUM>);
a second switch (<NUM>) coupled between a voltage supply and gates of the second pair of drain-extended transistors (<NUM>, <NUM>); and
a third switch (<NUM>) coupled between the voltage supply and sources of the second pair of drain-extended transistors (<NUM>, <NUM>).