Patent Description:
Integrated circuits (ICs) are generally tested for faults. Logic circuits are commonly tested using a method often referred to as scan testing. During scan testing, patterns are shifted in through one or more chains of flip-flops (also referred to as a scan chains) to stimulate one or more logic circuits. Results from the stimulated logic circuits are loaded into the scan chains and are shifted out for evaluation. When the shifted out patterns match expected patterns (based on proper functionality of the one or more logic circuits), then no faults are detected. When the shifted out patterns do not match the expected patterns, then faults are detected.

<FIG> shows exemplary launch-on-capture (LOC) waveforms of scan chain clock signal clk and scan enable signal scan_en. As shown in <FIG>, when scan_en is in a high state, data (also referred to as test vectors, test patterns, vectors, or patterns) shifts into the scan chain each time clock signal clk pulses. When scan enable signal scan_en transitions to a low state, the first pulse of clock signal clk causes the logic circuits having inputs coupled to the scan chain to transition in a step generally referred to as launch. The second pulse of clock signal clk causes the loading of the outputs of the stimulated logic circuits into flip-flops of the scan chain. Once scan enable signal scan_en transitions to the high state, data in the scan chain shifts out each time clock signal clk pulses. The data shifted out is then evaluated for faults.

The launch and capture clock pulses may be performed at-speed so that the logic circuits are tested for faults related to transition delays.

As can be seen in <FIG>, LOC testing allows for shifting data into or out of the scan chain at slow speed while still performing at-speed testing of the logic circuits. Thus, in some implementations, LOC testing may allow for an easier implementation of the scan circuit (compared with LOS testing) since the scan enable signal scan_en transition may be slow.

<FIG> shows exemplary launch-on-shift (LOS) waveforms of scan chain clock signal clk and scan enable signal scan_en. As shown, LOS testing is very similar to LOC testing. However, LOS testing performs the launch operation during the last shift pulse of clock signal clk. Thus, as shown in <FIG>, scan enable signal scan_en transitions to the low state after the last shift pulse of clock signal clk but before the capture pulse of clock signal clk.

In a similar manner as in LOC testing, LOS testing may be performed at-speed. Thus, in some implementations, the scan enable signal scan_en implementation is designed to transition fast enough to allow for at-speed testing during LOS.

As can be seen in <FIG>, in some implementations, LOS testing may allow for faster test time (compared with LOC testing) since LOS testing uses the clock pulse for the last shift for both shifting data through the scan chain and for the launch operation.

<FIG> shows exemplary pipeline LOS waveforms of scan chain clock signal clk, scan enable signal scan_en and internal scan enable signal internal_scan_en. As shown, pipeline LOS testing is a mixture of both LOC and LOS testing. For example, pipeline LOS is similar to LOC since it performs at-speed launch and capture operations with external scan enable signal "scan_en" low. Pipeline LOS is similar to LOS since it performs the launch operation during the last shift pulse of clock signal clk. However, pipeline LOS relies on internal scan enable signal "internal_scan_en" (e.g., forced high) instead of external scan enable signal "scan_en" for the capture operation, where the internal scan enable signal may be delayed (e.g., gated) based, e.g., on timing design constraints. So pipeline LOS testing may allow for faster test time (compared with LOC testing) since pipeline LOS testing uses the clock pulse with internal scan enable for the last shift for both shifting data through the scan chain and for the launch operation, and may allow for easier implementation than LOS testing since timing considerations for scan enable signal scan_en may be relaxed.

In some implementations, the internal scan enable signal internal_scan_en may transition from '<NUM>' to '<NUM>' on the negative edge of the launch clock pulse instead of on the positive edge of the launch clock pulse (as shown in <FIG>).

Scan testing, e.g., with implementations as illustrated in <FIG>, may be implemented in an automated test equipment (ATE), where, e.g., the ATE provides the test vectors to the IC and evaluates the results (data shifted out) for determining faults. Scan testing may also be performed as a logic built-in-self-test (LBIST), where the IC applies the test vectors to itself (e.g., using a pseudorandom number generator) and determines whether a fault occurred by using an LBIST controller of the IC.

Document <CIT> discloses an apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A third clocked flip-flop has a third flip-flop data input coupled to an inversion of the second flip-flop output, a third flip-flop scan-in input, a clock input coupled to the signal source, a scan enable input latched low, and a third flip-flop output, the third flip-flop inverting the third flip-flop data input at the third flip-flop output. A first AND gate has a first input coupled to an inversion of the scan enable signal, a second input coupled to the second flip-flop output, and a first AND gate output. A second AND gate has a first input coupled to the first AND gate output, a second input coupled to the third flip-flop output, and a second AND gate output coupled to a write enable signal enabling the SRAM Document <CIT> discloses a test point circuit that constitutes a scan chain, and captures, in one capture operation period of a clock sequential test, a first operation result in a second capture clock that comes after a first capture clock. Document <CIT> discloses an integrated circuit provided with a serial scan chain comprising partial scan cells where a fixed value is captured and stored during a scan mode in which serial data is being shifted into and out of serial scan cells.

A method for performing scan as claimed in claim <NUM> includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

An integrated circuit as claimed in claim <NUM> includes a plurality of logic circuits and a scan circuit. The integrated circuit is configured to: enter scan mode; receive a test pattern; apply the test pattern through a first scan chain of the scan circuit by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; and while applying the test pattern through the first scan chain, controlling a further scan flip-flop of the scan circuit with the first scan chain without transitioning a further scan enable input of the further scan flip-flop.

The making and using of the embodiments disclosed are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

The description below illustrates the various specific details to provide an in-depth understanding of several example embodiments according to the description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials and the like. In other cases, known structures, materials or operations are not shown or described in detail so as not to obscure the different aspects of the embodiments. References to "an embodiment" in this description indicate that a particular configuration, structure or feature described in relation to the embodiment is included in at least one embodiment. Consequently, phrases such as "in one embodiment" that may appear at different points of the present description do not necessarily refer exactly to the same embodiment. Furthermore, specific formations, structures or features may be combined in any appropriate manner in one or more embodiments.

Embodiments of the present invention will be described in a specific context, a scan circuit of an IC, a method for performing scan using LBIST or ATPG modes, and a method of modifying a scan circuit, e.g., after scan insertion. Embodiments of the present invention may be used in non-integrated circuits, such as circuits implemented in a printed circuit board (PCB). Some embodiments may be used with modes different from LBIST of ATPG and/or without modifying the scan circuit after scan insertion.

In an embodiment of the present invention, a scan circuit that includes a first scan chain provides controllability during scan to a logic circuit with an output of a further scan flip-flop that is not inside the first scan chain. The further scan flip-flop is operated without transitioning its scan enable signal (e.g., as similar to pipeline LOS mode but the further scan flip-flop SE remains '<NUM>' in both clk pulses (launch and capture) when scan_en = '<NUM>'). In some embodiments, the scan flip-flop can be incorporated inside the first scan chain (e.g., based on a selection signal) without changing the length of the first scan chain by replacing a given scan flip-flop of the first scan chain. When the further scan flip-flop is incorporated in the first scan chain, the replaced given scan flip-flop is operated without transitioning its scan enable signal (e.g., as similar to pipeline LOS mode but the replaced given scan flip-flop SE remains '<NUM>' in both clk pulses (launch and capture) when scan_en = '<NUM>'), e.g., to provide controllability to a logic circuit coupled to the replaced given scan flip-flop.

Scan circuits, which may include, e.g., one or more scan chains, test pattern compression and decompression circuits, and other circuits, are generally designed, e.g., to detect faults of the IC to be tested (often referred to as device under test, or DUT). In some applications, it is common practice to use automated test pattern generation (ATPG) technology to generate test patterns that maximize coverage and minimize execution time (often referred to as scan test time) while executing in a reliable and consistent manner.

In some ICs, both LBIST and ATPG may be implemented.

After scan insertion (e.g., once the scan circuit is implemented in the IC, together with other functional circuits of the IC, and timing closure has been performed), the scan circuit is generally capable of testing the IC using test patterns at a desired speed (e.g., at-speed).

It is not uncommon for changes to be performed to one or more logic circuits after scan insertion, which may be specified in an engineering change order (ECO). For example, logic circuits (which may include one or more flip-flops) may be added or modified after scan insertion, e.g., to fix design issues (often referred to as bugs), to add new functionality, or to remove features. For example, a logic circuit may be added after scan insertion for determining aging in the field.

When a logic circuit changes after scan insertion, it may not be covered by the already implemented scan circuit. The lack of coverage may be, e.g., due to no observability or no controllability. No observability may result from the changed logic circuit not providing an output to a flip-flop of the scan chain. No controllability may result from the changed logic circuit not having an input coupled to the scan chain so that the scan chain can (e.g., effectively) stimulate the changed logic circuit with the shifted data.

After a logic circuit change, the scan circuit may be modified to include additional flip-flops in the scan chain(s) to cover the changed logic circuit. Since adding new flip-flops to the scan chain(s) changes the length and/or flip-flop sequence of the scan chain(s), an LBIST controller, scan compressor and decompressor, and/or ATPG may be regenerated.

In some IC design flows, the scan circuit may be designed with additional dummy flip-flops in the scan chains so that they can be used in the event of a logic circuit change after scan insertion. In the event of a logic circuit change after scan insertion, the dummy flip-flops are rerouted so that the provide coverage to the changed logic circuit. But adding dummy flip-flops may unnecessarily increase the scan chain length if there is no logic circuit change after scan insertion. If there are not enough dummy flip-flops to accommodate for the logic circuit change after scan insertion, new scan flip-flops may need to be added to the scan chain(s) to provide scan coverage to the changed logic circuit, which may change the length and/or flip-flop sequence of the scan chain(s), an LBIST controller, scan compressor and decompressor, and/or cause ATPG to be regenerated.

In an embodiment of the present invention, a scan flip-flop that is not in a scan chain is controlled by the scan chain when in scan mode. The scan enable input terminal of the scan flip-flop that is not in the scan chain is kept asserted so that the scan flip-flop that is not in the scan chain operates in shift mode during scan. In some embodiments, the scan enable input terminal of the scan flip-flop that is not in the scan chain does not toggle during scan mode.

Advantages of some embodiments include the ability to control, during scan, a logic circuit that is not directly controlled by a scan flip-flop of a scan chain by using another scan flip-flop that is not in the scan chain, thereby advantageously allowing controllability of the logic circuit without interfering with the operation of the scan chain. Thus, some embodiments advantageously allow controllability of, e.g., a logic circuit added after scan insertion without adding scan flip-flops to the scan chain and, in some embodiments, without using dummy scan flip-flops of the scan chain.

<FIG> shows a portion of scan circuit <NUM>, according to an embodiment of the present invention. Scan circuit <NUM> includes scan chain <NUM>, which includes scan flip-flops <NUM>, <NUM>, <NUM>, and <NUM> for testing logic circuits <NUM>, <NUM>, <NUM>, and <NUM>. Scan circuit <NUM> also includes scan flip-flop <NUM> for controlling logic circuit <NUM>. It is understood that scan chain <NUM> may include additional scan flip-flops (not shown).

In some embodiments, scan chain <NUM> may operate in LOC mode. For example, when scan enable signal scan_en is asserted (e.g., high), scan flip-flops <NUM>, <NUM>, <NUM>, and <NUM>, perform a shift operation by outputting at their respective Q output data at their respective SI input during each pulse of clock signal clk. When scan enable signal scan_en deasserts (e.g., low), data at the respective D inputs of each scan flip-flops <NUM>, <NUM>, <NUM>, and <NUM> is outputted at their respective Q output during a pulse of clock signal clk. Thus, when scan enable signal scan_en is deasserted, outputs from logic circuits <NUM>, <NUM>, <NUM>, and <NUM> are captured in the scan flip flops <NUM>, <NUM>, <NUM>, and <NUM>. After capture, scan enable signal scan_en is asserted, thus causing a shift in scan chain <NUM> each pulse of clock signal clk.

Scan flip-flops of scan chain <NUM> may stimulate one or more logic circuits. As an example, logic circuits <NUM> and <NUM> are stimulated by outputs of scan flip-flops <NUM> and <NUM>, respectively. Other logic circuits may be coupled to outputs of one or more scan flip-flops of scan chain <NUM>. In some embodiments, some scan flip-flops may not have a logic circuit coupled to its output.

It is understood that logic circuits <NUM>, <NUM>, <NUM>, and <NUM>, may be stimulated (e.g., during the launch operation) by, e.g., other circuits, such as other scan chain flip-flops (not shown) of scan chain <NUM>, or another scan chain. It is also understood that one or more of scan flip-flops <NUM>, <NUM>, <NUM>, and <NUM> may have its output Q coupled to one or more logic circuits (not shown).

In some embodiments, scan chain <NUM> may operate in LOS mode or pipeline mode without affecting the controllability of scan flip-flop <NUM> (e.g., with the SE input of scan flip-flop <NUM> remaining high).

Scan circuit <NUM> may be used to provide scan controllability to a logic circuit (e.g., <NUM>) by using a scan flip-flop (e.g., <NUM>) that is not inside scan chain <NUM>. For example, in the embodiment of <FIG>, logic circuit <NUM> may be controlled during scan by an output of scan flip-flop <NUM>, which is not inside scan chain <NUM>. In some embodiments, one or more outputs of logic circuit <NUM> are observable during scan by being coupled to inputs of scan flip-flops of scan chain <NUM> and/or other scan chains (not shown).

In some embodiments, controllability of flip-flop <NUM> may be as follows. During scan mode (e.g., in LBIST mode or ATPG mode), the output of OR gate <NUM> is kept high. For example, signal LBIST_mode may be received from a register bit that is high during LBIST mode. Similarly, signal ATPG_mode may be received from a register bit that is high during ATPG mode.

Since the output of OR gate <NUM> is kept high during scan (e.g., regardless of whether scan enable signal scan_en is high or low), the output of scan flip-flop <NUM> (which is coupled to the SI input of scan flip-flop <NUM>) is outputted at the Q output of scan flip-flop <NUM> each pulse of clock signal clk, thereby stimulating logic circuit <NUM> (which may have its output captured using, e.g., LOC, LOS, or pipeline LOS by, e.g., another scan flip-flop).

As can be seen in <FIG>, in some embodiments, by keeping the SE input of scan flip-flop <NUM> high during scan mode, scan chain <NUM> provides controllability to scan flip-flop <NUM> in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse. Thus, some embodiments advantageously use shorter test patterns (because of the extended pipeline LOS controllability) without the challenges associated with SE transitioning during LOS mode and pipeline LOS mode, such as timing challenges associated with a fast SE transition.

In some embodiments, scan flip-flop <NUM> and/or logic circuit <NUM> may advantageously be added after scan insertion without modifying scan chain <NUM> (e.g., without increasing/decreasing the length of scan chain <NUM> or otherwise modifying scan chain <NUM> in a way that would affect the shift/launch/capture operation of scan chain <NUM>). Thus, in some embodiments, logic circuit <NUM> may be advantageously controlled (e.g., stimulated) during scan by scan chain <NUM> without modifying scan chain <NUM>.

Logic circuits <NUM>, <NUM>, <NUM>, and <NUM> may be portions of the same or different logic circuits of the IC.

Scan flip-flops <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> have D, SI, SE, CLK, and XR inputs and a Q output. In the embodiment shown in <FIG>, the scan flip flops are configured to output at Q the value at D when CLK pulses and input SE is low. The scan flip flops <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are configured to output at Q the value at SI when CLK pulses and input SE is high. The output at Q is cleared (e.g., set to low) when input XR is asserted (e.g., low). Scan flip-flops <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may be implemented in other ways known in the art.

In some embodiments, the output of logic circuit <NUM> may be coupled (e.g., directly connected) to a dummy scan flip-flop of scan chain <NUM>. In some embodiments, the output of logic circuit <NUM> may be coupled (e.g., directly connected) to a dummy scan flip-flop of a scan chain different than scan chain <NUM>.

In some embodiments, the frequency of clock signal clk may be, e.g., <NUM>. Faster frequencies, such as <NUM>, <NUM>, or faster, or slower frequencies, such as <NUM>, <NUM>, or slower, may also be used. In some embodiments, the frequency of clock signal clk when running at-speed may be based on the functional specification (e.g., datasheet) of the IC.

In an embodiment of the present invention, a scan chain is configurable to select a scan flip-flop from a plurality of scan flip-flops to be inside the scan chain. In some embodiments, an unselected scan flip-flop of the plurality of scan flip-flops, although not inside the scan chain, may receive an input from the scan chain, e.g., to control a logic circuit during scan, e.g., in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse.

<FIG> shows a portion of scan circuit <NUM>, according to an embodiment of the present invention. Scan circuit <NUM> includes scan chain <NUM>, which includes scan flip-flops <NUM>, <NUM>, and <NUM> for testing logic circuits <NUM>, <NUM>, <NUM>, and <NUM>. Scan circuit <NUM> also includes scan flip-flop <NUM> for controlling logic circuit <NUM> and for observing an output of logic circuit <NUM>. As will be described in more details later, scan chain <NUM> also includes either scan flip-flop <NUM> or scan flip-flop <NUM>.

During scan, signal ff_sel selects either scan flip-flop <NUM> or scan-flip-flop <NUM> to be inside scan chain <NUM>. For example, when signal ff_sel is low, scan enable signal scan_en controls the SE input of scan flip-flop <NUM> and MUX <NUM> couples the Q output of scan flip-flop <NUM> with the SI input of scan flip-flop <NUM>. Since signal ff_sel is coupled to the SE input of scan flip-flop <NUM> via inverter <NUM> and OR gate <NUM>, the input SE of scan flip-flop <NUM> remains high when signal ff_sel is low. Thus, when signal ff_sel is low, scan circuit <NUM> operates in a similar manner as scan circuit <NUM> (e.g., with the difference that scan flip-flop <NUM> provides controllability to scan flip-flop <NUM> instead of scan flip-flop <NUM>), thereby providing controllability to scan flip-flop <NUM> (which stimulates logic circuit <NUM>) in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse, and providing observability to logic circuit <NUM> (via scan flip-flop <NUM> and MUX <NUM>).

When signal ff_sel is high, scan enable signal scan_en controls the SE input of scan flip-flop <NUM>, MUX <NUM> couples the Q output of scan flip-flop <NUM> with the SI input of scan flip-flop <NUM>, and the input SE of scan flip-flop <NUM> remains high. Thus, when signal ff_sel is high, scan circuit <NUM> provides controllability to scan flip-flop <NUM> (which stimulates logic circuit <NUM>) in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse, and provides observability to logic circuit <NUM> (via scan flip-flop <NUM> and MUX <NUM>).

In some embodiments, the outputs of OR gates <NUM> and <NUM> may be gated (e.g., using respective AND gates) based on a scan mode signal scan_mode indicative of whether the IC is in scan mode.

As illustrated, e.g., by <FIG>, some embodiments advantageously allow for providing scan observability and controllability to logic circuits that may be added or modified after scan insertion without changing the length of the scan chain. For example, in an embodiment, logic circuits <NUM> and <NUM>, and scan flip-flop <NUM> may be added after scan insertion.

In some embodiments, a first set of test vectors may be run through scan chain <NUM> with signal ff_sel low, to, e.g., provide observability to logic circuit <NUM> and controllability to logic circuits <NUM> and <NUM>, and a second set of test vectors may be run through scan chain <NUM> with signal ff_sel high, to, e.g., provide observability to logic circuit <NUM> and controllability to logic circuits <NUM> and <NUM>. Thus, in some embodiments, signal ff_sel may be static while running a set of test patterns.

In the embodiment of <FIG>, scan flip-flop <NUM> is shown to be between two scan flip flops. For example, when scan flip-flop <NUM> is selected to be in scan chain <NUM> (when signal ff_sel is low) scan flip-flop <NUM> receives its SI input from another scan flip-flop of scan chain <NUM> (scan flip-flop <NUM>) and provides its Q output to another scan flip flop of scan chain <NUM> (scan flip-flop <NUM>). In some embodiments, scan flip-flop <NUM> may be implemented as the first scan flip-flop of scan chain <NUM> (e.g., receiving its SI input directly from an LBIST controller or from an ATE). In some embodiments, scan flip-flop <NUM> may be implemented as the last scan flip-flop of scan chain <NUM> (e.g., providing its Q output directly to the LBIST controller or to the ATE).

In some embodiments, the scan chain is configured to dynamically select which scan flip-flop is inside the scan chain, e.g., based on a test pattern. For example, <FIG> shows a portion of scan circuit <NUM>, according to an embodiment of the present invention. Scan circuit <NUM> includes scan chain <NUM>, which includes scan flip-flops <NUM>, <NUM>, and <NUM> and ether scan flip-flop <NUM> or <NUM>. Scan circuit <NUM> also includes scan chain <NUM>. As will be described in more detail later, scan chain <NUM> may be a scan chain that receives test patterns that are not compressed using test pattern compression techniques.

In the embodiment of <FIG>, during scan (when signal scan_mode is high), if signal static_sel is high, then scan circuit <NUM> operates in a similar manner as scan circuit <NUM>. For example, as illustrated in <FIG>, when signal static_sel is high, signal ff_sel may be controlled based on signal LBIST_FF_ctrl or signal ATPF_FF_ctrl, e.g., via OR gate <NUM>.

If signal static_sel is low, then signal ff_sel is controlled by scan chain <NUM>. For example, when signal static_sel is low, signal ff_sel is equal to signal sc_ff_sel. Signal sc_ff_sel is latched based on scan enable signal scan_en and has a value based on the output of scan flip-flop <NUM>. When the value of signal sc_ff_sel is high, then the value of signal ff_sel is high and scan circuit <NUM> provides observability to logic circuit 572and controllability to logic circuits <NUM> and <NUM> (e.g., in a similar manner as described with respect to <FIG>). When the value of signal sc_ff_sel is low, then the value of signal ff_sel is low and scan circuit <NUM> provides observability to logic circuit <NUM> and controllability to logic circuits <NUM> and <NUM> (e.g., in a similar manner as described with respect to <FIG>).

As illustrated in <FIG>, some embodiments advantageously allow for dynamic selection of which scan flip-flop is inside a scan chain (e.g., scan chain <NUM>) during execution of a test pattern and based on an output from a scan flip-flop of another scan chain (e.g., scan chain <NUM>).

In some embodiments, signals LBIST_FF_ctrl and signal ATPF_FF_ctrl are based on respective register bits. In some embodiments, signal LBIST_FF_ctrl is generated by LBIST controller <NUM>. In some embodiments, signal ATPF_FF_ctrl is generated externally to scan circuit <NUM>, such as by an ATE or from a register bit.

In some embodiments, signal static_sel may be based on either a register bit (e.g., static_sel_reg) or a bit stored in non-volatile memory (e.g., static_sel_nvm).

In some embodiments, the signal scan_mode, which is indicative of whether the IC that includes scan circuit <NUM> is in scan mode, is generated based on signal LBIST_mode (which is indicative of whether scan circuit <NUM> is in LBIST mode), or signal ATPG_mode (which is indicative of wehtehr scan circuit <NUM> is in ATPG mode). In some embodiments, signals LBIST_mode and ATPG_mode are based on respective register bits.

In some embodiments, scan enable signal scan_en is generated based on signal ATPG_SE (which is a scan enable signal associated with ATPG test patterns), signal LBIST_SE (which is a scan enable signal associated with LBIST test patterns), and signals ATPG_mode and LBIST_mode.

In some embodiments, LBIST controller <NUM> is part of scan circuit <NUM> and is configured to generate test patterns for testing the logic circuit of the IC (e.g., logic circuits <NUM>, <NUM>, <NUM>, <NUM>). In some embodiments, LBIST controller <NUM> generates the test patterns using a random number generator. LBIST controller <NUM> may be implemented in any way known in the art. A same or similar LBIST controller may be included in other scan circuits (e.g., scan circuits <NUM> or <NUM>). In some embodiments, scan flip-flop <NUM> is configured to control the state of signal ff_sel. Scan flip-flop <NUM> may be the first scan flip-flop of scan chain <NUM>, the last scan flip-flop of scan chain <NUM>, or a scan flip-flop coupled between the first and last scan flip-flops of scan chain <NUM>.

<FIG> shows waveforms of scan circuit <NUM>, according to an embodiment of the present invention. As shown in <FIG>, when signal ff_sel is low, scan_en_alt1 is, e.g., identical to scan enable signal scan_en while signal scan_en_alt2 is kept high. When signal ff_sel is high, scan_en_alt2 is, e.g., identical to scan enable signal scan_en while signal scan_en_alt1 is kept high. Thus, in some embodiments, one of the alternative scan flip-flops (e.g., <NUM>/<NUM>) operates, e.g., in LOC mode while the other of the alternative scan flip-flops (e.g., <NUM>/<NUM>) shifts during each pulse of clock signal clk regardless of the state of scan enable signal scan_en.

Scan circuit <NUM> is a possible implementation for dynamically selecting which scan flip-flop is inside a scan chain (e.g., scan chain <NUM>) during execution of a test pattern and based on an output from a scan flip-flop of another scan chain (e.g., scan chain <NUM>). Other implementations are also possible. For example, <FIG> shows a portion of scan circuit <NUM>, according to an embodiment of the present invention. Scan circuit <NUM> is similar and may operate in a similar manner as scan circuit <NUM>. In some embodiments, scan circuit <NUM> may generate waveforms similar or identical to the waveforms shown in <FIG>. Scan circuit <NUM>, however, includes latch <NUM> instead of scan flip-flop <NUM>.

Latch <NUM> is configured to latch the value of its D input, and output such value at its Q output when its L input transitions from high to low. Latch <NUM> may be implemented in any way known in the art.

In some embodiments, more than one scan flip-flop may be (statically or dynamically) selectable to be part of a scan chain while the other provides controllability to one or more logic circuits in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse. For example, <FIG> shows a portion of scan circuit <NUM>, according to an embodiment of the present invention. Scan circuit <NUM> is similar and operates in a similar manner as scan circuit <NUM>. Scan circuit <NUM>, however, has two scan flip-flops that are selectable to be part of scan chain <NUM>. For example, when signal ff_sel is low, scan flip-flops <NUM> and <NUM> provide observability to logic circuits <NUM> and <NUM>, respectively, and provide controllability to logic circuits <NUM> and <NUM>, respectively, while scan flip-flops <NUM> and <NUM> provide controllability to logic circuits <NUM> and <NUM>, respectively, in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse. When signal ff_sel is high, scan flip-flops <NUM> and <NUM> provide observability to logic circuits <NUM> and <NUM>, respectively, and provide controllability to logic circuits <NUM> and <NUM>, respectively, while scan flip-flops <NUM> and <NUM> provide controllability to logic circuits <NUM> and <NUM>, respectively, in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse.

As shown in <FIG>, and in a similar manner as shown in <FIG> and <FIG>, signals ff_sel, scan_en_alt1, and scan_en_alt2 may be generated by circuit <NUM>. In some embodiments, scan circuit <NUM> may be implemented with circuit <NUM> instead of circuit <NUM> (in which latch <NUM> is used instead of scan flip-flop <NUM>). Other implementations are also possible.

As shown in <FIG>, alternatively selectable scan flip-flops <NUM> and <NUM> may be understood as being part of alternative scan chain <NUM>, which is alternatively selectable to replace a portion of scan chain <NUM> of similar length (the same number of scan flip-flops, in this example <NUM> scan flip-flops) based on signal ff_sel. In some embodiments, alternative scan chain <NUM> may have more than two scan flip-flops. For example, in some embodiments, alternative scan chain <NUM> has L scan flip-flops that are alternatively selectable to replace L scan flip-flops of scan chain <NUM> based on signal ff_sel, where L is a positive integer greater than or equal to <NUM>, such as <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or higher.

In some embodiments, a scan chain may have more than one separate portions that are alternatively selectable based on signal ff_sel. For example, <FIG> shows a portion of scan circuit <NUM>, according to an embodiment of the present invention. Scan circuit <NUM> includes scan chain <NUM>, which has five portions (802a, 802b, 802c, 802d, and 802e).

During scan mode, scan chain <NUM> receives test patterns at its input (si<NUM>) and produces outputs at its output (so<NUM>). When signal ff_sel is low, scan chain <NUM> operates in a similar manner as described with respect to <FIG> when signal ff_sel is low. When signal ff_sel is high, alternatively selectable scan chains <NUM> and <NUM> replace portions 802b and 802d of scan chain <NUM>, respectively, so that portions 802b and 802d are controllable in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse.

As shown in <FIG>, MUXes <NUM> and <NUM> are controlled by signal ff_sel, portions 802b and 802d receive the same signal scan_en_alt1 (e.g., for scan enable of the scan flip-flops of portions 802b and 802d), and scan chains <NUM> and <NUM> receive the same signal scan_en_alt2 (e.g., for scan enable of the scan flip-flops of portions scan chains <NUM> and <NUM>). In some embodiments, signals ff_sel, scan_en_alt1, and scan_en_alt2 may be generated, e.g., as shown in <FIG>. Other implementations are also possible. For example, in some embodiments, MUX <NUM>, portion 802b, and scan chain <NUM> may receive a first set of signals (e.g., signals ff_sel<NUM>, scan_en_alt1<NUM>, and scan_en_alt2<NUM>, respectively), and MUX <NUM>, portion 802d, and scan chain <NUM> may receive a second set of signals (e.g., signals ff_sel<NUM>, scan_en_alt1<NUM>, and scan_en_alt2<NUM>, respectively), where the first and second sets of signals are generated based on different scan flip-flops. For example, in some embodiments, the first set of signal may be based on scan flip-flop <NUM> while the second set of signals may be based on another scan flip-flop, which may be another scan-flip flop of scan chain <NUM> or of another scan chain. In some embodiments, alternative scan chains <NUM> and <NUM> have the same length. For example, in some embodiments, both scan chains <NUM> and <NUM> have one scan flip-flops). In other embodiments, scan chains <NUM> and <NUM> may both have more than <NUM> scan flip-flop, such as <NUM>, <NUM>, <NUM>, or more).

In some embodiments, alternative scan chains <NUM> and <NUM> have different lengths. For example, in some embodiments, scan chain <NUM> has <NUM> scan flip-flops while scan chain <NUM> has three scan flip-flops. A different number of scan flip-flops for scan chains <NUM> and <NUM> is also possible.

Although <FIG> illustrates two alternative scan chains (<NUM> and <NUM>), more than two alternative scan chains may be used in the same scan chain (<NUM>).

It is understood that scan circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may be adapted to operate with a different polarity of the signals.

In some embodiments, test patterns run through scan chain <NUM> are not decompressed/compressed. For example, <FIG> shows a portion of scan circuit <NUM>, according to an embodiment of the present invention. Scan circuit <NUM> includes decompressor <NUM>, compressor <NUM>, a plurality of scan chains coupled between decompressor <NUM>, and compressor <NUM>, and scan chain <NUM>, which is not dependent on compression.

Although scan circuit <NUM> is illustrated in <FIG> as having <NUM> inputs coupled to decompressor <NUM> (si1 to si10), <NUM> outputs coupled to compressor <NUM> (so1 to so10) and <NUM> scan chains coupled between decompressor <NUM> and compressor <NUM>, it is understood that a different number of scan inputs coupled to decompressor <NUM> (e.g., <NUM>, <NUM>, or lower, or <NUM>, <NUM>, <NUM>, or higher), a different number of scan outputs (e.g., <NUM>, <NUM>, or lower, or <NUM>, <NUM>, <NUM>, or higher) and/or a different number of scan chains coupled between decompressor <NUM> and compressor <NUM> (e.g., <NUM>, <NUM>, <NUM> or lower, or <NUM>, <NUM>, <NUM>, or higher) may also be used.

During scan, the decompressor <NUM> receives at their inputs (e.g., si1 to si10) compressed test patterns from, e.g., LBIST controller <NUM> or from the ATE. The inputs coupled to decompressor <NUM> (e.g., si1 to si10) are decompressed in a known manner and converted into a plurality of outputs coupled to the plurality of scan chains (e.g., scan chain <NUM> to scan chain <NUM>). Data outputted by the plurality of scan chains (e.g., scan chain <NUM> to scan chain <NUM>) are compressed in a known manner and converter into compressed outputs (e.g., so1 to so10). The compressed outputs are transmitted, e.g., to LBIST controller <NUM> or the ATE, and evaluated in a known manner to detect faults in the logic circuits coupled to the plurality of scan chains (e.g., scan chain <NUM> to scan chain <NUM>). By using decompressor <NUM> and compressor <NUM>, some embodiments advantageously run test patterns across N scan chains using less than N inputs and outputs (e.g., <NUM> times less inputs and outputs, or less).

In some embodiments, one or more scan chains of the plurality of scan chains (e.g., scan chain <NUM> to scan chain <NUM>) may be implemented as scan chain <NUM>, <NUM>, <NUM>, <NUM>, or and/or <NUM>. For example, in the embodiment of <FIG>, scan chain i (also referred to as scan chain <NUM>) may be implemented as <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>, where i is an integer greater or equal to <NUM> and lower or equal to <NUM>.

In some embodiments, at least one scan chain is not coupled between the decompressor and the compressor. For example, as shown in <FIG>, in scan circuit <NUM>, scan chain <NUM> is not coupled between decompressor <NUM> and compressor <NUM> and, e.g., is not dependent on compression. For example, in some embodiments, scan chain <NUM> may be used, e.g., for on-chip clocking (OCC), power control, shift power control (SPC), etc..

In some embodiments, scan chain <NUM> is implemented as scan chain <NUM> and includes scan flip-flop <NUM>. For example, in some embodiments, scan chain <NUM> is implemented as scan chain <NUM> and scan chain <NUM> is implemented as scan chain <NUM>, so that scan chains <NUM> and <NUM> operate in a similar manner as described with respect to <FIG>. As another example, in some embodiments, scan chain <NUM> is implemented as scan chain <NUM> and scan chain <NUM> is implemented as scan chain <NUM>, so that scan chains <NUM> and <NUM> operate in a similar manner as described with respect to <FIG>. Other implementations are also possible.

In some embodiments, the same scan enable signal scan_en is applied to all scan chains of circuit <NUM>. For example, in some embodiments, the same scan enable signal scan_en is applied to scan chains <NUM> to <NUM> and to scan chain <NUM>. In some embodiments, the scan enable signal scan_en may be generated by (e.g., a single) circuit <NUM>.

As shown, e.g., in <FIG> and <FIG>, some embodiments advantageously allow for selecting (statically or dynamically) which scan flip-flop to use inside a scan chain, where the selected scan flip-flop is capable of providing observability and controllability (e.g., in LOC mode), and the non-selected scan flip-flop is capable of providing controllability in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse. As shown, e.g., in <FIG>, some embodiments advantageously allow for selecting (statically or dynamically) which sub-scan chain to use inside a scan chain, where the selected sub-scan chain is capable of providing observability and controllability (e.g., in LOC mode), and the non-selected sub-scan chain is capable of providing controllability in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse.

In some embodiments, the size of the sub-scan chain may be the same as the scan chain. In other words, in some embodiments, a scan chain may be selectable from among two scan chains so that the selected scan chain provides controllability and observability (e.g., in LOC mode) while the non-selected scan chain provides controllability in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse. For example, <FIG> shows a portion of scan circuit <NUM>, according to an embodiment of the present invention. Scan circuit <NUM> includes decompressor <NUM>, compressor <NUM>, a plurality of scan chains coupled between decompressor <NUM> and compressor <NUM>, and scan chain <NUM>, which is not dependent on compression.

As shown in <FIG>, scan circuit <NUM> is capable of dynamically selecting a first set of scan chains (scan chains <NUM> to <NUM>) or a second set of scan chains (scan chains <NUM> to <NUM>) for providing observability and controllability to logic circuits coupled to the scan chains of the selected set of scan chains while the non-selected set of scan chains provides controllability to logic circuits coupled to the scan chains of the non-selected set of scan chains.

As shown in <FIG>, signals ff_sel, scan_en_alt1 and scan_en_alt2 may be generated by circuit <NUM>. Signal ff_sel is applied to all MUXes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. Signal scan_en_alt1 is applied to the SE input of all scan flip-flops of scan chains <NUM> to <NUM>. Signal scan_en_alt2 is applied to the SE input of all scan flip-flops of scan chains <NUM> to <NUM>.

MUXes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are configured to select between the first set of scan chains (scan chains <NUM> to <NUM>) and the second set of scan chains (scan chains <NUM> to <NUM>) based on signal ff_sel.

In some embodiments, when ff_sel is low, scan chains <NUM> to <NUM> provide observability to logic circuits having outputs coupled to the scan flip-flops of scan chains <NUM> to <NUM> and controllability to the logic circuits having inputs coupled to scan flip-flops of scan chains <NUM> to <NUM> (e.g., in LOC mode), and scan chains <NUM> to <NUM> provide controllability to the logic circuits having inputs coupled to the scan flip-flops of scan chains <NUM> to <NUM> in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse. When ff_sel is high, scan chains <NUM> to <NUM> provide observability to logic circuits having outputs coupled to the scan flip-flops of scan chains <NUM> to <NUM> and controllability to the logic circuits having inputs coupled to scan flip-flops of scan chains <NUM> to <NUM> (e.g., in LOC mode), and scan chains <NUM> to <NUM> provide controllability to the logic circuits having inputs coupled to the scan flip-flops of scan chains <NUM> to <NUM> in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse.

In some embodiments, logic circuits controllable by scan chains <NUM> to <NUM> have outputs coupled to scan flip-flops of scan chains <NUM> to <NUM> so that they are observable when signal ff_sel is low. In some embodiments, logic circuits controllable by scan chains <NUM> to <NUM> have outputs coupled to scan flip-flops of scan chains <NUM> to <NUM> so that they are observable when signal ff_sel is high.

As shown in <FIG>, some embodiments may be implemented with decompressor <NUM> independently driving each of scan chains <NUM> to <NUM>. In other embodiments, decompressor <NUM> may provide the same inputs to scan chains i and i + <NUM> (e.g., scan chains <NUM> and <NUM> are driven by the same input, etc.) By independently driving each of scan chains <NUM> to <NUM>, some embodiments advantageously achieve higher coverage and/or lower test time when compared with embodiments having scan chains i and <NUM> + i sharing the same input.

Advantages of some embodiments include reducing test time of scan without compromising scan coverage and without designing the scan enable signal to satisfy fast transition times of LOS mode and pipeline LOS mode. For example, a conventional CODEC with LOC architecture and internal scan chains having a length of <NUM> (<NUM> scan flip-flops), <NUM>,<NUM> test patterns and clock period of <NUM> ns may result in a test time of <NUM>,<NUM>,<NUM> ns (since ((<NUM>*<NUM>)+<NUM>+<NUM>)*<NUM> = 40404000ns). If an embodiment decompression/compression architecture, e.g., as illustrated in <FIG>, is used, then scan chains with half the length (e.g., <NUM>) may be used. For such architecture, similar coverage may be achieved with about <NUM>,<NUM> test patterns, which at a clock period of <NUM> ns results in a test time of <NUM>,<NUM>,<NUM> ns (since ((<NUM>*<NUM>)+<NUM>+<NUM>)*<NUM> = <NUM> ns). Thus, the test time saved may be about <NUM>,<NUM>,<NUM> ns or over <NUM>%.

<FIG> shows a flow chart of embodiment method <NUM> for performing scan, according to an embodiment of the present invention. Method <NUM> may be implemented, e.g., by scan circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>.

During step <NUM>, an IC that includes a scan circuit (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) enters scan mode. In some embodiments, entering scan mode comprises asserting (e.g., high) a scan mode signal (e.g., scan_mode). In some embodiments, entering LBIST mode (e.g., LBIST_mode set to high) or entering ATPG mode (e.g., ATPG_mode set to high) causes the scan mode signal to be asserted.

In some embodiments, the scan circuit is capable of entering LBIST mode or ATPG mode, but not both. In some embodiments, the scan circuit is capable of entering LBIST mode and ATPG mode.

During step <NUM>, the scan circuit receives a test pattern. For example, in some embodiments, the scan circuit receives a test pattern directly from the ATPG or LBIST controller into an input of a first scan chain (e.g., at an SI input of a first scan flip-flop of the first scan chain, where the first scan chain may be, e.g., scan chain <NUM>, <NUM>, <NUM>, or <NUM>). In some embodiments, the test pattern is received at an input of a decompressor (e.g., <NUM>, <NUM>) that has an output coupled to the first scan flip-flop of the first scan chain.

During step <NUM>, the received pattern is decompressed in a known manner by the decompressor and applied to the first scan chain. In embodiments in which the first scan chain is not dependent on compression, step <NUM> may be omitted.

During step <NUM>, while the test pattern is applied to the first scan chain (e.g., in LOC mode), a further scan flip-flop (e.g., <NUM>) is controlled with an output of a scan flip-flop of the first scan chain (e.g., <NUM>) without transitioning the SE input of the further scan flip-flop (e.g., in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse), e.g., to control a further logic circuit (e.g., <NUM>) with the further scan flip-flop. In some embodiments, an output of the further logic circuit is coupled to a scan flip-flop of the first scan chain. In some embodiments, the output of the further logic circuit is coupled to a scan flip-flop of another scan chain different from the first scan chain.

During step <NUM>, an output of the first scan chain is compressed by a compressor (e.g., <NUM>, <NUM>) an outputted for evaluation. In embodiments in which the first scan chain is not dependent on compression, step <NUM> may be omitted.

During step <NUM>, the output of the first scan chain is evaluated in a known manner for detecting faults (e.g., stuck-at faults, timing faults, etc.) in logic circuits having outputs coupled to the first scan chain.

As shown by <FIG>, some embodiments advantageously provide controllability during scan mode by a first scan chain to a further scan flip-flop that is not inside the first scan chain.

<FIG> shows a flow chart of embodiment method <NUM> for performing scan, according to an embodiment of the present invention. Method <NUM> may be implemented, e.g., by scan circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>. Method <NUM> includes steps <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. Steps <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may be performed in a similar manner as in method <NUM>.

During step <NUM>, a sub-scan chain is selected to become part of the first scan chain from two sub-scan chains. In some embodiments, the selected sub-scan chain receives an input at an SI input of a first scan flip-flop of the selected sub-scan chain from a Q output of a scan flip-flop of the first scan chain and provides an output at a Q output of a last scan flip-flop of the selected sub-scan chain to an SI input of a scan flip-flop of the first scan chain. In some embodiments, the unselected sub-scan chain receives an input at an SI input of a first scan flip-flop of the unselected sub-scan chain from a Q output of a scan flip-flop of the first scan chain but the output at the Q output of a last scan flip-flop of the unselected sub-scan chain is not coupled to an SI input of a scan flip-flop of the first scan chain.

The length of the two sub-scan chains may be <NUM> or more. For example, in some embodiments (e.g., scan circuits <NUM>, <NUM>, and <NUM>), the length of the two sub-scan chains may be a single scan flip-flop (e.g., scan flip-flop <NUM> being one sub-scan chain and scan flip-flop <NUM> being the other sub-scan chain). In other embodiments (e.g., scan circuit <NUM>, and <NUM>), the two sub-scan chains may have more than one scan flip-flop such as two or more. For example, scan circuit <NUM> illustrates an embodiment having two sub-scan chains with two scan flip-flops each (one having scan flip-flops <NUM> and <NUM> and the other having scan flip-flops <NUM> and <NUM>).

In some embodiments, the sub-scan chain is selected based on a state of a selection signal (e.g., ff_sel). In some embodiments, the state of the selection signal is based on a register bit (e.g., LBIST_FF_ctrl or ATPF_FF_ctrl). In some embodiments, the state of the selection signal is based on an output of a scan flip-flop (e.g., <NUM>) of a scan chain.

During step <NUM>, while the test pattern is applied to the first scan chain (e.g., in LOC mode), a further scan flip-flop of the unselected sub-scan chain is controlled with an output of a scan flip-flop of the first scan chain without transitioning the SE input of the further scan flip-flop (e.g., in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse), e.g., to control a further logic circuit with the further scan flip-flop. In some embodiments, an output of the further logic circuit is coupled to a scan flip-flop of the first scan chain. In some embodiments, the output of the further logic circuit is coupled to a scan flip-flop of another scan chain different from the first scan chain.

<FIG> shows a flow chart of embodiment method <NUM> for scan compression, according to an embodiment of the present invention. Method <NUM> may be implemented, e.g., by scan circuits <NUM>. Method <NUM> includes steps <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. Step <NUM> may be performed in a similar manner as in method <NUM>.

During step <NUM>, test patterns are received at inputs (e.g., si1 to si10) of a scan circuit (e.g., <NUM>). During step <NUM>, the test patterns are decompressed by a decompressor (e.g., <NUM>) so that the test patterns are applied to plurality of scan chains.

During step <NUM>, scan chains from the plurality of scan chains (scan chain <NUM> to scan chain <NUM>) are dynamically selected (e.g., selecting either scan chains <NUM> to <NUM> or <NUM> to <NUM>) so that test patterns are applied to the selected scan chain, e.g., in LOC mode while the unselected scan chains are controlled in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse. In some embodiments, a selection signal (e.g., ff_sel) is used to select between first (e.g., scan chain <NUM> to scan chain <NUM>) and second (e.g., scan chain <NUM> to scan chain <NUM>) sets of scan chains. In some embodiments, the selection signal is controlled by an output of a scan flip-flop (e.g., <NUM>) that, e.g., is in a scan chain (e.g., scan chain <NUM>) that is not dependent on compression.

During step <NUM>, the outputs of the plurality of scan chains are compressed so that they are evaluated during step <NUM> to detect faults.

Some embodiments advantageously allow for providing observability and/or controllability to logic circuits added after scan insertion without affecting the length of the original scan chains. For example, <FIG> shows a flow chart of embodiment method <NUM> for modifying a scan circuit to provide observability and/or controllability to logic circuits added or modified after scan insertion, according to an embodiment of the present invention.

During step <NUM>, an SI input of a further scan flip-flop is coupled to a Q output of a scan flip-flop of a first scan chain. For example, as shown in <FIG>, <FIG>, and <FIG>, in some embodiments, an SI input of a further scan flip-flop (e.g., <NUM>) is coupled to a Q output of a scan flip-flop (e.g., <NUM>) of a first scan chain (e.g., <NUM>, <NUM>). In some embodiments, e.g., as shown in <FIG>, and SI input of further scan flip-flop (e.g., <NUM>) is coupled to a Q output of a scan flip-flop (e.g., <NUM>) of a first scan chain (e.g., <NUM>). In some embodiments, the further scan flip-flop may be added after scan insertion. In other embodiments, the further scan flip-flop is not added after scan insertion. For example, in some embodiments, the further scan flip-flop may be a dummy scan flip-flop already implemented, e.g., in one of the scan chains of the IC.

During step <NUM>, the Q output of the further scan flip-flop is coupled to a further logic circuit (e.g., <NUM>). In some embodiments, performing steps <NUM> and <NUM> provides controllability to the further scan flip-flop in a mode similar to pipeline LOS mode without having an SE input transition in launch and also in capture clk pulse so that the further logic circuit is stimulated while the first scan chain runs test patterns.

During step <NUM>, the Q output of the further scan flip-flop is further coupled to an SI input of another scan flip-flop (e.g., <NUM>), e.g., via a MUX (e.g., <NUM>). Upon selecting the further scan flip-flop by the MUX, the first scan chain does not change its length, e.g., since the further scan flip-flop replaces an original scan flip-flop (e.g., <NUM>) upon selection.

In some embodiments, the selection signal (e.g., ff_sel) for controlling the MUX is based on a scan flip-flop (e.g., <NUM>) of a scan chain (e.g., <NUM>). In some embodiments, the scan flip-flop (e.g., <NUM>) is implemented as a dummy scan flip-flop before scan insertion, e.g., in anticipation of using such flip-flop for controlling the selection signal.

In some embodiments, all or some of the additional logic for performing steps <NUM>, <NUM>, and/or <NUM> (e.g., circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM>) may be added after scan insertion. In some embodiments, all or some of the additional logic for performing steps <NUM>, <NUM>, and/or <NUM> may be implemented before scan insertion and the coupling modified after scan insertion.

In some embodiments, step <NUM> may be omitted.

Advantages of some embodiments include providing static or dynamic selection of scan flip-flops to be included in a scan chain while non-selected scan flip-flops provide additional controllability with mode similar to pipeline LOS architecture but with SE input remaining high throughout capture.

Claim 1:
A method for performing scan, the method comprising:
entering scan mode (<NUM>);
receiving a test pattern (<NUM>; <NUM>);
applying the test pattern (<NUM>, <NUM>, <NUM>) through a first scan chain (<NUM>, <NUM>, <NUM>, <NUM>) by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain (<NUM>, <NUM>);
the method is characterised in that
while applying the test pattern (<NUM>, <NUM>, <NUM>) through the first scan chain, controlling a further scan flip-flop (<NUM>) with the first scan chain (<NUM>, <NUM>) without transitioning a further scan enable input (SE) of the further scan flip-flop (<NUM>); and
evaluating (<NUM>, <NUM>) an output of the first scan chain to detect faults.