Patent Description:
A single wire is a serial communication protocol that uses a single wire to transfer digital information (bits). The protocol allows a host device and one or more slave devices (e.g., peripheral devices) to transfer digital information only in one direction at a time (half duplex). The host device and the slave device can be a transmitter and a receiver. The host device initiates and controls single wire operations. The single wire protocol uses CMOS/TTL logic and operates at a wide range of supply voltage.

Serial transmission of digital information through a single wire is less costly than parallel transmission through multiple wires because the serial transmission requires only a single pin count while the parallel transmission requires a higher pin count. However, some single wire protocol require input/output (I/O) bit banging software which must be configured to read and write inputs and handle timing. Also, the data transfer rate of some single wire protocols is generally limited to a maximum rate of <NUM> kbps depending on the cable/trace length.

For increased data rates, the universal asynchronous receiver-transmitter (UART) single wire communication protocol is used in a wide range of hardware devices in half duplex mode. In the UART protocol, data format and transmission speed are configurable. A UART device may not directly generate or receive external signals between different devices. Separate interface circuits (e.g., driver circuits) are used to convert logic level signals of the UART to and from an external device. A UART host device takes bytes of data and transmits individual bits sequentially using a driver circuit. At the destination, a slave UART device receives the bits using a driver circuit and re-assembles the bits into complete bytes. In contrast to the conventional or legacy single wire protocol which allows transmission of only a single bit per time slot (e.g., <NUM> micro seconds), the UART protocol allows transmission of <NUM> bits per time slot. Due to UART's higher speed, a wide range of hardware devices (e.g., microcontrollers) are configured to communicate using the UART protocol. However, since many legacy slave devices are configured to operate only in the conventional single wire protocol, many systems have both conventional single wire compatible devices and UART compatible devices coupled to a UART host device.

<CIT> and <CIT> disclose protocol or speed adaptation for the communication between a first and a second device.

Various aspects of this description are directed to methods and systems for data communication using the single wire communication protocol and the universal asynchronous receiver-transmitter (UART) communication protocol. In one aspect, a method includes receiving by a first device a reset pulse. The method further includes operating the first device in a standard speed single wire protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds. The method also includes operating the first device in an overdrive speed single wire protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds. The method also includes operating the first device in a universal asynchronous receiver-transmitter (UART) protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds. The method also includes transmitting by the first device an answer responsive to the reset pulse. The method also includes transmitting data by a second device responsive to the answer from the first device. The method also includes synchronizing the first device with the second device responsive to the reset pulse.

In an additional aspect of the description, a method of communication between a host device and one or more slave devices includes transmitting by the host device a reset pulse and receiving by a slave device the reset pulse. The method further includes determing the width of the reset pulse. The method also includes operating the slave device in a standard speed single wire protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds. The method also includes operating the slave device in an overdrive speed single wire protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds. The method also includes operating the slave device in a universal asynchronous receiver-transmitter (UART) protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds. The method also includes transmitting by the slave device an answer responsive to the reset pulse.

In an additional aspect of the description, a data communication system includes a host device configured to provide a reset pulse through a transmit terminal and to receive an answer at a receive terminal. The system further includes a slave device configured to receive the reset pulse at an input/output (I/O) terminal and to provide the answer through the I/O terminal. The slave device includes a second terminal coupled to ground. The system also includes an NMOS transistor having a drain terminal coupled to the I/O terminal and the transmit termial and having a source terminal coupled to ground. The NMOS transistor includes a gate terminal. The system also includes a pull-up resistor coupled between the drain terminal and a voltage supply terminal and includes an inverter having an input terminal coupled to the transmit terminal and having an output terminal coupled to the gate terminal. The slave device is configured to operate in a standard speed single wire protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds, and is configured to operate in an over drive speed single wire protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds, and is configured to operate in a universal asynchronous receiver-transmitter (UART) protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds.

In an additional aspect of the description, the NMOS transistor is configured to turn ON responsive to the reset pulse being LOW and to drive the drain terminal to ground, and the NMOS transistor is configured to turn OFF responsive to the reset pulse being HIGH and to drive the drain terminal HIGH.

In an additional aspect of the description, a data communication system includes a host device configured to provide a reset pulse through a transmit terminal and to receive an answer at a receive terminal. The system further includes a slave device configured to receive the reset pulse at an input/output (I/O) terminal and to provide the answer through the I/O terminal. The slave device includes a second terminal coupled to ground. The system also includes a PMOS transistor having a source terminal coupled to the I/O terminal and the transmit terminal and having a drain terminal coupled to ground. The PMOS transistor includes a gate terminal. The system also includes a pull-up resistor coupled between the source terminal and a voltage supply terminal and includes an inverter having an input terminal coupled to the transmit terminal and having an output terminal coupled to the gate terminal. The slave device is configured to operate in a standard speed single wire protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds, and is configured to operate in an overdrive speed single wire protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds, and is configured to operate in a universal asynchronous receiver-transmitter (UART) mode if the width of the reset pulse is between <NUM> and <NUM> micro seconds.

In an additional aspect of the description, the PMOS transistor is configured to turn OFF responsive to the reset pulse being LOW and to drive the drain terminal HIGH, and the PMOS transistor is configured to turn ON responsive to the reset pulse being HIGH and to drive the drain terminal to ground.

Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, in which some embodiments are shown.

Various aspects of this description are directed to methods and systems for data communication using the single wire communication protocol and the universal asynchronous receiver-transmitter (UART) communication protocol. In one aspect, the methods and systems enable a host device and one or more slave devices to communicate using both the conventional or legacy single wire communication protocol and the universal asynchronous receiver-transmitter (UART) communication protocol. Depending on the communication protocol used by the host device to transfer digital information (bits), the slave device selects between the UART protocol and the conventional or legacy single wire protocol.

<FIG> illustrates a data communication system <NUM> in accordance with an example of this description. The system <NUM> includes a host device <NUM> (also referred to as a master <NUM>) having a transmit terminal <NUM> and a receive terminal <NUM>. The receive terminal <NUM> is coupled to a single wire bus <NUM>. The host device <NUM> may, for example, be a microcontroller. The system <NUM> also includes a slave device <NUM> (also referred to as a peripheral device <NUM>) having an input/output (I/O) terminal <NUM> coupled to the single wire bus <NUM>. The slave device or peripheral device <NUM> includes a second terminal <NUM> coupled to ground.

With continuing reference to <FIG>, the system <NUM> includes a transistor <NUM> having a first terminal <NUM> coupled to the bus <NUM> and having a second terminal <NUM> coupled to ground. The transistor <NUM> also includes a gate terminal <NUM> coupled to an output terminal <NUM> of an inverter <NUM>. The inverter <NUM> includes an input terminal <NUM> coupled to the transmit terminal <NUM> of the host <NUM>. The system <NUM> also includes a pull-up resistor RPUP coupled between the bus <NUM> and a voltage supply terminal <NUM> which can be coupled to a voltage supply VDD.

In an example, the transistor <NUM> is an NMOS transistor having a drain terminal (terminal <NUM>) coupled to the bus <NUM> and having a source terminal (terminal <NUM>) coupled to ground. In another example, the transistor <NUM> is a PMOS transistor having a source terminal (terminal <NUM>) coupled to the bus <NUM> and having a drain terminal (terminal <NUM>) coupled to ground.

With continuing reference to <FIG>, data transfer between the host device <NUM> and the slave device <NUM> is a bit-oriented operation with data read and write. The host device <NUM> initiates and controls four basic operations: (<NUM>) Reset; (<NUM>) Write bit <NUM> - Send bit <NUM> to the slave device; (<NUM>) Write bit <NUM> - Send bit <NUM> to the slave device; and (<NUM>) Read bit - Read a bit from the slave device. Most single wire devices support two data rates: a standard speed of about <NUM> kbps and a overdrive speed of about <NUM> kbps or more. A communication sequence starts when the host device <NUM> drives a defined Reset pulse. The slave device <NUM> responds to the Reset pulse with an answer pulse and synchronizes with the host device <NUM>.

Reset Pulse: To send a Reset pulse to the slave device <NUM>, the bus <NUM> is driven LOW and delayed for <NUM> micro seconds. The bus <NUM> is then released and delayed for <NUM> micro seconds.

Write Bit <NUM>: To send bit <NUM> to the slave device <NUM>, the bus <NUM> is driven LOW and delayed for <NUM> micro seconds. The bus <NUM> is then released and delayed for up to <NUM> micro seconds.

Read Bit: To read a bit from the slave device <NUM>, the bus <NUM> is driven LOW and delayed for <NUM> micro seconds. The bus <NUM> is then released and delayed for up to <NUM> micro seconds. <FIG> illustrates timing diagrams of a Reset pulse <NUM>, a Write bit <NUM> (<NUM>), a Write bit <NUM> (<NUM>), and a Read bit (<NUM>).

<FIG> illustrates timing diagrams of an exemplary time slot <NUM> and bits transfered in the time slot <NUM>. The time slot <NUM> is divided into eight sample windows D0-D7 that can be used by the host device and the slave device to sample a bit. Under the conventional or legacy single wire protocol, a single bit is sent in the time slot <NUM>, but under the UART protocol, <NUM> bits are sent in the time slot <NUM>. In a pulse <NUM>, the host device sends bit <NUM> (Host Write-<NUM>) in the sample windows D0-D7 which is sampled by the slave device in the sample window D3, and in a pulse <NUM>, the host device sends bit <NUM> (Host Write-<NUM>) in the sample windows D0-D7 which is sampled by the slave device in the sample window D3. In a pulse <NUM>, the host device receives bit <NUM> (Host Read-<NUM>) which is sampled in sample window D3, and in a pulse <NUM>, the host device receives bit <NUM> (Host Read-<NUM>) which is sampled in the sample window D3. Although in the example of <FIG>, the bits are sampled by the host device and the slave device in the sample window D3, any one of the sample windows D0-D7 can be used to sample the bits. The receiving device encodes the transmitted signal as logic <NUM> (bit <NUM>) or logic <NUM> (bit <NUM>) depending on the percentage of time the signal is LOW. For example, in a given time slot, if the transmitted signal is LOW at least <NUM>% of the duration, the signal is encoded as logic <NUM> (bit <NUM>), and if the transmitted signal is LOW <NUM>% of the duration or less, the signal is encoded as logic <NUM> (bit <NUM>).

<FIG> illustrates timing diagrams of a sequence of pulses in a write and a read operation. A write operation starts when the host device <NUM> sends a Reset pulse 404A over the single wire bus followed by an answer 404B from the slave device <NUM>. The host device <NUM> then sends bit <NUM>404C which is sampled by the slave device <NUM> in a sample window 404D. The host device <NUM> then sends bit <NUM>404E over the bus which is sampled by the slave device <NUM> in a sample window 404F. A read operation starts with a Reset pulse 408A followed by an answer 408B from the slave device <NUM>. The slave device <NUM> sends bit <NUM>408C which is sampled by the host device <NUM> in the sampling window 408D. The slave device <NUM> then sends bit <NUM>408E which is sampled by the host device <NUM> in the sampling window 408F.

As described above, the conventional single wire protocol allows transfer of only one bit per time slot, but the UART protocol allows transfer of <NUM> bits in a time slot. Embodiments of this description enable a system such as, for example, the system <NUM> to switch between the conventional single wire or the UART protocol relying on the same hardware interface. Thus, the host device <NUM> can send bits over the bus <NUM> using the legacy single wire protocol or using the UART protocol. The slave device <NUM> identifies the communication protocol and switches between the legacy single wire protocol or the UART protocol.

In accordance with an example of this description, the width of the Reset pulse is used to determine whether to operate in the conventional single wire protocol or the UART protocol. Also, the width of the Reset pulse is used to set the speed (standard speed or overdrive speed) of the single wire protocol.

In an example, a reset pulse detector <NUM> in the slave device <NUM> measures the width of the Reset pulse. If the width of the Reset pulse is between <NUM> micro seconds and <NUM> micro seconds, the slave device is operated in accordance with the standard speed single wire protocol. If the width of the Reset pulse is between <NUM> micro seconds and <NUM> micro seconds, the slave device is operated in accordance with the overdrive single wire protocol.

<FIG> shows timing diagrams of waveforms in standard speed and overdrive single wire protocols in accordance with an example. For the standard speed single wire protocol, the host device sends a Reset pulse 504A having a width between <NUM> micro seconds and <NUM> micro seconds, followed by an answer 504B from the slave device. The slave device switches to the standard speed single wire protocol. The host device performs two write operations: transmits bit <NUM> (504C) and then transmits bit <NUM> (504D). Thereafter, the host device performs two read operations: receives bit <NUM> (504E) and then receives bit <NUM> (504F).

For the overdrive single wire protocol, the host device sends a Reset pulse 508A having a width between <NUM> micro seconds and <NUM> micro seconds, followed by an answer 508B from the slave device. The slave device switches to the overdrive single wire protocol. The host device performs two write operations: transmits bit <NUM> (508C) and then transmits bit <NUM> (508D). Thereafter, the host performs two read operations: receives bit <NUM> (508E) and then receives bit <NUM> (508F).

<FIG> shows timing diagrams of waveforms in the UART protocol. For the UART protocol, the host device sends a Reset pulse 604A having a width between <NUM> micro seconds and <NUM> micro seconds and receives an optional alert or response 604B. The host device then sends a Baud Rate Training Pattern 604C to enable the slave device to align (i.e., synchronize) its internal clock to decode UART frames. The host device then sends a host command or data 604D. The host device then receives data 604E from the slave device.

<FIG> is a flow diagram <NUM> of a method in accordance with an example. In a block <NUM>, the host device <NUM> sends a Reset pulse over the bus <NUM>. The slave device <NUM> receives the Reset pulse and in a block <NUM> determines if the width of the Reset pulse is less than <NUM> micro seconds. If the width of the Reset pulse is less than <NUM> micro seconds, in a block <NUM> the slave device <NUM> switches to the overdrive speed single wire protocol, and in a block <NUM> the slave device <NUM> receives command and data sent by the host device.

If, in the block <NUM>, the slave device <NUM> determines the width of the Reset pulse in not less than <NUM> micro second, the flow moves to a block <NUM> where the slave device <NUM> determines if the width of the Reset pulse is greater than <NUM> micro seconds. If the width of the Reset pulse is greater than <NUM> micro seconds, the slave device <NUM> switches to the standard speed single wire protocol in a block <NUM>. If the width of the Reset pulse is not greater than <NUM> micro seconds, the slave device <NUM> switches to the UART protocol mode in a block <NUM>. The flow moves to the block <NUM> where commands and data are received by the slave device <NUM>.

Thus, only if the width of the Reset pulse is between <NUM> micro seconds and <NUM> micro seconds, the slave device <NUM> is operated in the UART mode. Since the width of the Reset pulse for the standard speed single wire protocol is between <NUM> micro seconds and <NUM> micro seconds and the width of the Reset pulse for the overdrive speed single wire protocol is between <NUM> micro seconds and <NUM> micro seconds, a pulse width in the range of <NUM>-<NUM> micro seconds is reserved for the UART mode, thus allowing the slave device <NUM> to recognize that the host device <NUM> intends to communicate in the UART protocol.

With reference to <FIG>, the operation of the system <NUM> will now described. Consider, for example, the transistor <NUM> is an NMOS transistor. To perform a write <NUM> operation, the host device <NUM> drives the transmit terminal <NUM> LOW which causes the output <NUM> of the inverter <NUM> to be driven HIGH. The gate terminal <NUM>, which is coupled to the output <NUM>, is also driven HIGH, causing the NMOS transistor to turn ON and provide a conduction path. As a result, the drain terminal <NUM> is driven LOW, causing the bus <NUM> to also be driven LOW. Thus, bit <NUM> appears at the I/O terminal <NUM>.

To perform a write <NUM> operation, the host device <NUM> drives the transmit terminal <NUM> HIGH which causes the output <NUM> of the inverter <NUM> to be driven LOW. Thus, the gate terminal <NUM>, which is coupled to the output <NUM>, is also driven LOW, causing the NMOS transistor to turn OFF. As a result, the drain terminal <NUM> is driven HIGH, causing the bus <NUM> to also be driven HIGH. Thus, bit <NUM> appears at the I/O terminal <NUM> of the slave device <NUM>.

To perform a read <NUM> operation, the slave device <NUM> drives the I/O terminal <NUM> LOW, causing the bus <NUM> to be driven LOW. Thus, bit <NUM> appears at the receive terminal <NUM>. When the I/O terminal <NUM> is driven LOW, a low resistance path from the voltage supply VDD to the I/O terminal is created causing current to flow from the voltage supply VDD to the I/O terminal <NUM>. However, the pull up resistor RPUP limits current flowing from the voltage supply VDD to the I/O terminal <NUM>.

To perform a read <NUM> operation, the slave device <NUM> drives the I/O terminal <NUM> HIGH, causing the bus <NUM> to be driven HIGH. Thus, bit <NUM> appears at the receive terminal <NUM>.

Consider, for example, the transistor <NUM> is a PMOS transistor. To perform a write <NUM> operation, the host device <NUM> drives the transmit terminal <NUM> HIGH which causes the output <NUM> of the inverter <NUM> to be driven LOW. The gate terminal <NUM>, which is coupled to the output of the inverter <NUM>, is also driven LOW, causing the PMOS transistor to turn ON and the source terminal <NUM> to be driven LOW. As a result, the bus <NUM> is driven LOW. Thus, bit <NUM> appears at the I/O terminal <NUM>.

To perform a write <NUM> operation, the host device <NUM> drives the transmit terminal <NUM> LOW which causes the output <NUM> of the inverter <NUM> to be driven HIGH. Thus, the gate terminal <NUM>, which is coupled to the output <NUM>, is also driven HIGH, causing the PMOS transistor to turn OFF. As a result, the source terminal <NUM> is driven HIGH, causing the bus <NUM> to be driven HIGH. Thus, bit <NUM> appears at the I/O terminal <NUM>. To read bit <NUM>, the slave device <NUM> drives the I/O terminal <NUM> LOW, causing the bus <NUM> to be driven LOW. Thus, bit <NUM> appears at the receive terminal <NUM>. To read bit <NUM>, the slave device <NUM> drives the I/O terminal <NUM> HIGH, causing the bus <NUM> to be driven HIGH. Thus, bit <NUM> appears at the receive terminal <NUM>.

Various illustrative components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. The described functionality may be implemented in varying ways for each particular application.

Claim 1:
A method comprising:
receiving by a first device a reset pulse;
operating the first device in a standard speed single wire protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds;
operating the first device in an overdrive speed single wire protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds; and
operating the first device in a universal asynchronous receiver-transmitter (UART) protocol if the width of the reset pulse is between <NUM> and <NUM> micro seconds.