Patent Description:
A chip system in an electronic device usually includes a central processing unit (central processing unit, CPU), a memory, and a coprocessor. The CPU accesses the memory in a running process to obtain or store data. The coprocessor is configured to perform an operation that cannot be or does not need to be performed by the CPU. Currently, an access address used by a CPU to access a memory is a virtual address, and a memory management unit (memory management unit, MMU) in the coprocessor may translate the virtual address into a corresponding physical address. Therefore, how to determine the physical address attracts increasing attention.

In the conventional technology, when the MMU receives a virtual address access request from a CPU for a virtual address space, the MMU may obtain, from the memory, a level-<NUM> page table corresponding to the virtual address space. The level-<NUM> page table includes a plurality of entries, and each entry includes an association relationship between an entry index address and a physical address. The MMU obtains a corresponding entry index address from the level-<NUM> page table based on the virtual address, and then determines, from the level-<NUM> page table based on the entry index address, a physical address corresponding to the virtual address.

However, a start virtual address of the virtual address space may not start from <NUM>, but the entries included in the level-<NUM> page table are usually allocated based on a virtual address <NUM> to the maximum virtual address of the virtual address space. As a result, a quantity of entries in the level-<NUM> page table is greater than a quantity of entries actually required by the virtual address space, some entries with relatively low addresses in the level-<NUM> page table are not used, memory space occupied by these entries is wasted, and memory utilization is relatively low.

The paper by<NPL> describes as main technical problem the inefficiency of traditional page-based memory management schemes that often result in frequent page-table walks, which can degrade performance and memory bandwidth utilization due to stalls during application execution. The specific issue highlighted is the poor utilization of the Translation Lookaside Buffer (TLB) and data-level parallelism inherent in system hardware which can lead to increased overheads from these page-table walks. The solution proposed here to solve this problem is a scheme called "Compaction of Allocated Memory Blocks (CAMB) in a page table. " The essence of this scheme is to allow the operating system (OS) to compact the information about allocated memory blocks in the page table, thereby enabling a single page-table walk to acquire multiple blocks, as opposed to just one. This compaction takes advantage of the data-level parallelism in hardware and the block-level allocation in the operating system. The approach involves a coalescing method associated with the compaction, which is realized in both hardware/software designs.

<CIT> discloses that an apparatus includes a virtual address space generation unit generating a virtual address space of a guest operating system, the guest operating system being executed in the virtual address space, and a virtual address space of a virtual machine monitor, the virtual machine monitor being executed in the virtual address space; a gateway page generation unit generating a gateway page allocated to a predetermined region of an actual memory region and mapped to the virtual address space of the guest operating system and the virtual address space of the guest machine monitor; and a memory management unit executing the gateway page to map a kernel region of the guest operating system to the predetermined region of the virtual address space of the virtual machine monitor to perform translation between the virtual address space of the guest operating system and the virtual address space of the virtual machine monitor.

<CIT> discloses a memory access method and device and is applied to the technical field of computer information. According to the method, when a translation Look aside buffer (TLB) lacks information corresponding to a first virtual address, a computer system transforms the first virtual address to obtain a second virtual address, calculates a first physical address according to the preset relation between the first physical address corresponding to the first virtual address and the second physical address corresponding to the second virtual address and accesses the memory according to the first physical address, and accordingly, the computer system can access the memory corresponding to the first virtual address. By the aid of the method and the device, when a TLB lacks information corresponding to certain virtual address, for example, the first virtual address, the first physical address corresponding to the first virtual address can be obtained through calculation directly without obtaining the virtual address and physical address transformational relations from page tables of computer system memories, and accordingly, TLB loss processing expenses are reduced.

<CIT> discloses a HASH algorithm-based inverted page table determinacy management method. The method includes the steps of adjusting virtual address space sizes of all partitions on the basis of acquiring the number of the partitions of an application scenario and the necessary virtual address space sizes of the partitions, and performing preliminary page table size allocation according to a physical memory space size; performing sequence on all the virtual address partitions according to the virtual address space sizes, and unifying virtual initial addresses of all the partitions; randomly allocating a hash operator of a first partition, and perform simulation to allocate a page index of the first partition to a page table; and allocating a hash operator of the current partition according to an operator and the virtual address space size of the previous partition and the virtual space size of the current partition to avoid offset conflicts of the virtual addresses in the page table as far as possible, and adjusting the hash operator if the obtained hash operator of the current partition is <NUM>.

<CIT> discloses a file access method and apparatus, and a storage system. The method comprises: receiving a file access request comprising a file identifier; according to a first virtual address space and a first mapping relationship between the first virtual address space and a first physical address space of a file storage system, accessing the first physical address space; acquiring an index node of a target file indicated by the file identifier in the first physical address space; according to information of a file page table of the target file contained in the index node, acquiring the file page table, a second physical address space of the target file being recorded in the file page table; allocating a second virtual address space to the target file; establishing a second mapping relationship between the second physical address space and the second virtual address space; and according to the second virtual address space and the second mapping relationship, accessing the target file in the second physical address space. The software running overhead for file access can be reduced effectively. Meanwhile, the file access rate can be improved.

<CIT> discloses an address conversion method, an address conversion module and an address conversion system, and the method comprises the steps: obtaining a memory access request which comprises a target virtual address; judging whether the target virtual address is matched with a preset virtual address of a first type of physical pages or not, wherein the storage space mapped by the first type of physical pages is not smaller than a set storage space; if the target virtual address is matched with a preset virtual address of a first type of physical page, determining a target physical address base address corresponding to the target virtual address according to a preset physical address base address corresponding to the virtual address of the first type of physicalpage; and determining a physical address corresponding to the target virtual address according to the target physical address base address. According to the embodiment of the disclosure, the address conversion modes can be distinguished for different sizes of physical pages, the address conversion delay for a larger physical page is reduced, and the address conversion efficiency is improved.

<CIT> discloses a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

The document by <NPL>) discloses a virtual memory system on an ARM-based hardware platform, specifically for the Raspberry Pi. The document involves setting up the ARM's virtual memory system, which is the foundation for various computing functionalities such as process protection, shared memory, multitasking, and privileged mode execution in an operating system. This helps to understand and practically implement a simple virtual memory system with all essential features. Features include shared pages, allowing different virtual pages to map to the same physical page, and maintaining different mapping characteristics for various pages. Once this system is working, it can be extended to a full-fledged system. The techniques described involve creating and managing page tables that translate virtual addresses to physical addresses, dealing with the Translation Lookaside Buffer (TLB), and understanding the ARM processor's memory management unit (MMU) structure and functionality.

The object of the present invention is to provide a method for determining a physical address and a chip system, to reduce memory occupied by a page table and improve memory utilization. This object is solved by the attached independent claims and further embodiments and improvements of the invention are listed in the attached dependent claims. Hereinafter, up to the "brief description of the drawings", expressions like ". aspect according to the invention", "according to the invention", or "the present invention", relate to technical teaching of the broadest embodiment as claimed with the independent claims. Expressions like "implementation", "design", "optionally", "preferably", "scenario", "aspect" or similar relate to further embodiments as claimed, and expressions like "example", ". aspect according to an example", "the disclosure describes", or "the disclosure" describe technical teaching which relates to the understanding of the invention or its embodiments, which, however, is not claimed as such.

According to a first aspect, the invention provides a method for determining a physical address, including: when a first virtual address of a first virtual address space is obtained, determining a first entry index address corresponding to the first virtual address; and determining, from a first page table based on the first entry index address, a first target physical address corresponding to the first virtual address.

The first page table is used to determine a physical address corresponding to each virtual address in the first virtual address space, a start virtual address of the first virtual address space corresponds to a second entry index address in the first page table, the second entry index address is greater than or equal to a base address of the first page table and less than a sum of the base address of the first page table and a quotient of dividing the start virtual address by a size of a second virtual address space, a largest entry index address of the first page table is less than a sum of the base address of the first page table and a quotient of dividing a largest virtual address of the first virtual address space by the size of the second virtual address space, and the second virtual address space is virtual address space associated with any entry in the first page table. In other words, the second virtual address space may be a subset of the first virtual address space.

It should be noted that the page table is a special data structure stored in a memory. The page table may be used as an index of the virtual address space and may include a plurality of entries. Each entry includes an association relationship between an entry index address and a physical address. The physical address may be carried in a page table descriptor of the entry. The page table descriptor may be used to indicate a base address of a next-level page table or a base address of a physical address corresponding to the virtual address.

According to the invention, when obtaining the first virtual address in the first virtual address space, the MMU may determine the first entry index address corresponding to the first virtual address in the first page table, and determine, from the first page table based on the first entry index address, the first target physical address corresponding to the first virtual address. The first page table may be used to determine a physical address corresponding to each virtual address in the first virtual address space, the start virtual address of the first virtual address space corresponds to the second entry index address in the first page table, the second entry index address is greater than or equal to the base address of the first page table, and is less than the sum of the base address of the first page table and the quotient of dividing the start virtual address by the size of the second virtual address space, the largest entry index address of the first page table is less than the sum of the base address of the first page table and the quotient of dividing the largest virtual address of the first virtual address space by the size of the second virtual address space, and the second virtual address space is virtual address space associated with any entry in the first page table. Therefore, the first page table may include at least an entry actually required by the first virtual address space. This saves memory and improves memory utilization.

Optionally but not claimed, a second page table corresponding to the first virtual address space may be obtained in advance (for example, before the first entry index address corresponding to the first virtual address is determined when the first virtual address of the first virtual address space is obtained). If a fourth entry index address is greater than a base address of the second page table, it may be determined that an unused entry exists in the second page table, page table descriptors in the second page table may be sequentially offset downward by entries of a first entry quantity, and entries of a first entry quantity in a high address part of the second page table are deleted, so as to obtain the first page table corresponding to the first virtual address space.

A fourth entry index address is an entry index address, in the second page table, corresponding to the start virtual address of the first virtual address space. When the page table descriptors in the second page table are sequentially offset downward by the entries of the first entry quantity, the fourth entry index address is the same as the second entry index address.

Optionally but not claimed, the first entry quantity may be greater than <NUM> and less than or equal to a second entry quantity.

The second entry quantity may be a maximum value by which a page table descriptor in the second page table can be offset downwards. The second entry quantity may be calculated in a plurality of manners, but calculation results in the plurality of calculation manners may be the same. For example, the second entry quantity = the start virtual address of the first virtual address space/the size of the second virtual address space, or the second entry quantity = the entry quantity of the second page table - the size of the first virtual address space/the size of the second virtual address space.

It should be noted that a larger first entry quantity indicates a larger entry offset amplitude and larger saved memory. The second page table and the first page table are used as an example, memory saved by the first page table and the second page table = a first entry quantity x a memory size occupied by each entry in the second page table (or the first page table).

Certainly, in actual application, the first virtual address space may also be obtained first. If the start virtual address of the first virtual address space is greater than <NUM>, the fourth entry index address in the second page table may be greater than the base address of the second page table. Therefore, the page table descriptor of the second page table may be sequentially offset downward by the entries of the first entry quantity corresponding to the second page table, to obtain the first page table.

According to the invention, the determining a first entry index address corresponding to the first virtual address includes: determining a second virtual address based on the first virtual address and a first offset value, where the first virtual address is greater than the second virtual address, and optionally but not claimed the first offset value is less than or equal to the start virtual address of the first virtual address space; and according to the invention, determining the first entry index address based on the second virtual address. Optionally but not claimed, the first offset value = the first entry quantity corresponding to the first page table * the size of second virtual address space associated with each entry of the first page table.

When an arithmetic logic unit (arithmetic logic unit, ALU) completes offsetting on the first virtual address and determines the second virtual address, the MMU may determine the base address of the first page table, and determine the first entry index address based on the base address of the first page table and the second virtual address. In addition, when the first target physical address corresponding to the first virtual address is determined, searching is sequentially performed from the level-<NUM> page table, a level-<NUM> page table, a level-<NUM> page table. , until the corresponding first target physical address is found. Therefore, the first entry index address may be determined based on the base address of the first page table and the second virtual address in the following two possible implementations:
In a possible implementation, when the first page table is the level-<NUM> page table, the first virtual address may be compared with a virtual address space corresponding to each translation table base register (translation table base register, TTBR). If the first virtual address belongs to a virtual address space corresponding to a TTBR (the first virtual space may be a subset of the virtual address space corresponding to the TTBR), the base address of the first page table is obtained from the TTBR corresponding to the virtual address space. A sum of the base address of the first page table and a level-<NUM> page table index bit in the second virtual address is determined as the first entry index address.

In another possible but not claimed implementation, when the first page table is a secondary page table, the base address of the first page table may be determined based on a third page table, and the first entry index address is determined based on the base address of the first page table and the second virtual address, where the third page table is a previous-level page table adjacent to the first page table.

Optionally but not claimed, the determining a first entry index address corresponding to the first virtual address includes: determining, based on the first virtual address, a third entry index address to be offset; and determining the first entry index address based on the third entry index address and a second offset value, where the third entry index address is greater than the first entry index address, and the second offset value = the first entry quantity.

It can be learned from the foregoing that, in a process of determining the first target physical address corresponding to the first virtual address, the MMU may need to search for a plurality of levels of page tables. The first page table may be any level of page table, that is, any page table may have an offset. If the MMU first offsets the first virtual address by using the ALU to obtain the second virtual address, and then determines the corresponding first entry index address from the first page table based on the second virtual address, regardless of which page tables in the plurality of levels of page tables are offset, the obtained second virtual address may match the offset page table provided that the first virtual address is offset at least once. If the MMU first determines the to-be-offset third entry index address based on the first virtual address, and then offsets the third entry index address to obtain the first entry index address, when determining the first entry index address in the offset page table at each layer, the MMU may separately offset the third entry index address for the page table to obtain the first entry index address.

Optionally, before the determining a first entry index address corresponding to the first virtual address, the method further includes: obtaining page table offset flag information, where the page table offset flag information is used to indicate to determine, based on the first page table, the first target physical address corresponding to the first virtual address.

Optionally, the page table offset flag information is indicated by an offset indicator bit in a translation table base control register (translation table base control register, TTBCR), and the obtaining page table offset flag information includes: when a value of the offset indicator bit in the TTBCR is a first indicator, determining that the page table offset flag information is obtained.

Optionally but not claimed, the method further includes:
setting the value of the offset indicator bit in the TTBCR to the first indicator.

Optionally, the first page table is the level-<NUM> page table or the level-<NUM> page table.

Optionally, the first virtual address space is kernel mode address space.

An address range of the kernel mode address space may be 0x80000000 to 0xFFFFFFFF.

According to a second aspect, the invention also provides a chip system, where the chip system includes at least one CPU, at least one memory, and at least one coprocessor, and the at least one coprocessor includes at least one MMU. The at least one MMU is configured to: when an access request initiated by the at least one CPU for the at least one memory is received, and the access request carries a first virtual address of a first virtual address space, determine a first entry index address corresponding to the first virtual address; determine, from a first page table based on the first entry index address, a first target physical address corresponding to the first virtual address. The first page table is used to determine a physical address corresponding to each virtual address in the first virtual address space, a start virtual address of the first virtual address space corresponds to a second entry index address in the first page table, the second entry index address is greater than or equal to a base address of the first page table and less than a sum of the base address of the first page table and a quotient of dividing the start virtual address by a size of a second virtual address space, a largest entry index address of the first page table is less than a sum of the base address of the first page table and a quotient of dividing a largest virtual address of the first virtual address space by the size of the second virtual address space, and the second virtual address space is virtual address space associated with any entry in the first page table.

Optionally, the at least one MMU includes at least one ALU.

The at least one ALU is configured to determine a second virtual address based on the first virtual address and a first offset value, where the first virtual address is greater than the second virtual address.

The at least one MMU is further configured to determine the first entry index address based on the second virtual address.

Optionally but not claimed, the at least one MMU is further configured to: determine, based on the first virtual address, a third entry index address to be offset; and determine the first entry index address based on the third entry index address and a second offset value, where the third entry index address is greater than the first entry index address.

Optionally but not claimed, the at least one MMU further includes at least one TTBCR, and the at least one MMU is further configured to:
obtain page table offset flag information, where the page table offset flag information is indicated by an offset indicator bit in the at least one TTBCR.

Optionally but not claimed, the MMU further includes at least one TTBR, and each TTBR may store a base address of one level-<NUM> page table. Correspondingly, the TTBCR may be used to indicate TTBRs selected when physical addresses corresponding to virtual addresses in different virtual address spaces are determined. In other words, the TTBRs corresponding to the different virtual address spaces are determined.

Optionally but not claimed, the at least one coprocessor may be integrated into the at least one CPU.

According to a third aspect, the invention also provides an electronic device, where the electronic device includes the chip system according to any implementation of the second aspect.

According to a fourth but not claimed aspect, a computer program product is provided. When the computer program product runs on an electronic device, the electronic device is enabled to perform the method according to any implementation of the first aspect.

It may be understood that, for beneficial effects of the second aspect to the fourth aspect, reference may be made to the related descriptions in the first aspect. Furthermore, in the following description, features which in the above summary of the invention have been marked as "not claimed" or "according to the invention" are also hereinafter, when they are described and explained with reference to the drawings, to be understood as "not claimed" or "not part of the invention" or "according to the invention", even if sometimes the above features of the invention are referred to below with the terms "can" or "may". That is, those features of the invention are not to be regarded as "optional" but "essential" also in the description of the embodiments of the invention below.

A method for determining a physical address in embodiments of this application may be applied to an electronic device such as a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, an augmented reality (augmented reality, AR) device/a virtual reality (virtual reality, VR) device, a notebook computer, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook, a personal digital assistant (personal digital assistant, PDA), or a server. A specific type of the electronic device is not limited in embodiments of this application.

<FIG> is a schematic diagram of a structure of an electronic device <NUM> according to an embodiment of this application. The electronic device <NUM> may include a CPU <NUM>, an external memory interface <NUM>, an internal memory <NUM>, a universal serial bus (universal serial bus, USB) interface <NUM>, a charging management module <NUM>, a power management module <NUM>, a battery <NUM>, an antenna <NUM>, an antenna <NUM>, a mobile communications module <NUM>, a wireless communications module <NUM>, an audio module <NUM>, a speaker 170A, a receiver 170B, a microphone 170C, a headset jack 170D, a sensor module <NUM>, a button <NUM>, a motor <NUM>, an indicator <NUM>, a camera <NUM>, a display <NUM>, a subscriber identification module (subscriber identification module, SIM) card interface <NUM>, and the like. The sensor module <NUM> may include a pressure sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, an optical proximity sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor L, a bone conduction sensor, and the like.

It may be understood that the structure shown in this embodiment of this application does not constitute a specific limitation on the electronic device <NUM>. In some other embodiments of this application, the electronic device <NUM> may include more or fewer components than those shown in the figure, or some components may be combined, or some components may be split, or different component arrangements may be used. The components shown in the figure may be implemented by hardware, software, or a combination of software and hardware.

The CPU <NUM> may include one or more processing units. For example, the CPU <NUM> may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a memory, and a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a neural-network processing unit (neural-network processing unit, NPU), and the like. Different processing units may be independent components, or may be integrated into one or more processors.

The controller may be a nerve center and a command center of the electronic device <NUM>. The controller may generate an operation control signal based on an instruction operation code and a time sequence signal, to complete control of instruction reading and instruction execution.

In some embodiments, the CPU <NUM> may include one or more interfaces.

The I2C interface is a two-way synchronization serial bus, and includes a serial data line (serial data line, SDA) and a serial clock line (serial clock line, SCL). In some embodiments, the CPU <NUM> may include a plurality of groups of I2C buses. The CPU <NUM> may be separately coupled to the touch sensor, a charger, a flash, the camera <NUM>, and the like by using different I2C bus interfaces. For example, the CPU <NUM> may couple the touch sensor by using the I2C interface, so that the CPU <NUM> communicates with the touch sensor by using the I2C bus interface, to implement a touch function of the electronic device <NUM>.

The I2S interface may be configured to perform audio communication. In some embodiments, the CPU <NUM> may include a plurality of groups of I2S buses. The CPU <NUM> may be coupled to the audio module <NUM> by using the I2S bus, to implement communication between the CPU <NUM> and the audio module <NUM>. In some embodiments, the audio module <NUM> may transmit an audio signal to the wireless communications module <NUM> through the I2S interface, to implement a function of answering a call through a Bluetooth headset.

The PCM interface may also be used to perform audio communication, and sample, quantize, and code an analog signal. In some embodiments, the audio module <NUM> may be coupled to the wireless communications module <NUM> through a PCM bus interface. In some embodiments, the audio module <NUM> may also transmit an audio signal to the wireless communications module <NUM> through the PCM interface, to implement a function of answering a call through a Bluetooth headset. Both the I2S interface and the PCM interface may be used for audio communication.

The UART interface is a universal serial data bus, and is configured to perform asynchronous communication. The bus may be a two-way communications bus. The bus converts to-be-transmitted data between serial communication and parallel communication. In some embodiments, the UART interface is usually configured to connect the CPU <NUM> to the wireless communications module <NUM>. For example, the CPU <NUM> communicates with the Bluetooth module in the wireless communications module <NUM> by using the UART interface, to implement a Bluetooth function. In some embodiments, the audio module <NUM> may transmit an audio signal to the wireless communications module <NUM> through the UART interface, to implement a function of playing music through a Bluetooth headset.

The MIPI interface may be configured to connect the CPU <NUM> to peripheral components such as the display <NUM> and the camera <NUM>. The MIPI interface includes a camera serial interface (camera serial interface, CSI), a display serial interface (display serial interface, DSI), and the like. In some embodiments, the CPU <NUM> communicates with the camera <NUM> by using the CSI interface, to implement a photographing function of the electronic device <NUM>. The CPU <NUM> communicates with the display <NUM> by using the DSI interface, to implement a display function of the electronic device <NUM>.

The GPIO interface may be configured by software. The GPIO interface may be configured as a control signal or a data signal. In some embodiments, the GPIO interface may be configured to connect the CPU <NUM> to the camera <NUM>, the display <NUM>, the wireless communications module <NUM>, the audio module <NUM>, the sensor module <NUM>, and the like. The GPIO interface may alternatively be configured as an I2C interface, an I2S interface, a UART interface, an MIPI interface, or the like.

The USB interface <NUM> is an interface that conforms to a USB standard specification, and may be specifically a mini USB interface, a micro USB interface, a USB type-C interface, or the like. The USB interface <NUM> may be configured to connect to a charger to charge the electronic device <NUM>, or may be configured to transmit data between the electronic device <NUM> and a peripheral device, or may be configured to connect to a headset for playing audio through the headset. The interface may be further configured to connect to another electronic device <NUM>, for example, an AR device.

It may be understood that an interface connection relationship between the modules shown in this embodiment of this application is merely an example for description, and constitutes no limitation on the structure of the electronic device <NUM>. In some other embodiments of this application, the electronic device <NUM> may alternatively use an interface connection manner different from that in the foregoing embodiment, or use a combination of a plurality of interface connection manners.

The charging management module <NUM> is configured to receive a charging input from the charger. The charger may be a wireless charger or a wired charger. In some embodiments of wired charging, the charging management module <NUM> may receive a charging input of a wired charger through the USB interface <NUM>. In some embodiments of wireless charging, the charging management module <NUM> may receive a wireless charging input through a wireless charging coil of the electronic device <NUM>. The charging management module <NUM> may further supply power to the electronic device <NUM> through the power management module <NUM> while charging the battery <NUM>.

The power management module <NUM> is configured to connect the battery <NUM>, the charging management module <NUM>, and the CPU <NUM>. The power management module <NUM> receives input of the battery <NUM> and/or the charging management module <NUM>, and supplies power to the CPU <NUM>, the internal memory <NUM>, the external memory, the display <NUM>, the camera <NUM>, the wireless communications module <NUM>, and the like. The power management module <NUM> may further be configured to monitor parameters such as a battery capacity, a battery cycle count, and a battery health state (electric leakage or impedance). In some other embodiments, the power management module <NUM> may alternatively be disposed in the CPU <NUM>. In some other embodiments, the power management module <NUM> and the charging management module <NUM> may alternatively be disposed in a same component.

The antenna <NUM> and the antenna <NUM> are configured to transmit and receive an electromagnetic wave signal. Each antenna in the electronic device <NUM> may be configured to cover one or more communications frequency bands. Different antennas may be further multiplexed, to improve antenna utilization. For example, the antenna <NUM> may be multiplexed as a diversity antenna of a wireless local area network. In some other embodiments, the antenna may be used in combination with a tuning switch.

The mobile communications module <NUM> may provide a solution applied to the electronic device <NUM> for wireless communication such as <NUM>/<NUM>/<NUM>/<NUM>. The mobile communications module <NUM> may include at least one filter, a switch, a power amplifier, a low noise amplifier (low noise amplifier, LNA), and the like. The mobile communications module <NUM> may receive an electromagnetic wave through the antenna <NUM>, perform processing such as filtering or amplification on the received electromagnetic wave, and transmit the electromagnetic wave to the modem processor for demodulation. The mobile communications module <NUM> may further amplify a signal modulated by the modem processor, and convert the signal into an electromagnetic wave for radiation through the antenna <NUM>. In some embodiments, at least some functional modules of the mobile communications module <NUM> may be disposed in the CPU <NUM>. In some embodiments, at least some functional modules of the mobile communications module <NUM> and at least some modules of the CPU <NUM> may be disposed in a same component.

The modem processor may include a modulator and a demodulator. The modulator is configured to modulate a to-be-sent low-frequency baseband signal into a medium-high frequency signal. The demodulator is configured to demodulate a received electromagnetic wave signal into a low-frequency baseband signal. Then, the demodulator transmits the low-frequency baseband signal obtained through demodulation to the baseband processor for processing. The low-frequency baseband signal is processed by the baseband processor and then transmitted to the application processor. The application processor outputs a sound signal by using an audio device (which is not limited to the speaker 170A, the receiver 170B, or the like), or displays an image or a video by using the display <NUM>. In some embodiments, the modem processor may be an independent component. In some other embodiments, the modem processor may be independent of the CPU <NUM>, and is disposed in a same device as the mobile communications module <NUM> or another functional module.

The wireless communications module <NUM> may provide a wireless communication solution that includes a wireless local area network (wireless local area network, WLAN) (for example, a wireless fidelity (wireless fidelity, Wi-Fi) network), Bluetooth (Bluetooth, BT), a global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), a near field communication (near field communication, NFC) technology, an infrared (infrared, IR) technology, or the like and that is applied to the electronic device <NUM>. The wireless communications module <NUM> may be one or more components integrating at least one communications MMU. The wireless communications module <NUM> receives an electromagnetic wave by using the antenna <NUM>, performs frequency modulation and filtering processing on the electromagnetic wave signal, and sends a processed signal to the CPU <NUM>. The wireless communications module <NUM> may further receive a to-be-sent signal from the CPU <NUM>, perform frequency modulation and amplification on the signal, and convert the signal into an electromagnetic wave by using the antenna <NUM> and radiate the electromagnetic wave.

In some embodiments, the antenna <NUM> and the mobile communications module <NUM> in the electronic device <NUM> are coupled, and the antenna <NUM> and the wireless communications module <NUM> in the electronic device <NUM> are coupled, so that the electronic device <NUM> can communicate with a network and another device by using a wireless communications technology. The wireless communications technology may include a global system for mobile communications (global system for mobile communications, GSM), a general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), time-division code division multiple access (time-division code division multiple access, TD-SCDMA), long term evolution (long term evolution, LTE), BT, a GNSS, a WLAN, NFC, FM, an IR technology, and/or the like. The GNSS may include a global positioning system (global positioning system, GPS), a global navigation satellite system (global navigation satellite system, GLONASS), a BeiDou navigation satellite system (BeiDou navigation satellite system, BDS), a quasi-zenith satellite system (quasi-zenith satellite system, QZSS), and/or a satellite based augmentation system (satellite based augmentation system, SBAS).

The electronic device <NUM> may implement a display function through the GPU, the display <NUM>, the application processor, and the like. The GPU is a microprocessor for image processing, and is connected to the display <NUM> and the application processor. The GPU is configured to: perform mathematical and geometric computation, and render an image. The CPU <NUM> may include one or more GPUs, and the GPUs execute program instructions to generate or change display information.

The display <NUM> is configured to display an image, a video, and the like. The display <NUM> includes a display panel. The display panel may be a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (organic light-emitting diode, OLED), an active-matrix organic light emitting diode (active-matrix organic light emitting diode, AMOLED), a flexible light-emitting diode (flexible light-emitting diode, FLED), a mini-LED, a micro-LED, a micro-OLED, a quantum dot light emitting diode (quantum dot light emitting diode, QLED), or the like. In some embodiments, the electronic device <NUM> may include one or N displays <NUM>, where N is a positive integer greater than <NUM>.

The electronic device <NUM> may implement a photographing function through the camera <NUM>, the ISP, the video codec, the GPU, the display <NUM>, the application processor and the like.

The ISP is configured to process data fed back by the camera <NUM>. For example, during photographing, a shutter is pressed, and light is transmitted to a photosensitive element of the camera through a lens. An optical signal is converted into an electrical signal, and the photosensitive element of the camera transmits the electrical signal to the ISP for processing, to convert the electrical signal into a visible image. The ISP may further perform algorithm optimization on noise, brightness, and complexion of the image. The ISP may further optimize parameters such as exposure and a color temperature of a photographing scenario. In some embodiments, the ISP may be disposed in the camera <NUM>.

The camera <NUM> is configured to capture a static image or a video. An optical image of an object is generated through the lens, and is projected onto the photosensitive element. The photosensitive element may be a charge coupled device (charge coupled device, CCD) or a complementary metal-oxide-semiconductor (complementary metal-oxide-semiconductor, CMOS) phototransistor. The light-sensitive element converts an optical signal into an electrical signal, and then transmits the electrical signal to the ISP to convert the electrical signal into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard format such as RGB or YUV. In some embodiments, the electronic device <NUM> may include one or N cameras <NUM>, where N is a positive integer greater than <NUM>.

The digital signal processor is configured to process a digital signal, and may process another digital signal in addition to the digital image signal. For example, when the electronic device <NUM> selects a frequency, the digital signal processor is configured to perform Fourier transformation on frequency energy.

The video codec is configured to compress or decompress a digital video. The electronic device <NUM> may support one or more video codecs. In this way, the electronic device <NUM> may play or record videos in a plurality of coding formats, for example, moving picture experts group (moving picture experts group, MPEG)-<NUM>, MPEG-<NUM>, MPEG-<NUM>, and MPEG-<NUM>.

The NPU is a neural-network (neural-network, NN) computing processor, quickly processes input information by referring to a structure of a biological neural network, for example, by referring to a mode of transmission between human brain neurons, and may further continuously perform self-learning. Applications such as intelligent cognition of the electronic device <NUM> may be implemented through the NPU, for example, image recognition, facial recognition, speech recognition, and text understanding.

The external memory interface <NUM> may be used to connect to an external storage card, for example, a micro SD card, to extend a storage capability of the electronic device <NUM>. The external memory card communicates with the CPU <NUM> by using the external memory interface <NUM>, to implement a data storage function. For example, files such as music and videos are stored in the external storage card.

The internal memory <NUM> may be configured to store computer-executable program code. The executable program code includes instructions. The CPU <NUM> executes various functional applications and data processing of the electronic device <NUM> by running the instructions stored in the internal memory <NUM>. The internal memory <NUM> may include a program storage area and a data storage area. The program storage area may store an operating system, an application required by at least one function (for example, a sound playing function or an image playing function), and the like. The data storage area may store data (for example, audio data or an address book) created during use of the electronic device <NUM>, and the like. In addition, the internal memory <NUM> may include a high-speed random access memory, or may include a nonvolatile memory such as at least one disk storage device, a flash memory, or a universal flash storage (universal flash storage, UFS).

An MMU <NUM> may be disposed in a coprocessor (not shown in <FIG>), and the coprocessor may be disposed between the CPU <NUM> and a bus of the internal memory <NUM> and the external memory interface <NUM>. When the CPU <NUM> needs to access the internal memory <NUM> (that is, the memory in the foregoing), a virtual address may be provided, and the MMU maps the virtual address to a physical address, so that the CPU <NUM> can read or write data to the internal memory <NUM> based on the physical address.

The virtual address is an address in an address space that can be identified or generated by an operating system in the electronic device, and a size range of the virtual address may be determined by a quantity of bits of the operating system running in the CPU <NUM>. For example, if the operating system running in the CPU <NUM> is <NUM> bits, and the virtual address is also <NUM> bits, the address range of the virtual address is <NUM> to 0xFFFFFFFF (4GB). If the operating system running in the CPU <NUM> is <NUM> bits, and the virtual address is also <NUM> bits, the address space of the virtual address is <NUM> to 0xFFFFFFFFFFFFFFFF (16EB).

The virtual address may be divided into a plurality of virtual address spaces based on an actual requirement, for example, a user mode address space and a kernel mode address space. The user mode address space may be accessed by a user mode program (for example, reading, writing, opening, closing, or drawing) and a kernel mode program (for example, process management, storage management, file management, or device management). The kernel mode address space may be accessed only by the kernel mode program during running.

The physical address may be an address in the address space actually owned by a hardware storage device such as the internal memory <NUM>. The address space of the physical address may be less than the address space of the virtual address. For example, when a size of the address space of the virtual address may be <NUM> GB, a size of the address space of the physical address may be <NUM> MB.

The MMU <NUM> may include several ALUs <NUM> (only one is shown in <FIG>), a TTBCR <NUM>, and several TTBRs <NUM> (only two are shown in <FIG>).

The TTBCR <NUM> may be configured to store TTBR-related control information, for example, specify a TTBR <NUM> corresponding to the kernel mode address space and the user mode address space. In this embodiment of this application, a reserved bit in the TTBCR <NUM> may be further used to indicate whether to offset the virtual address before the virtual address is mapped.

The TTBR <NUM> may be used to indicate a base address of the level-<NUM> page table (that is, an entry index address of a first entry in the level-<NUM> page table). The ALU <NUM> may be configured to perform a logical operation, for example, offset a virtual address upward or downward.

The electronic device <NUM> may implement an audio function such as music playing and recording through the audio module <NUM>, the speaker 170A, the receiver 170B, the microphone 170C, the headset jack 170D, the application processor, and the like.

The audio module <NUM> is configured to convert digital audio information into an analog audio signal for output, and is also configured to convert analog audio input into a digital audio signal. The audio module <NUM> may be further configured to code and decode an audio signal. In some embodiments, the audio module <NUM> may be disposed in the CPU <NUM>, or some function modules of the audio module <NUM> are disposed in the CPU <NUM>.

The speaker 170A, also referred to as a "loudspeaker", is configured to convert an audio electrical signal into a sound signal. The electronic device <NUM> may be used to listen to music or answer a call in a hands-free mode over the speaker 170A.

The receiver 170B, also referred to as an "earpiece", is configured to convert an electrical audio signal into a sound signal. When a call is answered or speech information is received through the electronic device <NUM>, the receiver 170B may be put close to a human ear to listen to a voice.

The microphone 170C, also referred to as a "mike" or a "mic", is configured to convert a sound signal into an electrical signal. When making a call or sending a voice message, a user may make a sound near the microphone 170C through the mouth of the user, to input a sound signal to the microphone 170C. At least one microphone 170C may be disposed in the electronic device <NUM>. In some other embodiments, two microphones 170C may be disposed in the electronic device <NUM>, to collect a sound signal and implement a noise reduction function. In some other embodiments, three, four, or more microphones 170C may alternatively be disposed in the electronic device <NUM>, to collect a sound signal, implement noise reduction, and identify a sound source, so as to implement a directional recording function and the like.

The headset jack 170D is configured to connect to a wired headset. The headset jack 170D may be a USB interface <NUM>, or may be a <NUM> open mobile terminal platform (open mobile terminal platform, OMTP) standard interface or a cellular telecommunications industry association of the USA (cellular telecommunications industry association of the USA, CTIA) standard interface.

The button <NUM> includes a power button, a volume button, and the like. The button <NUM> may be a mechanical button, or may be a touch button. The electronic device <NUM> may receive a button input, and generate a button signal input related to a user setting and function control of the electronic device <NUM>.

The motor <NUM> may generate a vibration prompt. The motor <NUM> may be configured to provide an incoming call vibration prompt and a touch vibration feedback. For example, touch operations performed on different applications (for example, photographing and audio play) may correspond to different vibration feedback effects. The motor <NUM> may also correspond to different vibration feedback effects for touch operations performed on different areas of the display <NUM>. Different application scenarios (for example, a time reminder, information receiving, an alarm clock, and a game) may also correspond to different vibration feedback effects. A touch vibration feedback effect may be further customized.

The SIM card interface <NUM> is configured to connect to a SIM card. The SIM card may be inserted into the SIM card interface <NUM> or removed from the SIM card interface <NUM>, to implement contact with or separation from the electronic device <NUM>. The electronic device <NUM> may support one or N SIM card interfaces, where N is a positive integer greater than <NUM>. The SIM card interface <NUM> may support a nano-SIM card, a micro-SIM card, a SIM card, and the like. A plurality of cards may be inserted into a same SIM card interface <NUM> at the same time. The plurality of cards may be of a same type or different types. The SIM card interface <NUM> may be compatible with different types of SIM cards. The SIM card interface <NUM> is also compatible with an external storage card. The electronic device <NUM> interacts with a network through the SIM card, to implement functions such as conversation and data communication. In some embodiments, the electronic device <NUM> uses an eSIM, that is, an embedded SIM card. The eSIM card may be embedded into the electronic device <NUM>, and cannot be separated from the electronic device <NUM>.

A software system of the electronic device <NUM> may use a layered architecture, an event-driven architecture, a microkernel architecture, a micro service architecture, or a cloud architecture.

When the CPU in the electronic device accesses the memory, the CPU sends the virtual address to the MMU. The MMU maps the virtual address to the corresponding physical address, that is, translates the access to the virtual address into the access to the physical memory, so as to save a physical address space and protect the physical address space. The MMU may use a paging mechanism to manage the virtual address space by using a page as a unit, and each page may include a virtual address space of a preset size.

The virtual address space may include more than one virtual address, and one virtual address space may correspond to one page table set. The page table set may be used to determine a physical address corresponding to a virtual address of the virtual address space. The page table set may include one level-<NUM> page table, or the page table set may include one level-<NUM> page table and at least one secondary page table. The secondary page table may include a level-<NUM> page table, a level-<NUM> page table, or even a lower-level page table. Correspondingly, the MMU may determine, through at least level-<NUM> mapping, the physical address corresponding to the virtual address, and a level of mapping is consistent with a level of the page table set. For example, when the physical address corresponding to the virtual address is determined through level-<NUM> mapping, the level-<NUM> mapping is referred to as segment mapping, and the page table set may include only level-<NUM> page table. When the physical address corresponding to the virtual address is determined through level-<NUM> mapping, the level-<NUM> mapping is referred to as page mapping, and the page table set may include one level-<NUM> page table and at least one level-<NUM> page table.

The page table is a special data structure stored in the memory. The page table may be used as an index of the virtual address space and may include a plurality of entries. Each entry includes an association relationship between an entry index address and a physical address. The physical address may be carried in a page table descriptor of the entry. The page table descriptor may be used to indicate a base address of a next-level page table or a base address of a physical address corresponding to the virtual address. For example, in the level-<NUM> mapping, a page table descriptor in the level-<NUM> page table is used to indicate a segment base address, and the segment base address is a base address of a physical address corresponding to a virtual address. In level-<NUM> mapping, the page table descriptor in the level-<NUM> page table is used to indicate a base address of the level-<NUM> page table, the page table descriptor in the level-<NUM> page table may be used to indicate a page base address, and the page base address is a physical address base address of a page corresponding to the virtual address.

Certainly, in an actual application, the page table descriptor may be further used to indicate more information related to virtual-physical address mapping. For example, the page table descriptor further includes a mapping level indicator bit and a granularity indicator bit. The mapping level indicator bit may be used to indicate a mapping level of current mapping or whether a mapping level indicator bit (that is, level-<NUM> mapping or level-<NUM> mapping) of a next-level mapping exists. The granularity indicator bit may be used to indicate a granularity indicator bit of segment mapping or page mapping (that is, a size of a virtual address space associated with a page table).

<FIG> is a schematic diagram of a logical relationship among a virtual address space, a page table, and a physical address space according to an embodiment of this application. An address range of the virtual address space is [0x00000000, 0xFFFFFFFF], and a size of the virtual address space is <NUM> GB. An address range of a user mode address space is [0x00000000, 0x80000000) (that is, the 0th GB to the 2nd GB), an address range of a kernel mode address space is [0x80000000, 0xFFFFFFFF] (that is, the 2nd GB to the 4th GB), an address range of the physical address space is (0x40000000, 0XBFFFFFFF), and a size is <NUM> GB. A base address of a page table <NUM> that is stored in a TTBR <NUM> is set through the TTBCR. A physical address in the physical address space to which a virtual address of a kernel mode address space <NUM> is mapped is determined through the page table <NUM>. Based on a base address of a page table <NUM> that is stored in a TTBR <NUM>, a physical address in the physical address space to which a virtual address of the user mode address space is mapped is determined through a page table <NUM>.

<FIG> is a schematic diagram of a page table descriptor of a level-<NUM> page table according to an embodiment of this application. In a <NUM>-bit operating system, a 0th bit and a 1st bit of the page table descriptor are mapping level indicator bits. When the [<NUM>:<NUM>]th bits (that is, the 0th bit and the 1st bit) are <NUM>, current mapping is level-<NUM> mapping (that is, segment mapping), and the highest <NUM> or <NUM> bits in the page table descriptor store a segment base address. When the [<NUM>:<NUM>]th bits are <NUM>, the current mapping is level-<NUM> mapping (that is, page mapping), and the most highest <NUM> bits in the page table descriptor store a base address of a level-<NUM> page table. An 18th bit of the page table descriptor may be a mapping granularity indicator bit. When the [<NUM>]th bit is <NUM>, a mapping granularity is <NUM> MB, and the most highest <NUM> bits in the page table descriptor store a segment base address. When the [<NUM>]th bit is <NUM>, the mapping granularity is <NUM> MB, and the most highest <NUM> bits in the page table descriptor store a segment base address.

<FIG> is a schematic diagram of a structure of a page table descriptor of a level-<NUM> page table according to an embodiment of this application. In a <NUM>-bit operating system, the [<NUM>:<NUM>]th bits in the page table descriptor are mapping granularity indicator bits. When the [<NUM>:<NUM>]th bits are <NUM> or <NUM>, a mapping granularity is <NUM> KB, and the highest <NUM> bits in the page descriptor are a page base address. When the [<NUM>:<NUM>]th bits are <NUM>, the mapping granularity is <NUM> KB, and the highest <NUM> bits in the page descriptor are the page base address.

In addition, based on different mapping levels, bits of a virtual address in the virtual address space also have different meanings. The virtual address may include at least a level-<NUM> page table index bit and a physical address offset bit. Each level of index bit may be used to indicate a specific location of a page table descriptor corresponding to the virtual address in the level of page table. A physical address offset bit may be used to indicate an offset of a physical address corresponding to the virtual address. A sum of the physical address offset bit and a physical address base address (for example, a segment base address or a page base address) determined by a page table set corresponding to the virtual address space is a physical address corresponding to the virtual address.

For example, the operating system in the electronic device is <NUM> bits, level-<NUM> mapping is used. A mapping granularity is <NUM> MB, [<NUM>:<NUM>]th bits in the virtual address are level-<NUM> page table index bits, and [<NUM>:<NUM>]th bits are segment offset bits. Alternatively, when level-<NUM> mapping is used, a mapping granularity is <NUM> KB, [<NUM>:<NUM>]th bits in a second virtual address are level-<NUM> page table index bits, [<NUM>:<NUM>]th bits are level-<NUM> page table index bits, and [<NUM>:<NUM>]th bits are page offset bits.

It can be learned from the foregoing description that a start virtual address of the virtual address space may not start from <NUM>. However, in some embodiments, the page table is used as an index of the virtual address space, and entries included in the page table are allocated based on the virtual address from <NUM> to the maximum virtual address of the virtual address space. Therefore, a quantity of entries in the page table is greater than a quantity of entries actually required by the virtual address space, some entries with relatively low index addresses in the page table are not used, memory space occupied by these entries is wasted, and memory usage is low.

<FIG> is a schematic diagram of a logical relationship between a virtual address space, a page table, and a physical address space. In a <NUM>-bit operating system, an address range of a kernel mode address space <NUM> is [0x80000000, 0xFFFFFFFF], an address range of a physical address space <NUM> is [0x40000000, 0XBFFFFFFF], mapping is performed through a level-<NUM> page table <NUM> (that is, the level-<NUM> page table <NUM> corresponds to the kernel mode address space <NUM>). Each entry in the level-<NUM> page table is associated with a <NUM> MB virtual address. Therefore, a total of <NUM> GB/<NUM> MB=<NUM> (that is, <NUM>) entries are required, each entry needs to occupy <NUM> B memory, and the level-<NUM> page table <NUM> needs to occupy <NUM> KB memory in total. A start address of the kernel mode address space <NUM> is 0x80000000, and a corresponding entry index is 0x80000000/0x100000=0x800. Based on the entry index 0x800, it may be determined that a physical address corresponding to 0x80000000 is 0x40000000. However, it can be learned from <FIG> that, in this level-<NUM> page table <NUM>, when the physical address corresponding to the virtual address in the kernel mode address space <NUM> is determined, only <NUM> (that is, <NUM>) entries which are greater than or equal to 0x800 in a high address direction are actually occupied. The <NUM> entries include a page table descriptor, and <NUM> entries in a low address direction [0X000, 0X7FF] are not used. Therefore, the <NUM> KB memory occupied by the <NUM> entries in the low-address direction is wasted. Similarly, a same problem also exists in secondary page tables such as a level-<NUM> page table and a level-<NUM> page table.

To resolve this technical problem, an embodiment of this application provides a method for determining a physical address.

In this embodiment of this application, when obtaining the first virtual address in the first virtual address space, the MMU may determine the first entry index address corresponding to the first virtual address in the first page table, and determine, from the first page table based on the first entry index address, the first target physical address corresponding to the first virtual address. The first page table may be used to determine a physical address corresponding to each virtual address in the first virtual address space, the start virtual address of the first virtual address space corresponds to the second entry index address in the first page table, the second entry index address is greater than or equal to the base address of the first page table, and is less than the sum of the base address of the first page table and the quotient of dividing the start virtual address by the size of the second virtual address space, the largest entry index address of the first page table is less than the sum of the base address of the first page table and the quotient of dividing the largest virtual address of the first virtual address space by the size of the second virtual address space, and the second virtual address space is virtual address space associated with any entry in the first page table. Therefore, the first page table may include at least an entry actually required by the first virtual address space. This saves memory and improves memory utilization.

Specific embodiments are used below to describe in detail the technical solutions of this application. The following several specific embodiments may be combined with each other, and a same or similar concept or process may not be described repeatedly in some embodiments.

Before the MMU performs, for the first time, the method for determining the physical address provided in this embodiment of this application, initialization setting needs to be performed on the MMU.

<FIG> is a flowchart of mapping initialization setting according to an embodiment of this application.

To reduce memory occupied by a page table, for a page table in which a quantity of included entries is greater than a quantity of page tables actually required by a corresponding virtual address space, a page table descriptor in the page table may be offset downward (that is, in a low address direction) based on a position in the page table. In this way, a quantity of unused entries is reduced, and saved storage space may be released or used as common memory.

Optionally, a second page table corresponding to a first virtual address space may be obtained. If a fourth entry index address is greater than a base address of a second page table, it may be determined that an unused entry exists in the second page table, page table descriptors in the second page table may be sequentially offset downward by entries of the first entry quantity, and entries of the first entry quantity in the high address part of the second page table are deleted, so as to obtain a first page table corresponding to the first virtual address space.

The first page table and the second page table may be used to determine a physical address corresponding to each virtual address in the first virtual address space. The fourth entry index address is an entry index address, in the second page table, corresponding to a start virtual address of the first virtual address space. When the page table descriptors in the second page table are sequentially offset downward by the entries of the first entry quantity, the fourth entry index address is the same as a second entry index address, and the second entry index address is an entry index address, in the first page table, corresponding to a start address of the first virtual address space. The first page table may include at least one entry. The start virtual address of the first virtual address space corresponds to a second entry index address of the first page table. The second entry index address is greater than or equal to a base address of the first page table, and is less than a sum of the base address of the first page table and a quotient of dividing the start virtual address of the first virtual address space by the size of the second virtual address space associated with the entry. The largest entry index address of the first page table is less than a sum of the base address of the first page table and a quotient of dividing the largest virtual address of the first virtual address space by the size of the second virtual address space. The second virtual address space may be a virtual address space corresponding to each entry in the first page table or the second page table, and the second virtual address space may be a subset of the first virtual address space.

Optionally, the first entry quantity may be greater than <NUM> and less than or equal to a second entry quantity.

<FIG> is a schematic diagram of a logical relationship between a virtual address space and a page table according to an embodiment of this application. It can be learned from <FIG> that virtual address space associated with a second page table <NUM> is a first virtual address space <NUM>, the second page table <NUM> includes a plurality of entries <NUM>, a virtual address space associated with each entry <NUM> is a second virtual address space <NUM>, the second virtual address space is a subset of the first virtual address space, and a size of the first virtual address space = a quantity of entries <NUM> * a size of the second virtual address space.

Certainly, in actual application, the first virtual address space may alternatively be obtained first. If the start virtual address of the first virtual address space is greater than <NUM>, the fourth entry index address in the second page table may be greater than the base address of the second page table. Therefore, the page table descriptor of the second page table may be sequentially offset downward by the entries of the first entry quantity corresponding to the second page table, to obtain the first page table.

Optionally, the first virtual address space is kernel mode address space. It can be learned from <FIG> that storage space of the first virtual address space is <NUM> GB, an address range is [0x80000000, 0xFFFFFFFF], and a start virtual address is 0x80000000. A second page table corresponding to the kernel mode address space is a level-<NUM> page table <NUM>. Each entry corresponds to <NUM> MB second virtual address space, each entry occupies 4B memory, and a fourth entry index address corresponding to the start virtual address in the level-<NUM> page table <NUM> is 0X800. Because 0X800 is greater than the base address 0X00 of the level-<NUM> page table, 0X00 to 0X7FF in the level-<NUM> page table <NUM> have a total of <NUM> GB/<NUM> MB=<NUM> entries that are not used. In this case, if the level-<NUM> page table <NUM> is offset, a maximum of <NUM> entries may be offset. When a page table descriptor in the level-<NUM> page table <NUM> is offset downward by <NUM> entries, it is obtained that the first page table is a level-<NUM> page table <NUM>, as shown in <FIG>. In the level-<NUM> page table <NUM>, a second entry index address is 0X00. A physical address associated with 0X00 is the same as a physical address associated with 0X800 in the level-<NUM> page table <NUM> in <FIG>, and both are 0x40000000. However, compared with the level-<NUM> page table <NUM>, it can be learned that the level-<NUM> page table <NUM> saves memory of <NUM>*4B=8KB.

It should be noted that offset manners of secondary page tables such as the level-<NUM> page table and the level-<NUM> page table may be similar to offset manners of the level-<NUM> page table. Details are not described in this embodiment of this application.

The register configuration may include adding an offset indicator bit to a reserved bit of the TTBCR and setting the offset indicator bit to a first indicator or a second indicator, and may further include specifying a TTBR for which address virtual mapping is currently performed.

Optionally, an ALU used to implement a virtual address offset operation may be added to an MMU.

To achieve compatibility with the conventional technology and reduce user perception, an offset indicator bit (denoted as offset <NUM>) may be added to the reserved bit of the TTBCR to indicate whether to offset the virtual address. If the offset <NUM> is set to <NUM>, it indicates that an offset function is enabled, and the ALU performs offset calculation on the virtual address. If the offset <NUM> is set to <NUM>, it indicates that the offset function is disabled, and the ALU does not perform an offset operation on the virtual address, or directly transmits the virtual address to a subsequent functional module. In addition, the TTBR currently used for the virtual-physical address mapping may be indicated through the TTBCR.

For example, in a startup process of the operating system, the offset indicator bit may be configured by using the following instruction, to instruct to enable the offset function:.

It should be noted that, in this embodiment of this application, the offset indicator bit in the TTBCR is used to indicate whether to offset the virtual address. When the offset indicator bit is <NUM>, the offset indicator bit can be used as page table offset flag information indicating that the virtual address is offset. However, it may be understood that, in actual application, information in another form may be used as the page table offset flag information. A form of the page table offset flag information is not specifically limited in this embodiment of this application.

In addition, in another possible implementation, the page table offset flag information may not be set, including that the offset indicator bit is not added to the reserved bit of the TTBCR. In this case, in a subsequent process of determining the physical address, the page table offset flag information does not need to be obtained.

It should be noted that, in actual application, S601 may also be performed on any occasion before S603.

After the MMU is initialized, the MMU can determine the physical address by performing the following steps.

<FIG> is a flowchart of a method for determining a physical address according to an embodiment of this application. It should be noted that the method is not limited to a specific sequence described in <FIG> and the following. It should be understood that in another embodiment, a sequence of some steps in the method may be exchanged according to an actual requirement, or some steps in the method may be omitted or deleted.

S901: An MMU obtains a first virtual address in a first virtual address space.

Because a CPU needs to access memory in a running process, but the CPU directly accesses a virtual address, to convert the access into access for a physical address of the memory, the MMU may obtain a virtual address from the CPU. Because a first page table associated with the first virtual address space is an offset page table, different manners may be used to determine a first target physical address corresponding to the first virtual address in the first virtual address space and determine a physical address corresponding to a virtual address that does not belong to the first virtual address space. Therefore, to facilitate a manner used for subsequently determining the physical address corresponding to the virtual address, whether the virtual address is the first virtual address in the first virtual address space may be determined.

The MMU may determine an address range of the first virtual address space in advance, and compare the obtained virtual address with a start virtual address and an end virtual address of the first virtual address space. If the virtual address is greater than or equal to the start virtual address and less than or equal to an end virtual address, the virtual address may be determined as the first virtual address.

For example, referring to <FIG> and <FIG> again, the first virtual address space is the kernel mode address space, the address range of the first virtual address space is [0x80000000, 0xFFFFFFFF], a corresponding first page table is a level-<NUM> page table <NUM>, and the level-<NUM> page table <NUM> is obtained by migrating the level-<NUM> page table <NUM>. Therefore, if the obtained first virtual address is any one of [0x80000000, 0xFFFFFFFF], S902 may be performed.

S902: The MMU obtains page table offset flag information. If the page table offset flag information is obtained, S903 is performed. If the page table offset flag information is not obtained, S905 is performed.

It can be learned from the foregoing that, in this embodiment of this application, the page table may be offset. Correspondingly, a manner of determining the physical address corresponding to the first virtual address is different from that when the page table is not offset. To enable the MMU to be compatible with two different manners of determining the physical address when the page table is offset or not offset, the page table offset flag information may be set, and the page table offset flag information is obtained when the physical address corresponding to the first virtual address is determined. If the page table offset flag information is obtained when the physical address corresponding to the first virtual address is determined, it may be determined that the page table is offset. In this case, the physical address may be determined in a corresponding manner in a subsequent step.

Optionally, the MMU may obtain an offset indicator bit in the TTBCR. If the offset indicator bit is a first indicator (for example, <NUM>), the MMU may determine that the page table offset flag information is obtained, and S903 is performed. If the offset indicator bit is a second indicator (for example, <NUM>), the MMU may determine that the page table offset flag information is not obtained, and S905 is performed.

Certainly, in an actual application, if the page table offset flag information further has another form, whether the page table offset flag information is obtained may also be determined in another corresponding manner. For example, in another possible implementation, an offset indication module may be additionally disposed in the MMU. The offset indication module may include a specific character string that can be used as the page table offset flag information. The specific character string may be obtained from the offset indication module. If the specific character string is obtained, it may be determined that the page table offset flag information is obtained. If the specific character string is not obtained, it may be determined that the page table offset flag information is not obtained.

It should be noted that, in an actual application, compatibility when the page table is not offset may not be considered, that is, S902 is not performed, but S903 is directly performed after S901. In other words, S902 is an optional step.

S903: The MMU determines a first entry index address corresponding to the first virtual address in the first page table.

It can be learned from the foregoing description that an entry in the page table includes an association relationship between an entry index address and a physical address. Therefore, to determine a first target physical address corresponding to the first virtual address, the first entry index address corresponding to the first virtual address in the first page table may be first determined.

In a possible implementation, when the MMU determines the first entry index address corresponding to the first virtual address in the first page table, because a page table descriptor stored in an entry in the first page table before and after offset may change, and a physical address associated with the entry may also change, that is, an entry index associated with a same physical address changes, the first entry index address corresponding to the first virtual address in the first page table may be determined in the following manner <NUM> or manner <NUM>.

Manner <NUM>: The MMU determines a second virtual address based on the first virtual address and a first offset value. The MMU determines the first entry index address based on the second virtual address. The first virtual address is greater than the second virtual address. In other words, the second virtual address is equal to a value obtained by subtracting the first offset value from the first virtual address.

In the manner <NUM>, the MMU first performs a corresponding offset on the first virtual address.

The MMU may determine the second virtual address based on the first virtual address and the first offset value by using an ALU.

It should be noted that the first offset value may be determined in advance, and the first offset value may be less than or equal to the start virtual address of the first virtual address space. The first offset value = a first entry quantity corresponding to the first page table * a size of a second virtual address space associated with each entry in the first page table, and the second virtual address = the first virtual address - the first offset value.

For example, an operating system of an electronic device is <NUM> bits. As shown in <FIG> and <FIG>, the first page table is a level-<NUM> page table, the level-<NUM> page table is offset downward by <NUM> entries, and a page table descriptor in each entry is associated with <NUM> MB virtual address space. In this case, the first offset value = <NUM> * 1MB = 2GB, that is, 0x80000000.

When completing offsetting on the first virtual address and determining the second virtual address, the MMU may determine a base address of the first page table, and determine the first entry index address based on the base address of the first page table and the second virtual address. In addition, when the first target physical address corresponding to the first virtual address is determined, searching is sequentially performed from the level-<NUM> page table, a level-<NUM> page table, a level-<NUM> page table. , until the corresponding first target physical address is found. Therefore, the first entry index address may be determined based on the base address of the first page table and the second virtual address in the following two possible implementations:
In a possible implementation, when the first page table is the level-<NUM> page table, the first virtual address may be compared with a virtual address space corresponding to each TTBR. If the first virtual address belongs to a virtual address space (a first virtual space may be a subset of the virtual address space corresponding to a TTBR) corresponding to the TTBR, the base address of the first page table is obtained from the TTBR corresponding to the virtual address space. A sum of the base address of the first page table and a level-<NUM> page table index bit in the second virtual address is determined as the first entry index address.

To describe the manner <NUM> in detail, <FIG> is a schematic diagram of a logical relationship between a virtual address space, a page table, and a physical address space according to an embodiment of this application. The operating system in the electronic device is <NUM> bits, the first virtual address space is a kernel mode address space <NUM>, and an address range is [0x80000000, 0xFFFFFFFF]. For example, the first virtual address in the first virtual address space is 0x80100000. An MMU may determine that a TTBR corresponding to a kernel mode address space <NUM> is a TTBR <NUM>, and obtain, from the TTBR <NUM>, a base address 0X000 of a level-<NUM> page table <NUM>. It can be learned from a page table descriptor in a 0X000 entry that, if mapping level indicator bits [<NUM>:<NUM>] of a page table descriptor are <NUM>, and a granularity indicator bit [<NUM>] is <NUM>, it is determined that current mapping is level-<NUM> mapping, and a mapping granularity is <NUM> MB. Therefore, the first virtual address is offset downward by 0x80000000, to obtain a second virtual address 0x00100000, where [<NUM>:<NUM>]th bits in the second virtual address are level-<NUM> page table index bits, and [<NUM>:<NUM>]th bits are segment offset bits. The MMU determines a sum 0X001 of the [<NUM>:<NUM>]th bits 0X001 of the first virtual address and the base address 0X000 of the level-<NUM> page table as the first entry index address, where a page table descriptor in the 0X001 entry can indicate that a first target physical address associated with 0x80100000 is 0x40100000. Certainly, if the mapping level indicator bits [<NUM>:<NUM>] of the page table descriptor are <NUM>, it is determined that a level-<NUM> page table is further included. The [<NUM>:<NUM>]th bits of the page table descriptor are base addresses of the level-<NUM> page table. Correspondingly, the [<NUM>:<NUM>]th bits in the second virtual address are the level-<NUM> page table index bits, [<NUM>:<NUM>]th bits are level-<NUM> page table index bits, and [<NUM>:<NUM>]th bits are page offset bits.

In another possible implementation, when the first page table is a secondary page table, the base address of the first page table may be determined based on a third page table, and the first entry index address is determined based on the base address of the first page table and the second virtual address, where the third page table is a previous-level page table adjacent to the first page table.

For example, the first page table is the level-<NUM> page table, and the third page table is the level-<NUM> page table. The MMU may obtain a base address of the level-<NUM> page table from the page table descriptor based on a granularity indicator bit of a page table descriptor in the third page table, obtain a level-<NUM> page table index bit from the first virtual address space, and determine a sum of the base address of the level-<NUM> page table and the level-<NUM> page table index bit as the first entry index address.

For example, the operating system in the electronic device is <NUM> bits, and the MMU determines that the mapping level indicator bits [<NUM>:<NUM>] of the page table descriptor that are in the level-<NUM> page table and that correspond to the first virtual address are <NUM>, that is, determines that the level-<NUM> page table is further included. In this case, the [<NUM>:<NUM>]th bits of the page table descriptor are obtained as the base addresses of the level-<NUM> page table, the [<NUM>: <NUM>]th bits of the second virtual address are obtained as level-<NUM> page table index bits, and a sum of the base addresses of the level-<NUM> page table and the level-<NUM> page table index bits is determined as the first entry index address.

It should be noted that, when the first page table is another secondary page table, a manner of determining the first entry index address based on the second virtual address may be similar to a manner when the first page table is a secondary page table.

Manner <NUM>: The MMU determines, based on the first virtual address, a third entry index address to be offset, and determines the first entry index address based on the third entry index address and the second offset value.

When the first page table is the level-<NUM> page table, the MMU may determine the base address of the level-<NUM> page table in a manner similar to the foregoing manner, obtain a level-<NUM> page table index bit from the first virtual address, determine a sum of the level-<NUM> page table index bit and the base address of the level-<NUM> page table as the third entry index address, and then offset the third entry index address, including subtracting the second offset value from the third entry index address, to obtain a first entry index address.

It should be noted that the second offset value may be determined in advance, and the second offset value = a first entry quantity.

To describe the manner <NUM> in detail, <FIG> is a schematic diagram of a logical relationship between a virtual address space, a page table, and a physical address space according to an embodiment of this application. An operating system in an electronic device is <NUM> bits, the first virtual address space is a kernel mode address space <NUM>, and an address range is [0x80000000, 0xFFFFFFFF]. A first virtual address in the first virtual address space is 0x80100000. An MMU may determine that a TTBR corresponding to the kernel mode address space <NUM> is a TTBR <NUM>, and obtain, from the TTBR <NUM>, a base address 0X000 of a level-<NUM> page table <NUM>. It can be learned from the page table descriptor in the 0X000 entry that, if mapping level indicator bits [<NUM>:<NUM>] of the page table descriptor are <NUM>, and a granularity indicator bit [<NUM>] is <NUM>, it is determined that the current mapping is level-<NUM> mapping, and a mapping granularity is <NUM> MB. Therefore, [<NUM>:<NUM>]th bits in 0x80100000 in the first virtual address are level-<NUM> page table index bits, and [<NUM>:<NUM>]th bits are segment offset bits. The MMU determines a sum 0X801 of the [<NUM>:<NUM>]th bits 0X801 of the first virtual address and the base address 0X000 of the level-<NUM> page table as a third entry index address, and then determines a difference obtained by subtracting a first entry quantity 0X800 (a hexadecimal value corresponding to a binary value <NUM>) from the third entry index address (0X801) as the first entry index address 0X001.

S904: The MMU determines, from the first page table based on the first entry index address, a first target physical address corresponding to the first virtual address.

Because the first entry index address is an entry index address corresponding to the first virtual address, an entry corresponding to the first virtual address in the first page table may be determined based on the first entry index address, and the first target physical address is determined based on the entry.

When the first page table is a last-level page table (for example, a level-<NUM> page table in level-<NUM> mapping or a level-<NUM> page table in level-<NUM> mapping), the page table descriptor in the entry corresponding to the first entry index address may indicate a base address of the first target physical address. Therefore, the MMU may obtain the base address of the first target physical address from the page table descriptor, obtain a physical address offset bit from the first virtual address or the second virtual address, and determine a sum of the base address of the first target physical address and the physical address offset bit as the first target physical address. When the first page table is not the last-level page table, the first representation index address may indicate a base address of a next-level page table. The MMU may continue to search the next-level page table for the first entry index address corresponding to the first virtual address until the last-level page table is found, so as to determine the first target physical address. In other words, the MMU may perform S903 and S904 at least once, to determine the first target physical address corresponding to the first virtual address by sequentially obtaining the level-<NUM> page table, the level-<NUM> page table, the level-<NUM> page table, and the like.

It should be noted that, when the first virtual address is offset, the offset is actually the at least level-<NUM> page table index bit in the first virtual address, and the physical address offset bit does not change. Therefore, the MMU may obtain the physical address offset bit from the first virtual address or the second virtual address.

Still refer to <FIG> and <FIG>. Because the first page table is the level-<NUM> page table <NUM>, a page table descriptor in a 0X001 entry in the level-<NUM> page table <NUM> indicates the base address 0x40100000 of the first target physical address corresponding to the first virtual address 0x80100000, and both the first virtual address 0x80100000 and the [<NUM>:<NUM>]th bits of the second virtual address are <NUM>, that is, the physical address offset bit is <NUM>. Therefore, the first target physical address is 0x40100000+0x00000000=0x40100000. Certainly, if the mapping level indicator bits [<NUM>:<NUM>] of the page table descriptor are <NUM>, it is determined that the level-<NUM> page table is further included, and the [<NUM>:<NUM>]th bits of the page table descriptor are base addresses of the level-<NUM> page table. In this case, S605 may be returned, to determine the first target physical address from the level-<NUM> page table.

It can be learned from the foregoing that, in a process of determining the first target physical address corresponding to the first virtual address, the MMU may need to search for a plurality of levels of page tables. The first page table may be any level of page table, that is, any page table may have an offset. If the MMU first offsets the first virtual address to obtain the second virtual address, and then determines the corresponding first entry index address from the first page table based on the second virtual address, regardless of which page tables in the plurality of levels of page tables are offset, the obtained second virtual address may match the offset page table provided that the first virtual address is offset at least once. If the MMU first determines the third entry index address based on the first virtual address, and then offsets the third entry index address to obtain the first entry index address, when determining the first entry index address in the offset page table at each layer, the MMU may separately offset the third entry index address for the page table to obtain the first entry index address.

S905: Determine a third entry index address corresponding to the first virtual address in the second page table corresponding to the first page table, and determine, from the second page table corresponding to the first page table based on the third entry index address, a second target physical address corresponding to the first virtual address.

An operation manner of S905 may be similar to that of S903 and S904, and a difference lies in that the first virtual address or the third entry address does not need to be offset in S905.

It should be noted that, in this embodiment of this application, the first page table is obtained by offsetting the entries in the second page table. Therefore, the first target physical address determined from the first page table by using S903 and S904 may be the same as the second target physical address determined from the second page table by using S905. The memory of the electronic device may store only the first page table or the second page table. If the first page table is stored, the MMU can obtain the page table offset flag information in S902, so as to perform S903 and S904. If the second page table is stored, the MMU cannot obtain the page table offset flag information in S902, and therefore S905 is performed.

It may be understood that if the MMU determines the first target physical address and the second target physical address from a same page table (the first page table or the second page table) separately based on S903, S904, and S905, the determined first target physical address and the determined second target physical address may be different.

In addition, in this embodiment of this application, a page table descriptor in the second page table including a redundant entry is offset downward, to reduce or eliminate redundant entries, to obtain the first page table including fewer entries. In actual application, to make a manner of setting a page table and determining a physical address more flexible, the second page table may also be offset upward (that is, in a high address direction). In this case, the second page table may be any page table, a quantity of third entries offset upward may also be any value, and the obtained first page table may include more entries. Correspondingly, when determining the first entry index address corresponding to the first virtual address, the MMU may determine a sum of the first virtual address and the first offset value as the second virtual address (that is, the first virtual address is also offset in the high address direction), and then determine the first entry index address based on the second virtual address, or may determine a to-be-offset third entry index address based on the first virtual address, and determine a sum of the third entry index address and the second offset value as the first entry index address (that is, the third entry index address is also offset in the high address direction). When the first entry index address is determined, the first target physical address corresponding to the first virtual address is determined from the first page table based on the first entry index address.

The first offset value = the third entry quantity * the size of the second virtual address space associated with each entry in the first page table, the second offset value = the third entry quantity, the first virtual address may be less than the second virtual address, and the third entry index address may be less than the first entry index address.

Based on a same inventive concept, an embodiment of this application further provides a chip system <NUM>.

Refer to <FIG>. The chip system <NUM> includes at least one CPU <NUM> (only one is shown in <FIG>), at least one memory <NUM> (only one is shown in <FIG>), and at least one coprocessor <NUM> (only one is shown in <FIG>). The at least one coprocessor <NUM> includes at least one MMU <NUM> (only one is shown in <FIG>). The MMU <NUM> includes at least one ALU <NUM> (only one is shown in <FIG>), at least one TTBCR <NUM> (only one is shown in <FIG>), and at least one TTBR <NUM> (only one is shown in <FIG>).

The at least one MMU <NUM> is configured to:.

The first page table is used to determine a physical address corresponding to each virtual address in the first virtual address space, a start virtual address of the first virtual address space corresponds to a second entry index address in the first page table, the second entry index address is greater than or equal to a base address of the first page table and less than a sum of the base address of the first page table and a quotient of dividing the start virtual address by a size of a second virtual address space, a largest entry index address of the first page table is less than a sum of the base address of the first page table and a quotient of dividing a largest virtual address of the first virtual address space by the size of the second virtual address space, and the second virtual address space is virtual address space associated with any entry in the first page table.

Optionally, the at least one ALU <NUM> is configured to determine a second virtual address based on a first virtual address and a first offset value, where the first virtual address is greater than the second virtual address.

The at least one MMU <NUM> is further configured to determine a first entry index address based on the second virtual address.

Optionally, the at least one MMU <NUM> is further configured to:.

Optionally, the at least one MMU <NUM> is further configured to:
obtain page table offset flag information, where the page table offset flag information is indicated by an offset indicator bit in the at least one TTBCR <NUM>.

Optionally, each TTBR <NUM> may store a base address of one level-<NUM> page table. Correspondingly, the TTBCR <NUM> may be used to indicate TTBRs <NUM> selected when physical addresses corresponding to virtual addresses in different virtual address spaces are determined. In other words, the TTBRs <NUM> corresponding to different virtual address spaces are determined.

Optionally, the at least one coprocessor <NUM> may be integrated into at least one CPU <NUM>.

It should be noted that the memory <NUM> may include an internal memory <NUM> in <FIG>.

<FIG> is a schematic diagram of a structure of another chip system <NUM> according to an embodiment of this application. The system <NUM> includes a CPU <NUM>, an ALU <NUM>, a TTBCR <NUM>, a virtual memory conversion module <NUM>, and a memory <NUM>, where the TTBCR <NUM>, the ALU <NUM>, and the virtual memory conversion module <NUM> may be disposed in an MMU <NUM>, and the MMU <NUM> may be disposed in a coprocessor, or may be integrated in the CPU <NUM>.

The CPU <NUM> may send an access request to the memory <NUM>, where the access request carries a first virtual address of a kernel mode address space. When obtaining the first virtual address and determining that an offset indicator bit in the TTBCR <NUM> is a first indicator (for example, offset <NUM>), the ALU <NUM> offsets the first virtual address to a second virtual address. The virtual memory conversion module <NUM> determines, based on the second virtual address, a first entry index address from a page table set corresponding to the kernel mode address space, and further determines a first target physical address. The CPU <NUM> may access an internal memory <NUM> based on the first target physical address.

It should be noted that the ALU <NUM>, the TTBCR <NUM>, and the virtual memory conversion module <NUM> may be disposed in the MMU <NUM>, and the MMU <NUM> may further include a TTBR <NUM>.

It should be further noted that the virtual memory conversion module <NUM> may be configured to determine the first entry index address based on a third entry index address and a second offset value.

Based on a same inventive concept, an embodiment of this application further provides an electronic device. The electronic device includes any one of the foregoing chip systems.

An embodiment of this application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the method in the foregoing method embodiment is implemented.

An embodiment of this application further provides a computer program product. When the computer program product runs on an electronic device, the electronic device is enabled to perform the method in the foregoing method embodiments.

When the foregoing integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, the integrated unit may be stored in a computer-readable storage medium. Based on such an understanding, all or some of the procedures of the method in embodiments of this application may be implemented by a computer program instructing related hardware. The computer program may be stored in a computer-readable storage medium. When the computer program is executed by the processor, steps of the foregoing method embodiments may be implemented. The computer program includes computer program code. The computer program code may be in a source code form, an object code form, an executable file form, some intermediate forms, or the like. The computer-readable storage medium may include at least any entity or apparatus capable of carrying the computer program code to a photographing apparatus/terminal device, a recording medium, a computer memory, a read-only memory (read-only memory, ROM), a random access memory (random access memory, RAM), an electrical carrier signal, a telecommunications signal, and a software distribution medium, for example, a USB flash drive, a removable hard disk, a magnetic disk, or an optical disc. In some jurisdictions, the computer-readable medium cannot be the electrical carrier signal or the telecommunication signal according to legislation and patent practices.

For a part that is not described in detail or recorded in an embodiment, refer to related descriptions in other embodiments.

A person skilled in the art may use different methods to implement the described functions for each particular application, but it should not be considered that the implementation goes beyond the scope of the appended claims.

In embodiments provided in this application, it should be understood that the disclosed apparatus/ device and method may be implemented in other manners. For example, the described apparatus/device embodiment is merely an example. For example, division into the modules or units is merely logical function division and may be other division in an actual implementation. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections may be implemented through some interfaces.

It should be understood that, when used in the specification and the appended claims of this application, the term "include" indicates presence of the described features, entireties, steps, operations, elements, and/or components, but does not exclude presence or addition of one or more other features, entireties, steps, operations, elements, components, and/or sets thereof.

It should also be understood that the term "and/or" used in the specification and the appended claims of this application refers to any combination and all possible combinations of one or more associated listed items, and includes these combinations.

As used in the specification and the appended claims of this application, according to the context, the term "if" may be interpreted as "when" or "once" or "in response to determining" or "in response to detecting". Likewise, the phrase "if it is determined that" or "if (a described condition or event) is detected" may be interpreted as a meaning of "once it is determined that" or "in response to determining" or "once (a described condition or event) is detected" or "in response to detecting (a described condition or event)" depending on the context.

In addition, in the descriptions of the specification and claims of this application, the terms "first", "second", "third", and the like are merely intended for a purpose of differentiated description, but shall not be understood as an indication or an implication of relative importance.

Reference to "an embodiment", "some embodiments", or the like described in the specification of this application indicates that one or more embodiments of this application include a specific feature, structure, or characteristic described with reference to embodiments. Therefore, statements such as "in an embodiment", "in some embodiments", "in some other embodiments", and "in other embodiments" that appear at different places in this specification do not necessarily mean referring to a same embodiment. Instead, the statements mean "one or more but not all of embodiments", unless otherwise specifically emphasized in another manner. The terms "include", "have", and their variants all mean "include but are not limited to", unless otherwise specifically emphasized in another manner.

Claim 1:
A method for determining a physical address, comprising:
when a first virtual address of a first virtual address space (<NUM>) is obtained (S901), determining a first entry index address (OX) corresponding to the first virtual address); and
determining (S904), from a first page table based on the first entry index address (OX), a first target physical address corresponding to the first virtual address, wherein
the first page table is used to determine a physical address corresponding to each virtual address in the first virtual address space (<NUM>), a start virtual address of the first virtual address space (<NUM>) corresponds to a second entry index address in the first page table, the second entry index address is greater than or equal to a base address of the first page table and less than a sum of the base address of the first page table and a quotient of dividing the start virtual address by a size of a second virtual address space (<NUM>), a largest entry index address of the first page table is less than a sum (OX) of the base address of the first page table and a quotient of dividing a largest virtual address of the first virtual address space (<NUM>) by the size of the second virtual address space (<NUM>), and the second virtual address space (<NUM>) is virtual address space associated with any entry (<NUM>) in the first page table; and
characterised in that
the determining a first entry index address (OX) corresponding to the first virtual address comprises:
determining a second virtual address based on the first virtual address and a first offset value, wherein the first virtual address is greater than the second virtual address (0x); and
determining the first entry index address based on the second virtual address.