Patent Description:
Recently, a neural network system has been widely applied to many AI application systems to provide the intelligent processing capability such as the pattern recognition capability, the data classification capability and the object detection capability. Hereinafter, a neural network system for recognizing numbers will be described. <NPL>, discloses an in-situ processing approach, where memristor crossbar arrays not only store input weights, but are also used to perform dot-product operations in an analog manner.

<FIG> is a schematic diagram illustrating the architecture of a neural network system for recognizing numbers. The neural network system <NUM> is used for recognizing the handwritten numbers on a handwriting board <NUM>. The handwriting board <NUM> is composed of <NUM> (=<NUM>×<NUM>) sensing points.

As shown in <FIG>, the neural network system <NUM> comprises an input layer <NUM>, a hidden layer <NUM> and an output layer <NUM>. Generally, each sensing point on the handwriting board <NUM> corresponds to an input neuron of the input layer. Consequently, the input layer <NUM> comprises <NUM> (=<NUM>×<NUM>) input neurons I<NUM>~I<NUM>. It means that the size of the input layer <NUM> is <NUM>.

Since the neural network system <NUM> has to recognize ten numbers <NUM>~<NUM>, the output layer <NUM> comprises ten output neuron O<NUM>~O<NUM>. It means that the size of the output layer <NUM> is <NUM>.

The hidden layer <NUM> of the neural network system <NUM> comprises <NUM> neurons H<NUM>~H<NUM>. That is, the size of the hidden layer <NUM> is <NUM>. Consequently, the size of the neural network system <NUM> is indicated as <NUM>-<NUM>-<NUM>.

Each connection line between the input layer <NUM> and the hidden layer <NUM> denotes a neuron connection weight. Similarly, each connection line between the hidden layer <NUM> and the output layer <NUM> also denotes a neuron connection weight. Please refer to <FIG>. The neuron connection weights between the <NUM> input neurons I<NUM>~I<NUM> of the input layer <NUM> and the neuron H<NUM> of the hidden layer <NUM> are indicated as IH<NUM>,<NUM>~IH<NUM>,<NUM>. Similarly, the neuron connection weights between the <NUM> input neurons I<NUM>~I<NUM> of the input layer <NUM> and the <NUM> neurons H<NUM>~H<NUM> of the hidden layer <NUM> are indicated as IH<NUM>,<NUM>~IH<NUM>,<NUM> and (IH<NUM>,<NUM>~IH<NUM>,<NUM>)-(IH<NUM>,<NUM>-IH<NUM>,<NUM>). Consequently, there are <NUM>×<NUM> neuron connection weights between the input layer <NUM> and the hidden layer <NUM>.

The <NUM> neurons H<NUM>~H<NUM> of the hidden layer <NUM> are connected with the ten output neurons O<NUM>~O<NUM> of the output layer <NUM>. Consequently, <NUM>×<NUM> neuron connection weights between the neurons H<NUM>~H<NUM> of the hidden layer <NUM> and the output neuron O<NUM>~O<NUM> of the output layer <NUM> are indicated as (HO<NUM>,<NUM>~HO<NUM>,<NUM>)~(HO<NUM>,<NUM>~HO<NUM>,<NUM>). Moreover, the neuron connection weights (IH<NUM>,<NUM>~IH<NUM>,<NUM>)~(IH<NUM>,<NUM>-IH<NUM>,<NUM>) and (HO<NUM>,<NUM>~HO<NUM>,<NUM>)~(HO<NUM>,<NUM>~HO<NUM>,<NUM>) are collaboratively combined as a weight group.

After the values of the neurons of the previous layer are multiplied by the corresponding neuron connection weights and accumulated, the neuron values of the next layer are acquired. Take the neuron value H<NUM> of the hidden layer <NUM> for example. The neuron value H<NUM> of the hidden layer <NUM> is calculated by the following formula: <MAT>.

The other neuron values H<NUM>~H<NUM> of the hidden layer <NUM> also can be calculated by referencing the above formula.

Similarly, the output neuron value O<NUM> of the output layer <NUM> is calculated by the following formula: <MAT>.

The other output neuron values O<NUM>~O<NUM> of the output layer <NUM> also can be calculated by referencing the above formula.

Before the practical applications of the neural network system <NUM>, the neural network system <NUM> has to be in a training phase to acquire all neuron connection weights in the weight group. After all neuron connection weights in the weight group are acquired through many iterations of training, the well-trained neural network system <NUM> is established.

In an application phase, the number written on the handwriting board <NUM> can be recognized by the neural network system <NUM>. As shown in <FIG>, the number "<NUM>" is written on the handwriting board <NUM>. Since the neuron O<NUM> of the output layer <NUM> has the highest value, the number "<NUM>" is recognized by the neural network system <NUM>.

The example of the neural network system <NUM> as shown in <FIG> is presented herein for purpose of illustration and description only. In case that the neural network system is more complicated, the neural network system comprises plural hidden layers to increase the recognition capability. Moreover, the sizes of the hidden layers are not restricted.

Since the multiplication operation and the accumulation operation have to be performed on the neural network system continuously, the use of a computer system can execute the calculations about the multiplication operation and the accumulation operation. For example, all neuron connection weights are stored in the memory of the computer system. Then, a central processing unit (CPU) in the computer system accesses the neuron connection weights from the memory. After the multiplication operation and the accumulation operation are performed according to the neuron connection weights, all neuron values are acquired.

However, as the size of the neural network system is gradually increased, it is necessary to increase the storage capacity of the memory to store the neuron connection weights and the neuron values. Moreover, since the central processing unit has to access the data from the memory, the performance of the computer system is largely reduced and the power consumption of the computer system is increased.

Nowadays, according to the characteristics of the neural network system, a multiply accumulate circuit (also abbreviated as MAC) has been disclosed to calculate the neuron values.

Please refer to <FIG> and <FIG>. <FIG> is a schematic diagram illustrating the architecture of a multiply accumulate circuit. <FIG> is a schematic circuit diagram illustrating a MAC group with plural multiply accumulate circuits. <FIG> is a schematic block diagram illustrating a control circuit.

In <FIG>, the multiply accumulate circuit <NUM> is shown. After the input values X<NUM>~Xn are multiplied by the corresponding weights W<NUM>,j~Wn,j and the products are accumulated, the output value Yj is acquired according to the following formula: <MAT>.

When the multiply accumulate circuit <NUM> is applied to the neural network system, the weights W<NUM>,j~Wn,j of the multiply accumulate circuit <NUM> are the neuron connection weights. Moreover, the input values are the neuron values of the previous layer, and the output value Yj is the neuron value of the next layer.

As shown in <FIG>, the MAC group <NUM> comprises plural multiply accumulate circuits <NUM>~25j. The MAC group <NUM> is used to calculate the size n of the previous layer and the size j of the next layer in the neural network system.

Take the multiply accumulate circuit <NUM> for example. The multiply accumulate circuit <NUM> comprises n electrical conductance elements. The n electrical conductance elements have the conductance values G<NUM>,<NUM>~Gn,<NUM>, respectively. Each electrical conductance element comprises a variable resistor. After the resistance value of the variable resistor is tuned, the reciprocal of the resistance value is the conductance value. For example, if the tuned resistance value is <NUM> ohms (Ω), the conductance value is <NUM> siemens (S). In addition, the conductance values G<NUM>,<NUM>~Gn,<NUM> are tuned according to the neuron connection weights of the neural network system.

Moreover, the n input terminals of the multiply accumulate circuit <NUM> receive n input voltages V1~Vn, respectively. The voltage values of the input voltages V1~Vn denote the neuron values of the previous layer. The output terminal of the multiply accumulate circuit <NUM> generates an output current I1. The output current I1 denotes the neuron value of the next layer. The conductance values G<NUM>,<NUM>~Gn,<NUM> are connected between the n input terminals and the output terminal of the multiply accumulate circuit <NUM>. The structure of each of the multiply accumulate circuits <NUM>~25j is similar to the structure of the multiply accumulate circuit <NUM>, and is not redundantly described herein.

In a training phase of the neural network system, the n×j conductance values G<NUM>,<NUM>~Gn,j of the multiply accumulate circuits <NUM>~25j are tuned and used as n×j neuron connection weights.

In an application phase of the neural network system, the input terminals of the multiply accumulate circuits <NUM>~25j receive the n input voltages V1~Vn, and the output terminals of the multiply accumulate circuits <NUM>~25j are connected with a ground voltage (not shown). Consequently, the output currents I1~Ij from the multiply accumulate circuits <NUM>~25j denote the j neuron values of the next layer.

For example, after the conductance values G<NUM>,<NUM>~Gn,<NUM> of the multiply accumulate circuit <NUM> receive the n input voltages V1~Vn, n currents I<NUM>,<NUM>~In,<NUM> are generated. The n currents I<NUM>,<NUM>~In,<NUM> are superposed into an output current I1 according to the following formula: <MAT>.

As shown in <FIG>, the control circuit <NUM> comprises a digital-to-analog converter (DAC) <NUM>, the MAC group <NUM> and an analog-to-digital converter (ADC) <NUM>. The digital-to-analog converter <NUM> is used for converting digital values into analog voltages. The analog-to-digital converter <NUM> is used for converting analog currents into digital values.

Firstly, the n neuron values Din_1~Din_n of the previous layer are inputted into the digital-to-analog converter <NUM> and converted into the corresponding n input voltages V1~Vn. Then, the MAC group <NUM> receives the n input voltages V1~Vn and generates j output currents I1~lj. Then, the j output currents I1~lj are received by the analog-to-digital converter <NUM> and converted into j neuron values Do_1~DoJ of the next layer. The neuron values Din_1~Din_n and the neuron values Do_1~DoJ are digital values.

In other words, the neural network system of any size can be implemented with the control circuit <NUM> of <FIG>. For example, the size of the neural network system <NUM> as shown in <FIG> is indicated as <NUM>-<NUM>-<NUM>. Consequently, the neural network system <NUM> comprises two control circuits. The first control circuit receives the <NUM> neuron values I<NUM>~I<NUM> of the input layer <NUM> and generates the <NUM> neuron values H<NUM>~H<NUM> of the hidden layer <NUM>. The second control circuit receives the <NUM> neuron values H<NUM>~H<NUM> of the hidden layer <NUM> and generates the output neuron O<NUM>~O<NUM> of the output layer <NUM>.

The report "<NPL>. This report discloses an in-situ processing approach, where memristor crossbar arrays not only store input weights, but also used to perform dot-product operations in analog manner.

The report "<NPL>). It is a survey of recent works in developing neuromorphic or neuro-inspired hardware systems. In particular, it focuses the systems which can either learn from data in an unsupervised or online supervised manner.

The present invention provides a novel structure of a multiply accumulate circuit for a neural network system and an associated control circuit.

An embodiment of the present invention provides a control circuit for a neural network system. The control circuit includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. The first neuron value storage circuit is connected with the n word lines, and includes n registers. Moreover, n neuron values of a first layer are stored in the corresponding registers. The first processor is connected with the first bit line. In an application phase of the neural network system, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values, so that the first multiply accumulate circuit generates plural first bitline currents to the first processor through the first bit line. After the first processor performs an analog computation on the plural first bitline currents to covert the plural first bitline currents into an output current, the output current is converted into a first neuron value of a second layer. The n word lines are activated or inactivated in response to the binary codes of the neuron values, a first portion of the n memristive cells corresponding to the activated word lines generates cell currents, and a second portion of the n memristive cells corresponding to the inactivated word lines does not generate the cell current. The binary codes of the n neuron values of the first layer are L-bit values, and the first neuron value storage circuit sequentially provides one bit of the n neuron values for L times to control the n word lines of the first multiply accumulate circuit, so that the first multiply accumulate circuit generates the first bitline currents for L times.

Numerous objects, features and advantages of the present invention will be readily apparent upon a reading of the following detailed description of embodiments of the present invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting.

The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:.

As is well known, a memristor is an electric component with the characteristics of a resistor. Moreover, by providing a specified bias voltage to set the memristor, the memristor has a specified resistance value. After the specified bias voltage is not provided, the resistance value of the memristor is maintained at the specified resistance value and kept unchanged. For changing the resistance value of the memristor again, it is necessary to provide another bias voltage to the memristor. Generally, the memristor can be applied to a resistive random access memory (also abbreviated as RRAM or ReRAM), a non-volatile memory with a floating gate transistor or any other appropriate non-volatile memory.

<FIG> is a schematic circuit diagram illustrates an example of a memristive cell. As shown in <FIG>, the memristive cell <NUM> comprises a switch transistor M and a memristor R. A first drain/source terminal of the switch transistor M is used as a first terminal t1 of the memristive cell <NUM>. A second drain/source terminal of the switch transistor M is connected with a first terminal of the memristor R. A second terminal of the memristor R is used as a second terminal t2 of the memristive cell <NUM>. A gate terminal of the switch transistor M is used as a control terminal tc of the memristive cell <NUM>. By providing proper bias voltages to the three terminals t1, t2 and tc of the memristive cell <NUM>, the resistance value of the memristor R is correspondingly controlled.

In the memristive cell <NUM> as shown in <FIG>, the switch transistor M is an n-type transistor. In some other embodiments, the switch transistor M is a p-type transistor. Moreover, the memristor R may be implemented with an n-type floating gate transistor or a p-type floating gate transistor.

<FIG> is a schematic circuit diagram illustrates another example of a memristive cell. As shown in <FIG>, the memristive cell <NUM> comprises a switch transistor M and a floating gate transistor F. A first drain/source terminal of the switch transistor M is used as a first terminal t1 of the memristive cell <NUM>. A second drain/source terminal of the switch transistor M is connected with a first drain/source terminal of the floating gate transistor F. A second drain/source terminal of the floating gate transistor F is used as a second terminal t2 of the memristive cell <NUM>. A gate terminal of the switch transistor M is used as a control terminal tc of the memristive cell <NUM>. By providing proper bias voltages to the three terminals t1, t2 and tc of the memristive cell <NUM>, a specified amount of hot carriers are injected into the floating gate. Consequently, the internal resistance value of the floating gate transistor F is correspondingly controlled. The hot carriers are electrons.

Moreover, plural memristive cells <NUM>, plural memristive cells <NUM> or other types of memristive cells may be collaboratively formed as a cell array.

<FIG> is a schematic circuit diagram illustrating a cell array with plural memristive cells. As shown in <FIG>, the cell array comprises plural memristive cells <NUM> as shown in <FIG>. The cell array <NUM> comprises n×j memristive cells c11~cnj. The memristive cells c11~cnj comprises respective switch transistors M<NUM>,<NUM>~Mn,j and respective floating gate transistors F<NUM>,<NUM>~Fn,j. The structure of each of the memristive cells c11~cnj is similar to the structure of the memristive cell <NUM> as shown in <FIG>, and is not redundantly described herein. The first terminals of all memristive cells c11~cnj receive a supply voltage Vs.

The control terminals of the first row of j memristive cells c11~c1j in the cell array <NUM> are connected with a word line WL1. The second terminals of the memristive cells c11~c1j are connected with the corresponding bit lines BL1~BLj, respectively. The control terminals of the second row of j memristive cells c21~c2j in the cell array <NUM> are connected with a word line WL2. The second terminals of the memristive cells c21~c2j are connected with the corresponding bit lines BL1~BLj, respectively. The rest may be deduced by analog.

The cell array <NUM> can be applied to a non-volatile memory to store or receive data. During a program action or a read action of the non-volatile memory, one of the n word lines WL1~WLn in the cell array <NUM> is activated and the other word lines are inactivated. For example, during the program action, the word line WL1 is activated. Meanwhile, various bias voltages are provided to the bit lines BL1~BLj, and different amounts of hot carriers are injected into the floating gates of the floating gate transistors F<NUM>,<NUM>~F<NUM>,j of the j memristive cells c11~c1j. Consequently, the internal resistance values of the floating gate transistors F<NUM>,<NUM>~F<NUM>,j are correspondingly controlled.

In accordance with a feature of the present invention, a multiply accumulate circuit is implemented with the cell array <NUM> as shown in <FIG>. Moreover, the way of controlling the cell array <NUM> is specially designed. That is, the cell array and other circuits collaboratively work to form a control circuit in order to define the multiply accumulate circuit of a neural network system.

<FIG> is a schematic circuit diagram illustrating a control circuit according to an embodiment of the present invention. As shown in <FIG>, the control circuit <NUM> comprises a first neuron value storage circuit <NUM>, a cell array <NUM>, a processing circuit <NUM> and a second neuron value storage circuit <NUM>.

The first neuron value storage circuit <NUM> comprises n registers <NUM>~41n. The n registers <NUM>~41n store n neuron values Din_1~Din_n of the previous layer. The n neuron values Din_1~Din_n are digital values.

The cell array <NUM> comprises n×j memristive cells c11~cnj. The structure of each of the memristive cells c11~cnj is similar to the structure of the memristive cell <NUM> as shown in <FIG>, and is not redundantly described herein. Alternatively, the structure of each of the memristive cells is similar to the structure of the memristive cell <NUM>. It is noted that the structure of the memristive cell is not restricted. Take the memristive cell c11 for example. The memristive cell c11 comprises a switch transistor M<NUM>,<NUM> and a floating gate transistor F<NUM>,<NUM>. A first terminal of the memristive cell c11 receives the supply voltage Vs. A second terminal of the memristive cell c11 is connected with the bit line BL1. A control terminal of the memristive cell c11 is connected with the word line WL1.

The n word lines WL1~WLn of the cell array <NUM> are connected with the first neuron value storage circuit <NUM>. Moreover, each column of n memristive cells in the cell array <NUM> are defined as a multiply accumulate circuit. That is, the cell array <NUM> comprises j multiply accumulate circuits <NUM>~42j. The j multiply accumulate circuits <NUM>~42j are connected with the n word lines WL1~WLn. Moreover, the j multiply accumulate circuits <NUM>~42j are connected with the corresponding bit lines BL1~BLj, respectively. For example, the multiply accumulate circuit <NUM> comprises n memristive cells c11~cn1. The first terminals of the n memristive cells c11~cn1 receive the supply voltage Vs. The second terminals of the n memristive cells c11~cn1 are connected with the bit line BL1. The control terminals of the n memristive cells c11~cn1 are connected with the corresponding word lines WL1~WLn, respectively. The structures of the multiply accumulate circuits <NUM>~42j are similar to the structure of the multiply accumulate circuit <NUM>, and are not redundantly described herein.

The processing circuit <NUM> comprises j processors <NUM>~43j. The j processors <NUM>~43j are connected with the corresponding bit lines BL1~BI_j, respectively. The second neuron value storage circuit <NUM> is connected with the processing circuit, and the second neuron value storage circuit <NUM> comprises j registers <NUM>~45j. The j registers <NUM>~45j store the neuron values Do_1~DoJ of the next layer. The j neuron values Do_1~Do_j are digital values.

The word lines WL1~WLn of the cell array <NUM> are operated according to the n neuron values Din_1~Din_n. That is, it is not necessary to convert the n neuron values Din_1~Din_n through the digital-to-analog converter (DAC). Especially, the word lines WL1~WLn of the cell array <NUM> are selectively activated or inactivated according to the binary codes of the neuron values Din_1~Din_n. In other words, two or more than two word lines of the word lines WL1~WLn of the cell array <NUM> may be activated simultaneously.

Since the neuron values Din_1~Din_n are digital values, the multiply accumulate circuits <NUM>~42j perform multiple operations according to the bit numbers of the neuron values Din_1~Din_n. For example, if the neuron values Din_1~Din_n are <NUM>-bit digital values, the multiply accumulate circuits <NUM>~42j perform eight operations and generate bitline currents to the corresponding bit lines BL1~BLj for eight times.

Moreover, the processors <NUM>~43j of the processing circuit <NUM> receive the bitline currents from the corresponding bit lines BL1~BLj for many times. After the processors <NUM>~43j perform an analog computation on the bitline currents, the neuron values Do_1~DoJ are generated and transmitted to the j registers <NUM>~45j of the second neuron value storage circuit <NUM>, respectively.

For brevity, the operations of the multiply accumulate circuit <NUM> and the corresponding processor <NUM> will be described as follows.

<FIG> is a schematic circuit diagram illustrating the operations of a processor of the control circuit according to the embodiment of the present invention. As shown in <FIG>, the processor <NUM> comprises a voltage clamping circuit <NUM>, a current-to-voltage converter <NUM>, an analog computing circuit <NUM> and an analog-to-digital converter (ADC) <NUM>. The analog-to-digital converter <NUM> is used for converting analog currents into digital values.

In the processor <NUM>, the current-to-voltage converter <NUM> is connected with the voltage clamping circuit <NUM> for receiving the bitline current ISL1 and converting the bitline current ISL1 into a converted voltage Va. That is, the input terminal of the current-to-voltage converter <NUM> receives the bitline current ISL1 from the multiply accumulate circuit <NUM>, and the output terminal of the current-to-voltage converter <NUM> generates the converted voltage Va to the analog computing circuit <NUM>.

The voltage clamping circuit <NUM> comprises a control transistor Me and an operation amplifier <NUM>. A first drain/source terminal of the control transistor Mc is connected with the bit line BL1. The second drain/source terminal of the control transistor Mc is connected with an input terminal of the current-to-voltage converter <NUM>. A positive input terminal of the operation amplifier <NUM> receives a bias voltage Vb. A negative input terminal of the operation amplifier <NUM> is connected with the first drain/source terminal of the control transistor Mc. An output terminal of the operation amplifier <NUM> is connected with a gate terminal of the control transistor Mc. Consequently, during the operation of the multiply accumulate circuit <NUM>, the voltage of the bit line BL1 is fixed at the bias voltage Vb.

In some embodiments, the processor <NUM> is not equipped with the voltage clamping circuit <NUM>. Under this circumstance, the input terminal of the current-to-voltage converter <NUM> is connected with the bit line BL1. The current-to-voltage converter <NUM> receives the bitline current IBL1 from the multiply accumulate circuit <NUM>, and the output terminal of the current-to-voltage converter <NUM> generates the converted voltage Va to the analog computing circuit <NUM>.

The analog computing circuit <NUM> is connected between the current-to-voltage converter <NUM> and the analog-to-digital converter <NUM>. In this embodiment, the analog computing circuit <NUM> comprises L amplifying circuits <NUM><NUM>~<NUM>L-<NUM>. These amplifying circuits have the identical circuitry structures. For example, the amplifying circuit <NUM><NUM> comprises a switch sw<NUM>, a capacitor C<NUM> and an amplifying transistor M<NUM>. A first terminal of the switch sw<NUM> is connected with the output terminal of the current-to-voltage converter <NUM>. A second terminal of the switch sw<NUM> is connected with a first terminal of the capacitor C<NUM> and the gate terminal of the amplifying transistor M<NUM>. A second terminal of the capacitor C<NUM> is connected with a ground terminal Gnd. A first drain/source terminal of the amplifying transistor M<NUM> is connected with a node d. A second drain/source terminal of the amplifying transistor M<NUM> is connected with the ground terminal Gnd. The node d is also connected with the analog-to-digital converter <NUM>. The analog computing circuit <NUM> receives a switching signal S. The switches sw<NUM>~swL-<NUM> of the L amplifying circuits <NUM><NUM>~<NUM>L-<NUM> are operated according to the switching signal S.

The aspect ratios of the amplifying transistors M<NUM>~ML-<NUM> of the amplifying circuits <NUM><NUM>~<NUM>L-<NUM> are in a fixed power relationship. For example, the aspect ratio of the amplifying transistor M<NUM> is <NUM><NUM>×(W/L). The aspect ratio of the amplifying transistor M<NUM> is <NUM><NUM>×(W/L). The rest may be deduced by analogy. The aspect ratio of the amplifying transistor ML-<NUM> is <NUM>L-<NUM>×(W/L).

In a training phase of the neural network system, the internal resistance values of the n floating gate transistors F<NUM>,<NUM>~Fn,<NUM> of the multiply accumulate circuit <NUM> are tuned. For example, the internal resistance values of the floating gate transistors F<NUM>,<NUM>~Fn,<NUM> are tuned to r<NUM>,<NUM>~rn,<NUM>, respectively. When the word line WL1 is activated, the switch transistor The M<NUM>,<NUM> of the memristive cell c11 is turned on. Consequently, the cell current I<NUM>,<NUM> generated by the memristive cell c11 is equal to [(Vs-Vb)/r<NUM>,<NUM>]. Similarly, the other memristive cells c21~cn1 of the multiply accumulate circuit <NUM> generate the cell currents I<NUM>,<NUM>~In,<NUM>, respectively.

In case that the word line WL1 is inactivated, the memristive cell c11 does not generate the cell current I<NUM>,<NUM>. That is, I<NUM>,<NUM>=<NUM>. Similarly, in case that the word lines WL2~WLn are inactivated, the corresponding memristive cells c21~cn1 do not generate the cell currents I<NUM>,<NUM>~In,<NUM>.

In an application phase of the neural network system, the multiply accumulate circuit <NUM> performs multiple operations according to the bit numbers of the neuron values Din_1~Din_n. Whenever one operation is performed, a bitline current ISL1 is generated to the processor <NUM>. According to the bitline current IBL1 generated at each time, the processor <NUM> generates the neuron values Do_1.

For example, the neuron values Din_1~Din_n are <NUM>-bit values. The first neuron value storage circuit <NUM> successively provides one bit of the neuron values Din_1~Din_n to control the corresponding word lines WL1~WLn. Consequently, the memristive cells c11-c1j of the multiply accumulate circuit <NUM> generate the cell currents I<NUM>,<NUM>~In,<NUM>. The bitline current ISL1 that is equal to the total of the cell currents I<NUM>,<NUM>~In,<NUM> is outputted to the processor <NUM> through the bit line BL1. Since the neuron values Din_1~Din_n are <NUM>-bit values, the first neuron value storage circuit <NUM> generates a total of eight bitline currents IBL1 to the processor <NUM>. The eight bitline currents IBL1 are sequentially converted into eight converted voltages Va by the current-to-voltage converter <NUM>. The converted voltages Va are inputted into the analog computing circuit <NUM>. Then, the analog computing circuit <NUM> generates an output current Iout. According to the output current Iout, the analog-to-digital converter <NUM> generates the neuron values Do_1 of the next layer.

Similarly, in case that the neuron values Din_1~Din_n are L-bit values, the first neuron value storage circuit <NUM> generates a total of L bitline currents IBL1 to the processor <NUM> sequentially. The L bitline currents ISL1 are sequentially converted into L converted voltages Va by the current-to-voltage converter <NUM>. The converted voltages Va are inputted into the analog computing circuit <NUM>. Then, the analog computing circuit <NUM> generates an output current Iout to the analog-to-digital converter <NUM>. Consequently, the analog-to-digital converter <NUM> generates the neuron values Do_1 of the next layer.

A method of performing the calculations by the multiply accumulate circuit <NUM> will be described in more details as follows. Firstly, the first neuron value storage circuit <NUM> successively provides one bit of the neuron values Din_1~Din_n in the registers <NUM>~41n to control the corresponding word lines WL1~WLn.

Take the register <NUM> for example. An L-bit neuron value Din_1 is stored in the register <NUM>. The binary codes of the L-bit neuron value Din_1 contain the bits a<NUM>,L-<NUM>,. , a<NUM>,<NUM>, a<NUM>,<NUM> from the most significant bit (MSB) to the least significant bit (LSB) sequentially. If the binary code is "<NUM>", the word line WL1 is activated and the switch transistor M<NUM>,<NUM> is turned on. Consequently, the memristive cell c11 generates the cell current I<NUM>,<NUM>. Whereas, if the binary code is "<NUM>", the word line WL1 is inactivated and the switch transistor M<NUM>,<NUM> is turned off. Consequently, the memristive cell c11 does not generate the cell current I<NUM>,<NUM>. It is noted that control method is not restricted. For example, in another embodiment, the word line WL1 is activated if the binary code is "<NUM>", and the word line WL1 is inactivated if the binary code is "<NUM>".

Moreover, the on/off states of the switches sw<NUM>~swL-<NUM> of the analog computing circuit <NUM> are controlled according to the switching signal S and according to the sequence of the binary codes from the register <NUM>. For example, in case that the register <NUM> provides the binary codes from the most significant bit (MSB) to the least significant bit (LSB) sequentially, the witches swL-<NUM>~sw<NUM> are sequentially in the close state according to the switching signal S. For example, when the register <NUM> provides the most significant bit (MSB), the switch swL-<NUM> is in the close state and the other switches swL-<NUM>~sw<NUM> are in the open state according to the switching signal S. The rest may be deduced by analogy. When the register <NUM> provides the least significant bit (LSB), the switch sw<NUM> is in the close state and the other switches swL-<NUM>~sw<NUM> are in the open state according to the switching signal S. Whereas, in case that the register <NUM> provides the binary codes from the least significant bit (LSB) to the most significant bit (MSB) sequentially, the witches sw<NUM>~swL-<NUM> are sequentially in the close state according to the switching signal S.

During a first operation of the multiply accumulate circuit <NUM>, the first neuron value storage circuit <NUM> provides the most significant bits (MSB) in the registers <NUM>~41n to control the corresponding word lines WL1~WLn. That is, the first neuron value storage circuit <NUM> controls the word line WL1 according to the bit "a<NUM>,L-<NUM>" in the register <NUM>, and the first neuron value storage circuits <NUM> control the word line WL2 according to the bit "a<NUM>,L-<NUM>" in the register <NUM>. The rest may be deduced by analogy. The first neuron value storage circuit <NUM> controls the word line WLn according to the bit "an,L-<NUM>" in the register 41n. Consequently, in the first operation, the bitline current IBL1 generated by the multiply accumulate circuit <NUM> may be expressed by the following formula: <MAT>.

Then, the bitline current IBL1 is converted into a first converted voltage Va by the current-to-voltage converter <NUM>. The converted voltage Va is inputted into the analog computing circuit <NUM>. Since the switch swL-<NUM> is in the close state, the converted voltage Va is stored in the capacitor CL-<NUM> of the amplifying circuit <NUM>L-<NUM>. The magnitude of the converted voltage Va is in direct proportion to the magnitude of the bitline current ISL1.

The rest may be deduced by analogy. During the second last (i.e., the (L-<NUM>)-th) operation of the multiply accumulate circuit <NUM>, the first neuron value storage circuit <NUM> provides the second bits in the registers <NUM>~41n to control the corresponding word lines WL1~WLn. That is, the first neuron value storage circuit <NUM> controls the word line WL1 according to the bit "a<NUM>,<NUM>" in the register <NUM>, and the first neuron value storage circuits <NUM> control the word line WL2 according to the bit "a<NUM>,<NUM>" in the register <NUM>. The rest may be deduced by analogy. The first neuron value storage circuit <NUM> controls the word line WLn according to the bit "an,<NUM>" in the register 41n. Consequently, in the (L-<NUM>)-th operation, the bitline current ISL1 generated by the multiply accumulate circuit <NUM> may be expressed by the following formula: <MAT>.

Then, the bitline current IBL1 is converted into an (L-<NUM>)-th converted voltage Va by the current-to-voltage converter <NUM>. The converted voltage Va is inputted into the analog computing circuit <NUM>. The converted voltage Va is stored in the capacitor C<NUM> of the amplifying circuit <NUM><NUM>. Similarly, the magnitude of the converted voltage Va is in direct proportion to the magnitude of the bitline current IBL1.

During the last (i.e., the L-th) operation of the multiply accumulate circuit <NUM>, the first neuron value storage circuit <NUM> provides the least significant bits (LSB) in the registers <NUM>~41n to control the corresponding word lines WL1~WLn. That is, the first neuron value storage circuit <NUM> controls the word line WL1 according to the bit "a<NUM>,<NUM>" in the register <NUM>, and the first neuron value storage circuits <NUM> control the word line WL2 according to the bit "a<NUM>,<NUM>" in the register <NUM>. The rest may be deduced by analogy. The first neuron value storage circuit <NUM> controls the word line WLn according to the bit "an,<NUM>" in the register 41n. Consequently, in the L-th operation, the bitline current IBL1 generated by the multiply accumulate circuit <NUM> may be expressed by the following formula: <MAT>.

Then, the bitline current ISL1 is converted into an L-th converted voltage Va by the current-to-voltage converter <NUM>. The converted voltage Va is inputted into the analog computing circuit <NUM>. The converted voltage Va is stored in the capacitor C<NUM> of the amplifying circuit <NUM><NUM>. Similarly, the magnitude of the converted voltage Va is in direct proportion to the magnitude of the bitline current IBL1.

After the L-th operation of the multiply accumulate circuit <NUM>, the converted voltages Va have been stored in the capacitors C<NUM>~CL-<NUM> of the amplifying circuits <NUM><NUM>~<NUM>L-<NUM>. Then, the analog-to-digital converter <NUM> is enabled in response to an enabling signal EN. The analog computing circuit <NUM> generates the output current Iout to the analog-to-digital converter <NUM>. According to the output current Iout, the analog-to-digital converter <NUM> generates the neuron values Do_1 of the next layer.

As mentioned above, the aspect ratios of the amplifying transistors M<NUM>~ML-<NUM> of the amplifying circuits <NUM><NUM>~<NUM>L-<NUM> are in a fixed power relationship. The relation between the amplified current I<NUM> generated by the amplifying circuit <NUM><NUM> and the converted voltage Va may be expressed as: I<NUM>=<NUM><NUM>×p<NUM>×Va<NUM>, wherein the amplifying circuits <NUM><NUM>~<NUM>L-<NUM> operate in the saturation region, and p<NUM> is a constant. The relation between the amplified current I<NUM> generated by the amplifying circuit <NUM><NUM> and the converted voltage Va may be expressed as: I<NUM>=<NUM><NUM>×p<NUM>×Va<NUM>. The rest may be deduced by analogy. The relation between the amplified current IL-<NUM> generated by the amplifying circuit <NUM>L-<NUM> and the converted voltage Va may be expressed as: IL-<NUM>=<NUM>L-<NUM>×p<NUM>×Va<NUM>. For example, p<NUM> is device parameter of the transistor M<NUM>.

Consequently, the output current Iout may be calculated by the following formulae: <MAT>.

Since c is a constant, (c×Ii,<NUM>) may be considered as a neuron connection weight, where i is an integer, and <NUM> ≤ i ≤ n. In other words, after the n cell currents I<NUM>,<NUM>~In,<NUM> are adjusted, the corresponding n neuron connection weights are adjusted. According to the output current Iout, the analog-to-digital converter <NUM> generates the digital neuron values Do_1.

<FIG> is a schematic circuit diagram illustrating an example of the current-to-voltage converter of the processor as shown in <FIG>. The current-to-voltage converter <NUM> comprises a diode-connected transistor Md. A first drain/source terminal of the transistor Md receives the bitline current IBL1. A second drain/source terminal of the transistor Md is connected with the ground terminal Gnd. The gate terminal of the transistor Md and the first drain/source terminal of the transistor Md are connected with each other. Consequently, the converted voltage Va<NUM> =rmd×IBL1, wherein rmd is the internal resistance value of the diode-connected transistor Md. It is noted that the circuitry structure of the current-to-voltage converter is not restricted to that of the current-to-voltage converter <NUM> as shown in <FIG>. That is, any other appropriate current-to-voltage converter can be used in the processor.

<FIG> is a schematic circuit diagram illustrating an example of the analog-to-digital converter of the processor as shown in <FIG>. The analog-to-digital converter <NUM> is used for converting the analog current into the digital value. As shown in <FIG>, the analog-to-digital converter <NUM> comprises a transistor Me, a resistor R and a voltage-type analog-to-digital conversion circuit ADC_v <NUM>.

A first drain/source terminal of the transistor Me receives the supply voltage Vs. A second drain/source terminal of the transistor Me is connected with a node c. The gate terminal of the transistor Me receives the enabling signal EN. A first terminal of the resistor R is connected with the node c. A second terminal of the resistor R is connected with the node d to receive the output current Iout. The input terminal of the voltage-type analog-to-digital conversion circuit ADC_v <NUM> is connected with the node c. The output terminal of the voltage-type analog-to-digital conversion circuit ADC_v <NUM> generates the digital neuron values Do_1.

When the enabling signal EN is activated (e.g., in the low level state), the transistor Me is turned on and the voltage Vc at the node c is equal to R×Iout. Consequently, the voltage Vc at the node c is converted into the digital neuron values Do_1 by the voltage-type analog-to-digital conversion circuit ADC_v <NUM>. It is noted that the circuitry structure of the analog-to-digital converter is not restricted to that of the analog-to-digital converter <NUM> as shown in <FIG>. That is, any other appropriate analog-to-digital converter can be used in the processor.

<FIG> is a schematic circuit diagram illustrating another example of the analog-to-digital converter of the processor as shown in <FIG>. As shown in <FIG>, the analog-to-digital converter <NUM> comprises a current mirror <NUM>, a resistor R and a voltage-type analog-to-digital conversion circuit ADC_v <NUM>.

The current receiving terminal of the current mirror <NUM> is connected with the node d to receive the output current Iout. The control terminal of the current mirror <NUM> receives the enabling signal EN. The current mirroring terminal of the current mirror <NUM> is connected with the node c. The current mirroring terminal of the current mirror <NUM> is capable of generating the output current Iout in response to the enabling signal EN. A first terminal of the resistor R is connected with the node c. A second terminal of the resistor R receives a supply voltage Gnd. The input terminal of the voltage-type analog-to-digital conversion circuit ADC_v <NUM> is connected with the node c. The output terminal of the voltage-type analog-to-digital conversion circuit ADC_v <NUM> generates the digital neuron values Do_1.

Furthermore, the current mirror <NUM> includes transistors Me1~Me4. A first drain/source terminal of the transistor Me1 receives the supply voltage Vs. A second drain/source terminal of the transistor Me1 is connected with a first drain/source terminal of the transistor Me2. A gate terminal of the transistor Me1 is connected with the node d. A second drain/source terminal of the transistor Me2 is connected with a node d. A gate terminal of the transistor Me2 receives the enabling signal EN. A first drain/source terminal of the transistor Me3 receives the supply voltage Vs. A second drain/source terminal of the transistor Me3 is connected with a first drain/source terminal of the transistor Me4. A gate terminal of the transistor Me3 is connected with the node d. A second drain/source terminal of the transistor Me4 is connected with a node c. A gate terminal of the transistor Me4 receives the enabling signal EN.

When the enabling signal EN is activated (e.g., in the low level state), the current mirror <NUM> is enabled and the voltage Vc at the node c is equal to R×Iout. Consequently, the voltage Vc at the node c is converted into the digital neuron values Do_1 by the voltage-type analog-to-digital conversion circuit ADC_v <NUM>.

<FIG> is a schematic circuit diagram illustrating the operations of a processor of the control circuit according to another embodiment of the present invention. In comparison with the processor <NUM> of <FIG>, the types of the transistors in the processor <NUM>' of this embodiment are distinguished. For example, the p-type transistors are replaced by n-type transistors, and the n-type transistors are replaced by p-type transistors.

As shown in <FIG>, the processor <NUM>' comprises a voltage clamping circuit <NUM>, a current-to-voltage converter <NUM>, an analog computing circuit <NUM> and an analog-to-digital converter (ADC) <NUM>. The voltage clamping circuit <NUM> comprises an operation amplifier <NUM>. The analog computing circuit <NUM> comprises L amplifying circuits <NUM><NUM>~<NUM>L-<NUM>. The analog-to-digital converter <NUM> is used for converting analog currents into digital values.

The connecting relationships of the components of the processor <NUM>' and the operating principles of the processor <NUM>' are similar to those of the processor <NUM> as shown in <FIG>, and are not redundantly described herein.

From the above descriptions, the present invention provides a multiply accumulate circuit for a neural network system and an associated control circuit. In the control circuit, the binary codes of the neuron values Din_1~Din_n of the previous layer are sequentially provided to control the multiply accumulate circuits <NUM>~42j of the cell array <NUM>. Moreover, the processing circuit <NUM> receives the bitline currents from the multiply accumulate circuits <NUM>~42j. After an analog computation is performed on the bitline currents, the neuron values Do_1~Do_j of the next layer are generated.

Claim 1:
A control circuit (<NUM>) for a neural network system (<NUM>), the control circuit comprising:
a first multiply accumulate circuit (<NUM>) comprising n memristive cells (c11~cn1), wherein first terminals of the n memristive cells (c11~cn1) receive a supply voltage (Vs), second terminals of the n memristive cells (c11~cn1) are connected with a first bit line (BL1), and control terminals of the n memristive cells (c11~cn1) are respectively connected with n word lines (WL1~WLn);
a first neuron value storage circuit (<NUM>) connected with the n word lines (WL1~WLn), and comprising n registers (<NUM>~41n), wherein n neuron values (Din_1~Din_n) of a first layer are stored in the corresponding registers (<NUM>~41n); and
a first processor (<NUM>) connected with the first bit line (BL1);
wherein in an application phase of the neural network system (<NUM>), the first neuron value storage circuit (<NUM>) controls the n word lines (WL1~WLn) according to binary codes of the n neuron values (Din_1~Din_n), so that the first multiply accumulate circuit (<NUM>) generates plural first bitline currents (IBL1) to the first processor (<NUM>) through the first bit line (BL1), wherein after the first processor (<NUM>) performs an analog computation on the plural first bitline currents (IBL1) to covert the plural first bitline currents (IBL1) into an output current (Iout), the output current (Iout) is converted into a first neuron value (Do_1) of a second layer;
wherein the n word lines (WL1~WLn) are activated or inactivated in response to the binary codes of the neuron values (Din_1~Din_n), a first portion of the n memristive cells (c11~cn1) corresponding to the activated word lines generates cell currents, and a second portion of the n memristive cells (c11~cn1) corresponding to the inactivated word lines does not generate the cell current,
wherein the binary codes of the n neuron values (Din_1~Din_n) of the first layer are L-bit values, and the first neuron value storage circuit (<NUM>) sequentially provides one bit of the n neuron values (Din_1~Din_n) for L times to control the n word lines (WL1~WLn) of the first multiply accumulate circuit (<NUM>), so that the first multiply accumulate circuit (<NUM>) generates the first bitline currents (IBL1) for L times.