Patent Description:
NPUs are used to accelerate computation of deep-learning algorithms, such as a convolution neural network (CNN). NPUs may include dot-product compute units in which the output of an array of multiplications is input to an adder tree and then to accumulators to perform a dot-product operation. Different quantization techniques may be used to quantize weights and/or activations of deep learning algorithms. The quantization techniques may lead to different quantization precisions, such as an <NUM>-bit precision or a <NUM>-bit precision. Mixed-precision NPUs support accelerating different deep-learning algorithms having different precisions (e.g., number of bit per weight). Mixed-precision NPUs are typically built using a low-precision multiplication unit. Temporal or spatial fusion may be used in mixed-precision NPUs to support higher-precision computation. In spatial fusion, multiplication units (i.e., processing elements (PEs)) are divided into multiple sets or tiles. High-precision data may be divided into low-precision components (e.g., nibbles) and distributed to each set of multiplier according to the component location (e.g., most significant nibble (MSN), least significant nibbles (LSN)). Each set performs a partial computation of the high precision result using the low-precision multipliers. Results for each set may be combined (fused) together to generate a higher-precision calculation.

<CIT> discloses: An accelerating apparatus for a neural network includes an input processor configured to decide a computation mode according to precision of an input signal, and change or maintain the precision of the input signal according to the decided computation mode; and a computation circuit configured to receive the input signal from the input processor, perform select one or more operations among multiple operations including a multiplication based on the input signal, boundary migration to rearrange multiple signals divided from the input signal, and an addition of the input signal subjected to the boundary migration, according to the computation mode, and perform the selected one or more operations on the input signal.

An aspect provides a neural network accelerator that includes a multiplication unit, and adder tree unit and an accumulator unit. The multiplication unit and an adder tree unit are configured to perform lattice-multiplication operations. The accumulator unit is coupled to an output of the adder tree and form dot-product values from the lattice-multiplication operations performed by the multiplication unit and the adder tree unit. The multiplication unit includes n multiplier units that perform lattice-multiplication-based operations and output product values. Each multiplier unit is an N x N multiplier unit, and each multiplier unit includes four N/<NUM> x N/<NUM> multipliers. n and N comprise <NUM>, and each multiplier unit receives a first multiplicand and a second multiplicand in which the first multiplicand includes a most significant nibble and a least significant nibble and the second multiplicand includes a most significant nibble and a least significant nibble. Each multiplier unit includes a first multiplier that receives the least significant nibble of the first multiplicand and the least significant nibble of the second multiplicand, a second multiplier that receives the least significant nibble of the first multiplicand and the most significant nibble of the second multiplicand, a third multiplier that receives a most significant nibble of the first multiplicand and the least significant nibble of the second multiplicand, and a fourth multiplier that receives the most significant nibble of the first multiplicand and the most significant nibble of the second multiplicand.

In one embodiment, the most significant nibble of the first multiplicand equals <NUM>, and the most significant nibble of the second multiplicand may be greater than <NUM>.

In another embodiment, the most significant nibble of the first multiplicand may be greater than <NUM>, and the most significant nibble of the second multiplicand equals <NUM>.

In still another embodiment, the first multiplier of each multiplier unit may output a least significant nibble L0 and a most significant nibble M0 of a first product value, the second multiplier of each multiplier unit may output a least significant nibble L1 and a most significant nibble M1 of a second product value, the third multiplier of each multiplier unit may output a least significant nibble L2 and a most significant nibble M2 of a third product value, and the fourth multiplier of each multiplier unit may output a least significant nibble L3 and a most significant nibble M3 of a fourth product value.

In yet another embodiment, the adder tree may form a first sum S0 by adding all least significant nibbles of the first product values output by the n multiplier units, a second sum S1 by adding all least significant nibbles of the second product values, all least significant nibbles of the third product values and all most significant nibbles of the first product value output by the n multiplier units, a third sum S2 by adding all least significant nibbles of the fourth product values, all most significant nibbles of the second product values and all most significant nibbles of the third product values output by the n multiplier units, and a fourth sum S3 by adding all least most significant nibbles output by the n multiplier units.

In one embodiment, the second sum S1 may further include a carry value from the first sum S0, the third sum S2 may further include a carry value from the second sum S1, and the fourth sum S3 may further include a carry value from the third sum S2.

In the following section, the aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments illustrated in the figures, in which:.

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. It will be understood, however, by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail to not obscure the subject matter disclosed herein.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment disclosed herein. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "according to one embodiment" (or other phrases having similar import) in various places throughout this specification may not necessarily all be referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "serving as an example, instance, or illustration. " Any embodiment described herein as "exemplary" is not to be construed as necessarily preferred or advantageous over other embodiments. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. Similarly, a hyphenated term (e.g., "two-dimensional," "pre-determined," "pixel-specific," etc.) may be occasionally interchangeably used with a corresponding non-hyphenated version (e.g., "two dimensional," "predetermined," "pixel specific," etc.), and a capitalized entry (e.g., "Counter Clock," "Row Select," "PIXOUT," etc.) may be interchangeably used with a corresponding non-capitalized version (e.g., "counter clock," "row select," "pixout," etc.). Such occasional interchangeable uses shall not be considered inconsistent with each other.

Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. It is further noted that various figures (including component diagrams) shown and discussed herein are for illustrative purpose only, and are not drawn to scale. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.

The terminology used herein is for the purpose of describing some example embodiments only and is not intended to be limiting of the claimed subject matter.

It will be understood that when an element or layer is referred to as being on, "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present.

The terms "first," "second," etc., as used herein, are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functionality. Such usage is, however, for simplicity of illustration and ease of discussion only; it does not imply that the construction or architectural details of such components or units are the same across all embodiments or such commonly-referenced parts/modules are the only way to implement some of the example embodiments disclosed herein.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs.

As used herein, the term "module" refers to any combination of software, firmware and/or hardware configured to provide the functionality described herein in connection with a module. For example, software may be embodied as a software package, code and/or instruction set or instructions, and the term "hardware," as used in any implementation described herein, may include, for example, singly or in any combination, an assembly, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The modules may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, but not limited to, an integrated circuit (IC), system-on-a-chip (SoC), an assembly, and so forth.

The subject matter disclosed herein provides a fusion mechanism for a dot-product unit. An output of a multiplier is divided into nibbles (<NUM>-bits) to perform a nibble-wise summation. The summation results are fused (combined) to obtain a final precision output. An optimized mixed-precision architecture is also disclosed herein that accelerates computation of deep-learning applications based on a dot-product compute unit. A mixed-precision feature may be obtained by nibble-wise summation of the low-precision multiplier output, then the summation results may be fused after the adder tree. A latency (i.e., speed) of the mixed-precision dot-product unit may be improved by first performing output nibble-wise summation, then fusing the summation results to obtain the final output.

The subject matter disclosed herein does not depend on (shift-add) comparing used with traditional multiplication, but utilizes a lattice-multiplication technique to minimize a critical path of a neural network accelerator and optimize circuit speed of the neural network accelerator. Additionally, mixed-precision dot-products are supported for different tile dimensions, e.g., INT8XINT4, INT8XINT8.

<FIG> depicts a block diagram of an example embodiment of a mixed-precision neural network accelerator tile <NUM> having lattice fusion according to the subject matter disclosed herein. The neural network accelerator <NUM> may be used to calculate dot-products. The neural network accelerator <NUM> includes an n multiplication unit <NUM>, an adder trees unit <NUM>, a swap unit <NUM>, accumulation units 104a and 104b, and a fusion unit <NUM> arranged and connected as shown in <FIG>. The different functional blocks depicted in <FIG> may be embodied as modules and/or circuits that may be any combination of software, firmware and/or hardware configured to provide the functionality described herein in connection a particular functional block.

The n multiplication unit <NUM> includes n <NUM>-bit x <NUM>-bit multiplier units that are configured to generate product values based on lattice multiplication. The adder trees unit <NUM> may be configured to reduce the product values generated by the n multiplication unit <NUM>. Together the multiplication unit <NUM> and the adder trees unit <NUM> operate based on a lattice multiplication technique. The swap unit <NUM> may be used to swap adder tree outputs based on the input precision of the multiplicands input to the multiplication unit <NUM>. The accumulation units 104a and 104b may be configured to accumulate reduced product values that has been output from the adder trees unit <NUM>. The fusion unit circuit <NUM> may be configured to fuse, or combine, lower precision values to form higher-precision values.

<FIG> depicts an example <NUM>-bit x <NUM>-bit multiplier unit <NUM> that may be used in the n multiplication unit <NUM> to perform a lattice-based multiplication operation. The multiplier unit <NUM> includes four <NUM>-bit x <NUM>-bit multipliers <NUM>. Operation of the multiplier unit <NUM> may be illustrated by considering two unsigned <NUM>-bit input values A and W that may be input to the multiplier unit <NUM>. The <NUM> bits of A and W each form two hex digits {Ma,La} and {Mw,Lw} in which each hex digit is a nibble. Ma is the Most Significant Nibble (MSN) of A, and La is the Least Significant Nibble (LSN) of A. Similarly, Mw is the MSN of W, and Lw is the LSN of W.

<FIG> depicts a lattice multiplication operation <NUM> for the <NUM>-bit values A and W. Product values output by the multipliers <NUM> located in diagonals having the same shade of gray are summed to complete the lattice multiplication operation. The multiplicands and products are labelled in both <FIG>. The sum and carry for the lattice multiplication <NUM> of A and Ware: <MAT> <MAT> <MAT> <MAT>.

The final result R of the lattice multiplication <NUM> of A and W is <MAT>.

The multiplication unit <NUM> may be used for generating a mixed-precision dot-product using a lattice multiplication approach. For example, consider two vectors A and W that each have four vector elements in which each element has <NUM> bits. Vector A, vector W and the dot-product of vectors A and B may be defined as follows. <MAT> <MAT> <MAT> in which i is an index for elements of the vectors A and W.

<FIG> depicts a lattice multiplication <NUM> to generate product values and a dot-product value for two four-element vectors A and W in which each element has <NUM>-bits. Product values along corresponding diagonals are summed. To generate a dot-product value, product values having the reference indicator L0 are summed; product values having the reference indicators L1, L2 and M0 are summed; product values having the reference indicators L3, M1 and M2 are summed; and product values having the reference indicator M3 are summed.

<FIG> depicts an example <NUM>-bit x <NUM>-bit multiplier unit <NUM> that may be used to generate the product values depicted in the lattice multiplication <NUM> for the vectors A and W. The multiplier unit <NUM> includes four <NUM>-bit x <NUM>-bit multipliers <NUM>. A multiplier unit <NUM> may be used for each pair of correspondingly indexed elements of the vectors A and W. The multiplicands and products are labelled for both <FIG>.

To obtain the dot-product sum of vectors A and W, product values along corresponding diagonals are summed as follows: <MAT> <MAT> <MAT> <MAT> in which C<NUM> is a carry bit for sum S<NUM>, C<NUM> is a carry bit for sum S<NUM>, C<NUM> is a carry bit for sum S<NUM>, and C<NUM> is a carry bit for sum S<NUM>.

The final dot-product sum is S = {C<NUM>, S<NUM>, S<NUM>, S<NUM>, S<NUM>}.

Table <NUM> sets forth bit positions in the final sum <NUM> for the different diamond-based summations in <FIG>. In Table <NUM>, d = log<NUM>(n) in which n is the number of elements in the dot product. For the example of <FIG>, n = <NUM>.

<FIG> shows an example embodiment of the adder trees unit <NUM> according to the subject matter disclosed herein. The multiplication unit <NUM> and the adder trees unit <NUM> may be configured as described herein to provide a lattice multiplication operation. The adder trees unit <NUM> may include adder trees <NUM><NUM>-<NUM><NUM> that reduce the product values generated by the multipliers <NUM> to produce final sums of the lattice multiplications for a dot-product computation. Superscripts <NUM> through n - <NUM> on the inputs of the adder trees represent corresponding outputs from the n multiplier units <NUM>.

The multiplier units <NUM> may be used to provide a mixed-precision dot-product computation. Consider an example situation in which the input precision of each element a four element vector A is <NUM> bits, and the input precision of each element of a four element vector W is <NUM> bits. In such a situation, Mw is actually a LSN. The final sum output for even indices i is: <MAT> <MAT> <MAT>.

The final dot-product output for odd indices i is: <MAT> <MAT> <MAT>.

<FIG> depicts a lattice multiplication <NUM> to generate a dot-product for two four-element vectors A and W in which vector A has <NUM>-bit elements and vector W has <NUM>-bit elements. The equations defining the dot-product sum for even-indexed elements and odd-indexed elements are shown below <FIG>. For comparison to the lattice multiplication <NUM>, <FIG> depicts the lattice multiplication <NUM> (<FIG>) to generate a dot-product for two four-element vectors A and W in which each vector has <NUM>-bit elements. The changes in the summations of the lattice multiplication change as the precision of the two input vectors change between <NUM>-bits x <NUM>-bits (<FIG>) and <FIG>-bits x <NUM>-bits (<FIG>).

<FIG> shows how the dot-product summations change for a (8x4) input precision <NUM> and for a (4x8) input precision <NUM>'. The summations change by L1 and L2 being swapped, and by M1 and M2 being swapped. The input swap unit <NUM> (<FIG>) swaps L1 and L2 and swaps M1 and M2 depending upon the input precision.

<FIG> depicts how the even indices and the odd indices summations for an input precision of 8x4 may be combined to form an 8x8 input precision. When the input precision is 4x8, the even and odd indices summations are nearly the same, except that L1 and L2, and M1 and M2 may be swapped depending upon the input precision. Toward the top of <FIG>, a lattice multiplication <NUM> for (8x4) input precision and a lattice multiplication <NUM> for an (8x8) are depicted. Toward the bottom of <FIG>, the summation equations for both (8x4) and (8x8) precisions are indicated. To turn a (4x8) and a (8x4) summation into an (8x8) summation, two adders <NUM> and <NUM> may be used. Adder <NUM> adds the (C1,S1)<NUM> and (C0,S0)<NUM> summations to form a (C1,S1) summation. Adder <NUM> adds the (C3, S3)<NUM> and the (C1,S1)<NUM> summations to form the (C2,S2) summation. The functionality depicted in <FIG> along with some additional control logic (not shown) may be part of an accumulation unit 104a (and/or 104b) (<FIG>) to provide mixed-precision capability.

<FIG> depicts a block diagram for an example embodiment of an accumulation unit <NUM> (even) 104b for d ≤ <NUM> according to the subject matter disclosed herein. The accumulation unit <NUM> (odd) 104a is identical to the accumulation unit <NUM> (even) 104b except that the outputs that are shown as being received from the adder trees L0, L2, M0 and M2 are instead respectively received from the adder trees L1, L3, M1 and M3.

The accumulation unit <NUM> (even) 104b may include <NUM>-bit adders <NUM>-<NUM>, and <NUM>-bit register files <NUM> and <NUM>. Register file <NUM> is a <NUM>+d+c bit register file. The register files <NUM>-<NUM> form the output of the accumulation unit <NUM> (even) 104b. The adder <NUM> receives a <NUM>-bit output from the L0 adder tree and a <NUM>-bit output from the register file <NUM>. The adder <NUM> outputs a <NUM>-bit sum to the register file <NUM> and outputs one temporal carry bit to the adder <NUM>.

The adder <NUM> receives d spatial carry bits output from the L0 adder tree in which d = log<NUM>(n) and n is the number of elements in the dot product. The adder <NUM> also receives <NUM>-bit output from the M0 adder tree, and outputs a <NUM>-bit sum to the adder <NUM> and a carry bit to the adder <NUM>.

The adder <NUM> receives a <NUM>-bit output from the L2 adder tree and the <NUM>-bit output from the adder <NUM>, and outputs a <NUM>-bit sum to the adder <NUM>. The adder <NUM> receives a <NUM>-bit input from the register file <NUM>, and outputs a <NUM>-bit sum to the register file <NUM> and one carry bit to the adder <NUM>.

The adder <NUM> receives the <NUM>-bit output from the L2 adder tree and d bits from the adder tree M0. The adder <NUM> outputs d + <NUM> bits to adder <NUM>. The adder <NUM> receives <NUM> + d bits output from the adder tree M2, and outputs a <NUM>-bit sum to the adder <NUM>. The adder <NUM> receives a <NUM> + d + c -bit output from the register file <NUM> in which c is the maximum supported temporal iteration, e.g., c = log<NUM>(<NUM>×<NUM>×<NUM>). The adder <NUM> outputs a (<NUM> + d + c)-bit sum to the register file <NUM>.

<FIG> depicts a block diagram for an example embodiment of a fusion unit <NUM> according to the subject matter disclosed herein. The fusion unit <NUM> may include an 8x4 Result <NUM> register <NUM>, a 8x4 Result <NUM> register <NUM>, an adder <NUM>, a shifter <NUM>, and an 8x8 Result register <NUM>.

The register <NUM> receives the output from accumulator unit <NUM> (odd) 104a and the register <NUM> receives the output from accumulator unit <NUM> (even) 104b. To form an 8x8 result, the output from accumulator unit <NUM> (odd) 104a is input to the adder <NUM>. The output of accumulator unit <NUM> (even) 104b is shifted left two (<NUM>) bits by shifter <NUM> and then input to the adder <NUM>. The output of adder <NUM> is input to the register <NUM>.

<FIG> depicts an electronic device <NUM> that includes a neural processing unit includes a neural network accelerator according to the subject matter disclosed herein. The electronic device <NUM> may include a controller (or CPU) <NUM>, an input/output device <NUM> such as, but not limited to, a keypad, a keyboard, a display, a touch-screen display, a camera, and/or an image sensor, a memory <NUM>, an interface <NUM>, a GPU <NUM>, an imaging-processing unit <NUM>, and a neural processing unit <NUM> that are coupled to each other through a bus <NUM>. The controller <NUM> may include, for example, at least one microprocessor, at least one digital signal processor, at least one microcontroller, or the like. The memory <NUM> may be configured to store a command code to be used by the controller <NUM> or a user data. Electronic device <NUM> and the various system components of electronic device <NUM> may be formed by one or more modules.

In one embodiment, the neural processing unit <NUM> may be configured to include a neural network accelerator according to the subject matter disclosed herein. The interface <NUM> may be configured to include a wireless interface that is configured to transmit data to or receive data from a wireless communication network using a RF signal. The wireless interface <NUM> may include, for example, an antenna. The electronic device <NUM> also may be used in a communication interface protocol of a communication system, such as, but not limited to, Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), North American Digital Communications (NADC), Extended Time Division Multiple Access (E-TDMA), Wideband CDMA (WCDMA), CDMA2000, Wi-Fi, Municipal Wi-Fi (Muni Wi-Fi), Bluetooth, Digital Enhanced Cordless Telecommunications (DECT), Wireless Universal Serial Bus (Wireless USB), Fast low-latency access with seamless handoff Orthogonal Frequency Division Multiplexing (Flash-OFDM), IEEE <NUM>, General Packet Radio Service (GPRS), iBurst, Wireless Broadband (WiBro), WiMAX, WiMAX-Advanced, Universal Mobile Telecommunication Service - Time Division Duplex (UMTS-TDD), High Speed Packet Access (HSPA), Evolution Data Optimized (EVDO), Long Term Evolution - Advanced (LTE-Advanced), Multichannel Multipoint Distribution Service (MMDS), Fifth-Generation Wireless (<NUM>), Sixth-Generation Wireless (<NUM>), and so forth.

Embodiments of the subject matter and the operations described in this specification may be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer-program instructions, encoded on computer-storage medium for execution by, or to control the operation of data-processing apparatus. Alternatively or additionally, the program instructions can be encoded on an artificially-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. A computer-storage medium can be, or be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial-access memory array or device, or a combination thereof. Moreover, while a computer-storage medium is not a propagated signal, a computer-storage medium may be a source or destination of computer-program instructions encoded in an artificially-generated propagated signal. The computer-storage medium can also be, or be included in, one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). Additionally, the operations described in this specification may be implemented as operations performed by a data-processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

While this specification may contain many specific implementation details, the implementation details should not be construed as limitations on the scope of any claimed subject matter, but rather be construed as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Thus, particular embodiments of the subject matter have been described herein. Other embodiments are within the scope of the following claims. In some cases, the actions set forth in the claims may be performed in a different order and still achieve desirable results. Additionally, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claim 1:
A neural network accelerator (<NUM>), comprising:
a multiplication unit (<NUM>) and an adder tree unit (<NUM>) configured to perform lattice-multiplication operations; and
an accumulator unit (<NUM>, 104b) coupled to an output of the adder tree unit (<NUM>) to form dot-product values from the lattice-multiplication operations performed by the multiplication unit (<NUM>) and the adder tree unit (<NUM>),
wherein the multiplication unit (<NUM>) comprises n multiplier units (<NUM>, <NUM>, <NUM>) that perform lattice-multiplication-based operations and output product values,
wherein each multiplier unit (<NUM>, <NUM>, <NUM>) comprises an N x N multiplier unit (<NUM>, <NUM>, <NUM>), and each multiplier unit (<NUM>, <NUM>, <NUM>) comprises four N/<NUM> x N/<NUM> multipliers,
wherein n and N comprise <NUM>, and each multiplier unit (<NUM>, <NUM>, <NUM>) receives a first multiplicand and a second multiplicand, the first multiplicand comprising a most significant nibble and a least significant nibble and the second multiplicand comprising a most significant nibble and a least significant nibble, and
wherein each multiplier unit (<NUM>, <NUM>, <NUM>) comprises a first multiplier that receives the least significant nibble of the first multiplicand and the least significant nibble of the second multiplicand, a second multiplier that receives the least significant nibble of the first multiplicand and the most significant nibble of the second multiplicand, a third multiplier that receives a most significant nibble of the first multiplicand and the least significant nibble of the second multiplicand, and a fourth multiplier that receives the most significant nibble of the first multiplicand and the most significant nibble of the second multiplicand.