Patent Description:
The demand for increased performance and reduced form factor are driving packaging architectures towards multi-chip integration architectures. Multi-chip integration allows for dies manufactured at different process nodes to be implemented into a single electronic package. However, current multi-chip architectures result in larger form factors that are not suitable for some use cases, or are not otherwise desirable to end users.

<CIT> discloses a package having a passive device disposed over semiconductor die in an inverted pyramid cavity. <CIT> discloses that a plurality of cavities or openings is formed through substrate and a semiconductor die is disposed in cavities. <CIT> discloses a semiconductor package using an embedded interconnect bridge. <CIT> discloses that a memory die and a CPU die are fastened to the substrate and a bridge embedded within a die provides connectors to the CPU die and connectors to the memory die. <CIT> discloses that the circuit structure can have a through hole, which is an opening or hole that traverses between one surface of a structure to an opposite surface of the structure, and an integrated circuit device can be in the through hole. <CIT> discloses an integrated circuit package with a path of high thermal conductivity.

<CIT> discloses Fan-Out Wafer Level Packages (FO-WLPs) and methods for assembling FO-WLPs including double-sided molded package bodies in which first and second layers of components are embedded in a back-to-back relationship.

Described herein are multi-chip packaging architectures with one or more dies attached to a base substrate and one or more components embedded in cavities in the base substrate and methods of forming such electronic packages, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

As noted above, the trends in electronic packaging architectures are driving towards the use of multi-chip architectures. However, form factors are not currently at desired levels. Accordingly, embodiments disclosed herein include multi-chip package architectures with improved form factor. Particularly, embodiments disclosed herein allow for homogenous or heterogeneous integrations over a base substrate. Furthermore, the base substrate may comprise one or more cavities that allow for additional components to be located below (and at least partially within the footprint of) the dies. Accordingly, the form factor is improved by reducing the overall footprint in the X-Y plane, as well as reducing the Z-height. Positioning the additional components within the footprint of the one or more dies also reduces the length of signal paths between dies and the additional components. As such, signal integrity is optimized.

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> is shown, in accordance with an embodiment. In an embodiment, the electronic package <NUM> may comprise a base substrate <NUM>. The base substrate <NUM> may be a silicon substrate in some embodiments. The base substrate <NUM> may comprise signaling traces, pads, and the like (not shown) proximate to surface <NUM> of the base substrate. The surface <NUM> may be referred to herein as a redistribution layer (or layers), a back end of line (BEOL) stack, or the like. In an embodiment, the base substrate <NUM> is a passive substrate. That is, only passive components (e.g., pads, traces, vias, etc.) are fabricated on the base substrate <NUM>. In other embodiments, the base substrate <NUM> is an active substrate. That is, active circuitry (e.g., transistors, etc.) may be fabricated on the base substrate.

In an embodiment, a plurality of through substrate vias (TSVs) <NUM> (also referred to as through silicon vias when the base substrate is a silicon substrate) may pass through a thickness of the base substrate <NUM>. TSVs <NUM> may provide electrical connections between surfaces of the base substrate <NUM>. For example, package side bumps (PSBs) <NUM> may be electrically coupled to features in the surface <NUM> of the base substrate <NUM>.

In an embodiment, a die <NUM> may be attached to the base substrate <NUM>. For example, first level interconnects (FLIs) <NUM> may electrically couple the die <NUM> to the surface <NUM> of the base substrate <NUM>. In an embodiment, the die <NUM> may have an active surface <NUM> (i.e., the surface proximate to where active circuitry is fabricated). The active surface <NUM> may be oriented to face the surface <NUM> of the base substrate <NUM>. In an embodiment, the die <NUM> is embedded in a mold layer <NUM>. In some embodiments, a backside surface of the die <NUM> opposite from the active surface <NUM> may be exposed. In other embodiments, the backside surface of the die <NUM> is covered by the mold layer <NUM>.

In an embodiment, a cavity <NUM> is formed into the base substrate <NUM>. The cavity <NUM> may pass through a thickness of the base substrate <NUM> and end at the surface <NUM> of the base substrate <NUM>. In an embodiment, the cavity <NUM> may be at least partially within a footprint of the die <NUM>. As used herein, "within a footprint" refers to being positioned within an outer perimeter of a given feature. For example, the cavity <NUM> is within the outer perimeter of the die <NUM> in <FIG>.

In an embodiment, a component <NUM> may be positioned in the cavity <NUM>. The component <NUM> may be any of a variety of different component types, such as a die or die stack (e.g., a processor die, a memory die, a power die, a communication die, etc.), a passive component (e.g., a bridge, a capacitor, an inductor, etc.), a cooling module (e.g., a thermoelectric cooling (TEC) module), or the like. In embodiments where the component <NUM> is a die or a die stack, the component <NUM> may be fabricated at a first process node and the die <NUM> may be fabricated at a second process node. In some embodiments, the first process node may be different than the second process node.

In an embodiment, the component <NUM> may have an active surface <NUM>. The active surface <NUM> may be electrically coupled to the backside surface with one or more TSVs <NUM>. In an embodiment, the active surface <NUM> may be oriented in a face-to-face configuration with the die <NUM>. That is, the active surface <NUM> of the component <NUM> may face the active surface <NUM> of the die <NUM>. In an embodiment, the component <NUM> may be coupled to the surface <NUM> of the base substrate <NUM> with FLIs <NUM>.

In an embodiment, the component <NUM> may be embedded in a mold layer <NUM>. The mold layer <NUM> may substantially fill the remaining portion of the cavity <NUM> that is not occupied by the component <NUM>, the FLIs <NUM>, and any underfill material (not shown) surrounding the FLIs <NUM>. In an embodiment, a backside surface of the component <NUM> may be exposed (i.e., not covered by the mold layer <NUM>). In other embodiments, the mold layer <NUM> may cover the backside surface of the component <NUM>.

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> with a first die <NUM> and a second die <NUM> is shown, in accordance with an embodiment. In an embodiment, the electronic package <NUM> in <FIG> may be substantially similar to the electronic package <NUM> in <FIG>, with the exception that a second die is added and the position of the cavity <NUM> is moved.

As shown in <FIG>, a second die <NUM> may be positioned over the surface <NUM> of the base substrate <NUM>. That is, the second die <NUM> may be laterally adjacent to the first die <NUM>. In an embodiment, the second die <NUM> has an active surface <NUM> that faces the surface <NUM> of the base substrate <NUM>. In an embodiment, the first die <NUM> is different than the second die <NUM>. For example, the first die <NUM> may be fabricated at a first process node and the second die <NUM> may be fabricated at a second (different) process node. In other embodiments, the first die <NUM> may be substantially similar to the second die <NUM>. For example, the first die <NUM> and the second die <NUM> may be processor dies that are electrically coupled together by a bridge (or any other interconnect) in order to function as a monolithic die.

In an embodiment, the cavity <NUM> may be positioned at least partially within a footprint of the first die <NUM> and at least partially within a footprint of the second die <NUM>. That is, the cavity <NUM> may span a gap separating the first die <NUM> from the second die <NUM>. Such an embodiment may be particularly beneficial when the component <NUM> is coupled to both the first die <NUM> and the second die <NUM>. For example, the component <NUM> may be a bridge (e.g., an embedded multi-die interconnect bridge (EMIB)) that electrically couples the first die <NUM> to the second die <NUM>. Alternative embodiments may include a component <NUM> that is a memory device (or any other component) that is accessible by both the first die <NUM> and the second die <NUM>.

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> with a first die <NUM> and a second die <NUM> is shown, in accordance with an additional embodiment. The electronic package <NUM> in <FIG> is substantially similar to the electronic package <NUM> in <FIG>, with the exception of the location of the cavity <NUM>. As shown, the cavity <NUM> is entirely within a footprint of the first die <NUM>. Such an embodiment may be particularly beneficial when the component <NUM> is only accessed by a single one of the dies (e.g., the first die <NUM>).

In an embodiment, the electronic package <NUM> in <FIG> may also differ from the electronic package <NUM> in <FIG> in that traces <NUM> are fabricated in the surface <NUM> of the base substrate <NUM> to provide a connection between the first die <NUM> and the second die <NUM>. In embodiments where the base substrate <NUM> is a silicon substrate, traces with fine line spacing (FLS) may be patterned directly onto the base substrate <NUM> and there may not be a need for a dedicated bridge die to couple the first die <NUM> to the second die <NUM>.

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> with a first component <NUM> and a second component <NUM> is shown, in accordance with an embodiment. The electronic package <NUM> in <FIG> may be substantially similar to the electronic package <NUM> in <FIG>, with the exception that a second cavity <NUM>B and a second component <NUM> are positioned in the base substrate <NUM>. In an embodiment, the first cavity <NUM>A and the first component <NUM> may be at least partially within a footprint of the first die <NUM> and at least partially within a footprint of the second die <NUM>, and the second cavity <NUM>B and the second component <NUM> may be entirely within a footprint of the first die <NUM>.

In an embodiment, the second component <NUM> may be any of a variety of different component types, such as a die or die stack (e.g., a processor die, a memory die, a power die, a communication die, etc.), a passive component (e.g., a bridge, a capacitor, an inductor, etc.), a cooling module (e.g., a TEC module), or the like. In embodiments where the second component <NUM> is a die or a die stack, the second component <NUM> may be fabricated at a first process node and the die <NUM> may be fabricated at a second process node. In some embodiments, the first process node may be different than the second process node. In an embodiment, the first component <NUM> and the second component <NUM> may be the same component. In other embodiments, the first component <NUM> and the second component <NUM> may be different components.

In an embodiment, the second component <NUM> may comprise an active surface <NUM>. The active surface <NUM> may be oriented in a face-to-face configuration with the first die <NUM>. The second component <NUM> may be electrically coupled to the surface <NUM> of the base substrate <NUM> with FLIs <NUM>. In an embodiment, TSVs <NUM> may pass through the second component <NUM> to provide electrical connections from a backside surface of the second component <NUM> to the active surface <NUM> of the second component <NUM>. In an embodiment, the second component <NUM> may be embedded in a mold layer <NUM>. As shown in <FIG>, the mold layer <NUM> does not cover the backside surface of the second component <NUM>. Other embodiments may include the mold layer <NUM> covering the backside surface of the second component <NUM>.

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> with a first component <NUM> and a second component <NUM> is shown, in accordance with an embodiment. The electronic package <NUM> in <FIG> is substantially similar to the electronic package <NUM> in <FIG>, with the exception that the second component <NUM> is oriented in a different direction. As shown, the second component <NUM> is oriented with the active surface <NUM> facing away from the active surface <NUM> of the first die <NUM> (i.e., a face-to-back configuration). As such, the first component <NUM> and the second component <NUM> are oriented in opposite directions. However, it is to be appreciated that in some embodiments, both the first component <NUM> and the second component <NUM> may be oriented in a face-to-back configuration with the first die <NUM> and the second die <NUM>.

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> with a first component <NUM> and a second component <NUM> is shown, in accordance with an embodiment. The electronic package <NUM> in <FIG> may be substantially similar to the electronic package <NUM> in <FIG>, with the exception that the first component <NUM> does not include TSVs. In an embodiment, dummy PSBs <NUM>' may be positioned on the backside surface of the first component <NUM> in order to provide structural robustness. "Dummy PSBs" <NUM>' refer to PSBs that are not electrically coupled to other circuitry of the electronic package <NUM>. While the second component <NUM> is shown as having TSVs <NUM>, it is to be appreciated that in some embodiments, the second component <NUM> may also omit TSVs <NUM>.

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> with a first component <NUM> and a second component <NUM> is shown, in accordance with an embodiment. The electronic package <NUM> in <FIG> is substantially similar to the electronic package <NUM> in <FIG>, with the exception that there are no dummy PSBs <NUM>' below the first component <NUM>. Additionally, the mold layer <NUM> completely embeds the first component <NUM> (i.e., the backside surface of the first component <NUM> is covered by the mold layer <NUM>).

Referring now to <FIG>, a cross-sectional illustration of an electronic package <NUM> is shown, in accordance with an additional embodiment. In an embodiment, the electronic package <NUM> may be substantially similar to the electronic package 1C, with the exception that a plurality of components <NUM>A-C are included in the cavity <NUM>. For example, the plurality of components <NUM>A-C may comprise a stack of dies (e.g., a memory die stack).

Referring now to <FIG>, a plan view illustration of an electronic package <NUM> is shown, in accordance with an embodiment. In an embodiment, the electronic package <NUM> may comprise a first die <NUM> and a second die <NUM> placed over a base substrate <NUM>. The first die <NUM> may be electrically coupled to the second die <NUM> by a plurality of components <NUM> (e.g., bridges). In an embodiment, the plurality of components <NUM> may be disposed in a single cavity <NUM>. In other embodiments, each component <NUM> may be disposed in separate cavities <NUM>. As shown in <FIG>, additional components <NUM> and cavities <NUM> may be formed entirely under one of the first die <NUM> and/or the second die <NUM>.

Referring now to <FIG>, a plan view illustration of an electronic package <NUM> is shown, in accordance with an additional embodiment. In an embodiment, a first die <NUM>, a second die <NUM>A, and a third die <NUM>B may be placed over the base substrate <NUM>. In an embodiment, components <NUM> embedded in cavities <NUM> in the base substrate <NUM> may electrically couple the first die <NUM> to the second die <NUM>A, and/or electrically couple the first die <NUM> to the third die <NUM>B.

Referring now to <FIG>, a plan view illustration of an electronic package <NUM> is shown, in accordance with an additional embodiment. The electronic package <NUM> in <FIG> may be substantially similar to the electronic package <NUM> in <FIG>, with the exception that a cavity <NUM> below the first die houses a pair of components <NUM>, and a pair of cavities <NUM> are positioned below the second die <NUM>. Each of the cavities <NUM> may comprise one or more components <NUM>.

While <FIG> illustrate electronic packages <NUM> with one, two, or three dies and one or more components embedded in cavities in the base substrate, it is to be appreciated that embodiments are not limited to such configurations. For example, electronic packages may include a plurality of dies (e.g., two or more dies) and/or a plurality of components (e.g., two or more components). Furthermore, each cavity in the base substrate may house one or more components.

Referring now to <FIG>, a series of cross-sectional illustrations depict a process for fabricating an electronic package in accordance with an embodiment. In <FIG> only a single cavity, component, and die are shown for simplicity. However, it is to be appreciated that additional cavities and components and/or dies may also be included in the electronic package using similar processing operations to those described.

Referring now to <FIG>, a cross-sectional illustration of a base substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the base substrate <NUM> may be a silicon substrate. The base substrate <NUM> may have a thickness T<NUM>. For example, the thickness T<NUM> may be a standard wafer thickness (e.g., <NUM>).

In an embodiment, a surface <NUM> of the base substrate <NUM> may comprise a conductive features (e.g., traces, pads, etc.). In some embodiments, the base substrate <NUM> is a passive substrate. Other embodiments include an active base substrate <NUM>. For example, the base substrate <NUM> may comprise transistors or the like. In an embodiment, a plurality of TSVs <NUM> may be positioned in the base substrate <NUM>. As shown in <FIG>, the plurality of TSVs <NUM> may not extend entirely through the base substrate <NUM>. The TSVs <NUM> may be omitted from regions where a cavity is desired. For example, there are no TSVs <NUM> in a central region of the base substrate <NUM> shown in <FIG>.

Referring now to <FIG>, a cross-sectional illustration of the base substrate <NUM> after the base substrate is thinned is shown, in accordance with an embodiment. For example, the base substrate <NUM> may be thinned to have a thickness T<NUM> that is approximately <NUM> or less. The base substrate <NUM> may be thinned with a grinding or polishing process. As shown, thinned base substrate <NUM> may still have the TSVs <NUM> fully embedded. That is, the TSVs <NUM> do not pass completely through the base substrate <NUM> at this point.

Referring now to <FIG>, a cross-sectional illustration of the base substrate <NUM> after a carrier <NUM> is attached is shown, in accordance with an embodiment. In an embodiment, the carrier <NUM> may be secured to the surface <NUM> of the base substrate <NUM> by an adhesive film <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the base substrate <NUM> after a cavity <NUM> is formed is shown, in accordance with an embodiment. In an embodiment, the cavity <NUM> may be formed with an etching process that removes a portion of the base substrate <NUM>. The etching process may be a wet or dry etching process that utilizes a photoresist (not shown) over the base substrate <NUM> in order to define the boundary of the cavity <NUM>. The cavity <NUM> may extend through the base substrate <NUM> and end at the surface <NUM>. In an embodiment, a plurality of pads <NUM> may be exposed by the cavity <NUM>. The pads <NUM> may have been fabricated as part of the surface <NUM> prior to the formation of the cavity <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the base substrate <NUM> after a component <NUM> is mounted in the cavity <NUM> is shown, in accordance with an embodiment. The component <NUM> may be attached to the pads <NUM> exposed by the cavity <NUM> by FLIs <NUM>. In an embodiment, the attachment may be a thermocompression bonding (TCB) attachment process. In some embodiments a flux (e.g., epoxy flux) may be used during the attachment process. The FLIs <NUM> may comprise solder that is reflown between pads. In other embodiments, the FLIs <NUM> may comprise a copper to copper attachment. After attachment of the component <NUM> to the pads <NUM>, an underfill material <NUM> may be dispensed around the FLIs <NUM>.

In an embodiment, the component <NUM> may comprise any of a variety of different component types, such as a die or die stack (e.g., a processor die, a memory die, a power die, a communication die, etc.), a passive component (e.g., a bridge, a capacitor, an inductor, etc.), a cooling module (e.g., a TEC module), or the like. In an embodiment, the component <NUM> may comprise an active surface <NUM>. The active surface <NUM> may be oriented to face the surface <NUM>. However, in other embodiments, the active surface <NUM> may face away from surface <NUM> (e.g., similar to the component <NUM> shown in <FIG>). In some embodiments, the backside surface of the component <NUM> may be electrically coupled to the active surface <NUM> by one or more TSVs <NUM>. In other embodiments, the TSVs <NUM> may be omitted (e.g., similar to the component <NUM> shown in <FIG>).

The component <NUM> may sit completely in the cavity <NUM>. That is, the depth of the cavity <NUM> may be greater than a combined thickness of the component <NUM> and the FLIs <NUM>. Accordingly, a backside surface of the component <NUM> may be recessed below a backside surface of the base substrate <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the base substrate <NUM> after the cavity <NUM> is filled with a mold layer <NUM> is shown, in accordance with an embodiment. The mold layer <NUM> may substantially fill the remainder of the cavity <NUM>. In an embodiment, the mold layer <NUM> may be an epoxy or the like. In some embodiments, the mold layer <NUM> may also surround the FLIs <NUM>, and in which case, the underfill material <NUM> may be omitted. The mold layer <NUM> may also embed the component <NUM>. For example, the mold layer <NUM> may cover sidewalls and a backside surface of the component <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the base substrate <NUM> after it has been planarized to expose the TSVs <NUM> and TSVs <NUM> is shown, in accordance with an embodiment. In an embodiment, the base substrate <NUM> may be planarized with a polishing process (e.g., chemical mechanical polishing (CMP) or the like). The polishing process may also recess the mold layer <NUM> to expose the backside surface of the component <NUM> and the TSVs <NUM> (when present).

Referring now to <FIG>, a cross-sectional illustration of the base substrate <NUM> after PSBs <NUM> are disposed over the TSVs <NUM> and <NUM> is shown, in accordance with an embodiment. In an embodiment, the PSBs <NUM> may comprise a pad or bump (e.g., a copper bump) and/or a solder ball. In an embodiment, the PSBs <NUM> over the TSVs <NUM> may be substantially similar to the PSBs <NUM> over the TSVs <NUM> of the component <NUM>.

Referring now to <FIG>, a cross-sectional illustration after the carrier <NUM> is removed is shown, in accordance with an embodiment. In an embodiment, the carrier <NUM> may be removed by mechanically separating the carrier <NUM>. In an embodiment, any residual portion of the adhesive film <NUM> on the base substrate <NUM> may be cleaned with suitable cleaning processes.

Referring now to <FIG>, a cross-sectional illustration after a die <NUM> is attached to the base substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the die <NUM> may be attached to the base substrate <NUM> with FLIs <NUM>. For example, the attachment process may be a TCB process or the like. A mold layer <NUM> may then be formed over the die <NUM>, with suitable processes (e.g., molded underfill (MUF) process). In an embodiment, the mold layer <NUM> may cover sidewall surfaces of the die <NUM>, and a backside surface of the die <NUM> may remain exposed. In other embodiments, the backside surface of the die <NUM> may be covered by the mold layer <NUM>.

In an embodiment, the die <NUM> may have an active surface <NUM>. The active surface <NUM> may be oriented to face the surface <NUM> of the base substrate <NUM>. Accordingly, the die <NUM> may be referred to as having a face-to-face configuration with the base substrate <NUM> and with the component <NUM>. In embodiments where the component is oriented with the active surface <NUM> facing away from surface <NUM>, the die <NUM> and the component <NUM> may be referred to as having a face-to-back orientation.

Referring now to <FIG>, a series of cross-sectional illustrations depicting a process for forming an electronic package with a via-last process flow is shown, in accordance with an embodiment.

Referring now to <FIG>, a cross-sectional illustration of a base substrate <NUM> is shown, in accordance with an embodiment. The base substrate <NUM> may be a silicon substrate in some embodiments. In an embodiment, the base substrate <NUM> may comprise a surface <NUM>. The surface <NUM> may comprise conductive features (e.g., pads, traces, etc.). In some embodiments where the base substrate <NUM> is an active substrate, the surfaces <NUM> may also comprise active circuitry (e.g., transistors or the like). In an embodiment, the base substrate <NUM> may have a thickness T<NUM>. For example, the thickness T<NUM> may be approximately <NUM> or less. It is to be appreciated that the reduced thickness T<NUM> (compared to a typical silicon wafer thickness of <NUM>) may be provided by grinding the base substrate <NUM> down to a desired thickness. In contrast to the base substrate <NUM> illustrated in <FIG>, the base substrate <NUM> does not have TSVs at this point in the process flow.

Referring now to <FIG>, a cross-sectional illustration of the base substrate <NUM> after TSVs <NUM> are formed is shown, in accordance with an embodiment. In an embodiment, the TSVs <NUM> may be formed by creating openings through the base substrate <NUM> and filling the openings with a conductive material. The openings may be formed with an etching process using a photoresist (not shown) as a mask. The TSVs <NUM> may have a surface exposed at the backside surface of the base substrate <NUM>.

Referring now to <FIG>, a cross-sectional illustration of the base substrate after a cavity is formed is shown, in accordance with an embodiment. In an embodiment, the cavity <NUM> may be formed with an etching process that removes a portion of the base substrate <NUM>. The etching process may be a wet or dry etching process that utilizes a photoresist (not shown) over the base substrate <NUM> in order to define the boundary of the cavity <NUM>. The cavity <NUM> may extend through the base substrate <NUM> and end at the surface <NUM>. In an embodiment, a plurality of pads <NUM> may be exposed by the cavity <NUM>. The pads <NUM> may have been fabricated as part of the surface <NUM> prior to the formation of the cavity <NUM>.

After formation of the cavity <NUM>, the processing may continue with substantially the same processing operations detailed with respect to <FIG> in order to provide an electronic package in accordance with an embodiment.

Referring now to <FIG> a series of cross-sectional illustrations depicting a process for forming a cavity and disposing a component in the cavity is shown in greater detail, in accordance with an embodiment.

Referring now to <FIG>, a cross-sectional illustration of a base substrate <NUM> on a carrier <NUM> is shown, in accordance with an embodiment. The base substrate <NUM> may be attached to the carrier <NUM> with an adhesive film <NUM>. The adhesive film may cover the surface <NUM> of the base substrate <NUM> and any pads <NUM> over the surface <NUM>. In some embodiments, the surface <NUM> may comprise conductive features <NUM>, such as traces, pads, vias, and the like that will provide interconnections to components and dies of the electronic package.

In an embodiment, a plurality of pads <NUM> may be formed along the surface <NUM> and embedded in the body of the base substrate <NUM>. The pads <NUM> are located where the component will be attached in a subsequent processing operation. In some embodiments, the pads <NUM> may be separated from the surface <NUM> by an insulative liner (e.g., SiN or the like). In an embodiment, the base substrate <NUM> may also comprise TSVs <NUM> that are over pads <NUM>. The TSVs <NUM> may not extend entirely through the base substrate <NUM> at this point in the process flow.

Referring now to <FIG>, a cross-sectional illustration of the base substrate <NUM> after a cavity <NUM> is formed is shown, in accordance with an embodiment. In an embodiment, the cavity <NUM> may be formed into the base substrate <NUM> through the backside surface. The cavity <NUM> may be positioned between TSVs <NUM> and expose the pads <NUM>. In some embodiments, the cavity <NUM> may be lined with a lining (not shown) such as a nitride. The exposed pads <NUM> may also be plated with a conductive barrier layer, or the like.

Referring now to <FIG>, a cross-sectional illustration after the component <NUM> is attached to the pads <NUM> is shown, in accordance with an embodiment. In an embodiment, the component <NUM> may comprise pads <NUM> over an active surface <NUM>. The pads <NUM> may be coupled to the pads <NUM> with a FLIs <NUM>. The FLIs <NUM> may comprise solder. In other embodiments, the FLIs <NUM> may comprise a copper to copper interconnection between the pads <NUM> and the pads <NUM>.

Referring now to <FIG>, a cross-sectional illustration after a mold layer <NUM> is disposed into the cavity <NUM> is shown, in accordance with an embodiment. In an embodiment, the mold layer <NUM> may be an epoxy or the like. In the illustrated embodiment, the mold layer <NUM> may also function as an underfill material that surrounds the FLIs <NUM>. However, other embodiments may include a dedicated underfill material that surrounds the FLIs <NUM> and that is distinct from the mold layer (e.g., similar to what is shown in <FIG>). After the mold layer <NUM> fills the cavity <NUM>, the base substrate <NUM> (and the mold layer <NUM>) may be planarized in order to expose the TSVs <NUM> at the backside surface of the base substrate <NUM>. While not illustrated in <FIG>, it is to be appreciated that the planarizing process may also expose TSVs in the component <NUM> when they are present.

Referring now to <FIG>, a series of cross-sectional illustrations depicting a process for forming a cavity and disposing a component in the cavity with a via last process is shown in greater detail, in accordance with an embodiment.

In an embodiment, a plurality of pads <NUM> may be formed along the surface <NUM> and embedded in the body of the base substrate <NUM>. The pads <NUM> are located where the component will be attached in a subsequent processing operation. In some embodiments, the pads <NUM> may be separated from the surface <NUM> by an insulative liner (e.g., SiN or the like). In contrast to the embodiment shown in <FIG>, the base substrate <NUM> may omit TSVs at this point in the process flow.

Referring now to <FIG>, a cross-sectional illustration after via openings <NUM> are formed into the base substrate <NUM> is shown, in accordance with an embodiment. In an embodiment, the openings <NUM> may be formed with an etching process that utilizes a photoresist mask (not shown) to define the openings. In some embodiments, the openings <NUM> may be lined with an insulating liner (e.g., SiN, or the like). The openings <NUM> may expose portions of pads <NUM> embedded in the base substrate <NUM>.

Referring now to <FIG>, a cross-sectional illustration after TSVs <NUM> are disposed in the openings <NUM> is shown, in accordance with an embodiment. In an embodiment, the TSVs <NUM> may be plated with any suitable process, such as electroless plating or the like.

Referring now to <FIG>, a cross-sectional illustration of the base substrate <NUM> after a cavity <NUM> is formed and a component is disposed in the cavity <NUM> is shown, in accordance with an embodiment. In an embodiment, the cavity <NUM> may be formed into the base substrate <NUM> through the backside surface. The cavity <NUM> may be positioned between TSVs <NUM> and expose the pads <NUM>. In some embodiments, the cavity <NUM> may be lined with a lining (not shown) such as a SiN. The exposed pads <NUM> may also be plated with a conductive barrier layer, or the like.

In an embodiment, the component <NUM> may comprise pads <NUM> over an active surface <NUM>. The pads <NUM> may be coupled to the pads <NUM> with a FLIs <NUM>. The FLIs <NUM> may comprise solder. In other embodiments, the FLIs <NUM> may comprise a copper to copper interconnection between the pads <NUM> and the pads <NUM>. Subsequent to the attachment of the component <NUM> to pads <NUM>, the processing flow may continue in substantially the same manner described above with respect to <FIG>.

Referring now to <FIG>, a cross-sectional illustration of an electronic system <NUM> is shown, in accordance with an embodiment. In an embodiment, the electronic system <NUM> may comprise an electronic package <NUM> that is attached to a board <NUM>, such as a printed circuit board (PCB) or the like. In an embodiment, the electronic package <NUM> may be coupled to the board <NUM> with PSBs <NUM> or any other suitable interconnect architecture.

In an embodiment, the electronic package <NUM> may be any package such as those described above in greater detail. For example, the electronic package <NUM> may comprise a base substrate <NUM>. In an embodiment, the base substrate <NUM> may be an active or passive substrate. The base substrate <NUM> may comprise a surface <NUM> that includes conductive routing or other conductive features (not shown). The base substrate <NUM> may comprise silicon. In an embodiment, a plurality of dies (e.g., dies <NUM> and <NUM>) may be coupled to the base substrate. For example, active surfaces <NUM> and <NUM> of the dies <NUM> and <NUM> may be attached to the surface <NUM> with FLIs <NUM>. In an embodiment, the base substrate <NUM> may comprise TSVs <NUM>. In an embodiment, the plurality of dies <NUM>, <NUM> may be embedded in a mold layer <NUM>.

In an embodiment, the base substrate <NUM> may comprise a plurality of cavities (e.g., cavities <NUM>A and <NUM>B). In an embodiment, one or more of the cavities <NUM> are entirely within a footprint of one of the dies <NUM>, <NUM>. In other embodiments, one or more of the cavities <NUM> are at least partially within a footprint of a first die <NUM> and at least partially within a footprint of a second die <NUM>.

In an embodiment, each of the cavities <NUM> may be filled with a component (e.g., component <NUM> or component <NUM>). The components <NUM>, <NUM> may be any of a variety of different component types, such as a die or die stack (e.g., a processor die, a memory die, a power die, a communication die, etc.), a passive component (e.g., a bridge, a capacitor, an inductor, etc.), a cooling module (e.g., a TEC module), or the like. In embodiments where the component <NUM> and/or <NUM> is a die or a die stack, the components <NUM>, <NUM> may be fabricated at a first process node and one or both of the dies <NUM>, <NUM> may be fabricated at a second process node. In some embodiments, the first process node may be different than the second process node. In an embodiment, the components <NUM>, <NUM> may comprise active surfaces <NUM>, <NUM>. The active surfaces <NUM>, <NUM> may be oriented in a face-to-face configuration or back-to-face configuration with the dies <NUM>, <NUM>. In an embodiment, one or both of the components <NUM>, <NUM> may comprise TSVs <NUM>, <NUM>. The components <NUM>, <NUM> may be electrically coupled to the surface <NUM> of the base die <NUM> with interconnects <NUM>.

<FIG> illustrates a computing device <NUM> in accordance with one implementation of the invention. The computing device <NUM> houses a board <NUM>. The board <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> is physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> is also physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within the processor <NUM>. In some implementations of the invention, the integrated circuit die of the processor may be packaged in an electronic system that comprises a multi-chip package with a base substrate that comprises a cavity that houses a component, in accordance with embodiments described herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. In accordance with another implementation of the invention, the integrated circuit die of the communication chip may be packaged in an electronic system that comprises a multi-chip package with a base substrate that comprises a cavity that houses a component, in accordance with embodiments described herein.

Claim 1:
A multi-chip electronic package (<NUM>), comprising:
a base substrate (<NUM>), the base substrate (<NUM>) having a plurality of through substrate vias (<NUM>);
a first die (<NUM>) over the base substrate (<NUM>);
a second die (<NUM>) over the base substrate (<NUM>);
a first cavity (115A) into the base substrate (<NUM>), wherein the first cavity (<NUM>) is partially within a footprint of the first die (<NUM>) and partially within a footprint of the second die (<NUM>);
a second cavity (115B) into the base substrate (<NUM>), wherein the second cavity (115B) is entirely within a footprint of the first die (<NUM>);
a first component (<NUM>) in the first cavity (115A); and
a second component (<NUM>) in the second cavity (115B),
wherein the first component (<NUM>) includes an active surface (<NUM>) that is electrically coupled to a backside surface of the first component (<NUM>) with one or more through substrate vias, TSVs, (<NUM>) and/or the second component (<NUM>) includes an active surface (<NUM>) that is electrically coupled to a backside surface of the second component (<NUM>) with one or more TSVs (<NUM>).