Patent Description:
Quantum computing is a class of computing in which inherently quantum mechanical phenomena, such as quantum state superposition and entanglement, are harnessed to perform certain computations far more quickly than any classical computer could ever be capable of. In a "topological" quantum computer, calculations are performed by manipulating quasiparticles - called "non-abelian anyons" - that occur in certain physical systems. Anyons have unique physical characteristics that distinguish them from both fermions and bosons. Non-abelian anyons also have unique properties with respect to abelian anyons. It is these unique properties that serve as a basis for topological quantum computing, in which information is encoded as a topological property of non-abelian anyons; specifically the braiding of their space-time worldlines. This has certain benefits over other models of quantum computation. One key benefit is stability, as the quantum braiding is unaffected by perturbations on a scale that could cause error-inducing quantum decoherence in other types of quantum computer.

Broadly speaking, to date, two types of physical system have been considered as potential hosts of non-abelian anyons, namely "<NUM>/<NUM> fractional quantum Hall" systems in condensed matter physics, and (more recently) semiconductor-superconductor (SE/SU) nanowires. Regarding the latter, a key advance in the field was the realization that non-abelian anyons, in the form of "Majorana zero modes" (MZMs) can be formed in semiconductor (SE) nanowires (NWs) coupled to a superconductor (SU).

One of the issues encountered in the context of SE/SU nanowires is the existence of so-called "soft gap" states. The soft gap issue been documented in publicly-available literature, and suffice it to say that these soft gap states, when present, are a source of decoherence for the MZMs. Analysis and experiments indicate that a source of the soft gap is disorder in the SE/SU interface, and there has been recent work in the field on improving the quality of the SE/SU interface with the aim of providing more stable MZMs.

Das <NPL>" discloses a catalyst-free growth technique to directly integrate III-V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. Krogstrup et al.

(<NPL>" discloses epitaxial growth of semiconductor-metal core-shell nanowires by molecular bean epitaxy.

Whilst recent developments in fabrication technology have led to significant improvements in the quality of the SE/SU interface in SE/SU nanowires, the approaches in question are all facing challenges with scalability. This imposes limits on the size and complexity of the SE/SU nanowire networks that can be fabricated with these approaches. Examples are given later to provide context.

Provided herein are methods of fabricating SE/SU nanowire structures, which can not only produce high-quality SE/SU interfaces but can also do so in a scalable manner to allow the production of large and potentially complex SE/SU nanowire networks. This is achieved through a combination of selective area grown (SAG) semiconductor technology with superconductor deposition/growth (note, the terms "selected area growth" and "selective area growth" are used interchangeably herein).

In one aspect, the present invention provides a method of fabricating a mixed semiconductor-superconductor platform, according to claim <NUM>. The method comprises the following steps. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. The semiconductor material in the one or more exposed regions forms a network of in-plane nanowires. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

The layer of superconducting material may be epitaxially grown in the superconductor growth phase.

The superconducting material may be epitaxially grown using molecular beam epitaxy (MBE).

The layer of superconducting material may be formed, in the superconductor growth phase, using a beam.

The beam may have a non-zero angle of incidence relative to the normal of a plane of the substrate.

The particle beam may be angled relative to the substrate, such that the beam is incident on one side of a structure protruding outwardly of the plane of the substrate, thereby preventing a shadow region on the other side of the protruding structure from being covered with the superconductor material.

The protruding structure may be a protruding portion of the semiconductor material, such that the shadow region separates the semiconductor material from a portion of the superconductor material deposited in a gating region.

The method may comprise: removing semiconductor material from the gating region; and forming a gate, from a gating material, in the gating region.

The protruding structure may be formed of dielectric material.

The protruding structure may be adjacent a nanowire formed by the semiconductor material, the shadow region extending across the width of the nanowire such that a section of the nanowire is not covered by the superconductor material across its entire width, thereby forming a junction between two further sections of the nanowire, both of which are at least partially covered by the superconductor material.

The selective area growth phase and the superconductor growth phase may be performed in a vacuum chamber, with the substrate remaining in the vacuum chamber throughout and in between those phases.

Another aspect of the present invention provides a quantum circuit according to claim <NUM>, comprising: a selective area grown (SAG) semiconductive region comprising conducting in-plane nanowires; and a superconducting region. The superconducting region comprises superconductor material in direct contact with semiconductor material of the SAG semiconductive region.

The in-plane nanowires may be tunable via a side gate, top gate, or bottom gate.

The quantum circuit may comprise an insulating substrate on which the SAG semiconductive region was grown and a dielectric mask formed on the insulating substrate, the superconducting region formed of superconductor material selectively grown on one or more regions of the substrate that are not covered by the dielectric mask.

Another aspect of the present invention provides a topological quantum computer according to claim <NUM>, comprising: a network of selective area grown (SAG) nanowires; and a layer of superconductor material formed on the SAG nanowires. The network of SAG nanowires and the superconductor material are coupled so as to provide Majorana modes for use in performing quantum computations.

For a better understanding of the present technology, and to show how embodiments of the same may be carried into effect, reference is made by way of example only to the following figures in which:.

Epitaxial semiconductor-superconductor materials are a promising platform for gatable low-dissipation superconducting electronics and superconducting quantum computation. In the context of topological quantum computing, superconducting nanowires with strong spin-orbit coupling can support topological excitations that can serve as the basis for fault tolerant quantum information processing.

Current approaches to synthesize semiconductor-superconductor materials for gatable superconducting nanowire electronics are either based on two-dimensional planar materials (see, e.g., <NPL>)) or bottom up grown nanowire materials (see, e.g.,<NPL>)). Both approaches are facing challenges with scalability for different reasons. Regarding the latter approach, this has been able to achieve a very high quality SE/SU interface. However, with this approach, the SE/SU nanowires to form part of a network have to be individually grown and, once grown, individually placed on an insulating material to form the actual network. Thus, scaling up this approach to larger networks presents very significant challenges.

Example embodiments of the disclosed technology provide a solution to the problem of scalability by combining SAG semiconductors with a superconducting phase.

With reference to <FIG>, an example three-phase fabrication method will now be described. The fabrication method can be used to create a network of SE/SU nanowires, which in turn can for example form the basis of a quantum circuit (e.g. for a quantum computer) or other mixed semiconductor-superconductor platform. In particular, the method is particularly suitable for fabricating a SE/SU nanowire network capable of hosting stable MZMs, with no or significantly reduced soft gap decoherence, which can form the basis of fault-free topological quantum computations.

It is noted, however, that although the material platform is relevant for quantum computing, the gatable superconducting electronics it provides may well have other applications outside of or which are not directly related to quantum computing, particularly in contexts where low energy dissipation is required.

As will become apparent, because the SE/SU nanowire network is created using SAG, an entire nanowire network can be fabricated as a whole on an insulating substrate. The insulating substrate and the nanowire can incorporated directly into the final product, without any need to transfer the nanowires to a different surface. Thus the method is significantly more saleable than the existing approaches.

In a first phase P1 (masking phase) a patterned layer of dielectric material <NUM> (dielectric mask) is formed on top of an insulating substrate <NUM>. A side-view and a top-view of the substrate <NUM> with the dielectric mask <NUM> are shown on the left hand side of <FIG>. The substrate <NUM> can be formed of any suitable substrate material such as InP (Indium Phosphide), and is an insulating substrate in the described examples. In the described examples, the dielectric material <NUM> is an oxide but it can be any dielectric material that facilitates SAG in a second phase P2 of the fabrication method (see below).

The oxide layer is patterned in that the oxide layer <NUM> is formed so as to leave narrow strips of the substrate - in a desired region <NUM> - exposed (i.e. not covered by the oxide <NUM>). The pattern in this context refers to the structure of the desired region <NUM>, which will ultimately become the structure of the nanowire network, as it is this exposed region <NUM> in which SE nanowires are grown. Accordingly, the size and structure of the nanowires matches the size and structure of the exposed region <NUM>. Although only one exposed region <NUM> is shown in <FIG>, nanowires can be grown simultaneously in multiple regions and all description pertaining to the desired region <NUM> applies equally to multiple such regions. Accordingly, the structure of an entire nanowire network can be defined by the structure of the exposed region(s). In this example, the strips and hence the resulting nanowires have a width of the order of tens or hundreds of nanometers.

The oxide layer <NUM> can be formed so as to leave the desired region <NUM> exposed in any suitable manner. For example, a uniform, continuous layer of oxide can be deposited on the substrate <NUM>, and the exposed region <NUM> can then be formed by selectively etching away the oxide <NUM> from the desired region <NUM> (in this case, it is the etching that defines the eventual nanowire network structure). As another example, the oxide layer <NUM> can be selectively deposited on the substrate <NUM> with a mask used to prevent deposition of the oxide <NUM> in the desired regions <NUM> (in this case, it is the mask that defined the eventual nanowire network structure).

The SAG nanowires are defined along high symmetry in-plane crystal orientations on the substrate, which also gives well-defined faceting of the nanowires. This makes the SU/SE interface flat, potentially atomically flat, and well defined.

In the second phase P2, namely the SAG phase, a semiconductor material <NUM> is selectively grown within the desired regions <NUM>, on top of the exposed portion of the substrate <NUM>. An example is illustrated at the top right of <FIG>, at which a side-view of the substrate <NUM> is shown. Due to the patterning of the oxide layer <NUM>, the selectively grown semiconductor <NUM> forms in-plane nanowires (that is, nanowires lying in the place of the substrate <NUM>).

SAG is a growth method using crystal growth vacuum chambers. SAG refers to localized growth of semiconductor in exposed regions of the substrate, with growth conditions selected to prevent such growth on the dielectric mask itself. This can be based on Chemical Beam Epitaxy (CBE), Molecular Beam Epitaxy (MBE), or Metal-Organic Chemical Vapour Deposition (MOCVD), for example. In the context of semiconductors, SAG refers to a particular class of epitaxial semiconductor growth (and is also referred to as selective area epitaxy), in which a patterned dielectric mask is used to define the intended structure of the semiconductor material to be grown (a form of lithography). The SAG process is tuned such that semiconductor growth occurs only on regions of the substrate that are not covered by the dielectric mask, and not on the dielectric mask itself. This is quite different from other deposition/growth processes, such as bottom up growth (in which no mask is used) and uniform deposition (epitaxial or otherwise) in which material is uniformly deposited across a surface irrespective its material composition (as in phase P3 - see below). SAG is conducted in a high or ultra-high vacuum, and requires careful tuning to achieve the desired selective semiconductor growth.

Any suitable SAG process can be used in the second phase P2 to create the desired SE nanowires in the exposed region <NUM>.

SAG per-se is known, and is therefore not discussed in further detail herein. For further description of SAG, see, e.g., <NPL>; <NPL>; <NPL>.

Suffice it to say that the SAG phase P2 is such that, at the end of that phase, the semiconductor material <NUM> fills the desired region <NUM> (that is, the region <NUM> in which the substrate <NUM> is not covered by the oxide mask <NUM>) but does not extend, in the plane of the substrate <NUM> (xy-plane hereafter), beyond the boundaries of the desired region <NUM> as defined the oxide layer <NUM>. However, as can be seen, it does extend outwardly in a direction normal (perpendicular) to the plane of the substrate <NUM> (z-direction hereafter) so as to protrude outwardly of the oxide mask <NUM>. That is, the semiconductor material <NUM> extends a greater distance from the substrate <NUM> than the oxide layer <NUM> in the z-direction. In this manner, the semiconductor material <NUM> forms nanowires lying substantially in the plane of the substrate <NUM> (in-place nanowires).

The semiconductor material <NUM> can be any suitable semiconductor material, such as Indium arsenide (InAs). The SAG semiconductor <NUM> can for example be confined 2DEG (two-dimensional electron gas) semiconductor or single material semiconductor.

In a third phase P3 (superconductor growth phase) a layer of superconducting material <NUM> is grown using a particle beam <NUM>. Herein, a superconducting material means a material that exhibits superconducting properties at least under certain conditions. An example of such a material is aluminum (Al). In the following examples, the superconductor is grown epitaxially in phase P3, and the superconductor growth phase P3 may be referred to as an epitaxial growth phase in this context. However, the technology is not limited in this respect, and it may be possible to achieve the intended result via non-epitaxial superconductor growth in phase P3.

The superconducting material <NUM> can be grown in phase P3 using molecular beam epitaxy (MBE) electron gun epitaxy, for example.

At least part of the superconductor layer <NUM> is deposited on top of the SE nanowire <NUM> such that this part of the superconductor layer <NUM> (labelled <NUM> in <FIG>) is in direct contact with the SE nanowire <NUM>. That is, such that the SE nanowire <NUM> is at least partially covered with superconducting material.

This is also a form of epitaxy, but it is not SAG. In particular, in the epitaxial growth phase P3, epitaxial growth does occur on the oxide layer <NUM>, as well as on the SE nanowires <NUM>.

The beam can be angled in substantially the z-direction such that essentially all of the exposed surfaces of the oxide layer <NUM> and the SE material <NUM> are covered by the SU layer <NUM>. However, in this example, the particle beam <NUM> is incident on the substrate <NUM> with a non-zero angle of incidence relative to the z-direction (deposition angle). As a consequence of this non-zero deposition angle and the protruding structure of the SE nanowire <NUM>, the SE nanowire <NUM> is only partially coated by the superconductor layer <NUM>; that is, a part of the SE nanowire (labelled <NUM>) is not coated by the superconductor material. The bulk of the oxide layer <NUM> is also coated by the superconductor layer <NUM>, however due to the angle of the incoming beam <NUM> and the protruding structure of the SE nanowires <NUM>, small regions of the oxide layer <NUM> (shadow regions) immediately adjacent the protruding SE nanowires <NUM> are left exposed, i.e. not coated by the SU material. One such shadow region is labelled <NUM> in <FIG>. The shadow region <NUM> separates the SE material <NUM> from a portion of the SU layer <NUM> in a "sidegate" region <NUM>. The portion of the SU layer <NUM> in the sidegate region <NUM> can be used to form a gate for controlling the SE nanowires <NUM>, or (more likely) the SU material can be etched away from this region and replaced with a more suitable gate material, as in the example below. Either way, the shadow gap <NUM> ensures the gate operates as intended. Forming the gap <NUM> using such "in-situ" patterning in the SU epitaxy phase P3 (as described above) ensures that material does not need to be etched away too close to the delicate nanowires <NUM>.

This is an example of the basic process where the superconductor is deposited as a uniform layer, but where a "shadow" from the selective area grown material is used to form a gap between the semiconductor and the superconductor. In this particular case, the superconductor, that does not touch the semiconductor, can be used as a side gate or etched away and replaced with a more suitable gate material, while the superconductor that are in direct contact with the semiconductor are used to induce superconductivity.

The bottom right of <FIG> shows both a side-view and a top-view of the substrate <NUM> at the end of the third phase P3. Note that, in the top-view, the part <NUM> of the superconductor layer <NUM> that partially coats the SE nanowire <NUM> is not distinguished from the uncoated part <NUM> of SE nanowires <NUM>; rather the combined nanowire structure formed of the nanowires <NUM> and the portion of the superconductor material <NUM> that (partially) covers those nanowires (i.e. that is in direct contact therewith) is depicted as a single element, labelled SE//SU. This combined structure is similarly represented and labelled in later figures, and herein references to "SE/SU nanowires" or "SEHSU nanowires" refer to the SE nanowires <NUM> and the SU material <NUM> that (partially) covers the SE nanowires <NUM>, unless otherwise indicated.

To further aid illustration, <FIG> shows a schematic perspective view of first and second nanowires 108A, 108B during the third phase P3, which are partially coated by respective parts 116A, 116B of the superconductor layer <NUM>. A shadow gap <NUM> of the kind described above is shown, which is immediately adjacent the first nanowire 108A and separates the first nanowire 108A from a portion of the semiconductor layer <NUM> in a sidegate region <NUM>, in the manner described above.

The SAG phase P2 and superconductor growth phase P3 can be conducted in a vacuum chamber, preferably without moving the substrate <NUM> between phases. These phases can be carried out under high vacuum or ultra-high vacuum conditions (~<NUM>-<NUM> - <NUM>-<NUM> Torr or less), and those vacuum conditions may be maintained between phases. Among other things, this ensures a clean SE/SU interface, free from unwanted impurities.

As will be appreciated, both the SAG semiconductor growth of phase P2 and the superconductor growth of phase P3 require carefully calibrated conditions to get within respective "growth windows" for these two phases, and thereby achieve the desired semiconductor and superconductor growth respectively. Depending on the material type, the growth conditions, temperature and flux needs to chosen carefully. For example, for MBE (which can be used in both the semiconductor SAG phase P2 and superconductor growth phase P3), the substrate generally needs to be heated to temperatures of around <NUM> or more to clean the surface for native oxide. However, in the SE SAG growth phase P2 and SU growth phase P3, the respective temperature windows in which the desired growth takes place is dependent on the composition of the SE material <NUM> and SU material <NUM> respectively. The superconductor is grown/deposited in-situ, without breaking vacuum. In this way the surface of SAG is not oxidized in air and remain clean until the SU is put on, which ensure a clean SE-SU interface.

Using SAG as a basis for gatable superconductor network desirably involves an insulated substrate, and that the selective area grown material can carry induced superconductivity.

The substrate <NUM> and oxide layer <NUM> on which the SEHSU nanowire network is grown can be incorporated in the end-product, such as a quantum circuit or quantum computer, along with the SE/SU nanowire network, without transferring the nanowires from the substrate on which they were originally fabricated.

Embodiments of the disclosed technology include topologically protected quantum computing circuits that comprise networks of nanowires formed using such mixed semiconductor and superconductor regions.

In <FIG>, for instance, a wire-pattern consisting of InAs nanowires grown on an insulating InP substrate is shown. In particular, <FIG> shows the fabrication of a complicated network based on one-dimensional nanowire network. The network is a SAG InAs nanowire network formed on an InP substrate.

<FIG> shows a schematic top-view of a T-shaped SE//SU nanowire structure, which has been fabricated using the method described above, to form a quantum circuit <NUM>. Contacts <NUM> of the quantum circuit <NUM> have been added to the SE//SU nanowires, to allow electrical connection therewith. Gating regions <NUM> are shown, in which most of the SU material <NUM> has been etched away, e.g. to be replaced with a different gating material (not shown), in order to form a side gate for manipulating the SE//SU nanowires, and - in the context of topological quantum computing, for example - for manipulating Majorana zero modes hosted by the SE//SU nanowires, in order to perform quantum computations.

<FIG> shows a top-view image <NUM> of two matching, side-by-side example SE/SU nanowire structures 502a, 502b, fabricated according to the described method. Here, contacts (bright vertical lines) and top-gates (dark vertical line) can be seen applied to SAG nanowires (bright horizontal lines). These can be added using lithography methods, for example.

<FIG> also shows respective I-V (current-voltage) graphs 504a, 504b for the matching structures 502a, 502b respectively. As can be seen, the two SE/SU nanowire structures 502a, 502b exhibit very similar I-V characteristics. This demonstrates one of the benefits of the fabrication method, namely reproducibility, i.e. the ability to produce nanowire structures with consistent physical characteristics. This level of reproducibility represents a significant improvement with respect to existing nanowire fabrication methods.

<FIG> and <FIG> schematically illustrate one example of an extension of the method of <FIG>, in which protruding dielectric structure 102P is used, in conjunction with an angled beam <NUM> in the superconductor growth phase P3, to perform in-situ patterning. The principle is similar to the in-situ patterning provided by the protruding SE material <NUM>, in that the protruding dielectric structure 102P selectively obstructs the angles beam to prevent deposition of the SU material <NUM> from occurring in certain shadow regions of the kind described.

In this example, the protruding dielectric structure 102P is a "pillar" of dielectric material located adjacent a SE nanowire <NUM>, so as to provide a shadow region <NUM> extending across the entire width of the nanowire <NUM>, such that the nanowire <NUM> is entirely uncoated with SU material in this region <NUM> across its entire width. This uncoated portion <NUM> thus forms a SE junction between two sections 604a, 604b of SE/SU nanowire. This is shown in the side and top views of <FIG>, and the perspective view of <FIG>.

As illustrated in <FIG>, multiple protruding dielectric structures 102P can be used to achieve any desired in-situ patterning.

As will be appreciated, this is not limited to the formation of junctions, and protruding dielectric structures (e.g. walls, pillars, loops etc.) can be used, individually or in combination, to achieve any desired patterning of the SU material, according to the principles set out above.

<FIG> illustrates two crystalline nanowire structures that may be found in certain types of quantum circuit, namely a "[<NUM>]" SE/SU nanowire and a "[<NUM>]" SE/SU nanowire. Here, [<NUM>] and [<NUM>] are Miller indices, which in this context refer to the orientation of a nanowire's crystalline structure relative to the nanowire orientation itself. As can be seen, different miller indices result in the growth of different shaped nanowires in the SAG phase P2. In particular, an SAG [<NUM>] wire has an essentially triangular profile when a cross-section is taken across their width, whereas an SAG [<NUM>] wire has a flatter portion at its top. On account of the different profiles, in the epitaxial growth phase P3, the angle of the particle beam <NUM> is preferably selected in dependence on the miller index of the SAG nanowire(s). For [<NUM>] nanowires, an angle of at least <NUM> digress relative to the z-axis may be suitable, whereas for [<NUM>] nanowires, an angle of at least <NUM> degrees may be appropriate.

<FIG> and <FIG> show top-down images of fabricated SE//SU nanowires for different deposition angles - illustrated schematically at the top-left of each figure. As can be seen, different deposition angles can be used to achieve shadow gaps <NUM> of different widths. Here, the shadow gap is created due to the SE nanowire <NUM> obstructing the angles beam, as described above, to separate the resulting SE/SU nanowire from a gating region <NUM>.

The SE/SU nanowires of <FIG> were fabricated using Al deposition from an electron-gun (e-gun) at a low temperature stage in a metal deposition chamber.

The SE/SU nanowires of <FIG> and <FIG> were fabricated using MBE, in an MBE chamber, with a beam angle of only <NUM> degrees from normal (i.e. relative to the z-axis as defined above). This is purely an example and most systems allow the angle to be varied to the desired direction.

<FIG> shows another image of an SE/SU nanowire structure fabricated using the described methods.

In general, the superconducting material can either deposited/grown uniformly on the whole substrate and subsequently removed in specified regions, or deposited/grown in specified regions using lithography masks during deposition/growth. This can be a form on in-situ patterning, as described above. In some example implementations, the selective-area-grown materials leave conducting in-plane oriented nanowires that can be tuned with a side gate, top gate, and/or a bottom gate. Further, in some example implementations, the substrate is insulated to prevent leakage currents.

Claim 1:
A method of fabricating a mixed semiconductor-superconductor platform, the method comprising:
in a masking phase (P1), forming a dielectric mask (<NUM>) on a substrate (<NUM>), such that the dielectric mask (<NUM>) leaves one or more regions of the substrate (<NUM>) exposed;
in a selective area growth phase (P2), selectively growing a semiconductor material (<NUM>) on the substrate in the one or more exposed regions, wherein the semiconductor material (<NUM>) in the one or more exposed regions forms a network of in-plane nanowires; and
in a superconductor growth phase (P3), forming a layer of superconducting material (<NUM>), at least part of which (<NUM>) is in direct contact with the selectively grown semiconductor material (<NUM>);
wherein the mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material (<NUM>) and the superconducting material in direct contact with the selectively grown semiconductor material (<NUM>).