Patent Description:
Mobile radio frequency (RF) chips (e.g., mobile RF transceivers) have migrated to a deep sub-micron process node due to cost and power consumption considerations. Designing mobile RF transceivers is further complicated by added circuit functions for supporting communication enhancements, such as fifth generation (<NUM>) communication systems. Further design challenges for mobile RF transceivers include using passive devices, which directly affect analog/RF performance considerations, including mismatch, noise, and other performance considerations.

Passive devices may involve high performance capacitor components. For example, analog integrated circuits use various types of passive devices, such as integrated capacitors. These integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, p-n junction capacitors, metal-insulator-metal (MIM) capacitors, poly-to-poly capacitors, metal-oxide-metal (MOM) capacitors, and other like capacitor structures. MOM capacitors are also known as vertical parallel plate (VPP) capacitors, natural vertical capacitors (NVCAP), lateral flux capacitors, comb capacitors, as well as interdigitated finger capacitors. MOM capacitors exhibit beneficial characteristics including high capacitance density, low parasitic capacitance, superior RF characteristics, and good matching characteristics without additional masks or process steps relative to other capacitor structures.

MOM capacitors are one of the most widely used capacitors due to their beneficial characteristics. MOM capacitor structures realize capacitance by using the fringing capacitance produced by sets of interdigitated fingers. That is, MOM capacitors harness lateral capacitive coupling between plates formed by metallization layers and wiring traces.

The design of mobile RF transceivers may include integrating MOM/MIM/MOS capacitors with inductors and/or transformers. Unfortunately, integrating MOM/MIM/MOS capacitors with inductors and/or transformers may degrade a performance of the inductors and/or transformers. Attention is drawn to <CIT> relating to Metal-oxide-metal (MOM) type capacitors including a first terminal configured to receive a first voltage, the first terminal being formed on a first dielectric layer; a first set of fingers formed on the first dielectric layer, the first set of fingers being coupled to the first terminal via a conductive trace formed on a second dielectric layer; a second terminal configured to receive second voltage, the second terminal being formed on the first dielectric layer; and a second set of fingers formed on the first dielectric layer, the second set of fingers being coupled to the second terminal, wherein the fingers of the second set are interspersed with the fingers of the first set. Further attention is drawn to <CIT> relating to Back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor. Attention is also drawn to <CIT> relating to an electric circuit including: an inductive element having wiring at least partially enclosing a certain region; a first capacitative element having a comb-shaped electrode extending in a direction substantially perpendicular to the wiring in one of an inner region and an outer region of the wiring; at least one of a second capacitative element having a comb-shaped electrode extending in the direction substantially perpendicular to the wiring in the other region of the inner region and the outer region of the wiring and a shield having a shield wire extending in the direction substantially perpendicular to the wiring. Further attention is drawn to JPH06333740A relating to a quartz substrate with a high heat resistance, for example, for a substrate, and a thin film integrated circuit having a silicon gate type TFT using a silicon material is provided as electric wiring on the substrate. A fetch electrode of this thin film integrated circuit is formed on the same substrate. A silicon oxide film as a protective film covering this thin film integrated circuit is formed, and a through hole is formed at the portion corresponding to the fetch electrode. A capacitor portion and an inductor are provided as a laminated construction on the protective film. Attention is further drawn to <CIT> relating to a capacitance circuit assembly mounted on a semiconductor chip, and method for forming the same, comprising a plurality of divergent capacitors in a parallel circuit connection between first and second ports, the plurality of divergent capacitors comprising at least one Metal Oxide Silicon Capacitor and at least one capacitor selected from the group comprising a Vertical Native Capacitor and a Metal-Insulator-Metal Capacitor. In one aspect, the assembly has vertical orientation, the Metal Oxide Silicon capacitor located at the bottom and defining the footprint, middle Vertical Native Capacitor comprising a plurality of horizontal metal layers comprising a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, a vertically asymmetric orientation provides a reduced total parasitic capacitance. Additional attention is drawn to <CIT> relating to an integrated circuit device including a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of a second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern and the second metal pattern. The third metal pattern is electrically grounding. An inductor is disposed over the third metal pattern. Attention is also drawn to <CIT> relating to integrated circuits including at least one inductor-capacitor component, where each of the inductor-capacitor components includes an inductor and a capacitor constructed between the inductor and a substrate. The inductor includes at least one metal loop over a shield pattern forming a first capacitor terminal over patterned oxide layer with a second capacitor layer between the patterned oxide layer and the substrate.

An integrated circuit (IC) includes a capacitor array in at least one first back-end-of-line (BEOL) interconnect level. The capacitor array includes a pair of capacitor manifolds coupled to parallel capacitor routing traces and capacitors coupled between each pair of parallel capacitor routing traces. The IC also includes an inductor trace having at least one turn in at least one second BEOL interconnect level. The inductor trace defines a perimeter to overlap at least a portion of the capacitor array.

A method for fabricating a radio frequency integrated circuit (RFIC) is described. The method includes fabricating a capacitor array in at least one first back-end-of-line (BEOL) interconnect level. The method also includes depositing parallel capacitor routing traces. Capacitors of the capacitor array are coupled between each pair of the parallel capacitor routing traces. The method further includes fabricating a pair of capacitor manifolds on a same side of the capacitor array. Each of the pair of capacitor manifolds is coupled to the parallel capacitor routing traces. The method also includes fabricating an inductor trace having at least one turn in at least one second BEOL interconnect level. The inductor trace defines a perimeter to overlap at least a portion of the capacitor array.

A radio frequency integrated circuit (RFIC) includes a capacitor array in at least one first back-end-of-line (BEOL) interconnect level. The capacitor array has a pair of capacitor manifolds on a same side of the capacitor array. Each of the pair of capacitor routing manifolds is coupled to means for routing capacitor fingers. Capacitors are coupled between the means for routing capacitor fingers. The RFIC also includes an inductor trace having at least one turn in at least one second BEOL interconnect level. The inductor trace defines a perimeter to overlap at least a portion of the capacitor array.

This has outlined, rather broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the present disclosure will be described below. It should be appreciated by those skilled in the art that this present disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the present disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

It will be apparent, however, to those skilled in the art that these concepts may be practiced without these specific details.

As described herein, the use of the term "and/or" is intended to represent an "inclusive OR", and the use of the term "or" is intended to represent an "exclusive OR". As described herein, the term "exemplary" used throughout this description means "serving as an example, instance, or illustration," and should not necessarily be construed as preferred or advantageous over other exemplary configurations. As described herein, the term "coupled" used throughout this description means "connected, whether directly or indirectly through intervening connections (e.g., a switch), electrical, mechanical, or otherwise," and is not necessarily limited to physical connections. Additionally, the connections can be such that the objects are permanently connected or releasably connected. The connections can be through switches. As described herein, the term "proximate" used throughout this description means "adjacent, very near, next to, or close to. " As described herein, the term "on" used throughout this description means "directly on" in some configurations, and "indirectly on" in other configurations.

Mobile radio frequency (RF) chips (e.g., mobile RF transceivers) have migrated to a deep sub-micron process node due to cost and power consumption considerations. Designing mobile RF transceivers is complicated by added circuit functions for supporting communication enhancements, such as fifth generation (<NUM>) communication systems. Further design challenges for mobile RF transceivers include using passive devices, which directly affect analog/RF performance considerations, including mismatch, noise, and other performance considerations.

Passive devices in mobile RF transceivers may include high performance capacitor components. For example, analog integrated circuits use various types of passive devices, such as integrated capacitors. These integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, p-n junction capacitors, metal-insulator-metal (MIM) capacitors, poly-to-poly capacitors, metal-oxide-metal (MOM) capacitors, and other like capacitor structures. Capacitors are generally passive elements used in integrated circuits for storing an electrical charge. For example, parallel plate capacitors are often made using plates or structures that are conductive with an insulating material between the plates. The amount of storage, or capacitance, for a given capacitor is contingent upon the materials used to make the plates and the insulator, the area of the plates, and the spacing between the plates. The insulating material is often a dielectric material.

These parallel plate capacitors consume a large area on a semiconductor chip because many designs place the capacitor over the substrate of the chip. Unfortunately, this approach reduces the available area for active devices. Another approach is to create a vertical structure, which may be known as a vertical parallel plate (VPP) capacitor. VPP capacitor structures may be created through stacking of the interconnect layers on a chip.

VPP capacitors structures, however, have lower capacitive storage, or lower "density," in that these structures do not store much electrical charge. In particular, the interconnect and via layer interconnect traces used to fabricate VPP capacitors may be very small in size. The spacing between the interconnects and via layer conductive traces in VPP structures is limited by design rules, which often results in a large area for achieving certain desired capacitance for such structures. Although described as "vertical," these structures can be in any direction that is substantially perpendicular to the surface of the substrate, or at other angles that are not substantially parallel to the substrate.

A MOM capacitor as well as a MOS capacitor are examples of VPP capacitors. MOM capacitors are one of the most widely used capacitors due to their beneficial characteristics. In particular, MOM capacitors are typically used for providing high quality capacitors in semiconductor processes without incurring the cost of an extra processing step relative to other capacitor structures. MOM capacitor structures realize capacitance by using the fringing capacitance produced by sets of interdigitated fingers. That is, MOM capacitors harness lateral capacitive coupling between plates formed by metallization layers and wiring traces.

The design of mobile RF transceivers may include integrating MOM/MOS/MIM capacitors with inductors and/or transformers. Unfortunately, integrating MOM/MOS/MIM capacitors with inductors and/or transformers may degrade performance of the inductors and/or transformers. Consequently, conventional arrangements for implementing multi-turn inductors continue to consume unused area in RF integrated circuit (RFIC) analog devices.

Various aspects of the disclosure provide a capacitor array integrated within an inductor area, which is conventionally unused. The process flow for fabrication of the capacitor array and inductor may include front-end-of-line (FEOL) processes, middle-of-line (MOL) processes, and back-end-of-line (BEOL) processes. It will be understood that the term "layer" includes film and is not to be construed as indicating a vertical or horizontal thickness unless otherwise stated. As described, the term "substrate" may refer to a substrate of a diced wafer or may refer to a substrate of a wafer that is not diced. Similarly, the terms chip and die may be used interchangeably.

As described, the back-end-of-line interconnect layers may refer to the conductive interconnect layers (e.g., a first interconnect layer (M1) or metal one M1, metal two (M2), metal three (M3), metal four (M4), etc.) for electrically coupling to front-end-of-line active devices of an integrated circuit. The various back-end-of-line interconnect layers are formed at corresponding back-end-of-line interconnect levels, in which lower back-end-of-line interconnect levels use thinner metals layers relative to upper back-end-of-line interconnect levels. The back-end-of-line interconnect layers may electrically couple to middle-of-line interconnect layers, for example, to connect M1 to an oxide diffusion (OD) layer of an integrated circuit. The middle-of-line interconnect layer may include a zero interconnect layer (M0) for connecting M1 to an active device layer of an integrated circuit. A back-end-of-line first via (V2) may connect M2 to M3 or others of the back-end-of-line interconnect layers.

In practice, inductors/transformers are commonly used in radio frequency integrated circuits (RFICs). These inductors/transformers are generally formed at the upper back-end-of-line (BEOL) interconnect levels because the upper BEOL interconnect levels provide thicker metal layers relative to the lower BEOL interconnect levels for achieving a desired inductance. These inductors/transformers, however, occupy significant semiconductor area due to the thick metal layers provided by the upper BEOL interconnect levels. Unfortunately, adding circuits/capacitors below these inductors/capacitors normally decreases an inductor quality (Q)-factor.

Aspects of the present disclosure describe a capacitor array for reusing an area below the inductors/transformers, while maintaining an inductor Q-factor. For example, the inductor may be fabricated at an upper BEOL interconnect level (e.g., M5). Conventionally, the area in a lower BEOL interconnect level (e.g., M1-M4) is unused because occupying this area generally degrades the inductor's Q-factor.

According to aspects of the present disclosure, a capacitor array may be formed in the lower BEOL interconnect levels, without degrading the inductor's Q-factor. In this way, a perimeter defined by a trace of the inductor may overlap and possibly enclose the capacitor array. In addition, a pair of manifolds (e.g., capacitor routing terminals) of the capacitor array may be proximate one another, and outside of the capacitor array and the perimeter defined by the inductor trace.

<FIG> is a schematic diagram of a radio frequency (RF) front end (RFFE) module <NUM> employing passive devices including a capacitor <NUM> (e.g., a capacitor array) integrated within an inductor area of an inductor <NUM>. The RF front end module <NUM> includes power amplifiers <NUM>, duplexer/filters <NUM>, and a radio frequency (RF) switch module <NUM>. The power amplifiers <NUM> amplify signal(s) to a certain power level for transmission. The duplexer/filters <NUM> filter the input/output signals according to a variety of different parameters, including frequency, insertion loss, rejection, or other like parameters. In addition, the RF switch module <NUM> may select certain portions of the input signals to pass on to the rest of the RF front end module <NUM>.

The radio frequency (RF) front end module <NUM> also includes tuner circuitry <NUM> (e.g., first tuner circuitry 112A and second tuner circuitry 112B), the diplexer <NUM>, a capacitor <NUM>, an inductor <NUM>, a ground terminal <NUM>, and an antenna <NUM>. The tuner circuitry <NUM> (e.g., the first tuner circuitry 112A and the second tuner circuitry 112B) includes components such as a tuner, a portable data entry terminal (PDET), and a house keeping analog to digital converter (HKADC). The tuner circuitry <NUM> may perform impedance tuning (e.g., a voltage standing wave ratio (VSWR) optimization) for the antenna <NUM>. The RF front end module <NUM> also includes a passive combiner <NUM> coupled to a wireless transceiver (WTR) <NUM>. The passive combiner <NUM> combines the detected power from the first tuner circuitry 112A and the second tuner circuitry 112B. The wireless transceiver <NUM> processes the information from the passive combiner <NUM> and provides this information to a modem <NUM> (e.g., a mobile station modem (MSM)). The modem <NUM> provides a digital signal to an application processor (AP) <NUM>.

As shown in <FIG>, the diplexer <NUM> is between the tuner component of the tuner circuitry <NUM> and the capacitor <NUM>, the inductor <NUM>, and the antenna <NUM>. The diplexer <NUM> may be placed between the antenna <NUM> and the tuner circuitry <NUM> to provide high system performance from the RF front end module <NUM> to a chipset including the wireless transceiver <NUM>, the modem <NUM>, and the application processor <NUM>. The diplexer <NUM> also performs frequency domain multiplexing on both high band frequencies and low band frequencies. After the diplexer <NUM> performs its frequency multiplexing functions on the input signals, the output of the diplexer <NUM> is fed to an optional LC (inductor/capacitor) network including the capacitor <NUM> and the inductor <NUM>. The LC network may provide extra impedance matching components for the antenna <NUM>, when desired. Then, a signal with the particular frequency is transmitted or received by the antenna <NUM>. Although a single capacitor and inductor are shown, multiple components are also contemplated.

<FIG> is a schematic diagram of a wireless local area network (WLAN) (e.g., WiFi) module <NUM> including a first diplexer <NUM>-<NUM> and an RF front end (RFFE) module <NUM> including a second diplexer <NUM>-<NUM> for a chipset <NUM>, including a capacitor array integrated within an inductor area. The WiFi module <NUM> includes the first diplexer <NUM>-<NUM> communicably coupling an antenna <NUM> to a wireless local area network module (e.g., WLAN module <NUM>). The RF front end module <NUM> includes the second diplexer <NUM>-<NUM> communicably coupling an antenna <NUM> to the wireless transceiver (WTR) <NUM> through a duplexer <NUM>. The wireless transceiver <NUM> and the WLAN module <NUM> of the WiFi module <NUM> are coupled to a modem (MSM, e.g., baseband modem) <NUM> that is powered by a power supply <NUM> through a power management integrated circuit (PMIC) <NUM>. The chipset <NUM> also includes capacitors <NUM> and <NUM>, as well as an inductor(s) <NUM> to provide signal integrity.

The PMIC <NUM>, the modem <NUM>, the wireless transceiver <NUM>, and the WLAN module <NUM> each include capacitors (e.g., <NUM>, <NUM>, <NUM>, and <NUM>) and operate according to a clock <NUM>. In addition, the inductor <NUM> couples the modem <NUM> to the PMIC <NUM>. The geometry and arrangement of the various capacitors and inductors in the chipset <NUM> may consume substantial chip area. The design of the chipset <NUM> likely includes integrating MOM/MIM/MOS capacitors with inductors and/or transformers. Unfortunately, integrating MOM/MIM/MOS capacitors with inductors and/or transformers may degrade performance of the inductors and/or transformers. Consequently, conventional arrangements for implementing multi-turn inductors continue to consume unused area in RF integrated circuit (RFIC) analog devices.

Capacitors are widely used in analog integrated circuits. <FIG> is a block diagram illustrating a cross section of an analog integrated circuit (IC) device <NUM> including an interconnect stack <NUM>. The interconnect stack <NUM> of the IC device <NUM> includes multiple conductive interconnect layers (M1,. , M9, M10) on a semiconductor substrate (e.g., a diced silicon wafer) <NUM>. The semiconductor substrate <NUM> support a metal-oxide-metal (MOM) capacitor <NUM> and/or a metal-oxide-semiconductor (MOS). In this example, the MOM capacitor <NUM> is formed in the M3 and M4 interconnect layers, below the M5 and M6 interconnect layers. The MOM capacitor <NUM> is formed from lateral conductive fingers of different polarities using the conductive interconnect layers (M3 and M4) of the interconnect stack <NUM>. A dielectric (not shown) is provided between the conductive fingers.

In this example, the MOM capacitor <NUM> is formed within the lower conductive interconnect layers (e.g., M1 - M4) of the interconnect stack <NUM>. The lower conductive interconnect layers of the interconnect stack <NUM> have smaller interconnect widths and spaces. For example, the dimensions of the conductive interconnect layers M3 and M4 are half the size of the dimensions of the conductive interconnect layers M5 and M6. Likewise, the dimensions of the conductive interconnect layers M1 and M2 are half the size of the dimensions of the conductive interconnect layers M3 and M4. The small interconnect widths and spaces of the lower conductive interconnect layers enable the formation of MOM capacitors with increased capacitance density.

As shown in <FIG>, the MOM capacitor <NUM> makes use of a lateral (intra layer) capacitive coupling <NUM> between fingers (e.g., <NUM>, <NUM>) formed by standard metallization of the conductive interconnects (e.g., wiring lines and vias). In aspects of the present disclosure, one or more of the MOM/MIM/MOS capacitor arrays are integrated within an inductor area, as shown in <FIG>.

<FIG> is a schematic diagram illustrating a top view of an on-chip inductor/transformer that overlaps a capacitor array, according to aspects of the present disclosure. Representatively, a radio frequency integrated circuit (RFIC) <NUM> includes an on-chip inductor/transformer that is shown as a one-turn inductor trace (e.g., inductor trace <NUM>) formed in an upper back-end-of-line (BEOL) interconnect level (e.g., M5-M8). The upper BEOL interconnect level may begin at a fifth BEOL interconnect level (M5). In this example, a capacitor array <NUM> is fabricated in lower BEOL interconnect levels (e.g., M1-M4). Although the upper and lower BEOL interconnect levels are described with reference to particular BEOL interconnect levels, it should be understood that other ranges are contemplated according to aspects of the present disclosure.

In this aspect of the present disclosure, the capacitor array <NUM> includes capacitors <NUM> fabricated within an inductor area defined by a perimeter of the inductor trace <NUM>. The capacitors <NUM> of the capacitor array <NUM> are coupled between positive (e.g., <NUM>, <NUM>, <NUM>) and negative (e.g., <NUM>, <NUM>, <NUM>) parallel capacitor routing traces. For example, each pair of parallel capacitor routing traces includes capacitors <NUM> coupled there between. It should be recognized that number of the positive (e.g., <NUM>, <NUM>, <NUM>) and negative (e.g., <NUM>, <NUM>, <NUM>) parallel capacitor routing traces shown is merely exemplary, as more or fewer parallel capacitor routing traces are contemplated according to aspects of the present disclosure.

In this aspect of the present disclosure, a positive capacitor manifold <NUM> is coupled to the positive parallel capacitor routing traces (e.g., <NUM>, <NUM>, <NUM>). In addition, a negative capacitor manifold <NUM> is coupled to the negative parallel capacitor routing traces (e.g., <NUM>, <NUM>, <NUM>). In this example, the positive capacitor manifold <NUM> is placed proximate to the negative capacitor manifold <NUM>, and both manifolds are outside the perimeter of the inductor trace <NUM>. This arrangement of the capacitor manifolds (e.g., <NUM>, <NUM>) prevents the capacitor array <NUM> from negatively affecting the Q-factor of the inductor trace <NUM> by avoiding forming of a loop current within the capacitor array <NUM> when the negative capacitor manifold <NUM> and the positive capacitor manifold <NUM> are placed on opposite sides of the capacitor array <NUM>. The capacitor manifolds (e.g., <NUM>, <NUM>) can also be within the perimeter of the inductor traces <NUM> in same configurations. Although the inductor trace <NUM> is shown as having one turn in <FIG>, it should be recognized that aspects of the present disclosure contemplate multi-turn inductors.

Although shown as perpendicular and/or parallel relative to the inductor trace <NUM>, the positive and negative parallel capacitor routing traces (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) may be placed at any angle relative to the inductor trace <NUM>. As shown in <FIG>, the positive and negative parallel capacitor routing traces (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) are parallel at some location and perpendicular at some other locations relative to the inductor trace <NUM>. In addition, although the positive and negative parallel capacitor routing traces (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) are shown perpendicular to the positive and negative capacitor manifolds (e.g., <NUM> and <NUM>), it should be recognized that an angle between the routing traces and the manifolds may include angles other than ninety degrees (<NUM>°).

<FIG> are schematic diagrams further illustrating the on-chip inductor/transformer that overlaps a capacitor array of <FIG>, according to aspects of the present disclosure.

<FIG> is a top view of the on-chip inductor/transformer/capacitor array of <FIG>, in which the inductor trace is not shown to further illustrate the MOM/MIM/MOS capacitors, according to aspects of the present disclosure. In this configuration, a capacitor array <NUM> includes capacitors <NUM> coupled between positive (e.g., <NUM>, <NUM>, <NUM>) and negative (e.g., <NUM>, <NUM>, <NUM>) parallel capacitor routing traces. For example, each pair of parallel capacitor routing traces includes capacitors <NUM> coupled there between. It should be recognized that number of the positive (e.g., <NUM>, <NUM>, <NUM>) and negative (e.g., <NUM>, <NUM>, <NUM>) parallel capacitor routing traces shown is merely exemplary, as more or fewer parallel capacitor routing traces are contemplated according to aspects of the present disclosure.

In this example, a positive capacitor manifold <NUM> is coupled to the positive parallel capacitor routing traces (e.g., <NUM>, <NUM>, <NUM>). A negative capacitor manifold <NUM> is also coupled to the negative parallel capacitor routing traces (e.g., <NUM>, <NUM>, <NUM>). In this example, the positive capacitor manifold <NUM> and the negative capacitor manifold <NUM> may be arranged as shown in <FIG> (e.g., proximate one another and outside the perimeter of the capacitor array <NUM>). In the configuration shown in <FIG>, capacitor fingers <NUM>/<NUM> are coupled to the positive (e.g., <NUM>, <NUM>, <NUM>) and negative (e.g., <NUM>, <NUM>, <NUM>) parallel capacitor routing traces, respectively. The various capacitors formed in the capacitor array <NUM> are illustrated in <FIG>, as cross-section views along a line A-A'.

<FIG> is a cross-section view along the line A-A' of the capacitor array <NUM> illustrating a first capacitor type, according to aspects of the present disclosure. In this example, the capacitor array <NUM> includes a metal oxide metal (MOM) capacitor <NUM>. The MOM capacitor <NUM> is formed from multiple layers of the capacitor fingers <NUM>/<NUM>. For example, positive capacitor fingers <NUM> (<NUM>-<NUM>,. , <NUM>-N) are coupled together over a substrate <NUM> (e.g., a semiconductor substrate). In addition, negative capacitor fingers <NUM> (<NUM>-<NUM>,. , <NUM>-N) are coupled together over the substrate <NUM>. A dielectric layer (not shown) may be deposited between the capacitor fingers <NUM>/<NUM> to complete formation of the MOM capacitor <NUM>, for example, within a first interconnect layer M1 and a fourth interconnect layer M4.

<FIG> is a cross-section view along the line A-A' of the capacitor array <NUM> of <FIG>, illustrating a second capacitor type, according to aspects of the present disclosure. In this example, the capacitor array <NUM> includes the MOM capacitor <NUM> stacked on a metal oxide semiconductor (MOS) capacitor <NUM> to from a MOM on MOS capacitor <NUM>. The MOS capacitor <NUM> is formed from source (S)/drain (D) contacts as well as a gate (G) contact. In this example, the positive capacitor fingers <NUM> and the negative capacitor fingers <NUM> are interconnected with the S/D contacts and the gate (G) contact for completing the MOM on MOS capacitor <NUM>.

<FIG> is a cross-section view along the line A-A' of the capacitor array <NUM> of <FIG>, illustrating a third capacitor type, according to aspects of the present disclosure. In this example, the capacitor array <NUM> includes the MOS capacitor <NUM>. The MOS capacitor <NUM> is formed to include source (S)/drain (D) contacts as well as a gate (G) contact. In this example, the positive capacitor fingers <NUM> and the negative capacitor fingers <NUM> are interconnected with the S/D contacts and the G contact to complete formation of the MOS capacitor <NUM>.

<FIG> are schematic diagrams further illustrating the on-chip inductor/transformer/capacitor array of <FIG>, according to aspects of the present disclosure.

<FIG> is a top view of the on-chip inductor/transformer that overlaps a capacitor array of <FIG>, in which the inductor trace is not shown to further illustrate the MOM/MIM/MOS capacitors, according to aspects of the present disclosure. In this configuration, the capacitor fingers <NUM>/<NUM> are coupled to the positive (e.g., <NUM>, <NUM>, <NUM>) and negative (e.g., <NUM>, <NUM>, <NUM>) parallel capacitor routing traces, respectively. The various capacitors that may be formed in a capacitor array <NUM> are illustrated in <FIG>, as cross-section views along a line A-A' of the capacitor array <NUM>.

<FIG> is a cross-section view along the line A-A' of the capacitor array <NUM> of <FIG>, illustrating a fourth capacitor type, according to aspects of the present disclosure. In this example, the capacitor array <NUM> includes a metal-insulator-metal (MIM) capacitor <NUM>. The MIM capacitor <NUM> is formed from multiple layers of the capacitor fingers <NUM>/<NUM>, which may a first capacitor plate and a second capacitor plate of the MIM capacitor <NUM>. For example, the positive capacitor fingers <NUM> (<NUM>-<NUM>,. , <NUM>-N) and the negative capacitor fingers <NUM> (<NUM>-<NUM>,. , <NUM>-N) may be stacked over the substrate <NUM> (e.g., a semiconductor substrate) to form the MIM capacitor <NUM>. In addition, a dielectric layer (not shown) may be deposited between the capacitor fingers <NUM>/<NUM> to complete formation of the MIM capacitor <NUM>.

<FIG> is a cross-section view along the line A-A' of the capacitor array <NUM> of <FIG>, illustrating a fifth capacitor type, according to aspects of the present disclosure. In this example, the capacitor array <NUM> includes the MIM capacitor <NUM> stacked on a MOS capacitor <NUM> to from a MIM on MOS capacitor <NUM>. In this configuration, the MOS capacitor <NUM> is formed to include a drain (D) contact and a gate (G) contact. In this example, the positive capacitor fingers <NUM> and the negative capacitor fingers <NUM> are interconnected with the D contact and the G contact for completing the MIM on MOS capacitor <NUM>.

In this aspect of the present disclosure, an inductor trace <NUM> (<FIG>) defines a perimeter of an inductor area that overlaps at least a capacitor array (e.g., <NUM>/<NUM>/<NUM>) for maintaining the Q-factor of the inductor trace <NUM>, which may be fabricated as shown in <FIG>.

<FIG> is a process flow diagram illustrating a method <NUM> for fabricating a radio frequency integrated circuit (RFIC), according to an aspect of the present disclosure. In block <NUM>, a capacitor array is fabricated in at least one first back-end-of-line (BEOL) interconnect level. For example, as shown in <FIG>, the capacitor array <NUM>, including capacitors <NUM>, is fabricated in lower interconnect levels (e.g., M1-M4). In block <NUM>, parallel capacitor routing traces are deposited. Capacitors of the capacitor array are coupled between each pair of the parallel capacitor routing traces. For example, as shown in <FIG>, the capacitors <NUM> are coupled between the positive (e.g., <NUM>, <NUM>, <NUM>) and the negative (e.g., <NUM>, <NUM>, <NUM>) parallel capacitor routing traces.

In block <NUM>, a pair of capacitor manifolds are fabricated on a same side of the capacitor array. Each of the pair of capacitor manifolds is coupled to the parallel capacitor routing traces. As shown in <FIG>, a positive capacitor manifold <NUM> is coupled to the positive parallel capacitor routing traces (e.g., <NUM>, <NUM>, <NUM>). In addition, the negative capacitor manifold <NUM> is coupled to the negative parallel capacitor routing traces (e.g., <NUM>, <NUM>, <NUM>). In this example, the positive capacitor manifold <NUM> is proximate to the negative capacitor manifold <NUM>, and both manifolds are outside the perimeter of the inductor trace <NUM>. In alternate configurations (not shown), the positive and negative capacitor manifolds are inside the perimeter of the inductor trace or on a different side (e.g., the left side of the top view diagram rather than the top side as seen in the top view diagram of <FIG>. ) In block <NUM>, an inductor trace is fabricated with at least one turn in at least one second BEOL interconnect level. The inductor trace defines a perimeter overlapping at least a portion of the capacitor array. As shown in <FIG>, the inductor trace <NUM> is fabricated in upper BEOL interconnect levels (e.g., M5-M8) and defines a perimeter of an inductor area that overlaps at least the capacitor array <NUM>.

According to a further aspect of the present disclosure, an RFIC includes a capacitor array within an inductor area defined by a perimeter of an inductor trance. In one configuration, the RFIC has means for routing capacitor fingers. In one configuration, the capacitor finger routing means may be the positive (e.g., <NUM>, <NUM>, <NUM>) parallel capacitor routing traces and the negative (e.g., <NUM>, <NUM>, <NUM>) parallel capacitor routing traces, as shown in <FIG>. In another aspect, the aforementioned means may be any structure or any material configured to perform the functions recited by the aforementioned means.

<FIG> is a block diagram showing an exemplary wireless communication system <NUM> in which an aspect of the disclosure may be advantageously employed. For purposes of illustration, <FIG> shows three remote units <NUM>, <NUM>, and <NUM> and two base stations <NUM>. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units <NUM>, <NUM>, and <NUM> include IC devices 825A, 825C, and 825B that include the disclosed inductor/transformer/capacitor array. It will be recognized that other devices may also include the disclosed inductor/transformer/capacitor array, such as the base stations, switching devices, and network equipment. <FIG> shows forward link signals <NUM> from the base station <NUM> to the remote units <NUM>, <NUM>, and <NUM> and reverse link signals <NUM> from the remote units <NUM>, <NUM>, and <NUM> to base stations <NUM>.

In <FIG>, remote unit <NUM> is shown as a mobile telephone, remote unit <NUM> is shown as a portable computer, and remote unit <NUM> is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit, such as a personal data assistant, a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit, such as a meter reading equipment, or other device that stores or retrieves data or computer instructions, or combinations thereof. Although <FIG> illustrates remote units according to the aspects of the disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the disclosure may be suitably employed in many devices, which include the disclosed inductor/transformer/capacitor array.

<FIG> is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the capacitors disclosed above. A design workstation <NUM> includes a hard disk <NUM> containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation <NUM> also includes a display <NUM> to facilitate design of a circuit <NUM> or an RF component <NUM> such as a inductor/transformer/capacitor array. A storage medium <NUM> is provided for tangibly storing the design of the circuit <NUM> or the RF component <NUM> (e.g., the inductor/transformer/capacitor array). The design of the circuit <NUM> or the RF component <NUM> may be stored on the storage medium <NUM> in a file format such as GDSII or GERBER. The storage medium <NUM> may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation <NUM> includes a drive apparatus <NUM> for accepting input from or writing output to the storage medium <NUM>.

Data recorded on the storage medium <NUM> may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium <NUM> facilitates the design of the circuit <NUM> or the RF component <NUM> by decreasing the number of processes for designing semiconductor wafers.

For a firmware and/or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. A machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein. For example, software codes may be stored in a memory and executed by a processor unit. Memory may be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" refers to types of long term, short term, volatile, nonvolatile, or other memory and is not to be limited to a particular type of memory or number of memories, or type of media upon which memory is stored.

If implemented in firmware and/or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be an available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

In addition to storage on computer readable medium, instructions and/or data may be provided as signals on transmission media included in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the technology of the disclosure as defined by the appended claims. For example, relational terms, such as "above" and "below" are used with respect to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. Additionally, if oriented sideways, above and below may refer to sides of a substrate or electronic device. Moreover, the scope of the present application is not intended to be limited to the particular configurations of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding configurations described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Claim 1:
An integrated circuit, IC, comprising:
a semiconductor substrate (<NUM>, <NUM>);
a capacitor array (<NUM>, <NUM>, <NUM>) in at least one first back-end-of-line, BEOL, interconnect level, the capacitor array having a pair of capacitor manifolds (<NUM>, <NUM>, <NUM>, <NUM>) coupled to a plurality of parallel capacitor routing traces (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), a plurality of capacitors (<NUM>, <NUM>, <NUM>) coupled between each pair of parallel capacitor routing traces, one of the plurality of capacitors stacked on a metal-oxide-semiconductor, MOS, capacitor (<NUM>, <NUM>) in direct contact with the semiconductor substrate; and
an inductor trace (<NUM>) having at least one turn in at least one second BEOL interconnect level, the inductor trace defining a perimeter to overlap at least a portion of the capacitor array.