Patent Description:
A non-volatile memory device is a semiconductor memory device capable of retaining stored data even when power supply is terminated. Examples of a non-volatile memory device include programmable read only memory (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), and flash memory device.

Recently, according to the technical demands for high integration and low power consumption characteristics and random access to memory cells, next generation semiconductor memory devices such as magnetic random access memory (MRAM) and phase-change random access memory (PRAM) have been developed.

Such next generation semiconductor devices may include variable resistance elements whose resistance values vary with an electric current or a voltage applied thereto. The variable resistance elements may have characteristics of maintaining the varied resistance values even when electric current or voltage supply is cut off. In order to obtain high integration and low power consumption, resistance variation characteristics of the variable resistance element may occur at a low application voltage and a range of resistance variation may be wide.

United States Patent Application Publication Number <CIT> discloses a vertical memory device including a variable resistance structure according to the preamble of independent claim <NUM>, further comprising quantum dots.

United States Patent Application Publication Number <CIT> presents a similar nonvolatile semiconductor memory device that prevents a leak current and may be operated at high speed.

Provided are variable resistance memory devices with improved variable resistance performance.

According to an aspect of the invention, there is provided a variable resistance memory device according to independent claim <NUM>. Further advantageous features are set out in the dependent claims.

Embodiments provide a vertical resistive switching device using a Hf-Al-O layer, for example.

According to one or more proposed concepts, a composition capable of forming the oxygen vacancies among variable resistance materials is presented.

The variable resistance material may have a large difference in resistance between the HRS and the LRS, because the more oxygen vacancy increases, the better filament formation by the oxygen vacancies. By way of example, in some embodiments, Hf-Al-O oxide, in which two metals having different valences, Hf and Al, may be mixed with each other, may be used as the variable resistance material to induce the formation of a large number of oxygen vacancy.

It is proposed to use a ternary oxide material including two metals having different valences as the variable resistance material (which can be confirmed by TEM).

According to an embodiment, there may be provided a vertical resistance-variable device using a ternary or higher oxide made of two or more metals with different valences as a variable resistance material. Each of the metal oxides may be a material with a band gap of <NUM> eV or more. A variable resistance material layer may be deposited next to a SiO<NUM> layer next to a silicon channel layer of the vertical resistance-variable device. A thickness of the variable resistance material may be <NUM> or less, and preferably <NUM> or less.

In some embodiments, the first conductive element and the second conductive element may contact the second layer.

In some embodiments, the metal oxide may be represented by (M1)x(M2)yOz, M1 and M2 may each be a metal element, a valance of M1 may be greater than that of M2, and x≥y may be satisfied.

In some embodiments, a thickness of the first layer may be less than or equal to <NUM>.

In some embodiments, the thickness of the first layer may be in a range of <NUM> to <NUM>.

In some embodiments, a thickness of the second layer may be less than or equal to <NUM>.

According to an embodiment, an electronic device includes any one of variable resistance memory devices described above.

For example, "at least one of A, B, and C," "at least one of A, B, or C," "one of A, B, C, or a combination thereof," and "one of A, B, C, and a combination thereof," respectively, may be construed as covering any one of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C.

When the terms "about" or "substantially" are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical value. Moreover, when the words "generally" and "substantially" are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as "about" or "substantially," it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical values or shapes.

The embodiments described below are merely examples, and various modifications may be possible from the embodiments. In the drawings, like reference numerals refer to like elements throughout, and sizes of elements may be exaggerated for clarity and convenience of explanation.

It will be understood that when an element or layer is referred to as being "above" or "on" another element or layer, the element or layer may be directly on another element or layer or intervening elements or layers.

It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these terms are only used to distinguish one element from another element. These terms are not intended to limit differences in materials or structures of elements.

It will be further understood that the terms "comprises" and/or "comprising" used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

The term used in the embodiments such as "unit" or "module" indicates a unit for processing at least one function or operation, and may be implemented in hardware or software, or in a combination of hardware and software.

The use of "the" and other demonstratives similar thereto may correspond to both a singular form and a plural form.

With respect to operations that constitute a method, the operations may be performed in any appropriate sequence unless the sequence of operations is clearly described or unless the context clearly indicates otherwise. Also, the use of any and all examples, or language provided herein, is intended merely to better illuminate the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed.

<FIG> is a cross-sectional view showing a schematic structure of a variable resistance memory device suitable for understanding the present invention, and <FIG> is a conceptual diagram describing a principle of resistance variation occurring in a variable resistance layer provided in a variable resistance memory device of <FIG>.

Referring to <FIG>, a variable resistance memory device <NUM> includes a variable resistance layer <NUM> including a first layer <NUM> and a second layer <NUM>, and a first conductive element E1 and a second conductive element E2 for applying a voltage to the variable resistance layer <NUM>.

The first conductive element E1 and the second conductive element E2 are disposed to contact the second layer <NUM> and are disposed to be spaced apart from each other on the variable resistance layer <NUM> to form a current path in a direction perpendicular to a direction in which the first layer <NUM> and the second layer <NUM> are stacked in the variable resistance layer <NUM>.

The first layer <NUM> includes a ternary or higher metal oxide of two or more metals having different valances. A metal of a metal oxide of the first layer <NUM> may be at least one of Rb, Ti, Ba, Zr, Ca, Hf, Sr, Sc, Mg Al, K, Y, La, Be, Nb, Ni, Ta, W, V, La, Gd, Cu, Mo, Cr, or Mn. The first layer <NUM> includes a ternary or higher metal oxide of at least two metals (M1 and M2) having different valences and the second layer <NUM> includes an oxide, such as silicon oxide (SiO<NUM>).

The second layer <NUM> includes an oxide. The second layer <NUM> may include a silicon oxide, but is not limited thereto. The second layer <NUM> may include an oxide of a material in contact with the second layer <NUM> in a device to which the variable resistance memory device <NUM> is applied.

The first conductive element E1 and the second conductive element E2 may be disposed on opposite ends of the variable resistance layer <NUM>, and may be disposed to form a current path in a horizontal direction, that is, a direction perpendicular to a direction in which the first layer <NUM> and the second layer <NUM> are stacked, in the variable resistance layer <NUM> when a voltage is applied. The first conductive element E1 and the second conductive element E2 may be formed to contact opposite ends of the second layer <NUM>.

The variable resistance layer <NUM> has a resistance characteristic that varies according to an applied voltage. The resistance characteristic of the variable resistance layer <NUM> may depend upon whether a conductive filament forms from oxygen generation in the variable resistance layer <NUM> in response a voltage applied to the first conductive element E1 and the second conductive element E2 formed on the variable resistance layer <NUM>. According to whether the conductive filament is formed, the variable resistance layer <NUM> may represent a low-resistive state or a high-resistive state, and accordingly, information of "<NUM>" or "<NUM>" may be written. An applied voltage that changes the variable resistance layer <NUM> from a high-resistive state to a low-resistive state is referred to as a set voltage (Vset), and an applied voltage that changes the variable resistance layer <NUM> from a low-resistive state to a high-resistive state is referred to as a reset voltage (Vreset). The variable resistance memory device <NUM> according to an embodiment suggests a configuration of the variable resistance layer <NUM> which implements a low set voltage and has a large difference between resistance of a high-resistive state and resistance of a low-resistive state.

A metal oxide including two metals having different valences may include a plurality of oxygen vacancies Vo. For example, as illustrated in <FIG>, when a metal oxide included in the first layer <NUM> is HfAlO formed of having a valence of <NUM> and AI having a valence of <NUM>, AI moves into a Hf site and an oxygen vacancy is formed at an interface between a HfAlO layer and a SiO<NUM> layer. Such atomic behavior may be represented as follows.

Al<NUM><NUM><NUM> + HfO<NUM> → 2AlHf* + Vo** + <NUM> Oox.

In the atomic behavior representation above, AlHF' refers to a structure in which some Al occupies a Hf site in HfO<NUM> in the structure of Al<NUM>O<NUM>. Vo** refers to a structure in which an O site is empty, and OOx refers to a structure in which O is positioned in an O site.

The oxygen vacancies Vo formed as above are gathered to form a conductive filament, and resistance of the variable resistance layer <NUM> is lowered by the conductive filament.

When a conductive filament is easily formed even at a low applied voltage and a difference between resistance of a low-resistive state and resistance of a high-resistive state generated by the applied voltage increases, the variable resistance performance may be excellent.

When the variable resistance layer <NUM> is configured as in the devices of the present application, such as in <FIG> and/or <FIG> and <FIG> discussed below, a desired range of resistance variation may be realized with a less thickness compared to a case of using a charge trapping-based variable resistance element or a variable resistance element using a phase change material. A thickness of the first layer <NUM> may be less than or equal to about <NUM> or may be less than or equal to about <NUM>. A thickness of the first layer <NUM> may be greater than or equal to about <NUM>. A thickness of the second layer <NUM> may be less than or equal to about <NUM>.

As metals (M1 and M2) forming the metal oxide of the first layer <NUM> a metal having a band gap energy of <NUM> eV or more of the oxide may be used. These metals and their valances are shown in Table <NUM>.

Referring to Table <NUM>, a metal oxide (M1-M2-O) including two metal materials having different valences may be formed. A combination as shown in Table <NUM> may be used.

A difference between a valance of M1 and a valence of M2 may be greater than or equal to <NUM>. Alternatively, a difference between a valence of M1 and a valence of M2 may be greater than or equal to <NUM>. The greater the difference in valences, the more oxygen vacancies there may be, and a combination that has a difference in valences greater than <NUM> may be set.

A content proportion of each of M1 and M2 in a metal compound, M1-M2-O, is not particularly limited. An appropriate content ratio at which oxygen vacancies are generated as many as possible may be set. An optimum content ratio may be determined according to valences of M1 and M2, and an optimum content ratio may be determined according to a type of atom. For example, a metal oxide may be represented by (M1)x(M2)yOz, and when M1 is a metal having a greater valance than that of M2, x≥y may be satisfied. When represented as x+y=<NUM>, x may be in a range of <NUM>≤x<<NUM> and y may be in a range of <NUM><y≤<NUM>. Alternatively, x may be in a range of <NUM>≤x<<NUM>, and y may be in a range of <NUM><y≤<NUM>. However, the disclosure is not limited thereto, and may be adjusted differently according to the type of a metal element.

Although ternary oxides including two metals are described above, a quaternary oxide including three metals having different valences may be employed in the variable resistance layer <NUM>. For example, in a combination of M1-M2-M3-O, M1, M2, and M3 are different metals, and at least two metals among M1, M2, and M3 may have different valences. In other words, at least two of M1, M2, and M3 have different valences, and not all of M1, M2, and M3 should have different valences. In some embodiments, the first layer <NUM> of the variable resistance layer <NUM> may include a quaternary oxide.

<FIG> are cross-sectional views showing schematic structures of samples manufactured to test variable resistance performance of various variable resistance materials, and <FIG> illustrate I-V curves for the samples of <FIG>, respectively.

As described in <FIG>, SiO<NUM>, N-type Si, SiO<NUM>, and N-type Si are sequentially deposited on Si wafer, and a cylindrical structure of N-Si/SiO<NUM>/N-Si is formed by using patterning and etching processes. A variable resistance material, e.g., HfO<NUM>, is deposited to a thickness of <NUM> on a side surface of a cylindrical element, and when voltage is applied between an upper electrode, e.g., N-Si, and a lower electrode, e.g., N-Si, an electric current flows from the upper N-Si to the lower N-Si along a HfO<NUM>/SiO<NUM> layer. In this case, Ti/Pt is deposited on the upper electrode, e.g., N-Si, to improve contact resistance between the upper electrode, N-Si, and a probe station terminal.

In <FIG>, Al<NUM>O<NUM> (<NUM>) is deposited as a variable resistance material on a surface of a cylindrical structure of N-Si/SiO<NUM>/N-Si, and when a voltage is applied between an upper electrode, e.g., N-Si, and a lower electrode, e.g., N-Si, an electric current flows from the upper N-Si to the lower N-Si along a Al<NUM>O<NUM>/SiO<NUM> layer.

In <FIG>, Hf-Al-O (<NUM>) is deposited as a variable resistance material on a surface of a cylindrical structure of N-Si/SiO<NUM>/N-Si, and when a voltage is applied between an upper electrode, e.g., N-Si, and a lower electrode, e.g., N-Si, an electric current flows from the upper N-Si to the lower N-Si along a HfAlO/SiO<NUM> layer.

<FIG> illustrates I-V curves for the samples of <FIG>, respectively.

When a voltage is changed from <NUM> V to <NUM> V (step ①), a resistance state of a variable resistance material is changed from a high-resistive state (HRS) to a low-resistive state (LRS), and a voltage is lowered from <NUM> V to <NUM> V again (step ②), and a voltage is changed from <NUM> V to -<NUM> V (step ③), the resistance state of the variable resistance material is changed from the LRS to the HRS. Then, a process of changing a voltage from -<NUM> V to <NUM> V (step ④) is performed, thereby ending one cycle.

In order to identify a resistance variation phenomenon, resistance of the variable resistance material is read at <NUM> V. In this case, it may be determined that a sample when a resistance value at <NUM> V in the first step (①) in the HRS and a resistance value at <NUM> V in the second step (②) differ by a factor of <NUM>,<NUM> may be used as a variable resistance device.

As a result of measuring <NUM> samples of each of <FIG> using HfO<NUM>, Al<NUM>O<NUM>, and HfAlO as variable resistance materials, respectively, a yield satisfying above requirements is <NUM>% for HfO2 and <NUM>% for Al2O3. Resistance values of HfAlO differ by a factor of <NUM>,<NUM> at a yield of <NUM>%.

In other words, compared to HfO<NUM> and Al<NUM>O<NUM> used as variable resistance materials in the related art, in a case of HfAlO used as a variable resistance material in the present embodiment, the yield is increased by about <NUM>% or more. The reason for the above case is that, since, unlike HfO<NUM> and Al<NUM>O<NUM>, which are metal oxides of only a single metal, HfAlO has two metals with different valences mixed with each other, an oxygen vacancy exists even before a voltage is applied. Such result is the same as a result that is predictable with a concept of border trap density.

<FIG> are cross-sectional views showing schematic configurations of samples manufactured to measure border trap density for the variable resistance materials of <FIG>, and <FIG> are graphs of voltage versus capacitance measured for the samples of <FIG>, respectively.

Border trap density (Qot) may be obtained by using the following formulae. <MAT>
<MAT>
<MAT>.

In the above formulae, Cox refers to oxide capacitance in accumulation, VFB refers to flat-band voltage, CFB refers to flat-band capacitance, q refers to basic quantity of electric charge, A refers to an area of an electrode, εSi refers to permittivity of silicon, LD refers to Debye length, and NA refers to doping concentration. Cox is extracted from a capacitance graph, and Cox is calculated from CFB. In the graph, an interval between two V values corresponding to the calculated CFB is ΔVFB. However, CFB displayed in the graph is illustratively expressed to explain ΔVFB, and is not an exact numerical value.

A result of calculating the border trap density from the measured capacitance graph is shown in the following table.

In Table <NUM>, yields at which high-resistive values/low-resistive values are greater than or equal to <NUM>,<NUM> according to I-V curves of <FIG> are shown, and SiO<NUM>/HfAlO has the highest yield and the highest border trap density among the three cases. Oxygen vacancies are formed more easily and much more in an oxide in which at least two metal materials having different valences are mixed.

<FIG> show computational simulation results for Vo formation energy, trap depth, and I-V curve for a variable resistance layer including various types of metal oxides.

<FIG> illustrates oxygen vacancy formation energy. In the graph, a comparative example is expressed as Ref, and refers to a case where a variable resistance layer is SiO<NUM>/HfO<NUM>, and the following representations of metal elements (M) indicate a case where a variable resistance layer is SiO<NUM>/HfMO. M includes B, Mg, Al, K, Ca, Sc, Sr, Y, Ba, and La.

As the oxygen vacancy formation energy (Vo formation energy) has a positively (+) high value, the state is unstable, and thus, it may be seen that it is difficult to form oxygen vacancies well or to maintain the formed oxygen vacancies well. Thus, it is expected that the higher the oxygen vacancy formation energy, the higher the set voltage Vset that allows a variable resistance layer to be changed from a high-resistive state to a low-resistive state. In contrast, as the oxygen vacancy formation energy is negatively (-) low, the state is stable, and oxygen vacancies may be well formed or the formed oxygen vacancies may be well maintained, and thus, it is expected that the set voltage Vset decreases.

As shown in the graph, an oxygen vacancy formation energy is lower in all cases where a ternary metal oxide is used for a variable resistance layer than in the case of the comparative example (Ref) in which HfO<NUM> is used, and thus, it may be confirmed that a ternary metal oxide may be usefully applied to reduce a set voltage.

<FIG> illustrates a trap depth. Also in the graph of <FIG>, the comparative example is expressed as Ref, and refers to a case where a variable resistance layer is SiO<NUM>/HfO<NUM>, and the following representations of metal elements (M) indicate a case where a variable resistance layer is SiO<NUM>/HfMO. M includes B, Mg, Al, K, Ca, Sc, Sr, Y, Ba, and La.

The trap depth is defined as ϕτ in the following formula.

Here, J refers to current density, q refers to unit quantity of electric charge, µ refers to mobility, E refers to electric field, Nc refers to state density in a conduction band, k refers to Boltzmann constant, T refers to absolute temperature, and ε refers to permittivity.

The trap depth denotes a difference between trap level and conduction band minimum in the band diagram. When the trap depth is small, electrons at the trap level may move well to the conduction band, and when moving to the conduction band, the electrons may freely move, and thus, the current density may be increased. The smaller the trap depth, the higher the probability that electrons may ascend to the conduction band. Meanwhile, the trap density described above is the number of traps per unit volume of a variable resistance material, and the higher the trap density, the greater the number of electrons that may ascend over the conduction band. Therefore, when the trap density is large and the trap depth is small, it is advantageous to improve the current density. In addition, it is expected that the smaller the trap depth, the greater the current ratio, ION/IOFF, corresponding to a ratio of a high resistance to a low resistance.

As shown in the graph, the trap depth is smaller in all cases where a ternary metal oxide is used for a variable resistance layer than in the case of the comparative example (Ref) in which HfO<NUM> is used, and thus, it may be confirmed that a ternary metal oxide may be usefully applied to increase an on-off current ratio.

<FIG> illustrates an I-V curve. Also in the graph of <FIG>, the comparative example is expressed as Ref, and refers to a case where a variable resistance layer is SiO<NUM>/HfO<NUM>, and the following representations of metal oxides (HfMO) indicate a case where a variable resistance layer is SiO<NUM>/HfMO. In order from top to bottom, M refers to Al, Ca, Sr, Mg, K, Sc, and Ba.

The shown I-V curve is an I-V curve after oxygen vacancies are formed in a variable resistance layer and corresponds to a case where a low-resistive state is reached. It may be seen that a graph representing high current represents a high on-off current ratio, and from the graph, it may be seen that an on-off current ratio is higher in all cases where a ternary metal oxide is used for a variable resistance layer than in the case of the comparative example (Ref) in which HfO<NUM> is used.

The energy required to form oxygen vacancies may be seen as oxygen vacancy formation energy, and when a voltage is applied to a variable resistance layer, atoms obtain energy, and oxygen vacancies may be formed. Thus, when the oxygen vacancy formation energy is low, oxygen vacancies may be formed even at a low voltage, thereby reducing a set voltage. Therefore, it is expected that a set voltage is lower in all cases where a ternary metal oxide is used for a variable resistance layer than in the case of the comparative example (Ref) in which HfO<NUM> is used.

As such, lowering the set voltage and increasing the on-off current ratio may contribute to low power consumption and improvement in integration density, and for this, a ternary metal oxide provided in a variable resistance layer may be selected for the variable resistance layer to have a low Vo formation energy and a low trap depth. For example, referring to <FIG>, a ternary metal oxide employed in a variable resistance layer may be selected so that the variable resistance layer is less than or equal to <NUM> eV or less than or equal to <NUM> eV.

Hereinafter, variable resistance memory devices of various configurations to which such variable resistance layer is applied will be described.

<FIG> is a cross-sectional view showing a schematic configuration of a variable resistance memory device according to an embodiment of the present invention, and <FIG> illustrates an equivalent circuit of the variable resistance memory device of <FIG>. <FIG> is a conceptual diagram describing an example of an operation of the variable resistance memory device of <FIG>.

Referring to <FIG>, a variable resistance memory device <NUM> includes an insulating layer <NUM> (also referred to as a substrate <NUM>), a variable resistance layer <NUM> disposed on the insulating layer <NUM>, a channel layer <NUM> disposed on the variable resistance layer <NUM>, a gate insulating layer <NUM> disposed on the channel layer <NUM>, and a plurality of gate electrodes <NUM> formed on the gate insulating layer <NUM>. An insulator <NUM> is provided in a space between the plurality of gate electrodes <NUM> to separate adjacent gate electrodes <NUM>. However, the variable resistance memory device <NUM> is merely an example, and the insulator <NUM> may be omitted.

Referring to <FIG>, the variable resistance layer <NUM> includes a first layer <NUM> including a first material and a second layer <NUM> disposed on the first layer <NUM>. The first layer <NUM> includes a ternary or higher metal oxide of at least two metal materials (M1 and M2) having different valences. The second layer <NUM> includes an oxide. Materials in the variable resistance layer <NUM> and characteristics of the variable resistance layer <NUM> are substantially the same as those described for the variable resistance layer <NUM> of <FIG>. In an oxide in which at least two metal materials having different valences are mixed, there are a plurality of oxygen vacancies Vo, and thus a conductive filament may be easily formed.

The channel layer <NUM> may include a semiconductor material. According to the present invention, second layer <NUM> is in contact with the channel layer <NUM>, and the second layer <NUM> is an oxide of a material of the channel layer <NUM>. For example, the channel layer <NUM> may include, for example, poly-Si, and the second layer <NUM> may include a silicon oxide (SiO<NUM>) which is a native oxide due to poly-Si. The material of the channel layer <NUM> is not limited to poly-Si, and for example, may include various semiconductor materials such as Ge, IGZO, or GaAs. A native oxide material included in the second layer <NUM> may vary according to the material of the channel layer <NUM>.

A source electrode S and a drain electrode D may be connected to opposite ends of the channel layer <NUM>. The source electrode S may be referred to as a source S and the drain electrode D may be referred to as a drain D.

The gate insulating layer <NUM> may include various kinds of insulating materials. For example, a silicon oxide, a silicon nitride, or a silicon oxynitride may be used for the gate insulating layer <NUM>.

A voltage for turning on/off the channel layer <NUM> may be selectively applied to each of the plurality of gate electrodes <NUM>.

The variable resistance memory device <NUM> has a structure in which a plurality of memory cells MC are arrayed, and each of the plurality of the memory cells MC may have a transistor and a variable resistor connected in parallel as shown in the equivalent circuit of <FIG>. Each variable resistance is set by a voltage applied to a gate electrode and a voltage between the source electrode S and the drain electrode D and is a value corresponding to information of <NUM> or <NUM>.

An operation of the variable resistance memory device <NUM> will be described with reference to <FIG>.

When a memory cell to be written is selected, a gate voltage value of the corresponding memory cell is adjusted so that a channel is not formed in the selected memory cell, that is, the channel is turned off, and gate voltage values of unselected memory cells are adjusted so that channels in the unselected memory cells are turned on.

<FIG> illustrates a case in which a gate voltage is applied to a gate electrode <NUM> in each memory cell so that a memory cell MC2 at a center is turned off (OFF) and two memory cells MC1 and MC3 at opposite sides of the memory cell MC2 are turned on (ON). When a voltage is applied between the source electrode S and the drain electrode D, a conductive path denoted by an arrow A is formed. Referring to <FIG> and Table <NUM> below, desired information of <NUM> or <NUM> may be written in the selected memory cell MC2 by setting the applied voltage as a value of Vset or Vreset. Writing a <NUM>, or changing the value in a selected memory cell from a <NUM> to a <NUM>, also may be called an erase operation.

Similarly, in a read operation, read may be performed on a selected memory cell. That is, a gate electrode applied to each gate electrode <NUM> is adjusted so that the channel of the selected memory cell MC2 is turned off and the channels of the unselected memory cells MC1 and MC3 are turned on, and then an electric current flowing in the corresponding memory cell MC2 due to an applied voltage (Vread) between the source electrode S and the drain electrode D is measured to identify a memory cell state (<NUM> or <NUM>).

<FIG> is a cross-sectional view showing a schematic structure of a variable resistance memory device according to another embodiment of the present invention, and <FIG> is a perspective view showing a schematic structure of a memory string provided in the variable resistance memory device of <FIG>. <FIG> is an equivalent circuit diagram of the variable resistance memory device of <FIG>.

A variable resistance memory device <NUM> of the present embodiment is a vertical NAND (VNAND) memory in which a plurality of memory cells MC including variable resistance material are arrayed in a vertical direction.

Referring to <FIG>, a detailed configuration of the variable resistance memory device <NUM> will be described below.

First, referring to <FIG>, a plurality of cell strings CS are formed on a substrate <NUM>.

The substrate <NUM> may include a silicon material doped with first type impurities. For example, the substrate <NUM> may include a silicon material doped with p-type impurities. For example, the substrate <NUM> may be a p-type well (for example, a pocket p-well). Hereinafter, it is assumed that the substrate <NUM> is p-type silicon. However, the substrate <NUM> is not limited to the p-type silicon.

A doping region <NUM> as a source region is provided in the substrate <NUM>. The doping region <NUM> may be of an n-type that is different from that of the substrate <NUM>. Hereinafter, it is assumed that the doping region <NUM> is of the n-type. However, the doping region <NUM> is not limited to the n-type. The doping region <NUM> may be connected to a common source line CSL. The doping region <NUM> may also be referred to as a source <NUM>.

As shown in the circuit diagram of <FIG>, there may be k*n cell strings CS that are arranged in a matrix form and may be each be referred to as CSij (<NUM> ≤i≤k, <NUM> ≤j≤n) according to a position thereof in each row and column. Each of the cell strings CSij is connected to a bit line BL, a string select line SSL, a word line WL, and the common source line CSL.

Each of the cell strings CSij includes memory cells MC and a string select transistor SST. The memory cells MC and the string select transistor SST in each of the cell strings CSij may be stacked in a height direction.

A plurality of rows of the cell strings CS are connected to different string select lines SSL1 to SSLk, respectively. For example, string select transistors SST in cell strings CS11 to CS1n are commonly connected to a string select line SSL1. String select transistors SST in cell strings CSk1 to CSkn are commonly connected to a string select line SSLk.

A plurality of columns of the cell strings CS are connected to different bit lines BL1 to BLn, respectively. For example, memory cells MC and string select transistors SST in cell strings CS11 to CSk1 may be commonly connected to a bit line BL1, and memory cells MC and string select transistors SST in cell strings CS1n to CSkn may be commonly connected to a bit line BLn.

The plurality of rows of the cell strings CS may be connected to different common source lines CSL1 to CSLk, respectively. For example, the string select transistors SST in the cell strings CS11 to CS1n may be commonly connected to a common source line CSL1, and the string select transistors SST in the cell strings CSk1 to CSkn may be commonly connected to a common source line CSLk.

Gate electrodes of memory cells MC positioned at the same height from the substrate <NUM> or the string select transistors SST may be commonly connected to one word line WL, and gate electrodes of memory cells MC positioned at different heights from the substrate <NUM> or the string select transistors SST may be connected to different word lines WL1 to WLm, respectively.

The circuit structure shown in <FIG> is merely an example. For example, the number of rows of the cell strings CS may be increased or decreased. As the number of the rows of the cell strings CS varies, the number of string select lines connected to the rows of the cell strings CS and the number of cell strings CS connected to one bit line may also vary. As the number of rows of the cell strings CS varies, the number of common source lines connected to the rows of the cell strings CS may also vary.

The number of columns of cell strings CS may be increased or decreased. As the number of columns of the cell strings CS varies, the number of bit lines connected to the columns of the cell strings CS and the number of cell strings CS connected to one string select line may also vary.

The height of the cell strings CS may be increased or decreased. For example, the number of memory cells MC stacked in each of the cell strings CS may be increased or decreased. As the number of memory cells MC stacked in each of the cell strings CS varies, the number of word lines WL may also vary. For example, the number of string select transistors provided to each of the cell strings CS may be increased. As the number of the string select transistors provided to each of the cell strings CS varies, the number of string select lines or common source lines may also vary. When the number of the string select transistors increases, the string select transistors may be stacked like the memory cells MC.

For example, write and read operations may be performed in units of rows of the cell strings CS. The cell strings CS may be selected by the common source line CSL in units of one row and may be selected by the string select lines SSL in units of one row. Also, the voltage may be applied to the common source lines CSL in units of at least two common source lines CSL. The voltage may be applied to the common source lines CSL in units of total common source lines CSL.

In a selected row of the cell strings CS, the write and read operations may be performed in units of pages. A page may denote one row of memory cells connected to one word line WL. In the selected row of the cell strings CS, the memory cells may be selected by word lines WL in units of pages.

As illustrated in <FIG>, a cell string CS includes a pillar PL having a cylindrical shape and a plurality of gate electrodes <NUM> and a plurality of insulators <NUM> which surround the pillar PL in a ring shape. Each of the plurality of insulators <NUM> separates between the plurality of gate electrodes <NUM>, and each of the plurality of the gate electrodes <NUM> and the plurality of insulators <NUM> may be alternately stacked in a vertical direction (Z direction). The pillar PL having a cylindrical shape includes an insulating layer <NUM> extending in the vertical direction and having a cylindrical shape, and a variable resistance layer <NUM>, a channel layer <NUM>, and a gate insulating layer <NUM> sequentially surrounding the insulating layer <NUM> in a cylindrical shell shape.

The gate electrode <NUM> may include a metal material or a silicon material doped at a high concentration. Each gate electrode <NUM> is connected to one of the word line WL and the string select line SSL.

The insulator <NUM> may include various insulating materials such as a silicon oxide or a silicon nitride.

The pillar PL may include a plurality of layers. An outermost layer of the pillar PL may be the gate insulating layer <NUM>. For example, the gate insulating layer <NUM> may include various insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The gate insulating layer <NUM> may be conformally deposited on the pillar PL.

The channel layer <NUM> may be conformally deposited along an inner surface of the gate insulating layer <NUM>. The channel layer <NUM> may include a semiconductor material doped with a first type dopant. The channel layer <NUM> may include a silicon material doped with the same type as that of the substrate <NUM>, and for example, when the substrate <NUM> includes a silicon material doped as p-type, the channel layer <NUM> may also include the silicon material doped as the p-type. Alternatively, the channel layer <NUM> may include a material such as Ge, IGZO, or GaAs.

The variable resistance layer <NUM> may be disposed along an inner surface of the channel layer <NUM>. The variable resistance layer <NUM> may be disposed to contact the channel layer <NUM> and may be conformally deposited on the channel layer <NUM>.

The variable resistance layer <NUM> changes to a high-resistive state or a low-resistive state according to a voltage applied thereto, and includes a first layer <NUM> and a second layer <NUM>, the first layer <NUM> including a metal oxide of at least two metals having different valences and the second layer <NUM> including a silicon oxide in case a channel layer of silicon is used.

Materials in the variable resistance layer <NUM> and characteristics of the variable resistance layer <NUM> are substantially the same as those described for the variable resistance layer <NUM>. A metal oxide having a ternary system or more complex multicomponent system including two or more metals (M1 and M2) having different valences are included in the first layer <NUM>. M1 and M2 may each form an oxide having a band gap energy of <NUM> eV or more, for example, Rb, Ti, Ba, Zr, Ca, Hf, Sr, Sc, Mg, Al, K, Y, La, Be, Nb, Ni, Ta, W, V, La, Gd, Cu, Mo, Cr, or Mn. A metal oxide (M1-M2-O) included in the first layer <NUM> may be Al-Ti-O, Hf-Al-O, Hf-Mg-O, Hf-K-O, Hf-Ca-O, Hf-Sc-O, Hf-Sr-O, Hf-Ba-O, Hf-Y-O, Hf-La-O, Al-Zr-O, Mg-Zr-O, Zr-Nb-O, Hf-Nb-O, or Hf-Ta-O.

The variable resistance memory device <NUM> includes the variable resistance layer <NUM>, in which oxygen vacancies are easily formed, thereby allowing a difference between a resistance value of a high-resistive state and a resistance value of a low-resistive state to be increased. Accordingly, the variable resistance memory device <NUM> may have characteristics of low set voltage and low reset voltage.

The insulating layer <NUM> may be deposited along an inner surface of the variable resistance layer <NUM>. The insulating layer <NUM> may fill the innermost space of the pillar PL.

The channel layer <NUM> and the variable resistance layer <NUM> may contact the doping region <NUM>, that is, a common source region.

A drain region <NUM> may be provided on the pillar PL of the cell string CS. The drain region <NUM> may include a silicon material doped with second type dopants. For example, the drain region <NUM> may include a silicon material doped as n-type. The drain region <NUM> may also be referred to as a drain structure <NUM>.

A bit line <NUM> may be provided on the drain region <NUM>. The drain region <NUM> and the bit line <NUM> may be connected to each other via contact plugs.

Each of the gate electrodes <NUM> and regions in the gate insulating layer <NUM>, the channel layer <NUM>, and the variable resistance layer <NUM>, the regions facing each of the gate electrodes <NUM> in a horizontal direction (X direction), configure the memory cell MC. That is, the memory cell MC has a circuit structure in which a transistor including the gate electrode <NUM>, the gate insulating layer <NUM>, and the channel layer <NUM> and a variable resistor provided by the variable resistance layer <NUM> are connected in parallel.

The above parallel connection structure is continuously arranged in the vertical direction (Z direction) to form the cell string CS. In addition, opposite ends of the cell string CS may be connected to the common source line CSL and the bit line BL, as shown in the circuit diagram of <FIG>. When the voltage is applied to the common source line CSL and the bit line BL, the programming, read, and erase operations may be performed on the plurality of memory cells MC.

For example, referring to <FIG> and Table <NUM> below, when a memory cell MC to be written is selected, a gate voltage value of the corresponding memory cell is adjusted through a selected word line so that a channel is not formed in the selected memory cell, that is, the channel is turned off, and gate voltage values of unselected memory cells are adjusted through unselected word lines so that channels in the unselected memory cells are turned on. Accordingly, a current path formed by the voltage applied to the common source line CSL and the bit line BL passes through the region of the variable resistance layer <NUM> in the selected memory cell MC. At this time, a low-resistive state or a high-resistive state may be obtained by setting the applied voltage as a Vset value or a Vreset value, and desired information of <NUM> or <NUM> may be written in the selected memory cell MC. Writing a <NUM>, or changing the value in a selected memory cell from a <NUM> to a <NUM>, also may be called an erase operation.

In a reading operation, reading of the selected memory cell may be performed similarly as above. That is, a gate voltage applied to each gate electrode <NUM> is adjusted so that the channel of the selected memory cell MC is turned off and the channels of the unselected memory cells MC are turned on, and then an electric current flowing in the corresponding memory cell MC due to an applied voltage (Vread) between the common source line CSL and the bit line BL is measured to identify a memory cell state (<NUM> or <NUM>).

As described above, the variable resistance memory device <NUM> according to embodiments configures the memory cells MC to include the variable resistance layer <NUM>, in which a conductive filament is easily formed due to oxygen vacancies, and forms a memory element by arranging the memory cells MC. Therefore, the variable resistance layer <NUM> may be relatively thinner than a memory element with a conventional structure, for example, a phase change material-based memory element or a charge trapping-based memory element, and the variable resistance memory device <NUM> may have a low operating voltage.

In the above VNAND structure, due to packaging limitation according to a height of the cell string CS, there is a limit to increase the number of the gate electrodes <NUM> included in the cell string CS. Furthermore, in a case of the charge trapping-based memory device, there is a limit to reduce a distance between adjacent gate electrodes <NUM> due to interference. For example, it is known that it is difficult to reduce a sum Ls of vertical lengths of the gate electrode <NUM> and the insulator <NUM> adjacent to each other in the vertical direction (Z direction) to be less than or equal to about <NUM>, and thus the memory capacity is limited.

In the variable resistance memory device <NUM> according to an embodiment, the sum Ls of the lengths of the gate electrode <NUM> and the insulator <NUM> adjacent to each other in the vertical direction (Z direction) may be reduced and/or minimized using the variable resistance layer <NUM>. In an embodiment, the length may be reduced to be less than or equal to about <NUM>, for example, about <NUM>, and in this case, the memory capacity may be doubled or more.

The variable resistance memory device <NUM> may address a scaling issue between memory cells in a next-generation VNAND, thereby increasing a density and implementing a low-power consumption.

The variable resistance memory devices <NUM>, <NUM>, and <NUM> according to embodiments of the disclosure may be employed as memory systems of various electronic devices. The variable resistance memory device <NUM> may be implemented as a chip-type memory block to be used as a neuromorphic computing platform or used to construct a neural network.

<FIG> is a block diagram of a memory system including the present memory devices.

Referring to <FIG>, a memory system <NUM> may include a memory controller <NUM> and a memory device <NUM>. The memory controller <NUM> performs a control operation on the memory device <NUM>. For example, the memory controller <NUM> provides, to the memory device <NUM>, an address ADD and a command CMD for performing programming (or write), read, and/or erase operations on the memory device <NUM>. In addition, data for a programing operation and read data may be transmitted between the memory controller <NUM> and the memory device <NUM>.

The memory device <NUM> may include a memory cell array <NUM> and a voltage generator <NUM>. The memory cell array <NUM> may include a plurality of memory cells arranged in regions where a plurality of word lines and a plurality of bit lines cross each other. The memory cell array <NUM> may include a variable resistance memory device based on the devices of <FIG>, <FIG>, and <FIG>.

The memory controller <NUM> may include a processing circuitry such as a hardware including a logic circuit; a hardware/software combination such as processor execution software; or a combination thereof. Examples of the processing circuitry may include a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, and an application-specific integrated circuit (ASIC), but is not limited thereto. The memory controller <NUM> may operate in response to a request from a host (not shown), and may be configured to be changed into a special purpose controller by accessing to the memory device <NUM> and controlling a control operation (for example, a write/read operation) discussed above. The memory controller <NUM> may generate an address ADD and a command CMD for performing a programming/read/erase operation on the memory cell array <NUM>. In addition, in response to a command from the memory controller <NUM>, the voltage generator <NUM> (for example, a power circuit) may generate a voltage control signal for controlling a voltage level of a word line for the sake of data programming or data read in the memory cell array <NUM>.

In addition, the memory controller <NUM> may perform a determination operation on the data read from the non-volatile memory device <NUM>. For example, the number of on-cells and/or the number of off-cells may be determined from data read from a memory cell. The memory device <NUM> may provide a pass/fail signal P/F to the memory controller <NUM> according to a result of reading the read data. The memory controller <NUM> may control write and read operations of the memory cell array <NUM> with reference to the pass/fail signal P/F.

<FIG> is a block diagram showing a neuromorphic apparatus and an external device connected thereto, including the present memory devices.

Referring to <FIG>, a neuromorphic apparatus <NUM> may include a processing circuitry <NUM> and/or a memory <NUM>. The neuromorphic apparatus <NUM> may include a variable resistance memory device based on the devices of <FIG>, <FIG>, and <FIG>.

The processing circuitry <NUM> may be configured to control a function for driving the neuromorphic apparatus <NUM>. For example, the processing circuitry <NUM> may be configured to control the neuromorphic apparatus <NUM> by executing a program stored in the memory <NUM>. In some examples embodiments, the processing circuitry <NUM> may include a hardware such as a logic circuit, a hardware/software combination such as a processor configured to execute software, or a combination thereof. For example, the processor may include a CPU, a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic apparatus <NUM>, an ALU, a digital signal processor, a microcomputer, a FPGA, a SoC, a programmable logic unit, a microprocessor, and an ASIC, but is not limited thereto. The processing circuitry <NUM> may read/write various data with respect to an external device <NUM>, and/or may be configured to execute the neuromorphic apparatus <NUM> using the read/written data. In some embodiments, the external device <NUM> may include an external memory and/or a sensor array, each having an image sensor (for example, a complementary metal-oxide-semiconductor (CMOS) image sensor circuit).

The neuromorphic apparatus <NUM> of <FIG> may be applied to a machine learning system. The machine learning system may use various artificial neural network organizing and processing models such as a convolutional neural network (CNN), a deconvolutional neural network, a recurrent neural network (RNN) including a long short-term memory (LSTM) unit and/or a gated recurrent unit (GRU), a stacked neural network (SNN), a state-space dynamic neural network (SSDNN), a deep faith network (DBN), a generative adversarial network, and/or a restricted Boltzmann machine (RBM).

Alternatively or additionally, the machine learning system may include other forms of machine learning models, for example, linear and/or logistic regression, statistical clustering, Bayesian classification, decision tree, dimensionality reduction such as principal component analysis, an expert system, and/or a combination thereof including ensembles such as random forests. These machine learning models may be used to provide various services and/or applications. For example, an image classification service, a user authentication service based on biometrics or biometric data, an advanced driver assistance system (ADAS), a voice assistant service, or an automatic speech recognition (ASR) service may be executed by an electronic device.

In the variable resistance memory device, a resistance variation may occur under a low applied voltage.

The variable resistance memory device may have a wide range of resistance variation.

The variable resistance memory device may easily implement low power consumption and high integration density.

Claim 1:
A variable resistance memory device (<NUM>; <NUM>; <NUM>) comprising:
a variable resistance layer (<NUM>; <NUM>; <NUM>) including a first layer (<NUM>; <NUM>; <NUM>) and a second layer (<NUM>; <NUM>; <NUM>) on the first layer, the first layer including a ternary or higher metal oxide of two or more metals having different valences, and the second layer including an oxide;
a first conductive element (E1;<NUM>) on the variable resistance layer;
a second conductive element (E2; <NUM>) on the variable resistance layer and spaced apart from the first conductive element,
the first conductive element and the second conductive element, in response to an applied voltage, being configured to form a current path in a direction (Z) perpendicular to a direction (X) in which the first layer and the second layer are stacked an insulating layer (<NUM>; <NUM>) supporting the variable resistance layer;
a channel layer (<NUM>; <NUM>) on the variable resistance layer;
a gate insulating layer (<NUM>; <NUM>) on the channel layer; and
a plurality of gate electrodes (<NUM>; <NUM>) and a plurality of insulators (<NUM>; <NUM>) which are alternately and repeatedly disposed on the gate insulating layer in a first direction (Z) parallel to the channel layer,
wherein the first conductive element and the second conductive element are connected to opposite ends of the channel layer,
characterized in that the second layer is in contact with the channel layer and the oxide included in the second layer is an oxide of a material of the channel layer.