Patent Description:
CMOS image sensors have been mass produced and widely used. While traditional image sensors can generate two-dimensional (2D) images and videos, recently there has been a lot of interest in image sensors and systems that can generate three-dimensional (3D) images for applications such as face recognition, augmented reality (AR)/virtual reality (VR), and drones, etc..

One of the existing implementations of 3D image sensors is the time-of-flight (TOF) distance measurement technique. In this technique, in order to increase the accuracy, it is necessary to ensure that the phase relationship between the transmission time point of the light pulse and the sampling time point of the reflected light pulse is synchronized or fixed at a predetermined value, otherwise the accuracy will be degraded; therefore, how to achieve the above purpose has become an important task in this field.

<CIT> discloses an architecture to realize distance measurement based on the indirect phase ToF principle. In an embodiment, a signal processing unit comprises a replicate driver circuit arranged between a phase selector, as part of an oscillation module together with a clock generator and a phase interpolator, and the detection module. The oscillation module generates reference phases. A delay line locked loop provides four reference phases at a desired modulation frequency.

<CIT> discloses a clock signal generating circuit which is coupled through two delay lock loops to a series of photo pixels. The delay lock loops lock a delay of a clock signal from a clock signal generating circuit so that clock signals that are input to each photo pixel in the photo pixel array have the same delays/phases.

<CIT> discloses a distance measuring system for determining the distance to an object by means of a time-of-flight (TOF) method. A reference clock signal generating unit is constituted, for example, from a PLL (Phase Locked Loop).

One purpose of the present application is to disclose a time-of-flight (TOF) sensor, a distance measuring system, and an electronic device that can ensure that the phase relationship between the transmission time point of the light pulse and the sampling time point of the reflected light pulse is fixed at a preset value, so as to solve the issues mentioned above.

The invention is defined as a time-of-flight sensor according to claim <NUM>, as a time-of-flight distance measuring system according to independent claims <NUM> and <NUM>. Advantageous embodiments thereof are defined in the respective dependent claims.

One embodiment of the present application discloses an electronic device, including the above-mentioned distance measuring system and a processor, coupled to the distance measuring system.

The TOF sensor, the distance measuring system and the electronic device of the present disclosure can ensure that the phase relationship between the transmission time point of the light pulse and the sampling time point of the reflected light pulse is fixed at a preset value, so as to maintain the accuracy of the thus-obtained depth information.

The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various embodiments.

Further, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to discuss one element or feature's relationship to another element(s) or feature(s) as illustrated in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The apparatus may be otherwise oriented (e.g., rotated by <NUM> degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the term "about" generally means within <NUM>%, <NUM>%, <NUM>%, or <NUM>% of a given value or range. Alternatively, the term "about" means within an acceptable standard error of the mean when considered by one of ordinary skill in the art. As could be appreciated, other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values, and percentages (such as those for quantities of materials, durations of times, temperatures, operating conditions, portions of amounts, and the likes) disclosed herein should be understood as modified in all instances by the term "about. " Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Here, ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.

There are three main implementations of existing 3D image sensors: stereo binocular, structured light, and time of flight (TOF). Generally, in the TOF implementation, light pulses are transmitted first, and then a TOF sensor is used to sample the reflected light pulses to calculate the time-of-flight of photons between the target and the TOF sensor to obtain the depth information of the target.

However, the time-of-flight obtained by the TOF sensor is often affected by the physical characteristics of the electronic components in the TOF sensor. For example, when the temperature, voltage, or manufacturing process of the operating environment of the TOF sensor changes, the physical characteristics of the electronic components of the TOF sensor may be changed, causing the phase relationship between the transmission time point of the light pulse and the sampling time of the reflected light pulse to be unable to be fixed a preset value, which reduces the accuracy of the depth information obtained. On the contrary, if the phase relationship between the transmission time point of the light pulse and the sampling time point of the reflected light pulse is not affected by temperature, voltage, or manufacturing process, the accuracy of the TOF sensor can be improved. The details are described below.

<FIG> is a schematic diagram illustrating a TOF distance measuring system <NUM> according to the first embodiment of the present application. The TOF distance measuring system <NUM> includes a TOF sensor <NUM> and a light-emitting module <NUM>, which is configured to detect the distance between a target <NUM> and the distance measuring system <NUM>. It should be noted that the distance between the target <NUM> and the distance measuring system <NUM> should be smaller than or is equal to the maximum detectable distance of the distance measuring system <NUM>. In the present embodiment, the TOF sensor <NUM> is disposed at a first chip, for example, the first chip can be a sensor chip, or the TOF sensor <NUM> is part of the first chip; the light-emitting module <NUM> is disposed at a second chip, and the first chip and the second chip can be arranged in an electronic device. For example, the electronic device can be, such as, a smartphone, personal digital assistant, a hand-held computing system, or tablet computer, and the like.

Specifically, the TOF sensor <NUM> controls the light-emitting module <NUM> to transmit light pulse <NUM> following the preset frequency, intensity, and the like. In the present embodiment, the TOF sensor <NUM> controls the light-emitting module <NUM> to intermittently transmit the light pulse <NUM>. The light pulse <NUM> is reflected by the target <NUM> to generate a reflected light pulse <NUM>. The TOF sensor <NUM> senses and samples the reflected light pulse <NUM> to generate a sampling result pout, wherein the sampling result pout can be used to calculate the distance between the target <NUM> and the distance measuring system <NUM>, and a depth information of the target <NUM> can be obtained by calculating the distances to different parts of the target <NUM>.

The TOF sensor <NUM> includes a clock signal generation circuit <NUM>, a transmission circuit <NUM>, a replicated transmission circuit <NUM>, a delay locked loop <NUM>, a clock tree <NUM>, and a pixel array <NUM>. In the present embodiment, the clock signal generation circuit <NUM> is configured to generate a first clock signal clkl and a second clock signal clk2, wherein the first clock signal clkl and the second clock signal clk2 have the same frequency, and there is a predetermined phase difference ϕ1 between the first clock signal clkl and the second clock signal clk2. For example, the clock signal generation circuit <NUM> can generate the first clock signal clk1 and the second clock signal clk2 based on a reference clock (not shown in the drawings), wherein the reference clock source may come from a crystal oscillator external to the chip on which the TOF sensor is located. Moreover, it should be noted that the value of the predetermined phase difference ϕ1 may be set based on the TOF algorithm, and its determination method is outside the scope of the discussion of this application. Therefore, the present application does not particularly limit the value of the predetermined phase difference ϕ1; that is, the predetermined phase difference ϕ1 may be greater than zero, less than zero, or equal to zero.

As can be seen from <FIG>, the first clock signal clk1 passes through a path to control the light-emitting module <NUM> to transmit the light pulses <NUM>; the second clock signal clk2 passes through another path to control the timing of the pixel array <NUM> to sample the reflected light pulse <NUM>. The purpose of this application is to keep the difference between the time point at which the light-emitting module <NUM> transmits the light pulses <NUM> and the time point at which the pixel array <NUM> samples the reflected light pulses <NUM> at a predetermined phase difference ϕ1 as much as possible, and independent of temperature, voltage, or manufacturing process.

The transmission circuit <NUM> is configured to generate a third clock signal clk3 based on the first clock signal clkl, wherein the third clock signal clk3 is outputted to the light-emitting module <NUM>, so that the light-emitting module <NUM> intermittently transmits the light pulse <NUM>. Generally, the second chip where the light-emitting module <NUM> is located and the second chip where the TOF sensor <NUM> is located are different chips, and the frequency the first clock signal clkl may be several hundred MHz. Therefore, the transmission circuit <NUM> must process the first clock signal clkl in order to transmit the first clock signal clkl out of the chip where the TOF sensor <NUM> is located. For example, the transmission circuit <NUM> is a low-voltage differential signaling (LVDS) circuit, which converts the first clock signal clkl into a small amplitude differential signal to reduce noise and save power consumption. However, the present application is not limited thereto, and the transmission circuit <NUM> may also use other methods. For example, the third clock signal clk3 may be a non-differential signal.

- In short, no matter what method the transmission circuit <NUM> uses, it is impossible not to delay the first clock signal clkl; that is, it is difficult to ensure that the phase between the first clock signal clkl after passing through the transmission circuit <NUM> and the second clock signal clk2 remains unchanged, and thus, and the time point of controlling the light-emitting module <NUM> to transmit the light pulse <NUM> becomes uncontrollable. The solution of the present application is to add a replicated transmission circuit <NUM> in the path from the second clock signal clk2 to the pixel array <NUM> to simulate the transmission circuit <NUM>. The replicated transmission circuit <NUM> generates a fourth clock signal clk4 based on the second clock signal clk2. The design of the replicated transmission circuit <NUM> and the transmission circuit <NUM> are substantially the same, so the delays caused to the first clock signal clk1 and the third clock signal clk3 are also substantially the same. In addition, since the replicated transmission circuit <NUM> and the transmission circuit <NUM> are located on the same chip, the temperature, voltage, or manufacturing process will have substantially the same effects on the replicated transmission circuit <NUM> and the transmission circuit <NUM>. In other words, changes in temperature, voltage, or manufacturing process will affect both the replicated transmission circuit <NUM> and the transmission circuit <NUM>, so that the phase difference between the fourth clock signal clk4 and the third clock signal clk3 can be maintained at a predetermined phase difference ϕ1 when the temperature, bias voltage, or process changes. In some embodiments, the layout of the transmission circuit <NUM> is directly adjacent to the layout of the replicated transmission circuit <NUM>, so that the effects of temperature, voltage, or manufacturing process on the transmission circuit <NUM> and the replicated transmission circuit <NUM> are more uniform.

In the present embodiment, the layout of the replicated transmission circuit <NUM> and the layout of the transmission circuit <NUM> are identical. However, the present application is not limited thereto, in certain embodiments, the layout of the replicated transmission circuit <NUM> and the layout of the transmission circuit <NUM> are not identical; for example, it is within the scope of this application to dispose the layout of the replicated transmission circuit <NUM> and the layout of the transmission circuit <NUM> symmetrically, or through other special designs, as long as the delay caused by the transmission circuit <NUM> to the first clock signal clkl and the delay caused by the replicated transmission circuit <NUM> to the third clock signal can be substantially the same.

Since the fourth clock signal clk4 needs to be distributed to a plurality of pixel columns in the pixel array <NUM>, and generally the number of pixel columns in the pixel array <NUM> is large, in order to provide sufficient driving ability, the clock tree <NUM> is needed to generate a plurality of sixth clock signals clk6 with sufficient driving ability to the plurality of pixel columns in the pixel array <NUM>, and to keep the phase relationship between the plurality of sixth clock signals clk6 remains fixed. The delay locked loop <NUM> is designed to ensure that the phase differences between the plurality of sixth clock signals clk6 outputted by the clock tree <NUM> and the fourth clock signal clk4 are maintained at zero when temperature, bias voltage, or process changes, so as to ensure that the phase differences between the plurality of sixth clock signals clk6 outputted by the clock tree <NUM> and the third clock signal clk3 are maintained at the predetermined phase difference ϕ1. Specifically, the phases of the plurality of sixth clock signals clk6 outputted by the clock tree <NUM> are the same, and the delay locked loop <NUM> generates the fifth clock signal clk5 based on one of the plurality of sixth clock signals clk6 and the fourth clock signal clk4.

The clock tree <NUM> includes a plurality of paths, each of which includes a start terminal and an end terminal, wherein the plurality of start terminals are co-located and configured to receive the fifth clock signal clk5, and the plurality of end terminal respectively are coupled to a plurality of pixel columns of the pixel array <NUM>, so that the fifth clock signal clk5 starts from the source, and after passing through the plurality of paths, becomes the plurality of sixth clock signals clk6 to the plurality of pixel columns, and the plurality of paths respectively have a plurality of buffers to increase the driving ability, and the signal transmission distance and arrangement of buffers of each of the plurality of paths from the start terminal to the end terminal are designed such that, for example, the plurality of paths have the same length and have the same number of buffers so that the phase difference between the plurality of sixth clock signals clk6 can be maintained at zero when temperature, bias voltage or process changes.

It should be noted that the delay of each transmission line between the clock signal generation circuit <NUM>, the transmission circuit <NUM>, the replicated transmission circuit <NUM>, the delay locked loop <NUM>, the clock tree <NUM>, and the pixel array <NUM> in <FIG> is relatively small compared to the compensation brought by the replicated transmission circuit <NUM> and the delay locked loop <NUM> and the clock tree <NUM>, so the delay of each transmission line alone is ignored and not discussed here.

<FIG> is a schematic diagram illustrating the delay locked loop <NUM> shown in <FIG> according to the first embodiment of the present application. The delay locked loop <NUM> includes a phase detector <NUM>, a charge pump <NUM>, a filter <NUM>, and a voltage-controlled delay line <NUM>. The phase detector <NUM> receives any one of the sixth clock signals clk6 and the fourth clock signal clk4 and is configured to generate phase difference information se1 between the sixth clock signal and the fourth clock signal clk4. In the embodiment of <FIG>, the phase detector <NUM> is implemented using an analog circuit. The charge pump <NUM> is configured to generate a voltage information sc1 in response to the phase difference information selto to charge or discharge the filter <NUM>; the filter <NUM> performs a filtering process on the voltage information sc1 to generate a voltage-controlled delay line control signal sf1. In the embodiment of <FIG>, the filter <NUM> is implemented using an analog circuit.

The voltage-controlled delay line <NUM> is configured to control the fourth clock signal clk4 to pass through the voltage-controlled delay line <NUM> to generate the fifth clock signal clk5, and voltage-controlled delay line <NUM> causes a variable phase difference variable phase difference between the fifth clock signal clk5 and the fourth clock signal clk4, wherein the variable phase difference is under the control of the voltage-controlled delay line control signal sf1. In the embodiment of <FIG>, the voltage-controlled delay line <NUM> is implemented using an analog circuit. That is, the voltage-controlled delay line is under the control of the control signal sf1, so that the fourth clock signal clk4 input to the voltage-controlled delay line generates a corresponding phase difference to output the fifth clock signal clk5.

<FIG> is a schematic diagram illustrating the delay locked loop <NUM> shown in <FIG> according to the second embodiment of the present application. The delay locked loop <NUM> includes a phase detector <NUM>, an accumulator <NUM>, a filter <NUM>, and a digital delay line <NUM>. The delay locked loop <NUM> in <FIG> is similar to the delay locked loop <NUM> in <FIG>, and the difference is that the delay locked loop <NUM> in <FIG> is implemented by a digital circuit. The phase detector <NUM> is configured to generate phase difference information se2 between one of the plurality of sixth clock signals clk6 and the fourth clock signal clk4. In the embodiment in <FIG>, the phase detector <NUM> is implemented using an analog circuit. The accumulator <NUM> is configured to generate an accumulated phase information sc2 to the filter <NUM> based on the accumulated phase difference information se2, so that the filter <NUM> performs a filtering process on the voltage information sc2 to generate a digital delay line control signal sf2. In the embodiment in <FIG>, the filter <NUM> is implemented using a digital circuit.

The digital delay line <NUM> is configured to control the fourth clock signal clk4 to pass through the digital delay line <NUM> to generate the fifth clock signal clk5, and digital delay line <NUM> causes a variable phase difference between the fifth clock signal clk5 and the fourth clock signal clk4, wherein the variable phase difference is under the control of the digital delay line control signal sf2.

The pixel array <NUM> has a plurality of pixel columns, wherein the plurality of pixel columns respectively sample the reflected light pulse <NUM> based on the plurality of sixth clock signals clk6 to generate a sampling result pout. In certain embodiments, the TOF sensor <NUM> can includes a depth determination unit <NUM>, wherein the depth determination unit <NUM> is configured to obtain a depth information of the target <NUM> based on the sampling result pout. In some other embodiments, the depth determination unit <NUM> can be optional; for example, the sampling result pout generated by the pixel array <NUM> may be transmitted to a processor external to the chip where the TOF sensor <NUM> is located to calculate the depth information of the target <NUM>.

In some embodiments, in order to ensure that the interval between the time when the third clock signal clk3 reaches the light-emitting module <NUM> and the time when the light pulse <NUM> is actually transmitted is changed due to changes in temperature, bias voltage, or process, the light-emitting module <NUM> in <FIG> can be used. <FIG> is a schematic diagram of an embodiment of the light-emitting module <NUM> in <FIG>. In <FIG>, after the third clock signal clk3 reaches the light-emitting module <NUM>, the light source control signal sl is generated through the light source control path <NUM>, and the light source <NUM> intermittently transmits light pulses <NUM> according to the light source control signal sl. The light source <NUM> may be (but is not limited to) a laser diode (LD), a light-emitting diode (LED), or other light sources that can generate light pulses <NUM>. The light source control path <NUM> is specifically designed so that the phase difference between the light source control signal sl and the third clock signal clk3 is not affected by temperature, bias voltage, or process.

However, the embodiment of <FIG> does not necessarily require the use of the light-emitting module <NUM> of <FIG>. However, the use of a general light-emitting module may contribute a slight error such that the difference between the time point at which the light-emitting module <NUM> transmits the light pulse <NUM> and the time point at which the pixel array <NUM> samples the reflected light pulse <NUM> is not exactly equal to the predetermined phase difference ϕ1. Therefore, the present application also presents the embodiment of <FIG> to provide an alternative to using the light-emitting module <NUM> of <FIG>.

<FIG> is a schematic diagram of a second embodiment of the TOF distance measuring system <NUM> of the present application. The difference between the TOF distance measuring system <NUM> in <FIG> and the TOF distance measuring system <NUM> in <FIG> is that the fourth clock signal clk4 in <FIG> is sent directly to the delay locked loop <NUM>, but the fourth clock signal clk4 in <FIG> is sent to the light-emitting module <NUM> outside the chip where the TOF sensor <NUM> is located before it is fed back to the delay locked loop <NUM>. The purpose is to additionally simulate the light source control path <NUM> of the light emitting module <NUM> in the path of the second clock signal clk2 to match the path of the first clock signal clkl.

<FIG> shows a schematic diagram of an embodiment of light emitting module <NUM> in <FIG>. In the present embodiment, a replicated light source control path <NUM> is additionally incorporated in the path between the second clock signal clk2 to the pixel array <NUM> of the light-emitting module <NUM> to simulate a light source control path <NUM>, wherein the replicated light source control path <NUM> generate a seventh clock signal clk7 based on the fourth clock signal clk4. Because the replicated light source control path <NUM> and light source control path <NUM> are designed in substantially the same way, the delays caused to the third clock signal clk3 and the fourth clock signal clk4 are also substantially the same. In addition, since the replicated light source control path and light source control path <NUM> are located in the same chip, the effect of temperature, voltage, or manufacturing process on the replicated light source control path <NUM> and the light source control path <NUM> is substantially the same. In other words, a change in temperature, voltage, or manufacturing process will cause the replicated light source control path and the light source control path <NUM> to change synchronously, causing the phase difference between the light source control signal sl and the seventh clock signal clk7 can be maintained at a predetermined phase difference ϕ1 when temperature, bias voltage, or process changes. The seventh clock signal clk7 is also fed back to the delay locked loop <NUM> of the delay locked loop <NUM>.

Claim 1:
A TOF, time-of-flight, sensor (<NUM>), wherein the TOF sensor (<NUM>) controls a light-emitting module (<NUM>) to intermittently transmit a light pulse (<NUM>), and the light pulse (<NUM>) is reflected by a target (<NUM>) to generate a reflected light pulse (<NUM>), characterized in that the TOF sensor (<NUM>) comprises:
a clock signal generation circuit (<NUM>), configured to generate a first clock signal (clk1) and a second clock signal (clk2), wherein the first clock signal (clkl) and the second clock signal (clk2) have a same frequency, and there is a predetermined phase difference between the first clock signal (clkl) and the second clock signal (clk2);
a transmission circuit (<NUM>), configured to generate a third clock signal (clk3) based on the first clock signal (clkl), wherein the third clock signal (clk3) is outputted to the light-emitting module (<NUM>), so that the light-emitting module (<NUM>) intermittently transmit the light pulse (<NUM>);
a replicated transmission circuit (<NUM>), configured to simulate the transmission circuit (<NUM>), and generate a fourth clock signal (clk4) based on the second clock signal (clk2), so that the phase difference between the fourth clock signal (clk4) and the third clock signal (clk3) is kept the same as the predetermined phase difference;
a delay locked loop (<NUM>), coupled to the replicated transmission circuit (<NUM>) and one of a plurality of sixth clock signals (clk6) to generate a fifth clock signal (clk5) based on the fourth clock signal (clk4) and on one of the plurality of sixth clock signals (clk6), so that the phase difference between one of the plurality of sixth clock signals (clk6) and the fourth clock signal (clk4) is kept at zero;
a clock tree (<NUM>), configured to generate the plurality of sixth clock signals (clk6) based on the fifth clock signal (clk5), wherein a plurality of phases of the plurality of sixth clock signals (clk6) are all the same; and
a pixel array (<NUM>), having a plurality of pixel columns, wherein the plurality of pixel columns perform sampling on the reflected light pulse (<NUM>), respectively, based on the plurality of sixth clock signals (clk6) to generate a sampling result (pout).