Patent Description:
In the field of power electronics, high-voltage semiconductor devices (power devices) are used to which a high voltage is applied.

There has been known a vertical power device structure in which a large current can be applied easily and further a high-voltage resistance and a low on-resistance can be ensured easily (for example, see Patent Literature <NUM>).

Such a vertical power device includes, for example, an n+ type substrate, an n- type epitaxial layer laid on the substrate, a p type body region formed in a surficial portion of the epitaxial layer, and an n+ type source region formed in a surficial portion of the body region. A gate insulating film is such that it extends across the surface of the epitaxial layer outside the body region, the surface of the body region, and the surface of the source region. A gate electrode is then formed on the gate insulating film. A source electrode is connected electrically to the source region. A drain electrode is formed on the back surface of the substrate. The vertical power device is thus formed in which the source electrode and the drain electrode are arranged vertically, that is, perpendicularly to the principal surface of the substrate.

When a voltage equal to or higher than a threshold value is applied to the gate electrode while a source-drain voltage is applied between the source electrode and the drain electrode, an electric field on the gate electrode forms a channel in the vicinity of the interface with the gate insulating film in the body region. This causes a current to flow between the source electrode and the drain electrode and thus the power device to turn on.

<CIT> discloses a silicon carbide semiconductor device comprising a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductivity-type source region formed in a surficial portion of the body region, a gate insulated film provided on the semiconductor layer, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region and the source region, wherein the third portion of the gate insulating film has a thickness greater than a thickness of the first portion and then a thickness of the second portion.

<CIT> discloses a semiconductor device which includes: a SiC-containing n-type epitaxial layer which is stacked on a surface of a n+-type substrate containing SiC; n+-type source regions arranged away from each other in a surface layer of the epitaxial layer; a p-type well contact region sandwiched by the source regions; a p-type well region arranged in contact with surfaces of the source regions and p-type well contact region on the Substrate side; and p-type well extension regions arranged to sandwich the source regions and p-type well region. The impurity concentration of the p-type well region has a peak concentration at a position deeper in the depth direction from the surface of the epitaxial layer toward the substrate than the position of a peak concentration of the p-type well extension regions.

<CIT> discloses a silicon carbide semiconductor device having an n-type source region and a surface channel layer, an n---type epitaxial layer having a lower concentration than the surface channel layer, wherein the source region, the surface channel layer and the epitaxial layer are deposited by epitaxial growth on an epitaxial layer.

<CIT> discloses a method of fabricating an oxide layer and a silicon carbide layer by forming the oxide layer by at least one oxidizing a silicon carbide layer in an N<NUM>O environment or annealing the oxide layer of a silicon carbide layer in an N<NUM>O environment.

<CIT> discloses a silicon carbide semiconductor device, wherein a metal electrode which is another than a gate electrode and which is contacted with a single crystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermo-oxidization temperature by which a gate insulating film is formed.

Further, document <CIT> discloses a film with small hysteresis and high voltage resistance, which is obtained by reducing the carbon content in a gate insulating film on an SiC substrate.

It is functionally sufficient for the gate electrode and the gate insulating film to face the body region only between the source region and the epitaxial layer. However, the gate electrode and the gate insulating film actually overlap the source region in a plan view. This is mainly caused by the manufacturing process. That is, such an overlap region inevitably exists to reliably make the gate electrode and the gate insulating film face the body region between the source region and the epitaxial layer.

The inventors, however, have found from a detailed research that the gate insulating film has a shorter TDDB (Time-Dependent Dielectric Breakdown) lifetime on the source region than that on the epitaxial layer and the body region. This means that the gate insulating film on the source region puts a limitation on the long-term reliability of the entire gate insulating film, resulting in an obstacle in ensuring reliability of the device.

The present invention hence provides a semiconductor device having a structure in which a gate insulating film can easily ensure long-term reliability and thereby the device itself can easily ensure reliability, and also a method for manufacturing such a semiconductor device.

A semiconductor device according to the present invention is defined in claim <NUM>.

The aforementioned or other objects, features, and effects of the present invention will be clarified by the following description of embodiments with reference to the accompanying drawings.

A semiconductor device according to the present invention as defined by claim <NUM> provides a semiconductor device including: a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductive-type source region formed in a surficial portion of the body region, a gate insulating film provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region. The third portion of the gate insulating film has a thickness greater than the thickness of the first portion and the thickness of the second portion.

In the semiconductor device, the gate insulating film contains nitrogen atoms. The gate insulating film, composed of an oxide film contains nitrogen atoms at the interface of the oxide film, and has a reliability equal to or higher than <NUM> times that in the case of containing no nitrogen atom. More specifically, the QBD (Charge to Breakdown) increases. Further, in the semiconductor device, the third portion of the gate insulating film in contact with the source region has a thickness greater than the thickness of the first portion in contact with the semiconductor layer (e.g., epitaxial layer) and the second portion in contact with the body region. This allows an electric field, when applied to the gate insulating film, to be reduced in the third portion in contact with the source region, resulting in a reduced leak current in the third portion. This can prevent breakdown in the third portion in contact with the source region, whereby the entire gate insulating film can easily ensure long-term reliability. Accordingly, the entire semiconductor device can easily ensure reliability.

The thickness of the third portion of the gate insulating film is preferably equal to or greater than <NUM> times the thickness of the first portion. This results in that the long-term reliability of the third portion in contact with the source region is equal to or higher than that of the first portion in contact with the semiconductor layer. Thus, the long-term reliability of the third portion in contact with the source region does not put a limitation on the long-term reliability of the entire gate insulating film. The semiconductor layer may contain first conductive-type impurities at a concentration of <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM>, for example.

The thickness of the second portion of the gate insulating film is preferably equal to or greater than <NUM>. If the gate insulating film is composed of, for example, an oxide film containing nitrogen atoms, the second portion having a thickness of <NUM> or more can ensure a voltage resistance or <NUM> V or higher.

The source region preferably contains first conductive-type impurities at a concentration of <NUM> × <NUM><NUM> cm-<NUM> or higher (more preferably <NUM> × <NUM><NUM> cm-<NUM> or higher). In this case, the semiconductor layer outside the body region and the body region preferably have a first impurity concentration of lower than <NUM> × <NUM><NUM> cm-<NUM> (e.g., <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM>). This allows the third portion in contact with the source region to have a thickness greater than that of the first and second portions in contact, respectively, with the semiconductor layer and the body region, the gate insulating film being composed of a thermally-oxidized film formed by thermally oxidizing the surface of the semiconductor layer, the body region, and the source region. It is therefore possible to easily form a gate insulating film having a selectively thickened third portion.

The semiconductor device further includes an SiC substrate that has a silicon plane having an off-angle of <NUM> to <NUM> degrees, and the semiconductor layer is formed on the silicon plane of the SiC substrate. This can easily thicken the oxide film composed of a thermally-oxidized film formed by thermally oxidizing the surface of the semiconductor layer, the body region, and the source region. If the off-angle is greater than the above range or the semiconductor layer is formed on a carbon plane of an SiC crystal, it is difficult to form a thickened oxide film on the source region. It is noted that the surface of the semiconductor layer, if formed through crystal growth (epitaxial growth) on the silicon plane of the SiC substrate, is also formed of a silicon plane.

The third portion of the gate insulating film preferably has an area smaller than the area of the first portion and the area of the second portion. In this arrangement, since the third portion, which may put a limitation on the long-term reliability, has a smaller area, the entire gate insulating film can easily ensure reliability.

The body region preferably contains second conductive-type impurities at the surface in contact with the gate insulating film at a concentration of <NUM> × <NUM><NUM> cm-<NUM> or lower (more preferably <NUM> × <NUM><NUM> cm-<NUM> or lower). According to this arrangement, if the gate insulating film is composed of an oxide film, the thickness of the third portion on the source region can be greater than that of the second portion on the body region. In addition, since the body region has a relatively low impurity concentration, the device can achieve higher carrier mobility.

The gate electrode preferably protrudes into the source region by <NUM> to <NUM> (more preferably <NUM> to <NUM>) from the boundary between the body region and the source region. This arrangement allows the gate electrode to reliably face the body region, which exists between the source region and the semiconductor layer, whereby it is possible to reliably control the formation of a channel in the body region. Further, since the gate insulating film contains nitrogen atoms and has the thickened portion (third portion) on the source region, it is possible to ensure a sufficient resistance (voltage resistance) against an electric field between the gate electrode and the source region.

The semiconductor device preferably has a channel length of <NUM> or more. This results in a reduced off-state leak current and therefore an improved yield.

The gate electrode is preferably applied with a voltage of <NUM> V or higher. This allows a channel to be formed in the body region just beneath the gate electrode.

The gate electrode is preferably made of polysilicon (more preferably p type polysilicon).

The semiconductor layer is made of SiC. In devices using SiC as a semiconductor material, the reliability (lifetime) of a gate insulating film formed on the surface of an SiC semiconductor layer is inferior to the reliability (lifetime) of a gate insulating film in Si-semiconductor-based devices. This is for the reason that compared to Si, SiC provides a thermally-oxidized film with lower reliability. In addition, since step bunching occurs on the growth surface of an SiC single crystal, an electric field is likely to concentrate locally on the gate insulating film on the SiC semiconductor layer. Applying the present invention to SiC-semiconductor-based devices hence allows the gate insulating film to have a sufficient reliability. It is therefore possible to provide a higher-reliability SiC semiconductor device.

One embodiment not being part of but useful to understand the present invention provides a method for manufacturing a semiconductor device including the steps of forming a second conductive-type body region in a surficial portion of a first conductive-type semiconductor layer, implanting first conductive-type impurity ions into the body region while keeping the semiconductor layer at <NUM> or lower to form a source region containing first conductive-type impurities at a concentration of <NUM> × <NUM><NUM> cm-<NUM> or higher (preferably <NUM> × <NUM><NUM> cm-<NUM> or higher) in a surficial portion of the body region, oxidizing the surface of the semiconductor layer while supplying source gas containing nitrogen oxide gas to the surface of the semiconductor layer to form a gate insulating film containing nitrogen atoms and including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and forming a gate electrode on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region.

In the method, first conductive-type impurity ions are implanted into the body region while the semiconductor layer is kept at <NUM> or lower (preferably at room temperature) to form a source region having an impurity concentration of <NUM> × <NUM><NUM> cm-<NUM> or higher. This causes a gate insulating film, when formed thereafter by oxidizing the surface of the semiconductor layer, to include a third portion in contact with the source region, having a thickness greater than that of first and second portions in contact, respectively, with the semiconductor layer and the body region. In addition, the gate insulating film, which is formed while nitrogen oxide gas is supplied, contains nitrogen atoms. This improves the reliability (lifetime) of, particularly, the third portion in contact with the source region, whereby it is possible to form a gate insulating film with higher reliability. It is therefore possible to produce a reliable semiconductor device.

The source region preferably has a thickness of <NUM> or more before the oxidizing step. The gate insulating film, which is formed in the oxidizing step, also expands into the source region. The source region having a thickness of <NUM> or more hence allows the first conductive-type source region to remain just beneath the gate insulating film after being formed.

The method preferably further includes the step of epitaxially growing the semiconductor layer on a silicon plane having an off-angle of <NUM> to <NUM> degrees (preferably <NUM> to <NUM> degrees) of an SiC substrate. This causes the semiconductor layer to have a silicon plane having an off-angle of <NUM> to <NUM> degrees (preferably <NUM> to <NUM> degrees). Accordingly, the surfaces of the semiconductor layer, the source region, and the body region are all formed of a silicon plane having an off-angle of <NUM> to <NUM> degrees (preferably <NUM> to <NUM> degrees). This can easily thicken the oxide film if composed of a thermally-oxidized film formed by thermally oxidizing the surface of the semiconductor layer, the body region, and the source region. If the off-angle is greater than the above range or the semiconductor layer is formed on a carbon plane of an SiC crystal, it is difficult to form a thickened oxide film on the source region.

The step of forming the body region preferably includes the step of implanting second conductive-type impurity ions into the semiconductor layer to form the body region containing second conductive-type impurities in the surficial portion thereof at a concentration of <NUM> × <NUM><NUM> cm-<NUM> or lower. This allows the third portion on the source region to have a thickness greater than that of the second portion on the body region through the oxidizing step. In addition, since the body region has a relatively low impurity concentration, the device can achieve higher carrier mobility.

Embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings.

<FIG> are schematic plan views of a semiconductor device according to an embodiment of the present invention, where <FIG> is an overall view and <FIG> is an enlarged view of the internal structure. <FIG> is a cross-sectional view taken along the section line II-II of <FIG>.

The semiconductor device <NUM> is an SiC-based planar-gate VDMOSFET (Vertical Double diffused MOSFET) having a square chip form in a plan view, for example, as shown in <FIG>. The chip-formed semiconductor device <NUM> has vertical and horizontal lengths of about several millimeters, for example, on the plane of <FIG>.

A source pad <NUM> is formed on the surface of the semiconductor device <NUM>. The source pad <NUM> has an approximately square shape in a plan view with the four corners bent outward and is formed in a manner covering almost the entire surface of the semiconductor device <NUM>. A removal region <NUM> having an approximately square shape in a plan view is formed near the center of one side of the source pad <NUM>. The source pad <NUM> is not formed in the removal region <NUM>.

A gate pad <NUM> is disposed in the removal region <NUM>. The gate pad <NUM> and the source pad <NUM> are spaced apart and insulated from each other.

Next will be described the internal structure of the semiconductor device <NUM>.

The semiconductor device <NUM> includes an n+ type (at a concentration of <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM>, for example) SiC substrate <NUM>. The SiC substrate <NUM> serves as a drain of the semiconductor device <NUM> in the present embodiment, with the surface <NUM> (upper surface) thereof being an Si plane (silicon plane), while the back surface <NUM> (lower surface) thereof being a C plane (carbon plane). The surface <NUM> of the SiC substrate <NUM> is an Si plane having an off-angle of <NUM> to <NUM> degrees.

An n- type (at an n type impurity concentration of <NUM> × <NUM><NUM> to <NUM> × <NUM><NUM> cm-<NUM>, for example) SiC-based epitaxial layer <NUM> having a lower concentration than that of the SiC substrate <NUM> is laid on the SiC substrate <NUM>. The epitaxial layer <NUM>, which serves as a semiconductor layer, is formed on the SiC substrate <NUM> through so-called epitaxial growth. The epitaxial layer <NUM>, which is formed on the Si-plane surface <NUM>, is grown using the Si plane as a growth main face. Accordingly, the surface <NUM> of the epitaxial layer <NUM> formed through epitaxial growth is also an Si plane, as is the case with the surface <NUM> of the SiC substrate <NUM> and, more specifically, having an off-angle of <NUM> to <NUM> degrees, as is the case with the SiC substrate <NUM>.

As shown in <FIG>, the semiconductor device <NUM> is formed with an active region <NUM> disposed in the center on the epitaxial layer <NUM> in a plan view and serving as a field-effect transistor. Multiple (two in the present embodiment) guard rings <NUM> (indicated by the double-hatched line in <FIG>) are formed in the epitaxial layer <NUM> in a manner surrounding and spaced apart from the active region <NUM>.

The distance between the active region <NUM> and the guard rings <NUM> is approximately constant at every circumferential point. The guard rings <NUM> are p- type low-concentration (at a concentration of <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM>, for example) regions formed by implanting p type impurities into the epitaxial layer <NUM>.

In the active region <NUM>, many p type body regions <NUM> are formed in the surface <NUM> (Si plane) of the epitaxial layer <NUM> and arranged in a matrix at a constant pitch in the row and column directions. Each one of the body regions <NUM> has, for example, a square shape in a plan view and has vertical and horizontal lengths of about <NUM>, for example, on the plane of <FIG>. The body region <NUM> has a depth of about <NUM>, for example. The body region <NUM> also has a p type impurity concentration of <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM> (equal to or lower than <NUM> × <NUM><NUM> cm-<NUM>), for example. Such a low impurity concentration contributes to the device achieving higher carrier mobility. The p type impurity may be, for example, Al. On the other hand, the area of the epitaxial layer <NUM> closer to the SiC substrate <NUM> (C plane) than to the body region <NUM> remains unchanged after the epitaxial growth to serve as an n- type drift region <NUM>.

A p+ type body contact region <NUM> is formed in the center of a surficial portion of each body region <NUM>, and an n+ type source region <NUM> is formed in a manner surrounding the body contact region <NUM>. The body contact region <NUM> has a square shape in a plan view and has vertical and horizontal lengths of about <NUM>, for example, on the plane of <FIG>. The body contact region <NUM> has a depth of <NUM>, for example.

The n+ type source region <NUM> has an annular square shape in a plan view and has vertical and horizontal lengths of about <NUM>, for example, on the paper including <FIG>. The source region <NUM> has a depth of about <NUM>, for example. The source region <NUM> has an n type impurity concentration of <NUM> × <NUM>-<NUM> or higher, and preferably <NUM> × <NUM><NUM> cm-<NUM> or higher. More specifically, the concentration may be <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM>, and more preferably <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM>. The n type impurity may be P (phosphorus).

The region between the body regions <NUM> (inter-body region <NUM> sandwiched between side surfaces of adjacent body regions <NUM>), which are arranged in a matrix at a constant pitch in the active region <NUM>, is in a grid form having a constant width (e.g., <NUM>).

On the inter-body region <NUM>, a grid-like gate insulating film <NUM> (not shown in <FIG>) is formed along the inter-body region <NUM>. The gate insulating film <NUM> exists between adjacent body regions <NUM> and covers a portion of each body region <NUM> surrounding the source region <NUM> (a peripheral edge portion of each body region <NUM>) and the outer peripheral edge of each source region <NUM>. In the present embodiment, the gate insulating film <NUM> is composed of an oxide film containing nitrogen, i.e. a nitride-oxide silicon film formed through thermal oxidation using gas containing nitrogen and oxygen.

The gate insulating film <NUM> includes a first portion <NUM> in contact with the epitaxial layer <NUM> outside each body region <NUM>, a second portion <NUM> in contact with each body region <NUM>, and a third portion <NUM> in contact with each source region <NUM>. As clearly shown in <FIG>, the third portion <NUM> has a thickness T3 greater than the thickness T1 of the first portion <NUM> and the thickness T2 of the second portion. In more detail, the lower interface (with the source region <NUM>) of the third portion <NUM> is at a position lower (closer to the SiC substrate <NUM>, that is, at a deeper position from the surface of the epitaxial layer <NUM>) than the lower interface (with the epitaxial layer <NUM>) of the first portion <NUM> and the lower interface (with the body region <NUM>) of the second portion <NUM>. Also, the upper interface (with the gate electrode <NUM>) of the third portion <NUM> is at a position higher (closer to the gate electrode <NUM>, that is, at a farther position from the surface of the epitaxial layer <NUM>) than the upper interface (with the gate electrode <NUM>) of the first portion <NUM> and the upper interface (with the gate electrode <NUM>) of the second portion <NUM>. The thicknesses T1 and T2 of the first and second portions <NUM> and <NUM> may be, for example, <NUM> or more (e.g., about <NUM>). Meanwhile, the thickness T3 of the third portion <NUM> is preferably equal to or greater than <NUM> times the thickness T1 of the first portion <NUM>, for example, and may be about <NUM>.

The gate electrode <NUM> is formed on the gate insulating film <NUM>. The gate electrode <NUM> is formed in a grid along the grid-like gate insulating film <NUM> and faces a peripheral edge portion of each body region <NUM> with the gate insulating film <NUM> therebetween. In more detail, the gate electrode <NUM> faces an area extending across the epitaxial layer <NUM> outside the body region <NUM>, the body region <NUM>, and the source region <NUM>, with the gate insulating film <NUM> interposed therebetween. Accordingly, the gate electrode <NUM> overlaps the source region <NUM> in a plan view. For example, the gate electrode <NUM> protrudes onto the source region <NUM> by <NUM> to <NUM> (preferably <NUM> to <NUM>) from the boundary between the body region <NUM> and the source region <NUM>. This allows the gate electrode <NUM> to reliably face the body region <NUM>, which exists between the source region <NUM> and the epitaxial layer <NUM>, whereby it is possible to reliably control the formation of a channel in the body region <NUM>. The gate electrode <NUM> is made of, for example, polysilicon, into which p type impurities are introduced at high concentration to achieve lower resistance, for example. The gate electrode <NUM> has a thickness of about <NUM>Å, for example.

In the semiconductor device <NUM>, the boundary between unit cells is set at the center in the width direction of the inter-body region <NUM>. Each unit cell has vertical and horizontal lengths of about <NUM>, for example, on the plane of <FIG>. In each unit cell, a controlled voltage (e.g., of <NUM> V or higher) is applied to the gate electrode <NUM> to form an annular channel in a peripheral edge portion of the body region <NUM> in the unit cell. A drain current flowing in the drift region <NUM> along the four side surfaces of the body region <NUM> toward the surface <NUM> of the epitaxial layer <NUM> can then flow via the annular channel to the source region <NUM>. The channel length L is defined by the width of the body region <NUM> just beneath the gate electrode <NUM> and may be <NUM> or more (e.g., about <NUM>).

On the epitaxial layer <NUM>, an interlayer insulating film <NUM> made of, for example, SiO<NUM> is laid in a manner covering the gate electrode <NUM>. A contact hole <NUM> is formed in the interlayer insulating film <NUM>. Within the contact hole <NUM>, the central portion of the source region <NUM> and the entire body contact region <NUM> are exposed.

A source electrode <NUM> is formed on the interlayer insulating film <NUM>. The source electrode <NUM> is in collective contact with the body contact regions <NUM> and the source regions <NUM> of all the unit cells via each contact hole <NUM>. That is, the source electrode <NUM> serves as a wiring commonly used by all the unit cells. An interlayer insulating film (not shown) is formed on the source electrode <NUM> and, via the interlayer insulating film (not shown), the source electrode <NUM> is connected electrically to the source pad <NUM> (see <FIG>). On the other hand, the gate pad <NUM> (see <FIG>) is connected electrically to the gate electrode <NUM> via a gate wiring (not shown) installed on the interlayer insulating film (not shown).

The source electrode <NUM> may have a structure in which a Ti/TiN layer <NUM> and an Al layer <NUM> are laminated in this order from the side in contact with the epitaxial layer <NUM>. The Ti/TiN layer <NUM> is a laminated film in which a Ti layer serving as an adhesive layer is provided closer to the epitaxial layer <NUM> and a TiN layer serving as a barrier layer is laid on the Ti layer. The barrier layer prevents constituent atoms (Al atoms) of the Al layer <NUM> from diffusing into the epitaxial layer <NUM>.

On the back surface <NUM> of the SiC substrate <NUM>, a drain electrode <NUM> is formed in a manner covering the entire surface. The drain electrode <NUM> is commonly used by all the unit cells. To the drain electrode <NUM>, a laminate structure (Ti/Ni/Au/Ag) in which Ti, Ni, Au, and Ag are laminated, for example, in this order from the side closer to the SiC substrate <NUM> may be applied.

<FIG> are schematic cross-sectional views illustrating a method for manufacturing the semiconductor device <NUM>.

In the process of manufacturing the semiconductor device <NUM>, as shown in <FIG>, an SiC crystal is first grown on the surface <NUM> (Si plane) of an SiC substrate <NUM> while n type impurities (e.g., N (nitrogen)) are introduced with an epitaxial growth technique such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy), or MBE (Molecular Beam Epitaxy). An n- type epitaxial layer <NUM> is thus formed on the SiC substrate <NUM>. The n type impurity concentration is, for example, <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM>.

Next, as shown in <FIG>, an SiO<NUM> mask <NUM> having openings through which body regions <NUM> are to be formed is used to implant p type impurities (e.g., Al (aluminum)) into the epitaxial layer <NUM> through the surface <NUM> of the epitaxial layer <NUM>. Conditions of this implantation may include, for example, a dose amount of about <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM> and an acceleration energy of about <NUM> keV to <NUM> keV, although depending on the type of p type impurities. Body regions <NUM> are thus formed in a surficial portion of the epitaxial layer <NUM>. The body regions <NUM> have a p type impurity concentration of <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM> (equal to or lower than <NUM> × <NUM><NUM> cm-<NUM>), for example. A base layer portion of the epitaxial layer <NUM> remains unchanged after the epitaxial growth to form a drift region <NUM>.

Next, as shown in <FIG>, an SiO<NUM> mask <NUM> having openings through which source regions <NUM> are to be formed is used to implant n type impurities (e.g., P (phosphorus)) into the epitaxial layer <NUM> through the surface <NUM> of the epitaxial layer <NUM>. In this step, the epitaxial layer <NUM> is kept at a temperature of <NUM> or lower (e.g., at room temperature). More specifically, a multi-stage (e.g., <NUM>-stage) ion implantation may be performed while the epitaxial layer <NUM> is kept at room temperature at a dose amount of <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM> and an acceleration energy of <NUM> keV to <NUM> keV, for example, although depending on the type of n type impurities. Source regions <NUM> are thus formed in a surficial portion of each body region <NUM>. The epitaxial layer <NUM> is kept at a temperature of <NUM> or lower during the ion implantation so that the source regions <NUM> cannot crystallize. This allows a thick gate insulating film <NUM> to be formed on the source regions <NUM> in a thermal oxidation step (see <FIG>) to be described hereinafter. The source regions <NUM> have an n type impurity concentration of <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM>, for example, and more preferably <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM>.

Next, as shown in <FIG>, an SiO<NUM> mask <NUM> having openings through which guard rings <NUM> are to be formed is used to implant p type impurities (e.g., Al) into the epitaxial layer <NUM> through the surface <NUM> of the epitaxial layer <NUM>. More specifically, an ion implantation may be performed at a dose amount of about <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM> and an acceleration energy of about <NUM> keV, for example, although depending on the type of p type impurities. Guard rings <NUM> are thus formed and an active region <NUM> is defined.

Next, as shown in <FIG>, an SiO<NUM> mask <NUM> having openings through which body contact regions <NUM> are to be formed is used to implant p type impurities (e.g., Al) into the epitaxial layer <NUM> through the surface <NUM> of the epitaxial layer <NUM>. More specifically, a multi-stage (<NUM>-stage) implantation may be performed at a dose amount of about <NUM> × <NUM><NUM> cm-<NUM> to <NUM> × <NUM><NUM> cm-<NUM> and an acceleration energy of <NUM> keV to <NUM> keV, for example, although depending on the type of p type impurities. Body contact regions <NUM> are thus formed.

Next, as shown in <FIG>, the epitaxial layer <NUM> undergoes an annealing treatment (heat treatment) for <NUM> to <NUM> minutes at <NUM> to <NUM>, for example. This causes n type and p type impurity ions implanted in the surficial portion of the epitaxial layer <NUM> to be activated. The annealing treatment of the epitaxial layer <NUM> may be performed, for example, in a resistance heating furnace or a high-frequency induction heating furnace at an approximately controlled temperature.

Next, as shown in <FIG>, the surface <NUM> of the epitaxial layer <NUM> is thermally oxidized to form a gate insulating film <NUM> covering the entire surface <NUM>. More specifically, a gate insulating film <NUM> composed of a nitride-oxide silicon film is formed through thermal oxidation (e.g., for <NUM> to <NUM> days at about <NUM>) in an atmosphere containing nitrogen and oxygen. As mentioned above, the source regions <NUM> contain n type impurity ions implanted so as to have a concentration of <NUM> × <NUM><NUM> cm-<NUM> or higher and the ion implantation is performed at a low temperature (<NUM> or lower) at which the source regions <NUM> cannot crystallize. As a result, the gate insulating film <NUM>, formed through thermal oxidation, includes a third portion <NUM>, in contact with each source region <NUM>, having a locally increased thickness T3. Accordingly, the thickness T3 of the third portion <NUM> is greater than the thickness T1 of the first portion <NUM> in contact with the epitaxial layer <NUM> and the thickness T2 of the second portion <NUM> in contact with each body region <NUM>.

Next, as shown in <FIG>, a polysilicon material <NUM> is deposited on the epitaxial layer <NUM> using a CVD method while p type impurities (e.g., B (boron)) are introduced. It is to be understood that impurities may be introduced into the polysilicon material <NUM> through ion implantation.

Thereafter, as shown in <FIG>, unnecessary portions (portions not to be a gate electrode <NUM>) of the deposited polysilicon material <NUM> are removed through dry etching. A gate electrode <NUM> made of polysilicon is thus formed.

Next, as shown in <FIG>, an interlayer insulating film <NUM> made of SiO<NUM> is laid on the epitaxial layer <NUM> using a CVD method.

As shown in <FIG>, the interlayer insulating film <NUM> and the gate insulating film <NUM> are then patterned continuously to form contact holes <NUM>.

Thereafter, Ti, TiN, and Al are, for example, sputtered in this order on the interlayer insulating film <NUM> to form a source electrode <NUM>. Also, Ti, Ni, Au, and Ag are, for example, sputtered in this order on the back surface <NUM> of the SiC substrate <NUM> to form a drain electrode <NUM>.

Following the steps above, an interlayer insulating film (not shown), a source pad <NUM>, and a gate pad <NUM>, etc., are formed to obtain the semiconductor device <NUM> shown in <FIG>, and <FIG>.

In the semiconductor device <NUM>, when a drain (source-drain) voltage is applied between the source pad <NUM> (source electrode <NUM>) and the drain electrode <NUM> and a predetermined voltage (equal to or higher than a gate threshold voltage, that is, <NUM> V or higher, for example) is applied to the gate pad <NUM> (gate electrode <NUM>) with the source pad <NUM> grounded (i.e. the source electrode <NUM> is at <NUM> V), an annular channel is formed in a peripheral edge portion of the body region <NUM> of each unit cell. This causes a current to flow from the drain electrode <NUM> to the source electrode <NUM> and the unit cell to turn on.

The inventors of the present application have conducted research and found that if the gate insulating film <NUM> is formed to have a substantially uniform thickness at every point, TDDB (Time-Dependent Dielectric Breakdown) occurs at portions in contact with the source regions <NUM>. Hence, in the gate insulating film <NUM> of the present embodiment, the thickness T3 of the third portion <NUM> in contact with each source region <NUM> is greater than the thicknesses T1 and T2 of the other portions. This allows an electric field to be reduced in the third portion <NUM>, resulting in a reduced leak current and therefore a longer TDDB lifetime. This improves the reliability of the entire gate insulating film <NUM>, which in turn improves the reliability of the semiconductor device <NUM>. Additionally, the gate insulating film <NUM> is composed of a nitride-oxide film and contains nitrogen. As a result, the gate insulating film <NUM> has an increased voltage resistance and thus gains a higher reliability, which in turn further improves the reliability of the semiconductor device <NUM>.

<FIG> shows a comparison of QBD (Charge to Breakdown: constant-current TDDB test) between oxide films containing nitrogen and oxide films containing no nitrogen. The symbols "Δ" indicate QBD measurement results for oxide films containing nitrogen and the symbols "◇" indicate QBD measurement results for oxide films containing no nitrogen. The oxide films containing nitrogen were formed by thermally oxidizing the surface of an SiC crystal in an oxidation gas atmosphere containing N. The oxide films containing no nitrogen were formed by thermally oxidizing the surface of an SiC crystal in a dry oxygen (dry O<NUM>) atmosphere. It is found from the measurement results shown in <FIG> that the oxide films containing nitrogen show a QBD equal to or higher than <NUM> times, more specifically, one digit higher than that of the oxide films containing no nitrogen. It is therefore found that the gate insulating film <NUM>, which contains nitrogen, gains a high reliability against breakdown.

<FIG> shows results of TDDB tests (constant-voltage TDDB) conducted on thermally-oxidized films containing nitrogen. The line L1 indicates test results for a thermally-oxidized film formed in a <NUM>-µm square and the line L2 indicates test results for a thermally-oxidized film formed in a <NUM>-µm square. The horizontal axis of <FIG> represents the sample temperature during each test, while the vertical axis of <FIG> represents the time to breakdown occurring in <NUM>% of multiple samples. The larger the area of the thermally-oxidized film, the higher the possibility of having sites of poor film quality becomes, and the TDDB lifetime seems to be shortened.

For the reason above, in the gate insulating film <NUM>, the third portion <NUM> in contact with each source region <NUM> preferably has an area smaller than that of the first and second portions <NUM> and <NUM>. This results in a longer TDDB lifetime of the third portion <NUM>, avoiding the third portion <NUM> putting a limitation on the reliability of the gate insulating film <NUM>.

<FIG> shows an estimation result of TDDB lifetime (constant-voltage TDDB) for a thermally-oxidized film having a thickness of <NUM> (containing nitrogen atoms). The horizontal axis represents the voltage applied to the thermally-oxidized film, while the vertical axis represents the time to breakdown of the thermally-oxidized film. The line L3 is drawn based on results of measuring the TDDB lifetime when the applied voltage is <NUM> V, <NUM> V, and <NUM> V. For example, assuming that a voltage of <NUM> V is applied to the thermally-oxidized film under the practical environment of usage, the time to breakdown is <NUM> × <NUM><NUM> sec (<NUM> years). Accordingly, in the case of guaranteeing a lifetime of <NUM> years as a product, the second portion of the gate insulating film <NUM> in contact with each body region <NUM> is only required to have a thickness of <NUM> or more. In the above-described embodiment, the thicknesses T1 and T2 of the first and second portions <NUM> and <NUM> of the gate insulating film <NUM> are, for example, <NUM> or more (preferably <NUM> or more), whereby the first and second portions <NUM> and <NUM> can ensure a voltage resistance of <NUM> V or higher and have a sufficient TDDB lifetime.

<FIG> shows results of TDDB tests (constant-voltage TDDB) conducted on the produced multiple samples having an insulating film equivalent to the first portion <NUM> of the gate insulating film <NUM> and an insulating film equivalent to the third portion <NUM> of the gate insulating film <NUM>. When an electric field of <NUM> MV/cm was applied to the sample having an insulating film equivalent to the first portion <NUM>, the time to breakdown was about <NUM> sec (indicated by the line L4). On the other hand, when an electric field of <NUM> MV/cm was applied to the sample having an insulating film equivalent to the third portion <NUM>, the time to breakdown was shorter than <NUM> sec. From these results, if the gate insulating film <NUM> is produced such that the thickness T3 of the third portion <NUM> is equal to or smaller than <NUM>/<NUM> = <NUM> times the thickness T1 of the first portion <NUM>, the third portion <NUM> will be subject to breakdown, if occurring in the gate insulating film <NUM>. For example, if the first portion <NUM> has a thickness T1 of <NUM> and the third portion <NUM> has a thickness T3 of <NUM> and when the gate insulating film <NUM> is applied with a voltage of <NUM> V, the first portion <NUM> is applied with an electric field of <NUM> MV/cm, while the third portion <NUM> is applied with an electric field of <NUM> MV/cm, and therefore the third portion <NUM> will be subject to breakdown, if occurring in the gate insulating film.

On the other hand, when an electric field of <NUM> MV/cm was applied to the sample having an insulating film equivalent to the third portion <NUM>, the time to breakdown was about <NUM> sec (note that the data measurements for the cases of <NUM> MV/cm and <NUM> MV/cm were cut short, and the time to breakdown is actually longer than plotted in the graph). From these results, if the gate insulating film <NUM> is produced such that the thickness T3 of the third portion <NUM> is equal to or greater than <NUM>/<NUM> = <NUM> times the thickness T1 of the first portion <NUM>, it is possible to prevent or avoid the third portion <NUM> from being subject to breakdown, if occurring in the gate insulating film <NUM>. That is, if the thickness T3 of the third portion <NUM> is equal to or greater than <NUM> times the thickness T1 of the first portion <NUM>, the third portion <NUM>, which has a lower reliability, cannot be subject to breakdown, whereby the gate insulating film <NUM> can ensure required reliability.

<FIG> shows the I-V characteristics of the semiconductor device <NUM>. The horizontal axis represents the drain voltage, while the vertical axis represents the drain current. The drain voltage/drain current characteristics are shown at a gate voltage VG of <NUM> to <NUM> V. It is found from <FIG> that when the gate voltage VG is <NUM> V or higher, a channel is formed and the drain current shows a significant value.

<FIG> shows a relationship between the channel length L and the DS yield (off-characteristics). The DS yield means a ratio of products that undergo a source-drain off-state (cut-off state) when the gate voltage VG is lower than a threshold value (e.g., <NUM> V). <FIG> shows relative values, given that the yield at the channel length L = <NUM> is <NUM>. It is found from <FIG> that the DS yield is saturated at the channel length L = <NUM>. That is, the channel length L of <NUM> or more allows the semiconductor device <NUM> to be produced in good yield.

Next will be described the relationship between the impurity concentration in the SiC epitaxial layer and the thickness of the thermally-oxidized film formed on the surface of the epitaxial layer. Multiple test samples including <NUM> × <NUM> rectangular ones and fan-shaped ones having a radius of <NUM> or less were used to conduct an experiment.

Each sample underwent the following process flow. First, the sample substrate with an SiC epitaxial layer formed thereon was rinsed, and then phosphorus (P) ions were implanted into the SiC epitaxial layer as n type impurity ions. Next, the implanted phosphorus ions were activated through heat treatment (annealing), and then thermal oxidation was applied (in an oxidation gas atmosphere containing N). The thickness of the thermally-oxidized film formed on the surface of the SiC epitaxial layer was then measured.

The implantation of phosphorus ions was carried out while the epitaxial layer was kept at a temperature of <NUM> or lower (specifically at room temperature) under the first, second, or third condition shown in Table <NUM> below.

That is, under the first condition, the surficial portion of the SiC epitaxial layer contained n type impurities at a concentration of <NUM> × <NUM><NUM> cm-<NUM>. Also, under the second condition, the surficial portion of the SiC epitaxial layer contained n type impurities at a concentration of <NUM> × <NUM><NUM> cm-<NUM>. Further, under the third condition, the surficial portion of the SiC epitaxial layer contained n type impurities at a concentration of <NUM> × <NUM><NUM> cm-<NUM>.

Table <NUM> below shows results of measuring the film thickness (median values of the measured thickness for multiple samples). That is, the thickness was <NUM> under the first condition, <NUM> under the second condition, and <NUM> under the third condition. It is found from these results that the higher the n type impurity concentration, the more the thermally-oxidized film is likely to be thickened (the higher the oxidation rate becomes), and that if the n type impurity concentration is at least <NUM> × <NUM><NUM> cm-<NUM>, an increase in the oxidation rate is observed clearly.

As a result, in the semiconductor device <NUM>, each source region <NUM> preferably has an n type impurity concentration of <NUM> × <NUM><NUM> cm-<NUM> or higher, whereby the thickness T3 of the third portion <NUM> of the gate insulating film <NUM> in contact with each source region <NUM> can be increased selectively. Also, each source region <NUM> preferably has an n type impurity concentration of <NUM> × <NUM><NUM> cm-<NUM> or lower, at which there is an activation limit.

It is noted that in the semiconductor device <NUM>, since the surface <NUM> of the epitaxial layer <NUM> is formed of a silicon plane having an off-angle of <NUM> to <NUM> degrees, the gate insulating film <NUM> can be thickened easily during formation through thermal oxidation. This allows the third portion <NUM> in contact with each source region <NUM> to be thickened easily to ensure a required thickness.

Although the embodiment of the present invention has heretofore been described, the present invention can be embodied in still other forms.

The above-described embodiment also exemplifies arranging body regions <NUM> in a matrix, which is illustrative only. For example, the body regions <NUM> may be arranged in a staggered pattern. The body regions <NUM> may also have an elongated (e.g., strip-like) planar shape.

Claim 1:
A semiconductor device comprising:
an SiC substrate (<NUM>) that has a silicon plane having an off-angle of <NUM> to <NUM> degrees;
an n--type epitaxial semiconductor layer (<NUM>) formed on the silicon plane of the SiC substrate (<NUM>) and made of SiC;
p-type body regions (<NUM>) formed in a surficial portion of the semiconductor layer;
a respective p+-type body contact region (<NUM>) formed in a center of a surficial portion of each of the body regions (<NUM>);
a respective n+-type source region (<NUM>) formed in each of the body regions (<NUM>) and surrounded by the surficial portion of the corresponding body region and surrounding the corresponding body contact region (<NUM>);
a gate insulating film (<NUM>) composed of a thermally-oxidized film formed by thermally oxidizing the surface of the semiconductor layer (<NUM>) and provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion (<NUM>) having a lower interface in contact with the semiconductor layer outside the body regions, a second portion (<NUM>) having a lower interface in contact with the body regions, and a third portion (<NUM>) having a lower interface in contact with the source regions; and
a gate electrode (<NUM>) provided on the gate insulating film in an area extending across the semiconductor layer outside the body regions, the body regions, and the source regions, wherein
the third portion (<NUM>) of the gate insulating film (<NUM>) has a third thickness (T3) greater than a first thickness (T1) of the first portion (<NUM>) and a second thickness (T2) of the second portion (<NUM>),
the lower interface of the third portion (<NUM>) is at a position lower than the lower interface of the first portion (<NUM>), and lower than the lower interface of the second portion (<NUM>).