Patent Description:
Power management devices are ubiquitous in today's society and help to power most of the electronic devices we use every day such as phones and laptops. Many of those electronic devices contain batteries and batteries need to be charged. However, charging a battery under less than ideal power conditions can adversely affect the life and performance of the battery. To better control the power delivered to batteries, power management devices such as buck converters have been introduced into charging circuits to help to idealize power conditions under which the battery is being charged.

Most consumer electronic devices that have a battery are designed to be portable, and consumer demand for fast and convenient battery charging solutions has increased. At the same time, device footprints have become smaller leaving less area in the footprint for power management technologies. <CIT> relates to a multiple chargers configuration in one system. <CIT> discloses a voltage conversion apparatus.

To provide convenient charging solutions and compensate for shrinking device footprints, a driver circuit having two high-side switches and a single low-side switch, output inductor, and output capacitor is provided. By having multiple high-side switches, the driver can regulate power from multiple charging devices. However, each of these high-side switches share a channel with an input capacitor for that channel and the channels are connected to the low-side switch at a common node. When the capacitor for one of the channels becomes charged quickly, the capacitor of the other channel will balance itself with the charged capacitor. This balancing may cause a large amount of current to pass through the common node to the uncharged capacitor. The high-side switches along this path cannot withstand such a large current and could be damaged. To avoid damaging the high-side switches, a low-impedance bridge and driver circuit is connected between the channels.

The low-impendence bridge and driver circuit provides a safe path for the large amount of a current that flows during balancing. The low impendence bridge and driver circuit may be, for example, a control circuit connected between a first input capacitor and a first high-side switch and between a second input capacitor and a second high-side switch. The low impedance bridge and driver circuit may have, for example, a first enable switch and a second enable switch connected in series. A terminal of the first enable switch may be connected between the first input capacitor and the first high-side switch and a terminal of the second enable switch may be connected between the second input capacitor and the second high-side switch. The first and second enable switches may be controlled by a logic circuit configured to control the first enable switch and the second enable switch. The control circuit controls the enable switch such that they prevent current from passing through the first and second high-side switches in response to the voltage across the first input capacitor being different from the voltage across the second input capacitor.

The drawings are not necessarily drawn to scale. For example, the dimensions and/or relative positioning of some of the elements in the drawings may be exaggerated relative to other elements to help to improve understanding of various embodiments. Also, conventional elements that are useful or necessary in a commercially feasible embodiment are often not depicted to facilitate a less obstructed view of these various embodiments. Certain actions and/or steps may be described or depicted in a particular order of occurrence although such specificity with respect to sequence may or may not be required.

<FIG> illustrates a circuit diagram of a dual input charger apparatus having inputs terminals VBUS1 <NUM> and VBUS2 <NUM>. The input terminals VBUS1 <NUM> and VBUS2 120may connect to different power sources such as a USB port, an inductive or wireless charging technology, or a charging plug such as one that plugs into a wall outlet. Power flow from the input terminals VBUS1 <NUM> and VBUS2 <NUM> can be connected or disconnected by input switches SW_IN1 <NUM> and SW_IN2 <NUM>. The ability to connect or disconnect the power flow from a specific power source using input switches SW_IN1 <NUM> and SW_IN2 <NUM> allows the dual input charger apparatus to switch between power sources. When either input switch SW_IN1 <NUM> or SW_IN2 <NUM> is closed, the respective input terminal is powering the remainder of the dual input charger circuit. Input capacitors PMID_CAP1 <NUM> and PMID_CAP2 <NUM> smooth the voltage from the input terminals VBUS1 <NUM> and VBUS2 <NUM>. High-side switches SW_HS1 <NUM> and SW_HS2 <NUM> connect at a common node <NUM> to both the low-side switch SW_LS <NUM> and the output inductor <NUM>. The path from input terminal VBUS1 <NUM> through high-side switch SW_HS1 <NUM> to common node <NUM> forms a first channel. The path from input terminal VBUS2 <NUM> through high-side switch SW_HS2 <NUM> to common node <NUM> forms a second channel. Connecting the first and second channel at common node <NUM> allows the dual input charging devices to regulate power from multiple sources without having to duplicate SW_LS <NUM>, output inductor <NUM>, and output capacitor <NUM>. The power flowing through either channel to the output terminal VOUT <NUM> is pulse width modulated by controlling its respective high-side switch to regulate the voltage provided at the output terminal VOUT <NUM>. The output capacitor <NUM> acts to smooth the voltage provided at the output terminal VOUT <NUM>.

A control circuit <NUM> connects between the first and second channels. The control circuit <NUM> has two switches <NUM>(a) and <NUM>(b). As illustrated in <FIG>, the switches <NUM>(a) and <NUM>(b) may be implemented using N-type field effect transistors ("NFET") <NUM>(a) and <NUM>(b). The NFET transistors <NUM>(a) and <NUM>(b) may be, for example, laterally diffused metal oxide semiconductor field effect transistors ("LDMOS") or other metal oxide semiconductor ("MOS") type transistors. <FIG> further illustrates high-side driver circuits HS_Driver1 <NUM> and HS_Driver2 <NUM> and low-side driver circuit LS_Driver2 <NUM>. The high-side driver circuits, HS_Driver1 <NUM> and HS_Driver2 <NUM>, drive the high-side switches, SW_HS1 <NUM> and SW_HS2 <NUM>, by controlling the voltage to the gate of each of the high-side switches. The low-side driver circuit LS_Driver2 <NUM> drives the low-side switch <NUM> by controlling the voltage to the gate of the low-side switch <NUM>.

<FIG> illustrates current flow along current paths I1 <NUM>,<NUM><NUM>, and I3 <NUM> through the dual input driver circuit when the voltage across the input capacitor PMID_CAP1 <NUM> is larger than the voltage across the input capacitor PMID_CAP2 <NUM>. Similarly, current may flow in the direction opposite that illustrate and along current path I1 <NUM>, I2 <NUM>, and I3 <NUM> when the voltage across the input capacitor PMID_CAP2 <NUM> is larger than the voltage across the input capacitor PMID_CAP1 <NUM>. The current path I1 provides a safe path for excess current caused by the voltage imbalance between PMID_CAP1 <NUM> and PMID_CAP2 <NUM> to flow. Without the control circuit <NUM> the sum of the currents flowing through current paths I1 <NUM> and the I2 <NUM> would flow along the current path I2 <NUM>. Such a large current flowing through the current path I2 <NUM> will cause burnout of the high-side switch SW_HS1 and the high-side switch SW_HS2 <NUM> and reduce their useful life.

The ability to shunt the current that would have flowed through the current path I2 and instead cause it to flow along the current path I1 is controlled by turning NFET transistors <NUM>(a) and <NUM>(b) on and off using their respective enable signals EN_VBUS1 <NUM> and EN_VBUS2 <NUM>. The NFET transistors <NUM>(a) and <NUM>(b) have their source shorted to their body and have an intrinsic body diode between the body and the drain. The back-to-back intrinsic body diodes of NFET transistors <NUM>(a) and <NUM>(b) ensures no flows current flows through the control circuit <NUM> when the voltage level of either EN_VBUS1 <NUM> and EN_VBUS2 <NUM> is too low to overcome the threshold voltage of the NFET transistors <NUM>(a) and <NUM>(b) and cause them to conduct current. When the voltage across the input capacitor PMID_CAP1 <NUM> is greater than the voltage across the input capacitor PMID_CAP2 <NUM>, and when the high-side switch SW_HS1 <NUM> is on, the control circuit <NUM> will increase the gate to source voltage of the NFET transistor <NUM>(a) causing the current to along current path I1 <NUM> and limiting the current I2 <NUM> flowing through the high-side transistors SW_HS1 <NUM> and SW_HS2 <NUM>. Similarly, when the voltage across the input capacitor PMID_CAP2 <NUM> is greater than the voltage across the input capacitor PMID_CAP1 <NUM>, and when the high-side switch SW_HS1 <NUM> is on, the control circuit <NUM> will increase the gate to source voltage of the NFET transistor <NUM>(b) causing the current to along current path I1 <NUM> and limiting the current I2 <NUM> flowing through the high-side transistors SW_HS <NUM><NUM> and SW_HS2 <NUM>.

<FIG> illustrates details of the control circuit <NUM>. The NFET transistor <NUM>(a) is driven by driver circuit <NUM>(a), and the NFET transistor <NUM>(b) is driven by driver circuit <NUM>(b). The driver circuits <NUM>(a) and <NUM>(b) determine the gate to source voltage of the NFET transistors <NUM>(a) and <NUM>(b). The gate to source voltage of the NFET transistor <NUM>(a) is determined by the voltage between EN_VBUS <NUM> and VCEN <NUM> of the driver <NUM>(a), and the gate to source voltage of the NFET transistor <NUM>(b) is determined by the voltage between EN_VBUS2 <NUM> and VCEN <NUM> of the driver circuit <NUM>(b) control the gate to source voltage across the NFET transistor <NUM>(b). The input VCP1 voltage <NUM> to the driver <NUM>(a) is a boosted voltage signal that is the sum of the input voltage VBUS1 <NUM> and a constant voltage value such as, for example, six volts. The input voltage VCP2 <NUM> to the driver <NUM>(b) is a boosted voltage signal that is the sum of the input voltage at input terminal VBUS2 <NUM> and a constant voltage value such as, for example, six volts. As described in detail below, the signals EN1_5V and EN2_5V control the logic state of the drivers <NUM>(a) and <NUM>(b).

<FIG> illustrates a circuit diagram of the drivers <NUM>(a) and <NUM>(b). The drivers <NUM>(a) and <NUM>(b) are substantially identical. The following description will describe only the driver <NUM>(a) for brevity. An output circuit <NUM> regulates the gate to source voltage of an NFET transistor <NUM>(a). The output circuit <NUM> has a Zener diode <NUM> connected in series with a resistor <NUM>. The NFET transistor <NUM> and output capacitor <NUM> are arranged in parallel with the series connected Zener diode <NUM> and resistor <NUM>. The voltage across the output capacitor <NUM> represents the gate-to-source voltage (VDS) of the NFET transistor <NUM>(a). The voltage across the capacitor may vary from seven volts to negative seven tenths of a volt. The negative voltage ensures that the NFET transistors <NUM>(a) and <NUM>(b) fully turn off. For example, the negative voltage ensures that the NFET transistor <NUM>(a) is fully turned off when the enable signal EN_5V <NUM> is logic LOW.

When the enable signal EN_5V <NUM> logic is LOW, the sink switch <NUM> is closed and the sinking ten micro-amp source <NUM> in sinking circuit <NUM> will lower the gate to source voltage of the NFET <NUM>(a) to stop current from flowing through the NFET transistor <NUM>(a) along current path I1 <NUM>. In this case, current flows through the resistor <NUM> and then the Zener diode <NUM> and finally through the node <NUM> to ground. When the enable signal EN_5V <NUM> is logic HIGH, the Zener diode <NUM> will also be served as protection to clamp EN_VBUS <NUM> so that it will not exceed VCEN <NUM> plus six volts. The enable main signalcontrols the switch <NUM> and can interrupt the normal operation of the driver <NUM>(a) and pull the NFET transistor <NUM>(a) low. The NFET transistor <NUM> serves to conduct current from VCEN <NUM> to the node <NUM>. The diode <NUM> prevents current from flowing from the node <NUM> in the direction of the PFET (P-type field effect transistor) control transistor <NUM>.

When the enable signal EN_5V <NUM> is logic HIGH, the sink switch <NUM> is open and the capacitor <NUM> of the output circuit <NUM> is charged by a sourcing two mirco-amp current flowing through the node <NUM> from the sourcing circuit <NUM>. The two micro-amp current will increase the voltage across the capacitor <NUM> and in turn increase the gate to source voltage of the NFET transistor <NUM>(a). When the gate to source voltage of the NFET transistor <NUM>(a) exceeds its threshold voltage, current will be able to flow through the channel of the NFET transistor <NUM>(a) along current path I1 to prevent large currents from flowing through the high-side switches <NUM> and <NUM>.

The sourcing circuit <NUM> includes PFET transistors <NUM> and <NUM>. When enable signal EN_5V <NUM> is logic HIGH, the switch <NUM> is closed. While enable signal EN_5V <NUM> is logic HIGH, the current sink <NUM> causes the PFET transistors <NUM> and <NUM> to turn on and induces current to flow through the node <NUM>. The induced current flows into the sourcing circuit <NUM> at node <NUM> from the high-voltage level shifter circuit <NUM>. A portion of the current flows through the PFET transistor <NUM>, and a portion of the current flows through the PFET transistor <NUM>. The PFET control transistor <NUM> controls the current through the node <NUM> that charges the capacitor <NUM> causing the NFET transistor <NUM>(a) to turn on and allow current to flow along current path I1 through the channel of the NFET transistor <NUM>(a) to balance the voltage of the input capacitor PMID_CAP2 <NUM> with the voltage of the input capacitor PMID_CAP1 <NUM>. As the NFET transistor <NUM>(a) becomes fully turned on, the Isource current flowing through the node <NUM> becomes zero. This reduces quiescent current consumption of the driver circuit <NUM>(a) and provides soft-start behavior for turning on the NFET transistor <NUM>(a). The PFET control transistor <NUM> acts as a control switch connecting and disconnecting the Isource current to and from the output circuit <NUM>.

The high-voltage level shifter circuit <NUM> controls the voltage to the gate of the PFET control transistor <NUM> by level shifting the enable signal EN_5V <NUM>. The high-voltage level shifter circuit shifts the enable signal EN_5V <NUM> to a value between the VCP1 voltage <NUM> and the bias voltage <NUM>. The output of the high-voltage level shifter circuit <NUM> to the PFET control transistor <NUM> can be thought of digital signal having a logic HIGH value corresponding to VCP1 voltage <NUM> and a logic LOW value corresponding to the bias voltage <NUM>. The sources of the PFET transistor <NUM> and PFET transistor <NUM> are connected to the VCP1 voltage <NUM>. The gate of the PFET transistor <NUM> is connected to the drain of PFET transistor <NUM> and the source of the PFET transistor <NUM>. The gate of the PFET transistor <NUM> is connected to the drain of PFET transistor <NUM> and the source of the PFET transistor <NUM>. The drains of the PFET transistors <NUM> and <NUM> are controllable connected to ground. The switch <NUM> controls the connection between the drain of the PFET transistor <NUM> and ground. The switch <NUM> controls the connection between the drain of the PFET transistor <NUM> and ground. The drains of the PFET transistor <NUM> and <NUM> will not be connected to ground at the same time because the EN_5V signal causes the switch <NUM> to be closed and the switch <NUM> to be open when the enable signal EN_5V <NUM> is logic HIGH. The switch <NUM> is open when the enable signal EN_5V <NUM> is logic HIGH because the logic is inverted by inverter <NUM>. PFET transistors <NUM> and <NUM> are used to clamp the voltage at the drain of PFET transistors <NUM> and <NUM> respectively. When switch <NUM> is closed, the drain voltage of PFET transistor <NUM> will decrease until the gate to source voltage of the PFET transistor <NUM> becomes zero. When the gate to source voltage of the PFET transistor <NUM> becomes zero, the drain voltage of the PFET transistor <NUM> is clamped to the bias voltage <NUM>. Meanwhile, because the switch <NUM> is opened, the drain voltage of PFET transistor <NUM> will be pulled up to the VCP1 voltage <NUM>. At the same time, the gate voltage of PFET transistor <NUM> is decreased, clamping the drain of PFET transistor <NUM> to the VCP1 voltage <NUM>.

When the enable signal EN_5V <NUM> is logic HIGH, the switch <NUM> is open, and the high-voltage level shifter circuit <NUM> outputs a logic LOW value corresponding to VCP-6V. When the output of the high-voltage level circuit <NUM> to the PFET control transistor <NUM> is logic LOW, the PFET control transistor <NUM> is turned on, and current Isource flows through to charge up node <NUM> towards VCP1 voltage <NUM>.

When the enable signal EN-5V <NUM> signal is logic LOW, the switch <NUM> is closed, and the high-voltage level circuit <NUM> outputs a logic HIGH value corresponding to VCP1 voltage <NUM>. When the output of the high-voltage level circuit <NUM> to the PFET control transistor <NUM> is logic HIGH, the PFET control transistor <NUM> is off, and no current may flow through to node <NUM>.

The NFET transistors <NUM> and <NUM> further protect and clamp the drain of PFET transistors <NUM> and <NUM>. A bias voltage <NUM> is supplied to the gates of the PFET transistors <NUM>, <NUM>, <NUM> and <NUM>. The bias voltage <NUM> is also supplied to the body of the NFET transistors <NUM> and <NUM>. This configuration allows the NFET transistors to prevent the voltage to the drains of PFET transistors 501and <NUM> from dropping too low. If the voltage at the drain of the PFET control transistor <NUM> falls more than one voltage threshold below the bias voltage <NUM>, the NFET transistor <NUM> will turn on and prevent the drain from falling more than one voltage threshold below the bias voltage <NUM>. The voltage threshold corresponds to the voltage threshold of the intrinsic body diode of the NFET transistor <NUM> and is typically around seven tenths of a volt.

Similarly, the NFET transistor <NUM> will prevent the voltage at the gates of the PFET transistors <NUM> and <NUM> from dropping too low. If the voltage at the gate of the PFET control transistor <NUM> falls more than voltage threshold below the bias voltage <NUM>, the NFET transistor <NUM> will turn on and prevent the gate from falling more than one voltage threshold below the bias voltage <NUM>. In this case, the voltage threshold corresponds to the voltage threshold of the intrinsic body diode of the NFET transistor <NUM>.

So configured, a charging device can automatically re-route current based on the voltages present at different ports to reduce likelihood of damaging circuit components within the device due to excessive current flows.

Claim 1:
<NUM>. A dual input charger apparatus comprising:
_a first channel, connected to a first charging port and to which a first input capacitor (PMID_CAP1) and a first terminal of a first high-side switch (SW_HS <NUM>) are connected at a common node;
_a second channel, connected to a second charging port and to which a second input capacitor (PMID_CAP2) and a first terminal of a second high-side switch (SW_HS2) are connected at a further common node;
_wherein the respective two second terminals of the first and second high-side switches (SW_HS <NUM>, SW_HS2) are connected to a common node,
_the dual input charger apparatus further comprising:
_a control circuit (<NUM>) coupled between the common node of the first input capacitor (PMID_CAP1) and the first terminal of the first high-side switch (SW_HS1), and the common node of the second input capacitor (PMID_CAP2) and the first terminal of the second high-side switch (SW_HS2),
wherein control circuit (<NUM>) is configured to shunt a current passing through the first high-side switch (SW_HS1) and the second high-side switch (SW_HS2) in response to a first voltage across the first input capacitor (PMID_CAP1) being different from a second voltage across the second input capacitor (PMID_CAP2).