Patent Description:
Substrate structures for semiconductor integrated circuits, such as power modules, are used to route components internal and external to an integrated circuit and to dissipate heat. Direct bonded copper (DBC) substrates include a ceramic layer with a layer of copper bonded to one or both sides. Insulated metal substrate (IMS) substrates include a metal baseplate covered by a thin layer of dielectric (usually an epoxy-based layer) and a layer of copper.

<CIT>) discloses a circuit device which has a multilayer wiring structure including conductive patterns having different thicknesses, and a manufacturing method thereof.

It is the object of the invention to provide a method of forming an insulated metal substrate (IMS) for a power electronic device.

This object is accomplished by the features of claim <NUM>.

A method of forming an insulated metal substrate (IMS) for a power electronic device has the features of claim <NUM>.

The foregoing and other aspects, features, and advantages will be apparent to those artisans of ordinary skill in the art from the DESCRIPTION and DRAWINGS, and from the CLAIMS.

Implementations will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and:.

This disclosure, its aspects and implementations, are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and/or method elements known in the art consistent with the intended substrate structures and methods of manufacture will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and/or the like as is known in the art for such substrate structures and methods of manufacture, and implementing components and methods, consistent with the intended operation and methods.

Referring now to <FIG>, an implementation of a power electronic substrate <NUM> is illustrated that includes an insulated metal substrate (IMS) <NUM>. The IMS <NUM> has a metallic baseplate <NUM> which may be formed of, by non-limiting example, aluminum, copper, steel, and other heat-conducting materials. The metallic baseplate <NUM> has a first surface <NUM> which is configured to couple to, by non-limiting example, a heat sink, a motherboard, and the like. The metallic baseplate <NUM> has a second surface <NUM> on an opposite (opposing) side from the first surface <NUM>.

A dielectric layer <NUM> is coupled to the metallic baseplate <NUM>. The dielectric layer <NUM> has a first surface <NUM> which is coupled to the second surface <NUM> of the metallic baseplate <NUM> and a second surface <NUM> on an opposite side of the dielectric layer <NUM> from the first surface <NUM>. In various implementations the dielectric layer <NUM> includes a resin or epoxy <NUM>, though in other implementations it may include other dielectric (electrically insulative) materials.

A plurality of traces <NUM> are formed and coupled to the dielectric layer <NUM>. Each trace <NUM> has a first surface <NUM> coupled to the second surface <NUM> of the dielectric layer <NUM> and a first surface <NUM> on an opposite side of the trace <NUM> from the first surface <NUM>. The traces <NUM> are metallic and may be formed of, by non-limiting example, copper, aluminum, or other electrically conductive materials. Some of the traces <NUM> have a first thickness <NUM>, measured from the first surface <NUM> to the second surface <NUM>, and some of the traces <NUM> have a second thickness <NUM>, greater than the first thickness <NUM>, measured from the first surface <NUM> to the second surface <NUM>. In some implementations there could be traces <NUM> having a third thickness sized differently from both the first thickness <NUM> and second thickness <NUM> or other traces that contain both the first thickness and the second thickness. Referring to <FIG>, the difference in thicknesses is created at least in part by a pattern <NUM> which is formed in a first surface <NUM> of a copper layer <NUM> from which the traces <NUM> are formed, which will be discussed hereafter, and the traces <NUM> which have the smaller first thickness <NUM> correspond with the pattern <NUM> or, in other words, are located at the pattern <NUM> or formed of the material that composes the pattern <NUM>. Referring back to <FIG>, a layer of nickel <NUM> is included on the second surface <NUM> of each metallic trace <NUM>. In implementations a single trace <NUM> may have different thicknesses in different places and so may include the first thickness <NUM>, second thickness <NUM>, a third thickness, and so on. A trace <NUM> of this nature is illustrated in <FIG>.

Referring now to <FIG>, in particular implementations a power electronic substrate <NUM> is an IMS <NUM> that is similar in structure to IMS <NUM> except the traces lack the nickel <NUM> atop the traces <NUM>.

Referring now to <FIG>, implementations of a power electronic substrate <NUM> that are direct bonded copper (DBC) substrates are illustrated. The DBC substrate <NUM> has a metallic baseplate <NUM> which may be formed of, by non-limiting example, copper, aluminum, steel, and the like. The metallic baseplate <NUM> has a first surface <NUM> configured to be coupled to, by non-limiting example, a heat sink, a motherboard, and the like, and further has a second surface <NUM> on an opposite side of the metallic baseplate <NUM> from the first surface <NUM>. A first surface <NUM> of a ceramic layer <NUM> is coupled to the second surface <NUM> of the metallic baseplate <NUM>. The ceramic layer <NUM> has a second surface <NUM> on an opposite side of the ceramic layer <NUM> from the first surface <NUM>. A pattern <NUM> is formed in the second surface <NUM> of the ceramic layer <NUM> which may be formed, by non-limiting example, with a number of patterning techniques used to etch and shape ceramic materials. The ceramic layer <NUM> may be half-etched, though in implementations the etching may go more or less than halfway through the ceramic layer <NUM>. The etching may be accomplished through wet-etching techniques. In other implementations, the ceramic layer <NUM> may be patterned through printing, molding, or stamping when the ceramic material is still soft and pliable before curing, firing, or sintering of the layer has taken place.

The DBC substrate <NUM> has a plurality of traces <NUM> similar to IMS <NUM>. The traces <NUM> having the larger second thickness <NUM>, measured between the first surface <NUM> and second surface <NUM>, correspond with the pattern <NUM>, or in other words are located at or formed from the pattern <NUM>. A layer of nickel <NUM> is placed atop each trace <NUM>, similar to IMS <NUM>. which may be plated onto the traces <NUM>.

Referring now to <FIG>, in implementations a power electronic substrate <NUM> is a DBC substrate <NUM> that is similar to DBC substrate <NUM> except it lacks the nickel layer <NUM>.

Referring now to <FIG>, a method of forming an IMS <NUM> is illustrated. A copper layer <NUM> is first processed where the copper layer <NUM> has a first surface <NUM> and a second surface <NUM> on an opposite side of the copper layer <NUM> from the first surface <NUM>. A layer of photoresist <NUM> is placed on the first surface <NUM> and another layer of photoresist <NUM> is placed on the second surface <NUM>. A pattern is formed in the photoresist <NUM> on the first surface <NUM>, as seen in <FIG>. This may be done by exposing a portion of the photoresist <NUM> to ultraviolet (UV) light or other exposure techniques which make a portion of the photoresist <NUM> more resistant (or more susceptible) to being removed, and then developing the photoresist <NUM> with a solution that removes the treated (or untreated) portion to form the pattern.

While only a single part of the pattern is shown, it may be understood that <FIG> is a close-up view of only a portion of the elements, and that in reality a pattern of traces and other shapes may be formed in the photoresist <NUM>. An etching process is then used to etch a pattern <NUM> into the first surface <NUM> of the copper layer <NUM> through the spaces formed in the photoresist <NUM>. This may be done using any conventional etching mechanisms used to etch copper. The formation of the pattern <NUM> forms locations of the copper layer <NUM> that have the first thickness <NUM> and other locations that have the second thickness <NUM>, the smaller first thickness <NUM> corresponding with the patterned areas where the first surface <NUM> has been etched. It can be seen from <FIG> that the etching of the copper layer <NUM> is a partial etch which does not go all the way through to the second surface <NUM>. In some implementations, the etching may be half-etched. In other implementations, the pattern <NUM> may be etched more or less than halfway through the copper layer <NUM>.

Referring now to <FIG>, after the pattern <NUM> has been etched into the first surface <NUM> the layers of photoresist <NUM> are removed. It may be understood that the layer of photoresist <NUM> that was placed on the second surface <NUM> is used to prevent the second surface <NUM> from being etched during the etching process-such as, for instance, in cases where the etching was done with wet etching where the entire copper layer <NUM> was placed in an etching solution. Any of a wide variety of conventional methods for removing the photoresist <NUM> (ashing, solvent cleaning, etc.) may be employed in various implementations.

Referring now to <FIG>, a metallic baseplate <NUM> is illustrated that has a first surface <NUM> and second surface <NUM> as previously described. A dielectric layer <NUM> having first surface <NUM> and second surface <NUM> is also provided, which in the implementation shown includes an epoxy <NUM>. The copper layer <NUM> is positioned so that its first surface <NUM> faces the second surface <NUM> of the dielectric layer <NUM>.

Referring now to <FIG>, the copper layer <NUM>, dielectric layer <NUM>, and metallic baseplate <NUM> are illustrated after having been coupled together through a laminating or other pressure bonding process that presses the layers together. During the bonding step, the dielectric layer <NUM> flows under the pressure forces during this step of assembly and accommodates the pattern <NUM>, as seen in <FIG>, embedding the pattern <NUM> into the dielectric layer <NUM>. This bonding/laminating step forms a complementary, or substantially complementary pattern, to the pattern <NUM> in the dielectric layer <NUM>.

Referring to <FIG>, a layer of nickel <NUM> is plated or otherwise deposited onto the copper layer <NUM>. As illustrated in <FIG>, a first layer <NUM> of photoresist <NUM> is placed atop the nickel <NUM> and a pattern <NUM> is formed therein. While only one space of the pattern <NUM> is shown, it may be understood that this is a close-up view showing only a small portion of the elements, so that in reality a number of patterned areas may be formed in the first layer <NUM> of photoresist <NUM>. The nickel plating <NUM> and copper layer <NUM> are then fully etched down to the dielectric layer <NUM> at the pattern <NUM> and then the first layer <NUM> of photoresist <NUM> is removed, as seen in <FIG>.

A second layer <NUM> of photoresist <NUM> is then coated onto the elements as shown in <FIG> and a second pattern <NUM> is formed therein. Although only a single space of the pattern <NUM> is shown, it may be understood that a number of spaces may be formed therein. The nickel layer <NUM> and copper layer <NUM> are then fully etched through down to the dielectric layer at the pattern <NUM> to form the traces <NUM> and the second layer <NUM> of photoresist <NUM> is removed. Some of the traces <NUM> have the first thickness <NUM> and some have the second thickness <NUM>-and in the implementation shown some have both the first thickness <NUM> and second thickness <NUM>.

It may be perceived that a slightly modified version of this process may be used to form IMS <NUM> illustrated in <FIG>, wherein the step of adding the nickel <NUM> is unnecessary and the etching processes to form the traces <NUM> accordingly do not involve etching through the nickel <NUM>. It may also be understood that the process could be slightly modified to form traces <NUM> of more than two thicknesses. By non-limiting example, layers of photoresist <NUM> could be coated onto the copper layer <NUM> shown in <FIG>, a pattern formed therein, and an etching process may then be used to etch a second pattern into the copper layer <NUM>, which if etched to a different depth in the copper layer <NUM>, may be used to form a third thickness in the copper layer <NUM> different than the first thickness <NUM> and second thickness <NUM>. This process could be repeated numerous times to form many thicknesses in the copper layer <NUM>. This may be done with the second surface <NUM> of the copper layer <NUM> remaining flat and, accordingly, the remaining process steps are identical or fairly identical to those described previously.

<FIG> show a process of forming DBC substrate <NUM>, which in some aspects is similar to the process described above for forming IMS <NUM>, as it involves patterning a layer of copper as was previously described for use in subsequent processing. As A pattern <NUM> is formed in the first surface <NUM> of the copper layer <NUM> as already described in this document. With respect to shaping the ceramic layer, a pattern <NUM> is formed in the second surface <NUM> of the ceramic layer <NUM> which is complementary, or substantially complementary, to the pattern <NUM> in the copper layer <NUM>. The pattern <NUM> in the ceramic layer <NUM> may be formed using any of a variety of techniques for etching or shaping ceramic materials, including photoresist masking and dry or wet etching, or through stamping/forming processes prior to the ceramic material being cured/dried/fired/sintered. As shown in <FIG>, the copper layer <NUM>, ceramic layer <NUM> and metallic baseplate <NUM> are bonded together through a sintering or other similar process used to form intermetallic or other bonding layers between the copper and the ceramic material. A layer of nickel <NUM> is coupled atop the copper layer <NUM>, through electroplating or deposition as shown in <FIG>, and atop this a first layer <NUM> of photoresist <NUM> is added as shown in <FIG>. A pattern <NUM> is formed in the first layer <NUM>, as shown in <FIG>. As described above, although only a single space is formed there may be a plurality of spaces in the pattern <NUM>. The nickel <NUM> and copper layer <NUM> are fully etched through at the gap <NUM>, revealing the ceramic layer <NUM>, and the first layer <NUM> of photoresist <NUM> is then removed, as illustrated in <FIG>.

A second layer <NUM> of photoresist <NUM> is then added to the elements as shown in <FIG> and a pattern <NUM> is formed therein, as seen in <FIG>. Again, there may be a plurality of spaces composed in the pattern <NUM>. The nickel layer <NUM> and copper layer <NUM> are fully etched through at the pattern down to the ceramic layer <NUM> to form the traces <NUM>, and the second layer <NUM> of photoresist <NUM> is removed. Some traces <NUM> have the first thickness <NUM> and some have the second thickness <NUM> and, if desired, the process may be used to form some traces <NUM> having both thicknesses, as illustrated in <FIG>. As with other processes described above, there may be more than two trace thicknesses by making slight modifications to the process as described above with respect to the process for forming IMS <NUM> to shape the copper layer <NUM>. A process for forming DBC substrate <NUM> may be similar in many respects to the process for forming DBC substrate <NUM> except that the nickel plating <NUM> is not included (and, accordingly, is not etched through).

<FIG> illustrates a power electronic substrate <NUM> that can be considered a hybrid as it has some elements similar to an IMS and some elements similar to a DBC substrate. A metallic baseplate <NUM> is used, having the first surface <NUM> and second surface <NUM> as previously described. There are two dielectric layers <NUM> and <NUM>, and a ceramic layer <NUM> is sandwiched therebetween. The second dielectric layer <NUM> has a first surface <NUM>, on an opposite side from a second surface <NUM>, the first surface <NUM> being bonded to the second surface <NUM> of the metallic baseplate <NUM>.

A first surface <NUM> of the ceramic layer <NUM> has a bonding pattern <NUM> thereon. This may include bonding ridges <NUM>, conical projections <NUM>, pyramidal projections <NUM>, and the like dispersed on the first surface <NUM> of the ceramic layer. Other patterns and/or shapes may be employed to increase the surface area and/or the surface interaction between the ceramic layer <NUM> and the dielectric material. Referring to <FIG> (and the page on which the drawing is presented) the bonding pattern <NUM> may include a series of discrete elements that extend through the surface of the page (such as a grid or array of individual projections when viewed from above) and/or rows extending through the page surface. The second surface <NUM> of the second dielectric layer <NUM> receives the bonding pattern <NUM>. This may be accomplished by the second dielectric layer <NUM> behaving as a fluid when it is being bonded to the ceramic layer <NUM> via a laminating or other pressure process inducing localized flow of the dielectric material to effectively form a pattern that is complementary, or substantially complementary, to the bonding pattern <NUM>. The second dielectric layer <NUM> may be formed of an epoxy <NUM>, and the bonding pattern <NUM> may assist the epoxy <NUM> to bond sufficiently to the ceramic layer <NUM>.

A second surface <NUM> of the ceramic layer <NUM> opposite the first surface <NUM> also includes a bonding pattern <NUM>, which may include any features or characteristics previously described with respect to bonding pattern <NUM>, and may include bonding ridges <NUM>, conical projections <NUM>, pyramidal projections <NUM>, and the like. Other patterns and/or shapes may be used. The first surface <NUM> of the first dielectric layer <NUM> receives the bonding pattern <NUM> and, accordingly, forms a complementary or substantially complementary pattern on the first surface <NUM>. The first dielectric layer <NUM> may have any of the characteristics, features, and so forth of the second dielectric layer <NUM>. A second surface <NUM> of the first dielectric layer <NUM>, opposite the first surface <NUM>, is bonded to a copper layer <NUM>.

<FIG> is a view of the power electronic substrate <NUM> shown at a lesser degree of magnification so that the bonding patterns <NUM>, <NUM> is not visible. Traces <NUM> may be formed in the copper layer <NUM> at this point, in a similar manner as described above with respect to other power electronic substrates. The power electronic substrate <NUM> may have a copper layer <NUM> (and accordingly, traces <NUM>) of a uniform thickness, or the copper layer <NUM> may have a pattern <NUM> therein and the ceramic layer <NUM> may have a pattern <NUM> therein, as seen in <FIG>, that is complementary, or substantially complementary, to pattern <NUM> (and may be formed through etching processes as described herein) so that there will be traces <NUM> of varying thicknesses, which may be formed using techniques already described with respect to other power electronic substrates herein. In other implementations, however, the traces <NUM> may be formed without varying thicknesses.

In implementations of power electronic substrates disclosed herein which use an epoxy or resin for the dielectric layer, the dielectric layer may have a thickness from its first surface to its second surface of, or of about, <NUM> microns to, or to about, <NUM> microns. The epoxy or resin may include thermally conductive filler particles, such as by non-limiting example SiO<NUM>, Al<NUM>O<NUM>, BN, or the like, dispersed therein. Copper layers described herein may be copper foil and may have, by non-limiting example, thicknesses ranging from, or from about, <NUM> microns to, or to about <NUM> microns, or greater. In implementations in which the metallic baseplates are formed of aluminum they may have an alumite and/or anodized aluminum layer on the first and second surfaces. Some metallic baseplates may have, by non-limiting example, a thickness from the first surface to the second surface of, or of about, <NUM>.

In implementations herein in which a ceramic layer is used the ceramic layer may include, by non-limiting example, alumina, aluminum nitride, and other high thermally conductive ceramic or composite materials. A copper layer may be directly bonded to a ceramic layer using a high-temperature oxidation process wherein the copper and ceramic are heated to a controlled temperature in a nitrogen atmosphere containing about <NUM> ppm of oxygen (or about <NUM>% concentration of O<NUM> in atom percentage) to form a copper-oxygen eutectic which bonds both to the copper and to an oxide of the ceramic layer. In implementations the ceramic layer may be Al<NUM>O<NUM> and a thin layer of copper-aluminum-spinel may bond the copper layer to the ceramic layer. In implementations the ceramic layer may be aluminum nitride and a thin layer of copper-aluminum-nitride may be formed by first oxidizing the surface of the aluminum nitride to form a layer of alumina by high temperature oxidation. In implementations a copper layer may be bonded to a ceramic layer using a sintering process. In particular implementations, the sintering process may involve melting or softening small particles comprised in each of the copper layer and the ceramic layer to bond them with adjacent small particles. By small in this process is meant microscopic particles.

The hybrid power electronic substrate <NUM> shown in <FIG>, due to the lack of a direct copper-to-ceramic bond, eliminates the need for the high temperature bonding processes described above. In addition, because there is no need for a high temperature bonding or other sintering process, the substrate <NUM> including a ceramic layer can be formed using laminating or other pressure bonding processes.

Implementations of IMS panels prior to singulation may have sizes of, or of about, <NUM> square meter, and may have the form of a square or of a rectangle. Implementations of DBC substrate panels prior to singulation may be wafer-shaped and may have sizes of, or of about, <NUM> inches by <NUM> inches.

Implementations of power electronic substrates disclosed herein may be used, by non-limiting example, as substrates for insulated gate bipolar transistor (IGBT) power modules, intelligent power modules (IPMs), power integrated modules (PIMs), power metal-oxide-semiconductor field-effect-transistors (MOSFETs), and the like. In implementations terminals of a semiconductor package may be formed of the copper layers described herein. Packages formed using the power electronic substrates disclosed herein may include top leads, side leads, down leads, glass to metal seals, surface mounts, liquid cooling, and the like.

PIM products may use DBC substrates with thicker copper trace thicknesses while IPM products may use IMS substrates with thinner copper trace thicknesses. Thinner copper traces are better for fine line space for routing while thicker copper traces are better for thermal and electrical performance for power electronic devices. In implementations the power electronic substrates disclosed herein may allow both of these advantages to be realized on a single substrate. In such implementations the thicker copper traces are used for power lines for power electronics while the thinner copper traces may be used for the rest of the circuitry with fine line spacing, and/or for fine pitch circuitry, such as for one or more drivers. The use of some thinner copper traces may reduce overall substrate stress.

In particular implementations a leadframe of a power electronic device may be bonded to the top layer (copper or nickel) of a power electronic substrate described herein. This may be done, in implementations, using a solder, such as by non-limiting example an Sn/Ag/Cu solder.

As may be envisioned, the process of forming an IMS shown in <FIG> may be followed up by additional steps to form a stacked IMS. By non-limiting example, a second dielectric layer may be laminated over the traces (and nickel plating, if present) and a second copper layer (having a pattern therein, or not) may then be coupled to the second dielectric layer, with traces later formed in the second copper layer to form the stacked IMS for a power electronic, these later traces having, if desired, multiple thicknesses as previously described with respect to other traces.

Implementations of substrates disclosed herein may utilize principles disclosed in <CIT>, titled "Hybrid Integrated Circuit Device". Furthermore, forming ground connections to substrates as illustrated in that reference, such as, by non-limited example shown in FIG. 1B of that reference, may be incorporated into power electronic substrate designs disclosed herein. Forming such connections may be accomplished, by non-limited example, by etching or otherwise forming a through-hole through the dielectric material, ceramic layer, or other insulative layer during processing, using methods disclosed herein, and then coupling an electrical contact on a surface of a die to a grounded metallic baseplate using a wirebond or the like.

Furthermore, substrate implementations like those disclosed herein by use the principles disclosed in <CIT>, titled "Semiconductor Device and Hybrid Integrated Circuit Device". Implementations of power electronic substrates disclosed herein may be used to form hybrid integrated circuit (HIC) devices such as those disclosed in that reference. The "fused leads" of an HIC package as shown in that reference, such as by non-limiting example those shown in FIG. 6B (elements <NUM>, <NUM>) of that reference, may be formed of the same copper layer that is used to make the traces <NUM> described herein.

Substrate implementations like those may be formed employing the principles disclosed in <CIT>, titled "Method of Manufacturing Circuit Device". The methods disclosed therein of attaching a leadframe to multiple substrates (or in other words to a single panel containing multiple non-singulated substrates prior to singulation), to then be singulated, such as by non-limiting example the elements shown in FIG. 3A of that reference, may be incorporated in and/or used together with power electronic devices disclosed herein.

Implementations of substrates like those disclosed herein may be formed using the principles disclosed in <CIT>, titled "Circuit Device and Method of Manufacturing the same". Furthermore, packaging multiple HIC substrates within a single package as disclosed in that reference, such as that shown by non-limiting example in FIG. 1B and described in the specification of that reference, may be accomplished in part by forming several power electronic substrates according to methods disclosed herein in a single panel and then singulating each individual power electronic substrate, such as through punch or saw singulation, and interconnecting die and other components between HIC modules as shown in FIG. 1B of that reference.

In various implementations of substrates disclosed herein, the principles disclosed in <CIT>, titled "Advanced copper bonding (ACB) with ceramic substrate technology" may be employed. Any of the bonding techniques disclosed therein with respect to bonding copper layers to ceramic layers may be utilized in forming power electronic substrates disclosed herein including, by non-limiting example: forming a copper film having a thickness of less than <NUM> micron on a ceramic substrate by sputtering deposition under <NUM> torr and <NUM> degrees Celsius; plating a copper layer of <NUM>-<NUM> microns at room temperature, and; bonding a copper foil to the ceramic substrate by diffusion bonding under environments of high temperature, vacuum, and negative pressure inertia gas or H<NUM> partial pressure. In implementations a copper layer may be bonded to an aluminum oxide ceramic layer using methods described herein by heating in a sintering furnace up to <NUM> degrees Celsius (or higher, such as about <NUM> to about <NUM> degrees Celsius) to form the eutectic layer described previously. In implementations no sputtering of copper onto a ceramic layer is needed to form the copper layer.

Implementations of substrates disclosed herein that include a nickel layer may employ the methods and principles disclosed in <CIT>, titled "Circuit Device and Method of Manufacturing the same". Furthermore, any of the elements therein describing nickel plating over copper traces, heat sink elements, and other elements used when attaching a die to a copper trace and/or electrically coupling an electrical contact on the die with one or more traces, such as by non-limiting example the elements shown in FIG. 1C of that reference and related description in the specification thereof, may be incorporated and/or used together with power electronic substrates disclosed herein. Additionally, insulating layers and/or dielectric layers described herein may include any of the elements, characteristics, features and the like of resins and/or insulating layers described in <CIT>.

Implementations of substrates like those disclosed herein may employ the principles disclosed in Japan Patent Application Publication No. <CIT>, titled "Circuit Device and its Manufacturing Process". Furthermore, any of the elements therein that disclose nickel plating over copper traces, heat sink elements, and other elements used when attaching a die to a copper trace and/or electrically coupling an electrical contact on the die with one or more traces, such as by non-limiting example the elements shown in FIG. 1C of that reference and related description in the specification thereof, may be incorporated and/or used together with power electronic substrates disclosed herein. Additionally, insulating layers and/or dielectric layers described herein may include any of the elements, characteristics, features and the like of resins and/or insulating layers described in <CIT>.

Implementations of substrates like those disclosed herein may be manufactured using the principles disclosed in Japan Patent Application Publication No. <CIT>, titled "Hybrid Integrated Circuit Device". Furthermore, any of the v-score techniques applied to the substrates as disclosed therein in at least <FIG> and <FIG>, and related disclosure in the specification thereof, may be applied to and/or used with power electronic substrates disclosed herein to aid with singulation. In implementations such v-scores may be applied to the metallic baseplates described herein. In implementations double v-scores may be utilized wherein a plurality of v-scores are on an underside of the metallic baseplate and a corresponding plurality of v-scores are on the upper side of the metallic baseplate and aligned with the v-scores on the underside of the metallic baseplate to aid with singulation.

Referring to <FIG>, a first implementation of a semiconductor package <NUM> is illustrated. As illustrated, the package <NUM> includes an electrically insulative layer <NUM> (which may be a ceramic layer or an insulated metal substrate) and a metallic baseplate <NUM> coupled thereto at a first surface <NUM> of the layer <NUM>. A plurality of metallic traces <NUM> are coupled to a second surface <NUM> of the electrically insulative layer <NUM>. As can be observed, the some of the plurality of metallic traces have different thicknesses from the others, the thickness being measured perpendicularly to the second surface <NUM> of the electrically insulative layer <NUM>. Each of the plurality of metallic traces <NUM> is formed from one or more layers of metal. In particular implementations, the metal may be one of copper, aluminum, nickel, gold, nickel and gold, and any combination thereof. The shape of the cross section of each trace depends on how many metal layers are included in each trace. Collectively, the metallic baseplate <NUM>, the electrically insulative layer <NUM>, and the plurality of metallic traces <NUM> are referred to as a substrate <NUM> for the semiconductor package <NUM>. Semiconductor devices <NUM>, <NUM> are bonded to the plurality of metallic traces <NUM> at the uppermost exposed metal layer of the traces. Depending on the type of device, wire bonds <NUM>, <NUM> may be used to connect the devices <NUM>, <NUM> to the traces <NUM> or to other devices. Examples of semiconductor devices that could be included in various implementations include power devices, insulated-gate bipolar transistors (IGBTs), diodes, metal oxide semiconductor field effect transistors (MOSFETs), control chips, surface mounted devices (SMDs). The wire bond wires <NUM>, <NUM> may be made of aluminum, copper, or gold, and any alloy of the same. A mold compound <NUM> is included that encapsulates the semiconductor devices <NUM>, <NUM> and at least a portion of the substrate <NUM>. The mold compound may be any disclosed herein and may include silicon-containing gels, epoxies, and any other desired mold compound type. As illustrated, package electrical connectors <NUM> are included which are coupled to the structure of the substrate <NUM>.

The electrically insulative layer <NUM> may be formed of a wide variety of materials including, by non-limiting example, ceramic materials, Al<NUM>O<NUM>, Al<NUM>Si<NUM>. AlN, ZrO<NUM>, and other electrically insulating materials, including those disclosed in this document. The metallic baseplate <NUM> may be a plated first layer of copper or may be a bonded/sintered layer of copper or may be an anodized aluminum or copper layer/piece bonded/plated/sintered/laminated to the electrically insulative layer <NUM>.

First implementations of semiconductor packages may be formed using implementations of a method of forming a semiconductor package, where the metal used is copper (though other etchable and platable metals could be used in various implementations). <FIG> illustrates electrically insulative layer <NUM> with a first surface <NUM> opposing a second surface <NUM>. <FIG> shows the structure that exists after a first copper layer <NUM> has been plated on the second surface <NUM> and a first copper layer <NUM> has been plated on the first surface <NUM>. <FIG> illustrates the structure after the first copper layer <NUM> has been patterned using photoresist or other patterning materials disclosed herein and etched using any of the methods disclosed herein to create traces <NUM> in the layer <NUM>. Implementations of the method include the steps of plating additional copper layers onto the traces <NUM> formed in the first copper layer <NUM> and forming traces in each of the additional layers that correspond with the traces in the first copper layer. This process of plating additional copper layers can take place uniformly across all of the traces <NUM> in the first copper layer <NUM>, or may take place selectively on specific traces using a photoresist patterning and selective plating processes. This process of plating additional copper layers, selectively or uniformly, also can take place on the first copper layer <NUM> plated on the first surface <NUM> of the electrically insulative layer <NUM>.

<FIG> illustrates a substrate <NUM> following plating and patterning of additional copper layers on the first surface <NUM> and the second surface <NUM>. As can be seen, some of the traces <NUM> in the first copper layer <NUM> on the second surface <NUM> remain exposed in selected locations, while other traces have been plated with a second copper layer <NUM>, and some have been plated with a third copper layer <NUM>. By inspection, a width <NUM> of the traces of the second copper layer <NUM> is thinner/smaller than a width of the traces <NUM> of the first copper layer <NUM> (see also the width between numerals <NUM>). Also, by inspection, a width <NUM> of the traces of the third copper layer is also thinner/smaller than a width of the traces of the second copper layer <NUM>. The difference in width on each side of the traces of the second copper layer <NUM> relative to the traces of the first copper layer <NUM> and the difference in width on each side of the traces of the third copper layer <NUM> relative to the traces of the second copper layer <NUM> may be referred to as an offset distance. Because this offset distance is determined during patterning and/or plating of the second copper layer <NUM> and the third copper layer <NUM>, it may be determined and/or calculated. Likewise, the thickness of each of the first, second, third, and any additional layers of copper may be determined and/or calculated based on desired performance characteristics.

In various implementations, the thicknesses of the layers and the offset distances between layers are selected to reduce stresses in the copper layer(s). By non-limiting example, the thickness of the first copper layer may be about <NUM> microns, the thickness of the second layer maybe about <NUM> microns, and the thickness of the third layer may be about <NUM> microns, leading to a total stack thickness of about <NUM> microns. The offset distance between some, any, or all of the copper layers may be about <NUM> microns, about <NUM> microns, about <NUM> microns, or about <NUM> microns. Any of these offset distances could be used between any of the layers, i.e., between the first and second layers, the second and third layers, and the third and fourth layers. In a particularly implementation, the largest offset distance in the trace stack may be between the first and second layers. Such a design may help to reduce the stresses in the copper layers most effectively.

The same process of plating additional layers of copper can be used on the first side <NUM> of the substrate. <FIG> illustrates a first copper layer <NUM> with a second copper layer <NUM> plated over top of it. Because there may not be traces in the first copper layer <NUM>, the patterning done to the second copper layer <NUM> may be just to establish an offset distance <NUM> at the edges of the second copper layer <NUM>. This offset distance <NUM> is established when the distance from the edge of the electrically insulative layer <NUM> to the edge of the first copper layer <NUM> is smaller than the distance from the edge of the electrically insulative layer <NUM> to the edge of the second copper layer <NUM>. More than two copper layers may be used in various implementations, and any of the copper layers on the first side <NUM> may be patterned with traces or other heat conductive features in various implementations.

Because of the receding, stepped shape of the multilayered traces, a specially designed solder print stencil may be required to aid in enabling solder printing to allow for bonding of semiconductor devices and other devices onto the traces. Such a stencil may be a solder paste print stencil rather than a typical solder print stencil that requires the surface of the substrate <NUM> be flat. While the process flow is illustrated in <FIG> as being carried out on a single package level, those of ordinary skill will recognize that the process can be carried out in multiple package sizes as well, including panel and multipanel sizes.

Referring to <FIG>, a second implementation of a semiconductor package <NUM> is illustrated. Similar to the implementation illustrated in <FIG>, the package <NUM> includes various semiconductor devices <NUM>, <NUM> encapsulated in mold compound <NUM>. The devices <NUM>, <NUM> are bonded to traces <NUM>, <NUM>. As can be observed, traces <NUM> have a greater thickness than the traces <NUM> measured in a direction perpendicular to the second surface <NUM> of the electrically insulative layer <NUM>. The package implementation <NUM> illustrated in <FIG> has an electrically insulative layer <NUM> made of an IMS substrate like those disclosed herein and has an anodized aluminum or copper baseplate <NUM> bonded to it. The traces <NUM>, <NUM> are formed using the various methods disclosed herein that use IMS substrates. <FIG> shows how a patterned copper layer <NUM> that has been pre-etched to include at least two different layer thicknesses is positioned above the electrically insulative layer <NUM>. <FIG> illustrates the traces <NUM>, <NUM> following lamination of the patterned copper layer <NUM> with the electrically insulative layer <NUM> and then patterning and etching of the copper layer <NUM>. Since the surface of the traces <NUM>, <NUM> is still flat, unlike the implementation illustrated in <FIG>, a standard solder print stencil can be used. Following creation of the traces <NUM>, <NUM>, the bonding of the various semiconductor devices <NUM>, <NUM>, wire bonding, package electrical connectors/pins bonding and encapsulation can take place using methods like those described in this document.

Referring to <FIG>, a third implementation of a semiconductor package <NUM> is illustrated. Similar to the implementations illustrated in <FIG> and <FIG>, the package <NUM> contains semiconductor devices <NUM>, <NUM> and traces <NUM>, <NUM> which have two different thickness measured perpendicularly to a second surface <NUM> of the electrically insulative layer <NUM>. In the package implementation <NUM>, the electrically insulative layer <NUM> is a ceramic and/or similar material disclosed herein. The process of forming the package is similar to processes described herein that involve similar ceramic-type substrates. Referring to <FIG>, a pre-patterned copper layer <NUM> is shown prior to being engaged with electrically insulative layer <NUM> for sintering. Any of the sintering methods and systems disclosed in this document could be used in various implementations to perform the sintering. <FIG> illustrates the structure of the package <NUM> following sintering and patterning of the pre-patterned copper layer <NUM> to form the traces <NUM>, <NUM>. Following creation of the traces <NUM>, <NUM>, the bonding of the various semiconductor devices <NUM>, <NUM>, wire bonding, package electrical connectors/pins bonding and encapsulation can take place using methods like those described in this document.

Claim 1:
A method of forming an insulated metal substrate (IMS) for a power electronic device, comprising:
partially etching a first surface (<NUM>) of a copper layer (<NUM>) to form a pattern comprising a first thickness (<NUM>) and a second thickness (<NUM>) greater than the first thickness (<NUM>), the first thickness (<NUM>) and the second thickness (<NUM>) both measured perpendicular to a second surface (<NUM>) of the copper layer (<NUM>) opposite the first surface (<NUM>) of the copper layer (<NUM>), the partial etching being made using photoresist (<NUM>);
after removing the photoresist (<NUM>), laminating the first surface (<NUM>) of the copper layer (<NUM>) with a second surface (<NUM>) of a dielectric layer (<NUM>), the dielectric layer (<NUM>) coupled to a metallic baseplate (<NUM>) at a first surface (<NUM>) of the dielectric layer (<NUM>) opposite the second surface (<NUM>) of the dielectric layer (<NUM>) and at a second surface (<NUM>) of the metallic baseplate (<NUM>); and
forming traces (<NUM>) in the copper layer (<NUM>) by etching through the copper layer (<NUM>) at the first thickness (<NUM>) and etching through the copper layer (<NUM>) at the second thickness (<NUM>), wherein the traces (<NUM>) comprise two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the first surface (<NUM>) of the dielectric layer (<NUM>),
wherein etching through the copper layer (<NUM>) at the first thickness (<NUM>) and etching through the copper (<NUM>) layer at the second thickness (<NUM>) comprises coupling a first layer of photoresist (<NUM>) to the second surface (<NUM>) of the copper layer (<NUM>), forming a pattern in the first layer of photoresist (<NUM>), etching through the copper (<NUM>) layer at the first thickness (<NUM>) at spaces in the pattern in the first layer of photoresist (<NUM>), removing the first layer of photoresist (<NUM>), coupling a second layer of photoresist (<NUM>) to the second surface (<NUM>) of the copper layer (<NUM>), forming a pattern in the second layer of photoresist (<NUM>), etching through the copper layer (<NUM>) at the second thickness (<NUM>) at the spaces in the pattern in the second layer of photoresist (<NUM>), and removing the second layer of photoresist (<NUM>).