Patent Description:
Apparatuses for performing diagnostics on memory are known. For example, patent literature (PTL) <NUM> discloses an apparatus for performing diagnostics on a safety mechanism (SM) random access memory (RAM) area of RAM.

<CIT> discloses a method of cyclically performing progressive RAM tests during normal operation of an embedded system.

<CIT> discloses a data storage system configured to perform prioritized memory scanning for memory errors. The data storage system prioritizes scanning for memory errors based on a quality attribute of pages or zones of a non-volatile memory array. Pages or zones having quality attributes that reflect a lower level of reliability or endurance than other pages or zones are scanned more frequently for memory errors. When memory errors are discovered, the quality attribute of pages or zones can be adjusted to reflect a lower level of reliability or endurance. In addition, stored data can be recovered before it may become permanently lost and before a host system reads the stored data.

<CIT> discloses a combustion device and a fuel cell system in which a failure in a control device is detected and upon such failure detection, a fuel cut-off valve can be surely closed. Each of safety control portions includes the error detecting portion, which can detect own abnormality and abnormality of other safety control portions, and the fuel shutoff control portion which shuts off the supply of a fuel by driving the power source shutoff device so as to shut off the supply of a power source voltage to the fuel shutoff valves in a case where abnormality is detected by the error detecting portion.

<CIT> discloses a method and apparatus provided for use in testing a memory coupled to a processing node. A background scrubber in the processing node is initialized to perform a test of the memory. A status of the background scrubber is checked in which the status indicates whether an error occurred during the test. A predetermined action is taken in response to the status indicating that the error occurred during the test.

The apparatus disclosed in PTL <NUM>, however, merely performs diagnostics on the SMRAM area, which is a portion of the RAM. The apparatus disclosed in PTL <NUM> therefore cannot detect failure occurring in an undiagnosed area.

It is an objective of the present disclosure to provide a failure detection apparatus, a failure detection method, and a failure detection program capable of executing failure detection on all areas of RAM.

The above object is achieved by a failure detection apparatus according to claim <NUM>, a failure detection method and a failure detection program according to claim <NUM>. The dependent claims are directed to different advantageous aspects of the invention.

In a failure detection apparatus according to an embodiment, the controller may be configured to execute processing related to detection of a property of a liquid. This configuration can detect properties of liquids.

A failure detection method according to an embodiment is a failure detection method to be executed by a failure detection apparatus including a RAM. The RAM includes a plurality of partitioned areas generated by partitioning the entire area of the RAM. The failure detection method includes executing processing related to detection of a physical quantity in a predetermined sampling period and executing sequential failure detection on a portion of the plurality of partitioned areas during a time when the processing is not being executed in each of a plurality of the sampling periods. This configuration allows execution of failure processing on all of the areas of the RAM, including the areas that affect operation of a sensor apparatus.

A failure detection program according to an embodiment is for causing a failure detection apparatus, which includes a RAM that includes a plurality of partitioned areas generated by partitioning the entire area of the RAM, to execute the steps of executing processing related to detection of a physical quantity in a predetermined sampling period and executing sequential failure detection on a portion of the plurality of partitioned areas during a time when the processing is not being executed in each of a plurality of the sampling periods. This configuration allows execution of failure processing on the entire area of the RAM, including the areas that affect operation of a sensor apparatus.

The present disclosure can provide a failure detection apparatus, a failure detection method, and a failure detection program capable of executing failure detection on all areas of RAM.

Embodiments of the present disclosure are now described with reference to the drawings.

<FIG> is a functional block diagram illustrating an example schematic configuration of a safety instrumented system <NUM> according to an embodiment. The safety instrumented system <NUM> is, for example, provided on an operation line in a plant. The safety instrumented system <NUM> is a system provided to suspend the plant in a safe state during an emergency, such as when an abnormality occurs in a device on the operation line. Having the safety instrumented system <NUM> stop operation of the plant during an emergency can prevent disasters such as explosions or fatal accidents, environmental pollution, and the like and can protect equipment. Examples of the plant include an industrial plant such as a chemical plant; a plant for managing a well site, such as a gas field or oil field, and the surrounding area; a plant for managing power generation such as hydroelectric power, thermal power, nuclear power, or the like; a plant for managing environmental power generation such as solar power, wind power, or the like; and a plant for managing water and sewage, a dam, or the like. The plant is not, however, limited to these examples.

The example safety instrumented system <NUM> illustrated in <FIG> includes a sensor apparatus <NUM>, a calculation controller <NUM>, and a safety apparatus <NUM>. In the safety instrumented system <NUM>, the sensor apparatus <NUM> functions as a failure detection apparatus that performs failure detection on internal RAM.

The sensor apparatus <NUM> is an apparatus for executing processing related to detection of a predetermined physical quantity on the operation line. The processing related to detection of a predetermined physical quantity includes detection of the predetermined physical quantity and output of a signal corresponding to the detected physical quantity. The predetermined physical quantity may be determined appropriately in accordance with properties of the devices, substances, and the like used on the operation line. The sensor apparatus <NUM> transmits a signal corresponding to the detected physical quantity to the calculation controller <NUM>. In the example in <FIG>, the sensor apparatus <NUM> transmits a signal corresponding to the detected physical quantity to the calculation controller <NUM> using a <NUM> mA to <NUM> mA current. In other words, the sensor apparatus <NUM> transmits a current in a range of <NUM> mA to <NUM> mA to the calculation controller <NUM> in accordance with the value of the detected physical quantity. In the present disclosure, the predetermined physical quantity that the sensor apparatus <NUM> detects is described as being the hydrogen ion exponent (pH) of a fluid used in the operation line. The predetermined physical quantity is not, however, limited to pH. In the present disclosure, the processing executed by the sensor apparatus <NUM> is also referred to as "sensor processing". The sensor processing includes processing related to detection of a physical quantity.

As illustrated in <FIG>, the sensor apparatus <NUM> includes a sensor element <NUM> and a signal converter <NUM>. <FIG> is a functional block diagram illustrating an example schematic configuration of the sensor apparatus <NUM>.

The sensor element <NUM> is an element for detecting the above-described predetermined physical quantity. Here, the sensor element <NUM> is a sensor element capable of detecting the pH of a fluid.

The signal converter <NUM> receives an electric signal outputted by the sensor element <NUM> on the basis of the detection result, performs digital signal processing on the electric signal, and outputs a current of <NUM> mA to <NUM> mA to the calculation controller <NUM> on the basis of the result of the digital signal processing.

In the example in <FIG>, the signal converter <NUM> includes an analog-to-digital (A/D) converter <NUM>, a controller <NUM>, an output interface <NUM>, read only memory (ROM) <NUM>, and RAM <NUM>.

The A/D converter <NUM> converts an analog electric signal, outputted by the sensor element <NUM> on the basis of the detection result, to a digital signal.

The controller <NUM> controls and manages the signal converter <NUM> overall, starting with the functional blocks of the signal converter <NUM>. The controller <NUM> may be configured as software executed by a suitable processor, such as a central processing unit (CPU), or configured as a dedicated processor specialized for each process.

In accordance with a program stored in the ROM <NUM>, for example, the controller <NUM> performs predetermined calculation processing on the digital signal converted by the A/D converter <NUM>. The controller <NUM> stores the result of the calculation processing (calculation result) in the RAM <NUM>, for example. The controller <NUM> also converts the calculation result stored in the RAM <NUM> to a <NUM> mA to <NUM> mA current and outputs the current periodically, for example, to the calculation controller <NUM>.

The output interface <NUM> is an interface for outputting signals to the calculation controller <NUM> on the basis of control by the controller <NUM>. Here, the output interface <NUM> outputs <NUM> mA to <NUM> mA current signals to the calculation controller <NUM> on the basis of control by the controller <NUM>.

The ROM <NUM> functions as a memory of the signal converter <NUM>. The ROM <NUM> stores programs executed by the controller <NUM>, for example.

The RAM <NUM> functions as a memory of the signal converter <NUM>. The RAM <NUM> stores the calculation result from the controller <NUM>, for example.

<FIG> schematically illustrates an example of data areas in the RAM <NUM>. As illustrated in <FIG>, the RAM <NUM> includes an operating system (OS) area <NUM>, a stack area <NUM>, a data area for program operation control <NUM>, and a calculation result storage area <NUM> as data areas. The OS area <NUM> is an area storing software for the controller <NUM> to operate. The stack area <NUM> is an area for temporarily storing data during execution of processing by the controller <NUM>. The data area for program operation control <NUM> is an area for storing data used when running programs. Data such as the number of measurements for calculating an average is stored here. The calculation result storage area <NUM> is an area for storing the result of calculation processing that the controller <NUM> executes on the digital signal converted by the A/D converter <NUM>, as described above.

Referring again to <FIG>, the calculation controller <NUM> receives a current signal from the sensor apparatus <NUM>. The calculation controller <NUM> executes safety control logic for implementing safety control. When judging, for example on the basis of the received current signal, that an abnormality has occurred, the calculation controller <NUM> transmits a control signal to the safety apparatus <NUM> to cause the safety apparatus <NUM> to execute predetermined control. The calculation controller <NUM> may be constituted by a mechanism known as a logic solver.

The safety apparatus <NUM> executes predetermined control on the basis of the control signal received from the calculation controller <NUM>. For example, on the basis of the control signal received from the calculation controller <NUM>, the safety apparatus <NUM> executes control to stop the operation line.

The safety apparatus <NUM> may, for example, be formed by a valve positioner, an electromagnetic valve, or the like. When judging, on the basis of the received current signal, that an abnormality has occurred, the calculation controller <NUM> transmits a control signal to the safety apparatus <NUM> to close the valve. The safety apparatus <NUM> configured as a valve positioner or an electromagnetic valve can, for example, stop the supply of a fluid to the line by closing the valve in response to the control signal received from the calculation controller <NUM>.

In the safety instrumented system <NUM> illustrated as an example in <FIG>, a safety integrity level (SIL) is known as an index related to the likelihood of fulfilling a safety function. The safety integrity level is classified into four stages from SIL1 to SIL4, where SIL1 indicates the lowest level of safety, and SIL4 indicates the highest level of safety. The SIL may, for example, be determined in accordance with the functional safety standard IEC <NUM>.

The SIL of the safety instrumented system <NUM> is, for example, determined by the product of the probability of failure on demand (PFD) of each constituent element of the safety instrumented system <NUM>. In other words, in the example safety instrumented system <NUM> illustrated in <FIG>, the SIL is determined by the product of the PFDs of the sensor apparatus <NUM>, the calculation controller <NUM>, and the safety apparatus <NUM>. As the product of the PFDs of the constituent elements is lower, the index indicated by the SIL classification increases. In other words, as the product of the PFDs of the constituent elements is lower, safety is higher.

The sensor apparatus <NUM> of the safety instrumented system <NUM> includes the RAM <NUM>, as described with reference to <FIG>. Failure more easily occurs in the RAM <NUM>, however, than in the other functional units. In other words, the PFD of the RAM <NUM> tends to increase. The PFD of the RAM <NUM> therefore tends to have a large effect on the SIL of the safety instrumented system <NUM>. Hence, the SIL of the safety instrumented system <NUM> overall can easily be increased by improving the PFD of the RAM <NUM>.

In a known technique, failure detection is executed on the entire RAM <NUM> upon startup of the safety instrumented system <NUM>, for example, whereas during operation of the RAM <NUM>, failure detection is executed on the calculation result storage area <NUM> among the areas of the RAM <NUM>. Failure detection is only executed on the calculation result storage area <NUM> during operation of the RAM <NUM>, however, and failure detection is not executed on other areas that affect operation of the safety instrumented system <NUM>. In the example in <FIG>, the other areas that affect operation of the safety instrumented system <NUM> are the OS area <NUM>, the stack area <NUM>, and the data area for program operation control <NUM>. Furthermore, operation of the RAM <NUM> needs to stop if failure detection is to be executed on areas other than the calculation result storage area <NUM>, such as the OS area <NUM>, during operation of the RAM <NUM>. Stopping operation of the RAM <NUM> and executing failure detection, however, hinders operation of the safety instrumented system <NUM>. Stopping operation of the RAM <NUM> to execute failure detection is therefore not realistic.

On the other hand, if the RAM <NUM> included an error check and correct (ECC) function, the RAM <NUM> could execute failure detection on the entire RAM <NUM> by executing ECC-based failure detection, even during operation of the RAM <NUM>. The ECC function is capable of detecting that an error has occurred in data stored in the RAM <NUM> and of correcting the erroneous data. However, RAM <NUM> with an ECC function is more expensive than RAM <NUM> without an ECC function. Hence, the cost of the safety instrumented system <NUM> increases upon using RAM <NUM> with an ECC function.

The present disclosure therefore provides a failure detection apparatus, a failure detection method, and a failure detection program capable of using a less expensive RAM <NUM>, without an ECC function, to execute failure detection during operation of the RAM <NUM>.

Here, a concrete method of failure detection executed by the sensor apparatus <NUM> according to the present embodiment is described. Suppose that failure detection executed on the entire area of the RAM <NUM> requires approximately several hundred milliseconds to several seconds, for example. It is unrealistic, however, to stop the RAM <NUM> for several hundred milliseconds to several seconds while the RAM <NUM> is operating, as described above.

To address this issue, the sensor apparatus <NUM> according to the present embodiment executes sequential failure detection on a plurality of elements yielded by partitioning the entire area of the RAM <NUM> and thus divides up the entire area of the RAM <NUM> to perform failure detection.

<FIG> illustrates a method of failure detection executed by the sensor apparatus <NUM> according to the present embodiment. The upper and lower tiers of <FIG> are time charts illustrating processing executed by the sensor apparatus <NUM>. The horizontal axis in <FIG> represents time.

The time chart in the lower tier of <FIG> indicates processing when the sensor apparatus <NUM> executes failure detection at once on the entire area of the RAM <NUM>. When failure detection is executed at once on the entire area of the RAM <NUM>, a predetermined time T<NUM> is required for failure detection of the entire area of the RAM <NUM>. As described above, the predetermined time T<NUM> is several hundred milliseconds to several seconds, for example. When failure detection is thus executed at once on the entire area of the RAM <NUM>, operation of the RAM <NUM> needs to be stopped for the predetermined time T<NUM>.

The time chart in the upper tier of <FIG> illustrates failure detection processing executed by the sensor apparatus <NUM> according to the present embodiment. During failure detection, the sensor apparatus <NUM> according to the present embodiment uses a plurality of elements generated by partitioning the entire area of the RAM <NUM>. The partitioned elements generated by partitioning the entire area of the RAM <NUM> are also referred to as "partitioned areas" in the present disclosure. The time chart in the lower tier of <FIG> illustrates an example of partitioned areas yielded by partitioning the entire area of the RAM <NUM>. In the present embodiment, the partitioned areas of the RAM <NUM> may be determined in advance and set in the sensor apparatus <NUM>.

The partitioned areas may be partitioned by a different classification than the example data areas of the RAM <NUM> illustrated in <FIG>. In other words, the partitioned areas need not be the four areas consisting of the OS area <NUM>, the stack area <NUM>, the data area for program operation control <NUM>, and the calculation result storage area <NUM>. For example, the OS area <NUM>, the stack area <NUM>, the data area for program operation control <NUM>, and the calculation result storage area <NUM> may each be further partitioned to form the partitioned areas. In this case, each partitioned area belongs to one of the OS area <NUM>, the stack area <NUM>, the data area for program operation control <NUM>, and the calculation result storage area <NUM>.

As illustrated in the time chart in the upper tier in <FIG>, the sensor apparatus <NUM> according to the present embodiment executes the sensor processing over a certain sampling period T<NUM>, for example. The sampling period T<NUM> may be set appropriately in accordance with the physical quantity to be detected, the specifications of the sensor element <NUM>, and the like, for example.

During each the sampling period T<NUM>, the sensor apparatus <NUM> executes sensor processing. For example, the sensor apparatus <NUM> executes processing to detect a physical quantity during each sampling period T<NUM>. The sensor processing that the sensor apparatus <NUM> executes can be completed without taking up the entire sampling period T<NUM>. For example, in each sampling period T<NUM>, the sensor apparatus <NUM> can complete the sensor processing to be executed during the sampling period T<NUM> within a predetermined time T<NUM> after the start of sampling (where T<NUM> > T<NUM>). In other words, the sensor apparatus <NUM> does not execute sensor processing in each sampling period T<NUM> during a time T<NUM> yielded by subtracting the predetermined time T<NUM> from the sampling period T<NUM> (where T<NUM> = T<NUM> + T<NUM>). The predetermined time T<NUM> is also referred to below as the sensor processing time T<NUM>.

The sensor apparatus <NUM> according to the present embodiment executes failure detection during the time T<NUM>, within each sampling period T<NUM>, when sensor processing is not being executed. At this time, the sensor apparatus <NUM> executes failure detection on one partitioned area of the RAM <NUM>. The time T<NUM> is also referred to below as the failure detection time T<NUM>.

The sensor apparatus <NUM> repeatedly alternates between sensor processing during the sensor processing time T<NUM> and failure detection during the failure detection time T<NUM> in the sampling periods T<NUM>. During the failure detection times T<NUM> of the sampling periods T<NUM>, the sensor apparatus <NUM> executes sequential failure detection on all of the partitioned areas. The sensor apparatus <NUM> thus sequentially executes failure detection on the partitioned areas in the sampling periods T<NUM>. The sensor apparatus <NUM> can execute failure detection on the entire area of the RAM <NUM> by cycling through the same number of sampling periods T<NUM> as the number of partitioned areas. The time required for the sensor apparatus <NUM> according to the present embodiment to complete failure detection once on the entire area of the RAM <NUM> is also referred to below as the failure detection period TD.

The failure detection period TD includes the same number of sampling periods T<NUM> as the number of partitioned areas of the RAM <NUM>. The sensor apparatus <NUM> according to the present embodiment executes sequential failure detection on the partitioned areas of the RAM <NUM> in this way during the failure detection time T<NUM>, which is a portion of each sampling period T<NUM>. The sensor apparatus <NUM> can thereby execute failure detection on the entire area of the RAM <NUM> within the failure detection period TD.

<FIG> is a flowchart illustrating an example of processing executed by the sensor apparatus <NUM> during the failure detection time T<NUM>. The sensor apparatus <NUM> executes failure detection on one partitioned area by executing the processing illustrated as an example in <FIG> during the failure detection time T<NUM>.

<FIG> illustrates partitioned areas generated by partitioning the entire area of the RAM <NUM>. As illustrated in <FIG>, the RAM <NUM> has N partitioned areas (N > <NUM>), from area <NUM> to area N, as the partitioned areas for executing failure detection. Data, for example, is stored in each partitioned area. The sensor apparatus <NUM> executes failure detection sequentially on the N partitioned areas from area <NUM> to area N during the failure detection time T<NUM> of each sampling period T<NUM>. The procedures in <FIG> illustrate an example of failure detection processing on area <NUM> among the partitioned areas.

<FIG> schematically illustrates example registers included in the controller <NUM> of the signal converter <NUM>. In the present embodiment, the procedures in <FIG> are executed by the controller <NUM>, which includes at least five registers from R0 to R4, as in the example in <FIG>.

As illustrated in <FIG>, the controller <NUM> executes processing to disable interrupts at the start of the failure detection time T<NUM> (step S10). Consequently, processing other than failure detection does not interrupt. In other words, processing other than the processing illustrated in the procedures of <FIG> will not be executed.

Next, the controller <NUM> transfers the data (DATA <NUM>) stored in area <NUM> of the RAM <NUM> to register R3 of the controller <NUM> to store the DATA <NUM> in register R3 (step S11). The controller <NUM> thus temporarily saves the DATA <NUM> that was stored in area <NUM> in register R3.

The controller <NUM> then writes the value "0x55555555" as the DATA <NUM> of area <NUM> (step S12). "0x55555555" is a value represented as "<NUM>. " in a <NUM>-bit pattern.

The controller <NUM> calculates the exclusive OR of the DATA <NUM> and "0x55555555" and saves the calculation result in register R2 (step S13). Here, since "0x55555555" was written in the DATA <NUM> in step S12, the calculation result saved in register R2 is <NUM> if area <NUM> is normal.

The controller <NUM> then writes the value "0xAAAAAAAA" as the DATA <NUM> of area <NUM> (step S14). "0xAAAAAAAA" is a value represented as "<NUM>. " in a <NUM>-bit pattern.

The controller <NUM> calculates the OR of i) the exclusive OR of the DATA <NUM> and "0xAAAAAAAA" and ii) the calculation result saved in register R2 in step S13. The controller <NUM> saves the calculation result in register R0 (step S15). Here, since "0xAAAAAAAA" was written in the DATA <NUM> in step S14, the exclusive OR of the DATA <NUM> and "0xAAAAAAAA" is <NUM> if area <NUM> is normal. Accordingly, the calculation result saved in register R0 is <NUM> if area <NUM> is normal. Conversely, the calculation result saved in register R0 is a value other than <NUM> if an abnormality is present in area <NUM>.

Next, the controller <NUM> stores the original data that was saved in register R3 in area <NUM> (step S16). In this way, the controller <NUM> restores the original data that was stored in area <NUM>.

The controller <NUM> executes processing enabling interrupts (step S17). Consequently, processing other than failure detection can interrupt and be executed.

The controller <NUM> judges whether the calculation result saved in register R0 is <NUM> (step S18).

When judging that the calculation result saved in register R0 is <NUM> (step S18: Yes), the controller <NUM> judges that area <NUM> is normal and terminates the procedures.

Conversely, when judging that the calculation result saved in register R0 is not <NUM> (step S18: No), the controller <NUM> judges that an abnormality exists in area <NUM> and executes error processing (step S19). As the error processing, the controller <NUM> provides notification of the occurrence of an error, for example. The controller <NUM> then terminates the procedures.

Each time the failure detection time T<NUM> starts, the controller <NUM> executes the procedures in <FIG> to execute sequential failure detection on the partitioned areas from area <NUM> to area N. The controller <NUM> can thus execute failure detection on the entire area of the RAM <NUM> within the failure detection period TD.

In this way, the sensor apparatus <NUM> according to the present embodiment executes failure detection during the failure detection time T<NUM>, in which sensor processing is not being executed, within each sampling period T<NUM> on the partitioned areas yielded by partitioning the RAM <NUM>. The sensor apparatus <NUM> can therefore execute failure processing on all of the areas of the RAM <NUM>, including the areas that affect operation of the sensor apparatus <NUM>, i.e. the OS area <NUM>, the stack area <NUM>, and the data area for program operation control <NUM>. Furthermore, by executing failure detection during the failure detection time T<NUM> in which sensor processing is not being executed, the sensor apparatus <NUM> can execute failure detection without affecting the sensor processing executed by the sensor apparatus <NUM>. In other words, the sensor apparatus <NUM> can execute failure detection without impairing the functions in the safety instrumented system <NUM>.

Since the sensor apparatus <NUM> according to the present embodiment executes failure detection on the entire area of the RAM <NUM>, the probability of overlooking failure of the RAM <NUM> is lower than when failure detection is only executed on a portion of the area of the RAM <NUM>. The PFD of the sensor apparatus <NUM> thus decreases. Consequently, the PFD of the safety instrumented system <NUM> overall can be reduced, improving the SIL.

The SIL of the safety instrumented system <NUM> has been described in the above embodiment as being determined by the product of the PFDs of the constituent elements of the safety instrumented system <NUM>. The SIL of the safety instrumented system <NUM> may, however, be determined on the basis of the safe failure fraction (SFF) and the fault tolerance (FT). For example, the SIL may be determined so that the index indicated by the SIL classification increases as the SFF is higher or as the FT is higher.

In the above embodiment, the sensor apparatus <NUM> has been described as executing failure detection on one partitioned area of the RAM <NUM> during the failure detection time T<NUM> of each sampling period T<NUM>. However, the target of failure detection that the sensor apparatus <NUM> executes during the failure detection time T<NUM> of each sampling period T<NUM> is not limited to being one partitioned area. The sensor apparatus <NUM> may execute failure detection on two or more partitioned areas of the RAM <NUM> during the failure detection time T<NUM> of each sampling period T<NUM>. This approach may, for example, be taken only when failure detection can be executed on two or more partitioned areas during the failure detection time T<NUM>. In this way, the sensor apparatus <NUM> may execute failure detection on a portion of the plurality of partitioned areas of the RAM <NUM> during the failure detection time T<NUM> of each sampling period T<NUM>. When the sensor apparatus <NUM> executes failure detection on two or more partitioned areas during the failure detection time T<NUM> of each sampling period T<NUM>, the sensor apparatus <NUM> can execute failure detection processing on the entire RAM <NUM> earlier than when executing failure detection on one partitioned area. In other words, the failure detection period TD can be shortened.

In the above embodiment, the sensor apparatus <NUM> may execute failure detection on a priority basis on a specific partitioned area that is a portion of the plurality of partitioned areas. Here, executing failure detection on a priority basis refers to executing failure detection on the specific partitioned area before the other partitioned areas, i.e. at an earlier stage in the failure detection period TD. The specific partitioned area on which failure detection is executed on a priority basis may, for example, be determined in advance and set in the sensor apparatus <NUM>. Specific partitioned areas may, for example, be areas that could affect the SIL classification among the plurality of partitioned areas. Executing failure detection on a priority basis on specific partitioned areas facilitates earlier detection of failure in the specific partitioned areas.

For example, the specific partitioned areas may be the partitioned areas belonging to the calculation result storage area <NUM>. The sensor apparatus <NUM> may in this case execute failure detection on a priority basis on the partitioned areas belonging to the calculation result storage area <NUM> as the specific partitioned area. When failure occurs outside of the calculation result storage area <NUM>, for example in the OS area <NUM>, the sensor apparatus <NUM> operates abnormally, and failure of the sensor apparatus <NUM> can be discovered. On the other hand, when failure occurs in the calculation result storage area <NUM>, it is difficult to judge whether the calculation result is normal or abnormal, making it difficult to discover failure of the sensor apparatus <NUM>. The occurrence of failure in the calculation result storage area <NUM>, however, may result in a normal calculation result not being output, and the safety instrumented system <NUM> may stop operating normally. In this way, the probability of overlooking failure is high when failure occurs in the calculation result storage area <NUM>. This issue can be addressed by executing failure detection on a priority basis on partitioned areas belonging to the calculation result storage area <NUM>, as a specific partitioned area, to allow failure in the calculation result storage area <NUM> to be detected earlier.

The sensor apparatus <NUM> according to the above embodiment has been described as an apparatus for detecting a predetermined physical quantity on an operation line. Here, in particular when the sensor processing is executed, a longer sampling period T<NUM> is suitable for the failure detection method described in the above embodiment. The reason is that a longer failure detection time T<NUM> can more easily be set aside as the sampling period T<NUM> is longer, allowing more time to be used for failure detection in each sampling period T<NUM>.

In the case of a fluid being supplied to the operation line, for example, the properties of liquids generally tend to change more gradually than the properties of gases. Hence, if the sampling period T<NUM> is longer, a sensor apparatus <NUM> that detects properties of liquids can detect the properties more easily than can a sensor apparatus <NUM> that detects the properties of gases. The sensor apparatus <NUM> may therefore be an apparatus that detects the properties of a liquid or the change in the properties of the liquid as the predetermined physical quantity in the operation line. This is not, however, meant to exclude the sensor apparatus <NUM> from being an apparatus that detects the properties of a gas or the change in the properties of the gas.

Claim 1:
A sensor apparatus comprising a sensor element (<NUM>) and a failure detection apparatus (<NUM>), the failure detection apparatus (<NUM>) comprising:
a RAM (<NUM>); and
a controller (<NUM>) configured to execute processing related to detection of a physical quantity in a predetermined sampling period (T<NUM>),
wherein the RAM (<NUM>) comprises a plurality of partitioned areas generated by partitioning an entire area of the RAM (<NUM>),
wherein the controller (<NUM>) is configured to execute, during each sampling period (T<NUM>) in a sequence of sampling periods, sequential failure detection on a portion of the plurality of partitioned areas during remaining time of each sampling period, when the controller (<NUM>) is not executing the processing in each of the sampling periods, the controller thereby executing in alternating sequence the processing related to detection of a physical quantity and sequential failure detection,
wherein the controller (<NUM>) is configured to execute failure detection on a priority basis on a specific partitioned area among the plurality of partitioned areas,
wherein the specific partitioned area belongs to a calculation result storage area configured to store a higher prioritized result of calculation processing of sensor data executed by the controller (<NUM>), and
wherein the sampling periods are set on basis of the detected physical quantity.