Patent Description:
Recently, as various functions are installed in electronic devices, the frequency of processing important data, such as personal information and security information, in electronic devices has increased. Electronic devices can include an SE that performs a secure operation on important data in order to prevent hacking of important data.

The SE may be implemented as any one of an integrated SE included in a system-on-chip (SoC) included in the electronic device and a discrete SE disposed outside the SoC.

The integrated SE may directly access an external memory connected to the SoC to perform a secure operation. However, the integrated SE is difficult to commercialize due to issues, such as structural limitations within the SoC (e.g., semiconductor processes of the SoC and the integrated SE may be different), and thus, the integrated SE needs to be implemented as a discrete SE.

However, due to the limitation of the capacity of an internal memory included in the discrete SE, it may be difficult to store all of various important data having large capacity.

<CIT> discloses a security device having indirect access to external non-volatile memory.

The inventive concepts provide secure elements (SE) that perform secure operations using an external memory connected to a system-on-chip (SoC) and electronic devices including the same, as set out in the independent claims. Further aspects of the invention are set out in the dependent claims.

Example embodiments will be more clearly understood from the following detailed description taken in association with the accompanying drawings in which:.

<FIG> is a block diagram illustrating an electronic device <NUM> according to some example embodiments. <FIG> shows the electronic device <NUM> including only components necessary to explain the inventive concepts, and the electronic device <NUM> may further include other integrated circuits (ICs) (not shown) to which the inventive concepts are applicable.

Referring to <FIG>, the electronic device <NUM> may include a secure element (SE) <NUM>, a system-on-chip (SoC) <NUM>, and an external memory <NUM>.

In some example embodiments, the SE <NUM> may include secure element (SE) interface circuitry <NUM>, virtual secure direct memory access (DMA) circuitry <NUM>, a secure processor <NUM>, and an internal memory <NUM>.

In some example embodiments, the SoC <NUM> may include interface circuitry <NUM>, DMA circuitry <NUM>, a processor <NUM>, and input/output (I/O) interface circuitry <NUM>, and the SoC <NUM> may be connected to the external memory <NUM>.

Example embodiments of the SE <NUM> and the SoC <NUM> described below may be implemented or supported by artificial intelligence technology or one or more computer programs, each of which includes computer-readable program code and may be implemented in a computer-readable medium included in each of the SE <NUM> and the SoC <NUM>. The terms "application" and "program" refer to one or more computer programs, software components, sets of instructions, procedures, functions, objects, classes, instances, related data, or portions thereof suitable for implementation of suitable computer-readable program code. The term "computer-readable program code" includes any type of computer code including source code, object code, and executable code. The term "computer-readable medium" includes any type of medium that may be accessed by a computer, such as read only memory (ROM), random access memory (RAM), a hard disk drive, a compact disk (CD), a digital video disk (DVD), or any other type of memory. A "non-transitory" computer-readable medium excludes wired, wireless, optical, or other communication links that transmit transitory electrical or other signals. A non-transitory computer-readable medium includes a medium in which data may be permanently stored and a medium in which data may be stored and later overwritten, such as a rewritable optical disk or an erasable memory device.

The electronic device <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc. (or other circuitry, for example, SE <NUM>, interface circuitry <NUM>, DMA circuitry <NUM>, secure processor <NUM>, internal memory <NUM>, SoC <NUM>, interface circuitry <NUM>, DMA circuitry <NUM>, a processor <NUM>, and input/output (I/O) interface circuitry <NUM>, external memory <NUM>, first SE interface <NUM>, virtual secure DMA circuitry <NUM>, secure processor <NUM>, translation lookaside buffer (TLB) <NUM>, memory management unit (MMU) <NUM>, static random access memory (SRAM) <NUM>, non-volatile memory (NVM) <NUM>, bus <NUM>, electronic device <NUM>', <NUM>', <NUM>‴ and subcomponents thereof, and network system <NUM> and subcomponents thereof) may include hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc..

In some of the example embodiments described below, a hardware approach will be described as an example. However, although the example embodiments include technology using both hardware and software, the example embodiments do not exclude a software-based approach.

In some example embodiments, the SE <NUM> may perform a secure operation using the external memory <NUM>. In the present specification, the secure operation may include an operation of generating secure data from data based on a root of trust (RoT) or a secure application and an operation of verifying the secure data. For example, the secure application may include a virus scan-related application, an encryption-related application, a firewall-related application, an intrusion detection system-related application, a spyware control program-related application, and the like.

In some example embodiments, the SE <NUM> may generate secure data from data and transmit the secure data together with a write request to the SoC <NUM>, and the SoC <NUM> may write the secure data to the external memory <NUM> in response to the write request. In addition, the SE <NUM> may transmit a read request for secure data to the SoC <NUM>, and the SoC <NUM> may transmit secure data read from the external memory <NUM> to the SE <NUM> in response to the read request. That is, in order to prevent or reduce data access, tampering, forgery, etc. in the SoC <NUM>, a series of operations for generating secure data from data and verifying the secure data may be performed in the SE <NUM> side.

In some example embodiments, the SE <NUM> may perform a secure operation using the external memory <NUM> when an available capacity of the internal memory <NUM> for storing secure data is insufficient (e.g., there is not enough memory space, or another condition which prevents reliably storing the secure data in the internal memory <NUM>). To this end, the SE <NUM> may separately receive a signal indicating whether the external memory <NUM> is available from the SoC <NUM>, and perform a secure operation based on the received signal. In some example embodiments, the SE <NUM> may further include at least one pin for receiving the signal indicating whether the external memory <NUM> is available. In some example embodiments, the SE <NUM> may perform a secure operation using the external memory <NUM> in preference to the internal memory <NUM> (e.g., the SE <NUM> may rank the external memory at a higher priority for data storage than the internal memory <NUM>). For example, the SE <NUM> may first determine availability of the external memory <NUM> before using the internal memory <NUM>. In this case, the SE <NUM> may perform a secure operation using the internal memory <NUM> when receiving a signal from the SoC <NUM> indicating that the external memory <NUM> is not available.

In some example embodiments, the secure processor <NUM> may execute a secure application to control overall secure operations. For example, the secure processor <NUM> may determine a secure operation using the external memory <NUM> based on at least one of a state of the internal memory <NUM>, a state of the SoC <NUM>, and a state of the external memory <NUM>.

In some example embodiments, the virtual secure DMA circuitry <NUM> may generate secure data from data processed in the secure processor <NUM> in association with the internal memory <NUM> based on the executed secure application, or provide data obtained from the secure data verified by performing a verification operation on the secure data to the secure processor <NUM>. In some example embodiments, the internal memory <NUM> may store keys corresponding to a secure application and an anti-replay counter (ARC) table, and the virtual secure DMA circuitry <NUM> may perform a secure operation using keys read from the internal memory <NUM> and the ARC table. An anti-replay counter (ARC) may be used to provide protection against a replay attack. The ARC is a counter that increases each time a packet is sent. An ARC value is assigned and included in each encrypted packet. Both the transmitter and receiver keep track of the current ARC value based on the number of transmitted packets. This allows the receiver to verify the integrity of the received packet (e.g. by checking that the ARC value contained within the packet matches the current ARC value, or falls within an expected ARC window).

In some example embodiments, the SE interface circuitry <NUM> may transmit the secure data generated by the virtual secure DMA circuitry <NUM> to the interface circuitry <NUM> of the SoC <NUM> or receive secure data from the interface circuitry <NUM>. In this specification, a series of operations for transmitting and receiving signals including secure data between the SE interface circuitry <NUM> and the interface circuitry <NUM> may be referred to as communication operations between the SE interface circuitry <NUM> and the interface circuitry <NUM>. In addition, the SE interface circuitry <NUM> may transmit a write request or a read request or an address for the secure data to the interface circuitry <NUM>. In some example embodiments, the SE interface circuitry <NUM> may include at least one SE interface. In some example embodiments, the at least one SE interface may correspond to any one of a serial-to-peripheral interface (SPI), an inter-IC interface, and an improved inter-IC to support a high communication rate.

In some example embodiments, the SE interface circuitry <NUM> may include a plurality of SE interfaces, and the virtual secure DMA circuitry <NUM> may select one of the SE interfaces based on the executed secure application to use the selected SE interface to transmit or receive secure data. In some example embodiments, the SE interfaces may support different communication rates.

In some example embodiments, the interface circuitry <NUM> may transmit secure data, an address, a write request, a read request, etc. received from the SE interface circuitry <NUM> to the DMA circuitry <NUM>. Also, the interface circuitry <NUM> may transmit the secure data received from the DMA circuitry <NUM> to the SE interface circuitry <NUM>. In some example embodiments, the interface circuitry <NUM> may include at least one interface.

In some example embodiments, the DMA circuitry <NUM> may write secure data to the external memory <NUM> through input/output (I/O) interface circuitry <NUM> in response to a write request received from the SE interface circuitry <NUM>. The DMA circuitry <NUM> may read secure data from the external memory <NUM> through the I/O interface circuitry <NUM> in response to a read request received from the SE interface circuitry <NUM>. The DMA circuitry <NUM> may access the external memory <NUM> in response to a write request or a read request without intervention of the processor <NUM>. The DMA circuitry <NUM> may exclusively perform a memory operation on the secure data of the SE <NUM>, that is, a memory operation using the I/O interface circuitry <NUM> and the external memory <NUM>. However, this is only some example embodiments and the inventive concepts are not limited thereto, and the DMA circuitry <NUM> may separately perform a memory operation on data processed by the processor <NUM>. In some example embodiments, the I/O interface circuitry <NUM> may include at least one I/O interface.

In some example embodiments, the processor <NUM> may control the overall operation of the SoC <NUM>. The processor <NUM> may control the SE <NUM> to initiate an operation according to some example embodiments.

In some example embodiments, the external memory <NUM> may be implemented as DRAM corresponding to any one of double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate (LPDDR) SDRAM, graphic double data rate (GDDR) SDRAM, rambus DRAM (RDRAM), etc. However, this is only some example embodiments, and the external memory <NUM> may be implemented as a resistive memory, such as resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM) or a non-volatile memory, such as flash memory. The external memory <NUM> may include a first region in which data of the SoC <NUM> is stored and a second region in which data of the SE <NUM> is stored, and the first region and the second region may be physically or logically discriminated from each other. In some example embodiments, a size of each of the first region and the second region may be changed according to operations of the SE <NUM> and the SoC <NUM>. In detail, when a size of data of the SoC <NUM> to be stored increases, the first region may be changed to be larger than before and the second region may be changed to be smaller than before. In addition, when a size of the data of the SE <NUM> to be stored increases, the first region may be changed to be smaller than before and the second region may be changed to be larger than before.

In some example embodiments, the external memory <NUM> may be implemented as a high bandwidth memory in which chips including DRAM are vertically stacked, and further, the chips may include DRAM including vertical pillar transistors.

In some example embodiments, the SE <NUM> and the SoC <NUM> may be formed through different semiconductor processes. In detail, the SoC <NUM> may be produced by a finer semiconductor process than the SE <NUM>. For example, the SoC <NUM> may be produced by a semiconductor process having higher resolution (e.g., capable of forming smaller or more complex structures), higher accuracy of materials used, or other parameters one skilled in the art would understand as a finer semiconductor than the SE <NUM>.

The SE <NUM> according to some example embodiments may generate secure data from data or directly perform verification on the secure data, and store the secure data in the external memory <NUM> connected to the SoC <NUM>, thereby supplementing the limit of the capacity of the internal memory <NUM> of the SE <NUM> and, at the same time, preventing or reducing access, tampering, forgery, etc. on data through the SoC <NUM> to support high security performance.

<FIG> is a flowchart illustrating an operating method of an electronic device according to some example embodiments. The electronic device of <FIG> includes the SE <NUM> and the SoC <NUM>.

Referring to <FIG>, in operation S10, the SE <NUM> may generate secure data from data. In some example embodiments, the SE <NUM> may set an ARC prior to generating a hash key, an encryption key, and secure data corresponding to an executed secure application, and then generate secure data based on the set ARC. However, this is only some example embodiments and the inventive concepts are not limited thereto, and the SE <NUM> may generate secure data using various keys or values according to a type of the executed secure application. Some example embodiments of operation S10 is described below with reference to <FIG>.

In operation S11, the SE <NUM> may transmit an address, a write request, and secure data to the SoC <NUM>. In some example embodiments, the SE <NUM> may sequentially transmit an address, a write request, and secure data in an agreed order through SE interface circuitry <NUM> supporting a high communication rate. In some example embodiments, the SE <NUM> may transmit at least two of an address, a write request, and secure data in parallel via a plurality of channels of the SE interface circuitry <NUM>.

In operation S12, the SoC <NUM> may write secure data to a region corresponding to a received address of the external memory <NUM> connected thereto. In response to the write request, the SoC <NUM> may translate the received address to conform to an address system of the external memory <NUM>, and write secure data to a region of the external memory <NUM> corresponding to the translated address. In some example embodiments, the SoC <NUM> may write the secure data to the external memory <NUM> by using the received address as is without translation. In this case, the SE <NUM> may generate an address translation table by receiving information on an address system of the external memory <NUM> from the SoC <NUM> in advance, and the corresponding address may be generated based on the address translation table.

In some example embodiments, operations S10-S12 may together be a write operation of the electronic device <NUM>.

In operation S13, the SoC <NUM> may receive an address and a read request from the SE <NUM>. In some example embodiments, the SE <NUM> may sequentially transmit the address and the read request in an agreed order through the SE interface circuitry <NUM> supporting a high communication rate. In some example embodiments, the SE <NUM> may separately transmit the address and the read request in parallel via a plurality of channels of the SE interface circuitry <NUM>.

In operation S14, the SoC <NUM> may read secure data from a region corresponding to the received address of the external memory <NUM> connected thereto. In response to the read request, the SoC <NUM> may translate an address to conform to an address system of the external memory <NUM>, and read secure data from a region of the external memory <NUM> corresponding to the translated address. In some example embodiments, the SoC <NUM> may read the secure data from the external memory <NUM> by using the received address as it is without translation.

In operation S15, the SoC <NUM> may transmit secure data to the SE <NUM>.

In operation S16, the SE <NUM> may verify the secure data. In some example embodiments, the SE <NUM> may perform a verification operation on the secure data based on the hash key, the encryption key, and the set ARC used in operation S10. The SE <NUM> may use data obtained from the secure data when the data included in the secure data has passed integrity verification. Some example embodiments of operation S16 is described below with reference to <FIG>.

In some example embodiments, operations S13-S16 may together be a read operation of the electronic device <NUM>.

<FIG> is a block diagram illustrating an electronic device <NUM> according to some example embodiments.

Referring to <FIG>, the electronic device <NUM> may include an SE <NUM>, an SoC <NUM>, and an external memory <NUM>.

In some example embodiments, the SE <NUM> may include a first SE interface <NUM>, virtual secure DMA circuitry <NUM>, a secure processor <NUM>, a translation lookaside buffer (TLB) <NUM>, a memory management unit (MMU) <NUM>, static random access memory (SRAM) <NUM>, a non-volatile memory (NVM) <NUM>, and a bus <NUM>. The TLB <NUM>, the SRAM <NUM>, and the NVM <NUM> may be included in the internal memory <NUM> of <FIG>.

In some example embodiments, the SoC <NUM> may include a first interface <NUM>, first DMA circuitry <NUM>, and a first I/O interface <NUM>, and the SoC <NUM> may be connected to the external memory <NUM>.

In some example embodiments, the SRAM <NUM> may store first to n-th secure applications 116_1 to 116_n. In this specification, the SRAM <NUM> may be referred to as a cache memory. The first to n-th secure applications 116_1 to 116_n of the SRAM <NUM> may be copied from ROM in the SE <NUM>.

In some example embodiments, the secure processor <NUM> may execute any one of first to n-th secure applications 116_1 to 116_n. The MMU <NUM> may determine whether there is an available page in which data processed by the secure processor <NUM> is to be written or whether a page to be read exists in the internal memory using the TLB <NUM>. In detail, the MMU <NUM> may change a virtual address received from the secure processor <NUM> into a physical address based on an address translation cache of the TLB <NUM>, and determine whether a page corresponding to the resultant physical address exists in the TLB <NUM> or the SRAM <NUM>. The secure processor <NUM> may control a secure operation of the SE <NUM> based on a result of the determination from the MMU <NUM>. In detail, the secure processor <NUM> may control the secure operation using the external memory <NUM> when the result of the determination from the MMU <NUM> is a page fault. In some example embodiments, the MMU <NUM> may manage to perform a secure operation using the external memory <NUM> preferentially than the internal memory of the SE <NUM>.

In some example embodiments, the virtual secure DMA circuitry <NUM> may include a first submodule 112_1. The first submodule 112_1 may generate secure data based on an executed secure application among the first to n-th secure applications 116_1 to 116_n or perform a verification operation on the secure data. The NVM <NUM> may store first to n-th keys 117_11 to 117_1n and first to n-th ARC tables 117_21 to 117_2n respectively corresponding to the first to n-th secure applications 116_1 to 116_n. The first submodule 112_1 may read the keys and the ARC table corresponding to the executed secure application from the NVM <NUM> to generate secure data or to verify the secure data.

In some example embodiments, the first SE interface <NUM> may transmit the secure data generated by the first submodule 112_1 to the first interface <NUM> of the SoC <NUM> or receive secure data from the first interface <NUM>. The first SE interface <NUM> may be exclusively allocated to the first submodule 112_1. The first SE interface <NUM> may be implemented to support a communication rate and a communication method required by the SE <NUM>.

In some example embodiments, the first interface <NUM> may transmit secure data, an address, a write request, and a read request received from the first SE interface <NUM> to the first DMA circuitry <NUM>. The first interface <NUM> may transmit the secure data received from the first DMA circuitry <NUM> to the first SE interface <NUM>. The first interface <NUM> may support the same communication rate and communication method as those of the first SE interface <NUM>.

In some example embodiments, in response to a write request received from the first SE interface <NUM>, the first DMA circuitry <NUM> may write secure data to a first region <NUM> of the external memory <NUM> through the first I/O interface <NUM>. In response to a read request received from the first SE interface <NUM>, the first DMA circuitry <NUM> may read secure data from the first region <NUM> of the external memory <NUM> through the first I/O interface <NUM>. In some example embodiments, the first DMA circuitry <NUM> may exclusively connect to the first region <NUM> of the external memory <NUM>.

In some example embodiments, the first region <NUM> of the external memory <NUM> may be set to vary. As an example, the first region <NUM> may vary depending on a type of a secure application executed in the SE <NUM>. Also, the first region <NUM> may vary depending on a state of the SOC <NUM> (e.g., an operating mode of the SOC <NUM> or a required amount of memory space).

In some example embodiments, the first region <NUM> may be physically or logically divided for each secure application so that secure data corresponding to each of the first to n-th secure applications 116_1 to 116_n may be stored separately.

<FIG> and <FIG> are flowcharts illustrating an operating method of an electronic device according to some example embodiments. The electronic device of <FIG> and <FIG> may include the SE <NUM> and the SOC <NUM>. Hereinafter, it will be described with further reference to <FIG> for better understanding.

Referring to <FIG>, in operation S100, the SE <NUM> may generate a first virtual address for writing secure data.

In operation S110, the SE <NUM> may determine absence of an available page of the TLB <NUM> or the SRAM <NUM> using the MMU <NUM> and the TLB <NUM>. The SE <NUM> may translate a first virtual address into a first address based on the address translation cache of the TLB <NUM>, and determine that an available page corresponding to the first address is absent in the TLB <NUM> or the SRAM <NUM>. In other words, the SE <NUM> may determine that it is currently unable to store secure data in the TLB <NUM> or the SRAM <NUM>.

In operation S120, the SE <NUM> may determine to use the external memory <NUM>. In some example embodiments, based on operation S110 determining that it is currently unable to store secure data in the TLB <NUM> or the SRAM <NUM>, the SE <NUM> determine to use the external memory <NUM>.

In operation S130, the SE <NUM> may read keys for hashing and encryption from the NVM <NUM>, and may set an ARC. The set ARC may be stored in the NVM <NUM>. In detail, the set ARC may be included in the ARC table stored in the NVM <NUM>.

In operation S140, the SE <NUM> may generate secure data by performing hashing and encryption on data based on the read keys.

In operation S150, the SE <NUM> may transmit a first address, a write request, and secure data to the SoC <NUM>.

In operation S160, the SoC <NUM> may write secure data to the first region <NUM> of the external memory <NUM> using a second address corresponding to the first address. In some example embodiments, the first address may be the same as or different from the second address. When the first address is different from the second address, the SoC <NUM> may translate the first address into the second address based on a certain address translation table.

In operation S170, the SoC <NUM> may notify the SE <NUM> that the secure data has been written to the external memory <NUM>. In some example embodiments, the first DMA circuitry <NUM> may transmit a notification signal indicating completion of writing for the secure data to the first SE interface <NUM> through the first interface <NUM>.

Referring further to <FIG>, in operation S200, the SE <NUM> may generate a second virtual address for reading secure data.

In operation S210, the SE <NUM> may determine the absence of a page to which secure data is written in the TLB <NUM> or the SRAM <NUM> using the MMU <NUM> and the TLB <NUM>. The SE <NUM> may translate the second virtual address into a third address based on the address translation cache of the TLB <NUM>, and determine that there is no page corresponding to the third address in the TLB <NUM> or the SRAM <NUM>. In other words, the SE <NUM> may determine that no secure data is currently stored in the TLB <NUM> or the SRAM <NUM>. In some example embodiments, the SE <NUM> may store addresses corresponding to a plurality of pieces of secure data stored in the external memory <NUM>, compare the third address translated from the second virtual address with the stored addresses, and determine whether secure data has been stored in the TLB <NUM> or the SRAM <NUM> based on a comparison result, instead of operation S210.

In operation S220, the SE <NUM> may transmit a third address and a read request to the SOC <NUM>.

In operation S230, the SoC <NUM> may read secure data from the first region <NUM> of the external memory <NUM> using a fourth address corresponding to the third address. In some example embodiments, the third address may be the same as or different from the fourth address. When the third address is different from the fourth address, the SoC <NUM> may translate the third address into the fourth address based on a certain address translation table.

In operation S240, the SOC <NUM> may transmit secure data to the SE <NUM>.

In operation S250, the SE <NUM> may read an ARC set immediately before the keys for hashing and decryption and the received secure data are generated in the SE <NUM>, from the NVM <NUM>.

In operation S260, the SE <NUM> may verify the secure data using the read keys and the set ARC. The SE <NUM> may process data obtained from the verified secure data.

<FIG> and <FIG> are views illustrating an operation of virtual secure DMA circuitry according to some example embodiments. It is assumed that second secure data SD' of <FIG> has been read from first secure data SD of <FIG> written to an external memory.

Referring to <FIG>, the virtual secure DMA circuitry may perform a hash operation using a hash key HK on a first packet including first data D and an ARC. The ARC may be set before performing the hash operation and stored in a NVM within the secure element SE.

A first tag T may be generated as a result of the hash operation, and the virtual secure DMA circuitry may perform an encryption operation using an encryption key EK on a second packet including the first tag T and the first data D.

As a result of the encryption operation, the first secure data SD may be generated, and the virtual secure DMA circuitry may transmit the first secure data SD together with an address ADD to the SoC through an SE interface circuitry.

Referring further to <FIG>, the virtual secure DMA circuitry may receive the second secure data SD' from the SoC through the SE interface circuitry, and perform a decryption operation on the second secure data SD' using a decryption key DK. The decryption key DK may correspond to the encryption key EK.

As a result of the decryption operation, a third packet including a second tag T' and second data D' may be generated. The virtual secure DMA circuitry may perform a hash operation using the hash key HK on a fourth packet including the second data D' and the ARC read from the NVM to generate a third tag T".

The virtual secure DMA circuitry may perform integrity verification on the second data D' by comparing the second tag T' to the third tag T". For example, when the second tag T' is not identical to the third tag T" (NO), it may be determined that the integrity verification has failed, and a determination result may be notified to the secure processor. As an example, when the second tag T' is identical to the third tag T" (YES), it may be determined that the integrity verification has been successful and the second data D' may be provided to the secure processor. According to some embodiments, the electronic device <NUM> may perform an operation (e.g., a calculation operation, a processing operation, a communication operation, etc.) based on the second data D' having been verified as secure.

According to some example embodiments, improved devices as disclosed herein may improve reliability and structural robustness of the electronic device <NUM>, while allowing for the integrity verification and access to sufficient memory spaces as required to manage the data D. Accordingly, improved devices may maintain normal operation, while being able to verify integrity, with sufficient reliability, and thereby reduce the occurrence of erroneous operation, delay and/or resource consumption (power, processor, memory, etc.).

<FIG> is a block diagram illustrating an electronic device <NUM>' according to some example embodiments. In <FIG>, the same description as that of <FIG> is omitted.

Referring to <FIG>, as compared to the SE <NUM> of <FIG>, an SE <NUM>' may further include a second SE interface <NUM>, and virtual secure DMA circuitry <NUM>' may further include a switching module 112_2. Compared to the SoC <NUM> of <FIG>, the SoC <NUM>' may further include a second interface <NUM>, second DMA circuitry <NUM>, and a second I/O interface <NUM>. Also, compared to the external memory <NUM> of <FIG>, an external memory <NUM>' may further include a second region <NUM>. However, in <FIG>, the SE <NUM>' is illustrated as including first and second SE interfaces <NUM> and <NUM>, but this is only some example embodiments, and the inventive concepts are not limited thereto and may include more SE interfaces, and accordingly, the SoC <NUM>' may include more interfaces to correspond thereto.

In some example embodiments, the first SE interface <NUM> and the second SE interface <NUM> may support different communication rates. For example, the first SE interface <NUM> may support a higher communication rate than the second SE interface <NUM>. In some example embodiments, the first SE interface <NUM> and the second SE interface <NUM> may support different communication types.

In some example embodiments, the switching module 112_2 may control a connection between any one of the first and second SE interfaces <NUM> and <NUM> and the first submodule 112_1. In some example embodiments, the switching module 112_2 may select any one of the first and second SE interfaces <NUM> and <NUM> based on a data update frequency of the executed secure application among the first to n-th secure applications 116_1 to 116_n, and connect a selected one to the first submodule 112_1. As an example, when the data update frequency of the executed secure application is equal to or greater than a reference frequency, the switching module 112_2 may select the first SE interface <NUM> supporting a relatively high communication rate and connect the first SE interface <NUM> to the first submodule 112_1. As an example, when the data update frequency of the executed secure application is less than the reference frequency, the switching module 112_2 may select the second SE interface <NUM> supporting a relatively low communication rate and connect the second SE interface <NUM> to the first submodule 112_1.

In some example embodiments, the switching module 112_2 may select any one of the first and second SE interfaces <NUM> and <NUM> based on an operating mode of the SOC <NUM>' and connect the selected one to the first submodule 112_1. As an example, when the operating mode of the SOC <NUM>' is a high power mode, the switching module 112_2 may select the first SE interface <NUM> supporting a relatively high communication rate and connect the first SE interface <NUM> to the first submodule 112_1. As an example, when the operating mode of the SOC <NUM>' is a low power mode, the switching module 112_2 may select the second SE interface <NUM> supporting a relatively low communication rate and connect the second SE interface <NUM> to the first submodule 112_1.

In some example embodiments, the first interface <NUM> may communicate with the first SE interface <NUM>, and may support the same communication rate and communication method as those of the first SE interface <NUM>. The second interface <NUM> may communicate with the second SE interface <NUM>, and may support the same communication rate and communication method as those of the second SE interface <NUM>.

In some example embodiments, the second interface <NUM> may transmit secure data, an address, a write request, and a read request received from the second SE interface <NUM> to the second DMA circuitry <NUM>. The second interface <NUM> may transmit the secure data received from the second DMA circuitry <NUM> to the second SE interface <NUM>.

In some example embodiments, in response to the write request received from the second SE interface <NUM>, the second DMA circuitry <NUM> may write secure data to the second region <NUM> of the external memory <NUM>' through the second I/O interface <NUM>. The second DMA circuitry <NUM> may read secure data from the second region <NUM> of the external memory <NUM> through the second I/O interface <NUM>.

In some example embodiments, the first region <NUM> of the external memory <NUM>' may be connected exclusively by the first DMA circuitry <NUM>, and the second region <NUM> of the external memory <NUM>' may be connected exclusively by the second DMA circuitry <NUM>.

In some example embodiments, the first and second regions <NUM> and <NUM> may be physically or logically distinguished from each other for each secure application so that secure data corresponding to each of the first to n-th secure applications 116_1 to 116_n may be stored separately.

In some example embodiments, the SE <NUM>' may select any one of the first and second SE interfaces <NUM> and <NUM>, and perform a secure operation using the external memory <NUM>' using the selected SE interface.

<FIG> is a flowchart illustrating an operating method of an SE according to some example embodiments.

Referring to <FIG>, in operation S300, the SE may execute any one of a plurality of secure applications. In some example embodiments, the SE may receive a signal requesting or instructing to select and execute any one of the secure applications from the SoC, and execute a selected SE in response to the signal.

In operation S310, the SE may select any one of a plurality of SE interfaces included in an SE interface circuitry based on the executed secure application.

In operation S320, the SE may transmit and receive secure data to and from the SoC through the selected SE interface. In some example embodiments, the SE may perform a secure operation using an external memory of the SoC through the selected SE interface.

<FIG> is a block diagram illustrating an electronic device <NUM>" according to some example embodiments. In <FIG>, the same description as that of <FIG> and <FIG> is omitted.

Referring to <FIG>, compared to the SE <NUM> of <FIG>, the SE <NUM>" may further include a second SE interface <NUM>, and virtual secure DMA circuitry <NUM>" may further include a second submodule 112_3. Compared to the SoC <NUM> of <FIG>, the SoC <NUM>" may further include the second interface <NUM>, the second DMA circuitry <NUM>, and the second I/O interface <NUM>. Also, compared to the external memory <NUM> of <FIG>, an external memory <NUM>" may further include the second region <NUM>.

In some example embodiments, the first SE interface <NUM> may support the same or different communication rate as that of the second SE interface <NUM>. In some example embodiments, the first SE interface <NUM> and the second SE interface <NUM> may support the same or different communication types.

In some example embodiments, the first SE interface <NUM> may be exclusively allocated to the first submodule 112_1, and the second SE interface <NUM> may be allocated exclusively to the second submodule 112_3.

In some example embodiments, the first submodule 112_1 may select any one of the first to n-th secure applications 116_1 to 116_n and perform a secure operation based on the selected secure application. The second submodule 112_3 may select another one of the first to n-th secure applications 116_1 to 116_n to perform a secure operation based on the selected secure application.

In some example embodiments, the first and second submodules 112_1 and 112_3 may perform a secure operation using the external memory <NUM>" in parallel with each other by using the first and second SE interfaces <NUM> and <NUM>, respectively. In some example embodiments, the first and second submodules 112_1 and 112_3 may each complementarily perform a secure operation using the external memory <NUM>". In detail, the first submodule 112_1 may perform a secure operation based on any one of some of the first to n-th secure applications 116_1 to 116_n, and the second submodule 112_3 may perform a secure operation based on any one of the rest of the first to n-th secure applications 116_1 to 116_n.

In some example embodiments, the first and second DMA circuitries <NUM> and <NUM> may perform a memory operation in response to a request from the SE <NUM>" using the first and second interfaces <NUM> and <NUM> and the first and second I/O interfaces <NUM> and <NUM>. The first and second DMA circuitries <NUM> and <NUM> may perform memory operations in parallel with each other. In some example embodiments, the first and second DMA circuitries <NUM> and <NUM> may each perform a secure operation complementarily.

<FIG> is a block diagram illustrating an electronic device <NUM>‴ according to some example embodiments. With respect to <FIG>, the same descriptions as those of <FIG>, <FIG> and <FIG> are omitted.

Referring to <FIG>, compared to the SE <NUM> of <FIG>, an SE <NUM>‴ may further include a second SE interface <NUM> and virtual secure DMA circuitry <NUM>‴ may further include a second submodule 112_3 and a switching module 112_4. In addition, compared to the SoC <NUM> of <FIG>, an SoC <NUM>‴ may further include the second interface <NUM>, the second DMA circuitry <NUM>, and the second I/O interface <NUM>. Also, compared to the external memory <NUM> of <FIG>, the external memory <NUM>‴ may include the second region <NUM>.

In some example embodiments, the first SE interface <NUM> and the second SE interface <NUM> may support different communication rates. For example, the first SE interface <NUM> may support a higher communication rate than that of the second SE interface <NUM>. In some example embodiments, the first SE interface <NUM> and the second SE interface <NUM> may support different communication types.

In some example embodiments, the first and second submodules 112_1 and 112_2 may perform a secure operation using the external memory <NUM>‴ in parallel to each other by using the first and second SE interfaces <NUM> and <NUM>, respectively. In some example embodiments, the first and second submodules 112_1 and 112_3 may each perform a secure operation using the external memory <NUM>‴ complementarily.

In some example embodiments, the switching module 112_4 may control a connection between the first and second SE interfaces <NUM> and <NUM> and the first and second submodules 112_1 and 112_3. In some example embodiments, the switching module 112_4 may control a connection between the first and second SE interfaces <NUM> and <NUM> and the first and second submodules 112_1 and 112_3 based on secure applications based on each of the first and second submodules 112_1 and 112_3. For example, the switching module 112_4 may connect the first SE interface <NUM> supporting a relatively high communication rate to the first submodule 112_1, and connect the second SE interface <NUM> supporting a relatively low rate to the second submodule 112_3. In addition, the switching module 112_4 may connect the second SE interface <NUM> supporting a relatively low communication rate to the first submodule 112_1, and may connect the first SE interface <NUM> supporting a relatively high rate to the second submodule 112_3.

Referring to <FIG>, the electronic device <NUM> may include an SoC <NUM>, a first SE <NUM>, a second SE <NUM>, and an external memory <NUM>. The SoC <NUM> may include first and second interface circuitries <NUM> and <NUM>. The first SE <NUM> may include first SE interface circuitry <NUM>. The second SE <NUM> may include second SE interface circuitry <NUM>. The external memory <NUM> may include first and second regions <NUM> and <NUM>.

In some example embodiments, the first SE <NUM> may connect to the external memory <NUM> through communication with the first interface circuitry <NUM> of the SoC <NUM> through the first SE interface circuitry <NUM> to perform a secure operation. In detail, the first SE <NUM> may perform a secure operation using the first region <NUM> of the external memory <NUM> connected to the SoC <NUM>.

In some example embodiments, the second SE <NUM> may connect to the external memory <NUM> through communication with the second interface circuitry <NUM> of the SoC <NUM> through the second SE interface circuitry <NUM> to perform a secure operation. In detail, the second SE <NUM> may perform a secure operation using the second region <NUM> of the external memory <NUM> connected to the SoC <NUM>.

In some example embodiments, the first region <NUM> may store secure data of the first SE <NUM>, and the second region <NUM> may store secure data of the second SE <NUM>. For example, the first region <NUM> may be physically or logically separated from the second region <NUM>.

However, <FIG> is only some example embodiments, and the inventive concepts are not limited thereto, and the electronic device <NUM> may further include more SEs, the SoC <NUM> may further include interface circuities for communicating with more SEs, and the external memory <NUM> may further include regions for storing secure data of more SEs.

<FIG> is a block diagram illustrating an electronic device, according to some example embodiments.

Referring to <FIG>, the electronic device <NUM> may include a first IC <NUM>, a second IC <NUM>, a first external memory <NUM>, and a second external memory <NUM>.

In some example embodiments, the first IC <NUM> may include a first processor <NUM>, first virtual secure DMA circuitry <NUM>, first interface circuitry <NUM>, first DMA circuitry <NUM>, first I/O interface circuitry <NUM>, a first bus <NUM>, and a first pin P1. The first IC <NUM> may be connected to the first external memory <NUM>.

In some example embodiments, the second IC <NUM> may include a second processor <NUM>, second virtual secure DMA circuitry <NUM>, second interface circuitry <NUM>, second DMA circuitry <NUM>, second I/O circuitry <NUM>, a second bus <NUM>, and a second pin P2. The second IC <NUM> may be connected to the second external memory <NUM>.

In some example embodiments, the first IC <NUM> may store first data processed by the first processor <NUM> in the second external memory <NUM> of the second IC <NUM>. The first IC <NUM> may generate first secure data from the first data and store the generated first secure data in the second external memory <NUM> in order to prevent or reduce access, forgery, tampering, and the like.

In detail, the first virtual secure DMA circuitry <NUM> may generate first secure data from the first data. A method of generating the first secure data by the first virtual secure DMA circuitry <NUM> may vary. The first virtual secure DMA circuitry <NUM> may transmit the first secure data and a write request to the second IC <NUM> through the first interface circuitry <NUM>. In response to the write request, the second DMA circuitry <NUM> may write the first secure data received through the second interface circuitry <NUM> to the second external memory <NUM> through the second I/O interface circuitry <NUM>.

Also, the first virtual secure DMA circuitry <NUM> may transmit a read request to the second IC <NUM> through the first interface circuitry <NUM>. In response to the read request, the second DMA circuitry <NUM> may read the first secure data from the second external memory <NUM> through the second interface circuitry <NUM>. The second DMA circuitry <NUM> may transmit the read first secure data to the first IC <NUM> through the second interface circuitry <NUM>. The first virtual secure DMA circuitry <NUM> may perform a verification operation on the first secure data received through the first interface circuitry <NUM>.

In some example embodiments, the first virtual secure DMA circuitry <NUM> may receive a first signal indicating whether the second external memory <NUM> is available from the second IC <NUM> through the first pin P1 and perform a generating operation or a verification operation on the first secure data based on the first signal.

In some example embodiments, the first virtual secure DMA circuitry <NUM> may perform an operation based on an executed secure application among a plurality of secure applications, and the first interface circuitry <NUM> may operate at a communication rate according to the executed secure application.

In some example embodiments, the second IC <NUM> may store the second data processed by the second processor <NUM> in the first external memory <NUM> of the first IC <NUM>. The second IC <NUM> may generate second secure data from the second data and store the generated second secure data in the first external memory <NUM> in order to prevent or reduce access, forgery, tampering, etc. of the second data in the first IC <NUM>. Details thereof are the same as those of the first IC <NUM>, and thus, a description thereof is omitted.

In some example embodiments, the second virtual secure DMA circuitry <NUM> may receive a second signal indicating whether the first external memory <NUM> is available from the first IC <NUM> through the second pin P2 and perform a generating operation or a verification operation on the second secure data based on the second signal.

In some example embodiments, the second virtual secure DMA circuitry <NUM> may perform an operation based on an executed secure application among a plurality of secure applications, and the second interface circuitry <NUM> may operate at a communication rate according to the executed secure application.

As shown in <FIG>, each of the first and second ICs <NUM> and <NUM> may complementarily perform a memory operation including a secure operation using the first and second external memories <NUM> and <NUM>. That is, the first IC <NUM> may use the second external memory <NUM> connected to the second IC <NUM> when a usable capacity of the first external memory <NUM> is insufficient. The second IC <NUM> may use the first external memory <NUM> connected to the first IC <NUM> when a usable capacity of the second external memory <NUM> is insufficient.

Referring to <FIG>, the electronic device <NUM> may include first to fourth ICs <NUM> to <NUM> and first to fourth external memories <NUM> to <NUM>. The first to fourth ICs <NUM> to <NUM> may be connected to the first to fourth external memories <NUM> to <NUM>, respectively.

In some example embodiments, each of the first to fourth ICs <NUM> to <NUM> may perform a memory operation using an external memory connected to another IC when a usable capacity of an external memory connected thereto is insufficient. The corresponding memory operation may include a secure operation according to some example embodiments.

In some example embodiments, each of the first to fourth ICs <NUM> to <NUM> may include interface circuitry for communicating with each other and virtual secure DMA circuitry for performing a secure operation. Furthermore, each of the first to fourth ICs <NUM> to <NUM> may include a pin for transmitting and receiving a signal in order to share whether an external memory thereof is available.

Each of the first to fourth ICs <NUM> to <NUM> may have the same or different functions. In addition, each of the first to fourth ICs <NUM> to <NUM> may be generated by the same or different semiconductor processes.

<FIG> is a flowchart illustrating an operating method of an IC according to some example embodiments. The IC may be one of a plurality of ICs.

Referring to <FIG>, in operation S400, the IC may determine to use a memory of another IC.

In operation S410, the IC may search for an IC having an available memory space among a plurality of other ICs.

In operation S420, the IC may perform a memory operation using an external memory connected to a searched IC. The corresponding memory operation may include a secure operation according to some example embodiments.

<FIG> is a conceptual diagram illustrating an Internet of things (IoT) network system <NUM> to which embodiments are applied.

Referring to <FIG>, the IoT network system <NUM> may include a plurality of IoT devices <NUM>, <NUM>, <NUM>, and <NUM>, an access point <NUM>, a gateway <NUM>, a wireless network <NUM>, and a server <NUM>. The IoT may refer to a network between things using wired/wireless communication.

Each of the IoT devices <NUM>, <NUM>, <NUM>, and <NUM> may form a group according to characteristics of each IoT device. For example, IoT devices may be grouped into a home gadget group <NUM>, a home appliance/furniture group <NUM>, an entertainment group <NUM>, or a vehicle group <NUM>. The IoT devices <NUM>, <NUM>, and <NUM> may be connected to a communication network or connected to other IoT devices through the access point <NUM>. The access point <NUM> may be embedded in one IoT device. The gateway <NUM> may change a protocol to connect the access point <NUM> to an external wireless network. The IoT devices <NUM>, <NUM>, and <NUM> may be connected to an external communication network through the gateway <NUM>. The wireless network <NUM> may include the Internet and/or a public network. The IoT devices <NUM>, <NUM>, <NUM>, and <NUM> may be connected to the server <NUM> providing a certain service through the wireless network <NUM>, and a user may use a service through at least one of the IoT devices <NUM>, <NUM>, <NUM>, and <NUM>.

According to some example embodiments, each of the IoT devices <NUM>, <NUM>, <NUM>, and <NUM> may include an SE and an SoC, and the SE may perform a secure operation using an external memory connected to the SoC. Through this, the IoT devices <NUM>, <NUM>, <NUM>, and <NUM> may perform an effective secure operation to provide a safe quality service to the user.

Claim 1:
A secure element (<NUM>) coupled to a system-on-chip (<NUM>), hereinafter referred to as SoC, the secure element comprising:
an internal memory (<NUM>);
virtual secure direct memory access, hereinafter referred to as DMA, circuitry (<NUM>) configured to perform a secure operation using an external memory connected to the SoC in association with the internal memory;
secure element interface circuitry (<NUM>) configured to output first secure data and a write request generated by the virtual secure DMA circuitry to the SoC; and
a memory management unit, MMU (<NUM>), configured to manage available pages of the internal memory using a translation lookaside buffer, TLB (<NUM>);
wherein the virtual secure DMA circuitry is configured to perform the secure operation based on the absence of available pages determined using the MMU (<NUM>) and the TLB (<NUM>),
the first secure data being stored in the external memory.