Patent Description:
Display devices, such as a liquid crystal display (LCD), an organic light emitting diode display (OLED display), an electrophoretic display, and the like, typically include a field generating electrode and an electro-optical active layer. For example, an organic light emitting device includes an organic emission layer as an electro-optical active layer. The field generating electrode may be connected to a switching element, such as a thin film transistor, and may receive a data signal. The electro-optical active layer displays images by converting the data signal into an optical signal. Reference is made to <CIT>, <CIT>, <CIT>, <CIT>, <CIT>.

Document <CIT> is the most relevant document of the prior art and discloses the features of the preamble of claims <NUM> and <NUM>.

When an impurity, such as moisture or oxygen, is introduced into the display device from the outside, a lifespan of an electrical element included in the display device may be reduced, and emission efficiency of an emission layer of the organic light emitting device may be deteriorated. To prevent this, when the display device is manufactured, it is encapsulated by isolating the internal electrical elements from the outside so that the impurity, such as moisture, may not permeate the display device, and an encapsulation method may include a method for forming an encapsulation portion by stacking a plurality of thin films on a display area.

A touch sensor for a user to contact a screen with a finger or a pen and input information may be applied as an input device of the display device. From among various sensing methods of a touch unit including a touch sensor, a capacitive type for sensing a position where a change of capacitance caused by a contact at (or near) two electrodes separated from each other is used. When a height of an insulating layer disposed below the touch unit is not constant or includes steps, parasitic capacitance between an electrode (e.g., cathode) formed below the touch unit and a touch electrode of the touch unit may increase at a portion where the insulating layer disposed below the touch unit is thin. When unnecessary parasitic capacitance becomes larger between the touch electrode and a lower electrode, it may influence the touch sensing characteristic of the touch sensor of the touch unit.

Light emitted by the display area including a plurality of pixel areas for displaying images may be reflected again by the touch electrode of the touch unit overlapping the display area, the light reflected in this way may leak toward the edge of the display area and may be seen as a light leakage at the edge of the display area. In this manner, the light leakage becomes a cause of deteriorating display quality of the display device.

The above information disclosed in this section is only for understanding the background of the inventive concepts, and, therefore, may contain information that does not form prior art.

Some exemplary embodiments provide a display device capable of preventing changes in touch sensitivity of a touch unit of a display device and preventing light leakage at an edge of a display area.

Some exemplary embodiments provide a manufacturing method of a display device capable of preventing changes in touch sensitivity of a touch unit of a display device and preventing light leakage at an edge of a display area.

Additional aspects will be set forth in the detailed description which follows, and, in part, will be apparent from the disclosure, or may be learned by practice of the inventive concepts.

The present invention is defined in independent claims <NUM> and <NUM>. Further aspects of the invention are defined in the dependent claims.

In some exemplary embodiments, the touch unit may include touch electrodes and touch wires connected to the touch electrodes, and the cover layer may overlap the touch wires.

In some exemplary embodiments, the display device may further include a driving voltage line and spacers disposed in the non-display area. In a view perpendicular to the surface of the substrate, the cover layer may overlap the driving voltage line. In the view perpendicular to the surface of the substrate, the cover layer may overlap a first spacer among the spacers and may be spaced apart from a second spacer among the spacers.

In some exemplary embodiments, the thin film encapsulation layer may include inorganic insulating layers and at least one organic insulating layer, and in a direction perpendicular to the surface of the substrate, the inorganic insulating layers of the thin film encapsulation layer may be disposed between the cover layer and the substrate.

In some exemplary embodiments, the thin film encapsulation layer may include inorganic insulating layers and at least one organic insulating layer, and in a direction perpendicular to the surface of the substrate, the organic insulating layer and the cover layer may be disposed between at least two of the inorganic insulating layers of the thin film encapsulation layer.

The foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter.

The accompanying drawings, which are included to provide a further understanding of the inventive concepts, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the inventive concepts, and, together with the description, serve to explain principles of the inventive concepts.

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments.

Unless otherwise specified, the illustrated exemplary embodiments are to be understood as providing exemplary features of varying detail of some exemplary embodiments. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, aspects, etc. (hereinafter individually or collectively referred to as an "element" or "elements"), of the various illustrations may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

In the accompanying drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes.

When an element is referred to as being "on," "connected to," or "coupled to" another element, it may be directly on, connected to, or coupled to the other element or intervening elements may be present. When, however, an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. Other terms and/or phrases used to describe a relationship between elements should be interpreted in a like fashion, e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," "on" versus "directly on," etc. Further, the term "connected" may refer to physical, electrical, and/or fluid connection.

Although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. For the purposes of this disclosure, the phrase "on a plane" or "in a plan view" means viewing an object portion from above, and the phrase "on a cross-section" or "in a cross-sectional view" means viewing, from a side, a cross-section of which the object portion is vertically cut.

Spatially relative terms, such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), and the like, may be used herein for descriptive purposes, and, thereby, to describe one element's relationship to another element(s) as illustrated in the drawings.

Thus, exemplary embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. In this manner, regions illustrated in the drawings may be schematic in nature and shapes of these regions may not reflect the actual shapes of regions of a device, and, as such, are not intended to be limiting.

Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

As customary in the field, some exemplary embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and/or modules. Those skilled in the art will appreciate that these blocks, units, and/or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies. In the case of the blocks, units, and/or modules being implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform various functions discussed herein and may optionally be driven by firmware and/or software. It is also contemplated that each block, unit, and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Also, each block, unit, and/or module of some exemplary embodiments may be physically separated into two or more interacting and discrete blocks, units, and/or modules without departing from the inventive concepts. Further, the blocks, units, and/or modules of some exemplary embodiments may be physically combined into more complex blocks, units, and/or modules without departing from the inventive concepts.

A display device according to some exemplary embodiments will now be described with reference to <FIG>. <FIG> shows a top plan view of a display device according to some exemplary embodiments. <FIG> shows a cross-sectional view of part of a display device according to some exemplary embodiments. <FIG> shows an equivalent circuit diagram of a pixel of a display device according to some exemplary embodiments.

Referring to <FIG>, a display device <NUM> includes a display area DA for displaying an image, and a non-display area NDA disposed outside the display area DA.

The non-display area NDA includes a driving area PA. In the driving area PA, a driver <NUM> connected to driving signal lines w10, w20, and w30 for transmitting a signal to the display area DA and applying a driving voltage to the driving signal lines w10, w20, and w30 is disposed. The driving signal lines w10, w20, and w30 include touch wires w10 and w20 and a common voltage transmitting line w30.

The display area DA includes a plurality of pixels (not shown), and it includes a touch unit including a touch electrode <NUM> overlapping the display area DA. A configuration of a display area DA and a non-display area NDA of a display device <NUM> according to some exemplary embodiments will be described with reference to <FIG> and <FIG>.

Referring to <FIG>, the display area DA of the display device <NUM> includes a plurality of signal lines <NUM>, <NUM>, and <NUM>, and a plurality of pixels PXs connected thereto and substantially arranged in a matrix form. The pixel PX represents a minimum unit for displaying an image, and the display device <NUM> displays images using a plurality of pixels PXs.

The signal lines <NUM>, <NUM>, and <NUM> include a plurality of gate lines <NUM> for transmitting a gate signal (or a scanning signal), a plurality of data lines <NUM> for transmitting a data signal, and a plurality of driving voltage lines <NUM> for transmitting a driving voltage ELVDD. The gate lines <NUM> substantially extend in a first (e.g., row) direction and are substantially parallel with each other, and vertical portions of the data line <NUM> and the driving voltage line <NUM> substantially extend in a second (e.g., column) direction and are substantially parallel with each other.

The pixel PX includes a switching thin film transistor Qs, a driving thin film transistor Qd, a storage capacitor Cst, and an organic light emitting diode (OLED) LD. Although not shown in the drawings, one pixel PX may further include at least one thin film transistor and at least one capacitor so as to compensate an output current ILD supplied to the organic light emitting diode LD.

The switching thin film transistor Qs includes a control terminal, an input terminal, and an output terminal, and the control terminal is connected to the gate line <NUM>, the input terminal is connected to the data line <NUM>, and the output terminal is connected to the driving thin film transistor Qd. The switching thin film transistor Qs transmits the data signal applied to the data line <NUM> to the driving thin film transistor Qd in response to the scanning signal applied to the gate line <NUM>.

The driving thin film transistor Qd also includes a control terminal, an input terminal, and an output terminal, and the control terminal is connected to the switching thin film transistor Qs, the input terminal is connected to the driving voltage line <NUM>, and the output terminal is connected to the organic light emitting diode LD. The driving thin film transistor Qd provides an output current ILD that is variable by the voltage between the control terminal and the output terminal.

The storage capacitor Cst is connected between the control terminal and the input terminal of the driving thin film transistor Qd. The storage capacitor Cst charges the data signal applied to the control terminal of the driving thin film transistor Qd, and maintains it when the switching thin film transistor Qs is turned off.

The organic light emitting diode LD includes an anode connected to the output terminal of the driving thin film transistor Qd, and a cathode connected to a common voltage ELVSS. The organic light emitting diode LD displays images by emitting light with different intensities according to the output current ILD of the driving thin film transistor Qd.

An inter-layer configuration of the display device <NUM> will now be described with reference to <FIG>.

As described above, the display device <NUM> includes a display area DA and a non-display area NDA.

The display device <NUM> includes a substrate <NUM>, and the substrate <NUM> is flexible.

A buffer layer <NUM> is disposed on the substrate <NUM>. The buffer layer <NUM> may include a single layer of an insulating material, such as a silicon nitride (SiNx) or a silicon oxide (SiOx), or a plurality of layers forming a stack of insulating layers, each insulating layer including at least one of silicon nitride (SiNx) and silicon oxide (SiOx). The buffer layer <NUM> may prevent permeation of unnecessary components, such as impurities or moisture.

A first semiconductor layer <NUM> is disposed on the buffer layer <NUM> of the display area DA. The first semiconductor layer <NUM> may include polysilicon or an oxide semiconductor. In this instance, the oxide semiconductor may include one of an oxide made of titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In), or a compound oxide thereof.

The first semiconductor layer <NUM> includes a first channel region <NUM>, and a first source region <NUM> and a first drain region <NUM> disposed on respective sides of the first channel region <NUM>. The first channel region <NUM> of the first semiconductor layer <NUM> may be a region in which no impurity is doped, and the first source region <NUM> and the first drain region <NUM> of the first semiconductor layer <NUM> may be regions in which a conductive impurity is doped.

In a like manner, a second semiconductor layer <NUM> is disposed on the buffer layer <NUM> of the non-display area NDA. The second semiconductor layer <NUM> includes a second channel region <NUM>, and a second source region <NUM> and a second drain region <NUM> disposed on respective sides of the second channel region <NUM>.

A gate insulating layer <NUM> is disposed on the first semiconductor layer <NUM> and the second semiconductor layer <NUM>. The gate insulating layer <NUM> may be a single layer including tetraethyl orthosilicate (TEOS), a silicon oxide (SiOx), or a silicon nitride (SiNx), or a multilayer structure generated by stacking at least some of the aforementioned materials.

A first gate electrode <NUM> and a second gate electrode <NUM> are disposed on the gate insulating layer <NUM>. The first gate electrode <NUM> overlaps the first channel region <NUM>, and the second gate electrode <NUM> overlaps the second channel region <NUM>.

The first gate electrode <NUM> and the second gate electrode <NUM> may be a single layer or a multilayer structure including a low-resistance material, such as aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), nickel (Ni), or an alloy thereof, or a high corrosion-resistant material.

A first interlayer insulating layer <NUM> is disposed on the first gate electrode <NUM> and the second gate electrode <NUM>. The first interlayer insulating layer <NUM> may be a single layer including tetraethyl orthosilicate (TEOS), a silicon oxide (SiOx), or a silicon nitride (SiNx), or a multilayer structure generated by stacking at least some of the aforementioned materials.

The first interlayer insulating layer <NUM> and the gate insulating layer <NUM> include a first source contact hole <NUM> and a first drain contact hole <NUM> respectively overlapping the first source region <NUM> and the first drain region <NUM>, and a second source contact hole <NUM> and a second drain contact hole <NUM> respectively overlapping the second source region <NUM> and the second drain region <NUM>.

A first source electrode <NUM> and a first drain electrode <NUM>, and a second source electrode <NUM> and a second drain electrode <NUM>, are disposed on the first interlayer insulating layer <NUM>. Further, a common voltage transmitting line w30 is disposed on the first interlayer insulating layer <NUM> in the non-display area NDA.

The first source electrode <NUM> and the first drain electrode <NUM> are respectively connected to the first source region <NUM> and the first drain region <NUM> of the first semiconductor layer <NUM> through the first source contact hole <NUM> and the first drain contact hole <NUM>. Similarly, the second source electrode <NUM> and the second drain electrode <NUM> are respectively connected to the second source region <NUM> and the second drain region <NUM> of the second semiconductor layer <NUM> through the second source contact hole <NUM> and the second drain contact hole <NUM>.

The first source electrode <NUM> and the first drain electrode <NUM>, and the second source electrode <NUM>, and the second drain electrode <NUM> may be a single layer or a multilayer structure including a low-resistance material, such as aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), nickel (Ni), or an alloy thereof, or a high corrosion-resistant material. The common voltage transmitting line w30 may be simultaneously formed on the same layer as the first source electrode <NUM> and the first drain electrode <NUM>, and the second source electrode <NUM> and the second drain electrode <NUM>.

The first semiconductor layer <NUM>, the first gate electrode <NUM>, the first source electrode <NUM>, and the first drain electrode <NUM> of the display area DA may configure the driving thin film transistor Qd of the pixel PX shown in <FIG>, and the second semiconductor layer <NUM>, the second gate electrode <NUM>, the second source electrode <NUM>, and the second drain electrode <NUM> of the non-display area NDA may configure a thin film transistor included in a gate driver disposed in the non-display area NDA. Although <FIG> shows one transistor in each of the display area DA and the non-display area NDA, but this is disposed for ease of description, exemplary embodiments are not limited thereto.

A second interlayer insulating layer <NUM> is disposed on the first source electrode <NUM>, the first drain electrode <NUM>, the second source electrode <NUM>, and the second drain electrode <NUM>. The second interlayer insulating layer <NUM>, in a like manner as the first interlayer insulating layer <NUM>, may be a single layer including tetraethyl orthosilicate (TEOS), a silicon oxide (SiOx), or a silicon nitride (SiNx), or a multilayer structure generated by stacking at least some of the aforementioned materials.

The second interlayer insulating layer <NUM> includes a contact hole <NUM> overlapping the first drain electrode <NUM>. The second interlayer insulating layer <NUM> is removed from the region overlapping the common voltage transmitting line w30, most of the common voltage transmitting line w30 does not overlap the second interlayer insulating layer <NUM>, and part of an edge of the common voltage transmitting line w30 may overlap the second interlayer insulating layer <NUM>. However, the entire portion of the common voltage transmitting line w30 may not overlap the second interlayer insulating layer <NUM>.

A pixel electrode <NUM> is disposed on the second interlayer insulating layer <NUM>. The pixel electrode <NUM> may be an anode of the organic light emitting diode LD of <FIG>. The second interlayer insulating layer <NUM> is disposed between the pixel electrode <NUM> and the first drain electrode <NUM> according to some exemplary embodiments, but it may be disposed on a same layer as the pixel electrode <NUM> and the first drain electrode <NUM>, and it may be integrally formed with the first drain electrode <NUM>.

A partition wall <NUM> is disposed on the pixel electrode <NUM>. The partition wall <NUM> includes an opening <NUM> overlapping the pixel electrode <NUM>. The partition wall <NUM> may include a resin, such as a polyacrylate or a polyimide, and a silica-based inorganic material.

An organic emission layer <NUM> is disposed in the opening <NUM> of the partition wall <NUM>. The organic emission layer <NUM> may have multiple layers including at least one of an emission layer, a hole injection layer (HIL), a hole transporting layer (HTL), an electron transporting layer (ETL), and an electron injection layer (EIL). When the organic emission layer <NUM> includes all of the aforementioned layers, a hole injection layer may be disposed on the pixel electrode <NUM> that is an anode, and a hole transporting layer, an emission layer, an electron transporting layer, and an electron injection layer may be sequentially stacked thereon.

A common electrode <NUM> is disposed on the partition wall <NUM> and the organic emission layer <NUM>. The common electrode <NUM> is a cathode of the organic light emitting diode LD. In this manner, the pixel electrode <NUM>, the organic emission layer <NUM>, and the common electrode <NUM> configure an organic light emitting diode (or element) <NUM>. The organic light emitting device may be one of front display type, a rear display type, and a both-side display type according to the direction in which the organic light emitting diode <NUM> emits light.

In the case of the front display type, the pixel electrode <NUM> may be a reflective layer, and the common electrode <NUM> may be a semi-transflective layer or a transmissive layer. In the case of the rear display type, the pixel electrode <NUM> may be a transflective layer, and the common electrode <NUM> may be a reflective layer. In the case of the both-side display type, the pixel electrode <NUM> and the common electrode <NUM> may be a transparent layer or a transflective layer. The reflective layer and the transflective layer may be at least one metal, such as at least one of magnesium (Mg), silver (Ag), gold (Au), calcium (Ca), lithium (Li), chromium (Cr), and aluminum (Al), or an alloy thereof. The reflective layer and the transflective layer are determined by thickness, and the transflective layer may be formed to have a thickness that is equal to or less than <NUM>. As the thickness becomes smaller, transmittance of light increases, and when the thickness is much less, resistance increases. The transparent layer may include an indium tin oxide (ITO), an indium zinc oxide (IZO), a zinc oxide (ZnO), and/or an indium oxide.

The common electrode <NUM> may be disposed on a side of the substrate <NUM> including the display area DA and the non-display area NDA, and it contacts the common voltage transmitting line w30 of the non-display area NDA and receives the common voltage ELVSS.

A first spacer SP1 and a second spacer SP2 are disposed on an external side of the non-display area NDA. The first spacer SP1 and the second spacer SP2 may include a same layer as a part from among the second interlayer insulating layer <NUM> disposed in the display area DA and an insulating layer formed with the same layer as a partition wall <NUM>. That is, the first spacer SP1 may include the same layer as the second interlayer insulating layer <NUM> and the partition wall <NUM>, and the second spacer SP2 may further include an additional insulating layer in addition to the second interlayer insulating layer <NUM> and the partition wall <NUM>.

An encapsulation layer <NUM> is disposed on the common electrode <NUM>. The encapsulation layer <NUM> may be formed by alternately stacking at least one inorganic layer and at least one organic layer, and the number of the inorganic layer or the organic layer may be plural.

According to some exemplary embodiments, the encapsulation layer <NUM> includes a first inorganic encapsulation layer <NUM> and a second inorganic encapsulation layer <NUM>, and includes an organic encapsulation layer <NUM> disposed between the first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM>.

The first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM> are formed on a side of the substrate <NUM>, and are disposed on the first spacer SP1 and the second spacer SP2. The organic encapsulation layer <NUM> is not disposed on external sides of the first spacer SP1 and the second spacer SP2 in the non-display area NDA.

A thickness of the organic encapsulation layer <NUM> of the encapsulation layer <NUM> is reduced as it extends toward the edge of the display area DA, and accordingly, the height of an upper side of the organic encapsulation layer <NUM> is relatively and gradually reduced. To prevent the thickness of the organic encapsulation layer <NUM> of the encapsulation layer <NUM> from being reduced at the edge of the display area DA, the amount of the organic material layer is increased when the organic encapsulation layer <NUM> is formed so that an organic encapsulation layer <NUM> with sufficient thickness may be formed on the edge of the display area DA. However, in this case, a reflow amount of the organic material increases. The organic encapsulation layer <NUM> may then be formed up to the external sides of the first spacer SP1 and the second spacer SP2, and hence, the probability of the organic encapsulation layer <NUM> of the encapsulation layer <NUM> being exposed on the outermost edge of the display device <NUM> increases and vapor may permeate through the exposed organic encapsulation layer <NUM>, and the reliability of the display device <NUM> may be reduced. Therefore, in order for the organic encapsulation layer <NUM> of the encapsulation layer <NUM> to not be disposed up to the external sides of the first spacer SP1 and the second spacer SP2, the thickness of the organic encapsulation layer <NUM> of the encapsulation layer <NUM> is reduced on the edge of the display area DA by not increasing the amount of the organic material layer, so a surface height of the organic encapsulation layer <NUM> is reduced on the edge of the display area DA. That is, the upper side of the organic encapsulation layer <NUM> gradually becomes lower as it extends towards the external side of the display device <NUM> from the edge region of the display area DA disposed near the border of the display area DA and the non-display area NDA.

The thickness of the organic encapsulation layer <NUM> disposed on the edge of the display area DA is reduced, and a cover layer <NUM> is disposed on the edge of the organic encapsulation layer <NUM>. The cover layer <NUM> is disposed on the organic encapsulation layer <NUM> on the edge of the display area DA and the non-display area NDA, and the cover layer <NUM> includes a portion for covering the edge portion of the organic encapsulation layer <NUM> of which the height of the upper side is gradually reduced, and it compensates for a step of the organic encapsulation layer <NUM> of which the thickness is relatively reduced by the cover layer <NUM>. In this manner, the upper surfaces of the encapsulation layer <NUM> and the cover layer <NUM> become almost flat. Hence, the height of the encapsulation layer <NUM> is almost the same as the height of the cover layer <NUM>, so a gap between the substrate <NUM> and the upper surface of the encapsulation layer <NUM> is almost the same as a gap between the substrate <NUM> and the upper surface of the cover layer <NUM>.

The cover layer <NUM> is disposed on part of the edge of the display area DA and the non-display area NDA, and most thereof is disposed in the non-display area NDA. The cover layer <NUM> is disposed closer to the display area DA than is the second spacer SP2, which is disposed on the outermost part. That is, with respect to the display area DA, the cover layer <NUM> is not disposed to be further external than the second spacer SP2. The cover layer <NUM> is mainly disposed in the non-display area NDA, and overlaps the touch wires w10 and w20.

The cover layer <NUM> includes an organic material. Further, the cover layer <NUM> includes a light blocking material. The cover layer <NUM> may be formed on the encapsulation layer <NUM> by using a screen printing method or a photolithography method using a photosensitive organic material.

According to some exemplary embodiments, the cover layer <NUM> including an organic material includes a portion exposed to the outside, but the encapsulation layer <NUM> is disposed below the cover layer <NUM>, thereby preventing reduced reliability caused by vapor permeation. The encapsulation layer <NUM> includes a stacked inorganic layer, so when vapor permeates through the cover layer <NUM>, it does not reach the light-emitting device layer, e.g., the organic light emitting diode <NUM>, by passing through the encapsulation layer <NUM>.

Referring to <FIG> and <FIG>, a touch unit for sensing a touch is disposed on the encapsulation layer <NUM> and the cover layer <NUM>. Here, a touch may include a case in which an external object, such as a finger of a user, directly contacts a touch side of the display device <NUM>, and a case in which the external object hovers while it is approaching the touch side of the display device <NUM> or when it has approached the same. The touch unit may include a touch electrode <NUM> and touch wires w10 and w20 connected thereto. The touch electrode <NUM> receives a driving voltage from the touch wires w10 and w20. The touch electrode <NUM> may be disposed in the display area DA, and without being limited to this, it may be disposed in the non-display area NDA. The touch wires w10 and w20 may be disposed in the non-display area NDA, and they may include a portion disposed in the display area DA. The touch unit formed on the upper side of the display device <NUM> as described above will be referred to as an on-cell type.

According to some exemplary embodiments, the touch unit may include a plurality of touch electrodes <NUM>, and the touch electrodes <NUM> may include a first touch electrode <NUM> and a second touch electrode <NUM>. The first touch electrode <NUM> and the second touch electrode <NUM> may be alternately spread and disposed so that they may not overlap each other in the display area DA. The first touch electrode <NUM> and the second touch electrode <NUM> may be disposed on different layers.

The first touch electrode <NUM> includes a plurality of first electrode portions 91a and a plurality of first connectors 91b. A plurality of first electrode portions 91a of the first touch electrode <NUM> are disposed in the column direction and the row direction, respectively, and a plurality of the first electrode portions 91a of the first touch electrodes <NUM> arranged in the same column or row may be connected to each other through a plurality of first connectors 91b.

In a like manner, the second touch electrode <NUM> includes a plurality of second electrode portions 92a and a plurality of second connectors 92b. A plurality of second electrode portions 92a of the second touch electrode <NUM> are disposed in the column direction and the row direction respectively, and a plurality of the second electrode portions 92a of the second touch electrodes <NUM> arranged in the same column or row may be connected to each other through a plurality of second connectors 92b.

The first touch electrode <NUM> is connected to the first touch wire w10, and the second touch electrode <NUM> is connected to the second touch wire w20. The first touch electrode <NUM> and the second touch electrode <NUM> may have determined transmittance so that light emitted by the organic emission layer <NUM> may be transmitted therethrough. For example, the first touch electrode <NUM> and the second touch electrode <NUM> may be made of a thin metal layer, such as an indium tin oxide (ITO), an indium zinc oxide (IZO), or silver nanowire (AgNw), or a transparent conductive material, such as a metal mesh or carbon nanotubes (CNT), but exemplary embodiments are not limited thereto.

The first touch wire w10 and the second touch wire w20 may include a transparent conductive material included in a first touch electrode <NUM> and a second touch electrode <NUM>, or a low-resistance material, such as molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), or molybdenum/aluminum/molybdenum (Mo/Al/Mo).

First touch electrodes <NUM> neighboring each other and second touch electrodes <NUM> neighboring each other may form a self-sensing capacitance functioning as a touch sensor. The self-sensing capacitor may receive a sensing input signal and may be charged with a determined amount of charges, and when there is a contact of an external object, such as a finger, the stored amount of charges is changed and a sensing output signal that is different from the input sensing input signal may be output/sensed.

As described above, the touch unit is disposed on the encapsulation layer <NUM> having a flat surface and the cover layer <NUM>, so the gap between the common electrode <NUM> of the organic light emitting diode <NUM> and the first touch electrode <NUM> and the second touch electrode <NUM> of the touch unit may be constant (or substantially constant). By this, a difference of parasitic capacitance between the common electrode <NUM> and the first touch electrode <NUM> and the second touch electrode <NUM> of the touch unit may not be generated depending on a location. When a touch unit is formed on the encapsulation layer <NUM> having a step according to a position without a cover layer <NUM>, the parasitic capacitance between the first touch electrode <NUM> and the second touch electrode <NUM> of the touch unit formed on the edge portion of the encapsulation layer <NUM> that is relatively thin and the common electrode <NUM> becomes relatively larger and the touch sensitivity may accordingly reduce.

Further, light emitted by the organic emission layer <NUM> disposed on the edge of the display area DA may leak toward the edge of the display area DA, and by this, light leakage may be generated around the edge of the display area DA. However, as described above, as the cover layer <NUM> includes a light blocking material, it blocks the light leaking around the edge of the display area DA to thus prevent light leakage from occurring around the edge of the display area DA.

Although not shown, the display device <NUM> may further include an additional layer, such as a window on the touch unit.

A configuration of one pixel PX disposed in the display area DA of the display device <NUM> shown in <FIG> and <FIG> is merely an example, and the configuration of the pixel PX of the display device <NUM> is not limited to the configuration shown in <FIG> and <FIG>. The signal lines <NUM>, <NUM>, and <NUM> and the organic light emitting diode <NUM> may be formed in any suitable configuration. For example, in <FIG>, a display device <NUM> including two thin film transistors Qs and Qd and one storage capacitor Cst in one pixel PX is shown with respect to the display device <NUM>, but exemplary embodiments are not limited thereto. Therefore, the display device <NUM> is not limited in the number of thin film transistors, capacitors, and/or wires.

Characteristics of a display device according to some exemplary embodiments will now be described with reference to <FIG>. <FIG> shows a schematic view of part of a conventional display device. <FIG> shows a graph of a result of an experimental example. <FIG> shows a schematic view of part of a display device according to some exemplary embodiments. <FIG> shows a schematic view of part of a display device according to some exemplary embodiments.

Referring to <FIG>, the thickness of the encapsulation layer <NUM> disposed on a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6 may be different according to the position of the pixels PX1, PX2, PX3, PX4, PX5, and PX6, and when a touch electrode <NUM> is formed on the encapsulation layer <NUM> having different thicknesses depending on the position, the gap between a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6 and the touch electrode <NUM> may be different according to the position. For instance, there may be a first distance D1, a second distance D2, a third distance D3, and a fourth distance D4 that are different from each other according to the position. By this, the parasitic capacitance generated between the pixels PX1, PX2, PX3, PX4, PX5, and PX6 and the touch electrode <NUM> may be different according to the position, and particularly, the parasitic capacitance may be relatively large on the position where a relatively small third distance D3 and fourth distance D4 are disposed. Therefore, this may influence the touch sensitivity of the touch electrode <NUM>.

A change in sensitivity of a touch electrode <NUM> according to an experimental example will now be described with reference to <FIG>. In the present experimental example, sensitivity of the touch electrode <NUM> is measured for a first case (case A) in which the insulating layer between the common electrode <NUM> and the touch electrode <NUM> is formed to be about <NUM> thick, and a second case (case B) in which the insulating layer is formed to be about <NUM> thick. Other conditions except for the thickness of the insulating layer between the common electrode <NUM> and the touch electrode <NUM> are the same. As shown in <FIG>, the touch sensitivity of the first case (case A) in which the thickness of the insulating layer between the common electrode <NUM> and the touch electrode <NUM> is relatively small is found to be less than the touch sensitivity of the second case (case B) in which the thickness of the insulating layer between the common electrode <NUM> and the touch electrode <NUM> is relatively large. As described, it is found that the touch sensitivity of the touch electrode <NUM> is variable by the thickness of the insulating layer between the common electrode <NUM> and the touch electrode <NUM>.

Referring to <FIG>, the display device according to some exemplary embodiments includes an encapsulation layer <NUM> disposed on a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6, and the thickness of the encapsulation layer <NUM> is different according to the position. However, the cover layer <NUM> is disposed on the encapsulation layer <NUM> that is relatively less thick, and the cover layer <NUM> compensates for the step of the encapsulation layer <NUM> caused by the fact that the thickness of the encapsulation layer <NUM> is different according to the position, so the surfaces of the encapsulation layer <NUM> and the cover layer <NUM> are flat. In this manner, the gap between a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6 and the touch electrode <NUM> is constant to be the first distance D1. Therefore, the parasitic capacitance generated between the pixels PX1, PX2, PX3, PX4, PX5, and PX6 and the touch electrode <NUM> is constant, and the change in touch sensitivity generated by the difference of parasitic capacitance may be reduced.

Referring to <FIG>, part of the light emitted by a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6 may be input (or incident) to the touch electrode <NUM> along a first line L1, may be reflected to a second line L2 going toward the edge of the display area DA, and may be reflected to a third line L3. As described, the light going toward the edge of the display area DA may be seen as light leakage on the edge of the display area DA, but the cover layer <NUM> of the display device <NUM> according to the present invention includes a light blocking material, so the light reflected to the third line L3 is blocked by the cover layer <NUM> and is not seen. The cover layer <NUM> of the display device <NUM> does prevent the light leakage on the edge of the display area DA.

A display device according to some exemplary embodiments will now be described with reference to <FIG> shows a cross-sectional view of part of a display device according to some exemplary embodiments.

Referring to <FIG>, the display device is similar to the display device <NUM> in <FIG>. As such, no detailed description of the same constituent elements will be provided.

Referring to <FIG>, regarding the display device differing from the display device <NUM> shown in <FIG>, the cover layer 840_1 as well as the organic encapsulation layer 830_1 is disposed between the first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer 820_1 of the encapsulation layer 80_1. That is, the second inorganic encapsulation layer 820_1 of the encapsulation layer 80_1 is disposed on the cover layer 840_1 in addition to the organic encapsulation layer 830_1. Similar to as described above, the second inorganic encapsulation layer 820_1 is disposed on the cover layer 840_1 in addition to the organic encapsulation layer 830_1, thereby preventing impurity (e.g., moisture, etc.) permeation from the outside.

As with the display device <NUM> shown in <FIG>, the thickness of the organic encapsulation layer 830_1 of the display device shown in <FIG> disposed on the edge of the display area DA is reduced, and the cover layer 840_1 is disposed on the edge portion of the organic encapsulation layer 830_1 with a low thickness. The cover layer 840_1 is disposed on the edge of the display area DA with the organic encapsulation layer 830_1 and the non-display area NDA, the cover layer 840_1 includes a portion for covering the edge portion of the organic encapsulation layer 830_1 of which a height of an upper side is gradually reduced. In this manner, the cover layer 840_1 compensates for the step of the organic encapsulation layer 830_1 of which the thickness is relatively reduced by the cover layer 840_1, and the upper surfaces of the encapsulation layer 80_1 and the cover layer 840_1 become almost flat. Further, the touch electrode <NUM> is disposed on the encapsulation layer 80_1 with a flat surface and the cover layer 840_1, so the gap between the common electrode <NUM> of the organic light emitting diode <NUM> and the first touch electrode <NUM> and the second touch electrode <NUM> of the touch unit may be constant or substantially constant. By this, a difference in parasitic capacitance between the common electrode <NUM> and the first touch electrode <NUM> and the second touch electrode <NUM> of the touch unit is not generated, thereby preventing the change in touch sensitivity.

Further, as the cover layer 840_1 includes a light blocking material, it blocks the light leaking around the edge of the display area DA to thus prevent light leakage occurring around the edge of the display area DA. Other characteristics of the above-described display device <NUM> are applicable to the display device of <FIG>.

Referring to <FIG>, the display device is similar to the display devices shown in <FIG> and <FIG>. As such, no detailed descriptions of the same constituent elements will be provided.

Referring to <FIG>, the display device is different from the display device <NUM> shown in <FIG> in that a first cover layer 850a and a second cover layer 850b are at least disposed on the organic encapsulation layer <NUM>. The first cover layer 850a is disposed in the non-display area NDA, and overlaps the touch wires w10 and w20. Further, the second cover layer 850b is disposed in the display area DA, and overlaps the touch electrode <NUM>.

The first cover layer 850a and the second cover layer 850b include an organic material, and the surfaces of the first cover layer 850a and the second cover layer 850b are flat. The first cover layer 850a disposed in the non-display area NDA includes a light blocking material and is opaque, and the second cover layer 850b disposed in the display area DA may be transparent or be at least translucent.

As previously described, the thickness of the organic encapsulation layer <NUM> disposed on the edge of the display area DA is reduced to thus generate a step depending on the position. The first cover layer 850a and the second cover layer 850b that respectively have a flat surface are disposed on the encapsulation layer <NUM>, and the touch electrode <NUM> is disposed on the first cover layer 850a and the second cover layer 850b, so the gap between the common electrode <NUM> of the organic light emitting diode <NUM> and the first touch electrode <NUM> and the second touch electrode <NUM> of the touch unit may be constant or substantially constant. By this, a difference in parasitic capacitance between the common electrode <NUM> and the first touch electrode <NUM> and the second touch electrode <NUM> of the touch unit is not generated, thereby preventing the change in touch sensitivity. The first cover layer 850a and the second cover layer 850b are thicker than the step of the encapsulation layer <NUM>, thereby compensating the step of the encapsulation layer <NUM>.

Further, the first cover layer 850a disposed in the non-display area NDA includes a light blocking material, so it blocks the light leaking toward the edge of the display area DA to thus prevent light leakage that may be generated on the edge of the display area DA. The second cover layer 850b disposed in the display area DA is formed of a transparent material to thereby prevent the reduction of luminance of the display area DA. Other characteristics of the above-described display devices of <FIG> and <FIG> are applicable to the display device of <FIG>.

Characteristics of the display device of <FIG> will now be described with reference to <FIG> shows a schematic view of part of a display device according to some exemplary embodiments.

Referring to <FIG>, the display device includes an encapsulation layer <NUM> disposed on a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6, and the thickness of the encapsulation layer <NUM> is reduced from the edge of the display area DA and it becomes further reduced in the non-display area NDA. Therefore, the encapsulation layer <NUM> generates a step on the edge of the display area DA. However, the first cover layer 850a and the second cover layer 850b that respective have a flat surface are disposed on the encapsulation layer <NUM>, and the touch electrode <NUM> is disposed on the first cover layer 850a and the second cover layer 850b, so the gap between a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6 and the touch electrode <NUM> is the first distance D1, which is constant. Therefore, the parasitic capacitance generated between the pixels PX1, PX2, PX3, PX4, PX5, and PX6 and the touch electrode <NUM> is constant, and the change in touch sensitivity generated by the difference of parasitic capacitance may be reduced.

Further, part of the light emitted by the plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6 is input (or incident) to the touch electrode <NUM> along the fourth line L4, is reflected to the fifth line L5 disposed toward the edge of the display area DA, and may be reflected to the sixth line L6. As described, light disposed toward the edge of the display area DA may be seen as light leakage on the edge of the display area DA, but the first cover layer 850a disposed in the non-display area NDA of the display device of <FIG> includes a light blocking material, so the light reflected to the sixth line L6 is blocked by the first cover layer 850a and is not seen at the outside. The first cover layer 850a of the display device may prevent the light leakage on the edge of the display area DA.

A method of manufacturing display device <NUM> will now be described with reference to <FIG>, <FIG>, and <FIG>. <FIG> and <FIG> show cross-sectional views of a display device at various stages of manufacture according to some not-claimed embodiments.

Referring to <FIG>, a buffer layer <NUM>, a first semiconductor layer <NUM>, a second semiconductor layer <NUM>, a gate insulating layer <NUM>, a first gate electrode <NUM>, a second gate electrode <NUM>, and a first interlayer insulating layer <NUM> are formed on the substrate <NUM>, a first source contact hole <NUM> and a first drain contact hole <NUM> overlapping the first source region <NUM> and the first drain region <NUM>, and a second source contact hole <NUM> and a second drain contact hole <NUM> overlapping the second source region <NUM> and the second drain region <NUM> are formed in the first interlayer insulating layer <NUM> and the gate insulating layer <NUM>. A first source electrode <NUM>, a first drain electrode <NUM>, a second source electrode <NUM>, a second drain electrode <NUM>, a common voltage transmitting line w30, a second interlayer insulating layer <NUM>, a pixel electrode <NUM>, a partition wall <NUM>, an organic emission layer <NUM>, a common electrode <NUM>, first and second spacers SP1 and SP2, and an encapsulation layer <NUM> are formed. The thickness of the organic encapsulation layer <NUM> is gradually reduced as it extends towards the non-display area NDA from the edge of the display area DA, and hence, the height of the encapsulation layer <NUM> is gradually reduced toward the non-display area NDA from the edge of the display area DA.

As shown in <FIG>, a cover layer <NUM> is formed by stacking an organic material layer including a light blocking material and performing a photolithography process. The cover layer <NUM> may be formed by a screen printing method. The cover layer <NUM> is disposed on the edge of the display area DA with a thin organic encapsulation layer <NUM> and in the non-display area NDA. The cover layer <NUM> compensates the step of the organic encapsulation layer <NUM> according to the position so the upper surfaces of the encapsulation layer <NUM> and the cover layer <NUM> become almost flat.

As shown in <FIG>, a touch unit including a touch electrode <NUM> and touch wires w10 and w20 is formed on the encapsulation layer <NUM> and the cover layer <NUM>. Although not shown, an additional layer, such as a window may be formed on the touch unit.

As described, according to the method of manufacturing display device <NUM>, the touch electrode <NUM> is formed on the encapsulation layer <NUM> and the cover layer <NUM> that have a flat surface, and the gap between the common electrode <NUM> of the organic light emitting diode <NUM> and the touch electrode <NUM> is constant such that the change in touch sensitivity of the touch electrode <NUM> may be prevented. The cover layer <NUM> is formed to include a light blocking material, thereby preventing light leaking toward the edge of the display area DA and preventing light leakage that may be generated around the edge of the display area DA.

A method for manufacturing the display device of <FIG> will now be described with reference to <FIG> and <FIG>. <FIG>, <FIG>, and <FIG> show cross-sectional views of a display device at various stages of manufacture according to some exemplary embodiments.

Referring to <FIG>, a buffer layer <NUM>, a first semiconductor layer <NUM>, a second semiconductor layer <NUM>, a gate insulating layer <NUM>, a first gate electrode <NUM>, a second gate electrode <NUM>, and a first interlayer insulating layer <NUM> are formed on the substrate <NUM>. A first source contact hole <NUM> and a first drain contact hole <NUM> overlapping the first source region <NUM> and the first drain region <NUM>, and a second source contact hole <NUM> and a second drain contact hole <NUM> overlapping the second source region <NUM> and the second drain region <NUM> are formed on the first interlayer insulating layer <NUM> and the gate insulating layer <NUM>. A first source electrode <NUM>, a first drain electrode <NUM>, a second source electrode <NUM>, a second drain electrode <NUM>, a common voltage transmitting line w30, a second interlayer insulating layer <NUM>, a pixel electrode <NUM>, a partition wall <NUM>, an organic emission layer <NUM>, a common electrode <NUM>, first and second spacers SP1 and SP2, and an encapsulation layer <NUM> are formed. The thickness of the organic encapsulation layer <NUM> is gradually reduced as it extends towards the non-display area NDA from the edge of the display area DA, and hence, the height of the encapsulation layer <NUM> becomes gradually reduced as it extends towards the non-display area NDA from the edge of the display area DA.

Referring to <FIG>, a first cover layer 850a made of an organic material layer including a light blocking material is formed on the encapsulation layer <NUM> disposed in the non-display area NDA. The first cover layer 850a is formed by stacking an organic material layer including a light blocking material and performing a photolithography process. The first cover layer 850a may be formed by the screen printing method. The first cover layer 850a is disposed in the non-display area NDA, and is formed to, for instance, wrap the display area DA.

As shown in <FIG>, the first cover layer 850a is disposed as a partition wall on the encapsulation layer <NUM> of the display area DA surrounded by the first cover layer 850a disposed in the non-display area NDA, and a transparent organic material is stacked by inkjet printing, thereby forming a second cover layer 850b in the display area DA. The surface of the first cover layer 850a disposed in the non-display area NDA and the surface of the second cover layer 850b disposed in the display area DA are flat.

As shown in <FIG>, a touch unit including a touch electrode <NUM> and touch wires w10 and w20 is formed on the first cover layer 850a and the second cover layer 850b that respectively have a flat surface. The touch electrode <NUM> overlaps the second cover layer 850b, and the touch wires w10 and w20 overlap the first cover layer 850a. Although not shown, an additional layer, such as a window may be formed on the touch unit.

Claim 1:
A display device (<NUM>) comprising:
a substrate (<NUM>) comprising:
a display area (DA) comprising light emitting pixels (PX); and
a non-display area (NDA) disposed outside the display area (DA);
a thin film encapsulation layer (<NUM>) disposed on the substrate (<NUM>) over the light emitting pixels (PX);
wherein a
cover layer (<NUM>) overlaps an edge of the thin film encapsulation layer (<NUM>) such that the cover layer is disposed on an edge of the display area (DA) and in the non-display area (NDA), wherein:
the thin film encapsulation layer (<NUM>) is thinner at the edge thereof than at a center thereof;
the cover layer (<NUM>) overlaps the thin film encapsulation layer (<NUM>) at the thinner edge,
the height of the upper surface of the thin film encapsulation layer (<NUM>) and the height of the upper surface of the cover layer (<NUM>) with respect to the surface of the substrate (<NUM>) are substantially equivalent, such that the upper surfaces form a substantially flat surface,
a touch unit (<NUM>, W10) is disposed on the thin film encapsulation layer (<NUM>),the touch unit (<NUM>, W10) is also disposed on the cover layer (<NUM>),
characterized in that
the cover layer (<NUM>) comprises a light blocking material.