Patent Description:
The BLE technology is widely deployed in Internet-of-Things (IoT) applications due to its low energy consumption. Generally, a phase locked loop (PLL) which can support frequency modulation needs to be implemented in BLE systems. In order to reduce the die area of a BLE transceiver, small area oscillators are implemented along with injection-locking techniques in order to suppress the phase noise performance of the oscillators. Moreover, the system often requires the clock generator to support fractional-N mode. This makes the possibility for the system to tune the frequency offset of the crystal oscillator and enables the clock generator to generate small frequency step without using very small oscillator frequency.

For example, the document <CIT> shows a DTC-based PLL operable at fractional-N mode with an improved PLL output spectral purity. However, during the fractional-N, the delay of the DTC changes periodically and the period depends on the fractional part of the frequency control word (FCW). Thus, the non-linearity of the DTC introduces periodic error and this error leads to fractional spur at the output spectrum. In addition the frequency offset of the oscillator and the timing error between the injection path and the PLL path generate periodic error lead to reference spur at the output spectrum.

Publication <CIT> shows a circuit according to the preamble of claim <NUM>, and a method according to the preamble of claim <NUM>.

Accordingly, an object of the invention is to provide a circuit, a digital phase locked loop and a method that can overcome the aforementioned limitations.

The object is solved by the features of the claim <NUM> for the circuit, by the features of the claim <NUM> for the digital phase locked loop and by the features of the claim <NUM> for the method. The dependent claims contain further developments.

According to a first aspect of the invention, a circuit for facilitating random edge injection locking of an oscillator is provided. The circuit comprises a clock signal and a digitally controlled delay line, where said digitally controlled delay line is configured to delay the clock signal, thereby generating a delayed clock signal. The circuit further comprises an edge selector configured to generate a phase select signal with a random pulse sequence.

Moreover, the circuit preferably comprises a pulse generator downstream to the digitally controlled delay line configured to generate injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal. Therefore, the injection pulses are no longer injected to a fixed phase of the oscillator. Rather, the pulses are injected to different phases of the oscillator in order to break the repeating patterns that cause the spurs.

Preferably, the pulse generator is further configured to generate a first set of injection pulses for one phase of the at least two phases of the oscillator when the phase select signal is high and a second set of injection pulses for other phase of the at least two phases of the oscillator when the phase select signal is low.

For instance, the oscillator may generate RF signals at <NUM> degrees phase separation, i.e. at phases <NUM>, <NUM>, <NUM> and <NUM>. In this regard, the pulse generator may generate a first set of pulses for the RF signals at phase <NUM> and a second set of pulses for the RF signals at phase <NUM>, for example. Using the signal level of the phase select signal as a control input, the respective sets of pulses are injected to the respective phases of the oscillator. This advantageously facilitates the injection of the injection pulses at different phases of the oscillator in a simplified and an effective manner.

Preferably, the circuit further comprises control means configured to tune a delay of the digitally controlled delay line based on a duty cycle of the clock signal in order to compensate at least one half of oscillator period when injecting the injection pulses from one phase to the other phase of the at least two phases of the oscillator. This advantageously prevents the injection of pulses at an opposite or unwanted phase of the oscillator.

Further preferably, the edge selector comprises a pseudo-random binary sequence generator and the phase select signal preferably comprises a pseudo-random binary sequence. Therefore, random selection of phases of the oscillator to be injected is incorporated.

Preferably, the oscillator is an inverter-based oscillator, preferably an inverter-based ring oscillator, more preferably a quadrature four-stage ring oscillator operable with a minimum phase separation equal to pi/<NUM>. Advantageously, the proposed random edge injection locking technique can be implemented in a cost-effective manner due to the smaller area of the oscillator.

Further preferably, the oscillator is a multi-phase oscillator and wherein the pulse generator is configured to generate injection pulses for phases of the multi-phase oscillator based on the phase select signal. In this regard, the circuit further comprises switching means downstream to the pulse generator in order to inject the injection pulses at the phases of the multi-phase oscillator, and wherein the switching means is configured to be operable via a random switching logic. Advantageously, the proposed solution can be implemented with oscillators operable with a minimum phase separation of pi/N, where N is an even integer.

According to a second aspect of the invention, a digital phase locked loop (DPLL) is provided. The DPLL comprises a reference clock signal, and a digital to time converter. Said digital to time converter is configured to delay the reference clock signal, thereby generating a delayed reference clock signal. The DPLL further comprises an oscillator configured to generate radio frequency signals at at least two phases. Furthermore, the DPLL comprises a time to digital converter configured to generate an error signal by comparing an edge of the delayed reference clock signal and an edge of the radio frequency signals.

Moreover, the DPLL comprises a circuit configured to input the delayed reference clock signal and further to perform random edge injection locking of the oscillator according to the first aspect of the invention. Preferably, the DPLL further comprises a feedback path from the time to digital converter to a loop filter, and wherein the loop filter is configured to tune the oscillator based on the error signal generated by the time to digital converter.

Therefore, the digital to time converter delays the reference signal where the delayed reference signal phase is compared to the phase of the RF signals of the oscillator in order to phase-lock the oscillator output. On the other hand, the circuit, especially the digitally controlled delay line, takes the delayed reference clock signal as clock signal input and further delays the delayed reference clock signal. The latter is preferably used by the pulse generator along with the phase select signal in order to generate and further to inject pulses at different phases of the oscillator, thereby resetting the noisy phase in the oscillator.

Further preferably, the DPLL further comprises injection control means configured to control the generation of injection pulses at the pulse generator. In this regard, the injection control means is further configured to enable or disable the generation of injection pulses at the pulse generator for a predefined number of cycles of the reference clock signal. This advantageously keeps the balance between the reference spur and the effectiveness of the proposed random edge injection locking scheme, especially by disabling the injection in different numbers of reference cycles.

Preferably, the digital phase locked loop is an injection-locked fractional-N digital phase locked loop, preferably, an injection-locked ring-oscillator based fractional-N digital phase locked loop. Advantageously, the proposed DPLL supports BLE technology, especially the Gaussian-FSK modulation, and further provides a cost-effective solution due to the smaller size oscillator.

According to a third aspect of the invention, a method for facilitating random edge injection locking of an oscillator is provided. The method comprises the steps of providing a clock signal, generating a delayed clock signal, generating a phase select signal with a random pulse sequence, and generating injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal. Therefore, the injection pulses are injected to different phases of the oscillator in order to break the repeating patterns, thereby suppressing the level of reference spur and fractional spur effectively.

Preferably, the method further comprises the step of generating a first set of injection pulses for one phase of the at least two phases of the oscillator when the phase select signal is high. In addition, the method further comprises the step of generating a second set of injection pulses for another phase of the at least two phases of the oscillator when the phase select signal is low. This advantageously facilitates the injection of the injection pulses at different phases of the oscillator in a simplified and an effective manner.

Preferably, the method further comprises the step of compensating at least one half of an oscillator period when injecting the injection pulses from one phase to the other phase of the at least two phases of the oscillator. This advantageously prevents the injection of pulses at an opposite or unwanted phase of the oscillator.

Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. However, the following embodiments of the present invention may be variously modified and the range of the present invention is not limited by the following embodiments.

In <FIG>, a first exemplary embodiment of the circuit <NUM> according to the first aspect of the invention is illustrated. The circuit <NUM> comprises a clock signal <NUM> that is fed to a digitally controlled delay line or DCDL <NUM>, where the DCDL <NUM> generates a delayed clocked signal <NUM> by delaying the clock signal <NUM>. The circuit <NUM> further comprises an edge selector <NUM> that generates a phase select signal <NUM> with a random pulse sequence. Preferably, the edge selector <NUM> comprises a pseudo-random binary sequence generator that generates a pseudo-random binary sequence, i.e. PRBS-k as the phase select signal <NUM>, where k defines the size of a unique word of data in the sequence. However, other random sequences, e.g., true random sequences, chaotic sequences and the like, as known in the art can also be implemented in order to generate the phase select signal <NUM>.

The circuit <NUM> further comprises a pulse generator <NUM> downstream to the DCDL <NUM> and an oscillator <NUM> downstream to the pulse generator <NUM>. Said oscillator <NUM> is configured to generate radio frequency (RF) signals <NUM>,<NUM> at at least two phases, preferably more. In this regard, the pulse generator <NUM> generates injection pulses <NUM>,<NUM> from the delayed clock signal <NUM> for the two phases of the oscillator <NUM> based on the phase select signal <NUM>. The generation of said phase select signal <NUM> and the injection arrangement for the oscillator <NUM> will be discussed in the later sections in detail.

Therefore, the circuit <NUM> effectively solves the two main limitations specially associated with a fractional-N injection-locked oscillator, namely the high reference spur and the high fractional spur at the output spectrum. The circuit <NUM> effectively breaks the repeating patterns of pulse injection, especially by injecting pulses at different phases of the oscillator <NUM>.

For instance, if the above-mentioned injection locking is to be performed for a PLL with fractional-N mode having an injection-locked oscillator, the clock signal may correspond to the reference clock signal and the DCDL <NUM> can be extended to have a first DCDL and a second DCDL. The first DCDL (i.e. a digital to time converter) may generate a first delayed reference clock signal by delaying the reference clock signal and the second DCDL may generate a second delayed reference clock signal by delaying the first reference clock signal. Then, the pulse generator <NUM> may generate the injection pulses <NUM>,<NUM> from the second delayed reference clock signal for the two phases of the oscillator <NUM> based on the phase select signal <NUM>. Therefore, the oscillator <NUM> will be locked with respect to the first delayed reference clock signal whereas the second delayed reference clock signal is used to generate the injection pulses <NUM>,<NUM>.

It is important that when the pulses are sent from one phase to another phase of the oscillator <NUM>, one-half of the oscillator period needs to be compensated by the DCDL <NUM>. Otherwise, a large error will introduce which, in itself, may cause large spurious at the output spectrum. In order to do so, the circuit <NUM> comprises control means <NUM> that is configured to tune the delay of the DCDL <NUM> based on the duty cycle of the clock signal <NUM> or the reference clock signal coming from, for instance, a crystal oscillator. In this regard, the control means <NUM> is configured to tune the DCDL <NUM> according to the digital RF duty-cycle of the oscillator <NUM> and further to perform static timing offset calibration of the DCDL <NUM> by taking into account the random pulse sequence from the edge selector <NUM>, for instance.

In <FIG>, an exemplary embodiment of the pulse generator <NUM> according to the first aspect of the invention is illustrated. Here, the implementation of said pulse generator <NUM> is illustrated with digital logic gates, namely NOT gates or inverters and AND gates. However, it is to be noted that any alternative logic gate arrangements are feasible so long the output results in short pulses from a continuous signal. During the operation, the delayed clock signal <NUM> is inputted at a first inverter <NUM> that inverts the polarity of the delayed clock signal <NUM>. The output of the first inverter <NUM> acts as a common node, which serves two propagation paths <NUM>,<NUM>. The output of the first inverter <NUM> passes through a second inverter <NUM> along the propagation path <NUM>, reverting the polarity again that results in the delayed clock signal <NUM>, along with the propagation delay caused by the first and second inverter <NUM>,<NUM>, respectively.

Along the propagation path <NUM>, the output of the first inverter <NUM> is inverted twice, by a third inverter <NUM> and a fourth inverter <NUM>, respectively. This results in the delayed clock signal <NUM> with an opposite polarity along with propagation delay caused by the first inverter <NUM>, the third inverter <NUM> and the fourth inverter <NUM>. The signals at the propagation paths <NUM>,<NUM> are fed to a first AND gate <NUM>. Due to the inversion stages, the signal at the propagation path <NUM> has an opposite polarity than the signal at the propagation path <NUM>, however with the additional delay caused by the fourth inverter <NUM>, the signals will have same polarity for a brief moment, especially defined by the delay time cause by each delay stage of the inverters <NUM>,<NUM>,<NUM>,<NUM>,<NUM>. For this brief moment, the AND gate output will be high and will produce a pulse or injection pulse <NUM> with a width corresponding to the delay time of each inverter delay stage.

The injection pulse <NUM> is then fed to a second AND gate <NUM> where the second input of said AND gate <NUM> is the phase select signal <NUM>. Therefore, the output <NUM> of the second AND gate <NUM> will be high when the phase select signal <NUM> is high. Additionally, the injection pulse <NUM> is fed to a third AND gate <NUM> where the second input of said AND gate <NUM> is also the phase select signal, however with an opposite polarity, i.e. inverted via an inverter in-between. Therefore, the output <NUM> of the third AND gate will be high when the phase select signal <NUM> is low. In order to facilitate complementary arrangements, e.g. CMOS implementation, the outputs <NUM>, <NUM> of the second AND gate <NUM> and the third AND gate <NUM>, respectively, are further inverted. In <FIG>, the outputs <NUM> of the second AND gate <NUM> are shown as INJ0P and INJ0N for P-type and N-type transistors, respectively, in CMOS configuration. Similarly, the outputs <NUM> of the third AND gate <NUM> are shown as INJ180P and INJ180N for P-type and N-type transistors, respectively, in CMOS configuration.

In <FIG>, an exemplary embodiment of the oscillator <NUM> according to the first aspect of the invention is illustrated. Particularly, <FIG> shows the injection scheme for injecting the injection pulses at different phases of the oscillator <NUM>. The oscillator <NUM> illustrated herein as a quadrature four-stage ring oscillator having a <NUM><NUM> of phase separation. The four stages correspond to four inverters, namely a first inverter <NUM>, a second inverter <NUM>, a third inverter <NUM> and a fourth inverter <NUM>. The first inverter <NUM> results a first stage output <NUM>, the second inverter <NUM> results a second stage output <NUM>, the third inverter <NUM> results a third stage output <NUM> and the fourth inverter <NUM> results a fourth stage output <NUM>.

The first stage output <NUM> and the third stage output <NUM> carry complementary waveforms and so do the second stage output <NUM> and the fourth stage output <NUM>. In addition, the latter two are <NUM><NUM> out of phase with respect to the former two. Hence, the oscillator <NUM> consists of four one-pole stages, thereby generating <NUM><NUM> phase separations between consecutive nodes when oscillates. However, the outputs <NUM>,<NUM>,<NUM>,<NUM> prefer to latch up and then the loop can indefinitely maintain the first stage output <NUM> and the third stage output <NUM> high, and the second stage output <NUM> and the fourth stage output <NUM> low, or vice versa.

In order to prevent said indefinite latch up, a first pair of cross-coupled inverters <NUM> is included between the first stage output <NUM> and the third stage output <NUM> and further a second pair of cross-coupled inverters <NUM> is included between the second stage output <NUM> and the fourth stage output <NUM>. The first pair of cross-coupled inverters <NUM> and the second pair of cross-coupled inverters <NUM> prevent equal logical states at their respective input and output nodes.

The injection pulses INJ0P, INJ0N and INJ180P, INJ180N, as shown in <FIG>, are injected in a complementary arrangement at the respective phases of the oscillator <NUM>. In particular, the injection pulse INJ0P is injected at the first stage output <NUM> whereas the injection pulse INJ0N is injected at the third stage output <NUM>, which carries complementary waveform to the first stage output <NUM>. Similarly, the injection pulse INJ180P is injected at the third stage output <NUM> whereas the injection pulse INJ180N is injected at the first stage output <NUM>, which carries complementary waveform to the second stage output <NUM>.

In other words, the RF signals from the first stage output <NUM> correspond to RF signals at phase <NUM> of the oscillator <NUM> and the RF signals from the third stage output <NUM> correspond to RF signals at phase <NUM> of the oscillator <NUM>. It is to be noted that said injection principle can be analogously implemented for the second stage output <NUM> and the fourth stage output <NUM>, thereby injection locking the oscillator <NUM> at phases <NUM> and <NUM>, respectively.

In <FIG>, an exemplary timing diagram of operations according to the first aspect of the invention is illustrated. The signal CLK represents the clock input signal <NUM> of the DCDL <NUM> and the signal ODCDL represents the delayed clock signal <NUM>. The signal SELED represents the phase select signal <NUM> with random sequences for the polarity of the signal. The signal INJ<NUM> and INJ<NUM> represent the injection pulses <NUM> and <NUM>, respectively, generated by the pulse generator <NUM>. It can be seen that, the injection pulses INJ<NUM> are generated when SELED is high and the injection pulses INJ<NUM> are generated when SELED is low.

The signal RF<NUM> represents the RF signals at the phase <NUM> of the oscillator <NUM> and the signal RF<NUM> represents the RF signals at the phase <NUM> of the oscillator <NUM>. It can be seen that, when SELED is high, the injection pulses INJ<NUM> are injected at the phase <NUM> of the oscillator <NUM> as a clean reference pulse to reset RF<NUM>. Further, when SELED is low, the injection pulses INJ<NUM> are injected at the phase <NUM> of the oscillator <NUM> as a clean reference pulse to reset RF<NUM>.

In <FIG>, a second exemplary embodiment of the circuit <NUM> according to the first aspect of the invention is illustrated. The circuit <NUM> differs from the circuit <NUM> of <FIG> in that the circuit <NUM> comprises a multi-phase oscillator <NUM> and additional switching means <NUM> in order to drive the injection pulses <NUM> to a respective phase of the oscillator <NUM>. The multi-phase oscillator <NUM> can be a multi-stage ring oscillator, a multi-stage LC oscillator, or any oscillators operable with a minimum phase separation of pi/N, where N is an integer greater than <NUM>, preferably an even integer.

The switching means <NUM> is configured to be operable via a random switching logic <NUM>, preferably generated by the edge selector <NUM>. In this regard, the edge selector may further tune the DCDL <NUM> based on the random switching logic <NUM>, for instance via normalization, in order to synchronize the injection pulses <NUM> with the respective phases of the multi-phase oscillator <NUM>.

In <FIG>, an exemplary embodiment of the digital phase locked loop (DPLL) <NUM> according to the second aspect of the invention is illustrated. Said DPLL <NUM> comprises a reference clock signal <NUM>, preferably generated from an on-board crystal oscillator (not shown), and a digital to time converter (DTC) <NUM>. The DTC <NUM> generates a delayed reference clock signal <NUM> by delaying the reference clock signal <NUM>. The DPLL <NUM> further comprises the circuit <NUM> according to the first aspect of the invention, downstream to the DTC <NUM> so that the circuit <NUM> is able to take the delayed reference clock signal <NUM> as its input clock signal. The DPLL <NUM> further comprises the oscillator <NUM> that generates RF signals at phases <NUM> and <NUM>, for example, as described along <FIG>.

As described along <FIG>, the circuit <NUM> generates injection pulses <NUM>,<NUM> from the delayed reference clock signal <NUM> for the two phases of the oscillator <NUM>. The oscillator <NUM> outputs RF signals at two phases <NUM>,<NUM> that are reset by the injection pulses <NUM>,<NUM> and are further fed to a multiplexer <NUM>. The multiplexer <NUM> is implemented as, for instance a 2x1 multiplexer, which takes the RF signals at inputs and outputs a selective RF signal <NUM> out of the two based on a control signal. Said control signal is preferably the phase select signal <NUM> provided by the edge selector <NUM>. Hence, when the phase select signal <NUM> is high, the multiplexer <NUM> will output the RF signal at phase <NUM> of the oscillator <NUM> and when the phase select signal <NUM> is low, the multiplexer <NUM> will output the RF signal at phase <NUM> of the oscillator.

The DPLL <NUM> further comprises a time to digital converter (TDC) <NUM> that compares an edge of the delayed reference clock signal <NUM> at the output of DTC <NUM> with an edge of the RF signals <NUM>,<NUM> at the output <NUM> of the multiplexer <NUM>. Therefore, the TDC <NUM> generates an error signal based on the difference between the edges, i.e. phase difference, of said signals. The error signal is fed to a loop filter <NUM> through a feedback path <NUM>, where the loop filter <NUM> tunes the oscillator <NUM> based on said error signal.

It is to be noted that, if the proposed injection locking technique, as performed by the circuit <NUM>, is not implemented in the DPLL <NUM>, the DPLL <NUM> would align the phases between the output <NUM> of the DTC <NUM> and the output <NUM> of the multiplexer <NUM> with a random pattern. In other words, the DTC output <NUM> sometimes may align with the oscillator phase RF<NUM> and sometimes may align with RF<NUM> in a random manner. Hence, the injection pulses may sometimes be sent to the opposite RF edge if the DTC output <NUM> is directly used to generate the injection pulses without any compensation for said random patterns. This may result in huge disturbances to the oscillator <NUM> and may cause large spurious.

The proposed random edge injection technique, as facilitated by the circuit <NUM>, allows the DPLL <NUM> to align the DTC output <NUM>, for instance with rising edges of RF<NUM> when the phase select signal <NUM> is high, and, for instance with rising edges of RF<NUM> when the phase select signal <NUM> is low. The proposed random edge injection technique further ensures the polarity of the injection signals as described along <FIG> and <FIG>, so that the injection pulses INJ0P and INJ0N are generated if the phase select signal <NUM> is high otherwise the injection pulses INJ180P and INJ180N are generated.

The DPLL <NUM> further comprises an accumulator <NUM> that comprises a control input <NUM> and a data input <NUM>. The control input <NUM> corresponds to frequency control input, e.g. a frequency control word (FCW) and the data input <NUM> corresponds to the transmission data, especially during modulation. The accumulator <NUM> generally comprises a counter or counters for counting, e.g. the edges of the oscillator <NUM> in one reference clock to coarsely tune the oscillator <NUM> to the target frequency. Preferably, the accumulator <NUM> is disabled during the fine-tuning of the oscillator <NUM>, i.e. the correction of the phase error between the RF edge <NUM> and the delayed reference edge <NUM>.

The DPLL <NUM> further comprises so-called estimators <NUM>, which estimate and further calibrate, for instance, the duty cycle of the reference clock signal <NUM> (crystal oscillator duty cycle), the duty cycle of the oscillator <NUM>, static timing offset for the DCDL, and so on. The DPLL <NUM> further comprises injection control means <NUM> that is configured to control the generation of the injection pulses <NUM>,<NUM> at the pulse generator <NUM>. In particular, the injection control means enables or disables the injection path for a selective number of cycles or periods of the reference clock signal <NUM>. The operation of said injection control means will be described in a later section in detail.

In <FIG>, the DPLL <NUM> of <FIG> is illustrated in detail. The reference clock signal <NUM> is generated from a crystal oscillator (not shown) at a clock frequency of <NUM> and the DTC <NUM> generates the delayed reference clock signal <NUM> at a clock frequency of <NUM> (i.e. double edge). The DCDL <NUM> takes in the delayed reference clock signal <NUM> and further delays the signal <NUM>. The DCDL output <NUM> is fed to the pulse generator <NUM> along with the phase select signal <NUM> coming from the edge selector <NUM>. The pulse generator <NUM> generates a set of injection pulses <NUM> for the phase <NUM> of the oscillator <NUM> and a set of injection pulses <NUM> for the phase <NUM> of the oscillator <NUM> from the DCDL output <NUM> and the phase select signal <NUM>.

The oscillator <NUM> therefore generates RF signals, which are already reset by the injection pulses, particularly the RF signal at the phase <NUM> of the oscillator <NUM> and the RF signal at the phase <NUM> of the oscillator <NUM>. The multiplexer <NUM> outputs the respective pulses <NUM>,<NUM> to the TDC <NUM> with respect to the phase select signal <NUM>. The TDC <NUM> generates phase error signals by comparing the edges of the DTC output <NUM> with the respective RF signals <NUM>,<NUM> and feeds to the loop filter <NUM> via the feedback path <NUM>.

The loop filter <NUM> generates oscillator tuning words correspond to the phase error in order to tune the oscillator phases. The phase error signals are further fed to the estimators <NUM>,<NUM>,<NUM>. Particularly, the estimator <NUM> estimates and/or calibrates the duty cycles of crystal oscillator and the oscillator <NUM> and further tunes the DTC edges. The estimator <NUM> estimates and/or calibrates the static timing offset of the DCDL and the duty cycle of the oscillator <NUM> in order to tune the DCDL <NUM>. Moreover, the estimator <NUM> estimates or calibrates the DPLL <NUM> for the modulation of the transmitting data, especially when the DPLL <NUM> operates in the transmitter mode.

Along <FIG>, the operation phases of the DPLL <NUM> are illustrated. In particular, <FIG> shows the operation phases of the DPLL <NUM> over the required lock time. During the initial phase, the DPLL <NUM> uses the accumulator <NUM>, especially the counter, to count the edges of the oscillator <NUM> in one reference clock to coarsely tune the oscillator <NUM> close to the target frequency. Then the counter is disabled to reduce power consumption and the fine tuning of the oscillator <NUM> stats correcting the phase error between the RF edge <NUM> and the delayed reference edge <NUM>, where the phase error is measured by the TDC <NUM>.

During the PLL only phase, the TDC output, i.e. the phase error, is used to compute or estimate the duty cycle error of the reference clock and the RF signal and further to estimate the gain of the DTC <NUM>. Next, the injection path is enabled and the phase-locking path is frozen to avoid racing conditions between the two loops. During the injection lock only phase, the TDC output, i.e. the phase error, is used for calibrating the duty cycle of the crystal oscillator and further to tune the delay of the DCDL <NUM> in order to reduce the static timing offset. Finally, the phase-locking path and the injection path are enabled while the aforementioned calibrations are running in the background in order to decrease the level of spurious tones.

<FIG> shows the timing diagram for the operations of the DPLL <NUM>. The signal REF represents the reference clock signal <NUM>. The signal ODTC represents the DTC output, i.e. the delayed reference clock signal <NUM>. The signal ODCDL represents the DCDL output, i.e. the further delayed reference clock signal <NUM>. The signal SELED represents the phase select signal <NUM> generated from the edge selector <NUM>. The signal INJ<NUM> represents the injection pulses <NUM> to be injected at the phase <NUM> of the oscillator <NUM> and the signal INJ<NUM> represents the injection pulses <NUM> to be injected at the phase <NUM> of the oscillator <NUM>. The signal RF<NUM> represents the RF signal <NUM> from the oscillator <NUM> at the phase <NUM> and the signal RF<NUM> represents the RF signal <NUM> from the oscillator <NUM> at the phase <NUM>.

It can be seen that, by the virtue of the proposed random edge injection technique, the DPLL <NUM> aligns ODTC with rising edges of the RF<NUM> when the SELED is high and with rising edges of the RF<NUM> when the SELED is low. The proposed random edge injection technique further ensures the polarity of the injection signals such that the injection pulses INJ<NUM> are generated when SELED is high and the injection pulses INJ<NUM> are generated when SELED is low. As such, the random pattern of the DTC output <NUM> is effectively compensated, thereby eliminating any erroneous alignment between the phases of the ODTC and the RF signals.

Along <FIG>, the operation of the injection control means <NUM> is illustrated. Particularly, <FIG> shows an exemplary embodiment of the injection control means <NUM> in a simplified block diagram, where the components of the DPLL <NUM> are simplified into three basic blocks in order not to repeat the DPLL <NUM> operation as described along <FIG> and <FIG>. Generally, the injection control means <NUM> comprises a number pool <NUM> that is configured to select a number N <NUM> from a pool of numbers with a geometric distribution for selection. It is conceivable that the pool of numbers may comprise any random distribution. It is further conceivable that the number pool <NUM> may select the number N <NUM> from the pool of numbers in a random manner.

The injection control means <NUM> further comprises a nonuniform selector <NUM> that is configured to generate an enable signal <NUM> with a pulse duration corresponds to the number of clock periods based on the selected number N <NUM>. The pulse generator <NUM> is then configured such that the pulse generator <NUM> will be enabled when the enable signal <NUM> is high and the pulse generator <NUM> will be disabled when the enable signal <NUM> is low.

<FIG> shows the timing diagram for the operations performed by the injection control means <NUM>. The signal REF represents the reference clock signal. The signal N represents the number selected from the number pool <NUM>. The signal ENINJ represents the enable signal. The signal PINJ represents the injection pulses in general. The signal PE represents the phase error from the TDC <NUM>.

It can be seen that, for example, if the output of the number pool <NUM> is updated to <NUM>, the pulse generator <NUM> is enabled for <NUM> cycles of the reference clock REF. The TDC <NUM> compares the phase difference between the reference and the RF signal, and the output is used for tuning as described above. After <NUM> reference cycles, the ENINJ goes low, therefore no injection pulse is sent to the oscillator <NUM>. At this moment, the TDC output represents the phase (frequency) error of the oscillator <NUM> and the oscillator frequency is tuned, which further reduces the reference spur level. After that, a new number N is selected, e.g. <NUM> as shown, in order to prevent quasi static states from occurring.

Along <FIG>, measurement results are illustrated for the output spectrum indicating the spur level reduction by means of the proposed random edge injection technique. In particular, <FIG> shows the fractional spur level for two output spectrums, where the first spectrum <NUM> represents the DPLL output without the proposed random edge injection technique and the second spectrum <NUM> represents the DPLL output with the proposed random edge injection technique. <FIG> shows the reference spur level at the DPLL output <NUM> where the proposed random edge injection technique is implemented.

<FIG> shows the fractional spur at <NUM> where the fractional part is <NUM>. It can be seen that the fractional spur is -34dBc at the DPLL output <NUM> if the random edge injection technique is not implemented. Whereas, the fractional spur is -44dBc at the DPLL output <NUM> where the proposed random edge injection technique is implemented. From <FIG>, it can be seen that the reference spur at the DPLL output is -51dBc.

In <FIG>, an exemplary embodiment of the method according to the third aspect of the invention is illustrated. In a first step S1, a clock signal is provided. In a second step S2, a delayed clock signal is generated from the clock signal. In a third step S3, a phase select signal is generated with a random pulse sequence. In a fourth step S4, injection pulses are generated from the delayed clock signal for at least two phases of the oscillator based on the phase select signal.

Particularly, a first set of injection pulses are generated for one phase of the at least two phases of the oscillator when the phase select signal is high and a second set of injection pulses are generated for other phase of the at least two phases of the oscillator when the phase select signal is low.

The embodiments of the present invention can be implemented by hardware, software, or any combination thereof. Various embodiments of the present invention may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or the like.

Claim 1:
A circuit (<NUM>) for facilitating random edge injection locking of an oscillator (<NUM>) comprising:
a digitally controlled delay line (<NUM>) configured to receive a clock signal (<NUM>) and further to delay the clock signal (<NUM>), thereby generating a delayed clock signal (<NUM>),
an edge selector (<NUM>) configured to generate a phase select signal (<NUM>) with a pulse sequence, and
a pulse generator (<NUM>) downstream to the digitally controlled delay line (<NUM>) configured to generate injection pulses (<NUM>,<NUM>) from the delayed clock signal (<NUM>) for at least two phases of the signals generated by the oscillator (<NUM>) based on the phase select signal (<NUM>),
characterised in that
said edge selector is configured to generate said phase select signal with a random pulse sequence.