Patent Description:
Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory device. For example, binary devices have two states, often denoted by a logic "<NUM>" or a logic "<NUM>. " In other systems, more than two states may be stored. To access the stored information, the electronic device may read, or sense, the stored information in the memory device. To store information, the electronic device may write, or program, the state in the memory device.

Various types of memory devices exist, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., flash memory, can store data for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. A binary memory device may, for example, include a charged or discharged capacitor.

Memory devices typically includes power supply lines throughout the device that provide power from a power supply to the various transistors and other components that are included in the memory. The power supply lines are typically arranged in different metal layers associated with the device. The resistivity of these power supply lines can dissipate power and generate heat as power is transmitted from the power supply. The farther power travels along the power supply lines, the greater this power dissipation and heat generation can be. Additionally, some metal layer have greater resistivity than others. In some cases, lower metal layer have higher resistivity than upper metal layers. Thus, power that is transmitted on power supply lines located in lower metal layers may be more susceptible to dissipation than power that is transmitted on power supply lines that located in upper metal layers.

In order to reduce these power dissipation and heating issues, some memory devices include a redistribution layer that includes low resistivity lines that provide power to certain locations within the device. This layer may be referred to as an "iRDL layer" and may be formed in a semiconductor process that occurs before an assembly process. An iRDL layer may be an uppermost layer of the device, which may be the lowest resistivity layer in the device. In some cases, an iRDL layer is a metal <NUM> layer(M4) over the metal <NUM> layer(M3).

In order for power to be transferred from the iRDL layer to lower layers of a memory device, the memory device may include one or more vias, also known as contact plugs. A memory device may include one or more "iRDL vias" that provide conductive pathways between power distribution lines in the iRDL layer ("iRDL lines") to wiring that is this located in an underlying metal layer. In one example, an iRDL via provides a conductive pathway between a metal <NUM> layer and a metal <NUM> layer. The memory device may also include additional vias that provide conductive pathways between other layers, such as M3-M2 vias.

Conventionally, a memory device includes a dedicated area for routing of iRDL vias. These dedicated areas are used to avoid interference with control signals or other wiring that may be present in areas that underlie the redistribution layer. These dedicated areas result in unwanted increases in chip size, power consumption and other disadvantages. Thus, there is a need in the art for improved iRDL via routing. A system with meshed power and signal buses on cell array is known from <CIT>. Therein, an electrical connection is made between a first VSS bus and a second VSS bus using a through-hole located above a memory cell circuit. <CIT> discloses multi-bank semiconductor memory devices having optimized memory block layouts and data line routing to enable chip size reduction and increase operating memory access speed.

In accordance with the present invention, there is provided a semiconductor device as defined by claim <NUM>.

Embodiments of the present disclosure avoid conventional arrangements that include a dedicated iRDL layout region. Instead of using a dedicated region, present embodiments route iRDL vias in device locations that lack certain metal layer wirings, but contain other device components such that the iRDL via routing area is not exclusively dedicated to iRDL vias. In some embodiments, an iRDL via is routed above a memory MAT that is located at an edge of a memory bank. As used herein, a "memory MAT" generally refers to a subunit of the memory bank having a plurality of memory cells. In other embodiments, iRDL vias may be routed above both an edge MAT and an adjacent column decoder. In other embodiments, iRDL vias may be routed above adjacent memory MATs.

<FIG> is a schematic illustration of a portion of a memory <NUM> according to an embodiment of the present disclosure. The memory <NUM> includes an array <NUM> of memory cells, which may be, for example, DRAM memory cells, SRAM memory cells, flash memory cells, or some other type of memory cells. The memory <NUM> may be generally configured to operate in cooperation with a larger digital system that includes at least a processor configured to communicate with the memory <NUM>. In the present description, "external" refers to signals and operations outside of the memory <NUM>, and "internal" refers to signals and operations within the memory <NUM>. As an illustrative example, the memory <NUM> may be coupled to a microprocessor that provides external commands and clock signals to the memory <NUM>. Although examples in the present description are directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.

The memory <NUM> may be generally configured to execute read and/or write commands received from an external device. Read commands provide data stored in the array <NUM> to the external device across a data bus <NUM>. Write commands receive data from the external device across the data bus <NUM> and store the data in the memory array <NUM>. The following discussion generally references read commands by way of example and not limitation. In processing a read command, the memory <NUM> receives an input clock signal CLK and generates an internal clock that synchronizes internal signals so as to provide output data on the data bus <NUM> with appropriate timing. Here, the memory device <NUM> uses a delay-locked loop <NUM> to synchronize internal signals including generating a data strobe signal <NUM>. The data strobe signal <NUM> is provided as output to the external controller and is asserted at a time when the requested read data is available on the data bus <NUM> for capture by the external controller.

The memory system <NUM> includes a command decoder <NUM> that receives memory commands through a command bus <NUM>. The command decoder <NUM> responds to memory commands applied to the command bus <NUM> by generating corresponding control signal to perform various operations on the memory array <NUM>. For example, the command decoder <NUM> may generate internal control signals to read data from and/or write data to the memory array <NUM>. Row and column address signals associated with a particular command are applied to the memory <NUM> through an address bus <NUM>. The address bus <NUM> provides the row and column address signals to an address register <NUM>. The address register <NUM> then outputs a separate column address and a separate row address to the memory array <NUM>.

As can be seen in <FIG>, row and column addresses may be provided by the address register <NUM> to a row address decoder <NUM> and a column address decoder <NUM>, respectively. The column address decoder <NUM> selects bit lines extending through the array <NUM> corresponding to respective column addresses. The row address decoder <NUM> includes or is coupled to a word line driver or similar component that activates respective rows of memory cells in the array <NUM> corresponding to received row addresses. The selected data line (e.g., a bit line or bit lines) corresponding to a received column address are coupled to a read/write circuitry <NUM> to provide read data to a data output buffer or similar component via an input-output data bus <NUM>. Write data is applied to the memory array <NUM> through a data input buffer or similar component and the memory array read/write circuitry <NUM>.

The timing of signals external to the memory <NUM> may be determined by the external clock signal CLK. Operations within the memory <NUM> are typically synchronized to external operations. The delay-locked loop <NUM> is generally configured to receive the external clock signal CLK and generate a synchronized internal clock signal. The synchronized internal clock signal generated by the delay-locked look <NUM> may be provided to various internal memory components in order to facilitate the latching of command, address, and data signals in accordance with the external clock CLK. For example, data output may be placed on the data bus <NUM> of the memory <NUM> in synchronism with the external clock signal CLK so that the memory device <NUM> outputs data in a manner that allows the data to be captured by the external controller. To output data with proper timing, the delay-locked loop <NUM> develops an internal clock signal in response to the external clock signal and applies the internal clock signal to latches contained in the memory device <NUM> to clock data. The internal clock signal and external clock CLK are synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands.

<FIG> is a schematic diagram that illustrates an example layout for a semiconductor memory device <NUM> in accordance with the present disclosure. The semiconductor device <NUM> of <FIG> may correspond to the memory device of <FIG>. Certain components that are illustrated in <FIG> are omitted from <FIG> in order to simply the drawing. <FIG> includes a memory area <NUM> and a peripheral circuit area <NUM>. The memory area <NUM> may include a plurality of memory banks, which may correspond to the memory banks <NUM> illustrated in <FIG>. The memory area <NUM> of <FIG> includes eight memory banks B0-B7, by way of example and not limitation. Among the memory banks B0 to B7 associated with the memory area <NUM>, the even memory banks (B0, B2, B4, B6), which are half of the memory banks, are arranged in this order along an X-direction in a left half of the semiconductor chip in a Y-direction. The odd memory banks (B1, B3, B5, B7), which are the remaining half of the memory banks are arranged in this order along the X-direction in a right half of the semiconductor chip in the Y-direction.

The memory area <NUM> may be operatively coupled to various circuit components that are provided within the peripheral circuit area <NUM>. The peripheral circuit area <NUM> may be positioned to one side of the memory area <NUM> in the Y-direction. The peripheral circuit area <NUM> may be a first pad area that is arranged along an edge of a semiconductor chip. Although not specifically shown in <FIG>, memory array <NUM> may also be associated with a second peripheral circuit area that includes another pad area arranged along another edge of the semiconductor chip. The second peripheral circuit area may be arranged on an opposite side from the first peripheral circuit area <NUM>. It should be appreciated that semiconductor devices having pad areas located at chip edges are shown and described herein by way of example and not limitation. Implementations consistent with the present disclosure may use alternative configurations. For example, in some implementations, a pad area may be provided at or near a center or midline of a semiconductor chip.

The peripheral circuit area <NUM> may include one or more power generator blocks <NUM>, one or more DQ pad blocks <NUM>, one or more column address blocks <NUM>, and/or other components that are not specifically shown in <FIG>. The DQ pad blocks <NUM> may include an input receiver that receives an address input via an address pin and an address latch circuit that latches the address. The DQ pad blocks <NUM> may also include an output buffer that outputs read data to a data I/O pin and/or an input receiver that receives write data supplied via the data I/O pin. The column address block <NUM> may include a column address decoder that selects bit lines extending through the memory area <NUM> corresponding to respective column addresses. A column address decoder of the column address block <NUM> may correspond to the column address decoder <NUM> of <FIG>. The power generator block <NUM> may include a power source that supplies power to various circuit and components associated with the memory <NUM>. The power generator block <NUM> may be provided in association with one or more transmission lines or other power distribution lines that supply power from the power distribution block <NUM> to the various components.

Each of the memory banks B0-B7 provided in the memory area <NUM> includes a plurality of memory cells organized into a plurality of memory MATs. A "memory MAT" generally refers to a subunit of the memory bank. The memory area <NUM> additionally includes one or more supporting components such as a row decoder (XDEC) <NUM> provided adjacently to one side of each of the memory banks B0 to B7 in the X-direction. Column decoders (YDEC) <NUM> and main amplifiers (DSA) <NUM> may be provided adjacently to a side of the memory area <NUM> in the Y-direction.

The row decoder <NUM> is a circuit that drives a plurality of word lines to select particular memory cells within the memory area <NUM> based on a row address. The row decoder <NUM> may be configured to drive one or more main word lines (MWL) <NUM>, to which row decoders <NUM> may be directly coupled. For purposes of illustration, one main word line <NUM> is shown in <FIG>. Although not shown in <FIG>, the various main word lines <NUM> may be coupled to sub-word lines (SWL) that are arranged within the various memory MATs associated with the memory banks B0-B7. As described in greater detail below, this coupling may occur through various components that connect the main word lines <NUM> to the sub-word lines arranged within the various memory MATs.

The column decoder <NUM> is a circuit that selects a plurality of sense amplifiers contained in the memory cell area <NUM> on the basis of the column address. The column decoders <NUM> are coupled to the column address decoder <NUM>, which may correspond to the column address decoder of <NUM> of <FIG>. The column decoders <NUM> are configured to select a given plurality of sense amplifiers by driving column select (CS) <NUM> lines. <FIG> includes one column select line <NUM> by way of example and not limitation. The selected sense amplifiers are connected to the main amplifiers <NUM> via a global input/output lines (GIO) <NUM>. The main amplifiers <NUM> are configured to transfer data between the DQ pads <NUM> and the adjacent memory bank B0-B7. The main amplifiers <NUM> are coupled to adjacent memory banks through the global input/output lines <NUM>. The main amplifiers <NUM> are coupled to the DQ pads <NUM> through a global bus (GBUS) <NUM>. <FIG> includes two global input/output lines <NUM> and one global bus <NUM> by way of by way of example and not limitation.

<FIG> is a schematic diagram that illustrates the configuration of an example memory bank <NUM>. The example memory bank of <FIG> may correspond to one of the memory banks B0-B7 illustrated in <FIG>. The memory bank <NUM> may include a column decoder (YDEC) <NUM> and a main amplifier (DSA) <NUM>. The column decoder <NUM> may correspond to the column decoder <NUM> of <FIG>. The main amplifier <NUM> may correspond to the main amplifier <NUM> of <FIG>. The memory bank <NUM> may include a plurality of memory mats MAT 312a-n (collectively memory MATs <NUM>) arranged along the Y-direction. An adjacent circuit area <NUM> may be provided adjacent to the memory mats MAT <NUM> in the X-direction. The adjacent circuit area <NUM> may include a number of supporting components that are described in greater detail in connection with <FIG>. A sense amplifier area (SAA) <NUM> may be provided between two memory MATs <NUM> that are adjacent to each other in the Y-direction.

The sense amplifier area <NUM> may include a plurality of sense amplifiers <NUM>. <FIG> shows one sense amplifier <NUM> by way of example and not limitation. In some embodiments as shown in <FIG>, a sense amplifier <NUM> may be coupled to a pair of bit lines BLT and BLB. A memory device in accordance with the present disclosure having such a configuration may be understood as having an open bit-line structure or architecture. Here, bit lines BLT and BLB included in a bit line pair connected to one sense amplifier <NUM> may be arranged in different memory mats MAT (that is, two memory mats MAT that are adjacent to each other in the Y-direction), respectively.

Memory MAT 312a and memory MAT 312n, which positioned in the Y-direction end portions, are so-called end mats. The memory mats MAT 312a and MAT 312n only have half the number of bit lines of the other memory mats MATb to MATm. Therefore, even though N memory mats are arranged in the Y-direction, the capacity value is that of N-<NUM> mats. As for both the end mats MAT 312a and MAT 312n, a sense amplifier area <NUM> is provided only on one Y-direction side. Therefore, the number of bit lines BL provided is one-half of the number of bit lines of a normal memory mat (e.g. MAT 312b) in which sense amplifier areas <NUM> are provided on both sides.

A sense amplifier <NUM> amplifies a potential difference generated in pairs of the bit lines BLT and BLB. Read data amplified by the sense amplifier <NUM> is transferred to local input/output lines LIO (described below in connection with <FIG>), and then further transferred to the global input/output lines (GIO) <NUM>. A main amplifier <NUM> may be coupled to sense amplifiers <NUM> in the sense amplifier area <NUM> via the global input-output lines <NUM> and components coupled to the global input/output lines <NUM>. As shown in <FIG>, a main amplifier <NUM> may couple global input/output lines <NUM> to a global bus <NUM>, which, in turn, couples to a DQ pad <NUM>.

<FIG> shows that a global input/output lines <NUM> may be laid out in the Y-direction over one or more of the memory MATs <NUM> and over one or more of the sense amplifier areas <NUM>. A number of global input/output lines <NUM> extending in the Y-direction may be provided in parallel to each other and may be connected to the main amplifier <NUM>. Although not specifically shown in <FIG>, local input/output lines may extend in the X-direction, perpendicular to the global input/output lines <NUM> that extend in the Y-direction. The coupling between and among local input/output lines, sense amplifiers <NUM>, and global input/output lines <NUM> may be understood with reference to <FIG>.

<FIG> is a schematic diagram that illustrates a data path <NUM> that provides for transfer of data between an individual memory cell (MC) <NUM> and a DQ pad <NUM>. The memory cell <NUM> may be one of a plurality of memory cells that are arranged in a grid pattern within a memory MAT <NUM>. The memory MAT <NUM> may correspond to one of the memory MATs <NUM> that are illustrated in <FIG>. As shown in <FIG>, the memory mat <NUM> is an area in which sub-word lines (SWL) <NUM> and bit lines (BT) <NUM> extend. In a memory MAT <NUM>, memory cells <NUM> are arranged at respective intersections of sub-word lines <NUM> extending in the X-direction and bit lines <NUM> extending in the Y-direction. A memory cell <NUM> may have a configuration in which a cell transistor and a cell capacitor are connected in series between a corresponding one of the bit lines <NUM> and a plate wiring (such as a pre-charge line). The cell transistor may include an n-channel MOS transistor, and a gate electrode thereof may be connected to a corresponding one of the sub-word lines <NUM>.

A sub-word line <NUM> associated with the memory mat <NUM> may be driven by a sub-word driver (SWD) <NUM>. <FIG> includes one sub-word driver <NUM> by way of example and not limitation. Each of the sub-word drivers <NUM> drive a corresponding one of the sub-word lines <NUM> according to the row address. As described above in connection with <FIG> and <FIG>, the row address is provided by a row decoder XDEC, which drives the row address onto main word lines (MWL). The sub-word drivers <NUM> provide a coupling between the main word lines (MWL) and the sub-word lines (SWL) and in so doing drive sub-word lines <NUM> with appropriate signals responsive to the row address provided by the row decoder (XDEC). One or more sub-word drivers <NUM> may be located in the adjacent circuit area <NUM>, which is illustrated in <FIG>. <FIG> shows an example main word line <NUM>, which provides input to one or more sub-word drivers <NUM>.

The data path <NUM> shown in <FIG> additionally includes an example local input/output line (LIO) <NUM> and an example global input/output line (GIO) <NUM>. The local input/output lines <NUM> and the global input/output lines <NUM> are hierarchically structured input/output lines. The local input/output line <NUM> is used for transferring read data out from a memory cell <NUM> and/or write data to the memory cell <NUM>. The local input/output line <NUM> may be differential data input/output lines for transferring read data and write data by using a pair of lines. The global input/output lines <NUM> are used for transferring data between the main amplifier (DSA) <NUM> and the various memory MATs of a particular memory bank, which memory bank includes the memory MAT <NUM> shown in <FIG>. Thus, the global input/output lines <NUM> are used for transferring data from the memory bank to the main amplifier <NUM> and transferring write data from the main amplifier <NUM> to the memory bank. The global input/output lines <NUM> may also be differential data input/output lines for transferring read data and write data by using a pair of lines.

The data path <NUM> shown in <FIG> illustrates various components that are proximate to the memory MAT <NUM> and that facilitate transfer of data between the memory cell <NUM> and the local input/output line <NUM>. A sense amplifier <NUM> is coupled to the memory cell <NUM> via the bit line <NUM>. The sense amplifier <NUM> is configured to transfer data between the bit line <NUM> and the local input/output lines <NUM> via a column switch (YSW) <NUM>. The column switch <NUM> may be driven by a column select CS line (<FIG>) that enables a particular sense amplifier <NUM> to transfer its data onto the local input output lines <NUM>. The local input lines <NUM> are received as input at a sub-amplifier (Sub Amp) <NUM>. The sub-amplifier <NUM> is generally configured to transfer data between the local input/output lines <NUM> and the global input/output lines <NUM>. One or more column switches <NUM> may be located in the sense amplifier area <NUM>, which is illustrated in <FIG>. One or more sub-amplifiers <NUM> may be located in the adjacent circuit area <NUM>, which is illustrated in <FIG>.

Referring again to <FIG>, a memory device <NUM> in accordance with the present disclosure may include a power generator block <NUM> that provides power to various components located in the memory area <NUM> of the memory device <NUM>. In this regard, the power generator blocks <NUM> may be provided in association with one or more transmission lines or other power distribution lines that supply power to the various memory device <NUM> components. One example of such a power distribution line is the iRDL line. As used herein, "iRDL" refers a redistribution layer formed in a semiconductor process before an assembly process. In some cases, an iRDL line is in a metal <NUM> layer (M4) over a metal <NUM> layer (M3). An iRDL line may be provided in an uppermost layer, which may be the lowest resistivity layer in the device. An example of such an iRDL line is illustrated in <FIG>.

<FIG> is a schematic diagram that illustrates an example layout for a memory device <NUM> in accordance with the present disclosure. The memory device <NUM> of <FIG> may correspond to the memory device of <FIG>. Thus, the memory device <NUM> includes memory area <NUM> and a peripheral circuit <NUM> area. The memory area <NUM> may include a plurality of memory banks B0-B7, where a left side of the memory area <NUM> includes even-numbered memory banks (B0, B2, B4, B6) and a right side of the memory area <NUM> includes odd-numbered (B1, B3, B5, B7) memory banks. The peripheral circuit <NUM> area may include various circuit components such as one or more power generators <NUM>, one or more DQ pads <NUM>, and/or one or more column address blocks <NUM>. Within the memory area <NUM>, the memory device additionally includes row decoders (XDEC) <NUM> that drive main word lines (MWL) <NUM>, column decoders (YDEC) <NUM> that drive column select (CS) lines <NUM>, and main amplifiers (DSA) <NUM> that provide coupling between global input/output lines (GIO) <NUM> and global buses (GBUS) <NUM>.

In order to reduce power dissipation and heating issues associated with power distribution, the memory device may include a redistribution layer that includes low resistivity lines that provide power to certain locations within the device. This layer may be referred to as an "iRDL layer" and may contain "iRDL lines. " The iRDL layer be formed in a semiconductor process that occurs before an assembly process. An iRDL layer may be an uppermost layer of the device, which may be the lowest resistivity layer in the device. In some cases, an iRDL layer is a metal <NUM> layer(M4) over the metal <NUM> layer(M3). The memory device <NUM> of <FIG> includes example iRDL lines <NUM> that are coupled to the power generator blocks <NUM>. <FIG> show two iRDL lines <NUM> by way of example and not limitation. It should be appreciated a memory device <NUM> in accordance with the present disclosure may include more or less iRDL lines <NUM> depending on the implementation.

In order for power from the iRDL lines <NUM> to be provided to various memory device <NUM> components, the memory device <NUM> may include one or more vias that provide conductive pathways between various layers of the memory device <NUM>. Continuing with the example above where the iRDL lines are routed in a metal <NUM> layer, the memory device <NUM> may include one or more M4-M3 vias that provide a conductive pathways between the metal <NUM> layer and a metal <NUM> layer. Using the one or more M4-M3 vias, power may be provided from the iRDL lines <NUM> to components in the metal <NUM> layer. In some cases, the metal <NUM> layer may contain a network of power distribution lines that distribute power to various points in the memory device <NUM>. Components that consume the power provided by this power distribution network may have power input couplings that are located in lower device layers, such as a metal <NUM> layer (M2). Thus, a memory device <NUM> may additionally include M3-M2 vias that provide a conductive pathways between the metal <NUM> layer and the metal <NUM> layer.

In determining locations for vias between layers of the memory device <NUM>, consideration is given to the location of other components that are located in the various device layers. For example, the metal <NUM> layer may include wiring that implements various signal lines such as the input/output lines (GIO) <NUM>, global buses (GBUS) <NUM>, and/or various control signal lines for components such as the column decoder <NUM>, the main amplifier <NUM>, and so on. Thus, an M4-M3 via that provides a conductive pathway between the metal <NUM> layer and the metal <NUM> layer may be placed in an area of the memory device <NUM> that is otherwise free of signal wirings in the metal <NUM> layer. Such an M4-M3 via may provide a coupling between the iRDL lines <NUM> and a network of power distribution lines that distribute power to various points in the memory device <NUM>. This power distribution network may also couple to power lines or couplings that are located in the metal <NUM> layer. Accordingly, the memory device <NUM> may also include M3-M2 vias that may or may not be located proximate to the M4-M3 vias. In determining locations for the M3-M2 vias, consideration is given to the location of other wiring and components in the metal <NUM> layer. One example of a wiring that may be present in the metal <NUM> layer is the main word lines (MWL) <NUM> that are driven by the row decoders (XDEC) <NUM>.

Conventionally, a memory device includes a dedicated area for routing of iRDL vias. These dedicated areas are used to avoid interference with control signals or other wiring that may be present in areas that underlie the redistribution layer. These dedicated areas result in unwanted increases in chip size, power consumption and other disadvantages. Embodiments of the present disclosure avoid conventional arrangements that include a dedicated iRDL layout region. In this regard, present embodiments may route iRDL vias in device locations that lack certain metal layer wirings, but contain other device components such that the iRDL via routing area is not exclusively dedicated to iRDL vias. Continuing with the example above where the iRDL layer is routed in a metal <NUM> layer, a memory device in accordance with present embodiments may include one or more M4-M3 vias that provides conductive pathways between iRDL lines and a power distribution network that is located at least partially in the metal <NUM> layer. The memory device may additionally include one or M3-M2 vias that further distribute power to lower layers of the power distribution network.

<FIG> provides a first example of a memory device <NUM> in accordance with the present disclosure that routes iRDL vias in device locations that lack certain metal layer wirings, but contain other device components such that the iRDL via routing area is not exclusively dedicated to iRDL vias. More specifically, the memory device <NUM> of <FIG> routes iRDL vias above an edge MAT. As discussed in connection with <FIG>, a memory mat MAT that is positioned at one end of a column of memory MATs is referred to as an "edge MAT. " An edge MAT typically has half the memory capacity as it is typically associated with only one sense amplifier area (SSA). <FIG> shows a plurality of memory MATs 312a-n, including a first edge MAT 312a and a second edge MAT 312n. The first edge MAT 312a is the closest edge MAT to the main amplifier <NUM>. The second edge MAT 312n is the farthest edge MAT from the main amplifier <NUM>. <FIG> also shows global input/output lines <NUM> that are laid out in the Y-direction over one or more of the memory MATs <NUM> and over one or more of the sense amplifier areas <NUM>. As can be seen in <FIG>, the global input/output lines <NUM> extend over all of the memory MATs except for the second edge MAT 312n that is farthest from the main amplifier <NUM>. It is this area, the area over the edge MAT farthest from the main amplifier (DSA), that an iRDL via may be routed in accordance with an embodiment of the present disclosure.

In <FIG>, iRDL routing areas located in the even number memory banks (B0, B2, B4, B6) are generally indicated with reference number <NUM>. An iRDL routing area <NUM> generally corresponds to an edge MAT (and the sense amplifier area (SAA) associated with the edge MAT) that is located farthest from the main amplifier <NUM> associated with the memory bank to which the edge MAT belongs. As can be seen in <FIG> (and more particularly in <FIG>), global input/output lines <NUM> are not located in this iRDL routing area <NUM>. Because the iRDL routing area <NUM> lacks global input/output lines <NUM> or other metal <NUM> layer wiring at least in certain areas, one or more iRDL vias may be routed in the iRDL routing area <NUM>. The routing of these one or more iRDL vias may be understood with reference to <FIG> which includes an enlarged view of an iRDL routing area <NUM>.

<FIG> is a plan view schematic diagram of an iRDL routing area <NUM>. The iRDL routing area <NUM> may correspond to the iRDL routing area <NUM> of <FIG> The iRDL routing area <NUM> includes a sense amplifier area <NUM> and edge MAT <NUM>. Global bus lines <NUM> extend in the Y-direction across both the sense amplifier area <NUM> and the edge MAT <NUM>. Control signals <NUM>, such as for a column decoder (YDEC) and/or a main amplifier (DSA), extend in the Y-direction across both the sense amplifier area <NUM> and the edge MAT <NUM>. Global input/output (GIO) lines <NUM> extend in the Y-direction, but end at the sense amplifier area <NUM> such that they do not extend into the edge MAT <NUM> area. Main word lines (MWL) <NUM> extend across the edge MAT <NUM> in the X-direction. The global bus lines <NUM>, the control signal lines <NUM>, and the global input/output lines <NUM> may be routed in a metal <NUM> layer. The main word lines <NUM> may be routed in a metal <NUM> layer.

<FIG> additionally includes iRDL lines 628a-d that extend in the Y-direction across both the sense amplifier area <NUM> and the edge MAT <NUM>. <FIG> includes four iRDL lines 628a-d (collectively iRDL lines <NUM>) by way of example and not limitation. As discussed in connection with <FIG>, an iRDL line may be coupled to a power generator block and may be configured to distribute power to various points within a memory device. The iRDL lines <NUM> of <FIG> include two outer iRDL lines 628a,d and two inner iRDL lines 628b,c. The iRDL lines <NUM> may be routed in a metal <NUM> layer.

The iRDL lines <NUM> may provide power to a power distribution network that is disposed in metal layers that underlie the metal layer of the iRDL line (M4 in one example). In order for power to be provided from the iRDL lines <NUM> to the lower metal layers, the memory device may include vias that provide conductive pathways between various metal layers. iRDL vias (M4-M3 vias) <NUM> may provide coupling between the iRDL lines <NUM> and portions of the power distribution network that are located in the metal <NUM> layer. In the embodiment of <FIG>, the iRDL vias <NUM> are located above the edge MAT <NUM> in areas that lack global input/output lines <NUM> or other M3 wiring. As shown in <FIG>, the area above the edge MAT <NUM> and below the two outer iRDL lines 628a,d lacks global input/output lines <NUM> or other M3 wiring, while the area above the edge MAT <NUM> and below the two inner iRDL lines 628b,c includes M3 wiring such as the global bus lines <NUM> and the control signal lines <NUM>. Thus, in the embodiment of <FIG>, the iRDL vias <NUM> are located in the area above the edge MAT <NUM> and below the two outer iRDL lines 628a,d.

As shown in <FIG>, the iRDL vias <NUM> may be coupled to power distribution nodes <NUM> that are coupled to various power distribution wires. First power distribution wires <NUM> may be located in the metal <NUM> layer. First power distribution wires <NUM> may be arranged in the X-direction and may be configured to distribute power to the memory bank associated with memory MAT <NUM>, as well as to memory banks that are adjacent in the X-direction. Second power distribution wires <NUM> may be located in the metal <NUM> layer. The second power distribution wires <NUM> may be generally arranged in the Y-direction and configured to transmit power from the first power distribution wires <NUM> to components that are located adjacently in the Y-direction. For example, the second power distribution wires <NUM> may transmit power from the first power distribution wires <NUM> to sense amplifiers are that located in the sense amplifier area <NUM>.

The power distribution network of <FIG> may additionally include M3-M2 vias that provide conductive pathways between components and wires in the metal <NUM> layer and the metal <NUM> layer. A first group of M3-M2 vias <NUM> provide a conductive pathway between the distribution nodes <NUM> and the first power distribution wires <NUM>. <FIG> shows M3-M2 vias <NUM> between the distribution nodes <NUM> and particular first power distribution wires <NUM> by way of example and not limitation. In alternative embodiments, M3-M2 vias <NUM> may be provided between the distribution nodes <NUM> and any of the first power distribution wires <NUM> shown in <FIG>. Possible M3-M2 vias <NUM> routing locations are generally indicated in <FIG> by enclosed areas <NUM>. A second group of M3-M2 vias <NUM> provide a conductive pathway between the first power distribution wires <NUM> and the second distribution wires <NUM>. A third group of M3-M2 vias <NUM> provide a conductive pathway between the second distribution wires <NUM> and components in the sense amplifier area <NUM>.

<FIG> is a cross-sectional view of the iRDL routing area <NUM> of <FIG>. The cross section <NUM> of <FIG> is taken with respect to the A-A line shown in <FIG>. <FIG> is given to provide a greater understanding of the relationship between the components discussed in <FIG>. <FIG> includes a cross-sectional view of the sense amplifier area <NUM> and the edge MAT <NUM>. <FIG> also shows a portion of a full memory MAT <NUM> that is located on the opposite side of the sense amplifier area <NUM> from that of the edge MAT <NUM>. Additionally, <FIG> includes cross-sectional portions of an outer iRDL line 628a, a power distribution node <NUM>, first power distribution wires <NUM>, second power distribution wires <NUM>, global bus lines <NUM>, global input/output lines <NUM>, and main word lines <NUM>. It should be noted that the second power distribution wires <NUM> and global bus lines <NUM> are generally configured to run in the Y-direction, but the cross-sectional view of <FIG> captures a small portion of those lines that run in the X-direction. As show in <FIG>, the iRDL line 628a is routed in the metal <NUM> layer. The power distribution node <NUM>, the second power distribution wires <NUM>, the global bus lines <NUM>, and the global input/output lines <NUM> are routed in the metal <NUM> layer. The first power distribution wires <NUM> and the main word lines <NUM> are routed in the metal <NUM> layer. <FIG> also shows an iRDL via <NUM> that couples the iRDL line 628a to the power distribution node <NUM> and a first M3-M2 via <NUM> that couples the distribution node <NUM> to a first power distribution wire <NUM>. The second and third groups of M3-M2 <NUM>, <NUM> are outside of the A-A cross section and thus not shown in <FIG>.

Referring again to <FIG>, the memory device <NUM> additionally includes iRDL routing areas located in odd numbered memory banks (B1, B3, B5, B7). iRDL routing areas located in the odd number memory banks (B1, B3, B5, B7) are generally indicated with reference number <NUM>. An iRDL routing area <NUM> generally corresponds to an edge MAT (and the sense amplifier area (SAA) associated with the edge MAT) that is located farthest from the main amplifier <NUM> associated with the memory bank to which the edge MAT belongs. As can be seen in <FIG> (and more particularly in <FIG>), global input/output lines <NUM> are not located in this iRDL routing area <NUM>. Additionally, global bus lines <NUM> are not located in this iRDL routing area <NUM>. Because the iRDL routing area <NUM> lacks global input/output lines <NUM>, global bus lines <NUM> or other metal <NUM> layer lines at least in certain areas, one or more iRDL vias may be routed in the iRDL routing area <NUM>. The routing of these one or more iRDL vias may be understood with reference to <FIG> which includes an enlarged view of an iRDL routing area <NUM>.

<FIG> is a plan view schematic diagram of an iRDL routing area <NUM>. The iRDL routing area <NUM> may correspond to an iRDL routing area <NUM> of <FIG> The iRDL routing area <NUM> includes a sense amplifier area <NUM> and edge MAT <NUM>. Control signals <NUM>, such as for a column decoder (YDEC) and/or a main amplifier (DSA), extend in the Y-direction across both the sense amplifier area <NUM> and the edge MAT <NUM>. Global input/output (GIO) lines <NUM> extend in the Y-direction, but end at the sense amplifier area <NUM> such that they do not extend into the edge MAT <NUM>. Main word lines (MWL) <NUM> extend across the edge MAT <NUM> in the X-direction. The control signal lines <NUM>, and the global input/output lines <NUM> may be routed in a metal <NUM> layer. The main word lines <NUM> may be routed in a metal <NUM> layer.

<FIG> additionally includes iRDL lines 828a-d that extend in the Y-direction across both the sense amplifier area <NUM> and the edge MAT <NUM>. <FIG> includes four iRDL lines 828a-d (collectively iRDL lines <NUM>) by way of example and not limitation. As discussed in connection with <FIG>, an iRDL line may be coupled to a power generator block and may be configured to distribute power to various points within a memory device. The iRDL lines <NUM> of <FIG> include two outer iRDL lines 828a,d and two inner iRDL lines 828b,c. The iRDL lines <NUM> may be routed in a metal <NUM> layer.

The iRDL lines <NUM> may provide power to a power distribution network that is disposed in metal layers that underlie the metal layer of the iRDL line (M4 in one example). In order for power to be provided from the iRDL lines <NUM> to the lower metal layers, the memory device may include vias that provide conductive pathways between various metal layers. iRDL vias (M4-M3 vias) <NUM> may provide coupling between the iRDL lines <NUM> and portions of the power distribution network that are located in the metal <NUM> layer. In the embodiment of <FIG>, the iRDL vias <NUM> are located above the edge MAT <NUM> in areas that lack global input/output lines <NUM> or other M3 wiring. As shown in <FIG>, the area above the edge MAT <NUM> and below the two outer iRDL lines 828a,d lacks global input/output lines <NUM> or other M3 wiring. Additionally, the area above the edge MAT <NUM> and below one inner iRDL lines 828b also lacks global input/output lines <NUM> or other M3 wiring, while the area above the edge MAT <NUM> and below other inner iRDL lines 828c includes M3 wiring such as the control signal lines <NUM>. Thus, in the embodiment of <FIG>, the iRDL vias <NUM> are located in the areas above the edge MAT <NUM> and below the two outer iRDL lines 828a,d and the above the edge MAT <NUM> and below one inner iRDL lines 828b.

As shown in <FIG>, the iRDL vias <NUM> may be coupled to power distribution nodes <NUM> that are coupled to various power distribution wires. First power distribution wires <NUM> may be located in the metal <NUM> layer. First power distribution wires <NUM> may be arranged in the X-direction and may be configured to distribute power to the memory bank associated with memory mat <NUM>, as well as to memory banks that are adjacent in the X-direction. Second power distribution wires <NUM> may be located in the metal <NUM> layer. The second power distribution wires <NUM> may be generally arranged in the Y-direction and configured to transmit power from the first power distribution wires <NUM> to components that are located adjacently in the Y-direction. For example, the second power distribution wires <NUM> may transmit power from the first power distribution wires <NUM> to sense amplifiers are that located in the sense amplifier area <NUM>.

The power distribution network of <FIG> may additionally M3-M2 vias that provide conductive pathways between components and wires in the metal <NUM> layer and the metal <NUM> layer. A first group of M3-M2 vias <NUM> provide a conductive pathway between the distribution nodes <NUM> and the first power distribution wires <NUM>. <FIG> shows M3-M2 vias <NUM> between the distribution nodes <NUM> and particular first power distribution wires <NUM> by way of example and not limitation. In alternative embodiments, M3-M2 vias <NUM> may be provided between the distribution nodes <NUM> and any of the first power distribution wires <NUM> shown in <FIG>. Possible M3-M2 vias <NUM> routing locations are generally indicated in <FIG> by enclosed areas <NUM>. A second group of M3-M2 vias <NUM> provide a conductive pathway between the first power distribution wires <NUM> and the second distribution wires <NUM>. A third group of M3-M2 vias <NUM> provide a conductive pathway between the second distribution wires <NUM> and components in the sense amplifier area <NUM>.

<FIG> provides a second example of a memory device <NUM> in accordance with the present disclosure that routes iRDL vias in device locations that lack certain metal layer wirings, but contain other device components such that the iRDL via routing area is not exclusively dedicated to iRDL vias. More specifically, the memory device <NUM> of <FIG> routes iRDL vias above both an edge MAT and a column decoder (YDEC).

The memory device <NUM> of <FIG> additionally includes example iRDL lines <NUM> that are coupled to the power generator blocks <NUM>. <FIG> show two iRDL lines <NUM> by way of example and not limitation. It should be appreciated a memory device <NUM> in accordance with the present disclosure may include more or less iRDL lines <NUM> depending on the implementation. The iRDL lines <NUM> are generally configured to distribute power to various points within the memory area <NUM>. The memory device <NUM> includes iRDL routing areas <NUM> located in the even number memory banks (B0, B2, B4, B6). An iRDL routing area <NUM> generally corresponds to an edge MAT (and the sense amplifier area (SAA) associated with the edge MAT) that is located farthest from the main amplifier <NUM> associated with the memory bank to which the edge MAT belongs. An iRDL routing area <NUM> additionally includes the column decoder <NUM> that is adjacent to the edge MAT. As can be seen in <FIG> (and more particularly in <FIG>), global input/output lines <NUM> are not located in this iRDL routing area <NUM>. Because the iRDL routing area <NUM> lacks global input/output lines <NUM> or other metal <NUM> layer at least in certain areas, one or more iRDL vias may be routed in the iRDL routing area <NUM>. The routing of these one or more iRDL vias may be understood with reference to <FIG> which includes an enlarged view of an iRDL routing area <NUM>.

<FIG> is a plan view schematic diagram of an iRDL routing area <NUM>. The iRDL routing area <NUM> may correspond to the iRDL routing area <NUM> of <FIG> The iRDL routing area <NUM> includes a sense amplifier area <NUM>, edge MAT <NUM>, and column decoder <NUM>. Global bus lines <NUM> extend in the Y-direction across the sense amplifier area <NUM>, the edge MAT <NUM>, and the column decoder <NUM>. Control signals <NUM>, such as for the column decoder <NUM> and/or a main amplifier (DSA), extend in the Y-direction across the sense amplifier area <NUM>, the edge MAT <NUM>, and the column decoder <NUM>. Global input/output (GIO) lines <NUM> extend in the Y-direction, but end at the sense amplifier area <NUM> such that they do not extend into the edge MAT <NUM> or into the column decoder <NUM>. Main word lines (MWL) <NUM> extend across the edge MAT <NUM> in the X-direction. The global bus lines <NUM>, the control signal lines <NUM>, and the global input/output lines <NUM> may be routed in a metal <NUM> layer. The main word lines <NUM> may be routed in a metal <NUM> layer.

<FIG> additionally includes iRDL lines 1028a-d that extend in the Y-direction across the sense amplifier area <NUM>, the edge MAT <NUM>, and the column decoder <NUM>. <FIG> includes four iRDL lines 1028a-d (collectively iRDL lines <NUM>) by way of example and not limitation. As discussed in connection with <FIG>, an iRDL line may be coupled to a power generator block and may be configured to distribute power to various points within a memory device. The iRDL lines <NUM> of <FIG> include two outer iRDL lines 1028a,d and two inner iRDL lines 1028b,c. The iRDL lines <NUM> may be routed in a metal <NUM> layer.

The iRDL lines <NUM> may provide power to a power distribution network that is disposed in metal layers that underlie the metal layer of the iRDL line (M4 in one example). In order for power to be provided from the iRDL lines <NUM> to the lower metal layers, the memory device may include vias that provide conductive pathways between various metal layers. iRDL vias (M4-M3 vias) <NUM> may provide coupling between the iRDL lines <NUM> and portions of the power distribution network that are located in the metal <NUM> layer. In the embodiment of <FIG>, the iRDL vias <NUM> are located above the edge MAT <NUM> and the column decoder <NUM> in areas that lack global input/output lines <NUM> or other M3 wiring. As shown in <FIG>, the area above the edge MAT <NUM> and the column decoder <NUM> and below the two outer iRDL lines 1028a,d lacks global input/output lines <NUM> or other M3 wiring, while the area above the edge MAT <NUM> and the column decoder <NUM> and below the two inner iRDL lines 1028b,c includes M3 wiring such as the global bus lines <NUM> and the control signal lines <NUM>. Thus, in the embodiment of <FIG>, the iRDL vias <NUM> are located in the area above the edge MAT <NUM> and the column decoder <NUM> and below the two outer iRDL lines 1028a,d.

The power distribution network of <FIG> may additionally M3-M2 vias that provide conductive pathways between components and wires in the metal <NUM> layer and the metal <NUM> layer. A first group of M3-M2 vias <NUM> provide a conductive pathway between the power distribution nodes <NUM> and the first power distribution wires <NUM>. <FIG> shows M3-M2 vias <NUM> between the distribution nodes <NUM> and particular first power distribution wires <NUM> by way of example and not limitation. In alternative embodiments, M3-M2 vias <NUM> may be provided between the distribution nodes <NUM> and any of the first power distribution wires <NUM> shown in <FIG>. Possible M3-M2 vias <NUM> routing locations are generally indicated in <FIG> by enclosed areas <NUM>. A second group of M3-M2 vias <NUM> provide a conductive pathway between the first power distribution wires <NUM> and the second distribution wires <NUM>. A third group of M3-M2 vias <NUM> provide a conductive pathway between the second distribution wires <NUM> and components in the sense amplifier area <NUM>.

Referring again to <FIG>, the memory device <NUM> additionally includes iRDL routing areas located in odd numbered memory banks (B1, B3, B5, B7). iRDL routing areas located in the odd number memory banks (B1, B3, B5, B7) are generally indicated with reference number <NUM>. An iRDL routing area <NUM> generally corresponds to an edge MAT (and the sense amplifier area (SAA) associated with the edge MAT) that is located farthest from the main amplifier <NUM> associated with the memory bank to which the edge MAT belongs. An iRDL routing area <NUM> additionally includes the column decoder <NUM> that is adjacent to edge MAT. As can be seen in <FIG> (and more particularly in <FIG>), global input/output lines <NUM> are not located in this iRDL routing area <NUM>. Additionally, global bus lines <NUM> are not located in this iRDL routing area <NUM>. Because the iRDL routing area <NUM> lacks global input/output lines <NUM>, global bus lines <NUM> or other metal <NUM> layer at least in certain areas, one or more iRDL vias may be routed in the iRDL routing area <NUM>. The routing of these one or more iRDL vias may be understood with reference to <FIG> which includes an enlarged view of an iRDL routing area <NUM>.

<FIG> is a plan view schematic diagram of an iRDL routing area <NUM>. The iRDL routing area <NUM> may correspond to the iRDL routing area <NUM> of <FIG> The iRDL routing area <NUM> includes a sense amplifier area <NUM>, edge MAT <NUM>, and column decoder <NUM>. Control signals <NUM>, such as for the column decoder <NUM> and/or a main amplifier (DSA), extend in the Y-direction across the sense amplifier area <NUM>, the edge MAT <NUM>, and the column decoder <NUM>. Global input/output (GIO) lines <NUM> extend in the Y-direction, but end at the sense amplifier area <NUM> such that they do not extend into the edge MAT <NUM> or into the column decoder <NUM>. Main word lines (MWL) <NUM> extend across the edge MAT <NUM> in the X-direction. The control signal lines <NUM> and the global input/output lines <NUM> may be routed in a metal <NUM> layer. The main word lines <NUM> may be routed in a metal <NUM> layer.

<FIG> additionally includes iRDL lines 1128a-d that extend in the Y-direction across the sense amplifier area <NUM>, the edge MAT <NUM>, and the column decoder <NUM>. <FIG> includes four iRDL lines 1128a-d (collectively iRDL lines <NUM>) by way of example and not limitation. As discussed in connection with <FIG>, an iRDL line may be coupled to a power generator block and may be configured to distribute power to various points within a memory device. The iRDL lines <NUM> of <FIG> include two outer iRDL lines 1128a,d and two inner iRDL lines 1128b,c. The iRDL lines <NUM> may be routed in a metal <NUM> layer.

The iRDL lines <NUM> may provide power to a power distribution network that is disposed in metal layers that underlie the metal layer of the iRDL line (M4 in one example). In order for power to be provided from the iRDL lines <NUM> to the lower metal layers, the memory device may include vias that provide conductive pathways between various metal layers. iRDL vias (M4-M3 vias) <NUM> may provide coupling between the iRDL lines <NUM> and portions of the power distribution network that are located in the metal <NUM> layer. In the embodiment of <FIG>, the iRDL vias <NUM> are located above the edge MAT <NUM> and the column decoder <NUM> in areas that lack global input/output lines <NUM> or other M3 wiring. As shown in <FIG>, the area above the edge MAT <NUM> and the column decoder <NUM> and below the two outer iRDL lines 1128a,d lacks global input/output lines <NUM> or other M3 wiring. Additionally, the area above the edge MAT <NUM> and the column decoder <NUM> and below one inner iRDL line 1128b also lacks global input/output lines <NUM> or other M3 wiring, while the area above the edge MAT <NUM> and the and the column decoder <NUM> and below the other inner iRDL line 1128c includes M3 wiring such as the control signal lines <NUM>. Thus, in the embodiment of <FIG>, the iRDL vias <NUM> are located in the areas above the edge MAT <NUM> and the column decoder <NUM> and below the two outer iRDL lines 1128a,d and above the edge MAT <NUM> and the column decoder <NUM> and below the one inner iRDL line 1128b.

As shown in <FIG>, the iRDL vias <NUM> may be coupled to power distribution nodes <NUM> that are coupled to various power distribution wires. First power distribution wires <NUM> may be located in the metal <NUM> layer. First power distribution wires <NUM> may be arranged in the X-direction and may be configured to distribute power to the memory bank associated with memory mat <NUM>, as well as to memory banks that are adjacent in the X-direction. Second power distribution wires <NUM> may be located in the metal <NUM> layer. The second power distribution wires <NUM> may be generally arranged in the Y-direction and configured to transmit power from the first power distribution wires <NUM> to components that are located adjacently in the Y-direction. For example, the second power distribution wires <NUM> may transmit power from the first power distribution wires <NUM> to sense amplifiers that are located in the sense amplifier area <NUM>.

The power distribution network of <FIG> may additionally include M3-M2 vias that provide conductive pathways between components and wires in the metal <NUM> layer and the metal <NUM> layer. A first group of M3-M2 vias <NUM> provide a conductive pathway between the power distribution nodes <NUM> and the first power distribution wires <NUM>. <FIG> shows M3-M2 vias <NUM> between the distribution nodes <NUM> and particular first power distribution wires <NUM> by way of example and not limitation. In alternative embodiments, M3-M2 vias <NUM> may be provided between the distribution nodes <NUM> and any of the first power distribution wires <NUM> shown in <FIG>. Possible M3-M2 vias <NUM> routing locations are generally indicated in <FIG> by enclosed areas <NUM>. A second group of M3-M2 vias <NUM> provide a conductive pathway between the first power distribution wires <NUM> and the second distribution wires <NUM>. A third group of M3-M2 vias <NUM> provide a conductive pathway between the second distribution wires <NUM> and components in the sense amplifier area <NUM>.

<FIG> provides a third example of a memory device <NUM> in accordance with the present disclosure that routes iRDL vias in device locations that lack certain metal layer wirings, but contain other device components such that the iRDL via routing area is not exclusively dedicated to iRDL vias. More specifically, the memory device <NUM> of <FIG> routes iRDL vias above two adjacent edge MATs that face each other.

<FIG> is a schematic diagram that illustrates an example layout for a memory device <NUM> in accordance with the present disclosure. The memory device <NUM> of <FIG> is an alternative configuration with some similarities to the memory device <NUM> of <FIG>. Thus, the memory device <NUM> includes memory area <NUM> and a peripheral circuit <NUM> area. The memory area <NUM> may include a plurality of memory banks, three of which are shown in the figure by way of example and limitation. The peripheral circuit <NUM> area may include various circuit components such as one or more power generators, one or more DQ pads, and/or one or more column address blocks. The various components that may be included in the peripheral circuit <NUM> area are omitted from the drawing in order to simply the figure. Within the memory area <NUM>, the memory device additionally includes row decoders (XDEC) <NUM>, column decoders (YDEC) <NUM>, and main amplifiers (DSA) <NUM> that provide coupling between global input/output lines (GIO) <NUM> and global buses (GBUS). Global buses are also omitted from the omitted from the drawing in order to simply the figure.

The memory device <NUM> includes iRDL routing areas <NUM> located above two adjacent edge MATs that face each other. An iRDL routing area <NUM> generally corresponds to two edge MATs that face each other and that are located halfway between two main amplifiers <NUM> associated with the memory bank to which the edge MATs belongs. As can be seen in <FIG>, global input/output lines <NUM> are not located in this iRDL routing area <NUM>. Because the iRDL routing area <NUM> lacks global input/output lines <NUM> or other metal <NUM> layer at least in certain areas, one or more iRDL vias may be routed in the iRDL routing area <NUM>. The routing of these one or more iRDL vias may be understood with reference to <FIG> which includes an enlarged view of an iRDL routing area <NUM>.

<FIG> is a plan view schematic diagram of an iRDL routing area <NUM>. The iRDL routing area <NUM> may correspond to the iRDL routing area <NUM> of <FIG>. The iRDL routing area <NUM> includes a sense amplifier areas <NUM> and two edge MATs <NUM> that face each other. Global bus lines <NUM> extend in the Y-direction across the sense amplifier areas <NUM> and the edge MATs <NUM> Control signals, such as for a column decoder (YDEC) and/or a main amplifier (DSA), may also extend in the Y-direction across the sense amplifier areas <NUM> and the edge MATs <NUM>. Global input/output (GIO) lines <NUM> extend in the Y-direction, but end at the sense amplifier areas <NUM> such that they do not extend into the edge MATs <NUM>. Main word lines (MWL) <NUM> extend across the edges MAT <NUM> in the X-direction. The global bus lines <NUM> and the global input/output lines <NUM> may be routed in a metal <NUM> layer. The main word lines <NUM> may be routed in a metal <NUM> layer.

<FIG> additionally includes iRDL lines 1328a-d that extend in the Y-direction across the sense amplifier areas <NUM> and the edge MATs <NUM>. <FIG> includes four iRDL lines 1328a-d (collectively iRDL lines <NUM>) by way of example and not limitation. An iRDL line may be coupled to a power generator block and may be configured to distribute power to various points within a memory device. The iRDL lines <NUM> of <FIG> include two outer iRDL lines 1328a,d and two inner iRDL lines 1028b,c. The iRDL lines <NUM> may be routed in a metal <NUM> layer.

The iRDL lines <NUM> may provide power to a power distribution network that is disposed in metal layers that underlie the metal layer of the iRDL line (M4 in one example). In order for power to be provided from the iRDL lines <NUM> to the lower metal layers, the memory device may include vias that provide conductive pathways between various metal layers. iRDL vias (M4-M3 vias) <NUM> may provide coupling between the iRDL lines <NUM> and portions of the power distribution network that are located in the metal <NUM> layer. In the embodiment of <FIG>, the iRDL vias <NUM> are located above the edge MATs <NUM> in areas that lack global input/output lines <NUM> or other M3 wiring. As shown in <FIG>, the area above the edges MAT <NUM> and below the two outer iRDL lines 1328a,d lacks global input/output lines <NUM> or other M3 wiring, while the area above the edge MAT <NUM> and below the two inner iRDL lines 1328b,c includes M3 wiring such as the global bus lines <NUM>. Thus, in the embodiment of <FIG>, the iRDL vias <NUM> are located in the area above the edges MAT <NUM> and below the two outer iRDL lines 1328a,d.

As shown in <FIG>, the iRDL vias <NUM> may be coupled to power distribution nodes <NUM> that may be coupled to various power distribution wires. The power distribution nodes <NUM>, power distribution wires and related components may correspond to similar components described above in connection with <FIG>, <FIG>, <FIG>, and <FIG>.

The above specification, examples and data provide a complete description of the structure and use of exemplary embodiments of the invention as defined in the claims. Although various embodiments of the claimed invention have been described above with a certain degree of particularity, or with reference to one or more individual embodiments, those skilled in the art could make numerous alterations to the disclosed embodiments without departing from the scope of the claimed invention. Other embodiments are therefore contemplated. It is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative only of particular embodiments and not limiting. Changes in detail or structure may be made without departing from the basic elements of the invention as defined in the following claims.

Claim 1:
A semiconductor device, comprising:
an uppermost metal layer including a power supply enhancing wiring (628a);
power supply wiring (<NUM>) coupled to the power supply enhancing wiring through a via (<NUM>) between the uppermost metal layer and a metal layer underlying the uppermost metal layer;
at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer; and
a memory bank, including:
a plurality of sense amplifiers (<NUM>);
a plurality of memory mats coupled to the sense amplifiers, the memory mats including first and second edge mats (312a, 312n); and
a global input/output line (<NUM>) coupled to the sense amplifiers and disposed over the first edge mat (312a) and not disposed over the second edge mat (312n);
wherein the at least one memory device component disposed in vertical alignment with the via includes the second edge mat, and wherein the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer is located in an area that lacks global input/output lines.