Patent Description:
A PIN (P-type-Intrinsic-N-type) diode is a diode with an undoped intrinsic semiconductor region between a P-type semiconductor region and an N-type semiconductor region. Traditionally, PIN diode devices have been fabricated by the growth, deposition, or other placement of layers vertically on a substrate. A PIN diode is a diode with an undoped intrinsic semiconductor region between a P-type semiconductor region and an N-type semiconductor region. The P-type and N-type regions are typically heavily doped because they are used for ohmic contacts. The inclusion of the intrinsic region between the P-type and N-type regions is in contrast to an ordinary PN diode, which does not include an intrinsic region.

The top, P-type region is the anode of the PIN diode, and the bottom, N-type region or substrate is the cathode of the PIN diode. When unbiased, the PIN diode is in a high impedance state and can be represented as a capacitor, the capacitance of which is given by C=AAnodeDsiEo/T, where: AAnode is the area of the anode, Dsi is the dielelectric constant of the intrinsic silicon, Eo is the permittivity of free space, and T is the distance between the anode and cathode.

If a positive voltage larger than a threshold value is applied to the anode with respect to the cathode, a current will flow through the PIN diode and the impedance will decrease. A PIN diode in a forward biased state can be represented as a resistor whose value decreases to a minimum value as the current through the PIN diode increases. The bias to change the PIN diode from the high impedance (off) state to the low impedance (on) state can be DC or AC. In the case of an AC voltage, the magnitude must be greater than the threshold value and the duration of the positive voltage must be longer than the transit time of carriers across the intrinsic region.

A prior art monolithic diode switch is disclosed in "<NPL>.

According to the invention a monolithic multi-throw diode switch, according to claim <NUM>, and a method of manufacture of a monolithic multi-throw diode switch according to claim <NUM> are provided. Different embodiments become apparent from the content of the dependent claims.

A number of monolithic diode switches for applications in radio frequency circuits are described. In one example, a monolithic multi-throw diode switch includes a common port, a first port, and a second port. The switch also includes a first PIN diode comprising a first P-type region formed to a first depth into an intrinsic layer such the first PIN diode comprises a first effective intrinsic region of a first thickness, where the first PIN diode is electrically coupled to a node between the common port and the first port. The switch also includes a second PIN diode comprising a second P-type region formed to a second depth into the intrinsic layer such the second PIN diode comprises a second effective intrinsic region of a second thickness, where the second PIN diode is electrically coupled to a node between the common port and the second port. The switch also includes a first bias network for bias control of the first PIN diode, and a second bias network for bias control of the second PIN diode.

In one aspect of the embodiments, the first thickness of the first PIN diode is greater than the second thickness of the second PIN diode. This configuration allows for both the thinner intrinsic region PIN diode and the thicker intrinsic region PIN diode to be individually optimized. As one example, for a switch functioning in a dedicated transmit/receive mode, the first transmit PIN diode can have a thicker intrinsic region than the second receive PIN diode to maximize power handling for the transmit arm and maximize receive sensitivity and insertion loss in the receive arm.

In another aspect of the embodiments, the switch can also include at least one capacitor and at least one inductor formed over the intrinsic layer as part of the monolithic multi-throw diode switch. In other examples, the switch can also include at least one transmission line formed over the intrinsic layer as part of the monolithic multi-throw diode switch. These additional circuit elements, along with metal layers to interconnect all elements of the switch, can be realized monolithically to improve the overall reliability, circuit ruggedness, radio frequency (RF) performance, circuit size, and overall cost of the switch as compared to discrete solutions.

As examples of the monolithic diode switch topologies described herein, the first PIN diode can be series-connected in the node between the common port and the first port, and the second PIN diode can be series-connected in the node between the common port and the second port. In another case, the first PIN diode can be shunt-connected from the node between the common port and the first port to ground, and the second PIN diode can be shunt-connected from the node between the common port and the second port to ground. In still another case, the first PIN diode can be series-connected in the node between the common port and the first port, and the second PIN diode can be shunt-connected from a cathode of the first PIN diode to ground. Other topologies are described herein.

In other aspects of the embodiments, the monolithic diode switch can also include a dielectric layer over the intrinsic layer, where the dielectric layer includes a plurality of openings, the first P-type region is formed through a first opening among the plurality of openings, and the second P-type region is formed through a second opening among the plurality of openings. The first width of the first opening can be different than a second width of the second opening.

In another embodiment, a method of manufacture of a monolithic multi-throw diode switch is described. The method includes providing an intrinsic layer on an N-type semiconductor substrate, implanting a first P-type region to a first depth into the intrinsic layer to form a first PIN diode comprising a first effective intrinsic region of a first thickness, implanting a second P-type region to a second depth into the intrinsic layer to form a second PIN diode comprising a second effective intrinsic region of a second thickness, and forming at least one metal layer over the intrinsic layer to electrically couple the first PIN diode to a node between a common port and a first port of the switch and to electrically couple the second PIN diode to a node between the common port and a second port of the switch. In one aspect of the embodiment, the first thickness is greater than the second thickness. The method can also include forming at least one capacitor and at least one inductor over the intrinsic layer as part of the monolithic multi-throw diode switch.

The method can also include forming an insulating layer on the intrinsic layer, and forming a first opening in an insulating layer. In that case, implanting the first P-type region can include implanting the first P-type region through the first opening. After implanting the first P-type region, the method can also include forming a second opening in the insulating layer. In that case, implanting the second P-type region can include implanting the second P-type region through the second opening. In this example, a first width of the first opening is different than a second width of the second opening.

Aspects of the present disclosure can be better understood with reference to the following drawings. It is noted that the elements in the drawings are not necessarily to scale, with emphasis instead being placed upon clearly illustrating the principles of the embodiments. In the drawings, like reference numerals designate like or corresponding, but not necessarily the same, elements throughout the several views.

Discrete PIN diodes are available in various forms, such as in bare or discrete die form, in plastic packages, and in ceramic packages of various types (e.g., surface mount, pill packages, etc.). PIN diodes in ceramic packages are particularly suitable for waveguide, coaxial, and surface mount applications, while PIN diodes in bare die form are often used for chip and wire high frequency microwave applications.

However, many of the current design and fabrication techniques for PIN diodes are limited. These techniques cannot be used to form different PIN diode structures, such as PIN diodes with different intrinsic region thicknesses, on a single silicon wafer. Thus, the current design of multi-throw RF switches generally requires the use of a number of discrete PIN diodes, each formed from a different silicon wafer, to incorporate PIN diodes with different intrinsic region thicknesses into one multi-throw switch. These switches are formed by using a hybrid assembly of individual discrete PIN diodes mounted on a PCB or another multi-chip module format. The number of stages and specific arrangement of PIN diodes in each stage determines the low level RF turn-on, the flat leakage, and the power handling/limiting and frequency response. A monolithic (i.e., integrated silicon) solution would improve the overall reliability, circuit ruggedness, RF performance, circuit size, and overall cost of multi-throw switches and other circuits as compared to discrete solutions.

As noted above, the current design and fabrication techniques for planar PIN diodes limit the types of diode structures that can be realized across a silicon wafer. For example, one fabrication technique for PIN diodes limits all the PIN diodes fabricated on a silicon wafer to each have the same "I" (i.e., intrinsic) region thickness. This is a result of several factors. First, PIN diodes are almost exclusively vertical structures, where a metallurgical "I" region is grown or wafer bonded over a highly doped N-type substrate, where he N-type substrate forms the N+ cathode. The P+ anode is then formed in the "I" region either by ion implantation or solid state deposition of a P-type dopant, followed by a heat cycle to activate and diffuse the P-type dopant to a specie depth into the "I" region. The junction depth of the P+ anode after the thermal drive cycle will result in a reduction of the metallurgical "I" region thickness resulting in an effective or electrical "I" region thickness. This approach results in a wafer and subsequent derivative die having an "I" region of only one thickness. In other words, every PIN diode formed through this approach has the same "I" region thickness. For many high frequency circuit functions, however, it is necessary to have PIN diodes with multiple "I" region thicknesses, to achieve a control response over a desired frequency range, for example, and for other operating characteristics.

Another example fabrication technique for PIN diodes is described in <CIT>. <CIT> describes the formation of multiple thickness "I" regions on a single wafer using a photolithographic process and lateral gaps between separate P+ and N+ regions. The P+ and N+ regions are ion implanted/diffused into an undoped intrinsic silicon wafer or intrinsic region of a wafer. The difficulty with this lateral surface controlled approach is the fact that relatively high surface leakage, which is in general at least <NUM> times the leakage levels observed for bulk, vertical devices, produces a very inconsistent turn-on characteristic.

Due in part to the limitations outlined above, the current design of multi-throw switches generally requires the use of a number of discrete PIN diodes, each formed from a different silicon wafer, to incorporate PIN diodes with different "I" region thicknesses into one multi-throw switch. These switches use a hybrid assembly of individual discrete PIN diodes mounted on a printed circuit board (PCB), for example, or another multi-chip module format. The specific arrangement of PIN diodes in each arm of a multi-throw switch determines the insertion loss, isolation, incident power handling, sensitivity, linearity, and RF distortion of each switch arm. A monolithic (i.e., integrated silicon) solution would improve the overall reliability, circuit ruggedness, performance, size, and overall cost of multi-throw switches as compared to discrete solutions.

Also due to the limitations outlined above, monolithic multi-throw switches typically incorporate PIN diodes having the same "I" region thickness for all PIN diodes, regardless of the intended functional capability of each switch arm. Presently, monolithic multi-throw HNΠC switches use only one "I" region thickness for the PIN diodes in each switch arm. This monolithic HIMC approach results in a compromise solution relative to insertion loss, isolation, power handling, linearity, and distortion, because it does not account for the specific functional responses of different switch arms. For example, the primary design concerns for a transmit arm in a transmit/receive (T/R) switch include incident power handling, isolation, linearity, and distortion, while the receive arm needs to be optimized for insertion loss and sensitivity. These separate RF performance requirements require PIN diodes having different intrinsic "I" region thicknesses.

The concepts described herein achieve fully monolithic solutions for HMIC multi-throw switches using multiple, different "I" region thicknesses. The solution allows for individual optimization for insertion loss, isolation, and power handling for each switch arm/termination. The concepts can be relied upon to significantly reduce the size and improve the RF performance of switches as compared to hybrid discrete solutions.

First, a monolithic, vertical, planar semiconductor structure with a number PIN diodes having different "I" region thicknesses is described. The semiconductor structure includes an N-type silicon substrate, an intrinsic layer formed on the N-type silicon substrate, and a dielectric layer formed on the intrinsic layer. A number of openings are formed in the dielectric layer. Multiple anodes are sequentially formed into the intrinsic layer through the openings formed in the dielectric layer. For example, a first P-type region is formed through a first one the openings to a first depth into the intrinsic layer, and a second P-type region is formed through a second one of the openings to a second depth into the intrinsic layer. Additional P-type regions can be formed to other depths in the intrinsic layer. When these PIN diodes of different intrinsic regions are used in the design of multi-throw switches, the switches exhibit improved reliability, ruggedness, RF performance, size, and cost as compared to the current discrete solutions.

Additionally, a number of different monolithic, multi-throw PIN diode switches are described. The monolithic multi-throw diode switches can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a monolithic multi-throw diode switch have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. As one example, for a switch functioning in a dedicated transmit/receive mode, the first transmit PIN diode can have a thicker intrinsic region than the second receive PIN diode to maximize power handling for the transmit arm and maximize receive sensitivity and insertion loss in the receive arm. <FIG> illustrates an example vertical planar silicon PIN diode structure <NUM> with multi-thickness intrinsic regions according to various embodiments described herein. The PIN diode structure <NUM>, including three PIN diode devices, is illustrated as a representative example in <FIG>. Additional PIN diode devices (i.e., more than three) can be formed as part of the PIN diode structure <NUM>. The shapes, sizes, and relative sizes of the various layers of the PIN diode structure <NUM> are not necessarily drawn to scale in <FIG>. The layers shown in <FIG> are not exhaustive, and the PIN diode structure <NUM> can include other layers and elements not separately illustrated. The PIN diode structure <NUM> can also be formed as part of a larger integrated circuit device in combination with other diodes, capacitors, inductors, resistors, and layers of metal to electrically interconnect the circuit elements together to form switches, limiters, and other devices as described below. Additionally, a number of NIP diode devices can also be formed to have a structure similar to the structure shown in <FIG>, by interchanging the P-type and N-type dopants described below.

The PIN diode structure <NUM> includes an N-type semiconductor substrate <NUM>, an intrinsic layer <NUM>, a first P-type region <NUM> formed in the intrinsic layer <NUM>, a second P-type region <NUM> formed in the intrinsic layer <NUM>, and a third P-type region <NUM> formed in the intrinsic layer <NUM>. The P-type regions <NUM>-<NUM> are formed through openings of widths Wi-W<NUM>, respectively, in an insulating layer <NUM> as described in further detail below. The N-type semiconductor substrate <NUM> forms a cathode of the PIN diode structure <NUM>. The P-type regions <NUM>-<NUM> form first, second, and third anodes, respectively, of the PIN diode structure <NUM>. The PIN diode structure <NUM> also includes a cathode contact <NUM> formed on the N-type semiconductor substrate <NUM>, a first anode contact <NUM> formed over the first P-type region <NUM>, a second anode contact <NUM> formed over the second P-type region <NUM>, and a third anode contact <NUM> formed over the third P-type region <NUM>.

The PIN diode structure <NUM> shown in <FIG> includes three PIN diode devices, but the PIN diode structure <NUM> can be formed to include any suitable number of PIN diode devices. Electrical contact to the first PIN diode device is available between the cathode contact <NUM> and the first anode contact <NUM>. Electrical contact to the second PIN diode device is available between the cathode contact <NUM> and the second anode contact <NUM>. Electrical contact to the third PIN diode device is available between the cathode contact <NUM> and the third anode contact <NUM>.

To form the PIN diode structure <NUM> shown in <FIG>, the P-type anode regions <NUM>-<NUM> can be formed sequentially, or in turn, in the intrinsic layer <NUM> as described below with reference to <FIG>. The P-type anode region <NUM> is diffused to the least extent into the intrinsic layer <NUM>, the P-type anode region <NUM> diffused to a greater extent into the intrinsic layer <NUM>, and the P-type anode region <NUM> is diffused the greatest extent into the intrinsic layer <NUM>. Thus, the effective intrinsic region I<NUM> under the P-type anode region <NUM> is larger than the effective intrinsic region I<NUM> under the P-type anode region <NUM>, and the effective intrinsic region I<NUM> is larger than the effective intrinsic region I<NUM> under the P-type anode region <NUM>. In one example, the effective intrinsic region I<NUM> can be between about <NUM>-<NUM>, the effective intrinsic region I<NUM> can be about <NUM>, and the effective intrinsic region I<NUM> can be about <NUM>, although other ranges are within the scope of the embodiments.

The extent of the lateral diffusions, Ld1, Ld2, and Ld3 of the P-type regions <NUM>-<NUM> under the insulating layer <NUM> also vary, with the lateral diffusion Ld1 being the smallest and the lateral diffusion Ld3 being the largest. In some cases, to control the capacitance and the high-frequency characteristics of each individual PIN diode, the widths W<NUM>-W<NUM> of the openings formed in the insulating layer <NUM> can vary as compared to each other. For example, W<NUM> can be smaller than W<NUM>, and W<NUM> can be smaller than Wi.

<FIG> illustrates an example method of forming the PIN diode structure <NUM> shown in <FIG>. Alternatively, a NIP diode structure can also be formed using the method, by interchanging the P-type and N-type dopants, as described below. Although the method diagram illustrates a specific order in <FIG>, the order or the steps can differ from that which is depicted. For example, an order of two or more steps can be scrambled relative to the order shown in some cases. Also, two or more steps shown in succession can be performed, at least in part, at the same time. In some cases, one or more of the steps can be skipped or omitted. In other cases, additional steps not shown in <FIG> can be relied upon, such as steps among or after the steps shown in <FIG>.

At step <NUM>, the process includes providing or forming the N-type semiconductor substrate <NUM>. The semiconductor substrate <NUM> can be formed by melting and mixing silicon with Arsenic, among other suitable dopants, to a concentration of about <NUM>×<NUM><NUM> Arsenic atoms/cm<NUM> and then solidifying the mixture, although the substrate <NUM> can be formed by other methods to other charge carrier concentrations. Additionally or alternatively, step <NUM> can include providing or sourcing the semiconductor substrate <NUM>, such as when the semiconductor substrate <NUM> is sourced or purchased from a manufacturer. In another example, a NIP diode structure can be formed using the process shown in <FIG>. In that case, the process would include forming a P-type semiconductor substrate at step <NUM> using Boron, for example, or another P-type dopant rather than Arsenic.

At step <NUM>, the process includes providing the intrinsic layer <NUM> over the semiconductor substrate <NUM>. The intrinsic layer <NUM> can be provided or formed on the semiconductor substrate <NUM> using deposition, wafer bonding, or another suitable technique. The intrinsic layer <NUM> can have the thickness "Th" of between about <NUM>-<NUM> as shown in <FIG>, in some cases, although the intrinsic layer <NUM> can be thicker (e.g., up to about <NUM>) in other cases.

At step <NUM>, the process includes forming the insulating layer <NUM> over the intrinsic layer <NUM>. The insulating layer <NUM> can be formed over the intrinsic layer <NUM> by wet or dry oxidation in a furnace or reactor, local oxidation over the intrinsic layer <NUM>, or other suitable process step(s). The insulating layer <NUM> can be formed as a passivating dielectric layer of silicon dioxide, among other suitable dielectric insulators, on the upper surface of the intrinsic layer <NUM>. The insulating layer <NUM> can be formed to a thickness of between about 2000Å and about 5000Å, although other suitable thicknesses can be relied upon.

At step <NUM>, the process includes forming a first opening in the insulating layer <NUM>. Referring back to <FIG>, the opening of width W<NUM> can be formed at step <NUM>. The opening of width W<NUM> can be formed in the insulating layer <NUM> by etching a positive photoresist mask using wet chemistry, the application of plasma, or using another suitable technique. No other openings are formed at step <NUM>.

At step <NUM>, the process includes implanting the P-type region <NUM> into the top of the intrinsic layer <NUM>. The P-type region <NUM> can be formed by ion implantation or solid source deposition of a high concentration of P-type dopant through the opening formed in the insulating layer <NUM> at step <NUM>. The P-type region <NUM> can be formed by doping the intrinsic layer <NUM> with Boron, for example, to a concentration of about <NUM>×<NUM><NUM> atoms/cm<NUM>, although other P-type dopants can be used to other charge carrier concentrations to form the junction. When the P-type region <NUM> is formed, a junction is created between the P-type region <NUM> and the intrinsic layer <NUM>.

Step <NUM> can also include thermally driving and diffusing the doping element for the P-type region <NUM> into the intrinsic layer <NUM>. A rapid, high temperature, thermal processing or annealing process step can be used for thermal driving. The depth of the P-type region <NUM> and the size of the effective intrinsic region I<NUM> can be set by the high temperature thermal drive. In some cases, the thermal driving at step <NUM> is not relied upon, alone, to diffuse or drive the P-type region <NUM> to the full extent illustrated in <FIG>. In some cases, the thermal driving at steps <NUM> and <NUM> can also contribute to the diffusion of the P-type region <NUM> into the intrinsic layer <NUM>, at least in part, as described below.

Alternatively, to form a NIP diode structure, step <NUM> can include implanting an N-type region into the top of the intrinsic layer <NUM>. The N-type region can be formed by doping the intrinsic layer <NUM> with Arsenic, for example, or another suitable N-type dopant, to a suitable concentration. Step <NUM> can also include thermally driving and diffusing the N-type dopant into the intrinsic layer <NUM>.

At step <NUM>, the process includes forming a second opening in the insulating layer <NUM>. Referring back to <FIG>, the opening of width W<NUM> can be formed at step <NUM>. The opening of width W<NUM> can be formed in the insulating layer <NUM> by etching a positive photoresist mask using wet chemistry, the application of plasma, or using another suitable technique. No other openings are formed at step <NUM>.

In some cases, the width W<NUM> can be the same as the width Wi. However, one consideration for the PIN diode structure <NUM> relates to the extent of lateral diffusion, Ld1, Ld2, and Ld3, that results during the high temperature thermal drives at steps <NUM>, <NUM>, and <NUM>. As the junction depths of the P-type regions <NUM>-<NUM> increase, the lateral diffusions Ld1, Ld2, and Ld3 and the overall size of the resulting anodes also increase. In order to control the capacitance and the high-frequency characteristics of each individual PIN diode, the physical dimensions of the openings formed at steps <NUM>, <NUM>, and <NUM> can vary as compared to each other, to control the amount of the lateral diffusion. For example, W<NUM> can be formed smaller than W<NUM>, and W<NUM> can be formed smaller than Wi.

Step <NUM> can also include thermally driving and diffusing the doping element for the P-type region <NUM> into the intrinsic layer <NUM>. A rapid thermal processing or annealing process step can be used for thermal driving. The depth of the P-type region <NUM> and the effective intrinsic region I<NUM> can be set by the high temperature thermal drive. In some cases, the thermal driving at step <NUM> is not relied upon, alone, to diffuse or drive the P-type region <NUM> to the extent illustrated in <FIG>. In some cases, the thermal driving at step <NUM> can also contribute to the diffusion of the P-type region <NUM> into the intrinsic layer <NUM>, at least in part, as described below.

Ideally, the thermal driving of the P-type region <NUM> at step <NUM> would not impact or change the extent of the diffusion of the P-type region <NUM> into the intrinsic layer <NUM>. However, if this thermal restriction cannot be met, then the thermal budget for the thermal drive at step <NUM> must incorporate or account for the thermal drive at step <NUM>. In other words, the thermal driving at step <NUM> can also contribute to the diffusion of the P-type region <NUM> further into the intrinsic layer <NUM> in some cases, and that diffusion can be accounted for when setting the thermal budget for the thermal drive at step <NUM>.

Alternatively, to form a NIP diode structure, step <NUM> can include implanting an N-type region into the top of the intrinsic layer <NUM>. The N-type region can be formed by doping the intrinsic layer <NUM> with Arsenic, for example, to a suitable concentration, although other N-type dopants can be used. Step <NUM> can also include thermally driving and diffusing the N-type dopant into the intrinsic layer <NUM>.

At step <NUM>, the process includes forming a third opening in the insulating layer <NUM>. Referring back to <FIG>, the opening of width W<NUM> can be formed at step <NUM>. The opening of width W<NUM> can be formed in the insulating layer <NUM> by etching a positive photoresist mask using wet chemistry, the application of plasma, or using another suitable technique. No other openings are formed at step <NUM>.

Step <NUM> can also include thermally driving and diffusing the doping element for the P-type region <NUM> into the intrinsic layer <NUM>. A rapid thermal processing or annealing process step can be used for thermal driving. The depth of the P-type region <NUM> and the effective intrinsic region I<NUM> can be set by the high temperature thermal drive. In some cases, the thermal driving at step <NUM> can also contribute to the diffusion of the P-type regions <NUM> and <NUM> into the intrinsic layer <NUM>, at least in part. Ideally, the thermal driving of the P-type region <NUM> at step <NUM> would not impact or change the extent of the diffusion of the P-type regions <NUM> and <NUM> into the intrinsic layer <NUM>. However, if this thermal restriction cannot be met, then the thermal budgets for the thermal drive at steps <NUM> and <NUM> must incorporate or account for the thermal drive at step <NUM>.

The process shown in <FIG> can also include process steps to form more windows and implant additional anodes in the PIN diode structure <NUM>. Additional process steps, including backside processing steps, can also be relied upon to form the cathode contact <NUM> and the anode contacts <NUM>, <NUM>, and <NUM>. Other steps can be relied upon to form components on the PIN diode structure <NUM>, as part of a larger integrated circuit device including diodes, capacitors, inductors, resistors, and layers of metal to electrically interconnect the components together to form switches, limiters, and other devices. Particularly, additional steps can be relied upon to form capacitors, inductors, resistors, and layers of metal to electrically interconnect the components together to form the monolithic, multi-throw switches described below with reference to <FIG>.

<FIG> and <FIG> encompass monolithic, vertical, planar semiconductor structures including a number of diodes having different intrinsic regions. The diodes have intrinsic regions of different thicknesses as compared to each other. The diodes can also be integrated with other components, such as capacitors, resistors, and inductors on the monolithic semiconductor structure in a monolithic circuit format. The monolithic format can provide a number of advantages over conventional techniques where discrete diodes are used, such as smaller size, reduced cost, and better and more controllable frequency response.

The concepts shown in <FIG> and <FIG> can be extended to other types and arrangements of diode devices. For example, the cathodes of the diodes are electrically connected together in <FIG>, although the diodes (and the cathodes of the diodes) can be separated from each other in other example embodiments described below. Additionally, topside contacts can be formed for both the anodes and the cathodes of the diodes, and the backside contacts can be isolated for each diode, or even omitted in some cases, as described below. The diodes can also be integrated with other components, such as capacitors, resistors, and inductors on the monolithic semiconductor structure in a monolithic circuit format. The monolithic format can provide a number of advantages over conventional techniques where discrete diodes are used, such as smaller size, reduced cost, and better and more controllable frequency response. According to aspects of the embodiments described below, when these diode devices of different intrinsic regions are used in the design of a monolithic, multi-throw switch, the switch exhibits improved reliability, ruggedness, RF performance, size, and cost as compared to the current discrete solutions.

Turning to other embodiments, <FIG> illustrates an example HMΠC silicon PIN diode structure <NUM> according to various embodiments described herein. As compared to the diode structure <NUM> shown in <FIG>, the diode structure <NUM> includes a highly insulative material, such as glass, to form a type of heterolithic microwave integrated circuit (HMIC). The PIN diode structure <NUM> is illustrated as a representative example in <FIG>. The shapes and sizes of the layers of the PIN diode structure <NUM> are not necessarily drawn to scale. The layers shown in <FIG> are not exhaustive, and the PIN diode structure <NUM> can include other layers and elements not separately illustrated. Additionally, the PIN diode structure <NUM> can be formed as part of a larger integrated circuit device in combination with other diodes, capacitors, inductors, resistors, and layers of metal to electrically interconnect the circuit elements together to form switches, limiters, and other devices. In other embodiments, one or more NIP diodes can also be formed to have a structure similar to the structure shown in <FIG>, by interchanging the P-type and N-type dopants.

The PIN diode structure <NUM> includes an N-type semiconductor substrate <NUM>, an intrinsic layer <NUM>, and a P-type region <NUM> formed in the intrinsic layer <NUM>. These layers can be similar in form and size as compared to the corresponding layers in the structure <NUM>, as shown in <FIG>. The N-type semiconductor substrate <NUM> forms a cathode and the P-type region <NUM> forms an anode of the PIN diode structure <NUM>. The P-type region <NUM> is formed through the opening of width W<NUM> in the insulating layer <NUM>. The P-type region <NUM> can be formed to a depth of between about <NUM>-<NUM> in the intrinsic layer <NUM>. With a <NUM> thick intrinsic layer <NUM>, for example, the size of the effective intrinsic region Isi can range between about <NUM>-<NUM>.

The PIN diode structure <NUM> includes a topside anode contact <NUM> formed over the P-type region <NUM>. The PIN diode structure <NUM> also includes a backside cathode contact <NUM> and topside cathode contacts 234A and 234B. Metallic sidewall conductors 240A and 240B extend from and electrically connect the backside cathode contact <NUM> to the topside cathode contacts 234A and 234B, and N+-type doped sidewalls 242A and 242B insulate the metallic sidewall conductors 240A and 240B from the intrinsic layer <NUM>.

As shown in <FIG>, the N+-type doped sidewalls 242A and 242B and the metallic sidewall conductors 240A and 240B are formed along sidewalls of the intrinsic layer <NUM> and the substrate <NUM>. The sidewalls of the intrinsic layer <NUM> and the substrate <NUM> are exposed through vertical etching of the intrinsic layer <NUM> and the substrate <NUM>, which forms the intrinsic layer <NUM> and the substrate <NUM> into a type of pedestal as shown. The etching process step can be performed, in one example, after the P-type region <NUM> is formed but before the topside anode contact <NUM> and cathode contacts 234A and 234B are formed. Either a wet chemical etching or a dry etching technique can be relied upon to expose the sidewalls, as deep cavities can be obtained with either technique.

With a substrate <NUM> of sufficient thickness, the etching process can etch down through the intrinsic layer <NUM> and into the substrate <NUM> to a total depth of about <NUM>-<NUM> from a topside of the PIN diode structure <NUM>. If wet chemical etching is relied upon, the sidewalls of the intrinsic layer <NUM> and the substrate <NUM> can extend down at an angle (e.g., at about <NUM> degrees) from the top surface of the PIN diode structure <NUM>. If dry etching is relied upon, the sidewalls of the intrinsic layer <NUM> and the substrate <NUM> can extend substantially straight down (e.g., at an angle of about <NUM> degrees down from the top surface of the PIN diode structure <NUM>).

The N+-type doped sidewalls 242A and 242B and the metallic sidewall conductors 240A and 240B can be formed after the etching. The N+-type doped sidewalls 242A and 242B can be formed by diffusing phosphorus, for example, or another N+-type dopant, into the exposed sidewalls of the intrinsic layer <NUM> and the substrate <NUM>. The metallic sidewall conductors 240A and 240B can then be formed by depositing metal, such as cobalt silicide (CoSi<NUM>), over the N+-type doped sidewalls 242A and 242B.

The insulator <NUM> can then be formed around the metallic sidewall conductors 240A and 240B and, if multiple diodes are formed, between the diodes. The application of the insulator <NUM> can start with a blanket deposition of about <NUM>Å of silicon nitride, for example, by low pressure chemical vapor deposition (LPCVD), followed by the deposit of about <NUM>Å of low temperature oxide (LTO). Those layers (although not shown in <FIG>) can encapsulate and protect the diodes during the application of the insulator <NUM>. The insulator <NUM> can then be fused into the area around the metallic sidewall conductors 240A and 240B, forming a conformal layer. The insulator <NUM> can be formed to a thickness of at least <NUM> higher than the depth of the vertical etch, to allow for a step of glass planarization.

The insulator <NUM> can be a borosilicate glass, for example, which exhibits a low dielectric constant, a low loss tangent, and a thermal coefficient of expansion similar to silicon for ruggedness over a broad temperature range, although other types of insulators can be relied upon. Although a single diode device is illustrated in <FIG>, the insulator <NUM> can be relied upon to separate a number of different, side-by-side diode devices as described below with reference to <FIG>, <FIG>, and <FIG>. The insulator <NUM> also permits a variety of different electrical connections among the diodes, by isolating them from each other.

After the insulator <NUM> is fused, a number of backside processing steps can be performed. A backside of the substrate <NUM> can be ground down until the insulator <NUM> is exposed. The backside cathode contact <NUM> can then be formed to extend over the metallic sidewall conductors 240A and 240B and the bottom side of the substrate <NUM>. When formed, the backside cathode contact <NUM> is electrically connected to the metallic sidewall conductors 240A and 240B. The backside cathode contact <NUM> is then electrically connected to the topside cathode contacts 234A and 234B via the metallic sidewall conductors 240A and 240B. Thus, with the inclusion of the metallic sidewall conductors 240A and 240B and the topside cathode contacts 234A and 234B, both anode and cathode contacts are available on top of the PIN diode structure <NUM>. As such, the PIN diode structure <NUM> is designed to facilitate shunt connections among diodes.

In another embodiment, <FIG> illustrates an example HNΠC silicon PIN diode structure <NUM>. As compared to the PIN diode structure <NUM> shown in <FIG>, the PIN diode structure <NUM> also includes an insulating material layer <NUM>, such as boron nitride or a thermal epoxy, among other suitable insulators, between the N-type semiconductor substrate <NUM> and the backside cathode contact <NUM>. The semiconductor substrate <NUM> can be etched from the backside of the semiconductor substrate <NUM> to a depth of about <NUM>, opening an area or void for the insulating material layer <NUM>. Thus, the diode structure <NUM> is particularly suitable for series connections among diodes. The cathode contact <NUM> may be optionally included in the embodiment shown in <FIG> for the purpose of mechanical die attachment. In some cases, the cathode contact <NUM> can be omitted.

Both the PIN diode structure <NUM> shown in <FIG> and the PIN structure <NUM> shown in <FIG> can be extended to NIP structures. Additionally, both the PIN diode structure <NUM> and the PIN structure <NUM> can be extended to include a number of diodes with different "I" region thicknesses, in a monolithic format, as described below.

<FIG> illustrates an example HMIC silicon PIN diode structure <NUM> according to various embodiments described herein. The PIN diode structure <NUM> is illustrated as a representative example in <FIG>. The shapes and sizes of the layers of the PIN diode structure <NUM> are not necessarily drawn to scale. The layers shown in <FIG> are not exhaustive, and the PIN diode structure <NUM> can include other layers and elements not separately illustrated. Additionally, the PIN diode structure <NUM> can be formed as part of a larger integrated circuit device in combination with other diodes, capacitors, inductors, resistors, and layers of metal to electrically interconnect the circuit elements together to form switches, limiters, and other devices. In other embodiments, one or more NIP diodes can also be formed to have a structure similar to the structure shown in <FIG>, by interchanging the P-type and N-type dopants.

The PIN diode structure <NUM> includes PIN diode devices <NUM>, <NUM>, and <NUM>, formed as first, second, and third pedestals. The PIN diode device <NUM> includes an N-type semiconductor substrate <NUM> and an intrinsic layer <NUM>, which are formed into a first pedestal by etching as described below. These layers are similar in vertical thickness as compared to the corresponding layers in the structure <NUM> shown in <FIG>. A P-type region <NUM> is formed in the intrinsic layer <NUM>. The N-type semiconductor substrate <NUM> forms a cathode and the P-type region <NUM> forms an anode of the PIN diode device <NUM>. The P-type region <NUM> is formed through the opening of width W<NUM> in the insulating layer <NUM>. The PIN diode devices <NUM> and <NUM> also include similar N-type semiconductor substrate and an intrinsic layers as shown, which are formed into first and second pedestals, respectively, by etching.

The PIN diode devices <NUM> and <NUM> are similar in form and size as compared to the PIN diode device <NUM>. However, the P-type region <NUM> is diffused deeper than the P-type region <NUM>, and the P-type region <NUM> is diffused deeper than the P-type region <NUM>. To obtain that form, a method of manufacturing the PIN diode structure <NUM> can follow the process steps illustrated in <FIG> and described above. Particularly, the P-type regions <NUM>-<NUM> can be formed sequentially, or in turn, in the intrinsic layer <NUM> according to the process steps shown in <FIG>. In that way, the P-type region <NUM> is diffused to the least extent into the intrinsic layer <NUM>, the P-type region <NUM> diffused to a greater extent into the intrinsic layer <NUM>, and the P-type region <NUM> is diffused the greatest extent into the intrinsic layer <NUM>. Thus, the effective intrinsic region I<NUM> under the P-type region <NUM> is larger than the effective intrinsic region I<NUM> under the P-type region <NUM>, and the effective intrinsic region I<NUM> is larger than the effective intrinsic region I<NUM> under the P-type region <NUM>. In one example, the effective intrinsic region I<NUM> can be between about <NUM>-<NUM>, the effective intrinsic region I<NUM> can be about <NUM>, and the effective intrinsic region I<NUM> can be about <NUM>, although other ranges are within the scope of the embodiments.

The extent of the lateral diffusions, Ld1, Ld2, and Ld3 of the P-type regions <NUM>-<NUM> can also vary as described above, with the lateral diffusion Ld1 being the smallest and the lateral diffusion Ld3 being the largest. In some cases, to control the capacitance and the high-frequency characteristics of the PIN diode devices <NUM>, <NUM>, and <NUM>, individually, the widths W<NUM>-W<NUM> of the openings formed in the insulating layer <NUM> can vary as compared to each other. For example, W<NUM> can be smaller than W<NUM>, and W<NUM> can be smaller than W<NUM>.

The PIN diode device <NUM> includes a topside anode contact <NUM> formed over the P-type region <NUM>. The PIN diode device <NUM> also includes a backside cathode contact <NUM> and topside cathode contacts 334A and 334B. Metallic sidewall conductors 340A and 340B extend from and electrically connect the backside cathode contact <NUM> to the topside cathode contacts 334A and 334B, and N+-type doped sidewalls 342A and 342B insulate the metallic sidewall conductors 340A and 340B from the intrinsic layer <NUM>. These features can be similar in form and size as compared to the corresponding features in the structure <NUM> shown in <FIG>. The PIN diode devices <NUM> and <NUM> can include similar features as shown in FIG.

The N+-type doped sidewalls 342A and 342B and the metallic sidewall conductors 340A and 340B are formed along sidewalls of the intrinsic layer <NUM> and the substrate <NUM> of the PIN diode device <NUM>. The sidewalls of the intrinsic layer <NUM> and the substrate <NUM> are exposed through vertical etching of the intrinsic layer <NUM> and the substrate <NUM> in a manner similar to that described above with reference to <FIG>, but among all of the PIN diode devices <NUM>, <NUM>, and <NUM>. The insulator <NUM> can then be formed around the metallic sidewall conductors 340A and 340B and the corresponding sidewall features of the PIN diode devices <NUM> and <NUM>.

The application of the insulator <NUM> can start with a blanket deposition of silicon nitride by LPCVD, for example, followed by a deposit of LTO. Those layers (although not shown in FIG. 5A) can encapsulate and protect the PIN diode devices <NUM>, <NUM>, and <NUM> during the application of the insulator <NUM>. The insulator <NUM> can then be fused into the etched areas around the PIN diode devices <NUM>, <NUM>, and <NUM>, forming a conformal layer. The insulator <NUM> can be formed to a thickness of at least <NUM> higher than the depth of the vertical etch, to allow for a step of glass planarization. The insulator <NUM> can be a borosilicate glass, for example, which exhibits a low dielectric constant, a low loss tangent, and a thermal coefficient of expansion similar to silicon for ruggedness over a broad temperature range, although other types of insulators can be relied upon.

After the insulator <NUM> is fused, a number of backside processing steps can be performed. A backside of the substrate <NUM> can be ground down until the insulator <NUM> is exposed. The backside cathode contact <NUM> can then be formed to extend over the metallic sidewall conductors 340A and 340B and the bottom side of the substrate <NUM>. When formed, the backside cathode contact <NUM> is electrically connected to the metallic sidewall conductors 340A and 340B. The backside cathode contact <NUM> is then electrically connected to the topside cathode contacts 334A and 334B via the metallic sidewall conductors 340A and 340B. The PIN diode structure <NUM> is designed to facilitate shunt connections among the PIN diode devices <NUM>, <NUM>, and <NUM>.

<FIG> illustrates another example HNΠC silicon PIN diode structure 400B according to various embodiments described herein. The PIN diode structure 400B includes PIN diode devices 360B, 362B, and 364B. The PIN diode structure 400B is similar to the PIN diode structure <NUM> shown in FIG. However, as compared to the PIN diode device <NUM> shown in <FIG>, the PIN diode device 360B in <FIG> also includes the insulating material layer <NUM>, which is similar to the insulating material layer <NUM> in <FIG>. The PIN diode device 362B and 364B also include similar insulating material layers. Thus, the PIN diode structure 400B is formed for series connections among the PIN diode devices 360B, 362B, and 364B. The cathode contacts, such as the cathode contact <NUM>, may be optionally included in the embodiment shown in <FIG> for the purpose of mechanical die attachment. In some cases, the cathode contacts can be omitted.

In other examples, a diode structure including a combination of the PIN diode devices <NUM>, <NUM>, and <NUM>, as shown in <FIG>, and the PIN diode devices 360B, 362B, and 364B, as shown in <FIG>, can be formed together on the same substrate. In that case, a number of PIN diodes can be arranged in both series and shunt configurations along with various components in a monolithic circuit format suitable for microwave circuit applications.

<FIG> illustrates an example HNΠC silicon PIN diode structure <NUM> according to various embodiments described herein. The PIN diode structure <NUM> is illustrated as a representative example in <FIG>. The shapes and sizes of the layers of the PIN diode structure <NUM> are not necessarily drawn to scale. The layers shown in <FIG> are not exhaustive, and the PIN diode structure <NUM> can include other layers and elements not separately illustrated. Additionally, the PIN diode structure <NUM> can be formed as part of a larger integrated circuit device in combination with other diodes, capacitors, inductors, resistors, and layers of metal to electrically interconnect the circuit elements together to form switches, limiters, and other devices. In other embodiments, one or more NIP diodes can also be formed to have a structure similar to the structure shown in <FIG>, by interchanging the P-type and N-type dopants.

The PIN diode structure <NUM> includes PIN diode devices <NUM>, <NUM>, and <NUM>. The PIN diode device <NUM> includes an N-type semiconductor substrate <NUM>, an intrinsic layer <NUM>, and a P-type region <NUM> formed in the intrinsic layer <NUM>. The N-type semiconductor substrate <NUM> forms a cathode and the P-type region <NUM> forms an anode of the PIN diode device <NUM>. The P-type region <NUM> is formed through the opening of width W<NUM> in the insulating layer <NUM>. The PIN diode device <NUM> includes a topside anode contact <NUM> formed over the P-type region <NUM>. The PIN diode device <NUM> also includes a backside cathode contact <NUM>.

The PIN diode devices <NUM> and <NUM> are similar in form and size as compared to the PIN diode device <NUM>. However, the P-type region <NUM> is diffused deeper than the P-type region <NUM>, and the P-type region <NUM> is diffused deeper than the P-type region <NUM>. To obtain that form, a method of manufacturing the PIN diode structure <NUM> can follow the process steps illustrated in <FIG> and described above. Particularly, the P-type regions <NUM>-<NUM> can be formed sequentially, or in turn, in the intrinsic layer <NUM> according to the process steps shown in <FIG>. In that way, the P-type anode region <NUM> is diffused to the least extent into the intrinsic layer <NUM>, the P-type region <NUM> diffused to a greater extent into the intrinsic layer <NUM>, and the P-type region <NUM> is diffused the greatest extent into the intrinsic layer <NUM>. Thus, the effective intrinsic region I<NUM> under the P-type region <NUM> is larger than the effective intrinsic region I<NUM> under the P-type region <NUM>, and the effective intrinsic region I<NUM> is larger than the effective intrinsic region I<NUM> under the P-type region <NUM>. In one example, the effective intrinsic region I<NUM> can be between about <NUM>-<NUM>, the effective intrinsic region I<NUM> can be about <NUM>, and the effective intrinsic region I<NUM> can be about <NUM>, although other ranges are within the scope of the embodiments.

Sidewall insulators <NUM> can also be formed along the sidewalls of the intrinsic layer <NUM> and the substrate <NUM> of the PIN diode device <NUM>. The sidewall insulators <NUM> can include a passivating dielectric or oxide layer. To form the sidewall insulators <NUM>, the sidewalls of the intrinsic layer <NUM> and the substrate <NUM> are exposed through vertical etching in a manner similar to that described above with reference to <FIG>, but among all of the PIN diode devices <NUM>, <NUM>, and <NUM>. The sidewall insulators <NUM> can then be formed on the sidewalls of the PIN diode device <NUM> and the corresponding sidewalls of the PIN diode devices <NUM> and <NUM>, to ensure there are no vertical leakage paths between the anodes and the cathodes in those devices.

The insulator <NUM> can then be fused among the PIN diode devices <NUM>, <NUM>, and <NUM> in a manner similar to that described above. The application of the insulator <NUM> can start with a blanket deposition of silicon nitride by LPCVD, for example, followed by a deposit of LTO. Those layers (although not shown in <FIG>) can encapsulate and protect the PIN diode devices <NUM>, <NUM>, and <NUM> during the application of the insulator <NUM>. The insulator <NUM> can then be fused into the etched areas around the PIN diode devices <NUM>, <NUM>, and <NUM>, forming a conformal layer. The insulator <NUM> can be formed to a thickness of at least <NUM> higher than the depth of the vertical etch, to allow for a step of glass planarization. The insulator <NUM> can be a borosilicate glass, for example, which exhibits a low dielectric constant, a low loss tangent, and a thermal coefficient of expansion similar to silicon for ruggedness over a broad temperature range, although other types of insulators can be relied upon.

After the insulator <NUM> is fused, a number of backside processing steps can be performed. A backside of the substrate <NUM> can be ground down until the insulator <NUM> is exposed. The backside cathode contact <NUM> can then be formed to extend over the bottom side of the substrate <NUM>. In some cases, rather than forming a separate backside cathode contact for each of the PIN diode devices <NUM>, <NUM>, and <NUM> as shown in <FIG>, a single backside cathode contact can be formed to extend across the N-type semiconductor substrates of all the PIN diode devices <NUM>, <NUM>, and <NUM>. The PIN diode structure <NUM> is designed to facilitate shunt connections among the PIN diode devices <NUM>, <NUM>, and <NUM>.

Because no topside cathode returns are needed for shunt configurations of PIN diodes, the approach shown in <FIG> can be relied upon to control the capacitance of the individual PIN diode devices <NUM>, <NUM>, and <NUM>. In <FIG>, the etching process is used to determine the physical dimensions of the P-type regions <NUM>, <NUM>, and <NUM>, independent of the junction depths of the anodes and the sizes of the windows W<NUM>-W<NUM> in the insulating layer <NUM>. Thus, the concerns regarding the extent of the lateral diffusions, Ld1, Ld2, and Ld3 in the other embodiments can be controlled according to the approach shown in <FIG>. In other words, the etching process is used to determine the physical dimensions of the P-type regions <NUM>, <NUM>, and <NUM>, to control the capacitance and the high-frequency characteristics of each individual PIN diode.

The diode structures and methods described above can be used to fabricate a wide variety of useful integrated circuits. For example, the diodes described above can be integrated with various components in a monolithic circuit format suitable for microwave circuit applications. The diodes can be integrated with capacitors, resistors, and inductors formed on the monolithic semiconductor structure. The monolithic format can provide a number of advantages over conventional techniques where discrete diodes are used, such as smaller size, reduced cost, and better and more controllable frequency response. According to aspects of the embodiments described below, when diodes of different intrinsic regions are used in the design of a monolithic multi-throw switch, the switch exhibits improved reliability, ruggedness, RF performance, size, and cost as compared to the current discrete solutions.

<FIG> illustrates an example series-connected SPDT switch <NUM> according to various embodiments described herein. The switch <NUM> is illustrated as a representative example for discussion of the advantages of using a monolithic structure of diodes having different intrinsic regions in the design of a monolithic switch. Other arrangements of series-connected PIN diode switches with additional ports (e.g., series-connected SP3T, SP4T, etc. switches) are within the scope of the embodiments.

As shown in <FIG>, the switch <NUM> includes an RF common port, a first RF port, a second RF port, a first bias input node, and a second bias input node. In operation, the switch <NUM> can either "pass" or "stop" RF signals between the RF common and the first RF port and the second RF port. Particularly, the switch <NUM> can either pass or stop an RF signal between the RF common and the first RF port based on a voltage bias applied at the first bias input. The switch <NUM> can also pass or stop an RF signal between the RF common and the second RF port based on a voltage bias applied at the second bias input.

The switch <NUM> includes a capacitor <NUM>, a PIN diode <NUM>, and a capacitor <NUM> electrically coupled or connected in series between the RF common and the first RF port. Thus, the PIN diode <NUM> is electrically coupled to a node between the RF common and the first RF port. The switch <NUM> also includes a capacitor <NUM>, a PIN diode <NUM>, and a capacitor <NUM> connected in series between the RF common and the second RF port. Thus, the PIN diode <NUM> is electrically coupled to a node between the RF common port and the second RF port. The switch <NUM> includes an RF choke <NUM> or inductor that is connected at a node between the capacitor <NUM> and the PIN diode <NUM> at one and connected to ground at another end. The switch <NUM> also includes an RF choke <NUM> or inductor that is connected at a node between the capacitor <NUM> and the PIN diode <NUM> at one and connected to ground at another end. The switch <NUM> also includes a first bias network, including a capacitor <NUM> connected from the first bias input to ground and an RF choke <NUM> connected from the first bias input to an anode of the PIN diode <NUM>. The switch <NUM> also includes a second bias network, including a capacitor <NUM> connected from the second bias input to ground and an RF choke <NUM> connected from the second bias input to an anode of the PIN diode <NUM>.

In the switch <NUM>, each of the PIN diodes <NUM> and <NUM> can be placed into a "pass" condition when it is forward biased. The PIN diode <NUM> can be forward biased by application of a sufficient voltage at the first bias input. The PIN diode <NUM> can be forward biased by application of a sufficient voltage at the second bias input. When forward biased, each of the PIN diodes <NUM> and <NUM> presents a respective low forward resistance, Rs, between the RF common and one of the RF ports. For the "stop" condition, the PIN diodes <NUM> and <NUM> can be zero or reverse biased. When reverse biased, each of the PIN diodes <NUM> and <NUM> presents a high impedance between the RF input and the RF ports.

In series-connected switches, such as the switch <NUM>, insertion loss and power dissipation are functions of the forward series on-resistance, Rs, of the PIN diodes <NUM> and <NUM>. The maximum isolation obtainable is primarily a function of the capacitance, Xc, of the respective PIN diodes <NUM> and <NUM>. In a series-connected SPST switch, the insertion loss, IL, and the isolation, ISO, are given (in dB) by: <MAT> <MAT> For multi-throw series-connected switches, the insertion loss is slightly higher due to mismatch caused by the capacitance of any PIN diodes in "stop" arms. Also, for multi-throw switches, <NUM> dB can be added to the isolation figure to account for the <NUM> percent voltage reduction across the "stop" arm due to the characteristic impedance of the termination.

Among other operating characteristics, the forward resistances and capacitances of the respective PIN diodes <NUM> and <NUM> are functions of the structural characteristics of the diodes, including the "I" region thicknesses. Using the techniques and structures described herein, the switch <NUM> can be realized monolithically, in a single package, using a combination of one or more PIN diodes with different "I" region thicknesses. The PIN diodes <NUM> and <NUM> can be embodied using a combination of the PIN diodes of the structures shown in <FIG>, <FIG>, <FIG>, or <FIG>, for example, with PIN diodes of different "I" region thicknesses. For example, if the switch <NUM> is functioning in a dedicated transmit/receive mode, the transmit PIN diode <NUM> can have a thicker "I" region than the receive PIN diode <NUM> to maximize power handling for the transmit arm and maximize receive sensitivity/insertion loss in the receive arm.

While <FIG> illustrates an SPDT configuration of the series-connected switch <NUM>, the concepts described herein can be extended to have more ports (e.g., up to SP8T or more) and more inputs (e.g., DPDT, etc.). The configurations are also not restricted to one series-connected diode per arm. A SPDT switch can include two, three, or more series-connected PIN diodes in each arm, and each of the series-connected PIN diodes in any given arm can have the same or different "I" region thicknesses. These configurations can also be realized monolithically, in a single package. Using the concepts described herein, a monolithic, multi-throw series-connected switch with a combination of PIN diodes having different "I" region thicknesses can be formed.

A process of fabricating the switch <NUM> can include one or more of the steps described above with reference to <FIG> to form the PIN diodes <NUM> and <NUM>. Additional process steps can be relied upon to form the capacitors, inductors, transmission lines, bias networks, and other elements shown in <FIG>. The additional circuit elements can be formed over the intrinsic layer of the PIN diodes <NUM> and <NUM>. Additional process steps can also be relied upon to form the metal layers and realize the electrical connections between the circuit elements shown in <FIG>. For example, the steps can include forming at least one metal layer over the intrinsic layer of the PIN diodes <NUM> and <NUM> to electrically couple the first PIN diode to a node between the common RF port and the first port of the switch <NUM> and to electrically couple the second PIN diode to a node between the RF common port and the second port of the switch <NUM>.

<FIG> illustrates an example shunt-connected SPDT switch <NUM> according to various embodiments described herein. The switch <NUM> is illustrated as a representative example for discussion of the advantages of using a monolithic structure of diodes having different intrinsic regions in the design of a monolithic switch. Other arrangements of shunt-connected PIN diode switches with additional ports are within the scope of the embodiments.

As shown in <FIG>, the switch <NUM> includes an RF common, a first RF port, a second RF port, a first bias input, and a second bias input. In operation, the switch <NUM> can either "pass" or "stop" RF signals between the RF common and the first RF port and the second RF port. Particularly, the switch <NUM> can either pass or stop an RF signal between the RF common and the first RF port based on a voltage bias applied at the first bias input. The switch <NUM> can also pass or stop an RF signal between the RF common and the second RF port based on a voltage bias applied at the second bias input.

The switch <NUM> includes a capacitor <NUM>, a transmission line <NUM>, and a capacitor <NUM> electrically coupled or connected in series between the RF common and the first RF port. The transmission line <NUM> can be a quarter-wavelength (i.e., λ/<NUM>) transmission line in one example, and the capacitors <NUM> and <NUM> can be electrically coupled at any suitable position along the transmission line <NUM>. The switch <NUM> also includes a capacitor <NUM>, a transmission line <NUM>, and a capacitor <NUM> electrically coupled or connected in series between the RF common and the second RF port. The transmission line <NUM> can be a quarter-wavelength (i.e., λ/<NUM>) transmission line in one example, and the capacitors <NUM> and <NUM> can be electrically coupled at any suitable position along the transmission line <NUM>.

The switch <NUM> also includes a PIN diode <NUM> with an anode connected between the capacitor <NUM> and the capacitor <NUM> and a cathode connected to ground. Thus, the PIN diode <NUM> is electrically coupled to a node between the RF common port and the first RF port. The switch <NUM> also includes a PIN diode <NUM> with an anode connected between the capacitor <NUM> and the capacitor <NUM> and a cathode connected to ground. Thus, the PIN diode <NUM> is electrically coupled to a node between the RF common port and the second RF port. The switch <NUM> also includes a first bias network, including a capacitor <NUM> connected from the first bias input to ground and an RF choke <NUM> connected from the first bias input to an anode of the PIN diode <NUM>. The switch <NUM> also includes a second bias network, including a capacitor <NUM> connected from the second bias input to ground and an RF choke <NUM> connected from the second bias input to an anode of the PIN diode <NUM>.

In the switch <NUM>, each of the PIN diodes <NUM> and <NUM> can be placed into a "pass" condition when it is forward biased. For the "stop" condition, the PIN diode <NUM> can be forward biased by application of a sufficient voltage at the first bias input. The PIN diode <NUM> can be forward biased by application of a sufficient voltage at the second bias input. When forward biased, each of the PIN diodes <NUM> and <NUM> presents a respective low forward resistance, Rs, to ground. For the "pass" condition, the PIN diodes <NUM> and <NUM> can be zero or reverse biased. When reverse biased, each of the PIN diodes <NUM> and <NUM> presents a high impedance to ground.

Shunt-connected switches offer high isolation for many applications. Because the PIN diodes <NUM> and <NUM> can be coupled to a heat sink at one electrode, the switch <NUM> can handle relatively more RF power than the switch <NUM> in many cases. In shunt-connected switch designs, such as the switch <NUM>, isolation and power dissipation are functions of the forward resistance, Rs, of the PIN diodes <NUM> and <NUM>. The insertion loss is primarily dependent on the capacitance, Xc, of the respective PIN diodes <NUM> and <NUM>. In a shunt-connected SPST switch, the insertion loss, IL, and the isolation, ISO, are given (in dB) by: <MAT> <MAT> For multi-throw shunt-connected switches (e.g., the SPDT switch <NUM> shown in <FIG>, and greater than double throw), <NUM> dB can be added to the isolation figure.

Among other operating characteristics, the forward resistances and capacitances of each of the PIN diodes <NUM> and <NUM> are functions of the structural characteristics of the PIN diodes <NUM> and <NUM>, including the "I" region thicknesses. Using the techniques described herein, the switch <NUM> can be realized monolithically, in a single package, using a combination of one or more PIN diodes with different structural characteristics and "I" region thicknesses. The PIN diodes <NUM> and <NUM> can be embodied using a hybrid combination of the PIN diodes shown in <FIG>, <FIG>, <FIG>, or <FIG>, with PIN diodes of different "I" region thicknesses. For example, the PIN diode <NUM> can have a thicker "I" region than the PIN diode <NUM>.

While <FIG> illustrates a SPDT configuration of the shunt-connected switch <NUM>, the concepts described herein can be extended to have more ports (e.g., up to SP8T or more) and more inputs (e.g., DPDT, etc.). The configurations are also not restricted to one shunt-connected diode per arm. A SPDT switch can include two, three, or more shunt-connected PIN diodes in each arm.

A process of fabricating the switch <NUM> can include one or more of the steps described above with reference to <FIG> to form the PIN diodes <NUM> and <NUM>. Additional process steps can be relied upon to form the capacitors, inductors, transmission lines, bias networks, and other elements shown in <FIG>. The additional circuit elements can be formed over the intrinsic layer of the PIN diodes <NUM> and <NUM>. Additional process steps can also be relied upon to form the metal layers and realize the electrical connections between the circuit elements shown in <FIG>. For example, the steps can include forming at least one metal layer over the intrinsic layer of the PIN diodes <NUM> and <NUM> to electrically couple the first PIN diode to a node between the common RF port and the first port of the switch <NUM> and to electrically couple the second PIN diode to a node between the common RF port and the second port of the switch <NUM>.

<FIG> illustrates an example series-shunt-connected SPDT switch according to various embodiments described herein. The switch <NUM> is illustrated as a representative example for discussion of the advantages of using a monolithic structure of diodes having different intrinsic regions in the design of a monolithic switch. Other arrangements of series-connected PIN diode switches with additional ports (e.g., series-connected SP3T, SP4T, etc. switches) are within the scope of the embodiments.

The switch <NUM> includes a capacitor <NUM>, a PIN diode <NUM>, and a capacitor <NUM> electrically coupled or connected in series between the RF common and the first RF port. The switch <NUM> also includes a capacitor <NUM>, a PIN diode <NUM>, and a capacitor <NUM> connected in series between the RF common and the second RF port. The switch <NUM> also includes a PIN diode <NUM> with an anode connected between the PIN diode <NUM> and the capacitor <NUM> and a cathode connected to ground. The switch <NUM> also includes a PIN diode <NUM> with an anode connected between the PIN diode <NUM> and the capacitor <NUM> and a cathode connected to ground. The switch <NUM> also includes a first bias network, including a capacitor <NUM> connected from the first bias input to ground and an RF choke <NUM> connected from the first bias input to a cathode of the PIN diode <NUM>. The switch <NUM> also includes a second bias network, including a capacitor <NUM> connected from the second bias input to ground and an RF choke <NUM> connected from the second bias input to a cathode of the PIN diode <NUM>.

In the switch <NUM>, the PIN diodes <NUM> and <NUM> can be placed into a "pass" condition when forward biased and a "stop" condition when reverse biased based on the voltage at the second bias input. Similarly, the PIN diodes <NUM> and <NUM> can be placed into a "pass" condition when forward biased and a "stop" condition when reverse biased based on the voltage at the second bias input. When forward biased, each of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM> presents a respective low forward resistance, Rs. When reverse biased, each of the each of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM> presents a high impedance.

It can be difficult to achieve sufficient isolation using a single PIN diode, whether series- or shunt-connected, in an arm of a switch. To overcome this limitation, there are switch designs that employ combinations of series and shunt diodes (e.g., series-shunt-connected or compound switches) and switches that employ resonant structures (e.g., tuned switches) for improved isolation. The series-shunt-connected configuration shown in <FIG> is common for this purpose. In the insertion loss state for a compound switch, the series diode is forward biased and the shunt diode is at zero or reverse bias. The reverse is true for the isolation state. This adds some complexity to the bias circuitry in comparison to simple series- or shunt-connected switches.

In series-shunt-connected switches, such as the switch <NUM>, the insertion loss, the power dissipation, and the maximum isolation are functions of both the forward resistance, Rs, and the capacitance, Xc, of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM>. The power dissipation or loss is mostly limited by and a function of the forward resistances through the series PIN diodes <NUM> and <NUM>. In a series-shunt-connected SPST switch, the insertion loss, IL, and the isolation, ISO, are given (in dB) by: <MAT> <MAT>.

Among other operating characteristics, the forward resistances and capacitances of each of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM> are functions of the structural characteristics of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM>, including the "I" region thicknesses. The switch <NUM> could be implemented with each of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM> having the same the "I" region thickness. In that case, the arms of the switch <NUM> would be symmetric, and the transmit and receive arms would be treated the same. It would have been necessary in a conventional monolithic design for each of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM> to have the same the "I" region thickness. However, a compromise must be made between the transmit and receive functions in a symmetric switch because of the single "I" region thickness. Using the techniques described herein, the switch <NUM> can be realized monolithically, in a single package, using a combination of one or more PIN diodes with different structural characteristics and "I" region thicknesses. The PIN diodes <NUM>, <NUM>, <NUM>, and <NUM> can be embodied using a hybrid combination of the PIN diodes shown in <FIG>, <FIG>, <FIG>, or <FIG>, with PIN diodes of different "I" region thicknesses. Once a specific arm in the switch <NUM> is chosen for the transmit or receive function, the "I" region thickness in the respective arm can be optimized for radio frequency performance, by tailoring the "I" region thickness for junction capacitance, anode area, reverse breakdown, series resistance.

As presented in equations (<NUM>)-(<NUM>), the series on-resistance, Rs, and the off-state capacitance, Xc, leads to basic equations for the insertion loss IL and isolation ISO of each switch topology, with the assumption that RS and XC of the series and shunt PIN diodes in each arm are identical. Equations (<NUM>)-(<NUM>) are first-order approximations and do not include interconnect parasitics, nor the effect of adding multiple arms to the switch. In practical designs, these secondary effects must be accounted for, and the advantage of quarter wave transformations in the case of shunt diode designs and impedance matching can be accounted for in all cases.

Examining the effect of the on-resistance characteristic of a typical active element, it can be demonstrated by equation (<NUM>) that for a series-only configured switch, the insertion loss IL is dependent entirely on the value of the on-resistance and the off-state total output capacitance is essentially decoupled from the switch insertion loss. For a series-shunt configured switch, the output capacitance does play a role, but the examination of equation (<NUM>) reveals that it is also dominated by the device on-state series resistance. As another way of viewing this series resistance dependence for series configured switches, the RF energy in the "on" arm is flowing through the active element. It can be seen from equations (<NUM>)-(<NUM>) that the insertion loss and, in direct proportion, the RF power handling is limited by the losses and dissipation in this series element.

A similar evaluation can be made shunt-only configured switches, as shown in equation (<NUM>). In this case the RF energy in the "on" arm is not flowing through the active device, but instead is being transferred from input to output through low loss, high "Q" transmission lines. In this case the RF dissipation is primarily due to I<NUM>R losses in the metallic conductors with the active blocking element being DC reverse biased in an off-state. The insertion loss in this shunt configuration, as expressed in equation (<NUM>), is limited only by the output shunt capacitance. For multi-throw switch configurations, the loss in the quarter wave transformers needs to provide isolation between switch arms, and the IL will result in low values even for active device structures that have significant series on-resistance. A difficulty in this shunt-only switch configuration, as can be seen in equation (<NUM>), is that a high on-state resistance will result in degraded isolation ISO. If the forward on resistance is too high, the isolation in each switch arm may be so poor as to render the switch unusable.

Using these simplified assumptions in equations (<NUM>)-(<NUM>), it can be seen that for series-only and shunt-only switch optimizations of the series on-resistance and the off-state capacitance can dramatically alter high frequency switch performance. For existing PIN diode monolithic switch designs which can only employ a single "I" region thickness, this optimization of the individual active elements can only be accomplished by modifying the active area (anode) of the PIN structure. The embodiments described herein change that paradigm by allowing each discrete PIN diode to be individually adjusted by allowing the specific "I" region thickness to be modified.

In the series-shunt configuration, it is often found that the high frequency switch performance is improved by having the series and shunt elements in each arm having differing areas thus modifying the series resistance and the off-state capacitance. With existing monolithic designs an area change is the only way to affect these changes. The embodiments described herein, with various PIN diodes having multi-thickness "I" regions, provides an additional optimization factor for monolithic solutions.

While <FIG> illustrates a SPDT configuration of the switch <NUM>, the concepts described herein can be extended to have fewer ports (e.g., a series-shunt-connected SPST switch) or more ports (e.g., up to SP8T or more). The concepts can also be extended to have more inputs (e.g., DPDT, etc.). The configurations are also not restricted to one pair of series-shunt-connected diodes per arm. A series-shunt-connected switch can include two, three, or more series-shunt-connected PIN diodes in each arm.

A process of fabricating the switch <NUM> can include one or more of the steps described above with reference to <FIG> to form the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM>. Additional process steps can be relied upon to form the capacitors, inductors, transmission lines, bias networks, and other elements shown in <FIG>. The additional circuit elements can be formed over the intrinsic layer of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM>. Additional process steps can also be relied upon to form the metal layers and realize the electrical connections between the circuit elements shown in <FIG>.

<FIG> illustrates an example series-connected TEE SP3T switch <NUM> according to various embodiments described herein. The switch <NUM> is illustrated as a representative example for discussion of the advantages of using a monolithic structure of diodes having different intrinsic regions in the design of a monolithic switch. Other arrangements with additional ports (e.g., series-connected TEE SP4T, etc. switches) are within the scope of the embodiments.

As shown in <FIG>, the switch <NUM> includes an RF common, a first RF port, a second RF port, a third RF port, a first bias input, a second bias input, and a third bias input. The switch <NUM> a first PIN diode <NUM> in series between the RF common and the first RF port, a second PIN diode <NUM> in series between the RF common and the second RF port, and a third PIN diode <NUM> in series between the RF common and the third RF port. The switch <NUM> also includes bias networks for the first, second, and third, bias inputs as shown in <FIG>. In operation, the switch <NUM> can either "pass" or "stop" RF signals between the RF common and the RF ports based on voltage biases applied at the first, second, and third bias inputs.

Among other operating characteristics, the forward resistances and capacitances of each of the PIN diodes <NUM>, <NUM>, and <NUM> are functions of the structural characteristics of the PIN diodes <NUM>, <NUM>, and <NUM>, including the "I" region thicknesses. The switch <NUM> could be implemented with each of the PIN diodes <NUM>, <NUM>, and <NUM> having the same the "I" region thickness. In that case, the arms of the switch <NUM> would be symmetric, and the transmit and receive arms would be treated the same. It would have been necessary in a conventional monolithic design for each of the PIN diodes <NUM>, <NUM>, and <NUM> to have the same the "I" region thickness. However, a compromise must be made between the transmit and receive functions in a symmetric switch because of the single "I" region thickness. Using the techniques described herein, the switch <NUM> can be realized monolithically, in a single package, using a combination of one or more PIN diodes with different structural characteristics and "I" region thicknesses. Once a specific arm in the switch <NUM> is chosen for the transmit or receive function, the "I" region thickness in the respective arm can be optimized for radio frequency performance, by tailoring the "I" region thickness for junction capacitance, anode area, reverse breakdown, series resistance.

The PIN diodes <NUM>, <NUM>, and <NUM> can be embodied using a hybrid combination of the PIN diodes shown in <FIG>, <FIG>, <FIG>, or <FIG>, with PIN diodes of different "I" region thicknesses. For example, the PIN diode <NUM> can have a thicker "I" region than the PIN diode <NUM>, and the PIN diode <NUM> can have a thicker "I" region than the PIN diode <NUM>.

A process of fabricating the switch <NUM> can include one or more of the steps described above with reference to <FIG> to form the PIN diodes <NUM>, <NUM>, and <NUM>. Additional process steps can be relied upon to form the capacitors, inductors, transmission lines, bias networks, and other elements shown in <FIG>. The additional circuit elements can be formed over the intrinsic layer of the PIN diodes <NUM>, <NUM>, and <NUM>. Additional process steps can also be relied upon to form the metal layers and realize the electrical connections between the circuit elements shown in <FIG>.

<FIG> illustrates an example series-shunt-connected ring switch <NUM> according to various embodiments described herein. As shown in <FIG>, the switch <NUM> includes three RF common ports and three bias inputs. In operation, the switch <NUM> can either "pass" or "stop" RF signals between the RF common ports based on voltage biases applied at the bias inputs.

In the switch <NUM>, the node "A" can be electrically coupled to the node "A'," for a ring switch having three arms. However, the switch <NUM> can be extended to include any number of arms in the ring configuration. Among other components, one arm of the switch <NUM> includes a series-shunt-connection among PIN diodes <NUM> and <NUM> and a series-shunt-connection among PIN diodes <NUM> and <NUM>. When forward biased, each of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM> presents a respective low forward resistance, Rs. When reverse biased, each of the each of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM> presents a high impedance.

For series-shunt-connected switches, such as in switch <NUM>, the insertion loss, the power dissipation, and the maximum isolation are functions of both the forward resistance, Rs, and the capacitance, Xc, of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM>. The power dissipation or loss is mostly limited by and a function of the forward resistances through the series PIN diodes <NUM>, <NUM>, <NUM>, and <NUM>. Among other operating characteristics, the forward resistances and capacitances of each of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM> are functions of the structural characteristics of the PIN diodes <NUM>, <NUM>, <NUM>, and <NUM>, including the "I" region thicknesses. Using the techniques described herein, the switch <NUM> can be realized monolithically, in a single package, using a combination of one or more PIN diodes with different structural characteristics and "I" region thicknesses. The PIN diodes <NUM>, <NUM>, <NUM>, and <NUM> can be embodied using a hybrid combination of the PIN diodes shown in <FIG>, <FIG>, <FIG>, or <FIG>, with PIN diodes of different "I" region thicknesses.

The switches shown in <FIG> are provided as examples, and other switch topologies are within the scope of the embodiments. The structures and methods described herein can be used to fabricate a wide variety of useful integrated circuits, such as switches, limiters, and other devices. Particularly, combinations of the PIN and NIP diodes described above, with various "I" region thicknesses, can be integrated with various components (e.g., blocking capacitors, transmission lines, RF chokes, resistors, etc.) in a monolithic circuit format suitable for switches, limiters, and other devices in microwave circuit applications.

Claim 1:
A monolithic multi-throw diode switch (<NUM> ; <NUM> ; <NUM> ; <NUM> ; <NUM>), comprising:
a common port, a first port, and a second port;
a first PIN diode (<NUM>) comprising a first P-type region (<NUM>) formed to a first depth into an intrinsic layer (<NUM>) such that the first PIN diode comprises a first effective intrinsic region of a first thickness, the first PIN diode being electrically coupled to a node between the common port and the first port;
a second PIN diode (<NUM>) comprising a second P-type region (<NUM>) formed to a second depth into the intrinsic layer such that the second PIN diode comprises a second effective intrinsic region of a second thickness, the second PIN diode being electrically coupled to a node between the common port and the second port;
a first bias network for bias control of the first PIN diode; and
a second bias network for bias control of the second PIN diode,
wherein the first thickness is different than the second thickness.