Patent Description:
Quantum computing is a relatively new computing method that takes advantage of quantum effects, such as superposition of basis states and entanglement to perform certain computations more efficiently than a classical digital computer. In contrast to a digital computer, which stores and manipulates information in the form of bits (e.g., a "<NUM>" or "<NUM>"), quantum computing systems can manipulate information using qubits. A qubit can refer to a quantum device that enables the superposition of multiple states (e.g., data in both the "<NUM>" and "<NUM>" state) and/or to the superposition of data, itself, in the multiple states. In accordance with conventional terminology, the superposition of a "<NUM>" and "<NUM>" state in a quantum system may be represented, e.g., as α | <NUM>> + β | <NUM>>. The "<NUM>" and "<NUM>" states of a digital computer are analogous to the | <NUM>> and | <NUM>> basis states, respectively of a qubit. The value | α |<NUM> represents the probability that a qubit is in | <NUM>> state, whereas the value | β |<NUM> represents the probability that a qubit is in the | <NUM>> basis state.

Document <CIT> discloses a device according to the preamble of independent claim <NUM>, particularly a superconducting device with at least one enclosure. Some embodiments are directed to a device including multiple substrates comprising one or more troughs. The substrates are disposed such that the one or more troughs form at least one enclosure. At least one superconducting layer covers at least a portion of the at least one enclosure. Other embodiments are directed to a method for manufacturing a superconducting device. The method includes acts of forming at least one trough in at least a first substrate; covering at least a portion of the first substrate with a superconducting material; covering at least a portion of a second substrate with the superconducting material; and bonding the first substrate and the second substrate to form at least one enclosure comprising the at least one trough and the superconducting material.

Various embodiments and implementations can include one or more of the following advantages. For example, in some implementations, the devices and method allow a reduction in energy loss and dissipation in quantum circuit elements caused by deposited dielectric materials.

For the purposes of this disclosure, a superconductor (alternatively, superconducting) material may be understood as a material that exhibits superconducting properties at or below a superconducting critical temperature. Examples of superconductor material include aluminum (superconducting critical temperature of, e.g., <NUM>), niobium (superconducting critical temperature of, e.g., <NUM>) and titanium nitride (superconducting critical temperature of, e.g., <NUM>).

The details of one or more implementations of the invention are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description, the drawings, and the claims.

Quantum computing entails coherently processing quantum information stored in the quantum bits (qubits) of a quantum computer. In certain types of quantum computing processors, such as quantum annealers, the qubits of the quantum processor are coupled together in a controllable manner such that the quantum state of each qubit affects the corresponding quantum states of the other qubits to which it is coupled. Superconducting quantum computing is a promising implementation of quantum computing technology in which quantum circuit elements are formed, in part, from superconductor materials. Superconducting quantum computers are typically multilevel systems, in which only the first two levels are used as the computational basis. Such quantum computers are to be operated at very low temperatures so that superconductivity can be achieved and so that thermal fluctuations do not cause transitions between energy levels. Additionally, it may be preferable that the quantum circuit elements are operated with low energy loss/dissipation to avoid quantum decoherence.

Superconducting quantum circuit elements (also referred to as quantum circuit devices), such as qubits, inductance based photon detectors, and resonators, among others, rely on low loss reactive microwave components to achieve a high quality factor, Q. In some implementations, fabrication of complex quantum circuit structures (or classical circuit structures) may require using one or more layers of deposited dielectrics in addition to the superconductor material. However, deposited dielectrics, which may be amorphous or polycrystalline solids, typically have high loss compared to non-deposited dielectrics, such as single crystal silicon substrates (in some cases by many orders of magnitude). Such deposited dielectrics may not be suitable for high coherence/low decoherence superconducting quantum circuits. These so-called "lossy" deposited dielectrics may dominate dissipation in the system causing, e.g., qubit decoherence through field coupling, and thus limiting the performance of the quantum processor.

Accordingly, in some implementations, it may be useful to arrange complex circuit elements that have one or more layers of lossy dielectrics, relatively far away from the qubits, such as on a separate chip from the qubits. The chip (or chips) containing the qubits then may be stacked on the chip containing the complex quantum and/or classical circuit elements. However, even when the circuit elements having lossy dielectrics are arranged on a separate carrier chip, the circuit elements may lead to decoherence if they are too close to the qubits. For example, circuit elements having lossy dielectrics may be arranged on a surface of the carrier chip that faces the chip including the qubits, such that the distance between the circuit elements and the qubit carrying chip is limited to the thickness of the bond connections between the two chips. In some implementations, this can lead to lossy interactions between the circuit elements and the qubits, causing the qubits to decohere.

The present disclosure relates to reducing such loss in stacked quantum devices by arranging circuit elements having lossy dielectrics on a surface of the carrier chip facing away from chip containing the qubits (the "non-coherent side"). For instance, the circuit elements that would otherwise induce decoherence in nearby qubits may be placed on a reverse or backside of the carrier chip. Circuit elements that maintain high coherence and low loss may be arranged on the front side (the "coherent side") of the carrier wafer closer to the qubits of the qubit carrying chip. For example, circuits that maintain high coherence and low loss may be arranged within a single layer that is formed in direct contact with a surface of the carrier wafer.

<FIG> is a schematic that illustrates an example of a device <NUM> for reducing energy loss/dissipation in quantum processors, according to the present invention. The device <NUM> includes a first chip <NUM> including quantum circuit elements, such as qubits, joined (e.g., bonded) to a second chip <NUM>, also referred to as a carrier chip, including circuit elements for processing data obtained from the first chip <NUM> and/or for sending data to the first chip <NUM>. The second chip <NUM> includes a substrate <NUM> having first <NUM> and second <NUM> opposing surfaces, with the first surface <NUM> facing the first chip <NUM>. The second chip <NUM> includes a first layer <NUM> formed on the first surface <NUM>, in which the first layer <NUM> includes components and/or materials formed from a layer of superconducting metal that is in direct contact with the underlying substrate <NUM>. In implementations in which the substrate <NUM> is a crystalline dielectric, this provides a system that has low loss and high coherence, and is less likely to cause quantum circuit elements, such as qubits, on the first chip <NUM> to decohere. The second chip <NUM> also includes a second layer <NUM> formed on the second surface <NUM>, in which the second layer <NUM> includes components and/or materials that can cause relatively higher loss in quantum circuit elements than the materials/components of the first layer <NUM>. The first layer <NUM> and the second layer <NUM> are coupled (e.g., electrically connected) by a connector <NUM> that extends from the first surface <NUM> to the second surface <NUM> of the substrate <NUM>.

As explained herein, each of the first chip <NUM> and the second chip <NUM> includes one or more circuit elements for performing data processing operations. For example, in some implementations, the first chip <NUM> includes one or more quantum circuit elements for use in performing quantum processing operations. That is, the quantum circuit elements may be configured to make use of quantum-mechanical phenomena, such as superposition and entanglement, to perform operations on data in a non-deterministic manner. In contrast, classical circuit elements generally process data in a deterministic manner. In some implementations, the first chip <NUM> includes only quantum circuit elements, e.g., the first chip <NUM> does not include classical circuit elements.

Certain quantum circuit elements, such as qubits, may be configured to represent and operate on information in more than one state simultaneously. In some implementations, quantum circuit elements include circuit elements such as superconducting co-planar waveguides, quantum LC oscillators, flux qubits, charge qubits, superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC-SQUID), among others. The quantum circuit elements may include circuit elements formed, in part, from superconductor materials (e.g., aluminum, titanium nitride or niobium).

The quantum circuit elements of the first chip <NUM> may be formed on and/or within a substrate. The substrate of the first chip may be formed from, e.g., a low loss dielectric suitable for quantum circuit elements, such as a silicon or sapphire wafer. Other materials may be used for the substrate instead.

The second chip <NUM>, also referred to as a carrier chip, may include multiple quantum circuit elements as well. For example, quantum circuit elements formed on the second chip <NUM> may include superconductor co-planar waveguides, resonators, capacitors, transmission lines, ground planes, amplifiers, RF or DC superconducting quantum interference devices (SQUIDs), Josephson junctions, among other types of quantum circuit elements In some implementations, the quantum circuit elements on the first and/or second chips <NUM>, <NUM> may be arranged to form special purpose circuits, such as readout devices for the qubits or control devices for the qubits. For example, the coherent side of the second chip <NUM> may include a co-planar waveguide transmission line, a resonator and/or a single layer SQUID made from double angle evaporation. The non-coherent side may include, for example, microstrip transmission lines, complex multi-layer amplifier circuits, parallel plate capacitors, multi-layer wiring, and/or Josephson logic elements.

In some implementations, the second chip <NUM> may include classical circuit elements. The classical circuit elements also may be formed, in part, with superconductor materials to maintain uniform processing methods. Examples of classical circuit elements formed with superconductor materials include rapid single flux quantum (RSFQ) devices. RSFQ is a digital electronics technology that uses superconductor devices, namely Josephson junctions, to process digital signals. In RSFQ logic, information is stored in the form of magnetic flux quanta and transferred in the form of Single Flux Quantum (SFQ) voltage pulses. Josephson junctions are the active elements for RSFQ electronics, just as transistors are the active elements for semiconductor CMOS electronics. RSFQ is one family of superconductor or SFQ logic. Others include, e.g., Reciprocal Quantum Logic (RQL) and ERSFQ, which is an energy-efficient version of RSFQ that does not use bias resistors. Other examples of classical circuits include digital or analog CMOS devices. The classical circuit elements may be configured to collectively carry out instructions of a computer program by performing basic arithmetical, logical, and/or input/output operations on data, in which the data is represented in analog or digital form. In some implementations, the classical circuit elements on the second chip <NUM> may be used to transmit data to and/or receive data from the quantum circuit elements on the second chip <NUM> and/or the first chip <NUM> through electrical or electromagnetic connections.

Similar to the first chip <NUM>, the second chip <NUM> also may include a substrate <NUM> formed from a low loss dielectric material suitable for quantum circuits, such as single crystalline silicon or sapphire. The thickness of the substrate <NUM> may be between, e.g., approximately <NUM> and approximately <NUM>.

The first chip <NUM> may be joined to the second chip <NUM> through bump bonds <NUM>. The bump bonds <NUM> may be arranged to couple data between qubits on the first chip <NUM> and the circuit elements on the second chip <NUM>. The bump bonds <NUM> may include superconductor material to avoid energy loss and decoherence of qubits that may be located, e.g., on the first chip <NUM>. For instance, suitable superconductor material for use as a bump bond <NUM> includes, but is not limited to, indium, lead, rhenium, palladium, or niobium having a thin layer of gold. The bump bonds <NUM> may be formed on interconnect pads <NUM> on both the first chip <NUM> and the second chip <NUM>. In some implementations, to avoid diffusion between the bump bonds <NUM> and the interconnect pads <NUM>, the bump bonds <NUM> include a barrier layer that serves as an electrically conducting barrier to block diffusion of bump bond material into the interconnect pad <NUM> and/or vice-versa. An example barrier layer material includes titanium nitride.

The thickness of the bump bonds <NUM> may be set so that the first chip <NUM> and the second chip <NUM> are spaced to achieve a desired capacitive or inductive coupling between circuit elements on the first chip <NUM> and on the second chip <NUM>. For example, a distance <NUM> between a surface of the interconnect pads <NUM> on the first chip <NUM> and the interconnect pads <NUM> on the second chip <NUM> may be set to be between approximately <NUM> and approximately <NUM> (e.g., between approximately <NUM> and approximately <NUM>, between approximately <NUM> and <NUM>, between approximately <NUM> and approximately <NUM>, between approximately <NUM> and approximately <NUM>, between approximately <NUM> and approximately <NUM>, between approximately <NUM> and approximately <NUM>, or between approximately <NUM> and approximately <NUM>). The approximate distance may be within an uncertainty based on the accuracy and/or precision limitations of the deposition technique(s) used to deposit and/or remove material to form the bump bonds <NUM> (and/or other components that may affect the distance) as well as of the metrology technique(s) with which the distance is measured.

The interconnect pad <NUM> provides an electrical connection to a circuit element on the chip on which the pad <NUM> is formed. For example, the interconnect pads <NUM> of the first chip <NUM> are coupled (e.g., electrically or electromagnetically) to one or more circuit elements of the first chip <NUM>. Similarly, the interconnect pads <NUM> of the second chip <NUM> are coupled (e.g., electrically or electromagnetically) to one or more circuit elements of the second chip <NUM>. The coupling of the interconnect pads <NUM> to circuit elements may be provided by interconnects formed on and/or within the substrate of each chip. For instance, interconnect pads <NUM> of second chip <NUM> may be coupled to circuit elements through a single layer of metallization/superconductor material on the front-side surface of the substrate <NUM> (e.g., co-planar with the circuit elements). Alternatively, or in addition, the interconnect pads <NUM> of second chip <NUM> may be coupled to circuit elements on the backside surface <NUM> of substrate <NUM> using throughsubstrate contacts <NUM>. The interconnect pads <NUM> may be formed of a superconductor material to reduce decoherence and energy loss in adjacent quantum circuit elements and/or to reduce heat generated from the chip. For instance, the interconnect pads <NUM> may be formed from aluminum, niobium or titanium nitride. Other materials may be used for the interconnect pads <NUM> as well.

In some implementations, the second chip <NUM> also may include wire-bond pads <NUM>. The wire-bond pads <NUM> provide an area to which a wire-bond may be formed for electrically connecting the chip <NUM> to an external device, such as external electronic control and measurement devices. In some implementations, the wire-bond pads <NUM> are formed from the same material as the interconnect pads <NUM>. For example, the wire-bond pads may be formed from aluminum, niobium, or titanium nitride. Other materials also may be used for the wire-bond pads <NUM>.

As explained herein, the first layer <NUM> of second chip <NUM> includes components and/or materials that cause relatively low loss and decoherence in nearby quantum circuit elements, such as qubits, on the first chip <NUM>. For example, in some implementations, the first layer <NUM> includes a layer of superconductor material that is deposited on the low loss substrate <NUM>. The superconductor material of layer <NUM> may be patterned to form specific circuit elements, such as resonators, transmission lines, wire bond pads and interconnect pads <NUM>. In some implementations, the layer <NUM> may be formed directly in contact with the surface <NUM> of substrate <NUM>. In some implementations, the layer <NUM> does not include any dielectric material, such as deposited dielectrics. An advantage of forming the layer without dielectric material is that it reduces the loss such material can cause in nearby quantum circuit elements, such as qubits. According to the present invention, the layer <NUM> includes a single layer of superconductor material, such that the circuit elements of layer <NUM> are formed solely from the superconductor material. The superconductor material selected for layer <NUM> may include, e.g., aluminum, though other superconductor material may be used instead.

<FIG> is a schematic illustrating a top view of an example of layer <NUM> from carrier chip <NUM>. The layer <NUM> includes multiple co-planar circuit elements. For example, layer <NUM> may include one or more co-planar waveguide resonators <NUM>. The co-planar waveguide resonators <NUM> include a center line 202a, which is separated from a ground plane <NUM> on either side by a constant width gap (denoted by the black lines surrounding center lines 202a in <FIG>). In some implementations, the layer <NUM> includes one or more transmission lines <NUM>. The transmission lines <NUM> may be configured and arranged near one or more of the co-planar waveguide resonators <NUM> so that the transmission lines <NUM> can electromagnetically couple to the resonators <NUM> during operation of the carrier chip. Layer <NUM> may further include interconnect pads arranged to make contact with the bump bonds between the first chip <NUM> and the second chip <NUM>. Alternatively, or in addition, the interconnect pads may be electrically coupled to through-contacts arranged on or within the second chip. Layer <NUM> may further include wire-bond pads <NUM>. Each of the interconnect pads and the wire-bond pads <NUM> may be fabricated by etching away predetermined portions of the superconductor material on the substrate surface <NUM> to form defined superconductor regions. Wire-bond pads <NUM> may be electrically connected to the transmission lines <NUM>.

As explained herein, and referring again to <FIG>, the second chip <NUM> also includes second layer <NUM> formed on the second surface <NUM> of substrate <NUM>, in which the second layer <NUM> includes components and/or materials that can cause relatively higher loss in quantum circuit elements (e.g., qubits) than the materials/components of the first layer <NUM>. By arranging such circuit elements on the bottom side of the substrate <NUM>, those circuit elements are further away from the quantum circuit elements of the first chip <NUM> as well as from the quantum circuit elements of layer <NUM>. Therefore, the circuits formed within layer <NUM> are less likely to induce energy loss or decoherence in the quantum circuit elements of chip <NUM> or of layer <NUM>.

Layer <NUM> may include one or more layers of material. For example, layer <NUM> may include one or more layers of a deposited dielectric <NUM>, such as SiO<NUM>, SiN, or amorphous Si. Layer <NUM> may also include one or more layers of superconductor material <NUM>, such as aluminum. Alternatively or in addition, layer <NUM> may include materials that do not function as superconductors, such as copper or silver. The materials of layer <NUM> may be patterned into one or more quantum or classical circuit elements. Examples of quantum or classical circuit elements that may be formed in layer <NUM> include a resistor, an inductor, a capacitor (e.g., a parallel plate capacitor), a crossover wiring (e.g., an air-bridge connector), an amplifier (e.g., a traveling wave parametric amplifier), a resonator (e.g., an LC oscillator), or a Josephson logic circuit (e.g., an RSFQ device, and RQL device, or an ERSFQ device).

<FIG> is a schematic illustrating a top view of an example of layer <NUM>. As shown in the example of <FIG>, layer <NUM> includes multiple circuit elements. For instance, layer <NUM> in the example includes a co-planar transmission line <NUM>. The transmission line <NUM> includes a center line 302a formed from a superconductor material and may be separated from a ground plane <NUM>. Layer <NUM> also includes dielectric crossovers <NUM> that provide a common electrical connection between the ground planes on either side of the center line 302a without electrically connecting to the center line 302a. Layer <NUM> also includes a co-planar waveguide resonator <NUM>, parallel plate capacitors <NUM>, and hybrid junction transmission lines <NUM>. Fabrication of the parallel plate capacitors <NUM> and transmission lines <NUM> may include, e.g., deposition of a first layer of aluminum, followed by deposition of a dielectric layer, and then deposition of a second aluminum layer. In some implementations, a via opening may be established within the dielectric layer so that the second aluminum layer is deposited within the via and makes contact with the first aluminum layer after deposition. Multiple patterning (e.g., lithography and etching) steps may be required to define the different aluminum and dielectric layers.

Referring again to <FIG>, and as explained herein, first layer <NUM> and second layer <NUM> are coupled (e.g., electrically connected) by one or more connectors <NUM> that extend from the first surface <NUM> to the second surface <NUM> of the substrate <NUM> of carrier chip <NUM>. In some implementations, a connector <NUM> includes material that allows a low resistance electrical connection to be made be between one or more circuit elements of the first layer <NUM> and one or more circuit elements of the second layer <NUM>. For example, in some implementations, the second layer <NUM> includes an amplifier that is coupled to a measurement readout resonator through the connector <NUM>. Accordingly, in some implementations, a signal used to probe the resonator may be routed from layer <NUM> through connector <NUM> to the amplifier of layer <NUM>. Examples of material that can be used as the connector <NUM> include superconductor material such as aluminum or niobium. In some implementations, the connector <NUM> includes a material that is not a superconductor, but that still provides relatively low resistance, such as copper, tungsten or gold. The connectors <NUM> are located in a hole or via formed within the substrate <NUM>. The hole or via in the substrate may be formed using, e.g., reactive ion etching or other suitable technique that allows a relatively constant area opening to be formed through the thickness of the substrate <NUM>. Once the hole or via is formed, the hole or via may be filled to form the through-hole connector <NUM>. For instance, atomic layer deposition may be used to deposit tungsten or copper within the hole. Alternatively, or in addition, electroplating techniques may be used.

Although the connectors <NUM> are shown in <FIG> as extending through an opening in substrate <NUM>, the connectors <NUM> alternatively (or additionally) may be formed so that they extend along an outer edge of the substrate <NUM>, such that it is not necessary to form a hole within substrate <NUM>.

Implementations of the quantum subject matter and quantum operations described in this specification can be implemented in suitable quantum circuitry or, more generally, quantum computational systems, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term "quantum computational systems" may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, or quantum simulators.

The terms quantum information and quantum data refer to information or data that is carried by, held or stored in quantum systems, where the smallest non-trivial system is a qubit, e.g., a system that defines the unit of quantum information. It is understood that quantum memories are devices that can store quantum data for a long time with high fidelity and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

Quantum circuit elements may be used to perform quantum processing operations. That is, the quantum circuit elements may be configured to make use of quantum-mechanical phenomena, such as superposition and entanglement, to perform operations on data in a non-deterministic manner. Certain quantum circuit elements, such as qubits, may be configured to represent and operate on information in more than one state simultaneously. Examples of superconducting quantum circuit elements that may be formed with the processes disclosed herein include circuit elements such as co-planar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC-SQUID), inductors, capacitors, transmission lines, ground planes, among others.

In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements may be configured to collectively carry out instructions of a computer program by performing basic arithmetical, logical, and/or input/output operations on data, in which the data is represented in analog or digital form. In some implementations, classical circuit elements may be used to transmit data to and/or receive data from the quantum circuit elements through electrical or electromagnetic connections. Examples of classical circuit elements that may be formed with the processes disclosed herein include rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices and ERSFQ devices, which are an energy-efficient version of RSFQ that does not use bias resistors. Other classical circuit elements may be formed with the processes disclosed herein as well.

During operation of a quantum computational system that uses superconducting quantum circuit elements and/or superconducting classical circuit elements, such as the circuit elements described herein, the superconducting circuit elements are cooled down within a cryostat to temperatures that allow a superconductor material to exhibit superconducting properties.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what is claimed, but rather as descriptions of features that may be specific to particular implementations. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination.

For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. Moreover, the separation of various components in the implementations described above should not be understood as requiring such separation in all implementations.

Claim 1:
A device (<NUM>) comprising:
a first chip (<NUM>) comprising a quantum circuit element; and
a second chip (<NUM>) bonded to the first chip, the second chip comprising
a substrate (<NUM>) including a single first layer (<NUM>) on a first side (<NUM>) of the substrate, the single first layer joined to the first chip, wherein the single first layer comprises a superconductor material, and
a second layer (<NUM>) on a second different side (<NUM>) of the substrate,
characterised by a connector (<NUM>) that extends from the first side of the substrate to the second side of the substrate and connects a portion (<NUM>, <NUM>) of the single first superconductor layer to the second layer.