Patent Description:
light emitting elements are devices for converting electricity to light. As representative light emitting elements, there are light-emitting diodes (LEDs), semiconductor laser diodes (LD), etc..

LEDs are devices in which electrons and holes meet at P-N junction areas to emit light when currents are applied thereto. Usually, LEDs are fabricated in a package structure in which they are installed. An LED package is mounted on a printed circuit board (PCB) and configured to emit light by receiving currents from an electrode formed on the PCB.

In an LED package, heat generated in an LED may directly affect light-emitting performance or a lifespan of the LED package. When the heat generated in the LED stays therein for a long time, dislocation and mismatch may be generated in a crystal structure of the LED, which may shorten the lifespan of the LED.

Accordingly, techniques for promoting the dissipation of heat generated from an LED have been proposed. For example, a metal PCB having excellent heat dissipating characteristics may be applied to an LED package.

Meanwhile, when an LED package is mounted on a metal PCB, an expensive plating process may be performed to prevent oxidation, thus increasing the cost of the PCB.

<CIT> gives examples of metal substrate and light source device.

The present invention is directed to a printed circuit board and a light emitting device including the same.

According to an aspect of the present invention, there is provided a printed circuit board according to claim <NUM>.

According to still another aspect of the present invention, there is provided a light emitting device according to claim <NUM>.

The above and other objects, features, and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:.

Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, exemplary embodiments of the present invention may be embodied in many alternate forms and should not be construed as limited to the exemplary embodiments of the present invention set forth herein.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components and/or sections, these elements, components and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, or section from another. Therefore, a first element, a first component, or a first section could be termed a second element, a second component, or a second section within the scope of the invention. As used herein, the term "and/or" includes each and all combinations of at least one of the referred items.

Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

In the present disclosure, when it is expressed that any layer (film), region, pattern, or structure is formed "at the upper portion of (on)" or "at the lower portion of (under)" any layer (film), region, or pattern, the expressions "the upper portion (on)" and "the lower portion (under)" include both "directly" and "indirectly. " In addition, the criterion of "upper (on)" or "lower (under)" of each layer will be described based on the drawings.

In the drawings, the thickness and size of each layer shown in the drawings may be exaggerated, omitted, or schematically drawn for the purpose of convenience or clarity. In addition, the size of each component does not reflect an actual size.

Hereinafter, the embodiment of the present invention will be described in detail with reference to accompanying drawings. The same reference numerals denote the same components throughout the specification, and repeated descriptions thereof will be omitted.

<FIG> is a cross-sectional view illustrating a printed circuit board (PCB) according to an embodiment of the present invention, and <FIG> is a cross-sectional view illustrating a light emitting device including a PCB according to an embodiment of the present invention. In addition, <FIG> illustrates an example of an electroplating layer for wire-bonding.

Referring to <FIG>, a PCB <NUM> includes a substrate <NUM>, an insulating layer <NUM>, a circuit pattern <NUM>, a protection layer <NUM>, and a plating layer <NUM>.

The substrate <NUM> includes a first metal layer <NUM> having high thermal conductivity. The substrate <NUM> includes second and third metal layers <NUM> and <NUM> disposed on both sides of the first metal layer <NUM>. The first metal layer <NUM> is a copper (Cu) layer having high thermal conductivity. The first metal layer <NUM> may have low thermal resistance, and thus perform a heat-dissipating function to dissipate heat generated from a light emitting element package <NUM> to the outside.

The thickness of the first metal layer <NUM> may be designed to be different according to characteristics of a product to which the PCB <NUM> is applied.

The thickness of the first metal layer <NUM> may be, but is not limited to, <NUM> to <NUM>% of a total thickness of the substrate <NUM>.

For example, when the total thickness of the substrate <NUM> is <NUM>, the thickness of the first metal layer <NUM> may be <NUM> to <NUM>.

The second and third metal layers <NUM> and <NUM> are different kinds of metal layers from the first metal layer <NUM>. The second and third metal layers <NUM> and <NUM> are aluminum (Al) metal layers.

The second metal layer <NUM> is formed on the first metal layer <NUM> and disposed between the first metal layer <NUM> and the insulating layer <NUM>.

The second metal layer <NUM> may improve adhesion between the first metal layer <NUM> and the insulating layer <NUM>. In addition, the second metal layer <NUM> function to prevent surface oxidation of the substrate <NUM> exposed by a cavity <NUM>.

The third metal layer <NUM> may be formed on a rear surface of the first metal layer <NUM>.

The third metal layer <NUM> functions to prevent surface oxidation of the substrate <NUM>.

Al has a thermal conductivity of more than <NUM> W/m·k and has high temperature thermal resistance at high temperature.

Al has a relatively lighter weight but a relatively higher thermal resistance than Cu. Accordingly, as a ratio of thickness of the second and third metal layers <NUM> and <NUM> in the substrate <NUM> decreases, the thermal resistance of the substrate <NUM> may decrease. On the other hand, as a ratio of thickness of the second and third metal layers <NUM> and <NUM> in the substrate <NUM> increases, the substrate <NUM> may be fabricated to have a lighter weight, and the price of the substrate may be lowered.

The thicknesses of the second metal layer <NUM> and third metal layer <NUM> may be designed differently according to characteristics of a product to which the PCB <NUM> is applied.

The ratio of the thickness of the second and third metal layers <NUM> and <NUM>, that is, the sum of the thickness of the second metal layer <NUM> and the thickness of the third metal layer <NUM> in the substrate <NUM> may be, but is not limited to, <NUM> to <NUM>% of the total thickness of the substrate <NUM>. In addition, the thickness of each of the second and third metal layers <NUM> and <NUM> may be <NUM> to <NUM>% of the total thickness of the substrate <NUM>.

For example, when total thickness of the substrate <NUM> is <NUM>, the sum of the thickness of the second metal layer <NUM> and the thickness of the third metal layer <NUM> in the substrate <NUM> may be <NUM> to <NUM>. In addition, the thickness of each of the second and third metal layers <NUM> and <NUM> may be <NUM> to <NUM>.

When the ratio of the thickness of the second and third metal layers <NUM> and <NUM> in the substrate <NUM> is less than <NUM>%, a manufacturing process may become difficult and surface oxidation of the substrate <NUM> may not be prevented. In addition, when the ratio of the thickness of the second and third metal layers <NUM> and <NUM> in the substrate <NUM> is more than <NUM>%, a heat dissipating ability may be lowered and a light emitting device generating a large amount of heat, such as a light-emitting diode, may be difficult to mount on the PCB <NUM>.

The second metal layer <NUM> and the third metal layer <NUM> may have the same thickness. Alternatively, the second metal layer <NUM> and the third metal layer <NUM> may have different thicknesses.

The substrate <NUM> may be formed in a clad substrate so as to improve endurance. The clad substrate may be formed by stacking the first, second and third metal layers <NUM>, <NUM> and <NUM>, and then combining them using a hot- or cold-rolling method.

The insulating layer <NUM> may be disposed on the second metal layer <NUM>.

The insulating layer <NUM> may function to prevent the substrate <NUM> from being electrically connected to the circuit pattern <NUM>.

The insulating layer <NUM> may be selected from the group consisting of an epoxy resin, a polyester resin, and a polyimide resin.

The insulating layer <NUM> may be combined with second metal layer <NUM> in various methods.

The insulating layer <NUM> may be combined with the second metal layer <NUM> using a sputtering method.

The insulating layer <NUM> may be stacked on the second metal layer <NUM> in a provisionally cured state and then fully cured by compression to be combined with the second metal layer <NUM>.

The insulating layer <NUM> may be coated on the second metal layer <NUM> and then cured to be combined with the second metal layer <NUM>.

The cavity <NUM> configured to accommodate the light emitting element package <NUM> is formed through the insulating layer <NUM>.

The cavity <NUM> may be formed through the insulating layer <NUM> in the shape of an opening having an open top. Accordingly, a portion of the second metal layer <NUM> may form a lower surface of the cavity <NUM> and be exposed through the opening of the cavity <NUM>.

Accordingly, the second metal layer <NUM> may function to prevent surface oxidation of the substrate <NUM> exposed through the cavity <NUM>.

By forming the cavity <NUM>, the insulating layer <NUM> disposed between the light emitting element package <NUM> and the substrate <NUM> may be removed, and thus a thermal resistance factor by the insulating layer <NUM> may be removed. That is, since heat generated by the light emitting element package <NUM> is directly transmitted to the substrate <NUM> by forming the cavity <NUM>, a heat dissipating ability of the PCB <NUM> may be improved.

The cavity <NUM> may be formed by a cutting process using a laser apparatus, a computerized numerical control (CNC) milling process, or a punching process.

The circuit pattern <NUM> may be disposed on the insulating layer <NUM>.

The circuit pattern <NUM> may be formed of a conductive metal. For example, the circuit pattern <NUM> may be formed of Cu or a Cu alloy mainly composed of Cu.

The protection layer <NUM> and the plating layer <NUM> may be disposed on the circuit pattern <NUM>.

The protection layer <NUM> may function to electrically isolate the PCB <NUM> and reduce electrical/physical stress.

The protection layer <NUM> may be formed using a solder resist, a coverlay, or the like.

The plating layer <NUM> may be electrically connected to the circuit pattern <NUM>, and form a bonding pad configured for wire-bonding of the light emitting element package <NUM>.

The plating layer <NUM> may be formed by an electroless Cu plating method, a chemical Cu plating method, an electroless nickel immersion gold (ENIG) method, an electroless nickel electroless palladium immersion gold (ENEPIG) method, an electroless nickel auto-catalytic gold (ENAG) method, an electroless nickel electroless Au & Ag immersion gold (ENA2) method, a direct immersion gold (DIG) method, or an electroless silver plating method.

For example, the plating layer <NUM> may be formed by the ENEPIG method as illustrated in <FIG>. Referring to <FIG>, the ENEPIG method is an electroless plating method by which a three-layered structure of electroless Ni, electroless Pd, and substituted Au is formed. The plating layer <NUM> formed by the ENEPIG method may be formed by sequentially stacking a nickel (Ni) layer <NUM>, a palladium (Pd) layer <NUM>, and a gold layer <NUM>. Since the plating layer <NUM> formed by the ENEPIG method includes the palladium layer <NUM> between the Al layer <NUM> and the gold layer <NUM>, thermal diffusion of the Al layer <NUM> may be suppressed, and thus a bond strength of soldering may be improved.

Referring again to <FIG>, the light emitting device may include the PCB <NUM> and the light emitting element package <NUM> disposed on the PCB <NUM>.

The light emitting element package <NUM> may include a ceramic substrate <NUM> and a light emitting element chip <NUM> disposed on the ceramic substrate <NUM>.

The light emitting element package <NUM> may be accommodated in the cavity (reference numeral <NUM> in <FIG>) of the insulating layer <NUM>. In addition, the light emitting element package <NUM> may be attached to the second metal layer <NUM> of the substrate <NUM> exposed through the cavity <NUM> using a conductive adhesive <NUM> as a medium.

The conductive adhesive <NUM> may be an electrically conductive adhesive and include a metal paste, etc..

Wires electrically respectively connected to an anode terminal and a cathode terminal of the light emitting element package <NUM> may be electrically connected to the circuit pattern <NUM> through the plating layer <NUM>.

Generally, while manufacturing a PCB, a circuit pattern and a plating layer may be formed after a substrate and an insulating layer are stacked and combined. Accordingly, it is difficult to form a wire-bonding plating layer and an anti-oxidation layer in separate plating processes. This is because a masking process is required to form the plating layer for wire bonding and the anti-oxidation layer in separate plating processes, which may act as a factor increasing a failure rate.

According to the invention, by applying a clad substrate in which an Al metal layer is combined to both sides of a first metal layer of a PCB, an anti-oxidation layer need not be separately formed. In addition, since a plating layer is not formed on a surface of the Al metal layer due to the nature of Al even when a surface thereof is exposed to a plating process environment, a separate masking process need not be performed.

As described above, according to the disclosure, since the plating layer formed on a surface of the substrate in order to prevent oxidation is replaced by the Al metal layer, a high-end plating area portion may be minimized and thus material costs required in a plating process may be minimized. In addition, since the masking process for forming the wire-bonding plating layer and the anti-oxidation layer in separate processes is omitted, price competitiveness of a PCB may be improved.

Meanwhile, according to the invention, the substrate is formed as a clad substrate in which Al metal layers are stacked and combined on both sides of a Cu metal layer.

According to the an illustrative example not part of the invention, the Cu metal layer may be replaced by another metal layer having excellent thermal conductivity.

According to the disclosure, since an expensive plating process is omitted, a unit cost of the printed circuit may be reduced.

Claim 1:
A printed circuit board (<NUM>) comprising:
a substrate (<NUM>) including a first metal layer (<NUM>), a second metal layer (<NUM>) formed on one surface of the first metal layer (<NUM>) and which is a different kind of metal layer from the first metal layer (<NUM>), and a third metal layer (<NUM>) formed on the other surface of the first metal layer (<NUM>) and which is a different kind of metal layer from the first metal layer (<NUM>);
an insulating layer (<NUM>) formed on the substrate (<NUM>) and including a cavity (<NUM>) configured to accommodate a light emitting element package (<NUM>);
a circuit pattern (<NUM>) formed on the insulating layer (<NUM>);
a protection layer (<NUM>); and
a plating layer (<NUM>) formed on the circuit pattern (<NUM>),
wherein the plating layer (<NUM>) is not formed on a portion of the substrate (<NUM>) where the insulating layer (<NUM>) does not cover the substrate (<NUM>) ;
wherein the protection layer (<NUM>) is formed on the circuit pattern (<NUM>),
wherein a thermal conductivity of the first metal layer (<NUM>) is greater than thermal conductivities of the second metal layer (<NUM>) and the third metal layer (<NUM>),
wherein the second metal layer (<NUM>) is exposed by the cavity (<NUM>), a portion of the second metal layer (<NUM>) forming the entirety of the lower surface of the cavity (<NUM>),
wherein the second metal layer (<NUM>) and the third metal layer (<NUM>) prevent surface oxidation of the substrate (<NUM>),
wherein the first metal layer (<NUM>) is a copper (Cu) layer, and.
wherein the second metal layer (<NUM>) and the third metal layer (<NUM>) are aluminum metal (Al) layers.