Patent Description:
In many applications, it may be useful to have a MIM to be used as a capacitor in a relatively high voltage application, and an adjacent MIM to be used as a capacitor in a relatively low voltage application. In an example, in a conventional system, if both a high voltage MIM and a low voltage MIM are to be supported on a same wafer or process, this may require multiple mask layers (e.g., each mask layer to form a corresponding metal or insulator layer of a MIM), which may be costly and/or time consuming.

<CIT> and <CIT> disclose prior art configurations of integrated circuits including MIM capacitors having different characteristics.

The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

MIM capacitors are a particular type of capacitor, having a top metal plate and a bottom metal plate separated by a capacitor dielectric, which are often implemented in integrated circuits. In an example, a MIM capacitor may have multiple stacked conductive layers, each separated from an adjacent one by an insulator layer. In many applications (e.g., circuits used for RF applications), it may be useful to have a MIM to be used as a capacitor in a relatively high voltage application, and an adjacent MIM to be used as a capacitor in a relatively low voltage application.

In an example, an electric field of a capacitor may be given by:
<MAT>
where E may be the electric field, V may be the applied voltage, and d may be a distance between adjacent conductive plates.

In an example, a capacitance C of a capacitor may be given by:
<MAT>
where ε may be a permittivity associated with the capacitor, A may be an area of the capacitor, and d may be the distance between adjacent conductive plates.

In an example, an insulator may support limited electrical field, thereby limiting the value of E in equation <NUM>. For example, for higher voltage application (e.g., high V in equation <NUM>), the distance d may have to be increased. However, an increase in the distance d may result in a corresponding decrease in the capacitance.

In some embodiments, this disclosure discloses a device having a high voltage MIM capacitor formed adjacent to a low voltage MIM capacitor. In some embodiments, a via for the high voltage MIM capacitor has a larger width than the vias for the low voltage MIM capacitor. As discussed in further details herein, the difference in the dimensions of various vias allow for formation of the adjacent capacitors (e.g., on a same wafer, and using at least in part a same formation process). In some embodiments, the low voltage capacitor has at least a via passing through a conductive plate, without being in contact with the conductive plate (e.g., a spacer may block contact of the via from the conductive plate). Such designs and other features may allow formation of conductive and insulating layers of the high voltage capacitor MIM using a single mask, as discussed in further details herein. Similarly, conductive and insulating layers of the low voltage capacitor MIM may also be formed using a single mask, as discussed in further details herein. Thus, the principles of this disclosure may be used to reduce a number of masks for forming the device comprising the high voltage MIM and adjacent low voltage MIM, thereby resulting in cost, time and/or area improvements. Other technical effects will be evident from the various embodiments and figures.

In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on. " The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- <NUM>% of a target value.

Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B).

<FIG> illustrates a device <NUM> comprising two adjacent MIMs 100a and 100b, which may be configured for a high voltage operation and a low voltage operation, respectively, according to some embodiments. The MIM 100a may be configured for high voltage operation, where the high voltage may be, merely as an example, <NUM> Volts (V) or higher. The MIM 100b may be configured for low voltage operation, where the low voltage may be, merely as an example, less than <NUM> V. In some embodiments, the MIMs 100a and 100b are configured as two respective capacitors.

The MIM 100a comprises conductive layers 104a and 104b, and insulating layers 108a and 108b, arranged in an interleaved stack. The MIM 100b comprises conductive layers 104c and 104d, and insulating layers 108c and 108b, arranged in an interleaved stack. Thus, the insulating layer 108b is common to both the MIMs 100a and 100b. Although <FIG> illustrates two conductive layers and two insulating layers in each of the MIMs 100a and 100b, in some embodiments, the principles of this disclosure can be applied to MIMs comprising higher number of stacked conductive layers <NUM> and insulating layers <NUM>.

Elements referred to herein with a common reference label followed by a particular number or alphabet may be collectively referred to by the reference label alone. For example, conductive layers 104a, 104b, 104c, 104d may be collectively and generally referred to as conductive layers <NUM> in plural, and conductive layer <NUM> in singular. Similarly, insulating layers 108a, 108b, 108c may be collectively and generally referred to as insulating layers <NUM> in plural, and insulating layer <NUM> in singular.

In some embodiments and as discussed in further details herein, the conductive layers 104c and 104d are of a single continuous conductive layer (e.g., the conductive layers 104c and 104d may be formed by selectively etching the single continuous conductive layer). In an example, the conductive layers 104c and 104d may be referred to herein as part of a same layer. For example, the conductive layers 104c and 104d may be referred to herein as an upper layer of the MIMs 100a and 100b, respectively. Similarly, for example, the conductive layers 104b and 104d may be referred to herein as a middle layer of the MIMs 100a and 100b, respectively. In example, the insulating layers 108a and 108c may be formed by etching and dividing a single insulating layer. Thus, the insulating layers 108a and 108c may be referred to herein as a first insulating layer of the MIMs 100a and 100b, respectively (e.g., the insulating layers 108a and 108c may be referred to using a common label, such as a first insulating layer). In an example, the insulating layer 108b may be referred to herein as a second insulating layer of the MIMs 100a and 100b, respectively.

In some embodiments, heights of the conductive layers 104a and 104c along the Z axis in <FIG> are similar (e.g., as both the conductive layers 104a and 104c may be of a same conductive layer, as discussed herein), e.g., with ±<NUM>% of each other; a height of the conductive layers 104b and 104d may be similar (e.g., with ±<NUM>% of each other); and a height of the insulating layers 108a and 108c may be similar (e.g., with ±<NUM>% of each other).

In some embodiments and as illustrated in <FIG>, a thickness or height of the insulating layer 108b (e.g., along a Z axis) is larger than thicknesses or heights of one or more of the conductive layers 104a, 104b, 104c, 104d and/or the insulating layers 108a and 108c. For example, the height of the insulating layer 108b may be at least double or more than the heights of the conductive layers 104a, 104b, 104c, 104d and/or the insulating layers 108a and 108c. In another example, the height of the insulating layer 108b may be up to about <NUM> times the heights of the conductive layers 104a, 104b, 104c, 104d and/or the insulating layers 108a and 108c. For example, because the high voltage capacitor is formed using the insulating layer 108b, the height of the insulating layer 108b may be relatively larger. In contrast, because the low voltage capacitor is formed using the insulating layer 108c, the height of the insulating layer 108c may be relatively smaller. In some embodiments, the heights of the insulating layers 108b and 108c is based on the voltage ratings of the high voltage capacitor and the low voltage capacitor, respectively.

The insulating layer 108b has a higher breakdown voltage than one or both of the insulating layers 108a and 108c. For example, a breakdown voltage of a layer may be based on a composition of the layer, a thickness of the layer, a dielectric strength of the layer, etc. As the thickness or height of the insulating layer 108b is larger than thicknesses or heights of the insulating layers 108a and 108c, the insulating layer 108b has a higher breakdown voltage than the insulating layers 108a and 108c.

In some embodiments, sizes of the stacked layers <NUM> and <NUM> determine a capacitance of the MIMs 100a and 100b, and the size of individual ones of the stacked layers <NUM> and <NUM> is based on a desired capacitance of the MIMs 100a and 100b. In some embodiments, the dimensions (e.g., length and width, but not necessarily the height) of the layers 104a, 108a, and 104b are similar (e.g., the dimensions of these layers may be within <NUM>% of each other), e.g., as these layers may be formed using a single mask, as discussed in further details herein. In some embodiments, the dimensions (e.g., length and width, but not necessarily the height) of the layers 104c, 108c, and 104d are similar (e.g., the dimensions of these layers may be within <NUM>% of each other), e.g., as these layers may be formed using a single mask, as discussed in further details herein.

In some embodiments, the conductive layers <NUM> include conductive material, such as, but not limited to, one or more of platinum (Pt), aluminum-copper (AlCu), titanium nitride (TiN), gold (Au), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), copper (Cu), and/or the like. In some embodiments, the insulating layers <NUM> include insulating or dielectric material, such as, but not limited to, one or more of nickel oxide (NiO), titanium oxide (TiO), hafnium oxide (HfO), zirconium oxide (ZrO), zinc oxide (ZnO), tungsten oxide (WO3), aluminum oxide (Al2O3), tantalum oxide (TaO), molybdenum oxide (MoO), copper oxide (CuO), silicon dioxide (SiO2), silicon nitride (Si3 N4), polymide, and/or the like.

In some embodiments, the MIMs 100a, 100b are formed over an Inter-layer Dielectric (ILD) <NUM>. For example, a bottom side of the MIMs 100a, 100b may be encapsutaed by the ILD <NUM>. In some embodiments, a top side of the MIMs 100a, 100b (e.g., which may be opposite the bottom side) are encapsulated by ILD <NUM>. Any appropriate dielectric material (e.g., low k dielectric material) may be used for the ILDs <NUM> and <NUM>.

The MIM 100a includes a conductive layer <NUM>, which may form a bottom electrode of the MIM 100a (e.g., the conductive layer <NUM> may also be referred to as bottom electrode <NUM>, or simply as electrode <NUM>, of the MIM 100a). The electrode <NUM> may be form on the insulating layer 108b, and may be aligned to be underneath the stack comprising the layers 104a, 108a, and 104b. The electrode <NUM> may include conductive material, such as, but not limited to, one or more of platinum (Pt), aluminum-copper (AlCu), titanium nitride (TiN), gold (Au), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), copper (Cu), and/or the like. Merely as an example, the electrode <NUM> may comprise copper.

In some embodiments, the device <NUM> includes an interconnect layer <NUM> including conductive material such as, but not limited to, one or more of platinum (Pt), aluminum-copper (AlCu), titanium nitride (TiN), gold (Au), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), copper (Cu), and/or the like. Merely as an example, the interconnect layer <NUM> includes copper. In some embodiments, the interconnect layer <NUM> is not aligned (e.g., may not be underneath) the stack comprising the layers 104a, 108a, and 104b, or the stack comprising the layers 104c, 108c, and 104d.

In some embodiments, the MIM 100a comprises a via <NUM> that is at least in part through the stack comprising the layers 104a, 108a, and 104b. For example, the via <NUM> may extend through the conductive layer 104a and the insulating layer 108a, and may be in contact with the conductive layer 104b (e.g., may extend partially or fully through the conductive layer 104b). In an example, the via <NUM> may be in contact with the insulating layer 108b. In some embodiments, the via <NUM> is not in contact with the electrode <NUM> (e.g., the via may not extend through the insulating layer 108b). Thus, in an example, the via <NUM> may electrically connect the conductive layers 104a and 104b.

The insulating layer 108b separates the conductive layer 104b from the electrode <NUM>. In some embodiments, when voltage is applied between the via <NUM> and the electrode <NUM>, a capacitance is formed between the conductive layer 104b and the electrode <NUM> of the MIM 100a. In an example, as the insulating layer 108b may be relatively thick (e.g., having height larger than the height of the insulating layer 108c), the capacitor developed between the conductive layer 104b and the electrode <NUM> of the MIM 100a may be able to handle relatively higher voltage (e.g., compared to that of the MIM 100b). It may be noted that as the conductive layers 104a and 104b are connected by the via <NUM>, these two conductive layers may be at similar potential.

Thus, in some embodiments, upper conductive layer 104a, middle conductive layer 104b and lower conductive layer (or electrode) <NUM> may form a capacitor stack (e.g., along with the interleaved insulating layers 108a and 108b) associated with the MIM 100a. As discussed, this capacitor stack may be rated for relatively higher voltage (e.g., compared to that of the MIM 100b).

In some embodiments, the MIM 100b comprises a first via <NUM> and a second via <NUM>. The first via <NUM> extends at least in part through the stack comprising the layers 104c, 108c, 104d, 108b. For example, in the embodiment of <FIG>, the first via <NUM> extends through the layers 104c, 108c, 104d, 108b, and may be partially through the ILD <NUM>. In another embodiment, the first via <NUM> extends through the layers 104c, 108c, and is in contact with, partially extend, or fully extend through the layer 104d. In another embodiment, the first via <NUM> extends through the layers 104c, 108c, 104d, and is in contact with, partially extend, or fully extend through the layer 108b.

The via <NUM> is coupled to (e.g., in direct contact with, and attached to) the conductive layer 104d. The via <NUM> is not in contact with the conductive layer 104c. One or more spacers <NUM> isolate (e.g., physically and/or electrically isolate) the via <NUM> from the conductive layer 104c. For example, the spacer <NUM> may be between one or more sidewalls of the conductive layer 104c and a portion of the via <NUM> that extends through the conductive layer 104c. For example, the spacer <NUM> may act as a blocking layer to block or isolate the via <NUM> from the conductive layer 104c. In an example, the spacer <NUM> may also partially or fully isolate the via <NUM> from the insulating layer 108c. Thus, the spacer <NUM> results in the via <NUM> being in contact with the conductive layer 104d, while being isolated from the conductive layer 104c.

<FIG> illustrates a plan view of the via <NUM> surrounded by the spacer <NUM>, according to some embodiments. For example, the plan view of <FIG> may be along the line A of <FIG>. As illustrated in <FIG>, the spacers <NUM> may isolate the via <NUM> from the conductive layer 104c. For example, the spacer <NUM> may be between one or more sidewalls of the conductive layer 104c and a portion of the via <NUM> that extends through the conductive layer 104c.

Referring again to <FIG>, in some embodiments, the via <NUM> of the MIM 100b is in contact with the conductive layer 104c, while being isolated from the conductive layer 104d. For example, the via <NUM> may be in direct contact with, or at least partially or fully penetrate, the conductive layer 104c.

The insulating layer 108c separates the conductive layer 104c from the conductive layer 104d. In some embodiments, when voltage is applied between the via <NUM> and the via <NUM>, a capacitance is formed between the conductive layers 104c and 104d. In an example, as the insulating layer 108c may be relatively thin (e.g., having height smaller than the height of the insulating layer 108b), the capacitor developed between the conductive layers 104c and 104d of the MIM 100b may be able to handle relatively lower voltage (e.g., compared to that of the MIM 100a). In an example, the conductive layer 108b may not be used for developing the capacitance in the MIM 100b.

Thus, in some embodiments, upper conductive layer 104c and middle conductive layer 104d may form a capacitor stack (e.g., along with the interleaved insulating layers 108c and 108b) associated with the MIM 100b. As discussed, this capacitor stack may be rated for relatively lower voltage (e.g., compared to that of the MIM 100a).

Thus, in an example, the capacitor formed using the MIM 100a may be used for higher voltage applications, and the capacitor formed using the MIM 100b may be used for lower voltage applications. In an example, the high and low voltage capacitors may coexist adjacent to each other in the same chip.

In some embodiments, the spacer <NUM> has high breakdown voltage. For example, the breakdown voltage of the spacer <NUM> exceeds the breakdown voltage of the insulator layer 108c, e.g., so that the spacer <NUM> can withstand higher voltage than the insulating layer 108c, where the insulating layer 108c forms a part of the capacitor associated with the MIM 100b.

In some embodiments, the interconnect layer <NUM> is coupled to vias <NUM> and <NUM>. The interconnect layer <NUM> may form an interconnection between the vias <NUM> and <NUM>. In some embodiments, the vias <NUM> and <NUM> respectively comprise spacers <NUM> and <NUM> (e.g., as a byproduct of forming the spacers on the via <NUM>). In an example, the spacers <NUM>, <NUM> may not be used for any isolation purposes. In some other embodiments and although not illustrated in <FIG>, the spacers <NUM> and <NUM> are absent from the device <NUM>. In some other embodiments and although not illustrated in <FIG>, the interconnect layer <NUM> and/or the vias <NUM> and <NUM> are absent from the device <NUM>.

In some embodiments, the via <NUM> has a width (e.g., a cross-sectional diameter) of about m1; one or more of the vias <NUM>, <NUM>, and <NUM> has a width (e.g., a cross-sectional diameter) of about m2; and the via <NUM> has a width (e.g., a cross-sectional diameter) of about m3. In some embodiments, the dimensions m1, m2, and m3 are substantially different, e.g., m1 may be higher than m2, and m2 may be higher than m3. For example, m1 may be at least double or more than m2, and m2 may be at least double or more than m3. The difference in the dimensions m1, m2, and m3 may facilitate selective isolation of the vias <NUM>-<NUM>, such that a sidewall of via <NUM> is unlined (e.g., by spacers <NUM>-<NUM>) and continuity with both conductive layers 104a and 104b is maintained.

Although the components <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are referred to as vias, these components may also be referred to as metal plugs, interconnection structures, and/or the like.

Although the insulating layer 108b is illustrated to be a continuous layer among the two capacitor stacks of the two MIMs 100a and 100b, in some embodiments (and although not illustrated in <FIG>), the insulating layer 108b may also be separated to form two discontinuous layers for the two respective capacitor stacks.

In some embodiments and although not illustrated in <FIG>, the thickness of the insulating layer 108b can be swapped with the thickness of the insulating layers 108a and 108c. In such an embodiment, the insulating layer 108b is thinner than the insulating layers 108a and 108c. In such embodiments, for example, the via <NUM> is in contact with the conductive layer 104a, but not in contact with the conductive layer 104b (e.g., similar to the via <NUM> of <FIG>), and the electrode <NUM> extends through the bottom insulating layer 108b and is in contact with the conductive layer 104b. Positions and/or thicknesses of various layers and/or vias of the device <NUM> may be altered in some example.

<FIG> illustrate example processes for formation of the device <NUM> of <FIG>, according to some embodiments. For example, <FIG> are cross-sectional views of the device <NUM> evolving as example operations for formation of the device <NUM> are performed.

Referring to <FIG>, multiple interleaved and stacked conductive layers 204a, 204b, and insulating layers 208a, 108b may be formed over the ILD <NUM>. The stack of the conductive layers 204a, 204b, and the insulating layers 208a, 108b may be formed by deposition of thin films of conductive and insulating material. In some embodiments, the conductive layer <NUM> and the interconnect layer <NUM> are formed at appropriate positions underneath the insulating layer 108b.

Referring now to <FIG>, the stack of the conductive layers 204a, 204b, and insulating layers 208a, 108b may be etched to form a first stack 203a and a second stack 203b. The first stack 203a may comprise conductive layer 104a, insulating layer 108a, conductive layer 104b, and insulating layer 108b; and the second stack 203b may comprise conductive layer 104c, insulating layer 108c, conductive layer 104d, and insulating layer 108b. For example, the conductive layer 204a of <FIG> may be etched to form the conductive layers 104a and 104c of <FIG>; the insulating layer 208a of <FIG> may be etched to form the insulating layers 108a and 108c of <FIG>; and the conductive layer 204b of <FIG> may be etched to form the conductive layers 104b and 104d of <FIG>. The two stacks 203a and 203b may be adjacent to, but separate from each other, as illustrated in <FIG>.

The two stacks 203a, 203b of <FIG> may be formed by, for example, lithography using patterning and etching. The stack of <FIG> may be etched, e.g., using a mask, to form the stacks 203a and 203b. In some embodiments, because the stack 203a may be formed using a single mask, the layers 104a, 108a, 104b are of similar dimensions (e.g., similar length and width) and are aligned (e.g., not offset with respect to each other), as discussed with respect to <FIG>. In some embodiments, because the stack 203b may be formed using a single mask, the layers 104c, 108c, 104d are of similar dimensions (e.g., similar length and width) and are aligned (e.g., not offset with respect to each other), as discussed with respect to <FIG>.

Thus, the layers 104a and 104c are formed from a same layer 204a. In an example, the layers 104a and 104c are referred to as an upper layer of two separate capacitor stacks associated with the two MIMs 100a and 100b. Similarly, for example, the conductive layers 104b and 104d may be referred to herein as a middle layer of the MIMs 100a and 100b, respectively. Similarly, for example, the insulating layers 108a and 108c may be referred to herein as a first insulating layer of the MIMs 100a and 100b, respectively; and the insulating layer 108b may be referred to herein as a second insulating layer of the MIMs 100a and 100b, respectively.

Although the insulating layer 108b is illustrated to be a continuous layer among the two capacitor stacks of the two MIMs 100a and 100b, in some embodiments (and although not illustrated in the figures), the insulating layer 108b may also be etched to form two separate discontinuous layers for the two respective capacitor stacks.

Referring now to <FIG>, a ILD layer <NUM> may be deposited to encapsulate the stacks 203a and 203b. Subsequently, a hard mask layer <NUM> may be deposited on the ILD layer <NUM>. Photoresist layer <NUM> comprising photoresist material may be patterned over the hard mask layer <NUM>. In some embodiments, a first opening <NUM> (e.g., which may be over an eventual position of the via <NUM>) in the photoresist layer <NUM> over the stack 203a has a diameter of a1. A second opening <NUM> and a third opening <NUM> (e.g., which may be over eventual positions of the vias <NUM> and <NUM>, respectively) in the photoresist layer <NUM> over the stack 203a may have diameters of a2 and a3, respectively. A fourth opening <NUM> and a fifth opening <NUM> (e.g., which may be in eventual positions of the vias <NUM> and <NUM>, respectively) in the photoresist layer <NUM> over the interconnect layer <NUM> may have diameters of about a2. In some embodiments, a1 is larger than a2, and a2 is larger than a3. For example, a1 may be at least double or more than a2, and a2 may be at least double or more of a3. The difference in the dimensions a1, a2, and a3 may facilitate the formation of the various vias, e.g., as discussed herein in further detail.

Referring now to <FIG>, hark mask layer <NUM> exposed through the photoresist layer <NUM> may be etched, and the photoresist layer <NUM> may then be removed, thereby transferring the pattern into the hark mask layer <NUM>. Thus, the hard mask layer <NUM> may have various openings, e.g., similar to the openings of the photoresist layer <NUM> discussed herein above.

Referring now to <FIG>, a conformal hard mask layer <NUM> may be deposited (e.g., conformally deposited) on the hard mask layer <NUM>, e.g., using thin-film deposition methods, such as plating, chemical vapor deposition, atomic layer deposition, and/or the like. The conformal hard mask layer <NUM> may then be etched, for example, anisotropically. In some embodiments, as the width a1 of the opening <NUM> is larger than the widths a2 and a3 of the other openings <NUM>, <NUM>, <NUM>, <NUM>, the conformal hard mask layer <NUM> forms a ridge, recess or low depth region within the opening <NUM>. Etching of the conformal hard mask layer <NUM> may expose the ILD <NUM> through the opening <NUM>, as illustrated in <FIG>. Because of the relatively low width of the other openings <NUM>, <NUM>, <NUM>, <NUM> of the hard mask <NUM> (e.g., openings having width of a2 and a3), the deposition and etching of the conformal hard mask layer <NUM> may not expose the ILD <NUM> through these openings. Thus, due to the difference in the sizes of the various openings (e.g., as indicated in <FIG> and <FIG>), the ILD <NUM> may be exposed only through the opening <NUM> (and not exposed through the other openings).

Referring now to <FIG>, the ILD <NUM>, the conductive layer 104a and the insulating layer 108a may be selectively etched through the opening <NUM>. The etching in <FIG> may be performed using any appropriate etching technique, e.g., dry etch, wet chemical etch, etc. The etchants used may be selective to the material of the conductive layers <NUM> and the insulating layer <NUM>. Merely as an example, initially a selective etchant may be used to etch the ILD <NUM> underneath the opening <NUM>. Subsequently, another selective etchant may be used to etch the conductive layer 104a underneath the opening <NUM>. Finally, yet another selective etchant may be used to etch the insulating layer 108a underneath the opening <NUM>.

Referring now to <FIG>, a sacrificial material <NUM> may be deposited in the opening <NUM>. Subsequently, the conformal hard mask layer <NUM> may be removed (e.g., may be isotropically etched or stripped), thereby recovering the openings <NUM>, <NUM>, <NUM>, <NUM>, as illustrated in <FIG>.

Referring now to <FIG>, a conformal hard mask layer <NUM> may be deposited (e.g., conformally deposited) on the hard mask layer <NUM>, e.g., using thin-film deposition methods, such as plating, chemical vapor deposition, atomic layer deposition, and/or the like. The conformal hard mask layer <NUM> may then be etched. In some embodiments, as the width a2 of the openings <NUM>, <NUM>, <NUM> is larger than the width a3 of the opening <NUM>, the conformal hard mask layer <NUM> forms a ridge, recess or low depth region within the opening <NUM>, <NUM>, <NUM>. Etching of the conformal hard mask layer <NUM> may expose the ILD <NUM> through the openings <NUM>, <NUM>, <NUM>, as illustrated in <FIG>. Because of the relatively low width of the opening <NUM> of the hard mask <NUM> (e.g., opening having width of a3), the deposition and etching of the conformal hard mask layer <NUM> may not expose the ILD <NUM> through this opening, as illustrated in <FIG>. Thus, due to the difference in the sizes of the various openings (e.g., as indicated in <FIG> and <FIG>), the ILD <NUM> may be exposed only through the openings <NUM>, <NUM>, <NUM> of the hard mask layer <NUM> (and not exposed through the opening <NUM>).

Referring now to <FIG>, the ILD <NUM>, the conductive layers 104c, 104d, the insulating layers 108c, 108b (and optionally at least a part of IDL <NUM>) may be selectively etched through the opening <NUM>. In some embodiments, the ILD <NUM> also is selectively etched through the openings <NUM> and <NUM>. The etching in <FIG> may be performed using any appropriate etching technique, e.g., dry etch, wet chemical etch, etc., using one or more selective etchants (e.g., as discussed with respect to <FIG>). In some embodiments, spacers <NUM> are deposited within sections of the sidewalls of the opening <NUM>, e.g., such that the spacers <NUM> may block the conductive layer <NUM> (and may also optionally at least partially or fully block through the insulating layer 108c) from the opening <NUM>.

Merely as an example (and although not illustrated in the figures), the opening <NUM> may be initially extended through the ILD <NUM> and the layers 104c and 108c (but not though the layers 104d, 108b). Subsequently, the spacers <NUM> may be formed through the opening <NUM> on the sidewalls of the ILD <NUM> and the layers 104c, 108c, 104d. Sections of the spacers <NUM> may then be selectively etched from the sidewalls of the ILD <NUM> and the hard mask layer <NUM>, but other sections of the spacers <NUM> may remain on the sidewalls of the layers 108c, 104c. Then the opening <NUM> may be extended through the layers 104d, 108b, and possibly through the ILD <NUM>, as illustrated in <FIG>. In some embodiments, spacers <NUM> and <NUM> are deposited within sections of the sidewalls of the openings <NUM> and <NUM>, respectively.

Referring now to <FIG>, sacrificial material <NUM>, <NUM>, and <NUM> may be respectively deposited in the openings <NUM><NUM>, and <NUM>, and the conformal hard mask layer <NUM> may be removed (e.g., may be etched), thereby recovering the opening <NUM>.

Referring now to <FIG>, a conformal hard mask layer <NUM> may be deposited on the hard mask layer <NUM>, e.g., using thin-film deposition methods, such as plating, chemical vapor deposition, atomic layer deposition, and/or the like. The conformal hard mask layer <NUM> may then be etched. In some embodiments, the conformal hard mask layer <NUM> are deposited in the opening <NUM>, as well as the small openings adjacent to the sacrificial materials <NUM>, <NUM>, <NUM>, and <NUM>. However, the width a3 of the opening <NUM> may be larger than the width of the openings adjacent to the sacrificial materials <NUM>, <NUM>, <NUM>, and <NUM>. Thus, the conformal hard mask layer <NUM> may form a ridge, recess or low depth region within the opening <NUM>. Etching of the conformal hard mask layer <NUM> may expose the ILD <NUM> through the opening <NUM>, as illustrated in <FIG>.

Referring now to <FIG>, the ILD <NUM> may be selectively etched through the opening <NUM>. The etching in <FIG> may be performed using any appropriate etching technique, e.g., dry etch, wet chemical etch, etc., using one or more selective etchants (e.g., as discussed with respect to <FIG>). In some embodiments, the opening <NUM> is now in contact with (and possibly partially or fully extending through, although not illustrated in the figures) the conductive layer 104c.

Referring now to <FIG>, the sacrificial materials <NUM>, <NUM>, <NUM>, and <NUM> may be removed by an appropriate selective etching process. In some embodiments, the conformal hard mask layer <NUM> is also removed, as illustrated in <FIG>.

Referring now to <FIG>, the openings <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are respectively filled with conductive material (e.g., metal) to form vias <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. The device <NUM> in <FIG> is similar to the device <NUM> of <FIG>.

Thus, referring now to <FIG>, in some embodiments, the device <NUM> comprises a high voltage capacitor formed using the MIM 100a, and an adjacent low voltage capacitor formed using the MIM 100b. For example, a capacitor may be formed between the conductive layer 104b and the electrode <NUM> of the MIM 100a. As the insulating layer 108b may be relatively thick (e.g., having height higher than the height of the insulating layer 108c), the capacitor developed between the via <NUM> and the electrode <NUM> of the MIM 100a may be able to handle relatively higher voltage (e.g., compared to that of the MIM 100b). Similarly, a capacitor may be formed between the conductive layers 104c and 104d. As the insulating layer 108c may be relatively thin (e.g., having height lower than the height of the insulating layer 108b, as a result of which the insulating layers 108b may have a higher breakdown voltage than one or both of the insulating layers 108a and 108c), the capacitor developed between the conductive layers 104c and 104d of the MIM 100b may be able to handle relatively lower voltage (e.g., compared to that of the MIM 100a). In some embodiments, a capacitance per unit area of the capacitor of the MIM 100a is lower than a capacitance per unit area of second capacitor of the MIM 100b.

<FIG> is flow diagrams illustrating a method <NUM> of forming the device <NUM> of <FIG> comprising the MIM 100a with the high voltage capacitor and the MIM 100b with the low voltage capacitor, according to some embodiments. Although the blocks in the flowchart with reference to <FIG> are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in <FIG> may be optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

In some embodiments, the method <NUM> comprises, at <NUM>, forming a first interleaved stack of a first plurality of layers (e.g., conductive layers 104a and 104b) comprising conductive material and a second plurality of layers (e.g., insulating layer 108a and 108b) comprising insulating material. The method further comprises, at <NUM>, forming a second interleaved stack of a third plurality of layers (e.g., conductive layers 104c and 104d) comprising conductive material and a fourth plurality of layers comprising insulating material (e.g., insulating layer 108c and 108b).

The method further comprises, at <NUM>, forming a first via (e.g., via <NUM>) through one or more layers of the first stack, the first via coupled to two of the first plurality of layers. The method further comprises, at <NUM>, forming a second via (e.g., via <NUM>) through one or more layers of the second stack, the second via isolated from a first layer (e.g., conductive layer 104c) of the third plurality of layers and coupled to a second layer (e.g., conductive layer 104d) of the third plurality of layers. The method further comprises, at <NUM>, forming a third via (e.g., via <NUM>) that is coupled to the first layer of the third plurality of layers and isolated from the second layer of the third plurality of layers.

In some embodiments, forming the first via comprises: forming an ILD (e.g., ILD <NUM>) over the first interleaved stack and the second interleaved stack; forming a hard mask layer (e.g., hard mask layer <NUM>) over the ILD, the hard mask layer comprising: a first opening (e.g., opening <NUM>) for formation of the first via, a second opening (e.g., opening <NUM>) for formation of the second via, and a third opening (e.g., opening <NUM>) for formation of the third via; depositing a conformal hard mask layer (e.g., conformal hard mask layer <NUM>) over the hard mask layer; etching the conformal hard mask layer such that: the conformal hard mask layer does not fully cover the first opening, and the ILD is exposed through the first opening, and the conformal hard mask layer substantially covers the second and third openings, and the ILD is not exposed through the second and third openings (e.g., as illustrated in <FIG>); and selectively etching the ILD and the first interleaved stack to extend the first opening, without affecting the second or third openings (e.g., as illustrated in <FIG>), wherein the first via is formed in the extended first opening.

<FIG> illustrates a computing device or a SoC (System-on-Chip) <NUM> comprising a device (e.g., device <NUM> of <FIG>) including a MIM (e.g., the MIM 100a) with a high voltage capacitor and a MIM (e.g., the MIM 100b) with a low voltage capacitor, according to some embodiments. It is pointed out that those elements of <FIG> having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In some embodiments, computing device <NUM> represents an appropriate computing device, such as a computing tablet, a mobile phone or smart-phone, a laptop, a desktop, an IOT device, a server, a set-top box, a wireless-enabled e-reader, or the like. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device <NUM>.

In some embodiments, computing device <NUM> includes a first processor <NUM>. The various embodiments of the present disclosure may also comprise a network interface within <NUM> such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

In one embodiment, processor <NUM> can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor <NUM> include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device <NUM> to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, computing device <NUM> includes audio subsystem <NUM>, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device <NUM>, or connected to the computing device <NUM>. In one embodiment, a user interacts with the computing device <NUM> by providing audio commands that are received and processed by processor <NUM>.

Display subsystem <NUM> represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device <NUM>. Display subsystem <NUM> includes display interface <NUM>, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface <NUM> includes logic separate from processor <NUM> to perform at least some processing related to the display. In one embodiment, display subsystem <NUM> includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller <NUM> represents hardware devices and software components related to interaction with a user. I/O controller <NUM> is operable to manage hardware that is part of audio subsystem <NUM> and/or display subsystem <NUM>. Additionally, I/O controller <NUM> illustrates a connection point for additional devices that connect to computing device <NUM> through which a user might interact with the system. For example, devices that can be attached to the computing device <NUM> might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller <NUM> can interact with audio subsystem <NUM> and/or display subsystem <NUM>. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device <NUM>. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem <NUM> includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller <NUM>. There can also be additional buttons or switches on the computing device <NUM> to provide I/O functions managed by I/O controller <NUM>.

In one embodiment, I/O controller <NUM> manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device <NUM>. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

In one embodiment, computing device <NUM> includes power management <NUM> that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem <NUM> includes memory devices for storing information in computing device <NUM>. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem <NUM> can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device <NUM>. In one embodiment, computing device <NUM> includes a clock generation subsystem <NUM> to generate a clock signal.

Elements of embodiments are also provided as a machine-readable medium (e.g., memory <NUM>) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory <NUM>) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

Connectivity <NUM> includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device <NUM> to communicate with external devices. The computing device <NUM> could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Connectivity <NUM> can include multiple different types of connectivity. To generalize, the computing device <NUM> is illustrated with cellular connectivity <NUM> and wireless connectivity <NUM>. Cellular connectivity <NUM> refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) <NUM> refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

Peripheral connections <NUM> include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device <NUM> could both be a peripheral device ("to" <NUM>) to other computing devices, as well as have peripheral devices ("from" <NUM>) connected to it. The computing device <NUM> commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device <NUM>. Additionally, a docking connector can allow computing device <NUM> to connect to certain peripherals that allow the computing device <NUM> to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, the computing device <NUM> can make peripheral connections <NUM> via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

In some embodiments, the device <NUM> (e.g., comprising the MIM 100a and/or the MIM 100b, as discussed with respect to <FIG>) may be used as a high voltage capacitor and a low voltage capacitor in any appropriate component of the computing device <NUM>. The device <NUM> may be formed, e.g., as discussed with respect to <FIG>. In some embodiments, the device <NUM> may be used for any appropriate application of the computing device <NUM>, e.g., where one or more capacitors may be used (e.g., may be used in the processor <NUM>, in a memory of the memory subsystem <NUM>, or in another component).

While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

Claim 1:
An integrated circuit (IC) structure, comprising:
a first stack (203a) comprising a lower, a middle, and an upper layer of conductive material (<NUM>) with insulator layers (<NUM>) therebetween, wherein a first of the insulator layers has a lower breakdown voltage than a second of the insulator layers;
a second stack (203b) comprising at least the middle and upper layers of conductive material with one of the insulator layers therebetween;
a first via (<NUM>) comprising conductive material and over the first stack, wherein the first via is in contact with the upper and middle layers that have the first of the insulator layers therebetween; and
a second via (<NUM>) comprising conductive material and over the second stack,
wherein the second via extends through the upper layer and is in contact with the middle layer, the second via isolated from a sidewall of the upper layer by a spacer (<NUM>).