Patent Description:
<CIT> describes a method and system to control crosstalk among qubits on a chip. The method includes placing two or more components symmetrically on the chip, the chip including the qubits, and driving two or more ports symmetrically to control the crosstalk based on controlling coupling of chip mode frequencies and qubit frequencies.

<CIT> describes a quantum device that includes: a substrate; and at least three co-planar structures arranged on a surface of the substrate, each co-planar structure, of the at least three co-planar structures, including a superconductor, in which a first effective dielectric constant between a first co-planar structure and a second co-planar structure that is a nearest neighbor to the first co-planar structure is above a first threshold, a second effective dielectric constant between the first co-planar structure and a third co-planar structure that is a next nearest neighbor to the first so-planar structure is less than a second threshold, and the second threshold is less than the first threshold.

Embodiments of the invention are defined by the appended dependent claims.

The present disclosure relates to reducing parasitic capacitance in qubit systems.

A qubit system includes an array of multiple qubits, including, e.g., qubits arranged in, for instance, multiple rows and multiple columns. The qubit array may be used to implement quantum computation algorithms. In some implementations, these algorithms may require coupling between neighboring qubits, such as "nearest neighbor" qubits, which include, e.g., qubits that are nearest together in adjacent rows or adjacent columns of a rectangular array of qubits. In these algorithms, it may be required that there is negligible coupling between qubits other than "nearest neighbor" qubits, for example "next nearest neighbor" qubits and between the pairs of qubits which are farther from each other than "nearest neighbor" and "next nearest neighbor" qubits. However, due to proximity, undesired capacitive parasitic coupling may also occur between other qubits within the array, such as between "next nearest neighbor" qubits, which include, e.g., qubits on the array diagonals in a rectangular array of qubits. and this undesired capacitive parasitic coupling may have a non-negligible magnitude to the extent that it affects performing quantum computation algorithms. Such parasitic coupling may be present if it is desired from the system design that some of the neighboring qubits, within a certain distance range where capacitive coupling is non-negligible, are ideally not coupled to one another. Therefore, in such a design, capacitive coupling between qubits are inherently present. Such parasitic coupling may prohibit running large-scale quantum computation algorithms with many qubits. To prevent the parasitic coupling, a particular arrangement of qubits in an array is disclosed. This arrangement reduces or effectively nulls the parasitic coupling using the symmetry configuration and arrangement of the qubits within the array.

<FIG> illustrates an example array <NUM> of qubits for a qubit system not according to the claimed invention. The array <NUM> includes multiple qubits, e.g., qubits <NUM>-<NUM>, arranged in multiple rows, e.g., a first row ROW1 and a second row ROW2, and multiple columns, e.g., a first column COL1 and a second column COL2. The numbers of qubits, rows, and columns are not limited to the numbers illustrated in <FIG> and can include any suitable numbers of qubits, rows, and columns in various implementations. Similarly, the qubits <NUM>-<NUM> can be any suitable types of qubits including Xmon qubits, transmon qubits, fluxmon qubits, and spin qubits, among others. In some implementations, the qubits <NUM>-<NUM> can be differential qubits. As such, none of the nodes of the qubits <NUM>-<NUM> shares a common ground with another node of any of the qubits.

Each qubit of the qubits <NUM>-<NUM> can include two electrodes arranged in parallel. For example, the first qubit <NUM> can include a first electrode <NUM> and a second electrode <NUM>, the second qubit <NUM> can include a first electrode <NUM> and a second electrode <NUM>, the third qubit <NUM> can include a first electrode <NUM> and a second electrode <NUM>, and the fourth qubit <NUM> can include a first electrode <NUM> and a second electrode <NUM>. In this implementation, the second qubit <NUM> or the third qubit <NUM> may be identified as the "nearest neighbor" qubit of the first qubit <NUM>. The fourth qubit <NUM> that is diagonally located from the first qubit <NUM> may be identified as the "next nearest neighbor" qubit of the first qubit <NUM>. As another example, the first qubit <NUM> or the fourth qubit <NUM> may be identified as the "nearest neighbor" qubit of the second qubit <NUM>. The third qubit <NUM> that is diagonally located from the second qubit <NUM> may be identified as the "next nearest neighbor" qubit of the second qubit <NUM>.

In some implementations, the qubits <NUM>-<NUM> are not coupled to common ground. That is, electrodes of each qubit of the qubits <NUM>-<NUM> are coupled to different nodes that have respective potential values. For example, the second electrode <NUM> of the first qubit <NUM> is coupled to a first node that has a first potential value and the second electrode <NUM> of the fourth qubit <NUM> is coupled to a second node rather than the second electrode <NUM> and the second electrode <NUM> being coupled to the common ground.

Each qubit includes multiple co-planar waveguide arms (e.g., <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) connected to the electrodes and separated from a ground plane <NUM>. These co-planar waveguide arms will be explained in more detail later. In particular, each qubit of the qubits <NUM>-<NUM> can be coupled to four co-planar waveguide arms. For example, the first electrode <NUM> of the first qubit <NUM> can be coupled to the co-planar waveguide arms <NUM>, <NUM> and the second electrode <NUM> of the first qubit <NUM> can be coupled to the co-planar waveguide arms <NUM>, <NUM>. In some implementations, the co-planar waveguide arms <NUM>, <NUM> can extend along orthogonal directions and the co-planar waveguide arms <NUM>, <NUM> can extend along orthogonal directions. In some other implementations, the co-planar waveguide arms <NUM>, <NUM> can extend along non-orthogonal directions and the co-planar waveguide arms <NUM>, <NUM> can extend along non-orthogonal directions.

The second electrode <NUM> of the second qubit <NUM> can be coupled to the co-planar waveguide arms <NUM>, <NUM> and the second electrode <NUM> of the second qubit <NUM> can be coupled to the co-planar waveguide arms <NUM>, <NUM>. In some implementations, the co-planar waveguide arms <NUM>, <NUM> can extend along orthogonal directions and the co-planar waveguide arms <NUM>, <NUM> can extend along orthogonal directions. In some other implementations, the co-planar waveguide arms <NUM>, <NUM> can extend along non-orthogonal directions and the co-planar waveguide arms <NUM>, <NUM> can extend along non-orthogonal directions.

The first electrode <NUM> of the third qubit <NUM> can be coupled to the co-planar waveguide arms <NUM>, <NUM> and the second electrode <NUM> of the third qubit <NUM> can be coupled to the co-planar waveguide arms <NUM>, <NUM>. In some implementations, the co-planar waveguide arms <NUM>, <NUM> can extend along orthogonal directions and the co-planar waveguide arms <NUM>, <NUM> can extend along orthogonal directions. In some other implementations, the co-planar waveguide arms <NUM>, <NUM> can extend along non-orthogonal directions and the co-planar waveguide arms <NUM>, <NUM> can extend along non-orthogonal directions.

The first electrode <NUM> of the fourth qubit <NUM> can be coupled to the co-planar waveguide arms <NUM>, <NUM> and the second electrode <NUM> of the fourth qubit <NUM> can be coupled to the co-planar waveguide arms <NUM>, <NUM>. In some implementations, the co-planar waveguide arms <NUM>, <NUM> can extend along orthogonal directions and the co-planar waveguide arms <NUM>, <NUM> can extend along orthogonal directions. In some other implementations, the co-planar waveguide arms <NUM>, <NUM> can extend along non-orthogonal directions and the co-planar waveguide arms <NUM>, <NUM> can extend along non-orthogonal directions.

In some implementations, the qubits <NUM>-<NUM> of the array <NUM> may be surrounded by the ground plane <NUM>. The electrodes and co-planar waveguides may be separated from the ground plane <NUM> by gaps <NUM> which expose a substrate surface, e.g., a substrate surface on which the electrodes, co-planar waveguides and ground plane are formed. The substrate may include a dielectric substrate such as, e.g., silicon or sapphire. The electrodes, the co-planar waveguides and the ground plane may be formed from a superconductor material that exhibits superconducting properties at temperatures at or below a critical temperature, such as aluminum, niobium, or titanium nitride. Other superconductors may be used as well.

In some other implementations, the qubits and the co-planar waveguides are located in a different plane from a ground plane. For example, where multiple qubits and multiple co-planar waveguide arms are located in a qubit plane, the ground plane can be formed in parallel to the qubit plane. In this implementation, the ground plane can be coupled to the qubit plane through interconnectors, e.g., superconducting interconnectors.

<FIG> illustrates a SQUID <NUM> of a qubit <NUM> in the array <NUM> described with reference to <FIG>. For example, the fourth qubit <NUM> includes the SQUID <NUM> that is located between the first electrode <NUM> and the second electrode <NUM>. The SQUID <NUM> includes a first junction <NUM> and a second junction <NUM>. Each of the first junction <NUM> and the second junction <NUM> is coupled to both the first electrode <NUM> and the second electrode <NUM>. In some implementations, the junctions <NUM>, <NUM> can be Josephson junctions.

Referring back to <FIG>, during operation of a quantum computational system employing the qubit array <NUM>, the qubit array <NUM> may be used to implement quantum computation algorithms. In certain cases, these algorithms may require coupling between nearest neighbor qubits, e.g., qubits that are closest together in adjacent rows or adjacent columns of the array, such as coupling between qubit <NUM> and qubit <NUM>, or between qubit <NUM> and qubit <NUM>. However, due to proximity, charge present in one qubit may lead to charge induced in another qubit to which coupling is not desired. For example, charge present in qubit <NUM> may lead to undesired charge in, and thus parasitic capacitive coupling with, a next nearest neighbor qubit on the array diagonals, such as qubit <NUM>. Such parasitic coupling may adversely affect the operation of the algorithm and the quantum computational system as a whole. The parasitic coupling is described in greater detail with reference to <FIG>.

In some implementations, two electrodes of one qubit may be floating. That is, different AC voltages can be respectively applied to two electrodes of one qubit. For example, a first AC voltage can be applied to the first electrode <NUM> and a second AC voltage can be applied to the second electrode <NUM>. In some implementations, the first AC voltage can have a higher magnitude than the second AC voltage. In some implementations, the second AC voltage can have a higher magnitude than the first AC voltage. If different AC voltages are respectively applied to the two electrodes of one qubit, different charges are induced in the two electrodes. This charge difference can be coupled to the differential mode of the qubit. That is, charges induced in an electrode of one qubit can induce charges in electrodes of other qubits. For example, charges in the first electrode <NUM> of the first qubit <NUM> can induce charges in the first electrode <NUM> of the second qubit <NUM> or in the first electrode <NUM> of the fourth qubit <NUM>.

<FIG> is a schematic illustrating parasitic capacitive coupling between on-diagonal qubits within an array, such as qubit <NUM> and qubit <NUM> of <FIG>. As described above, where the qubits <NUM>-<NUM> are not coupled to common ground, when a charge is provided on an electrode (e.g., electrode <NUM>) of the first qubit <NUM>, a corresponding charge is induced in both electrodes (e.g., electrodes <NUM>, <NUM>) of the on-diagonal qubit <NUM>. In particular, since a distance D1 between the second electrode <NUM> and the first electrode <NUM> is different from a distance D2 between the second electrode <NUM> and the second electrode <NUM>, a different amount of charge is induced on each of electrode <NUM>, <NUM>. For example, a larger charge having a greater magnitude ("Q") may be induced on electrode <NUM>, and a smaller charge having a smaller magnitude ("q") may be induced on electrode <NUM>. The coupling between the qubit <NUM> and the qubit <NUM> then scales with the charge difference between the induced charges on each of the electrodes within the on-diagonal qubit <NUM>. That is, a first capacitance between the second electrode <NUM> and the first electrode <NUM> is different from a second capacitance between the second electrode <NUM> and the second electrode <NUM>. As a result, a charge in the second electrode <NUM> induces a charge difference between the first electrode <NUM> and the second electrode <NUM>. This charge difference is not cancelled by a charge in the first electrode <NUM> due to the difference in capacitance mentioned above, causing undesired parasitic coupling between the first qubit <NUM> and the fourth qubit <NUM>. For example, referring back to <FIG>, where a distance D between one qubit and its nearest qubit is <NUM>, the parasitic capacitance between the first qubit <NUM> and the fourth qubit <NUM> amounts to about <NUM> aF and the parasitic capacitance between the second qubit <NUM> and the third qubit <NUM> amounts to about <NUM> aF.

To reduce the parasitic capacitance, the orientation of the next nearest neighbor qubit may be modified so that there is little or no difference in charge between the electrodes of the next nearest neighbor qubit. Since the capacitive coupling scales with the difference in charge, reducing this difference may be relied on to reduce the amount of parasitic coupling. <FIG> illustrates one example of an array where the orientation of the next nearest neighbor qubit is modified.

<FIG> illustrates an example array <NUM> of qubits for a qubit system that may be used to reduce parasitic coupling to undesired qubits. The array <NUM> in <FIG> is the same as or similar to the array <NUM> in <FIG> except the following differences. The array <NUM> includes multiple qubits, e.g., qubits <NUM>-<NUM>, that are arranged in multiple rows, e.g., a first row ROW1a and a second row ROW2a, and multiple columns, e.g., a first column COL1a and a second column COL2a. The qubits <NUM>-<NUM> are differential qubits. As such, none of the nodes of the qubits <NUM>-<NUM> shares a common ground with another node of any of the qubits. The numbers of qubits, rows, and columns are not limited to the numbers illustrated in <FIG>. The array <NUM> can include any suitable numbers of qubits, rows, and columns in various implementations. Each qubit of the qubits <NUM>-<NUM> shown in <FIG> is referred to as a "differential Xmon qubit. " However, the qubits <NUM>-<NUM> can be any suitable types of qubits including Xmon qubits, transmon qubits, fluxmon qubits, flux qubits, gatemon qubits, gmon qubits, phase qubits, and spin qubits. In particular, the qubits <NUM>-<NUM> can be any types of qubits where parasitic coupling can occur between two of those qubits.

Similar to the array in <FIG>, each qubit of the qubits <NUM>-<NUM> includes two electrodes arranged in parallel. The first qubit <NUM> includes a first electrode <NUM> and a second electrode <NUM>, the second qubit <NUM> includes a first electrode <NUM> and a second electrode <NUM>, the third qubit <NUM> includes a first electrode <NUM> and a second electrode <NUM>, and the fourth qubit <NUM> includes a first electrode <NUM> and a second electrode <NUM>. In this implementation, the second qubit <NUM> or the third qubit <NUM> may be identified as the "nearest neighbor" qubit of the first qubit <NUM>. The fourth qubit <NUM> that is diagonally located from the first qubit <NUM> may be identified as the "next nearest neighbor" qubit of the first qubit <NUM>. As another example, the first qubit <NUM> or the fourth qubit <NUM> may be identified as the "nearest neighbor" qubit of the second qubit <NUM>. The third qubit <NUM> that is diagonally located from the second qubit <NUM> may be identified as the "next nearest neighbor" qubit of the second qubit <NUM>. Similar to the array in <FIG>, each of the qubits <NUM>-<NUM> also includes four co-planar waveguide arms (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>).

<FIG> illustrates a SQUID <NUM> of a qubit <NUM> in the array <NUM> described with reference to <FIG>. For example, the fourth qubit <NUM> includes a SQUID <NUM> that is located between the first electrode <NUM> and the second electrode <NUM>. The SQUID <NUM> includes a first junction <NUM> and a second junction <NUM>. Each of the first junction <NUM> and the second junction <NUM> is coupled to both the first electrode <NUM> and the second electrode <NUM>. In some implementations, the junctions <NUM>, <NUM> can be Josephson junctions. Referring again to <FIG>, the electrodes and co-planar waveguide of the qubits <NUM>-<NUM> are separated from a ground plane <NUM> by gaps <NUM>. The electrodes, ground planes, and co-planar waveguide arms shown in <FIG> may be formed from superconductor thin films, such as aluminum, niobium, or titanium nitride, among other superconductors. The qubits <NUM>-<NUM> and ground planes <NUM> in <FIG> are formed on a dielectric substrate such as, e.g., silicon or sapphire.

In some implementations, the qubits are located in a different plane from a ground plane. For example, where multiple qubits and multiple co-planar waveguide arms are located in a qubit plane, the ground plane can be formed in parallel to the qubit plane. In this implementation, the ground plane can be coupled to the qubit plane through interconnectors, e.g., superconducting interconnectors.

In implementation shown in <FIG>, electrodes of two diagonally-located qubits are arranged in perpendicular directions. The electrodes <NUM>, <NUM> of the first qubit <NUM> are arranged in a first direction and the electrodes <NUM>, <NUM> of the fourth qubit <NUM> that is a diagonally-located qubit of the first qubit <NUM> are arranged in a second direction that is perpendicular to the first direction such that the distance D3 between the second electrode <NUM> and the first electrode <NUM> is the same as the distance D4 between the second electrode <NUM> and the second electrode <NUM>.

To prevent the undesired parasitic coupling between the first qubit <NUM> and the fourth qubit <NUM>, the qubits <NUM>-<NUM> are not coupled to the same common ground. That is, electrodes of each qubit of the qubits <NUM>-<NUM> are coupled to different nodes that have respective potential values. For example, the second electrode <NUM> is coupled to a first node that has a first potential value and the second electrode of the fourth <NUM> of the fourth qubit <NUM> is coupled to a second node rather than the second electrode <NUM> and the second electrode <NUM> being coupled to the common ground. In some implementations, as described above, two electrodes of one qubit may be floating. That is, different AC voltages can be respectively applied to two electrodes of one qubit. If different AC voltages are respectively applied to the two electrodes of one qubit, different charges are induced in the two electrodes. This charge difference can be coupled to the differential mode of the qubit. That is, charges induced in an electrode of one qubit can induce charges in electrodes of other qubits. For example, charges in the first electrode <NUM> of the first qubit <NUM> can induce charges in the first electrode <NUM> of the second qubit <NUM> or in the first electrode <NUM> of the fourth qubit <NUM>.

During operation of a quantum computational system employing the qubit array <NUM>, due to proximity, charge present in one qubit may lead to charge induced in another qubit to which coupling is not desired. For example, charge present in the qubit <NUM> may lead to an induced charge in a next nearest neighbor qubit on the array diagonals, such as the qubit <NUM>. However, due to the modified positioning and arrangement of the electrodes within the qubit <NUM> relative to the qubit <NUM>, parasitic coupling between the qubit <NUM> and the qubit <NUM> may be reduced and even effectively nulled.

<FIG> is a schematic illustrating parasitic capacitive coupling between on-diagonal qubits within an array, such as the qubit <NUM> and the qubit <NUM> of <FIG>. Because the qubits are not operating in a common ground configuration, where, e.g., one electrode from each qubit is tied to the same ground potential, a same magnitude of charge (+Q) is induced in both the first electrode <NUM> and in the second electrode <NUM> of the fourth qubit <NUM> when a charge is provided to the electrode <NUM> of the first qubit <NUM>. An identical charge is induced in the electrodes <NUM>, <NUM> because both of the electrodes <NUM>, <NUM> are positioned at a same distance (D4 = D3) from the electrode <NUM> and are arranged to have the same orientation relative to the electrode <NUM>. Likewise, a charge in the first electrode <NUM> will induce equal charges in the electrodes <NUM> and <NUM>. Given that the coupling between a first qubit (e.g., qubit <NUM>) and a second qubit (e.g., <NUM>) scales with the charge difference between the induced charges on each of the electrodes within the second qubit, the parasitic capacitance between qubit <NUM> and qubit <NUM> is reduced or effectively nulled when the induced charges are the same magnitude and sign. Hence, the differential mode of the first qubit <NUM> does not couple to the differential mode of the fourth qubit <NUM>. In some implementations, the modified array of qubits shown in <FIG> may lead to a reduction in parasitic capacitance between qubits by about <NUM>% compared to the array of qubits shown in <FIG>. For example, where a distance D' between one qubit and its nearest qubit is <NUM>, the parasitic capacitance between the first qubit <NUM> and the fourth qubit <NUM> can be <NUM> aF. For the same or similar reasons, parasitic coupling between the second qubit <NUM> and the third qubit <NUM> can be reduced or effectively nulled. For example, the parasitic capacitance between the second qubit <NUM> and the third qubit <NUM> can be <NUM> aF.

In quantum algorithms, these unwanted parasitic couplings lead to increased error rates in other adjacent qubits. In particular, the parasitic capacitive coupling manifests itself as a state-dependent frequency shift of the affected qubits, which leads to phase error in gate operations. The corresponding error on a single qubit due to this interaction, so called ZZ error value, increases during the duration of each gate operation. Therefore, comparing to the array <NUM>, the array <NUM> has a lower ZZ error value. For example, where CouplingStrength represents the coupling strength between two diagonally-located qubits, Δ represents the detuning between two diagonally-located qubits, and, η represents the nonlinearity, the ZZ Interaction can be expressed as:
<MAT>.

Where t represents the time, the ZZ Error can be expressed as:
<MAT>.

For example, comparing to the ZZ Error of the array <NUM>, the ZZ Error of the array <NUM> can be reduced by about <NUM>%.

Although the array <NUM> reduces or effectively nulls the parasitic capacitance between diagonally-located qubits, the array <NUM> does not change the coupling capacitance between one qubit and its nearest neighbor qubit comparing to the array <NUM>. For example, Table <NUM> shows the coupling capacitance between one qubit and its nearest qubit for the array <NUM> described with reference to <FIG> and Table <NUM> shows the coupling capacitance between one qubit and its nearest qubit for the array <NUM> described with reference to <FIG>.

Table <NUM> and Table <NUM> show that the array <NUM> does not change the coupling capacitance between one qubit and its nearest qubit comparing to the array <NUM>. Since the coupling strength corresponds to coupling capacitance, the array <NUM> does not change coupling strength between one qubit and its nearest qubit comparing to the array <NUM>. For example, where the first qubit is tuned to a frequency between <NUM>-<NUM>, the coupling strength between the first qubit <NUM> and the second qubit <NUM> that is located the nearest from the first qubit <NUM> can be between <NUM>-<NUM> and the coupling strength between the first qubit <NUM> and the fourth qubit <NUM> that is diagonally located from the first qubit <NUM> can be between <NUM>-<NUM>. For example, a coupling capacitance of <NUM>. 57fF equals roughly to a coupling strength of <NUM> at an operating frequency of <NUM>.

In some implementations, to fabricate a qubit, such as the qubits in array <NUM> or array <NUM>, multiple layers may be required to form the SQUID junctions. For example, a first layer of superconductor material may be deposited for form a first contact of the junctions, followed by oxidation in select regions to form the junction insulator, and then a second layer of superconductor material may be deposited to form the second contact of the junction. To maintain low loss surfaces, the foregoing deposition and oxidation process is typically performed without breaking vacuum. The condition that vacuum may not be broken therefore may require patterning and application of a single mask to define the features of the qubit prior to deposition and oxidation. To avoid forming the first superconductor layer and the second superconductor layer in a single deposition step, however, an angled shadow deposition process may be used. In an angled shadow deposition process, a first superconductor layer is deposited by exposing the substrate and patterned mask to a first flux of superconductor material (e.g., using physical vapor deposition) at an oblique angle relative to the substrate surface. Portions of the mask may be relied on to block (i.e., effectively act as a shadow mask) deposition of the superconductor in regions where the second superconductor layer is to be performed. Following oxidation, the substrate is rotated (e.g., <NUM> degrees) and a second superconductor layer is deposited by exposing the device and patterned mask to a second flux of superconductor material again at an oblique angle relative to the substrate surface. Portions of the mask again may be relied on to block deposition of the superconductor material, but this time from being deposited in regions where the first superconductor layer has been formed. An advantage of the subject matter of the present disclosure is that even though the arrangement of the on-diagonal qubits are modified relative to one another, the angled shadow deposition process still may be used. That is, there is no need to change any steps of the qubit fabrication process other than the mask design. Thus, a substantial reduction in parasitic capacitance may be achieved with no increased fabrication cost.

Implementations of the quantum subject matter and quantum operations described in this specification can be implemented in suitable quantum circuitry or, more generally, quantum computational systems, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term "quantum computational systems" may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, topological quantum computers, or quantum simulators.

The terms quantum information and quantum data refer to information or data that is carried by, held or stored in quantum systems, where the smallest non-trivial system is a qubit, e.g., a system that defines the unit of quantum information. It is understood that the term "qubit" encompasses all quantum systems that may be described exactly or suitably approximated as a two-level system in the corresponding context. By way of example, such systems can include atoms, electrons, photons, trapped or un-trapped ions, atomic nuclei, color centers, topological qubits, quantum dots, Bose-Einstein condensates, or superconducting qubits. In some implementations the computational basis states are identified with the ground and first excited states, however it is understood that other setups where the computational states are identified with higher level excited states are possible. It is understood that quantum memories are devices that can store quantum data for a long time with high fidelity and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

Quantum circuit elements (also referred to as quantum computing circuit elements) include circuit elements for performing quantum processing operations. That is, the quantum circuit elements are configured to make use of quantum-mechanical phenomena, such as superposition and entanglement, to perform operations on data in a non-deterministic manner. Certain quantum circuit elements, such as qubits, can be configured to represent and operate on information in more than one state simultaneously. Examples of superconducting quantum circuit elements include circuit elements such as quantum LC oscillators, qubits (e.g., flux qubits, phase qubits, or charge qubits), and superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC-SQUID), among others.

In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements can be configured to collectively carry out instructions of a computer program by performing basic arithmetical, logical, and/or input/output operations on data, in which the data is represented in analog or digital form. In some implementations, classical circuit elements can be used to transmit data to and/or receive data from the quantum circuit elements through electrical or electromagnetic connections. Examples of classical circuit elements include circuit elements based on CMOS circuitry, rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices and ERSFQ devices, which are an energy-efficient version of RSFQ that does not use bias resistors.

Fabrication of the circuit elements described herein can entail the deposition of one or more materials, such as superconductors, dielectrics and/or metals. Depending on the selected material, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among other deposition processes. Processes for fabricating circuit elements described herein can entail the removal of one or more materials from a device during fabrication. Depending on the material to be removed, the removal process can include, e.g., wet etching techniques, dry etching techniques, or lift-off processes. The materials forming the circuit elements described herein can be patterned using known lithographic techniques (e.g., photolithography or e-beam lithography).

During operation of a quantum computational system that uses superconducting quantum circuit elements and/or superconducting classical circuit elements, such as the circuit elements described herein, the superconducting circuit elements are cooled down within a cryostat to temperatures that allow a superconductor material to exhibit superconducting properties. A superconductor (alternatively superconducting) material can be understood as material that exhibits superconducting properties at or below a superconducting critical temperature. Examples of superconducting material include aluminum (superconductive critical temperature of <NUM> kelvin) and niobium (superconducting critical temperature of <NUM> kelvin). Accordingly, superconducting structures, such as superconducting traces and superconducting ground planes, are formed from material that exhibits superconducting properties at or below a superconducting critical temperature.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

Moreover, the separation of various components in the implementations described above should not be understood as requiring such separation in all implementations.

Claim 1:
A system comprising an array of qubits arranged on a two-dimensional substrate, each qubit of the array of qubits comprising a first electrode (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) corresponding to a first node and a second electrode (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) corresponding to a second node,
wherein, for a first qubit (<NUM>, <NUM>) in the array of qubits and a next nearest neighbor second qubit (<NUM>, <NUM>) in the array of qubits, the first qubit is positioned and oriented relative to the second qubit such that a charge present on the first qubit induces a same charge on each of the first node of the second qubit and the second node of the second qubit, such that coupling between the first qubit and the second qubit is reduced,
wherein each of the first electrode of the first qubit and the second electrode of the first qubit are parallel to one another along a first direction,
wherein the first electrode of the second qubit and the second electrode of the second qubit are parallel to one another along a second direction,
wherein the first direction is orthogonal to the second direction,
wherein the first qubit is positioned and oriented such that a distance between the first electrode of the first qubit and the first electrode of the second qubit is the same as the distance between the first electrode of the first qubit and the second electrode of the second qubit, and
wherein none of the nodes share a common ground.