Patent Description:
As microelectronic packaging structure design requires ever increasing input out (I/O) density, reduced z-height and reduction in form factor, power delivery requirements become increasingly challenging. Inductor structures coupled with such microelectronic packaging structures can exhibit lower efficiency, which can affect power delivery requirements.

<CIT> relates to a semiconductor device. In said application, magnetic material is arranged as layers of a layer stack of a semiconductor package, with a conductive trace that is placed between portions of the layers.

<CIT> relates to an inductor element and to a method for manufacturing an inductor element. The inductor element comprises multiple conductive layers that are each covered by magnetic material, with a resin layer being used to separate the magnetic material covering a conductive layer from an adjacent conductive layer.

<CIT> relates to a thin film magnet 3D inductor structure that is integrated within a semiconductor substrate of a die.

<CIT> relates to forming inductor and transformer structures with magnetic materials using damascene processing for integrated circuits. A seed layer and a magnetic material is formed in an opening by utilizing sputtering, reactive sputtering, electroplating, chemical vapor deposition (CVD), atomic layer deposition (ALD) or evaporation techniques.

<CIT> relates to a wiring board and method for manufacturing the same. The wiring board forms a package substrate. An electroless plating procedure is used to form a nickel film on two surfaces of a core substrate of the package substate and on an inner hole of a through hole.

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment.

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims.

As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of" or "one or more of' can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

Embodiments of methods of forming in-package inductor structures comprising selectively electroplated magnetic material, are described herein. In embodiments, the in-package inductor structures may be formed by incorporating electroplated magnetic alloys that may be selectively formed within the microelectronic package structures. The selectively electroplated magnetic material may be incorporated within both cored and coreless packages. The magnetic material of the in-package inductor structures of the embodiments herein may be selectively electroplated within plated through holes (PTH) of a cored package substrate and may be formed as a via in coreless package structures. Those structures may include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

Various implementations of the embodiments herein may be formed or carried out on a substrate, such as a package substrate. A package substrate may comprise any suitable type of substrate capable of providing electrical communications between a die, such as an integrated circuit (IC) die, and a next-level component to which an microelectronic package may be coupled (e.g., a circuit board). In another embodiment, the substrate may comprise any suitable type of substrate capable of providing electrical communication between an IC die and an upper IC package coupled with a lower IC/die package, and in a further embodiment a substrate may comprise any suitable type of substrate capable of providing electrical communication between an upper IC package and a next-level component to which an IC package is coupled.

<FIG> is a cross-sectional view of a package structure <NUM>, wherein the package structure <NUM> includes an in-package inductor structure. The in-package inductor structure includes an electroplated magnetic material that has been selectively formed within the substrate <NUM> of the package structure <NUM>. The substrate <NUM> may comprise a portion of a package substrate <NUM>. The substrate <NUM> may provide structural support for a die/device, in the embodiments, and may comprise a coreless substrate, in an embodiment. By way of example, in one embodiment, the substrate <NUM> may comprise a multi-layer substrate - including alternating layers of a dielectric/electrically insulating material <NUM> and conductive interconnect structures <NUM>, <NUM>.

The electrically insulating material may comprise such materials as an epoxy laminate, in an embodiment. For example, the substrate <NUM> may include electrically insulating layers composed of materials such as, phenolic cotton paper materials (e.g., FR-<NUM>), cotton paper and epoxy materials (e.g., FR-<NUM>), woven glass materials that are laminated together using an epoxy resin (FR-<NUM>), glass/paper with epoxy resin (e.g., CEM-<NUM>), glass composite with epoxy resin, woven glass cloth with polytetrafluoroethylene (e.g., PTFE CCL), or other polytetrafluoroethylene-based prepreg material.

Other types of substrates and substrate materials may also find use with the disclosed embodiments (e.g., ceramics, sapphire, glass, etc.). Further, according to one embodiment, a substrate may comprise alternating layers of dielectric material and metal that are built-up over a die itself - this process is sometimes referred to as a "bumpless build-up process. " Where such an approach is utilized, conductive interconnects may or may not be needed (as the build-up layers may be disposed directly over a die, in some cases).

The substrate <NUM> may include at least one conductive via structure <NUM>, disposed within dielectric portions <NUM> of the substrate <NUM>, according to embodiments. The substrate <NUM> may comprise a coreless package substrate in an embodiment, and may be free of a core structure. Build up layers disposed within the substrate <NUM> may include conductive interconnect structures <NUM>, <NUM> which may comprise vias <NUM>, such as microvias, for example, and conductive traces <NUM> disposed within the dielectric materials <NUM>. The substrate <NUM> may comprise any number of dielectric layers <NUM>, which may include any number of conductive interconnect structures <NUM>, <NUM> as appropriate for a particular application. Individual ones of the conductive interconnect structures <NUM>, <NUM> may comprise traces, trenches, routing layers, ground planes, power planes, re-distribution layers (RDLs), and/or any other appropriate electrical routing features. Although specific patterns of the conductive interconnect structures <NUM>, <NUM> are illustrated in <FIG>, such patterns are merely exemplary, and may vary according to the particular application.

A magnetic material <NUM>, that according to the invention is an electroplated magnetic material, may comprise a portion of an in-package inductor structure. The magnetic material <NUM> may comprise a portion of an embedded inductor structure, wherein conductive material may be patterned around the magnetic material to form embedded inductor structures of any desired geometry, which will be described further herein. In an embodiment, the magnetic material <NUM> incorporated in the embedded inductor structure may comprise at least a portion of a power distribution system that may supply power to a die <NUM> and/or to other components, devices, or systems coupled to the substrate <NUM>/package structure <NUM>. For example, the embedded magnetic inductor of the embodiments herein may form a portion of a voltage regulator coupled to a power supply for a coupled die. Integrating such magnetic inductor structures into the substrate <NUM> may eliminate the need for an external inductor, in some embodiments.

The magnetic material <NUM> may be disposed on surfaces of the interconnect structures <NUM>, <NUM>. For example, a magnetic material <NUM> is located on conductive structures <NUM>, <NUM>', and is disposed within the dielectric material <NUM> of the package substrate <NUM>, and may not be disposed on a first surface <NUM>, nor on a second surface <NUM> of the substrate <NUM>. That is, the magnetic material <NUM> may be completely embedded within the substrate <NUM>. The magnetic material <NUM> comprises a selectively formed electroplated magnetic material, which may be formed according to particular design requirements in any suitable location/locations within the substrate <NUM>, as will be further described herein. In an embodiment, the magnetic material <NUM> is formed on a conductive seed layer, such as on a copper seed layer, for example. The magnetic material <NUM> may comprise such materials as iron, nickel, cobalt, molybdenum, and combinations thereof. The magnetic material <NUM> may comprise magnetic materials possessing a high permeability and a low coercivity, and may comprise those materials that are suitable for use as an efficient in-package inductor, to be described further herein.

<FIG> depict embodiments of forming an in-package magnetic inductor structure, such as the magnetic inductor structure of <FIG>, for example. <FIG> depicts a cross sectional view of a portion of a substrate <NUM>, such as a portion of a package substrate <NUM>. The package substrate <NUM> may comprise a dielectric material <NUM>, for example, wherein build up layers may subsequently be formed thereon/therein. The package substrate <NUM> may be a portion of a PCB, an interposer, or the like. In some exemplary embodiments, the package substrate <NUM> portion may comprise a PCB in a multi-level board including a plurality of conductive trace levels laminated with glass-reinforced epoxy sheets (e.g., FR-<NUM>). The portion of the package substrate <NUM> may comprise a first surface <NUM> and a second surface <NUM>.

In <FIG>, a removal process <NUM>, such as a laser drilling process, for example, may be employed, wherein openings <NUM> are formed in the substrate <NUM>. In an embodiment, the openings <NUM> may be formed through the substrate <NUM>, wherein buildup materials may subsequently be formed on a first side <NUM> of the substrate <NUM> and/or on a second side <NUM> of the substrate <NUM>, in an embodiment. In <FIG>, a conductive material <NUM>, such as a copper material for example, may be formed within the openings <NUM> of the substrate portion <NUM>. Interconnect structures <NUM> comprising conductive material may be formed on terminal end portions of the conductive material <NUM>, wherein the conductive material <NUM> formed within the openings <NUM> may comprise conductive via structures, in an embodiment. Dry film resist (DFR) patterning may be utilized to form the conductive structures <NUM>, <NUM>, in an embodiment.

In <FIG>, a dielectric material <NUM>, such as any suitable dielectric build up material, for example, may be formed/laminated on the conductive interconnect structures <NUM> and on the first and second surfaces <NUM>, <NUM> of the substrate <NUM>. At least one opening <NUM> may be formed within the dielectric material <NUM>, wherein a surface of the conductive interconnect structure <NUM> may be exposed. The at least one opening <NUM> may be formed utilizing a laser drilling and de-smear processing, in an embodiment. The at least one opening may be formed in locations where an in-package inductor is to be formed within the substrate <NUM>.

In an embodiment, a seed layer (not shown) may be formed on the conductive structure <NUM>. The seed layer may comprise a thickness of about <NUM> to about <NUM> microns, and may be formed by an electroplating process, in an embodiment. In other embodiments, the seed layer may be formed by any suitable formation process, such as by a physical vapor deposition process, for example. The seed layer may comprise such materials as copper, titanium or nickel, and combinations thereof, and may serve to prepare the surface of the conductive structure <NUM> for the subsequent formation of a magnetic material within the opening <NUM>.

A magnetic material <NUM> is formed utilizing an electroplating process <NUM> on the conductive interconnect structure <NUM>, and within the opening <NUM> (<FIG>). In an embodiment, the magnetic material <NUM> is formed on a seed layer (not shown) disposed on a surface of the conductive interconnect structure <NUM>. In an embodiment, a length <NUM> of the conductive interconnect structure <NUM> may be greater than a length <NUM> of the magnetic material formed in the opening <NUM>. In another embodiment, the length <NUM> of the magnetic material <NUM> may be less than about <NUM> times the length <NUM> of the conductive interconnect structure <NUM>.

An electroplating bath utilized in the electroplating process <NUM> may comprise various chemical constituents. Such constituents/elements as cobalt, nickel, iron, molybdenum and combinations thereof, may be included in the electroplating bath. For example, the bath may comprise various materials such as iron, nickel, and alloys of nickel and iron. In an embodiment, the electroplating bath may comprise a Permalloy (<NUM>% nickel and <NUM> percent iron), and/or a Semipermalloy (<NUM>% Ni, <NUM>% Fe and <NUM>% Mo). In an embodiment, the magnetic material <NUM> formed by using the electroplating process <NUM> may comprise a hardness factor greater than about <NUM>-<NUM> times the hardness of softer magnetic materials, such as softer iron-silicon magnetic materials, for example. Additionally, the resistivity of the magnetic material produced by the electroplating process <NUM> may be modulated by varying the ratio of iron to nickel, according to particular design requirements for a specific in-package inductor structure.

In another embodiment, an electroplating bath utilized in the electroplating process <NUM> may comprise NiCl<NUM>. <NUM><NUM>O, FeCl<NUM>. <NUM><NUM>O, wherein the Ni<NUM>+/ Fe<NUM>+ mass ratio may be varied to obtain desired magnetic properties. Stabilizers may be utilized in the electroplating bath, and may include boric acid and a saccharin as stabilizer. The electroplating bath constituents may be optimized to obtain such magnetic alloys/structures as NiFeMo, Ni<NUM>Fe<NUM> and orthonol Ni<NUM>Fe<NUM> (<NPL>. The electroplating bath may comprise any suitable constituents to form a magnetic material according to inductor design requirements, however some exemplary bath constituents are disclosed herein.

In an embodiment, the electroplating bath may comprise <NUM> CoCl2, <NUM> NaCl, <NUM><NUM>BO<NUM> and <NUM> saccharine. In another embodiment, the electroplating bath may comprise <NUM> CoSO<NUM> +<NUM> NaSO<NUM>, <NUM><NUM>BO<NUM>, and <NUM> saccharine. In an embodiment, the electroplating bath may comprise <NUM> CoCl2, <NUM> NaCl, <NUM><NUM>BO<NUM>, <NUM> saccharine, and <NUM> L'ascorbic acid. In an embodiment, the electroplating bath may comprise <NUM> CoSO<NUM>, <NUM> NaSO<NUM> , <NUM><NUM>BO<NUM>, <NUM> saccharine, and <NUM> L'ascorbic acid. In an embodiment, the electroplating bath may comprise <NUM> NiCl2, <NUM> NaCl, <NUM><NUM>BO<NUM> and <NUM> saccharine. In an embodiment, the electroplating bath may comprise <NUM> NiSO<NUM>, <NUM> NaSO<NUM> , <NUM><NUM>BO<NUM>, and <NUM> saccharine. In an embodiment, the electroplating bath may comprise <NUM> FeCl<NUM>, <NUM> NaCl, <NUM><NUM>BO<NUM>, <NUM> saccharine and <NUM> L'ascorbic acid. In an embodiment, the electroplating bath may comprise <NUM> FeSO<NUM>, <NUM> NaSO<NUM>, <NUM><NUM>BO<NUM>, <NUM> saccharine and <NUM> L'ascorbic acid.

In an embodiment, the electroplating process may form a cobalt iron magnetic material, and the electroplating bath may comprise <NUM> CoCl<NUM>, xM FeCl<NUM>, <NUM> NaCl, <NUM><NUM>BO<NUM>, <NUM> saccharine, and <NUM> L'ascorbic acid. In an embodiment, the electroplating bath may comprise <NUM> CoSO<NUM>, xM FeCl<NUM>, <NUM> NaSO<NUM>, <NUM><NUM>BO<NUM>, <NUM> saccharine and <NUM> L'ascorbic acid. In an embodiment, the electroplating process may form a nickel cobalt magnetic material, and the electroplating bath may comprise <NUM> NiCl2, xMCoCl<NUM>, <NUM> NaCl , <NUM><NUM>BO<NUM> and <NUM> saccharine. In an embodiment, the electroplating bath may comprise <NUM> NiSO<NUM> xMCoCl<NUM>, <NUM> NaSO<NUM>, <NUM><NUM>BO<NUM>, and <NUM> saccharine. In an embodiment, the electroplating process may form a CoNiFe magnetic material, and the electroplating bath may contain <NUM> NiCl2, <NUM>. 15MCoCl<NUM>, yM FeCl<NUM>, <NUM> NaCl, <NUM><NUM>BO<NUM>, <NUM> saccharine and <NUM> L'ascorbic acid. In an embodiment, the electroplating process may form a CoNiFe magnetic material, and the electroplating bath may comprise <NUM> NiSO<NUM>, <NUM>. 15MCoSO<NUM>, yM FeSO<NUM>, <NUM>. 15MCoSO4, <NUM> NaSO<NUM>, <NUM><NUM>BO<NUM>, <NUM> saccharine and <NUM> L'ascorbic acid.

The magnetic material <NUM> may comprise a low coercivity, and a permeability of greater than about <NUM> in general, and in some embodiments, may comprise a permeability of between about <NUM> to about <NUM>. The magnetic material <NUM> may comprise a thickness of between <NUM> microns to about <NUM> microns in an embodiment, but may vary according to the particular application. The magnetic material <NUM> may comprise a grain structure according to a particular electroplated magnetic material structure, as distinguished from magnetic paste material, for example, and may be free from fillers and resin, for example. The magnetic material <NUM> may be patterned after formation by utilizing self-aligned patterning process, for example. By utilizing such patterning and electroplating processes, the magnetic material <NUM> may be selectively formed within portions/locations of the package substrate <NUM>, according to particular design requirements wherein in-package inductor structures are desired to be located.

<FIG> depicts buildup layers <NUM> that may be formed on the via structures <NUM>, wherein a package structure <NUM> comprising an in-package inductor, is formed. The in-package inductor may comprise the magnetic material <NUM> disposed on the conductive interconnect material, and may comprise any suitable geometry such as a serpentine structure a race loop structure, or a magnetic material plated feature wherein a via is encapsulated by dielectric material. The number of levels of conductive traces/metallization levels that may be built up within the package structure <NUM> may vary according to the particular design requirements. Additional magnetic material <NUM>' may be formed on the conductive interconnect structures <NUM>, and may be patterned according to design requirements. In an embodiment, the magnetic material <NUM> comprises a first layer on a first side of the conductive trace, wherein a sidewall of the first layer is adjacent the dielectric material <NUM>. The magnetic material <NUM> may comprise a second layer on a second side of the conductive trace <NUM>, in an embodiment. Solder structures <NUM> may be formed on a surface/surfaces <NUM>, <NUM> of the substrate <NUM>. The solder structures may be electrically coupled to a die and/or a PCB/motherboard, in an embodiment. In an embodiment, a die <NUM>, may be electrically and physically coupled to the package substrate <NUM>, and may be coupled with the solder structures <NUM>.

The die/device <NUM> may comprise any type of integrated circuit device. In one embodiment, the die <NUM> may include a processing system (either single core or multi-core). For example, the die <NUM> may comprise a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, etc. In one embodiment, the die <NUM> may comprise a system-on-chip (SoC) having multiple functional units (e.g., one or more processing units, one or more graphics units, one or more communications units, one or more signal processing units, one or more security units, etc.). However, it should be understood that the disclosed embodiments are not limited to any particular type or class of devices/die.

Conductive interconnect structures may be disposed on a side(s) of the die/device <NUM> (not shown) and may comprise any type of structure and materials capable of providing electrical communication between a die/device and a substrate, or another die/device, for example. In an embodiment, conductive interconnect structures may comprise an electrically conductive terminal on a die (e.g., a pad, bump, stud bump, column, pillar, or other suitable structure or combination of structures) and a corresponding electrically conductive terminal on a substrate (e.g., a pad, bump, stud bump, column, pillar, or other suitable structure or combination of structures). Solder (e.g., in the form of balls or bumps) may be disposed on the terminals of the substrate and/or die/device, and these terminals may then be joined using a solder reflow process. Of course, it should be understood that many other types of interconnects and materials are possible (e.g., wirebonds extending between a die and a substrate).

The terminals on the die <NUM> may comprise any suitable material or any suitable combination of materials, whether disposed in multiple layers or combined to form one or more alloys and/or one or more intermetallic compounds. For example, the terminals on the die may include copper, aluminum, gold, silver, nickel, titanium, tungsten, as well as any combination of these and/or other metals. In other embodiments, a terminal may comprise one or more non-metallic materials (e.g., a conductive polymer). The terminals on a substrate may also comprise any suitable material or any suitable combination of materials, whether disposed in multiple layers or combined to form one or more alloys and/or one or more intermetallic compounds.

In another embodiment, at least one in-package inductor structure may be formed at a unit/panel level. In <FIG>, a seed layer <NUM> may be formed on selected locations of surfaces of a portion of a coreless substrate <NUM>, in an embodiment. The coreless substrate portion <NUM> may comprise vias <NUM> disposed in a dielectric material <NUM>, wherein further layers of dielectric material <NUM> may be formed/laminated on the surfaces of the vias <NUM>. The seed layer <NUM> may comprise a conductive material, such as a copper material, and may comprise a thickness of about <NUM> to about <NUM> microns, in an embodiment, and may be formed using any suitable formation process, such as a physical vapor deposition process, or an electroplating process, for example. The seed layer <NUM> may be formed on selected portions of the dielectric material <NUM>, where an in-package process is to be formed.

A magnetic material <NUM> is selectively formed on the seed layer <NUM>, and may not be formed on the adjacent dielectric material <NUM> (<FIG>), by utilizing the selective electroplating process <NUM>. A dielectric layer <NUM>' may then be formed on the magnetic material <NUM>, and further conductive structures <NUM>' may be formed within the dielectric layer <NUM>', adjacent the magnetic material <NUM> (<FIG>). The dielectric material <NUM> may be ground to planarize with the surfaces of the magnetic material <NUM> and the additional conductive material <NUM>', in an embodiment. Build up layers (not shown) are formed on the magnetic material <NUM>. A side perspective view of an in-package, embedded electroplated inductor structure <NUM> is depicted in <FIG>, wherein the magnetic material <NUM> is on the conductive material, such on conductive structure <NUM>, and wherein the dielectric material is adjacent the magnetic material <NUM>. In an embodiment, the conductive material is formed to loop around the magnetic material. A top view of a portion of an in-package/embedded inductor structure <NUM> is shown in <FIG>, wherein the magnetic material <NUM> is on a selected portion of the conductive material <NUM>, and wherein the inductor <NUM> is disposed within the dielectric material <NUM> of the substrate <NUM>, such as within the substrate <NUM> of <FIG>, for example, and is not disposed on a surface of the substrate <NUM>. <FIG> depicts another side perspective view of an embedded inductor structure <NUM>, wherein the inductor <NUM> geometry is in the form of a serpentine-like shape. <FIG> depicts a top view of another geometry, wherein an embedded inductor <NUM> comprises rectangular shaped conductive material <NUM> disposed on the magnetic material <NUM>, wherein the magnetic material <NUM> is embedded within the dielectric material <NUM> of the substrate, such as within the dielectric material of a build up layer.

<FIG> depict another method of forming an in-package inductor on a cored substrate, according to embodiments, by utilizing selective electroplated magnetic materials. In <FIG>, a portion of a substrate, which comprises a core portion <NUM> of a package substrate, comprises a dielectric material in an embodiment. The core material may comprise an organic material in an embodiment, and may comprise other suitable materials, such as ceramic and/or glass, for example. In an embodiment, the core <NUM> comprises a first surface <NUM> and a second surface <NUM>.

In an embodiment, openings <NUM>, which comprise openings for the formation of a via structure, such as a plated through hole (PTH), may be formed in the core <NUM> (<FIG>), wherein the openings <NUM> comprise sidewalls <NUM>. The openings <NUM> may be formed by a drilling process, such as a laser drilling process, for example. A seed layer <NUM> is formed on sidewalls <NUM> of the openings <NUM>, and on surfaces <NUM>, <NUM> of the core <NUM> (<FIG>). The seed layer <NUM> is formed by placing the core <NUM> in an electroplating bath in an embodiment according to the invention. In another embodiment not claimed, the seed layer <NUM> may be formed by such processes as physical vapor deposition, chemical vapor deposition, and any other suitable formation process. The seed layer may comprise a thickness between about x and y.

In <FIG>, a magnetic material <NUM> is formed, by a selective electroplating process, onto the surfaces <NUM>, <NUM> of the core <NUM>, and onto sidewalls <NUM> of the core <NUM>. The magnetic material <NUM> is selectively electroplated only where an in-package inductor is to be formed. The magnetic material <NUM> may comprise similar materials and properties as the magnetic material <NUM> of <FIG>, for example. The magnetic material <NUM> may comprise a thickness of about <NUM> microns to about <NUM> microns, and may comprise a low coercivity and a high permeability, such as comprising a permeability of greater than about <NUM>, for example. In an embodiment, the electroplated magnetic material <NUM> may be patterned by electroplating in a selected region in the substrate wherein the conductive material may be plated in an inductor area, and may be patterned in a serpentine fashion, for example, in an embodiment. In other cases, the inductor structure may be designed/patterned in such a way that the inductor geometry comprises multiple loops traveling the cross section of the substrate. The patterning of the magnetic material <NUM> may utilize a dry film resist (DFR) patterning technique, as well as stripping processes, such as flash etching, for example. Magnetic plating thickness can vary based on design requirements and plugin capability, in an embodiment.

A conductive material/layer <NUM> is formed/plated on the magnetic material <NUM> (<FIG>). The conductive material <NUM> may comprise copper, for example, and may be formed by any suitable formation process, such as a plating process, for example, and may be formed on sidewalls <NUM> and on surfaces <NUM>, <NUM> of the core <NUM>. In <FIG>, the conductive layer <NUM> may be planarized to expose the magnetic material <NUM> on the surfaces <NUM>, <NUM> of the core <NUM>, wherein a plugging and grinding process <NUM> may be employed. A conductive lid <NUM>, such as a copper lid, may be plated onto the surfaces <NUM>, <NUM> of the core <NUM> (<FIG>). In an embodiment, a first surface <NUM> and a second surface <NUM> of the via <NUM> is free of the magnetic material <NUM>. Build up layers <NUM> including conductive structures <NUM>, <NUM> are then formed on the surfaces <NUM>, <NUM> of the core <NUM>, and solder balls <NUM> may be attached to the surfaces of the build-up layers, to form the package structure <NUM> (<FIG>).

The in-package inductors of the embodiments provide efficient power delivery, and are economical to fabricate. The magnetic material of the in-package inductors described herein are embedded in specific locations in the substrate, by utilizing selective electroplating and patterning processes. The in-package inductors described herein alleviate such issues as biased highly accelerated stress testing and leaching risks. Additionally, the in-package inductor structures herein enable superior, high efficiency package fabrication.

<FIG> depicts a method <NUM> of forming an in-package inductor structure, wherein a magnetic material is selectively electroplated to form a portion of the in-package inductor structure. At operation <NUM>, an opening is formed in a package substrate. The opening comprises a plated through hole in a cored package substrate, or in the case of a coreless package, comprises an opening in a dielectric layer of the coreless package substrate. The opening may expose a conductive interconnect structure, such as a conductive pad, for example. At operation <NUM>, a magnetic material is selectively formed on at least one surface of the opening. The magnetic material may further be formed on a surface of the conductive interconnect structure. In an embodiment, a seed layer may initially be formed within the opening, and may also be formed on the conductive interconnect structure.

The seed layer may comprise any suitable conductive material with which to subsequently form a magnetic material. By selecting the locations of the openings and/or the seed layer formation, magnetic material layers of an inductor structure may be placed at desired locations within a package substrate. The magnetic material may comprise a thickness of between <NUM> microns to about <NUM>, in an embodiment, but may vary according to the particular application. The magnetic material may comprise materials that possess a low coercivity and a high permeability, such as nickel, iron, molybdenum, cobalt and combinations/alloys thereof. In an embodiment, a length of the conductive interconnect structure may be greater than a length of the magnetic material formed in the opening. In another embodiment, a length of the magnetic material may be less than about <NUM> times a length of the conductive interconnect structure <NUM>.

At operation <NUM>, a conductive material is formed on the magnetic material. The conductive material may comprise a copper material, for example. The inductor structure thus formed may be patterned in any suitable geometry within the package substrate. At step <NUM>, at least one build-up layer and/or dielectric layer may be formed on the inductor structure, so that the in-package inductor structure may be fully embedded within the package substrate.

<FIG> depicts a method of forming an in-package inductor structure, wherein a magnetic material is selectively electroplated at a unit/panel level to form portions of at least one in-package inductor structure. At operation <NUM>, a seed layer may be selectively formed on a surface of a package substrate panel, wherein the seed layer is formed adjacent to a conductive layer. The conductive layer may be disposed within a dielectric material within the substrate. The substrate panel may comprise an array of substrates prior to a singulation process, in an embodiment. The seed layer may be formed and patterned utilizing any suitable formation and patterning techniques. The seed layer may be formed in locations in which in-package inductor structures may be located.

At operation <NUM>, a magnetic material is selectively electroplated on the seed layer, such that the magnetic material is only formed where the seed layer is disposed. The magnetic material is electroplated according to the embodiments described herein, and may comprise a low coercivity and a high permeability magnetic material. The magnetic material may comprise such materials as nickel, cobalt, iron, molybdenum, and combinations thereof. At operation <NUM>, a build-up layer is formed on the magnetic material.

The package structures of the embodiments herein may be coupled with any suitable type of structures capable of providing electrical communications between a microelectronic device, such as a die, disposed in package structures, and a next-level component to which the package structures herein may be coupled (e.g., a circuit board). The device/package structures, and the components thereof, of the embodiments herein may comprise circuitry elements such as logic circuitry for use in a processor die, for example. Metallization layers and insulating material may be included in the structures herein, as well as conductive contacts/bumps that may couple metal layers/interconnects to external devices/layers. In some embodiments, the structures may further comprise a plurality of dies, which may be stacked upon one another, depending upon the particular embodiment. In an embodiment, a die(s) may be partially or fully embedded in a package structure of the embodiments herein.

The various embodiments of the device/package structures included herein may be used for system on a chip (SOC) products, and may find application in such devices as smart phones, notebooks, tablets, wearable devices and other electronic mobile devices. In various implementations, the package structures herein may be included in a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder, and wearable devices. In further implementations, the package devices herein may be included in any other electronic devices that process data.

Turning now to <FIG>, illustrated is a cross sectional view of an embodiment of a computing system <NUM>. The system <NUM> includes a mainboard <NUM> or other circuit board. Mainboard <NUM> includes a first side <NUM> and an opposing second side <NUM>, and various components may be disposed on either one or both of the first and second sides <NUM>, <NUM>. In the illustrated embodiment, the computing system <NUM> includes at least one die <NUM>, disposed on a surface (such as on a top or bottom or side surface) of a substrate <NUM>, such as a package substrate comprising at least one of the embedded inductor structures according to any of the various embodiments herein. The substrate <NUM> may comprise an interposer <NUM>, for example, or any other type of substrate, such as a cored substrate or a coreless substrate, for example.

The substrate <NUM> comprises various conductive layers <NUM>, for example, which are electrically and physically connected to each other by via structures <NUM>. The conductive layers <NUM> may comprise conductive traces in an embodiment.

The substrate <NUM> further comprises through substrate vias <NUM>, which comprise the magnetic material on sidewalls, such as in <FIG>, for example. Dielectric material <NUM> may separate/isolate conductive layers from each other within the substrate <NUM>. Joint structures <NUM> may electrically and physically couple the substrate <NUM> to the board <NUM>. The computing system <NUM> may comprise any of the embodiments of the in-package, embedded inductor structures described herein.

System <NUM> may comprise any type of computing system, such as, for example, a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a net top computer, etc.). However, the disclosed embodiments are not limited to hand-held and other mobile computing devices and these embodiments may find application in other types of computing systems, such as desk-top computers and servers.

Mainboard <NUM> may comprise any suitable type of circuit board or other substrate capable of providing electrical communication between one or more of the various components disposed on the board. In one embodiment, for example, the mainboard <NUM> comprises a printed circuit board (PCB) comprising multiple metal layers separated from one another by a layer of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route - perhaps in conjunction with other metal layers - electrical signals between the components coupled with the board <NUM>. However, it should be understood that the disclosed embodiments are not limited to the above-described PCB and, further, that mainboard <NUM> may comprise any other suitable substrate.

<FIG> is a schematic of a computing device <NUM> that may be implemented incorporating embodiments of the package structures described herein. For example, any suitable ones of the components of the computing device <NUM> may include, or be included in, package structures comprising the in-package inductor structures of the various embodiments disclosed herein. In an embodiment, the computing device <NUM> houses a board <NUM>, such as a motherboard <NUM> for example. The board <NUM> may include a number of components, including but not limited to a processor <NUM>, an on-die memory <NUM>, and at least one communication chip <NUM>. The processor <NUM> may be physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> may be physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the board <NUM>, and may or may not be communicatively coupled to each other. These other components include, but are not limited to, volatile memory (e.g., DRAM) <NUM>, non-volatile memory (e.g., ROM) <NUM>, flash memory (not shown), a graphics processor unit (GPU) <NUM>, a chipset <NUM>, an antenna <NUM>, a display <NUM> such as a touchscreen display, a touchscreen controller <NUM>, a battery <NUM>, an audio codec (not shown), a video codec (not shown), a global positioning system (GPS) device <NUM>, an integrated sensor <NUM>, a speaker <NUM>, a camera <NUM>, an amplifier (not shown), compact disk (CD) (not shown), digital versatile disk (DVD) (not shown), and so forth. These components may be connected to the system board <NUM>, mounted to the system board, or combined with any of the other components.

The communication chip <NUM> enables wireless and/or wired communications for the transfer of data to and from the computing device <NUM>. The communication chip <NUM> may implement any of a number of wireless or wired standards or protocols, including but not limited to Wi-Fi (IEEE <NUM> family), WiMAX (IEEE <NUM> family), IEEE <NUM>, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, Ethernet derivatives thereof, as well as any other wireless and wired protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond.

For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a wearable device, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data.

Embodiments of the package structures described herein may be implemented as a part of one or more memory chips, controllers, CPUs (Central Processing Unit), microchips or integrated circuits interconnected using a motherboard, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA).

The above embodiments may include specific combinations of features as further provided as examples.

An example relates to a microelectronic package structure. The microelectronic package structure comprises a substrate including a dielectric material, the substrate having a first side and a second side; a conductive trace located within the dielectric material, a first layer on a first side of the conductive trace, wherein the first layer comprises a magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material, and a second layer on a second side of the conductive trace, wherein the second layer comprises the magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

In an example, a seed layer is between the first layer and the conductive trace, wherein the seed layer comprises one or more of copper, titanium, nickel, and alloys thereof.

In an example, the seed layer comprises a thickness of between about <NUM> to about <NUM> microns.

In an example, the second layer is between the conductive trace and a solder ball, wherein the solder ball is at least partially on one of the first or the second surfaces of the substrate.

In an example, the substrate comprises a portion of a coreless package, and wherein a dielectric layer is on the second layer, and wherein a length of the second layer is less than a length of the conductive trace.

In an example, the magnetic material comprises a portion of an embedded inductor structure.

In an example, the magnetic material comprises one or more of iron, nickel, cobalt or molybdenum, their alloys, and combinations thereof.

In an example, the first side of the substrate includes a die electrically coupled thereto.

In an example, the substrate comprises a printed circuit board (PCB), and the die comprises a memory die.

An examples relates to a microelectronic package structure comprising a substrate, a core located within the substrate, wherein the core includes a first side and a second side, a via extending through at least a portion of the core, a magnetic material on a sidewall of the via, and a conductive material on the magnetic material.

In an example, the magnetic material comprises an electroplated magnetic material, wherein the electroplated magnetic material comprises one or more of iron, nickel, cobalt, molybdenum, and combinations thereof.

In an example, a seed layer is between the via sidewall and the magnetic material, and wherein the magnetic material is an electroplated magnetic material.

In an example, at least a portion of one of the first surface or the second surface of the core comprises the magnetic material adjacent the via.

In an example, the magnetic material comprises a thickness of between about <NUM> microns and about <NUM> microns.

In an example, a first surface and a second surface of the via is free of the magnetic material.

In an example, the via comprises a plated through hole.

In an example, the microelectronic package substrate comprises a microprocessor, a memory, and a battery, wherein at least the microprocessor is electrically coupled to the substrate.

An example relates to a method of fabricating a microelectronic package assembly. The method comprises forming an opening in a package substrate, wherein the package substrate comprises a first surface and a second surface, selectively electroplating a magnetic material on at least one surface of the opening, forming a conductive material on the magnetic material, and forming a buildup layer on the magnetic material.

In an example, the magnetic material comprises a portion of an embedded package inductor.

In an example, selectively electroplating the magnetic material comprises electroplating one or more of iron, cobalt, nickel, or molybdenum on the at least one surface of the opening.

In an example, selectively electroplating the magnetic material comprises forming a seed layer on a surface of the opening, and selectively electroplating the magnetic material on the seed layer.

In an example, forming the seed layer on the surface of the opening comprises forming one or more of copper, titanium, or nickel, and alloys thereof.

In an example, forming the opening comprises forming a plated through hole in a core portion of the substrate.

In an example, selectively electroplating the magnetic material comprises electroplating the magnetic material on a terminal portion of a via structure, wherein the via structure is located within the substrate.

Claim 1:
A microelectronic package structure, comprising:
a substrate (<NUM>; <NUM>) including a dielectric material (<NUM>; <NUM>), the substrate having a first side and a second side opposite to the first side;
a conductive trace (<NUM>; <NUM>) along the first side (<NUM>; <NUM>) and the second side (<NUM>; <NUM>), the conductive trace being located within the dielectric material;
characterized by
a first layer that is formed, using electroplating, directly on a first side of the conductive trace or that is formed on a seed layer that is on the first side of the conductive trace, wherein the first layer comprises a magnetic material (<NUM>), and wherein at least one sidewall of the first layer is in contact with the dielectric material; and
a second layer that is formed, using electroplating, directly on a second side of the conductive trace or that is formed on a seed layer that is on the second side of the conductive trace, wherein the second layer comprises the magnetic material (<NUM>), and wherein at least one sidewall of the second layer is in contact with the dielectric material.