Patent Description:
The use of power devices, such as uninterruptible power supplies (UPS), to provide regulated, uninterrupted power for sensitive and/or critical loads, such as computer systems and other data processing systems, is known. Known uninterruptible power supplies include on-line UPSs, off-line UPSs, line interactive UPSs, as well as others. On-line UPSs provide conditioned AC power as well as back-up AC power upon interruption of a primary source of AC power. Off-line UPSs typically do not provide conditioning of input AC power, but do provide back-up AC power upon interruption of the primary AC power source. Line interactive UPSs are similar to off-line UPSs in that they switch to battery power when a blackout occurs but also typically include a multi-tap transformer for regulating the output voltage provided by the UPS.

A typical on-line UPS rectifies input power provided by an electric utility using a Power Factor Correction circuit (PFC) to provide rectified power to a DC bus. The rectified DC voltage is typically used to charge a battery while mains power is available, as well as to provide power to the DC bus. In the absence of mains power, the battery provides power to the DC bus. From the DC bus, an inverter generates an AC output voltage, which is provided to the load. Since the DC bus may be powered by either the mains or the battery, the output power of the UPS is uninterrupted if the battery is sufficiently charged when the mains fails. Typical on-line UPSs may also operate in a bypass mode in which unconditioned power is provided directly from an AC power source through the bypass line to the load.

To provide enhanced scalability and/or redundancy, two or more UPSs may be electrically connected to form a parallel UPS system. In such a system, the combination of multiple UPSs may provide increased power capacity to a load attached to the parallel UPS system. Also, if one of the UPSs coupled in parallel fails, the other UPSs coupled in parallel may act as backup supplies for the failed UPS. Documents <CIT> and <CIT> and <CIT>.

disclose examples of UPS methods and systems according to available prior art.

Aspects and embodiments are generally directed to systems and methods for automatically balancing load sharing between each of a plurality of parallel UPSs during a bypass mode of operation. Aspects and embodiments discussed herein include one or more active components within a bypass circuit of each UPS which may be dynamically controlled to automatically interrupt an input current such that an output current of each UPS of the plurality provides a substantially equivalent Root Mean Square (RMS) current. Accordingly, aspects and embodiments provide a reduced size, weight, cost, and complexity load sharing system when compared to various known approaches for load balancing.

The main aspects and embodiments of the invention are set out in the appended claims.

Still other aspects, embodiments, and advantages of these exemplary aspects and embodiments, are discussed in detail below. Moreover, it is to be understood that both the foregoing information and the following detailed description are merely illustrative examples of various aspects and embodiments, and are intended to provide an overview or framework for understanding the nature and character of the claimed aspects and embodiments. Under the limitation of the appended claims any embodiment disclosed herein may be combined with any other embodiment in any manner consistent with at least one of the objectives, aims, and needs disclosed herein, and references to "an embodiment," "some embodiments," "an alternate embodiment," "various embodiments," "one embodiment" or the like are not necessarily mutually exclusive and are intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment. The appearances of such terms herein are not necessarily all referring to the same embodiment.

The figures are included to provide illustration and a further understanding of the various aspects and embodiments, and are incorporated in and constitute a part of this specification, but are not intended as a definition of the limits of the invention. In the figures:.

Aspects and embodiments are generally directed to systems and methods for automatically balancing load sharing between each of a plurality of parallel UPSs during a bypass mode of operation.

As discussed above, typical on-line UPSs may operate in a bypass mode or an on-line mode of operation. During the bypass mode, unconditioned power is provided directly from an AC power source (e.g., AC mains) through a bypass line (e.g., a bypass circuit) to a load. In the event of a disturbance at the AC mains, such as a sag or swell condition, the on-line UPS may enter the on-line mode, or battery mode, during which the bypass line is disconnected from the load by opening a bypass switch. During the on-line mode, the UPS is operated to condition power provided by the AC mains, or battery, and provide the conditioned power to an output coupled to the load.

As also discussed above, two or more UPSs may be electrically connected to form a parallel UPS system with a single output. In a parallel UPS system, successful (i.e., equal) load sharing between the on-line UPSs is achieved by operating the inverter of each on-line UPS during the on-line mode to properly regulate the power provided by each on-line UPS to the single output (coupled to the load).

Successful load sharing between on-line UPSs coupled in parallel is much more difficult to achieve in the bypass mode where unconditioned power is provided by each UPS to the single output. More specifically, even if similarly rated on-line UPSs are coupled together in parallel, and are each providing power to the output (i.e., the load), in bypass mode, manufacturing differences in components within each UPS may result in unequal load sharing between each UPS. Moreover, differences in the cables that couple each UPS to the power source and the single output may also significantly contribute to unbalanced load sharing.

If a load is unevenly shared between on-line UPSs coupled in parallel (and operating in bypass mode), one of the UPSs may become overloaded. For example, the uneven sharing of a load between on-line UPSs coupled in parallel may result in a protection circuit tripping (e.g., a breaker either upstream or internal to the on-line UPS), or a bypass switch opening, resulting in its share of the load being transferred to the other UPSs coupled in parallel. The additional load transferred to the other UPSs may result in the tripping of an additional protection circuit in another of the UPSs, and the transferring of its load to the other UPSs. As this breaker protection tripping/load transfer process continues, the remaining UPSs may eventually be unable to support the load, and the load may be dropped.

One typical technique for dealing with uneven load sharing between parallel UPSs operating in bypass mode is to identify the actual portion of the load supported by each UPS (i.e., the load sharing portion), and to adjust the impedance between each UPS and the load in an attempt to evenly distribute the load across the UPSs. The impedance between each UPS and the load may be managed by adjusting the length of the cable coupling each UPS to the load and/or adding a choke (i.e., an inductor) between a respective UPS and the load. However, such techniques are typically difficult to implement, require additional space for added cable length, increase the losses of the system (e.g., as a result of the additional cable length), and can be expensive to implement.

For example, it is generally accepted that despite adjusting the lengths of and/or adding chokes to the cables coupling parallel UPSs to a load, a maximum number of four on-line UPSs operating in bypass mode can be coupled together in parallel. Coupling more than four on-line UPSs together in parallel may result in a load sharing portion deviation of more than <NUM>% between the UPSs. Even with four parallel on-line UPSs operating in bypass mode, up to <NUM>% deviation in the load sharing portion of each UPS can occur.

Accordingly, various aspects and embodiments provide a system for automatic load sharing across multiple UPSs coupled in parallel during a bypass mode of operation. In addition to the other advantages discussed herein, various aspects and embodiments of the described system may reduce the amount of cable length and additional components (e.g., chokes) required to properly balance load sharing between multiple parallel UPSs. As such, various aspects and embodiments may provide a system having a reduced size, weight, cost, and complexity when compared to various known load balancing systems.

Examples of the systems and methods discussed herein are not limited in application to the details of construction and the arrangement of components set forth in the following description or illustrated in the accompanying drawings. The systems and methods are capable of implementation in other embodiments and of being practiced or of being carried out in various ways. Examples of specific implementations are provided herein for illustrative purposes only and are not intended to be limiting. In particular, acts, components, elements and features discussed in connection with any one or more examples are not intended to be excluded from a similar role in any other examples.

<FIG> is a block diagram of an example power system <NUM> including a plurality of on-line UPSs, according to certain aspects and embodiments. As illustrated, each of the UPSs may be coupled in parallel, such as the three illustrated UPSs 102a, 102b, 102c. Each UPS 102a-c may include an input <NUM>, an output <NUM>, and a bypass circuit <NUM>. The input <NUM> of each UPS 102a-c may be coupled to a power source <NUM> and configured to receive input power (e.g., AC power) therefrom. Similarly, the output <NUM> of each UPS 102a-c may be coupled to a shared load <NUM> and configured to provide output power to the load <NUM> based at least in part on the input power. The bypass circuit <NUM> (e.g., bypass line) of each UPS is interposed between the input <NUM> and the output <NUM> and may include at least one bypass switch <NUM>. As further discussed herein, control of the bypass switch <NUM> of a given UPS 102a-c may operate that UPS in one of a bypass mode of operation and an on-line mode of operation. In certain examples, the system <NUM> may include a controller <NUM> coupled to each UPS 102a-c. The controller <NUM> may manage the operation of the respective bypass switch <NUM>, as illustrated in <FIG>. However, in certain other examples a dedicated controller may be integrated within each UPS 102a-c. That is, a single controller <NUM> is shown in <FIG> for the convenience of illustration only. As further illustrated in <FIG>, each UPS 102a-c may further include an AC/DC converter <NUM>, a DC bus <NUM>, and a DC/AC converter <NUM>.

For each UPS 102a-c, the AC/DC converter <NUM> is interposed between the DC bus <NUM> and the input <NUM> and the DC/AC converter <NUM> is interposed between the DC bus <NUM> and the output <NUM>. Each UPS 102a-c is coupled in parallel so that the input <NUM> of each UPS 102a-c is coupled to the power source <NUM> and the output <NUM> of each UPS 102a-c is coupled to the load <NUM>. While the example of <FIG> illustrates three UPSs 102a-c coupled in parallel for the convenience of illustration, given the benefit of this disclosure one skilled in the art would appreciate that the system <NUM> may include any suitable number of UPSs coupled in parallel. For example, as a result of the improved functionality of the system <NUM>, the system <NUM> may include more than four UPSs coupled in parallel.

In certain examples, the controller <NUM> is coupled to each UPS 102a-c and configured to monitor the input power provided by the power source <NUM> to each UPS 102a-c. Based on the quality of the input power and/or the absence of the input power, the controller <NUM> is configured to control each of the UPSs 102a-c between various modes of operation, such as a "bypass" mode of operation, an "on-line" mode of operation, and/or a "battery" mode of operation.

In response to determining that the input power provided by the power source <NUM> is either lower than or greater than a desired level (e.g., is in a sag or swell condition), the controller <NUM> controls each UPS 102a-c to enter the on-line mode of operation. During the on-line mode of operation, the controller <NUM> operates a backfeed relay in each UPS 102a-c to close (thereby coupling the power source <NUM> to the input <NUM>), and operates the bypass switch <NUM> of each UPS 102a-c to open. Accordingly, the AC/DC converter <NUM> of each UPS 102a-c receives AC power from the power source <NUM> and converts the received AC power into DC power to provide the DC power to the DC bus <NUM>. According to various examples, the DC/AC converter <NUM> of each UPS 102a-c may receive the DC power from the DC bus <NUM> and may convert the received DC power into AC power to be provided to the output <NUM>.

In certain examples, during the on-line mode of operation the DC power on the DC bus <NUM> of each UPS 102a-c may be provided to a DC/DC converter <NUM> coupled to the DC bus <NUM>. The DC/DC converter <NUM> converts the DC power received from the DC bus <NUM> into DC power at a desired charging level. In such an example, the DC power at the desired charging level may be provided to a corresponding battery to charge the battery.

In response to a determination that the AC power provided by the power source <NUM> has failed (e.g., is in a brownout or blackout condition), the controller <NUM> operates each UPS 102a-c to enter the battery mode of operation. During the battery mode of operation, the controller <NUM> operates a backfeed relay in each UPS 102a-c to open (thereby decoupling the power source <NUM> from the input <NUM>). Similarly, the controller <NUM> operates the bypass switch <NUM> of each UPS 102a-c to open. DC power from the battery is then provided to the DC bus <NUM>. The DC/AC converter <NUM> may receive the DC power from the DC bus <NUM> and convert the received DC power into AC power, which is provided to the output <NUM>.

In response to a determination that the AC power provided by the power source <NUM> is at a desired level, the controller <NUM> may operate each UPS 102a-c to enter the bypass mode of operation. During the bypass mode of operation each UPS 102a-c may provide unconditioned power directly from the power source <NUM> (e.g., AC mains) through bypass circuit <NUM> to the load <NUM>. That is, each bypass circuit <NUM> receives an input current from the input <NUM> and provides an output current derived from the input current to the output <NUM>. In certain embodiments, during the bypass mode of operation the controller <NUM> controls the backfeed relay in each UPS 102a-c to close (thereby coupling the power source <NUM> to the input <NUM>), and controls the bypass switch <NUM> of each UPS 102a-c to close. Accordingly, in the bypass mode of operation, the input <NUM> of each UPS 102a-c is coupled directly to the output <NUM> of the corresponding UPS 102a-c via the bypass circuit <NUM>.

In certain embodiments, the controller <NUM> is coupled to the input <NUM> of each UPS 102a-c and configured to determine whether each UPS 102a-c should be in the bypass mode of operation. For instance, the controller <NUM> may monitor the input current to determine the presence, quality, and/or level of the input power. In particular examples, the controller <NUM> determines whether the input power is above or below a predetermined level (e.g., in a sag or swell condition) to determine if each UPS 102a-c should be in the bypass mode of operation. Responsive to determining that the UPSs 102a-c should be in the bypass mode of operation, the controller <NUM> operates the bypass switch <NUM> of each UPS 102a-c to close. When in the closed position, each bypass switch <NUM> couples the respective input <NUM> directly to the respective output <NUM> of each UPS 102a-c. In several embodiments, each bypass switch <NUM> is controlled by an analog or digital control signal (e.g., signals <NUM>) received from the controller <NUM>. In particular examples, each bypass switch <NUM> is a set of Silicon Controlled Rectifiers (SCR), such as a set of thyristors. However, in certain other examples each bypass switch <NUM> may be another suitable type of switch, such as a transistor-based switch.

In various embodiments, the controller <NUM> is configured to monitor the input current through the bypass circuit <NUM> of each UPS 102a-c during the bypass mode of operation. Based on the monitored input current, the controller <NUM> is configured to identify a first UPS of the UPSs 102a-c based on a determination of which current has the largest magnitude. For example, the controller <NUM> may determine which UPS 102a-c has the largest input current by comparing the current through the bypass circuit <NUM> of each UPS 102a-c with the current through the bypass circuit <NUM> of each other UPS 102a-c. In certain other examples, the controller <NUM> may identify which UPS 102a-c has the largest input current by comparing the current through each bypass circuit <NUM> with an average of the input currents. However, in still other examples, the controller <NUM> may use any other suitable process to identify the UPS with the largest input current magnitude.

Responsive to identifying the first UPS, the controller <NUM> provides a control signal to the bypass switch <NUM> of the first UPS to control the bypass switch <NUM> to interrupt the input current through the respective bypass circuit <NUM> for a duration of a first delay. In particular, the controller <NUM> operates the first bypass switch <NUM> to interrupt the input current such that each of the UPSs 102a-c provides a substantially balanced output current, among the UPSs 102a-c, to the load <NUM> (e.g., via the corresponding output <NUM>). That is, the controller <NUM> is configured to operate the bypass switch <NUM> of the first UPS such that the power provided to the load <NUM> is evenly distributed among each of the UPSs 102a-c. Also during the duration of the first delay, the controller <NUM> provides a control signal to each of the other UPSs (i.e., all of the UPSs excluding the first UPS) to maintain the respective bypass switch <NUM> in a closed position such that an output current waveform of each of the other UPSs is continuous during the duration of the first delay. That is, even though an interruption is introduced in the output current of the first UPS, the load <NUM> receives a full sinusoidal waveform (e.g., for a linear load) from each of the other UPSs during the duration of the first delay.

In certain embodiments, the controller <NUM> is configured to interrupt the input current through the bypass circuit <NUM> of the first UPS by reducing the input current through the bypass circuit <NUM>. For example, the controller <NUM> may operate the bypass switch <NUM> of the first UPS to open for the duration of the first delay and control the bypass switch <NUM> to close at the conclusion of the first delay. In certain examples, the controller <NUM> may track a waveform of the input current and operate the bypass switch <NUM> of the first UPS to open at about a zero-crossing of the waveform. Accordingly, the first delay may begin at about the zero-crossing of the input current waveform.

As discussed above, in certain examples each bypass switch <NUM> may include an SCR, and in particular, a set of SCRs. For example, each bypass switch <NUM> may include a pair of SCRs per phase of the input current. A first SCR of the pair may be controlled to operate during a positive portion of the input current waveform, and a second SCR of the pair (e.g., arranged in a substantially opposite orientation to the first SCR) may be controlled to operate during a negative portion of the input current waveform. In such an example, the controller <NUM> may provide a control signal to the set of SCRs to close, which permits propagation of the input current between the input <NUM> and the output <NUM>. To begin the interruption of the input current, the controller <NUM> may remove the control signal from the corresponding set of SCRs. Once the signal is removed, each SCR will open as the input current waveform reaches a zero crossing and interrupt the input current. In certain examples, the controller <NUM> may manage operation of the power system <NUM> such that the current through only one of the UPSs 102a-c is interrupted at any given time. Such an example provides the benefit of increased safety and avoidance of load interruptions.

In certain examples, during the duration of the first delay, each of the other UPSs will experience an increase in the instantaneous input current. In particular, the increase will be relative to the reduction of the input current through the bypass circuit <NUM> of the first UPS. Accordingly, the controller <NUM> may automatically adjust the duration of the first delay period such that each UPS 102a-c of the plurality provides a substantially equivalent Root Mean Square (RMS) current to the load <NUM> (e.g., via the corresponding output <NUM>). In some implementations, the controller <NUM> may interrupt the input current through the bypass circuit <NUM> of the first UPS for a duration of up to at least a full cycle of the input current waveform, which in some instances may include interrupting the input current for up to several (e.g., two or three) cycles of the input current waveform. However, in certain other instances, the interruption may be less than a full cycle of the waveform.

By dynamically adjusting the duration of the first delay period, the RMS current of each UPS102a-c can be controlled to a substantially equivalent RMS value (e.g., about the same RMS current value), despite differences in components and cabling. In particular examples, the controller <NUM> may dynamically adjust the duration of the first delay based at least in part on the monitored input current of each of the UPSs 102a-c.

For example, when determining the timing and duration of one or more delays, the controller <NUM> may first identify the cardinality of active UPSs within the power system <NUM>. Once identified, the controller <NUM> may define a controlled time period based on a targeted tolerance of the load. Specifically, the targeted tolerance may be based on a percentage variation in the input current. Once the controlled time period has been calculated, the controller <NUM> may assign a priority to each identified UPS within the power system <NUM>. For example, the controller <NUM> may assign a first priority to the first UPS 102a, a second priority to the second UPS 102b, and a third priority to the third UPS 102c. Interruption of the input current through one of the UPSs 102a-c is managed by the controller <NUM> according to the order of priorities to maintain the targeted tolerance during the controlled time period. At the conclusion of a first delay, the controller <NUM> may reassign the priorities or maintain the previous order of priorities. This order of operations may automatically continue until each identified active UPS within the system <NUM> provides a substantially balanced output current to the load across the active UPSs. In certain examples the controller <NUM> may assign priorities based on which UPS has an output current with the largest magnitude.

While in certain examples, the controller <NUM> may apply these operations for single-phase input power, in certain other examples, the controller <NUM> may also apply these operations for each phase of three-phase input power. For instance, when receiving three-phase power, the controller <NUM> may select and interrupt the phase with the largest magnitude, as discussed above. The controller <NUM> may then apply similar operations to the remaining two phases.

In certain examples, the duration of a given delay may be based on a relationship between a ratio of the input current of a UPS 102a-c and an average output current of the system <NUM>, and a duration of the controlled time period. For example, in response to determining that the input current of the first UPS 102a exceeds an average output current by <NUM>%, the controller <NUM> may operate the corresponding bypass switch <NUM> of the first UPS 102a to interrupt the input current through the first UPS 102a for a duration of about <NUM>% of the controlled time period. While control in such a manner illustrates one example, the controller <NUM> may perform certain other operations for calculating a suitable delay in other embodiments. In particular, in certain examples the controller <NUM> may adjust delays based on one or more regulatory requirements. As further discussed herein, such operations may be performed by the controller <NUM> continuously and/or dynamically during the operation of the system <NUM>. Such functionality offers the benefit of offering data which accurately reflects the thermal constraints applied to the power system <NUM>.

While in certain examples, such as those described above, the controller <NUM> may operate each bypass switch <NUM> based on an order of assigned priorities, it certain other embodiments, an order of interruptions may be based on a random determination. That is, the order in which the input current through each UPS 102a-c is interrupted may be random so long as each interruption is performed at an appropriate speed and for an appropriate duration. For example, the order of interruptions may be random so long as the duration of a thermal time constant of a corresponding bypass switch <NUM> is not exceeded.

As discussed above, at the conclusion of the duration of the first delay, the controller <NUM> may identify a second UPS. Responsive to identifying the second UPS, the controller <NUM> provides a control signal to the bypass switch <NUM> of the second UPS to interrupt the input current through the respective bypass circuit <NUM> for the duration of a second delay. In particular, the controller <NUM> is configured to operate the bypass switch <NUM> of the second UPS such that the duration of the first delay and the duration of the second delay are non-concurrent.

Similar to those processes discussed above with reference to the first UPS, the controller <NUM> may operate the bypass switch <NUM> of the second UPS to interrupt the input current such that each of the UPSs 102a-c provides a substantially balanced output current, among the UPSs 102a-c, to the load <NUM>. That is, the controller <NUM> is configured to operate the bypass switch <NUM> of the second UPS such that the power provided to the load <NUM> is evenly distributed among each of the UPSs 102a-c. Similar operations may be performed continuously and automatically by the controller <NUM> for a third UPS, a fourth UPS, a fifth UPS, etc. at the conclusion of the second delay period and each subsequent delay period. While discussed herein as first UPS, a second UPS, a third UPS, and etc. for the convenience of description, in various embodiments the controller <NUM> may operate any suitable number of UPSs, and each of the first UPS, second UPS, third UPS, and etc. may refer to the same UPS of the plurality.

According to certain examples, the input power received from the power source <NUM> may include single-phase electrical input power. In at least these examples, the controller <NUM> may be configured to provide a single control signal to the bypass switch <NUM> of each UPS 102a-c. Such an example is particularly advantageous when each bypass switch <NUM> includes a set of SCRs because simplified hardware and electronics may be used, reducing the complexity of the components necessary to control each bypass switch <NUM>. <FIG> illustrates one simplified arrangement of the connection between the controller <NUM> and the bypass switches <NUM>. <FIG> illustrates another simplified arrangement of the connection between the controller <NUM> and the bypass switches <NUM>.

When operating multiple UPSs, such as the three UPSs 102a, 102b, 102c illustrated in <FIG>, the controller <NUM> may control one of the UPSs 102a-c to remain continuously coupled to the load <NUM> during the operation of system <NUM>. That is, the controller <NUM> may control the bypass switches <NUM> of the UPSs 102a, 102b to interrupt the input current through the respective UPS while maintaining the bypass switch <NUM> of the UPS 102c in a continuously conductive state. Such an arrangement may help avoid load interruptions in some instances.

Referring to <FIG>, the controller <NUM> may include embedded hardware or software components such as a control and regulation circuit <NUM> and timing circuitry <NUM>. The embedded hardware or software components of the controller <NUM> may interact with embedded components of the bypass switch <NUM> to operate each bypass switch, and in particular, each SCR within a bypass switch <NUM>. As illustrated, in certain examples, a single control signal may operate each bypass switch <NUM>, and in particular, all of the SCRs within each bypass switch <NUM>. In such an example, each SCR within a bypass switch <NUM> may share the same embedded electronics <NUM>, and each bypass circuit <NUM> may be coordinated with a single timing circuit <NUM>. Such an example offers many of the discussed advantages over previous SCR control arrangements. For example, a typical SCR control scheme may require a dedicated timing circuit and embedded electronics for each SCR. <FIG> illustrates another improved, and simplified, control arrangement, according to an example. As shown in <FIG>, each bypass circuit <NUM> may receive a single control signal from a dedicated timing circuit <NUM>.

In certain other examples, the input power may include three-phase electrical input power. In at least these examples, the bypass switch <NUM> of each UPS 102a-c may include a plurality of bypass switches, such as a bypass switch A, a bypass switch B, and a bypass switch C. Specifically, each bypass switch A-C of the plurality may correspond to a single phase of the three-phase electrical power. In one example, the controller <NUM> may provide a single control signal to each bypass switch A-C of the plurality to interrupt the input current through the corresponding bypass circuit <NUM>. However, in another example, the controller <NUM> may provide control signals to control each bypass switch A-C of the plurality per phase, where per phase control is desired. Further, in at least another example, the controller <NUM> may provide a single control signal to trigger all bypass switches A-C of the plurality simultaneously to interrupt the input current through the corresponding bypass circuit <NUM>. In still other examples, any other suitable control scheme may be used. When receiving three-phase electrical power, the power system <NUM> may also balance the output current among each UPS <NUM> per phase of the three-phase power.

Referring to <FIG>, illustrated is a graph <NUM> of the current through the bypass circuits of each parallel UPS of an example power system according to aspects of the invention. In particular, <FIG> includes a first trace <NUM> which represents the input current through the bypass circuit <NUM> of UPS 102a during the bypass mode of operation, a second trace <NUM> which represents the input current through the bypass circuit <NUM> of UPS 102b during the bypass mode of operation, and a third trace <NUM> which represents the input current through the bypass circuit <NUM> of UPS 102c during the bypass mode of operation. In the graph <NUM>, a value of the current is represented by the vertical axis (i.e., y-axis) and the time is represented by the horizontal axis (i.e., x-axis). <FIG> is a more detailed graph <NUM> illustrating the input current through a bypass circuit of an example UPS, such as the UPS 102a illustrated in <FIG>. <FIG> and <FIG> are discussed with continuing reference to the example power system <NUM> illustrated in <FIG>.

As discussed with reference to <FIG>, in certain examples the controller <NUM> is configured to operate the bypass switch <NUM> of a first UPS to interrupt the input current through the respective bypass circuit <NUM> for the duration of a first delay. Referring to <FIG>, one such interruption <NUM> is illustrated in the first trace <NUM>. The duration of the first delay is represented by the first time span <NUM>. As illustrated, in certain examples interrupting the input current through the respective bypass circuit <NUM> may include reducing the input current to a substantially zero value. As further illustrated, during the duration of the first delay, each of the other traces <NUM>, <NUM> instantaneously increases in magnitude. Moreover, during the duration of the first delay each of the other traces <NUM>, <NUM> is substantially continuous. That is, each of the other traces <NUM>, <NUM> is substantially sinusoidal (e.g., when the load is linear). Accordingly, controlled and dynamic interruption of the first trace (i.e., input current of the UPS 102a) enables the system <NUM> to balance the power provided to the load <NUM>, and in particular, provide a substantially equivalent RMS output current from each UPS 102a-c.

<FIG> further illustrates an interruption <NUM> in the second trace <NUM>. As illustrated, in various embodiments, the second interruption <NUM> may temporally follow the first interruption <NUM> (e.g., the first interruption <NUM> and the second interruption <NUM> are non-concurrent). The duration of the second interruption <NUM> is represented by time span <NUM>. Similar to the first interruption <NUM>, interrupting the input current through the respective bypass circuit <NUM> may include reducing the input current to a substantially zero value. During the duration of the second delay, each of the other traces <NUM>, <NUM> instantaneously increases in magnitude. While shown in <FIG> as having a shorter duration than the first delay, in various embodiments the duration of the second delay may be greater than, less than, or the same as the duration of the first delay. Specifically, the duration of the second delay may be dynamically determined by the controller <NUM> based at least in part on the monitored values of the input current. Accordingly, in various embodiments the second interruption <NUM> allows the system <NUM> to compensate for the interruption <NUM> in the first trace <NUM> and maintain a substantially balanced power output among the various UPSs 102a-c. That is, automatic and dynamic control of the second interruption <NUM> allows the system <NUM> to maintain a substantially equivalent RMS output current from each UPS 102a-c.

While illustrated in the example waveforms of <FIG> as occurring in a second trace <NUM>, in various embodiments the controller <NUM> may control the same bypass switch <NUM> to interrupt the input current through the corresponding bypass circuit <NUM> for any number of desired delays. That is, the controller <NUM> may interrupt the input current of the first UPS for the duration of the first delay and subsequently interrupt the same input current for the duration of the second delay. <FIG> illustrates one such example. Referring to <FIG>, a trace <NUM> represents the input current through the bypass circuit <NUM> of UPS 102a during the bypass mode of operation. <FIG> further shows a first interruption <NUM> in the first trace <NUM> and a second interruption <NUM> in the first trace <NUM>. The duration of the first delay is represented by the first time span <NUM> and the duration of the second delay is represented by the second time span <NUM>. While in one example, the first interruption <NUM> and the second interruption may occur during the same controlled time period (e.g., controlled time period <NUM>), in certain other examples, the first and second interruptions <NUM>, <NUM> may occur during different controlled time periods, as illustrated in <FIG>.

As discussed above, several aspects and embodiments perform processes for automatically balancing load sharing between each of a plurality of parallel UPSs during a bypass mode of operation. In some embodiments, these processes are executed by a power system, such as the power system <NUM> described above with reference to <FIG>. One example of such a process <NUM> is illustrated in <FIG>. The illustrated process <NUM> is discussed with continuing reference to the example power system <NUM> illustrated in <FIG>. In certain embodiments, the process <NUM> may include the acts of closing the bypass switch <NUM> of each of the UPSs 102a-c, monitoring an input current through the bypass circuit <NUM> of each of the UPSs 102a-c, identifying a first UPS of the UPSs 102a-c, controlling the bypass switch <NUM> of the first UPS to interrupt the input current through the bypass circuit <NUM> thereof, and providing a balanced output current, among the UPSs 102a-c, to the load <NUM>. It is appreciated that in various embodiments the acts <NUM> - <NUM> may be performed in the order discussed below. However, in various other embodiments, acts <NUM> - <NUM> may be performed in any other suitable order.

According to various embodiments, the process <NUM> may include receiving input power from a power source <NUM> at an input <NUM> of each UPS of a plurality of UPSs (e.g., UPSs 102a-c). For example, the input power may be received after the bypass switch <NUM> of each UPS 102a-c has been closed (act <NUM>). In response to receiving the input power, the process <NUM> may include monitoring the input current through the bypass circuit <NUM> of each UPS 102a-c during the bypass mode of operation (act <NUM>). In act <NUM>, the process <NUM> may further include identifying a first UPS of the UPSs 102a-c based on a determination of which input current has the largest magnitude (i.e., the lowest path of impedance). In certain examples, the processes for determining which input current has the largest magnitude may include processes such as comparing each input current to the input current through each of the other bypass circuits, comparing each input current to an average, and/or any other suitable processes for identifying the UPS with the largest input current magnitude.

Once a first UPS has been identified, in act <NUM> the process <NUM> may include controlling the at least one bypass switch <NUM> of the first UPS to interrupt the input current through the bypass circuit <NUM> of the first UPS for the duration of a first delay such that each UPS 102a-c of the plurality provides a substantially balanced output current, among the UPSs 102a-c, to the load <NUM>. For example, in act <NUM> the controller <NUM> may provide one or more control signals (e.g., signals <NUM>) to the corresponding bypass switch <NUM> of the first UPS to open the bypass switch <NUM>. In particular, the process <NUM> may include operating the bypass switch <NUM> of the first UPS to interrupt the input current such that the power provided to the load <NUM> is evenly distributed among each of the UPSs 102a-c. Accordingly, act <NUM> may include providing an evenly distributed power from each UPS 102a-c to the load.

In various examples, controlling the at least one bypass switch <NUM> of the first UPS may include reducing the input current through the bypass circuit <NUM> of the first UPS such that each UPS 102a-c of the plurality provides a substantially equivalent Root Mean Square (RMS) current to the load <NUM>. Moreover, during the duration of the first delay, the process <NUM> may include providing a control signal to each of the other UPSs (i.e., all of the UPSs excluding the first UPS) to maintain the respective bypass switch <NUM> in a closed position such that an output current waveform of each of the other UPSs is continuous during the duration of the first delay. That is, even though an interruption is introduced in the output current of the first UPS, the load <NUM> receives a full sinusoidal waveform from each of the other UPSs during the duration of the first delay. Responsive to providing the balanced output power to the load <NUM>, the process <NUM> may return to act <NUM>.

While not explicitly illustrated or described with reference to <FIG> for the convenience of description, the example process <NUM> illustrated therein may include further acts and processes. Examples of these additional acts and processes are described with reference to the example power system illustrated in <FIG>.

<FIG> illustrates another example process flow <NUM> for operating a power system including a plurality of UPSs coupled in parallel. In particular, <FIG> illustrates the interoperation of sub-processes 502a, 502b, 502c as executed by a first UPS, a second UPS, and a third UPS, respectively. In some embodiments, the process <NUM> is executed by a power system, such as the power system <NUM> described above with reference to <FIG>. Accordingly, the illustrated process <NUM> is discussed with continuing reference to the example power system <NUM> illustrated in <FIG>. While illustrated in <FIG> as including a first sub-process 502a executed by a first UPS (e.g., UPS 102a), a second sub-process 502b executed by a second UPS (e.g., UPS 102b), and a third sub-process 502c executed by a third UPS (e.g., UPS 102c), in certain other examples the number of sub-processes may correspond to the number of UPSs <NUM> within the system <NUM>. That is, in certain examples the process <NUM> may include more, or less, than three sub-processes.

Each sub-process 502a-c may be performed by the corresponding UPS 102a-c, or by the controller <NUM>. In certain examples, sub-process 502a may include the acts of calculating an RMS current (act 504a), calculating a duration of a first delay (act 506a), waiting for authorization to interrupt the input current for the duration of the first delay (act 508a), receiving a control signal to interrupt the input current (e.g., "ON order removed") (act 510a), waiting for a conclusion of the duration of the delay (act 512a), receiving a control signal to close the respective bypass switch to end the interruption (e.g., "ON order set") (act 514a), transmitting an authorization to interrupt the input current at another UPS (act 516a), and waiting for a subsequent cycle of operation (act 518a). Each of sub-processes 502b and 502c may include similar acts, as further illustrated in <FIG>.

In certain examples, each sub-process 502a-c may operate simultaneously during the operation of the power system <NUM>. Accordingly, in certain examples the operation of each UPS 102a-c may be interrelated. For example, the transmitted authorization of the first UPS 102a (act 516a) may act as the authorization required to prompt interruption of the input current at the second UPS 102b (act 508b). Similarly, the transmitted authorization of the second UPS 102b (act 516b) may act as the authorization required to prompt interruption of the input current at the third UPS 102c (act 508c). The transmitted authorization of the third UPS 102c (act 516c) may act as the authorization required to prompt interruption of the input current at the first UPS 102a (act 508a). Such an example may be particularly advantageous when each UPS 102a-c includes a dedicated controller <NUM>, as discussed above.

<FIG> illustrates an example block diagram of computing components forming a system <NUM> which may be configured to implement one or more aspects disclosed herein. For example, the system <NUM> may be communicatively coupled to the controller <NUM>, included within the controller <NUM>, or included within a UPS dedicated controller. The system <NUM> may also be configured operate multiple UPSs in parallel as discussed above.

The system <NUM> may include for example a computing platform such as those based on Intel PENTIUM-type processor, Motorola PowerPC, Sun UltraSPARC, Texas Instruments-DSP, Hewlett-Packard PA-RISC processors, or any other type of processor. System <NUM> may include specially-programmed, special-purpose hardware, for example, an application-specific integrated circuit (ASIC). Various aspects of the present disclosure may be implemented as specialized software executing on the system <NUM> such as that shown in <FIG>.

The system <NUM> may include a processor/ASIC <NUM> connected to one or more memory devices <NUM>, such as a disk drive, memory, flash memory or other device for storing data. Memory <NUM> may be used for storing programs and data during operation of the system <NUM>. Components of the system <NUM> may be coupled by an interconnection mechanism <NUM>, which may include one or more buses (e.g., between components that are integrated within a same machine) and/or a network (e.g., between components that reside on separate machines). The interconnection mechanism <NUM> enables communications (e.g., data, instructions) to be exchanged between components of the system <NUM>. The system <NUM> also includes one or more input devices <NUM>, which may include for example, a keyboard or a touch screen. The system <NUM> includes one or more output devices <NUM>, which may include, for example, a display. In addition, the system <NUM> may contain one or more interfaces (not shown) that may connect the system <NUM> to a communication network, in addition or as an alternative to the interconnection mechanism <NUM>.

The system <NUM> may include a storage system <NUM>, which may include a computer readable and/or writeable nonvolatile medium in which signals may be stored to provide a program to be executed by the processor or to provide information stored on or in the medium to be processed by the program. The medium may, for example, be a disk or flash memory and in some examples may include RAM or other non-volatile memory such as EEPROM. In some embodiments, the processor may cause data to be read from the nonvolatile medium into another memory <NUM> that allows for faster access to the information by the processor/ASIC than does the medium. This memory <NUM> may be a volatile, random access memory such as a dynamic random access memory (DRAM) or static memory (SRAM). It may be located in storage system <NUM> or in memory system <NUM>. The processor <NUM> may manipulate the data within the integrated circuit memory <NUM> and then copy the data to the storage <NUM> after processing is completed. A variety of mechanisms are known for managing data movement between storage <NUM> and the integrated circuit memory element <NUM>, and the disclosure is not limited thereto. The disclosure is not limited to a particular memory system <NUM> or a storage system <NUM>.

The system <NUM> may include a computer platform that is programmable using a high-level computer programming language. The system <NUM> may be also implemented using specially programmed, special purpose hardware, e.g. an ASIC. The system <NUM> may include a processor <NUM>, which may be a commercially available processor such as the well-known Pentium class processor available from the Intel Corporation. Many other processors are available. The processor <NUM> may execute an operating system which may be, for example, a Windows operating system available from the Microsoft Corporation, MAC OS System X available from Apple Computer, the Solaris Operating System available from Sun Microsystems, or UNIX and/or LINUX available from various sources. Many other operating systems may be used.

The processor and operating system together may form a computer platform for which application programs in high-level programming languages may be written. It should be understood that the disclosure is not limited to a particular computer system platform, processor, operating system, or network. Also, it should be apparent to those skilled in the art that the present disclosure is not limited to a specific programming language or computer system. Further, it should be appreciated that other appropriate programming languages and other appropriate computer systems could also be used.

Accordingly, aspects and embodiments are generally directed to systems and methods for automatically balancing load sharing between each of a plurality of parallel UPSs during a bypass mode of operation. The described aspects and embodiments do not require cable length adjustments or the addition of expensive and complicated chokes to balance load sharing. By interrupting the input current through the bypass circuit of a first UPS for the duration of a first delay, and dynamically adjusting the duration of the first delay period, an RMS current of each UPS of the plurality can be controlled to provide a substantially equivalent RMS current to the load, despite differences in components and cabling. As the output current of each UPS is set to substantially the same output current value, the deviation between load sharing portions of each UPS is relatively low. Accordingly, more than four UPSs can be successfully coupled together in parallel while reducing many of the risks associated with performing load sharing between multiple UPSs coupled in parallel. While the systems and methods for providing equal load sharing discussed above are utilized with a parallel UPS system including on-line UPSs, in certain other examples, the systems and methods may be utilized with other types of UPSs or power systems.

Claim 1:
A power system (<NUM>) comprising:
a plurality of uninterruptible power supplies, UPSs, including a first UPS, a second UPS, and a third UPS;
the first UPS including:
an input (<NUM>) configured to be coupled to a power source (<NUM>) and configured to receive input power from the power source (<NUM>);
an output (<NUM>) configured to be coupled to a load and configured to provide output power to the load based at least in part on the input power; and
a first bypass circuit (<NUM>) interposed between the input (<NUM>) and the output (<NUM>) and including at least a first bypass switch (<NUM>), the at least first bypass switch (<NUM>) being positioned to couple the input (<NUM>) and the output (<NUM>) in a bypass mode of operation and decouple the input (<NUM>) and the output (<NUM>) in an on-line mode of operation; and
a controller (<NUM>) coupled to the first UPS, the second UPS, and the third UPS and configured to:
monitor a current through the first bypass circuit (<NUM>) of the first UPS during the bypass mode of operation, and to monitor the current through a second bypass circuit of the second UPS during the bypass mode of operation;
control the at least first bypass switch of the first UPS to interrupt the current through the first bypass circuit of the first UPS for the duration of a first delay during the bypass mode of operation such that the power provided to the load (<NUM>) is evenly distributed among each of the plurality of UPSs; and
the controller (<NUM>) is further configured to control the bypass switch of each UPS of the plurality of UPS's during the duration of the first delay such that an output current waveform of each UPS of the plurality of UPS's, other than the first UPS, is continuous.