Patent Description:
As known, electronic apparatuses are popular, used for example both in the consumer electronics field and in the industrial and automotive fields, which incorporate one or more sensors configured to each detect one or more physical quantities associated with the use of the respective electronic apparatus.

For example, the one or more sensors may be accelerometers, gyroscopes, temperature, pressure, electrical resistance, mechanical stress, strain sensors.

It is also known to make such sensors using MEMS technology, which allows sensors having small dimensions, low energy consumption and high detection accuracy to be obtained.

A MEMS sensor is configured to convert a physical quantity into an electrical signal, of analog type, whose trend over time is a function of the trend over time of the respective detected physical quantity.

It is known to design an electronic apparatus incorporating the MEMS sensor so that the analog signal generated by the MEMS sensor is, in sequence, processed by an analog front-end, for example is amplified; converted into a digital signal using a sampling frequency fs; and filtered by a filtering stage, for example by a low-pass filter, thus obtaining an output signal from the MEMS sensor having a sample frequency equal to the sampling frequency fs.

The analog front-end, the sampling frequency fs and the subsequent filtering allow the output signal to meet a set of technical requirements of the MEMS sensor and of the electronic apparatus incorporating the MEMS sensor. For example, the sampling frequency fs is chosen so to comply with the Nyquist sampling theorem relating to the band of the analog signal output by the MEMS sensor, and the filtering is such that it suppresses noise and/or possible demodulation tones generated at output by the analog-to-digital converter.

Furthermore, if the MEMS sensor comprises a mechanical oscillator, the output data rate from the MEMS sensor is determined by the operating frequency at which the mechanical oscillator is actuated.

As a result, the output data rate from the known MEMS sensor has a low level of personalization.

In order to increase the range of available values of the output data rate, it is known to incorporate a phase-locked loop (PLL) into the electronic apparatus. However, the output data rate is only changeable within the range of frequencies available in the oscillator used to obtain the PLL circuit. Furthermore, the PLL circuit has a high consumption of die area and energy and, in specific applications, meeting the desired design requirements is not always possible.

Alternatively, if the MEMS sensor comprises an electronic oscillator such as a clock, methods for trimming an oscillation frequency of the electronic oscillator are known, which also allow the output data rate from the MEMS sensor to be changed. However, such trimming methods are capable of changing the oscillation frequency only within a limited range of values, for example by a value comprised within ± <NUM>%.

It is also known to incorporate, in the electronic apparatus, a decimation circuit capable of scaling the output signal from the MEMS sensor by an integer factor, in particular in power of two. However, even this solution does not allow a high degree of personalization of the output data rate from the MEMS sensor.

Documents <CIT> and <CIT> describe further examples of methods and systems for modifying the output data rate of a sensor.

The aim of the present invention is to overcome the drawbacks of the prior art.

According to the present invention a sensor configured to personalize an output data rate, an electronic apparatus comprising the sensor and a method for personalizing an output data rate are provided as defined in the attached claims.

For a better understanding of the present invention, an embodiment thereof is now described, purely by way of nonlimiting example, with reference to the attached drawings, wherein:.

Hereinafter, unless otherwise specified, reference will be made to the frequency of a discretized (digital) signal to indicate the sample frequency thereof, i.e. the data rate at which the samples of the discretized signal are provided at output by the respective block generating it.

<FIG> schematically shows an electronic apparatus <NUM> comprising a sensor <NUM>, a memory <NUM> and a processing unit <NUM>, operatively coupled to each other.

The sensor <NUM> comprises a detection unit <NUM>, a signal conditioning stage <NUM> and an output data rate (ODR) modification block <NUM>, hereinafter also referred to as ODR modification block <NUM>.

The sensor <NUM>, in particular the detection unit <NUM>, is configured to detect one or more physical quantities associated with the operation of the electronic apparatus <NUM> and generate one or more electrical signals, here an analog signal SA, as a function of such physical quantities.

The sensor <NUM> may be, for example, an acceleration sensor, a temperature sensor, a pressure sensor, a mechanical stress sensor, an electrical resistance sensor, a gyroscope, etc..

In this embodiment, the sensor <NUM> is of MEMS type, that is the detection unit <NUM> is obtained using MEMS technology, and is formed in a die of semiconductor material, in particular of silicon.

In particular, in this embodiment, the detection unit <NUM> comprises a sensing element <NUM> and a mechanical oscillator <NUM>.

The mechanical oscillator <NUM> comprises a movable and/or deformable structure, for example deformable in an elastic manner, such as a cantilever, a membrane or a structure having any other shape, having a resonance frequency fr.

In use, the mechanical oscillator <NUM> is actuated, for example according to an electrostatic, piezoelectric or electromagnetic actuation principle, so that the respective movable and/or deformable structure oscillates at an operating frequency fo. In general, the operating frequency fo is a function of the resonance frequency fr, for example it is equal to the resonance frequency fr.

The mechanical oscillator <NUM> is configured so that the physical quantity to be detected modifies the movement of the movable and/or deformable structure of the mechanical oscillator <NUM>, for example modifying phase, amplitude and/or frequency thereof.

The sensing element <NUM> is configured to detect the movement of the movable and/or deformable structure of the mechanical oscillator <NUM>, for example according to an electrostatic, piezoresistive, piezoelectric or electromagnetic detection principle, and convert it into the analog signal SA. The trend of the analog signal SA over time is thus indicative of the movement variations of the movable and/or deformable structure of the mechanical oscillator <NUM> caused by the physical quantity to be detected.

The signal conditioning stage <NUM> is configured to receive the analog signal SA at input and provide a corresponding digital signal SD, obtained by sampling the analog signal SA, at output.

In detail, the signal conditioning stage <NUM> comprises an analog front-end (AFE) <NUM>, an analog-to-digital converter <NUM> and a filter <NUM>.

The analog front-end <NUM> comprises, for example, one or more operational amplifiers and is configured, for example, to filter, amplify or demodulate the analog signal SA, providing a conditioned analog signal S'A at output.

The analog-to-digital converter <NUM> is configured to receive the conditioned analog signal S'A at input and provide a sampled signal SS at output. The sampled signal SS is obtained by discretizing the conditioned analog signal S'A at a sampling frequency fs.

The sampling frequency fs is chosen during the design step on the basis of the requirements of the specific application. For example, the sampling frequency fs is such that it complies with the Nyquist sampling theorem, i.e. greater than twice the operating frequency fo of the mechanical oscillator <NUM> of the detection unit <NUM>.

The sampled signal SS output by the analog-to-digital converter <NUM> has therefore a sample frequency which is equal to the sampling frequency fs.

The filter <NUM> comprises one or more filters of low-pass or band-pass type, has one or more respective cut-off frequencies and is configured to receive the sampled signal SS at input and provide the digital signal SD at output. The digital signal SD is thus obtained by filtering the sampled signal Ss, for example to remove unwanted spectral components thereof introduced by the analog-to-digital converter <NUM>, by the analog front-end <NUM> and/or by the detection unit <NUM>.

According to the specific application and the design requirements, for example to meet a die area occupation requirement, the filter <NUM> may also be configured to reduce the frequency of the sampled signal SS, for example by an integer reduction factor, for example comprised between <NUM> and <NUM>.

Therefore, the digital signal SD has a conditioned sampling frequency f's, which, here, is lower than the sampling frequency fs. In other applications, the conditioned sampling frequency f's is equal to the sampling frequency fs.

The ODR modification block <NUM> is configured to receive the digital signal SD at input and provide an output signal So at output, having an output frequency fou which is different from the conditioned sampling frequency f's of the digital signal SD.

The output signal SO is obtained from the digital signal SD, modifying the sample frequency thereof, as described in detail hereinafter, on the basis of a parameters set, or group, K.

The output signal SO forms the output signal from sensor <NUM>.

The electronic apparatus <NUM> also comprises an interface <NUM> and a configuration register <NUM>. The interface <NUM> is configured to receive, from a user of the electronic apparatus <NUM>, a user signal SU indicative of the desired output frequency fou of the output signal SO from the sensor <NUM>.

The interface <NUM> is configured to convert the user signal SU into the parameters set K and store the parameters set K in the configuration register <NUM>.

According to another embodiment, the user signal SU is converted into the parameters set K by the processing unit <NUM> and the interface <NUM> functions as a signal transfer bus between the processing unit <NUM> and the configuration register <NUM>.

The parameters set K is formed by an interpolation factor I<NUM> and by a first decimation factor D<NUM>.

Furthermore, in this embodiment, the parameters set K also comprises a second decimation factor M.

As shown in <FIG>, the ODR modification block <NUM> comprises an interpolation device, or interpolator, <NUM> and a first decimator <NUM>.

The interpolator <NUM> includes an interpolation filter <NUM>, is configured to receive the interpolation factor I<NUM> and the digital signal SD (at the conditioned sampling frequency f's) at input and is configured to provide an interpolated digital signal SD,int at output. The interpolated digital signal SD,int has an interpolation frequency fint that is greater than the conditioned sampling frequency f's. In particular, here, the interpolation frequency fint is obtained by increasing the conditioned sampling frequency f's by the interpolation factor I<NUM>.

The interpolator <NUM>, in particular the respective interpolation filter <NUM>, may be obtained, in a known manner, using for example a linear or non-linear phase interpolation circuit, in particular of CIC ("Cascaded Integrator-Comb"), spline, Lagrangian, Hermitian type.

The first decimator <NUM> is configured to receive the interpolated digital signal SD,int and the first decimation factor D<NUM> at input.

In detail, as shown in <FIG>, the first decimator <NUM> comprises a filtering stage <NUM>, a downsampler <NUM> coupled to a counter <NUM>, and a gain block <NUM>.

The filtering stage <NUM> is a low-pass filter, for example an infinite impulse response (IIR) or a finite impulse response (FIR) filter such as a CIC circuit, and is configured to receive the first decimation factor D<NUM> and the interpolated digital signal SD,int at input and provide a filtered signal F at output.

The filtering stage <NUM> has a respective transfer function H(f, D<NUM>) having a respective cut-off frequency fc, which is chosen on the basis of the output frequency fou, in particular on the basis of the first decimation factor D<NUM>.

For example, the cut-off frequency fc is chosen in such a way that the ratio between the frequency of the decimated digital signal SD,dec and the cut-off frequency fc complies with the Nyquist sampling theorem. Furthermore, the cut-off frequency fc is chosen to suppress the high-frequency spectral images introduced by the interpolator <NUM>.

The transfer function H(f, D<NUM>) of the filtering stage <NUM>, in particular the respective cut-off frequency fc, may be modified, in use, in a known manner. For example, in case the filtering stage <NUM> is formed by a CIC filter of order N, the relative coefficients which determine the transfer function H(f, D<NUM>) thereof may be determined, in a known manner, from the ratio between the frequency of the decimated digital signal SD,dec and the frequency of the interpolated digital signal SD,int. In case the filtering stage <NUM> is formed by an IIR filter, the relative coefficients that determine the transfer function H(f, D<NUM>) thereof may be chosen from a specific look-up table, for example stored in the memory <NUM>.

The counter <NUM> is configured to receive the first decimation factor D<NUM> at input and provide a counter command signal SC, indicative of the first decimation factor D<NUM>, at output.

According to an embodiment, the sensor <NUM> comprises a clock configured to generate a clock signal having a respective frequency, for example of the order of megahertz, and the counter <NUM> is configured to receive also the clock signal at input. Furthermore, the counter <NUM> is configured to store a count number and to increase the count number by one unit at each cycle of the clock signal.

In this embodiment, the first decimation factor D<NUM> indicates a number of clock cycles.

Furthermore, the counter <NUM> is configured to compare, at each clock cycle, the count number with the first decimation factor D<NUM>. If the count number is equal to the first decimation factor D<NUM>, then the counter <NUM> generates the counter command signal SC.

The downsampler <NUM> is configured to receive the filtered signal F and the counter command signal SC at input and provide a downsampled signal DS at output. The downsampled signal DS is obtained from the filtered signal F. In detail, the counter command signal SC causes the downsampler <NUM> to provide every D<NUM>-th sample of the filtered signal F at output. In other words, the sample frequency of the downsampled signal DS is lower than the filtered signal F, as described in detail hereinafter.

The gain block <NUM> is configured to receive the downsampled signal DS and the first decimation factor D<NUM> at input, and provide the decimated digital signal SD,dec at output.

In detail, the gain block <NUM> is configured to amplify or attenuate, by a gain factor G, the value of the samples of the downsampled signal DS corresponding to a DC component (i.e. at zero frequency) of the downsampled signal DS. For example, the zero-frequency component of the downsampled signal DS is identified by performing a Fourier transform of the downsampled signal DS. The gain factor G is chosen as a function of the first decimation factor D<NUM> and as a function of the type of filter used in the filtering stage <NUM>.

In particular, if the filtering stage <NUM> is obtained using an IIR filter, then the gain factor G may be chosen from a specific look-up table, stored in the memory <NUM>. If the filtering stage <NUM> is obtained using a CIC filter, then the gain factor G may be calculated as <NUM>/D<NUM>N, wherein N is the order of the CIC filter of the filtering stage <NUM>.

Again with reference to <FIG>, the ODR modification block <NUM> further comprises a second decimator <NUM> including a decimation filter <NUM>. The decimation filter <NUM> is configured, in a known manner, to perform a power-of-two decimation of the discretized signal received at input. In detail, the second decimator <NUM> is configured to receive the decimated digital signal SD,dec and the second decimation factor M at input and provide the output signal SO at output.

In practice, in order to generate the output signal SO, the second decimator <NUM> downsamples the decimated digital signal SD,dec, reducing the sample frequency thereof by a factor <NUM>M. In other words, the output signal SO is obtained by providing a sample SOi at output every <NUM>M-th sample of the decimated digital signal SD,dec. According to an embodiment, the second decimator <NUM> is also configured to filter the decimated digital signal SD,dec, for example so that the output signal SO complies with the Nyquist sampling theorem.

In use, the sensor <NUM> performs a personalization of its output data rate, for example using a personalization method <NUM> as described hereinafter with reference to <FIG>.

The method <NUM> starts when a user of the electronic apparatus <NUM> indicates a desired output data rate ODRE from sensor <NUM>, i.e. the desired output frequency fou of the output signal SO, by sending the user signal SU to the interface <NUM> (<FIG>).

For example, the user signal SU may be indicative of a choice, by the user, of the desired output data rate ODRE from a list of predefined values stored in the memory <NUM>. A parameters set K, which is also stored in the memory <NUM>, corresponds to each predefined value of the desired output data rate ODRE.

Alternatively, the user may indicate, through the user signal SU, directly one or more of the parameters that form the parameters set K.

When the interface <NUM> receives the user signal SU, it determines the parameters set K; that is, here, determines the interpolation factor I<NUM>, the first decimation factor D<NUM> and the second decimation factor M, and writes them in the configuration register <NUM>.

Purely by way of example, in this embodiment, the interpolation factor I<NUM> may be equal to <NUM>, while the first and the second decimation factors D<NUM>, M may be variable, according to the desired output data rate ODRE chosen by the user. However, the interpolation factor I<NUM> may have a different value, in particular equal to a power of two.

In particular, here, the first decimation factor D<NUM> may be comprised between <NUM> and <NUM>, and the second decimation factor M may be comprised between <NUM> and <NUM>.

Subsequently, step <NUM>, the sensor <NUM>, in particular the ODR modification block <NUM>, receives the parameters set K and configures the respective interpolator <NUM>, the respective first decimator <NUM> and the respective second decimator <NUM>.

In detail, the interpolator <NUM> receives the interpolation factor I<NUM>, from which it sets the coefficients of the respective interpolation filter <NUM>, so that the interpolation filter <NUM> performs an interpolation equal to the interpolation factor I<NUM>. The first decimator <NUM> receives the first decimation factor D<NUM> and consequently configures the respective filtering stage <NUM>, the counter <NUM> and the gain block <NUM>.

Furthermore, here, the second decimator <NUM> receives the second decimation factor M, from which it sets the coefficients of the respective decimation filter <NUM>, so that the decimation filter <NUM> performs a decimation of value <NUM>M, wherein M is the second decimation factor.

In use, the ODR modification block <NUM> receives the digital signal SD from the signal conditioning stage <NUM>, at the conditioned sampling frequency f's. By way of example, consider for example that the conditioned sampling frequency f's is <NUM>.

When the modification block receives the digital signal SD, the digital signal SD is upsampled, upsampling <NUM>, by the interpolator <NUM> (<FIG>). The interpolator <NUM> generates the interpolated signal SD,int, whose sample frequency is increased by the interpolation factor I<NUM> with respect to the sample frequency of the digital signal SD. The sample frequency of the interpolated digital signal SD,int is therefore given by the formula f's·I<NUM>, and is therefore equal, in the considered example, to <NUM>.

The first decimator <NUM> receives the interpolated digital signal SD,int at input and downsamples (first decimation <NUM>) the interpolated digital signal SD,int by an amount indicated by the first decimation factor D<NUM>. As a result, the decimated digital signal SD,dec has a sample frequency given by f's·I<NUM>/D<NUM>. For example, considering the present example wherein the first decimation factor D<NUM> is comprised in the range <NUM>-<NUM>, and wherein the frequency of the interpolated digital signal SD,int is <NUM>, the sample frequency of the decimated digital signal SD,dec is comprised in the range <NUM>-<NUM>.

In detail, as shown in <FIG>, the first decimation <NUM> of the method <NUM> of <FIG> comprises in succession filtering 115A, downsampling 115B and amplification 115C.

During filtering 115A, the filtering stage <NUM> of the first decimator <NUM> receives the interpolated digital signal SD,int and the interpolated digital signal SD,int is subject to a low-pass filtering. The filtering stage <NUM> thus allows high-frequency components of the interpolated digital signal SD,int introduced by the interpolator <NUM> in the upsampling <NUM> to be removed.

Subsequently, during downsampling 115B, the downsampler <NUM> receives the filtered signal F and the counter command signal SC at input and provides the downsampled signal DS, which is formed by each D<NUM>-th sample of the filtered signal F, at output.

The gain block <NUM> receives the downsampled signal DS at input and amplifies (amplification 115C) the DC component (at zero frequency) thereof, to compensate for the attenuation caused by the filtering stage <NUM>, as described hereinabove.

According to a different embodiment, the gain block <NUM> may be configured both to amplify and to attenuate the DC component of the downsampled signal DS, depending on whether the filtering stage <NUM> has introduced an attenuation or an amplification, respectively, in the filtered signal F.

Again with reference to <FIG>, the decimated digital signal SD,dec output by the gain block <NUM> (and therefore by the first decimator <NUM>) is subject to a second decimation <NUM>. In detail, the second decimator <NUM> receives the decimated digital signal SD,dec at input and reduces the sample frequency thereof by an amount <NUM>M, wherein M is the second decimation factor. In other words, the output signal SO is formed by each <NUM>M-th sample of the decimated digital signal SD,dec.

The output signal SO from the ODR modification block <NUM>, and therefore from the sensor <NUM>, thus obtained, may be provided to further devices, internal or external to the electronic apparatus <NUM> and not shown here, for a subsequent processing.

Therefore, the desired output sample rate ODRE, i.e. the output frequency fou of the samples of the output signal SO, is overall related to the conditioned sampling frequency f's of the digital signal SD by the formula ODRE = f's·I<NUM>/D<NUM>/<NUM>M.

As a result, finally, the electronic apparatus <NUM> allows, using the method <NUM>, to personalize the frequency at which the sensor <NUM> provides at output the data relating to the physical quantity detected by the detection unit <NUM> (and therefore derived from the sampling of the analogue signal SA).

In particular, as apparent from what has been described hereinabove, the presence of the interpolator <NUM> and the first decimator <NUM> allows any ratio, either integer or rational, between the output frequency fou of the output signal SO and the conditioned sampling frequency f's to be obtained.

By suitably choosing the values of the parameters set K, it is also possible to cause the output frequency fou of the output signal SO to be greater than the conditioned sampling frequency f's.

As a result, the ODR modification block <NUM>, in particular the interpolator <NUM> and the first decimator <NUM>, confer high versatility to the electronic apparatus <NUM>, while allowing it to meet the band and sampling requirements of a specific application. In fact, the ODR modification block <NUM> is arranged in cascade to the signal conditioning stage <NUM>, which is designed to cause the digital signal SD to meet such requirements of the specific application. For example, the sampling frequency fs of the analog-to-digital converter <NUM> and the cut-off frequency of the filter <NUM> are chosen as a function of the band of the analog signal SA and/or the operating frequency fo of the mechanical oscillator <NUM>.

Additionally, the second decimator <NUM> confers a further degree of freedom in modifying the output frequency fou.

The electronic apparatus <NUM> may therefore be used in multiple applications, which require different values of output data rate from the sensor <NUM>, for example comprised between <NUM> and <NUM>.

Furthermore, the ODR modification block <NUM> also allows a variation in the output data rate of the sensor <NUM> from a respective design nominal value to be compensated for.

The variation in the output data rate may in fact be caused by possible deviations of the resonance frequency fr of the mechanical oscillator <NUM> from a respective design nominal value.

For example, the variation in the output data rate of the sensor <NUM> may be caused by variabilities of the manufacturing process of the detection unit <NUM> of the sensor <NUM>. In this case, a deviation of the resonance frequency fr from the respective design nominal value would also lead to a variation in the operating frequency fo. As a result, also the sampling frequency fs, which is chosen as a function of the operating frequency fo, would be subject to a variation which in turn, in the absence of the ODR modification block <NUM>, would cause a deviation of the output data rate of the sensor from the respective design nominal value.

The variation of the output data rate may also be caused by possible deviations of the oscillation frequency of an electronic oscillator, for example a clock, of the sensor <NUM> with respect to a design nominal value.

Therefore, the present sensor allows deviations of the output data rate from the sensor itself to be corrected, with respect to the desired nominal value.

Furthermore, the fact that the gain block <NUM> is arranged in cascade to the downsampler <NUM>, and therefore the amplification 115C of <FIG> of the first decimator <NUM> is performed after the respective downsampling 115B of <FIG>, allows the sensor <NUM>, and therefore the electronic apparatus <NUM>, to have a low energy consumption. In fact, the gain block <NUM> is configured to operate at the sample frequency of the downsampled signal DS, which is lower, for example, than the sample frequency of the filtered signal F output by the filtering stage <NUM>. Vice versa, for example, if the amplification 115C was carried out before the downsampling 115B, the gain block <NUM> should be configured to operate at the frequency of the filtered signal F (which is higher than the frequency of the downsampled signal DS), and therefore would entail a greater energy consumption of the sensor <NUM>, and therefore of the electronic apparatus <NUM>.

Finally, it is clear that modifications and variations may be made to the present sensor, the present electronic apparatus and the present method for personalizing the output data rate described and illustrated herein without thereby departing from the protective scope of the present invention, as defined in the attached claims.

For example, the steps of the method <NUM> of <FIG> may be obtained both by using a hardware solution, through dedicated circuits, and by using a software solution, through dedicated computer programs.

For example, the sensor <NUM> may be formed in a single die or in multiple dice of semiconductor material. In particular, the detection unit <NUM> may be formed in a first die and the signal conditioning stage <NUM> and the ODR modification block <NUM> may be formed in a second die. Alternatively, the analog circuits, here the analog front-end <NUM>, and the digital circuits, here the analog-to-digital converter <NUM>, the filter <NUM> and the ODR modification block <NUM>, may be formed on two different dies.

Claim 1:
A sensor (<NUM>) configured to provide a digital output signal (SO), the sensor comprising:
a digital detector (<NUM>), configured to detect a physical quantity and generate a conditioned digital signal (SD) indicative of the detected physical quantity; and
a rate modification stage (<NUM>), configured to receive the conditioned digital signal and a group of parameters (K), the group of parameters comprising an interpolation factor (I<NUM>) and a downsampling factor (D<NUM>, M), and to provide the digital output signal,
wherein the rate modification stage comprises an interpolator (<NUM>) and a decimation element (<NUM>, <NUM>), the interpolator being configured to receive and upsample the conditioned digital signal based on the interpolation factor and to provide an interpolated signal (SD,int), and the decimation element being configured to downsample the interpolated signal based on the downsampling factor, thereby generating the digital output signal,
wherein the decimation element comprises a first decimator (<NUM>) including a filtering stage (<NUM>), a downsampling stage (<NUM>, <NUM>) and a gain stage (<NUM>); the filtering stage (<NUM>) comprising a low-pass filter having a respective cut-off frequency (fc) and being configured to receive the interpolated signal (SD,int) and generate a filtered signal (F); the downsampling stage (<NUM>, <NUM>) being configured to downsample the filtered signal using a first decimation factor (D<NUM>) and to generate a downsampled signal (DS) having a DC component; and the gain stage (<NUM>) being configured to amplify or attenuate the DC component of the downsampled signal by a gain value (G),
wherein the cut-off frequency of the filtering stage (<NUM>) and the gain value of the gain stage (<NUM>) are a function of the first decimation factor (D<NUM>).