Patent Description:
A nonvolatile storage device is used to store data in a computing system such that the data are retained even when a power is interrupted. A storage device may include a nonvolatile memory such as a flash memory, a phase change memory, a magnetic memory, a ferroelectric memory, or a resistive memory and may be called auxiliary storage in a hierarchical structure of the computing system.

The operating speed of conventional storage devices has been considered a performance bottleneck. However, as storage devices have adopted nonvolatile memory-based solid state drives, instead of conventional hard disk drives, the communication speed between a host device and the storage device - instead of the operating speed of the storage device - has become the performance bottleneck.

Accordingly, the development of protocols defining a communication method between the host device and storage device have become an important area of consideration. In particular, as clock speeds associated with a communication protocol increase, signal integrity and a power integrity may become impaired.

<CIT> discloses: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

<CIT> discloses: A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.

Embodiments of the inventive concept provide a memory package providing improved signal integrity and improved power integrity with reduced costs by supporting package mirroring without changing a legacy structure of a nonvolatile memory chip and an operating method of the storage device.

According to an embodiment, a memory package includes; a first memory chip including first memory pads, and a buffer chip including first buffer pads respectively connected with the first memory pads and second buffer pads connected with an external device, wherein the buffer chip respectively communicates signals received via the second buffer pads to the first buffer pads in response to a swap enable signal having a disabled state, and the buffer chip swaps signals received via the second buffer pads to generate first swapped signals, and respectively communicates the first swapped signals to the first buffer pads in response to the swap enable signal having an enabled state.

According to an example for better understanding the invention, a storage device includes; a printed circuit board, a first memory package disposed on an upper surface of the printed circuit board and including a first package substrate, first memory chips stacked on the first package substrate, and a first buffer chip disposed on the first package substrate and electrically connecting the first memory chips with first solder balls associated with the first memory package, wherein the first buffer chip enables a swap of signals at the first solder balls in response to a swap enable signal, and a second memory package disposed on a lower surface of the printed circuit board and including a second package substrate, second memory chips stacked on the second package substrate, and a second buffer chip disposed on the second package substrate and electrically connecting the second memory chips with second solder balls associated with the second memory package, wherein the second buffer chip disables a swap of signals at the second solder balls in response to the swap enable signal.

According to an embodiment, an operating method for a storage device including memory chips and a buffer chip includes; receiving first signals from an external device at the buffer chip, swapping the first signals at the buffer chip in response to a swap enable signal to generate swapped first signals, communicating the swapped first signals to at least one of the memory chips, and communicating the first signals to at least another one of the memory chips, receiving second signals from memory chips at the buffer chip, swapping the second signals at the buffer chip in response to the swap enable signal to generate swapped first signals, and communicating the swapped second signals and the second signals to the external device.

The above and other objects and features of the inventive concept will become more apparent to those skilled in the art upon consideration of the following detail description together with the accompanying drawings, in which:.

Certain embodiments of the inventive concept will now be described in some additional detail with reference to the accompanying drawings. Throughout the written description and drawings, like reference numbers and labels are used to denote like or similar elements, components and/or features.

Throughout the written description certain geometric or spatial terms may be used to highlight relative relationships between elements, components and/or features with respect to embodiments of the inventive concept. Those skilled in the art will recognize that such terms are relative in nature, arbitrary in descriptive context and/or directed to certain aspect(s) of the illustrated embodiments. Such geometric terms may include, for example: height/width; vertical/horizontal; upper/lower; higher/lower; closer/farther; thicker/thinner; proximate/distant; above/below; under/over; upper/lower; center/side; surrounding; overlay/underlay; etc..

Figure (<FIG> is a perspective diagram and <FIG> is a cross-sectional diagram collectively illustrating a memory package <NUM> according to embodiments of the inventive concept.

Referring to <FIG> and <FIG>, the memory package <NUM> may include a package substrate <NUM>, package pads <NUM>, first package wires <NUM>, second package wires <NUM>, a mold <NUM>, solder balls <NUM>, a first nonvolatile memory chip <NUM>, a second nonvolatile memory chip <NUM>, a third nonvolatile memory chip <NUM>, a fourth nonvolatile memory chip <NUM> (hereafter, collectively referred to as "first to fourth nonvolatile memory chips <NUM> to <NUM>") and a buffer chip <NUM>.

In some embodiments, the package substrate <NUM> may be a printed circuit board (PCB). The package substrate <NUM> may electrically connect the package pads <NUM> with the solder balls <NUM>. For example, the package substrate <NUM> may include "wires" <NUM> (e.g., through-wires and/or through contacts) that route (and/or reroute) electrical connections among the various package pads <NUM> and the solder balls <NUM>.

The package pads <NUM> may be disposed on an upper surface of the package substrate <NUM>. Here, the first package wires <NUM> may respectively connect the package pads <NUM> with the buffer chip <NUM>. That is, the first package wires <NUM> may be respectively connected between at least one of the package pads <NUM> and at least one of first buffer pads <NUM> disposed (e.g.,) on an upper surface of the buffer chip <NUM>.

The second package wires <NUM> may respectively connect second buffer pads <NUM> of the buffer chip <NUM> with at least one of the first to fourth nonvolatile memory chips <NUM> to <NUM>. In some embodiments, for example, first memory pads <NUM> of the first nonvolatile memory chip <NUM>, second memory pads <NUM> of the second nonvolatile memory chip <NUM>, third memory pads <NUM> of the third nonvolatile memory chip <NUM> and/or fourth memory pads <NUM> of the fourth nonvolatile memory chip <NUM> may be variously (e.g., respectively and sequentially) connected by the second package wires <NUM>. That is, in the illustrated example of <FIG>, the second package wires <NUM> respectively and sequentially connect the second buffer pads <NUM> with the first memory pads <NUM>, the second memory pads <NUM>, the third memory pads <NUM>, and the fourth memory pads <NUM>. Accordingly, each of the second package wires <NUM> may be commonly connected with a corresponding pad of the first memory pads <NUM>, a corresponding pad of the second memory pads <NUM>, a corresponding pad of the third memory pads <NUM> and a corresponding pad of the fourth memory pads <NUM>.

Those skilled in the art will recognize that a number of first buffer pads <NUM> and/or a number of first package wires <NUM> may be different from a number of second buffer pads <NUM> and/or a number of second package wires <NUM>. For example, the number of first buffer pads <NUM> and/or the number of first package wires <NUM> may exceed the number of second buffer pads <NUM> and/or the number of second package wires <NUM>. That is, one or more signals communicated from an external device to the buffer chip <NUM> via the solder balls <NUM> and the wires <NUM> associated with the package substrate (e.g., a PCB) <NUM> may terminate at the buffer chip <NUM> and not be communicated to the first to fourth nonvolatile memory chips <NUM> to <NUM>.

The mold <NUM> may be provided to cover the first to fourth nonvolatile memory chips <NUM> to <NUM> and the buffer chip <NUM> on the package substrate <NUM>. In this regard, the mold <NUM> may encapsulate (wholly or in part) the first to fourth nonvolatile memory chips <NUM> to <NUM> and the buffer chip <NUM>, thereby protecting these components from contamination and environmental factors, such as moisture, humidity, temperature and static electricity. One or more external devices(s) (hereafter, singularly or collectively the "external device") may be variously connected to the buffer chip <NUM> and the first to fourth nonvolatile memory chips <NUM> to <NUM> via the solder balls <NUM>. That is, the solder balls <NUM> may be used to selectively communicate various signals between the external device and the buffer chip <NUM>.

Each of the first to fourth nonvolatile memory chips <NUM> to <NUM> may include at least one nonvolatile memory device, such as a flash memory, a phase change memory, a ferroelectric memory, a magnetic memory, a resistive memory, etc. In some embodiments, the first to fourth nonvolatile memory chips <NUM> to <NUM> may each include one or more flash memory device(s), however the scope of the inventive concept is not limited thereto.

The first memory pads <NUM> of the first nonvolatile memory chip <NUM> may be variously and electrically connected with internal components of the first nonvolatile memory chip <NUM>. That is, the first nonvolatile memory chip <NUM> may communicate with an external device (via the buffer chip <NUM>) through the first memory pads <NUM>. The respective configuration and operation of the second, third and fourth nonvolatile memory chips <NUM>, <NUM> and <NUM>, as well as the second, third and fourth memory pads <NUM>, <NUM> and <NUM> may be same as those described in relation to the first nonvolatile memory chip <NUM> and the first memory pads <NUM>.

The buffer chip <NUM> may communicate various signals between the first to fourth nonvolatile memory chips <NUM> to <NUM> (singularly or collectively) and the external device. That is, in some embodiments, the buffer chip <NUM> may communicate original (or raw) signals received from the external device to one or more of the first to fourth nonvolatile memory chips <NUM> to <NUM> without significant signal conversion. Alternately or additionally, the buffer chip <NUM> may perform various signal processing to improve the original signals receiver from the external device. Such "improvement" may include (e.g.,) improved compatibility, improved signal integrity (e.g., signal reshaping, noise reduction, or jitter reduction), improved timing (e.g., skew reduction) and/or improved power integrity (e.g., voltage/current level correction) for the signals communicated from the external device to the first to fourth nonvolatile memory chips <NUM> to <NUM> via the buffer chip <NUM>. In this regard, the foregoing signal processing may variously improve the original signals without altering the content (or information - e.g., digital values or orders of digital values) of the original signals.

Alternately or additionally, the signal processing provided by the buffer chip <NUM> may include a signal swap that swaps first signals of (i.e., apparent at) the first buffer pads <NUM> and second signals of the second buffer pads <NUM>. This type of "signal swap" may include a "direct communicate" of the first signals of the first buffer pads <NUM> to the second buffer pads <NUM> and/or a "selective communicate" in which one or more of the first signals of the first buffer pads <NUM> is selectively swapped - in terms of location(s) among the first buffer pads <NUM> - and then communicated to the second buffer pads <NUM>. In this regard, signal swapping may be used to improve signal integrity and/or power integrity by supporting signal mirroring at a package level of the memory package <NUM> (e.g., among components of the memory package <NUM> including the first to fourth nonvolatile memory chips <NUM> to <NUM>).

<FIG> is a plan diagram illustrating in one example a ball map for the solder balls <NUM> of the memory package <NUM> of <FIG> and <FIG>. Referring to <FIG>, <FIG> and <FIG>, the solder balls <NUM> may be disposed under (e.g., on a lower surface of) the package substrate <NUM>. The illustrated example of <FIG> assumes the inclusion of six (<NUM>) high-speed solder balls (e.g., first (HS1), second (HS2), third (HS3), fourth (HS4), fifth (HS5) and sixth (HS6) - hereafter collectively, "solder balls HS1 to HS6"), as well as fourteen (<NUM>) low-speed signal solder balls (e.g., analogously annotated "low-speed solder balls LS1 to LS14"). In this context, those skilled in the art will recognize that the term "solder ball" encompasses abroad range of electrically conductive elements capable of communicating one or more electrical signal(s).

In this regard, one or more of the first to sixth high-speed signal solder balls HS1 to HS6 may be used to communicate various "high-speed timing signal(s)" (e.g., clock(s) and/or data strobe(s)) that control the operational and/or inter-operational timing of circuitry associated with the first to fourth nonvolatile memory chips <NUM> to <NUM>. Alternately or additionally, one or more of the first to sixth high-speed signal solder balls HS1 to HS6 may be used to communicate "high-speed signal(s)" that are related to (e.g., synchronous with) the high-speed timing signal(s). For example, certain high-speed signal(s) may be used to communicate information (e.g., data) synchronously with one or more of the high-speed timing signal(s) (e.g., high-speed timing signals defining a particular high-speed data rate (e.g., a Double Data Rate or DDR).

In contrast, one or more of the first to fourteenth low-speed signal solder balls LS1 to LS <NUM> may be used to communicate certain "low-speed signal(s)", such as those commonly associated with operating modes (e.g., write protect, data masking, data inversion, etc.) as well as various "states" (e.g., enabled or disabled) for the operating modes. For example, low-speed signal(s) of the type communicated by one or more of the first to fourteenth low-speed signal solder balls LS1 to LS14 may indicate an enabled state or a disabled state when a corresponding event (e.g., receipt of a command, an address, and/or data) occurs. However, one of more of the first to fourteenth low-speed signal solder balls LS1 to LS14 may be used to communicate one or more low-speed signal(s) synchronously with a low-speed timing signal (e.g., a Single Data Rate or SDR).

In some embodiments, the first to sixth high-speed signal solder balls HS1 to HS6 may be used to communicate data signals DQ, a data strobe signal DQS, and/or a read enable signal RE. And the first to fourteenth low-speed signal solder balls LS1 to LS14 may be used to communicate one or more power signal(s) (e.g., a power supply voltage and/or ground voltage), a write protect signal WP, a command latch enable signal CLE, an address latch enable signal ALE, a chip enable signal CE, a ready and busy signal RnB, and/or a write enable signal WE.

With reference to the particular example illustrated in <FIG> and including first to sixth high-speed signal solder balls HS1 to HS6 and first to fourteenth low-speed signal solder balls LS <NUM> to LS <NUM>, those skilled in the art will recognize that the number and corresponding locations of high-speed solder balls and/or low-speed signal solder balls will may vary with design. Further, the number and type of high-sped timing signals, high-speed signals, low-speed timing signals and low-speed signals may vary with design.

<FIG> is a cross-sectional diagram illustrating a storage device <NUM> according to embodiments of the inventive concept. Referring to <FIG>, the storage device <NUM> may include a first memory package <NUM>, a second memory package <NUM>, a controller package <NUM>, a printed circuit board (PCB) <NUM> and a connector <NUM>.

Each of the first memory package <NUM> and the second memory package <NUM> may be similarly configured to the memory package <NUM> of <FIG>, <FIG> and <FIG>. In the illustrated example of <FIG>, the first memory package <NUM> is disposed on an upper surface of the PCB <NUM> and the second memory package <NUM> is disposed on a lower surface of the PCB <NUM> in an "opposing" manner (e.g., lower surface facing lower surface across the PCB <NUM>) with respect to the first memory package <NUM>. In this configuration, the first memory package <NUM> and the second memory package <NUM> may be readily connected to the PCB <NUM> using solder balls.

The controller package <NUM> may be provided on the upper and/or lower surface of the PCB <NUM>, wherein the controller package <NUM> may be selectively connected through the PCB <NUM> to the solder balls and used to control the overall operation of the first memory package <NUM> and the second memory package <NUM> in response to requests (or commands) received from the external device. In this regard, the controller package <NUM> may "communicate" (e.g., communicate and/or receive) signals including command(s), address(es), data and/or control signals between the first memory package <NUM> and/or the second memory package <NUM> and the external device in relation to various memory access operations, such as write operations, read operations, erase operations, housekeeping operations, etc..

That is, the controller package <NUM> may variously communicate with the external device through the connector <NUM>, such that the controller package <NUM> may receive a request (e.g., a read or a write request) from the external device through the connector <NUM>, and then access the first memory package <NUM> and/or the second memory package <NUM> in response to the request.

The PCB <NUM> may include various wires, wiring, through vias, etc. (hereafter, singularly or collectively "wires") connecting the first memory package <NUM> and the second memory package <NUM> with the controller package <NUM>, and further connecting the controller package <NUM> with the connector <NUM>. For example, so-called "high-speed signal wires" (HSSL shown by the dotted lines in <FIG>) may be used to communicate high-speed signal(s) between the controller package <NUM> and the first memory package <NUM> and the second memory package <NUM>. Relative to the illustrated example of <FIG>, the HSSL may be connected with the first to sixth high-speed signal solder balls HS1 to HS6 of the first memory package <NUM> and/or the first to sixth high-speed signal solder balls HS1 to HS6 of the second memory package <NUM>. Additionally, so-called low-speed signal wires (or LSSL shown by the solid lines in <FIG>) may communicate low-speed signal(s) between the controller package <NUM> and the first memory package <NUM> and the second memory package <NUM>. For example, the low-speed signal wires LSSL may be connected with the first to fourteenth low-speed signal solder balls LS <NUM> to LS14 of the first memory package <NUM> or the second memory package <NUM>.

As technologies enabling the manufacture of evermore powerful storage devices have developed, the frequency of various timing signals in storage devices have increased. And as the frequency of storage device timing signals have increased, the influence on performance of PCB signal transmission path(s) (e.g., delay, noise, etc.) on signal integrity and power integrity of various signals has also increased.

For example, referring to <FIG>, the first memory package <NUM> and the second memory package <NUM> may be respectively disposed on upper and lower surfaces of the PCB <NUM>. Here, a first length of a first wire extending from the controller package <NUM> to the first memory package <NUM> may be different than a second length of a second wire extending from the controller package <NUM> to the second memory package <NUM>. Such different lengths may result in different arrival times for signals respectively communicated via the first wire and the second wire. This is particularly true for high-speed signals. Further, different signal times of flight may result in signal interference and possible loss of signal information.

To prevent such outcomes, and as illustrated in <FIG>, the storage device <NUM> may be configured using a technique called "package mirroring" in which the first memory package <NUM> and the second memory package <NUM> are substantially vertically aligned one above the other, and respectively disposed on the upper and lower surfaces of the PCB <NUM>. As a result, at least some of first wires (or first signal paths) extending between the controller package <NUM> and the first memory package <NUM> and at least some of second wires (or second signal paths) extending between the controller package <NUM> and the second memory package <NUM> may be configured in mirroring arrangements. In some embodiments, the mirrored wires (or mirrored signal paths) among the first signal paths and the second signal paths may be used to communicate high-speed signals. That is, the mirrored signal paths among the first signal paths and the second signal paths may be used as HSSL to communicate high-speed signals from the package controller <NUM> to the first memory package <NUM> and the second memory package <NUM>. By using package mirroring, differences between analogous wire lengths (or signals paths) communicating at least certain high-speed signals may be minimized, thereby improving signal integrity and power integrity for signals associated with the storage device <NUM>.

In contrast and as further illustrated in <FIG>, wires (or signal paths) communicating low-speed signals (e.g., LSSL) need not necessarily be arranged in a mirroring arrangement, since differences in wire (or signal path) lengths do not adversely influence the transmission of the low-speed signals between the package controller <NUM> and the first memory package <NUM> and between the package controller <NUM> and the second memory package <NUM>.

<FIG> is a plan diagram illustrating in one example a package mirroring arrangement between the first memory package <NUM> and the second memory package <NUM> of <FIG>. Referring to <FIG> and <FIG>, because the first memory package <NUM> and the second memory package <NUM> are disposed in substantial alignment on upper and lower surfaces of the PCB <NUM>, a first arrangement of solder balls associated with the first memory package <NUM> will be mirrored (i.e., reversed as if seen in a facing mirror) by a second arrangement of solder balls associated with the second memory package <NUM>. (Thus, the laterally adjacent disposition of the first arrangement of solders balls associated with the first memory package <NUM> and the second arrangement of solder balls associated with the second memory package <NUM> should be viewed vertically adjacent above and below the PCB <NUM>).

It follows that high-speed signal wires (HSSL) will be connected to the first memory package <NUM> and to second memory package <NUM> at analogous (i.e., geometrically similar) locations with respect to the PCB <NUM>. That is, the first to sixth high-speed signal solder balls HS <NUM> to HS6 of the first memory package <NUM> and the first to sixth high-speed signal solder balls HS1 to HS6 of the second memory package <NUM> will be respectively and vertically aligned above and below the PCB <NUM>. For example, as illustrated in <FIG>, the first to third high-speed signal solder balls HS1 to HS3 of the first memory package <NUM> may be respectively connected with the fourth to sixth high-speed signal solder balls HS4 to HS6 of the second memory package <NUM>, And the fourth to sixth high-speed signal solder balls HS4 to HS6 of the first memory package <NUM> may be respectively connected with the first to third high-speed signal solder balls HS1 to HS3 of the second memory package <NUM>.

<FIG> is a conceptual diagram further illustrating in one example high-speed signal paths (or signal connections arranged according to package mirroring) between the controller package <NUM> and the first memory package <NUM> and between the controller package <NUM> and the second memory package <NUM> in the storage device <NUM> of <FIG> and <FIG>. Referring to <FIG>, <FIG>, and <FIG>, the controller package <NUM> is assumed to output bit values of "<NUM>" respectively through the first to sixth high-speed signal solder balls HS1 to HS6.

In the illustrated embodiment of <FIG>, the first to sixth high-speed signal solder balls HS1 to HS6 of the first memory package <NUM> may be respectively connected with the first to sixth high-speed signal solder balls HS <NUM> to HS6 of the controller package <NUM>. Accordingly, the first arrangement of solder balls (e.g., the first to sixth high-speed signal solder balls HS1 to HS6) associated with the first memory package <NUM> (which is disposed on the upper surface of the PCB together with the package controller <NUM>) will readily and respectively receive the communicated bits as "<NUM>".

However, as described in relation to <FIG>, the second memory package <NUM> is disposed in a mirroring arrangement on the lower surface of the PCB <NUM>. Hence, the first to third high-speed signal solder balls HS1 to HS3 of the second memory package <NUM> will be respectively connected with the fourth to sixth high-speed signal solder balls HS4 to HS6 of the first memory package <NUM>, and the fourth to sixth high-speed signal solder balls HS4 to HS6 of the second memory package <NUM> may be respectively connected with the first to third high-speed signal solder balls HS1 to HS3 of the first memory package <NUM>. Accordingly, the second arrangement of solder balls (e.g., the first to sixth high-speed signal solder balls HS1 to HS6) associated with the second memory package <NUM> will incorrectly receive the communicated bits as "<NUM>".

To remedy this outcome, a swapping operation may be performed in relation to the second memory package <NUM> that selectively swaps signals received at the first to third high-speed signal solder balls HS1 to HS3 with signals received at the fourth to sixth high-speed signal solder balls HS4 to HS6. Hence, the swapping operation has the effect of normalizing the receipt of signals at the second arrangement of solder balls associated with the second memory package <NUM> with the receipt of the signals at the first arrangement of solder balls associated with the first memory package <NUM>.

In this regard, the swapping operation may be performed, as needed, by respective memory package(s) provided by the first to fourth nonvolatile memory chips <NUM> to <NUM> of <FIG> and <FIG>. However, performance of the swapping operation may require certain structural change(s) in the first to fourth nonvolatile memory chips <NUM> to <NUM> that increase the overall cost of the storage device <NUM>.

To avoid increased costs, embodiments of the inventive concept provide the buffer chip <NUM> of <FIG> and <FIG> that may be configured to perform a swapping operation that selectively swaps signals in the buffer chip <NUM> to-be-communicated to the first to third high-speed signal solder balls HS1 to HS3 and/or to the fourth to sixth high-speed signal solder balls HS4 to HS6. Thus, the buffer chip <NUM> may be configured to arrange the communication of various signals the first to fourth nonvolatile memory chips <NUM> to <NUM> in such a manner that signal integrity and power integrity are protected. In this regard, the structure of the buffer chip <NUM> may be relatively simple, as compared with the structure of the first to fourth nonvolatile memory chips <NUM> to <NUM>. Accordingly, the structure and functionality of the buffer chip <NUM> may be configured to avoid costly changes to the structure and/or functionality of the first to fourth nonvolatile memory chips <NUM> to <NUM>.

<FIG> is a flow chart illustrating in one example an operating method for the buffer chip <NUM> of <FIG> and <FIG> according to embodiments of the inventive concept. Referring to <FIG>, <FIG>, and <FIG>, the buffer chip <NUM> may receive high-speed signals through the first to sixth high-speed signal solder balls HS1 to HS6 (S110). Optionally, the buffer chip <NUM> may perform certain signal processing such as reshaping of high-speed signals (S115). Here, "reshaping" may refer to changing toggle timing of timing signal(s), changing toggle timing of information signal(s), adjusting for jitter, adjusting for skew, etc..

Once the high-speed signals are received (and optionally reshaped), the buffer chip <NUM> may determine whether a swap is enabled (S120). When it is determined that the swap is not enabled (S120=NO), the buffer chip <NUM> may output the high-speed signal received via the first to sixth high-speed signal solder balls HS1 to HS6 to the first to fourth nonvolatile memory chips <NUM> to <NUM> without performing a swap operation (S130).

However, when it is determined that the swap is enabled (S120=YES), the buffer chip <NUM> may perform a swap operation on (or hereafter, "swap") the high-speed signals to generate swapped high-speed signals. For example, the buffer chip <NUM> may swap signals received via the first to third high-speed signal solder balls HS1 to HS3 with signals received via the fourth to sixth high-speed signal solder balls HS4 to HS6 (S140). Then, the buffer chip <NUM> may output the swapped high-speed signals to the first to fourth nonvolatile memory chips <NUM> to <NUM> (S150).

<FIG> is a block diagram illustrating a buffer chip <NUM> according to embodiments of the inventive concept. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, the buffer chip <NUM> may correspond to the buffer chip <NUM> of <FIG> and <FIG>. The buffer chip <NUM> may include a swap multiplexer <NUM>, a delay code generator <NUM>, read elements <NUM>, and write elements <NUM>.

The swap multiplexer <NUM> may receive a swap enable signal SE from an external source outside of the buffer chip <NUM>. The swap multiplexer <NUM> may receive data signals DQ from the read elements <NUM>. When the swap enable signal SE is disabled, the swap multiplexer <NUM> may return the data signals DQ to the read elements <NUM> without the swap. When the swap enable signal SE is enabled, the swap multiplexer <NUM> may swap the data signals DQ and may return the swapped data signals DQ to the read elements <NUM>.

The swap multiplexer <NUM> may receive the data signals DQ from the write elements <NUM>. When the swap enable signal SE is disabled, the swap multiplexer <NUM> may return the data signals DQ to the write elements <NUM> without the swap. When the swap enable signal SE is enabled, the swap multiplexer <NUM> may swap the data signals DQ and may return the swapped data signals DQ to the write elements <NUM>.

The delay code generator <NUM> may generate a delay code for synchronization between the data signals DQ and the data strobe signals DQS. The delay code generator <NUM> may communicate the delay code to the read elements <NUM> and the write elements <NUM>.

The read elements <NUM> may receive the read enable signal RE from the controller package <NUM> and may output the received read enable signal RE to the first to fourth nonvolatile memory chips <NUM> to <NUM>. The read enable signal RE may be included in the timing signal(s) described above.

The read elements <NUM> may receive the data signals DQ and the data strobe signals DQS from the first to fourth nonvolatile memory chips <NUM> to <NUM>. The data signals DQ may be included in the signal(s) or the information signal(s) communicating information, which are described above. The data strobe signals DQS may be included in the timing signal(s) described above. The read elements <NUM> may output the data signals DQ and the data strobe signals DQS to the controller package <NUM>.

The read elements <NUM> may include a read sampler <NUM>, a delay line <NUM>, and a read serializer <NUM>. The read sampler <NUM> may sample the data signals DQ in synchronization with the data strobe signals DQS output from the delay line <NUM>. The sampled data signals may be communicated to the swap multiplexer <NUM>.

The delay line <NUM> may delay the data strobe signals DQS communicated from the first to fourth nonvolatile memory chips <NUM> to <NUM> in response to the delay code communicated from the delay code generator <NUM>. In some embodiments, the centers of the data signals DQ output from the first to fourth nonvolatile memory chips <NUM> to <NUM> may be respectively synchronized with the centers of the data strobe signals DQS. The delay line <NUM> may delay and output the data strobe signals DQS communicated from the first to fourth nonvolatile memory chips <NUM> to <NUM> such that the centers of the data signals DQ are synchronized with the edges of the data strobe signals DQS.

The read serializer <NUM> may receive data signals, which are swapped or are not swapped, from the swap multiplexer <NUM>. The read serializer <NUM> may serialize the data signals communicated from the swap multiplexer <NUM> in synchronization with the data strobe signals DQS communicated from the delay line <NUM>, so as to be output as the data signals DQ. In some embodiments, the centers of the data signals DQ output from the read serializer <NUM> may be respectively synchronized with the centers of the data strobe signals DQS output from the delay line <NUM>.

In some embodiments, each of the first to fourth nonvolatile memory chips <NUM> to <NUM> may delay the read enable signal RE to generate the data strobe signals DQS. A waveform of the data strobe signals DQS may be the same as a waveform of the read enable signal RE and may be delayed with respect to the waveform of the read enable signal RE. The read enable signal RE may toggle when the read elements <NUM> are activated depending on a read command and may have a fixed level when the read elements <NUM> are not activated.

The write elements <NUM> may receive the data signals DQ and the data strobe signals DQS from the controller package <NUM>. The write elements <NUM> may communicate the data signals DQ and the data strobe signals DQS to the first to fourth nonvolatile memory chips <NUM> to <NUM>.

The write elements <NUM> may include a write sampler <NUM>, a delay line <NUM>, and a write serializer <NUM>. The write sampler <NUM> may sample the data signals DQ in synchronization with the data strobe signals DQS output from the controller package <NUM>. The sampled data signals may be communicated to the swap multiplexer <NUM>.

The delay line <NUM> may delay the data strobe signals DQS communicated from the controller package 230in response to the delay code communicated from the delay code generator <NUM>. The delay line <NUM> may output delayed versions of the data strove signals to the first to fourth nonvolatile memory chips <NUM> to <NUM>. In some embodiments, centers of the data signals DQ output from the controller package <NUM> may be synchronized with edges of the data strobe signals DQS. The delay line <NUM> may delay and output the data strobe signals DQS output from the controller package <NUM> such that the centers of the data signals DQ output from the write serializer <NUM> are synchronized with edges of the data strobe signals DQS output from the delay line <NUM>.

The write serializer <NUM> may receive data signals, which are swapped or are not swapped, from the swap multiplexer <NUM>. The write serializer <NUM> may serialize the data signals communicated from the swap multiplexer <NUM> in synchronization with the data strobe signals DQS communicated from the controller package <NUM>, so as to be output as the data signals DQ.

In some embodiments, the data signals DQ output from the read elements <NUM> and the data signals DQ received by the write elements <NUM> may be exchanged via analogous (or common) solder balls (e.g., high-speed signal solder balls) between the controller package <NUM> and the buffer chip <NUM>. The data strobe signals DQS output from the read elements <NUM> and the data strobe signals DQS received by the write elements <NUM> may be exchanged through common solder balls (e.g., high-speed signal solder balls) between the controller package <NUM> and the buffer chip <NUM>.

The data signals DQ received by the read elements <NUM> and the data signals DQ output from the write elements <NUM> may be exchanged via analogous (or common) pads between the buffer chip <NUM> and the first to fourth nonvolatile memory chips <NUM> to <NUM>. The data strobe signals DQS received by the read elements <NUM> and the data strobe signals DQS output from the write elements <NUM> may be exchanged via analogous (or common) pads between the buffer chip <NUM> and the first to fourth nonvolatile memory chips <NUM> to <NUM>.

The data strobe signals DQS may toggle when the read elements <NUM> or the write elements <NUM> are activated in response to a read command or a write command and may have a fixed level when the read elements <NUM> or the write elements <NUM> are deactivated. The data strobe signals DQS may be distinguished from an always toggling clock signal in that the data strobe signals DQS toggles only as required.

In some embodiments, a period of the data signals DQ when passing through the read sampler <NUM> may increase (e.g., by two times), and a period of the data signals DQ when passing through the read serializer <NUM> may decrease (e.g., by one half). Likewise, a period of the data signals DQ when passing through the write sampler <NUM> may increase (e.g., by two times), and a period of the data signals DQ when passing through the write serializer <NUM> may decrease (e.g., by one half). The swap multiplexer <NUM> may perform the swap more stably and more accurately by performing the swap between the read sampler <NUM> and the read serializer <NUM> and between the write sampler <NUM> and the write serializer <NUM>.

<FIG> is a plan diagram illustrating in one example a method by which the swap enable signal SE may be communicated to the buffer chip <NUM>. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, at least one low-speed signal solder ball (e.g., LS7) of the first memory package <NUM> may be biased to a voltage having a first level (e.g., a ground or VSS), and at least one low-speed signal solder ball (e.g., LS7) of the second memory package <NUM> may be biased to a voltage having a second level (e.g., a power supply voltage VDD).

When the low-speed signal solder ball (e.g., LS7) is set to VSS, the swap enable signal SE may be identified as disabled. When the low-speed signal solder ball (e.g., LS7) is set to VDD, the swap enable signal SE may be identified as enabled. That is, the buffer chip <NUM> of the first memory package <NUM> will not perform the swap, whereas the buffer chip <NUM> of the second memory package <NUM> will perform the swap.

In some embodiments, VSS and VDD may be readily provided from the controller package <NUM> to the first memory package <NUM> and the second memory package <NUM>. For another example, VSS and VDD may bypass the controller package <NUM>, and be directly communicated from the connector <NUM> to the first memory package <NUM> and the second memory package <NUM>.

In some embodiments, the enable/disable state of the swap enable signal SE may be identified by a waveform of a signal communicated to at least one solder ball of the first memory package <NUM> or at least one solder ball of the second memory package <NUM>, and not simply as the level of a particular voltage communicated to the at least one solder ball. The waveform of the signal may include at least one transition point at which a transition is made from a high level and a low level. In response to a first waveform being communicated, the first memory package <NUM> or the second memory package <NUM> may identify an enabled swap enable signal SE, and in response to a second waveform, different from the first waveform, being communicated, the first memory package <NUM> or the second memory package <NUM> may identify a disabled swap enable signal SE.

In some embodiments, the first buffer pads <NUM> of the buffer chip <NUM> may include at least one pad receiving a signal from at least one solder ball. A signal apparent at the at least one solder ball need not be communicated to the first to fourth nonvolatile memory chips <NUM> to <NUM>. Accordingly, the second buffer pads <NUM> of the buffer chip <NUM> may not include at least one pad used to communicate the signal from the at least one solder ball.

<FIG> is a block diagram illustrating a buffer chip <NUM> according to embodiments of the inventive concept. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, the buffer chip <NUM> may correspond to the buffer chip <NUM> of <FIG> and <FIG>. The buffer chip <NUM> may include a delay code generator <NUM>, read elements <NUM>, and write elements <NUM>.

Compared to the buffer chip <NUM> of <FIG>, the swap multiplexer <NUM> may be divided into a first swap multiplexer <NUM> and a second swap multiplexer <NUM> so as to be disposed at the read elements <NUM> and the write elements <NUM>, respectively. The first swap multiplexer <NUM> may receive data signals sampled by a read sampler <NUM> and may perform or omit the swap in response to the swap enable signal SE. The first swap multiplexer <NUM> may communicate the data signals, which are swapped or are not swapped, to a read serializer <NUM>.

The second swap multiplexer <NUM> may receive data signals sampled by a write sampler <NUM> and may perform or omit the swap in response to the swap enable signal SE. The second swap multiplexer <NUM> may communicate the data signals, which are swapped or are not swapped, to a write serializer <NUM>.

The respective structures and functions of the delay code generator <NUM>, the read sampler <NUM>, a delay line <NUM>, the read serializer <NUM>, the write sampler <NUM>, a delay line <NUM>, and the write serializer <NUM> may be the same as those of the delay code generator <NUM>, the read sampler <NUM>, the delay line <NUM>, the read serializer <NUM>, the write sampler <NUM>, the delay line <NUM>, and the write serializer <NUM> described in relation to <FIG>.

<FIG> is a block diagram illustrating a buffer chip <NUM> according to embodiments of the inventive concept. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, the buffer chip <NUM> may correspond to the buffer chip <NUM> of <FIG> and <FIG>. The buffer chip <NUM> may include a swap multiplexer <NUM>, a delay code generator <NUM>, read elements <NUM>, write elements <NUM>, and a timing signal swap multiplexer <NUM>.

Compared with the buffer chip <NUM> of <FIG>, the buffer chip <NUM> may further include the timing signal swap multiplexer <NUM>. The timing signal swap multiplexer <NUM> may receive the read enable signal RE and the data strobe signals DQS from the controller package <NUM>. The timing signal swap multiplexer <NUM> may output the read enable signal RE to the read elements <NUM> and may output the data strobe signals DQS to the write elements <NUM>.

The timing signal swap multiplexer <NUM> may receive the data strobe signals DQS from the read elements <NUM>. The timing signal swap multiplexer <NUM> may output the data strobe signals DQS to the controller package <NUM>. The timing signal swap multiplexer <NUM> may selectively perform the swap of timing signals between the controller package <NUM> and the read elements <NUM> and between the controller package <NUM> and the write elements <NUM>.

The data strobe signal DQS that is received from the controller package <NUM> and is swapped or is not swapped by the timing signal swap multiplexer <NUM> may be communicated to a write sampler <NUM>. The read enable signal RE that is received from the controller package <NUM> and is swapped or is not swapped by the timing signal swap multiplexer <NUM> may be communicated to the first to fourth nonvolatile memory chips <NUM> to <NUM> through the read elements <NUM>. The data strobe signals DQS that are received from the read elements <NUM> and are swapped or are not swapped by the timing signal swap multiplexer <NUM> may be communicated to the controller package <NUM>.

The respective structures and functions of the swap multiplexer <NUM>, the delay code generator <NUM>, the read elements <NUM> including a read sampler <NUM>, a delay line <NUM>, and a read serializer <NUM>, and the write elements <NUM> including the write sampler <NUM>, a delay line <NUM>, and a write serializer <NUM> may be the same as those of the swap multiplexer <NUM>, the delay code generator <NUM>, the read elements <NUM> including the read sampler <NUM>, the delay line <NUM>, and the read serializer <NUM>, and the write elements <NUM> including the write sampler <NUM>, the delay line <NUM>, and the write serializer <NUM> described in relation to <FIG>.

In some embodiments, as described with reference to <FIG>, the swap multiplexer <NUM> may be divided into two swap multiplexers so as to be disposed at the read elements <NUM> and the write elements <NUM>, respectively. Also, the timing signal swap multiplexer <NUM> may be divided into two swap multiplexers so as to be disposed at the read elements <NUM> and the write elements <NUM>, respectively.

<FIG> is a block diagram illustrating a buffer chip <NUM> according to embodiments of the inventive concept. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, the buffer chip <NUM> may correspond to the buffer chip <NUM> of <FIG> and <FIG>. The buffer chip <NUM> may include a delay code generator <NUM>, read elements <NUM>, write elements <NUM>, and an integrated swap multiplexer <NUM>.

The integrated swap multiplexer <NUM> may perform or omit the swap of the data signals DQ, the data strobe signals DQS, and the read enable signal RE in response to the swap enable signal SE. The integrated swap multiplexer <NUM> may selectively perform the swap of timing signals between the controller package <NUM> and the read elements <NUM> and between the controller package <NUM> and the write elements <NUM>.

The swap of timing signals including the data strobe signals DQS and the read enable signal RE may be performed the same as that described with reference to the timing signal swap multiplexer <NUM> of <FIG>. The swap of the data signals DQ may be performed between the read elements <NUM> and the controller package <NUM> or between the write elements <NUM> and the controller package <NUM> to be the same as that described with reference to <FIG>.

The respective structures and functions of the delay code generator <NUM>, the read elements <NUM> including a read sampler <NUM>, a delay line <NUM>, and a read serializer <NUM>, and the write elements <NUM> including a write sampler <NUM>, a delay line <NUM>, and a write serializer <NUM> may be the same as those of the delay code generator <NUM>, the read elements <NUM> including the read sampler <NUM>, the delay line <NUM>, and the read serializer <NUM>, and the write elements <NUM> including the write sampler <NUM>, the delay line <NUM>, and the write serializer <NUM> described in relation to <FIG>.

In some embodiments, as described with reference to <FIG>, the integrated swap multiplexer <NUM> may be divided into two swap multiplexers so as to be disposed at the read elements <NUM> and the write elements <NUM>, respectively.

Compared with the buffer chip <NUM> of <FIG>, the buffer chip <NUM> may further include the timing signal swap multiplexer <NUM>. The timing signal swap multiplexer <NUM> may receive the read enable signal RE from the read elements <NUM>. The timing signal swap multiplexer <NUM> may output the read enable signal RE to the first to fourth nonvolatile memory chips <NUM> to <NUM>. The timing signal swap multiplexer <NUM> may receive the data strobe signal DQS from the write element <NUM>. The timing signal swap multiplexer <NUM> may output the data strobe signal DQS to the first to fourth nonvolatile memory chips <NUM> to <NUM>.

The timing signal swap multiplexer <NUM> may receive the data strobe signals DQS from the first to fourth nonvolatile memory chips <NUM> to <NUM>. The timing signal swap multiplexer <NUM> may output the data strobe signals DQS to the read elements <NUM>. The timing signal swap multiplexer <NUM> may selectively perform the swap of timing signals between the first to fourth nonvolatile memory chips <NUM> to <NUM> and the read elements <NUM> and between the first to fourth nonvolatile memory chips <NUM> to <NUM> and the write elements <NUM>.

The read enable signal RE that is received from the read elements <NUM> and is swapped or is not swapped by the timing signal swap multiplexer <NUM> may be communicated to the first to fourth nonvolatile memory chips <NUM> to <NUM>. The data strobe signal DQS that is received from the write elements <NUM> and is swapped or is not swapped by the timing signal swap multiplexer <NUM> may be communicated to the first to fourth nonvolatile memory chips <NUM> to <NUM>. The data strobe signal DQS that is received from the first to fourth nonvolatile memory chips <NUM> to <NUM> and is swapped or is not swapped by the timing signal swap multiplexer <NUM> may be communicated to the read elements <NUM>.

The respective structures and functions of the swap multiplexer <NUM>, the delay code generator <NUM>, the read elements <NUM> including a read sampler <NUM>, a delay line <NUM>, and a read serializer <NUM>, and the write elements <NUM> including a write sampler <NUM>, a delay line <NUM>, and a write serializer <NUM> may be the same as those of the swap multiplexer <NUM>, the delay code generator <NUM>, the read elements <NUM> including the read sampler <NUM>, the delay line <NUM>, and the read serializer <NUM>, and the write elements <NUM> including the write sampler <NUM>, the delay line <NUM>, and the write serializer <NUM> described in relation to <FIG>.

The integrated swap multiplexer <NUM> may perform or omit the swap of the data signals DQ, the data strobe signals DQS, and the read enable signal RE in response to the swap enable signal SE. The integrated swap multiplexer <NUM> may selectively perform the swap of timing signals between the first to fourth nonvolatile memory chips <NUM> to <NUM> and the read elements <NUM> and between the first to fourth nonvolatile memory chips <NUM> to <NUM> and the write elements <NUM>.

<FIG> is a block diagram illustrating a buffer chip <NUM> according to embodiments of the inventive concept. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, the buffer chip <NUM> may correspond to the buffer chip <NUM> of <FIG> and <FIG>. The buffer chip <NUM> may include a swap multiplexer <NUM>, a delay code generator <NUM>, read elements <NUM>, write elements <NUM>, and a command parser <NUM>.

The command parser <NUM> may receive data signals sampled by a write sampler <NUM> of the write elements <NUM>. The command parser <NUM> may parse the received data signals and may enable or disable the swap enable signal SE depending on the parsed result.

For example, when a power is supplied to the storage device <NUM>, the controller package <NUM> may be configured to communicate a specified command to the first memory package <NUM> and the second memory package <NUM>. For example, the specified command may include an initialization command, a status read command, a get features command, or the like, and may be defined by the standard or vendor specific.

The command parser <NUM> may store a pattern (e.g., a pattern of bits) of the specified command. The command parser <NUM> may compare data signals, which are first sampled by the write sampler <NUM> after the power-on, with the pattern of the specified command. When a pattern of the sampled data signals coincides with the pattern of the specified command, the command parser <NUM> may disable the swap enable signal SE. When the pattern of the sampled data signals does not coincide with the pattern of the specified command, the command parser <NUM> may enable the swap enable signal SE.

Also, when the swap enable signal SE is enabled, the command parser <NUM> may control the swap multiplexer <NUM> such that the data signals compared by the command parser <NUM> are swapped and output by the swap multiplexer <NUM>.

In some embodiments, as described with reference to <FIG>, the swap multiplexer <NUM> may be divided into two swap multiplexers so as to be disposed at the read elements <NUM> and the write elements <NUM>, respectively. Also, as described with reference to <FIG> and <FIG>, the buffer chip <NUM> may further include a timing signal swap multiplexer for swapping timing signals. Also, as described with reference to <FIG> and <FIG>, an integrated swap multiplexer for swapping timing signals and the data signals DQ may be provided instead of the swap multiplexer <NUM>.

<FIG> is a block diagram illustrating a multiplexer <NUM> according to embodiments of the inventive concept. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, the multiplexer <NUM> may be implemented with the swap multiplexer <NUM> of <FIG>, the swap multiplexer <NUM> or the timing signal swap multiplexer <NUM> of <FIG>, the integrated swap multiplexer <NUM> of <FIG>, the swap multiplexer <NUM> or the timing signal swap multiplexer <NUM> of <FIG>, the integrated swap multiplexer <NUM> of <FIG>, or the swap multiplexer <NUM> of <FIG>.

The multiplexer <NUM> may include first elements <NUM> and second elements <NUM>. The first elements <NUM> may be implemented with the first swap multiplexer <NUM> of <FIG>, and the second elements <NUM> may be implemented with the second swap multiplexer <NUM> of <FIG>. The first elements <NUM> may be applied to timing signals or the data signals DQ that are communicated from the first to fourth nonvolatile memory chips <NUM> to <NUM> to the controller package <NUM>. The second elements <NUM> may be applied to timing signals or the data signals DQ that are communicated from the controller package <NUM> to the first to fourth nonvolatile memory chips <NUM> to <NUM>.

The first elements <NUM> may include first buffer chip elements <NUM>, second buffer chip elements <NUM>, and first multiplexers <NUM> to 112n (n being a positive integer more than <NUM>). Each of the first multiplexers <NUM> to 112n may select one of signals communicated from the first buffer chip elements <NUM> so as to be communicated to the second buffer chip elements <NUM>.

In some embodiments, one signal output from the first buffer chip elements <NUM> may be communicated to two first multiplexers. For example, an output signal (e.g., a first signal) associated with the first high-speed signal solder ball HS1 of the first buffer chip elements <NUM> may be output to a first multiplexer associated with the first high-speed signal solder ball HS <NUM> of the second buffer chip elements <NUM> and a first multiplexer associated with the fourth high-speed signal solder ball HS4 of the second buffer chip elements <NUM>. The two first multiplexers receiving the first signal may be output to either portions associated with the first high-speed signal solder ball HS1 of the second buffer chip elements <NUM> or portions associated with the fourth high-speed signal solder ball HS4 of the second buffer chip elements <NUM>.

The second elements <NUM> may include third buffer chip elements <NUM>, fourth buffer chip elements <NUM>, and second multiplexers <NUM> to 122n (n being a positive integer more than <NUM>). Each of the second multiplexers <NUM> to 122n may select one of signals communicated from the third buffer chip elements <NUM> so as to be communicated to the fourth buffer chip elements <NUM>.

In some embodiments, one signal output from the third buffer chip elements <NUM> may be communicated to two second multiplexers. For example, an output signal (e.g., a second signal) associated with the second high-speed signal solder ball HS2 of the third buffer chip elements <NUM> may be output to a second multiplexer associated with the second high-speed signal solder ball HS2 of the fourth buffer chip elements <NUM> and a second multiplexer associated with the fifth high-speed signal solder ball HS5 of the fourth buffer chip elements <NUM>. The two second multiplexers receiving the second signal may be output to either portions associated with the second high-speed signal solder ball HS2 of the fourth buffer chip elements <NUM> or portions associated with the fifth high-speed signal solder ball HS5 of the fourth buffer chip elements <NUM>.

<FIG> is a block diagram illustrating a nonvolatile memory chip <NUM> according to embodiments of the inventive concept. Referring to <FIG>, the nonvolatile memory chip <NUM> includes a memory cell array <NUM>, a row decoder block <NUM>, a page buffer block <NUM>, a pass/fail check block (PFC) <NUM>, a data input and output block <NUM>, a buffer block <NUM>, and a control logic block <NUM>.

The memory cell array <NUM> includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz includes a plurality of memory cells. Each of the memory blocks BLK1 to BLKz may be connected with the row decoder block <NUM> through ground selection lines GSL, word lines WL, and string selection lines SSL. Some of the word lines WL may be used as dummy word lines. Each of the memory blocks BLK1 to BLKz may be connected with the page buffer block <NUM> through a plurality of bit lines BL. The plurality of memory blocks BLK1 to BLKz may be connected in common with the plurality of bit lines BL.

In some embodiments, each of the plurality of memory blocks BLK1 to BLKz may be a unit of an erase operation. The memory cells belonging to each of the memory blocks BLK1 to BLKz may be erased at the same time. For another example, each of the plurality of memory blocks BLK1 to BLKz may be divided into a plurality of sub-blocks. Each of the plurality of sub-blocks may correspond to a unit of an erase operation.

The row decoder block <NUM> is connected with the memory cell array <NUM> through the ground selection lines GSL, the word lines WL, and the string selection lines SSL. The row decoder block <NUM> operates under control of the control logic block <NUM>.

The row decoder block <NUM> may decode a row address RA received from the buffer block <NUM> and may control voltages to be applied to the string selection lines SSL, the word lines WL, and the ground selection lines GSL based on the decoded row address.

The page buffer block <NUM> is connected with the memory cell array <NUM> through the plurality of bit lines BL. The page buffer block <NUM> is connected with the data input and output block <NUM> through a plurality of data lines DL. The page buffer block <NUM> operates under control of the control logic block <NUM>.

In a program operation, the page buffer block <NUM> may store data to be written in memory cells. The page buffer block <NUM> may apply voltages to the plurality of bit lines BL based on the stored data. In a read operation or in a verify read operation that is performed in the program operation or an erase operation, the page buffer block <NUM> may sense voltages of the bit lines BL and may store the sensing result.

In the verify read operation associated with the program operation or the erase operation, the pass/fail check block <NUM> may verify the sensing result of the page buffer block <NUM>. For example, in the verify read operation associated with the program operation, the pass/fail check block <NUM> may count the number of values (e.g., the number of <NUM>) respectively corresponding to on-cells that are not programmed to a target threshold voltage or more.

In the verify read operation associated with the erase operation, the pass/fail check block <NUM> may count the number of values (e.g., the number of <NUM>) respectively corresponding to off-cells that are not erased to a target threshold voltage or less. When the counted result is a threshold value or more, the pass/fail check block <NUM> may output a fail signal to the control logic block <NUM>. When the counted result is smaller than the threshold value, the pass/fail check block <NUM> may output a pass signal to the control logic block <NUM>. Depending on a result of the verification of the pass/fail check block <NUM>, a program loop of the program operation may be further performed, or an erase loop of the erase operation may be further performed.

The data input and output block <NUM> is connected with the page buffer block <NUM> through the plurality of data lines DL. The data input and output block <NUM> may receive a column address CA from the buffer block <NUM>. The data input and output block <NUM> may output data read by the page buffer block <NUM> to the buffer block <NUM> depending on the column address CA. The data input and output block <NUM> may provide data received from the buffer block <NUM> to the page buffer block <NUM>, based on the column address CA.

The buffer block <NUM> may receive a command CMD and an address ADDR from an external device through a first channel CH1 and may exchange data "DATA" with the external device. The buffer block <NUM> may operate under control of the control logic block <NUM>. The buffer block <NUM> may provide the command CMD to the control logic block <NUM>. The buffer block <NUM> may provide the row address RA of the address ADDR to the row decoder block <NUM> and may provide the column address CA of the address ADDR to the data input and output block <NUM>. The buffer block <NUM> may exchange the data "DATA" with the data input and output block <NUM>.

In some embodiments, the first channel CH1 may correspond to the data signals DQ. The command CMD and the address ADDR may be synchronized with the data strobe signals DQS in the SDR manner, and the data "DATA" may be synchronized with the data strobe signals DQS in the SDR or DDR manner.

The control logic block <NUM> may exchange control signals CTRL with the external device through a second channel CH2. The control logic block <NUM> may allow the buffer block <NUM> to route the command CMD, the address ADDR, and the data "DATA". The control logic block <NUM> may decode the command CMD received from the buffer block <NUM> and may control the nonvolatile memory chip <NUM> based on the decoded command.

In some embodiments, the second channel CH2 may correspond to high-speed signals including the data strobe signals DQS and the read enable signal RE and low-speed signals including the power, the write protect signal WP, the command latch enable signal CLE, the address latch enable signal ALE, the chip enable signal CE, the ready and busy signal RnB, or the write enable signal WE.

In some embodiments, the nonvolatile memory chip <NUM> may be manufactured in a bonding manner. The memory cell array <NUM> may be manufactured at a first wafer, and the row decoder block <NUM>, the page buffer block <NUM>, the pass/fail check block <NUM>, the data input and output block <NUM>, the buffer block <NUM>, and the control logic block <NUM> may be manufactured at a second wafer. The nonvolatile memory chip <NUM> may be implemented by coupling the first wafer and the second wafer such that an upper surface of the first wafer and an upper surface of the second wafer face each other.

For another example, the nonvolatile memory chip <NUM> may be manufactured in a cell over peri (COP) manner. The peripheral circuit including the row decoder block <NUM>, the page buffer block <NUM>, the pass/fail check block <NUM>, the data input and output block <NUM>, the buffer block <NUM>, and the control logic block <NUM> may be implemented on a substrate. The memory cell array <NUM> may be implemented on the upper of the peripheral circuit. The peripheral circuit and the memory cell array <NUM> may be connected by using through vias.

In the above embodiments, components according to the inventive concept are described by using the terms "first", "second", "third", and the like. However, the terms "first", "second", "third", and the like may be used to distinguish components from each other and do not limit the inventive concept. For example, the terms "first", "second", "third", and the like do not involve an order or a numerical meaning of any form.

In the above embodiments, components according to embodiments of the inventive concept are described by using blocks. The blocks may be implemented with various hardware devices, such as an integrated circuit, an application specific IC (ASIC), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as an application, or a combination of a hardware device and software. Also, the blocks may include circuits implemented with semiconductor elements in an integrated circuit or circuits enrolled as intellectual property (IP).

Claim 1:
A memory package (<NUM>, <NUM>, <NUM>) comprising:
a first memory chip (<NUM>) including first memory pads (<NUM>); and
a buffer chip (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) including first buffer pads (<NUM>) respectively connected with the first memory pads (<NUM>) and second buffer pads (<NUM>) connected with an external device,
wherein the buffer chip (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) respectively communicates signals received via the second buffer pads (<NUM>) to the first buffer pads (<NUM>) in response to a swap enable signal having a disabled state, and
the buffer chip swaps signals received via the second buffer pads (<NUM>) to generate first swapped signals, and respectively communicates the first swapped signals to the first buffer pads (<NUM>) in response to the swap enable signal having an enabled state.