Patent Description:
<CIT> relates to a method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal.

The process described in the following with reference to <FIG>, which is based on the implantation of C atoms into the top surface of a SiC epitaxial layer, is similar to one of the alternative processes disclosed in this document.

<CIT> discloses a further method to reduce the carbon vacancy concentration in a SiC semiconductor body. That method comprises forming trenches in a SiC body by means of RIE followed by thermal etching, forming a C-rich layer on the sidewalls of said trenches and diffusing them into the semiconductor body by heat treatment.

<CIT> relates to a SiC reverse blocking MOSFET that includes an active region including a MOS gate structure and a breakdown voltage structure portion surrounding the outer circumference of the active region, which are provided on the surface side of a SiC-n- drift layer that is grown on one main surface of a p+ SiC substrate.

<CIT> relates to a semiconductor device that includes a semiconductor layer made of a wide bandgap semiconductor, a trench that is selectively formed on a surface portion of the semiconductor layer and that defines a unit cell having a predetermined shape on the surface portion, and a surface electrode that is embedded in the trench so as to cover an upper surface of the unit cell and that forms a Schottky junction between the unit cell and the surface electrode, and side surfaces of the trench are formed of only a plurality of planes that have plane orientations crystallographically equivalent to each other.

<CIT> discloses a semiconductor device comprising a semiconductor body of a first semiconductor material, wherein at least a part of the semiconductor body constitutes a drift zone of a first conductivity type. The semiconductor device further comprises a channel layer structure comprising a semiconductor heterojunction between first and second semiconductor layers electrically coupled to the drift zone. The first and second semiconductor layers include semiconductor materials that are different to the first semiconductor material.

<CIT> discloses that, in a semiconductor diode a semiconductor body includes an injection efficiency control region between a drift region of a first conductivity type and a first electrode region of a second, opposite conductivity type. The injection efficiency control region includes a superjunction structure including a barrier region of the first conductivity type and a compensation region of a second conductivity type arranged consecutively along a lateral direction and directly adjoining each other. A net dopant concentration of the barrier region averaged along a vertical extension of the barrier region is at least three times greater than a net dopant concentration of the drift region averaged along <NUM>% of a vertical extension of the drift zone adjoining the barrier region.

Embodiments of the disclosure relate to improved semiconductor devices and methods for their manufacturing. Exemplarily, there is a need for semiconductor devices that have an improved lifetime, low defect density and/or can be manufactured in a flexible way using conventional semiconductor processing steps.

The invention is defined by the attached set of claims. Further details of the disclosed devices and methods are provided in the following, which are helpful for understanding the claimed invention.

According to a first aspect, a semiconductor device comprising at least one epitaxial layer made from a first semiconductor material comprising carbon and having a [<NUM>] crystallographic axis is provided. At least one implantation area is formed at a sidewall of the epitaxial layer, a normal direction of the sidewall being perpendicular to the [<NUM>] crystallographic axis. At least one part of the epitaxial layer has a reduced concentration of carbon vacancies with respect to the first semiconductor material of the at least one epitaxial layer as-grown.

The at least one at least one epitaxial layer made from a first semiconductor material comprises at least one of n-type <NUM>-SiC or n-type <NUM>-SiC semiconductor material. The at least one implantation area comprises an implanted species, comprising at least one of carbon ions or silicon ions. The at least one part of the epitaxial layer is adjacent to the sidewall and has a concentration of carbon vacancy Z<NUM>/<NUM> of below <NUM><NUM>/cm<NUM>.

By providing an implantation area at a sidewall of an epitaxial layer, implantation can be performed independent of other processing steps, which are typically performed in parallel to the [<NUM>] crystallographic axis, e.g. on or through the front face of the epitaxial layer. At the same time, motility of an implanted species is improved, which simplifies a later annealing of the at least one epitaxial layer and results in a reduced concentration of carbon vacancies therein.

According to at least one embodiment, the at least one implantation area is formed on one of a plurality of sidewalls of at least one semiconductor chip comprising the at least one epitaxial layer. Implanting a species through a sidewall of a semiconductor chip allows the reduction of carbon vacancies on already separated, almost finished semiconductor circuit component.

According to at least one embodiment, the semiconductor device comprises at least one trench having two sidewalls formed in the at least one epitaxial layer. The at least one implantation area is formed on at least one of the two sidewalls of the at least one trench. The at least one part of the epitaxial layer corresponds to a sublayer extending in a plane perpendicular to the [<NUM>] crystallographic axis, wherein a thickness of the sublayer corresponds to or exceeds a depth of the at least one trench. Use of trenches allows the implantation of a species on a vertical side-wall of an epitaxial layers having a relatively large spatial extent.

In at least one embodiment, the semiconductor device further comprises at least one electrode formed on a top or bottom surface of the at least one epitaxial layer, thereby forming an electrically active area, wherein the at least one implantation area is formed outside of an electrically active area. For example, the at least one implantation area may be formed in spatial proximity to the electrically active area of the semiconductor device. Such a spatial arrangement allows the reduction of carbon vacancies in the electrically active area without disturbing any elements within the electrically active area implementing a function of the semiconductor device.

For example, the at least one implantation area may comprises an implantation defect area, comprising amorphous silicon.

According to different embodiments, the semiconductor device may comprise different power electronic components, such as a PIN diode, a BJT, an IGBT, or a JBS diode.

According to a second aspect of the disclosure, a method for manufacturing a semiconductor device is provided. The method comprises growing at least one epitaxial layer made from a first semiconductor material comprising carbon and having a [<NUM>] crystallographic axis, and implanting ions through at least one sidewall of the at least one epitaxial layer in a direction perpendicular to the [<NUM>] crystallographic axis to form at least one implantation area, thereby reducing a concentration of carbon vacancies in the first semiconductor material with respect to the at least one epitaxial layer as-grown.

The at least one at least one epitaxial layer made from a first semiconductor material comprises at least one of n-type <NUM>-SiC or n-type <NUM>-SiC semiconductor material. The implanted ions in particular comprise at least one of carbon ions and silicon ions. The first semiconductor material of the finished semiconductor device has a concentration of carbon vacancy Z<NUM>/<NUM> of below <NUM><NUM>/cm<NUM>.

The above steps enable the manufacturing of a semiconductor device according to first aspect. They enable an improved degree of flexibility during manufacturing. In particular, the step of implanting ions can be performed towards the end of the manufacturing process after other steps negatively affecting carbon vacancies of the at least one epitaxial layer have been completed.

According to at least one embodiment, the method further comprises at least one of annealing or proton irradiating the at least one epitaxial layer to further reduce the concentration of carbon vacancies in the first semiconductor material with respect to the at least one epitaxial layer after implanting ions. Annealing or proton irradiation helps to diffuse generated carbon interstitials.

According to at least one embodiment, before implanting ions through at least one sidewall, the method further comprises: performing a plurality of processing steps to form at least one semiconductor circuit component comprising at least parts of the at least one epitaxial layer; and separating the at least one semiconductor circuit component to obtain a semiconductor chip having a top surface perpendicular to the [<NUM>] crystallographic axis and a plurality of sidewalls perpendicular to the top surface. Implanting ions through sidewalls of semiconductor chips enables the reduction of carbon vacancies in a separated, essentially finished semiconductor component.

According to another embodiment, the method further comprises forming at least one trench having two sidewalls within the at least one epitaxial layer, wherein implanting ions through at least one sidewall comprises plasma immersion ion implanting (PIII) of at least one of carbon (C) ions or silicon (Si) ions through the two sidewalls of the at least one trench.

Further aspects, embodiments and advantages of the present invention are disclosed in the following detailed description of embodiments as well as the attached set of claims.

The method for manufacturing a semiconductor device according to the second aspect described above is particularly suitable for manufacturing the semiconductor device according to the first aspect. Features and advantages described in connection with the semiconductor device can therefore be used in the manufacturing method and vice versa.

Thus, every feature described with respect to one of the aspects is also disclosed herein with respect to the other aspect, even if the respective feature is not explicitly mentioned in the context of the specific aspect.

The accompanying figures are included to provide a further understanding. In the figures, elements of the same structure and/or functionality may be referenced by the same reference signs. It is to be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

While the disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the figures and will be described in detail. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure defined by the appended claims.

Before various embodiments of the present disclosure are described in more detail, at first some challenges encountered in conventional silicon carbide semiconductor materials and their processing are discussed.

The so-called carbon vacancy (VC) is a technologically relevant, electrically active point defect in n-type <NUM> silicon carbide (<NUM>-SiC). The presence of carbon vacancy gives rise to two levels in the bandgap of the semiconductor material, referred to as Z<NUM>/<NUM> and EH<NUM>/<NUM>, located at <NUM> eV and <NUM> eV below the conduction band edge (EC), respectively. As the level of Z<NUM>/<NUM> defects is particularly close to the conduction band edge, it acts as a recombination center, affecting the lifetime, forward voltage drop of bipolar devices and leakage current in unipolar devices formed from such semiconductor materials.

In principle, it is possible to remove a carbon vacancy from an epitaxial layer as-grown as shown in <FIG>.

A semiconductor device <NUM> comprises a <NUM>-SiC epitaxial layer <NUM> grown on a surface of a substrate <NUM> in a [<NUM>] crystallographic axis direction X, as defined by Miller-Bravais indices. The [<NUM>] crystallographic axis typically corresponds to the normal direction of the surface of the substrate <NUM>. As-grown, the epitaxial layer <NUM> will comprise a number of carbon vacancies VC throughout the <NUM>-SiC epitaxial layer <NUM>. To reduce the concentration of carbon vacancy VC, a top surface area 4a is either oxidized at a temperature of <NUM> to <NUM>. Alternatively, a shallow carbon ions may be implanted into the top surface area 4a of SiC epitaxial layer <NUM>. Either approach will in the introduction of carbon interstitials CI into the <NUM>-SiC epitaxial layer <NUM>. Then, the epitaxial layer <NUM> is annealed at a temperature in excess of <NUM>, resulting in a diffusion of the carbon interstitials CI throughout the epitaxial layer <NUM>. The carbon interstitials CI can then recombine with the carbon vacancies VC. Consequently, the epitaxial layer <NUM> will have a reduced carbon vacancy concentration.

As shown in <FIG>, Carbon implantation is performed parallel to the [<NUM>] crystallographic axis. After diffusion of carbon interstitials CI, reactive ion etching (RIE) or chemical mechanical polishing (CMP) is used in order to remove the C-implanted layer formed in the top surface area 4a. A similar situation would occur if oxidation is employed for carbon vacancy VC reduction, where the oxide layer needs to be removed using hydrofluoric acid (HF).

Thus, the method for reducing carbon vacancy described above can only be carried out relatively early in a manufacturing processes, e.g. on the epitaxial layer <NUM> as-received. While this results in a <NUM>-SiC epitaxial layer <NUM> having a reduced concentration of carbon vacancies VC towards the start of the manufacturing of a semiconductor device <NUM>, subsequent processing steps such as activation of a highly doped p+ area or annealing of electrodes of an semiconductor circuit component, result in a regeneration of carbon vacancies VC in the epitaxial layer <NUM>. Once the carbon vacancies VC have been re-generated, a second Carbon ion implantation cannot be performed, as this would require implanting Carbon into electrically active areas of the semiconductor device, such as an anode area or electrode. Moreover, oxidation cannot be performed, as this would consume parts of the active circuit structures in case of relatively thick epitaxial layers <NUM>, e.g. epitaxial layers <NUM> having a thickness of <NUM> or more.

The present disclosure aims to describe alternative methods and devices having a reduced carbon vacancy concentration as compared to an epitaxial layer as-grown.

<FIG> shows a semiconductor device <NUM> according to an embodiment of the present disclosure. Steps S1 to S3 of a method for reducing carbon vacancy VC of an epitaxial layer <NUM> of the semiconductor device <NUM> are shown in <FIG>.

In a step S1, the epitaxial layer <NUM> is grown on a substrate <NUM> or other epitaxial layer (not shown). Initially, the epitaxial layer <NUM> will comprise a relatively high concentration of carbon vacancy VC. For example, untreated n-type <NUM>-SiC semiconductor material of the epitaxial layer <NUM> may have comprise <NUM><NUM> Z<NUM>/<NUM> defects per cm<NUM>.

Thus, in step S2, ions, for example carbon (C) ions, aluminum (Al) ions or silicon (Si) ions, are implanted through a sidewall 3a to form an implantation area <NUM> in the semiconductor material. Contrary to the situation shown in <FIG>, in the embodiment shown in <FIG>, ions are implanted through sidewalls 3a to form implantation areas <NUM> in a plane perpendicular to a top surface of the semiconductor device. That is to say, the implantation direction is perpendicular to the [<NUM>] crystallographic axis direction X of the epitaxial layer <NUM>. The side implantation may be performed at room temperature.

In the embodiment shown in <FIG>, carbon ions are implanted through two opposite sidewalls 3a to form carbon interstitial CI in two implantation areas <NUM>. It is also possible to implant ions through a single sidewall 3a to form a single implantation area <NUM>, or to implant ions through three or four sidewalls <NUM>, for example all sidewalls of a rectangular semiconductor chip. In the described embodiment, side implantation of Carbon on a <NUM>-<NUM> x <NUM><NUM> cm-<NUM> N-doped epitaxial layer <NUM> was carried out. One or more side implantation energies can be chosen so that the implantation profile will be outside the active electric area of the semiconductor device <NUM>. For example, three different implantation stages with energies in the range of <NUM> to <NUM> keV may be used. Side implantation doses can range from <NUM><NUM> to <NUM><NUM> cm-<NUM>.

As shown in <FIG>, step S2 may be carried out immediately after growing the epitaxial layer S1. However, it is also possible to form the implantation areas <NUM> towards the end of manufacturing the semiconductor device <NUM> as later described with regard to various specific semiconductor devices.

Side implantation can be followed by an optional, separate diffusion step S3. For example, the epitaxial layer <NUM> may be annealed at temperatures in excess of <NUM> for periods between <NUM> minute and <NUM> hours depending on the thickness of the epitaxial layer <NUM>. The thickness of the epitaxial layer <NUM> may lie in a range of <NUM> to <NUM> for example. In the described embodiment, the epitaxial layer <NUM> a relatively short annealing step is carried out at a temperature of <NUM> for a period of <NUM> minutes. During this period, the generated carbon interstitials CI further diffuse throughout the epitaxial layer <NUM>. Alternatively or in addition, proton irradiation may be used to further diffuse the generated carbon interstitials CI. For example, proton irradiation at or below <NUM> keV may be used.

Alternatively, side implantation with no subsequent diffusion step can be carried out on a finished semiconductor component. For example, after implantation of carbon with energies equal or higher than <NUM> keV, sufficient diffusion of carbon interstitials CI takes place without an additional diffusion step.

It has been found that point defects in crystal structure of the epitaxial layer <NUM> can migrate quickly and thus a relatively long distances perpendicular to the [<NUM>] crystallographic axis direction X. For example, carbon interstitials can diffuse long distances perpendicular to [<NUM>] direction after <NUM> keV proton irradiation even at room temperature. This in turn significantly reduces carbon vacancy VC throughout the epitaxial layer <NUM>. For example, using the parameters described above, a horizontal diffusion length of several millimeters can be achieved, resulting in a significant reduction of carbon vacancy VC throughout the entire width of the epitaxial layer <NUM> of a semiconductor chip having an edge length of <NUM>, for example. For example, a concentration of carbon vacancies VC may be reduced by two or more orders of magnitude as compared with the epitaxial layer <NUM> as-grown.

<FIG> shows the result of deep level transient spectroscopy (DLTS) analysis of the semiconductor device <NUM> according to <FIG>. Therein, the curve with reference sign A shows a DLTS spectrum of untreated n-type <NUM>-SiC epitaxial layer <NUM> as-grown after step S1. The curve shows with reference sign B shows the DLTS spectrum of the epitaxial layer <NUM> after implantation of carbon ions in step S2 and annealing in step S3. As can be seen, after step S1, the untreated semiconductor device <NUM> comprises a relatively high concentration of carbon vacancy. Exemplarily, it comprises a concentration of Z<NUM>/<NUM> defects in the order of <NUM><NUM>/cm<NUM>. As detailed above, the defect level Z<NUM>/<NUM> is very close to the conduction band edge EC and would therefore negatively affect the performance of a finished semiconductor device <NUM>.

After implantation of carbon ions in step S2 and annealing of the epitaxial layer in step S3, no detectable amount of Z<NUM>/<NUM> defects are present in the semiconductor device <NUM>. In addition, as can be seen in <FIG>, the presence of so-called deep level ON1 and ON2 peaks that lie <NUM> eV and <NUM> eV below the conduction band edge EC, respectively, can be detected. ON1 and ON2 levels are associated with carbon diffusion and typically detected after the implantation of carbon ions as described above with regard to <FIG>. Accordingly, side implantation of carbon ions through sidewalls 3a of a semiconductor device greatly reduce the concentration of carbon vacancy VC of an epitaxial layer <NUM> with respect to the concentration of carbon vacancies VC in the same epitaxial layer <NUM> as-grown.

In the following, manufacturing processes for various semiconductor devices <NUM> are described in more detail. The described processing steps will make apparent that a side implementation as described above with regard to <FIG> provides an enhanced degree of flexibility in the manufacturing of semiconductor devices <NUM>.

At first, processing steps for manufacturing a PIN diode <NUM> are shown with respect to <FIG>. In a first processing step shown in <FIG>, an n-type <NUM>-SiC epitaxial layer <NUM> is grown on a substrate <NUM>. As described above, the epitaxial layer <NUM> will have a relatively high concentration of carbon vacancies VC. In a next processing step shown in <FIG>, the epitaxial layer <NUM> is implanted with aluminum ions to form a highly doped p-type anode area <NUM>. This is followed by a high temperature annealing step (not shown).

During the annealing, further carbon vacancies VC are generated, even in the case carbon vacancies VC had been previously removed.

<FIG> shows the final p+-i-n structure of the PIN diode <NUM>, further comprising implanted field relaxation layers <NUM> formed by conventional ion implantation. In addition, a metal anode electrode <NUM> and a metal cathode electrode <NUM> are formed on a top and bottom surface of the anode area <NUM> and the substrate <NUM>, respectively. The anode electrode <NUM> and the cathode electrode <NUM> may be formed by electron-beam deposition. Forming of the field relaxation layers <NUM>, the anode electrode <NUM> and the cathode electrode <NUM> may result in the generation of further carbon vacancies VC in the epitaxial layer <NUM> acting as an intrinsic drift layer of the PIN diode <NUM>.

To improve the performance of the PIN diode <NUM>, and exemplarily of the n-type epitaxial layer <NUM>, two implantation areas <NUM> are formed on the sidewalls 3a of the PIN diode <NUM> (also shown in <FIG>). Implantation of Carbon or other ions in the implantation areas <NUM> and optional subsequent annealing of the epitaxial layer <NUM> will result in a reduced carbon vacancy VC concentration in the epitaxial layer <NUM> acting as a drift layer. This is indicated in <FIG> by the lighter shading of the epitaxial layer <NUM>.

As detailed above with <FIG>, the side implantation and subsequent annealing will also generate ON1 and ON2 levels. However, the presence of ON1 and ON2 levels in the epitaxial layer <NUM> does not influence the performance of the PIN diode <NUM>.

In the described embodiment, forming of the field relaxation areas <NUM> is performed by frontside processing of the epitaxial layer <NUM> on a wafer or other substrate <NUM>. Similarly, formation of the electrodes <NUM> and <NUM> is implemented by conventional metallization procedures from the front and back surfaces of the semiconductor device <NUM>. For efficiency, typically a relatively large number of semiconductor devices <NUM>, such as PIN diodes <NUM> are formed together on a common wafer or other substrate <NUM>.

To implant ions in the vertical implantation areas <NUM>, an area of the wafer or other substrate <NUM> corresponding to the PIN diode <NUM> may be separated from similar semiconductor circuit components grown on the same wafer or other substrate <NUM> by dicing. Thereby, individual semiconductor chips are formed, which may then be installed with the [<NUM>] crystallographic axis pointing sideways into an ion implantation system to implant carbon ions through the sidewalls 3a of the individual semiconductor chips. For this purpose, a modified target holder carrying one or more semiconductor chips may be employed. During implantation, a first implantation direction <NUM> for implanting ions into the field relaxation area <NUM> of the epitaxial layer <NUM> is orthogonal to a second implantation direction <NUM> for implanting ions into the implantation area <NUM>. Moreover, due to the side implantation, the implantation area <NUM> extends over the entire side surface of the semiconductor material, comprising the substrate <NUM> and the epitaxial layer <NUM>.

<FIG> show processing steps for manufacturing a bipolar junction transistor (BJT) <NUM>, exemplarily an NPN transistor, according to an embodiment of the present disclosure. In a first step shown in <FIG>, an n-type collector <NUM> made from a semiconductor material comprising carbon, such as <NUM>-SiC or <NUM>-SiC, is provided. Subsequently, a p-type base <NUM> is epitaxially grown on the n-type collector <NUM> (<FIG>). Then, an n-type emitter layer <NUM> is epitaxially grown on the p-type base <NUM> (<FIG>).

Subsequently, selected areas of the emitter <NUM> and corresponding top parts of the base <NUM> are etched to allow for the formation of gate electrodes as shown in <FIG>. At the base of the etched trenches, highly doped p-type layers <NUM> are formed in the p-type base <NUM>. Thereafter, a gate electrode <NUM> is formed on a top surface of the highly doped p-type layer <NUM>, an emitter electrode <NUM> is formed on a top surface of the n-type emitter <NUM>, and a collector electrode <NUM> is formed on a bottom surface of the n-type collector <NUM>.

The semiconductor material of both the n-type collector <NUM> as well as the n-type emitter <NUM> will comprise an increased concentration of carbon vacancies VC present in the respective epitaxial layers <NUM> as-grown and/or further processed during a processing of the BJT <NUM>. To reduce the carbon vacancy VC in the collector <NUM> and emitter <NUM>, implantation areas <NUM> are formed on sidewalls 3a of the BJT <NUM> as described above. The presence of the implantation areas <NUM> will result in the formation of carbon interstitials CI and thus a reduction of the carbon vacancy VC.

While the manufacturing method shown in <FIG> has been described with respect to formation of an NPN BJT, similarly, a PNP BJT may be formed using the disclosed side implantation method, comprising a n-type base with a reduced carbon vacancy VC after annealing with respect to the epitaxial layer later forming the base as-grown.

<FIG> show two stages of manufacturing an insulated-gate bipolar transistor (IGBT) <NUM>. Initially, an n-type base <NUM> made from <NUM>-SiC or <NUM>-SiC is epitaxially grown on a p-type collector <NUM>, as shown in <FIG>.

As shown in <FIG>, within the n-type base <NUM>, two p-type base wells <NUM> are formed by ion implantation through a top surface of the n-type base <NUM>. Therein, a total of four n-type areas <NUM> are formed by either plasma immersion ion implantation (PIII) or conventional ion implantation.

Thereafter, an oxide layer <NUM>, serving as electrical insulator, is formed in the central area of the n-type base <NUM> between right (inner) n-type area <NUM> of the left p-type base well <NUM> and the left (inner) n-type area <NUM> of the right p-type base well <NUM>. On top of the oxide layer <NUM>, an insulated gate electrode <NUM> is formed. Moreover, one or more emitter electrodes <NUM> are formed on top surface of the n-type areas <NUM>. On the back surface of the p-type collector <NUM>, a collector electrode <NUM> is formed. The electrodes <NUM>, <NUM> and <NUM> may be formed by e-beam deposition.

Although not shown in <FIG>, a buffer layer can be present at the interface between the n-type base <NUM> and the p-type collector <NUM>.

As detailed above, the n-type base layer <NUM> will have a high carbon vacancy VC concentration after forming the IGBT <NUM>. To reduce the unwanted point defects, implantation areas <NUM> are formed on sidewalls 3a of the IGBT <NUM> before annealing the n-type base <NUM>. As described above, this will remove carbon vacancy VC from the base <NUM> and result in the generation of ON1 and ON2 in the n-type layers <NUM> and <NUM>. However, the generated ON1 and ON2 are not harmful for the manufactured semiconductor device, e.g. the IGBT <NUM>. Moreover, although the process has been described for an IGBT <NUM> comprising an n-type base layer <NUM>, the same applies for an IGBT fabricated starting from an n-type collector layer and having a p-type base layer.

It is noted that in the examples described above with reference to <FIG>, it is not necessary to remove the implantation areas <NUM> after device manufacturing. In each case, the implantation area <NUM> is placed outside an electrically active area of the respective semiconductor device <NUM>. Thus, no additional RIE or CMP step is required as part of the disclosed manufacturing method, and the finished semiconductor device <NUM> may comprise a high concentration of the implanted species, such as carbon, in the implantation area <NUM>. Even in the case that an part of the implantation area <NUM> comprising the implanted species is removed after annealing, for example by RIE or CMP of the sidewalls 3a of the finished semiconductor chip, a remaining implantation defect area of the implantation area <NUM> will still contain amorphous silicon indicative of the previous side implantation step. Similarly, compared to the oxidation method detailed above with respect to <FIG>, no long oxidation time and no long HF etching time are required.

The described methods and devices have further advantages. For example, carbon vacancy VC can be reduced in epitaxial layers <NUM> of any thickness. The process is especially suited for very thick drift layers of more than <NUM> thickness. The method can be applied to both unipolar and bipolar devices. Some processing steps, such as annealing, can be carried out at lower temperatures compared to prior art methods.

The above steps for implanting ions through one or more sidewalls 3a of an individual semiconductor device <NUM> are particularly useful if the electrically active area of the finished device does not exceed the diffusion length of the implanted species. This will be the case for many typical power components, such as the PIN diode <NUM>, the BJT <NUM> and the IGBT <NUM> described above. However, in the case of relatively large electrically active areas or in the case that carbon vacancy VC removal is required before separation of individual semiconductor circuit component, an implantation through a sidewall of the epitaxial layer <NUM> can also be achieved using one or more trenches formed in an epitaxial layer <NUM> as described in further detail below. This may also be used in semiconductor devices, in which trenches are formed throughout a normal manufacturing process anyhow.

<FIG> schematically shows a cross-sectional view of a semiconductor device <NUM> according to an embodiment of the disclosure. The semiconductor device <NUM> comprises an epitaxial layer <NUM> of a reduced concentration of carbon vacancy Vc. The semiconductor device <NUM> comprises, besides the epitaxial layer <NUM>, a trench <NUM> extending in the epitaxial layer <NUM>. The trench <NUM> comprises an implantation layer <NUM> in form of an implanted carbon layer, which is provided on the trench sidewalls 3a and a trench bottom 3b. Instead of carbon (C), one of boron (B), aluminum (Al), germanium (Ge), nitrogen (N), phosphorus (P), arsenic (As), oxygen (O), sulfur (S), hydrogen (H), argon (Ar) or silicon (Si) may be implanted.

For example, the implantation may be performed by plasma immersion ion implantation (PIII). PIII can also be performed on the top surface of the epitaxial layer <NUM>, e.g. the main or front surface of the epitaxial layer <NUM>, at which the trench <NUM> opens. Thus, PIII can also be performed parallel to the [<NUM>] crystallographic axis (not shown in <FIG>). If PIII is applied at the front surface of the epitaxial layer <NUM>, the formed PIII sublayer needs to be removed later by dry etching. However, as detailed below, this is not necessary for surfaces within the trench <NUM>.

The epitaxial layer <NUM> comprises an epitaxial sublayer 2a of a reduced concentration of carbon vacancy Vc. As shown, the epitaxial sublayer 2a of the reduced concentration of carbon vacancy Vc extends perpendicular to a [<NUM>] crystallographic axis and parallel to this axis, and a thickness of the epitaxial sublayer 2a of the reduced carbon vacancy at least corresponds to a depth DT of the trench <NUM>.

Without any treatment, the epitaxial layer <NUM> based on Silicon Carbon (SiC) comprises an amount of electrically active levels, corresponding to the carbon vacancy (Vc) concentration, which cannot be neglected. In <FIG>, unfilled circles in the epitaxial layer are shown to illustrate the occurrence of carbon vacancy VC as detailed above.

The inventors have found that after plasma immersion ion implantation of a suitable species, such as B, Al, C, Si, Ge, N, P, As, O, S, F, H or Ar, and annealing the implantation area at <NUM>, carbon vacancies VC can be removed in an area of the epitaxial layer <NUM> below the implantation surface, for example a sublayer of <NUM> thickness along the [<NUM>] crystallographic axis. However, as detailed above, in a direction perpendicular to the [<NUM>] crystallographic axis, carbon vacancies VC can be removed over a much larger distance. For example, a horizontal diffusion length of several millimeters can be achieved. The PIII implanted species are confined in a relatively small space, for example a sublayer having a thickness of less than <NUM>. This causes stress that releases CI.

According to the exemplary embodiment of <FIG>, the epitaxial layer <NUM> comprises the trench <NUM> with the implantation layer <NUM>. The carbon layer <NUM>, for example, has a thickness of less than <NUM>. As detailed above, the PIII carbon in the trench sidewalls 3a and trench bottom 3b provides carbon interstitials CI, which are defects, and which can migrate perpendicular to the [<NUM>] crystallographic axis and recombine with the electrically active defects providing the carbon vacancy Vc as detailed above. In <FIG>, filled circles in the epitaxial layer <NUM> are shown to illustrate the carbon interstitials CI.

In <FIG>, the trench <NUM> extends parallel to or along the [<NUM>] crystallographic axis of the epitaxial layer <NUM>. The trench <NUM> may also extend at an angle α relative to the [<NUM>] crystallographic axis. In such case, the thickness of the epitaxial sublayer 2a and the depth of the trench <NUM> are defined by L = D cos (α).

In this context, L is a length of the PIII carbon layer <NUM> from a trench inlet to a trench ending. In the exemplary embodiment of <FIG>, L corresponds to the trench depth DT. D is a distance, which is measured parallel to the [<NUM>] crystallographic axis, from a beginning of the implantation layer <NUM> to an ending of the implantation layer <NUM> in the trench <NUM>. In the exemplary embodiment of <FIG>, D corresponds to the trench depth DT. α is an angle between L and D. In the exemplary embodiment of <FIG>, α is zero.

<FIG> schematically shows a deep level transient spectroscopy (DLTS) spectrum of an epitaxial layer <NUM> being treated by a method according to an embodiment. The epitaxial layer <NUM> is made of <NUM>-SiC. The DLTS spectrum is shown for the epitaxial layer <NUM> with and without Carbon diffusion perpendicular to the [<NUM>] crystallographic axis. The curve indicated by the reference sign A represents the DLTS spectrum in untreated material, that means the level Z<NUM>/<NUM> is in a range of <NUM><NUM> <NUM>/cm<NUM>. The curve indicated by the reference sign B represents the DLTS spectrum after implantation. It can be seen that no level Z<NUM>/<NUM> defects can be detected. Thus, as the <FIG> shows, after diffusion, the concentration of the level Z<NUM>/<NUM>, that means the negative charge state of the electrically active defects providing the carbon vacancy VC, is below a detection limit.

A manufacturing method according to an embodiment will be explained based on the flow diagram of <FIG> and specific embodiments as shown in <FIG>. The manufacturing method is suitable for providing a semiconductor device <NUM> with an epitaxial layer <NUM> with a reduced concentration of electrically active carbon levels in the epitaxial layer <NUM>. The semiconductor device <NUM> produced according to the steps shown in <FIG> is a Junction Barrier Schottky (JBS) diode <NUM>.

According to a step S12, the method comprises providing an epitaxial layer <NUM> on a substrate <NUM> (see <FIG> and <FIG>). The embodiment of <FIG> shows an n-type <NUM>-SiC epitaxial layer <NUM> with a doping concentration in a range from <NUM><NUM> <NUM>/cm<NUM> to <NUM><NUM> <NUM>/cm<NUM> being grown on a <NUM>-SiC substrate with a doping concentration of <NUM><NUM> <NUM>/cm<NUM>. The epitaxial layer thickness and doping are selected according to a voltage class of the semiconductor device <NUM>.

According to a step S12, the method comprises providing a photoresist layer <NUM> on the epitaxial layer <NUM> (see <FIG> and <FIG>) and exposing the photoresist layer <NUM> with electromagnetic radiation using a mask (not depicted). For example, the photoresist layer <NUM> being deposited on the epitaxial layer surface is patterned by photolithography according to the desired shape/dimensions of the trenches <NUM> which are provided in a subsequent step.

According to a step S13, the method comprises providing two trenches <NUM> in the epitaxial layer <NUM> (see <FIG> and <FIG>). For example, the epitaxial layer <NUM> is etched by reactive ion etching (RIE) in order to form the trenches <NUM>. The trenches <NUM> can have any cross section, such as square, round, rectangular, or polygonal. If DT is the depth of the trench <NUM> and <NUM> the width of the cross section, deep trenches <NUM> (DT>><NUM>) can also be formed.

According to a step S14, the method comprises implanting carbon or another suitable species in each of the trenches <NUM> (see <FIG> and <FIG>). In the described example, the trench sidewalls 3a and the trench bottom 3b of the trenches <NUM> are implanted with Carbon by plasma immersion ion implantation (PIII) to obtain the maximum doping concentration but not exceeding a solubility limit.

According to a step S15, the method comprises filling the trenches <NUM> with p-type polysilicon <NUM> (see <FIG> and <FIG>). The step of filling the trenches <NUM> with p-type polysilicon <NUM> may be, alternatively, carried out after removing the photoresist layer <NUM> (see description in the context of step S16 below). As detailed later, filling the trenches <NUM> may assist in forming contacts, and generally will improve the mechanical stability of the finished semiconductor device <NUM>.

According to a step S16, the method comprises carrying out an annealing process such that carbon ion diffusion from the at least one trench <NUM> perpendicular and/or parallel to a crystallographic [<NUM>] axis of the at least one epitaxial layer <NUM> is induced (see <FIG>; the diffusion process is not illustrated in <FIG>; <FIG> illustrates the diffusion process of the carbon interstitials CI). For example, Carbon is diffused by annealing at a temperature of less than <NUM> for a time in the range from <NUM> minutes to <NUM> minutes. Subsequently, oxygen plasma ashing is, for example, employed to remove the photoresist layer <NUM>.

Alternatively, the photoresist layer <NUM> can be removed after PIII in steps S14, and a graphitic cap is then formed on the epitaxial layer surface so to ensure low surface roughness on the trench walls 3a during activation. After annealing, a graphitic cap can be removed by oxygen plasma ashing.

Following Carbon diffusion, the epitaxial layer <NUM> has a VC concentration below the detection limit.

According to a step S17, the method comprises providing contact layers <NUM> according to a functioning of the semiconductor device <NUM>. In the exemplary embodiment, metal is deposited on an epitaxial layer surface and on a backside for Schottky/ohmic contact formation.

The manufacturing method according to the embodiment of <FIG> will also be described based on the <FIG>. The semiconductor device <NUM> produced according to the steps shown in <FIG> is a Bipolar Junction Transistor (BJT) <NUM>. In the exemplary embodiment, the BJT <NUM> is an NPN transistor.

<FIG> schematically shows a first step of the method for producing the BJT <NUM>. Two epitaxial layers <NUM> are provided, which are grown on a substrate <NUM>. The <FIG> shows an upper n-type <NUM>-SiC epitaxial layer <NUM> with a doping concentration in a range from <NUM><NUM> <NUM>/cm<NUM> to <NUM><NUM> <NUM>/cm<NUM>. It is grown on a middle epitaxial p-type epitaxial layer <NUM> with a doping concentration in a range from <NUM><NUM> <NUM>/cm<NUM> to <NUM><NUM> <NUM>/cm<NUM> on top of a <NUM>-SiC substrate <NUM> with a doping concentration of <NUM><NUM> <NUM>/cm<NUM>. The layer thicknesses and doping concentrations are selected according to the voltage class of the BJT <NUM>.

<FIG> schematically shows a second step of the method for producing the BJT <NUM>. The epitaxial layers <NUM> are etched by reactive ion etching (RIE) in order to form two trenches <NUM>. The trenches <NUM> can have any cross section, such as square, round, rectangular, or polygonal. Carbon is implanted in the trenches <NUM> by PIII and later diffused by annealing. After Carbon diffusion the upper epitaxial layer <NUM> corresponding to the n-type emitter <NUM> as well as the substrate <NUM> corresponding to the n-type collector <NUM> have a low carbon vacancy concentration. Trench sidewalls 3a and an epitaxial layer top can be protected by a graphitic cap.

<FIG> schematically shows a third step of a method for producing the BJT <NUM>. In this step, oxygen plasma ashing is employed to remove the graphitic cap. Last, high-doped p-type layers <NUM> are formed and metal is deposited for providing gate electrodes <NUM>, emitter electrodes <NUM>, and collector electrodes <NUM>.

The manufacturing method according to the embodiment of <FIG> will also be described based on the <FIG>. The semiconductor device <NUM> produced according to the steps shown in <FIG> is an insulated-gate bipolar transistor (IGBT) <NUM>.

<FIG> schematically shows a first step of the method for producing the IGBT <NUM>. The <FIG> shows an n-type <NUM>-SiC epitaxial layer <NUM> with a doping concentration in a range from <NUM><NUM> <NUM>/cm<NUM> to <NUM><NUM> <NUM>/cm<NUM> on top of a <NUM>-SiC substrate <NUM> with a doping concentration of <NUM><NUM> <NUM>/cm<NUM>. The epitaxial layer and substrate thicknesses and doping concentrations are selected according to the voltage class of the IGBT <NUM>.

<FIG> schematically shows a second step of the method for producing the IGBT <NUM>. The epitaxial layer <NUM> is etched by reactive ion etching (RIE) in order to form two trenches <NUM>. In this example, a depth DT of the trenches <NUM> corresponds to a thickness of the epitaxial layer <NUM>. A relatively deep trench <NUM> as shown in <FIG> assists in removing carbon vacancies throughout a relatively thick epitaxial layer <NUM>. The trenches <NUM> can have any cross section, such as square, round, rectangular, or polygonal. Carbon is implanted in the trenches <NUM> by PIII and later diffused by annealing. After Carbon diffusion the epitaxial layer <NUM> comprising an n-type base <NUM> has a low carbon vacancy concentration. The trench sidewalls 3a and an epitaxial layer top can be protected by a graphitic cap.

<FIG> schematically shows a third step of the method for producing the IGBT <NUM>. In this step, oxygen plasma ashing is employed to remove the graphitic cap. Two p-type base well <NUM> are formed by ion implantation and a total of four n-type areas <NUM> are formed inside them by either PIII or by ion implantation. Ion implantation would be carried out in a state, in which the device manufacturing is in the state shown in <FIG>. At last, a gate electrode <NUM>, an emitter electrode <NUM>, and a collector electrode <NUM> are formed by e-beam deposition. The gate electrode <NUM> is provided with an oxide layer <NUM>, which insulated the gate from the epitaxial layer <NUM> with the active electrical areas formed therein. A buffer layer can also be provided at the base/collector interface (not shown in <FIG>).

Claim 1:
A method for manufacturing a semiconductor device (<NUM>), comprising:
- growing at least one epitaxial layer (<NUM>), the at least one epitaxial layer (<NUM>) made from a first semiconductor material having a [<NUM>] crystallographic axis and comprising at least one of n-type <NUM>-SiC or n-type <NUM>-SiC semiconductor material; and
- implanting ions, comprising at least one of carbon ions and silicon ions, through at least one sidewall (3a) of the at least one epitaxial layer (<NUM>) in a direction perpendicular to the [<NUM>] crystallographic axis to form at least one implantation area (<NUM>), thereby reducing a concentration of carbon vacancies (VC) in the first semiconductor material with respect to the at least one epitaxial layer (<NUM>) as-grown, such that the respective first semiconductor material of the finished semiconductor device (<NUM>) has a concentration of carbon vacancy Z<NUM>/<NUM> of below <NUM><NUM>/cm<NUM>.