Patent Description:
As a semiconductor memory device, a nonvolatile memory device maintains information even when the power is turned off, and includes a number of memory cells that may use the stored information again when the power is turned on. Nonvolatile memory devices may be used in mobile phones, digital cameras, portable digital assistants (PDAs), mobile computer devices, fixed computer devices, and other devices.

Research is underway on the use of three-dimensional (or vertical) NAND (VNAND) on next-generation neuromorphic computing platforms or chips to form a neural network.

US Patent Application Number <CIT> describes a nonvolatile memory device with a vertical stack-type structure.

Provided are a nonvolatile memory device including a conductive pillar and an operating method of the same.

Provided are a nonvolatile memory device capable of applying a voltage having a small intensity to a semiconductor layer and an operating method of the same.

According to the invention, there is provided a nonvolatile memory device according to claim <NUM>.

In some embodiments, the first voltage and the second voltage may be different from each other.

In some embodiments, the first voltage may be greater than the second voltage.

In some embodiments, a difference between the first voltage and the second voltage may be less than an absolute value of the second voltage.

In some embodiments, the absolute value of the second voltage may be <NUM> V or less.

In some embodiments, the nonvolatile memory device may further include a controller. The controller may be configured to apply a turn-off voltage to a gate electrode corresponding to a selection memory cell among the plurality of gate electrodes, and the controller may be configured to apply a turn-on voltage to a gate electrode corresponding to a non-selection memory cell among the plurality of gate electrodes.

In some embodiments, the turn-off voltage may be less than at least one of the first voltage and the second voltage.

In some embodiments, the turn-on voltage may be greater than at least one of the first voltage and the second voltage.

In some embodiments, a difference between the first voltage and the second voltage may be less than a difference between the turn-on voltage and the turn-off voltage.

In some embodiments, all regions of the conductive pillar may be spatially spaced apart from all regions of the semiconductor layer.

In some embodiments, the nonvolatile memory device may further include an insulating layer between the resistance change layer and the conductive pillar.

In some embodiments, the insulating layer may include silicon oxide.

In some embodiments, the nonvolatile memory device may further include an insulating layer in the conductive pillar.

In some embodiments, the insulating layer in the conductive pillar may contact the resistance change layer.

Meanwhile, according to the invention, an operating method of a nonvolatile memory device is provided according to claim <NUM>.

For example, "at least one of A, B, and C," and similar language (e.g., "at least one selected from the group consisting of A, B, and C") may be construed as A only, B only, C only, or any combination of two or more of A, B, and C, such as, for instance, ABC, AB, BC, and AC.

When the terms "about" or "substantially" are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical value. Moreover, when the words "generally" and "substantially" are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as "about" or "substantially," it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical values or shapes. When ranges are specified, the range includes all values therebetween such as increments of <NUM>%.

In the disclosure, terms, such as "in some embodiments" or "in one embodiment" appearing in various places do not necessarily refer to the same embodiment.

Some embodiments of the disclosure may be represented by functional block configurations and various processing steps. Some or all of these functional blocks may be implemented with various numbers of hardware and/or software configurations that execute specific functions. For example, functional blocks of the disclosure may be implemented by a microprocessor or may be implemented by circuit configurations for certain functions. Functional blocks of the disclosure may be implemented in various programming or scripting languages. Functional blocks may be implemented by an algorithm executed by a processor. In addition, the disclosure may employ the prior art for electronic environment setting, signal processing, and/or data processing. Terms, such as "mechanism", "element", "means" and "configuration" may be widely used and are not limited to mechanical and physical configurations.

In addition, connection lines or connection members between components shown in the drawings are merely illustrative of functional connections and/or physical or circuit connections. In an actual device, connections between components may be represented by various functional connections, physical connections, or circuit connections that are replaceable or added.

Terms, such as "include" or "comprise" used in the disclosure should not be construed as necessarily including all of various components or steps described in the disclosure, and it should be understood that some of the components or some steps may not be included, or may further include additional components or steps.

Hereinafter, the term "upper portion" or "on" may also include "to be present above, below, or in the left or right on a non-contact basis" as well as "to be on the top portion, the bottom portion, or in the left or right in directly contact with". Hereinafter, only example embodiments will be described in detail with reference to the accompanying drawings.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by terms. The terms are used only for the purpose of distinguishing one component from other components.

<FIG> is a block diagram illustrating a memory system according to an embodiment.

Referring to <FIG>, the memory system <NUM> may include a memory controller <NUM> and a memory device <NUM>. The memory controller <NUM> performs a control operation on the memory device <NUM>, and for example, the memory controller <NUM> may perform a write (or read) operation on the memory device <NUM> by providing an address ADD and a command CMD to the memory device <NUM>. In addition, data for a write operation and read data may be transmitted and received between the memory controller <NUM> and the memory device <NUM>.

The memory device <NUM> may include a memory cell array <NUM> and a voltage generator <NUM> (e.g., power circuitry). The memory cell array <NUM> may include a plurality of memory cells arranged in regions where a plurality of word lines and a plurality of bit lines cross each other. The memory cell array <NUM> may include nonvolatile memory cells that store data so as to be nonvolatile, and as nonvolatile memory cells, the memory cell array <NUM> may include flash memory cells, such as a NAND flash memory cell array or a NOR flash memory cell array. Hereinafter, the embodiments of the disclosure will be described in detail assuming that the memory cell array <NUM> includes the flash memory cell array, and thus the memory device <NUM> is a nonvolatile memory device.

The memory controller <NUM> may include a write/read (WR/RD) controller <NUM>, a voltage controller <NUM>, and a data determiner <NUM>.

The write/read control unit <NUM> may generate an address ADD and a command CMD for performing write/read and erase operations on the memory cell array <NUM>. In addition, the voltage controller <NUM> may generate a voltage control signal for controlling a voltage level used in the nonvolatile memory device <NUM>. For example, the voltage controller <NUM> may generate a voltage control signal for controlling a voltage level of a word line in order to read data from the memory cell array <NUM> or write data to the memory cell array <NUM>.

Meanwhile, the data determiner <NUM> may perform a determination operation on data read from the memory device <NUM>. For example, the number of on-cells and/or off-cells among memory cells may be determined by determining data read from the memory cells. As an operation example, when writing is performed on a plurality of memory cells, it may be determined whether a write operation is normally completed for all cells by determining a state of data of the memory cells using a predetermined read voltage.

Meanwhile, the memory device <NUM> may include the memory cell array <NUM> and a voltage generator <NUM>. As described above, the memory cell array <NUM> may include nonvolatile memory cells, and for example, the memory cell array <NUM> may include flash memory cells. In addition, flash memory cells may be implemented in various forms, for example, the memory cell array <NUM> may include three-dimensional (or vertical) NAND (VAND) memory cells.

<FIG> is a block diagram illustrating an embodiment of a memory device according to <FIG>.

As illustrated in <FIG>, the memory device <NUM> may further include a row decoder <NUM> and a control logic <NUM>, in addition to a voltage generator <NUM>.

The memory cell array <NUM> may be connected to string selection lines SSL, a plurality of word lines WL1 to WLm, which include normal word lines and dummy word lines, and common source lines CSLs, and may also be connected to a plurality of bit lines BL1 to BLn.

The voltage generator <NUM> may generate word line voltages V1 to Vi, and the word line voltages V1 to Vi may be provided to the row decoder <NUM>. A signal for a write/read/erase operation may be applied to the memory cell array <NUM> through bit lines from an input/output (I/O) circuit <NUM>.

In addition, data to be written may be provided to the memory cell array <NUM> through the I/O circuit <NUM>, and read data may be provided to the outside (e.g., the memory controller <NUM>) through the I/O circuit <NUM>. The control logic <NUM> may provide various control signals related to memory operation to the row decoder <NUM> and the voltage generator <NUM> under the control of the memory controller <NUM>.

According to the decoding operation of the row decoder <NUM>, word line voltages V1 to Vi may be provided to various lines SSLs, WL1 to WLm, and CSLs. For example, the word line voltages V1 to Vi may include string selection voltages, word line voltages, and ground selection voltages, and string selection voltages may be provided to the string selection lines SSLs, word line voltages may be provided to the word lines WLs, and ground selection voltages may be provided to the common source lines CSLs.

<FIG> is a perspective view illustrating a memory cell array <NUM> according to <FIG>.

Referring to <FIG>, the memory cell array <NUM> includes a plurality of memory blocks BLK1 to BLKz. Each memory block BLK has a three-dimensional structure (or a vertical structure). For example, each memory block BLK includes structures extending along first to third directions.

Each cell string CS is connected to a bit line BL, a string selection line SSL, word lines WLs, and a common source line CSL That is, the memory blocks BLK1 to BLKz may be connected to a plurality of bit lines BLs a plurality of string selection lines SSLs, a plurality of word lines WLs, and a plurality of common source lines CSLs, respectively.

<FIG> is a perspective view illustrating a physical structure corresponding to a memory block according to an embodiment.

Referring to <FIG>, a substrate <NUM> is provided. The substrate <NUM> may include a silicon material doped with first type impurities. For example, the substrate <NUM> may include a silicon material doped with p-type impurities. Hereinafter, it is assumed that the substrate <NUM> is formed of p-type silicon. However, the substrate <NUM> is not limited to p-type silicon.

A common source region <NUM> is provided on the substrate <NUM>. For example, the common source region <NUM> may have a second type different from that of the substrate <NUM>. For example, the common source region <NUM> may have an n-type. Hereinafter, it is assumed that the common source region <NUM> is n-type. However, the common source region <NUM> is not limited to an n-type.

A plurality of gate electrodes <NUM> and a plurality of insulating elements <NUM> may be alternately arranged on the substrate <NUM>. The plurality of gate electrodes <NUM> and the plurality of insulating patterns <NUM> may be sequentially stacked while crossing in a thickness direction of the substrate <NUM>. The plurality of gate electrodes <NUM> may include, for example, a metal material (e.g., copper, silver, etc.), and the plurality of insulating patterns <NUM> may include silicon oxide, but are not limited thereto. Each gate electrode <NUM> is connected to one of the word line WL and the string selection line SSL.

A channel structure <NUM> vertically penetrating the plurality of gate electrodes <NUM> and the plurality of insulating patterns <NUM> is provided. The channel structure <NUM> may extend through a channel hole CH defined by the plurality of gate electrodes <NUM> and the plurality of insulating patterns <NUM>. The channel hole CH may extend vertical to an upper surface of the substrate <NUM>.

The channel structure (pillar) <NUM> may include a plurality of layers. In an embodiment, the outermost layer of the channel structure <NUM> may be a gate insulating layer <NUM>. For example, the gate insulating layer <NUM> may include silicon oxide. The gate insulating layer <NUM> may be conformally deposited on the channel structure <NUM>. The gate insulating layer <NUM> may have a thickness of about <NUM> to about <NUM>.

In addition, a semiconductor layer <NUM> may be conformally deposited along an inner side surface of the gate insulating layer <NUM>. In an embodiment, the semiconductor layer <NUM> may include a silicon material. Alternatively, the semiconductor layer <NUM> may also include a material, such as Ge, IGZO, GaAs, or the like. The semiconductor layer <NUM> may not be doped with a dopant. The Fermi level of the semiconductor layer <NUM> may be changed according to a voltage applied to the gate electrode <NUM>. However, embodiments are not limited thereto. The semiconductor layer <NUM> may include a silicon material doped with a first type. The semiconductor layer <NUM> may include a silicon material doped in the same type as the substrate <NUM>, and for example, when the substrate <NUM> includes a p-type-doped silicon material, the semiconductor layer <NUM> may also include a p-type-doped silicon material. The semiconductor layer <NUM> may have a thickness of about <NUM> to about <NUM>.

A resistance change layer <NUM> may be arranged along an inner side surface of the semiconductor layer <NUM>. The resistance change layer <NUM> may be conformally deposited on the semiconductor layer <NUM>. In an embodiment, the resistance change layer <NUM> may be formed of a material whose resistance varies according to an applied voltage. The resistance change layer <NUM> may change from a high resistance state to a low resistance state or from a low resistance state to a high resistance state according to a voltage applied to the gate electrode <NUM>. The resistance change may be a phenomenon caused by oxygen vacancies of the resistance change layer <NUM>.

The resistance change layer <NUM> may be formed of a material having hysteresis properties. For example, the resistance change layer <NUM> may include a transition metal oxide or a transition metal nitride. Specifically, the resistance change layer <NUM> may include an oxide or a nitride of at least one element selected from the group consisting of zinc (Zn), zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), and praseodymium (Pr). In addition, the resistance change layer <NUM> may include GeSbTe. The resistance change layer <NUM> may have a thickness of about <NUM> to about <NUM>.

A conductive pillar <NUM> may be arranged along an inner surface of the resistance change layer <NUM>. The conductive pillar <NUM> may be in contact with the resistance change layer <NUM>. The conductive pillar <NUM> may be conformally deposited on the resistance change layer <NUM>. The conductive pillar <NUM> may be formed of a material having excellent electrical conductivity. For example, the conductive pillar <NUM> may include at least one of W, Ti, TiN, Ru, RuO<NUM>, Ta, and TaN. The conductive pillar <NUM> may be formed of the same material as the gate electrode <NUM>.

All regions of the conductive pillar <NUM> may be spatially spaced apart from all regions of the semiconductor layer <NUM> by the resistance change layer <NUM>. Since the conductive pillar <NUM> and the semiconductor layer <NUM> are electrically insulated, voltages may be independently applied to the conductive pillar <NUM> and the semiconductor layer <NUM>.

The semiconductor layer <NUM> and the resistance change layer <NUM> may be in contact with the common source region <NUM>.

A first drain <NUM> may be provided on the first semiconductor layer <NUM>, and a second drain <NUM> may be provided on the conductive pillar <NUM>. The first drain <NUM> and the second drain <NUM> may be electrically insulated from each other. For example, the first drain <NUM> and the second drain <NUM> may be spatially spaced apart from each other, and air or an insulating material may be filled between the first drain <NUM> and the second drain <NUM>.

At least one of the first drain <NUM> and the second drain <NUM> may include a silicon material doped with a second type. For example, the first drain <NUM> and the second drain <NUM> may include an n-type doped silicon material.

A first bit line <NUM> may be electrically connected to the first drain <NUM>, and a second bit line <NUM> may be electrically connected to the second drain <NUM>. The first drain <NUM> and the first bit line <NUM> may be connected through a contact plug, and the second drain <NUM> and the second bit line <NUM> may be connected through a contact plug. The first bit line <NUM> and the second bit line <NUM> may include a metallic material. In one cell string, the first and second bit lines <NUM> and <NUM> may be one bit line BL as a set.

In other words, the memory device in the form of a cell string according to an embodiment includes the conductive pillar <NUM>, the resistance change layer <NUM> surrounding a side surface of the conductive pillar <NUM>, the semiconductor layer <NUM> surrounding a side surface of the resistance change layer <NUM>, the gate insulating layer <NUM> surrounding a side surface of the semiconductor layer <NUM>, and the plurality of gate electrodes <NUM> and the plurality of insulating patterns <NUM>, which are alternately arranged along a surface of the gate insulating layer <NUM>, while surrounding a side surface of the gate insulating layer <NUM>. In addition, the memory device may include the first bit line <NUM> that is electrically connected to the conductive pillar <NUM> to provide a voltage to the conductive pillar <NUM> and the second bit line <NUM> that is electrically connected to the semiconductor layer <NUM> while being insulated from the first bit line <NUM>, to provide a voltage to the semiconductor layer <NUM>.

The gate electrode <NUM>, the gate insulating layer <NUM>, and the semiconductor layer <NUM> may be certain components of a transistor, and the resistance change layer <NUM> may be a resistor. The semiconductor layer <NUM> and the resistance change layer <NUM> of the transistor may be directly bonded to each other, and the resistance change layer <NUM> may have a high resistance state or a low resistance state. In each memory cell MC, the semiconductor layer <NUM> and the resistance change layer <NUM> of a transistor are connected in parallel, and the parallel structure is continuously arranged in a vertical direction to form a cell string CS.

The common source line CSL, and the first and second bit lines <NUM> and <NUM> may be connected to both ends of the cell string CS, respectively. In addition, voltage is applied to the first and second bit lines <NUM> and <NUM>, so that write, read, and erase operations may be performed on the plurality of memory cells MCs.

According to example embodiments of the present disclosure, instead of configuring the memory block using the phase change material, a memory block is configured using the resistance change layer <NUM>, thereby reducing and/or solving heat generation and stress (pressure) problems caused by using the phase change material. In addition, as described above, even when memory cells included in a memory block are repeatedly operated by configuring a memory block and operating a memory block, it is possible to limit and/or prevent ion movement between adjacent memory cells and leakage current and operation failure due to the ion movement. In addition, the memory block according to the disclosure may solve the scaling issue between memory cells in the next-generation VNAND, thereby dramatically increasing the density.

Meanwhile, the memory block according to the disclosure may be implemented in the form of a chip and used as a neuromorphic computing platform. In addition, the block according to the disclosure may be implemented in a chip form to be used to configure a neural network.

The memory controller <NUM> may control the memory cell MC to operate as at least one of write, read, and erase. In other words, the memory controller <NUM> may control at least one of a write operation, a read operation, and an erase operation on the memory cell MC.

<FIG> is a diagram related to movement of oxygen vacancies in a resistance change layer <NUM> during a write operation according to an embodiment.

As illustrated in <FIG>, the gate electrodes <NUM> (e.g., 531a, 531b), the insulating patterns <NUM>, the gate insulating layer <NUM>, the semiconductor layer <NUM>, the resistance change layer <NUM>, and the conductive pillar <NUM> may be included on the substrate <NUM> (see <FIG> for substrate <NUM>). The gate insulating layer <NUM>, the semiconductor layer <NUM>, the resistance change layer <NUM>, and the conductive pillar <NUM> may extend in a first direction. The gate electrodes <NUM> and the insulating patterns <NUM> may alternately extend in a second direction perpendicular to the first direction. The first direction, second direction, and third direction may correspond to Y, X, and Z in <FIG>.

Meanwhile, the gate electrode <NUM>, the gate insulating layer <NUM>, and the semiconductor layer <NUM> may be certain components of a transistor, and the resistance change layer <NUM> may correspond to a resistor.

The control logic <NUM> of <FIG> may control to apply a turn-off voltage Voff to the gate electrode 531a of a selection memory cell <NUM> and a turn-on voltage Von to the gate electrode 531b of a non-selection memory cell <NUM>. The turn-off voltage Voff is a voltage that turns off the transistor and limits and/or prevents current from flowing through the semiconductor layer 522a of the transistor included in the selection memory cell <NUM>. The turn-on voltage Von is a voltage that turns on the transistor and allows current to flow through the semiconductor layer 522b of the transistor included in the non-selection memory cell <NUM>. Thus, the semiconductor layer 522a corresponding to the gate electrode 531a of the selection memory cell <NUM> may have insulation characteristics, and the semiconductor layer 522b corresponding to the gate electrode 531b of the non-selection memory cell <NUM> may have conductor characteristics.

The turn-off voltage Voff and the turn-on voltage Von may vary depending on the types and thicknesses of materials constituting the gate electrode <NUM>, the gate insulating layer <NUM>, the semiconductor layer <NUM>, the resistance change layer <NUM>, and the conductive pillar <NUM>. For example, when the turn-off voltage Voff is a negative voltage, the turn-off voltage Voff may be -<NUM> V or greater and -<NUM> V or less. When the turn-on voltage Von is a positive voltage, the turn-on voltage Von may be <NUM> V or greater and <NUM> V or less. A turn-on voltage Von of the same value may be applied to the non-selection memory cell <NUM> or turn-on voltages Von of different values may be applied thereto.

During a write operation, the memory controller <NUM> may apply a first voltage V<NUM> to the conductive pillar <NUM> through the first bit line <NUM>, and a second voltage V<NUM> to the semiconductor layer <NUM> through the second bit line <NUM>. The memory controller <NUM> may sequentially apply the first voltage V<NUM> and the second voltage V<NUM> one after the other or simultaneously.

The first voltage V<NUM> and the second voltage V<NUM> may vary depending on the types and thicknesses of materials constituting the gate electrode <NUM>, the gate insulating layer <NUM>, the semiconductor layer <NUM>, the resistance change layer <NUM>, and the conductive pillar <NUM>. The first voltage V<NUM> may be different from the second voltage V<NUM>. Alternatively, the first voltage V<NUM> may be the second voltage V<NUM> or greater. Alternatively, the first voltage V<NUM> may be greater than the second voltage V<NUM>. A difference between the first voltage V<NUM> and the second voltage V<NUM> may be smaller than an absolute value of the second voltage V<NUM>, and the absolute value of the second voltage V<NUM> may be about <NUM> V or less.

In the resistance change layer 523a corresponding to the selection memory cell <NUM>, an electric field E<NUM> in the horizontal direction may be generated by the first voltage V<NUM>, the second voltage V<NUM>, and the turn-off voltage Voff, and an electric field E<NUM> in the vertical direction may be generated by the second voltage V<NUM>. An intensity and a direction of the vertical electric field E<NUM> may be determined by the second voltage V<NUM>, and a direction and an intensity of the horizontal electric field E<NUM> may be determined by the turn-off voltage Voff, the first voltage V<NUM>, and the second voltage V<NUM>. The turn-off voltage Voff, the first voltage V<NUM>, and the second voltage V<NUM> may be set such that the horizontal electric field E<NUM> is headed from the conductive pillar <NUM> to the semiconductor layer <NUM>. The turn-off voltage Voff may be a negative voltage, and the first voltage V<NUM> and the second voltage V<NUM> may be positive voltages. For example, when the first voltage V<NUM> is equal to or greater than the second voltage V<NUM>, the intensity of the electric field E<NUM> in the horizontal direction may be stronger.

Oxygen vacancies in the resistance change layer 523a corresponding to the selection memory cell <NUM> may be concentrated in an interface between the semiconductor layer 522a and the resistance change layer 523a by the horizontal electric field E<NUM> and the vertical electric field E<NUM>, and the density of oxygen vacancies may increase in the interface between the semiconductor layer 522a and the resistance change layer 523a. Thus, a conductive filament may be easily formed at an interface between the semiconductor layer 522a and the resistance change layer 523a. The conductive filament changes the resistance change layer 523a to a low resistance state such that a current by the second voltage V<NUM> flows through the resistance change layer 523a, and thus the selection memory cell <NUM> may perform a write operation.

As described above, the resistance change layer 523a of the selection memory cell <NUM> according to an embodiment includes an electric field E<NUM> in the horizontal direction and an electric field E<NUM> in the vertical direction, which are formed therein, to cause oxygen vacancies to be concentrated in a specific area, that is, an interface between the semiconductor layer 522a and the resistance change layer 523a, so that a write operation may be easily performed even when the second voltage V<NUM> is small. In addition, the intensity of the electric field E<NUM> in the horizontal direction may be easily adjusted by adjusting the turn-off voltage Voff, the first voltage V<NUM>, and the second voltage V<NUM>. For example, since the first voltage V<NUM> and the second voltage V<NUM> may be independently applied through the first bit line <NUM> and the second bit line <NUM>, it is easy to adjust the first voltage V<NUM> and the second voltage V<NUM> by considering the physical properties of the semiconductor layer <NUM> and the resistance change layer <NUM>.

<FIG> and <FIG> are views related to movement of oxygen pores in a resistance change layer of a semiconductor device without a conductive film in a comparative example.

The cell strings in <FIG> and <FIG> do not contain a conductive pillar. For example, the cell string may include the gate electrode <NUM>, the insulating element <NUM>, the gate insulating layer <NUM>, the semiconductor layer <NUM>, the resistance change layer <NUM>, and the insulating layer <NUM> on the substrate <NUM> (not shown in <FIG> but illustrated in <FIG>). The gate insulating layer <NUM>, the semiconductor layer <NUM>, the resistance change layer <NUM>, and the insulating layer <NUM> may extend in the first direction. The gate electrodes <NUM> and the insulating patterns <NUM> may alternately extend in a second direction perpendicular to the first direction. Only the second bit line <NUM> for applying a voltage to the semiconductor layer <NUM> may exist in the cell string.

During a write operation, the memory controller <NUM> may control to apply a turn-off voltage Voff to the gate electrode 531a of a selection memory cell <NUM> and a turn-on voltage Von to the gate electrode 531b of a non-selection memory cell <NUM>.

The second voltage V<NUM> may be applied through the second bit line <NUM> electrically connected to the selection memory cell <NUM>. The electric field E<NUM> in the vertical direction may be formed in the resistance change layer 523a corresponding to the selection memory cell <NUM>. In the resistance change layer 523a corresponding to the selection memory cell <NUM>, oxygen vacancies may only move in the vertical direction and it may be difficult for oxygen vacancies to move in the horizontal direction. As shown in <FIG>, the density of oxygen vacancies in the vertical direction is low, and thus conductive filaments may not be formed in the vertical direction.

Meanwhile, in order to form a conductive filament in the vertical direction, a voltage V<NUM> greater than the second voltage V<NUM> may be applied to the selection memory cell <NUM> through the second bit line <NUM>, as illustrated in <FIG>. The voltage V<NUM> greater than the second voltage may increase the density of oxygen vacancies inside the resistance change layer 523a corresponding to the selection memory cell <NUM> and may form a conductive filament in the vertical direction. Since the conductive filament causes the resistance change layer <NUM> to be in a low resistance state, a current may flow in the resistance change layer 523a. Therefore, the memory device performs a write operation at a voltage having a large intensity, and it is difficult for the memory device to perform a write operation at a voltage having a small intensity.

The memory device without the conductive pillar <NUM> may also perform a write operation. However, in order to form a conductive filament in the vertical direction provided in the resistance change layer 523a of the selection memory cell <NUM>, the density of oxygen vacancies should be increased. In order to increase the density of oxygen vacancies, a relatively large operating voltage may have to be applied to the second bit line <NUM>. In general, a write voltage of about <NUM> V or more may be applied to a semiconductor device without the conductive pillar <NUM>. This may cause deterioration of the semiconductor layer <NUM> and thus cause malfunction of the semiconductor device.

Meanwhile, the semiconductor device according to an embodiment includes the conductive pillar <NUM>, and a voltage may be independently applied to the conductive pillar <NUM>. A force in the horizontal direction may be generated in the selected memory cell <NUM> by an electric field between the conductive pillar <NUM> and the gate electrode 531a of the selected memory cell <NUM>. The force may cause the oxygen vacancies to be concentrated in an interface between the semiconductor layer <NUM> and the resistance change layer <NUM>. Thus, even if the absolute value of the second voltage applied to the semiconductor layer <NUM> corresponding to the selection memory cell <NUM> is small, the conductive filament may be easily formed. In addition, since the absolute value of the second voltage is small, it is possible to limit and/or prevent the semiconductor layer <NUM> from deteriorating.

<FIG> is a view related to movement of oxygen vacancies in a resistance change layer during an erasure operation according to an embodiment.

The memory controller <NUM> may control to apply a turn-off voltage Voff to the gate electrode 531a of a selection memory cell <NUM> and a turn-on voltage Von to the gate electrode 531b of a non-selection memory cell <NUM>. Thus, the semiconductor layer 522a corresponding to the gate electrode 531a of the selection memory cell <NUM> may have insulation characteristics, and the semiconductor layer 522b corresponding to the gate electrode 531b of the non-selection memory cell <NUM> may have conductor characteristics.

During an erase operation, the memory controller <NUM> may apply a third voltage V<NUM> to the conductive pillar <NUM> through the first bit line <NUM>, and a fourth voltage V<NUM> to the semiconductor layer <NUM> through the second bit line <NUM>. The memory controller <NUM> may sequentially apply the third voltage V<NUM> and the fourth voltage V<NUM> one after the other or simultaneously.

The third voltage V<NUM> and the fourth voltage V<NUM> may vary depending on the types and thicknesses of materials constituting the gate electrode <NUM>, the gate insulating layer <NUM>, the semiconductor layer <NUM>, the resistance change layer <NUM>, and the conductive pillar <NUM>. For example, the fourth voltage V<NUM> may have the same absolute value as the second voltage V<NUM> and may have opposite signs thereto. When the second voltage V<NUM> is +<NUM> V, the fourth voltage V<NUM> may be -<NUM> V. A difference between the third voltage V<NUM> and the fourth voltage V<NUM> may be smaller than an absolute value of the fourth voltage V<NUM>, and the absolute value of the fourth voltage V<NUM> may be about <NUM> V or less.

The third voltage V<NUM> may be equal to or different from the fourth voltage V<NUM>. For example, the third voltage V<NUM> may be equal to or greater than the fourth voltage V<NUM>. A difference between the third voltage V<NUM> and the fourth voltage V<NUM> may be equal to a difference between the first voltage V<NUM> and the second voltage V<NUM>.

When the third voltage V<NUM> is applied to the conductive pillar <NUM> and the fourth voltage V<NUM> is applied to the semiconductor layer <NUM>, an electric field E<NUM> in the horizontal direction may be generated by the third voltage V<NUM>, the fourth voltage V<NUM>, and the turn-off voltage Voff in the resistance change layer 523a corresponding to the selection memory cell <NUM>, and an electric field E<NUM> in the vertical direction may be generated by the fourth voltage V<NUM>.

A direction with respect to the electric field E<NUM> in the vertical direction during the erase operation may be opposite to a direction with respect to the electric field E<NUM> in the vertical direction during the write operation.

A direction with respect to the electric field E<NUM> in the horizontal direction during the erase operation may be equal to or different from a direction with respect to the electric field E<NUM> in the horizontal direction during the write operation. For example, if the turn-off voltage Voff and the fourth voltage V<NUM> are negative and the third voltage V<NUM> is greater than or equal to the fourth voltage V<NUM>, the direction to the horizontal electric field E<NUM> during the erase operation may be the same as the direction to the horizontal electric field E<NUM> during the write operation. However, the intensity of the electric field E<NUM> in the horizontal direction during the erase operation may be smaller than that of the electric field E<NUM> in the horizontal direction during the write operation. Thus, in the oxygen vacancies during the erase operation, a force according to the electric field E<NUM> in the horizontal direction may be applied to the conductive pillar <NUM> from the semiconductor layer <NUM> than in the oxygen vacancies during the write operation. Alternatively, when the third voltage V<NUM> is less than the fourth voltage V<NUM>, the direction of the horizontal electric field E<NUM> during the erase operation may be different from the direction of the horizontal electric field E<NUM> during the write operation. Thus, a force according to the electric field E<NUM> in the horizontal direction may be applied to the oxygen vacancies from the semiconductor layer <NUM> toward the conductive pillar <NUM>.

In the erase operation, the oxygen vacancies in the resistance change layer 523a may move in a direction different from the movement direction in the write operation by the horizontal electric field E<NUM> and the vertical electric field E<NUM>. Thus, as the formed conductive filament is cut off, the selection memory cell <NUM> may perform an erase operation.

In the erase operation, the horizontal electric field E<NUM> and the vertical electric field E<NUM> are formed in the resistance change layer 523a of the selection memory cell <NUM>, so that the conductive filament may be easily cut off by varying the moving direction of the oxygen vacancies. Thus, the magnitude of the fourth voltage V<NUM> applied to the semiconductor layer <NUM> may be reduced. In addition, since the third voltage V<NUM> and the fourth voltage V<NUM> are independently applied to the conductive pillar <NUM> and the semiconductor layer <NUM>, it is easy to adjust the third voltage V<NUM> and the fourth voltage V<NUM> in consideration of the physical properties of the memory device.

<FIG> is a view illustrating a memory device including a first insulating layer <NUM> according to an embodiment. When comparing <FIG> and <FIG> with each other, the memory device of <FIG> may have a channel structure 520a that further includes a first insulating layer <NUM> between the resistance change layer <NUM> and the conductive pillar <NUM>. The first insulating layer <NUM> may surround a side surface and a lower surface of the conductive pillar <NUM>.

The first insulating layer <NUM> may be formed of an insulating material. For example, the first insulating layer <NUM> may include silicon oxide. After the resistance change layer <NUM> is formed, the first insulating layer <NUM> may be conformally deposited inside the resistance change layer <NUM>. The first insulating layer <NUM> may limit and/or prevent oxygen vacancies from moving in the resistance change layer <NUM> due to a potential difference between the conductive pillar <NUM> and the semiconductor layer <NUM>. In addition, the first insulating layer <NUM> may limit and/or prevent the resistance change layer <NUM> from being permanently broken down by the potential difference between the conductive pillar <NUM> and the gate electrode <NUM>.

<FIG> is a view illustrating a memory device including a second insulating layer <NUM> according to an embodiment. When comparing <FIG> and <FIG> with each other, the memory device of <FIG> may have a channel structure 520b that further includes a second insulating layer <NUM> embedded in the conductive pillar <NUM>. The second insulating layer <NUM> may be arranged on an inner wall surface of the conductive pillar <NUM>. The bottom surface of the second insulating layer <NUM> may be in contact with the resistance change layer <NUM>. After the conductive pillar <NUM> is formed, the second insulating layer <NUM> may be conformally deposited inside the conductive pillar <NUM>.

The second insulating layer <NUM> may be formed of an insulating material. For example, the second insulating layer <NUM> may include silicon oxide. The second insulating layer <NUM> may reduce the contact area between the conductive pillar <NUM> and the resistance change layer <NUM>, especially the regions arranged on the common source region <NUM> among the resistance change layer <NUM>. The second insulating layer <NUM> may limit and/or prevent the oxygen vacancies from moving to the resistance change layer <NUM> due to a potential difference between the conductive pillar <NUM> and the common source region <NUM>, and may limit and/or prevent the resistance change layer <NUM> from being permanently broken down due to a potential difference between the conductive pillar <NUM> and the common source region <NUM>.

<FIG> is a view illustrating a semiconductor device including first and second insulating layers according to an embodiment. When comparing <FIG> and <FIG> with each other, the semiconductor device of <FIG> may have a channel structure 520c that further includes a first insulating layer <NUM> and a second insulating layer <NUM> embedded in the conductive pillar <NUM> between the resistance change layer <NUM> and the conductive pillar <NUM>. The characteristics of the first insulating layer <NUM> and the second insulating layer <NUM> have been described above, and thus a detailed description thereof will be omitted. The semiconductor device in <FIG> may be a memory device.

<FIG> and <FIG> are reference views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment.

As illustrated in <FIG>, first insulating material layers <NUM> and second insulating material layers <NUM> may be alternately stacked on the substrate <NUM>. The first insulating material layers <NUM> and the second insulating material layers <NUM> may be alternately stacked in a direction perpendicular to the surface of the substrate <NUM>. The first and second insulating material layers <NUM> and <NUM> may be formed of different materials. The first and second insulating material layers <NUM> and <NUM> may include, for example, silicon oxide, silicon nitride, etc., but are not limited thereto.

As illustrated in <FIG>, a hole <NUM> is formed to penetrate the first and second insulating material layers <NUM> and <NUM>. Here, the hole <NUM> may be formed to extend in a direction perpendicular to the surface of the substrate <NUM>. The hole <NUM> may be formed to have a circular cross section. The hole <NUM> may be formed by anisotropically etching the first insulating material layer <NUM> and the second insulating material layer <NUM>. The surface of the substrate <NUM> may be exposed by the hole <NUM>.

As illustrated in <FIG>, the gate insulating layer <NUM>, the semiconductor layer <NUM>, the resistance change layer <NUM>, and the conductive pillar <NUM> may be sequentially formed on the inner wall of the hole <NUM>. The gate insulating layer <NUM> may be formed to extend in a direction perpendicular to the surface of the substrate <NUM>. The gate insulating layer <NUM> may be formed on an inner wall of the hole <NUM> to be in contact with the first and second insulating material layers <NUM> and <NUM>. The semiconductor layer <NUM> may be formed to be in contact with an inner side surface of the gate insulating layer <NUM>. The resistance change layer <NUM> may be formed on an inner side surface of the semiconductor layer <NUM> and an upper surface of the substrate <NUM> exposed by the hole <NUM>. A conductive pillar <NUM> may be further formed in the resistance change layer <NUM>. The conductive pillar <NUM> is formed in <FIG>, but the embodiments are not limited thereto. The conductive pillar <NUM> may be formed together when a gate electrode <NUM> to be described later is formed.

As shown in <FIG>, an opening <NUM> penetrating the first and second insulating material layers <NUM> and <NUM> may be formed, and the second insulating material layers <NUM> may be removed to expose the gate insulating layer <NUM>. The second insulating material layers <NUM> may be etched by a wet etching process.

As illustrated in <FIG>, gate electrodes <NUM> may be formed in regions from which the second insulating material layers <NUM> are removed. When the gate electrodes <NUM> are formed, the conductive pillar <NUM> may also be formed. The remaining first insulating material layers <NUM> may be insulating patterns <NUM>. When the gate electrodes <NUM> are formed, the conductive pillar <NUM> may also be formed together.

As illustrated in <FIG>, a common source region <NUM> may be formed in the substrate <NUM> exposed by the opening <NUM>. The common source region <NUM> may be formed by doping n-type impurities, such as phosphorus (P).

As shown in <FIG> and <FIG>, a first drain <NUM> may be formed on the conductive pillar <NUM>, a second drain <NUM> may be formed on the semiconductor layer <NUM>, and a first bit line <NUM> and a second bit line <NUM> respectively contacting the first drain <NUM> and the second drain <NUM> may be formed.

The memory device according to an embodiment includes a conductive pillar <NUM> capable of forming an electric field in a horizontal direction in the resistance change layer <NUM> of the selection memory cell <NUM>, thereby reducing the absolute value of the voltage applied to the semiconductor layer <NUM>. Since a voltage is independently applied to the conductive pillar <NUM> and the semiconductor layer <NUM>, the applied voltage may be easily adjusted according to the physical properties of the memory device.

While <FIG> illustrate the channel structure <NUM> from <FIG>, example embodiments are not limited thereto. The channel structures 520a, 520b, and 520c from <FIG>, <FIG>, and <FIG> alternatively may be formed instead of the channel structure <NUM> illustrated in <FIG> to manufacture nonvolatile memory devices including any one of the channel structures 520a, 520b, and 520c illustrated in <FIG>, <FIG>, and <FIG>.

<FIG> is a block diagram schematically illustrating an electronic device <NUM> including a nonvolatile memory device according to an embodiment.

Referring to <FIG>, an electronic device <NUM> according to an embodiment may be one of a PDA, a laptop computer, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a wired or wireless electronic device, and a composite electronic device including at least two of them. The electronic device <NUM> may include a controller <NUM> coupled to each other through a bus <NUM>, an input/output device <NUM>, such as a keypad, a keyboard, and a display, a memory <NUM>, and a wireless interface <NUM>.

The controller <NUM> may include, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. The memory <NUM> may be used, for example, to store an instruction to be executed by the controller <NUM>.

The memory <NUM> may be used to store user data. The memory <NUM> may include at least one of nonvolatile memory devices according to an embodiment.

The electronic device <NUM> may use a wireless interface <NUM> to transmit data to a wireless communication network communicating with an RF signal or to receive data from the network. For example, the wireless interface <NUM> may include an antenna, a wireless transceiver, or the like. The electronic device <NUM> may be used in communication interface protocols, such as third-generation communication systems, such as CDMA, GSM, NADC, E-TDMA, WCDAM, CDMA2000, fidelity (Wi-Fi), Bluetooth, a wireless universal serial bus (USB), Zigbee, near-field communication (NFC), radio-frequency identification (RFID), a 4th generation (<NUM>) communication system, or long term evolution (LTE), or a <NUM> (5th Generation) communication system.

<FIG> is a block diagram schematically illustrating a memory system i1100 including a nonvolatile memory device according to an embodiment.

Referring to <FIG>, nonvolatile memory devices according to an embodiment may be used to implement a memory system. The memory system <NUM> may include a memory <NUM> and a memory controller <NUM> for storing a large capacity of data. The memory controller <NUM> controls the memory <NUM> to read data stored from the memory <NUM> or write data in the memory <NUM> in response to a read/write request from the host <NUM>. The memory controller <NUM> may configure an address mapping table for mapping an address provided from a host <NUM>, for example, a mobile device or a computer system, to a physical address of the memory <NUM>. The memory <NUM> may include at least one of semiconductor memory devices according to an embodiment.

The nonvolatile memory device according to the embodiment described so far may be implemented in the form of a chip and used as a neuromorphic computing platform. For example, <FIG> schematically illustrates a neuromorphic device including a memory device according to an embodiment. Referring to <FIG>, the neuromorphic device <NUM> may include a processing circuit <NUM> and/or a memory <NUM>. The memory <NUM> of the neuromorphic device <NUM> may include a memory system according to an embodiment.

The processing circuit <NUM> may be configured to control functions for driving the neuromorphic device <NUM>. For example, the processing circuit <NUM> may control the neuromorphic device <NUM> by executing a program stored in the memory <NUM> of the neuromorphic device <NUM>.

The processing circuit <NUM> may include hardware such as a logic circuit, a combination of hardware and software such as a processor that executes the software, or a combination thereof. For example, the processor may include a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) within a neuromorphic device <NUM>, an arithmetic logic unit (ALU), a digital processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific Integrated circuit (ASIC), or the like.

In addition, the processing circuit <NUM> may read and write various data in the external device <NUM> and execute the neuromorphic device <NUM> using the data. The external device <NUM> may include a sensor array including an external memory and/or an image sensor (e.g., a CMOS image sensor circuit).

The neuromorphic device <NUM> shown in <FIG> may be applied to a machine learning system. The machine learning system may utilize various artificial neural network organizations and processing models including, for example, a recurrent neural network (RNN), a stacked neural network (SNN), a state-space dynamic neural network (SSDNN), a deep belief network (DBN), generative adversarial networks (GANs), and/or restricted Boltzmann machines (RBM), or the like, which selectively include a convolutional neural network (CNN), a deconvolutional neural network, a long short-term memory (LSTM), and/or a gated recurrent unit (GRU).

Such machine learning systems may include, for example, linear regression and/or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensional reduction such as principal component analysis, and other types of machine learning models such as expert systems, and/or ensemble techniques such as random forest, and a combination thereof. These machine learning models may be used to provide various services, such as image classification services, biometric information or biometric data based authentication services, advanced driver assistance systems (ADAS), voice assistant services, and automatic speech recognition (ASR) services, and may be mounted and executed on other electronic devices.

The semiconductor device according to an embodiment includes the conductive pillar capable of forming the electric field in the horizontal direction in the resistance change layer of the selection memory cell, thereby reducing the absolute value of the voltage applied to the semiconductor layer.

Since a voltage is independently applied to the conductive pillar and the semiconductor layer, a voltage range may be easily adjusted according to physical properties of the semiconductor device.

One or more of the elements disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU) , an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc..

Claim 1:
A nonvolatile memory device comprising:
a conductive pillar (<NUM>);
a resistance change layer (<NUM>) surrounding a side surface of the conductive pillar;
a semiconductor layer (<NUM>) surrounding a side surface of the resistance change layer;
a common source region (<NUM>) configured to be in contact with the semiconductor layer and the resistance change layer;
a gate insulating layer (<NUM>) surrounding a side surface of the semiconductor layer;
a plurality of insulating patterns (<NUM>) and a plurality of gate electrodes (<NUM>), the plurality of insulating patterns and the plurality of gate electrodes being alternately arranged along a surface of the gate insulating layer, and the plurality of insulating patterns and the plurality of gate electrodes surrounding a side surface of the gate insulating layer;
a first bit line (<NUM>) electrically connected to the conductive pillar, the first bit line being configured to provide a first voltage (V<NUM>) to the conductive pillar; and
a second bit line (<NUM>) electrically insulated from the first bit line, the second bit line being electrically connected to the semiconductor layer, and the second bit line being configured to provide a second voltage (V<NUM>) to the semiconductor layer.