Patent Description:
A semiconductor package is provided to implement an integrated circuit chip included in electronic products. A semiconductor package is typically configured to be mounted on a printed circuit board, and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the development of electronic industry, various studies have been conducted to improve reliability and durability of semiconductor packages.

<CIT> describes an electronic component-embedded board that includes: a core substrate; a cavity which penetrates the core substrate; a wiring layer formed on one face of the core substrate; a component mounting pattern formed of the same material as the wiring layer and laid across the cavity to partition the cavity into through holes in plan view; an electronic component mounted on the component mounting pattern and arranged inside the cavity; a first insulating layer formed on the one face of the core substrate to cover one face of the electronic component; and a second insulating layer formed on the other face of the core substrate to cover the other face of the electronic component. The cavity is filled with the first insulating layer and the second insulating layer.

<CIT> describes an assembly structure for an embedded passive device, including at least one passive device embedded in a through hole of a core layer in a circuit substrate. The embedded passive device comprises plural electrodes, which electrically connect through the top side and the bottom side of the core layer.

<CIT> describes how a through hole in the thickness direction of a board is bored in a core material to be used as a nucleus in the manufacture of a multilayer board. A passive element such as the bypass capacitor or the like is mounted inside the through hole in such a way that both terminals of it have a direction which faces the opening part of the through hole.

<CIT> describes a substrate assembly having at least one embedded component in a via of a substrate core and including a first adhesive layer coupled to the substrate core, and a second adhesive layer on at least portions of a top surface of the substrate core and above portions of the embedded component.

<CIT> describes a method to form a stacked CMOS image sensor that includes forming a signal processing layer including a plurality of discrete signal processing circuits, an image sensor layer including a plurality of discrete image sensing units, and an intermediate capacitor layer including a dielectric layer and a plurality of capacitors.

<CIT> describes a three-dimensional module with multiple firing modes. The three-dimensional module comprises multiple device layers, wherein each device layer comprises multiple passive elements and each passive element contains at least one layer of dielectric material with a high dielectric constant.

<CIT> describes a method for forming a redistribution structure in a semiconductor package. The method includes encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.

Example embodiments in the disclosure provide a semiconductor package in a reduced size with increased reliability, and a method of manufacturing the same. According to an aspect of the invention there is provided a semiconductor package according to claim <NUM>.

According to embodiments, there is provided a semiconductor package that may include: a redistribution substrate; at least one passive device in the redistribution substrate the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal.

According to embodiments, there is provided a semiconductor package that may include: a redistribution substrate; a capacitor in the redistribution substrate, the capacitor including a base layer, a first terminal, and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the capacitor, wherein the redistribution substrate includes: a dielectric layer in contact with lateral surfaces and a bottom surface of the base layer; a redistribution metal pattern in the dielectric layer and laterally spaced apart from the capacitor; and a redistribution seed pattern that covers a top surface of the redistribution metal pattern, wherein a top surface of the redistribution seed pattern is at a level substantially the same as a level of a top surface of the base layer.

According to embodiments, there is provided a semiconductor package that may include: a redistribution substrate; a solder pattern on a bottom surface of the redistribution substrate; a first semiconductor chip on a top surface of the redistribution substrate; a molding layer on the top surface of the redistribution substrate, the molding layer covering the first semiconductor chip; a first capacitor in the redistribution substrate, the first capacitor vertically overlapping the first semiconductor chip; and a second capacitor disposed side by side with the first capacitor in the redistribution substrate, wherein the first capacitor comprises a first base layer a first terminal and a second terminal, wherein the redistribution substrate includes: a dielectric layer in contact with sidewalls of the first base layer and sidewalls of the second capacitor; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the lower conductive pattern, and directly connected to the first terminal; an upper conductive pattern on the second terminal; an upper seed pattern provided between the second terminal and the upper conductive pattern and directly connected to the second terminal; a first redistribution pattern in the dielectric layer and laterally spaced apart from the first capacitor and the second capacitor; and a second redistribution pattern between the first redistribution pattern and the solder pattern, wherein a thickness of the second capacitor is substantially the same as a thickness of the first capacitor, and wherein a width of the second capacitor is different from a width of the first capacitor.

The embodiments described herein are all example embodiments, and thus, the inventive concept is not limited thereto and may be realized in various other forms.

It will be understood that when an element or layer is referred to as being "over," "above," "on," "below," "under," "beneath," "connected to" or "coupled to" another element or layer, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly over," "directly above," "directly on," "directly below," "directly under," "directly beneath," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present.

Spatially relative terms, such as "over," "above," "on," "upper," "below," "under," "beneath," "lower," and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures.

In this description, like reference numerals may indicate like components. The following will now describe semiconductor packages and their manufacturing methods according to an embodiment.

<FIG> illustrates a plan view of a semiconductor package according to an embodiment. <FIG> illustrates a cross-sectional view taken along line I-II of <FIG>, according to an embodiment. <FIG> illustrates an enlarged view showing section A of <FIG>, according to an embodiment.

Referring to <FIG>, a semiconductor package <NUM> may include a package substrate <NUM>, a redistribution substrate <NUM>, solder patterns <NUM>, a first semiconductor chip <NUM>, a chip stack <NUM>, first bonding bumps <NUM>, second bonding bumps <NUM>, and a molding layer <NUM>.

The package substrate <NUM> may include a printed circuit board. The package substrate <NUM> may include metal lines <NUM> and metal pads <NUM>. The metal lines <NUM> may be provided in the package substrate <NUM>. The phrase "connected to the package substrate <NUM>" may mean "connected to the metal lines <NUM>. " The metal pads <NUM> may be provided on a top surface of the package substrate <NUM> and electrically connected to the metal lines <NUM>. External coupling terminals <NUM> may be provided on a bottom surface of the package substrate <NUM> and connected to corresponding metal lines <NUM>. External electrical signals may be transmitted through the external coupling terminals <NUM> to the metal lines <NUM>. Solder balls may be used as the external coupling terminals <NUM>. The external coupling terminals <NUM> may include metal, such as a solder material. In this description, the solder material may include tin, bismuth, lead, silver, or any alloy thereof.

The redistribution substrate <NUM> may be disposed on the package substrate <NUM>. The redistribution substrate <NUM> may serve as an interposer substrate. For example, the redistribution substrate <NUM> may be disposed between the first semiconductor chip <NUM> and the package substrate <NUM> and between the chip stack <NUM> and the package substrate <NUM>.

The redistribution substrate <NUM> may include a dielectric layer, a first redistribution pattern <NUM>, a second redistribution pattern <NUM>, a third redistribution pattern <NUM>, a fourth redistribution pattern <NUM>, a lower seed pattern <NUM>, a lower conductive pattern <NUM>, an upper seed pattern <NUM>, and an upper conductive pattern <NUM>. Here, since a combination of the lower seed pattern <NUM> and the lower conductive pattern <NUM> and a combination of the upper seed pattern <NUM> and an upper conductive pattern <NUM> are included in the redistribution substrate, each of these combinations may also be referred to as another redistribution pattern. The dielectric layer may include a first dielectric layer <NUM>, a second dielectric layer <NUM>, a third dielectric layer <NUM>, and a fourth dielectric layer <NUM>. Each of the first dielectric layer <NUM>, the second dielectric layer <NUM>, the third dielectric layer <NUM>, and the fourth dielectric layer <NUM> may include an organic material, such a photosensitive polymer. In this description, the photosensitive polymer may include, for example, at least one selected from photosensitive polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers. The third dielectric layer <NUM> may be a lowermost dielectric layer. The second dielectric layer <NUM>, the first dielectric layer <NUM>, and the fourth dielectric layer <NUM> may be stacked on a top surface of the third dielectric layer <NUM>. The second dielectric layer <NUM>, the first dielectric layer <NUM>, and the fourth dielectric layer <NUM> may be sequentially stacked on a top surface of the third dielectric layer <NUM>. As an example, the first dielectric layer <NUM>, the second dielectric layer <NUM>, the third dielectric layer <NUM>, and the fourth dielectric layer <NUM> may include the same material as each other. An indistinct interface may be provided between two adjacent dielectric layers among the first dielectric layer <NUM>, the second dielectric layer <NUM>, the third dielectric layer <NUM>, and the fourth dielectric layer <NUM>. The number of the dielectric layers <NUM>, <NUM>, <NUM>, and <NUM> may be variously changed.

The first redistribution pattern <NUM> may be disposed in the first dielectric layer <NUM>. The first redistribution pattern <NUM> may include a first seed pattern <NUM> and a first metal pattern <NUM>. The first seed pattern <NUM> may be disposed in the first dielectric layer <NUM>. The first seed pattern <NUM> may be a redistribution seed pattern. The first seed pattern <NUM> may include a seed metallic material, such as copper, titanium, or any alloy thereof. The first seed pattern <NUM> may be a barrier pattern. For example, the first seed pattern <NUM> may prevent diffusion of materials included in the first metal pattern <NUM>. The first metal pattern <NUM> may be disposed on a bottom surface of the first seed pattern <NUM>. The first metal pattern <NUM> may be a redistribution metal pattern. The first metal pattern <NUM> may include, for example, copper or an alloy of copper. The first metal pattern <NUM> may include a material different from that forming the first seed pattern <NUM>.

The second redistribution pattern <NUM> may be connected to a bottom surface of the first metal pattern <NUM>. The first dielectric layer <NUM> may have the second redistribution pattern <NUM> disposed on a bottom surface thereof.

The second redistribution pattern <NUM> may include a second seed pattern <NUM> and a second metal pattern <NUM>. The second metal pattern <NUM> may include a line part and a via part. In this description, a via part of a certain conductive component may be a portion for vertical connection (e.g. a portion that extends substantially vertically). A line part of a certain conductive component may be a portion of horizontal connection (e.g. a portion that extends substantially horizontally). When a certain component includes a via part and a line part, the line part may have a width greater than that of the via part. The via part of the second metal pattern <NUM> may be disposed between the first redistribution pattern <NUM> and the line part of the second metal pattern <NUM>. The line part of the second metal pattern <NUM> may have a top surface at a level lower than that of a top surface of the via part included in the second metal pattern <NUM>. The via part of the second metal pattern <NUM> may extend vertically from the level of the top surface of the line part of the second metal pattern <NUM>. The via part and the line part of the second metal pattern <NUM> may include the same material, and may be connected to each other with no boundary therebetween.

The second seed pattern <NUM> may be disposed on a top surface of the second metal pattern <NUM>. For example, the second seed pattern <NUM> may be disposed on the top surface and a sidewall of the via part included in the second metal pattern <NUM>, and may also be disposed on the top surface of the line part included in the second metal pattern <NUM>. The second seed pattern <NUM> may be interposed between the first redistribution pattern <NUM> and the second metal pattern <NUM> and between the first dielectric layer <NUM> and the second metal pattern <NUM>. The second seed pattern <NUM> may not be disposed on a bottom surface of the second metal pattern <NUM>. The second seed pattern <NUM> may include a material different from that forming the second metal pattern <NUM>. The second seed pattern <NUM> may include a seed metallic material the same as or similar to that discussed in the example of the first seed pattern <NUM>.

The second dielectric layer <NUM> may be disposed on the bottom surface of the first dielectric layer <NUM>, and may cover a lower portion of the second redistribution pattern <NUM>. The second dielectric layer <NUM> may have an undulation at a bottom surface thereof, not being limited thereto.

The third redistribution pattern <NUM> may be disposed on a bottom surface of the second redistribution pattern <NUM> and connected to the second redistribution pattern <NUM>. The second dielectric layer <NUM> may have the third redistribution pattern <NUM> provided on the bottom surface thereof.

The third redistribution pattern <NUM> may include a third seed pattern <NUM> and a third metal pattern <NUM>. The third metal pattern <NUM> may include a line part and a via part. The via part of the third metal pattern <NUM> may be disposed between the second redistribution pattern <NUM> and the line part of the third metal pattern <NUM>. The third seed pattern <NUM> may be disposed on a top surface of the third metal pattern <NUM>. The third seed pattern <NUM> may be interposed between the second redistribution pattern <NUM> and the third metal pattern <NUM> and between the second dielectric layer <NUM> and the third metal pattern <NUM>. The third seed pattern <NUM> may include a material different from that forming the third metal pattern <NUM>. The third seed pattern <NUM> may include a seed metallic material the same as or similar to that discussed in the example of the first seed pattern <NUM>.

The third dielectric layer <NUM> may be disposed on the bottom surface of the second dielectric layer <NUM>, and may cover a lower portion of the third redistribution pattern <NUM>. The third dielectric layer <NUM> may have a bottom surface that is substantially flat, but the embodiment is not limited thereto.

The fourth redistribution pattern <NUM> may be disposed on a bottom surface of the third redistribution pattern <NUM> and connected to the third metal pattern <NUM>. The third dielectric layer <NUM> may have the fourth redistribution pattern <NUM> disposed on the bottom surface thereof.

The fourth redistribution pattern <NUM> may include a fourth seed pattern <NUM> and a fourth metal pattern <NUM>. The fourth metal pattern <NUM> may include a line part and a via part. The via part of the fourth metal pattern <NUM> may be disposed between the third redistribution pattern <NUM> and the line part of the fourth metal pattern <NUM>. The fourth seed pattern <NUM> may be interposed between the third redistribution pattern <NUM> and the fourth metal pattern <NUM> and between the third dielectric layer <NUM> and the fourth metal pattern <NUM>. The fourth seed pattern <NUM> may be disposed on a top surface of the fourth metal pattern <NUM>. The fourth seed pattern <NUM> may not be disposed on a bottom surface of the fourth metal pattern <NUM>. The fourth redistribution pattern <NUM> may correspond to a lowermost redistribution pattern.

The fourth redistribution pattern <NUM> may be provided in plural, and the plurality of fourth redistribution patterns <NUM> may be disposed side by side with each other. In this description, the phrase "certain components are disposed side by side" may mean "any two neighboring components among the certain components are spaced apart from each other, without the same or similar component therebetween, in a first direction D1 or a second direction D2. " The first direction D1 may be parallel to a top surface of the first semiconductor chip <NUM>. The second direction D2 may also be parallel to the top surface of the first semiconductor chip <NUM> while intersecting the first direction D1. The second direction D2 may be substantially perpendicular to the first direction D1.

Although not shown in the drawings, the redistribution substrate <NUM> may further include a passivation layer. The passivation layer may be disposed on the bottom surface of the third dielectric layer <NUM>, and may also be disposed on lower sidewalls of the fourth redistribution patterns <NUM>. The passivation layer may include a dielectric material.

The solder patterns <NUM> may be disposed on a bottom surface of the redistribution substrate <NUM>. The solder patterns <NUM> may be correspondingly disposed on bottom surfaces of the fourth redistribution patterns <NUM>. The solder patterns <NUM> may be connected to corresponding fourth metal patterns <NUM> and attached to the bottom surfaces of the fourth metal patterns <NUM>. The fourth redistribution patterns <NUM> may serve as solder pads. The solder patterns <NUM> may act as terminals. The solder patterns <NUM> may have a solder-ball shape and include a solder material.

The first dielectric layer <NUM> may have, on its top surface, the fourth dielectric layer <NUM> that is disposed on a top surface of the first redistribution pattern <NUM> and the top surface of the first dielectric layer <NUM>. An upper bonding pattern may be disposed on the fourth dielectric layer <NUM>. The upper bonding pattern may include an upper seed pattern <NUM> and an upper conductive pattern <NUM>. The upper conductive pattern <NUM> may be disposed in and on the fourth dielectric layer <NUM>. The upper conductive pattern <NUM> may include metal, such as copper. The upper conductive pattern <NUM> may have a lower portion that serves as a via part. The lower portion of the upper conductive pattern <NUM> may be disposed in the fourth dielectric layer <NUM>. The upper conductive pattern <NUM> may have an upper portion that extends onto a top surface of the fourth dielectric layer <NUM>. The upper portion and the lower portion of the upper conductive pattern <NUM> may be connected to each other with no boundary therebetween. The upper portion of the upper conductive pattern <NUM> may serve as a pad part or a line part.

The upper seed pattern <NUM> may be disposed on a bottom surface of the upper conductive pattern <NUM>, and may be disposed between the upper conductive pattern <NUM> and the fourth dielectric layer <NUM>. The bottom surface of the upper conductive pattern <NUM> may be located at a level substantially the same as that of a bottom surface of the fourth dielectric layer <NUM>. The upper seed pattern <NUM> may include a different material from that forming the upper conductive pattern <NUM>. For example, the upper seed pattern <NUM> may include copper, titanium, or any alloy thereof.

A passive device may be disposed in the redistribution substrate <NUM>. The passive device may be a capacitor <NUM>. In a plan view as shown in <FIG>, the capacitor <NUM> may overlap the first semiconductor chip <NUM>. The capacitor <NUM> may be provided in plural in the redistribution substrate <NUM>. The plurality of capacitors <NUM> may be laterally spaced apart from each other. Each of the plurality of capacitors <NUM> may include a base layer <NUM>, a first terminal <NUM>, a second terminal <NUM>, and a stack structure <NUM>. The base layer <NUM> may include a dielectric material. For example, the base layer <NUM> may include a silicon-based dielectric material, such as one or more of tetraethyl orthosilicate, silicon oxide, silicon carbide, and silicon nitride. As illustrated in <FIG>, the first terminal <NUM> may be exposed on a bottom surface of the base layer <NUM>. The bottom surface of the base layer <NUM> may correspond to a bottom surface of a corresponding capacitor <NUM>. The first terminal <NUM> may include a conductive material, such as metal and/or doped polysilicon. The second terminal <NUM> may be disposed and exposed on a top surface 350a of the base layer <NUM>. The second terminal <NUM> may have a top surface at a level substantially the same as that of the top surface 350a of the base layer <NUM>, but the embodiment is not limited thereto. The second terminal <NUM> may include a conductive material, such as metal and/or doped polysilicon.

The stack structure <NUM> may be disposed in the base layer <NUM>. The stack structure <NUM> may have sidewalls surrounded by the base layer <NUM>. The base layer <NUM> may be interposed between the stack structure <NUM> and the redistribution substrate <NUM>. The base layer <NUM> may separate the stack structure <NUM> from the first dielectric layer <NUM>. The stack structure <NUM> may include a plurality of conductive layers <NUM> and dielectric films <NUM> between the conductive layers <NUM>. For example, the base layer <NUM> may have a trench, and the stack structure <NUM> may be disposed in the trench of the base layer <NUM>. The stack structure <NUM> may serve as a capacitor unit. One of the capacitors <NUM> may include a plurality of stack structures <NUM> or a single stack structure <NUM>. The base layer <NUM> may act as a dummy pattern or a buffer pattern.

The plurality of capacitors <NUM> may have their top surfaces at substantially the same level. The capacitors <NUM> may have their thicknesses that are substantially the same as each other. The thickness of each of the capacitors <NUM> may correspond to an interval between the top surface 350a and the bottom surface of the base layer <NUM>. For example, the capacitors <NUM> may include a first capacitor <NUM> and a second capacitor <NUM> that are spaced apart from each other. The second capacitor <NUM> may have a thickness T2 substantially the same as a thickness T1 of the first capacitor <NUM>. The thicknesses of the capacitors <NUM> may each be about <NUM>% to about <NUM>% of a thickness of the redistribution substrate <NUM>. For example, each of the thickness T1 of the first capacitor <NUM> and the thickness T2 of the second capacitor <NUM> may be about <NUM>% to about <NUM>% of the thickness of the redistribution substrate <NUM>. The thickness of the redistribution substrate <NUM> may correspond to an interval between a top surface of the upper conductive pattern <NUM> and the bottom surface of the fourth redistribution pattern <NUM>.

The capacitors <NUM> may have different widths to each other. The widths of the capacitors <NUM> may be measured in the first direction D1. For example, the second capacitor <NUM> may have a width W2 different from a width W1 of the first capacitor <NUM>. The capacitors <NUM> may have different lengths from each other as shown in <FIG>. The lengths of the capacitors <NUM> may be measured in the second direction D2. The second capacitor <NUM> may have a length different from that of the first capacitor <NUM>. The second capacitor <NUM> may have a planar area different from that of the first capacitor <NUM>. For brevity of description, the following will discuss a single capacitor <NUM>.

The capacitor <NUM> may be directly in contact with the redistribution substrate <NUM>. For example, neither an under-fill layer nor an adhesive layer may be provided between the capacitor <NUM> and the redistribution substrate <NUM>. According to embodiments, the first dielectric layer <NUM> may be in contact with a first sidewall, a second sidewall, and a bottom surface of the capacitor <NUM>. The second sidewall of the capacitor <NUM> may be opposite to the first sidewall of the capacitor <NUM>. The first side wall and the second sidewall of the capacitor <NUM> may correspond to outer sidewalls of the base layer <NUM>. The bottom surface of the capacitor <NUM> may connect an edge of the first sidewall to an edge of the second sidewall. Therefore, the capacitor <NUM> may be satisfactorily encapsulated in the first dielectric layer <NUM>. The fourth dielectric layer <NUM> may cover or may be disposed on the top surface of the capacitor <NUM>. As shown in <FIG>, the fourth dielectric layer <NUM> may be in contact with the top surface of the capacitor <NUM>. The top surface of the capacitor <NUM> may be opposite to the bottom surface of the capacitor <NUM>. The top surface of the capacitor <NUM> may include the top surface 350a of the base layer <NUM>. The top surface of the capacitor <NUM> may further include a top surface of the second terminal <NUM>.

The lower conductive pattern <NUM> may be disposed on a bottom surface of the first terminal <NUM>. The lower conductive pattern <NUM> may include metal, such as copper. The lower seed pattern <NUM> may be interposed between and directly connected to the lower conductive pattern <NUM> and the first terminal <NUM>. Therefore, the redistribution substrate <NUM> may become small in size and may exhibit improved reliability. The lower seed pattern <NUM> may include a different material from that of the lower conductive pattern <NUM>. For example, the lower seed pattern <NUM> may include a conductive material, such as copper, titanium, or any alloy thereof. The lower seed pattern <NUM> may include a different material from that of the first terminal <NUM>, but the embodiment is not limited thereto. The lower seed pattern <NUM> may include no solder material. The lower seed pattern <NUM> may extend between the first dielectric layer <NUM> and the lower conductive pattern <NUM>.

The third redistribution pattern <NUM> may be provided in plural. One of the third redistribution patterns <NUM> may be disposed on a bottom surface of the lower conductive pattern <NUM> and electrically connected to the lower conductive pattern <NUM>. Another of the third redistribution patterns <NUM> may be disposed on the bottom surface of the second redistribution pattern <NUM>, as discussed above, and may be electrically connected to the second redistribution pattern <NUM>.

An external electric signal may be transmitted to the first terminal <NUM> through the solder pattern <NUM>, the one of the third redistribution patterns <NUM>, and the lower conductive pattern <NUM>. The electric signal may be a voltage signal or a data signal. The first terminal <NUM> may be an input terminal, but the embodiment is not limited thereto.

Differently from that shown, a plurality of lower conductive patterns <NUM> and a plurality of lower seed patterns <NUM> may be disposed on the bottom surface of the first terminal <NUM>, thereby connected to the first terminal <NUM>. The first terminal <NUM> may be electrically connected through a plurality of lower seed patterns <NUM> to a plurality of solder patterns <NUM>. The capacitor <NUM> may receive external electric signals from a plurality of solder patterns <NUM>.

As shown in <FIG>, the upper conductive pattern <NUM> may include a first upper conductive pattern 153A and a second upper conductive pattern 153B. The upper seed pattern <NUM> may include a first upper seed pattern 151A and a second upper seed pattern 151B.

The first upper conductive pattern 153A may be disposed on the top surface of the second terminal <NUM>. The first upper seed pattern 151A may be interposed between the first upper conductive pattern 153A and the second terminal <NUM>. The first upper seed pattern 151A may be directly connected to a bottom surface of the first upper conductive pattern 153A and the top surface of the second terminal <NUM>. The first upper conductive pattern 153A may be connected through the first upper seed pattern 151A to the second terminal <NUM>. A plurality of first upper conductive patterns 153A may be connected to the second terminal <NUM> of the first capacitor <NUM>. Therefore, a plurality of first bonding bumps <NUM> may be electrically connected to the second terminal <NUM> of the first capacitor <NUM>. As shown in <FIG>, a single upper conductive pattern <NUM> may be connected to the second terminal <NUM> of the second capacitor <NUM>. In this case, a single first bonding bump <NUM> may be electrically connected to the second terminal <NUM> of the second capacitor <NUM>. The second terminal <NUM> may be an output terminal of the capacitor <NUM>, but the embodiment is not limited thereto.

The first redistribution pattern <NUM> may be laterally spaced apart from the capacitor <NUM>. For example, the first metal pattern <NUM> may be laterally spaced apart from the first capacitor <NUM> and the second capacitor <NUM>. A top surface of the first seed pattern <NUM> may be located at a level substantially the same as that of the top surface of the capacitor <NUM>. For example, as shown in <FIG>, the first seed pattern <NUM> may have a top surface 111a at a level substantially the same as that of the top surface 350a of the base layer <NUM>. The top surface 111a of the first seed pattern <NUM> may be located at a level substantially the same as that of the top surface of the second terminal <NUM>. According to an embodiment, the first seed pattern <NUM> may not be provided.

The second upper conductive pattern 153B may be spaced apart from the first upper conductive pattern 153A. The second upper conductive pattern 153B may not vertically overlap the capacitor <NUM>. The term "vertical" may mean "a third direction D3" or "a direction opposite to the third direction D3. " The third direction D3 may be substantially perpendicular to the top surface of the first semiconductor chip <NUM>, and may intersect the first direction D1 and the second direction D2. The third direction D3 may be substantially perpendicular to the first direction D1 and the second direction D2. The second upper conductive pattern 153B may be disposed on the top surface of the first redistribution pattern <NUM>. The second upper seed pattern 151B may be interposed between the second upper conductive pattern 153B and the first redistribution pattern <NUM>, thereby being directly connected to the first redistribution pattern <NUM>. For example, the second upper seed pattern 151B may be directly connected to the first seed pattern <NUM>. The second upper seed pattern 151B may be in contact with the top surface 111a of the first seed pattern <NUM>. According to an embodiment, the first seed pattern <NUM> may be omitted, and the second upper seed pattern 151B may be directly connected to the first metal pattern <NUM>. Accordingly, the semiconductor package <NUM> may become small in size. Further, two redistribution patterns (e.g., the first redistribution pattern <NUM> and the combination of the upper seed pattern <NUM> and the upper conductive pattern <NUM>) are vertically coupled or connected to each other as shown in <FIG>, one or more seed patterns (e.g., the first seed pattern <NUM> and the upper seed pattern <NUM>) may be omitted to further reduce the size of the semiconductor package <NUM>.

As shown in <FIG>, the first semiconductor chip <NUM> may be mounted on a top surface of the redistribution substrate <NUM>. In a plan view, the first semiconductor chip <NUM> may be disposed on a central region of the redistribution substrate <NUM>. The first semiconductor chip <NUM> may include integrated circuits (not shown) and chip pads <NUM>. The integrated circuits may be provided in the first semiconductor chip <NUM>. The chip pads <NUM> may be disposed on a bottom surface of the first semiconductor chip <NUM> and electrically connected to the integrated circuits. The phrase "a certain component is connected to the chip pad <NUM>" may mean that "the certain component is connected to the first semiconductor chip <NUM>. " The first bonding bumps <NUM> may be provided between and connected to a plurality of upper conductive patterns <NUM> and the chip pads <NUM> of the first semiconductor chip <NUM>. Therefore, the first semiconductor chip <NUM> may be electrically connected through the first bonding bumps <NUM> to the second semiconductor chip <NUM>, the capacitors <NUM>, and the solder patterns <NUM>. Although not shown in the drawings, additional conductive patterns (not shown) may further be interposed between the first bonding bumps <NUM> and the upper conductive patterns <NUM>. Each of the first bonding bumps <NUM> may include a solder, a pillar, or a combination thereof. The first bonding bumps <NUM> may include a conductive material, such as copper or a solder material. The first bonding bumps <NUM> may have therebetween a pitch less than that of the solder patterns <NUM> and that of the external coupling terminals <NUM>.

According to embodiments, because the capacitor <NUM> is disposed in the redistribution substrate <NUM>, an electrical path may be reduced between the capacitor <NUM> and the first semiconductor chip <NUM>. For example, an interval B1 between the top surface of the capacitor <NUM> and the top surface of the redistribution substrate <NUM> may be less than an interval B2 between the bottom surface of the capacitor <NUM> and the bottom surface of the redistribution substrate <NUM>. Therefore, the electrical path between the capacitor <NUM> and the first semiconductor chip <NUM> may be additionally reduced to increase electrical characteristics of the semiconductor package <NUM>. For example, the semiconductor package <NUM> may exhibit improved power integrity properties. The interval B1 between the top surface of the capacitor <NUM> and the top surface of the redistribution substrate <NUM> may correspond to a difference in level between the top surface of the upper conductive pattern <NUM> and the top surface of the capacitor <NUM>. The interval B2 between the bottom surface of the capacitor <NUM> and the bottom surface of the redistribution substrate <NUM> may correspond to an interval between the bottom surface of the capacitor <NUM> and the bottom surface of the fourth redistribution pattern <NUM>. In this description, the language "level" may indicate "vertical level", and the expression "difference in level" may be measured in a direction parallel to the third direction D3.

The chip stack <NUM> may be mounted on the top surface of the redistribution substrate <NUM>. The chip stack <NUM> may be laterally spaced apart from the first semiconductor chip <NUM>. The chip stack <NUM> may include a plurality of stacked second semiconductor chips <NUM>. The second semiconductor chips <NUM> may each include integrated circuits (not shown) therein. The second semiconductor chips <NUM> may be disposed on the top surface at an edge region of the redistribution substrate <NUM>. In a plan view, the edge region of the redistribution substrate <NUM> may be provided between a lateral surface and the central region of the redistribution substrate <NUM>. The edge region may surround the central region of the redistribution substrate <NUM>.

The second semiconductor chips <NUM> may be of a type different from the first semiconductor chip <NUM>. For example, the first semiconductor chip <NUM> may be one of a logic chip, a buffer chip, and a system-on-chip (SOC). A lowermost second semiconductor chip <NUM> may be a logic chip, and the other second semiconductor chips <NUM> may be memory chips. The memory chip may include a high bandwidth memory (HBM) chip. The lowermost second semiconductor chip <NUM> may be a logic chip whose type is different from that of the first semiconductor chip <NUM>. For example, the lowermost second semiconductor chip <NUM> may be a controller chip, and the first semiconductor chip <NUM> may include an application specific integrated circuit (ASIC) chip or an application processor (AP) chip. The ASIC chip may include an application specific integrated circuit (ASIC). According to an embodiment, the lowermost second semiconductor chip <NUM> may be a memory chip.

Each of the second semiconductor chips <NUM> may include a lower pad <NUM>, a through electrode <NUM>, and an upper pad <NUM>. The lower pad <NUM> and the upper pad <NUM> may be respectively provided on a bottom surface and a top surface of the second semiconductor chip <NUM>. One or more of the lower pad <NUM> and the upper pad <NUM> may be electrically connected to integrated circuits of the second semiconductor chip <NUM>. The through electrode <NUM> may be disposed in the second semiconductor chip <NUM>, and may be connected to the lower pad <NUM> and the upper pad <NUM>. An uppermost second semiconductor chip <NUM> may include the lower pad <NUM>, but may not include the through electrode <NUM> or the upper pad <NUM>. Differently from that shown, the uppermost second semiconductor chip <NUM> may further include the through electrode <NUM> and the upper pad <NUM>. An interposer bump <NUM> may be interposed between two vertically neighboring second semiconductor chips <NUM>, and may be connected to the lower pad <NUM> of an upper second semiconductor chip <NUM> thereof and the upper pad <NUM> of a lower second semiconductor chip <NUM> thereof. Therefore, a plurality of second semiconductor chips <NUM> may be electrically connected to one another. The interposer bump <NUM> may include a solder, a pillar, or a combination thereof. The interposer bump <NUM> may include metal or a solder material, but the embodiment is not limited thereto.

According to an embodiment, the interposer bump <NUM> may be omitted. In this case, the lower pad <NUM> of the upper second semiconductor chip <NUM> thereof may be directly bonded to the upper pad <NUM> of the lower second semiconductor chip <NUM> thereof.

The second bonding bumps <NUM> may be interposed between the lowermost second semiconductor chip <NUM> and the redistribution substrate <NUM>, and may be connected to corresponding lower pads <NUM> and corresponding upper conductive patterns <NUM>. Therefore, the second semiconductor chips <NUM> may be electrically connected through the redistribution substrate <NUM> to the first semiconductor chip <NUM> and the solder patterns <NUM>. In this description, the phrase "electrically connected to the redistribution substrate <NUM>" may mean "electrically connected to one or more of the upper conductive pattern <NUM> and the first redistribution pattern <NUM>, the second redistribution pattern <NUM>, the third redistribution pattern <NUM>, and the fourth redistribution pattern <NUM>. The second bonding bumps <NUM> may have therebetween a pitch less than that of the solder patterns <NUM> and that of the external coupling terminals <NUM>. The second bonding bumps <NUM> may include a solder, a pillar, or a combination thereof. The second bonding bumps <NUM> may include metal or a solder material, but the embodiment is not limited thereto.

The chip stack <NUM> may be provided in plural. The plurality of chip stacks <NUM> may be laterally spaced apart from each other. The first semiconductor chip <NUM> may be disposed between the chip stacks <NUM>. Therefore, an electrical path may be reduced between the first semiconductor chip <NUM> and the chip stacks <NUM>.

The semiconductor package <NUM> may further include a first under-fill layer <NUM> and second under-fill layer <NUM>. A first under-fill layer <NUM> may be provided in a first gap between the redistribution substrate <NUM> and the first semiconductor chip <NUM>, thereby encapsulating the first bonding bump <NUM>. The first under-fill layer <NUM> may include a dielectric polymer, such as an epoxy-based polymer. The second under-fill layers <NUM> may correspondingly be provided in second gaps between the redistribution substrate <NUM> and the chip stacks <NUM>, thereby encapsulating corresponding second bonding bumps <NUM>. The second under-fill layers <NUM> may include a dielectric polymer, such as an epoxy-based polymer. Differently from that shown, the second under-fill layers <NUM> may be omitted, and in this case, the first under-fill layer <NUM> may further extend into the second gaps, thereby encapsulating the first bonding bumps <NUM> and the second bonding bumps <NUM>. A third under-fill layer <NUM> may further be provided in a third gap between the second semiconductor chips <NUM>, thereby encapsulating a plurality of interposer bumps <NUM>. The third under-fill layer <NUM> may include a dielectric polymer, such as an epoxy-based polymer.

The molding layer <NUM> may be disposed on the redistribution substrate <NUM>, and may also be disposed on a sidewall of the first semiconductor chip <NUM> and sidewalls of the second semiconductor chips <NUM>. The molding layer <NUM> may expose the top surface of the first semiconductor chip <NUM> and a top surface of the uppermost second semiconductor chip <NUM>. Differently from that shown, the molding layer <NUM> may also be disposed on the top surface of the first semiconductor chip <NUM> and the top surface of the uppermost second semiconductor chip <NUM>. According to an embodiment, the first and second under-fill layers <NUM> and <NUM> may be omitted, and the molding layer <NUM> may extend into the first and second gaps.

The semiconductor package <NUM> may further include a conductive plate <NUM>. The conductive plate <NUM> may be disposed on the top surface of the first semiconductor chip <NUM>, a top surface of the chip stack <NUM>, and a top surface of the molding layer <NUM>. The conductive plate <NUM> may further extend onto a sidewall of the molding layer <NUM>. The conductive plate <NUM> may protect the first semiconductor chip <NUM> and the chip stack <NUM> against external environment. For example, the conductive plate <NUM> may absorb external physical impact. The conductive plate <NUM> may include a material whose thermal conductivity is high, and may serve as a heat sink or a heat slug. For example, when the semiconductor package <NUM> operates, the conductive plate <NUM> may promptly externally discharge heat generated from the redistribution substrate <NUM>, the first semiconductor chip <NUM>, and/or the second semiconductor chips <NUM>. The conductive plate <NUM> may have electrical conductivity and serve as an electromagnetic field shield layer. For example, the conductive plate <NUM> may shield electromagnetic interference (EMI) between the first semiconductor chip <NUM> and the second semiconductor chips <NUM>. In this case, the conductive plate <NUM> may be electrically grounded through the redistribution substrate <NUM>, and may prevent the first semiconductor chip <NUM> and/or the second semiconductor chips <NUM> from being electrically damaged caused by electrostatic discharge (ESD).

Although not shown in the drawings, a third semiconductor chip may further be mounted on the redistribution substrate <NUM>. The third semiconductor chip may be of a type different from the first and second semiconductor chips <NUM> and <NUM>. Differently from that shown, the molding layer <NUM> may be omitted.

The number of stacked redistribution patterns <NUM>, <NUM>, <NUM>, and <NUM> may be variously changed. For example, one or more of the second redistribution pattern <NUM> and the third redistribution pattern <NUM> may be omitted. According to an embodiment, a fifth redistribution pattern (not shown) may further be interposed between the third redistribution pattern <NUM> and the fourth redistribution pattern <NUM>.

<FIG> illustrates an enlarged cross-sectional view of section A depicted in <FIG>, showing a connection relationship between a capacitor and a redistribution substrate according to an embodiment. <FIG> will be also referred in explaining <FIG> below.

Referring to <FIG>, the capacitor <NUM> may include a base layer <NUM>, a stack structure <NUM>, a first terminal <NUM>, and a plurality of second terminals <NUM>. The second terminals <NUM> may be laterally spaced apart from each other. A plurality of first upper seed patterns 151A may be directly connected to corresponding second terminals <NUM>. The second terminals <NUM> may be electrically connected through the first upper seed patterns 151A to corresponding chip pads <NUM> of the first semiconductor chip <NUM>.

The first terminal <NUM> may be disposed on a bottom surface of the base layer <NUM>. The first terminal <NUM> may not vertically overlap the second terminal <NUM>. Differently from that shown, the first capacitor <NUM> may include a plurality of first terminals <NUM>, and the plurality of first terminals <NUM> may be connected to corresponding solder patterns (see <NUM> of <FIG>).

<FIG> illustrates a cross-sectional view taken along line I-II of <FIG>, showing a semiconductor package, according to an embodiment. <FIG> illustrates an enlarged view showing section A of <FIG>, according to an embodiment.

Referring to <FIG> and <FIG>, a semiconductor package 1A may include a package substrate <NUM>, a redistribution substrate <NUM>', a capacitor <NUM>, solder patterns <NUM>, a first semiconductor chip <NUM>, a chip stack <NUM>, first bonding bumps <NUM>, second bonding bumps <NUM>, and a molding layer <NUM>.

The redistribution substrate <NUM>' may include a first dielectric layer <NUM>, a second dielectric layer <NUM>, a third dielectric layer <NUM>, a first redistribution pattern <NUM>, a third redistribution pattern <NUM>, a fourth redistribution pattern <NUM>, a lower seed pattern <NUM>, a lower conductive pattern <NUM>, an upper seed pattern <NUM>, and an upper conductive pattern <NUM>. The first redistribution pattern <NUM>, the third redistribution pattern <NUM>, the fourth redistribution pattern <NUM>, the lower seed pattern <NUM>, the lower conductive pattern <NUM>, the upper seed pattern <NUM>, and the upper conductive pattern <NUM> may be substantially the same as those discussed in the examples of <FIG>. In contrast, the redistribution substrate <NUM>' may not include the second redistribution pattern <NUM> or the fourth dielectric layer <NUM> discussed in the examples of <FIG>. The first dielectric layer <NUM> may have the first redistribution pattern <NUM> disposed on a bottom surface thereof. The first redistribution pattern <NUM> may include a first metal pattern <NUM> and a first seed pattern <NUM>. The first metal pattern <NUM> may include a line part and a via part. The via part of the first metal pattern <NUM> may be provided on the line part of the first metal pattern <NUM>, and may have a width less than that of the line part of the first metal pattern <NUM>.

The first seed pattern <NUM> may be disposed on the first metal pattern <NUM>. The first seed pattern <NUM> may have a first top surface 111a'. The first top surface 111a' of the first seed pattern <NUM> may be provided on a top surface of the via part of the first metal pattern <NUM>. The first top surface 111a' of the first seed pattern <NUM> may be located at a level substantially the same as that of the top surface 350a of the base layer <NUM>. The first seed pattern <NUM> may be interposed between the first metal pattern <NUM> and the second upper seed pattern 151B, thereby being directly connected to the second upper seed pattern 151B. The first seed pattern <NUM> may further have a second top surface. The second top surface may be disposed on a top surface of the line part of the first metal pattern <NUM>. The second top surface of the first seed pattern <NUM> may be located at a level lower than that of the first top surface 111a' of the first seed pattern <NUM>. The first seed pattern <NUM> may be further disposed on a sidewall of the via part of the first metal pattern <NUM>.

<FIG> illustrates a cross-sectional view taken along line I-II' of <FIG>, showing a semiconductor package, according to an embodiment.

Referring to <FIG>, a semiconductor package 1B may include a package substrate <NUM>, a redistribution substrate <NUM>, a plurality of capacitors <NUM>, solder patterns <NUM>, a first semiconductor chip <NUM>, a chip stack <NUM>, first bonding bumps <NUM>, second bonding bumps <NUM>, and a molding layer <NUM>.

The capacitors <NUM> may include a first capacitor <NUM>, a second capacitor <NUM>, and a third capacitor <NUM>. Each of the capacitors <NUM> may include a base layer <NUM>, a stack structure <NUM>, a first terminal <NUM>, and a second terminal <NUM>. The first capacitor <NUM> and the second capacitor <NUM> may be substantially the same as those discussed in the examples of <FIG>.

The third capacitor <NUM> may be provided in the redistribution substrate <NUM>, and may vertically overlap the chip stack <NUM>. For example, the third capacitor <NUM> may vertically overlap at least one second semiconductor chip <NUM>. The third capacitor <NUM> may be directly in contact with the first dielectric layer <NUM>. For example, the base layer <NUM> of the third capacitor <NUM> may have opposite sidewalls and a bottom surface that are directly in contact with the first dielectric layer <NUM>. The first terminal <NUM> of the third capacitor <NUM> may be directly connected to the lower seed pattern <NUM>. The second terminal <NUM> of the third capacitor <NUM> may be directly in contact with the upper seed pattern <NUM>.

The third capacitor <NUM> may have a thickness T3 substantially the same as a thickness T1 of the first capacitor <NUM> and a thickness T2 of the second capacitor <NUM>. The third capacitor <NUM> may have a top surface at a level substantially the same as that of a top surface of the first capacitor <NUM> and that of a top surface of the second capacitor <NUM>. The third capacitor <NUM> may have a width W3 different from a width W1 of the first capacitor <NUM>. The width W3 of the third capacitor <NUM> may be different from a width W2 of the second capacitor <NUM>.

<FIG> illustrate cross-sectional views showing a method of fabricating a semiconductor package, according to embodiments. For brevity of description, top and bottom surfaces of a certain component will be discussed based on their related drawing in describing <FIG>. A duplicate description will be omitted below.

Referring to <FIG>, a first carrier substrate <NUM> may be provided. The first carrier substrate <NUM> may be a semiconductor wafer. The semiconductor wafer may include a crystalline semiconductor material. For example, the semiconductor wafer may include silicon, germanium, or a combination thereof.

An etch stop layer <NUM> may be formed on the first carrier substrate <NUM>. The etch stop layer <NUM> may include a silicon-based material. For example, the etch stop layer <NUM> may include silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

First terminals <NUM>, a preliminary base layer <NUM>, stack structures <NUM>, and second terminals <NUM> may be formed on the etch stop layer <NUM>. The second terminals <NUM> may be formed on one surface of the etch stop layer <NUM>. The second terminals <NUM> may be in contact with the one surface of the etch stop layer <NUM>. The second terminals <NUM> may be laterally spaced apart from each other. The second terminals <NUM> may be in contact with one surface of the etch stop layer <NUM>. The preliminary base layer <NUM> may be formed on the etch stop layer <NUM> and the second terminals <NUM>. The preliminary base layer <NUM> may be disposed on one surface of the etch stop layer <NUM>, top surfaces of the second terminals <NUM>, and sidewalls of the second terminals <NUM>. The preliminary base layer <NUM> may include a silicon-based dielectric material.

The stack structures <NUM> may be formed in the preliminary base layer <NUM> and may be connected to the second terminals <NUM>. The formation of the stack structures <NUM> may include forming a trench in the preliminary base layer <NUM>, and forming a dielectric layer and a conductive layer in the trench. The formation of the dielectric and conductive layers may be repeatedly performed. Therefore, the stack structure <NUM> may include a plurality of conductive layers and a plurality of dielectric layers disposed between corresponding conductive layers. The first terminals <NUM> may be formed on the stack structures <NUM>. The first terminals <NUM> may be laterally spaced apart from each other.

Referring to <FIG>, the preliminary base layer <NUM> may undergo an etching process to form capacitors <NUM>. The etching process may partially remove the preliminary base layer <NUM> to form base layers <NUM>. The base layers <NUM> may be laterally spaced apart from each other, and may expose the etch stop layer <NUM>. Each of the capacitors <NUM> may include a corresponding one of the first terminals <NUM>, a corresponding one of the base layers <NUM>, a corresponding at least one of the stack structures <NUM>, and a corresponding one of the second terminals <NUM>. Each of the stack structures <NUM> may be provided in a corresponding one of the base layers <NUM>. For example, the stack structure <NUM> may have a sidewall that is covered with the base layer <NUM> and is not exposed to the outside. The capacitors <NUM> may be laterally spaced apart from each other.

The capacitors <NUM> may be formed substantially at the same time in a single process. Therefore, the capacitors <NUM> may have the same thickness. For example, the capacitors <NUM> may include a first capacitor <NUM> and a second capacitor <NUM>, and the second capacitor <NUM> may have a thickness T2 substantially the same as a thickness T1 of the first capacitor <NUM>. The second capacitor <NUM> may have a width different from that of the first capacitor <NUM>. According to an embodiment, the second capacitor <NUM> may have the same width as that of the first capacitor <NUM>.

Referring to <FIG>, a first redistribution pattern <NUM> may be formed on an exposed surface of the etch stop layer <NUM>. The formation of the first redistribution pattern <NUM> may include forming a first seed pattern <NUM> and forming a first metal pattern <NUM> on the first seed pattern <NUM>. The first seed pattern <NUM> may be in contact with one surface of the etch stop layer <NUM>. The formation of the first metal pattern <NUM> may include performing an electroplating process in which the first seed pattern <NUM> is used as an electrode. The first redistribution pattern <NUM> may be laterally spaced apart from the capacitors <NUM>.

A first dielectric layer <NUM> may be formed on the first redistribution pattern <NUM> to be also disposed on one surface of the etch stop layer <NUM>, a top surface and sidewalls of the first redistribution pattern <NUM>, and top surfaces and sidewalls of the capacitors <NUM>. The formation of the first dielectric layer <NUM> may include coating a photosensitive polymer. The first dielectric layer <NUM> may have undulation on a top surface thereof.

Referring to <FIG>, a second redistribution pattern <NUM>, a lower seed pattern <NUM>, and a lower conductive pattern <NUM> may be formed in the first dielectric layer <NUM> and on a top surface of the first dielectric layer <NUM>. The formation of the second redistribution pattern <NUM>, the lower seed pattern <NUM>, and the lower conductive pattern <NUM> may include forming openings in the first direction layer <NUM>, forming a seed layer in the openings and on the top surface of the first dielectric layer <NUM>, forming on the seed layer a resist pattern that has guide openings, performing an electroplating process in which the seed layer is used as an electrode, removing a portion of the resist pattern to expose a portion of the seed layer, and etching the exposed portion of the seed layer. The openings may expose the first terminal <NUM> or the first redistribution pattern <NUM>. The guide openings may be spatially connected to corresponding openings. The electroplating process may form a lower conductive pattern <NUM> and a second metal pattern <NUM> in the openings. The lower conductive pattern <NUM> and the second metal pattern <NUM> may fill a lower portion of their corresponding guide opening. The lower conductive pattern <NUM> may include the same material as that of the second metal pattern <NUM>. The etching of the seed layer may form a second seed pattern <NUM> and a lower seed pattern <NUM>. The lower seed pattern <NUM> may be disposed on one of the capacitors <NUM>, and may be directly connected to the first terminal <NUM>.

The second seed pattern <NUM> may be spaced and electrically separated from the lower seed pattern <NUM>. The second seed pattern <NUM> and the lower seed pattern <NUM> may be formed in a single process. The second seed pattern <NUM> may have the same thickness as that of the lower seed pattern <NUM>, and may include the same material as that of the lower seed pattern <NUM>.

Referring to <FIG>, a second dielectric layer <NUM>, a third redistribution pattern <NUM>, a third dielectric layer <NUM>, and a fourth redistribution pattern <NUM> may be formed above one surface of the first carrier substrate <NUM>. The second dielectric layer <NUM> may be formed on the second redistribution pattern <NUM> and the top surface of the first dielectric layer <NUM>. The second dielectric layer <NUM> may be formed by the same method used for forming the first dielectric layer <NUM>. The third redistribution pattern <NUM> may be formed in the second dielectric layer <NUM> and on a top surface of the second dielectric layer <NUM>. The third redistribution pattern <NUM> may include a plurality of third redistribution patterns <NUM>. At least one of the third redistribution patterns <NUM> may be connected to the second redistribution pattern <NUM>. Another at least one of the third redistribution patterns <NUM> may be connected to the lower conductive pattern <NUM>. The third redistribution pattern <NUM> may be formed by substantially the same method used for forming the second redistribution pattern <NUM>. The third dielectric layer <NUM> may be formed on the second dielectric layer <NUM> and the third redistribution pattern <NUM>.

When the capacitors <NUM> have their thicknesses each of which is greater than about <NUM>% of that of a redistribution substrate <NUM> which will be manufactured in <FIG>, the third dielectric layer <NUM> may have undulation at a top surface thereof in <FIG>. According to embodiments, the capacitors <NUM> may have their thicknesses each of which is equal to or less than about <NUM>% of that of a redistribution substrate (see <NUM> of <FIG>), and thus, the third dielectric layer <NUM> may have reduced or no undulation at the top surface thereof in <FIG>. For example, the first capacitor <NUM> and the second capacitor <NUM> may respectively have a thickness T1 and a second thickness T2 each of which is about <NUM>% to about <NUM>% of the thickness of the redistribution substrate <NUM>.

A plurality of fourth redistribution patterns <NUM> may be formed in the third dielectric layer <NUM> and on a top surface of the third dielectric layer <NUM>. The fourth redistribution patterns <NUM> may be connected to corresponding third redistribution patterns <NUM>. Accordingly, the preliminary redistribution substrate 100P may be formed. The preliminary redistribution substrate 100P may include the first dielectric layer <NUM>, the second dielectric layer <NUM>, the third dielectric layer <NUM>, the first redistribution pattern <NUM>, the second redistribution pattern <NUM>, the third redistribution pattern <NUM>, the fourth redistribution pattern <NUM>, the lower seed pattern <NUM>, and the lower conductive pattern <NUM>.

Differently from the explanation of <FIG> and <FIG>, the lower seed pattern <NUM> and the lower conductive pattern <NUM> may be formed by a single process used for forming the third redistribution pattern <NUM>. In this case, the lower seed pattern <NUM> and the lower conductive pattern <NUM> may be disposed on the top surface of the second dielectric layer <NUM>, and may penetrate the second dielectric layer <NUM> and the first dielectric layer <NUM>, thereby being connected to the first terminal <NUM>. For example, the third redistribution pattern <NUM> may not be connected to the lower conductive pattern <NUM>, and at least one of the fourth redistribution patterns <NUM> may be connected to the lower conductive pattern <NUM>.

Referring to <FIG>, solder patterns <NUM> may be formed on the preliminary redistribution substrate 100P. According to an embodiment, the solder patterns <NUM> may be correspondingly formed on top surface of the fourth redistribution patterns <NUM>. For example, the formation of the solder patterns <NUM> may include performing a solder-ball attaching process.

A second carrier substrate <NUM> may be disposed on the solder patterns <NUM> and the third dielectric layer <NUM>. A carrier adhesive layer <NUM> may be formed between the third dielectric layer <NUM> and the second carrier substrate <NUM>. The carrier adhesive layer <NUM> may be interposed between and encapsulate the solder patterns <NUM>. The second carrier substrate <NUM> may be attached through the carrier adhesive layer <NUM> to the preliminary redistribution substrate 100P. The placement of the second carrier substrate <NUM> may be followed or preceded by the formation of the carrier adhesive layer <NUM>.

Referring to <FIG>, the preliminary redistribution substrate 100P may be turned upside down to place the second carrier substrate <NUM> on a bottom surface of the preliminary redistribution substrate 100P. The first carrier substrate <NUM> may be disposed on a top surface of the preliminary redistribution substrate 100P.

Referring to <FIG>, the first carrier substrate <NUM> and the etch stop layer <NUM> may be removed to expose a top surface of the first dielectric layer <NUM>, a top surface of the first seed pattern <NUM>, and top surfaces of the capacitors <NUM>. For example, the removal of the first carrier substrate <NUM> and the etch stop layer <NUM> may expose a top surface of the base layer <NUM> in each of the capacitors <NUM>, and may also expose a top surface of the second terminal <NUM> in each of the capacitors <NUM>. Because the first seed pattern <NUM> and the capacitors <NUM> are formed on one surface of the etch stop layer <NUM> as discussed in the examples of <FIG>, the first seed pattern <NUM> may have a top surface at a level substantially the same as that of the top surfaces of the capacitors <NUM>. For example, the top surface of the first seed pattern <NUM> may be located at a level substantially the same as that of a top surface of the base layer <NUM> in each of the capacitors <NUM>. The top surface of the first seed pattern <NUM> may be located at a level substantially the same as that of a top surface of the second terminal <NUM>, but the embodiment is not limited thereto.

Referring to <FIG>, a fourth dielectric layer <NUM> may be formed on a top surface of the first dielectric layer <NUM>, the top surface of the first seed pattern <NUM>, the top surface of the base layer <NUM>, and the top surface of the second terminal <NUM>. The fourth dielectric layer <NUM> may be in contact with the top surfaces of the capacitors <NUM>. For example, the fourth dielectric layer <NUM> may be in contact with the top surface of the base layer <NUM> and the top surface of the second terminal <NUM> in each of the capacitors <NUM>. The fourth dielectric layer <NUM> may be formed by a coating process, but the embodiment is not limited thereto.

Upper seed patterns <NUM> and upper conductive patterns <NUM> may be formed in and on the fourth dielectric layer <NUM>. The upper seed patterns <NUM> and the upper conductive patterns <NUM> may be substantially the same as those discussed in <FIG>. The processes mentioned above may form a redistribution substrate <NUM>.

Referring to <FIG>, a first semiconductor chip <NUM> and chip stacks <NUM> may be mounted on the redistribution substrate <NUM>. The mounting of the first semiconductor chip <NUM> may include forming first bonding bumps <NUM> between chip pads <NUM> of the first semiconductor chip <NUM> and their corresponding upper conductive patterns <NUM>. The mounting of the chip stacks <NUM> on the redistribution substrate <NUM> may include forming second bonding bumps <NUM> between lower pads <NUM> of lowermost second semiconductor chips <NUM> and their corresponding upper conductive patterns <NUM>. The chip stack <NUM> may be the same as that discussed in the examples of <FIG>.

A first under-fill layer <NUM> may be formed between the redistribution substrate <NUM> and the first semiconductor chip <NUM>. A plurality of second under-fill layers <NUM> may be formed between the redistribution substrate <NUM> and a plurality of second semiconductor chips <NUM>. A molding layer <NUM> may be formed on the redistribution substrate <NUM> to cover the first semiconductor chip <NUM> and the chip stacks <NUM>. The molding layer <NUM> may undergo a grinding process to expose a top surface of the first semiconductor chip <NUM> and a top surface of uppermost second semiconductor chip <NUM>. A conductive plate <NUM> may further be formed on the first semiconductor chip <NUM>, the molding layer <NUM>, and the uppermost second semiconductor chips <NUM>.

After the formation of the molding layer <NUM>, the second carrier substrate <NUM> and the carrier adhesive layer <NUM> may be removed to expose the redistribution substrate <NUM> and the solder patterns <NUM> as indicated by dotted lines. For example, a bottom surface of the third dielectric layer <NUM> may be exposed.

Referring back to <FIG>, the redistribution substrate <NUM> may be disposed on a package substrate <NUM>, and the solder patterns <NUM> may be aligned with corresponding metal pads <NUM>. The solder patterns <NUM> and their corresponding metal pads <NUM> may be connected to electrically connect the redistribution substrate <NUM> to the package substrate <NUM>. Through the processes mentioned above, the semiconductor package <NUM> of <FIG> may be eventually manufactured.

<FIG> illustrate cross-sectional views showing a method of fabricating a semiconductor package, according to embodiments. A duplicate description will be omitted below. For brevity of description, top and bottom surfaces of a certain component will be discussed based on their related drawing in describing <FIG>.

Referring to <FIG>, an etch stop layer <NUM> may be formed on a first carrier substrate <NUM>. The method discussed in the example of <FIG> may be used to form the etch stop layer <NUM>. Capacitors <NUM> may be formed on one surface of the etch stop layer <NUM>. The capacitors <NUM> may be formed by the processes discussed in the example of <FIG>.

A first dielectric layer <NUM> may be formed on one surface of the etch stop layer <NUM> and also on top surfaces and sidewalls of the capacitors <NUM>.

A first redistribution pattern <NUM>, a lower seed pattern <NUM>, and a lower conductive pattern <NUM> may be formed in and on the first dielectric layer <NUM>. The formation of the first redistribution pattern <NUM> may include forming openings in the first dielectric layer <NUM>, forming a seed layer in the openings, forming on the seed layer a resist pattern that has guide openings, performing an electroplating process in which the seed layer is used as an electrode, removing the resist pattern to expose a portion of the seed layer, and etching the exposed portion of the seed layer. The openings may expose the first terminals <NUM> or a surface of the etch stop layer <NUM>. The guide openings may be spatially connected to corresponding openings. The electroplating process may form a lower conductive pattern <NUM> and a first metal pattern <NUM> in each of the openings. The lower conductive pattern <NUM> and the first metal pattern <NUM> may fill a lower portion of their corresponding guide opening. The etching of the seed layer may form a first seed pattern <NUM> and a lower seed pattern <NUM>. The first seed pattern <NUM> may be laterally spaced apart from the capacitors <NUM>, and may be in contact with the etch stop layer <NUM>. The lower seed pattern <NUM> may be disposed on one of the capacitors <NUM>, and may be directly connected to the first terminal <NUM>. The lower seed pattern <NUM> may be spaced apart and electrically separated from the first seed pattern <NUM>. The lower seed pattern <NUM> and the first seed pattern <NUM> may be formed in a single process. The lower seed pattern <NUM> may have substantially the same thickness as that of the first seed pattern <NUM>, and may include the same material as that of the first seed pattern <NUM>.

The first metal pattern <NUM> may be formed on the first seed pattern <NUM>. The lower conductive pattern <NUM> may be formed on the lower seed pattern <NUM>. The lower conductive pattern <NUM> may include the same material as that of the first metal pattern <NUM>.

Referring to <FIG>, a second dielectric layer <NUM>, third redistribution patterns <NUM>, a third dielectric layer <NUM>, and fourth redistribution patterns <NUM> may be formed to form a preliminary redistribution substrate 100P. The method discussed in the example of <FIG> may be used to form the second dielectric layer <NUM>, the third redistribution patterns <NUM>, the third dielectric layer <NUM>, and the fourth redistribution patterns <NUM>.

Referring to <FIG>, solder patterns <NUM> may be formed on corresponding fourth redistribution patterns <NUM>. A carrier adhesive layer <NUM> may be formed on the preliminary redistribution substrate 100P and the third dielectric layer <NUM>. The carrier adhesive layer <NUM> may cover the solder pattern <NUM>. A second carrier substrate <NUM> may be attached to the carrier adhesive layer <NUM>. The preliminary redistribution substrate 100P may be fixed through the carrier adhesive layer <NUM> to the second carrier substrate <NUM>.

Referring to <FIG>, the preliminary redistribution substrate 100P may be turned upside down to place the second carrier substrate <NUM> on a bottom surface of the preliminary redistribution substrate 100P. Afterwards, as indicated by dotted lines, the first carrier substrate <NUM> and the etch stop layer <NUM> may be removed to expose a top surface of the first dielectric layer <NUM>, a first top surface of the first seed pattern <NUM>, and top surfaces of the capacitors <NUM>. For example, the removal of the first carrier substrate <NUM> and the etch stop layer <NUM> may expose a top surface of the second terminal <NUM> in each of the capacitors <NUM>, and may also expose a top surface of the base layer <NUM> in each of the capacitors <NUM>.

Referring to <FIG>, upper seed patterns <NUM> may be correspondingly formed on the first top surface of the first seed pattern <NUM> and the top surfaces of the second terminals <NUM>. Upper conductive patterns <NUM> may be formed on corresponding upper seed patterns <NUM>. Accordingly, a redistribution substrate <NUM>' may be eventually formed.

Referring to <FIG> and <FIG>, a first semiconductor chip <NUM> and chip stacks <NUM> may be mounted on a top surface of the redistribution substrate <NUM>'. A first under-fill layer <NUM>, second under-fill layers <NUM>, a molding layer <NUM>, and a conductive plate <NUM> may be formed on the top surface of the redistribution substrate <NUM>'. The second carrier substrate <NUM> and the carrier adhesive layer <NUM> may be removed to expose the solder patterns <NUM> and the third dielectric layer <NUM>. The redistribution substrate <NUM>' may be disposed on the package substrate <NUM>. The solder patterns <NUM> may be aligned with and connected to corresponding metal pads <NUM>. Accordingly, the semiconductor package 1A of <FIG> and <FIG> may be eventually fabricated.

<FIG> illustrates a cross-sectional view showing a semiconductor package, according to an embodiment.

Referring to <FIG>, a semiconductor package <NUM> may include a redistribution substrate <NUM>, capacitors <NUM>, solder patterns <NUM>, a first semiconductor chip <NUM>, first bonding bumps <NUM>, and a molding layer <NUM>. The redistribution substrate <NUM>, the capacitors <NUM>, the solder patterns <NUM>, the first semiconductor chip <NUM>, the first bonding bumps <NUM>, and the molding layer <NUM> may be substantially the same as those discussed in the examples of <FIG>. The semiconductor package <NUM> may further include a first under-fill layer <NUM>. In contrast, the semiconductor package <NUM> may include neither of the chip stack <NUM>, the second under-fill layers <NUM>, and the package substrate <NUM>.

Differently from that shown, the semiconductor package <NUM> may be manufactured using the redistribution substrate <NUM>' discussed in <FIG> and <FIG>. In this case, the first redistribution pattern <NUM>, the upper seed pattern <NUM>, and the upper conductive pattern <NUM> may be substantially the same as those discussed in the examples of <FIG> and <FIG>.

Referring to <FIG>, a semiconductor package <NUM> may include a lower package <NUM> and an upper package <NUM>. The lower package <NUM> may include a redistribution substrate <NUM>, capacitors <NUM>, solder patterns <NUM>, first bumps 251A, second bumps 252A, a first lower semiconductor chip 210A, a second lower semiconductor chip 220A, a molding layer <NUM>, and a conductive structure <NUM>. The redistribution substrate <NUM>, the capacitors <NUM>, the solder patterns <NUM>, and the molding layer <NUM> may be substantially the same as those discussed in the examples of <FIG>.

The first lower semiconductor chip 210A and the second lower semiconductor chip 220A may be mounted on a top surface of the redistribution substrate <NUM>. The second lower semiconductor chip 220A may be laterally spaced apart from the first lower semiconductor chip 210A. The second lower semiconductor chip 220A may be of a type different from the first lower semiconductor chip 210A. For example, the first lower semiconductor chip 210A may include one of a logic chip, a memory chip, and a power management chip, and the second lower semiconductor chip 220A may include another of a logic chip, a memory chip, and a power management chip. The logic chip may include an application specific integrated circuit (ASIC) chip or an application processor (AP) chip. The power management chip may include a power management integrated circuit (PMIC). For example, the first lower semiconductor chip 210A may be an ASIC chip, and the second lower semiconductor chip 220A may be a power management chip. Each of the first and second lower semiconductor chips 210A and 220A may be analogous to the first semiconductor chip <NUM> discussed in <FIG> and <FIG>. Differently from that shown, one or more of the first and second lower semiconductor chips 210A and 220A may be omitted. Alternatively, a third semiconductor chip (not shown) may further be mounted on the top surface of the redistribution substrate <NUM>.

The capacitors <NUM> may include a first capacitor <NUM> and a second capacitor <NUM>. At least a portion of the first capacitor <NUM> may vertically overlap the first lower semiconductor chip 210A. A single or plurality of first capacitors <NUM> may be provided. At least a portion of the second capacitor <NUM> may vertically overlap the second lower semiconductor chip 220A. A single or plurality of second capacitors <NUM> may be provided. Differently from that shown, one or both of the first capacitor <NUM> and the second capacitor <NUM> may be omitted.

The first bumps 251A and the second bumps 252A may be respectively similar to the first bonding bumps <NUM> and the second bonding bumps <NUM> discussed in <FIG> and <FIG>. The first lower semiconductor chip 210A may have chip pads 215A that are electrically connected through the first bumps 251A to the redistribution substrate <NUM> and the first capacitor <NUM>. The second lower semiconductor chip 220A may have chip pads 225A that are electrically connected through the second bumps 252A to the redistribution substrate <NUM> and the second capacitor <NUM>. The second lower semiconductor chip 220A may be electrically connected through the redistribution substrate <NUM> to the first lower semiconductor chip 210A.

The redistribution substrate <NUM> may be provided on its top surface with the conductive structure <NUM> connected to its corresponding upper conductive pattern <NUM>. The conductive structure <NUM> may be laterally spaced apart from the first and second lower semiconductor chips 210A and 220A. In a plan view, the conductive structure <NUM> may be provided on an edge region of the redistribution substrate <NUM>. A metal pillar may be provided on the redistribution substrate <NUM> to form the conductive structure <NUM>. For example, the conductive structure <NUM> may be a metallic column. The conductive structure <NUM> may be electrically connected to the redistribution substrate <NUM>. For example, the conductive structure <NUM> may be electrically connected through the redistribution substrate <NUM> to the first lower semiconductor chip 210A, the second lower semiconductor chip 220A, and/or the solder pattern <NUM>. The conductive structure <NUM> may include metal, such as copper. Differently from that shown, the conductive structure <NUM> may be electrically connected to one of the capacitors <NUM>.

The molding layer <NUM> may be disposed on the top surface of the redistribution substrate <NUM>, and may cover the first and second lower semiconductor chips 210A and 220A. The molding layer <NUM> may cover sidewalls of the conductive structure <NUM>. The molding layer <NUM> may have a sidewall aligned with that of the redistribution substrate <NUM>. The molding layer <NUM> may expose a top surface 550a of the conductive structure <NUM>.

The lower package <NUM> may further include an upper redistribution layer <NUM>. The upper redistribution layer <NUM> may be provided on a top surface of the molding layer <NUM>. The upper redistribution layer <NUM> may include an upper dielectric layer <NUM>, an upper redistribution pattern <NUM>, and upper bonding pads <NUM>. The upper dielectric layer <NUM> may be stacked on the molding layer <NUM>. The upper dielectric layer <NUM> may include a photosensitive polymer. Each of the upper redistribution patterns <NUM> may include a via part in the upper dielectric layers <NUM> and a line part. The via part of the each of the upper redistribution patterns <NUM> may be in corresponding one of the upper dielectric layers <NUM>. The line part of the each of the upper redistribution patterns <NUM> may be provided between the upper dielectric layers <NUM>. The upper redistribution pattern <NUM> may include metal, such as copper. The upper redistribution pattern <NUM> may be in contact with the top surface 550a of the conductive structure <NUM>. The upper bonding pads <NUM> may be disposed in the upper dielectric layer <NUM>, and may be connected to the upper redistribution patterns <NUM>. The upper bonding pad <NUM> may be electrically connected through the upper redistribution pattern <NUM> and the conductive structure <NUM> to the solder pattern <NUM>, the first lower semiconductor chip 210A, and/or the second lower semiconductor chip 220A. The presence of the upper redistribution pattern <NUM> may allow the upper bonding pad <NUM> to not be vertically aligned with (e.g. to not overlap) the conductive structure <NUM>.

According to an embodiment, the lower package <NUM> may be manufactured using the redistribution substrate <NUM>' discussed in the example of <FIG> and <FIG>.

The upper package <NUM> may be disposed on the lower package <NUM>. For example, the upper package <NUM> may be placed on the upper redistribution layer <NUM>. The upper package <NUM> may include an upper substrate <NUM>, an upper semiconductor chip <NUM>, and an upper molding layer <NUM>. The upper substrate <NUM> may be a printed circuit board or a redistribution layer. A first connection pad <NUM> and a second connection pad <NUM> may be respectively disposed on a bottom surface and a top surface of the upper substrate <NUM>. The upper substrate <NUM> may be provided therein with a wiring line <NUM> connected to the first connection pad <NUM> and the second connection pad <NUM>. The wiring line <NUM> is schematically illustrated, and may be variously changed in shape and arrangement. The first connection pad <NUM>, the second connection pad <NUM>, and the wiring line <NUM> may include a conductive material, such as metal.

The upper semiconductor chip <NUM> may be disposed on the upper substrate <NUM>. The upper semiconductor chip <NUM> may include integrated circuits (not shown), and the integrated circuits may include a memory circuit, a logic circuit, or a combination thereof. The upper semiconductor chip <NUM> may be of a type different from the first and second lower semiconductor chips 210A and 220A. For example, the upper semiconductor chip <NUM> may be a memory chip. A bump terminal <NUM> may be interposed between the upper substrate <NUM> and the upper semiconductor chip <NUM>, and may be connected to the second connection pad <NUM> and a chip pad <NUM> of the upper semiconductor chip <NUM>. Differently from that shown, the bump terminal <NUM> may be omitted, and the chip pad <NUM> may be directly connected to the second connection pad <NUM>.

The upper molding layer <NUM> may be provided on the upper substrate <NUM>, and may cover the upper semiconductor chip <NUM>. The upper molding layer <NUM> may include a dielectric polymer, such as an epoxy-based polymer.

The upper package <NUM> may further include a thermal radiation structure <NUM>. The thermal radiation structure <NUM> may include a heat sink, a heat slug, or a thermal interface material (TIM) layer. The thermal radiation structure <NUM> may include, for example, metal. The thermal radiation structure <NUM> may be disposed on a top surface of the upper molding layer <NUM>. The thermal radiation structure <NUM> may further extend onto a sidewall of the upper molding layer <NUM> or a sidewall of the molding layer <NUM>.

The semiconductor package <NUM> may further include a connection terminal <NUM>. The connection terminal <NUM> may be interposed between and connected to the upper bonding pad <NUM> and the first connection pad <NUM>. Therefore, the upper package <NUM> may be electrically connected through the connection terminal <NUM> to the first lower semiconductor chip 210A, the second lower semiconductor chip 220A, and/or the solder pattern <NUM>. The connection terminal <NUM> may include a solder, a bump, or a combination thereof. The connection terminal <NUM> may include a solder material. An electrical connection with the upper package <NUM> may mean an electrical connection with integrated circuits in the upper semiconductor chip <NUM>.

According to an embodiment, the upper substrate <NUM> may be omitted, and the connection terminal <NUM> may be directly connected to the chip pad <NUM> of the upper semiconductor chip <NUM>. In this case, the upper molding layer <NUM> may be in direct contact with a top surface of the upper redistribution layer <NUM>. According to an embodiment, the upper substrate <NUM> and the connection terminal <NUM> may be omitted, and the chip pad <NUM> of the upper semiconductor chip <NUM> may be directly connected to the upper bonding pad <NUM>.

Claim 1:
A semiconductor package comprising:
a redistribution substrate (<NUM>);
at least one passive device (<NUM>) in the redistribution substrate (<NUM>), the passive device (<NUM>) including a first terminal (<NUM>) and a second terminal (<NUM>); and
a semiconductor chip (<NUM>) on a top surface of the redistribution substrate (<NUM>), the semiconductor chip (<NUM>) vertically overlapping at least a portion of the passive device (<NUM>),
wherein the redistribution substrate (<NUM>) comprises:
a dielectric layer (<NUM>) in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device (<NUM>);
a lower conductive pattern (<NUM>) on the first terminal (<NUM>);
a lower seed pattern (<NUM>) provided between the first terminal (<NUM>) and the lower conductive pattern (<NUM>), and directly connected to the first terminal (<NUM>);
a first upper conductive pattern (<NUM>) on the second terminal (<NUM>);
a first upper seed pattern (<NUM>) provided between the second terminal (<NUM>) and the first upper conductive pattern (<NUM>), and directly connected to the second terminal (<NUM>),
wherein an interval between a top surface of the passive device (<NUM>) and the top surface of the redistribution substrate (<NUM>) is less than an interval between the bottom surface of the passive device (<NUM>) and a bottom surface of the redistribution substrate (<NUM>).