Patent Description:
With the rapid growth in the Internet and various mission-critical applications, the importance of preserving data integrity and ensuring continuous access to critical information cannot be overstated. To satisfy the needs in preserving and accessing reliable data, redundant array of independent disks (RAID) algorithm has been used to improve the performance, reliability, power consumption, and scalability in NAND memory devices. RAID algorithm employs the techniques of striping, mirroring, and/or parity to create large reliable data stores from multiple storage units.

Amongst the different levels of RAIDs, the level <NUM> of RAID, a. RAID <NUM>, is commonly used in preserving data integrity in NAND memory devices. RAID <NUM> employs of block-level striping with distributed parity (e.g., redundant information). The parity information is distributed among the drives. Upon failure of a single drive, the data in the failed drive can be retrieved from the distributed parity and the rest of the drives such that no memory data is lost. A memory apparatus for storing redundancy data in unused space of the memory according to two different redundancy schemes is described by <CIT>. Another memory system for controlling the redundancy of a memory by writing redundancy data in a sub space of the memory as well as a corresponding method is described by <CIT>.

A memory apparatus is provided. The apparatus includes a plurality of memory cells stored with memory data in N dies. Each of the N dies includes M planes. Each of the M planes includes a memory block. N and M are each a positive integer. The apparatus also includes a controller operatively coupled to the plurality of memory cells. The controller is configured to determine J layers in the memory block in each of the M planes and in each of the N dies, each of the J layers comprising a pair of adj acent gate conductive layers. J is a positive integer. The controller is also configured to determine M sets of stripes. Each of the M sets of stripes comprising a plurality of data portions stored in a respective one of the M planes. The controller is further configured to determine M sets of parity data portions. Each of the M sets of parity data portions corresponding to a respective one of the M stripes. The controller is further configured to control a temporary storage unit to store the M sets of parity data portions.

A memory apparatus is provided. The apparatus includes a plurality of memory cells stored with memory data in N dies. Each of the N dies includes M planes. Each of the M planes includes a memory block. N and M are each a positive integer. The apparatus includes a controller operatively coupled to the plurality of memory cells. The controller is configured to determine J layers in the memory block in each of the M planes and in each of the N dies. Each of the J layers includes a pair of adjacent gate conductive layers. J is a positive integer of at least <NUM>. The controller is also configured to determine J stripes each corresponding to M layers of the same level in the M planes and comprising M×N data portions. Each of the M×N data portions is stored in a respective portion of the respective M layers. The controller is further configured to determine J parity data portions each corresponding to a respective stripe. The controller is further configured to control a temporary storage unit to store the J parity data portions.

A method for operating a memory apparatus using RAID striping is provided. The apparatus includes a plurality of memory cells stored with memory data in N dies. Each of the N dies includes M planes. Each of the M planes includes a memory block. N and M are each a positive integer. The method includes determining J layers in the memory block in each of the M planes and in each of the N dies. Each of the J layers includes a pair of adjacent gate conductive layers. J is a positive integer. The method also includes determining M sets of stripes, each of the M sets of stripes comprising a plurality of data portions stored in a respective one of the M planes. The method also includes determining M sets of parity data portions. Each of the M sets of parity data portions corresponds to a respective one of the M stripes. The method further includes controlling a temporary storage unit to store the M sets of parity data portions.

A method for operating a memory apparatus using RAID striping is provided. The apparatus includes a plurality of memory cells stored with memory data in N dies. Each of the N dies includes M planes. Each of the M planes includes a memory block. N and M are each a positive integer. The method includes determining J layers in the memory block in each of the M planes and in each of the N dies. Each of the J layers includes a pair of adjacent gate conductive layers. J is a positive integer of at least <NUM>. The method also includes determining J stripes each corresponding to M layers of the same level in the M planes and comprising M×N data portions. Each of the M×N data portions is stored in a respective portion of the respective M layers. The method further includes determining J parity data portions each corresponding to a respective stripe. The method further includes controlling a temporary storage unit to store the J parity data portions.

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate implementations of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

Aspects of the present disclosure will be described with reference to the accompanying drawings.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present discloses.

As used herein, the term "memory string" refers to a vertically-oriented string of memory cell transistors connected in series on a laterally-oriented substrate so that the string of memory cell transistors extends in the vertical direction with respect to the substrate. As used herein, the term "vertical/vertically" means perpendicular to the lateral surface of a substrate.

To increase storage capacity, NAND Flash memories often include, laterally, multiple dies, each having multiple planes. Each plane is laterally divided into one or more memory blocks, each including multiple gate conductive layers extending laterally. One memory block includes a number of gate conductive layers arranged vertically in a number of levels, and each gate conductive layer is coupled to memory cells in multiple pages laterally distributed in the memory block. As the number gate conductive layers continue to increase vertically to increase the storage capacity of the NAND Flash memories, the space between adjacent gate conductive layers becomes smaller. Interferences between adjacent gate conductive layers become prominent. To improve the integrity and readability of the memory cells, RAID <NUM> has been widely used in NAND Flash memory. Typically, RAID <NUM> employs striping in memory blocks to divide the memory data in the memory blocks into a plurality of data portions, performing exclusive or (XOR) operations amongst data portions in the stripe to generate respective parity data, and stores the parity data in the memory cells. One data portion can represent the memory data in one page. One stripe often includes data portions located in two-dimensions, e.g., laterally in different memory blocks across different dies and different planes, and vertically in different levels in the same memory blocks. For example, for memory blocks in <NUM> planes and <NUM> dies, a stripe can include <NUM> data portions, distributed laterally (e.g., in all the planes and dies) and vertically (e.g., in more than one level). Laterally, the stripe can include data portions at the same locations in different planes. Vertically, the stripe can include data portions at the same locations in different levels. The last data portion often includes the parity data of the stripe. In case of programming failure in one data portion of a stripe, the compromised data portion can be recovered, e.g., by performing XOR operations, using the parity data of the stripe and the rest of the data portions in the stripe. For example, for a stripe that has <NUM> data portions, <NUM> data portions are used to store the memory data, and one data portion is used to store the parity data of the stripe, the error correction capability of RAID <NUM> using such striping configuration can thus be described as (<NUM>+<NUM>).

However, the RAID <NUM> can be used to recover only one compromised data portion in a stripe. In case of scenarios that cause two or more compromised data portions in a stripe, the RAID <NUM>, with the striping configuration as described above, is incapable of recovering the more than one compromised data portion. For example, one scenario that can cause more than one compromised data portions in one stripe is a "multi-plane failure," which can be caused by programming errors when multiple planes are being programmed in parallel. Data portions, in the same stripe, at the same locations in different planes, can be compromised. Another scenario that can cause more than one compromised data portions in one stripe is a "source-select gate (SSG) leakage failure," which is caused by current leakage of SSG. The SSG leakage failure can cause the data portions coupled to the SSG, e.g., at the same locations in more than levels, to be compromised. The current striping configuration is susceptible to having more than one compromised data portions in a single stripe if one or both of the scenarios occur. As a result, memory data in these compromised data portions may be lost. The striping configuration of the RAID <NUM> needs to be improved.

To address one or more aforementioned issues, the present disclosure introduces a solution in which RAID technologies (e.g., RAID <NUM>) can be used to recover more than one compromised data portion laterally and vertically. In these implementations, two adjacent gate conductive layers are defined as a layer, and each memory block includes a plurality of layers in the vertical direction. Compared to a RAID <NUM> in which a stripe includes data portions distributed laterally and vertically in memory blocks across the planes and the dies, the provided method employs stripes that are shorter. Temporary parity data are generated for each respective stripe. The temporary parity data is stored in a temporary storage unit and used for recovering the compromised data portion in the respective stripe. The temporary parity data can be used to generate the parity data set for the stripes in all the planes and dies. When the temporary parity data is no longer needed, e.g., no programming failure detected or all the programming failures recovered, the temporary parity data can be removed from the temporary storage unit. No additional storage space is needed in the NAND memory for the temporary parity data portions. The error correction capability of RAID <NUM> can be improved without adding complexity to the algorithm. In an example, for one memory block in <NUM> planes and <NUM> dies, the error correction capability of RAID <NUM> can be described as (<NUM>+X), in which <NUM> represents the number of data portions stored with memory data, and X represents the number of data portions in which programming failures occur, where X is a positive integer greater than <NUM>. That is, for the same number of memory cells in the apparatuses, more compromised memory data can be recovered. The data reliability of the apparatuses can be improved.

To improve the error correction capability, various striping configurations have been proposed. These striping configurations can be used in the RAID algorithm such that compromised data portions caused by multi-plane failure, SSG leakage failure, or both can be recovered. In some implementations, a stripe includes data portions distributed in a plurality of layers in memory blocks in a respective plane and in all dies, and a plane temporary parity data portion is determined for each stripe. The stripe does not include data portions in other planes. In case of programming failures detected, e.g., due to multi-plane failure, the plane parity portion of a respective stripe can be used to locate and recover the compromised data portion. In some implementations, a stripe includes data portions distributed in a single layer in memory blocks in all planes and in all dies, and a layer parity data portion is determined for each stripe. The stripe does not include data portions in other layers. A stripe can be formed in each single layer in the memory blocks. In case of programming failures detected, e.g., due to SSG leakage failure, the layer parity portion of a respective stripe can be used to locate and recover the compromised data portion. In some implementations, a stripe includes data portions distributed in a single layer in memory blocks in a single plane and in all dies, and a parity data portion is generated for each stripe. In case of programming failures detected, e.g., due to SSG leakage failure and/or multi-plane failure, the parity portion of a respective stripe can be used to locate and recover the compromised data portion.

<FIG> illustrates a schematic diagram of an apparatus <NUM> in which the provided methods are operated, according to some aspects of the present disclosure. As shown in <FIG>, apparatus <NUM> includes a host processor <NUM>, a Flash memory controller <NUM>, a random-access memory (RAM) <NUM>, and NAND memory <NUM> on a printed circuit board (PCB) <NUM>. Each one of host processor <NUM>, Flash memory controller <NUM>, NAND memory <NUM>, and RAM <NUM> is a discrete chip with its own packaging and mounted on PCB <NUM>. Host processor <NUM> is a specialized processor for performing data processing of NAND memory <NUM>. For example, host processor <NUM> may include a central processing unit (CPU) and/or a system-on-chip (SoC), such as an application processor. Data is transmitted between host processor <NUM> and Flash memory controller <NUM> and between host processor <NUM> and RAM <NUM> each through a respective interlink, such as a processor bus. Host processor <NUM> may thus control the operations of RAM <NUM> and Flash memory controller <NUM>. NAND memory <NUM> may include arrays of memory cells that are configured in a RAID. NAND memory <NUM> is a 3D NAND memory or a 2D NAND memory, which transfers data with Flash memory controller <NUM> through another interlink. RAM <NUM> may include any suitable static random-access memory (SRAM) and/or dynamic random-access memory (DRAM).

Flash memory controller <NUM> can manage the data stored in flash memory (either NAND Flash memory or NOR Flash memory) and communicate with host processor <NUM>. In some implementations, Flash memory controller <NUM> is designed for operating in a low duty-cycle environment like Secure Digital (SD) cards, Compact Flash (CF) cards, USB Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, Flash memory controller <NUM> is designed for operating in a high duty-cycle environment like solid-state drives (SSDs) or embedded Multi-Media-Cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Flash memory controller <NUM> can be configured to control operations of the NAND memory <NUM>, such as read, write, erase, and program operations. Flash memory controller <NUM> can also be configured to manage various functions with respect to the data stored or to be stored in NAND memory <NUM> including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, and so on. In some implementations, Flash memory controller <NUM> is further configured to process error correction codes (ECCs) with respect to the data read from or written to NAND memory <NUM>. Any other suitable functions may be performed by Flash memory controller <NUM> as well, for example, formatting the Flash memory.

<FIG> illustrates an exemplary implementation of Flash memory controller <NUM>, according to some implementations. Flash memory controller <NUM> may control the operations of NAND memory <NUM> by generating control signals to control the striping, computing, and storage of memory data in NAND memory <NUM>. Consistent with the present disclosure, Flash memory controller <NUM> may receive signals from host processor <NUM> for the operation of NAND memory <NUM>. In some implementations, Flash memory controller <NUM> may include a processor <NUM>, a memory <NUM>, and a storage <NUM>. In some embodiments, Flash memory controller <NUM> may have different modules in a single device, such as an integrated circuit (IC) chip (implemented as, for example, an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA)), or separate devices with dedicated functions. In some embodiments, components of Flash memory controller <NUM> may be in an integrated device, or distributed at different locations but communicate with each other through a network.

Processor <NUM> may include any appropriate type of general-purpose or special-purpose microprocessor, digital signal processor, or microcontroller. Processor <NUM> may be configured as a stand-alone processor module dedicated to analyzing signals (e.g., signals from host processor <NUM>) and/or controlling the scan schemes. Alternatively, processor <NUM> may be configured as a shared processor module for performing other functions unrelated to signal analysis/scan scheme control. Although not shown in <FIG>, processor <NUM> may include multiple functional units or modules that can be implemented using software, hardware, middleware, firmware, or any combination thereof. The multiple functional units may perform striping, computing, and controlling the storage of parity data of the present disclosure based on signals from host processor <NUM> or any pre-stored control data.

Storage <NUM> and memory <NUM> may include any appropriate type of mass storage provided to store any type of information that processor <NUM> may need to operate. Memory <NUM> and/or storage <NUM> may be volatile or non-volatile, magnetic, semiconductor-based, tape-based, optical, removable, non-removable, or other type of storage device or tangible (i.e., non-transitory) computer-readable medium including, but not limited to, a ROM, a flash memory, a dynamic RAM, a static RAM, a hard disk, an SSD, an optical disk, etc. Storage <NUM> and/or memory <NUM> may be configured to store one or more computer programs that may be executed by processor <NUM> to perform functions disclosed herein. For example, memory <NUM> and/or storage <NUM> may be configured to store program(s) that may be executed by processor <NUM> to form RAID stripes, compute parity data, and control the storage of parity data. In some implementations, storage <NUM> and memory <NUM> may also be configured to store/cache information and data received and/or used by processor <NUM>. For instance, storage <NUM> and memory <NUM> may store/cache data received from host processor <NUM>, and/or data (e.g., temporary parity data) generated during the RAID operation.

Referring back to <FIG>, Flash memory controller <NUM> can include a host interface (I/F) operatively coupled to host processor <NUM>, for example, through a processor bus, and configured to receive the instruction from host processor <NUM>. The host I/F can include a serial attached SCSI (SAS), parallel SCSI, PCI express (PCIe), NVM express (NVMe), advanced host controller interface (AHCI), to name a few. Flash memory controller <NUM> can also include a management module and a NAND memory interface (I/F). In some implementations, the management module is operatively coupled to the host I/F and the NAND memory I/F and configured to generate one or more control signals to control operations (e.g., read, write, erase, and program operations) of NAND memory <NUM> based on the instruction received from host processor <NUM> and send the control signals to the NAND memory I/F. For example, the management module determines stripes in NAND memory <NUM>, and performs computation to determine temporary parity data and recover memory data in stripes. The management module can be any suitable control and state machine. In some implementations, the NAND memory I/F is configured to transmit the control signals to NAND memory <NUM> and receive the status signals from NAND memory <NUM>. The status signal can indicate the status of each operation performed by NAND memory <NUM> (e.g., failure, success, delay, etc.), which can be sent back to the management module as feedbacks. The NAND memory I/F can include single data rate (SDR) NAND Flash interface, open NAND Flash interface (ONFI), Toggle double data rate (DDR) interface, to name a few.

NAND memory <NUM> be a NAND Flash memory having an array of NAND memory cells in the form of an array of 3D NAND memory cells. In some implementations, the array of NAND memory cells is an array of 3D NAND memory cells, formed by the intersections of word lines and memory strings, each of which extends vertically above a substrate through a memory stack. Depending on the 3D NAND technology (e.g., the number of layers/tiers in the memory stack), a memory string typically includes <NUM> to <NUM> NAND memory cells, each of which includes a floating-gate transistor or a charge-trapping transistor.

NAND memory cells can be organized into pages, which are then organized into memory blocks, in which each NAND memory cell is electrically connected to a separate line called a bit line (BL). All cells with the same position in the NAND memory cell can be electrically connected through the control gates by a word line (WL), i.e., a conductive gate layer. Each word line may be electrically coupled with the control gates of memory cells in a plurality of pages. In some implementations, a plane contains a certain number of memory blocks that are electrically connected through the same bit line. <FIG> illustrates a schematic diagram of a cross-sectional view of NAND memory <NUM> in a memory block in a lateral direction, according to some implementations. As shown in <FIG>, a plurality of gate conductive layers, i.e., GCL1, GCL2,. , are arranged in a memory block in the vertical direction. Each of the gate conductive layers extend laterally. Memory cells formed by a single gate conductive layer and memory strings form a page. Each gate conductive layer, in one memory block, can be coupled to memory cells of multiple pages. That is, one memory block can include multiple pages on a single level. Two adjacent gate conductive layers form a layer, defined in the present disclosure. For example, GCL1 and GCL2 form layer <NUM>, GCL3 and GCL4 form layer <NUM>, etc. SSGs can each be electrically coupled to a plurality of gate conductive layers (e.g., a plurality of memory cells) in the vertical direction. In some implementations, NAND memory <NUM> includes multiple dies, each having at least one plane. Examples of NAND memory <NUM> are illustrated in detail in <FIG>, <FIG> and <FIG>, and <FIG> and the related descriptions.

Host processor <NUM> may coordinate operations in different modules/parts in apparatus <NUM> based on data and/or signals transmitted from Flash memory controller <NUM>. Host processor <NUM> may control the operation of RAM <NUM> based on data and/or signals transmitted from Flash memory controller <NUM>. For example, host processor <NUM> may receive temporary parity data from Flash memory controller <NUM> and store the temporary parity data in RAM <NUM> for computation and/or reference. Host processor <NUM> may also remove the temporary parity data from RAM <NUM> when the temporary parity data is no longer needed.

In another example (not shown), the chips of Flash memory controller <NUM> and NAND memory <NUM> may be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package, and electrically connected through wire bonding. Flash memory controller <NUM> then may transfer data with host processor <NUM> through an interlink, such as a processor bus, which is driven by a software driver, such as a UFS driver software or an MMC driver software.

In some implementations, apparatus <NUM> also includes a peripheral circuit (not shown, also known as the control and sensing circuits) that includes any suitable digital, analog, and/or mixed-signal circuits used for facilitating the operations of NAND memory <NUM>. For example, the peripheral circuit can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors).

RAID algorithm may be performed on the memory data of NAND memory <NUM>, configured into a plurality of stripes, to create data redundancy. A stripe may include a plurality of data portions, distributed in desired physical locations (e.g., pages, memory blocks, etc.) of NAND memory <NUM>. Temporary parity data can be generated for detecting and/or recovering compromised memory data of a respective stripe. Optionally, the temporary parity data can be retained or removed. Overall parity data may be generated for the memory data in all the stripes. <FIG>, <FIG> and <FIG>, and <FIG> illustrate three different striping configurations in respective NAND memories and corresponding RAID algorithm, according to some implementations. <FIG> illustrate temporary parity data storage for respective RAID algorithm, according to some aspects of the present disclosure. <FIG> each illustrates a flowchart of a method for striping and performing data recovery using RAID algorithm in a respective striping configuration, according to some aspects of the present disclosure. It is understood that the operations shown in methods <NUM>, <NUM>, and <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

NAND memories <NUM>, <NUM>, and <NUM> in <FIG>, <FIG> and <FIG>, and <FIG> are each an example of NAND memory <NUM> in <FIG>. The operations on NAND memories <NUM>, <NUM>, and <NUM> may be controlled by a Flash memory controller, e.g., Flash memory controller <NUM>. For ease of illustration, NAND memories <NUM>, <NUM>, and <NUM> may each include N dies (e.g., DIE<NUM>, DIE<NUM>,. , DIEN), where N is a positive integer of at least <NUM>. Each die may be laterally divided into M planes (e.g., PLN<NUM>, PLN<NUM>,. , PLNM), M being a positive integer of at least <NUM>. In some implementations, M is equal to or greater than <NUM>. In some implementations, M is greater than or equal to <NUM>, such as <NUM> or <NUM>. Each plane may be laterally divided into X memory blocks (B<NUM>, B<NUM>,. , BX), X being a positive integer of at least <NUM>. Each memory block may include a plurality of memory cells formed by the intersections of a number of gate conductive layers (e.g., extending laterally) and a plurality of memory strings (e.g., extending vertically). The number of gate conductive layers, arranged vertically, in each memory block may be equal to or greater than <NUM>. In some implementations, gate conductive layers of the same level in adjacent memory blocks may be in contact with each other. Each memory block may be laterally divided into a plurality of pages. Memory data may be stored in the memory cells in pages, memory blocks, planes, and dies. In some implementations, M is equal to <NUM>. In some implementations, N is equal to <NUM>. In some implementations, the number of gate conductive layers in a memory block is equal to or greater than <NUM>.

<FIG> illustrates a striping configuration for a RAID algorithm employed in NAND memory <NUM>, and <FIG> illustrates a temporary storage unit <NUM> employed for storing temporary parity data generated according to the RAID algorithm, according to some aspects of the present disclosure. The RAID algorithm can be a RAID <NUM>. In some implementations, the striping in NAND memory <NUM> can be used to recover memory data in a multi-plane failure. <FIG>, <FIG>, and <FIG> are described together.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which J layers are determined in each memory block in the M planes and the N dies, where J is a positive integer of at least <NUM>. Each layer includes a pair of adjacent gate conductive layers. <FIG> illustrates a corresponding configuration for method <NUM>.

As shown in <FIG>, in memory block B<NUM> of each plane (e.g., PLN<NUM>, PLN<NUM>,. , PLNM), J layers, L<NUM>, L<NUM>,. , LJ, may be determined in each die DIE<NUM>, DIE<NUM>,. Each layer may include a pair of adjacent gate conductive layers. In some implementations, memory block B1 includes at least <NUM> gate conductive layers, and J is equal to or greater than <NUM>. Flash memory controller <NUM> may perform this operation.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which M stripes are determined, each stripe being configured in a respective plane.

As shown in <FIG>, M stripes, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(M-<NUM>), and <NUM>-M, may be determined. Each of the M stripes may correspond to a respective plane and may include J×N data portions that are stored in the J layers in a respective plane in all N dies. Each data portion may include memory data stored in the memory cells formed by the intersections of the respective layer (i.e., the pair of adjacent gate conductive layers) in the respective memory block and the memory strings in the memory block. For example, stripe <NUM>-<NUM> may correspond to plane PLN<NUM>, and may include J×N data portions stored in the J layers in memory blocks B<NUM> in the N dies (i.e., DIE<NUM>-DIEN), and stripe <NUM>-M may correspond to plane PLNM, and may include J×N data portions stored in the J layers in memory blocks B<NUM> in the N dies (i.e., DIE<NUM>-DIEN). Each data portion in stripe <NUM>-<NUM> includes the memory data stored in the memory cells formed by the two gate conductive layers in layer L<NUM> and the memory strings in the respective memory blocks B<NUM> in PLN<NUM>. In other words, memory data stored in layer L<NUM> in memory block B<NUM> of plane PLN<NUM> in die DIE<NUM> may form a first data portion of stripe <NUM>-<NUM>, memory data stored in layer L<NUM> in memory block B<NUM> of plane PLN<NUM> in die DIE<NUM> may form a second data portion of stripe <NUM>-<NUM>,. , memory data stored in layer LJ in memory block B<NUM> of plane PLN<NUM> in die DIE<NUM> may form a (J×N-(N-<NUM>))th data portion of stripe <NUM>-<NUM>,. , and memory data stored in layer LJ in memory block B<NUM> of plane PLN<NUM> in die DIEN may form a (J×N)th data portion of stripe <NUM>-<NUM>. In some implementations, Flash memory controller <NUM> may perform this operation.

As shown in <FIG>, the M stripes <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(M-<NUM>), and <NUM>-M are each configured in the respective plane, and does not include data portions in another plane. That is, the data portions of each stripe are configured only in the respective plane and are not in another plane, e.g., not "across planes. " The striping configuration may ensure that the programming failure occurs in the parallel programming of multiple planes does not impact more than one data portion in a single stripe. That is, the multi-plane failure can result in at most one compromised data portion in a single stripe. Thus, more than one compromised data portion in a stripe, caused by multi-plane failure, can be avoided. The compromised data portion can thus be recovered using the temporary parity data of the stripe. Details are provided below.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which M plane data portions are determined for the M stripes.

As shown in <FIG>, M plane parity data portions, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(M-<NUM>), <NUM>-M, may be determined for the M stripes. Each of the plane parity data portions may be generated based on the data portions of the respective stripe. In some implementations, an exclusive or (XOR) operation is performed amongst the J×N data portions of each stripe to generate the respective plane parity data portion. For example, plane parity data portion <NUM>-<NUM> may be the result of the XOR operation on all J×N data portions in stripe <NUM>-<NUM>, plane parity data portion <NUM>-<NUM> may be the result of the XOR operation on all J×N data portions in stripe <NUM>-<NUM>,. , plane parity data portion <NUM>-(M-<NUM>) may be the result of the XOR operation on all J×N data portions in stripe <NUM>-(M-<NUM>), and plane parity data portion <NUM>-M may be the result of the XOR operation on all J×N data portions in stripe <NUM>-M. In some implementations, Flash memory controller <NUM> may perform this operation.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which a temporary storage unit is controlled to store the M plane parity data portions.

As shown in <FIG>, a temporary storage unit <NUM> is controlled to store each of the M plane parity data portions <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(M-<NUM>), <NUM>-M. <FIG> illustrates a diagram of the temporary storage unit <NUM> in which the M plane parity data portions are stored. Temporary storage unit <NUM> may be a storage space in any suitable medium that allows the M plane parity data portions to be stored for a desirable amount of time. In various implementations, temporary storage unit <NUM> may be a partition in RAM <NUM> and/or a dedicated storage space in NAND memory <NUM>. In some implementations, temporary storage unit <NUM> may be in memory <NUM> and/or storage <NUM>. In some implementations, temporary storage unit <NUM> may be an external storage space coupled to apparatus <NUM>. In some implementations, temporary storage unit <NUM> is located in RAM <NUM>. In some implementations, the duration for which the M plane parity data portions are stored is sufficiently long for Flash memory controller <NUM> to identify any programming failure, locate the compromised data portion, and use the respective plane parity data portion to recover the compromised data portion. In some implementations, the M plane parity data portions are removed after the recovery operation is completed or no programming failure is detected. In some other implementations, the M plane parity data portions are retained. In some implementations, Flash memory controller <NUM> may perform this operation.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which any programming failure due to multi-plane failure is being detected. If a programming failure is detected, method <NUM> proceeds to operation <NUM>, in which the memory data stored in the compromised data portion in which the multi-plane failure occurred is recovered using the respective plane parity data portion. After the recovery of the compromised data portion, method <NUM> proceeds to operation <NUM>, in which a parity data set is generated from the M plane parity data portions. If no programming failure is detected, method <NUM> proceeds to operation <NUM>.

Flash memory controller <NUM> may determine whether any multi-plane failure occurs during the parallel programming of planes PLN<NUM>-PLNM. As previously explained, the multi-plane failure due to parallel programming of multiple planes may cause the memory data in memory cells at the same location of these planes to be compromised. As a result, data portions at the same location of one or more stripes (i.e., <NUM>-<NUM>,. , <NUM>-M) can be compromised. In some implementations, Flash memory controller <NUM> may use the plane parity data portion of each stripe to determine whether any multi-plane failure occurred in a data portion in the respective stripe. In some implementations, Flash memory controller <NUM> may perform an XOR operation amongst the data portions of the respective stripe and the plane parity data portion of the respective stripe to detect and identify the compromised data portion. The location of the compromised data portion in each (if any) stripe may be determined.

If a compromised data portion is detected in a stripe, Flash memory controller <NUM> may generate a replacement data portion based on the rest of the data portions (e.g., the data portions that are not compromised) in the stripe and the plane parity data portion of the stripe to generate the replacement data portion. In some implementations, the generation of the replacement data portion includes performing an XOR operation amongst the rest of the data portions in the stripe and the plane parity data portion of the stripe. Flash memory controller <NUM> may recover the compromised data portion with the replacement data portion such that the memory data in the compromised data portion can be retained. In some implementations, Flash memory controller <NUM> may access the plane parity data portions from temporary storage unit <NUM> if computation is needed, e.g., for identifying and locating a compromised data portion and/or generating a replacement data portion.

A parity data set <NUM> that represents the parity/redundancy data of the J layers in memory block B1 in the M planes and N dies, e.g., the J×N×M data portions, may be generated from the M plane parity data portions. In some implementations, parity data set <NUM> is obtained by performing an XOR operation amongst the M plane parity data portions. Parity data set <NUM> may be stored in a permanent storage unit (e.g., a plurality of memory cells) in NAND memory <NUM>. In some implementations, parity data set <NUM> may be stored in a data portion in stripe <NUM>-M. Flash memory controller <NUM> may perform this operation.

In some implementations, Flash memory controller <NUM> may continue to perform operations <NUM>-<NUM> for the remaining layers in memory block B1 in the M planes and N dies. For example, plane parity data portions <NUM>-<NUM>,. , <NUM>-M, corresponding to layers L(J+<NUM>) to LK of memory block B1, may be stored in temporary storage unit <NUM> for computation and/or reference, as shown in <FIG>. The same operations may also be performed for other memory blocks in the M planes and the N dies.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which the M plane parity data portions are removed from the temporary storage unit.

In some implementations, after the recovery of the compromised data portion(s), Flash memory controller <NUM> may remove the M plane parity data portions from temporary storage unit <NUM>. In some implementations, if no programming failure is detected, Flash memory controller <NUM> removes the M plane parity data portions from temporary storage unit <NUM>. By recovering compromised data portion(s) in different planes using respective plane parity data portions, more than one compromised data portion at the same location in different planes, caused by the multi-plane failure, can be recovered. Compared with a RAID method in which one stripe includes data portions across the planes, the number of data portions that can be recovered/protected in these planes is increased, e.g., to more than <NUM>.

<FIG> and <FIG> illustrate a striping configuration for a RAID algorithm employed in NAND memory <NUM>, and <FIG> illustrates a temporary storage unit <NUM> employed for storing temporary parity data generated according to the RAID algorithm, according to some aspects of the present disclosure. The RAID algorithm can be a RAID <NUM>. In some implementations, the striping in NAND memory <NUM> can be used to recover memory data in an SSG leakage failure. <FIG>, <FIG>, <FIG>, and <FIG> are described together.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which J layers are determined in memory blocks in the M planes and the N dies, J being a positive integer of at least <NUM>. Each layer includes a pair of adjacent gate conductive layers. <FIG> and <FIG> illustrate a corresponding configuration for method <NUM>. Flash memory controller <NUM> may perform this operation. This operation can be similar or the same as operation <NUM>, and the detailed description is not repeated herein.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which J stripes are determined, each stripe being configured in a single layer in the M planes and N dies.

As shown in <FIG> and <FIG>, J stripes, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(J-<NUM>), and <NUM>-J, may be determined. Each of the J stripes may correspond to a respective one of the J layers. Each of the J stripes may include M×N data portions that are stored in the respective single layer in all planes and all dies. Each data portion may include memory data stored in the memory cells formed by the intersections of the respective layer (i.e., the pair of adjacent gate conductive layers) in the respective memory block and the memory strings in the memory block. For example, stripe <NUM>-<NUM> may correspond to layer L<NUM>, and may include M×N data portions stored in layer L<NUM> in memory block B<NUM> in the M planes (i.e., PLN<NUM>-PLNM) and the N dies (i.e., DIE<NUM>-DIEN), and stripe <NUM>-J may correspond to layer LJ, and may include M×N data portions stored in layer LJ in memory block B<NUM> the M planes and the N dies. Each data portion in stripe <NUM>-<NUM> includes the memory data stored in the memory cells formed by the two gate conductive layers and the memory strings in the respective memory block B1 in the M planes and the N dies. In other words, memory data stored in layer L<NUM> in memory block B<NUM> of plane PLN<NUM> in die DIE<NUM> may form a first data portion of stripe <NUM>-<NUM>, memory data stored in layer L<NUM> in memory block B<NUM> of plane PLN<NUM> in die DIE<NUM> may form a (N+<NUM>)th data portion of stripe <NUM>-<NUM>,. , memory data stored in layer L<NUM> in memory block B<NUM> of plane PLNM in die DIE<NUM> may form an (M×N-(N-<NUM>))th data portion of stripe <NUM>-<NUM>,. , and memory data stored in layer L<NUM> in memory block B<NUM> of plane PLNM in die DIEN may form a (M×N)th data portion of stripe <NUM>-<NUM>. In some implementations, Flash memory controller <NUM> may perform this operation.

As shown in <FIG> and <FIG>, the J stripes <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(J-<NUM>), and <NUM>-J are each configured in the respective layer, and are not configured in another layer. That is, each of the J stripes includes data portions in only in a single layer in the memory blocks and does not include data portions in another layer, e.g., not "across layers. " The striping configuration may ensure that SSG leakage failure does not cause more than one compromised data portions in a single stripe. The SSG leakage failure can at most cause compromised data portions in different layers, each in a different stripe. Thus, more than two compromised data portions in a single stripe, caused by SSG leakage failure, can be avoided. The compromised data portion can each be recovered using the parity data of the stripe. Details are provided below.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which J layer parity data portions are determined for the J stripes.

As shown in <FIG> and <FIG>, J layer parity data portions, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(J-<NUM>), <NUM>-J, may be determined for the J stripes. Each of the layer parity data portions may be generated based on the data portions of the respective stripe. In some implementations, an exclusive or (XOR) operation is performed amongst the M×N data portions of each stripe to generate the respective layer parity data portion. For example, layer parity data portion <NUM>-<NUM> may be the result of the XOR operation on all M×N data portions of stripe <NUM>-<NUM>, layer parity data portion <NUM>-<NUM> may be the result of the XOR operation on all M×N data portions of stripe <NUM>-<NUM>,. , layer parity data portion <NUM>-(J-<NUM>) may be the result of the XOR operation on all M×N data portions of stripe <NUM>-(J-<NUM>), and layer parity data portion <NUM>-J may be the result of the XOR operation on all M×N data portions of stripe <NUM>-J. In some implementations, Flash memory controller <NUM> may perform this operation.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which a temporary storage unit is controlled to store the J layer parity data portions.

As shown in <FIG> and <FIG>, a temporary storage unit <NUM> is controlled to store each of the J layer parity data portions <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(J-<NUM>), <NUM>-J. <FIG> illustrates a diagram of the temporary storage unit <NUM> in which the J layer parity data portions are stored. Temporary storage unit <NUM> may be a storage space in any suitable medium that allows the J layer parity data portions to be stored for a desirable amount of time. In various implementations, temporary storage unit <NUM> may be a partition in RAM <NUM> and/or a dedicated storage space in NAND memory <NUM>. In some implementations, temporary storage unit <NUM> may be an external storage space coupled to apparatus <NUM>. In some implementations, temporary storage unit <NUM> is located in RAM <NUM>. In some implementations, the duration for which the J layer parity data portions are stored is sufficiently long for Flash memory controller <NUM> to identify any programming failure, locate the compromised data portion, and use the respective layer parity data portion to recover the compromised data portion. In some implementations, the J layer parity data portions are removed after the recovery operation is completed or no programming failure is detected. In some other implementations, the J layer parity data portions are retained. In some implementations, Flash memory controller <NUM> may perform this operation.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which any programming failure, e.g., due to SSG leakage failure, is being detected. If a programming failure is detected, method <NUM> proceeds to operation <NUM>, in which the memory data stored in the compromised data portion in which the programming failure occurred is recovered using the respective layer parity data portion. After the recovery of the compromised data portion, method <NUM> proceeds to operation <NUM>, in which a parity data set is generated from the J layer parity data portions. If no programming failure is detected, method <NUM> proceeds to operation <NUM>.

Flash memory controller <NUM> may determine whether any programming failure due to SSG leakage failure occurred. As previously explained, the programming failure due to SSG leakage failure may cause the memory data in memory cells at the same location of different levels to be compromised. However, the striping illustrated in <FIG> and <FIG> can ensure only a single data portion, if any, in a stripe can be compromised due to SSG leakage failure. The SSG leakage failure can at most cause data portions in different stripes to be compromised. In some implementations, Flash memory controller <NUM> may use the layer parity data portion of each stripe to determine whether any programming failure occurred in a data portion in the respective stripe. In some implementations, Flash memory controller <NUM> may perform an XOR operation amongst the data portions of the respective stripe and the layer parity data portion of the respective stripe to detect and identify the compromised data portion. The location of the compromised data portion in each (if any) stripe may be determined.

If a compromised data portion is detected in a stripe, Flash memory controller <NUM> may generate a replacement data portion based on the rest of the data portions (e.g., the data portions that are not compromised) in the stripe and the layer parity data portion of the stripe to generate the replacement data portion. In some implementations, the generation of the replacement data portion includes performing an XOR operation amongst the rest of the data portions in the stripe and the layer parity data portion of the stripe. Flash memory controller <NUM> may recover the compromised data portion with the replacement data portion such that the memory data in the compromised data portion can be retained. In some implementations, Flash memory controller <NUM> may obtain the layer parity data portions from temporary storage unit <NUM> if computation is needed, e.g., for identifying and locating a compromised data portion and/or generating a replacement data portion.

A parity data set <NUM> that represents the parity/redundancy data of the J layers in memory block B1 in the M planes and N dies, e.g., the J×N×M data portions, may be generated from the J layer parity data portions. In some implementations, parity data set <NUM> is obtained by performing an XOR operation amongst the J layer parity data portions. Parity data set <NUM> may be stored in a permanent storage unit (e.g., a plurality of memory cells) in NAND memory <NUM>. Flash memory controller <NUM> may perform this operation.

In some implementations, Flash memory controller <NUM> may continue to perform operations <NUM>-<NUM> for the remaining layers in memory block B1 in the M planes and N dies. For example, layer parity data portions <NUM>-(J+<NUM>),. , <NUM>-(K-<NUM>), <NUM>-K, corresponding to layers L(J+<NUM>) to LK of memory blocks B1, may be stored in temporary storage unit <NUM> for computation and/or reference. The same operations may also be performed for other memory blocks in the M planes and the N dies.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which the J layer parity data portions are removed from the temporary storage unit.

In some implementations, after the recovery of the compromised data portion(s) and the generation of the parity data set, Flash memory controller <NUM> may remove the J layer parity data portions from temporary storage unit <NUM>. In some implementations, if no programming failure is detected, Flash memory controller <NUM> removes the J layer parity data portions from temporary storage unit <NUM>. By recovering compromised data portion(s) in different layers using respective layer parity data portions, more than one compromised data portions, caused by the programming failure due to SSG leakage failure at the same location in more than one layers, can be recovered. Compared with a RAID method in which one stripe includes data portions across the layers, the number of data portions that can be recovered/protected in these layers is increased, e.g., to more than <NUM>.

<FIG> illustrate a striping configuration for a RAID algorithm employed in NAND memory <NUM>, <FIG> illustrates a temporary storage unit <NUM> employed for storing temporary parity data generated according to the RAID algorithm, according to some aspects of the present disclosure, and <FIG> illustrates a second temporary storage unit <NUM> employed for storing temporary parity data generated according to the RAID algorithm, according to some implementations. The RAID algorithm can be a RAID <NUM>. In some implementations, the striping configuration in NAND memory <NUM> can be used to recover memory data compromised by an SSG leakage failure, a multi-plane failure, or both. <FIG>, <FIG>, <FIG>, and <FIG> are described together.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which J layers are determined in each memory block in the M planes and the N dies, J being a positive integer of at least <NUM>. Each layer includes a pair of adjacent gate conductive layers. <FIG> illustrate a corresponding configuration for method <NUM>. Flash memory controller <NUM> may perform this operation. This operation can be similar or the same as operation <NUM>, and the detailed description is not repeated herein.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which M sets of stripes are determined, each set having J stripes. Each of the M sets corresponds to a respective one of the M planes. Each of the J stripes is configured in a single layer in the respective plane in the N dies.

As shown in <FIG>, J×M stripes, configured in M sets (i.e., set <NUM>,. , set <NUM>) of stripe, each set having J stripes (i.e., stripe <NUM>, stripe <NUM>,. , stripe J), may be determined. Each of the M sets may correspond to a respective one of the M planes. Each of the J stripes may correspond to a respective one of the J layers in the respective plane. Each of the J stripes may include N data portions that are stored in the respective single layer in the N dies. Each data portion may include memory data stored in the memory cells formed by the intersections of the respective layer (i.e., the pair of adjacent gate conductive layers) in the respective memory block and the memory strings in the memory block. For example, stripe <NUM> of set <NUM> may correspond to layer L<NUM> in memory blocks B<NUM> in plane PLN<NUM>, and may include N data portions stored in layer L<NUM> in memory blocks B<NUM> in plane PLN<NUM> and the N dies (i.e., DIE<NUM>-DIEN); and stripe J of set <NUM> may correspond to layer LJ in memory blocks B<NUM> in plane PLNM, and may include N data portions stored in layer LJ in memory blocks B<NUM> in plane PLNM and the N dies. Each data portion in a stripe includes the memory data stored in the memory cells formed by the two gate conductive layers and the memory strings in the respective memory block B1 in the respective planes and the N dies. In other words, for each one of the M sets of stripes, memory data stored in layer L<NUM> in memory block B<NUM> in die DIE<NUM> may form a first data portion of stripe <NUM>, and memory data stored in layer L<NUM> in memory block B<NUM> in die DIEN may form an Nth data portion of stripe <NUM>,. , memory data stored in layer LJ in memory block B<NUM> in die DIE<NUM> may form a first data portion of stripe J, and memory data stored in layer LJ in memory block B<NUM> in die DIEN may form an Nth data portion of stripe J. In some implementations, Flash memory controller <NUM> may perform this operation.

As shown in <FIG>, the M sets of stripes are each configured in the respective plane, and the J stripes in each set are each configured in a single respective layer. That is, each stripe is configured in a single plane and a single layer. The data portions of each stripe are thus configured only in a single layer and a single plane, and are not in another layer or another plane, e.g., not "across planes" or "across layers. " The striping may ensure that programming failure, e.g., multi-plane failure and/or SSG leakage failure, can only compromise a single data portion in a stripe. Multi-plane failure and/or SSG leakage failure can at most compromise memory data in different stripes. Thus, more than one compromised data portion in a stripe, caused by programming failure such as SSG leakage failure and/or multi-plane failure, can be avoided, and the compromised data portion can be recovered using the respective parity data of the stripe. Details are provided below.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which M sets of data parity portions, each set having J parity data portions, are determined for the M sets of stripes.

As shown in <FIG>, M sets of parity data portions, each set having J parity data portions, may be determined. Each set of parity data portions may correspond to a respective set of stripes, and each of the J parity portions in a set may correspond to a respective stripe in the respective set. As shown in <FIG>, a first set of parity data portions may include parity data portions <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-J; an (M-<NUM>)th set of parity data portions may include parity data portions <NUM>(M-<NUM>)-<NUM>, <NUM>(M-<NUM>)-<NUM>,. , <NUM>(M-<NUM>)-(J-<NUM>), <NUM>(M-<NUM>)-J; and an Mth set of parity data portions may include parity data portions <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(J-<NUM>), <NUM>-J. Each of the parity data portions may be generated based on the data portions of the respective stripe. In some implementations, an exclusive or (XOR) operation is performed amongst the N data portions of each stripe to generate the respective parity data portion. For example, parity data portion <NUM>-<NUM> may be the result of the XOR operation on all N data portions of stripe <NUM> in set <NUM> of stripes, parity data portion <NUM>-<NUM> may be the result of the XOR operation on all N data portions of stripe <NUM> of set <NUM> of stripes,. , parity data portion <NUM>-<NUM> may be the result of the XOR operation on all N data portions of stripe <NUM> of set <NUM> of stripes, and parity data portion <NUM>-J may be the result of the XOR operation on all N data portions of stripe J of set <NUM> of stripes. In some implementations, Flash memory controller <NUM> may perform this operation.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which a temporary storage unit is controlled to store the M sets of parity data portions.

As shown in <FIG>, a temporary storage unit <NUM> is controlled to store each of the M sets of parity data portions. <FIG> illustrates a diagram of the temporary storage unit <NUM> in which the M sets of parity data portions are stored. Temporary storage unit <NUM> may be a storage space in any suitable medium that allows the parity data portions to be stored for a desirable amount of time. In various implementations, temporary storage unit <NUM> may be a partition in RAM <NUM> and/or a dedicated storage space in NAND memory <NUM>. In some implementations, temporary storage unit <NUM> is located in RAM <NUM>. In some implementations, the duration for which the M sets of parity data portions are stored is sufficiently long for Flash memory controller <NUM> to identify any programming failure, locate the compromised data portion, and use the respective layer parity data portion to recover the compromised data portion. In some implementations, the M sets of parity data portions are removed after the recovery operation is completed or no programming failure is detected. In some other implementations, the M sets of parity data portions are retained. In some implementations, Flash memory controller <NUM> may perform this operation.

In some implementations, for each set of parity data portions, Flash memory controller <NUM> may compute a temporary parity data portion. M temporary parity data portions may be determined. In some implementations, for each set of stripes, Flash memory controller <NUM> computes parity data portions sequentially, e.g., form the parity data portion of stripe <NUM> to the parity data portion of stripe J, to obtain the M sets of parity data portions. For each set of parity data portions, Flash memory controller <NUM> may perform an XOR operation between the second parity data portion (e.g., of stripe <NUM>) and the first parity data portion (e.g., of stripe <NUM>) to generate a temporary parity portion; and may perform an XOR operation between the third parity data portion (e.g., of stripe <NUM>) and the temporary parity data portion to generate a new temporary parity data portion. Flash memory controller <NUM> may store the temporary parity data portion in a second temporary storage unit (now shown), and replace it with the new temporary parity data portion. The second temporary storage unit may be a partition in RAM <NUM> and/or a dedicated storage space in NAND memory <NUM>. In some implementations, the second temporary storage unit may be an external storage space coupled to apparatus <NUM>. In some implementations, the second temporary storage unit is located in RAM <NUM>. In some implementations, the second temporary storage unit is in the same medium as temporary storage unit <NUM>. Flash memory controller <NUM> may continue to compute the parity data portion of each of the rest of the J stripes, and generate a new temporary parity data portion for each of the rest of the J stripes. Flash memory controller <NUM> may store the J parity data portions of each set in temporary storage unit <NUM>, and update the previous temporary parity data portion with the new temporary parity data portion in the second temporary storage unit for each of these stripes.

For example, as shown in <FIG>, for each of the M sets of stripes, Flash memory controller <NUM> may compute first parity data portions <NUM>-<NUM>,. , <NUM>(M-<NUM>)-<NUM>, <NUM>-<NUM>. Flash memory controller <NUM> may then compute second parity data portions <NUM>-<NUM>,. , <NUM>(M-<NUM>)-<NUM>, <NUM>-<NUM>. Flash memory controller <NUM> may then compute a temporary parity data portion of each set (e.g., <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>(M-<NUM>)-<NUM>, <NUM>-<NUM>) by performing an XOR operation between the second parity data portion and the first parity data portion. For example, Flash memory controller <NUM> may determine that <NUM>-<NUM>=<NUM>-<NUM>×<NUM>-<NUM>, <NUM>-<NUM>=<NUM>-<NUM>×<NUM>-<NUM>,. , <NUM>(M-<NUM>)-<NUM>=<NUM>(M-<NUM>)-<NUM>×<NUM>(M-<NUM>)-<NUM>, <NUM>-<NUM>=<NUM>-<NUM>×<NUM>-<NUM>. The temporary parity data portions <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>(M-<NUM>)-<NUM>, <NUM>-<NUM> may be stored in the second temporary storage unit. Flash memory controller <NUM> may then compute third parity data portions <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>(M-<NUM>)-<NUM>, <NUM>-<NUM>, and a new temporary parity data portion corresponding to each set of stripes. For example, Flash memory controller <NUM> may determine that <NUM>-<NUM>=<NUM>-<NUM>×<NUM>-<NUM>, <NUM>-<NUM>=<NUM>-<NUM>×<NUM>-<NUM>,. , <NUM>(M-<NUM>)-<NUM>=<NUM>(M-<NUM>)-<NUM>×<NUM>(M-<NUM>)-<NUM>, <NUM>-<NUM>=<NUM>-<NUM>×<NUM>-<NUM>. Flash memory controller <NUM> may replace the temporary parity data portions in the second temporary storage unit with the respective new temporary parity data portions. In some implementations, Flash memory controller <NUM> may repeat the above operations until the last stripe of each set. As shown in <FIG>, Flash memory controller <NUM> may determine <NUM>-(J-<NUM>)=<NUM>-(J-<NUM>)×<NUM>-J, <NUM>-(J-<NUM>)=<NUM>-(J-<NUM>)×<NUM>-J,. , <NUM>(M-<NUM>)-(J-<NUM>)=<NUM>(M-<NUM>)-(J-<NUM>)×<NUM>(M-<NUM>)-J, <NUM>-(J-<NUM>)=<NUM>-(J-<NUM>)×<NUM>-J. M temporary parity data portions can then be obtained and stored in the second temporary storage unit for computation and/or reference.

In some implementations, for n=<NUM>, n representing a positive integer, Flash memory controller <NUM> may perform an XOR operation, on each set of stripes, between an nth parity data portion and an (n-<NUM>)th parity data portion to generate a (n-<NUM>)th temporary parity data portion. Flash memory controller <NUM> may then store the (n-<NUM>)th temporary parity data portion into the second temporary storage unit. For n><NUM>, n representing a positive integer, Flash memory controller <NUM> may perform an XOR operation, on each set of stripes, between a parity data portion of an nth parity data portion and an (n-<NUM>)th temporary parity data portion to generate an (n-<NUM>)th temporary parity data portion. Flash memory controller <NUM> may store the (n-<NUM>)th temporary parity data portion in the second temporary storage unit and replace the stored (n-<NUM>)th temporary parity data portion with the (n-<NUM>)th temporary parity data portion. When n is equal to L, Flash memory controller <NUM> may generate M temporary parity data portions, each corresponding to a respective plane (or set of stripes). The M temporary parity data portions may be <NUM>-(J-<NUM>), <NUM>-(J-<NUM>),. , <NUM>(M-<NUM>)-(J-<NUM>), <NUM>-(J-<NUM>), and may be stored in a second temporary storage unit <NUM>, as shown in <FIG>. Flash memory controller <NUM> may perform an XOR operation amongst the M temporary parity data portions <NUM>-(J-<NUM>), <NUM>-(J-<NUM>),. , <NUM>(M-<NUM>)-(J-<NUM>), <NUM>-(J-<NUM>) to generate a parity data set corresponding to J×N×M data portions in the M planes and N dies. Flash memory controller <NUM> may then store the parity data set in a permanent storage unit in the memory cells of NAND memory <NUM>.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which any programming failure, e.g., due to SSG leakage failure and/or multi-plane failure, is being detected. If a programming failure is detected, method <NUM> proceeds to operation <NUM>, in which the memory data stored in the compromised data portion in which the programming failure occurred is recovered using the respective parity data portion. After the recovery of the compromised data portion, method <NUM> proceeds to operation <NUM>, in which a parity data set is generated from the M sets of parity data portions. If no programming failure is detected, method <NUM> proceeds to operation <NUM>.

Flash memory controller <NUM> may determine whether any programming failure, e.g., due to SSG leakage failure and/or multi-plane failure, occurred. As previously explained, SSG leakage failure may cause the memory data in memory cells at the same location of different levels to be compromised, and the multi-plane failure may cause the memory data in memory cells at the same location of different planes to be compromised. However, the striping configuration illustrated in <FIG> can ensure only a single data portion, if any, in a stripe can be compromised by SSG leakage failure and/or multi-plane failure. In some implementations, Flash memory controller <NUM> may use the parity data portion of each stripe to determine whether any programming failure occurred in a data portion in the respective stripe. In some implementations, Flash memory controller <NUM> may perform an XOR operation amongst the data portions of the respective stripe and the parity data portion of the respective stripe to detect and identify the compromised data portion. The location of the compromised data portion in each (if any) stripe may be determined.

If a compromised data portion is detected in a stripe, Flash memory controller <NUM> may generate a replacement data portion based on the rest of the data portions (e.g., the data portions that are not compromised) in the stripe and the parity data portion of the stripe to generate the replacement data portion. In some implementations, the generation of the replacement data portion includes performing an XOR operation amongst the rest of the data portions in the stripe and the parity data portion of the stripe. Flash memory controller <NUM> may recover the compromised data portion with the replacement data portion such that the memory data in the compromised data portion can be retained. In some implementations, Flash memory controller <NUM> may access the parity data portions from temporary storage unit <NUM> if computation is needed, e.g., for identifying and locating a compromised data portion and/or generating a replacement data portion.

A parity data set <NUM> that represents the parity/redundancy data of the J layers in memory block B1 in the M planes and N dies, e.g., the J×N×M data portions, may be generated from the M temporary parity data portions. In some implementations, parity data set <NUM> is obtained by performing an XOR operation amongst the M temporary parity data portions. Parity data set <NUM> may be stored in a permanent storage unit (e.g., a plurality of memory cells) in NAND memory <NUM>. Flash memory controller <NUM> may access the second temporary storage unit and perform this operation.

In some implementations, Flash memory controller <NUM> may continue to perform operations <NUM>-<NUM> for the remaining layers in memory block B1 in the M planes and N dies. The parity data portions and temporary parity data portions are respectively stored in temporary storage unit <NUM> and the second temporary storage unit for computation and/or reference. The same operations may also be performed for other memory blocks in the M planes and the N dies.

Referring back to <FIG>, method <NUM> proceeds to operation <NUM>, in which the M sets of parity data portions are removed from the temporary storage unit and the M temporary parity data portions are removed from the second temporary storage unit.

Claim 1:
A memory apparatus (<NUM>), comprising:
a plurality of memory cells stored with memory data in N dies, each of the N dies comprising M planes, each of the M planes comprising a memory block, N and M each being a positive integer; and
a controller (<NUM>) operatively coupled to the plurality of memory cells, the controller (<NUM>) being configured to:
determine J layers in the memory block in each of the M planes and in each of the N dies, each of the J layers comprising a pair of adjacent gate conductive layers, J being a positive integer;
determine M sets of stripes, each of the M sets of stripes comprising a plurality of data portions stored in a respective one of the M planes;
determine M sets of parity data portions, each of the M sets of parity data portions corresponding to a respective one of the M stripes; and
control a temporary storage unit (<NUM>, <NUM>, <NUM>), which is outside of the plurality of memory cells, to store the M sets of parity data portions.