Patent Description:
<CIT> (<NUM>-<NUM>-<NUM>) relates to a minimal dead time digitally compensated process transmitter.

<CIT> (<NUM>-<NUM>-<NUM>) relates to a frequency response compensation in a digital to analog converter.

<CIT> describes a method of providing an improved transfer function for a Discrete Multitone (DMT) type modulation transmitter with digital filtering after modulation followed by digital to analog converter.

Process transmitters generally include process variable sensors and measurement circuitry for measuring process related parameters (temperature, pressure, flow rate, volume, etc.). Pressure transmitters also include output circuitry for transmitting a process parameter output to instrumentation and control equipment. Frequently, this transmission is over an analog circuit such as a <NUM>-<NUM> mA current loop, which requires analog output circuitry.

The present invention provides a process transmitter and a corresponding method with the features of the independent claims. Further advantageous embodiments are subject-matter of the dependent claims.

A process transmitter includes a circuit producing a plurality of digital values representing magnitudes for an analog signal and a filter receiving the plurality of digital values and producing a plurality of filtered digital values. Output analog circuitry in the process transmitter is configured to receive the filtered digital values and output an analog signal on a communication channel of the process transmitter. The output analog circuitry has a transfer function and the filter has a transfer function. The transfer function of the filter at least partially offsets the transfer function of the output analog circuitry.

A process transmitter includes a sensor providing a sensor signal representative of a process variable and circuit elements providing a plurality of digital values based on the sensor signal. A filter filters the plurality of digital values to form filtered digital values and output analog circuitry receives the filtered digital values and produces an analog signal based on the filtered digital values. The output analog circuitry has a frequency-domain transfer function and the filtered digital values at least partially counteract effects of the frequency-domain transfer function.

A method includes generating a digital value representing a desired magnitude for an analog output of a process transmitter and filtering the digital value to produce a filtered digital value. The filtered digital value is applied to output analog circuitry to produce the analog output for the process transmitter. The output analog circuitry has a transfer function with a pole and the filter has a transfer function with a zero that is the inverse of the pole.

<FIG> provides a block diagram of a process transmitter <NUM> in accordance with the prior art. Process transmitter <NUM> senses a process variable of a fluid or material carried in a conduit <NUM> and communicates information about the process variable along a communication channel <NUM>. Process transmitter <NUM> includes a sensor <NUM> that senses the process variable and generates an analog value representative of the process variable. The analog value is provided to an analog-to-digital converter <NUM>, which converts the analog signal into a series of digital values that are stored in a register <NUM>. A microprocessor <NUM> accesses input register <NUM> to retrieve the stored values and either provides the stored values directly to a digital-to-analog converter <NUM> or compensates the digital values to account for errors in sensor <NUM> and/or to shift and scale the digital values so that they fit within a range of values that are allowed by communication channel <NUM>. For example, when communication channel <NUM> is a two-wire current loop that utilizes the <NUM>-<NUM> mA standard, each digital value is scaled so as to produce a current that is between <NUM> and <NUM> mA. Digital-to-analog converter <NUM> converts the digital values it receives into an analog signal that is then applied to additional analog components in an I/O circuit <NUM> to control the signal on communication channel <NUM>.

In some applications, the speed with which process transmitter <NUM> can obtain a new sensor value and transmit that value on communication loop <NUM> is critical to the monitoring of the process variable. For example, in compressor control applications, the response time of the pressure transmitter to pressure changes must be fast enough to capture transient changes in flow that occur during surges to capture when the operating point crosses the surge line, which can occur within a <NUM>-<NUM> millisecond time period. One component of a process transmitter's response time is the time constant of the analog circuit elements in digital-to-analog converter <NUM> and I/O circuit <NUM> that produce the analog signal on communication channel <NUM>.

In accordance with one embodiment, the effect that the digital-to-analog converter and I/O circuit have on the process transmitter's response time is offset or partially neutralized by applying the digital values from the microprocessor to a compensating filter before providing the filtered digital values to the digital-to-analog converter. <FIG> provides a block diagram of one such example.

In <FIG>, a process transmitter <NUM> contains a sensor <NUM> that senses a process variable of a fluid or material carried in conduit <NUM>. Sensor <NUM> provides an analog sensor signal to an analog-to-digital converter <NUM>, which converts the analog sensor signal into a series of digital values by sampling the analog sensor signal at periodic intervals. The series of digital values are stored in a register <NUM>, which is accessed by a microprocessor or circuit <NUM>. Microprocessor or circuit <NUM> passes the stored digital values either directly to a compensating filter <NUM> or alters the stored digital values to compensate for errors in sensor <NUM> and/or to shift and scale the sensor values to place the sensor values in the range of output values supported by communication channel <NUM>. In either case, the digital values provided to compensating filter <NUM> represent magnitudes of the analog signal that is to be placed on communication channel <NUM>. Compensating filter <NUM> filters the series of digital values from microprocessor <NUM> to produce a series (also referred to as a plurality) of filtered digital values that are input to digital-to-analog converter <NUM>. Digital-to-analog converter <NUM> uses the digital values to generate an analog signal that that further drives output analog elements in I/O circuit <NUM> to produce an analog communication signal on communication channel <NUM>. In accordance with one example, communication channel <NUM> is a <NUM>-<NUM> mA current loop, however, the example is not limited to a single communication standard.

To offset the effect that digital-to-analog converter <NUM> and I/O circuit <NUM> have on the response time of the process transmitter, compensating filter <NUM> is designed to at least partially offset or neutralize the frequency-domain transfer function of the output analog circuitry of digital-to-analog converter <NUM> and I/O circuit <NUM>.

Specifically, the output analog circuitry of digital-to-analog converter <NUM> and I/O circuit <NUM> has a frequency domain transfer function of: <MAT> The inverse of this function is <MAT> Of course, the product of these two transfer functions is simply the identity value of <NUM>: <MAT> Which indicates that using a compensating filter with a transfer function that is the inverse of the transfer function of the output analog circuitry will completely offset or neutralize the effects of the output analog circuitry's transfer function. To ensure the stability of the compensating filter, a pole is added to the inverse function. Specifically, in one example, an all-pass filter is created by adding the pole <NUM> + s T/<NUM> where T is the update period of digital-to-analog converter <NUM> so that the transfer function of the compensating filter becomes <MAT> Note that this filter contains a zero, <NUM> + s τa, that is the inverse of the pole, <MAT>, found in the transfer function of the output analog circuitry. This filter is converted to the digital domain by using the well-known bilateral transform: <MAT> Which is re-written as <MAT> From this result, it is easy to write the difference equation that describes the digital output, y(n), of compensating filter <NUM> in terms of a latest unfiltered digital input, x(n), and a previous unfiltered digital input, x(n-<NUM>): <MAT> or <MAT> Where <MAT>.

For example, for a digital-to-analog converter with an update period T of <NUM> and an output analog circuitry time constant τa of <NUM>, equations <NUM> and <NUM> become: <MAT> and <MAT>.

By using compensating filter <NUM> to at least partially neutralize or offset the frequency-domain transfer function of the output analog circuitry, the response time of the output analog circuitry can be reduced while maintaining the output analog circuitry and its critical time constant, which ensures signal stability as well as desired output behavior.

<FIG> provides a block diagram of compensating filter <NUM>. In <FIG>, compensating filter <NUM> includes a delay unit <NUM> and a difference calculating module <NUM>. Compensating filter <NUM> receives a sequence of digital values with the current digital value being provided directly to difference calculation module <NUM> and a previous digital value being provided by delay unit <NUM>. Difference calculation module <NUM> also receives circuit time constant <NUM> and update period <NUM> from a register or a memory location. Using Equation <NUM> or <NUM> above, difference calculation module <NUM> applies circuit time constant <NUM>, update period <NUM>, the current digital value and the previous digital value to compute a filtered digital value <NUM> for each input digital value. The filtered digital values are provided to digital-to-analog converter <NUM>.

<FIG> provides a flow diagram of a method of utilizing compensating filter <NUM> and digital-to-analog converter <NUM>. At step <NUM>, a determination is made as to whether changes have been received to the time constant or update period. If changes to either of these two values have been received, the parameters of the difference equation are re-determined for the filter at step <NUM> using Equation <NUM> above. If the time constant and update period have not changed at step <NUM>, the process continues at step <NUM> where a current digital value (also referred to as a digital-to-analog converter reading) is received. The current digital value and a preceding digital value are then applied to the difference equation to produce a filtered digital value at step <NUM>. The filtered digital value is then applied to the digital-to-analog converter at step <NUM>. After the filtered digital value has been applied to the digital-to-analog converter, the process returns to step <NUM> to see if there have been any changes to the time constant or update period.

In alternative example, changes to the difference equation parameters are triggered by an interrupt indicating that the time constant or update period has been changed. This interrupt can take the form of a call to a function to alter the difference equation parameters based on a new time constant and/or update period. Alternatively, the parameters for the difference equation can be calculated by a device other than the process transmitter <NUM> and can be sent to process transmitter <NUM> through communication channel <NUM>.

<FIG> provides a graph <NUM> of the analog output of digital-to-analog converter <NUM> and I/O circuit <NUM> in response to a series of unfiltered digital values <NUM> and a graph <NUM> of the analog output of digital-to-analog converter <NUM> and I/O circuit <NUM> in response to a series of filtered digital values <NUM>. Filtered digital values <NUM> are produced by compensation filter <NUM> in response to the series of unfiltered digital values <NUM>. In <FIG>, vertical axis <NUM> shows the magnitudes of the digital and analog values normalized relative to the minimum and maximum allowed values on the communication channel. For example, for a <NUM>-<NUM> mA channel, the minimum value is 4mA, which is designated as <NUM> on the vertical axis and the maximum value is <NUM> mA, which is designated as <NUM> on the vertical axis. Thus, each analog and digital value is shifted and scaled to position it on the graphs of <FIG> by subtracting <NUM> mA from the value and dividing the result by <NUM> mA. Time is shown along horizontal axis <NUM>. In the example of <FIG>, the update period T is <NUM> milliseconds.

In <FIG>, the unfiltered digital values <NUM> show a step function where the unfiltered digital value at time <NUM> changes from <NUM> mA to <NUM> mA and then remains at <NUM> mA. In prior art process transmitter <NUM>, this step input results in analog output <NUM>, which has a response time (the time required to reach <NUM>% of its final value) of <NUM>.

Compensating filter <NUM> receives unfiltered digital values <NUM> and produces filtered digital values <NUM> from the unfiltered values. In particular, for an update period of <NUM> and a time constant of <NUM>, compensating filter <NUM> produces a filtered digital value of <NUM> mA at time point <NUM> because the preceding unfiltered digital value was <NUM> mA and the current unfiltered digital value is <NUM> mA resulting in: <MAT> (using Equation <NUM> above).

At <NUM> and every update period thereafter, compensating filter <NUM> produces a filtered digital value of <NUM> mA because the preceding unfiltered digital value is <NUM> mA and the current unfiltered digital value is <NUM> mA resulting in: <MAT> (using Equation <NUM> above).

When filtered digital values <NUM> are applied to digital-to-analog converter <NUM>, the resulting analog output <NUM> has a response time of <NUM>, which is much shorter than the <NUM> of the prior art. In addition, analog output <NUM> reaches its final value within a single update period.

In the example of <FIG>, digital-to-analog converter <NUM> must have a large dynamic range to accommodate the large range of digital values output by compensating filter <NUM>. For example, using the example filter described above, digital-to-analog converter <NUM> must be able to accommodate a digital command of <NUM> mA associated with a full range positive step in the unfiltered digital values and must accommodate a digital command of -20mA, which is the filtered digital value produced by the example filter in response to a full range negative step (from <NUM> mA to <NUM> mA) in the unfiltered digital values.

As an alternative to utilizing a digital-to-analog converter <NUM> with such a large dynamic range, an embodiment shown in <FIG> utilizes a clipping filter <NUM> in place of compensating filter <NUM>, where clipping filter <NUM> limits the range of filtered digital values (digital commands) applied to the digital-to-analog converter. In <FIG>, a process transmitter <NUM> senses a process variable of a fluid or material in a conduit <NUM> and generates an analog signal on a communication channel <NUM> representative of the sensed process variable. In particular, processor transmitter <NUM> includes a sensor <NUM>, which generates an analog sensor signal indicative of the process variable. The analog sensor signal is provided to an analog-to-digital converter <NUM>, which converts the analog signal into a series of digital values that are stored in a register <NUM>. A microprocessor or circuit <NUM> accesses the stored values in register <NUM> and either provides them directly to clipping filter <NUM> or alters them to compensate the digital values for errors in sensor <NUM> and/or to scale and shift the values to a range of values supported by communication channel <NUM> such as values between <NUM> and <NUM> mA. In either case, the digital values provided to clipping filter <NUM> represent the magnitudes of the analog signal to be transmitted on communication channel <NUM>. Clipping filter <NUM> includes a compensating filter emulator, which generates filtered digital values similar to the way in which compensating filter <NUM> generates filtered values so as to at least partially neutralize or offset the frequency-domain transfer function of digital-to-analog converter <NUM>. In addition, clipping filter <NUM> examines the output filtered digital values and replaces any digital values outside of a clipping range with a maximum or minimum value of the range. The digital values output by clipping filter <NUM> are provided to digital-to-analog converter <NUM>, which uses the values to generate an analog signal used to control I/O circuit <NUM> and thereby form an analog signal on communication channel <NUM>.

<FIG> provides a block diagram of one embodiment of clipping filter <NUM> and <FIG> provides a method of using clipping filter <NUM> in the embodiment of <FIG>. Clipping filter <NUM> consists of a filter emulator <NUM>, a clipping module <NUM> and an analog circuitry output emulator <NUM>. In step <NUM> of <FIG>, clipping filter <NUM> determines if a new value for the analog circuit time constant or a new value for the update period has been received. If the time constant or update period have changed, the difference equation (Equation <NUM>) is re-determined for the new time constant and/or new update period at step <NUM>. In accordance with other embodiments, instead of receiving a new time constant and/or new update period, clipping filter <NUM> can simply receive the new parameters for the difference equation through communication channel <NUM>. After the difference equation has been re-determined at step <NUM> or if the difference equation does not need to be re-determined, the process of <FIG> continues at step <NUM> where the analog circuitry output emulator <NUM> estimates a latest output of the analog circuitry. In accordance with one embodiment, the latest output of the analog circuitry is estimated using: <MAT>
where a[n] is the estimated latest analog circuitry output in response to the previous digital value output by clipping filter <NUM>, a[n-<NUM>] is the estimated analog circuitry output at the instance before the previous digital value output by clipping filter <NUM> was applied to digital-to-analog converter <NUM>, T is the update period of the digital-to-analog convertor, τa is the time constant of the analog circuit, and DAC[n-<NUM>] is the previous output of clipping filter <NUM> provided to digital-to-analog converter <NUM>.

At step <NUM>, a latest unfiltered digital value is received from microprocessor <NUM> as input <NUM>. At step <NUM>, a filter emulator <NUM> uses the latest unfiltered digital value <NUM> and the estimated latest output of the analog circuitry from equation <NUM> to produce a filtered digital value. In particular, the filtered digital value is determined as: <MAT>
where a[n] is the estimated latest output of the analog circuitry determined in step <NUM>, T is the update time period <NUM>, τa is the analog circuit time constant <NUM> and x(n) is the latest unfiltered digital value <NUM>. Note that a[n] is used in equation <NUM> instead of x(n-<NUM>) because a[n] reflects any clipping applied by clipping filter <NUM>.

The filtered digital value, y(n), output by filter emulator <NUM> is provided to clipping module <NUM>, which performs a clipping function by determining if the filtered digital value exceeds a maximum of a digital-to-analog clipping range <NUM> at step <NUM>. If the filtered digital value exceeds the maximum of the clipping range, clipping module <NUM> replaces the filtered digital value with the maximum of the clipping range at step <NUM> and provides the maximum of the clipping range as the output of clipping filter <NUM> for time n at step <NUM>. If the filtered digital value is not greater than the maximum of the clipping range at step <NUM>, clipping module <NUM> determines if the filtered digital value is less than the minimum of the clipping range at step <NUM>. If the filtered digital value is less than the minimum of the clipping range at step <NUM>, the filtered digital value is replaced with the minimum of the clipping range at step <NUM> and the minimum of the clipping range is provided as the output of clipping filter <NUM> for time n at step <NUM>. If the filtered digital value is not less than the minimum of the clipping range, clipping module <NUM> provides the filtered digital value produced by filter emulator <NUM> as the output of clipping filter <NUM> for time n at step <NUM>. In accordance with other embodiments, the filtered digital value is compared to the minimum of the clipping range before being compared to the maximum of the clipping range.

The selected output of clipping filter <NUM> is provided to digital-to-analog converter <NUM> and is fed back to analog circuitry output emulator <NUM>, which uses the clipping filter output to form a new estimate of the output of the analog circuitry upon returning to step <NUM>.

<FIG> provides a graph <NUM> of the analog output of digital-to-analog converter <NUM> for unfiltered digital input <NUM> and a graph <NUM> of the analog output of digital-to-analog converter <NUM> for the filtered digital input <NUM> from clipping filter <NUM>. In <FIG>, filtered digital input <NUM> is produced by clipping filter <NUM> from unfiltered digital input <NUM>. In <FIG>, vertical axis <NUM> shows the magnitudes of the digital and analog values normalized relative to the minimum and maximum allowed values on communication channel <NUM>. For example, for a <NUM>-<NUM> mA channel, the minimum value is 4mA, which is designated as <NUM> on the vertical axis and the maximum value is <NUM> mA, which is designated as <NUM> on the vertical axis. Thus, each analog and digital value is shifted and scaled to position it on the graphs of <FIG> by subtracting <NUM> mA from the value and dividing the result by <NUM> mA. Time is shown along horizontal axis <NUM>. In the example of <FIG>, the update period T is <NUM> milliseconds.

In accordance with the embodiments shown in <FIG>, the clipping range of clipping filter <NUM> is set to <NUM>-<NUM> mA for an output range on communication channel <NUM> of <NUM>-<NUM> mA. A value of <NUM> mA is equivalent to a normalized magnitude of <NUM> in the graphs of <FIG>. As shown in <FIG>, the step input of unfiltered digital values <NUM> causes clipping filter <NUM> to initially output clipped values of <NUM> mA (<NUM> in <FIG>) for the first three update periods <NUM>, <NUM> and <NUM>. Thus, for the first three update periods, clipping filter <NUM> reduces the filtered digital values produced by filter emulator <NUM> to the maximum of clipping range <NUM>. For the fourth update period <NUM>, the filtered digital value generated by filter emulator <NUM> is greater than the unfiltered digital value but less than the maximum of the clipping range so the filtered digital value is output directly as the output of clipping filter <NUM>. At fifth update period <NUM> and all update periods thereafter, the filtered digital value is the same as the unfiltered digital value.

As shown by analog output <NUM>, the response time for the output analog circuitry was reduced to <NUM> milliseconds when using the clipping filter digital values and was <NUM> milliseconds when using the unfiltered digital values. Thus, the embodiment of <FIG> and <FIG> is able to reduce the response time of the output analog circuitry without greatly increasing the dynamic range of digital-to-analog converter <NUM>.

Although the response time of the output analog circuitry was reduced, the combination of clipping filter <NUM> and digital-to-analog converter <NUM> requires four update time periods in order for the analog output to reach its final value. Thus, although the dynamic range requirement is reduced in the embodiment of <FIG> and <FIG> relative to the embodiment of <FIG> and <FIG>, the amount of time required to reach the final value of the analog output is increased in the embodiments of <FIG> and <FIG> relative to the embodiments of <FIG> and <FIG>.

<FIG> provides a graph of the number of time update periods required to reach a final analog value from a beginning analog value using a clipping range of <NUM> to <NUM> mA for an analog output range of <NUM> to <NUM> mA. In <FIG>, a desired analog output is shown on vertical axis <NUM> and a current analog output is shown on horizontal axis <NUM>. Transitions from an analog output on the horizontal axis to an analog output on the vertical axis shown in the white area <NUM> can be achieved in a single update period. Transitions from a current analog output to a desired analog output shown in grey areas <NUM> and <NUM> can be achieved in two update periods. Transitions from a current analog output to a desired analog output shown in areas <NUM> and <NUM> can be achieved in three updates and transitions from a current analog output to a desired analog output shown in areas <NUM> and <NUM> can be achieved in four update periods. As shown in <FIG>, <NUM>% of the possible conditions are met in a single update, <NUM>% of the possible conditions are met in two updates and <NUM>% of the possible conditions are met in just three updates.

In one exemplary embodiment, a pressure transmitter is used in a compressor application to detect surge events. In this embodiment, the control point that will trigger the identification of a surge event is set to an analog output of <NUM> mA from the pressure transmitter. This provides <NUM>% of the full range of the pressure transmitter output to use for control purposes (20mA-<NUM>. 33mA/20mA-4mA) while allowing ~<NUM>% of full range events (events that start at 20mA output and cross to or below <NUM>. 33mA output) to be detected in a single update period and ∼<NUM>% of full range events to be detected in two update periods.

Claim 1:
A process transmitter (<NUM>) comprising:
a circuit (<NUM>) producing a plurality of digital values representing magnitudes for an analog signal;
a filter (<NUM>) receiving the plurality of digital values and producing a plurality of filtered digital values;
a digital-to-analog converter (<NUM>); and
output analog circuitry (<NUM>) configured to receive the plurality of filtered digital values and output an analog signal on a communication channel (<NUM>) of the process transmitter, wherein the output analog circuitry (<NUM>) has a transfer function and wherein the filter (<NUM>) has a transfer function that is the inverse of the transfer function of the output analog circuitry (<NUM>) such as to offset the transfer function of the output analog circuitry (<NUM>),
wherein the filter (<NUM>) comprises a clipping module (<NUM>) to limit the filtered digital values to a range of values supported by the digital-to-analog converter (<NUM>), and
wherein the filter (<NUM>) further comprises an analog circuitry output emulator (<NUM>) to emulate a latest output of the output analog circuitry (<NUM>).