Patent Description:
Document <CIT> discloses a housing for a power semiconductor module arrangement including sidewalls and a lid. The lid includes a first layer of a first material having a plurality of openings, and second layer of a second material that is different from the first material. The second layer completely covers a bottom surface of the first layer. The second layer includes a plurality of protrusions, each protrusion extending into a different one of the plurality of openings of the first layer such that each of the plurality of openings is completely covered by one of the protrusions.

Document <CIT> discloses a housing for a power semiconductor module including sidewalls and a top that includes a first surface extending in a first horizontal plane and a second surface opposite and in parallel to the first surface, a plurality of openings of a first kind, each of the plurality of openings of the first kind including a first through hole extending through the top from the first surface to the second surface, and a plurality of openings of a second kind, each of the plurality of openings of the second kind comprising a second through hole extending through the top from the first surface to the second surface. Each of the plurality of openings of the first kind includes a collar or sleeve. Each of the plurality of openings of the second kind includes a trench or indentation arranged adjacent to and forming a closed loop around the respective second through hole.

Document <CIT> discloses a semiconductor package comprising a package body, at least one semiconductor chip arranged in the package body, and at least two electric terminals by means of which the at least one semiconductor chip is electrically connected, the at least two electric terminals protrude from the package body, wherein the package body comprises a first body compound and a second body compound, the first body compound has a lower comparative tracking index, CTI, than the second body compound, and the CTI of the second body compound is at least <NUM> larger than the CTI of the first body compound.

Power semiconductor module arrangements often include at least one semiconductor substrate arranged in a housing. A semiconductor arrangement including a plurality of controllable semiconductor elements (e.g., two IGBTs in a half-bridge configuration) or non-controllable semiconductor elements (e.g., arrangements of diodes) is arranged on each of the at least one substrate. Each substrate usually comprises a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer and a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor elements are mounted, for example, on the first metallization layer. The second metallization layer may optionally be attached to a base plate. Other semiconductor module arrangements are known which do not comprise substrates, e.g., semiconductor module arrangements using cooling structures with floating potentials.

The semiconductor substrate and the elements mounted thereon are usually electrically coupled to the outside of the housing by means of terminal elements. Such terminal elements are electrically coupled to the substrate or one or more of the elements mounted thereon with a first end, and extend from the substrate through the housing to the outside of the housing. A power semiconductor module arrangement usually comprises a plurality of such terminal elements. Different terminal elements may be coupled to the same or to different electrical potentials. If two terminal elements that are coupled to different electrical potentials are arranged close to each other, a creepage distance between the second ends of such terminal elements outside of the housing may be shorter than a minimal creepage distance. This may result in unwanted short-circuits that may negatively affect the operation of the power semiconductor module or even destroy the power semiconductor module arrangement.

There is a need for a housing and a power semiconductor module comprising a housing wherein a length of the creepage distances equals or is larger than a minimum creepage distance and that may be produced at comparably low costs.

A housing for a power semiconductor module arrangement includes sidewalls and a top, wherein the top includes a first layer of a first material including a plurality of openings, and a second layer of a second material that is different from the first material, wherein the second material has a comparative tracking index CTI that is higher than a comparative tracking index CTI of the first material, and at least one of the second layer partly covers at least one of a bottom surface of the first layer and a top surface of the first layer, and the first layer comprises at least one additional opening, each of the at least one additional opening being sealed by a section of the second layer such that the second layer forms at least one section of the housing.

A power semiconductor module includes a semiconductor substrate, at least one semiconductor body arranged on a top surface of the semiconductor substrate, and the housing, wherein the semiconductor substrate with the at least one semiconductor body arranged thereon is arranged within the housing or forms a bottom of the housing.

A method for forming a top of a housing includes forming a first layer of a first material including a plurality of openings, and forming a second layer of a second material that is different from the first material, wherein the second material has a comparative tracking index CTI that is higher than a comparative tracking index CTI of the first material, and at least one of the second layer partly covers at least one of a bottom surface of the first layer and a top surface of the first layer, and the first layer comprises at least one additional opening, each of the at least one additional opening being sealed by a section of the second layer such that the second layer forms at least one section of the housing.

<FIG>, <FIG> and <FIG> fall within the scope of the present invention.

In the following detailed description, reference is made to the accompanying drawings. The drawings show specific examples in which the invention may be practiced. It is to be understood that the features and principles described with respect to the various examples may be combined with each other, unless specifically noted otherwise. In the description, as well as in the claims, designations of certain elements as "first element", "second element", "third element" etc. are not to be understood as enumerative. Instead, such designations serve solely to address different "elements". That is, e.g., the existence of a "third element" does not require the existence of a "first element" and a "second element". An electrical line or electrical connection as described herein may be a single electrically conductive element, or include at least two individual electrically conductive elements connected in series and/or parallel. Electrical lines and electrical connections may include metal and/or semiconductor material, and may be permanently electrically conductive (i.e., non-switchable). A semiconductor body as described herein may be made from (doped) semiconductor material and may be a semiconductor chip or be included in a semiconductor chip. A semiconductor body has electrically connecting pads and includes at least one semiconductor element with electrodes.

Referring to <FIG>, a cross-sectional view of a power semiconductor module arrangement <NUM> is illustrated. The power semiconductor module arrangement <NUM> includes a housing <NUM> and a semiconductor substrate <NUM>. The semiconductor substrate <NUM> includes a dielectric insulation layer <NUM>, a (structured) first metallization layer <NUM> attached to the dielectric insulation layer <NUM>, and a (structured) second metallization layer <NUM> attached to the dielectric insulation layer <NUM>. The dielectric insulation layer <NUM> is disposed between the first and second metallization layers <NUM>, <NUM>.

Each of the first and second metallization layers <NUM>, <NUM> may consist of or include one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; any other metal or alloy that remains solid during the operation of the power semiconductor module arrangement. The semiconductor substrate <NUM> may be a ceramic substrate, that is, a substrate in which the dielectric insulation layer <NUM> is a ceramic, e.g., a thin ceramic layer. The ceramic may consist of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulation layer <NUM> may consist of or include one of the following materials: Al<NUM>O<NUM>, AIN, SiC, BeO or Si<NUM>N<NUM>. For instance, the substrate <NUM> may, e.g., be a Direct Copper Bonding (DCB) substrate, a Direct Aluminum Bonding (DAB) substrate, or an Active Metal Brazing (AMB) substrate. Further, the substrate <NUM> may be an Insulated Metal Substrate (IMS). An Insulated Metal Substrate generally comprises a dielectric insulation layer <NUM> comprising (filled) materials such as epoxy resin or polyimide, for example. The material of the dielectric insulation layer <NUM> may be filled with ceramic particles, for example. Such particles may comprise, e.g., SiO<NUM>, Al<NUM>O<NUM>, AlN, or BN and may have a diameter of between about <NUM> and about <NUM>. The substrate <NUM> may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulation layer <NUM>. For instance, a non-ceramic dielectric insulation layer <NUM> may consist of or include a cured resin.

The semiconductor substrate <NUM> is arranged in a housing <NUM>. In the example illustrated in <FIG>, the semiconductor substrate <NUM> forms a ground surface of the housing <NUM>, while the housing <NUM> itself solely comprises sidewalls and a cover. This is, however, only an example. It is also possible that the housing <NUM> further comprises a ground surface and the semiconductor substrate <NUM> be arranged inside the housing <NUM>. According to another example, the semiconductor substrate <NUM> may be mounted on a base plate (not illustrated). In some power semiconductor module arrangements <NUM>, more than one semiconductor substrate <NUM> is arranged on a single base plate. The base plate may form a ground surface of the housing <NUM>, for example. The top of the housing <NUM> can either be a separate cover or lid that can be removed from the sidewalls, or may be formed integrally with at least the sidewalls of the housing <NUM>. In the latter case, the top and at least the sidewalls of the housing <NUM> may be formed as a single piece such that the top cannot be removed from the sidewalls without destroying the housing. Other semiconductor module arrangements are known which do not comprise substrates, e.g., semiconductor module arrangements using cooling structures with floating potentials.

One or more semiconductor bodies <NUM> may be arranged on the semiconductor substrate <NUM>. Each of the semiconductor bodies <NUM> arranged on the semiconductor substrate <NUM> may include a diode, an IGBT (Insulated-Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a JFET (Junction Field-Effect Transistor), a HEMT (High-Electron-Mobility Transistor), or any other suitable controllable or non-controllable semiconductor element.

The one or more semiconductor bodies <NUM> may form a semiconductor arrangement on the semiconductor substrate <NUM>. In <FIG>, only two semiconductor bodies <NUM> are exemplarily illustrated. The second metallization layer <NUM> of the semiconductor substrate <NUM> in <FIG> is a continuous layer. The first metallization layer <NUM> is a structured layer in the example illustrated in <FIG>. "Structured layer" means that the first metallization layer <NUM> is not a continuous layer, but includes recesses between different sections of the layer. Such recesses are schematically illustrated in <FIG>. The first metallization layer <NUM> in this example includes four different sections. Different semiconductor bodies <NUM> may be mounted to the same or to different sections of the first metallization layer <NUM>. Different sections of the first metallization layer may have no electrical connection or may be electrically connected to one or more other sections using, e.g., bonding wires <NUM>. Electrical connections <NUM> may also include connection plates or conductor rails, for example, to name just a few examples. The one or more semiconductor bodies <NUM> may be electrically and mechanically connected to the semiconductor substrate <NUM> by an electrically conductive connection layer <NUM>. Such an electrically conductive connection layer may be a solder layer, a layer of an electrically conductive adhesive, or a layer of a sintered metal powder, e.g., a sintered silver powder, for example.

The power semiconductor module arrangement <NUM> illustrated in <FIG> further includes terminal elements <NUM>. The terminal elements <NUM> are electrically connected to the first metallization layer <NUM> and provide an electrical connection between the inside and the outside of the housing <NUM>. The terminal elements <NUM> may be electrically connected to the first metallization layer <NUM> with a first end <NUM>, while a second end <NUM> of the terminal elements <NUM> protrudes out of the housing <NUM>. The terminal elements <NUM> may be electrically contacted from the outside at their second end <NUM>. The terminal elements <NUM> illustrated in <FIG>, however, are only examples. Terminal elements <NUM> may be implemented in any other way and may be arranged at any other position. For example, one or more terminal elements <NUM> may be arranged close to or adjacent to the sidewalls of the housing <NUM>. Any other suitable implementation is possible. The terminal elements <NUM> may consist of or include a metal such as copper, aluminum, gold, or silver, for example.

Conventional power semiconductor module arrangements <NUM> generally further include a casting compound <NUM>. The casting compound <NUM> may consist of or include a silicone gel or may be a rigid molding compound, for example. The casting compound <NUM> may at least partly fill the interior of the housing <NUM>, thereby covering the components and electrical connections that are arranged on the semiconductor substrate <NUM>. The terminal elements <NUM> may be partly embedded in the casting compound <NUM>. At least their second ends <NUM>, however, are not covered by the casting compound <NUM> and protrude from the casting compound <NUM>, e.g., through through holes <NUM> of the housing <NUM>, to the outside of the housing <NUM>. The casting compound <NUM> is configured to protect the components and electrical connections inside the power semiconductor module <NUM>, in particular inside the housing <NUM>, from certain environmental conditions and mechanical damage. The casting compound <NUM> further provides for an electrical isolation of the components inside the housing <NUM>. The casting compound <NUM> generally is chosen to have a very high CTI (e.g., 600V or more) such that it is able to guarantee a sufficient creepage distance between terminal elements <NUM> that are arranged close to each other (e.g., a creepage distance on the surface of the casting compound <NUM>).

<FIG> schematically illustrates a semiconductor module with a plurality of terminal elements <NUM> (second ends <NUM> of terminal elements) protruding out of the top of the housing <NUM>. The top comprises a plurality of openings <NUM>. Terminal elements <NUM> protrude out of some but not all of the openings <NUM>. By providing a plurality of openings <NUM> in the top, one and the same housing <NUM> can be used for many different layouts or applications without the need for customizing the housing <NUM> for specific applications or customers. For example, each of the through holes <NUM> may have a round, square, or any other suitable cross-section, and each terminal element <NUM> may protrude (centrally) through one of the through holes <NUM>. A housing <NUM> comprising more through holes <NUM> as are required, however, is only an example. A housing <NUM> may alternatively comprise the same number of through holes <NUM> as the number of terminal elements <NUM>. That is, for each terminal element <NUM>, a separate through hole <NUM> may be provided, but not more. According to other examples, terminal elements <NUM> can be considered being part of the housing <NUM>. For example, terminal elements may be molded into the material forming the housing <NUM>, or may be snapped into the housing <NUM> by means of suitable elements.

As can be seen in <FIG>, it is possible that different terminal elements <NUM> extend through neighboring through holes <NUM>, or through through holes <NUM> that are arranged comparably close to each other. Terminal elements <NUM> are generally used to electrically contact the components inside the housing <NUM>. One or more of the terminal elements <NUM>, therefore, may be coupled to a first electrical potential while one or more different ones of the terminal elements <NUM> may be coupled to a second electrical potential during the use of the power semiconductor module arrangement. It is also possible that other terminal elements <NUM> are coupled to even further electrical potentials. It is not always possible to arrange terminal elements <NUM> that are connected to different electrical potentials distant to each other in the power semiconductor module arrangement. Therefore, it is possible that one first terminal element <NUM> is coupled to a first electrical potential (e.g., positive potential), while another terminal element <NUM> which is arranged close to the first terminal element <NUM> is coupled to a second electrical potential that is different from the first electrical potential (e.g., negative potential). In order to avoid short circuits, electric flashovers or breakthroughs between such neighboring (or close) terminal elements <NUM>, the distance between two respective terminal elements <NUM> should be chosen such that a minimum creepage distance is achieved. The creepage distance generally is the shortest path along the surface of a solid insulating material between two conductive parts.

This is schematically illustrated for a flat surface in the cross-sectional view of <FIG> schematically illustrates a section of a top of a housing <NUM> between two neighboring terminal elements <NUM>. In this example, the creepage distance (illustrated in a dashed line) is defined by a direct path between the neighboring terminal elements <NUM>. That is, the creepage distance corresponds to the shortest distance d4 between the terminal elements <NUM>.

The creepage distance can be extended by providing trenches <NUM>, <NUM> in and/or protrusions <NUM> on the surface of the top, for example. This is schematically illustrated in the cross-sectional view of <FIG>. The creepage distance may be extended by double the height h734 of a protrusion <NUM> and/or by double the depth d732 of a trench <NUM>, if the width w732 of the trench <NUM> is larger than a minimum width. In the example illustrated in <FIG>, one of the trenches <NUM> has a width w730 that is less than the minimum width. Therefore, the depth d730 of this trench does not extend the creepage distance. The minimum width of a trench <NUM> that is necessary to achieve an extension of the creepage distance generally depends on different factors such as, e.g., a degree of contamination of the environment in which the power semiconductor module arrangement is mounted during operation. Different degrees of contamination may include clean room environment, normal environment, or highly contaminated environment, for example. In a normal environment, the minimum width that is required for a trench to be able to extend the creepage distance may be <NUM>, for example. This minimum width may be shorter in a clean room environment, and longer in a highly contaminated environment.

The required creepage distance further depends on the material of the respective surface. Different materials do have different properties such as, different comparative tracking indices CTIs, for example. The CTI is a scaling factor which is required for the correct calculation of the creepage distance. Especially for power semiconductor modules with very high requirements concerning the electrical isolation, a material having a high CTI may be required. Generally, it can be said that the higher the CTI, the shorter the minimum creepage distance. Another important property of a material used for the top of a housing <NUM> is the relative temperature index RTI, for example. The RTI of a material generally defines the maximum temperature at which the critical properties of a material will still remain within acceptable limits over a long period of time.

Materials having a high CTI are generally more expensive than materials having a lower CTI. Even further, materials having both a high CTI and a high RTI are rare and even more expensive or are not stable concerning mechanical requirements for housings used for power semiconductor module arrangements (as is the case, e.g., with silicone materials which are usually not hard enough for power semiconductor module housings). Therefore, in order to keep the overall costs of a power semiconductor module arrangement at a minimum, materials are often used that have either a high CTI or a high RTI, but not both. If a material having a low CTI is used to form the housing <NUM>, either a minimum distance dmin between different terminal elements <NUM> being connected to different potentials is comparably large (d4 ≥ dmin), or a very sophisticated top is needed with many trenches <NUM> and/or protrusions <NUM> which is generally difficult to produce and only at high production costs. In some cases, it might not even be possible to create a geometry of the housing fulfilling the requirements concerning the minimum creepage distance.

Now referring to <FIG>, wherein <FIG> do not fall under the scope of the present invention and <FIG> falls under the scope of the present invention, sections of housings according to embodiments of the disclosure are schematically illustrated. The housings combine the properties of different materials while it is still possible to produce them at comparably low costs. A housing <NUM> according to embodiments of the disclosure comprises a first layer <NUM> and a second layer <NUM>. The first layer <NUM> forms at least the top of the housing <NUM> and, optionally, the sidewalls. The first layer <NUM>, therefore, comprises a plurality of openings <NUM> (not specifically illustrated in <FIG>). The first layer <NUM> is formed from a first material which comprises certain material properties. The housing <NUM> further comprises a second layer <NUM> formed from a second material that comprises certain material properties. At least one of the material properties of the second material is different from the respective material property of the first material. In particular, the second material has a comparative tracking index CTI that is higher than a comparative tracking index CTI of the first material.

According to one example, the first material comprises a sufficiently high RTI and sufficient mechanical properties. The housing <NUM>, therefore, generally fulfills the thermal and mechanical requirements. As has been discussed above, in order to reduce the overall costs of the housing, the first material may comprise a comparably low CTI. This would normally require comparably large distances d4 between terminal elements <NUM> (or any other elements) that are coupled to different electrical potentials P1, P2. In order to reduce the minimum distance dmin required between terminal elements <NUM> (or any other elements) that are coupled to different electrical potentials P1, P2 while still keeping the overall costs of the housing <NUM> comparably low, the second layer <NUM> is only arranged on some sections of the first layer <NUM>. For example, the second layer <NUM> may be arranged in such sections of the housing <NUM> where a higher CTI is required in order to be able to arrange elements (e.g., terminal elements <NUM>) that are coupled to different electrical potentials P1, P2 closer to each other. The second layer <NUM>, in order to keep the costs of the housing <NUM> low, is not necessarily arranged on the entire surface of the first layer <NUM>. That is, it partly covers the first layer <NUM>. It partly or at least partly covers at least one of a bottom surface of the first layer <NUM> and/or it partly or at least partly covers a top surface of the first layer <NUM>. The bottom surface is a surface of the first layer <NUM> which, when the housing <NUM> is arranged to surround a substrate <NUM> faces the substrate <NUM> (the inside of the housing), and the top surface is a surface of the first layer <NUM> which, when the housing <NUM> is arranged to surround a substrate <NUM> faces the outside of the housing <NUM>. In the examples illustrated in <FIG>, and which do not fall within the scope of the present invention, the second layer <NUM> partly covers only the top surface of the first layer <NUM>. In the example illustrated in <FIG>, and which does not fall within the scope of the present invention, the second layer <NUM> partly covers the top surface and partly covers the bottom surface of the first layer <NUM>. The second layer <NUM> may be a flat layer, as is schematically illustrated in <FIG>. It is, however, also possible that the second layer <NUM> is an uneven layer <NUM> that forms trenches and/or protrusions (see <FIG>), similar to what has been described with respect to <FIG> above. Referring to <FIG>, it is also possible that the first layer <NUM> is an uneven layer that forms trenches and/or protrusion, wherein the uneven first layer <NUM> is covered by a section of a (thin) second layer <NUM> at least in sections between two elements that are coupled to different potentials P1, P2. Referring to <FIG>, which falls under the scope of the present invention, according to further alternative embodiments it is even possible that the first layer <NUM> be omitted in those parts of the housing <NUM> requiring a higher CTI. That is, the first layer <NUM> comprises at least one gap (or additional opening), each of the at least one gap being sealed by a section of the second layer <NUM> such that the second layer <NUM> forms at least one section of the housing <NUM>. In this example it is also possible that the second layer <NUM> is a flat layer (as illustrated in <FIG>) or an uneven layer (not specifically illustrated). In all of the different examples, the distance d4 between two elements that are coupled to different electrical potentials P1, P2 may be decreased even further. However, as the CTI of the second material is high with respect to the CTI of the first material, no or only few trenches or protrusions may generally be required. By arranging the second layer <NUM> only in some sections of the housing <NUM>, the advantages of the first material and the second material may be combined for the concerned sections, while keeping the overall costs of the housing <NUM> comparably low. In the examples illustrated in <FIG>, the second layer <NUM> is only arranged in sections of the housing <NUM> that are arranged between a first potential P1 and a second potential P2 that is different from the first potential P1.

Now referring to <FIG>, a cross-sectional view of a power semiconductor module arrangement <NUM> comprising a housing <NUM> according to embodiments of the disclosure is schematically illustrated. The power semiconductor module arrangement <NUM> essentially corresponds to the arrangement as has been described with respect to <FIG> above. The housing <NUM>, however, comprises a first layer <NUM> consisting of a first material having a first (comparably low) CTI, and a second layer <NUM> that partly covers the first layer <NUM>, wherein the second layer <NUM> consists of a second material having a second CTI that is larger than the first CTI of the first material. The second layer <NUM> in the example of <FIG> not falling within the scope of the present invention covers the first layer <NUM> in sections that are arranged between two neighboring terminal elements <NUM>. In this way, the distance d4 between the two terminal elements <NUM> may be smaller as compared to the arrangement of <FIG> where the housing <NUM> only comprises a single layer of material. The protrusions and trenches as illustrated in the second layer <NUM> in <FIG>, however, are optional.

Now referring to <FIG>, an even further embodiment of a power semiconductor module arrangement <NUM> is schematically illustrated. In this embodiment falling within the scope of the present invention, the second layer <NUM> covers large parts of the first layer <NUM>, both on the top side and on the bottom side of the first layer <NUM>. That is, some sections of the first layer <NUM> are sandwiched between portions of the second layer <NUM>. The second layer <NUM>, however, does not cover the entire first layer <NUM>. That is, at least some parts of the first layer <NUM> are not covered by the second layer <NUM>. The second layer <NUM>, optionally, may also be arranged within one or more of the through holes <NUM>. That is, parts of the second layer <NUM> may extend into the through holes <NUM> and may be arranged between the terminal elements <NUM> and the respective through holes <NUM> they protrude through. In this way, any gaps or spaces between the first layer <NUM> and the terminal element <NUM> may be sealed by the second layer <NUM> when a terminal element <NUM> extends through the opening <NUM>. This may further increase the electrical isolation. At the same time, the through holes <NUM> are sealed by means of the second layer <NUM>. In this way, any contaminants, moisture or corrosive gases, for example, may be prevented from entering the housing <NUM>.

It is noted that in many power semiconductor modules, the bottom surface of the substrate <NUM> (surface facing away from the semiconductor bodies <NUM>) is connected to ground potential. Therefore, the creepage distance between a terminal element <NUM> and ground potential is usually of highest interest. This is the case especially for high power semiconductor modules with isolation voltages of, e.g., 12kV or more. This similarly applies for spring contacts which are often used to press the power semiconductor module on a cooling unit (usually done at customer site) and which are usually connected to ground potential.

When the housing <NUM> is mounted on a power semiconductor module arrangement and at least one terminal element <NUM> protrudes through at least one of the openings <NUM>, the first layer <NUM> may not be in direct contact with the at least one terminal element <NUM>. For example, each of the openings <NUM> may have a round, square, or any other suitable cross-section, and the terminal element <NUM> may protrude centrally through the opening <NUM>. The second layer <NUM> on the other hand may adjoin and directly contact one or more of the terminal elements <NUM>. In this way, each of the plurality of openings <NUM> may be sealed to prevent air, contaminants, moisture and corrosive gases from entering the inside of the housing <NUM>. The second layer <NUM> may be a continuous layer or a structured layer.

To even better protect the power semiconductor module arrangement <NUM> against corrosive gases, the second layer <NUM> may further include a reactant or additives, for example. The reactant may be configured to chemically react with corrosive gases, or, in particular, with sulfur or sulfur-containing compounds of corrosive gases. Corrosive gas may also be trapped, adsorbed or absorbed by the reactant. By chemically reacting with the corrosive gas, the reactant further prevents the harmful substances from reaching the (metal) components inside the housing <NUM> and thereby protects the components against corrosion. The reactant may be, for example, a powder of a third material which is distributed throughout the second material of the second layer <NUM>. The third material may include any materials, e.g., metallic materials, which react with the corrosive gases and which may, e.g., form a metal sulfide when exposed to corrosive gases. The reactant may be essentially evenly distributed throughout the second material of the second layer <NUM>. It is also possible to, e.g., add copper particles to the second material. Copper particles may act as sacrificial material and will react with hydrogen sulfide, for example, before it is able to reach the inside of the housing <NUM>.

As has been described above, the first layer <NUM> comprises a first material and the second layer <NUM> comprises a second material that is different from the first material. According to embodiments of the disclosure, the first material can be a comparably rigid material. In this way, the housing <NUM> can provide sufficient protection against mechanical damage. Mechanical stability of the housing is also required, e.g., when mounting the semiconductor module including the housing to a cooling unit. The housing is usually used to press the substrate and/or a base plate against the cooling unit. A housing providing sufficient mechanical stability results in a substrate having sufficient contact to the cooling unit over the entire surface of the substrate to provide sufficient heat transfer between the substrate and the cooling unit. The second material, on the other hand, can be a material that is soft as compared to the first material. The second material can further comprise certain elastic properties. This allows the terminal elements <NUM> to penetrate through the second layer <NUM>, for example, and to tightly close any gaps between the first layer <NUM> and the terminal elements <NUM>. The first layer <NUM>, for example, can comprise a thermoplastic material or any kind of hard plastic materials or epoxy. The second layer <NUM> can comprise at least one of soft polymers, silicones, (thermoplastic) elastomers, polyurethanes, acrylates, or rubbers, for example. According to one example, the second layer <NUM> consists of or comprises a liquid silicon rubber (LSR). A different material hardness of the first material and the second material may also improve the vibration robustness of the power semiconductor module arrangement <NUM>, for example. Further, many rigid materials that may be used for the first layer <NUM> are very smooth and, therefore, may be difficult to handle manually. Materials that are comparably soft are generally much easier to handle, as they provide certain soft touch properties, especially when handled manually.

The housing <NUM> can be produced using (<NUM>) injection molding, or manual assembly of separately produced injection molded or casted parts, for example. According to one example, a method for producing a housing <NUM> comprises, in a first step, forming a first layer <NUM> of a first material. The first layer <NUM> may have a rectangular or square cross-section, for example, and comprise a plurality of openings <NUM>. According to one example, the plurality of openings <NUM> are distributed over the plane of the first layer <NUM> in a regular pattern. This, however, is only an example. The plurality of openings <NUM> can be distributed over the plane of the first layer <NUM> in any suitable way. The first layer <NUM> can be formed by means of an injection molding process, for example.

According to one example, the first layer <NUM> may remain in the mold and the second layer <NUM> is formed directly on the first layer <NUM> in the same mold. The second layer <NUM> is formed to partly cover the first layer <NUM>. The second layer <NUM> may be arranged adjacent to and may directly adjoin the first layer <NUM>, for example. When forming the first layer <NUM> and the second layer <NUM> by means of a <NUM> injection molding process, the second layer <NUM> generally adheres to the first layer <NUM> and may not be easily removed from the first layer <NUM>. The second layer <NUM> generally may adhere to the first layer, e.g., by means of chemical bonding, mechanical interlock and/or any other suitable connection method. Depending on the materials used for the first layer <NUM> and the second layer <NUM>, a chemical bond may be formed between the layers <NUM>, <NUM>, for example. According to one example, the second layer <NUM> has a certain adhesiveness such that it adheres to the first layer <NUM> to a certain degree without the need for any mechanical interlocks.

In order to form a power semiconductor module arrangement, the top that is formed by means of methods according to embodiments of the disclosure may be connected to sidewalls in order to form a housing <NUM> that is then arranged to enclose at least one substrate <NUM>. The sidewalls, however, may also be formed during the same injection molding process as the top of the housing <NUM>.

Claim 1:
A housing (<NUM>) for a power semiconductor module arrangement (<NUM>) comprises sidewalls and a top, wherein the top comprises:
a first layer (<NUM>) of a first material comprising a plurality of openings (<NUM>); and
a second layer (<NUM>) of a second material that is different from the first material,
wherein
the second material has a comparative tracking index CTI that is higher than a comparative tracking index CTI of the first material, and at least one of
the second layer (<NUM>) partly covers at least one of a bottom surface of the first layer (<NUM>) and a top surface of the first layer (<NUM>), and
the first layer (<NUM>) comprises at least one additional opening, each of the at least one additional opening being sealed by a section of the second layer (<NUM>) such that the second layer (<NUM>) forms at least one section of the housing (<NUM>).