Patent Description:
<CIT> is directed to an amplitude modulation apparatus, an amplitude limiting method, and a transmission apparatus for performing amplitude limitation on an orthogonally modulated signal.

<NPL>, discusses an I/O-codeword diamond-shape clipping.

<CIT> is directed to applying crest factor reduction techniques to a digitally modulated signal used in communication applications.

In an IQ transmitter, the transmit signal is broken into an I component and a Q component which may be processed in separate processing paths. At any given time, a value of the I signal component (hereinafter the "I value") and a value of the Q signal component (hereinafter the "Q value") define Cartesian coordinates describing a data point being communicated. In the complex plane, conventionally the horizontal axis is called the real axis and is labeled as the "I" axis and the vertical axis is called the imaginary axis and is labeled as the "Q" axis. Thus, the I value defines the data point's location with respect to the I axis and the Q value defines the data point's location with respect to the Q axis. This is in contrast to polar transmitter in which the transmit signal is broken into a magnitude component and an angle or phase component. At any given time, the magnitude component defines a distance the data point is from the origin of the complex plane and the angle or phase component defines an angle from the <NUM> degree reference position at which the data point is located.

In a digital IQ transmitter, the radio frequency (RF) digital-to-analog convertors (DACs) convert digital baseband I and Q transmit signal components to analog I and Q transmit signal components and at the same time up-convert the signal components to the desired RF frequency. The analog transmit signals are amplified by a power amplifier for transmission by an antenna. IQ RFDACs suffer in general from a <NUM> decibel (dB) power penalty when converting signals with a circular boundary shape in the complex plane, compared to the minimal necessary solution (e.g., a polar RFDAC). This power penalty is caused by the fact that the maximum of the sum of I and Q is in its worst case √<NUM> times the maximum of the signal magnitude, which is the radius of a circular boundary shape.

Some IQ RFDACs are implemented with max (|I| + |Q|) number of thermometer-coded DAC cells. This architecture has its maximum efficiency at full scale and thus any reduction in the magnitude of the transmit signal causes an efficiency penalty. Therefore, decreasing PAPR of the transmit signal increases the efficiency of the RFDAC at maximum output power. Some PAPR reduction schemes limit the envelope of the instantaneous magnitude and thus require computation of the instantaneous magnitude of the transmit signal, which consumes power. Some PAPR reduction schemes may clip portions of the signal that do not exceed the RFDAC limitation boundary.

Described herein are systems, circuitries, and methods that reduce PAPR by determining a single clipping error that is subtracted from both the I and the Q value to clip I and Q values that exceed the clipping boundary. This use of a single clipping error to adjust both the I and the Q value recognizes symmetry in the clipping error. Because there is a single clipping error rather than separate I and Q clipping errors, the systems, circuitries, and methods described herein can use a single filter to filter the clipping error, reducing components and power consumption. The invention is defined in the appended independent claims.

The present disclosure will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. As utilized herein, terms "component," "system," "interface," "circuitry" and the like are intended to refer to a computer-related entity, hardware, software (e.g., in execution), and/or firmware. For example, a circuitry can be a circuit, a processor, a process running on a processor, a controller, an object, an executable, a program, a storage device, and/or a computer with a processing device.

<FIG> illustrates one example of a baseband architecture <NUM> of a transmitter that includes exemplary peak-to-average power ratio (PAPR) circuitry <NUM> and an RFDAC <NUM>. While a single RFDAC is illustrated in <FIG>, in some examples, the architecture <NUM> includes multiple RFDACs. The PAPR reduction circuitry <NUM> receives and Q values (I[k] and Q[k]) from baseband processing circuitry (not shown) and outputs a digital transmit signal corresponding to clipped I and Q values (I'[k] and Q'[k]) that decrease the PAPR of the signal processed by the RFDAC <NUM>. The RFDAC <NUM> converts the digital transmit signal (i.e., I'[k] and Q'[k]) to an analog signal that is amplified by a power amplifier (not shown) of the transmitter.

The PAPR reduction circuitry <NUM> includes clipping circuitry <NUM>, filter circuitry <NUM>, and combination circuitry <NUM>. The clipping circuitry <NUM> is configured to detemine a single clipping error e[k] that will be combined with both the I value I[k] and the Q value Q[k] to generate the clipped I and Q values I'[k] and Q'[k], The filter circuitry <NUM> filters the clipping error e[k] to generate a filtered clipping error e'[k]. Because there is a single clipping error, only a single filter circuitry <NUM> is needed. This is to be contrasted with clipping systems that generate a separate clipping error for the I and Q values, which may require two filters, one for each clipping error. The combination circuitry <NUM> combines the filtered clipping error e'[k] with the I value I[k] and the Q value Q[k] to generated a clipped I value I'[k] and a clipped Q value Q'[k],.

<FIG> illustrates one example of how a single clipping error may be determined for both an I value and a Q value. The clipping circuitry <NUM> clips the trajectory of the baseband signal I[k], Q[k] to a diamond shape representing the RFDAC limitation |I|+|Q|<=N. The clipping is implemented by projecting a complex trajectory point I[k],Q[k] lying out of the boundary defined by a clipping boundary |I|+ |Q|=X onto a nearest point I'[k], Q'[k] on the clipping boundary. <FIG> shows the projection for a point in the first quadrant (I>=<NUM>, Q=><NUM>). The clipping boundary has a <NUM>° angle in the complex plane and the projection is done <NUM>° to the clipping boundary. Thus, in this example the clipping error e[k] corresponds to the the magnitude of the vector difference between the original vector I[k],Q[k], and the projected vector I'[k], Q'[k]. The symmetry of the clipping error with respect to the I and Q values is shown by the fact that the distances D in <FIG> are equal. This means that the same clipping error may be used for both the I signal and the Q signal. Further, when an I and Q value pair falls below or within the clipping boundary, the clipped values I'[k], Q'[k] are equal to the original values (e.g., e[k] = <NUM> for that point).

<FIG> illustrates one example of a baseband architecture <NUM> of a transmitter that includes exemplary peak-to-average power ratio (PAPR) circuitry <NUM> and an RFDAC <NUM> that performs a hard clip operation on the digital transmit signal I'[k], Q'[k]. The PAPR reduction circuitry <NUM> includes clipping circuitry <NUM>, filter circuitry <NUM>, and combination circuitry <NUM>. The clipping circuitry <NUM> determines a clipping error e[k] that corresponds to the magnitude of the vector difference between I[k], Q[k] and I'[k], Q'[k] as illustrated in <FIG>. The clipping circuitry <NUM> includes circuitry or components that implement an absolute value or magnitude operation on the I value (<NUM>) and the Q value (<NUM>). This magnitude operation maps the I and Q values to the first quadrant as illustrated in <FIG>. Error circuitry <NUM> determines the clipping error e[k] clipping error to be either i) zero if the point defined by |I|, |Q| is below the clipping boundary (e.g., the line |I|+|Q|=X, where X is the clipping limit) or ii) the magnitude of the vector difference between I[k], Q[k] and I'[k], Q'[k] as illustrated in <FIG>. The clipping error e[k] is filtered by the filter circuitry <NUM> to generate e'[k].

The combination circuitry <NUM> includes sign operator circuitries <NUM>,<NUM> that apply original sign of I[k] and Q[k] to the filtered clipping error e'[k]. This compensates for the magnitude operation performed by the clipping circuitry <NUM>. In one example, the sign operator circuitries perform a <NUM>'s complement operation on the filtered clipping error e'[k] to change the sign of the filtered error when the I or Q value is negative. Combination circuitry <NUM> subtracts the filtered error signal having the same sign as I[k] from an output of a delay operator <NUM> that delays I[k]. Combination circuitry <NUM> subtracts the filtered error signal having the same sign as Q[k] from an output of a delay operator <NUM> that delaysQ[k]. The output of combination circuitry <NUM> is the clipped I signal I'[k]. The output of combination circuitry <NUM> is the clipped Q signal Q'[k]. The clipped I and Q signals together form the digital transmit signal processed by the RFDAC <NUM>.

The PAPR reduction circuitry <NUM> provides the correct clipped signal as long as two subsequent peaks that are clipped and filtered are separated in time by a longer duration than the filtering circuitry <NUM> has settling time. While this cannot be guaranteed for all signals, simulations have shown that the error made by overlapping transients of clipping errors with a partially wrong sign are small enough to be negligible and occurs at very low power spectral density (PSD).

The filtering circuitry reduces the height of the clipping error and may therefore cause peak regrowth in the final clipped signal. Therefore, in the example of <FIG> the RFDAC <NUM> includes a hard clipping function that imposes a hard limitation on the values of I'[k] and Q'[k], This hard clipping operation limits the digital transmit signal to a final boundary. The hard clipping operation can be implemented directly at the RFDAC input code.

<FIG> illustrates a flow diagram outlining one embodiment of a method <NUM> configured to clip I and Q values according to a clipping boundary. The method <NUM> may be performed by PAPR reduction circuitry <NUM>, <NUM>, of <FIG> and <FIG>, respectively. The method includes, at <NUM>, receiving an I value and a Q value. At <NUM> a clipping error between the I value and the Q value and the clipping boundary is determined. The clipping error is combined with the I value to generate a clipped I value and the Q value to generate a clipped Q value at <NUM>. At <NUM> the method includes providing the clipped I value and the clipped Q value to a power amplifier in a transmit chain.

It can be seen from the foregoing description that calculating a single clipping error and applying the clipping error to both an I signal and a Q signal reduces the number of components necessary to implement a clipping system while still providing satisfactory results.

Use of the word exemplary is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term "comprising".

To provide further context for various aspects of the disclosed subject matter, <FIG> illustrates a block diagram of an embodiment of user equipment <NUM> (e.g., a mobile device, communication device, personal digital assistant, etc.) related to access of a network (e.g., base station, wireless access point, femtocell access point, and so forth) that can enable and/or exploit features or aspects of the disclosed aspects.

The user equipment or mobile communication device <NUM> can be utilized with one or more aspects of the PAPR reduction circuitry described herein according to various aspects. The user equipment device <NUM>, for example, comprises a digital baseband processor <NUM> that can be coupled to a data store or memory <NUM>, a front end <NUM> (e.g., an RF front end, an acoustic front end, or the other like front end) and a plurality of antenna ports <NUM> for connecting to a plurality of antennas <NUM><NUM> to <NUM>k (k being a positive integer). The antennas <NUM><NUM> to <NUM>k can receive and transmit signals to and from one or more wireless devices such as access points, access terminals, wireless ports, routers and so forth, which can operate within a radio access network or other communication network generated via a network device (not shown).

The user equipment <NUM> can be a radio frequency (RF) device for communicating RF signals, an acoustic device for communicating acoustic signals, or any other signal communication device, such as a computer, a personal digital assistant, a mobile phone or smart phone, a tablet PC, a modem, a notebook, a router, a switch, a repeater, a PC, network device, base station or a like device that can operate to communicate with a network or other device according to one or more different communication protocols or standards.

The front end <NUM> can include a communication platform, which comprises electronic components and associated circuitry that provide for processing, manipulation or shaping of the received or transmitted signals via one or more receivers or transmitters (e.g. transceivers) <NUM>, a mux/demux component <NUM>, and a mod/demod component <NUM>. The front end <NUM> is coupled to the digital baseband processor <NUM> and the set of antenna ports <NUM>, in which the set of antennas <NUM><NUM> to <NUM>k can be part of the front end.

The processor <NUM> can confer functionality, at least in part, to substantially any electronic component within the mobile communication device <NUM>, in accordance with aspects of the disclosure. As an example, the processor <NUM> can be configured to execute, at least in part, executable instructions that perform the method <NUM> of <FIG> and/or compute clipping error and/or adjust the I and Q signals with the clipping error. Thus the processor <NUM> may embody various aspects of the PAPR reduction circuitry <NUM>, <NUM> of <FIG> and <FIG>. In other embodiments, the processor <NUM> or PAPR reduction circuitry includes custom hardware configured to compute the clipping error and/or adjust the I and Q signals with the clipping error.

The processor <NUM> is functionally and/or communicatively coupled (e.g., through a memory bus) to memory <NUM> in order to store or retrieve information necessary to operate and confer functionality, at least in part, to communication platform or front end <NUM>, the phase locked loop system <NUM> and substantially any other operational aspects of the phase locked loop system <NUM>. The phase locked loop system <NUM> includes at least one oscillator (e.g., a VCO, DOO or the like) that can be calibrated via core voltage, a coarse tuning value, signal, word or selection process according the various aspects described herein.

The processor <NUM> can operate to enable the mobile communication device <NUM> to process data (e.g., symbols, bits, or chips) for multiplexing/demultiplexing with the mux/demux component <NUM>, or modulation/demodulation via the mod/demod component <NUM>, such as implementing direct and inverse fast Fourier transforms, selection of modulation rates, selection of data packet formats, inter-packet times, etc. The processor <NUM> may embody the PAPR reduction circuitry (<NUM>, <NUM>, of <FIG> and <FIG>, respectively) and perform stored instructions that calculate the clipping value. Memory <NUM> can store data structures (e.g., metadata), code structure(s) (e.g., modules, objects, classes, procedures, or the like) or instructions, network or device information such as policies and specifications, attachment protocols, code sequences for scrambling, spreading and pilot (e.g., reference signal(s)) transmission, frequency offsets, cell IDs, and other data for detecting and identifying various characteristics related to RF input signals, a power output or other signal components during power generation. Memory <NUM> may include a static random access memory (SRAM) that stores various parameters used for calculating the clipping error, such as the clipping boundary (e.g., as used by the PAPR reduction circuitry of <FIG> and <FIG>).

It is to be understood that aspects described herein may be implemented by hardware, software, firmware, or any combination thereof. When implemented in software, functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

Various illustrative logics, logical blocks, modules, and circuits described in connection with aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform functions described herein. A general-purpose processor may be a microprocessor, but, in the alternative, processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Additionally, at least one processor may comprise one or more modules operable to perform one or more of the acts and/or actions described herein.

For a software implementation, techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform functions described herein. Software codes may be stored in memory units and executed by processors. Memory unit may be implemented within processor or external to processor, in which case memory unit can be communicatively coupled to processor through various means as is known in the art. Further, at least one processor may include one or more modules operable to perform functions described herein.

Further, the acts and/or actions of a method or algorithm described in connection with aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or a combination thereof. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium may be coupled to processor, such that processor can read information from, and write information to, storage medium. In the alternative, storage medium may be integral to processor. Further, in some aspects, processor and storage medium may reside in an ASIC. Additionally, ASIC may reside in a user terminal. In the alternative, processor and storage medium may reside as discrete components in a user terminal. Additionally, in some aspects, the acts and/or actions of a method or algorithm may reside as one or any combination or set of codes and/or instructions on a machine-readable medium and/or computer readable medium, which may be incorporated into a computer program product.

Claim 1:
A method configured to clip a signal according to a clipping boundary, wherein the signal comprises an I component comprising a series of I values and a Q component comprising a series of Q values, wherein each I value and Q value pair defines Cartesian coordinates of a data point being transmitted on the real and imaginary axes of the complex plane, respectively, the method comprising:
receiving (<NUM>) an I value and a Q value;
determining a magnitude of the I value (<NUM>);
determining a magnitude of the Q value (<NUM>);
determining (<NUM>) a clipping error as a vector distance between a first point defined by the magnitude of the I value and the magnitude of the Q value and a nearest point on the clipping boundary to the first point;
filtering the clipping error to generate a filtered clipping error;
combining the filtered clipping error with the I value to generate a clipped I value; and
combining the filtered clipping error with the Q value to generate a clipped Q value; and
wherein if the clipped I value or the clipped Q value exceeds a hard clipping limit, subsequently clipping the clipped I value or the clipped Q value that exceeds the hard clipping limit;
providing (<NUM>) the clipped I value and the clipped Q value to a radio frequency digital-to-analog converter, RFDAC, (<NUM>) in a transmit chain.