Patent Description:
Demand for higher performance integrated circuits (ICs) in electronic device applications has motivated increasingly dense transistor architectures. Fabricating interconnect metallization over both a front side of a transistor structure and over a back side of the transistor structure is a form of monolithic 3D integration where transistor structures are interconnected into a double-sided IC from both the front and back side. Such double-sided interconnect routing can reduce density and parasitics of the IC.

Transistor structures with different drive currents may be needed for different applications within a given IC. For finFETs architectures, one may vary the number of fins between different transistor structures to achieve different drive-currents. Gate-all-around (GAA) transistor structures, such as ribbon or wire (RoW) architectures include a plurality of channel regions that are in a vertical stack with one channel region self-aligned over another. To vary the number of channel regions, one of the GAA transistor structures may be depopulated in one stack relative to the other.

RoW depopulation techniques and double-sided transistor structures that result from such techniques may advantageously achieve different drive currents in GAA transistor structures of a double-sided IC.

Document <CIT> discloses a stacked nanowire device width adjustment.

Document <CIT> discloses a semiconductor memory device comprising stacked pull-up and pull-down transistors and a method for forming such a device.

Document <CIT> discloses a semiconductor device comprising a gate-all-around structure.

Document <CIT> discloses an I/O device scheme for gate-all-around transistors.

The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:.

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention. Reference throughout this specification to "an embodiment" or "one embodiment" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in an embodiment" or "in some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the invention.

As used in the description of the invention and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause and effect relationship).

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or layer disposed over or under another may be directly in contact or may have one or more intervening materials or layers. Moreover, one material or layer disposed between two materials or layers may be directly in contact with the two materials or layers or may have one or more intervening materials or layers. In contrast, a first material or material "on" a second material or layer is in direct contact with that second material/layer. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of" or "one or more of" can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

In accordance with some embodiments, double-sided integrated circuit transistor structures with depopulated bottom channel regions are fabricated. In accordance with the present invention, for transistor structures that have a number of channel regions arranged in a vertical stack between an overlying front-side metallization level and underlying back-side metallization level, the number of channel regions in a particular transistor structure is depopulated by removing, or otherwise deactivating, a portion of the transistor structure nearest to the back-side metallization level. For a double-sided transistor structure that is contacted from either, or both, a front side and a back side metallization level, embodiments herein are practiced to depopulate the number of channel region in a particular transistor structure during backside processing of the IC structure.

Back-side depopulation in accordance with some embodiments may avoid complications to front-side processing that would be associated with depopulating a channel from the front side of a transistor structure. Channel depopulation solutions implemented in the front-end process as part of the initial fabrication of a gate-all-around transistor (GAA) structure could further increase the complexity of the front-end process to the point of having significant IC die yield issues.

One or both of front-side and back-side channel depopulation may be practiced to arrive at a GAA transistor structure having desired operational parameters. For example, the removal or inactivation of one or more channel region in an upper portion of a transistor channel stack during initial fabrication of a GAA transistor structure may be less complicated than removal of a channel region from a lower portion the transistor channel stack. In contrast, back-side processing subsequent to an initial fabrication of a GAA transistor structure may be advantageously leveraged in the removal or inactivation of one or more channel region in a lower portion the transistor channel stack. Hence, depending from where in a channel stack a channel region is to be pruned, back-side channel depopulation in accordance with some embodiments herein may be less invasive than front-side depopulation. Indeed, even where front-side population is possible (e.g., where an upper channel region of the stack may be deactivated), it may be advantageous to instead deactivate a lower channel region of the stack so as to reduce variability in the front side features of the transistor structure.

Notably, back-side channel depopulation in accordance with embodiments herein may be employed in conjunction with front-side channel depopulation techniques, or may be employed in exclusion of front-side channel depopulation techniques to arrive at transistor structures that have fewer than a design maximum number of channel regions.

<FIG> illustrates a double-sided IC structure <NUM> that includes GAA transistor structure <NUM> having a plurality of stacked channel regions 115A-115D following back-side channel depopulation in accordance with some embodiments where bottom channel region 115A has been removed (and replaced with placeholder material), or otherwise deactivated, as represented by an "X". Transistor structure <NUM> therefore includes only three active channel regions even though transistor structure <NUM> has a design maximum of four channel regions. Where other transistors of a double-side IC structure include the design maximum channel regions, the illustrated backside depopulation may differentiate operational parameters of two transistors. Notably, all transistors of a double-side IC structure <NUM> may also be depopulated substantially as transistor structure <NUM>, for example to electrically isolate the transistor structures from an underlying feature, such as a sub-channel material, or backside metallization feature, etc..

As further illustrated in <FIG>, double-sided IC structure <NUM> includes one or more front-side metallization levels <NUM> over a "top" or "front" side of transistor structure <NUM>, and one or more back-side metallization levels <NUM> over (under) a "bottom" or "back" side of transistor structure <NUM>. Structural aspects of front-side metallization levels <NUM> and back-side metallization levels <NUM> are not depicted in <FIG> to avoid obscuring the view of transistor structure <NUM>. Front-side metallization levels <NUM> may have any known structure, and any number of levels interconnecting one or more transistor terminals with other nodes in a circuit. Similarly, back-side metallization levels <NUM> may have any known structure, and any number of levels interconnecting one or more transistor terminals with other nodes in the circuit. In some exemplary embodiments, there are more levels (e.g., <NUM>-<NUM>, or more) front-side metallization levels <NUM> than back-side metallization levels <NUM> (e.g., <NUM>-<NUM> levels). For such embodiments, front-side metallization levels <NUM> may be readily distinguished from back-side metallization levels <NUM> even where double-side IC structure <NUM> is inverted from the orientation illustrated. Regardless of orientation, depopulated/inactivated channel region 115A is nearest to back-side metallization levels <NUM>, and is therefore referred as a "bottom," or "lower," channel region. In contrast, channel region 115D is nearest front-side metallization levels <NUM> and may therefore be referred to as a "top," or "upper," channel region.

In <FIG>, two orthogonal planes are demarked by dashed line. Plane A is a "gate-cut" plane that passes through a transverse length of gate electrode <NUM> and passes through a longitudinal length of channel regions 115A-115D. Plane B is a "fin-cut" plane that passes through a transverse length of channel regions 115A-115D and passes through a longitudinal length of gate electrode <NUM>. As further illustrated, source and drain regions <NUM> are electrically and physically coupled to opposite sides of channel regions 115A-115D. In this example, source and drain regions <NUM> comprise faceted epitaxial material that has been grown, for example laterally from an end portion of channel regions 115A-115D embedded with in a spacer dielectric material <NUM>, or from cantilevered source/drain nanowire ends (e.g., 105D) drawn in dashed line.

Source and drain regions <NUM> need not be epitaxial material, in which case the illustrated facets may not be present. Source and drain regions <NUM> also need not be merged into a unitary body, in which case cantilevered source/drain nanowire ends (e.g., 105D) may be individually contacted by a terminal contact metal. In the illustrated example, back-side metallization levels <NUM> include a back-side source and drain metallization <NUM> that is in contact with source and drain regions <NUM>. Although not depicted for the sake of clarity, front-side metallization levels <NUM> may include a front-side source and/or drain contact that is similarly in contact with one or more of source and drain regions <NUM>. Likewise, front-side metallization levels <NUM> and/or back-side metallization levels <NUM> may further include a contact to gate electrode <NUM> (not depicted). Gate electrode <NUM> is between source and drain region <NUM>, with intervening spacer dielectric material <NUM> between gate electrode <NUM> and source and drain region <NUM>. Transistor structure <NUM> may further include one or more additional dielectric materials. In the illustrated example, there is a dielectric material <NUM> under gate electrode <NUM> where gate electrode <NUM> extends laterally beyond channel regions 115A-11D.

<FIG> illustrates a cross-sectional view of double-sided IC structure <NUM> along the A-A' plane introduced in <FIG>, in accordance with some embodiments. <FIG> illustrates a second cross-sectional view of the double-side IC structure <NUM> along the B-B' plane introduced in <FIG>, in accordance with some embodiments. As shown in <FIG>, IC structure <NUM> includes a transistor structure <NUM> that lacks at least one active bottom channel region. Transistor structure <NUM> is adjacent to a transistor structure <NUM> that has a full complement of active channel regions. Transistor structure <NUM> is therefore an embodiment of transistor structure <NUM> (<FIG>) including an electrically inactive channel material 215A.

Transistor structures <NUM> and <NUM> may be two transistors within any IC topology, for example where different transistor drive currents are advantageous. In some embodiments, IC structure <NUM> is a CMOS structure with transistor structure <NUM> having a first conductivity type while transistor structure <NUM> has a second, complementary conductivity type. In the illustrated example, transistor structure <NUM> is a PMOS transistor structure with source and drain region <NUM> having p-type conductivity, while transistor structure <NUM> is a NMOS transistor structure with source and drain region <NUM> having n-type conductivity. In other embodiments, transistor structure <NUM> is an NMOS transistor structure with source and drain region <NUM> having n-type conductivity, while transistor structure <NUM> is a PMOS transistor structure with source and drain region <NUM> having p-type conductivity. In other embodiments, transistor structures <NUM> and <NUM> are both PMOS transistor structures or both NMOS transistor structures.

Source and drain region <NUM>, <NUM> is coupled together through channel regions 115B, 115C and 115D. Each of channel regions 115B-115D are operable to contribute to a total drive current for transistor structures <NUM>, <NUM>. Transistor structure <NUM> includes a bottom channel region 115A that is absent from transistor structure <NUM>, and which increases the drive current of transistor structure <NUM> beyond that of transistor structure <NUM>. In the illustrated example, transistor structure <NUM> therefore has four channel regions whereas transistor structure 201sp has only three channel regions with an inactive channel material 215A in place of bottom channel region 115A. As shown in <FIG>, inactive channel material 215A is co-planar with bottom channel region 115A along a plane C demarked in dashed line. Transistor structures <NUM> and <NUM> may alternatively include any number of channel regions <NUM>. Also, while transistor structure <NUM> is illustrated as lacking bottom channel region 115A, transistor structure <NUM> may lack any number channel regions relative to a transistor having a design maximum number of channel regions, such as transistor structure <NUM>. For embodiments where more than one channel region is rendered inactive, two or more of the lowest channel regions, nearest back-side metallization levels <NUM>, may be absent with inactive channel material <NUM> then being coplanar with one or more of channel regions 115B-115C, for example.

Source/drain semiconductor region <NUM> and source/drain semiconductor region <NUM> may comprise any semiconductor material suitable for a transistor. In some embodiments, source/drain semiconductor regions <NUM>, <NUM> include impurity-doped portions of semiconductor material portions 105A-105D protruding laterally beyond channel regions 115A-115D, and denoted by dashed lines. In the illustrated embodiment, source/drain regions <NUM>, <NUM> include a unified epitaxial semiconductor source/drain structure. This unified epitaxial semiconductor source/drain structure may have been grown, for example, from semiconductor material portions 105A-105D that were cantilevered beyond spacer dielectric material <NUM>. In absence of any such cantilevered semiconductor material portions 105A-105D, a unified epitaxial source/drain semiconductor structure may have been laterally grown from surfaces of channel regions 115A-115D embedded within spacer dielectric <NUM>. Source/drain region <NUM>, <NUM> may be comprise one or more electrically active impurities. In some embodiments, for example, source/drain region <NUM> is a Group IV semiconductor material (e.g., Si, Ge, or SiGe alloy) with a p-type impurity, such as, but not limited to, boron or gallium. In some further embodiments, source/drain region <NUM> is also a Group IV semiconductor material, but with an n-type impurity, such as, but not limited to, phosphorus, arsenic, or antimony.

Channel regions 115B-115D have a longitudinal channel length LC (e.g., along y-axis) associated with a distance between source and drain region <NUM> in transistor structure <NUM>. Channel regions 115B-115D may extend through dielectric (spacer) material <NUM>, as illustrated, or not. In the illustrated example, inactive channel material 215A also has length between source and drain region <NUM> that is substantially equal to channel length LC. However, in other embodiments, inactive channel material 215A may have a longitudinal length significantly less than the channel length LC, for example where only some portion of channel length LC is electrically inactive material. Transistor structure <NUM> similarly includes channel regions 115A-115D having a longitudinal channel length (e.g., along y-axis) associated with a distance between source and drain region <NUM>.

Channel regions 115A-115D are non-planar bodies of semiconductor material that may have been patterned from a fin in a front (top) side of a substrate material layer, for example. The trapezoidal profiles illustrated for both gate electrode <NUM> and channel regions 115A-115D are representative of structural asymmetry associated with front-side transistor fabrication. Such asymmetry may be a result of feature sidewall slopes that evolve during subtractive patterning of one or more of a semiconductor fin or gate electrode. Although channel regions 115A-115D are illustrated in <FIG> as nanowires having a transverse width approximately equal to their vertical thickness, channel regions 115A-115D may instead be nanoribbons.

In some embodiments, channel regions 115A-115D are crystalline semiconductor. Although the crystalline semiconductor includes polycrystalline thin film material, the crystalline semiconductor may be advantageously substantially monocrystalline. In some such embodiments, the crystallinity of channel regions 115A-115D is cubic with the top surfaces nearest to front-side metallization levels <NUM> having crystallographic orientation of (<NUM>), (<NUM>), or (<NUM>), for example. Other crystallographic orientations are also possible. In some embodiments, channel regions 115A-115D are a substantially monocrystalline group IV semiconductor material, such as, but not limited to substantially pure silicon (e.g., having only trace impurities), silicon alloys (e.g., SiGe), germanium alloys (e.g., GeSn, SiGeSn) or substantially pure germanium (e.g., having only trace impurities). In other embodiments, channel regions 115A-115D are a Group III-V alloy semiconductor material. Channel regions 115A-115D may also have any of these same exemplary compositions in alternative polycrystalline or amorphous embodiments, for example where transistor structures <NUM>, <NUM> have been fabricated from a thin film semiconductor material layer. Alternative polycrystalline or amorphous embodiments may instead include semiconducting metal oxides, such as IGZO. Although channel regions 115A-115D are illustrated as having a substantially homogenous composition, they may alternatively comprise one or more semiconductor heterojunctions that, for example further include a first semiconductor material adjacent to a second semiconductor material.

Inactive channel material 215A is compositionally different from channel regions 115A-115D. Inactive channel material 215A may be any material that is inoperable as a channel material, at least under the gate bias voltages at which channel regions 115A-115D are operable and/or to which transistor structure <NUM> is biased during circuit operation. In some exemplary embodiments, inactive channel material 215A is a dielectric material. Suitable dielectric materials include, but are not limited to, silicon dioxide, a low-k dielectric (e.g., SiOC), silicon oxynitride, silicon nitride, or an even high-k dielectric (e.g., metal oxide).

As further illustrated in <FIG>, transistor structures <NUM> and <NUM> have substantially the same gate electrode height H1. Below height H1, transistor structure <NUM> includes a sub-channel material <NUM> extending a height H2 from a nearest one of back-side metallization levels <NUM>. Sub-channel material <NUM> is under the stack of channel regions 115A-115D, under gate electrode <NUM>, and may be a base of a fin, for example, from which channel regions 115A-115D were formed. As such, sub-channel material <NUM> may have a composition and/or microstructure similar to channel regions <NUM>-115D. For example, in some embodiments where channel regions 115A-115D are of a Group IV material (e.g., silicon), sub-channel material <NUM> is also a Group IV material (e.g., silicon). n some further embodiments where channel regions 115A-115D are substantially monocrystalline, sub-channel material <NUM> is also substantially monocrystalline, and has the same crystallinity and/or crystal orientation as that of channel regions 115A-115D.

In addition to lacking channel region 115A, transistor structure <NUM> also lacks sub-channel material <NUM>. As shown, inactive channel material 215A is in place of both sub-channel material <NUM> and channel region 115A, having a height H3 from back-side metallization levels <NUM>. In other words, inactive channel material 215A is coplanar with both sub-channel material <NUM> and channel region 115A. In the illustrated example, within transistor structure <NUM>, inactive channel material 215A also occupies a region where a bottom portion of the gate stack resides within transistor structure <NUM>. As such, for transistor structure <NUM>, spacing between a given one of back-side interconnect metallization levels <NUM> and a nearest one of channel regions 115B-115D is greater than height H3. In contrast, for transistor structure <NUM>, spacing between the given one of back-side interconnect metallization levels <NUM> and a nearest one of channel regions 115A-115D is less than height H3.

As further described below, transistor structure <NUM> may have been modified from a transistor structure that was substantially the same as transistor structure <NUM> through selective back-side processing that has removed sub-channel material <NUM>, as well as channel region 115A, and replaced it with inactive channel material 215A. Notably, channel regions 115B-115D of transistor structure <NUM> remain advantageously unaltered from their counterpart regions of transistor structure <NUM>, which is one of the advantages of back-side channel depopulation in accordance with embodiments herein.

As further shown in <FIG>, transistor structures <NUM> and <NUM> include a gate stack further including gate electrode <NUM> and a gate dielectric <NUM> cladding channel regions <NUM>-115D to provide gate-all-around control of channel conductivity. Gate dielectric <NUM> may be any dielectric material(s) known to be suitable as an insulator of a gate electrode, such as, but not limited to SiO2, SiONx. In some exemplary embodiments, gate dielectric <NUM> includes a high-k material (with a bulk relative permittivity greater than <NUM>). Exemplary high-k materials include metal oxides, such as, but not limited to a metal oxide comprising predominantly aluminum (e.g., Al2O3), a metal oxide comprising predominantly magnesium (e.g., MgO), a metal oxide comprising predominantly lanthanum (e.g., La2O3), a metal oxide comprising predominantly hafnium (e.g., HfO2), or an alloy metal oxide comprising significant portions of two or more of these metals (e.g., HfAlOx). In some further embodiments, the high-k material further includes silicon. For example, metal silicates, such as, but not limited to HfSiOx, or TaSiOx may also be suitable for some semiconductor compositions (e.g., Si, Ge, SiGe, III-V). Some specific examples of high-k gate dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

In the illustrated embodiment, the gate electrode <NUM> is shown as a single monolithic layer. However, gate electrode <NUM> may comprise a workfunction metal over the gate dielectric <NUM>, and a compositionally distinct fill metal. An n-type workfunction metal may have a workfunction between about <NUM> eV and about <NUM> eV, for example. Suitable n-type work function metals include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and metal carbides that include these elements (e.g., titanium carbide, zirconium carbide, tantalum carbide, hafnium carbide and aluminum carbide). A p-type workfunction metal may have a workfunction between about <NUM> eV and about <NUM> eV, for example. Suitable p-type materials include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide).

<FIG> illustrates a cross-sectional view of double-sided IC structure <NUM> along the A-A' plane introduced in <FIG>, in accordance with some alternative embodiments. <FIG> illustrates a second cross-sectional view of the double-side IC structure <NUM> along the B-B' plane introduced in <FIG>, in accordance with the alternative embodiments. As shown in <FIG>, IC structure <NUM> includes a transistor structure <NUM> that lacks at least one active bottom channel region. Transistor structure <NUM> is again adjacent to transistor structure <NUM> that has the full complement of active channel regions. Transistor structure <NUM> is therefore an alternative embodiment of transistor structure <NUM> (<FIG>) that includes an electrically inactive channel material 315A.

Transistor structures <NUM> and <NUM> may be two transistors within any IC topology, for example where different transistor drive currents are advantageous. In some embodiments, IC structure <NUM> is a CMOS structure with transistor structure <NUM> having a first conductivity type while transistor structure <NUM> has a second, complementary conductivity type. In the illustrated example, transistor structure <NUM> is a PMOS transistor structure with source and drain region <NUM> again having p-type conductivity, while transistor structure <NUM> is an NMOS transistor structure with source and drain region <NUM> again having n-type conductivity. In other embodiments, transistor structure <NUM> is an NMOS transistor structure with source and drain region <NUM> having n-type conductivity, while transistor structure <NUM> is a PMOS transistor structure with source and drain region <NUM> having p-type conductivity. In other embodiments, transistor structures <NUM> and <NUM> are both PMOS transistor structures or both NMOS transistor structures.

Transistor structures <NUM> share many of the structural elements described above for transistor structures <NUM> and <NUM>. The reference numbers introduced in <FIG> are retained in <FIG> for structural features in transistor structures <NUM> that have a direct analog in transistor structures <NUM> and <NUM>. As in transistor structure <NUM>, transistor structure <NUM> lacks a bottom channel region 115A, however there is an inactive channel material 315A that has been derived from the channel region material. For this embodiment, inactive channel material 315A may have a less dramatically different composition and/or microstructure than channel regions 115A-115D. For example, in some embodiments where channel regions 115B-115D are substantially monocrystalline, inactive channel material 315A is also substantially monocrystalline, and has the same crystallinity and/or crystal orientation as that of channel regions 115B-115D. In some embodiments, inactive channel material 315A has a greater concentration of impurities that render inactive channel material 315A inoperable as a channel material, at least under the gate bias voltages at which channel regions 115A-115D are operable. Except for the greater impurity concentration, inactive channel material 315A may be substantially the same material as channel regions 115B-115D. For example, where channel regions 115B-115D are a Group IV semiconductor material (e.g., predominantly silicon), inactive channel material 315A may also be the Group IV semiconductor material, but impurity doped to have a threshold voltage that renders inactive channel material 315A in an "off" state under all gate bias voltages that transistor structure <NUM> may experience during circuit operation.

In some embodiments, inactive channel material 315A includes an electrically active impurity that results in inactive channel material 315A having a conductivity type complementary to source/drain region <NUM>. For example, where transistor structure is a PMOS device and source/drain material have p-type conductivity, inactive channel material 315A may be n-type. Complementary doping may provide junction isolation with source and drain region <NUM>. Suitable impurities for an n-type inactive silicon channel material 315A of a PMOS device include, but are not limited to, phosphorus, arsenic, or antimony. P-type inactive channel material 315A is also possible. For example, where transistor structure <NUM> is instead an NMOS device, suitable impurities for an inactive p-type silicon channel material 315A include, but are not limited to, boron or gallium or indium.

Although the impurity concentration level may vary widely, in some exemplary embodiments, inactive channel material 315A has an impurity concentration in excess of 1e19 atoms/cm3 (e.g., approximately 1e20 atoms/cm3, or more). In the illustrated embodiment, substantially the entire channel length LC is impurity doped into inactive channel material 315A. For such embodiments, a co-planar portion of source/drain regions <NUM> (e.g., along plane C in <FIG>) may also be counter-doped with the same impurity present within inactive channel material 315A. Alternatively, a longitudinal length significantly less than channel length LC may be impurity doped into inactive channel material 315A. The longitudinal length of inactive channel material 315A should however at least be sufficient to avoid significant source-to-drain leakage through inactive channel material 315A.

As further illustrated in <FIG>, transistor structure <NUM> includes sub-channel material <NUM> extending a height H2 from back-side metallization levels <NUM>. As noted above, sub-channel material <NUM> may be a base of a fin, for example, from which inactive channel material 315A and channel regions 115B-115D were formed. As such, sub-channel material <NUM> may have a composition and/or microstructure similar to channel regions 115B-115D. For example, in some embodiments where channel regions 115B-115D are of a Group IV material (e.g., silicon), sub-channel material <NUM> is also a Group IV material (e.g., silicon). In some further embodiments where channel regions 115B-115D are substantially monocrystalline, sub-channel material <NUM> is also substantially monocrystalline, and has the same crystallinity and/or crystal orientation as that of channel regions 115B-115D.

Notably, a significant impurity concentration may be advantageously limited to inactive channel material 315A with channel region 115B remaining operable with an associated threshold voltage. In exemplary embodiments, the concentration of the impurity present in inactive channel material 315A is at least two orders of magnitude lower within channel regions 115B-115D, and may be advantageously three orders of magnitude, or more. Hence, channel regions 115B-115D (as well as channel region 115A of transistor structure <NUM>) may be substantially undoped by the impurity present within inactive channel material 315A. A steep impurity gradient along the height H3 may therefore be present within transistor structure <NUM> with no such impurity along the height H3 in transistor structure <NUM>. Sub-channel material <NUM> may, in contrast, be doped with the impurity present within inactive channel material 315A. For example, where the inactive channel material impurity is complementary to impurities in source/drain region <NUM>, inclusion of a significant impurity concentration within sub-channel material <NUM> may also improve electrical isolation of sub-channel material <NUM>. Sub-channel material <NUM> may alternatively have a significantly lower concentration of the impurity found in inactive channel material 315A.

In some embodiments, inactive channel material 315A has a lower degree of crystallinity that channel regions 115B-115D. Lesser long range order within inactive channel material 315A may help to confine impurities to within the inactive channel material 315A, increasing the impurity gradient along the height H3. In addition to being more amorphous, inactive channel material 315A may include one or more amorphizing impurities, such as silicon or germanium or argon or xenon or krypton or tin. For some embodiments where channel regions 115B-115D comprise predominantly silicon, the presence of germanium within inactive channel material 315A is indicative of a targeted amorphization. For other embodiments where channel regions 115B-115D comprise predominantly germanium, the presence of silicon within inactive channel material 315A is likewise indicative of a targeted amorphization. Such impurities within a majority Group IV semiconductor may impart significant lattice damage that reduces the crystallinity of inactive channel material 315A below that of channel regions 115B-115D. Although most lattice damage will occur where an amorphizing impurity comes to rest (e.g., within inactive channel material 315A), sub-channel material <NUM> may also incur some lesser degree of lattice damage and may also comprise some lower concentration of the one or more amorphizing impurities found at a higher concentration within inactive channel material 315A. Amorphizing impurities are advantageously substantially absent from channel regions 115B-115D (as well as 115A in transistor structure <NUM>). So, in addition to greater crystallinity, channel regions 115B-115D may have a much lower amorphizing impurity concentration than inactive channel material 315A.

As further described below, transistor structure <NUM> may have been modified from a transistor structure that was substantially the same as transistor structure <NUM> through selective back-side implantation of impurities (electrically active or amorphizing) into channel region 115A, converting it into inactive channel material 315A. Notably, channel regions 115B-115D of transistor structure <NUM> remain advantageously unaltered from their counterpart regions of transistor structure <NUM>. For example, a lack of crystal damage (i.e., high degree of crystallinity) and low (e.g., intrinsic levels) of impurities within channel regions 115B-115D are indicative of back-side channel depopulation in accordance with embodiments herein.

The ability to vary drive current across different transistors within a single IC may take a variety of forms and have a number of advantages. For example, assist circuitry that would otherwise be required to accommodate a uniform drive current across all transistors may be avoided. Drive current modulation through backside channel depopulation in accordance with some embodiments herein may be particularly beneficial to SRAM cells of a double-sided IC. <FIG> is a plan view layout of a six-transistor (<NUM>-T) SRAM cell that includes multiple transistor structures, at least one of the transistor structures including a first number active channel regions, and at least a second of the transistor structures including a second number of active channel regions, in accordance with some embodiments. In SRAM cell <NUM>, a plurality of channel regions <NUM> and gate electrodes <NUM> are interconnected by both front-side and back-side metallization levels (not depicted).

SRAM cell <NUM> comprises a pair of PMOS pull-up transistors (PU1 and PU2), a pair of NMOS pass-gate transistors (PG1 and PG2), and a pair of NMOS pull-down transistors (PD1 and PD2). In a typical architecture (i.e., where all transistors have the same number of channel regions), the read stability and write-ability can be unbalanced, and assist circuitry (not shown) is needed. However, in accordance with some embodiments, the PU1 and PU2 transistors have the transistor structure <NUM> or <NUM> while PG1 and PG2 and PD1 and PD2 all have transistor structure <NUM>. Hence, the drive strength of the PU transistors will be less than that of the PD and PG transistors. As such, better balance between the read stability and write-ability may be provided, potentially eliminating the need for assist circuits, and reducing IC area and/or IC power consumption.

<FIG> is a cross-sectional view through a first plurality of transistors in the <NUM>-T SRAM cell <NUM> along the B1-B1' line, in accordance with some embodiments. <FIG> is a cross-sectional view through a second plurality of transistors in the <NUM>-T SRAM cell <NUM> along the B2-B2' line, in accordance with some embodiments. As shown, the PG1, PG2, PD1, and PD2 transistors each have the design maximum number (e.g., four) of channel regions (e.g., 115A-115D). The PU1 and PU2 transistors each have an inactive channel material 215A and less than the design maximum number of channel regions (e.g., only three channel regions 115B-115D). In alternative embodiments, PU1 and PU2 transistors each instead have at least one inactive channel material 315A, for example having the transistor structure <NUM> rather than transistor structure <NUM>.

The transistor structures lacking a bottom channel region described above may be fabricated according to a number of techniques. <FIG> is a flow diagram illustrating methods <NUM> for depopulating one or more bottom channel regions of a RoW transistor structure, in accordance with some embodiments. <FIG> illustrate cross-sectional views of two transistor structures in a double-side IC structure evolving during the practice of methods <NUM> to provide a different number of channel regions in transistor structures <NUM> and <NUM> (<FIG>).

Referring first to <FIG>, methods <NUM> begin at input <NUM> where an IC workpiece with a ribbon or wire (RoW) transistor structures is received. In exemplary embodiments, the IC workpiece includes a plurality of RoW transistor structures over an area of substrate, such as a semiconductor wafer, that is to become in IC chip. The IC workpiece may be substantially complete through both a front-end-of-line process (FEOL) where the transistor structures were fabricated, and a back-end-of-line process (BEOL) where front-side metallization levels interconnecting the transistor structures have been completed.

At block <NUM>, a front side of the IC workpiece is bonded, at least temporarily, to a handle or host substrate. Any bonding technique (e.g., wafer-level) suitable for the IC workpiece may be performed at block <NUM>. In the example illustrated in <FIG>, a suitable host substrate <NUM> has been bonded to an uppermost material layer of front-side metallization levels <NUM>. Front-side metallization levels <NUM> is illustrated in dashed line to emphasize front-side metallization levels <NUM> may include any number of BEOL interconnect metallization levels. With host substrate <NUM> supporting the IC workpiece, the composite IC workpiece may be inverted, as further illustrated in <FIG>, to subject a back-side of a donor substrate <NUM> to back-side processing.

Returning to <FIG>, methods <NUM> continue at block <NUM> where the back-side processing proceeds with removal or thinning of the host substrate to reveal a back side of transistor structures within the IC workpiece. <FIG> further illustrates an example where at least a portion of a donor substrate <NUM> has been removed exposing a back-side of sub-channel material <NUM>. Removal of donor substrate <NUM> may entail a polish (e.g., CMP) and/or a wet or dry (e.g., plasma) etch process. Any grind, polish, and/or wet/dry etch process known to be suitable for the composition of the donor substrate <NUM> may be employed. For example, where the carrier layer is a group IV semiconductor (e.g., silicon) a CMP slurry known to be suitable for thinning the semiconductor may be employed. Likewise, any wet etchant or plasma etch process known to be suitable for thinning the group IV semiconductor may also be employed.

In some embodiments, removal of donor substrate <NUM> entails a cleaving or fracture process that removes a substantial portion of the donor substrate thickness, reducing the polish or etch time required. For example, donor substrate <NUM> is <NUM>-<NUM> of, for example, silicon, <NUM>-<NUM> may be cleaved off by practicing any blanket implant known to promote a wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the donor substrate where the fracture plane is desired. Donor substrate material removal may be continued until an endpoint criteria is met. As further illustrated in <FIG>, for example, donor substrate material removal may be terminated upon exposing dielectric material <NUM>, which surrounds some portion of sub-channel material <NUM>.

Returning to <FIG>, methods <NUM> continue to block <NUM> where a bottom number of channel regions are removed with one or more etch process suitable for the materials encountered during a back-side recess etch. In the example further illustrated in <FIG>, a back-side etch process selective to sub-channel material <NUM> has been employed to form a recess <NUM> that exposed a back side of gate electrode <NUM>. Recess <NUM> is further advanced through a back-side (bottom) thickness of gate electrode <NUM>, for example with another etch process that is selective to the composition of gate electrode <NUM>. Recess <NUM> is further advanced through a back-side (bottom) thickness of gate dielectric <NUM>, which exposes a back-side of channel region 115A illustrated in dash line. Channel region 115A is also etched away, for example with any etch process (wet chemical or dry plasma) suitable for the composition of channel region 115A (e.g., silicon, SiGe, Ge, etc.). With channel region 115A removed, advancement of recess <NUM> may halted, or continued to remove one or more additional channel regions 115B-115D, to complete block <NUM> (<FIG>). Notably, in the illustrated example the backside recess etching is substantially self-aligned, requiring only an etch mask that protects adjacent transistor structures that are to retain the design maximum number of channel regions.

Methods <NUM> continue to block <NUM> where the recess formed at block <NUM> is backfilled with a material that will be electrically inactive. For example, in some embodiments, the channel regions removed from a transistor structure at block <NUM> are replaced with a dielectric material. In the example illustrated in <FIG>, electrically inactive channel material 215A is deposited into recess <NUM>. Any suitable deposition process and/or planarization process may be employed to at least partially backfill recess <NUM>.

Returning to <FIG> with one or more transistor structures now depopulated of one or more lower channel regions, methods <NUM> end at output <NUM> where a back-side interconnect metallization levels of the IC workpiece are completed. Any other back-side processing may also be completed to arrive at a final double-side IC structure. In the example illustrated in <FIG> (which is along the A-A' plane of <FIG>), back-side source/drain contact metallization <NUM> is formed as a first of one or more back-side metallization levels <NUM>. In some embodiments the formation of back-side source/drain contact metallization <NUM> entails an (e.g., unmasked, self-aligned) etch of dielectric material <NUM> with an etchant that is selective to the composition of dielectric material <NUM> relative to that of inactive channel material 215A. Any metal deposition process and planarization process may then be practiced to arrive at the transistor structures <NUM> and <NUM>.

<FIG> is a flow diagram illustrating methods <NUM> for depopulating one or more bottom channel regions of a RoW transistor structure, in accordance with some alternative embodiments relying on ion implantation from a back side of an IC workpiece. <FIG> illustrate cross-sectional views of two transistor structures in a double-side IC structure evolving during the practice of methods <NUM> to provide a different number of active bottom channel regions in transistor structures <NUM> and <NUM> (<FIG>).

Referring first to <FIG>, methods <NUM> again begin at input <NUM> where an IC workpiece with RoW transistor structures is received. In exemplary embodiments, the IC workpiece includes a plurality of RoW transistor structures over an area of substrate, such as a semiconductor wafer, that is to become in IC chip. The IC workpiece may be substantially complete through both a front-end-of-line process (FEOL) where the transistor structures were fabricated, and a back-end-of-line process (BEOL) where front-side metallization levels interconnecting the transistor structures have been completed.

At block <NUM>, a front side of the IC workpiece is bonded, at least temporarily, to a host or handle substrate. Any bonding technique (e.g., wafer-level) suitable for the IC workpiece may be performed at block <NUM>, substantially as described above. Methods <NUM> continue at block <NUM> where the host substrate is removed to reveal a back side of transistor structures within the IC workpiece, for example substantially as described above, to arrive at the exemplary structure further illustrated in <FIG>.

Returning to <FIG>, methods <NUM> proceed to block <NUM> where one or more ion implantations are performed to implant one or more impurities into a number of transistor channel regions. In some embodiments, a pre-amorphization implant is performed from the back side of the IC workpiece so that the species is implanted through a depth of the transistor to come to rest within one or more of the lower channel regions that are to be electrically deactivated. In some further embodiments, one or more impurities that can be eclectically activated may be similarly implanted from the back side of the IC workpiece so that the impurity similarly comes to rest within one or more of the lower channel regions that are to be electrically deactivated. In the example further illustrated in <FIG>, an n-type impurity (n-) is illustrated as being implanted to achieve a concentration profile qualitatively represented as peaking at a plane of channel region 115A within one of the transistor structures. An amorphization species concentration may be implanted to achieve a similar impurity concentration profile.

In some embodiments, a pre-amorphization species is implanted into the transistor structure, through any sub-channel material exposed on the back side. Species implantation may be with an incident angle that is substantially normal to a back-side surface of the transistor structures (i.e., with no tilt). As such, the pre-amorphization and/or electrically active dopant species will only enter the channel regions through the bottom channel region 115A. The energy of the implantation process may be chosen to isolate the majority of the pre-amorphization and/or electrically active dopant species within the bottom channel region 115A. For example, an implantation energy of a silicon or germanium pre-amorphization species may be between approximately 1keV and approximately 2keV. Such an implant may induce a change in crystallinity of channel region 115A. Notably, additional channel regions 115B-115D (from the bottom-up) may also be altered to amorphize more than one channel region.

Implanted dopants that can be electrically activated similarly only enter the stack through the back side, encountering a desired number of bottom channel regions. In embodiments where a pre-amorphization implant is performed, a secondary implant may be subsequently performed without an annealing process between the two implant processes. As such, the disrupted crystal structure of channel region 115A is maintained and the n-species concentration profile may be made more peaked to ensure channel region 115B may remain active.

In some embodiments, the n- impurity is implanted with an energy in the range of <NUM>-2keV. However, a higher energy may be employed to increase impurity concentrations deeper into the IC workpiece, for example within an additional number of channel regions (e.g., 115B-115D). In some further embodiments, sub-channel material <NUM> may also be impurity doped by the back-side implantation employed to deactivate one or more channel regions. Notably, the only mask required during the backside implantation process(es) is one which protects various adjacent structures that are to retain a full complement of channel regions. Following the impurity implant, a short (flash) activation anneal may be performed to electrically active some percentage of the impurities implanted into channel region 115A sufficient to render it inactive channel material 315A, as illustrated in <FIG>.

Returning to <FIG> with one or more one or more lower channel regions now electrically deactivated, methods <NUM> complete at output <NUM> where back-side interconnect metallization levels of the IC workpiece are completed. Any other back-side processing may also be completed to arrive at a final double-side IC structure. In the example illustrated in <FIG> (which is along the A-A' plane of <FIG>), back-side source/drain contact metallization <NUM> has been formed as a first of one or more back-side metallization levels <NUM>. In some embodiments, formation of back-side source/drain contact metallization <NUM> entails an (unmasked, self-aligned) etch of dielectric material <NUM> with an etchant that is selective to the composition of dielectric material <NUM> relative to that of inactive channel material 315A (e.g., selective to n-type silicon). Any metal deposition process and planarization process may then be practiced to arrive at the transistor structures <NUM> and <NUM> substantially as described above.

<FIG> is a cross-sectional view of a double-sided IC structure <NUM>, in accordance with some embodiments. Double-sided IC structure <NUM> illustrates a portion of a monolithic IC that includes FEOL interconnect metallization levels <NUM> over and/or on a front side of transistor structures <NUM> that include RoW transistor structures, one or more of which have been depopulated of one or more lower (back-side) channel regions.

Within double-sided IC structure <NUM>, front-side interconnect metallization levels <NUM> include interconnect metallization <NUM> electrically insulated by dielectric material <NUM>. In the exemplary embodiment illustrated, front-side interconnect metallization levels <NUM> includes metal-one (M1), metal-two (M2), metal-three (M3) and metal-n (Mn) interconnect metallization levels. Interconnect metallization <NUM> may be any metal(s) suitable for IC interconnection. Interconnect metallization <NUM>, may be, for example, an alloy of predominantly Cu, an alloy of predominantly W, an alloy of predominantly Ru, an alloy of predominantly Al, an alloy of predominantly Mo, etc. Dielectric material <NUM> may be any dielectric material known to be suitable for electrical isolation of monolithic ICs. In some embodiments, dielectric material <NUM> comprises silicon, and at least one of oxygen and nitrogen. Dielectric material <NUM> may be SiO, SiN, or SiON, for example. Dielectric material <NUM> may also be a low-K dielectric material (e.g., having a dielectric constant below that of SiO2).

Double-sided IC structure <NUM> further includes back-side interconnect metallization levels <NUM>. Within interconnect metallization levels <NUM>, interconnect metallization <NUM> is again electrically insulated by dielectric material <NUM>. Back-side metallization levels <NUM> may comprise any number of metallization levels over, or on, a back side of transistor structures <NUM>. In the illustrated example back-side metallization levels <NUM> include a metallization level M1' through nearest to transistor structures <NUM> (e.g., opposite M1) through an uppermost back-side metallization level Mn'.

Although IC structure <NUM> includes one level of transistor structures <NUM>, there may be multiple levels of transistor structures located within the various interconnect metallization levels, for example where a front-side metallization level of one IC structure has been bonded to a back-side metallization level of another IC structure to arrive at a composite 3DIC.

In the example shown in <FIG>, transistor structures <NUM> includes one or more PMOS GAA transistor structures having a smaller number of channel regions than one or more NMOS GAA transistor structures. In other embodiments, one or more NMOS GAA transistor structures have a smaller number of channel regions than one or more PMOS GAA transistor structures. In other embodiments, one or more first PMOS GAA transistor structures have a smaller number of channel regions than one or more second PMOS GAA transistor structures. In still other embodiments, one or more first NMOS GAA transistor structures have a smaller number of channel regions than one or more second NMOS GAA transistor structures. For any of the GAA transistor structure having few channel regions, one or more lower channel regions may have been depopulated according to any of the back-side techniques described herein to arrive at any of the structures described elsewhere herein.

The transistor structures with varying number of channel regions, and the methods of back-side channel depopulation described herein may be integrated into a wide variety of ICs and computing systems that include such ICs. <FIG> illustrates a system in which a mobile computing platform <NUM> and/or a data server machine <NUM> employs an IC with including a double-sided memory and/or microprocessor IC with depopulated RoW transistor structures, for example in accordance with some embodiments described elsewhere herein. The server machine <NUM> may be any commercial server, for example including any number of high-performance computing platforms within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a monolithic IC <NUM>. The mobile computing platform <NUM> may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform <NUM> may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level integrated system <NUM>, and a battery <NUM>.

Whether disposed within the integrated system <NUM> illustrated in the expanded view <NUM>, or as a stand-alone packaged chip within the server machine <NUM>, IC <NUM> may include memory circuitry (e.g., RAM), and/or a logic circuitry (e.g., a microprocessor, a multi-core microprocessor, graphics processor, or the like) at least one of which further includes one or more back-side depopulated RoW transistor structures, for example in accordance with some embodiments described elsewhere herein. IC <NUM> may be further coupled to a board, a substrate, or an interposer <NUM> that further hosts one or more additional ICs, such as power management IC <NUM> and radio frequency IC <NUM>. RFIC <NUM> may have an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE <NUM> family), WiMAX (IEEE <NUM> family), IEEE <NUM>, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond.

<FIG> is a functional block diagram of an electronic computing device <NUM>, in accordance with some embodiments. Device <NUM> further includes a motherboard <NUM> hosting a number of components, such as, but not limited to, a processor <NUM> (e.g., an applications processor). Processor <NUM> may be physically and/or electrically coupled to motherboard <NUM>. In some examples, processor <NUM> is part of a monolithic IC structure including one or more back-side depopulated RoW transistor structures, as described elsewhere herein. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips <NUM> may also be physically and/or electrically coupled to the motherboard <NUM>. In further implementations, communication chips <NUM> may be part of processor <NUM>. Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to motherboard <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM <NUM>), non-volatile memory (e.g., ROM <NUM>), flash memory (e.g., NAND or NOR), magnetic memory (MRAM <NUM>), a graphics processor <NUM>, a digital signal processor, a crypto processor, a chipset <NUM>, an antenna <NUM>, touchscreen display <NUM>, touchscreen controller <NUM>, battery <NUM>, audio codec, video codec, power amplifier <NUM>, global positioning system (GPS) device <NUM>, compass <NUM>, accelerometer, gyroscope, speaker <NUM>, camera <NUM>, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth, or the like.

Communication chips <NUM> may enable wireless communications for the transfer of data to and from the computing device <NUM>. Communication chips <NUM> may implement any of a number of wireless standards or protocols, including, but not limited to, those described elsewhere herein. As discussed, computing device <NUM> may include a plurality of communication chips <NUM>. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.

The following examples are provided as additional information. They are not to be construed as defining the invention. The invention is defined in the claims.

In first examples, an integrated circuit (IC) structure comprises a first interconnect metallization level, a second interconnect metallization level, and first and second transistor structures between the first interconnect metallization level and the second interconnect metallization level. The first transistor structure comprises a first gate electrode around a stack of a first number of channel regions. The second transistor structure comprises a second gate electrode around a stack of a second number of channel regions, greater than the first number of channel regions. A first spacing between the second interconnect metallization level and a nearest one of the first number of channel regions is greater than a second spacing between the second interconnect metallization level and a nearest one of the second number of channel regions.

In second examples, for any of the first embodiments, the first transistor structure further comprises a first source region coupled to a first drain region through the first number of channel regions, and the first source region and the first drain region have a first conductivity type. The second transistor structure further comprises a second source region coupled to a second drain region through the second number of channel regions, the second source region and the second drain region have a second conductivity type, complementary to the first conductivity type.

In third examples, for any of the first through second examples an IC structure further comprises an inactive semiconductor material between the nearest one of the first number of channel regions and the second interconnect metallization level. The inactive semiconductor material is substantially coplanar with the nearest one of the second number of channel regions, and the inactive semiconductor material has the second conductivity type with an impurity concentration exceeding that in the first number of channel regions.

In fourth examples, for any of the first through third examples the first channel regions have a first channel length between the first source and the first drain, and the inactive semiconductor material also has the first channel length.

In fifth examples, for any of the first through fourth examples, the first transistor structure is a PMOS transistor structure and the first conductivity type is p-type. The second transistor structure is an NMOS transistor structure and the second conductivity type is n-type. The impurity comprises at least one of P, Ar, or Sb, and the impurity concentration is at least 1e19cm-<NUM>.

In sixth examples, for any of the third examples the IC structure further comprises a monocrystalline material between the second interconnect metallization level and the nearest one of the first number of channel regions. The monocrystalline material is also between the second interconnect metallization level and the nearest one of the second number of channel regions.

In seventh examples, for any of the sixth examples, the monocrystalline material has a lower concentration of the impurity than the inactivated semiconductor material.

In eighth examples for any of the second examples the IC structure further comprises a dielectric material between the nearest one of the first number of channel regions and the second interconnect metallization level. The dielectric material is substantially coplanar with the nearest one of the second number of channel regions.

In ninth examples, for any of the eighth examples the dielectric material is between a portion of the first source region and a portion of the first drain region.

In tenth examples, for any of the ninth examples the first number of channel regions have a first channel length, and the dielectric material has at least the first channel length.

In eleventh examples, for any of the ninth through tenth examples the second metallization level is coupled to at least one of the first source region or the first drain region through a contact metallization located between the second metallization level and a portion of the first source or the first drain that is adjacent to the dielectric material.

In twelfth examples, a static random access memory (SRAM) cell structure comprises a pair of pull-up transistor structures. Individual ones of the pull-up transistor structures comprise a gate electrode around individual ones of a first number of channel regions in a stack. The SRAM cell structure further comprises a pair of pull-down transistor structures. Individual ones of the pull-down transistor structures comprise a gate electrode around individual ones of a second number of channel regions in a stack. The SRAM cell structure further comprises a pair of pass-gate transistor structures. Individual ones of the pass-gate transistor structures comprise a gate electrode around individual ones of a third number of channel regions in a stack. The SRAM cell structure further comprises a first interconnect metallization level over a first side of the transistor structures and coupled to one or more of the pass-gate, pull-up, or pull-down transistor structures. The SRAM cell structure further comprises a second interconnect metallization level under a second side of the transistor structures and coupled to one or more of the pass-gate, pull-up, or pull-down transistor structures. The first number of channel regions is less than both the second number of channel regions and the third number of channel regions. A first spacing between the second interconnect metallization level and a nearest one of the first number of channel regions is greater than a second spacing between the second interconnect metallization level and a nearest one of the second number of channel regions.

In thirteenth examples, for any of the twelfth examples the pull-up transistor structure further comprises an inactive semiconductor material or dielectric material between a portion of a source region and a drain region further coupled to the first number of channel regions.

In fourteenth examples, for any of the thirteenth examples the computer system comprises a power supply and an IC die coupled to the power supply, the IC die comprising the integrated circuit (IC) structure of the first through eleventh examples.

In fifteenth examples, for any of the thirteenth through fourteenth examples, the computer system further comprises a battery coupled to the power supply.

In sixteenth examples, a method of fabricating an IC structure comprises receiving a workpiece comprising transistor structures and front-side interconnect metallization, the transistor structures comprising a stack of a first number of channel regions. The method comprises exposing a back side of the transistor structures by removing or thinning a back-side substrate from the workpiece. The method further comprises removing or disabling one or more of the channel regions nearest to the back-side of the workpiece in at least one of the transistor structures.

In seventeenth examples, for any of the sixteenth examples removing or disabling one or more of the channel regions comprises implanting an impurity into at least one of the transistor structures from the back side.

In eighteenth examples, for any of the seventeenth examples the implanting is to depth that includes only one of the channel regions.

In nineteenth examples, for any of the sixteenth examples removing or disabling one or more of the channel regions comprises exposing a first of the channel regions by etching through one or more materials from the back side of at least one of the transistor structures, and removing at least a portion of the first of the channel regions.

In twentieth examples, for any of the nineteenth examples, the method further comprises at least partially backfilling a recess where the first of the channel regions was removed with a dielectric material.

In twenty first examples, a computer system comprises a power supply and an IC die coupled to the power supply, the IC die comprising the integrated circuit (IC) structure of any one of the first through eleventh examples.

Claim 1:
An integrated circuit, IC, structure (<NUM>), comprising:
a first interconnect metallization level (<NUM>);
a second interconnect metallization level (<NUM>); and
first (<NUM>; <NUM>) and second (<NUM>; <NUM>) transistor structures between the first interconnect metallization level (<NUM>) and the second interconnect metallization level (<NUM>), wherein:
the first transistor structure (<NUM>; <NUM>) comprises a first gate electrode around a stack of a first number of channel regions;
the second transistor structure (<NUM>; <NUM>) comprises a second gate electrode around a stack of a second number of channel regions, greater than the first number of channel regions; and
a first spacing between the second interconnect metallization level and a nearest one of the first number of channel regions is greater than a second spacing between the second interconnect metallization level and a nearest one of the second number of channel regions;
wherein the first interconnect metallization level (<NUM>) is over a top of the first (<NUM>; <NUM>) and second (<NUM>; <NUM>) transistor structures; and
wherein the second interconnect metallization level (<NUM>) is under a bottom of the first (<NUM>) and second (<NUM>) transistor structures.