Patent Description:
<CIT> discloses a processor including an instruction execution unit, a first mode resource storage unit, a second mode resource storage unit, and a mapping access interface. The instruction execution unit is connected with the first mode resource storage unit, the second mode resource storage unit, and the mapping access interface. The first mode resource storage unit is used for storing resource information in a first mode of the processor, the second mode resource storage unit is used for storing resource information in a second mode of the processor, and the mapping access interface is connected with the second mode resource storage unit.

The claimed invention is defined by the appended independent claims.

Embodiments of the present disclosure provides a processor having multiple operating modes, comprising: a first mode resource storage circuitry configured to store first mode resources when the processor is operating in a first mode, wherein the first mode resource storage circuitry comprises a resource mapping circuitry configured to provide second mode resources to the processor operating in the first mode; a second mode resource storage circuitry configured to store the second mode resources when the processor is operating in a second mode; and an access control interface communicatively coupled to the resource mapping circuitry and the second mode resource storage circuitry, the access control interface configured to provide the resource mapping circuitry with an access to the second mode resource storage circuitry.

Embodiments of the present disclosure further provides a system on chip, comprising a processor configured to operate in multiple operating modes, comprising: a first mode resource storage circuitry configured to store first mode resources when the processor is operating in a first mode, wherein the first mode resource storage circuitry comprises a resource mapping circuitry configured to provide second mode resources to the processor operating in the first mode; a second mode resource storage circuitry configured to store the second mode resources when the processor is operating in a second mode; and an access control interface communicatively coupled to the resource mapping circuitry and the second mode resource storage circuitry, the access control interface configured to provide the resource mapping circuitry with an access to the second mode resource storage circuitry.

Embodiments of the present disclosure further provides a processor configured to operate in multiple operating modes, the processor comprising an ordinary user mode stack pointer register configured to store a stack pointer when the processor is operating in an ordinary user mode; a superuser mode register bank configured to store values of registers when the processor is operating in a superuser mode, the superuser register bank comprising a map register configured to provide the ordinary user stack pointer to the processor when he processor is operating in the superuser mode; and an access control interface communicatively coupled to the map register and the ordinary user stack pointer register, the access control interface configured to provide the map register with an access to the ordinary user stack pointer register.

Embodiments of the present disclosure further provides a system on chip, comprising a processor configured to operate in multiple operating modes, comprising: an ordinary user mode stack pointer register configured to store a stack pointer when the processor is operating in an ordinary user mode; a superuser mode register bank configured to store values of registers when the processor is operating in a superuser mode, the superuser register bank comprising a map register configured to provide the ordinary user stack pointer to the processor when he processor is operating in the superuser mode; and an access control interface communicatively coupled to the map register and the ordinary user stack pointer register, the access control interface configured to provide the map register with an access to the ordinary user stack pointer register.

Embodiments of the present disclosure further provides a processor configured to operate in multiple operating modes, comprising a non-trusted world register bank configured to store values of registers when the processor is operating in a non-trusted world mode; a trusted world register bank configured to store values of registers when the processor is in operating a trusted world mode, the trusted world register bank comprising a map register configured to provide the values of non-trusted world registers in the non-trusted world register bank to the processor when the processor is operating in the trusted world mode; and an access control interface communicatively coupled to the map register and the non-trusted world register, the access control interface configured to provide the map register with an access to the non-trusted world register.

Embodiments of the present disclosure further provides a system on chip, comprising processor configured to operate in multiple operating modes, comprising: a non-trusted world register bank configured to store values of registers when the processor is operating in a non-trusted world mode; a trusted world register bank configured to store values of registers when the processor is in operating a trusted world mode, the trusted world register bank comprising a map register configured to provide the values of non-trusted world registers in the non-trusted world register bank to the processor when the processor is operating in the trusted world mode; and an access control interface communicatively coupled to the map register and the non-trusted world register, the access control interface configured to provide the map register with an access to the non-trusted world register.

To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure are described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are merely some rather than all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those with ordinary skill in the art without creative efforts should fall within the protective scope of the present disclosure.

To enhance processor security, a new trusted world status can be added to the operating modes of the processor. The trusted world status can be a safe and reliable operating mode in which sensitive, important hardware and software resources in processors in trusted worlds, system IPs of trusted attributes, and other systems can be configured to become a part of the trusted worlds. Hardware mechanisms can be utilized to ensure that resources in the trusted worlds can only be accessed by members of the trusted worlds, thus isolating the trusted worlds from non-trusted worlds and further ensuring the confidentiality and integrity of secure resources.

In a processor architecture that supports operation in multiple modes, a processor can provide resources, such as a register bank, for each mode specifically. As a result, the processor operating in one operating mode may not directly access various processor resources in other operating modes, thereby ensuring the security of the processor. To access processor resources in other operating modes, the processor may need to perform mode switching to access processor resources in other modes.

For an operating mode with higher authority, processor resources in an operating mode with lower authority should be accessible under the permission of the authority. Existing technologies often rely on mode switching methods, which can cause a high overhead for the access process. Therefore, a more direct and efficient method is desired so that the processor in a higher-authority operating mode may directly access the processor resources in a low-authority operating mode.

<FIG> is a schematic diagram of a processor configured to operate in different modes, according to some embodiments of the present disclosure. As shown in <FIG>, a processor <NUM> can operate in a first mode <NUM> and a second mode <NUM>. Depending on the structural design of processor <NUM>, processor <NUM> may define operating modes in a variety of ways. In some embodiments, the operating modes of processor <NUM> may comprise a first mode <NUM> and a second mode <NUM> according to the identity of the instruction execution. In some embodiments, first mode <NUM> and second mode <NUM> can be a superuser operating mode and an ordinary user operating mode, respectively. In some embodiments, first mode <NUM> and second mode <NUM> can be a trusted world mode and a non-trusted world mode, respectively, according to an instruction execution environment.

The present disclosure is not limited to specific division forms of the modes, and the above-mentioned execution modes may be further combined to form more execution modes. For example, trusted world mode and non-trusted world mode may further comprise a trusted world superuser operating mode, a trusted world ordinary user operating mode, a non-trusted world superuser operating mode, and a non-trusted world ordinary user operating mode. All manners in which various different operating modes can be defined in the processor are within the scope of the present disclosure.

When processor <NUM> is operating in an operating mode, processor <NUM> can provide for the operating mode resources that are available in this mode. For example, as shown in <FIG>, processor <NUM> can include a first mode resource storage unit <NUM> in a first mode <NUM> and a second mode resource storage unit <NUM> in a second mode <NUM>. In some embodiments, first mode resource storage unit <NUM> or second mode resource storage unit <NUM> can comprise circuitries.

First mode resource storage unit <NUM> can store resources when processor <NUM> is operating in first mode <NUM>, and second mode resource storage unit <NUM> can store resources when processor <NUM> is operating in second mode <NUM>. Processor <NUM> may provide various resources, such as various registers, including a general-purpose register for temporarily storing data, a general-purpose vector register for vector calculation, a control register, or a stack pointer register. Processor <NUM> may also provide a memory space dedicated to a certain mode, such as a stack associated with one mode. The present disclosure is not limited to the specific content of the resources, and all resources dedicated to a specific operating mode are within the scope of the present disclosure.

The resources provided by the processor in first mode <NUM> and the resources provided in second mode <NUM> may be different. In the case where first mode <NUM> has a higher authority than that of second mode <NUM>, the processor may provide more resources in first mode <NUM> than resources provided in second mode <NUM>. For example, when first mode <NUM> is the superuser operating mode and second mode <NUM> is the ordinary user operating mode, in addition to providing resources for stack pointers in both first model <NUM> and second model <NUM> (e.g., first mode resource storage unit <NUM> includes a superuser mode stack pointer register for a superuser mode stack pointer and second mode resource storage unit <NUM> includes an ordinary user mode stack pointer register for an ordinary user mode stack pointer), processor <NUM> can also provide, in first mode <NUM>, a plurality of registers for storing processor field contents when processor <NUM> has an exception. For example, first mode resource storage unit <NUM> can further include a register for saving an exception entry base address. In some embodiments, in order to directly access the processor resources from second mode <NUM> in first mode <NUM> that has a higher authority, first mode resource storage unit <NUM> can further include a resource mapping unit <NUM>. In some embodiments, Resource mapping unit <NUM> can provide the content stored in second mode resource storage unit <NUM>. In some embodiments, resource mapping unit <NUM> can comprise circuitries. Resource mapping unit <NUM> can provide an access interface to second mode resource storage unit <NUM>. In other words, resource mapping unit <NUM> can map to second mode resource storage unit <NUM>. When resource mapping unit <NUM> is accessed in first mode <NUM>, the content in second mode resource storage unit <NUM> may be accessed. For example, in first mode <NUM>, the content in resource mapping unit <NUM> may be read, so that the content in second mode resource storage unit <NUM> is read. When some content is written into resource mapping unit <NUM>, a corresponding content may be written into second mode resource storage unit <NUM>.

In some embodiments, to facilitate execution of the processor and instruction operations, resource mapping unit <NUM> may be in the same form as that of second mode resource storage unit <NUM>. For example, when second mode resource storage unit <NUM> is a register, resource mapping unit <NUM> may also take a form of a register. When second mode resource storage unit <NUM> is a segment of memory space, resource mapping unit <NUM> may also be in a form of a segment of memory space. In some embodiments, second mode resource storage unit <NUM> can be a collection of a variety of memory types (e.g., a register, a segment of memory space, etc.), and resource mapping unit <NUM> may also be in a form of the same collection of the variety of memory types.

In some embodiments, processor <NUM> can provide multiple resources in both first mode <NUM> and second mode <NUM>. Resource mapping unit <NUM> may map some of the resources as needed. In other words, resource mapping unit <NUM> may map one or more units in second mode resource storage units <NUM>. For example, when first mode <NUM> is a superuser operating mode and second mode <NUM> is an ordinary user operating mode, resource mapping unit <NUM> may map the ordinary user mode stack pointer register in second mode resource storage unit <NUM>, so that the stack pointer in the ordinary user mode may be accessed in the superuser mode.

In some embodiments, to enable resource mapping unit <NUM> to map second mode resource storage unit <NUM>, processor <NUM> can further include an access control interface <NUM>. Access control interface <NUM> can be communicatively coupled to resource mapping unit <NUM> and second mode resource storage unit <NUM>, and access control interface <NUM> can provide resource mapping unit <NUM> with access to second mode resource storage unit <NUM>. As a result, when processor <NUM> is operating in first mode <NUM> and the content of resource mapping unit <NUM> is read, the content in second mode <NUM> stored in second mode resource storage unit <NUM> is read via access control interface <NUM>. When some content is written into resource mapping unit <NUM>, corresponding content in second mode <NUM> is written into second mode resource storage unit <NUM> via access control interface <NUM>.

Access control interface <NUM> can be implemented in a variety of ways. In some embodiments, if processor <NUM> can only operate in either a trusted world mode or a non-trusted world mode, access control interface <NUM> may obtain a storage location of second mode resource storage unit <NUM> in the memory space before switching from second mode <NUM> to first mode <NUM>, and associate the storage location with resource mapping unit <NUM> when processor <NUM> operates in first mode <NUM>. For example, when processor <NUM> switches to first mode <NUM>, some content is read from the storage location into resource mapping unit <NUM>, and when processor <NUM> switches out first mode <NUM>, the content in resource mapping unit <NUM> can be written to the storage location, thereby implementing the mapping between resource storage unit <NUM> and second mode resource storage unit <NUM>.

In some embodiments, when processor <NUM> is operating in second mode <NUM>, access control interface <NUM> may monitor the value or data stored in second mode resource storage unit <NUM> in real time and write the value or the data to a predetermined storage location in the memory space. When processor <NUM> is operating in first mode <NUM>, the storage location is associated with resource mapping unit <NUM>. For example, when processor <NUM> switches to first mode <NUM>, some content is read from the storage location into resource mapping unit <NUM>, and when processor <NUM> switches out first mode <NUM>, the content of resource mapping unit <NUM> is written to the storage location. When processor <NUM> switches back to the second mode, the content may be read from the storage location and written into second mode resource storage unit <NUM>, thereby implementing mapping between resource storage unit <NUM> and second mode resource storage unit <NUM>.

In some embodiments, processor <NUM> can support operations in first mode <NUM> and second mode <NUM> simultaneously. For example, processor <NUM> can be a multi-core processor in which one or more processor cores can operate in a first mode (e.g., trusted world mode) while one or more other processor cores can operate in a second mode (e.g., non-trusted world mode). In this case, access control interface <NUM> may use a dedicated storage area in the memory space, monitor values or data stored in second mode resource storage unit <NUM> in real time, and write the values or the data into the dedicated storage area in the storage space. When processor <NUM> reads the content in resource mapping unit <NUM> in first mode <NUM>, the content can be obtained from the dedicated storage area. When the content is written into resource mapping unit <NUM>, the content can also be written into the dedicated storage area and is then synchronized to second mode resource storage unit <NUM>, thereby implementing mapping between resource mapping unit <NUM> and second mode resource storage unit <NUM>.

The present disclosure is not limited to specific implementations of access control interface <NUM>. All manners in which the mapping relationship between resource mapping unit <NUM> and second mode resource storage unit <NUM> may be established are within the scope of the present disclosure.

In some embodiments, processor <NUM> can support instructions written in a corresponding instruction set and define corresponding instructions or operand forms of resources provided in various operating modes. For example, processor <NUM> may define a list of resources provided in first mode <NUM> and a list of resources provided in second mode <NUM>. Moreover, processor <NUM> may further define an operand form of resource mapping unit <NUM> in first mode <NUM>. As described above, resource mapping unit <NUM> may have the same form as that of second mode resource storage unit <NUM> to be mapped, thereby facilitating instruction processing.

In some embodiments, as shown in <FIG>, processor <NUM> can further include an instruction execution unit <NUM>. In some embodiments, instruction execution unit <NUM> can comprise circuitries. Instruction execution unit <NUM> can execute decoded instructions. When processor <NUM> is operating in the first mode, instruction execution unit <NUM> can execute one or more instructions to access the resources provided in the first mode. When processor <NUM> is operating in the second mode, instruction execution unit <NUM> can execute one or more instructions to access the resources provided in the second mode. In some embodiments, when processor <NUM> is in the first mode, if an instruction includes an access to resource mapping unit <NUM>, instruction execution unit <NUM> can execute the instruction to access resource mapping unit <NUM> to further access the content of second mode resource storage unit <NUM> that is mapped to resource mapping unit <NUM>.

In some embodiments processor <NUM> can further include a mode identifier <NUM> to indicate which operating mode processor <NUM> is currently in. In some embodiments, instruction execution unit <NUM> may access the processor resources in the corresponding operating mode according to an operating mode (e.g., first or second mode, etc.) indicated by the value of mode identifier <NUM>.

In some embodiments, processor <NUM> can further include more operating modes. For example, processor <NUM> may include a third mode <NUM> or a fourth mode <NUM>. Accordingly, processor <NUM> can include a third mode resource storage unit <NUM> or a fourth mode resource storage unit <NUM>. In some embodiments, third mode resource storage unit <NUM> or fourth mode resource storage unit <NUM> can comprise circuitries. Third mode resource storage unit <NUM> can store resources provided when processor <NUM> is in third mode <NUM>, and fourth mode resource storage unit <NUM> can store resources provided when processor <NUM> is in fourth mode <NUM>.

In some embodiments, resource mapping unit <NUM> may further provide mappings to third mode resource storage unit <NUM> and fourth mode resource storage unit <NUM> such that when processor <NUM> is operating in first mode <NUM> that has a higher authority, contents respectively stored in second, third, and fourth mode resource storage units <NUM>, <NUM>, and <NUM> may be accessed via resource mapping unit <NUM>.

Similarly, access control interface <NUM> can also provide resource mapping unit <NUM> with an access to third mode resource storage unit <NUM> and fourth mode resource storage unit <NUM>.

It should be noted that the present disclosure may be extended to processor <NUM> having more modes, and by providing a resource mapping unit in a resource storage unit in a higher-authority operating mode, a lower-authority resource storage unit can be mapped, so that processor resources in a lower-authority operating mode may be directly accessed in a higher-authority operating mode.

<FIG> is a schematic diagram of a processor configured to operate in two modes, according to some embodiments of the present disclosure. In some embodiments, processor <NUM> shown in <FIG> can comprise units or circuitries similar to processor <NUM>. As shown in <FIG>, processor <NUM> may operate in two modes. In some embodiments, a first mode <NUM> can be a superuser mode and a second mode <NUM> can be an ordinary user mode. A first mode resource storage unit <NUM> can include a superuser mode register bank <NUM>. In some embodiments, superuser mode register bank <NUM> can include an exception entry base address register <NUM>, an exception retention status register <NUM>, an exception retention program counter register <NUM>, or a superuser mode stack pointer register <NUM>. Second mode resource storage unit <NUM> can include an ordinary user mode stack pointer register <NUM>. Resource mapping unit <NUM> can be a map register <NUM> in the superuser mode register bank <NUM> and can map to an ordinary user mode stack pointer register <NUM> in second mode <NUM>. In some embodiments, map register <NUM> can be a part of superuser mode register bank <NUM>.

In some embodiments, a mode identifier (e.g., mode identifier <NUM> described in <FIG> and not shown) can be configured as a status bit S stored in a processor status register <NUM>. The value of status bit S can indicate which mode processor <NUM> is in. For example, when the value of status bit S is <NUM>, processor <NUM> can be in the superuser mode. When the value of status bit S is <NUM>, processor <NUM> can be in the ordinary user mode. In some embodiments, instruction execution unit <NUM> can determine which mode processor <NUM> is in based on the value of status bit S.

In some embodiments, in the instruction set specification supported by processor <NUM>, the same stack pointer register can be used to store stack pointers in the ordinary user mode and the superuser mode, respectively. When instruction execution unit <NUM> executes an instruction, if status bit S in processor status register <NUM> indicates that processor <NUM> is in the superuser mode, the stack pointer register can be used as superuser mode stack pointer register <NUM>, and a superuser mode stack pointer can be obtained. If status bit S indicates that processor <NUM> is in the ordinary user mode, the stack pointer register can be used as ordinary user mode stack pointer register <NUM>, and the ordinary user mode stack pointer can be obtained. In some embodiments, if the value of the ordinary user mode stack pointer is to be obtained in the superuser mode, an instruction may be executed to access map register <NUM> to access the ordinary user mode stack pointer via access control interface <NUM>.

<FIG> is a schematic diagram of a processor configured to operate in a trusted world mode and a non-trusted world mode, according to some embodiments of the present disclosure. In some embodiments, processor <NUM> shown in <FIG> can comprise units or circuitries similar to processor <NUM> or processor <NUM>. As shown in <FIG>, processor <NUM> may operate in two modes. a first mode <NUM> can be a trusted world mode and a second mode <NUM> can be a non-trusted world mode.

A first mode resource storage unit <NUM> can include a trusted world register bank <NUM>. In some embodiments, trusted world register bank <NUM> can include a general-purpose register GPR <NUM>, a vector general-purpose register VGPR <NUM>, a control register CR <NUM>, and a trusted processor status register T_PSR <NUM>. A second mode resource storage unit <NUM> can include a non-trusted world register bank <NUM>. In some embodiments, non-trusted world register bank <NUM> can include a general-purpose register GPR <NUM>, a vector general-purpose register VGPR <NUM>, a control register CR <NUM>, a non-trusted processor status register NT _PSR <NUM>, a non-trusted world exception entry base address register <NUM>, a non-trusted world exception retention status register <NUM>, and a non-trusted world exception retention program counter register <NUM>. A resource mapping unit <NUM> can refer to a map register bank or a plurality of map registers in trusted world register bank <NUM> and may respectively map to non-trusted program status register NT _PSR <NUM>, non-trusted world exception entry base address register <NUM>, non-trusted world exception retention status register <NUM>, and non-trusted world exception retention program counter register <NUM> in the non-trusted world mode. In some embodiments, resource mapping unit can be a part of trusted world register bank <NUM>.

In some embodiments, a mode identifier (e.g., mode identifier <NUM> described in <FIG>, not shown) can be configured as a status bit T of the processor status register to indicate which mode processor <NUM> is in. For example, when the value of status bit T is <NUM>, processor <NUM> can be in the trusted world mode, and when the value of status bit T bit is <NUM>, processor <NUM> can be in the non-trusted world mode. In some embodiments, instruction execution unit <NUM> can determine which mode processor <NUM> is in based on the value of status bit T.

In some embodiments, processor <NUM> can further include a trusted processor status register T_PSR <NUM> in trusted world mode, and a non-trusted program status register NT _PSR <NUM> in non-trusted world mode. In some embodiments, these two registers can have essentially the same structure and may provide an access in the same logical way (e.g., under the name of the processor status register PSR). That is, in the case where processor <NUM> is in the trusted world mode, when an instruction in processor <NUM> accesses processor status register PSR, the instruction accesses trusted processor status register T_PSR <NUM>. In the case where processor <NUM> is in the non-trusted world mode, when an instruction in processor <NUM> accesses PSR, the instruction accesses non-trusted processor status register NT_PSR <NUM>.

Trusted processor status register T_PSR <NUM> and non-trusted processor status register NT_PSR <NUM> each have a trusted world status bit T as a mode identifier. The value of trusted world status bit T can indicate which mode processor <NUM> is in. For example, when the value of trusted world status bit T is <NUM>, it is indicated that processor <NUM> is in the trusted world mode currently. When the value of trusted world status bit T is <NUM>, it is indicated that processor <NUM> is in the non-trusted world mode currently. In some embodiments, the value of trusted world status bit T of T_PSR <NUM> can be fixed at <NUM>, while the value of trusted world status bit T of NT_PSR <NUM> can be fixed at <NUM>.

In some embodiments, when instruction execution unit <NUM> executes an instruction, if trusted world status bit T in processor status register PSR indicates that processor <NUM> is in the trusted world mode, trusted world register bank <NUM> may be accessed. If trusted world status bit T indicates that processor <NUM> is in the non-trusted world mode, non-trusted world register bank <NUM> may be accessed. If values stored in some registers in non-trusted world register bank <NUM> are to be obtained in the trusted world mode, an instruction may be executed to access map registers in map register bank <NUM> to access corresponding non-trusted world registers in non-trusted world register bank <NUM> via access control interface <NUM>.

<FIG> is a schematic diagram of a processor configured to operate in four different modes, according to some embodiments of the present disclosure. In some embodiments, processor <NUM> shown in <FIG> can comprise units or circuitry similar to processor <NUM>, processor <NUM>, or processor <NUM>. As shown in <FIG>, processor <NUM> may operate in four modes. A first mode <NUM> can be a trusted world superuser mode. A second mode <NUM> can be a trusted world ordinary user mode. A third mode <NUM> can be a non-trusted world superuser mode. A fourth mode <NUM> can be a non-trusted world ordinary user mode. A first mode resource storage unit <NUM> can include a trusted world superuser register bank <NUM>. Trusted world superuser register bank <NUM> can include a general-purpose register GPR <NUM>, a vector general-purpose register VGPR <NUM>, a control register CR <NUM>, a trusted processor status register T_PSR <NUM>, and a trusted world superuser stack pointer register <NUM>.

A second mode resource storage unit <NUM> can include a trusted world ordinary user register bank <NUM>. The trusted world ordinary user register bank can include a trusted world ordinary user stack pointer register <NUM>.

A third mode resource storage unit <NUM> can include a non-trusted world superuser register bank <NUM>. Non-trusted world superuser register bank <NUM> can include a general-purpose register GPR <NUM>, a vector general-purpose register VGPR <NUM>, a control register CR <NUM>, a non-trusted processor status register NT_PSR <NUM>, a non-trusted world exception entry base address register <NUM>, a non-trusted world exception retention status register <NUM>, a non-trusted world exception retention program counter register <NUM>, and a non-trusted world superuser stack pointer register <NUM>. In some embodiments, vector general-purpose register VGPR <NUM> can correspond to vector general-purpose register VGPR <NUM> in trusted world superuser register bank <NUM>. Control register CR <NUM> can correspond to control register CR <NUM> in trusted world superuser register bank <NUM>. Non-trusted processor status register NT_PSR <NUM> can correspond to trusted processor status register T_PSR <NUM> in trusted world superuser register bank <NUM>.

A fourth mode resource storage unit <NUM> can include a non-trusted world ordinary user register bank <NUM>. Non-trusted world ordinary user register bank can include a non-trusted world ordinary user stack pointer register <NUM>.

A resource mapping unit <NUM> can refer to a map register bank or a plurality of map registers, which may respectively map to trusted world ordinary user stack pointer register <NUM> in the trusted world ordinary user mode, non-trusted world processor status register NT_PSR <NUM> in the non-trusted world superuser mode, non-trusted world exception entry base address register <NUM> in the non-trusted world superuser mode,, the non-trusted world exception retention status register <NUM> in the non-trusted world superuser mode, non-trusted world exception retention program counter register <NUM> in the non-trusted world superuser mode, and non-trusted world ordinary user stack pointer register <NUM> in the non-trusted world ordinary user mode. In some embodiments, resource mapping unit <NUM> can be a part of trusted world superuser register bank <NUM>.

In some embodiments, a mode identifier (e.g., mode modifier <NUM> described in <FIG> and not shown) can be configured as a status bit T and a status bit S of the processor status register (e.g., status bit T of <FIG> and status bit S of <FIG>). For example, when the value of status bit T is <NUM> and the value of status bit S is <NUM>, processor <NUM> can be in the trusted world superuser mode. When the value of status bit T is <NUM> and the value of status bit S is <NUM>, processor <NUM> can be in the trusted world ordinary user mode. When the value of status bit T is <NUM> and the value of status bit S is <NUM>, processor <NUM> can be in the non-trusted world superuser mode. When the value of status bit T is <NUM> and value of status bit S is <NUM>, processor <NUM> can be in the non-trusted world ordinary user mode. A instruction execution unit <NUM> can determine which mode processor <NUM> is in based on the values of status bit T and status bit S.

According to the processor architecture of the present disclosure, a resource mapping unit may be provided in a resource storage unit in a higher-authority operating mode to map a resource storage unit in a lower-authority operating mode, so that processor resources in a lower-authority operating mode may be directly accessed in a higher-authority operating mode. Thus, processor resources in a low-authority operating mode may be accessed without mode switching by the processor, thus saving processor overhead.

The processor described above with reference to <FIG> may be included in a processing system. The processing system may further include other components such as various interrupt sources, coprocessors, and storage devices. These components together with the processor form a processing system. In some embodiments, the processing system includes a SoC (System on Chip) or the like.

<FIG> is a schematic diagram of a system on chip, according to some embodiments of the present disclosure. As shown in <FIG>, SoC <NUM> can include processor <NUM>, various interrupt sources <NUM>, memory space <NUM>, and coprocessor <NUM> (e.g., such as accelerators). Processors <NUM> can be any of processors <NUM>-<NUM> described above. In some embodiments, SoC <NUM> can be integrated on a circuit board and constitutes a relatively complete processing system. Interrupt sources <NUM> can include, for example, various peripheral interfaces that receive external inputs and output outputs processed by the processors <NUM>. In some embodiments, interrupt sources <NUM> can also include software-based interrupt sources. Memory space <NUM> can provide external memory space for processor <NUM> to store codes to be executed by processor <NUM> and various output data generated. Coprocessor <NUM> can be a specialized processor for performing specialized processing tasks, such as image operations.

In the foregoing specification, embodiments have been described with reference to numerous specific details that can vary from implementation to implementation. Certain adaptations and modifications of the described embodiments can be made. Other embodiments can be apparent to those skilled in the art from consideration of the specification and practice of the embodiments disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the scope of the invention being indicated by the following claims. It is also intended that the sequence of steps shown in figures are only for illustrative purposes and are not intended to be limited to any particular sequence of steps. As such, those skilled in the art can appreciate that these steps can be performed in a different order while implementing the same method.

As used herein, unless specifically stated otherwise, the term "or" encompasses all possible combinations, except where infeasible. For example, if it is stated that a database may include A or B, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or A and B. As a second example, if it is stated that a database may include A, B, or C, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

Claim 1:
A processor (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) configured to operate in multiple operating modes, the processor comprising:
a first mode resource storage circuitry (<NUM>) configured to store first mode resources when the processor is operating in a first mode (<NUM>), wherein the first mode resource storage circuitry comprises a resource mapping circuitry (<NUM>) configured to provide second mode resources to the processor operating in the first mode;
a second mode resource storage circuitry (<NUM>) configured to store the second mode resources when the processor is operating in a second mode (<NUM>);
a third mode resource storage circuitry (<NUM>) configured to store third mode resources when the processor is operating in a third mode (<NUM>);
a fourth mode resource storage circuitry (<NUM>) configured to store fourth mode resources when the processor is operating in a fourth mode (<NUM>), wherein the resource mapping circuitry is configured to provide the third and fourth mode resources to the processor operating in the first mode;
an access control interface (<NUM>) communicatively coupled to the resource mapping circuitry, the second mode resource storage circuitry, the third mode resource storage circuitry, and the fourth mode resource storage circuitry, the access control interface configured to provide the resource mapping circuitry with an access to the second mode resource storage circuitry, the third mode resource storage circuitry, and the fourth mode resource storage circuitry; and
an instruction execution circuitry (<NUM>) configured to:
execute an instruction to access the first mode resources when the processor is operating in the first mode,
execute an instruction to access the second mode resources when the processor is operating in the second mode,
execute an instruction to access the resource mapping circuitry when the processor is operating in the first mode so that the second mode resources in the second mode resource storage circuitry are accessed via the access control interface,
execute an instruction to access the third mode resources when the processor is operating in the third mode, and
execute an instruction to access the fourth mode resources when the processor is operating in the fourth mode.