Patent Description:
In modern mobile devices (e.g., smartphones, tablets, etc.), multiple complicated system-on-chips (SOC) are used to enable various functionalities, such as application processor, dynamic random-access memory (DRAM), Flash memory, various controllers for Bluetooth, Wi-Fi, global positioning system (GPS), frequency modulation (FM) radio, display, etc., and baseband processor, which are formed as discrete chips. For example, application processor typically is large in size including central processing units (CPUs), graphics processing units (GPUs), on-chip memory, accelerating function hardware, and other analog components. <CIT> discloses a semiconductor device with a circuit region and a first memory region, wherein a second memory region is arranged above the circuit region and the first memory region In more details, said document shows:
A unified semiconductor chip comprising:.

Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed herein.

A unified semiconductor chip according to the present invention is defined in claim <NUM>.

A method for forming a unified semiconductor chip according to the present invention is defined in independent claim <NUM>.

A method for operating a unified semiconductor chip according to the present invention is defined in independent claim <NUM>.

It is noted that none of the drawings shows all the features of the claimed invention in combination. The drawings are however useful to understand the claimed invention even if none of the drawings shows the feature of the independent claims that the one or more processors and the array of embedded DRAM cells are stacked one over another.

Moreover, such phrases do not necessarily refer to the same embodiments.

Based on the particular technology node, the term "about" can indicate a value of a given quantity that varies within, for example, <NUM>-<NUM>% of the value (e.g., ± <NUM>%, ±<NUM>%, or ±<NUM>% of the value).

As used herein, the term "3D NAND memory string" refers to a vertically-oriented string of memory cell transistors connected in series on a laterally-oriented substrate so that the string of memory cell transistors extends in the vertical direction with respect to the substrate.

In existing smartphones (and other mobile devices), the application processor and memory (e.g., DRAM and NAND) are placed on the PCB separately communicating through long and slow interlink on the PCB. Data throughput suffers as a result. Also, the size of the PCB is large because of area consumption from the separate application processor and DRAM and NAND memory chips, limiting room available for the battery and other discrete components in the smartphone. Moreover, the application processor has on-chip memory, which further increases its chip size.

Various embodiments in accordance with the present disclosure provide a unified semiconductor chip having one or more processors (e.g., application processor and baseband processor) and volatile and non-volatile memory (e.g., embedded DRAM and NAND memory), with improved bidirectional data transfer throughput between the processing units and data storage as well as between volatile and non-volatile memory, thereby achieving overall faster system speed, while reducing PCB footprint at the same time. In some embodiments, the peripheral circuit of the memory is formed on the same substrate with the processing units (e.g., processors and controllers). In some embodiments, embedded DRAM is also formed on the same substrate with the processing units as a high-speed memory buffer to eliminate on-chip memory and reduce chip size. The NAND memory cell array (either 2D or 3D) is, in accordance with the claimed invention, formed on another substrate and then bonded to the substrate on which the processors are formed. In one example, the unified semiconductor chip disclosed herein can enable an instant-on feature on mobile devices (e.g., smartphones) to save power consumption because of its high-speed non-volatile data storage capability.

<FIG> illustrates a schematic view of a cross-section of an exemplary unified semiconductor chip <NUM>, according to some embodiments. Unified semiconductor chip <NUM> represents an example of a bonded chip. The components of unified semiconductor chip <NUM> (e.g., processors/embedded DRAM and NAND memory) can be formed separately on different substrates and then jointed to form a bonded chip. Unified semiconductor chip <NUM> includes a first semiconductor structure <NUM> including a plurality of processors and an array of embedded DRAM cells. In some embodiments, the processors and embedded DRAM cell array in first semiconductor structure <NUM> use complementary metal-oxide-semiconductor (CMOS) technology. Both the processors and the embedded DRAM cell array can be implemented with advanced logic processes (e.g., technology nodes of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.) to achieve high speed.

The processors can include specialized processors including, but not limited to, CPU, GPU, digital signal processor (DSP), tensor processing unit (TPU), vision processing unit (VPU), neural processing unit (NPU), synergistic processing unit (SPU), physics processing unit (PPU), and image signal processor (ISP). The processors can also include SoCs that combine multiple processors. According to the claimed invention, the one or more processors comprise an application processor and a baseband processor. In some embodiments in which unified semiconductor chip <NUM> is used in mobile devices (e.g., smartphones, tablets, eyeglasses, wrist watches, virtual reality/augmented reality headsets, laptop computers, etc.), an application processor handles applications running in an operating system environment, and a baseband processor handles the cellular communications, such as the second generation (<NUM>), the third generation (<NUM>), the fourth generation (<NUM>), the fifth generation (<NUM>), the sixth generation (<NUM>) cellular communications, and so on.

Other processing units besides processors can be formed in first semiconductor structure <NUM> as well, such as one or more controllers and the peripheral circuit of the NAND memory. A controller can handle a specific operation in an embedded system. In some embodiments in which unified semiconductor chip <NUM> is used in mobile devices, each controller can handle a specific operation of the mobile device, for example, communications other than cellular communication (e.g., Bluetooth communication, Wi-Fi communication, FM radio, etc.), power management, display drive, positioning and navigation, touch screen, camera, etc. First semiconductor structure <NUM> of unified semiconductor chip <NUM> thus can further include a Bluetooth controller, a Wi-Fi controller, a FM radio controller, a power controller, a display controller, a GPS controller, a touch screen controller, a camera controller, to name a few, each of which is configured to control operations of the corresponding component in a mobile device.

In some embodiments, first semiconductor structure <NUM> of unified semiconductor chip <NUM> further includes the peripheral circuit of the NAND memory. The peripheral circuit (also known as control and sensing circuits) can include any suitable digital, analog, and/or mixed-signal circuits used for facilitating the operations of the NAND memory. For example, the peripheral circuit can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors).

An embedded DRAM is a DRAM integrated on the same substrate of logic circuits (e.g., the processors), which allows wider bus and higher operation speed. Embedded DRAM, like all types of DRAM, requires periodic refreshing of the memory cells. The memory controller for refreshing the embedded DRAM can be embedded as another example of the controllers described above. In some embodiments, each embedded DRAM cell includes a capacitor for storing a bit of data as a positive or negative electrical charge as well as one or more transistors that control access to it. In one example, each embedded DRAM cell is a one-transistor, one-capacitor (1T1C) cell.

In accordance with the claimed invention, unified semiconductor chip <NUM> can-also includes a second semiconductor structure <NUM> including an array of NAND memory cells. That is, second semiconductor structure <NUM> can be a NAND Flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings and/or an array of 2D NAND memory cells. NAND memory cells can be organized into pages which are then organized into blocks in which each NAND memory cell is electrically connected to a separate line called a bit line (BL). All cells with the same vertical position in the NAND memory cell can be electrically connected through the control gates by a word line (WL). In some embodiments, a plane contains a certain number of blocks that are electrically connected through the same bit line. Second semiconductor structure <NUM> can include one or more planes, and the peripheral circuit that is needed to perform all the read/write/erase operations can be included in first semiconductor structure <NUM> as described above.

In some embodiments, the array of NAND memory cells are an array of 2D NAND memory cells, each of which includes a floating-gate transistor. The array of 2D NAND memory cells include a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells (e.g., <NUM> to <NUM> memory cells) connected in series (resembling a NAND gate) and two select transistors, according to some embodiments. Each 2D NAND memory string is arranged in the same plane on the substrate (in 2D), according to some embodiments. In some embodiments, the array of NAND memory cells are an array of 3D NAND memory strings, each of which extends vertically above the substrate (in 3D) through a memory stack. Depending on the 3D NAND technology (e.g., the number of layers/tiers in the memory stack), a 3D NAND memory string typically includes <NUM> to <NUM> NAND memory cells, each of which includes a floating-gate transistor or a charge-trap transistor.

As shown in <FIG>, unified semiconductor chip <NUM> further includes a bonding interface <NUM> vertically between first semiconductor structure <NUM> and second semiconductor structure <NUM>. As described below in detail, first and second semiconductor structures <NUM> and <NUM> can be fabricated separately (and in parallel in some embodiments) such that the thermal budget of fabricating one of first and second semiconductor structures <NUM> and <NUM> does not limit the processes of fabricating another one of first and second semiconductor structures <NUM> and <NUM>. Moreover, a large number of interconnects (e.g., bonding contacts) can be formed through bonding interface <NUM> to make direct, short-distance electrical connections between first semiconductor structure <NUM> and second semiconductor structure <NUM>, as opposed to the long-distance chip-to-chip data bus on the circuit board (e.g., PCB), thereby eliminating chip interface delay and achieving high-speed I/O throughput with reduced power consumption. Data transfer between the NAND memory in second semiconductor structure <NUM> and the embedded DRAM in first semiconductor structure <NUM> as well as between the NAND memory in second semiconductor structure <NUM> and the processors in first semiconductor structure <NUM> can be performed through the interconnects (e.g., bonding contacts) across bonding interface <NUM>. By vertically integrating first and second semiconductor structures <NUM> and <NUM>, the chip size can be reduced, and the memory cell density can be increased. Furthermore, as a "unified" chip, by integrating multiple discrete chips (e.g., various processors, controllers and memories) into a single bonded chip (e.g., unified semiconductor chip <NUM>), faster system speed and smaller PCB size can be achieved as well. For example, all or most of the functional components of a mobile device may be integrated into unified semiconductor chip <NUM> to enable "mobile device-on-a-chip.

It is understood that the relative positions of stacked first and second semiconductor structures <NUM> and <NUM> are not limited. <FIG> illustrates a schematic view of a cross-section of another exemplary unified semiconductor chip <NUM>, according to some embodiments. Being different from unified semiconductor chip <NUM> in <FIG> in which second semiconductor structure <NUM> including the array of NAND memory cells is above first semiconductor structure <NUM> including the processors and the array of embedded DRAM cells, in unified semiconductor chip <NUM> in <FIG>, first semiconductor structure <NUM> including the processors and the array of embedded DRAM cells is above second semiconductor structure <NUM> including the array of NAND memory cells. Nevertheless, bonding interface <NUM> is formed vertically between first and second semiconductor structures <NUM> and <NUM> in unified semiconductor chip <NUM>, and first and second semiconductor structures <NUM> and <NUM> are joined vertically through bonding (e.g., hybrid bonding) according to some embodiments. Data transfer between the NAND memory in second semiconductor structure <NUM> and the embedded DRAM in first semiconductor structure <NUM> as well as the data transfer between NAND memory in second semiconductor structure <NUM> and the processors in first semiconductor structure <NUM> can be performed through the interconnects (e.g., bonding contacts) across bonding interface <NUM>.

<FIG> illustrates a schematic plan view of an exemplary semiconductor structure <NUM> having processors, controllers, and an embedded DRAM, according to some embodiments. Semiconductor structure <NUM> may be one example of first semiconductor structure <NUM>. Semiconductor structure <NUM> can include the peripheral controlling circuit and sensing NAND memory, including word line drivers <NUM>, page buffers <NUM>, and any other suitable devices. Semiconductor structure <NUM> further includes embedded DRAM <NUM> on the same substrate as the peripheral circuit and fabricated using the same logic processes as the peripheral circuit. <FIG> shows an exemplary layout of the peripheral circuit (e.g., word line drivers <NUM>, page buffers <NUM>) and embedded DRAM <NUM> in which peripheral circuit (e.g., word line drivers <NUM>, page buffers <NUM>) and embedded DRAM <NUM> are formed in different regions on the same plane. For example, embedded DRAM <NUM> may be formed outside of the peripheral circuit (e.g., word line drivers <NUM>, page buffers <NUM>).

Semiconductor structure <NUM> also includes multiple processors on the same substrate as the peripheral circuit and embedded DRAM <NUM> and fabricated using the same logic process as the peripheral circuit and embedded DRAM <NUM>. In the exemplary layout shown in <FIG>, the processors can include an application processor <NUM>, a baseband processor <NUM>, and a DSP <NUM>. In some embodiments, application processor <NUM> includes, for example, one or more CPUs, GPUs, cache, connectivities, interfaces (I/Fs), audio, and security modules. In some embodiments, baseband processor <NUM> includes, for example, filters, power amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and modem. DSP <NUM> is a specialized processor that is optimized for operational needs of digital signal processing, such as measuring, filtering, or compressing continuous analog signals, according to some embodiments.

Semiconductor structure <NUM> can further include multiple controllers (also known as microcontroller units "MCUs") on the same substrate as the peripheral circuit and embedded DRAM <NUM> and fabricated using the same logic processes as the peripheral circuit and embedded DRAM <NUM>. In the exemplary layout shown in <FIG>, the controllers can include a display controller <NUM>, a power controller <NUM>, various communication controllers, such as a Bluetooth controller <NUM> and a Wi-Fi controller <NUM>, and a GPS controller <NUM>. Each controller <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM> is configured to control operations of the corresponding component. For example, display controller <NUM> may receive display data generated by application processor <NUM> (e.g., by its GPU) and provide control signals (e.g., scan signals, frame data, timing signals, etc.) to drive the display. In another example, power controller <NUM> (also known as power management unit "PMU") may control power-related operations, such as monitoring power connections and battery charges, charging the battery, regulating the power to other components, and managing power consumption. In still another example, each communication controller <NUM> or <NUM> may control the corresponding transceiver to transmit and receive wireless signals based on the corresponding communication standards and protocols, e.g., Bluetooth <NUM>. x, Bluetooth <NUM>. x, Bluetooth Lower Energy (BLE), Bluetooth <NUM>. x, Wi-Fi <NUM>, Wi-Fi <NUM>, Wi-Fi <NUM>, etc. In yet another example, GPS controller <NUM> may control the global navigation transceiver to transmit and receive signals for positioning and navigation using GPS, GLObal NAvigation Satellite System (GLONASS), Galileo, or BeiDou system.

It is understood that the layout of semiconductor structure <NUM> is not limited to the exemplary layout in <FIG>. In some embodiments, at least some of the peripheral circuit (e.g., word line drivers <NUM>, page buffers <NUM>), the processors (e.g., application processor <NUM>, baseband processor <NUM>, DSP <NUM>), the controllers (e.g., display controller <NUM>, power controller <NUM>, Bluetooth controller <NUM>, Wi-Fi controller <NUM>, GPS controller <NUM>), and embedded DRAM <NUM> (e.g., the array of embedded DRAM cells) are stacked one over another, i.e., in different planes. For example, embedded DRAM <NUM> (e.g., the array of embedded DRAM cells) may be formed above or below the peripheral circuit and, in accordance with the claimed invention, embedded DRAM <NUM> is formed above or below the processors to further reduce the chip size.

<FIG> illustrates a cross-section of an exemplary unified semiconductor chip <NUM> having 3D NAND memory, according to some embodiments. As one example of unified semiconductor chip <NUM> described above with respect to <FIG>, unified semiconductor chip <NUM> is a bonded chip including a first semiconductor structure <NUM> and a second semiconductor structure <NUM> stacked over first semiconductor structure <NUM>. First and second semiconductor structures <NUM> and <NUM> are jointed at a bonding interface <NUM> therebetween, according to some embodiments. As shown in <FIG>, first semiconductor structure <NUM> can include a substrate <NUM>, which can include silicon (e.g., single crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable materials.

First semiconductor structure <NUM> of unified semiconductor chip <NUM> can include a device layer <NUM> above substrate <NUM>. It is noted that x- andy-axes are added in <FIG> to further illustrate the spatial relationship of the components in unified semiconductor chip <NUM>. Substrate <NUM> includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (the lateral direction or width direction). As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a semiconductor device (e.g., unified semiconductor chip <NUM>) is determined relative to the substrate of the semiconductor device (e.g., substrate <NUM>) in the y-direction (the vertical direction or thickness direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing the spatial relationship is applied throughout the present disclosure.

In some embodiments, device layer <NUM> includes one or more processors <NUM> on substrate <NUM> and an array of embedded DRAM cells <NUM> on substrate <NUM> and outside of processors <NUM>. In some embodiments, processors <NUM> include a plurality of logic transistors <NUM> forming any suitable specialized processors and/or SoCs as described above in detail, such as an application processor (e.g., including one or more CPUs and GPUs) and a baseband processor. In some embodiments, logic transistors <NUM> also form any suitable controllers as described above in detail, such as a display controller, a power controller, a GPS controller, and one or more communication controllers (e.g., Bluetooth controller, Wi-Fi controller). In some embodiments, logic transistors <NUM> further form a peripheral circuit, i.e., any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of the 3D NAND memory including, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference. That is, device layer <NUM> can include one or more controllers and/or the peripheral circuit of the 3D NAND memory on substrate <NUM> as well.

Logic transistors <NUM> can be formed "on" substrate <NUM>, in which the entirety or part of logic transistors <NUM> are formed in substrate <NUM> (e.g., below the top surface of substrate <NUM>) and/or directly on substrate <NUM>. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of logic transistors <NUM>) can be formed in substrate <NUM> as well. Logic transistors <NUM> are high-speed with advanced logic processes (e.g., technology nodes of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.), according to some embodiments.

In some embodiments, each embedded DRAM cell <NUM> includes a DRAM selection transistor <NUM> and a capacitor <NUM>. Embedded DRAM cell <NUM> can be a 1T1C cell consisting of one transistor and one capacitor. It is understood that embedded DRAM cell <NUM> may be of any suitable configurations, such as 2T1C cell, 3T1C cell, etc. In some embodiments, DRAM selection transistors <NUM> are formed "on" substrate <NUM>, in which the entirety or part of DRAM selection transistors <NUM> are formed in substrate <NUM> (e.g., below the top surface of substrate <NUM>) and/or directly on substrate <NUM>. Isolation regions (e.g., STIs) and doped regions (e.g., source regions and drain regions of DRAM selection transistors <NUM>) can be formed in substrate <NUM> as well. As shown in <FIG>, DRAM selection transistors <NUM> and logic transistors <NUM> can be formed, in embodiments which do not form part of the claimed invention, in different regions on the same plane, e.g., on substrate <NUM>. That is, DRAM selection transistors <NUM> can be formed outside of the region in which processors <NUM> are formed on substrate <NUM>. In some embodiments, capacitors <NUM> are formed above DRAM selection transistors <NUM>. Each capacitor <NUM> includes two electrodes, one of which is electrically connected to one node of respective DRAM selection transistor <NUM>, according to some embodiments. Another node of each DRAM selection transistor <NUM> is electrically connected to a bit line <NUM> of embedded DRAM, according to some embodiments. Another electrode of each capacitor <NUM> can be electrically connected to a common plate <NUM>, e.g., a common ground. It is understood that the structure and configuration of embedded DRAM cell <NUM> are not limited to the example in <FIG> and may include any suitable structure and configuration. For example, capacitor <NUM> may be a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor.

In some embodiments, first semiconductor structure <NUM> of unified semiconductor chip <NUM> further includes an interconnect layer <NUM> above device layer <NUM> to transfer electrical signals to and from processors <NUM> and array of embedded DRAM cells <NUM>. Interconnect layer <NUM> can include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and vertical interconnect access (via) contacts. As used herein, the term "interconnects" can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Interconnect layer <NUM> can further include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which the interconnect lines and via contacts can form. That is, interconnect layer <NUM> can include interconnect lines and via contacts in multiple ILD layers. The interconnect lines and via contacts in interconnect layer <NUM> can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in interconnect layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. In some embodiments, the devices in device layer <NUM> are electrically connected to one another through the interconnects in interconnect layer <NUM>. For example, array of embedded DRAM cells <NUM> may be electrically connected to processors <NUM> through interconnect layer <NUM>.

As shown in <FIG>, first semiconductor structure <NUM> of unified semiconductor chip <NUM> further includes a bonding layer <NUM> at bonding interface <NUM> and above interconnect layer <NUM> and device layer <NUM> (including processors <NUM> and array of embedded DRAM cells <NUM>). Bonding layer <NUM> includes a plurality of bonding contacts <NUM> and surrounding dielectrics. Bonding contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer <NUM> is formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding.

Similarly, as shown in <FIG>, second semiconductor structure <NUM> of unified semiconductor chip <NUM> also includes a bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM> of first semiconductor structure <NUM>. Bonding layer includes a plurality of bonding contacts <NUM> and surrounding dielectrics. Bonding contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer <NUM> is formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding.

As described above, second semiconductor structure <NUM> can be bonded on top of first semiconductor structure <NUM> in a face-to-face manner at bonding interface <NUM>. In some embodiments, bonding interface <NUM> is disposed between bonding layers <NUM> and <NUM> as a result of hybrid bonding (also known as "metal/dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, bonding interface <NUM> is the place at which bonding layers <NUM> and <NUM> are met and bonded. In practice, bonding interface <NUM> can be a layer with a certain thickness that includes the top surface of bonding layer <NUM> of first semiconductor structure <NUM> and the bottom surface of bonding layer <NUM> of second semiconductor structure <NUM>.

In some embodiments, second semiconductor structure <NUM> of unified semiconductor chip <NUM> further includes an interconnect layer <NUM> above bonding layer <NUM> to transfer electrical signals. Interconnect layer <NUM> can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. Interconnect layer <NUM> can further include one or more ILD layers in which the interconnect lines and via contacts can form. The interconnect lines and via contacts in interconnect layer <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in interconnect layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

In some embodiments, second semiconductor structure <NUM> of unified semiconductor chip <NUM> includes a NAND Flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings <NUM> above interconnect layer <NUM> and bonding layer <NUM>. Each 3D NAND memory string <NUM> extends vertically through a plurality of pairs each including a conductor layer <NUM> and a dielectric layer <NUM>, according to some embodiments. The stacked and interleaved conductor layers <NUM> and dielectric layer <NUM> are also referred to herein as a memory stack <NUM>. Interleaved conductor layers <NUM> and dielectric layers <NUM> in memory stack <NUM> alternate in the vertical direction, according to some embodiments. In other words, except the ones at the top or bottom of memory stack <NUM>, each conductor layer <NUM> can be adjoined by two dielectric layers <NUM> on both sides, and each dielectric layer <NUM> can be adjoined by two conductor layers <NUM> on both sides. Conductor layers <NUM> can each have the same thickness or different thicknesses. Similarly, dielectric layers <NUM> can each have the same thickness or different thicknesses. Conductor layers <NUM> can include conductor materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. Dielectric layers <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

In some embodiments, each 3D NAND memory string <NUM> is a "charge trap" type of NAND memory string including a semiconductor channel <NUM> and a memory film <NUM>. In some embodiments, semiconductor channel <NUM> includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, memory film <NUM> is a composite dielectric layer including a tunneling layer, a storage layer (also known as "charge trap/storage layer"), and a blocking layer. Each 3D NAND memory string <NUM> can have a cylinder shape (e.g., a pillar shape). Semiconductor channel <NUM>, the tunneling layer, the storage layer, and the blocking layer of memory film <NUM> are arranged along a direction from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, the blocking layer can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO). In another example, the blocking layer can include a high-k dielectric layer, such as aluminum oxide (Al<NUM>O<NUM>), hafnium oxide (HfO<NUM>) or tantalum oxide (Ta<NUM>O<NUM>) layer, and so on.

In some embodiments, 3D NAND memory strings <NUM> further include a plurality of control gates (each being part of a word line). Each conductor layer <NUM> in memory stack <NUM> can act as a control gate for each memory cell of 3D NAND memory string <NUM>. In some embodiments, each 3D NAND memory string <NUM> includes two plugs <NUM> and <NUM> at a respective end in the vertical direction. Plug <NUM> can include a semiconductor material, such as single-crystal silicon, that is epitaxially grown from a semiconductor layer <NUM>. Plug <NUM> can function as the channel controlled by a source select gate of 3D NAND memory string <NUM>. Plug <NUM> can be at the upper end of 3D NAND memory string <NUM> and in contact with semiconductor channel <NUM>. As used herein, the "upper end" of a component (e.g., 3D NAND memory string <NUM>) is the end father away from substrate <NUM> in the y-direction, and the "lower end" of the component (e.g., 3D NAND memory string <NUM>) is the end closer to substrate <NUM> in the y-direction when substrate <NUM> is positioned in the lowest plane of unified semiconductor chip <NUM>. Another Plug <NUM> can include semiconductor materials (e.g., polysilicon) or conductor materials (e.g., metals). In some embodiments, plug <NUM> includes an opening filled with titanium/titanium nitride (Ti/TiN, as a barrier and glue layer) and tungsten (as a conductor). By covering the upper end of 3D NAND memory string <NUM> during the fabrication of second semiconductor structure <NUM>, plug <NUM> can function as an etch stop layer to prevent etching of dielectrics filled in 3D NAND memory string <NUM>, such as silicon oxide and silicon nitride. In some embodiments, plug <NUM> functions as the drain of 3D NAND memory string <NUM>.

In some embodiments, second semiconductor structure <NUM> further includes semiconductor layer <NUM> disposed above memory stack <NUM> and 3D NAND memory strings <NUM>. Semiconductor layer <NUM> can be a thinned substrate on which memory stack <NUM> and 3D NAND memory strings <NUM> are formed. In some embodiments, semiconductor layer <NUM> includes single-crystal silicon from which plugs <NUM> can be epitaxially grown. In some embodiments, semiconductor layer <NUM> can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable materials. Semiconductor layer <NUM> can also include isolation regions and doped regions (e.g., functioning as an array common source for 3D NAND memory strings <NUM>, not shown). Isolation regions (not shown) can extend across the entire thickness or part of the thickness of semiconductor layer <NUM> to electrically isolate the doped regions. In some embodiments, a pad oxide layer including silicon oxide is disposed between memory stack <NUM> and semiconductor layer <NUM>.

It is understood that 3D NAND memory strings <NUM> are not limited to the "charge trap" type of 3D NAND memory strings and may be "floating gate" type of 3D NAND memory strings in other embodiments. Semiconductor layer <NUM> may include polysilicon as the source plate of the "floating gate" type of 3D NAND memory strings.

As shown in <FIG>, second semiconductor structure <NUM> of unified semiconductor chip <NUM> can further include a pad-out interconnect layer <NUM> above semiconductor layer <NUM>. Pad-out interconnect layer <NUM> include interconnects, e.g., contact pads <NUM>, in one or more ILD layers. Pad-out interconnect layer <NUM> and interconnect layer <NUM> can be formed at opposite sides of semiconductor layer <NUM>. In some embodiments, the interconnects in pad-out interconnect layer <NUM> can transfer electrical signals between unified semiconductor chip <NUM> and outside circuits, e.g., for pad-out purposes.

In some embodiments, second semiconductor structure <NUM> further includes one or more contacts <NUM> extending through semiconductor layer <NUM> to electrically connect pad-out interconnect layer <NUM> and interconnect layers <NUM> and <NUM>. As a result, array of embedded DRAM cells <NUM> can be electrically connected to array of 3D NAND memory strings <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. One or more processors <NUM> (and controllers and the peripheral circuit if any) can also be electrically connected to array of 3D NAND memory strings <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Moreover, processors <NUM>, array of embedded DRAM cells <NUM>, and array of 3D NAND memory strings <NUM> can be electrically connected to outside circuits through contacts <NUM> and pad-out interconnect layer <NUM>.

<FIG> illustrates a cross-section of an exemplary unified semiconductor chip <NUM> having 2D NAND memory, according to some embodiments. Similar to unified semiconductor chip <NUM> described above in <FIG>, unified semiconductor chip <NUM> represents an example of a bonded chip including first semiconductor structure <NUM> having one or more processors <NUM> and embedded DRAM cells <NUM>. Different from unified semiconductor chip <NUM> described above in <FIG> that includes second semiconductor structure <NUM> having 3D NAND memory strings <NUM>, unified semiconductor chip <NUM> in <FIG> includes a second semiconductor structure <NUM> having 2D NAND memory cells <NUM>. Similar to unified semiconductor chip <NUM> described above in <FIG>, first and second semiconductor structures <NUM> and <NUM> of unified semiconductor chip <NUM> are bonded in a face-to-face manner at bonding interface <NUM>, as shown in <FIG>. It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both unified semiconductor chips <NUM> and <NUM> may not be repeated below.

Similarly, as shown in <FIG>, second semiconductor structure <NUM> of unified semiconductor chip <NUM> also includes a bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM> of first semiconductor structure <NUM>. Bonding layer includes a plurality of bonding contacts <NUM>. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding. In some embodiments, second semiconductor structure <NUM> of unified semiconductor chip <NUM> further includes an interconnect layer <NUM> above bonding layer <NUM> to transfer electrical signals. Interconnect layer <NUM> can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. Interconnect layer <NUM> can further include one or more ILD layers in which the interconnect lines and via contacts can form.

In some embodiments, second semiconductor structure <NUM> of unified semiconductor chip <NUM> includes a NAND Flash memory device in which memory cells are provided in the form of an array of 2D NAND memory cells <NUM> above interconnect layer <NUM> and bonding layer <NUM>. Array of 2D NAND memory cells <NUM> can include a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells <NUM> connected in series by sources/drains <NUM> (resembling a NAND gate) and two select transistors <NUM> at the ends of the 2D NAND memory string, respectively. In some embodiments, each 2D NAND memory string further includes one or more select gates and/or dummy gates besides select transistors <NUM>. In some embodiments, each 2D NAND memory cell <NUM> includes a floating-gate transistor having a floating gate <NUM> and a control gate <NUM> stacked vertically. Floating gate <NUM> can include semiconductor materials, such as polysilicon. Control gate <NUM> can be part of the word line of the NAND Flash memory device and include conductive materials including, but not limited to, W, Co, Cu, Al, doped polysilicon, silicides, or any combination thereof. In some embodiments, the floating-gate transistor further includes dielectric layers, such as a blocking layer disposed vertically between control gate <NUM> and floating gate <NUM> and a tunneling layer disposed above floating gate <NUM>. The blocking layer can include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. The tunneling layer can include silicon oxide, silicon oxynitride, or a combination thereof. Channels can be formed laterally between sources/drains <NUM> and above the gate stacks (including the tunneling layer, floating gate <NUM>, the blocking layer, and control gate <NUM>). Each channel is controlled by the voltage signal applied to the respective gate stack through control gate <NUM>, according to some embodiments. It is understood that 2D NAND memory cell <NUM> may include a charge-trap transistor, which replaces floating gate <NUM> with a storage layer as described above in detail. In some embodiments, the storage layer includes silicon nitride, silicon oxynitride, or any combination thereof and has a thickness smaller than that of floating gate <NUM>.

In some embodiments, second semiconductor structure <NUM> further includes semiconductor layer <NUM> disposed above and in contact with array of 2D NAND memory cells <NUM>. Semiconductor layer <NUM> can be a thinned substrate on which 2D NAND memory cells <NUM> are formed. In some embodiments, semiconductor layer <NUM> includes single-crystal silicon. In some embodiments, semiconductor layer <NUM> includes polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable materials. Semiconductor layer <NUM> can also include isolation regions and doped regions (e.g., functioning as sources/drains <NUM> of 2D NAND memory cells <NUM>).

As shown in <FIG>, second semiconductor structure <NUM> of unified semiconductor chip <NUM> can further include a pad-out interconnect layer <NUM> above semiconductor layer <NUM>. Pad-out interconnect layer <NUM> includes interconnects, e.g., contact pads <NUM>, in one or more ILD layers, according to some embodiments. Pad-out interconnect layer <NUM> and interconnect layer <NUM> can be formed at opposite sides of semiconductor layer <NUM>. The interconnects in pad-out interconnect layer <NUM> can transfer electrical signals between unified semiconductor chip <NUM> and outside circuits, e.g., for pad-out purposes.

In some embodiments, second semiconductor structure <NUM> further includes one or more contacts <NUM> extending vertically through semiconductor layer <NUM> to electrically connect pad-out interconnect layer <NUM> and interconnect layers <NUM> and <NUM>. As a result, embedded DRAM cells <NUM> can be electrically connected to 2D NAND memory cells <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. One or more processors <NUM> (and controllers and the peripheral circuit if any) can also be electrically connected to 2D NAND memory cells <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Moreover, processors <NUM>, embedded DRAM cells <NUM>, and 2D NAND memory cells <NUM> can be electrically connected to outside circuits through contacts <NUM> and pad-out interconnect layer <NUM>.

<FIG> illustrates a cross-section of another exemplary unified semiconductor chip <NUM> having 3D NAND memory, according to some embodiments. Similar to unified semiconductor chip <NUM> described above in <FIG>, unified semiconductor chip <NUM> represents an example of a bonded chip in which a first semiconductor structure <NUM> including 3D NAND memory strings and a second semiconductor structure <NUM> including one or more processors and embedded DRAM cells are formed separately and bonded in a face-to-face manner at a bonding interface <NUM>. Different from unified semiconductor chip <NUM> described above in <FIG> in which first semiconductor structure <NUM> including the processors and embedded DRAM cells is below second semiconductor structure <NUM> including the 3D NAND memory strings, unified semiconductor chip <NUM> in <FIG> includes second semiconductor structure <NUM> including one or more processors and embedded DRAM cells disposed above first semiconductor structure <NUM> including 3D NAND memory strings. It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both unified semiconductor chips <NUM> and <NUM> may not be repeated below.

First semiconductor structure <NUM> of unified semiconductor chip <NUM> can include a substrate <NUM> and a memory stack <NUM> including interleaved conductor layers <NUM> and dielectric layers <NUM> above substrate <NUM>. In some embodiments, an array of 3D NAND memory strings <NUM> each extends vertically through interleaved conductor layers <NUM> and dielectric layers <NUM> in memory stack <NUM> above substrate <NUM>. Each 3D NAND memory string <NUM> can include a semiconductor channel <NUM> and a memory film <NUM>. Each 3D NAND memory string <NUM> further includes two plugs <NUM> and <NUM> at its lower end and upper end, respectively. 3D NAND memory strings <NUM> can be "charge trap" type of 3D NAND memory strings or "floating gate" type of 3D NAND memory strings. In some embodiments, a pad oxide layer including silicon oxide is disposed between memory stack <NUM> and substrate <NUM>.

In some embodiments, first semiconductor structure <NUM> of unified semiconductor chip <NUM> also includes an interconnect layer <NUM> above memory stack <NUM> and 3D NAND memory strings <NUM> to transfer electrical signals to and from 3D NAND memory strings <NUM>. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in interconnect layer <NUM> also include local interconnects, such as bit line contacts and word line contacts. In some embodiments, first semiconductor structure <NUM> of unified semiconductor chip <NUM> further includes a bonding layer <NUM> at bonding interface <NUM> and above interconnect layer <NUM> and memory stack <NUM>. Bonding layer <NUM> includes a plurality of bonding contacts <NUM> and dielectrics surrounding and electrically isolating bonding contacts <NUM>.

As shown in <FIG>, second semiconductor structure <NUM> of unified semiconductor chip <NUM> includes another bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM>. Bonding layer <NUM> includes a plurality of bonding contacts <NUM> and dielectrics surrounding and electrically isolating bonding contacts <NUM>. In some embodiments, second semiconductor structure <NUM> of unified semiconductor chip <NUM> also includes an interconnect layer <NUM> above bonding layer <NUM> to transfer electrical signals. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts.

Second semiconductor structure <NUM> of unified semiconductor chip <NUM> can further include a device layer <NUM> above interconnect layer <NUM> and bonding layer <NUM>. In some embodiments, device layer <NUM> includes one or more processors <NUM> above interconnect layer <NUM> and bonding layer <NUM> and an array of embedded DRAM cells <NUM> above interconnect layer <NUM> and bonding layer <NUM> and outside of processors <NUM>. In some embodiments, the devices in device layer <NUM> are electrically connected to one another through the interconnects in interconnect layer <NUM>. For example, array of embedded DRAM cells <NUM> may be electrically connected to processors <NUM> through interconnect layer <NUM>.

In some embodiments, processors <NUM> include a plurality of logic transistors <NUM> forming any suitable specialized processors and/or SoCs, such as an application processor (e.g., including one or more CPUs and GPUs) and a baseband processor. Device layer <NUM> can also include one or more controllers and/or the peripheral circuit of the 3D NAND memory formed by logic transistors <NUM> as described above in detail. Logic transistors <NUM> can be formed "on" a semiconductor layer <NUM>, in which the entirety or part of logic transistors <NUM> are formed in semiconductor layer <NUM> and/or directly on semiconductor layer <NUM>. Isolation regions (e.g., STIs) and doped regions (e.g., source regions and drain regions of logic transistors <NUM>) can be formed in semiconductor layer <NUM> as well.

In some embodiments, each embedded DRAM cell <NUM> includes a DRAM selection transistor <NUM> and a capacitor <NUM>. Embedded DRAM cell <NUM> can be a 1T1C cell consisting of one transistor and one capacitor. It is understood that embedded DRAM cell <NUM> may be of any suitable configurations, such as 2T1C cell, 3T1C cell, etc. In some embodiments, DRAM selection transistors <NUM> are formed "on" semiconductor layer <NUM>, in which the entirety or part of DRAM selection transistors <NUM> are formed in semiconductor layer <NUM> and/or directly on semiconductor layer <NUM>. Isolation regions (e.g., STIs) and doped regions (e.g., source regions and drain regions of DRAM selection transistors <NUM>) can be formed in semiconductor layer <NUM> as well. As shown in <FIG>, DRAM selection transistors <NUM> and logic transistors <NUM> can be formed, in embodiments which do not form part of the claimed invention, in different regions on the same plane, e.g., on semiconductor layer <NUM>. That is, DRAM selection transistors <NUM> can be formed outside of the region in which processors <NUM> are formed on semiconductor layer <NUM>. In some embodiments, capacitors <NUM> are disposed below DRAM selection transistors <NUM>. Each capacitor <NUM> includes two electrodes, one of which is electrically connected to one node of respective DRAM selection transistor <NUM>, according to some embodiments. Another node of each DRAM selection transistor <NUM> is electrically connected to a bit line <NUM> of embedded DRAM, according to some embodiments. Another electrode of each capacitor <NUM> can be electrically connected to a common plate <NUM>, e.g., a common ground. It is understood that the structure and configuration of embedded DRAM cell <NUM> are not limited to the example in <FIG> and may include any suitable structure and configuration. For example, capacitor <NUM> may be a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor.

In some embodiments, second semiconductor structure <NUM> further includes semiconductor layer <NUM> disposed above device layer <NUM>. Semiconductor layer <NUM> can be a thinned substrate on which logic transistors <NUM> and DRAM selection transistors <NUM> are formed. In some embodiments, semiconductor layer <NUM> includes single-crystal silicon. In some embodiments, semiconductor layer <NUM> can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable materials. Semiconductor layer <NUM> can also include isolation regions and doped regions.

As shown in <FIG>, second semiconductor structure <NUM> of unified semiconductor chip <NUM> can further include a pad-out interconnect layer <NUM> above semiconductor layer <NUM>. Pad-out interconnect layer <NUM> include interconnects, e.g., contact pads <NUM>, in one or more ILD layers. In some embodiments, the interconnects in pad-out interconnect layer <NUM> can transfer electrical signals between unified semiconductor chip <NUM> and outside circuits, e.g., for pad-out purposes. In some embodiments, second semiconductor structure <NUM> further includes one or more contacts <NUM> extending through semiconductor layer <NUM> to electrically connect pad-out interconnect layer <NUM> and interconnect layers <NUM> and <NUM>. As a result, array of embedded DRAM cells <NUM> can be electrically connected to array of 3D NAND memory strings <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. One or more processors <NUM> (and controllers and the peripheral circuit if any) can also be electrically connected to array of 3D NAND memory strings <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Moreover, processors <NUM>, array of embedded DRAM cells <NUM>, and array of 3D NAND memory strings <NUM> can be electrically connected to outside circuits through contacts <NUM> and pad-out interconnect layer <NUM>.

<FIG> illustrates a cross-section of another exemplary unified semiconductor chip <NUM> having 2D NAND memory, according to some embodiments. Similar to unified semiconductor chip <NUM> described above in <FIG>, unified semiconductor chip <NUM> represents an example of a bonded chip including second semiconductor structure <NUM> having one or more processors <NUM> and embedded DRAM cells <NUM>. Different from unified semiconductor chip <NUM> described above in <FIG> that includes first semiconductor structure <NUM> having 3D NAND memory strings <NUM>, unified semiconductor chip <NUM> in <FIG> includes a first semiconductor structure <NUM> having 2D NAND memory cells <NUM>. Similar to unified semiconductor chip <NUM> described above in <FIG>, first and second semiconductor structures <NUM> and <NUM> of unified semiconductor chip <NUM> are bonded in a face-to-face manner at bonding interface <NUM>, as shown in <FIG>. It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both unified semiconductor chips <NUM> and <NUM> may not be repeated below.

In some embodiments, first semiconductor structure <NUM> of unified semiconductor chip <NUM> includes a NAND Flash memory device in which memory cells are provided in the form of an array of 2D NAND memory cells <NUM> on substrate <NUM>. Array of 2D NAND memory cells <NUM> can include a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells connected in series by sources/drains <NUM> (resembling a NAND gate) and two select transistors <NUM> at the ends of the 2D NAND memory string, respectively. In some embodiments, each 2D NAND memory cell <NUM> includes a floating-gate transistor having a floating gate <NUM> and a control gate <NUM> stacked vertically. In some embodiments, the floating-gate transistor further includes dielectric layers, such as a blocking layer disposed vertically between control gate <NUM> and floating gate <NUM> and a tunneling layer disposed below floating gate <NUM>. Channels can be formed laterally between sources/drains <NUM> and below the gate stacks (including the tunneling layer, floating gate <NUM>, the blocking layer, and control gate <NUM>). Each channel is controlled by the voltage signal applied to the respective gate stack through control gate <NUM>, according to some embodiments. It is understood that 2D NAND memory cell <NUM> may include a charge-trap transistor, which replaces floating gate <NUM> with a storage layer as described above in detail.

In some embodiments, first semiconductor structure <NUM> of unified semiconductor chip <NUM> also includes an interconnect layer <NUM> above 2D NAND memory cells <NUM> to transfer electrical signals to and from 2D NAND memory cells <NUM>. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in interconnect layer <NUM> also include local interconnects, such as bit line contacts and word line contacts. In some embodiments, first semiconductor structure <NUM> of unified semiconductor chip <NUM> further includes a bonding layer <NUM> at bonding interface <NUM> and above interconnect layer <NUM> and 2D NAND memory cells <NUM>. Bonding layer <NUM> includes a plurality of bonding contacts <NUM> and dielectrics surrounding and electrically isolating bonding contacts <NUM>.

<FIG> illustrate a fabrication process for forming an exemplary semiconductor structure having one or more processors and an embedded DRAM, according to some embodiments. <FIG> and <FIG> illustrate a fabrication process for forming an exemplary semiconductor structure having 3D NAND memory strings, according to some embodiments. <FIG> and <FIG> illustrate a fabrication process for forming an exemplary unified semiconductor chip, according to some embodiments. <FIG> is a flowchart of an exemplary method <NUM> for forming a unified semiconductor chip, according to some embodiments. Examples of the unified semiconductor chip depicted in <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> include unified semiconductor chip <NUM> depicted in <FIG> and unified semiconductor chip <NUM> depicted in <FIG>. <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

As depicted in <FIG>, a first semiconductor structure including one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts is formed. As depicted in <FIG> and <FIG>, a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts is formed. As depicted in <FIG> and <FIG>, the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which the one or more processors and the array of embedded DRAM cells are formed on a first substrate. The first substrate can be a silicon substrate. In some embodiments, to form the processors and the array of embedded DRAM cells, a plurality of transistors are formed on the first substrate, and a plurality of capacitors are formed above and in contact with some of the transistors. In some embodiments, one or more controllers are formed on the first substrate. In some embodiments, a peripheral circuit of the array of NAND memory cells is formed on the first substrate.

As illustrated in <FIG>, a plurality of transistors (e.g., logic transistors <NUM> and DRAM selection transistors <NUM>) are formed on a silicon substrate <NUM>. Transistors <NUM> and <NUM> can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions are formed in silicon substrate <NUM> by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of transistors <NUM> and <NUM>. In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate <NUM> by wet/dry etch and thin film deposition.

As illustrated in <FIG>, a plurality of capacitors <NUM> are formed above and in contact with DRAM selection transistors <NUM>. Each capacitor <NUM> can be patterned by photography to be aligned with respective DRAM selection transistor <NUM> to form a 1T1C memory cell, for example, by electrically connecting one electrode of capacitor <NUM> with one node of respective DRAM selection transistor <NUM>. In some embodiments, bit lines <NUM> and common plates <NUM> are formed as well for electrically connecting DRAM selection transistors <NUM> and capacitors <NUM>. Capacitors <NUM> can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. A device layer <NUM> including one or more processors (having logic transistors <NUM>) and an array of embedded DRAM cells (each having DRAM selection transistor <NUM> and capacitor <NUM>) is thereby formed. In some embodiments, device layer <NUM> further includes one or more controllers and/or a peripheral circuit of the array of NAND memory cells formed by logic transistors <NUM> as well.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first interconnect layer is formed above the processors and the array of embedded DRAM cells. The first interconnect layer can include a first plurality of interconnects in one or more ILD layers. As illustrated in <FIG>, an interconnect layer <NUM> can be formed above device layer <NUM> including the processors (having logic transistors <NUM>) and the array of embedded DRAM cells (each having DRAM selection transistor <NUM> and capacitor <NUM>). Interconnect layer <NUM> can include interconnects of MEOL and/or BEOL in a plurality of ILD layers to make electrical connections with device layer <NUM>. In some embodiments, interconnect layer <NUM> includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in interconnect layers <NUM> can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. Fabrication processes to form the interconnects can also include photolithography, CMP, wet/dry etch, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in <FIG> can be collectively referred to as interconnect layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first bonding layer is formed above the first interconnect layer. The first bonding layer includes a plurality of first bonding contacts. As illustrated in <FIG>, a bonding layer <NUM> is formed above interconnect layer <NUM>. Bonding layer <NUM> includes a plurality of bonding contacts <NUM> surrounded by dielectrics. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer <NUM> by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts <NUM> then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer <NUM> by first patterning contact holes through the dielectric layer using patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and/or a seed layer before depositing the conductor.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a memory stack is formed above a second substrate. The second substrate can be a silicon substrate. As illustrated in <FIG>, interleaved sacrificial layers (not shown) and dielectric layers <NUM> are formed above a silicon substrate <NUM>. The interleaved sacrificial layers and dielectric layers <NUM> can form a dielectric stack (not shown). In some embodiments, each sacrificial layer includes a layer of silicon nitride, and each dielectric layer <NUM> includes a layer of silicon oxide. The interleaved sacrificial layers and dielectric layers <NUM> can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some embodiments, a memory stack <NUM> can be formed by a gate replacement process, e.g., replacing the sacrificial layers with conductor layers <NUM> using wet/dry etch of the sacrificial layers selective to dielectric layers <NUM> and filling the resulting recesses with conductor layers <NUM>. As a result, memory stack <NUM> can include interleaved conductor layers <NUM> and dielectric layers <NUM>. In some embodiments, each conductor layer <NUM> includes a metal layer, such as a layer of tungsten. It is understood that memory stack <NUM> may be formed by alternatingly depositing conductor layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without the gate replacement process in other embodiments. In some embodiments, a pad oxide layer including silicon oxide is formed between memory stack <NUM> and silicon substrate <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the array of 3D NAND memory strings extending vertically through the memory stack are formed. As illustrated in <FIG>, 3D NAND memory strings <NUM> are formed above silicon substrate <NUM>, each of which extends vertically through interleaved conductor layers <NUM> and dielectric layers <NUM> of memory stack <NUM>. In some embodiments, fabrication processes to form 3D NAND memory string <NUM> include forming a channel hole through memory stack <NUM> and into silicon substrate <NUM> using dry etching/and or wet etching, such as deep reactive-ion etching (DRIE), followed by epitaxially growing a plug <NUM> in the lower portion of the channel hole from silicon substrate <NUM>. In some embodiments, fabrication processes to form 3D NAND memory string <NUM> also include subsequently filling the channel hole with a plurality of layers, such as a memory film <NUM> (e.g., a tunneling layer, a storage layer, and a blocking layer) and a semiconductor layer <NUM>, using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof. In some embodiments, fabrication processes to form 3D NAND memory string <NUM> further include forming another plug <NUM> in the upper portion of the channel hole by etching a recess at the upper end of 3D NAND memory string <NUM>, followed by filling the recess with a semiconductor material using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second interconnect layer is formed above the array of 3D NAND memory strings. The second interconnect layer can include a second plurality of interconnects in one or more ILD layers. As illustrated in <FIG>, an interconnect layer <NUM> can be formed above memory stack <NUM> and array of 3D NAND memory strings <NUM>. Interconnect layer <NUM> can include interconnects of MEOL and/or BEOL in a plurality of ILD layers to make electrical connections with 3D NAND memory strings <NUM>. In some embodiments, interconnect layer <NUM> includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in interconnect layers <NUM> can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Fabrication processes to form the interconnects can also include photolithography, CMP, wet/dry etch, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in <FIG> can be collectively referred to as interconnect layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second bonding layer is formed above the second interconnect layer. The second bonding layer includes a plurality of second bonding contacts. As illustrated in <FIG>, a bonding layer <NUM> is formed above interconnect layer <NUM>. Bonding layer <NUM> includes a plurality of bonding contacts <NUM> surrounded by dielectrics. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer <NUM> by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts <NUM> then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer <NUM> by first patterning contact holes through the dielectric layer using patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and/or a seed layer before depositing the conductor.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first substrate and the second substrate are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at the bonding interface. The bonding can be hybrid bonding. In some embodiments, the first substrate on which the processors and embedded DRAM cells are formed (e.g., the first semiconductor structure) is disposed above the second substrate on which the 3D NAND memory strings are formed (e.g., the second semiconductor structure) after the bonding. In some embodiments, the second substrate on which the 3D NAND memory strings are formed (e.g., the second semiconductor structure) is disposed above the first substrate on which the processors and embedded DRAM cells are formed (e.g., the first semiconductor structure) after the bonding.

As illustrated in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., 3D NAND memory strings <NUM>) are flipped upside down. Bonding layer <NUM> facing down is bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming a bonding interface <NUM> (as shown in <FIG>). In some embodiments, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. Although not shown in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., device layer <NUM>) can be flipped upside down, and bonding layer <NUM> facing down can be bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming bonding interface <NUM>. After the bonding, bonding contacts <NUM> in bonding layer <NUM> and bonding contacts <NUM> in bonding layer <NUM> are aligned and in contact with one another, such that device layer <NUM> (e.g., the processors and embedded DRAM cells therein) can be electrically connected to 3D NAND memory strings <NUM>. It is understood that in the bonded chip, 3D NAND memory strings <NUM> may be either above or below device layer <NUM> (e.g., the processors and embedded DRAM cells therein). Nevertheless, bonding interface <NUM> can be formed between 3D NAND memory strings <NUM> and device layer <NUM> (e.g., the processors and embedded DRAM cells therein) after the bonding as illustrated in <FIG>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first substrate or the second substrate is thinned to form a semiconductor layer. In some embodiments, the first substrate of the first semiconductor structure, which is above the second substrate of the second semiconductor structure after the bonding, is thinned to form the semiconductor layer. In some embodiments, the second substrate of the second semiconductor structure, which is above the first substrate of the first semiconductor structure after the bonding, is thinned to form the semiconductor layer.

As illustrated in <FIG>, the substrate at the top of the bonded chip (e.g., silicon substrate <NUM> as shown in <FIG>) is thinned, so that the thinned top substrate can serve as a semiconductor layer <NUM>, for example, a single-crystal silicon layer. The thickness of the thinned substrate can be between about <NUM> and about <NUM>, such as between <NUM> and <NUM>, or between about <NUM> and about <NUM>, such as between <NUM> and <NUM>. Silicon substrate <NUM> can be thinned by processes including, but not limited to, wafer grinding, dry etch, wet etch, CMP, any other suitable processes, or any combination thereof. It is understood that when silicon substrate <NUM> is the substrate at the top of the bonded chip, another semiconductor layer may be formed by thinning silicon substrate <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a pad-out interconnect layer is formed above the semiconductor layer. As illustrated in <FIG>, a pad-out interconnect layer <NUM> is formed above semiconductor layer <NUM> (the thinned top substrate). Pad-out interconnect layer <NUM> can include interconnects, such as pad contacts <NUM>, formed in one or more ILD layers. Pad contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after the bonding and thinning, contacts <NUM> are formed extending vertically through semiconductor layer <NUM>, for example by wet/dry etch followed by depositing conductive materials. Contacts <NUM> can be in contact with the interconnects in pad-out interconnect layer <NUM>.

As described above, 2D NAND memory cells, instead of 3D NAND memory strings, may be formed on a separate substrate and bonded into the unified semiconductor chip. <FIG> and <FIG> illustrate a fabrication process for forming an exemplary semiconductor structure having 2D NAND memory cells, according to some embodiments. <FIG> and <FIG> illustrate a fabrication process for forming another exemplary unified semiconductor chip, according to some embodiments. <FIG> is a flowchart of another exemplary method <NUM> for forming a unified semiconductor chip, according to some embodiments. Examples of the unified semiconductor chip depicted in <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> include unified semiconductor chip <NUM> depicted in <FIG> and unified semiconductor chip <NUM> depicted in <FIG>. <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

Operations <NUM>, <NUM>, and <NUM> of method <NUM> in <FIG> are described above with respect to method <NUM> in <FIG> and thus, are not repeated. Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which an array of 2D NAND memory cells are formed on a second substrate. As illustrated in <FIG>, 2D NAND memory cells <NUM> are formed on silicon substrate <NUM> in the form of 2D NAND memory strings, each of which includes a plurality of memory cells connected in series by sources/drains <NUM> (resembling a NAND gate) and two select transistors <NUM> at the ends of the 2D NAND memory string, respectively. Memory cells <NUM> and select transistors <NUM> can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in silicon substrate <NUM> by ion implantation and/or thermal diffusion, which function, for example, as sources/drains <NUM>. In some embodiments, isolation regions (e.g., STIs, not shown) are also formed in silicon substrate <NUM> by wet/dry etch and thin film deposition.

In some embodiments, a gate stack is formed for each 2D NAND memory cell <NUM>. The gate stack can include a tunneling layer, a floating gate <NUM>, a blocking layer, and a control gate <NUM> from bottom to top in this order for "floating gate" type of 2D NAND memory cells <NUM>. In some embodiments, floating gate <NUM> is replaced by a storage layer for "charge trap" type of 2D NAND memory cells. The tunneling layer, floating gate <NUM> (or storage layer), blocking layer, and control gate <NUM> of the gate stack can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second interconnect layer is formed above the array of 2D NAND memory cells. The second interconnect layer can include a second plurality of interconnects in one or more ILD layers. As illustrated in <FIG>, an interconnect layer <NUM> can be formed above array of 2D NAND memory cells <NUM>. Interconnect layer <NUM> can include interconnects of MEOL and/or BEOL in a plurality of ILD layers to make electrical connections with 2D NAND memory cells <NUM>. In some embodiments, interconnect layer <NUM> includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in interconnect layers <NUM> can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in <FIG> can be collectively referred to as interconnect layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second bonding layer is formed above the second interconnect layer. The second bonding layer includes a plurality of second bonding contacts. As illustrated in <FIG>, a bonding layer <NUM> is formed above interconnect layer <NUM>. Bonding layer <NUM> includes a plurality of bonding contacts <NUM> surrounded by dielectrics. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer <NUM> by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts <NUM> then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer <NUM> by first patterning contact holes through the dielectric layer using patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing an adhesion layer, a barrier layer, and/or a seed layer before depositing the conductor.

Operations <NUM>, <NUM>, and <NUM> of method <NUM> in <FIG> are described above with respect to method <NUM> in <FIG> and thus, are not repeated. As illustrated in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., 2D NAND memory cells <NUM>) are flipped upside down. Bonding layer <NUM> facing down is bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming a bonding interface <NUM> (as shown in <FIG>). Although not shown in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., device layer <NUM>) can be flipped upside down, and bonding layer <NUM> facing down can be bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming bonding interface <NUM>. After the bonding, bonding contacts <NUM> in bonding layer <NUM> and bonding contacts <NUM> in bonding layer <NUM> are aligned and in contact with one another, such that device layer <NUM> (e.g., the processors and embedded DRAM cells therein) can be electrically connected to 2D NAND memory cells <NUM>. It is understood that in the bonded chip, 2D NAND memory cells <NUM> may be either above or below device layer <NUM> (e.g., the processors and embedded DRAM cells therein).

As illustrated in <FIG>, the substrate at the top of the bonded chip (e.g., silicon substrate <NUM> as shown in <FIG>) is thinned, so that the thinned top substrate can serve as a semiconductor layer <NUM>, for example, a single-crystal silicon layer. Silicon substrate <NUM> can be thinned by processes including, but not limited to, wafer grinding, dry etch, wet etch, CMP, any other suitable processes, or any combination thereof. It is understood that when silicon substrate <NUM> is the substrate at the top of the bonded chip, another semiconductor layer may be formed by thinning silicon substrate <NUM>. As illustrated in <FIG>, a pad-out interconnect layer <NUM> is formed above semiconductor layer <NUM> (the thinned top substrate). Pad-out interconnect layer <NUM> can include interconnects, such as pad contacts <NUM>, formed in one or more ILD layers. In some embodiments, after the bonding and thinning, contacts <NUM> are formed extending vertically through semiconductor layer <NUM>, for example by wet/dry etch followed by depositing conductive materials. Contacts <NUM> can be in contact with the interconnects in pad-out interconnect layer <NUM>.

As described above, in existing mobile devices, processing units (e.g., various processors and controllers) and memory (e.g., DRAM and NAND memory) are placed on the PCB as discrete chips, which communicate with each other through relatively long and slow interlinks (e.g., various data buses) on the PCB, thereby suffering from relatively low data throughput. Moreover, the large number of discrete chips occupy large PCB area, limiting the further reduction of the mobile device size and the equipment of a larger battery for longer battery life. For example, <FIG> illustrates a schematic diagram of discrete processor <NUM>, DRAM <NUM>, and NAND memory <NUM> on a PCB <NUM> and operations thereof. Each one of processor <NUM>, DRAM <NUM>, and NAND memory <NUM> is a discrete chip with its own package and mounted on PCB <NUM>. Processor <NUM> is an application processor or a baseband processor. Data is transmitted between processor <NUM> and DRAM <NUM> through an interlink, such as a memory bus. NAND memory <NUM> is a 3D NAND memory or a 2D NAND memory, which transfers data with DRAM <NUM> through another interlink, such as a peripheral component interconnect express (PCIe) bus or a serial at attachment (SATA) bus. Due to the relatively low data throughput between processor <NUM> and memory <NUM> and <NUM>, processor <NUM> also includes on-chip memory (e.g., cache) as a high-speed buffer for fast access, which further increases the PCB footprint of processor <NUM>.

<FIG> illustrates a schematic diagram of an exemplary unified semiconductor chip <NUM> on a PCB <NUM> and operations thereof, according to some embodiments. <FIG> is a flowchart of an exemplary method <NUM> for operating a unified semiconductor chip, according to some embodiments. Examples of the unified semiconductor chip depicted in <FIG> include unified semiconductor chip <NUM> depicted in <FIG> and <FIG> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>. As illustrated in <FIG>, unified semiconductor chip <NUM> includes a processor <NUM>, embedded DRAM <NUM> having an array of embedded DRAM cells, and NAND memory <NUM> having an array of NAND memory cells. Processor <NUM>, embedded DRAM <NUM>, and NAND memory <NUM> (either a 3D NAND memory or a 2D NAND memory) can be formed in the same bonded chip as described above in detail, such as unified semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which data is transferred from one or more processors to an array of embedded DRAM cells. As illustrated in <FIG>, any suitable type of data generated by processor <NUM> can be transferred to embedded DRAM <NUM> of unified semiconductor chip <NUM>, for example, display data generated by a GPU in an application processor to be presented by the display or data generated by a modem in a baseband application to be transmitted by the cellular transceiver.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the data is buffered in the array of embedded DRAM cells. As illustrated in <FIG>, embedded DRAM <NUM> can work as an integrated high-speed, on-chip buffer of unified semiconductor chip <NUM> for buffering the data transferred from processor <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the data is stored in the array of NAND memory cells from the array of embedded DRAM cells. As illustrated in <FIG>, the data buffered in embedded DRAM <NUM> can be stored in NAND memory <NUM>. In some embodiments, bidirectional, direct data transfer between processor <NUM> and NAND memory <NUM> becomes available, such that the data can be buffered in embedded DRAM <NUM> and stored in NAND memory <NUM> in parallel.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the data is transferred between the one or more processors and the array of NAND memory cells through a plurality of bonding contacts. For example, data can be bidirectionally transferred between processor <NUM> and NAND memory <NUM> through direct electrical connections by a plurality of bonding contacts (e.g., over millions of bonding contacts in parallel) as described above in detail, which have shortened distance, higher throughput, and lower power consumption compared with the conventional on-board chip-to-chip data bus, for example, shown in <FIG>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the data is transferred between the array of embedded DRAM cells and the array of NAND memory cells through the plurality of bonding contacts. For example, data can be bidirectionally transferred between embedded DRAM <NUM> and NAND memory <NUM> through direct electrical connections by a plurality of bonding contacts (e.g., over millions of bonding contacts in parallel) as described above in detail, which have shortened distance, higher throughput, and lower power consumption compared with the conventional on-board chip-to-chip data bus, for example, shown in <FIG>.

Embedded DRAM <NUM> along with direct electrical connections can work as the high-speed memory buffer to eliminate the need for on-chip memory, thereby reducing chip size and enable additional features, such as an instant-on feature. In some embodiments, the transferring of data between embedded DRAM <NUM> and NAND memory <NUM> is triggered in response to power on or power off of unified semiconductor device <NUM>. For example, an instant-on feature of unified semiconductor chip <NUM> can be enabled by the data transferred between embedded DRAM <NUM> and NAND memory <NUM>. In some embodiments, in response to power off of unified semiconductor chip <NUM>, a snapshot of user data and/or operation system data buffered in embedded DRAM <NUM> is immediately transferred to NAND memory <NUM>, which can be retained after power off. In response to power on of unified semiconductor chip <NUM>, the snapshot of user data and/or operation system data stored in NAND memory <NUM> can be immediately transferred back to embedded DRAM <NUM> to restore the last state of unified semiconductor chip <NUM> prior to the power-off.

<FIG> illustrates a schematic diagram of an exemplary mobile device <NUM> having a unified semiconductor chip <NUM>, according to some embodiments. Mobile device <NUM> can be any portable or handheld computing devices including, but not limited to VR/AR headsets, smartphones, tablets, eyeglasses, wrist watches, portable gaming consoles, laptop computers, etc. Mobile device <NUM> includes a display <NUM> and a plurality of transceivers including a cellular transceiver <NUM> for cellular communication, a Bluetooth transceiver <NUM> for Bluetooth communication, a Wi-Fi transceiver <NUM> for Wi-Fi communication, and a GPS transceiver <NUM> for positioning and navigation. Display <NUM> may be an organic light emitting diode (OLED) display, a micro-LED display, a liquid crystal display (LCD), an E-ink display, an electroluminescent display (ELD), or any other suitable type of display. It is understood that mobile device <NUM> may include additional components that are not shown in <FIG>, such as a battery, a camera, various sensors, to name a few.

Unified semiconductor chip <NUM> can be any unified semiconductor chips disclosed herein (e.g., unified semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>) operatively coupled to display <NUM> and transceivers <NUM>, <NUM>, <NUM>, and <NUM> through any suitable interfaces and interlinks. As described above in detail and according to the claimed invention, unified semiconductor chip <NUM> is a single chip that includes two semiconductor structures (not shown) bonded together. In accordance with the claimed invention, a first semiconductor structure includes an application processor, a baseband processor, an array of embedded DRAM cells, and a first bonding layer including first bonding contacts, and a second semiconductor structure includes an array of NAND memory cells and a second bonding layer including second bonding contacts. A bonding interface exists between the first bonding layer and the second bonding layer at which the first bonding contacts are in contact with the second bonding contacts, according to the claimed invention.

In some embodiments, the application processor in unified semiconductor chip <NUM> is configured to generate data to be presented by display <NUM>, and the baseband processor is configured to process data received by cellular transceiver <NUM> and data to be transmitted by cellular transceiver <NUM>. The data transferred between the application processor and display <NUM> or between the baseband processor and cellular transceiver <NUM> is buffered in the array of embedded DRAM cells, according to some embodiments. As a result, in some embodiments, the application processor is free of on-chip memory. In some embodiments, the application processor in unified semiconductor chip <NUM> is further configured to transfer data from or to the array of NAND memory cells through the first and the second bonding contacts.

Claim 1:
A unified semiconductor chip (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), comprising:
a first semiconductor structure (<NUM>, <NUM>, <NUM>, <NUM>) comprising a plurality of processors (<NUM>, <NUM>, <NUM>, <NUM>), wherein the plurality of processors (<NUM>, <NUM>, <NUM>, <NUM>) comprises an application processor (<NUM>) and a baseband processor (<NUM>), an array of embedded dynamic random-access memory, DRAM, cells, and a first bonding layer (<NUM>, <NUM>, <NUM>, <NUM>) comprising a plurality of first bonding contacts (<NUM>, <NUM>, <NUM>, <NUM>);
a second semiconductor structure (<NUM>, <NUM>, <NUM>, <NUM>) comprising an array of NAND memory cells and a second bonding layer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprising a plurality of second bonding contacts (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>); and
a bonding interface (<NUM>, <NUM>, <NUM>, <NUM>) between the first bonding layer (<NUM>, <NUM>, <NUM>, <NUM>) and the second bonding layer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>), wherein the first bonding contacts (<NUM>, <NUM>, <NUM>, <NUM>) are in contact with the second bonding contacts (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) at the bonding interface (<NUM>, <NUM>, <NUM>, <NUM>), the plurality of processors (<NUM>, <NUM>, <NUM>, <NUM>) and the array of embedded DRAM cells (<NUM>, <NUM>) being stacked one over another.