Patent Description:
Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices, which typically has the advantage of keeping stored data even when the device is not connected to an electrical source.

The aforementioned MR effect has also been used in magnetic field sensor areas including but not limited to for example electronic compass components used in global positioning system (GPS) of cellular phones for providing information regarding moving location to users. Currently, various magnetic field sensor technologies such as anisotropic magnetoresistance (AMR) sensors, GMR sensors, magnetic tunneling junction (MTJ) sensors have been widely developed in the market. Nevertheless, most of these products still pose numerous shortcomings such as high chip area, high cost, high power consumption, limited sensibility, and easily affected by temperature variation and how to come up with an improved device to resolve these issues has become an important task in this field. <CIT> relates to a magneto resistive stack/structure and a method for obtaining it. <CIT> relates to a magnetic tunneling junction with synthetic free layer for spin orbit torque MRAM
<CIT> relates to a strained ferromagnetic Hall metal spin orbit torque layer.

According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic random access memory (MRAM) region and a logic region, forming a first inter-metal dielectric (IMD) layer on the substrate, forming a first metal interconnection and a second metal interconnection in the first IMD layer on the MRAM region, forming a spin orbit torque (SOT) layer on the first metal interconnection and the second metal interconnection, forming a magnetic tunneling junction (MTJ) stack on the SOT layer, forming a hard mask on the MTJ stack, using the hard mask to pattern the MTJ stack for forming the MTJ, forming the cap layer on the SOT layer and the hard mask, and patterning the cap layer and the SOT layer.

According to the present invention, a semiconductor device includes a spin orbit torque (SOT) layer on a substrate, a magnetic tunneling junction (MTJ) on the SOT layer, a hard mask on the MTJ, and a cap layer on the SOT layer and the MTJ.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings, the invention being defined by the appended claims.

<FIG> illustrate a method for fabricating a MRAM device according to an embodiment of the present invention.

Referring to <FIG> illustrate a method for fabricating a MRAM device according to an embodiment of the present invention. As shown in <FIG>, a substrate <NUM> made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si-Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs), and a MRAM region <NUM> and a logic region <NUM> are defined on the substrate <NUM>.

Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer <NUM> could also be formed on top of the substrate <NUM>. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate <NUM>, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain region, spacer, epitaxial layer, and contact etch stop layer (CESL). The ILD layer <NUM> could be formed on the substrate <NUM> to cover the MOS transistors, and a plurality of contact plugs could be formed in the ILD layer <NUM> to electrically connect to the gate structure and/or source/drain region of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

Next, metal interconnect structures <NUM>, <NUM> are sequentially formed on the ILD layer <NUM> on the MRAM region <NUM> and the logic region <NUM> to electrically connect the aforementioned contact plugs, in which the metal interconnect structure <NUM> includes an inter-metal dielectric (IMD) layer <NUM> and metal interconnections <NUM> embedded in the IMD layer <NUM>, and the metal interconnect structure <NUM> includes a stop layer <NUM>, an IMD layer <NUM>, and at least two metal interconnections <NUM> embedded in the stop layer <NUM> and the IMD layer <NUM> on the MRAM region <NUM>.

In this embodiment, each of the metal interconnections <NUM> from the metal interconnect structure <NUM> preferably includes a trench conductor and the metal interconnection <NUM> from the metal interconnect structure <NUM> on the MRAM region <NUM> includes a via conductor. Preferably, each of the metal interconnections <NUM>, <NUM> from the metal interconnect structures <NUM>, <NUM> could be embedded within the IMD layers <NUM>, <NUM> and/or stop layer <NUM> according to a single damascene process or dual damascene process. For instance, each of the metal interconnections <NUM>, <NUM> could further include a barrier layer <NUM> and a metal layer <NUM>, in which the barrier layer <NUM> could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer <NUM> could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. In this embodiment, the metal layers <NUM> in the metal interconnections <NUM> are preferably made of copper, the metal layer <NUM> in the metal interconnections <NUM> is made of tungsten, the IMD layers <NUM>, <NUM> are preferably made of silicon oxide such as tetraethyl orthosilicate (TEOS), and the stop layer <NUM> is preferably made of nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or combination thereof.

Next, as shown in <FIG>, a spin orbit torque (SOT) layer <NUM>, a MTJ stack <NUM> or stack structure, and a hard mask <NUM> are formed on the metal interconnect structure <NUM>. In this embodiment, the formation of the MTJ stack <NUM> could be accomplished by sequentially depositing a pinned layer, a barrier layer, and a free layer on the SOT layer <NUM>. Preferably, the pinned layer could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB) or cobalt-iron (CoFe). Alternatively, the pinned layer could also be made of antiferromagnetic (AFM) material including but not limited to for example ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), or combination thereof, in which the pinned layer is formed to fix or limit the direction of magnetic moment of adjacent layers. The barrier layer could be made of insulating material including but not limited to for example oxides such as aluminum oxide (AlOx) or magnesium oxide (MgO). The free layer could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), in which the magnetized direction of the free layer could be altered freely depending on the influence of outside magnetic field.

Preferably, the SOT layer <NUM> is serving as a channel for the MRAM device as the SOT layer <NUM> could include metals such as tantalum (Ta), tungsten (W), platinum (Pt), or hafnium (Hf) and/or topological insulator such as bismuth selenide (BixSe<NUM>-x). The hard mask <NUM> preferably includes conductive or dielectric material such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or combination thereof.

Next, as shown in <FIG>, an etching process or more specifically a photo-etching process is conducted to pattern the hard mask <NUM> for exposing the surface of the MTJ stack <NUM> underneath. Specifically, the photo-etching process could be accomplished by first forming a patterned mask (not shown) such as patterned resist on the hard mask <NUM>, and then an etching process is conducted by using the patterned mask to remove part of the hard mask <NUM> for forming a patterned hard mask <NUM> and exposing the surface of the MTJ stack <NUM>. Preferably, the etching process conducted at this stage includes a reactive ion etching (RIE) process.

Next, as shown in <FIG>, one or more etching process is conducted by using the patterned hard mask <NUM> as mask to remove part of the MTJ stack <NUM> for forming a MTJ <NUM> on the MRAM region <NUM>, in which part of the hard mask <NUM> could be consumed so that the overall thickness of the hard mask <NUM> could be slightly reduced during the etching process.

Next, as shown in <FIG>, a cap layer <NUM> is formed on the MTJ <NUM> to cover the surface of the SOT layer <NUM> on the MRAM region <NUM> and logic region <NUM>. In this embodiment, the cap layer <NUM> preferably includes silicon nitride (SiN), but could also include other dielectric material including but not limited to for example silicon oxide, silicon oxynitride (SiON), or silicon carbon nitride (SiCN).

Next, as shown in <FIG>, an etching process is conducted without forming any patterned mask to remove part of the cap layer <NUM> so that the cap layer <NUM> directly contacting the top surface of the hard mask <NUM> and the cap layer <NUM> directly contacting the top surface of the SOT layer <NUM> have same thickness while the cap layer <NUM> directly contacting the top surface of the SOT layer <NUM> and the cap layer <NUM> directly contacting the sidewall of the MTJ <NUM> have different thicknesses, and more specifically the thickness the cap layer <NUM> directly contacting the top surface of the SOT layer <NUM> is less than the thickness of the cap layer <NUM> directly contacting the sidewall of the MTJ <NUM>. In this embodiment, the thickness of the cap layer <NUM> directly contacting sidewall of the MTJ <NUM> is approximately twice or more such as three or even four times the thickness of the cap layer <NUM> directly contacting the top surface of the SOT layer <NUM>.

Next, as shown in <FIG>, a photo-etching process is conducted to pattern the cap layer <NUM> and the SOT layer <NUM> by using a patterned mask (not shown) such as a patterned resist as mask to remove part of the cap layer <NUM> and part of the SOT layer <NUM> through etching process and expose the top surface of the IMD layer <NUM>, in which the sidewall of the patterned cap layer <NUM> is aligned with the sidewall of the patterned SOT layer <NUM>. It should be noted that even though none of the IMD layer <NUM> is removed during patterning of the cap layer <NUM> and the SOT layer <NUM>, according to other embodiment of the present invention, it would also be desirable to remove part of the IMD layer <NUM> when part of the cap layer <NUM> and part of the SOT layer <NUM> are removed. In this instance, the sidewall of the cap layer <NUM> would be aligned with the sidewall of the IMD layer <NUM>, which is also within the scope of the present invention.

Next, as shown in <FIG>, an atomic layer deposition (ALD) process is conducted to from an IMD layer <NUM> on the cap layer <NUM> and the IMD layer <NUM>, in which the IMD layer <NUM> could include an ultra low-k (ULK) dielectric layer including but not limited to for example porous material or silicon oxycarbide (SiOC) or carbon doped silicon oxide (SiOCH).

Next, as shown in <FIG>, a planarizing process such as chemical mechanical polishing (CMP) process or etching back process is conducted to remove part of the IMD layer <NUM> so that the top surface of the remaining IMD layer <NUM> includes a planar surface and is still higher than the top surface of the cap layer <NUM>. Next, a pattern transfer process is conducted by using a patterned mask (not shown) to remove part of the IMD layer <NUM>, part of the IMD layer <NUM>, and part of the stop layer <NUM> on the MRAM region <NUM> and logic region <NUM> to form contact holes (not shown) exposing the metal interconnections <NUM> underneath and conductive materials are deposited into the contact hole afterwards. For instance, a barrier layer selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and metal layer selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP) could be deposited into the contact holes, and a planarizing process such as CMP could be conducted to remove part of the conductive materials including the aforementioned barrier layer and metal layer to form metal interconnections <NUM> in the contact holes electrically connecting the metal interconnections <NUM>.

Next, as shown in <FIG>, a stop layer <NUM> is formed on the MRAM region <NUM> and logic region <NUM> to cover the IMD layer <NUM> and metal interconnections <NUM>, an IMD layer <NUM> is formed on the stop layer <NUM>, and one or more photo-etching process is conducted to remove part of the IMD layer <NUM>, part of the stop layer <NUM>, and part of the IMD layer <NUM> on the MRAM region <NUM> and logic region <NUM> to form contact holes (not shown). Next, conductive materials are deposited into each of the contact holes and a planarizing process such as CMP is conducted to form metal interconnections <NUM> connecting the MTJ <NUM> and metal interconnections <NUM> underneath, in which the metal interconnections <NUM> on the MRAM region <NUM> directly contact the hard mask <NUM> and metal interconnections <NUM> underneath while the metal interconnections <NUM> on the logic region <NUM> directly contacts the metal interconnections <NUM> on the lower level.

In this embodiment, the stop layers <NUM> and <NUM> could be made of same or different materials, in which the two layers <NUM>, <NUM> could all include nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or combination thereof. Similar to the metal interconnections formed previously, each of the metal interconnections <NUM> could be formed in the IMD layer <NUM> through a single damascene or dual damascene process. For instance, each of the metal interconnections <NUM> could further include a barrier layer and a metal layer, in which the barrier layer could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

Referring again to <FIG> further illustrates a structural view of a MRAM device according to an embodiment of the present invention. As shown in <FIG>, the MRAM device includes a substrate <NUM> having a MRAM region <NUM> and a logic region <NUM>, an IMD layer <NUM> disposed on the substrate <NUM>, at least two metal interconnections <NUM> disposed in the IMD layer <NUM> on the MRAM region <NUM>, a SOT layer <NUM> disposed on a directly contacting top surface of the two metal interconnections <NUM>, a MTJ <NUM> disposed on the surface of the SOT layer <NUM>, a hard mask <NUM> disposed on the MTJ <NUM>, a cap layer <NUM> disposed on the SOT layer <NUM> and the MTJ <NUM>, an IMD layer <NUM> surrounding the cap layer <NUM> and the SOT layer <NUM>, metal interconnections <NUM> disposed in the IMD layer <NUM> on the MRAM region <NUM> and the logic region <NUM>, a stop layer <NUM> disposed on the IMD layer <NUM>, an IMD layer <NUM> disposed on the stop layer <NUM>, metal interconnections <NUM> disposed in the IMD layer <NUM> on the MRAM region <NUM> to electrically connect the MTJ <NUM> and the SOT layer <NUM> and metal interconnection in the IMD layer <NUM> on the logic region <NUM> to electrically connect the metal interconnection <NUM> underneath. It should be noted that even though the bottom surface of the MTJ <NUM> is directly contacting the SOT layer <NUM> in this embodiment, according to other embodiment of the present invention, it would also be desirable to form an electrode layer between the MTJ <NUM> and the SOT layer <NUM>, in which the electrode layer could include conductive material such as but not limited to for example Ta, TaN, Pt, Cu, Au, Al, or combination thereof.

Viewing from a more detailed perspective, the cap layer <NUM> is disposed on the top surface of the hard mask <NUM>, sidewalls of the hard mask <NUM>, sidewalls of the MTJ <NUM>, and top surface of the SOT layer <NUM>, in which the top surface of the cap layer <NUM> is slightly lower than the top surface of the metal interconnections <NUM> also embedded in the IMD layer <NUM>. Moreover, the cap layer <NUM> directly contacting the top surface of the hard mask <NUM> and the cap layer <NUM> directly contacting the top surface of the SOT layer <NUM> preferably have same thickness, and the cap layer <NUM> directly contacting the top surface of the SOT layer <NUM> and the cap layer <NUM> directly contacting sidewalls of the MTJ <NUM> and hard mask <NUM> have different thicknesses and more specifically the thickness of the cap layer <NUM> directly contacting the top surface of the SOT layer <NUM> is less than the thickness of the cap layer <NUM> directly contacting sidewalls of the MTJ <NUM> and the hard mask <NUM>. Preferably, the MTJ <NUM> and the hard mask <NUM> share same widths, the sidewall of the cap layer <NUM> is aligned with sidewall of the SOT layer <NUM>, and the width of the SOT layer <NUM> is greater than twice the width of each of the MTJ <NUM> or the hard mask <NUM>. For instance, the width of the SOT layer <NUM> could be three times, four times, or even five times more than the width of the MTJ <NUM> or the hard mask <NUM>, which are all within the scope of the present invention.

Claim 1:
A method for fabricating a semiconductor device, comprising:
forming a spin orbit torque, SOT, layer (<NUM>) on a substrate (<NUM>);
forming a magnetic tunneling junction, MTJ, (<NUM>) on the SOT layer (<NUM>);
forming a cap layer (<NUM>) on the SOT layer (<NUM>) and the MTJ (<NUM>), wherein the thickness of the cap layer (<NUM>) directly contacting the top surface of the SOT layer (<NUM>) is less than the thickness of the cap layer (<NUM>) directly contacting the sidewall of the MTJ (<NUM>); and
patterning the cap layer (<NUM>) and the SOT layer (<NUM>).