Patent Description:
An image sensing device is a semiconductor element that converts optical information into an electrical signal. The image sensing device may include a CCD (Charge Coupled Device) image sensing device and a CMOS (Complementary Metal-Oxide Semiconductor) image sensing device.

A CMOS image sensor may be abbreviated as CIS (CMOS image sensor). The CIS may include a plurality of pixels disposed two-dimensionally. Each of the pixels may include, for example, a photodiode (PD). The photodiode may serve to convert incident light thereto into an electrical signal.

Recently, with the development of the computer industry and the communications industry, demand for miniaturized image sensing devices having improved performance is increasing in various fields such as digital cameras, camcorders, smartphones, game devices, security cameras, medical micro cameras, and robots. Accordingly, research on highly scaled and highly integrated semiconductor elements in the image sensing device is in progress. Patterns of the semiconductor elements may have fine widths and may be spaced apart from each other by a fine pitch.

<CIT> discloses an image sensor comprising a substrate comprising a pixel area, a first side, and a second side opposite to the first side, wherein light is incident to the second side and the pixel area comprises a plurality of pixels; a pixel separation structure arranged in the substrate to separate the pixels from each other and comprising a conductive layer therein; and a voltage-applying wire layer spaced apart from the conductive layer and arranged on the substrate to surround at least a portion of an outer portion of the pixel area, wherein the voltage-applying wire layer is electrically connected to the conductive layer through at least one contact.

<CIT> discloses a color filter is disposed on a substrate. An organic photodiode is disposed on the color filter. The organic photodiode includes an electrode insulating layer having a recess region on the substrate, a first electrode on the color filter, the first electrode filling the recess region of the electrode insulating layer, a second electrode on the first electrode, and an organic photoelectric conversion layer interposed between the first electrode and the second electrode. The first electrode includes a seam extending at a first angle from a side surface of the recess region of the electrode insulating layer.

An aspect of the present disclosure relates to an image sensor with improved performance and/or reliability.

Another aspect of the present disclosure relates to a method for manufacturing an image sensor with improved performance and/or reliability.

The invention provides an image sensor and a method of manufacturing an image sensor as set out in the claims.

The above and other aspects and features of embodiments the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings, in which:.

Hereinafter, the present disclosure will be described in more detail with reference to the accompanying drawings according to some embodiments of the present disclosure. Referring to <FIG>, image sensors according to some embodiments will be described.

<FIG> is an example block diagram of an image sensor according to some embodiments.

Referring to <FIG>, the image sensor according to some embodiments may include a first semiconductor chip <NUM> and a second semiconductor chip <NUM>. The first semiconductor chip <NUM> and the second semiconductor chip <NUM> may be disposed to overlap each other in a plan view. The first semiconductor chip <NUM> and the second semiconductor chip <NUM> may be stacked in a vertical direction.

Alternatively, the image sensor according to some embodiments may further include a third semiconductor chip. In one example, the third semiconductor chip may include a memory cell array. However, inventive concepts of the present disclosure are not limited thereto. The first to third semiconductor chips may be sequentially stacked in the vertical direction.

The first semiconductor chip <NUM> may include a pixel array <NUM>. The second semiconductor chip <NUM> may include a logic circuit <NUM> and ADC (Analog Digital Converter) <NUM>. The pixel array <NUM> may generate charges proportional to an amount of light entering the pixel array <NUM>. Further, the pixel array <NUM> may convert an optical signal into an electrical signal, that is, an analog signal under control of the logic circuit <NUM>. The pixel array <NUM> may output the analog signal to the ADC <NUM>. The ADC <NUM> may convert an analog signal to a digital signal. The ADC <NUM> may provide data based on the digital signal.

Although not shown, the image sensor according to some embodiments may further include a memory cell array in the second semiconductor chip <NUM>. The memory cell array may store therein the data based on the digital signal.

The data may be image data generated on a frame basis. The number of bits of the data may be determined based on a resolution of the ADC <NUM>. The number of bits of the data may be determined based on HDR (High Dynamic Range) supported by the image sensor. Further, the bits of the data may further include at least one extension bit indicating a data generation position, information about the data, and the like.

In some embodiments, the second semiconductor chip <NUM> may further include a built-in processor such as an ISP (image signal processor), a DSP (digital signal processor), or the like that processes the data output from the pixel array <NUM>. The processor may lower noise of an image data, correct an image, or perform subsequent operations related to the image output from the pixel array <NUM>.

<FIG> is a block diagram to illustrate the pixel array, the logic circuit, and the ADC of <FIG>.

Referring to <FIG>, the pixel array <NUM> may be implemented in the first semiconductor chip <NUM>. The logic circuit (<NUM> in <FIG>) may be implemented in the second semiconductor chip <NUM>.

The pixel array <NUM> may convert incident light thereto into an electrical signal. The pixel array <NUM> may include unit pixel regions arranged in a matrix form along a row direction and a column direction. The pixel array <NUM> may operate under the control of the logic circuit <NUM>. Specifically, the logic circuit <NUM> may control a plurality of transistors included in the pixel array <NUM>.

The logic circuit <NUM> may efficiently receive the data from the pixel array <NUM> and generate an image frame. For example, the logic circuit <NUM> may use a global shutter scheme in which all unit pixel regions are simultaneously sensed, a flutter shutter scheme that adjusts an exposure time for which all unit pixel regions are simultaneously sensed, and a rolling shutter or coded rolling shutter scheme that controls the unit pixel regions on a row basis. The logic circuit <NUM> may include a row driver <NUM>, a timing controller, and the ADC <NUM>.

The row driver <NUM> may control the pixel array <NUM> on a row basis under control of the timing controller <NUM>. The row driver <NUM> may select at least one row from among rows of the pixel array <NUM> based on a row address. The row driver <NUM> may decode the row address and may be connected to a select transistor AX, a reset transistor RX, and a source follower transistor SX. The pixel array <NUM> may operate based on a plurality of drive signals such as a pixel select signal, a reset signal and a charge transfer signal received from the row driver <NUM>.

The ADC <NUM> may be connected to the pixel array <NUM> through column lines COL. The ADC <NUM> may convert the analog signals received from the pixel array <NUM> through the column lines COL into the digital signals. The number of the ADCs <NUM> may be determined based on the number of the column lines COL and the number of unit pixel regions arranged along one row. The number of the ADCs <NUM> may be at least one. However, inventive concepts of the present disclosure are not limited thereto.

For example, the ADC <NUM> may include a reference signal generator REF, a comparator CMP, a counter CNT, and a buffer BUF. The reference signal generator REF may generate a ramp signal having a specific slope and provide the ramp signal as a reference signal of the comparator. The comparator CMP may compare the analog signal and the ramp signal of the reference signal generator REF with each other, and may output comparison signals having respective transition times based on valid signal components. The counter CNT may perform a counting operation to generate a counting signal and may provide the counting signal to the buffer BUF. The buffer BUF may include latch circuits connected to the column lines COL, respectively, and may latch the counting signal output from the counter CNT in response to the transition of the comparison signal on a column basis, and may output the latched counting signal as the data.

In some embodiments, the logic circuit <NUM> may further include correlated double sampling (CDS) circuits which obtain a difference between a reference voltage representing a reset state of each of the unit pixel regions and an output voltage representing a signal component corresponding to the incident light to perform correlation double the sampling, and output an analog sampling signal corresponding to a valid signal component. The correlated double sampling circuits may be connected to the column lines COL.

The timing controller <NUM> may control an operation timing of each of the row driver <NUM> and the ADC <NUM>. The timing controller <NUM> may provide a timing signal and a control signal to each of the row driver <NUM> and the ADC <NUM>. More specifically, the timing controller <NUM> may control the ADC <NUM>. The ADC <NUM> may provide the data to the logic circuit <NUM> under control of the timing controller <NUM>. Further, the timing controller <NUM> may further include circuits that provide a request, a command, or an address to the logic circuit <NUM> so that the data of the ADC <NUM> is stored in the memory cell array.

<FIG> is a circuit diagram to illustrate a unit pixel region of a pixel array of <FIG>. For reference, <FIG> may be based on a 4T structure of each of the unit pixel regions constituting the pixel array.

Referring to <FIG>, the pixel array may include photoelectric conversion layers PD1 and PD2, transfer transistors TX, a floating diffusion area FD, a reset transistor RX, a source follower transistor SX and a select transistor AX.

The photoelectric conversion layers PD1 and PD2 may generate electric charges in proportion to an amount of light incident thereto from an outside. Each of the photoelectric conversion layers PD1 and PD2 may be embodied as a photodiode including an n-type impurity area and a p-type impurity area. Each of the photoelectric conversion layers PD1 and PD2 may be coupled to each transfer transistor TX that transmits charges generated and accumulated in each of the photoelectric conversion layers PD1 and PD2 to the floating diffusion area FD. The floating diffusion area FD may refer to an area that converts the charges into a voltage. Since the floating diffusion area FD has parasitic capacitance, the charges may be stored in the floating diffusion area FD in a cumulative manner.

One end of each transfer transistor TX may be connected to each of the photoelectric conversion layers PD1 and PD2, while the other end of each transfer transistor TX may be connected to the floating diffusion area FD. The transfer transistor TX may be embodied as a transistor operating based on a desired and/or alternatively predefined bias, for example, a transfer signal. The transfer signal may be applied thereto through each of transfer gates TG1 and TG2. That is, each transfer transistor TX may transmit the charges generated from each of the photoelectric conversion layers PD1 and PD2 to the floating diffusion area FD based on each of the transfer signals.

The source follower transistor SX may amplify change in an electrical potential of the floating diffusion area FD upon receiving the charges from the photoelectric conversion layers PD1 and PD2, and output the amplified change to an output line VOUT. When the source follower transistor SX is turned on, a desired and/or alternatively predefined electrical potential, for example, a power voltage VDD provided to a drain of the source follower transistor SX may be delivered to a drain area of the select transistor AX. A source follower gate SF of the source follower transistor SX may be connected to the floating diffusion area FD.

The select transistor AX may select the unit pixel region to be read on a row basis. The select transistor AX may be embodied as a transistor driven by a select line that applies a desired and/or alternatively predefined bias, for example, a row select signal. The row select signal may be applied thereto through a select gate SEL.

The reset transistor RX may periodically reset the floating diffusion area FD. The reset transistor RX may be embodied as a transistor driven by a reset line that applies a desired and/or alternatively predefined bias, for example, a reset signal. The reset signal may be applied thereto through a reset gate RG. When the reset transistor RX is turned on based on the reset signal, a desired and/or alternatively predefined electrical potential, for example, the power voltage VDD provided to a drain of the reset transistor RX may be transferred to the floating diffusion area FD.

In <FIG>, a structure in which the photoelectric conversion layers PD1 and PD2 electrically share one floating diffusion area FD is illustrated. However, inventive concepts of the present disclosure are not limited thereto. For example, one unit pixel region may include one of the photoelectric conversion layers PD1 and PD2, the floating diffusion area FD and the four transistors TX, RX, AX, and SX, and the reset transistor RX, the source follower transistor SX, or the select transistor AX may be shared by neighboring unit pixel regions. Further, the number of photoelectric conversion layers PD1 and PD2 electrically sharing one floating diffusion area FD is not limited thereto. Accordingly, integration of the image sensor according to some embodiments may be improved.

Unlike the example as shown, as a size of the unit pixel region becomes smaller, the photoelectric conversion layer PD and the transfer transistor TX may be formed in one semiconductor chip, while the reset transistor RX, the source follower transistor SX and the select transistor AX may be formed in the other semiconductor chip. The semiconductor chips may be aligned with each other to constitute the unit pixel regions.

<FIG> is an example plan view of an image sensor according to some embodiments. <FIG> is a cross-sectional view taken along a line A-A of <FIG>.

Referring to <FIG> and <FIG>, the image sensor according to some embodiments may include the first semiconductor chip <NUM> and the second semiconductor chip <NUM>. The first semiconductor chip <NUM> may act as a sensor chip, while the second semiconductor chip <NUM> may act as a logic chip.

The first semiconductor chip <NUM> may include a light-receiving area APS, a light-blocking area OB, and a pad area PAD. In the light-receiving area APS, and the light-blocking area OB, a plurality of unit pixel regions PX may be arranged two-dimensionally, for example, in a matrix form. The unit pixel regions PX may be arranged in a matrix form in a plane across which a first direction D1 and a second direction D2 extend. The first direction D1 and the second direction D2 may intersect each other. The first direction D1 and the second direction D2 may be substantially perpendicular to each other. A third direction D3 may be substantially perpendicular to the first direction D1 and the second direction D2.

In the light-receiving area APS, active pixels that receive light and generate an active signal may be arranged. Optical black pixels generating an optical black signal by blocking light may be arranged in the light-blocking area OB. The light-blocking area OB may be disposed, for example, along a perimeter of the light-receiving area APS. However, this is only an example. In some embodiments, dummy unit pixel regions DPX may be arranged in the light-blocking area OB. The dummy unit pixel region DPX may refer to an area of a pixel that does not generate the active signal.

The pad area PAD may be disposed around the light-blocking area OB. The pad area PAD may be disposed adj acent to an edge of the image sensor according to some embodiments. However, this is only an example. The pad area PAD may be configured to be connected to an external device and the like to transmit/receive an electrical signal between the image sensor according to some embodiments and the external device. For example, a third pad pattern <NUM> may be disposed on a first substrate <NUM> of the pad area PAD. The third pad pattern <NUM> may be connected to the external device, etc..

The image sensor according to some embodiments may include the first substrate <NUM>, a pixel defining pattern <NUM>, a surface insulating film <NUM>, a first color filter <NUM>, a grid pattern <NUM>, a micro lens <NUM>, a second substrate <NUM>, a first pad pattern <NUM>, a second pad pattern <NUM>, and the third pad pattern <NUM>.

The first substrate <NUM> may be embodied as a semiconductor substrate. For example, the first substrate <NUM> may be made of bulk silicon or an SOI (silicon-on-insulator). The first substrate <NUM> may be a silicon substrate, or may be made of a material other than silicon, for example, silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide. Alternatively, the first substrate <NUM> may include a base substrate and an epitaxial layer formed on the base substrate.

The first substrate <NUM> includes a first surface 110a and a second surface 110b opposite to each other. In some embodiments, the second surface 110b of the first substrate <NUM> may be a light receiving surface on which light is incident. That is, the image sensor according to some embodiments may be embodied as a backside-illuminated (BSI) image sensor.

A plurality of unit pixel regions PX are be formed in the first substrate <NUM> and may be formed in the light-receiving area APS and the light-blocking area OB. Each unit pixel region PX includes a photoelectric conversion layer PD. A dummy unit pixel region DPX that does not include a photoelectric conversion layer PD may be included in the first substrate <NUM> and in the light-blocking area OB. However, inventive concepts of the present disclosure are not limited thereto. A signal generated from the dummy unit pixel region DPX may be used as information to remove process noise afterwards.

Each unit pixel region PX includes the photoelectric conversion layer PD, and may include the floating diffusion area FD and the transfer transistor TX. The photoelectric conversion layer PD may be formed in the first substrate <NUM> and in each of the light-receiving area APS and the light-blocking area OB. The photoelectric conversion layer PD may generate an electric charge in proportion to the amount of light incident thereto from the outside. The photoelectric conversion layer PD may transmit the generated and accumulated charges therein to the floating diffusion area FD.

The floating diffusion area FD may be formed in the first substrate <NUM> and in each of the light-receiving area APS and the light-blocking area OB. The floating diffusion area FD may be formed in the first surface 110a of the first substrate <NUM>. The charge transmitted to the floating diffusion area FD may be applied to the source follower gate SF in <FIG>.

The transfer transistor TX may be embedded in the first substrate <NUM>. One end of the transfer transistor TX may be connected to the photoelectric conversion layer PD, while the other end of the transfer transistor TX may be connected to the floating diffusion area FD. The transfer transistor TX may transmit the charges generated from the photoelectric conversion layer PD to the floating diffusion area FD.

The transfer transistor TX may include a transfer gate, a gate insulating film, and a gate spacer. The transfer gate may include a portion embedded in the first substrate <NUM>. The gate insulating film may be disposed between the transfer gate and the first substrate <NUM>. The gate spacer may be disposed on each of both opposing side walls of the transfer gate.

The pixel defining pattern <NUM> is formed in the first substrate <NUM>. The pixel defining pattern <NUM> may be formed by filling an insulating material in a deep trench formed by patterning the first substrate <NUM>. The pixel defining pattern <NUM> may extend through the first substrate <NUM> in the third direction D3. For example, the pixel defining pattern <NUM> may extend from the first surface 110a to the second surface 110b. The pixel defining pattern <NUM> may be embodied as FDTI (front deep trench isolation).

The pixel defining pattern <NUM> defines each of the plurality of unit pixel regions PX and may define the dummy unit pixel region DPX. The pixel defining pattern <NUM> may be arranged in a grid manner in a plan view to space the plurality of unit pixel regions PX and the dummy unit pixel region DPX from each other.

In some embodiments, an element isolation pattern <NUM> may be provided. The element isolation pattern <NUM> may be disposed within the first substrate <NUM>. For example, the element isolation pattern <NUM> may be received in a trench in which a portion of the first substrate <NUM> is recessed. The trench may be recessed from the first surface 110a of the first substrate <NUM>. The element isolation pattern <NUM> may be embodied as a shallow trench isolation (STI) film. The element isolation pattern <NUM> may define each of active areas (ACT in <FIG>).

A width in the second direction D2 of the element isolation pattern <NUM> may gradually decrease as the pattern <NUM> extends from the first surface 110a of the first substrate <NUM> toward the second surface 110b thereof. The element isolation pattern <NUM> may overlap the pixel defining pattern <NUM> in the second direction D2 or the first direction D1. The pixel defining pattern <NUM> may extend through the element isolation pattern <NUM> in the third direction D3. The element isolation pattern <NUM> may include an insulating material. The element isolation pattern <NUM> may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride.

The image sensor according to some embodiments may further include first line insulating films <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. The first line insulating films <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may be formed on the first surface 110a of the first substrate <NUM>. For example, the first line insulating films <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may cover the first surface 110a of the first substrate <NUM>. The first substrate <NUM> and the first line insulating films <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may constitute the first semiconductor chip <NUM>. In <FIG>, it is illustrated that the number of the first line insulating films <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> is five. However, the present disclosure is not limited thereto. The number of the first line insulating films <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are only an example.

Each of the first line insulating films <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant (low-k) material having a lower dielectric constant than that of silicon oxide. However, inventive concepts of the present disclosure are not thereto.

A plurality of first contacts <NUM> and <NUM> and a plurality of first line patterns <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may be disposed in the first line insulating films <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. The plurality of first contacts <NUM> and <NUM> may electrically connect the floating diffusion area FD to the plurality of first line patterns <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. Some of the plurality of first line patterns <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may be connected to a first connective structure <NUM>. However, inventive concepts of the present disclosure are not thereto.

Each of the first contacts <NUM> and <NUM> and the first line patterns <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. However, inventive concepts of the present disclosure are not thereto.

The second substrate <NUM> may be made of bulk silicon or SOI (silicon-on-insulator). The second substrate <NUM> may be embodied as a silicon substrate, or may be made of a material other than silicon, for example, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide. Alternatively, the second substrate <NUM> may include a base substrate and an epitaxial layer formed on the base substrate.

The second substrate <NUM> may include an upper surface and a bottom surface. The upper surface of the second substrate <NUM> may be a face facing the first semiconductor chip <NUM>. The bottom surface of the second substrate <NUM> may be a face opposite to the upper surface of the second substrate <NUM>.

A plurality of transistors TR may be formed on the upper surface of the second substrate <NUM>. The transistors TR may be, for example, logic circuits. The transistors TR may control the transfer transistor TX, the reset transistor (RX of <FIG>), the select transistor (AX of <FIG>), and the source follower transistor (SX of <FIG>).

A second line insulating film <NUM> may be formed on the second substrate <NUM>. For example, the second line insulating film <NUM> may cover the upper surface of the second substrate <NUM>. The second substrate <NUM> and the second line insulating film <NUM> may constitute the second semiconductor chip <NUM>. The second line insulating film <NUM> may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant (low-k) material having a lower dielectric constant than that of silicon oxide. However, inventive concepts of the present disclosure are not thereto.

A plurality of second line patterns <NUM> and <NUM> may be disposed in the second line insulating film <NUM>. The plurality of second line patterns <NUM> and <NUM> may be connected to the transistors TR, respectively, and may be connected to the floating diffusion area FD of the first semiconductor chip <NUM>. Some of the plurality of second line patterns <NUM> and <NUM> may be connected to the first connective structure <NUM>. Further, the other of the plurality of second line patterns <NUM> and <NUM> may be connected to a third connective structure <NUM>. However, inventive concepts are not limited thereto.

Each of the second line patterns <NUM> and <NUM> may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. However, inventive concepts of the present disclosure are not thereto.

The surface insulating film <NUM> may be formed on the second surface 110b of the first substrate <NUM>. The surface insulating film <NUM> may extend along the second surface 110b of the first substrate <NUM>. In some embodiments, at least a portion of the surface insulating film <NUM> may contact the pixel defining pattern <NUM>.

The surface insulating film <NUM> may include an insulating material. For example, the surface insulating film <NUM> may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and a combination thereof. However, inventive concepts of the present disclosure are not thereto.

The surface insulating film <NUM> functions as an anti-reflective film to limit and/or prevent reflection of light incident on the first substrate <NUM>, thereby improving light reception of the photoelectric conversion layer PD. Further, the surface insulating film <NUM> functions as a planarization film, so that the first color filter <NUM> and the micro lens <NUM> which will be described later may be formed at a uniform vertical level.

The first color filter <NUM> may be formed on the surface insulating film <NUM> and in the light-receiving area APS. In some embodiments, the first color filter <NUM> may be disposed to correspond to each unit pixel region PX. For example, the plurality of first color filters <NUM> may be arranged two-dimensionally, for example, in a matrix form.

The first color filter <NUM> may include various color filters based on the unit pixel region PX. For example, the first color filter <NUM> may be arranged in a Bayer pattern including a red color filter, a green color filter, and a blue color filter. However, this is only an example. The first color filter <NUM> may include a yellow filter, a magenta filter, and a cyan filter, and may further include a white filter.

The grid pattern <NUM> may be formed on the surface insulating film <NUM>. The grid pattern <NUM> may be formed in a grid shape in the plan view and may be interposed between the plurality of first color filters <NUM>.

The grid pattern <NUM> may include a low refractive index material having a refractive index lower than that of silicon (Si). For example, the grid pattern <NUM> may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and a combination thereof. However, inventive concepts of the present disclosure are not thereto. The grid pattern <NUM> including the low refractive index material may refract or reflect the light incident obliquely to the image sensor to improve the quality of the image sensor.

In some embodiments, a first protective film <NUM> may be formed on the surface insulating film <NUM> and the grid pattern <NUM>. The first protective film <NUM> may be interposed between the surface insulating film <NUM> and the first color filter <NUM> and between the grid pattern <NUM> and the first color filter <NUM>. For example, the first protective film <NUM> may extend along a profile of an upper surface of the surface insulating film <NUM> and a side face and an upper surface of the grid pattern <NUM>.

The first protective film <NUM> may include, for example, aluminum oxide. However, inventive concepts of the present disclosure are not thereto. The first protective film <NUM> may limit and/or prevent damage to the surface insulating film <NUM> and the grid pattern <NUM>.

The micro lens <NUM> may be formed on the first color filter <NUM>. The micro lens <NUM> is disposed to correspond to each unit pixel region PX. For example, the micro lenses <NUM> may be arranged two-dimensionally, for example, in a matrix form in a plan view.

The micro lens <NUM> has a convex shape and may have a desired and/or alternatively predefined radius of curvature. Accordingly, the micro lens <NUM> may condense the light to be incident on the photoelectric conversion layer PD. The micro lens <NUM> may include, for example, a light-transmissive resin. However, inventive concepts of the present disclosure are not limited thereto.

In some embodiments, a second protective film <NUM> may be formed on the micro lens <NUM>. The second protective film <NUM> may extend along a surface of the micro lens <NUM>. The second protective film <NUM> may include, for example, an inorganic oxide film. For example, the second protective film <NUM> may include at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and combinations thereof. However, inventive concepts of the present disclosure are not limited thereto. In some embodiments, the second protective film <NUM> may include a low-temperature oxide (LTO).

The second protective film <NUM> may protect the micro lens <NUM> from the outside. For example, the second protective film <NUM> may include an inorganic oxide film to protect the micro lens <NUM> including an organic material. Further, the second protective film <NUM> may improve light condensing ability of the micro lens <NUM>. For example, the second protective film <NUM> may fill a space between the micro lenses <NUM> to reduce reflection, refraction, and scattering of incident light reaching the space between the micro lenses <NUM>.

The image sensor according to some embodiments may further include the first connective structure <NUM>, a second connective structure <NUM>, and the third connective structure <NUM>.

The first connective structure <NUM> may be formed in the light-blocking area OB. The first connective structure <NUM> may limit and/or prevent light from being incident to the light-blocking area OB. The first connective structure <NUM> may be formed on the surface insulating film <NUM> and in the light-blocking area OB. The first connective structure <NUM> may be in contact with the pixel defining pattern <NUM>. The first connective structure <NUM> may be in contact with a first defining pattern (<NUM> in <FIG>) of the pixel defining pattern <NUM>.

For example, a fourth trench t4 exposing the first defining pattern <NUM> may be formed in the first substrate <NUM> and the surface insulating film <NUM> and in the light-blocking area OB. The first connective structure <NUM> may be formed in the fourth trench t4 and may contact the first defining pattern <NUM> in the light-blocking area OB. The first connective structure <NUM> may extend along a profile of a sidewall and a bottom surface of the fourth trench t4.

The first connective structure <NUM> may be electrically connected to the first defining pattern <NUM>. For example, the first connective structure <NUM> may be electrically connected to a first conductive layer (121F of <FIG>) of the first defining pattern <NUM>. The first connective structure <NUM> may include, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film that are sequentially stacked.

In some embodiments, on the first connective structure <NUM>, the first pad pattern <NUM> may be formed. The first pad pattern <NUM> may fill a remaining portion of the fourth trench t4 which the first connective structure <NUM> does not fill. A first voltage may be applied to the first defining pattern <NUM> of the pixel defining pattern <NUM> through the first pad pattern <NUM>. For example, the first voltage may be applied to the first conductive layer (121F of <FIG>) via the first pad pattern <NUM> and the first connective structure <NUM> including the conductive material. The first voltage may be a negative voltage. Accordingly, charges generated due to ESD, etc. may be discharged to the first pad pattern <NUM> through the first defining pattern <NUM>, such that ESD bruising defect may be effectively limited and/or prevented.

The first pad pattern <NUM> may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. However, inventive concepts of the present disclosure are not limited thereto.

The second connective structure <NUM> may be formed in the light-blocking area OB. The second connective structure <NUM> may limit and/or prevent light from being incident to the light-blocking area OB. The second connective structure <NUM> may be formed on the surface insulating film <NUM> and in the light-blocking area OB. The second connective structure <NUM> may be in contact with the pixel defining pattern <NUM>. The second connective structure <NUM> may be in contact with a second defining pattern (<NUM> in <FIG>) of the pixel defining pattern <NUM>. The second connective structure <NUM> may be in contact with a second conductive layer of the pixel defining pattern <NUM>. The second defining pattern may refer to the second conductive layer.

For example, a third trench t3 exposing the second defining pattern <NUM> may be formed in the first substrate <NUM> and the surface insulating film <NUM> and in the light-blocking area OB. The second connective structure <NUM> may be formed in the third trench t3 so as to contact the second defining pattern <NUM> in the light-blocking area OB. The second connective structure <NUM> may extend along a profile of a sidewall and a bottom surface of the third trench t3.

The second connective structure <NUM> may be electrically connected to the second defining pattern <NUM>. For example, the second connective structure <NUM> may be electrically connected to the second conductive layer of the second defining pattern <NUM>. The second connective structure <NUM> may include, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film that are sequentially stacked.

In some embodiments, on the second connective structure <NUM>, the second pad pattern <NUM> may be formed. The second pad pattern <NUM> may fill a remaining portion of the third trench t3 which the second connective structure <NUM> does not fill. A second voltage may be applied to the second defining pattern <NUM> of the pixel defining pattern <NUM> through the second pad pattern <NUM> and the second connective structure <NUM> including the conductive material. For example, the second voltage may be applied to the second conductive layer <NUM> through the second pad pattern <NUM> and the second connective structure <NUM>. The second voltage may be a well bias voltage.

The second pad pattern <NUM> may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. However, inventive concepts of the present disclosure are not limited thereto.

In some embodiments, a fifth trench t5 may be formed in the first substrate <NUM> and in the light-blocking area OB. The fifth trench t5 may expose a portion of each of the first line patterns <NUM> and <NUM> of the first semiconductor chip <NUM>. The fifth trench t5 may expose a portion of the second line pattern <NUM> of the second semiconductor chip <NUM>. The first connective structure <NUM> may be formed in the fifth trench t5 so as to connect the first line patterns <NUM> and <NUM> to the second line pattern <NUM>. The first connective structure <NUM> may extend along a sidewall and a bottom surface of the fifth trench t5.

In some embodiments, on the first connective structure <NUM>, a first filling insulating film <NUM> may be formed. The first filling insulating film <NUM> may fill a remaining portion of the fifth trench t5 which the first connective structure <NUM> does not fill. The first filling insulating film <NUM> may include, for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and a combination thereof. However, inventive concepts of the present disclosure are not limited thereto.

In some embodiments, a first capping pattern <NUM> may be formed on the first filling insulating film <NUM>. The first capping pattern <NUM> may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and silicon oxynitride), and a high dielectric material (e.g., hafnium oxide, and aluminum oxide). The first capping pattern <NUM> may include the same material as that of a capping film 121C. However, inventive concepts of the present disclosure are not limited thereto.

In some embodiments, a second color filter 170C may be formed on the first connective structure <NUM> and the second connective structure <NUM>. For example, the second color filter 170C may be formed to cover a portion of the first protective film <NUM> in the light-blocking area OB. The second color filter 170C may include, for example, a blue color filter. However, inventive concepts of the present disclosure are not limited thereto.

In some embodiments, a third protective film <NUM> may be formed on the second color filter 170C. For example, the third protective film <NUM> may be formed to cover a portion of the first protective film <NUM> in the light-blocking area OB. In some embodiments, the second protective film <NUM> may extend along a surface of the third protective film <NUM>. The third protective film <NUM> may include, for example, a light-transmissive resin. However, inventive concepts of the present disclosure are not limited thereto. In some embodiments, the third protective film <NUM> may contain the same material as that of the micro lens <NUM>.

The third connective structure <NUM> may be formed in the pad area PAD. The third connective structure <NUM> may be formed on the surface insulating film <NUM> and in the pad area PAD.

In some embodiments, a sixth trench t6 may be formed in the first substrate <NUM> and in the pad area PAD. The third connective structure <NUM> may fill a portion of the sixth trench t6. The third connective structure <NUM> may be formed along a sidewall and a bottom surface of the sixth trench t6.

A seventh trench t7 exposing the second line pattern <NUM> may be formed in the second semiconductor chip <NUM> and in the pad area PAD. The third connective structure <NUM> may fill a portion of seventh trench t7. The third connective structure <NUM> may be formed along a sidewall and a bottom surface of the seventh trench t7.

The third connective structure <NUM> may be formed in the seventh trench t7 so as to contact a portion of the second line pattern <NUM>. The third connective structure <NUM> may electrically connect a portion of the second line pattern <NUM> to the third pad pattern <NUM>. The third connective structure <NUM> may include, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film that are sequentially stacked.

On the third connective structure <NUM>, the third pad pattern <NUM> may be formed. The third pad pattern <NUM> may fill a remaining portion of the sixth trench t6 which the third connective structure <NUM> does not fill. The third pad pattern <NUM> may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. However, inventive concepts of the present disclosure are not limited thereto.

In some embodiments, a portion of the third pad pattern <NUM> may be exposed. For example, an exposure opening partially exposing the third pad pattern <NUM> may be formed. Accordingly, the third pad pattern <NUM> may be configured to be connected to an external device and the like so as to transmit/receive an electrical signal between the image sensor according to some embodiments and the external device.

A second filling insulating film <NUM> may be formed on the third connective structure <NUM>. The second filling insulating film <NUM> may fill a remaining portion of the seventh trench t7 which the third connective structure <NUM> does not fill. The second filling insulating film <NUM> may include, for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and a combination thereof. However, inventive concepts of the present disclosure are not limited thereto.

In some embodiments, a second capping pattern <NUM> may be formed on the second filling insulating film <NUM>. The second capping pattern <NUM> may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and silicon oxynitride) and a high dielectric material (e.g., hafnium oxide, and aluminum oxide). The second capping pattern <NUM> may include the same material as that of the capping film 121C. However, inventive concepts of the present disclosure are not limited thereto.

In some embodiments, a fourth protective film <NUM> may be formed on the third connective structure <NUM> and in the pad area PAD. For example, the fourth protective film <NUM> may be formed to cover a portion of the first protective film <NUM> in the pad area PAD. In some embodiments, the second protective film <NUM> may extend along a surface of the fourth protective film <NUM>. The fourth protective film <NUM> may include, for example, a light-transmissive resin. However, inventive concepts of the present disclosure are not limited thereto. In some embodiments, the fourth protective film <NUM> may include the same material as that of the micro lens <NUM>.

<FIG> and <FIG> are enlarged views of a P area of <FIG>. <FIG> is a cross-sectional view taken along a line B-B of <FIG>. Hereinafter, with reference to <FIG>, the image sensor according to some embodiments will be described in more detail.

Referring to <FIG>, the element isolation pattern <NUM> may define each of the active areas ACT.

In the plan view, each of the active areas ACT may have a line shape extending in the second direction D2. However, the shape of each of the active areas ACT is not limited to the shape shown in <FIG> and <FIG>, and may be variously modified. The floating diffusion area FD, the transfer transistor TX, and the select transistor AX, the reset transistor RX, and the source follower transistor SX may be disposed on the active areas ACT. The transfer transistor TX may include the transfer gate TG.

In <FIG>, the floating diffusion area FD may be disposed on one side of the transfer transistor TX. The floating diffusion area FD may have a conductivity type opposite to that of the first substrate <NUM>. For example, an n-type impurity may be doped in the floating diffusion area FD. In <FIG>, the floating diffusion area FD may surround the transfer gate TG of the transfer transistor TX.

In some embodiments, a portion of the unit pixel region PX may contain the select transistor AX, and the source follower transistor SX. The select transistor AX may include the select gate SEL, and the source follower transistor SX may include the source follower gate SF. Another portion of the unit pixel region PX may contain the reset transistor RX. The reset transistor RX may include the reset gate RG. However, inventive concepts of the present disclosure are not limited thereto, and the arrangement and the number of the transistors included in the unit pixel region PX may be modified.

The pixel defining pattern <NUM> defines each of the unit pixel regions PX. For example, the pixel defining pattern <NUM> may be disposed between adjacent unit pixel regions PX. In the plan view, the pixel defining pattern <NUM> may have a grid structure. In the plan view, the pixel defining pattern <NUM> may surround an entirety of each of the unit pixel regions PX. The pixel defining pattern <NUM> may be arranged in a grid structure extending in the first direction D1 and the second direction D2.

In a cross-sectional view, the pixel defining pattern <NUM> may extend through the first substrate <NUM> in the third direction D3. The pixel defining pattern <NUM> may extend from the first surface 110a of the first substrate <NUM> to the second surface 110b thereof. The pixel defining pattern <NUM> may be embodied as a deep trench isolation (DTI) film. A width in the second direction D2 of the pixel defining pattern <NUM> may gradually decrease as the pattern <NUM> extends from the first surface 110a of the first substrate <NUM> toward the second surface 110b thereof. However, inventive concepts of the present disclosure are not limited thereto.

The pixel defining pattern <NUM> includes the first defining pattern <NUM> and the second defining pattern <NUM>. The first defining pattern <NUM> is disposed in the first trench t1. The second defining pattern <NUM> is disposed in the second trench t2. The first trench t1 and the second trench t3 may be aligned with each other in the third direction D3. That is, the first defining pattern <NUM> and the second defining pattern <NUM> may be aligned with each other in the third direction D3.

The first defining pattern <NUM> includes a liner film <NUM>, the first conductive layer 121F, and may include the capping film 121C. The liner film <NUM> is disposed along and on a sidewall and a bottom surface of the first trench t1. In the present disclosure, the bottom surface of the first trench t1 is defined as a face facing the first surface 110a of the first substrate <NUM>. The first conductive layer 121F is disposed on the liner film <NUM>. The capping layer 121C may be disposed on the first conductive layer 121F.

The liner film <NUM> may include an oxide film having a lower refractive index than that of the first substrate <NUM>. For example, the liner film <NUM> may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and a combination thereof. However, inventive concepts of the present disclosure are not limited thereto. The liner film <NUM> which has a lower refractive index than that of the first substrate <NUM> may refract or reflect light incident obliquely to the photoelectric conversion layer PD. Further, the liner film <NUM> may limit and/or prevent photoelectric charges generated in a specific unit pixel region PX due to the incident light from random drifting and moving to a unit pixel region PX adjacent thereto. That is, the liner film <NUM> may improve the light reception of the photoelectric conversion layer PD to improve the quality of the image sensor according to some embodiments.

In some embodiments, the first conductive layer 121F may include a conductive material. For example, the first conductive layer 121F may include, but is not limited to, polysilicon (poly Si). In some embodiments, a negative voltage may be applied to the first conductive layer 121F including the conductive material. Accordingly, ESD (electrostatic discharge) bruising defect of the image sensor according to some embodiments may be effectively limited and/or prevented. In this regard, the ESD bruising defect refers to a phenomenon in which electric charges generated by ESD etc. accumulate on a surface (for example, the second surface 110b) of the substrate, resulting in bruising-like stains on the image.

In some embodiments, the capping film 121C may include an insulating material. For example, the capping layer 121C may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and silicon oxynitride) and a high dielectric material (e.g., hafnium oxide, and aluminum oxide). The capping film 121C may include the same material as that of each of the first capping pattern <NUM> and the second capping pattern <NUM>. However, inventive concepts of the present disclosure are not limited thereto.

The second defining pattern <NUM> is disposed in the second trench t2. The second defining pattern <NUM> includes the second conductive layer. In one example, the second defining pattern <NUM> may be composed of the second conductive layer. The second defining pattern <NUM> may be in contact with the first substrate <NUM>. The second conductive layer <NUM> may be in contact with the first substrate <NUM>. Hereinafter, the second defining pattern <NUM> is referred to as the second conductive layer <NUM>. In some embodiments, the second conductive layer <NUM> may be a single layer. However, inventive concepts of the present disclosure are not limited thereto. In some embodiments, an upper surface <NUM> of the second conductive layer <NUM> may be coplanar with the second surface 110b of the first substrate <NUM>.

The second conductive layer <NUM> may include a conductive material. The second conductive layer <NUM> may include, for example, polysilicon (poly Si) or silicon doped with arsenic (As), phosphorus (P), or carbon (C). However, inventive concepts of the present disclosure are not limited thereto. The first conductive layer 121F and the second conductive layer <NUM> may include the same material. However, inventive concepts of the present disclosure are not limited thereto. The material constituting the second conductive layer <NUM> may be different from the material constituting the first conductive layer 121F. In this case, the material constituting the second conductive layer <NUM> and the material constituting the first conductive layer 121F may have etch selectivity relative to each other. When the material constituting the second conductive layer <NUM> is different from the material constituting the first conductive layer 121F, the first conductive layer 121F may include polysilicon, while the second conductive layer <NUM> may include a metal material. However, inventive concepts of the present disclosure are not limited thereto.

In some embodiments, the second voltage may be applied to the second conductive layer <NUM> including the conductive material. The second voltage may be a well bias voltage. As the well bias voltage is applied to the second conductive layer <NUM>, a separate ground area may not be disposed on the first surface 110a of the first substrate <NUM>. A ground voltage may be applied to the first substrate <NUM> through the second conductive layer <NUM>. The second conductive layer <NUM> is in contact with the first substrate <NUM>, such that when the second voltage is applied to the second conductive layer <NUM>, the second voltage may be applied to the first substrate <NUM>. Accordingly, the image sensor with improved integration may be manufactured.

The first conductive layer 121F and the second conductive layer <NUM> are spaced apart from each other. The first conductive layer 121F and the second conductive layer <NUM> may be spaced apart from each other in the third direction D3. The first conductive layer 121F and the second conductive layer <NUM> may be electrically insulated from each other. The liner film <NUM> including an insulating material may be disposed between the first conductive layer 121F and the second conductive layer <NUM>. Different voltages may be respectively applied to the first conductive layer 121F and the second conductive layer <NUM>. For example, the first voltage may be applied to the first conductive layer 121F, while the second voltage may be applied to the second conductive layer <NUM>.

In some embodiments, the first conductive layer 121F includes an upper surface 121F_US. The upper surface 121F_US of the first conductive layer 121F may face the second surface 110b of the first substrate <NUM>. The photoelectric conversion layer PD includes an upper surface PD_US. The upper surface PD_US of the photoelectric conversion layer PD may face the second surface 110b of the first substrate <NUM>.

In some embodiments, a vertical level of the upper surface 121F_US of the first conductive layer 121F based on the first surface 110a of the first substrate <NUM> is higher than that of the upper surface PD_US of the photoelectric conversion layer PD based on the first surface 110a of the first substrate <NUM>. Accordingly, the first conductive layer 121F may overlap an entirety of the photoelectric conversion layer PD in the second direction D2. In some embodiments, a vertical length of the first conductive layer 121F may be greater than a vertical length of the second conductive layer <NUM>.

In some embodiments, a width W1 in the second direction D2 of the first conductive layer 121F may be smaller than a width W2 in the second direction D2 of the second conductive layer <NUM>. Because the first conductive layer 121F is disposed between both opposing liner films <NUM>, and the second conductive layer <NUM> is a single layer filling the second trench t2, the width W1 in the second direction D2 of the first conductive layer 121F may be smaller than the width W2 in the second direction D2 of the second conductive layer <NUM>.

<FIG> is an enlarged view of a Q area of <FIG>. <FIG> is a cross-sectional view taken along a line C-C in <FIG>. For convenience of description, following descriptions are based on differences thereof from those described using <FIG>.

Referring to <FIG>, <FIG>, and <FIG>, in the light-receiving area APS, the unit pixel region PX may include a first pixel region PR1 and a second pixel region PR2.

The first pixel region PR1 and the second pixel region PR2 may be adjacent to each other and may be spaced from each other. The first pixel region PR1 may be the same as the unit pixel region PX described using <FIG>.

The second pixel region PR2 may include a first sub-pixel SP1 and a second sub-pixel SP2. The first sub-pixel SP1 and the second sub-pixel SP2 may be adjacent to each other. In <FIG>, the first sub-pixel SP1 and the second sub-pixel SP2 are shown to be aligned with each other in the second direction D2. However, inventive concepts of the present disclosure are not limited thereto.

The second pixel region PR2 may include a ground area GND. That is, each of the first sub-pixel SP1 and the second sub-pixel SP2 may include the ground area GND in a pixel area thereof. On the contrary, the first pixel region PR1 may not include the ground area GND.

In each of the first sub-pixel SP1 and the second sub-pixel SP2, the ground area GND may be disposed on one side of the transfer transistor TX. Unlike the illustration, the ground area GND may be formed in an area in each of the first sub-pixel SP1 and the second sub-pixel SP2 other than an area on one side of the transfer transistor TX.

In <FIG>, the ground area GND may be disposed between opposing portions of the element isolation pattern <NUM>. That is, in each of the first and second sub-pixels SP1 and SP2, the element isolation pattern <NUM> may define the ground area GND.

The image sensor according to some embodiments may further include a first ground contact CT1 connected to the ground area GND. The first ground contact CT1 may be connected to the ground area GND, and may apply the second voltage to the ground area GND. The second voltage may be, for example, a well bias voltage. That is, the voltage applied to the ground area GND and the voltage applied to the second conductive layer <NUM> may be the same as each other.

In some embodiments, the first sub-pixel SP1 and the second sub-pixel SP2 may share the micro lens <NUM>. That is, one micro lens <NUM> may cover the first sub-pixel SP1 and the second sub-pixel SP2. The first sub-pixel SP1 and the second sub-pixel SP2 share the micro lens <NUM>, so that signals respectively generated from the first sub-pixel SP1 and the second sub-pixel SP2 may be used as information for auto-focusing in an ISP (image signal processor) of the logic chip.

<FIG> is a cross-sectional view taken along a line D-D of <FIG>. For convenience of description, following descriptions are based on differences thereof from those described using <FIG> and <FIG>.

Referring to <FIG>, the image sensor according to some embodiments may include the first pad pattern <NUM> and the second pad pattern <NUM>.

The first pad pattern <NUM> may fill a portion of the fourth trench t4. The first pad pattern <NUM> may be connected to the first conductive layer 121F of the first defining pattern <NUM>. The first pad pattern <NUM> may be electrically connected to the first conductive layer 121F of the first defining pattern <NUM>. Accordingly, the first voltage may be applied to the first conductive layer 121F through the first pad pattern <NUM>. The first voltage may be, for example, a negative voltage.

The second pad pattern <NUM> may fill a portion of the third trench t3. The second pad pattern <NUM> may be connected to the second conductive layer <NUM>. The second pad pattern <NUM> may be electrically connected to the second conductive layer <NUM>. Accordingly, the second voltage may be applied to the second conductive layer <NUM> through the second pad pattern <NUM>. The second voltage may be different from the first voltage. The second voltage may be, for example, a well bias voltage.

In some embodiments, a depth in the third direction D3 of the first pad pattern <NUM> may be greater than a depth in the third direction D3 of the second pad pattern <NUM>. For example, the first pad pattern <NUM> may include a bottom surface 365BS. The bottom surface 365BS of the first pad pattern <NUM> may face the second surface 110b of the first substrate <NUM>. The second pad pattern <NUM> may include a bottom surface 355BS. The bottom surface 355BS of the second pad pattern <NUM> may face the second surface 110b of the first substrate <NUM>.

A vertical level of the bottom surface 365BS of the first pad pattern <NUM> based on the first surface 110a of the first substrate <NUM> may be lower than that of the bottom surface 355BS of the second pad pattern <NUM> based on the first surface 110a of the first substrate <NUM>. That is, the bottom surface 365BS of the first pad pattern <NUM> may be closer to the first surface 110a of the first substrate <NUM> than the bottom surface 355BS of the second pad pattern <NUM> may be. Further, the first pad pattern <NUM> may include a portion that does not overlap with the second pad pattern <NUM> in the second direction D2. Because the first pad pattern <NUM> is connected to the first conductive layer 121F, the second pad pattern <NUM> is connected to the second conductive layer <NUM>, and the first conductive layer 121F and the second conductive layer <NUM> are spaced apart from each other in the third direction D3, a vertical level of the bottom surface 365BS of the first pad pattern <NUM> based on the first surface 110a of the first substrate <NUM> may be lower than that of the bottom surface 355BS of the second pad pattern <NUM> based on the first surface 110a of the first substrate <NUM>.

<FIG> is a cross-sectional view taken along a line E-E of <FIG>. For convenience of description, following descriptions are based on differences thereof from those described using <FIG> and <FIG>.

Referring to <FIG>, in the image sensor according to some embodiments, the dummy unit pixel region DPX may include the ground area GND.

In the dummy unit pixel region DPX, the ground area GND may be disposed in the first surface 110a of the first substrate <NUM>. The ground area GND may be disposed between opposing portions of the element isolation pattern <NUM>. A well bias voltage may be applied to the ground area GND. For example, a second ground contact CT2 connected to the ground area GND may be provided. The well bias voltage may be applied to the ground area GND through the second ground contact CT2. The voltage applied to the ground area GND of the dummy unit pixel region DPX and the voltage applied to the second conductive layer <NUM> may be identical with each other.

<FIG> is an example cross-sectional view of an image sensor according to some embodiments. For convenience of description, following descriptions are based on differences thereof from those described using <FIG>.

Referring to <FIG>, the pixel defining pattern <NUM> is disposed in the first trench t1 and the second trench t2. The pixel defining pattern <NUM> includes the first defining pattern <NUM> and the second defining pattern <NUM>. The first defining pattern <NUM> fills the first trench t1, and the second defining pattern <NUM> fills the second trench t2. The second defining pattern <NUM> may refer to the second conductive layer.

The second trench t2 may be recessed from the second surface 110b of the first substrate <NUM>. That is, a width in the second direction D2 of the second trench t2 may gradually decrease as the trench t2 extends from the second surface 110b of the first substrate <NUM> toward the first surface 110a thereof. The first trench t1 may be recessed from the first surface 110a of the first substrate <NUM>. That is, a width in the second direction D2 of the first trench t1 may gradually decrease as the trench t1 extends from the first surface 110a of the first substrate <NUM> toward the second surface 110b thereof.

A width in the second direction D2 of the pixel defining pattern <NUM> may gradually decrease and then gradually increase as the pattern <NUM> extends from the first surface 110a of the first substrate <NUM> toward the second surface 110b thereof.

In some embodiments, at a boundary between the first trench t1 and the second trench t2, a width in the second direction D2 of the first trench t1 may be the same as a width in the second direction D2 of the second trench t2. However, inventive concepts of inventive concepts of the present disclosure are not limited thereto.

<FIG> is an example cross-sectional view of an image sensor according to some embodiments. For convenience of description, following descriptions are based on differences thereof from those described using <FIG> and <FIG>.

Referring to <FIG>, at the boundary between the first trench t1 and the second trench t2, the width in the second direction D2 of the first trench t1 and the width in the second direction D2of the second trench t2 may be different from each other.

For example, at the boundary between the first trench t1 and the second trench t2, the width in the second direction D2 of the first trench t1 may be greater than the width in the second direction D2 of the second trench t2. This structure may be generated when the first trench t1 and the second trench t2 are not aligned with each other in a process of forming the second trench t2 after forming the first defining pattern <NUM>.

Referring to <FIG>, a portion of the second conductive layer <NUM> may overlap the first defining pattern <NUM> in the second direction D2.

In the process of forming the second trench t2 after forming the first defining pattern <NUM>, the first trench t1 and the second trench t2 may not be aligned with each other. In this case, a portion of the second trench t2 may overlap with the first defining pattern <NUM> in the second direction D2. When the second conductive layer <NUM> fills the second trench t2, the first defining pattern <NUM> and the second conductive layer <NUM> may partially overlap each other in the second direction D2.

Referring to <FIG>, the second conductive layer <NUM> according to some embodiments may not be a single layer.

The second conductive layer <NUM> may include, for example, a first portion 122_1 and a second portion 122_2. The first portion 122_1 of the second conductive layer <NUM> may be disposed on an inner sidewall of the second trench t2. The second portion 122_2 of the second conductive layer <NUM> may be disposed between opposing portions of the first portion 122_1 of the second conductive layer <NUM>.

In some embodiments, the first portion 122_1 of the second conductive layer <NUM> may include a conductive material. For example, the first portion 122_1 of the second conductive layer <NUM> may include titanium nitride (TiN). However, inventive concepts of the present disclosure are not limited thereto. The second portion 122_2 of the second conductive layer <NUM> may include a conductive material. For example, the second portion 122_2 of the second conductive layer <NUM> may include polysilicon (poly Si). However, inventive concepts of the present disclosure are not limited thereto.

Referring to <FIG>, a vertical level of the upper surface 121F_US of the first conductive layer 121F based on the first surface 110a of the first substrate <NUM> may be lower than that of the upper surface PD_US of the photoelectric conversion layer PD based on the first surface 110a of the first substrate <NUM>. That is, a portion of the first conductive layer 121F may not overlap the photoelectric conversion layer PD in the second direction D2.

Hereinafter, a method for manufacturing an image sensor according to some embodiments will be described with reference to <FIG>.

<FIG> show structures of intermediate operations for illustrating a method for manufacturing an image sensor according to some embodiments. For reference, the image sensor manufactured with reference to <FIG> may be, for example, the image sensor of <FIG>.

Referring to <FIG>, the first substrate <NUM> including the first surface 110a and a third face 110c opposite to each other is provided.

The element isolation pattern <NUM> may be formed in the first substrate <NUM>. First, a trench may be formed by recessing a portion of the first surface 110a of the first substrate <NUM>. The element isolation pattern <NUM> may be formed in the trench. The element isolation pattern <NUM> may define each of the active areas.

Referring to <FIG>, a first mask film MASK1 may be formed on the first surface 110a of the first substrate <NUM>. The first mask film MASK1 may have an opening that roughly specifies a location of a pre-trench pt. The first mask film MASK1 may be composed of at least one of a photoresist film, ACL (Amorphous Carbon Layer), SOH (Spin on Hardmask), and SOC (Spin on Carbon) and a silicon nitride film.

Subsequently, the pre-trench pt may be formed using the first mask film MASK1 as an etching mask. The pre-trench pt may extend through the element isolation pattern <NUM>.

Referring to <FIG>, a pre-second conductive layer 122p may be formed. The pre-second conductive layer 122p may fill the pre-trench pt. The pre-second conductive layer 122p may cover an entirety of the first mask film MASK1. The pre-second conductive layer 122p may include a conductive material. For example, the pre-second conductive layer 122p may include polysilicon.

Referring to <FIG>, the second conductive layer <NUM> may be formed by etching the pre-second conductive layer 122p. The second conductive layer <NUM> may refer to the second defining pattern. The first trench t1 and the second trench t2 may be formed by etching the pre-second conductive layer 122p. Specifically, the second conductive layer <NUM> may be formed through an etch-back process. The second conductive layer <NUM> may fill the second trench t2. The first trench t1 may expose the second conductive layer <NUM>.

Since the first mask film MASK1 is disposed on the first surface 110a of the first substrate <NUM>, damage to the first substrate <NUM> may be minimized in a process of forming the second conductive layer <NUM>.

In some embodiments, a material of the pre-second conductive layer 122p may have an etch selectivity relative to a material constituting the first substrate <NUM>. For example, when the pre-second conductive layer 122p is silicon doped with arsenic (As), phosphorus (P), or carbon (C), the pre-second conductive layer 122p may have an etch selectivity relative to the first substrate <NUM> including silicon. In this case, the second conductive layer <NUM> may be formed without damaging the first substrate <NUM>.

Referring to <FIG>, a pre-liner film 121Lp may be formed along and on the sidewall and the bottom surface of the first trench t1. In the present disclosure, the bottom surface of the first trench t1 is defined as the face facing the first surface 110a of the first substrate <NUM>. A pre-first conductive layer 121Fp may be formed on the pre-liner film 121Lp.

The pre-liner film 121Lp may extend along and on an upper surface of the first mask film MASK1. The pre-liner film 121Lp may include an insulating material. For example, the pre-liner film 121Lp may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. However, inventive concepts of the present disclosure are not thereto.

The pre-first conductive layer 121Fp may include a conductive material. For example, the pre-first conductive layer 121Fp may include polysilicon. However, inventive concepts of the present disclosure are not thereto.

Referring to <FIG>, the first conductive layer 121F may be formed by etching a portion of the pre-first conductive layer 121Fp. The first conductive layer 121F may be formed through an etch-back process.

Referring to <FIG>, the pixel defining pattern <NUM> may be formed. The pixel defining pattern <NUM> may include a first defining pattern <NUM> and a second conductive layer <NUM>.

First, a pre-capping film (not shown) may be formed on the first conductive layer 121F. Then, a portion of the pre-capping film, a portion of the pre-liner film 121Lp, and the first mask film MASK1 may be removed to form the liner film <NUM> and the capping film 120C. A portion of the pre-capping film, a portion of the pre-liner film 121Lp, and the first mask film MASK1 may be removed such that the first surface 110a of the first substrate <NUM> may be exposed.

Referring to <FIG>, the second conductive layer <NUM> may be exposed by removing a portion of the first substrate <NUM>.

The first substrate <NUM> may be removed in a starting manner from the third side 110c of the first substrate <NUM>. A portion of the first substrate <NUM> may be removed to form the second surface 110b. The second surface 110b of the first substrate <NUM> may expose the second conductive layer <NUM>. One face of the second conductive layer <NUM> may be coplanar with the second surface 110b of the first substrate <NUM>.

<FIG> shows structures of intermediate operations for illustrating a method for manufacturing an image sensor according to some embodiments. For reference, the image sensor manufactured with reference to <FIG> may be, for example, the image sensor shown in <FIG>.

Referring to <FIG>, the first substrate <NUM> including the first surface 110a and the second surface 110b opposite to each other is provided.

The element isolation pattern <NUM> may be formed in the first substrate <NUM>. First, a trench in which a portion is recessed from the first surface 110a of the first substrate <NUM> may be formed in the first substrate <NUM>. The element isolation pattern <NUM> may be formed in the trench. The element isolation pattern <NUM> may define each of the active areas.

Referring to <FIG>, a second mask film MASK2 may be formed on the first surface 110a of the first substrate <NUM>. The second mask film MASK2 may have an opening that roughly specifies a location of the first trench t1. The second mask film MASK2 may be composed of at least one of a photoresist film, ACL (Amorphous Carbon Layer), SOH (Spin on Hardmask), SOC (Spin on Carbon) and a silicon nitride film.

Subsequently, the first trench t1 may be formed using the second mask film MASK2 as an etch mask. The first trench t1 may extend through the element isolation pattern <NUM>.

Referring to <FIG>, the pre-liner film 121Lp may be formed along the sidewall and the bottom surface of the first trench t1. The pre-first conductive layer 121Fp may be formed on the pre-liner film 121Lp.

The pre-liner film 121Lp may extend along and on an upper surface of the second mask film MASK2. The pre-liner film 121Lp may include an insulating material. For example, the pre-liner film 121Lp may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. However, inventive concepts of the present disclosure are not thereto.

Referring to <FIG>, the first defining pattern <NUM> is formed. The first defining pattern <NUM> includes the liner film <NUM>, the first conductive layer 121F, and may include the capping film 121C.

First, the first conductive layer 121F may be formed by etching a portion of the pre-first conductive layer 121Fp. The first conductive layer 121F may be formed through an etch-back process. Subsequently, the pre-capping film (not shown) may be formed on the first conductive layer 121F. Then, a portion of the pre-capping film, a portion of the pre-liner film 121Lp, and the second mask film MASK2 may be removed to form the liner film <NUM> and the capping film 120C. A portion of the pre-capping film, a portion of the pre-liner film 121Lp, and the second mask film MASK2 may be removed such that the first surface 110a of the first substrate <NUM> may be exposed.

Referring to <FIG>, a third mask film MASK3 may be formed on the second surface 110b of the first substrate <NUM>. The third mask film MASK3 may have an opening that roughly specifies a location of the second trench t2. The third mask film MASKS may be composed of at least one of a photoresist film, ACL (Amorphous Carbon Layer), SOH (Spin on Hardmask), SOC (Spin on Carbon) and a silicon nitride film.

Subsequently, the second trench t2 may be formed using the third mask film MASK3 as an etching mask. The second trench t2 may expose the first defining pattern <NUM>.

Referring to <FIG>, the pre-second conductive layer 122p filling the second trench t2 may be formed. The pre-second conductive layer 122p may cover an entirety of the third mask film MASK3. The pre-second conductive layer 122p may include a conductive material. For example, the pre-second conductive layer 122p may include polysilicon. However, inventive concepts of the present disclosure are not thereto.

Referring to <FIG>, the second conductive layer <NUM> may be formed by removing a portion of the pre-second conductive layer 122p. The second conductive layer <NUM> may be formed, so that the pixel defining pattern <NUM> may be formed. The pixel defining pattern <NUM> includes the first defining pattern <NUM> and the second defining pattern <NUM>. The second defining pattern <NUM> may refer to the second conductive layer.

Subsequently, the third mask film MASK3 may be removed.

In one or more example embodiments discussed above, power circuitry, for example power circuitry in the first and/or second semiconductor chips <NUM> and <NUM> and/or power circuitry in an external power supply (e.g., battery) connected to the first and/or second semiconductor chips <NUM> and <NUM>, may apply the first voltage to the first conductive layer 121F through the first pad pattern <NUM>, apply the second voltage (e.g., well bias voltage) to the second conductive layer <NUM> through the second pad pattern <NUM>, and/or apply the second voltage (e.g., well bias voltage, ground voltage) to ground areas GND through ground contacts (e.g., first ground contact CT1).

Claim 1:
An image sensor comprising:
a substrate (<NUM>) including, a first region (APS), a second region (OB), a first surface (110a) and a second surface (110b) opposite each other, the substrate including a plurality of unit pixel regions (PX) in the substrate (<NUM>), each of the plurality of unit pixel regions (PX) including a photoelectric conversion layer (PD1);
a pixel defining pattern (<NUM>) extending through the substrate (<NUM>) in a first direction, the pixel defining pattern (<NUM>) defining each of the plurality of unit pixel regions (PX), the pixel defining pattern (<NUM>) includes a first conductive layer (121F) and a second conductive layer spaced apart from the first conductive layer (121F); a micro lens (<NUM>) on the second surface (110b) of the substrate (<NUM>) in the first region of the substrate, and the micro lens (<NUM>) corresponding to the plurality of unit pixel regions (PX); wherein the pixel defining pattern includes a first defining pattern (<NUM>) and a second defining pattern (<NUM>) aligned with each other in the first direction and including the first and second conductive layers respectively; a first pad pattern (<NUM>) on the second surface of the substrate (110b) in the second region of the substrate (<NUM>), the first pad pattern (<NUM>) being electrically connected to the first defining pattern (<NUM>); and a second pad pattern (<NUM>) on the second surface (110b) of the substrate (<NUM>) in the second region (OB) of the substrate (<NUM>), the second pad pattern (<NUM>) being electrically connected to the second defining pattern (<NUM>), wherein the second defining pattern (<NUM>) is in contact with the substrate (<NUM>), wherein the first defining pattern (<NUM>) includes a liner film (<NUM>) and a first conductive layer (121F) on the liner film, the liner film (<NUM>) is disposed along and on a sidewall of the first trench (t1) and a bottom surface of the first trench (t1).