Patent Description:
Memory arrays are used in electronic devices to store large amounts of digital data for quick access by a processing device. Memory arrays are typically two-dimensional (2D) arrays of memory bit cell circuits ("memory bit cells") organized in memory rows and memory columns. The memory array is configured to have digital data bits written into and read from the memory bit cells in a memory row. A memory row of memory bit cells in a memory array can store a data word, which may be <NUM>, <NUM>, or <NUM> bits of data, for example, and may include additional bits for error detection and correction. In a memory read operation, a processing circuit sends the memory array an address of the data to be read and also provides an indication of a read operation. Some bits of the address are used to determine which memory row is to be read. Those address bits may be provided to a decoding circuit within the memory array. The memory array includes word lines corresponding to each memory row and bit lines corresponding to each memory column. The read operation includes activating the word line coupled to every memory bit cell in the memory row. The decoding circuit activates the word line corresponding to the memory row that contains the data word to be read. Each memory bit cell is also coupled to a bit line of a corresponding memory column. In response to the word line of a memory row being activated, stored data bits of the data word from the memory row are generated on the bit lines of the memory columns. The data bits generated on the bit lines are provided to an output of the memory array and sent back to the processing circuit and/or another circuit. Any variations in the word line signal that activates a word line during a read operation may cause incorrect data to be returned in a read operation.

Operations of the processing circuit and memory array circuit are synchronized by a periodic system clock signal. The system clock signal is typically in a first clock state for a portion of a clock period and in a second clock state for the remainder of the clock period based on a clock duty cycle. Signals may be triggered to propagate from a source to a destination by an edge (e.g., rising or falling voltage level) of the system clock signal and may be captured at another clock edge. The state of a signal may be captured and stored in a sequential storage circuit such as a latch, flip-flop, register, bit cell or other memory circuit. The signal to be captured may be a binary value (e.g., "<NUM>" or "<NUM>") indicated by a voltage level (e.g., VSS or VDD, respectively), for example.

The voltage level of a signal may be captured accurately and reliably when the received signal is held stable. In addition, variations in a signal controlling a read or write operation can cause errors in data written to and read from the memory array circuit. As processing circuit speeds increase, a period of the system clock signal becomes shorter, leaving less time for signals to stabilize. Memory arrays need to receive and decode memory addresses within a short clock period and improve timing robustness.

<CIT> describes a memory (<NUM>) includes a plurality of latching predecoders (<NUM>, <NUM>, <NUM>, <NUM>), each including a first transistor (<NUM>, <NUM>) coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor (<NUM>, <NUM>) coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor (<NUM>, <NUM>) coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor (<NUM>, <NUM>) coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor (<NUM>, <NUM>) coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value (A6A7b) during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.

Exemplary aspects disclosed herein include memory array circuits including word line circuits for improved word line signal timing. Related methods of providing stable word line signals in a memory array are also disclosed. In an exemplary aspect, memory access operation, the states of word line signals on word lines in the memory rows of the memory array may be generated based on word line latches during a first clock state of a latch clock signal. The word line latches receive address decode signals generated from a decoded memory address. An inverted delay clock circuit is configured to generate a self-timed pulse from the latch clock signal in the first clock state. The word line latches store the address decode signals during the self-timed pulse and generate word line signals based on the stored address decode signals, isolating the word lines from fluctuations in the memory address. In some examples, the memory address may be received from an address capture circuit coupled to an address bus. The address capture circuit may include pass-through latches to maximize time for a decoder to decode the memory address. However, any fluctuations in the memory address may propagate through the pass-through latches to the address decode signals. The word line latches hold the word lines stable during a memory access operation. In this regard, a time for generating a more stable word line signal to access a memory row is maximized and fluctuations in the word line signals during a memory access operation are reduced.

Exemplary aspects disclose herein include a memory array circuit comprising a plurality of memory rows, each comprising a plurality of memory bit cell circuits, and a word line coupled to each of the plurality of memory bit cell circuits. The memory array circuit includes an inverted delay clock circuit configured to receive a latch clock signal comprising one of a first clock state and a second clock state, generate an inverted delay clock signal comprising the second clock state in response to receiving the latch clock signal comprising the first clock state, and generate the inverted delay clock signal comprising the first clock state in response to receiving the latch clock signal comprising the second clock state. The memory array circuit also includes a plurality of word line latch circuits each coupled to the word line of one of the plurality of memory rows and configured to receive the latch clock signal and the inverted delay clock signal and receive an address decode signal comprising a decode state comprising one of an active state and an inactive state. Each of the plurality of word line latches is further configured to, in response to the latch clock signal comprising the first clock state and the inverted delay clock signal comprising the first clock state, store the decode state of the received address decode signal and generate a word line signal comprising the stored decode state of the address decode signal on the word line in the one of the plurality of memory rows. Each of the plurality of word line latch circuits is further configured to hold the word line signal in the stored decode state of the address decode signal on the word line in the one of the plurality of memory rows in response to the latch clock signal comprising the first clock state and the inverted delay clock signal comprising the second clock state, and generate the word line signal comprising the inactive state of the address decode signal on the word line in the one of the plurality of memory rows in response to the latch clock signal comprising the second clock state.

In an exemplary aspect, an integrated circuit (IC) comprising a memory array circuit is disclosed. The memory array circuit comprises a plurality of memory rows, each comprising a plurality of memory bit cell circuits, and a word line coupled to each of the plurality of memory bit cell circuits. The memory array circuit includes an inverted delay clock circuit configured to receive a latch clock signal comprising one of a first clock state and a second clock state, generate an inverted delay clock signal comprising the second clock state in response to receiving the latch clock signal comprising the first clock state, and generate the inverted delay clock signal comprising the first clock state in response to receiving the latch clock signal comprising the second clock state. The memory array circuit also includes a plurality of word line latch circuits each coupled to the word line of one of the plurality of memory rows and configured to receive the latch clock signal and the inverted delay clock signal and receive an address decode signal comprising a decode state comprising one of an active state and an inactive state. Each of the plurality of word line latch circuits is further configured to, in response to the latch clock signal comprising the first clock state and the inverted delay clock signal comprising the first clock state, store the decode state of the received address decode signal and generate a word line signal comprising the stored decode state of the address decode signal on the word line in the one of the plurality of memory rows. Each of the plurality of word line latch circuits is further configured to hold the word line signal in the stored decode state of the address decode signal on the word line in the one of the plurality of memory rows in response to the latch clock signal comprising the first clock state and the inverted delay clock signal comprising the second clock state, and generate the word line signal comprising the inactive state of the address decode signal on the word line in the one of the plurality of memory rows in response to the latch clock signal comprising the second clock state.

In another exemplary aspect, a method in a memory array circuit comprising a plurality of memory rows each comprising memory bit cell circuits coupled to a word line is disclosed. The method comprises receiving a latch clock signal comprising one of a first clock state and a second clock state, generating an inverted delay clock signal comprising the first clock state in response to the latch clock signal comprising the second clock state, and generating the inverted delay clock signal comprising the second clock state in response to the latch clock signal comprising the first clock state. The method includes receiving, in one of the plurality of memory rows, an address decode signal comprising a decode state comprising one of an active state and an inactive state and, in response to the latch clock signal comprising the first clock state and the inverted delay clock signal comprising the first clock state, storing the decode state of the received address decode signal and generating the stored decode state of the address decode signal on the word line in the one of the plurality of memory rows. The method further includes, in response to the latch clock signal comprising the first clock state and the inverted delay clock signal comprising the second clock state, generating the stored decode state of the address decode signal on the word line in the one of the plurality of memory rows. The method further includes, in response to the latch clock signal comprising the second clock state, generating the inactive state of the address decode signal on the word line in the one of the plurality of memory rows.

<FIG> is a schematic diagram of an exemplary memory array circuit <NUM> including an inverted delay clock circuit <NUM> and a plurality of word line latch circuits ("word line latches") <NUM> configured to generate stable word line signals <NUM> on word lines <NUM>. The memory array circuit <NUM> may be coupled to a processing circuit (not shown) that is configured to execute memory access instructions. The memory array circuit <NUM> includes memory rows <NUM> that include a plurality of memory bit cell circuits ("memory bit cells") <NUM>. Each of the memory bit cells <NUM> store a data bit <NUM> of a data word <NUM>. Data words <NUM> may be accessed (e.g., read or written) in a memory access operation in response to a memory instruction executed in the processing circuit. The memory array circuit <NUM> determines the memory row <NUM> containing the data word <NUM> to be accessed in a memory access operation based on an address signal <NUM> received on an address bus <NUM>. The address signal <NUM> is received in an address capture circuit <NUM>. The address signal <NUM> is captured and stored in the address capture circuit <NUM> and held on an internal address bus <NUM> while a system clock signal CLKSYS ("system clock CLKsys") is in a first clock state. After the system clock CLKSYS transitions from the first clock state to a second clock state, the address signal <NUM> provided on the address bus <NUM> may propagate through the address capture circuit <NUM> to the internal address bus <NUM>. In this regard, the address capture circuit <NUM> may be referred to as a pass-through circuit when the system clock CLKSYS is not in the first clock state.

It should be noted that a state of a signal, such as the first and second clock states of the system clock CLKSYS, refers to an electrical state of a signal on a line or conductor. For example, a clock state or signal state may refer to a voltage level of a signal generated at a first voltage level in a first state and at a second voltage level in a second state. In this regard, the voltage levels may correspond to binary values and may include a ground voltage (e.g., VSS or <NUM> volts) indicating a first binary state ("<NUM>" or "<NUM>") and a power supply voltage (e.g., VDD) indicating the other binary state ("<NUM>" or "<NUM>"), where a power supply voltage may be a positive or negative voltage.

From the internal address bus <NUM>, the address signal <NUM> is provided to a decoding circuit <NUM> that decodes the address signal <NUM> to identify the memory row <NUM> to be accessed. The decoding circuit <NUM> generates address decode signals <NUM> corresponding to each of the memory rows <NUM>. Each of the address decode signals <NUM> is in a decode state (i.e., an active state or an inactive state) based on the address signal <NUM>. For example, if the memory array circuit <NUM> includes <NUM> memory rows <NUM>, the address signal <NUM> may include <NUM> bits, and the decoding circuit <NUM> may generate up to <NUM><NUM> (<NUM>) address decode signals <NUM>, each one corresponding to one of the memory rows <NUM>. One of the address decode signals <NUM> corresponds to the address signal <NUM> and that one is driven to an active state for the memory access operation while the address decodes signals <NUM> of the other memory rows <NUM> are in an inactive state. The address decode signals <NUM> are received in the word line latches <NUM> from which the word line signals <NUM> are generated. The word line latches <NUM> operate in response to a latch clock signal CLKLAT that may be synchronized to the system clock CLKSYS rising. The second clock state starting of CLKLAT and CLKSYS might or might not be synchronized to each other in different implementations.

With further reference to the address capture circuit <NUM>, the address signal <NUM> is captured and held stable while the system clock CLKSYS is in the first clock state. During this state, the address signal <NUM> is held constant on the internal address bus <NUM> and the decoding circuit <NUM> to provide unfluctuating address decode signals <NUM> to the word line latches <NUM>. When the system clock CLKSYS is in the second clock state, the address signals <NUM> pass through the address capture circuit <NUM> and into the decoding circuit <NUM>. Any fluctuations in the address signal <NUM> on the address bus <NUM> may cause state changes in the address decode signals <NUM>. In this context, the term "variation" with regard to the address signal <NUM> refers to binary bits on the address bus <NUM> changing from a "<NUM>" to a "<NUM>" or from a "<NUM>" to a "<NUM>", or other instability in the signals on the address bus <NUM> that may cause the decoded address indicated by the address signal <NUM> to change. Variations or instability, such as a voltage fluctuation, of the word line signals <NUM> on the word lines <NUM> during a memory access operation can cause an error in the memory access operation. For example, in a memory read operation, changes to the word line signal <NUM> on the memory row <NUM> that is being read from may cause incorrect data to be generated on the bit lines in the memory array circuit <NUM>, resulting in a memory read error.

As previously noted, the word line latches <NUM> operate in response to the latch clock signal CLKLAT, which rises in synchronization with the system clock CLKSYS. Specifically, in response to the system clock CLKSYS transition from the second clock state to the first clock state (e.g., a rising edge of a clock), the latch clock signal CLKLAT also changes from the second clock state to the first clock state. The word line signals <NUM> are generated in an active state on the word lines <NUM> only when the latch clock signal CLKLAT is in the first state. The word line signals <NUM> are generated in an inactive state in response to the latch clock signal CLKLAT being in the second clock state. The system clock CLKSYS may not remain in the first clock state through the entire memory access operation. Thus, to keep the word line signals <NUM> active long enough to perform a memory access operation, the latch clock signal CLKLAT may not transition back to the second clock state in response to the system clock transitioning to the second clock state. In other words, the duty cycle of the latch clock signal CLKLAT may be longer than that of the system clock CLKSYS. With the system clock CLKSYS in the second clock state, if the address decode signals <NUM> were provided to the word line latches <NUM> through combinational logic, the word line signals <NUM> could become unstable while the latch clock signal CLKLAT is still in the first clock state. Thus, rather than passing the unstable address decode signals <NUM> through the word line latches <NUM> while the latch clock signal CLKLAT is in the first clock state, the word line latches <NUM> are configured to store decode states of the address decode signals <NUM> and generate the word line signals <NUM> based on the stored decode states. In further detail, the inverted delay clock circuit <NUM> is configured to receive the latch clock signal CLKLAT and, in response to receiving the latch clock signal CLKLAT in the first clock state, the inverted delay clock circuit <NUM> is further configured to generate an inverted delay clock signal CLKDLY in the second clock state. However, the inverted delay clock circuit <NUM> generates the inverted delay clock signal CLKDLY after a delay period, which is the time for the latch clock signal CLKLAT to propagate through the inverted delay clock circuit <NUM>.

The word line latches <NUM> receive the inverted delay clock signal CLKDLY and receive the address decode signals <NUM> in one of two decode states, either an active state or an inactive state. The word line latches <NUM> store the decode state of the address decode signals <NUM> in response to the latch clock signal CLKLAT in the first clock state and the inverted delay clock signal CLKDLY also in the first clock state. That is, prior to the inverted delay clock signal CLKDLY transitioning from the first clock state to the second clock state in response to the transition of the latch clock signal CLKLAT from the second clock state to the first clock state, both of the latch clock signal CLKLAT and the inverted delay clock signal CLKDLY are in the first clock state. This occurs while the system clock CLKSYS is still in the first clock state and the address decode signals <NUM> are held stable by the address capture circuit <NUM>. In this condition, the word line latches <NUM> capture the address decode signals <NUM> and generate the word line signals <NUM> on the word lines <NUM> based on the stored decode states of the address decode signals <NUM>. One of the word lines <NUM> for the target memory row <NUM> of the memory access operation receives a word line signal <NUM> in an active state based on the address signal <NUM>. The word lines <NUM> of the other (e.g., <NUM> out of <NUM>) memory rows <NUM> receive a word line signal <NUM> in an inactive state.

As noted, the transition of the latch clock signal CLKLAT to the first clock state propagates through the inverted delay clock circuit <NUM> and causes the inverted delay clock signal CLKDLY to transition to the second clock state upon expiration of a delay period. In response to the latch clock signal CLKLAT in the first clock state and the inverted delay clock signal CLKDLY in the second clock state, the word line latches <NUM> hold the word line signals <NUM> on the word lines <NUM> in the stored decode states of the address decode signals <NUM>. The latch clock signal CLKLAT transitions back to the second clock state and, in response to the latch clock signal CLKLAT in the second clock state, the word line latches <NUM> generate the word line signals <NUM> in the inactive state on the word lines <NUM>.

<FIG> is a schematic diagram provided for reference in a detailed description of an example of the inverted delay clock circuit <NUM> and the word line latches <NUM> in <FIG>, which are configured to reduce fluctuations in the word line signals <NUM>. The latch clock signal CLKLAT is inverted and the delay period or "self-timed pulse" is created by the inverted delay clock circuit <NUM>, which includes a delay circuit <NUM> that receives the latch clock signal CLKLAT and an inverter circuit <NUM>. The inverter circuit <NUM> includes an input coupled to the delay circuit <NUM>. A propagation delay of the latch clock signal CLKLAT through the inverted delay clock circuit <NUM> creates the self-timed pulse to the word line latches <NUM> during which the decode states of the address decode signals <NUM> are expected to be stable (i.e., while the system clock CLKSYS is in the first clock state). The word line signals <NUM> are generated by the stored address decode signals <NUM> and are not exposed to variations in the address signal <NUM> after the self-timed pulse. The self-timed pulse begins when the latch clock signal CLKLAT transitions to a first clock state from a second clock state and the inverted delay clock signal CLKDLY is still in the first clock state. The duration of the self-timed pulse is determined by the time of a propagation delay of the latch clock signal CLKLAT through the inverted delay clock circuit <NUM> (i.e., until expiration of the delay period). The self-timed pulse ends when the inverted delay clock signal CLKDLY transitions to the second clock state.

<FIG> shows that the word line latch <NUM> includes a pull-up circuit <NUM> coupled to an internal node <NUM>, and a pull-down circuit <NUM> coupled to the internal node <NUM>. The word line latch <NUM> also includes an inverter circuit <NUM> coupled to the internal node <NUM> and the word line <NUM>. The pull-up circuit <NUM> includes a first transistor circuit <NUM> that is configured to pull up (e.g., a voltage level) the internal node <NUM> to a supply voltage (e.g., VDD) in response to the latch clock signal CLKLAT being in the second clock state. The active state generated on the internal node <NUM> is inverted by the inverter circuit <NUM> to generate the word line signal <NUM> in an inactive state on the word line <NUM>.

The first transistor circuit <NUM> includes a pull-up transistor <NUM>, which further includes a first terminal <NUM> coupled to a supply voltage node <NUM> that provides the supply voltage VDD. The pull-up transistor <NUM> includes a second terminal <NUM> coupled to the internal node <NUM>. The pull-up transistor <NUM> also includes a gate terminal <NUM> configured to control coupling the supply voltage node <NUM> to the internal node <NUM> in response to the latch clock signal CLKLAT in the second clock state.

The pull-up circuit <NUM> also includes a keep-up circuit <NUM> configured to maintain a stored inactive state of the word line signal <NUM>. In response to the word line signal <NUM> in the inactive state, the keep-up circuit <NUM> is configured to hold (i.e., the voltage level of) the internal node <NUM> to the supply voltage VDD under either of two conditions. First, in the condition that the address decode signal <NUM> provided to the word line latch <NUM> is in the inactive state and the word line signal <NUM> is in the inactive state, the internal node <NUM> may be held up in the active state by the pull-up circuit <NUM>. Second, in the condition that the inverted delay clock signal CLKDLY is in the second clock state and the word line signal <NUM> is in the inactive state, the internal node <NUM> may be held up in the active state by the pull-up circuit <NUM>. In either of these conditions, the active state generated on the internal node <NUM> is inverted by the inverter circuit <NUM> to continue to generate the word line signal <NUM> in an inactive state on the word line <NUM>.

In detail, the keep-up circuit <NUM> includes a second transistor <NUM>, a third transistor <NUM>, and a fourth transistor <NUM>. The pull-up transistor <NUM>, second transistor <NUM>, third transistor <NUM>, and fourth transistor <NUM> may be P-type metal-oxide semiconductor (PMOS) transistors but are not limited in this regard. An example of a P-type transistor is a silicon transistor doped with a pentavalent dopant such as aluminum, indium or gallium. The second transistor <NUM> includes a first terminal <NUM> coupled to a pull-up node <NUM>, a second terminal <NUM> coupled to the internal node <NUM>, and a gate terminal <NUM>. The gate terminal <NUM> is configured to control coupling the pull-up node <NUM> to the internal node <NUM> in response to the address decode signal <NUM> in the inactive state. The third transistor <NUM> includes a first terminal <NUM> coupled to the supply voltage node <NUM>, a second terminal <NUM> coupled to the pull-up node <NUM>, and a gate terminal <NUM>. The gate terminal <NUM> is configured to control coupling the supply voltage node <NUM> to the pull-up node in response to the word line signal <NUM> in the inactive state. The fourth transistor <NUM> includes a first terminal <NUM> coupled to the pull-up node <NUM>, a second terminal <NUM> coupled to the internal node <NUM>, and a gate terminal <NUM>. The gate terminal <NUM> is configured to control coupling the pull-up node <NUM> to the internal node <NUM> in response to the inverted delay clock signal CLKDLY in the second clock state.

The pull-down circuit <NUM> is configured to pull-down (i.e., a voltage level of) the internal node <NUM> to a second supply voltage, such as a ground voltage, in the condition that the latch clock signal CLKLAT is in the first clock state when one of two additional conditions exist. First, the pull-down circuit <NUM> may hold down the internal node <NUM> when the latch clock signal CLKLAT is in the first clock state and the word line signal <NUM> on the word line <NUM> is in the active state. Second, the pull-down circuit <NUM> may pull-down the internal node <NUM> if the latch clock signal CLKLAT is in the first clock state, the address decode signal <NUM> is in the active state, and the inverted delay clock signal CLKDLY is in the first clock state.

In detail, the pull-down circuit <NUM> includes a fifth transistor <NUM>, a sixth transistor <NUM>, a seventh transistor <NUM>, and an eighth transistor <NUM>. The fifth transistor <NUM>, sixth transistor <NUM>, seventh transistor <NUM>, and eighth transistor <NUM> may be N-type metal-oxide semiconductor (NMOS) transistors but are not limited in this regard. An example of an N-type transistor is a silicon transistor doped with a trivalent dopant such as arsenic, antimony, or bismuth. The fifth transistor <NUM> includes a first terminal <NUM> coupled to the internal node <NUM>, a second terminal <NUM> coupled to a pull-down node <NUM>, and a gate terminal <NUM>. The gate terminal <NUM> is configured to control coupling the internal node <NUM> to the pull-down node <NUM> in response to the latch clock signal CLKLAT in the first clock state. The sixth transistor <NUM> includes a first terminal <NUM> coupled to the pull-down node <NUM>, a second terminal <NUM>, and a gate terminal <NUM>. The gate terminal <NUM> is configured to control coupling the pull-down node <NUM> to the second terminal <NUM> in response to the address decode signal <NUM> in the active state. The seventh transistor <NUM> of the pull-down circuit <NUM> includes a first terminal <NUM> coupled to the second terminal <NUM> of the sixth transistor <NUM> and a second terminal <NUM> coupled to a second supply voltage node <NUM> providing the second supply voltage (e.g., VSS or ground). A gate <NUM> controls coupling the second supply voltage node <NUM> to the first terminal <NUM> of the seventh transistor <NUM> in response to the inverted delay clock signal CLKDLY in the first clock state. The eighth transistor <NUM> includes a first terminal <NUM> coupled to the pull-down node <NUM>, a second terminal <NUM> coupled to the second supply voltage node <NUM>, and a gate terminal <NUM>. The gate terminal <NUM> is configured to control coupling the second supply voltage node <NUM> to the pull-down node <NUM> in response to the word lines signal <NUM> in the active state.

Referring back to <FIG>, a detailed description of the decoding circuit <NUM> and the address capture circuit <NUM> are provided. The decoding circuit <NUM> includes an input <NUM> coupled to the internal address bus <NUM> and a plurality of outputs <NUM> each coupled to one of the plurality of word line latches <NUM>. The decoding circuit <NUM> is configured to receive the address signal <NUM> on the internal address bus <NUM>, decode the address signal <NUM>, and generate the decode states of the address decode signals <NUM> on the outputs <NUM>. In particular, on the one output <NUM> corresponding to the address signal <NUM>, the decoding circuit <NUM> is configured to generate the address decode signal <NUM> in the active state. On the other outputs <NUM> (i.e., not corresponding to the address signal <NUM>), the decoding circuit <NUM> is configured to generate the address decode signal <NUM> in the inactive state. The memory array circuit <NUM> may be included in an integrated circuit (IC) <NUM> that further includes a processing circuit (not shown), for example.

The second clock state active pass-through address capture circuit <NUM> is coupled to the internal address bus <NUM> and also to the address bus <NUM>. The address capture circuit <NUM> is configured to receive the address signal <NUM> on the address bus <NUM> and receive the system clock CLKSYS. In response to the system clock CLKSYS in the active state, the address capture circuit <NUM> stores the address signal <NUM> and holds, on the internal address bus <NUM>, the address signal <NUM> stored in the address capture circuit <NUM>. Also, in response to the system clock CLKSYS in the inactive state, the address capture circuit <NUM> generates, on the internal address bus <NUM>, the address signal <NUM> received on the address bus <NUM>. While the system clock CLKSYS in inactive state, the address capture circuit <NUM> is in pass-through state to maximize time available for address decoding.

<FIG> is an illustration of a word line circuit <NUM> employed in a conventional memory array in which fluctuations on the address bus are propagated and may become fluctuations and timing margin violations on the word lines. An internal node <NUM> is pulled up to an active state whenever the latch clock signal CLKLAT is in the second clock state and also whenever an address decode signal <NUM> is in an inactive state. The internal node <NUM> is pulled down under the condition of the latch clock signal CLKLAT being in the first clock state and the address decode signal <NUM> being in the active state. An inverter <NUM> generates a word line signal <NUM> that is an inverse of a state of the internal node <NUM>. Thus, the word line circuit <NUM> does not store the address decode signal <NUM> and, instead, generates the word line signal <NUM> combinationally based on the address decode signal <NUM>, including any fluctuations or timing variations, which may potentially cause errors in memory access operations.

<FIG> is a timing diagram illustrating the states of signals in the conventional memory array circuit employing the word line circuit <NUM> in <FIG> and signals of the exemplary memory array circuit <NUM> in <FIG> employing the exemplary inverted delay clock circuit <NUM> and word line latches <NUM> in <FIG> and <FIG>. Signals in <FIG> are referred to using the same labels as in.

The signals are described below in descending order from the first signal (address signal <NUM>) at the top of the timing diagram in <FIG>. As indicated, the first signal in <FIG> is the address signal <NUM> arriving on the address bus <NUM>. Prior to the time T0, the address signal <NUM> transitions from the second clock state (e.g., low) to the first clock state (e.g., high) based on a memory address provided by a processing circuit. The second signal in <FIG> is the system clock CLKSYS. At time T0 the system clock CLKSYS transitions from a second clock state to a first clock state, remains in the first clock state for a time based on the clock duty cycle, and transitions back, at time T2, to the second clock state. The address capture circuit <NUM> in <FIG> captures the state of the address signal <NUM> in response to the system clock CLKSYS being in the first clock state from time T0 to time T2. The address capture circuit <NUM> holds the captured state of the address signal <NUM> on the internal address bus <NUM> from time T0 to time T2, when the system clock CLKSYS transitions back to the second clock state.

The third signal shown in <FIG> is the internal address bus <NUM> carrying the address signal <NUM>. Before the time T0 and after the time T2, the address signal <NUM> propagates through the address capture circuit <NUM> from the address bus <NUM> to the internal address bus <NUM>. Thus, any fluctuations that may occur on the address bus <NUM> before time T0 and after time T2 cause fluctuations on the address signal <NUM> on the internal address bus <NUM>.

The fourth signal in <FIG> is the address decode signal <NUM> corresponding to the address signal <NUM> on the internal address bus <NUM>. Before time T3, the address signal <NUM> has transitioned from an inactive state to an active state and transitions back to the inactive state after time T3, as an example of a fluctuation in the address signal <NUM>. Because the address capture circuit is a pass-through latch when the system clock CLKSYS is in the second clock state, the address decode signal <NUM> transitions from an inactive state to an active state and back to the inactive state. Thus, fluctuations on the address signal <NUM> on the address bus <NUM> are propagated through the address capture circuit <NUM> and through the decoding circuit <NUM>.

The fifth signal in <FIG> is the latch clock signal CLKLAT, which rises in synchronization with the system clock CLKSYS. The amount of time the latch clock signal CLKLAT remains in the first clock state may be determined by a self-timed circuit or in another manner. In this regard, the latch clock signal CLKLAT transitions (e.g., rises) from the second clock state to the first clock state in response to the system clock CLKSYS at time T0, but the latch clock signal CLKLAT has a longer duty cycle than the system clock CLKSYS.

The sixth signal in <FIG> is the word line signal <NUM> generated in the word line circuit <NUM> in the conventional memory array circuit. The word line signal <NUM> is an example of a problem with the conventional method, for purposes of comparison. As shown in <FIG>, any fluctuations to the address signal <NUM> on the address bus <NUM> (e.g., time T3), when the system clock CLKSYS is in the second clock state, are propagated through the word line circuit <NUM> to cause variations in the word line signal <NUM>.

The seventh signal in <FIG> is the inverted delay clock signal CLKDLY. As shown, the state of the inverted delay clock signal CLKDLY is based on the delayed and inverted state of the latch clock signal CLKLAT. The word line latches <NUM> in <FIG> capture and store the address decode signals <NUM> when both the latch clock signal CLKLAT and the inverted delay clock signal CLKDLY are in the first clock state (e.g., high). This condition exists from time T0 to time T1, which is referred to herein as a self-timed pulse. The word line signals <NUM> are held in a state determined by the captured address decode signals <NUM> until the latch clock signal CLKLAT transitions to the second clock state (e.g., falls to a low state). After the latch clock signal CLKLAT transitions back to the second clock state, the word line signals <NUM> are pulled down to the inactive state.

The eighth signal in <FIG> is the internal node <NUM> in <FIG>, which is inverted to generate the word line signal <NUM>. The last signal in <FIG> is the word line signal <NUM> on the word line <NUM>. One of the word line signals <NUM> in the memory array circuit <NUM>, corresponding to the address identified by the address signal <NUM>, is activated. The word line signal <NUM> does not change in response to fluctuations in the address signal <NUM> on the address bus <NUM> because those fluctuations do not propagate through the word line latches <NUM>.

<FIG> and <FIG> are a flow chart illustrating a method <NUM> in the memory array circuit <NUM> in <FIG> for capturing address decode signals <NUM> in response to a clock pulse to reduce errors due to fluctuations of the address signal <NUM> on the address bus <NUM>. The method <NUM> is a method in a memory array circuit <NUM> including a plurality of memory rows <NUM> each comprising memory bit cell circuits <NUM> coupled to a word line <NUM>. The method <NUM> begins at <FIG> and includes receiving a latch clock signal CLKLAT in one of a first clock state and a second clock state (block <NUM>). The method includes generating an inverted delay clock signal CLKDLY comprising the first clock state in response to the latch clock signal CLKLAT comprising the second clock state (block <NUM>) and generating the inverted delay clock signal CLKDLY comprising the second clock state in response to the latch clock signal CLKLAT comprising the first clock state (block <NUM>). The method further includes receiving, in one of the plurality of memory rows <NUM>, an address decode signal <NUM> comprising a decode state comprising one of an active state and an inactive state (block <NUM>). The method <NUM> further includes, in response to the latch clock signal CLKLAT comprising the first clock state and the inverted delay clock signal CLKDLY comprising the first clock state, storing the decode state of the received address decode signal <NUM> and generating the stored decode state of the address decode signal <NUM> on the word line <NUM> in the one of the plurality of memory rows <NUM> (block <NUM>). The method continues at <FIG> and further includes, in response to the latch clock signal CLKLAT comprising the first clock state and the delay clock signal CLKDLY comprising the second clock state, holding the stored decode state of the address decode signal <NUM> on the word line <NUM> in the one of the plurality of memory rows <NUM> (block <NUM>). The method also includes, in response to the latch clock signal CLKLAT comprising the second clock state, generating the inactive state of the address decode signal <NUM> on the word line <NUM> in the one of the plurality of memory rows <NUM> (block <NUM>).

<FIG> is a block diagram of an exemplary processor-based system <NUM> that includes a processor <NUM> (e.g., a microprocessor) that includes an instruction processing circuit <NUM>. The processor-based system <NUM> may be a circuit or circuits included in an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server, or a user's computer. In this example, the processor-based system <NUM> includes the processor <NUM>. The processor <NUM> represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, or the like. More particularly, the processor <NUM> may be an EDGE instruction set microprocessor, or other processor implementing an instruction set that supports explicit consumer naming for communicating produced values resulting from execution of producer instructions. The processor <NUM> is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor <NUM> includes an instruction cache <NUM> for temporary, fast access memory storage of instructions accessible by the instruction processing circuit <NUM>. Fetched or prefetched instructions from a memory, such as from a main memory <NUM> over a system bus <NUM>, are stored in the instruction cache <NUM>. Data may be stored in a cache memory <NUM> coupled to the system bus <NUM> for low-latency access by the processor <NUM>. The instruction processing circuit <NUM> is configured to process instructions fetched into the instruction cache <NUM> and process the instructions for execution.

The processor <NUM> and the main memory <NUM> are coupled to the system bus <NUM> and can intercouple peripheral devices included in the processor-based system <NUM>. As is well known, the processor <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the processor <NUM> can communicate bus transaction requests to a memory controller <NUM> in the main memory <NUM> as an example of a slave device. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus constitutes a different fabric. In this example, the memory controller <NUM> is configured to provide memory access requests to a memory array <NUM> in the main memory <NUM>. The memory array <NUM> is comprised of an array of storage bit cells for storing data. The main memory <NUM> may be a read-only memory (ROM), flash memory, dynamic random-access memory (DRAM), such as synchronous DRAM (SDRAM), etc., and a static memory (e.g., flash memory, static random-access memory (SRAM), etc.), as non-limiting examples.

Other devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include the main memory <NUM>, one or more input device(s) <NUM>, one or more output device(s) <NUM>, a modem <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem <NUM> can be any device configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem <NUM> can be configured to support any type of communications protocol desired. The processor <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display(s) <NUM> can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc..

The processor-based system <NUM> in <FIG> may include a set of instructions <NUM> to be executed by the processor <NUM> for any application desired according to the instructions. The instructions <NUM> may be stored in the main memory <NUM>, processor <NUM>, and/or instruction cache <NUM> as examples of a non-transitory computer-readable medium <NUM>. The instructions <NUM> may also reside, completely or at least partially, within the main memory <NUM> and/or within the processor <NUM> during their execution. The instructions <NUM> may further be transmitted or received over the network <NUM> via the modem <NUM>, such that the network <NUM> includes computer-readable medium <NUM>.

While the computer-readable medium <NUM> is shown in an exemplary embodiment to be a single medium, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that stores the one or more sets of instructions. The term "computer-readable medium" shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by the processing device and that causes the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term "computer-readable medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical medium, and magnetic medium.

The processor <NUM> in the processor-based system <NUM> may include, in any of the devices therein, a memory array circuit that employs an inverted delay clock circuit and word line latches for generating more stable word line signals on the word lines in the memory rows, as illustrated in <FIG> and <FIG>.

The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

The embodiments disclosed herein may be provided as a computer program product, or software, that may include a machine-readable medium (or computer-readable medium) having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: a machine-readable storage medium (e.g., ROM, random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, flash memory devices, etc.); and the like.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The components of the distributed antenna systems described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not actually recite an order to be followed by its steps, or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is in no way intended that any particular order be inferred.

Claim 1:
A memory array circuit (<NUM>) comprising:
a plurality of memory rows (<NUM>), each comprising:
a plurality of memory bit cell circuits (<NUM>); and
a word line (<NUM>) coupled to each of the plurality of memory bit cell circuits (<NUM>);
an inverted delay clock circuit (<NUM>) configured to:
receive a latch clock signal (CLKLAT) comprising one of a first clock state and a second clock state;
generate an inverted delay clock signal (CLKDLY) comprising the second clock state in response to receiving the latch clock signal (CLKLAT) comprising the first clock state; and
generate the inverted delay clock signal (CLKDLY) comprising the first clock state in response to receiving the latch clock signal (CLKLAT) comprising the second clock state; and
a plurality of word line latch circuits (<NUM>) each coupled to the word line (<NUM>) of one of the plurality of memory rows (<NUM>) and configured to:
receive the latch clock signal (CLKLAT) and the inverted delay clock signal (CLKDLY);
receive an address decode signal (<NUM>) comprising a decode state comprising one of an active state and an inactive state;
in response to the latch clock signal (CLKLAT) comprising the first clock state and the inverted delay clock signal (CLKDLY) comprising the first clock state, store the decode state of the received address decode signal (<NUM>) and generate a word line signal (<NUM>) comprising the stored decode state of the address decode signal (<NUM>) on the word line (<NUM>) in the one of the plurality of memory rows (<NUM>);
hold the word line signal (<NUM>) comprising the stored decode state of the address decode signal (<NUM>) on the word line (<NUM>) in the one of the plurality of memory rows (<NUM>) in response to the latch clock signal (CLKLAT) comprising the first clock state and the inverted delay clock signal (CLKDLY) comprising the second clock state; and
generate the word line signal (<NUM>) comprising the inactive state of the address decode signal (<NUM>) on the word line (<NUM>) in the one of the plurality of memory rows (<NUM>) in response to the latch clock signal (CLKLAT) comprising the second clock state.