Patent Description:
The present invention relates generally to quantum and classical digital superconducting circuits, and specifically to Josephson memory and logic circuits using a quasi-long-junction interconnect.

In the field of digital logic, extensive use is made of well known and highly developed complementary metal-oxide semiconductor (CMOS) technology. As CMOS has begun to approach maturity as a technology, there is an interest in alternatives that may lead to higher performance in terms of speed, power dissipation computational density, interconnect bandwidth, and the like. An alternative to CMOS technology comprises superconductor based single flux quantum circuitry, utilizing superconducting Josephson junctions, with typical signal power of around <NUM> nanowatts (nW), at a typical data rate of <NUM> gigabits per second (Gb/s) or greater, and operating temperatures of around <NUM> kelvins.

A non-destructive readout (NDRO) circuit is a circuit that can retrieve a stored information state (e.g., one or multiple bits) for transmission to other circuitry for processing or output without erasing, destroying, changing, or otherwise corrupting the stored information state. For the purposes of this description, the term NDRO should not be interpreted to include circuits that destructively retrieve a stored information state but then thereafter perform a restorative write-back.

Reciprocal quantum logic (RQL) is a family of low-power superconducting circuits. In wave-pipelined RQL, a logical "<NUM>" can be encoded as a positive single flux quantum (SFQ) pulse followed by a reciprocal negative pulse, whereas a logical "<NUM>" can be encoded as the absence of either such pulse.

Document <CIT> discloses an example of a superconducting logic-based memory.

The present invention is defined by a Josephson memory array according to independent claim <NUM> and a method of memory access in said Josephson memory array according to independent claim <NUM>. <NUM> Advantageous features are set out in the dependent claims.

Quasi-long-junction interconnects can be used, instead of Josephson transmission lines (JTLs) or passive transmission lines (PTLs), in non-destructive readout (NDRO) circuits to create a fast, dense reciprocal quantum logic (RQL) memory array. Logic circuits, such as an address decoder associated with such a memory array, can include similar circuits as those used in the memory and can thereby operate on the same principles. The circuits can advantageously incorporate π-junctions in addition to standard Josephson junctions. Fast, low-power, low-latency RQL logic benefits from a suitable memory technology that is similarly fast, low-power, and low-latency. This is particularly true for low-level cache memory. Accordingly, the circuits described herein provide a fast, dense memory technology for RQL, suitable for low-level caches and other memories collocated with an RQL processor, thus filling a critical technology gap.

In some examples, the circuits described herein offer a more efficient implementation of an RQL NDRO memory array than of the type described in <CIT>, and entitled "Superconducting Non-Destructive Readout Circuits". For convenience of reference, the NDRO circuit topology described therein will herein be referred to as the "body-tails NDRO. " An example memory cell incorporating the circuits described herein has a similar logic behavior as a body-tails NDRO-based memory cell, featuring x-y addressing for writes, but with multiplexor logic for reads. As with a memory cell based on the body-tails NDRO, both write and read operations are word-organized at the array level. In contrast to the body-tails NDRO, however, the presently described circuits advantageously make use of a quasi-long-junction interconnect among cells in the array, which is fast and power-efficient. Also described herein is an implementation of the unit cell that is physically small (i.e., using a frustrated array of Josephson junctions and π-junctions) and with symmetric states (i.e., multi-fold degeneracy). The degeneracy minimizes fan-out requirements on the address lines. The present description further describes use of quasi-longjunction interconnect for the NOR-gate-based readout.

<FIG> shows a schematic of a unit cell <NUM> that can be tiled to make a memory array. Address lines E (write enable) and Rm (read enable) feed sub-circuit <NUM>, which receives data input on line D, and outputs data on bit line B. These address lines and data lines each form interconnects that use only small-value interconnect inductors L, e.g., having an inductance value of between about one picohenry and about ten picohenries, e.g., between about one picohenry and about five picohenries, making the resultant memory array small, fast, and power-efficient. Inputs to sub-circuit <NUM> are provided through floating Josephson junctions <NUM>, <NUM>, <NUM>, which are also referred to herein as escape junctions. As viewed across the tiled memory array, the address and data lines are quasi-long Josephson junctions, in that they retain the signal propagation characteristics of long Josephson junctions, without necessarily retaining the capability of being analyzed by the same analytical formula applicable to long Josephson junctions, for reason that there are other components between floating Josephson junctions <NUM>, <NUM>, <NUM> and their respective connections to ground, as indicated by the broken lines inside sub-circuit <NUM>.

The following description provides an explanation of the meaning of "quasi-long Josephson junction" ("quasi-LJJ") as that term is used in the present description. In a typical Josephson transmission line (JTL), such as one configured as an interconnect between different RQL gates, memory cells, or other circuit elements, a line of parallel Josephson junctions connected to ground at one end of each are linked with each other by interconnect inductors at the other end, and when one Josephson junction in the JTL is triggered by an incoming single flux quantum (SFQ) pulse, it triggers the next Josephson junction in the JTL, and so on down the line, with each Josephson junction triggering distinctly from its neighbors.

A lumped-element long Josephson junction (LJJ) can resemble a JTL but with the interconnect inductors made to be much smaller, e.g., between about one picohenry and about ten picohenries, e.g., between about one picohenry and about five picohenries, or in other words about ten times smaller than in a typical JTL. In such an LJJ, and in contrast to the functional behavior of a JTL, the way in which the Josephson junctions trigger is distinct from that observed in a typical JTL: the signal propagation instead exhibits a wavelike behavior, with the triggering not localizable to any particular Josephson junction in the LJJ as compared to the triggering of its neighboring Josephson junctions. The transmitted SFQ pulse then becomes a soliton traveling through the nonlinear medium of the lumped-element LJJ. "Lumped-element" in this context is used to distinguish the LJJ structure from LJJs that are true continuous Josephson junctions, rather than, as with a lumped-element LJJ, a set of discrete Josephson junctions linked by very small interconnect inductors.

Because of their relatively poor performance at reliably transmitting signals over the relatively long chip layout distances frequently associated with inter-gate connections, lumped-element LJJs are typically not practical as logic interconnects. However, LJJs are capable of passing pulses at very fast speeds and with much lower energy usage than JTL interconnects, and require less damping and applied power, when the transmission distance is low. LJJs therefore are well-suited to usage as interconnects in a memory array, where there is a very tight fabric of elements (i.e., the individual memory cells of the array) with relatively small distances between each of the elements. In such an LJJ, pulses are not transmitted at the speed of light as they would be through a passive transmission line, but the LJJ interconnection permits maintaining pulse integrity over the associated small transmission distances.

The LJJ interconnects as provided to memory cells (as shown in <FIG>) are referred to herein as "quasi-long Josephson junctions" ("quasi-LJJs"). Whereas an analytical formula can be used to analyze LJJs consisting only of Josephson junctions and interconnect inductors, the same such formula does not apply to analyze LJJs where some of the Josephson junctions are connected to ground only indirectly by memory unit cells, such that true LJJ dynamics are not achieved. In such case, the behavior cannot be analytically reduced to a simple formula, as with lumped-element LJJs. Although quasi-LJJ interconnects as viewed across an entire memory array do not analytically behave as true LJJs, the key features of very fast signal propagation and no fan-out are preserved. Accordingly, "quasi-long Josephson junction," as that term is used herein, means a JTL structure with small linking inductance values (e.g., between about one picohenry and about ten picohenries, e.g., between about one picohenry and about five picohenries) characteristic of an LJJ and wherein at least some of the Josephson junctions do not terminate directly to ground on the side opposite the signal transmission path, but instead terminate to ground indirectly within a memory unit cell sub-circuit.

The memory unit cell <NUM> has the same logical operation as the body-tails NDRO memory, but uses an interconnect that can be smaller and faster. Instead of using JTL-based splitter networks to distribute signals, unit cell <NUM> uses simple JTL chains that do not fan out and can have very small inductor values. The small inductor values enable quasi-long junction dynamics, where power and damping can be reduced relative to a JTL-based splitter network approach. The interconnect is physically compact and fast. There are effectively three inputs to the internal sub-circuit <NUM> of unit cell <NUM>, labeled d, e, and r_m, corresponding respectively to data input, write enable, and read enable lines D, E, and Rm, as well as one output b, corresponding to the bit line B on which data read from the memory unit cell <NUM> is output. As indicated by the broken lines in the box schematic of internal sub-circuit <NUM> of memory cell <NUM>, each of d, e, and r_m inputs are tied to ground through some component or set of components.

The "m" designation (for "mirrored") in the name assigned to the read enable line Rm and the sub-circuit node r_m indicates that the corresponding assertion signal is mirrored from that of the other signals shown (E, D B). For example, if the other signals (E, D, B) are asserted using a positive pulse followed by a negative pulse, according to the typical positive-negative pulse pair encoding convention frequently used to indicate logical assertion in wave-pipelined RQL, then in the signals propagated along read enable line Rm, a negative pulse is transmitted before a positive pulse in the reciprocal pulse pair to indicate logical assertion. Suitable polarity inverter circuits can be provided only at the periphery of a tiled memory array, so as to achieve the polarity-inverted signals Rm supplied along the read enable lines, rather than having to provide an inverter to each unit cell <NUM> in the array. Examples of suitable polarity inverter circuits can be found in <CIT>, entitled "Josephson Polarity and Logical Inverter Gates.

<FIG> illustrates an example internal sub-circuit <NUM> of a memory unit cell, having a circular configuration. Thus, sub-circuit <NUM> can correspond to internal sub-circuit <NUM> in <FIG>. (Another example internal sub-circuit is described with respect to, and illustrated in, <FIG>. ) The illustrated unit cell internals <NUM> have a circular structure between the d, e, and r_m input nodes. Phase shifter elements are implemented as π Josephson junctions <NUM>, <NUM>, <NUM>, <NUM>. The b readout node is connected to the r_m input node via π Josephson junction <NUM> and inductor Lbr_m as shown. Mutual inductance coupling <NUM> can be provided between inductor Ldr_m and inductor Lbr_m. Similarly, mutual inductance <NUM> can be provided between Lr_me and inductor Lbr_m. These mutual inductances can be provided to tune the potential energy levels of the different states to be equal.

Considering schematic <NUM> of <FIG> in tandem with the external quasi-LJJs shown in schematic <NUM> of <FIG>, there are two Josephson junctions in series before each respective quasi-LJJ is connected to ground: Josephson junction pairs <NUM>, <NUM>; <NUM>, <NUM>; and <NUM>, <NUM>. Thus, every time a pulse is propagated along one of the quasi-LJJs, one or the other of those two Josephson junctions triggers. As such, each quasi-LJJ continues to act as a pulse repeater and to send a pulse along, but it does not have the ideal behavior that a true LJJ would have. The use of quasi-LJJs permits the pulses to propagate fast and enables very compact physical layout for a tiled memory. Moreover, the total configuration (e.g., schematics <NUM> and <NUM> considered together) allow for the quasi-LJJs not to have to split into different JTLs in order to feed into different memory unit cells, because a pulse propagating along one of the quasi-LJJs can impact the sub-circuit <NUM> as it goes by, without necessitating fan-out.

The timing diagram of <FIG> illustrates an example operation of an NDRO unit cell like that of <FIG> in physical-level simulation in SPICE, with the traces representative of phase over time in nanoseconds. Successive positive-then-negative or negative-then-positive steps in the traces indicative of signal logical assertion within a clock cycle will be referred to as phase pulses, to distinguish them from voltage pulses (e.g., SFQ pulses). Each phase pulse seen in the traces is formed by a reciprocal pair of voltage pulses propagating through the circuit.

During data write operations, the internal logical state of the unit cell is updated to the present logical state of the data input (D) upon a falling edge of a phase pulse corresponding to an assertion of the write enable (E) input. The timing diagram shows two such assertions of the write enable (E) input having respective falling edges <NUM>, <NUM> at the first and second nanosecond marks, respectively. At the time of the falling edge <NUM> of first write enable (E) assertion, the data input (D) signal phase is high <NUM>, changing the internal state from logical "<NUM>" to logical "<NUM>", as can be seen by the rise to a high phase value <NUM> at internal node e. At the time of the falling edge <NUM> of second write enable (E) assertion, the data input (D) signal phase is low <NUM><NUM>, and accordingly the internal state is changed from logical "<NUM>" back to logical "<NUM>", as can be seen by the return to a low phase value <NUM> at internal node e.

As illustrated, the read enable waveform Rm has inverted polarity with respect to the other waveforms, i.e., low phase signal portions indicate logical assertion, meaning that a negative voltage pulse (e.g., an SFQ pulse) brings the signal phase low (to assert Rm) and a subsequent positive voltage pulse (e.g., an SFQ pulse) brings the signal phase high again (to deassert Rm). During data read operations, in addition to the read enable signal Rm being asserted, corresponding to a read enable phase pulse propagating through the fabric of tiled memory units in the word direction (i.e., horizontally in <FIG>), what is known as a "pilot phase pulse" or "interrogation phase pulse" propagates through the memory fabric in the orthogonal direction (i.e., vertically in <FIG>), with one such pilot phase pulse propagating for each bit to be read. The pilot phase pulse propagates through all the unit cells in the fabric and emerges at the bottom periphery of the memory, except if the unit cell being read (as designated by the vertex between the issued pilot phase pulse and the read enable phase pulse) is in the logical "<NUM>" state, in which case the pilot phase pulse will be blocked (at the location of the unit cell), and will not emerge at the bottom periphery of the memory. Thus, the memory functions according to an inverting read, wherein an unasserted signal emerging from the bit line (B) is indicative of a logical "<NUM>" memory state having been read, and an asserted signal-as asserted initially by the pilot phase pulse-emerging from the bit line (B) is indicative of a logical "<NUM>" memory state having been read.

In the illustrated example, two pilot pulses are issued on the bit line (B) in quick succession every nanosecond, for a total of four pilot pulses <NUM>, <NUM>, <NUM>, <NUM>. Only two of the pilot pulses, <NUM>, <NUM>, correspond to read operations on the observed unit cell; the other two pilot pulses <NUM>, <NUM> are possibly for read operations on other unit cell(s) in the same column. Also in the illustrated example, two read enable pulses are issued on the read enable line (Rm) in quick succession every nanosecond, for a total of four read enable pulses <NUM>, <NUM>, <NUM>, <NUM>. Only two of the read enable pulses, <NUM>, <NUM>, correspond to read operations on the observed unit cell; the other two read enable pulses <NUM>, <NUM> are possibly for read operations on other unit cell(s) in the same row. The effect of the memory state along the bit line is indicated in the timing diagram by the phase at node b (i.e., the bottom trace in <FIG>), which trace follows the bit line signal (B), except that a pulse corresponding to the first pilot pulse <NUM> is missing from the node b phase trace, because on the first read operation, at the intersection between pilot phase pulse <NUM> and the contemporaneous phase pulse <NUM> on the read enable signal line (Rm), the pilot phase pulse is blocked. Data input pulses <NUM>, <NUM> correspond to half-select conditions, i.e., where a phase pulse is issued on the data input line (D) without a contemporaneous write pulse being issued on the write enable line (E).

The following truth table relates the effect of phase pulses within a clock cycle on the input lines and the phase at node b. The numbers in parentheses at the beginning of each line indicate the relative order in which the listed operations appear in the timing diagram of <FIG>.

As can be seen in the potential energy plot <NUM> of <FIG> (which drawing otherwise duplicates the timing diagram of <FIG>), apart from switching transients that appear as brief spikes in the potential energy plot <NUM>, the total potential energy of the unit cell in the different states is shown to be equal, which provides the advantage that the address lines (D, E, Rm, B) do not need to provide power gain or fan-out. This enables the quasi-long-junction interconnect, which does not have explicit fan-out. The potential energy difference of a single Josephson junction is shown by potential energy bar <NUM>.

<FIG> illustrate detailed write operations, with states of the circuit array under different input select and half-select conditions being depicted. All possible signal combinations starting from the two initial states are shown. Each state is a combination of persistent currents running in the indicated directions through the three current loops in the triangular structure of unit cell internals <NUM>, with d, e, and r_m nodes being indicated, corresponding to the same nodes depicted in <FIG>. Clockwise currents are denoted by the abbreviation "CW" while counter-clockwise currents are denoted by the abbreviation "CCW. " Dots on either sides of the Josephson junctions indicate junction phase transitions that by convention are positive in the direction of the dot. Due to the π Josephson junction phaseshifters, each persistent current is ±½Φ<NUM>. "No change" means the signal is absorbed by the respective escape junction that connects the circuit node to the address line. For simplicity of illustration, these escape junctions are not shown in <FIG>, but see Josephson junctions <NUM>, <NUM>, <NUM> in <FIG>.

<FIG> show the effect on the circuit of a read enable phase pulse transit (i.e., absent a data input pulse contemporaneous to it in the same clock cycle) starting from the "<NUM>" memory state of the circuit (i.e., when the illustrated unit cell is storing a logical "<NUM>"). Following the "<NUM>" state of <FIG>, a voltage pulse (e.g., SFQ pulse) corresponding to the initial falling edge of the read enable phase pulse flips the directions of currents <NUM>, <NUM> in <FIG>. Then, a subsequent voltage pulse (e.g., SFQ pulse) of opposite polarity corresponding to the rising edge of the read enable phase pulse again flips the directions of the same currents, placing the circuit back in the original state of <FIG> in <FIG>.

<FIG> show the effect on the circuit of a read enable phase pulse transit (i.e., absent a data input pulse contemporaneous to it in the same clock cycle) starting from the "<NUM>" memory state of the circuit (i.e., when the illustrated unit cell is storing a logical "<NUM>"). This memory state can be noted from the difference in current directions <NUM>, <NUM> in <FIG> versus their counterparts in <FIG>. Following the "<NUM>" state of <FIG>, a voltage pulse (e.g., SFQ pulse) corresponding to the initial falling edge of the read enable phase pulse has no effect on the directions of currents in <FIG>, because the pulse is absorbed by the respective escape junction (e.g., <NUM> in <FIG>). Then, a subsequent voltage pulse (e.g., SFQ pulse) of opposite polarity corresponding to the rising edge of the read enable phase pulse again has no effect on the directions of the currents, such that the circuit remains in the original state of <FIG> in both <FIG>.

<FIG> show the effect on the circuit of a write enable phase pulse starting from the "<NUM>" memory state of the circuit, without a contemporaneous phase pulse transmitted on the data input line, effectively writing a "<NUM>" to a memory unit cell that is already of state "<NUM>". Following the "<NUM>" state of <FIG>, a voltage pulse (e.g., SFQ pulse) corresponding to the initial rising edge of the write enable phase pulse flips the directions of currents <NUM>, <NUM> in <FIG>. Then, a subsequent voltage pulse (e.g., SFQ pulse) of opposite polarity corresponding to the falling edge of the write enable phase pulse again flips the directions of the same currents, placing the circuit back in the original state of <FIG> in <FIG>. This sequence thus resembles that of <FIG> in that the current directions, indicative of the "<NUM>" memory state, start and end in the same configuration, but the sequences differ in which currents flip and flop direction during the sequence.

<FIG> show the effect on the circuit of a write enable phase pulse starting from the "<NUM>" memory state of the circuit, without a contemporaneous phase pulse transmitted on the data input line, effectively writing a "<NUM>" to the memory unit cell. Following the "<NUM>" state of <FIG>, a voltage pulse (e.g., SFQ pulse) corresponding to the initial rising edge of the write enable phase pulse has no effect on the directions of currents in <FIG>, because the pulse is absorbed by the respective escape junction (e.g., <NUM> in <FIG>). Josephson junction <NUM> cannot be triggered by this rising edge because it would effectively be triggering Josephson junction <NUM> the wrong way. Then, a subsequent voltage pulse (e.g., SFQ pulse) of opposite polarity corresponding to the falling edge of the write enable phase pulse triggers Josephson junction <NUM> and flips directions of currents on the directions of currents <NUM>, <NUM>, such that the circuit returns to the "<NUM>" memory state illustrated in <FIG> and <FIG>.

<FIG> show the effect on the circuit of a write enable phase pulse starting from the "<NUM>" memory state of the circuit, with a contemporaneous asserted phase pulse transmitted on the data input line, effectively writing a "<NUM>" to the memory unit cell. Following the "<NUM>" state of <FIG>, a voltage pulse (e.g., SFQ pulse) corresponding to the initial rising edge of the write enable phase pulse triggers Josephson junction <NUM>, flipping currents as shown in <FIG>. Then, in <FIG>, a voltage pulse (e.g., SFQ pulse) corresponding to the initial rising edge of the data input phase pulse triggers Josephson junction <NUM>, flipping currents differently such that the configuration of <FIG> differs from both that of <FIG> and that of <FIG>. At this point, as shown in <FIG>, a voltage pulse corresponding to the falling edge of the write enable phase pulse is not able to untrigger Josephson junction <NUM>. It may be observed here that the two currents flowing through Josephson junction <NUM> are opposite in direction. This is insufficient to untrigger Josephson junction <NUM>. If it were to untrigger, this would result in all three of the currents flowing in the counter-clockwise direction, which is a disallowed circuit condition. Instead, the voltage pulse corresponding to the falling edge of the write enable phase pulse causes the respective escape junction (e.g., <NUM> in <FIG>) to trigger in <FIG>. Then, the voltage pulse corresponding to the falling edge of the data input phase pulse causes Josephson junction <NUM> to untrigger in <FIG>. It may be noted by the configuration of current directions that the "<NUM>" state of <FIG> and <FIG> has been achieved in <FIG>.

<FIG> show the effect on the circuit of a write enable phase pulse starting from the "<NUM>" memory state of the circuit, with a contemporaneous asserted phase pulse transmitted on the data input line, effectively writing a "<NUM>" to the memory unit cell that is already of state "<NUM>". Following the "<NUM>" state of <FIG>, a voltage pulse (e.g., SFQ pulse) corresponding to the initial rising edge of the write enable phase pulse cannot trigger Josephson junction <NUM>, and so triggers respective escape junction (e.g., <NUM> in <FIG>), with the result that no currents are flipped in <FIG>. Then, in <FIG>, a voltage pulse (e.g., SFQ pulse) corresponding to the initial rising edge of the data input phase pulse triggers Josephson junction <NUM>, temporarily changing the current configuration by flipping two currents. At this point, as shown in <FIG>, a voltage pulse corresponding to the falling edge of the write enable phase pulse is also not able to trigger Josephson junction <NUM>, for the reason discussed previously with respect to <FIG>. Instead, the voltage pulse corresponding to the falling edge of the write enable phase pulse causes the respective escape junction (e.g., <NUM> in <FIG>) to untrigger in <FIG>. Then, the voltage pulse corresponding to the falling edge of the data input phase pulse causes Josephson junction <NUM> to untrigger in <FIG>, effectively placing the current configuration the same as it was before the rising edge of the data input phase pulse. Thus, the "<NUM>" state is maintained at the end of the sequence.

<FIG> illustrate the "<NUM>" state half-select condition, i.e., the effect on the circuit of a data input phase pulse without a contemporaneous phase pulse transmitted on the write enable line, in this case when the circuit is starting from the "<NUM>" state. In memory design, it can be important that memory unit cells can tolerate signals bypassing them (on the data input line, for instance) which signals are on their way to x-y addressing some other unit cell in the memory fabric, without such signals affecting a memory unit cell to which it is not addressed. Following the "<NUM>" state of <FIG>, a voltage pulse (e.g., SFQ pulse) corresponding to the initial rising edge of the data input phase pulse has no effect on the directions of currents in <FIG>, because the pulse is absorbed by the respective escape junction (e.g., <NUM> in <FIG>). Josephson junction <NUM> cannot be triggered by this rising edge because it would effectively be triggering Josephson junction <NUM> the wrong way. Then, a subsequent voltage pulse (e.g., SFQ pulse) of opposite polarity corresponding to the falling edge of the data input phase pulse untriggers the same escape junction. Accordingly, the memory unit cell circuit experiences no change in current direction configuration and thus no change in memory state, which is the desired behavior of the half-select condition. The circuit remains in the "<NUM>" memory state.

<FIG> illustrate the "<NUM>" state half-select condition, i.e., the effect on the circuit of a data input phase pulse without a contemporaneous phase pulse transmitted on the write enable line, in this case when the circuit is starting from the "<NUM>" state (<FIG>). In contrast to the "<NUM>" state half-select condition, in the "<NUM>" state half-select, the rising edge of the data input phase pulse does cause Josephson junction <NUM> to trigger (<FIG>), disrupting the current direction configuration by changing the directions of currents <NUM>, <NUM>, but the falling edge of the data input phase pulse causes Josephson junction <NUM> to subsequently untrigger, placing the circuit back in the state (<FIG>). The "<NUM>" state half-selection condition is thus only a transient disturbance to the circuit state, lasting the duration of the data input phase pulse.

The initialization protocols of <FIG> show a way to initialize all cells to a known and valid state, starting from an unknown phase-initialization (±π) of each π Josephson junction. All of the states illustrated in <FIG> involve one counter-clockwise loop current and two clockwise loop currents. In an alternate chirality, the individual circuit states can involve two counter-clockwise loop currents and one clockwise loop current. Triggering Josephson junctions in the illustrated circuits cannot change the initial-state chirality, because each such triggering changes two current directions, not just one. Initialization of the π Josephson junctions to three clockwise or three counter-clockwise states would result in a non-functional cell, but these are not among the low-energy states so it is expected they will not occur during initialization. However, if the circuit initializes with one clockwise and two counter-clockwise loop currents, the circuit will not operate properly. Each cell will have the loop currents illustrated in <FIG> after a write "<NUM>" operation. In other words, only one of the two possible initial-state chiralities is functional. Therefore, circuit components can be provided to the unit cell sub-circuit produce operable-chirality initialization. As shown in <FIG>, for example, an initialization Josephson junction JINIT and a control line <NUM>, inductively coupled to the sub-circuit via an inductor in the same arm of the sub-circuit as the initialization Josephson junction, can be provided to reverse the counter-clockwise current <NUM> to a clockwise current <NUM> (<FIG>) in an initialization procedure that ramps a control current provided through the control line <NUM> up to a prescribed value and then back to zero. Resultantly, each memory unit cell can be initialized to a known state of the operable chirality. For example, the memory array can be initialized to a "<NUM>" state for every unit cell in the array, followed by activation of the control line <NUM> for every unit cell, ensuring that every unit cell in the array is then in a "<NUM>" state of the valid chirality (compare <FIG>, both showing the "<NUM>" state).

<FIG> details the read path <NUM>, with six unit cell stages <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> illustrated as an example. Only the part of each unit cell relevant to the read operation is illustrated; the remainder of the unit cell is omitted for clarity. Effectively, as shown the bit line <NUM> is coupled only to the Rm junction in each unit cell illustrated. Stages <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> all have clockwise currents through the illustrated arm of the respective unit cell; only stage <NUM> has a counter-clockwise current through its arm. In the illustrated example, stage <NUM> ("ROW <NUM>") is the stage currently being read. The cells that are not being read are guaranteed, irrespective of their internal state, to have clockwise currents (as shown), such that a pilot phase pulse propagating down the bit line <NUM> can pass through each of them, whereas the cell being read, if in the "<NUM>" state, will have a counter-clockwise current (as shown for stage <NUM>), and if in the "<NUM>" state, will have a clockwise current. Consequently, a pilot phase pulse will be blocked at stage <NUM>, which is in the "<NUM>" state as illustrated.

Thus, NOR logic is used, wherein the pilot phase pulse is conditionally blocked at the cell being read, dependent on the state of that cell. As with the write lines, the bit line <NUM> (i.e., the read line) can use small-value inductors L, resulting in high density and speed. The readout circuit of the array can be a wide-input NOR gate. A first voltage pulse of the pilot phase pulse input at B is conditionally blocked at each input, as shown by the potential diagram of <FIG> (showing the potential only for one stage, e.g., stage <NUM>, "ROW1"). If the direction of current in a stage in <FIG> is clockwise, the regular transmission line dynamics permit this voltage pulse to get over the potential energy hump <NUM> and end up back where it started, energetically speaking, as the voltage pulse rolls through the transmission line <NUM>. If, on the other hand, the direction of current in a stage in <FIG> is counter-clockwise, plot <NUM> shows that it is highly energetically unfavorable or impossible to trigger the Josephson junction in the direction that would be required for further propagation of the voltage pulse down the bit line <NUM>. This causes the voltage pulse either to reflect or to be stored and annihilated by its counterpart opposite-polarity voltage pulse half a clock cycle later when RQL data encoding is used.

<FIG> illustrates an example linear implementation <NUM> of the unit cell sub-circuit <NUM> that, as compared to the circular implementation <NUM> of the sub-circuit <NUM> illustrated in <FIG>, has better initialization properties at the expense of unequal potential energy levels for the different states (absent mutual inductance configuration among inductors, as discussed below). In linear sub-circuit implementation <NUM>, a linear array always initializes to the correct state simply by exercising the write and read functions, irrespective of the initial state of the π Josephson junctions (i.e., there is no issue of the circuit initializing to the incorrect chirality, as described with regard to <FIG>). However, in linear implementation <NUM>, the potential energy levels of the different states are not equal (cf. <FIG>), unless mutual inductance (e.g., mutual inductance <NUM>) is introduced between adjacent pairs of inductors. Providing mutual inductance between each pair of inductors can achieve full degeneracy. Mutual inductance <NUM> only between one pair of inductors can be provided as illustrated to achieve degeneracy with respect to the bit line pulse, which is the most important degeneracy to achieve. Also, in linear implementation <NUM> as compared to circular implementation <NUM>, it is the data output signal (here labeled b_m), not the read enable signal (here labeled r), that is the mirrored signal, meaning that appropriate polarity inversion can be provided at the ends of the bit line on the periphery of a memory array composed of unit cells implemented as linear implementation <NUM>, rather than on the ends of the read enable line.

In implementation <NUM> of <FIG>, every π Josephson junction has a Josephson junction in series with it. Two of these Josephson junctions are shown (Josephson junction <NUM> is in series with π Josephson junction <NUM>;, Josephson junction <NUM> is in series with π Josephson junction <NUM>), whereas the other two (paired with π Josephson junctions <NUM>, <NUM>) are not shown in <FIG> but are the respective escape junctions (e.g., <NUM>, <NUM> in <FIG>). The series order of a Josephson junction in series with a π Josephson junction can be reversed without material change to the operation of the circuit. A Josephson junction in series with a π Josephson junction can be fabricated as a single device. The initial current directions (CW or CCW) are as illustrated.

<FIG> illustrates another example implementation <NUM> of the unit cell sub-circuit <NUM> that, as compared to the implementations <NUM> and <NUM>, uses only three π Josephson junctions <NUM>, <NUM>, <NUM> instead of four. As with implementation <NUM>, mutual inductances <NUM>, <NUM> can be provided to promote equal potential energy levels. An initialization current can be provided to a transformer coupling to inductor Led as part of an initialization protocol that also includes first writing a "<NUM>" to the memory unit cell. As with implementation <NUM>, the read enable signal is the mirrored signal. As illustrated, Josephson junction <NUM> is in series with, and can be fabricated as the same device as, π Josephson junction <NUM>. Similarly, Josephson junction <NUM> is in series with, and can be fabricated as the same device as, π Josephson junction <NUM>. A Josephson junction <NUM> can be coupled between the write enable node e and ground. A Josephson junction <NUM> can be coupled between the data input node d and ground. The current directions (CW or CCW) following initialization are as illustrated.

<FIG> illustrates another example linear implementation <NUM> of the unit cell sub-circuit <NUM> that includes π Josephson junctions <NUM>, <NUM>, <NUM>, <NUM> and Josephson junctions <NUM>, <NUM>, <NUM>, <NUM>. Mutual inductance <NUM> can be provided to promote equal potential energy levels. An initialization current can be provided to a transformer coupling to inductor Lgd as part of an initialization protocol (a "<NUM>" need not be first written to the unit cell). As with implementation <NUM>, the read enable signal is the mirrored signal. The current directions (CW or CCW) following initialization are as illustrated.

The circuits described herein have good parametric operating margins, low component count, and provide efficiency and cost advantages as compared to other implementations. For the purposes of this description, a π Josephson junction and a Josephson junction are distinct circuit components, and one cannot be interpreted as the other, although, as mentioned above, it is possible to fabricate the two as one physical device.

Claim 1:
A Josephson memory array comprising a plurality of unit cells (<NUM>), each of the plurality of unit cells comprising:
an internal sub-circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprising a plurality of π Josephson junctions (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), and
first, second, third, and fourth quasi-long-Josephson-junction interconnects (E, Rm, D, B), each coupled to the internal sub-circuit at respective first, second, third, and fourth electrical nodes (e, r_m, d, b) of the sub-circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>), the interconnects including:
a write enable line (E) configured to enable writing a binary memory state to the unit cell (<NUM>),
a read enable line (Rm) configured to enable reading the binary memory state from the unit cell (<NUM>),
a data input line (D) configured to provide the binary memory state to the unit cell (<NUM>), and
a bit line (B) configured to read out the binary memory state from the unit cell (<NUM>),
wherein each of the first, second, third, and fourth quasi-long-Josephson-junction interconnects (E, Rm, D, B) is adapted to connect together multiple ones of the plurality of unit cells (<NUM>) in the memory array,
wherein for each of the plurality of unit cells (<NUM>), the electrical node (e) of the sub-circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) to which the write enable line (E) is connected, the electrical node (d) of the sub-circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) to which the data input line (D) is connected, and the electrical node (r_m) of the sub-circuit (<NUM>) to which the read enable line (Rm) is connected are each coupled to ground via a respective Josephson junction (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) in the sub-circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>), and
wherein each of the quasi-long-Josephson-junction interconnects is a Josephson transmission line having connecting inductors (L) of between about one picohenry and ten picrohenries.