Patent Description:
This application relates to the technical field of semiconductor memories, and in particular to a write operation circuit, a semiconductor memory, and a write operation method.

This section is intended to provide background or context for the embodiments of the application defined in the appended claims. Thus, the description of this section is not to be interpreted as prior art for the mere fact of being included in this section.

Semiconductor memories include static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), Read-Only Memory (ROM), flash memory, and so on.

In the DRAM protocol of the Joint Electron Device Engineering Council (JEDEC), there are specific speed and power saving requirements for DRAM. It therefore has become an urgent problem to be solved as to make DRAM more power-saving while also ensuring signal integrity and reliability of data transfer and storage. <CIT> discloses a semiconductor memory apparatus including an input data bus inversion unit, a data input line, a termination unit, a data recovery unit and a memory bank. The input data bus inversion unit determines whether or not to invert a plurality of input data based on an operation mode signal and the plurality of input data and generates a plurality of conversion data. The data input line transmits the plurality of conversion data. The termination unit terminates the data input line in response to the operation mode signal. The data recovery unit receives the plurality of conversion data and generates a plurality of storage data. The memory bank configured to store the plurality of storage data.

In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present application will be easily understood by referring to the accompanying drawings and the following detailed description.

In the drawings, unless otherwise specified, the same reference numerals refer to the same or similar parts or elements throughout the multiple drawings. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict some embodiments according to the present application.

Illustrative embodiments will now be described more fully below in connection with the accompanying drawings. However, these illustrative embodiments may be able to be practiced in a variety of forms. On the contrary, these embodiments are provided so that this application will become comprehensive and complete, and will be able to fully convey the concept of these illustrative embodiments to those having ordinary skill in the art. In these drawings, same reference numerals denote the same or similar parts, and thus they will not be repeatedly detailed.

<FIG> schematically shows a block diagram of a part of the structure of a semiconductor memory according to an embodiment of the present application. As shown in <FIG>, the semiconductor memory <NUM> includes a DQ port <NUM>, a memory bank (bank) <NUM>, and a write operation circuit. The write operation circuit includes a global bus (Global Bus), an inversion flag (identification) signal line, a serial-to-parallel conversion circuit <NUM>, a data determination module <NUM>, a data buffer module (Data Bus Buffer) <NUM>, a data receiving module <NUM>, and a precharge module <NUM>. In an embodiment, the semiconductor memory <NUM> is a DRAM, such as a fourth-generation double-rate synchronous dynamic random access memory (Double Data Rate SDRAM <NUM>, DDR4 for short).

In an example, as shown in <FIG>, a <NUM>-bit first input data DQ<<NUM>:<NUM>> is input from the DQ port <NUM>, so that the data to be written (namely the decoded data) D<<NUM>:<NUM> would be written into the memory bank <NUM> through the write operation circuit. One Active command turns on one unique designated memory bank <NUM>, and the write operation can only be performed on one memory bank <NUM>. In other words, when one of the eight memory banks <NUM> (i.e. Bank<<NUM>:<NUM>>) is operating, the other Banks are not operating. It should be noted, however, that the number of memory banks <NUM>, the number of data bits of each memory bank <NUM>, the number of the DQ ports <NUM> and the number of data bits of the DQ ports <NUM> will not be limited in the embodiment. For example, there may be one DQ port <NUM>, which is used to input a <NUM>-bit first input data; there may also be two DQ ports <NUM>, that is, each DQ port <NUM> is used to input a <NUM>-bit first input data DQ<<NUM>:<NUM>> or DQ<<NUM>:<NUM>>, thus inputting in effect a <NUM>-bit first input data DQ<<NUM>:<NUM>>.

For example, as shown in <FIG>, a write operation is performed on a set of memory banks Bank<<NUM>:<NUM>> by writing the first input data DQ<<NUM>:<NUM>> through the above-mentioned write operation circuit; a write operation is performed on another set of memory banks Bank<<NUM>:<NUM>> by writing the first input data DQ<<NUM>:<NUM>> through the above-mentioned another write operation circuit. Accordingly, among the eight memory banks <NUM> corresponding to DQ<<NUM>:<NUM>> (i.e. Bank<<NUM>:<NUM>>), when only one bank operates, the other banks do not operate.

The semiconductor memory <NUM> has an array structure, and different units may have the same structure. However, because the input data are different, the output data of different units may be different. The following takes one memory bank as an example to introduce the write operation circuit of the embodiment.

As shown in <FIG> and <FIG>, the write operation circuit of the embodiment includes a data determination module <NUM>, which is used to determine, according to the number of high data bits in the input data of the semiconductor memory <NUM>, whether to invert the input data so as to generate inversion flag data and first intermediate data.

The data determination module <NUM> is configured to output the inverted data of the input data as the first intermediate data in the case where the number of high data bits in the input data is greater than the preset value, and set the Flag data to high, and output the original input data as the first intermediate data in the case where the number of high data bits in the input data is less than or equal to the preset value, and set the Flag data to low.

For example, the input data has <NUM> bits. If the number of bits equal to "<NUM>" in the input data is more than half, that is, more than <NUM> bits (e.g., <NUM> bits), then Flag=<NUM>, and the output first intermediate data will be equal to the inverted data of the input data. Otherwise if the number of bits equal to "<NUM>" in the written data is less than half, e.g., if the data bits equal to "<NUM>" have <NUM> bits, then Flag=<NUM>, and the output first intermediate data will be equal to the original input data.

As meant herein, a "high" data bit may mean a data bit that is equal to "<NUM>", while a "low" data bit may be a data bit that is equal to "<NUM>". Data inversion can be understood as changing from "<NUM>" to "<NUM>", or from "<NUM>" to "<NUM>". The inversion of the data line or the signal line may be understood as changing a high level to a low level, or changing a low level to a high level.

In an embodiment, the write operation circuit includes a serial-to-parallel conversion circuit <NUM>. The serial-to-parallel conversion circuit <NUM> is coupled between the DQ port <NUM> and the data determination module <NUM>, and is used to perform serial-to-parallel conversion on the first input data of the DQ port <NUM> so as to generate second input data. For example, the serial-to-parallel conversion circuit <NUM> performs serial-to-parallel conversion on the <NUM>-bit first input data DQ<<NUM>:<NUM>>, thus generating a <NUM>-bit second input data D2'<<NUM>:<NUM>> corresponding to Bank0.

In an embodiment, the second input data D2'< <NUM>:<NUM>> is divided into M sets, the Flag data has M bits, which have one-to-one correspondence relationship with the M sets of second input data, and each set of second input data has N bits, where M and N are integers greater than <NUM>. In the case where the number of high data bits in one input set of second input data is greater than N/<NUM>, the data determination module <NUM> is used for outputting the inverted data of the set of second input data as the corresponding set of first intermediate data, and setting the data bit in the inversion flag data corresponding to the set of second input data to high. In the case where the number of high data bits in one input set of second input data is less than or equal to N/<NUM>, the data determination module is used for outputting the set of second input data as the corresponding set of first intermediate data, and setting the data bit in the inversion flag data corresponding to the set of second input data to low.

For example, the second input data D2'<<NUM>:<NUM>> is divided into <NUM> sets, where each set of second input data has <NUM> bits, and each set of second input data corresponds to one bit of the Flag data. Correspondingly, the Flag data has <NUM> bits, such as Flag<<NUM>:<NUM>>. The first intermediate data D1'<<NUM>:<NUM>> will be divided into <NUM> sets accordingly. Each bit of Flag data corresponds to a set of first intermediate data. For a set of second input data D2'<<NUM>:<NUM>>, if the number of digits equal to "<NUM>" in D2'<<NUM>:<NUM>> is greater than <NUM> bits, then the corresponding Flag<<NUM>>=<NUM>, the set of first intermediate data D1'<<NUM>:<NUM>> that is output is equal to the inverted data of D2'<<NUM>:<NUM>>. If the number of bits equal to "<NUM>" in the second input data is less than or equal to <NUM> bits, then the corresponding Flag< <NUM> >=<NUM>, and the set of first intermediate data D1'<<NUM>:<NUM>> that is output is just D2'<<NUM>: <NUM>>. Similarly, for a set of second input data D2'<<NUM>:<NUM>>, if the number of bits equal to "<NUM>" in D2'<<NUM>:<NUM>> is greater than <NUM>, then the corresponding Flag<<NUM>>=<NUM>, the set of first intermediate data D1'<<NUM>:<NUM>> that is output is equal to the inverted data of D2'<<NUM>:<NUM>>. Otherwise if the number of bits equal to "<NUM>" in the second input data is less than or equal to <NUM> bits, then the corresponding Flag<<NUM>>=<NUM>, and the output set of first intermediate data D1'<<NUM>:<NUM>> is just D2'<<NUM>: <NUM>>. For a set of second input data D2'<<NUM>:<NUM>>, if the number of bits equal to "<NUM>" in D2'<<NUM>:<NUM>> is greater than <NUM>, then the corresponding Flag<<NUM>>=<NUM>, the output set of first intermediate data D1'<<NUM>:<NUM>> is equal to the inverted data of D2'<<NUM>:<NUM>>. Otherwise if the number of bits equal to "<NUM>" in the second input data is less than or equal to <NUM> bits, then the corresponding Flag<<NUM>>=<NUM>, and the output set of first intermediate data D1'<<NUM>:<NUM>> will just be D2'<<NUM>: <NUM>>. Therefore, in the first intermediate data D1'<<NUM>:<NUM>>, there are relatively more data bits that are "<NUM>".

Further, the semiconductor memory <NUM> of the embodiment further includes a data buffer module <NUM> and a precharge module <NUM>. <FIG> schematically shows a circuit diagram (corresponding to one memory bank <NUM>) of a data buffer module <NUM> according to an embodiment of the present application. <FIG> schematically shows a circuit diagram (corresponding to <NUM> memory banks <NUM>) of a data buffer module <NUM> according to an embodiment of the present application.

As shown in <FIG>, the data buffer module <NUM> includes a plurality of PMOS (Positive Channel Metal Oxide Semiconductor) transistors <NUM> and a plurality of first inverters <NUM>. The gate of the PMOS transistor <NUM> is coupled to the data determination module <NUM> through the first inverter <NUM>, and the drain of the PMOS transistor <NUM> is coupled to the global bus. The first inverter <NUM> is used to perform an inversion operation on the first intermediate data to generate the second intermediate data, so that the data buffer module <NUM> further determines whether to invert the global bus according to the second intermediate data. Since there are relatively more data bits of "<NUM>" in the first intermediate data, there are relatively more data bits of "<NUM>" in the second intermediate data.

The precharge module <NUM> is coupled to the precharge signal line (Precharge), and is used to set the initial state of the global bus to low. That is to say, in the embodiment, the semiconductor memory <NUM> adopts a precharge pull-down (Low) global bus transfer structure. In particular, the precharge module <NUM> includes a plurality of NMOS (Negative Channel Metal Oxide Semiconductor) transistors <NUM> and a plurality of hold circuits <NUM>. The gate of the NMOS transistor <NUM> is coupled to the precharge signal line, and the drain of the NMOS transistor <NUM> is coupled to the global bus. The input and output ends of the hold circuit <NUM> are coupled to the global bus, thereby forming a positive feedback circuit.

The Precharge serves the function of setting the initial state of each global bus to low. The specific process includes generating a pull-down pulse (pulse, lasting about 2ns) by the Precharge signal, thus pulling down the corresponding global bus for a while. The hold circuit <NUM> then forms a positive feedback and locks the global bus at low level, but the ability of the hold circuit <NUM> to pull up and pull down current is relatively weak. When a global bus needs to change to a high level, the data line corresponding to the global bus (that is, the data line coupled to the gate of the PMOS transistor <NUM> corresponding to this global bus) is pulled down for a bit (also a pulse, lasting about 2ns), so that the corresponding PMOS transistor <NUM> will pull up the global bus for a while (the pull-up capability is greater than the pull-down capability of the hold circuit <NUM>). Then the global bus will be locked to a high level through positive feedback to complete the inversion action of the data line. Since there are relatively more data bits "<NUM>" in the second intermediate data, relatively fewer inversion actions are required. Therefore, the IDD4W (write current) of the semiconductor memory will be reduced, thereby reducing the power consumption of the semiconductor memory.

In an example, there are multiple global buses, which are divided into M (M is an integer greater than <NUM>) sets, and each global bus transfers one bit of the global bus data. For example, there are <NUM> global buses, where global bus<<NUM>> transfers global bus data D'<<NUM>>, global bus<<NUM>> transfers global bus data D'<<NUM>>;. , global bus<<NUM>> transfers global bus data D'<<NUM>>. The <NUM> global buses are divided into <NUM> sets.

In one example, each bit of Flag data corresponds to a set of global bus data. Correspondingly, there are <NUM> Flag signal lines, and the Flag data has <NUM> bits, such as Flag<<NUM>:<NUM>>. Each Flag signal line transfers <NUM> bit of Flag data. For example, Flag signal line <<NUM>> transfers Flag data Flag<<NUM>>, and corresponds to the global bus data D"<<NUM>:<NUM>>, indicating whether D'<<NUM>:<NUM>> is the inverted data of the second intermediate data. The Flag signal line <<NUM>> transfers Flag data Flag<<NUM>>, and corresponds to the global bus data D'<<NUM>:<NUM>>, indicating whether D'<<NUM>:<NUM>> is the inverted data of the second intermediate data, and so on and so forth. , until the Flag signal line <<NUM>> transfers Flag data Flag< <NUM>>, and corresponds to the global bus data D'<<NUM>:<NUM>>, indicating whether D'<<NUM>:<NUM>> is the inverted data of the second intermediate data.

Since the second intermediate data is the inverted data of the first intermediate data D1'<<NUM>:<NUM>>, when Flag<<NUM>>=<NUM>, the global bus data D'< <NUM>:<NUM>>=D1'< <NUM>:<NUM> >. When Flag<<NUM>>=<NUM>, the global bus data D'<<NUM>:<NUM>> is the inverted data of D1'<<NUM>:<NUM>>. Similarly, when Flag<<NUM>>=<NUM>, D'<<NUM>:<NUM> >=D1'<<NUM>:<NUM>>; when Flag<<NUM>>=<NUM>, D'<<NUM>:<NUM>> is the inverted data of D1'<<NUM>: <NUM>>. When Flag<<NUM>>=<NUM>, D'<<NUM>:<NUM>>=D1'<<NUM>:<NUM>>; when Flag<<NUM>>=<NUM>, D'<<NUM>:<NUM>> is the inverted data of D1'<<NUM>:<NUM>>.

Therefore, in the global bus data D'<<NUM>:<NUM>> transferred on the global bus, there are more data bits that are "<NUM>". Accordingly, in the semiconductor memory <NUM> shown in <FIG>, the <NUM>-bit global bus data (including the <NUM>-bit global bus data corresponding to DQ<<NUM>:<NUM>> and the <NUM>-bit global bus data corresponding to DQ<<NUM>:<NUM>>), there are relatively more data bits of "<NUM>".

In an embodiment, as shown in <FIG>, the data determination module <NUM> includes a data determination unit <NUM> and a data selector <NUM>.

The input end of the data determination unit <NUM> is coupled to the serial-to-parallel conversion circuit <NUM>, and the output end of the data determination unit <NUM> is coupled to the Flag signal line, and is further coupled to the input end of the data selector <NUM>. The data determination unit <NUM> is configured to set the Flag data to high in the case where the number of high data bits in the second input data is greater than the preset value, and set the Flag data to low in the case where the number of high data bits in the second input data is less than or equal to the preset value.

The input end of the data selector <NUM> is coupled to the data determination unit <NUM> for receiving the second input data through the data determination unit <NUM>. The input end of the data selector <NUM> also receives the Flag data through the Flag signal line, and the output end of the data selector <NUM> is coupled to the input end of the first inverter <NUM>. The data selector <NUM> is used to output the inverted data of the second input data as the first intermediate data in the case where the Flag data is high, and use the original second input data as the first intermediate data in the case where the Flag data is high.

In an embodiment, the data selector <NUM> includes a plurality of data selection units <NUM>', where each data selection unit <NUM>' is used to process one bit of Flag data and a set of second input data. For example, there may be <NUM> data selection units <NUM>', corresponding to respective <NUM> sets of second input data and one bit of Flag data.

<FIG> shows an implementation of the data selection unit <NUM>'. As shown in <FIG>, the data selection unit <NUM>' includes a second inverter 232A, a third inverter 232B, a first transmission gate 232C, and a second transmission gate 232D.

The input end of the second inverter 232A receives Flag data through the Flag signal line. The input end of the third inverter 232B is coupled to the data determination unit <NUM> for receiving the second input data from the data determination unit <NUM>. The input end of the first transmission gate 232C is coupled to the output end of the third inverter 232B. The output end of the first transmission gate 232C is coupled to the input end of the first inverter <NUM> for outputting the first intermediate data. The negative control end of the first transmission gate 232C (the upper control end shown in <FIG>) is coupled to the output end of the second inverter 232A. The positive control end of the first transmission gate 232C (the lower control end shown in <FIG>) receives the Flag data through the Flag signal line. The input end of the second transmission gate 232D is coupled to the data determination unit <NUM> for receiving the second input data from the data determination unit <NUM>. The output end of the second transmission gate 232D is coupled to the input end of the first inverter <NUM> for outputting the first intermediate data. The negative control end of the second transmission gate 232D receives the Flag data through the Flag signal line. The positive control end of the second transmission gate 232D is coupled to the output end of the second inverter 232A.

Take Flag<<NUM>> and the second input data D2'<<NUM>:<NUM>> as an example, as shown in <FIG>, when Flag=<NUM>, the first intermediate data D1'<<NUM>:<NUM>> is the inverted data of second input data D2' <<NUM>:<NUM>>. Otherwise when Flag=<NUM>, the first intermediate data D1'<<NUM>:<NUM>> is just the second input data D2'<<NUM>:<NUM>>.

It should be noted that one set of the third inverter 232B, first transmission gate 232C and second transmission gate 232D are used to process one bit of the second input data and output one bit of the corresponding first intermediate data. In other words, corresponding to the <NUM>-bit second input data D2'<<NUM>:<NUM>>, there should also be <NUM> sets of the third inverter 232B, the first transmission gate 232C, and the second transmission gate 232D, thus outputting the <NUM>-bit first intermediate data D1'<<NUM>:<NUM>>.

Thus, when the Flag data is <NUM>, the global bus data D'<<NUM>:<NUM>> is the inverted data of the second input data D2'<<NUM>:<NUM>>. When the Flag data is <NUM>, the global bus data D'<<NUM>:<NUM>> is the original second input data D2'<<NUM>:<NUM>>.

As shown in <FIG>, <FIG> and <FIG>, the write operation circuit in the embodiment further includes a data receiving module <NUM>. The input end of the data receiving module <NUM> is coupled to the global bus and to the inversion flag signal line. The output end of the data receiving module <NUM> is coupled to the memory bank <NUM>. The data receiving module <NUM> is used to determine whether to invert the global bus data (decoding the global bus data) according to the Flag data, and write the decoded data (write data) into the memory bank <NUM>. For example, in the case where the Flag data is high, the inverted data of the global bus data is output as the data to be written; and when the Flag data is low, the original global bus data is output as the data to be written.

As a result, the written data is restored to the input data of the semiconductor memory. Accordingly, the data and functions of the external ports of the semiconductor memory <NUM>, such as the DQ port <NUM> and the DBI port (not shown in the figures), will not be changed.

In an embodiment, the data receiving module <NUM> may include a plurality of data receiving units <NUM>, where each data receiving unit <NUM> is used to process one bit of Flag data and a set of global bus data. For example, there may be <NUM> data receiving units <NUM>, corresponding to respective <NUM> sets of global bus data and one bit of Flag data. <FIG> shows an implementation of the data receiving unit <NUM>.

As shown in <FIG>, the data receiving unit <NUM> includes a fourth inverter <NUM>, a fifth inverter <NUM>, a third transmission gate <NUM>, and a fourth transmission gate <NUM>.

The input end of the fourth inverter <NUM> receives the Flag data through the Flag signal line. The input end of the fifth inverter <NUM> receives the global bus data through the global bus. The input end of the third transmission gate <NUM> is coupled to the output end of the fifth inverter <NUM>. The output end of the third transmission gate <NUM> is coupled to the memory bank <NUM> for outputting data to be written into the memory bank <NUM>. The negative control end of the third transmission gate <NUM> (the upper control end shown in <FIG>) is coupled to the output end of the third inverter <NUM>. The positive control end of the third transmission gate <NUM> receives the Flag data through the Flag signal line. The input end of the fourth transmission gate <NUM> receives the global bus data through the global bus. The output end of the fourth transmission gate <NUM> is coupled to the memory bank <NUM> for outputting data to be written into the memory bank <NUM>. The negative control end (the upper control end shown in <FIG>) of the fourth transmission gate <NUM> receives Flag data through the Flag signal line, and the positive control end (the lower control end shown in <FIG>) of the fourth transmission gate <NUM> is coupled to the output end of the fourth inverter <NUM>.

Take Flag<<NUM>> and global bus data D'<<NUM>:<NUM>> as an example, as shown in <FIG>, when Flag=<NUM>, written data D<<NUM>:<NUM>> is the inverted data of the global bus data D'<<NUM>:<NUM> >. Otherwise when Flag=<NUM>, the written data D<<NUM>:<NUM>> is just the global bus data D'<<NUM>:<NUM>>, that is, D<<NUM>:<NUM>>= D'<<NUM>:<NUM>>.

It should be noted that one set of the fifth inverter <NUM>, third transmission gate <NUM>, and fourth transmission gate <NUM> are used to process one bit of global bus data and output one bit of corresponding written data. In other words, corresponding to <NUM>-bit global bus data D'<<NUM>:<NUM>>, there should also be eight sets of the fifth inverter <NUM>, the third transmission gate <NUM>, and the fourth transmission gate <NUM>, thus then outputting the <NUM>-bit written data D<<NUM>:<NUM>>.

According to the semiconductor memory <NUM> of the embodiment, in the process of writing data (DQ<<NUM>:<NUM>>=<<NUM>>; DQ<<NUM>:<NUM>>=<<NUM>>) to the semiconductor memory <NUM>, the global bus data is <NUM> bits, so if there is a need to invert <NUM>-bit global bus data, it will turn out that only the <NUM>-bit Flag data will be inverted, so that the IDD4W will be greatly compressed.

The semiconductor memory <NUM> of the embodiment further includes other structures such as a sense amplifier, a precharge circuit, etc. in practical applications, which are all existing technologies and so are not repeatedly detailed in the embodiment for brevity.

<FIG> schematically shows a flowchart of a write operation method according to an embodiment of the present application. This writing operation method can be applied to the semiconductor memory <NUM> described above. As shown in <FIG>, the write operation method may include the following operations:.

In an embodiment, operation S902 may include: performing serial-to-parallel conversion on the first input data of the DQ port to generate the second input data; and determining whether or not to invert the second input data according to the number of high data bits in the second input data, so as to generate the inversion flag data and the first intermediate data.

In an embodiment, the operation of determining whether or not to invert the second input data according to the number of high data bits in the second input data, so as to generate the inversion flag data and the first intermediate data include: dividing the second input data into M sets, where each set of second input data has N bits; in the case where the number of high data bits in one input set of second input data is greater than N/<NUM>, outputting the inverted data of the set of second input data as the corresponding set of first intermediate data, and setting the data bit in the inversion flag data corresponding to the set of second input data to high; and in the case where the number of high data bits in one input set of second input data is less than or equal to N/<NUM>, outputting the set of second input data as the corresponding set of first intermediate data, and setting the data bit in the inversion flag data corresponding to the set of second input data to low.

The write operation circuit provided by the embodiment of the present application can be applied to a semiconductor memory with a global bus transfer structure of the precharge pull-down type, which can reduce the number of internal global bus inversions before data is written into the memory block, thus greatly compressing the current and reducing the power consumption.

As used herein, references to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. are intended to mean that specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. Furthermore, the described specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner. In addition, those having ordinary skill in the art may be able to combine the different embodiments or examples and the features of the different embodiments or examples described in this specification, in the premise that no contradiction or conflict is present.

Furthermore, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. However, those having ordinary skill in the art will be able to realize that the technical solutions of the present application can be practiced without the presence of one or more of the specific details, or other methods, components, materials, devices, steps, etc. can be used. In other cases, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of the present application.

As used herein, terms "first", "second", or the like are merely used for illustrative purposes, and shall not be construed as indicating relative importance or implicitly indicating the number of technical features specified. Thus, the features defined by "first" and "second" may explicitly or implicitly include one or more of such features. As used herein, terms "multiple" or "a plurality of" means two or more, unless otherwise specifically defined.

Claim 1:
A write operation circuit applied to a semiconductor memory (<NUM>), the write operation circuit comprises:
a data determination module (<NUM>), configured to determine, according to a number of high data bits in input data of the semiconductor memory (<NUM>), whether to invert the input data to generate inversion flag data and first intermediate data,
characterized in that, the write operation circuit further comprises:
a data buffer module (<NUM>), comprising a plurality of P-channel Metal Oxide Semiconductor, PMOS, transistors (<NUM>) and a plurality of first inverters (<NUM>), wherein the plurality of first inverters (<NUM>) are configured to perform an inversion operation on the first intermediate data to generate a second intermediate data, a gate of each of the plurality of PMOS transistors (<NUM>) is coupled to the data determination module (<NUM>) through a respective first inverter (<NUM>) and is configured to receive the second intermediate data, and a drain of each of the plurality of PMOS transistors (<NUM>) is coupled to a global bus, wherein the data buffer module (<NUM>) is configured to determine whether to invert the global bus according to the second intermediate data;
a data receiving module (<NUM>) coupled to a memory bank, wherein the data receiving module (<NUM>) is configured to receive a global bus data on the global bus, receive the inversion flag data through an inversion flag signal line, decode the global bus data according to the inversion flag data, and write a decoded data into the memory bank of the semiconductor memory (<NUM>), wherein the decoding comprises determining whether to invert the global bus data; and
a precharge module (<NUM>), coupled to a precharge signal line and configured to set an initial state of the global bus to low,
wherein the data determination module (<NUM>) is specifically configured to: output inverted data of the input data as the first intermediate data in a case where the number of high data bits in the input data is greater than a preset value, and set the inversion flag data to high; and output the original input data as the first intermediate data in a case where the number of high data bits in the input data is less than or equal to the preset value, and set the inversion flag data to low.