Patent Description:
In large quantum computing processors nearest neighbor qubits are coupled together in order to generate the qubit-qubit interactions involved with performing quantum gates. When the interactions are always on, unintentional coherent rotations and/or coherent qubit errors occur on spectator qubits (e.g., adjacent qubits) that result in gate errors during quantum computations. Such coherent rotations and/or coherent qubit errors limit qubit performance, and are currently preventing the advancement of quantum computing processors. The coupling between adjacent qubits is a major source of coherent qubit errors; in particular ZZ errors.

Some prior art technologies attempt to eliminate such coherent rotations and/or coherent qubit errors (e.g., ZZ errors) by coupling a tunable coupler to qubits used to perform a quantum gate. A problem with such prior art technologies is that the tunable coupler is designed to operate at a resonant frequency that is above that of the qubits. With a resonant frequency that is above that of the qubits, the ZZ turn on is small, and it becomes more difficult to achieve a fast gate for a broad range of detuning.

<NPL>, , arXiv. org discloses four coupled qubits that can operate as a quantum gate, where two qubits control the operation on two target qubits (a four-qubit gate). This configuration can implement four different controlled two-qubit gates: two different entangling swap and phase operations, a phase operation distinguishing states of different parity, and the identity operation (idle quantum gate), where the choice of gate is set by the state of the control qubits. The device exploits quantum interference to control the operation on the target qubits by coupling them to each other via the control qubits.

The invention is defined in the appended independent claims. Preferred embodiments are defined in the appended dependent claims.

One or more embodiments are now described with reference to the drawings, wherein like referenced numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of the one or more embodiments.

Quantum computing is generally the use of quantum-mechanical phenomena for the purpose of performing computing and information processing functions. Quantum computing can be viewed in contrast to classical computing, which generally operates on binary values with transistors. That is, while classical computers can operate on bit values that are either <NUM> or <NUM>, quantum computers operate on quantum bits (qubits) that comprise superpositions of both <NUM> and <NUM>, can entangle multiple quantum bits, and use interference.

Given the problems described above with prior art technologies, the present disclosure can be implemented to produce a solution to these problems in the form of devices and/or computer-implemented methods that can facilitate a quantum gate (e.g., a controlled phase (Cphase) gate) between a first qubit and a second qubit using a quantum coupler device comprising: a tunable coupler coupled between the first qubit and the second qubit; and a capacitor device coupled between the first qubit and the second qubit, where the capacitor device generates a coupling that is opposite in sign to a coupling from the tunable coupler based on a resonant frequency of the tunable coupler being smaller than a resonant frequency of both the first qubit and the second qubit. An advantage of such devices and/or computer-implemented methods is that they can be implemented to improve the speed of a quantum gate (e.g., reduce the time it takes to complete an operation on a qubit).

In some embodiments, the present disclosure can be implemented to produce a solution to the problems described above in the form of devices and/or computer-implemented methods that can facilitate a quantum gate (e.g., a Cphase gate) between the first qubit and the second qubit using the quantum coupler device described above, where the tunable coupler is configured to control the first coupling and the capacitor device is configured to provide the second coupling to eliminate coherent rotations between the first qubit and the second qubit. An advantage of such devices and/or computer-implemented methods is that they can be implemented to turn off the coupling between the first qubit and the second qubit, thereby eliminating coherent rotations and/or coherent qubit errors on the first qubit and/or the second qubit that cause gate errors during quantum computations.

It will be understood that when an element is referred to as being "coupled" to another element, it can describe one or more different types of coupling including, but not limited to, communicative coupling, electrical coupling, electromagnetic coupling, operative coupling, optical coupling, physical coupling, thermal coupling, and/or another type of coupling. It will also be understood that the following terms referenced herein are be defined as follows:.

<FIG> illustrates a circuit schematic of an example, non-limiting device <NUM> that can facilitate a quantum gate between qubits using a tunable coupler and a capacitor device in accordance with one or more embodiments described herein. Device <NUM> can comprise a semiconducting and/or a superconducting device that can be implemented in a quantum device. For example, device <NUM> can comprise an integrated semiconducting and/or superconducting circuit (e.g., a quantum circuit) that can be implemented in a quantum device such as, for instance, quantum hardware, a quantum processor, a quantum computer, and/or another quantum device. Device <NUM> can comprise a semiconducting and/or a superconducting device such as, for instance, a quantum coupler device and/or a tunable quantum coupler device that can be implemented in such a quantum device defined above.

As illustrated by the example embodiment depicted in <FIG>, device <NUM> comprises a tunable coupler <NUM> (denoted as Coupler Qubit in <FIG> and as Coupler Qubit <NUM> in <FIG>) that is coupled between terminals 104a and 104b of a same polarity (e.g., positive (+) or negative (-)) of a first qubit 106a (denoted as Q1 in <FIG>) and a second qubit 106b (denoted as Q2 in <FIG>). Tunable coupler <NUM> illustrated in the example embodiment depicted in <FIG> can comprise a superconducting quantum interference device (SQUID) <NUM> (referred to herein as SQUID <NUM>). In the example embodiment depicted in <FIG>, SQUID <NUM> can comprise two Josephson Junctions 120a, 120b (each denoted as an X in <FIG>) and a capacitor 122a. In various embodiments, SQUID <NUM> can be used to control the tunability of tunable coupler <NUM> as described herein (e.g., by applying a magnetic flux threading through SQUID <NUM>). First qubit 106a and second qubit 106b illustrated in the example embodiment depicted in <FIG> can respectively comprise a Josephson Junction 120c and 120d (each denoted as an X in <FIG>) and a capacitor 122b and 122c.

As illustrated by the example embodiment depicted in <FIG>, tunable coupler <NUM> is coupled between terminals 104a and 104b of a same polarity (e.g., positive (+) or negative (-)) of first qubit 106a and second qubit 106b via capacitive couplings represented visually in <FIG> as capacitor 108a and capacitor 108b, respectively. Tunable coupler <NUM> can comprise a tunable coupler including, but not limited to, a flux tunable coupler, a tunable coupler qubit, a flux tunable coupler qubit, a tunable qubit, a tunable bus, a flux tunable qubit bus, and/or another tunable coupler. First qubit 106a and/or second qubit 106b can comprise a qubit including, but not limited to, a fixed frequency qubit, a tunable qubit, a transmon qubit, a fixed frequency transmon qubit, a tunable transmon qubit, and/or another qubit.

As illustrated by the example embodiment depicted in <FIG>, device <NUM> further comprises a capacitor device <NUM> (denoted as Bypass Capacitor in <FIG> and as Bypass Capacitor <NUM> in <FIG>) that is coupled to terminals 104a and 104c of an opposite polarity (e.g., positive (+) and negative (-)) of first qubit 106a and second qubit 106b. As illustrated by the example embodiment depicted in <FIG>, capacitor device <NUM> can comprise a first terminal 112a and a second terminal 112b that can be cross coupled between first qubit 106a and second qubit 106b, where tunable coupler <NUM> can be directly coupled between first qubit 106a and second qubit 106b. For example, as illustrated in <FIG>, first terminal 112a of capacitor device <NUM> can be coupled to terminal 104a of first qubit 106a and second terminal 112b of capacitor device <NUM> can be coupled to terminal 104c of second qubit 106b. Capacitor device <NUM> can comprise a capacitor device including, but not limited to, a differential capacitor (e.g., a capacitor that connects opposite voltage paddles of a transmon qubit), a bypass capacitor, and/or another capacitor device.

The following describes design rules for capacitor device <NUM>, and/or second capacitor device <NUM> of device <NUM> described below with reference to <FIG>, that can be implemented in accordance with one or more embodiments of the subjected disclosure described herein. It should be appreciated that, in various embodiments, tunable coupler <NUM>, and/or second tunable coupler <NUM> of device <NUM> described below with reference to <FIG>, can yield an exchange interaction (J) between first qubit 106a and second qubit 106b, and/or between second qubit 106b and third qubit <NUM> of device <NUM> described below with reference to <FIG>, that can be approximated by equation (<NUM>) below. In should be further appreciated that, in these embodiments, equation (<NUM>) defined below can by employed to estimate one or more design specifications of capacitor device <NUM> of device <NUM> and/or second capacitor device <NUM> of device <NUM>. <MAT>
where:.

In some embodiments, the bypass capacitance associated with capacitor device <NUM>, and/or second capacitor device <NUM> of device <NUM> described below with reference to <FIG>, can be set (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, an AWG, a VNA, etc.) to produce a qubit to qubit coupling that is opposite is sign of J<NUM>,<NUM>, and greater than or equal to, in magnitude, the magnitude of J<NUM>,<NUM>. For instance, in these embodiments, the bypass capacitance associated with capacitor device <NUM>, and/or second capacitor device <NUM> of device <NUM> described below with reference to <FIG>, can be set (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, an AWG, a VNA, etc.) based on the following device parameters:.

In various embodiments, tunable coupler <NUM> can be configured to generate and/or control a first coupling <NUM> (e.g., a tunable coupling, not illustrated in <FIG>) between first qubit 106a and second qubit 106b. In various embodiments, capacitor device <NUM> can be configured to generate and/or provide a second coupling <NUM> (e.g., a capacitive coupling, not illustrated in <FIG>) that is opposite in sign relative to first coupling <NUM> between first qubit 106a and second qubit 106b, where first coupling <NUM> can be generated and/or controlled by tunable coupler <NUM> as described above. In these embodiments, capacitor device <NUM> can generate and/or provide second coupling <NUM> based on a resonant frequency of tunable coupler <NUM> being smaller than a resonant frequency of both first qubit 106a and second qubit 106b as described below. In these embodiments, capacitor device <NUM> can generate and/or provide second coupling <NUM> based on a resonant frequency of tunable coupler <NUM> being smaller than a resonant frequency of first qubit 106a and small than a resonant frequency of second qubit 106b as described below, where such resonant frequencies of first qubit 106a and second qubit 106b can be the same or different.

In an example embodiment, although not depicted in <FIG>, device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM> can be coupled to a pulse generator device that can be external to device <NUM>. For instance, in an example embodiment, device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM> can be coupled to a pulse generator device including, but not limited to, an arbitrary waveform generator (AWG), a vector network analyzer (VNA), and/or another pulse generator device that can transmit and/or receive pulses (e.g., microwave pulses) to and/or from device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>, where such a pulse generator device can be external to device <NUM>. In this example embodiment, such a pulse generator device (e.g., an AWG, a VNA, etc.) can also be coupled to a computer (e.g., computer <NUM> described below with reference to <FIG>) comprising a memory (e.g., system memory <NUM> described below with reference to <FIG>) that can store instructions thereon (e.g., software, routines, processing threads, etc.) and a processor (e.g., processing unit <NUM> described below with reference to <FIG>) that can execute such instructions that can be stored on the memory. In this example embodiment, such a computer can be employed to operate and/or control (e.g., via processing unit <NUM> executing instructions stored on system memory <NUM>) such a pulse generator device (e.g., an AWG, a VNA, etc.), thereby enabling the pulse generator device to transmit and/or receive pulses (e.g., microwave pulses) to and/or from device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>.

Continuing with the example embodiment described above, based on receiving a pulse from such a pulse generator device (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, etc.), tunable coupler <NUM> can provide a tunable coupling (e.g., first coupling <NUM>) between terminals 104a and 104b of a same polarity (e.g., positive (+) or negative (-)) of first qubit 106a and second qubit 106b. In this example embodiment, based on receiving a pulse from such a pulse generator device (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, etc.), capacitor device <NUM> can provide a capacitive coupling (e.g., second coupling <NUM>) between terminals 104a and 104c of opposite polarity (e.g., positive (+) and negative (-)) of first qubit 106a and second qubit 106b. In this example embodiment, based on receiving a pulse from such a pulse generator device (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, etc.), tunable coupler <NUM> can further tune a resonant frequency associated with the tunable coupling (e.g., first coupling <NUM>), where the capacitive coupling (e.g., second coupling <NUM>) generates a coupling that cancels the tunable coupling when the resonant frequency associated with the tunable coupling is smaller than a resonant frequency of both first qubit 106a and second qubit 106b (e.g., smaller than a resonant frequency of first qubit 106a and smaller than a resonant frequency of second qubit 106b).

Continuing with the example embodiment described above, based on receiving a pulse from such a pulse generator device (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, etc.), device <NUM> can facilitate performing a quantum gate between first qubit 106a and second qubit 106b. For example, as described below with reference to <FIG>, based on receiving a pulse from such a pulse generator device (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, etc.), tunable coupler <NUM> can tune the resonant frequency associated with the tunable coupling (e.g., first coupling <NUM>) such that it moves closer to that of first qubit 106a and second qubit 106b and increase ZZ.

In various embodiments, tunable coupler <NUM> can be configured to control (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, an AWG, a VNA, etc.) first coupling <NUM> and capacitor device <NUM> can be configured to provide (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, an AWG, a VNA, etc.) second coupling <NUM> to eliminate coherent rotations and/or coherent qubit errors (e.g., ZZ errors) on first qubit 106a, second qubit 106b, and/or an adjacent qubit 106c (not illustrated in <FIG>). In these embodiments, such an adjacent qubit 106c can comprise a qubit that can be formed on device <NUM> at a location that is adjacent to first qubit 106a and/or second qubit 106b. In these embodiments, based on receiving pulses (e.g., microwave pulses) from a pulse generator device (e.g., an AWG, a VNA, etc.) as described above (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, etc.), tunable coupler <NUM> and capacitor device <NUM> can decouple first qubit 106a from second qubit 106b and/or adjacent qubit 106c from first qubit 106a and/or second qubit 106b. In these embodiments, tunable coupler <NUM> and capacitor device <NUM> can decouple first qubit 106a from second qubit 106b and/or adjacent qubit 106c from first qubit 106a and/or second qubit 106b based on (e.g., using) the capacitive coupling (e.g., second coupling <NUM>) described above that can cancel the tunable coupling (e.g., first coupling <NUM>) when the resonant frequency associated with the tunable coupling (e.g., the resonant frequency associated with tunable coupler <NUM>) is smaller than the resonant frequency of both first qubit 106a and second qubit 106b (e.g., smaller than a resonant frequency of first qubit 106a and smaller than a resonant frequency of second qubit 106b). In these embodiments, based on such decoupling of first qubit 106a from second qubit 106b and/or adjacent qubit 106c from first qubit 106a and/or second qubit 106b, tunable coupler <NUM> and capacitor device <NUM> can thereby eliminate coherent rotations and/or coherent qubit errors (e.g., ZZ errors) on first qubit 106a, second qubit 106b, and/or adjacent qubit 106c. In these embodiments, based on such elimination of the coherent rotations and/or coherent qubit errors, device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM> can thereby facilitate: reduced quantum gate errors associated with first qubit 106a, second qubit 106b, and/or adjacent qubit 106c; increased speed of a quantum gate comprising first qubit 106a and second qubit 106b; improved performance of a quantum processor comprising device <NUM> (e.g., which can comprise a quantum coupler device); and/or improved fidelity of such a quantum processor comprising device <NUM>.

<FIG> illustrates a circuit schematic of an example, non-limiting device <NUM> that can facilitate a quantum gate between qubits using a tunable coupler and a capacitor device in accordance with one or more embodiments described herein. Device <NUM> can comprise an example, non-limiting alternative embodiment of device <NUM>, where device <NUM> can comprise an additional tunable coupler and an additional capacitor device coupled to second qubit 106b and further coupled to an additional qubit. Repetitive description of like elements and/or processes employed in respective embodiments is omitted for sake of brevity.

As illustrated by the example embodiment depicted in <FIG>, device <NUM> can comprise a second tunable coupler <NUM> (denoted as Coupler Qubit <NUM> in <FIG>) that can be coupled between terminals 204a and 204b of a same polarity (e.g., positive (+) or negative (-)) of second qubit 106b and a third qubit <NUM> (denoted as Q3 in <FIG>). Second tunable coupler <NUM> illustrated in the example embodiment depicted in <FIG> can comprise a superconducting quantum interference device (SQUID) <NUM> (referred to herein as SQUID <NUM>). In the example embodiment depicted in <FIG>, SQUID <NUM> can comprise two Josephson Junctions 222a, 222b (each denoted as an X in <FIG>) and a capacitor 224a. In various embodiments, SQUID <NUM> can be used to control the tunability of second tunable coupler <NUM> as described herein (e.g., by applying a magnetic flux threading through SQUID <NUM>). Third qubit <NUM> illustrated in the example embodiment depicted in <FIG> can comprise a Josephson Junction 222c (denoted as an X in <FIG>) and a capacitor 224b.

As illustrated by the example embodiment depicted in <FIG>, second tunable coupler <NUM> can be coupled between terminals 204a and 204b of a same polarity (e.g., positive (+) or negative (-)) of second qubit 106b and third qubit <NUM> via capacitive couplings represented visually in <FIG> as capacitor 208a and capacitor 208b, respectively. Second tunable coupler <NUM> can comprise a tunable coupler including, but not limited to, a flux tunable coupler, a tunable coupler qubit, a flux tunable coupler qubit, a tunable qubit, a tunable bus, a flux tunable qubit bus, and/or another tunable coupler. Third qubit <NUM> can comprise a qubit including, but not limited to, a fixed frequency qubit, a tunable qubit, a transmon qubit, a fixed frequency transmon qubit, a tunable transmon qubit, and/or another qubit.

As illustrated by the example embodiment depicted in <FIG>, device <NUM> can further comprise a second capacitor device <NUM> (denoted as Bypass Capacitor <NUM> in <FIG>) that can be coupled to terminals 204a and 204c of an opposite polarity (e.g., positive (+) and negative (-)) of second qubit 106b and third qubit <NUM>. As illustrated by the example embodiment depicted in <FIG>, second capacitor device <NUM> can comprise a first terminal 212a and a second terminal 212b that can be cross coupled between second qubit 106b and third qubit <NUM>, where second tunable coupler <NUM> can be directly coupled between second qubit 106b and third qubit <NUM>. For example, as illustrated in <FIG>, first terminal 212a of second capacitor device <NUM> can be coupled to terminal 204a of second qubit 106b and second terminal 212b of second capacitor device <NUM> can be coupled to terminal 204c of third qubit <NUM>. Second capacitor device <NUM> can comprise a capacitor device including, but not limited to, a differential capacitor (e.g., a capacitor that connects opposite voltage paddles of a transmon qubit), a bypass capacitor, and/or another capacitor device.

In various embodiments, second tunable coupler <NUM> can be configured to generate and/or control a third coupling <NUM> (e.g., a second tunable coupling, not illustrated in <FIG>) between second qubit 106b and third qubit <NUM>. In various embodiments, second capacitor device <NUM> can be configured to generate and/or provide a fourth coupling <NUM> (e.g., a second capacitive coupling, not illustrated in <FIG>) that is opposite in sign relative to third coupling <NUM> between second qubit 106b and third qubit <NUM>, where third coupling <NUM> can be generated and/or controlled by second tunable coupler <NUM> as described above. In these embodiments, second capacitor device <NUM> can generate and/or provide fourth coupling <NUM> based on a resonant frequency of second tunable coupler <NUM> being smaller than a resonant frequency of both second qubit 106b and/or third qubit <NUM> as described below (e.g., smaller than a resonant frequency of second qubit 106b and smaller than a resonant frequency of third qubit <NUM>).

In an example embodiment, although not depicted in <FIG>, device <NUM>, tunable coupler <NUM>, capacitor device <NUM>, second tunable coupler <NUM>, and/or second capacitor device <NUM> can be coupled to a pulse generator device (e.g., an AWG, a VNA, etc.) that can be external to device <NUM> and can transmit and/or receive pulses (e.g., microwave pulses) to and/or from device <NUM>, tunable coupler <NUM>, capacitor device <NUM>, second tunable coupler <NUM>, and/or second capacitor device <NUM>. In this example embodiment, such a pulse generator device (e.g., an AWG, a VNA, etc.) can also be coupled to a computer (e.g., computer <NUM> described below with reference to <FIG>) comprising a memory (e.g., system memory <NUM> described below with reference to <FIG>) that can store instructions thereon (e.g., software, routines, processing threads, etc.) and a processor (e.g., processing unit <NUM> described below with reference to <FIG>) that can execute such instructions that can be stored on the memory. In this example embodiment, such a computer can be employed to operate and/or control (e.g., via processing unit <NUM> executing instructions stored on system memory <NUM>) such a pulse generator device (e.g., an AWG, a VNA, etc.), thereby enabling the pulse generator device to transmit and/or receive pulses (e.g., microwave pulses) to and/or from device <NUM>, tunable coupler <NUM>, capacitor device <NUM>, second tunable coupler <NUM>, and/or second capacitor device <NUM>.

Continuing with the example embodiment described above, based on receiving a pulse from such a pulse generator device (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, etc.): tunable coupler <NUM> can provide a tunable coupling (e.g., first coupling <NUM>) between terminals 104a and 104b of a same polarity (e.g., positive (+) or negative (-)) of first qubit 106a and second qubit 106b; and/or second tunable coupler <NUM> can provide a second tunable coupling (e.g., third coupling <NUM>) between terminals 204a and 204b of a same polarity (e.g., positive (+) or negative (-)) of second qubit 106b and third qubit <NUM>. In this example embodiment, based on receiving a pulse from such a pulse generator device (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, etc.): capacitor device <NUM> can provide a capacitive coupling (e.g., second coupling <NUM>) between terminals 104a and 104c of opposite polarity (e.g., positive (+) and negative (-)) of first qubit 106a and second qubit 106b; and/or second capacitor device <NUM> can provide a second capacitive coupling (e.g., fourth coupling <NUM>) between terminals 204a and 204c of opposite polarity (e.g., positive (+) and negative (-)) of second qubit 106b and third qubit <NUM>. In this example embodiment, based on receiving a pulse from such a pulse generator device (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, etc.): tunable coupler <NUM> can further tune a resonant frequency associated with the tunable coupling (e.g., first coupling <NUM>), where the capacitive coupling (e.g., second coupling <NUM>) generates a coupling that cancels the tunable coupling when the resonant frequency associated with the tunable coupling is smaller than a resonant frequency of both first qubit 106a and second qubit 106b (e.g., smaller than a resonant frequency of first qubit 106a and smaller than a resonant frequency of second qubit 106b); and/or second tunable coupler <NUM> can further tune a resonant frequency associated with the second tunable coupling (e.g., third coupling <NUM>), where the second capacitive coupling (e.g., fourth coupling <NUM>) generates a coupling that cancels the second tunable coupling when the resonant frequency associated with the second tunable coupling is smaller than a resonant frequency of both second qubit 106b and third qubit <NUM> (e.g., smaller than a resonant frequency of second qubit 106b and smaller than a resonant frequency of third qubit <NUM>).

In various embodiments, tunable coupler <NUM> or second tunable coupler <NUM> can be configured to respectively control (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, an AWG, a VNA, etc.) first coupling <NUM> or third coupling <NUM> and capacitor device <NUM> or second capacitor device <NUM> can be configured to respectively provide (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, an AWG, a VNA, etc.) second coupling <NUM> or fourth coupling <NUM> to eliminate coherent rotations and/or coherent qubit errors (e.g., ZZ errors) on first qubit 106a, second qubit 106b, third qubit <NUM>, and/or an adjacent qubit <NUM> (not illustrated in <FIG>). In these embodiments, such an adjacent qubit <NUM> can comprise a qubit that can be formed on device <NUM> at a location that is adjacent to first qubit 106a, second qubit 106b, and/or third qubit <NUM>.

In these embodiments, based on receiving pulses (e.g., microwave pulses) from a pulse generator device (e.g., an AWG, a VNA, etc.) as described above (e.g., via computer <NUM>, system memory <NUM>, processing unit <NUM>, etc.) tunable coupler <NUM> and capacitor device <NUM> can decouple: first qubit 106a from second qubit 106b; and/or adjacent qubit <NUM> from first qubit 106a and/or second qubit 106b. In these embodiments, based on receiving such pulses from such a pulse generator device as described above, second tunable coupler <NUM> and second capacitor device <NUM> can decouple: second qubit 106b from third qubit <NUM>; and/or adjacent qubit <NUM> from second qubit 106b and/or third qubit <NUM>.

In these embodiments, based on receiving such pulses from such a pulse generator device as described above, tunable coupler <NUM> and capacitor device <NUM> can decouple first qubit 106a from second qubit 106b and/or adjacent qubit 106c from first qubit 106a and/or second qubit 106b based on (e.g., using) the capacitive coupling (e.g., second coupling <NUM>) described above that can cancel the tunable coupling (e.g., first coupling <NUM>) when the resonant frequency associated with the tunable coupling (e.g., the resonant frequency associated with tunable coupler <NUM>) is smaller than the resonant frequency of both first qubit 106a and second qubit 106b (e.g., smaller than a resonant frequency of first qubit 106a and smaller than a resonant frequency of second qubit 106b). In these embodiments, based on receiving such pulses from such a pulse generator device as described above, second tunable coupler <NUM> and second capacitor device <NUM> can decouple second qubit 106b from third qubit <NUM> and/or adjacent qubit <NUM> from second qubit 106b and/or third qubit <NUM> based on (e.g., using) the second capacitive coupling (e.g., fourth coupling <NUM>) described above that can cancel the second tunable coupling (e.g., third coupling <NUM>) when the resonant frequency associated with the second tunable coupling (e.g., the resonant frequency associated with second tunable coupler <NUM>) is smaller than the resonant frequency of both second qubit 106b and third qubit <NUM> (e.g., smaller than a resonant frequency of second qubit 106b and smaller than a resonant frequency of third qubit <NUM>).

In these embodiments, based on such decoupling of first qubit 106a from second qubit 106b, second qubit 106b from third qubit <NUM>, and/or adjacent qubit <NUM> from second qubit 106b and/or third qubit <NUM>, tunable coupler <NUM> and capacitor device <NUM> and/or second tunable coupler <NUM> and second capacitor device <NUM> can thereby eliminate coherent rotations and/or coherent qubit errors (e.g., ZZ errors) on first qubit 106a, second qubit 106b, third qubit <NUM>, and/or adjacent qubit <NUM>. In these embodiments, based on such elimination of the coherent rotations and/or coherent qubit errors, device <NUM>, tunable coupler <NUM>, capacitor device <NUM>, second tunable coupler <NUM>, and/or second capacitor device <NUM> can thereby facilitate: reduced quantum gate errors associated with first qubit 106a, second qubit 106b, third qubit <NUM>, and/or adjacent qubit <NUM>; increased speed of a quantum gate comprising first qubit 106a and second qubit 106b or second qubit 106b and third qubit <NUM>; improved performance of a quantum processor comprising device <NUM> (e.g., which can comprise a quantum coupler device); and/or improved fidelity of such a quantum processor comprising device <NUM>.

In an example embodiment, during operation of device <NUM>, to perform a quantum gate between first qubit 106a and second qubit 106b, tunable coupler <NUM> can be pulsed on, while second tunable coupler <NUM> remains in an off state. Conversely, in this example embodiment, during operation of device <NUM>, to perform a quantum gate between second qubit 106b and third qubit <NUM>, second tunable coupler <NUM> can be pulsed on, while tunable coupler <NUM> remains in an off state. In an example, non-limiting alternative embodiment of device <NUM> that can comprise more qubits (e.g., <NUM> or more qubits, not illustrated in the figures), each pair of qubits, between which a two qubit quantum gate can be performed, can have their own coupler qubit (e.g., tunable coupler <NUM> or second tunable coupler <NUM>) and bypass capacitor (e.g., capacitor device <NUM> or second capacitor device <NUM>). In this example, non-limiting alternative embodiment of device <NUM>, one or more of the embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can be generalized (e.g., scaled) to accommodate a certain number of qubits (e.g., <NUM> or more) and/or to accommodate a various topologies (e.g., various superconducting circuit topologies).

Fabrication of the various embodiments of the subject disclosure described herein and/or illustrated in the figures (e.g., device <NUM>, <NUM>, etc.) can comprise multi-step sequences of, for example, photolithographic and/or chemical processing steps that facilitate gradual creation of electronic-based systems, devices, components, and/or circuits in a semiconducting and/or a superconducting device (e.g., an integrated circuit). For instance, the various embodiments of the subject disclosure described herein and/or illustrated in the figures (e.g., device <NUM>, <NUM>, etc.) can be fabricated on a substrate (e.g., a silicon (Si) substrate, etc.) by employing techniques including, but not limited to: photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive-tone photoresist, negative-tone photoresist, hybrid-tone photoresist, etc.), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, etc.), evaporation techniques, sputtering techniques, plasma ashing techniques, thermal treatments (e.g., rapid thermal anneal, furnace anneals, thermal oxidation, etc.), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical-mechanical planarization (CMP), backgrinding techniques, and/or another technique for fabricating an integrated circuit.

The various embodiments of the subject disclosure described herein and/or illustrated in the figures (e.g., device <NUM>, <NUM>, etc.) can be fabricated using various materials. For example, the various embodiments of the subject disclosure described herein and/or illustrated in the figures (e.g., device <NUM>, <NUM>, etc.) can be fabricated using materials of one or more different material classes including, but not limited to: conductive materials, semiconducting materials, superconducting materials, dielectric materials, polymer materials, organic materials, inorganic materials, non-conductive materials, and/or another material that can be utilized with one or more of the techniques described above for fabricating an integrated circuit.

<FIG> illustrates example, non-limiting graph <NUM> that can facilitate a quantum gate between qubits using a tunable coupler and a capacitor device in accordance with one or more embodiments described herein. Repetitive description of like elements and/or processes employed in respective embodiments is omitted for sake of brevity.

Graph <NUM> can comprise results data yielded from implementing one or more embodiments of the subject disclosure described herein. For example, graph <NUM> can comprise results data yielded from implementing (e.g., simulating, quantizing, etc.) device <NUM> in accordance with one or more embodiments (e.g., computer-implemented methods <NUM> and/or <NUM> described below with reference to <FIG> and <FIG>, respectively) of the subject disclosure described herein. In this example, as illustrated in <FIG>, graph <NUM> can comprise a three dimensional (3D) graph of results data yielded from implementing device <NUM> that can be plotted as: qubit detuning expressed in megahertz (MHz) in the Y-axis (e.g., the vertical axis of graph <NUM>); the frequency of tunable coupler <NUM> (denoted as Bus Frequency in <FIG>) in the X-axis (e.g., the horizontal axis of graph <NUM>), where the frequency of tunable coupler <NUM> can be controlled by magnetic flux threading through SQUID <NUM> of device <NUM> and expressed in gigahertz (GHz); and ZZ interaction frequencies represented by varying shades of gray in the Z-axis (e.g., the axis of graph <NUM> extending into and out of the page) that correspond with frequencies ranging from <NUM> to <NUM> as illustrated by the ZZ legend depicted in <FIG>.

In an example embodiment, to produce graph <NUM>, device <NUM> can be quantized using the following parameters:.

In an example embodiment, to produce graph <NUM>, device <NUM> can be quantized using the above defined parameters, where the frequency and the detuning of tunable coupler <NUM> can be varied. In this example embodiment, the ZZ interaction between first qubit 106a and second qubit 106b can be calculated based on such variations of the frequency and the detuning of tunable coupler <NUM>. In this example embodiment, as illustrated by graph <NUM> depicted in <FIG>, a region <NUM> near tunable coupler <NUM> frequency = <NUM> is where ZZ interactions are relatively small, which can represent the operating point where tunable coupler <NUM> is off. In this example embodiment, to form a two qubit gate between first qubit 106a and second qubit 106b, the frequency of tunable coupler <NUM> can be increased to a relatively large value (e.g., <NUM>). For instance, in this example embodiment, the frequency of tunable coupler <NUM> can be controlled (e.g., increased, decreased, etc.) by applying a magnetic flux threading through SQUID <NUM> (e.g., by providing a pulse via computer <NUM>, system memory <NUM>, processing unit <NUM>, an AWG, a VNA, etc. as described above with reference to <FIG>).

An example, non-limiting alternative embodiment of graph <NUM> can comprise a two-dimensional representation of a plane extending through graph <NUM>, where such a plane can be defined along line <NUM> depicted in <FIG>. For instance, graph <NUM> described below and illustrated in <FIG> can comprise such an example, non-limiting alternative embodiment of graph <NUM>, where graph <NUM> can comprise a two-dimensional side view of such a plane extending through graph <NUM> that can be defined along line <NUM> depicted in <FIG>.

<FIG> illustrates example, non-limiting information <NUM> that can facilitate a quantum gate between qubits using a tunable coupler and a capacitor device in accordance with one or more embodiments described herein. Repetitive description of like elements and/or processes employed in respective embodiments is omitted for sake of brevity.

As described above, graph <NUM> can comprise an example, non-limiting alternative embodiment of graph <NUM>, where graph <NUM> can comprise a two-dimensional side view of a plane extending through graph <NUM> that can be defined along line <NUM> depicted in <FIG>. As illustrated in the example embodiment depicted in <FIG>, graph <NUM> shows the ZZ interaction strength between first qubit 106a and second qubit 106b for a given set of device parameters (e.g., the device parameters defined above with reference to <FIG>). In this example embodiment, such ZZ interaction strength values are plotted in the Y-axis (e.g., vertical axis) of graph <NUM> and correspond to various flux pulse values (denoted as F Bus (GHz)) of tunable coupler <NUM> plotted along the X-axis (e.g., horizontal axis) of graph <NUM>. In the example embodiment depicted in <FIG>, graph <NUM> can have a corresponding time graph <NUM> illustrating the duration of each flux pulse that can be applied to device <NUM> (e.g., tunable coupler <NUM>, capacitor device <NUM>, etc.) when implementing the quantum gate sequence described below.

As described above with reference to <FIG>, device <NUM> can be implemented (e.g., quantized, simulated, etc.) by providing a pulse to tunable coupler <NUM> that can turn ZZ interaction on and off and results data obtained from such implementation can be plotted as graph <NUM>, graph <NUM>, and/or time graph <NUM> depicted in <FIG> and <FIG>. In the example embodiment of graph <NUM> and time graph <NUM> illustrated in <FIG>, the first step of a quantum gate sequence (e.g., between first qubit 106a and second qubit 106b) is denoted by the numeral <NUM> in graph <NUM> and time graph <NUM>. In this example embodiment, at step <NUM> of such a quantum gate sequence, the frequency (e.g., resonant frequency) of tunable coupler <NUM> (e.g., which can comprise a tunable bus) can be set such that the ZZ interaction is negligible (e.g., with a flux pulse of <NUM>, the corresponding ZZ interaction strength is approximately <NUM>-<NUM> MHz). In this example embodiment, the second step of such a quantum gate sequence is denoted by the numeral <NUM> in graph <NUM> and time graph <NUM>. In this example embodiment, at step <NUM> of such a quantum gate sequence, the frequency (e.g., resonant frequency) of tunable coupler <NUM> can be tuned with a flux pulse (e.g., <NUM>) in order to turn on the ZZ interaction between first qubit 106a and second qubit 106b. In this example embodiment, the third step of such a quantum gate sequence is denoted by the numeral <NUM> in graph <NUM> and time graph <NUM>. In this example embodiment, at step <NUM> of such a quantum gate sequence, after the flux pulse finishes, the frequency (e.g., resonant frequency) of tunable coupler <NUM> is returned to the off position and the ZZ interaction between first qubit 106a and second qubit 106b is again negligible.

The various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can be associated with various technologies. For example, the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can be associated with quantum computing technologies, quantum gate technologies, quantum coupler technologies, quantum hardware and/or software technologies, quantum circuit technologies, superconducting circuit technologies, machine learning technologies, artificial intelligence technologies, cloud computing technologies, and/or other technologies.

The various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can provide technical improvements to systems, devices, components, operational steps, and/or processing steps associated with the various technologies identified above. For example, the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can provide a tunable coupling between terminals of a same polarity of a first qubit (e.g., first qubit 106a) and a second qubit (e.g., second qubit 106b); provide a capacitive coupling between terminals of opposite polarity of the first qubit and the second qubit; and/or tune a resonant frequency associated with the tunable coupling, where the capacitive coupling generates a coupling that cancels the tunable coupling when the resonant frequency associated with the tunable coupling is smaller than a resonant frequency of both the first qubit and the second qubit. In this example, based on such cancelation (e.g., zero out, offset, negate, etc.) of the tunable coupling, the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can thereby eliminate coherent rotations and/or coherent qubit errors on the first qubit, the second qubit, and/or an adjacent qubit (e.g., adjacent qubit 106c) that cause gate errors during quantum computations. In this example, based on such elimination of coherent rotations and/or coherent qubit errors on the first qubit, the second qubit, and/or the adjacent qubit, the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can thereby facilitate: reduced quantum gate errors associated with the first qubit, the second qubit, and/or the adjacent qubit; increased speed of a quantum gate comprising the first qubit and the second qubit; improved performance of a quantum processor (e.g., a quantum processor comprising device <NUM> or device <NUM>); and/or improved fidelity of the quantum processor.

The various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can provide technical improvements to a processing unit (e.g., a quantum processor comprising device <NUM> or device <NUM>, processing unit <NUM>, etc.) associated with a classical computing device and/or a quantum computing device (e.g., a quantum processor, quantum hardware, superconducting circuit, etc.) that can be associated with one or more of the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.). For example, by cancelling (e.g., zero out, offset, negate, etc.) the tunable coupling and eliminating coherent rotations and/or coherent qubit errors on the first qubit, the second qubit, and/or the adjacent qubit as described above, one or more of the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can thereby facilitate: reduced quantum gate errors associated with the first qubit, the second qubit, and/or the adjacent qubit; and/or increased speed of a quantum gate comprising the first qubit and the second qubit. In this example, by reducing such quantum gate errors and/or increasing the speed of such a quantum gate, one or more of the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can facilitate: improved performance of a quantum processor (e.g., a quantum processor comprising device <NUM> or device <NUM> and that executes the quantum gate); and/or improved fidelity of such a quantum processor.

Based on such cancelation of the tunable coupling and elimination of coherent rotations and/or coherent qubit errors on the first qubit, the second qubit, and/or the adjacent qubit as described above, a practical application of the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) is that they can be implemented in a quantum device (e.g., a quantum processor, a quantum computer, etc.) to more quickly and more efficiently compute, with improved fidelity, one or more solutions (e.g., heuristic(s), etc.) to a variety of problems ranging in complexity (e.g., an estimation problem, an optimization problem, etc.) in a variety of domains (e.g., finance, chemistry, medicine, etc.). For example, based on such cancelation of the tunable coupling and elimination of coherent rotations and/or coherent qubit errors on the first qubit, the second qubit, and/or the adjacent qubit as described above, a practical application of one or more of the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) is that they can be implemented in, for instance, a quantum processor (e.g., a quantum processor comprising device <NUM> or device <NUM>) to compute one or more solutions (e.g., heuristic(s), etc.) to an optimization problem in the domain of chemistry, medicine, and/or finance, where such a solution can be used to engineer, for instance, a new chemical compound, a new medication, and/or a new options pricing system and/or method.

It should be appreciated that the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) provide a new approach driven by relatively new quantum computing technologies. For example, the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) provide a new approach to eliminate unintentional coherent rotations and/or coherent qubit errors that occur on spectator qubits (e.g., first qubit 106a, second qubit 106b, and/or adjacent qubit 106c) that result in gate errors during quantum computations. In this example, such a new approach to eliminate such unintentional coherent rotations and/or coherent qubit errors can enable faster and more efficient quantum computations with improved fidelity using a quantum processor comprising one or more of the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.).

The various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can employ hardware or software to solve problems that are highly technical in nature, that are not abstract and that cannot be performed as a set of mental acts by a human. In some embodiments, one or more of the processes described herein can be performed by one or more specialized computers (e.g., a specialized processing unit, a specialized classical computer, a specialized quantum computer, etc.) to execute defined tasks related to the various technologies identified above. The various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can be employed to solve new problems that arise through advancements in technologies mentioned above, employment of quantum computing systems, cloud computing systems, computer architecture, and/or another technology.

It is to be appreciated that the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can utilize various combinations of electrical components, mechanical components, and circuitry that cannot be replicated in the mind of a human or performed by a human, as the various operations that can be executed by the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) are operations that are greater than the capability of a human mind. For instance, the amount of data processed, the speed of processing such data, or the types of data processed by the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) over a certain period of time can be greater, faster, or different than the amount, speed, or data type that can be processed by a human mind over the same period of time.

According to several embodiments, the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can also be fully operational towards performing one or more other functions (e.g., fully powered on, fully executed, etc.) while also performing the various operations described herein. It should be appreciated that such simultaneous multi-operational execution is beyond the capability of a human mind. It should also be appreciated that the various embodiments of the subject disclosure described herein (e.g., device <NUM>, device <NUM>, etc.) can include information that is impossible to obtain manually by an entity, such as a human user. For example, the type, amount, and/or variety of information included in device <NUM> and/or device <NUM> can be more complex than information obtained manually by a human user.

<FIG> illustrates a flow diagram of an example, non-limiting computer-implemented method <NUM> that can facilitate a quantum gate between qubits using a tunable coupler and a capacitor device in accordance with one or more embodiments described herein. Repetitive description of like elements and/or processes employed in respective embodiments is omitted for sake of brevity.

At <NUM>, computer-implemented method <NUM> comprises providing, by a system (e.g., a system comprising computer <NUM> coupled to an AWG and/or a VNA that can be further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>) operatively coupled to a processor (e.g., processing unit <NUM>, etc.), a tunable coupling (e.g., first coupling <NUM>) between terminals (e.g., terminals 104a and 104b) of a same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., first qubit 106a and second qubit 106b).

At <NUM>, computer-implemented method <NUM> comprises providing, by the system (e.g., computer <NUM> coupled to an AWG and/or a VNA and further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>), a capacitive coupling (e.g., second coupling <NUM>) between terminals (e.g., terminals 104a and 104c) of opposite polarity (e.g., positive (+) and negative (-)) of the first qubit and the second qubit.

At <NUM>, computer-implemented method <NUM> comprises tuning, by the system (e.g., computer <NUM> coupled to an AWG and/or a VNA and further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>), a resonant frequency associated with the tunable coupling, where the capacitive coupling generates a coupling that cancels the tunable coupling when the resonant frequency associated with the tunable coupling is smaller than a resonant frequency of both the first qubit and the second qubit (e.g., smaller than a resonant frequency of first qubit 106a and smaller than a resonant frequency of second qubit 106b).

At <NUM>, computer-implemented method <NUM> can comprise tuning, by the system (e.g., computer <NUM> coupled to an AWG and/or a VNA and further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>), a resonant frequency associated with the tunable coupling, where the capacitive coupling generates a coupling that cancels the tunable coupling when the resonant frequency associated with the tunable coupling is smaller than a resonant frequency of both the first qubit and the second qubit (e.g., smaller than a resonant frequency of first qubit 106a and smaller than a resonant frequency of second qubit 106b).

At <NUM>, computer-implemented method <NUM> comprises decoupling, by the system (e.g., computer <NUM> coupled to an AWG and/or a VNA and further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>), the first qubit from the second qubit based on the coupling that cancels the tunable coupling when the resonant frequency associated with the tunable coupling is smaller than the resonant frequency of both the first qubit and the second qubit (e.g., smaller than a resonant frequency of first qubit 106a and smaller than a resonant frequency of second qubit 106b).

At <NUM>, computer-implemented method <NUM> can comprise eliminating, by the system (e.g., computer <NUM> coupled to an AWG and/or a VNA and further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>), coherent rotations on at least one of the first qubit or the second qubit based on the coupling that cancels the tunable coupling when the resonant frequency associated with the tunable coupling is smaller than the resonant frequency of both the first qubit and the second qubit, thereby facilitating at least one of: reduced quantum gate errors associated with at least one of the first qubit or the second qubit; increased speed of a quantum gate comprising the first qubit and the second qubit; improved performance of a quantum processor (e.g., a quantum processor comprising device <NUM>, which can comprise a quantum coupler device); or improved fidelity of the quantum processor.

At <NUM>, computer-implemented method <NUM> can comprise providing, by a system (e.g., a system comprising computer <NUM> coupled to an AWG and/or a VNA that can be further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>) operatively coupled to a processor (e.g., processing unit <NUM>), a first tunable coupling (e.g., first coupling <NUM>) between terminals (e.g., terminals 104a and 104b) of a same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., first qubit 106a and second qubit 106b), and a second tunable coupling (e.g., third coupling <NUM>) between terminals (e.g., terminals 204a and 204b) of a same polarity (e.g., positive (+) or negative (-)) of the second qubit and a third qubit (e.g., third qubit <NUM>).

At <NUM>, computer-implemented method <NUM> comprises providing, by the system (e.g., computer <NUM> coupled to an AWG and/or a VNA and further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>), a first capacitive coupling (e.g., second coupling <NUM>) between terminals (e.g., terminals 104a and 104c) of opposite polarity (e.g., positive (+) and negative (-)) of the first qubit and the second qubit, and a second capacitive coupling (e.g., fourth coupling <NUM>) between terminals (e.g., terminals 204a and 204c) of opposite polarity (e.g., positive (+) and negative (-)) of the second qubit and the third qubit.

At <NUM>, computer-implemented method <NUM> comprises tuning, by the system (e.g., computer <NUM> coupled to an AWG and/or a VNA and further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>), a first resonant frequency associated with the first tunable coupling, and a second resonant frequency associated with the second tunable coupling, wherein the first capacitive coupling comprises a first coupling that cancels the first tunable coupling when the first resonant frequency is smaller than a third resonant frequency of both the first qubit and the second qubit (e.g., smaller than a resonant frequency of first qubit 106a and smaller than a resonant frequency of second qubit 106b), and wherein the second capacitive coupling comprises a second coupling that cancels the second tunable coupling when the second resonant frequency is smaller than a fourth resonant frequency of both the second qubit and the third qubit (e.g., smaller than a resonant frequency of second qubit 106b and smaller than a resonant frequency of third qubit <NUM>).

At <NUM>, computer-implemented method <NUM> comprises providing, by a system (e.g., a system comprising computer <NUM> coupled to an AWG and/or a VNA that can be further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>) operatively coupled to a processor (e.g., processing unit <NUM>), a first tunable coupling (e.g., first coupling <NUM>) between terminals (e.g., terminals 104a and 104b) of a same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., first qubit 106a and second qubit 106b), and a second tunable coupling (e.g., third coupling <NUM>) between terminals (e.g., terminals 204a and 204b) of a same polarity (e.g., positive (+) or negative (-)) of the second qubit and a third qubit (e.g., third qubit <NUM>).

At <NUM>, computer-implemented method <NUM> can comprise decoupling, by the system (e.g., computer <NUM> coupled to an AWG and/or a VNA and further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>), at least one of the first qubit from the second qubit or the second qubit from the third qubit based on at least one of the first tunable coupling or the second tunable coupling, respectively, where at least one of the first qubit, the second qubit, or the third qubit comprises at least one of a fixed frequency qubit, a tunable qubit, a transmon qubit, a fixed frequency transmon qubit, or a tunable transmon qubit.

At <NUM>, computer-implemented method <NUM> can comprise eliminating, by the system (e.g., computer <NUM> coupled to an AWG and/or a VNA and further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>), coherent rotations on at least one of the first qubit, the second qubit, or the third qubit based on at least one of the first tunable coupling or the second tunable coupling, thereby facilitating at least one of: reduced quantum gate errors associated with at least one of the first qubit, the second qubit, or the third qubit; increased speed of a quantum gate comprising the first qubit and the second qubit or the second qubit and the third qubit; improved performance of a quantum processor (e.g., a quantum processor comprising device <NUM>, which can comprise a quantum coupler device); or improved fidelity of the quantum processor.

At <NUM>, computer-implemented method <NUM> can comprise providing (e.g., via a system comprising computer <NUM> coupled to an AWG and/or a VNA that can be further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>) a tunable coupling (e.g., first coupling <NUM>) between terminals (e.g., terminals 104a and 104b) of a same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., first qubit 106a and second qubit 106b).

At <NUM>, computer-implemented method <NUM> can comprise providing (e.g., via a system comprising computer <NUM> coupled to an AWG and/or a VNA that can be further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>) a capacitive coupling (e.g., second coupling <NUM>) between terminals (e.g., terminals 104a and 104c) of opposite polarity (e.g., positive (+) and negative (-)) of the first qubit and the second qubit.

At <NUM>, computer-implemented method <NUM> can comprise tuning (e.g., via a system comprising computer <NUM> coupled to an AWG and/or a VNA that can be further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>) a resonant frequency associated with the tunable coupling (e.g., a resonant frequency associated with first coupling <NUM> that can be generated and/or controlled by tunable coupler <NUM>). For instance, with reference to the example embodiments described above and illustrated in <FIG>, <FIG>, and <FIG>, a magnetic flux can be provided (e.g., via a system comprising computer <NUM> coupled to an AWG and/or a VNA that can be further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>) to tunable coupler <NUM> that can enable tuning of the resonant frequency of tunable coupler <NUM> such that it is above, at, or below the resonant frequency of both first qubit 106a and second qubit 106b (e.g., above, at, or below a resonant frequency of first qubit 106a and above, at, or below a resonant frequency of second qubit 106b).

At <NUM>, computer-implemented method <NUM> can comprise determining (e.g., via a system comprising computer <NUM> coupled to an AWG and/or a VNA that can be further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>) whether the ZZ interaction between the first qubit and the second qubit is turned on. For instance, with reference to the example embodiments described above and illustrated in <FIG>, <FIG>, and <FIG>, whether the resonant frequency associated with tunable coupler <NUM> is above or below the resonant frequency of both first qubit 106a and second qubit 106b can correspond with the strength of the ZZ interaction between first qubit 106a and second qubit 106b (e.g., above - corresponds with ZZ turned on; below - corresponds with ZZ turned off). Consequently, in these example embodiments, a determination as to whether the ZZ interaction is turned on can be performed using graph <NUM>, graph <NUM>, and/or time graph <NUM>. In these example embodiments, when the resonant frequency of tunable coupler <NUM> is above the resonant frequency of both first qubit 106a and second qubit 106b (e.g., above a resonant frequency of first qubit 106a and above a resonant frequency of second qubit 106b), the capacitive coupling (e.g., second coupling <NUM>) does not cancel (e.g., does not zero out, negate, offset, etc.) the tunable coupling (e.g., first coupling <NUM>) and the ZZ interaction between the first qubit 106a and second qubit 106b can be increased by applying increasing flux pulse to a point where a quantum gate can be performed between first qubit 106a and second qubit 106b (e.g., as illustrated by graph <NUM> in <FIG>, at a flux pulse of <NUM>, the corresponding ZZ interaction strength is approximately <NUM>-. <NUM> MHz).

If it is determined at <NUM> that the ZZ interaction between the first qubit and the second qubit is turned on, at <NUM>, computer-implemented method <NUM> can comprise performing (e.g., via a system comprising computer <NUM> coupled to an AWG and/or a VNA that can be further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>) a quantum gate between the first qubit and the second qubit. For instance, with reference to the example embodiments described above and illustrated in <FIG>, <FIG>, and <FIG>, when the resonant frequency of tunable coupler <NUM> is tuned to a point above the resonant frequency of both first qubit 106a and second qubit 106b (e.g., above a resonant frequency of first qubit 106a and above a resonant frequency of second qubit 106b, for example, as illustrated by graph <NUM> in <FIG>, at a flux pulse of <NUM>) the corresponding strength of the ZZ interaction between the first qubit 106a and second qubit 106b can enable performance of a quantum gate between first qubit 106a and second qubit 106b.

At <NUM>, computer-implemented method <NUM> can comprise tuning (e.g., via a system comprising computer <NUM> coupled to an AWG and/or a VNA that can be further coupled to device <NUM>, tunable coupler <NUM>, and/or capacitor device <NUM>) the resonant frequency associated with the tunable coupling to turn off the ZZ interaction between the first qubit and the second qubit. For instance, in the example embodiments described above and illustrated in <FIG>, <FIG>, and <FIG>, when the resonant frequency of tunable coupler <NUM> is below the resonant frequency of both first qubit 106a and second qubit 106b (e.g., below a resonant frequency of first qubit 106a and below a resonant frequency of second qubit 106b), the capacitive coupling (e.g., second coupling <NUM>) can cancel (e.g., zero out, negate, offset, etc.) the tunable coupling (e.g., first coupling <NUM>), at which point, the ZZ interaction between the first qubit 106a and second qubit 106b is negligible, and therefore, effectively turned off (e.g., as illustrated by graph <NUM> in <FIG>, at a flux pulse of <NUM>, the corresponding ZZ interaction strength is approximately <NUM>-<NUM> MHz).

If it is determined at <NUM> that the ZZ interaction between the first qubit and the second qubit is not turned on, computer-implemented method <NUM> can comprise returning to operation <NUM> to tune the resonant frequency associated with the tunable coupling. In various embodiments, operations <NUM> and <NUM> of computer-implemented method <NUM> can be repeated until the ZZ interaction between the first qubit and the second qubit is turned on. In these embodiments, based on repeating operations <NUM> and <NUM> until the ZZ interaction between the first qubit and the second qubit is turned on, computer-implemented method <NUM> can proceed to operations <NUM> and <NUM>.

In order to provide a context for the various aspects of the disclosed subject matter, <FIG> as well as the following discussion are intended to provide a general description of a suitable environment in which the various aspects of the disclosed subject matter can be implemented. <FIG> illustrates a block diagram of an example, non-limiting operating environment in which one or more embodiments described herein can be facilitated. For example, as described below, operating environment <NUM> can be used to implement the example, non-limiting multi-step fabrication sequences described above with reference to <FIG> and <FIG> that can be implemented to fabricate device <NUM> and/or device <NUM> in accordance with one or more embodiments of the subject disclosure as described herein. In another example, as described below, operating environment <NUM> can be used to implement one or more of the example, non-limiting computer-implemented methods <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM> described above with reference to <FIG>. Repetitive description of like elements and/or processes employed in other embodiments described herein is omitted for sake of brevity.

The example, non-limiting multi-step fabrication sequences described above with reference to <FIG> and <FIG>, which can be implemented to fabricate device <NUM> and/or device <NUM>, can be implemented by a computing system (e.g., operating environment <NUM> illustrated in <FIG> and described below) and/or a computing device (e.g., computer <NUM> illustrated in <FIG> and described below). In non-limiting example embodiments, such computing system (e.g., operating environment <NUM>) and/or such computing device (e.g., computer <NUM>) can comprise one or more processors and one or more memory devices that can store executable instructions thereon that, when executed by the one or more processors, can facilitate performance of the example, non-limiting multi-step fabrication sequences described above with reference to <FIG> and <FIG>. As a non-limiting example, the one or more processors can facilitate performance of the example, non-limiting multi-step fabrication sequences described above with reference to <FIG> and <FIG> by directing and/or controlling one or more systems and/or equipment operable to perform semiconductor and/or superconductor device fabrication.

In another example, one or more of the example, non-limiting computer-implemented methods <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM> described above with reference to <FIG> can also be implemented (e.g., executed) by operating environment <NUM>. As a non-limiting example, the one or more processors of such a computing device (e.g., computer <NUM>) can facilitate performance of one or more of the example, non-limiting computer implemented methods <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM> described above with reference to <FIG> by directing and/or controlling one or more systems and/or equipment (e.g., an AWG, a VNA, etc.) operable to perform the operations and/or routines of such computer-implemented method(s).

For simplicity of explanation, the computer-implemented methodologies are depicted and described as a series of acts. It is to be understood and appreciated that the subject innovation is not limited by the acts illustrated and/or by the order of acts, for example acts can occur in various orders and/or concurrently, and with other acts not presented and described herein. Furthermore, not all illustrated acts can be required to implement the computer-implemented methodologies in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that the computer-implemented methodologies could alternatively be represented as a series of interrelated states via a state diagram or events. Additionally, it should be further appreciated that the computer-implemented methodologies disclosed hereinafter and throughout this specification are capable of being stored on an article of manufacture to facilitate transporting and transferring such computer-implemented methodologies to computers. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage media.

With reference to <FIG>, a suitable operating environment <NUM> for implementing various aspects of this disclosure can also include a computer <NUM>. The computer <NUM> can also include a processing unit <NUM>, a system memory <NUM>, and a system bus <NUM>. The system bus <NUM> couples system components including, but not limited to, the system memory <NUM> to the processing unit <NUM>. The processing unit <NUM> can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit <NUM>. The system bus <NUM> can be any of several types of bus structure(s) including the memory bus or memory controller, a peripheral bus or external bus, and/or a local bus using any variety of available bus architectures including, but not limited to, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE <NUM>), and Small Computer Systems Interface (SCSI).

The system memory <NUM> can also include volatile memory <NUM> and nonvolatile memory <NUM>. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer <NUM>, such as during start-up, is stored in nonvolatile memory <NUM>. Computer <NUM> can also include removable/non-removable, volatile/non-volatile computer storage media. <FIG> illustrates, for example, a disk storage <NUM>. Disk storage <NUM> can also include, but is not limited to, devices like a magnetic disk drive, floppy disk drive, tape drive, Jaz drive, Zip drive, LS-<NUM> drive, flash memory card, or memory stick. The disk storage <NUM> also can include storage media separately or in combination with other storage media. To facilitate connection of the disk storage <NUM> to the system bus <NUM>, a removable or non-removable interface is typically used, such as interface <NUM>. <FIG> also depicts software that acts as an intermediary between users and the basic computer resources described in the suitable operating environment <NUM>. Such software can also include, for example, an operating system <NUM>. Operating system <NUM>, which can be stored on disk storage <NUM>, acts to control and allocate resources of the computer <NUM>.

System applications <NUM> take advantage of the management of resources by operating system <NUM> through program modules <NUM> and program data <NUM>, e.g., stored either in system memory <NUM> or on disk storage <NUM>. It is to be appreciated that this disclosure can be implemented with various operating systems or combinations of operating systems. A user enters commands or information into the computer <NUM> through input device(s) <NUM>. Input devices <NUM> include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit <NUM> through the system bus <NUM> via interface port(s) <NUM>. Interface port(s) <NUM> include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device(s) <NUM> use some of the same type of ports as input device(s) <NUM>. Thus, for example, a USB port can be used to provide input to computer <NUM>, and to output information from computer <NUM> to an output device <NUM>. Output adapter <NUM> is provided to illustrate that there are some output devices <NUM> like monitors, speakers, and printers, among other output devices <NUM>, which require special adapters. The output adapters <NUM> include, by way of illustration and not limitation, video and sound cards that provide a means of connection between the output device <NUM> and the system bus <NUM>. It should be noted that other devices and/or systems of devices provide both input and output capabilities such as remote computer(s) <NUM>.

Computer <NUM> can operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s) <NUM>. The remote computer(s) <NUM> can be a computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device or other common network node and the like, and typically can also include many or all of the elements described relative to computer <NUM>. For purposes of brevity, only a memory storage device <NUM> is illustrated with remote computer(s) <NUM>. Remote computer(s) <NUM> is logically connected to computer <NUM> through a network interface <NUM> and then physically connected via communication connection <NUM>. Network interface <NUM> encompasses wire and/or wireless communication networks such as local-area networks (LAN), wide-area networks (WAN), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring and the like. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL). Communication connection(s) <NUM> refers to the hardware/software employed to connect the network interface <NUM> to the system bus <NUM>. While communication connection <NUM> is shown for illustrative clarity inside computer <NUM>, it can also be external to computer <NUM>. The hardware/software for connection to the network interface <NUM> can also include, for exemplary purposes only, internal and external technologies such as, modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

The present invention may be a system, a method, an apparatus and/or a computer program product at any possible technical detail level of integration. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium can also include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing.

These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks. The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational acts to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

While the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on a computer and/or computers, those skilled in the art will recognize that this disclosure also can or can be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and/or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive computer-implemented methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, mini-computing devices, mainframe computers, as well as computers, hand-held computing devices (e.g., PDA, phone), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects can also be practiced in distributed computing environments in which tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all aspects of this disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices. For example, in one or more embodiments, computer executable components can be executed from memory that can include or be comprised of one or more distributed memory units. As used herein, the term "memory" and "memory unit" are interchangeable. Further, one or more embodiments described herein can execute code of the computer executable components in a distributed manner, e.g., multiple processors combining or working cooperatively to execute code from one or more distributed memory units. As used herein, the term "memory" can encompass a single memory or memory unit at one location or multiple memories or memory units at one or more locations.

As used in this application, the terms "component," "system," "platform," "interface," and the like, can refer to and/or can include a computer-related entity or an entity related to an operational machine with one or more specific functionalities. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between two or more computers. In another example, respective components can execute from various computer readable media having various data structures stored thereon. The components can communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems via the signal). As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts, wherein the electronic components can include a processor or other means to execute software or firmware that confers at least in part the functionality of the electronic components. In an aspect, a component can emulate an electronic component via a virtual machine, e.g., within a cloud computing system.

Claim 1:
A quantum coupler device, comprising:
a tunable coupler (<NUM>) coupled between terminals (104a, 104b) of a same polarity of a first qubit (106a) and a second qubit (106b), the tunable coupler (<NUM>) configured to control a first coupling between the first qubit (106a) and the second qubit (106b); and
a capacitor device (<NUM>) coupled to terminals (104a, 104c) of an opposite polarity of the first qubit (106a) and the second qubit (106b), the capacitor device (<NUM>) configured to provide a second coupling that is opposite in sign relative to the first coupling;
wherein the capacitor device (<NUM>) provides the second coupling based on a resonant frequency of the tunable coupler (<NUM>) being smaller than a resonant frequency of both the first qubit (106a) and the second qubit (106b).