Patent Description:
A camera system is disclosed in <CIT>. In the camera system, plural camera sections (hereinafter abbreviated as CHUs), each of which captures a video, and plural camera control units (hereinafter abbreviated as CCUs) are connected on a one-to-one basis via camera cables, and a video signal captured by each of the CRUs is supplied to a video switcher via respective one of the CRUs.

<CIT> (<NUM>-<NUM>-<NUM>) relates to a camera system having a plurality of camera pairs. Each pair comprises a camera control unit and a camera head unit respectively connected together by way of an asynchronous transmission network. The camera system comprises a central processing unit configured to obtain a video signal delay amount, representative of a time delay between a respective camera control unit and its respective camera head unit, for each of the plurality of camera pairs, and to adjust the video signal delay amount between at least one said camera control unit and its respective camera head unit to be equal to a selected video signal delay amount of another said camera control unit and its respective camera head unit.

<CIT> (<NUM>-<NUM>-<NUM>) relates to a camera system including a plurality of cameras, a camera controller configured to control the plurality of cameras, a control signal line configured to facilitate an exchange of at least one control signal between the camera controller and the plurality of cameras and a synchronization signal line commonly connected to the plurality of cameras, and configured to transmit at least one transmission synchronization signal for synchronizing at least two cameras among the plurality of cameras.

The above camera system has the following problem. Even when timings of the video signals at a time point of being supplied to the video switcher match, a transfer delay time is generated due to a cable length. Thus, the images-capture timing by each of the CHUs varies by a difference in the cable length. Even in the case where optical fiber camera cables are used, a transfer delay difference of approximately 5µ seconds is generated with the difference of <NUM> in the cable length, which causes a mismatch of the images-capture timings.

Such a mismatch of several µ seconds possibly causes the following problems. For example, in the case where images taken by plural cameras are used to determine whether a hit tennis ball drops on and passes a sideline or drops on the ground outside the sideline in a tennis game, accurate ball tracking calculations may not be performed, and thus the accurate determination may not be made. In addition, in the case where a multiple-perspective video is broadcast in a live baseball game program, a still image is displayed at a timing when a batter swings a bat and hits a ball, and the images by the plural cameras with different viewpoints are sequentially switched. Even in such a situation, if the images-capture timings of the cameras mismatch, an image of a moment when the bat hits the ball, an image of a moment when the ball leaves the bat, and the like are displayed in a non-uniform manner. As a result, the viewpoint cannot be changed smoothly.

In order to solve such a problem, it is considered to uniform all the cable lengths from the camera control unit to the cameras. However, this requires the wasteful cable length.

Such a problem is inherent not only in the video judgement but also in an images-capture system in which the cable length from the camera control unit to each of the cameras varies significantly and such a mismatch cannot be ignored.

The present invention has been made to solve the above problem and therefore provides a camera controller according to the appended claims, that allows images-capture at a constant timing with respect to an input synchronizing signal even when a length of a camera cable varies.

In the present specification, a reference synchronizing signal (a black burst signal, a tri-level sync signal, or the like) that is input to each of synchronizing demultiplexing circuits <NUM>, <NUM> of CCUs in the embodiments corresponds to the "input synchronizing signal". A "frame pulse signal" is a binary signal (a digital signal) indicating a position of beginning of each frame in a sequential video signal, and time at which an H level is dropped to an L level corresponds to a timing of the beginning of each of the video frames.

Each of CCUs <NUM> to <NUM> in the embodiments corresponds to the "camera controller".

A synchronizing demultiplexing circuit <NUM> and a phase control circuit <NUM> in the first embodiment and a synchronizing demultiplexing circuit <NUM> and a phase control circuit <NUM> in the second embodiment correspond to the "phase control section".

Features, the other purposes, applications, effects, and the like of the present invention will become apparent with reference to the embodiments and the drawings.

<FIG> illustrates an overview of a camera-captured images transfer device <NUM> according to the present invention.

The camera-captured images transfer device <NUM> has: plural cameras (hereinafter abbreviated as CHUs) <NUM> to <NUM>; and a camera control system <NUM> that has a delay adjustment images-capture function to adjust images-capture timings of the CHUs <NUM> to <NUM>.

The camera control system <NUM> includes a reference synchronizing signal generator <NUM> and plural camera control units (hereinafter abbreviated as CCUs) <NUM> to <NUM>. The CCUs <NUM> to <NUM> are respectively connected to the CHUs <NUM> to <NUM> by single-mode optical fibers 153a to c. Each of the CCUs <NUM> to <NUM> outputs images-capture data in an SDI standard.

<FIG> illustrates hardware configurations of the CHU <NUM> and the CCU <NUM> in <FIG>. Since the hardware configuration of the CHU <NUM> is the same as the conventional art, a brief description thereon will be made.

The CHU <NUM> includes an optical-electrical converter <NUM>, a demultiplexing circuit <NUM>, a multiplexing circuit <NUM>, a synchronizing signal generation circuit <NUM>, a synchronizing demultiplexing circuit <NUM>, a drive pulse generation circuit <NUM>, a CMOS images-capture element <NUM>, a video signal processing circuit <NUM>, and an electrical-optical converter <NUM>.

The CCU <NUM> transfers, to the optical-electrical converter <NUM>, a multiplexed optical signal that includes a clock signal and a frame pulse signal. The optical-electrical converter <NUM> converts this optical signal into an electric signal by a photodiode. The demultiplexing circuit <NUM> demultiplexes the electric signal in a serial state into the clock signal and the frame pulse signal, outputs the demultiplexed frame pulse signal to the multiplexing circuit <NUM>, and outputs the demultiplexed clock signal and frame pulse signal to the synchronizing signal generation circuit <NUM>. The synchronizing signal generation circuit <NUM> generates a tri-level sync signal from the received frame pulse signal and clock signal, and outputs the tri-level sync signal to the synchronizing demultiplexing circuit <NUM>.

The synchronizing demultiplexing circuit <NUM> generates a horizontal synchronizing signal and a vertical synchronizing signal from the received analog tri-level sync signal.

The drive pulse generation circuit <NUM> generates an images-capture element drive pulse from the horizontal synchronizing signal and the vertical synchronizing signal that are output from the synchronizing demultiplexing circuit <NUM>.

Light that passes through a lens <NUM> forms an image on an images-capture element surface of the CMOS images-capture element <NUM>. The CMOS images-capture element <NUM> receives an images-capture element drive pulse to capture a video image with <NUM> effective horizontal pixels and <NUM> effective vertical pixels and at a frame rate of <NUM> fps, and outputs an RGB digital video signal. The video signal processing circuit <NUM> executes gamma processing and matrix processing on the RGB digital video signal, which is output from the CMOS images-capture element <NUM>, and outputs a video signal that includes a luminance signal and a color-difference signal.

The multiplexing circuit <NUM> multiplexes the luminance signal and the color-difference signal, which are output from the video signal processing circuit <NUM>, and the frame pulse signal, which is demultiplexed by the demultiplexing circuit <NUM>, and converts the multiplexed signal into a serial signal. The electrical-optical converter <NUM> converts this serial signal into the optical signal by a laser diode and transfers the optical signal to the CCU <NUM>.

As described above, when the CHU receives the optical signal that includes the clock signal and the frame pulse signal from the CCU <NUM>, the CHU <NUM> outputs captured video data to the CCU <NUM>.

<FIG> separately illustrates the sections in the CHU <NUM> into an images-capture unit <NUM> and a control unit <NUM>. However, the present invention is not limited thereto. Configurations of the other CHUs <NUM>, <NUM> are the same as that of the CHU <NUM>.

Here, in the case where lengths of optical cables between the CCUs and the CHUs differ, the images-capture timings mismatch by a difference in the optical cable length even with simultaneous provision of the optical signals including the frame pulse signal from the CCUs. To handle such a problem, in this embodiment, a phase control circuit <NUM> is provided to each of the CCUs, so as to match the images-capture timings. A description thereon will be made below.

The CCU <NUM> has a synchronizing demultiplexing circuit <NUM>, the phase control circuit <NUM>, a multiplexing circuit <NUM>, an electrical-optical converter <NUM>, an optical-electrical converter <NUM>, a demultiplexing circuit <NUM>, a serial output circuit <NUM>, an output terminal <NUM>, and a reference synchronizing signal input terminal <NUM>.

The synchronizing demultiplexing circuit <NUM> receives an analog tri-level sync signal as a reference synchronizing signal from the reference synchronizing signal generator <NUM>(see <FIG>). When the synchronizing signal circuit <NUM> receives this tri-level sync signal, the synchronizing demultiplexing circuit <NUM> detects the horizontal synchronizing signal and the vertical synchronizing signal from the tri-level sync signal, generates a video sampling clock signal and the frame pulse signal that indicates a time position of beginning of a video frame, and outputs the video sampling clock signal and the frame pulse signal to the phase control circuit <NUM>.

When the phase control circuit <NUM> receives the horizontal synchronizing signal, the vertical synchronizing signal, and the frame pulse signal from the synchronizing demultiplexing circuit <NUM>, as will be described below, the phase control circuit <NUM> advances a timing of the frame pulse signal by an amount of mismatching prevention data, and then outputs the video sampling clock signal and the frame pulse signal.

The multiplexing circuit <NUM> multiplexes a signal that includes the video sampling clock signal and the frame pulse signal output from the phase control circuit <NUM>, further serializes this multiplexed signal, and outputs an electric signal. The electrical-optical converter <NUM> converts the electric signal output from the multiplexing circuit <NUM> into the optical signal by a laser diode, and provides the optical signal to the CHU <NUM>.

As it has already been described, the CCU <NUM> receives, from the CHU <NUM>, the luminance signal and the color-difference signal as the video signal as well as the video data in which the frame pulse signal and the video sampling clock as control signals are serialized.

The optical-electrical converter <NUM> converts the received optical signal into an electric signal by a photodiode. The demultiplexing circuit <NUM> demultiplexes the electric signal in the serial state into the video signal, which includes the luminance signal and the color-difference signal, and into the frame pulse signal, and outputs the video signal and the frame pulse signal separately. The serial output circuit <NUM> serializes the video signal including the luminance signal and the color-difference signal, and outputs an SDI signal in the SMPTE <NUM> standard to the outside.

The frame pulse signal that is demultiplexed by the demultiplexing circuit <NUM> is provided to the phase control circuit <NUM>. The phase control circuit <NUM> measures a time difference between the frame pulse signal from the demultiplexing circuit <NUM> and the frame pulse signal transferred to the multiplexing circuit <NUM>, determines a half of this time difference as an adjustment time, and thereafter outputs the frame pulse signal at an advanced timing by the adjustment time.

In this embodiment, for <NUM> seconds from power-on, the frame pulse signal is output at the timings of the horizontal synchronizing signal and the vertical synchronizing signal, which are provided from the synchronizing demultiplexing circuit <NUM>. Then, after a lapse of <NUM> seconds since the power-on, the adjustment time is determined, and the frame pulse signal is output at the timing that is advanced by the adjustment time.

<FIG> illustrates a flowchart of the above processing. More specifically, in a period from the power-on to the lapse of <NUM> seconds, the phase control circuit <NUM> outputs the input frame pulse signal, which is received from the synchronizing demultiplexing circuit <NUM>, as is to the multiplexing circuit <NUM> (step S1).

Then, after the lapse of <NUM> seconds since the power-on, the phase control circuit <NUM> measures a delay time from the time difference between the frame pulse signal output from the demultiplexing circuit <NUM> and the frame pulse signal output from the synchronizing demultiplexing circuit <NUM>, and calculates the adjustment time that is the half of the delay time (step S3). In addition, the phase control circuit <NUM> outputs, to the multiplexing circuit <NUM>, the frame pulse signal, the phase of which is advanced by the adjustment time retained for the frame pulse signal output from the synchronizing demultiplexing circuit <NUM> (step S4).

A description will be made on adjustment of the delay with reference to <FIG> and <FIG>. A description will hereinafter be made on a case where the lengths of the optical cables from the CCUs to the CHUs are <NUM>, <NUM>, and <NUM> as an example. In <FIG>, a point C1P1K is an input point to the synchronizing demultiplexing circuit <NUM>, a point C1P2K is an output point from the synchronizing demultiplexing circuit <NUM>, a point C1P3K is an output point from the phase control circuit <NUM>, a point C1P4K is an input point to the CHU, a point C1P5K is an output point from the CHU, and a point C1P6K is an input point to the CCU. In <FIG>, in the case where the cable length is <NUM>, a mismatch that becomes a problem does not occur at the points C1P1K to C1P6K. Here, in the case where the cable length is <NUM>, the delay of approximately <NUM>/<NUM> occurs in calculation. However, since the delay of such an extent is not problematic, it is handled that the mismatch does not occur.

On the contrary, in the case where the cable length is <NUM>, the delay of <NUM> from the input timing of the synchronizing signal to the CCU occurs at the points C1P4K and C1P5K, and the delay of <NUM> from the input timing of the synchronizing signal to the CCU occurs at the point C1P6K.

Meanwhile, in the case where the cable length is <NUM>, the delay of <NUM> from the input timing of the synchronizing signal to the CCU occurs at the points C1P4K and C1P5K, and the delay of <NUM> from the input timing of the synchronizing signal to the CCU occurs at the point C1P6K.

Such delays occur by the optical cable length from each of the CCUs to respective one of the CHUs. In this embodiment, in order to match the images-capture timings of the CHUs, a time from the input timing of the synchronizing signal to each of the CCUs to a timing at which each of the CCUs receives the signal from respective one of the CHUs is calculated. Then, the phase control circuit <NUM> advances the output timing of the frame pulse signal by a half of this time. More specifically, as illustrated in <FIG>, the output timing (the point C1P3K) from the phase control circuit <NUM> is advanced by <NUM> when the cable length is <NUM>, and is advanced by <NUM> when the cable length is <NUM>. As a result, the timings at the point C1P4K and C1P5K match regardless of the cable length.

Here, in <FIG> and <FIG>, in order to simplify the explanation, it is assumed that a processing delay in each of the sections is set to zero.

As described above, in this embodiment, the phase control circuit in each of the CCUs transfers, to respective one of the CHUs, the frame pulse signal, the phase of which is advanced by the mismatching prevention data from the time position of the beginning of the frame of the reference synchronizing signal (the tri-level sync signal or a black burst signal) received by each of the CCUs. Accordingly, the frame pulse signal, the phase of which is advanced by the mismatching prevention data from that in the reference synchronizing signal received from the reference synchronizing signal generator is transferred to the CHU. In this way, the timings of the beginning of the frames of the synchronizing signals, which are output from the synchronizing signal generation circuits in the CHUs, match. As a result, the images-capture timings match.

In the above first embodiment, as apparent from the timing chart in <FIG>, the images-capture timings of the CHUs can match regardless of the cable length between each of the CCUs and respective one of the CHUs. However, even in such a case, output timings from the CCUs to an image synchronizing computer <NUM> mismatch by the delay that occurs due to the optical cables from the CHUs to the CUUs (the delay at the point C1P6K in <FIG>).

Such a delay can be eliminated by the conventional genlock function. However, by adopting a configuration as in a second embodiment, it is possible to eliminate the delay at the point C1P6K in <FIG>.

As a hardware configuration, as illustrated in <FIG>, FIFO (First In, First Out) memory <NUM> is provided between the serial output circuit <NUM>, which outputs the signal from the CCU <NUM> to the image synchronizing computer <NUM>, and the demultiplexing circuit <NUM>. Similar to the first embodiment, it is configured that a phase control circuit <NUM> outputs the frame pulse signal at an earlier timing by a sum of the mismatching prevention data and a specified time (for example, <NUM>) than the frame pulse signal received from the synchronizing demultiplexing circuit <NUM>.

As processing in the phase control circuit <NUM>, the frame pulse signal only needs to be transferred at the further advanced timing by <NUM> in either step S1 or step S4 of <FIG>.

More specifically, in the period from the power-on and before the lapse of <NUM> seconds, the phase control circuit <NUM> advances the phase of the frame pulse signal, which is received from the synchronizing demultiplexing circuit <NUM>, by <NUM>, and outputs the frame pulse signal to the multiplexing circuit <NUM>. Then, after the lapse of <NUM> seconds since the power-on, the phase control circuit <NUM> measures the delay time from the time difference between the frame pulse signal output from the demultiplexing circuit <NUM> and the frame pulse signal output from the synchronizing demultiplexing circuit <NUM>, and calculates the adjustment time that is the half of the delay time. In addition, the phase control circuit <NUM> outputs, to the multiplexing circuit <NUM>, the frame pulse signal, the phase of which is advanced by the adjustment time, which is retained for the frame pulse signal output from the synchronizing demultiplexing circuit <NUM>, + <NUM>.

As described above, the frame pulse signal, which controls the CHU, is output by advancing the timing by a time which is obtained by adding the specified time to the mismatching prevention data. In this way, even in the case where the delay based on the cable length between the CCU and the CHU occurs, the timings of the beginning of the frames of the synchronizing signals, which are output from the synchronizing signal generation circuits <NUM> in the CHUs, match. Therefore, the images-capture timings of the plural CHUs match.

In addition, the video signals from the plural CHUs are captured at the advanced timing by the specified time. In the case where each of such a video signal is written in the FIFO memory <NUM> and is read from the FIFO memory <NUM> at the timing of the frame pulse signal output from the synchronizing demultiplexing circuit <NUM>, output timings of the video signals from the plural CCUs can match.

The specified time is set to <NUM>. This specified time is set to secure a margin for the mismatching prevention data of the CCU that receives the video signal from the CHU at the latest timing among the plural CCUs. However, the specified time is not limited thereto.

A description will be made on the FIFO memory <NUM>. The FIFO memory <NUM> is controlled by a write address reset pulse and a read address reset pulse. For the write address reset pulse, information indicating the beginning of the frame, which is demultiplexed by the demultiplexing circuit <NUM>, is used. For the read address reset pulse, the frame pulse signal output from the synchronizing demultiplexing circuit <NUM> is used.

A description will be made on a timing chart in this embodiment with reference to <FIG>, <FIG>. Points in <FIG>, <FIG> are the same as those in <FIG>, <FIG>.

<FIG> is a timing chart for <NUM> seconds from the power-on. The frame pulse signal, the phase of which is advanced by <NUM> from the input frame pulse signal, is output to the multiplexing circuit <NUM>. In this state, similar to the first embodiment, the images-capture timings of the CHUs mismatch. On the contrary, after the lapse of <NUM> seconds since the power-on, as illustrated in FIG. <NUM>, similar to the first embodiment, the frame pulse signal is further advanced by the half of the time from the output timing from the CCU to the received timing, and is transferred to the multiplexing circuit <NUM>. In this way, the mismatch of the images-capture timings of the CHUs is eliminated. In addition, the phase of the frame pulse signal is advanced by <NUM> from the input frame pulse signal, and the read timing from the FIFO memory <NUM> is made to match the timing of the synchronizing signal input to the phase control circuit <NUM>. In this way, it is possible to absorb the delay that is based on a returning distance from the CHU to the CCU.

More specifically, the FIFO memory <NUM> writes the video signal that is output from the demultiplexing circuit <NUM>, reads the video signal, and outputs the video signal to the serial output circuit <NUM>. A write address is controlled at the synchronizing timing (the timing of the frame pulse signal indicating the beginning of the frame) of the video signal output from the demultiplexing circuit <NUM>. Then, a read address is controlled at the timing of the frame pulse signal output from the synchronizing demultiplexing circuit <NUM>. As a result, the video signal is delayed by the time difference between the frame pulses signal on both sides, and is output.

In this embodiment, the delay is not adjusted until the lapse of <NUM> seconds since the power-on. Thereafter, the delay is adjusted for each time. However, the above time is not limited to <NUM> seconds.

The delay based on the cable length is measured each time. However, once the delay adjustment time is set, the calculation may not be performed thereafter, and the delay may be adjusted by using such data.

The above embodiment can be implemented as a device that determines the delay adjustment data in order to match the images-capture timings of the CHUs according to the difference in the cable length.

In the above embodiment, the description has been made on the case of use for the video judgement. However, the application is not limited thereto. For example, the problem of synchronizing the images-capture timings of the plural cameras occurs similarly in the case of synchronizing <NUM>-dimensional images from video data of the plural cameras. Thus, the present invention can be applied to such a case similarly.

In the above embodiment, the description has been made on the case where the optical fibers are used as the connection cables between the camera control units and the cameras. However, any cable can be adopted as long as the cable can perform high-speed transfer, can be used for a long distance, and can be installed separately. For example, a triax cable or the like may be adopted.

In the second embodiment, the specified time is fixed. However, the mismatch prevention data of the CCU that receives the video signal from the CHU at the latest timing among the plural CCUs may be measured, and the measured data or data further added with the margin may be set as the specified time.

Claim 1:
A camera controller configured to:
receive an input synchronizing signal,
transfer a video frame synchronizing signal based on the input synchronizing signal to a camera section, wherein the camera section is connected to the camera controller via a camera cable, and
receive a video signal captured by the camera section at a timing of the video frame synchronizing signal;
wherein the camera controller is characterized in that it is configured to:
measure a mismatch of a timing between the video frame synchronizing signal that is transferred to the camera section and a video frame synchronizing signal in the video signal received from the camera section,
advance a phase of the video frame synchronizing signal transferred to the camera section by a half of the mismatch of the timing, and
transfer the video frame synchronizing signal to the camera section.