Patent Description:
System-in-package (SiP) technology currently attempts to interconnect numerous semiconductor devices within a single semiconductor package. SiP technology includes various interconnect techniques, such as utilizing copper pillar interconnects, flip-chip interconnects, interconnect fabric such as interposers, and the like.

<CIT>) provides a compensation system, with a central clock generator. The central clock generator supplies a 'central' clock signal via a first line to a first chip. Separately, the central clock generator sends a clock signal on a second line to a second chip. Each chip is equipped with a 'variable clock delay' circuit. That circuit receives the clock signal from the clock generator. Separate circuitry is provided on each chip to send data between the two chips. The data exchange between the two chips is used to derive skew information. The circuitry that exchanges data between the two chips feeds back information about the skew to the variable clock delay circuit of the chip. That information allows the variable clock delay circuit of the chip to apply an adjustment to the central clock signal received by the chip. The chip can then use that adjusted version of the central clock signal on the chip.

<CIT>) provides a method and apparatus for clock skew reduction. US'<NUM> again deals with a centrally generated and distributed clock. A modulator generates a clock signal, which is input to a unit on a clock regulator chip. That clock regulator chip supplies, as an output, a clock for distribution to various other ASICs. At least two clock signals are generated on the clock regulator chip from the centrally generated clock that was supplied to the clock regulator chip.

<CIT>) provides a method of communicating a slave clock signal from a master block of a circuit to a slave block of the circuit. Four clock signals may be sent from the master block to the slave block. The four clock signals are separated from each other by a constant phase difference, such as <NUM> degrees. The four clock signals will be subject to delay when passing from the master block to the slave block. One clock signal will be sent to a phase detector. A replicator provides a second signal to the phase detector. The phase detector compares the two signals that it receives and produces a 'control signal'. Based on the control signal, a selector circuit choses one of the four clock signals, to serve as a clock signal for the slave circuit.

<CIT>) provides a clock distribution network. A clock signal is to be distributed within one integrated circuit. A system clock is supplied from outside an integrated circuit to a Master Phase Locked Loop on the integrated circuit. The system clock is to be distributed to various different clock processor nodes that are located on the integrated circuit. However, that distribution process leads to delay variations, in the various routes between the Master Phase Locked Loop and the various different clock processor nodes that are distributed on the integrated circuit. An alignment control circuit may be provided in each path between the Master Phase Locked Loop and the clock processor node to which that path leads. The alignment control circuit may compensate for the particular delay on the path to that particular clock processor node.

The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements, unless otherwise noted.

The following sets forth a detailed description of various embodiments intended to be illustrative of the invention and should not be taken to be limiting.

An integrated circuit often includes synchronous elements, or elements that must be synchronized using a clock signal. As the clock signal is distributed to the elements in the integrated circuit via a clock distribution network, the clock signal may arrive at the elements at different times due to various factors affecting the clock signal, such as differing path length to the elements, temperature variation, electromagnetic interference, resistive-capacitive coupling, propagation delays of buffers used in the clock distribution network, and the like. In order for the integrated circuit to operate properly, such clock skew must be reduced by balancing the clock signal across the integrated circuit to ensure that the synchronous elements receive logic level changes of the clock signal simultaneously.

System-in-package (SiP) technology currently attempts to interconnect numerous different types of semiconductor devices (or SiP devices) within a single semiconductor package (or SiP package). The integrated circuits of the different SiP devices also include synchronous elements. Many high performance applications require synchronous communication within an SiP package, where the various synchronous elements of the SiP devices must be synchronized. Present solutions often utilize clock domain crossing logic within interfacing logic on each interconnected interface of the SiP devices. However, clock domain crossing can cause significant latency penalties for high performance applications as signals cross from one clock domain to another clock domain and must be synchronized to the destination clock domain.

The present disclosure provides adaptive clock signal alignment across synchronous elements of multiple SiP devices within an SiP package that implements a single clock domain by compensating for interconnect delay. A source clock signal is provided by a master or host device to one or more secondary or expansion devices of an SiP package. The source clock signal, as well as other signals transmitted from device to device, experiences delay when traveling across SiP interconnect circuitry from the host device to a given expansion device, also referred to as interconnect delay. The interconnect delay is compensated for by each expansion device to properly align local clock signal(s) with the host device's source clock signal. Each expansion device includes local synchronous logic that utilizes the local aligned clock signal(s), achieving synchronous communication with the host device's synchronous logic that utilizes the source clock signal.

In some embodiments, the interconnect delay is determined for each expansion device and set before operation of the SiP package (e.g., during factory settings). In other embodiments, the interconnect delay is dynamically (e.g., on the fly) determined by each expansion device during operation of the SiP package. In both types of embodiments, adaptive clock signal alignment compensates for the interconnect delay and automatically adjusts a local clock signal to be aligned with the source clock signal of the host device. In this manner, the present disclosure provides a flexible and low latency solution for partitioning synchronous elements within the same clock domain onto multiple SiP devices, where the SiP devices achieve synchronous communication at high speeds (e.g., greater than or equal to <NUM>), even for differing SiP technologies.

<FIG> illustrates a simplified block diagram depicting an example semiconductor device <NUM> of a system <NUM> in which the disclosure is implemented. In some embodiments, semiconductor device <NUM> is a die <NUM> that is part of an expansion device included in a system-in-package (SiP) package, which also includes a host die (not shown). In other embodiments, semiconductor device <NUM> and a host semiconductor device are part of a single die, where the semiconductor device <NUM> and the source semiconductor device are intraconnected devices on the single die. It is noted that semiconductor device <NUM> is described herein as die <NUM> for illustrative purposes, and should not be taken to be limiting. While die <NUM> includes a great variety of components, many components are omitted in <FIG> to maintain simplicity.

Die <NUM> includes on-chip synchronous logic <NUM>, or integrated circuitry that includes synchronous elements. On-chip synchronous logic <NUM> is configured to be in synchronous communication with synchronous logic on a host die (not shown) via a number of data lines <NUM>, level shifter <NUM>, and a number of data lines <NUM>. Also, bus and address control lines (not shown) are associated with data lines <NUM> and <NUM>. An example embodiment of on-chip synchronous logic <NUM> includes a synchronous bus that is configured to be in synchronous communication with a synchronous bus on the host die, which is further discussed below in connection with <FIG>.

Die <NUM> also includes interconnect circuitry configured to provide an interface to communicate with another die, such as a host die. Interconnect circuitry may be any one of various interconnect technologies, such as copper pillar interconnect technology (e.g., for stacked devices), flip-chip interconnect technology (e.g., for flip-chip devices), interconnect fabric (e.g., for some types of SiP devices), and the like. Some embodiments of interconnect technology also include technology translation circuitry, such as level shift circuitry that allows die of different technologies to communicate with one another. The embodiment illustrated in <FIG> shows die <NUM> having interconnect circuitry including technology translation circuitry, which is illustrated as level shifter <NUM>. Level shifter <NUM> is configured to adjust signals received from a host die (not shown) to a level utilized by internal circuitry of die <NUM>, as well as to adjust outgoing signals to a level utilized by the host die for transmission to the host die. In some embodiments, level shifter <NUM> translates signals between some standard signal level at the interconnect and an internal signal level utilized by internal circuitry of die <NUM> when receiving or transmitting such signals. As such, die <NUM> is agnostic as to the type of die with which die <NUM> communicates.

Die <NUM> is configured to receive a source clock signal <NUM> from a host die. Source clock <NUM> is input to level shifter <NUM>, which outputs a level shifted version of the source clock <NUM>, also referred to herein as a received source clock signal <NUM>. As source clock <NUM> travels from the host die to die <NUM> via interconnect circuitry, source clock <NUM> experiences delay arising from the interconnect circuitry, also referred to herein as interconnect delay <NUM>. For example, source clock <NUM> experiences delay <NUM> from level shifter <NUM> due to a variety of reasons, including but not limited to propagation delay of logic or buffer circuitry within level shifter <NUM>, signal path length, temperature variation, electromagnetic interference, resistive-capacitive coupling, and the like. As discussed herein, interconnect delay <NUM> is an amount of delay that is introduced to source clock signal <NUM> as it travels from a point where source clock <NUM> is available to synchronous elements on the host die (e.g., is used to clock synchronous logic on host die) through interconnect circuitry (including through level shifter <NUM>) to a point where received source clock signal <NUM> is available to clock aligning block <NUM>. In the embodiment illustrated in <FIG>, interconnect delay <NUM> is modeled to include level shifter (LS) delay <NUM>.

Die <NUM> also includes a clock alignment loop circuit, which in turn includes a clock aligning block <NUM>, a clock control block <NUM>, a clock distribution network <NUM>, and a clock delay circuit <NUM>. The clock alignment loop circuit includes a generated clock signal path from clock aligning block <NUM> to clock distribution network <NUM> (via clock control block <NUM>), and a feedback clock signal path from clock distribution network <NUM> to clock aligning block <NUM> (via clock delay circuit <NUM>). The clock alignment loop circuit is configured to align one or more local clock signals, or aligned clock(s) <NUM> as discussed below, with source clock signal <NUM> to achieve a single clock domain.

Clock aligning block <NUM> has two inputs, the received source clock signal <NUM> and a feedback clock signal received from clock delay circuit <NUM>, which is illustrated as intermediate adjusted clock <NUM>. The feedback clock signal is further discussed below in connection with clock delay circuit <NUM>. Clock aligning block <NUM> is configured to compare phases of the received source clock signal <NUM> and the feedback clock signal to determine a delay (or phase difference) exhibited by the feedback clock signal, as compared with the received source clock signal <NUM>. Clock aligning block <NUM> is also configured to output a master adjusted clock signal <NUM> whose phase is adjusted in order to compensate for the delay exhibited by the feedback clock signal. Such delay is further discussed below in connection with clock delay circuit <NUM>. Examples of circuitry included in clock aligning block <NUM> include, but are not limited to, a phase detector, a variable delay line, a variable frequency oscillator, a delay- locked loop (DLL) circuit (e.g., a phase detector coupled with a variable delay line), a phase-locked loop (PLL) circuit (e.g., a phase detector coupled with a variable frequency oscillator), and similar circuitry that is configured to output an adjustable periodic clock signal.

Clock control block <NUM> is configured to receive master adjusted clock signal <NUM> and to output one or more generated clock signals <NUM>. One or more generated clock signals <NUM> may each have a different clock frequency, where each clock signal <NUM> has a frequency that is some factor (e.g., multiple or fraction) of the frequency of master adjusted clock signal <NUM>. Examples of circuitry included in clock control block <NUM> include, but are not limited to, clock frequency divider circuits, clock frequency multiplier circuits, and similar circuitry that is configured to receive an input clock signal and generate one or more clock signals based on the frequency of the input clock signal.

Clock distribution network <NUM> is configured to distribute the one or more generated clock signals <NUM> as one or more balanced clock signals <NUM> to synchronous elements of logic circuitry on die <NUM>, including to on-chip synchronous logic <NUM>. Clock distribution network <NUM> is balanced, where the clock signals are distributed to the synchronous elements in such a way that the synchronous elements receive logic level changes of the clock signals simultaneously. In other words, clock distribution network <NUM> provides one or more balanced clock signals <NUM> to on-chip synchronous logic <NUM>. One or more balanced clock signals <NUM> may be phase aligned with one another. One or more balanced clock signals <NUM> may each have a different clock frequency, where each clock signal <NUM> has a frequency that is some factor (e.g., multiple or fraction) of the frequency of master adjusted clock signal <NUM>. Examples of circuitry included in clock distribution network <NUM> include, but is not limited to, balanced clock trees, buffers to drive synchronous elements (e.g., registers) at the leaves of the clock tree, de-skew circuits, de-jitter circuits, and the like.

Various delay is introduced into the generated clock signal path as one or more clock signals are propagated through logic gate elements of the clock alignment loop circuit, where each logic gate element requires a certain amount of time after an input is received for its output to change. For example, clock control block <NUM> includes data latches, such as D-type flip flops that include various logic gate elements, where each data latch requires a certain amount of time after a clock edge is received for its output to change, also referred to as clock-to-output propagation delay. The overall propagation delay introduced into generated clocks <NUM> (as compared with master adjusted clock <NUM>) by clock control block <NUM> is referred to as CCB (clock control block) delay <NUM>. Additionally, the buffers in clock distribution network <NUM>, which also include various logic gate elements, also each require a certain amount of time to change its output after a clock edge is received. The overall propagation delay introduced into balanced clocks <NUM> (as compared with generated clocks <NUM>) is referred to as CDN (clock distribution network) delay <NUM>. CCB delay <NUM> and CDN delay <NUM> often change during operation of die <NUM> for a variety of reasons, including but not limited to voltage supply variation, temperature variation, electromagnetic interference, resistive-capacitive coupling, and the like.

Clock delay circuit <NUM> is configured to receive one of the balanced clock signals <NUM> (also referred to as a feedback balanced clock signal <NUM>) and to output a delayed version of the feedback balanced clock signal <NUM> as intermediate adjusted clock signal <NUM>, which is provided to clock aligning block <NUM> as the feedback clock signal. Clock delay circuit <NUM> includes a delay element configured to introduce some delay into the feedback balanced clock signal <NUM> according to delay value <NUM>, which results in intermediate adjusted clock signal <NUM>. Delay value <NUM> corresponds to the interconnect delay <NUM> from host die to die <NUM>. In some embodiments, delay value <NUM> is a delay control signal (e.g., a voltage signal that is proportional to interconnect delay <NUM>) utilized by clock delay circuit <NUM> to control the delay element (e.g., a variable delay line or a variable frequency oscillator) to introduce a delay time into feedback balanced clock signal <NUM>, where the delay time is equal to interconnect delay <NUM>. In other embodiments, delay value <NUM> is one or more delay control signals utilized to control one or more delay elements. In still other embodiments, delay value <NUM> is a delay code or other numerical value that represents the delay time equal to interconnect delay <NUM>. Clock delay circuit <NUM> is configured to determine a delay control signal corresponding to delay value <NUM>, where the delay control signal is utilized to control the delay element to introduce the delay time (equal to interconnect delay <NUM>) into feedback balanced clock signal <NUM>. In the embodiment illustrated in <FIG>, delay value <NUM> is determined at some time before operation of die <NUM> (e.g., during factory setting), where interconnect delay <NUM> is measured and a delay value <NUM> corresponding to the measured interconnect delay <NUM> is programmed in clock delay circuit <NUM> (e.g., in a register or other data storage element). In other embodiments, delay value <NUM> is provided by a user at a time during operation of die <NUM>. Examples of circuitry included in clock delay circuit <NUM> include, but are not limited to, a variable delay line, a variable frequency oscillator, and the like.

When clock aligning block <NUM> compares received source clock signal <NUM> and intermediate adjusted clock signal <NUM>, clock aligning block <NUM> is configured to output a master adjusted clock signal <NUM> that is adjusted to compensate for delay exhibited by intermediate adjusted clock signal <NUM>. It is noted that received source clock signal <NUM> is a delayed version of source clock signal <NUM> due to interconnect delay <NUM> and intermediate adjusted clock signal <NUM> is a delayed version of the feedback balanced clock signal <NUM> with a delay time equal to interconnect delay <NUM>. As a result of phase aligning the delayed versions of source clock signal <NUM> and feedback balanced clock signal <NUM> (i.e., by phase aligning received source clock signal <NUM> and intermediate adjusted clock signal <NUM>), the feedback balanced clock signal <NUM> and other balanced clock signals <NUM> distributed by clock distribution network <NUM> also become phase aligned with the source clock signal <NUM>. Clock aligning block <NUM> also adjusts master adjusted clock signal <NUM> to compensate for other delay exhibited by intermediate adjusted clock signal <NUM>, including CCB delay <NUM> and CDN delay <NUM>.

Once the balanced clock signals <NUM> distributed by clock distribution network <NUM> are phase aligned with the source clock signal <NUM>, the aligned clock signals <NUM> are used to clock on-chip synchronous logic <NUM> on die <NUM>, while source clock signal <NUM> is used to clock synchronous logic on the host die. One or more aligned clock signals <NUM> may each have a different clock frequency, where each clock signal <NUM> has a frequency that is some factor (e.g., multiple or fraction) of the frequency of master adjusted clock signal <NUM> or intermediate adjusted clock signal <NUM>. For example, an aligned clock signal <NUM> provided to on-chip synchronous logic <NUM> may have a clock frequency divided by two or four, as compared with the clock frequency of intermediate adjusted clock signal <NUM>. In such an example, a similarly divided clock signal may also be provided to synchronous logic on the host die. This results in synchronous communication between on-chip synchronous logic <NUM> on die <NUM> and synchronous logic on the host die. In this manner, a solution for aligning clock signals utilizing a static delay value is provided in <FIG>.

<FIG> illustrates a simplified block diagram depicting an example semiconductor device <NUM> of a system <NUM> in which the disclosure is implemented. In some embodiments, semiconductor device <NUM> is a die <NUM> that is an expansion device included in a system-in-package (SiP) package <NUM>, which also includes host die <NUM>. In other embodiments, semiconductor device <NUM> and a host semiconductor device <NUM> are part of a single die, where the semiconductor device <NUM> and host semiconductor device <NUM> are intraconnected devices on the single die. While die <NUM> and <NUM> include a great variety of components, many components are omitted in <FIG> to maintain simplicity.

Die <NUM> includes a number of components discussed above in connection with <FIG>, where like reference numbers indicate similar components. For example, die <NUM> includes level shifter <NUM>, on-chip synchronous logic <NUM>, clock aligning block <NUM>, clock control block <NUM>, clock distribution network <NUM>, and clock delay circuit <NUM>, which operate as similarly discussed above. While the embodiment illustrated in <FIG> includes a level shifter on die <NUM> and not on die <NUM>, it is noted that other embodiments provide for a level shifter on die <NUM> and not on die <NUM>. It is also noted that some other embodiments provide for a level shifter on both die <NUM> and on die <NUM>, and still other embodiments provide that a level shifter is not included on either die <NUM> or on die <NUM>.

Die <NUM> includes a host clock control block <NUM> that is configured to receive a master adjusted clock signal (not shown) and to output one or more generated clock signals to host clock distribution network <NUM>. Host clock distribution network <NUM> is balanced and distributes one or more clock signals, including source clock signal <NUM>, to on-chip synchronous logic <NUM> of die <NUM> in such a way that the synchronous elements receive logic level changes of the distributed clock signals simultaneously. On-chip synchronous logic <NUM> is configured to be in synchronous communication with on-chip synchronous logic <NUM> via data lines <NUM>, level shifter <NUM>, and data lines <NUM>. Also, bus and address control lines (not shown) are associated with data lines <NUM> and <NUM>. An example embodiment of on-chip synchronous logic <NUM> and <NUM> includes a synchronous bus that is configured to provide synchronous communication between die <NUM> and host die <NUM>.

Die interconnect delay <NUM> (or simply interconnect delay <NUM>) is an amount of delay that is introduced to source clock signal <NUM> as it travels from a point where source clock <NUM> is available to synchronous elements on host die <NUM> (e.g., at output of host clock distribution network <NUM>) through interconnect circuitry of host die <NUM> and interconnect circuitry (including through level shifter <NUM>) of die <NUM> to a point where received source clock signal <NUM> is available to clock aligning block <NUM>. In the embodiment illustrated in <FIG>, interconnect delay <NUM> is modeled to include LS delay <NUM> and die-to-die delay <NUM>, represented as delay elements <NUM> in <FIG>. Die-to-die delay <NUM> includes delay time introduced by various interconnect circuitry during transmission of source clock signal <NUM> from host die <NUM> to die <NUM> (excluding LS delay <NUM>). For example, die-to-die delay <NUM> may include propagation delay of buffers (not shown) utilized to strengthen source clock signal <NUM> before and after transmission between die <NUM> and <NUM>, as well as propagation delay of interconnect circuitry not shown in <FIG>. For simplicity's sake, die-to-die delay <NUM> is shown as being a same amount of delay in both directions, from die <NUM> to host die <NUM> (e.g., a path shown as node A to node B) and from host die <NUM> to die <NUM> (e.g., a path shown as node C to node D). In some embodiments, die-to-die delay <NUM> may be a different amount of delay in different directions.

Die <NUM> also includes a delay measure circuit <NUM> that is configured to dynamically measure interconnect delay <NUM> between host die <NUM> and die <NUM> (during operation of die <NUM>) using a loopback path over interconnect circuitry on die <NUM> that is coupled to interconnect circuitry on host die <NUM>. The loopback path is illustrated as a path traveling from delay measure circuit <NUM> as transmitted signal <NUM>, traverses level shifter <NUM>, traverses remaining interconnect circuitry from die <NUM> to host die <NUM> through nodes A and B, traverses the remaining interconnect circuitry returning from host die <NUM> to die <NUM> through nodes C and D, traverses level shifter <NUM>, and is received as received signal <NUM> at delay measure circuit <NUM>. Following loopback path, node A is located immediately before transmit interconnect circuitry of die <NUM>, node B is located immediately after receipt interconnect circuitry of host die <NUM>, node C is located immediately before transmit interconnect circuitry of host die <NUM>, and node D is located immediately after receipt interconnect circuitry of die <NUM>.

Delay measure circuit <NUM> is configured to output a transmitted signal <NUM> (or a measurement signal) through level shifter <NUM> to host die <NUM> via the first half of the loopback path. Host die <NUM> receives and returns the signal to die <NUM> via the second half of the loopback path through level shifter <NUM>, where delay measure circuit <NUM> receives the returned signal as received signal <NUM> (or a delayed measurement signal). As illustrated in <FIG>, the transmitted signal <NUM> experiences delay arising from traversing transmit interconnect circuitry on die <NUM> and receipt interconnect circuitry on host die <NUM>, which is represented as a die-to-die delay element <NUM> between nodes A and B. The transmitted signal <NUM> also experiences delay arising from traversing transmit interconnect circuitry on host die <NUM> and receipt interconnect circuitry on die <NUM>, which is also represented as a die-to-die delay element <NUM> between nodes C and D. Since the loopback path travels to die <NUM> and back to die <NUM>, the loopback path replicates twice the delay experienced by source clock signal <NUM> as it travels from die <NUM> to die <NUM>. As noted above, die-to-die delay <NUM> is the same amount of delay in both directions in the embodiments discussed herein. Delay measure circuit <NUM> is configured to measure the round-trip delay introduced into the transmitted signal <NUM> while traveling through level shifter <NUM> (which is LS delay <NUM>), along the first half of the loopback path through interconnect circuitry of die <NUM> and <NUM> (which is die-to-die delay <NUM>), along the second half of the loopback path through interconnect circuitry of die <NUM> and <NUM> (which is also die-to-die delay <NUM>), and through level shifter <NUM> (which is LS delay <NUM>).

It is noted that data signals also experience delay from similarly traversing interconnect circuitry on host die <NUM> and die <NUM>, which is also represented as a die-to-die delay element <NUM> between nodes N and O, which are on opposing sides of the coupled interconnect circuitry of die <NUM> and <NUM> (e.g., node N is similar in position to nodes B and C, while node O is similar in position to nodes A and D).

Delay measure circuit <NUM> is configured to measure the round-trip delay by comparing phases of the transmitted signal <NUM> (measurement signal) and the received signal <NUM> (delayed measurement signal) to determine the phase difference between the transmitted signal <NUM> and the received signal <NUM>. The phase difference indicates the total round-trip delay. Delay measure circuit <NUM> is configured to divide the total round-trip delay by two to determine the (one-way) interconnect delay <NUM> between host die <NUM> and die <NUM>. Delay measure circuit <NUM> then outputs a delay value <NUM> to clock delay circuit <NUM>, where delay value <NUM> corresponds to the interconnect delay <NUM>. In some embodiments, delay value <NUM> is a delay control signal (e.g., a voltage signal that is proportional to interconnect delay <NUM>) utilized by clock delay circuit <NUM> to control a delay element (e.g., a variable delay line or a variable frequency oscillator) to introduce a delay time into feedback balanced clock signal <NUM>, where the delay time is equal to interconnect delay <NUM>. In other embodiments, delay value <NUM> is a delay code or other numerical value that represents the delay time equal to interconnect delay <NUM>. Clock delay circuit <NUM> is configured to determine a delay control signal corresponding to delay value <NUM>, where the delay control signal is utilized to control a delay element that introduces the delay time (equal to interconnect delay <NUM>) into feedback balanced clock signal <NUM>. Since interconnect delay <NUM> is determined dynamically, delay value <NUM> is provided dynamically to clock delay circuit <NUM>. Examples of circuitry included in delay measure circuit <NUM> include, but are not limited to, a phase detector, and the like.

As similarly discussed above, clock delay circuit <NUM> is configured to output a delayed version of the feedback balanced clock signal <NUM>, according to delay value <NUM>, as intermediate adjusted clock signal <NUM>, which is provided to clock aligning block <NUM> as the feedback clock signal. When clock aligning block <NUM> compares received source clock signal <NUM> and intermediate adjusted clock signal <NUM>, clock aligning block <NUM> is configured to output a master adjusted clock signal <NUM> that is adjusted to compensate for delay exhibited by intermediate adjusted clock signal <NUM>. It is again noted that received source clock signal <NUM> is a delayed version of source clock signal <NUM> due to interconnect delay <NUM> and intermediate adjusted clock signal <NUM> is a delayed version of the feedback balanced clock signal <NUM> with a delay time equal to interconnect delay <NUM>. As a result of phase aligning the delayed versions of source clock signal <NUM> and balanced clock signal <NUM> (i.e., by phase aligning received source clock signal <NUM> and intermediate adjusted clock signal <NUM>), the feedback balanced clock signal <NUM> (and other balanced clock signals <NUM> distributed by clock distribution network <NUM>) also become phase aligned with the source clock signal <NUM>. Clock aligning block <NUM> also adjusts master adjusted clock signal <NUM> to compensate for other delay exhibited by intermediate adjusted clock signal <NUM>, including CCB delay <NUM> and CDN delay <NUM>.

Once the balanced clock signals <NUM> distributed by clock distribution network <NUM> are phase aligned with the source clock signal <NUM>, the aligned clock signals <NUM> are used to clock on-chip synchronous logic <NUM> on die <NUM>, while source clock signal <NUM> is used to clock synchronous logic <NUM> on host die <NUM>. This results in synchronous communication between on-chip synchronous logic <NUM> on die <NUM> and synchronous logic <NUM> on host die <NUM>. In this manner, a solution for aligning clock signals utilizing dynamic delay measurement is provided in <FIG>.

<FIG> illustrates a simplified block diagram depicting an example semiconductor device <NUM> of system <NUM> in which the disclosure is implemented. In some embodiments, semiconductor device <NUM> is a die <NUM> that is included in a system-in-package (SiP) package <NUM>, which also includes host die <NUM>. In other embodiments, semiconductor device <NUM> and a host semiconductor device <NUM> are part of a single die, where the semiconductor device <NUM> and the host semiconductor device <NUM> are intraconnected devices on the single die. While die <NUM> and <NUM> include a great variety of components, many components are omitted in <FIG> to maintain simplicity.

Die <NUM> includes a number of components discussed above in connection with <FIG> and <FIG>, where like reference numbers indicate similar components. For example, die <NUM> includes level shifter <NUM>, on-chip synchronous logic <NUM>, clock control block <NUM>, and clock distribution network <NUM>, which operate as similarly discussed above. Host die <NUM> includes a number of components discussed above in connection with <FIG>, where like reference numbers also indicate similar components. For example, die <NUM> includes host clock control block <NUM>, host clock distribution network <NUM>, and on-chip synchronous logic <NUM>, which operate as similarly discussed above. Host die <NUM> and die <NUM> are configured to be in die-to-die communication via data lines <NUM>, level shifter <NUM>, and data lines <NUM>, as similarly discussed above. While the embodiment illustrated in <FIG> includes a level shifter on die <NUM> and not on die <NUM>, it is noted that other embodiments provide for a level shifter on die <NUM> and not on die <NUM>. It is also noted that some other embodiments provide for a level shifter on both die <NUM> and on die <NUM>, and still other embodiments provide that a level shifter is not included on either die <NUM> or on die <NUM>.

Die <NUM> includes a clock alignment loop circuit, which in turn includes an interconnect delay clock adjusting block <NUM>, a combined delay clock adjusting block <NUM>, an on-chip delay measure circuit <NUM>, an on-chip delay clock adjusting block <NUM>, a clock control block <NUM>, a clock distribution network <NUM>, and an interconnect delay measure circuit <NUM>. The clock alignment loop circuit includes a generated clock signal path from interconnect delay clock adjusting block <NUM> (in combination with interconnect delay measure circuit <NUM>) to clock distribution network <NUM>, and a feedback signal path from clock distribution network <NUM> to combined delay clock adjusting block <NUM>. The clock alignment loop circuit is configured to align one or more local clock signals with source clock signal <NUM> to achieve a single clock domain between die <NUM> and die <NUM>.

Interconnect delay clock adjusting block <NUM> and interconnect delay measure circuit <NUM> are configured to dynamically determine interconnect delay <NUM> using a loopback path during operation of die <NUM>. The loopback path is illustrated as a path that traverses through level shifter <NUM> as received source clock signal <NUM> is transmitted to die <NUM>, traverses remaining interconnect circuitry from die <NUM> to die <NUM> through nodes A and B, traverses the remaining interconnect circuitry returning from host die <NUM> to die <NUM> through nodes C and D, traverses level shifter <NUM>, and is received as received signal <NUM> at interconnect delay measure circuit <NUM>. Following loopback path, node A is located immediately before transmit interconnect circuitry of die <NUM>, node B is located immediately after receipt interconnect circuitry of host die <NUM>, node C is located immediately before transmit interconnect circuitry of host die <NUM>, and node D is located immediately after receipt interconnect circuitry of die <NUM>. A transmitted signal (or measurement signal), such as the transmitted version of received source clock signal <NUM> in <FIG>, experiences delay arising from traversing interconnect circuitry on die <NUM> and interconnect circuitry on die <NUM>, which is represented by die-to-die delay element <NUM> between nodes A and B and between nodes C and D, as similarly discussed above. As noted above, die-to-die delay <NUM> is the same amount of delay in both directions in the embodiments discussed herein.

The transmitted signal also experiences delay arising from traversing one or more buffer elements <NUM> on die <NUM> and host die <NUM>, where the buffer elements <NUM> are utilized to strengthen the source clock signal <NUM> and received source clock signal <NUM>. Each buffer <NUM> also includes logic gate elements and introduces additional propagation delay. In the embodiment illustrated in <FIG>, interconnect delay <NUM> is modeled to include LS delay <NUM>, die-to-die delay <NUM> (excluding buffer delay <NUM> and LS delay <NUM>), and buffer delay <NUM> on both die <NUM> and die <NUM>. Although not shown, similar buffers <NUM> may also be implemented to strengthen data lines <NUM> on die <NUM> before transmission to die <NUM> and strengthen data lines <NUM> after being output by level shifter <NUM>, in some embodiments.

In order for the loopback path to accurately replicate the delay experienced by source clock signal <NUM> transmitted from host die <NUM> to die <NUM>, a buffer delay <NUM> is implemented on die <NUM> as part of the loopback path. Buffer delay <NUM> is configured to introduce a delay time equivalent to twice the total buffer delay time introduced by both buffers <NUM> on die <NUM> and on die <NUM>. For example, buffer delay <NUM> may represent four buffers <NUM> connected end to end on die <NUM> to introduce an equivalent buffer delay in the loopback path in order to accurately represent the total delay experienced by source clock signal <NUM> traveling round-trip from die <NUM> to die <NUM> and back to die <NUM>. By accurately replicating twice the delay experienced by source clock signal <NUM>, an accurate round-trip delay can be measured, which when halved yields an accurate interconnect delay <NUM> (which is half of the round-trip delay).

The loopback path replicates twice the delay experienced by source clock signal <NUM> as it travels from host die <NUM> to die <NUM>. Interconnect delay measure circuit <NUM> is configured to measure the total round-trip delay introduced into received source clock signal <NUM> while traveling along the loopback path. The total round-trip delay includes delay through level shifter <NUM> (which is LS delay <NUM>), along the first half of the loopback path through interconnect circuitry of die <NUM> and <NUM> (which is die-to-die delay <NUM>), through buffer delay <NUM>, along the second half of the loopback path through interconnect circuitry of die <NUM> and <NUM> (which is also die-to-die delay <NUM>), and through level shifter <NUM> (which is also LS delay <NUM>).

Interconnect delay measure circuit <NUM> has two inputs, the received signal <NUM> (or the delayed measurement signal) and a delayed clock signal <NUM> from interconnect delay clock adjusting block <NUM>. Interconnect delay measure circuit <NUM> is configured to measure the round-trip delay by comparing phases of received signal <NUM> and the delayed clock signal <NUM> to determine the phase difference between the received signal <NUM> and the delayed clock signal <NUM>. The phase difference indicates the round-trip delay. Based on the phase difference, interconnect delay measure circuit <NUM> is configured to output an increase/decrease (inc/dec) control signal <NUM>, which is provided to interconnect delay clock adjusting block <NUM>. Inc/dec control signal <NUM> indicates to interconnect delay clock adjusting block <NUM> whether the phase of the delayed clock signal <NUM> should be delayed by a greater or lesser amount of delay in order to phase align the delayed clock <NUM> with the received signal <NUM>. For example, if a positive clock edge of delayed clock signal <NUM> is received before a positive clock edge of received signal <NUM>, inc/dec control signal <NUM> indicates that the phase of delayed clock signal <NUM> should be delayed by a greater amount of delay in order to phase align with received signal <NUM> (e.g., control signal <NUM> indicates "increase" to clock adjusting block <NUM>). Similarly, if a positive clock edge of delayed clock signal <NUM> is received after a positive clock edge of received signal <NUM>, inc/dec control signal <NUM> indicates that the phase of delayed clock signal <NUM> should be delayed by a smaller amount of delay in order to phase align with received signal <NUM> (e.g., control signal <NUM> indicates "decrease" to clock adjusting block <NUM>). Examples of circuitry included in interconnect measure circuit <NUM> include, but are not limited to, a phase detector, and the like.

Interconnect delay clock adjusting block <NUM> has two inputs, the received source clock signal <NUM> and the increase/decrease control signal <NUM> from interconnect delay measure circuit <NUM>. Interconnect delay clock adjusting block <NUM> is configured to output a delayed version of receive source clock <NUM> (which is delayed or adjusted according to inc/dec control signal <NUM>, as described above) as the delayed clock signal <NUM> to interconnect delay measure circuit <NUM>. Interconnect delay clock adjusting block <NUM> also includes tracking circuitry to determine the round-trip delay by accumulating the amount of delay introduced to received source clock signal <NUM> (which results in delayed clock signal <NUM>) based on the on-going indications of inc/dec control signal <NUM>. In other words, the phase difference between received source clock <NUM> and delayed clock signal <NUM> (once delayed clock signal <NUM> is phase aligned or locked with received signal <NUM>) indicates the round-trip delay, where the phase difference is introduced by interconnect delay measure circuit <NUM> (e.g., incrementally or otherwise). Interconnect delay clock adjusting block <NUM> is configured to divide the round-trip delay by two to determine the (one-way) interconnect delay <NUM> from host die <NUM> to die <NUM>. Interconnect delay clock adjusting block <NUM> then outputs a delay code <NUM> to combined delay clock adjusting block <NUM>, where delay code <NUM> represents the delay time equal to interconnect delay <NUM>. In some embodiments, delay code <NUM> is also stored at interconnect delay clock adjusting block <NUM>. Since interconnect delay <NUM> is determined dynamically (and may change due to variations in voltage supply, temperature, electromagnetic interference, and the like), delay code <NUM> is also determined dynamically and provided to combined delay clock adjusting block <NUM>. Examples of circuitry included in interconnect delay clock adjusting block <NUM> include, but are not limited to, a variable delay line, a variable frequency oscillator, and similar circuitry that is configured to output an adjustable periodic clock signal utilized for delay measurement, as well as output a delay code reflecting the delay measurement.

Combined delay clock adjusting block <NUM> has two inputs, a feedback balanced clock <NUM> and the delay code <NUM>. Combined delay clock adjusting block <NUM> includes a delay element and circuitry configured to utilize delay code <NUM> to set or control the delay element to introduce the delay time (equal to interconnect delay <NUM>) into feedback balanced clock <NUM>, which is output as intermediate adjusted clock <NUM> to on-chip delay measure circuit <NUM>. In other embodiments (not shown), delay code <NUM> is a delay control signal (e.g., a voltage signal that is proportional to interconnect delay <NUM>) utilized by combined delay clock adjusting block <NUM> to control the delay element (e.g., a variable delay line or a variable frequency oscillator) to introduce a delay time (equal to interconnect delay <NUM>) into feedback balanced clock signal <NUM>. Examples of circuitry included in combined delay clock adjusting block <NUM> include but are not limited to a variable delay line, a variable frequency oscillator, and similar circuitry that is configured to output an adjustable periodic clock signal.

On-chip delay measure circuit <NUM> has two inputs, intermediate adjusted clock <NUM> and received source clock <NUM>. On-chip delay measure circuit <NUM> is configured to measure on-chip delay by comparing phases of intermediate adjusted clock signal <NUM> and received source clock signal <NUM> to determine the phase difference between the phases. The phase difference indicates the on-chip delay, which includes CCB delay <NUM> and CDN delay <NUM>. Based on the phase difference, on-chip delay measure circuit <NUM> is configured to output an increase/decrease (inc/dec) control signal <NUM>, which is provided to on-chip delay clock adjusting block <NUM>. Inc/dec control signal <NUM> indicates to on-chip delay clock adjusting block <NUM> whether the phase of intermediate adjusted clock <NUM> should be delayed by a greater or lesser amount of delay in order to phase align intermediate adjusted clock <NUM> with received source clock signal <NUM>, as similarly discussed above in connection with inc/dec control signal <NUM> of interconnect delay measure circuit <NUM>. Examples of circuitry included in on-chip delay measure circuit <NUM> include, but are not limited to, a phase detector, and the like.

On-chip delay clock adjusting block <NUM> has two inputs, received source clock signal <NUM> and the increase/decrease control signal <NUM> from on-chip delay measure circuit <NUM>. On-chip delay clock adjusting block <NUM> is configured to output a delayed version of received source clock <NUM> (which is delayed or adjusted according to inc/dec control signal <NUM>, as described above) as the master adjusted clock signal <NUM> to clock control block <NUM>. The phase of master adjusted clock signal <NUM> compensates for on-chip delay (including CCB delay <NUM> and CDN delay <NUM>) exhibited by intermediate adjusted clock <NUM>, as compared with received source clock <NUM> by on-chip delay measure circuit <NUM>. The phase of master adjusted clock signal <NUM> also compensates for interconnect delay <NUM> (including die-to-die delay <NUM>, LS delay <NUM>, and delay arising from one or more buffers <NUM>). Master adjusted clock <NUM> is provided to clock control block <NUM>, as similarly discussed above.

It is again noted that received source clock signal <NUM> is a delayed version of source clock signal <NUM> due to interconnect delay <NUM>. The intermediate adjusted clock signal <NUM> is a delayed version of the feedback balanced clock signal <NUM> by a delay time equal to interconnect delay <NUM>. As a result of phase aligning the delayed versions of source clock signal <NUM> and balanced clock signal <NUM> (i.e., by phase aligning received source clock signal <NUM> and intermediate adjusted clock signal <NUM>), the feedback balanced clock signal <NUM> (and other balanced clock signals <NUM> distributed by clock distribution network <NUM>) also become phase aligned with the source clock signal <NUM>.

Once the balanced clock signals <NUM> distributed by clock distribution network <NUM> are phase aligned with the source clock signal <NUM>, the aligned clock signals <NUM> are used to clock on-chip synchronous logic <NUM> on die <NUM>, while source clock signal <NUM> is used to clock synchronous logic <NUM> on the host die <NUM>. This results in synchronous communication between on-chip synchronous logic <NUM> on die <NUM> and synchronous logic <NUM> on the host die <NUM>. In this manner, a solution for aligning clock signals utilizing dynamic delay measurement is provided in <FIG>.

<FIG> illustrates waveforms of example clock signals present at a plurality of nodes of a semiconductor device in which the present disclosure is implemented. The waveforms illustrate the introduction of delay into source clock signal <NUM> and the compensation of such delay to achieve aligned clocks <NUM> that are phase aligned with the source clock signal <NUM>. While the waveforms illustrated in <FIG> are explained herein using the embodiment of the present disclosure illustrated in <FIG> involving die <NUM> and host die <NUM>, similar waveforms exist for other embodiments, as will be noted below. The illustrated waveforms are present after phase alignment of source clock signal <NUM> and balanced clock signals <NUM> (which are also referred to as aligned clock signals <NUM>).

Source clock signal <NUM> is illustrated at the top of <FIG>, with received clock signal <NUM> illustrated immediately below. It is noted that a phase difference exists between source clock signal <NUM> and received clock signal <NUM>, as illustrated by the positive edge of received clock signal <NUM> following the positive edge of source clock signal <NUM> by die-to-die delay <NUM> and level shifter (LS) delay <NUM>. The sum of this delay is interconnect delay <NUM>, and in some embodiments (such as the embodiment discussed in connection with <FIG>) is measured directly at a time prior to device operation (e.g., during a factory setting period of time prior to runtime operation) and a representation of such interconnect delay <NUM> is programmed as delay value <NUM> into clock delay circuit <NUM>, as discussed above. In such an embodiment, interconnect delay <NUM> is introduced into aligned clocks <NUM> prior to clock alignment block <NUM>, which phase aligns received clock signal <NUM> and intermediate adjusted clock <NUM>. Since both source clock <NUM> and aligned clocks <NUM> are delayed by the same amount of interconnect delay <NUM>, source clock signal <NUM> and aligned clocks <NUM> are also phase aligned.

In order to measure interconnect delay <NUM> in some embodiments (such as the embodiments discussed in connection with <FIG> and <FIG>), a signal is transmitted on a loopback path that includes nodes A, B, C, and D in order to determine a round trip delay <NUM>, as discussed above. For simplicity's sake, transmitted signal <NUM> is illustrated as the same waveform of received clock signal <NUM>, although transmitted signal <NUM> may actually be another waveform that has some phase difference from received clock signal <NUM>. For example, in the embodiment of <FIG>, received clock signal <NUM> is transmitted to host die <NUM> and is equivalent to transmitted signal <NUM> (not labeled in <FIG>), where transmitted signal <NUM> has the same waveform as received clock signal <NUM>. By contrast, the transmitted signal <NUM> in the embodiment of <FIG> is independent from received clock signal <NUM>, where transmitted signal <NUM> has a different waveform than received clock signal <NUM> (and would thus likely have some phase difference from received clock signal <NUM>).

Regardless of the presence of any relationship between received clock signal <NUM> and transmitted signal <NUM>, it is noted that a phase difference exists between the waveforms of transmitted signal <NUM> and node A signal, as illustrated by the positive edge of node A signal following the positive edge of transmitted signal <NUM> by LS delay <NUM>. LS delay <NUM> arises as the transmitted signal <NUM> traverses LS shifter <NUM> to node A. Similarly, a phase difference exists between the waveforms of nodes A and B, as illustrated by the positive edge of node B signal following the positive edge of node A signal by die-to-die delay <NUM>. Die-to-die delay <NUM> arises as the node A signal traverses the transmit interconnect circuitry of die <NUM> and the receipt interconnect circuitry of host die <NUM> to node B.

Since the embodiment of <FIG> indicates that the node B signal is immediately returned to die <NUM>, the node C signal is illustrated as the same waveform of node B signal. In the embodiment of <FIG>, the waveforms of nodes B and C would have a phase difference equal to the buffer delay <NUM>, which would also increase the (overall) interconnect delay <NUM> and the round-trip delay <NUM>.

It is noted that a phase difference exists between the waveforms of nodes C and D, as illustrated by the positive edge of node D following the positive edge of node C by die-to-die delay <NUM>. Die-to-die delay <NUM> arises as the node C signal traverses the transmit interconnect circuitry of host die <NUM> and the receipt interconnect circuitry of die <NUM> to node D. Similarly, a phase difference exists between the waveforms of node D and received signal <NUM>, as illustrated by the positive edge of received signal <NUM> following the positive edge of node D by LS delay <NUM>. LS delay <NUM> arises as the node D signal traverses LS shifter <NUM> to an input of delay measure circuit <NUM>.

As the transmitted signal traverses the loopback path, delay introduced to the transmitted signal <NUM> accumulates, resulting in round trip delay <NUM>. In other words, a phase difference equal to the round-trip delay <NUM> exists between transmitted signal <NUM> and received signal <NUM>. The round-trip delay <NUM> is equal to twice the interconnect delay <NUM>. Once the round-trip delay <NUM> is determined, interconnect delay <NUM> is determined by dividing round-trip delay <NUM> by two.

Master adjusted clock <NUM> is shown with a phase that has been adjusted to compensate for both on-chip delay and interconnect delay <NUM>. As discussed above, clock alignment block <NUM> is configured to phase align received source clock signal <NUM> and intermediate adjusted clock <NUM> by adjusting the delay of master adjusted clock signal <NUM>. As shown in <FIG>, master adjusted clock <NUM> experiences CCB delay <NUM> as it traverses clock control block <NUM> and is output as one or more generated clock signals <NUM>. The generated clock signals <NUM> then experience CDN delay <NUM> as the generated clock signals traverse the clock distribution network <NUM> and are output as aligned clocks <NUM>. Finally, clock delay circuit <NUM> introduces delay <NUM> to aligned clocks <NUM> immediately before clock alignment block <NUM>, resulting in intermediate adjusted clock <NUM>. Thus, the position of a rising edge of master adjusted clock <NUM> is adjusted to compensate for the delays that include CCB delay <NUM>, CDN delay <NUM>, and interconnect delay <NUM> between master adjusted clock <NUM> and intermediate adjusted clock <NUM>. Further, since intermediate adjusted clock <NUM> is a delayed version of aligned clocks <NUM> and received clock signal <NUM> is a delayed version of source clock signal <NUM>, source clock <NUM> and aligned clocks <NUM> are also phase aligned as a result of phase aligning intermediate adjusted clock <NUM> with received clock signal <NUM>.

<FIG> illustrates waveforms of example data signals present at a plurality of nodes of a semiconductor device in which the disclosure is implemented. The waveforms illustrate synchronous communication achieved between two semiconductor devices, or die, within the same clock domain.

Data signals being received by a die, such as by any of the die discussed above in connection with <FIG>, <FIG>, and <FIG>, is illustrated on the top half of <FIG>. Node N data signal that is transmitted from a host die (e.g., die <NUM> or <NUM>) and received on a secondary die (e.g., die <NUM>, <NUM>, or <NUM>), experiences some propagation delay from on-chip synchronous logic <NUM> on the host die before being transmitted, as illustrated by the edge of node N valid data following the positive edge of aligned clock <NUM> (which is phase aligned with source clock signal <NUM>) by some clock-to-output delay of registers in on-chip synchronous logic <NUM>.

Node O data signal experiences die-to-die delay <NUM> as the data signal traverses transmit interconnect circuitry of the host die and the receipt interconnect circuitry of the secondary die, as illustrated by the edge of node O valid data following the edge of node N valid data by die-to-die delay <NUM>. Node P data signal experiences LS delay <NUM> as the data signal traverses LS shifter <NUM> to node P, as illustrated by the edge of node P valid data following the edge of node O valid data by LS delay <NUM>. The edge of valid data of node P signal occurs at a time before the next positive edge of aligned clock <NUM> to satisfy setup time requirements of elements within on-chip synchronous logic <NUM> of the secondary die. The valid data of node P signal also remains stable for a time after the positive edge of aligned clock <NUM> to satisfy hold time requirements of elements within on-chip synchronous logic <NUM> of the secondary die.

Data signals being transmitted by a die, such as from any of the die discussed above in connection with <FIG>, <FIG>, and <FIG>, is illustrated on the bottom half of <FIG>. Node P data signal that is transmitted from the secondary die (e.g., die <NUM>, <NUM>, or <NUM>) and received on the host die (e.g., die <NUM> or <NUM>), experiences some propagation delay from on-chip synchronous logic <NUM> on the secondary die before being transmitted, as illustrated by the edge of node P valid data following the positive edge of aligned clock <NUM> (which is phase aligned with source clock signal <NUM> on die <NUM> or <NUM>) by some clock-to-output delay from a register in on-chip synchronous logic <NUM>.

Node O data signal experiences LS delay <NUM> as the data signal traverses LS shifter <NUM>, as illustrated by the edge of node O valid data following the edge of node P valid data by LS delay <NUM>. Node N data signal experiences die-to-die delay <NUM> as the data signal traverses transmit interconnect circuitry of the secondary die and receipt interconnect circuitry of the host die, as illustrated by the edge of node N valid data following the edge of node O valid data by die-to-die delay <NUM>. The edge of valid data of node N occurs at a time before the next positive edge of source clock <NUM> to satisfy setup time requirements of element within on-chip synchronous logic <NUM> of the host die. The valid data of node N signal also remains stable for a time after the positive edge of source clock <NUM> to satisfy hold time requirements of elements within on-chip synchronous logic <NUM> of the host die.

By now it should be appreciated that there have been provided embodiments for adaptive clock signal alignment, which compensates for interconnect delay between semiconductor devices and automatically adjusts a local clock signal to be aligned with a source clock signal of a host device. In one embodiment of the present disclosure, a semiconductor device is provided that includes a clock delay circuit configured to receive a delay value associated with an interconnect delay, where the interconnect delay is measured across interconnect circuitry that communicatively couples a host semiconductor device with the semiconductor device. The clock delay circuit is also configured to delay a local clock signal by an amount of delay indicated by the delay value, where the local clock signal is generated on the semiconductor device. The semiconductor device also includes a clock alignment block configured to receive a delayed local clock signal from the clock delay circuit, receive a delayed source clock signal, where the delayed source clock signal is received from the host semiconductor device via the interconnect circuitry, and output a master clock signal based on a comparison of the delayed source clock signal and the delayed local clock signal, the master clock signal being adjusted to compensate for delay in the delayed local clock signal by phase aligning the delayed source clock signal and the delayed local clock signal. The master clock signal is utilized to generate one or more aligned clock signals on the semiconductor device that are aligned with a source clock signal generated on the host semiconductor device. The clock delay circuit is configured to receive one of the one or more aligned clock signals as the local clock signal.

One aspect of the above embodiment provides that the semiconductor device further includes synchronous logic configured to utilize one of the one or more aligned clock signals as a local source clock signal, where the synchronous logic is configured for synchronous communication with host synchronous logic in the host semiconductor device, and the host synchronous logic is configured to utilize the source clock signal.

Another aspect of the above embodiment provides that the semiconductor device further includes a clock control block configured to utilize the master clock signal to output one or more generated clock signals, where the one or more generated clock signals include a first local delay introduced by the clock control block.

A further aspect of the above embodiment provides that the semiconductor device further includes a clock distribution network configured to distribute the one or more generated clock signals as one or more aligned clock signals to synchronous elements on the semiconductor device, where the one or more generated clock signals include a second local delay introduced by the clock distribution network, where the clock alignment block is further configured to adjust the master clock signal to compensate for the first local delay and the second local delay.

Another aspect of the above embodiment provides that the semiconductor device includes a first semiconductor die, the host semiconductor device includes a second semiconductor die, and the first semiconductor die and the second semiconductor die are included in a package.

Another aspect of the above embodiment provides that the delay value includes one of a factory-stored nonvolatile value and a user-provided nonvolatile value.

Another aspect of the above embodiment provides that the semiconductor device further includes a delay measure circuit configured to measure the interconnect delay, where the delay measure circuit is further configured to transmit a measurement signal to the host semiconductor device via the interconnect circuitry, receive a delayed measurement signal from the host semiconductor device via the interconnect circuitry, compare the measurement signal and the delayed measurement signal to determine a round-trip delay, calculate the interconnect delay from the round-trip delay, and output the delay value that indicates the interconnect delay to the clock delay circuit.

A further aspect of the above embodiment provides that the delay measure circuit is configured to transmit the measurement signal on a loopback path that includes a first path from an output of the delay measure circuit to the host semiconductor device that traverses the interconnect circuitry and a second path from the host semiconductor device to an input of the delay measure circuit that traverses the interconnect circuitry, and the delay measure circuit is configured to receive the delayed measurement signal from the second path.

Another further aspect of the above embodiment provides that the interconnect circuitry includes a first set of transmit circuitry on the semiconductor device and a first set of receive circuitry on the host semiconductor device, the interconnect circuitry includes a second set of transmit circuitry on the host semiconductor device and a second set of receive circuitry on the host semiconductor device, the first path of the loopback path traverses the first sets of transmit and receive circuitry, the first path is associated with a die-to-die delay, the second path of the loopback path traverses the second sets of transmit and receive circuitry, and the second path is associated with the die-to-die delay.

Another further aspect of the above embodiment provides that the interconnect circuitry includes a level shifter, the interconnect delay includes a delay associated with the level shifter, and the first path and the second path of the loopback path each traverse the level shifter.

Another further aspect of the above embodiment provides that the interconnect circuitry includes a first set of buffer elements associated with a first overall buffer delay, the loopback path traverses a second set of buffer elements associated with a second overall buffer delay, and the second overall buffer delay includes twice the first overall buffer delay.

In another embodiment of the present disclosure, a method is provided that includes receiving a delay value associated with an interconnect delay, where the interconnect delay is measured across interconnect circuitry that communicatively couples a host semiconductor device with a semiconductor device. The method also includes delaying a local clock signal by an amount of time delay indicated by the delay value to produce a delayed local clock signal, where the local clock signal is generated on the semiconductor device; receiving a delayed source clock signal, where the delayed source clock signal is received from the host semiconductor device via the interconnect circuitry; and outputting a master clock signal based on a comparison of the delayed source clock signal and the delayed local clock signal the master clock signal being adjusted to compensate for delay in the delayed local clock signal by phase aligning the delayed source clock signal and the delayed local clock signal. The master clock signal is utilized to generate one or more aligned clock signals on the semiconductor device that are aligned with a source clock signal generated on the host semiconductor device. The local clock signal is one of the one or more aligned clock signals.

One aspect of the above embodiment provides that the method further includes clocking synchronous logic with one of the one or more aligned clock signals, where the synchronous logic is configured for synchronous communication with host synchronous logic in the host semiconductor device, and the host synchronous logic is configured to utilize the source clock signal.

Another aspect of the above embodiment provides that the method further includes generating one or more generated clock signals based on the master clock signal, where the one or more generated clock signals include a first local delay introduced by the generating.

A further aspect of the above embodiment provides that the method further includes distributing the one or more generated clock signals as one or more aligned clock signals to synchronous elements on the semiconductor device, where the one or more aligned clock signals include a second local delay introduced by the distributing; and adjusting the master clock signal to compensate for the first local delay and the second local delay.

Another aspect of the above embodiment provides that the method further includes measuring the interconnect delay, the measuring includes transmitting a measurement signal to the host semiconductor device via the interconnect circuitry, receiving a delayed measurement signal from the host semiconductor device via the interconnect circuitry, comparing the measurement signal and the delayed measurement signal to determine a round-trip delay, calculating the interconnect delay from the round-trip delay, and outputting the delay value that indicates the interconnect delay to the clock delay circuit.

The measurement signal may be transmitted on a loopback path that includes a first path from the semiconductor device to the host semiconductor device that traverses the interconnect circuitry and a second path from the host semiconductor device to the semiconductor device that traverses the interconnect circuitry, and the delayed measurement signal is received from the second path of the loopback path.

The interconnect circuitry may include a first set of transmit circuitry on the semiconductor device and a first set of receive circuitry on the host semiconductor device, the interconnect circuitry includes a second set of transmit circuitry on the host semiconductor device and a second set of receive circuitry on the host semiconductor device, the first path of the loopback path traverses the first sets of transmit and receive circuitry, the first path is associated with a die-to-die delay, the second path of the loopback path traverses the second sets of transmit and receive circuitry, and the second path is associated with the die-to-die delay.

The interconnect circuitry may include a level shifter, the interconnect delay may include a delay associated with the level shifter, and the first path and the second path of the loopback path each traverse the level shifter.

The interconnect circuitry may include a first set of buffer elements associated with a first overall buffer delay, the loopback path may traverse a second set of buffer elements associated with a second overall buffer delay, and the second overall buffer delay includes twice the first overall buffer delay.

A semiconductor device may be provided that includes a delay measure circuit configured to determine a round-trip delay based on a comparison of a measurement signal and a delayed measurement signal. Interconnect circuitry communicatively couples a host semiconductor device and the semiconductor device, the measurement signal is transmitted to the host semiconductor device via the interconnect circuitry, and the delayed measurement signal is received from the host semiconductor device via the interconnect circuitry. The delay measure circuit is also configured to calculate an interconnect delay of the interconnect circuitry based on the round-trip delay. The semiconductor device also includes a clock alignment loop circuit configured to generate a local source clock signal on the semiconductor device, delay the local source clock signal by the interconnect delay to generate a delayed local source clock signal, and receive a delayed host source clock signal, where the delayed host source clock signal is received from the host semiconductor device via the interconnect circuitry. The clock alignment loop circuit is also configured to generate a master clock signal based on a comparison of the delayed local source clock signal and the delayed host source clock signal, where the master clock signal is utilized to generate an aligned local source clock signal that is aligned with a host source clock signal generated on the host semiconductor device.

A semiconductor device may be provided that includes an interconnect delay clock adjusting block configured to receive a delayed host source clock signal, where interconnect circuitry communicatively couples a host semiconductor device and the semiconductor device, and the delayed host source clock signal is received from the host semiconductor device via the interconnect circuitry. The interconnect delay clock adjusting block is also configured to output an intermediate clock signal based on the delayed host source clock signal. The semiconductor device also includes an interconnect delay measure circuit configured to output a first control signal based on the intermediate clock signal and a comparison of a delayed measurement signal, where the delayed host source clock signal is immediately transmitted to the host semiconductor device via the interconnect circuitry as a measurement signal, the delayed measurement signal is received from the host semiconductor device via the interconnect circuitry. The interconnect delay clock adjusting block is further configured to delay the intermediate clock signal based on the first control signal, and track an amount of delay introduced into the intermediate clock signal. The interconnect delay measure circuit is further configured to determine a delay code based on the amount of delay, where the delay code corresponds to an interconnect delay of the interconnect circuitry. The semiconductor device also includes a combined delay clock adjusting block configured to adjust a local source clock signal based on the delay code to generate a delayed local source clock signal; and an on-chip delay measure circuit configured to output a second control signal based on a comparison of the delayed host source clock signal and the delayed local source clock signal. The semiconductor device also includes an on-chip delay clock adjusting block configured to adjust the delayed host source clock signal based on the second control signal to output a master clock signal, where the master clock signal is utilized to generate an aligned local source clock signal that is aligned with a host source clock signal generated on the host semiconductor device.

The circuitry described herein may be implemented on a semiconductor substrate, which can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.

As used herein, the term "bus" is used to refer to a plurality of signals or conductors which may be used to transfer one or more various types of information, such as data, addresses, control, or status. The conductors as discussed herein may be illustrated or described in reference to being a single conductor, a plurality of conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, separate unidirectional conductors may be used rather than bidirectional conductors and vice versa. Also, plurality of conductors may be replaced with a single conductor that transfers multiple signals serially or in a time multiplexed manner. Likewise, single conductors carrying multiple signals may be separated out into various different conductors carrying subsets of these signals. Therefore, many options exist for transferring signals.

The terms "assert" or "set" and "negate" (or "deassert" or "clear") are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.

Each signal described herein may be designed as positive or negative logic, where negative logic can be indicated by a bar over the signal name or an asterix (*) following the name. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein can be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

The term "coupled," as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.

Claim 1:
A semiconductor device (<NUM>) comprising:
a clock delay circuit (<NUM>) configured to:
receive a delay value (<NUM>) associated with an interconnect delay (<NUM>), wherein the interconnect delay (<NUM>) is measured across interconnect circuitry that communicatively couples a host semiconductor device (<NUM>) with the semiconductor device (<NUM>), and
delay a local clock signal by an amount of time delay indicated by the delay value (<NUM>), wherein the local clock signal is generated on the semiconductor device (<NUM>); and
a clock alignment block (<NUM>) configured to:
receive a delayed local clock signal (<NUM>) from the clock delay circuit (<NUM>),
receive a delayed source clock signal (<NUM>), wherein the delayed source clock signal (<NUM>) is received from the host semiconductor device (<NUM>) via the interconnect circuitry, and
output a master clock signal (<NUM>), based on a comparison of the delayed source clock signal (<NUM>) and the delayed local clock signal (<NUM>), the master clock signal being adjusted to compensate for delay in the delayed local clock signal (<NUM>) by phase aligning the delayed source clock signal (<NUM>) and the delayed local clock signal (<NUM>), wherein the master clock signal (<NUM>) is utilized to generate one or more aligned clock signals (<NUM>) on the semiconductor device (<NUM>) that are aligned with a source clock signal (<NUM>) generated on the host semiconductor device (<NUM>), and wherein the clock delay circuit (<NUM>) is configured to receive one of the one or more aligned clock signals (<NUM>) as the local clock signal.