Patent Description:
Power semiconductor module arrangements often include a base plate within a housing. At least one substrate is arranged on the base plate. A semiconductor arrangement including a plurality of controllable semiconductor components (e.g., two IGBTs in a half-bridge configuration) is usually arranged on at least one of the at least one substrate. Each substrate usually comprises a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer and a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor components are mounted, for example, on the first metallization layer. The first metallization layer may be a structured layer while the second metallization layer is usually a continuous layer. The second metallization layer is usually attached to the base plate.

Heat that is generated by the controllable semiconductor components is dissipated through the substrate to the base plate or to a heat sink. As the first metallization layer usually is a structured layer, the distribution of the electrical fields occurring in the substrate during the use of the semiconductor arrangement is not homogenous and may result in local spikes. In areas of high field strength, partial discharging effects may occur. These partial discharging effects may result in a degradation of the substrate layer which may reduce the lifetime of the power semiconductor module arrangement.

Document <CIT> discloses a method for manufacturing a body. In the cross section orthogonal to the joint surface, the average diameter of the second phase particles <NUM> is <NUM> or more and <NUM> or less, and the major axis and minor axis of the corresponding ellipse when the second phase particle is regarded as an ellipse. The average value of the ratio is <NUM> or more and <NUM> or less. Furthermore, <NUM>% or more of the second phase particles have an orientation angle of <NUM> ° or less and an average orientation angle of <NUM> ° or more and <NUM> ° or less.

Document <CIT> discloses a method for forming substrate formed from a mixture of highly purified aluminium-oxide (Al2O3), zirconium-oxide (ZrO2), and an organic bonding material by conventional injection moulding. Apertures, blank spaces, circuit vias, cooling grooves, etc. may be formed at the same time. The substrate is then sintered and selectively etched to give a rough surface. This ensures a secure bond between the substrate and the metal layers formed by galvanisation, which comprise the PCB. For optimum adhesion between the metal and the substrate the purity of the aluminium-oxide must be \><NUM>% (pref.

Document <CIT> discloses a ceramic substrate comprising a core layer and a plurality of surface layers, optionally it further comprises a plurality of transition layers. The core layer is made of zirconia toughened alumina; the surface layers symmetrically located on the upper and lower surfaces of the core layer are made of Al<NUM>O <NUM>; and the transition layers symmetrically located between the surface layer and the core layer are made of zirconia toughened alumina. The core layer has a chemical composition of 0wt%<ZrO <NUM>≤40wt% and 60wt%≤Al <NUM>O <NUM><100wt%.

Document <CIT> discloses a copper-ceramic composite comprising a ceramic substrate containing alumina, a coating of copper or a copper alloy present on the ceramic substrate, wherein the copper or copper alloy has a number distribution of grain sizes with a median d <NUM> , an arithmetic mean d arith and a symmetry value S (Cu) = d <NUM> / d arith , the alumina has a number distribution of grain sizes with a median d <NUM> , an arithmetic mean value d arith and a symmetry value S (Al<NUM>O<NUM>) = d <NUM> / d arith , and S (Al <NUM>O<NUM>) and S (Cu) satisfy the following condition: <NUM> ≦ S (Al <NUM> O <NUM> ) / S (Cu) ≤ <NUM>.

Document <CIT> discloses shaped ceramic products characterised by their composition, Ceramics compositions, Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on non-oxide ceramics based on borides, nitrides, i.e. nitrides, oxynitrides, carbonitrides or oxycarbonitrides or silicides based on silicon nitride.

There is a need for an improved semiconductor substrate which has a good thermal conductivity and an increased resistance against partial discharging effects.

A semiconductor substrate includes a dielectric insulation layer, and a first metallization layer attached to the dielectric insulation layer. The dielectric insulation layer comprises a first material having a thermal conductivity of between <NUM> and <NUM> W/mK, and an insulation strength of between <NUM> and <NUM> kV/mm, and a second electrically conducting or semiconducting material, wherein the second material is distributed within the first material. The first material comprises one of AlN, and Si3N4, and the second material comprises ZrN.

The components in the figures are not necessarily to scale, emphasis is instead being placed upon illustrating the principles of the invention.

In the following detailed description, reference is made to the accompanying drawings. The drawings show specific examples in which the invention may be practiced. It is to be understood that the features and principles described with respect to the various examples may be combined with each other, unless specifically noted otherwise. In the description as well as in the claims, designations of certain elements as "first element", "second element", "third element" etc. are not to be understood as enumerative. Instead, such designations serve solely to address different "elements". That is, e.g., the existence of a "third element" does not require the existence of a "first element" and a "second element". A semiconductor body as described herein may be made from (doped) semiconductor material and may be a semiconductor chip or be included in a semiconductor chip. A semiconductor body has electrically connecting pads and includes at least one semiconductor element with electrodes.

<FIG> exemplarily illustrates a power semiconductor module arrangement comprising a semiconductor substrate <NUM>. The semiconductor substrate <NUM> includes a dielectric insulation layer <NUM>, a structured first metallization layer <NUM> attached to the dielectric insulation layer <NUM>, and a second metallization layer <NUM> attached to the dielectric insulation layer <NUM>. The dielectric insulation layer <NUM> is disposed between the first and second metallization layers <NUM>, <NUM>. The power semiconductor module arrangement may further comprise a housing <NUM>, wherein the housing <NUM> may comprise sidewalls and a cover.

Each of the first and second metallization layers <NUM>, <NUM> may consist of or include one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; any other metal or alloy that remains solid during the operation of the power semiconductor module arrangement. The semiconductor substrate <NUM> is a ceramic substrate, that is, a substrate in which the dielectric insulation layer <NUM> is a ceramic, e.g., a thin ceramic layer. The ceramic may consist of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulation layer <NUM> may consist of or include one of the following materials: Al<NUM>O<NUM>, AlN, or Si<NUM>N<NUM>. For instance, the substrate may, e.g., be a Direct Copper Bonding (DCB) substrate, a Direct Aluminium Bonding (DAB) substrate, or an Active Metal Brazing (AMB) substrate. The dielectric insulation layer <NUM> generally comprises a high insulation resistance while, at the same time, having a low thermal conduction coefficient.

Usually one or more semiconductor bodies <NUM> are arranged on a semiconductor substrate <NUM>. Each of the semiconductor bodies <NUM> arranged on a semiconductor substrate <NUM> may include a diode, an IGBT (Insulated-Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a JFET (Junction Field-Effect Transistor), a HEMT (High-Electron-Mobility Transistor), or any other suitable controllable semiconductor element. One or more semiconductor bodies <NUM> may form a semiconductor arrangement on the semiconductor substrate. In <FIG>, two semiconductor bodies <NUM> are exemplarily illustrated. Any other number of semiconductor bodies <NUM>, however, is also possible.

The semiconductor substrate <NUM> may be attached to a base plate or heat sink <NUM> with the second metallization layer <NUM> arranged between the dielectric insulation layer <NUM> and the base plate/heat sink <NUM>. This, however, is only an example. Other semiconductor module arrangements are known, wherein the semiconductor substrate <NUM> comprises only a first metallization layer <NUM>, and wherein the second metallization layer <NUM> is omitted. In such power semiconductor module arrangements, the dielectric insulation layer <NUM> may form the base plate and may be attached to a heat sink <NUM> without a second metallization layer <NUM> arranged between the dielectric insulation layer <NUM> and the heat sink <NUM>. Heat that is generated by the semiconductor bodies <NUM> may be dissipated through the semiconductor substrate <NUM> to the base plate or heat sink <NUM>. This is exemplarily illustrated by the bold arrows in <FIG>. The second metallization layer <NUM> of the semiconductor substrate <NUM> in <FIG> is a continuous layer. The first metallization layer <NUM> of the semiconductor substrate <NUM> in <FIG> is a structured layer in the arrangement illustrated in <FIG>. "Structured layer" means that the first metallization layer <NUM> is not a continuous layer, but includes recesses between different sections of the layer. Such recesses are schematically illustrated in <FIG>. The first metallization layer <NUM> in this arrangement exemplarily includes four different sections. Different semiconductor bodies <NUM> may be mounted to the same or to different sections of the first metallization layer <NUM>. Different sections of the first metallization layer <NUM> may have no electrical connection or may be electrically connected to one or more other sections using electrical connections such as, e.g., bonding wires. Electrical connections may also include connection plates or conductor rails, for example, to name just a few examples. The first metallization layer <NUM> being a structured layer, however, is only an example. It is also possible that the first metallization layer <NUM> is a continuous layer.

During the use of the power semiconductor module arrangement, electrical fields are generated within the arrangement. Such electrical fields may be inhomogeneously distributed within the dielectric insulation layer <NUM>. Typical voltages during the use of a semiconductor arrangement range up to 6500V AC RMS (root mean square), for example, resulting in electric field strengths within the dielectric insulation layer <NUM> of up to <NUM> kV/mm and even more, especially in areas adjacent to the (structured) first metallization layer <NUM> (adjacent to the junction between the first metallization layer <NUM> and the dielectric insulation layer <NUM>). Due to the high electric field strengths, the insulation strength of the dielectric insulation layer <NUM> may be exceeded, resulting in partial discharging effects in some parts of the dielectric insulation layer <NUM>. Partial discharging effects usually are slow-growing degradations of the ceramic material, typically close to the surface in areas where a junction is formed between the first metallization layer <NUM> and the dielectric insulation layer <NUM>. This is schematically illustrated in <FIG>, which exemplarily illustrates a section A of the semiconductor substrate <NUM> of <FIG>. As can be seen in <FIG>, the degradations usually extend tree-like into the dielectric insulation layer <NUM>, thereby weakening the dielectric insulation layer <NUM>.

Degradations caused by partial discharging effects are linked to several physical principles. On the one hand, they depend on the electric field strength, as already mentioned before. On the other hand, they depend on the average free length of path within the dielectric insulation layer <NUM>, which is the distance over which a charged particle is able to accelerate in an electric field. Cavities within a dielectrically insulating material may function as reproduction centers for partial discharging, because they may allow the average free length to become great enough to move further free charge carriers to higher energy levels which again may cause further free charge carriers to move to higher energy levels. In this way, avalanche effects may occur.

As has been described before, the dielectric insulation layer <NUM> may comprise aluminum nitride (AlN), for example. The crystal structure of AlN is exemplarily illustrated in <FIG>. The aluminum Al<NUM>+ and nitride N<NUM>- atoms are evenly distributed within the crystal lattice. The ceramic crystals have a generally triangular or needle-shaped structure, as is indicated by the dotted lines in <FIG>. The crystals of other ceramic materials may have similar structures. Such crystal structures may facilitate the formation of cavities within the dielectric insulation layer <NUM> which may lead to the disadvantages outlined above.

As is schematically illustrated in <FIG>, the dielectric insulation layer <NUM>, according to one example, includes a first material <NUM> and a second material <NUM>. The first material <NUM> has a thermal conductivity of between <NUM> - <NUM> W/mK and an insulation strength of between <NUM> and <NUM> kV/mm. The first material <NUM>, e.g., may be a ceramic material, as has been described above. For example, the first material <NUM> may comprise one of Al<NUM>O<NUM>, AlN, and Si<NUM>N<NUM>. Any other suitable materials having a thermal conductivity of between <NUM> - <NUM> W/mK and an insulation strength of between <NUM> and <NUM> kV/mm, however, are also possible. The second material <NUM> may be added to the first material <NUM> and may be evenly distributed within the first material <NUM>. Now referring to <FIG>, the dielectric insulation layer <NUM> comprises a first length <NUM>, a first width w and a first height h. The first height h corresponds to a distance between the first metallization layer <NUM> and the second metallization layer <NUM> (metallization layers <NUM>, <NUM> not illustrated in <FIG>). The dielectric insulation layer <NUM>, therefore, forms a first volume V = l * w * h. The second material <NUM> may be evenly distributed within the entire volume V.

The second material <NUM> is an electrically conducting or semiconducting material. Generally speaking, the first material <NUM> has a first specific resistance and the second material <NUM> has a second specific resistance, wherein the second specific resistance is less than the first specific resistance. Adding a certain amount of the second material <NUM> to the first material <NUM>, therefore, reduces the electrical resistance of the dielectric insulation layer <NUM> to a certain degree and increases the electrical conductivity of the dielectric insulation layer <NUM> as compared to a dielectric insulation layer <NUM> which is formed only by the first material <NUM>. The amount of second material <NUM>, therefore, should be chosen such that an adequate insulation capacity of the dielectric insulation layer <NUM> is still maintained. Adding a small amount of second material <NUM> usually does not lead to a significant reduction of the insulating properties of the dielectric insulation layer <NUM>.

The amount of second material <NUM> that is added to the first material <NUM> may depend on the type of the first material <NUM>. For example, the amount of second material <NUM> that can be added to AlN may be significantly lower than the amount of second material <NUM> that can be added to Si<NUM>N<NUM>. The amount of first material <NUM> in any case may be greater than the amount of second material <NUM>. The ratio between the amount of first material <NUM> and the amount of second material <NUM> may be less than <NUM>:<NUM>, for example. A dielectric insulation layer <NUM> comprising more than <NUM>% of the second material <NUM> may not provide sufficient insulation strength. The amount of second material <NUM> may depend on the type of first material <NUM> that is used for the dielectric insulation layer <NUM>. For some types of first material <NUM>, the maximum amount of second material <NUM> may only be about <NUM>%. For most applications, the amount of second material <NUM> within the dielectric insulation layer <NUM> may be between <NUM>% and <NUM>%. The second material <NUM> may comprise particles that are evenly distributed within the crystal lattice of the first material <NUM>. The amount of second material <NUM> within the first material <NUM> may be sufficiently low such that no conductive paths are formed by a plurality of adjacent particles of the second material <NUM>.

In <FIG>, the particles of the first and second material <NUM>, <NUM> are schematically illustrated in round shapes for convenience only. <FIG> solely serves to illustrate in a very simple way the distribution of the second material <NUM> within the first material <NUM>. Some particles of the second material <NUM> may be arranged adjacent to one of the surfaces of the dielectric insulation layer <NUM>. Other particles may be surrounded by particles of the first material <NUM>. The second material <NUM> may comprise particles with a particle size of less than <NUM> or less than <NUM>, for example. The particle size may depend on the impact of the second material <NUM> on the mechanical properties of the dielectric insulation layer <NUM>. For example, the breaking strength of the dielectric insulation layer <NUM> could be reduced if the particle size of the second material <NUM> is too large. This, however, depends on the first material <NUM> that is used to form the dielectric insulation layer <NUM>.

The second material <NUM> may comprise at least one of ZrN, ZrO<NUM>, and graphite, for example. These materials, however, are only examples. Any other suitable electrically conducting or semiconducting materials may be used which are compatible to the first material <NUM>. Compatible in this context means that the particles of the second material <NUM> may be inserted in the crystal structure of the first material <NUM>. The structure of ZrN is exemplarily illustrated in <FIG>. As is indicated in dotted lines in <FIG>, the ZrN structure has the shape of an octahedron. By adding this material of different shape to the triangular shape of the ceramic material, the formation of cavities can be reduced. Further, if high field strengths occur in the vicinity of a particle of the second material <NUM>, this selective field strain may be spread by the particle over a greater area with a lower electrical resistance which may reduce the degradation of the ceramic material of the dielectric insulation layer <NUM> due to permanent selective electric field strain.

As can be seen from what has been described above, the second material <NUM> forms capturing centers within the first material <NUM> which reduce the average free length of path for free charge carriers within the dielectric insulation layer <NUM>. Thereby, avalanche effects can be reduced or even prevented. The electric field is more evenly distributed within the dielectric insulation layer <NUM>.

According to one example, the first material <NUM> is silicone nitride Si<NUM>N<NUM>, and the second material is zirconium nitride ZrN. Silicone nitride generally has a very high breaking strength. However, silicone nitride is usually not suitable for high voltage applications which require voltages of more than 3300V AC RMS, because it is vulnerable to partial discharging effects. At high field strengths, silicone nitride tends to completely lose its insulating properties. For example, a dielectric insulation layer <NUM> formed of silicone nitride, having a height h of <NUM> may lose its insulating properties at voltages of about <NUM> to 10kV AC RMS. Adding, e.g., zirconium nitride to the silicone nitride, increases the electrical stability of the dielectric insulation layer <NUM>. A dielectric insulation layer <NUM> comprising silicone nitride and a certain amount of zirconium nitride may be used for higher voltages as compared to a dielectric insulation layer <NUM> which solely comprises silicone nitride. For example, voltages of 3300V AC RMS or more are possible for a layer including silicone nitride and a certain amount of zirconium nitride. A pure silicone nitride substrate is usually used at voltages of 1700V AC RMS or less.

According to another example, the first material <NUM> is Al<NUM>O<NUM> and the second material <NUM> is ZrO<NUM>. According to an even further example, the first material <NUM> is AlN and the second material <NUM> is ZrN.

Claim 1:
A power semiconductor module arrangement comprising a semiconductor substrate (<NUM>), the semiconductor substrate (<NUM>) comprising:
a dielectric insulation layer (<NUM>); and
a first metallization layer (<NUM>) attached to the dielectric insulation layer (<NUM>);
wherein
the dielectric insulation layer (<NUM>) comprises particles of
a first material (<NUM>) having a thermal conductivity of between <NUM> and <NUM> W/mK, and an insulation strength of between <NUM> and <NUM> kV/mm, and particles of
a second electrically conducting or semiconducting material (<NUM>), wherein
the first material (<NUM>) comprises one of AlN, and Si<NUM>N<NUM>, and
the second material (<NUM>) comprises ZrN, and wherein the particles of the second material are evenly distributed among the particles of the first material.