Patent Description:
When an excessive voltage is applied to an internal circuit of a semiconductor chip due to noise such as static electricity or surge, dielectric breakdown of a gate oxide film and destruction or deterioration of PN junction are caused, so that permanent failure, change in circuit characteristics, or the like of the semiconductor chip occur. In order to prevent the destruction or deterioration of the internal circuit caused by such noise and to realize a semiconductor chip having higher reliability, a protective circuit needs to be provided between a pad and the internal circuit so that an excessive voltage is not applied to the internal circuit even when noise is applied. In the technique described in PTL <NUM>, a polysilicon resistor and a clamp transistor are provided between an input pad and an internal circuit. When an excessive voltage is applied to the pad, the clamp transistor breaks down or snaps back to a low resistance state, and thus, a current flows from the pad to the ground terminal through the polysilicon resistor and the clamp transistor. At this time, most of the energy of noise is absorbed by the polysilicon resistor, and the voltage applied to the internal circuit is clamped to a certain value or less, so that it is possible to prevent the above-mentioned element destruction and deterioration in characteristics.

PTL <NUM> describes a damping resistor that is connected to a protection circuit for protection of an internal circuit against an overvoltage. PTL <NUM> describes an input protective apparatus for a semiconductor device that comprises a MOS transistor having a thick gate insulating film formed therein. PTL <NUM> describes a semiconductor device that includes a first semiconductor chip, at least one second semiconductor chip, a first connector, and a second connector.

However, in the technology in the related art, a contact is needed in order to connect the pad and the polysilicon resistor, and there is a problem that the contact is easily broken by noise. In general, the contact is configured with a metal material such as tungsten, and one polysilicon resistor is configured with a semiconductor material, so parasitic resistance occurs at the junction between the contact and the polysilicon resistor. In addition, in recent years, due to miniaturization, the contact size may be reduced, and thus, the contact is relatively high in resistance. As a result, the energy of noise concentrates on the contact, and the contact may be burned out.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor chip having higher reliability by improving noise tolerance of an on-chip noise protective circuit.

According to the present invention for achieving the above object, there is provided a semiconductor chip in which a resistance value of a metal interconnection on a path leading from a pad to a protective element is higher than a resistance value of the protective element, as defined in claim <NUM>.

According to the present invention, no contact is required between a pad and a protective resistor, and thus, it is possible to provide a semiconductor chip having higher reliability.

A semiconductor chip according to a first embodiment of the present invention will be described with reference to <FIG>, <FIG>, and <FIG>. <FIG> illustrates a circuit configuration of the semiconductor chip according to the first embodiment. <FIG> is a diagram illustrating an example of characteristics of a protective element <NUM>. <FIG> is a cross-sectional diagram including a pad <NUM> of the semiconductor chip illustrated in <FIG>, a metal protective resistor <NUM>, and the protective element <NUM>.

The configuration of the semiconductor chip according to the embodiment will be described with reference to <FIG>. The semiconductor chip <NUM> according to the embodiment is configured to include a pad <NUM>, a metal protective resistor <NUM>, a protective element <NUM> (hereinafter, the metal protective resistor <NUM> and the protective element <NUM> are collectively referred to as a protective circuit <NUM>), a ground <NUM>, and an internal circuit <NUM> which includes an MOS transistor. The pad <NUM> is configured with a metal material such as aluminum. Like the pad <NUM>, the metal protective resistor <NUM> is configured with a metal material such as aluminum. The protective element <NUM> is a diode element of which an anode is connected to the ground <NUM> and of which a cathode is connected to interconnection <NUM> extending from the metal protective resistor <NUM> to the internal circuit <NUM>, and for example, the protective element is obtained by forming an N-type diffusion layer on a P-type substrate. A resistance value Rm of the metal protective resistor <NUM> is set to be higher than a resistance value Rd of the protective element <NUM>. In other words, the metal interconnection connecting the protective element <NUM> and the pad <NUM> has a high resistance portion having a resistance higher than that of the protective element <NUM> on an electrical path between the protective element <NUM> and the pad <NUM>.

Operations at the time of applying noise in the embodiment will be described with reference to <FIG> illustrates a current-voltage characteristic of the diode at the time of reverse biasing. During a normal operation of the semiconductor chip <NUM>, the diode is reverse-biased with a voltage near an operating voltage VCC of the internal circuit, and almost no current flows. On the other hand, when noise is applied to the pad <NUM> and a voltage across the diode becomes equal to or higher than a breakdown voltage VBD, a current Id flows through the diode due to a physical phenomenon called Zener breakdown or avalanche breakdown. At this time, if the energy consumed by the metal protective resistor <NUM> and the energy consumed by the diode are denoted by Em and Ed, respectively, the following relationship is satisfied. <MAT><MAT>.

Herein, the noise voltage applied to the pad <NUM> is denoted by VN. In addition, Rd is defined by dividing the voltage Vd across the diode by Id and is defined as including a resistance component of the diode itself and a resistance component of the contact to the diffusion layer. In addition, since the current consumption of the internal circuit <NUM> is very small in comparison with the current Id at the time of breakdown of the diode, the current consumption is neglected herein. As can be seen from Mathematical Formulas <NUM> and <NUM>, the ratio of the energy consumed by the protective resistor and the diode is equal to the ratio of the respective resistances. Since Rm is larger than Rd in the embodiment, a half or more of the energy of noise can be absorbed by the resistance, and thus, it is possible to prevent the diode element including the contact from being destructed.

In the semiconductor chip <NUM>, the pad <NUM> has a function of any one of a power supply terminal, a signal input terminal, a signal output terminal, and a signal input/output terminal. In the case where the pad <NUM> is a power supply terminal, it is preferable to set the resistance value Rm of the metal protective resistor <NUM> so as to satisfy the following mathematical formula.

Herein, VIN is a voltage supplied to the pad at the time of using the semiconductor chip, VCCMIN is a minimum operating voltage of the internal circuit <NUM>, and ICC is current consumption of the internal circuit <NUM>. By setting Rm to be within the range of the mathematical formula (Mathematical Formula <NUM>), it is possible to prevent the internal circuit <NUM> from malfunctioning due to the voltage drop caused by the protective resistor during a normal operation, and thus, it is possible to realize a semiconductor chip having higher reliability.

<FIG> is a diagram illustrating an example of a cross-sectional structure from the pad <NUM> to the protective circuit <NUM> in <FIG>. The metal protective resistor <NUM> is configured with the same metal interconnection layer as the pad <NUM>, and an input end <NUM> of the metal protective resistor <NUM> is directly connected to the pad <NUM>. On the other hand, an output end <NUM> of the metal protective resistor <NUM> is connected to a diffusion layer <NUM> of the protective element <NUM> through a via <NUM>, a lower metal interconnection layer <NUM>, and a contact <NUM> to the diffusion layer. According to such a configuration, a contact vulnerable to noise is not required between the pad <NUM> and the metal protective resistor <NUM>, so that the noise tolerance of the semiconductor chip <NUM> is improved. Another advantage of this configuration is an improvement in the withstand voltage of the protective resistor to the substrate. A reference of the withstand voltage of the oxide film is generally <NUM> MV/cm, in other words, <NUM> V per <NUM>. Namely, as the distance between the protective resistor and a substrate <NUM> increases, the breakdown voltage of the interlayer insulating film between the protective resistor and the substrate is improved. In this configuration, since the metal protective resistor <NUM> and the input terminal <NUM> of the metal protective resistor <NUM> to which a high voltage caused by noise is directly applied are located at positions separated from the substrate <NUM>, in comparison with the polysilicon protective resistor formed on a field oxide film described in PTL <NUM>, the withstand voltage of the input end <NUM> of the metal protective resistor <NUM> to the substrate is improved. In the electrostatic test, depending on the standard, a voltage of <NUM> to <NUM> V is instantaneously applied to the pad, so in order to prevent dielectric breakdown of the interlayer insulating film between the metal protective resistor <NUM> and the substrate <NUM>, the metal protective resistor <NUM> and the substrate <NUM> is separated by <NUM> or more. According to the claimed invention, the thickness of the stacked structure of the insulating film formed over the substrate <NUM> be <NUM> or more, and a metal interconnection film be formed on this stacked structure. In the example illustrated in <FIG>, the case where the number of the metal interconnection layers is two is illustrated, but the number of the metal interconnection layers is not limited to two. Even in the case of one layer or three or more layers, the same effect can be obtained by the same structure.

In addition, the type of the protective element <NUM> is not limited to a diode. For example, a gate-grounded NMOS (ggNMOS) <NUM> having a gate and a source connected to the ground as illustrated in <FIG> or a PMOS <NUM> having a gate and a source connected to a high potential side as illustrated in <FIG> may be used. In addition, as illustrated in <FIG>, a varistor element <NUM> may be used. In addition, as illustrated in <FIG>, in the case where a drain diffusion layer of the transistor <NUM> is connected to the metal protective resistor <NUM>, a parasitic diode <NUM> formed between the diffusion layer of the transistor <NUM> and the substrate or the well may be used as a protective element. The transistor <NUM> is not limited to an NMOS transistor illustrated in <FIG>, but the transistor may be a PMOS transistor or a bipolar transistor. In the case of a bipolar transistor, the parasitic diode is formed between any one of the collector, the base, and the emitter and the substrate or the well.

The effects of the semiconductor chip <NUM> according to the embodiment will be described. The first effect is that, since there is no contact vulnerable to noise between the pad <NUM> and the metal protective resistor <NUM> and the contact to the protective element <NUM> is protected by the metal protective resistor <NUM> of the anterior stage, the protective circuit <NUM> is hard to be destroyed with respect to noise. The second effect is that, since the input terminal of the protective resistor is separated from the substrate in comparison with the polysilicon protective resistor in the related art, the withstand voltage to the substrate is higher, and thus, it is possible to provide a protection function with respect to higher voltage noise.

A protective circuit of a semiconductor chip according to a second embodiment of the present invention will be described with reference to <FIG> is a top diagram of the protective circuit of the semiconductor chip according to the second embodiment. Description of the same configurations as in the first embodiment will be omitted. The protective circuit according to the second embodiment is characterized in that the metal protective resistor <NUM> in the semiconductor chip <NUM> according to the first embodiment is configured with a spiral metal interconnection resistor <NUM>. The metal interconnection resistor <NUM> is configured with the same interconnection layer as a pad <NUM> and is connected to a diffusion layer <NUM> of the protective element <NUM> through a via <NUM>, a lower interconnection layer <NUM>, and a contact <NUM>. According to such a configuration, in addition to the same effect as in the semiconductor chip <NUM> illustrated in the first embodiment, due to an inductance component of the spiral metal interconnection, higher impedance to noise having a high frequency component such as static electricity can be provided to the metal protective resistor <NUM>. Specifically, the impedance Zm of the metal protective resistor <NUM> is expressed by the following mathematical formula.

Herein, Rm is a resistance component of the metal interconnection resistor <NUM>, ω is an angular frequency of the noise, and Lm is inductance of the metal interconnection resistor <NUM>. Assuming that the noise voltage is VN and the ON resistance of the protective element is Rd, the voltage Vd applied to the internal circuit can be obtained by the following mathematical formula.

As can be seen from Mathematical Formula <NUM>, the voltage applied to the internal circuit at the time of applying the noise is lowered by the inductance of the metal interconnection resistor <NUM>. In other words, the protection performance of the metal protective resistor <NUM> improves.

More preferably, the spiral metal interconnection resistor <NUM> may be configured to have corner portions. More specifically, the bent angle of the interconnection is allowed to be smaller than <NUM> degrees. <FIG> illustrates an example in which corner portions <NUM> of the metal interconnection resistor <NUM> are configured by twice bending at <NUM> degrees. In addition, the extraction portion from the pad <NUM> may be formed to have a straight line section <NUM> to a certain extent. According to such a configuration, it is possible to suppress the damage of the interconnection due to the concentration of the current on the corner portions of the interconnection at the time of applying noise, and thus, it is possible to realize a semiconductor chip having higher reliability.

<FIG> illustrates a modified example of the protective circuit of the semiconductor chip according to the second embodiment. The protective circuit according to the embodiment is characterized in that the metal protective resistor <NUM> is configured with a spiral metal interconnection resistor <NUM> formed below the pad <NUM> and the metal protective resistor is arranged below the pad. According to such a configuration, in addition to the same effect as in the second embodiment, since the metal protective resistor <NUM> is formed between the pad <NUM> and the contact <NUM>, it is possible to further reduce the area of the protective circuit.

A protective circuit of a semiconductor chip according to a third embodiment of the present invention will be described with reference to <FIG> is a cross-sectional diagram of a protective circuit of the semiconductor chip according to the third embodiment. Description of the same configurations as in the first embodiment will be omitted. The protective circuit <NUM> according to the third embodiment is characterized in that the metal protective resistor <NUM> according to the first embodiment is configured with a metal interconnection <NUM> in the same layer as the pad <NUM>, a metal interconnection <NUM> below the pad <NUM>, and a via <NUM> connecting the metal interconnection <NUM> and the metal interconnection <NUM>. The terminal of the metal interconnection <NUM> closer to the internal circuit is connected to a diffusion layer <NUM> of the protective element <NUM> by the contact <NUM>. According to such a configuration, in addition to the same effect as in the first embodiment, it is possible to secure a larger interconnection length with the same resistance area as in the first embodiment. Namely, the high resistance of the protective resistor can be implemented. In other words, in comparison with the same resistance value, it is possible to reduce the area of the resistor. In <FIG>, the metal protective resistor <NUM> is configured by using two metal interconnection layers, but three or more metal interconnection layers may be used. In this case, it is possible to further reduce the area of the metal protective resistor <NUM>.

<FIG> illustrates a modified example of the protective circuit of the semiconductor chip according to the third embodiment. In the protective circuit according to the modified example, the metal protective resistor <NUM> is configured with a plurality of interconnection layers and vias. Namely, the protective circuit is characterized in that metal interconnection layers <NUM> and metal interconnection layers <NUM> below the metal interconnection layers are connected in series through vias <NUM>. According to such a configuration, in addition to the same effect as in the first embodiment, it is possible to secure a larger interconnection length with the same resistance area as in the first embodiment. Namely, the high resistance of the protective resistor can be implemented. In other words, in comparison with the same resistance value, it is possible to reduce the area of the resistor. In addition, if the material of the via <NUM> is a high resistance metal such as tungsten, it is possible to further reduce the area.

A protective circuit of a semiconductor chip according to a fourth embodiment of the present invention will be described with reference to <FIG>. The protective circuit according to the embodiment is characterized in that a polysilicon resistor <NUM> is further connected in series between the protective resistor <NUM> and the protective element <NUM> in the semiconductor chip <NUM> according to the first embodiment. <FIG> is a diagram illustrating an example of the cross-sectional structure from the pad to the protective circuit in <FIG>. The protective resistor <NUM> is configured in the same metal interconnection layer as the pad <NUM>, and the protective resistor <NUM> is connected to the polysilicon resistor <NUM> through a via <NUM> and a contact <NUM>. In general, the resistivity of the polysilicon resistor is higher than that of the metal interconnection resistor by one or more ordes of magnitude, and thus, if the same resistance value is used, the polysilicon resistor can be made smaller in area than the metal interconnection resistor. In the embodiment, the contact <NUM> to the polysilicon resistor <NUM> vulnerable to noise is protected by the metal interconnection resistor <NUM>. In addition, the metal interconnection resistor <NUM> also has an effect of lowering the voltage applied to the polysilicon resistor <NUM>. The noise voltage is lowered by using the metal interconnection resistor <NUM> having a high withstand voltage to the substrate, the polysilicon resistor having a relatively low withstand voltage to the substrate can also be used. On the other hand, a portion of the protective resistor is configured with a polysilicon resistor having high resistivity, so that it is possible to reduce the area when viewed as the whole protective resistor. According to such a configuration, in addition to the same effect as in the first embodiment, it is possible to reduce the area of the resistor in comparison with the first embodiment. As a modified example of the fourth embodiment, the metal protective resistor <NUM> may be configured in the spiral shape described in the second embodiment, in the multiple metal film layer structure described in the third embodiment, or in a combination of the spiral shape in the second embodiment and the multiple metal film layer structure in the third embodiment, and the same effect can be obtained.

A protective circuit of a semiconductor chip according to a fifth embodiment of the present invention will be described with reference to <FIG>. The protective circuit <NUM> according to the embodiment is characterized in that a protective capacitor <NUM> is added in parallel to the metal protective resistor <NUM> in the first embodiment. In <FIG>, for the convenience of description, the metal protective resistor <NUM> is virtually divided into three series resistors <NUM>, <NUM>, and <NUM>, and protective capacitors <NUM> and <NUM> are connected between the resistors. However, the number of division and the connection positions of the protective capacitors are not limited thereto. Since the metal protective resistor <NUM> and the protective capacitors <NUM> and <NUM> constitute an RC low-pass filter, the peak voltage in the protective circuit according to the embodiment can be lower with respect to high-frequency noise than the protective circuit according to the first embodiment. Therefore, when noise is applied, the voltage applied to the internal circuit is reduced, and thus, it is possible to realize a semiconductor chip having higher reliability.

<FIG> is a top diagram illustrating an example of a structure from the pad to the protective circuit in <FIG>. The protective circuit is characterized in that electrodes <NUM> and <NUM> are arranged on both sides of the metal interconnection resistor <NUM> by using the same metal interconnection layer. By fixing the electrodes <NUM> and <NUM> to the ground potential, parasitic capacitance formed between the metal interconnection resistor <NUM> and the electrode <NUM> and parasitic capacitance formed between the metal interconnection resistor <NUM> and the electrode <NUM> are used as protective capacitors <NUM> and <NUM>, respectively. According to such a configuration, an RC low-pass filter can be configured without preparing a special capacitor element, and thus, it is possible to further reduce the area of the protective circuit. The method of realizing the protective capacitors <NUM> and <NUM> is not limited to the structure of <FIG>. For example, <FIG> illustrates another method of realizing the protective capacitor, and by arranging interconnections <NUM>, <NUM>, and <NUM> and vias <NUM> and <NUM> connecting the interconnections so as to stereoscopically surround the upper, lower, left and right sides of the metal interconnection resistor <NUM>, capacitors may be configured between the metal interconnection resistor <NUM> and the interconnection.

A sensor device <NUM> including a semiconductor chip <NUM> according to a sixth embodiment of the present invention will be described with reference to <FIG>. The sensor device <NUM> according to the embodiment is configured to include a sensor element <NUM>, a semiconductor chip <NUM>, a power supply terminal <NUM>, an output terminal <NUM>, and a ground terminal <NUM>. The sensor element <NUM> is an element of which electric characteristic changes according to physical quantities. In <FIG>, the sensor element <NUM> is illustrated as a discrete component, but the sensor element may be formed in the semiconductor chip <NUM>. The semiconductor chip <NUM> is configured to include a power supply pad <NUM>, an output pad <NUM>, a ground pad <NUM>, a metal protective resistor <NUM>, a metal protective resistor <NUM>, a protective element <NUM>, a protective element <NUM>, and an internal circuit <NUM>. The semiconductor chip <NUM> controls the sensor element <NUM>, processes the output signal of the sensor element <NUM>, and outputs the output signal to the output pad <NUM>. The metal protective resistor <NUM> and the metal protective resistor <NUM>, the protective element <NUM> and the protective element <NUM> are those illustrated in the above embodiments. From noise such as static electricity or surge applied from the outside of the sensor device <NUM> to the terminals <NUM>, <NUM>, and <NUM>, the power supply terminal <NUM> is protected by the protective resistor <NUM> and the protective element <NUM>, and the output terminal <NUM> is protected by the protective resistor <NUM> and the protective element <NUM>. According to such a configuration, by providing the semiconductor chip <NUM> with tolerance to noise, it is possible to reduce external protective elements of the semiconductor chip <NUM>, to reduce discrete components included in the sensor device <NUM>, and to enhance reliability of the sensor device <NUM>.

A protective circuit of a semiconductor chip according to a seventh embodiment of the present invention will be described with reference to <FIG> is a diagram illustrating an example of a cross-sectional structure of a protective circuit of the semiconductor chip according the seventh embodiment. The protective circuit <NUM> according to the embodiment is characterized in that a thin film <NUM> having a thermal resistance lower than that of an interlayer insulating film <NUM> is arranged between the metal protective resistor <NUM> and the substrate <NUM> in the semiconductor chip <NUM> according to the first embodiment. According to such a configuration, the heat generated by the protective resistor <NUM> at the time of applying the noise is more easily released to the substrate, and thus, it is possible to enhance the tolerance of the metal protective resistor <NUM> to the noise energy. As a result, it is possible to realize a more reliable semiconductor chip. For example, the interlayer insulating film <NUM> is SiO2 (example of thermal resistance value: <NUM>·m/W), and as a material having a thermal resistance lower than that of SiO2, a silicon nitride film Si3N4 (example of thermal resistance value: <NUM>·m/W) or a mixture SiON thereof, aluminum oxide Al2O<NUM>, aluminum nitride AlN, and the like are suitable. In addition, the thin film <NUM> having a thermal resistance lower than that of the interlayer insulating film <NUM> is not limited to an insulating film such as a silicon nitride film. As illustrated in <FIG>, a structure <NUM> where a metal interconnection layer below the metal protective resistor <NUM> or a plurality of metal interconnection layers are connected through vias may be used. In general, the thermal resistance of the metal material is lower by about one order of magnitude than that of the silicon nitride film, and thus, it is possible to further improve the heat releasing property. As a result, it is possible to increase the tolerance of the protective resistor to the noise energy and to realize a semiconductor chip having higher reliability. The embodiment can be applied not only to the first embodiment but also to the other embodiments described above.

A protective circuit of a semiconductor chip according to an eighth embodiment of the present invention will be described with reference to <FIG> is a layout diagram of a plurality of pads <NUM> and <NUM>, metal interconnection resistors <NUM> and <NUM>, and protective elements <NUM> and <NUM> on the semiconductor chip <NUM> according to the eighth embodiment. The protective circuit <NUM> according to the embodiment is characterized in that the pads <NUM> and <NUM> and the protective elements <NUM> and <NUM> corresponding to the pads <NUM> and <NUM> are arranged on the semiconductor chip <NUM> in a cross-cuppled manner and are connected to each other by the metal interconnection resistors <NUM> and <NUM>. According to such a configuration, the metal interconnection resistor can be arranged without expanding the distance between the pads <NUM> and <NUM> and the protective elements <NUM> and, <NUM>. In <FIG>, since the distance between the pads <NUM> and <NUM> and the protective element protective elements <NUM> and <NUM> can be taken without expanding the distance in the vertical direction, it is possible to secure the resistance value of the metal interconnection resistors <NUM> and <NUM> by suppressing an increase in chip area.

Claim 1:
A semiconductor chip comprising:
a pad (<NUM>);
a protective element (<NUM>) protecting an internal circuit (<NUM>);
a metal interconnection (<NUM>) for electrically connecting the pad and the protective element,
wherein the metal interconnection has a high resistance portion of which resistance value is higher than a resistance value of the protective element (<NUM>), when noise is applied to the pad and a voltage across the protecting element becomes equal to or higher than a breakdown voltage of said protective element,
wherein the high resistance portion is a metal protection resistor (<NUM>),
characterized in that
the high resistance portion includes a metal thin film layer formed in the same layer as the pad;
wherein an input end (<NUM>) of the metal protective resistor (<NUM>) is directly connected to the pad (<NUM>), and an output end (<NUM>) of the metal protective resistor (<NUM>) is connected to a diffusion layer (<NUM>) of the protective element (<NUM>) through a via (<NUM>), a lower metal interconnection layer (<NUM>), and a contact (<NUM>) to the diffusion layer (<NUM>),
wherein the semiconductor chip comprises a substrate (<NUM>) in which surface the diffusion layer (<NUM>) of the protective element (<NUM>) is formed, and wherein the substrate (<NUM>) and the metal protective resistor (<NUM>) are separated by an interlayer insulation film of <NUM> or more.