Patent Description:
Matrix operations, such as matrix multiplication and convolutions, can be highly processor-intensive and memory-intensive operations, as they often involve complex operations on large, multi-dimensional matrix operands. Accordingly, the performance of complex matrix operations can be limited by the processing and/or memory latency. As matrix operations are increasingly utilized in a variety of applications and with ever-growing data sets (from graphics and image processing to machine learning and artificial intelligence), the demand for high-performance and flexible processing of matrix operations is increasing.

<CIT> discloses a multiprocessor with matrix processors each performing matrix operations.

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not necessarily drawn to scale, and are used for illustration purposes only. Where a scale is shown, explicitly or implicitly, it provides only one illustrative example. In other embodiments, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

The following disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. Different embodiments may have different advantages, and no particular advantage is necessarily required of any embodiment.

Matrix processing operations (e.g., linear algebra operations that involve matrix and/or vector operands) have a wide range of applications in computing systems, from graphics processing to machine learning and artificial intelligence, among other examples. For example, complex matrix operations may be used to implement artificial neural networks that provide artificial intelligence and machine learning capabilities, including computer vision, autonomous navigation, speech and audio recognition, and natural language processing, among other examples. These complex matrix operations (e.g., matrix multiplication and convolutions) may be used to implement the fundamental operations of neural networks, such as forward propagation, backward propagation, and weight updates. These matrix operations, however, can be highly processor and memory intensive, as they often involve complex operations on large, multi-dimensional matrix operands. Accordingly, the performance of these matrix operations can be limited by processing and/or memory latency. Moreover, these rigid matrix operations are often implemented without any flexibility to implement new types or variations of matrix operations and/or modify the behavior of existing operations. As matrix operations are increasingly utilized in a variety of applications with ever-growing data sets, such as artificial intelligence and machine learning, the demand for both high-performance processing and flexible implementations of matrix operations is increasing.

Existing matrix processing approaches suffer from various inefficiencies, particularly when used to implement artificial intelligence and machine learning in artificial neural networks. For example, while central processing units (CPUs) could be used to perform matrix operations, many CPU architectures are designed for low arithmetic intensity operations (i.e., a low ratio of arithmetic operations relative to memory operations), and thus are not designed for efficient execution of matrix operations. Moreover, many CPU architectures utilize complex local or cache memory management routines, which may increase processing overhead and execution complexity for operations involving large matrix operands. Graphics processing units (GPUs) could also be used to perform matrix operations. GPUs, however, are often designed for high precision computations and may provide a level of precision that is unnecessary for certain matrix operations, thus reducing the volume of matrix operations that can be performed. Accordingly, existing matrix processing approaches are inefficient for certain matrix operations, such as matrix multiplication or convolution operations involving large matrix operands and/or matrix operands with certain dimensions, among other examples. Moreover, existing approaches cannot be efficiently scaled to perform these matrix operations across additional processing resources in parallel. Thus, existing approaches do not achieve <NUM>% processing efficiency when scaling and/or distributing these matrix operations. Moreover, existing approaches are often rigid and inflexible with limited or no ability to define new matrix operations, modify existing matrix operations, and so forth.

The matrix processing functionality described throughout this disclosure provides a flexible or "programmable" approach for defining or implementing particular matrix operations. For example, certain embodiments may include a matrix processor that can execute programmable matrix routines. A matrix routine, for example, may be a programmable routine that is designed to perform a particular matrix operation when executed by a matrix processor. For example, a matrix routine may include a series of instructions and/or commands, supported by a particular matrix processor, and designed to perform a desired matrix operation when executed by the matrix processor. In some embodiments, for example, a matrix processor may be designed to support a set of instructions and/or commands for performing various fundamental operations. In this manner, matrix routines for more complex matrix operations can be programmed using the fundamental instructions and/or commands supported by the matrix processor. In some embodiments, these matrix routines can be stored on a matrix routine memory associated with a matrix processor. Then, when a particular matrix operation needs to be performed, the matrix processor can retrieve the corresponding matrix routine from the matrix routine memory, and then execute the instructions and/or commands of the routine to perform the desired matrix operation.

The programmable matrix processing functionality described throughout this disclosure provides numerous technical advantages, including alleviating the inefficiencies of existing approaches, and enabling flexible matrix operations to be efficiently defined and implemented using programmable matrix routines. These programmable matrix routines enable wide varieties of matrix processing functionality to be implemented on matrix processors programmatically rather than via inefficient, time-consuming, and costly hardware-based implementations.

Example embodiments that may be used to implement the matrix processing functionality of this disclosure will now be described with more particular reference to the attached FIGURES.

<FIG> illustrates a schematic diagram for an example computing system <NUM> according to certain embodiments.

In some embodiments, the matrix processing functionality described throughout this disclosure may be implemented in system <NUM>. Matrix processing functionality may be used in system <NUM> for a wide range of applications and/or use cases involving matrix operations, from graphics processing to machine learning and artificial intelligence, among other examples. For example, in some embodiments, matrix processing functionality may be used to implement artificial intelligence and machine learning in artificial neural networks. Moreover, matrix processing functionality may be implemented by any component of system <NUM>. For example, in the illustrated embodiment, system <NUM> includes edge devices <NUM>, cloud services <NUM>, matrix processing nodes <NUM>, and network <NUM>. Matrix processing nodes <NUM> may include any component or device with matrix processing functionality, including any component of system <NUM>. For example, matrix processing nodes <NUM> may include cloud services <NUM> and/or servers implemented with matrix processing functionality (e.g., application servers in a datacenter), edge devices <NUM> implemented with matrix processing functionality (e.g., end-user devices <NUM>, Internet-of-Things devices <NUM>, gateways <NUM>), and so forth. These various components of system <NUM> are discussed further below.

Edge devices <NUM> may include any equipment and/or devices deployed or connected near the "edge" of a communication system <NUM>. Edge devices <NUM> may communicate with each other and/or with other remote networks and services (e.g., cloud services <NUM>) through one or more networks and/or communication protocols, such as network <NUM>. In some embodiments, certain edge devices <NUM> may include the matrix processing functionality described throughout this disclosure, and thus may be used as matrix processing nodes <NUM>. In the illustrated embodiment, edge devices <NUM> include end-user devices <NUM> (e.g., desktops, laptops, mobile devices), Internet-of-Things (loT) devices <NUM>, and gateways and/or routers <NUM>, among other examples.

End-user devices <NUM> may include any device that enables or facilitates user interaction with computing system <NUM>, including, for example, desktop computers, laptops, tablets, mobile phones and other mobile devices, and wearable devices (e.g., smart watches, smart glasses, headsets), among other examples.

loT devices <NUM> may include any device capable of communicating and/or participating in an Internet-of-Things (IoT) system or network. IoT systems may refer to new or improved ad-hoc systems and networks composed of multiple different devices (e.g., loT devices <NUM>) interoperating and synergizing for a particular application or use case. Such ad-hoc systems are emerging as more and more products and equipment evolve to become "smart," meaning they are controlled or monitored by computer processors and are capable of communicating with other devices. For example, an loT device <NUM> may include a computer processor and/or communication interface to allow interoperation with other components of system <NUM>, such as with cloud services <NUM> and/or other edge devices <NUM>. loT devices <NUM> may be "greenfield" devices that are developed with loT capabilities from the ground-up, or "brownfield" devices that are created by integrating IoT capabilities into existing legacy devices that were initially developed without loT capabilities. For example, in some cases, loT devices <NUM> may be built from sensors and communication modules integrated in or attached to "things," such as equipment, toys, tools, vehicles, living things (e.g., plants, animals, humans), and so forth. Alternatively, or additionally, certain loT devices <NUM> may rely on intermediary components, such as edge gateways or routers <NUM>, to communicate with the various components of system <NUM>.

loT devices <NUM> may include various types of sensors for monitoring, detecting, measuring, and generating sensor data and signals associated with characteristics of their environment. For instance, a given sensor may be configured to detect one or more respective characteristics, such as movement, weight, physical contact, temperature, wind, noise, light, position, humidity, radiation, liquid, specific chemical compounds, battery life, wireless signals, computer communications, and bandwidth, among other examples. Sensors can include physical sensors (e.g., physical monitoring components) and virtual sensors (e.g., software-based monitoring components). IoT devices <NUM> may also include actuators to perform various actions in their respective environments. For example, an actuator may be used to selectively activate certain functionality, such as toggling the power or operation of a security system (e.g., alarm, camera, locks) or household appliance (e.g., audio system, lighting, HVAC appliances, garage doors), among other exam ples.

Indeed, this disclosure contemplates use of a potentially limitless universe of IoT devices <NUM> and associated sensors/actuators. IoT devices <NUM> may include, for example, any type of equipment and/or devices associated with any type of system <NUM> and/or industry, including transportation (e.g., automobile, airlines), industrial manufacturing, energy (e.g., power plants), telecommunications (e.g., Internet, cellular, and television service providers), medical (e.g., healthcare, pharmaceutical), food processing, and/or retail industries, among others. In the transportation industry, for example, loT devices <NUM> may include equipment and devices associated with aircrafts, automobiles, or vessels, such as navigation systems, autonomous flight or driving systems, traffic sensors and controllers, and/or any internal mechanical or electrical components that are monitored by sensors (e.g., engines). IoT devices <NUM> may also include equipment, devices, and/or infrastructure associated with industrial manufacturing and production, shipping (e.g., cargo tracking), communications networks (e.g., gateways, routers, servers, cellular towers), server farms, electrical power plants, wind farms, oil and gas pipelines, water treatment and distribution, wastewater collection and treatment, and weather monitoring (e.g., temperature, wind, and humidity sensors), among other examples. IoT devices <NUM> may also include, for example, any type of "smart" device or system, such as smart entertainment systems (e.g., televisions, audio systems, videogame systems), smart household or office appliances (e.g., heat-ventilation-air-conditioning (HVAC) appliances, refrigerators, washers and dryers, coffee brewers), power control systems (e.g., automatic electricity, light, and HVAC controls), security systems (e.g., alarms, locks, cameras, motion detectors, fingerprint scanners, facial recognition systems), and other home automation systems, among other examples. IoT devices <NUM> can be statically located, such as mounted on a building, wall, floor, ground, lamppost, sign, water tower, or any other fixed or static structure. IoT devices <NUM> can also be mobile, such as devices in vehicles or aircrafts, drones, packages (e.g., for tracking cargo), mobile devices, and wearable devices, among other examples. Moreover, an IoT device <NUM> can also be any type of edge device <NUM>, including end-user devices <NUM> and edge gateways and routers <NUM>.

Edge gateways and/or routers <NUM> may be used to facilitate communication to and from edge devices <NUM>. For example, gateways <NUM> may provide communication capabilities to existing legacy devices that were initially developed without any such capabilities (e.g., "brownfield" loT devices). Gateways <NUM> can also be utilized to extend the geographical reach of edge devices <NUM> with short-range, proprietary, or otherwise limited communication capabilities, such as loT devices <NUM> with Bluetooth or ZigBee communication capabilities. For example, gateways <NUM> can serve as intermediaries between loT devices <NUM> and remote networks or services, by providing a front-haul to the loT devices <NUM> using their native communication capabilities (e.g., Bluetooth, ZigBee), and providing a back-haul to other networks <NUM> and/or cloud services <NUM> using another wired or wireless communication medium (e.g., Ethernet, Wi-Fi, cellular). In some embodiments, a gateway <NUM> may be implemented by a dedicated gateway device, or by a general purpose device, such as another loT device <NUM>, end-user device <NUM>, or other type of edge device <NUM>.

In some instances, gateways <NUM> may also implement certain network management and/or application functionality (e.g., loT management and/or loT application functionality for IoT devices <NUM>), either separately or in conjunction with other components, such as cloud services <NUM> and/or other edge devices <NUM>. For example, in some embodiments, configuration parameters and/or application logic may be pushed or pulled to or from a gateway device <NUM>, allowing IoT devices <NUM> (or other edge devices <NUM>) within range or proximity of the gateway <NUM> to be configured for a particular loT application or use case.

Cloud services <NUM> may include services that are hosted remotely over a network <NUM>, or in the "cloud. " In some embodiments, for example, cloud services <NUM> may be remotely hosted on servers in datacenter (e.g., application servers or database servers). Cloud services <NUM> may include any services that can be utilized by or for edge devices <NUM>, including but not limited to, data storage, computational services (e.g., data analytics, searching, diagnostics and fault management), security services (e.g., surveillance, alarms, user authentication), mapping and navigation, geolocation services, network or infrastructure management, loT application and management services, payment processing, audio and video streaming, messaging, social networking, news, and weather, among other examples. In some embodiments, certain cloud services <NUM> may include the matrix processing functionality described throughout this disclosure, and thus may be used as matrix processing nodes <NUM>.

In general, edge devices <NUM> (and in particular loT devices <NUM>) may generate an extremely large volume and variety of data. IoT edge devices <NUM> typically offload this data to the cloud for processing and/or storage (e.g., by cloud services <NUM>). Cloud services <NUM>, however, may not necessarily be suited to handle the rapidly growing volume, variety, and velocity of data generated by loT devices <NUM> and other edge devices <NUM>. For example, cloud-based processing may not be ideal in certain circumstances, such as processing time-sensitive or highly confidential data, or when faced with network bandwidth constraints, among other examples. In some embodiments, cloud services <NUM> may leverage "edge" based processing using edge devices <NUM> to improve the performance of cloud services. Edge processing is an approach that involves processing certain data at the network edge (e.g., using edge devices <NUM>), near where the data is generated, rather than simply funneling large volumes of data to the cloud for processing and storage. Certain data may still be sent to the cloud, as appropriate, such as for deeper analysis and/or long-term storage. Edge processing may be used to complement the shortcomings of cloud-based processing (e.g., when cloud-based processing is inefficient, ineffective, and/or unsecure), and thus improve the handling of the growing volume, variety, and velocity of data generated by loT devices <NUM> and/or other edge devices <NUM>. For example, in some cases, processing data near its source (e.g., in the network edge) rather than in the cloud may improve performance and/or avoid system failures or disasters. Edge processing may also conserve network bandwidth, which may be particularly beneficial when facing bandwidth constraints and/or limited network connectivity.

In some embodiments, edge devices <NUM> that provide edge-based processing for cloud services <NUM> may be collectively referred to as the "fog," as they serve to extend the "cloud" to the edge of the network, thus creating a "fog" over the network edge. In some embodiments, devices <NUM> in the "fog" may connect and/or communicate with each other, for example, using an interconnection standard or protocol. For example, in some embodiments, device interconnection may be implemented using the open interconnect consortium (OIC) standard specification <NUM>, released by the Open Connectivity Foundation™ (OCF) on December <NUM>, <NUM>, which enables devices to discover and connect with each other. Another interconnection protocol that may be used is Thread, a networking protocol for Internet-of-Things (IoT) devices used in "smart" home automation and similar deployments, which has been developed by an alliance of organizations named the "Thread Group. " Other interconnection protocols may also be used, including, for example, the optimized link state routing (OLSR) protocol, or the better approach to mobile ad-hoc networking (B. ), among others.

Network <NUM> may be used to facilitate communication between the components of computing system <NUM>. For example, edge devices <NUM>, such as end-user devices <NUM> and loT devices <NUM>, may use network <NUM> to communicate with each other and/or access one or more remote cloud services <NUM>. Network <NUM> may include any number or type of communication networks, including, for example, local area networks, wide area networks, public networks, the Internet, cellular networks, Wi-Fi networks, short-range networks (e.g., Bluetooth or ZigBee), and/or any other wired or wireless networks or communication mediums.

Any, all, or some of the computing devices of system <NUM> may be adapted to execute any operating system, including Linux or other UNIX-based operating systems, Microsoft Windows, Windows Server, MacOS, Apple iOS, Google Android, or any customized and/or proprietary operating system, along with virtual machines adapted to virtualize execution of a particular operating system.

While <FIG> is described as containing or being associated with a plurality of elements, not all elements illustrated within system <NUM> of <FIG> may be utilized in each alternative implementation of the present disclosure. Additionally, one or more of the elements described in connection with the examples of <FIG> may be located external to system <NUM>, while in other instances, certain elements may be included within or as a portion of one or more of the other described elements, as well as other elements not described in the illustrated implementation. Further, certain elements illustrated in <FIG> may be combined with other components, as well as used for alternative or additional purposes in addition to those purposes described herein.

<FIG> illustrate block diagrams for an example embodiment of a matrix processing architecture.

In some embodiments, the matrix processing functionality described throughout this disclosure may be implemented using a matrix processing architecture, such as the matrix processing architecture of <FIG>. Matrix processing architectures, such as the matrix processing architecture of <FIG>, may be implemented or used in a variety of systems, devices, and/or components, such as those described throughout this disclosure, including system <NUM> of <FIG> and/or any of its associated components (e.g., cloud services <NUM> / datacenter servers, edge devices <NUM>, matrix processing nodes <NUM>). In some embodiments, the matrix processing architecture of <FIG> may be used to implement artificial intelligence and machine learning in neural networks. The matrix processing architecture illustrated in <FIG> is merely one example embodiment for performing the matrix processing functionality described throughout this disclosure. Other embodiments may use different types, arrangements, and/or numbers of components. For example, other embodiments may include any number of matrix processing chips <NUM>, matrix processing clusters <NUM>, matrix processing units (MPUs) <NUM>, high bandwidth memory (HBM) modules <NUM>, and/or memory resource blocks (MRBs) <NUM>. Moreover, all or part of any component of the matrix processing architecture of <FIG> (e.g., any component of matrix processing system <NUM>, matrix processing chips <NUM>, and/or matrix processing clusters <NUM>) may be implemented as a separate or stand-alone component or chip, or may be integrated with other components or chips, such as a system-on-a-chip (SoC) that integrates various computer components into a single chip.

<FIG> illustrates a block diagram for an example embodiment of a matrix processing system <NUM>. In the illustrated embodiment, matrix processing system <NUM> includes host processor <NUM>, host memory <NUM>, matrix processing resources <NUM>, and interconnect bus <NUM>.

Host processor <NUM> may be configured to control and/or manage matrix processing system <NUM>. For example, in some embodiments, host processor <NUM> may use matrix processing resources <NUM> to perform complex matrix operations. Host processor <NUM> may be any processing resource capable of controlling and/or managing matrix processing functionality of matrix processing system <NUM>. For example, in some embodiments, host processor <NUM> may be implemented using computer processors <NUM> or <NUM> of <FIG> and <FIG>, respectively. In some embodiments, host processor <NUM> may be a separate or stand-alone component that is communicatively coupled to matrix processing resources <NUM>. Alternatively, in other embodiments, host processor <NUM> and matrix processing resources <NUM> may be integrated into the same component or chip. For example, in some embodiments, the components of matrix processing system <NUM>, including host processor <NUM> and matrix processing resources <NUM>, may be implemented as a system-on-a-chip (SoC).

Host memory <NUM> may include any type or combination of volatile and/or non-volatile memory. Examples of volatile memory include various types of random access memory (RAM), such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and static random access memory (SRAM), among other examples. Examples of non-volatile memory include disk-based storage mediums (e.g., magnetic and/or optical storage mediums), solid-state storage (e.g., any form of persistent flash memory, including planar or three dimensional (3D) NAND flash memory or NOR flash memory), 3D crosspoint memory, electrically erasable programmable read-only memory (EEPROM), and/or other types of non-volatile random access memories (RAM), among other examples. Host memory <NUM> may be used, for example, to store information for host processor <NUM> during execution, such as code and/or data.

Interconnect bus <NUM> may be used, in some embodiments, to communicatively couple host processor <NUM> and host memory <NUM> to matrix processing resources <NUM>. Interconnect bus <NUM> may use any interconnection protocol, such as Peripheral Component Interconnect express (PCIe), Universal Serial Bus (USB), or Small Computer Systems Interface (SCSI), among other examples.

Matrix processing resources <NUM> may include any processing resources configured to perform matrix operations. For example, matrix processing resources <NUM> may be configured to perform matrix multiplication operations, convolution operations, element-wise matrix operations (e.g., +, *, / <, >, __), dimension shuffle operations, and/or any combination thereof. In some embodiments, matrix processing resources <NUM> may include processing resources that are designed and optimized for performing matrix operations. In some embodiments, matrix processing resources <NUM> may also be arranged hierarchically with multiple levels of processing resources. For example, in the illustrated embodiment, matrix processing resources <NUM> include a plurality of matrix processing chips <NUM>, and may also include any processing resources within each matrix processing chip <NUM>. For example, as discussed below in connection with <FIG>, each matrix processing chip <NUM> may include a plurality of high bandwidth memory (HBM) modules <NUM> and a plurality of matrix processing clusters <NUM>, and each matrix processing cluster <NUM> may include multiple matrix processing units <NUM>. Thus, in some embodiments, matrix processing resources <NUM> may include multiple matrix processing chips <NUM>, multiple high bandwidth memory (HBM) modules <NUM> and multiple matrix processing clusters <NUM> on each matrix processing chip <NUM>, and/or multiple matrix processing units <NUM> on each matrix processing cluster <NUM>.

Matrix processing chips <NUM> may be, for example, any chips or other components configured to perform matrix operations. For example, in some embodiments, a matrix processing chip <NUM> may be a peripheral card or chip connected to host processor <NUM> using any type of interconnect interface, such as a PCIe interface. In some embodiments, a matrix processing chip <NUM> may be implemented using an integrated circuit, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and/or any other type of circuitry. In the illustrated embodiment, matrix processing chips <NUM> are configured in a cyclical arrangement, with communication channels <NUM> between neighboring matrix processing chips <NUM>. In some embodiments, communication channels <NUM> may provide one-way communication between neighboring matrix processing chips <NUM>. In other embodiments, however, communication channels <NUM> may provide bi-directional communication between neighboring matrix processing chips <NUM>. A cyclical arrangement with one-way communication between neighboring processing resources may be referred to as a "single-cyclical" configuration, while a cyclical arrangement with bi-directional communication between neighboring processing resources may be referred to as a "dual-cyclical" configuration.

Moreover, although not illustrated, in some embodiments matrix processing system <NUM> may include a communication interface to communicate over a communication network. For example, in some embodiments, matrix processing system <NUM> may communicate over a network with one or more remote matrix processing chips to perform distributed matrix operations.

<FIG> illustrates a block diagram for an example embodiment of a matrix processing chip <NUM>. In the illustrated embodiment, matrix processing chip <NUM> includes controller <NUM>, host interface <NUM>, inter-chip links <NUM>, high bandwidth memory (HBM) modules <NUM>, and matrix processing clusters <NUM>.

Controller <NUM> may be configured to control and/or manage matrix operations performed by matrix processing chip <NUM>. In some embodiments, controller <NUM> may control and/or manage matrix operations in conjunction with host processor <NUM> of <FIG> and/or master control CPUs (MCCs) <NUM> of matrix processing clusters <NUM> of <FIG>. For example, in some embodiments, host processor <NUM>, controller <NUM>, and/or master control CPUs (MCCs) <NUM> may be configured to receive a matrix operation or command, and distribute the matrix operation and matrix operands across matrix processing clusters <NUM> and high bandwidth memory (HBM) modules <NUM>. In some embodiments, controller <NUM> may be a microprocessor, an integrated circuit, and/or any other type of circuitry and/or processing logic.

Host interface <NUM> may be a communication interface that enables a matrix processing chip <NUM> to communicate with host processor <NUM> of <FIG>. In some embodiments, for example, controller <NUM> may use host interface <NUM> to communicate with host processor <NUM> of <FIG>. Host interface <NUM> may use any type of interconnect protocol or interface, including Peripheral Component Interconnect express (PCIe), Universal Serial Bus (USB), or Small Computer Systems Interface (SCSI), among other examples.

Inter-chip links (ICLs) <NUM> may enable a matrix processing chip <NUM> to communicate with other matrix processing chips. For example, inter-chip links <NUM> may be used to implement the communication channels <NUM> between matrix processing chips <NUM> in <FIG>. An inter-chip link <NUM> may be, for example, any communication interface that enables a matrix processing chip <NUM> to communicate with another matrix processing chip. In some embodiments, a matrix processing chip <NUM> may include multiple inter-chip links <NUM> (e.g., twelve inter-chip links). In some embodiments, an inter-chip link <NUM> may be implemented using one or more serializer / de-serializer (SerDes) interfaces. A SerDes interface may be a communication interface that converts data from serial to parallel, and vice-versa. For example, the transmitter of a SerDes interface may include a serial-to-parallel converter, and the receiver of a SerDes interface may include a parallel-to-serial converter. In some embodiments, a matrix processing chip <NUM> may use multiple SerDes interfaces for each connection to another matrix processing chip (e.g., four SerDes interfaces between each pair of connected matrix processing chips).

High bandwidth memory (HBM) modules <NUM> may be memory components associated with matrix processing chip <NUM> that are used to store matrix operands and other matrix data. In some embodiments, high bandwidth memory (HBM) modules <NUM> may be designed to efficiently store and retrieve matrix data. In some embodiments, high bandwidth memory (HBM) modules <NUM> may be multi-dimensional memory components configured to store and retrieve data in multiple dimensions. For example, in some embodiments, high bandwidth memory (HBM) modules <NUM> may be memory components configured to store and retrieve data in two dimensions, such as rows and columns. Other embodiments, however, may use memory components configured to store and retrieve data using any other number of dimensions (e.g., one dimension, three dimensions, four dimensions, and so forth). In the illustrated embodiment, matrix processing chip <NUM> includes four high bandwidth memory (HBM) modules 240a-d. In some embodiments, high bandwidth memory (HBM) modules <NUM> may be shared by the matrix processing clusters <NUM> of a matrix processing chip <NUM>.

Matrix processing clusters <NUM> may include processing resources configured to perform matrix operations, such as matrix multiplication, convolutions, and/or dimension shuffling, among other examples. In some embodiments, matrix processing clusters <NUM> may be collectively used to execute a particular matrix operation by performing matrix processing in parallel. In the illustrated embodiment, matrix processing chip <NUM> includes twelve matrix processing clusters 230a-I. Moreover, in the illustrated embodiment, matrix processing clusters <NUM> are configured or arranged using a two-dimensional mesh interconnection topology. The interconnection topology of matrix processing clusters <NUM> may facilitate cyclical communication among the matrix processing clusters <NUM>. Moreover, other embodiments may include any number and/or arrangement of matrix processing clusters <NUM>.

<FIG> illustrates a block diagram for an example embodiment of a matrix processing cluster <NUM>. In the illustrated embodiment, matrix processing cluster <NUM> includes master control CPU (MCC) <NUM>, matrix processing units (MPUs) <NUM>, slicing engine <NUM>, and memory resource blocks (MRBs) <NUM>.

Master control CPU (MCC) <NUM> may be configured to control and/or manage matrix operations performed by a matrix processing cluster <NUM>. In some embodiments, master control CPU <NUM> may be a microprocessor, an integrated circuit, and/or any other type of circuitry and/or processing logic. In some embodiments, master control CPU <NUM> may receive instructions from another component, such as host processor <NUM> of <FIG> and/or controller <NUM> of <FIG>. Based on the instructions, master control CPU <NUM> may then use matrix processing units <NUM> to perform matrix operations, such as matrix multiplication, convolutions, and/or dimension shuffling, among other examples. For example, master control CPU <NUM> may receive an instruction to perform a matrix multiplication operation, such as C = A * B. The instruction may include the handles or identifiers for each matrix, and may also indicate how the matrices should be stored in memory resource blocks (MRBs) <NUM>. Matrices A and B may then be broken down into a series of smaller matrices (e.g., 32x32 matrices). Matrix operations may then be performed on the smaller matrices, and the partial results may be stored in memory resource blocks (MRBs) <NUM>, until the output matrix C has been fully computed.

Matrix processing units (MPUs) <NUM> may be configured to perform matrix operations, such as matrix multiplication, convolutions, and/or dimension shuffling. In some embodiments, matrix processing units (MPUs) <NUM> perform matrix operations based on commands received from master control CPU (MCC) <NUM>. Moreover, in some embodiments, each matrix processing cluster <NUM> may include multiple matrix processing units (MPUs) <NUM>. For example, in the illustrated embodiment, matrix processing cluster <NUM> includes two matrix processing units (MPUs) <NUM>. A matrix processing unit (MPU) <NUM> may be capable of performing matrix operations, such as matrix multiplication, on small matrices (e.g., 32x32 matrices). In some cases, a matrix processing unit (MPU) <NUM> may be designed and/or optimized to perform matrix multiplication operations. A matrix processing unit (MPU) <NUM> may load matrix operands from memory resource blocks (MRBs) <NUM>. In some embodiments, a matrix processing unit (MPU) <NUM> may support the following arithmetic operations: matrix multiplication; unary matrix operations; binary matrix operations, such as addition (+), subtraction (-), multiplication (*), division (/), bitwise XOR, AND, OR, logical and arithmetic left and right shift, comparison (>, <, > = , < = , = = , !=); and column-wise, row-wise, and matrix-wide operations, such as sum, max value, and min value.

Slicing engine <NUM> may be configured to slice the matrix operands of a particular matrix operation into smaller partial matrices. For example, in some embodiments, master control CPU (MCC) <NUM> may use slicing engine <NUM> to break up matrix operands into smaller partial matrices for matrix processing units (MPUs) <NUM>. In some embodiments, slicing engine <NUM> may include a convolution slicing engine (CSE) to perform matrix slicing for convolution operations. For example, in some embodiments, a convolution slicing engine (CSE) may slice matrix operands in a manner that enables a convolution operation to be cast as a matrix multiplication operation, thus enabling the same processing logic to perform both matrix multiplication and convolution operations. Moreover, in some embodiments, slicing engine <NUM> and/or the associated convolution slicing engine (CSE) may be used to perform the dimension shuffle operations to reorder the dimensions of a matrix.

Memory resource blocks (MRBs) <NUM> may be memory components on matrix processing cluster <NUM> used to store matrix operands and other matrix data. In some embodiments, memory resource blocks (MRBs) <NUM> may be designed to store and retrieve matrix data efficiently. In some embodiments, memory resource blocks (MRBs) <NUM> may be multi-dimensional memory components configured to store and retrieve data in multiple dimensions. For example, in some embodiments, memory resource blocks (MRBs) <NUM> may be memory components configured to store and retrieve data in two dimensions, such as rows and columns. In the illustrated embodiment, matrix processing cluster <NUM> includes ten memory resource blocks (MRBs) <NUM>. Other embodiments, however, may include a different number of memory resource blocks (MRBs) <NUM> on a matrix processing cluster <NUM>. In some embodiments, each memory resource block (MRB) <NUM> may be capable of storing a matrix of a certain size (e.g., a <NUM>×<NUM> matrix). In some embodiments, memory resource blocks (MRBs) <NUM> may be shared by the matrix processing units (MPUs) <NUM> of a particular matrix processing cluster <NUM>.

In some embodiments, the matrix processing architecture of <FIG> may be used to implement the matrix processing functionality described throughout this disclosure. For example, matrix processing system <NUM> may be used to perform matrix operations using a distributed approach that achieves <NUM>% processing efficiency using the available processing resources. For example, in some embodiments, a matrix operation may be distributed across multiple processing resources <NUM> that are optimized for matrix processing, thus enabling full utilization of the processing resources <NUM> throughout the duration of the matrix operation. For example, matrix processing system <NUM> may include multiple processing resources <NUM> that are designed and optimized for performing matrix operations. In some embodiments, these processing resources <NUM> may be configured in a single-cyclical or dual-cyclical arrangement. In addition, the processing resources <NUM> may be arranged hierarchically with multiple levels of processing resources. For example, in some embodiments, the processing resources <NUM> may include multiple matrix processing chips <NUM>, multiple high bandwidth memory (HBM) modules <NUM> and multiple matrix processing clusters <NUM> on each matrix processing chip <NUM>, and/or multiple matrix processing units (MPUs) <NUM> on each matrix processing cluster <NUM>. This processing architecture enables matrix operations to be distributed across multiple processing resources <NUM> and/or processing hierarchies with <NUM>% processing efficiency. In addition, this processing architecture enables matrix operations to be efficiently scaled across a variable number of processing resources <NUM> operating in parallel, while still achieving <NUM>% processing efficiency. For example, scaling may be achieved by adjusting the number of processing resources <NUM> used to perform a particular matrix operation, such as the number of matrix processing systems <NUM> or servers, the number of matrix processing chips <NUM> in each matrix processing system <NUM> or server, and so forth.

As an example, the matrix processing architecture of <FIG> may be used to implement matrix multiplication and/or convolution operations. For example, in some embodiments, a matrix multiplication operation may be distributed across multiple processing resources <NUM> in a manner that results in the latency for communicating matrix operands being less than the matrix processing time, which allows the communication of matrix operands to be completed while the matrix processing is being performed. For example, for certain matrix operations involving matrix operands with certain dimensions (e.g., matrix multiplication with a "thin" matrix operand), the time required to access and communicate matrix operands may exceed the time required to perform the actual matrix computations, resulting in idle processing time while the matrix operands are being obtained from memory and/or communicated to processing resources <NUM>. For example, a single-cyclical configuration (e.g., where each processing resource <NUM> only obtains matrix operands and data from one neighboring processing resource <NUM> at any given time) may be unable to achieve <NUM>% processing efficiency for these particular types of matrix operations and matrix operands. However, a dual-cyclical configuration of processing resources <NUM> enables each processing resource to perform matrix computations while simultaneously obtaining matrix operands and data from both of its neighboring processing resources <NUM>, which significantly reduces the latency for communicating matrix operands, and thus avoids any idle processing time. For example, the communication latency for certain operations may be reduced by half when using a dual-cyclical approach as opposed to a single-cyclical approach. In this manner, the latency for communicating matrix operands and matrix data can be fully masked by the matrix processing time, thus avoiding any wasted or idle processing time and achieving <NUM>% processing efficiency. Accordingly, matrix operations (e.g., matrix multiplication or GEMM) can be performed efficiently even for large matrix operands and/or matrix operands with certain dimensions, such as a large matrix operand that is neither square nor a single vector (e.g., a "thin" matrix with a much larger height than width). For example, matrix multiplication can be performed efficiently even when multiplying two thin matrices, a thin matrix and a square matrix, and so forth. Similarly, convolution operations may be distributed across multiple processing resources <NUM> in a manner that results in <NUM>% processing efficiency using the available processing resources.

As an example, when a matrix operation or command is received, the matrix operation may be distributed across the processing resources <NUM> of matrix processing system <NUM>. For example, the matrix operands (or input matrices) may be partitioned based on the number of available processing resources <NUM>. Moreover, in some embodiments, the partitions may be across the rows of the matrix operands, and/or across any other dimension of the matrix operands. Each partition may then be distributed to a particular processing resource <NUM>. Each processing resource <NUM> may then perform a plurality of partial matrix operations. In some embodiments, the plurality of partial matrix operations is performed in a plurality of stages. For example, each processing resource <NUM> may perform a particular stage of partial matrix operations while simultaneously sending and receiving partial matrix data to and from its neighboring processing resources <NUM>. For example, in a single-cyclical configuration of processing resources <NUM>, each processing resource <NUM> either sends or receives partial matrix data to or from each neighbor processing resource. Similarly, in a dual-cyclical configuration of processing resources <NUM>, each processing resource <NUM> may send and receive partial matrix data to and from each neighboring processing resource <NUM>.

Each processing resource <NUM> may then use the partial matrix data for subsequent partial matrix operations. The result of the matrix operation may then be determined based on the partial matrix operations collectively performed by the processing resources <NUM>.

Moreover, if the processing resources <NUM> are arranged hierarchically, the matrix operation may be distributed in a hierarchical manner. For example, the matrix operands (or input matrices) may initially be partitioned based on the number of available matrix processing chips <NUM>. Each partition, and the associated partial matrix operations, may then be distributed to a particular matrix processing chip <NUM>. The partition and partial matrix operations distributed to a particular matrix processing chip <NUM> may then be similarly partitioned and distributed across the matrix processing clusters <NUM> and/or high bandwidth memory (HBM) modules <NUM> of the particular matrix processing chip <NUM>. For example, for certain matrix operations, partial matrix operations may be distributed to each matrix processing cluster <NUM>. Alternatively, for certain matrix operations, partial matrix operations may be distributed across various "logical processing nodes" (e.g., groups of matrix processing clusters <NUM> associated with a high-bandwidth memory (HBM) module <NUM>), and may then be distributed to each matrix processing cluster <NUM> of a particular logical processing node. In some embodiments, the matrix processing clusters <NUM> (and/or the logical processing nodes) may be cyclically configured similar to the matrix processing chips <NUM>. The partition and partial matrix operations distributed to a particular matrix processing cluster <NUM> may then be similarly partitioned and distributed across the matrix processing units (MPUs) <NUM> of the particular matrix processing cluster <NUM>.

<FIG> and <FIG> illustrate block diagrams for example embodiments of computer processors that may be used in accordance with embodiments disclosed herein. For example, the computer processors illustrated in <FIG> and <FIG> may be used as host processors associated with matrix processing systems (e.g., host processor <NUM> in matrix processing system <NUM> of <FIG>), or as processors associated with other components and/or devices discussed throughout this disclosure (e.g., processors associated with components in system <NUM> of <FIG>). Other processor and system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

<FIG> illustrates a block diagram for an example embodiment of a processor <NUM>. Processor <NUM> is an example of a type of hardware device that can be used in connection with the embodiments described throughout this disclosure. Processor <NUM> may be any type of processor, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a multi-core processor, a single core processor, or other device to execute code. Although only one processor <NUM> is illustrated in <FIG>, a processing element may alternatively include more than one of processor <NUM> illustrated in <FIG>. Processor <NUM> may be a single-threaded core or, for at least one embodiment, the processor <NUM> may be multi-threaded in that it may include more than one hardware thread context (or "logical processor") per core.

<FIG> also illustrates a memory <NUM> coupled to processor <NUM> in accordance with an embodiment. Memory <NUM> may be any of a wide variety of memories (including various layers of memory hierarchy) as are known or otherwise available to those of skill in the art. Such memory elements can include, but are not limited to, random access memory (RAM), read only memory (ROM), logic blocks of a field programmable gate array (FPGA), erasable programmable read only memory (EPROM), and electrically erasable programmable ROM (EEPROM).

Processor <NUM> can execute any type of instructions associated with algorithms, processes, or operations detailed herein. Generally, processor <NUM> can transform an element or an article (e.g., data) from one state or thing to another state or thing.

Code <NUM>, which may be one or more instructions to be executed by processor <NUM>, may be stored in memory <NUM>, or may be stored in software, hardware, firmware, or any suitable combination thereof, or in any other internal or external component, device, element, or object where appropriate and based on particular needs. In one example, processor <NUM> can follow a program sequence of instructions indicated by code <NUM>. Each instruction enters a front-end logic <NUM> and is processed by one or more decoders <NUM>. The decoder may generate, as its output, a micro operation such as a fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals that reflect the original code instruction. Front-end logic <NUM> may also include register renaming logic and scheduling logic, which generally allocate resources and queue the operation corresponding to the instruction for execution.

Processor <NUM> can also include execution logic <NUM> having a set of execution units 316a, 316b, 316n, etc. Some embodiments may include a number of execution units dedicated to specific functions or sets of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. Execution logic <NUM> performs the operations specified by code instructions.

After completion of execution of the operations specified by the code instructions, back-end logic <NUM> can retire the instructions of code <NUM>. In one embodiment, processor <NUM> allows out of order execution but requires in order retirement of instructions. Retirement logic <NUM> may take a variety of known forms (e.g., re-order buffers or the like). In this manner, processor <NUM> is transformed during execution of code <NUM>, at least in terms of the output generated by the decoder, hardware registers and tables utilized by register renaming logic <NUM>, and any registers (not shown) modified by execution logic <NUM>.

Although not shown in <FIG>, a processing element may include other elements on a chip with processor <NUM>. For example, a processing element may include memory control logic along with processor <NUM>. The processing element may include I/O control logic and/or may include I/O control logic integrated with memory control logic. The processing element may also include one or more caches. In some embodiments, non-volatile memory (such as flash memory or fuses) may also be included on the chip with processor <NUM>.

<FIG> illustrates a block diagram for an example embodiment of a multiprocessor <NUM>. As shown in <FIG>, multiprocessor system <NUM> is a point-to-point interconnect system, and includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. In some embodiments, each of processors <NUM> and <NUM> may be some version of processor <NUM> of <FIG>.

Processors <NUM> and <NUM> are shown including integrated memory controller (IMC) units <NUM> and <NUM>, respectively. Processor <NUM> also includes as part of its bus controller units point-to-point (P-P) interfaces <NUM> and <NUM>; similarly, second processor <NUM> includes P-P interfaces <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via a point-to-point (P-P) interface <NUM> using P-P interface circuits <NUM>, <NUM>. As shown in <FIG>, IMCs <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> may each exchange information with a chipset <NUM> via individual P-P interfaces <NUM>, <NUM> using point to point interface circuits <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> may optionally exchange information with the coprocessor <NUM> via a high-performance interface <NUM>. In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, matrix processor, or the like.

In one embodiment, first bus <NUM> may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of this disclosure is not so limited.

As shown in <FIG>, various I/O devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. In one embodiment, one or more additional processor(s) <NUM>, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), matrix processors, field programmable gate arrays, or any other processor, are coupled to first bus <NUM>. In one embodiment, second bus <NUM> may be a low pin count (LPC) bus. Various devices may be coupled to a second bus <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage unit <NUM> such as a disk drive or other mass storage device which may include instructions/code and data <NUM>, in one embodiment. Further, an audio I/O <NUM> may be coupled to the second bus <NUM>. Note that other architectures are possible. For example, instead of the point-to-point architecture of <FIG>, a system may implement a multi-drop bus or other such architecture.

All or part of any component of <FIG> may be implemented as a separate or stand-alone component or chip, or may be integrated with other components or chips, such as a system-on-a-chip (SoC) that integrates various computer components into a single chip.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Certain embodiments may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Accordingly, embodiments of this disclosure also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

<FIG> illustrates an example embodiment of a programmable matrix processing engine <NUM>. In some embodiments, matrix processing engine <NUM> may be implemented by a matrix processing architecture, such as the matrix processing architecture of <FIG>. For example, in some embodiments, matrix processing engine <NUM> may be implemented by a matrix processing cluster on a matrix processing chip (e.g., matrix processing clusters <NUM> of matrix processing chip <NUM> from <FIG>). In those embodiments, a particular matrix processing cluster may use its associated matrix processing engine <NUM> to perform matrix-based processing and operations, such as partial matrix operations associated with a particular matrix operation distributed across multiple matrix processing resources (e.g., as described throughout this disclosure).

In the illustrated embodiment, matrix processing engine <NUM> includes read engine <NUM>, slice engines <NUM>, and output engine <NUM>, which are discussed further below. The illustrated embodiment also depicts various components of the underlying matrix processing architecture that may be involved when performing matrix operations using matrix processing engine <NUM>. For example, the illustrated embodiment depicts high bandwidth memory (HBM) modules <NUM>, master control CPU (MCC) <NUM>, matrix processing units (MPUs) <NUM>, memory resource blocks (MRBs) <NUM>, and matrix routine memory <NUM>. In the illustrated embodiment, for example, these various components are superimposed on matrix processing engine <NUM> to illustrate how and when they would be used by matrix processing engine <NUM>, as described further below.

HBM modules <NUM> may be high bandwidth memory (HBM) modules designed to efficiently store and retrieve large volumes of matrix data. In some embodiments, for example, HBM modules <NUM> may be high bandwidth memory (HBM) modules on a matrix processing chip (e.g., HBM modules <NUM> of matrix processing chip <NUM> from <FIG>).

MCC <NUM> may be a master control CPU (MCC) used to control and/or manage matrix operations. In some embodiments, for example, MCC <NUM> may be the master control CPU on a particular matrix processing cluster (e.g., MCC <NUM> of matrix processing cluster <NUM> from <FIG>). In those embodiments, for example, MCC <NUM> may be used to control and/or manage matrix operations performed on its particular cluster.

MPUs <NUM> may be matrix processing units (MPUs) used to perform matrix operations. In some embodiments, for example, MPUs <NUM> may be matrix processing units on a particular matrix processing cluster (e.g., MPUs <NUM> of matrix processing cluster <NUM> from <FIG>). For example, in some embodiments, a matrix processing cluster may include multiple matrix processing units (MPUs) for performing matrix operations. The illustrated embodiment, for example, depicts two matrix processing units (MPUs) 534a and 534b. In some embodiments, MPUs <NUM> may perform matrix operations based on commands or instructions from master control CPU (MCC) <NUM>.

Memory resource blocks (MRBs) <NUM> may be memory components designed to efficiently store and retrieve matrix data. In some embodiments, for example, MRBs <NUM> may be memory resource blocks on a particular matrix processing cluster (e.g., memory resource blocks <NUM> of matrix processing cluster <NUM> from <FIG>). In those embodiments, for example, MRBs <NUM> may be used to store and retrieve matrix data associated with matrix operations performed on the particular cluster.

Matrix routine memory <NUM> may be a memory component used to store matrix routines. A matrix routine, for example, may be a programmable routine for a matrix processor that is designed to perform a particular matrix operation when executed by the matrix processor. For example, a matrix routine may include a series of instructions and/or commands, supported by a particular matrix processor, and designed to perform a desired matrix operation when executed by the matrix processor. In some embodiments, for example, a matrix processor may be designed to support a set of instructions and/or commands for performing various fundamental operations. For example, in some embodiments, a matrix processor may support instructions for processing data, performing various arithmetic operations, and/or identifying matrix operands and outputs for the various instructions and operations.

For example, certain instructions may be used for processing data, such as reading, writing, and/or copying data (e.g., matrix data) to and from different locations, slicing matrix data, extracting matrix data, rearranging matrix data, and so forth.

As another example, certain instructions may be used to perform particular arithmetic operations, including any of the following operations: matrix multiplication; convolutions; unary matrix operations; binary matrix operations, such as addition (+), subtraction (-), multiplication (*), division (/), bitwise XOR, AND, OR, logical and arithmetic left and right shift, comparison (>, <, > =, < =, = = , !=); and column-wise, row-wise, and matrix-wide operations, such as sum, max value, and m in value.

Moreover, special "register operand" (REGOP) instructions may be used to identify the matrix operands and outputs for the various supported instructions and operations. The register operand instructions, for example, may be used to specify the size and location of the operands and outputs of a particular instruction or operation. For example, in some embodiments, a register operand instruction may be used to identify a location in a high bandwidth memory (HBM) module or a memory resource block (MRB) that is associated with a particular operand or output. As an example, a basic matrix multiplication operation could be programmed using REGOP instructions to identify the location of each operand and the location of the output, followed by an instruction to perform a matrix multiplication operation.

In this manner, the fundamental instructions and/or commands supported by the matrix processor can be used to program matrix routines for more complex matrix operations, such as distributed matrix multiplication and/or convolution operations, dimension shuffle operations, reshape operations, and so forth.

Matrix routine memory <NUM> may be implemented in any portion of a matrix processing architecture, such as matrix processing chips, matrix processing clusters, and/or a host computing system. In some embodiments, for example, a matrix processing chip (e.g., matrix processing chip <NUM> of <FIG>) may include a matrix routine memory <NUM> that is accessible to the respective clusters on that matrix processing chip. As another example, in some embodiments, a matrix processing cluster (e.g., matrix processing cluster <NUM> of <FIG>) may include its own matrix routine memory <NUM>. As yet another example, in some embodiments, a host computing system of a matrix processing architecture may include a matrix routine memory <NUM> accessible to its associated matrix processing resources (e.g., in <FIG>, host memory <NUM> of matrix processing system <NUM> may include a matrix routine memory accessible to matrix processing resources <NUM>).

Moreover, matrix routine memory <NUM> may be any component or mechanism capable of storing data, including any type or combination of volatile and/or non-volatile memory, such as random access memory (RAM) (e.g., dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), static random access memory (SRAM)), flash-based memory, read only memory (ROM), logic blocks of a field programmable gate array (FPGA), erasable programmable read only memory (EPROM), electrically erasable programmable ROM (EEPROM), and/or any suitable combination of the foregoing.

As an example, in some embodiments, matrix routine memory <NUM> could be implemented using random access memory (e.g., SRAM) on a matrix processing chip. In these embodiments, for example, matrix routines could be loaded on matrix routine memory <NUM> by a host computing system (e.g., host processor <NUM> of <FIG>). For example, a host computing system could transfer the matrix routines to a matrix processing chip via an interconnect interface (e.g., a PCIe interface), and the matrix processing chip could then store the matrix routines on its associated matrix routine memory <NUM>. In some embodiments, a software driver of the host computing system could be used to load the matrix routines. Moreover, in some embodiments, any existing matrix routines could be loaded on matrix routine memory <NUM> during system startup, while any additional matrix routines could be subsequently loaded after system startup, as appropriate.

In the illustrated example, matrix processing engine <NUM> performs multiple matrix operations <NUM> and <NUM> in parallel. For example, as noted above, in some embodiments matrix processing engine <NUM> may be implemented on a particular matrix processing cluster, and the particular matrix processing cluster may include multiple MPUs <NUM>. In the illustrated example, matrix processing engine <NUM> is implemented on a cluster with two MPUs 534a-b. Accordingly, matrix processing engine <NUM> can perform two matrix operations <NUM> and <NUM> in parallel using the respective MPUs <NUM>. The illustrated example shows the control flow of matrix processing engine <NUM> for both the <NUM>st matrix operation <NUM> and the <NUM>nd matrix operation <NUM>.

In the illustrated example, the control flow for the <NUM>st matrix operation <NUM> begins with the read engine <NUM> of matrix processing engine <NUM>. Read engine <NUM> may first retrieve matrix data (e.g., matrix data associated with the operands of matrix operation <NUM>) from a corresponding HBM module 540a of a matrix processing chip, and read engine <NUM> may then store that matrix data in certain MRBs 538a of the particular cluster associated with read engine <NUM>. For example, as noted above, HBM module 540a may be a high bandwidth memory module on a particular matrix processing chip (e.g., memory shared by the matrix processing clusters of the particular matrix processing chip), and MRBs <NUM> may be local memory resource blocks on a particular matrix processing cluster. Moreover, in some embodiments, read engine <NUM> may use the master control CPU (MCC) <NUM> on its respective cluster for storing and retrieving data on HBMs <NUM> and MRBs <NUM>.

Slice engine 536a may then "slice" the matrix data stored in MRBs 538a to extract the particular matrix operands associated with matrix operation <NUM>. For example, in some cases, the associated matrix operands may only include a subset of the matrix data stored in MRBs 538a, and/or the matrix operands may not be arranged contiguously in the matrix data stored in MRBs 538a. Accordingly, slice engine 536a may extract particular "slices" or pieces of the matrix data stored in MRBs 538a, and may then arrange the slices to form the respective matrix operands. For example, in the illustrated example, matrix operation <NUM> is associated with a convolution operation, and accordingly, slice engine 536a is used to extract a sliced matrix operand and filter from the matrix data stored in MRBs 538a. The sliced matrix operand and filter are then stored in MRBs 538b and 538c, respectively. In some cases, the particular slicing approach used by slice engine 536a may depend on various factors, including the type of matrix operation <NUM>, the number of available processing resources, the size of the operands, and so forth. Moreover, in some embodiments, the particular slicing performed by slice engine 536a for a particular operation may be programmed and/or defined using a set of instructions supported by slice engine 536a.

Output engine <NUM> may then be used to compute a result for the particular matrix operation <NUM>. For example, output engine <NUM> may perform the appropriate matrix operation <NUM> using the matrix operands generated by slice engine 536a (e.g., the matrix operands stored in MRBs 538b and 538c). For example, in some embodiments, output engine <NUM> may first identify an associated matrix routine corresponding to the particular matrix operation <NUM>, and output engine <NUM> may then obtain that matrix routine from matrix routine memory <NUM>. In some embodiments, output engine <NUM> may use the master control CPU (MCC) <NUM> on its respective cluster to retrieve matrix routines from matrix routine memory <NUM>.

Output engine <NUM> may then specify or supply certain information or fields used by the matrix routine, if appropriate. For example, in some embodiments, certain information and/or fields of a matrix routine may be incomplete or unspecified, such as the size and/or location of the particular operands for the matrix routine. Accordingly, in some embodiments, output engine <NUM> may use MCC <NUM> to specify or supply any remaining information and/or fields for the particular matrix routine (e.g., the size and/or location of matrix operands).

Output engine <NUM> may then execute the particular matrix routine. For example, output engine <NUM> may use MCC <NUM> and/or MPU 534a to execute the programmed instructions associated with the particular matrix routine. MCC <NUM>, for example, may be used to perform certain tasks specified by the instructions, such as reading and writing data, communicating with other resources, and so forth. MPU 534a, for example, may be used to perform particular arithmetic operations specified by the instructions. Moreover, in some cases, a particular matrix routine may be repeatedly executed or looped until the particular operation has been performed or completed for all requisite data (e.g., all data of a particular matrix operand).

Output engine <NUM> may then store the output or result of the matrix routine in certain MRB(s) 538d of the cluster used to execute the matrix routine. In some cases, output engine <NUM> may then provide the output stored in MRBs 538d to another component of the matrix processing architecture. For example, in some cases, a matrix operation <NUM> may be a partial matrix operation associated with a larger matrix operation distributed across multiple processing resources, and thus the output of matrix operation <NUM> may be a partial result associated with the larger distributed operation. Moreover, the output of partial matrix operation <NUM> may be needed by other processing resource(s) involved in the distributed matrix operation. Accordingly, output engine <NUM> may provide the output of partial matrix operation <NUM> to the appropriate resource, for example, for further processing and/or storage. In some cases, the appropriate resource may vary based on the circumstances, including the type of matrix operation being performed, the implementation of the associated matrix routine(s), the number and availability of processing resources, and so forth. For example, in some cases, the particular processing and/or destination of the output of a matrix operation may be programmed or defined by the associated matrix routine. Moreover, in some embodiments, output engine <NUM> may use the master control CPU (MCC) <NUM> on its respective cluster in order to provide the output of partial matrix operation <NUM> to the appropriate destination.

In some cases, for example, output engine <NUM> may provide the output of partial matrix operation <NUM> (e.g., the output stored in MRBs 538d) to a particular destination used to store the partial results of a distributed matrix operation. For example, for a distributed matrix operation, the respective partial results determined by each processing resource may be consolidated on a particular memory component, such as a particular HBM 540b of a matrix processing chip. For example, in some cases, the respective partial results determined by each cluster of a matrix processing chip may be consolidated on a particular HBM 540b of the matrix processing chip. Moreover, the partial results may be stored on an HBM 540b using a particular arrangement that collectively forms the complete result of the matrix operation.

As another example, in some cases output engine <NUM> may feed the output of partial matrix operation <NUM> (e.g., the output stored in MRBs 538d) back to MPU 534a, for example, to enable MPU 534a to use that output as an operand in a subsequent partial operation. In some cases, for example, the output of a partial operation in one stage of a distributed matrix operation may be used as an input or operand for a partial operation in another stage of the distributed matrix operation.

As another example, in some cases output engine <NUM> may provide the output of partial matrix operation <NUM> (e.g., the output stored in MRBs 538d) to another matrix processing resource, such as another matrix processing cluster on the same matrix processing chip, or another matrix processing chip altogether. For example, in some cases, a distributed matrix operation may be distributed across multiple clusters of a matrix processing chip, and/or across multiple matrix processing chips. Moreover, in some cases, the output of a partial operation performed by a particular matrix processing resource may be used as an operand in another partial operation performed by a different processing resource.

In the illustrated example, the <NUM>nd matrix operation <NUM> may be executed in parallel with the <NUM>st matrix operation <NUM>. Moreover, the control flow for the <NUM>nd matrix operation <NUM> may be similar to the control flow described above for the <NUM>st matrix operation <NUM>. The <NUM>nd matrix operation <NUM>, however, may be a different matrix operation (e.g., performed using a different matrix routine), with different matrix operands and results, using different memory locations of HBMs <NUM> and/or MRBs <NUM>, and executed using a different MPU 534b and associated slicing engine 536b.

<FIG> illustrates a flowchart <NUM> for an example embodiment of programmable matrix processing. Flowchart <NUM> may be implemented, in some embodiments, by components described throughout this disclosure (e.g., the matrix processing architecture of <FIG> and/or the programmable matrix processing engine of <FIG>).

The flowchart may begin at block <NUM> by receiving a command to perform a matrix operation. The matrix operation may comprise an operation on one or more matrix operands. For example, the matrix operation could include any matrix-based arithmetic operation, including element-wise matrix operations, matrix multiplication, convolutions, and/or any combination of such operations.

Moreover, in some embodiments, matrix operations may be used to implement computer vision artificial intelligence and machine learning capabilities in an artificial neural network. For example, in some embodiments, the matrix operation of block <NUM> may be associated with operations in an artificial neural network, such as forward propagation, backward propagation, and/or weight update operations.

The flowchart may then proceed to block <NUM> to obtain matrix data from memory. The matrix data, for example, may be associated with one or more matrix operands of the matrix operation. In some embodiments, the matrix data may be obtained from multi-dimensional memory. Multi-dimensional memory, for example, may be a memory component designed to efficiently store and retrieve matrix data in multiple dimensions (e.g., two-dimensions). In some embodiments, the matrix data may be obtained by executing one or more instructions to obtain the matrix data from one or more memory locations of the multi-dimensional memory.

The flowchart may then proceed to block <NUM> to obtain matrix operands from the matrix data. In some embodiments, for example, the matrix operands may be obtained by slicing the matrix data to extract the matrix operands from the matrix data. Moreover, in some embodiments, the matrix operands may be obtained by executing one or more instructions to slice or extract the matrix operands from the matrix data.

The flowchart may then proceed to block <NUM> to identify a matrix routine associated with the matrix operation. A matrix routine, for example, may be a programmable routine for a matrix processor that is designed to perform a particular matrix operation when executed by the matrix processor. For example, a matrix routine may include a series of instructions and/or commands, supported by a particular matrix processor, and designed to perform a desired matrix operation when executed by the matrix processor. In some embodiments, for example, a matrix processor may be designed to support a set of instructions and/or commands for performing various fundamental matrix operations. For example, a matrix processor may include instructions and/or commands for identifying memory locations of matrix operands, obtaining matrix operands from memory, and/or performing particular arithmetic operations or computations on the matrix operands, among other examples. In this manner, the fundamental instructions and/or commands supported by the matrix processor can be used to program matrix routines for more complex matrix operations.

In some embodiments, a matrix routine memory may be used to store matrix routines, and the matrix routines may be retrieved from the matrix routine memory as needed. For example, in order to perform a desired matrix operation, a corresponding matrix routine may first be obtained from the matrix routine memory. In some cases, however, a particular matrix routine may not yet be stored on the matrix routine memory. Accordingly, the particular matrix routine may need to be loaded on the matrix routine memory. Thus, in some cases, a particular matrix routine may first be obtained from a host computing system, and may then be stored on the matrix routine memory.

The flowchart may then proceed to block <NUM> to execute the matrix routine. In some embodiments, for example, the matrix routine may be executed on a matrix processor using the one or more matrix operands. The flowchart may then proceed to block <NUM> to obtain a result of the matrix operation based on the matrix routine executed by the matrix processor. For example, in some cases, the particular matrix routine may return a result determined by the series of instructions and/or commands executed by the matrix processor.

At this point, the flowchart may be complete. In some embodiments, however, the flowchart may restart and/or certain blocks may be repeated. For example, in some embodiments, the flowchart may restart at block <NUM> to continue receiving and processing commands to perform matrix operations.

The flowcharts and block diagrams in the FIGURES illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various aspects of the present disclosure. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order or alternative orders, depending upon the functionality involved.

The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the scope of the present disclosure.

All or part of any hardware element disclosed herein may readily be provided in a system-on-a-chip (SoC), including a central processing unit (CPU) package. An SoC represents an integrated circuit (IC) that integrates components of a computer or other electronic system into a single chip. The SoC may contain digital, analog, mixed-signal, and radio frequency functions, all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip-module (MCM), with a plurality of chips located within a single electronic package and configured to interact closely with each other through the electronic package. In various other embodiments, the computing functionalities disclosed herein may be implemented in one or more silicon cores in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and other semiconductor chips.

As used throughout this specification, the term "processor" or "microprocessor" should be understood to include not only a traditional microprocessor (such as Intel's® industry-leading x86 and x64 architectures), but also matrix processors, graphics processors, and any ASIC, FPGA, microcontroller, digital signal processor (DSP), programmable logic device, programmable logic array (PLA), microcode, instruction set, emulated or virtual machine processor, or any similar "Turing-complete" device, combination of devices, or logic elements (hardware or software) that permit the execution of instructions.

In a general sense, any suitably-configured processor can execute instructions associated with data or microcode to achieve the operations detailed herein. Any processor disclosed herein could transform an element or an article (for example, data) from one state or thing to another state or thing. In another example, some activities outlined herein may be implemented with fixed logic or programmable logic (for example, software and/or computer instructions executed by a processor) and the elements identified herein could be some type of a programmable processor, programmable digital logic (for example, a field programmable gate array (FPGA), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM)), an ASIC that includes digital logic, software, code, electronic instructions, flash memory, optical disks, CD-ROMs, DVD ROMs, magnetic or optical cards, other types of machine-readable mediums suitable for storing electronic instructions, or any suitable combination thereof.

In operation, a storage may store information in any suitable type of tangible, non-transitory storage medium (for example, random access memory (RAM), read only memory (ROM), field programmable gate array (FPGA), erasable programmable read only memory (EPROM), electrically erasable programmable ROM (EEPROM), or microcode), software, hardware (for example, processor instructions or microcode), or in any other suitable component, device, element, or object where appropriate and based on particular needs. Furthermore, the information being tracked, sent, received, or stored in a processor could be provided in any database, register, table, cache, queue, control list, or storage structure, based on particular needs and implementations, all of which could be referenced in any suitable timeframe. Any of the memory or storage elements disclosed herein should be construed as being encompassed within the broad terms 'memory' and 'storage,' as appropriate. A non-transitory storage medium herein is expressly intended to include any non-transitory special-purpose or programmable hardware configured to provide the disclosed operations, or to cause a processor to perform the disclosed operations. A non-transitory storage medium also expressly includes a processor having stored thereon hardware-coded instructions, and optionally microcode instructions or sequences encoded in hardware, firmware, or software.

Computer program logic implementing all or part of the functionality described herein is embodied in various forms, including, but in no way limited to, hardware description language, a source code form, a computer executable form, machine instructions or microcode, programmable hardware, and various intermediate forms (for example, forms generated by an HDL processor, assembler, compiler, linker, or locator). In an example, source code includes a series of computer program instructions implemented in various programming languages, such as an object code, an assembly language, or a high-level language such as OpenCL, FORTRAN, C, C+ +, JAVA, or HTML for use with various operating systems or operating environments, or in hardware description languages such as Spice, Verilog, and VHDL. The source code may define and use various data structures and communication messages. The source code may be in a computer executable form (e.g., via an interpreter), or the source code may be converted (e.g., via a translator, assembler, or compiler) into a computer executable form, or converted to an intermediate form such as byte code. Where appropriate, any of the foregoing may be used to build or describe appropriate discrete or integrated circuits, whether sequential, combinatorial, state machines, or otherwise.

In one example, any number of electrical circuits of the FIGURES may be implemented on a board of an associated electronic device. The board can be a general circuit board that can hold various components of the internal electronic system of the electronic device and, further, provide connectors for other peripherals. More specifically, the board can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processor and memory can be suitably coupled to the board based on particular configuration needs, processing demands, and computing designs. Other components such as external storage, additional sensors, controllers for audio/video display, and peripheral devices may be attached to the board as plug-in cards, via cables, or integrated into the board itself. In another example, the electrical circuits of the FIGURES may be implemented as stand-alone modules (e.g., a device with associated components and circuitry configured to perform a specific application or function) or implemented as plug-in modules into application specific hardware of electronic devices.

Note that with the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electrical components. However, this has been done for purposes of clarity and example only. It should be appreciated that the system can be consolidated or reconfigured in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, and elements of the FIGURES may be combined in various possible configurations, all of which are within the broad scope of this specification. In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows by only referencing a limited number of electrical elements. It should be appreciated that the electrical circuits of the FIGURES and its teachings are readily scalable and can accommodate a large number of components, as well as more complicated/sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of the electrical circuits as potentially applied to a myriad of other architectures.

Claim 1:
An apparatus comprising:
a plurality of matrix processing chips (220a, ..., 220d) integrated on a package and configured in a cyclical arrangement, each matrix processing chip (220a, ..., 220d) to process matrix instructions;
inter-chip links, ICLs, (<NUM>) to connect two or more of the plurality of matrix processing chips (220a, ..., 220d), the ICLs to enable bi-directional communication between neighboring ones of the two or more matrix processing chips of the plurality of matrix processing chips (220a, ..., 220d);
a plurality of high bandwidth memory, HBM, modules (240a, ...240d), an HBM module (240a, ...240d) of the plurality of HBM modules (240a, ...240d) to store matrix data for processing by a matrix processing chip of the plurality of matrix processing chips (220a, ..., 220d);
each of the plurality of matrix processing chips (220a, ..., 220d) comprising:
a host interface (<NUM>) to couple the respective matrix processing chip to a host processor (<NUM>),
a controller (<NUM>) to control and/or manage matrix operations of a programmed matrix routine comprising a series of instructions and/or commands supported by the respective matrix processing chip,
a plurality of programmable matrix processing units (<NUM>) coupled to the controller (<NUM>) configured to perform a matrix multiplication operation based on a matrix multiplication instruction from the programmed matrix routine, the matrix multiplication instruction specifying matrix operands, including a first input matrix, A, and a second input matrix, B, the matrix processing units (<NUM>) to produce an output matrix, C, by multiplying the first input matrix, A, and the second input matrix, B, and
a slicing engine (<NUM>) configured to slice the matrix operands of particular matrix operations into smaller partial matrices, the slicing engine comprising a convolution slicing engine, CSE, which slices matrix operands in a manner that enables a convolution operation to be cast as the matrix multiplication operation comprising to perform dimension shuffle operations to reorder the dimensions of the matrix operands.