Patent Description:
A memory whose data is protected against transient errors using error correcting code (ECC) is called an ECC memory. Error-correcting code (ECC) memory is a type of computer data storage that can detect and correct the most common kinds of internal data corruption. ECC memory is used in computers where data corruption cannot be tolerated under nearly any circumstances, such as for, safety, scientific and/or financial computing. ECC memory has Error Correcting Code (ECC) bits along with data to facilitate detection and correction of errors. The extra error correcting code bits can be stored along with the data in the data memory or in a separate code memory of the ECC memory. A common error correcting code, a single-error correction and double-error detection (SECDED) Hamming code, allows a single-bit error to be corrected and double-bit errors to be detected.

In some examples, ECC memory maintains a memory system immune to single-bit errors. Accordingly, the data that is read from each word in ECC memory is the same as the data that had been written to the ECC memory, even if one or more bits previously stored have been flipped to the wrong state. ECC schemes may be based on a data size that is larger than a smallest size of data that can be written, which is referred to a "partial data write". For such partial data writes, a read-modify-write operation is performed. To execute a read-modify-write operation, data is read data from the memory and checked for errors using the ECC checking logic. In case of a single bit error (SBE), the data is repaired using correction logic and corrected read data is then combined with the partial write data and written into the data memory. Combined data is also used to compute a new ECC code to be written into the code memory. <CIT> relates to a memory component having an internal read modify-write operation. The read data is always corrected prior to merging with the write data associated with the read-modify-write operation.

A memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data before correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

A memory controller includes an ECC check and repair module that receives read data and an error-correcting code from ECC memory and provides an ECC error signal indicating whether an error is detected in at least one bit location of the read data. The memory controller also includes a read-modify-write logic module that receives a partial write data request for partial write data in the ECC memory and combines the partial write data in the partial write data request with the read data provided from the ECC memory to form combined data before the ECC check and repair module detecting an error in the at least one bit location of the read data. The memory controller further includes a write control module that controls writing of the combined data to the ECC memory based on the ECC error signal.

A method includes receiving a partial write data request for data in ECC memory. The method also includes combining partial write data in the partial write data request with read data provided from the ECC memory to form combined data. The method further includes checking the accuracy of the read data in parallel with the combining.

Example embodiments include memory controllers and methods for implementing error-correcting code (ECC) protected memory during a partial memory write operation. The memory controllers are configured to operate in a manner that meets relatively tight timing requirements for ECC cores (main/master controllers) of large memories (data storage) including partial-width data writes.

In at least one example, the memory controller implements a read path and a write path that operate in parallel during a partial write. For example, in a parallel operation, data that is read from an ECC memory ("read data") is combined with partial write data before correcting errors in the read data. The resultant combined data is employed to generate a new error-correcting code on the write path. For simplicity of explanation, as used henceforth, the term "ECC" denotes hardware (e.g., ECC memory), and the term "error-correcting code" denotes an actual instance of data that represents the error-correcting code, which may also be referred to as an error code word.

In parallel (e.g., both operating concurrently and operating on a parallel path), the error-correcting code is regenerated (re-computed), and a syndrome is generated for the read data by comparing the regenerated error-correcting code against the stored error-correcting code in code memory. The syndrome is used to decode the data bit error location in case of a single bit error detection. If an error is found to be in a bit location that is used to generate the combined data for computing a new error-correcting code for a partial write, the memory controller flips corrupted bits (through an XOR operation) and the resulting repaired data (which includes the partial write data) is written to memory. Similarly, bits in the error-correcting code that are impacted by corrupted data bits are flipped (through an XOR function) using a relatively simple logic gate operation (e.g., one level of logic) to generate a repaired error-correcting code, which is written to the ECC memory. By generating the error-correcting code for the read and write paths in parallel, the timing of the controller is relaxed by avoiding the need for serial (back-to-back) calculations of error-correcting codes. For example, by employing the parallel paths, as described herein, the partial write can be completed in two (<NUM>) clock cycles. In such a situation, during a first clock cycle, data is read from the data memory. During a second clock cycle, combined data is generated by combining data in the partial write with the read data, a new error-correcting code for the combined data is computed, and the combined data and the new error correcting code are written to the ECC memory (after the XOR function).

In another example, the memory controller implements pipelined-parallel processes on a read path and a write path to execute a partial memory write operation. In high frequency designs involving memories of big size (e.g., <NUM> Gigabyte or more), the memory delays may prohibit adding more logic levels on the read path. In such situations, the read data is registered (stored in a delay) before being used on the read path. The registering precedes error-correcting code computation and syndrome decoding on the read path. This registering results in latency increasing for a partial memory write (in the read-modify-write operation) by at least one clock cycle, such that the partial write operation completes in at least <NUM> clocks cycles instead of <NUM> clock cycles. However, the extra clock cycle can be avoided/mitigated by employment of pipelined-parallel operations, which is described as follows.

In the pipelined-parallel operations of a partial write, in a first clock cycle the data is read from ECC memory ("read data"). Moreover, a stall signal is asserted to the master controller to hold the write control signals for the ECC memory for one more clock cycle. In the second clock cycle, the read data is combined with the partial write data by the memory controller to form combined data, and an ECC generator generates a new error-correcting code. The combined data and the new error-correcting code are written into the ECC memory, and the stall signal is de-asserted. Also, in the second clock cycle, the read data is registered in a delay (flip flops).

The registered read data is available in the third clock cycle and is checked for data corruption. In case of a single bit error, the memory controller re-asserts the stall signal for one additional clock cycle to update the data in and the error-correcting code in the ECC memory with the correct values. Because the probability of a memory bit corruption is expected to be very low and infrequent (e.g., less than about <NUM> % of the time), the additional latency of one more clock cycle for error correcting is non-consequential.

<FIG> illustrates a block diagram of a portion of a memory controller <NUM> for executing a partial write to ECC memory <NUM> through a read-modify-write operation. The term "partial write" may alternatively be referred to as a partial data write or a partial data transfer. The ECC memory <NUM> is a non-transitory machine readable medium (e.g., random access memory) that may be employed in situations where highly accurate data (e.g., non-corrupted) is needed. Accordingly, ECC memory <NUM> is often employed in safety applications, such as automotive brake control and/or airbag deployment wherein incorrect (corrupted data) could cause the improper function of the safety system. However, the ECC memory <NUM> may be deployed in nearly any computing environment where highly accurate data is needed or desired. The ECC memory <NUM> includes a data memory <NUM> and a code memory <NUM>.

The data memory <NUM> includes memory cells for storing data, and the code memory <NUM> includes data cells for storing error-correcting codes for data stored in the data memory <NUM>. Data words (referred to simply as "words") are formed of multiple cells in the data memory <NUM> and the code memory <NUM> are uniquely addressable. Data stored in data memory <NUM> of the ECC memory <NUM> has an assigned word size of K bits, where K is an integer equal greater than or equal to two (<NUM>).

In at least one example, the memory controller <NUM> includes read-modify-write logic <NUM> (a read-modify-write logic module) that executes a read-modify-write operation on the ECC memory <NUM> in response to a partial write data request (labeled in <FIG> as "PARTIAL WR DATA"). The partial write data request includes a unique address for a word in the data memory <NUM>. Moreover, the partial write data request includes T number of bits to be written to the data memory <NUM>, where T is an integer greater than or equal to one (<NUM>) and less than K, the word size of the data memory <NUM>. Accordingly, if the data memory <NUM> has a word size of <NUM> bits, T can be <NUM>-<NUM> bits to be written to the data memory <NUM> in the read-modify-write operation.

The read-modify-write logic <NUM> receives an active low memory enable signal ("EZ" in <FIG>) and an active low write enable signal ("WZ" in <FIG>) concurrently with the partial write data request. As used herein, an active low signal is asserted in situations where the active low signal is a logical '<NUM>' and de-asserted in situations where the active low signal is a logical '<NUM>'. If the memory enable EZ is de-asserted (e.g., a logical '<NUM>'), the memory cells included ECC memory <NUM> are inactive, and cannot be read and cannot be written to. Conversely, if EZ is asserted (e.g., a logical '<NUM>'), the memory cells included in the ECC memory are active and can be read from and/or written to. Moreover, WZ is de-asserted (e.g., logical '<NUM>') while EZ is asserted (e.g., logical '<NUM>'), the ECC memory <NUM> is executing a read operation. Also, if WZ is asserted (e.g., logical '<NUM>') while EZ is asserted (e.g., logical '<NUM>'), the ECC memory is executing a write operation.

In response to the write signal, WZ and the memory enable signal, EZ being asserted (e.g., logical '<NUM>'), the read-modify-write logic <NUM> asserts an active-low stall signal, STALL_N (logical '<NUM>'), which prevents subsequent memory operations on the ECC memory <NUM>. Also, the read-modify-write logic <NUM> forwards an address signal, MEM ADDR (included in the partial write data request, PARTIAL WR DATA) to the ECC memory <NUM>. In response, the data memory <NUM> provides a read data signal ("RD DATA" in <FIG>. ) to the read-modify-write logic <NUM>. The read data signal, RD DATA includes the data stored at the memory location of the data memory <NUM> identified in the address of the signal (e.g., a data word).

In response to the read data signal, RD DATA, the read-modify-write logic <NUM> combines the data in RD DATA with data in the partial write data request, PARTIAL WR DATA to form combined data and generate a write data signal ("WR DATA" in <FIG>). The write data signal, WR DATA contains the combined data that is to be written to the same location the data memory <NUM> (the location identified by the address signal, MEM ADDR). The write data signal WR DATA is generated before any error-correcting of the data in the read data signal RD DATA. The write data signal WR DATA is provided to a write control <NUM> (a write control module) and to an ECC generator <NUM>.

In response to the write data signal, WR DATA, the ECC generator <NUM> generates a new error-correcting code for the combined data included in the write data signal, WR DATA and forwards the new error-correcting code to the write control <NUM>. The write control <NUM> controls a timing of writing data to the data memory <NUM> and the code memory <NUM>.

In a first example (hereinafter, "the first example"), which may be referred to as a parallel operation, and is described in detail with respect to <FIG>, the read data signal, RD DATA is also provided to an ECC check and repair <NUM> (an ECC check and repair module). Also, in response to the address signal, MEM ADDR, the code memory <NUM> of the ECC memory <NUM> provides an error-correcting code signal ("ECC1 in <FIG>") to the ECC check and repair <NUM>. The error-correcting code signal, ECC includes an error-correcting code stored at an address in the code memory <NUM> that corresponds to the address identified by the address signal, MEM ADDR, which address can be referred to as the error code address.

Continuing with the first example, in response to the read data signal, RD DATA, the ECC check and repair <NUM> employs the error-correcting code, ECC1 to identify errors in the data included in the read data signal, RD DATA. Moreover, the ECC check and repair <NUM> generates a data repair pattern signal ("DATA REPAIR PATTERN" in <FIG>) that is provided to the write control <NUM>. The data repair pattern signal, DATA REPAIR PATTERN includes data for correcting errors. Similarly, the ECC check and repair <NUM> generates an ECC repair pattern signal ("ECC REPAIR PATTERN") that is provided to the write control <NUM>.

In the first example, the write control <NUM> employs the combined data in the write data signal, WR DATA and the data in the data repair pattern signal, DATA REPAIR PATTERN to generate a repaired data signal that includes data that is written to the data memory <NUM> at the address identified in the address signal, MEM ADDR. Also, the write control <NUM> employs the new error-correcting code from the ECC generator <NUM> and the ECC repair pattern signal, ECC REPAIR PATTERN from the error check and repair <NUM> to generate a repaired error-correcting code for the data that is written to the code memory <NUM> at the error code address. Further, following the repaired error-correcting code being written, the read-modify-write logic <NUM> de-asserts the stall signal, STALL_N (e.g., logical '<NUM>') to enable subsequent memory operations on the ECC memory <NUM>.

In a second example (hereinafter, "the second example"), which may be referred to as a pipelined-parallel operation and is described in detail with respect to <FIG>, in response to the write data signal, WR DATA and the new error-correcting code, the write control <NUM> writes the combined data to the data memory <NUM> at the address identified in the address signal, MEM ADDR and the new error-correcting code to the error code address of the code memory <NUM>. Further, the read-modify-write logic <NUM> de-asserts the stall signal, STALL_N (e.g., logical '<NUM>').

Subsequently, the read-data signal, RD DATA (registered in delays) and the error-correcting code, ECC1 are analyzed for errors, and if the ECC check and repair <NUM> determines that a single bit error is present in the data included in the read data signal, RD DATA, the ECC check and repair <NUM> asserts (e.g., logical '<NUM>') an ECC single bit error signal ("ECC SBE" in <FIG>) and provides the ECC single bit error signal, ECC SBE to the write control <NUM> and to the read-modify-write logic <NUM>. The ECC single bit error signal, ECC SBE may alternatively be referred to as an ECC error signal. Conversely, if the ECC check and repair <NUM> determines that no error is present in the read data signal, RD DATA, the ECC single bit error signal, ECC SBE is de-asserted (e.g., logical '<NUM>') and provided to the write control <NUM> and to the read-modify-write logic <NUM>.

In the second example, in response to the single bit error signal, ECC SBE being asserted (e.g., logical '<NUM>'), the read-modify-write logic <NUM> asserts the stall signal, STALL_N (e.g., logical '<NUM>') that prevents subsequent data transfers for other operations on the ECC memory <NUM>. Also, assertion of the single bit error signal, ECC SBE causes the write control <NUM> to employ the data repair pattern signal, DATA REPAIR PATTERN and the ECC repair pattern signal, ECC REPAIR PATTERN to correct the data that was written to the address of the data memory <NUM> identified in the address signal, MEM ADDR and to the error-correcting code that was written to the error address of the code memory <NUM>. Moreover, the read-modify-write logic <NUM> de-asserts the stall signal, STALL_N and allows subsequent operations on the ECC memory <NUM>.

Conversely, in the second example, in response to the single bit error signal, ECC SBE being de-asserted (e.g., logical '<NUM>'), the read-modify-write logic <NUM> continues to de-assert the stall signal, STALL_N (e.g., logical '<NUM>'). In this manner, the combine data and the new error-correcting code written to the ECC memory <NUM> are unchanged.

In both the first and second examples, the data (included in RD DATA) is read from the data memory <NUM> and combined with the data in the partial write data request, PARTIAL WR DATA before error correction of the data in the read data signal, RD DATA. Thus, the error correction is executed in parallel with other operations to reduce latency of the read-modify-write operation.

<FIG> illustrates another example of a block diagram of a portion of a memory controller <NUM> for executing a partial write to ECC memory <NUM> with a read-modify-write operation. The memory controller <NUM> executes processes in a parallel operation. In at least one example, the memory controller <NUM> may be employed to implement the memory controller <NUM> illustrated in <FIG>. The ECC memory <NUM> is a non-transitory machine readable medium (e.g., random access memory) that may be employed in situations where highly accurate data (e.g., non-corrupted) is needed, such as safety applications (e.g., automotive), financial applications or the like. The ECC memory <NUM> includes a data memory <NUM> and a code memory <NUM>.

The data memory <NUM> includes memory cells for storing data, and the code memory <NUM> includes data cells for storing error-correcting codes for data stored in the data memory <NUM>. Words are formed of multiple cells in the data memory <NUM> and the code memory <NUM> are uniquely addressable. Data stored in data memory <NUM> of the ECC memory <NUM> has an assigned word size of K bits.

In at least one example, the memory controller <NUM> includes read-modify-write logic <NUM> that executes a read-modify-write operation on the ECC memory <NUM> in response to a partial write data request (labeled in <FIG> as "PARTIAL WR DATA"). The partial write data request, PARTIAL WR DATA includes a unique address for a word in the data memory <NUM>. Moreover, the partial write data request, PARTIAL WR DATA includes T number of bits to be written to the data memory <NUM>, where T is an integer greater than or equal to one (<NUM>) and less than K, the word size of the data memory <NUM>. Accordingly, if the data memory <NUM> has a word size of <NUM> bits, T can be <NUM>-<NUM> bits to be written to the data memory <NUM> in the read-modify-write operation.

The read-modify-write logic <NUM> receives an active low memory enable signal ("EZ" in <FIG>) and an active low write enable signal ("WZ" in <FIG>) concurrently with the partial write data request, PARTIAL WR DATA. In response to the write enable signal, WZ and the memory enable signal, EZ being de-asserted (e.g., logical '<NUM>'), in a first clock cycle (from a master memory controller, not shown), the read-modify-write logic <NUM> asserts a stall signal, STALL_N, which prevents subsequent memory operations on the ECC memory <NUM>. Also, the read-modify-write logic <NUM> forwards an address signal, MEM ADDR (included as ADDR in the partial write data signal, PARTIAL WR DATA to the data memory) to the ECC memory <NUM>. The read-modify-write logic <NUM> also provides an active-low asserted conditioned memory enable signal, MEM EZ (e.g., logical '<NUM>') and an active-low de-asserted conditioned memory rewrite signal, MEM WZ (e.g., logical '<NUM>') that correspond to the memory enable signal, MZ and the write enable signal, WZ. In response, the data memory <NUM> provides a read data signal ("RD DATA" in <FIG>. ) to the read-modify-write logic <NUM> and to an ECC generator <NUM> of an ECC check and repair <NUM>. The read data signal, RD DATA includes the data stored at the memory address identified in the address signal, MEM ADDR (e.g., a data word). In further response to the address signal, MEM ADDR, the code memory <NUM> of the ECC memory <NUM> provides an error-correcting code signal ("ECC1 in <FIG>") to an ECC compare <NUM> of the ECC check and repair <NUM>. The error-correcting code signal, ECC includes an error code stored at an address in the code memory <NUM> that corresponds to the address identified by the address signal, MEM ADDR, which address can be referred to as the error code address.

In the second clock cycle (from the main memory controller), in response to the read data signal, RD DATA, the read-modify-write logic <NUM> modifies the data in RD DATA by combining the data in RD DATA with data in the partial write data request, PARTIAL WR DATA to generate a write data signal ("WR DATA" in <FIG>). Also, the read-modify-write logic <NUM> asserts the MEM_WZ signal (e.g., logical '<NUM>'). The write data signal, WR DATA contains combined data that is to be written to the same location the data memory <NUM> (the location identified by the address signal, MEM ADDR). The write data signal, WR DATA is generated before employment of any error-correcting codes to correct errors of data that may be previously stored in the data memory <NUM>. The write data signal, WR DATA is provided to XOR data logic <NUM> of a write control <NUM> and to an ECC generator <NUM>. Further, the read-modify-write logic <NUM> de-asserts the stall signal, STALL_N.

Also, in the second clock cycle, in response to the write data signal, WR DATA, the ECC generator <NUM> generates an error-correcting code that is provided to the XOR ECC logic <NUM> (XOR gate logic). Also, during the second clock cycle, in a parallel operation, in response to the read data signal, RD DATA, the ECC generator <NUM> of the ECC check and repair <NUM> generates a re-computed error-correcting code ("ECC2" in <FIG>) for data included in the read data signal, RD DATA. The re-computed error-correcting code, ECC2 is provided to the ECC compare <NUM>. The ECC compare <NUM> compares the error-correcting code, ECC1 provided from the code memory <NUM> with the re-computed error-correcting code, ECC2 and generates a syndrome signal ("SYNDROME" in <FIG>) that identifies errors in the data included in the read data signal, RD DATA. For example, the syndrome signal SYNDROME identifies bits in the read data signal, RD DATA that are corrupted. In at least one example, if no bits in the data included in the read data signal, RD DATA and/or the error-correcting code, ECC1 have changed since the error-correcting code ECC1 was generated (at the time of storage at the data memory <NUM>), the syndrome signal, SYNDROME has a value of logical '<NUM>'. In that example, if one or more bits in the data included in the read data signal, RD DATA have changed since the error-correcting code ECC1 was generated, the syndrome signal, SYNDROME is set to a value that identifies particular bits that have been corrupted in the data from the read data signal, RD DATA.

The syndrome signal, SYNDROME is provided to a data repair lookup table (LUT) <NUM> and to an ECC repair LUT <NUM>. The data repair LUT <NUM> converts the syndrome signal into a data repair pattern signal ("DATA REPAIR PATTERN" in <FIG>) that is provided to the XOR data logic <NUM> of the write control <NUM>. The data repair pattern signal, DATA REPAIR PATTERN, contains data that is employable to restore/correct the data in the read data signal, RD DATA to the same value that the data in the data read signal, RD DATA to the correct value. Similarly, the ECC repair LUT <NUM> converts the syndrome signal, SYNDROME into an ECC repair pattern signal ("ECC REPAIR PATTERN" in <FIG>) that is employable to restore/correct the error-correcting code, ECC1.

The XOR data logic <NUM> executes an XOR function on the data repair pattern signal, DATA REPAIR PATTERN and the write data signal, WR DATA to generate a repaired data value that is written in the memory address of the data memory <NUM> identified in the address signal, MEM ADDR. For example, the XOR data logic <NUM> flips ("XOR's") corrupted data bits (identified by the syndrome signal, SYNDROME) before writing the corrected data to the data memory <NUM>. The XOR ECC logic <NUM> executes an XOR function on the ECC repair pattern signal, ECC REPAIR PATTERN and the new error-correcting code to generate the repaired data value that is written to the code memory <NUM> at the error code address. For example, the XOR ECC logic <NUM> flips error-correcting code bits that are impacted by the corrupted data to generate the repaired error-correcting code that is written to the code memory <NUM>. Also, the read-modify write logic de-asserts the conditioned memory enable signal, MEM EZ and the conditioned memory write signal MEM WZ signal (e.g., logical '<NUM>').

<FIG> illustrates a timing diagram <NUM> of example waveforms employed by the memory controller <NUM>. In the timing diagram <NUM>, the clock signal, CLK, the address signal ADDR and the data signal DATA are included in the partial write data signal PARTIAL WR DATA of <FIG>, or are provided as separate signals (not shown). The timing diagram <NUM> illustrates a partial write of D0 to memory address A0.

As illustrated in the timing diagram <NUM>, memory, Q0 is read from the data memory <NUM> and combined with D0 to form memory M0. The memory M0 is written to the data memory <NUM> in the address A0.

Referring again to <FIG>, by employing the portion of the memory controller <NUM>, the data read from the data memory <NUM> (RD DATA) is directly used to combine with the data in the partial write data request, PARTIAL WR DATA. Accordingly, the error-correcting code generation executed by the ECC generator <NUM> (in the write path) operates in parallel with the error-correcting code re-generation executed by the ECC generator <NUM> of the ECC check and repair <NUM>. Therefore, a timing path for a read-modify-write operation avoids the need to serially (e.g., back-to-back) generate error-correcting codes.

As an example, the critical path for the read-modify-write operation executed by the memory controller <NUM> is defined by Equation <NUM>. <MAT> wherein:.

In some examples, the critical path, CP has a delay of about <NUM>% (or greater) less than the critical path of a system that employs serially generated error-correcting codes. Accordingly, the memory controller <NUM> is employable in systems that have a high frequency clock signal, without the need for additional control logic.

<FIG> illustrates another example of a block diagram of a portion of a memory controller <NUM> for executing a partial write to ECC memory <NUM> with a read-modify-write operation. In at least one example, the memory controller <NUM> is employed to implement a pipelined-parallel operation. In at least one example, the memory controller <NUM> may be employed to implement the memory controller <NUM> illustrated in <FIG>. The ECC memory <NUM> is a non-transitory machine readable medium (e.g., random access memory) that may be employed in situations where highly accurate data (e.g., non-corrupted) is needed, such as safety applications (e.g., automotive), financial applications or the like. The ECC memory <NUM> includes a data memory <NUM> and a code memory <NUM>.

The read-modify-write logic <NUM> receives an active low memory enable signal ("EZ" in <FIG>) and an active low write enable signal ("WZ" in <FIG>) concurrently with the partial write data request, PARTIAL WR DATA. In response to the write enable signal WZ and memory enable signal EZ being asserted (e.g., logical '<NUM>'), in a first clock cycle (from a main/master memory controller, not shown), the read-modify-write logic <NUM> asserts an active-low stall signal, STALL_N (e.g., logical '<NUM>'), which prevents subsequent memory operations on the ECC memory <NUM>. Also, the read-modify-write logic <NUM> forwards an address signal, MEM ADDR (included as ADDR in the partial write data signal, PARTIAL WR DATA) to the ECC memory <NUM>. The read-modify-write logic <NUM> also forwards an asserted active-low conditioned memory enable signal, MEM EZ (e.g., logical '<NUM>') and a de-asserted conditioned memory write signal, MEM WZ (e.g., logical '<NUM>'). In response, the data memory <NUM> provides a read data signal ("RD DATA" in <FIG>. ) to the read-modify-write logic <NUM> and to a delay <NUM> (e.g., flip-flops), thereby registering/pipelining the data in the read data signal, RD DATA. The read data signal, RD DATA includes the data stored at the memory location identified in the address signal (e.g., a data word). After a predetermined delay (e.g., about one (<NUM>) clock cycle), the delay <NUM> passes the read data signal, RD DATA to an ECC generator <NUM> of an ECC check and repair <NUM>. The delay <NUM> also passes the read data signal, RD DATA to XOR data logic <NUM> (e.g., XOR gates) of a write control <NUM>.

In further response to the address signal, MEM ADDR, the code memory <NUM> of the ECC memory <NUM> provides an error-correcting code signal ("ECC in <FIG>") to a delay <NUM>, thereby registering the error-correcting code signal, ECC. The error-correcting code signal, ECC includes an error code stored at an address in the code memory <NUM> that corresponds to the address identified by the address signal, MEM ADDR, which address can be referred to as the error code address. After a predetermined delay, such as about one clock cycle, the delay <NUM> passes the error-correcting code signal, ECC to an ECC compare <NUM> of the ECC check and repair <NUM>. The delay <NUM> and the delay <NUM> are illustrated as being a functional block of the ECC check and repair <NUM>. But in other examples, the delay <NUM> and/or the delay <NUM> could be implemented external to the ECC check and repair <NUM>.

In the second clock cycle (from the main memory controller), in response to the read data signal, RD DATA, the read-modify-write logic <NUM> modifies the data in RD DATA by combining the data in RD DATA with data in the partial write data request, PARTIAL WR DATA to generate combined data. The read-modify-write logic <NUM> generates a write data signal ("WR DATA" in <FIG>) and asserts the conditioned memory write signal, MEM EZ (e.g., logical '<NUM>'). The write data signal, WR DATA contains the combined data that is to be written to the same location in the data memory <NUM> (the location identified by the address signal, MEM ADDR). The write data signal, WR DATA is generated before employment of any error-correcting codes to correct errors of data that may be previously stored in the data memory <NUM>. The write data signal, WR DATA is provided to an input node of a data multiplexer (MUX) <NUM> of the write control <NUM> and to an ECC generator <NUM>.

The ECC generator <NUM> generates a new error-correcting code for the combined data in the write data signal, WR DATA and passes the new error-correcting code to an input of an ECC MUX <NUM> and to a delay <NUM>. After a predetermined amount of time (e.g., one clock cycle), the delay <NUM> passes the new error-correcting code to XOR logic <NUM> of the write control <NUM>. Further, the read-modify-write logic <NUM> de-asserts (e.g., logical '<NUM>') the stall signal, STALL_N. Also, in some examples, the read-modify-write logic <NUM> also de-asserts (e.g., logical '<NUM>') the conditioned memory write signal, MEM WZ.

The XOR data logic <NUM> provides a signal to another input of the data MUX <NUM>. Also, the XOR ECC logic <NUM> provides a signal to another input of the ECC MUX <NUM>. Moreover, the ECC compare <NUM> provides an ECC single bit error ("ECC SBE" in <FIG>) to a control/selection node of the data MUX <NUM> and the ECC MUX <NUM>. During the second clock cycle, the ECC single bit error signal, ECC SBE is de-asserted (e.g., logical '<NUM>') causing the data MUX <NUM> and the ECC MUX <NUM> to select the input node assigned to the write data signal, WR DATA. In response to the single bit error signal, ECC SBE, the data mux <NUM> writes the combined data in the write data signal, WR DATA to the address in the data memory <NUM> identified in the address signal, MEM ADDR. Also, the ECC MUX <NUM> writes the new error-correcting code to the corresponding error address in the code memory <NUM>. In this manner, the combined data is registered with the ECC memory <NUM>.

Further, in a third clock cycle, after writing the combined data to the data memory <NUM> and the new error-correcting code to the code memory <NUM>, the registered/pipelined read data, RD DATA is output from the delay <NUM> to the ECC generator <NUM>. Similarly, the error-correcting code, ECC1 at the delay <NUM> outputs the registered/pipelined error-correcting code, ECC1 to the ECC compare <NUM>. The ECC generator <NUM> of the ECC check and repair <NUM> generates a re-computed error-correcting code ("ECC2" in <FIG>) for data included in the read data signal, RD DATA. The re-computed error-correcting code, ECC2 is provided to the ECC compare <NUM>. The ECC compare <NUM> compares the error-correcting code, ECC1 provided from the delay <NUM> with the re-computed error-correcting code, ECC2 and generates a syndrome signal ("SYNDROME" in <FIG>) that identifies errors in the data included in the read data signal, RD DATA. In at least one example, if no bits in the data included in the read data signal, RD DATA and/or the error-correcting code, ECC1 have changed since the error-correcting code ECC1 was generated (at the time of storage at the data memory <NUM>), the syndrome signal, SYNDROME has a value of logical '<NUM>'. In that example, if one or more bits in the data included in the read data signal, RD DATA have changed (e.g., through corruption) since the error-correcting code ECC1 was generated, the syndrome signal, SYNDROME is set to a value that identifies particular bits that have been corrupted in the data from the read data signal, RD DATA and/or the error-correcting code, ECC1.

The ECC compare <NUM> sets the ECC single bit error signal, ECC SBE based on the value of the syndrome signal. For example, if the syndrome signal, SYNDROME has a value indicating that no errors are in the data in the read data signal, RD DATA and/or the error-correcting code, ECC1, the ECC compare <NUM> maintains the single bit error signal, ECC SBE at the initial state (e.g., logical '<NUM>'). Conversely, if the syndrome signal, SYNDROME has a value indicating that no errors are in the data in the read data signal, RD DATA and/or the error-correcting code, ECC1, the ECC compare <NUM> sets the single bit error signal, ECC SBE to an error state (e.g., logical '<NUM>'). As described herein, the ECC single bit error signal ECC SBE is provided to the read-modify-write logic <NUM>, the data MUX <NUM> and the ECC MUX <NUM>.

The syndrome signal, SYNDROME is provided to a data repair LUT <NUM> and to an ECC repair LUT <NUM>. The data repair LUT <NUM> converts the syndrome signal into a data repair pattern signal ("DATA REPAIR PATTERN" in <FIG>) that is provided to the XOR data logic <NUM> of the write control <NUM>. The data repair pattern signal, DATA REPAIR PATTERN, contains data that is employable to correct corrupted data in the read data signal, RD DATA. Similarly, the ECC repair LUT <NUM> converts the syndrome signal, SYNDROME into an ECC repair pattern signal ("ECC REPAIR PATTERN" in <FIG>) that is employable to restores the error-correcting code, ECC1.

The XOR data logic <NUM> executes an XOR function on the data repair pattern signal, DATA REPAIR PATTERN, and the data from the read data signal, RD DATA, provided from the delay <NUM> to generate a repaired data value that is input to the other input of the data MUX <NUM>. For example, the XOR data logic <NUM> flips ("XOR's") corrupted data bits (identified by the syndrome signal, SYNDROME), which are provided to the other input of the data MUX <NUM>. The XOR ECC logic <NUM> executes an XOR function on the ECC repair pattern signal, ECC REPAIR PATTERN, and the new error-correcting code provided from the delay <NUM> to generate a repaired error-correcting code that is provided to the other input of the ECC MUX <NUM>. For example, the XOR ECC logic <NUM> flips error-correcting code bits that are impacted by the corrupted data to generate the repaired error-correcting code that is provided to the other input of the ECC MUX <NUM>.

During the third clock cycle, in response to receipt of the single bit error signal, ECC SBE in the error state (e.g., logical '<NUM>'), the read-modify-write logic <NUM> asserts the stall signal, STALL_N and the conditioned write signal, MEM WZ (e.g., logical '<NUM>'). Also, in response to receipt of the single bit error signal, ECC SBE in the error state (e.g., logical '<NUM>'), the data MUX <NUM> selects the other input from the XOR data logic <NUM> and the ECC MUX <NUM> selects the other input from the XOR ECC logic <NUM>. Moreover, the value provided to the data MUX <NUM> from the XOR data logic <NUM> (repaired data) is written to the data memory <NUM> at the address identified in the address signal, MEM ADDR. Similarly, the value provided to the ECC MUX <NUM> from the XOR ECC logic <NUM> (repaired error-correcting code) is written to the corresponding error address in the code memory <NUM>. The read-modify-write logic <NUM> de-asserts the stall signal, STALL_N (e.g., logical '<NUM>'). Also, in some examples, the read-modify-write logic <NUM> de-asserts (e.g., logical '<NUM>') the conditioned memory enable signal, MEM EZ and the conditioned write signal, WZ.

<FIG> illustrates a timing diagram <NUM> of example waveforms employed by the memory controller <NUM>. In the timing diagram <NUM>, the clock signal, CLK, the address signal, MEM ADDR and the data signal, DATA are included in the partial write data signal, WR DATA of <FIG> or may be provided separately (not shown). The timing diagram <NUM> illustrates a partial write of D0 to memory address A0, and a partial write of D1 to memory address A1.

In the timing diagram <NUM>, the read data signal, RD DATA provides data, Q0, which is combined with data in the data signal, D0 to form combined data, M0 that is written to the data memory <NUM>. However, it is presumed that an error is in the data, Q0, which is indicated by a rising edge (indicating the error state) on the ECC single bit error signal, ECC SBE. Thus, the stall signal, STALL_N is asserted, and the data is corrected to form data M0' that is re-written to the data memory <NUM>, which causes the ECC signal bit error signal, ECC SBE to return to the initial state. This allows the second partial write of D1 to memory address A1 to commence. The second partial write combines data Q1 with the data D1 to form combined data M1 that is written to the memory address A1.

Referring again to <FIG>, by employing the portion of the memory controller <NUM>, the data read from the data memory <NUM> (RD DATA) is directly used to combine with the data in the partial write data request, PARTIAL WR DATA. Moreover, when an error occurs, a third clock cycle is employed to correct the error. However, in many applications, errors are extremely rare, often occurring at less than <NUM>% of the time. Thus, by writing data to the ECC memory <NUM> before completion of an error check and repair is completed, significant time savings can be achieved. Accordingly, the memory controller <NUM> provides time savings by operating under the assumption that the great majority of the time (e.g., about <NUM>% or more), no correction of data and/or an error-correcting code is needed.

In view of the foregoing structural and functional features described hereinabove, an example method is described with reference to <FIG>. For simplicity of explanation, the example method of <FIG> is shown and described as executing serially, but (unless otherwise noted) these examples are not limited by the illustrated order, as some actions could in other examples occur in different orders, multiple times and/or concurrently from that shown and described herein. Moreover, some described actions are optional to implement a method.

<FIG> illustrates a flowchart of an example method <NUM> for executing a partial write to ECC memory. For example, the method <NUM> could be executed by a memory controller, such as the memory controller <NUM> of <FIG> and/or the memory controller <NUM> of <FIG>. At <NUM>, a read-modify-write logic (e.g., the read-modify-write logic <NUM>) receives a partial write data request for data stored in data memory (e.g., the data memory <NUM>) of the ECC memory (e.g., the ECC memory <NUM>). At <NUM>, data read from the data memory is combined with data in the partial write data request at the memory read-modify-write logic to form combined data. At <NUM>, data repair pattern and ECC repair pattern signals are generated by an ECC check and repair (e.g., the ECC check and repair <NUM>) based on a checking of the accuracy of the read data and a corresponding error-correcting code. The read-modify-write logic executes the combining in parallel with the checking executed by the ECC check and repair.

At <NUM>, an error-correcting code for the combined data is generated by an ECC generator (e.g., the ECC generator <NUM>). At <NUM>, an XOR function is executed on the data repair pattern signal and the combined data and an XOR function is executed on the ECC repair pattern signal and the error code for the combined data by a write control to generate repaired data and repaired error-correcting code. At <NUM>, the repaired data and the repaired error-correcting code are written to the ECC memory.

<FIG> illustrates a flowchart of another example method <NUM> for executing a partial write to ECC memory. For example, the method <NUM> could be executed by a memory controller, such as the memory controller <NUM> of <FIG> and/or the memory controller <NUM> of <FIG>. At <NUM>, a read-modify-write logic (e.g., the read-modify-write logic <NUM>) receives a partial write data request for data stored in data memory (e.g., the data memory <NUM>) of the ECC memory (e.g., the ECC memory <NUM>). At <NUM>, data read from the data memory is combined with data in the partial write data request at the memory read-modify-write logic to form combined data. At <NUM>, an error-correcting code for the combined data is generated by an ECC generator (e.g., the ECC generator <NUM>). At <NUM>, an ECC check and repair (e.g., the ECC check and repair <NUM>) checks the accuracy of the read data and an error-correcting code.

At <NUM>, data and ECC repair pattern signals are generated by the ECC check and repair based on a checking of the accuracy of the read data and a corresponding error-correcting code. At <NUM>, write control can write the combined data and the repaired error-correcting code to the ECC memory. At <NUM>, a determination can be made by the ECC check and repair as to whether an error is detected. If the determination at <NUM> is negative (e.g., NO), the method <NUM> can returns to <NUM> (to process a next partial data write request). If the determination at <NUM> is positive (e.g., YES), the method <NUM> can proceed to <NUM>. Also, at <NUM>, an ECC single bit error signal can be output indicating the determination at <NUM>.

At <NUM>, the read-modify-write logic can assert a stall signal for one clock cycle, thereby preventing receipt and execution of subsequent partial write data requests. At <NUM>, the write control can apply XOR functions to generate repaired data and ECC repaired data. At <NUM>, the write control writes the repaired data and the ECC repaired data to the ECC memory. The method <NUM> returns to <NUM> to process the next partial write data request.

Claim 1:
A memory controller comprising:
a read-modify-write logic module (<NUM>) that receives a partial write data request for partial write data in error-correcting code ECC memory (<NUM>) and combines the partial write data in the partial write data request with read data provided from the ECC memory (<NUM>) to form combined data before correcting the read data; and
a write control module (<NUM>) that controls the writing of the combined data to the ECC memory (<NUM>).