Patent Description:
In a conventional packaged integrated circuit (IC) component which is packaged by a ball grid array package process, a solder ball array is formed at the bottom of the package substrate. The solder ball array includes a plurality of solder balls as external contacts so that a chip of the conventional packaged IC component can be electrically connected to a printed circuit board for signal transmission between the chip and the printed circuit board.

Currently, in the designs of the printed circuit board and the ball grid array, ground balls are electrically connected to a ground plane of the printed circuit board respectively through ground vias, and power balls are electrically connected to a power plane of the printed circuit board respectively through power vias. In order to reduce the voltage drop (or IR drop) resulting from the parasitic resistance of the printed circuit board, the numbers of the ground balls and the power balls would be increased as much as possible so as to increase the current paths. Accordingly, the numbers of the ground vias and the power vias are increased with the increasing numbers of the ground balls and the power balls, such that the arrangements of the ground vias and the power vias become denser. In addition, the conventional ground and power balls are respectively arranged in different regions to simplify the fabrication of wiring layers of the printed circuit board.

Furthermore, in order to further minimize the size of the packaged IC component, a pitch between any two adjacent solder balls has to be further shortened; for example, the pitch may be shortened from <NUM> to <NUM>. However, the space for arranging the ground vias and the power vias would be further reduced so as to be in cooperation with the smaller pitches.

Accordingly, respective apertures of the ground and power vias has to be further reduced without decreasing respective quantities of the ground and power vias.

Although the ground vias and the power vias with smaller aperture can be fabricated by laser drilling, the fabrication cost is higher. Another solution is decreasing the respective quantities of the solder balls, ground vias, and power vias so as to minimize the size of the packaged IC component. However, decreasing the quantities of the solder balls, ground vias, and power vias may result in an increase in impedance.

<CIT>, <CIT>, <CIT> as well as <CIT> relate to different versions of printed circuit boards having power pads and ground pads which are arranged to correspond to the power boards and ground boards of the respective integrated circuit.

In response to the above-referenced technical inadequacies, the present disclosure provides a control device and an electronic apparatus comprising a circuit board, in which the size of the control device can be reduced without significantly increasing the impedance and higher fabrication cost.

In one aspect, the present inventions relates to a control device comprising the features of claim <NUM>.

In one aspect, the present disclosure provides an electronic apparatus according to claim <NUM> including a circuit board and the inventive control device. The control device includes a ball grid array disposed at a bottom thereof. The circuit board includes a laminated board and a pad array disposed on the laminated board. The control device is assembled on the circuit board through the ball grid array and the pad array. The ball grid array includes a plurality of ground balls and a plurality of power balls, which are jointly arranged in a ball region. The power balls are divided into a plurality of power ball groups, and the ground balls are divided into a plurality of ground ball groups. At least one of the ground ball groups includes two of the ground balls and is adjacent to at least one of the power ball groups. A ball pitch between the two ground balls of the at least one of the ground ball groups is greater than that between one of the power balls and one of the ground balls that are adjacent to each other. The laminated board has a first surface and a second surface opposite to the first surface. The laminated board includes a ground layer and a power layer which is insulated from the ground layer. The pad array is disposed on the first surface and corresponds to the ball grid array. The pad array includes a plurality of power pads which are electrically connected to the power layer, and a plurality of ground pads which are electrically connected to the ground layer. The power pads and the ground pads are jointly arranged in a first predetermined region of the first surface. The power pads are divided into a plurality of power pad groups, and the ground pads are divided into a plurality of ground pad groups. At least one of the ground pad groups includes two ground pads and is adjacent to one of the power pad groups, and a pad pitch between the two ground pads of the at least one of the ground pad groups is greater than a pad pitch between one of the power pad and one of the ground pad that are adjacent to each other.

Therefore, one of the advantages of the present disclosure is that in the control device and the electronic apparatus provided in the present disclosure, by the technical features of "a ball pitch between the two ground balls of the at least one of the ground ball groups is greater than the ball pitch between the power ball and the ground ball which are adjacent to each other" or "the ground balls and the power balls are alternately arranged to form a first column, a second column, and a third column, all of which extend in a first direction, and a first column pitch between the first and second columns is greater than a second column pitch between the second and third columns," the size of the control device can be further reduced without overly reducing the space for disposing the ground conductive vias and the power conductive vias in the circuit board.

These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions.

The present disclosure will become more fully understood from the following detailed description and accompanying drawings.

Reference is made to <FIG>, which is a partial view of the bottom of a control device according to an embodiment of the present disclosure. The control device <NUM> can be assembled on a circuit board to form an electronic apparatus. Furthermore, the control device <NUM> can operate with the circuit board.

The control device <NUM> can be a central processing unit (CPU) or a graphic processing unit (GPU), which can be a package structure of a system on chip (SoC). Furthermore, the control device <NUM> can operate at a high frequency.

The control device <NUM> includes a ball grid array <NUM> disposed at a bottom thereof, and the ball grid array <NUM> includes a plurality of power balls P1 and a plurality of ground balls G1. It should be noted that in the embodiment of the present disclosure, the ball pitches between the balls (including the power balls P1 and the ground balls G1) are modified so that the size of the control device <NUM> can be further reduced.

It should be noted that, <FIG> is a schematic view of the ball grid array <NUM> with portions thereof being omitted in order to more clearly illustrate the concept of the present disclosure, rather than a view showing the ball grid array being used in practical application. In practice, the ball grid array <NUM> further includes signal balls, but the signal balls are not illustrated in <FIG> for convenience of explanation.

As shown in <FIG>, the ground balls G1 and the power balls P1 of the ball grid array <NUM> are arranged in the same ball region 10R. The power balls P1 are divided into a plurality of power ball groups <NUM>, and the ground balls G1 are divided into a plurality of ground ball groups <NUM>.

Specifically, at least one of the ground ball groups <NUM> includes two ground balls G1 and is adjacent to one of the power ball groups <NUM>. Furthermore, one of the power ball groups <NUM> includes two power balls P1. As shown in <FIG>, in the instant embodiment, one of the power ball groups <NUM>' can include only one power ball P1.

Reference is made to <FIG>. In the instant embodiment, the power ball groups <NUM> and the ground ball groups <NUM> are arranged to form a column in an alternating manner. Specifically, one of the ground ball groups <NUM> is arranged between every two of the power ball groups <NUM>. In one embodiment, the two power balls P1 of the power ball groups <NUM> and the two ground balls G1 are in alignment with one another along the first direction D1.

Furthermore, the power ball groups <NUM> and the ground ball groups <NUM> are arranged in a second direction D2 in an alternating manner. To be more specific, the two power balls P1 in one of the power ball groups <NUM> and the two ground balls G1 in the adjacent one of the ground ball groups <NUM> are in alignment with one another in the second direction D2.

It should be noted that in one of the ground ball groups <NUM>, a ball pitch d1 between the two ground balls G1 is greater than a ball pitch d2 between the power ball P1 and the ground ball G1 that are adjacent to each other. Similarly, in one of the power ball groups <NUM>, a ball pitch between the two power balls P1 is greater than the ball pitch d2 between the power ball P1 and the ground ball G1 that are adjacent to each other.

In the instant embodiment, the ball pitch between the two power balls P1 is the same as the ball pitch d1 between the two ground balls G1. Furthermore, the term of "ball pitch" or "pitch between two adjacent balls" means a linear distance between two respective geometric centers of two adjacent balls.

As a whole, in the embodiment shown in <FIG>, the ground balls G1 and the power balls P1 are alternately arranged in a plurality of columns in the first direction D1. The first column pitch (which is equal to the ball pitch d1) between a first column and a second column is greater than a second column pitch (which is equal to the ball pitch d2) between the second column and a third column.

Furthermore, the power balls P1 and the ground balls G1 are arranged in a plurality of rows in a second direction D2. A row pitch between any two adjacent rows is less than the first column pitch. In the instant embodiment, the row pitch between any two adjacent rows is substantially the same as the ball pitch d2.

In one embodiment, the ball pitch d1 between the two ground balls G1 of the ground ball group <NUM> or between the two power balls P1 of the power ball group <NUM> ranges from <NUM> to <NUM>. Furthermore, the ball pitch d2 between the power ball P1 and the ground ball G1 which are adjacent to each other ranges from <NUM> to <NUM>.

That is to say, rather than reducing all of the ball pitches, in the present disclosure, a portion of the ball pitches (such as the ball pitch d1) in one of the directions (the second direction D2) are relatively increased and another portion of the ball pitches (such as the ball pitch d2) are relatively reduced so that the size of the control device <NUM> can be reduced.

Furthermore, since the ball pitch d1 between the two ground balls G1 in any ground ball group <NUM> is greater, a first corresponding region 100R is defined between the two ground balls G1 so that a position of the ground conductive via on the circuit board <NUM> can be further defined. Similarly, a second corresponding region 101R can be defined between the two adjacent power balls P1 in any power ball group <NUM>, so that a position of the power conductive via on the circuit board <NUM> can be defined.

In the instant embodiment, an imaginary connection line connecting two centers of the two ground balls G1 extends across the first corresponding region 100R, and an imaginary connection line that is connected between the two centers of the two power balls P1 extends across the first corresponding region 101R. Furthermore, in the instant embodiment, when the power ball group <NUM>' includes only one power ball P1, the second corresponding region 101R is adjacent to the power ball P1 and located at a side of the power ball P1 which is farther away from the ground ball group <NUM>.

Accordingly, by reducing a portion of the ball pitches, the size of the control device <NUM> can be minimized without excessively reducing the space for arranging the ground conductive vias or power conductive vias, thereby preventing the overall impedance from being lowered. It should be noted that as long as the power ball P1 and the ground ball G1 are not short-circuited when the control device <NUM> is disposed on the circuit board <NUM>, the ball pitch d2 between the power ball P1 and the ground ball G1, which are adjacent to each other, is allowed to be further reduced. Accordingly, the present disclosure is not limited to the embodiment shown in <FIG>.

Reference is made to <FIG> and <FIG>. <FIG> is a partial top view of a circuit board according to an embodiment of the present disclosure. <FIG> is a partial cross-sectional view taken along line III-III of <FIG>. The circuit board <NUM> includes a laminated board <NUM> and a pad array <NUM> disposed on the laminated board <NUM>.

As shown in <FIG>, the laminated board <NUM> has a first surface 20a and a second surface 20b opposite to the first surface 20a. Furthermore, the laminated board <NUM> includes a ground layer <NUM> and a power layer <NUM>.

It should be noted that in the present disclosure, in all of the cross-sectional views of the circuit board <NUM>, only the ground layer <NUM> and the power layer <NUM> are illustrated, and the other layers of the laminated board <NUM> are omitted. In practice, the laminated board <NUM> is formed by stacking a plurality of insulating layers and a plurality of conductive layers, one of the conductive layers can serve as the ground layer <NUM>, and another one of the conductive layers can serve as the power layer <NUM>. The ground layer <NUM> and the power layer <NUM> can be insulated from each other by an insulating layer disposed therebetween.

As shown in <FIG>, the pad array <NUM> is disposed on the laminated board <NUM>. In the instant embodiment, the control device <NUM> can be assembled on the first surface 20a of the laminated board <NUM>. Accordingly, the pad array <NUM> is located at the first surface 20a of the laminated board <NUM>.

The pad array <NUM> includes a plurality of power pads P2 and a plurality of ground pads G2. The power pads P2 can respectively correspond to the power balls P1 of the ball grid array <NUM> shown in <FIG>, and the ground pads G2 can respectively correspond to the ground balls G1 shown in <FIG>.

In the instant embodiment, the ground pads G2 and the power pads P2 are jointly arranged in a first predetermined region 200R of the first surface 20a. Similar to the ball grid array <NUM> of the control device <NUM> shown in <FIG>, the pad array <NUM> includes a plurality of power pads P2 which are electrically connected to the power layer <NUM>, and a plurality of ground pads G2 which are electrically connected to the ground layer <NUM>.

To be more specific, in the instant embodiment, the power pads P2 and the ground pads G2 are jointly arranged in a plurality of columns in the first direction D1. The power pads P2 and the ground pads G2 in each column are arranged in an alternating manner. Furthermore, in the pad array <NUM>, the power pads P2 can be divided into a plurality of power pad groups <NUM>, and the ground pads G2 can be divided into a plurality of ground pad groups <NUM>.

Reference is made to <FIG> in conjunction with <FIG>. At least one ground pad group <NUM> includes two ground pads G2 and is adjacent to one of the power pad groups <NUM>, and a pad pitch d1' between the two ground pads G2 of the at least one ground pad group <NUM> is greater than a pad pitch d2' between the power pad P2 and the ground pad G2 which are adjacent to each other.

In order to correspond to the ball grid array <NUM>, at least one power pad group <NUM> includes two power pads P2, and a pad pitch d1' between the two power pads P2 is greater than a pad pitch d2' between any one of the power pads P2 and the ground pad G2 adjacent thereto.

As shown in <FIG>, the power pad groups <NUM> and the ground pad groups <NUM> are arranged in the first direction in an alternating manner. That is to say, in the first direction D1, one of the ground pad groups <NUM> is disposed between every two of the power pad groups <NUM>. Furthermore, the power pad groups <NUM> and the ground pad groups <NUM> are also arranged in alternating manner in the second direction D2.

As shown in <FIG>, the circuit board <NUM> of the embodiment in the present disclosure further includes a conductive via array. The conductive via array includes a plurality of ground conductive vias C21 and a plurality of power conductive vias C22. Each of the ground conductive vias C21 and the power conductive vias C22 passes through the laminated board <NUM>. Each of the power pads P2 is electrically connected to the corresponding power conductive via C22, and each of the ground pads G2 is electrically connected to the corresponding ground conductive via C21.

Specifically, the pad pitch d1' between the two ground pads G2 of the at least one ground pad group <NUM> is wider so that a space for arranging one of the ground conductive vias C21 can be defined between the two ground pads G2. Accordingly, each of the ground conductive vias C21 can be disposed between the two ground pads G2 of the corresponding ground pad group <NUM>. Similarly, each of the power conductive vias C22 can be disposed between the two power pads P2 of the corresponding power pad group <NUM>.

In one embodiment, the pad pitch d1' between the two ground pads G2 of each ground pad group <NUM> (or between the two power pads P2 of each power pad group <NUM>) ranges from <NUM> to <NUM>. Moreover, the pad pitch d2' between the power pad P2 and the ground pad G2, which are adjacent to each other, ranges from <NUM> to <NUM>.

It should be noted that since the pad pitch d2' between the power pad P2 and the adjacent ground pad G2 is narrower, no conductive via is disposed between the power pad P2 and the adjacent ground pad G2. Accordingly, the pad pitch d2' between the power pad P2 and the adjacent ground pad G2 can be reduced to less than <NUM>.

On the other hand, since the power pad groups <NUM> and the ground pad groups <NUM> are arranged in an alternating manner, the power conductive vias C22 and the ground conductive vias C21 are also arranged in alternating manner in the laminated board <NUM>.

Accordingly, the power conductive vias C22 and the ground conductive vias C21 are alternately arranged so as to be in conjunction with the positions of the power pad groups <NUM> and the ground pad groups <NUM>. Specifically, in the conductive via array, the power conductive vias C22 and the ground conductive vias C21 are alternately arranged in a plurality of columns in the first direction D1 and a plurality of rows in the second direction D2.

It should be noted that a transient current and a parasitic inductance that are generated during the operation of the control device <NUM> would result in simultaneous switching noise (SSN) in the circuit, thereby decreasing the supply voltage of the control device <NUM>.

Furthermore, during the operation of the control device <NUM>, the control device <NUM> may be switched from a low-power state to a high-power state within a few nanoseconds, which results in an increase of a current applied to the control device <NUM> within a very short period of time. The significant increase of the transient current variation magnifies the negative effects caused by the parasitic inductance. Accordingly, voltage drop of the power voltage may increase with the significant increase of the transient current variation and the existence of the parasitic inductance. As such, the power integrity would be reduced, thereby decreasing the operating stability of an electronic apparatus during the operation thereof.

In the present disclosure, the ground conductive vias C21 and the power conductive vias C22 are arranged in an alternating manner, such that an area defined by a current loop that is formed by the power pad P2, the power conductive via C22, the ground pad G2, and the ground conductive via C21 can be reduced, thereby decreasing parasitic inductance.

Since the parasitic inductance is decreased, a voltage drop that results from the parasitic inductance and a variation of transient current can be further reduced, so that the power integrity can be improved.

Reference is made to <FIG>. The circuit board <NUM> further includes a wiring layer <NUM>. The wiring layer <NUM> includes a plurality of front-side ground traces <NUM> and a plurality of front-side power traces <NUM>.

The front-side ground traces <NUM> are disposed on the first surface 20a. Each of the front-side ground traces <NUM> is electrically connected to the corresponding ground pads G2 and the corresponding ground conductive vias C21. Specifically, in each of the ground pad groups <NUM>, the two ground pads G2 are electrically connected to the ground conductive via C21 located therebetween by the corresponding one of the front-side ground traces <NUM>.

Similarly, the front-side power traces <NUM> are disposed on the first surface 20a. Each of the front-side power traces <NUM> is electrically connected to the corresponding power pad P2 and the corresponding power conductive via C22. In each of the power pad groups <NUM>, the two power pads P2 are electrically connected to the power conductive via C22 located therebetween by the corresponding one of the front-side power traces <NUM>.

Reference is made to <FIG> and <FIG> is a partial view of the bottom of the circuit board of <FIG>. As shown in <FIG>, the circuit board <NUM> of the present embodiment further includes a plurality of contact pad groups <NUM>, and the contact pad groups <NUM> are disposed on the second surface 20b of the laminated board <NUM>.

In the instant embodiment, each of the contact pad groups <NUM> includes an anode contact pad 24a and a cathode contact pad 24b for being electrically connected to a passive element. The passive element is such as a multilayer ceramic capacitor (MLCC).

In the instant embodiment, in the first direction D1, the anode contact pad 24a and the cathode contact pad 24b are arranged between the two adjacent rows of the conductive via array in the first direction D1. For two adjacent contact pad groups <NUM>, the anode contact pad 24a in one of the contact pad groups <NUM> is adjacent to the cathode contact pad 24b in the other one of the contact pad groups <NUM>.

That is to say, for two adjacent contact pad groups <NUM>, the anode contact pad 24a and the cathode contact pad 24b in one of the contact pad groups <NUM> are respectively arranged at positions opposite to the positions of anode contact pad 24a and the cathode contact pad 24b in the other contact pad group <NUM>.

Moreover, as shown in <FIG>, the circuit board <NUM> further includes a bottom-side wiring layer (not assigned with a reference numeral) disposed on the second surface 20b so that the anode contact pad 24a is electrically connected to the corresponding one of the power conductive vias C22, and the cathode contact pad 24b is electrically connected to the corresponding one of the ground conductive vias C21.

Reference is made to <FIG>, the anode contact pad 24a and the cathode contact pad 24b in each of contact pad groups <NUM> are arranged at a corresponding region between the power pad group <NUM> and the ground pad group <NUM> which are adjacent to each other. That is to say, the anode contact pad 24a and the cathode contact pad 24b in each of contact pad groups <NUM> are arranged at a region that is not occupied by any of the ground conductive vias C21 and the power conductive vias C22. Accordingly, the number of the contact pad groups <NUM> can be adjusted according to the number of the passive element.

Furthermore, in the embodiment of the present disclosure, since the ground conductive vias C21 and the power conductive vias C22 are arranged in an alternating manner, the contact pad groups <NUM> can be scattered across the region on which neither the power conductive vias C22 nor the ground conductive vias C21 is disposed. When the passive elements are disposed on the circuit board <NUM>, the passive elements are also scattered and disposed among the conductive via array so as to be electrically connected to more numbers of the ground conductive vias C21 and the power conductive vias C22, thereby effectively reducing the impedance during the high-frequency operation of the control device <NUM>.

Accordingly, when the passive elements are disposed on the second surface 20b of the circuit board <NUM> respectively through the contact pad groups <NUM> corresponding thereto, the passive elements can be electrically connected in parallel to one another, thereby reducing the parasitic inductance.

Reference is made to <FIG> in conjunction with <FIG>, in which <FIG> is a partial top view of a ground layer according to an embodiment of the present disclosure.

As shown in <FIG>, the ground layer <NUM> has a plurality of first conductive holes 210a so that the ground layer <NUM> can be electrically connected to the ground conductive vias C21. In other words, each of the ground conductive vias C21 can be electrically connected to the ground layer <NUM> through the corresponding first conductive hole 210a.

Furthermore, the ground layer <NUM> further has a plurality of first insulating holes 210b so that the ground layer <NUM> can be insulated from the power conductive vias C22 passing through the laminated board <NUM>. The first insulating holes 210b are arranged at positions respectively corresponding to the positions of the power conductive vias C22. As such, each of the power conductive vias C22 can be insulated from the ground layer <NUM> by the corresponding one of the first insulating holes 210b.

As shown in <FIG>, a first pattern that is jointly formed by the first insulating holes 210b on the surface of the ground layer <NUM> is the same as a power pattern that is jointly formed by the power conductive vias C22 on the first surface 20a.

Similarly, reference is made to <FIG> in conjunction with <FIG>, in which <FIG> is a partial top view of a power layer according to an embodiment of the present disclosure.

As shown in <FIG> the ground conductive vias C21 pass through the laminated board <NUM>. Accordingly, in order to insulate the power layer <NUM> from the ground conductive vias C21 and electrically connect the power layer <NUM> to the power conductive vias C22, the power layer <NUM> further has a plurality of second insulating holes 220a and a plurality of second conductive holes 220b formed therein.

The second insulating holes 220a are arranged at the positions respectively corresponding to the positions of the ground conductive vias C21. That is to say, each of the ground conductive vias C21 can be insulated from the power layer <NUM> by the corresponding one of the second insulating holes 220a.

The second conductive holes 220b are arranged at positions respectively corresponding to the positions of the power conductive vias C22, so that each of the power conductive vias C22 can be electrically connected to the power layer <NUM> by the corresponding one of the second conductive holes 220b.

As shown in <FIG>, the second insulating holes 220a jointly form a second pattern on the surface of the power layer <NUM>, and the second pattern is the same as a ground pattern that is formed by the ground conductive vias C21 on the first surface 20a.

Reference is made to <FIG>, which is a partial sectional view of the control device assembled on the circuit board according to an embodiment of the present disclosure. When the control device <NUM> is assembled on the circuit board <NUM>, the power ball groups <NUM> of the control device <NUM> respectively correspond to the power pad groups <NUM> of the circuit board <NUM>. Furthermore, the ground ball groups <NUM> of the control device <NUM> respectively correspond to the ground pad groups <NUM> of the circuit board <NUM>, and respectively correspond to the ground conductive vias C21.

Specifically, the two ground balls G1 in each of the ground ball groups <NUM> are respectively in alignment with the two ground pads G2 in the corresponding one of the ground pad groups <NUM>. Furthermore, since the ball pitch d1 between the two adjacent ground balls G1 is relatively wider, the first corresponding region 100R defined between the two adjacent ground balls G1 is in alignment with one of the ground conductive vias C21.

Similarly, the two power balls P1 in each of the power ball groups <NUM> are respectively in alignment with the two power pads P2 in the corresponding one of the power pad groups <NUM>. Furthermore, the second corresponding region 101R defined between the two adjacent power balls P2 can correspond to one of the power conductive vias C22. On the other hand, since the ball pitch d2 between the ground ball G1 and the power ball P1 which are adjacent to each other is relatively narrower, the region located between the ground ball G1 and the power ball P1 which are adjacent to each other is not in alignment with any one conductive via.

In conclusion, one of the advantages of the present disclosure is that in the control device and the circuit board provided in the present disclosure, by the technical features of "a ball pitch d1 between the two ground balls G1 of the at least one of the ground ball groups <NUM> is greater than the ball pitch d2 between the power ball P1 and the ground ball G1 which are adjacent to each other" or "the ground balls G1 and the power balls P1 are alternately arranged to form a first column, a second column, and a third column, all of which extend in a first direction D1, and a first column pitch between the first and second columns is greater than a second column pitch between the second and third columns," the size of the control device <NUM> can be further reduced without overly reducing the space for disposing the ground conductive vias C21 and the power conductive vias C22 in the circuit board <NUM>.

As such, even though the size of the control device <NUM> is reduced, significant increases of the impedance and the fabrication cost can be avoided. That is to say, the size of the control device <NUM> can be reduced by arranging the ball grid array with different ball pitches, with the ball pitch d1 between any two adjacent ground balls G1 (or two adjacent power balls P1), and the ball pitch d2 between any ground ball G1 and the power ball P1 adjacent thereto. In one embodiment, the control device <NUM> in the present disclosure is about <NUM> times the size (<NUM><NUM>) of the conventional integrated circuit device package.

Furthermore, the arrangement of the pad array <NUM> of the circuit board <NUM> corresponds to the arrangement of the ball grid array <NUM> of the control device <NUM>, such that the power conductive vias C22 and the ground conductive vias C21 can be alternately arranged. As such, the parasitic inductance generated in the circuit board <NUM> can be reduced, thereby avoiding too large a voltage variation resulting from the significant increase of the transient current variation when the control device operates in high frequency.

Claim 1:
A control device (<NUM>) comprising a ball grid array (<NUM>) disposed at a bottom thereof, wherein the ball grid array (<NUM>) includes a plurality of ground balls (G1) and a plurality of power balls, which are jointly arranged in a ball region (10R), the power balls (P1) being divided into a plurality of power ball groups (<NUM>, <NUM>'), and the ground balls (G1) being divided into a plurality of ground ball groups (<NUM>);
wherein at least one of the ground ball groups (<NUM>) and at least one of the power ball groups (<NUM>, <NUM>') are adjacent to each other, and a ball pitch (d1) between the two adjacent ones of the ground balls (G1) of the at least one of the ground ball groups (<NUM>) is greater than a ball pitch (d2) between one of the power balls (P1) and one of the ground balls (G1) that are adjacent to each other,
characterized in that
the at least one of the ground ball groups (<NUM>) includes two adjacent ones of the ground balls (G1), the two adjacent ones of the ground balls (G1) of the at least one of the ground ball groups (<NUM>) and one of the power balls (P1) of the at least one of the power ball groups (<NUM>, <NUM>') are arranged in the same row,
wherein the ball pitch means a linear distance between two respective geometric centers of any two adjacent ones of the ground balls (G1) and the power balls (P1).