Patent Description:
There has conventionally been known a technique of removing interference waves from a beat signal. For example, Patent Document <NUM> (<CIT>) discloses a radar system as follows. That is, in the radar system, in each of a first signal processing path and a second signal processing path that are signal processing circuits parallel to each other, interference is removed from a copy of a beat signal, at least one window function is selected from multiple window functions having different frequency responses and is applied to the beat signal, and the beat signal is transformed from the time domain to the frequency domain. The radar system combines the output of the first signal processing path with the output of the second signal processing path and generates an output beat signal. Here, in each of the first signal processing path and the second signal processing path in the radar system, an interference removal method and a window function different from those of other parallel signal processing paths are applied.

In the technique described in Patent Document <NUM>, due to the removal of interference waves from the beat signal, a range side lobe in a power spectrum generated based on the beat signal may increase, and a target may not be able to be accurately detected. There is a desire for a technique that surpasses the technique described in Patent Document <NUM> and is capable of relatively accurately detecting a target based on a beat signal. <CIT>, <CIT>, and <CIT> likewise disclose use of windowing techniques in a similar context. Problems with the prior art techniques are solved by the subject-matter of the independent claims.

The purpose of the disclosure relates to a radar signal processing device, a radar device, a radar signal processing method, and a radar signal processing program capable of relatively accurately detecting a target based on a beat signal.

A radar signal processing device (<NUM>) is provided. The radar signal processing device includes an extracted signal generator (<NUM>), a converter (<NUM>) and an integrated data generator (<NUM>). The extracted signal generator (<NUM>) generates a processing signal based on a beat signal of a transmission signal and a reception signal, and generates a plurality of extracted beat signals by applying a plurality of window functions on the processing signal. The converter (<NUM>) converts the plurality of extracted beat signals to amplitude data indicating a relationship between a distance and an amplitude. The extracted signal generator (<NUM>) integrates a plurality of the amplitude data into integrated data.

In this way, by the configuration to generate multiple extracted beat signals extracted based on multiple different time ranges from the processing signal based on the beat signal, convert the extracted beat signals respectively to the amplitude data, and generate the integrated data in which multiple amplitude data are integrated, the integrated data can be generated using the amplitude data based on the extracted beat signal that does not include a beat signal whose amplitude is replaced with zero in order to remove, for example, an interference component. Thus, an increase in range side lobe in the integrated data due to the amplitude of some beat signals being replaced with zero can be suppressed, and a target can be relatively accurately detected based on the integrated data having a small range side lobe. Therefore, the target can be relatively accurately detected based on the beat signal.

According to the disclosure, a target can be relatively accurately detected based on a beat signal.

The integrated data generator (<NUM>) preferably selects the amplitude of one of the plurality of amplitude data (DS, DSA, DSA_1, DSA_2, DSB, DSC) for each of the distance (d) into the integrated data (DI).

A first window function (WfB) and a second window function (WfC) of the plurality of window functions (Wf, WfA, WfB, WfC) do not overlap in time.

A third window function (WfA) of the plurality of window functions (Wf, WfA, WfB, WfC) overlap both the first window function (WfB) and the second window function (WfC).

The plurality of window functions (Wf, WfA, WfB, WfC) preferably have a same type.

A radar device (<NUM>) is provided. The radar device preferably includes the radar signal processing device (<NUM>), a transmitter (<NUM>), and a receiver (<NUM>). The transmitter (<NUM>) is configured to transmit the transmission signal. The receiver (<NUM>) is configured to receive a reflected signal reflected by a target.

The transmitter (<NUM>) preferably transmits the transmission signal via a rotating antenna (<NUM>).

The receiver (<NUM>) preferably receives the reflected signal via a rotating antenna (<NUM>).

A radar signal processing method, and a non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a computer, cause the computer to execute the following processing, may be provided.

The method and the instructions may include generating a processing signal based on a beat signal (E, EA, EB, EC) of a transmission signal and a reception signal, generating a plurality of extracted beat signals by applying a plurality of window functions (Wf, WfA, WfB, WfC) on the processing signal, converting the plurality of extracted beat signals (E, EA, EB, EC) to amplitude data (DS, DSA, DSA_1, DSA_2, DSB, DSC) indicating a relationship between a distance and an amplitude, and integrating a plurality of the amplitude data (DS, DSA, DSA_1, DSA_2, DSB, DSC) into integrated data (DI).

Hereinafter, embodiments of the disclosure are described with reference to the drawings. The same or equivalent portions in the drawings are assigned with the same reference numerals and description thereof will not be repeated. In addition, at least some of the embodiments described below may be arbitrarily combined.

<FIG> illustrates a configuration of a radar device according to an embodiment of the disclosure.

Referring to <FIG>, a radar device <NUM> includes a radar <NUM> and a display processor <NUM>. The radar <NUM> includes a signal generator <NUM>, a transmitter <NUM>, a transmitting antenna <NUM>, a receiving antenna <NUM>, a receiver <NUM>, a mixer part <NUM>, an analog to digital (A/D) converter <NUM>, and a signal processor <NUM>. The signal processor <NUM> is an example of a radar signal processing device. For example, the radar device <NUM> is a frequency modulated continuous wave (FM-CW) radar device and is mounted on a ship. The radar device <NUM> may perform processing configured to display, on a display device (not shown), an echo image indicating the presence or absence of a target in a detection target area being a domain monitored by the ship as well as a distance between the radar device <NUM> and the target.

The radar <NUM> may output, to the display processor <NUM>, echo data indicating a detection result of the target in a divided target area being a domain obtained by dividing the detection target area into multiple domains. The transmitting antenna <NUM> and the receiving antenna <NUM> may rotate so that an azimuth angle in a radio wave radiation direction of the transmitting antenna <NUM> changes by a particular angle every particular sweep period T. The radar <NUM> may output, to the display processor <NUM>, the echo data in multiple divided target areas for each sweep period T.

The display processor <NUM> may perform processing configured to display the echo image in the detection target area on the display device based on multiple echo data received from the radar <NUM>.

The signal generator <NUM> may repeatedly generate an analog signal of a particular pattern and output the same to the transmitter <NUM>. More specifically, in the sweep period T, the signal generator <NUM> may output, to the transmitter <NUM>, an analog signal generated by a modulation method such as an FM-CW method and having a frequency increasing by a particular amount per unit time. Specifically, for example, the signal generator <NUM> includes a voltage generator and a voltage-controlled oscillator (VCO). In the sweep period T, the voltage generator may generate an FM modulated voltage having a magnitude increasing at a constant rate and output the same to the VCO. The VCO may generate an analog signal having a frequency corresponding to the magnitude of the FM modulated voltage received from the voltage generator and output the same to the transmitter <NUM>.

The transmitter <NUM> may transmit a transmission signal. More specifically, in the sweep period T, the transmitter <NUM> may generate a transmission signal of a radio frequency (RF) band based on the analog signal received from the signal generator <NUM>, and output the generated transmission signal of the RF band to the divided target area via the transmitting antenna <NUM> that rotates with rotation of the radar <NUM>. The transmitter <NUM> may output the generated transmission signal of the RF band to the mixer part <NUM>. Specifically, for example, the transmitter <NUM> includes a mixer and a power amplifier. This mixer may generate the transmission signal of the RF band based on the analog signal received from the signal generator <NUM>, and output the generated transmission signal to the power amplifier and the mixer part <NUM>. In the transmitter <NUM>, the power amplifier may amplify the transmission signal received from the mixer, and output the amplified transmission signal to the divided target area via the transmitting antenna <NUM>.

The receiver <NUM> may receive a reflected signal obtained by reflecting the transmission signal by the target. More specifically, the receiver <NUM> may receive a reflected signal of the RF band via the receiving antenna <NUM> that rotates with rotation of the radar <NUM>. The reflected signal of the RF band is obtained by reflecting the transmission signal transmitted from the transmitting antenna <NUM> by the target in the divided target area. The receiver <NUM> may also receive, via the receiving antenna <NUM>, an interference wave transmitted by an interfering object. The interfering object is, for example, a pulse radar device located in the divided target area or outside the divided target area. The receiver <NUM> may output a signal received via the receiving antenna <NUM> to the mixer part <NUM>. Specifically, for example, the receiver <NUM> includes a low noise amplifier. The low noise amplifier may amplify a reception signal of the RF band received via the receiving antenna <NUM>, and output the amplified reception signal to the mixer part <NUM>.

The mixer part <NUM> may generate a beat signal of the transmission signal transmitted from the radar device <NUM> and the reception signal received by the radar device <NUM>. Here, the beat signal is a signal having a frequency component of a difference between a frequency component of the transmission signal transmitted by the transmitter <NUM> and a frequency component of the reception signal received by the receiver <NUM>. More specifically, the mixer part <NUM> includes, for example, two mixers. A branch part (not shown) may branch the transmission signal output from the transmitter <NUM> and apply a phase difference of <NUM> ° to the transmission signals obtained by branching, and output the same to each mixer in the mixer part <NUM>. The branch part (not shown) may branch the reception signal output from the receiver <NUM> and output the same to each mixer in the mixer part <NUM>. The two mixers in the mixer part <NUM> may respectively multiply the transmission signals and reception signals, thereby generating an analog beat signal SA composed of a pair of an I signal Si and a Q signal Sq and outputting the same to the A/D converter <NUM>.

The A/D converter <NUM> may convert the analog beat signal SA received from the mixer part <NUM> to a beat signal SD being a digital signal composed of a pair of the I signal Si and the Q signal Sq. More specifically, the A/D converter <NUM> may perform sampling at a particular sampling frequency every sweep period T, thereby generating N beat signals SD composed of pairs of N I signals Si and N Q signals Sq and outputting the same to the signal processor <NUM>. N is an integer equal to or greater than <NUM>.

The signal processor <NUM> may process the N beat signals SD received from the A/D converter <NUM> in each sweep period T, thereby generating the echo data indicating the detection result of the target in the divided target area for each sweep period T. The signal processor <NUM> may output the generated echo data to the display processor <NUM>. Hereinafter, the beat signal SD received by the signal processor <NUM> from the A/D converter <NUM> in the sweep signal T and having a sample number n is also referred to as a beat signal SD(n). n is an integer equal to or greater than <NUM> and equal to or less than N, and corresponds to an elapsed time from the start of the sweep period T. The beat signal SD(n) is a signal composed of a pair of an I signal Si(n) having the sample number n and a Q signal Sq(n) having the sample number n.

The radar device <NUM> may be configured to include, instead of the transmitting antenna <NUM> and the receiving antenna <NUM>, one antenna that functions as the transmitting antenna <NUM> and the receiving antenna <NUM>. In this case, for example, the transmitter <NUM> may transmit the transmission signal to the transmitting antenna <NUM> via a circulator. For example, the receiver <NUM> may receive the reception signal from the receiving antenna <NUM> via the circulator.

The display processor <NUM> may, based on the echo data for each divided target area that is received from the signal processor <NUM>, generate integrated data being the echo data in the detection target area, and may, based on the generated integrated data, perform the processing configured to display the echo image in the detection target area on the display device (not shown).

<FIG> illustrates a configuration of a signal processor in a radar device according to an embodiment of the disclosure. Referring to <FIG>, the signal processor <NUM> includes an interference remover <NUM>, a window function and fast Fourier transform (FFT) processor <NUM>, and an absolute value to logarithmic converter <NUM>.

The interference remover <NUM> may receive N beat signals SD from the A/D converter <NUM>, and perform FFT preprocessing configured to remove an interference component (a component based on an interference wave) from components of the received beat signal SD every sweep period T. For example, in the FFT preprocessing, if the beat signal SD(n) including an interference wave is detected, the interference remover <NUM> may remove the interference component by replacing the amplitude of the I signal Si(n) and Q signal Sq(n) in the beat signal SD(n) including the interference wave with zero. The interference remover <NUM> may output the beat signal SD(n) after the FFT preprocessing to the window function and FFT processor <NUM>.

The window function and FFT processor <NUM> may perform window function processing configured to multiply the N beat signals SD(n) after the FFT preprocessing that are received from the interference remover <NUM> by a particular window function and perform processing such as FFT processing on the beat signal SD(n) after the window function processing, thereby generating the integrated data DI every sweep period T. The window function and FFT processor <NUM> may output the generated integrated data DI to the absolute value to logarithmic converter <NUM>. The window function processing and FFT processing performed by the window function and FFT processor <NUM> will be described in detail later.

The absolute value to logarithmic converter <NUM> may generate the echo data by logarithmic transformation of an absolute value of the integrated data DI received from the window function and FFT processor <NUM>, and output the generated echo data to the display processor <NUM>.

<FIG> illustrates a configuration of a window function and FFT processor in a signal processor according to an embodiment of the disclosure. Referring to <FIG>, the window function and FFT processor <NUM> includes an extracted signal generator <NUM>, a converter <NUM>, and an integrated data generator <NUM>. The extracted signal generator <NUM> includes window function processors 31A, 31B, and 31C. The converter <NUM> includes FFT processors 32A, 32B, and 32C.

The extracted signal generator <NUM> may generate, from a processing signal generated based on a beat signal, multiple extracted beat signals E extracted based on multiple different time ranges. For example, based on the beat signal SD(n) of a target time domain Ta, the extracted signal generator <NUM> may generate multiple extracted beat signals E respectively based on the beat signals SD(n) in multiple time ranges different from each other in the target time domain Ta. The beat signal SD(n) of the target time domain Ta is an example of the processing signal.

More specifically, each of the window function processors 31A, 31B, and 31C may receive the beat signal SD(n) from the interference remover <NUM>, and, based on the beat signal SD(n) of a particular target time domain Ta, which is some or all of the received beat signals SD(n), generate the extracted beat signal E. As an example, each of the window function processors 31A, 31B, and 31C may, based on the beat signal SD(n) of the target time domain Ta, which is all of the N beat signals SD(n) received from the interference remover <NUM>, generate the extracted beat signal E composed of a pair of an extracted I signal Ei and an extracted Q signal Eq..

Here, the window function processors 31A, 31B and 31C may receive from the interference remover <NUM>, as the beat signal SD(n) from which the interference component has been removed, for example, the beat signal SD(n) in which the amplitude of some of the I signals Si(n) and Q signals Sq(n) are replaced with zero.

<FIG> and <FIG> illustrate an example of a beat signal received from an interference remover by a window function and FFT processor in a signal processor according to an embodiment of the disclosure. <FIG> is an enlarged view of a region R1 in <FIG>. In <FIG> and <FIG>, the horizontal axis indicates the value of the sample number n of the beat signal SD(n), and the vertical axis indicates amplitude. The solid line in <FIG> and <FIG> indicates the I signal Si(n) in the beat signal SD(n). The broken line in <FIG> and <FIG> indicates the Q signal Sq(n) in the beat signal SD(n).

Referring to <FIG> and <FIG>, as an example, the window function processors 31A, 31B, and 31C may receive from the interference remover <NUM>, the beat signal SD(n) in which the amplitude of the I signal Si(n) and Q signal Sq(n) having the sample number n of <NUM> to <NUM> is replaced with zero.

For example, the window function processors 31A, 31B, and 31C may perform the window function processing on the beat signal SD(n) received from the interference remover <NUM>. Each of the window function processors 31A, 31B and 31C may generate multiple extracted beat signals E from the beat signal SD(n) by multiplying multiple window functions Wf different in pass time domain. That is, in the window function processing, each of the window function processors 31A, 31B, and 31C may generate the extracted beat signal E by multiplying the N beat signals SD(n) received from the interference remover <NUM> by the window functions Wf different from each other in pass time domain TP (a time domain serving as a pass band).

More specifically, the window function processor 31A may multiply the I signal Si(n) and Q signal Sq(n) in the beat signal SD(n) by a window function WfA (which is also referred to as a third window function), thereby generating an extracted beat signal EA being the extracted beat signal E composed of a pair of an extracted I signal EiA and an extracted Q signal EqA.

The window function processor 31B may multiply the I signal Si(n) and Q signal Sq(n) in the beat signal SD(n) by a window function WfB (which is also referred to as a first window function), thereby generating an extracted beat signal EB being the extracted beat signal E composed of a pair of an extracted I signal EiB and an extracted Q signal EqB.

The window function processor 31C may multiply the I signal Si(n) and Q signal Sq(n) in the beat signal SD(n) by a window function WfC (which is also referred to as a second window function), thereby generating an extracted beat signal EC being the extracted beat signal E composed of a pair of an extracted I signal EiC and an extracted Q signal EqC.

<FIG> illustrates an example of a window function used in a window function and FFT processor of a signal processor according to an embodiment of the disclosure. In <FIG>, the horizontal axis indicates the value of the sample number n of the beat signal SD(n), and the vertical axis indicates window weight of the window function Wf. As described above, the sample number n corresponds to the elapsed time from the start of the sweep period T. The solid line in <FIG> indicates the window function WfA used in the window function processing by the window function processor 31A. The broken line in <FIG> indicates the window function WfB used in the window function processing by the window function processor 31B. The chain line in <FIG> indicates the window function WfC used in the window function processing by the window function processor 31C.

Referring to <FIG>, a pass time domain TPA being the pass time domain TP of the window function WfA indicates the time from time t0 corresponding to the sample number n=zero to time tN corresponding to the sample number n=N. A pass time domain TPB being the pass time domain TP of the window function WfB indicates the time from time t0 corresponding to the sample number n=zero to time tk corresponding to the sample number n=k. A pass time domain TPC being the pass time domain TP of the window function WfC indicates the time from time t(k+<NUM>) corresponding to the sample number n=(k+<NUM>) to time tN corresponding to the sample number n=N. Here, k is an integer equal to or greater than <NUM> and less than N, and is, for example, an integer closest to N/<NUM>. That is, the pass time domains TPA, TPB, and TPC respectively correspond to a time domain of the whole target time domain Ta, a time domain of the first half of the target time domain Ta, and a time domain of the latter half of the target time domain Ta. For example, multiple window functions Wf include those having the same shape design. In the example shown in <FIG>, the window function WfB and the window function WfC have the same shape in the pass time domains TPB and TPC. The shapes of the window functions WfA, WfB, and WfC are not limited to the shapes shown in <FIG> and may be any other shape.

For example, the extracted signal generator <NUM> may generate multiple extracted beat signals E extracted based on a temporally continuous time range. That is, the extracted signal generator <NUM> may generate multiple extracted beat signals E respectively based on the beat signals SD(n) in multiple time ranges that are temporally continuous. More specifically, the pass time domain TPB being the time from time t0 to time tk and the pass time domain TPC being the time from time t(k+<NUM>) to time tN are time domains that are temporally continuous in this order. The window function processors 31B and 31C may respectively multiply the beat signal SD(n) by the window functions WfB and WfC, thereby generating the extracted beat signals EB and EC respectively based on the beat signals SD(n) in multiple time ranges that are temporally continuous.

For example, the extracted signal generator <NUM> may generate, as one of the extracted beat signals E, the extracted beat signal E extracted based on a time range including multiple time ranges. That is, the extracted signal generator <NUM> may generate, as one of multiple extracted beat signals E, the extracted beat signal E based on the beat signal SD(n) of the target time domain Ta. More specifically, the pass time domain TPA is a time domain corresponding to the target time domain Ta. The window function processor 31A may multiply the beat signal SD(n) by the window function WfA, thereby generating the extracted beat signal EA based on the beat signal SD(n) of the target time domain Ta.

For example, while the pass time domain TPA and the pass time domain TPB include a time corresponding to the sample number n of <NUM> to <NUM>, the pass time domain TPC does not include the time corresponding to the sample number n of <NUM> to <NUM>. That is, while the extracted beat signals EA and EB include the I signal Si(n) and Q signal Sq(n) whose amplitude is replaced with zero, the extracted beat signal EC does not include the I signal Si(n) and Q signal Sq(n) whose amplitude is replaced with zero.

The window function processors 31A, 31B, and 31C may respectively output the generated extracted beat signals EA, EB, and EC to the FFT processors 32A, 32B, and 32C in the converter <NUM>.

The converter <NUM> may convert multiple extracted beat signals E to amplitude data DS indicating a relationship between distance and amplitude. That is, the converter <NUM> may convert multiple extracted beat signals E being complex signals respectively to the amplitude data DS indicating a relationship between a distance d from the radar device <NUM> and an amplitude.

More specifically, the converter <NUM> may receive multiple extracted beat signals E from the extracted signal generator <NUM> and perform the FFT processing on the received extracted beat signals E, thereby generating a power spectrum P being a complex signal. Then, the converter <NUM> may perform processing configured to multiply a frequency in each power spectrum P generated for each extracted beat signal E by a coefficient C to convert the frequency to the distance d, or the like, thereby generating the amplitude data DS being a complex signal for each extracted beat signal E.

Specifically, the FFT processor 32A may receive the extracted beat signal EA from the window function processor 31A and perform the FFT processing on the received extracted beat signal EA, thereby generating a power spectrum PA. Then, the FFT processor 32A may perform processing configured to multiply a frequency in the generated power spectrum PA by the coefficient C to convert the frequency to the distance d, thereby generating amplitude data DSA indicating the relationship between the distance d and the amplitude.

The FFT processor 32B may receive the extracted beat signal EB from the window function processor 31B and perform the FFT processing on the received extracted beat signal EB, thereby generating a power spectrum PB. Then, the FFT processor 32B may perform processing configured to multiply a frequency in the generated power spectrum PB by the coefficient C to convert the frequency to the distance d, and double each of I data and Q data in the power spectrum PB, thereby generating amplitude data DSB indicating the relationship between the distance d and the amplitude. Here, since the pass time domain TPB of the window function WfB is <NUM>/<NUM> of the pass time domain TPA of the window function WfA, the output of the power spectrum PB is <NUM>/<NUM> of that of the power spectrum PA. Therefore, in order to compensate for a ratio of the power spectrum P generated by a ratio of the pass time domain TP of the window function Wf, the FFT processor 32B may perform the processing configured to double each of the I data and Q data in the power spectrum PB. For example, in the case where the pass time domain TPB of the window function WfB is <NUM>/K of the pass time domain TPA of the window function WfA, in order to compensate for a ratio of the output of the power spectrum PB to the power spectrum PA, the FFT processor 32B may perform processing configured to multiply each of the I data and Q data in the power spectrum PB by K.

The FFT processor 32C may receive the extracted beat signal EC from the window function processor 31C and perform the FFT processing on the received extracted beat signal EC, thereby generating a power spectrum PC. Then, the FFT processor 32C may perform processing configured to multiply a frequency in the generated power spectrum PC by the coefficient C to convert the frequency to the distance d, and double each of the I data and Q data in the power spectrum PC similarly to the FFT processor 32B, thereby generating amplitude data DSC indicating the relationship between the distance d and the amplitude.

<FIG> illustrates an example of amplitude data generated in a window function and FFT processor of a signal processor according to an embodiment of the disclosure. In <FIG>, the horizontal axis indicates distance d [m] and the vertical axis indicates amplitude [dB]. The broken line in <FIG> indicates an amplitude Xa of the amplitude data DSA. The chain line in <FIG> indicates an amplitude Xb of the amplitude data DSB. The chain double-dashed line in <FIG> indicates an amplitude Xc of the amplitude data DSC.

Referring to <FIG>, the amplitude data DSC has a smaller range side lobe than the amplitude data DSA and DSB. The reason is that as described above, while the extracted beat signals EA and EB include the I signal Si(n) and Q signal Sq(n) whose amplitude is replaced with zero, the extracted beat signal EC does not include the I signal Si(n) and Q signal Sq(n) whose amplitude is replaced with zero.

The FFT processors 32A, 32B, and 32C may respectively output the generated amplitude data DSA, DSB, and DSC to the integrated data generator <NUM>.

The integrated data generator <NUM> may generate integrated data in which multiple amplitude data are integrated. More specifically, based on the amplitude for each distance d in the amplitude data DSA, DSB, and DSC, the integrated data generator <NUM> may generate the integrated data DI indicating the relationship between the distance d and the amplitude.

For example, the integrated data generator <NUM> may generate the integrated data DI by selecting the amplitude of any one of the amplitude data DSA, DSB, and DSC for each distance d. As an example, the integrated data generator <NUM> may take the minimum value of the amplitude data DSA, DSB, and DSC, thereby generating the integrated data DI being a set of minimum values of the amplitude of the amplitude data DSA, DSB, and DSC.

More specifically, the integrated data generator <NUM> may calculate an amplitude absolute value ampA(d) for each distance d of the amplitude data DSA, represented by the following Equation (<NUM>), an amplitude absolute value ampB(d) for each distance d of the amplitude data DSB, represented by the following Equation (<NUM>), and an amplitude absolute value ampC(d) for each distance d of the amplitude data DSC, represented by the following Equation (<NUM>). <MAT> <MAT> <MAT>.

Here, (Ia)^<NUM>+(Qa)^ <NUM> is the sum of the square of the I data in the amplitude data DSA and the square of the Q data in the amplitude data DSA. (Ib)^<NUM>+(Qb)^<NUM> is the sum of the square of the I data in the amplitude data DSB and the square of the Q data in the amplitude data DSB. (Ic)^<NUM>+(Qc)^<NUM> is the sum of the square of the I data in the amplitude data DSC and the square of the Q data in the amplitude data DSC.

The integrated data generator <NUM> may select the minimum value of the amplitude absolute values ampA(d), ampB(d), and ampC(d) for each distance d. Hereinafter, the distance d when the minimum value of the amplitude absolute values ampA(d), ampB(d), and ampC(d) is the amplitude absolute value ampA(d) is defined as a distance da, the distance d when the minimum value of the amplitude absolute values ampA(d), ampB(d), and ampC(d) is the amplitude absolute value ampB(d) is defined as a distance db, and the distance d when the minimum value of the amplitude absolute values ampA(d), ampB(d), and ampC(d) is the amplitude absolute value ampC(d) is defined as a distance dc.

That is, the integrated data generator <NUM> may determine the distance d to be any one of the distances da, db, and dc based on a comparison result between the amplitude absolute values ampA(d), ampB(d), and ampC(d).

Then, the integrated data generator <NUM> may select an amplitude in the amplitude data DSA that corresponds to the distance da, an amplitude in the amplitude data DSB that corresponds to the distance db and an amplitude in the amplitude data DSC that corresponds to the distance dc, and generate the integrated data DI including the selected amplitudes.

<FIG> and <FIG> illustrate an example of integrated data generated in a window function and FFT processor of a signal processor according to an embodiment of the disclosure. <FIG> is an enlarged view of a region R2 in <FIG>. In <FIG> and <FIG>, the horizontal axis indicates distance d [m] and the vertical axis indicates amplitude [dB]. The solid line in <FIG> and <FIG> indicates amplitude of the integrated data DI. The broken line in <FIG> and <FIG> indicates amplitude of the amplitude data DSA. The chain line in <FIG> and <FIG> indicates amplitude of the amplitude data DSB. The chain double-dashed line in <FIG> and <FIG> indicates amplitude of the amplitude data DSC.

Referring to <FIG> and <FIG>, the integrated data generator <NUM> may generate the integrated data DI being a set of minimum values of the amplitude of the amplitude data DSA, the amplitude of the amplitude data DSB, and the amplitude of the amplitude data DSC.

The integrated data generator <NUM> may output the generated integrated data DI to the absolute value to logarithmic converter <NUM>.

<FIG> and <FIG> illustrate an example of integrated data generated in a window function and FFT processor of a signal processor according to an embodiment of the disclosure. <FIG> is an enlarged view of a region R3 in <FIG>. In <FIG> and <FIG>, the horizontal axis indicates distance d [m] and the vertical axis indicates amplitude [dB]. The solid line in <FIG> and <FIG> indicates amplitude of the integrated data DI. The broken line in <FIG> and <FIG> indicates amplitude data DSA_1 generated by performing the FFT processing or the like on the extracted beat signal EA based on the beat signal SD(n) in which interference is mixed and a domain thereof is replaced with zero. The chain line in <FIG> and <FIG> indicates amplitude data DSA_2 generated by performing the FFT processing or the like on the extracted beat signal EA based on an ideal beat signal SD(n) in which no interference is mixed and no domain is replaced with zero.

Referring to <FIG> and <FIG>, the amplitude data DSA_1 generated based on the beat signal SD(n) from which the interference component has been removed has a larger range side lobe than the amplitude data DSA_2. On the other hand, the integrated data DI has the same peak shape as the amplitude data DSA_1 and DSA_2, and has a smaller range side lobe than the amplitude data DSA_1. Therefore, in the radar device <NUM> according to an embodiment of the disclosure, based on the beat signal SD(n) from which the interference component has been removed, the integrated data DI can be generated having a small range side lobe while maintaining the same peak shape as the ideal beat signal having no interference mixing therein. Thus, a target can be relatively accurately detected based on the integrated data DI.

A radar device according to an embodiment of the disclosure includes a computer including a memory. An arithmetic processor such as a CPU in the computer may read from the memory a program including some or all of steps of the following flowchart and sequence and execute the same. The program can be installed from the outside. The program is stored in a recording medium or distributed via a communication line.

<FIG> is a flowchart defining an example of an operation procedure when a radar device according to an embodiment of the disclosure generates integrated data.

Referring to <FIG>, firstly, the radar device <NUM> may multiply the beat signal SD(n) by the window functions WfA, WfB, and WfC, respectively, thereby generating the beat signals EA, EB, and EC (step S102).

Next, the radar device <NUM> may perform the FFT processing or the like on the extracted beat signals EA, EB, and EC, thereby converting the extracted data signals EA, EB, and EC to the amplitude data DSA, DSB, and DSC (step S104).

Next, the radar device <NUM> may calculate the amplitude absolute value ampA(d) for each distance d of the amplitude data DSA, the amplitude absolute value ampB(d) for each distance d of the amplitude data DSB, and the amplitude absolute value ampC(d) for each distance d of the amplitude data DSC (step S106).

Next, the radar device <NUM> may select the minimum value of the amplitude absolute values ampA(d), ampB(d), and ampC(d) for each distance d, thereby distributing the distance d to any of the distances da, db, and dc (step S108).

Next, the radar device <NUM> may generate the integrated data DI including the amplitude in the amplitude data DSA that corresponds to the distance da, the amplitude in the amplitude data DSB that corresponds to the distance db and the amplitude in the amplitude data DSC that corresponds to the distance dc (step S110).

In the signal processor <NUM> according to an embodiment of the disclosure, the extracted signal generator <NUM> is configured to generate the extracted beat signals EA, EB, and EC by multiplying the beat signal SD(n) by the window functions WfA, WfB, and WfC having different time domains serving as pass bands. However, the disclosure is not limited thereto. The extracted signal generator <NUM> may be configured to generate the extracted beat signals EA, EB, and EC being beat signals SD(n) in multiple time ranges different from each other by extraction of some or all the beat signals SD(n) without use of the window functions WfA, WfB, and WfC.

In the signal processor <NUM> according to an embodiment of the disclosure, the extracted signal generator <NUM> is configured to generate the extracted beat signals EB and EC respectively based on the beat signals SD(n) in multiple time ranges that are temporally continuous. However, the disclosure is not limited thereto. The extracted signal generator <NUM> may be configured to generate the extracted beat signals EB and EC respectively based on the beat signals SD(n) in multiple time ranges that partially overlap. That is, the pass time domains TPB and TPC may temporally overlap. However, since the extracted signal generator <NUM> is configured to generate the extracted beat signals EB and EC respectively based on the beat signals SD(n) in multiple time ranges that are temporally continuous, it is possible to prevent that the same I signal Si(n) and Q signal Sq(n) whose amplitude is replaced with zero in the interference remover <NUM> are included in both the extracted beat signals EB and EC.

In the signal processor <NUM> according to an embodiment of the disclosure, the extracted signal generator <NUM> is configured to generate the extracted beat signal EA based on the beat signal SD(n) of the target time domain Ta. However, the disclosure is not limited thereto. The extracted signal generator <NUM> may be configured to generate the extracted beat signals EB and EC, but not to generate the extracted beat signal EA. That is, the extracted signal generator <NUM> may be configured not to include the window function processor 31A.

In the signal processor <NUM> according to an embodiment of the disclosure, the extracted signal generator <NUM> is configured to generate the extracted beat signals EA, EB, and EC. However, the disclosure is not limited thereto. The extracted signal generator <NUM> may be configured to generate two or four or more extracted beat signals E. For example, the extracted signal generator <NUM> may be configured to generate M extracted beat signals E respectively based on the beat signals SD(n) in M time ranges that are different from each other by dividing the target time domain Ta by M. That is, the extracted signal generator <NUM> may be configured to include M window function processors that respectively generate the beat signals E by respectively multiplying the beat signal SD(n) by M window functions Wf having different pass time domains TP from each other. Here, M is an integer equal to or greater than <NUM>. Even if the beat signal SD(n) includes more interference waves as M increases, the integrated data DI having a relatively small range side lobe can be generated. On the other hand, the smaller M is, the simpler the configuration of the window function and FFT processor <NUM> can be.

In the signal processor <NUM> according to an embodiment of the disclosure, the integrated data generator <NUM> is configured to generate the integrated data DI being a set of minimum values of the amplitude of the amplitude data DSA, DSB, and DSC. However, the disclosure is not limited thereto. The integrated data generator <NUM> may be configured to generate the integrated data DI by performing arithmetic processing such as calculation of an average value for the amplitude of the amplitude data DSA, DSB, and DSC.

By the way, there is a desire for a technique capable of relatively accurately detecting a target based on a beat signal.

For example, the radar system described in Patent Document <NUM> is configured to include a signal processing path for removing interference waves from the beat signal and a signal processing path for not removing interference waves from the beat signal. In such a configuration, a range side lobe in a power spectrum generated based on the beat signal may increase, and a target may not be able to be accurately detected.

In contrast, in the signal processor <NUM> according to an embodiment of the disclosure, the extracted signal generator <NUM> generates the extracted beat signals EA, EB, and EC extracted based on multiple different time ranges from a processing signal generated based on a beat signal of a transmission signal and a reception signal. The converter <NUM> converts the extracted beat signals EA, EB, and EC to the amplitude data DSA, DSB, and DSC indicating the relationship between the distance d and the amplitude. The integrated data generator <NUM> generates the integrated data DI in which the amplitude data DSA, DSB, and DSC are integrated.

In this way, by the configuration to generate the extracted beat signals EA, EB, and EC extracted based on multiple different time ranges from the processing signal based on the beat signal, convert the extracted beat signals EA, EB, and EC respectively to the amplitude data DSA, DSB, and DSC, and generate the integrated data DI in which multiple amplitude data DSA, DSB, and DSC are integrated, the integrated data DI can be generated using the amplitude data DSC based on the extracted beat signal EC that does not include the beat signal SD(n) whose amplitude is replaced with zero in order to remove, for example, the interference component. Thus, an increase in range side lobe in the integrated data DI due to the amplitude of some beat signals SD(n) being replaced with zero can be suppressed, and the target can be relatively accurately detected based on the integrated data DI having a small range side lobe. Therefore, the target can be relatively accurately detected based on the beat signal SD(n).

In the signal processor <NUM> according to an embodiment of the disclosure, the extracted signal generator <NUM> generates the extracted beat signals EA, EB, and EC from the processing signal by multiplying multiple window functions different in pass time domain.

By such a configuration, for example, by performing a Fourier transform on the extracted beat signals EA, EB, and EC generated by using an appropriate window function, the amplitude data DSA, DSB, and DSC having relatively small error can be generated.

In the signal processor <NUM> according to an embodiment of the disclosure, the integrated data generator <NUM> generates the integrated data DI by selecting the amplitude of any one of the amplitude data DSA, DSB, and DSC for each distance d.

By such a configuration, for example, the amplitude data DS having a smallest range side lobe can be selectively used and the integrated data DI having a relatively small range side lobe can be easily generated.

In the signal processor <NUM> according to an embodiment of the disclosure, the extracted signal generator <NUM> generates the extracted signal signals EB and EC extracted based on a temporally continuous time range.

By such a configuration, it can be suppressed that one beat signal SD(n) whose amplitude is replaced with zero in order to remove, for example, the interference component, is included in both the extracted beat signals EB and EC. Thus, in at least one of the amplitude data DSB and DSC based on the extracted beat signals EB and EC, an increase in range side lobe due to the amplitude of the beat signal SD(n) being replaced with zero can be suppressed.

In the signal processor <NUM> according to an embodiment of the disclosure, the extracted signal generator <NUM> generates, as one of the extracted beat signal E, the extracted beat signal EA extracted based on a time range including multiple time ranges.

By such a configuration, the amplitude data DSA having a relatively high range resolution can be generated based on the extracted beat signal EA based on the beat signal SD(n) having a relatively large sample number. Thus, the integrated data DI having a relatively high range resolution can be generated using the amplitude data DSA.

In the signal processor <NUM> according to an embodiment of the disclosure, the window function includes those having the same shape design.

By such a configuration, there is no need to perform correction processing or the like on the extracted beat signal according to a difference in the shape of the window function, and the integrated data DI can be generated by a simple configuration and processing.

The radar device <NUM> according to an embodiment of the disclosure includes the signal processor <NUM>, the transmitter <NUM>, and the receiver <NUM>. The transmitter <NUM> transmits the transmission signal. The receiver <NUM> receives the reflected signal obtained by reflecting the transmitted transmission signal by the target.

By such a configuration, the radar device <NUM> that relatively accurately detects the target based on the beat signal SD(n) can be realized.

In the radar device <NUM> according to an embodiment of the disclosure, the transmitter <NUM> transmits the transmission signal via the rotating transmitting antenna <NUM>. The receiver <NUM> receives the reflected signal via the rotating receiving antenna <NUM>.

By such a configuration, the transmission signal can be transmitted and the reflected signal can be received in various directions. Thus, the target can be detected in a relatively wide range.

A radar signal processing method according to an embodiment of the disclosure is a radar signal processing method in the signal processor <NUM> used in the radar device <NUM>. In the radar signal processing method, firstly, the signal processor <NUM> may generate the extracted beat signals EA, EB, and EC extracted based on multiple different time ranges from the processing signal generated based on the beat signal of the transmission signal and the reception signal. Next, the signal processor <NUM> may convert the extracted beat signals EA, EB, and EC to the amplitude data indicating the relationship between the distance d and the amplitude. Next, the signal processor <NUM> may generate the integrated data DI in which the amplitude data DSA, DSB, and DSC are integrated.

Claim 1:
A radar signal processing device (<NUM>) comprising:
an extracted signal generator (<NUM>) configured to:
generate a processing signal based on a beat signal of a transmission signal and a reception signal, and
generate a plurality of extracted beat signals (E, EA, EB, EC) by applying a plurality of window functions (Wf, WfA, WfB, WfC) on the processing signal, wherein a first window function (WfB) and a second window function (WfC) of the plurality of window functions (Wf, WfA, WfB, WfC) do not overlap in time, and wherein a third window function (WfA) of the plurality of window functions (Wf, WfA, WfB, WfC) overlaps both of the first window function (WfB) and the second window function (WfC) in time;
a converter (<NUM>) configured to convert the plurality of extracted beat signals (E, EA, EB, EC) by using FFT to amplitude data (DS, DSA, DSA_1, DSA_2, DSB, DSC) indicating a relationship between a distance (d) and an amplitude; and
an integrated data generator (<NUM>) configured to integrate a plurality of the amplitude data (DS, DSA, DSA_1, DSA_2, DSB, DSC) into integrated data (DI).