Patent Description:
Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices, which typically has the advantage of keeping stored data even when the device is not connected to an electrical source.

The aforementioned MR effect has also been used in magnetic field sensor areas including but not limited to for example electronic compass components used in global positioning system (GPS) of cellular phones for providing information regarding moving location to users. Currently, various magnetic field sensor technologies such as anisotropic magnetoresistance (AMR) sensors, GMR sensors, and magnetic tunneling junction (MTJ) sensors have been widely developed in the market. Nevertheless, most of these products still pose numerous shortcomings such as high chip area, high cost, high power consumption, limited sensibility, and easily affected by temperature variation and how to come up with an improved device to resolve these issues has become an important task in this field. <CIT> relates to a method for forming embedded MRAM in interconnects using a metal hard mask process. <CIT> relates to methods for forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions. <CIT> relates to device and a method for forming a device and including firstly providing a substrate defined with first and second functional regions and first and second non-functional regions. <CIT> relates to an integrated chip, which includes a magneto resistive random-access memory (MRAM) device surrounded by a dielectric structure disposed over a substrate.

One of the objectives of the present disclosure is to provide a semiconductor device, which includes a dummy magnetic tunneling junction (MTJ) with a novel structure, so as to be directly disposed within a logic region, thereby simplifying the layout pattern of the semiconductor device and improving the device functions.

To achieve the purpose described above, one embodiment of the present invention provides a semiconductor device, comprising: a substrate; a first dielectric layer disposed on the substrate, the first dielectric layer around a first metal interconnection; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer around a via and a second metal interconnection, the second metal interconnection directly contacting the first metal interconnection; and a third dielectric layer disposed on the second dielectric layer, the third dielectric layer around a first magnetic tunneling junction, MTJ, structure and a third metal interconnection, wherein e- characterized in that the via (<NUM>) and the second metal interconnection (<NUM>) respectively contact the first MTJ structure and the third metal interconnection (<NUM>), and the third metal interconnection (<NUM>) directly contacts the first MTJ structure.

Overall speaking, the dummy MTJ of the present invention is directly disposed within a logic region of a general MRAM device, and the dummy structure of the dummy MTJ is caused by the metal interconnections disposed within the logic region, leading to the short circuit or the open circuit of MTJs. Through these arrangements, the semiconductor device of the present invention is allowable to integrate the logic region and the dummy MRAM region of the general MRAM device, for sufficiently shrinking the layout pattern thereof. In this way, the design of the MRAM device may save more space in element arrangement and greatly improve the leakage issue.

To provide a better understanding of the presented invention, preferred embodiments will be described in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.

Please refer to <FIG>, which shows a top view of a semiconductor device <NUM> according to a first preferred embodiment of the present invention. The semiconductor device <NUM> is for example a magnetoresistive random access memory (MRAM) device, and which includes a substrate (not shown in the drawings) such as a substrate made of semiconductor material, with the semiconductor material being selected from the group consisting of silicon (Si), germanium (Ge), Si-Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs). The substrate preferably includes a MRAM region <NUM> and a logic region <NUM> defined thereon. In the present embodiment, the MRAM region <NUM> may be disposed at least one outer side of the logic region <NUM>, and a dummy MRAM region <NUM> is further disposed between the MRAM region <NUM> and the logic region <NUM>, in which, a plurality of magnetic tunneling junction (MTJ) structures <NUM> is disposed in the MRAM region <NUM> and a plurality of dummy MTJ structures <NUM> is disposed in the dummy MRAM region <NUM>. In other words, the MRAM region <NUM> and the logic region <NUM> are spaced apart by the dummy MRAM region <NUM> in the semiconductor device <NUM>.

The MRAM region <NUM> of the substrate includes a plurality of metal-oxide semiconductor (MOS) transistors <NUM>, which may be planar MOS transistors or non-planar (such as FinFETs) MOS transistors. More specifically, the MOS transistors <NUM> includes a plurality of doped regions <NUM> and a plurality of gate structures <NUM> (for example metal gates) across the doped regions <NUM>, in which each of the doped regions <NUM> parallel extended along a same direction (such as the x-direction), and portions of the doped regions <NUM> disposed at two sides of the gate structures <NUM> may be configured as source/drain (not shown in the drawings) of each of the gate structures <NUM>. Since the fabrication of planar or non-planar transistors is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

An interlayer dielectric layer (not shown in the drawings) is further disposed on the substrate to cover the MOS transistors <NUM>, and a plurality of plugs <NUM>, <NUM>, <NUM> and a plurality of metal layers <NUM>, <NUM>, <NUM> are disposed in the dielectric layer. In one embodiment, the metal layers <NUM>, <NUM>, <NUM> and the plugs <NUM>, <NUM>, <NUM> may be embedded within the dielectric layer according to a single damascene process or dual damascene process. Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. In the present embodiment, the metal layers <NUM>, <NUM>, <NUM> may be referred as the first level metal interconnect layer (M1), and other metal interconnections (not shown in the drawings) may be further disposed over the first level metal interconnect layer. However, in order to simplify the illustration, only the first level metal interconnect layer is illustrated in <FIG>.

The plugs <NUM> and the metal layers <NUM> are electrically connected to the source of each of the MOS transistors <NUM>. The metal layers <NUM> may be referred as a common source line which connects the source of MOS transistors <NUM> which are adjacent to each other, and the source may be further connected to an external voltage through other interconnections formed sequentially, with the aforementioned other interconnections including but not limited to for example the first level via conductor layer (V1), the second level metal interconnect layer (M2), the second level via conductor layer (V2), and the third level metal interconnect layer (M3) disposed over the first level metal interconnect layer. The plugs <NUM> and the metal layers <NUM> are electrically connection to the drain of each of the MOS transistors <NUM> respectively, as shown in <FIG>. On the other hand, the plugs <NUM> and the metal layers <NUM> are disposed within the logic region <NUM>, to electrically connect the gate structures <NUM> of the MOS transistors <NUM>. Then, the MOS transistors <NUM> may be further connected to a word line (WL, not shown in the drawings) and a bit line (BL, not shown in the drawings) through the aforementioned other interconnections, for receiving voltage signals from the word line and the bit line respectively.

In the semiconductor device <NUM> of the present embodiment, the dummy MRAM region <NUM> is additionally provided to fill the space between the MRAM region <NUM> and the logic region <NUM>. For example, the dummy MRAM region <NUM> includes two rows of dummy MTJ structures <NUM> which are staggeredly arranged within the dummy MRAM region <NUM>, while no MTJs including active MTJs such as the MTJ structures <NUM> or dummy MTJs such as the dummy MTJ structures <NUM> is disposed in the logic region <NUM>. Through this arrangement, the layout pattern of the semiconductor device <NUM> is composed by the MRAM region <NUM>, the dummy MRAM region <NUM> and the logic region <NUM>, and the contamination and/or inducing leakage issue which is caused by upper level metal interconnect layers may be successfully avoided, so as to improve the device functions. It is noted that, the arranged number of the dummy MTJ structures <NUM> in the semiconductor device <NUM> is only for example, and the specific arrangement number of the dummy MTJ structures <NUM> within the dummy MRAM region <NUM> may be further adjustable according to the product requirements.

People well known in the arts should easily realize the semiconductor device in the present invention is not limited to the aforementioned embodiment, and may further include other examples or variety in order to meet the practical requirements. As an example, the layout of the semiconductor device <NUM> in the aforementioned embodiment consumes a lot of space, which may affect the overall performance substantially. The following description will detail the different embodiments of the semiconductor device in the present invention. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols.

Please refers to <FIG>, which show a semiconductor device <NUM> according to a second preferred embodiment of the present invention, in which <FIG> shows a top view of the semiconductor device <NUM>, and <FIG> and <FIG> are respectively show a cross-sectional view take along cross lines A-A' and B-B' in <FIG>. The semiconductor device <NUM> is also a MRAM device for example, and which includes a substrate <NUM>, such as a substrate made of the aforementioned semiconductor material. Also, a plurality of the MOS transistors <NUM>, and a plurality of plugs <NUM>, <NUM> electrically connected to the MOS transistors <NUM> are disposed on the substrate <NUM>. All similarities between the present embodiment and the aforementioned first embodiment will not be redundantly described hereinafter. For simplifying the description, the first level metal interconnect layer (for example including the metal layers <NUM>, <NUM>, <NUM>) of the semiconductor device <NUM> has been omitted in <FIG>, to only illustrate the second level via conductor layer (for example including the metal interconnections <NUM>), the third level metal interconnect layer (for example including the metal interconnections <NUM>), and the MTJs (for example including the MTJ structures <NUM> and the dummy MTJ structures <NUM>) disposed over the first level metal interconnect layer. In <FIG> and <FIG>, the first level metal interconnect layer, the MOS transistors <NUM> and the plugs <NUM>,<NUM> are omitted to only illustrate the second level metal interconnect layer (for example including metal interconnections <NUM>), the second via conductor layer, the third level metal interconnect layer, and the MTJs of the semiconductor device <NUM>.

In the present embodiment, the substrate <NUM> includes a MRAM region <NUM> and a dummy MRAM region <NUM> defined thereon. The dummy MRAM region <NUM> integrates the dummy MRAM region <NUM> and the logic region <NUM> of the aforementioned first embodiment, that is, the dummy MTJs disposed within the dummy MRAM region <NUM> and the interconnection disposed within the logic region <NUM> are jointly disposed in the same region namely the dummy MRAM region <NUM> of the present embodiment. Specifically, a plurality of the MTJ structures <NUM> is also disposed within the MRAM region <NUM>, and a plurality of dummy MTJ structures <NUM> is disposed within the MRAM region <NUM> in a staggered arrangement, wherein the dummy MTJ structures <NUM>, and a plurality of metal interconnections <NUM> which is also disposed within the dummy MRAM region <NUM>, are repeatedly arranged by repeating one dummy MTJ structure <NUM> followed by one metal interconnection <NUM>, as shown in <FIG>.

As shown in <FIG> and <FIG>, a stop layer <NUM>, an inter-metal dielectric layer <NUM> and a plurality of the metal interconnections <NUM> are further disposed on the substrate <NUM>. Specifically, the stop layer <NUM> and the inter-metal dielectric layer <NUM> sequentially cover the first level metal interconnect layer and other active elements (not shown in the drawings) or passive elements (not shown in the drawings) rather disposed on the substrate <NUM> or disposed in the substrate <NUM>, around the metal interconnections <NUM>. Moreover, a plurality of plugs <NUM> and the metal interconnections <NUM> disposed within the dummy MRAM region <NUM> are further disposed on the inter-metal dielectric layer <NUM>, to electrically connect the metal interconnections <NUM> disposed underneath. Then, the MTJ structures <NUM>, the dummy MTJ structures <NUM> and/or the metal interconnections <NUM> are disposed on the plugs <NUM> and the metal interconnections <NUM>, wherein a stop layer <NUM> and an inter-metal dielectric layer <NUM> further surrounds the plugs <NUM> and the metal interconnections <NUM>, and another inter-metal dielectric layer <NUM> disposed on the inter-metal dielectric layer <NUM> surrounds the MTJ structures <NUM>, the dummy MTJ structures <NUM> and the metal interconnections <NUM>. Accordingly, the metal interconnections <NUM> may be electrically connected to the metal interconnections <NUM> through the metal interconnections <NUM>. Also, another stop layer <NUM> is further disposed on the substrate <NUM>, to cover the MTJ structures <NUM>, the dummy MTJ structures <NUM>, the metal interconnections <NUM>, and the inter-metal dielectric layer <NUM>.

In the present embodiment, each of the aforementioned metal interconnections <NUM>, <NUM>, <NUM> may be embedded within each inter-metal dielectric layer (for example including the inter-metal dielectric layers <NUM>, <NUM>, <NUM>) and/or each stop layer (for example including the stop layers <NUM>, <NUM>) according to a single damascene process or dual damascene process, to electrically connect with each other. Preferably, each of the metal interconnections <NUM> includes a trench conductor, to be referred as the second level metal interconnect layer, each of the metal interconnections <NUM> includes a via conductor, to be referred as the second level via conductor layer, and each of the metal interconnections <NUM> includes a trench conductor, to be referred as the third level metal interconnect layer, but is not limited thereto.

Also, each of the metal interconnections <NUM>, <NUM>, <NUM> may further include a barrier layer (not shown in the drawings) and a metal layer (not shown in the drawings) which are sequentially deposited in the trenches or the via, in which the barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). The metal layer preferably includes copper, but is not limited thereto. On the other hand, the material of the plugs <NUM> may be selected from the group consisting of tungsten, copper, aluminum, titanium aluminide, and cobalt tungsten phosphide, and preferably, the material of the plugs <NUM> may be different from that of the metal layer, but is not limited thereto. In the present embodiment, the inter-metal dielectric layers <NUM>, <NUM> preferably include a dielectric material with ultra-low dielectric constant, the inter-metal dielectric layer <NUM> preferably includes tetraethyl orthosilicate (TEOS), and the stop layers <NUM>, <NUM>, <NUM> preferably include nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or a combination thereof.

Next, in the present embodiment, each of the MTJ structures <NUM> and each of the dummy MTJ structures <NUM> may respectively include a bottom electrode <NUM>, <NUM>, a top electrode <NUM>, <NUM>, a MTJ stack <NUM>, <NUM> and a spacer <NUM>, <NUM>. Specifically, each bottom electrode <NUM>, <NUM> of the MTJ structures <NUM> and the dummy MTJ structures <NUM> is disposed on the plugs <NUM> or on the inter-metal dielectric layer <NUM>, and each MTJ stack <NUM>, <NUM> and each top electrode <NUM>, <NUM> are sequentially stacked on each bottom electrode <NUM>, <NUM>, with each spacer <NUM>, <NUM> entirely covering the sidewall and the top surface of the top electrode <NUM>, <NUM>, the MTJ stack <NUM>, <NUM> and the bottom electrode <NUM>, <NUM>. The spacer <NUM>, <NUM> may further extend to the inter-metal dielectric layer <NUM>, and cover a portion of the sidewall of the plugs <NUM> and the metal interconnections <NUM>, as shown in <FIG> and <FIG>. Preferably, each of the MTJ structures <NUM> and each of the dummy MTJ structures <NUM> include a fixed layer 355a, 365a, a barrier layer 355b, 365b, and a free layer 355c, 365c stacked from bottom to top. The bottom electrodes <NUM>, <NUM> and top electrodes <NUM>, <NUM> preferably include a conductive material including but not limited to for example Ta, Pt, Cu, Au, Al, or a combination thereof. The fixed layer 355a, 365a may include an antiferromagnetic (AFM) material including but not limited to for example ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), or a combination thereof, in which the fixed layer 355a, 365a is formed to fix or limit the direction of magnetic moment of adjacent layers. The barrier layer 355b, 365b may include an insulating material including but not limited to for example oxides such as aluminum oxide (AlOx) or magnesium oxide (MgO). The free layer 355c, 365c may include a ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB). The spacers <NUM>, <NUM> may include a dielectric material including but not limited to silicon nitride.

It is noted that, if viewed from the cross-sectional views according to <FIG>, each of the MTJ structures <NUM>, each of the dummy MTJ structures <NUM>, and the third level metal interconnect layer (for example including the metal interconnections <NUM>) are preferably all disposed in the inter-metal dielectric layer <NUM>, and the plugs <NUM> and the second level via conductor layer (for example including the metal interconnections <NUM>) are preferably both disposed in the inter-metal dielectric layer <NUM>, wherein, each of the MTJ structures <NUM> is disposed directly above the plugs <NUM>, with the stop layer <NUM> further covering the top of the MTJ structure <NUM>. On the other hand, the dummy MTJs such as the dummy MTJ structure 360a as shown at the left side of <FIG> may be disposed directly above the plugs <NUM>, or the dummy MTJs such as the dummy MTJ structure 360b as shown at the right side of <FIG> may also be disposed directly above the inter-metal dielectric layer <NUM> without in contact with any metal interconnection, wherein the top of the dummy MTJ structure <NUM> (including the dummy MTJ structures 360a, 360b) is covered by the metal interconnections <NUM>. In one embodiment, the dummy MTJ structures 360a and the dummy MTJ structures 360b may be alternately arranged along a direction such as the direction along the cross lines B-B' as shown in <FIG>, but is not limited thereto. In another embodiment, the dummy MTJ structures 360a and the dummy MTJ structures 360b may also be arranged in different arrangements for example only arranging the dummy MTJ structures 360a or only arranging the dummy MTJ structures 360b, but not limited thereto. Since a portion of the inter-metal dielectric layer <NUM> and a portion of the spacer <NUM> may be both etched while forming the metal interconnections <NUM>, the metal interconnections <NUM> directly contact the top electrode <NUM> of each dummy MTJ structure 360a, and then directly conduct with the metal interconnections <NUM> underneath through the metal interconnections <NUM> and/or the plugs <NUM>, thereby leading to the short circuit of MTJ structures.

It is also noted that, the etching degree of the spacers <NUM> may be adjustable according to practical product requirements, during the formation of the metal interconnections <NUM>. For example, in one embodiment, the portion of each spacer <NUM> covered on each top electrode <NUM> may be completely removed while performing the etching process, and another portion of each spacer <NUM> covered on the sidewall of each MTJ stack <NUM> and each bottom electrodes <NUM> may be partially removed without directly exposing the MTJ stack <NUM> or the bottom electrode <NUM>. Accordingly, each of the spacers <NUM> may be etched to form a stepped structure, thereby exposing the top electrode <NUM> of each of the dummy MTJ structures <NUM>. Then, the metal interconnections <NUM> disposed over the dummy MTJ structures <NUM> directly contact the top electrode <NUM> as shown in <FIG>. In one embodiment, each of the spacers <NUM> of the dummy MTJ structures 360a surrounds the sidewall of the MTJ stack <NUM>, the bottom electrode <NUM>, and a portion of the plug <NUM> disposed underneath, and each of the spacers <NUM> of the dummy MTJ structures 360b surround the MTJ stack <NUM>, the bottom electrode <NUM> and a portion of the inter-metal dielectric layer <NUM>, as shown in <FIG>. However, in another embodiment, the portion of each spacer covered on each top electrode <NUM> and each MTJ stack <NUM> may also be completely removed while performing the etching process, so that, spacers <NUM> disposed only on the bottom electrodes <NUM>, the plugs <NUM>, and/or the inter-metal dielectric layer <NUM> may be formed thereby, as shown in <FIG> and <FIG>. With these arrangements, the top surface of each of the spacers <NUM> may be coplanar with the bottom surface of each MTJ stack <NUM>, and each of the metal interconnections <NUM> disposed on the dummy MTJ structures <NUM> further coat on the top electrode <NUM> and the MTJ stack <NUM>, as shown in <FIG>.

In the semiconductor device <NUM> of the present embodiment, the metal interconnections <NUM> and the plugs <NUM> are respectively disposed above and below the dummy MTJs, so that, the dummy MTJ structures 360a may directly conduct with the metal interconnections <NUM> disposed underneath through the metal interconnections <NUM> and/or the plugs <NUM>, thereby leading to the short circuit of the dummy MTJs. On the other hand, the dummy MTJ structure 360b may be directly disposed on the inter-metal dielectric layer <NUM>, to lead to the open circuit of dummy MTJs. Accordingly, dummy MTJs with novel structures such as including the dummy MTJ structures 360a or the dummy MTJ structures 360b may be provided, and the aforementioned dummy MTJs may be directly disposed within a login region of a general MRAM device such as the logic region <NUM> of the aforementioned first embodiment, with the short circuit or the open circuit of the aforementioned dummy MTJs being caused by the interconnections disposed within the logic region. Then, the semiconductor device <NUM> of the present embodiment may integrate the logic region and the dummy MRAM region of the general MRAM device, to simplify the layout pattern of the semiconductor device <NUM>.

Claim 1:
A semiconductor device (<NUM>), comprising:
a substrate (<NUM>);
a first dielectric layer (<NUM>) disposed on the substrate (<NUM>), the first dielectric layer (<NUM>) further disposed around a first metal interconnection (<NUM>);
a second dielectric layer (<NUM>) disposed on the first dielectric layer (<NUM>), the second dielectric layer (<NUM>) further disposed around a via (<NUM>)
and a second metal interconnection (<NUM>), the second metal interconnection directly contacting the first metal interconnection (<NUM>); and
a third dielectric layer (<NUM>) disposed on the second dielectric layer (<NUM>), the third dielectric layer (<NUM>) further disposed around a first magnetic tunneling junction, MTJ, structure (<NUM>) and a third metal interconnection (<NUM>), characterized in that the via (<NUM>) and the second metal interconnection (<NUM>) respectively contact the first MTJ structure (<NUM>) and the third metal interconnection (<NUM>), and in that the third metal interconnection (<NUM>) directly contacts the first MTJ structure (<NUM>).