Patent Description:
Memory repair is necessary to correct faults contained within memory structures, which can be present from manufacturing defects or can develop over time in operation. In some applications, a repair control system (RCS) is used to swap a determined faulty memory element with a suitable spare memory element. An example of a RCS could be a Built-in Signature Register (BISR). RCSs operate with a specific repair interface that controls chronologically how memory repairs are implemented across the serviced components. The repair interface used by any given device is dependent on many factors, and can differ between manufacturers and designers.

Repair interfaces are available in both parallel and serial formats. In a parallel interface, multiple spare memory elements can be exchanged directly for faulty elements by the RCS. This can be performed in various ways, to include a column based exchange, a row based exchange, or a combination of both. In a serial interface, there are multiple unique components to each memory that must be sequenced correctly by the RCS to effect a repair. This means that in a serial repair interface the RCS must usually effect a repair one memory structure at a time.

Repair sharing is a method in which similar memory structures are assigned the same RCS to effect repairs. This method assumes that if any one memory of a given set is determined to be faulty, that all memories of the group must be repaired regardless of their individual fault status. Repair sharing reduces the overall physical footprint of a RCS as the number of bits required to construct a system capable of scanning each individual memory may be prohibitively high from a functional or business perspective.

<CIT> describes an error injection system of a built-in self-repairable memory system renders the redundant spare columns of the repairable memory accessible to built-in self-test (BIST) read and write operations. <CIT> describes a communication interface device, system, method, and design structure for bit shadowing in a memory system. <CIT> describes a memory repair mechanism for memories clustered across multiple power domains and can be switched on and off independent of each other. <CIT> describes a system for repairing embedded memories on an
integrated circuit. <CIT> describes a BISR scheme which provides that fuse blocks are shared between memories to reduce hard-BISR implementation costs.

This specification describes systems and techniques for implementing repair sharing in a serial self-repair interface according to independent claims <NUM>, <NUM> and <NUM>. Further preferred embodiments are defined in their dependent claims.

In a serial self-repair interface, there are sequential elements that need to be programmed via a serial interface (e.g. CLK, SI, EN, RST, or SO) which controls the selection of redundant elements. Repairing in this type of interface usually occurs one memory structure at a time, with the serial self-repair interface repairing each component of the memory structure in succession. Repair sharing in serial self-repair interfaces cannot follow the same process as parallel interfaces due to the need to sequence the repair of the individual components of each memory. However, there would still be benefits to introducing repair sharing to a serial self-repair interface. For example, these techniques can effectuate an overall footprint reduction and have additional benefits to the system. One example solution is a memory BISR sharing structure (MBSS). The MBSS can have multiple different functional areas, and, in one example, these areas include a shadow BISR chain, fault identification, fault diagnostic, and fault reinjection areas. Other implementations of a similar system may choose to have more, or less, functional areas.

The shadow BISR chain in this example identifies multiple memories for which repair sharing is to be performed. The process of selecting compatible memories can depend on multiple factors, to include processing type or capability, fault density, failure rate, or guidance from the manufacturer. Once suitable memories have been identified, one of the memories in the group is designated the 'main' memory, while all other memories are designated the 'shadow' memories. There is no limit to how many shadow memories can be designated in this manner.

Once suitable memories are grouped and designated, a scan-in signal is sent to the main memory. The MBSS in this example also sends the same scan-in signal to all of the shadow memories in parallel. In this example, a singular logical result, for example 'high' or 'low', is obtained for all of the shadow memories. This is obtained through the logic structure of the fault identification functional area, which in some examples includes a comparator. Additionally, this singular shadow memory scan-out is combined with the main memory scan-out through the fault reinjection functional area, in some examples through the use of a multiplexer, such that either a fault in serial repair RCS infrastructure, from the main memory or the overall shadow memory fault logic will trigger a failure for all memories, main and shadow. This signal is transmitted as one final 'scan-out' signal sent to the external repair infrastructure.

In this example, the MBSS is designed such that the external repair infrastructure needs to send only one input, and in return, receives only one output. One of the advantages of this process in this format is that it does not require any changes to the external serial repair infrastructure, as the external devices continue to 'see' their expected inputs and outputs for a single memory, in essence, one repair signal. The end result is that the MBSS can be utilized with a variety of serial repair infrastructures without changes to those devices.

Implementing the example system or a similar design allows an overall reduction in One-Time Programmable (OTP) memory. This results in a lower physical system footprint for repairing infrastructure. Additionally, the reduced repair chain length of this system can result in improved system boot up times or BISR reloading times. Also achieved is a reduction in the max chain length and the total BISR bits required. Finally, because the MBSS in this example is configured to work with existing serial repair interfaces, it does not require any changes to external hardware or software to implement.

<FIG> is a diagram of a device <NUM> communicatively coupled to two, or more, memory devices <NUM> and 120a-c. The device <NUM> has a comparator <NUM>, a fault reinjection system <NUM>, and a fault detection system <NUM>. The device <NUM> can be installed on or integrated into any appropriate computing device, which may be referred to as a host device.

The device <NUM> services multiple similar memory structures, for example <NUM> and 120a-c. Each of the memory structures can have serial self-repair interfaces. One of these memory structures <NUM> can act as a main memory while all other memories act as the shadow memories 120a-c. The device <NUM> is not limited to a certain number of memories, and can be configured to function with any given number of memory words or addresses. The device <NUM> can be designed such that it communicates with external memory test controllers which are allowed to view the contained virtual memories.

To repair the memories associated with the device <NUM>, a scan-in (RSCIN) <NUM> is broadcast by using serial self-repair interfaces of the memories beginning with the main memory <NUM>. The same RSCIN <NUM> from the the serial self-repair interface is also applied to each of the shadow memories 120a-c in parallel. The result of the scan for the main memory <NUM> is then scanned out to the fault reinjection system <NUM>. The results of the scan for all memories, main <NUM> and shadow 120a-c, are scanned out to the comparator <NUM>.

The comparator <NUM> includes a certain number (N) of exclusive OR (XOR) gates 132a-b that receive the scan out from the memories <NUM> and 120a-c. Upon receiving a mismatched scan out from the memories <NUM> or 120a-c, the comparator passes this high scan out to the fault reinjection system <NUM>. The logic in the comparator is such that one XOR gate 132a-b is assigned to two memory structures, or two downstream XOR gates. There is no limit to how many XOR gates 132a-b are used in this fashion, provided that each XOR gate has two inputs and only one output. A mistmached scan out triggered by a faulty RCS path of memory will result in a high signal to its associated XOR gates. When a XOR gate receives differing input, one high and one low, from both of its associated memories, or downstream XOR gates, that XOR gate then passes a high signal to the next component, whether that is another XOR gate or the fault reinjection system <NUM>. If the XOR gate receives a high or low signal from both of its associated memories or downstream XOR gates, the resulting output is low.

The comparator also sends any high scan-out received to the sticky flops 152a-b in the fault detection system <NUM>. The fault detection system <NUM> can include multiple sticky flops 152a-b that activate a high signal upon sensing a mismatch indicated by the output of the comparator <NUM>. This is then stored in the sticky flops 152a-b. The sticky flops 152a-b are then unloaded at the end of the test vector via a test data register (TDR) <NUM>. The TDR <NUM> can then be used to indicate which memory triggered the failure and contains the faulty RCS infrastructure.

The fault reinjection system <NUM> includes a certain number (2N) of OR gates <NUM>, an AND gate <NUM> that combines output from the OR gates <NUM> and shadow fault detection <NUM>, and a multiplexer (MUX) <NUM>. There is no limit to how many OR gates <NUM> are used in this fashion, provided that the ratio of OR gates <NUM> in the fault reinjection system <NUM> to the number of XOR gates 132a-b in the comparator <NUM> is two-to-one (2N/N), and each OR gate <NUM> has two inputs and only one output. Upon receiving a high signal from either of the downstream XOR gates 132a-b, or downstream OR gates, the OR gate <NUM> passes a high signal to the AND gate <NUM>. The OR gate <NUM> will also pass a high signal to the next component in the event that both downstream XOR gates 132a-b, or OR gates, send high signals. The AND gate <NUM> receives input from the OR gate <NUM> and shadow fault detection <NUM>. If shadow fault detection <NUM> is enabled, this input will be high. With shadow fault detection <NUM> disabled, this input is low. If both the OR gate <NUM> and shadow fault detection <NUM> send high signals, the AND gate <NUM> passes a high signal to the multiplexer <NUM>. If the AND gate receives mixed signals, one high and one low, or two low signals, a low signal is passed to the multiplexer <NUM>.

The fault reinjection feature is disabled in order to determine the fault status of only the main memory <NUM> RCS. Relatedly, the fault reinjection feature is enabled to check shadow memories 120a-c. Upon receiving a high signal from the AND gate <NUM> the multiplexer <NUM> selects the path with the inverter <NUM> and flips the scan out from the main chain and sends as (RSCOUT) <NUM> back to the serial self-repair interface. This inversion of main memory RSCOUT creates a bit flip in the data stream which gets identified as a fault in the shadow memory.

<FIG> illustrate several examples of memory structures of different word and address lengths that could be serviced by the device <NUM>. These examples are not meant to be an exhaustive list. <FIG> illustrates a memory structure that has one word and three addresses. <FIG> illustrates a memory structure that has three words and one address. <FIG> illustrates a memory that has two words and two addresses. Referring to the example of <FIG>, in some implementations memories 210a and 210b together share the same word, as do memories 210c and 210d. Additionally, memories 210a and 210c together share the same address, as do memories 210b and 210d. The device <NUM> does not have a limit to how many different memory words or addresses can be serviced.

<FIG> illustrates a detailed view of a fault re-injection system <NUM>, comparator <NUM>, and fault detection system <NUM>. The function of the major components of this system <NUM> is similar to the functions of system <NUM> as described for <FIG>. This system <NUM> has been illustrated to show additional XOR gates <NUM> in the comparator <NUM>, as well as additional sticky flops <NUM> in the fault detection system <NUM>, for added clarity on the logical structure of the comparator and the integration of the fault detection system within the output of the comparator, respectively. In the fault re-injection system <NUM>, the 2N OR gate <NUM> is a simplification of the logic needed for this representative example, including four XOR gates <NUM> servicing four memories. The 2N OR gate <NUM> could be constructed of any logic gates such that the final logical truth table would be such that the output is high for any high input received.

<FIG> illustrates an example process for checking faults on a component serviced by the system. Other examples of this process could use a different order for checking faults, or have more, or less, steps.

The first step in this example process disables fault reinjection (<NUM>). This is done such that the RCS fault status of the main memory can be determined, separate of the fault status of any of the shadow memories. In some embodiments, the fault reinjection must be disabled in order for the output of the multiplexer to be independent of the logical output of the shadow memories' comparator. By disabling fault reinjection in this example embodiment, the shadow memories' AND gate in the fault reinjection system will always receive one low input, and as such its output to the multiplexer will always be the data stream from main memory. In this way, only a fault with the main memory can cause a failure.

After disabling fault reinjection, a main self-repair chain test is then performed (<NUM>). This chain test outputs any faults associated with the main memory RCS only. These output faults are indicated as Main memory faults <NUM>. In some embodiments, the fault status of the shadow memories RCS is ignored by the fault reinjection system in this case.

Following a main self-repair test, fault reinjection is enabled (<NUM>). This sends one high signal to the shadow memories' AND gate in the fault reinjection system. In some embodiments this is done such that when combined with a high signal from the shadow memories' comparator, the output of the AND gate to the multiplexer is a high signal. This ultimately triggers a bit flip via inverter <NUM> into the data stream in case of a mismatch flagged by the comparator resulting in fault indication.

One or more shadow self-repair chain tests are then performed (<NUM>). These chain tests output any faults that are associated with the one or more shadow memories. These output faults are indicated as Shadow memory faults <NUM>. By performing this test after a successful main self-repair chain test (step <NUM>), any faults can then be isolated to the shadow memories RCS.

A computer program which may also be referred to or described as a program, software, a software application, an app, a module, a software module, a script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

Claim 1:
A device (<NUM>) comprising:
a plurality of memory devices each having a serial self-repair interface, one of the memory devices acting as a main memory (<NUM>) and all other memory devices acting as shadow memories (120a-c); and
a sharing structure comprising logic circuitry for inputting a same set of self-repair data to each of the plurality of memory devices and receiving self-repair outputs from the plurality of memory devices,
wherein the sharing structure comprises fault identification logic configured to detect mismatches between the self-repair outputs of the plurality of memory devices,
the fault identification logic comprises a plurality of XOR gates (132a-b) configured to compare self-repair outputs from respective pairs of the plurality of memory devices, and
the fault identification logic comprises an N-input OR gate (<NUM>) having a number of inputs equal to the number of XOR gates (132a-b).