Patent Description:
Laser based optical probing techniques are commonly used in failure analysis of an integrated circuit (IC) or semiconductor device that has failed. These techniques, however have not been able to measure direct current (DC) electrical parameters such as DC voltage and current levels. Also, laser based optical probing techniques are unable to detect alternating current (AC) electrical parameters that operate at a frequency below a predetermined minimum frequency FMIN, which, together with the inability to detect DC parameters, limited these techniques mostly to the digital IC domain for measuring internal nodes that carry or convey alternating electrical parameters at or above FMIN. In the analog domain, constant or low frequency alternating electrical parameters are more common. Up until now, micro-probing techniques have been required to accurately measure these constant or low frequency alternating electrical parameters. Micro-probing techniques required sample-preparation with, for example, Focused Ion Beam (FIB) and also required direct contact with the internal node to be measured. The direct contact of the IC by a probe-needle presents a significant risk of damaging the semiconductor device. Other than the risk of permanent damage, direct contact with a probe-needle often affects the measured parameters potentially resulting in less accurate or even erroneous results.

<CIT> discloses a method of measuring the transistor leakage current. In one embodiment, the method involves driving a ring oscillator with a dynamic node driver having a leakage test device biased to an off state to produce a test signal. The test signal is extracted and the frequency is measured. The leakage current is estimated from the measured frequency.

According to an aspect, there is provided an integrated circuit block according to claim <NUM>. Further features according to embodiments are set out in the dependent claims.

Embodiments of the present invention are illustrated by way of example and are not limited by the accompanying figures. Similar references in the figures may indicate similar elements.

The inventors have recognized that standard laser based optical probing techniques are not adequate for measuring DC electrical parameters or low frequency AC electrical parameters of an integrated circuit (IC) or semiconductor device. They have also recognized the deficiencies and risks of micro-probing techniques that have been used for measuring such parameters. The term "electrical parameter" in general refers to any electrical signal, value, or variable that is developed on the IC or semiconductor device when powered, such as electrical current, electrical voltage, alternating electrical signals, etc. As used herein, a "low frequency electrical parameter" includes any DC electrical parameter or any AC electrical parameter that varies or alternates at a frequency below a predetermined minimum frequency level FMIN. As used herein, a "high frequency electrical parameter" includes any electrical parameter that varies or alternates at a frequency at or above FMIN for detection using laser based optical probing techniques. FMIN is a minimum frequency level that is detectable by a laser voltage probe system. In particular, a laser beam focuses on a point within a laser probe area carrying an electrical signal alternating at or above FMIN is modulated and detectable by the laser voltage probe system.

Given the deficiencies of conventional configurations, the inventors have therefore developed an integrated laser voltage probe pad provided on an IC or semiconductor device that enables measuring such low frequency electrical parameters (including DC parameters) using laser based optical probing techniques. A converter circuit is coupled to a sense node that contains or otherwise carries the low frequency electrical parameter, in which the converter circuit converts the low frequency electrical parameter into high frequency electrical parameter that alternates at a frequency at or above FMIN. The converter may include, for example, a ring oscillator, a switch circuit energized by a high frequency clock signal, a capacitor having a charge rate that is based on the level of the low frequency electrical parameter, etc. The converter circuit also includes a laser probe area that is energized by the high frequency electrical parameter such that it modulates the reflected laser beam from an incident laser beam focused on a point within the laser probe area for detection by a laser voltage probe test system. The integrated laser voltage probe pad, therefore, enables measurement of low frequency electrical parameters (including DC parameters) by the laser voltage probe test system.

<FIG> is a simplified block diagram of a laser voltage probe (LVP) test system <NUM> used to test an integrated circuit (IC) or semiconductor device, such as a device under test (DUT) <NUM>, which includes a converter <NUM> for converting a low frequency electrical parameter to a high frequency electrical parameter that it is detectable by the LVP test system <NUM>. The LVP test system <NUM> includes a laser <NUM> that provides a laser beam <NUM> focused on a selected active region of the DUT <NUM>. The laser beam <NUM> passes through a beam splitter <NUM> and an objective lens <NUM> which focuses the laser beam <NUM> on an active region of the DUT <NUM>. The illustrated active region is a laser probe area <NUM> located on the substrate of the DUT <NUM>. Although not specifically shown, the laser beam <NUM> passes through the substrate and the laser probe area <NUM>, reflects off interfaces between layers located at the laser probe area <NUM>, and passes back through the laser probe area <NUM> and the substrate as a reflected laser beam <NUM>. The reflected laser beam <NUM> returns back through the objective lens <NUM> and is guided by the beam splitter <NUM> into a detector <NUM>. The detector <NUM> generates an output signal <NUM> that correlates to an electric field generated at the laser probe area <NUM>, in which the output signal <NUM> is provided to an input of a display device <NUM> under control of test equipment <NUM>. The display device <NUM> may be a digital sampling oscilloscope or a frequency analyzer or the like. It is noted that a laser beam is focused on a point within a specified laser probe area identified in the figures suitable to modulate the laser beam, which may not include every possible point within the indicated probe area shown in the figures.

The DUT <NUM> is "active" in that it is powered and operating in a selected normal operating mode or a selected test mode. Under such powered conditions, the DUT <NUM> develops many active regions including, for example, the laser probe area <NUM>. The active regions develop an electric field which modulates the reflected laser beam <NUM>, and the detector <NUM> detects the laser modulations attributed to the electric field to generate the output signal <NUM>. In this manner, the output signal <NUM> reflects one or more electrical parameters of the electric signal generated at the laser probe area <NUM>. The laser probe area <NUM> develops or otherwise contains a current or voltage signal that alternates at or above a predetermined minimum frequency level FMIN in order to modulate the laser beam. FMIN may be relatively high, such as <NUM> kilohertz (kHz) or greater. The LVP test system <NUM> may be operated at a higher minimum frequency level above FMIN, such as <NUM> or the like. Such a relatively high frequency level, however, precludes the ability to directly detect locations on the DUT <NUM> which are operating at a constant level or at a relatively low frequency level (e.g., below <NUM>).

It is desired, for example, to detect a low frequency electrical parameter (including a DC parameter) associated with a sense node <NUM> which is part of the functional circuit <NUM> of the DUT <NUM>. It is noted that the term "functional circuit" is intended to include any number of analog or digital circuits integrated on a semiconductor device or IC performing functional or test operations when the device or IC is powered. The electrical parameter at the sense node <NUM>, which may be either a voltage or a current or the like, is either a constant value or is alternating below FMIN so that it is not directly detectable by the LVP test system <NUM>. Thus, the converter <NUM> is implemented (or integrated) onto the substrate of the DUT <NUM> along with a sense circuit <NUM> used to convey the electrical parameter to the converter <NUM>. When the electrical parameter is a constant or low frequency voltage, the sense circuit <NUM> may simply be an electrical conductor that conveys the voltage to the converter <NUM>. When the electrical parameter is a constant or low frequency current, the sense circuit <NUM> may be or may otherwise include a current mirror branch or the like that develops the current within the converter <NUM>. The converter <NUM> converts the low frequency electrical parameter to a high frequency electrical parameter at the laser probe area <NUM> having a frequency level that is above FMIN so that it is detectable by the LVP test system <NUM>. As described further herein, the frequency or other characteristic of the electrical signal at the laser probe area <NUM> is indicative of the value of the low frequency electrical parameter at the sense node <NUM>, which value is incorporated into the reflected laser signal <NUM> provided to the detector <NUM>. In this manner, the output signal <NUM> is indicative of the value of the low frequency electrical parameter at the sense node <NUM>.

The converter <NUM> is representative of one or more such converters implemented on the DUT <NUM> as further described herein. During normal operation of the DUT <NUM>, the converter <NUM> may be disabled or at least configured to consume only a negligible amount of power in order to optimize performance of the functional circuit <NUM>. A laser probe support (LPS) circuit <NUM> is included to provide one or more enable signals LVP_EN<> to enable or otherwise activate the converter <NUM> for testing by the LVP test system <NUM>. An LVP enable circuit <NUM> is provided to enable the LPS circuit <NUM> as further described herein.

<FIG> is a schematic diagram of a DUT <NUM> illustrating the DUT <NUM> implemented according to one embodiment of the present invention using a ring oscillator <NUM> for converting a DC or low frequency current into a higher frequency signal at or above FMIN. The DUT <NUM> includes a portion of a functional circuit <NUM> further including a sense node <NUM> illustrating a more specific configuration of a small portion of the functional circuit <NUM> and the sense node <NUM> of the DUT <NUM>. In this case, the sense node <NUM> is, or is otherwise part of, an electrical conductor through which a current IIN flows when the DUT <NUM> is powered. The current IIN is shown flowing into a drain terminal of an N-type (or N-channel) MOS (NMOS) transistor N1 as part of the functional circuit <NUM>. N1 is diode-connected having its drain terminal connected to its gate terminal, and further has a source terminal coupled to a reference supply voltage level, such as ground (GND). The electrical current IIN is a low frequency electrical parameter that is either constant or alternates at a relatively low frequency level below FMIN. Nonetheless, it is desired to detect the value of IIN using the LVP test system <NUM>, which can only detect high frequency electrical parameters that alternate at or above FMIN. The DUT <NUM> further includes a sense circuit <NUM> illustrating an embodiment of the sense circuit <NUM> for detecting IIN. The sense circuit <NUM> includes another NMOS transistor N2, having a gate terminal coupled to the gate and drain terminals of N1, and having a source terminal coupled to a reference supply voltage level, such as GND. In this manner, N2 is added and coupled to N1 into a current mirror configuration in which a mirrored current IM flows into the drain terminal of N2 having a current level equal to or otherwise proportional to IIN.

It is noted that N1 is depicted as a portion of a current mirror that is already a part of the underlying functional circuit, in which additional current branches (not shown) may be included for mirroring IIN into other portions of the functional circuit <NUM>. In this case, N2 is an added current mirror branch for developing IM based on IIN. N2 may be implemented to have the same size as N1 so that IM is substantially equal to IIN, or N2 may be sized at a multiple of the size of N1 to adjust the magnitude of IM relative to IIN. In functional circuit configurations in which IIN is not already configured to flow into a current mirror branch (e.g., N1 or the like is not already provided), then the sense circuit <NUM> incorporates additional devices, such as N1, for implementing a current mirror to develop the mirrored current (e.g., IM).

The sense circuit <NUM> further includes an electrical conductor <NUM>, such as a conductive trace or the like, to convey IM to a converter <NUM>. The converter <NUM> is a more specific embodiment of the converter <NUM>. In this case the converter <NUM> includes the ring oscillator <NUM> configured with three (or any odd number of) inverters I1, I2, and I3 coupled in series and a feedback node <NUM> coupled between its input and output developing an alternating voltage VAC. As shown, for example, the output of I1 is coupled to the input of I2, having its output coupled to the input of I3, having its output fed back to the input of I1 via the feedback node <NUM>. Any one of the inverters I1 - I3 includes a PN junction serving as a laser probe area <NUM> implementing the laser probe area <NUM>. Each of the inverters I1 - I3 has a lower supply voltage terminal coupled to the electrical conductor <NUM>, and an upper supply voltage terminal coupled to a supply enable <NUM>. The supply enable <NUM> receives a VDD enable signal VDDEN from a laser probe support (LPS) circuit <NUM> implementing an embodiment of the LPS circuit <NUM>. In one embodiment, the supply enable <NUM> is a node receiving VDDEN as a supply voltage VDD from the LPS circuit <NUM> which supplies VDD to enable the converter <NUM>. In another embodiment, the supply enable <NUM> is a switch coupled between the supply voltage VDD and the upper supply voltage terminals of the inverters of the ring oscillator <NUM>, in which the LPS circuit <NUM> asserts VDDEN as a logic signal that closes the switch to couple VDD to the converter <NUM>.

In operation, the LPS circuit <NUM> may assert VDDEN to an appropriate level (e.g., low) to disable or turn off the converter <NUM>. When disabled, the converter <NUM> does not affect operation of the functional circuit <NUM>. When the LPS circuit <NUM> asserts VDDEN to an appropriate enable level (e.g., high), then the converter <NUM> is activated and the ring oscillator <NUM> oscillates VAC at a frequency based on the delay of each of the inverters I1 - I3, in which the delay of each of the inverters I1 - I3 is further based on the current level of IM. The inverter delay is relatively short even for relatively low values of IM, so that the frequency of oscillation of VAC is relatively high and well above FMIN. The current level of IM is based on the current level of IIN because of the current mirror configuration. When the laser beam <NUM> is focused on the laser probe area <NUM> (e.g., any PN junction of any of the inverters I1 - I3), then the reflected laser beam <NUM> is modulated based on the frequency of the ring oscillator <NUM> and thus VAC, so that the output signal <NUM> displayed on the display device <NUM> has a frequency level within a frequency range at or above FMIN, in which the specific frequency level is based on the current level of IIN. In this manner, IIN is converted to an oscillating or alternating signal VAC having a frequency at or above FMIN with a specific frequency based on the current level of IIN, so that the current level of IIN may be measured by the test equipment <NUM>.

<FIG> is a schematic diagram of a DUT <NUM> illustrating the DUT <NUM> implemented according to another embodiment of the present invention using a ring oscillator <NUM> for converting a DC or low frequency current into a higher frequency signal at or above FMIN. The DUT <NUM> is similar to the DUT <NUM> and includes a similar portion of a functional circuit <NUM> which further includes a sense node <NUM> illustrating another embodiment of a small portion of the functional circuit <NUM> and the sense node <NUM> of the DUT <NUM>. In a similar manner as with the DUT <NUM>, the sense node <NUM> is, or is otherwise part of, an electrical conductor through which a current IIN flows when the DUT <NUM> is powered. Again, the electrical current IIN is a low frequency electrical parameter that is either constant or varies at a relatively low frequency level below FMIN, and it is desired to detect the value of IIN using the LVP test system <NUM>, which can only detect electrical parameters that alternate at a frequency at or above FMIN.

The DUT <NUM> further includes a sense circuit <NUM> illustrating an embodiment of the sense circuit <NUM> for detecting IIN. In this case, the functional circuit <NUM> develops the IIN current to flow out of a drain terminal of a P-type (or P-channel) MOS (PMOS) transistor P1 as part of a mirror circuit (not shown). P1 is diode-connected having its drain terminal connected to its gate terminal, and P1 further has a source terminal coupled to the supply voltage VDD. The sense circuit <NUM> includes a PMOS transistor P2, having a gate terminal coupled to the gate and drain terminals of P1, and having a source terminal coupled to VDD. In this manner, P2 is coupled to P1 to form a current mirror configuration in which a mirrored current IM flows out of the drain terminal of P2 having a current level equal to or otherwise proportional to IIN. Additional current branches (not shown) may be included for mirroring IIN into other portions of the functional circuit <NUM>, in which P2 is an added current mirror branch for developing IM. P2 may be implemented to have the same size as P1 so that IM is substantially equal to IIN, or P2 may be sized relative to P1 to adjust the magnitude of IM relative to IIN. In a similar manner as previously described for N1 and N2 of the DUT <NUM>, if P1 is not otherwise provided in the functional circuit <NUM> forming a branch of the mirror circuit, then the added sense circuit <NUM> includes P1 and P2 (and any other support devices) to develop the mirror current IM.

The sense circuit <NUM> further includes an electrical conductor <NUM>, such as a conductive trace or the like, that conveys IM to a converter <NUM> (implementing the converter <NUM>). The converter <NUM> is substantially similar to the converter <NUM>, including a ring oscillator <NUM> configured with three (or any odd number of) similar inverters I1, I2, and I3 coupled in series with a feedback node <NUM> developing an alternating voltage VAC coupled between its input and output in a similar manner previously described for the ring oscillator <NUM>. Any one of the inverters I1 - I3 includes a PN junction serving as a laser probe area <NUM> implementing the laser probe area <NUM>. Each of the inverters I1 - I3 has an upper supply voltage terminal coupled to the electrical conductor <NUM>, and a lower supply voltage terminal coupled to a supply enable <NUM>. The supply enable <NUM> receives a ground enable signal GNDEN from a laser probe support (LPS) circuit <NUM> implementing an embodiment of the LPS circuit <NUM>. In one embodiment, the supply enable <NUM> is a node receiving GNDEN as the GND voltage from the LPS circuit <NUM> which provides GND to enable the converter <NUM>. In another embodiment, the supply enable <NUM> is a switch coupled between GND and the ring oscillator <NUM>, in which the LPS circuit <NUM> asserts GNDEN as a logic signal that closes the switch to couple GND to the converter <NUM>. In either case, GNDEN facilitates coupling of GND to the converter <NUM>.

In operation, the LPS circuit <NUM> may assert GNDEN to an appropriate level (e.g., high) to disable or turn off the converter <NUM>. When disabled, the converter <NUM> does not affect operation of the functional circuit <NUM>. When the LPS circuit <NUM> pulls GNDEN to an appropriate enable level (e.g., low), then the converter <NUM> is activated and the ring oscillator <NUM> oscillates VAC at a frequency based on the delay of each of the inverters I1 - I3, in which the delay of each of the inverters I1 - I3 is further based on the current level of IM. The current level of IM is based on the current level of IIN because of the current mirrored configuration. When the laser beam <NUM> is focused on the laser probe area <NUM> (e.g., any PN junction of any of the inverters I1 - I3), then the reflected laser beam <NUM> is modulated based on the frequency of the ring oscillator <NUM> (and thus VAC), so that the output signal <NUM> displayed on the display device <NUM> has a frequency level within a frequency range at or above FMIN, in which the specific frequency level is based on the current level of IIN. In this manner, IIN is converted to an oscillating or alternating signal VAC having a frequency at or above FMIN with a specific frequency based on the current level of IIN, so that the current level of IIN may be measured by the test equipment <NUM>.

It is appreciated that the current mirror configuration of N1 and N2 of the DUT <NUM> is substantially similar to the current mirror configuration of P1 and P2 of the DUT <NUM> except that one is N-type while the other is P-type. In either case, a current IIN of the underlying functional circuit (<NUM> or <NUM>) is mirrored to provide a mirrored current IM which is used to activate a ring oscillator (<NUM> or <NUM>) within a corresponding converter (<NUM> or <NUM>) to convert IM into an oscillating signal having a frequency at or above FMIN. Although shown and described for different DUTs <NUM> and <NUM>, it is appreciated that both configurations may be implemented on the same IC or semiconductor device (e.g., both on DUT <NUM> or DUT <NUM>).

<FIG> is a graphic diagram plotting the frequency of the VAC signal (FVAC) in Megahertz (MHz) versus the current level of IIN microamperes (µA) for either DUT <NUM> or <NUM> according to one embodiment. The conversion operation for both DUTs <NUM> and <NUM> is substantially the same with only slight variations in numerical values of frequency or current. In either case, the delay of each of the inverters I1 - I3 is relatively small so that the frequency of oscillation of VAC may be well above FMIN even with relatively small values of IIN (reflected as the mirrored current IM). The particular current range of IIN or the particular frequency range of FVAC may be different without departing from the scope of this disclosure. For example, the particular frequency range of FVAC may be significantly less, such as in the kHz range (as long as greater than FMIN), or significantly greater (e.g., in the Gigahertz (GHz) range). Likewise, the particular current range of IIN may be less (e.g., in the nanoampere (nA) range) or more (e.g., in the milliampere (mA) range). In any event, the determined relationship between the FVAC and the corresponding current level of IIN enables measurement of IIN using the LVP test system <NUM>.

<FIG> is a schematic diagram of a DUT <NUM> illustrating the DUT <NUM> implemented according to yet another embodiment of the present invention using a ring oscillator <NUM> for converting a DC or low frequency voltage into a higher frequency signal at or above FMIN. The DUT <NUM> also includes a portion of a functional circuit <NUM> further including a sense node <NUM> illustrating another embodiment of a small portion of the functional circuit <NUM> and the sense node <NUM> of the DUT <NUM>. In this case, the sense node <NUM> develops an input voltage VIN when the DUT <NUM> is powered. The electrical voltage VIN is a low frequency electrical parameter that is either constant or varies at a relatively low frequency level below FMIN, and it is desired to detect the value of VIN using the LVP test system <NUM>, which can only detect electrical parameters that alternate at a frequency at or above FMIN. The DUT <NUM> further includes a sense circuit <NUM> for conveying VIN to an input of a converter <NUM> implementing an embodiment of the converter <NUM>. In this case, the sense circuit <NUM> may simply be an electrical conductor <NUM> which is coupled between the sense node <NUM> and the converter <NUM>.

The converter <NUM>, which is similar to the converter <NUM>, includes the ring oscillator <NUM> configured with three (or any odd number of) similar inverters I1, I2, and I3 coupled in series with a feedback node <NUM> coupled between its input and output which develops an alternating voltage VAC in a similar manner previously described for the ring oscillator <NUM>. Any one of the inverters I1 - I3 includes a PN junction serving as a laser probe area <NUM> implementing an embodiment of the laser probe area <NUM>. Each of the inverters I1 - I3 has an upper supply voltage terminal which may be coupled to a first supply enable <NUM>. In this case for sensing VIN, each of the inverters I1 - I3 has a lower supply voltage terminal coupled to a drain terminal of an NMOS transistor NA, having its source terminal coupled to a second supply enable <NUM> and a gate terminal coupled to the electrical conductor <NUM> for receiving VIN. NA is used for converting voltage to current, in which it is understood that other types of transistors are contemplated, such as a field-effect transistor (FET) or a bipolar transistor or the like, or any other suitable voltage to current conversion device or circuit.

The supply enable <NUM> is shown coupled to VDD and includes an input receiving VDDEN from a laser probe support (LPS) circuit <NUM> implementing an embodiment of the LPS circuit <NUM>, and the supply enable <NUM> is shown coupled to GND and includes an input receiving GNDEN from the LPS circuit <NUM>. The supply enables <NUM> and <NUM>, the signals conveying VDDEN and GNDEN, and the VDD/GND connections are shown using dashed lines representing several different configurations. In a first embodiment, the supply enable <NUM> is simply a conductor or is not provided in which the upper supply voltage inputs of each of the inverters I1 - I3 are coupled directly to VDD and VDDEN is not provided by the LPS circuit <NUM>. In this first case, the supply enable <NUM> is provided and is either a switch for coupling the converter <NUM> to GND when GNDEN is asserted, or is a conductor in which GNDEN itself provides the GND connection. In either case, GNDEN facilitates coupling of GND to the converter <NUM>. In a second embodiment, the supply enable <NUM> is simply a conductor or is not provided in which the source terminal of NA is coupled directly to GND and GNDEN is not provided by the LPS circuit <NUM>. In this second case, the supply enable <NUM> is provided and is either a switch for coupling the converter <NUM> to VDD when VDDEN is asserted, or is a conductor in which VDDEN itself provides the VDD connection. In either case, VDDEN facilitates coupling of VDD to the converter <NUM>. A third embodiment is possible in which both supply enables <NUM> and <NUM> are provided and both enabled or disabled together.

In operation, the LPS circuit <NUM> may assert either one or both GNDEN or VDDEN to an appropriate level to disable or turn off the converter <NUM>. When disabled, the converter <NUM> does not affect operation of the functional circuit <NUM>. When the LPS circuit <NUM> asserts VDDEN or GNDEN (or both) to an appropriate enable level, then the converter <NUM> is activated and the ring oscillator <NUM> oscillates VAC at a frequency based on the voltage level of VIN. The voltage level of VIN controls the drain current of NA which further controls the frequency of oscillation of the ring oscillator <NUM>. It is noted that the size of NA may be selected based on the voltage range of VIN so that the drain current of NA develops at a level similar to the current IM of <FIG>. The ring oscillator <NUM> oscillates VAC at a frequency based on the delay of each of the inverters I1 - I3, in which the delay of each of the inverters I1 - I3 is further based on the drain current level of NA which is further based on the voltage level of VIN. When the laser beam <NUM> is focused on the laser probe area <NUM> (e.g., any PN junction of any of the inverters I1 - I3), then the reflected laser beam <NUM> is modulated based on the frequency of the ring oscillator <NUM> (and thus VAC), so that the output signal <NUM> displayed on the display device <NUM> has a frequency level within a relatively high frequency range, in which the specific frequency level is based on the voltage level of VIN. In this manner, VIN is converted to an oscillating or alternating signal VAC having a relatively high frequency with a specific frequency based on the voltage level of VIN, so that the voltage level of VIN may be measured by the test equipment <NUM>.

<FIG> is a schematic diagram illustrating the DUT <NUM> implemented according to an embodiment of the present invention similar to the DUT <NUM> using a ring oscillator <NUM>, in which the DUT <NUM> also includes a portion of a functional circuit <NUM> including a sense node <NUM> developing an input voltage VIN when the DUT <NUM> is powered. Again, the electrical voltage VIN is a low frequency electrical parameter that is either constant or varies at a relatively low frequency level below FMIN, and it is desired to detect the value of VIN using the LVP test system <NUM>. The DUT <NUM> further includes a sense circuit <NUM> which may simply be an electrical conductor <NUM> coupled between the sense node <NUM> and an input of a converter <NUM> configured in a similar manner as the converter <NUM>. The converter <NUM> is shown coupled between first and second supply enables <NUM> and <NUM> receiving VDDEN and GNDEN from an LPS circuit <NUM> in substantially the same manner as the first and second supply enables <NUM> and <NUM> and the LPS circuit <NUM> described for the DUT <NUM>. Any one of several different configurations and corresponding operations for enabling the converter <NUM> of the DUT <NUM> are substantially the same as that described for the converter <NUM> of the DUT <NUM>. As before, VDDEN facilitates coupling of VDD to the converter <NUM> if not already coupled, and GNDEN facilitates coupling of GND to the converter <NUM> if not already coupled.

The converter <NUM> is similar to the converter <NUM>, except that NA is replaced by a PMOS transistor PA having its source terminal coupled to the supply enable <NUM> (for receiving VDD or any other suitable supply voltage), and its drain terminal coupled to the upper voltage supply terminals of similar inverters I1, I2 and I3 of a similar ring oscillator <NUM>. Similar to NA, in this case PA is used for converting voltage to current, in which it is understood that other types of transistors are contemplated, such as a FET or a bipolar transistor or the like, or any other suitable voltage to current conversion device or circuit. The lower voltage supply terminals of I1 - I3 are coupled to the supply enable <NUM> and the inverters I1 - I3 are coupled together in a ring configuration having a feedback node <NUM> developing VAC in the same manner previously described. Operation of the converter <NUM> is substantially the same as the converter <NUM>, such that when the converter <NUM> is enabled by the LPS circuit <NUM>, the voltage level of VIN determines the drain current through PA which in turns determines the specific frequency of oscillation of the ring oscillator <NUM>. The ring oscillator <NUM> oscillates VAC at a frequency based on the delay of each of the inverters I1 - I3, in which the delay of each of the inverters I1 - I3 is further based on the drain current level of PA which is further based on the voltage level of VIN. Thus, when the laser beam <NUM> is focused on the laser probe area <NUM> (e.g., any PN junction of any of the inverters I1 -I3), then the reflected laser beam <NUM> is modulated based on the frequency of the ring oscillator <NUM> (and thus VAC), so that the output signal <NUM> displayed on the display device <NUM> has a frequency level at or above FMIN in which the specific frequency level is based on the voltage level of VIN. In this manner, VIN is converted to an oscillating or alternating signal VAC having a relatively high frequency with a specific frequency based on the voltage level of VIN, so that the voltage level of VIN may be measured by the test equipment <NUM>.

<FIG> is a graphic diagram plotting the frequency of VAC (FVAC) in MHz versus the voltage level of VIN in Volts (V) (for DUT <NUM>) or the voltage level of VDD - VIN (for DUT <NUM>) illustrating operation of either of the DUTs <NUM> or <NUM>. The conversion operation for both DUTs <NUM> and <NUM> is substantially the same with only slight variations in numerical values of frequency or voltage. Similar to that described for the DUT <NUM>, FVAC may have a frequency range well below the MHz range (as long as at or above FMIN) or well above the MHz range in different configurations, and VIN may also have a different voltage range. For either DUT <NUM> or <NUM>, the delay of each of the inverters I1 - I3 is relatively small so that the frequency of oscillation of VAC may be significantly larger than FMIN even with relatively small values of VIN. In the illustrated configurations, the voltage level on the order of 1V or so results in a frequency level in the Megahertz range, which is well above FMIN. Also, the known relationship between the voltage level of VIN and FVAC enables measurement of VIN using the LVP test system <NUM>. It is noted that the same DUT may include any combination of the converters <NUM>, <NUM>, <NUM>, or <NUM> for measuring corresponding current or voltage levels.

<FIG> is a schematic diagram of a DUT <NUM> illustrating an embodiment of the DUT <NUM> implemented according one embodiment of the present invention including a converter <NUM> receiving one or more enable signals based on a clock signal LVP_CLK having a suitable frequency at or above FMIN. The DUT <NUM> includes a portion of a functional circuit <NUM> which further includes a sense node <NUM> in similar manner as in other configurations, in which the sense node <NUM> develops VIN. Again, the electrical voltage VIN is a low frequency electrical parameter that is either constant or varies at a relatively low frequency level below FMIN, and it is desired to detect the value of VIN using the LVP test system <NUM>. A sense circuit including an electrical conductor <NUM> conveys VIN to an input of the converter <NUM>. The converter <NUM> includes a diode D1 having an anode coupled to a first, lower reference voltage VREF1 and a cathode coupled to a detect node <NUM> developing VAC. The diode D1 incorporates a PN junction forming a laser probe area <NUM> implementing an embodiment of the laser probe area <NUM>. In an alternative embodiment, the same diode or a similar diode D2 (shown using dotted lines) has its anode coupled to the detect node <NUM> and its cathode coupled to a second, higher reference voltage VREF2 providing the same or similar laser probe area <NUM>. Operation using the diode D2 is similar to that of diode D1 and is not further described. Alternative devices other than diodes are contemplated that may serve as the laser probe area <NUM>. The detect node <NUM> develops an alternating voltage VAC at a frequency at or above FMIN based on the voltage level of VIN as further described herein.

A first switch S1 has switched terminals coupled between VREF1 and the detect node <NUM> and has a control input receiving a first clock enable signal CK1_EN, a second switch S2 has switched terminals coupled between conductor <NUM> (receiving VIN) and the detect node <NUM> and has a control input receiving a second clock enable signal CK2_EN, and a third switch S3 has switched terminals coupled between VREF2 and the detect node <NUM> and has a control input receiving a third clock enable signal CK3_EN. The voltage levels of VREF1 and VREF2 are selected such that the range of VIN is between VREF1 and VREF2, or VREF1 ≤ VIN ≤ VREF2. It is noted that either one or both of the known reference voltages VREF1 and VREF2 may be a supply voltage. For example, VREF1 may be GND or VREF2 may be VDD. Each of the switches S1 - S3 are opened when its corresponding clock enable signal is asserted at a first logic level (e.g., low) and are closed when its corresponding clock enable signal is asserted at a second logic level (e.g., high). The DUT <NUM> includes an LPS circuit <NUM> implementing an embodiment of the LPS circuit <NUM>. The LPS circuit <NUM> receives the clock signal LVP_CLK which is used to develop the clock enable signals CK1_EN, CK2_EN, and CK3_EN. LVP_CLK may be developed on the DUT <NUM> or may be externally provided, such as from the test equipment <NUM>.

The LPS circuit <NUM> may enable or disable the converter <NUM> using the clock enable signals CK1_EN, CK2_EN, and CK3_EN. In order to disable the converter <NUM>, the LPS circuit <NUM> asserts the clock enable signals at a constant logic level to keep the switches S1 - S2 opened. In an alternative embodiment, one or both supply voltages, such as either GND or VDD or both, may also be switched by the LPS circuit <NUM> in a similar manner previously described, such as using a corresponding supply enable or the like receiving a supply voltage or an enable signal.

<FIG> is a timing diagram plotting the clock enable signals CK1_EN, CK2_EN, CK3_EN and the sensed alternating voltage signal VAC versus time when the DUT <NUM> is powered and the converter <NUM> is enabled according to one embodiment using the diode D1. The clock enable signals CK1_EN, CK2_EN, and CK3_EN are each asserted high in a cyclical manner for each of consecutive cycles. In the illustrated configuration, only one of the clock enable signals is asserted at a time, although alternative configurations are contemplated using different sequencing and switching frequencies. In the illustrated configuration, CK1_EN is asserted first while CK2_EN and CK3_EN remain low, then CK2_EN is asserted next while CK1_EN and CK3_EN remain low, and then CK3_EN is asserted last while CK1_EN and CK2_EN remain low, and the process is repeated in subsequent cycles. When CK1_EN is asserted high, S1 closes pulling VAC to VREF1. When CK2_EN is asserted high, S2 closes pulling VAC to the voltage level of VIN. When CK3_EN is asserted high, S3 closes pulling VAC to the voltage level of VREF2. In this manner, VAC has a stair-step waveform having at least one voltage step related to the voltage of VIN, and at least one voltage step related to a known voltage level, such as VREF1 or VREF2.

The frequencies of the clock enable signals CK1_EN, CK2_EN, and CK3_EN may be substantially equal to each other and may be based on the frequency of LVP_CLK operating at a frequency level above FMIN, so that the detect node <NUM> alternates VAC at or above FMIN. In this manner, when the laser beam <NUM> is focused on the laser probe area <NUM>, then the reflected laser beam <NUM> is modulated based on the frequency of VAC so that the output signal <NUM> displayed on the display device <NUM> follows VAC. The voltage levels of VREF1 and VREF2 are both known, so that the voltage level of VIN may be derived based on its voltage level relative to VREF1 and VREF2. In this manner, VIN is converted to an oscillating or alternating signal VAC having a frequency based on the frequency of LVP_CLK, and the voltage level of VIN may be derived by the test equipment <NUM> relative to the known voltage levels of VREF1 and VREF2. In the case in which diode D1 is replaced by the diode D2, the waveform of VAC is similar so that the voltage level of VIN is readily determined.

<FIG> is a schematic and block diagram of a DUT <NUM> implemented according to another embodiment in which a capacitor C is repeatedly charged and discharged to convert a DC or low frequency current signal IIN into an alternating voltage signal VAC on node <NUM> having a frequency at or above FMIN for laser detection. The functional circuit (not shown) on the DUT <NUM> includes a sense circuit <NUM> depicted as a current sink referenced to GND developing the current IIN. The electrical current IIN is a low frequency electrical parameter that is either constant or alternates at a relatively low frequency level below FMIN, in which it is desired to detect the value of IIN using the LVP test system <NUM>. The sense circuit <NUM> may be implemented as a current mirror branch in a similar manner as shown and described in <FIG> in which the current IIN shown developed by the current sink may actually be a mirrored current signal from the functional circuit. An electrical conductor <NUM> conveys the current IIN to a converter <NUM> in a similar manner previously described, in which the conductor <NUM> is coupled to the node <NUM> in the illustrated embodiment. The converter <NUM> includes the capacitor C and a PMOS transistor (or other suitable transistor type, such as a FET or bipolar transistor or the like) PB, having its source terminal coupled to one end and its drain terminal coupled to the other end of the capacitor C. The source terminal of PB is also shown coupled to VDD (or other suitable reference voltage level), and the drain terminal of PB is coupled to node <NUM> developing VAC. An LPS circuit <NUM> provides a clock enable signal CLK_EN based on a clock signal LVP_CLK, which may be developed on the DUT <NUM> or externally provided. The capacitor C or the transistor PB may serve as an embodiment of the laser probe area <NUM>.

Although the converter <NUM> is shown connected to VDD, in an alternative embodiment VDD may be a switched connection controlled by the LPS circuit <NUM> in a similar manner previously described to ensure that the converter <NUM> does not have any electrical effect on the underlying functional circuit.

<FIG> is a graphic diagram plotting CLK_EN and VAC versus time for the DUT <NUM> when the converter <NUM> is enabled in which VAC ramps down at a rate based on IIN. In the illustrated embodiment, the LPS circuit <NUM> may hold CLK_EN high keeping PB off to disable the converter <NUM>. The LPS circuit <NUM> toggles CLK_EN based on LVP_CLK to enable the converter <NUM>, in which CLK_EN has a frequency at or above FMIN for detection by the LVP test system <NUM>. When CLK_EN goes low, PB turns on and discharges the capacitor C so that VAC is pulled high to VDD. When CLK_EN goes high, PB is turned off and the capacitor C charges at a rate based on the current level of IIN. As the capacitor C charges, VAC ramps down at a rate based on the current level of IIN. Thus, VAC decreases more quickly for higher values of IIN and decreases more slowly for lower values of IIN. The value of IIN may be determined based on the slope of VAC when CLK_EN goes low. Operation repeats in this manner for successive cycles of CLK_EN.

<FIG> is a schematic and block diagram of a DUT <NUM> implemented according to another embodiment similar to the DUT <NUM> in which a capacitor C is repeatedly charged and discharged to convert a DC or low frequency current signal IIN into an alternating signal VAC on a node <NUM> having a frequency at or above FMIN for laser detection. The functional circuit (not shown) on the DUT <NUM> includes a sense circuit <NUM> depicted as a current source referenced to VDD developing the current IIN in a similar manner as the sense circuit <NUM> of <FIG>. Again, the electrical current IIN is a low frequency electrical parameter that is either constant or alternates at a relatively low frequency level below FMIN, in which it is desired to detect the value of IIN using the LVP test system <NUM>. Also, IIN may be represented as a mirrored current signal. An electrical conductor <NUM> conveys the current IIN to the node <NUM> of a converter <NUM> in a similar manner previously described. The converter <NUM> includes the capacitor C and an NMOS transistor (or other suitable transistor type, such as a FET or bipolar transistor or the like) NB, having its source terminal coupled to one end and its drain terminal coupled to the other end of the capacitor C. The source terminal of NB is also shown coupled to GND, and the drain terminal of NB is coupled to node <NUM> which conveys IIN and which also develops the voltage VAC. An LPS circuit <NUM> provides a clock enable signal CLK_EN based on a clock signal LVP_CLK, which may be developed on the DUT <NUM> or externally provided. The capacitor C or the transistor NB serve as the laser probe area <NUM>.

Although the converter <NUM> is shown connected to GND, in an alternative embodiment VDD may be a switched connection controlled by the LPS circuit <NUM> in a similar manner previously described to ensure that the converter <NUM> does not have any electrical effect on the underlying function circuit.

<FIG> is a graphic diagram plotting CLK_EN and VAC versus time for the DUT <NUM> when the converter <NUM> is enabled in which VAC ramps up at a rate based on IIN. In the illustrated embodiment, the LPS circuit <NUM> may hold CLK_EN low keeping NB off to disable the converter <NUM>. The LPS circuit <NUM> toggles CLK_EN based on LVP_CLK to enable the converter <NUM>, in which CLK_EN has a frequency at or above FMIN for detection by the LVP test system <NUM>. When CLK_EN goes high, NB turns on and discharges the capacitor C so that VAC is pulled low to GND. When CLK_EN goes low, NB is turned off and the capacitor C charges at a rate based on the current level of IIN. As the capacitor C charges, VAC ramps up at a rate based on IIN. Thus, VAC increases more quickly for higher values of IIN and increases more slowly for lower values of IIN. The value of IIN may be determined based on the slope of VAC when CLK_EN goes low. Operation repeats in this manner for successive cycles of CLK_EN.

<FIG> is a schematic and block diagram of a DUT <NUM> implemented according to another embodiment similar to the DUT <NUM> in which a capacitor C is repeatedly charged and discharged to convert a DC or low frequency voltage signal VIN into an alternating signal having a frequency at or above FMIN for laser detection. The functional circuit (not shown) on the DUT <NUM> includes a sense node <NUM> and an electrical conductor <NUM> conveys the voltage VIN to an input of a converter <NUM> in a similar manner previously described. The electrical voltage VIN is a low frequency electrical parameter that is either constant or alternates at a relatively low frequency level below FMIN, in which it is desired to detect the value of VIN using the LVP test system <NUM>. The converter <NUM> includes the capacitor C, a PMOS transistor (or other suitable transistor type, such as a FET or bipolar transistor or the like) PC, and an NMOS transistor (or other suitable transistor type, such as a FET or bipolar transistor or the like) NC. NC has its source terminal coupled to GND, its gate terminal coupled to the electrical conductor <NUM> for receiving VIN, and its drain terminal coupled to one end of the capacitor C at a node <NUM> developing VAC. PC has its drain terminal coupled to the node <NUM>, its source terminal coupled to the other end of the capacitor C and to VDD (or other suitable reference or supply voltage), and its gate terminal receiving a clock enable signal CLK_EN. An LPS circuit <NUM> provides CLK_EN based on a clock signal LVP_CLK, which may be developed on the DUT <NUM> or externally provided. The capacitor C or the transistor PC serves as the laser probe area <NUM>.

Although the converter <NUM> is shown connected to both VDD and GND, in an alternative embodiment, one or both VDD and GND may be a switched connection controlled by the LPS circuit <NUM> in a similar manner previously described to ensure that the converter <NUM> does not have any electrical effect on the underlying function circuit.

<FIG> is a graphic diagram plotting CLK_EN and VAC versus time for the DUT <NUM> when the converter <NUM> is enabled in which VAC ramps down at a rate based on input voltage VIN. In the illustrated embodiment, the LPS circuit <NUM> may hold CLK_EN high keeping PC off to disable the converter <NUM>. The LPS circuit <NUM> toggles CLK_EN based on LVP_CLK to enable the converter <NUM>, in which CLK_EN has a frequency at or above FMIN for detection by the LVP test system <NUM>. When CLK_EN goes low, PC turns on and discharges the capacitor C so that VAC is pulled high to VDD. When CLK_EN goes high, PC is turned off and the capacitor C charges at a rate based on the voltage level of VIN (which controls the drain current of QC). As the capacitor C charges, VAC decreases at a rate based on VIN. Thus, VAC decreases more quickly for higher values of VIN and decreases more slowly for lower values of VIN. The value of VIN may be determined based on the slope of VAC when CLK_EN goes low. Operation repeats in this manner for successive cycles of CLK_EN.

<FIG> is a schematic and block diagram of a DUT <NUM> implemented according to another embodiment similar to the DUT <NUM> in which a capacitor C is repeatedly charged and discharged to convert a DC or low frequency voltage signal VIN into an alternative signal having a frequency at or above FMIN for laser detection. The functional circuit (not shown) on the DUT <NUM> includes a sense node <NUM> and an electrical conductor <NUM> conveys the voltage VIN to a converter <NUM> in a similar manner previously described. The electrical voltage VIN is a low frequency electrical parameter that is either constant or alternates at a relatively low frequency level below FMIN, in which it is desired to detect the value of VIN using the LVP test system <NUM>. The converter <NUM> includes the capacitor C, a PMOS transistor (or other suitable transistor type, such as a FET or bipolar transistor or the like) PD, and an NMOS transistor (or other suitable transistor type, such as a FET or bipolar transistor or the like) ND. PD has its source terminal coupled to VDD (or other suitable supply or reference voltage), its gate terminal coupled to the electrical conductor <NUM> for receiving VIN, and its drain terminal coupled to one end of the capacitor C at a node <NUM> developing VAC. ND has its drain terminal coupled to the node <NUM>, its source terminal coupled to the other end of the capacitor C and to GND, and its gate terminal receiving a clock enable signal CLK_FN. An LPS circuit <NUM> provides CLK_EN based on a clock signal LVP_CLK, which may be developed on the DUT <NUM> or externally provided. The capacitor C or the transistor ND serve as the laser probe area <NUM>.

<FIG> is a graphic diagram plotting CLK_EN and VAC versus time for the DUT <NUM> when the converter <NUM> is enabled in which VAC ramps up at a rate based on VIN. In the illustrated embodiment, the LPS circuit <NUM> may hold CLK_EN low keeping ND off to disable the converter <NUM>. The LPS circuit <NUM> toggles CLK_EN based on LVP_CLK to enable the converter <NUM>, in which CLK_EN has a frequency at or above FMIN for detection by the LVP test system <NUM>. When CLK_EN goes high, ND turns on and shorts the capacitor C so that VAC is pulled high to GND. When CLK_EN goes low, ND is turned off and the capacitor C charges at a rate based on the voltage level of VIN (which controls the drain current of PD). As the capacitor C charges, VAC increases at a rate based on VIN. Thus, VAC increases more quickly for higher values of VIN and increases more slowly for lower values of VIN. The value of VIN may be determined based on the slope of VAC when CLK_EN goes low. Operation repeats in this manner for successive cycles of CLK_EN.

<FIG> is a block diagram of a DUT <NUM> implemented according to one embodiment including multiple converters <NUM> referenced to GND, individually shown as CVR1, CVR2, CVR3, CVR4, CVR5,. , CVRN, for converting any number N of voltage or current values (e.g., VIN1, VIN2, VIN3,. , IIN1, IIN3, IIN3, etc.) of an underlying functional circuit (not shown) of the DUT <NUM>. These voltage or current values VINx, IINx are low frequency electrical parameters that are either constant or that alternate at relatively low frequencies below FMIN, in which it is desired to detect the values of either VINx or IINx of VIN using the LVP test system <NUM>. Each converter <NUM> may be configured according applicable ones of the converters previously described, such as the converters <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc. The DUT <NUM> includes an LPS circuit <NUM> referenced to GND for supporting and enabling one or more of the converters <NUM>. The DUT <NUM> may include an input/output (I/O) pad or pin <NUM> for receiving and providing an external clock signal LVP_CLK to the LPS circuit <NUM>. The LPS circuit <NUM> provides the corresponding ones of the enable signals LVP ENABLE<> to each of the converters <NUM> in a similar manner previously described, such as any combination of supply voltages (GND, VDD, etc.), clock enable signals, logic enable signals, etc..

The DUT <NUM> further includes an LVP enable circuit <NUM> as a more specific embodiment of the LVP enable circuit <NUM>. The LPS circuit <NUM> initially has both its upper and lower supply voltage terminals coupled to GND so that it is initially disabled, which further disables each of the converters <NUM>. A circuit edit <NUM> may be made to cut the GND connection from the upper supply voltage terminal of the LPS circuit <NUM>, and another circuit edit <NUM> may be made to connect the upper supply voltage terminal of the LPS circuit <NUM> to VDD to enable the LPS circuit <NUM>. The circuits edits <NUM> and <NUM> may be made in any suitable manner, such as using a Focused Ion Beam (FIB) apparatus or the like. Once enabled, the DUT <NUM> may be powered up and operated in a selected normal operating mode or a selected test mode and used as the DUT <NUM> for measuring by the LVP test system <NUM>. In this manner, the laser beam <NUM> may be focused on any one of the converters <NUM> (CVR1, CVR2, CVR3, CVR4, CVR5,. , CVRN) for detecting and measuring the voltage or current values (e.g., VIN1, VIN2, VIN3,. , IIN1, IIN3, IIN3, etc.) of the underlying functional circuit of the DUT <NUM>.

<FIG> is a block diagram of a DUT <NUM> implemented according to another embodiment including multiple converters <NUM> referenced to VDD, individually shown as CVR1, CVR2, CVR3, CVR4, CVR5,. , CVRN, for converting any number N of voltage or current values (e.g., VIN1, VIN2, VIN3,. , IIN1, IIN3, IIN3, etc.) of an underlying functional circuit of the DUT <NUM>. As with the DUT <NUM>, these voltage or current values VINx, IINx are low frequency electrical parameters that are either constant or that alternate at relatively low frequencies below FMIN, in which it is desired to detect the values of either VINx or IINx of VIN using the LVP test system <NUM>. Each converter <NUM> may be configured according applicable ones of the converters previously described, such as the converters <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc. The DUT <NUM> includes an LPS circuit <NUM> referenced to VDD for supporting and enabling one or more of the converters <NUM>. The DUT <NUM> may include an I/O pad or pin <NUM> for receiving and providing an external clock signal LVP_CLK to the LPS circuit <NUM>. The LPS circuit <NUM> provides the corresponding ones of enable signals LVP ENABLE<> to each of the converters <NUM> in a similar manner previously described, such as any combination of supply voltages (GND, VDD, etc.), clock enable signals, logic enable signals, etc..

The DUT <NUM> further includes an LVP enable circuit <NUM> as a more specific embodiment of the LVP enable circuit <NUM>. The LPS circuit <NUM> initially has both its upper and lower supply voltage terminals coupled to VDD so that it is initially disabled, which further disables each of the converters <NUM>. A circuit edit <NUM> may be made to cut the VDD connection from the lower supply voltage terminal of the LPS circuit <NUM>, and another circuit edit <NUM> may be made to connect the upper supply voltage terminal of the LPS circuit <NUM> to GND to enable the LPS circuit <NUM>. The circuits edits <NUM> and <NUM> may be made in any suitable manner, such as using an FIB apparatus or the like. Once enabled, the DUT <NUM> may be powered up and operated in a selected normal operating mode or a selected test mode and used as the DUT <NUM> for testing by the LVP test system <NUM>. In this manner, the laser beam <NUM> may be focused on any one of the converters <NUM> (CVR1, CVR2, CVR3, CVR4, CVR5,. , CVRN) for detecting and measuring the voltage or current values (e.g., VIN1, VIN2, VIN3,. , IIN1, IIN3, IIN3, etc.) of the underlying functional circuit of the DUT <NUM>.

<FIG> is a block diagram of a DUT <NUM> implemented according to an embodiment similar to the DUT <NUM> in which similar components assume identical reference numerals. The DUT <NUM> includes the converters <NUM> (CVR1, CVR2, CVR3, CVR4, CVR5,. , CVRN) referenced to GND for converting any number N of voltage or current values (e.g., VIN1, VIN2, VIN3,. , IIN1, IIN3, IIN3, etc.) of the underlying functional circuit of the DUT <NUM>, and also includes the LPS circuit <NUM> referenced to GND for supporting and enabling one or more of the converters <NUM> via the corresponding enable signals LVP_ENABLE<>. Also, the DUT <NUM> may include the pin <NUM> for receiving and providing LVP_CLK to the LPS circuit <NUM>.

The LVP enable circuit <NUM>, however, is replaced by an LVP enable circuit <NUM> which is a different embodiment of the of the LVP enable circuit <NUM>. The LVP enable circuit <NUM> includes a pair of switches SW1 and SW2 controlled by an LVP enable signal LVP_EN. SW1 is normally closed and SW2 is normally open. The lower supply voltage terminal of the LPS circuit <NUM> is connected to GND in similar manner as for the DUT <NUM>. The upper supply voltage terminal of the LPS circuit <NUM>, however, is instead coupled to one switched terminal of each of the switches SW1 and SW2. The other switched terminal of SW2 is connected to VDD and the other switched terminal of SW1 is connected to GND. The switches SW1 and SW2 both have a control terminal receiving LVP_EN. LVP_EN may either be developed by a functional or test circuit (not shown) located on the DUT <NUM> or may be externally provided, such as by the test equipment <NUM> or the like.

In operation, when LVP_EN is asserted to a logic level such that SW1 couples the upper supply voltage terminal of the LPS circuit <NUM> to GND, the LPS circuit <NUM> and each of the converters <NUM> are disabled. When LVP_EN is asserted to a different or opposite logic level such that SW2 enables the LPS circuit <NUM>, its upper supply voltage terminal is coupled to VDD and the LPS circuit <NUM> may then enable any one or more of the converters <NUM> to enable the LVP test system <NUM> to detect and measure constant or low frequency electrical parameters of the DUT <NUM>.

<FIG> is a block diagram of a DUT <NUM> implemented according to an embodiment similar to the DUT <NUM> in which similar components assume identical reference numerals. The DUT <NUM> includes the converters <NUM> (CVR1 - CVRN) referenced to VDD for converting any number N of voltage or current values (e.g., VIN1, VIN2, VIN3, IIN1, IIN3, IIN3, etc.) of the underlying functional circuit of the DUT <NUM>, and also includes the LPS circuit <NUM> referenced to VDD for supporting and enabling one or more of the converters <NUM> via the corresponding enable signals LVP_ENABLE<>. Also, the DUT <NUM> may include the pin <NUM> for receiving and providing LVP_CLK to the LPS circuit <NUM>.

The LVP enable circuit <NUM>, however, is replaced by an LVP enable circuit <NUM> which is a different embodiment of the of the LVP enable circuit <NUM>. The LVP enable circuit <NUM> includes a pair of switches SW1 and SW2 controlled by an LVP enable signal L VP _EN. SW1 is normally open and SW2 is normally closed. The upper supply voltage terminal of the LPS circuit <NUM> is connected to VDD in similar manner as for the DUT <NUM>. The lower supply voltage terminal of the LPS circuit <NUM>, however, is instead coupled to one switched terminal of each of the switches SW1 and SW2. The other switched terminal of SW2 is connected to VDD and the other switched terminal of SW1 is connected to GND. The switches SW1 and SW2 both have a control terminal receiving LVP_EN. LVP_EN may either be developed by functional or test circuit (not shown) located on the DUT <NUM> or may be externally provided, such as by the test equipment <NUM> or the like.

In operation, when LVP_EN is asserted to a logic level such that SW2 couples the lower supply voltage terminal of the LPS circuit <NUM> to VDD, the LPS circuit <NUM> and each of the converters <NUM> are disabled. When LVP_EN is asserted to a different or opposite logic level such that SW1 enables the LPS circuit <NUM> by coupling its lower supply voltage terminal to GND, then the LPS circuit <NUM> may then enable any one or more of the converters <NUM> to enable the LVP test system <NUM> to detect and measure constant or low frequency electrical parameters of the DUT <NUM>.

The illustrated converters detect the input signals VIN or IIN at a specific point in time which is particularly advantageous for electrical parameters that are DC or relatively constant. For low frequency AC signals, however the test equipment <NUM> may be configured to store multiple iterations over time in which post-processing techniques may be used to evaluate a rate of change of the measured signal over time to determine a corresponding frequency. Alternatively, or in addition, the test equipment <NUM> may include a frequency analyzer which may be used to determine the frequency of measured signals.

The DUTs with converters may exhibit sample to sample manufacturing variations, so that the frequencies of the converters based on a ring oscillator (e.g., <NUM>, <NUM>, <NUM>, and <NUM>) or the like may vary by a significant amount from one DUT to another thereby rendering the measurements indeterminate or at least less accurate. In one embodiment, a calibration process may be used to normalize measurements of each DUT. In another embodiment as illustrated by <FIG>, normalization may be achieved by pad matching using externally provided known reference values.

<FIG> is a block diagram illustrating various configurations of pad matching that may be used to normalize voltage measurements for a given DUT. The DUT may include an I/O pin <NUM> receiving a known reference voltage VREF, although VREF may also be internally provided. The set of converters on the DUT may include one or more voltage reference converters, such as <NUM> or <NUM>, or both, receiving VREF. The voltage reference converter <NUM> is referenced to GND and the voltage reference converter <NUM> is referenced to VDD. In one embodiment, the reference converters <NUM> and <NUM> may include ring oscillators for converting VREF to a corresponding reference frequency for detection by the LVP test system <NUM>. In this manner, the test equipment <NUM> may use the relationship between VREF and the reference frequency to normalize or correct for variances of the frequency to voltage conversion by pads using ring oscillators such as that shown in <FIG>. In addition or in the alternative, the reference converters <NUM> and <NUM> or other similar reference converters (not shown) may including charging capacitors, such as those shown in DUTs <NUM> and <NUM>.

<FIG> is a block diagram illustrating various configurations of pad matching that may be used to normalize current measurements for a given DUT. The DUT may include an I/O pin <NUM> sinking or sourcing an external known reference current IREF. An external current sink <NUM> referenced to GND may sink IREF via pin <NUM> for a current reference converter <NUM> referenced to GND, or an external current source <NUM> referenced to VDD may source IREF via pin <NUM> (or another pin) for a current reference converter <NUM> reference to VDD. In one embodiment, the reference converters <NUM> and <NUM> may include substantially identical ring oscillators for converting IREF to a corresponding reference frequency for detection by the LVP test system <NUM>. In this manner, the test equipment <NUM> may use the relationship between IREF and the reference frequency to normalize or correct for variances of the frequency to current conversion by pads using ring oscillators such as that shown in <FIG>. In addition or in the alternative, the reference converters <NUM> and <NUM> or other similar reference converters (not shown) may including charging capacitors, such as those shown in DUTs <NUM> and <NUM>.

The capacitor charging converters <NUM>, <NUM>, <NUM> and <NUM> are implemented within a design window based on the low frequency cutoff of the LVP test system <NUM>, system jitter, and parasitic parameters. In particular, the targeted rising or falling slope should be less than the slope due to system jitter but greater than the low frequency cutoff of the LVP test system <NUM>. The capacitance of the capacitor C, including parasitic capacitance, may be determined by the pad size. The low frequency cutoff of the LVP test system <NUM> may be adjusted to a known value, such as, for example, <NUM>. A reasonable slope limit may be used for system jitter, such as, for example, <NUM> nanoseconds (ns), although this value may be different for different configurations. These parameters determine a reasonable window for IIN. In one embodiment, for example, IIN may range from <NUM> nanoamperes (nA) to <NUM> microamperes (µA). If IIN is outside the target window and the parameters are not readily adjustable, then a different converter type may be used.

Although the present invention has been described in connection with several embodiments, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the scope of the invention as defined by the appended claims. For example, variations of positive logic or negative logic may be used in various embodiments in which the present invention is not limited to specific logic polarities, device types or voltage levels or the like. For example, VDD and GND are supply voltage levels in which each may have any positive or negative voltage level, and VDD may have a higher or lower voltage level relative to GND. Also, alternative supply or reference voltages may be used instead or VDD or GND.

Claim 1:
An integrated circuit block for a laser voltage probe test system (<NUM>), the integrated circuit block comprising:
a sense node (<NUM>) wherein the integrated circuit block is configured such that the sense node develops a low frequency electrical parameter when the integrated circuit block is powered, wherein said low frequency electrical parameter is constant or varies at a frequency below a predetermined frequency level of <NUM>; and
a converter circuit (<NUM>) coupled to said sense node and including a laser probe area (<NUM>), wherein said converter circuit is configured to convert said low frequency electrical parameter into an alternating electrical parameter having a frequency at or above <NUM>, wherein the laser probe area is configured to be energized by the alternating electrical parameter such that it creates an electric field which modulates an incident reflected laser beam (<NUM>) focused on a point within said laser probe area for detection by the laser voltage probe test system.