Patent Description:
This invention relates generally to a semiconductor package, and in particular to an improved leadframe chip package secure to physical probing or hardware hacking. More particularly, the present invention relates to a semiconductor package according to the pre-characterizing part of independent claim <NUM> and to a method of fabricating a semiconductor package according to the pre-characterizing part of independent claim <NUM>. Such a semiconductor package and method are shown in document <CIT>. Such a semiconductor package is also shown in documents <CIT> and <CIT>. A similar semiconductor package is shown in documents <CIT> and <CIT>.

Many integrated circuits are used to store sensitive or confidential information such as personal or financial information. The technology for reverse engineering an integrated circuit (IC) has progressed to the point where the state of individual circuits can be read off of an operating microcircuit. For example, a leadframe chip package such as a quad flat no-lead (QFN) package typically has pins (or perimeter lands) located on the edge of the package and is susceptible to physical probing or hardware hacking.

Protection of integrated circuits from such intrusions, which may allow access to the sensitive or confidential information, is becoming increasingly important. Therefore, there is a constant need in this industry to provide an improved leadframe chip package capable of reducing the ability of a hacker to physically probe an IC package with such perimeter lands.

Document <CIT> discloses methods of fabricating leadless packages.

It is one object of the invention to provide an improved leadframe chip package with shaded lead terminals. A semiconductor package according to the invention is defined in independent claim <NUM>, a printed circuit board assembly according to the invention is defined in claim <NUM>, and a method for fabricating a semiconductor package according to the invention is defined in independent claim <NUM>. The dependent claims define preferred embodiments thereof.

According to one aspect of the invention, a semiconductor package includes a die attach pad; a plurality of lead terminals disposed around the die attach pad; a semiconductor die mounted on the die attach pad; a molding compound encapsulating the plurality of lead terminals, the semiconductor die, and the die attach pad; and a step cut sawn into the molding compound along a perimeter of a bottom surface of the semiconductor package. The step cut penetrates through an entire thickness of each of the plurality of lead terminals, whereby each of the plurality of lead terminals has at least an exposed outer end at the step cut.

Preferably, the semiconductor die comprises a plurality of input/output (I/O) pads disposed along a perimeter of the semiconductor die, and wherein the plurality of I/O pads of the semiconductor die is electrically connected to the lead terminals by bond wires.

Preferably, the semiconductor package has a thickness greater than <NUM>.

The step cut has a height greater than the thickness of each of the plurality of lead terminals and a width of about <NUM>-<NUM>.

Preferably, a bottom surface of the die attach pad is exposed from the bottom surface of the semiconductor package.

A remaining portion of the molding compound masks a side surface of the lead terminals.

According to another aspect of the invention, a printed circuit board assembly includes a printed circuit board comprising a chip-mounting face; and a semiconductor package mounted on the chip-mounting face. The semiconductor package has a rectangular outline, a top surface, a bottom surface, and four sidewalls between the top surface and the bottom surface.

The semiconductor package includes a die attach pad; a plurality of lead terminals disposed around the die attach pad; a semiconductor die mounted on the die attach pad; a molding compound encapsulating the plurality of lead terminals, the semiconductor die, and the die attach pad; and a step cut sawn into the molding compound along a perimeter of a bottom surface of the semiconductor package. The step cut penetrates through an entire thickness of each of the plurality of lead terminals, whereby each of the plurality of lead terminals has at least an exposed outer end at the step cut. The semiconductor package may include the preferred features described above.

Preferably, a solder fillet is provided on the exposed outer end at the step cut.

Preferably, the solder fillet does not protrude beyond the four sidewalls of the semiconductor package.

Preferably, the solder fillet is in direct contact with the exposed outer end and has a half-spherical profile or a curved outer surface.

Preferably, the exposed outer end and the solder fillet are shaded by the molding compound at the step cut.

Preferably, a remaining portion of the molding compound masks a side surface of the lead terminals.

According to another aspect of the invention, a method for fabricating a semiconductor package is provided. A leadframe strip populated with a plurality of leadframes is provided. Each of the plurality of leadframes comprises a die attach pad supported in a central region and lead terminals disposed around the die attach pad. A semiconductor die is mounted on the die attach pad. The semiconductor die is electrically coupling with the lead terminals. The lead terminals, the semiconductor die, and the die attach pad are encapsulated with a molding compound. A step cut is sawn into the molding compound along a perimeter around the lead terminals using a step cut saw width. A sawing process is performed to saw through the molding compound along the step cut using saw width, wherein the step cut saw width is wider than the saw width.

According to some embodiments, the semiconductor die comprises a plurality of input/output (I/O) pads disposed along a perimeter of the semiconductor die, and wherein the plurality of I/O pads of the semiconductor die is electrically connected to the lead terminals by bond wires.

Preferably, the leadframes comprise half-etched regions between the lead terminals.

Preferably, the lead terminals are connected by connecting portions, and wherein the half-etched regions are disposed under the connecting portions.

Preferably, the molding compound within the half-etched regions is removed, and the connecting portions are removed when sawing the step cut into the molding compound.

Preferably, the step cut saw width is approximately <NUM> and the saw width is approximately <NUM>-<NUM>.

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. In the drawings:.

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.

These embodiments are described in sufficient detail to enable those skilled in the art to practice them. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.

It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present.

There are various leadframe-based surface mount components, such as quad flat no-lead (QFN) package, advanced QFN (aQFN) package, low-profile quad flat package (LQFP) or the like. A package can be attached to a printed circuit board (PCB) by, for example, soldering it to the PCB. The attachment of the packages (i.e. packaged integrated circuit) to PCBs produces printed circuit board assemblies (PCBAs), which can be used as motherboards in computers, portable devices such as mobile phone, tablets, notebooks, etc..

Generally, a leadframe strip is populated with a plurality of leadframes. A semiconductor die or microelectronic device may be mounted on each leadframe and encapsulated with a molding compound. Leadframes are separated during singulation of the strip to create individual semiconductor packages. One type of the semiconductor packages is a flat-pack no-lead package where each terminal is exposed at a bottom and at a side of the package. Typically, the sawing process during singulation of the strip typically results in lead terminals that have at least some exposed base metal on a cut end, or flank, of each lead terminal. Typically, the aforesaid cut end is vertically flush with a sidewall surface of the package or the sidewall surface of a molding compound.

The term of quad flat no-lead or small outline no-lead package indicates that the leads do not have cantilevered leads, but flat leads, which are typically arrayed along the periphery of the packaged device. The metal of the leads may be connected by solder material to the metal of respective contact pads of an external part. QFN packages typically use a copper leadframe for the die assembly and PCB interconnection.

Please refer to <FIG> is a schematic, cross-sectional diagram showing an exemplary leadframe chip package <NUM> not falling under the present invention. <FIG> is a perspective view of the flipped leadframe chip package <NUM> of <FIG>. As shown in <FIG>, the leadframe chip package <NUM> such as a QFN package may comprise a plurality of lead terminals (or pins) <NUM> disposed around a die attach pad <NUM> that is supported in a central region of the leadframe chip package <NUM>. The leadframe chip package <NUM> may have a rectangular outline. The leadframe chip package <NUM> may have a top surface 1a, a bottom surface 1b, and four sidewalls S<NUM>-S<NUM> between the top surface 1a and the bottom surface 1b. The first sidewall S<NUM> is opposite to the third sidewall S<NUM> and the second sidewall S<NUM> is opposite to the fourth sidewall S<NUM>. Optionally, a ground ring <NUM> may be disposed between the plurality of lead terminals <NUM> and the die attach pad <NUM>. It is to be understood that the number of lead terminals and dimension of the leadframe chip package are for illustration purposes only.

Preferably, at least one semiconductor die <NUM> is mounted on a top surface 210a of the die attach pad <NUM>. The semiconductor die <NUM> comprises a plurality of input/output (I/O) pads <NUM> disposed along the perimeter of the semiconductor die <NUM>. Preferably, for example, the I/O pads <NUM> of the semiconductor die <NUM> may be electrically connected to the lead terminals <NUM> by bond wires <NUM>. The plurality of lead terminals <NUM>, the semiconductor die <NUM>, the bond wires <NUM>, and the die attach pad <NUM> are encapsulated by a molding compound <NUM> comprising, for example, epoxy resin and filler. In some embodiments, the at least one semiconductor die <NUM> may be installed within the package in a flip-chip manner.

A step cut ST is sawn into the molding compound <NUM> along the perimeter of the bottom surface 1b of the leadframe chip package <NUM>. The step cut ST may penetrate through an entire thickness of each of the plurality of lead terminals <NUM>. Therefore, each of the plurality of lead terminals <NUM> has at least an exposed outer end 200a, or flank, at the step cut ST. The exposed outer ends 200a are retracted and shaded at the step cut ST and therefore do not present on the four sidewalls S<NUM>-S<NUM> of the leadframe chip package <NUM>.

Preferably, the leadframe chip package <NUM> may have a thickness t that is greater than <NUM>. Alternatively preferably, the leadframe chip package <NUM> may have a thickness t of about <NUM>-<NUM>, for example, <NUM>. Preferably, the step cut ST may have a height h of about <NUM>-<NUM>, for example, <NUM>, and a width d of about <NUM>-<NUM>, for example, <NUM>. The height h of the step cut ST is greater than a thickness of the plurality of lead terminals <NUM>.

Preferably, a bottom surface 210b of the die attach pad <NUM> may be exposed from the bottom surface 1b of the leadframe chip package <NUM> and may be connected to a ground plane and/or heat-dissipating plugs (not shown) in a printed circuit board (PCB). Preferably, the ground ring <NUM> is half-etched from the bottom surface 1b and is not exposed from the bottom surface 1b of the leadframe chip package <NUM>.

Please briefly to <FIG> is a schematic, cross-sectional diagram showing an exemplary printed circuit board assembly (PCBA) in accordance with one embodiment of the invention. <FIG> is a perspective partial view of the PCBA in <FIG>.

As shown in <FIG>, the PCBA <NUM> comprises the leadframe chip package <NUM> as set forth in <FIG>, and a printed circuit board <NUM>. The leadframe chip package <NUM> is soldered to the printed circuit board <NUM>. Preferably, the printed circuit board <NUM> may be a laminated board made of insulating material layers <NUM> and layers of metal traces <NUM> such as copper traces separated by the insulating material layers <NUM>. The metal traces <NUM> may function to establish electrical connections between devices mounted on the printed circuit board <NUM>, conduct heat, or provide a ground. On a chip-mounting face 4a of the printed circuit board <NUM>, bonding pads 420p are provided and solder openings 412a are formed in a solder mask <NUM> to define soldering regions on the bonding pads 420p, respectively.

To solder the leadframe chip package <NUM> to the printed circuit board <NUM>, solder paste SP can be applied to the surface of the bonding pads 420p within the defined regions. The solder paste SP can be applied onto the printed circuit board <NUM> by stencil printing methods, but not limited thereto. After the application of solder paste SP, the leadframe chip package <NUM> can be positioned on the printed circuit board <NUM>, and the PCBA <NUM> can be placed into an oven and heated. The heating cause the solder to melt, leading to wetting and wicking. The solder mask <NUM> on the printed circuit board <NUM> can control the solder paste SP during heating. The solder mask <NUM> is placed on the printed circuit board <NUM>, and solder paste SP is applied to areas of the printed circuit board <NUM> to which the leadframe chip package <NUM> is to be attached that are not protected by the solder mask <NUM>.

Preferably, a solder fillet F may be observed on the exposed outer end 200a at the step cut ST. Preferably, the solder fillet F does not protrude beyond the four sidewalls S<NUM>-S<NUM>. Preferably, the solder fillet F is in direct contact with the exposed outer end 200a. Preferably, the solder fillet F wicking up to the exposed outer end 200a may have a half-spherical profile or a curved outer surface, but is not limited thereto. As can be discerned from <FIG>, the exposed outer end 200a and the solder fillet F are shaded by the molding compound <NUM> at the step cut ST. It is to be understood that in some embodiments the solder fillet F may not be observed on the exposed outer end 200a depending upon the design of the PCB.

The step cut ST shown in <FIG> and <FIG> is a continuous ring-shaped region recessed into the molding compound <NUM> along the perimeter of the bottom surface 1b of the leadframe chip package <NUM> and does not fall under the present invention. The step cut ST of the present invention is a discontinuous region depending upon the design requirements. <FIG> are bottom views of the leadframe chip packages according to various embodiments of the invention, wherein like layers, regions, or elements are designated by like numeral numbers or labels.

As shown in <FIG> not falling under the present invention, the step cut ST is a continuous ring-shaped region recessed into the molding compound <NUM> along the perimeter of the bottom surface 1b of the leadframe chip package <NUM>. The cut ends 200a of the lead terminals <NUM> are not exposed on the sidewalls S<NUM>-S<NUM>.

As shown in <FIG>, the step cut ST is a C-shaped region sawn into the molding compound <NUM> along the perimeter of the bottom surface 1b of the leadframe chip package <NUM> and is formed only under the three sidewalls S<NUM>-S<NUM>. The lead terminals <NUM> have cut ends 201a exposed from the sidewall S<NUM>.

As shown in <FIG>, the step cut ST is a discontinuous ring-shaped region sawn into the molding compound <NUM> along the perimeter of the bottom surface 1b of the leadframe chip package <NUM>. At the discontinuity, the lead terminals <NUM> have cut ends 201a exposed from the sidewall S<NUM>. The lead terminals <NUM> may have a length that is different from that of the lead terminals <NUM>.

As shown in <FIG>, the leadframe chip package <NUM> comprises L-shaped step cut ST<NUM> and step cut ST<NUM> sawn into the molding compound <NUM> along the perimeter of the bottom surface 1b of the leadframe chip package <NUM>. At the discontinuity, the lead terminals <NUM> have cut ends 201a exposed from the sidewalls S<NUM> and S<NUM>. The lead terminals <NUM> may have a length that is different from that of the lead terminals <NUM>.

As shown in <FIG>, the leadframe chip package <NUM> comprises step cut ST only adjacent to the sidewall S<NUM>. The lead terminals <NUM> have cut ends 201a exposed from the sidewalls Si, S<NUM> and S<NUM>.

As shown in <FIG>, the leadframe chip package <NUM> comprises step cut ST<NUM> adjacent to the sidewall S<NUM> and step cut ST<NUM> adjacent to the sidewall S<NUM>. The lead terminals <NUM> have cut ends 201a exposed from the sidewalls S<NUM> and S<NUM>.

<FIG> are schematic, cross-sectional diagrams showing a method for fabricating the leadframe chip package <NUM> in <FIG> according to an embodiment of the invention, wherein like layers, regions, or elements are designated by like numeral numbers or labels.

As shown in <FIG>, a leadframe strip (or carrier) <NUM> populated with a plurality of leadframes <NUM> is provided. Preferably, the leadframe strip <NUM> may be composed of a metal sheet or metal layer, for example, a copper layer. Each of the plurality of leadframes <NUM> comprises a die attach pad <NUM> supported in a central region and lead terminals <NUM> disposed around the die attach pad <NUM>. Although not shown in the figures, it is understood that the die attach pad <NUM> may be supported by four tie-bars extending at the four corners and a gap GP may be formed between the die attach pad <NUM> and the lead terminals <NUM>. Preferably, the leadframes <NUM> may comprise half-etched regions 200r between the lead terminals <NUM>. Preferably, the half-etched regions 200r are disposed under connecting portions <NUM>.

As shown in <FIG>, a semiconductor die <NUM> is mounted on a top surface 210a of the die attach pad <NUM>. For example, the semiconductor die <NUM> may be secured to the top surface 210a of the die attach pad <NUM> by using an adhesive layer <NUM>, but is not limited thereto. The semiconductor die <NUM> comprises a plurality of I/O pads <NUM> disposed along the perimeter of the semiconductor die <NUM>. Preferably, for example, the I/O pads <NUM> of the semiconductor die <NUM> may be electrically connected to the lead terminals <NUM> by bond wires <NUM>.

As shown in <FIG>, the plurality of lead terminals <NUM>, the semiconductor die <NUM>, the bond wires <NUM>, and the die attach pad <NUM> are encapsulated by a molding compound <NUM>. Preferably, the molding compound <NUM> may comprise, for example, epoxy resin and filler, but not limited thereto. Preferably, a bottom surface 210b of the die attach pad <NUM> may be exposed. Preferably, the half-etched regions 200r and the gap GP may be filled with the molding compound <NUM>.

As shown in <FIG>, a step cut ST is sawn into the molding compound <NUM> along the perimeter around the lead terminals <NUM>. Preferably, the molding compound <NUM> within the half-etched regions 200r is removed. Preferably, the connecting portions <NUM> are removed. The step cut ST may be formed by using a step cut saw width W<NUM>. Preferably, the step cut saw width W<NUM> may be approximately <NUM>, but not limited thereto. Preferably, the step cut ST may have a height h of about <NUM>-<NUM>, for example, <NUM>. Preferably, the height h of the step cut ST may be greater than a thickness of the plurality of lead terminals <NUM>. After the step cut ST is formed, each of the lead terminals <NUM> has an exposed outer end 200a, or flank, at the step cut ST.

As shown in <FIG>, subsequently, a sawing process is performed to saw through the molding compound <NUM> along the step cut ST. Preferably, the sawing process may be performed using a saw width W<NUM> less than the step cut saw width W<NUM>. Preferably, the saw width W<NUM> is approximately <NUM>-<NUM>, for example, <NUM>.

<FIG> are schematic, cross-sectional diagrams showing a method for fabricating a leadframe chip package according to another embodiment of the invention, wherein like layers, regions, or elements are designated by like numeral numbers or labels.

As shown in <FIG>, a leadframe strip <NUM> populated with a plurality of leadframes <NUM> is provided. Each of the plurality of leadframes <NUM> comprises a die attach pad <NUM> supported in a central region and lead terminals <NUM> disposed around the die attach pad <NUM>. Although not shown in the figures, it is understood that the die attach pad <NUM> may be supported by four tie-bars extending at the four corners and a gap GP may be formed between the die attach pad <NUM> and the lead terminals <NUM>. Preferably, the leadframes <NUM> may comprise half-etched regions 200r between the lead terminals <NUM>. Preferably, the half-etched regions 200r are disposed under connecting portions <NUM>.

As shown in <FIG>, a step cut ST is sawn into the molding compound <NUM> along the perimeter around the lead terminals <NUM>. The step cut ST may be formed by using a step cut saw width W<NUM>. Preferably, the step cut saw width W<NUM> may be smaller than <NUM>, but not limited thereto. Preferably, the step cut ST may have a height h of about <NUM>-<NUM>, for example, <NUM>. Preferably, the height h of the step cut ST may be greater than a thickness of the plurality of lead terminals <NUM>. Preferably, the molding compound <NUM> within the half-etched regions 200r is not completely removed. The remaining portion <NUM> of the molding compound <NUM> within the half-etched regions 200r masks the side surface of the lead terminals <NUM>. Preferably, the connecting portions <NUM> are cut through, thereby exposing the end surfaces 206a above the remaining portion <NUM> of the molding compound <NUM> within the half-etched regions 200r.

Claim 1:
A semiconductor package (<NUM>), comprising:
a die attach pad (<NUM>);
a plurality of lead terminals (<NUM>, <NUM>) disposed around the die attach pad (<NUM>);
a semiconductor die (<NUM>) mounted on the die attach pad (<NUM>);
a molding compound (<NUM>) encapsulating the plurality of lead terminals (<NUM>, <NUM>), the semiconductor die (<NUM>), and the die attach pad (<NUM>); and
a step cut (ST) sawn into the molding compound (<NUM>) along a perimeter of a bottom surface (1b) of the semiconductor package (<NUM>), wherein the step cut penetrates through an entire thickness of each of the plurality of lead terminals (<NUM>) and wherein the step cut (ST) has a height (h) greater than the thickness of each of the plurality of lead terminals (<NUM>), whereby each of the plurality of lead terminals (<NUM>) has at least an exposed outer end (200a) at the step cut (ST);
characterized in that
the step cut (ST) is a discontinuous region and has a width (d) of <NUM>-<NUM>, wherein at the discontinuity of the region the lead terminals (<NUM>) have cut ends (201a) exposed from the sidewall of the package.