Patent Description:
Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to multi-threshold voltage devices and associated techniques and configurations as defined in the appended claims.

Transistor leakage and switching speed may be modulated by a threshold voltage (Vth) of the transistor. Emerging circuits may utilize transistors with multiple threshold voltages to optimize power dissipation and clock frequency. For example, subcircuitry that constrains circuit performance may use lower Vth transistors to increase switching speed and subcircuitry that does not constrain circuit performance may use higher Vth transistors to reduce power consumption. Traditional methods of modulating threshold voltage of a transistor may be based on doping a channel region with different amounts of impurities. For example, an n-type device may have a higher Vth if a greater number of p-type dopants are implanted into the channel. When different transistors are implanted with different levels of channel dopants, different threshold voltages may be realized. However, doping the channel (e.g., by implant) may adversely affect switching speed of a transistor for a given leakage level. Dopant atoms may scatter mobile charge carriers reducing carrier charge mobility. Additionally, transistor performance variation may increase with increasing dopant levels. For example, variation of Vth may increase with increased dopant levels due to random dopant fluctuations.

<CIT> discloses methods of fabricating semiconductor devices and structures thereof.

<CIT> discloses a semiconductor device that includes a dual gate and a method of fabricating the same.

Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.

The description may use perspective-based descriptions such as top/bottom, side, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.

The term "coupled with," along with its derivatives, may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term "directly coupled" may mean that two or more elements are in direct contact.

In various embodiments, the phrase "a first feature formed, deposited, or otherwise disposed on a second feature," may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

As used herein, the term "module" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.

<FIG> schematically illustrates a top view of an example die <NUM> in wafer form <NUM> and in singulated form <NUM>, in accordance with some embodiments. In some embodiments, the die <NUM> may be one of a plurality of dies (e.g., dies <NUM>, 102a, 102b) of a wafer <NUM> composed of semiconductor material such as, for example silicon or other suitable material. The plurality of dies may be formed on a surface of the wafer <NUM>. Each of the dies may be a repeating unit of a semiconductor product that includes multi-threshold voltage transistor devices as described herein. For example, the die <NUM> may include circuitry having transistor elements such as, for example, one or more channel bodies <NUM> (e.g., fin structures, nanowires, etc.) that provide a channel pathway for mobile charge carriers in multi-threshold voltage transistor devices. Although the one or more channel bodies <NUM> are depicted in rows that traverse a substantial portion of the die <NUM> in <FIG>, it is to be understood that one or more channel bodies <NUM> may be configured in any of a wide variety of other suitable arrangements on the die <NUM> in other embodiments.

After a fabrication process of the semiconductor product embodied in the dies is complete, the wafer <NUM> may undergo a singulation process in which each of the dies (e.g., die <NUM>) is separated from one another to provide discrete "chips" of the semiconductor product. The wafer <NUM> may be any of a variety of sizes. In some embodiments, the wafer <NUM> has a diameter ranging from about <NUM> to about <NUM>. The wafer <NUM> may include other sizes and/or other shapes in other embodiments. According to various embodiments, the one or more channel bodies <NUM> may be disposed on a semiconductor substrate in wafer form <NUM> or singulated form <NUM>. The one or more channel bodies <NUM> described herein may be incorporated in a die <NUM> for logic or memory, or combinations thereof. In some embodiments, the one or more channel bodies <NUM> may be part of a system-on-chip (SoC) assembly.

<FIG> schematically illustrates a cross-section side view of an integrated circuit (IC) assembly <NUM>, in accordance with some embodiments. In some embodiments, the IC assembly <NUM> may include one or more dies (hereinafter "die <NUM>") electrically and/or physically coupled with a package substrate <NUM>. The die <NUM> may include one or more channel bodies (e.g., one or more channel bodies <NUM> of <FIG>) that serve as channel bodies of multi-threshold voltage transistor devices as described herein. In some embodiments, the package substrate <NUM> may be electrically coupled with a circuit board <NUM>, as can be seen.

The die <NUM> may represent a discrete product made from a semiconductor material (e.g., silicon) using semiconductor fabrication techniques such as thin film deposition, lithography, etching and the like used in connection with forming CMOS devices. In some embodiments, the die <NUM> may be, include, or be a part of a processor, memory, SoC or ASIC in some embodiments. In some embodiments, an electrically insulative material such as, for example, molding compound or underfill material (not shown) may encapsulate at least a portion of the die <NUM> and/or die-level interconnect structures <NUM>.

The die <NUM> can be attached to the package substrate <NUM> according to a wide variety of suitable configurations including, for example, being directly coupled with the package substrate <NUM> in a flip-chip configuration, as depicted. In the flip-chip configuration, an active side, S1, of the die <NUM> including circuitry is attached to a surface of the package substrate <NUM> using die-level interconnect structures <NUM> such as bumps, pillars, or other suitable structures that may also electrically couple the die <NUM> with the package substrate <NUM>. The active side S1 of the die <NUM> may include multi-threshold voltage transistor devices as described herein. An inactive side, S2, may be disposed opposite to the active side S1, as can be seen.

In some embodiments, the die-level interconnect structures <NUM> may be configured to route electrical signals between the die <NUM> and other electrical devices. The electrical signals may include, for example, input/output (I/O) signals and/or power/ground signals that are used in connection with operation of the die <NUM>.

In some embodiments, the package substrate <NUM> is an epoxy-based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate. The package substrate <NUM> may include other suitable types of substrates in other embodiments including, for example, substrates formed from glass, ceramic, or semiconductor materials.

The package substrate <NUM> may include electrical routing features configured to route electrical signals to or from the die <NUM>. The electrical routing features may include, for example, pads or traces (not shown) disposed on one or more surfaces of the package substrate <NUM> and/or internal routing features (not shown) such as, for example, trenches, vias or other interconnect structures to route electrical signals through the package substrate <NUM>. For example, in some embodiments, the package substrate <NUM> may include electrical routing features such as pads (not shown) configured to receive the respective die-level interconnect structures <NUM> of the die <NUM>.

The circuit board <NUM> may be a printed circuit board (PCB) composed of an electrically insulative material such as an epoxy laminate. For example, the circuit board <NUM> may include electrically insulating layers composed of materials such as, for example, polytetrafluoroethylene, phenolic cotton paper materials such as Flame Retardant <NUM> (FR-<NUM>), FR-<NUM>, cotton paper and epoxy materials such as CEM-<NUM> or CEM-<NUM>, or woven glass materials that are laminated together using an epoxy resin prepreg material. Interconnect structures (not shown) such as traces, trenches, vias may be formed through the electrically insulating layers to route the electrical signals of the die <NUM> through the circuit board <NUM>. The circuit board <NUM> may be composed of other suitable materials in other embodiments. In some embodiments, the circuit board <NUM> is a motherboard (e.g., motherboard <NUM> of <FIG>).

Package-level interconnects such as, for example, solder balls <NUM> may be coupled to one or more pads (hereinafter "pads <NUM>") on the package substrate <NUM> and/or on the circuit board <NUM> to form corresponding solder joints that are configured to further route the electrical signals between the package substrate <NUM> and the circuit board <NUM>. The pads <NUM> may be composed of any suitable electrically conductive material such as metal including, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), and combinations thereof. Other suitable techniques to physically and/or electrically couple the package substrate <NUM> with the circuit board <NUM> may be used in other embodiments.

The IC assembly <NUM> may include a wide variety of other suitable configurations in other embodiments including, for example, suitable combinations of flip-chip and/or wire-bonding configurations, interposers, multi-chip package configurations including system-in-package (SiP) and/or package-on-package (PoP) configurations. Other suitable techniques to route electrical signals between the die <NUM> and other components of the IC assembly <NUM> may be used in some embodiments.

<FIG> schematically illustrates an example band diagram <NUM> for transistor devices with various threshold voltages, in accordance with some embodiments. The band diagram <NUM> may depict workfunction energy levels (in dashed form) corresponding with threshold voltage differences between each of a plurality of multi-threshold transistor devices (hereinafter "devices") n0, n1, n2, p2, p1, p0 formed using silicon. As can be seen, a threshold voltage of device n0 (e.g., nearest a conduction band of silicon) may be less than a threshold voltage of device n1, which may be less than a threshold voltage of device n2. A threshold voltage of device p2 may be less than a threshold voltage of device p1, which may be less than a threshold voltage of device p0 (e.g., nearest a valence band of silicon). In some embodiments, the workfunction of devices n2, p2 may be the same or substantially the same. In some embodiments, a difference between each of the threshold voltages (e.g., between n0 and n1, between n1 and n2, p2, etc.) is from <NUM> millivolts (mV) to <NUM> mV or more. In one embodiment, the difference between each of the threshold voltages is about <NUM> mV. Differences between each of the threshold voltages may have other suitable values in other embodiments.

The variation of threshold voltages of the devices n0, n1, n2, p2, p1, p0 may be achieved using different thicknesses of gate electrode material, which may change a workfunction of the gate instead of or in addition to creating a difference in Fermi level of an underlying channel body by doping. For example, variation of threshold voltages in n-type devices may be achieved by varying a thickness of a p-type gate electrode and variation of threshold voltages in p-type devices may be achieved by varying a thickness of an n-type gate electrode. In the depicted embodiment, for an n-type device array, layers Q1, Q2, Q3 and Q4 may each have a corresponding arrow that represents a different thickness of a p-type workfunction metal (pWFM) formed on a channel body to modulate the threshold voltages of n0, n1, n2/p2, p1 and p0. That is, layer Q1 may have a greatest thickness of pWFM corresponding with device p0, layer Q2 may have a smaller thickness of pWFM relative to layer Q1 and corresponding with device p1, layer Q3 may have a smaller thickness of pWFM relative to layer Q2 and corresponding with devices n2, p2, and layer Q4 may have a smallest thickness of pWFM corresponding with device n1. Device n0 may not have a thickness of pWFM at all and may have an n-type workfunction metal (nWFM) formed on the respective channel body. The pWFM and nWFM may be switched in the above example to provide multi-threshold voltage devices for a p-type device array according to various embodiments. Although the band diagram <NUM> has been described in connection with silicon, similar principles described herein may be used in connection with other suitable semiconductor materials in other embodiments. Furthermore, suitable electrode materials other than workfunction metals may be used in other embodiments.

<FIG> schematically illustrates a cross-section side view of transistor devices with various threshold voltages during various stages of fabrication, in accordance with some embodiments. Varying thicknesses of gate electrode material may be formed in gate electrode regions (hereinafter "regions") corresponding with devices n0, n1, n2, p2, p1 and p0 to provide varying threshold voltages for devices n0, n1, n2, p2, p1 and p0 according techniques described in connection with <FIG>. The regions may include openings over the channel body <NUM> for each of the devices n0, n1, n2, p2, p1 and p0, as can be seen. According to various embodiments, the devices n0, n1, n2, p2, p1 and p0 may correspond with the similarly labeled devices n0, n1, n2, p2, p1 and p0 in <FIG>.

At 400a, a transistor structure is depicted along a lengthwise direction (e.g., indicated by arrow L) of a channel body <NUM> subsequent to depositing and patterning a dielectric material <NUM> to form openings over respective regions of the channel body <NUM> for the devices n0, n1, n2, p2, p1 and p0, depositing a gate dielectric <NUM> onto exposed surfaces of the channel body <NUM> and depositing a thickness of electrode material <NUM> on the channel body <NUM> (e.g., on the gate dielectric <NUM>) in a region corresponding with the p0 device. The term "transistor structure" used herein may include a structure that includes portions of multiple transistors in some embodiments. For example, in the depicted embodiment, six transistor gates are represented corresponding with devices n0, n1, n2, p2, p1 and p0. According to the invention, the channel body <NUM> is a fin structure disposed on a semiconductor substrate (e.g., bulk or silicon-on-insulator (SOI)) and the gate dielectric <NUM> and the electrode material <NUM> are further disposed on at least a portion of sidewall surfaces of the fin structure in addition to a top surface of the fin structure. The gate dielectric <NUM> includes a film that is disposed between the electrode material <NUM> and the channel body <NUM>. The electrode material <NUM> may be a workfunction metal that modifies a threshold voltage of a transistor device. In some embodiments, the electrode material <NUM> may be referred to as a workfunction modifying layer.

According to various embodiments, at 400a, the transistor structure is depicted subsequent to depositing a thickness of electrode material <NUM> on the channel body <NUM> in all regions corresponding with respective devices n0, n1, n2, p2, p1 and p0 and removing the electrode material <NUM> from the regions corresponding with all devices n0, n1, n2, p2, p1 except device p0. An example technique for performing such deposition and removal process at 400a is described in connection with <FIG>.

<FIG> schematically illustrates an example patterning technique to form the transistor devices of <FIG>, in accordance with some embodiments. At 500a, a transistor structure is depicted subsequent to forming openings in dielectric material <NUM> over a channel body <NUM> in regions corresponding with device p0 and p1 of <FIG>. Device g1 may represent one or more of the devices in <FIG> where the electrode material is removed. For example, device g1 may represent any one or more of the devices n0, n1, n2, p2 and p1 at 400a, the devices n0, n1, n2 and p2 at 400b, the devices n0 and n1 at 400c, and/or device n0 at 400d. Device g0 may represent one or more of the devices in <FIG> where the electrode material remains. A gate dielectric (e.g., gate dielectric <NUM> of <FIG>) is deposited onto the channel body <NUM> in the openings, but is not shown in <FIG> for simplicity.

At 500b, the transistor structure is depicted subsequent to depositing an electrode material <NUM> onto the channel body <NUM> in the openings. The deposition of the electrode material <NUM> may be conformal, as can be seen, in some embodiments.

At 500c, the transistor structure is depicted subsequent to depositing a pattern transfer layer <NUM> (e.g., photosensitive material) on the electrode material <NUM>.

At 500d, the transistor structure is depicted subsequent to removing a portion of the pattern transfer layer <NUM> over a region where the underlying electrode material <NUM> is to be removed. For example, a patterning process such as photolithography or etch processes may be used to expose and remove select portions of the pattern transfer layer <NUM>.

At 500e, the transistor structure is depicted subsequent to etching the electrode material <NUM> that is not protected by the pattern transfer layer <NUM>. In the depicted embodiment, the electrode material <NUM> is removed from the channel body <NUM> in the region of device p1, but remains on the channel body <NUM> in the region of device p0.

At 500f, the pattern transfer layer <NUM> may be removed using any suitable technique such as, for example, a photoresist strip process.

Returning again to <FIG>, at 400b, the transistor structure is depicted subsequent to depositing a thickness of electrode material <NUM> on the channel body <NUM> in regions corresponding with respective devices n0, n1, n2, p2, p1 and p0 and removing the electrode material <NUM> from the regions corresponding with devices n0, n1, n2, p2, but not from regions corresponding with devices p0 and p1. In this manner, another thickness of electrode material <NUM> is deposited at 400b onto the thickness of the electrode material <NUM> remaining on the channel body <NUM> in the region of device p0 at 400a to provide a greater thickness of electrode material <NUM> in the p0 region than a thickness of electrode material <NUM> in the p1 region.

The deposition and removal process of electrode material <NUM> at 400b may comport with embodiments described in connection with actions 500a through 500f in <FIG>. A thickness of the electrode material <NUM> that is deposited at each of actions 400a-d may range from ~<NUM> Angstrom to <NUM> Angstroms in some embodiments. In one embodiment, the thickness of the electrode material <NUM> that is deposited at each of actions 400a-d is about <NUM> Angstroms. In such embodiment, at 400b, the thickness of electrode material <NUM> in the p0 region is about <NUM> Angstroms and the thickness of electrode material in the p1 region is about <NUM> Angstroms. Other suitable thicknesses may be used in other embodiments.

At 400c, the transistor structure is depicted subsequent to depositing a thickness of electrode material <NUM> on the channel body <NUM> in regions corresponding with respective devices n0, n1, n2, p2, p1 and p0 and removing the electrode material <NUM> from the regions corresponding with devices n0 and n1, but not from regions corresponding with devices p0, p1, p2 and n2. In this manner, another thickness of electrode material <NUM> is deposited at 400c onto the thickness of the electrode material <NUM> remaining on the channel body <NUM> in the regions of devices p0 and p1 at 400b to provide a greater thickness of electrode material <NUM> in the p0 region than a thickness of electrode material <NUM> in the p1 region and a greater thickness of electrode material <NUM> in the p1 region than a thickness of electrode material <NUM> in the p2, n2 regions, as can be seen. The deposition and removal process of electrode material <NUM> at 400c may comport with embodiments described in connection with actions 500a through 500f in <FIG>.

At 400d, the transistor structure is depicted subsequent to depositing a thickness of electrode material <NUM> on the channel body <NUM> in regions corresponding with respective devices n0, n1, n2, p2, p1 and p0 and removing the electrode material <NUM> from the regions corresponding with device n0, but not from regions corresponding with devices p0, p1, p2, n2 and n1. In this manner, another thickness of electrode material <NUM> is deposited at 400d onto the thickness of the electrode material <NUM> remaining on the channel body <NUM> in the regions of devices p0, p1, p2 and n2 at 400c to provide a greater thickness of electrode material <NUM> in the p0 region than a thickness of electrode material <NUM> in the p1 region, a greater thickness of electrode material <NUM> in the p1 region than a thickness of electrode material <NUM> in the p2, n2 regions, and a greater thickness of electrode material <NUM> in the p2, n2 regions than a thickness of electrode material <NUM> in the n1 region, as can be seen. The deposition and removal process of electrode material <NUM> at 400d may comport with embodiments described in connection with actions 500a through 500f in <FIG>.

At 400e, the transistor structure is depicted subsequent to depositing a thickness of another electrode material <NUM> on the electrode material <NUM>. The electrode material <NUM> disposed on the channel body <NUM> in regions corresponding with devices pO, p1, p2, n2 and n1 may have a same chemical composition and the other electrode material <NUM> has a chemical composition that is different than the electrode material <NUM>. In some embodiments, the electrode material <NUM> may be one of an n-type or p-type material and the electrode material <NUM> may be n-type if the electrode material <NUM> is p-type or the electrode material <NUM> may be p-type if the electrode material <NUM> is n-type. For example, in some embodiments, the electrode material <NUM> may be pWFM and the electrode material <NUM> may be nWFM. A thickness of the other electrode material <NUM> on the channel body <NUM> in the region of device nO may be greater than a thickness of the electrode material <NUM> on the channel body <NUM> in the regions of devices n1, n2, p2, p1, and pO, as can be seen. In some embodiments, the electrode material <NUM> may be a fill material and may not be a workfunction metal in some embodiments.

In some embodiments, the other electrode material <NUM> may fill the openings over the regions corresponding with devices pO, p1, p2, n2, n1 and nO. A planarizing process such as, for example, chemical mechanical polish (CMP) may be used to remove excess amounts of the electrode material <NUM> and to provide a substantially planar surface.

According to the invention, the channel body <NUM> is composed of undoped semiconductor material. Modulation of threshold voltage for transistors (e.g., devices nO, n1, n2, p2, p1 and pO) may be accomplished solely by varying thickness of the electrode material <NUM> without implanting the channel body <NUM> with n-type or p-type impurities, which may result in transistors (e.g., FINFET transistors) having greater switching speed for a given leakage level, greater carrier mobility and reduced transistor performance variation.

In some embodiments, a thickness of the electrode material <NUM> generally increases or stays the same in a first direction parallel with the lengthwise direction (e.g., indicated by arrow L) of the channel body <NUM> and generally decreases or stays the same in a second direction that is perpendicular with the first direction, as can be seen. For example, at 400c-e, the electrode material <NUM> on the channel body <NUM> in the region of device p1 may be disposed between the electrode material <NUM> on the channel body <NUM> in the region of device pO and p2 and may have a thickness that is greater than the electrode material <NUM> on the channel body <NUM> in the region of device P2 and smaller than the electrode material <NUM> on the channel body <NUM> in the region of device p0. In some embodiments a thickness of the electrode material <NUM> of device p0 at 400e is equal to <NUM> Angstroms or less. Other suitable thicknesses may be used in other embodiments.

Other suitable techniques to provide a variation of thickness of electrode material <NUM> may be used in other embodiments including, for example, patterning processes that allow selective deposition in p0 device region at 400a, selective deposition in p0 and p1 at 400b, and so forth. For example, a mask or other protective barrier may be used to protect regions of devices p1, p2, n2, n1 and n0 during deposition of electrode material <NUM> at 400a and to protect regions of devices p2, n2, n1, and n0 during deposition of electrode material <NUM> at 400b, and so forth.

<FIG> schematically illustrates another example band diagram <NUM> for transistor devices with various threshold voltages, in accordance with some embodiments. The band diagram <NUM> may depict workfunction energy levels (in dashed form) corresponding with threshold voltage differences between each of a plurality of multi-threshold devices n0, n1, n2, p2, p1, p0 formed using silicon. As can be seen, a threshold voltage of device n0 (e.g., nearest a conduction band of silicon) may be less than a threshold voltage of device n1, which may be less than a threshold voltage of device n2. A threshold voltage of device p2 may be less than a threshold voltage of device p1, which may be less than a threshold voltage of device p0 (e.g., nearest a valence band of silicon). In some embodiments, the workfunction of devices n2, p2 may be the same or substantially the same. In some embodiments, a difference between each of the threshold voltages (e.g., between n0 and n1, between n1 and n2, p2, etc.) is from <NUM> millivolts (mV) to <NUM> mV or more. In one embodiment, the difference between each of the threshold voltages is about <NUM> mV. Differences between each of the threshold voltages may have other suitable values in other embodiments.

The variation of threshold voltages of the devices n0, n1, n2, p2, p1, p0 may be achieved using different thicknesses of gate electrode material, which may change a workfunction of the gate instead of or in addition to creating a difference in Fermi level of an underlying channel body by doping. For example, variation of threshold voltages in n-type devices may be achieved by varying a thickness of a p-type gate electrode (e.g., workfunction modifiying layer) and variation of threshold voltages in p-type devices may be achieved by varying a thickness of an n-type gate electrode (e.g., workfunction modifiying layer). For example, threshold voltage of n-type devices may be modified by inserting thin layers of p-type work function metal in another otherwise n-type workfunction metal stack (e.g., n-type workfunction fill material).

In the depicted embodiment, for an n-type device array, layers Q1 and Q2 may each have a corresponding arrow(s) that represents a different thickness of a p-type workfunction metal (pWFM) formed on a channel body to modulate the threshold voltages of n0, n1, n2/p2, p1 and p0. That is, layer Q1 may represent deposition of a same thickness of pWFM in two regions and layer Q2 may represent a deposition of a thickness of pWFM that is greater than a thickness of layer Q1 in a single region of the two regions. The layer DMG may not have a thickness of pWFM at all and may represent a layer of sacrificial material used to provide a replacement nWFM as described in connection with <FIG>. The pWFM and nWFM may be switched in the above example to provide multi-threshold voltage devices for a p-type device array according to various embodiments. Although the band diagram <NUM> has been described in connection with silicon, similar principles described herein may be used in connection with other suitable semiconductor materials in other embodiments. Furthermore, suitable electrode materials other than workfunction metals may be used in other embodiments.

<FIG> schematically illustrates a cross-section side view of transistor devices with various threshold voltages during various stages of fabrication, in accordance with some embodiments. Varying thicknesses of gate electrode material may be formed in regions corresponding with devices n0, n1, n2, p2, p1 and p0 to provide varying threshold voltages for devices n0, n1, n2, p2, p1 and p0 according techniques described in connection with <FIG>. According to various embodiments, the devices n0, n1, n2, p2, p1 and p0 may correspond with the similarly labeled devices n0, n1, n2, p2, p1 and p0 in <FIG>. Not all numeric labels are repeated in each of the actions 700a through 700e for the sake of clarity and simplicity.

At 700a, a transistor structure is depicted along a lengthwise direction (e.g., indicated by arrow L) of a channel body <NUM> subsequent to depositing and patterning a dielectric material <NUM> to form openings over respective regions of the channel body <NUM> for the devices n0, n1, n2, p2, p1 and p0 and depositing a gate dielectric <NUM> onto exposed surfaces of the channel body <NUM>. According to the invention, the channel body <NUM> is a fin structure disposed on a semiconductor substrate (e.g., bulk or silicon-on-insulator (SOI)). The exposed surfaces of the channel body <NUM> may include, for example, top surfaces and at least a portion of opposing sidewall surfaces of each fin structure in the region where openings are formed in the dielectric material <NUM>. The gate dielectric <NUM> is disposed on at least a portion of sidewall surfaces of the fin structure in addition to a top surface of the fin structure. In some embodiments, the gate dielectric <NUM> may be conformally deposited to form a film of substantially uniform thickness on exposed surfaces of the transistor structure including on the channel body <NUM> and the dielectric material <NUM>. The gate dielectric <NUM> may comport with embodiments described in connection with <FIG> and vice versa.

At 700b, the transistor structure is depicted subsequent to depositing a thickness of electrode material <NUM> on the channel body <NUM> (e.g., on the gate dielectric <NUM>) in a region corresponding with the devices p2 and n2. In some embodiments, a thickness of electrode material <NUM> may be deposited on the channel body <NUM> in all regions corresponding with respective devices n0, n1, n2, p2, p1 and p0 and removing the electrode material <NUM> from the regions corresponding with all devices n0, n1, n2, p2, p1 except devices p2 and n2. The deposition of the electrode material <NUM> at 700b may correspond with the Q1 layer of <FIG>. The deposition and removal process of electrode material <NUM> at 700b may comport with embodiments described in connection with actions 500a through 500f in <FIG>.

At 700c, the transistor structure is depicted subsequent to depositing a thickness of electrode material <NUM> on the channel body <NUM> in regions corresponding with respective devices n0, n1, n2, p2, p1 and p0 and removing the electrode material <NUM> from the regions corresponding with devices n0 and p1 but not from regions corresponding with devices p0, p2, n2 and n1. In this manner, another thickness of electrode material <NUM> is deposited at 700c onto the thickness of the electrode material <NUM> remaining on the channel body <NUM> in the region of devices p2, n2 at 700b to provide a greater thickness of electrode material <NUM> in the p2 and n2 regions than a thickness of electrode material <NUM> in the p0 and n1 regions. The deposition of the electrode material <NUM> at 700c may correspond with the Q2 layer of <FIG>.

The deposition and removal process of electrode material <NUM> at 700c may comport with embodiments described in connection with actions 500a through 500f in <FIG>. A thickness of the electrode material <NUM> that is deposited at each of actions 700b and 700c may range from ~<NUM> Angstrom to <NUM> Angstroms in some embodiments. In some embodiments, the thickness of the electrode material <NUM> that is deposited at each of actions 700b and 700c is <NUM> Angstroms to <NUM> Angstroms. In one embodiment, the thickness of the electrode material <NUM> that is deposited at each of actions 700b and 700c is about <NUM> Angstroms. In such embodiment, at 700c, the thickness of electrode material <NUM> in the p2 and n2 regions is about <NUM> Angstroms and the thickness of electrode material in the p0 and n1 regions is about <NUM> Angstroms. Other suitable thicknesses may be used in other embodiments.

At 700d, the transistor structure is depicted subsequent to depositing another electrode material <NUM> in regions p0 and p1 and a sacrificial material <NUM> in regions p2, n2, n1 and n0. In some embodiments, the electrode material <NUM> disposed on the channel body <NUM> in regions corresponding with devices p0, p2, n2 and n1 may have a same chemical composition. In some embodiments, the electrode material <NUM> is a p-type material (e.g., pWFM) and the other electrode material <NUM> may be any suitable material to serve as a fill material of a pWFM stack including, for example, n-type or p-type materials that are more n-type (e.g., farther from valence band edge) relative to the electrode material <NUM>. In a case where the electrode material <NUM> is an n-type material, the other electrode material <NUM> may be any suitable material to serve as a fill material of a nWFM stack including, for example, n-type or p-type materials that are more p-type (e.g., closer to valence band edge) relative to the electrode material <NUM>. In some embodiments, the other electrode material <NUM> may be a composite material that provides a desired workfunction according to a workfunction energy level of the composite material. In some embodiments, the other electrode material <NUM> may be a same material as electrode material <NUM> such that devices p0 and p1 have a same workfunction. The sacrificial material <NUM> may include any suitable sacrificial material including, for example, silicon oxide.

An example technique for making the transistor structure depicted at 700d from the transistor structured depicted at 700c is described in connection with <FIG> schematically illustrates an example patterning technique to form the transistor devices of <FIG>, in accordance with some embodiments. The transistor structures depicted at 800a1, 800b1, 800c1, 800d1, 800e1, 800f1, 800g1, 800h1, 800i1, 800j1 and 800k1 are cross-section side views along a lengthwise direction of a single channel body <NUM> while the transistor structures depicted at 800a2, 800b2, 800c2, 800d2, 800e2, 800f2, 800g2, 800h2, 800i2, 800j2 and 800k2 are cross-section side views perpendicular to the lengthwise direction and depicting multiple channel bodies 104a adjacent to one another. For example, the channel body <NUM> depicted at 800a1 may be one of the channel bodies 104a at 800a2. The transistor structure at 800a1 and 800a2 may be at a same stage of fabrication, and so forth for 800b1 and 800b2, 800c1 and 800c2, etc. The transistor structure may have more or fewer channel bodies <NUM> than depicted in other embodiments. Not all numeric labels are repeated in the depictions of <FIG> for the sake of clarity and simplicity.

At 800a1 and 800a2, a transistor structure is depicted subsequent to forming openings in dielectric material <NUM> over regions corresponding with devices g2 and g3 and depositing a gate dielectric <NUM> on exposed surfaces of the channel body <NUM> or channel bodies 104a. The device g2 may represent any device that is configured to receive the sacrificial material <NUM> and the device g3 may represent any device that is configured to receive the electrode material <NUM>. For example, the device g2 may represent devices p2, n2, n1 and n0 and the device g3 may represent devices p0 and p1 at 700d of <FIG>. In some embodiments, the device g3 and/or g2 may have electrode material <NUM> disposed in the respective openings at 800a1 and 800a2. For example, the device g3 at 800a1 and 800a2 may represent the p0 device at 700c or the device g2 at 800a1 and 800a2 may represent the p2, n2, n1 devices at 700c. Subsequent actions of <FIG> may be performed on the devices g2 and/or g3 having thicknesses of electrode material <NUM> described in connection with 700c.

At 800b1 and 800b2, the transistor structure is depicted subsequent to depositing a pattern transfer layer <NUM> on the dielectric material <NUM> to fill the openings in regions of devices g2 and g3. In some embodiments, the pattern transfer layer <NUM> may comprise carbon and may be referred to as a carbon underlayer. The pattern transfer layer may be composed of other suitable materials in other embodiments, including, for example, silicon oxide, photoresist materials and the like.

At 800c1 and 800c2, the transistor structure is depicted subsequent to removing material of the pattern transfer layer <NUM> from the opening over the device g2 and/or any other openings that are configured to receive the sacrificial material <NUM>. The pattern transfer layer <NUM> may be removed using any suitable patterning process including, for example, lithography and/or etch processes. The removal process at 800c1 and 800c2 does not substantially remove electrode material <NUM>, if any, in the openings of devices g2 and g3.

At 800d1 and 800d2, the transistor structure is depicted subsequent to depositing sacrificial material <NUM> in the opening over the device g2 and/or any other openings where the pattern transfer layer <NUM> has been removed.

At 800e1 and 800e2, the transistor structure is depicted subsequent to performing a polish process or other suitable process to expose the pattern transfer layer <NUM>. The polish process may provide a substantially planar surface of the sacrificial material <NUM> and the pattern transfer layer <NUM>, as can be seen.

At 800f1 and 800f2, the transistor structure is depicted subsequent to removing the pattern transfer layer <NUM> in the region of device g3. The pattern transfer layer may be removed by any suitable process including, for example, a selective etch process that is configured to remove material of the pattern transfer layer <NUM> while leaving the material of the sacrificial material <NUM>. The removal process at 800f1 and 800f2 does not substantially remove electrode material <NUM>, if any, in the openings of devices g2 and g3.

At 800g1 and 800g2, the transistor structure is depicted subsequent to depositing electrode material <NUM> in the openings where pattern transfer layer <NUM> has been removed. In some embodiments, the electrode material <NUM> may be a PMOS gate stack material. The electrode material <NUM> may be deposited on any electrode material <NUM>, if any, in the openings of devices g2 and g3.

At 800h1 and 800h2, the transistor structure is depicted subsequent to a polishing process or other suitable process that removes material of the deposited electrode material <NUM> to expose underlying material of the sacrificial material <NUM> in the region of device g2. The transistor structure at 800h1 and 800h2 may represent the same stage of fabrication as the transistor structure 700d of <FIG>.

Referring again to <FIG>, at 700e, the transistor structure is depicted subsequent to replacing the sacrificial material <NUM> with another electrode material <NUM>. In some embodiments, the electrode material <NUM> may be one of an n-type or p-type material and the electrode material <NUM> may be n-type if the electrode material <NUM> is p-type or the electrode material <NUM> may be p-type if the electrode material <NUM> is n-type. For example, in some embodiments, the electrode material <NUM> may be pWFM and the electrode material <NUM> may be nWFM. In some embodiments, the electrode material <NUM> may have a different chemical composition than electrode material <NUM>. A thickness of the other electrode material <NUM> on the channel body <NUM> in the region of device n0 may be greater than a thickness of the electrode material <NUM> on the channel body <NUM> in the regions of devices n1, n2, p2 and p0, as can be seen. According to various embodiments, the transistor structure at 700e may be formed according to techniques described in connection with actions at 800i1, 800i2 through 800k1, 800k2 of <FIG>.

Referring again to <FIG>, at 800i1 and 800i2, the transistor structure is depicted subsequent to removing the sacrificial material <NUM> from the region of the device g2. The sacrificial material <NUM> may be removed using any suitable process including, for example a selective etch process that removes only the sacrificial material <NUM>. The removal process at 800i1 and 800i2 does not substantially remove electrode material <NUM>, if any, in the openings of devices g2 and g3.

At 800j1 and 800j2, the transistor structure is depicted subsequent to depositing another electrode material <NUM> in the region of device g2 where the sacrificial material <NUM> has been removed. The electrode material <NUM> may be deposited on any electrode material <NUM>, if any, in the openings of devices g2 and g3.

At 800k1 and 800k2, the transistor structure is depicted subsequent to removing and planarizing the electrode materials <NUM> and <NUM>. The removing and planarizing may be performed, for example, using a polish process or any other suitable technique.

In some embodiments, the techniques of <FIG> may be further simplified by using a material for the pattern transfer layer <NUM> that can withstand deposition of electrode material. For example, at 800d1 and 800d2, the electrode material <NUM> or <NUM> may be deposited instead of sacrificial material <NUM> and the other of the electrode material <NUM> or <NUM> that is not deposited at 800d1 and 800d2 may be deposited at 800g1 and 800g2 according to various embodiments.

<FIG> schematically illustrates yet another example band diagram <NUM> for transistor devices with various threshold voltages, in accordance with some embodiments. The band diagram <NUM> may depict workfunction energy levels (in dashed form) corresponding with threshold voltage differences between each of a plurality of multi-threshold devices n0, n1, n2, p2, p1, p0 formed using silicon. As can be seen, a threshold voltage of device n0 (e.g., nearest a conduction band of silicon) may be less than a threshold voltage of device n1, which may be less than a threshold voltage of device n2. A threshold voltage of device p2 may be less than a threshold voltage of device p1, which may be less than a threshold voltage of device p0 (e.g., nearest a valence band of silicon). In some embodiments, the workfunction of devices n2, p2 may be the same or substantially the same. In some embodiments, a difference between each of the threshold voltages (e.g., between n0 and n1, between n1 and n2, p2, etc.) is from <NUM> millivolts (mV) to <NUM> mV or more. In one embodiment, the difference between each of the threshold voltages is about <NUM> mV. Differences between each of the threshold voltages may have other suitable values in other embodiments.

The variation of threshold voltages of the devices n0, n1, n2, p2, p1, p0 may be achieved using different thicknesses of gate electrode material, which may change a workfunction of the gate instead of or in addition to creating a difference in Fermi level of an underlying channel body by doping. For example, variation of threshold voltages in n-type devices may be achieved by varying a thickness of a p-type gate electrode and variation of threshold voltages in p-type devices may be achieved by varying a thickness of an n-type gate electrode.

In the depicted embodiment, for an n-type device array, layers Q1 and Q2 may each have a corresponding arrow that represents a different thickness of a p-type workfunction metal (pWFM) formed on a channel body to modulate the threshold voltages of n0, n1, n2/p2, p1 and p0. The arrows of layers Q1 and Q3 may represent deposition of a thickness of pWFM and the arrows of layer Q2 may represent deposition of a thickness of nWFM. The pWFM and nWFM may be switched in the above example to provide multi-threshold voltage devices for a p-type device array according to various embodiments. Although the band diagram <NUM> has been described in connection with silicon, similar principles described herein may be used in connection with other suitable semiconductor materials in other embodiments. Furthermore, suitable electrode materials other than workfunction metals may be used in other embodiments.

<FIG> schematically illustrates a cross-section side view of transistor devices with various threshold voltages during various stages of fabrication, in accordance with some embodiments. At 1000a and 1000b, a transistor structure depicted subsequent to actions described in connection with respective actions at 700a and 700b of <FIG> and/or actions at 400a of <FIG>. At 1000b, the transistor structure is depicted subsequent to depositing a thickness of electrode material <NUM> in the region of the p0 device. The thickness of electrode material <NUM> at 1000b may correspond with the layer Q3 of <FIG>.

At 1000c, the transistor structure is depicted subsequent to depositing a thickness of another electrode material <NUM> in the regions of the p2, n2 and n0 devices. The thickness of the electrode material <NUM> deposited at 1000c may correspond with the layer Q2 of <FIG>. For example, in some embodiments, the electrode material <NUM> may be deposited in regions of all the devices p0, p1, p2, n2, n1 and n0 and subsequently removed from only regions of p0, p1 and n1 devices according to techniques described herein (e.g., <FIG>). In some embodiments, an etch process may selectively remove the electrode material <NUM> without substantially removing the electrode material <NUM>.

At 1000d, the transistor structure is depicted subsequent to depositing another thickness of the electrode material <NUM> in the regions of the p0, p1, p2, and n2 devices. The thickness of the electrode material <NUM> deposited at 1000d may correspond with the layer Q1 of <FIG>. For example, in some embodiments, the electrode material <NUM> may be deposited in regions of all the devices p0, p1, p2, n2, n1 and n0 and subsequently removed from only regions of n1, n0 devices according to techniques described herein (e.g., <FIG>). In some embodiments, an etch process may selectively remove the electrode material <NUM> without substantially removing the electrode material <NUM> (e.g., from region of device n0).

At 1000e, the transistor structure is depicted subsequent to depositing another electrode material <NUM> to fill a remaining region, if any, in the regions of the devices p0, p1, p2, n2, n1 and n0. In some embodiments, the electrode material <NUM> is a p-type material such as pWFM, the electrode material <NUM> is an n-type material such as nWFM and the electrode material <NUM> is an n-type material. In some embodiments, the electrode material <NUM> may be an n-type or p-type material that provides a fill material that is more p-type than electrode material <NUM> and more n-type than electrode material <NUM>. Dimensions of the thicknesses for the deposition actions described in connection with <FIG> may comport with embodiments described in connection with <FIG> and <FIG>.

<FIG> schematically illustrates a flow diagram for a method <NUM> of fabricating transistor devices with various threshold voltages, in accordance with some embodiments. The method <NUM> may comport with various techniques and configurations described in connection with <FIG> and vice versa, according to various embodiments.

At <NUM>, the method <NUM> may include providing a channel body (e.g., channel body <NUM> of <FIG> and <FIG>) disposed on a semiconductor substrate (e.g., die <NUM>). The channel body includes, according to the invention, a fin structure or, according to embodiments not forming part of the invention, any other suitable channel body which may benefit from principles described herein. In some embodiments, providing the channel body may include forming the channel body by, for example, patterning and etching a semiconductor material to form fin structures in the semiconductor material.

At <NUM>, the method <NUM> may include depositing a dielectric material (e.g., dielectric material <NUM> of <FIG> and <FIG>) on the channel body. The dielectric material may include any suitable material and may be deposited using any suitable technique.

At <NUM>, the method <NUM> may include forming openings in the dielectric material corresponding with at least a first gate electrode and a second gate electrode. The openings may expose portions of the channel body and may correspond with openings formed in regions of two or more of devices n0, n1, n2, p2, p1 and p0 of <FIG> and <FIG>. The openings may be formed using any suitable technique including patterning such as lithography and/or etch.

At <NUM>, the method <NUM> may include depositing a gate dielectric (e.g., gate dielectric <NUM>) on the channel body. In some embodiments, the gate dielectric is deposited on exposed surfaces of the channel body in the openings formed at <NUM>. The gate dielectric may be deposited using any suitable technique. According to various embodiments, the gate dielectric may be formed of a material such as silicon dioxide (SiO2) or a high-k material. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

According to various embodiments, for a PMOS transistor, metals that may be used for the gate electrode (e.g., electrode material <NUM>) include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A p-type metal layer may enable the formation of a PMOS gate electrode with a workfunction that is between about <NUM> eV and about <NUM> eV. For an NMOS transistor, metals that may be used for the gate electrode (e.g., electrode material <NUM>) include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer may enable the formation of an NMOS gate electrode with a workfunction that is between about <NUM> eV and about <NUM> eV. Other suitable materials may be used to form the gate electrodes in other embodiments.

At <NUM>, the method <NUM> may include forming a first gate electrode and a second gate electrode coupled with the channel body, wherein the first gate electrode has a first thickness, the second gate electrode has a second thickness and the first thickness is greater than the second thickness. The first gate electrode and the second gate electrode may be formed according to any of the techniques described in connection with <FIG>. For example, the first gate electrode may be a workfunction electrode (e.g., electrode material <NUM> of <FIG> and <FIG>) formed in the openings of the devices p0, p1, p2, n2, n1 and n0 that has a thickness that is greater than another workfunction electrode (e.g., electrode material <NUM> of <FIG> and <FIG>) formed in the openings of the devices p0, p1, p2, n2, n1 and n0. In some embodiments, three or more gate electrodes may be formed according to techniques described herein to provide varying threshold voltages of the devices.

In some embodiments, forming the first gate electrode and the second gate electrode may include simultaneously depositing an electrode material (e.g., electrode material <NUM> of <FIG> and <FIG>) in a first region of the first gate electrode and a second region of the second gate electrode as part of a first deposition. The electrode material may be selectively removed in the second region using any suitable technique including, for example, patterning techniques. The electrode material be simultaneously deposited in the first region and the second region as part of a second deposition subsequent to selectively removing the electrode material in the second region.

In some embodiments, actions at <NUM> may include forming a third gate electrode coupled with the fin structure, the third gate electrode having a third thickness that is smaller than the second thickness. In some embodiments, actions at <NUM> may include forming a fourth gate electrode having a fourth thickness coupled with the fin structure. The fourth thickness (e.g., thickness of electrode material <NUM> at n0 in <FIG>) may be greater than the first thickness and may be composed of another electrode material (e.g., electrode material <NUM> of <FIG>) having a different chemical composition than the electrode material.

In some embodiments, another electrode material (e.g., electrode material <NUM> of <FIG>) may be deposited on the electrode material of the first gate electrode and the second gate electrode. In some embodiments, the other electrode material may fill a remainder of the opening that is not filled by the electrode material.

In some embodiments, no doping process (e.g., implantation of impurities) may be performed on the channel body to modulate a threshold voltage of one or more transistors. Modulation of the threshold voltage may be solely accomplished using varying thicknesses of workfunction material (e.g., electrode material <NUM>) in some embodiments. In some embodiments, forming the first gate electrode comprises replacing a sacrificial material with material of the first gate electrode (e.g., as described in connection with <FIG>). In some embodiments, a third gate electrode may be formed on the first gate electrode and a fourth gate electrode may be formed on the third gate electrode, wherein material of the fourth gate electrode is a fill material that is more p-type than material of the first gate electrode and more n-type than material of the third gate electrode (e.g., as described in connection with <FIG>).

Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. Embodiments of the present disclosure may be implemented into a system using any suitable hardware and/or software to configure as desired.

<FIG> schematically illustrates an example system (e.g., computing device <NUM>) that may include transistor devices with various threshold voltages as described herein, in accordance with some embodiments. The motherboard <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> may be physically and electrically coupled to the motherboard <NUM>. In some implementations, the at least one communication chip <NUM> may also be physically and electrically coupled to the motherboard <NUM>. In further implementations, the communication chip <NUM> may be part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the motherboard <NUM>. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip <NUM> may enable wireless communications for the transfer of data to and from the computing device <NUM>. The communication chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE <NUM> family), IEEE <NUM> standards (e.g., IEEE <NUM>-<NUM> Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE <NUM> compatible BWA networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE <NUM> standards. The communication chip <NUM> may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip <NUM> may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip <NUM> may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The communication chip <NUM> may operate in accordance with other wireless protocols in other embodiments.

The processor <NUM> of the computing device <NUM> may include a die (e.g., die <NUM> of <FIG>) having transistors structures with modulated threshold voltage using workfunction modifying layers as described herein. For example, the die <NUM> of <FIG> may be mounted in a package assembly that is mounted on the motherboard <NUM>. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> may also include a die (e.g., die <NUM> of <FIG>) having transistors structures with modulated threshold voltage using workfunction modifying layers as described herein. In further implementations, another component (e.g., memory device or other integrated circuit device) housed within the computing device <NUM> may contain a die (e.g., die <NUM> of <FIG>) having transistors structures with modulated threshold voltage using workfunction modifying layers as described herein.

In various implementations, the computing device <NUM> may be a mobile computing device, laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data.

The above description of illustrated implementations is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.

Claim 1:
An integrated circuit comprising:
a semiconductor substrate;
a first fin, a second fin, and a third fin wherein the first fin, the second fin and the third fin are comprised of undoped semiconductor material, and the first fin, the second fin and the third fin are disposed on the semiconductor substrate;
a first gate electrode, of a first n-type metal-oxide-semiconductor, NMOS, transistor device (n2) having a first threshold voltage, on a top surface and sidewalls of the first fin, the first gate electrode including a layer of a first electrode material (<NUM>) having a thickness above the top surface of the first fin and a layer of a second electrode material (<NUM>) having a thickness over the layer of the first electrode material (<NUM>) in the first gate electrode, the second electrode material (<NUM>) having a different chemical composition than the first electrode material (<NUM>);
a second gate electrode, of a second NMOS transistor device (n1) having a second threshold voltage, on a top surface and sidewalls of the second fin, wherein the second gate electrode includes a layer of the first electrode material (<NUM>) having a thickness above the top surface of the second fin and a layer of the second electrode material (<NUM>) having a thickness over the layer of the first electrode material (<NUM>) in the second gate electrode, the thickness of the layer of the first electrode material (<NUM>) in the second gate electrode being less than the thickness of the layer of the first electrode material (<NUM>) in the first gate electrode;
a third gate electrode, of a third n-type metal-oxide-semiconductor, NMOS, transistor device (n0) having a third threshold voltage, on a top surface and sidewalls of the third fin, the third gate electrode including a layer of the second electrode material (<NUM>) having a thickness above the top surface of the third fin; and
a first gate dielectric (<NUM>) between the first gate electrode and the first fin, a second gate dielectric between the second gate electrode and the second fin, and a third gate dielectric between the third gate electrode and the third fin; wherein,
the third threshold voltage is less than the second threshold voltage,
the second threshold voltage is less than the first threshold voltage.