Patent Description:
Document <CIT> refers to a circuit board including a substrate having a thickness in a first direction, extending in a plane perpendicular to the first direction, and having at least one of a through hole and a recess, and an optical transmission channel having an end thereof at a perimeter of the one of a through hole and a recess and having a portion thereof extending a predetermined distance from the end in a direction substantially perpendicular to the first direction, the portion being provided in the substrate or on a surface of the substrate.

Document <CIT> refers to a method of forming a photonic integrated circuit package (PIC). The method may include forming a redistribution layer (RDL) over a carrier. The method may also include forming a through hole or cavity on the redistribution layer. The method may additionally include providing a stop-ring structure, the stop-ring structure including a ring of suitable material, the stop-ring structure defining a hollow space, over the redistribution layer so that the hollow space is over the through hole or cavity. The method may further include arranging a photonic integrated circuit (PIC) die over the redistribution layer so that the photonic integrated circuit (PIC) die is on the stop-ring structure. The method may also include forming a molded package by forming a mold structure to at least partially cover the photonic integrated circuit (PIC) die to form the photonic integrated circuit package.

Document <CIT> refers to a high density interconnect arrangement that takes the form of a backplane-pluggable card, with electrical connections formed along a single (pluggable) edge and all remaining connections provided via optical fibers. An exemplary inter-connect arrangement also includes on-board optical sources and silicon photonic-based circuitry for providing optical transceiver functionality. Passively aligned fiber arrays are utilized to provide I/O connections to external elements, as well as between laser sources and on-board silicon photonics.

Document <CIT> refers to various leaf switch modules including optical network inter-faces, electrical network interfaces and packet processors. Some of the leaf switch modules as described herein are adapted for upward transmission of signals from external client devices to an electrical fabric, and include O/E converters; other leaf switch modules are adapted for downward transmission of signals from an electrical fabric to external client devices, and include E/O converters. A third type of leaf switch as described herein is adapted for both upward and downward transmission of signals, and includes both types of converter. In addition to the leaf switch modules themselves, an optoelectronic switch containing a plurality of those leaf switches is also described.

The present invention is defined in the independent claim. One aspect of the disclosure provides an integrated circuit (IC) package comprising a substrate, an IC die mounted to the substrate, one or more photonic modules attached to the substrate, and one or more serializer/deserializer (SerDes) interfaces connecting the IC die to the one or more photonic modules. The one or more SerDes interfaces may include a plurality of copper traces and the copper traces may be deposited on the substrate. In some instances, the IC die may be an application specific integrated circuit (ASIC) die. In some instances, the IC package may be configured to connect to a land grid array (LGA) socket. Power may be delivered to the IC package via the LGA socket.

In some instances, the one or more photonic modules may include a controller. The controller may manage transmission of data between its respective photonic module and the IC die. Each of the one or more photonic modules may further include a photonic integrated circuit (PIC) and fiber array. Each of the one or more SerDes interfaces may include a first side connected to a respective photonic module and a second, opposite side connected to the IC die. In some examples, the one or more photonic modules may be mounted to one or more additional substrates and the one or more additional substrates may be attached to the substrate via one or more sockets.

Another aspect of the disclosure provides an application specific integrated circuit (ASIC) package comprising a substrate, an ASIC die mounted to the substrate, one or more photonic modules attached to the substrate; one or more serializer/deserializer (SerDes) interfaces connecting the ASIC die to the one or more photonic modules, and a voltage regulator. In some instances, the voltage regulator may be mounted to the opposite side of the substrate where the ASIC die is mounted. The one or more SerDes interfaces may include a plurality of copper traces and the copper traces may be deposited on the substrate. In some examples, the substrate may be configured to connect to a land grid array (LGA) socket and power may be delivered to the voltage regulator via the LGA socket.

In some instances, each of the one or more photonic modules in the ASIC package may include a controller that manages transmission of data between its respective photonic module and the ASIC die. Each of the one or more photonic modules may further include a photonic integrated circuit (PIC) and fiber array. The one or more SerDes interfaces may include a first side and a second, opposite side, wherein for each of the SerDes interfaces, the first side connects to a respective photonic module and the second, opposite side connects to the ASIC die. The one or more photonic modules may be mounted to one or more additional substrates and wherein the one or more additional substrates may be attached to the substrate via one or more sockets.

The technology relates generally to an application specific integrated circuit (ASIC) package having an integrated photonic module and vertically integrated power regulator. As previously described, I/O systems which connect an ASIC package with other components may have insufficient bandwidth to handle the data throughput required by the ASIC die. To address this issue, I/O systems having bandwidths of around 100Gbps may be used to reduce I/O system bottlenecks. However, these I/O system are typically connected via an external connection to the ASIC package via interfaces. As the bandwidth of the interfaces are increased to handle the throughput of the I/O system and, the traces of the interfaces, which carry the signals between the I/O system and ASIC die, may cause signal loss such as through high-frequency roll-off. The signal loss may be exacerbated by the length of the traces of the interfaces from the ASIC die to the externally located I/O system.

To reduce the amount of signal loss over an interface, the substrates through which the traces of the interface travel may be made from materials having low dielectric constants (Dk) and dielectric losses (Df). Moreover, the roughness of the surface of the traces may be reduced to further limit the amount of signal loss. However, even with the use of low Dk and Df materials, and smoothed traces, only marginal improvements to the amount of signal loss may be realized.

To remove or further remediate the issue of signal loss, I/O systems including photonic modules, may be integrated into the ASIC package. By integrating the photonic modules, the length of the traces connecting the photonic modules to the ASIC die may be reduced, thereby minimizing the amount of signal loss. In this regard, the length of the traces of the interfaces may be integrated into a low Dk and Df PCB. The traces which may connect the ASIC die to an external I/O system, may be around <NUM> inches. During operation at <NUM> Gbps, the <NUM> inch traces may experience a signal loss of around <NUM> dB.

By integrating the photonic modules into the ASIC package and attaching the photonic modules 220A and 220B to the same substrate as the ASIC die <NUM>, as shown in the top-down cutaway view of ASIC package <NUM> in <FIG>, the length of the traces 291A and 292B may be reduced. In this regard, the traces 291A and 291B in the interfaces from the ASIC die <NUM> to the integrated photonics modules 220A and 220B may be reduced to around <NUM>-<NUM>. Thus, at operating speeds of <NUM> Gbps, the amount of signal loss may be reduced by around <NUM> dB, relative to the signal loss over interfaces connecting an ASIC die with an I/O system outside of the ASIC package. As such, the PCB into which the traces of the interface are integrated may have higher Dk and Df values, which may save material costs, production costs, and while still providing improved signal transmission. These benefits may continue to be realized at even higher operating speeds, such as <NUM> Gbps or more.

<FIG> illustrate examples of ASIC package configurations with integrated photonic modules. For example, and as shown in <FIG>, the ASIC package <NUM> includes an ASIC die <NUM> mounted to a substrate <NUM> via a socket <NUM>. The socket may be a ball grid array (BGA), land grid array (LGA), pin grid array (PGA), or other such socket connections. The ASIC package <NUM> further includes photonic modules, shown as dashed boxes 220A and 220B including fiber arrays 226A, 226B, photonic integrated circuits (PICs) 224A, 224B, and controllers 222A, 222B, which may operate as an I/O system for the ASIC package. The photonic modules 220A and 220B may be attached to a substrate, such as substrate <NUM> as further shown in <FIG>. The attachment of the photonic modules 220A and 220B may be either permanent or via a removable connection, as described herein. An interface, such as a serializer/deserializer (SerDes) interface (described herein), shown by the double-sided arrow lines 290A and 290B in <FIG>, connects the photonic modules 220A and 220B to the ASIC die <NUM>.

The ASIC package <NUM> may also include a voltage regulator <NUM> mounted to the opposite side of the substrate <NUM> where the ASIC die <NUM> is mounted. Power may be delivered to the ASIC die <NUM> by the voltage regulator <NUM>, as shown by the dashed-line arrow <NUM> in <FIG>. The ASIC package <NUM> may be configured to connect to a socket, such as LGA socket <NUM>, through which power from an external source, shown by the double-sided dashed arrow <NUM> may be provided to the voltage regulator <NUM>. The ASIC package <NUM> may include a housing, such as housing <NUM> in which the components of the ASIC package <NUM> are positioned.

A photonic module, such as photonic modules 220A and 220B, may include any number of components including fiber arrays 226A, 226B, photonic integrated circuits (PICs) 224A, 224B, and/or controllers 222A, 222B. The components in a photonic module may be discrete elements and or combinations of elements. For instance, a fiber array may be integrated into a PIC and/or a PIC may be integrated into a controller.

A fiber array, such as fiber arrays 226A and 226B may be a collection of one or more fiber optic cables capable of carrying optical signals into or out of the ASIC package, such as ASIC package <NUM>. The fiber arrays may be one-dimensional (1D) arrays or <NUM>-dimensional (2D) arrays of fiber optic cables. The fiber arrays may be coupled to the PIC via a side or vertical coupling.

The fiber arrays may be mounted onto supports. For example, and as shown in <FIG>, fiber array 226A is mounted onto support 228A and fiber array 226B is mounted onto support 228B. The supports may attach the fiber arrays to a substrate, such as substrate <NUM>. Depending upon the shape and size of the supports, the physical height and positioning of the fiber arrays may be adjusted. For instance, by increasing the height of a support, such as support 228A, fiber array 226A that is attached to the support may be positioned further from the substrate <NUM> and higher in the ASIC package <NUM>. In some instances, the supports 228A, 228B may be configured to position the fiber arrays 226A, 226B at particular angles relative to the substrate.

A photonic integrated circuit, such as PICs 224A and 224B may be configured to convert electrical signals into optical signals and/or convert optical signals into electrical signals. For instance, and referring to <FIG>, the ASIC package <NUM> includes two photonic modules 220A and 220B, with each photonic module including a PIC, 224A and 224B. The first PIC 224A may be configured to receive optical signals from the attached fiber array 226A and convert the optical signals into electrical signals. The first PIC may then pass the electrical signals to the attached controller 222A. The second PIC 224B may be configured to receive electrical signals from the attached controller 222B and convert the electrical signals to optical signals to be passed out of the ASIC package by the attached fiber array 226B. In some instances, the PICs may include one or more waveguides for guiding optical signals between the PICs and fiber arrays.

A controller may be used to direct the flow of electrical signals between the ASIC die and the PIC. For instance, and as shown in <FIG>, the ASIC package <NUM> includes two controllers 222A and 222B. The controllers 222A and 22B may be a trans-impedance amplifier (TIA) and/or integrated circuit (IC) configured to modulate or demodulate signals. For instance, controller 222A may receive a modulated signal from PIC 224A, such as a signal which has been modulated using <NUM>-level pulse amplitude modulation (PAM4) or some other type of modulation. Controller 222A may demodulate the signal and pass it through an interface, such as interface 290A to the ASIC die <NUM>. Controller 222B may receive an unmodulated signal from the ASIC die <NUM> through interface 290B. The controller 222B may modulate the using PAM4 or some other modulation and pass the modulated signal to PIC 224A. In some instances the controllers may amplify signals or perform other digital signal processing on the signals.

According to the claimed invention, the photonic modules are connected to the ASIC die via a SerDes interface. For instance, and as shown in <FIG>, the SerDes interfaces (illustrated by the double sided arrows 290A and 290B) connect the ASIC die <NUM> to the two photonic modules 220A and 220B. Referring back to <FIG>, the SerDes interface may include a collection of traces, such as copper traces 291A and 291B, which connect the ASIC die <NUM> to the photonic modules 220A and 220B. The copper traces 291A and 291B may be printed directly onto the substrate and/or be implemented via wires.

At each end of the traces of the interface may be a serializer and/or a deserializer which may connect to dies and/or photonic modules. In this regard, each end of the traces may include a serializer and a deserializer to allow for two-way communication over the traces. For instance, and as shown in the exploded view of interface 290A in <FIG>, serializer 293A on a first end of some of the traces 291A is connected to a deserializer 294B on the opposite side of the traces 291A. Similarly, serializer 293B is found on the opposite side of the traces as deserializer 294A. Although only nine traces are shown in each SerDes interface 290A and 290B, any number of traces may be in an interface. In some instances, the serializers and deserializers may be integrated into the controller and/or ASIC. In some examples, the serializers and deserializers may be integrated into a combined serializer/deserializer.

In operation, serializers 293A, 293B may convert parallel signals into serial signals for transmission over the traces 291A. Deserializers 294A, 294B on the other end of the traces 291A may then convert the serial signals back into parallel signals.

The components of a photonic module may be mounted to the same substrate as the ASIC die and/or a different substrate. For instance, and as shown in <FIG> and <FIG>, the components of the photonic modules 220A, 220B in are mounted to the same substrate as the ASIC die <NUM> - substrate <NUM>. By mounting the photonic modules 220A, 220B to the same substrate as the ASIC die, vertical transitions of the SerDes interfaces 290A, 290B between substrates may be avoided thereby reducing impendence which may cause signal loss.

In <FIG> and <FIG>, the components of the two photonic modules 420A and 420B, which may be compared to photonic modules 220A, 220B, are mounted to different substrates 403A and 403B, respectively. These two substrates 403A and 403B are each different than the substrate <NUM> on which the ASIC die <NUM> is mounted.

As further shown in <FIG> and <FIG>, the substrates 403A and 403B, on which the photonic modules are mounted, may be connected to the substrate <NUM> on which the ASIC die <NUM> is mounted. The connection may be formed via a high speed socket and/or soldering, such as socket 415A which connects substrate 403A to substrate <NUM> and socket 415B which connects substrate 403B to substrate <NUM>. Although <FIG> and <FIG> shown the photonic modules 420A and 420B being mounted to different substrates 403A and 403B, respectively, the photonic modules 420A and 420B may be mounted on the same substrate. The substrates may be printed circuit boards (PCBs) or other suitable materials.

ASIC packages that have photonic modules on different substrates than the ASIC die may include interfaces which connect the photonic modules to the ASIC die through the substrates. For instance, and as shown in ASIC packages <NUM> and <NUM> in <FIG> and <FIG>, respectively, SerDes interfaces, shown by the double arrowed lines 490A and 490B may connect the photonic modules 420A and 420B with ASIC die <NUM>. In this regard, SerDes interface 490A may travel through socket 415A to connect photonic module 420A on substrate 403A with the ASIC die <NUM> on substrate <NUM>. Similarly, SerDes interface 490B may travel through socket 415B to connect photonic module 420B on substrate 403B with the ASIC die <NUM> on substrate <NUM>.

By mounting the photonic modules 420A and 420B on different substrates, such as shown in ASIC packages <NUM> and <NUM> of <FIG> and <FIG>, the length of the traces in the SerDes interfaces may be longer than when the photonic modules are mounted on the same substrate as the ASIC die, such as shown in ASIC packages <NUM> and <NUM> of <FIG> and <FIG>. The increased length of the SerDes interfaces when the photonic modules are on different substrates may increase signal loss as a signal travels the SerDes traces, and travel time of the signal travel time between components may be increased. However, production yield of ASIC packages <NUM> and <NUM> may be improved relative to ASIC packages <NUM> and <NUM>, as broken components (e.g., a broken photonic module, broken ASIC die, etc.,) can be swapped out without a need to replace the entire ASIC package.

Increases in processing speed of an ASIC die, such as ASIC dies <NUM> and <NUM>, may also increase the amount of power required to operate the ASIC die. In this regard, and as shown in <FIG>, an ASIC package <NUM> may be connected to a power source (not shown) via a ball grid array (BGA) <NUM>. The BGA <NUM> may include a plurality of solder balls, such as solder ball <NUM>, formed on the base of the ASIC package <NUM>. The solder balls may be aligned with corresponding pads, such as copper pad <NUM>, formed on the substrate <NUM> where the ASIC package <NUM> is to be mounted. The solder balls are soldered to their corresponding pads to permanently mount the ASIC package <NUM> to the substrate <NUM>. For instance, solder ball <NUM> is soldered to corresponding pad <NUM> to form a solder joint. A power source may deliver power to the ASIC die <NUM>, and in some instances, photonic modules 720A and 720B, through solder joints of the BGA <NUM> and wires and/or other such connections (not shown) within the substrate <NUM>, as illustrated by dashed arrow <NUM>.

An increase in power drawn by an ASIC die <NUM> may result in an increase of heat within the ASIC package due to copper losses generated by the wires and/or other such connections which carry the power through the ASIC package <NUM> and substrate <NUM> to the ASIC die <NUM>. Copper losses, also known as "I<NUM>R losses" (where 'I' is the current flowing through the copper in wiring and 'R' is the resistance of the wiring), is the amount of heat dissipated as current passes through wiring. The increase in temperature generated by the increased power draw of the ASIC die <NUM> may result in BGA solder electromigration and potential failure of one or more solder joints. The increase of temperature may also affect the thermal performance of the ASIC die <NUM>, potentially leading failure of the ASIC die <NUM> or other components of the ASIC package <NUM>.

To reduce the amount of copper losses generated by wires, planes (e.g., copper planes), and/or other such connections which carry the power through the ASIC package to the ASIC die, a voltage regulator may be integrated into the ASIC package. In accordance with the claimed invention, a voltage regulator <NUM> is mounted to the opposite side of substrate <NUM> where ASIC die <NUM> is mounted, as shown in ASIC package <NUM> of <FIG>. And as shown in ASIC package <NUM> of <FIG>, a voltage regulator <NUM> is mounted to the opposite side of the substrate <NUM> where the ASIC die <NUM> is mounted. Power may be delivered to the voltage regulator <NUM>, <NUM> from an external power source. In this regard, the external power source may provide power to the voltage regulator <NUM>, <NUM> through a socket to which the ASIC package is mounted, as shown by the dashed double-sided arrows <NUM> and <NUM> in <FIG> and <FIG>, respectively. The voltage regulator <NUM>, <NUM> may then provide power to the ASIC die <NUM>, <NUM> via one or more wires, planes (e.g., copper planes,) and/or other such connections on or within the substrate.

The voltage regulator may maintain a consistent power draw from the external power source, thereby preventing or reducing the number of increases in power carried by the wires, traces, and/or other such connections on or within the substrate. Moreover, the length of the wires, traces, and/or other such connections between the voltage regulator and the ASIC die, such as ASIC dies <NUM> and <NUM>, may be reduced relative to when power is received by the ASIC dies <NUM> and <NUM> directly from the external power source, as shown by the dashed arrows <NUM> and <NUM> in <FIG> and <FIG>, respectively. As socket contacts on the ASIC package, such as contacts <NUM> of ASIC package <NUM>, typically have high contact resistance, heat loss generated by power flowing through the contact <NUM> may be significant. By moving the voltage regulator into the ASIC package, the amount of power flowing through the contacts <NUM> may be reduced. Thus, the heat within the ASIC packages <NUM> and <NUM> generated by copper losses may be reduced. In accordance with the claimed invention, voltage regulators <NUM> and <NUM> are shown as being directly underneath the ASIC dies <NUM> and <NUM>; in examples not falling under the scope of the claims, the voltage regulators may be offset from the ASIC dies.

Heat may be further reduced through the use of heat sinks and heat spreaders. For instance, and as shown in <FIG> and <FIG>, heat spreader <NUM> may be positioned around ASIC dies <NUM> to pull the heat generated by the ASIC die <NUM> away from the ASIC die <NUM>. Similarly, heat spreader <NUM> may be positioned around ASIC dies <NUM> to pull the heat generated by the ASIC die <NUM> away from the ASIC die <NUM>.

Heat sinks may be positioned within the interior of the ASIC package to pull the heat from the interior of the package, such as heat generated by the photonic module and ASIC die, and push it towards the housing of the ASIC package. For instance, and as shown in <FIG> and <FIG>, heat sink <NUM> may be positioned above ASIC die <NUM> and heat spreader <NUM>. The heat sink <NUM> may pull heat from the ASIC die <NUM> and heat spreader <NUM>. Similarly, heat sink <NUM> may pull heat from the ASIC die <NUM> and heat spreader <NUM>.

As discussed above, a typical ASIC package may be connected to a power source via pins soldered onto a ball grid array (BGA). However, given the larger size of an ASIC package having integrated photonic modules and/or voltage regulators, an LGA socket, as LGA sockets <NUM> and <NUM> <FIG> may be used. Referring to <FIG>, LGA socket <NUM> may include pins <NUM> which align with contacts <NUM> formed on substrate <NUM>. When the ASIC package <NUM> is arranged such that the contacts <NUM> align with pins <NUM>, the ASIC package <NUM> may be secured to the LGA socket <NUM>. In some instances, the pins <NUM> may be soldered to the contacts <NUM>. However, the pins <NUM> may provide sufficient contact with the contacts <NUM> of the ASIC package to reduce the need for solder joints and thereby the risk for solder electromigration. In lieu of, or in addition to soldering, a latch or other such locking component may maintain the ASIC package <NUM> secure in the LGA socket <NUM>. In instances where the ASIC package <NUM> is not soldered to the LGA socket <NUM>, the ASIC package <NUM> may be removable from the LGA socket <NUM>.

Although the example ASIC packages <NUM>, <NUM>, <NUM>, and <NUM> shown in <FIG> include only a single ASIC die <NUM> or <NUM>, each ASIC package may include any number of ASIC dies. Moreover, each ASIC package may include any number of photonic modules, components within the photonic modules, voltage regulators, or other components. Additionally, although the packages described herein are described as ASIC packages having ASIC dies, any type of die may be used, such as an integrated circuit die.

The features described herein allow for the integration of photonic modules into an ASIC package. By doing such, I/O system bottlenecks may be reduced or removed. Further, signal loss over the connection interface between the photonics module and ASIC die may be reduced. Additionally, by integrating a voltage regulator into the ASIC package, the copper losses generated by wires, traces, and/or other such connections which carry the power through the ASIC package to the ASIC die may be reduced. Configuring the ASIC package to mount to a LGA socket may reduce the risk of broken solder joints and, solder electromigration, as well as provide the ability to remove the ASIC package as needed.

Claim 1:
An integrated circuit, IC, package (<NUM>) comprising:
a substrate (<NUM>);
an IC die mounted to a first surface of the substrate (<NUM>), wherein the IC die comprises an application specific integrated circuit, ASIC, die (<NUM>);
one or more photonic modules (220A, 220B) attached to the first surface of the substrate (<NUM>);
one or more serializer/deserializer, SerDes, interfaces (290A, 290B) connecting the IC die to the one or more photonic modules; and
characterized by:
a voltage regulator (<NUM>) mounted on a second surface of the substrate (<NUM>) directly under the IC die, wherein the second surface of the substrate (<NUM>) is opposite the first surface of the substrate (<NUM>).