Patent Description:
The average or, more generally, the interpolation of two voltages is often needed in analog signal processing. For instance, the interpolation of two voltages can be used as a reference voltage for a signal conversion, such as the reference interpolation in a Flash converter. As another example, the interpolation of two voltages can be used for biasing purposes. For example, interpolation can be used to define in a fully differential amplifier, based on two biasing voltages from its core, the optimum value to regulate its output common mode level to allow for maximum output signal swing.

<NPL> discloses a technique for online calibration and digital correction of the mismatched among the elements of a digital-to-analog converter used in a feedback loop of multi-bit sigma-delta modulators using a limited amount of additional circuitry.

<CIT> discloses a reference buffer circuit comprising a first reference voltage circuit to provide a first reference voltage at a first port to sink a first current at the first port; a second reference voltage circuit to provide a second reference voltage at a second port to sink a second current at the second port; and a current source circuit to source a source current at an output port, where the output port is connected to the second port. According to another embodiment of the present invention, the first and second ports are connected to a resistor ladder network of a flash analog-to-digital converter.

<CIT> discloses a low dropout (LDO) voltage regulator including a voltage regulation loop for providing a gate drive signal to an output device, the gate drive signal proportional to an output current. The voltage regulation loop includes a current bias input for receiving a bias current. The LDO voltage regulator further includes a current bias control circuit for providing the adaptive bias current at a first value that is proportional to current limit value lab and the width-to-length ratio of transistors of the transconductance amplifier when the output current less than or equal to a threshold and increases the bias current from a threshold to a current limit value. The output current varies substantially linearly over a range of output current values between the threshold and the current limit value.

This disclosure is directed to, among other things, techniques for interpolating two voltages without loading them and without requiring significant power or additional area. Described are specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

In some aspects, this disclosure is directed to a circuit to generate an output voltage, the circuit comprising: a voltage divider including at least a first resistive device and a second resistive device, wherein the output voltage is generated at a node along the voltage divider; a first closed-loop amplifier circuit to: drive a first terminal (Va) of the voltage divider; and receive a first reference voltage (VA), wherein the first closed-loop amplifier circuit is configured to derive first biasing currents from a first tail current that is a scaled version of the current through the voltage divider; and a second closed-loop amplifier circuit to: drive a second terminal (Vb) of the voltage divider; and receive a second reference voltage (VB), wherein the second closed-loop amplifier circuit is configured to derive second biasing currents from a second tail current that is a scaled version of the current through the voltage divider.

In some aspects, this disclosure is directed to a method of generating an output voltage using a circuit including a voltage divider having at least a first resistive device and a second resistive device, wherein the output voltage is generated at a node along the voltage divider, the method comprising: driving a first terminal (Va) of the voltage divider; receiving a first reference voltage (VA); generating a first tail current that is a scaled version of the current through the voltage divider; deriving first biasing currents from the first tail current; driving a second terminal (Vb) of the voltage divider; receiving a second reference voltage (VB); generating a second tail current that is a scaled version of the current through the voltage divider; and deriving second biasing currents from the second tail current.

In a comparable example, this disclosure is directed to a circuit to generate an output voltage, the circuit comprising: a voltage divider including at least a first resistive device and a second resistive device, wherein the output voltage is generated at a node along the voltage divider; a first closed-loop amplifier circuit including a first output transistor driving the voltage divider and having a first gate terminal, the first closed-loop amplifier circuit to: drive a first terminal (Va) of the voltage divider; and receive a first reference voltage (VA), wherein the first closed-loop amplifier circuit is configured to derive first biasing currents from a current through the voltage divider; and a second closed-loop amplifier circuit to: drive a second terminal (Vb) of the voltage divider; and receive a second reference voltage (VB), wherein the second closed-loop amplifier circuit is configured to derive second biasing currents from the current through the voltage divider, wherein the first closed-loop amplifier circuit includes a first tail current circuit to generate a first tail current in response to a voltage at the first gate terminal of the first output transistor, and wherein the first tail current is a scaled version of the current through the voltage divider.

This summary is intended to provide an overview of subject matter of the present patent application.

The average or, more generally, the interpolation of two voltages is often needed in analog signal processing. Existing approaches to interpolate between two reference voltages can either load the reference voltages or buffer the reference voltages. The approaches that prevent the loading of the reference voltages can require demanding amplifiers in terms of frequency compensation and/or power consumption, or these approaches use undemanding amplifiers but at the expense of substantial inaccuracy in the interpolated voltage.

To prevent loading of the reference voltages, amplifier circuits can buffer the reference voltages and, to keep the accuracy of the generated average voltage, negative feedback can be provided around the buffering function. However, such an approach can require significant power and frequency compensation to perform adequately.

The present inventors have recognized a need for a solution for interpolating two voltages without loading them and without requiring significant power or additional area. This disclosure describes, among other things, specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

<FIG> is an example of a voltage divider to generate an interpolation of two voltages. The simplest approach to generate an average voltage is to use a resistive voltage divider <NUM> (also referred to in this disclosure as a "voltage divider") with reference voltages VA and VB (VA ≥ VB) driving the voltage divider <NUM>, and a voltage VC tapped at an intermediate node, as shown in <FIG>.

The intermediate node divides the total resistance RT of the voltage divider into two segments of equivalent resistance RA and RB (RT = RA + RB), as shown in <FIG>. Applying Kirchhoff's circuit laws and assuming that the voltage VC is interfaced to a high-impedance node, the resulting voltage VC is as shown in Eq. <NUM>: <MAT>.

The voltage VC can adopt any value between the voltages VA and VB by adjusting the relative size of RA and RB. Applying Eq. <NUM> to the specific case for which RA and RB are nominally equal (RA ≈ RB = R), the voltage VC = (VA + VB)/<NUM> becomes the average of voltages VA and VB.

The current IAB flowing through RA and RB would be the same IAB (again, assuming that VC is interfaced to a high-impedance node) and set by the total resistance RT of the voltage divider by means of the Ohm's law: <MAT>.

The current established by Eq. <NUM> represents the loading experienced by the reference voltages VA and VB due to the presence of the resistive voltage divider (see <FIG>). In general, such loading |IAB| > <NUM> is undesirable because it can impact the performance of the circuits providing the reference voltages VA and/or VB, As a result, the accuracy of the generated average at the intermediate node can be diminished.

A solution to reduce |IAB| and, therefore, the loading effect of the resistive voltage divider can be to increase the total resistance RT of the resistive voltage divider, such as keeping the ratio RA/RB to offer the same voltage VC. However, if the accuracy of the generated average voltage is to be competitive, this approach implies the use of potentially huge resistors in value and, for practical technologies, also in area. As a result, the required thermal noise, layout area and/or layout parasitics can become prohibitive.

<FIG> is an example of a voltage divider circuit buffered by closed-loop amplifiers to generate an interpolation of two voltages. The circuit <NUM> of <FIG> includes a resistive voltage divider, such as the resistive voltage divider <NUM> of <FIG>, and two amplifier (buffer) circuits A1, A2 to buffer the reference voltages VA and VB before applying them to the voltage divider, thus preventing the loading of the reference voltages VA and VB by having the amplifier circuits supply the current IAB. In this approach, a dedicated buffer can be applied to each reference voltage. The circuit implementing each buffer can be different and optimized to the expected range of each reference voltage.

In some examples, this can be accomplished by using open-loop amplifiers, such as using a source-follower topology. However, the imperfections of the open-loop amplifiers (in particular, due to the possible level shifting of their outputs) can cause the reference voltages effectively applied (Va and Vb) to the voltage divider to be inaccurate. This limitation can be overcome by replacing the open-loop amplifiers with closed-loop amplifiers (A1 and A2) with sufficiently high gain, as shown in <FIG>.

In general, the use of closed-loop amplifiers in this context, such as by using operational amplifiers in unity gain configuration by means of negative feedback, implies a substantial cost in terms of area, power and/or complexity of frequency compensation. The present inventors have recognized a need for a voltage interpolator that does not load the reference voltages and that offers an accuracy comparable to the one achievable using traditional closed-loop amplifiers, but without incurring their overhead.

This disclosure describes various topologies for buffering closed-loop amplifiers that provide a competitive accuracy without relying on a significant open-loop gain and that can offer a solution for an accurate voltage interpolator without costly frequency compensation schemes (due its relatively low open-loop gain) and, thus, without significant cost in terms of area and power. Such a closed-loop amplifier can be built from a topology that does not rely on internal high impedance nodes. As a result, independent current sources are not used for the biasing of the amplifier and, hence, the current level of its branches can be defined by a feedback loop from an active current. In such a case, the load current can be conveniently used to define the biasing of the internal branches of the amplifier.

For the voltage interpolator of <FIG>, the load current IAB is defined according to Eq. <NUM> by the total resistance of the resistor string and one amplifier (A1) will source the load current IAB while the other amplifier (A2) will sink it. Therefore, since the load current IAB is well controlled by the design parameters, the amplifiers of the buffered voltage interpolator are good candidates to be biased from the load current IAB and, since they are linked by the same load, they may advantageously share some structures. These considerations lead to the circuit shown in <FIG>.

<FIG> is an example of a circuit to generate an interpolated voltage using various techniques of this disclosure. The circuit <NUM> of <FIG> can generate an output voltage VC, e.g., an interpolated output voltage. The circuit <NUM> can include a voltage divider <NUM> including at least a first resistive device RA and a second resistive device RB, where the output voltage VC is generated at a node <NUM> along the voltage divider <NUM>.

The circuit <NUM> can include a first closed-loop amplifier circuit, shown generally at 306A, and a second closed-loop amplifier circuit 306B. The first closed-loop amplifier circuit 306A can be formed by transistors mip1, min1, mlp1, min1, mo1, mt1, mtb0, and mtb and can drive a first terminal <NUM> of the voltage divider <NUM>. The first closed-loop amplifier circuit 306A can receive a first reference voltage VA by the transistor mip1 without loading the first reference voltage VA at the frequencies of interest. The output voltage Va can be fed back to the transistor min1. The first closed-loop amplifier circuit 306A can be configured to derive first biasing currents from a current IAB through the voltage divider <NUM>, as described in more detail below.

The second closed-loop amplifier circuit 306B, can be formed by transistors mip2, min2, mlp2, min2, mo2, and mt2 and can drive a second terminal <NUM> of the voltage divider <NUM>. The second closed-loop amplifier circuit 306B can receive a second reference voltage VB by the transistor mip2 without loading the second reference voltage VB at the frequencies of interest. The output voltage Vb can be fed back to the transistor min2. It is assumed VA ≥ VB, without loss of generality. The second closed-loop amplifier circuit 306B can be configured to derive second biasing currents from the current IAB through the voltage divider <NUM>, as described in more detail below. In <FIG>, the output voltage VC, e.g., an interpolated output voltage, is between the output voltage Va of the first closed-loop amplifier 306A and the output voltage Vb second closed-loop amplifier Vb.

In some examples, at least one of the first closed-loop amplifier circuit 306A and the second closed-loop amplifier circuit 306B can include a differential amplifier circuit. For example, the input stage of the first closed-loop amplifier circuit 306A can be formed by a differential input transistor pair mip1-min1, a differential load transistor pair mlp1-mln1, and a tail current source transistor mt1. The first closed-loop amplifier circuit 306A can be a simple differential amplifier with passive load that drives the output stage transistor mo1 of the first closed-loop amplifier circuit 306A. A negative feedback loop can be formed by transistors min1, mip1, and mo1 and can force, assuming it is stable, the reference voltage VA value into the output of the first closed-loop amplifier circuit 306A (which is one of the extremes Va of the voltage divider <NUM>), while the output transistor mo1 delivers the corresponding load current IAB.

The load current IAB is set by the total resistance in the voltage divider <NUM>. The techniques of <FIG>, for example, can capture any variation in the load current IAB by a variation in the tail current ITN. The effect is to balance the voltage at the load of the input stage of the first closed-loop amplifier circuit 306A, e.g., at the drains of the input transistor pair mip1-min1, which can result in an even distribution of tail current ITN and improved accuracy.

There are two negative feedback loops in the top portion of <FIG>: a first negative feedback loop through the transistors mo1 and min1 and a second through the tail current circuit. Two similar negative feedback loops are present in the bottom portion of <FIG>. The feedback loop that monitors the load current IAB forces the even distribution of the tail current in the input stage of the first closed-loop amplifier circuit 306A. If imbalances exist at the drains of the input transistor pair mip1-min1, then the load current IAB changes and the tail current ITN changes.

As mentioned above, the first closed-loop amplifier circuit 306A can be configured to derive first biasing currents from a current through the voltage divider <NUM>. For example, first biasing currents for the transistors mip1 and min1 in <FIG> can be generated from a first tail current ITN. The first closed-loop amplifier circuit 306A can include a first tail current circuit, e.g., transistors mtb, mtb0, and mt1, to provide the first tail current ITN. The transistor mtb and mtb0 can form an extra branch to generate the first tail current ITN from the gate voltage of the first output transistor mo1. The first tail current ITN provided by the transistor mt1 for the operation of the differential input pair mip1-min1 in the input stage of the first closed-loop amplifier circuit 306A is a scaled version of the load current IAB through the voltage divider <NUM>, after being conveyed by transistors mtb and mtb0 through current mirroring.

The first closed-loop amplifier circuit 306A can include a first output transistor mo1 driving the voltage divider <NUM> and having a first gate terminal <NUM>. The first tail current circuit can generate the first tail current ITN in response to a voltage at the first gate terminal <NUM> of the first output transistor mo1. This additional negative feedback loop can balance the input stage loads by making their bias currents track the load current IAB, thus helping mitigate the systematic errors that would prevent the output voltage Va from approaching the first reference voltage VA without the need for significant open-loop gain in the first closed-loop amplifier circuit 306A.

Similarly, the second closed-loop amplifier circuit 306B can include a differential amplifier circuit in some example configurations. For example, the input stage of the second closed-loop amplifier circuit 306B can be formed by the differential input transistor pair mip2-min2, its differential load transistor pair mlp2-mln2, and its tail current source transistor mt2. The second closed-loop amplifier circuit 306B can be a simple differential amplifier with passive load that drives the output stage of the second closed-loop amplifier circuit 306B formed by the transistor mo2. The negative feedback loop formed by transistors min2, mip2 and mo2 forces, assuming it is stable, the second reference voltage VB value into the output of the second closed-loop amplifier circuit 306B (which is one of the extremes Vb of the voltage divider <NUM>), while the output transistor mo2 delivers the corresponding load current IAB. The second closed-loop amplifier circuit 306B can include a second output transistor mo2 driving the voltage divider <NUM> and having a second gate terminal <NUM>.

The second closed-loop amplifier circuit 306B can be configured to derive second biasing currents from the current through the voltage divider <NUM>. For example, second biasing currents for the transistors mip2 and min2 in <FIG> can be generated from a second tail current ITP. The second closed-loop amplifier circuit 306B can include a second tail current circuit, e.g., transistor mt2, to provide the second tail current ITP. The second tail current ITP provided by the transistor mt2 for the operation of the differential input pair mip2-min2 in the input stage of the second closed-loop amplifier circuit 306B is a scaled version of the load current IAB through the voltage divider <NUM>. The second tail current circuit can generate the second tail current ITP in response to a voltage at the first gate terminal <NUM> of the first output transistor mo1.

Complementary output transistors mo1 and mo2 can drive the load (in this case, the voltage divider <NUM>) in such a way that the load current IAB flowing through them approaches the current given by Eq. <NUM>. Ignoring the possible residual errors, the action of the first closed-loop amplifier circuit 306A and the second closed-loop amplifier circuit 306B can produce Va ≈ VA and Vb ≈ VB, respectively. Therefore, the output voltage VC, e.g., an interpolated output voltage, can follow Eq. <NUM> as targeted.

In the approach represented by <FIG>, frequency compensation is secondary and, in general, optional due to its topological simplicity and relatively low open-loop gain derived from the lack of high-impedance nodes. In other approaches, however, frequency compensation would be a critical consideration and a significant cost in terms of circuitry if traditional amplifiers are used in schemes like the one in <FIG>.

In some examples, the circuits of this disclosure can include a resistive voltage divider based on resistors. However, other resistive devices, such as diodes, can be used instead of resistors if they comply with a desired matching relation.

The resistive voltage divider can accept some modifications to expand its functionality. For example, dividing it into several elements in series to make more interpolation tap voltages available, or adding resistor strings in parallel to accomplish several effects. Also, currents can be strategically injected at given nodes of the voltage divider to produce shifts in the output voltage. The solution resulting from such modifications does not depart from the spirit of the disclosed techniques.

Having additional interpolating tap voltages available can motivate the introduction of the means to select a given one as the output of the voltage interpolator, such as part of a calibration scheme or a technique for digital enhancement. The possible gain applied to the voltage references by the amplifiers working as buffers may be also subject to calibration. Again, the principle of operation of the disclosed idea would be preserved in such a case.

As a design note, the self-biasing nature of the amplifiers in <FIG> can imply the desirability for start-up circuits to guarantee a valid initial solution for the loops, a usual consideration in the state-of-the-art.

In conclusion, the circuit shown in <FIG>, for example, can buffer the reference voltages, offer competitive accuracy, and does not require demanding compensation techniques and/or power consumption as is the case using other techniques.

<FIG> depicts DC error from the ideal average (~1V) of the circuit of <FIG> simulated across process and temperature variability. The x-axis represents temperature in degrees Celsius and the y-axis represents the output error voltage in microvolts. Each of the curves <NUM>-<NUM> represents a different process corner in the semiconductor manufacturing of the circuit of <FIG>. The curve <NUM> represents the nominal output voltage of the circuit of <FIG> with an expected fabrication accuracy.

The obtained error is well confined around ~<NUM>µV as shown by <FIG>. Assuming, hence, a relative error of <NUM>µV/<NUM>V = <NUM>µ, the equivalent open-loop DC gain of the combined amplifiers of the simulated voltage interpolator can be roughly estimated as <NUM> · log<NUM>(<NUM>/520µ) ≈ <NUM>dB.

However, simulating (again, across process and temperature variability) the AC behavior of the same voltage interpolator, the obtained differential mode open-loop DC gain G is below ~<NUM>dB, showing how an accuracy equivalent to the one of a traditional amplifier (with a gain of ~<NUM>dB, according to the estimate from <FIG>) can be obtained with less open-loop gain by the use of the circuit shown in <FIG> and its intrinsic capability to cancel systematic errors to boost the accuracy. This relatively low open-loop gain G allows an acceptable stability without applying explicit compensations techniques. For example, simulations have shown a differential mode open-loop phase margin PM > <NUM>°.

<FIG> is another example of a circuit to generate an interpolated voltage using various techniques of this disclosure. The circuit <NUM> of <FIG> can generate an output voltage e.g., an interpolated output voltage. The circuit <NUM> is a complementary version of the circuit <NUM> of <FIG>. The circuit <NUM> can include a voltage divider <NUM> including at least a first resistive device RA and a second resistive device RB, where the output voltage VC is generated at a node <NUM> along the voltage divider <NUM>.

The circuit <NUM> can include a first closed-loop amplifier circuit 506A and a second closed-loop amplifier circuit 506B. The first closed-loop amplifier circuit 506A can be formed by transistors mip2, min2, mlp2, mln2, mo2, mt2, mtb0, and mtb and can drive a first terminal <NUM> of the voltage divider <NUM>. The first closed-loop amplifier circuit 506A can receive a first reference voltage VB by the transistor mip2 without loading the first reference voltage VB at the frequencies of interest. The output voltage Vb can be fed back to the transistor min2. The first closed-loop amplifier circuit 506A can be configured to derive first biasing currents from a current through the voltage divider <NUM>, as described in more detail below.

The second closed-loop amplifier circuit 506B, can be formed by transistors mip1, min1, mlp1, min1, mo1, and mt1 and can drive a second terminal <NUM> of the voltage divider <NUM>. The second closed-loop amplifier circuit 506B can receive a second reference voltage VA by the transistor mip1 without loading the second reference voltage VA at the frequencies of interest. The output voltage Va can be fed back to the transistor min1. It is assumed VB ≥ VA, without loss of generality. The second closed-loop amplifier circuit 506B can be configured to derive second biasing currents from the current through the voltage divider <NUM>, as described in more detail below.

In some examples, at least one of the first closed-loop amplifier circuit 506A and the second closed-loop amplifier circuit 506B can include a differential amplifier circuit. For example, the input stage of the first closed-loop amplifier circuit 506A can be formed by a differential input transistor pair mip2-min2, a differential load transistor pair mlp2-mln2, and a tail current source transistor mt2. The first closed-loop amplifier circuit 506A can be a simple differential amplifier with passive load that drives the output stage transistor mo2 of the first closed-loop amplifier circuit 506A. A negative feedback loop can be formed by transistors min2, mip2, and mo2 and can force, assuming it is stable, the reference voltage VB value into the output of the first closed-loop amplifier circuit 506A (which is one of the extremes Vb of the voltage divider <NUM>), while the output transistor mo2 delivers the corresponding load current IAB.

As mentioned above, the first closed-loop amplifier circuit 506A can be configured to derive first biasing currents from a current through the voltage divider <NUM>. For example, first biasing currents for the transistors mip2 and min2 in <FIG> can be generated from a first tail current ITP. The first closed-loop amplifier circuit 506A can include a first tail current circuit, e.g., transistors mtb, mtb0, and mt2, to provide the first tail current ITP. The first tail current ITP provided by the transistor mt2 for the operation of the differential input pair mip2-min2 in the input stage of the first closed-loop amplifier circuit 506A is a scaled version of the load current IAB through the voltage divider <NUM>, after being conveyed by transistors mtb and mtb0, which form a current mirror.

The first closed-loop amplifier circuit 506A can include a first output transistor mo2 driving the voltage divider <NUM> and having a first gate terminal <NUM>. The first tail current circuit can generate the first tail current ITP in response to a voltage at the first gate terminal <NUM> of the first output transistor mo2. This additional negative feedback loop can balance the input stage loads by making their bias currents track the load current IAB, thus helping mitigate the systematic errors that would prevent the output voltage Vb from approaching the first reference voltage VB without the need for significant open-loop gain in the first closed-loop amplifier circuit 506A.

Similarly, the second closed-loop amplifier circuit 506B can include a differential amplifier circuit. For example, the input stage of the second closed-loop amplifier circuit 506B can be formed by the differential input transistor pair mip1-min1, its differential load transistor pair mlp1-mln1, and its tail current source transistor mt1. The second closed-loop amplifier circuit 506B can be a simple differential amplifier with passive load that drives the output stage of the second closed-loop amplifier circuit 506B formed by the transistor mo1. The negative feedback loop formed by transistors min1, mip1 and mo1 forces, assuming it is stable, the second reference voltage VA value into the output of the second closed-loop amplifier circuit 506B (which is one of the extremes Va of the voltage divider <NUM>), while the output transistor mo1 delivers the corresponding load current IAB. The second closed-loop amplifier circuit 506B can include a second output transistor mo1 driving the voltage divider <NUM> and having a second gate terminal <NUM>.

The second closed-loop amplifier circuit 506B can be configured to derive second biasing currents from the current through the voltage divider <NUM>. For example, second biasing currents for the transistors mip1 and min1 in <FIG> can be generated from a first tail current ITP. The second closed-loop amplifier circuit 506B can include a second tail current circuit, e.g., transistor mt1, to provide the second tail current ITN. The second tail current ITN provided by the transistor mt1 for the operation of the differential input pair mip1-min1 in the input stage of the second closed-loop amplifier circuit 506B is a scaled version of the load current IAB through the voltage divider <NUM>. The second tail current circuit can generate the second tail current ITN in response to a voltage at the first gate terminal <NUM> of the first output transistor mo2.

Complementary output transistors mo1 and mo2 can drive the load (in this case, the voltage divider <NUM>) in such a way that the load current IAB flowing through them approaches the current given by Eq. <NUM>. Ignoring the possible residual errors, the action of the first closed-loop amplifier circuit 506A and the second closed-loop amplifier circuit 506B can produce Vb ≈ VB and Va ≈ VA, respectively. Therefore, the output voltage VC, e.g., an interpolated output voltage, can follow Eq. <NUM> as targeted.

<FIG> is another example of a circuit to generate an interpolated voltage using various techniques of this disclosure. In the circuit <NUM> of <FIG>, the first and second closed-loop amplifier circuits 606A, 606B can be biased from the current IAB through the voltage divider <NUM> by mirroring their corresponding output transistor mo1, mo2. This is in contrast to the circuit <NUM> of <FIG> and the circuit <NUM> of <FIG> in which the biasing currents for both of the closed-loop amplifier circuits were derived using one of the two output transistors. For example, in <FIG>, the biasing currents of both the first closed-loop amplifier circuit 306A and the second closed-loop amplifier circuit 306B can be derived using the voltage on the first gate terminal <NUM> of the first output transistor mo1.

In <FIG>, the first closed-loop amplifier circuit 606A can include a first output transistor mo1 having a first gate terminal <NUM>. A first tail current circuit can include transistors mtb1, mtb01, and mt1 and can generate a first tail current ITN in response to a voltage at the first gate terminal <NUM> of the first output transistor mo1. The second closed-loop amplifier circuit 606B can include a second output transistor mo2 having a second gate terminal <NUM>. A second tail current circuit can include transistors mtb2, mtb02, and mt2 and can generate a second tail current ITP in response to a voltage at the second gate terminal <NUM> of the second output transistor mo2. The configuration in <FIG> is in contrast to the circuit in <FIG>, for example, where a second tail current can be generated in response to the first gate terminal <NUM> of the first output transistor mo1.

<FIG> is another example of a circuit to generate an interpolated voltage using various techniques of this disclosure. The circuit <NUM> is a more compact and symmetric circuit as compared to the asymmetric circuits of <FIG> and <FIG>, for example. The circuit <NUM> can include a voltage divider <NUM>, a first closed-loop amplifier 706A, and a second closed-loop amplifier 706B.

The circuit <NUM> of <FIG> included a circuit branch having transistors mtb and mtb0 that has been removed in the circuit <NUM> of <FIG>. Like in <FIG>, for example, the first closed-loop amplifier 706A of <FIG> can include a first output transistor mo1 and the second closed-loop amplifier 706B can include a second output transistor mo2. In contrast to the circuit <NUM> of <FIG>, the tail current ITP for the second closed-loop amplifier 706B can be generated by mirroring the first output transistor mo1, e.g., using the transistor mt2, and the tail current ITN for the first closed-loop amplifier 706A can be generated by mirroring the second output transistor mo2, e.g., using the transistor mt1.

<FIG> is another example of a circuit to generate an output voltage using various techniques of this disclosure. The circuit <NUM> can generate either an interpolated output voltage or an extrapolated output voltage, where an extrapolated output voltage can be generated at a node <NUM> of the voltage divider <NUM>, and wherein the extrapolated voltage extends outside a range of output voltages Va, Vb of the first closed-loop amplifier 806A and the second closed-loop amplifier 806B. The circuit <NUM> of <FIG> can extrapolate values beyond VA and VB by extending the voltage divider <NUM> beyond the amplifiers' outputs Va and Vb, and tapping voltages like Vx > VA and Vy < VB as shown, for example, in <FIG> by the addition of resistive elements Rx and Ry, respectively.

The circuit shown in <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> can be adapted to interpolate not only the average between the reference voltages VA and VB but any intermediate value (VB ≤ VC ≤ VA) by adjusting the relative resistances of resistors RA and RB. In practice, this can mean tapping the output voltage VC at a different node, e.g., node VX or VY, along the voltage divider <NUM>.

The descriptions of the voltage interpolator circuits above adopted the typical case in which the reference voltages are buffered with a unity gain. However, in general, the techniques of this disclosure can be adapted to apply a different gain factor to expand or reduce the range of available interpolation (or extrapolation values). Moreover, the amplification can be asymmetrical between both amplifiers, producing the corresponding shift in the available interpolation/extrapolation range.

The voltage interpolator techniques described in this disclosure can be used as a standalone circuit or as part of a more complex system. This disclosure has implicitly focused on the case of integrated circuits. However, the techniques are also applicable to discrete circuits or combinations of integrated circuits and discrete circuits.

Claim 1:
A circuit (<NUM>) to generate an output voltage, the circuit comprising:
a voltage divider (<NUM>) including at least a first resistive device (RA) and a second resistive device (RB), wherein the output voltage is generated at a node (<NUM>) along the voltage divider between the first and second resistive devices (RA, RB);
a first closed-loop amplifier circuit (306A) to:
drive a first terminal (Va) of the voltage divider; and
receive a first reference voltage (VA),
wherein the first closed-loop amplifier circuit is configured to derive first biasing currents of a first differential input transistor pair (mip1, min1) from a current through the voltage divider, and the first biasing currents are generated from a first tail current that is a scaled version of the current through the voltage divider; and
a second closed-loop amplifier circuit (306B) to:
drive a second terminal (Vb) of the voltage divider; and
receive a second reference voltage (VB),
wherein the second closed-loop amplifier circuit is configured to derive second biasing currents of a second differential input transistor pair (mip2, min2) from the current through the voltage divider, and the second biasing currents are generated from a second tail current that is a scaled version of the current through the voltage divider.