Patent Description:
Planar integrated circuit (IC) devices are scaled to smaller sizes by improving process technology, circuit designs, programming algorithms, and the fabrication process. However, as feature sizes of the logic/analog devices and memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, density and bandwidth for planar IC devices approach an upper limit. A three-dimensional (3D) IC architecture can address the density and performance limitation in planar IC device. <CIT> discloses a stacked semiconductor device and method of manufacturing the same. <CIT> discloses a semiconductor memory device.

Embodiments of a three-dimensional integrated circuit device and methods for forming the same are described in the present disclosure.

One aspect of the present disclosure provides a method for forming a three-dimensional semiconductor device according to claim <NUM>.

In some embodiments, the method for forming a three-dimensional semiconductor device also includes forming at least one vertical interconnect structure, extending through the third substrate of the microprocessor chip, where the at least one vertical interconnect structure provides electrical connection to the at least one third interconnect structure.

In some embodiments, the method for forming a three-dimensional semiconductor device further includes forming at least one input/output pad electrically connected with the at least one vertical interconnect structure of the microprocessor chip.

In some embodiments, the method for forming a three-dimensional semiconductor device further includes thinning the first or the second substrate after the bonding of the first interconnect layer of the first memory chip with the second interconnect layer of the second memory chip, where the thinning comprises grinding, wet or dry etching, or chemical-mechanical polishing.

In some embodiments, the method for forming a three-dimensional semiconductor device further includes thinning the second or the third substrate after the bonding of the third interconnect layer of the microprocessor chip with the first substrate of the first memory chip, where the thinning comprises grinding, wet or dry etching, or chemical-mechanical polishing.

In some embodiments, the forming of the microprocessor chip includes forming a digital signal processor, a microcontroller, or a central computing unit for a computer or a mobile device.

In some embodiments, the forming of the first memory chip includes forming a static random-access memory or a dynamic random-access memory.

In some embodiments, the forming of the second memory chip includes forming a flash memory.

Another aspect of the present disclosure provides a three-dimensional (3D) semiconductor device according to claim <NUM>.

In some embodiments, in the three-dimensional semiconductor device, the at least one first memory cell of the first memory chip is electrically connected with the at least one second memory cell of the second memory chip through the interconnect structures of the first and second memory chips.

In some embodiments, the three-dimensional semiconductor device also includes a bonding interface between the interconnect layer of the microprocessor chip and the substrate of the first memory chip, where the bonding interface includes dielectric-to-dielectric bonding and metal-to-metal bonding.

In some embodiments, the microprocessor chip includes a digital signal processor, a microcontroller, or a central computing unit for a computer or a mobile device.

In some embodiments, the first memory chip includes a static random-access memory or a dynamic random-access memory.

In some embodiments, the second memory chip includes a flash memory.

It is noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology can be understood at least in part from usage in context. For example, the term "one or more" as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as "a," "an," or "the," again, can be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of "on," "above," and "over" in the present disclosure should be interpreted in the broadest manner such that "on" not only means "directly on" something, but also includes the meaning of "on" something with an intermediate feature or a layer therebetween. Moreover, "above" or "over" not only means "above" or "over" something, but can also include the meaning it is "above" or "over" something with no intermediate feature or layer therebetween (i.e., directly on something).

Further, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or process step in addition to the orientation depicted in the figures. The apparatus can be otherwise oriented (rotated <NUM> degrees or at other orientations) and the spatially relative descriptors used herein can likewise be interpreted accordingly.

The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where a semiconductor device is formed, and therefore the semiconductor device is formed at a top side of the substrate unless stated otherwise. The bottom surface is opposite to the top surface and therefore a bottom side of the substrate is opposite to the top side of the substrate.

A layer has a top side and a bottom side where the bottom side of the layer is relatively close to the substrate and the top side is relatively away from the substrate. A layer can extend over the entirety of an underlying or overlying structure, or can have an extent less than the extent of an underlying or overlying structure. For example, a layer can be located between any set of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. For example, an interconnect layer can include one or more conductive and contact layers (in which contacts, interconnect lines, and/or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

As used herein, the term "nominal/nominally" refers to a desired, or target, value of a characteristic or parameter for a component or a process step, set during the design phase of a product or a process, together with a range of values above and/or below the desired value.

As used herein, the term "vertical" or "vertically" means nominally perpendicular to the lateral surface of a substrate.

As technology development for integrated circuits (ICs) approaching fundamental limitations in semiconductor device performance, three-dimensional (3D) ICs, which contain multiple stacked layers of active devices and circuits, offer an attractive alternative to traditional two-dimensional (2D) planar ICs. 3D ICs can provide many benefits including high density, high band-width, low-power, and small form-factor. One possible application is stacking a single or multiple memory chips on top of a logic chip, where the logic chip and the memory chip can communicate through hundreds of interconnects, e.g., inputs/outputs (IOs), allowing high-bandwidth with low power consumption. By optimizing the architecture and floor-planning, interconnection lengths between the memory chip and the logic chip can be minimized, resulting in reduced delay and improved bandwidth.

Through-Silicon-Via (TSV) has been used as a solution in building 3D ICs. It is a technology where vertical interconnects are formed through the (silicon) substrate to enable communication among the stacked chips. Although silicon substrate can be thinned down, certain thickness is required to maintain mechanical strength and provide support to the multi-stacked 3D ICs. Due to the thickness of the silicon substrate and challenges in high aspect ratio VIA etching and metal filling, TSV has large lateral dimensions and pitch, limiting the number of TSVs that can be used and thereby limiting performance improvement of the 3D ICs.

Various embodiments in accordance with the present disclosure provide fabricating methods and corresponding 3D IC devices with smaller size, higher density, higher bandwidth and improved performance (speed/power) compared with other 3D ICs. By using hybrid bonding technology, dynamic random-access memory (DRAM), NAND flash memory or other functional chips can be integrated with a central processing unit (CPU) chip through thousands or millions of metal interconnects, enabling a super chip, e.g., a computer-on-a-chip.

An example not falling under the scope of the independent claims, but useful for understanding the present invention will now be described with reference to <FIG>.

<FIG> illustrates a schematic view of an exemplary 3D IC device <NUM>. 3D IC device <NUM> can include a microprocessor chip <NUM> and a memory chip <NUM>. The microprocessor chip <NUM> can be any suitable microprocessor, for example, a digital signal processor, a microcontroller, or a central computing unit (CPU) for a computer or a mobile device. The memory chip <NUM> can be any suitable volatile or non-volatile memory, for example, a static random-access memory (SRAM), a dynamic random-access memory (DRAM), a phase change memory, a magnetic random-access memory or a flash memory. As an example, the microprocessor chip <NUM> can be a CPU chip and is also referred to as the CPU chip <NUM>, and the memory chip <NUM> can be a DRAM chip and is also referred to as the DRAM chip <NUM>. The CPU chip <NUM> and the DRAM chip <NUM> can include a plurality of CPU interconnect VIAs <NUM> and DRAM interconnect VIAs <NUM>, respectively. Through hybrid bonding, the DRAM chip <NUM> and the CPU <NUM> can be joined together to form the 3D IC device <NUM>. The DRAM chip <NUM> and the CPU chip <NUM> can be electrically connected together through the CPU/DRAM interconnect VIAs <NUM>/<NUM>.

<FIG> illustrates a cross-section of an exemplary CPU <NUM>. The CPU chip <NUM> can include a CPU substrate <NUM>, which can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), ), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, glass, III-V compound, any other suitable materials or any combinations thereof.

The CPU chip <NUM> can include one or more microprocessor device or CPU device <NUM> on the CPU substrate <NUM>. The CPU device can be formed "on" the CPU substrate <NUM>, in which the entirety or part of the CPU device <NUM> is formed in the CPU substrate <NUM> (e.g., below the top surface of the CPU substrate <NUM>) and/or directly on the CPU substrate <NUM>. The CPU device <NUM> can include any suitable semiconductor devices, for example, metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BITs), diodes, resistors, capacitors, inductors, etc. Among the semiconductor devices, p-type and/or n-type MOSFETs are widely implemented in logic circuit design, and are used as examples for the CPU device <NUM> in the present disclosure.

A CPU device <NUM> can be either a p-channel MOSFET or an n-channel MOSFET and can include, but not limited to, an active device region surrounded by shallow trench isolation (STI) (not shown in <FIG>), a well <NUM> formed in the active device region with n-type or p-type doping, a gate stack <NUM> that includes a gate dielectric, a gate conductor and/or a gate hard mask. The CPU device <NUM> can also include a source/drain extension and/or halo region (not shown in <FIG>), a gate spacer <NUM> and a source/drain <NUM> locating on each side of the gate stack. The CPU device <NUM> can further include a silicide contact area (not shown) in the top portion of the source/drain. Other known devices can be also formed on the CPU substrate <NUM>. The structure and fabrication method of the CPU device <NUM>, are known to those skilled in the art, and are incorporated herein for entirety.

The STI can be formed through patterning the substrate using lithography and etching, filling an insulating material and polishing the insulating material to form a coplanar surface on the substrate <NUM>. An insulating material for STI can include silicon oxide, silicon oxynitride, TEOS, low-temperature oxide (LTO), high temperature oxide (HTO), silicon nitride, etc. An insulating material for STI can be disposed using techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), low pressure chemical vapor deposition (LPCVD), high density plasma (HDP) chemical vapor deposition, rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), sputtering, thermal oxidation or nitridation, or combinations thereof. The forming of STI can also include a high temperature annealing step to densify the disposed insulating material for better electrical isolation. Other STI structures can be employed, as would be apparent to a person of ordinary skill in the art.

The well <NUM> of the CPU device <NUM> can include a p-type doping for n-channel MOSFET and an n-type doping for p-channel MOSFET, and is called p-well and n-well, respectively. The dopant profile and concentration of the well <NUM> affects the device characteristics of the CPU device <NUM>. For MOSFET devices with low threshold voltage (Vt), the well <NUM> can be doped with lower concentration, and can form low-voltage p-well or low-voltage n-well. For MOSFET with high Vt, the well <NUM> can be doped with higher concentration, and can form high-voltage p-well or high-voltage n-well. In some embodiments, to provide electrical isolation from p-type substrate <NUM>, a deep n-well can be formed underneath a high-voltage p-well for an n-channel MOSFET with high Vt.

The forming of an n-well can include any suitable n-type dopant, such as phosphorus, arsenic, antimony, etc., and/or any combination thereof. The forming of a p-well can include any suitable p-type dopant, for example boron. The dopant incorporation can be achieved through ion implantation followed by activation anneal, or through in-situ doping during epitaxy for the active device region.

The gate stack <NUM> of the CPU device <NUM> can be formed by a "gate first" scheme, where the gate stack <NUM> is disposed and patterned prior to source/drain formation. The gate stack <NUM> of the CPU device <NUM> can also be formed by a "replacement" scheme, where a sacrificial gate stack can be formed first and then replaced by a high-k dielectric layer and a gate conductor after source/drain formation.

The gate dielectric can be made of silicon oxide, silicon nitride, silicon oxynitride, and/or high-k dielectric films such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, or lanthanum oxide films, and/or combinations thereof. The gate dielectric can be disposed by any suitable methods such as CVD, PVD, PECVD, LPCVD, RTCVD, sputtering, MOCVD, ALD, thermal oxidation or nitridation, or combinations thereof.

The gate conductor can be made from a metal, such as tungsten, cobalt, nickel, copper, or aluminum, and/or combinations thereof. In some embodiments, the gate conductor can also include a conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), etc. The gate conductor can be formed by any suitable deposition methods, for example, sputtering, thermal evaporation, e-beam evaporation, ALD, PVD, and/or combinations thereof.

The gate conductor can also include a poly-crystalline semiconductor, such as poly-crystalline silicon, poly-crystalline germanium, poly-crystalline germanium-silicon and any other suitable material, and/or combinations thereof. In some embodiments, the poly-crystalline material can be incorporated with any suitable types of dopant, such as boron, phosphorous, or arsenic, etc. In some embodiments, the gate conductor can also be an amorphous semiconductor.

The gate conductor can be made from a metal silicide, including WSix, CoSix, NiSix, or AlSix, etc. The forming of the metal silicide material can include forming a metal layer and a poly-crystalline semiconductor using similar techniques described above. The forming of metal silicide can further include applying a thermal annealing process on the deposited metal layer and the poly-crystalline semiconductor layer, followed by removal of unreacted metal.

The gate spacer <NUM> can be formed through disposing an insulating material and then performing anisotropic etching. The insulating material for the gate spacer <NUM> can be any insulator, including silicon oxide, silicon nitride, silicon oxyntiride, TEOS, LTO, HTO, etc. The gate spacer <NUM> can be disposed using techniques such as CVD, PVD, PECVD, LPCVD, RTCVD, MOCVD, ALD, sputtering, or combinations thereof. The anisotropic etching of the gate spacer <NUM> includes dry etching, for example reactive ion etching (RIE).

A length L of the gate stack <NUM> between the source/drain <NUM> is an important feature of the MOSFET. The gate length L determines the magnitude of drive current of a MOSFET and is therefore scaled down aggressively for logic circuits. The gate length L can be less than about <NUM>. The gate length can be in a range between about <NUM> to about <NUM>. Patterning of the gate stack with such a small dimension is very challenging, and can use techniques including optical proximity correction, double exposure and/or double etching, self-aligned double patterning, etc..

The source / drain <NUM> of the CPU device <NUM> is incorporated with high concentration dopants. For n-type MOSFETs, the dopant for source/drain <NUM> can include any suitable n-type dopant, such as phosphorus, arsenic, antimony, etc., and/or any combination thereof. For p-type MOSFETs, the dopant for source/drain <NUM> can include any suitable p-type dopant, for example boron. The dopant incorporation can be achieved through ion implantation followed by dopant activation anneal. The source/drain <NUM> can be made of the same material as the substrate <NUM>, for example, silicon. The source/drain <NUM> of a CPU device <NUM> can be made of a different material from the substrate <NUM> to achieve high performance. For example, on a silicon substrate, the source/drain <NUM> for a p-type MOSFETs can include SiGe and the source/drain <NUM> for an n-type MOSFETs can include carbon incorporation. The forming of the source/drain <NUM> with a different material can include etching back the substrate material in the source/drain area and disposing new source/drain material using techniques such as epitaxy. Doping for source/drain <NUM> can also be achieved through in-situ doping during epitaxy.

The CPU device <NUM> can also have an optional source/drain extension and/or halo region (not shown in <FIG>) along each side of the gate stack <NUM>. The source/drain extension and/or halo region locates inside the active device region below the gate stack, and is implemented mainly for better short channel control for the CPU device <NUM> with a channel length less than about <NUM>. The forming of the source/drain extension and/or halo region can be similar to the forming of the source/drain <NUM>, but may use different implantation conditions (e.g., dose, angle, energy, species, etc.) to obtain optimized doping profile, depth or concentration.

The CPU device <NUM> can be formed on the CPU substrate <NUM> with a planar active device region (as shown in <FIG>), where the direction of MOSFET's channel and current flow is parallel to the top surface of the CPU substrate <NUM>. The CPU device can also be formed on the CPU substrates <NUM> with a 3D active device region, for example a so-called "FINFET" in a shape like a "FIN" (not shown), where the gate stack of the MOSFET is wrapped around the FIN, and the MOSFET's channel lies along three sides of the FIN (top and two sidewalls under the gate). The structure and methods for FINFET device are known to those skilled in the art and are not discussed further in present disclosure.

The CPU device <NUM>, however, is not limited to MOSFET. The structures of the other devices, for example diodes, resistors, capacitors, inductors, BITs, etc., can be formed simultaneously during MOSFETs fabrication through different mask design and layout. To form devices other than MOSFETs, process steps can be added or modified in a MOSFET's process flow, for example, processes to obtain different dopant profiles, film thicknesses or material stacks, etc. The CPU device <NUM> other than MOSFET can also be fabricated with additional design and/or lithography mask levels to achieve specific circuit requirements.

A plurality of the CPU devices <NUM> can be used to form any digital, analog, and/or mixed-signal circuits for the operation of the CPU chip <NUM>. The CPU chip <NUM> can perform, for example, the basic arithmetic, logic, controlling, and input/output (I/O) operations specified by instructions.

The CPU chip <NUM> can include a CPU interconnect layer <NUM> above the CPU devices <NUM> to provide electrical connections between different CPU devices <NUM> and external devices (e.g., power supply, another chip, I/O device, etc.). The CPU interconnect layer <NUM> can include one or more interconnect structures, for example, one or more vertical contact structures <NUM> and one or more lateral conductive lines <NUM>. The contact structure <NUM> and conductive line <NUM> can broadly include any suitable types of interconnects, such as middle-of-line (MOL) interconnects and back-end-of-line (BEOL) interconnects. The contact structure <NUM> and conductive line <NUM> in the CPU chip <NUM> can include any suitable conductive materials such as tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicides (WSix, CoSix, NiSix, AlSix, etc.), or any combination thereof. The conductive materials can be deposited by one or more thin film deposition processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof.

CPU interconnect layer <NUM> can further include an insulating layer <NUM>. The insulating layer <NUM> in the CPU interconnect layer <NUM> can include insulating materials, for example, silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide (such as F-, C-, N- or H- doped oxides), tetraethoxysilane (TEOS), polyimide, spin-on-glass (SOG), low-k dielectric material such as porous SiCOH, silsesquioxan (SSQ), or any combination thereof. The insulating materials can be deposited by one or more thin film deposition processes such as CVD, PVD, PECVD, ALD, high-density-plasma CVD (HDP-CVD), sputtering, spin-coating, or any combination thereof.

In <FIG>, two conductive levels <NUM> (also referred to as "metal levels") are illustrated as an example, where each metal level <NUM> include the contact structures <NUM> and the conductive lines <NUM> with the conductive lines <NUM> of the same metal level located at the same distance from the CPU substrate <NUM>. The number of metal levels <NUM> for the CPU chip <NUM> is not limited and can be any number optimized for the CPU performance.

The CPU interconnect layer <NUM> can be formed by stacking metal levels <NUM> from bottom to the top of the CPU chip <NUM>. In the example of the CPU chip <NUM> in <FIG>, the bottom metal level <NUM>-<NUM> can be formed first and then the upper metal level <NUM>-<NUM> can be formed on top of the bottom metal level <NUM>-<NUM>. Fabrication processes of each metal level <NUM> can include, but not limited to, disposing a portion of the insulating layer <NUM> with a thickness required for the metal level, patterning the portion of the insulating layer <NUM> using photo lithography and dry/wet etching to form contact holes for the contact structures <NUM> and the conductive lines <NUM>, disposing conductive materials to fill the contact holes for the contact structures <NUM> and the conductive lines <NUM>, and removing excess conductive materials outside the contact holes by using planarization process such as chemical mechanical polishing (CMP) or reactive ion etching (RIE).

The topmost conductive lines <NUM> are coplanar with the top surface <NUM> of the CPU chip <NUM>, where the topmost conductive lines <NUM> can be directly connected to the conductive lines on another chip or an external device.

The topmost conductive lines <NUM> are embedded inside the insulating layer <NUM>, where the insulating material on top of the conductive lines <NUM> provide scratch protection during shipping or handling. Electrical connections to the topmost conductive lines <NUM> can be established later by forming metal VIAs, or simply by etching back the insulating layer <NUM> using dry/wet etching.

<FIG> illustrates a cross-section of an exemplary CPU chip <NUM> at certain process stage. The CPU chip <NUM> includes a bonding layer <NUM> disposed on top of the CPU chip <NUM>. The CPU chip <NUM> also includes a plurality of CPU interconnect VIAs <NUM>, where the CPU interconnect VIAs <NUM> extend through the bonding layer <NUM> into the insulating layer <NUM> and form electrical contacts with the conductive lines <NUM> of the CPU chip <NUM>.

The bonding layer <NUM> can include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride or any combination thereof. The bonding layer <NUM> can also include adhesion materials, for example, epoxy resin, polyimide, dry film, photosensitive polymer, etc. The bonding layer <NUM> can be formed by one or more thin film deposition processes such as CVD, PVD, PECVD, ALD, high-density-plasma CVD (HDP-CVD), sputtering, spin-coating, or any combination thereof.

The CPU interconnect VIA <NUM> can include metal such as copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof. The metal of CPU interconnect VIA <NUM> can be disposed by one or more thin film deposition processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof.

The fabrication process of the CPU interconnect VIA <NUM> can further include, but not limited to, photolithography, wet/dry etching, planarization (e.g., CMP, or RIE etch-back), etc..

<FIG> illustrates a cross-section of an exemplary DRAM <NUM>. The DRAM chip <NUM> includes a DRAM substrate <NUM>, DRAM peripheral devices (not shown), DRAM memory cells and a DRAM interconnect layer <NUM>. The DRAM substrate <NUM> can be similar to the CPU substrate <NUM>. The DRAM interconnect layer <NUM> can be similar to the CPU interconnect layer <NUM> and can be formed using similar materials and similar processes. For example, interconnect structures (such as contact structure <NUM> and conductive line <NUM>) and insulating layer <NUM> of the DRAM interconnect layer <NUM> are similar to the interconnect structures (such as contact structure <NUM> and conductive line <NUM>) and insulating layer <NUM> of the CPU interconnect layer <NUM>, respectively.

The DRAM peripheral device can include any active and/or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc. A plurality of DRAM peripheral devices can form suitable digital, analog, and/or mixed-signal peripheral circuits to support the operation of the DRAM chip <NUM>. For example, the peripheral circuit can include a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, timing and controls, and the like circuitry. The DRAM peripheral device can be similar to the CPU device <NUM> and can be formed using similar processes.

A plurality of DRAM memory cells can be arranged as a DRAM memory array, the core region of the DRAM chip that provides storage functions. Each DRAM memory cell include a DRAM device <NUM> and a DRAM capacitor <NUM>. The DRAM device <NUM> can be similar to the CPU device <NUM> and can also include any suitable semiconductor devices, for example, metal oxide semiconductor field effect transistors (MOSFETs). N-type MOSFETs are often implemented in DRAM memory cells as access transistors. In <FIG> MOSFETs are illustrated as an example of the DRAM devices <NUM>.

Similar to the CPU device <NUM>, the DRAM device <NUM> can also include, but not limited to, an active device region surrounded by shallow trench isolation (STI), a well formed in the active device region with n-type or p-type doping, a gate stack <NUM> that includes a gate dielectric, a gate conductor and/or a gate hard mask. The DRAM device <NUM> can also include a source/drain extension and/or halo region, a gate spacer <NUM> and a source/drain <NUM> locating on each side of the gate stack. The CPU device <NUM> can further include a silicide contact area in the top portion of the source/drain. For simplicity, the STI, well, extension/halo, and silicide contact area of the DRAM device <NUM> are not shown in <FIG>. Other known devices can be also formed on the DRAM substrate <NUM>. The structure and fabrication method of the DRAM device <NUM> can be similar to the CPU device <NUM> with modifications (e.g., dimension, thickness, dopant/concentration, etc.) for different device performance.

The DRAM device <NUM> can be formed on the DRAM substrate <NUM> with a planar active device region (as shown in <FIG>), where the direction of MOSFET's channel and current flow is parallel to the top surface of the DRAM substrate <NUM>. The DRAM device <NUM> can also be formed on the DRAM substrates <NUM> with a 3D active device region, for example a vertical MOSFET or gate-all-around MOSFET, where the gate stack of the MOSFET is wrapped around a silicon pillar and the current flow direction is perpendicular to the DRAM substrate <NUM>. The structure and methods for the vertical MOSFET and gate-all-around MOSFET device are known to those skilled in the art and are not discussed further in present disclosure.

The DRAM capacitor <NUM> of the DRAM chip <NUM> can include a capacitor dielectric layer <NUM> sandwiched between two capacitor electrodes <NUM>. The capacitor dielectric layer <NUM> can include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The capacitor dielectric layer <NUM> can also include high-k dielectric materials, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof. The capacitor dielectric layer <NUM> can be disposed by any suitable methods such as thermal oxidation, CVD, PVD, PECVD, LPCVD, sputtering, MOCVD, ALD, or any combination thereof. The capacitor electrode <NUM> can include any suitable conductive material, for example, a metal or metallic compound such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and/or any combination thereof. The metal or metallic compound can be disposed using a suitable deposition method such as CVD, PVD, PECVD, sputtering, thermal evaporation, e-beam evaporation, MOCVD, and/or ALD.

The topmost conductive lines <NUM> are coplanar with the top surface <NUM> of the DRAM chip <NUM>, where the topmost conductive lines <NUM> can be directly connected to the conductive lines on another chip or an external device.

The topmost conductive lines <NUM> are embedded inside the insulating layer <NUM>, where the insulating material on top of the conductive lines <NUM> provides scratch protection during shipping or handling. Electrical connections to the topmost conductive lines <NUM> can be established later by forming metal VIAs, or simply by etching back the insulating layer <NUM> using dry/wet etching.

<FIG> illustrates a cross-section of an exemplary DRAM chip <NUM> at certain process stage. The DRAM chip <NUM> includes the DRAM chip <NUM>, a bonding layer <NUM> disposed on the DRAM chip <NUM>, and a plurality of DRAM interconnect VIAs <NUM> formed for the DRAM chip <NUM>. The structure and fabrication method for the DRAM bonding layer <NUM> and interconnect VIAs <NUM> are similar to the CPU bonding layer <NUM> and interconnect VIAs <NUM>, respectively.

DRAM chip <NUM> stores each bit of data in the DRAM capacitor <NUM> that can be charged or discharged. A DRAM memory cell usually include one DRAM capacitor <NUM> and one DRAM device <NUM> (e.g. access transistor using n-type MOSFET). DRAM's memory cells are usually arranged in a rectangular array, where the word lines are connected to the gate electrodes of the DRAM devices <NUM> and the bit lines are connected to the drains of the DRAM devices <NUM>.

As a volatile memory, DRAM periodically rewrite the bit of data to maintain the storage bit in the DRAM capacitor <NUM>. However, compared to four or six transistors in a static random access memory (SRAM) cell, the DRAM memory cell is much simpler and smaller. This allows DRAM to reach very high densities, making DRAM much cheaper per bit. Therefore, DRAM is widely used in digital electronics where low-cost and high-capacity memory is required. One of the largest applications for DRAM is the main memory in microprocessors (e.g., CPU and GPU).

Traditionally a DRAM chip is wire-bonded to a CPU chip during packaging. Stacking DRAM chip on top of a CPU chip (or vice versa) becomes increasingly difficult as the number of I/O in the chips increase. Through-silicon-via (TSV) has the potential to offer larger interconnect density. However TSV is relative large compared to the conventional BEOL Cu VIAs. In addition, as the contact pitch getting smaller and smaller, underfill becomes extremely challenging post bonding.

The DRAM chip <NUM> can be bonded to the CPU chip <NUM> using hybrid bonding technique.

<FIG> illustrates a cross-section of an exemplary 3D IC device <NUM>. The 3D IC device <NUM> illustrates an example of 3D IC device <NUM> in <FIG>, where the DRAM chip <NUM> can be bonded with the CPU chip <NUM> and electrically connected with the CPU chip <NUM> through the CPU/DRAM interconnect VIAs <NUM>/<NUM>.

The 3D IC device <NUM> can include a bonding interface <NUM> formed between the insulating layer <NUM> of the CPU interconnect layer <NUM> and the insulating layer <NUM> of the DRAM interconnect layer <NUM>. Interconnect VIAs <NUM>/<NUM> can be joined at bonding interface <NUM> to electrically connect any conductive line <NUM> or contact structure <NUM> of the CPU interconnect layer <NUM> and any conductive line <NUM> or contact structure <NUM> of the DRAM interconnect layer <NUM>. As such, the CPU chip <NUM> and the DRAM chip <NUM> can be electrically connected.

The 3D IC device <NUM> can include a bonding interface <NUM> formed between the bonding layer <NUM> of the CPU chip <NUM> and the bonding layer <NUM> of the DRAM chip <NUM>. In this example, the interconnect VIAs <NUM>/<NUM> extend through the bonding layer <NUM>/<NUM> respectively and also form electrical connections between any conductive line <NUM> or contact structure <NUM> of the CPU interconnect layer <NUM> and the conductive line <NUM> or contact structure <NUM> of the DRAM interconnect layer <NUM>. As such, the CPU chip <NUM> and the DRAM chip <NUM> can also be electrically connected.

After bonding, any device or circuit on the CPU chip <NUM> can be electrically connected to any device or circuit on the DRAM chip <NUM>. <FIG> illustrates that the DRAM chip <NUM> is bonded on top of the CPU chip <NUM>. The CPU chip <NUM> can be bonded on top of the DRAM chip <NUM>.

<FIG> illustrates an exemplary fabrication process <NUM> for forming the 3D IC devices shown in <FIG>. It should be understood that the operations shown in fabrication process <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Some process steps of exemplary fabrication process <NUM> can be omitted or include other process steps that are not described here for simplicity. Process steps of method <NUM> can be performed in a different order and/or vary.

As shown in <FIG>, fabrication process <NUM> starts at process step S610, in which a microprocessor chip is formed on a first substrate. In some embodiments, the forming of the microprocessor chip includes forming a digital signal processor, a microcontroller, or a central computing unit for a computer or a mobile device. In an example, the microprocessor chip can be the CPU chip <NUM> shown in <FIG>, including a CPU device <NUM> and a CPU interconnect layer <NUM>. The fabrication process for the CPU chip can be similar to fabrication process for the CPU chip <NUM>.

A plurality of CPU interconnect VIAs can be formed for the CPU chip <NUM>. The CPU interconnect VIAs can be the CPU interconnect VIAs <NUM> in <FIG>, and can be made of similar material and formed by using similar processes. The CPU interconnect VIAs are formed to make electrical connections for the CPU chip <NUM>. The fabrication processes for the interconnect VIA include, lithography, trench formation using wet/dry etching, disposing and filling conductive material inside the trench, and removing excess materials outside the trench by using a planarization process such as CMP.

A bonding layer can be disposed on the CPU chip <NUM>. The bonding layer can be the bonding layer <NUM> in <FIG>, and can be fabricated using similar techniques.

At process step S620, a memory chip is formed on a second substrate. The forming of the memory chip includes forming a static random-access memory, a dynamic random-access memory or a flash memory. In an example, the memory chip can be the DRAM chip <NUM> shown in <FIG>, including DRAM peripheral devices, DRAM memory cells and a DRAM interconnect layer <NUM>.

A plurality of DRAM interconnect VIAs can be formed for the DRAM chip <NUM>. The DRAM interconnect VIAs can be the DRAM interconnect VIAs <NUM> in <FIG>, and can be formed using similar techniques.

A bonding layer can be disposed on the DRAM chip <NUM>. The bonding layer can be the bonding layer <NUM> in <FIG>, and can be fabricated using similar techniques.

At process step S630, the DRAM chip can be bonded to the CPU chip to form an 3D IC device, wherein the 3D IC device can be the 3D IC device <NUM> in <FIG>.

The CPU chip <NUM> and the DRAM chip <NUM> can be bonded together at die level (e.g., die-to-die, or chip-to-chip) or at wafer level (e.g., wafer-to-wafer or chip-to-wafer), depending on the product design and manufacturing strategy. Bonding at wafer level can provide high throughput, where all the dies/chips on the first substrate with the CPU chips <NUM> can be joined simultaneously with the second substrate with the DRAM chips <NUM>. Individual 3D IC device <NUM> can be diced after wafer bonding. On the other hand, bonding at die level can be performed after dicing and die test, where functional dies of the CPU chip <NUM> and DRAM chip <NUM> can be selected first and then bonded to form 3D IC device <NUM>, enabling higher yield of 3D IC device <NUM>.

The DRAM chip <NUM> can be flipped upside down and positioned above the CPU chip (or vice versa). The DRAM interconnect layer <NUM> of the DRAM chip <NUM> can be aligned with the CPU interconnect layer <NUM> of the CPU chip <NUM>.

Aligning the DRAM interconnect layer <NUM> with CPU interconnect layer <NUM> is performed by aligning DRAM interconnect VIAs <NUM> of the DRAM chip <NUM> with corresponding CPU interconnect VIAs <NUM> of the CPU chip <NUM>. As a result, corresponding interconnect VIAs can be connected at the bonding interface <NUM> and the DRAM chip <NUM> can be electrically connected to the CPU chip <NUM>.

The CPU chip <NUM> and the DRAM chip <NUM> can be joined by hybrid bonding. Hybrid bonding, especially metal/dielectric hybrid bonding, can be a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives), which obtains metal-metal bonding and dielectric-dielectric bonding simultaneously. As illustrated in <FIG> and <FIG>, the DRAM chip <NUM> can be joined with the CPU chip <NUM>, thereby forming a bonding interface <NUM>.

A bonding layer can be formed on the CPU chip <NUM> and/or DRAM chip <NUM> prior to hybrid bonding. The bonding layer can be the bonding layer <NUM> on the CPU chip <NUM> shown in <FIG>, and the bonding layer <NUM> on the DRAM chip <NUM> in <FIG>. The bonding layer <NUM>/<NUM> can be a dielectric material, for example, silicon nitride, silicon oxynitride, or silicon oxide. At the bonding interface <NUM>, the bonding can take place between silicon nitride to silicon nitride, silicon oxide to silicon oxide , or silicon nitride to silicon oxide, in addition to metal to metal bonding. The bonding layer can also include an adhesive material to enhance bonding strength, for example, epoxy resin, polyimide, dry film, etc..

A treatment process can be used to enhance the bonding strength at the bonding interface <NUM>. The treatment process can prepare the surfaces of DRAM interconnect layer <NUM> and the CPU interconnect layer <NUM> so that the surfaces of the insulating layers <NUM>/<NUM> form chemical bonds. The treatment process can include, for example, plasma treatment (e.g. with F, Cl or H containing plasma) or chemical process (e.g., formic acid). The treatment process can include a thermal process that can be performed at a temperature from about <NUM> to about <NUM>° C in a vacuum or an inert ambient (e.g., with nitrogen or Argon). The thermal process can cause metal inter-diffusion between the CPU interconnect VIAs <NUM> and the DRAM interconnect VIAs <NUM>. As a result, metallic materials in the corresponding pairs of the interconnect VIAs can be inter-mixed with each other or forming alloy after the bonding process.

The first and/or the second substrate can be thinned after bonding. In some embodiments, a handle wafer (e.g., glass, plastic, or silicon) can be attached to the first or the second substrate prior to the Substrate thinning process can include one or more of grinding, dry etching, wet etching, and chemical mechanical polishing (CMP).

An example of an embodiment of the present disclosure will now be described with reference to <FIG>.

<FIG> illustrates a schematic view of an exemplary 3D IC device <NUM>, according to some embodiments of the present disclosure. The 3D IC device <NUM> includes a microprocessor chip, a first memory chip and a second memory chip. In some embodiments, the microprocessor chip can be any suitable microprocessor, for example, a digital signal processor, a microcontroller, or a central computing unit (CPU) for a computer or a mobile device. In an example, the microprocessor chip can be similar to the microprocessor chip <NUM> shown in <FIG> and is also referred to as the CPU chip <NUM>. In some embodiments, the first memory chip can be any volatile memory, for example, a static random-access memory (SRAM) or a dynamic random-access memory (DRAM). In an example, the first memory chip can be similar to the memory chip <NUM> shown in <FIG>, <FIG> and is also referred to as the DRAM chip <NUM>. In some embodiments, the second memory chip can be any suitable non-volatile memory such as a phase change memory, a magnetic random-access memory, a flash memory, etc. In an example, the second memory chip can be a NAND flash memory and is referred to as the NAND chip <NUM>.

The CPU chip <NUM> includes a plurality of CPU interconnect VIAs <NUM>, similar to those depicted in <FIG> and <FIG>. The NAND chip <NUM> also includes a plurality of NAND interconnect VIAs <NUM>. The DRAM chip <NUM> includes a plurality of DRAM interconnect VIAs 107f and 107b on a top and bottom sides of the DRAM chip <NUM>, respectively. The "top" side of the chip is referred to as the side where functional devices (e.g., transistors, diodes, etc.) are fabricated. The "bottom" side of the chip is opposite of the top side.

Through hybrid bonding, the NAND chip <NUM>, the DRAM chip <NUM> and the CPU <NUM> can be joined together to form the 3D IC device <NUM>. The DRAM chip <NUM> and the CPU chip <NUM> can be electrically connected together through the CPU/DRAM interconnect VIAs <NUM>/107b, while the DRAM chip <NUM> and the NAND chip <NUM> can be electrically connected together through the DRAM/NAND interconnect VIAs 107f/<NUM>.

<FIG> illustrates a cross-section of an exemplary DRAM chip <NUM> at certain process stage, according to some embodiments of the present disclosure. The DRAM chip <NUM> can be similar to the DRAM chip <NUM> in <FIG>, including the DRAM chip <NUM>, the bonding layer <NUM> disposed on the DRAM chip <NUM>, and a plurality of DRAM interconnect VIAs 107f formed on the top side of the DRAM chip <NUM>.

In some embodiments, the DRAM chip <NUM> also includes a DRAM substrate contact <NUM>. The DRAM substrate contact <NUM> can be formed using similar material and process as the contact structure <NUM>. The DRAM substrate contact <NUM> can provide electrical connection to the DRAM substrate <NUM>. In some embodiments, a plurality of metal levels with contact structures <NUM> and conductive lines <NUM> can be connected with the substrate contact <NUM>.

In some embodiments, DRAM substrate <NUM> can be double-side polished prior to DRAM device <NUM> fabrication. In this example, the DRAM substrate <NUM> includes surfaces on the top and bottom side both polished and treated to provide a smooth surface for high quality semiconductor devices. In some embodiments, the DRAM substrate <NUM> can be thinned down from a standard wafer thickness (about <NUM> for a silicon substrate) to a thickness mechanically strong enough to support the subsequent structures, for example, about <NUM> thick for a <NUM> silicon wafer.

<FIG> illustrates a cross-section of an exemplary NAND chip <NUM> at certain process stage, according to some embodiments of the present disclosure. The NAND chip <NUM> can include the NAND chip <NUM>, a bonding layer <NUM> disposed on the NAND chip <NUM>, and a plurality of the NAND interconnect VIAs <NUM>, where the NAND interconnect VIA <NUM> extends through the bonding layer <NUM> and forms electrical connection with the NAND chip <NUM>.

The NAND chip <NUM> can include a NAND substrate <NUM>, peripheral devices (not shown), NAND memory cells and a NAND interconnect layer <NUM>. The NAND substrate <NUM> can be similar to the CPU substrate <NUM>. The NAND interconnect layer <NUM> can be similar as the CPU interconnect layer <NUM> and can be formed using similar materials and similar processes. For example, interconnect structures (e.g., contact structures <NUM> and conductive lines <NUM>) and insulating layer <NUM> of the NAND interconnect layer <NUM> are similar to the interconnect structures (e.g., contact structures <NUM>, conductive lines <NUM>) and insulating layer <NUM> of the CPU interconnect layer <NUM>, respectively.

In some embodiments, the NAND peripheral device can include any active and/or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc. A plurality of NAND peripheral devices can form suitable digital, analog, and/or mixed-signal peripheral circuits to support the operation of the NAND chip <NUM>. For example, the peripheral circuit can include a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, timing and controls, and the like circuitry. The NAND peripheral device can be similar to the CPU device <NUM> and can be formed using similar processes.

It is noted that x and y axes are added in <FIG> to further illustrate the spatial relationship of the components in NAND chip <NUM>. The substrate <NUM> includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (the lateral direction or width direction). As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a semiconductor device (e.g., the NAND chip <NUM>) is determined relative to the substrate of the semiconductor device (e.g., the substrate <NUM>) in the y-direction (the vertical direction or thickness direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing spatial relationship is applied throughout the present disclosure.

In some embodiments, the NAND chip <NUM> can be a 3D NAND Flash memory in which the NAND memory cells includes an NAND memory string <NUM>. The NAND memory string <NUM> extends through a plurality of conductor layer <NUM> and dielectric layer <NUM> pairs. The plurality of conductor/dielectric layer pairs are also referred to herein as an "alternating conductor/dielectric stack" <NUM>. The conductor layers <NUM> and the dielectric layers <NUM> in alternating conductor/dielectric stack <NUM> alternate in the vertical direction. In other words, except the ones at the top or bottom of the alternating conductor/dielectric stack <NUM>, each conductor layer <NUM> can be sandwiched by two dielectric layers <NUM> on both sides, and each dielectric layer <NUM> can be sandwiched by two conductor layers <NUM> on both sides. The conductor layers <NUM> can each have the same thickness or have different thicknesses. Similarly, the dielectric layers <NUM> can each have the same thickness or have different thicknesses. In some embodiments, the alternating conductor/dielectric stack <NUM> includes more conductor layers or more dielectric layers with different materials and/or thicknesses than the conductor/dielectric layer pair. The conductor layers <NUM> can include conductor materials such as W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, silicides (e.g., NiSix, WSix, CoSix, TiSix) or any combination thereof. The dielectric layers <NUM> can include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in <FIG>, each NAND memory string <NUM> can include a semiconductor channel <NUM> and a memory film <NUM>. In some embodiments, the semiconductor channel <NUM> includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, the memory film <NUM> is a composite layer including a tunneling layer, a storage layer (also known as "charge trap/storage layer"), and a blocking layer. Each NAND memory string <NUM> can have a cylinder shape (e.g., a pillar shape). The semiconductor channel <NUM>, the tunneling layer, the storage layer, and the blocking layer are arranged along a direction from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon nitride, or any combination thereof. The blocking layer can include silicon oxide, silicon nitride, high dielectric constant (high-k) dielectrics, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the memory film <NUM> includes ONO dielectrics (e.g., a tunneling layer including silicon oxide, a storage layer including silicon nitride, and a blocking layer including silicon oxide).

In some embodiments, the NAND memory strings <NUM> further include a plurality of control gates (each being part of a word line for NAND memory strings <NUM>). Each conductor layer <NUM> in alternating conductor/dielectric stack <NUM> can act as a control gate for each memory cell of NAND memory string <NUM>. As shown in <FIG>, the NAND memory string <NUM> can include a lower select gate <NUM> (e.g., a source select gate) at a lower end of the NAND memory string <NUM>. The NAND memory string <NUM> can also include a top select gate <NUM> (e.g., a drain select gate) at an upper end of the NAND memory string <NUM>. As used herein, the "upper end" of a component (e.g., NAND memory string <NUM>) is the end further away from NAND substrate <NUM> in the y-direction, and the "lower end" of the component (e.g., NAND memory string <NUM>) is the end closer to NAND substrate <NUM> in the y-direction. As shown in <FIG>, for each NAND memory string <NUM>, the drain select gate <NUM> can be above the source select gate <NUM>. In some embodiments, the select gates <NUM>/<NUM> include conductor materials such as W, Co, Cu, Al, doped silicon, silicides, or any combination thereof.

In some embodiments, the NAND chip <NUM> includes an epitaxial layer <NUM> on an lower end of the semiconductor channel <NUM> of the NAND memory string <NUM>. The epitaxial layer <NUM> can include a semiconductor material, such as silicon. The epitaxial layer <NUM> can be epitaxially grown from a semiconductor layer <NUM> on the NAND substrate <NUM>. The semiconductor layer <NUM> can be un-doped, partially doped (in the thickness direction and/or the width direction), or fully doped by p-type or n-type dopants. For each NAND memory string <NUM>, the epitaxial layer <NUM> is referred to herein as an "epitaxial plug. " The epitaxial plug <NUM> at the lower end of each NAND memory string <NUM> can contact both the semiconductor channel <NUM> and a doped region of semiconductor layer <NUM>. The epitaxial plug <NUM> can function as the channel of the lower selective gate <NUM> at the lower end of NAND memory string <NUM>.

In some embodiments, the array device further includes multiple word line contacts <NUM> in a staircase structure region. Each word line contact <NUM> can form electrical contact with a corresponding conductor layer <NUM> in alternating conductor/dielectric stack <NUM> to individually control a memory cell. The word line contact <NUM> can be formed by dry/wet etching of a contact hole, followed by filling with a conductor, for example, W, Ti, TiN, Cu, TaN, Al, Co, Ni, or any combination thereof.

As shown in <FIG>, the NAND chip <NUM> also includes bit line contacts <NUM> formed on the top of the NAND memory strings <NUM> to provide individually access to the semiconductor channels <NUM> of the NAND memory strings <NUM>.

The conductive lines connected to the word line contacts <NUM> and the bit line contacts <NUM> form word lines and bit lines of the NAND chip <NUM>. Typically the word lines and bit lines are laid perpendicular to each other (e.g., in rows and columns, respectively), forming an "array" of the memory.

In some embodiments, the NAND chip <NUM> also includes a NAND substrate contact <NUM>. The NAND substrate contact <NUM> can be formed using similar material and process as the contact structure <NUM>. The NAND substrate contact <NUM> can provide electrical connection to the NAND substrate <NUM> from a top surface 900t of the NAND chip <NUM> through the NAND interconnect VIA <NUM>. In some embodiments, a plurality of metal levels with contact structures <NUM> and conductive lines <NUM> can be used in connecting the substrate contact <NUM>.

<FIG> illustrates a cross-section of an exemplary 3D IC device <NUM>, according to some embodiments of the present disclosure. The 3D IC device <NUM> includes the DRAM chip <NUM> and the NAND chip <NUM>, where the NAND chip <NUM> can be bonded with the DRAM chip <NUM>, similar to the structure and method used for 3D IC device <NUM> in <FIG>. The NAND chip <NUM> and the DRAM chip <NUM> can be bonded together at die/chip level or at wafer level to form 3D IC device <NUM>. The NAND interconnect VIAs <NUM> and DRAM interconnect VIAs 107f can form electrical connections after the bonding.

The 3D IC device <NUM> includes a first bonding interface <NUM> formed between the insulating layer <NUM> of the DRAM interconnect layer <NUM> and the insulating layer <NUM> of the NAND interconnect layer <NUM>. Interconnect VIAs 107f/<NUM> are joined at the first bonding interface <NUM> to electrically connect the conductive lines <NUM>/contact structures <NUM> of the DRAM interconnect layer <NUM> with the conductive line <NUM>/contact structures <NUM> of the NAND interconnect layer <NUM>. As such, the DRAM chip <NUM> and the NAND chip <NUM> are electrically connected.

The 3D IC device <NUM> includes the first bonding interface <NUM> formed between the bonding layer <NUM> of the DRAM chip <NUM> and the bonding layer <NUM> of the NAND chip <NUM>. In this example, the interconnect VIAs 107f/<NUM> extend through the bonding layer <NUM>/<NUM>, respectively, and also form electrical connections between the conductive line <NUM>/contact structure <NUM> of the DRAM interconnect layer <NUM> and the conductive line <NUM>/contact structure <NUM> of the NAND interconnect layer <NUM>. As such, the devices and circuits on the DRAM chip <NUM> and the NAND chip <NUM> are electrically connected.

In some embodiments, the 3D IC device <NUM> can include the DRAM substrate contact <NUM> connected to the conductive line <NUM> and the contact structure <NUM> of DRAM chip <NUM>. In some embodiments, the 3D IC device <NUM> can include the NAND substrate contact <NUM> connected to the conductive line <NUM> and the contact structure <NUM> of NAND chip <NUM>.

In some embodiments, the 3D IC device <NUM> can include the DRAM substrate contact <NUM> connected to the NAND substrate contact <NUM> at the first bonding interface <NUM> through DRAM/NAND interconnect VIAs 107f/<NUM> DRAM/NAND. In some embodiments, the 3D IC device <NUM> can include the DRAM substrate contact <NUM> connected to the conductive line <NUM> and the contact structure <NUM> of the NAND chip <NUM>. In some embodiments, the 3D IC device <NUM> can include the NAND substrate contact <NUM> connected to the conductive line <NUM> and the contact structure <NUM> of the DRAM chip <NUM>. In these examples, the electrical connections cross over the first bonding interface <NUM>.

After bonding, any device or circuit on the DRAM chip <NUM> can be electrically connected to any device or circuit on the NAND chip <NUM>. <FIG> illustrates an embodiment that the NAND chip <NUM> is bonded on top of the DRAM chip <NUM>. In some embodiments, the DRAM chip <NUM> can be bonded on top of the NAND chip <NUM>.

<FIG> illustrates a cross-section of an exemplary 3D IC device <NUM>, according to some embodiments of the present disclosure. The 3D IC device <NUM> includes a vertical interconnect structure (also referred to as through-silicon-VIA (TSV)) <NUM> formed in the DRAM substrate <NUM> of the 3D IC device <NUM> (in <FIG>), wherein the TSV <NUM> forms an electrical connection with the DRAM substrate contact <NUM>.

In some embodiments, an electrical connection can be formed between the TSV <NUM>, the DRAM substrate contact <NUM>, the conductive line <NUM> and/or contact structure <NUM> of the DRAM chip. In this example, any device or circuit on the DRAM chip <NUM> can be electrically wired to the bottom surface 402b through TSV <NUM>.

An electrical connection is formed between the TSV <NUM>, the DRAM substrate contact <NUM> and the DRAM/NAND interconnect VIAs 107f/<NUM>. As such, electrical connection can be established from the TSV <NUM> of the DRAM chip <NUM> to any device or circuit on the NAND chip <NUM> through various electrical paths using the contact structure <NUM>, conductive line <NUM> or substrate contact <NUM> of the NAND chip <NUM>.

In some embodiments, the TSV <NUM> can be formed after thinning the DRAM substrate <NUM> using grinding, CMP, RIE, wet chemical etching, etc. In some embodiments, a protective film can be disposed over the 3D IC device <NUM> prior to thinning process on the DRAM substrate <NUM>. The protective film can include photoresist, polyimide, silicon oxide, silicon nitride, etc., and can be removed after the thinning process.

The 3D IC device <NUM> also includes the through-silicon-VIA (TSV) <NUM> in the NAND substrate <NUM> from a surface 1100t of the 3D IC device <NUM> (not shown in <FIG>), wherein the TSV <NUM> forms an electrical connection with the NAND substrate contact <NUM>. An electrical connection is formed between the TSV <NUM>, the NAND substrate contact <NUM>, the conductive line <NUM> and/or contact structure <NUM> of the NAND chip <NUM>. In this example, any device or circuit on the NAND chip <NUM> can be electrically wired to the surface 1100t through TSV <NUM>. In some embodiments, an electrical connection can be formed between the TSV <NUM> in the NAND substrate <NUM>, the NAND substrate contact <NUM>, and the DRAM/NAND interconnect VIAs 107f/<NUM>. As such, electrical connection can be established from the TSV <NUM> of the NAND chip <NUM> to any device or circuit on the DRAM chip <NUM> through various electrical paths using the contact structure <NUM>, conductive line <NUM> or substrate contact <NUM> of the DRAM chip <NUM>.

<FIG> illustrates a cross-section of an exemplary 3D IC device <NUM>, according to some embodiments of the present disclosure. The 3D IC device <NUM> includes a bonding layer <NUM> and a plurality of DRAM interconnect VIAs 107b formed on the bottom surface 420b of the 3D IC device <NUM> in <FIG>, wherein the DRAM interconnect VIAs 107b extend through the bonding layer <NUM>. The bonding layer <NUM> and the DRAM interconnect VIA 107b are similar to the bonding layer <NUM> and the DRAM interconnect VIA 107f and are formed by similar material and processes.

In some embodiments, the DRAM interconnect VIA 107b is disposed on the TSV <NUM> and forms electrical connection with the TSV <NUM>. In <FIG>, for simplicity, not all TSVs <NUM> are drawn to shown electrical connections with the DRAM interconnect VIAs 107b.

<FIG> illustrates a cross-section of an exemplary 3D IC device <NUM>, according to some embodiments of the present disclosure. The 3D IC device <NUM> includes the 3D IC device <NUM> (shown in <FIG>) and the CPU chip <NUM> (shown in <FIG>), wherein the 3D IC device <NUM> is bonded to the CPU chip <NUM> with a second bonding interface <NUM>. The CPU interconnect VIA <NUM> on the CPU chip <NUM> is in electrical contact with the DRAM interconnect VIA 107b on the 3D IC device <NUM>. The 3D IC device <NUM> and the CPU chip <NUM> can be bonded together at die/chip level or at wafer level to form 3D IC device <NUM>.

The 3D IC device <NUM> includes the second bonding interface <NUM> formed between the insulating layer <NUM> of the CPU interconnect layer <NUM> and the DRAM substrate <NUM> of the 3D IC device <NUM>. Interconnect VIAs 107b/<NUM> are joined at the second bonding interface <NUM> to electrically connect the conductive lines <NUM>/contact structures <NUM> of the CPU interconnect layer <NUM> with the TSVs <NUM> of the 3D IC device <NUM>. As such, the CPU chip <NUM> and the DRAM chip <NUM> are electrically connected. Through the TSV <NUM>, the DRAM substrate contact <NUM>, the conductive lines <NUM>/<NUM> and/or the contact structures <NUM>/<NUM> on the CPU/DRAM chip <NUM>/<NUM>, any device and circuit on the DRAM chip <NUM> can be electrically connected with any device and circuit on the CPU chip <NUM>.

In some embodiments, the CPU chip <NUM> can also include CPU substrate contacts (not shown in <FIG>), similar to the DRAM substrate contacts <NUM>. The CPU substrate contacts can provide further electrical path between the DRAM chip <NUM> and the CPU chip <NUM> or within the CPU chip <NUM>.

The DRAM substrate <NUM> also includes a dielectric layer on the bottom surface 402b (not shown in <FIG>). The second bonding interface <NUM> is formed between the dielectric layer on the bottom surface 402b of the DRAM substrate <NUM> and the insulating layer <NUM> of the CPU interconnect layer <NUM>. The dielectric layer on the bottom surface 402b of the DRAM substrate <NUM> can include silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

The 3D IC device <NUM> includes the second bonding interface <NUM> formed between the bonding layer <NUM> of the DRAM chip <NUM> and the bonding layer <NUM> of the CPU chip <NUM>. In this example, the interconnect VIAs 107b /<NUM> extend through the bonding layer <NUM>/<NUM>, respectively, and also form electrical connections between the TSV <NUM> of the DRAM chip <NUM> and the conductive line <NUM>/contact structure <NUM> of the CPU interconnect layer <NUM>. As such, through the TSV <NUM>, the substrate contact <NUM>, the conductive lines <NUM>/<NUM> and/or the contact structures <NUM>/<NUM> on the CPU/DRAM chip <NUM>/<NUM>, any devices and circuits on the CPU chip <NUM> and the DRAM chip <NUM> can be electrically connected.

The 3D IC device <NUM> includes three electrically connected chips, e.g., the CPU chip <NUM>, the DRAM chip <NUM> and the NAND chip <NUM>, wherein the NAND chip <NUM> and the DRAM chip <NUM> are bonded at the first bonding interface <NUM>, and the DRAM chip <NUM> and the CPU chip <NUM> are bonded at the second bonding interface <NUM>. Across the first bonding interface <NUM>, any device or circuit on the NAND chip <NUM> can be electrically connected with any device or circuit on the DRAM chip <NUM>. Across the second bonding interface <NUM>, any device or circuit on the DRAM chip <NUM> can be electrically connected to any device or circuit on the CPU chip <NUM>.

The NAND chip <NUM> includes the substrate contact <NUM> and the DRAM chip <NUM> includes the substrate contact <NUM>. In this example, a direct electrical connection can be formed between the NAND substrate contact <NUM> and the DRAM substrate contact <NUM> through the interconnect VIAs <NUM>/107f with minimum number of conductive lines <NUM>/<NUM> and contact structures <NUM>/<NUM>. As such, any device/circuit on the CPU chip <NUM> can be directly connected to any device/circuit on the NAND chip <NUM> without extensive length of wirings through the DRAM chip <NUM>.

In some embodiments, the CPU chip <NUM> can also include substrate contacts (not shown in <FIG>). In this example, external signals can be sent to any one of the three chips on the 3D IC device <NUM> in parallel. The CPU chip <NUM>, DRAM chip <NUM> and the NAND chip <NUM> can be accessed individually and directly by an external device.

<FIG> illustrated an example of the 3D IC device <NUM> where the DRAM chip <NUM> is bonded to the NAND chip <NUM> first forming 3D IC device <NUM> (see <FIG>), where the top side of DRAM chip <NUM> facing the top side of the NAND chip <NUM> while the bottom of the NAND substrate <NUM> and the bottom of the DRAM substrate <NUM> forming the two sides of the 3D IC device <NUM> after bonding. Here, the "top" side of a substrate is referred to the side where active semiconductor devices are formed. In this example, the top side of the CPU chip <NUM> is bonded subsequently to the bottom surface of the DRAM substrate <NUM> during the second bonding process to form the 3D IC device <NUM>.

In some embodiments, the CPU chip <NUM> can be bonded to the DRAM chip <NUM> first, where the top side of the CPU chip <NUM> facing the top side of the DRAM chip <NUM>. In this example, the NAND chip <NUM> can be bonded subsequently to the DRAM chip <NUM>, where the top side of the NAND chip <NUM> facing the bottom side of the DRAM substrate <NUM>.

<FIG> illustrates a cross-section of an exemplary 3D IC device <NUM>, according to some embodiments of the present disclosure. The 3D IC device <NUM> includes an insulating film <NUM> disposed on the NAND substrate <NUM> of the 3D IC device <NUM> in <FIG>, one or more input/output (I/O) pads <NUM> formed in the insulating film <NUM>, and one or more TSVs <NUM> connecting the I/O pads to the substrate contacts <NUM> through the NAND substrate <NUM>. The TSV <NUM> can be similar to the TSV <NUM> of the DRAM chip <NUM> and can be formed using similar process.

The insulating film <NUM> can be any suitable insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide (such as F-, C-, N- or H- doped oxides), tetraethoxysilane (TEOS), polyimide, spin-on-glass (SOG), low-k dielectric material such as porous SiCOH, silsesquioxan (SSQ), or any combination thereof. The insulating film <NUM> can be deposited by one or more thin film deposition processes such as CVD, PVD, PECVD, ALD, high-density-plasma CVD (HDP-CVD), sputtering, spin-coating, or any combination thereof.

In some embodiments, the I/O pad <NUM> is coplanar with the insulating film <NUM>. In some embodiments, the I/O pad <NUM> can be extruded or recessed from the insulating film <NUM>. The I/O pad <NUM> can include any suitable conductive material, for example, copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), aluminum (Al), TiN, TaN, Al, or any combination thereof. The I/O pad <NUM> can be disposed by one or more thin film deposition processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof. The fabrication process of the I/O pad <NUM> can also include, but not limited to, lithography, wet/dry etching, planarization (e.g., RIE etch-back and CMP).

In some embodiments, the insulating film <NUM>, the I/O pad <NUM> and the TSV <NUM> can also be formed on the CPU substrate <NUM>. In this example, the CPU chip <NUM> can include one or more substrate contacts as well.

Through the I/O pads <NUM>, external devices can be connected to the 3D IC device <NUM>. In some embodiments, through the I/O pads <NUM>, external devices can be connected to any device or circuit on the NAND chip <NUM>, the DRAM chip <NUM> and/or the CPU chip <NUM>.

<FIG> illustrates an exemplary fabrication process <NUM> for forming the 3D IC devices shown in <FIG>, in accordance with some embodiments. It should be understood that the operations shown in fabrication process <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. In some embodiments, some process steps of exemplary fabrication process <NUM> can be omitted or include other process steps that are not described here for simplicity. In some embodiments, process steps of method <NUM> can be performed in a different order and/or vary.

At process step S1510, a first memory chip is formed on a first substrate. In some embodiments, the forming of the first memory chip includes forming a static random-access memory or a dynamic random-access memory. In an example, the first memory chip can be the DRAM chip <NUM> in <FIG>. The DRAM chip <NUM> can include DRAM peripheral devices, DRAM memory cells and the DRAM interconnect layer <NUM>. The fabrication process of DRAM chip <NUM> is described with respect to <FIG>, at process step S620 in <FIG>, and <FIG>.

In some embodiments, the DRAM chip includes a bonding layer, a plurality of interconnect VIAs and a substrate contact on the top side, which are illustrated, for example in <FIG>, as the bonding layer <NUM>, the DRAM interconnect VIAs 107f and the DRAM substrate contact <NUM>. The top side of the DRAM chip is referred to the side of the DRAM substrate where the DRAM peripheral devices and memory cells are formed.

In some embodiments, the bonding layer <NUM> can be disposed on the DRAM chip <NUM> after completing the DRAM interconnect layer <NUM>. The bonding layer <NUM> can include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride or any combination thereof. The bonding layer <NUM> can also include adhesion materials, for example, epoxy resin, polyimide, dry film, photosensitive polymer, etc. The bonding layer <NUM> can be formed by one or more thin film deposition processes such as CVD, PVD, PECVD, ALD, high-density-plasma CVD (HDP-CVD), sputtering, spin-coating, or any combination thereof.

In some embodiments, the DRAM interconnect VIAs 107f can be formed in the DRAM interconnect layer <NUM>, electrically connected to one or more of the conductive lines <NUM> and/or the contact structures <NUM> on the DRAM chip <NUM>. The fabrication process of the DRAM interconnect VIA 107f can include photolithography and wet/dry etching to form a trench for the DRAM interconnect VIA 107f. Next, a layer of conductive material is disposed on the DRAM chip <NUM> to fill up the trench for the DRAM interconnect VIA 107f. In some embodiments, the DRAM interconnect VIA 107f can include conductive material such as copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), aluminum (Al), tantalum, titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof. The conductive material of DRAM interconnect VIA 107f can be formed by one or more thin film deposition processes such as CVD, PVD, plating, sputtering, evaporation, or any combination thereof. The excess conductive material outside of the trench can be removed by using a planarization process (e.g., CMP, or RIE etch-back).

At process step S1520, a second memory chip is formed on a second substrate. In some embodiments, the forming of the second memory chip includes forming a phase change memory, a magnetic random-access memory or a flash memory. In an example, the second memory chip can be the NAND chip <NUM> in <FIG>. The NAND chip <NUM> can include NAND peripheral devices, NAND memory cells and the NAND interconnect layer <NUM>.

In some embodiments, the NAND peripheral devices can be any suitable semiconductor devices, such as n-type MOSFETs, p-type MOSFETs, diodes, resistors, capacitors, inductors, etc. The fabrication processes for the peripheral devices are similar to the CPU devices or DRAM peripheral devices.

In some embodiments, the NAND chip <NUM> is a 3D NAND flash memory. The NAND memory cells can include a NAND memory string <NUM> and a staircase structure.

In some embodiments, fabrication of the NAND chip <NUM> can include forming a plurality of dielectric layer pairs (also referred to herein as an "alternating dielectric stack") with a first dielectric layer <NUM> and a second dielectric layer (not shown in figures) that is different from first dielectric layer <NUM>. In some embodiments, the first dielectric layer can be silicon oxide and the second dielectric layer can be silicon nitride. Alternating dielectric stack can be formed by one or more thin film deposition processes such as CVD, PVD, ALD, sputtering, or any combination thereof.

In some embodiments, fabrication of the NAND chip <NUM> can also include forming a staircase structure at an end of the alternating dielectric stack by using multiple etch-trim processes.

In some embodiments, fabrication of the NAND chip <NUM> can also include removing the second dielectric layer and replacing with a conductor layer <NUM> to form an alternating conductor/dielectric stack <NUM>. The replacement of the second dielectric layers with conductor layers <NUM> can be performed by wet etching the second dielectric layers selective to first dielectric layers <NUM> and filling the structure with conductor layers <NUM>. The conductor layer <NUM> includes polysilicon, W, Co, Ti, TiN, Ta, TaN, Al, Ni, silicides, etc., and can be filled by CVD, ALD, etc..

In some embodiments, fabrication of the NAND chip <NUM> can further include forming a plurality of NAND memory strings <NUM> penetrating alternating conductor/dielectric stack <NUM>. In some embodiments, fabrication processes to form NAND memory strings <NUM> can include forming a semiconductor channel <NUM> that extends vertically through alternating conductor/dielectric stack <NUM>. In some embodiments, semiconductor channel <NUM> can be an amorphous silicon layer or a polysilicon layer formed by using a thin film deposition process, such as a CVD, ALD, etc..

In some embodiments, fabrication processes to form NAND memory strings <NUM> can further include forming a memory film <NUM> between semiconductor channel <NUM> and the plurality of conductor/dielectric layer pairs in alternating conductor/dielectric stack <NUM>. Memory film <NUM> can be a composite dielectric layer, such as a combination of multiple dielectric layers such as a blocking layer, a storage layer, and a tunneling layer.

The blocking layer can be used for blocking the outflow of the electronic charges. In some embodiments, the blocking layer can be a silicon oxide layer or a combination of silicon oxide/silicon oxynitride/silicon oxide (SiO<NUM>-SiON-SiO<NUM>) multi-layer stack. In some embodiments, the blocking layer includes high dielectric constant (high-k) dielectrics (e.g., aluminum oxide). In one example, the blocking layer includes a silicon oxide layer formed by In-Situ Steam Generation (ISSG) oxidation after a silicon nitride deposition process.

The storage layer can be used for storing electronic charges. The storage and/or removal of charges in the storage layer can impact the on/off state and/or a conductance of the semiconductor channel. The storage layer can include polycrystalline silicon (polysilicon) or silicon nitride. The storage layer can include one or more films of materials including, but are not limited to, silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride, or any combination thereof. In some embodiments, the storage layer can include a nitride layer formed by using one or more deposition processes.

The tunneling layer can be used for tunneling electronic charges (electrons or holes). The tunneling layer can be dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the tunneling layer can be an oxide layer formed by using a deposition process.

In some embodiments, fabrication of the NAND chip <NUM> can further include forming an epitaxial layer <NUM> at an end of NAND memory string <NUM>. In some embodiments, epitaxial layer <NUM> can be formed in the second substrate, and correspond to each NAND memory string <NUM> as an epitaxial plug <NUM>. Epitaxial layer <NUM> can be implanted to a desired doping level.

In some embodiments, fabrication of the NAND chip <NUM> can further include forming multiple word line contacts. As illustrated in <FIG>, each word line contact <NUM> can extend vertically to form electrical contact to a corresponding conductor layer <NUM> of the staircase structure, wherein each conductor layer <NUM> can individually control a memory cell of NAND memory strings <NUM>. In some embodiments, fabrication processes to form word line contacts <NUM> include forming a vertical opening through an insulating layer <NUM> using dry/wet etch process, followed by filling the opening with conductive materials such as W, Co, Cu, Al, doped poly-silicon, silicides, or any combination thereof. The conductive materials can be disposed by ALD, CVD, PVD, plating, sputtering, or any combination thereof.

In some embodiments, fabrication of the NAND chip <NUM> can further include forming the NAND interconnect layer <NUM>, which can electrically connect the NAND memory strings with peripheral devices. As shown in <FIG>, in some embodiments, the NAND interconnect layer <NUM> can include one or more contact structures <NUM> and conductive lines <NUM> in the insulating layer <NUM>. In some embodiments, fabrication processes to form NAND interconnect layer <NUM> include forming the insulating layer <NUM>, followed by forming a plurality of bit line contacts <NUM> in contact with NAND memory strings <NUM> in the insulating layer <NUM>. The insulating layer <NUM> can include one or more layers of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The insulating layer <NUM> can be formed by one or more thin film deposition processes such as CVD, PVD, PECVD, ALD, high-density-plasma CVD (HDP-CVD), sputtering, spin-coating, or any combination thereof. Bit line contacts <NUM> can be formed by forming openings in the insulating layer <NUM>, followed by filling the openings with conductive materials such as W, Co, Cu, Al, Ti, TiN, Ta, TaN, doped silicon, silicides, or any combination thereof, deposited by CVD, PVD, sputtering, evaporating, plating, or any combination thereof.

In some embodiments, fabrication processes to form NAND interconnect layer <NUM> further include forming one or more conductive lines <NUM> and one or more contact structures <NUM> in the insulating layer <NUM>. Conductor layers and contact layers can include conductor materials such as W, Co, Cu, Al, Ti, Ta, TiN, TaN, doped silicon, silicides, or any combination thereof. Conductor layers and contact layers can be formed by any suitable known BEOL methods.

In some embodiments, other structures can also be formed on the NAND chip, for example, a bonding layer, a plurality of interconnect VIAs and a substrate contact, which are illustrated in <FIG>, as the bonding layer <NUM>, the NAND interconnect VIAs <NUM> and the NAND substrate contact <NUM>.

In some embodiments, the bonding layer <NUM> can be disposed on the NAND chip <NUM> after completing the NAND interconnect layer <NUM>. The bonding layer <NUM> can include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride or any combination thereof. The bonding layer <NUM> can also include adhesion materials, for example, epoxy resin, polyimide, dry film, photosensitive polymer, etc. The bonding layer <NUM> can be formed by one or more thin film deposition processes such as CVD, PVD, PECVD, ALD, high-density-plasma CVD (HDP-CVD), sputtering, spin-coating, or any combination thereof.

In some embodiments, the NAND interconnect VIAs <NUM> can be formed in the NAND interconnect layer <NUM>, electrically connected to one or more of the conductive lines <NUM> and/or the contact structures <NUM> on the NAND chip <NUM>. The fabrication process of the NAND interconnect VIA <NUM> can include photolithography and wet/dry etching to form a trench for the NAND interconnect VIA <NUM>. Next, a layer of conductive material is disposed on the NAND chip <NUM> to fill up the trench for the NAND interconnect VIA <NUM>. In some embodiments, the NAND interconnect VIA <NUM> can include conductive material such as copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), aluminum (Al), tantalum, titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof. The conductive material of NAND interconnect VIA <NUM> can be formed by one or more thin film deposition processes such as CVD, PVD, plating, sputtering, evaporation, or any combination thereof. The excess conductive material outside of the trench can be removed by using a planarization process (e.g., CMP, or RIE etch-back).

At process step S <NUM>, the DRAM chip is bonded with the NAND chip to form a first 3D IC device. An example of the first 3D IC device is shown in <FIG> as the 3D IC device <NUM>, where the NAND chip <NUM> can be flipped upside down and positioned above the DRAM chip <NUM>. In some embodiments, the DRAM chip <NUM> can be bonded on top of the NAND chip <NUM>.

In some embodiments, the NAND chip <NUM> and the DRAM chip <NUM> can be bonded together at die level (e.g., die-to-die, or chip-to-chip) or at wafer level (e.g., wafer-to-wafer or chip-to-wafer).

In some embodiments, the NAND chip <NUM> is position on the DRAM chip <NUM> by aligning the NAND interconnect VIAs <NUM> with corresponding DRAM interconnect VIAs 107f. As a result, corresponding interconnect VIAs can be connected at a first bonding interface <NUM>, where the DRAM chip <NUM> can be electrically connected to the NAND chip <NUM>.

The NAND chip <NUM> and the DRAM chip <NUM> are joined by hybrid bonding, where the bonding can take place between different materials at a bonding interface simultaneously, e.g., metal to metal and dielectric to dielectric. The hybrid bonding process can be similar to the process described at process step S630 in <FIG>. In this example, metal to metal bonding can take place between the NAND interconnect VIAs <NUM> and the DRAM interconnect VIAs 107f. The dielectric to dielectric bonding can take place between the insulating layer <NUM>/<NUM> of the NAND/DRAM interconnect layers <NUM>/<NUM>, respectively. In some embodiments, the dielectric to dielectric bonding can take place between the bonding layer <NUM> of the NAND chip <NUM> and the bonding layer <NUM> of the DRAM chip <NUM>, wherein the bonding layers <NUM>/<NUM> are dielectric materials, for example, silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the bonding layer can also include an adhesive material to enhance bonding strength, for example, epoxy resin, polyimide, dry film, etc..

In some embodiments, a treatment process can be performed before, during or after bonding. The treatment process can include plasma treatment, wet chemical treatment or thermal treatment, and is similar to the process used at process step S630 for the CPU chip and the DRAM chip.

In some embodiments, the substrates of the NAND chip <NUM> and/or the DRAM chip <NUM> can be thinned after bonding. In some embodiments, a handle wafer (e.g., glass, plastic, or silicon) can be attached to the NAND/DRAM chip <NUM>/<NUM> prior to the thinning process. In some embodiments, substrate thinning process can include grinding, dry etching, wet etching, and chemical mechanical polishing (CMP).

A plurality of vertical interconnect structures (through-silicon-VIAs (TSV)) are formed for the DRAM chip <NUM> and/or the NAND chip <NUM>. The TSV for DRAM chip <NUM> is similar to the TSV <NUM> in <FIG> and the TSV for NAND chip <NUM> is similar to the TSV <NUM> in <FIG>. The TSVs can be formed before or after the bonding of the DRAM chip <NUM> and the NAND chip <NUM>. In some embodiments, TSVs can be formed after substrate thinning.

In some embodiments, the TSV <NUM> can be formed from the bottom surface 420b of the DRAM chip <NUM> by using a patterning process to form a TSV trench followed by conductive material filling and planarization. The patterning process for TSV <NUM> can include lithography and etching. In addition to photoresist, an anti-reflective coating (ARC) such as dielectric ARC (DARC) or bottom ARC (BARC) can be used to improve lithography quality and provide extra protection during etching. In some embodiments, a hard mask (e.g., silicon oxide, silicon nitride or silicon oxynitride) can be deposited on the bottom surface 420b of the DRAM substrate <NUM> prior to TSV <NUM> patterning to provide more protection of underlying materials during etching. The etching process for TSV <NUM> can include, for example, wet chemical etching, reactive ion etching (RIE), high-aspect ratio plasma etching, or any combination thereof. In some embodiments, a deep silicon trench of the TSV <NUM> can be formed by alternating plasma etching using SF<NUM> chemistry and protection film deposition using C<NUM>F<NUM> chemistry. The conductive material used to fill the trench of the TSV <NUM> can include tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, polysilicon, polycrystalline silicon germanium, polycrystalline germanium, silicides (WSix, CoSix, NiSix, AlSix, etc.), or any combination thereof. The conductive materials can be deposited by one or more thin film deposition processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof. The excess conductive materials can be removed by a planarization process, for example, RIE etch-back, chemical-mechanical polishing (CMP). The forming of the TSV <NUM> for the NAND chip <NUM> is similar to the TSV <NUM> described above.

To prepare the NAND chip <NUM> and/or the DRAM chip <NUM> for the next bonding process, in some embodiments, a bonding layer and a plurality of interconnect VIAs can be formed on the bottom side of the DRAM chip after forming the first 3D IC device. Here the "top" side is referred to the side of the DRAM chip <NUM> where DRAM memory cells are formed. In this example shown in <FIG>, the top side of the DRAM chip <NUM> is closer to the bonding interface with the NAND chip <NUM>. Thereby, the bottom side of the DRAM chip is farther away from the bonding interface. The bonding layer and the interconnect VIAs are similar to the bonding layer <NUM> and the DRAM interconnect VIA 107b in <FIG> and can be formed similarly to the bonding layer <NUM> and the DRAM interconnect VIA 107f described in process step S1510.

At process step S1540, a microprocessor chip is formed on a third substrate. In some embodiments, the forming of the microprocessor chip includes forming a digital signal processor, a microcontroller, or a central computing unit for a computer or a mobile device. In one example, the microprocessor chip can be a CPU chip, wherein the CPU chip includes a CPU device and a CPU interconnect layer. The CPU chip can also include a bonding layer and a plurality of interconnect VIAs. The CPU chip can be the CPU chip <NUM> shown in <FIG> and using similar processes as described for process step S610 in <FIG>.

At process step S1550, the first 3D IC device is bonded with the CPU chip to form a second 3D IC device. An example of the second 3D IC device is shown in <FIG> as the 3D IC device <NUM>, where bottom of the DRAM chip <NUM> can be bonded with the top of the CPU chip <NUM>. In some embodiments, the first 3D IC device and CPU chip can be bonded together at die level (e.g., die-to-die, or chip-to-chip) or at wafer level (e.g., wafer-to-wafer or chip-to-wafer). In some embodiments, the bonding is performed by aligning the DRAM interconnect VIAs 107b on the bottom of the DRAM chip <NUM> with the corresponding CPU interconnect VIAs <NUM> on the top of the CPU chip <NUM>.

In some embodiments, the first 3D IC device and the CPU chip <NUM> can be joined by hybrid bonding, wherein the hybrid bonding process is similar to the process described at process step S1520.

In some embodiments, TSVs can be formed on the CPU chip <NUM>. TSVs are formed on the DRAM chip <NUM> and the NAND chip <NUM>. The TSVs are similar to the TSVs <NUM> and <NUM> in <FIG> and <FIG>, and can be formed with similar processes.

One or more I/O pads are formed on the NAND chip <NUM> and optionally on the CPU chip <NUM>, connecting to TSVs of the NAND chip <NUM> and the CPU chip <NUM>, respectively. An example of the I/O pad is shown in <FIG> as I/O pad <NUM>. To form the I/O pad <NUM>, an insulating film is disposed on the substrate of the NAND chip. In the example shown in <FIG>, the top side of the NAND chip is closer to the bonding interface, and the insulating film is disposed on the backside of the NAND substrate <NUM>. The insulating film can be the insulating film <NUM> in <FIG> and can be any suitable insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide (such as F-, C-, N- or H- doped oxides), tetraethoxysilane (TEOS), polyimide, spin-on-glass (SOG), low-k dielectric material such as porous SiCOH, silsesquioxan (SSQ), or any combination thereof. The insulating film <NUM> can be deposited by one or more thin film deposition processes such as CVD, PVD, PECVD, ALD, high-density-plasma CVD (HDP-CVD), sputtering, spin-coating, or any combination thereof.

Next, the insulating film <NUM> is patterned using lithography and wet/dry etching to form a hole or trench for the I/O pad <NUM>, exposing the TSV <NUM> of the NAND chip <NUM> for electrical contact in the subsequent processes. A conductive material is then disposed on the NAND substrate <NUM> and filled the hole and trench for the I/O pad <NUM>. The conductive material for the I/O pad <NUM> can include copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), aluminum (Al), TiN, TaN, Al, or any combination thereof. The conductive material for the I/O pad <NUM> can be disposed by one or more thin film deposition processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof. The excess conductive materials outside the hole/trench of the I/O pad can be removed by a planarization process (e.g., RIE etch-back and CMP). In some embodiments, the I/O pad <NUM> is coplanar with the insulating film <NUM>. In some embodiments, the I/O pad <NUM> can be extruded or recessed from the insulating film <NUM>.

In some embodiments, similar insulating film, I/O pads and TSVs can also be formed on the CPU substrate <NUM>. In this example, the CPU chip <NUM> can include one or more substrate contacts as well.

In some embodiments, one or more functional chips (e.g., SRAM, DRAM, GPU, etc.) can be further bonded with the CPU chip <NUM> of the 3D IC device <NUM> using similar techniques. To prepare the CPU chip <NUM> of the second 3D IC device for another bonding process, the CPU substrate <NUM> can be thinned, followed by TSV, bonding layer and interconnect VIA formation on the bottom of the CPU substrate. As such, through hybrid bonding, multiple functional chips can be stacked on top of each other, forming electrical connections with shorter distance, less latency and higher bandwidth.

Accordingly, various embodiments of three-dimensional devices with integrated circuits and methods of making the same are described in the present disclosure. By integrating functional chips in a vertical stack, the distance of electrical connection between the functional chips can be greatly reduced. Therefore, the 3D IC devices can achieve smaller size, higher density, faster speed and higher bandwidth compared with other two-dimensional ICs.

The foregoing description of the specific embodiments will so fully reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt, for various applications, such specific embodiments, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the disclosure and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the disclosure and guidance.

Claim 1:
A method (<NUM>, <NUM>) for forming a three-dimensional semiconductor device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), comprising:
forming a first memory chip (<NUM>), comprising:
forming at least one first memory cell on a first substrate (<NUM>) and
forming a first interconnect layer (<NUM>) on the at least one first memory cell, the first interconnect layer comprising at least one first interconnect structure;
forming a second memory chip (<NUM>), comprising:
forming at least one second memory cell on a second substrate (<NUM>); and
forming a second interconnect layer (<NUM>) on the at least one second memory cell,
the second interconnect layer comprising at least one second interconnect structure;
bonding the first interconnect layer of the first memory chip with the second interconnect layer of the second memory chip, such that the at least one first memory cell of the first memory chip is electrically connected with the at least one second memory cell of the second memory chip through the at least one first interconnect structure and the at least one second interconnect structure, wherein the bonding of the first interconnect layer of the first memory chip with the second interconnect layer of the second memory chip comprises dielectric-to-dielectric bonding and metal-to-metal bonding at a bonding interface (<NUM>, <NUM>, <NUM>, <NUM>);
forming a microprocessor chip (<NUM>, <NUM>), comprising:
forming at least one microprocessor device (<NUM>) on a third substrate (<NUM>); and
forming a third interconnect layer (<NUM>) on the at least one microprocessor device
(<NUM>), the third interconnect layer comprising at least one third interconnect structure;
bonding the third interconnect layer of the microprocessor chip (<NUM>, <NUM>) with the first substrate of the first memory chip, such that the at least one microprocessor device (<NUM>) of the microprocessor chip (<NUM>, <NUM>) is electrically connected with the at least one first memory cell of the first memory chip (<NUM>) through a TSV (<NUM>) structure through the first substrate (<NUM>), through the at least one first interconnect structure and through the at least one third interconnect structure; and
disposing an insulating film (<NUM>) on the second substrate, wherein one or more input/output (I/O) pads (<NUM>) are formed in the insulating film (<NUM>) and one or more TSVs (<NUM>) connecting through the second substrate the I/O pads to substrate contacts (<NUM>).