Patent Description:
A voltage regulator ideally provides a constant direct current (DC) output voltage regardless of changes in load current or input voltage. Voltage regulators may be classified as either linear regulators or switching regulators. While linear regulators tend to be small and compact, many applications may benefit from the increased efficiency of a switching regulator. A linear regulator may be implemented by a low-dropout (LDO) regulator, for example. A switching regulator may be implemented by a switched-mode power supply (SMPS), such as a buck converter, a boost converter, or a buck-boost converter.

Power management integrated circuits (power management ICs or PMICs) are used for managing the power requirement of a host system and may include and/or control one or more voltage regulators (e.g., boost converters). A PMIC may be used in battery-operated devices, such as mobile phones, tablets, laptops, wearables, etc., to control the flow and direction of electrical power in the devices. The PMIC may perform a variety of functions for the device such as DC-to-DC conversion (e.g., using a voltage regulator as described above), battery charging, power-source selection, voltage scaling, power sequencing, etc. For example, a PMIC may feature a boost converter to boost a voltage level of a DC input voltage.

<CIT> discloses paralleling of monolithic embedded LDO linear regulator power rails to provide an additional load current, while maintaining current sharing and balancing between the paralleled LDOs. Lossless current sensing is used to sense the current for each channel. An offset generator compares the voltages for a master channel and one or more slave channels, and generates an offset voltage according to the sensed error. The offset voltage is added between an input reference voltage and an output regulated voltage to cancel the offset of each channel, so the current of each channel is substantially the same. The lossless current sensing can be realized with equivalent series resistance compensation or current limit sensing. The offset generator can be realized with a resistor and current mirror topology or an input pair added to an error amplifier input.

Certain aspects of the present disclosure relate to a power supply system. The power supply system generally includes a first voltage regulator, a second voltage regulator, outputs of the first voltage regulator and the second voltage regulator being coupled to an output of the power supply system, and a current balancer circuit configured to adjust an output current of the first voltage regulator based on determined headrooms of the first voltage regulator and the second voltage regulator.

Certain aspects of the present disclosure relate to a method of supplying power. The method generally includes generating a first output current via a first voltage regulator, generating a second output current via a second voltage regulator, the first output current and the second output current being sourced to a common output node, and adjusting, via a current balancer circuit, the first output current based on determined headrooms of the first voltage regulator and the second voltage regulator.

Certain aspects of the present disclosure relate to an apparatus for supplying power. The apparatus generally includes means for generating a first output current, means for generating a second output current, the first output current and the second output current being sourced to a common output node, and means for adjusting the first output current based on determined headrooms associated with the means for generating the first output current and the means for generating the second output current.

Certain aspects of the present disclosure are directed to apparatus and techniques for ganging of voltage regulators, such as low-dropout (LDO) regulators. For example, multiple LDO regulators may be used to source current to a common load. Some aspects of the present disclosure use determined headrooms of the LDO regulators to perform current balancing and headroom adjustment for the LDO regulators. For example, if any of the LDO regulators has a headroom that is too low, then the headrooms of (all) the LDO regulators may be increased. If the headrooms of all the LDO regulators are too high, then the headrooms for the LDO regulators may be decreased. If any of the LDO regulators has a headroom that is too high, while one or more other LDO regulators has a headroom that is acceptable, current balancing may be used to balance output currents of the LDO regulators, as described in more detail herein.

The techniques described herein may be used in combination with various wireless technologies such as Code Division Multiple Access (CDMA), Orthogonal Frequency Division Multiplexing (OFDM), Time Division Multiple Access (TDMA), Spatial Division Multiple Access (SDMA), Single Carrier Frequency Division Multiple Access (SC-FDMA), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), and so on. Multiple user terminals can concurrently transmit/receive data via different (<NUM>) orthogonal code channels for CDMA, (<NUM>) time slots for TDMA, or (<NUM>) subbands for OFDM. A CDMA system may implement IS-<NUM>, IS-<NUM>, IS-<NUM>, Wideband-CDMA (W-CDMA), or some other standards. An OFDM system may implement Institute of Electrical and Electronics Engineers (IEEE) <NUM>, IEEE <NUM>, Long Term Evolution (LTE) (e.g., in TDD and/or FDD modes), or some other standards. A TDMA system may implement Global System for Mobile Communications (GSM) or some other standards. These various standards are known in the art.

<FIG> illustrates a device <NUM>. The device <NUM> may be a battery-operated device such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet, a personal computer, etc. The device <NUM> is an example of a device that may be configured to implement the various systems and methods described herein.

The device <NUM> may include a processor <NUM> which controls operation of the device <NUM>. The processor <NUM> may also be referred to as a central processing unit (CPU). Memory <NUM>, which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to the processor <NUM>. A portion of the memory <NUM> may also include non-volatile random access memory (NVRAM). The instructions in the memory <NUM> may be executable to implement the methods described herein.

The device <NUM> may also include a housing <NUM> that may include a transmitter <NUM> and a receiver <NUM> to allow transmission and reception of data between the device <NUM> and a remote location. The transmitter <NUM> and receiver <NUM> may be combined into a transceiver <NUM>. A plurality of antennas <NUM> may be attached to the housing <NUM> and electrically coupled to the transceiver <NUM>. The device <NUM> may also include (not shown) multiple transmitters, multiple receivers, and multiple transceivers.

The device <NUM> may also include a signal detector <NUM> that may be used in an effort to detect and quantify the level of signals received by the transceiver <NUM>. The signal detector <NUM> may detect such signals as total energy, energy per subcarrier per symbol, power spectral density and other signals. The device <NUM> may also include a digital signal processor (DSP) <NUM> for use in processing signals.

The device <NUM> may further include a battery <NUM> used to power the various components of the device <NUM>. The device <NUM> may also include a power management integrated circuit (power management IC or PMIC) <NUM> for managing the power from the battery to the various components of the device <NUM>. The PMIC <NUM> may perform a variety of functions for the device such as DC-to-DC conversion, battery charging, power-source selection, voltage scaling, power sequencing, etc. In certain aspects, the PMIC <NUM> may include a voltage regulator system implemented by ganging of low-dropout (LDO) regulators.

The various components of the device <NUM> may be coupled together by a bus system <NUM>, which may include a power bus, a control signal bus, and a status signal bus in addition to a data bus.

Certain aspects of the present disclosure generally relate to techniques for ganging regulators (e.g., low-dropout (LDO) regulators). Ganging of regulators allows for a power management integrated circuit (PMIC) (e.g., PMIC <NUM>) to meet higher current demands. Ganging of regulators also provides more flexibility to repurpose existing PMICs for different chipsets. Configuring the regulators to operate within an acceptable headroom range (e.g., a desired headroom range for improving performance and lowering power consumption) may save system power and resolve thermal challenges. Some aspects of the present disclosure use current balancing with an aim to increase power efficiency associated with the ganging of the regulators. As used herein, the term "current balancing" may involve adjusting output currents of regulators to improve performance or increase power efficiency associated with the ganging of the regulators, even though the output currents may not be equal after such adjustment. Current balancing may be used when the headroom of an amplifier is too low resulting in the amplifier performance beginning to degrade. In some aspects, the headroom of each amplifier may be detected, and the detected headrooms may be used to adjust the current balancing of the regulator to increase power efficiency for the power supply system.

<FIG> illustrates a power supply system <NUM> that uses ganging LDO regulators, in accordance with certain aspects of the present disclosure. As shown, the power supply system <NUM> may include multiple LDO regulators (e.g., LDO regulator <NUM> and LDO regulator <NUM>) having outputs coupled to a load (e.g., represented by current source <NUM>). For instance, LDO regulator <NUM> may include a transistor <NUM> (referred to as a "pass transistor") having a drain coupled to an input voltage (Vin) node <NUM>, and a source coupled to an output voltage (Vout1) node <NUM>. LDO regulator <NUM> also includes an amplifier <NUM> (e.g., an error amplifier) having a first input (e.g., positive input) coupled to an input reference voltage (Vref_in) node <NUM>, and a second output (e.g., negative output) coupled to the Vout1 node <NUM>. Vref_in at the Vref_in node <NUM> may be used to control output current (Iout1) <NUM> (e.g., drain-to-source current of transistor <NUM>) of the LDO regulator <NUM>, in effect regulating the voltage at the Vout1 node <NUM> (e.g., labeled "Vout1"). In other words, increasing Vref_in may result in an increase of Iout1 <NUM> (e.g., through resistive element R1).

As shown, LDO regulator <NUM> may include a transistor <NUM> having a drain coupled to the Vin node <NUM>, and a source coupled to an output voltage node <NUM> (labeled "Vout2"). LDO regulator <NUM> also includes an amplifier <NUM> having a first input (e.g., positive input) coupled to a common reference voltage (Vref) node <NUM>, and a second input (e.g., negative input) coupled to the Vout2 node <NUM>. Vref at the Vref node <NUM> may be used to control output current (Iout2) <NUM> (e.g., drain-to-source current of transistor <NUM>) of the LDO regulator <NUM>. In other words, increasing Vref may result in an increase of Iout2 <NUM> (e.g., through resistive element R2). As shown, the Vout2 node <NUM> and the Vout1 node <NUM> are coupled to a common output node <NUM> (labeled "Vout") through respective resistive elements R1 and R2 (e.g., in some aspects, the resistances of resistive elements R1 and R2 may differ due to resistor tolerance and/or routing variations). The common output node <NUM> may be coupled to a load circuit, represented by current source <NUM> (labeled "Iload"). The difference between Vin (e.g., at Vin node <NUM>) and Vout1 or Vout2 represents the headroom (HR) of the LDO regulator <NUM> or LDO regulator <NUM>, respectively. HR associated with an LDO is described in more detail with respect to <FIG>.

<FIG> is a graph <NUM> illustrating various operating regions of an LDO regulator, in accordance with certain aspects of the present disclosure. The operating regions described with respect to <FIG> may be associated with different HR and output current ranges for different LDO regulators, depending on the characteristics of the LDO regulators (e.g., characteristics of transistors used to implement the LDO regulators). As shown, an LDO regulator may operate within one of three regions of operation: the triode region <NUM>, the saturation region <NUM>, and an HR acceptable region <NUM> (also referred to as an "HR just right" region). As used herein, operating at an acceptable HR (e.g., operating in the HR acceptable region <NUM>) generally refers to setting a HR for an LDO regulator that provides a better performance as compared to operating in the triode region and a better power efficiency as compared to operating in the saturation region. The HR acceptable region <NUM> may be a region following the curve <NUM>, represented by equation: <MAT> where Irated is the rated current (e.g., <NUM> mV) of the transistor (e.g., transistor <NUM> or transistor <NUM>) of the LDO, Iout is the output current (e.g., Iout1 <NUM> or Iout2 <NUM>) of the LDO regulator, and HR is the headroom of the LDO. As shown, there are different acceptable HRs (e.g., in HR acceptable region <NUM>) depending on the Iout of the LDO regulator. For a specific output current of an LDO regulator, the HR acceptable region <NUM> may have a range (e.g., HR range <NUM>) that may be set based on implementation and using a configured tolerance from the curve <NUM>. The curves <NUM>, <NUM>, <NUM>, <NUM> correspond to different gate-to-source voltages (Vgs) of the transistor of the LDO regulator (e.g., transistor <NUM> or <NUM>).

In some aspects of the present disclosure, an LDO regulator may detect the HR of the LDO regulator. If HR is too low (e.g., the HR corresponds to operating in the triode region <NUM>), the LDO regulator may be unable to source enough current and may request that the HR for the LDO regulator be increased. For example, referring back to <FIG>, when the HR of the LDO regulator <NUM> is too low (e.g., the LDO regulator is operating in the triode region <NUM>), LDO performance starts to roll off. The power supply system <NUM> may include a power supply <NUM> (e.g., a switched-mode power supply, such as a buck converter) that may generate and regulate Vin. When the HR of the LDO regulator <NUM> is too low, the power supply <NUM> may increase Vin, in effect increasing the HR of the LDO regulator <NUM> (e.g., as well as LDO regulator <NUM> since the Vin node <NUM> is common for both of the LDO regulators <NUM>, <NUM>).

If the HR of the LDO regulator is just right (e.g., the LDO regulator is operating in the HR acceptable region <NUM>), the LDO may not request any change to the HR. If the HR of the LDO regulator is too high (e.g., the LDO regulator is operating in the saturation region <NUM>), the LDO regulator may be configured to provide more current (e.g., decreasing the output of current to be sourced by other LDO regulators) until all LDOs report the same condition, and then request that the HR be decreased to save power, as described in more detail with respect to <FIG>.

<FIG> is a table <NUM> illustrating example techniques for HR adjustment and current balancing, in accordance with certain aspects of the present disclosure. As shown, if any of the LDO regulators have too low HR (e.g., is operating in triode region <NUM>), Vin may be increased to increase the HR of all LDO regulators. For example, as shown by table <NUM>, if either LDO regulator <NUM> (also referred to as "LDO <NUM>") or LDO regulator <NUM> (also referred to as "LDO <NUM>") has a HR that is too low, the HR of both LDOs may be increased.

If all the LDO regulators have HRs that are too high (e.g., are operating in the saturation region <NUM>), Vin may be decreased to decrease the HR of all LDO regulators. For example, as shown by table <NUM>, if both LDO regulator <NUM> and LDO regulator <NUM> have HR that is too high, the HR of both LDOs may be decreased.

For other scenarios, such as the HR of one LDO regulator being too high, and the HR of another LDO regulator being just right, current balancing may be used. Referring back to <FIG>, the power supply system <NUM> may include a current balancer <NUM>. The current balancer <NUM> may include an adjustable voltage source <NUM> which may be controlled to set a voltage difference (ΔVref) between Vref and Vref_in. By increasing ΔVref (e.g., increasing the voltage offset associated with the adjustable voltage source <NUM>), Iout1 <NUM> may increase resulting in a decrease of Iout2 <NUM>. On the other hand, by decreasing ΔVref (e.g., decreasing the voltage associated with the adjustable voltage source <NUM>), Iout1 <NUM> may decrease resulting in an increase of Iout2 <NUM>. The current balancer <NUM> may be used to control the gate voltage of the transistor <NUM> of the LDO regulator <NUM> by applying voltage offset to Vref used to control the gate voltage of the transistor <NUM> of LDO regulator <NUM>. Thus, the LDO regulator <NUM> may be referred to as a "slave LDO regulator," and the LDO regulator <NUM> may be referred to as a "master LDO regulator.

If a subset of the LDO regulators is in the HR acceptable region <NUM>, and at least another one of the LDO regulators is in the saturation region <NUM>, current balancing (e.g., via the current balancer <NUM>) may be used to balance the current being sourced by the LDO regulators. For example, as shown by table <NUM>, if LDO regulator <NUM> (LDO <NUM>) has an HR that is too high (e.g., the LDO regulator <NUM> is operating in the saturation region <NUM>), but LDO regulator <NUM> (LDO <NUM>) has an HR that is acceptable (e.g., the LDO regulator <NUM> is operating in the HR acceptable region <NUM>), the current balancer may increase ΔVref. As an example, if LDO regulator <NUM> (LDO <NUM>) is operating at operating point <NUM> shown in <FIG>, ΔVref may be increased, increasing Iout1 of LDO regulator <NUM> such that LDO regulator <NUM> is operating at operating point <NUM> (e.g., in the HR acceptable region <NUM>). On the other hand, if LDO regulator <NUM> (LDO <NUM>) has an HR that is too high (e.g., the LDO regulator <NUM> is operating in the saturation region), but LDO regulator <NUM> (LDO <NUM>) has an HR that is acceptable (e.g., the LDO regulator <NUM> is operating in the acceptable HR region), the current balancer may decrease ΔVref.

In some aspects, power supply system <NUM> of <FIG> may include auto-headroom control (AHC) circuit <NUM>. The LDO regulator <NUM> and LDO regulator <NUM> may provide AHC request signals (AHC_REQ_1 and AHC_REQ_2, respectively) to the AHC circuit <NUM>. The AHC request signals may indicate whether each respective LDO regulator has a HR that is too high, too low, or acceptable. For example, each of the LDO regulator <NUM> and LDO regulator <NUM> may include circuitry that detects the HR of the LDO regulator (e.g., difference between Vin and Vout1 or difference between Vin and Vout2) and the output current of the LDO (e.g., Iout1 <NUM> or Iout2 <NUM>). Based on the detected HR and Iout, each LDO regulator may determine and indicate whether the LDO regulator has an HR that is too high, too low, or acceptable as shown in graph <NUM>. In some cases, each LDO regulator may provide more detailed information, such as the detected HR and Iout of the LDO, via the AHC request signals.

Based on the AHC request signals, the AHC circuit <NUM> may control the power supply <NUM> (e.g., for controlling HR by regulating Vin) and the current balancer <NUM> (e.g., for current balancing), in accordance with the techniques described with respect to <FIG>. For instance, the AHC circuit may provide an AHC direction signal to the power supply indicating whether HR is to be increased or decreased, and an AHC stepper signal indicating a step size associated with the increase or decrease.

While only two LDO regulators are described to facilitate understanding, the aspects of the present disclosure may be implemented for any number of multiple LDO regulators. For example, if ganging of more than two LDO regulators is implemented, a current balancer may be implemented for all except one of the LDO regulators. For example, for three LDO regulators, if any of the three LDO regulators has an HR that is too low, then the HRs of all the LDO regulators may be increased. If the HRs of all three LDO regulators are too high, then the HRs for the LDO regulators may be decreased. If any of the LDO regulators has an HR that is too high, while one or more other LDO regulators has an HR that is acceptable, current balancing may be used to balance output currents of the LDO regulators, as described herein.

Certain aspects described herein may achieve higher power efficiency as compared to conventional implementations. The techniques described herein may be expandable to multiple LDOs across the PMIC and may be implemented for ganging of LDO regulators of different types.

<FIG> is a flow diagram illustrating example operations <NUM> for supplying power, in accordance with certain aspects of the present disclosure. The operations <NUM> may be performed, for example, by the power supply system <NUM>.

The operations <NUM> begin, at block <NUM>, with the power supply system generating a first output current (e.g., Iout1 <NUM>) via a first voltage regulator (e.g., LDO regulator <NUM>). At block <NUM>, the power supply system generates a second output current (e.g., Iout2 <NUM>) via a second voltage regulator (e.g., LDO regulator <NUM>), the first output current and the second output current being sourced to a common output node (e.g., common output node <NUM>). At block <NUM>, the power supply system adjusts, via a current balancer circuit (e.g., current balancer <NUM>), the first output current based on determined headrooms of the first voltage regulator and the second voltage regulator.

In some aspects, the first voltage regulator may include a first transistor (e.g., transistor <NUM>), the determined headroom of the first voltage regulator being a difference between a drain voltage (e.g., Vin) and a source voltage (e.g., Vout1) of the first transistor. The second voltage regulator may include a second transistor (e.g., transistor <NUM>), the determined headroom of the second voltage regulator being a difference between a drain voltage (e.g., Vin) and a source voltage (e.g., Vout2) of the second transistor.

According to the invention the power supply system adjusts, via the current balancer circuit, the first output current based on whether the determined headroom of the first voltage regulator is within a first headroom range (e.g., corresponding to an HR range in the HR acceptable region <NUM> for LDO regulator <NUM>) and whether the determined headroom of the second voltage regulator is within a second headroom range (e.g., corresponding to an HR range in the HR acceptable region <NUM> for LDO regulator <NUM>). An upper limit of the first headroom range or the second headroom range is less than a lower limit of a third headroom range (e.g., an HR range in the saturation region <NUM>) associated with the first voltage regulator or the second voltage regulator operating in saturation, respectively. A lower limit of the first headroom range or the second headroom range may be greater than an upper limit of a fourth headroom range (e.g., an HR range in the triode region <NUM>) associated with the first voltage regulator or the second voltage regulator operating in triode, respectively. In some aspects, adjust the first output current may include decreasing the first output current based on the determined headroom of the second voltage regulator (e.g., LDO regulator <NUM>) being higher than an upper limit of the second headroom range (e.g., HR range in the HR acceptable region <NUM> for LDO regulator <NUM>) and the determined headroom of the first voltage regulator (e.g., LDO regulator <NUM>) being lower than a lower limit of the first headroom range (e.g., HR range in the HR acceptable region <NUM> for LDO regulator <NUM>). In some aspects, adjust the first output current may include increasing the first output current based on the determined headroom of the first voltage regulator (e.g., LDO regulator <NUM>) being higher than an upper limit of the first headroom range (e.g., HR range in the HR acceptable region <NUM> for LDO regulator <NUM>) and the determined headroom of the second voltage regulator being lower than a lower limit of the second headroom range (e.g., HR range in the HR acceptable region <NUM> for LDO regulator <NUM>).

In some aspects, the power supply system may adjust, via a headroom adjustment circuit (e.g., AHC circuit <NUM>), a headroom of the first voltage regulator and a headroom of the second voltage regulator based on at least one of the determined headrooms of the first voltage regulator and the second voltage regulator. In some aspects, adjusting the headrooms may include increasing the headrooms of the first voltage regulator and the second voltage regulator based on the determined headroom of at least one of the first voltage regulator or the second voltage regulator being lower than a headroom range (e.g., HR range in the HR acceptable region <NUM>). In some aspects, adjusting the headrooms may include decreasing the headrooms of the first voltage regulator and the second voltage regulator based on the determined headrooms of the first voltage regulator and the second voltage regulator being higher than a headroom range (e.g., HR range in the HR acceptable region <NUM>).

In some aspects, the power supply system may adjust, via a headroom adjustment circuit (e.g., power supply <NUM>), headrooms of the first voltage regulator and the second voltage regulator. The power supply system may also receive, via an auto headroom control circuit (e.g. AHC circuit <NUM>), indications (e.g., AHC request signals) of the determined headrooms of the first voltage regulator and the second voltage regulator, and control, via the auto headroom control circuit, the headroom adjustment circuit and the current balancer circuit based on the indications of the determined headrooms. In some aspects, the headroom adjustment circuit may include a power supply (e.g., power supply <NUM>) configured to generate an input voltage (e.g., at Vin node <NUM>) for the first voltage regulator and the second voltage regulator. In some aspects, adjusting the first output current may include adjusting an offset (e.g., corresponding to ΔVref) between a first reference voltage (e.g., Vref_in) for the first voltage regulator and a second reference voltage (e.g., Vref) for the second voltage regulator.

The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application-specific integrated circuit (ASIC), or processor.

For example, means for generating an output current may include an LDO regulator, such as the LDO regulator <NUM> or LDO regulator <NUM>. Means for generating an output current may alternatively or additionally include a power source, such as a battery (e.g., battery <NUM>), and one or more power supply circuits (e.g., power supply <NUM>). Means for adjusting may include a current balancer circuit, such as the current balancer <NUM>.

For example, "determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database, or another data structure), ascertaining, and the like. Also, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Also, "determining" may include resolving, selecting, choosing, establishing, and the like.

As an example, "at least one of: a, b, or c" is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.

The functions described may be implemented in hardware, software, firmware, or any combination thereof. The network adapter may be used to implement the signal processing functions of the physical (PHY) layer. In the case of a user terminal, a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus.

The processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture. Alternatively, the processing system may be implemented with an ASIC with the processor, the bus interface, the user interface in the case of an access terminal), supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more FPGAs, PLDs, controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure.

Claim 1:
A power supply system (<NUM>), comprising:
a first voltage regulator (<NUM>);
a second voltage regulator (<NUM>), outputs of the first voltage regulator (<NUM>) and the second voltage regulator (<NUM>) being coupled to an output (<NUM>) of the power supply system (<NUM>); and
a current balancer circuit (<NUM>) configured to adjust an output current (Iout1) of the first voltage regulator (<NUM>) based on determined headrooms (VDS) of the first voltage regulator (<NUM>) and the second voltage regulator (<NUM>); characterized in that:
the current balancer circuit (<NUM>) is configured to adjust the output current (Iout1) of the first voltage regulator (<NUM>) based on whether the determined headroom (VDS) of the first voltage regulator (<NUM>) is within a first headroom range and whether the determined headroom (VDS) of the second voltage regulator (<NUM>) is within a second headroom range ;
an upper limit of the first headroom range or the second headroom range is less than a lower limit of a third headroom range associated with the first voltage regulator (<NUM>) or the second voltage regulator (<NUM>) operating in saturation, respectively; and
a lower limit of the first headroom range or the second headroom range is greater than an upper limit of a fourth headroom range associated with the first voltage regulator (<NUM>) or the second voltage regulator (<NUM>) operating in triode, respectively.