Patent Description:
Any mention and/or discussion of prior art throughout the specification should not be considered, in any way, as an admission that this prior art is well known or forms part of common general knowledge in the field.

The next-generation mobile network, <NUM>, will need to handle the massive scale of Internet-of-Things (IoT) devices and challenging connectivity requirements of diverse devices, sensors, and applications. It will also provide high reliability and availability for autonomous cars and high precision, mission-critical industrial devices in real-time by means of less-than-<NUM> latency. Moreover, as a revolution from <NUM> long term evolution (LTE), <NUM> will provide the download speeds of up to 20Gbps. <NUM> new radio (NR) is a true <NUM> native technology that addresses the need for the above new radio access technology. <NUM> will also provide truly ubiquitous network in the most challenging and remote areas of the world, connecting billions of Internet of Things (IoT) devices with a wide variety of speed and data volume requirements.

However, realizing a <NUM> NR especially in a mobile device is very challenging since it needs to be implemented with many emerged technologies, such as carrier aggregation (CA), multiple input multiple output (MIMO), and mm-Wave for extremely high data rates and robustness. For example, <NUM> will use both sub-<NUM> and mm-Wave frequencies with the above emerged technologies for seamless user experience, which requires multiple radio frequency (RF) channels causing large area and power consumption. Thus, high level of integration of <NUM> NR is crucial for realizing it on a smartphone or a user equipment (UE).

Speeds of up to <NUM> Gbps will be achieved by <NUM> NR in which a combination of innovations such as carrier aggregation (CA), massive multiple input multiple output (MIMO), and high level of quadrature amplitude modulation (QAM) is implemented. <FIG> shows the concept of CA of three carrier components (CCs) with different bandwidth and carrier frequencies, i.e. CC<NUM>/f<NUM>, CC<NUM>/f<NUM> and CC<NUM>/f<NUM>. Since it is based on orthogonal frequency division multiplexing (OFDM) communication, each CC can accommodate a different number of subcarriers of its OFDM signal with different subcarrier e.g. <NUM>, <NUM>, <NUM> spacing, depending on the data rates requirement and frequency availability at the time of data transmission. Assuming that CC<NUM> in <FIG> is in the mm-Wave frequency range, it could occupy wider bandwidth due to the plenty of frequency resources in mm-Wave frequencies and spatial multiplexing technique using antenna beam forming.

Available carrier frequency and bandwidth resources dynamically change in real communication environment. To support carrier aggregation in such dynamic conditions, different number of RF transceivers in different frequency bands (e.g. sub-<NUM>, <NUM> ISM, and/or mm-Wave) at each moment of wireless transmission and reception should be activated simultaneously to deliver multiple data streams from a digital baseband processor, with high data rates and robustness for one or multiple users while the channel availability remains.

<CIT> describes a transceiver architecture for millimeter wave wireless communications. The transceiver architecture includes two transceiver chip modules configured to communicate in different frequency ranges. The first transceiver chip module includes a baseband sub-module, a first radio frequency front end (RF FE) component and associated antenna array. The second transceiver chip module includes a second RF FE component and associated antenna array. The second transceiver chip module is separate from the first transceiver chip module and is electrically coupled to the baseband sub-module of the first transceiver chip module.

However, in the transceiver architecture described in <CIT> multiple transceiver chip modules are required and operate only in millimeter wave frequency ranges. Also, in using printed circuit board technology, the dual chip implementation of the transceiver architecture described in <CIT> does not provide an area and power efficient design.

<CIT> discloses that transmitting and/or receiving beamforming may be applied to the control channel transmission/reception, e.g., in mmW access link system design. Techniques to identify candidate control channel beams and/or their location in the subframe structure may provide for efficient WTRU operation. A framework for beam formed control channel design may support varying capabilities of mBs and/or WTRUs, and/or may support time and/or spatial domain multiplexing of control channel beams. For a multi-beam system, modifications to reference signal design may discover, identify, measure, and/or decode a control channel beam. Techniques may mitigate inter-beam interference. WTRU monitoring may consider beam search space, perhaps in addition to time and/or frequency search space. Enhancements to downlink control channel may support scheduling narrow data beams. Scheduling techniques may achieve high resource utilization, e.g., perhaps when large bandwidths are available and/or WTRUs may be spatially distributed.

<CIT> discloses that a mobile station performs a method for random access in a wireless network. The method includes receiving, from a base station, information regarding a configuration of at least one receive beam of the base station to receive a random access signal. The method also includes configuring at least one transmit beam for a transmission of the random access signal based on the configuration information from the base station. The method further includes transmitting the random access signal to the base station on the at least one transmit beam.

<NPL>, discloses a single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE <NUM>. 11a/b/g wireless LAN. The chip is implemented in a <NUM>-/spl mu/m CMOS technology and occupies a total silicon area of <NUM>/sup <NUM>/. The IC transmits <NUM> dBm/<NUM> dBm error vector magnitude (EVM)-compliant output power for a <NUM>-QAM OFDM signal. The overall receiver noise figure is <NUM>/<NUM> dB at <NUM>/<NUM>. The phase noise is -<NUM> dBc/Hz at a <NUM>-kHz offset and the spurs are below -<NUM> dBc when measured at the <NUM>-GHz transmitter output.

<CIT> discloses methods, systems, and devices for transceiver architecture for millimeter wave wireless communications. A device may include two transceiver chip modules configured to communicate in different frequency ranges. The first transceiver chip module may include a baseband sub-module, a first radio frequency front end (RFFE) component and associated antenna array. The second transceiver chip module may include a second RFFE component and associated antenna array. The second transceiver chip module may be separate from the first transceiver chip module. The second transceiver chip module may be electrically coupled to the baseband sub-module of the first transceiver chip module.

Embodiments of the present invention seek to address at least one of the above problems.

Further improvements and preferable embodiments of the invention are defined by the dependent claims.

In accordance with a first aspect of the present invention, there is provided an apparatus for wireless communication, comprising two or more transceiver array groups, each transceiver array group comprising one or more radio frequency, RF, circuits, and one or more RF front end, RF FE, circuits; wherein the transceiver array groups are configured to operate at different frequencies; wherein the transceiver array groups are configured to be connected to one corresponding digital baseband processor; and wherein the transceiver array groups comprise at least one first transceiver array group configured to operate at cm wavelength or larger.

The transceiver array groups are configured to enable selective coupling of each RF circuit of one transceiver array group to one or more of the RF FE circuits of the same transceiver array group and vice versa. A first of the transceiver array groups includes a first RF FE circuit which is connected to an RF circuit and which does not have phase and amplitude control blocks, and a second of the transceiver array groups different from the first of the transceiver array groups includes a second RF FE circuit which is connected to an RF circuit and which comprises phase and amplitude control blocks. Preferably, the transceiver array groups comprise at least one second transceiver array group configured to operate at mm wavelength.

In accordance with a second aspect of the present invention, there is provided a method for wireless communication, the method comprising the steps of operating two or more transceiver array groups, each transceiver array group comprising one or more radio frequency, RF, circuits, and one or more RF front end, RF FE, circuits and being configured to be connected to one corresponding digital baseband processor, at different frequencies; and operating at least one first transceiver array group of the transceiver array groups at cm wavelength or larger.

Each RF circuit of one transceiver array group is selectively coupled to one or more of the RF FE circuits of the same transceiver array group and vice versa. A first of the transceiver array groups includes a first RF FE circuit which is connected to an RF circuit and which does not have phase and amplitude control blocks, and a second of the transceiver array groups different from the first of the transceiver array groups includes a second RF FE circuit which is connected to an RF circuit and which comprises phase and amplitude control blocks.

In accordance with a third aspect of the present invention, there is provided a method of fabricating the apparatus of the first aspect, the method comprising fabricating both CMOS and III-V semiconductor devices on a single die.

Embodiments of the present invention can provide an RF architecture of highly integrated multiple wireless transceivers enabling carrier aggregation (CA), multiple input and multiple output (MIMO), and beamforming for <NUM> mobile and fixed wireless communication, by leveraging a III-V and Si monolithic integrated process to substantially reduce area and power. The integrated wireless transceivers can include both transmitters and receivers, as well as RF front-end circuits such as low noise amplifiers (LNAs), power amplifiers (PAs), RF switches, and phase shifters interfacing various RF and phased array antennas, which can also be realized together with existing <NUM> communication circuits further increasing the level of integration on a single wafer.

The RF architecture of highly integrated multiple wireless transceivers according to example embodiments can advantageously be realized using a fabrication process that deposits both III-V and CMOS devices and circuits on a single wafer, providing a small form factor and low power consumption for both a base station and a mobile device.

More specifically, example embodiments of the present invention provide a structure of transceivers array groups for both mm-Wave & cm-Wave carrier aggregation/MIMO, that can be integrated on a single die or wafer using existing fabrication processes. As will be described in more detail below with reference to <FIG>, in an example embodiment the CMOS/III-V boundary <NUM> on the single chip radio <NUM> for a corresponding digital baseband processor <NUM> is preferably determined by the operating frequency of the transceivers array groups <NUM>, <NUM>, <NUM> as well as the structure of the transceivers groups <NUM>, <NUM>, <NUM>. In the example embodiment shown in <FIG>, all the RF1 e.g. <NUM> and Front-End1 e.g. <NUM> circuits operating at e.g. <NUM> or under can be designed using CMOS only. The RF2 e.g. <NUM> and Front-End2 e.g. <NUM> circuits operating at e.g. <NUM> with the Type-<NUM> RF transceiver structure described below with reference to <FIG> can be designed using both CMOS and III-V. In the example embodiment shown in <FIG>, all the RF2 e.g. <NUM> circuits can be implemented using CMOS only while all the Front-End2 e.g. <NUM> circuits can be implemented using both III-V and CMOS. The RF3 e.g. <NUM> and Front-End3 e.g. <NUM> circuits operating at <NUM> or higher with the Type-<NUM> RF transceiver structure described below with reference to <FIG> can also be designed using both CMOS and III-V. However, in the example embodiment shown in <FIG> some of the RF3 circuits e.g. <NUM> can be implemented using both III-V and CMOS depending on their high frequency performance and/or circuit topology. All the Front-End3 e.g. <NUM> circuits can also be implemented using both III-V and CMOS. Overall, the III-V portion of the whole chip <NUM> design is located about <NUM>~<NUM> below the surface of the CMOS portion of the design according to an example embodiment, and CMOS and III-V parts are connected together through metal lines transversing the CMOS/III-V boundary <NUM> on a single semiconductor die or wafer.

As mentioned in the background section, for mobile speeds of 20Gbps, <NUM> NR will use CA fully utilizing available frequency slots and bandwidth with an appropriate communication scheme at each carrier frequency. <FIG> shows an example embodiment of a radio <NUM> with multiple RF transceiver array groups <NUM>, <NUM>, <NUM> of one or more transceivers each (i.e. TRX1, TRX2, TRX3) for carrier aggregation (CA) with different wireless transmission techniques operating simultaneously at different frequencies.

Specifically, <FIG> depicts an example embodiment of a radio <NUM> with integrated multiple RF transceiver array groups <NUM>, <NUM>, <NUM> supporting CA using three different carrier frequencies, f<NUM>, f<NUM>, and f<NUM>. In this embodiment, f<NUM> is sub-<NUM>, f2 is unlicensed <NUM>, and f3 is <NUM> assigned for <NUM> mm-Wave. At f1, traditional single radio (TRX1) transmission is used with a bit large sized antenna (ANT1), while MIMO is used with multiple RF transceivers (TRX2) and antennas (ANT2) at f<NUM> to maximize the channel capacity in the unlicensed <NUM> frequency band. At f<NUM>, due to the shorter wavelength of the mm-Wave signals, phased array antennas (ANT3) can be implemented in a smaller area with phase and amplitude control blocks, e.g. <NUM>, <NUM>, respectively, in addition to the RF transceiver (TRX3).

More detailed block diagrams of transceivers TRX1, TRX2, TRX3 of <FIG> are shown in <FIG> depending on their antenna configuration. Each RF channel is depicted as comprising an RF circuit 300a, 301a, and an RF Front-End (RF FE) circuit e.g. 300b, 301b. In each RF channel there are frequency conversion blocks e.g. <NUM>, <NUM> (i.e. up-mixers and down-mixers), amplifiers e.g. <NUM>-<NUM>, filters e.g. <NUM>, <NUM>, switches e.g. <NUM>, <NUM>, digital-to-analog converters e.g. <NUM>, <NUM> and analog-to-digital converters e.g. <NUM>, <NUM>, and a frequency generation block e.g. <NUM>, <NUM> (i.e. PLL), as will be appreciated by a person skilled in the art. In <FIG> an RF channel with a conventional Type-<NUM> RF front-end (FE) 301a is shown. In the case of using phased array antennas or massive MIMO technique, amplitude and phase control <NUM> functionality is added to each Type-<NUM> RF FE circuit e.g. 301b, for analog beamforming, as shown in <FIG>. If a digital beamforming technique is adopted in different embodiments, the amplitude and/or phase control <NUM> functionality can be implemented in a digital baseband processor, using high performance and high power-consuming digital-to-analog converters e.g. <NUM>, <NUM> and analog-to-digital converters e.g. <NUM>, <NUM> in such embodiments.

In embodiments of the present invention, a radio is provided with multiple RF array groups corresponding to a single baseband processor supporting carrier aggregation and including both Type-<NUM> transceivers shown in <FIG> and Type-<NUM> transceivers shown in <FIG>.

<FIG>, as an example embodiment, depicts two RF transceiver array groups <NUM>, <NUM>, where both Type-<NUM> and Type-<NUM> transceivers build a radio <NUM> corresponding to a single digital baseband processor <NUM> that is capable of running carrier aggregation function at two different carrier frequencies. More array groups at different frequency bands can be integrated together in different embodiments, and any number of RF channels (e.g. RF <NUM> circuit <NUM> and Type-<NUM> RF FE circuit <NUM> ) in each RF array group e.g. <NUM> with appropriate antenna configurations can be activated simultaneously and automatically configured through control signals <NUM> from the digital baseband processor <NUM> in which the control signals <NUM> are generated based on the computation about wireless channel conditions and availability. The Type-<NUM> RF transceivers array group <NUM> with ANT2 in the example embodiment shown in <FIG> can also be used for massive MIMO and/or beamforming for a single or multiple users. In the example embodiment shown in <FIG>, one RF2 circuit e.g. <NUM> may be connectable to one or more Type-<NUM> RF FE's circuits e.g. <NUM>, <NUM> and antennas (ANT2) e.g. <NUM>, <NUM>, in which the amplitude and phase control circuitry <NUM> described above with reference to in <FIG> can be integrated with (or embedded in) a power amplifier (PA), a low noise amplifier (LNA), and/or an antenna switch.

In an example embodiment, different carrier frequencies for activated RF channels for a single user are preferably synchronized to transmit and receive multiple data streams e.g. <NUM>, <NUM> from the single baseband processor <NUM> at the same time. Thus, f<NUM> and f<NUM> in <FIG> (or more carrier frequencies) are preferably generated from a single frequency synthesizer or phase-locked loop (PLL) <NUM> with frequency division <NUM> and/or multiplication <NUM> functional blocks, as depicted in <FIG>. In other example embodiments, multiple PLLs <NUM>, <NUM> for different frequency bands can be synchronized using a single reference clock source <NUM> and a phase synchronization block <NUM> shown in <FIG>, in either a transmitter or a receiver, or both. <FIG> show examples for multiple-user cases, specifically in <FIG> a single PLL <NUM> for multiple users, and in <FIG> multiple PLLs <NUM>, <NUM> for multiple users.

In implementing a radio with multiple RF transceiver array groups according to example embodiments of the present invention, designers can face two challenges - form-factor and power consumption - especially in a mobile device.

In some example embodiments, a unique fabrication process is leveraged, the LEES (Low Energy Electronics Systems) process [<NUM>-<NUM>], where both CMOS and III-V semiconductor devices can be fabricated on a single die as shown in <FIG>. This advantageously allows the use of the most suitable III-V devices/circuits [<NUM>] grown below conventional CMOS devices/circuits, interfaced via metal layers. Such single-die integration can advantageously offer the superior performance required by <NUM> specifications at the small form factor and within the tight power budget of a smartphone implementation.

For details of the LEES process, reference is made to [<NUM>-<NUM>] for various example process steps with associated fabrication techniques and conditions as described therein, which can be applied in fabricating a radio with RF transceiver array groups on a single wafer/chip according to example embodiments. One non-limiting example of an LEES fabrication process for fabrication of a radio with RF transceiver array groups according to example embodiments will be described below with reference to <FIG>.

More specifically, <FIG> show schematic cross-sectional views of the monolithically integrated III-V (e.g. GaN high electron mobility transistor (HEMT)) with Si CMOS process used according to an example embodiment: <FIG> shows a silicon-on-insulator (SOI) wafer <NUM> with fabricated Si devices <NUM>. As will be appreciated by a person skilled in the art, the Si devices may be formed by inserting the wafer <NUM> into a front-end CMOS process. Following removal of the partially processed wafer <NUM> with the fabricated Si devices <NUM>, an oxide layer <NUM> is formed on the partially processed wafer <NUM> in this example embodiment. The wafer <NUM> is then flipped and temporarily attached to a handle wafer (not shown), and a Si CMOS/GaN-on-Si wafer <NUM> is realized by two-step bonding technology, as shown in <FIG>. In this example embodiment, the two-step bonding technology involves first attaching the handle wafer to the partially processed wafer <NUM>, for example by wafer bonding at elevated temperatures greater than or equal to <NUM> degrees Celsius. Following removal of the bulk Si <NUM> of the wafer <NUM>, the remaining flipped partially processed wafer <NUM>* is attached to a GaN-on-Si wafer <NUM>, for example by wafer bonding at elevated temperatures equal to or greater than the temperature at which the GaN HEMT devices are subsequently formed, forming the Si CMOS/GaN-on-Si wafer <NUM>.

As shown in <FIG> GaN window(s) <NUM> are then opened to expose the non-silicon device layer(s) <NUM> and device isolation <NUM>, <NUM> are formed by, for example by having a distance between CMOS and III-V regions or by forming a n-well with a DC bias. Non-silicon devices and plugs or vias for making contact are formed in the window(s) <NUM> and the Si CMOS/GaN-on-Si wafer <NUM> is re-inserted into the CMOS process for back end CMOS processing. <FIG> shows a schematic cross-sectional view of the monolithically integrated GaN HEMT devices <NUM> after removal from the CMOS back-end processing with final metal interconnection e.g. <NUM>-<NUM> of fabricated HEMT devices <NUM> and Si CMOS devices <NUM>.

<FIG> depicts another example embodiment of a single chip radio <NUM> including RF transceiver array groups <NUM>, <NUM>, <NUM> with both Type-<NUM> RF transceivers (i.e. RF <NUM> circuits e.g. <NUM> and Type-<NUM> RF FE circuits e.g. <NUM>) and Type-<NUM> RF transceivers (i.e. RF <NUM> circuits e.g. <NUM> and Type-<NUM> RF FE circuits e.g. <NUM>), in which low frequency blocks can be implemented using CMOS process technology while high frequency and high power blocks including PA, LNA, antenna switch, and amplitude/phase control circuitry can be implemented using III-V technology on a single wafer for single chip <NUM> design, by means of the LEES process. Data Stream <NUM>, <NUM>, and <NUM> from the digital baseband processor <NUM> in <FIG> can be independently used for two or more users (i.e. multi-user), for which the generated carrier frequencies, f<NUM>, f<NUM>, and f<NUM>, can also be independent. However, if all the data streams are used for a single user to improve data rates and/or robustness, all the generated carrier frequencies should be synchronized, as described above with reference to <FIG>.

Advantageously, the single chip integrated radio <NUM> according to an example embodiment with RF transceiver array groups <NUM>, <NUM>, <NUM>, fabricated using e.g. the LEES process described above with reference to <FIG>, can support massive MIMO, beamforming, and carrier aggregation with multiple antenna configurations for one or more users.

In the example embodiment shown in <FIG>, multiple transceiver array groups operating in any frequency ranges including millimeter wave (e.g. <NUM> or <NUM> for transceiver array group <NUM>), centimeter wave (e.g. <NUM> or <NUM> for transceiver array group <NUM>), and sub-<NUM> for transceiver array group <NUM>, can advantageously be provided. In one embodiment, one or more simple Type-<NUM> RF transceivers forming one array group operating at low frequency ranges (e.g. sub-<NUM>), e.g. transceiver array groups <NUM> and <NUM>, can be integrated with one or more Type-<NUM> RF transceivers forming another array group operating at millimeter wave frequency ranges, e.g. transceiver array group <NUM>, in a single communication apparatus, preferably in a single chip apparatus.

In the RF transceiver array groups <NUM>, <NUM>, <NUM>, i.e. including those operating in millimeter wave frequency ranges, example embodiments of the present invention can support more flexible configuration between RF circuits and RF front-end circuits (either Type-<NUM> or Type-<NUM>). For example, in the embodiment shown in <FIG>, one RF3 circuit e.g. <NUM> can be selectively connected to multiple Front-End3 circuits e.g. <NUM>, <NUM> for analog beamforming and each RF2 circuit e.g. <NUM> can be selectively connected to one or multiple Front-End2 circuits e.g. <NUM>, <NUM> for digital beamforming or massive MIMO.

<FIG> shows a block diagram illustrating an apparatus <NUM> for wireless communication, according to an example embodiment. The apparatus comprises two or more transceiver array groups <NUM>, <NUM>, each transceiver array group <NUM>, <NUM> comprising one or more radio frequency, RF, circuits, <NUM>, <NUM> and one or more RF front end, RF FE, circuits <NUM>, <NUM> wherein the transceiver array groups <NUM>, <NUM> are configured to operate at different frequencies; wherein the transceiver array groups <NUM>, <NUM> are configured to be connected to one corresponding digital baseband processor <NUM>; and wherein the transceiver array groups <NUM>, <NUM> comprise at least one first transceiver array group <NUM> configured to operate at cm wavelength or larger.

The transceiver array groups <NUM>, <NUM> may comprise at least one second transceiver array group <NUM> configured to operate at mm wavelength.

The transceiver array groups <NUM>, <NUM> may be configured to enable selective coupling of each RF circuit e.g. <NUM> of one transceiver array group <NUM> to one or more of the RF FE circuits e.g. <NUM> of the same transceiver array group <NUM>.

One or more of the RF FE circuits e.g. <NUM> may comprise phase and amplitude control blocks.

One or more of the transceiver array groups <NUM>, <NUM> may be configured to support multiple-input-multiple-output, MIMO, or massive MIMO.

One or more of the transceiver array groups <NUM>, <NUM> may be configured to support analogue beamforming, digital beamforming, or hybrid analogue/digital beamforming.

One or more of the transceiver array groups <NUM>, <NUM> may be configured to support carrier aggregation.

The transceiver array groups <NUM>, <NUM> may be implemented on a single chip. The single chip may comprise both complementary metal-oxide-semiconductor, CMOS, and III-V semiconductor devices.

The apparatus <NUM> may further comprising the corresponding digital baseband processor <NUM>.

<FIG> shows a flow-chart <NUM> illustrating a method for wireless communication, according to an example embodiment. At step <NUM>, two or more transceiver array groups, each transceiver array group comprising one or more radio frequency, RF, circuits, and one or more RF front end, RF FE, circuits and being configured to be connected to one corresponding digital baseband processor, are operated at different frequencies. At step <NUM>, at least one first transceiver array group of the transceiver array groups is operated at cm wavelength or larger.

The method may comprise operating at least one second transceiver array group of the transceiver array groups at mm wavelength.

The method may comprise selectively coupling each RF circuit of one transceiver array group to one or more of the RF FE circuits of the same transceiver array group.

The method may comprise phase and amplitude control in one or more of the RF FE circuits.

The method may comprise supporting multiple-input-multiple-output, MIMO, or massive MIMO using the one or more of the transceiver array groups.

The method may comprise supporting analogue beamforming, digital beamforming, or hybrid analogue/digital beamforming using one or more of the transceiver array groups.

The method may comprise performing carrier aggregation using one or more of the transceiver array groups.

The method may comprise implementing the transceiver array on a single chip. The single chip may comprise both complementary metal-oxide-semiconductor, CMOS, and III-V semiconductor devices.

In one embodiment, a method of fabricating the apparatus described above with reference to <FIG> is provided, the method comprising fabricating both CMOS and III-V semiconductor devices on a single die.

The method may comprise using low energy electronics systems, LEES, processing.

Industrial applications of example embodiments include:.

In some example embodiments, an area- & power-efficient single chip integration of those multiple RF transceiver array groups using the LEES CMOS+III-V semiconductor process is advantageously provided. High level of integration of multiple RF channels and RF front-ends on a single wafer according to example embodiments of the present invention can advantageously provide more flexible configurations, as described herein.

The various functions or processes disclosed herein may be described as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and/or instructions through wireless, optical, or wired signaling media or any combination thereof. Examples of transfers of such formatted data and/or instructions by carrier waves include, but are not limited to, transfers (uploads, downloads, e-mail, etc.) over the internet and/or other computer networks via one or more data transfer protocols (e.g., HTTP, FTP, SMTP, etc.). When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of components and/or processes under the system described may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs.

Aspects of the systems and methods described herein may be implemented as functionality programmed into any of a variety of circuitry, including programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), programmable array logic (PAL) devices, electrically programmable logic and memory devices and standard cell-based devices, as well as application specific integrated circuits (ASICs). Some other possibilities for implementing aspects of the system include: microcontrollers with memory (such as electronically erasable programmable read only memory (EEPROM)), embedded microprocessors, firmware, software, etc. Furthermore, aspects of the system may be embodied in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types. Of course the underlying device technologies may be provided in a variety of component types, e.g., metal-oxide semiconductor field-effect transistor (MOSFET) technologies like complementary metal-oxide semiconductor (CMOS), bipolar technologies like emitter-coupled logic (ECL), polymer technologies (e.g., silicon-conjugated polymer and metal-conjugated polymer-metal structures), mixed analog and digital, etc..

The above description of illustrated embodiments of the systems and methods is not intended to be exhaustive or to limit the systems and methods to the precise forms disclosed.

The teachings of the systems and methods provided herein can be applied to other processing systems and methods, not only for the systems and methods described above.

The elements and acts of the various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the systems and methods in light of the above detailed description.

In general, in the following claims, the terms used should not be construed to limit the systems and methods to the specific embodiments disclosed in the specification and the claims, but should be construed to include all processing systems that operate under the claims. Accordingly, the systems and methods are not limited by the disclosure, but instead the scope of the systems and methods is to be determined entirely by the claims.

Claim 1:
An apparatus (<NUM>) for wireless communication, comprising:
two or more transceiver array groups (<NUM>, <NUM>), each transceiver array group (<NUM>, <NUM>) comprising one or more radio frequency, RF, circuits (300a, 301a, <NUM>, <NUM>), and one or more RF front end, RF FE, circuits (300b, 301b, <NUM>, <NUM>);
wherein the transceiver array groups (<NUM>, <NUM>) are configured to operate at different frequencies;
wherein the transceiver array groups (<NUM>, <NUM>) are configured to be connected to one corresponding digital baseband processor;
wherein the transceiver array groups (<NUM>, <NUM>) comprise at least one first transceiver array group configured to operate at cm wavelength or larger;
characterized in that
the transceiver array groups (<NUM>, <NUM>) are configured to enable selective coupling of each RF circuit (300a, 301a, <NUM>, <NUM>) of one transceiver array group to one or more of the RF FE circuits (300b, 301b, <NUM>, <NUM>) of the same transceiver array group and vice versa, and
wherein a first of the transceiver array groups includes a first RF FE circuit (301a) which is connected to an RF circuit and which does not have phase and amplitude control blocks (<NUM>), and a second of the transceiver array groups different from the first of the transceiver array groups includes a second RF FE circuit (301b) which is connected to an RF circuit and which comprises phase and amplitude control blocks (<NUM>).