Patent Description:
In recent years, a programmable device such as a field programmable gate array (FPGA) and a dynamically reconfigurable processor (DRP) has been used.

For example, PTL <NUM> discloses a programmable device. The programmable device disclosed in PTL <NUM> generates a configuration code for achieving a plurality of circuits having different features, and stores the configuration code in a memory, for each task to be executed. When the programmable device operates, a circuit appropriate for causing the programmable device to execute according to an operation state of a system is selected from among the plurality of circuits having different features, and a configuration code associated with the selected circuit is loaded from the memory to the programmable device. The programmable device starts processing with respect to input data by the selected circuit at a stage when loading of the configuration code is completed. <CIT> discloses a processor having an internal raster of execution units. <CIT> relates to a parallel arithmetic device including a plurality of data wirings disposed in a first direction and a second direction. <CIT> discloses an integrated circuit (IC) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity.

The programmable device is configured in such a way that logical blocks are regularly disposed and wired by a mesh data path as illustrated in <FIG>. Such a layout becomes a constraint when a universal layout and wiring of logical blocks are performed. Such a layout of logical blocks needs a large number of wirings for transmitting a signal, and a large area for a switch region, as compared with an arithmetic element. This also becomes a constraint in terms of improving a degree of integration. PTL <NUM> fails to disclose a configuration for solving such an issue.

An object of the present invention is to provide a processor element and a programmable device that enable improving a degree of integration with less constraints on a layout and wiring of logical blocks.

Dependent claims describe preferred embodiments.

In one aspect of the invention, a processor element comprises: an arithmetic unit that performs arithmetic processing based on a function in which an instruction set generated according to a program is implemented; a register that stores an argument of the function; a first bypass switch that switches whether to bypass the arithmetic unit; a second bypass switch that switches whether to bypass the register; a connection setting unit that switches connection of a function unit being a pair of the register and the arithmetic unit; a multiplexer that switches an input to the connection setting unit; a demultiplexer that switches an output destination of an output from the connection setting unit; and a selection unit that performs, according to a state, switching of the first bypass switch, the second bypass switch, the connection setting unit, a multiplexer, and a demultiplexer.

In one aspect of the invention, a plurality of the processor elements in a programmable device are disposed adjacent to one another, wherein processor elements that are not adjacent to one another are not directly connected, and processor elements adjacent to one another are connected to one another.

In one aspect of the invention, a control method of a processor element, comprises: performing arithmetic processing based on a function in which an instruction set generated according to a program is implemented; performing storing processing of an argument of the function; and performing, according to a state, switching whether to bypass the arithmetic processing, switching whether to bypass the storing processing, switching a sequence of function processing being a pair of the arithmetic processing and the storing processing, and switching an input to the function processing and an output destination of the function processing.

The present invention enables improving a degree of integration with less constraints on a layout and wiring of logical blocks in a processor element and a programmable device.

In the following, a first example embodiment according to the present invention is described. First, a background of the present invention is described.

There are two issues to be solved in a micro-controller unit (MCU) including a computer architecture of a stored program method on the basis of finite automaton. One of the issues is how to eliminate overhead that a finite state machine inherent to an application stored in an external memory element is simulated by a finite state machine within a finite state control unit (specifically, within an arithmetic unit of the MCU). The other is how to utilize a high-level synthesis technique and an operation synthesis technique with respect to definition of an arithmetic unit.

It is necessary to provide measures against these issues, and propose a processor element incorporated with advantages of an MCU, an FPGA, and a DRP being programmable devices. While it is possible to mount the processor element as a design plan, by incorporating the processor element in a development tool, it becomes possible to utilize the method, as a general-purpose designing method for designing a processor element in which a processor is embedded in a sensing device.

In order to achieve the above, it is necessary to define a basic architecture of a processor element, and make it possible to designate a content of the definition in a high-level programming language.

In formulating an architecture of a processor element, it has been aimed at maintaining a programming environment in which an entirety of the architecture can be designed by a function language such as C language. When debugging of a source code is performed, it is necessary that a debugging tool can execute a program along a context extracted from an application program. Specifically, it is necessary that a context of a series of operations written in a function language can be traced.

It is assumed that an architecture of a processor element according to the present example embodiment is configured in such a way that a context of a high-level programming language can be expressed based on semantics and lambda calculation, and two types of contexts can be expressed. One of the contexts is a replaceable static context, which is frequently referred to as information stored in a file, and the other is a dynamic context to be expressed as information stored in a heap register. It is assumed that these contexts can be expressed as function description.

A dynamic context of an application program is expressed by functions as follows.

In the static context, an argument is implemented as a register, and a function body is implemented as an arithmetic unit including an instruction set generated according to the application program. A function unit being a pair of a register and an arithmetic unit is defined in the static context along a request of the application program. A bypass switch for switching whether to bypass the register and the arithmetic unit is defined. The static context is defined by grouping a required register, arithmetic unit, and bypass switch according to a state.

It is assumed that connection of a group can be described by functions as follows.

Next, a configuration according to a first example embodiment is described. <FIG> is a block diagram illustrating a configuration of a processor element according to the present example embodiment.

An instruction set is generated based on a request of an application program, and n arithmetic units 11a, 11b, and 11n (where n is an integer of <NUM> or larger) are implemented. Specifically, arithmetic units 11a, 11b, and 11n perform arithmetic processing on the basis of a function in which an instruction set generated according to an application program is implemented.

Registers 12a, 12b, and 12n are provided in processor element <NUM> in association with arguments of instruction sets to be implemented in associated arithmetic units 11a, 11b, and 11n. Specifically, registers 12a, 12b, and 12n respectively store arguments to be used in functions of arithmetic units 11a, 11b, and 11n.

In the following, pairs of arithmetic units 11a, 11b, 11c, and registers 12a, 12b, 12n associated with the arithmetic units are referred to as function units 20a, 20b, 20n.

In the following description, when it is not necessary to describe by designating a specific arithmetic unit, an arithmetic unit is referred to as arithmetic unit <NUM>. Likewise, when it not necessary to describe by designating a specific register, a register is referred to as register <NUM>, and when it is not necessary to describe by designating a specific function unit, a function unit is referred to as function unit <NUM>.

In processor element <NUM> according to the present example embodiment, a static context of an application is expressed as a context in which selected function units <NUM> are connected. The static context is defined by grouping required register <NUM> and arithmetic unit <NUM> according to a state. Processor element <NUM> includes selection unit <NUM> for selecting required function unit <NUM> from among function units 20a, 20b, 20n according to each static context in order to associate each static context with each state within processor element <NUM>. Selection unit <NUM> also designates a connection sequence of the selected function unit. Selection unit <NUM> is achieved by a finite state machine (FSM) generated according to an application by high-level synthesis, for example.

Processor element <NUM> includes connection setting unit <NUM> for setting connection of function unit <NUM>, based on an instruction of selection unit <NUM>. Processor element <NUM> includes bypass switches 13a, 13b, and 13n for respectively switching whether to bypass arithmetic units 11a, 11b, and 11n, based on an instruction of selection unit <NUM>, and bypass switches 14a, 14b, and 14n for respectively switching and selecting whether to bypass registers 12a, 12b, and 12n, based on an instruction of selection unit <NUM>. In the following description, when it is not necessary to describe by designating a specific bypass switch among bypass switches for respectively switching whether to bypass arithmetic units 11a, 11b, and 11n, bypass switches 13a, 13b, and 13n are referred to as bypass switches <NUM>. Likewise, when it is not necessary to describe by designating a specific bypass switch among bypass switches for respectively switching whether to bypass registers 12a, 12b, and 12n, bypass switches 14a, 14b, and 14n are referred to as bypass switches <NUM>.

Processor element <NUM> includes multiplexer <NUM> for switching an input to connection setting unit <NUM>, and demultiplexer <NUM> for switching an output destination of an output from connection setting unit <NUM>.

Selection unit <NUM> outputs, to bypass switch <NUM>, bypass switch <NUM>, connection setting unit <NUM>, multiplexer <NUM>, and demultiplexer <NUM>, a selection signal for instructing switching according to a state within processor element <NUM>. Thus, selection of a function unit associated with each state and selection of a processing sequence of the function unit are performed, and selection unit <NUM> performs selection of a function associated with each state by bypassing a function unit that is not required, and switching a connection sequence of function unit <NUM>. Selection unit <NUM> switches an input to a function unit associated with each state, and an output destination.

The selection signal includes a static context selection signal being a selection signal for a static context, and a dynamic context selection signal being a selection signal for a dynamic context.

In this way, in the present example embodiment, selection unit <NUM> being a finite state machine (FSM) associates a static context with each state within processor element <NUM>, and switches setting of bypass switch <NUM>, bypass switch <NUM>, and connection setting unit <NUM> within function unit <NUM>, as the state proceeds.

Processor element <NUM> is connected to four processor elements <NUM> respectively adjacent to four sides of processor element <NUM>. Signals output from four adjacent processor elements <NUM> are input to multiplexer <NUM>. Multiplexer <NUM> selects one of inputs from a plurality of adjacent processor elements <NUM> according to a selection signal to be output from selection unit <NUM>, and inputs an output of selected processor element <NUM> to connection setting unit <NUM>.

Connection setting unit <NUM> outputs, to an arithmetic unit of a function unit which performs first processing, a signal from multiplexer <NUM>, based on a selection signal from selection unit <NUM>. The output of the arithmetic unit is output to a register of the same function unit. When bypassing the arithmetic unit by a bypass switch is instructed by a selection signal from selection unit <NUM>, a signal input to the arithmetic unit bypasses the arithmetic unit and is output to the register.

The output of register <NUM> is output to connection setting unit <NUM>. When bypassing the register by a bypass switch is instructed by a selection signal from selection unit <NUM>, a signal input to the register bypasses the register and is output to connection setting unit <NUM>.

Connection setting unit <NUM> outputs, to an arithmetic unit of a function unit which performs next processing, an output of a function unit which performs first processing, based on an instruction of selection unit <NUM>. When the output is an output from register <NUM> of a function unit which performs last processing, connection setting unit <NUM> outputs, to demultiplexer <NUM>, a signal from register <NUM>, based on an instruction of selection unit <NUM>.

Demultiplexer <NUM> outputs an output from a connection setting unit being an output from a function unit which performs last processing by selecting one of a plurality of adjacent processor elements <NUM> according to a selection signal to be output from selection unit <NUM>.

This operation is similar to context switching in a DRP. Specifically, this is equivalent to generating an optimum DRP according to an application each time in a processor element according to the present example embodiment.

In the above-described MCU including a computer architecture of a stored program method on the basis of finite automaton, an FSM inherent to an application is implemented on a memory element, which is mounted on an outside of a processor element. In this point, the present example embodiment is different from the above-described MCU. In the above-described MCU, since an FSM according to an application is simulated by reading and writing with respect to a memory by an addressing function of an external memory element, overhead is additionally required by an amount corresponding to the simulation. In processor element <NUM> according to the present example embodiment, since an FSM according to an application directly operates on a hardware of processor element <NUM>, electric power consumption is improved, as compared with the above-described MCU.

Each constituent element of a moving target search system according to the first example embodiment illustrated in <FIG> and the other example embodiments to be described later indicates a block of a functional unit. A part or all of each constituent element of a moving target search system according to each example embodiment may be achieved by any combination of computer <NUM> as illustrated in <FIG>, and a program, for example. Computer <NUM> includes, as one example, the following components.

Each constituent element of each example embodiment is achieved by causing CPU <NUM> to acquire and execute program <NUM> for achieving these functions. For example, in the example of processor element <NUM> in <FIG>, arithmetic unit <NUM> may achieve a function by causing CPU <NUM> that has acquired program <NUM> to execute arithmetic processing on the basis of a function, based on program <NUM>. Register <NUM> may achieve a function by causing CPU <NUM> that has acquired program <NUM> to execute storing processing of storing an argument of the above-described function on storage device <NUM>. Bypass switches <NUM> and <NUM> may achieve a function by causing CPU <NUM> that has acquired program <NUM> to bypass the above-described arithmetic processing and the above-described storing processing, based on program <NUM>. Connection setting unit <NUM> may achieve a function by causing CPU <NUM> that has acquired program <NUM> to switch a sequence of arithmetic processing and storing processing for achieving a function, based on program <NUM>. Selection unit <NUM> may achieve a function by causing CPU <NUM> that has acquired program <NUM> to perform switching whether to bypass the above-described arithmetic processing, switching whether to bypass the above-described storing processing, and switching a sequence of arithmetic processing and storing processing, based on program <NUM>. Multiplexer <NUM> may achieve a function by causing CPU <NUM> that has acquired program <NUM> to select and input an output of either of the adjacent processor elements, based on program <NUM>. Demultiplexer <NUM> may achieve a function by causing CPU <NUM> that has acquired program <NUM> to select, as an output destination, either of the adjacent processor elements, based on program <NUM>.

Program <NUM> for achieving a function of each constituent element of each example embodiment may be stored in advance, for example, in storage device <NUM>, ROM <NUM>, or RAM <NUM>, and configured in such a way that CPU <NUM> reads program <NUM> as necessary.

Program <NUM> may be supplied to CPU <NUM> via communication network <NUM>, or may be stored in advance in recording medium <NUM>, and supplied to CPU <NUM> by causing driver device <NUM> to read the program.

Next, a layout of a processor element and wiring among processor elements on a programmable device according to the present example embodiment are described. As illustrated in <FIG>, in the above-described general MCU, FPGA, and DRP, there are constraints such that logical blocks are regularly disposed and wired on the above-described MCU and FPGA by a mesh data path. Such a layout and wiring become constraints, when a high-level synthesizing tool performs a universal layout and wiring.

<FIG> is a diagram illustrating details of <FIG>. As illustrated in <FIG>, the above-described MCU and FPGA are configured of a logical block, a wiring connection switch, an input-output switch, and a wire track. The logical block is configured of a look-up table (LUT) being a variable logic, and a flip-flop being a sequence circuit, the wiring connection switch switches vertical and horizontal wiring connections, the input-output switch is used for connection between a logical block and wiring, and the wire track is used for wiring between wiring connection switches.

On the other hand, in the present example embodiment, it is assumed that a data path as illustrated in <FIG> is not fixedly disposed among processor elements, and connection among processor elements is among adjacent processor elements. On a programmable device according to the present example embodiment, a logical block expressed as a function is universally connectable. Processor element <NUM> according to the present example embodiment avoids constraints with respect to a high-level synthesizing tool by also enabling to define a function merely of a bypass. In processor element <NUM> according to the present example embodiment, a general-purpose arithmetic unit is not prepared in advance. By determining with use of a high-level synthesizing tool in mounting, in processor element <NUM> according to the present example embodiment in which a bit width of an arithmetic unit is also arbitrarily settable, the above configuration enables enhancing mounting efficiency.

<FIG> is a block diagram illustrating one example of a configuration of a connecting portion to an adjacent processor in a processor element according to the present example embodiment. As illustrated in <FIG>, processor element <NUM> includes four terminals <NUM> for connecting to four adjacent processor elements <NUM>. Each of four terminals <NUM> is connected to either of input terminals of multiplexer <NUM>, and is connected to either of output terminals of demultiplexer <NUM>. Signals output from four adjacent processor elements <NUM> are input to multiplexer <NUM> via four terminals <NUM>. A signal output from demultiplexer <NUM> is output to associated processor element <NUM> via either of four terminals <NUM>.

<FIG> is a diagram illustrating an overview of a connection switching function of a processor element according to the present example embodiment. As illustrated in <FIG>, processor element <NUM> according to the present embodiment is able to select which one of processor elements other than an adjacent processor element selected as an input is an output of processor element <NUM> by switching an output of demultiplexer <NUM>. Although not illustrated in <FIG>, processor element <NUM> according to the present example embodiment is able to select which one of outputs of adjacent processor elements is an input of processor element <NUM> by switching multiplexer <NUM> in <FIG>. Processor element <NUM> according to the present example embodiment is able to select whether to bypass arithmetic units 11a, 11b, and 11n, and registers 12a, 12b, and 12n by switching bypass switches 13a, 13b, and 13n, and 14a, 14b, and 14n within processor element <NUM>.

These configurations do not necessitate a layout wiring switch (switch block), an input-output switch (connection block), and a wire track, which are used in a general FPGA and the like, and enable covering the entire surface of a chip of a programmable device with an arithmetic resource.

<FIG> is a diagram illustrating an example of a configuration of a programmable device configured by connecting a processor elements. As illustrated in <FIG>, in programmable device <NUM>, a plurality of processor elements are disposed adjacent to one another. On programmable device <NUM>, processor elements that are not adjacent to one another are not directly connected, and processor elements adjacent to one another are connected to one another. Also in such a layout, as described above, as illustrated in <FIG>, processor element <NUM> according to the present example embodiment is able to select which one of processor elements other than an adjacent processor element selected as an input is an output of processor element <NUM> by switching an output of demultiplexer <NUM>. By switching bypass switches 13a, 13b, and 13n, and 14a, 14b, and 14n within processor element <NUM>, processor element <NUM> is able to select whether to bypass arithmetic units 11a, 11b, and 11n, and registers 12a, 12b, and 12n. By such a configuration, it is possible to configure programmable device <NUM> by universally connecting a plurality of logical blocks configured of function unit <NUM>, selection unit <NUM>, and connection setting unit <NUM> of processor element <NUM> to a logical block away from the logical blocks on a processor element. <FIG> is a diagram illustrating an example of a configuration of programmable device <NUM> configured by connecting programmable devices <NUM> in <FIG>. As illustrated in <FIG>, connection among programmable devices <NUM> in <FIG> may be only among adjacent programmable devices.

<FIG> is a block diagram illustrating one example of a configuration of a connection setting unit according to the present example embodiment. As illustrated in <FIG>, connection setting unit <NUM> includes multiplexers 161a, 161b, and 161c for selecting a signal to be input to arithmetic units 11a, 11b, and 11c, and demultiplexers 162a, 162b, and 162c for selecting an output destination of a signal from registers 12a, 12b, and 12c. Connection setting unit <NUM> includes demultiplexer <NUM> for selecting a signal input to connection setting unit <NUM>, and multiplexer <NUM> for selecting an output destination of a signal to be output from connection setting unit <NUM>. A selection signal to be output from selection unit <NUM> is input to these elements.

Multiplexers 161a, 161b, and 161c connected to arithmetic units 11a, 11b, and 11c are connected to an output of demultiplexer <NUM>. Demultiplexer <NUM> selects either of multiplexers 161a, 161b, and 161c, based on a selection signal from selection unit <NUM>, and outputs a signal input to connection setting unit <NUM>.

A demultiplexer to be connected to a register of a function unit other than a function unit of a connected arithmetic unit, and demultiplexer <NUM> are connected to an input to multiplexers 161a, 161b, and 161c. Multiplexers 161a, 161b, and 161c select, from among signals from the demultiplexer to be connected to the register of the other function unit, and demultiplexer <NUM>, a signal to be input to the connected arithmetic unit, based on a selection signal from selection unit <NUM>.

A multiplexer connected to an arithmetic unit of a function unit other than a function unit of a connected register, and multiplexer <NUM> are connected to an output from demultiplexers 162a, 162b, and 162c. Demultiplexers 162a, 162b, and 162c select either of the multiplexer connected to the arithmetic unit of the other function unit, and multiplexer <NUM>, based on a selection signal from selection unit <NUM>, and outputs a signal from the connected register.

Demultiplexers 162a, 162b, and 162c connected to registers 12a, 12b, and 12c are connected to an input of multiplexer <NUM>. Multiplexer <NUM> selects a signal input from either of demultiplexers 162a, 162b, and 162c, based on a selection signal from selection unit <NUM>, and outputs the selected signal from connection setting unit <NUM>.

For example, when static context 10a illustrated in <FIG> is achieved, demultiplexer <NUM> selects multiplexer 161a as an output destination of a signal input to connection setting unit <NUM>, based on a selection signal from selection unit <NUM>, and multiplexer 161a selects a signal from demultiplexer <NUM>, based on a selection signal from selection unit <NUM>. Demultiplexer 162a selects multiplexer <NUM> as an output destination of a signal from connected register 12a, based on a selection signal from selection unit <NUM>, and multiplexer <NUM> selects a signal from demultiplexer 162a, based on a selection signal from selection unit <NUM>, and outputs the selected signal from connection setting unit <NUM>.

For example, when static context 10b illustrated in <FIG> is achieved, demultiplexer <NUM> selects multiplexer 161b as an output destination of a signal input to connection setting unit <NUM>, based on a selection signal from selection unit <NUM>, and multiplexer 161b selects a signal from demultiplexer <NUM>, based on a selection signal from selection unit <NUM>. Demultiplexer 162b selects multiplexer 161c as an output destination of a signal from connected register 12b, based on a selection signal from selection unit <NUM>, and multiplexer 161c selects a signal from demultiplexer 162b as a signal to be input to arithmetic unit 11c to be connected, based on a selection signal from selection unit <NUM>. Demultiplexer 162c selects multiplexer <NUM> as an output destination of a signal from connected register 12c, based on a selection signal from selection unit <NUM>, and multiplexer <NUM> selects a signal from demultiplexer 162c, based on a selection signal from selection unit <NUM>, and outputs the selected signal from connection setting unit <NUM>.

For example, when static context 10c illustrated in <FIG> is achieved, demultiplexer <NUM> selects multiplexer 161a as an output destination of a signal input to connection setting unit <NUM>, based on a selection signal from selection unit <NUM>. Multiplexer 161a selects a signal from demultiplexer <NUM> as a signal to be input to arithmetic unit 11a to be connected, based on a selection signal from selection unit <NUM>. Demultiplexer 162a selects multiplexer 161b as an output destination of a signal from connected register 12a, based on a selection signal from selection unit <NUM>. Multiplexer 161b selects a signal from demultiplexer 162a as a signal to be input to arithmetic unit 11b to be connected, based on a selection signal from selection unit <NUM>. Demultiplexer 162b selects multiplexer <NUM> as an output destination of a signal from connected register 12b, based on a selection signal from selection unit <NUM>. Multiplexer <NUM> selects a signal from demultiplexer 162b, based on a selection signal from selection unit <NUM>, and outputs the selected signal from connection setting unit <NUM>.

In this way, according to the present example embodiment, it becomes possible to output a signal input to connection setting unit <NUM> to an arithmetic unit of at least one function unit, based on a selection signal from selection unit <NUM>, connect a required function unit in any sequence, and output, from connection setting unit <NUM>, an output from a register of a last function unit. Arithmetic units 11a, 11b, and 11c are sharable among static contexts.

As described above, a configuration according to the present example embodiment enables improving a degree of integration with less constraints on a layout and wiring of a logical block in a programmable device.

Next, a second example embodiment is described. The present example embodiment is an example embodiment, when the present invention is applied to an FPGA. <FIG> is a block diagram illustrating a configuration of a processor element according to the second example embodiment. As illustrated in <FIG>, processor element <NUM> according to the present example embodiment includes look-up table (LUT) <NUM>. Arithmetic unit <NUM>, register <NUM>, bypass switches <NUM> and <NUM>, and connection setting unit <NUM> similarly to those in the first example embodiment are implemented in LUT <NUM>. Processor element <NUM> includes multiplexer <NUM> and demultiplexer <NUM> to be connected to adjacent processor element <NUM>, similarly to the first example embodiment.

Processor element <NUM> according to the present example embodiment includes line <NUM> for bypassing LUT <NUM>, and multiplexer <NUM> for selecting line <NUM> and an output of LUT <NUM>. Processor element <NUM> includes flip-flop <NUM> to which a clock and an output of multiplexer <NUM> are input, and line <NUM> for bypassing flip-flop <NUM>, and includes multiplexer <NUM> for selecting line <NUM> and an output of flip-flop <NUM>. LUT <NUM> includes selection unit <NUM> for performing selection of multiplexers <NUM>, <NUM>, and <NUM>, demultiplexer <NUM>, arithmetic units of function units 20a, 20b, 20n and bypass switches of registers, and connection setting unit <NUM>.

A configuration according to the present example embodiment provides an advantageous effect similar to that in the first example embodiment in a processor element being an FPGA.

Next, a third example embodiment is described. <FIG> is a diagram illustrating a configuration of a processor element according to the third example embodiment. As illustrated in <FIG>, processor element <NUM> according to the present example embodiment further includes ALU <NUM> to be generated by high-level synthesis, and register <NUM>, in addition to a configuration according to the second example embodiment. ALU <NUM> is configured in such a way that an output of multiplexer <NUM> is branched and input, and an output of ALU <NUM> is connected to multiplexer <NUM>. An output of LUT <NUM>, line <NUM> for bypassing LUT <NUM>, and an output of ALU <NUM> are connected to multiplexer <NUM>. Multiplexer <NUM> selects either of these outputs, based on an instruction from selection unit <NUM> of LUT <NUM>, and outputs the selected output to flip-flop <NUM> and multiplexer <NUM>.

A configuration according to the present example embodiment provides an advantageous effect similar to that in the first example embodiment in a processor element in which an FPGA and an ALU are mounted in combination.

Next, a fourth example embodiment is described. <FIG> is a diagram illustrating a configuration of a processor element according to the fourth example embodiment. As illustrated in <FIG>, processor element <NUM> according to the present example embodiment further includes PE matrix <NUM> of a DRP and configuration memory <NUM>, in addition to a configuration according to the second example embodiment. PE matrix <NUM> is configured in such a way that an output of multiplexer <NUM> is branched and input, and an output of PE matrix <NUM> is connected to multiplexer <NUM>. An output of LUT <NUM>, line <NUM> for bypassing LUT <NUM>, and an output of PE matrix <NUM> are connected to multiplexer <NUM>. Multiplexer <NUM> selects either of these outputs, based on an instruction from selection unit <NUM> of LUT <NUM>, and outputs the selected output to flip-flop <NUM> and multiplexer <NUM>.

A configuration according to the present example embodiment provides an advantageous effect similar to that in the first example embodiment in a processor element in which an FPGA and a DRP are mounted in combination.

Next, a fifth example embodiment is described. <FIG> is a diagram illustrating a configuration of a processor element according to the fifth example embodiment. As illustrated in <FIG>, processor element <NUM> according to the present example embodiment further includes streaming microprocessor <NUM> of a GPGPU and execution queue <NUM>, in addition to a configuration according to the second example embodiment. Streaming microprocessor <NUM> is configured in such a way that an output of multiplexer <NUM> is branched and input, and an output of streaming microprocessor <NUM> is connected to multiplexer <NUM>. An output of LUT <NUM>, line <NUM> for bypassing LUT <NUM>, and an output of streaming microprocessor <NUM> are connected to multiplexer <NUM>. Multiplexer <NUM> selects either of these outputs, based on an instruction from selection unit <NUM> of LUT <NUM>, and outputs the selected output to flip-flop <NUM> and multiplexer <NUM>.

A configuration according to the present example embodiment provides an advantageous effect similar to that in the first example embodiment in a processor element in which an FPGA and a GPGPU are mounted in combination.

Claim 1:
A processor element (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprising:
an arithmetic unit (<NUM>, 11a, 11b, 11c, 11n) that performs arithmetic processing based on a function in which an instruction set is implemented, the instruction set being generated according to a program;
a register (<NUM>, 12a, 12b, 12c, 12n) that stores an argument of the function;
a first bypass switch (<NUM>, 13a, 13b, 13n) that switches whether to bypass the arithmetic unit (<NUM>, 11a, 11b, 11c, 11n);
a second bypass switch (<NUM>, 14a, 14b, 14n) that switches whether to bypass the register (<NUM>, 12a, 12b, 12c, 12n);
a plurality of function units (<NUM>, 20a, 20b, 20n);
a connection setting unit (<NUM>) for switching connection of one of the plurality of function units (<NUM>, 20a, 20b, 20n) comprising the register (<NUM>, 12a, 12b, 12c, 12n), the arithmetic unit (<NUM>, 11a, 11b, 11c, 11n), the first bypass switch (<NUM>, 13a, 13b, 13n) and the second bypass switch (<NUM>, 14a, 14b, 14n);
a multiplexer that switches an input to the connection setting unit (<NUM>);
a demultiplexer that switches an output destination of an output from the connection setting unit (<NUM>); and
a selection unit (<NUM>) for performing, according to a state, switching of the first bypass switch (<NUM>, 13a, 13b, 13n), the second bypass switch (<NUM>, 14a, 14b, 14n), the connection setting unit (<NUM>), a multiplexer, and a demultiplexer, thereby selecting a required function unit associated with the state from among the plurality of function units (<NUM>, 20a, 20b, 20n) and selecting a processing sequence of the required function unit, wherein
in a case where the first bypass switch (<NUM>, 13a, 13b, 13n) is instructed to bypass the arithmetic unit (<NUM>, 11a, 11b, 11c, 11n), input to the arithmetic unit (<NUM>, 11a, 11b, 11c, 11n) is input to the register (<NUM>, 12a, 12b, 12c, 12n), and
in a case where the second bypass switch (<NUM>, 14a, 14b, 14n) is instructed to bypass the register (<NUM>, 12a, 12b, 12c, 12n), output of the arithmetic unit (<NUM>, 11a, 11b, 11c, 11n) is input to the connection setting unit (<NUM>).