Patent Description:
Magneto-resistive random access memory (MRAM) is a non-volatile random access memory technology in which data is stored by magnetic storage elements. These magnetic storage elements are typically formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin dielectric layer, i.e., the tunnel barrier. One of the two plates is a permanent magnetic set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. Such configuration is known as a magnetic tunnel junction (MTJ) pillar.

For high performance MRAM devices based on perpendicular MTJ pillars, well-defined interfaces and interface control are essential. Embedded MTJ pillar structures are usually formed by patterning of blanket MTJ stacks. Reactive ion etch (RIE), and ion beam etch (IBE) processing of such MTJ stacks presents a major challenge, as it typically leads to electrical shorts due to re-sputtering of underlying thick bottom metal layers onto MTJ stack sidewalls. <CIT> describes a semiconductor structure and fabrication method for forming a semiconductor structure. The structure is a MRAM element having a first conductive electrode embedded in a first interconnect dielectric material layer upon which a multi-layered magnetic tunnel junction (MTJ) memory element is formed in a magnetoresistive random access memory (MRAM) device area. The first conductive electrode includes a first end having a top surface of a first surface area and a second end having a bottom surface of a second surface area, the first surface area being smaller than the second surface area. The second end of the bottom electrode includes a barrier liner material including a metal fill material, and the first end of the bottom electrode is a pillar structure formed as a result of an etchback process in which the metal barrier liner is recessed relative to the metal fill material. <CIT> describes a system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. <CIT> describes a magnetic tunnel junction (MTJ) structure having faceted sidewalls, which is formed on a conductive landing pad that is present on a surface of an electrically conductive structure embedded in a dielectric material layer. No metal ions are re-sputtered onto the sidewalls of the MTJ structure during the patterning of the MTJ material stack that provides the MTJ structure. The absence of re-sputtered metal on the MTJ structure sidewalls reduces the risk of shorts. International Patent publication number <CIT>) discloses a memory cell in which a bottom electrode of a magnetoresistive random access memory (MRAM) device is connected to one of the source/drain contact structure of a transistor, and a lower contact structure is connected to another of the source/drain contact structures of the transistor. In the present application, the MRAM device and the lower contact structure are present in the middle-of-the-line (MOL) not the back-end-of-the-line (BEOL). Moreover, the bottom electrode of the MRAM device, and a lower portion of the lower contact structure are present in a same dielectric material (i.e. a MOL dielectric material). United States Patent Application publication number <CIT>) discloses a memory device including an MTJ structure and a first metal residue. The MTJ structure includes a top surface having a first width, a bottom surface having a second width greater than the first width, and a stepped sidewall structure between the top surface and the bottom surface. The stepped sidewall structure includes a first sidewall, a second sidewall, and an intermediary surface connecting the first sidewall to the second sidewall. The first metal residue is in contact with the first sidewall and not in contact with the second sidewall.

Therefore, there is a need for improved designs and techniques that can prevent the deposition of re-sputtered conductive metal particles from underlying (thick) bottom metal layers on sidewalls of the MTJ stack.

According to an aspect of the present invention, there is provided a method of forming a memory device according to independent method claim <NUM>.

According to another aspect of the present invention, there is provided a memory device according to independent device claim <NUM>.

The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which:.

The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

For purposes of the description hereinafter, terms such as "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. Terms such as "above", "overlying", "atop", "on top", "positioned on" or "positioned atop" mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.

In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.

MRAM devices include cells or magnetic storage elements for storing data having a magnetically hard layer (i.e., the reference layer) and a magnetically soft layer (i.e., the free layer) separated by a thin dielectric layer (i.e., the tunnel barrier). This configuration is known as a magnetic tunnel junction (MTJ) pillar. MTJ pillar structures typically include a cobalt(Co)-based synthetic anti-ferromagnet (SAF), a CoFeB-based reference layer, a MgO-based tunnel barrier, a CoFeB-based free layer, and cap layers containing materials such as tantalum (Ta) and/or ruthenium (Ru). As mentioned above, embedded MTJ pillar structures are usually formed by patterning of blanket MTJ stacks. Reactive ion etch (RIE), and ion beam etch (IBE) processing of such MTJ stacks presents a major challenge, as it typically leads to shorts due to re-sputtering of thick bottom metal layers onto MTJ stack sidewalls.

Embodiments of the present disclosure generally relates to the field of magnetic storage devices, and more particularly to high performance MRAM devices based on perpendicular MTJ structures. Embodiments of the present disclosure provide an MRAM device with an embedded MTJ pillar structure, and a method of making the same, in which a free layer of the MTJ pillar structure is laterally recessed and surrounded by a dielectric material to prevent re-sputtered conductive metal particles from depositing on the tunnel barrier material of the MTJ pillar structure. Stated differently, the proposed embodiments may prevent back-sputtering of conductive metal particles during etching of the MTJ pillar structure by recessing the free layer of the MTJ pillar structure and depositing a dielectric material around the recessed free layer. This may reduce the risk of electrical shorts which is a common failure mode in traditional MTJ configurations, thereby increasing device reliability.

Embodiments by which the MTJ pillar structure with laterally-recessed free layer can be formed is described in detailed below by referring to the accompanying drawings in <FIG>.

Referring now to <FIG>, a cross-sectional view of a memory device <NUM> at an intermediate step during a semiconductor manufacturing process is shown, according to an embodiment of the present disclosure. The memory device <NUM> may include any MTJ-containing device such as, for example, MRAM, spin-transfer torque (STT) MRAM, spin-orbit torque (SOT) MRAM and the like. In the embodiment of <FIG>, the memory device <NUM> is an MRAM device based on a perpendicular MTJ pillar structure.

According to an embodiment, the memory device <NUM> includes an electrically conductive structure <NUM> that is embedded in an interconnect dielectric material layer <NUM>. A diffusion barrier liner <NUM> can be formed on sidewalls and a bottom wall of the electrically conductive structure <NUM>, as shown in the figure. Collectively, the electrically conductive structure <NUM>, the diffusion barrier liner <NUM>, and the interconnect dielectric material layer <NUM> provide an interconnect level. It should be noted that at least one other interconnect level and/or a middle-of-the-line (MOL) level may be located beneath the interconnect level including the interconnect dielectric material layer <NUM>, the electrically conductive structure <NUM>, and the diffusion barrier liner <NUM>. These other levels are not shown for clarity.

The interconnect dielectric material layer <NUM> can be composed of any interconnect dielectric material including, for example, silicon dioxide, silsesquioxanes, C doped oxides (i.e., organosilicates) that includes atoms of Si, C, O and H, thermosetting polyarylene ethers, or multilayers thereof. The term "polyarylene" is used in this application to denote aryl moieties or inertly substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl and the like.

The electrically conductive structure <NUM> is composed of an electrically conductive metal or metal alloy. Examples of electrically conductive materials that may be used in the present application include copper (Cu), aluminum (Al), or tungsten (W), while an example of an electrically conductive metal alloy is a Cu-Al alloy.

The diffusion barrier liner <NUM> is formed along the sidewalls and bottom wall of the electrically conductive structure <NUM>. In some embodiments, no diffusion barrier liner is present. The diffusion barrier liner <NUM> is composed of a diffusion barrier material (i.e., a material that serves as a barrier to prevent a conductive material such as copper from diffusing there through). Examples of diffusion barrier materials that can be used in providing the diffusion barrier liner <NUM> may include, but are not limited to, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN. In some embodiments, the diffusion barrier liner <NUM> may include a material stack of diffusion barrier materials. In one example, the diffusion barrier material may be composed of a stack of Ta/TaN.

The interconnect level including the interconnect dielectric material layer <NUM>, the electrically conductive structure <NUM>, and the diffusion barrier liner <NUM> may be formed utilizing conventional processes that are well-known to those skilled in the art including, for example, a damascene process. So as not to obscure the method of the present application, the techniques used to form the interconnect level including the interconnect dielectric material layer <NUM>, the electrically conductive structure <NUM>, and the diffusion barrier liner <NUM> are not provided herein.

With continued reference to <FIG>, a bottom electrode <NUM> is formed above top surfaces of the interconnect dielectric material layer <NUM>, the electrically conductive structure <NUM>, and the diffusion barrier liner <NUM>. As shown in the figure, the bottom electrode <NUM> covers an entirety of topmost surfaces of the interconnect dielectric material layer <NUM>, the electrically conductive structure <NUM>, and the diffusion barrier liner <NUM>.

The bottom electrode <NUM> may be composed of a conductive material such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN or any combination thereof. The bottom electrode <NUM> may have a thickness varying from approximately <NUM> to approximately <NUM> and ranges there between, although a thickness less than <NUM> and greater than <NUM> may be acceptable. The bottom electrode <NUM> may be formed by a deposition process such as, for example, sputtering, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). An etch back process, a planarization process (such as, for example, chemical mechanical polishing), or a patterning process (such as, for example, lithography and etching) may follow the deposition of the conductive material that provides the bottom electrode <NUM>.

In some embodiments (not shown), the bottom electrode <NUM> is located on a recessed surface of the electrically conductive structure <NUM>. In such embodiments, prior to forming the bottom electrode <NUM>, an upper portion of the electrically conductive structure <NUM> is removed utilizing a recess etching process, and thereafter the bottom electrode <NUM> is formed upon the recessed surface of the electrically conductive structure <NUM>. Thus, the bottom electrode <NUM> would be located on an entirety of the recessed topmost surface of the electrically conductive structure <NUM>. In such embodiments, a topmost surface of the bottom electrode <NUM> must not be coplanar with a topmost surface of the interconnect dielectric material layer <NUM>. Instead, the topmost surface of the bottom electrode <NUM> should be located approximately <NUM> to approximately <NUM> above (in z-direction) the topmost surface of the interconnect dielectric material <NUM>. And, a bottommost surface of bottom electrode <NUM> should be located approximately <NUM> to approximately <NUM> below (in z-direction) the topmost surface of the interconnect dielectric material <NUM>.

In some embodiments, a conductive layer (not shown) including any conductive material can be formed above the bottom electrode <NUM>. In some embodiments, a material that has, or combination of materials that have, a lower atomic weight than the conductive material that provides the bottom electrode <NUM> can be used as the conductive layer (not shown). Typically, the conductive material that provides the conductive layer has a lower sticking coefficient than that of the bottom electrode <NUM>. Illustrative examples of conductive materials that can be used as the conductive layer can include one of the conductive materials mentioned above for the bottom electrode <NUM> with the proviso that the selected conductive material of the conductive layer (not shown) has a lower atomic weight than the conductive material of bottom electrode <NUM>. In one example, and when the bottom electrode <NUM> is composed of TaN, then the conductive layer can be composed of Ti or TiN, Nb or NbN.

If present, the conductive layer (not shown) can be formed by a deposition process such as, for example, sputtering, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). The thickness of the conductive layer may be from <NUM> to <NUM>. Other thicknesses besides the specified range can also be employed as the thickness of the conductive layer.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> is shown depicting forming an MTJ stack <NUM> above the bottom electrode <NUM>, according to an embodiment of the present disclosure. The MTJ stack <NUM> may include at least a magnetic reference layer <NUM>, a tunnel barrier layer <NUM>, and a magnetic free layer <NUM> as depicted in <FIG>. It should be noted that other MTJ stack <NUM> configurations are possible such as, for example, the magnetic free layer <NUM> being located at the bottom of the MTJ stack <NUM> and the magnetic reference layer <NUM> being at the top of the MTJ stack <NUM>.

The MTJ stack <NUM> also includes a non-magnetic spacer layer (not shown) located on the magnetic free layer, a second magnetic free layer located on the non-magnetic spacer layer, and/or a MTJ cap layer located on the magnetic free layer <NUM> or on the second magnetic free layer. The various material layers of the MTJ stack <NUM> can be formed by utilizing one or more deposition processes such as, for example, plating, sputtering, plasma enhanced atomic layer deposition (PEALD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD).

The magnetic reference layer <NUM> has a fixed magnetization. The magnetic reference layer <NUM> may be composed of a metal or metal alloy (or a stack thereof) that includes one or more metals exhibiting high spin polarization. In alternative embodiments, exemplary metals for the formation of the magnetic reference layer <NUM> may include iron, nickel, cobalt, chromium, boron, or manganese. Exemplary metal alloys may include the metals exemplified by the above. In another embodiment, the magnetic reference layer <NUM> may be a multilayer arrangement having (<NUM>) a high spin polarization region formed from a metal and/or metal alloy using the metals mentioned above, and (<NUM>) a region constructed of a material or materials that exhibit strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that may be used include a metal such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and may be arranged as alternating layers. The strong PMA region may also include alloys that exhibit strong PMA, with exemplary alloys including cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, and/or iron-palladium. The alloys may be arranged as alternating layers. In one embodiment, combinations of these materials and regions may also be employed.

The tunnel barrier layer <NUM> is composed of an insulator material and is formed at such a thickness as to provide an appropriate tunneling resistance. Exemplary materials for the tunnel barrier layer <NUM> may include magnesium oxide, aluminum oxide, and titanium oxide, or materials of higher electrical tunnel conductance, such as semiconductors or low-bandgap insulators.

The magnetic free layer <NUM> may be composed of a magnetic material (or a stack of magnetic materials) with a magnetization that can be changed in orientation relative to the magnetization orientation of the magnetic reference layer <NUM>. Exemplary magnetic materials for the magnetic free layer <NUM> include alloys and/or multilayers of cobalt, iron, alloys of cobalt-iron, nickel, alloys of nickel-iron, and alloys of cobalt-iron-boron.

It should be noted that some elements and/or features of the memory device <NUM> are illustrated in the figures but not described in detail in order to avoid unnecessarily obscuring the presented embodiments. For illustration purposes only, without intent of limitation, only one MTJ stack <NUM> with a corresponding bottom electrode <NUM> is depicted in the memory device <NUM>. As may be understood by those skilled in the art, the memory device <NUM> may include more than one MTJ stack <NUM>.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> is shown depicting forming a patterned hardmask layer <NUM>, according to an embodiment of the present disclosure.

The patterned hardmask layer <NUM> may be composed of a metal (not shown) such as TaN, TaAlN, WN as the bottommost material, and a dielectric material (not shown) such as silicon dioxide, silicon nitride, silicon carbide, and the like, as the topmost material. The hardmask layer <NUM> can be deposited by any suitable deposition method known in the art. It should be noted that the metal layer in the patterned hardmask layer <NUM> is not sacrificial, while the dielectric layer in the patterned hardmask layer <NUM> is sacrificial, in that the dielectric layer will be removed after completion of the patterning process. In some embodiments, top layers (not shown) of the MTJ stack <NUM> may act as both a hardmask for etching the MTJ stack <NUM> and as an interlayer conductor channel.

A (vertical) thickness of the hardmask layer <NUM> may vary between approximately <NUM> to approximately <NUM>, although other thicknesses above or below this range may be used as desired for a particular application. It should be noted that the process of forming and patterning the hardmask layer <NUM> for etching the underlying MTJ stack <NUM> is standard and well known in the art.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> depicting etching the magnetic free layer <NUM> is shown, according to an embodiment of the present disclosure. In this embodiment, a dry etching technique such as a reactive-ion etching (RIE) or ion beam etching (IBE) can be implemented to recess the magnetic free layer <NUM>, as depicted in the figure. The magnetic free layer <NUM> is laterally recessed until a (horizontal) thickness of the magnetic free layer <NUM> is between approximately <NUM> to approximately <NUM>.

The process of patterning the MTJ stack <NUM> consists of steps well-known in the art, which generally include forming a pattern on a photoresist layer (not shown) that is transferred to the patterned hardmask layer <NUM> and used to pattern the underlying MTJ stack <NUM> (and bottom electrode <NUM>) via any suitable etching technique. In this embodiment, patterning of the MTJ stack <NUM> starts by laterally recessing the magnetic free layer <NUM>, then the etching process is stopped at an uppermost surface of the tunnel barrier layer <NUM>. As will be described below, a spacer material is deposited on the memory device <NUM> after recessing the magnetic free layer <NUM>.

Alternatively or additionally, in some embodiments, the etching process may continue until an uppermost surface of the magnetic reference layer <NUM>. Thus, in such instances, the tunnel barrier layer <NUM> may also be laterally recessed. In some embodiments, the tunnel barrier layer <NUM> can be partially or completely removed during the etching process.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> depicting the formation of a spacer material <NUM> is shown, according to an embodiment of the present disclosure. The spacer material <NUM> can be deposited on the memory device <NUM> and subsequently etched (<FIG>) to form sidewall spacers <NUM> as configured in <FIG>.

The spacer material <NUM> may include an insulator material such as an oxide, nitride, oxynitride, silicon carbon oxynitride, silicon boron oxynitride, low-k dielectric, or any combination thereof. Standard deposition and etching techniques may be used to form the spacer material <NUM>.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> depicting forming sidewall spacers <NUM> from the spacer material <NUM> (<FIG>) is shown, according to an embodiment of the present disclosure. The spacer material <NUM> (<FIG>) can be etched using, for example, an anisotropic etch, to form the sidewall spacers <NUM>. As known by those skilled in the art, the insulator material forming the spacer material <NUM> (<FIG>) is removed from all horizontal surfaces of the memory device <NUM> during the etching process.

According to an embodiment, the sidewall spacers <NUM> are positioned on opposing sidewalls of the magnetic free layer <NUM> and a bottom portion of the patterned hardmask layer <NUM>. A bottom surface of the sidewall spacers <NUM> is directly above the tunnel barrier layer <NUM>. Thus, the sidewall spacers <NUM> confine an active region of the memory device <NUM> formed by the magnetic free layer <NUM> and portions of the tunnel barrier layer <NUM> underneath the magnetic free layer <NUM>. This configuration may prevent back-sputtering of metal particles from bottom metal layers, such as the bottom electrode <NUM>, onto the tunnel barrier layer <NUM> during patterning of the MTJ stack <NUM>, thus preventing electrical shorts or leakage current between bottom metal layers and top metal layers within the MTJ stack <NUM>.

According to an embodiment, a (horizontal) thickness of the sidewall spacers <NUM> may vary between approximately <NUM> to approximately <NUM>, although other thicknesses above or below this range may be used as desired for a particular application.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> depicting etching a bottom portion of the MTJ stack <NUM> and the bottom electrode <NUM> is shown, according to an embodiment of the present disclosure.

In this embodiment, patterning of the MTJ stack <NUM> continues by etching remaining bottom layers of the MTJ stack <NUM> including the magnetic reference layer <NUM> and the tunnel barrier layer <NUM>. Any suitable etching technique can be used to recess the magnetic reference layer <NUM> and the tunnel barrier layer <NUM>. For example, the magnetic reference layer <NUM> and the tunnel barrier layer <NUM> can be recessed using a dry etching technique such as reactive ion etch (RIE), or ion beam etch (IBE). A (horizontal) thickness of the sidewall spacers <NUM> together with a thickness of the magnetic free layer <NUM> indicate a thickness of the magnetic reference layer <NUM> and the tunnel barrier layer <NUM>. Stated differently, the magnetic reference layer <NUM> and the tunnel barrier layer <NUM> of the magnetic tunnel junction stack <NUM> located below the magnetic free layer <NUM> are recessed until a thickness of the magnetic reference layer <NUM> and the tunnel barrier layer <NUM> is equal to a thickness of the sidewall spacers <NUM> plus a thickness of the magnetic free layer <NUM>.

The patterning process continues by recessing the bottom electrode <NUM>. In an embodiment, an ion beam etch (IBE) can be performed to recess the bottom electrode <NUM> (i.e., electrode open), as depicted in the figure.

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> depicting forming a dielectric capping layer <NUM> is shown, according to an embodiment of the present disclosure.

The dielectric capping layer <NUM> is conformally deposited on the memory device <NUM>. As depicted in the figure, portions of the dielectric capping layer <NUM> perpendicular to the interconnect dielectric material layer <NUM> are located laterally adjacent to the bottom electrode <NUM>, the magnetic reference layer <NUM>, the tunnel barrier layer <NUM>, sidewall spacers <NUM> and sidewalls of the hardmask layer <NUM>. Portions of the dielectric capping layer <NUM> parallel to the interconnect dielectric material layer <NUM> are located above the interconnect dielectric material layer <NUM> and a top surface of the hardmask layer <NUM>. Optionally, in another embodiment of the invention, the portions of the dielectric capping layer <NUM> parallel to the interconnect dielectric material layer <NUM> are removed by a directional etch process such as RIE.

The dielectric capping layer <NUM> may be composed of any dielectric material such as, for example, SiC, Si3N4, SiO2, a carbon doped oxide, a nitrogen and hydrogen doped silicon carbide SiC(N,H) or multilayers thereof. The dielectric capping layer <NUM> can be formed utilizing a conventional deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), chemical solution deposition, evaporation, or plasma enhanced atomic layer deposition (PEALD).

Referring now to <FIG>, a cross-sectional view of the memory device <NUM> depicting forming a dielectric filling layer <NUM> is shown, according to an embodiment of the present disclosure. Any suitable deposition process can be used to form the dielectric filling layer <NUM> in the memory device <NUM>. The dielectric filling layer <NUM> may be made of analogous materials and formed in similar ways as the interconnect dielectric material layer <NUM>. In some embodiments, a planarization process may be conducted on the memory device <NUM> after deposition of the dielectric filling layer <NUM>.

Therefore, by recessing the magnetic free layer <NUM> and forming the sidewalls spacers <NUM> on opposing sides of the magnetic free layer <NUM> prior to patterning of the MTJ stack <NUM> and bottom electrode <NUM>, back sputtering of metal particles can be prevented during subsequent etching of bottom metal layers. More particularly, the laterally-recessed magnetic free layer <NUM> surrounded by the sidewall spacers <NUM> confines the active MTJ region such that re-sputtering does not lead to electrical shorts in the memory device <NUM>, thereby improving device reliability.

Further, embodiments of the present disclosure, may extend scalability of embedded MRAM devices and other embedded memory elements (such as RRAM) due to lack of tunnel barrier or metal-oxide device layer shorts.

Finally, embodiments of the present disclosure, provide a method including a sequence of processing steps that can be conducted using only one chamber, thereby avoiding exposure of the MTJ stack <NUM> to oxygen. Specifically, the processing steps described in <FIG> can be performed in the same processing chamber, thus facilitating the manufacturing process and reducing exposure of the MTJ stack <NUM> to oxygen.

Claim 1:
A method of forming a memory device, comprising:
forming a bottom electrode (<NUM>) above an electrically conductive structure (<NUM>) embedded in an interconnect dielectric material (<NUM>), wherein the electrically conductive structure (<NUM>) further comprises a diffusion barrier liner (<NUM>) located on a bottom surface and lateral sidewalls of the electrically conductive structure;
forming a magnetic tunnel junction stack (<NUM>) above the bottom electrode, the magnetic tunnel junction stack comprising a magnetic reference layer (<NUM>) above the bottom electrode, a tunnel barrier layer (<NUM>) above the magnetic reference layer (<NUM>), and a magnetic free layer (<NUM>) above the tunnel barrier layer;
recessing opposed lateral portions of the magnetic free layer (<NUM>); and
forming sidewall spacers (<NUM>) on the opposed lateral portions of the magnetic free layer (<NUM>) for, at least in part, confining an active region formed by the magnetic free layer and the tunnel barrier layer (<NUM>); characterized by:
recessing the bottom electrode;
the magnetic tunnel junction stack further comprising:
a non-magnetic spacer layer located on the magnetic free layer (<NUM>), a second magnetic free layer located on the non-magnetic spacer layer, and a magnetic tunnel junction cap layer located on at least one of the magnetic free layer (<NUM>) and the second magnetic free layer;
wherein recessing the opposed lateral portions of the magnetic free layer (<NUM>) further comprises:
forming a patterned hardmask layer (<NUM>) above the magnetic free layer (<NUM>); and
etching the opposed lateral portions of the magnetic free layer (<NUM>); and
wherein the patterned hardmask layer (<NUM>) comprises a metal as a bottommost material, and a sacrificial dielectric material as a topmost material.