Patent Description:
At least one embodiment of the present disclosure relates to a substrate and a method of manufacturing the same, an electronic device.

Driving circuits, integrated circuit chips and so on for control of display operation are generally provided in or connected to a peripheral circuit region that surrounds a display region of a display. These structures occupy a larger space, and this will lead to a larger bezel size of the display. To increase the percentage of the area of the display area to the area of the display as much as possible while the reliability of fixing between the bezel and the display screen is ensured, it is necessary that the size of the peripheral circuit region is compressed as much as possible to form a bezel that is as narrow as possible. As the resolution of the display is becoming bigger and bigger, to decrease the percentage of a bezel in the display as much as possible, the manufacturers are all devoted to a research in narrowing of the display's bezel. <CIT> discloses an organic light emitting diode (OLED) display with improved display unit sealing performance. The OLED display includes a substrate, a display unit formed over the substrate and including a plurality of pixels, a conductive contact layer disposed at a distance from the display unit around the display unit, and a sealing member facing the display unit and being fixed to the substrate by the conductive contact layer. The sealing member includes a plurality of metal layers laminated with an insulating adhesive layer formed therebetween, and the plurality of metal layers is electrically connected to the display unit through the conductive contact layer.

It is an objective of the present disclosure to provide a substrate, an electronic device and a method of manufacturing a substrate.

The object is achieved by the respective independent claims. Further embodiments are defined in corresponding dependent claims.

A brief description will be given below to the accompanying drawings of the embodiments to provide a more clear understanding of the technical proposals of the embodiments of the present disclosure. Apparently, the drawings described below only involve some embodiments of the present disclosure but are not intended to limit the present disclosure.

In order to make objects, technical details and advantages of the embodiments of the present disclosure apparent, the technical solutions of the embodiments will be described in a clearly and completely way in connection with the drawings related to the embodiments of the disclosure. The scope of the present invention is not limited to the disclosed embodiments, but is defined by the appended claims.

Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms, such as 'first,' 'second,' or the like, which are used in the description and the claims of the present disclosure, are not intended to indicate any sequence, amount or importance, but for distinguishing various components. The terms, such as 'comprise/comprising,' 'include/including,' or the like are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but not preclude other elements or objects. The terms, 'in/inside,' 'out/outside,' 'on,' 'under,' or the like are only used to indicate relative position relationship, and when the absolute position of the object which is described is changed, the relative position relationship may be changed accordingly.

The dimensions of attached drawings used in the present disclosure are not drawn strictly in accordance with the actual proportion, and the amount of components in an array substrate is not limited to the amount shown in the drawings. The specific dimension and quantity of each structure may be determined according to the actual needs. The attached drawings in this disclosure are only structurally schematic diagrams.

In this disclosure, "outside of a working region" refers to a side of the working region near the outer profile edge of a base substrate. The direct overlap between structure A and structure B refers to that structure A contacts structure B and no any other structure exists between the structure A and the structure B. For example, structure A is a bridging conductive layer, and structure B is a common electrode lead. For example, structure A is a common electrode, and structure B is a bridging conductive layer.

It is to be noted that for a source electrode and a drain electrode of any one of thin film transistors in the present disclosure, the two are merely distinguished by the name, and in fact, the source electrode and the drain electrode of any of a plurality of thin film transistors in the present disclosure are exchangeable.

For an organic light emitting diode (OLED) display device, it may not use a backlight, and moreover, the display viewing angle is wide, the picture quality is uniform, the response speed is fast, colorization is easier, light emission can be achieved with a simple driving circuit, the manufacturing process is simple, manufacture into a flexible panel is possible, it complies with the demands of lightness, thinness, shortness and smallness, and the application covers panels of various sizes. However, an active matrix OLED (AMOLED) display device at present stage still has some shortcomings in some aspects. For example, compared with an active matrix LCD (AMLCD) display device, a peripheral circuit structure of an active back panel for the AMOLED display device occupies a relatively large area, and this makes its frame width be larger. In addition, lifetime of the AMOLED display device is also lower than that of the AMLCD at present, and it is partly due to the fact that the Joule heat at a current concentration region in the peripheral circuit leads to a higher temperature rise, and the lifetime of OLED devices in the vicinity of this region is adversely affected. Reducing the temperature rise caused by the Joule heat of the peripheral circuit also needs to occupy a larger area to reduce the wiring resistance of the peripheral circuit generally.

<FIG> is a schematic plan view of a substrate, and <FIG> is a schematically sectional view taken along a line I-I' in <FIG>. Referring to <FIG>, the substrate is a display substrate, which includes a base substrate <NUM> including a display region <NUM> and a peripheral region <NUM> around the display region <NUM>, and the peripheral region <NUM> includes a drive circuit region <NUM>. On the base substrate <NUM>, a drive circuit layer <NUM> is disposed, and in a place of the drive circuit layer <NUM> corresponding to the drive circuit region <NUM>, a driving circuit is disposed, such as a gate driving circuit. The substrate further includes a common electrode lead <NUM> disposed on the base substrate <NUM>. The common electrode lead <NUM> is located on a side of the drive circuit region <NUM> away from the display region <NUM>, and extends along the outer profile edge of the base substrate <NUM>. A first insulating layer is arranged between the common electrode lead <NUM> and the drive circuit layer <NUM>, so that the common electrode lead <NUM> is insulated from the driving circuit located in the drive circuit region <NUM>. The substrate's peripheral circuit structure further includes a bridging conductive layer <NUM> and a common electrode <NUM> that is electrically connected to the common electrode lead <NUM> via the bridging conductive layer <NUM>, that is, the bridging conductive layer <NUM> acts as a bridge by which electrical connection between the common electrode <NUM> and the common electrode lead <NUM> is realized. The common electrode <NUM> extends from the display region <NUM> to the drive circuit region <NUM> and contacts an end of the bridging conductive layer <NUM> near the display region <NUM> so as to achieve electrical connection, and an end of the bridging conductive layer <NUM> away from the display region <NUM> contacts the common electrode lead <NUM> so as to achieve electrical connection.

In the display substrate shown in <FIG>, the common electrode lead occupies a given width alone (that is, it does not share with other circuit structure) around the display region, that is, it occupies a given area alone, and this is not advantage in achieving a narrower bezel around the display region. In addition, the distance between the common electrode lead and the common electrode is larger, and the width of the bridging conductive layer is longer, which results in a larger resistance of the bridging conductive layer, and it is not advantage to increase the transmission speed of signal, and will also lead to the increasing of joule heat, and it is also disadvantage to the lifetime of the display device to which the display substrate is applied.

According to at least one embodiment of the present disclosure, a substrate is provided, which includes a base substrate, a peripheral circuit and a common electrode lead. The base substrate includes a working region, a non-working region outside of the working region and an outer profile edge. The non-working region includes a peripheral circuit region near the working region and a non-circuit region away from the working region. The peripheral circuit is arranged in the peripheral circuit region, and the common electrode lead is arranged in the non-working region. The peripheral circuit region includes the peripheral circuit provided therein, and the peripheral circuit is not provided in the non-circuit region. The orthographic projection of the common electrode lead on the base substrate at least partially coincides with the orthographic projection of the peripheral circuit region on the base substrate, and the common electrode lead is insulated from the peripheral circuit.

For example, <FIG> is a schematic plan view of a substrate provided by an embodiment of the present disclosure, <FIG> is an exemplarily schematic sectional view taken along a line H-H' in <FIG>, <FIG> is another exemplarily schematic sectional view taken along the line H-H' in <FIG>, <FIG> is still another exemplarily schematic sectional view taken along the line H-H' in <FIG>, and <FIG> is yet still another exemplarily schematic sectional view taken along the line H-H' in <FIG>.

As shown in <FIG>, the substrate <NUM> includes a base substrate <NUM> and a common electrode lead <NUM>. The base substrate <NUM> includes a working region <NUM>, a non-working region <NUM> outside of the working region <NUM> and an outer profile edge <NUM>. That is, the non-working region <NUM> is located on a side of the working region <NUM> near the outer profile edge <NUM> of the base substrate <NUM>. The outer profile edge <NUM> refers to an outer border of the base substrate <NUM>. The non-working region <NUM> includes a peripheral circuit region <NUM> near the working region <NUM> and a non-circuit region away from the working region <NUM>. For example, the working region <NUM> may be a display region or a light-emitting region, etc., and accordingly, the non-working region <NUM> may be a non-display region or a non-light-emitting region, etc. The non-working region <NUM>, for example, may have circuits, pads, interconnection structures and so on for supporting and implementing display, light emission and other functions provided therein, although it is not used for display, light emission, etc..

A circuit layer <NUM> is provided on the base substrate <NUM>. The circuit layer <NUM> includes a peripheral circuit <NUM> (the structure of which is not specifically shown in <FIG>) located in the peripheral circuit region <NUM>, for controlling the working state of a working unit within the working region <NUM>. For example, when the working unit is a light-emitting unit, the peripheral circuit <NUM> may be used to control whether the light-emitting unit emits light, or not, and the emitted light intensity. The peripheral circuit <NUM> may, for example, be a driving circuit, such as a gate driving circuit, etc. The present embodiment does not limit the type and concrete structure of the peripheral circuit <NUM>.

As shown in <FIG>, for example, the common electrode lead <NUM> is arranged along the outer profile edge <NUM> of the base substrate <NUM>. In other embodiment of the present disclosure, the common electrode lead <NUM> may be arranged along a portion of the outer profile edge <NUM> of the base substrate <NUM>. The orthographic projection of the common electrode lead <NUM> on the base substrate <NUM> partially coincides with the orthographic projection of the peripheral circuit region <NUM> on the base substrate <NUM>. For example, a portion of the common electrode lead <NUM> is located in the peripheral circuit region <NUM>, and the other portion of the common electrode lead <NUM> is located in a non-circuit region of the non-working region <NUM>. The orthographic projection of the common electrode lead <NUM> on the base substrate <NUM> partially coincides with the orthographic projection of the peripheral circuit region <NUM> on the base substrate <NUM>. For example, the orthographic projection of the common electrode lead <NUM> on the base substrate <NUM> partially coincides with the orthographic projection of the peripheral circuit <NUM> on the base substrate <NUM>. That is, in a direction perpendicular to the base substrate <NUM>, a portion of the common electrode lead <NUM> coincides with a portion of the peripheral circuit <NUM>. For another example, the peripheral circuit <NUM> includes a plurality of circuit elements (e.g., thin film transistors, lead wires, etc.) and a spacer zone between the plurality of circuit elements, and the orthographic projection of the common electrode lead <NUM> on the base substrate <NUM> coincides with the orthographic projection of the spacer zone on the base substrate <NUM>. Also, the common electrode lead <NUM> is insulated from the peripheral circuit <NUM>. Compared with the substrate shown in <FIG>, the width occupied by the common electrode lead <NUM> alone in the non-working region <NUM> can be reduced in the substrate <NUM> provided by an embodiment of the present disclosure, and when the peripheral circuit structure is applied to a substrate, panel or display device, the bezel around a working region can be narrowed (width of the bezel in a direction perpendicular to the common electrode lead is reduced). Or, due to the fact that a portion of the common electrode lead <NUM> overlaps with a portion of the peripheral circuit <NUM> and thus that portion of space occupied by the common electrode lead <NUM> is reduced, it is conducive to increasing the width of the common electrode lead <NUM>, so as to reduce the resistance of the common electrode lead <NUM>. In this way, on the one hand, it is propitious in improvement of the transmission speed of signal in the common electrode lead, in addition, it is conductive to reducing the power consumption and generated joule heat of the common electrode lead during operation, and to reducing the temperature rise caused by the joule heat. Consequently, it is propitious for improvement of lifetime of a device to which the substrate's peripheral circuit structure is applied, fir example, a display device.

It is to be noted that the width of the common electrode lead <NUM> in the embodiment of this disclosure refers to size of a dimension h in a direction perpendicular to the outer profile edge <NUM> as shown in <FIG>.

The substrate <NUM> further includes a common electrode <NUM>, which extends from the working region <NUM> to the peripheral circuit region <NUM>, and is electrically connected to the common electrode lead <NUM>. In this way, a common electrical signal (voltage) is transmitted to the common electrode <NUM> via the common electrode lead <NUM>, so as to control or drive the working state of the working region <NUM>.

As shown in <FIG>, the substrate <NUM> further includes a bridging conductive layer <NUM>, which is located in a non-working region <NUM> (e.g., in a peripheral circuit region <NUM>) and insulated from the peripheral circuit <NUM>. The bridging conductive layer <NUM> extends across the peripheral circuit <NUM> and electrically connects the common electrode lead <NUM> with the common electrode <NUM>. For example, a portion of the common electrode <NUM> may be situated in the <NUM> non-working region <NUM> and extend from the <NUM> non-working region <NUM> to the working region <NUM>. One end of the common electrode <NUM> away from the working region <NUM> is electrically connected to the bridging conductive layer <NUM>. For example, one end of the common electrode <NUM> away from the working region <NUM> may be in direct contact with one end of the bridging conductive layer <NUM> near the working region <NUM> so as to achieve electrical connection. That is, the common electrode <NUM> directly overlaps with the bridging conductive layer <NUM> so as to realize electrical connection between the common electrode <NUM> and the bridging conductive layer <NUM>. At the same time, the bridging conductive layer <NUM> is electrically connected to the common electrode lead <NUM>, so as to electrically connect the common electrode lead <NUM> to the common electrode <NUM> by the bridging conductive layer <NUM>. For example, one end of the bridging conductive layer <NUM> away from the working region <NUM> directly overlaps with the common electrode lead <NUM>, so as to achieve electrical connection between the bridging conductive layer <NUM> and the common electrode lead <NUM>. This direct overlapping is beneficial to the reduction of the contact resistance and is easy to fabricate it. Generally, the common electrode <NUM> may be formed by chemical vapor deposition or magnetron sputtering, or the like, the bridging conductive layer <NUM> may be formed by photolithography, while the dimensional accuracy of a film layer formed by chemical vapor deposition or magnetron sputtering is lower than that of a photolithography process, and it generally need to reserve a sufficient packaging space previously in a place of the non-working region <NUM> on the periphery of a substrate that is near the outer profile edge <NUM> of the base substrate <NUM>. If the common electrode <NUM> is made to directly overlap with the common electrode lead <NUM>, it needs more packaging space to be reserved previously. By provision of the bridging conductive layer, the dimensional accuracy in the case that a packaging space is reserved previously can be improved. In this way, it is further conducive to the realization of narrower bezel.

In the substrate's peripheral circuit structure provided by an embodiment of the present disclosure, the common electrode lead <NUM> may also be arranged along a portion of the outer profile edge <NUM> of the base substrate <NUM>. The orthographic projection of the common electrode lead <NUM> on the base substrate <NUM> partially coincides with the orthographic projection of the peripheral circuit region <NUM> on the base substrate <NUM>, and this is also beneficial to the reduction of the width of the bridging conductive layer <NUM>, so as to beneficial to reducing the resistance of the bridging conductive layer <NUM>. In this way, on the one hand, it is propitious for the improvement of the transmission speed of a signal in the bridging conductive layer, in addition, it is conductive to reducing the power consumption and the generated Joule heat of the bridging conductive layer during operation, and to reducing temperature rise caused by the Joule heat. Consequently, it is beneficial to the improvement of lifetime of a device, to which the substrate's peripheral circuit structure is applied, for example, for a display device. The width of the bridging conductive layer <NUM> refers to the width of the bridging conductive layer <NUM> in a direction where the above dimension h lies.

For example, the bridging conductive layer <NUM>, the common electrode lead <NUM> and the common electrode <NUM> include material, which is a transparent conductive material, or an opaque conductive material, and the transparent conductive material, for example, may be indium tin oxide (ITO), indium zinc oxide (IZO), or the like, and the opaque conductive material, for example, may be a metallic material, such as copper, aluminum, a copper alloy, an aluminum alloy, or the like, with higher conductivity. The bridging conductive layer <NUM> and common electrode lead <NUM> adopt the above materials or materials of other kinds with higher conductivity, and this is beneficial to the improvement of the transmission speed of a common signal. For example, when the working region <NUM> is a light-emitting region, and light needs to exit from the common electrode <NUM> side in <FIG>, the common electrode <NUM> made of a transparent material.

The material types listed above are only exemplary embodiments. Embodiments of the present disclosure do not limit materials of the bridging conductive layer, the common electrode lead, and the common electrode, and those skilled in the art can choose according to specific needs.

For example, the peripheral circuit <NUM> may include an external connection portion <NUM>, and the external connection portion <NUM> includes an external connection joint <NUM> and an external connection lead <NUM>. The peripheral circuit <NUM> may include an internal connection portion and the external connection portion <NUM>. The internal connection portion refers to a conductive structure and so on formed by interconnection of various components of the peripheral circuit <NUM>. For example, the peripheral circuit <NUM> is a driving circuit, such as a gate driving circuit, or a data driving circuit. Exemplary description will be made below by taking the peripheral circuit <NUM> being a gate driving circuit as an example, and the gate driving circuit is of GOA type. The internal connection portion includes leads inside each driving unit of the gate driving circuit, leads between driving units, and interconnection parts between thin film transistors and capacitors. The external connection portion <NUM> includes a portion of the peripheral circuit <NUM> connected to its external signal transmission structure. For example, the external connection portion <NUM> includes an external connection joint <NUM> connected to a plurality of drive units of a gate driving circuit and an external connection lead <NUM>, and the external connection lead <NUM> can be used to electrically connect the external connection joint <NUM> with the external signal transmission structure. For example, the external connection portion <NUM> may be used for connection to a timing controller.

For example, the orthographic projection of the external connection joint <NUM> on the base substrate <NUM> does not coincide with the orthographic projection of the common electrode lead <NUM> on the base substrate <NUM>. For example, the peripheral circuit region <NUM> includes a first zone <NUM> away from the working region <NUM> and a second zone <NUM> near the working region. The external connection joint <NUM> is arranged in the second zone <NUM> of the peripheral circuit region <NUM>. For example, the second zone <NUM> does not overlap with the common electrode lead <NUM> in a direction perpendicular to the base substrate <NUM>, so that the orthographic projection of the external connection joint <NUM> on the base substrate <NUM> does not coincide with the orthographic projection of the common electrode lead <NUM> on the base substrate <NUM>. In this way, it is convenient to form a via hole over the external connection joint <NUM> and to arrange the external connection lead <NUM>, so that this process will not be hindered by the common electrode lead <NUM>.

For example, the substrate <NUM> may further include an interlayer insulating layer <NUM> arranged between the peripheral circuit <NUM> and the common electrode lead <NUM>, and the interlayer insulating layer <NUM> covers the peripheral circuit <NUM> so that the peripheral circuit <NUM> is insulated from the common electrode lead <NUM>. For example, material of the interlayer insulating layer <NUM> may be an organic insulating material, such as resin, and rubber, and may also be an inorganic insulating material, such as silicon nitride. Material of the interlayer insulating layer <NUM> is not limited to the above listed types, and embodiments of the present disclosure do not limit them.

For example, the interlayer insulating layer <NUM> includes a via hole exposing the external connection joint <NUM> of the peripheral circuit <NUM>, through which the external connection lead <NUM> is electrically connected to the external connection joint <NUM> of the peripheral circuit <NUM>. For example, the external connection lead <NUM> may be electrically connected to an external controller, such as a timing controller, so that the external controller and the peripheral circuit can be used for joint control of the working state of the working region <NUM>, for example, for control of the turn-on and turn-off of work units of the work region <NUM>, execution of progressive scanning, and so on.

For example, the external connection lead <NUM> may be of a same material and arranged in a same layer as the common electrode lead <NUM>. This is conducive to simplifying the structure and simplifying the manufacturing process. Material of the external connection lead <NUM> may refer to the previous description about the material of the common electrode lead <NUM>.

It is to be noted that, in this disclosure, the external connection lead and the common electrode lead being arranged in the same layer refers to that the external connection lead and the common electrode lead may be formed by a same patterning process with the same mask, and the external connection lead and the common electrode lead are in contact with a same layer. For example, in <FIG>, both the external connection lead <NUM> and the common electrode lead <NUM> contact the interlayer insulating layer <NUM>.

For example, the substrate <NUM> may further include a planarization layer <NUM> covering the peripheral circuit <NUM> and a portion of the common electrode lead <NUM>, for providing a flat surface for arrangement of functional devices in the working region <NUM> while insulation of the external connection portion <NUM> of the peripheral circuit <NUM> from the bridging conductive layer <NUM> and the common electrode <NUM> located above the planarization layer is achieved. The planarization layer <NUM> exposes a portion of the common electrode lead <NUM>, so that the bridging conductive layer <NUM> can be electrically connected to the common electrode lead <NUM>.

For example, in the embodiment shown in <FIG>, at a side of the interlayer insulating layer <NUM> near the outer profile edge <NUM> of the base substrate <NUM>, a step portion is formed, and the common electrode lead <NUM> covers the step portion, and extends from a lower position relative to the base substrate <NUM> to a higher position relative to the base substrate <NUM>. In other embodiment of the present disclosure, no this step portion is provided. For example, in the embodiment shown in <FIG>, the interlayer insulating layer <NUM> has a flat surface on a side near the outer profile edge of the base substrate <NUM>, and in this case, the common electrode lead <NUM> is arranged on the flat surface.

The above embodiment is the case where a portion of the common electrode lead <NUM> overlaps with the first zone <NUM> of the peripheral circuit region <NUM> in a direction perpendicular to the base substrate <NUM>, and in another embodiment of the present disclosure, as shown in <FIG>, the entire common electrode lead <NUM> overlaps with the peripheral circuit <NUM> in a direction perpendicular to the base substrate <NUM>. That is, the orthographic projection of the common electrode lead <NUM> on the base substrate <NUM> falls within the orthographic projection of the peripheral circuit <NUM> on the base substrate <NUM>. In this way, width of the non-working region <NUM> can be further reduced, and the bezel width of a device, to which the substrate's peripheral circuit structure <NUM> is applied, such as a display device, is further reduced.

In still another embodiment of the present disclosure, as shown in <FIG>, the common electrode <NUM> and the bridging conductive layer <NUM> may also be an integral structure to realize electrical connection between the common electrode <NUM> and the common electrode lead <NUM>. It can be understood that the common electrode <NUM> and the common electrode lead <NUM> may overlap directly to realize electrical connection between them, while no bridging conductive layer <NUM> is provided.

In the embodiment shown in <FIG>, the external connection joint <NUM> is disposed on a side of the common electrode lead <NUM> away from the outer profile edge <NUM> of the base substrate <NUM>.

In another embodiment, an external connection joint may also be located on a side of a common electrode lead near the outer profile edge of a base substrate. <FIG> is a schematic plan view illustrating another substrate's peripheral circuit structure provided by an embodiment of the present disclosure; <FIG> is a schematically sectional view taken along a line G-G' in <FIG>. For example, as shown in <FIG>, an external connection joint <NUM> is disposed on a side of a common electrode lead <NUM> near the outer profile edge of a base substrate <NUM>, that is, the connection joint <NUM> is disposed between the common electrode lead <NUM> and the outer profile edge of the base substrate <NUM>. Compared with the embodiment shown in <FIG>, the length of the bridging conductive layer <NUM> can be further reduced by the embodiment shown in <FIG>, and the resistance of the bridging conductive layer <NUM> is further reduced. Other technical effects brought about by the embodiment shown in <FIG> can refer to the above descriptions, and no details are repeated here.

<FIG> is a schematically partial enlarged view of a peripheral circuit in <FIG>. Exemplarily, as shown in <FIG>, the peripheral circuit <NUM> may include a plurality of thin film transistors arranged on the base substrate <NUM>, for example, a first thin film transistor <NUM> and a second thin film transistor <NUM>. Each of the first thin film transistor <NUM> and the second thin film transistor <NUM> includes a first portion <NUM> and a gate electrode <NUM>. A source electrode, a drain electrode, and a channel area are included in each of the first portions <NUM> of the first thin film transistor <NUM> and the second thin film transistor <NUM>. The peripheral circuit <NUM> may further include a first insulating layer <NUM> covering the first portions <NUM> of the first thin film transistor <NUM> and the second thin film transistor <NUM>, a capacitor and a peripheral circuit signal output lead <NUM>. The peripheral circuit signal output lead <NUM> is configured to output an output signal of the peripheral circuit to the working region on an inner side of the non-working region. For example, when the peripheral circuit <NUM> is a GOA driving circuit, a gate driving signal (a progressive scanning signal) is outputted from the peripheral circuit signal output lead <NUM>. The capacitor includes a first plate <NUM> and a second plate <NUM> disposed to be opposed. For example, the gate electrode <NUM> of thin film transistor, the first plate <NUM> of the capacitor and the peripheral circuit signal output lead <NUM> are arranged in a same layer, and each of them is disposed on the first insulating layer <NUM>. They may be made of a same material, and may be formed simultaneously by a same process. For example, they are formed by a same patterning process with a same mask. The peripheral circuit may further include a second insulating layer <NUM> covering the gate electrode <NUM>, the first plate <NUM> of the capacitor and the peripheral circuit signal output lead <NUM>. The first insulating layer <NUM> and the second insulating layer <NUM> contain second via holes exposing source electrodes or drain electrodes of the thin film transistors.

For example, the peripheral circuit <NUM> further includes an internal connection portion including a connecting line, and for example, the connecting line includes a first portion <NUM>, a second portion <NUM> and a third portion <NUM>. The second plate <NUM> of the capacitor, the connecting line and the external connection joint <NUM> are arranged on the second insulating layer <NUM>. A drain electrode of the first thin film transistor <NUM> is electrically connected to a source electrode of the second thin film transistor <NUM> by the second portion <NUM> of the connecting line through a second via hole. The second plate <NUM> of the capacitor is electrically connected to a source electrode of the first thin film transistor <NUM> by the first portion <NUM> of the connecting line through a second via hole. Furthermore, the second plate <NUM> of the capacitor and the connecting line <NUM> may be formed integrally, and they can be formed of a same material simultaneously by a same patterning process with a same mask. A drain electrode of the second thin film transistor <NUM> is electrically connected to the peripheral circuit signal output lead <NUM> by the third portion <NUM> of the connecting line. In addition, the external connection joint <NUM>, the second plate <NUM> of the capacitor and the connecting line are disposed in a same layer.

It is to be noted that 'being disposed in the same layer' in the present disclosure refers to that structures disposed in the same layer may be formed from the same material simultaneously by the same patterning process with the same mask, and in contact with a same layer, which does not refer to that height of these structures relative to the base substrate is the same. For example, the external connection joint <NUM>, the second plate <NUM> of the capacitor and the connecting line are made of a same material, and formed from a same film layer simultaneously by a same patterning process with a same mask, and the external connection joint <NUM>, the second plate <NUM> of the capacitor and the connecting line are all in contact with the second insulating layer <NUM>, so as to simplify structure of the peripheral circuit and fabrication process.

For example, material of the external connection joint <NUM>, the second plate <NUM> of the capacitor and the connecting line may be copper, aluminum, a copper alloy, an aluminum alloy, silver, chromium, or the like, but is not limited to the above listed categories. Embodiments of the present disclosure do not set a limit to the material of components, and those skilled in the art can make a reference to a common technique.

In the substrate provided by an embodiment of the present disclosure, the entire peripheral circuit <NUM> is located below the interlayer insulating layer <NUM>, that is, the interlayer insulating layer <NUM> covers the peripheral circuit <NUM>. For example, the interlayer insulating layer <NUM> covers the external connection joint <NUM>, the second plate <NUM> of the capacitor and the connecting line, etc. In this way, a flat insulating layer can be formed on the peripheral circuit <NUM>, and when a common electrode lead <NUM> is arranged on an interlayer insulating layer <NUM>, and the common electrode lead <NUM> partially or even completely overlaps with a peripheral circuit below the interlayer insulating layer <NUM>, insulation of the common electrode lead <NUM> from the peripheral circuit <NUM> can be achieved.

For example, the substrate provided by an embodiment of the present disclosure may be an array substrate, or a display substrate, etc. <FIG> is a schematic plan view of an array substrate provided by an embodiment of the present disclosure, <FIG> is a schematic plan view of another array substrate provided by an embodiment of the present disclosure, <FIG> is a schematic plan view of still another array substrate provided by an embodiment of the present disclosure; and <FIG> is a schematically sectional view taken along a line G-G' in <FIG>.

For example, as shown in <FIG>, a common electrode lead <NUM> and a peripheral circuit of a peripheral circuit region <NUM> are used to control the working state of a working region <NUM>. The common electrode lead <NUM> and the peripheral circuit region <NUM> may be in a place on the left side of an array substrate <NUM> near its outer profile edge, and a control signal is input from the left side to the working region <NUM>. For example, as shown in <FIG>, a common electrode lead <NUM> and a peripheral circuit region <NUM> may also be arranged in a place on the upper side of an array substrate <NUM> near its outer profile edge, and a control signal is input from the upper side to a working region <NUM>. For another example, as shown in <FIG>, a common electrode lead <NUM> and a peripheral circuit region <NUM> may also be arranged in a place on opposite sides of an array substrate <NUM>, such as on the left side and the right side, near its outer profile edge. In this way, control signals can be input to a working region <NUM> at two sides at the same time, and a technical effect of reducing signal delay can be achieved. In this way, a better working effect is achieved by the array substrate <NUM>. For the case that the planar area of an array substrate <NUM> is larger, this technical effect is more significant. It is to be noted that terms "left", "right", "upper" in the embodiments of this disclosure refer to the relative locations shown in corresponding drawings.

For example, the working region is provided with a display element therein, and the display element includes a pixel defining layer, a light emitting layer, a first electrode and a second electrode. The pixel defining layer includes a plurality of openings; the light emitting layer is disposed in the plurality of openings; the first electrode covers the pixel defining layer and the light emitting layer, and extends from the display region toward the first common electrode lead; and the second electrode is arranged between the base substrate and the light emitting layer. The first electrode is a common cathode, and the first common electrode lead is a common cathode lead; or the first electrode is a common anode, and the first common electrode lead is a common anode wire.

For example, as shown in <FIG>, the working region <NUM> is provided with a plurality of array elements <NUM>, and the plurality of array elements include a common electrode <NUM>, and the common electrode <NUM> is electrically connected to a common electrode lead <NUM>. For example, the array elements <NUM> may be an organic light-emitting diode device, and the organic light-emitting diode device may be a top emission configuration, a bottom emission configuration, or other configuration. Exemplarily, the organic light-emitting diode device may include an anode <NUM> arranged on a base substrate <NUM>, a cathode disposed on the base substrate <NUM> to be opposed to the anode <NUM>, and an organic light-emitting layer <NUM> arranged between the anode <NUM> and the cathode. In the embodiment shown in <FIG>, the cathode is a common electrode <NUM>, and in this case, the common electrode lead <NUM> is a common cathode lead, the first electrode is a cathode (i.e., the common cathode), the second electrode is an anode, and a low-level signal is input to the common electrode <NUM> during the operation. For example, the anode <NUM> may be a reflective electrode, or a reflective layer (not shown in the figure) is disposed to be adjacent to the anode <NUM>, and lights are exited from the cathode side during operation. Alternatively, the cathode may be a reflective electrode, or a reflective layer is provided to be adjacent to the cathode, and lights are exited from the anode side during operation. In other embodiment of the present disclosure, positions of the anode and the cathode are exchangeable. For example, the anode may be a common electrode <NUM>. In this case, the common electrode lead <NUM> is a common anode lead, the first electrode is an anode (i.e., the common anode), the second electrode is a cathode, and a high-level signal is input to the common electrode <NUM> during operation.

For example, the organic light-emitting diode device may further include a pixel defining layer <NUM> to define a plurality of light-emitting units or pixel units, so that crosstalk between lights from adjacent light-emitting units or adjacent pixel units is prevented. The pixel defining layer <NUM> includes a plurality of openings, the organic light-emitting layer <NUM> is arranged in the openings, and the common electrode <NUM> may cover the pixel defining layer <NUM>.

For example, the perimeter circuit <NUM> may be a gate driving circuit, or a data driving circuit, etc. For example, the gate driving circuit or the data driving circuit includes thin film transistors, capacitors, gate-line leads or data-line leads, etc..

The array substrate provided by an embodiment of the disclosure can be used for electronic devices, such as display devices, illuminating devices, or the like. In the array substrate provided by the embodiment of the present disclosure, width occupied by the common electrode lead <NUM> alone in the non-working region <NUM> is reduced, so that the array substrate has a narrower bezel. In this way, a narrower bezel can be realized by a display device, an illuminating device, or the like, which adopt the array substrate. A narrower bezel can be realized by a display device, an illuminating device, or the like, which adopt the array substrate. While a narrow bezel is realized, the saved space can be used to increase width of a common electrode lead, so as to reduce the resistance of the common electrode lead. In this way, the resistance of the common electrode lead can be reduced. On the one hand, it is propitious for the improvement of the transmission speed of a signal in the common electrode lead, in addition, it is helpful to reducing the power consumption and the generated Joule heat of the common electrode lead during the operation, and to reducing temperature rise caused by the Joule heat. Consequently, it is beneficial to the improvement of the lifetime of the array substrate, the display device, or the illuminating device.

At least one embodiment of the present disclosure also provides an electronic device, which includes any of the substrates provided by embodiments of the present disclosure. For example, the electronic device may be a display device, an illuminating device, etc. Exemplarily, <FIG> is a schematic diagram of a display device provided by an embodiment of the present disclosure. As shown in <FIG>, the display device includes any of the array substrates provided by the embodiments of the present disclosure. For example, the display device may be an organic light-emitting diode display device. For example, the display device may be implemented as the following products: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any other product or component with display function.

<FIG> is only a schematic diagram of a display device that includes any of the array substrates provided in embodiment <NUM>. For other structures of the display device that are not shown, reference can be made to conventional techniques by those skilled in the art, and embodiments of the present disclosure do not limit them.

A narrower bezel can be achieved by the display device provided by an embodiment of the present disclosure. While a narrow bezel is realized, it is also beneficial to increasing width of a common electrode lead, so as to reduce the resistance of the common electrode lead. In this way, the resistance of the common electrode lead can be reduced. On the one hand, it is propitious for the improvement of the transmission speed of signal in the common electrode lead, in addition, it is beneficial to reducing power consumption and the generated joule heat of the common electrode lead during operation, to reducing the temperature rise caused by the Joule heat. Consequently, it is beneficial to the improvement of the lifetime of an array substrate, a display device, or an illuminating device.

At least one embodiment of the present disclosure also provides an array substrate manufacturing method, including: providing a base substrate including a working region, a non-working region outside of the working region and an outer profile edge, the non-working region including a peripheral circuit region near the working region and a non-circuit region away from the working region; a peripheral circuit is formed in the peripheral circuit region of the non-working region; and a common electrode lead extending along at least part of the outer profile edge of the base substrate is formed. A common electrode is formed to be electrically connected to the common electrode lead, and a bridging conductive layer is formed in the non-working region to electrically connect the common electrode lead with the common electrode. The peripheral circuit region is provided with the peripheral circuit, the peripheral circuit is not provided in the non-circuit region, the orthographic projection of the common electrode lead on the base substrate at least partially coincides with the orthographic projection of the peripheral circuit region on the base substrate, and the common electrode lead is insulated from the peripheral circuit An orthographic projection of the bridging conductive layer on the base substrate at least partially coincides with an orthographic projection of the peripheral circuit region on the base substrate, and the bridging conductive layer is insulated from the peripheral circuit.

Exemplarily, <FIG> are schematic diagrams illustrating an array substrate manufacturing method provided by an embodiment of the present disclosure. An exemplary introduction will be given below with reference to an example in which an array substrate with an organic light-emitting diode (OLED) device being included in a working region is formed.

As shown in <FIG>, a base substrate <NUM> is provided. The base substrate <NUM> may be, for example, a glass substrate, a quartz substrate, a resin (e.g. polyethylene) substrate, etc. The base substrate <NUM> has an outer profile edge <NUM> and includes a working region <NUM> and a non-working region <NUM> outside of the working region <NUM>. The non-working region <NUM> includes a peripheral circuit region <NUM> near the working region <NUM>. A circuit layer <NUM> is formed on the base substrate <NUM>, which includes forming a peripheral circuit <NUM> in the peripheral circuit region <NUM>. The peripheral circuit <NUM> may, for example, be a driving circuit, such as a gate driving circuit, or a data driving circuit. The manufacturing method of the circuit will be exemplarily introduced below by taking the peripheral circuit <NUM> being a gate driving circuit as an example.

<FIG> are schematic diagrams illustrating a manufacturing method of the driving circuit. Forming the peripheral circuit <NUM> includes forming an internal connection portion and an external connection portion of the peripheral circuit <NUM>. The external connection portion includes an external connection joint and an external connection lead, and the orthographic projection of the external connection joint on the base substrate <NUM> does not coincide with the orthographic projection of a common electrode lead <NUM> on the base substrate <NUM>. For example, the peripheral circuit region <NUM> includes a first zone <NUM> away from the working region <NUM> and a second zone <NUM> near the working region <NUM>. The internal connection portion is disposed in the first zone <NUM> of the peripheral circuit region <NUM>, and the external connection joint is formed within the second zone <NUM> of the peripheral circuit region <NUM>. For example, the first zone <NUM> does not coincide with the common electrode lead <NUM> in a direction perpendicular to the base substrate <NUM>, so that the orthographic projection of the external connection joint on the base substrate <NUM> does not coincide with the orthographic projection of the common electrode lead <NUM> on the base substrate <NUM>. Description will be made below by taking formation of thin film transistors as an example.

Forming the peripheral circuit includes forming a plurality of thin film transistors, such as forming a first thin film transistor and a second thin film transistor. A gate electrode, a source electrode, and a drain electrode are included in each of the first thin film transistor and the second thin film transistor.

As shown in <FIG>, a plurality of first portions <NUM> and a first insulating layer <NUM> are formed in the first zone <NUM> using conventional techniques in the field. A first portion <NUM> includes a channel area, a source area, and a drain area.

As shown in <FIG>, a gate metal layer <NUM> is formed on the first insulating layer <NUM>, and for example, the gate metal layer <NUM> may be formed by chemical vapor deposition, magnetron sputtering, or the like. Material of the gate metal layer <NUM> may be copper, aluminum, a copper alloy, an aluminum alloy, silver, chromium, or the like, but is not limited to the above listed categories.

Forming the peripheral circuit includes forming a gate-metal-layer pattern. For example, it may include forming gate electrodes of a plurality of thin film transistors, a first plate of a capacitor, a pattern of a connecting line between the gate electrodes of the plurality of thin film transistors and a pattern of a peripheral circuit output lead by a same patterning process with a same mask. As shown in <FIG>, the gate metal layer <NUM> is patterned, to simultaneously form a pattern of a plurality of gate electrodes <NUM> corresponding to first portions <NUM> of the plurality of thin film transistors, respectively, the first plate <NUM> of the capacitor, the plurality of gate electrodes <NUM> and a peripheral circuit signal output lead <NUM>. For example, the patterning can be realized by a photolithographic process.

As shown in <FIG>, a second insulating layer <NUM> covering a pattern formed by a gate metal layer <NUM>. Second via holes <NUM> for exposing source electrodes and drain electrodes of a plurality of thin film transistors that are located in the first insulating layer <NUM> and the second insulating layer <NUM> are formed. For example, material of the first insulating layer <NUM> and the second insulating layer <NUM> may be an inorganic insulating material, such as silicon nitride, etc. In this case, the second via holes <NUM> may be formed by a photolithographic process including exposure, development and etching. For example, material of the first insulating layer <NUM> and the second insulating layer <NUM> may be an inorganic insulating material or an organic insulating material, which may, for example, be a photosensitive organic insulating material. In this case, the second via holes <NUM> may be formed by exposure-development process. In this way, the etching steps can be decreased, and the process can be simplified.

For example, the method further includes forming a second-metal-layer pattern, which may include forming a second plate of a capacitor, a connecting line of the peripheral circuit, and the external connection joint by a same patterning process with a same mask. The connecting line includes a first portion, a second portion and a third portion. The second plate of the capacitor is electrically connected to a source electrode of the first thin film transistor by the first portion of the connecting line. A drain electrode of the first thin film transistor is electrically connected with a source electrode of the second thin film transistor by the second portion of the connecting line. A drain electrode of the second thin film transistor is electrically connected with the peripheral circuit signal output lead by the third portion of the connecting line.

Exemplarily, as shown in <FIG>, a second metal layer <NUM> is formed on the second insulating layer <NUM>, and the second metal layer <NUM> is electrically connected to the source areas and drain areas of active layers of the thin film transistors through the second via holes <NUM>. For example, the second metal layer <NUM> may be formed by chemical vapor deposition, magnetron sputtering, or the like. Material of the second metal layer <NUM> may be copper, aluminum, a copper alloy, an aluminum alloy, silver, chromium, or the like, but is not limited thereto.

As shown in <FIG>, the second metal layer <NUM> is patterned to simultaneously form a pattern of a second plate <NUM> of a capacitor, a first portion <NUM> of a connecting line for electrically connecting the second plate <NUM> of the capacitor to a source electrode of the first thin film transistor, a second portion <NUM> of the connection line that electrically connects a drain electrode of the first thin film transistor to a source electrode of the second thin film transistor, a third portion <NUM> of the connecting line for electrically connecting a drain electrode of the second thin film transistor to the peripheral circuit signal output lead <NUM> and an external connection joint <NUM>.

For example, locating the external connection joint <NUM> in the second zone <NUM> may be realized in the process of patterning the second metal layer <NUM>. For example, it may be electrically connected to source electrodes or drain electrodes of a plurality of thin film transistors in each row. It may also be used for connection to a controller outside of the gate driving circuit <NUM>, for example, it may be connected to a timing controller, or the like. The peripheral circuit layer <NUM> shown in <FIG> may be formed by using the above method, and it is realized that an internal connecting portion of the peripheral circuit is formed in the first zone <NUM> of the peripheral circuit region <NUM>, and the external connection joint <NUM> is disposed in the second zone <NUM> of the peripheral circuit region <NUM>, so as to make preparation for the subsequent formation of an external connection portion of the peripheral circuit in the second zone <NUM>. With the method provided by an embodiment of the present disclosure, it is possible that after a part of devices (such as a second plate of a capacitor and an external connection joint) of the peripheral circuit and connection pattern between devices are simultaneously formed with the second metal layer <NUM>, it is unnecessary to separately form a metal used to connect the devices after formation of devices of the peripheral circuit, which is beneficial to the simplification of the process. It is to be noted that number/amount of the external connection joints <NUM> shown in <FIG> is one, which is merely acts as an exemplary description, and amount of the external connection joints <NUM> may be multiple.

As shown in <FIG>, the method further includes forming an interlayer insulating layer <NUM> on the peripheral circuit layer <NUM>. The whole peripheral circuit <NUM> is disposed below the interlayer insulating layer <NUM>, that is, the interlayer insulating layer <NUM> covers the peripheral circuit <NUM>. For example, the interlayer insulating layer <NUM> covers the external connection joint <NUM>, the second plate <NUM> of the capacitor, and the connecting line, etc. In this way, a flat insulating layer can be formed on the peripheral circuit <NUM>. When a common electrode lead <NUM> is arranged on the interlayer insulating layer <NUM>, and a portion or even the entirety of the common electrode lead <NUM> overlaps with the peripheral circuit under the interlayer insulating layer <NUM>, the insulation of the common electrode lead <NUM> from the peripheral circuit <NUM> can be realized. Material of the interlayer insulating layer <NUM> may be the same as that of the first insulating layer <NUM>, which can refer to the above description. For example, the interlayer insulating layer <NUM> may be formed by a coating process, a deposition process, or the like.

As shown in <FIG>, a via hole <NUM> exposing the external connection joint <NUM> is formed in the interlayer insulating layer <NUM>. The specific method may refer to the above description about the method for forming the second via hole <NUM>.

As shown in <FIG>, a common electrode lead layer <NUM> is formed on the interlayer insulating layer <NUM>. Material of the common electrode lead layer <NUM> may, for example, be a transparent conductive material or an opaque conductive material. The transparent conductive material may be material, such as indium tin oxide (ITO), indium zinc oxide (IZO), or the like, and the opaque conductive material may, for example, be a metallic material, such as copper, aluminum, a copper alloy, or the like, with higher conductivity. The common electrode lead layer <NUM> may be formed by chemical vapor deposition, magnetron sputtering, or the like.

As shown in <FIG>, for example, the common electrode lead layer <NUM> may be patterned by a photolithographic process so as to form a common electrode lead <NUM> along at least part of the outer profile edge of the base substrate <NUM>. The orthographic projection of the common electrode lead <NUM> on the base substrate <NUM> coincides with a portion of the projection of an internal connected portion of the peripheral circuit <NUM> in the peripheral circuit region <NUM> on the base substrate <NUM>, that is, it overlaps with the internal connection portion of the peripheral circuit in the peripheral circuit region <NUM> in a direction perpendicular to the base substrate <NUM>. In this way, the width area occupied by the common electrode lead <NUM> alone in the non-working region <NUM> can be reduced in the array substrate obtained by using the method provided by an embodiment of the present disclosure, and the array substrate can have a narrower bezel. In this way, a narrower bezel can be achieved by a display device, an illuminating device, or the like, which adopt the array substrate. The saved space may be used to increase the width of a common electrode lead, so as to reduce the resistance of the common electrode lead.

In <FIG>, the interlayer insulating layer <NUM> is arranged between the peripheral circuit <NUM> and the common electrode lead <NUM>, and covers the peripheral circuit <NUM>, so that the peripheral circuit <NUM> and the common electrode lead <NUM> are insulated from each other. The external connection portion <NUM> of the peripheral circuit <NUM> includes an external connection joint <NUM> and an external connection lead <NUM>. The external connection lead <NUM> is formed while the common electrode lead <NUM> is formed by patterning the common electrode lead layer <NUM>, namely the external connection lead <NUM> of the peripheral circuit <NUM> and the common electrode lead <NUM> are formed by a same patterning process with a same mask. In this way, it is beneficial to the simplification of the fabricating process of the array substrate. The external connection lead <NUM> is electrically connected to the external connection joint <NUM> through the via hole <NUM>. In this way, the external connection joint <NUM> is formed in a second zone <NUM> of the peripheral circuit region that does not overlap with the common electrode lead <NUM> in a direction perpendicular to the base substrate <NUM>, so as to facilitate forming a via hole over the external connection joint <NUM> and arranging the external connection lead <NUM>. In this way, this process will not be hindered by the common electrode lead <NUM>.

As shown in <FIG>, a planarization layer <NUM> covering the base substrate <NUM> is formed. The specific formation method and material of the planarization layer 5may refer to conventional techniques in the field.

As shown in <FIG>, the planarization layer <NUM> is patterned to form an opening that exposes at least part of the common electrode lead <NUM>.

As shown in <FIG>, a pixel defining layer <NUM> is formed on the planarization layer <NUM> by photolithography. The pixel defining layer <NUM> has an opening.

As shown in <FIG>, a conductive layer <NUM> is formed on the planarization layer <NUM>. Material of the conductive layer <NUM> may be a transparent conductive material, or an opaque conductive material. The transparent conductive material may be material, such as indium tin oxide (ITO), or indium zinc oxide (IZO), or the like, and the opaque conductive material may, for example, be a metallic material, such as copper, aluminum, a copper alloy, an aluminum alloy, or the like. For example, the conductive layer <NUM> may be formed by chemical vapor deposition, magnetron sputtering, or the like. It is to be noted that material and specific production method of the conductive layer <NUM> are not limited to the above listed categories.

As shown in <FIG>, for example, the conductive layer <NUM> may be patterned by photolithography, to form a bridging conductive layer <NUM> and an anode <NUM> simultaneously. In other embodiment, the anode <NUM> formed in <FIG> may also be changed to be a cathode. Here, description will be made by taking the anode as an example. The anode <NUM> is located in the working region <NUM>, and in an opening of the pixel defining layer <NUM>. The bridging conductive layer <NUM> is formed in the peripheral circuit region <NUM>, and is insulated from the peripheral circuit <NUM> and extends across the peripheral circuit <NUM>. The bridging conductive layer <NUM> is electrically connected with the common electrode lead <NUM>. In the embodiment shown in <FIG>, one end of the bridging conductive layer <NUM> away from the working region <NUM> directly overlaps with the common electrode lead <NUM> to achieve electrical connection between the two. This direct overlapping is beneficial to the reduction of the contact resistance and is easy to be fabricated. The orthographic projection of the common electrode lead <NUM> on the base substrate <NUM> partially coincides with the orthographic projection of the peripheral circuit region <NUM> on the base substrate <NUM>. For example, the orthographic projection of the common electrode lead <NUM> on the base substrate <NUM> partially coincides with the orthographic projection of the peripheral circuit <NUM> on the base substrate <NUM>. That is, in a direction perpendicular to the base substrate <NUM>, a portion of the common electrode lead <NUM> coincides with a portion of the peripheral circuit <NUM>. For another example, the peripheral circuit <NUM> includes a plurality of circuit elements (such as thin film transistors, and leads, etc.) and a spacer zone interposed between the plurality of circuit elements, and the orthographic projection of the common electrode lead <NUM> on the base substrate <NUM> coincides with the orthographic projection of the spacer zone on the base substrate <NUM>.

As shown in <FIG>, for example, an organic light-emitting layer <NUM> may be formed on the anode <NUM> by a coating process or a deposition process. In other embodiment, it may be an electroluminescent layer (e.g., an organic electroluminescent layer).

As shown in <FIG>, a common electrode <NUM> is formed in the working region <NUM>. For example, the common electrode <NUM> may on the organic light-emitting layer <NUM> and the pixel defining layer <NUM>, and extend to the peripheral circuit region <NUM> and directly contact the bridging conductive layer <NUM> to achieve electrical connection between them. In this way, electrical connection between the common electrode <NUM> and the common electrode lead <NUM> is achieved through the bridging conductive layer <NUM>. That is, the bridging conductive layer <NUM> electrically connects the common electrode lead <NUM> with the common electrode <NUM>. An array substrate <NUM> as shown in <FIG> can be formed by the above method.

<FIG> is an enlarged schematic diagram of part <NUM> of the array substrate <NUM> in <FIG>. The enlarged schematic diagram exemplarily illustrates structure of the peripheral circuit <NUM>.

Embodiments of the present disclosure provide a display-substrate peripheral circuit structure, an array substrate and a method of manufacturing the same, and a display device, in which, a common electrode lead at least partially overlaps with and is insulated from a peripheral circuit region, so that the width area occupied by the common electrode lead alone in a non-working region can be reduced, and when the peripheral circuit structure is applied to the display device and so on, it is beneficial to the realization of a narrower bezel.

The foregoing is only the exemplary embodiments of the present disclosure and not intended to limit the scope of the present invention.

Claim 1:
A substrate, comprising
a base substrate (<NUM>), comprising a working region (<NUM>), a non-working region (<NUM>) outside of the working region (<NUM>) and an outer profile edge (<NUM>), the non-working region (<NUM>) including a peripheral circuit region (<NUM>) near the working region (<NUM>) and a non-circuit region away from the working region (<NUM>);
a peripheral circuit (<NUM>) in the peripheral circuit region (<NUM>);
a common electrode lead (<NUM>) in the non-working region (<NUM>);
a common electrode (<NUM>), wherein the common electrode (<NUM>) is electrically connected to the common electrode lead (<NUM>);
a bridging conductive layer (<NUM>), wherein the bridging conductive layer (<NUM>) is in the non-working region (<NUM>), and electrically connects the common electrode lead (<NUM>) with the common electrode (<NUM>);
and the common electrode lead (<NUM>) is insulated from the peripheral circuit (<NUM>); and the bridging conductive layer (<NUM>) is insulated from the peripheral circuit (<NUM>),
characterised in that:
an orthographic projection of the common electrode lead (<NUM>) on the base substrate (<NUM>) at least partially coincides with an orthographic projection of the peripheral circuit region (<NUM>) on the base substrate (<NUM>), and
an orthographic projection of the bridging conductive layer (<NUM>) on the base substrate (<NUM>) at least partially coincides with an orthographic projection of the peripheral circuit region (<NUM>) on the base substrate (<NUM>).