Patent Description:
In today's environment, solid state power controllers (SSPC) are used to control power that is supplied to a connected load. The SSPCs can control the voltage and/or current supplied to the load, and can provide protections to power systems by identifying overload conditions and preventing short circuits in the system. SSPCs provide optimal restoration time after a failure occurs and is no longer detected. The rapid restoration time returns the operation of mission-critical loads to the power systems after the failure has been resolved. Power system applications that use SSPCs include the power systems of aircrafts and vehicles. Fuses and fuse links have been used to provide protection in SSPCs for shorted field effect transistors (FET) or other failure modes. This configuration can provide a backup mode in the case of an overcurrent condition. The SSPCs also provide additional functionality and performance advantages over other protection components. For example, other protection components such as breakers and relays are limited in their usability when compared to the versatility of SSPCs. <CIT> and <CIT> both relate to protection circuits for power systems. <CIT> and <CIT> relate to detecting failure modes.

Disclosed is a system for eliminating secondary fuses in high power solid state power controllers defined in claim <NUM>.

Also disclosed is a method for eliminating secondary fuses in high power solid state power controllers defined in claim <NUM>.

Solid state power controllers (SSPC) provide a wide range of operability for different applications where the SSPCs can be used in both high power and low power applications. In the event of a field effect transistor (FET) short, the bond wires to each of the individual FETs will open. In high powered SSPCs, the bond wires have been known to open on a shorted FET during a normal load due to the higher current flowing through the wires. In a low power SSPCs, a shorted FET may not open into a steady state load which results in the channel connected to the load remaining in the ON state.

Currently, there is no protection for failure modes where the gate driver is shorted ON or when a primary controller malfunctions and commands the gate power to remain ON at all times. This is a problem being addressed by one or more embodiments described herein. The gate driver can be used to drive a FET array having a plurality of FETs. When the gate driver receives a command to power ON the FET array, the power can be supplied to each of the FETs. In the event, the gate driver is shorted ON, all of the devices of the FET array will be turned ON. This requires a very high fault current in order for each of the fuse links that are coupled to each FET in the FET array to open up. When all of the devices are turned ON, a very high fault current can occur which requires a larger fuse and/or fuse link to be used. This does not coordinate well with the wire when used in high power applications. As the size of the fuses get larger for high power system protection, the amount of board space that is used and the amount of heat dissipation from the fuses increases. This configuration will prove to be unworkable as high power applications are implemented. Also, if a secondary fuse is used for protecting the circuit, after the fuse opens, the channel connected to the load will be unavailable because of the opened fuse. In this example, the blown fuse must be replaced prior to restoring normal operation.

In the event a single FET is shorted in a large array, the shorted FET holds the channel in an ON state where the channel is coupled to a load. When the remaining FETs of the array are turned OFF, the remaining load current is funneled through the shorted FET. The increase in the current through the shorted FET causes the FET to open. The remaining FETs in the array and the channel that is coupled to the load are still functional. Upon restoring the gate power to the FET array, normal operation can resume. In this scenario, the secondary controller can detect the fault and switch the gate power OFF that is supplied to the remaining FETs in the array. However, if a single secondary fuse were to be used and the fuse opened, the channel would not be operational after the fuse has blown open. In the previously described configuration, the individual FETs of the FET array act as fuses without requiring a large secondary fuse to be incorporated into the system.

In one or more embodiments, the secondary controller can determine a fault based on the current state of the system and disable the gate driver when the secondary controller detects a fault condition. The secondary controller is configured to prevent a gate from being stuck on, which is controlled by the primary controller.

Now referring to <FIG>, a prior art system <NUM> incorporating secondary fuses <NUM> is shown. As shown, the system <NUM> includes a primary controller <NUM>. The primary controller <NUM> is configured to receive system commands <NUM> from a source for controlling the gate driver <NUM>. The primary controller <NUM> controls the gate driver <NUM> through a primary control signal <NUM>. The primary controller <NUM> is also configured to receive a load voltage signal <NUM> and load current <NUM> from a current sensor amplifier <NUM> and a sensor <NUM>. The combination of these signals can indicate the current state of the system <NUM>.

The gate driver <NUM> receives power from a gate power supply <NUM> being which receives power form a control supply <NUM>. The gate driver <NUM> is coupled to the FET array <NUM>. The FET array <NUM> can be comprised of a plurality of FETs. In an embodiment, the FETs can be any known type of transistor, device, switch, etc. The FET array <NUM> receives a feed signal <NUM> which can be provided to the load <NUM>.

In the event of a failure along with an overcurrent fault, the fuse <NUM> can open to disconnect the channel coupling the load <NUM> in the system <NUM>. However, after the fuse <NUM> has opened the channel that is connected to the load <NUM> is unavailable. In high power applications, the system <NUM> requires larger fuses <NUM> to be used to provide the overload protection. The larger the fuses <NUM> become, the higher the heat dissipation becomes that is associated with the fuse <NUM>.

Now referring to <FIG>, a system <NUM> for eliminating secondary fuses in a high power SSPC in accordance with one or more embodiments is shown. As shown in <FIG>, a secondary controller <NUM> and gate switch <NUM> is integrated into the system <NUM>. The primary controller <NUM> and the secondary controller <NUM> can be solid state power controllers. In one or more embodiments, the secondary controller <NUM> is configured to receive the same system command signals <NUM> as the primary controller <NUM>. In addition, the secondary controller <NUM> is configured to receive a load voltage signal <NUM> and the load current signal <NUM> from at least one connected load <NUM>. In one or more embodiments, the secondary fuse <NUM> (shown in <FIG>) is eliminated from the system <NUM>. The overload protection is provided by the secondary controller <NUM> and the gate switch <NUM>. The gate power can be detected by the secondary controller <NUM> through the signal <NUM>. The configuration of the FETs in the FET array <NUM> can affect the power system overload protection operation. In a non-limiting example, smaller FETs can be used in the FET array <NUM> to increase the channel availability during a failure mode caused by an FET of the FET array <NUM> having short circuited. After the gate power is removed from the remaining FETs of the FET array <NUM>, under control of the secondary controller <NUM>, the shorted FET will open and the channel will still be operational after power is restored to the remaining FETs.

The secondary controller <NUM> controls the gate switch <NUM> based on detecting a fault or failure mode in the system <NUM>. In the event a failure is detected by the secondary controller <NUM>, the secondary controller <NUM> can provide a signal <NUM> to the gate switch <NUM> to disable the gate power supplied to the gate driver <NUM>. The signal <NUM> can also be used to enable the gate switch <NUM> to allow the gate power to be provided to the gate driver <NUM>.

The secondary controller <NUM> is configured to receive the command signals <NUM> so the secondary controller <NUM> will know when the FET array <NUM> is to be powered ON and when the FET array <NUM> is to be powered OFF. For example, the secondary controller <NUM> will be able to detect a fault in the event the FET array <NUM> is receiving gate power when in an OFF state.

In one or more embodiments, the gate switch <NUM> can be located in different positions relative to the gate power supply <NUM>. In an embodiment, the gate switch <NUM> can be located between the control supply <NUM> and upstream of the gate power supply <NUM>. In a different embodiment, the gate switch <NUM> can be located between the gate power supply <NUM> and upstream of the gate driver <NUM>. In one or more of the configurations, the gate switch <NUM> is coupled and controlled by the secondary controller <NUM>. In the event a failure mode is detected, the secondary controller <NUM> opens the gate switch <NUM> to disable the gate power from being provided to the FET driver <NUM> and FET array <NUM> until the failure mode has been resolved. In a different embodiment, the gate power supply <NUM> can include an enable line to control the gate power where the enable line is controlled by the secondary controller <NUM>.

In another embodiment, a FET in the FET array <NUM> can open during a failure mode which protects the system from the overload condition. After this FET blows open, the other FETs and channel coupled to the load will remain operational even though the single FET is open. This availability cannot be realized when using a single large secondary fuse. In this configuration, the FETs themselves become the fuse, and once opened the channel is operational again less the one opened FET in the array <NUM>. The techniques described herein avoid the use of secondary fuses for implementing circuit protection from overcurrent that may occur in the system.

Now referring to <FIG>, a system <NUM> for eliminating secondary fuses in high power SSPCs in accordance with one or more embodiments is shown. In the configuration shown in <FIG>, the secondary controller <NUM> is coupled to the primary controller <NUM> and is configured to receive a watchdog signal <NUM>. A watchdog signal is a timer that is used to detect computer malfunctions. During normal operation, the watchdog signal is regularly pulsed to prevent it from elapsing or "timing out.

In the event that a failure in the primary controller <NUM> is detected, the secondary controller <NUM> provides a signal <NUM> to the gate switch <NUM> to remove the gate power being supplied to the FET array <NUM>. In one or more embodiments, the configurations of <FIG> can include the use of a watchdog signal <NUM>.

Now referring to <FIG>, a method <NUM> for eliminating the use of secondary fuses in SSPCs in accordance with one or more embodiment is shown. Block <NUM> provides controlling gate power provided to a FET array. In one or more embodiment, the secondary controller can control the gate power by controlling a gate switch that is coupled to a gate driver that provides the gate power to the FET array.

Block <NUM> provides detecting a failure mode. In one or more embodiments, a secondary controller can be used to detect a failure mode of the system. A non-limiting example of the failure mode is based on the failure or malfunctioning of a gate power supply. Another non-limiting example of a failure mode is a failed FET in the FET array which couples a feed signal to a load. In another embodiment, the secondary controller can compare the current state of the system with the configured state of the system based on receiving common signals the primary controller receives such as the command signal, load current, load voltage, etc..

Block <NUM> provides disabling the gate power based at least in part on detecting the failure mode. In an embodiment, the secondary controller disables the gate power that is provided to the FET array upon detection of the failure mode and during the failure mode. Block <NUM> provides restoring the gate power responsive to resolving the failure mode.

In one or more embodiments, the elimination of any secondary protection fuse components reduces the board space taken for providing overload protection particularly in high power applications that require larger fuses for protection. Because the large secondary fuses are eliminated from the circuit, the heat dissipation associated with large secondary fuses is also removed. In addition, the higher availability of the channel is maintained by allowing the individual FETS of large FET arrays to clear their own faults while the other FETs and channels remain viable to complete the mission.

Claim 1:
A system for eliminating secondary fuses in high power solid state power controllers, the system comprises:
a field effect transistor, FET, array (<NUM>), wherein the FET array (<NUM>) includes a plurality of FETs, wherein a channel coupling the system to a load is configured to remain operational after a FET of the plurality of FETs has blown open;
a gate driver (<NUM>) coupled to the FET array (<NUM>);
a gate switch power supply (<NUM>);
a gate switch (<NUM>) coupled between the gate switch power supply (<NUM>) and the gate driver (<NUM>);
a primary controller (<NUM>) coupled to the gate driver (<NUM>), and
a secondary controller (<NUM>), coupled to between the gate switch (<NUM>) and the gate driver (<NUM>), configured to monitor the power coming from the gate switch power supply (<NUM>) and going through the gate switch (<NUM>) in order to detect a failure mode; wherein the secondary controller (<NUM>) is configured to control the gate switch (<NUM>) to enable or disable power from the gate switch power supply (<NUM>) to the gate driver (<NUM>), wherein the primary controller (<NUM>) and the secondary controller (<NUM>) are configured to receive common signals for controlling the FET array (<NUM>),
wherein the secondary controller (<NUM>) is configured to disable power to the gate driver based at least in part on detecting the failure mode; and
wherein the secondary controller (<NUM>) is further configured to restore the gate power responsive to resolving the failure mode.