Patent Description:
With the rapid development of manufacturing technologies of a modern large-scale integrated circuit, a size of an integrated component within a chip is also continuously reduced, with a quantum effect becoming increasingly non-negligible. In many solutions to the failure crisis of Moore's law, a quantum processor (also referred to as a quantum chip) designed based on principles of quantum mechanics has become an important layout and vital interest in the scientific and technological fields in various countries in the world due to its breakthrough performance improvement and excellent quantum algorithm applications (for example, performing current classic computer key assignment, cracking, and the like).

Compared with a classical integrated circuit chip that constructs classical bits by means of one transistor, the quantum chip constructs qubits by using different physical systems, for example, a superconducting quantum chip uses a Josephson junction to implement a two-level system, and a semiconductor quantum dot uses electric field bound quantum dots to implement a two-level system. The superconducting quantum chip based on a Josephson junction has advantages such as good scalability and high gate-operation fidelity, and thus is one of the most promising systems for implementing quantum computing.

The larger a quantity of qubits on a superconducting quantum chip, the stronger the computing power of a quantum computer. However, integration of qubits and corresponding signal transmission lines on a surface of a substrate having a limited area makes it difficult to expand the quantity of qubits.

DONNA-RUTH WYOST ET AL discloses a 3D quantum chip structure. The SMCM (superconducting multichip module) is at the bottom layer. The SMCM contains circuits for signal routing and qubit control and measurement. The qubit chip in the upper layer is provided with qubits, and the qubits are provided on a silicon wafer.

<CIT> discloses a vertical distributed quantum bit reading device, including a first substrate having a first surface and a second surface. A readout pad is provided on the first surface and a readout resonator is provided on the second surface; and a second substrate is connected to the first substrate and quantum bits are arranged thereon.

<CIT> discloses quantum bit (qubit) circuits, coupler circuit structures and coupling techniques. Such circuits and techniques may be used to provide multi-qubit circuits suitable for use in multichip modules (MCMs).

The present application provides a quantum chip and a fabrication method thereof, to solve a problem in the related technologies that qubits on a quantum chip are difficult to expand. According to the quantum chip and the fabrication method thereof provided in the present application, signal transmission lines and a qubit can be formed on different circuit layers to implement an electrical connection, thereby improving an integration degree of a quantum chip.

The present application provides a quantum chip according to claim <NUM>. Further implementations are provided according to dependent claims <NUM>-<NUM>.

The application further provides a fabrication method for a quantum chip according to claims <NUM> and <NUM>.

Compared with the related technologies, the quantum chip of the present application includes: a base substrate on which signal transmission lines are formed; and at least one insulating substrate located on the base substrate, and an isolation layer between the at least one insulating substrate and the base substrate,
where a qubit and a through hole penetrating through the insulating substrate and the isolation layer are formed on the insulating substrate, a metal piece is formed in the through hole, and two ends of the metal piece are electrically connected to the signal transmission lines and the qubit, respectively. In the present application, the signal transmission lines and the qubit are respectively formed on the base substrate and the insulating substrate, and the through hole penetrating through the insulating substrate and the metal piece located in the through hole are formed. The signal transmission lines on the base substrate and the qubit on the insulating substrate are electrically connected by means of the metal piece, so that signal transmission is implemented between the signal transmission lines and the qubit, forming a complete qubit circuit located on different layers. In addition, a plurality of insulating substrates may be stacked to form qubits located on different layers, thereby jointly forming a quantum chip in which a quantity of qubits is easy to expand. In this way, an integration degree of the quantum chip is improved.

Reference signs are as follows:
<NUM>. base substrate, <NUM>. signal terminal, <NUM>. signal transmission line, <NUM>. qubit control signal line, <NUM>. qubit microwave resonant cavity, <NUM>. qubit read signal line, <NUM>. insulating substrate, <NUM>. first insulating substrate, <NUM>. second insulating substrate, <NUM>. qubit, <NUM>. first qubit, <NUM>. second qubit, <NUM>. loop superconducting circuit, <NUM>. capacitor, <NUM>. through hole, <NUM>. control signal line through hole, <NUM>. read signal line through hole, <NUM>. metal piece, <NUM>. isolation layer, <NUM>. insulating isolation layer, <NUM>. via hole, and <NUM>. metal isolation layer.

The embodiments described below with reference to the accompanying drawings are exemplary and merely used to explain the present application, but cannot be understood as a limitation on the present application.

To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following describes the embodiments of the present application in detail with reference to the accompanying drawings. However, a person of ordinary skill in the art may understand that many technical details are put forward in the embodiments of the present application to make a reader better understand the present application. However, even without the technical details and various changes and modifications on a basis of the following embodiments, the technical solutions claimed in the present application may be implemented. The division of the following embodiments is for convenience of description, and should not constitute any limitation on the specific implementations of the present application, and various embodiments may be mutually referenced on the premise of no contradiction.

It should be noted that the terms "first", "second" and the like in this specification, claims, and drawings of the present application are used to distinguish between similar objects, rather than to describe a particular order or a sequential order. It should be understood that the data used in this way may be interchangeable under appropriate circumstances such that embodiments of the present application described herein are capable of being implemented in an order different from that illustrated or described herein. In addition, the terms "include" and "have" and any other variants thereof are intended to cover the non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those expressly listed steps or units, but may include other steps or units not expressly listed or inherent to such process, method, product, or device.

In addition, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it may be directly on another layer or substrate, and/or there may be an insertion layer. In addition, it should be understood that when a layer is referred to as being "under" another layer, it may be directly under another layer, and/or there may be one or more insertion layers. In addition, for "on" a layer and "under" a layer, reference may be made to the figures.

The solutions proposed in the present application are intended to solve a problem that it is difficult to expand a quantity of qubits because at present a manner of integrating qubits and corresponding signal transmission lines on a surface of a substrate having a limited area is used.

A quantum chip structure shown in <FIG> is a structural diagram designed by the applicant according to the related technologies for forming six qubits <NUM> and corresponding signal transmission lines <NUM> on a surface of a two-dimensional substrate. It may be seen from the figure that the six qubits <NUM> occupy a few structural dimensions on the surface of the substrate, and most of surface structures are occupied by the signal transmission lines <NUM>. In addition, due to the physical structure of the qubits <NUM>, wiring of the signal transmission lines <NUM> may be limited. It is contemplated that if more bits of qubits <NUM> need to be integrated on the surface of the two-dimensional substrate, the integration may be very difficult due to size limitation of a chip, making it difficult to extend the quantity of qubits <NUM>. Through research and experiments of the inventors, a novel quantum chip structure that facilitates extension of a quantity of qubits <NUM> is proposed.

Some embodiments of the present application provide a quantum chip.

<FIG> is a schematic structural diagram of an exemplary quantum chip not forming part of the present invention.

With reference to <FIG>, a quantum chip provided in an embodiment of the present application may include: a base substrate <NUM> on which signal transmission lines <NUM> are formed; and at least one insulating substrate <NUM>, where the at least one insulating substrate <NUM> is located on the base substrate <NUM>, a qubit <NUM> and a through hole <NUM> penetrating through the insulating substrate <NUM> are formed on the insulating substrate <NUM>, a metal piece <NUM> is formed in the through hole <NUM>, and two ends of the metal piece <NUM> are electrically connected to the signal transmission lines <NUM> and the qubit <NUM>, respectively.

In particular, the base substrate <NUM> may include a substrate in the field of semiconductor chips, for example, a sapphire substrate, a silicon substrate, a silicon carbide substrate, or a gallium nitride substrate. In the present application, a silicon carbide substrate is preferably selected as the base substrate <NUM>, so that a quantum chip formed easily has a good thermal conductivity, thereby greatly reducing thermal power consumption during operation of the quantum chip, and making thermal power consumption and thermal radiation in a quantum computing system including the quantum chip reduced.

In addition, the signal transmission lines <NUM> for regulating and controlling the qubit <NUM> are all integrated on the base substrate <NUM>, and the qubit <NUM> is formed on another insulating substrate <NUM>, so that regulation and control of the connected qubit <NUM> by a signal on the signal transmission lines <NUM> are more accurate, and a crosstalk impact on another qubit <NUM> may be reduced.

For a process of forming the signal transmission lines <NUM> on the base substrate <NUM>, reference may be made to a semiconductor chip fabrication process in the related technologies as follows: first, forming a metal layer on a surface of the base substrate <NUM> by using an evaporation method, atomic deposition method, and the like; and then performing patterning, exposing, developing, and etching on the metal layer to form desired signal transmission lines <NUM>. A more detailed process is not described again in the embodiment of the present application.

After the signal transmission lines <NUM> for regulating and controlling the qubit <NUM> is formed on the base substrate <NUM>, a layer of insulating substrate <NUM> for arrangement of a circuit structure of the qubit <NUM> is formed on the base substrate <NUM>. The insulating substrate <NUM> may be formed on the base substrate <NUM> by separately processing the insulating substrate <NUM> and grafting the insulating substrate <NUM> onto the base substrate <NUM>, or may be formed directly on the base substrate <NUM> by using an atomic deposition process or a sputtering process. In the present application, the second method is used, that is, the insulating substrate <NUM> is formed on the base substrate <NUM> by using a sputtering process. Additionally, the signal transmission lines <NUM> are formed on a surface of the base substrate <NUM>, and the insulating substrate <NUM> formed on the base substrate <NUM> covers a surface of the signal transmission lines <NUM>, so as to isolate the signal transmission lines <NUM> from a circuit structure of the qubit <NUM>, thereby achieving insulation and isolation functions.

Therefore, after the insulating substrate <NUM> on the surface of the signal transmission lines <NUM> is formed, the circuit structure of the qubit <NUM> may be formed on the surface of the insulating substrate <NUM>. Certainly, the circuit structure of the qubit <NUM> formed in this case is disconnected from the signal transmission lines <NUM>. Before the circuit structure of the qubit <NUM> is formed, a through hole <NUM> penetrating through the insulating substrate <NUM> needs to be formed on the insulating substrate <NUM>, and a metal piece <NUM> is filled in the through hole <NUM>; therefore, the signal transmission lines <NUM> and the qubit <NUM> may be electrically connected by means of the metal piece <NUM>. The circuit structure of the qubit <NUM> may be formed on the surface of the insulating substrate <NUM> after the through hole <NUM> and the metal piece <NUM> located in the through hole <NUM> are prepared on the insulating substrate <NUM>.

The formed circuit structure of the qubit <NUM> is electrically connected to one end of the metal piece <NUM>, and the other end of the metal piece <NUM> is electrically connected to the signal transmission lines <NUM> on the base substrate <NUM>. In this way, the circuit structure of the qubit <NUM> and the signal transmission lines <NUM> are electrically connected by means of the metal piece <NUM>, so that signal transmission is implemented between the signal transmission lines <NUM> and the qubit <NUM>, constructing a complete circuit structure of the qubit <NUM>.

Compared with the related technologies, in the present example, the signal transmission lines <NUM> and the qubit <NUM> are respectively formed on the base substrate <NUM> and the insulating substrate <NUM>, the through hole <NUM> penetrating through the insulating substrate <NUM> and the metal piece <NUM> located in the through hole <NUM> are formed, and then the signal transmission lines <NUM> on the base substrate <NUM> and the qubit <NUM> on the insulating substrate <NUM> are electrically connected by means of the metal piece <NUM>, so that signal transmission is implemented between the signal transmission lines <NUM> and the qubit <NUM>, forming a complete qubit circuit located on different layers. In addition, a plurality of insulating substrates <NUM> that are stacked may be used for forming qubits <NUM> located on insulating substrates <NUM> in different layers, thereby expanding a quantity of the qubits <NUM> to an enough amount. In this way, an integration degree of a quantum chip is improved.

For example, as shown in <FIG>, the signal transmission lines <NUM> provided in the example not forming part of the present invention include: a qubit control signal line <NUM> coupled to the qubit <NUM>, where the qubit control signal line <NUM> is configured to regulate and control information of the qubit <NUM>; a qubit microwave resonant cavity <NUM> coupled to the qubit <NUM>, where the qubit microwave resonant cavity <NUM> is configured to read information of the qubit <NUM>; and a qubit read signal line <NUM> coupled to the qubit microwave resonant cavity <NUM>, where the qubit read signal line <NUM> is configured to read information output by the qubit microwave resonant cavity <NUM>.

In the field of quantum computing, a quantum chip running quantum computing integrates a plurality of computing units (namely, qubits <NUM>), and each qubit <NUM> is a two-level system. Transition frequency and transition energy of an energy level system of each qubit <NUM> are both regulated and controlled by using an applied regulation signal, for example, the transition frequency of the qubit <NUM> is regulated and controlled by applying a direct-current bias signal and the transition energy of the qubit <NUM> is regulated and controlled by applying a microwave signal. Therefore, each qubit <NUM> needs to be provided with a corresponding qubit control signal line <NUM>, and the qubit control signal line <NUM> is configured to transmit an applied regulation and control signal to the qubit <NUM>. In addition, in order to read information of a regulated and controlled qubit <NUM>, a corresponding qubit read signal line <NUM> further needs to be disposed to read the qubit <NUM>. Since response sensitivity of the qubit <NUM> to a signal is very high, the qubit <NUM> cannot be read directly through the qubit read signal line <NUM>, and need to be read indirectly by means of the qubit microwave resonant cavity <NUM>, and then information of the qubit <NUM> fed back through the qubit microwave resonant cavity <NUM> is read through the qubit read signal line <NUM>.

For example, as shown in <FIG>, the qubit microwave resonant cavity <NUM> provided in the example includes a coplanar waveguide transmission line. The qubit microwave resonant cavity <NUM> is formed on the base substrate <NUM> and a form of a coplanar waveguide transmission line is used, which is easy to prepare, and compared with the form of microstrip transmission lines, less crosstalk occurs between signals transmitted on the coplanar waveguide transmission lines.

As shown in <FIG>, according to the invention, the quantum chip provided in the embodiment of the present application further includes an isolation layer <NUM>, where the isolation layer <NUM> is located between the base substrate <NUM> and the insulating substrate <NUM>, and the through hole <NUM> penetrates through the isolation layer <NUM>.

The embodiment of the present application provides a quantum chip structure, that is, a layer of isolation layer <NUM> is formed between the base substrate <NUM> and the insulating substrate <NUM>. In order to ensure that electrical connection can be implemented between the signal transmission lines <NUM> on the base substrate <NUM> and the qubit <NUM> on the insulating substrate <NUM>, the through hole <NUM> also needs to penetrate through the formed isolation layer <NUM>, that is, the through hole <NUM> penetrates through the insulating substrate <NUM> and the isolation layer <NUM>. In addition, the metal piece <NUM> is formed in the through hole <NUM>, and two ends of the metal piece <NUM> are respectively electrically connected to the signal transmission lines <NUM> on the base substrate <NUM> and the qubit <NUM> on the insulating substrate <NUM>. In this way, signal transmission between the signal transmission lines <NUM> and the qubit <NUM> is implemented.

During specific implementation and test, the applicant finds that, when an isolation layer <NUM> is formed between the base substrate <NUM> and the insulating substrate <NUM>, an isolation effect between the signal transmission lines <NUM> on the base substrate <NUM> and the qubit <NUM> on the insulating substrate <NUM> may be improved, so that there is less crosstalk impact of a signal transmitted on the signal transmission lines <NUM> on another qubit <NUM>. For example, the isolation layer <NUM> provided in the embodiment of the present application may include: an insulating isolation layer <NUM> located on the base substrate <NUM>, where the insulating isolation layer <NUM> covers the signal transmission lines <NUM>, and the through hole <NUM> penetrates through the insulating isolation layer <NUM>; and a metal isolation layer <NUM> located on the insulating isolation layer <NUM>, where a via hole <NUM> for forming a mesh is formed in the metal isolation layer <NUM>, and the through hole <NUM> is located in the via hole <NUM> for forming a mesh.

In the embodiment of the present application, the metal isolation layer <NUM> is used, and the metal isolation layer <NUM> is disposed between the base substrate <NUM> and the insulating substrate <NUM>, so that there has a good isolation effect between the signal transmission lines <NUM> on the base substrate <NUM> and the qubit <NUM> on the insulating substrate <NUM>. Specifically, a material of the metal isolation layer <NUM> includes one of copper, aluminum, gold, and niobium or a metal or an alloy of another material, as long as an effect of isolation can be achieved. In a specific implementation of the present application, copper is preferably selected, because copper has a low cost and a simple fabrication process.

In addition, the metal isolation layer <NUM> not only is located on the base substrate <NUM>, but also covers the signal transmission lines <NUM> and contacts the signal transmission lines <NUM>. If the metal isolation layer <NUM> is directly formed on the signal transmission lines <NUM>, a short circuit may be caused between the metal isolation layer <NUM> and the signal transmission lines <NUM>. Therefore, an insulating isolation layer <NUM> needs to be further disposed between the metal isolation layer <NUM> and the signal transmission lines <NUM>, and the insulating isolation layer <NUM> is configured to protect the signal transmission lines <NUM> from being short circuited by the metal isolation layer <NUM>. In addition, the insulating substrate <NUM> is formed on an upper surface of the metal isolation layer <NUM>, and because the insulating substrate <NUM> is made of an insulating material, the qubit <NUM> formed on the insulating substrate <NUM> is not affected. A material of the insulating isolation layer <NUM> includes one of silicon dioxide, amorphous silicon and Teflon. In a specific implementation of the present application, silicon dioxide is preferably used, because silicon dioxide has a simple fabrication process.

Additionally, the through hole <NUM> also needs to be formed in the insulating isolation layer <NUM> and the metal isolation layer <NUM> that are formed between the base substrate <NUM> and the insulating substrate <NUM>. In addition, because the metal isolation layer <NUM> is a metal isolation layer, a via hole <NUM> for forming a mesh with an aperture greater than that of the through hole <NUM> needs to be further formed on the metal isolation layer <NUM>. Furthermore, the via hole <NUM> for forming a mesh and the through hole <NUM> are coaxially disposed, so that the through hole <NUM> is located in the via hole '<NUM> for forming a mesh. That is to say, a coverage region of the through hole <NUM> is allowed to be located within a coverage region of the via hole <NUM> for forming a mesh, so as to ensure that there is no short circuit between the metal isolation layer <NUM> and the metal piece <NUM> in the through hole <NUM> penetrating through the metal isolation layer <NUM>.

As shown in <FIG>, an embodiment of the present application provides a structure in which a via hole <NUM> for forming a mesh is formed in a metal isolation layer <NUM>. To form the via hole <NUM> for forming a mesh in the metal isolation layer <NUM>, a metal layer may be first formed on an insulating isolation layer <NUM>, and then the via hole <NUM> for forming a mesh is formed by using an etching process. A position of the via hole <NUM> for forming a mesh needs to be set based on a position of the through hole <NUM>, so as to ensure that the through hole <NUM> penetrating through the insulating substrate <NUM>, the insulating isolation layer <NUM>, and the metal isolation layer <NUM> is located inside the via hole <NUM> for forming a mesh. That is to say, a coverage region of the through hole <NUM> is allowed to be located within a coverage area of the via hole <NUM> for forming a mesh, to ensure that after the metal piece <NUM> in the through hole <NUM> electrically connects the signal transmission lines <NUM> on the base substrate <NUM> and the qubit <NUM> on the insulating substrate <NUM>, there is no short circuit between the metal piece <NUM> and the metal isolation layer <NUM>.

The hole of the metal isolation layer <NUM> shown in <FIG> is a structure of the via hole <NUM> for forming a mesh. In addition, the via hole <NUM> for forming a mesh may also have a variety of hole-like structures, such as strip-shaped holes shown in <FIG>, <FIG>, and <FIG>, so long as a hole in the metal isolation layer <NUM> can surround the through hole <NUM>, and ensure that there is no short circuit between the metal isolation layer <NUM> and the metal piece <NUM> in the through hole <NUM>.

As shown in <FIG>, for example, the at least one insulating substrate provided in the embodiment of the present application may include a first insulating substrate <NUM> and a second insulating substrate <NUM>. The first insulating substrate <NUM> is located on the base substrate <NUM>, a first qubit <NUM> and a through hole <NUM> are formed on the first insulating substrate <NUM>, the through hole <NUM> penetrates through the first insulating substrate <NUM>, a metal piece <NUM> is formed in the through hole <NUM>, and two ends of the metal piece <NUM> are electrically connected to the signal transmission lines <NUM> and the first qubit <NUM>, respectively, so as to implement signal transmission between the signal transmission lines <NUM> and the first qubit <NUM>. The second insulating substrate <NUM> is located on the first insulating substrate <NUM>, a second qubit <NUM> and a through hole <NUM> are formed on the second insulating substrate <NUM>, the through hole <NUM> penetrates through the second insulating substrate <NUM>, a metal piece <NUM> is formed in the through hole <NUM>, and two ends of the metal piece <NUM> are electrically connected to the signal transmission lines <NUM> and the second qubit <NUM>, respectively, so as to implement signal transmission between the signal transmission lines <NUM> and the second qubit <NUM>.

Specifically, a structure in which a plurality of layers of insulating substrates <NUM> are stacked may be used, for example, when there are a plurality of qubits <NUM> for a superconducting quantum chip and it is difficult to integrate circuit structures of the plurality of qubits <NUM> on one layer of insulating substrate <NUM>, a plurality of layers of insulating substrates <NUM> that are stacked may be formed, and a circuit structure of a qubit <NUM> may be formed on a surface of each insulating substrate <NUM>. In addition, a through hole <NUM> penetrating through the insulating substrate <NUM> needs to be formed in each insulating substrate <NUM> in the plurality of layers of insulating substrates <NUM>, and a metal piece <NUM> is formed in the through hole <NUM>, so that all circuits of the qubits <NUM> on the surface of the plurality of layers of insulating substrates <NUM> are electrically connected to the signal transmission lines <NUM> on the base substrate <NUM> by means of the metal piece <NUM>.

The first insulating substrate <NUM> and the second insulating substrate <NUM> described in the embodiment of the present application are merely examples, and a third insulating substrate, a fourth insulating substrate, and more insulating substrates may be further formed on the second insulating substrate <NUM>. A through hole <NUM> penetrating through each layer of the insulating substrate <NUM> needs to be formed in each layer of the insulating substrate <NUM> and a metal piece <NUM> needs to be formed in the through hole <NUM>. The circuit structures of the qubits <NUM> may be arranged by forming a plurality of layers of stacked insulating substrates <NUM>, an integration degree of the qubits <NUM> on the quantum chip may be greatly improved; and a same process is used in a fabrication process, facilitating production and fabrication.

As an example, <FIG> is a diagram of a circuit structure of the first qubit <NUM> on a surface of the first insulating substrate <NUM>, and <FIG> shows a diagram of a circuit structure of the second qubit <NUM> on a surface of the second insulating substrate <NUM>, where a corresponding structural diagram of the base substrate <NUM> is shown in <FIG>. Specifically, two through holes <NUM>, namely, control signal line through holes <NUM>, are formed beside the circuit structure of each of the first qubit <NUM> and the second qubit <NUM> respectively on the first insulating substrate <NUM> and the second insulating substrate <NUM>. A metal piece <NUM> is formed in each of the through holes <NUM> for electrically connecting the qubit control signal line <NUM>, and the metal piece <NUM> is configured to transmit signals for controlling transition frequency and transition energy of an energy level system of a qubit <NUM> to the qubit <NUM>. In addition, a through hole <NUM>, namely, a read signal line through hole <NUM>, is formed at an end away from the structure of the qubit <NUM>. The qubit <NUM> is electrically connected to a qubit microwave resonant cavity <NUM> located on the base substrate <NUM> by means of the metal piece <NUM> in the through hole <NUM>, thereby transmitting information of the qubit <NUM> to the read signal line through hole <NUM>.

Referring to the circuit diagram of the signal transmission lines <NUM> on the surface of the base substrate <NUM> in <FIG>, each qubit <NUM> is at least paired to form at least two control signal line through holes <NUM> and one read signal line through hole <NUM>, and a metal piece <NUM> in each of the three through holes <NUM> is electrically connected to a corresponding qubit <NUM>.

For example, the metal piece <NUM> provided in the embodiment of the present application fully fills the through hole <NUM>. The metal piece <NUM> is formed in the through hole <NUM> for implementing electrical connection between the base substrate <NUM> and a circuit structure on the insulating substrate <NUM>. In a specific fabrication process, a metal piece <NUM> in a shape of a metal film may be formed on the inner surface of the through hole <NUM> by sputtering, or a metal piece <NUM> in a columnar shape may be formed inside the through hole <NUM>. In the present application, during implementation, the metal piece <NUM> in a columnar shape is used, so as to avoid that the formed through hole <NUM> and a metal layer formed by sputtering on the surface of the through hole <NUM> are uneven and have a high roughness, thereby affecting transmitted control signals. The metal piece <NUM> in a columnar shape may be formed by fully filling the through hole <NUM>.

As shown in <FIG>, <FIG>, for example, a capacitor <NUM> for connecting the qubit <NUM> and the metal piece <NUM> is formed on the insulating substrate <NUM> provided in the embodiment of the present application, and adjacent qubits <NUM> are also coupled through the capacitor <NUM>. The qubit <NUM> is coupled to the qubit microwave resonant cavity <NUM>, and the qubit microwave resonant cavity <NUM> is directly electrically connected to the metal piece <NUM>, so that a capacitor <NUM> is provided between the qubit <NUM> and the metal piece <NUM>, and a coupling effect also exists between two adjacent qubits <NUM>, so that a capacitor <NUM> of a cross shape is formed. A first end of the capacitor <NUM> of a cross shape is directly electrically connected to the qubit <NUM>, and a second end of the capacitor <NUM> is coupled to a metal piece <NUM> in the through hole <NUM> and then electrically connected to the qubit microwave resonant cavity <NUM>. A third end and a fourth end of the capacitor <NUM> are respectively coupled to adjacent qubits <NUM>, so as to realize coupling with the adjacent qubits <NUM>.

As shown in <FIG>, for example, when the quantum chip of the present application is a superconducting quantum chip, a qubit <NUM> may include a loop superconducting circuit <NUM> and the capacitor <NUM>. The qubit <NUM> on the quantum chip is a two-level system formed by a non-linear inductor and a resonant capacitor. The non-linear inductor is a loop superconducting circuit <NUM> connected in parallel, and the resonant capacitor is also formed based on the capacitor <NUM>, that is, the capacitor is formed by both cross transmission lines in the middle connected to the loop superconducting circuit <NUM> and surrounding ground (corresponding "ground" on the insulating substrate <NUM>) in <FIG>. Additionally, the metal piece <NUM> that is in the through hole <NUM> and connects the qubit <NUM> is connected to the loop superconducting circuit <NUM>. A two-level resonator system equivalent to an LC resonance (classical resonant circuit) is formed by the loop superconducting circuit <NUM> and the resonant capacitor, and then the two-level resonant system is regulated and controlled by receiving, through the metal piece <NUM> connected to the loop superconducting circuit <NUM>, a control signal transmitted on the signal transmission lines <NUM> located on the base substrate <NUM>. A structure of a qubit includes, but is not limited to, the structure of the loop superconducting circuit <NUM> and the capacitor <NUM> in this embodiment.

For example, the loop superconducting circuit <NUM> provided in the embodiment of the present application includes at least two superconducting Josephson junctions connected in parallel. The loop superconducting circuit <NUM> functions as the non-linear inductor in the two-level resonant system, and the loop superconducting circuit <NUM> is regulated and controlled by a control signal obtained by mean of the metal piece <NUM> and applied to the signal transmission lines <NUM>, specifically by applying a control signal causing a change in magnetic flux. That is, the loop superconducting circuit <NUM> is formed as a closed loop formed by at least two superconducting Josephson junctions connected in parallel, and the closed loop induces a change in the magnetic flux (the change in the magnetic flux is controlled and regulated by a bias voltage applied to the signal transmission lines <NUM>), so that a parameter of the closed loop, namely, the loop superconducting circuit <NUM>, is adjusted.

Still referring to <FIG> and <FIG>, for example, a quantum chip provided in the example not forming part of the present invention, further includes signal terminals <NUM>, and the signal terminals <NUM> are formed on a side surface of the base substrate <NUM> and electrically connected to the signal transmission lines <NUM> in a one-to-one correspondence manner. The signal transmission lines <NUM> located on the base substrate <NUM> are configured to receive a regulation and control signal. The regulation and control signal is supplied from an external signal source, so that the signal terminals <NUM> need to be formed on the quantum chip to receive a control signal supplied from the external signal source and transmit the control signal to the qubit <NUM> through the signal transmission lines <NUM> and the metal piece <NUM>. Since the signal transmission lines <NUM> on the quantum chip provided in the present application is formed on the base substrate <NUM>, the signal terminals <NUM> are also formed on the base substrate <NUM> to facilitate direct electrical connection with the signal transmission lines <NUM>. In addition, in order to facilitate connection with the external signal source to receive the control signal, the signal terminals <NUM> are formed on the side surface of the base substrate <NUM>, and a function thereof is similar to pins of a semiconductor chip.

A fabrication method for a quantum chip is provided in some other implementations of the embodiment of the present application.

<FIG> shows an exemplary fabrication method for a quantum chip.

As shown in <FIG>, and with reference to <FIG> and <FIG>, an example provides a fabrication method for a quantum chip, and the fabrication method may include the following steps.

Step S10: Providing a base substrate <NUM> on which signal transmission lines <NUM> are formed.

Specifically, a base substrate <NUM> is provided, and the base substrate <NUM> may be a sapphire substrate, a silicon substrate, or the like. First, a superconducting metal layer is formed on a surface of the base substrate <NUM> by using an evaporation method, atomic deposition method, and the like; and further, a metal layer is patterned, exposed, developed, and etched to form desired signal transmission lines <NUM>.

Step S20: Forming at least one insulating substrate <NUM> on the base substrate <NUM>, where a qubit <NUM> and a through hole <NUM> penetrating through the insulating substrate <NUM> are formed on the insulating substrate <NUM>, a metal piece <NUM> is formed in the through hole <NUM>, and two ends of the metal piece <NUM> are electrically connected to the signal transmission lines <NUM> and the qubit <NUM>, respectively.

After the signal transmission lines <NUM> are formed on the base substrate <NUM>, the insulating substrate <NUM> is formed on the base substrate <NUM> by using an atomic deposition process or a sputtering process, a through hole <NUM> penetrating through the insulating substrate <NUM> is formed on the insulating substrate <NUM>, and a metal piece <NUM> is formed by filling a metal in the through hole <NUM>, so that circuit structures on both sides of the insulating substrate <NUM> may be electrically connected by means of the metal piece <NUM>.

As shown in <FIG>, and with reference to <FIG>, for example, an embodiment of the present application provides a method for forming at least one insulating substrate <NUM> on the base substrate <NUM>, and the method may include:.

The constructions, features and functions of the present application are described in detail in the embodiments with reference to the accompanying drawings. The foregoing is merely preferred embodiments of the present application, and the present application is not limited by the accompanying drawings, the invention being defined by the claims.

The present application provides a quantum chip and a fabrication method therefor, and the quantum chip includes a base substrate on which signal transmission lines are formed; and at least one insulating substrate located on the base substrate, and an isolation layer between the base substrate and the at least one insulating substrate,
where a qubit and a through hole penetrating through the insulating substrate and the isolation layer are formed on the insulating substrate, a metal piece is formed in the through hole, and two ends of the metal piece are electrically connected to the signal transmission lines and the qubit, respectively, such that signal transmission between the signal transmission lines and the qubit is implemented and a qubit complete circuit located on different layers is formed , and a plurality of insulating substrates that are stacked are used for forming qubits located on insulating substrates in different layers, thereby expanding a quantity of the qubits to an enough amount. In this way, an integration degree of a quantum chip is improved.

Claim 1:
A quantum chip, comprising:
a base substrate (<NUM>) on which signal transmission lines (<NUM>) are formed; and
at least one insulating substrate (<NUM>), wherein the insulating substrate (<NUM>) is located on the base substrate (<NUM>), a qubit (<NUM>) and a through hole (<NUM>) penetrating through the insulating substrate (<NUM>) are formed on the insulating substrate (<NUM>), a metal piece (<NUM>) is formed in the through hole (<NUM>); and two ends of the metal piece (<NUM>) are electrically connected to the signal transmission lines (<NUM>) and the qubit (<NUM>), respectively, characterized in that
the quantum chip further comprises an isolation layer (<NUM>), wherein the isolation layer (<NUM>) is located between the base substrate (<NUM>) and the insulating substrate (<NUM>), and the through hole (<NUM>) penetrates through the isolation layer (<NUM>).