Patent Description:
RDMA is a method for communication between hosts in a computer network. It typically requires special hardware support in at least one Network Interface Card (NIC). Most conventional devices and methods conform to the widely accepted "Infiniband" standard by the Infiniband Trade Association (IBTA), which covers hardware specifications, protocol formats, and how applications may use them. Notably, some NIC vendors extend their implementations with additional, non-standard functionality.

RDMA is, for example, widely used in data centers and clusters, particularly for low-latency and high-bandwidth networking. RDMA operations include the following types (wherein (<NUM>) indicates a "one-sided operation", and (<NUM>) indicates a "two-sided operation"):.

As illustrated exemplarily in <FIG>, a conventional device for RDMA performs any of the above-described operations based on a packet including at least the memory location (e.g., a virtual or physical address of the memory). <FIG> shows exemplarily a conventional target device <NUM> (also referred to as physical target host) including a virtual memory <NUM>, a NIC <NUM>, and a (physical) memory <NUM>, wherein the target device <NUM> executes an RDMA write operation in the memory <NUM>. The RDMA operation is based on a RDMA packet <NUM> including a destination virtual address (VA) <NUM>, a memory key <NUM>, the data <NUM> to be written, and a data length <NUM> of the data <NUM>. The packet <NUM> is provided by an initiator device (not shown) of the RDMA operation. Conventionally, the target device <NUM> does not control the location of the destination memory defined by the destination VA <NUM>.

In particular, when the packet <NUM> arrives, the following steps may take place at the target device <NUM>:.

A problem with such a conventional RDMA operation, and accordingly of the conventional devices and methods suitable for RDMA, is that an efficient communication with zero-copy on the target device is hard to achieve. In particular, zero-copy on the target is harder than on the initiator side, since it is hard for the target device to control/anticipate incoming packets/data and sizes thereof. Notably, zero-copy denotes a method, wherein each message (e.g. the packet including the data) is passed only once (a) from the initiator's region to its NIC (zero-copy send) and (b) from the target's NIC to the destination region (zero-copy receive). Zero-copy is desired, since it reduces the communication latency.

A conventional custom, ad hoc approach, such as "tag-matching" does not completely solve the above problem. In this approach, the target device informs the NIC of expected messages (and regions for them). Incoming messages are then identified by some fixed-size prefix ("tag"), against a list of expected tags. If the incoming message matches a tag, the respective memory region (zero-copy) is used. If it does not match, it is written to some temporary buffer pool (to be copied later, so not zero-copy). Disadvantages of this approach are that it is not "transparent" to the application, since it requires code modification to use (specify tags). Further, it is slower than the alternatives, due to costly software (SW) - hardware (HW) synchronization. In addition, it requires non-standard hardware.

<NPL>, discloses "Martini," a network interface controller chip for a network called RHiNET. Martini is designed to provide high-bandwidth and low-latency communication with small overhead. To obtain high performance communication, protected user-level zero-copy RDMA communication functions are completely implemented by a hardwired logic, and to reduce the communication latency efficiently, PIO-based communication mechanisms called "On-the-fly (OTF)" are implemented on Martini.

In view of the above-mentioned problems and disadvantages, embodiments of the present invention aim to improve the conventional devices, methods and approaches. An objective is to provide devices and methods for RDMA, which enable efficient zero-copy on the target.

The objective is achieved by the embodiments of the invention as described in the enclosed independent claims. Advantageous implementations of the embodiments of the invention are further defined in the dependent claims. In the following, parts of the description and drawings referring to embodiments not covered by the claims, are not part of the invention, but are illustrative examples necessary for understanding the invention.

Embodiments of the invention are based on a combination of any of the above-described RDMA operations (RDMA read/write/atomic operation) with atomic access to one or more offset values (wherein access may include incrementing the one or more offset values according to a size of a RDMA read/write operation, but other types of access are possible). The combination may be "atomic", meaning that it may be guaranteed to happen without interruptions (which is beneficial for cases of multiple concurrent operations).

A first aspect of this disclosure provides a device for RDMA, wherein for executing an RDMA operation on a memory, the device is configured to: receive a packet including a first destination address and a destination key; obtain one or more offset values; obtain a second destination address based on the first destination address, the destination key, and the one or more offset values; and initiate the RDMA operation on the memory based on the second destination address.

Thus, a new RDMA operation, particularly a RDMA operation with offset is introduced. The device of the first aspect may be the target device of that RDMA operation. This new RDMA operation enables zero-copy on the target as discussed above.

In an implementation form of the first aspect, the packet further comprises one or more first offset addresses and one or more offset keys, and the device is configured to obtain the one or more offset values based on the one or more first offset addresses and the one or more offset keys.

In an implementation form of the first aspect, the device is further configured to initiate a modification of at least one offset value, after the RDMA operation is performed on the memory.

In an implementation form of the first aspect, the modification of the at least one offset value comprises an increase or a decrease of the at least one offset value.

In an implementation form of the first aspect, the packet further comprises a data length, and the device is configured to initiate the modification of the at least one offset value based on the data length.

In an implementation form of the first aspect, the first destination address is a virtual address of a virtual memory of the device, and the second destination address is a physical address of the memory, and the device is configured to translate the first destination address into the second destination address based on a base virtual address, a base physical address of the memory, and the one or more offset values.

In an implementation form of the first aspect, the device is further configured to obtain one or more second offset addresses based on the one or more first offset addresses; and obtain the one or more offset values using the one or more second offset addresses.

In an implementation form of the first aspect, the one or more first offset addresses are virtual addresses of a virtual memory of the device, and the one or more second offset addresses are physical addresses of the memory, and the device is configured to translate the one or more first offset addresses into the one or more second offset addresses based on one or more offset base virtual addresses and an offset base physical address of the memory.

In an implementation form of the first aspect, the device is configured to obtain the one or more offset base virtual addresses and the offset base physical address based on the one or more offset keys.

In an implementation form of the first aspect, the one or more offset values are stored in the device, and/or the one or more offset values are stored on the memory, wherein the device comprises the memory, or the memory is a remote memory the device is configured to communicate with.

For the device of the first aspect, the "remote memory" is a memory of a remote host or device, i.e., a memory that is neither comprised by nor located at the device of the first aspect. For instance, it may be the memory of a third device.

A second aspect of this disclosure provides a device for RDMA, wherein for initiating an RDMA operation on a remote memory, the device is configured to provide a packet including a destination address, a destination key, one or more offset addresses, and one or more offset keys, to another device, wherein the destination address indicates a location for the RDMA operation on the remote memory, and wherein the one or more offset addresses indicate a location of one or more offset values at the other device or on the remote memory.

Thus, a new RDMA operation, particularly a RDMA operation with offset is introduced. The device of the second aspect may be the initiator device of that RDMA operation. This new RDMA operation enables zero-copy on the target as discussed above.

For the device of the second aspect, the "remote memory" is a memory of a remote host or device, i.e., a memory that is neither comprised by nor located at the device of the second aspect. For instance, it may be a memory comprised by or located at the device of the first aspect.

In an implementation form of the second aspect, the RDMA operation is an RDMA write operation, or an RDMA read operation, or an RDMA atomic operation.

The RDMA operation may be determined or indicated by an opcode in the packet.

A third aspect of this disclosure provides a method for RDMA, wherein for executing an RDMA operation on a memory, the method comprises: receiving a packet including a first destination address and a destination key; obtaining one or more offset values; obtaining a second destination address based on the first destination address and the one or more offset values; and initiating the RDMA operation on the memory based on the second destination address.

In an implementation form of the third aspect, the packet further comprises one or more first offset addresses and one or more offset keys, and the method further comprises obtaining the one or more offset values based on the one or more first offset addresses and the one or more offset keys.

In an implementation form of the third aspect, the method further comprises initiating a modification of at least one offset value, after the RDMA operation is performed on the memory.

In an implementation form of the third aspect, the modification of the at least one offset value comprises an increase or a decrease of the at least one offset value.

In an implementation form of the third aspect, the packet further comprises a data length, and the method further comprises initiating the modification of the at least one offset value based on the data length.

In an implementation form of the third aspect, the first destination address is a virtual address of a virtual memory, and the second destination address is a physical address of the memory, and the method further comprises translating the first destination address into the second destination address based on a base virtual address, a base physical address of the memory, and the one or more offset values.

In an implementation form of the third aspect, the method further comprises obtaining one or more second offset addresses based on the one or more first offset addresses, and obtaining the one or more offset values using the one or more second offset addresses.

In an implementation form of the third aspect, the one or more first offset addresses are virtual addresses of a virtual memory, and the one or more second offset addresses are physical addresses of the memory, and the method further comprises translating the one or more first offset addresses into the one or more second offset addresses based on one or more offset base virtual addresses and an offset base physical address of the memory.

In an implementation form of the third aspect, the method further comprises obtaining the one or more offset base virtual addresses and the offset base physical address based on the one or more offset keys.

In an implementation form of the third aspect, the one or more offset values are stored in the device, and/or the one or more offset values are stored on the memory, wherein the device comprises the memory, or the memory is a remote memory the device is configured to communicate with.

The method of the third aspect provides the same advantages as the device of the first aspect.

A fourth aspect of this disclosure provides a method for RDMA, wherein for initiating an RDMA operation on a remote memory, the method comprises providing a packet including a destination address, a destination key, one or more offset addresses, and one or more offset keys, wherein the destination address indicates a location for the RDMA operation on the remote memory, and wherein the one or more offset addresses indicate a location of one or more offset values at a device maintaining the one or more offset values or on the remote memory.

In an implementation form of the fourth aspect, the RDMA operation is an RDMA write operation, or an RDMA read operation, or an RDMA atomic operation.

The method of the fourth aspect provides the same advantages as the device of the second aspect.

A fifth aspect of this disclosure provides a computer program comprising a program code for performing the method according to the third aspect or fourth aspect or any implementation form thereof, when executed on a computer.

A sixth aspect of this disclosure provides a non-transitory storage medium storing executable program code, which, when executed by a processor, causes the method according to the third aspect or fourth aspect or any of their implementation forms to be performed.

In summary, the aspects and implementation forms (embodiments of the invention) define a new class of RDMA operations (RDMA operations with offset), all of which employ one or more offset values, extending the list of the currently available RDMA operation types, which do not employ such offset values (e.g. RDMA Write is extended to RDMA Write-with-offset). Adding the one or more offset values at the side of the target device, to be used and updated during/after any new RDMA operation, solves the aforementioned issues. As each packet arrives, the actual memory destination in the target memory depends on the value of said one or more offset values (which are, e.g., maintained in an offset register at the target device or memory). For example, by adding the data length of the data to that offset register, the next data (using the same offset register, now containing the updated offset value) may be written right after the previous data in the memory. The new mechanism for calculating the destination memory for these RDMA operations can be used in applications to allow zero-copy on the target, without any per-data software actions (it may only need one-time establishment).

It has to be noted that all devices, elements, units and means described in the present application could be implemented in software or hardware elements or any kind of combination thereof.

The above described aspects and implementation forms (embodiments of the invention) will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which.

<FIG> shows a device <NUM> and a device <NUM>, according to embodiments of the invention. The devices <NUM> and <NUM> are both suitable for RDMA. In particular, the device <NUM> is a target device <NUM> of an RDMA operation, i.e. for executing the RDMA operation, and the device <NUM> is an initiator device <NUM> of the RDMA operation, i.e. for initiating the RDMA operation.

The target device <NUM> may execute the RDMA operation in a (physical) memory <NUM>. The target device <NUM> may comprise the memory <NUM>. However, the memory <NUM> may also be a "remote memory" for the target device <NUM>, e.g. it may belong to a further device. For the initiator device <NUM>, the memory <NUM> is in any case a "remote memory", whether it is comprised by the target device <NUM> or by a further device. In the following, reference is made only to the "memory <NUM>".

For executing the RDMA operation in the memory <NUM>, the target device <NUM> is configured to receive a packet <NUM>, wherein the packet <NUM> includes at least a first destination address <NUM> and a destination key <NUM>. The target device <NUM> may receive the packet <NUM> from the initiator device <NUM>. Thus, the initiator device <NUM> is configured to provide the packet <NUM>, in order to initiate the RDMA operation in the memory <NUM>. The destination address <NUM> indicates a location for the RDMA operation in the memory <NUM>.

Further, the target device <NUM> is configured to obtain one or more offset values <NUM>. There are different ways to obtain the one or more offset values <NUM>, which are described further below. Then, the target device <NUM> is configured to obtain a second destination address <NUM> based on the first destination address <NUM>, based on the destination key <NUM>, and based on the one or more offset values <NUM>. Then, the target device <NUM> is configured to initiate and/or execute the RDMA operation in the memory <NUM> based on the second destination address <NUM>. The RDMA operation may thereby be an RDMA Write operation, or an RDMA Read operation, or an RDMA Atomic operation, i.e., more precisely it may be an RDMA Write-with-offset operation, or an RDMA Read-with-offset operation, or an RDMA Atomic-with-offset operation.

The target device <NUM> and/or the initiator device <NUM> may comprise a processor or processing circuitry (not shown) configured to perform, conduct or initiate the various operations of the target device <NUM> and/or the initiator device <NUM> described herein. The processing circuitry may comprise hardware and/or the processing circuitry may be controlled by software. The hardware may comprise analog circuitry or digital circuitry, or both analog and digital circuitry. The digital circuitry may comprise components such as application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), digital signal processors (DSPs), or multi-purpose processors.

The target device <NUM> and/or the initiator device <NUM> may further comprise memory circuitry, which stores one or more instruction(s) that can be executed by the processor or by the processing circuitry, in particular under control of the software. For instance, the memory circuitry may comprise a non-transitory storage medium storing executable software code which, when executed by the processor or the processing circuitry, causes the various operations of the target device <NUM> and/or the initiator device <NUM> to be performed.

In one embodiment, the processing circuitry comprises one or more processors and a non-transitory memory connected to the one or more processors. The non-transitory memory may carry executable program code which, when executed by the one or more processors, causes the target device <NUM> and/or the initiator device <NUM> to perform, conduct or initiate the operations or methods described herein.

<FIG> shows an example of an "explicit" RDMA Write-with-offset operation (wherein the type of the RDMA operation may be determined or indicated by an opcode <NUM> in the packet <NUM>), which may be executed by the target device <NUM> (also referred to as "Physical target host for the RDMA operation") and initiated by the initiator device <NUM>, respectively. In particular, the packet <NUM> is shown as provided by the initiator device <NUM> (not shown). Based on this packet <NUM>, the target device <NUM> can execute the RDMA Write-with-offset operation in the memory <NUM>. In this example, the memory <NUM> is comprised by the target device <NUM>. Further, in this example, the target device <NUM> also comprises a virtual memory <NUM>, and a NIC <NUM>. The RDMA operation is referred to as "explicit", because the one or more offset values <NUM> to be used in this RDMA operation are indicated (explicitly) by the packet <NUM>.

In particular, the packet <NUM> includes the first destination address <NUM> and the destination key <NUM>. In the example of <FIG>, the destination key <NUM> is a memory key of the memory <NUM>, and the first destination address <NUM> is a destination VA. The destination VA <NUM> is an address of the virtual memory <NUM> and is associated with a buffer of the target device <NUM>. The packet <NUM> further comprises a first offset address <NUM> and an offset key <NUM>. In the example of <FIG>, the first offset address <NUM> is an offset VA. The offset VA <NUM> is an address of the virtual memory <NUM> and is associated with a location of storage of the offset value <NUM>. The offset VA <NUM> may indicate a physical location <NUM> of the offset value <NUM> in the memory <NUM> of the target device <NUM> (or alternatively on a remote memory of a further device that the target device <NUM> is configured to communicate with (alternative not shown)).

The packet <NUM> may further comprise data <NUM> (to be written). The packet <NUM> would not comprise such data <NUM> if the RDMA operation was a RDMA Read-with-offset operation. The packet <NUM> may further comprise a data length <NUM> of the data <NUM>. Finally, the packet <NUM> may further comprise the opcode <NUM>, which determines or indicates the RDMA operation to be executed.

The data <NUM> may particularly be written by the target device <NUM> to a physical location <NUM> in the memory <NUM> (e.g., a physical location <NUM> in a certain memory region of the memory <NUM>, wherein the memory region may be indicated by the memory key <NUM>). The physical location <NUM> corresponds to the second destination address <NUM> (in the example of <FIG>, the second destination address <NUM> is a destination physical address (PA) of the memory <NUM>), which may be derived by the target device <NUM> based on the destination VA <NUM> - as provided by the initiator device <NUM> - and further based on the offset value <NUM>. That is, the data <NUM> may be written to the destination PA <NUM>. In particular, the data <NUM> may thereby be first written using the destination VA <NUM> of the virtual memory <NUM>, i.e. into the buffer of the target device <NUM>, and then by the target device <NUM> into the memory <NUM> using the destination PA <NUM>, i.e., to the physical location <NUM>.

Accordingly, both sides, i.e. the initiator device <NUM> and the target device <NUM>, can contribute to generating the second destination address <NUM>. In particular, by adding the offset value <NUM> on the side of the target device <NUM>, the target device <NUM> is allowed to control the write destination, and thus the operation nature is changed from one-sided (control only at the initiator device <NUM>) to two-sided (control at both devices).

In the example of <FIG>, the destination PA <NUM> of the memory <NUM> may be obtained by the target device <NUM> by translating the destination VA <NUM> into the destination PA <NUM> based on a base VA, a base PA of the memory <NUM>, and based on the one or more offset values <NUM>.

The base VA and/or base PA may be known to the target device <NUM>, or may be obtained or received by the target device <NUM>. As shown in <FIG>, the base VA and base PA may be available or maintained by the NIC <NUM>. For instance, the target device <NUM>, in particular the NIC <NUM>, may calculate the destination PA <NUM> based on the offset value <NUM>, according to the following equation: <MAT>.

Thereby, the offset value <NUM> may be obtained using a second offset address, which, in this example of <FIG>, is an offset PA, according to the following equation: <MAT>.

The offset PA identifies the physical location <NUM> in the memory <NUM>, at which the offset value <NUM> is stored, and from which it can be obtained by the NIC <NUM>.

The offset PA may be calculated by the target device <NUM> based on an offset base VA and an offset base PA of the memory <NUM> (each known and/or obtained by the target device <NUM>, particularly maintained by the NIC <NUM>), and the destination offset VA <NUM> according to the following equation: <MAT>.

The target device <NUM> may further, after writing the data <NUM> using the destination PA <NUM>, initiate an increase of the at least one offset value <NUM>, e.g. modify the current offset value <NUM> stored in the memory <NUM>, based on the data length <NUM> of the data <NUM> according to the following equation: <MAT>.

That is, the data length <NUM> is added to the current offset value <NUM>, and the thus obtained new offset value <NUM> is stored in the physical location <NUM> in the memory <NUM>.

In some embodiments, the offset value(s) <NUM> could also be selected by the initiator device <NUM> (particularly for the "explicit" RDMA Write-with-offset operation shown in <FIG>), or the offset value(s) <NUM> may be chosen by the target device <NUM>, for instance, upon arrival of the packet <NUM>. However, the offset value(s) <NUM> may be located on the target device <NUM>, and may affect the calculation of the second destination address <NUM> in either way.

The offset value(s) <NUM> may generally be modified after any RDMA operation, e.g. the offset value(s) <NUM> may be increased or decreased. As already mentioned above, the offset value(s) <NUM> may be increased by the size of the incoming data <NUM> (included in the packet <NUM>, e.g., as indicated by the data length <NUM>), so that a subsequent, identical RDMA Write-with-offset operation (same destination address <NUM> given in the packet <NUM>, e.g. same destination VA <NUM>) would not overwrite the previously written data <NUM>, but the new data <NUM> would rather be written right after the previously written data <NUM> in the memory <NUM> at a different physical location. In particular, according to the example of <FIG> and the previously mentioned equation: <MAT> if the offset value <NUM> changes (e.g., is increased by the target device <NUM>), the same destination VA <NUM> in the next packet <NUM> will result in a different destination PA <NUM>, i.e. a different physical location <NUM> in the memory <NUM> to which the data <NUM> is written.

Thus, the further data <NUM> may be logically appended to the previously written data <NUM>, when an identical further packet <NUM> arrives, i.e., the further data <NUM> included in that identical further packet <NUM> may be placed right after the previously written data <NUM> of the previous packet <NUM>, as is shown in <FIG>.

In particular, <FIG> shows an example of an RDMA Write-with-offset operation (see opcode <NUM>), in which the destination VA <NUM> has a value of 0x2111, the memory key <NUM> has a value of 0x1, the destination VA <NUM> has a value of 0x3010, the memory key <NUM> has a value of 0x3, the data length has a value of 0x5, and the data <NUM> is "ABCDE". Further, the base VA has a value of 0x2000, the base PA has a value of 0x0, the offset base VA has a value of 0x3000 and the offset base PA has a value of 0x2000. Thereby, the given values are hexadecimal values, wherein 0x denotes the hexadecimal value.

According to the above given equations, the offset PA is thus calculated as being a value of 0x2010 by using the above values (i.e., Offset PA = 0x3010 - 0x3000 + 0x2000). Notably, the offset VA <NUM> refers to the virtual memory <NUM> of the target device <NUM>, and the NIC <NUM> translates the offset VA <NUM> into the offset PA. The offset value <NUM> that can be obtained from the physical location <NUM> of the memory <NUM> corresponding to the offset PA has exemplarily a value of 0x123 in <FIG>.

Based on this offset value <NUM>, the destination PA <NUM> is calculated as being a value of 0x234 using the above values (i.e., Destination PA = 0x2111 - 0x2000 + 0x0 + 0x123).

The data "ABCDE" is then written by the target device <NUM>, particularly the NIC <NUM>, into the physical location <NUM> in the memory <NUM> corresponding to the destination PA <NUM>. Thereby, the data <NUM> may first be written to the buffer of the target device <NUM> using the destination VA <NUM>, and then from the buffer to the physical location <NUM> using the destination PA <NUM>.

After the writing of the data <NUM>, the offset value <NUM> may be increased by the target device <NUM>, particularly the NIC <NUM>, by the length <NUM> of the data, i.e., by the value of 0x5. Accordingly, the new offset value <NUM> becomes 0x128 (i.e., new offset value = 0x5 + 0x123).

If now a further packet <NUM> arrives from the initiator device <NUM> (with the same destination VA <NUM>), the data <NUM> of the further packet <NUM> will not overwrite the previously written data <NUM>, since the (new) offset value <NUM> is now different, namely has now a value of 0x128 and not anymore of 0x123. In particular, the destination PA <NUM> for the next RDMA write operation will calculate to: destination PA = 0x2111 - 0x2000 + 0x0 + 0x128. The data <NUM> of the further packet <NUM> will thus be logically appended to the previously written data <NUM>. Afterwards, the offset value <NUM> may again be increased to a value of 0x12D = 0x128 + 0x5 (if the data length <NUM> of the further data <NUM> was again 0x5).

The changes (compared to conventional systems and a conventional RDMA Write operation) to the packet <NUM> and calculation of the second destination address <NUM>, which are described above for the RDMA Write-with-offset operation, can also be applied to the other RDMA operation types. That is, the initiator device <NUM> and target device <NUM> may also perform a RDMA Read-with-offset operation, and/or a RDMA Atomic-with-offset operation (not shown in the figures).

<FIG> shows an alternative example to the "explicit" RDMA Write-with-offset operation shown as example in <FIG> and <FIG>. Namely, <FIG> shows an "implicit" RDMA Write-with-offset operation. The operation is referred to as "implicit", because the one or more offset values <NUM> are not indicated by the packet <NUM>, but are implicitly derived by the target device <NUM>. Notably, same elements in <FIG> and <FIG> share the same reference signs and function likewise.

In this operation, the packet <NUM> remains unchanged compared to the packet <NUM> of the conventional RDMA Write operation, as shown in <FIG>. That is, the packet <NUM> includes the opcode <NUM>, the destination VA <NUM>, the memory key <NUM>, the data <NUM> and the data length <NUM>. However, the packet <NUM> does not include the destination offset VA <NUM> and the offset key <NUM> as the packet <NUM> shown in <FIG>. The target device <NUM> nevertheless uses the offset value <NUM> when translating the destination VA <NUM> to the destination PA <NUM> (in the same manner as described with respect to <FIG>). The offset value <NUM> may be controlled by the target device <NUM> as described for the "explicit" RDMA Write-with-offset operation of <FIG>. The offset value <NUM> may, as in the previous "explicit" variant shown in <FIG>, be stored at the target device <NUM>, e.g., in the memory <NUM>, in particular the physical location <NUM>. The target device <NUM> obtains the offset value <NUM> on its own motion, without being given any information in this respect via the packet <NUM>.

The RDMA operations with offset may further be based on the following principles:.

Combining the above principles with the RDMA with offset operations enables a scheme, wherein each packet <NUM> resp. data <NUM> is passed only once (a) from the region of the initiator device <NUM> to its NIC (zero-copy send) and (b) from the NIC <NUM> of the target device <NUM> to the destination region (zero-copy receive). This significantly reduces the communication latency.

<FIG> shows a method <NUM> for executing an RDMA operation according to an embodiment of the invention. The method <NUM> can be performed by the target device <NUM>. For executing an RDMA operation on a memory <NUM>, the method <NUM> comprises: a step <NUM> of receiving a packet <NUM> including a first destination address <NUM> and a destination key <NUM>; a step <NUM> of obtaining one or more offset values <NUM>; a step <NUM> of obtaining a second destination address <NUM> based on the first destination address <NUM> and the one or more offset values <NUM>; and a step <NUM> of initiating the RDMA operation in the memory <NUM> based on the second destination address <NUM>.

Claim 1:
A device (<NUM>) for executing a Remote Direct Memory Access, RDMA, operation in a memory (<NUM>), wherein the device (<NUM>) is configured to:
receive a packet (<NUM>) including a first destination address (<NUM>), a destination key (<NUM>), one or more first offset addresses (<NUM>), and one or more offset keys (<NUM>), wherein the first destination address is a virtual address of a virtual memory of the device;
obtain one or more offset values (<NUM>) based on the one or more first offset addresses (<NUM>) and the one or more offset keys (<NUM>);
obtain a second destination address (<NUM>) based on the first destination address (<NUM>), the destination key (<NUM>), and the one or more offset values (<NUM>); and
initiate the RDMA operation in the memory (<NUM>) based on the second destination address (<NUM>).