Patent Description:
Avalanche diodes are used as photon detectors in many applications. The detection process comprises (<NUM>) the avalanche diode generating electrons and holes in response to electromagnetic radiation, charged particles, or photons; (<NUM>) separating the electrons and holes in the diode using a strong reverse bias voltage applied to the diode; (<NUM>) using the strong reverse bias voltage to further accelerate the electrons in the diode and generate additional electrons through impact ionization (an internal gain mechanism); and (<NUM>) forming a detection signal using the multiple electrons generated through the impact ionization from each of the photo-generated electrons.

<FIG> illustrates a Low-Gain-Avalanche-Detector (LGAD) having an n+-type layer (cathode) forming a junction with a p-type multiplication layer. Electrons are photo-generated in a p-type bulk region in response to the electromagnetic radiation and the p- type multiplication layer is the gain layer wherein the additional electrons are generated through the impact ionization. A p+-anode is formed on the p-type bulk region so that an ohmic connection can be made between the p-type bulk and an anode plane that allows for the application of a reverse bias voltage across the anode and the cathode. Such an LGAD fabricated in silicon can be used for particle detection, particularly in the arena of ultra-fast (~<NUM> ps) timing. However, the high electric fields needed to induce the impact ionization process lead to breakdown between the separated n-p junctions that are used to simultaneously deplete the sensors and establish the readout segmentation. As a result, working devices have included a Junction Termination Extension (JTE) that provides electrostatic isolation between neighboring implants, but at a cost of introducing a dead region between the sensor segments that is insensitive to the deposited charge from an incident charged particle or photon. The width of this dead region is <NUM> or more, making conventional LGAD sensors inefficient for granularity or spatial resolution scales much below <NUM>.

However, particle physics (4D tracking) and photon science (high frame-rate X-Ray imaging) applications require granularity or spatial resolution at the <NUM> scale. Thus, there is a need to overcome the current granularity limits of LGAD sensors. The present disclosure satisfies this need.

The documents "<NPL>; "<NPL>; and "<NPL>, disclose known structures of low gain avalanche detectors.

As discussed herein, avalanche diodes use high electric fields to provide signal gain by using a high electric field at or near a p-n junction to generate an "avalanche" of additional signal charge. However, the high electric field can also cause breakdown in the readout structure of the avalanche diode, resulting in a limit to the granularity of the readout from the diode.

The present invention is defined in the appended claims and describes a Low-Gain Avalanche Detector (LGAD) comprising a buried junction that localizes the high electric field region and isolates it from the readout structure, thereby solving the problem of granularity limits on the LGADs. In typical examples, a planar, highly-doped diode junction is buried several micrometers below the surface of the device, allowing for a low electric field region in the area close to the surface readout structure while the high electric field region in the area of the junction produces the gain characteristic of LGADs.

In typical embodiments, the buried diode junction eliminates the need for the Junction-Termination Extension (JTE) structure, employed in conventional LGADs, that limits achievable granularity. The significantly higher degree of granularity achievable using embodiments described herein opens up a range of additional applications for the LGAD.

In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made within the scope of the appended claims without departing from the scope of the present invention.

The present disclosure describes an entirely novel approach to the problem of improving the granularity of LGAD sensors - the Deep Junction ("DJ-LGAD") LGAD comprising the high electric-field gain region (wherein impact ionization takes place) moved away from the readout structure.

<FIG> illustrates the LGAD comprises a diode (p-n) junction buried a few micrometers below and away from the upper surface of the LGAD (the upper surface comprising the surface where segmentation is imposed). In the example shown, such positioning of the high electric-field gain region avoids the need for the JTE.

More specifically, <FIG> illustrates an example avalanche diode <NUM> including a semiconductor structure <NUM> including an n-type region <NUM>; a p-type region <NUM>; and a gain region <NUM> buried between the n-type region <NUM> and the p-type region <NUM>. The gain region includes an n+-type region <NUM> having a higher n-type dopant density than the n-type region; a p+-type region <NUM> having a higher p-type dopant density than the p-type region; and a p-n junction <NUM> including an interface 210a between the n+-type region and the p+-type region.

The n-type region <NUM> includes a plurality of segments <NUM>, each of the segments including a first surface <NUM> of the n-type region <NUM> and the semiconductor structure.

<FIG> further illustrates the avalanche diode as including a readout structure <NUM> comprising a plurality of first electrodes <NUM>, wherein at least one of the first electrodes is on each of the segments and the first electrodes on different segments are electrically isolated from one another. A second electrode <NUM> is deposited on a second surface <NUM> of the semiconductor structure/p-type region and an ohmic contact <NUM> is formed between the p-type region and the second electrode. The p-n junction is reverse biased by application of an electric field between the first electrodes in the readout structure and the second electrode. As illustrated in <FIG>, each of the segments include implanted regions <NUM> having a higher dopant density than the n-type region <NUM>. The implanted regions <NUM> form an ohmic contact with the first electrodes. Also shown in <FIG> are electrostatic isolation barriers <NUM> (e.g., p-type wells) electrically isolating the segments.

<FIG> illustrates the LGAD as comprising a gain layer including both the n+ region (dark blue section) and the p+ region (dark red section), rather than just a dark red section. In other words, the gain layer comprises the full p-n junction, rather than just the p+ doped area. A key benefit of burying the entire junction, rather than just the highly-doped p+ region, is that application of a reverse bias (creating a depletion zone) establishes an electric field in the region of the junction that is similar to that of a parallel-plate capacitor. Specifically, application of the reverse bias voltage creates two planes comprising near equal (but opposite sign) high charge density, so that the electric field in the region of the junction is sufficiently high to induce the limited and controlled impact ionization that is characteristic of LGADs. The electric fields are much lower outside the highly doped junction region, however, thereby avoiding the need to provide isolation between the readout segmentation and the junction.

The structure of <FIG> was simulated with version K_2015. <NUM>-SP2 of the Sentaurus Device simulation package from the Synopsys Corporation. A challenge of designing a workable DJ-LGAD is to determine the doping profiles that:.

Table <NUM> illustrates a sample doping profile ("Baseline-<NUM>" configuration) that achieves these conditions (<NUM>) and (<NUM>), while maintaining electric fields at the readout surface low enough to allow for conventional segmentation techniques and avoid the use of a JTE. All further results presented herein are for the simulated behavior of this Baseline-<NUM> configuration.

<FIG> shows the resulting two-dimensional electric field profile, as a function of depth into the Baseline-<NUM> detector and of a lateral coordinate parallel to the surface of the device, for a bias voltage of 210V. For bias voltages above <NUM> Volts, the electric field in the p-type drift region and the n-type isolation region is relatively insensitive to the applied voltage, leading to stable charge collection properties. The impact ionization process, which depends upon electric field in the gain region, is also well controlled, leading to the smooth dependence of gain upon bias voltage shown in <FIG>.

<FIG> shows the gain variation as a function of lateral position that results from the electric field depicted in <FIG>; uniformity at the +/-<NUM>% level is observed. Gain is defined by the collected charge in the LGAD over the collected charge in a same thickness silicon sensor without the gain layer structure.

<FIG> shows the temporal signal profile as a function of applied bias voltage (obtained using the simulation). A sharp rising edge, conducive to a fast timing measurement, is observed for all bias voltages, with a slew-rate that grows monotonically with bias voltage. Consistent with the saturation drift velocity (approximately <NUM> per nanoseconds) of carriers in silicon, the majority of the charge within this <NUM> device is collected within <NUM> picoseconds, suggesting an achievable device repetition rate in excess of <NUM>.

<FIG> is a flowchart illustrating a method of making an avalanche diode (referring also to <FIG>).

Block <NUM> represents obtaining or creating a semiconductor structure (e.g., epitaxial layers) on a substrate. In one or more examples, the semiconductor structure is a silicon semiconductor structure and the substrate is a silicon substrate (or the semiconductor structure and the substrate may comprise or consist essentially of silicon). In one example, the semiconductor structure includes a bulk p-type region; a gain region including a p-n junction on or above the bulk p-type region; and an n-type region (isolation region) on or above the gain region (n-side up configuration). In another example, the semiconductor structure includes a bulk n-type region; a gain region including a p-n junction on or above the bulk n-type region; and the p-type region (isolation region) on or above the gain region (p-side up configuration). The gain region includes an n+-type region having a higher n-type dopant density than the n-type region; a p+-type region having a higher p-type dopant density than the p-type region; and the p-n junction between the n+-type region and the p+-type region. The p+-type region typically forms a j unction interface in physical contact with the n+-type region. Example p-type dopants include, but are not limited to, boron, gallium, aluminum, and indium. Example n-type dopants include, but are not limited to, phosphorus, arsenic, antimony, bismuth and lithium.

Block <NUM> represents forming a readout structure so that the surface of the n-type (p-type) region forms the readout structure. The step comprises defining a plurality of segments in the n-type region or the p-type region depending on the configuration (n-side up or p-side up).

Block <NUM> represents creating or generating (e.g., depositing) a plurality of first electrodes forming an ohmic contact with the readout structure and a second electrode forming an ohmic contact with the p-type (n-type) region. At least one of the first electrodes is on each of the segments and the first electrodes on different segments are electrically isolated from one another. Established segmentation schemes for conventional (non-LGAD) silicon diode sensors may also be used. The step further comprises forming a first ohmic contact between the implanted regions and the first electrodes, and a second ohmic contact between the bulk p-type region and the bulk n-type region and a second electrode, so that the p-n junction is reverse biased by application of an electric field of appropriate polarity between the first electrodes and the second electrode. The second ohmic contact is typically formed on a second surface of the semiconductor structure opposite the first surface.

Block <NUM> represents the end result, an avalanche diode. The avalanche diode can be used in many applications, including but not limited to, as a pixel sensor (e.g., at the large hadron collider (LHC) or proposed Electron-Ion Collider (EIC)) with fast timing capabilities.

As described above, conventional LGADs are biased with high electric fields required to induce the impact ionization process, leading to breakdown between the separated n-p junctions that are used to simultaneously deplete the sensors and establish the readout segmentation. As a result, working LGAD devices have included a Junction Termination Extension (JTE) that provides electrostatic isolation between neighboring implants, but at the cost of introducing a dead region between the sensor segments that is insensitive to the deposited charge from an incident particle. The width of this dead region is <NUM> or more, making conventional LGAD sensors inefficient for granularity scales much below <NUM>. The following devices have been proposed to circumvent the JTE limit.

Therefore, these approaches (<NUM>)-(<NUM>) for increasing LGAD granularity make use of more complex, and less proven segmentation techniques. Exemplary device embodiments described herein, on the other hand, include the diode junction gain layer buried below a lightly-doped isolation layer, enabling the use of conventional segmentation techniques to achieve high granularity. This allows for the removal of constraints on the granularity of LGADs while maintaining their attractive properties of internal gain, timing resolution and repetition rate.

Claim 1:
a Low Gain Avalanche Detector (LGAD) (<NUM>), comprising
a semiconductor structure (<NUM>) comprising:
an n-type (respectively p-type) region (204a) comprising a plurality of segments (<NUM>) each comprising an implanted region (<NUM>) having a higher dopant density than the n-type (respectively p-type) region;
a p-type (respectively n-type) region (206a); and
a gain region (<NUM>) between the n-type (respectively p-type) region (204a) and the p-type (respectively n-type) region (206a), the gain region buried between the n-type (respectively p-type) region and the p-type (respectively n-type) region and the gain region comprising:
an n+-type region (<NUM>) having a higher n-type dopant density than the n-type region;
a p+-type region (<NUM>) having a higher p-type dopant density than the p-type region; and
a p-n junction (<NUM>) between the n+-type region (<NUM>) and the p+-type region (<NUM>);
a readout structure (<NUM>) comprising:
a plurality of first electrodes (<NUM>), wherein:
each of the first electrodes is on a different one of the segments (<NUM>),
the first electrodes (<NUM>) are electrically isolated from one another; and
each of the segments (<NUM>) comprises a first ohmic contact between the implanted region (<NUM>) and the one of the first electrodes (<NUM>) on the implanted region (<NUM>);
a second ohmic contact (<NUM>) between the p-type (respectively n-type) region (206a) and a second electrode (<NUM>); and
wherein the p-n junction (<NUM>) experiences a reverse bias electric field when an appropriate polarity bias is applied between the first electrodes (<NUM>) and the second electrode.