Patent Description:
An image sensor is a semiconductor device for converting an optical image into electrical signals. As computer and communication industries have been developed, high-performance image sensors there has been increasing demanded in various fields such as digital cameras, camcorders, personal communication systems (PCS), game consoles, security cameras, and medical micro cameras. Image sensors may be categorized as any one of charge coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. CIS is short for the CMOS image sensor. The CIS may include a plurality of pixels arranged two-dimensionally. Each of the pixels may include a photodiode (PD). The photodiode may convert incident light into an electrical signal. The plurality of pixels may be defined by a deep device isolation pattern disposed therebetween.

<CIT> discloses a photoelectric conversion device having an isolation structure. First and second isolation portions are provided between first and second photoelectric conversion elements. The first isolation portion extends from a first plane of a semiconductor layer to a position corresponding to at least a quarter of a length from the first plane to a second plane of the semiconductor layer. The second isolation portion extends from the second plane of the semiconductor layer to a position corresponding to at least a quarter of the length from the first plane to the second plane.

<CIT> discloses an image sensor which includes a substrate, a shallow trench isolation layer, a first deep trench isolation layer, and a second deep trench isolation layer. The substrate includes a first surface, a second surface opposing the first surface, and a plurality of unit pixel regions. The shallow trench isolation layer is adjacent to the first surface. The first deep trench isolation layer is adjacent to the shallow trench isolation layer and extends toward the second surface in the substrate. The second deep trench isolation layer is adjacent to the second surface and vertically overlaps the first deep trench isolation layer. The first and second deep trench isolation layers isolate the unit pixel regions from each other.

Embodiments may provide an image sensor capable of preventing a cross-talk phenomenon and of minimizing noise, and a method of manufacturing the same.

According to an aspect of the present invention there is provided an image sensor according to claim <NUM>.

According to an aspect of the present disclosure, but not forming part of the claimed invention, there is provided an image sensor which includes: a substrate including a plurality of pixel regions, the substrate having a first surface, a second surface opposite the first surface, and a first trench recessed from the first surface; a shallow device isolation pattern provided in the first trench; and a deep device isolation pattern provided in the substrate between pixel regions of the plurality of pixel regions. The deep device isolation pattern includes a semiconductor pattern penetrating at least a portion of the substrate, and an isolation pattern provided between the substrate and the semiconductor pattern. The isolation pattern includes a first isolation pattern adjacent to the second surface of the substrate, and a second isolation pattern adjacent to the first surface of the substrate. The second isolation pattern includes a lower portion provided under the shallow device isolation pattern, and an upper portion penetrating the shallow device isolation pattern. The lower portion of the second isolation pattern is aligned with the first isolation pattern. The first isolation pattern includes a first material, and the second isolation pattern includes a second material that is different from the first material.

According to an aspect of the present, but not forming part of the claimed invention, there is provided an image sensor which includes: a substrate including a plurality of pixel regions, the substrate having a first surface, a second surface opposite, and a first trench recessed from the first surface; a shallow device isolation pattern provided in the first trench; a deep device isolation pattern provided between pixel regions of the plurality of pixel regions and disposed in the substrate; a transistor provided on the first surface of the substrate; micro lenses provided on the second surface of the substrate; and color filters provided on the plurality of pixel regions and between the substrate and the micro lenses. The deep device isolation pattern includes a semiconductor pattern penetrating at least a portion of the substrate, and an isolation pattern provided between the substrate and the semiconductor pattern. The isolation pattern includes a first isolation pattern adjacent to the second surface of the substrate, and a second isolation pattern adjacent to the first surface of the substrate. The first isolation pattern includes a first insulating material and the second isolation pattern includes a second insulating material that is different from the first insulating material.

The above and other aspects, features, and advantages of certain example embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:.

Example embodiments of the disclosure will now be described more fully with reference to the accompanying drawings.

<FIG> is a block diagram schematically illustrating an image sensor according to an example embodiment.

Referring to <FIG>, an image sensor may include an active pixel sensor array <NUM>, a row decoder <NUM>, a row driver <NUM>, a column decoder <NUM>, a timing generator <NUM>, a correlated double sampler (CDS) <NUM>, an analog-to-digital converter (ADC) <NUM>, and an input/output (I/O) buffer <NUM>.

The active pixel sensor array <NUM> may include a plurality of pixels arranged two-dimensionally and may convert optical signals into electrical signals. The active pixel sensor array <NUM> may be driven by a plurality of driving signals (e.g., a pixel selection signal, a reset signal, and a charge transfer signal) provided from the row driver <NUM>. In addition, the electrical signals converted by the active pixel sensor array <NUM> may be provided to the correlated double sampler <NUM>.

The row driver <NUM> may provide the plurality of driving signals for driving the plurality of pixels to the active pixel sensor array <NUM> in response to signals decoded in the row decoder <NUM>. When the pixels are arranged in a matrix form, the driving signals may be provided by rows of the matrix form.

The timing generator <NUM> may provide timing signals and control signals to the row decoder <NUM> and the column decoder <NUM>.

The correlated double sampler (CDS) <NUM> may receive electrical signals generated from the active pixel sensor array <NUM> and may hold and sample the received electrical signals. The correlated double sampler <NUM> may doubly sample a specific noise level and a signal level of the electrical signal and may output a difference level corresponding to a difference between the noise level and the signal level.

The analog-to-digital converter (ADC) <NUM> may convert an analog signal, which corresponds to the difference level outputted from the correlated double sampler <NUM>, into a digital signal and may output the digital signal.

The I/O buffer <NUM> may latch the digital signals and may sequentially output the latched signals to an image signal processing unit in response to signals decoded in the column decoder <NUM>.

<FIG> is a circuit diagram illustrating an active pixel sensor array of an image sensor according to an example embodiment.

Referring to <FIG> and <FIG>, the active pixel sensor array <NUM> may include a plurality of pixel regions PX, and the pixel regions PX may be arranged in a matrix form. Each of the pixel regions PX may include a transfer transistor TX and logic transistors RX, SX and DX. The logic transistors may include a reset transistor RX, a selection transistor SX, and a drive transistor DX. The transfer transistor TX, the reset transistor RX and the selection transistor SX may include a transfer gate TG, a reset gate RG and a selection gate SG, respectively. Each of the pixel regions PX may further include a photoelectric conversion element PD and a floating diffusion region FD.

The photoelectric conversion element PD may generate and accumulate photocharges in proportion to the amount of light incident from the outside. The photoelectric conversion element PD may be a photodiode including a P-type dopant region and an N-type dopant region. The transfer transistor TX may transfer photocharges (or charges) generated from the photoelectric conversion element PD to the floating diffusion region FD. The floating diffusion region FD may receive the charges generated from the photoelectric conversion element PD and may cumulatively store the received charges. The drive transistor DX may be controlled according to the amount of the charges accumulated in the floating diffusion region FD.

The reset transistor RX may periodically reset the charges accumulated in the floating diffusion region FD. A drain electrode of the reset transistor RX may be connected to the floating diffusion region FD, and a source electrode of the reset transistor RX may be connected to a power voltage VDD. When the reset transistor RX is turned-on, the power voltage VDD connected to the source electrode of the reset transistor RX may be applied to the floating diffusion region FD. Thus, when the reset transistor RX is turned-on, the charges accumulated in the floating diffusion region FD may be discharged to reset the floating diffusion region FD.

The drive transistor DX may function as a source follower buffer amplifier. The drive transistor DX may amplify a potential change in the floating diffusion region FD and may output the amplified potential change to an output line VOUT.

The selection transistor SX may select pixel regions PX to be read in the unit of row. When the selection transistor SX is turned-on, the power voltage VDD may be applied to a drain electrode of the drive transistor DX.

The unit pixel region PX including a single photoelectric conversion element PD and four transistors TX, RX, DX and SX is illustrated as an example in <FIG>, but embodiments are not limited thereto. In certain embodiments, the reset transistor RX, the drive transistor DX and/or the selection transistor SX may be shared by adjacent pixel regions PX. Thus, an integration density of the image sensor may be improved.

<FIG> is a plan view illustrating an image sensor according to an example embodiment. <FIG> is a cross-sectional view taken along a line I-I' of <FIG> to illustrate an image sensor according to an example embodiment. <FIG> is an enlarged view of a portion 'A' of <FIG>.

Referring to <FIG> and <FIG>, an image sensor may include a photoelectric conversion layer <NUM>, an interconnection layer <NUM>, and a light transmitting layer <NUM>. The photoelectric conversion layer <NUM> may be disposed between the interconnection layer <NUM> and the light transmitting layer <NUM>.

The photoelectric conversion layer <NUM> may include a substrate <NUM>. The substrate <NUM> may be a semiconductor substrate (e.g., a silicon substrate, a germanium substrate, a silicon-germanium substrate, a group II-VI compound semiconductor substrate, or a group III-V compound semiconductor substrate) or a silicon-on-insulator (SOI) substrate. The substrate <NUM> may have a first surface 100a and a second surface 100b, which are opposite to each other. For example, the first surface 100a of the substrate <NUM> may be a front surface, and the second surface 100b of the substrate <NUM> may be a back surface. In use, light may be incident to the second surface 100b of the substrate <NUM>.

The substrate <NUM> may include a plurality of pixel regions PX. The plurality of pixel regions PX may be two-dimensionally arranged in a first direction D1 and a second direction D2 which are parallel to the second surface 100b of the substrate <NUM>, when viewed in a plan view as shown, e.g., in <FIG>. The first direction D1 and the second direction D2 may intersect each other (e.g. may be perpendicular to each other). The substrate <NUM> may include a plurality of photoelectric conversion regions PD therein. The photoelectric conversion regions PD may be located between the first surface 100a and the second surface 100b of the substrate <NUM>. The photoelectric conversion regions PD may be provided in the pixel regions PX of the substrate <NUM>, respectively. The photoelectric conversion region PD may mean a region in which the photoelectric conversion element PD of <FIG> is disposed.

The substrate <NUM> may have a first conductivity type, and the photoelectric conversion region PD may be a region doped with dopants having a second conductivity type different from the first conductivity type. For example, the first conductivity type may be a P-type, and the second conductivity type may be an N-type. Dopants having the first conductivity type may include at least one of, for example, aluminum, boron, indium, or gallium. The dopants having the second conductivity type may include at least one of, for example, phosphorus, arsenic, bismuth, or antimony. The photoelectric conversion region PD may form a PN junction with the substrate <NUM> to form a photodiode.

The photoelectric conversion layer <NUM> may include a shallow device isolation pattern <NUM>. The shallow device isolation pattern <NUM> may be disposed adjacent to the first surface 100a of the substrate <NUM>. Each of the plurality of pixel regions PX may include active regions ACT defined by the shallow device isolation pattern <NUM>. The shallow device isolation pattern <NUM> may be disposed in a first trench TR1 recessed from the first surface 100a of the substrate <NUM>. The shallow device isolation pattern <NUM> may include at least one of, for example, silicon oxide, silicon nitride, or silicon oxynitride.

The photoelectric conversion layer <NUM> includes a deep device isolation pattern <NUM>. The deep device isolation pattern <NUM> is disposed in the substrate <NUM> between the plurality of pixel regions PX. The deep device isolation pattern <NUM> may penetrate at least a portion of the substrate <NUM>. The deep device isolation pattern <NUM> may penetrate the shallow device isolation pattern <NUM> and may extend into the substrate <NUM> (e.g. may penetrate into the substrate <NUM> beyond the depth of the shallow device isolation pattern <NUM>). The term 'depth' may mean a distance measured from the second surface 100b of the substrate <NUM> into the substrate <NUM> along a direction perpendicular to the second surface 100b of the substrate <NUM> (e.g. parallel to a third direction D3 that is perpendicular to the second surface 100b of the substrate <NUM>). The deep device isolation pattern <NUM> is disposed in a second trench TR2. The second trench TR2 penetrates the shallow device isolation pattern <NUM> and extends toward the second surface 100b of the substrate <NUM>. A width of an upper portion of the second trench TR2 may be less than a width of a bottom surface of the first trench TR1. The term 'width' may mean a distance measured in a direction parallel to the second surface 100b of the substrate <NUM>, for example, a distance measured in the second direction D2. The deep device isolation pattern <NUM> may have a grid structure surrounding each of the plurality of pixel regions PX, when viewed in a plan view as shown, e.g., in <FIG>. In some embodiments, the deep device isolation pattern <NUM> may extend from the first surface 100a of the substrate <NUM> to the second surface 100b of the substrate <NUM>, and a bottom surface 150b of the deep device isolation pattern <NUM> may be substantially coplanar with the second surface 100b of the substrate <NUM>. For example, the deep device isolation pattern <NUM> may include an insulating material of which a refractive index is lower than that of the substrate <NUM>.

Referring to <FIG> and <FIG>, the deep device isolation pattern <NUM> may include an isolation pattern IP, a semiconductor pattern <NUM>, and an insulating pattern <NUM>. The isolation pattern IP may penetrate at least a portion of the substrate <NUM>. The isolation pattern IP may be disposed between the pixel region PX and the semiconductor pattern <NUM>. The isolation pattern IP may also be disposed between the substrate <NUM> and a side surface of the semiconductor pattern <NUM> and between the shallow device isolation pattern <NUM> and the insulating pattern <NUM>. The isolation pattern IP may extend from the side surface of the semiconductor pattern <NUM> onto a side surface of the insulating pattern <NUM>. The isolation pattern IP may fill a portion of the second trench TR2. The isolation pattern IP may cover an inner side surface of the second trench TR2. The isolation pattern IP may expose a bottom surface of the second trench TR2. The isolation pattern IP may surround each of the pixel regions PX when viewed in a plan view.

The isolation pattern IP may include a first isolation pattern <NUM> adjacent to the second surface 100b of the substrate <NUM>, and a second isolation pattern <NUM> adjacent to the first surface 100a of the substrate <NUM>. The first isolation pattern <NUM> may penetrate a portion of the substrate <NUM>. The first isolation pattern <NUM> may extend from the second surface 100b of the substrate <NUM> into the substrate <NUM>. The first isolation pattern <NUM> may be disposed between each of the pixel regions PX and the side surface of the semiconductor pattern <NUM>. A top surface of the first isolation pattern <NUM> may be disposed in the substrate <NUM>. A bottom surface of the first isolation pattern <NUM> may correspond to the bottom surface 150b of the deep device isolation pattern <NUM> and may be substantially coplanar with the second surface 100b of the substrate <NUM>.

The second isolation pattern <NUM> may penetrate the shallow device isolation pattern <NUM> and may penetrate a portion of the substrate <NUM>. The second isolation pattern <NUM> may extend from the first surface 100a of the substrate <NUM> into the substrate <NUM>. A top surface of the second isolation pattern <NUM> may be substantially coplanar with the first surface 100a of the substrate <NUM>. A bottom surface of the second isolation pattern <NUM> may be disposed in the substrate <NUM>. The second isolation pattern <NUM> may extend from the side surface of the semiconductor pattern <NUM> onto the side surface of the insulating pattern <NUM>. The second isolation pattern <NUM> may extend between the shallow device isolation pattern <NUM> and the insulating pattern <NUM>.

A first interface IF1 at which the first isolation pattern <NUM> is in contact with the second isolation pattern <NUM> may be located at a lower level than a bottom surface of the shallow device isolation pattern <NUM>. The first interface IF1 may be spaced apart from the shallow device isolation pattern <NUM>. The first interface IF1 may be located at a lower level than a bottom surface of the first trench TR1. The term 'level' may mean a height from the second surface 100b of the substrate <NUM> toward the first surface 100a of the substrate <NUM>.

The second isolation pattern <NUM> may include a lower portion 153BP disposed under the shallow device isolation pattern <NUM>, and an upper portion 153UP penetrating the shallow device isolation pattern <NUM>. The lower portion 153BP of the second isolation pattern <NUM> may have a first side surface 153OS adjacent to (or in contact with) the substrate <NUM>, and a second side surface 153IS adjacent to (or in contact with) the semiconductor pattern <NUM>. The first isolation pattern <NUM> may have a first side surface 151OS adjacent to (or in contact with) the substrate <NUM>, and a second side surface 151IS adjacent to (or in contact with) the semiconductor pattern <NUM>. The lower portion 153BP of the second isolation pattern <NUM> may be aligned with the first isolation pattern <NUM>. More particularly, the first side surface 153OS of the lower portion 153BP of the second isolation pattern <NUM> may be aligned with the first side surface 151OS of the first isolation pattern <NUM>, and the second side surface 153IS of the lower portion 153BP of the second isolation pattern <NUM> may be aligned with the second side surface 151IS of the first isolation pattern <NUM>. The first side surface 153OS of the lower portion 153BP of the second isolation pattern <NUM> may be coplanar with the first side surface 151OS of the first isolation pattern <NUM>, and the second side surface 153IS of the lower portion 153BP of the second isolation pattern <NUM> may be coplanar with the second side surface 151IS of the first isolation pattern <NUM>. In other words, as shown, e.g., in <FIG> and <FIG>, the lower portion 153BP of the second isolation pattern <NUM> and the first isolation pattern <NUM> may not have a stepped surface therebetween.

The first isolation pattern <NUM> may include a different material from that of the second isolation pattern <NUM>. For example, the first isolation pattern <NUM> may include a first insulating material, and the second isolation pattern <NUM> may include a second insulating material. The first insulating material and the second insulating material may be different materials. The first isolation pattern <NUM> may include, for example, a low refractive index (LRI) material. For example, a refractive index (n) of the first isolation pattern <NUM> may range from <NUM> to <NUM>, in particular, from <NUM> to <NUM>. The second isolation pattern <NUM> may include, for example, a high-k material. For example, a dielectric constant (k) of the second isolation pattern <NUM> may range from <NUM> to <NUM>. In some embodiments, the first isolation pattern <NUM> may include a material having a refractive index (n) lower than that of the second isolation pattern <NUM>. In this context, the terms 'low' and 'high' may be relative (e.g. as compared to the other isolation pattern). In some embodiments, the second isolation pattern <NUM> may include a material having a dielectric constant (k) higher than that of the first isolation pattern <NUM>. However, embodiments are not limited thereto, and the first isolation pattern <NUM> may include the low refractive index (LRI) material, and the second isolation pattern <NUM> may include the high-k material. For example, the first isolation pattern <NUM> may include an oxide (e.g., silicon oxide). For example, the second isolation pattern <NUM> may include at least one of a nitride, a metal nitride, or a metal oxide. For example, the nitride may include silicon nitride. For example, the metal nitride may include at least one of tungsten nitride or hafnium nitride. For example, the metal oxide may include at least one of tungsten oxide or hafnium oxide.

A height <NUM> of the first isolation pattern <NUM> may be greater than a height <NUM> of the second isolation pattern <NUM>. For example, the height <NUM> of the first isolation pattern <NUM> may range from <NUM>% to <NUM>% of a total height (<NUM>+<NUM>) of the isolation pattern IP. For example, the height <NUM> of the first isolation pattern <NUM> may range from <NUM> times to <NUM> times the height <NUM> of the second isolation pattern <NUM>. For example, the height <NUM> of the first isolation pattern <NUM> may range from <NUM> to <NUM>. The term 'height' may mean a distance measured in a direction (e.g., the third direction D3) perpendicular to the second surface 100b of the substrate <NUM>.

The semiconductor pattern <NUM> may penetrate at least a portion of the substrate <NUM>. The semiconductor pattern <NUM> may be disposed between the plurality of pixel regions PX. The semiconductor pattern <NUM> fills a lower portion of the second trench TR2. The semiconductor pattern <NUM> may cover the bottom surface of the second trench TR2. The semiconductor pattern <NUM> may cover an inner side surface of the first isolation pattern <NUM> and may be in contact with the first isolation pattern <NUM>. A top surface of the semiconductor pattern <NUM> may be located at a lower level than the first surface 100a of the substrate <NUM>. A bottom surface of the semiconductor pattern <NUM> may correspond to the bottom surface 150b of the deep device isolation pattern <NUM> and may be substantially coplanar with the second surface 100b of the substrate <NUM>. The semiconductor pattern <NUM> may include a conductive material, for example, a semiconductor material doped with dopants. The dopants may have a P-type or an N-type. For example, the semiconductor pattern <NUM> may include doped poly-silicon.

The insulating pattern <NUM> may be disposed on the semiconductor pattern <NUM>. The insulating pattern <NUM> may be disposed in the shallow device isolation pattern <NUM>. The insulating pattern <NUM> may penetrate the shallow device isolation pattern <NUM> so as to be in contact with the semiconductor pattern <NUM>. The insulating pattern <NUM> may be spaced apart from the shallow device isolation pattern <NUM> by the second isolation pattern <NUM>. For example, the insulating pattern <NUM> may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

According to an embodiment, the isolation pattern IP of the deep device isolation pattern <NUM> may include at least two or more isolation patterns including different materials. More particularly, the first isolation pattern <NUM> adjacent to the second surface 100b of the substrate <NUM> to which light will be incident may include the low refractive index (LRI) material, and the second isolation pattern <NUM> adjacent to the first surface 100a of the substrate <NUM> may include the high-k material. Accordingly, incident light may be totally reflected by the first isolation pattern <NUM>, and thus cross-talk between the pixel regions PX adjacent to each other may be effectively prevented and a loss of light sensitivity may be minimized. In addition, noise may be minimized by the second isolation pattern <NUM>, and thus a signal-to-noise ratio (SNR) may be improved.

Referring again to <FIG> and <FIG>, transfer transistors TX and logic transistors RX, SX and DX may be disposed on the first surface 100a of the substrate <NUM>. Each of the transistors TX, RX, SX and DX may be disposed on a corresponding active region ACT of each of the pixel regions PX. The transfer transistor TX may include a transfer gate TG and a floating diffusion region FD, which are disposed on and in a corresponding active region ACT, respectively. A lower portion of the transfer gate TG may be inserted in the substrate <NUM>, and an upper portion of the transfer gate TG may protrude above the first surface 100a of the substrate <NUM>. A gate dielectric layer GI may be disposed between the transfer gate TG and the substrate <NUM>. The floating diffusion region FD may be disposed in the corresponding active region ACT at a side of the transfer gate TG. The floating diffusion region FD may be a region doped with dopants (e.g., N-type dopants) having the second conductivity type different from the first conductivity type of the substrate <NUM>.

The drive transistor DX may include a drive gate SFG on a corresponding active region ACT, and the selection transistor SX may include a selection gate SG on a corresponding active region ACT. The reset transistor RX may include a reset gate RG on a corresponding active region ACT. An additional gate dielectric layer GI may be disposed between each of the drive, selection and reset gates SFG, SG and RG and the substrate <NUM>.

The interconnection layer <NUM> may be disposed on the first surface 100a of the substrate <NUM>. The interconnection layer <NUM> may include a first interlayer insulating layer <NUM>, a second interlayer insulating layer <NUM> and a third interlayer insulating layer <NUM>, which are sequentially stacked on the first surface 100a of the substrate <NUM>. The interconnection layer <NUM> may further include contact plugs BCP in the first interlayer insulating layer <NUM>, first interconnection patterns <NUM> in the second interlayer insulating layer <NUM>, and second interconnection patterns <NUM> in the third interlayer insulating layer <NUM>. The first interlayer insulating layer <NUM> may be disposed on the first surface 100a of the substrate <NUM> to cover the transistors TX, RX, SX and DX, and the contact plugs BCP may be connected to terminals of the transistors TX, RX, SX and DX. The contact plugs BCP may be connected to corresponding ones of the first interconnection patterns <NUM>, and the first interconnection patterns <NUM> may be connected to corresponding ones of the second interconnection patterns <NUM>. The first and second interconnection patterns <NUM> and <NUM> may be electrically connected to the transistors TX, RX, SX and DX through the contact plugs BCP. Each of the first to third interlayer insulating layers <NUM>, <NUM> and <NUM> may include an insulating material, and the contact plugs BCP, the first interconnection patterns <NUM> and the second interconnection patterns <NUM> may include a conductive material.

The light transmitting layer <NUM> may be disposed on the second surface 100b of the substrate <NUM>. The light transmitting layer <NUM> may include a plurality of color filters CF and a plurality of micro lenses <NUM>. The light transmitting layer <NUM> may collect and filter light incident from the outside and may provide the light to the photoelectric conversion layer <NUM>.

The micro lenses <NUM> may be provided on the second surface 100b of the substrate <NUM>. Each of the micro lenses <NUM> may vertically (e.g., in the third direction D3) overlap with the photoelectric conversion region PD of a corresponding pixel region PX. The micro lenses <NUM> may have convex shapes to concentrate or collect light incident to the pixel regions PX.

The color filters CF may be disposed between the second surface 100b of the substrate <NUM> and the micro lenses <NUM>. Each of the color filters CF may vertically (e.g., in the third direction D3) overlap with the photoelectric conversion region PD of a corresponding pixel region PX. Each of the color filters CF may include a red, green or blue color filter, depending on a corresponding unit pixel. The color filters CF may be two-dimensionally arranged, and in certain embodiments, each of the color filters CF may include a yellow filter, a magenta filter, or a cyan filter.

An anti-reflection layer <NUM> may be disposed on the second surface 100b of the substrate <NUM>. The anti-reflection layer <NUM> may be disposed between the second surface 100b of the substrate <NUM> and the color filters CF. The anti-reflection layer <NUM> may conformally cover the second surface 100b of the substrate <NUM>. The anti-reflection layer <NUM> may prevent reflection of light incident to the second surface 100b of the substrate <NUM> to allow the light to smoothly reach the photoelectric conversion region PD. For example, the anti-reflection layer <NUM> may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material (e.g., hafnium oxide or aluminum oxide).

A first passivation layer <NUM> may be disposed between the anti-reflection layer <NUM> and the color filters CF. A second passivation layer <NUM> may be disposed between the color filters CF and the micro lenses <NUM>. The first passivation layer <NUM> may conformally cover the anti-reflection layer <NUM>. The first passivation layer <NUM> may include at least one of, for example, a metal oxide or a nitride. For example, the metal oxide may include aluminum oxide, and the nitride may include silicon nitride.

A grid pattern <NUM> may be provided between the pixel regions PX. The grid pattern <NUM> may be disposed between the first passivation layer <NUM> and the color filters CF. The grid pattern <NUM> may vertically overlap with the deep device isolation pattern <NUM>. The grid pattern <NUM> may have a lattice or grid shape when viewed in a plan view. The grid pattern <NUM> may guide light incident to the second surface 100b of the substrate <NUM> in such a way that the light is incident into the photoelectric conversion region PD. The grid pattern <NUM> may include at least one of a metal material or a low refractive index (LRI) material. The metal material may include at least one of, for example, tungsten or titanium. For example, the low refractive index (LRI) material may include at least one of materials having refractive indexes lower than refractive indexes of silicon oxide and the color filters CF.

<FIG> is a cross-sectional view taken along the line I-I' of <FIG> to illustrate an image sensor according to an example embodiment. <FIG> is an enlarged view of a portion 'B' of <FIG>. Hereinafter, differences between the present embodiments and the above embodiments of <FIG> will be mainly described for the purpose of ease and convenience in explanation.

Referring to <FIG> and <FIG>, an image sensor according to an example embodiment may include a photoelectric conversion layer <NUM>, an interconnection layer <NUM>, and a light transmitting layer <NUM>.

A deep device isolation pattern <NUM> may include an isolation pattern IP, a semiconductor pattern <NUM>, and an insulating pattern <NUM>. The isolation pattern IP may include a first isolation pattern <NUM>, a second isolation pattern <NUM>, and a third isolation pattern <NUM>. The third isolation pattern <NUM> may be disposed in the substrate <NUM>. The third isolation pattern <NUM> may be disposed on the second isolation pattern <NUM> and may be disposed between the first surface 100a of the substrate <NUM> and the second isolation pattern <NUM>.

The third isolation pattern <NUM> may penetrate the shallow device isolation pattern <NUM> and may penetrate a portion of the substrate <NUM>. The third isolation pattern <NUM> may extend from the first surface 100a of the substrate <NUM> into the substrate <NUM>. A top surface of the third isolation pattern <NUM> may be substantially coplanar with the first surface 100a of the substrate <NUM>. A bottom surface of the third isolation pattern <NUM> may be disposed in the substrate <NUM>. The third isolation pattern <NUM> may extend from the side surface of the semiconductor pattern <NUM> onto the side surface of the insulating pattern <NUM>. The third isolation pattern <NUM> may extend between the shallow device isolation pattern <NUM> and the insulating pattern <NUM>.

A second interface IF2 at which the second isolation pattern <NUM> is in contact with the third isolation pattern <NUM> may be located at a lower level than the bottom surface of the shallow device isolation pattern <NUM>. The second interface IF2 may be spaced apart from the shallow device isolation pattern <NUM>. The second interface IF2 may be located at a lower level than the bottom surface of the first trench TR1. The second interface IF2 may be located at a level between the bottom surface of the device isolation pattern <NUM> and the first interface IF <NUM>.

The third isolation pattern <NUM> may include a lower portion 155BP disposed under the shallow device isolation pattern <NUM>, and an upper portion 155UP penetrating the shallow device isolation pattern <NUM>. The lower portion 155BP of the third isolation pattern <NUM> may have a first side surface 155OS adjacent to (or in contact with) the substrate <NUM>, and a second side surface 155IS adjacent to (or in contact with) the semiconductor pattern <NUM>. The second isolation pattern <NUM> may have a first side surface 153OS adjacent to (or in contact with) the substrate <NUM>, and a second side surface 153IS adjacent to (or in contact with) the semiconductor pattern <NUM>. The lower portion 155BP of the third isolation pattern <NUM> may be aligned with the second isolation pattern <NUM>. More particularly, the first side surface 155OS of the lower portion 155BP of the third isolation pattern <NUM> may be aligned with the first side surface 153OS of the second isolation pattern <NUM>, and the second side surface 155IS of the lower portion 155BP of the third isolation pattern <NUM> may be aligned with the second side surface 153IS of the second isolation pattern <NUM>. The first side surface 155OS of the lower portion 155BP of the third isolation pattern <NUM> may be coplanar with the first side surface 153OS of the second isolation pattern <NUM>, and the second side surface 155IS of the lower portion 155BP of the third isolation pattern <NUM> may be coplanar with the second side surface 153IS of the second isolation pattern <NUM>. In other words, as shown, e.g., in <FIG> and <FIG>, the lower portion 155BP of the third isolation pattern <NUM> and the second isolation pattern <NUM> may not have a stepped surface therebetween.

The third isolation pattern <NUM> may include a different material from that of the second isolation pattern <NUM>. The third isolation pattern <NUM> may include an insulating material (e.g., a third insulating material), for example, a high-k material. For example, a dielectric constant (k) of the third isolation pattern <NUM> may range from <NUM> to <NUM>. For example, the third isolation pattern <NUM> may include a material having a dielectric constant (k) higher than that of the second isolation pattern <NUM>. However, embodiments are not limited thereto. The third isolation pattern <NUM> may include at least one of, for example, a nitride, a metal nitride, or a metal oxide. For example, the nitride may include silicon nitride. For example, the metal nitride may include at least one of tungsten nitride or hafnium nitride. For example, the metal oxide may include at least one of tungsten oxide or hafnium oxide.

In some embodiments, a height <NUM> of the first isolation pattern <NUM> may be greater than a total height (<NUM>+<NUM>) of the second isolation pattern <NUM> and the third isolation pattern <NUM>. For example, the height <NUM> of the first isolation pattern <NUM> may range from <NUM> times to <NUM> times the total height (<NUM>+<NUM>) of the second isolation pattern <NUM> and the third isolation pattern <NUM>. Except for the descriptions of the third isolation pattern <NUM>, other components and features of the image sensor according to the present embodiments may be substantially the same as corresponding components and features of the image sensor described above with reference to <FIG>.

<FIG> are cross-sectional views corresponding to the line I-I' of <FIG> to illustrate a method of manufacturing an image sensor according to an example embodiment. The descriptions to the same features as described with reference to <FIG> will be omitted or mentioned briefly for the purpose of ease and convenience in explanation.

Referring to <FIG> and <FIG>, a substrate <NUM> having a first surface 100a and a second surface 100b which are opposite to each other may be provided. A first trench TR1 may be formed adjacent to the first surface 100a of the substrate <NUM>. The formation of the first trench TR1 may include forming a first mask pattern MP on the first surface 100a of the substrate <NUM>, and etching the substrate <NUM> using the first mask pattern MP as an etch mask. The first trench TR1 may define active regions ACT in the substrate <NUM>.

Referring to <FIG> and <FIG>, a device isolation layer <NUM> may be formed on the first surface 100a of the substrate <NUM>. The device isolation layer <NUM> may fill the first trench TR1 and may cover the first mask pattern MP. The device isolation layer <NUM> may include at least one of, for example, silicon oxide, silicon nitride, or silicon oxynitride.

Referring to <FIG> and <FIG>, a second trench TR2 may be formed in the substrate <NUM>. The formation of the second trench TR2 may include forming a second mask pattern defining a region, in which the second trench TR2 will be formed, on the device isolation layer <NUM>, and etching the device isolation layer <NUM> and the substrate <NUM> using the second mask pattern as an etch mask. A bottom surface of the second trench TR2 may be located at a higher level than the second surface 100b of the substrate <NUM>. The device isolation layer <NUM> may be etched more (along the second direction D2) than the substrate <NUM>, and thus an upper region of the second trench TR2 may be further expanded and a portion of a bottom surface of the first trench TR1 may be exposed. A plurality of pixel regions PX may be defined in the substrate <NUM> by the second trench TR2. Each of the pixel regions PX may include the active regions ACT defined by the first trench TR1.

Referring to <FIG> and <FIG>, a first isolation layer <NUM> may be formed on the substrate <NUM>. The first isolation layer <NUM> may conformally cover an inner surface (i.e., an inner side surface and the bottom surface) of the second trench TR2. The first isolation layer <NUM> may cover the portion of the bottom surface of the first trench TR1, which is exposed by the second trench TR2. The first isolation layer <NUM> may conformally cover the expanded upper region of the second trench TR2 and may extend to cover a top surface of the device isolation layer <NUM>. For example, the first isolation layer <NUM> may include an insulating material, e.g., a low refractive index (LRI) material. For example, the first isolation layer <NUM> may include an oxide such as silicon oxide.

Referring to <FIG> and <FIG>, a semiconductor pattern <NUM> may be formed to fill a lower region of the second trench TR2. The formation of the semiconductor pattern <NUM> may include forming a conductive layer filling the second trench TR2, and etching the conductive layer by an etch-back process. The conductive layer may include a conductive material, for example, a semiconductor material doped with dopants. For example, the conductive layer may include doped poly-silicon.

Referring to <FIG> and <FIG>, an etching process may be performed to form a first isolation pattern <NUM>. The formation of the first isolation pattern <NUM> may include etching a portion of the first isolation layer <NUM>. By the etching process, the first isolation layer <NUM> exposed by the semiconductor pattern <NUM> may be removed and a portion of the first isolation layer <NUM> disposed in an upper portion of the second trench TR2 may be removed. Thus, an empty space may be formed between an upper portion of the second trench TR2 and an upper portion of the semiconductor pattern <NUM>, and a top surface of the first isolation pattern <NUM> may be exposed. For example, the etching process may be a wet etching process using an etchant, and an etch rate of the first isolation layer <NUM> by the etchant may be higher than those of the substrate <NUM> and the semiconductor pattern <NUM> by the etchant. A process time of the etching process and/or a concentration of the etchant may be appropriately adjusted, and thus the whole of the first isolation layer <NUM> may not be removed.

Referring to <FIG> and <FIG>, a second isolation layer <NUM> may be formed on the substrate <NUM>. The second isolation layer <NUM> may fill the empty space between the upper portion of the second trench TR2 and the upper portion of the semiconductor pattern <NUM>. The second isolation layer <NUM> may conformally cover the expanded upper region of the second trench TR2 and may extend to cover the top surface of the device isolation layer <NUM>. For example, the second isolation layer <NUM> may include an insulating material, e.g., a high-k material. For example, the second isolation layer <NUM> may include at least one of a nitride, a metal nitride, or a metal oxide. For example, the nitride may include silicon nitride. For example, the metal nitride may include at least one of tungsten nitride or hafnium nitride. For example, the metal oxide may include at least one of tungsten oxide or hafnium oxide.

Referring to <FIG> and <FIG>, an insulating pattern <NUM> may be formed to fill the upper region of the second trench TR2. For example, the formation of the insulating pattern <NUM> may include forming an insulating layer filling a remaining portion of the second trench TR2 on the substrate <NUM> having the semiconductor pattern <NUM>, and planarizing the insulating layer, the second isolation layer <NUM> and the device isolation layer <NUM> until the first surface 100a of the substrate <NUM> is exposed. The insulating layer may include at least one of, for example, silicon oxide, silicon nitride, or silicon oxynitride. The first mask pattern MP may be removed by the planarization process. The insulating pattern <NUM>, a second isolation pattern <NUM> and a shallow device isolation pattern <NUM> may be formed by the planarizing of the insulating layer, the second isolation layer <NUM> and the device isolation layer <NUM>, respectively. The first isolation pattern <NUM> and the second isolation pattern <NUM> may be referred to as an isolation pattern IP. Thus, a deep device isolation pattern <NUM> including the isolation pattern IP, the semiconductor pattern <NUM> and the insulating pattern <NUM> may be formed.

A photoelectric conversion region PD may be formed in each of the plurality of pixel regions PX. For example, the formation of the photoelectric conversion region PD may include injecting dopants having the second conductivity type (e.g., an N-type) different from the first conductivity type (e.g., a P-type) into the substrate <NUM>.

Transistors TX, RX, SX and DX may be formed on the first surface 100a of the substrate <NUM> and may be formed on each of the pixel regions PX. For example, the formation of a transfer transistor TX may include forming a floating diffusion region FD by doping a portion of a corresponding active region ACT with dopants, and forming a transfer gate TG on the corresponding active region ACT. The formation of a drive transistor DX, a selection transistor SX and a reset transistor RX may include forming dopant regions by doping portions of corresponding active regions ACT with dopants, and forming a drive gate SFG, a selection gate SG and a reset gate RG on the corresponding active regions ACT.

Referring to <FIG>, an interconnection layer <NUM> may be formed on the first surface 100a of the substrate <NUM>. More particularly, a first interlayer insulating layer <NUM> may be formed on the first surface 100a of the substrate <NUM> and may cover the transistors TX, RX, SX and DX. Contact plugs BCP may be formed in the first interlayer insulating layer <NUM> and may be connected to terminals of the transistors TX, RX, SX and DX. A second interlayer insulating layer <NUM> and a third interlayer insulating layer <NUM> may be sequentially formed on the first interlayer insulating layer <NUM>. First interconnection patterns <NUM> and second interconnection patterns <NUM> may be formed in the second interlayer insulating layer <NUM> and the third interlayer insulating layer <NUM>, respectively. The first and second interconnection patterns <NUM> and <NUM> may be electrically connected to the transistors TX, RX, SX and DX through the contact plugs BCP.

A thinning process may be performed on the second surface 100b of the substrate <NUM>. Portions of the substrate <NUM> and the deep device isolation pattern <NUM> may be removed by the thinning process. Due to the thinning process, a lower portion of the deep device isolation pattern <NUM> may be removed, and a bottom surface 150b of the deep device isolation pattern <NUM> may be substantially coplanar with the second surface 100b of the substrate <NUM>. A photoelectric conversion layer <NUM> may be formed by the manufacturing processes described above.

Referring again to <FIG> and <FIG>, a light transmitting layer <NUM> may be formed on the second surface 100b of the substrate <NUM>. In detail, an anti-reflection layer <NUM> and a first passivation layer <NUM> may be sequentially formed on the second surface 100b of the substrate <NUM>. A grid pattern <NUM> may be formed on the first passivation layer <NUM> and may vertically overlap with the deep device isolation pattern <NUM>. For example, the formation of the grid pattern <NUM> may include depositing a metal layer on the first passivation layer <NUM>, and patterning the metal layer. Color filters CF may be formed on the first passivation layer <NUM> and may be formed to cover the grid pattern <NUM>. The color filters CF may be disposed on the pixel regions PX, respectively. A second passivation layer <NUM> may be formed on the color filters CF, and micro lenses <NUM> may be formed on the second passivation layer <NUM>.

<FIG> are cross-sectional views corresponding to the line I-I' of <FIG> to illustrate a method of manufacturing an image sensor according to an example embodiment. Hereinafter, the descriptions to the same features as described with reference to <FIG> will be omitted for the purpose of ease and convenience in explanation.

Referring to <FIG>, <FIG> and <FIG>, after the formation of the second isolation layer <NUM>, the second isolation layer <NUM> may be etched to form a second isolation pattern <NUM>. The formation of the second isolation pattern <NUM> may include etching a portion of the second isolation layer <NUM>. By the etching process, the second isolation layer <NUM> exposed by the semiconductor pattern <NUM> may be removed and a portion of the second isolation layer <NUM> disposed in an upper portion of the second trench TR2 may be removed. Thus, an empty space may be formed between an upper portion of the second trench TR2 and an upper portion of the semiconductor pattern <NUM>, and a top surface of the second isolation pattern <NUM> may be exposed. For example, the etching process may be a wet etching process using an etchant, and an etch rate of the second isolation layer <NUM> by the etchant may be higher than those of the substrate <NUM> and the semiconductor pattern <NUM> by the etchant. Since a process time of the etching process and/or a concentration of the etchant is/are appropriately adjusted, the whole of the second isolation layer <NUM> may not be removed.

Referring to <FIG> and <FIG>, a third isolation layer <NUM> may be formed on the substrate <NUM>. The third isolation layer <NUM> may fill the empty space between the upper portion of the second trench TR2 and the upper portion of the semiconductor pattern <NUM>. The third isolation layer <NUM> may conformally cover the expanded upper region of the second trench TR2 and may extend to cover the top surface of the device isolation layer <NUM>. The third isolation layer <NUM> may include a different material from that of the second isolation pattern <NUM>. For example, the third isolation layer <NUM> may include an insulating material, e.g., a high-k material. For example, the third isolation layer <NUM> may include at least one of a nitride, a metal nitride, or a metal oxide. For example, the nitride may include silicon nitride. For example, the metal nitride may include at least one of tungsten nitride or hafnium nitride. For example, the metal oxide may include at least one of tungsten oxide or hafnium oxide.

Referring to <FIG>, an insulating pattern <NUM> may be formed to fill the upper region of the second trench TR2. The insulating pattern <NUM> may be formed by the same method as described above with reference to <FIG>. The first isolation pattern <NUM>, the second isolation pattern <NUM> and the third isolation pattern <NUM> may be referred to as an isolation pattern IP. Thus, a deep device isolation pattern <NUM> including the isolation pattern IP, the semiconductor pattern <NUM> and the insulating pattern <NUM> may be formed.

An interconnection layer <NUM> may be formed on the first surface 100a of the substrate <NUM>. Transistors TX, RX, SX and DX may be formed on the first surface 100a of the substrate <NUM>, and a thinning process may be performed on the second surface 100b of the substrate <NUM> to form a photoelectric conversion layer <NUM>. The interconnection layer <NUM> and the photoelectric conversion layer <NUM> may be formed by substantially the same method as described above with reference to <FIG>.

Referring again to <FIG> and <FIG>, a light transmitting layer <NUM> may be formed on the second surface 100b of the substrate <NUM>. The light transmitting layer <NUM> may be formed by the same method as described above with reference to <FIG>.

<FIG> is a cross-sectional view taken along the line I-I' of <FIG> to illustrate an image sensor according to an example embodiment. Hereinafter, differences between the present embodiments and the above embodiments of <FIG> will be mainly described for the purpose of ease and convenience in explanation.

Referring to <FIG>, an image sensor according to an example embodiment may include a photoelectric conversion layer <NUM>, an interconnection layer <NUM>, and a light transmitting layer <NUM>. The photoelectric conversion layer <NUM> includes a substrate <NUM> including pixel regions PX, and a deep device isolation pattern <NUM> disposed in the substrate <NUM> between the pixel regions PX. The deep device isolation pattern <NUM> may extend from a second surface 100b of the substrate <NUM> toward a first surface 100a of the substrate <NUM>, and a bottom surface 150b of the deep device isolation pattern <NUM> may be located at a higher level than the first surface 100a of the substrate <NUM>. That is, the bottom surface 150b of the deep device isolation pattern <NUM> may be positioned at a level between the first surface 100a and the second surface 100b of the substrate <NUM>. Here, the term 'level' may mean a height from the first surface 100a of the substrate <NUM> toward the second surface 100b of the substrate <NUM> (e.g. as measured along the third direction D3). Note that in this embodiment, as the deep device isolation pattern <NUM> extends from the second surface 100b of the substrate <NUM> toward the first surface 100a of the substrate <NUM>, the bottom surface 150b of the deep device isolation pattern <NUM> is the surface that is located closest to the first surface 100a of the substrate <NUM>. This is in contrast to the embodiment of <FIG> and <FIG>, in which the deep device isolation pattern <NUM> extends from the first surface 100a of the substrate <NUM> to the second surface 100b of the substrate <NUM>, resulting in the bottom surface 150b of the deep device isolation pattern <NUM> being located closest to (e.g. coplanar with) the second surface 100b of the substrate <NUM>.

A shallow device isolation pattern <NUM> may be disposed adjacent to the first surface 100a of the substrate <NUM>. In some embodiments, the deep device isolation pattern <NUM> (i.e., the bottom surface 150b of the deep device isolation pattern <NUM>) may be spaced apart from the shallow device isolation pattern <NUM> (e.g. as measured along the third direction D3).

The deep device isolation pattern <NUM> may include a semiconductor pattern <NUM> penetrating a portion of the substrate <NUM>, and an isolation pattern IP disposed between the semiconductor pattern <NUM> and the substrate <NUM>. The isolation pattern IP may be disposed between each of the pixel regions PX and a side surface of the semiconductor pattern <NUM> and may extend between a bottom surface of the semiconductor pattern <NUM> and the substrate <NUM>. A bottom surface of the isolation pattern IP may correspond to the bottom surface 150b of the deep device isolation pattern <NUM>. Top surfaces of the isolation pattern IP and the semiconductor pattern <NUM> may be substantially coplanar with the second surface 100b of the substrate <NUM>.

The isolation pattern IP may include a first isolation pattern <NUM> adjacent to the second surface 100b of the substrate <NUM>, and a second isolation pattern <NUM> forming the bottom surface 150b of the deep device isolation pattern <NUM> (e.g. located closest to the first surface 100a of the substrate <NUM>). The first isolation pattern <NUM> may penetrate a portion of the substrate <NUM>. The first isolation pattern <NUM> may extend from the second surface 100b of the substrate <NUM> into the substrate <NUM>. The first isolation pattern <NUM> may be disposed between each of the pixel regions PX and the side surface of the semiconductor pattern <NUM>. A top surface of the first isolation pattern <NUM> may correspond to a top surface of the deep device isolation pattern <NUM> and may be substantially coplanar with the second surface 100b of the substrate <NUM>. A bottom surface of the first isolation pattern <NUM> may be disposed in the substrate <NUM>.

The second isolation pattern <NUM> may be disposed in the substrate <NUM>. The second isolation pattern <NUM> may be spaced apart from the first surface 100a of the substrate <NUM>. The second isolation pattern <NUM> may be disposed between each of the pixel regions PX and the side surface of the semiconductor pattern <NUM> and may extend between the bottom surface of the semiconductor pattern <NUM> and the substrate <NUM>. A bottom surface of the second isolation pattern <NUM> may correspond to the bottom surface 150b of the deep device isolation pattern <NUM>.

A first interface IF1 at which the first isolation pattern <NUM> is in contact with the second isolation pattern <NUM> may be spaced apart from the shallow device isolation pattern <NUM>. The first isolation pattern <NUM> may be aligned with the second isolation pattern <NUM>. More particularly, side surfaces of the first isolation pattern <NUM> may be aligned with or coplanar with corresponding side surfaces of the second isolation pattern <NUM>, respectively. A height <NUM> of the first isolation pattern <NUM> may be greater than a height <NUM> of the second isolation pattern <NUM>. Here, the term 'height' may mean a distance measured in a direction (e.g., the third direction D3) perpendicular to the first surface 100a of the substrate <NUM>.

Except for the photoelectric conversion layer <NUM> described above, the interconnection layer <NUM> and the light transmitting layer <NUM> may be substantially the same as described with reference to <FIG>.

<FIG> is a cross-sectional view taken along the line I-I' of <FIG> to illustrate an image sensor according to an example embodiment. Hereinafter, differences between the present embodiments and the above embodiments of <FIG>, <FIG>, <FIG> and <FIG> will be mainly described for the purpose of ease and convenience in explanation.

Referring to <FIG>, an image sensor according to an example embodiment may include a photoelectric conversion layer <NUM>, an interconnection layer <NUM>, and a light transmitting layer <NUM>. The photoelectric conversion layer <NUM> may include a substrate <NUM> including pixel regions PX, and a deep device isolation pattern <NUM> disposed in the substrate <NUM> between the pixel regions PX. The deep device isolation pattern <NUM> may extend from a second surface 100b of the substrate <NUM> toward a first surface 100a of the substrate <NUM>, and a bottom surface 150b of the deep device isolation pattern <NUM> may be located at a higher level than the first surface 100a of the substrate <NUM>. That is, the bottom surface 150b of the deep device isolation pattern <NUM> may be positioned at a level between the first surface 100a and the second surface 100b of the substrate <NUM>. Here, the term 'level' may mean a height from the first surface 100a of the substrate <NUM> toward the second surface 100b of the substrate <NUM> (e.g. as measured along the third direction D3).

A shallow device isolation pattern <NUM> may be disposed adjacent to the first surface 100a of the substrate <NUM>. In some embodiments, the deep device isolation pattern <NUM> (i.e., the bottom surface 150b of the deep device isolation pattern <NUM>) may be spaced apart from the shallow device isolation pattern <NUM>.

The isolation pattern IP may include a first isolation pattern <NUM> adjacent to the second surface 100b of the substrate <NUM>, a third isolation pattern <NUM> forming the bottom surface 150b of the deep device isolation pattern <NUM> (e.g. located closest to the first surface 100a of the substrate <NUM>), and a second isolation pattern <NUM> disposed between the first isolation pattern <NUM> and the third isolation pattern <NUM>. The first isolation pattern <NUM> may penetrate a portion of the substrate <NUM>. The first isolation pattern <NUM> may extend from the second surface 100b of the substrate <NUM> into the substrate <NUM>. The first isolation pattern <NUM> may be disposed between each of the pixel regions PX and a side surface of the semiconductor pattern <NUM>. A top surface of the first isolation pattern <NUM> may correspond to a top surface of the deep device isolation pattern <NUM> and may be substantially coplanar with the second surface 100b of the substrate <NUM>. A bottom surface of the first isolation pattern <NUM> may be disposed in the substrate <NUM>.

The second isolation pattern <NUM> may be disposed in the substrate <NUM>. The second isolation pattern <NUM> may be disposed between each of the pixel regions PX and the side surface of the semiconductor pattern <NUM>.

The third isolation pattern <NUM> may be disposed in the substrate <NUM>. The third isolation pattern <NUM> may be spaced apart from the first surface 100a of the substrate <NUM>. The third isolation pattern <NUM> may be disposed between each of the pixel regions PX and the side surface of the semiconductor pattern <NUM> and may extend between a bottom surface of the semiconductor pattern <NUM> and the substrate <NUM>. A bottom surface of the third isolation pattern <NUM> may correspond to the bottom surface 150b of the deep device isolation pattern <NUM>.

A second interface IF2 at which the second isolation pattern <NUM> is in contact with the third isolation pattern <NUM> may be spaced apart from the shallow device isolation pattern <NUM>. The first isolation pattern <NUM> may be aligned with the second isolation pattern <NUM>. More particularly, side surfaces of the first isolation pattern <NUM> may be aligned with or coplanar with corresponding side surfaces of the second isolation pattern <NUM>, respectively. The second isolation pattern <NUM> may be aligned with the third isolation pattern <NUM>. More particularly, the side surfaces of the second isolation pattern <NUM> may be aligned with or coplanar with corresponding side surfaces of the third isolation pattern <NUM>, respectively. A height <NUM> of the first isolation pattern <NUM> may be greater than a total height (<NUM>+<NUM>) of the second isolation pattern <NUM> and the third isolation pattern <NUM>. Here, the term 'height' may mean a distance measured in a direction (e.g., the third direction D3) perpendicular to the first surface 100a of the substrate <NUM>.

Referring to <FIG>, an image sensor according to an example embodiment may include a photoelectric conversion layer <NUM>, an interconnection layer <NUM>, and a light transmitting layer <NUM>. The photoelectric conversion layer <NUM> may include a substrate <NUM> including pixel regions PX, and a deep device isolation pattern <NUM> disposed in the substrate <NUM> between the pixel regions PX. The deep device isolation pattern <NUM> may extend from a first surface 100a of the substrate <NUM> toward a second surface 100b of the substrate <NUM>. A bottom surface 150b of the deep device isolation pattern <NUM> may be located at a higher level than the second surface 100b of the substrate <NUM>. A shallow device isolation pattern <NUM> may be disposed adjacent to the first surface 100a of the substrate <NUM>.

The photoelectric conversion layer <NUM> may further include a back isolation pattern <NUM>. The back isolation pattern <NUM> may extend from the second surface 100b of the substrate <NUM> into the substrate <NUM>. The back isolation pattern <NUM> may fill a back trench BTR recessed from the second surface 100b of the substrate <NUM>. The back isolation pattern <NUM> may be provided between the pixel regions PX. The back isolation pattern <NUM> may have a lattice or grid structure surrounding each of the pixel regions PX when viewed in a plan view. In some embodiments, the back isolation pattern <NUM> may extend to cover the second surface 100b of the substrate <NUM>. The deep device isolation pattern <NUM> may be in contact with the back isolation pattern <NUM>. Thus, the deep device isolation pattern <NUM> and the back isolation pattern <NUM> may define the pixel regions PX. The back isolation pattern <NUM> may include at least one of, for example, a silicon-based insulating material or a metal oxide.

Except that the bottom surface 150b of the deep device isolation pattern <NUM> is spaced apart from the second surface 100b of the substrate <NUM> and is in contact with the back isolation pattern <NUM>, other features of the deep device isolation pattern <NUM> may be substantially the same as described with reference to <FIG>.

Except that the bottom surface 150b of the deep device isolation pattern <NUM> is spaced apart from the second surface 100b of the substrate <NUM> and is in contact with the back isolation pattern <NUM>, other components and features of the deep device isolation pattern <NUM> may be substantially the same as described with reference to <FIG>, <FIG>, <FIG> and <FIG>.

<FIG> is a plan view illustrating an image sensor according to an example embodiment. <FIG> is a cross-sectional view taken along a line II-II' of <FIG> to illustrate an image sensor according to an example embodiment.

Referring to <FIG> and <FIG>, an image sensor may include a substrate <NUM> including a pixel array region AR, an optical black region OB and a pad region PR, an interconnection layer <NUM> on a first surface 100a of the substrate <NUM>, a base substrate <NUM> on the interconnection layer <NUM>, and a light transmitting layer <NUM> on a second surface 100b of the substrate <NUM>. The interconnection layer <NUM> may be disposed between the first surface 100a of the substrate <NUM> and the base substrate <NUM>. The interconnection layer <NUM> may include an upper interconnection layer <NUM> adjacent to the first surface 100a of the substrate <NUM>, and a lower interconnection layer <NUM> between the upper interconnection layer <NUM> and the base substrate <NUM>. The pixel array region AR may include a plurality of pixel regions PX, and a deep device isolation pattern <NUM> disposed between the pixel regions PX. The pixel array region AR may be substantially the same as the image sensor described with reference to <FIG>. For example, the deep device isolation pattern <NUM> may be substantially the same as the deep device isolation pattern <NUM> described with reference to <FIG>.

A first connection structure <NUM>, a first contact <NUM> and a bulk color filter <NUM> may be disposed on the optical black region OB of the substrate <NUM>. The first connection structure <NUM> may include a first light blocking pattern <NUM>, a first separation pattern <NUM>, and a first capping pattern <NUM>. The first light blocking pattern <NUM> may be disposed on the second surface 100b of the substrate <NUM>. The first light blocking pattern <NUM> may cover the first passivation layer <NUM> and may conformally cover an inner surface of each of a third trench TR3 and a fourth trench TR4. The first light blocking pattern <NUM> may penetrate the photoelectric conversion layer <NUM> and the upper interconnection layer <NUM>. The first light blocking pattern <NUM> may be connected to the deep device isolation pattern <NUM> of the photoelectric conversion layer <NUM> and may be connected to interconnection lines provided in the upper and lower interconnection layers <NUM> and <NUM>. Thus, the first connection structure <NUM> may electrically connect the photoelectric conversion layer <NUM> and the interconnection layer <NUM>. The first light blocking pattern <NUM> may include a metal material (e.g., tungsten). The first light blocking pattern <NUM> may block light incident to the optical black region OB.

The first contact <NUM> may fill a remaining portion of the third trench TR3. The first contact <NUM> may include a metal material (e.g., aluminum). The first contact <NUM> may be connected to the deep device isolation pattern <NUM>. The first separation pattern <NUM> may fill a remaining portion of the fourth trench TR4. The first separation pattern <NUM> may penetrate the photoelectric conversion layer <NUM> and may penetrate a portion of the interconnection layer <NUM>. The first separation pattern <NUM> may include an insulating material. The first capping pattern <NUM> may be disposed on the first separation pattern <NUM>.

The bulk color filter <NUM> may be disposed on the first connection structure <NUM> and the first contact <NUM>. The bulk color filter <NUM> may cover the first connection structure <NUM> and the first contact <NUM>. A first protective layer <NUM> may be disposed on the bulk color filter <NUM> to seal or encapsulate the bulk color filter <NUM>.

A photoelectric conversion region PD may be provided in a corresponding pixel region PX of the optical black region OB. The photoelectric conversion region PD of the optical black region OB may be a region doped with dopants (e.g., N-type dopants) having the second conductivity type different from the first conductivity type of the substrate <NUM>. The photoelectric conversion region PD of the optical black region OB may have a structure similar to that of the photoelectric conversion regions PD of the pixel array region AR but may not perform the same operation (i.e., the operation of generating an electrical signal using received light) as the photoelectric conversion regions PD of the pixel array region AR.

A second connection structure <NUM>, a second contact <NUM> and a second protective layer <NUM> may be disposed on the pad region PR of the substrate <NUM>. The second connection structure <NUM> may include a second light blocking pattern <NUM>, a second separation pattern <NUM>, and a second capping pattern <NUM>.

The second light blocking pattern <NUM> may be disposed on the second surface 100b of the substrate <NUM>. The second light blocking pattern <NUM> may cover the first passivation layer <NUM> and may conformally cover an inner surface of each of a fifth trench TR5 and a sixth trench TR6. The second light blocking pattern <NUM> may penetrate the photoelectric conversion layer <NUM> and the upper interconnection layer <NUM>. The second light blocking pattern <NUM> may be connected to interconnection lines provided in the lower interconnection layer <NUM>. Thus, the second connection structure <NUM> may electrically connect the photoelectric conversion layer <NUM> and the interconnection layer <NUM>. The second light blocking pattern <NUM> may include a metal material (e.g., tungsten). The second light blocking pattern <NUM> may block light incident to the pad region PR.

The second contact <NUM> may fill a remaining portion of the fifth trench TR5. The second contact <NUM> may include a metal material (e.g., aluminum). The second contact <NUM> may function as an electrical connection path between the image sensor and an external device. The second separation pattern <NUM> may fill a remaining portion of the sixth trench TR6. The second separation pattern <NUM> may penetrate the photoelectric conversion layer <NUM> and may penetrate a portion of the interconnection layer <NUM>. The second separation pattern <NUM> may include an insulating material. The second capping pattern <NUM> may be disposed on the second separation pattern <NUM>. The second protective layer <NUM> may cover the second connection structure <NUM>.

A current applied through the second contact <NUM> may flow into the deep device isolation pattern <NUM> through the second light blocking pattern <NUM>, the interconnection lines of the interconnection layer <NUM> and the first light blocking pattern <NUM>. Electrical signals generated from the photoelectric conversion regions PD in the pixel regions PX of the pixel array region AR may be transmitted to the outside through the interconnection lines of the interconnection layer <NUM>, the second light blocking pattern <NUM> and the second contact <NUM>.

According to an embodiment, the isolation pattern of the deep device isolation pattern may include at least two or more isolation patterns including different materials. More particularly, the first isolation pattern adjacent to one surface of the substrate to which light is incident may include the low refractive index (LRI) material, and the second isolation pattern adjacent to another surface of the substrate may include the high-k material. Thus, light incident to the first isolation pattern may be totally reflected to effectively prevent cross-talk between the pixel regions adjacent to each other and to minimize a loss of light sensitivity. In addition, noise may be minimized by the second isolation pattern, and thus a signal-to-noise ratio (SNR) may be improved.

Claim 1:
An image sensor comprising:
a substrate (<NUM>) comprising a plurality of pixel regions (PX), the substrate (<NUM>) having a first surface (100a), a second surface (100b) opposite the first surface (100a), and a first trench (TR1) recessed from the first surface (100a);
a shallow device isolation pattern (<NUM>) provided in the first trench (TR1); and
a deep device isolation pattern (<NUM>) provided in the substrate (<NUM>) between pixel regions (PX) of the plurality of pixel regions (PX),
wherein the deep device isolation pattern (<NUM>) is disposed in a second trench (TR2) that penetrates the shallow device isolation pattern (<NUM>) and extends into the substrate (<NUM>) towards the second surface (100b),
wherein the deep device isolation pattern (<NUM>) comprises a semiconductor pattern (<NUM>) penetrating at least a portion of the substrate (<NUM>), and an isolation pattern (IP) provided between the substrate (<NUM>) and the semiconductor pattern (<NUM>),
wherein the semiconductor pattern (<NUM>) fills a lower portion of the second trench (TR2),
wherein the isolation pattern (IP) comprises a first isolation pattern (<NUM>) adjacent to the second surface of the substrate (100b), and a second isolation pattern (<NUM>) adjacent to the first surface of the substrate (100a),
wherein a first interface (IF1) at which the first isolation pattern (<NUM>) contacts the second isolation pattern (<NUM>) is spaced apart from the shallow device isolation pattern (<NUM>),
wherein the first isolation pattern (<NUM>) comprises a first material, and the second isolation pattern (<NUM>) comprises a second material that is different from the first material,
wherein the deep device isolation pattern (<NUM>) further comprises an insulating pattern (<NUM>) disposed on the semiconductor pattern (<NUM>) and penetrating the shallow device isolation pattern (<NUM>),
wherein the insulating pattern (<NUM>) fills an upper portion of the second trench (TR2), and
wherein the isolation pattern (IP) extends between the shallow device isolation pattern (<NUM>) and the insulating pattern (<NUM>).