Patent Description:
The present application claims priority of <CIT>, entitled "BOTTOM ELECTRODE VIA STRUCTURES FOR MICROMACHINED ULTRASONIC TRANSDUCER DEVICES".

The present disclosure relates generally to micromachined ultrasonic transducers and, more specifically, to bottom electrode via structures for micromachined ultrasonic transducer cavities.

Ultrasound devices may be used to perform diagnostic imaging and/or treatment, using sound waves with frequencies that are higher than those audible to humans. When pulses of ultrasound are transmitted into tissue, sound waves are reflected off the tissue with different tissues reflecting varying degrees of sound. These reflected sound waves may then be recorded and displayed as an ultrasound image to the operator. The strength (amplitude) of the sound signal and the time it takes for the wave to travel through the body provide information used to produce the ultrasound images.

Some ultrasound imaging devices may be fabricated using micromachined ultrasonic transducers, including a flexible membrane suspended above a substrate. A cavity is located between part of the substrate and the membrane, such that the combination of the substrate, cavity and membrane form a variable capacitor. When actuated by an appropriate electrical signal, the membrane generates an ultrasound signal by vibration. In response to receiving an ultrasound signal, the membrane is caused to vibrate and, as a result, generates an output electrical signal. <CIT> describes a method of manufacturing a capacitive electromechanical transducer. A first electrode is formed on a substrate, an insulating layer which has an opening leading to the first electrode is formed on the first electrode, and a sacrificial layer is formed on the insulating layer. A membrane having a second electrode is formed on the sacrificial layer, and an aperture is provided as an etchant inlet in the membrane. The sacrificial layer is etched to form a cavity, and then the aperture serving as an etchant inlet is sealed. <CIT> describes an electro-acoustic transducer including a conductive substrate provided with at least one cell and at least one electrode, and a pad substrate disposed corresponding to the conductive substrate and provided with at least one pad corresponding to the electrode, in which at least one of the electrode and the pad includes an electric pattern for electric connection and at least one dummy pattern that is provided around the electric pattern to be separated the electric pattern. <CIT> describes complementary metal oxide semiconductor (CMOS) ultrasonic transducers (CUTs) and methods for forming CUTs. The CUTs may include monolithically integrated ultrasonic transducers and integrated circuits for operating in connection with the transducers. The CUTs may be used in ultrasound devices such as ultrasound imaging devices and/or high intensity focused ultrasound (HIFU) devices.

In one aspect, an ultrasonic transducer device includes a bottom electrode layer of a transducer cavity disposed over a substrate, and a plurality of vertical interconnect accesses (vias) that electrically connect the bottom electrode layer with the substrate. A first portion of the bottom electrode layer comprises a transducer bottom electrode and a second portion of the bottom electrode layer comprises a bypass metal structure that is electrically isolated from the transducer bottom electrode. A first portion of the plurality of vias connect to the bypass metal structure and are disposed in locations directly beneath a footprint of the transducer cavity. A bottom cavity layer is disposed over the bottom electrode layer, and one or more openings are formed in the bottom cavity layer so as to expose the bypass metal structure of the bottom electrode layer to the transducer cavity, wherein locations of the one or more openings correspond to locations where a majority of the first portion of the plurality of vias are not disposed directly beneath.

According to an embodiment, the one or more openings formed in the bottom cavity layer comprise segments disposed proximate an outer perimeter of the transducer cavity, the segments being spaced apart from one another about the outer perimeter of the transducer cavity, and a transducer membrane sealing the transducer cavity. The bypass metal structure serves as a getter material to consume one or more gaseous materials present in the transducer cavity during bonding of the transducer membrane.

Various aspects and embodiments of the application will be described with reference to the following figures. Items appearing in multiple figures are indicated by the same reference number in all the figures in which they appear.

The techniques and structures described herein relate to metallic getter opening patterns used during cavity bonding operations in the manufacturing of micromachined ultrasonic transducer (MUT) cavities. In one aspect, a segmented getter opening pattern provides the same or substantially similar gettering benefits with respect to a fully annular getter opening pattern, and with at least an additional advantage of ensuring good electrical conductivity of the bypass capacitor electrodes even in the event that if the getter opening dry etching process is over-etched. This in turn may provide improved process margin, which is desired for large volume manufacturing of MUT devices.

One type of transducer suitable for use in ultrasound imaging devices is a MUT, which can be fabricated from, for example, silicon and configured to transmit and receive ultrasound energy. MUTs may include capacitive micromachined ultrasonic transducers (CMUTs) and piezoelectric micromachined ultrasonic transducers (PMUTs), both of which can offer several advantages over more conventional transducer designs such as, for example, lower manufacturing costs and fabrication times and/or increased frequency bandwidth. With respect to the CMUT device, the basic structure is a parallel plate capacitor with a rigid bottom electrode and a top electrode residing on or within a flexible membrane. Thus, a cavity is defined between the bottom and top electrodes. In some designs (such as those produced by the assignee of the present application for example), a CMUT may be directly integrated on an integrated circuit that controls the operation of the transducer. One way of manufacturing a CMUT is to bond a membrane substrate to an integrated circuit substrate, such as a complementary metal oxide semiconductor (CMOS) substrate. This may be performed at temperatures sufficiently low to prevent damage to the devices of the integrated circuit.

Referring initially to <FIG>, which does not form part of the claimed subject-matter and is shown for illustration purposes only, there is shown a cross-sectional view of an exemplary micromachined ultrasonic transducer device <NUM>, such as a CMUT. The transducer device <NUM> includes a substrate, generally designated by <NUM>, (e.g., a CMOS substrate, such as silicon) having one or more layers, such as for example: CMOS integrated circuits and wiring layers (at or below region <NUM>), one more insulation/passivation layers <NUM>, and one or more wiring redistribution layers <NUM>. A transducer bottom electrode layer, designated generally at <NUM>, is disposed over the substrate <NUM> and includes patterned regions of a metal layer <NUM> (e.g., titanium (Ti)), between which are located regions of an insulation layer <NUM> (e.g., silicon oxide (SiO<NUM>)). In the illustrated example, first portions of the patterned metal layer <NUM> may serve as a transducer bottom electrode <NUM> (e.g., in a "donut" or ring configuration), while second portions of the patterned metal layer <NUM> may serve another function (e.g., a bypass metal structure <NUM>). As specific substrate and transducer bottom electrode patterns are not the focus of the present disclosure, only a single example is presented in the figures. It will be appreciated, however, that the present embodiments may also be implemented in conjunction with several other transducer electrode structures including (but not limited to), for example: the aforementioned donut shaped electrode pattern (e.g., interior metal removed), multiple segment or ring electrodes, and additional metal patterns used for other purposes besides bottom electrodes (e.g., cavity getter during bonding).

Still referring to <FIG>, electrically conductive vias <NUM> (e.g., tungsten (W)) electrically connect the one or more wiring redistribution layers <NUM> to the patterned metal layer <NUM> of the transducer bottom electrode layer <NUM>. The formation and specific locations of such vias <NUM> is discussed in further detail below. A bottom cavity layer <NUM> is disposed over the transducer bottom electrode layer <NUM>. The bottom cavity layer <NUM> may include, for example, an electrically insulating, thin film layer stack including an SiO<NUM> layer deposited by chemical vapor deposition (CVD) and an aluminum oxide (Al<NUM>O<NUM>) layer deposited by atomic layer deposition (ALD). A transducer cavity <NUM> is defined by lithographic patterning and etching of a membrane support layer <NUM> that is formed on the bottom cavity layer <NUM>. The membrane support layer <NUM> may be an insulating layer, such as SiO<NUM> for example, the remaining portions of which provide a support surface to which a flexible transducer membrane <NUM> (e.g., highly doped silicon at a concentration of about <NUM> × <NUM> atoms/cm3 to about <NUM> × <NUM> atoms/cm3 ) is bonded. In order to preserve the integrity and functionality of the various CMOS devices residing within the substrate <NUM> (such as CMOS circuits and wiring layers at or below region <NUM>), a relatively low temperature bonding process (e.g., less than about <NUM>) is employed for bonding the transducer membrane <NUM> to the membrane support layer <NUM>.

However, during bonding of the membrane substrate to the CMOS substrate, there may be a difference in cavity pressures across the die and wafer due to the water vapor and other gaseous byproducts and the propagation of the bond. This in turn may result in undesired variability of certain CMUT-based operating parameters such as for example, collapse voltage, as well as transmit/receive pressure sensitivity. Accordingly, it is desirable to be able to control cavity pressure within such a transducer device during the manufacturing process, as well as over the lifetime of the device. Thus, as additionally illustrated in <FIG>, a getter opening pattern <NUM> is defined (e.g., by etching) in the bottom cavity layer <NUM> prior to membrane bonding so as to expose a portion of the bypass metal structure <NUM> proximate the outer perimeter of the transducer cavity <NUM>. In one example (and as discussed in further detail below), the getter opening pattern <NUM> may be an annular or ring-shaped pattern etched into the bottom cavity layer <NUM> prior to bonding of the transducer membrane <NUM>. By exposing the metal material of the bypass metal structure <NUM>, gaseous material present in the cavity region (e.g., oxygen, nitrogen, argon, water vapor, etc.) may be consumed by the metal, resulting in a more uniform pressure across the various cavities <NUM> of the ultrasound device. Additional information regarding cavity gettering may be found in co-pending <CIT> and <CIT>, both assigned to the assignee of the present application.

In addition to maintaining desirable cavity pressures during bonding of the membrane substrate to the CMOS substrate, it is further desirable to have a smooth bonding interface between the bonded surfaces. In the example described, the bonding interface is represented by the top surface of the membrane support layer <NUM> and the bottom surface of the transducer membrane <NUM>. Such an interface desirably has a surface roughness of less than about <NUM> over a range of about <NUM> pm. During the manufacturing of structures such as the exemplary transducer device <NUM>, chemical mechanical polishing (CMP) may be used to planarize certain structures such as the metal layer <NUM>, the insulation layer <NUM>, and the material (e.g., W) of the vias <NUM> in order to provide a smooth bonding interface for downstream steps.

However, certain fabrication steps may introduce surface planarization difficulties resulting from individual vias being in relatively close proximity to one another. For example, dishing caused by erosion or protrusion caused by oxide buffering may occur if the CMP process is not well controlled or experiences variations/fluctuations. Any such surface planarization problems can in turn affect downstream layer formation planarity and ultimately negatively impact the transducer membrane bonding integrity. In the former case, dishing may result in the top surface of the insulating layer <NUM> being recessed below an ideal horizontal plane, in the vicinity of the vias <NUM>. In the latter case, oxide buffering might cause the vias <NUM> and portions of the insulation layer <NUM> (e.g., oxide) between the vias <NUM>, to extend above remaining upper surfaces of the insulation layer <NUM>.

One way to reduce the impact of (and/or eliminate altogether) via planarization operations in the formation of micromachined ultrasonic transducer devices may be to pattern and locate of the vias connecting the CMOS wiring redistribution layers to the transducer bottom electrode layer so as to be primarily confined below a cavity footprint of the transducers. An example of this approach is illustrated in conjunction with the micromachined ultrasonic transducer device <NUM> shown in <FIG> (where like elements are designated with like reference numbers). As will be noted by a comparison of <FIG> with <FIG>, the outermost sets of vias <NUM> shown in <FIG> have been relocated in <FIG> so as to be disposed directly beneath a footprint <NUM> of the transducer cavity <NUM>. This is the case for via connection to both the transducer bottom electrode structures <NUM> and the bypass metal structures <NUM> of the metal layer <NUM>. That is, the regions <NUM> beyond the footprint <NUM> of the transducer cavity <NUM> do not have any of the vias <NUM> disposed directly below. In this manner, any difficulties associated with the formation of the vias (in terms of surface planarity as discussed above) may have little to no impact on the surface planarity of the membrane support layer <NUM> (i.e., the membrane bonding regions). This distinction in via location between the device of <FIG> with the device of <FIG> is may be further illustrated by reference to a side-by-side comparison of <FIG>.

Both <FIG> illustrate a plan view of a portion of a transducer array (<NUM> x <NUM> in this particular example) illustrating exemplary via locations for transducers. The vias <NUM> in each figure are relatively small compared to other features and therefore appear as dots. As will be noted from <FIG>, which corresponds to the structure of <FIG>, the vias <NUM> are present both below the transducer cavity footprint (denoted by the darker shaded circular regions), as well as below the bonding regions corresponding to the patterned membrane support layer <NUM>. That is, the vias <NUM> in <FIG> are used to make an electrical connection to the transducer bottom electrode structures <NUM> below the cavity footprint, as well as to the bypass metal structures <NUM> beyond the cavity footprint (i.e., beneath the membrane support layer <NUM>).

In contrast, <FIG> illustrates that each of the vias <NUM> that connect to the transducer bottom electrode structures <NUM> or to the bypass metal structures <NUM> are located directly beneath the cavity footprint. That is, the regions directly beneath the membrane support layer <NUM> are free from (or substantially free from) having vias located therein. As a result, in the event where CMP processing variations exist, such a via location scheme may minimize any process impact to the bonding field regions. Additional information regarding providing smooth bonding interfaces for micromachined ultrasonic transducer devices may be found in <CIT>, assigned to the assignee of the present application.

By way of further illustration, <FIG> are a series of cross- sectional views illustrating a process that may be used to form the transducer device <NUM> of <FIG>, including both the aforementioned getter opening structures and the via-below-cavity structures. <FIG> illustrates the CMOS substrate <NUM> having insulation layer <NUM> formed thereon. In <FIG>, via openings <NUM> are patterned into the insulation layer <NUM> using, for example a patterned photoresist material (not shown) followed by etching to access the one or more wiring redistribution layers <NUM>. Then, as shown in <FIG>, a fill material metal layer <NUM> such as W, for example, is formed over the patterned insulation layer <NUM> and via openings <NUM>. This is followed by a planarizing operation, such chemical mechanical polishing (CMP) for example, to remove excess fill material of the metal layer <NUM> to the top surface of the insulation layer <NUM>, thereby defining the vias <NUM> as shown in <FIG>.

In <FIG>, the metal layer <NUM> (e.g., Ti) defining the bottom electrode layer <NUM> is deposited. The metal layer <NUM> is patterned as shown in <FIG> (such as by photoresist patterning and etching) to define the aforementioned transducer electrode and bypass metal structures <NUM>, <NUM>, respectively. This is followed by deposition of additional oxide material fill (e.g., the same as insulation layer <NUM>) as shown in <FIG> and oxide planarizing to the metal layer <NUM> as shown in <FIG>. Then, in <FIG>, the membrane support layer <NUM> is formed, followed by etching of the transducer cavity <NUM> in <FIG>. As shown in <FIG>, the aforementioned getter opening pattern <NUM> is etched into the bottom cavity layer <NUM> to expose a portion of the bypass metal structures <NUM>, after which the transducer cavity <NUM> may then be sealed by bonding a transducer membrane <NUM> to the membrane support layer <NUM>. Such a bonding operation may be, for example, a low temperature oxide-to-oxide fusion bonding process in which the transducer membrane <NUM> is bonded to the membrane support layer <NUM> at about room temperature and thereafter annealed at a temperature below about <NUM>.

The getter opening pattern <NUM> shown in <FIG> represents a desired case where the etch process ends once the bypass metal structures <NUM> are exposed and will serve as a getter material. However, as illustrated in <FIG>, it is possible that some over etching could occur such that some thickness of the bypass metal structures <NUM> is also unintentionally removed as well. This is represented in <FIG> by getter opening pattern <NUM>'. Consequently, a getter opening process (e.g., dry etching) may have the potential for electrical conductivity degradation of the bypass capacitor (<NUM>) if there is over etching of the bypass metal material. Moreover, any metal loss from over etching can have a more pronounced impact on an embodiment such as shown in <FIG>, since the majority of the vias connecting to the bypass metal structures <NUM> are located directly below the getter opening pattern <NUM>', as will be recalled from an inspection of <FIG>. To further illustrate, <FIG> depicts a similar view to that of <FIG>, but with the added view of illustrating the bottom cavity layer <NUM> (dark regions) and the annular getter opening pattern <NUM>' (light regions) etched into the bottom cavity layer <NUM>. As can be seen, the annular getter opening pattern <NUM>' exposes a portion of the bypass metal that directly overlies the vias <NUM>. Thus, in a situation where there is significant bypass metal loss from over-etching, this may result in poor electrical conductivity between the vias <NUM> (e.g., W) and the bypass capacitor electrode metal <NUM> (e.g., Ti).

Even in the event where no substantial over etching of the getter opening pattern occurs, the gettering process itself might also induce some amount of Ti film loss by virtue of how the gettering process works (e.g., the getter metal absorbs different gas species inside the CMUT cavity, thereby converting the top surface of the getter metal film will turn into a metal oxide. For example, in the case of a Ti getter metal, a getter byproduct may be the formation of Ti oxide at a thickness of about <NUM> angstroms (A). This oxidation can also reduce the electrical conductivity so long as the getter location overlaps with the underneath electrical connection vias, such as in <FIG>.

Accordingly, <FIG> illustrates an alternative getter opening pattern <NUM>, in accordance with an exemplary embodiment. As will be noted, instead of a completely annular pattern, the pattern <NUM> in <FIG> is segmented in a manner such that significantly reduces or minimizes the amount of vias <NUM> that are located directly beneath the getter metal exposed by the getter opening pattern <NUM>. In some cases there may be no vias directly below a given portion of the pattern <NUM>, and in other cases there may be a few vias directly below a given portion of the pattern <NUM>. In this manner, the getter opening process (e.g., etching) and/or the cavity gas getting process itself (e.g., oxidation) may have a minimal impact on via electrical conductivity. It should be noted that since the overall effective getter area in the embodiment of <FIG> is reduced with respect to that of <FIG>, getter efficiency may be experimentally evaluated (e.g., by varying getter pattern sizes and/or locations) in order to determine a maximum acceptable getter area reduction that does not substantially affect the purpose of the gettering itself (i.e., to getter cavity gas species).

By way of further illustration, <FIG> is an enlarged view of one of the transducers of <FIG>, which shows an example relationship between the transducer cavity "footprint" (outer circle) and the footprint of the segmented getter opening pattern (dashed pattern) of <FIG>. As can be seen, the vias <NUM> that connect to both the transducer electrode <NUM> and the bypass metal structure <NUM> are directly below the transducer cavity footprint. Further, a majority of the vias <NUM> connecting to the bypass metal structure <NUM> are not directly below the segmented getter opening pattern, but are instead offset in other regions of the bypass metal structure <NUM>. Alternatively, <FIG> illustrates an embodiment where none of the vias <NUM> contacting the bypass metal structure <NUM> are disposed directly below the segmented getter opening pattern, but instead are all displaced (offset) from being directly below the segmented getter opening pattern.

<FIG> illustrates a top view of an example ultrasonic transducer device <NUM> formed using any of the exemplary transducer structure embodiments described herein. As illustrated, the transducer device includes an array of individual transducers <NUM>, such as those respectively described above in conjunction with <FIG> and <FIG>. The specific number of transducers <NUM> shown in <FIG> should not be construed in any limiting sense, and may include any number suitable for a desired imaging application, which may be for example on the order of tens, hundreds, thousands, tens of thousands or more. <FIG> further illustrates an example location of metal <NUM> that may distribute an electrical signal to the membranes (upper electrodes) of the transducers <NUM>.

It should also be appreciated that although the exemplary geometric structure of this portion of the ultrasonic transducer <NUM> is generally circular in shape, other configurations are also contemplated such as for example, rectangular, hexagonal, octagonal, and other multi-sided shapes, etc. Consequently, the resulting segmented getter opening pattern may have individual getter segments that generally correspond to the geometric shape of the transducer cavity. By way of one additional example, <FIG> illustrate a hexagonal shaped transducer cavity, and the differences between an annular shaped getter opening pattern and a segmented getter opening pattern. The getter opening pattern <NUM> formed in the bottom cavity layer <NUM> of the embodiment of <FIG> is similar to that of the circular cavity configuration in <FIG>, in that the pattern <NUM> is continuous and extends adjacently around the entire perimeter of the hexagonal transducer. As is the case with <FIG>, it will be seen that the annular getter opening pattern <NUM> exposes a portion of the bypass metal that directly overlies the vias <NUM>.

In contrast, the individual segments of the segmented getter opening pattern <NUM> in <FIG> are advantageously located so as to expose bypass metal that avoids directly overlying most (if not all) of the vias beneath. It will be appreciated that there can also be a greater number or a lesser number of individual segments of the getter opening pattern <NUM> in <FIG>, and that each individual segment need not be identical to one another in shape and/or size.

As will thus be appreciated, the above described embodiments, whether implemented alone or in combination with one another, may provide certain benefits such as (for example) improved process margins and wafer bonding yield. As such, they may be particularly desirable for volume manufacturing of ultrasonic transducer devices and systems incorporating such devices.

The above-described embodiments can be implemented in any of numerous ways. For example, the embodiments may be implemented using hardware, software or a combination thereof. When implemented in software, the software code can be executed on any suitable processor (e.g., a microprocessor) or collection of processors, whether provided in a single computing device or distributed among multiple computing devices. It should be appreciated that any component or collection of components that perform the functions described above can be generically considered as one or more controllers that control the above-discussed functions. The one or more controllers can be implemented in numerous ways, such as with dedicated hardware, or with general purpose hardware (e.g., one or more processors) that is programmed using microcode or software to perform the functions recited above.

Various aspects of the present invention may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

Also, some aspects of the technology may be embodied as a method, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

Claim 1:
An ultrasonic transducer device (<NUM>; <NUM>), comprising:
a bottom electrode layer (<NUM>) of a transducer cavity (<NUM>) disposed over a substrate (<NUM>), wherein a first portion of the bottom electrode layer (<NUM>) comprises a transducer bottom electrode (<NUM>) and a second portion of the bottom electrode layer (<NUM>) comprises a bypass metal structure (<NUM>) that is electrically isolated from the transducer bottom electrode (<NUM>);
a plurality of vias (<NUM>) that electrically connect the bottom electrode layer (<NUM>) with the substrate (<NUM>), wherein a first portion of the plurality of vias (<NUM>) connect to the bypass metal structure (<NUM>) and are disposed in locations directly beneath a footprint (<NUM>) of the transducer cavity (<NUM>);
a bottom cavity layer (<NUM>) disposed over the bottom electrode layer (<NUM>); and
one or more openings (<NUM>) formed in the bottom cavity layer (<NUM>) so as to expose the bypass metal structure (<NUM>) of the bottom electrode layer (<NUM>) to the transducer cavity (<NUM>),
characterized in that locations of the one or more openings (<NUM>) correspond to locations where a majority of the first portion of the plurality of vias (<NUM>) are not disposed directly beneath.