Patent Description:
Microcontroller units (MCUs: Micro Controller Unit) are applied in all fields, for example, in the field of applications. In many cases, the MCU requires functions such as data transfer and data reduction. For example, in a situation where data transfer and data reduction are periodically performed, it is necessary to perform data transfer and data reduction in which the acquired data is made usable at high speed.

In the MCU, for example, a processor such as a CPU (Central Processing Unit), control such as data transfer to the main memory (RAM or the like) is performed. Here, it is assumed that data stored in a register provided as a peripheral function in the MCU is transferred to the main memory.

The CPU designates a predetermined address of the register and reads data from the designated address via the bus as transfer data. Then, the CPU specifies an arbitrary address of the main memory and writes the read data to the specified address. The CPU thus transfers data from the register to the main memory. Data reduction is performed after the read data is written to the main memory.

Further, data transfer may be performed by, for example, a DMA (Direct Memory Access) controller shown in Patent Document <NUM> or a DTC (Data Transfer Controller) controller shown in Patent Document <NUM>. For example, DMA/DTC controller specifies the number of data, the transfer source address (register), the transfer destination address (main memory), the transfer mode, and the like, and transfers data from the transfer source address (register) to the transfer destination address (main memory) via the bus.

There are disclosed techniques listed below.

<CIT> discloses an apparatus for reordering data received from a data stream into a contiguous ordering, has reorder unit that has multiple input buffers and image sensor is configured to generate received data as series of pixels in a non-contiguous order.

<CIT> discloses a method in that data can be accessed as a single contiguous chunk in the address space by assigning the registers to consecutive addresses by use of mirror registers, thus performing single DMA transfer even when the registers are not allocated to consecutive addresses.

<CIT> discloses a graphics system that uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. The system uses a local bus and a DC bus, Z-bus and pixel bus.

However, when the CPU is used, it is necessary to specify a transfer source address and a transfer destination address for each transfer. Further, since the CPU is involved in the data transfer, the data transfer time becomes longer. Also, during data transfer, the CPU cannot perform other processing.

On the other hand, when DMA/DTC is used, the transfer source address and transfer destination address can be specified for each register. However, since it is necessary to perform data reduction using the CPU after data transfer, if the time of data reduction is included, the processing time may be longer than when processing is performed only by the CPU.

It is an object of the present invention to provide a semiconductor device capable of reducing the time required for data transfer and data organizing.

A summary of representative ones of the inventions disclosed in the present application will be briefly described as follows. A typical solid state device includes a processor, a memory, an external interface, a register that stores data received by the external interface, a mirror register buffer, and an internal bus coupled to the processor, memory, external interface, registers, and mirror register buffers. The register outputs data to the mirror register buffer without going through the internal bus. The mirror register buffer gives the data input from the register the address in the mirror register buffer different from the address assigned to the register, and transfers the data to the memory without going through the internal bus.

The invention as defined by the appended claims effects to shorten the time required for data transfer and data organizing.

In all the drawings for explaining the embodiments, the same portions are denoted by the same reference numerals in principle, and repetitive descriptions thereof are omitted.

<FIG> is a block diagram showing an example of a semiconductor device according to Embodiment <NUM> of the present invention. As shown in <FIG>, the semiconductor device <NUM> includes a processor <NUM>, a DMA/DTC controller <NUM>, a main memory <NUM>, an external interface <NUM>, a register group <NUM>, a mirror register buffer (MRB) <NUM>, a first internal bus <NUM>, a bus interface <NUM>, a second internal bus <NUM>, and the like. An example of the semiconductor device <NUM> is an MCU or the like.

Processor <NUM> is an arithmetic processing unit comprising, for example, a CPU. The processor <NUM> reads data from the register group <NUM>, for example, through the second internal bus <NUM> and the first internal bus <NUM>. The processor <NUM> writes the read data to the main memory <NUM> through the first internal bus <NUM>. In this manner, the processor <NUM> transfers the data stored in the register group <NUM> to the main memory <NUM>.

The processor <NUM> reads and executes various kinds of data including various programs and parameters stored in the main memory <NUM>, for example, to realize a function block that performs various functions such as data transfer by software. The processor <NUM> may realize a function block in which hardware and software are cooperated, or may realize a part of the function block only by hardware.

DMA/DTC controller <NUM>, instead of the processor <NUM>, transfers data from the register group <NUM> to the main memory <NUM> via the second internal bus <NUM> and the first internal bus <NUM>.

Main memory <NUM> is a volatile memory such as, for example, SRAM (Static Random Access Memory). The main memory <NUM> includes an interface <NUM> and a memory array <NUM> that holds various data, as shown in <FIG>. Interface <NUM> is connected to the first internal bus <NUM> and the mirror register buffer <NUM>. Processor <NUM>, DMA/DTC controller <NUM>, and mirror register buffer <NUM> access main memory <NUM> via interface <NUM>.

The main memory <NUM> holds data transferred from the register group <NUM> or the mirror register buffer <NUM> through the bus (the second internal bus <NUM> and the first internal bus <NUM>) using the processor <NUM> or DMA/DTC controller <NUM> as the master, and data of the register group <NUM> directly written from the mirror register buffer <NUM> without going through the bus. The main memory <NUM> holds various data such as a program, a parameter, and an operation result of the processor <NUM>.

The semiconductor device <NUM> may include a storage (not shown). Examples of the storage include a non-volatile memory such as a flash memory and a EEPROM. The nonvolatile memory to be used is appropriately selected according to conditions such as capacity. When the storage is provided, a program, parameters, and the like for operating the semiconductor device <NUM> are stored in the storage.

The first internal bus <NUM> is coupled to the processor <NUM>, DMA/DTC controllers <NUM>, and the main memory <NUM>. The first internal bus <NUM> is connected to the second internal bus <NUM> through a bus interface <NUM>.

The external interface <NUM>, the register group <NUM>, the mirror register buffer <NUM>, the second internal bus <NUM>, and the like constitute a peripheral function in the semiconductor device <NUM>. The external interface <NUM>, register group <NUM>, and mirror register buffer <NUM> are connected to a second internal bus <NUM>. As described above, the second internal bus <NUM> is connected to the first internal bus <NUM> through the bus interface <NUM>.

The external interface <NUM> is an interface for transmitting and receiving data to and from an external device. The external interface <NUM> is connected to an external device such as, for example, a measuring device or a sensor. External device transmits the acquired measurement data to the semiconductor device <NUM>. The external interface <NUM> receives the measurement data transmitted from the external device. The external interface <NUM> transfers the received measurement data to a predetermined storage area of the register group <NUM> via the second internal bus <NUM>.

The register group <NUM> is, for example, a storage device that stores various types of data such as measurement data, time data, and peripheral environment data received from an external device by the external interface <NUM>. The register group <NUM> includes a different register for each type of data to be stored. For example, the register group <NUM> includes a measurement data register <NUM> for storing measurement data, a time data register <NUM> for storing time data, each register such as a peripheral environment data register <NUM> for storing the peripheral environment data. Data is written to and read from each register via the second internal bus <NUM> or the like.

As shown in <FIG>, each register of the register group <NUM> is connected to a mirror register buffer <NUM>. The connection between each register and the mirror register will be described in detail later.

<FIG> is a diagram specifically illustrating a configuration of a register and data stored in the register. <FIG> shows the measurement data register <NUM>, the time data register <NUM>, and the data stored in the peripheral environment data register <NUM>, respectively.

The measurement data register <NUM> stores, for example, measurement data of a plurality of measurement devices X, Y, and Z, all of which are not shown. As shown in <FIG>, the measurement data register <NUM> stores measurement data (Meter X[<NUM>:<NUM>]) of the measurement device X, measurement data (Meter Y[<NUM>:<NUM>]) of the measurement device Y, and measurement data (Meter Z[<NUM>:<NUM>]) of the measurement device Z.

These measurement data, for example [<NUM>:<NUM>], [<NUM>:<NUM>], [<NUM>:<NUM>], is stored so as to be able to read divided every predetermined number of bits (e.g., <NUM> bits, <NUM> bits). In addition, the measurement data of each measuring instrument is the data measured almost simultaneously. Although only the measurement data measured at a certain time is shown in <FIG>, the measurement data measured at a subsequent time may be stored in succession.

The measurement data register <NUM> may include registers 51a, 51b, and 51c corresponding to the measurement devices X, Y, and Z, respectively. In this instance, the register 51a stores the measurement data Meter X[<NUM>:<NUM>] of the measurement device X. The register 51b stores measurement data (Meter Y[<NUM>:<NUM>]) of the measurement device Y. The register 51c stores measurement data (Meter Z[<NUM>:<NUM>]) of the measurement device Z.

The time data register <NUM> stores the measurement time corresponding to the measurement data stored in the measurement data register <NUM> as the measurement time data. In <FIG>, the measurement data is displayed as a Calendar. The measurement time may be the time at which the measurement data is received or the time at which the measurement data is stored in the measurement data register <NUM>. The time data register <NUM> may store a plurality of clock data.

The peripheral environment data register <NUM> stores peripheral environment data. The ambient environment data includes, for example, temperature and humidity. The ambient data register <NUM> stores, for example, temperature data (Temperature) and humidity data (Humidity). The peripheral environment data stored in the peripheral environment data register <NUM> is data indicating the temperature and the humidity at the measurement time described above.

The peripheral environment data register <NUM> may include peripheral environment registers 53a and 53b corresponding to the temperature data and the humidity data, respectively. The peripheral environment register 53a stores temperature data. The peripheral environment register 53b stores the humidity data.

The mirror register buffer <NUM> is a circuit that adds consecutive addresses to the data stored in the register group <NUM> and transfers the data to the main memory <NUM> without passing through the internal bus <NUM>. The data stored in the register group <NUM> is addressed to a register or a storage area within the register. However, addresses may not be contiguous between registers or within registers. As a result, because the addresses are not consecutive, extra processing is required for data transfer to the main memory <NUM>, which increases the transfer time. If the addresses of the data are not consecutive, data must be sorted so that data can be written to consecutive addresses.

Therefore, in the present embodiment, in the mirror register buffer <NUM>, to add a continuous address, by grouping, so as to reduce the time required for data transfer and data reduction. Further, by providing a circuit for transferring the grouped data to the main memory <NUM>, the data can be directly written from the mirror register buffer <NUM> to the main memory <NUM>.

<FIG> is a block diagram showing an exemplary configuration of a mirror register buffer according to the first embodiment of the present disclosure. <FIG> is a diagram illustrating a configuration of an address setting register and an interrupt setting register in <FIG> shows a configuration including the mirror register buffer <NUM> and its periphery. As shown in the drawing 3A, the mirror register buffer <NUM> includes a plurality of addressing circuits <NUM> (65a0 to 65a2,. , 65d, 65e, 65f), a data output control circuit <NUM> (<NUM>, <NUM>), a buffer circuit <NUM>, an interrupt setting register <NUM>, and a data write control circuit <NUM>.

The address assigning circuit <NUM> is provided corresponding to each register included in the register group <NUM> of <FIG>. In this example, the address providing circuits 65a0 to 65a2 are provided corresponding to the measurement data register 51a, and are provided corresponding to the three registers 51a0 to 51a2 in <NUM>-bit units included in the measurement data register 51a, respectively.

Similarly, the address providing circuits 65c0 to 65c2 are provided corresponding to the measurement data register 51c of <FIG>, and are provided corresponding to the three registers 51c0 to 51c2 in <NUM>-bit units included in the measurement data register 51c, respectively. Note that illustration of 65c1, 65c2, 51c1, and 51c2 is omitted. The addressing circuit 65d, 65e are provided corresponding to the peripheral environment register 53a, 53b of <FIG>, respectively. The address assigning circuit 65f is provided corresponding to the time data register <NUM> of <FIG>.

Each addressing circuit <NUM>, as shown in <FIG>, the address setting register <NUM>, the address comparator <NUM>, the data selection circuit <NUM>, and a <NUM>. The address setting register <NUM> is composed of, for example, a flip-flop circuit. The address setting register <NUM>, as shown in <FIG>, any mirror register address MADR to be given to the mirror register is set, holds the mirror register address MADR. The mirror register is a register that mirrors the corresponding register, for example a virtual register. As an example, the mirror register virtually included in the address assignment circuit 65d mirrors the peripheral environment register 53a.

The mirror register address MADR set in the address setting register <NUM>, as shown in <FIG>, for example, the group address GADR is set to the upper <NUM> bits ([<NUM>:<NUM>]), the lower <NUM> bits ([<NUM>:<NUM>]) is set to consecutive addresses in the group. In this case, <NUM> kinds of grouping can be performed, and <NUM> pieces of data can be allocated to each group.

For example, as illustrated in <FIG>, when the peripheral environmental registers 53a and 53b are set to the same group, the same group address GADR may be set to the upper <NUM> bits of the address setting register <NUM> in the address assigning circuit 65d and the upper <NUM> bits of the address setting register <NUM> in the address assigning circuit 65e. In addition, "0x0" may be set in the lower <NUM> bits of the address setting register <NUM> in the address providing circuit 65d, and "0x1" may be set in the lower <NUM> bits of the address setting register <NUM> in the address providing circuit 65e. That is, the lower <NUM> bits of the address setting register <NUM> may be set to consecutive addresses in the group.

The data write control circuit <NUM> controls the write destination addresses RADR to the main memories <NUM> and the write data WDTs based on the setting contents of the interrupt setting register <NUM> in response to external events, for example, interrupt signals INT from the measurement circuit including the register group <NUM>. External events include reception of server log data in addition to interrupts.

The interrupt setting register <NUM>, as shown in <FIG>, the write destination address to the main memory <NUM>, in detail, the start address of the write (base address) RADRb, the group address GADR, the number of data NUM in the group, the interrupt number INTN, and the enable bit EN are set. In this example, the base address RADRb is <NUM> bits, the group address GADR, the number of data NUM, and the interrupt number INTN are <NUM> bits each, and the enable bit EN is <NUM> bit.

When receiving the interrupt signal INT matching the interrupt number INTN, the data write control circuit <NUM> outputs the base address RADRb to the main memory <NUM> and outputs, for example, an <NUM>-bit selected address SADR to each address giving circuit <NUM>. At this time, the data write controller <NUM> sequentially determines the selected address SADR based on the group address GADR and the number of data NUMs in the interrupt setting register <NUM>.

More specifically, the data write controller <NUM> sets the upper <NUM> bits to the set value of the group address GADR, and outputs the selected address SADR while sequentially incrementing the lower <NUM> bits until the set value of the number-of-data-NUM is reached. In response to the increment of the selected address SADR, the data write control circuit <NUM> sequentially increments the write destination address RADR to the main memory <NUM> from the base address RADRb.

In <FIG>, the write destination address RADR is a byte address, and the write data WDT is a word (<NUM>-bit) unit. In this case, the least significant bit ([<NUM>]) of the base address RADRb and the write destination address RADR is fixed to "<NUM>". The data write controller <NUM> increments the second bit ([<NUM>]) of the write destination address RADR every one cycle of outputting the selected address SADR.

The data width of the write data WDT can be changed as appropriate, for example, <NUM> bits or <NUM> bits. For example, when the data width of the write data WDT is a double word (<NUM> bits), the lower <NUM> bits ([<NUM>], [<NUM>]) of the base address RADRb and the write destination address RADR are fixed to "<NUM>". Further, in <FIG>, although one interrupt setting register <NUM> is shown, in detail, a plurality of events, i.e. corresponding to the interrupt signal INT interrupt number INTN differs, a plurality of interrupt setting registers <NUM> is provided. Then, for each of the plurality of interrupt setting registers <NUM>, different optional group address GADR and the base address RADRb is set.

In the address assigning circuit <NUM> illustrated in <FIG>, the address comparison circuit <NUM> compares the mirror register address MADR held by the address setting register <NUM> with the selected address SADR from the data write control circuit <NUM>. More specifically, the address comparator <NUM> compares, for example, the upper <NUM> bits in the <NUM> bits in the mirror register address MADR with the upper <NUM> bits in the <NUM> bits in the selected address SADR. The address comparison circuit <NUM> outputs a "<NUM>" level when the comparison results match, and outputs a "<NUM>" level when the comparison results do not match.

Data selection circuit <NUM>, <NUM> is composed of, for example, a three-input AND gate. The output from the address comparison circuit <NUM> and the <NUM>-bit data D[<NUM> : <NUM>] from the corresponding register are input to the data selection circuits <NUM> and <NUM> as two inputs among the three inputs. The value of the least significant bit ([<NUM>]) of the mirror register address MADR is input to the data selection circuit <NUM> as the remaining one input among the three inputs, and the inverted value of the least significant bit ([<NUM>]) is input to the data selection circuit <NUM>.

Thus, when the comparison results of the address comparison circuit <NUM> match, the data selection circuits <NUM> and <NUM> select whether to output the <NUM>-bit data D[<NUM> : <NUM>] from the corresponding register to the upper <NUM> bits or the lower <NUM> bits of the <NUM>-bit write data WDT based on the values of the least significant bits ([<NUM>]) of the mirror register address MADR. Specifically, when the value of the least significant bit ([<NUM>]) of the mirror register address MADR is "<NUM>" level, the data selection circuit <NUM> outputs the data D[<NUM> : <NUM>], and when the value of the least significant bit ([<NUM>]) is "<NUM>" level, the data selection circuit <NUM> outputs the data D[<NUM> : <NUM>].

For example, it is assumed that the same group A is set in the address setting register <NUM> in the address assigning circuits 65d and 65e, the address in the group A in the address assigning circuit 65d is set to "0x0", and the address in the group A in the address assigning circuit 65e is set to "0x1". Further, as the selected address SADR, assume that the group A, and the address "0x0" in the group A is output.

In this case, the data selection circuit <NUM> in the address assignment circuit 65d outputs <NUM>-bit data of the peripheral environment register 53a, and in parallel, the data selection circuit <NUM> in the address assignment circuit 65e outputs <NUM>-bit data of the peripheral environment register 53b. If the selected address SADR following "0x0" is output, the selected address SADR becomes "0x2" on the assumption that the least significant bit [<NUM>] is fixed to "<NUM>" in accordance with the relationship between the byte data and the word data.

Data output control circuit <NUM>, <NUM> is composed of, for example, an OR gate. Data output control circuit <NUM>, the output from the data selecting circuit <NUM> of the upper bit side in the plurality of addressing circuits <NUM> is input, substantially, and outputs the output from any one of the data selecting circuit <NUM> to the subsequent stage. On the other hand, the data output control circuit <NUM>, the output from the data selection circuit <NUM> of the lower bit side in the plurality of addressing circuits <NUM> is input, substantially, the output from any one of the data selection circuit <NUM> to the subsequent stage.

The buffer circuit <NUM> is formed of, for example, a flip-flop circuit. The buffer circuit <NUM> latches a total of <NUM>-bit data with <NUM>-bit data from the data output control circuit <NUM> as upper bits and <NUM>-bit data from the data output control circuit <NUM> as lower bits. Then, the buffer circuit <NUM> outputs the latched <NUM>-bit data as the write data WDT to the main memory <NUM> in response to a control signal from the data write control circuit <NUM>.

The buffer circuit <NUM> is provided to temporarily hold transfer data in case of conflicting with access via the first internal bus <NUM>, for example, when data transfer from the mirror register buffer <NUM> to the main memory <NUM>, i.e., writing of transfer data is performed. That is, by providing the buffer circuit <NUM>, the write timing of transfer data can be shifted, and access to the main memory <NUM> via the bus and data transfer from the mirror register buffer <NUM> to the main memory <NUM> can be performed.

As described above, the addressing circuit <NUM>, by the address setting register <NUM>, the data input from each register in the register group <NUM> (e.g., the peripheral environment register 53a or the like) is assigned an address in the mirror register buffer different from the address assigned to the register, that is, a mirror register address MADR. The mirror register buffer <NUM> transfers the data input from the register to the memory <NUM> without passing through the internal bus. Thus, it is possible to significantly reduce the data transfer time. Also in this embodiment, as in the conventional case, data can be transferred from the register to the main memory <NUM> via the bus.

<FIG> is a schematic diagram illustrating an exemplary operation of <FIG>. <FIG> shows an example of a relation between a plurality of address setting register 61A∼<NUM>, an interrupt setting register <NUM>, a real register RREG in the register group <NUM>, a mirror register MREG, and the main memory <NUM>. For convenience of explanation, the number of each of the address setting register <NUM> and the real register RREG is assumed to be seven.

Address setting register 61A∼<NUM> is included in each of the plurality of addressing circuitry <NUM> shown in <FIG>. Among these, for example, "0x21", "0x20", "0x22" and "0x23" are respectively set in the address setting register 61A, 61B, 61D, 61E. That is, the address setting register 61A, 61B, 61D, 61E, the same group address "0x2" is set.

The actual register RREG corresponds to a plurality of registers in the measurement circuitry shown in <FIG>. A predetermined address ADR is assigned to the plurality of registers in advance. Of these, for example, "0xF0400", "0xF0401", "0xF0600", and "0xF0601" are assigned to the registers "A", "B", "D", and "E", respectively. That is, the addresses ADR of registers "A", "B", "D", and "E" may include discontinuous ones.

The address setting register 61A, 61B, 61D, 61E corresponds to registers "A", "B", "D", and "E", respectively. As a result, "0xF0721", "0xF0720", "0xF0722" and "0xF0723" are assigned as mirror register addresses MADR to mirror registers MREG "A", "B", "D" and "E" corresponding to registers "A", "B", "D" and "E", respectively. Incidentally, the portion of the higher <NUM> bits in the mirror register address MADR "0xF07" is intended to be fixed in advance, the portion of the lower <NUM> bits is arbitrarily defined by the address setting register <NUM>.

For example, "0x8123-<NUM>" is set in the interrupt setting register <NUM>. In this case, the base address RADRb is "0x3050", the group address ADR is "0x2", the number of data NUM in the group is "<NUM>", the interrupt number ININ is "0x1". The setting to the address setting register 61A∼<NUM> and interrupt setting register <NUM> is performed in advance, for example, by the processor <NUM> or the like.

When the interrupt signal INT having the interrupt number INTN of "0x1" is generated, the data write control circuit <NUM> outputs the selected address SADR and the write destination address RADR based on the interrupt setting register <NUM>. In this example, for convenience, the data width of the write data WDT shall be <NUM> bits for ease of illustration.

In this case, the data write control circuit <NUM> outputs the selected address SADR "0x20", "0x21", "0x22", and "0x23" in this order over four cycles in the first transfer period (1st) based on the group address ADR and the number of data NUMs in the group. As a result, in the <NUM> cycles, as the write data WDT, the data of the register "B", "A", "D", and "E" is output in order.

In the four cycles, the data write controller <NUM> outputs the write destination address RADR "0x3050", "0x3051", "0x3052", and "0x3053" in this order based on the base address RADRb. As a result, the data of the registers "B", "A", "D" and "E" are transferred to the write destination addresses RADR "0x3050", "0x3051", "0x3052" and "0x3053" of the main memory <NUM>, respectively.

Thereafter, the data write control circuit <NUM>, when the interrupt number ININ receives the interrupt signal INT of "0x1" again, in the same manner as in the case of the first transfer period (1st), the second transfer period (2nd) processing to execute. In this case, unlike the case of the first transfer period (1st), the data write control circuit <NUM> holds "0x3053" which is the last write destination address RADR outputted in the first transfer period (1st), and sets the next address "0x3054" as the base address.

In this manner, the mirror register buffer <NUM> makes a grouping of a plurality of registers "B", "A", "D", a plurality of data input from "E", by giving the same group address GADR "0x2" and consecutive addresses in the group. In this case, the addresses of the plurality of registers "B", "A", "D", and "E" before grouping may be discontinuous. Then, the mirror register buffer <NUM>, an external event, for example, when the interrupt signal INT is generated, selects a group corresponding to the external event (group address GADR "0x2" group), and transfers the data belonging to the selected group to the main memory <NUM>.

Here, a specific example of data transfer by the mirror register buffer <NUM>. <FIG> is a diagram for explaining a specific example of data transfer by the mirror register buffer. <FIG> is a diagram specifically showing a data structure corresponding to <FIG>. <FIG> is a diagram showing the data stored in each register before data reduction. <FIG> is a diagram showing a data structure organized by grouping. <FIG> is a diagram showing a data configuration of the transfer data after transfer to the main memory <NUM>.

First, measurement data (Meter X, Meter Y, Meter Z), timing data (Calendar), temperature data (Temperature), and humidity data (Humidity) of the measurement devices X, Y, and Z are stored in the respective registers. The data stored in the register is given a predetermined address for each register (<FIG>).

Then, the mirror register buffer <NUM>, for example, grouping these data (<FIG>). Specifically, the mirror register buffer <NUM>, the same group address to the data to be grouped, and by giving consecutive addresses in the group, performs grouping. That is, the address setting register <NUM> corresponding to the data to be grouped, the same group address, and consecutive mirror register addresses in the group is set. Further, in <FIG>, as the start address of these mirror registers (base address), 0xF300 is set fixed.

In the case of <FIG>, the measurement data (Meter X) and the timing data (Calendar) are transferred first. Next, the measurement data (Meter Y) and the thermal data (Temperature) are transferred. Next, the measurement data (Meter Z) and the humidity data (Humidity) are transferred.

Specifically, measurement data (Meter X) is written to the address (<NUM>) (base address), clock data (Calendar) is written to the address (<NUM>) and consecutive addresses (<NUM>) (<FIG>). As a result, the measurement data (Meter X) and the timing data (Calendar) are continuously written in the main memory <NUM> (<FIG>).

Next, measurement data (Meter Y) is written to the address (<NUM>) and consecutive addresses (<NUM>), temperature data (Temperature) is written to the address (<NUM>) and consecutive addresses (<NUM>) (<FIG>). As a result, the measurement data (Meter X), the time measurement data (Calendar), the measurement data (Meter Y), and the thermal data (Temperature) are continuously written in the main memory <NUM> (<FIG>).

The measurement data (Meter Z) is written to the address (<NUM>) and consecutive addresses (<NUM>), the humidity data (Humidity) is written to the address (<NUM>) and consecutive addresses (<NUM>) (<FIG>). As a result, the measurement data (Meter X), the time measurement data (Calendar), the measurement data (Meter Y), the temperature data (Temperature), the measurement data (Meter Z), and the humidity data (Humidity) are consecutively written in the main memory <NUM> (<FIG>).

By repeating these operations, the mirror register buffer <NUM> continuously writes measurement data and the like measured at different times into the main memory <NUM> as transfer data (<FIG>).

Next, an application example of data reduction will be described. <FIG> is a diagram for explaining an application example of data reduction. <FIG> exemplify a data organizing method in an MCU having different pin numbers. PL0, PL1 in <FIG> indicates a register (port latch register) for storing data for each pin. For example, PL0 is a register that stores the data of the port <NUM>, and PL1 is a register that stores the data of the port <NUM>, respectively.

In <FIG>, a method of organizing data of consecutive ports is shown. The addresses of consecutive port registers are contiguous, but because some of the bits are disabled, the addresses are not contiguous as data. Therefore, in the example of <FIG>, the mirror register buffer <NUM>, <NUM> ports of data are summarized in two times of the transfer data. Further, in the example of <FIG>, the mirror register buffer <NUM>, <NUM> ports of data are summarized in one transfer data.

<FIG> is a diagram illustrating another application example of data reduction. In <FIG>, a method for organizing data of a plurality of non-contiguous ports is shown. As shown in <FIG>, the address of the port <NUM> and the port <NUM> registers is discontinuous. That is, the addresses of the registers of the plurality of data before grouping are discontinuous. Therefore, the mirror register buffer <NUM> generates transfer data collectively and the data of the port <NUM> and the data of the port <NUM> separated from each other.

<FIG> is a diagram for explaining another application example of the data reduction. Here, the case where the user flexibly organizes the data is shown. In <FIG>, data of the address F0400, F0500, F0600, F0601 is summarized as transfer data. Addressing F0700 ∼F0703 is assigned to the summarized data-to-be-transferred data. Thus, by assigning the data of the remote address to the adjacent address, these data will be written to the consecutive address, and data reduction is facilitated.

According to the present embodiment, the mirror register buffer <NUM> gives an address in another mirror register buffer than the address assigned to the register to data in the register, and writes the data to which the address is gives as transfer data directly from the mirror register buffer <NUM> to the main memory <NUM>. At this time, the mirror register buffer <NUM> writes the grouped data to consecutive addresses in the main memory <NUM>. According to this configuration, it is possible to perform data transfer and data reduction from the register to the main memory <NUM> in a short time.

In addition, since data is written to consecutive addresses, it is possible to perform data processing efficiently.

Here, a comparative example with respect to the present embodiment. The comparative example will be described in comparison with the above-described <FIG> and <FIG>.

<FIG>, which is not falling under the scope of the claimed invention, is a diagram for explaining data transfer and data reduction in the comparative example. <FIG> are diagrams specifically showing a data structure corresponding to <FIG>. <FIG> is a diagram showing a configuration of data written to the main memory before data reduction. <FIG> is a diagram showing a data structure after data is organized.

In the comparative example, as shown in <FIG>, data is transferred from the register to the main memory by DMA/DTC controllers <NUM>. DMA/DTC controller <NUM> reads the measurement data (Meter X), sets the transfer destination address of the measurement data (Meter X) to the address (<NUM>), and transfers to the main memory. Next, DMA/DTC controller <NUM> reads the measurement data (Meter Y), sets the transfer destination address of the measurement data (Meter Y) to the address (<NUM>), and transfers to the main memory. Then, DMA/DTC controller <NUM> reads out the measurement data (Meter Z), sets the transfer destination address of the measurement data (Meter Z) to the address (<NUM>), and transfers it to the main memory (<FIG>, <FIG>).

Similarly, DMA/DTC controller <NUM> transfers the temperature data (Temperature) to the address (<NUM>), the humidity data (Humidity) to the address (<NUM>), and the timing data (Calendar) to the address (<NUM>), respectively (<FIG> and <FIG>).

The processor reads data from the main memory, organizes the read data, and writes the organized data to the main memory (<FIG> and <FIG>).

As described above, in the comparative example, data is transferred from the register to the main memory, data is read from the memory, data is reorganized, and data is written to the memory, so that data transfer and data reduction take a long time.

<FIG> is a timing chart showing a comparison between the present embodiment and the comparative example. <FIG> is a timing chart for comparing the present embodiment with the comparative example in the case where data transfer is performed once. <FIG> is a timing chart for comparing the present embodiment with the comparative example in the case where data transfer is performed twice in succession.

In <FIG>, when transferring data in the DTC controller, command processing is performed from the activation request to the fifth clock. Then, data is read from the register at the sixth clock, data is written to the main memory at the seventh clock. Then, write-back is performed at the eighth clock. Then, the operation of the DTC controller ends.

In <FIG>, when data is transferred by the DMA controller, the command processing of bus arbitration is performed on the first clock. Then, data is read to the second clock, data is written to the main memory to the third clock. Then, the operation of the DMA controller ends.

In <FIG>, when transferring data in the mirror register buffer <NUM>, the command processing of bus arbitration is performed on the first clock. Then, the second clock, data is written to the main memory by the mirror register buffer <NUM>. Then, the operation of the mirror register buffer <NUM> is completed.

Comparing them, the data transfer takes the most time when the DTC controller is used. Further, when using the DMA controller, the data transfer time is only one clock different from the case of using the mirror register buffer <NUM>. However, even if data transfer is performed using the DMA controller, it is necessary to perform data reduction by the processor. Therefore, in consideration of the time until data reduction end, the present embodiment using the mirror register buffer <NUM>, it is possible to end the processing in a very short time.

In the example of <FIG>, the time difference required for data transfer is further expanded. When using the mirror register buffer <NUM>, it is possible to transfer a plurality of data in parallel, the data transfer time is the same as in <FIG>. Moreover, the DMA controller cannot perform continuous data transfer.

<FIG> is a diagram showing a comparison between the present embodiment and the comparative example in terms of power consumption. <FIG> shows the operation of the processor and the power consumption in comparison. <FIG> illustrates the intermittent operation. <FIG> shows the power consumption in <FIG> by comparing this embodiment with a comparative example.

In an intermittent operation, the operating mode of the processor switches between a normal mode, a stop mode, and a snooze mode. Snooze mode is a mode in which a processor is not used and only a peripheral function is operated.

In this embodiment using the mirror register buffer <NUM>, after the standby release, data transfer is performed in Snooze mode. However, when the CPU is used, data transfer is performed in normal mode because data transfer cannot be performed in Snooze mode. Further, when using the CPU, the data transfer time is longest.

Therefore, as shown in <FIG>, the power consumption required for data transfer is the lowest in the present embodiment, and is the highest in the case where a CPU is used. <FIG> is an estimate of the R78 architecture. As described above, the present embodiment is more effective than the prior art from the viewpoint of power consumption.

Next, a second embodiment will be described. As mentioned earlier, mirror register buffers can be organized by grouping data in registers. In the first embodiment, data is directly transferred from the mirror register buffer to the main memory <NUM> without passing through the bus, but in the present embodiment, data from the mirror register buffer is output to the bus in response to access from the processor <NUM> or DMA/DTC controller <NUM>.

<FIG> is a diagram showing a configuration example of a mirror register buffer according to Embodiment <NUM> of the present invention. The mirror register buffer <NUM> of <FIG> has a configuration in which the buffer circuit <NUM>, the interrupt setting register <NUM>, and the data write control circuit <NUM> are deleted from the mirror register buffer <NUM> of <FIG>.

The mirror register buffer <NUM> is accessed, for example, from the processor <NUM> or DMA/DTC controller <NUM>, and selected address SADR from the processor <NUM> or DMA/DTC controller <NUM> is input through the second internal bus <NUM>. Any mirror register address MADR is set in advance in the address setting registers <NUM> in the plurality of address providing circuits <NUM> so as to be convenient for data transfers, data organizing, and the like.

The mirror register buffer <NUM> compares the mirror register address MADR held by the address setting register <NUM> with the selected address SADR inputted through the buses in the respective address assigning circuits <NUM>. Then, the data is outputted from the register corresponding to the address assigning circuit <NUM> in which the mirror register address MADR and the selected address SADR coincide with each other. The output data can be transferred to various locations via the second internal bus <NUM>. That is, the transfer destination is not limited to the main memory <NUM>.

Claim 1:
A semiconductor device comprising:
a processor (<NUM>);
a memory (<NUM>);
an external interface (<NUM>);
a plurality of registers (<NUM>, <NUM>, <NUM>) for storing data received by the external interface (<NUM>), the data stored in the registers (<NUM>, <NUM>, <NUM>) being given a predetermined address per register;
a mirror register buffer (<NUM>); and
an internal bus (<NUM>, <NUM>) connected to the processor (<NUM>), the memory (<NUM>), the external interface (<NUM>), the registers (<NUM>, <NUM>, <NUM>), and the mirror register buffer (<NUM>),
wherein the registers (<NUM>, <NUM>, <NUM>) are configured to output the data directly to the mirror register buffer (<NUM>) without passing through the internal bus (<NUM>, <NUM>), and
wherein the mirror register buffer (<NUM>; <NUM>) is configured to set addresses to the data input from the registers (<NUM>, <NUM>, <NUM>), the addresses being different from the addresses assigned to the registers (<NUM>, <NUM>, <NUM>), and transfer the data directly to the memory (<NUM>) without passing through the internal bus (<NUM>, <NUM>),
wherein the mirror register buffer (<NUM>) is configured to set the addresses by making a grouping of the data input from the plurality of registers (<NUM>, <NUM>, <NUM>) while giving a same group address and consecutive addresses to a plurality of items of the data.