Patent Description:
Smart Power technologies have had increasing demands in automotive, industrial and consumer applications. Integrating high voltage devices with high side capability onto an advanced CMOS platform is both technically and economically challenging. To prevent damage from the effects of electrostatic discharge (ESD) in many applications, the integrated high voltage devices are typically protected by ESD clamps, which are triggered above the operating voltage and below the device breakdown voltage. Therefore, achieving a sufficient breakdown voltage with a tight distribution is essential to the success of the ESD protection.

In some circumstances, the Breakdown Voltage (BV) of conventional high voltage devices decreases as the device width of these devices is decreased. Moreover, the BV variation of these narrow devices may also increase. Thus, providing adequate ESD protection becomes more challenging as the dimensions of high voltage devices are reduced to achieve certain design goals. Increasing the minimum device width of the high voltage device will improve the BV characteristics. However, a larger minimum device width will result in some disadvantageous characteristics, (e.g., a higher sense current when the high voltage device is used as a sense FET and a larger parasitic capacitance to the substrate). Therefore, it is highly desirable to improve breakdown performance through innovative device design while maintaining a minimum device width.

United States patent, publication number <CIT> discloses a lateral diffused metal oxide semiconductor transistor and manufacturing thereof. A deep well region is disposed in a substrate. An isolation structure is disposed on the substrate to define a first active area and the second active area. A well region is disposed in the deep well region of the first active area. A gate is disposed on the substrate and the first active area. A gate dieletric is disposed between the gate and the substrate. A first doped region is disposed in the well region of the first active area and located at one side of the gate. A second doped region is disposed in the deep well region in the second active area. A conductive structures disposed on the isolation structure, surrounds the second doped region and is connected to the gate. United States patent application, publication number <CIT> discloses a low on-resistance semiconductor device. It may have a second polysilicon layer, which, it is stated may be part of "any type of geometrical structure". Sawtooth and scalloped geometries are depicted, but not described. United States patent application, publication number <CIT> discloses a semiconductor device which includes a substrate, a plurality of first insulators provided on an upper portion of the semiconductor structure, and a plurality of second insulator provided in the upper portion of the semiconductor substrate. The second insulator is thicker than the first insulator. The first insulators in the second insulators are arranged alternately.

Embodiments described herein provide for an improvement in BV. Specifically, a unique poly flap is used in a main device operation area, wherein the poly flap has a greater length (and hence shorter distance to the active drain area) than a gate length near the device termination ends. Accordingly, the BV dependence on the device width is reduced and the BV distribution is also narrowed, without requiring a wider device width with a corresponding increase in parasitic capacitance and higher sense currents in certain sensing applications.

<FIG> shows an example <NUM> of a p-type LDMOS arranged as a pair of split-gate transistors. The LDMOS is formed on an n-type wafer (e.g., an n-wafer) <NUM>. A bulk oxide (e.g., box) <NUM> is formed on the n-wafer <NUM>. An oxide <NUM> encloses a vertical n-type polysilicon <NUM>. An n-type buried layer (e.g., lnbl) <NUM> is formed on the box <NUM>. The box <NUM> and the oxide <NUM> form a shielded region, within which transistors are formed. A p-type epitaxial layer (e.g., p-epi) <NUM> is formed above the lnbl <NUM>. N-type high voltage implants (e.g., nhv) <NUM> are formed over the lnbl <NUM> to form a respective body region for each of two transistors included in the embodiment <NUM>. The p-type epitaxial layer <NUM> remains between the oxide <NUM> and the respective nhv <NUM>. A pair of p-type high voltage p-wells (e.g., hvpw) <NUM> is formed in the p-epi <NUM>. A Shallow Trench Isolation (STI) <NUM> is formed between a body contact <NUM> of each respective transistor and the deep trench isolation (DTI) formed by the oxide <NUM> and polysilicon <NUM>. The body contact <NUM> forms a low impedance connection to the nhv <NUM>. A source contact <NUM> abuts the body contact <NUM>. A pair of p-type lightly doped drain implants (e.g., pldd) <NUM> are formed adjacent to the source contact <NUM>. An STI <NUM> is formed in the hvpw <NUM> drift region for each respective transistor.

A first polysilicon gate electrode <NUM> is formed over a channel region <NUM> and controls the formation and conduction of the channel region <NUM>. A shared drain <NUM> is formed in the hvpw <NUM> and the p-epi <NUM>. A second polysilicon gate electrode <NUM> is formed over each of the STI <NUM> for each respective transistor to form a respective field plate. Each of the second polysilicon gate electrodes <NUM> form a respective field plate with the underlying drift region in the hvpw <NUM>. A spacer <NUM> is formed laterally on the side of the first polysilicon gate electrode <NUM> which is close to the source <NUM> and on the side of the second polysilicon gate electrode <NUM> which is close to the drain <NUM>. A spacer <NUM> is formed between each first polysilicon gate electrode <NUM> and the second polysilicon gate electrode <NUM>. A silicide <NUM> is formed over the butted body contact <NUM> and source contact <NUM> for each respective transistor. The silicide <NUM> is also formed over each polysilicon gate electrode <NUM> and <NUM> and the shared drain <NUM>. In another embodiment, the drift region in hvpw <NUM> further includes an n-type compensation (NCOM) region <NUM> to lower the doping concentration in this region. The second polysilicon gate electrode <NUM> is separated from the drain <NUM> by a first distance <NUM>. The example embodiment <NUM> of <FIG> shows a split-gate design. It should be understood that the teachings throughout this disclosure also apply to an embodiment using a single poly gate design, wherein the single poly gate is used to form the channel region <NUM> as well as a field plate.

<FIG> is a plan view of an example <NUM> showing several processing layers of the embodiment <NUM> of <FIG>. <FIG> is a plan view of an example embodiment <NUM> showing additional processing layers of the embodiment <NUM> of <FIG>. <FIG> with continued reference to <FIG>, shows the DTI <NUM> surrounding the nhv region <NUM>, which forms the body region. The nhv region <NUM> surrounds the hvpw region <NUM>, which forms the drift region. In one embodiment, the drift region further includes the implanted NCOM region <NUM> to improve Hot Carrier Injection (HCI) - Time Dependent Dielectric Breakdown (TDDB) robustness by lowering the doping concentration in the drift region. The DTI <NUM> and Box layer <NUM> (not shown) isolates the transistor pair from neighboring devices to improve isolation. A p-type epitaxial layer <NUM> (unfilled area in <FIG>) between the DTI <NUM> and the nhv <NUM> further increases BV for both High-Side (HS) and Low-Side (LS) power applications. An active region <NUM> defined where channel conduction occurs. In the example <NUM>, the active region <NUM> is shown as a single rectangular area. A central axis <NUM> is defined, which bisects the active area <NUM> in a direction of a current flow between the source <NUM> and the drain <NUM>.

<FIG> with continued reference to <FIG> and <FIG>, shows a merged polysilicon layer <NUM>, which conductively merges the first gate electrode <NUM> (forming the poly gate over the channel region <NUM>) and the second gate electrode <NUM> (forming a field plate over the STI <NUM>) outside of the active area <NUM>. A pair of gaps <NUM> are used to form the split-gate transistor by separating the first gate electrode <NUM> and the second gate electrode <NUM>. The drain <NUM> is separated from the second polysilicon gate electrode <NUM> by the first distance <NUM> at a first location <NUM> on the central axis <NUM> of the active area <NUM>. The second polysilicon gate electrode <NUM> includes a first field flap length <NUM> at the first location <NUM>. The drain <NUM> is separated from the second polysilicon gate electrode <NUM> by a second distance <NUM> at a second location <NUM> distal from the central axis <NUM> and within the active area <NUM> of the example <NUM>. The second polysilicon gate electrode <NUM> includes a second field flap length <NUM> at the second location <NUM>.

The second gate electrode <NUM>, overlaying the STI <NUM> in the hvpw <NUM>, or drift region, includes a right-side portion <NUM>, a left-side portion <NUM>, a top portion <NUM> and a bottom portion <NUM>. The terms right-side, left-side, top and bottom are provided in the context of <FIG> for ease of illustration and are not intended to confer an orientation limitation on the example <NUM>. A charge balance proximal to the first location <NUM> is different than the charge balance at the device termination (e.g., proximal to the second location <NUM>). For example, the drift region (in the hvpw <NUM> region) proximal to the first location <NUM> is only depleted by the body region under the right-side portion <NUM>. In contrast, the depletion of the drift region proximal to the second location <NUM> is accomplished by the body regions under the right-side portion <NUM> and the top portion <NUM>. Accordingly, the BV characteristics and the first location <NUM> and the second location <NUM> are different, and correspondingly the required length of the first field flap length <NUM> and the second field flap length <NUM> are different. <FIG> shows an example <NUM> of the combined layers of <FIG>, separately presented for clarity of exposition.

<FIG> shows a graphical view of the BV characteristics of the example <NUM> with a device width of <NUM>. In the example shown in <FIG>, the measured BV <NUM> for five dice exceeds the BV threshold <NUM> of 135V. The measured BV <NUM> also shows a tight voltage distribution. However as shown in <FIG>, as the device width is reduced to <NUM>, the measured BV <NUM> is reduced below the BV threshold <NUM> of 135V and exhibits a wider voltage distribution.

<FIG> is a graphical view of the BV characteristics of the LDMOS of <FIG> with a modified poly layer having various poly flag to drain spacings, in accordance with examples of the present disclosure. <FIG> compares the BV as a function of the first distance <NUM> between the poly flap and drain for a device width of <NUM> and <NUM>. In the examples of <FIG> for a <NUM> device width an optimal first distance <NUM> of <NUM> is empirically determined that maximizes the BV exceeding the BV threshold <NUM>. For a <NUM> device width, an optimal first distance <NUM> of <NUM> is empirically determined that maximizes the BV exceeding the BV threshold <NUM>. Optimizing the first distance <NUM> depends upon the device width because the device terminations play a more important role in the narrower device, where the drift region can be fully depleted with an assistance of a shorter poly flap (e.g., a larger flap to drain space, or the first distance <NUM>).

<FIG> show three embodiments <NUM>, <NUM> and <NUM> respectively of a modified poly layer having a modified poly flap design to improve BV characteristics. To take in account the impact of device terminations on the device performance, the poly flap of each embodiment is shortened at the terminations and in the area close to the terminations, while the poly flap at the central axis <NUM> of the active area <NUM> remains unchanged. Referring to <FIG> with reference to <FIG> and <FIG>, an example embodiment of a single stepped flap is shown. As discussed, with regards to <FIG>, in one embodiment the first distance <NUM>, (and thus the first field flap length <NUM>), is determined empirically. Similarly, in another embodiment, the flap width <NUM> and flap spacing <NUM> are determined empirically to maximize the BV exceeding the BV threshold <NUM>. <FIG> shows an example embodiment <NUM>, similar to the single stepped flap of embodiment <NUM> but with a chamfered flap. <FIG> shows an example embodiment <NUM>, similar to the single stepped flap of embodiment <NUM> but with a multiple stepped flap.

<FIG> and <FIG> show graphical views of the BV characteristics of the example <NUM> with the poly flap of embodiment <NUM> in <FIG>. Similar to <FIG>, the embodiment in <FIG> having a device width of <NUM>, shows a measured BV <NUM> for five dice exceeding the BV threshold <NUM> of 135V. The measured BV <NUM> shows a tight voltage distribution, similar to that shown in <FIG>. In contrast to <FIG>, the embodiment in <FIG> having a device width of <NUM>, shows a measured BV <NUM> for five dice exceeding the BV threshold <NUM> of 135V. The measured BV <NUM> further shows a tight voltage distribution, significantly improved over the distribution shown in <FIG>.

<FIG> shows an embodiment <NUM> of a method for manufacturing an LDMOS with an improved breakdown performance. Referring to <FIG>, with continued reference to <FIG> and <FIG> at <NUM>, a conductive electrode <NUM> (e.g., field plate), is formed over an isolation region <NUM>. At <NUM>, a drain electrode <NUM> is formed and connected to a drift region <NUM>. The drain electrode <NUM> is surrounded by the conductive electrode <NUM>. A first location <NUM> of the gate electrode <NUM> is on a central axis <NUM> of an active area <NUM>. The conductive electrode <NUM> has a longer field flap length <NUM> than at a second location <NUM> of the conductive electrode <NUM> on a line parallel to the central axis <NUM> and within the active area <NUM>.

<FIG> shows another embodiment <NUM> of a method for manufacturing an LDMOS with an improved breakdown performance. Referring to <FIG>, with continued reference to <FIG> and <FIG>, at <NUM>, a plate structure <NUM> is formed over an isolation region <NUM>. A drain electrode <NUM> is formed and connected to a drift region <NUM>. A first location <NUM> of the plate structure <NUM> is on a central axis <NUM> of an active area <NUM>. The plate structure <NUM> has a longer field flap length <NUM> than at a second location <NUM> of the plate structure <NUM> on a line parallel to the central axis <NUM> and within the active area <NUM>.

As will be appreciated, embodiments as disclosed include at least the following. In one embodiment, a method for manufacturing a Laterally Diffused Metal Oxide Semiconductor (LDMOS) comprises forming a conductive electrode over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed. The conductive electrode surrounds the drain electrode, wherein the drain electrode is separated from a first location of the conductive electrode by a first distance along a central axis of an active area of the LDMOS in a direction of a current flow between a source and a drain of the LDMOS. The drain electrode is separated from a second location of the conductive electrode by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

Forming the conductive electrode comprises forming a rectilinear polysilicon flap at the first location, wherein the rectilinear polysilicon flap is not at the second location. The conductive electrode comprises a polysilicon gate portion connected to a field plate portion in an active area of the LDMOS.

Alternative embodiments of the method for manufacturing a Laterally Diffused Metal Oxide Semiconductor (LDMOS) include one of the following features, or any combination thereof. Manufacturing the LDMOS comprises manufacturing a p-type field effect transistor. Manufacturing the LDMOS comprises manufacturing an n-type field effect transistor. Forming the conductive electrode comprises forming a chamfered polysilicon flap at the first location, wherein the chamfered polysilicon flap is not at the second location. Forming the conductive electrode comprises forming a stepped polysilicon flap at the first location, wherein the stepped polysilicon flap is not at the second location. The conductive electrode comprises a field plate, wherein the field plate is laterally separated from a conductive gate structure in an active area of the LDMOS.

In another embodiment, an apparatus comprises a conductive electrode over an isolation region. A drain electrode is connected to a drift region underlying the isolation region. The conductive electrode surrounds the drain electrode, wherein the drain electrode is separated from a first location of the conductive electrode by a first distance along a central axis of an active area of an LDMOS in a direction of a current flow between a source and a drain of the LDMOS. The drain electrode is separated from a second location of the conductive electrode by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

The first location comprises a rectilinear polysilicon flap, wherein the rectilinear polysilicon flap is not at the second location. The conductive electrode comprises a polysilicon gate portion connected to a field plate portion in an active area of the LDMOS.

Alternative embodiments of the apparatus include one of the following features, or any combination thereof. The LDMOS is a p-type field effect transistor. The LDMOS is an n-type field effect transistor. The first location comprises a chamfered polysilicon flap, wherein the chamfered polysilicon flap is not at the second location. The first location comprises a stepped polysilicon flap, wherein the stepped polysilicon flap is not at the second location. The conductive electrode comprises a field plate, wherein the field plate is laterally separated from a conductive gate structure in an active area of the apparatus.

In another embodiment, a method for manufacturing a semiconductor device comprises forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device. The drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

Forming the plate structure comprises forming a rectilinear polysilicon flap at the first location, wherein the rectilinear polysilicon flap is not at the second location.

Alternative embodiments of the method for manufacturing a semiconductor device include one of the following features, or any combination thereof. The plate structure is laterally separated from a conductive electrode in an active area of the semiconductor device. Forming the plate structure comprises forming a chamfered polysilicon flap at the first location, wherein the chamfered polysilicon flap is not at the second location.

Claim 1:
A method for manufacturing a Laterally Diffused Metal Oxide Semiconductor, LDMOS, comprising:
forming a conductive electrode (<NUM>) over an isolation region (<NUM>) and comprising a polysilicon gate portion (<NUM>) connected to a field plate portion (<NUM>) in an active area of the LDMOS, wherein forming the conductive electrode comprises forming a rectilinear polysilicon flap at a first location (<NUM>), wherein the rectilinear polysilicon flap is not at a second location (<NUM>); and
forming a drain electrode (<NUM>) electrically connected to a drift region (<NUM>) underlying the isolation region, the conductive electrode (<NUM>) surrounding the drain electrode, wherein the drain electrode is separated from a first location of the conductive electrode by a first distance (<NUM>) along a central axis of an active area of the LDMOS in a direction of a current flow between a source and a drain of the LDMOS, the drain electrode is separated from a second location (<NUM>) of the conductive electrode by a second distance along a line parallel to the central axis and within the active area, and the first distance being less than the second distance.