Patent Description:
This disclosure relates to a novel approach allowing Known Good Chiplet (KGC) testing to occur with IC wafers, chips, and/ or chiplets having, for example, large numbers (><NUM>, and even ><NUM>,<NUM>) of very fine-pitch (typically ≤<NUM> µm) interconnect pads.

Probe testing of IC chips is well known in the industry, but is limited to chips having rather large pitches (for example, ~<NUM> µm or more) of its interconnection pads. Temporary aligned "tack" bonding of microelectronic parts, as disclosed herein, is not known in the art. 'Tack' bonding is a temporary bond that has the potential to be detached or to be made permanent. While low temperature (friction bonding, seizing, cold welding) solid-state bonding of metal surfaces has been well established and has been reported in the literature for over <NUM> years (even at cryogenic temperatures), a microfabrication process with fine-alignment (~micron scale) capability at room temperature that allows inspection and rework, if needed, is lacking. See, for example, <NPL> and <NPL>).

Prior art technologies, which are referred to as Tech I, Tech II, Tech III and Tech IV herein, may relate to the following (and not necessarily in this order): Cascade Microtech (see www. cascademicrotech. com/ files/ PYRPROBE_APP. PDF); Technoprobe: (see www. technoprobe. com/ soluzione/ tpeg-mems-t4-power-your-device); FormFactor: (see www. formfactor. com/ product/ probe-cards/ foundry-logic/ vx-mp); and MJC Cantilever (see www. jp/ en/ products/ semiconductor/ probe_card.

<CIT> describes a machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.

<CIT> describes a method for forming a self-limiting, silicon based interconnect for making temporary electrical contact with bond pads on a semiconductor die is provided. The interconnect includes a silicon substrate having an array of contact members adapted to contact the bond pads on the die for test purposes (e.g., burn-in testing). The interconnect is fabricated by: forming the contact members on the substrate; forming a conductive layer on the tip of the contact members; and then forming conductive traces to the conductive layer. The conductive layer is formed by depositing a silicon containing layer (e.g., polysilicon, amorphous silicon) and a metal layer (e.g., titanium, tungsten, platinum) on the substrate and contact members. These layers are reacted to form a silicide. The unreacted metal and silicon containing layer are then etched selective to the conductive layer which remains on the tip of the contact members. Conductive traces are then formed in contact with the conductive layer using a suitable metallization process. Bond wires are attached to the conductive traces and may be attached to external test circuitry. Alternately, another conductive path such as external contacts (e.g., slide contacts) may provide a conductive path between the conductive traces and external circuitry. The conductive layer, conductive traces and bond wires provide a low resistivity conductive path from the tips of the contact members to external test circuitry.

In this document novel knife-edge microstructure contacts are disclosed that enable high local pressures to be applied that form weak temporary bonds to be established at room temperatures or stronger bonds to be formed (if higher pressures and temperatures are used). These microstructures, shown in the accompanying drawing figures, may be fabricated using standard microfabrication processes and are easily integrated into CMOS or other device technology layout formats.

As mentioned above, probe testing is well known in the industry, but the Small Pitch Integrated Knife Edge (SPIKE) approach presented here is significantly different from traditional needle probe or area array (e.g. pyramid probe) technology with respect to design and implementation. It is not an obvious extension of probe testing technology or thermo compression bonding technology.

There has been some debate among those in the technical community as to whether 2D and 3D integration manufacturing will require known-good-die testing prior to integration, or whether the yield of unscreened (untested) dies will be high enough and the drop-out associated with the integration process low enough that integrated multi-die-module yield will be sufficient. It is not surprising that some raise this question, as in many cases in commercial industry today, unscreened dies are packaged and only screened following packaging. However, we maintain that, with both conventional fabrication and advanced 2D and 3D integration manufacturing, yield and associated cost will drive the necessity of die/chiplet screening when the total integrated die/chiplet area exceeds ~<NUM><NUM> (indeed, the economic impact of poor yield is one reason why commercial companies such as Xilinx, Intel, and NVIDIA are producing multi-chip processors integrated using interposer technology today). This point is illustrated in <FIG> and discussed in detail below.

Although exceptionally complex and detailed integrated circuit yield models can be developed that incorporate details of the process and associated yield limiters at every mask step, a simple commonly used yield model for semiconductor processes is the Murphy model (see the equation on <FIG>), which depends only on an aggregated defect density associated with all mask steps (D) and the total die area (A). The Murphy model accounts for some degree of spatial correlation between defects, hence predicting a somewhat higher yield than an independent defect (Poisson) model. Assuming defects from chiplet to chiplet are independent, the yield of a complete module assembly with unscreened chiplets is simply the product of the yields of all of the individual chiplets multiplied by the integration yield for all chiplets (here we assume the same probability for successfully integrating each single chiplet, shown in the legend of <FIG>, such that the total integration yield is the single chiplet yield to the power of the total number of chiplets). The cost multiplier (i.e., cost of producing a single fully functional module divided by the cost of producing a single untested module, or equivalently, the total number of modules, one must assemble in order to produce one functioning module on average) is simply the reciprocal of this overall yield product. For the plot shown, we assume a maximum chiplet size of <NUM><NUM>, but the curves are very weakly dependent on this choice (as a smaller chiplet size results in higher yield, but correspondingly more chiplets are needed to achieve the total desired chiplet area such that the total yield is roughly unchanged).

The invention is defined by the ebclosed claims. The claimed invention allows creating a temporary electrical connection to a microelectronic component (e.g. a semiconductor die) with very fine-pitch interconnects (for example, an interconnect pitch of ≤<NUM> µm). One important use case for such a technology is to perform electrical screening of semiconductor dies or other microelectronic components with very fine-pitch interconnects (≤<NUM> µm pitch) in order to establish inventories of "known good die" (KGD) semiconductor modules or dies. The technology disclosed herein can be used with semiconductor dies or other microelectronic components having interconnects that are more widely spaced, if desired.

The claimed invention also allows temporary assembly of a number of dies into an integrated assembly, performing testing or use of the integrated assembly, then later replacing one or more die which may have been determined to have failed or degraded. In one embodiment, the disclosed method marries conventional wafer-probing techniques with die-bonding technology by using microfabrication of Small Pitch Integrated Knife Edge (SPIKE) probe "bumps" with shaped tips to allow fine-pitch probing or temporary attachments. The disclosed technology allows overcoming the limitation of conventional wafer-probing methods that generally only support much larger interconnect pitches (~<NUM> µm or greater). For a die screening/ probe use embodiment, a test fixture having a probe head with the microfabricated pointed SPIKE probe bumps is aligned to the die under test, preferably using a commercial precision die bonder (or a modest modification thereof), that enables the probe bumps to touch-down on contact pads and create a low resistance (≤<NUM> Ohm for <NUM> x <NUM> µm<NUM> pads) contact between SPIKE bumps and interconnect bumps of the chiplet under test. The touch down process preferably does not form a strong metallurgical bond, and as such, the SPIKE and chiplet bumps can be easily disengaged following testing. In the temporary assembly use embodiment, the SPIKE probes make a small area weak metallurgical bond which does not require continual pressure (as in the die screening case), but which can be disengaged as needed from the contacts for rework of the integrated assembly by die replacement, or can be bonded with more force in order to form a more permanent, traditional metallurgical bond.

In order to form this weak metallurgical bond, the probe tips are preferably formed of metals like Ti or W or even Au or Al, so long as the metal selected for the probe tips is at least somewhat harder than the metal of contact pads, which may be formed, for example, of In, Al, Cu, or Au. So when compressive pressure is applied between probes and pads, they become physically connected. the bond that occurs (which we call a weak metallurgical bond) is not really a chemical bond, but something more like a physical restraint, which provides excellent ohmic contact, yet the physical restraint or weak metallurgical bond can be broken to allow rework of the integrated assembly.

One use of the technology disclosed herein is to form temporary bonds between stacked component pairs including die-to-die, die-to-wafer, and wafer-to-wafer configurations to allow alignment and quality inspection (and possibly also electrical testing) prior to permanent flip-chip bonding, and/ or to allow characterization of temporary assemblies. The technology disclosed herein finds use in electronic packaging and integration applications, especially those that currently lack a temporary bonding technology to allow alignment inspection, and if necessary, repair, before final attachment, such as 3D and <NUM>. 5D integration, heterogeneous integration of diverse semiconductors, and hybridization processes. The temporary bonding technology disclosed herein can be performed at room temperature (for example, <NUM>° ± <NUM> and better yet <NUM>° ± <NUM> if in a climate-controlled environment). The advantages of temporary room temperature tack bonding include the following:.

The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications.

In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

The reader's attention is directed to (i) all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification and (ii) all papers and documents which are cited in the present application.

In the context of this document, the SPIKE concept is described primarily as a means for performing known-good-die testing for "chiplets", or die with very small, fine pitch pads. We envision that the same structures and roughly the same bonding approach could be used for a temporary assembly use embodiment.

We disclose herein a novel approach for performing known-good-chiplet (KGC) testing on chiplets with large numbers (><NUM>, and even ><NUM>,<NUM>) of very fine-pitch (≤<NUM> µm) interconnect pads, reducing the cost of integrated circuits (ICs) or chip modules which comprise, for example, a large aggregate chiplet area (by a factor of 10X to 100X). The disclosed method leverages techniques we have developed for fabricating Small Pitch Integrated Knife-Edge (SPIKE) uniform pointed bumps on pads of this target pitch (and below) to develop a novel fine-pitch probing technology, representing a significant improvement over the existing state of the art (See Table I).

Considering the table set forth above, the HRL SPIKE technology (HRL Probes <NUM>) disclosed herein meets a target specific contact resistance of <<NUM> Ohm-µm<NUM> which is consistent with the data set forth in <FIG> is a graph of measured series resistance vs chain length for four <NUM> x <NUM> arrays indicating <NUM>% yield and an essentially uniform contact resistance of <NUM> mOhm (<NUM> ohm per contact). Since the target of <<NUM> Ohm-µm<NUM> equals, for a 5x5 µm<NUM> pad, <<NUM> ohm per contact, obtaining a contact resistance of <NUM> ohm per contact means that the target has been exceeded by this technology.

As noted above, there has been some debate among those in the technical community as to whether a 2D or 3D integration manufacturing system will require known-good-die testing prior to integration, or whether the yield of unscreened die will be high enough and the drop-out associated with the integration process low enough that a 2D or 3D integration manufacturing system module yield will be sufficient.

We believe that, with both conventional fabrication and with a 2D or 3D integration manufacturing system, yield and associated cost will drive the necessity of die/ chiplet screening when the total integrated die/ chiplet area exceeds ~<NUM><NUM>. This point is illustrated in <FIG> and discussed in greater detail below.

Although exceptionally complex and detailed integrated circuit yield models can be developed that incorporate details of the process and associated yield limiters at every mask step, a simple commonly used yield model for semiconductor processes is the Murphy model (see equation in <FIG>), which depends only on an aggregated defect density associated with all mask steps (D) and the total die area (A). The Murphy model accounts for some degree of spatial correlation between defects, hence predicting a somewhat higher yield than an independent defect (Poisson) model. Assuming defects from chiplet to chiplet are independent, the yield of a complete module assembly with unscreened chiplets is simply the product of the yields of all of the individual chiplets multiplied by the integration yield for all chiplets (here we assume the same probability for successfully integrating each single chiplet, shown in the legend of <FIG>, such that the total integration yield is the single chiplet yield to the power of the total number of chiplets). The cost multiplier (i.e., cost of producing a single fully functional module divided by the cost of producing a single untested module, or equivalently, the total number of modules, one must assemble in order to produce one functioning module on average) is simply the reciprocal of this overall yield product. For the plot shown, we assume a maximum chiplet size of <NUM><NUM>, but the curves are very weakly dependent on this choice (as a smaller chiplet size results in higher yield, but correspondingly more chiplets are needed to achieve the total desired chiplet area such that the total yield is roughly unchanged).

For typical or even very aggressive defect densities for advanced semiconductor (e.g., CMOS) processes (<NUM> - <NUM>/ cm<NUM>), single-die yield begins to drop off significantly (<NUM>% to <NUM>%) once the die area exceeds <NUM><NUM>. As a result, the cost multiplier without die screening becomes prohibitive even for modest total chiplet areas, (e.g., a 10X cost results from a <NUM><NUM> total chiplet area with a <NUM>/ cm<NUM> defect density, or a <NUM><NUM> total chiplet area with a <NUM>/ cm<NUM> defect density). By comparison, the cost multiplier resulting from even a relatively modest per-chiplet integration yield (<NUM>% to <NUM>%) is correspondingly very low. Therefore, once total chiplet areas exceed roughly <NUM><NUM>, known-good-chiplet (KGC) screening (testing) becomes important in order to manage cost by ensuring that semiconductor wafers / chips/ chiplets are in fact good (KGC) before incorporating the wafer/ chip/ chiplet into some apparatus under fabrication. In fact, as can be seen from <FIG>, even if the cost of performing KGC screening were to become several times the cost of producing a single integrated module, at a large enough total chiplet area, cost considerations associated with utilizing a faulty wafer/ chip/ chiplet would still make KGC screening cost-beneficial.

For conventional semiconductor dies (chips), a number of probing technologies exist today, including various forms of DC and microwave "wedge" probes for peripheral contacts, and products such as Cascade Microtech's Pyramid Probe cards (which use microformed probe tips on a flex substrate) for area array probing. However, these technologies are generally limited to fairly large pitch (≥ <NUM> µm) interconnect pads and some are also limited to relatively small numbers of connections (~ <NUM> - <NUM>). See, for example, "Pyramid Probe Cards" by Cascade Microtech (available at www. cascademicrotech. com/ files / PYRPROBE_APP. PDF); "TPEG™ MEMS T4 - POWER YOUR DEVICE" by Technoprobe (available at www. technoprobe. com/soluzione/tpeg-mems-t4-power-your-device/); "Vx-MP" by FormFactor (available at www. formfactor. com/ product/ probe-cards/ foundry-logic/vx-mp/); and "Probe Card" by MJC Micronics Japan Co. (available at www. jp/ en/ products/ semiconductor/ probe_card.

In the long term, for high volume production, a KGC probing solution (see <FIG>) is envisioned that combines the best features of probe card technology with many of the features of a conventional die bonder (e.g. precise placement accuracy and application of mating force), and utilizing shaped (pointed) fine pitch bumps as probe tips <NUM> to be temporarily mated with the fine pitch chiplet pads <NUM> on a wafer/ chip/ chiplet <NUM> under test. The probes <NUM> have tapered edges which may be formed to a point or may take on a wedge shape formed to a ridge as shown in <FIG>. The tapered edges or slopes on the probes <NUM> may be formed using techniques known in the art. See, for example, "Image Reversal Resists and their Processing" (copy attached as Appendix A hereto) for a discussion of one way to form pointed, spike-like or knife-edge shaped members having tapered sidewalls using image reversal technology). If the deposition of the metal shown in figure <NUM> in Appendix A is continued, the resulting probes <NUM> may have a sharp knife-like distal edges or points as opposed to the blunter edge or point shown in Appendix A. Those practicing the present technology may choose to use the pointed, spike-like or knife-edge shaped probes <NUM> disclosed herein, but it should be understood that the probes <NUM> may alternatively be somewhat blunter thereby having contact regions which are less pointed or knife-like than the probes <NUM> depicted herein.

A successful method of contacting and testing fine-pitch (≤<NUM> µm) pads on chiplet die and/ or wafers should satisfy a number of criteria:.

Using evaporated metal deposition (typically Ti, Au or Al) and lift-off lithography (see Appendix A for example), we have demonstrated the ability to fabricate very uniform arrays of tall (several microns high) pointed tips on ten micron pitch bump or probe <NUM> arrays. In order to make the tips of probes <NUM> more robust, we recommend adding a coating of tungsten or nickel layer to the probes <NUM> (see <FIG>). The wafers/ chips/ chiplets under test <NUM> use conventional Au or Au-Sn pads <NUM> preferably with a flat surface profile. We expect the harder probe tips suggested above (with a layer or coating of tungsten or nickel) to enter slightly into the pads <NUM> when compressive pressure is applied by the bonding equipment, thus making electrical contact between probes <NUM> and pads <NUM> during testing, but preferably not making a metallurgical bond between the two (as with conventional bump bonding) and not precluding detachment of the wafers/chips/chiplets under test <NUM> after testing is completed or subsequent permanent bonding of the tested (and good) wafers/ chips/ chiplets <NUM> into some apparatus utilizing same.

Multiple probes <NUM> may be formed on a base or pad <NUM> and therefor are electrically connected in common to test apparatus via the base or pad <NUM> and a conductor <NUM>. The multiple probes <NUM> of <FIG> are sized to mate temporarily with a single pad <NUM> on the wafer/ chip/ chiplet to be tested. A wafer typically is several inches in diameter and many chips (or chiplets) are formed from a single wafer. The term "chip" refers to a single integrated circuit or IC. The term "chiplet" refers to an integrated circuit or IC which may be packaged or combined with other chiplets to form a single integrated circuit or IC. The testing disclosed herein may be done on a wafer-by-wafer basis or a chip-by-chip basis or a chiplet-by-chiplet basis. If done on a wafer-by-wafer basis then all chips embodied in the wafer may be tested simultaneously or a subset thereof may be tested at some instant in time. If done on a chip-by-chip basis or on a chiplet-by-chiplet basis it is preferred that the chips or chiplets remain attached to each other in the wafer so as to reduce the amount of set up work which would be with the die bonder. Of course, if all chips or chiplets on a wafer are to be tested simultaneously, then the probe head <NUM> should be sized so that multiple arrays of probes <NUM> can make contact with corresponding multiple arrays of pads <NUM>, each such array typically being then associated with a single chip or chiplet in the wafer.

An array of probe pads <NUM> may be fabricated on probe head <NUM> which is preferably constructed as a replaceable unit (a temporary testing fixture) attached to an interposer <NUM> to which a wafer/ chip/ chiplet <NUM> under test may be temporarily attached using the apparatuses and processes disclosed herein. The probes <NUM> are mated with the fine-pitch chiplet pad <NUM> pattern, under compression, using, for example, a FC300 die bonder made by Smart Equipment Technologies (SET Corporation SA) of Saint Jeoire, France, to apply a compressive force between its upper head (or tool head <NUM>) and its lower stage <NUM> thereby applying a compressive force between probes <NUM> and the pads <NUM> with which they mate during testing of wafer/ chip/ chiplet <NUM>. The die bonder functions as a press apparatus and, of course, other apparatuses may be used instead to apply a compressive force between the array of probes <NUM> and a corresponding pattern (or array) <NUM> of the fine-pitch wafer/ chip/ chiplet <NUM> pads <NUM>. The interposer <NUM> may distribute electrical connections from the pattern or array of the fine-pitch chiplet pads <NUM> via probes <NUM> and probe head <NUM> to an arrangement of conventional probe pads <NUM>, preferably disposed at periphery of the interposer <NUM> (see <FIG>). In some embodiments, the arrangement of conventional probe pads <NUM> may be located elsewhere such as at the periphery of the probe head <NUM> (see <FIG>). The conventional probe pads <NUM> are typically arranged on a much larger (relatively coarse, conventional) pitch compared to the fine-pitch pad pattern used on the wafer/ chip/ chiplet <NUM> under test, thereby allowing chiplet testing using conventional probes and probe station hardware to interface with the conventional, coarse pitch probe pad pattern <NUM>, and conduct whatever testing is desired for the wafer/ chip/ chiplet <NUM> to ensure that it is KGC before being more or less permanently affixed to some apparatus being constructed that utilizes the wafer/ chip/ chiplet <NUM>.

<FIG> is similar in many regards to the embodiment of <FIG>, but in the embodiment of <FIG>, the pads <NUM> are disposed on the probe head <NUM>. Exemplary connections <NUM> between pads <NUM> (for the test equipment) and the probes <NUM> (for the wafer/ chip/ chiplet <NUM> under test) are shown and none is needed within or on the interposer <NUM> in this embodiment. Also, in <FIG>, the elements of the die bonder (the upper stage <NUM> and lower stage <NUM>) which apply pressure between the interposer <NUM> and the wafer or chiplet under test <NUM> are omitted thereby allowing <FIG> to better depict the probes <NUM>.

<FIG> presents yet another embodiment of the probes <NUM>, associated pads <NUM>, probe head <NUM> and interposer <NUM>, but in this embodiment probes <NUM> are utilized not only to make contact to the pads <NUM> on the wafer/ chip/ chiplet <NUM> under test, but also (i) to make conductive contacts between the (replaceable, in this embodiment) probe head <NUM> and interposer <NUM> and (ii) to make conductive contacts between the interposer <NUM> and a readout IC, which is utilized in this embodiment in lieu of the pads <NUM> of the embodiment of <FIG>. The readout IC performs the function of the test equipment mentioned above. Also, as in <FIG>, the elements of the die bonder (the upper stage <NUM> and lower stage <NUM>) which apply pressure between the interposer <NUM> and the wafer or chiplet under test <NUM> are omitted thereby allowing <FIG> to better depict the probes <NUM> and the additional uses therefor.

Those skilled in the art should now recognize that the probes <NUM> can be used in a number of different ways and that the apparatus used to test the wafer/ chip/ chiplet <NUM> can take several different forms and yet additional forms beyond those depicted in <FIG>, <FIG> and <FIG> will now suggest themselves to those skilled in the art.

One embodiment of a process flow for fabricating probes <NUM> is shown in <FIG>. The probes <NUM> are preferably embodied as a knife-edge microstructures. But the probes <NUM> need not necessarily end in a pointed or knife-edge end, but may be somewhat blunter, if desired. An important factor in controlling the knife-edge probe structure is the reentrant photoresist <NUM> (see <FIG>) profile (using image reversal lithography) and the geometric spread of an evaporation or sputter source during deposition of the probes <NUM>. See Appendix A for a discussion of Image Reversal Lithography. The height of the knife-edge probe microstructure can be designed over a wide range (< <NUM>µm - <NUM>µm for example) depending on the linewidth opening G size in the resist <NUM> (see <FIG>). The probes <NUM> can be made blunter and less knife-edge-like by reducing the amount of material (see metal <NUM> in <FIG>) deposited during their formation.

The probe fabrication process employs standard semiconductor fabrication processes starting with a substrate, such as substrate <NUM><NUM> or <NUM><NUM> having a dielectric layer, such as dielectric layer <NUM><NUM> or <NUM><NUM>, disposed or formed thereon. Since the probes <NUM> may be utilized with either or both the probe head <NUM> and/ or the interposer <NUM>, both possibilities are described here since the same process flow may be used with either one or both, as desired. The substrate <NUM><NUM> or <NUM><NUM> is preferably formed of silicon because it is mechanically strong and also due to its low cost. The substrate <NUM><NUM> or <NUM><NUM> and the dielectric layer <NUM><NUM> or <NUM><NUM> form either the probe head <NUM> (see the embodiments of <FIG>, <FIG> and <FIG>) or the interposer <NUM> (see the embodiment of <FIG>).

A metal (typically Ti, Au or Al) contact layer is deposited and formed into an array of probe pads <NUM> using a patterned resist (not shown) or alternatively the resist may be deposited first, then patterned and then depositing the metal contact layer with the probe pads <NUM> then being formed by a lift off process. Not shown in <FIG> is additional metal preferably formed at the same time probe pads <NUM> are formed, the additional metal forming, for example, the coarse pitch probe pad pattern <NUM> (if utilized) and possibly also all or of a portions of conductors <NUM> which provide connections between pads <NUM> (if used, for the test equipment) and the probes <NUM> (for the wafer/ chip/ chiplet <NUM> under test and elsewhere in some embodiments) since those are easily formed using standard semiconductor fabrication processes. Also not shown are buried conductors <NUM> or the vertical vias though silicon for conductors <NUM> or the redistribution layer also for conductors <NUM> depicted in prior figures which may also be easily formed using standard semiconductor fabrication processes. These details are not shown in <FIG> since those figures are intended to teach a method of making the knife-edge probes <NUM>.

After the probe pads <NUM> are formed as shown in <FIG>, a re-entrant resist layer <NUM> is formed (see <FIG>) on dielectric layer <NUM><NUM> or <NUM><NUM> and patterned with sloping side walls (due to undercutting of the resist <NUM>) leaving an opening or gap G opening therein above each probe pad <NUM> at the top of the layer of resist <NUM>. As mentioned above, the size (linewidth) of the opening or gap G will affect the height of the soon to be deposited probes <NUM>. In <FIG>, each pad <NUM> is depicted with a single probe <NUM>. This embodiment can be easily modified (by making the probe pads <NUM> wider, so that a single probe pad <NUM> can accommodate multiple probes <NUM> as is depicted by <FIG> and <FIG>.

Turning to <FIG>, metal <NUM> (typically Ti, Au, Pd or Al) is then deposited, preferably by evaporation, on the structure depicted by <FIG>. Much of the deposited metal <NUM> ends up on resist <NUM>, but some of the metal <NUM> transits the openings or gaps G in resist <NUM> forming metal probes <NUM> with sloping sidewalls. The metal probes <NUM> are formed from metal <NUM> on each of the probe pads <NUM> exposed via openings or gaps G in resist <NUM>.

Metal <NUM> may start out being Au or Al as mentioned above, but change to tungsten or nickel towards the end of the deposition process so that the probes end up with a thin layer of tungsten or nickel on them to make them more robust as suggested above. <FIG> depicts, in a cross-sectional view, a single probe <NUM> not forming part of the claimed invention, having a relatively softer inner core <NUM>I (made of Au or Al, for example) and relatively harder outer surface <NUM>O (made of Ti or W, for example). These materials may be reversed with the inner core <NUM>I made of a relatively harder material and having outer surface <NUM>O made of a relatively softer material.

According to the claimed invention, probe <NUM> is formed of a stack of layers (see, for example, the embodiment of <FIG>) of a relatively harder material <NUM>H, for example, alternating with layers of a relatively softer material <NUM>S. So the stack embodiment of probe <NUM> may comprise layers of different materials, such as Ti/ Au/Ti/ Au. Furthermore, the stack embodiment of <FIG> may be utilized as inner core <NUM>I of probe <NUM> as depicted by <FIG>, in which case the stack of materials of <FIG> is covered with an outer surface <NUM>O as is the case with the embodiment of <FIG>. The outer surface <NUM>O may similarly be defined as a stack of materials similar to that shown in <FIG>. So there are many ways in which a number of different materials having differing hardnesses (moduli of elasticity) can give rise to a probe <NUM> having a desired modulus of elasticity. The modulus of elasticity governs the contact properties of the probes <NUM>. Typically, it is the metal contact pad <NUM> of the wafer/ chip/ chiplet <NUM> under test that determines what material is desirously used for the probes <NUM>. Moreover, one would typically desire a sufficiently hard probe <NUM> so that it plastically deforms the contact pad <NUM>. We found that layered metal structures (see <FIG> with alternating hard metals <NUM>H and soft metals <NUM>S so that the tip or pointed end <NUM> of a probe <NUM>, formed of Ti or Ni for example, would initially indent the contact pad <NUM> and then the softer body portions <NUM>S, formed of Al or Au, for example, of probe <NUM> would spread out when the compressive force is applied by the die bonder.

Turning again to <FIG>, the metal <NUM> on resist <NUM> as well as resist <NUM> is removed by dissolving resist <NUM> in a liftoff process, exposing the probes <NUM> as depicted by <FIG>, for example.

Claim 1:
A bonding apparatus for forming removable and/ or temporary connections between a testing fixture (<NUM>) and a wafer, chip or chiplet, the wafer, chip or chiplet having a plurality of flat metallic pads coupled to circuits to be tested in the wafer, chip or chiplet, the temporary bond apparatus comprising:
a plurality of knife-edge members (<NUM>) configured to be disposed on said testing fixture, said knife-edge members pointing in a direction normal to a major axis of the testing fixture;
a press apparatus (<NUM>, <NUM>) for imparting a compressive force between the knife-edged members and the plurality of flat wafer pads to thereby form, in use, a temporary electrical connection bond between (i) the plurality of flat wafer pads on the wafer, chip or chiplet to be tested and (ii) the plurality of knife-edge members;
characterised in that said knife-edge members comprise each of a stack of layers of a relatively harder metal, alternating with layers of a relatively softer metal.