Patent Description:
Various time-to-digital conversion approaches are known in the art. For example, "<NPL> describes a time-to-digital converter architecture with fine time resolution, and "<NPL>, describes a time-to-digital architecture to measure the timing difference between single-event two pulses with fine resolution.

Many time-to-digital converters (TDC:s) experience one or more of the following problems: that the maximum resolution is lower than desired, that the maximum (time) range is lower than desired, that the power consumption is higher than desired, that the implementation complexity and/or size is higher than desired, that the accuracy is lower than desired, that the noise is higher than desired, and that the non-linearity is higher than desired.

Therefore, there is a need for alternative time-to-digital converters.

<CIT> discloses a time measurement device for calculating a time from an input of a first trigger signal to an input of a second trigger signal as a measured time that includes a start gate configured to generate a start signal, a stop gate configured to generate a stop signal, a TDC circuit configured to generate a digital code corresponding to the time from an input of a start signal to an input of a stop signal, a delay circuit configured to delay an input of at least one of the start signal and the stop signal to the TDC circuit by a predetermined delay time, and a control unit configured to calculate a measured time on the basis of a plurality of digital codes generated by the TDC circuit, wherein the time delay unit selects at least two delay times.

In <CIT>, a pipeline time-to-digital converter (TDC) is provided. The pipeline TDC includes a plurality of TDC cells. Each of the TDC cells includes a delay unit, an output unit and a determination unit. The delay unit receives a first clock signal and a first reference signal output from a previous stage TDC cell. The delay unit generates sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and samples the first clock signal to obtain sampling values in accordance with the sampling phases. The output unit calculates the sampling values for outputting a conversion value. The determination unit uses and analyses the sampling values and the sampling phases for outputting time residue to a next stage TDC cell.

A first aspect is a time-to-digital converter (TDC) circuitry for converting a phase difference between an input reference signal and an input clock signal to a digitally represented output signal.

The TDC circuitry comprises a plurality of constituent TDC:s, wherein each constituent TDC is configured to convert a phase difference between a constituent reference signal and a constituent clock signal to a digitally represented constituent output signal.

The TDC circuitry also comprises a reference signal provider configured to provide the respective constituent reference signals to each of the constituent TDC:s, wherein - in at least a parallel operation mode of the TDC circuitry - each respective constituent reference signal comprises a respectively delayed version of the input reference signal with different respective delays for at least two of the respective constituent reference signals.

The TDC circuitry also comprises a digital signal combiner configured to provide the digitally represented output signal based on the digitally represented constituent output signals of the constituent TDC:s.

The reference signal provider is configured to provide - in at least the parallel operation mode of the TDC circuitry - the respective constituent reference signals as respectively delayed versions of the input reference signal with the respective delays being stochastically generated.

In some embodiments, the digital signal combiner is configured to provide - in at least the parallel operation mode of the TDC circuitry - the digitally represented output signal by one or more of: digital addition of two or more of the digitally represented constituent output signals, calculation of an average value of two or more of the digitally represented constituent output signals, and determination of a median value of two, three, or more of the digitally represented constituent output signals.

In some embodiments, the reference signal provider is configured to provide - in at least the parallel operation mode of the TDC circuitry - the respective constituent reference signals as respectively delayed versions of the input reference signal with the respective delays being randomly distributed.

In some embodiments, the reference signal provider is configured to provide - in at least the parallel operation mode of the TDC circuitry - the respective constituent reference signals as respectively delayed versions of the input reference signal with the respective delays being distributed within a range associated with a constituent TDC resolution.

In some embodiments, the reference signal provider is configured to provide - in at least the parallel operation mode of the TDC circuitry - the respective constituent reference signals as respectively delayed versions of the input reference signal with the respective delays being uniformly distributed.

In some embodiments, each constituent TDC comprises a plurality of delay elements arranged in sequence to successively delay the constituent clock signal, and a corresponding plurality of output ports, wherein each output port is configured to - when triggered by the constituent reference signal - provide an output of one of the delay elements as a symbol of the digitally represented constituent output signal.

In some embodiments - in the parallel operation mode of the TDC circuitry, the TDC circuitry is configured to provide the input clock signal as the respective constituent clock signal to each of the constituent TDC:s.

In some embodiments, at least some constituent TDC:s are configured to provide respectively delayed versions of the input clock signal.

In some embodiments - in a serial operation mode of the TDC circuitry, the TDC circuitry is configured to provide the input clock signal as respective constituent clock signal to one constituent TDC, and to successively provide respectively delayed versions of the input clock signal as respective constituent clock signals to the other constituent TDC:s, and the digital signal combiner is configured to provide the digitally represented output signal as a concatenation of the digitally represented constituent output signals of the constituent TDC:s.

In some embodiments, the reference signal provider is configured to provide - in the serial operation mode of the TDC circuitry - the same constituent reference signal to all of the constituent TDC:s.

In some embodiments - in an intermediate operation mode of the TDC circuitry (wherein each of a plurality of collections of constituent TDC:s comprises serially arranged constituent TDC:s), the TDC circuitry is configured to provide the input clock signal as the respective constituent clock signal to first constituent TDC:s of each collection, and to successively - within each collection - provide respectively delayed versions of the input clock signal as respective constituent clock signal to the constituent TDC:s of the collection, and the digital signal combiner is configured to provide the digitally represented output signal based on concatenations of the digitally represented constituent output signals of constituent TDC:s in each collection.

In some embodiments, the reference signal provider is configured to provide - in the intermediate operation mode of the TDC circuitry and within each collection - the same constituent reference signal to all constituent TDC:s within the collection.

In some embodiments, the TDC circuitry further comprises a mode selection signal input configured to control one or more of: provision of the respective constituent clock signal, provision of the constituent reference signal, and provision of the digitally represented output signal.

A second aspect is a phase locked loop (PLL) comprising the TDC circuitry of the first aspect.

A third aspect is an analog-to-digital converter (ADC) comprising the TDC circuitry of the first aspect.

A fourth aspect is a communication device comprising the TDC circuitry of the first aspect.

A fifth aspect is a method for converting a phase difference between an input reference signal and an input clock signal to a digitally represented output signal. The method comprises providing respective constituent reference signals to each of a plurality of constituent TDC:s, wherein - in at least a parallel operation mode - each respective constituent reference signal comprises a respectively delayed version of the input reference signal with different respective delays for at least two of the respective constituent reference signals with the respective delays being stochastically generated, converting a phase difference between the respective constituent reference signal and a respective constituent clock signal to a digitally represented constituent output signal for each of the plurality of constituent TDC:s, and providing the digitally represented output signal based on the digitally represented constituent output signals of the constituent TDC:s using a digital signal combiner.

An advantage of some embodiments is that the maximum resolution may be increased compared to prior art solutions.

An advantage of some embodiments is that the maximum (time) range may be increased compared to prior art solutions.

An advantage of some embodiments is that the power consumption may be decreased compared to prior art solutions.

An advantage of some embodiments is that the implementation complexity and/or size may be decreased compared to prior art solutions.

An advantage of some embodiments is that the accuracy may be increased compared to prior art solutions.

An advantage of some embodiments is that the noise may be decreased compared to prior art solutions.

An advantage of some embodiments is that the non-linearity may be decreased compared to prior art solutions.

Some advantages of some embodiments include: increase of resolution beyond the gate-delay of an applied technology, possibility to used small size inverters which may lead to low power consumption, avoidance of increased line length (compare with Vernier solutions), inherent linearity, a solution that scales well to very high resolution, embrace of random variations which may lead to advantages when the technology scales, and application of parallel TDC lines which may lead to less noise.

Some advantages of some embodiments with multi-mode operation include: flexibility between range and resolution, no need for separate frequency locking loop to achieve locking of a phase locked loop (PLL), and flexibility between phase noise and robustness in a PLL.

An advantage of some embodiments is that two or more of the above advantages may be achieved in combination.

An advantage of some embodiments is that trade-offs between two or more advantages may be less pronounced compared to prior art solutions.

In the following, embodiments will be described which provide time-to-digital converter (TDC) circuitry.

There is a fundamental trade-off between TDC resolution, linearity and power consumption. When a required resolution is lower than a shortest possible gate-delay of an applied technology, the trade-off typically gets more severe (e.g., since more complex and/or more power consuming architectures may be applicable).

The TDC circuitries provided herein may, in some embodiments, mitigate these and/or other problems.

Generally, the TDC circuitries of some embodiments presented herein are configured to convert a phase difference between an input reference signal and an input clock signal to a digitally represented output signal. Converting a phase difference between two signals to a digitally represented signal may be seen as time-to-digital conversion as is well understood in the art. One motivation therefore is that a phase difference between two signals may, given a frequency of the two signals, be expressed in terms of a time duration.

<FIG> schematically illustrates an example TDC circuitry <NUM> according to some embodiments. The example TDC circuitry <NUM> is for converting a phase difference between the input reference signal represented by <NUM> and an input clock signal represented by <NUM> to a digitally represented output signal <NUM>.

The TDC circuitry <NUM> comprises a reference signal provider (RSP) <NUM>, a plurality of constituent TDC:s (cTDC) <NUM>, <NUM>, <NUM>, and a digital signal combiner (COMB) <NUM>.

The example TDC circuitry <NUM> represents a parallel operation mode TDC circuitry, wherein the plurality of constituent TDC:s <NUM>, <NUM>, <NUM> operate in a parallel processing fashion.

The reference signal provider <NUM> is configured to provide respective constituent reference signals <NUM>, <NUM>, <NUM> to each of the constituent TDC:s <NUM>, <NUM>, <NUM>. Each of the respective constituent reference signals <NUM>, <NUM>, <NUM> is based on the input reference signal <NUM>.

Each constituent TDC is configured to convert a phase difference between the constituent reference signal <NUM>, <NUM>, <NUM> and a constituent clock signal to a digitally represented constituent output signal <NUM>, <NUM>, <NUM>. In this embodiment, the input clock signal <NUM> is used directly as constituent clock signal for each of the constituent TDC:s <NUM>, <NUM>, <NUM>.

The digital signal combiner <NUM> is configured to provide the digitally represented output signal <NUM> based on the digitally represented constituent output signals <NUM>, <NUM>, <NUM> of the constituent TDC:s.

In the example TDC circuitry <NUM>, each respective constituent reference signal comprises a respectively delayed version of the input reference signal <NUM>, with different respective delays for at least two of the respective constituent reference signals. The delay of the input reference signal <NUM> may be achieved by the reference signal provider <NUM> having delay elements <NUM>, <NUM>, <NUM> providing a respective delay for each of the constituent TDC:s <NUM>, <NUM>, <NUM>.

The delay elements <NUM>, <NUM>, <NUM> may be variably controllable as illustrated in <FIG>. The control may be exercised by a controller (e.g., controlling circuitry or a control module) comprised in, or otherwise associated with (e.g., connectable, or connected, to) the reference signal provider <NUM>.

In some embodiments, the respective delays are stochastically generated and/or randomly distributed. For example, the respective delays may be provided according to any suitable random, or pseudo-random, value generation algorithm. The provision of the respective delays may, for example, be implemented by a random number generator (RNG) <NUM> - an exemplification of a controller of the delay elements <NUM>, <NUM>, <NUM>.

Whether or not the respective delays are stochastically generated and/or randomly distributed, the respective delays <NUM>, <NUM>, <NUM> may be distributed within a range associated with a constituent TDC resolution. For example, the range associated with the constituent TDC resolution may be based on (e.g., equal to, substantially equal to, or slightly exceeding) the (average) delay of one delay element of a constituent TDC; which delay elements will be exemplified further in connection to <FIG>, and should not be confused with the delay elements <NUM>, <NUM>, <NUM> of the reference signal provider.

Whether or not the respective delays are stochastically generated and/or randomly distributed, the respective delays <NUM>, <NUM>, <NUM> may be uniformly distributed within a distribution range (which may, or may not, be associated with the constituent TDC resolution), according to some embodiments. Non-uniform distributions may be applied in other embodiments.

In the example TDC circuitry <NUM>, the digital signal combiner <NUM> is configured to provide the digitally represented output signal <NUM> based directly on the digitally represented constituent output signals <NUM>, <NUM>, <NUM> of each of the constituent TDC:s. For example, the digitally represented output signal <NUM> may be provided as a digital addition of two or more (typically all) of the digitally represented constituent output signals <NUM>, <NUM>, <NUM>, as an average value of two or more (typically all) of the digitally represented constituent output signals <NUM>, <NUM>, <NUM>, or as a median value of two, three, or more (typically all) of the digitally represented constituent output signals <NUM>, <NUM>, <NUM>.

Each of the constituent TDC:s <NUM>, <NUM>, <NUM> can be implemented according to any suitable TDC approach.

<FIG> schematically illustrates an example constituent TDC (cTDC) <NUM> according to some embodiments. The example cTDC <NUM> of <FIG> may be used as one or more of the constituent TDC:s <NUM>, <NUM>, <NUM> of <FIG> and/or as one or more of the constituent TDC:s <NUM>,. , <NUM> of <FIG> (which will be described later herein).

The constituent TDC <NUM> comprises a plurality of delay elements (D; e.g., implemented using inverters) <NUM>, <NUM>, <NUM> arranged in sequence to successively delay a constituent clock signal <NUM> (compare with <NUM> of <FIG> and <NUM>,. , <NUM> of <FIG>).

The constituent TDC <NUM> also comprises a corresponding plurality of output ports, wherein each output port is configured to - when triggered by a constituent reference signal <NUM> (compare with <NUM>, <NUM>, <NUM> or <FIG> and <NUM>,. , <NUM> of <FIG>) - provide an output of one of the delay elements <NUM>, <NUM>, <NUM> as a symbol (e.g., a bit) 232a, 232b, 232c of the digitally represented constituent output signal <NUM> (compare with <NUM>, <NUM>, <NUM> of <FIG> and <NUM>,. , <NUM> of <FIG>).

In the example constituent TDC <NUM>, each output port is implemented using a (digital) flip-flop circuit (FF) <NUM>, <NUM>, <NUM> having an output of a respective delay element <NUM>, <NUM>, <NUM> as input and being triggered (clocked) by the constituent reference signal <NUM> to output the respective symbol 232a, 232b, 232c.

Thus, in some embodiments, the constituent clock signal (CKV; e.g., a variable clock) is fed to the delay line comprising the plurality of delay elements, and the delay line state is sampled (e.g., by digital flip-flops) at an edge of the constituent reference signal (REF). The time difference between CKV and REF is thereby converted into the sampled state as quantized by the delay elements.

In some embodiments, the example constituent TDC <NUM> is also configured to provide a delayed version <NUM> of the constituent clock signal <NUM>. This may, for example, be achieved by using the output of the last delay element <NUM> (either directly as illustrated in <FIG>, or by using a buffer).

Generally, all of the plurality of constituent TDC:s of a TDC circuitry (e.g., <NUM>, <NUM>, <NUM> of <FIG> and/or <NUM>,. , <NUM> of <FIG>) may be identical. Alternatively or additionally, one or more of the constituent TDC:s of a TDC circuitry may differ in one or more aspects from other constituent TDC:s of a TDC circuitry. Differences between constituent TDC:s may, for example, be different length (e.g., different number of delay elements <NUM>, <NUM>, <NUM> and corresponding output ports) and/or different delay duration for each of the delay elements <NUM>, <NUM>, <NUM>.

The TDC circuitry <NUM> comprises a reference signal provider (RSP) <NUM>, a plurality of constituent TDC:s (cTDC) <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and a digital signal combiner (COMB) <NUM>.

The example TDC circuitry <NUM> represents a TDC circuitry configured for switching between a parallel operation mode and at least one of a serial operation mode and one or more intermediate operation modes.

Switching between the different operation modes may be accomplished by a mode selection signal input <NUM>, for example. In some embodiments, the mode selection signal input may be configured to receive any of two alternative inputs (e.g., in the form of a bit having a value of either zero or one); e.g., when the example TDC circuitry <NUM> is configured for switching between two operation modes. In some embodiments, the mode selection signal input may be configured to receive any of a more than two (e.g., three, four, etc.) alternative inputs; e.g., when the example TDC circuitry <NUM> is configured for switching between more than two operation modes. For example, when the example TDC circuitry <NUM> is configured for switching between three operation modes, the mode selection signal input may be configured to receive any of three alternative inputs (e.g., in the form of two bits having a value of either <NUM>, <NUM>, or <NUM> - <NUM> being unused), and when the example TDC circuitry <NUM> is configured for switching between four operation modes, the mode selection signal input may be configured to receive any of four alternative inputs (e.g., in the form of two bits having a value of either <NUM>, <NUM>, <NUM>, or <NUM>), etc..

In the parallel operation mode, the plurality of constituent TDC:s <NUM>,. , <NUM> operate in a parallel processing fashion (compare with <FIG>). In this operation mode, a maximum resolution may be achieved.

In the serial operation mode, the plurality of constituent TDC:s <NUM>,. , <NUM> operate in a serial processing fashion, wherein all of the constituent TDC:s are successively connected to each other such that a delayed version (compare with <NUM> of <FIG>) of the constituent clock signal (compare with <NUM> of <FIG>) of a first constituent TDC is used as the constituent clock signal for a second constituent TDC, a delayed version of the constituent clock signal of the second constituent TDC is used as the constituent clock signal for a third constituent TDC, and so on. In this operation mode, a maximum range may be achieved (which may be useful, e.g., for a frequency acquisition procedure of a phase locked loop, PLL).

In an intermediate operation mode, the plurality of constituent TDC:s <NUM>,. , <NUM> are grouped into a plurality of (non-overlapping) collections of constituent TDC:s. Within each collection, the constituent TDC:s operate in a serial processing fashion as described above, while the plurality of collections of constituent TDC:s operate in a parallel processing fashion. In this operation mode, a medium resolution and a medium range may be achieved.

In the following, embodiments will be described with one intermediate operation mode. However, this is not intended as limiting. Contrarily, two or more intermediate operation modes may be applicable according to some embodiments. Different intermediate operation modes may apply different grouping. For example, one intermediate operation mode may have two collections of constituent TDC:s, and other intermediate operation modes may have more than two (e.g., three, four,. , etc.) collections of constituent TDC:s.

The reference signal provider <NUM> is configured to provide respective constituent reference signals <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> to each of the constituent TDC:s <NUM>,. Each of the respective constituent reference signals <NUM>,. , <NUM> is based on the input reference signal <NUM>.

Each constituent TDC is configured to convert a phase difference between the constituent reference signal <NUM>,. , <NUM> and a constituent clock signal <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> to a digitally represented constituent output signal <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>.

In this embodiment, the constituent clock signal <NUM>,. , <NUM> for each of the constituent TDC:s is either the input clock signal <NUM> used directly or a respectively delayed version <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> (compare with <NUM> of <FIG>) of the constituent clock signal <NUM>,. , <NUM> from another constituent TDC. Selection of the constituent clock signal <NUM>,. , <NUM> for a constituent TDC, between the input clock signal <NUM> and a delayed version thereof <NUM>,. , <NUM> is implemented using respective switching circuitry <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>.

The digital signal combiner <NUM> is configured to provide the digitally represented output signal <NUM> based on the digitally represented constituent output signals <NUM>,. , <NUM> of the constituent TDC:s.

In the parallel operation mode, each respective constituent reference signal <NUM>,. , <NUM> comprises a respectively delayed version of the input reference signal <NUM>, with different respective delays for at least two of the respective constituent reference signals. The delay of the input reference signal <NUM> may be achieved by the reference signal provider <NUM> having delay elements <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> providing a respective delay for each of the constituent TDC:s <NUM>,.

The delay elements <NUM>,. , <NUM> may be variably controllable as illustrated in <FIG>. The control may be exercised by a controller (e.g., controlling circuitry or a control module) comprised in, or otherwise associated with (e.g., connectable, or connected, to) the reference signal provider <NUM>. For example, the provision of the respective delays may, for example, be implemented by a random number generator (RNG) <NUM>.

As mentioned above, the respective delays may be stochastically generated and/or randomly distributed, and/or distributed within a range associated with a constituent TDC resolution, and/or uniformly or non-uniformly distributed within a distribution range.

In the parallel operation mode, the constituent clock signal <NUM>,. , <NUM> for each of the constituent TDC:s is the input clock signal <NUM> used directly. Thus, the mode selection signal input <NUM> may cause all of the respective switching circuitries <NUM>,. , <NUM> to convey the input clock signal <NUM> (upper switch position according to <FIG>).

In the parallel operation mode, the digital signal combiner <NUM> is configured to provide the digitally represented output signal <NUM> based directly on the digitally represented constituent output signals <NUM>,. , <NUM> of each of the constituent TDC:s. For example, the digitally represented output signal <NUM> may be provided as a digital addition of two or more (typically all) of the digitally represented constituent output signals <NUM>,. , <NUM>, as an average value of two or more (typically all) of the digitally represented constituent output signals <NUM>,. , <NUM>, or as a median value of two, three, or more (typically all) of the digitally represented constituent output signals <NUM>,.

In this operation mode, the cTDC:s operate in parallel, and interleaving is used to provide high resolution.

In the serial operation mode, each respective constituent reference signal <NUM>,. , <NUM> may comprise a respectively delayed version of the input reference signal <NUM>, with different respective delays for at least two of the respective constituent reference signals, as in the parallel operation mode. Alternatively, the same constituent reference signal <NUM>,. , <NUM> (e.g., the input reference signal <NUM>, or an equally delayed version thereof) may be provided to all of the constituent TDC:s.

In the serial operation mode, the input clock signal <NUM> is provided directly as respective constituent clock signal <NUM> to one constituent TDC <NUM>, and respectively delayed versions <NUM>,. , <NUM> of the input clock signal are successively provided as respective constituent clock signals <NUM>,. , <NUM> to the other constituent TDC:s <NUM>,. Thus, the mode selection signal input <NUM> may cause the respective switching circuitry <NUM> to convey the input clock signal <NUM> (upper switch position according to <FIG>), and all of the other respective switching circuitries <NUM>,. , <NUM> to convey the respectively delayed versions <NUM>,. , <NUM> of the input clock signal (lower switch position according to <FIG>).

In the serial operation mode, the digital signal combiner <NUM> is configured to provide the digitally represented output signal <NUM> as a concatenation of the digitally represented constituent output signals <NUM>,. , <NUM> of the constituent TDC:s.

In this operation mode, there is no cTDC parallelization (and no interleaving will take place to provide high resolution). Instead, high range is achieved due to the long chain of cTDC:s.

In the intermediate operation mode, each respective constituent reference signal <NUM>,. , <NUM> may comprise a respectively delayed version of the input reference signal <NUM>, with different respective delays for at least two of the respective constituent reference signals, as in the parallel operation mode.

For example, at least two of the respective constituent reference signals within a (e.g., each) collection of constituent TDC:s may have different respective delays, as in the parallel operation mode. Alternatively, the same constituent reference signal (e.g., the input reference signal <NUM>, or an equally delayed version thereof) may be provided to all of the constituent TDC:s within a (e.g., each) collection of constituent TDC:s, wherein the constituent reference signal may, or may not, differ between collections.

In the intermediate operation mode, the input clock signal <NUM> is provided directly as respective constituent clock signal <NUM>, <NUM>, <NUM> to one (first) constituent TDC <NUM>, <NUM>, <NUM> of each collection, and respectively delayed versions <NUM>, <NUM>; <NUM>; <NUM>, <NUM> of the input clock signal are successively provided within each collection as respective constituent clock signals <NUM>, <NUM>; <NUM>; <NUM>, <NUM> to the other constituent TDC:s <NUM>, <NUM>; <NUM>; <NUM>, <NUM>. Thus, the mode selection signal input <NUM> may cause the respective switching circuitries <NUM>, <NUM>, <NUM> to convey the input clock signal <NUM> (upper switch position according to <FIG>), and all of the other respective switching circuitries <NUM>, <NUM>; <NUM>; <NUM>, <NUM> to convey the respectively delayed versions <NUM>, <NUM>; <NUM>; <NUM>, <NUM> of the input clock signal (lower switch position according to <FIG>).

In the intermediate operation mode, the digital signal combiner <NUM> is configured to provide the digitally represented output signal <NUM> based on concatenations <NUM>, <NUM>, <NUM> of the digitally represented constituent output signals <NUM>,. , <NUM>, wherein each concatenation <NUM>, <NUM>, <NUM> is for a corresponding collection of constituent TDC:s. For example, the digitally represented output signal <NUM> may be provided as a digital addition of two or more (typically all) of the digitally represented signal values of concatenations <NUM>, <NUM>, <NUM> of the digitally represented constituent output signals <NUM>,. , <NUM>, as an average value of two or more (typically all) of the digitally represented signal values of concatenations <NUM>, <NUM>, <NUM> of the digitally represented constituent output signals <NUM>,. , <NUM>, or as a median value of two, three, or more (typically all) of the digitally represented signal values of concatenations <NUM>, <NUM>, <NUM> of the digitally represented constituent output signals <NUM>,. The mode selection signal input <NUM> may be configured to receive a control signal specifying the operation mode (parallel operation mode or other operation mode, wherein the other operation mode is one or more of serial operation mode and one or more intermediate operation mode). Thus, the control signal may have two allowed values (e.g., parallel / serial or parallel / intermediate), three allowed values (e.g., parallel / intermediate / serial or parallel / first intermediate / second intermediate), or more than three allowed values (e.g., parallel / two or more intermediate / serial or parallel / three or more intermediate).

Based on the operation mode indicated by the control signal, the mode selection signal input <NUM> may cause the reference signal provider <NUM> to provide the constituent reference signal according to the above description, and/or cause the switching circuitries <NUM>,. , <NUM> to provide the respective constituent clock signal according to the above description, and/or cause the digital signal combiner <NUM> to provide the digitally represented output signal according to the above description.

According to various embodiments, some of the switching circuitries <NUM>,. , <NUM> and/or some of the respectively delayed version outputs <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may be omitted, depending on whether or not they are necessary for any of the operation modes of the embodiment under consideration. For example, in the example described for <FIG>, the switching circuitry <NUM> and the respectively delayed version outputs <NUM> are not used in any of the operation modes, and may therefore be omitted. When omitted, the switching circuitry (e.g., <NUM>) may be replaced by an equivalent delay according to some embodiments.

Generally, the digitally represented signal value (e.g., <NUM>, <NUM>, <NUM>; <NUM>,. , <NUM>; <NUM>, <NUM>, <NUM>) may represent the position of change in signal polarity. This may be particularly applicable for the longer delay lines (e.g., serial and possibly some intermediate operational modes), where multiple transitions can occur within the same delay line and counting the number of ones is typically not a viable approach. For short delay lines (e.g., parallel and possibly some intermediate operational modes) however, counting the number of ones may be a beneficial approach to eliminate problems with non-distinct transitions (so called bubbles).

The TDC circuitry of some embodiments may be used in any applications where a TDC is suitable. For example, the TDC circuitry disclosed herein may be used for one or more of: an analog-to-digital converter (ADC), a phase locked loop (PLL), a communication transmitter, a communication receiver, a communication device, a range finder, a RADAR equipment, a LIDAR equipment, and an equipment for determining collision times in a particle collider. The TDC circuitry of some embodiments may be particularly beneficial when a high resolution, without unnecessary increase of power consumption and/or chip area and/or complexity, is desired.

<FIG> schematically illustrates an example analog-to-digital converter (ADC) <NUM> according to some embodiments. The ADC <NUM> has an input port <NUM> for the analog signal to be converted and an input port <NUM> for a reference signal (compare with the <NUM> of <FIG> and <NUM> of <FIG>). The signal to be converted and the reference signal are input to a voltage-to-time converter (VTC) <NUM> and the output therefrom is a clock signal delayed with respect to the reference signal (with a delay depending on, e.g., proportional to, the input signal voltage). This signal (which corresponds to the input clock signal <NUM>, <NUM> of <FIG> and <FIG>) is input to a time-to-digital converter circuitry (TDCC) <NUM>, which may be any or the TDC circuitries described herein (e.g., any of the TDC circuitries <NUM> of <FIG> and <NUM> of <FIG>). The TDCC measures the time difference between the reference signal and the signal delayed by the VTC. The TDCC thereby provides a digitized version of the signal to be converted (corresponding to the digitally represented output signal <NUM>, <NUM> of <FIG> and <FIG>) via an output port <NUM>. A digital signal processor (DSP) <NUM> controls the VTC <NUM> and the TDCC <NUM>.

<FIG> schematically illustrates an example phase locked loop (PLL) <NUM> according to some embodiments. The PLL <NUM> has an input port <NUM> for a reference signal (compare with the <NUM> of <FIG> and <NUM> of <FIG>). The reference signal is input to a time-to-digital converter circuitry (TDCC) <NUM>, which may be any or the TDC circuitries described herein (e.g., any of the TDC circuitries <NUM> of <FIG> and <NUM> of <FIG>). The TDCC also receives a feedback signal <NUM> (which corresponds to the input clock signal <NUM>, <NUM> of <FIG> and <FIG>). In response to the phase difference between the input signals, the TDCC provides a digital signal (corresponding to the digitally represented output signal <NUM>, <NUM> of <FIG> and <FIG>) via an output port, which signal is passed through a low-pass filter (LPF) <NUM>. The output of the low-pass filer is used to control an oscillator <NUM> producing a signal <NUM> for feedback. The signal <NUM> for feedback may be provided as the feedback signal <NUM> to the TDCC. Optionally, the signal <NUM> for feedback is passed through a pre-scaler (PS) <NUM> before being provided as the feedback signal <NUM> to the TDCC. Particularly, the pre-scaler <NUM> may be useful when the frequency of the oscillator is higher than the maximum frequency that the TDCC can handle with high performance. A digital signal processor (DSP) <NUM> controls the TDCC <NUM> and the low-pass filter <NUM>.

Digital phase locked loops (DPLLs) may - due to CMOS technology scaling - achieve similar performance as their analog counterparts. A DPLL typically comprises a time-to-digital converter (TDC), which converts the phase difference between the reference signal (REF) and the digitally controlled oscillator (DCO) variable clock output (CKV) into a digital representation. The in-band phase noise of the DPLL is dependent on the resolution of the TDC and the spur level is dependent on TDC linearity.

The TDC requirements on resolution and range typically lead to a trade-off between power consumption and noise, for example, if a TDC such as that of <FIG> is used. A high resolution TDC typically needs a large number of delay cells (compare with <NUM>, <NUM>, <NUM>) with a small delay for each cell to satisfy the range requirement, which requires high power consumption.

Furthermore, the TDC detection range typically needs to cover at least one clock cycle of the feedback signal. To limit power consumption of the TDC it is common to avoid that the TDC range exceeds this one clock cycle by more than a very slight amount. One consequence of this is that a DPLL often has a limited range where it can observe the signal, and may therefore need some additional approach to be able to lock reliably.

Typically, there is also a minimum delay per cell for a given technology. Achieving a higher resolution than given by the minimum delay may require more complex (and more power consuming) architectures like a Vernier structure.

<FIG> is a simulation plot illustrating example results achievable by application of some embodiments. The plot illustrates a simulation of effective resolution improvement versus number of parallel delay lines (represented by the x-axis) for a TDC circuitry as presented herein. The simulation was performed in a circuit simulator with commercial models in a Monte-Carlo analysis for device variability. The y-axis is represented in dB. The resolution was simulated using input signals with a sinusoidal delay modulation with time. Hence, the TDC circuitry should produce a digital sinusoid at the output. The deviations of the TDC circuitry output from an ideal sampled sinusoid was identified as the TDC error. The root mean square of the TDC error was defined as the resolution. Quantization noise improvement over a single-chain TDC is shown by <NUM>, and normalized power consumption is shown by <NUM>. As can be seen in <FIG>, the effective resolution improves faster than the power consumption, yielding about 4dB resolution-to-power ratio improvement for a large number of constituent TDC:s.

<FIG> illustrates an example method <NUM> according to some embodiments. The method is for converting a phase difference between an input reference signal and an input clock signal to a digitally represented output signal. The execution details of the method may be dependent on an operational mode as described above and illustrated by optional step <NUM>. In step <NUM>, respective constituent reference signals are provided to each of a plurality of constituent TDC:s, as described above. In optional step <NUM>, respective constituent clock signals are provided to each of a plurality of constituent TDC:s, as described above. In step <NUM>, a phase difference between the respective constituent reference signal and the respective constituent clock signal is converted to a digitally represented constituent output signal for each of the plurality of constituent TDC:s, as described above. In step <NUM>, the digitally represented output signal is provided based on the digitally represented constituent output signals of the constituent TDC:s using a digital signal combiner, as described above.

<FIG> schematically illustrates an example communication device (CD) <NUM> according to some embodiments. The communication device <NUM> may, for example, be a wireless communication device or a wired communication device. Example communication devices include a receiver, a transmitter, a transceiver, a user equipment (UE), a station (STA), and a radio access node (e.g., a base station, access point or other network node).

The communication device <NUM> comprises a time-to-digital converter (TDCC) <NUM>, which may be any or the TDC circuitries described herein (e.g., any of the TDC circuitries <NUM> of <FIG> and <NUM> of <FIG>). Optionally, the communication device <NUM> may also comprise a controller (CNTR) <NUM> for controlling the TDCC <NUM> (e.g., selecting an operational mode and/or providing time delays for the reference signal).

Generally, various embodiments present a TDC architecture that uses parallel delay-lines with random time interleaving, and wherein the output may be found by summation. High resolution can be achieved as the number of delay-lines is increased, and the circuitry is inherently linear. Small sized inverters can be used, as the architecture is based on random variations, which results in attractive power consumption for a high resolution TDC. The phase noise performance increases with targeted resolution. The circuitry of some embodiments can be re-configured between high resolution over a small range and low resolution over a wide range; possibly in several steps.

In approaches of a stochastic multiple chain TDC, several delay lines are operated in parallel (in a time interleaved fashion) to achieve high resolution. The resolution may ideally increase by a factor N, where N is the number of TDC chains (delay lines). To keep the power consumption low, the chains may use very small-sized inverter stages. The delay lines will typically be affected by random process variations and noise, and the timing between the delay lines may thus depart from ideal interleaved conditions (showing a random distribution along the delay lines).

Due to the random properties the decision points will typically be well spread out, corresponding to high time resolution, but with some loss compared to the ideal positions. Letting the initial timing of a delay line be random may ensure random time interleaving along the full delay line. A random number generator may be used to control the initial delay of the delay lines over a range of about one inverter delay. In this way, stochastic properties (i.e., resolution and linearity) may be close to identical over the full TDC range.

The output may be achieved by summation of all the TDC chain outputs (much like in a stochastic flash ADC). The individual timing position of each chain becomes unimportant, since the effective characteristic of the TDC is given by all the transition points of the inverters in all chains together.

The performance may be dependent only on the uniformity of the distribution of those transition points in time. The randomization may provide high linearity, using several parallel lines may provide low noise, and using several lines together may decrease the average distance to the closest decision point (i.e., provide high resolution).

In a multi-mode stochastic TDC, the multiple TDC chains may be operating in parallel as described above, or in series (e.g., during locking time of a DPLL, or when interference calls for more robustness). Some or all of the individual TDC chains can be connected in series to create a longer TDC chain that covers multiple periods of the regular CKV signal with less resolution. The division ratio of the PLL feedback could then be increased. Hence, robustness can be traded against phase noise.

The described embodiments and their equivalents may be realized in hardware. The embodiments may be performed by general purpose circuitry and/or by specialized circuitry. For example, the digital signal combiner and/or the reference signal provider may be (partly or fully) implemented using general purpose circuitry. Alternatively or additionally, the constituent TDC:s and/or the digital signal combiner and/or the reference signal provider may be (partly or fully) implemented using specialized circuitry.

Examples of general purpose circuitry include digital signal processors (DSP), central processing units (CPU), co-processor units, field programmable gate arrays (FPGA) and other programmable hardware.

Examples of specialized circuitry include application specific integrated circuits (ASIC), delay elements (with fixed or variable delay), flip-flip circuitry, and switches.

The general purpose circuitry and/or the specialized circuitry may, for example, be associated with or comprised in an apparatus such as a transmitter, a receiver, a wireless communication device, or a network node.

Embodiments may appear within an electronic apparatus (such as a transmitter, a receiver, a wireless communication device, or a network node) comprising arrangements, circuitry, and/or logic according to any of the embodiments described herein. Alternatively or additionally, an electronic apparatus (such as a transmitter, a receiver, a wireless communication device, or a network node) may be configured to perform methods according to any of the embodiments described herein.

For example, the partition of functional blocks into particular units is by no means intended as limiting.

Claim 1:
A time-to-digital converter, TDC, circuitry for converting a phase difference between an input reference signal (<NUM>, <NUM>) and an input clock signal (<NUM>, <NUM>) to a digitally represented output signal (<NUM>, <NUM>), the TDC circuitry comprising:
a plurality of constituent TDC:s (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, ..., <NUM>), wherein each constituent TDC is configured to convert a phase difference between a constituent reference signal (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, ..., <NUM>) and a constituent clock signal (<NUM>, <NUM>, <NUM>, ..., <NUM>) to a digitally represented constituent output signal (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, ..., <NUM>);
a reference signal provider (<NUM>, <NUM>) configured to provide the respective constituent reference signals (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, ..., <NUM>) to each of the constituent TDC:s (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, ..., <NUM>), wherein - in at least a parallel operation mode of the TDC circuitry - each respective constituent reference signal comprises a respectively delayed version of the input reference signal (<NUM>, <NUM>) with different respective delays for at least two of the respective constituent reference signals; and
a digital signal combiner (<NUM>, <NUM>) configured to provide the digitally represented output signal (<NUM>, <NUM>) based on the digitally represented constituent output signals (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, ..., <NUM>) of the constituent TDC:s;
wherein the reference signal provider (<NUM>, <NUM>) is configured to provide - in at least the parallel operation mode of the TDC circuitry - the respective constituent reference signals (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, ..., <NUM>) as respectively delayed versions of the input reference signal (<NUM>, <NUM>) with the respective delays (<NUM>, <NUM>, <NUM>, <NUM>, ..., <NUM>) being stochastically generated.