Patent Description:
Successive-approximation-register analog-to-digital converters (SAR ADCs) are known in the prior art. They are suitable in applications where low power consumption, in particular low power per conversion step, is required. To achieve a high conversion rate, two SAR ADC stages may be pipelined, connected through an inter-stage amplifier. Conversion rates up to several hundreds of megasamples per second (MS/s) may be reached.

<NPL>, relates to a <NUM>-stage fully-dynamic high-gain residue amplifier for a <NUM>-bit <NUM>/s two-stage SAR assisted pipeline ADC.

<NPL>, relates to a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC.

An objective of the present inventive concept is to provide a high-conversion-rate SAR ADC with reduced power consumption.

The present invention concerns a pipelined SAR ADC according to independent claim <NUM> and a method of analog-to-digital conversion of an analog level according to independent claim <NUM>.

According to a first aspect of the present inventive concept, there is provided a pipelined successive approximation register analog-to-digital converter, SAR ADC, comprising a first SAR ADC stage; an inter-stage amplifier for amplifying an analog residue from the first SAR ADC stage; and a second SAR ADC stage input from the inter-stage amplifier, wherein the inter-stage residue amplifier comprises one or more MOS transistors, wherein the source and drain terminals of each of the one or more MOS transistors are connected to each other and may be toggled between ground and a supply voltage.

The one or more MOS transistors provide a fully passive low-power and low-noise amplifier based on switchable gate capacitance, where transfer to or from the amplifier occurs through charge sharing. Hereby, the power consumption of the pipelined SAR ADC may be considerably reduced - a significant contribution to the power consumption of a pipelined SAR ADC may otherwise be due to the inter-stage amplifier - while still allowing for a high conversion rate, low noise and robustness against temperature and voltage variations.

In particular, power consumption of the pipelined SAR ADC is considerably reduced compared to using an operational amplifier as inter-stage amplifier.

Further, compared to using a dynamic amplifier as an inter-stage amplifier, the sensitivity of the amplifier to voltage and temperature variations is considerably reduced, removing the need for background calibration required to continuously monitor and adjust the gain, which otherwise increases circuit complexity and thereby power requirements and cost of the pipelined SAR ADC.

Compared to using no inter-stage amplifier at all, the resulting stringent noise requirements on the backend - especially if high resolutions are targeted - are reduced, the implementation of which also would result in an increase in power consumption.

According to one embodiment, the one or more MOS transistors comprise a complementary pair consisting of an NMOS transistor and a PMOS transistor. This further reduces the dependence on voltage variations. Further, clock feedthrough and common-mode shift are canceled and linearity is improved.

According to one embodiment, the pipelined SAR ADC is implemented in CMOS technology.

According to one embodiment, the second SAR ADC stage comprises an input capacitor connected to the gate terminal of each of the one or more MOS transistors. This allows for a reduction of the input capacitance of the second SAR ADC stage, which maximized the amplification of the inter-stage amplifier.

According to one embodiment, at least one of the first SAR ADC stage and the second SAR ADC stage is a charge redistribution SAR ADC stage.

In particular, each of the first SAR ADC stage and the second SAR ADC stage is a charge redistribution SAR ADC stage. This allows for a SAR ADC that, possibly with the exception of comparators in the ADC stages, has no active components, where in particular the residue transfer and the inter-stage amplification is performed in a fully passive way, further reducing power requirements.

According to a second aspect of the present inventive concept, there is provided a method of analog-to-digital conversion of an analog voltage, comprising performing a first successive approximation analog-to-digital conversion of the analog level; amplifying an analog residue from the first successive approximation by inputting the analog residue on the gate terminal of one or more MOS transistors, wherein the respective source and drain terminals of each of the one or more MOS transistors are connected to each other and may be toggled between ground and a supply voltage, and toggling the source and drain terminals of the one or more MOS transistors, resulting in an amplified voltage on the gate terminal; and performing a second successive approximation analog-to-digital conversion of the result of the amplifying.

Advantages and embodiments of this second aspect are at least the same as and/or compatible with those described above in conjunction with the first aspect.

<FIG> shows a pipelined successive approximation register analog-to-digital converter (SAR ADC) <NUM>. The SAR ADC <NUM> comprises a first SAR ADC stage <NUM>; an inter-stage amplifier <NUM>; and a second SAR ADC stage <NUM>. The inter-stage amplifier is connected to the first SAR ADC stage <NUM> on an output line <NUM> of the first SAR ADC stage <NUM>. In turn, the amplified voltage output from the inter-stage amplifier <NUM>, is input to the second SAR ADC stage <NUM> on a line <NUM>. Each of the stages of the pipelined SAR ADC may be implemented in CMOS technology, and may be comprised in a System-on-Chip.

At least one of the first SAR ADC stage <NUM> and the second SAR ADC stage <NUM>, may be a charge redistribution SAR ADC stage. For example, as depicted, each of the first SAR ADC stage <NUM> and the second SAR ADC stage <NUM> may be a charge redistribution SAR ADC stage.

The first SAR ADC stage <NUM> is connected to an input line vin <NUM> through a normally-open switch <NUM>, controlled by a signal line STRK, to a common bus <NUM>.

Each capacitor <NUM> of a plurality of capacitors is at one connected to the common bus <NUM> and at its other end switchably connected to be toggled between a supply voltage VDD and ground. The plurality of capacitors comprises capacitors <NUM> with values that are powers of <NUM> of a capacitance C. The number of capacitors, and thereby the number of powers of <NUM>, depend on the resolution of the SAR ADC stage <NUM>. In the depicted example, the plurality of capacitors comprises capacitors <NUM> with capacitances C, 2C, 4C, 8C, and 16C, for a resolution of <NUM> bits. As depicted, each capacitance may be represented by two capacitors <NUM> in the plurality of capacitors, to provide a dual DAC structure to keep constant the common mode voltage at each comparator cycle.

Further, an adjustable, programmable capacitor <NUM> with capacitance CFS1 is connected between the common bus <NUM> and ground for to adjusting the full scale of the first SAR ADC stage <NUM>.

The common bus <NUM> is connected to the switch <NUM> of the inter-stage amplifier <NUM> (see below), for outputting a residue voltage of the first SAR ADC stage <NUM> after analog-to-digital conversion. Switching of the plurality of capacitors <NUM>, the programmable capacitor and the switch <NUM> is controlled by a logic block <NUM>. A comparator <NUM> is connected to the common bus <NUM> and outputting its result to the logic block <NUM>.

Similarly, an input <NUM> of the second SAR ADC stage <NUM> is connected to an output <NUM> of the inter-stage amplifier <NUM>. An optional input series capacitor <NUM> with capacitance CBR is connected between the input <NUM> and a common bus <NUM> to reduce the input capacitance of the second SAR ADC stage.

Each capacitor <NUM> of a plurality of capacitors is at one connected to the common bus <NUM> and at its other end switchably connected to be toggled between the supply voltage VDD and ground. The plurality of capacitors comprises capacitors <NUM> with values that are powers of <NUM> of a capacitance C. The capacitance C of the second SAR ADC stage <NUM> may be different from the capacitance C of the first SAR ADC stage <NUM>. The number of capacitors, and thereby the number of powers of <NUM>, depend on the resolution of the SAR ADC stage <NUM>. In the depicted example, the plurality of capacitors comprises capacitors <NUM> with capacitances C, 2C, 4C, 8C, and 16C, for a resolution of <NUM> bits. As depicted, each capacitance may be represented by a pair of capacitors comprising an upper capacitor 33a and a lower capacitor 33b in the plurality of capacitors <NUM>, wherein the upper capacitor 33a, during operation, is pre-charged to the supply voltage VDD and the lower capacitor 33b is pre-charged to ground. This provides a dual DAC structure to keep constant the common mode voltage at each comparator cycle.

Further, an adjustable, programmable capacitor <NUM> with capacitance CFS2 is connected between the common bus <NUM> and ground for adjusting the full scale of the second SAR ADC stage <NUM>.

The common bus <NUM> is connected to ground through a normally open switch <NUM> controlled by a signal line SRSTb. Switching of the plurality of capacitors <NUM>, the programmable capacitor and the switch <NUM> is controlled by a logic block <NUM>. A comparator <NUM> is connected to the input <NUM> and outputting to the logic block <NUM>.

With reference for <FIG> and <FIG>, an inter-stage residue amplifier <NUM>, connected between the first SAR ADC stage <NUM> and the second SAR ADC stage <NUM>, is configured to amplifying a residue voltage output on the output line <NUM> of the first SAR ADC stage <NUM>.

The inter-stage amplifier <NUM> comprises one or more MOS transistors, for example, as depicted, a complementary pair of an PMOS transistor <NUM> and a NMOS transistor <NUM>. The source and drain terminals of each of the PMOS transistor <NUM> and the NMOS transistor <NUM> are connected to each other and to a respective switch <NUM>, <NUM>, both controlled by a signal line SAMP, so that the respective source and drain terminals may be toggled between ground and a supply voltage VDD.

The gate terminals of the PMOS transistor <NUM> and the NMOS transistor <NUM> are connected to the output line <NUM> of the first SAR ADC stage <NUM> through a normally-open switch <NUM> controlled by a signal line SSHR and to the output <NUM> of the inter-stage amplifier <NUM>, which is connected to ground through a normally-open switch <NUM> controlled by a signal line SRSTa.

In the following, a method example <NUM> of analog-to-digital conversion of an analog voltage with the SAR ADC <NUM> of <FIG> will be described with reference to the timing diagram of <FIG> and the operation of the inter-stage residue amplifier <NUM> shown in <FIG>.

At <NUM>, the control signal STRK is put high (leading edge) by the logic block <NUM>, closing the switch <NUM>. In a tracking phase <NUM>, the lower capacitors 33b of the plurality of capacitors <NUM> and the capacitor <NUM> are charged to the input voltage vin, the other ends of the capacitors <NUM> being switched to ground. Meanwhile, the upper capacitors 33a of the plurality of capacitors <NUM> are charged to the difference of the input voltage vin and the supply voltage VDD. Thus, the input signal is first sampled on the full DAC array of the first SAR ADC stage <NUM>.

At <NUM>, the control signal STRK is put low (falling edge) by the logic block <NUM>, opening the switch <NUM>. Analog-to-digital conversion in the first SAR ADC stage <NUM> is performed, by successive approximation known per se, in a conversion phase <NUM> between <NUM> and <NUM>, by the comparator <NUM> comparing the voltage on the common bus <NUM> to ground during successive switching of the capacitors of the plurality of capacitors <NUM> to the supply voltage VDD or to ground depending on the comparator <NUM> output.

Meanwhile, still in the conversion phase <NUM> between <NUM> and <NUM>, a previous residue voltage from the first SAR ADC stage <NUM>, as amplified by the inter-stage amplifier <NUM>, is undergoing analog-to-digital conversion in the second SAR ADC stage <NUM>, by successive approximation as known per se, by the comparator <NUM> comparing the resulting voltage on the input <NUM> to ground during successive switching of the capacitors of the plurality of capacitors <NUM> to the supply voltage VDD or to ground depending on the comparator <NUM> output.

During the tracking phase <NUM>, and at the start of the conversion phase <NUM>, as shown in <FIG>, the signal line SSHR is kept low by one of the logic blocks <NUM>. As a result, the switch <NUM> between the common bus <NUM> and the inter-stage amplifier <NUM>, is open. Further, the signal line SAMP is low, resulting in the source and drain terminals of the NMOS transistor <NUM> being connected to the supply voltage VDD through the switch <NUM> and the source and drain terminals of the PMOS transistor <NUM> being connected to ground through the switch <NUM>. As a result, both the NMOS transistor <NUM> and the PMOS transistor <NUM> are in depletion mode.

At <NUM>, as shown in <FIG>, still in the conversion phase <NUM>, the signal line SAMP is brought high (rising edge) by one of the logic blocks <NUM>. Thereby, the source and drain terminals of the NMOS transistor <NUM> are toggled to ground by the switch <NUM> and the source and drain terminals of the PMOS transistor <NUM> are toggled to the supply voltage VDD by the switch <NUM>. As a result, both the NMOS transistor <NUM> and the PMOS transistor <NUM> are brought into strong inversion mode.

At <NUM>, through square pulses on each of the signal lines SRSTa and SRSTb, respectively, switches <NUM> and <NUM> are shortened to ground, discharging the capacitors of the of the second SAR ADC stage <NUM>.

At this time, the most significant bits of the analog level to be converted have been evaluated by the first SAR ADC stage <NUM>, and an analog residue voltage is present on the common bus <NUM>, ready to be transferred on to the inter-stage amplifier <NUM>. At <NUM>, this is performed through passive charge sharing, with a square pulse <NUM> on the signal line SSHR, resulting in the switch <NUM> closing for a short time. Thereby, the residue voltage is input on the gate terminals of the PMOS transistor <NUM> and the NMOS transistor <NUM>. With both the PMOS transistor <NUM> and the NMOS transistor <NUM> being in strong inversion mode, the analog residue voltage from the first SAR ADC stage <NUM> is sampled on a total capacitance <MAT> wherein Cinv,P and Cinv,N are the respective channel capacitances of the PMOS <NUM> and PMOS <NUM> transistors in strong inversion mode, and CDAC<NUM> is the total capacitance of the second SAR ADC stage <NUM> (compare <FIG>, where CDAC<NUM> is symbolically represented, to <FIG>).

At <NUM>, the signal line SAMP is again brought low, resulting in the source and drain terminals of the NMOS transistor <NUM> being toggled to the supply voltage VDD by the switch <NUM> and the source and drain terminals of the PMOS transistor <NUM> being toggled to ground by the switch <NUM>. As a result, both the NMOS transistor <NUM> and the PMOS transistor <NUM> are brought into depletion mode. The total capacitance is now <MAT>.

Cdep,P and Cdep,N are the respective gate capacitances of the PMOS <NUM> and NMOS <NUM> transistors in depletion mode; they are, respectively, much smaller than Cinv,P and Cinv,N. Since the total charge transferred from the first SAR ADC stage <NUM> is preserved, the voltage is amplified by a factor: <MAT>.

Assuming that the total capacitance CDAC<NUM> of the first SAR ADC stage <NUM> (again compare <FIG>) mainly is limited by matching requirements, its value can be made much bigger compared to the total capacitance CDAC<NUM> of the second SAR ADC stage <NUM> and of the inter-stage amplifier <NUM>. This results in a little attenuation of the analog residue voltage of the first SAR ADC stage due to the charge sharing operation and a negligible loss in the effective gain. The capacitance CBR of the capacitor <NUM> is sized to reduce the input capacitance of the second stage and the attenuation of the residue. Including the charge sharing attenuation, the effective gain, i.e., the factor by which the residue voltage from the first successive approximation in the first SAR ADC stage is amplified, is given by: <MAT>.

After a sufficient settling time, the comparator <NUM> of the second SAR ADC stage <NUM> is triggered and, in a second conversion phase <NUM>, a second successive approximation analog-to-digital conversion of the result of the amplifying is performed by the second SAR ADC stage <NUM>, estimating the less significant bits by successive approximation known per se, by successively switching the capacitors <NUM> of the plurality of capacitors of the second SAR ADC stage <NUM> to the supply voltage VDD and the comparator <NUM>, comparing the resulting voltage on the input <NUM> to ground.

Meanwhile, a new tracking phase <NUM> followed by a new conversion phase <NUM> is started at the first SAR ADC stage <NUM>, as described above.

In the following, some further performance characteristics of the pipelined SAR ADC <NUM> and the inter-stage amplifier <NUM> comprised therein, will be discussed.

The inter-stage amplifier <NUM> performs low power-amplification and dissipates only dynamic power. The power consumption is only due to the switching of the source/drain terminals of the MOS transistors <NUM> and <NUM> from ground to the supply voltage VDD and vice versa. As a result, the total energy dissipated per conversion step is given by <MAT>.

Due to the fully passive nature of this architecture, the only noise contributions on the signal path are due to kT/C noise. The total noise at the input of second stage does not depend on CDAC1 but only on the total capacitance of the backend. After the charge sharing operation, the noise is given by <MAT>.

At the falling edge <NUM> of SAMP, the residue and noise are amplified by the same gain. Thus, the inter-stage amplifier <NUM> itself does not imply any signal-to-nose degradation. After the amplification, the noise becomes <MAT>.

In the following, some simulation results related to the pipelined SAR ADC <NUM> and the inter-stage amplifier <NUM> comprised therein, will be discussed.

<FIG> shows the input capacitance of the inter-stage residue amplifier <NUM> versus input voltage. The simulation reported shows the total capacitance seen at the input of the inter-stage amplifier <NUM> for implementations having, respectively, two NMOS transistors <NUM>, two PMOS transistors <NUM>, or the complementary pair of the PMOS transistor <NUM> and the NMOS transistor <NUM>. The simulation was performed for a <NUM> CMOS process for a nominal capacitance of approximately <NUM> fF, equally distributed between the NMOS transistors <NUM>, the PMOS transistor <NUM>, and the capacitor, with the transistors are equally sized. As can be seen, the implementation comprising the complementary pair improves the minimization of the dependent variation of the capacitance, yielding higher linearity compared to the implementations comprising single-type PMOS or NMOS transistors.

<FIG> show simulated amplifier gain versus, respectively, supply voltage and temperature. The passive inter-stage amplifier <NUM> was in simulation with a dynamic amplifier reported, with both amplifiers implemented in a <NUM> CMOS process and designed for approximately the same gain. As can be seen, in contrast to the dynamic amplifier, the passive inter-stage amplifier <NUM> is more robust versus varying supply voltage and almost insensitive to temperature variations.

The effectiveness of the architecture was verified in schematic level simulations. The full circuit of the pipelined SAR ADC <NUM> was simulated in <NUM> CMOS process, with the first SAR ADC stage <NUM> and the second SAR ADC stage <NUM>, implementing, respectively <NUM> bits and <NUM> bits, with an <NUM>/<NUM>-bit inter-stage redundancy for an ideal quantization of <NUM> + <NUM> - log2(<NUM>/<NUM>) = <NUM> bits. With a full scale of the ADC of <NUM> V, the resulting voltage range of the analog residue voltage was approximately <NUM> mV. Such a small range ensures enough linearity of the amplifier. The MOS capacitors <NUM>, <NUM> and the capacitors of the second SAR ADC stage <NUM> were sized for a charge sharing attenuation of <NUM> and a gain of <NUM>. As a result, the full scale of the second SAR was approximately <NUM> mV which makes quite relaxed the noise requirements of the comparator. The capacitance of each MOS transistor was approximately <NUM> fF, with the total input capacitance of the second SAR ADC stage <NUM> similarly sized. As a result, the amplifier only consumed <NUM> fJ per conversion step for a <NUM> V supply voltage and the input referred noise of the amplifier was <NUM>µV. Integral nonlinearity (INL) and differential nonlinearity (DNL) were observed to be below half the least significant bit (LSB), showing that that the linearity of the amplifier is high enough for this ADC resolution.

In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims. For example, one or both of the first SAR ADC stage <NUM> and the second SAR ADC stage <NUM> may provide a higher or a lower ADC resolution than depicted above, reflected in more or fewer capacitors in the plurality of capacitors <NUM>.

Claim 1:
A pipelined successive approximation register analog-to-digital converter (<NUM>), SAR ADC, comprising:
a first SAR ADC stage (<NUM>) comprising a first plurality of capacitors configured for successive approximation of an input voltage;
a passive inter-stage amplifier (<NUM>) for amplifying an analog residue from said successive approximation of said first SAR ADC stage; and
a second SAR ADC stage (<NUM>) input from said inter-stage amplifier and comprising a second plurality of capacitors configured for successive approximation of the amplified analog residue,
wherein said passive inter-stage amplifier (<NUM>) comprises one or more MOS transistors (<NUM>, <NUM>), wherein the source and drain terminals of each of said one or more MOS transistors (<NUM>, <NUM>) are connected to each other and may be toggled between ground and a supply voltage, wherein the gates of said one or more MOS transistors are connectable to said first plurality of capacitors of said first SAR ADC stage, for passive charge sharing of said analog residue between said plurality of capacitors of said first SAR ADC stage and said one or more MOS transistors of said passive inter-stage amplifier (<NUM>), and the gates of said one or more MOS transistors are connected to said second plurality of capacitors of said second SAR ADC stage for passive charge sharing of the amplified analog residue voltage between said plurality of MOS transistors of said passive inter-stage amplifier (<NUM>) and said second plurality of capacitors, and wherein said one or more MOS transistors are configured to passively amplify the voltage at their gates when their source and drain terminals are toggled between ground the supply voltage.