Patent Description:
Smelyanskiy et al. discusses "implementation of a quantum simulator on a classical computer, that can simulate general single qubit gates and two-qubit controlled gates. " See <NPL>. Further, Smelyanskiy et al. discusses performance of "a number of single- and multi-node optimizations, including vectorization, multi-threading, cache blocking, as well as overlapping computation with communication.

However, these simulations remain inefficient regarding memory utilization (e.g., cache hits and misses) and execution time (e.g., the time needed to perform the simulated computation).

To facilitate the use and research of quantum systems, embodiments of the invention for simulating quantum circuits are described herein. In one embodiment of the invention, software can be installed on a computing device that allows a user to run quantum circuit-based experimental programs on a quantum circuit simulator running locally or one or more simulators that can be accessed remotely over a network. Embodiments of the invention allow the user to create and input quantum circuits in textual form, such as via text editor, in graphical form, etc. A quantum circuit representation, such as an Open Quantum Assembly Language (QASM or OpenQASM) file, is then generated by the software. As will be described further herein, the quantum circuit representation is optimized to minimize the computing resources needed to simulate the quantum circuit. Simulations of the quantum circuit are requested (locally or from a remote system) and results are output to the user. The results can be in any graphical textual form that facilitates analysis by a user or another computing device.

A problem of the art is that fusion of a measure gate with another quantum gate for simulating a quantum circuit was neither taught nor suggested because of the complexity of the operations performed to simulate a measure gate. According to the invention, dividing the measure gate into virtual gates provides a solution. Although gate fusion for quantum simulation are known, the invention is the first to recognize gate fusion with at least a portion of a measure gate based on dividing the measure gate into virtual gates.

An advantage of embodiments of the invention is to mitigate the relatively high computational demands placed upon a system running such a simulation. Fusion of the measure gate with one or more other quantum gates enables load and store operations executed for the simulation to be conducted more efficiently, based on cache blocking for the computations used by the simulation. Accordingly, the invention provides improved temporal locality, permit more efficient memory usage, and reduce execution time of the simulation.

Furthermore, in the invention, the measure gate is divided into virtual gates for a sum operation, a determine operation, and a renorm (or renormalization) operation. The virtual gate for the sum operation is then fused to a previous quantum gate adjacent to the measure gate. The virtual gate for the renorm operation can be fused with the quantum gate that is adjacent after the measure gate. In the invention where the measure gate is divided into a first virtual gate for a sum operation, a second virtual gate for a determine operation, and third virtual gate for a normalization operation, are useful to enable virtual gates for the measure gate to be fused with different quantum gates, for example, the quantum gates that are adjacent before and after the measure gate in the quantum circuit.

The embodiments of the invention where a simulation request is submitted to a location on the network are also useful for enabling the system and methods to utilize a remote computing resource to perform the simulation, for example, for a simulation for large qubit quantum circuit. In addition, these embodiments of the invention are useful to allow cooperation with multiple simulators and/or hardware resources over a network.

Referring to <FIG>, a quantum circuit <NUM> comprises a first quantum gate, a U3 gate <NUM> operating on a qubit q1, a measure gate <NUM> operating on a qubit q0, and an additional quantum gate, such as a second U3 gate <NUM> operating on qubit q1.

However, the measure gate <NUM> is divided into virtual gates <NUM>, <NUM>, and <NUM>. A first virtual gate <NUM> corresponds to sum operations based on calculating the probability of a qubit being in state <NUM> or <NUM> based on iterating across all states. A second virtual gate <NUM> corresponds to a determine operation to determine whether a qubit is in state <NUM> or <NUM> based on a random number. A third virtual gate <NUM> corresponds to a normalization or renorm operation that normalizes the state of the qubit.

One or more of the virtual gates <NUM>, <NUM>, and <NUM> are then fused with a quantum gate, such as quantum gates <NUM> and <NUM>. For example, as shown, to facilitate a simulation of the quantum circuit <NUM>, virtual gate <NUM> can be fused (and/or combined) with U3 gate <NUM> and virtual gate <NUM> can be fused (and/or combined) with U3 gate <NUM>. As shown, this fusion allows the store and load operations to be executed based on block caching. For example, as shown in operations <NUM> and <NUM>, halves of U3 gate <NUM> and virtual gate <NUM> are combined and executed within the same memory access. Likewise, as shown in operations <NUM> and <NUM>, halves of U3 gate <NUM> and virtual gate <NUM> are combined and executed within the same memory access. This approach thus allows the simulation to be performed in fewer operations.

In addition, the operations for virtual gates <NUM> and <NUM> can scheduled and executed based on the commutativity (i.e., the extent by which changing of the order of operations when fusing the virtual gates <NUM> and <NUM> with a quantum gate does not change a result of the overall operation) of the operations for the quantum gate being fused. For example, the sum operations implemented by virtual gate <NUM> can be executed and aggregated earlier and virtual gate <NUM> can be executed and aggregated later based on the extent of commutativity of the operations being implemented by virtual gates <NUM> and <NUM> and a respective quantum gate to which they are being fused. As another example, fusing <NUM> quantum gates followed by single qubit measurements can be efficiently simulated. In addition, for example, quantum circuits composed of exponentiated Pauli operators can be simulated efficiently when followed by single-qubit measurements.

Referring to <FIG>, the measure gate <NUM> is divided into virtual gates <NUM>, <NUM>, and <NUM> for sum, determine, and renorm operations respectively. Virtual gates <NUM>, <NUM>, and <NUM> can be implemented or compiled into program code to perform the simulation.

Pseudo code portion <NUM> performs the sum operations in measure gate <NUM> for virtual gate <NUM>. Pseudo code <NUM> performs the determine operation in measure gate <NUM> for virtual gate <NUM>. And, pseudo code <NUM> performs the renorm operations in measure gate <NUM> for virtual gate <NUM>.

Accordingly, when a simulation is performed, these code portions <NUM>, <NUM> and <NUM> can be fused with the store and load operations for other quantum gate, such as quantum gates <NUM> and <NUM> (not shown in <FIG>) and optimized to mitigate the memory access requests and improve their locality in memory.

Referring to <FIG>, a system that facilitates quantum computing simulation can be implemented based on a front-end system <NUM> and a back-end system <NUM>.

The systems <NUM> and <NUM> can comprise a processor, a memory, network interface, and/or a storage. The memory stores computer executable components and instructions.

Aspects of systems (e.g., systems <NUM>, <NUM>, and the like), apparatuses, or processes explained herein can constitute machine-executable component(s) embodied within machine(s), e.g., embodied in one or more computer readable mediums (or media) associated with one or more machines. Such component(s), when executed by the one or more machines, e.g., computer(s), computing device(s), virtual machine(s), etc. can cause the machine(s) to perform the operations described. For example, <FIG> describes a computing environment <NUM> that can be implemented in systems <NUM> and <NUM>.

The systems <NUM> and <NUM> can be any type of component, machine, device, facility, apparatus, and/or instrument that comprises a processor and/or can be capable of effective and/or operative communication with a wired and/or wireless network. Components, machines, apparatuses, devices, facilities, and/or instrumentalities that can comprise the front-end system <NUM> can include tablet computing devices, handheld devices, server class computing machines and/or databases, laptop computers, notebook computers, desktop computers, cell phones, smart phones, consumer appliances and/or instrumentation, industrial and/or commercial devices, hand-held devices, digital assistants, multimedia Internet enabled phones, multimedia players, and the like.

Components, machines, apparatuses, devices, facilities, and/or instrumentalities that can comprise the back-end system <NUM> can include, server class computing machines and/or databases, laptop computers, notebook computers, desktop computers, and the like. The system <NUM> and/or components of the system <NUM> can be employed to solve new problems that arise through advancements in technologies mentioned above, computer architecture, and/or the like. The system <NUM> can provide technical improvements to quantum computing systems, quantum circuit systems, quantum processor systems, artificial intelligence systems, and/or other systems. The system <NUM> can also provide technical improvements to a quantum processor (e.g., a superconducting quantum processor) by improving processing performance, processing efficiency, processing characteristics, timing characteristics, and/or power efficiency of the quantum processor.

Accordingly, systems <NUM> and <NUM> can employ hardware and/or software to solve problems that are highly technical in nature, that are not abstract and that cannot be performed as a set of mental acts by a human. Further, in certain embodiments, some of the processes performed can be performed by one or more specialized computers (e.g., one or more specialized processing units, a specialized computer with a quantum computing component, etc.) to carry out defined tasks related to machine learning.

The front-end system <NUM> can comprise a development component <NUM> and an interface component <NUM>. These components will now be further described.

Development component <NUM> provides a development platform that allows a user to create/input quantum circuits, compile the quantum circuits into a representation that can be simulated, such as a QASM file, and simulate the quantum circuit. The development component <NUM> is a software development kit that can be installed on front-end system <NUM>. Development component <NUM> can comprise various application programming interfaces (APIs) and libraries that interface a programming language, such as Python or C++. In addition, the development component <NUM> can comprise various tools to assist in creating and editing quantum circuit data, such as quantum circuit data <NUM>, and compile the quantum circuit data <NUM> into a quantum circuit representation, such as a QASM file. The development component <NUM> can also comprise various tools to analyze and format simulation result data <NUM> into graphical, textual, or other desired format.

As shown, the development component <NUM> can comprise a compiler <NUM>. Compiler <NUM> can be a compiler or transcompiler that transforms and converts quantum circuit data <NUM> into an appropriate representation, such as a QASM file. Compiler <NUM> can provide allow the quantum circuit data <NUM> to be simulated based on different hardware configurations, quantum scope and breadth, etc. The compiler <NUM> can receive as input the quantum circuit data <NUM>, unroll quantum circuit data <NUM> by expanding the data structures and definitions, perform various swaps to optimize the quantum circuit, and perform one or more gate cancellations.

The compiler <NUM> divides a measure gate, such as measure gate <NUM> into virtual gates <NUM>, <NUM>, and <NUM>. As noted above, virtual gate <NUM> can correspond to sum operations based on calculating the probability of a qubit being in state <NUM> or <NUM> based on iterating across all states. Virtual gate <NUM> can correspond to a determine operation to determine whether a qubit is in state <NUM> or <NUM> based on a random number. Virtual gate <NUM> can correspond to a normalization or renorm operation that normalizes the state of the qubit.

Compiler <NUM> can then fuse one or more of the virtual gates <NUM>, <NUM>, and <NUM> can then be fused with a quantum gate indicated in the quantum circuit data <NUM>, for example, as described with reference to <FIG> and <FIG>.

Local simulator <NUM> can be simulator that is executed locally on front-end system <NUM>. Local simulator <NUM> can provide a local simulation environment to develop and deploy simulation experiments on front-end system <NUM>.

Interface component <NUM> provides an interface for front-end system <NUM> to communicate with other components running on system <NUM>, such as compiler <NUM> and local simulator <NUM>, as well as other computing devices, such as back-end system <NUM>. Interface component <NUM> is software that provides various routines, protocols, and tools for front-end system <NUM>.

The back-end system <NUM> provides a remote additional resource to perform quantum computing simulations. For example, back-end system <NUM> can be accessible via a network and provide an array of simulators and quantum computing hardware. A plurality of front-end systems <NUM> can interface with back-end system <NUM>, for example, to submit simulation requests. As shown, back-end system <NUM> can comprise an interface component <NUM> and a simulation controller <NUM>.

Interface component <NUM> is a corresponding API to interface component <NUM> running on front-end system <NUM>. interface component <NUM> can assign unique tokens to each simulation request received from front-end system <NUM>.

Simulation controller <NUM> schedules, executes, and outputs the results of the simulation requests, for example, received from front-end system <NUM>. The simulation controller <NUM> provide simulation result data <NUM> via interface component <NUM>. Simulation controller <NUM> can provide simulation result data <NUM> in various forms, such as graphical data, text/numerical data, stream data, etc..

<FIG> is a flow diagram of a method <NUM> that can illustrate a process for simulating a quantum circuit locally on a computing device, such as front-end system <NUM> and fusing at least a portion of the measure gate with a quantum gate to improve the simulation.

At <NUM>, quantum circuit data <NUM> is received by front-end system <NUM> (via development component <NUM>) for a quantum circuit. For example, a user at front-end system <NUM> can use development component <NUM> to receive quantum circuit data <NUM> for a quantum circuit. The quantum circuit data <NUM> can be provided from a quantum algorithm, a text editor, such as QASM editor, or other form of data input. In response, development component <NUM> and compiler <NUM> can then generate a representation of the quantum circuit, such as in the form of a QASM file or other data format.

At <NUM>, measure gate <NUM> is divided (e.g., via compiler <NUM> in development component <NUM>) into one or more virtual gates. For example, compiler <NUM> in development component <NUM> can compile analyze and parse the quantum circuit data <NUM> and perform various transformation or edits to the quantum circuit. As noted above, the compiler <NUM> can divide measure gates, such as measure gate <NUM>, into one or more virtual gates <NUM>, <NUM>, and <NUM>.

At <NUM>, one or more of the virtual gates <NUM>, <NUM>, and <NUM> are fused (e.g., by compiler <NUM> in development component <NUM>) with a quantum gate (such as measure gate <NUM>) in the quantum circuit represented in quantum circuit data <NUM>. For example, compiler <NUM> compile virtual gates <NUM>, <NUM>, and <NUM> into code portions <NUM>, <NUM>, and <NUM> and combine these code portions with operations with a quantum gate, such as a quantum gate adjacent to the measure gate <NUM>. Development component <NUM> can then generate a new, revised representation of the quantum circuit and modify quantum circuit data <NUM>, for example, as a revised QASM file.

At <NUM>, the quantum circuit is simulated (e.g., by local simulator <NUM>). For example, development component <NUM> can submit a simulation request to interface component <NUM> with an address locator corresponding to local simulator <NUM>. Alternatively, development component <NUM> can use interface component <NUM> and submit a simulation request to back-end system <NUM>. For example, the development component <NUM> may determine a location of a simulator, for example, based on a network location specified in the QASM file for one or more simulators hosted by back-end system <NUM>.

<FIG> is a flow diagram of a method <NUM> for submitting a simulation request to remote device, such as back-end system <NUM>. The simulation request is based upon fusing at least a portion of a measure gate with a quantum gate to improve the simulation's memory and processing performance.

At <NUM>, quantum circuit data <NUM> is received (e.g., by development component <NUM>) for a quantum circuit. For example, a user at front-end system <NUM> can use development component <NUM> to receive quantum circuit data <NUM> for a quantum circuit. The quantum circuit data <NUM> can be provided from a quantum algorithm, a text editor, such as QASM editor, or other form of data input. In response, development component <NUM> and compiler <NUM> can then generate a representation of the quantum circuit, such as in the form of a QASM file or other data format.

At <NUM>, measure gate <NUM> is divided (by compiler <NUM> in development component <NUM>) into one or more virtual gates <NUM>, <NUM>, and <NUM>. For example, compiler <NUM> in development component <NUM> can compile analyze and parse the quantum circuit data <NUM> and perform various transformation or edits to the quantum circuit. As noted above, in one embodiment, the compiler <NUM> can divide measure gates, such as measure gate <NUM>, into one or more virtual gates <NUM>, <NUM>, and <NUM>,.

At <NUM>, one or more of the virtual gates <NUM> and <NUM> are fused with a quantum gate (such as measure gate <NUM>) in the quantum circuit. For example, compiler <NUM> compiles virtual gates <NUM>, <NUM>, and <NUM> into code portions <NUM>, <NUM>, and <NUM> and combine these code portions with operations with a quantum gate, such as a quantum gate adjacent to the measure gate <NUM>. For example, in one embodiment, the compiler <NUM> fuses virtual gates by creating a <NUM>n × <NUM>n unitary matrix to represent each virtual gate being fused and multiplying all the unitary matrixes to calculate a new <NUM>n × <NUM>n matrix to represent the gate fusion.

At <NUM>, a representation of the quantum circuit is generated (by development component <NUM>) based on the fusion of the virtual gate and a quantum gate in the quantum circuit. For example, development component <NUM> can generate a new, revised representation of the quantum circuit and modify quantum circuit data <NUM>, for example, as a revised QASM file.

At <NUM>, the development component <NUM> can then create a simulation request based on quantum circuit data <NUM> and transmit (e.g., via the interface component <NUM>) the simulation request to back-end system <NUM>. For example, development component <NUM> can submit a simulation request to interface component <NUM> having an address locator corresponding to the location of back-end system <NUM> on a network. In response, interface component <NUM> can forward the simulation request to interface component <NUM> at back-end system <NUM>. Simulation controller <NUM> can then schedule and run the simulation. In some embodiments, simulation controller <NUM> can provide a plurality of simulation platforms corresponding to quantum computing devices having different breadth of qubits, e.g., of <NUM> qubits or more. Simulation controller <NUM> will then generate simulation result data <NUM>, for example, based on compiling and executing program code (e.g., QASM data) in the simulation request. The simulation result data can be in any suitable form, such as text, numerical data, graphical data, stream data, etc..

At <NUM>, simulation results are received. For example, front-end system <NUM> can receive simulation result data <NUM> from back-end system <NUM> via interface components <NUM> and <NUM>. In one embodiment, a user can use one or more tools provided by development component <NUM> to output, analyze, and/or visualize the simulation result data <NUM>.

In an example implementation, the program instructions can cause a processor, for example on front-end system <NUM> to receive quantum circuit data that represents a quantum circuit. The quantum circuit comprises a quantum gate and a measure gate. The program instructions can further cause the processor to divide the measure gate into one or more virtual gates and simulate the quantum circuit based on a fusion of at least one of the one or more virtual gates with the quantum gate to generate a simulation result
According to another example implementation, the program instructions can cause a processor, for example on front-end system <NUM>, to receive quantum circuit data for a quantum circuit, generate a representation of the quantum circuit based on dividing the measure gate into one or more virtual gates and fusing at least one of the one or more virtual gates with the quantum gate; and transmitting, over a network, for example to back-end system <NUM>, a simulation request based on the representation of the quantum circuit.

For simplicity of explanation, the computer-implemented methodologies are depicted and described as a series of acts. It is to be understood and appreciated that the subject innovation is not limited by the acts illustrated and/or by the order of acts, for example acts can occur in various orders and/or concurrently, and with other acts not presented and described herein. Furthermore, not all illustrated acts can be required to implement the computer-implemented methodologies in accordance with the invention. In addition, those skilled in the art will understand and appreciate that the computer-implemented methodologies could alternatively be represented as a series of interrelated states via a state diagram or events. Additionally, it should be further appreciated that the computer-implemented methodologies disclosed hereinafter and throughout this specification are capable of being stored on an article of manufacture to facilitate transporting and transferring such computer-implemented methodologies to computers. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage media.

In order to provide a context for the various aspects of the invention, <FIG> as well as the following discussion are intended to provide a general description of a suitable environment in which the various aspects of the disclosed subject matter can be implemented.

<FIG> is a block diagram of an operating environment <NUM> in which one or more embodiments of the invention can be facilitated. With reference to <FIG>, operating environment <NUM> can include a computer <NUM>. The computer <NUM> can also include a processing unit <NUM>, a system memory <NUM>, and a system bus <NUM>. The system bus <NUM> couples system components including, but not limited to, the system memory <NUM> to the processing unit <NUM>. The processing unit <NUM> can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit <NUM>. The system bus <NUM> can be any of several types of bus structure(s) including the memory bus or memory controller, a peripheral bus or external bus, and/or a local bus using any variety of available bus architectures including, but not limited to, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), Video Electronics Standards Association (VESA)Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE <NUM>), and Small Computer Systems interface (SCSI). The system memory <NUM> can also include volatile memory <NUM> and nonvolatile memory <NUM>. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer <NUM>, such as during start-up, is stored in nonvolatile memory <NUM>. By way of illustration, and not limitation, nonvolatile memory <NUM> can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), flash memory, or nonvolatile Random Access Memory (RAM) (e.g., Ferroelectric RAM (FeRAM)). Volatile memory <NUM> can also include RAM, which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), Direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM.

Computer <NUM> can also include removable/non-removable, volatile/non-volatile computer storage media. <FIG> illustrates, for example, a disk storage <NUM>. Disk storage <NUM> can also include, but is not limited to, devices like a magnetic disk drive, floppy disk drive, tape drive, Jaz drive, Zip drive, LS-<NUM> drive, flash memory card, or memory stick. The disk storage <NUM> also can include storage media separately or in combination with other storage media including, but not limited to, an optical disk drive such as a compact disk ROM device (CD-ROM), CD recordable drive (CD-R Drive), CD rewritable drive (CD-RW Drive) or a digital versatile disk ROM drive (DVD-ROM). To facilitate connection of the disk storage <NUM> to the system bus <NUM>, a removable or non-removable interface is typically used, such as interface <NUM>. <FIG> also depicts software that acts as an intermediary between users and the basic computer resources described in the suitable operating environment <NUM>. Such software can also include, for example, an operating system <NUM>. Operating system <NUM>, which can be stored on disk storage <NUM>, acts to control and allocate resources of the computer <NUM>. System applications <NUM> take advantage of the management of resources by operating system <NUM> through program modules <NUM> and program data <NUM>, e.g., stored either in system memory <NUM> or on disk storage <NUM>. It is to be appreciated that this disclosure can be implemented with various operating systems or combinations of operating systems. A user enters commands or information into the computer <NUM> through input device(s) <NUM>. Input devices <NUM> include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit <NUM> through the system bus <NUM> via interface port(s) <NUM>. interface port(s) <NUM> include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device(s) <NUM> use some of the same type of ports as input device(s) <NUM>. Thus, for example, a USB port can be used to provide input to computer <NUM>, and to output information from computer <NUM> to an output device <NUM>. Output adapter <NUM> is provided to illustrate that there are some output devices <NUM> like monitors, speakers, and printers, among other output devices <NUM>, which require special adapters. The output adapters <NUM> include, by way of illustration and not limitation, video and sound cards that provide a method of connection between the output device <NUM> and the system bus <NUM>. It should be noted that other devices and/or systems of devices provide both input and output capabilities such as remote computer(s) <NUM>.

Computer <NUM> can operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s) <NUM>. The remote computer(s) <NUM> can be a computer, a server, a router, a network PC, a workstation, a microprocessor-based appliance, a peer device or other common network node and the like, and typically can also include many or all of the elements described relative to computer <NUM>. For purposes of brevity, only a memory storage device <NUM> is illustrated with remote computer(s) <NUM>. Remote computer(s) <NUM> is logically connected to computer <NUM> through a network interface <NUM> and then physically connected via communication connection <NUM>. Network interface <NUM> encompasses wire and/or wireless communication networks such as local-area networks (LAN), wide-area networks (WAN), cellular networks, etc. LAN technologies include Fiber Distributed Data interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring and the like. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL). Communication connection(s) <NUM> refers to the hardware/software employed to connect the network interface <NUM> to the system bus <NUM>. While communication connection <NUM> is shown for illustrative clarity inside computer <NUM>, it can also be external to computer <NUM>. The hardware/software for connection to the network interface <NUM> can also include, for exemplary purposes only, internal and external technologies such as, modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

The present invention can be a system, a method, an apparatus and/or a computer program product at any possible technical detail level of integration. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium can also include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing.

These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create method for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks. The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational acts to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

While the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on a computer and/or computers, those skilled in the art will recognize that this disclosure also can be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform tasks and/or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive computer-implemented methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, mini-computing devices, mainframe computers, as well as computers, hand-held computing devices (e.g., PDA, phone), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all aspects of this disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules can be in both local and remote memory storage devices.

As used in this application, the terms "component," "system," "platform," "interface," and the like, can refer to and/or can include a computer-related entity or an entity related to an operational machine with one or more specific functionalities. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between two or more computers. In another example, respective components can execute from various computer readable media having various data structures stored thereon. The components can communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems via the signal). As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor can be internal or external to the apparatus and can execute at least a part of the software or firmware application. Yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts, wherein the electronic components can include a processor or other method to execute software or firmware that confers at least in part the functionality of the electronic components. In an aspect, a component can emulate an electronic component via a virtual machine, e.g., within a cloud computing system.

Claim 1:
A system, comprising:
a memory (<NUM>) that stores computer executable components; and
a processor (<NUM>) that executes the computer executable components stored in the memory (<NUM>),
wherein the computer executable components comprise:
a development component (<NUM>) that receives data for a quantum circuit (<NUM>), wherein the quantum circuit (<NUM>) comprises a quantum gate (<NUM>) that manipulates a state of a qubit (q0, q1) in the quantum circuit (<NUM>) and a measure gate (<NUM>) that measures the state of the qubit in the quantum circuit (<NUM>), and wherein the development component (<NUM>) generates a representation of the quantum circuit (<NUM>) based on dividing the measure gate (<NUM>) into virtual gates (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) and fusing at least one of the virtual gates (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) with the quantum gate (<NUM>);
an interface component (<NUM>, <NUM>) that submits a simulation request based on the representation of the quantum circuit (<NUM>) and receives a simulation result based on the simulation request,
wherein load and store operations executed for the simulation are conducted based on cache blocking for the computations used by the simulation enabled by fusing at least one of the virtual gates (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) with the quantum gate (<NUM>), and
wherein the development component (<NUM>) generates the representation of the quantum circuit (<NUM>) based on dividing the measure gate (<NUM>) into a first virtual gate (<NUM>, <NUM>) for a sum operation of quantum states of a qubit (q0, q1) being measured by the measure gate (<NUM>), a second virtual gate (<NUM>, <NUM>) for a determine operation that determines a state of <NUM> or <NUM> of the qubit (q0, q1) being measured, and a third virtual gate (<NUM>, <NUM>) for a normalization operation that normalizes a state of the qubit (q0, q1) being measured.