Patent Description:
The subject-matter of claim <NUM> is reflected by the embodiments shown in <FIG> and <FIG>.

A switched mode power supply (SMPS) can include elements such as a controller, gate driver, and a power converter. In some examples, the SMPS further includes a current sense circuit. The current sense circuit measures a discontinuous current of the power converter and outputs a signal representative of (e.g., proportional to) the current being measured. The discontinuous current results from switching of the power converter. In some implementations, each current to be measured has a dedicated circuit. For example, a dedicated circuit may measure input current, another dedicated circuit may measure average inductor current, and so forth. However, the implementation of multiple dedicated circuits for monitoring the power converter can be inefficient in both power consumption during operation and space consumed by the circuits. Additionally, at least some current sense circuits can have inefficient topologies. For example, some current sense circuits may sense a current, process the current signal to convert the current signal to a voltage signal that is mirrored through a voltage mirror, and then process the voltage signal to convert that voltage signal back to a current signal. At least some of these signals have a high frequency such that one or more high bandwidth amplifiers are used in the processing. The high bandwidth amplifiers, in some examples, consume a greater amount of current than low bandwidth amplifiers and require additional circuit complexity to provide for offset cancellation. In contrast, a current sense circuit that performs the processing at low frequency and utilizing low bandwidth amplifiers may provide certain benefits in current consumption and circuit complexity. The benefits can lead to reduced cost of manufacture, implementation, and/or operation of the current sense circuit.

At least some aspects of the present disclosure provide for a current sense circuit. The current sense circuit, in at least some examples, senses a current flowing through a power converter and outputs a signal having a current proportional to the current flowing through the power converter. In some examples, the current flowing through the power converter is an average input current (IINAVE). In other examples, the current flowing through the power converter is an average inductor current (ILAVE). Accordingly, in at least some examples the current sense circuit is a multi-function circuit. For example, when in a first configuration the current sense circuit generates an output signal proportional to IINAVE. When in a second configuration, the current sense circuit generates an output signal proportional to ILAVE. The current sense circuit, in various implementations, is suitable for measuring IINAVE and ILAVE in a plurality of power converter topologies including buck, buck-boost, boost, and inverting buck-boost. More generally, the teachings of the present disclosure may be applicable to any switched mode system, whether related to providing power or unrelated to providing power.

In at least some examples, the current sense circuit amplifies a difference between a current flowing through a sense FET (e.g., a scaled replica FET of the high side transistor) of the current sense circuit and an output of a low-pass filter that averages a current flowing through the current sense circuit. The current flowing through the current sense circuit that is averaged may be, for example, an input current of the power converter or an inductor current of the power converter. The current sense circuit further drives a voltage controlled current source based on a result of the amplification to generate the current proportional to the current flowing through the power converter. In at least some examples, this current is provided to another circuit or component for monitoring of the power converter and/or control of the power converter. By low-pass filtering the current flowing through the current sense circuit, in at least some examples, subsequent processing of the current sense circuit may be performed at a low frequency. For example, at least partially because of the filtering, the amplifier that amplifies the difference between the current flowing through the sense FET and the output of the low-pass filter may be a low bandwidth amplifier, providing at least some of the benefits discussed above.

Turning now to <FIG>, a block diagram of an illustrative SMPS <NUM> is shown. In at least one example, the SMPS <NUM> includes a controller <NUM> and a power converter <NUM>. The SMPS <NUM>, at least through the power converter <NUM>, switches power provided at the node <NUM> by a power source <NUM>. In some examples, the power is switched to a load <NUM>. The power converter <NUM> is, for example, a buck-boost power converter that is capable of operating according to a buck mode of operation, a boost mode of operation, and a buck-boost mode of operation. In other examples, the power converter <NUM> is a buck power converter capable of operating according to the buck mode of operation. In yet other examples, the power converter <NUM> is a boost converter capable of operating according to the boost mode of operation. In yet other examples, the power converter <NUM> is an inverting buck converter capable of operating according to the buck mode of operation and inverting a polarity of VOUT with respect to a polarity of VIN.

In at least one example, the controller <NUM> includes, or is configured to couple to, a feedback circuit <NUM>, a current sense circuit <NUM>, a processing element <NUM>, and a gate driver <NUM>. At least one example of the SMPS <NUM> includes at least some aspects of the controller <NUM> and the power converter <NUM> on a same semiconductor die and/or in a same component package, while in other examples the controller <NUM> and the power converter <NUM> may be fabricated separately and configured to couple together. For example, at least some aspects of the controller <NUM> may be fabricated separately and coupled together. Accordingly, while illustrated as not including the gate driver <NUM>, in at least one example the controller <NUM> does include the gate driver. Additionally, in at least some examples the controller <NUM> does not include the current sense circuit <NUM> but is instead configured to couple to the current sense circuit <NUM>. Alternatively, in at least some examples one or more components of the power converter <NUM> are implemented on a same die as one or more components of the current sense circuit <NUM>. Further, while the current sense circuit <NUM> is described herein as detecting a current flowing through the power converter <NUM>, the present disclosure is not so limited. Instead, the current sense circuit <NUM> is suitable for measuring a discontinuous (e.g., switched) current in any circuit in which the current flows through a FET across which the current sense circuit <NUM> can couple to sense or measure the discontinuous current.

In at least one example, the feedback circuit <NUM> includes a resistor <NUM> coupled between a node <NUM> and a node <NUM> and a resistor <NUM> coupled between the node <NUM> and a ground node <NUM>. The feedback circuit <NUM> further includes an amplifier <NUM> having a first input terminal (e.g., a non-inverting input terminal) coupled to a node <NUM> and configured to receive a reference voltage (VREF) at the node <NUM>. The amplifier <NUM> further has a second input terminal (e.g., an inverting input terminal) coupled to the node <NUM>, and an output terminal coupled to a node <NUM>. A resistor <NUM> is coupled between the node <NUM> and a top plate of a capacitor <NUM> and a bottom plate of the capacitor <NUM> is coupled to the ground node <NUM>.

In at least some examples, the current sense circuit <NUM> has front end <NUM> having a first input terminal coupled to the power converter <NUM>, a second input terminal coupled to the power converter <NUM>, a gain stage <NUM> coupled between the front end <NUM> and a voltage controlled current source <NUM> having an output terminal. In some implementations, the output terminal of the voltage controlled current source <NUM> is coupled to the node <NUM>. Although not shown, in at least some implementations, the output terminal of the voltage controlled current source <NUM> is further coupled to an input terminal of the processing element <NUM>. The processing element <NUM> further has one or more output terminals coupled to additional input terminals of the current sense circuit <NUM> (e.g., control terminals of switches of the current sense circuit <NUM>, such as in the front end <NUM>). The processing element <NUM> is, in various examples, a controller, microcontroller, processor, logic circuit, or any other component capable of receiving input signals, making one or more determinations or decisions, and outputting one or more control signals. A buffer or other isolation circuit (not shown) may be coupled between the node <NUM> and the resistor <NUM> to prevent impedance of the resistor <NUM> and/or the resistor <NUM> from affecting operation of the current sense circuit <NUM> and/or the processing element <NUM>.

In some examples, the gate driver <NUM> has an input terminal coupled to the node <NUM>, and one or more output terminals coupled to the power converter <NUM> While illustrated as having only one coupling between the driver <NUM> and the power converter <NUM>, in various examples the driver <NUM> may have a plurality of couplings to the power converter <NUM>. For example, the driver <NUM> may include a first output terminal coupled to a gate terminal of a high-side transistor (not shown) of the power converter <NUM> and a second output terminal coupled to a gate terminal of a low-side transistor (not shown) of the power converter <NUM>. In at least some examples, the gate driver <NUM> outputs a high-side gate control signal (HSCTRL) at a first output terminal of the gate driver <NUM> and outputs a low-side gate control signal (LSCTRL) at a second output terminal of the gate driver <NUM>. Generally, in at least some examples a number of couplings between the driver <NUM> and the power converter <NUM> may be equal to or greater than a number of transistors (not shown) of the power converter <NUM>.

In at least one example, the SMPS <NUM> is configured to receive VIN from the power source <NUM> and provide VOUT at the node <NUM> for supplying the load <NUM>. VOUT is based at least partially on the input voltage and VREF received by the SMPS <NUM> at the node <NUM>. VREF may be received from any suitable device (not shown) such as a processor, microcontroller, or any other device exerting control over the SMPS <NUM> to control a value of VOUT. Although not shown, in at least some examples VREF is provided to the feedback circuit <NUM> by the processing element <NUM>. In other examples, VREF is received by the SMPS <NUM> at a pin or other user-facing terminal at which a user provides a signal for use as VREF. VREF has a value representative of a desired (e.g., user-desired, target, preconfigured, programmed, etc.) value of a feedback voltage (VFB) that is a scaled representation of the output of the current sense circuit <NUM>. For example, VFB is a scaled representation of IINAVE or a scaled representation of ILAVE.

In at least one example, the feedback circuit <NUM> is configured to receive VREF and the output of the current sense circuit <NUM> and generate an error signal (ERROR) indicating a variation in VREF from VFB. In at least some examples, VFB is an output of a voltage divider formed of the resistor <NUM> and the resistor <NUM>, where an input to the voltage divider is the output of the current sense circuit <NUM>. In at least some examples, the error signal is generated by the amplifier <NUM> (e.g., such as an error amplifier or a transconductance amplifier), where a current value of the error signal indicates the variation in VREF from VFB. The error signal is subsequently filtered by the resistor <NUM> and the capacitor <NUM> before being received as a control signal by the gate driver <NUM>.

The current sense circuit <NUM>, in some examples, monitors a current flowing through the power converter <NUM> (e.g., IINAVE or ILAVE) and generates an output signal. Based on the monitored current, the current sense circuit <NUM> generates and outputs a signal having a current proportional to the current flowing through the power converter <NUM>. In at least some examples the current sense circuit <NUM> is a multi-function circuit (e.g., monitoring IINAVE or ILAVE), as discussed above. For example, when in a first configuration the current sense circuit <NUM> generates an output signal proportional to IINAVE. When in a second configuration, the current sense circuit <NUM> generates an output signal proportional to ILAVE. The configuration of the current sense circuit <NUM> is changed, in some implementations, by one or more signals received by the front end <NUM>. For example, the front end <NUM> receives one or more signals that control switches (not shown) of the front end <NUM> to be in open or closed states, defining the configuration of the current sense circuit <NUM>. In some examples, the gain stage <NUM> of the current sense circuit <NUM> amplifies a difference between a current flowing through a sense FET (not shown) of the front end <NUM> and an output of a low-pass filter (not shown) of the front end <NUM>. The current sense circuit <NUM> further drives the voltage controlled current source <NUM> based on a result of the amplification to generate the current proportional to the current flowing through the power converter <NUM>. In at least some examples, this current is provided to another circuit or component for monitoring of the power converter <NUM> and/or control of the power converter <NUM>. For example, the current sense circuit <NUM> provides the current to the feedback circuit <NUM> for creation of VFB and comparison to VREF and/or to the processing element <NUM> for use by the processing element <NUM>.

Based on the control signal received from the feedback circuit <NUM>, the gate driver <NUM> generates one or more gate control signals for controlling power transistors of the power converter <NUM>, as discussed above. For example, the gate driver <NUM> generates gate control signals that alternatingly, and selectively, turn the power transistors of the power converter on and off to energize and de-energize elements such as an inductor and/or a capacitor. This energizing and deenergizing provides the buck, boost, and/or buck-boost functionality discussed herein. The gate driver <NUM> is implemented according to any suitable architecture, the scope of which is not limited herein.

Turning now to <FIG> and <FIG>, schematic diagrams of an illustrative current sense circuit <NUM> are shown. In at least some examples, the circuit <NUM> is suitable for implementation as the current sense circuit <NUM> of the SMPS <NUM> of <FIG>. Accordingly, reference is made to at least some components of <FIG> in describing <FIG> and <FIG>. The circuit <NUM>, in some examples, is suitable for monitoring IINAVE and ILAVE (non-simultaneously) in buck power converter topology, an inverting buck power converter topology, and/or a buck-boost power converter topology.

In an example architecture, the circuit <NUM> includes a switch <NUM>, a switch <NUM>, a resistor <NUM>, a capacitor <NUM>, a replica FET <NUM>, an amplifier <NUM>, a capacitor <NUM>, voltage controlled current source <NUM>, and a voltage controlled current source <NUM>. The switch <NUM> is coupled between a node <NUM> and a node <NUM>. The switch <NUM> is coupled between a node <NUM> and the node <NUM>. The resistor <NUM> is coupled between the node <NUM> and a node <NUM>. The capacitor <NUM> is coupled between the node <NUM> and the node <NUM>. The replica FET <NUM> has a drain terminal coupled to the node <NUM>, a source terminal coupled to a node <NUM>, and a gate terminal. The amplifier <NUM> has a first input terminal (e.g., a non-inverting input terminal) coupled to the node <NUM>, a second input terminal (e.g., an inverting input terminal) coupled to the node <NUM>, and an output terminal coupled to a node <NUM>. In at least some examples, the capacitor <NUM> is coupled between the node <NUM> and a ground node <NUM>. The voltage controlled current source <NUM> has a first terminal coupled to the node <NUM>, a second terminal coupled to the ground node <NUM>, and a control terminal coupled to the node <NUM>. The voltage controlled current source <NUM> has a first terminal coupled to a node <NUM>, a second terminal coupled to the ground node <NUM>, and a control terminal coupled to the node <NUM>. In at least some examples, a current mirror (not shown) is coupled between the node <NUM> and a node at which the circuit <NUM> outputs a signal representative of the current flowing through the power converter <NUM>. In some examples, the current mirror is coupled between the node <NUM> and the node <NUM> of <FIG> to provide the signal representative of the current flowing through the power converter <NUM> at the node <NUM>. In other examples, the signal representative of the current flowing through the power converter <NUM> is provided directly at the node <NUM>, for example, such that the node <NUM> and the node <NUM> may be regarded as being the same node.

In at least some examples, the circuit <NUM> is implemented on a same die as at least some transistors that will be monitored by the circuit <NUM>. For example, the circuit <NUM> may be implemented on a same die as at least some components of the power converter <NUM>. In such examples, the circuit <NUM> further includes, or is configured to couple to, a FET <NUM> and a FET <NUM>. The FET <NUM> has a drain terminal coupled to the node <NUM>, a source terminal coupled to the node <NUM>, and a gate terminal. The FET <NUM> has a drain terminal coupled to the node <NUM>, a source terminal, and a gate terminal. A node to which the source terminal of the FET <NUM> couples, or is configured to couple, may depend on a particular topology and/or desired operation of the power converter <NUM>. For example, a node to which the source terminal of the FET <NUM> couples may be determined based on the FET <NUM> being of p-type or n-type. Additionally, in at least some examples the switch <NUM> is configured to receive and be controlled by a same high-side control signal (HSon) as is received at the gate terminal of the FET <NUM>. The switch <NUM> is configured to receive and be controlled by a same low-side control signal (LSon) as is received at the gate terminal of the FET <NUM>. The replica FET <NUM> is configured to receive and be controlled by a control signal HSRon. When HSon is asserted, the switch <NUM> is closed. Otherwise, the switch <NUM> is open. When LSon is asserted, the switch <NUM> is closed. Otherwise, the switch <NUM> is open. In at least some examples, HSon and LSon are logical inversions of each other.

In an example of operation, the circuit <NUM> monitors a current across the FET <NUM> to output a signal at the node <NUM> having a current proportional to the current across the FET <NUM> (e.g., a current flowing through the power converter <NUM>). In at least some examples, the current flowing across the FET <NUM> is ILAVE. For example, when the FET <NUM> is turned on (e.g., conducting between its drain and source terminals) and the FET <NUM> is turned off (e.g., not conducting between its drain and source terminals), the circuit <NUM> is in a sensing phase. While in the sensing phase, the FET <NUM> is controlled to be turned on, the replica FET <NUM> is controlled to be turned on, the switch <NUM> is controlled to be closed, and the switch <NUM> is controlled to be open. As shown in <FIG>, this configuration forms three signal paths in the circuit <NUM> during the sensing phase. A first path <NUM> is formed from the node <NUM> to the node <NUM>, passing through the FET <NUM>. A second path <NUM> is formed from the node <NUM> to the node <NUM> through the replica FET <NUM>, continuing on through the voltage controlled current source <NUM>. A third path <NUM> is formed from the node <NUM> to the node <NUM> through the capacitor <NUM>, the resistor <NUM>, and the switch <NUM>.

In at least some examples, the node <NUM> is a switch node of the power converter <NUM> to which, in some examples, an inductor (not shown) couples. During the sensing phase, current flowing into the node <NUM> through the first path <NUM> and the second path <NUM> flows to a device coupled to the node <NUM> (e.g., such that an inductor coupled to the node <NUM> is charged during the first phase). Further during the sensing phase, the capacitor <NUM> is charged.

In another example of operation, the circuit <NUM> monitors a current across the FET <NUM> to output a signal at the node <NUM> having a current proportional to the current flowing through the node <NUM>. In at least some examples, such as when the node <NUM> is coupled to a terminal of an inductor, the current flowing through the node <NUM> is IINAVE. When the FET <NUM> is turned off and the FET <NUM> is turned on, the circuit <NUM> is in an averaging phase. While in the averaging phase, the FET <NUM> is controlled to be turned off, the FET <NUM> is controlled to be turned on, the replica FET <NUM> is controlled to be turned on, the switch <NUM> is controlled to be open, and the switch <NUM> is controlled to be closed. As show in <FIG>, this configuration forms up to three signal paths in the circuit <NUM> during the averaging phase. A first path <NUM> is formed from the node <NUM> to the node <NUM> through the replica FET <NUM>, continuing on through the voltage controlled current source <NUM>. A second path <NUM> is formed from the node <NUM> back to the node <NUM> through the switch <NUM>, the resistor <NUM>, and the capacitor <NUM>. A third path <NUM>, in some examples, is formed between the node <NUM> and the source terminal of the FET <NUM>, where the source terminal of the FET <NUM> may couple to various components or nodes according to a topology of the power converter <NUM>. During the averaging phase, the capacitor <NUM> discharges to the node <NUM> and the resistor <NUM> and the capacitor <NUM> together form a low-pass filter having an output at the node <NUM>. Accordingly, during the averaging phase, a signal present at the node <NUM> represents a low-pass filtering of a signal present at the node <NUM>.

In each phase, both sensing and averaging, the amplifier <NUM> amplifies a difference between a value of a signal present at the node <NUM> and a value of a signal present at the node <NUM>. This difference is amplified by the amplifier <NUM> according to a gain of the amplifier <NUM> and is output as a current signal. Accordingly, in at least some examples the amplifier <NUM> is a transconductance amplifier. The current signal output by the amplifier <NUM> charges the capacitor <NUM> to cause a voltage present at the node <NUM> to increase with time. The voltage present at the node <NUM>, in at least some examples, controls the voltage controlled current source <NUM> and the voltage controlled current source <NUM>. For example, as the voltage present at the node <NUM> increases, the current generated by the voltage controlled current source <NUM> and the voltage controlled current source <NUM> also increases. In at least some examples, the current of the voltage controlled current source <NUM>, generated based on control of the voltage present at the node <NUM>, is sunk from the node <NUM> through the replica FET <NUM>. Because the voltage present at the node <NUM> also controls the voltage controlled current source <NUM>, a current sunk by the voltage controlled current source <NUM> from the node <NUM> is approximately equal to a current flowing through the node <NUM>.

Based on the above actions of the sensing phase, the switch <NUM> samples a voltage across the FET <NUM>, where the sampled voltage is present at the node <NUM>. The resistor <NUM> and the capacitor <NUM> filter the sampled voltage to generate a filtered signal present at the node <NUM>. The filtered signal present at the node <NUM>, in at least some examples, is an average of the signal present at the node <NUM>. The amplifier <NUM>, the capacitor <NUM>, and the voltage controlled current source <NUM> together form a negative feedback loop. The negative feedback loop controls an amount of current sunk from the node <NUM> by the voltage controlled current source <NUM> to force a potential present at the node <NUM> to approximately equal a potential of the filtered signal present at the node <NUM>. An average voltage difference of node <NUM> minus node <NUM>, which is approximately equal to the average voltage difference of node <NUM> minus node <NUM>, is forced across the replica FET <NUM> by the negative feedback loop. Because there is no direct current (DC) flowing through the inputs of the amplifier <NUM> and no DC flowing through into capacitor <NUM>, there is no DC flowing through the resistor <NUM>. Because no DC flows through the resistor <NUM>, there is no DC voltage drop across the resistor <NUM>. Further, because the replica FET <NUM> is a scaled replica of the FET <NUM> (e.g., N times smaller than the FET <NUM>), a current flowing through the replica FET <NUM> is approximately equal to a current conducted by the voltage controlled current source <NUM>. The current conducted by the voltage controlled current source <NUM> is in turn approximately equal to a result of an average current flowing through the FET <NUM> divided by N. Thus, the current conducted by the voltage controlled current source <NUM> is approximately equal to II,AVE divided by N. Because the voltage controlled current source <NUM> and the voltage controlled current source are controlled according to the same voltage present at the node <NUM>, a current sunk from the node <NUM> is also approximately equal to ILAVE divided by N. Additionally, at least some of the above signals present in the circuit <NUM> while operating in the sensing phase are illustrated in <FIG>, which is a diagram of illustrative signal waveforms.

Further, based on the above actions of the averaging phase, the switch <NUM> samples a voltage present at the node <NUM>. As in the sensing phase, the resistor <NUM> and the capacitor <NUM> filter the sampled voltage present at the node <NUM> to generate a filtered signal present at the node <NUM>. Again, the filtered signal present at the node <NUM> is, in some examples, an average of the sampled voltage present at the node <NUM>. The negative feedback loop controls the amount of current sunk from the node <NUM> by the voltage controlled current source <NUM> to force a potential present at the node <NUM> to approximately equal a potential of the filtered signal present at the node <NUM>. Because a current flowing through the replica FET <NUM> is approximately the same as a current flowing through the node <NUM> (and therefore node <NUM>), the current flowing through the node <NUM> is approximately equal to a current conducted by the voltage controlled current source <NUM>. The current conducted by the voltage controlled current source <NUM> is in turn approximately equal to IINAVE. Because the voltage controlled current source <NUM> and the voltage controlled current source are controlled according to the same voltage present at the node <NUM>, a current sunk from the node <NUM> is also approximately equal to IINAVE. Additionally, at least some of the above signals present in the circuit <NUM> while operating in the averaging phase are illustrated in <FIG>, which is a diagram of illustrative signal waveforms.

In at least some examples, IINAVE, as sunk by the circuit <NUM> from the node <NUM>, is approximately equal to D*ILAVE_TON, where D is a duty cycle of the FET <NUM> and ILAVE_TON is ILAVE during an on time of the FET <NUM>. An average voltage across the capacitor <NUM> is approximately equal to a difference in voltage present at the node <NUM> and at the node <NUM>, which approximately equals IINAVE multiplied by a drain to source resistance of the FET <NUM>. When the circuit <NUM> is operating in a discontinuous conduction mode, ILAVE is approximately equal to ILA VE_TON*(TON+TOFF)/T, where ILAVE_TON and TON are as defined above, TOFF is the off time of the FET <NUM>, and T is a switching period of the FET <NUM>. When the circuit <NUM> is operating in a continuous conduction mode, ILAVE is approximately equal to ILAVE_TON, as defined above.

Turning now to <FIG>, <FIG>, and <FIG>, schematic diagrams of an illustrative current sense circuit <NUM> are shown. In at least some examples, the circuit <NUM> is suitable for implementation as the current sense circuit <NUM> of the SMPS <NUM> of <FIG>. Accordingly, reference is made to at least some components of <FIG> in describing <FIG>. The circuit <NUM>, in some examples, is suitable for monitoring IINAVE and ILAVE (non-simultaneously) in buck power converter topology, an inverting buck power converter topology, and/or a buck-boost power converter topology.

In an example architecture, the circuit <NUM> includes a switch <NUM>, a switch <NUM>, a switch <NUM>, a resistor <NUM>, a capacitor <NUM>, a replica FET <NUM>, an amplifier <NUM>, a capacitor <NUM>, voltage controlled current source <NUM>, and a voltage controlled current source <NUM>. The switch <NUM> is coupled between a node <NUM> and a node <NUM>. The switch <NUM> is coupled between a node <NUM> and the node <NUM>. The switch <NUM> is coupled between the node <NUM> and a node <NUM>. The resistor <NUM> is coupled between the node <NUM> and a node <NUM>. The capacitor <NUM> is coupled between the node <NUM> and the node <NUM>. The replica FET <NUM> has a drain terminal coupled to the node <NUM>, a source terminal coupled to the node <NUM>, and a gate terminal. The amplifier <NUM> has a first input terminal (e.g., a non-inverting input terminal) coupled to the node <NUM>, a second input terminal (e.g., an inverting input terminal) coupled to the node <NUM>, and an output terminal coupled to a node <NUM>. In at least some examples, the capacitor <NUM> is coupled between the node <NUM> and a ground node <NUM>. The voltage controlled current source <NUM> has a first terminal coupled to the node <NUM>, a second terminal coupled to the ground node <NUM>, and a control terminal coupled to the node <NUM>. The voltage controlled current source <NUM> has a first terminal coupled to a node <NUM>, a second terminal coupled to the ground node <NUM>, and a control terminal coupled to the node <NUM>. In at least some examples, a current mirror (not shown) is coupled between the node <NUM> and a node at which the circuit <NUM> outputs a signal representative of the current flowing through the power converter <NUM>. In some examples, the current mirror is coupled between the node <NUM> and the node <NUM> of <FIG> to provide the signal representative of the current flowing through the power converter <NUM> at the node <NUM>. In other examples, the signal representative of the current flowing through the power converter <NUM> is provided directly at the node <NUM>, for example, such that the node <NUM> and the node <NUM> may be regarded as being the same node.

In at least some examples, the circuit <NUM> is implemented on a same die as at least some transistors that will be monitored by the circuit <NUM>. For example, the circuit <NUM> may be implemented on a same die as at least some components of the power converter <NUM>. In such examples, the circuit <NUM> further includes, or is configured to couple to, a FET <NUM> and a FET <NUM>. The FET <NUM> has a drain terminal coupled to the node <NUM>, a source terminal coupled to the node <NUM>, and a gate terminal. The FET <NUM> has a drain terminal coupled to the node <NUM>, a source terminal, and a gate terminal. A point to which the source terminal of the FET <NUM> couples, or is configured to couple, may depend on a particular topology and/or desired operation of the power converter <NUM>. Additionally, in at least some examples the switch <NUM> is configured to receive and be controlled by a sense phase control signal (SNS) and the switch <NUM> is configured to receive and be controlled by an average phase control signal (AVE). Further, the switch <NUM> is configured to receive and be controlled by a hold phase control signal (HOLD). The FET <NUM> is configured to receive, at its gate terminal, and be controlled by HSon. The FET <NUM> is configured to receive, at its gate terminal, and be controlled by LSon. The replica FET <NUM> is configured to receive, at its gate terminal, and be controlled by HSRon. When SNS is asserted, the switch <NUM> is closed. Otherwise, the switch <NUM> is open. When AVE is asserted, the switch <NUM> is closed. Otherwise, the switch <NUM> is open. When HOLD is asserted, the switch <NUM> is closed. Otherwise, the switch <NUM> is open. In at least some examples, only one of SNS, AVE, or HOLD is asserted at a given point in time.

In an example of operation, the circuit <NUM> monitors a current across the FET <NUM> to output a signal at the node <NUM> having a current proportional to the current across the FET <NUM> (e.g., a current flowing through the power converter <NUM>). For example, when the FET <NUM> is turned on (e.g., conducting between its drain and source terminals) and the FET <NUM> is turned off (e.g., not conducting between its drain and source terminals), the circuit <NUM> is in a sensing phase. While in the sensing phase, the FET <NUM> is controlled to be turned on, the replica FET <NUM> is controlled to be turned on, the switch <NUM> is controlled to be closed, the switch <NUM> is controlled to be open, and the switch <NUM> is controlled to be open. As shown in <FIG>, this configuration forms three signal paths in the circuit <NUM> during the sensing phase. A first path <NUM> is formed from the node <NUM> to the node <NUM>, passing through the FET <NUM>. A second path <NUM> is formed from the node <NUM> to the ground node <NUM> through the replica FET <NUM>, node <NUM> and voltage controlled current source <NUM>. A third path <NUM> is formed from the node <NUM> to the node <NUM> through the replica FET <NUM>, the capacitor <NUM>, the resistor <NUM>, and the switch <NUM>.

When the FET <NUM> is turned off and the FET <NUM> is turned on, the circuit <NUM> is in an averaging phase. While in the averaging phase, the FET <NUM> is controlled to be turned off, the FET <NUM> is controlled to be turned on, the replica FET <NUM> is controlled to be turned on, the switch <NUM> is controlled to be open, the switch <NUM> is controlled to be closed, and the switch <NUM> is controlled to be open. As shown in <FIG>, this configuration forms up to three signal paths in the circuit <NUM> during the averaging phase. A first path <NUM> is formed from the node <NUM> to the node <NUM> through the replica FET <NUM>. A second path is formed from the node <NUM> back to the node <NUM> through the switch <NUM>, the resistor <NUM>, and the capacitor <NUM>. A third path <NUM>, in some examples, is formed between the node <NUM> and the source terminal of the FET <NUM>, where the source terminal of the FET <NUM> may couple to various components or nodes according to a topology of the power converter <NUM>. During the averaging phase, the capacitor <NUM> discharges to the node <NUM> and the resistor <NUM> and the capacitor <NUM> together form a filter having an output at the node <NUM>. Accordingly, during the averaging phase, a signal present at the node <NUM> is a low-pass filtering of a signal present at the node <NUM>.

When the FET <NUM> and the FET <NUM> are both turned off, the circuit <NUM> is a holding phase. While in the holding phase, the FET <NUM> is controlled to be turned off, the FET <NUM> is controlled to be turned off, the replica FET <NUM> is controlled to be turned on, the switch <NUM> is controlled to be open, the switch <NUM> is controlled to be open, and the switch <NUM> is controlled to be closed. As shown in <FIG>, this configuration forms two signal paths in the circuit <NUM> during the holding phase. A first path <NUM> is formed from the node <NUM> to the node <NUM> through the replica FET <NUM> and the voltage controlled current source <NUM>. A second path <NUM> is formed in a loop from the node <NUM> through the switch <NUM>, the resistor <NUM>, and the capacitor <NUM> back to the node <NUM>.

In each phase, sensing, averaging, and holding, the amplifier <NUM> amplifies a difference between a value of a signal present at the node <NUM> and a value of a signal present at the node <NUM>. The capacitor <NUM>, in at least some examples, is a coupling capacitor between the node <NUM> and the node <NUM> that improves common-mode response in the circuit <NUM>. The capacitor <NUM> improves the common mode response of the circuit <NUM> by making noise present at the node <NUM> and the node <NUM> appear as a common-mode signal from a perspective of the amplifier <NUM>. Making noise present at the node <NUM> and the node <NUM> appear as a common-mode signal to the amplifier <NUM>, in at least some examples, mitigates an effect of the noise on an output signal of the amplifier <NUM>. This difference between the value of the signal present at the node <NUM> and the value of a signal present at the node <NUM> is amplified by the amplifier <NUM> according to a gain of the amplifier <NUM> and is output as a current signal. Accordingly, in at least some examples the amplifier <NUM> is a transconductance amplifier. The current signal output by the amplifier <NUM> charges the capacitor <NUM> to cause a voltage present at the node <NUM> to increase with time. The voltage present at the node <NUM>, in at least some examples, controls the voltage controlled current source <NUM> and the voltage controlled current source <NUM>. For example, as the voltage present at the node <NUM> increases, the current generated by the voltage controlled current source <NUM> and the voltage controlled current source <NUM> also increases. In at least some examples, the current of the voltage controlled current source <NUM>, generated based on control of the voltage present at the node <NUM>, is sunk from the node <NUM> through the replica FET <NUM>. Because the voltage present at the node <NUM> also controls the voltage controlled current source <NUM>, a current sunk by the voltage controlled current source <NUM> from the node <NUM> is approximately equal to a current flowing through the node <NUM>.

Operation of the circuit <NUM> in the averaging phase and the sensing phase, in at least some examples, follows a same general principle of operation of the circuit <NUM> in the averaging and sensing phases, respectively, with some exceptions. For example, as discussed above, in the circuit <NUM> the capacitor <NUM> is coupled between the first input terminal and the second input terminal of the amplifier <NUM>. By coupling the capacitor <NUM> between the input terminals of the amplifier <NUM>, noise rejection at the input terminals of the amplifier <NUM> is improved. For example, alternating current disturbance or noise present at the node <NUM> and/or the node <NUM> is made common for both inputs of the amplifier <NUM>, thus negating an impact of that alternating current disturbance or noise in an output of the amplifier <NUM> at the node <NUM>. Additionally, a direct current operating voltage of the capacitor <NUM> is approximately zero, which increases a speed of the circuit <NUM> settling to an operation point when compared to other circuits that lack the capacitor <NUM> coupled as in the circuit <NUM>. Furthermore, some circumstances may exist in the circuit <NUM> in which neither AVE nor SNS is asserted. Under such circumstances, the node <NUM> may be floating or otherwise have an unknown potential, which may result in undesirable operation of the circuit <NUM>. To maintain a defined potential at the node <NUM>, the switch <NUM>, when neither AVE nor SNS is asserted HOLD is asserted. When HOLD is asserted, the switch <NUM> couples the node <NUM> to the node <NUM>, providing a known potential at the node <NUM>. Additionally, at least some of the above signals present in the circuit <NUM> while operating in the sensing phase are illustrated in <FIG>, which is a diagram of illustrative signal waveforms. Furthermore, at least some of the above signals present in the circuit <NUM> while operating in the averaging phase are illustrated in <FIG>, which is a diagram of illustrative signal waveforms.

In at least some examples, IINAVE, as sunk by the circuit <NUM> from the node <NUM>, is approximately equal to D*ILAVE_TON, where D and ILAVE_TON are each as described above with respect to the circuit <NUM> of <FIG>. An average voltage across the capacitor <NUM> is approximately equal to zero. This results from a comparatively high gain of the amplifier <NUM>, which forces a differential input of the amplifier <NUM>, across which the capacitor <NUM> is coupled, to approximately equal zero. When the circuit <NUM> is operating in a discontinuous conduction mode, ILAVE is approximately equal to ILAVE_TON*(TON+TOFF)/T, where ILAVE TON, TOFF, and T are as described above with respect to the circuit <NUM>. When the circuit <NUM> is operating in a continuous conduction mode, ILAVE is approximately equal to ILAVE TON, as defined above with respect to the circuit <NUM>.

Turning now to <FIG> and <FIG>, schematic diagrams of an illustrative current sense circuit <NUM> are shown. In at least some examples, the circuit <NUM> is suitable for implementation as the current sense circuit <NUM> of the SMPS <NUM> of <FIG>. Accordingly, reference is made to at least some components of <FIG> in describing <FIG>. The circuit <NUM>, in some examples, is suitable for monitoring IINAVE and ILAVE (non-simultaneously) in boost power converter topology.

In an example architecture, the circuit <NUM> includes a switch <NUM>, a switch <NUM>, a switch <NUM>, a resistor <NUM>, a capacitor <NUM>, a replica FET <NUM>, an amplifier <NUM>, a capacitor <NUM>, voltage controlled current source <NUM>, and a voltage controlled current source <NUM>. The switch <NUM> is coupled between a node <NUM> and a node <NUM>. The switch <NUM> is coupled between the node <NUM> and the node <NUM>. The switch <NUM> is coupled between the node <NUM> and the node <NUM>. The resistor <NUM> is coupled between the node <NUM> and a node <NUM>. The capacitor <NUM> is coupled between the node <NUM> and the node <NUM>. The replica FET <NUM> has a drain terminal coupled to the node <NUM>, a source terminal coupled to the node <NUM>, and a gate terminal coupled to a node <NUM>. The amplifier <NUM> has a first input terminal (e.g., a non-inverting input terminal) coupled to the node <NUM>, a second input terminal (e.g., an inverting input terminal) coupled to the node <NUM>, and an output terminal coupled to a node <NUM>. In at least some examples, the capacitor <NUM> is coupled between the node <NUM> and a ground node <NUM>. The voltage controlled current source <NUM> has a first terminal coupled to the node <NUM>, a second terminal coupled to the ground node <NUM>, and a control terminal coupled to the node <NUM>. The voltage controlled current source <NUM> has a first terminal coupled to a node <NUM>, a second terminal coupled to the ground node <NUM>, and a control terminal coupled to the node <NUM>. In at least some examples, a current mirror (not shown) is coupled between the node <NUM> and a node at which the circuit <NUM> outputs a signal representative of the current flowing through the power converter <NUM>. In some examples, the current mirror is coupled between the node <NUM> and the node <NUM> of <FIG> to provide the signal representative of the current flowing through the power converter <NUM> at the node <NUM>. In other examples, the signal representative of the current flowing through the power converter <NUM> is provided directly at the node <NUM>, for example, such that the node <NUM> and the node <NUM> may be regarded as being the same node.

In at least some examples, the circuit <NUM> is implemented on a same die as at least some transistors that will be monitored by the circuit <NUM>. For example, the circuit <NUM> may be implemented on a same die as at least some components of the power converter <NUM>. In such examples, the circuit <NUM> further includes, or is configured to couple to, a FET <NUM> and a FET <NUM>. The FET <NUM> has a drain terminal coupled to the node <NUM>, a source terminal coupled to the node <NUM>, and a gate terminal coupled to the node <NUM>. The FET <NUM> has a drain terminal coupled to the node <NUM>, a source terminal coupled to the ground node <NUM>, and a gate terminal. In at least some examples, the switch <NUM> is replaced by, or implemented as, a second replica FET (not shown). In such examples, the circuit <NUM> may have added functionality of outputting a signal at the node <NUM> that is representative of an output current (e.g., current at the node <NUM>) of the circuit <NUM>. Additionally, in at least some examples the switch <NUM> is configured to receive and be controlled by an inversion of a high-side control signal (HSoff). The switch <NUM> is configured to receive and be controlled by SNS. Further, the switch <NUM> is configured to receive and be controlled by HOLD. The replica FET <NUM> and the FET <NUM> are configured to receive, at their gate terminals, and be controlled by HSon. The FET <NUM> is configured to receive, at its gate terminal, and be controlled by LSon. When HSoff is asserted, the switch <NUM> is closed. Otherwise, the switch <NUM> is open. When SNS is asserted, the switch <NUM> is closed. Otherwise, the switch <NUM> is open. When HOLD is asserted, the switch <NUM> is closed. Otherwise, the switch <NUM> is open.

In an example of operation, the circuit <NUM> monitors a current across the FET <NUM> to output a signal at the node <NUM> having a current proportional to the current across the FET <NUM> (e.g., a current flowing through the power converter <NUM>). For example, when the FET <NUM> is turned on (e.g., conducting between its drain and source terminals) and the FET <NUM> is turned off (e.g., not conducting between its drain and source terminals), the circuit <NUM> is in a sensing phase. While in the sensing phase, the FET <NUM> is controlled to be turned on, the replica FET <NUM> is controlled to be turned on, the switch <NUM> is controlled to be closed, the switch <NUM> is controlled to be open, and the switch <NUM> is controlled to be open. As shown in <FIG>, this configuration forms three signal paths in the circuit <NUM> during the sensing phase. A first path <NUM> is formed from the node <NUM> to the node <NUM>, passing through the FET <NUM>. A second path <NUM> is formed from the node <NUM> to the ground node <NUM> through the replica FET <NUM> and the voltage controlled current source <NUM>. A third path <NUM> is formed from the node <NUM> to the node <NUM> through the replica FET <NUM>, the switch <NUM>, the resistor <NUM>, and the capacitor <NUM>. During the sensing phase, the resistor <NUM> and the capacitor <NUM> together form a filter having an output at the node <NUM>. Accordingly, during the sensing phase, a signal present at the node <NUM> is a low-pass filtering of a signal present at the node <NUM>. In at least some examples, the node <NUM> is a switch node of the power converter <NUM> to which, in some examples, an inductor (not shown) couples.

When the FET <NUM> is turned off and the FET <NUM> is turned on, the circuit <NUM> is in a holding phase. While in the holding phase, the FET <NUM> is controlled to be turned off, the FET <NUM> is controlled to be turned on, the replica FET <NUM> is controlled to be turned off, the switch <NUM> is controlled to be open, the switch <NUM> is controlled to be closed, and the switch <NUM> is controlled to be closed. As shown in <FIG>, this configuration forms up to three signal paths in the circuit <NUM> during the holding phase. A first path <NUM> is formed from the node <NUM> to the ground node <NUM> through the switch <NUM> and the voltage controlled current source <NUM>. A second path <NUM> is formed from the node <NUM> back to the node <NUM> through the switch <NUM>, the resistor <NUM>, and the capacitor <NUM>. A third path <NUM>, in some examples, is formed between the node <NUM> and the ground node <NUM> through the FET <NUM>.

In each phase, both sensing and holding, the amplifier <NUM> amplifies a difference between a value of a signal present at the node <NUM> and a value of a signal present at the node <NUM>. This difference is amplified by the amplifier <NUM> according to a gain of the amplifier <NUM> and is output as a current signal. Accordingly, in at least some examples the amplifier <NUM> is a transconductance amplifier. The current signal output by the amplifier <NUM> charges the capacitor <NUM> to cause a voltage present at the node <NUM> to increase with time. The voltage present at the node <NUM>, in at least some examples, controls the voltage controlled current source <NUM> and the voltage controlled current source <NUM>. For example, as the voltage present at the node <NUM> increases, the current generated by the voltage controlled current source <NUM> and the voltage controlled current source <NUM> also increases. In at least some examples, the current of the voltage controlled current source <NUM>, generated based on control of the voltage present at the node <NUM>, is sunk from the node <NUM> through the replica FET <NUM>. Because the voltage present at the node <NUM> also controls the voltage controlled current source <NUM>, a current sunk by the voltage controlled current source <NUM> from the node <NUM> is approximately equal to a current flowing through the node <NUM>.

Based on the above actions of the sensing phase, the switch <NUM> samples a voltage across the replica FET <NUM>, where the sampled voltage is present at the node <NUM>. The resistor <NUM> and the capacitor <NUM> filter the sampled voltage to generate a filtered signal present at the node <NUM>. The filtered signal present at the node <NUM>, in at least some examples, is an average of the sampled voltage present at the node <NUM>. The amplifier <NUM>, the capacitor <NUM>, and the voltage controlled current source <NUM> together form a negative feedback loop. The negative feedback loop controls an amount of current sunk from the node <NUM> by the voltage controlled current source <NUM> to force a potential present at the node <NUM> to approximately equal a potential of the filtered signal present at the node <NUM>. This causes an average voltage drop across each of the FET <NUM> and the replica FET <NUM> to be approximately equal to ILAVE multiplied by a drain-to-source resistance of the FET <NUM> when the FET <NUM> is conductive. Because the replica FET <NUM> is a scaled replica of the FET <NUM> (e.g., N times smaller than the FET <NUM>), a current flowing through the replica FET <NUM> is approximately equal to a current conducted by the voltage controlled current source <NUM>. The current conducted by the voltage controlled current source <NUM> is in turn approximately equal to a result of an average current flowing through the FET <NUM> divided by N. Thus, the current conducted by the voltage controlled current source <NUM> is approximately equal to ILAVE divided by N. Because the voltage controlled current source <NUM> and the voltage controlled current source are controlled according to the same voltage present at the node <NUM>, a current sunk from the node <NUM> is also approximately equal to ILAVE divided by N. Additionally, in at least some examples of the circuit <NUM> ILAVE is approximately equal to IINAVE. Accordingly, in at least some examples the current sunk from the node <NUM> is approximately equal to ILAVE divided by N. Additionally, in at least some examples the node <NUM> may be floating or otherwise have an unknown potential when SNS is de-asserted, which may result in undesirable operation of the circuit <NUM>. To maintain a defined potential at the node <NUM>, HOLD is asserted when SNS is de-asserted. When HOLD is asserted, the switch <NUM> couples the node <NUM> to the node <NUM>, providing a known potential at the node <NUM>. Additionally, at least some of the above signals present in the circuit <NUM> while operating in the sensing phase are illustrated in <FIG>, which is a diagram of illustrative signal waveforms.

In at least some examples, IINAVE, as sunk by the circuit <NUM> from the node <NUM>, is approximately equal to ILAVE which is approximately equal to ILAVE_TON, where ILAVE and ILAVE TON are each as described above with respect to the circuit <NUM> of <FIG>. An average voltage across the capacitor <NUM> is approximately equal to zero. This results from a comparatively high gain of the amplifier <NUM>, which forces a differential input of the amplifier <NUM>, across which the capacitor <NUM> is coupled, to approximately equal zero. An average voltage between the node <NUM> and the node <NUM> is approximately equal IINAVE multiplied by a drain to source resistance of the FET <NUM>, which approximately equals ILAVE multiplied by the drain to source resistance of the FET <NUM>.

In the foregoing discussion, the terms "including" and "comprising" are used in an openended fashion, and thus should be interpreted to mean "including, but not limited to. " The term "couple" is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A. A device that is "configured to" perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. Furthermore, a circuit or device that is said to include certain components may instead be configured to couple to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be configured to couple to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.

While certain components are described herein as being of a particular process technology (e.g., FET, MOSFET, n-type, p-type, etc.), these components may be exchanged for components of other process technologies (e.g., replace FET and/or MOSFET with bi-polar junction transistor (BJT), replace n-type with p-type or vice versa, etc.) and reconfiguring circuits including the replaced components to provide desired functionality at least partially similar to functionality available prior to the component replacement. Components illustrated as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the illustrated resistor. Additionally, uses of the phrase "ground voltage potential" in the foregoing discussion are intended to include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of the present disclosure. Unless otherwise stated, "about", "approximately", or "substantially" preceding a value means +/- <NUM> percent of the stated value.

Claim 1:
A current sense circuit adapted to be coupled between a first current terminal of a high-side transistor (<NUM>) of a converter and a second current terminal of the high-side transistor (<NUM>), the circuit comprising:
a first switch (<NUM>) coupled between a first node and a second node, the first node adapted to be coupled to the second current terminal of the high-side transistor (<NUM>);
a second switch (<NUM>) coupled between a third node and the second node, the third node adapted to be coupled to the first current terminal of the high-side transistor (<NUM>);
a resistor (<NUM>) coupled between the second node and a fourth node;
a capacitor (<NUM>) comprising a first terminal coupled to the fourth node and a second terminal coupled to the third node;
a transistor (<NUM>) comprising a drain terminal coupled to the third node, a source terminal coupled to a fifth node, and a gate terminal; and
an amplifier (<NUM>) comprising a first input terminal coupled to the fifth node, a second input terminal coupled to the fourth node, and an output terminal coupled to a sixth node;
a second capacitor (<NUM>) coupled between the sixth node and a ground node;
a first voltage controlled current source (<NUM>) coupled between the fifth node and the ground node and controlled by a signal present at the sixth node; and
a second voltage controlled current source (<NUM>) coupled between a seventh node and the ground node and controlled by the signal present at the sixth node.