Patent Description:
The present disclosure relates to a power supply system and a power supply apparatus.

An example of a known power supply apparatus used in a redundant power supply reduces the output voltage as the current outputted to the load increases. For example, see patent literature (PTL) <NUM>.

When a redundant power supply is configured by the power supply apparatus disclosed in PTL <NUM>, the outputs of two power supply apparatuses are directly combined. If one of the power supply apparatuses suffers a short-circuit failure, the voltage supplied to the load might lower.

In light of this point, it would be helpful to provide a power supply system and a power supply apparatus that are highly reliable.

It is an object of the present invention to provide a power supply apparatus and a power supply system that obviate or mitigate at least one of the disadvantages and shortcomings of the related prior art.

This object is solved by the present invention as claimed in the appended claims <NUM> and <NUM>. Particular embodiments of the present invention are defined by the appended dependent claims.

A power supply system according to the present invention includes at least two power supply apparatuses that supply current to one load. Each power supply apparatus includes a converter that supplies current to the load, a FET connected in series between the converter and the load, a current detector including a current detection unit configured to detect current flowing between the converter and the load, a droop characteristic controller configured to cause output voltage of the converter to droop at a droop rate determined based on the magnitude of load current flowing from the converter towards the load, and a reverse current limitation unit configured to limit a reverse current flowing from the load towards the converter to be a reverse current limit or less by controlling a voltage between a gate and source of the FET. The FET is configured to control the current outputted from the converter based on a signal outputted by the current detector. The droop rate when the load current is included in a first current section is greater than the droop rate when the load current is included in each of a second current section and a third current section. The second current section includes current that is smaller than current included in the first current section. The third current section includes current that is larger than the current included in the first current section. The load current is easier to balance when the droop rate is thus increased in a predetermined current section. Consequently, the reliability of the power supply system increases.

In a power supply system according to an embodiment, each power supply apparatus may further include a reverse current limitation unit that limits, based on a reverse current reference limit, a reverse current flowing from the load towards the converter. If one power supply apparatus suffers a short-circuit failure, this configuration reduces the probability of chain-reaction suspension of other operating power supply apparatuses. Consequently, the reliability of the power supply system increases.

In a power supply system according to an embodiment, the reverse current limitation unit may include a separation unit that inputs, to a gate of the FET, a signal based on the result of comparing the reverse current as detected by the current detection unit with the reverse current reference limit. The reverse current is limited by this configuration to be within a predetermined value. Consequently, the reliability of the power supply system increases.

In a power supply system according to an embodiment, the reverse current limitation unit may include a voltage monitor that inputs, to the gate of the FET, a signal based on the result of comparing the potential of the drain of the FET with the sum of the potential of the source of the FET and a monitoring offset voltage. The FET is cut off in this configuration when the reverse current exceeds a predetermined value. Consequently, the loss at the FET due to reverse current becomes nearly zero.

In a power supply system according to an embodiment, the converter may have a rated current. The rated current may be set to a larger value than the sum of the maximum load current and the reverse current reference limit. If reverse current flows in one power supply apparatus, this configuration reduces the probability of chain-reaction suspension of other operating power supply apparatuses. Consequently, the reliability of the power supply system increases.

In a power supply system according to an embodiment, a resistance element may be connected in series in at least one of paths short-circuiting between a current path from the converter towards the load and a ground point. This configuration limits short-circuit current flowing due to a short-circuit failure inside the power supply apparatus. Consequently, the reliability of the power supply system increases.

In a power supply system according to an embodiment, the first current section may include a current that is <NUM>% of the maximum load current. This configuration balances the current outputted by each power supply apparatus when two power supply apparatuses are connected to the load. Balanced current reduces the difference in the amount of heat generated inside each power supply apparatus. The difference in lifespan of components in each power supply apparatus thereby reduces, increasing the reliability of the power supply system.

In a power supply system according to an embodiment, the droop rate when the load current is included in a fourth current section may be greater than the droop rate when the load current is included in each of a fifth current section and the third current section, the fourth current section may include current that is larger than current included in the third current section, the fifth current section may include current that is larger than current included in the fourth current section, the first current section may include current represented by the product of the maximum load current and the inverse of a first predetermined number, and the fourth current section may include current represented by the product of the maximum load current and the inverse of a second predetermined number yielded by subtracting one from the first predetermined number. The currents outputted by operating power supply apparatuses are easier to balance with this configuration, both when all of the first predetermined number of power supply apparatuses connected to the load are operating and when one of the power supply apparatuses has failed. Consequently, the reliability of the power supply system increases.

A power supply apparatus according to the present invention includes a converter configured to supply current to a load, a FET connected in series between the converter and the load, a current detector including a current detection unit configured to detect current flowing between the converter and the load, a droop characteristic controller configured to cause output voltage of the converter to droop at a droop rate determined based on the magnitude of load current flowing from the converter towards the load, and a reverse current limitation unit configured to limit a reverse current flowing from the load towards the converter to be a reverse current limit or less by controlling a voltage between a gate and source of the FET. The FET is configured to control the current outputted from the converter based on a signal outputted by the current detector. The droop rate when the load current is included in a first current section is greater than the droop rate when the load current is included in each of a second current section and a third current section. The second current section includes current that is smaller than current included in the first current section. The third current section includes current that is larger than the current included in the first current section. The load current is easier to balance when the droop rate is thus increased in a predetermined current section. Consequently, the reliability of the power supply apparatus increases.

The present disclosure provides a power supply system and a power supply apparatus that are highly reliable.

Embodiments and/or examples mentioned in the following description that do not fall under the scope of the appended claims are to be construed as comparative examples useful for understanding the present invention.

Embodiments of the present disclosure are described while being compared to comparative examples.

As illustrated in <FIG>, a power supply system <NUM> according to a first comparative example includes a power supply apparatus <NUM> and a power supply apparatus <NUM>. The power supply apparatus <NUM> includes a converter <NUM>, a redundancy diode <NUM>, an output terminal <NUM>, and a ground terminal <NUM>. The power supply apparatus <NUM> includes a converter <NUM>, a redundancy diode <NUM>, an output terminal <NUM>, and a ground terminal <NUM>. Matter that is common to the power supply apparatuses <NUM>, <NUM> is described only with respect to the power supply apparatus <NUM>.

The power supply apparatuses <NUM>, <NUM> are connected to a load <NUM> in parallel. One terminal of the load <NUM> is connected to the output terminals <NUM>, <NUM>. The other terminal of the load <NUM> is connected to a ground point <NUM> and to the ground terminals <NUM>, <NUM>. The power supply system <NUM> supplies the load <NUM> with the current yielded by combining the current outputted by the power supply apparatus <NUM> from the output terminal <NUM> and the current outputted by the power supply apparatus <NUM> from the output terminal <NUM>. The current supplied to the load <NUM> may flow to the ground point <NUM> or may return to the power supply apparatuses <NUM>, <NUM> through the ground terminals <NUM>, <NUM>.

The redundancy diodes <NUM>, <NUM> are assumed to be Schottky barrier diodes with a small forward voltage drop. The power supply apparatuses <NUM>, <NUM> are connected to the load <NUM> in parallel via the redundancy diodes <NUM>, <NUM>. The redundancy diode <NUM> prevents current from flowing from the output terminal <NUM> towards the converter <NUM>. The redundancy diode <NUM> prevents current from flowing from the output terminal <NUM> towards the converter <NUM>.

The converter <NUM> controls voltage between the output terminal <NUM> and the ground terminal <NUM>. The converter <NUM> controls voltage between the output terminal <NUM> and the ground terminal <NUM>. By controlling the voltage of the output terminals <NUM> and <NUM>, the converters <NUM> and <NUM> can supply the current required by the load <NUM> while balancing the magnitude of the current provided by each of the power supply apparatuses <NUM>, <NUM> to the load <NUM>.

If one of the power supply apparatuses <NUM>, <NUM> stops due to failure or the like, then the other power supply apparatus supplies all of the current required by the load <NUM>. For example, when the power supply apparatus <NUM> stops, then the power supply apparatus <NUM> supplies all of the current required by the load <NUM>. Consequently, even if one of the power supply apparatuses <NUM>, <NUM> stops, the power supply system <NUM> overall can maintain the supply of power to the load <NUM>. In other words, the power supply system <NUM> is redundant. In this case, each of the power supply apparatuses <NUM>, <NUM> needs to be capable of supplying all of the current required by the load <NUM>.

When the power supply apparatus <NUM> is connected to the load <NUM> via the redundancy diode <NUM>, as in the power supply system <NUM>, then loss increases at the redundancy diode <NUM>. For example, when the forward voltage drop of the redundancy diode <NUM> is <NUM> volts (V), then a current of <NUM> amperes (A) provided to the load <NUM> generates a loss of up to <NUM> watts (W) at the redundancy diode <NUM>. The power supply apparatus <NUM> needs to include a heat dissipation member, such as a large heatsink, in this case. The heat dissipation member prevents the power supply apparatus <NUM> from being reduced in size. Furthermore, the heat generated at the redundancy diode <NUM> raises the temperature of electronic components such as an electrolytic capacitor, thereby shortening the lifespan of the electronic components. Consequently, the reliability of the power supply apparatus <NUM> decreases.

The power supply apparatus <NUM> controls the voltage of the stage prior to the redundancy diode <NUM>. In this case, the redundancy diode <NUM> is located outside of the feedback loop of the feedback control by the power supply apparatus <NUM>. The converter <NUM> therefore cannot compensate for the current-voltage characteristics or temperature characteristics of the redundancy diode <NUM>, nor for individual variation in these characteristics. The inability to compensate for the characteristics of the redundancy diode <NUM> increases the error of the voltage outputted by the power supply apparatus <NUM>. Consequently, it is difficult for the power supply apparatus <NUM> that includes the redundancy diode <NUM> to control the voltage. In other words, the voltage regulation characteristics of the power supply apparatus <NUM> that includes the redundancy diode <NUM> are poor.

The forward voltage drop of the redundancy diode <NUM> typically has negative temperature characteristics. For example, in a Schottky barrier diode with a forward voltage drop of approximately <NUM> V, the difference in the forward voltage drop between the low temperature environment and the high temperature environment might be approximately <NUM> V to <NUM> V. When the power supply apparatus <NUM> outputs a voltage of <NUM> V, for example, and the forward voltage drop changes by <NUM> V to <NUM> V due to the temperature characteristics, then this change causes the output voltage also to change by <NUM>% to <NUM>%. The regulation standard for a typical power supply is roughly ±<NUM>%. Accordingly, it is difficult to satisfy the regulation standard in a power supply that includes an element causing the output voltage to change by <NUM>% to <NUM>%. To satisfy the regulation standard, it becomes necessary to use a trimmer resistor or the like for precise adjustment of the voltage setting. This precise adjustment raises manufacturing costs.

The higher the temperature of the redundancy diode <NUM>, the more the forward voltage drop of the redundancy diode <NUM> decreases due to the negative temperature characteristics. This decrease in the forward voltage drop of the redundancy diode <NUM> increases the voltage outputted by the power supply apparatus <NUM>. In turn, the increase in the voltage outputted by the power supply apparatus <NUM> increases the current outputted by the power supply apparatus <NUM> to the load <NUM>. The increase in the current outputted by the power supply apparatus <NUM> raises the temperature of the redundancy diode <NUM>. In this way, positive feedback may occur in the temperature of the redundancy diode <NUM>. The current outputted by the power supply apparatus <NUM> to the load <NUM> and the current outputted by the power supply apparatus <NUM> to the load <NUM> therefore easily become imbalanced in the configuration that connects to the load <NUM> via the redundancy diodes <NUM>, <NUM>.

The case of the power supply apparatuses <NUM>, <NUM> not including the redundancy diodes <NUM>, <NUM> is described as a second comparative example. In the second comparative example, the current-voltage characteristics of the power supply apparatuses <NUM>, <NUM> exhibit a droop characteristic. The droop characteristic represents the characteristic whereby the outputted voltage decreases as the current outputted to the load <NUM> increases. When the power supply apparatuses <NUM>, <NUM> are connected in parallel to the load <NUM>, the droop characteristic makes it easier to balance the current outputted by each of the power supply apparatuses <NUM>, <NUM> even though the redundancy diodes <NUM>, <NUM> are not included. However, the lack of redundancy diodes <NUM>, <NUM> means that if the power supply apparatus <NUM> suffers a short-circuit failure, for example, the current of the power supply apparatus <NUM> flows to the short-circuit point of the power supply apparatus <NUM>. This leads to effects such as the current supplied from the power supply apparatus <NUM> to the load <NUM> becoming insufficient, or the voltage outputted by the power supply apparatus <NUM> decreasing. The power supply system <NUM> overall therefore becomes unable to maintain the supply of power to the load <NUM>.

A configuration in which each of the power supply apparatuses <NUM>, <NUM> output current matching the current outputted by another apparatus is described as a third comparative example. In the third comparative example, the power supply apparatus <NUM> needs to include a circuit for detecting the current outputted by another apparatus and a circuit for controlling the outputted current based on the detected current. Such a configuration leads to increased apparatus cost.

A configuration in which the power supply apparatuses <NUM>, <NUM> include a micro control unit (MCU) is described as a fourth comparative example. In the fourth comparative example, one of the power supply apparatuses <NUM>, <NUM> that are connected in parallel to the load <NUM> functions as a master, and the other functions as a slave. Based on the detected voltage and current outputted by each apparatus, the MCU of the apparatus functioning as the master outputs control information to the MCU of the apparatus functioning as the slave. This configuration allows the MCU to balance the current outputted by each apparatus and to reduce variation in the voltage. A configuration using an MCU, however, requires that each apparatus detect and communicate the outputted voltage and current. A program to operate the MCU is also required. Use of an MCU therefore leads to an increase in device cost.

As described above, the configurations in the comparative examples have problems such as a difficulty in balancing the current outputted by the power supply apparatuses <NUM>, <NUM> and vulnerability to short-circuit failure. These problems reduce the reliability of the power supply system <NUM> and the power supply apparatus <NUM>.

The present disclosure therefore describes a highly reliable power supply apparatus and power supply system.

As illustrated in <FIG>, a power supply system <NUM> according to an embodiment includes power supply apparatuses 10a, 10b. The power supply apparatuses 10a, 10b are referred to as a power supply apparatus <NUM> when no distinction therebetween is necessary.

The power supply apparatus 10a includes an output terminal 11a and a ground terminal 12a. The power supply apparatus 10b includes an output terminal 11b and a ground terminal 12b. The output terminals 11a, 11b are referred to as an output terminal <NUM> when no distinction therebetween is necessary. The ground terminals 12a, 12b are referred to as a ground terminal <NUM> when no distinction therebetween is necessary.

The power supply apparatuses 10a, 10b are connected to a load <NUM> in parallel. One terminal of the load <NUM> is connected to the output terminals 11a, 11b. The other terminal of the load <NUM> is connected to a ground point <NUM> and to the ground terminals 12a, 12b. The current outputted by the power supply apparatus 10a from the output terminal 11a is represented as I1. The current outputted by the power supply apparatus 10b from the output terminal 11b is represented as I2. The power supply system <NUM> supplies the load <NUM> with the current yielded by combining the current outputted by the power supply apparatus 10a from the output terminal 11a and the current outputted by the power supply apparatus 10b from the output terminal 11b. In other words, the power supply system <NUM> provides the current represented as I1 + I2 to the load <NUM>. The current supplied to the load <NUM> may flow to the ground point <NUM> or may return to the power supply apparatuses 10a, 10b through the ground terminals 12a, 12b.

The present embodiment is described below assuming that two power supply apparatuses <NUM> are connected to the load <NUM> in parallel. Three or more power supply apparatuses <NUM> may instead be connected to the load <NUM> in parallel.

When the two power supply apparatuses <NUM> are connected in parallel to the load <NUM>, and one power supply apparatus <NUM> fails, then the other power supply apparatus <NUM> supplies power to the load <NUM>. The power supply system <NUM> overall thereby continues to supply power to the load <NUM>. The current outputted by each power supply apparatus <NUM> when both power supply apparatuses <NUM> are operating normally may be controlled to be <NUM>% of the current required by the load <NUM>. The current required by the load <NUM> is thereby supplied from the two power supply apparatuses <NUM> in a balanced manner. The current outputted by each power supply apparatus <NUM> is referred to as the load current IL. The maximum current required by the load <NUM> is referred to as the maximum load current. When the load <NUM> requires the maximum load current, each power supply apparatus <NUM> is controlled so that the sum of the load currents IL becomes the maximum load current. In the present embodiment, the load <NUM> is assumed to require the maximum load current.

As illustrated in <FIG>, the power supply apparatus <NUM> includes a converter <NUM>, a current detector <NUM>, a FET <NUM>, and a voltage monitor <NUM>.

The converter <NUM> includes a converter output terminal <NUM>, a converter ground terminal <NUM>, and a feedback terminal <NUM>. The converter <NUM> outputs the load current IL from the converter output terminal <NUM> towards the output terminal <NUM>. The current detector <NUM> and the FET <NUM> are connected in series between the converter output terminal <NUM> and the output terminal <NUM>. The load current IL outputted from the converter output terminal <NUM> flows through the current detector <NUM> and the FET <NUM> and is outputted from the output terminal <NUM> to the load <NUM>. In other words, the power supply apparatus <NUM> outputs the load current IL from the output terminal <NUM> that is connected to one terminal of the load <NUM>.

The power supply apparatus <NUM> outputs an output voltage Vout between the output terminal <NUM> and the ground terminal <NUM>. The output voltage Vout corresponds to the voltage yielded by subtracting the voltage drop due to the load current IL flowing through the current detector <NUM> and the FET <NUM> from the voltage outputted by the converter <NUM> between the converter output terminal <NUM> and the converter ground terminal <NUM>. The voltage outputted by the converter <NUM> between the converter output terminal <NUM> and the converter ground terminal <NUM> is also referred to as the converter voltage VCONV. The converter <NUM> controls the converter voltage VCONV based on a signal inputted to the feedback terminal <NUM>.

The current detector <NUM> detects the load current IL flowing from the converter output terminal <NUM> to the output terminal <NUM>. Based on the detected load current IL, the current detector <NUM> generates a current signal ID to input to the feedback terminal <NUM>. As described below, the converter <NUM> feeds the inputted current signal ID back to the control of the converter voltage VCONV.

The FET <NUM> is driven by receiving power from the power supply, represented as VCC. Based on the signal outputted by the current detector <NUM>, the FET <NUM> controls the current that flows between the converter output terminal <NUM> and the output terminal <NUM>. The FET <NUM> is assumed to be an n-channel metal oxide silicon FET (MOSFET), but this example is not limiting. The FET <NUM> includes a body diode. The FET <NUM> is connected so that the forward direction of the body diode matches the direction in which the load current IL flows from the converter <NUM> towards the load <NUM>. The FET <NUM> is also referred to as a redundancy FET.

The voltage monitor <NUM> detects the voltage across both ends of the FET <NUM>. Based on the detection result, the voltage monitor <NUM> controls the opening and closing of a switching element Q14. When closed, the switching element Q14 creates a short circuit between the source and gate of the FET <NUM>.

As illustrated in <FIG>, the converter <NUM> includes a controller <NUM>, an error amplifier <NUM>, and a voltage converter <NUM>. The converter <NUM> converts the power supplied from an external power supply VIN to direct current (DC) power identified by the load current IL and the converter voltage VCONV.

The voltage converter <NUM> includes a switching element Q1, a diode D1, an inductor L1, and a capacitor C1. The switching element Q1 is assumed to be an n-channel MOSFET, but this example is not limiting. The drain of the switching element Q1 is connected to the external power supply VIN. The external power supply VIN is represented as a DC power supply but may instead be an alternating current (AC) power supply. The source of the switching element Q1 is connected to the cathode of the diode D1 and one terminal of the inductor L1. The gate of the switching element Q1 is connected to the controller <NUM>. The other terminal of the inductor L1 is connected to one terminal of the capacitor C1. The anode of the diode D1 and the other terminal of the capacitor C1 are connected to the ground point <NUM>.

The switching element Q1 converts the voltage of the external power supply VIN to an AC signal by switching between being open and closed based on a control signal from the controller <NUM>. The controller <NUM> may control the AC signal by a pulse width modulation (PWM) method or by another modulation method. The switching element Q1 is assumed to generate a PWM signal controlled by a PWM method.

The PWM signal is rectified by the diode D1 and is smoothed by the inductor L1 and the capacitor C1 to be converted to DC voltage having a predetermined voltage level. In other words, the voltage converter <NUM> forms a step-down switching power supply that steps down the voltage of the external power supply VIN. As the duty ratio of the PWM signal is larger, the voltage level of the DC voltage outputted by the voltage converter <NUM> increases. The voltage converter <NUM> may be a boost switching power supply.

The node of the voltage converter <NUM> between the inductor L1 and the capacitor C1 is connected to the converter output terminal <NUM>. The DC voltage outputted by the voltage converter <NUM> is outputted from the converter output terminal <NUM> as the converter voltage VCONV.

The error amplifier <NUM> includes an operational amplifier U1, resistors R121, R122, and a reference power supply Vref.

The resistors R121, R122 are connected in series between the converter output terminal <NUM> and the converter ground terminal <NUM>. The node between the resistor R121 and the resistor R122 is connected to an inverting input terminal of the operational amplifier U1. The voltage of the node between the resistor R121 and the resistor R122 corresponds to a voltage yielded by dividing the converter voltage VCONV. In other words, the voltage yielded by dividing the converter voltage VCONV is inputted to the inverting input terminal of the operational amplifier U1. The reference power supply Vref is connected to a non-inverting input terminal of the operational amplifier U1. The voltage of the reference power supply Vref is inputted to the non-inverting input terminal of the operational amplifier U1. The output terminal of the operational amplifier U1 is connected to the inverting input terminal of the operational amplifier U1 via a feedback circuit. The feedback circuit may include a resistor and a capacitor.

The output terminal of the operational amplifier U1 is connected to the controller <NUM>. The operational amplifier U1 operates so that the voltage inputted to the inverting input terminal matches the voltage inputted to the non-inverting input terminal. The operational amplifier U1 outputs a signal, to the controller <NUM>, for matching the voltage of the node between the resistor R121 and the resistor R122 to the voltage of the reference power supply Vref.

Based on the output of the operational amplifier U1, the controller <NUM> outputs a control signal for controlling the opening and closing of the switching element Q1 to the gate of the switching element Q1. The controller <NUM> can control the converter voltage VCONV by using the PWM method to control the AC signal outputted by the switching element Q1. The controller <NUM> may include a processor such as a central processing unit (CPU). The controller <NUM> may control the converter voltage VCONV by executing a predetermined program.

When the current signal ID is not inputted to the feedback terminal <NUM>, the converter <NUM> controls the converter voltage VCONV based on the voltage of the reference power supply Vref. When the current signal ID is inputted to the feedback terminal <NUM>, the current signal ID flows to the ground point <NUM> via the resistor R122. In other words, the current signal ID flows to the resistor R122 superimposed on current that is based on the converter voltage VCONV. The current signal ID is also referred to as a superimposed current signal. The voltage of the node between the resistor R121 and the resistor R122 rises as a result of the superimposed current signal flowing to the resistor R122. As a result of the operations of the operational amplifier U1 and the controller <NUM>, the converter voltage VCONV reduces as the current signal ID grows larger. The relationship between the load current IL and the converter voltage VCONV can be appropriately set by the current detector <NUM> determining the current signal ID based on the load current IL, as described below.

As illustrated in <FIG>, the current detector <NUM> includes a resistor Rs connected in series between the converter output terminal <NUM> and the FET <NUM>. The resistor Rs detects the load current IL. The resistor Rs is also referred to as a current detection unit. The sign of the load current IL is assumed to be positive when current flows from the converter output terminal <NUM> towards the FET <NUM>.

The current detector <NUM> includes a droop characteristic controller <NUM>. The droop characteristic controller <NUM> generates the current signal ID based on the voltage across both ends of the resistor Rs. The voltage across both ends of the resistor Rs corresponds to the magnitude of the voltage drop occurring due to the current flowing through the resistor Rs and is expressed as the product of Rs and IL. The potential at the converter <NUM> side of the resistor Rs is expressed as VCONV. The potential at the FET <NUM> side of the resistor Rs is expressed as VCONV - Rs · IL. The potential at each end of the resistor Rs is expressed as the potential difference from the ground point <NUM>.

The droop characteristic controller <NUM> includes operational amplifiers U13B, U13C, U13D, resistors R135, R136, R137, R138, a Zener diode REFN, and a switching element Q139.

The terminal of the resistor Rs on the FET <NUM> side is connected to a non-inverting input terminal of the operational amplifier U13B. The terminal of the resistor Rs on the converter <NUM> side is connected to the inverting input terminal of the operational amplifier U13B via the resistor R136 and is also connected to the inverting input terminal of the operational amplifier U13B via the Zener diode REFN and the resistor R135. In other words, the resistor R136 and the series connection circuit including the Zener diode REFN and the resistor R135 are connected in parallel between the terminal of the resistor Rs on the converter <NUM> side and the inverting input terminal of the operational amplifier U13B. The output terminal of the operational amplifier U13B is connected to the inverting input terminal of the operational amplifier U13B via the resistor R137.

The operational amplifier U13B controls output so that the voltage inputted to the inverting input terminal matches the voltage inputted to the non-inverting input terminal. In the example in <FIG>, the operational amplifier U13B controls the output voltage VB of its output terminal to be the value represented by Expression (<NUM>) below. <MAT> Here, R135//R136 represents the parallel resistance between the resistor R135 and the resistor R136.

The operational amplifier U13C is connected to the Zener diode REFN and the operational amplifiers U13B, U13D and clamps the lower limit of the voltage inputted to the non-inverting input terminal of the operational amplifier U13D to a predetermined value. The non-inverting input terminal of the operational amplifier U13C is connected to the Zener diode REFN. The voltage inputted to the non-inverting input terminal of the operational amplifier U13C is represented by VCONV - REFN. The inverting input terminal of the operational amplifier U13C is connected to the non-inverting input terminal of the operational amplifier U13D and is also connected to the output terminal of the operational amplifier U13C via a diode. In other words, the output terminal of the operational amplifier U13C is connected, via a diode, to the inverting input terminal of the operational amplifier U13C and the non-inverting input terminal of the operational amplifier U13D. The output terminal of the operational amplifier U13C is further connected to the output terminal of the operational amplifier U13B via a resistor. The diode connected to the output terminal of the operational amplifier U13C is connected so that current from the output terminal of the operational amplifier U13C flows in the forward direction. By being connected in this way, the operational amplifier U13C clamps the lower limit of the voltage inputted to the non-inverting input terminal of the operational amplifier U13D at VCONV - REFN.

The operational amplifier U13D is connected to the operational amplifiers U13B, U13C, the resistor R138, and the switching element Q139. The switching element Q139 is assumed to be a p-channel MOSFET, but this example is not limiting. The operational amplifier U13D and the switching element Q139 generate a current signal ID based on the load current IL. The non-inverting input terminal of the operational amplifier U13D is connected to the output terminals of the operational amplifiers U13B and U13C. The voltage inputted to the non-inverting input terminal of the operational amplifier U13D is designated VD. The inverting input terminal of the operational amplifier U13D is connected to the converter <NUM> side of the resistor Rs via the resistor R138 and also to the source of the switching element Q139. The output terminal of the operational amplifier U13D is connected to the gate of the switching element Q139. The drain of the switching element Q139 is connected to the feedback terminal <NUM> of the converter <NUM>. The operational amplifier U13D controls the current signal ID that flows from the drain of the switching element Q139 to the feedback terminal <NUM>. The current signal ID is controlled in three different ways, indicated by cases <NUM> to <NUM> below, based on the magnitude of the load current IL.

This is the case when the following expression holds. <MAT> <MAT>.

This is the case when the following expressions both hold. <MAT> <MAT> <MAT>.

This is the case when the following expression holds.

The value of the load current IL that differentiates between case <NUM> and case <NUM> is also referred to as a first threshold current. The value of the load current IL that differentiates between case <NUM> and case <NUM> is also referred to as a second threshold current. By Expression (<NUM>), the current signal ID is not outputted until the load current IL reaches the first threshold current. By Expression (<NUM>), the current signal ID increases as the load current IL increases while the load current IL is larger than the first threshold current but does not reach the second threshold current. By Expression (<NUM>), the current signal ID becomes constant once the load current IL exceeds the second threshold current.

The converter <NUM> controls the converter voltage VCONV based on the current signal ID inputted to the feedback terminal <NUM>. The converter voltage VCONV decreases as the current signal ID increases. When the load current IL is in the range specified by case <NUM>, the converter voltage VCONV does not decrease. When the load current IL is in the range specified by case <NUM>, the amount of decrease in the converter voltage VCONV is larger as the load current IL increases. When the load current IL is in the range specified by case <NUM>, the amount of decrease in the converter voltage VCONV becomes constant.

Based on the relationship between the load current IL and the current signal ID identified by Expressions (<NUM>) to (<NUM>), the relationship between the load current IL and the output voltage Vout is determined, for example as in the graph in <FIG>. The horizontal axis represents the load current IL, and the vertical axis represents the output voltage Vout in the graph in <FIG>. The plot labeled Typ characteristics represents typical current-voltage characteristics based on a configuration according to the present embodiment. The plots labeled Max variation characteristics and Min variation characteristics represent the assumed upper limit and lower limit on current-voltage characteristics within the possible range of variation exhibited by parameters such as FETs or operational amplifiers in the configuration according to the present embodiment. The plot labeled Typ characteristics is assumed below to represent the current-voltage characteristics according to the present embodiment.

A rated current is set as part of the specifications of the power supply apparatus <NUM>. The rated current represents the upper limit of the current at which the power supply apparatus <NUM> can operate stably. In other words, operations of the power supply apparatus <NUM> are stable when the power supply apparatus <NUM> outputs current at or below the rated current. Conversely, operations of the power supply apparatus <NUM> may become unstable if the power supply apparatus <NUM> outputs current exceeding the rated current. The rated current is indicated by Irate on the horizontal axis of the graph in <FIG>.

Even if one power supply apparatus <NUM> alone supplies current to the load <NUM>, the upper limit of the load current IL of the power supply apparatus <NUM> is the maximum load current. In the power supply apparatus <NUM>, the rated current is set to a larger value than the maximum load current. The rated current may be the same value as the maximum load current. The maximum load current is indicated by <NUM>% (ILmax) on the horizontal axis of the graph in <FIG>. The ratio of the load current IL to the maximum load current is also referred to as the load factor. The horizontal axis of the graph in <FIG> represents the value of the load current IL along with the load factor. Each power supply apparatus <NUM> is controlled so that the sum of the load currents IL becomes the maximum load current. For example, when two power supply apparatuses <NUM> are connected to the load <NUM> in parallel, and the load factor of one power supply apparatus <NUM> is <NUM>%, then the load factor of the other power supply apparatus <NUM> is <NUM>%.

As part of the specifications of the power supply apparatus <NUM>, an overload protection (OLP) point is set for protecting the power supply apparatus <NUM> from overload. When the load current IL is greater than the OLP point, the power supply apparatus <NUM> executes an overload protection operation and suspends power supply to the load <NUM>.

The plot representing the current-voltage characteristics according to the present embodiment (Typ characteristics in <FIG>) includes a region in which the output voltage Vout hardly changes despite an increase in the load current IL and a region in which the output voltage Vout decreases as the load current IL increases. The region in which the output voltage Vout decreases as the load current IL increases is also referred to as a droop region. The range of the droop region is represented by the shaded area. The droop characteristic controller <NUM> can be considered to cause the output voltage Vout to droop in accordance with an increase in the load current IL in the droop region. The droop region and other regions may be distinguished between by the slope of the plot. The slope of the plot represents the rate of change in the output voltage Vout relative to change in the load current IL. The rate at which the output voltage Vout reduces relative to an increase in the load current IL is also referred to as the droop rate. The absolute value of the slope of the plot in the droop region is greater than the slope of the plot in other regions. In other words, the output voltage Vout decreases more in the droop region.

In <FIG>, the slope of the plot changes suddenly at two locations. The point at which the slope first changes suddenly after the load current IL starts to increase from zero is represented as P1. The load current IL at P1 corresponds to the first threshold current. The point at which the load current IL becomes a larger value than the first threshold current and the slope suddenly changes for the second time is represented as P2. The load current IL at P2 corresponds to the second threshold current.

The horizontal axis of the graph in <FIG> is divided into a plurality of sections with the first threshold current and the second threshold current as boundaries. The section in which the current is larger than the first threshold current and smaller than the second threshold current is the section that identifies the droop region. This section is referred to as the first current section. The section in which the current is smaller than the first threshold current is referred to as the second current section. The section in which the current is larger than the second threshold current is referred to as the third current section. The second current section includes a current that is smaller than the current included in the first current section. The third current section includes a current that is larger than the current included in the first current section. The droop rate when the load current IL is included in the first current section can be considered greater than the droop rate when the load current IL is included in each of the second current section and the third current section.

In the present embodiment, the first threshold current is set to a smaller value than <NUM>% of the maximum load current, but this example is not limiting. The first threshold current may be set to any value smaller than the second threshold current. The second threshold current is set to a larger value than <NUM>% of the maximum load current, but this example is not limiting. The second threshold current may be set to any value larger than the first threshold current.

The graph in <FIG> represents the relationship between the load current IL and the output voltage Vout in the above-described configuration of the second comparative example. The horizontal axis represents the load current IL, and the vertical axis represents the output voltage Vout in the graph in <FIG>. The plot labeled Typ characteristics represents typical current-voltage characteristics in the second comparative example. The plots labeled Max variation characteristics and Min variation characteristics represent the assumed upper limit and lower limit on current-voltage characteristics within the possible range of variation exhibited by parameters such as FETs or operational amplifiers in the configuration according to the second comparative example. In the comparative example, the output voltage Vout reduces in the plot labeled Typ characteristics once the load current IL begins to increase from zero. The slope of the plot changes suddenly at one point.

The load current IL outputted by each power supply apparatus <NUM> tends to be stable within the droop region when two power supply apparatuses <NUM> are connected to the load <NUM> in parallel. In the configuration of the second comparative example, the droop region includes the case of the load factor being <NUM>%. The load factor of one power supply apparatus <NUM> in this case may stabilize at or near <NUM>%, or may stabilize at <NUM>%. If the load factor of one power supply apparatus <NUM> stabilizes at <NUM>%, the load factor of the other power supply apparatus stabilizes at <NUM>%. In other words, the load factor of the power supply apparatus <NUM> could become unstable in the configuration of the second comparative example. The droop region in the configuration according to the present embodiment, on the other hand, is limited to a load factor that is larger than the first threshold current and smaller than the second threshold current. In this case, the load factor of the power supply apparatus <NUM> is more stable than in the second comparative example. Consequently, the power supply apparatus <NUM> according to the present embodiment can improve the balance of the load currents IL.

When the first threshold current is set to a value smaller than <NUM>% of the maximum load current, and the second threshold current is set to a value larger than <NUM>% of the maximum load current, then each of the two power supply apparatuses <NUM> is controlled to reduce the difference between the load currents IL. In other words, it becomes easier to balance the load currents IL of the two power supply apparatuses <NUM>.

IBmax and IBmin are indicated on the horizontal axis of the graphs in <FIG> and <FIG>. IBmax represents the current flowing at the Max variation characteristics when Vout = VB. IBmin represents the current flowing at the Min variation characteristics when Vout = VB. The current outputted by each power supply apparatus <NUM> falls between IBmax and IBmin when two power supply apparatuses <NUM> connected in parallel to the load <NUM> output current that is <NUM>% of the maximum load current to the load <NUM>. In other words, the difference between IBmax and IBmin represents the variation in the load factor of the power supply apparatus <NUM>. The range from IBmin to IBmax is referred to as the variation range of current balance at <NUM>% load. As the difference between IBmax and IBmin is smaller, the variation in the load factor of the power supply apparatus <NUM> is smaller. A small variation in the load factor makes it easier to improve the balance of the load currents IL. The variation in the load factor within the current-voltage characteristics according to the present embodiment is smaller than the variation in the load factor within the current-voltage characteristics according to the second comparative example. Consequently, the power supply apparatus <NUM> according to the present embodiment can more easily improve the balance of the load currents IL than the second comparative example.

In the droop region of the graph in <FIG>, the difference between IBmax and IBmin is smaller as the slope of the plot is sharper. In other words, the variation in the load factor can be made smaller as the droop rate is greater.

The variation in the amount of heat generated inside each power supply apparatus <NUM> can be reduced by the load factors of the two power supply apparatuses <NUM> being balanced. The more the amount of heat generation of the power supply apparatus <NUM> increases, the greater the decrease is in the lifespan of the aluminum electrolytic capacitor that follows the Arrhenius law, or the time until failure of components that have a lifespan, such as photocouplers. Accordingly, the time until failure of at least one of the two power supply apparatuses <NUM> can be lengthened by the load factors of the two power supply apparatuses <NUM> being balanced. Consequently, the reliability of the power supply system <NUM> increases.

The power supply apparatus <NUM> according to the present embodiment includes the FET <NUM> instead of the redundancy diode <NUM> of the first comparative example. The loss due to the ON resistance of a FET is smaller than the loss due to the voltage drop of a diode. For example, if the ON resistance of the FET <NUM> is <NUM> mΩ, then the loss becomes <NUM> W when the load current IL is <NUM> A. On the other hand, if the voltage drop at the redundancy diode <NUM> of the first comparative example is <NUM> V, then the loss becomes <NUM> W when the current outputted by the power supply apparatus <NUM> is <NUM> A. The power supply apparatus <NUM> according to the present embodiment can, in other words, reduce loss by including the FET <NUM>. The reduction in loss makes heat dissipation components, such as a heatsink, unnecessary and also leads to an improvement in reliability. Consequently, a reduction in size and an improvement in reliability of the power supply apparatus <NUM> can be achieved.

The ON resistance of the FET <NUM> in the present embodiment is low, which lowers the voltage drop at the FET <NUM>. In other words, even when the output voltage Vout is controlled based on the result of detecting the voltage of the stage prior to the FET <NUM>, the regulation characteristics of the voltage of the stage subsequent to the FET <NUM> are not easily affected by the voltage drop. Even if the ON resistance of the FET <NUM> changes based on temperature characteristics, or if the ON resistance exhibits variation due to individual differences between FETs <NUM>, the change in the output voltage Vout caused by these factors is smaller than the change in the output voltage Vout caused by the temperature characteristics of the redundancy diode <NUM>. A small change in the output voltage Vout makes it easier for the regulation of the output voltage Vout to satisfy standards. Consequently, adjustment of the output voltage Vout at the time of assembly of the power supply apparatus <NUM> can be omitted. Manufacturing costs can thereby be reduced.

The ON resistance of the FET <NUM> typically has positive temperature characteristics. The redundancy diode <NUM> of the first comparative example has negative temperature characteristics, causing positive feedback with respect to an increase in the current outputted by the power supply apparatus <NUM>. This tends to destabilize or worsen the load balance. In the power supply apparatus <NUM> according to the present embodiment, the ON resistance of the FET <NUM> has positive temperature characteristics, causing negative feedback with respect to an increase in the load current IL. Consequently, the load balance tends to be stable.

The current detector <NUM> includes a separation unit <NUM>, as illustrated in <FIG>. The separation unit <NUM> includes an operational amplifier U13A, resistors R131, R132, and a Zener diode REFP. When the power supply apparatus <NUM> is operating normally, the load current IL flows from the converter <NUM> towards the FET <NUM>. In this case, the potential of the resistor Rs on the converter <NUM> side is higher than the potential of the resistor Rs on the FET <NUM> side.

If a short-circuit failure occurs inside the converter <NUM>, and the FET <NUM> is on, then current would flow to the resistor Rs from the FET <NUM> towards the converter <NUM>. In this case, the potential of the resistor Rs on the converter <NUM> side is lower than the potential of the resistor Rs on the FET <NUM> side.

A non-inverting input terminal of the operational amplifier U13A is connected to the cathode side of the Zener diode REFP via the resistor R131 and is connected to the converter <NUM> side of the resistor Rs via the resistor R132. The voltage inputted to the non-inverting input terminal of the operational amplifier U13A is the result of adding, to VCONV, the voltage of the Zener diode REFP divided at the resistors R131, R132. The inverting input terminal of the operational amplifier U13A is connected to the FET <NUM> side of the resistor Rs. The voltage inputted to the inverting input terminal of the operational amplifier U13A is VCONV - Rs · IL. The output terminal of the operational amplifier U13A is connected to the inverting input terminal via a feedback circuit that includes a resistor and a capacitor and is connected to the gate of the FET <NUM>.

When the power supply apparatus <NUM> is operating normally, the voltage inputted to the non-inverting input terminal of the operational amplifier U13A is higher than the voltage inputted to the inverting input terminal. Accordingly, the output of the operational amplifier U13A reaches its maximum positive value, which turns the FET <NUM> on. If a short-circuit failure occurs inside the converter <NUM>, the operational amplifier U13A limits the current flowing from the FET <NUM> towards the converter <NUM> to be a predetermined value or less. The current flowing from the FET <NUM> to the converter <NUM> is also referred to as reverse current. The upper limit of the reverse current controlled by the operational amplifier U13A is referred to as the reverse current limit Ibk. The sign of Ibk is negative when current flows from the FET <NUM> towards the converter <NUM>. Ibk is represented by Expression (<NUM>) below based on how the non-inverting input terminal and the inverting input terminal of the operational amplifier U13A form a virtual short.

The operational amplifier U13A can limit the reverse current to be Ibk or less by controlling the voltage between the gate and source of the FET <NUM>. If the cause of reverse current flowing to the resistor Rs is temporary, it is required that the FET <NUM> return to the on state when the cause is resolved. The FET <NUM> turns on automatically in the configuration whereby the operational amplifier U13A limits the reverse current.

If the absolute value of Ibk is excessively large, then when reverse current flows to one power supply apparatus <NUM>, the other power supply apparatus <NUM> needs to output a current yielded by combining the load current IL and the reverse current. Accordingly, the sum of the absolute value of the Ibk and the maximum load current needs to be equal to or less than the rated current. This relationship is represented as Expression (<NUM>) below. <MAT> In other words, when power supply apparatuses <NUM> for which Expression (<NUM>) holds are adjoined and connected in parallel to the load <NUM>, then the overall operation of the power supply system <NUM> is maintained even if reverse current flows into one of the power supply apparatuses <NUM>.

As illustrated in <FIG>, the voltage monitor <NUM> includes an operational amplifier U14 and resistors R141, R142, R143. The voltage monitor <NUM> is connected to the switching element Q14. The switching element Q14 is assumed to be an n-channel MOSFET, but this example is not limiting. The source of the switching element Q14 is connected to the source of the FET <NUM>. The drain of the switching element Q14 is connected to the gate of the FET <NUM>. The gate of the switching element Q14 is connected to the output terminal of the operational amplifier U14. When the output terminal of the operational amplifier U14 outputs a larger voltage than a threshold voltage to the gate of the switching element Q14, the switching element Q14 turns on. When the switching element Q14 is on, the source and gate of the FET <NUM> short circuit. The voltage monitor <NUM> limits the reverse current by controlling the state of the switching element Q14.

The non-inverting input terminal of the operational amplifier U14 is connected to the drain of the FET <NUM> via the resistor R143. The voltage inputted to the non-inverting input terminal of the operational amplifier U14 is the voltage of the drain of the FET <NUM>. The inverting input terminal of the operational amplifier U14 is connected to the source of the FET <NUM> via the resistor R142 and is connected to the cathode of the Zener diode REFP (see <FIG>) via the resistor R141. The voltage inputted to the inverting input terminal of the operational amplifier U14 is the result of adding, to the voltage of the source of the FET <NUM>, the voltage of the Zener diode REFP divided at the resistors R141, R142. The voltage of the Zener diode REFP divided at the resistors R141, R142 is also referred to as a monitoring offset voltage.

The operational amplifier U14 can detect the reverse current based on the voltage between the source and the gate of the FET <NUM>. When the power supply apparatus <NUM> is operating normally, the load current IL flows from the source to the drain of the FET <NUM>. In this case, the voltage of the source of the FET <NUM> is higher than the voltage of the drain. In other words, the voltage inputted to the inverting input terminal of the operational amplifier U14 becomes higher than the voltage inputted to the non-inverting input terminal. The voltage that the output terminal of the operational amplifier U14 outputs to the gate of the switching element Q14 becomes <NUM>. Consequently, the switching element Q14 turns off.

If a short-circuit failure occurs inside the converter <NUM> and reverse current flows, the voltage of the source of the FET <NUM> becomes lower than the voltage of the drain. When the difference between the voltage of the drain and the voltage of the source of the FET <NUM> becomes larger than the voltage of the Zener diode REFP divided by the resistors R141, R142, the output terminal of the operational amplifier U14 outputs positive voltage to the gate of the switching element Q14. As a result of a larger voltage than the threshold voltage being inputted to the gate of the switching element Q14, the source and gate of the FET <NUM> short circuit. The FET <NUM> turns off due to the short circuiting of the source and gate of the FET <NUM>. Consequently, the reverse current flowing to the FET <NUM> is cut off. When the internal voltage applied to the source side of the FET <NUM> reduces due to internal failure of the converter <NUM> or the like upon the reverse current being cut off at the FET <NUM>, the FET <NUM> is maintained in the off state by the output voltage of the other power supply apparatus <NUM> at the drain side of the FET <NUM> being applied.

The operational amplifier U14 compares the voltage of the drain of the FET <NUM> with the sum of the voltage of the source of the FET <NUM> and the monitoring offset voltage and outputs a signal based on the result of comparison to the gate of the switching element Q14. The switching element Q14 controls the resistance between the source and gate of the FET <NUM> based on the signal inputted to the gate. In other words, the voltage monitor <NUM> inputs, to the gate of the FET <NUM>, a signal based on the result of comparing the voltage of the drain of the FET <NUM> with the sum of the voltage of the source of the FET <NUM> and the monitoring offset voltage. The reverse current is consequently controlled.

A reverse current threshold ILoff at which the reverse current is cut off is expressed by Expression (<NUM>) below. <MAT> The reverse current threshold ILoff is assumed to be a positive value when current flows from the source to the drain of the FET <NUM>. Ron represents the ON resistance of the FET <NUM>.

If the FET <NUM> turns off due to noise or the like while the power supply apparatus <NUM> is operating normally, then the load current IL flowing in the FET <NUM> momentarily decreases. However, if ILoff is always a negative value regardless of circuit variation or the like, the FET <NUM> always turns back on.

If current at the reverse current threshold ILoff flows in one power supply apparatus <NUM>, then the other power supply apparatus <NUM> needs to output a current yielded by combining the load current IL and the reverse current. An excessively large absolute value of ILoff causes the current yielded by combining the load current IL and the reverse current to exceed the OLP point. If the current outputted by the power supply apparatus <NUM> exceeds the OLP point, the power supply apparatus <NUM> reduces the output voltage Vout with an overload protection function. In this case, the supply of power to the load <NUM> can no longer be continued. Accordingly, the sum of the absolute value of ILoff and the maximum load current needs to be limited to a current equal to or less than the OLP point of the power supply apparatus <NUM>. This relationship is represented as Expression (<NUM>) below. <MAT> IOLP2 represents the current at the OLP point.

If the sum of the absolute value of ILoff and the maximum load current is equal to or less than the OLP point of the power supply apparatus <NUM>, then the power supply apparatus <NUM> in which reverse current is not flowing is not stopped by the overload protection function. Consequently, the power supply system <NUM> overall can continue to supply power to the load <NUM>. In other words, when power supply apparatuses <NUM> for which Expression (<NUM>) holds are adjoined and connected in parallel to the load <NUM>, then the overall operation of the power supply system <NUM> is maintained even if reverse current flows into one of the power supply apparatuses <NUM>.

Normally, operations of the power supply apparatus <NUM> are guaranteed by the current output of the power supply apparatus <NUM> being limited to being equal to or less than the rated current. In Expression (<NUM>), however, output of current at the OLP point, which exceeds the rated current, is allowed. The reason why this configuration allows a current exceeding the rated current is that failure of the power supply apparatus <NUM> can be avoided by limiting the length of time that such current flows.

The length of time that current with a magnitude of ILoff flows is limited by the FET <NUM> turning off to cut off reverse current when reverse current in the power supply apparatus <NUM> exceeds ILoff. In this way, output of current exceeding the rated current of the power supply apparatus <NUM> is permitted for a limited time.

The configuration combining the voltage monitor <NUM> and the switching element Q14 may be replaced with a synchronous rectification control IC.

The function for the voltage monitor <NUM> and the switching element Q14 to limit the reverse current and the function for the separation unit <NUM> to limit the reverse current can replace each other. Accordingly, the power supply apparatus <NUM> can limit the reverse current and improve reliability by including at least one of the configuration combining the voltage monitor <NUM> and the switching element Q14 and the configuration of the separation unit <NUM>. The configuration combining the voltage monitor <NUM> and the switching element Q14 and the configuration of the separation unit <NUM> are also referred to as a reverse current limitation unit. The reverse current limit Ibk and the reverse current threshold ILoff are also referred to as a reverse current reference limit.

When the reverse current is limited by the voltage monitor <NUM> and the switching element Q14, the FET <NUM> turns off. The loss in the FET <NUM> when a short-circuit failure occurs is therefore reduced or brought nearly to zero. The reduction of loss in the FET <NUM> reduces the probability of chain-reaction failure in the other power supply apparatus <NUM> connected in parallel to the load <NUM>.

When the reverse current is limited by the separation unit <NUM>, the variation in the limit on the reverse current can be reduced by a reduction in the variation of Zener voltage of the Zener diode REFP and in the variation of resistance of the resistors R131, R132.

The operational amplifier U14 sometimes includes a grounding unit to be grounded to the ground point <NUM>. When the grounding unit of the operational amplifier U14 is grounded, the operational amplifier U14 forms a bridge between the path for outputting the load current IL of the power supply apparatus <NUM> and the ground point <NUM>. Besides the operational amplifier U14, other circuit components included in the current detector <NUM> might form a bridge between the path for outputting the load current IL of the power supply apparatus <NUM> and the ground point <NUM>. A component that forms a bridge between the path for outputting the load current IL of the power supply apparatus <NUM> and the ground point <NUM> is also referred to as a bridge component. A path that forms a bridge between the path for outputting the load current IL of the power supply apparatus <NUM> and the ground point <NUM> is also referred to as a bridge path.

When a bridge component suffers a short-circuit failure, short-circuit current flows in the bridge path. In the example in <FIG>, for example, if the grounding unit and the non-inverting input terminal or the inverting input terminal of the operational amplifier U14 short circuit due to an internal failure or the like of the operational amplifier U14, then the path for outputting the load current IL of the power supply apparatus <NUM> and the ground point <NUM> short circuit. Consequently, short-circuit current flows from the path for outputting the load current IL to the ground point <NUM>.

As a result of the resistor R143 being inserted in series between the non-inverting input terminal of the operational amplifier U14 and the path over which the load current IL flows, the resistor R143 limits the short-circuit current passing through the non-inverting input terminal. As a result of the resistor R142 being inserted in series between the inverting input terminal of the operational amplifier U14 and the path over which the load current IL flows, the resistor R142 limits the short-circuit current passing through the inverting input terminal. A resistance element may be connected in series in the bridge path not only in the operational amplifier U14 but also in any other bridge component for the resistance element to limit the short-circuit current due to short-circuit failure of the bridge component.

A resistance element connected in series in the bridge path facilitates continued operations of the power supply apparatus <NUM>. Consequently, the reliability of the power supply apparatus <NUM> increases.

As described above, the reliability of the power supply system <NUM> increases when the power supply system <NUM> is configured by connecting power supply apparatuses <NUM> according to the present embodiment in parallel to the load <NUM>. The power supply apparatus <NUM> according to the present embodiment can achieve various functions for improving reliability without use of an MCU. Apparatus costs can be reduced by the omission of an MCU.

As illustrated in <FIG>, a power supply system <NUM> according to another embodiment includes power supply apparatuses 10a, 10b, 10c. The power supply apparatuses 10a, 10b are assumed to be the same as the power supply apparatuses 10a, 10b illustrated in <FIG>. The power supply apparatuses 10a, 10b, 10c are referred to as a power supply apparatus <NUM> when no distinction therebetween is necessary.

The power supply apparatus 10c includes an output terminal 11c and a ground terminal 12c. The output terminals 11a, 11b, 11c are referred to as an output terminal <NUM> when no distinction therebetween is necessary. The ground terminals 12a, 12b, 12c are referred to as a ground terminal <NUM> when no distinction therebetween is necessary.

The power supply apparatuses 10a, 10b, 10c are connected to a load <NUM> in parallel. One terminal of the load <NUM> is connected to the output terminals 11a, 11b, 11c. The other terminal of the load <NUM> is connected to a ground point <NUM> and to the ground terminals 12a, 12b, 12c. The current outputted by the power supply apparatus 10a from the output terminal 11a is represented as I1. The current outputted by the power supply apparatus 10b from the output terminal 11b is represented as I2. The current outputted by the power supply apparatus 10c from the output terminal 11c is represented as I3. The power supply system <NUM> supplies the load <NUM> with the current yielded by combining the current outputted by the power supply apparatus 10a from the output terminal 11a, the current outputted by the power supply apparatus 10b from the output terminal 11b, and the current outputted by the power supply apparatus 10c from the output terminal 11c. In other words, the power supply system <NUM> provides the current represented as I1 + I2 + I3 to the load <NUM>. The current supplied to the load <NUM> may flow to the ground point <NUM> or may return to the power supply apparatuses 10a, 10b, 10c through the ground terminals 12a, 12b, 12c.

When the three power supply apparatuses <NUM> are connected in parallel to the load <NUM>, and one power supply apparatus <NUM> fails, then another power supply apparatus <NUM> supplies power to the load <NUM>. The power supply system <NUM> overall thereby continues to supply power to the load <NUM>. The current outputted by each power supply apparatus <NUM> when all three power supply apparatuses <NUM> are operating normally may be controlled to be <NUM>/<NUM> of the current required by the load <NUM>. The current required by the load <NUM> is thereby supplied from the three power supply apparatuses <NUM> in a balanced manner.

The relationship between the load current IL and the output voltage Vout in the power supply apparatus <NUM> according to the present embodiment is, for example, determined as in the graph of <FIG>. The horizontal axis represents the load current IL, and the vertical axis represents the output voltage Vout in the graph in <FIG>. The plot labeled Typ characteristics represents typical current-voltage characteristics based on a configuration according to the present embodiment. The plots labeled Max variation characteristics and Min variation characteristics represent the assumed upper limit and lower limit on current-voltage characteristics within the possible range of variation exhibited by parameters such as FETs or operational amplifiers in the configuration according to the present embodiment. The plot labeled Typ characteristics is assumed below to represent the current-voltage characteristics according to the present embodiment.

In <FIG>, the slope of the plot changes suddenly at four locations. The point at which the slope first changes suddenly after the load current IL starts to increase from zero is represented as P1. The load current IL at P1 corresponds to a first threshold current. The point at which the load current IL becomes a larger value than the first threshold current and the slope suddenly changes for the second time is represented as P2. The load current IL at P2 corresponds to a second threshold current. The point at which the load current IL becomes a larger value than the second threshold current and the slope suddenly changes for the third time is represented as P3. The load current IL at P3 corresponds to a third threshold current. The point at which the load current IL becomes a larger value than the third threshold current and the slope suddenly changes for the fourth time is represented as P4. The load current IL at P4 corresponds to a fourth threshold current.

The horizontal axis of the graph in <FIG> is divided into a plurality of sections with the first threshold current through the fourth threshold current as boundaries. The section in which the current is larger than the first threshold current and smaller than the second threshold current is the section that identifies a first droop region. This section is referred to as the first current section. The section in which the current is smaller than the first threshold current is referred to as the second current section. The section in which the current is larger than the second threshold current and smaller than the third threshold current is referred to as the third current section. The section in which the current is larger than the third threshold current and smaller than the fourth threshold current is the section that identifies a second droop region. This section is referred to as the fourth current section. The section in which the current is larger than the fourth threshold current is referred to as the fifth current section. The second current section includes a current that is smaller than the current included in the first current section. The third current section includes a current that is larger than the current included in the first current section and smaller than the current included in the fourth current section. The fifth current section includes a current that is larger than the current included in the fourth current section. The droop rate when the load current IL is included in the first current section can be considered greater than the droop rate when the load current IL is included in each of the second current section and the third current section. The droop rate when the load current IL is included in the fourth current section can be considered greater than the droop rate when the load current IL is included in each of the third current section and the fifth current section.

When the current outputted by each power supply apparatus <NUM> is balanced with respect to the maximum load current ILmax of the load <NUM>, the current outputted by each power supply apparatus <NUM> is referred to as an ideal balanced current IB1. The first threshold current is set to a smaller value than IB1. The second threshold current is set to a larger value than IB1. IB1 is represented by Expression (<NUM>) below.

IB1max and IB1min are indicated on the horizontal axis of the graph in <FIG>. IB1max represents the current flowing at the Max variation characteristics, and IB1min represents the current flowing at the Min variation characteristics, when Vout = VB1. VB1 represents the voltage outputted by the output terminal of the operational amplifier U13B in the droop characteristic controller <NUM> when the load currents IL of the three power supply apparatuses <NUM> are balanced. The difference between IB1max and IB1min represents the variation of the load factor that can occur when the load currents IL of the three power supply apparatuses <NUM> are balanced. In other words, as the difference between IB1max and IB1min is smaller, the variation in the load factor of the three power supply apparatuses <NUM> is smaller.

If one of the three power supply apparatuses <NUM> fails, and the current outputted by the two operating power supply apparatuses <NUM> is balanced, then the current outputted by each of the two power supply apparatuses <NUM> is referred to as an ideal balanced current IB2. The third threshold current is set to a smaller value than IB2. The fourth threshold current is set to a larger value than IB2. Expression (<NUM>) below holds when the maximum reverse current that can flow to one power supply apparatus <NUM> that has failed is represented by the reverse current limit Ibk.

IB2max and IB2min are indicated on the horizontal axis of the graph in <FIG>. IB2max represents the current flowing at the Max variation characteristics, and IB2min represents the current flowing at the Min variation characteristics, when Vout = VB2. VB2 represents the voltage outputted by the output terminal of the operational amplifier U13B in the droop characteristic controller <NUM> when one power supply apparatus <NUM> has failed and the load currents IL of the other two power supply apparatuses <NUM> are balanced. The difference between IB2max and IB2min represents the variation of the load factor that can occur when the load currents IL of the two power supply apparatuses <NUM> are balanced. In other words, as the difference between IB2max and IB2min is smaller, the variation in the load factor of the two power supply apparatuses <NUM> is smaller.

IB2max represents the maximum value of the load current IL that can flow in one of the two power supply apparatuses <NUM> whose load currents IL are balanced. IB2max is larger than IB2. IB2max is required to be equal to or less than the rated current Irate. Therefore, Expression (<NUM>) below holds.

As a result of the current-voltage characteristics of the power supply apparatuses <NUM> being set as in the graph in <FIG>, the load currents IL of the operating power supply apparatuses <NUM> are easier to balance, both when all three power supply apparatuses <NUM> are operating and when one power supply apparatus <NUM> has failed. Consequently, the reliability of the power supply system <NUM> increases.

In more general terms, the power supply system <NUM> may include (N + <NUM>) power supply apparatuses <NUM>. Here, N is a natural number and is two or more. In this case, the above-described Expressions (<NUM>) to (<NUM>) are generalized as Expressions (<NUM>) to (<NUM>) below. <MAT> <MAT> <MAT>.

(N + <NUM>) is referred to as a first predetermined number. N is referred to as a second predetermined number. The second predetermined number is the result of subtracting one from the first predetermined number. Based on Expression (<NUM>), IB1 is represented as the product of the maximum load current ILmax and the inverse of the first predetermined number. Based on Expression (<NUM>), IB2 is represented as the product of (i) the sum of the maximum load current ILmax and the absolute value of the reverse current limit Ibk and (ii) the inverse of the second predetermined number. When the reverse current limit Ibk is sufficiently smaller than the maximum load current ILmax, Expression (<NUM>) may be replaced by Expression (<NUM>) below. <MAT> In this case, IB2 is represented as the product of the maximum load current ILmax and the inverse of the second predetermined number.

As a result of Expression (<NUM>), Expression (<NUM>) or (<NUM>), and Expression (<NUM>) holding, the load currents IL of N power supply apparatuses <NUM> are easier to balance, both when (N + <NUM>) power supply apparatuses <NUM> are all operating and when one power supply apparatus <NUM> has failed. Consequently, the reliability of the power supply system <NUM> increases.

When the power supply apparatus <NUM> supplies negative power output, a p-channel MOSFET may be used as the FET <NUM>.

In an embodiment, the current detection unit is connected in series to the path over which the load current IL outputted by the converter <NUM> flows towards the load <NUM>. In another embodiment in which the load current IL outputted by the converter <NUM> returns to the converter <NUM> over an independent path, the current detection unit may be connected in series to the path over which the load current IL returns from the load <NUM> to the converter <NUM>. This allows an operational amplifier that is not rail-to-rail to be used as the operational amplifier that acquires the detection result of the current detection unit in the current detector <NUM>.

Claim 1:
A power supply apparatus (<NUM>) comprising:
a converter (<NUM>) configured to supply current to a load (<NUM>);
a FET (<NUM>) connected in series between the converter (<NUM>) and the load (<NUM>);
a current detector (<NUM>) including a current detection unit (Rs) configured to detect current flowing between the converter (<NUM>) and the load (<NUM>);
a droop characteristic controller (<NUM>) configured to cause output voltage of the converter (<NUM>) to droop at a droop rate determined based on a magnitude of load current flowing from the converter (<NUM>) towards the load (<NUM>); and
a reverse current limitation unit (U13A) configured to limit a reverse current flowing from the load (<NUM>) towards the converter (<NUM>) to be a reverse current limit or less by controlling a voltage between a gate and source of the FET (<NUM>);
wherein the droop rate when the load current is included in a first current section is greater than the droop rate when the load current is included in each of a second current section and a third current section;
wherein the FET (<NUM>) is configured to control the current outputted from the converter (<NUM>) based on a signal outputted by the current detector (<NUM>);
wherein the second current section includes current that is smaller than current included in the first current section; and
wherein the third current section includes current that is larger than the current included in the first current section.