Patent Description:
A FD transceiver utilizes the same time-frequency resource units for signal transmission (TX) and signal reception (RX). In the context of data communication (either wireless or wire-based), the FD transceiver is capable of achieving higher spectral efficiency than a Half-Duplex (HD) transceiver due to HD orthogonal use of resources for the TX and RX, as is the case for Time Division Duplex (TDD) or Frequency Division Duplex (FDD). In the context of radar technology, the FD transceiver may be used as a continuous wave radar, which is an alternative to a pulse wave radar. Furthermore, FD transceivers may also be used for joint wireless data communication and sensing, and this joint functionality is of increasing interest as frequency resources become scarcer and more sensing capabilities are required for next-generation applications of wireless devices.

At the same time, the main bottleneck for the implementation of FD transceivers is a quantization noise due to a SI. Given that the TX and RX are performed simultaneously, the FD transceiver is interfered by its own transmitted signal which propagates to a receiver of the FD transceiver via a SI channel. Consequently, a signal received at the FD transceiver has an undesired component due to the SI plus a desired component, i.e. the Sol.

The existing solutions for the problem of Sol degradation due to the presence of the SI may be classified in the following three categories: TX and RX path isolation, analog SI cancellation, and digital SI cancellation. All these categories of the existing solutions are aimed at mitigating or cancelling the SI such that a SI power at the receiver of the FD transceiver is reduced. However, the TX and RX path isolation, the analog SI cancellation, and the digital SI cancellation, as used individually or in any combination, do not efficiently deal with the Sol degradation caused by the presence of the SI.

<CIT> describes a method, apparatus, and computer program product to reduce self-interference in a transceiver. In the context of a method, a self-interference channel estimate may be determined. A reconstructed interference may further be determined based at least in part on the self-interference channel estimate and a signal to be transmitted and the reconstructed self-interference is caused to be subtracted from a received signal.

<CIT> describes a method for digital self-interference cancelation, including receiving inputs, transforming the inputs, generating outputs based on the transformed inputs, transforming the outputs, and/or generating a cancellation signal based on the outputs.

<CIT> describes an in-band Full-Duplex (FD) transceiver and a corresponding method. The FD transceiver comprises a transmitter and a receiver. It further comprises. The FD transceiver also comprises a converter configured to digitalize at least two analog reference signals and an analog receive signal of the receiver, and a digital canceller configured to generate a cancellation signal based on the at least two digitalized analog reference signals.

The present invention is defined by the features disclosed in the independent claims. Additional embodiments are defined in the dependent claims. This summary is not intended to identify key features of the present disclosure, nor is it intended to be used to limit the scope of the present disclosure.

It is an objective of the present disclosure to provide a FD transceiver architecture that enables efficient SI cancellation in a received signal comprising a Sol and a SI.

The objective is achieved by the features of the independent claims in the appended claims. Further embodiments and examples are apparent from the dependent claims, the detailed description, and the accompanying drawings.

According to a first aspect, a FD transceiver is provided. The FD transceiver comprises an analog front-end, a variable gain amplifier, a modulo-based Analog-to-Digital Converter (ADC), and a digital canceller. The analog front-end is configured to receive an analog signal comprising a Sol and a SI. The variable gain amplifier is configured to amplify the analog signal based on a gain parameter. The modulo-based ADC is configured to generate a digital signal based on the amplified analog signal. As a result of a modulo-based analog-to-digital conversion operation, the digital signal is a folded and quantized representation of the amplified analog signal. The digital canceller is configured to estimate the SI in the digital signal based on one or more reference signals, and to obtain a digital representation of the Sol based on the digital signal and the estimated SI. An advantage of the FD transceiver according to the first aspect comes from the fact that the modulo-based ADC used in the FD transceiver according to the first aspect does not suffer from a saturation problem inherent in conventional ADCs, since the received (FD) analog signal is folded via a modulo operation before quantization to match an input range of a quantizer used in the modulo-based ADC. Consequently, the variable gain parameter may be set such that quantization levels of the quantizer are better adapted to the Sol instead of being adapted to the received analog signal (including the SI). Furthermore, the SI estimation and cancellation may be fully performed in a digital domain, whereupon the state-of-the-art analog SI cancellation and/or isolation techniques are not required, thereby avoiding their drawbacks and limitations. In fact, under ideal operating conditions, i.e. when the SI may be perfectly estimated, the FD transceiver according to the first aspect incurs almost no Sol degradation due to the presence of the SI.

In one embodiment of the first aspect, the modulo-based ADC is configured to generate the digital signal by transforming the amplified analog signal into a phase-domain signal which is folded every 2π radians, and by quantizing the phase-domain signal. By so doing, it is possible to implement the modulo-based analog-to-digital conversion operation on the received analog signal, which results in its folded and quantized representation (i.e. the digital signal).

In another embodiment of the first aspect, the modulo-based ADC is configured to generate the digital signal by applying an incremental fold counter to the amplified analog signal. By so doing, it is possible to implement the modulo-based analog-to-digital conversion operation on the received analog signal, which results in its folded and quantized representation (i.e. the digital signal).

In another embodiment of the first aspect, the modulo-based ADC comprises one or more voltage-controlled oscillator-based ADCs (e.g., ring oscillator-based ADCs). By using the voltage-controlled oscillator-based ADCs, it is possible to implement the modulo-based analog-to-digital conversion operation on the received analog signal, which results in its folded and quantized representation (i.e. the digital signal).

In one embodiment of the first aspect, the one or more reference signals comprise one or more analog and/or digital signals sent from the analog front-end. By using such reference signals, it is possible to increase the efficiency of the SI estimation.

In one embodiment of the first aspect, the FD transceiver further comprises a memory configured to store the one or more reference signals. By using this memory, it is possible to select (with greater efficiency) which of the reference signals previously sent from the analog front-end are to be used for the SI estimation.

In one embodiment of the first aspect, the memory storing the reference signals is configured as a First-In First-Out (FIFO) buffer (e.g., a FIFO circular buffer). By storing the reference signals on a FIFO basis, it is possible to provide their easy and convenient manipulation in future, i.e. when estimating the SI.

In one embodiment of the first aspect, the digital canceller is configured to apply an adaptive filter to estimate the SI in the digital signal based on the one or more reference signals. By using the adaptive filter, it is possible to estimate the SI in the digital signal more efficiently.

In one embodiment of the first aspect, the adaptive filter applied by the digital canceller is based on one of a least-mean-square (LMS) algorithm, a normalized LMS algorithm, a leaky LMS algorithm, and a recursive least square algorithm. This may make the FD transceiver according to the first aspect more flexible in use.

In another embodiment of the first aspect, the digital canceller is further configured to apply a machine-learning algorithm to estimate the SI in the digital signal based on the one or more reference signals. By using the machine-learning algorithm, it is possible to estimate the SI in the digital signal more efficiently.

In one embodiment of the first aspect, the FD transceiver further comprises a gain control unit configured to tune the gain parameter of the variable gain amplifier based on at least one of the estimated SI, the digital representation of the Sol, and the one or more reference signals. By so doing, it is possible to provide dynamic adaptation of the gain parameter of the variable gain amplifier, thereby resulting in the proper amplification of received analog signals.

According to a second aspect, a method for operating a FD transceiver is provided. The method starts with the step of receiving an analog signal. The analog signal comprises a Sol and a SI. Then, the method proceeds to the step of amplifying the analog signal based on a gain parameter. After that, the method goes on to the step of generating a digital signal based on the amplified analog signal. The digital signal is obtained by performing a modulo-based analog-to-digital conversion operation on the amplified analog signal, for which reason the digital signal is represented by a folded and quantized representation of the amplified analog signal. The method further proceeds to the steps of estimating the SI in the digital signal based on one or more reference signals and obtaining a digital representation of the Sol based on the digital signal and the estimated SI. By so doing, it is possible to provide efficient SI estimation and cancellation. Moreover, since the SI estimation and cancellation are performed in the digital domain, the state-of-the-art analog SI cancellation and/or isolation techniques are not required, thereby avoiding their drawbacks and limitations. In fact, under ideal operating conditions, i.e. when the SI may be perfectly estimated, it is possible to avoid Sol degradation due to the presence of the SI.

In one embodiment of the second aspect, the step of generating the digital signal comprises transforming the amplified analog signal into a phase-domain signal that is folded every 2π radians, and generating the digital signal by quantizing the phase-domain signal. By so doing, it is possible to implement the modulo-based analog-to-digital conversion operation on the received analog signal, which results in its folded and quantized representation (i.e. the digital signal).

In another embodiment of the second aspect, the step of generating the digital signal comprises generating the digital signal by applying an incremental fold counter to the amplified analog signal. By so doing, it is possible to implement the modulo-based analog-to-digital conversion operation on the received analog signal, which results in its folded and quantized representation (i.e. the digital signal).

In another embodiment of the second aspect, the step of generating the digital signal comprises generating the digital signal by using one or more voltage-controlled oscillators. By so doing, it is possible to implement the modulo-based analog-to-digital conversion operation on the received analog signal, which results in its folded and quantized representation (i.e. the digital signal).

In one embodiment of the second aspect, the one or more reference signals comprise one or more analog and/or digital signals sent from the FD transceiver. By using such reference signals, it is possible to increase the efficiency of the SI estimation.

In one embodiment of the second aspect, the step of estimating the SI in the digital signal is performed by using an adaptive filter. By using the adaptive filter, it is possible to estimate the SI in the digital signal more efficiently.

In one embodiment of the second aspect, the adaptive filter is based on one of a least-mean-square (LMS) algorithm, a normalized LMS algorithm, a leaky LMS algorithm, and a recursive least square algorithm. This may make the method according to the second aspect more flexible in use.

In another embodiment of the second aspect, the step of estimating the SI in the digital signal is performed by using a machine-learning algorithm. By using the machine-learning algorithm, it is possible to estimate the SI in the digital signal more efficiently.

In one embodiment of the second aspect, the method further comprises the step of tuning the gain parameter based on at least one of the estimated SI, the digital representation of the Sol, and the one or more reference signals. By so doing, it is possible to provide dynamic adaptation of the gain parameter of the variable gain amplifier, thereby resulting in the proper amplification of received analog signals.

According to a third aspect, a computer program product is provided. The computer program product comprises a computer-readable storage medium storing a computer code which, when executed by a processor of a FD transceiver, causes the FD transceiver to perform the method according to the second aspect. By using such a computer program product, it is possible to simplify the implementation of the method according to the second aspect in any FD transceiver, like the FD transceiver according to the first aspect.

Other features and advantages of the present disclosure will be apparent upon reading the following detailed description and reviewing the accompanying drawings.

The present disclosure is explained below with reference to the accompanying drawings, in which:.

Various embodiments of the present disclosure are further described in more detail with reference to the accompanying drawings. However, the present disclosure may be embodied in many other forms and should not be construed as limited to any certain structure or function discussed in the following description. In contrast, these embodiments are provided to make the description of the present disclosure detailed and complete.

According to the detailed description, it will be apparent to the ones skilled in the art that the scope of the present disclosure encompasses any embodiment thereof, which is disclosed herein, irrespective of whether this embodiment is implemented independently or in concert with any other embodiment of the present disclosure. For example, the apparatus and method disclosed herein may be implemented in practice by using any numbers of the embodiments provided herein. Furthermore, it should be understood that any embodiment of the present disclosure may be implemented using one or more of the features presented in the appended claims.

The word "exemplary" is used herein in the meaning of "used as an illustration". Unless otherwise stated, any embodiment described herein as "exemplary" should not be construed as preferable or having an advantage over other embodiments.

According to the embodiments disclosed herein, a Full-Duplex (FD) transceiver refers to a transceiver that utilizes the same time-frequency resources for signal transmission (TX) and reception (RX). It should be noted that the signal TX and RX may be performed concurrently via either wireless or wire-based communications, for which reason each mention of analog signals transmitted and received at the FD transceiver should be construed herein as relating to the analog signals transmitted and received via any suitable wireless or wire-based communications. The FD transceiver may be implemented as an individual communication device or as part of a user equipment (UE). The UE may refer to a mobile device, a mobile station, a mobile terminal, a subscriber unit, a mobile phone, a cellular phone, a smart phone, a cordless phone, a personal digital assistant (PDA), a wireless communication device, a desktop computer, a laptop computer, a tablet computer, a gaming device (e.g., a gaming console, a gaming controller, etc.), a netbook, a smartbook, an ultrabook, a medical device or medical equipment, a biometric sensor, a wearable device (e.g., a smart watch, smart glasses, a smart wrist band, etc.), an entertainment device (e.g., an audio player, a video player, etc.), a vehicular component or sensor, a smart meter/sensor, an unmanned vehicle (e.g., an industrial robot, a quadcopter, etc.), industrial manufacturing equipment, a global positioning system (GPS) device, an Internet-of-Things (IoT) device, a machine-type communication (MTC) device, a group of Massive IoT (MloT) or Massive MTC (mMTC) devices/sensors, or any other suitable device configured to support wireless or wire communications. In some embodiments, the UE may refer to at least two collocated and inter-connected UEs thus defined.

<FIG> shows a block diagram of a conventional FD transceiver <NUM> for concurrently transmitting and receiving data via analog signals over the same time-frequency resources. To perform the concurrent signal TX and RX, the FD transceiver <NUM> comprises a transmitting antenna <NUM> and a receiving antenna <NUM>. The FD transceiver <NUM> further comprises an analog front-end <NUM> for different analog signal processing, a Digital Signal Processing (DSP) unit <NUM> for different digital signal processing, a Digital-to-Analog Converter (DAC) <NUM> and an Analog-to-Digital Converter (ADC) <NUM> which are both arranged between the analog front-end <NUM> and the DSP unit <NUM>, and a variable gain amplifier <NUM> which applies a certain gain parameter to received analog signals. The gain parameter is selected such that it adapts a power of a received analog signal to a dynamic range of the ADC <NUM>.

The main bottleneck for the implementation of the FD transceiver <NUM> is a quantization noise that occurs due to a Self-Interference (SI). Due to the concurrent signal TX and RX, the FD transceiver <NUM> is interfered by its own transmitted signal which goes out of the transmitting antenna <NUM> and propagates to the receiving antenna <NUM> via a SI channel <NUM>. Consequently, the analog signal received at the receiving antenna <NUM> of the FD transceiver <NUM> has an undesired component due to the SI plus a desired component that is called a Signal of Interest (Sol) coming from a remote transmitter.

Let us use za(t) and xa(t) to denote the SI and Sol, respectively, at the input of the variable gain amplifier <NUM>, and g to denote the gain parameter of the variable gain amplifier <NUM>. Thus, at the input of the ADC <NUM>, the contribution of the SI is given by gza(t) with power g<NUM>PSI and the contribution of the Sol is given by gxa(t) with power g<NUM>PSoI. Since these SI and Sol are dominant signals at the receiving antenna <NUM> (e.g., they are stronger than a thermal noise), then an approximation of the received analog signal at the input of the ADC <NUM> is given by <MAT>.

In practice, PSI is larger than PSoI because the distance traveled by the SI is shorter than the distance traveled by the Sol. The ADC <NUM> applies a sampling operation (i.e. continuous-to-discrete time conversion) and a quantization operation (i.e. continuous-to-digital voltage level conversion), and the output of the ADC <NUM> is as follows: <MAT> where ℓ denotes the ℓ-th sample, Qb() is the quantization function with a resolution of b bits, and Ts is the sampling period or inverse of a sampling frequency fs, i.e. Ts = <NUM>/fs. It should be noted that the sampling operation is inherent in all ADCs, and each ADC which will be further mentioned herein should be construed as performing the sampling operation even if there is no explicit indication thereto.

<FIG> shows a block diagram of the FD transceiver <NUM>, in which the DSP unit <NUM> is implemented as a combination of a TX and RX DSP subunit <NUM> and a digital canceller <NUM>. The TX and RX DSP subunit <NUM> is responsible for different digital signal processing, while the digital canceller <NUM> is configured to perform digital SI estimation and cancellation based on different digital and/or analog input references. Given such arrangement of the digital canceller <NUM>, and assuming that the digital canceller <NUM> has perfect knowledge of the quantized SI given by Qb(gza(ℓTs)), then, after the perfect digital cancellation of the SI, one can obtain the following digital representation or estimate of the Sol: <MAT> and the quantization noise nQ[ℓ] for the Sol, i.e. the noise or error in representing gxa(ℓTs) by using x̂d[ℓ], given by <MAT>.

The quantization noise nQ[ℓ] is a function of the gain parameter g and the quantization function Qb() which are fixed before the digital SI cancellation. Since g is set as function of za(t) + xa(t) such that g(za(t) + xa(t)) would ideally span all the quantization levels of the ADC <NUM> (while avoiding saturation) and since the amplitude of za(t) is larger than the amplitude of xa(t) , then, as a result, gza(t) spans most of the quantization levels of the ADC <NUM>, while leaving few levels of quantization for gxa(t). In summary, the small amplitude of gxa(t) results in gxa(t) spanning few levels of quantization of the ADC <NUM>, and this leads to the large quantization noise nQ[ℓ] for the Sol due to the SI. Thus, the quantization noise nQ[ℓ] cannot be removed even after the perfect digital SI cancellation.

<FIG> shows a graphical description of the quantization noise nQ[ℓ] due to the SI. For the sake of simplicity, the SI and Sol are shown with different frequencies, but they may be of the same frequency in the FD transceiver <NUM>. At first, the amplified SI and Sol, i.e. gza(t) and gxa(t), respectively, are fed as their sum, i.e. ra(t), to the input of the ADC <NUM> (see <FIG>: the picture on the left). The ADC <NUM> then converts ra(t) to rd[ℓ], as defined above (see <FIG>: the picture in the middle). The digital canceller <NUM> is assumed to perform the perfect digital SI estimation and cancellation, and outputs the digital estimate x̂d[ℓ] of the Sol (see <FIG>: the picture on the right). Note that, even after the perfect digital SI cancellation, the resulting signal x̂d[ℓ] represents a poorly quantized version of the Sol, i.e. gxa(ℓTs). Consequently, the quality of the Sol after the ADC <NUM> is degraded due to the quantization noise nQ[ℓ] caused by the presence of the SI in the received analog signal.

<FIG> shows a Signal to Quantization Noise Ratio (SQNR) as function of the inverse of a Signal to Interference Ratio (SIR). The results in <FIG> have been obtained assuming the perfect digital SI cancellation, and the shown SQNR is the one observed at the output of the digital canceller <NUM> of the FD transceiver <NUM>. More specifically, the SQNR is given by <MAT> where PQ is the power of the quantization noise nQ[ℓ]. In turn, the SIR is given by <MAT>.

The dashed lines in <FIG> show the benchmark performance without the SI, i.e. where za(t) = <NUM> and g is based solely on xa(t), whereupon g adapts xa(t) to the input range of the ADC <NUM>. The solid lines in <FIG> show the performance with the SI. Hence, g adapts za(t) + xa(t) to the input range of the ADC <NUM>. The solid lines are shown as a function of increasing <NUM>/SIR (i.e. the power of za(t) increases with respect to the power of xa(t)). Note that the SQNR decreases as <NUM>/SIR increases. Hence, the larger SI leads to larger performance degradation in terms of the observed SQNR. This degradation in the SQNR, observed for all SIR values considered, is the main bottleneck in the implementation of FD transceivers.

In an attempt to solve the problem of the SQNR degradation (or, in other words, the Sol degradation) due to the presence of the SI, it has been previously proposed to use the following techniques: TX and RX path solation, or analog SI cancellation. These techniques are both aimed at mitigating or cancelling the SI such that the power of the SI is reduced respectively at the receiving antenna <NUM> or the variable gain amplifier <NUM> within the FD transceiver <NUM>.

By isolating TX and RX paths from each other, it is possible to reduce the received power of the SI, thereby resulting in a reduction of the quantization noise nQ[ℓ] that is due to the SI. However, two main issues caused by using such isolation are as follows: (<NUM>) a separate antenna architecture required for the isolation may not be feasible due to form-factor constraints of the FD transceiver <NUM>; and (<NUM>) the isolation is not effective in a multipath environment because the quantization noise due to the SI may not be reduced when the received SI has components that are due to reflections from surrounding objects.

The analog SI cancellation consists in subtracting, in an analog domain, an estimate of the SI signal from the received analog signal. Let us use <MAT> to denote the received SI in the analog RF domain and <MAT> to denote the estimate of <MAT>. The received analog signal is composed of the sum of the Sol <MAT> and the SI. Hence, the received analog signal after the analog SI cancellation is equal to <MAT>.

The main advantage of the analog SI cancellation is that the power of the SI is reduced before the variable gain amplifier <NUM>, and this reduces the quantization noise nQ[ℓ] due to the SI. However, two main issues peculiar to the analog SI cancellation solutions are as follows: (<NUM>) required analog processing may involve bulky or expensive components like analog delay lines, analog vector modulators and DACs; and (<NUM>) analog hardware constraints result in a limited amount of SI cancellation (~40dB). Consequently, the reduction in the quantization noise nQ[ℓ] due to the SI is also limited.

The digital SI cancellation (e.g., applied after the ADC <NUM>) is implemented by computing an estimate of the SI based on an analog or digital input reference and subtracting the estimate of the SI from the received analog signal. Digital cancellers are typically built as adaptive filters, which are well-known in the art. The goal of a digital canceller is to reduce the SI to a noise floor. The state-of-the-art digital cancellers may virtually remove all SI up to the noise floor, as long as the digital or analog input reference is free of noise, and if the received analog signal is only corrupted by white noise. If a quantization noise or non-linear effects are added to the received analog signal, the digital cancellers may lose performance.

Finally, the above-described three techniques for SI mitigation or cancellation may also be combined. However, even this combination does not efficiently solve the problem of the quantization noise due to the SI.

The exemplary embodiments disclosed herein provide a technical solution that allows mitigating or even eliminating the above-sounded drawbacks peculiar to the prior art. In particular, the technical solution disclosed herein addresses the problem of the quantization noise in FD operation by using, instead of a conventional ADC (like the ADC <NUM> in <FIG> and <FIG>), a modulo-based ADC in a FD transceiver architecture. The modulo-based ADC applies a modulo operation, before quantization, in order to fold a received and amplified analog signal such that the analog signal perfectly matches a quantizer input range. Thus, a digital signal obtained by the modulo-based ADC is a folded and quantized representation of the analog signal. The digital signal is then fed to a digital canceller that is configured to estimate the SI in the digital signal by using one or more reference signals and obtain a digital representation of the Sol based on the digital signal and the estimated SI. By so doing, it is possible to provide efficient SI estimation and cancellation. Moreover, since the SI estimation and cancellation are performed in the digital domain, the state-of-the-art analog SI cancellation and/or isolation techniques are not required, thus avoiding their drawbacks and limitations. In fact, under ideal operating conditions, i.e. when the SI may be perfectly estimated, it is possible to avoid Sol degradation due to the quantization noise caused by the presence of the SI in the received analog signal.

<FIG> shows a block diagram of a FD transceiver <NUM> in accordance with one exemplary embodiment. The FD transceiver <NUM> comprises the following constructive elements: a transmitting antenna <NUM>, a receiving antenna <NUM>, an analog front-end <NUM>, a DSP unit <NUM>, a DAC <NUM>, a modulo-based ADC <NUM>, a variable gain amplifier <NUM>, and a gain control unit <NUM>. As also shown in <FIG>, the DSP unit <NUM> comprises a TX and RX DSP subunit <NUM> and a digital canceller <NUM>. It should be noted that the number, arrangement and interconnection of the constructive elements constituting the FD transceiver <NUM>, which are shown in <FIG>, are not intended to be any limitation of the present disclosure, but merely used to provide a general idea of how the constructive elements may be implemented within the FD transceiver <NUM>. For example, the gain control unit <NUM> may be implemented as an individual constructive element of the FD transceiver <NUM> or as part of either the DSP unit <NUM> or the variable gain amplifier <NUM>. Furthermore, since the present disclosure is aimed at addressing the problem of the quantization noise due to the SI propagating via a SI channel <NUM> between the transmitting and receiving antennas <NUM> and <NUM>, further discussion will focus on those constructive elements of the FD transceiver <NUM> which are involved in the SI estimation and cancellation. Looking ahead, we note that those constructive elements are represented by the analog front-end <NUM>, the modulo-based ADC <NUM>, the variable gain amplifier <NUM>, the gain control unit <NUM>, and the digital canceller <NUM>.

The analog front-end <NUM> may be configured as one or more analog signal conditioning circuits (e.g., based on operational amplifiers, signal filters, signal splitters, etc.) intended for different analog signal processing. The modulo-based ADC <NUM> and the variable gain amplifier <NUM> may be implemented based on any suitable semiconductor technology, such, for example, as Complementary Metal-Oxide-Semiconductor (CMOS), Bipolar CMOS technology, etc..

The digital canceller <NUM> may be implemented by using a CPU, general-purpose processor, single-purpose processor, microcontroller, microprocessor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), digital signal processor (DSP), complex programmable logic device, etc. In some embodiments, the digital canceller <NUM> may be implemented as any combination of the aforesaid, e.g., as two or more microprocessors.

Let us now say a few words about modulo-based ADCs. The basic idea behind the modulo-based ADCs is to apply a modulo operation to an original analog signal such that the resulting folded signal perfectly matches the quantizer input range. Then, the original analog signal is reconstructed in the digital domain from modulo-reduced quantized samples by relying either on: (a) some correlation assumptions on the analog signal, or (b) some oversampling in a time domain or, in the case of multichannel analog-to-digital conversion, some increased dimensionality generated by creating multiple linear combinations of the analog signals and jointly using, for reconstruction, the outputs of multiple modulo-ADCs.

However, in terms of the FD operation, we are not interested in reconstructing the original analog signal, which in case of FD contains the Sol and the SI. Actually, analog-to-digital conversion in the FD operation differs from the conventional case by the fact that a part of the signal to be converted, i.e. the SI, is not (directly) required and is partially known. Given this particularity of the FD operation, the modulo-based ADC <NUM> is used in the FD transceiver <NUM> along with an appropriate reconstruction procedure described below.

Similar to the aforesaid for <FIG>, let us use za(t) and xa(t) to denote respectively the SI and the Sol at the input of the variable gain amplifier <NUM>. Thus, at the input of the modulo-based ADC <NUM>, the contribution of the SI is given by gza(t) with power g<NUM>PSI and the contribution of the Sol is given by gxa(t) with power g<NUM>PSoI. Since these are dominant signals at the RX chain of the FD transceiver <NUM> (e.g. stronger than a thermal noise), then an approximation of the amplified analog signal at the input of the modulo-based ADC <NUM> is given by <MAT>.

Let us, for example, assume that the modulo-based ADC <NUM> uses:.

It is worth noting that this is a conventional ADC which suffers from saturation effects whenever the input analog signal exceeds the input range [-λ/<NUM>,λ/<NUM>].

Given the assumptions above, the output of the modulo-based ADC <NUM> can be written as <MAT> where <MAT> , and <MAT> denotes the quantization noise, which is approximately uniformly distributed in [-µ/<NUM>, µ/<NUM>].

Let us further assume that the digital canceller <NUM> has perfect knowledge of the SI, i.e. zd[ℓ], so that it is possible to perform the perfect digital SI cancellation by exploiting the following commutative property of the modulo operator: <MAT> and, finally, the Sol is reconstructed as <MAT>.

By using the above-presented expression for rd[ℓ] together with the commutative property of the modulo operator, one can write x̂d[ℓ] as follows: <MAT> where xd[ℓ] = xa(ℓTs). Hence, whenever |gxd[ℓ] + nQ[ℓ]| ≤ λ/<NUM>, it holds that modλ(gxd[ℓ] + nQ[ℓ])= gxd[ℓ] + nQ[ℓ], and x̂d[ℓ] provides a successful digital reconstruction of the Sol and with the SQNR given by <MAT> which is independent of the power PSI of SI. In consequence, it is possible to set the variable gain parameter g only as a function of PSoI and maximize the SQNR as long as it is guaranteed that <MAT>.

In practice, this results in negligible SQNR degradation with respect to the case in which the Sol gxd(t) could be directly quantized.

<FIG> shows the SQNR as function of <NUM>/SIR = PSI/PSoI, as obtained when assuming that the SI is perfectly estimated in the FD transceiver <NUM>. The dashed lines in <FIG> show the benchmark performance without the SI for different bits of quantization. The solid lines in <FIG> show the performance with the SI for the same bits of quantization. The <NUM> dB loss with respect to the benchmark SQNR is independent from the SI power and comes from the necessity of guaranteeing the condition Pr(|gxd[ℓ] + nQ[ℓ]| ≤ λ/<NUM>) ≈ <NUM>. One can see that the FD transceiver <NUM> outperforms the state-of-the-art FD transceivers in the high <NUM>/SIR region (see <FIG>) without requiring any analog SI cancellation and isolation technique.

<FIG> shows a flowchart of a method <NUM> for operating the FD transceiver <NUM> in accordance with one exemplary embodiment. In general, the method <NUM> describes the operation of the FD transceiver <NUM> in terms of the SI estimation and cancellation. The method <NUM> starts with a step S802, in which the analog front-end <NUM> receives an analog signal comprising a Sol and a SI. The analog front-end <NUM> may receive the analog signal directly (if the analog signal is transmitted via wire-based communications) or with the aid of the receiving antenna <NUM> (if the analog signal is transmitted via wireless communications). The analog front-end <NUM> is intended to perform the whole required analog processing of the analog signal, such, for example, as filtering, power amplification, low noise amplification, up- and down-conversion to and from a carrier signal, etc. Then, the method <NUM> proceeds to a step S804, in which the variable gain amplifier <NUM> amplifies the analog signal with a gain parameter, thereby outputting the amplified analog signal in the form of ra(t). The gain parameter is tuned by the gain control unit <NUM>. After that, the method <NUM> goes on to a step S806, in which the modulo-based ADC <NUM> generates, based on the amplified analog signal ra(t), a digital signal in the form of rd[ℓ]. The digital signal is obtained by performing a modulo-based analog-to-digital conversion operation on the amplified analog signal, for which reason the digital signal is represented by a folded and quantized representation of the amplified analog signal. In other words, the fact that the digital signal is generated as rd[ℓ] means that the amplified analog signal is subjected to the modulo-based analog-to-digital conversion operation in the FD transceiver <NUM>. The method <NUM> further proceeds to a step S808, in which the digital canceller <NUM> receives the digital signal rd[ℓ] and estimates the SI therein by using one or more reference signals, as will be described further in more detail. Further, a step S810 is initiated, in which the digital canceller <NUM> obtains a digital representation of the Sol, i.e. x̂d[ℓ], based on the digital signal and the estimated SI. The digital representation x̂d[ℓ] that is free of the SI may be then fed to the TX and RX DSP subunit <NUM> for further digital processing, if required.

In one exemplary embodiment, the modulo-based ADC <NUM> is configured to generate the digital signal rd[ℓ] in the step S806 of the method <NUM> by transforming the amplified analog signal ra(t) into a phase-domain signal which is folded every 2π radians (e.g., a phase-domain signal sin (ra(t))), and by quantizing the phase-domain signal. It should be noted that the quantized phase-domain signal may be further subjected to particular post-quantization processing, for example, to improve its linearity, if required.

In another exemplary embodiment, the modulo-based ADC <NUM> is configured to apply an incremental fold counter to the amplified analog signal ra(t) when generating the digital signal rd[ℓ] in the step S806 of the method <NUM>. In this exemplary embodiment, the modulo operation is implemented as the incremental fold counter that will take as input the analog signal ra(t) and output the signal r̃a(t) = ra(t) + k(t) * λ, where k(t) is the integer that represents the number of folds of the original analog signal. After a sample period Ts, the modulo-based ADC <NUM> will check whether <MAT>.

If this condition is verified, then it sets k(t + Ts) = k(t) ± <NUM> depending on the sign of ra(t + Ts). This operation corresponds to incrementing or decrementing the fold counter. The practical limitation of this fold counter is that it requires that |ra(t + Ts) - ra(t)| is bounded by λ since it is required to track at most <NUM> fold in the duration Ts. This may require a reduction in the sample period Ts.

In yet another exemplary embodiment, the modulo-based ADC <NUM> is configured as one or more voltage-controlled oscillator-based ADCs, such, for example, as ring oscillator-based ADCs, in order to generate the digital signal rd[ℓ] in the step S806 of the method <NUM>. A ring oscillator is a circular chain of inverter circuits, in which an output of each inverter in the chain is connected to an input of a next inverter in the chain. The inversion for all inverters is then controlled by the same input signal ra(t). When the inverters are wired in this way, the frequency of oscillation in the ring oscillator will be a function of the input signal ra(t) and it will generate a frequency modulated signal. Such a circuit has been long used for generating such frequency modulated signals, for example, for frequency modulated radio diffusion, but it can be repurposed as a modulo operator for the modulo-based ADC <NUM>.

As noted above, the digital canceller <NUM> performs the following two functions: it estimates the SI from the digital signal rd[ℓ] and removes the estimated SI from the digital signal rd[ℓ], using one or more reference signal(s) with the final objective of providing the digital representation x̂d[ℓ] of the Sol in the step S810 of the method <NUM>. Doing so, the digital canceller <NUM> exploits the commutative property of the modulo operator to account for the effect of the modulo-based analog-to-digital conversion on the received analog signal. In the embodiments disclosed herein, the digital canceller <NUM> is an evolution of the state-of-the-art techniques adapted with necessary algorithmic steps to handle the modulo operation included in the modulo-based analog-to-digital conversion.

The reference signals may comprise reference symbols representative of analog and/or digital signals that have been sent from the analog front-end <NUM>. In one exemplary embodiment, the FD transceiver <NUM> may further comprise a memory configured to store the reference signals or symbols. This memory may be implemented as a FIFO circular buffer of length N. Let us denote each of these reference symbol as u[ℓ - n], where ℓ is the index of the received reference symbol, and n is the offset of the reference symbol in the past. A vector of reference symbols is then <MAT>.

To keep the vector of length N, one should pop the oldest reference value from u[ℓ] from the back of the vector and insert the newest reference value from the front. A digital SI cancellation algorithm is used to find a function of u[ℓ] that best estimates the SI zd[ℓ]. This is typically done through an adaptive filter. The cancellation is done through a set of weights denoted by w[ℓ], so that the SI zd[ℓ] is estimated by ẑd[ℓ] as <MAT>.

There is a multitude of ways to iteratively update the weights w[ℓ] to improve the performance of the digital SI cancellation algorithm.

In one exemplary embodiment, the adaptive filter used by the digital canceller <NUM> may be based on a normalized least-mean-square (NLMS) algorithm. An estimation error may be successively computed as <MAT> and the adaptive filter may be iteratively updated as <MAT> when the adaptive filter is applied to real signals as is the case, for example, when processing separately in-phase and quadrature components of a signal. The choice of the gain parameter g is important for the convergence and behavior of the NLMS algorithm. The gain control unit <NUM> used for this purpose will be described further in detail.

It should be noted that the present disclosure is not limited to the NLMS algorithm - in some exemplary embodiment, the adaptive filter may be based on one of an LMS algorithm, a leaky LMS algorithm, a recursive least squares algorithm, etc. Moreover, the algorithm which the adaptive filter is based on may be adapted to any number of digital and/or analog reference signals. On top of that, in another exemplary embodiment, the digital canceller <NUM> is configured to apply, instead of the adaptive filter, a machine-learning algorithm (e.g., neural networks) to estimate the SI in the digital signal rd[ℓ] by using the reference signals.

<FIG> shows how the digital canceller <NUM> may be implemented in the FD transceiver <NUM> in accordance with one exemplary embodiment. As shown in <FIG>, the digital canceller <NUM> uses an adaptive filter <NUM> that receives a digital reference signal through digital means of the FD transceiver <NUM>, i.e. from the TX and RX DSP subunit <NUM>. Further digital SI cancellation may be performed as discussed above.

<FIG> shows how the digital canceller <NUM> may be implemented in the FD transceiver <NUM> in accordance with another exemplary embodiment. As shown in <FIG>, the digital canceller <NUM> uses an adaptive filter <NUM> that receives an analog reference signal through an auxiliary RX chain <NUM> of the analog front-end <NUM>, which in turn is coupled to a TX chain <NUM> of the analog front-end <NUM>. The digital canceller <NUM> further uses an ADC <NUM> to perform an analog-to-digital conversion operation on the analog reference signal. Further digital SI cancellation for the analog signal received through a RX chain <NUM> of the analog front-end <NUM> may be performed as discussed above.

<FIG> shows how the digital canceller <NUM> may be implemented in the FD transceiver <NUM> in accordance with another exemplary embodiment. As shown in <FIG>, the digital canceller <NUM> uses a set of adaptive filters <NUM>-<NUM>, <NUM>-<NUM>,. <NUM>-n that receive multiple delayed analog reference signals from a TX chain <NUM> of the analog front-end <NUM>. The digital canceller <NUM> further uses a set of ADCs <NUM>-<NUM>, <NUM>-<NUM>,. <NUM>-n for the adaptive filters <NUM>-<NUM>, <NUM>-<NUM>,. <NUM>-n, respectively, to perform the analog-to-digital conversion operation on the delayed analog reference signals. Further digital SI cancellation for the analog signal received through a RX chain <NUM> of the analog front-end <NUM> may be performed as discussed above.

Turning back to <FIG>, the gain control unit <NUM> is configured to tune the gain parameter g of the variable gain amplifier <NUM> based on at least one of the estimated SI (i.e. zd[ℓ]), the digital representation of the Sol (i.e. x̂d[ℓ]), and the reference signals used by the digital canceller <NUM>. By so doing, it is possible to provide dynamic adaptation of the gain parameter g of the variable gain amplifier <NUM>, thereby resulting in the proper amplification of received analog signals. In the meantime, the gain parameter g is to be set such that the effect of the quantization noise nQ [ℓ] on the Sol is reduced, while guaranteeing that the digital canceller <NUM> performs as expected.

For this purpose, it is required to set the gain parameter g to its highest possible value in order to maximize the SQNR. Simultaneously, it is required to guarantee that the digital canceller <NUM> operates at such g. Hence, in a preferred embodiment, the gain parameter g is chosen at time instant ℓ based on the above-mentioned feedback information from the digital canceller <NUM> as the highest g verifying <MAT> for some small ε > <NUM>. In formal terms, this means that one should choose g so that the error left after estimating the SI gẑd[ℓ] is close to the Sol plus the quantization noise term nQ[ℓ] with high probability.

In another embodiment, the gain parameter g may be fixed and set so that the average received signal power verifies <MAT> where B > <NUM> is a backoff value used to allow some margin for proper operation of the FD transceiver <NUM>.

While working, the above solution with fixed gain parameter g suffers from the fact that the digital SI cancellation algorithm breaks down for higher values of <NUM>/SIR, i.e. PSI/PSoI. Thus, the gain parameter ginitial has to be set so that <MAT> and the digital SI cancellation algorithm may perfectly recover the weights needed to remove the SI. Once this step is over, one can set the gain parameter gfinal as <MAT> with the final backoff Bfinal > <NUM> set to a low value, for example, <NUM> dB. In this case, the gain control unit <NUM> switch between g[ℓ] = ginitial when ℓ ≤ L and g[ℓ] = gfinal if ℓ > L. By so doing, it is possible to improve the results from the approach with the fixed gain parameter, as shown in <FIG> (where L = <NUM> samples). The implementation of the FD transceiver using the modulo-based ADC <NUM> manages to achieve perfect recovery with a resolution of <NUM> bits up to a ratio PSI/PSoI of <NUM> dB, and <NUM> dB for a resolution of <NUM> bits.

Although the FD transceiver <NUM> provides the efficient digital SI cancellation without having to use any analog SI cancellation and isolation technique, it still could be combined with these techniques, if required. One example of such combination is shown in <FIG> where the FD transceiver <NUM> uses an analog canceller <NUM> in concert with the digital canceller <NUM>. The analog canceller <NUM> is arranged between a RX chain <NUM> of the analog front-end <NUM> and the receiving antenna <NUM>, and may receive digital and/or analog reference signals, for example, from a TX chain <NUM> of the analog front-end <NUM> to perform the analog SI cancellation. The residual SI is then cancelled in the digital canceller <NUM> in accordance with the method <NUM>.

It should be noted that each step or operation of the method <NUM>, or any combinations of the steps or operations, can be implemented by various means, such as hardware, firmware, and/or software. As an example, one or more of the steps or operations described above can be embodied by processor executable instructions, data structures, program modules, and other suitable data representations. Furthermore, the executable instructions which embody the steps or operations described above can be stored on a corresponding data carrier and executed by at least one process included in the FD transceiver <NUM>. This data carrier can be implemented as any computer-readable storage medium configured to be readable by said at least one processor to execute the processor executable instructions. Such computer-readable storage media can include both volatile and nonvolatile media, removable and non-removable media. By way of example, and not limitation, the computer-readable media comprise media implemented in any method or technology suitable for storing information. In more detail, the practical examples of the computer-readable media include, but are not limited to information-delivery media, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile discs (DVD), holographic media or other optical disc storage, magnetic tape, magnetic cassettes, magnetic disk storage, and other magnetic storage devices.

Claim 1:
A full-duplex (FD) transceiver (<NUM>) comprising:
an analog front-end (<NUM>) configured to receive an analog signal, the analog signal comprising a signal of interest (Sol) and a self-interference (SI);
a variable gain amplifier (<NUM>) configured to amplify the analog signal based on a gain parameter;
a modulo-based analog-to-digital converter (ADC) (<NUM>) configured to generate a digital signal based on the amplified analog signal, the digital signal being a folded and quantized representation of the amplified analog signal, wherein the modulo-based ADC (<NUM>) is configured to apply a modulo operation, before quantization, to fold the amplified analog signal such that the analog signal matches an input range of a quantizer used in the modulo-based ADC (<NUM>); and
a digital canceller (<NUM>) configured to:
estimate the SI in the digital signal based on one or more reference signals; and
obtain a digital representation of the Sol based on the digital signal and the estimated SI.