Patent Description:
For instance, one or more embodiments may be applied to detecting clipping of PWM signals in audio systems.

Clipping is a form of waveform distortion that limits a signal once it exceeds a certain threshold and may occur, for instance, when an amplifier is overdriven and attempts to deliver an output voltage or current beyond its maximum capability, i.e. when the amplifier is saturated.

In the case of PWM signals, clipping (also referred to as "saturation" in the present description) may result in a duty cycle which is close or equal to <NUM>% or <NUM>%.

Particularly in the case of audio systems comprising switching PWM modulators, the behavior of the audio system may be affected as a result of the PWM signal being saturated or almost saturated, i.e. when clipping may occur.

Therefore, detecting clipping phenomena of PWM signals may be relevant, insofar as detecting clipping may provide a way for recognizing saturation of the PWM signal and consequently triggering feedback devices and/or corrective techniques for limiting distortion effects on the output signal of the (audio) system.

Known solutions for detecting clipping of a PWM signal are based on counting "missing" pulses in the PWM signal generated by a PWM modulator circuit, as exemplified in <FIG>.

<FIG> is a circuit diagram exemplary of a PWM modulator circuit <NUM> and a clipping detection circuit <NUM> coupled thereto. The PWM modulator circuit <NUM> is configured to generate a PWM signal PWMout, and the clipping detection circuit <NUM> is configured to detect clipping (i.e., saturation) of the signal PWMout.

The PWM modulator circuit <NUM> comprises:.

As long as the modulation signal Vmod is comprised between an upper threshold Vtri,H and a lower threshold Vtri,L of the periodic carrier signal Vtri, the signal PWMout is not saturated (or clipped) and comprises a pulse, i.e. a pair of edges (one rising edge and one falling edge), at each period of the periodic carrier signal Vtri.

Conversely, as a result of the modulation signal Vmod being not comprised between the upper threshold Vtri,H and the lower threshold Vtri,L (i.e., Vmod being higher than Vtri,H or lower than Vtri,L), the output node of the comparator circuit <NUM> does not commute and the signal PWMout is saturated, i.e. the signal PWMout does not comprise edges and stays at a low logic level (as exemplified in <FIG>, when Vmod > Vtri,H) or at a high logic level.

Therefore, saturation (clipping) of signal PWMout can be detected by sensing the signal PWMout and detecting "missing" pulses therein by means of a clipping detection circuit <NUM>, i.e. detecting the absence of a pulse in the signal PWMout during at least one period of the periodic carrier signal Vtri.

In known solutions as exemplified in <FIG>, a clipping detection circuit <NUM> comprises an up-counter <NUM> (implemented, for instance, with one or more flip-flops) configured to receive the signal PWMout and a clock signal ClkPkTri.

The clock signal ClkPkTri is a clock signal synchronized with the periodic carrier signal Vtri. For instance, clock signal ClkPkTri may be synchronized with peaks and valleys of the periodic carrier signal Vtri, e.g., having a falling edge when the periodic carrier signal Vtri reaches the upper threshold Vtri,H and a rising edge when the periodic carrier signal Vtri reaches the lower threshold Vtri,L, as exemplified in <FIG>.

The signal PWMout is received at an (asynchronous) reset input R of the up-counter <NUM>, so that the up-counter <NUM> increases (e.g., by one unit) an internal count number at each period of the clock signal ClkPkTri (e.g., at each rising edge or falling edge of the clock signal ClkPkTri), with the internal count number being (asynchronously) reset to zero at each occurrence of a pulse in the signal PWMout.

The clipping detection circuit <NUM> therefore counts the number of consecutive missing pulses in the received signal PWMout, being a pulse expected at each period of the clock signal ClkPkTri if the signal PWMout is not saturated.

As a result of the count of consecutive missing pulses reaching a certain value n (e.g., n = <NUM>), an output signal ClipDet of the clipping detection circuit <NUM> is asserted (e.g., set to high, see instant t<NUM> in <FIG>), thereby indicating saturation of the signal PWMout.

In known solutions as exemplified in <FIG>, the clipping detection circuit <NUM> also comprises an internal logic reset circuit block (not visible in the Figures annexed herein) configured to de-assert (e.g., set to low) the output signal ClipDet at the first occurrence of a pulse in the signal PWMout after assertion of the saturation condition (see, for instance, instant t<NUM> in <FIG>), i.e. when the internal count number is reset to zero.

In this context, the U. Patent Application published as <CIT> discloses a PWM amplifier adapted to a class-D amplifier, where the PWM amplifier comprises a clipping detection circuit. The clipping detection circuit receives a clock signal having the same frequency as the PWM signal. The clock signal is supplied to the clock terminals of a first set of D flip-flops combined together to form a first shift register and to the clock terminals of a second set of D flip-flops combined together to form a second shift register. The PWM signal is supplied to the reset terminals of the D flip-flops in the first set, and an inverted replica of the PWM signal is supplied to the reset terminals of the D flip-flops in the second set. A signal indicative of a clipping condition is generated at the output of a NOR logic gate which combines the output signals of the first shift register and the second shift register. Thus, the signal indicative of clipping is asserted to indicate a clipping condition when the PWM signal is kept at a high level or at a low level for a certain number of consecutive clock periods, and it is de-asserted to indicate a non-clipping condition when an edge is detected in the PWM signal.

Patent Application published as <CIT> discloses a PWM differential amplifier comprising a clipping detection circuit configured to detect clipping of a first PWM signal and a second PWM signal. A signal indicative of a clipping condition is asserted when one or both of the PWM signals maintain a same value between two consecutive edges of the clock signal, and it is de-asserted when both the PWM signals change their value between the consecutive edges of the clock signal.

Despite the extensive activity in the area, further improved solutions are desirable.

For instance, solutions are desirable for increasing robustness of clipping detection circuits and methods for PWM signals against possible spurious commutations due to noise.

Additionally, solutions are desirable which may reduce instability of the output signal in clipping detection circuits for PWM signals, particularly in the case of PWM signals at relatively high frequency, e.g., higher than <NUM>.

The inventors have observed that the known solutions as exemplified in <FIG> are not suitable for use with PWM signals at relatively high frequency, e.g., at frequencies higher than <NUM>, since they may not be stable.

In particular, the inventors have observed that at a higher frequency the up-counter <NUM> in the clipping detection circuit <NUM> increases the internal count number at a faster rate, so that at low frequencies detection of clipping may take place unexpectedly soon also when the signal PWMout is not clipped, unless the value n is chosen high. Considering low-frequency signals such as <NUM> or lower, the clipping detection suffers from a longer time interval during which the PWM amplifier loses and acquires pulses (corresponding to an instability region of Class D amplifiers), caused by an intrinsic limitation of the smallest/biggest duty-cycle realized by the switching stage. This phenomenon worsens as a result of the frequency of the clock signal ClockPkTri increasing, e.g., increasing from <NUM> to <NUM>, causing the output signal ClipDet to switch ON/OFF many times.

Also, known solutions may suffer from the presence of noise in the modulation signal Vmod especially when the duty cycle of the signal PWMout is close to <NUM>% or <NUM>%, i.e. when the modulation signal Vmod is close to one of the upper threshold Vtri,H and the lower threshold Vtri,L of the periodic carrier signal Vtri. In these conditions, the signal PWMout may be rather unstable and have less regular pulses, so that also the output signal ClipDet may be affected by instability, e.g., comprising spurious commutations, with this issue being even more relevant in case of high switching frequencies such as, e.g., <NUM>.

An object of one or more embodiments is to contribute in providing such improved solutions.

According to one or more embodiments, such an object can be achieved by means of a circuit having the features set forth in claim <NUM> that follows.

According to one or more embodiments, such an object can be achieved by means of a corresponding electronic system according to claim <NUM>.

According to one or more embodiments, such an object can be achieved by means of a corresponding method according to claim <NUM>.

The claims are an integral part of the technical teaching provided herein in respect of the embodiments.

As mentioned above, various embodiments of the present disclosure relate to a clipping detector circuit.

In various embodiments, the clipping detector circuit is configured to detect clipping of a pulse-width modulated signal and comprises:.

wherein the clipping detector circuit is configured for generating at output a clipping detection signal indicative of whether the pulse-width modulated signal is clipped or not as a function of the first signal and the second signal, wherein the clipping detection signal is asserted in response to said first signal being asserted or said second signal being de-asserted, and the clipping detection signal is de-asserted in response to the first signal being de-asserted and the second signal being asserted.

In various embodiments, the clipping detector circuit comprises an OR logic gate configured to generate the output clipping detection signal by performing OR processing of the first signal and a complemented replica of the second signal.

Various embodiments relate to an electronic system comprising:.

Various embodiments relate to a method of detecting clipping of a pulse-width modulated signal by means of a circuit according to one or more embodiments or an electronic system according to one or more embodiments, the method comprising:.

Throughout the figures annexed herein, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for brevity.

The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

<FIG> is a flow chart exemplary of steps of a method of detecting clipping of a PWM signal according to one or more embodiments.

It will be understood that receiving the signals PWMout and ClkPkTri and generating the signal ClipDet' are actions which may be performed continuously according to the method, with the value of the output signal ClipDet' which may change at any point in time as a function of the signal PWMout.

In particular, after starting at a step <NUM>, the method comprises at a step <NUM> setting to a first (default) value the clipping detection signal ClipDet', the first value (e.g., ClipDet' = <NUM>, de-asserted) being indicative of the signal PWMout not being clipped and the switching PWM modulator operating in the so-called "linear region".

After setting the clipping detection signal ClipDet' to the first (default) value, the method comprises periodically checking, for instance at each period of the clock signal ClkPkTri (e.g., at each rising or falling edge thereof), whether the signal PWMout has had at least one voltage transition (e.g., one rising edge or one falling edge, also referred to as voltage commutation in the present disclosure) over a certain time period TMAX, as exemplified by block <NUM> in <FIG>. For instance, the time period TMAX may correspond to a certain number n (e.g., n = <NUM>) of the past (latest) periods of the clock signal ClkPkTri preceding the checking act <NUM>.

In case the signal PWMout has had at least one voltage transition over a time period TMAX preceding the checking act <NUM> (e.g., over n of the past periods of the clock signal ClkPkTri), corresponding to a positive outcome Y of block <NUM>, the value of the clipping detection signal ClipDet' is not changed (i.e., it is left with the first value indicative of the signal PWMout not being clipped) and the checking act <NUM> is repeated on the signal PWMout, e.g., at the next period of the clock signal ClkPkTri.

Therefore, if the signal PWMout has at least one voltage transition every time period TMAX (e.g., every n clock periods), it is detected as not clipped (saturated), and the method cyclically goes through steps <NUM> and <NUM>, periodically performing the checking act <NUM> (e.g., at each clock cycle) and leaving unchanged the value of the clipping detection signal ClipDet' as long as the outcome of the checking act <NUM> is positive, i.e. as long as the signal PWMout is not clipped.

In case the checking act <NUM> detects that the signal PWMout has not had at least one voltage transition over a time period TMAX preceding the checking act <NUM> (e.g., over n of the past latest periods of the clock signal ClkPkTri), corresponding to a negative outcome N of block <NUM>, the value of the clipping detection signal ClipDet' is changed (e.g., it is switched to a second value indicative of the signal PWMout being clipped and the switching PWM modulator operating in the so-called "clipping region") in an act exemplified by block <NUM>.

After setting the clipping detection signal ClipDet' to the second value, the method comprises again periodically checking, e.g., at each period of the clock signal ClkPkTri, whether the signal PWMout has had at least one voltage transition over a certain time period TMAX (e.g., again a certain number n of the past latest periods of the clock signal ClkPkTri), as exemplified by block <NUM> in <FIG>.

In case the signal PWMout has not had at least one voltage transition over the time period TMAX (e.g., over n of the past periods of the clock signal ClkPkTri), corresponding to a negative outcome N of block <NUM>, the value of the clipping detection signal ClipDet' is not changed (i.e., it is left with the second value indicative of the signal PWMout being clipped) and the checking act <NUM> is repeated on the signal PWMout, e.g., at the next period of the clock signal ClkPkTri.

Therefore, if the signal PWMout remains clipped (saturated) with no voltage transitions over a time period TMAX (e.g., n of the past periods of the clock signal ClkPkTri), the method cyclically goes through steps <NUM> and <NUM>, periodically performing the checking act <NUM> (e.g., at each clock cycle) and leaving unchanged the value of the clipping detection signal ClipDet' as long as the outcome of the checking act <NUM> is negative, i.e. as long as the signal PWMout is clipped.

In case the checking act <NUM> detects that the signal PWMout has had at least one voltage transition over a time period TMAX (e.g., n of the past periods of the clock signal ClkPkTri), corresponding to a positive outcome Y of block <NUM>, a further checking act <NUM> is performed.

The further checking act <NUM> comprises checking whether the signal PWMout has had at least a certain number m of pulses since the last occurrence of a negative outcome of the checking act <NUM>, i.e. since the last time the signal PWMout was found to be clipped (saturated).

In case the signal PWMout has not had a certain number m of pulses since the last occurrence of a negative outcome of the checking act <NUM> (negative outcome, N, of block <NUM>), the value of the clipping detection signal ClipDet' is not changed (i.e., it is left with the second value indicative of the signal PWMout being clipped) and the checking act <NUM> is repeated on the signal PWMout, e.g., at the next period of the clock signal ClkPkTri.

Therefore, even if the signal PWMout may have (temporarily) exited from the saturation/clipping condition (as indicated by the positive outcome of the checking act <NUM>), the clipping detection signal ClipDet' is de-asserted (only) as a result of the signal PWMout comprising at least a certain number m of pulses since the last voltage transition over a time period TMAX detected in the signal PWMout.

In case the checking act <NUM> detects that the signal PWMout has had a certain number m of pulses since the last occurrence of a negative outcome of the checking act <NUM> (positive outcome, Y, of block <NUM>), the value of the clipping detection signal ClipDet' is changed (e.g., it is switched to the first value indicative of the signal PWMout not being clipped) and the method may resume operation from step <NUM>.

Therefore, advantageously with respect to known solutions, a method as exemplified in <FIG> improves stability of the clipping detection signal ClipDet' in particular when the signal PWMout exits from the clipping condition, and/or in cases where the duty-cycle of signal PWMout is close to <NUM>% or <NUM>% (i.e., when signal PWMout is almost saturated and spurious commutations of the clipping detection signal ClipDet' may happen).

<FIG> is a circuit diagram exemplary of one or more embodiments suitable for implementing a method as exemplified with reference to <FIG>.

In <FIG>, the reference number <NUM> indicates a clipping detection circuit <NUM> configured to co-operate with a switching PWM modulator circuit <NUM>.

As previously discussed, the switching PWM modulator circuit <NUM> is configured to generate a pulse-width modulated signal PWMout by comparing a modulation signal Vmod with a periodic carrier signal Vtri (e.g., a triangular or saw-tooth signal).

The clipping detection circuit <NUM> comprises a first timer circuit <NUM> configured for monitoring whether the signal PWMout has had at least one voltage transition over a certain time period TMAX.

The timer circuit <NUM> is configured to sense (monitor) edges (rising and/or falling) of the signal PWMout and to assert (e.g., set to high) a respective output signal ClipDet as a result of a certain time period TMAX elapsing since the last occurrence of an edge in the signal PWMout, thereby indicating saturation of the signal PWMout.

Additionally, the timer circuit <NUM> is configured to de-assert the respective output signal ClipDet and to reset the internal timer as a result of an edge occurring in the signal PWMout.

The timer circuit <NUM> is implemented with a first up-counter <NUM> configured to receive the signal PWMout and a clock signal ClkPkTri.

Thus, in the presently considered embodiment, the signal PWMout is received at a reset input R of the up-counter <NUM>, so that the up-counter <NUM> periodically increases an internal count number (e.g., at each period of the clock signal ClkPkTri), with the internal count number being reset to zero at each occurrence of a pulse in the signal PWMout.

As a result of the count of consecutive missing pulses in the signal PWMout reaching a certain value n (e.g., n = <NUM>), the output signal ClipDet of the up-counter <NUM> is asserted (e.g., set to high), thereby indicating saturation of the signal PWMout.

In a preferred embodiment, the clock signal ClkPkTri is synchronized with the periodic carrier signal Vtri.

Additionally, a second up-counter <NUM> is provided in the clipping detection circuit <NUM>. The second up-counter <NUM> is configured to:.

In particular, the second up-counter <NUM> is configured to receive the output signal ClipDet from the timer circuit <NUM> at a respective asynchronous reset input, and to receive the signal PWMout as a clock signal.

Therefore, the second up-counter <NUM> increases (e.g., by one unit) a respective internal count number at each pulse occurring in the signal PWMout, with the respective internal count number being (asynchronously) reset to zero at each assertion of the signal ClipDet, i.e. when the signal PWMout is found to enter the clipping region.

The second up-counter <NUM> therefore counts the number of pulses in the received signal PWMout since the last de-assertion of the signal ClipDet.

As a result of the count of pulses in the received signal PWMout since the last de-assertion of the signal ClipDet reaching a certain value m (e.g., m = <NUM>), the output signal ClipOut of the second up-counter <NUM> is asserted (e.g., set to high).

Additionally, an output signal ClipDet' of the clipping detection circuit <NUM> may be generated at the output of an OR logic gate <NUM> which receives the signal ClipDet and a complemented replica of the signal ClipOut, as exemplified in <FIG>.

In one or more embodiments, a modulation signal Vmod may cause the switching PWM modulator circuit <NUM> to operate in linear region (i.e., with Vtri,L < Vmod < Vtri,H), resulting thereby in a pulse of the signal PWMout at each period of a clock signal ClkPkTri synchronized with the periodic carrier signal Vtri, or in saturation (clipping) region, resulting in a duty-cycle of the signal PWMout close to <NUM>% or <NUM>% and almost no pulses in the signal PWMout.

As a result of the switching PWM modulator circuit <NUM> operating in linear region, the first timer circuit <NUM> may be reset at each period of the clock signal ClkPkTri, thereby keeping the signal ClipDet de-asserted (i.e., ClipDet = <NUM>). Additionally, the second up-counter <NUM> does not get reset and provides a signal ClipOut asserted (i.e., ClipOut = <NUM>). As a result, the output clipping detection signal ClipDet' is de-asserted, i.e. kept at a low logic level indicative of the signal PWMout not being clipped.

As a result of the modulation signal Vmod decreasing below Vtri,L or increasing above Vtri,H, thereby causing the switching PWM modulator circuit <NUM> to start operating in clipping region, no pulses are generated in the signal PWMout.

In case no pulses are generated in the signal PWMout for a certain period of time TMAX, e.g., for a certain number n of consecutive periods of the clock signal ClkPkTri, the signal ClipDet is commuted to a high logic value, thereby causing also the clipping detection signal ClipDet' to commute to a high logic value and the internal counter of the second up-counter <NUM> to be reset to zero. The switching PWM modulator circuit <NUM> is detected as being operating in clipping region.

As long as no pulses are detected in the signal PWMout, the state of the clipping detection circuit <NUM> remains unaltered, with ClipDet = <NUM>, ClipOut = <NUM> and ClipDet' = <NUM>.

As a result of a pulse being detected in the signal PWMout, the counter of the first timer circuit <NUM> is reset to zero causing the signal ClipDet to commute to low. With ClipDet = <NUM>, the counter of the second up-counter <NUM> does not get reset and starts counting pulses in the signal PWMout.

The state of the circuit remains unaltered, with ClipDet = <NUM>, ClipOut = <NUM> and ClipDet' = <NUM>, until the counter of the second up-counter <NUM> reaches a certain value m. In such case (and provided that ClipDet stays at a low logic value) the signal ClipOut commutes to a high logic value, resulting in the output clipping detection signal ClipDet' commuting to a low logic value. Thus, the switching PWM modulator circuit <NUM> is detected as being operating again in linear region.

It will be noted that the signal ClipDet from the first timer circuit <NUM> being directly coupled to the OR logic gate <NUM> results in the output clipping detection signal ClipDet' commuting to high in any case as a result of n consecutive missing pulses being detected in the signal PWMout, independently from the value of the signal ClipOut.

<FIG> are exemplary of possible time behavior of signals in one or more embodiments, according to different operating status.

For instance, <FIG> is exemplary of a case wherein n = <NUM> and m = <NUM>. The switching PWM modulator circuit <NUM> initially operates in linear region, with the first timer circuit <NUM> being reset at each period of the clock signal ClkPkTri and resulting in ClipDet = <NUM>. The second up-counter <NUM> does not get reset and provides ClipOut = <NUM>. As a result, ClipDet' = <NUM>. As a result of the switching PWM modulator circuit <NUM> entering the clipping region, no pulses are generated in the signal PWMout. After n = <NUM> missing pulses in the signal PWMout, the signal ClipDet is commuted to a high logic value, thereby causing also the clipping detection signal ClipDet' to commute to a high logic value and the counter of the second up-counter <NUM> being reset to zero, resulting in ClipOut = <NUM>.

<FIG> is exemplary of a case wherein the switching PWM modulator circuit <NUM> initially operates in linear region with ClipDet = <NUM>, ClipOut = <NUM> and ClipDet' = <NUM>, then transitions to the clipping region with ClipDet = <NUM>, ClipOut = <NUM> and ClipDet' = <NUM> (i.e., the initial portion of the signals exemplified in <FIG> may correspond to the final portion of the signals exemplified in <FIG>).

As a result of a pulse P1 being detected in the signal PWMout, the counter of the first timer circuit <NUM> is reset to zero causing the signal ClipDet to commute to low. With ClipDet = <NUM>, the counter of the second up-counter <NUM> does not get reset and starts counting pulses in the signal PWMout, with ClipOut = <NUM>. As exemplified in <FIG>, the signal ClipOut is not commuted to high until the second up-counter <NUM> reaches the value m (e.g., m = <NUM>) (not visible in <FIG>).

As exemplified in <FIG> (again, the initial portion of the signals exemplified in <FIG> may correspond to the final portion of the signals exemplified in <FIG>), after the pair of pulses P1 and P2, the signal PWMout may not comprise other pulses for some time. In such case, if a number n (e.g., n = <NUM>) of clock cycles elapse after the pulse P2 without any additional pulse in the signal PWMout, the signal ClipDet commutes again to high. The signal ClipOut stays low and the signal ClipDet' stays high, so that pulses P1 and P2 are identified as spurious pulses and do not cause the signal ClipDet' to commute to low.

<FIG> (again, the initial portion of the signals exemplified in <FIG> may correspond to the final portion of the signals exemplified in <FIG>) is exemplary of a case wherein the switching PWM modulator circuit <NUM> initially operates in clipping region. As a result of a pulse P3 being detected in the signal PWMout, the counter of the timer circuit <NUM> is reset to zero causing the signal ClipDet to commute to low. With ClipDet = <NUM>, the counter of the second up-counter <NUM> does not get reset and starts counting pulses P3, P4, P5,. in the signal PWMout, with ClipOut = <NUM>. Once the second up-counter <NUM> reaches the value m (e.g., m = <NUM>), the signal ClipOut is commuted to high, determining a commutation to low of the signal ClipDet' which is indicative of the switching PWM modulator circuit <NUM> having exited from the clipping region.

One or more embodiments may thus be suitable for use in PWM-modulation based system wherein detection of a saturated PWM signal may trigger feedback systems and/or corrective and/or diagnostic circuits. This may be the case, for instance, of audio amplifiers as exemplified in <FIG>.

<FIG> is a circuit diagram of a PWM amplifier <NUM> exemplary of a possible context of use of a clipping detection circuit <NUM> according to one or more embodiments.

The PWM amplifier <NUM> is configured to receive an input analog signal Vin. The input analog signal Vin is propagated to an integrator circuit block <NUM>, thereby generating a modulation signal Vmod. As described in the foregoing, the modulation signal Vmod is compared to a triangular or saw-tooth signal Vtri in a comparator circuit <NUM>, thereby generating a PWM signal oscillating between values +Vsig and -Vsig. Such PWM signal is used for driving a PWM amplifier stage <NUM>, e.g., a half-bridge arrangement, to generate an output PWM signal oscillating between values +Vpot and -Vpot. The output PWM signal is thus propagated through an LC filter block <NUM>, thereby providing an output signal K·Vin which is an amplified replica of the input analog signal Vin. A feedback network <NUM> with a gain factor <NUM>/K is also provided between the output of the PWM amplifier stage <NUM> and the input of the integrator circuit block <NUM>.

As exemplified in <FIG>, a clipping detection circuit <NUM> receives the signal PWMout generated at the output of the comparator circuit <NUM> and a clock signal ClkPkTri, possibly synchronized with the signal Vtri, to generate a clipping detection signal ClipDet'. For instance, the clipping detection signal ClipDet' may be received at a processing and/or control unit <NUM> (e.g., a microprocessor) which may use ClipDet' as a sort of interrupt signal and/or as a control signal for triggering feedback and/or corrective devices for limiting distortion effects on the output signal K·Vin of the PWM amplifier <NUM>.

One or more embodiments may advantageously be employed with high frequency (e.g., <NUM>) switching PWM modulators.

One or more embodiments may facilitate generating an output clipping detection signal ClipDet' which is stable and without spurious commutations or glitches due to the high frequency involved, and which is robust against oscillations and/or noise in the modulation signal Vmod.

One or more embodiments may facilitate monitoring pulses in the signal PWMoul in real time and independently from the clock signal.

One or more embodiments may be tunable and/or adjustable, e.g., by tuning and/or adjusting the threshold values n and m of the first and second up-counters <NUM>, <NUM>, thereby making the behavior of the clipping detection circuit <NUM> adaptable to different applications and/or requirements.

Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

Claim 1:
A clipping detector circuit (<NUM>) configured to detect clipping of a pulse-width modulated signal (PWMout) and comprising:
- a first up-counter circuit (<NUM>) configured to:
- receive the pulse-width modulated signal (PWMout) at a respective reset input,
- receive a clock signal (ClkPkTri) having the same period of the pulse-width modulated signal (PWMout) at a respective clock input,
- increase a respective internal count number at each cycle of the clock signal (ClkPkTri) and reset to zero the respective internal count number at each occurrence of an edge in the pulse-width modulated signal (PWMout), and
- assert a first signal (ClipDet) as a result of the respective internal count number reaching a certain number n, and de-assert the first signal (ClipDet) as a result of an edge occurring in the pulse-width modulated signal (PWMout);
the clipping detector circuit (<NUM>) being characterized in that it comprises a second up-counter circuit (<NUM>) configured to:
- receive the first signal (ClipDet) at a respective asynchronous reset input and the pulse-width modulated signal (PWMout) at a respective clock input,
- increase a respective internal count number at each occurrence of a pulse in the pulse-width modulated signal (PWMout) and reset to zero the respective internal count number at each assertion of the first signal (ClipDet), and
- assert a second signal (ClipOut) as a result of the respective internal count number reaching a certain number m,
and in that the circuit is configured (<NUM>) for generating at output a clipping detection signal (ClipDet') indicative of whether the pulse-width modulated signal (PWMout) is clipped or not as a function of the first signal (ClipDet) and the second signal (ClipOut), wherein said clipping detection signal (ClipDet') is asserted in response to said first signal (ClipDet) being asserted or said second signal (ClipOut) being de-asserted, and said clipping detection signal (ClipDet') is de-asserted in response to said first signal (ClipDet) being de-asserted and said second signal (ClipOut) being asserted.