Patent Description:
While fabricating a nonvolatile semiconductor memory cell array, e.g., an array of stacked-gate memory cells in which each memory cell has a floating gate and a control gate, the fabrication process requires the use of many masks and corresponding processing steps, which adds complexity, making the process less efficient and more difficult to control.

In addition, when the memory cells are each designed to have a floating gate portion disposed in a trench in the substrate, difficulties arise when forming the trench. For instance, when etching through thick layers of oxide, it is difficult to detect the surface of the silicon substrate, leading to non-uniform trench depths across the wafer.

<CIT> describes an array of non-volatile memory cells is arranged in a plurality of rows and columns where each cell has a first region and a second region spaced apart from one another with a channel region therebetween for the conduction of charges between the first region and the second region.

Accordingly, there is a need to improve the efficiency of processes for manufacturing nonvolatile memory cells, such as NOR memory cells. Such methods improve the fabrication efficiency by combining certain deposition steps when forming peripheral logic transistor gates and memory cell gates. Such methods further improve the fabrication process by depositing less oxide in the vicinity of the trenches, thereby improving trench depth uniformity which in turn leads to more uniform memory cell operation across the wafer.

A method according to the invention is presented in claim <NUM>. Embodiments of the invention are presented in the dependent claims.

For a better understanding of the various described embodiments, reference should be made to the Description of Embodiments below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the figures.

Attention is now directed toward embodiments of an electrically erasable programmable nonvolatile memory cell, sometimes called a NOR memory cell or split-gate NOR memory cell, in accordance with some embodiments. <FIG> is a cross section of a pair of memory cells <NUM>, <NUM>. The memory cells mirror each other, with a memory cell formed on each side of, and including, a shared source line <NUM>. In the interest of brevity, the remainder of this disclosure references only one memory cell, memory cell <NUM>. However, it is appreciated that neighboring memory cell <NUM> has corresponding features and behaves similarly under similar circumstances. In some embodiments, memory cells <NUM> and <NUM> correspond to memory cells <NUM> and <NUM> as described with regard to <FIG> of <CIT>, entitled "NOR Memory Cell with Vertical Floating Gate," which is incorporated by reference in its entirety.

In some embodiments, memory cell <NUM> includes a semiconductor substrate <NUM> having a first substrate region <NUM> (sometimes referred to as a drain region) and a trench region <NUM> (sometimes referred to as a source region or a source line region). In some embodiments, the first substrate region <NUM> serves as a drain, although it is appreciated that the source and drain of a transistor can be switched during operation. Substrate <NUM> further includes a horizontal surface <NUM>, disposed over the drain region <NUM> and extending in a lateral direction towards trench region <NUM>. In some embodiments, at least a portion of surface <NUM> is a silicon-oxide interface (e.g., between a silicon substrate and an oxide-based insulation region). For the purposes of this disclosure, the term "trench" describes a region from which substrate material has been removed, and thus an absence of substrate material, while the term "trench region" describes various regions of the substrate adjacent to the trench.

In some embodiments, memory cell <NUM> further includes an electrically conductive control gate <NUM> (sometimes referred to herein as a word line), an electrically conductive floating gate <NUM>, and an insulation region <NUM> (sometimes referred to herein as a gate separation insulation region, or an oxide layer) disposed between control gate <NUM> and floating gate <NUM>. In some embodiments, floating gate <NUM> includes a first portion disposed inside the trench, and a second portion disposed above the trench and extending away from the trench. In some embodiments, the second portion is longer than the first portion. In some embodiments, the second portion includes a pointed tip (e.g., located at the end of the floating gate closest to the erase gate <NUM>). In some embodiments, the second portion includes a tip that is not pointed, but instead has a diameter substantially equal to a diameter of the first portion of the floating gate. Stated another way, while in some embodiments the tip of the floating gate <NUM> is tapered (as shown in <FIG>), the floating gate in other embodiments is so thin that the tip and the body of the floating gate are substantially the same diameter (not shown).

In some embodiments, memory cell <NUM> further includes an electrically conductive source line <NUM> electrically connected to a bottom portion of the trench region <NUM>. Source line <NUM> extends away from the substrate. In some embodiments, source line <NUM> includes a first portion disposed at least partially inside the trench and electrically connected to the bottom of the trench region <NUM>, and a second portion disposed above the first portion. In some embodiments, at least a portion of the source line is disposed outside the trench.

In some embodiments, memory cell <NUM> further includes a dielectric layer between at least a portion of the floating gate <NUM> and at least a portion of the source line <NUM>. In some embodiments, the dielectric layer is a "thin" dielectric layer, so as to provide a strong capacitive coupling between floating gate <NUM> and source line <NUM>. In some embodiments, the dielectric layer comprises a combination of oxide and nitride, or other high dielectric constant material. In some embodiments, the dielectric layer has a combined total thickness between <NUM> and <NUM>.

In some embodiments, memory cell <NUM> further includes an insulation layer between at least a portion of the floating gate <NUM> and at least a portion of the trench sidewall. In some embodiments, the insulation layer comprises a combination of oxide and nitride, or other high dielectric constant material. In some embodiments, compared with a conventional silicon oxide layer, the insulation layer provides a lower interface energy barrier (sometimes called an energy barrier height) for hot electrons to overcome in order to be injected into the floating gate <NUM>. In some embodiments, the low interface energy barrier provided by the dielectric material of the insulation layer is less than <NUM> eV (electron volts), and in some embodiments is less than <NUM> eV, or less than <NUM> eV.

In some embodiments, memory cell <NUM> further includes an electrically conductive erase gate <NUM> insulated from and disposed over the top of the floating gate <NUM>. Erase gate <NUM> is insulated from the floating gate portion <NUM> by an insulation layer <NUM>, sometimes referred to herein as an erase gate insulation region, disposed between the erase gate and the tip of the second floating gate portion. In some embodiments, the insulation layer is a tunnel oxide, through which tunneling electrons travel between the tip of the floating gate and the erase gate. In some embodiments, erase gate <NUM> is further disposed over at least a portion of the source line <NUM>. In some embodiments, the capacitive coupling between floating gate <NUM> and erase gate <NUM> is much weaker than the capacitive coupling between floating gate <NUM> and source line <NUM>, which is beneficial for efficiently and quickly erasing the memory cell. In some embodiments, the combined capacitive coupling between the floating gate <NUM>, source line <NUM>, and control gate <NUM> is greater than the capacitive coupling between the floating gate <NUM> and the erase gate <NUM> by a ratio of at least <NUM> to <NUM> (i.e., the capacitive coupling ratio is at least <NUM> to <NUM>), and in some embodiments the aforementioned capacitive coupling ratio is at least <NUM> to <NUM>, <NUM> to <NUM>, or <NUM> to <NUM>. The strong capacitive coupling between the floating gate <NUM> and the source line <NUM> (compared to the capacitive coupling between the floating gate and the erase gate) is caused by the proximity of the floating gate <NUM> to the source line <NUM>, as well as the large surface area of the vertical face of the floating gate <NUM> that is in close proximity to the source line <NUM>. In some embodiments, the space between the tip of the floating gate <NUM> and the erase gate is in the range of 100Å-200Å. In some embodiments, the space between the floating gate <NUM> and the source line <NUM> is 50Å - 100Å (e.g., 80Å).

In some embodiments, conductive elements of the memory cell <NUM> (e.g., control gate <NUM>, floating gate <NUM>, source line <NUM>, and/or erase gate <NUM>) are constructed of appropriately doped polysilicon. It is appreciated that "polysilicon" refers to any appropriate conductive material, formed at least in part from silicon or metal material, that can be used to form the conductive elements of nonvolatile memory cells. In addition, in accordance with some embodiments, insulation elements of the memory cell <NUM> (e.g., insulation regions <NUM> and <NUM>) are constructed of silicon dioxide, silicon nitride, and/or any appropriate insulator that can be used to form the insulation elements of nonvolatile memory cells.

In some embodiments, as shown in <FIG>, memory cells <NUM> and <NUM> are memory cells in an array of memory cells, located in a memory cell region <NUM> of a semiconductor device <NUM>, sometimes called a chip or die, that also includes a peripheral circuit region <NUM> in which logic circuitry, the logic circuitry including transistors, sometimes herein called peripheral transistors.

<FIG> illustrates an example cross section of memory cells <NUM> and <NUM> (e.g., located in memory cell region <NUM> in <FIG>), and a peripheral transistor <NUM> (e.g., located in peripheral circuit region <NUM> in <FIG>). As shown in the example, memory cell <NUM> includes a control gate <NUM>, and peripheral transistor <NUM> includes a gate <NUM>. In some embodiments, gates <NUM> and <NUM> are fabricated during the same manufacturing steps, as described in more detail with reference to <FIG> below.

<FIG> illustrates a plan view of a memory cell array <NUM> in accordance with some embodiments. In some embodiments, metal <NUM> bit lines <NUM> interconnect with drain regions <NUM>. Oxide spacer defined word lines <NUM> extend across both the active regions <NUM> and the isolation regions <NUM>. The self-aligned source lines <NUM> electrically connect to the source regions for each row of paired memory cells. The floating gates <NUM> are disposed in trenches in the active regions <NUM> underneath the erase gates <NUM>. In some embodiments, metal <NUM> source line <NUM> is connected to source lines <NUM> (e.g., <FIG>).

Attention is now directed to <FIG>, which illustrate a process for manufacturing a memory cell (e.g., memory cell <NUM>) in accordance with some embodiments. A process in accordance with some embodiments begins in <FIG>, which shows a cross-section view of silicon substrate <NUM> and an oxide layer <NUM> (e.g., a thin gate oxide), above which polysilicon material <NUM> is deposited. The final structure depicted in <FIG> and <FIG> is substantially similar to the memory cell structure described in <CIT>. However, embodiments of the fabrication process described herein are simpler, and easier to control. In the <CIT> process, when polysilicon is deposited for the control gates of memory cells of the integrated circuit, transistors forming peripheral logic of the integrated circuit have not yet been formed. But in embodiments described herein, the peripheral transistors are substantially complete, to the extent that the peripheral transistor gates are formed at the same time as the control gates of the memory cells. The peripheral transistors, which have different oxide thicknesses, are well defined.

Referring to <FIG>, polysilicon (hereinafter poly) <NUM> is deposited over a thin gate oxide layer <NUM> (e.g., having a thickness of 22Å) on top of the substrate <NUM>. The gate oxide <NUM> is also used for peripheral logic transistors (see, e.g., <FIG>). The poly <NUM> serves as: (i) gate material (also called gate conductor material) for peripheral logic transistors (see <FIG> gate <NUM>), and (ii) the word line of the memory cell (see <FIG> control gate <NUM>). In particular, at this stage of the process, a transistor region of the peripheral circuit region looks substantially the same as the memory cell portion shown in <FIG> (see <FIG> regions <NUM> and <NUM>), except that, in some embodiments, the peripheral transistor gate oxide has a different thickness than the thickness of thin gate oxide <NUM>. Typically, the gate oxide <NUM> for the memory cell and peripheral circuitry is between 20Å and 50Å thick.

Referring to <FIG>, an oxide layer <NUM>, sometimes called a first stacking oxide layer, and a nitride layer <NUM> (e.g., SiN) are deposited on top of the poly <NUM>. See <FIG> for an expanded view of this process step, including the memory cell region <NUM> and the peripheral circuit region <NUM>.

Referring to <FIG>, the source line region is defined (e.g., using an etch operation <NUM>). The source line region defines the decoupling oxide <NUM>, the floating gate, and the source line for each memory cell. In some embodiments, the source line region is opened using a mask <NUM> and etching <NUM>.

Referring to <FIG>, a halo implantation creates a source line halo region <NUM> in the substrate <NUM> to prevent punch-through. Decoupling oxide <NUM> is deposited and etched <NUM>, forming a shape that will facilitate the formation of a vertical floating gate with tapered top, as discussed below (see, e.g., <FIG>, <NUM>).

In the process described in <CIT>, the spacer etch is defined by a nitride mask at the top and later etched all the way down (Figs. 5C-D in that application). In that process, a relatively thick layer (e.g., 1000Å) of oxide is deposited and etched to form a spacer. As the oxide is etched down and the silicon begins to be etched, various silicon trenches may become non-uniform across the wafer. Some cells may have deeper trenches, other cells may have trenches that are more shallow, leading to uniformity problems across the wafer. However, in embodiments described in this application, a thinner layer of oxide can be deposited (e.g., 350Å) and etched to form a spacer. As such, for the spacer etch, only that 350Å of oxide needs to be etched. Since the thinner oxide layer makes it easier to detect the Si surface, embodiments of this process allow for better control of the trench depths across the wafer.

Referring to <FIG>, the silicon trench <NUM> is etched. At this point, the gate material <NUM> that will be used for the word line is already present. In the process described in <CIT>, the word line would be deposited as a spacer, formed later in the process. But in the embodiments described in this application, the poly <NUM> that will form the word line has already been deposited at this point in the process, as is also the case for the gates for peripheral region transistors.

Referring to <FIG>, the beginning of floating gate formation is depicted. First, an oxide layer <NUM> (e.g., having a thickness of 80Å or less), sometimes called a floating gate oxide layer, is deposited. Then, a metal layer <NUM> (e.g., TiN, having a thickness of 30Å or less), sometimes called a floating gate metal layer, is deposited. The metal from this layer <NUM> forms the floating gate. Then, an optional nitride layer <NUM> (e.g., SiN, having a thickness of 10Å or less), sometimes called a floating gate nitride layer, is deposited to protect the metal layer <NUM>.

Referring to <FIG>, a separation mask <NUM> is deposited, covering the floating gate metal layer <NUM> and nitride layer <NUM> for floating gate separation.

Referring to <FIG>, the floating gate material <NUM> is patterned using one or more defining etches <NUM>. In some embodiments, etches <NUM> etch the floating gate oxide layer <NUM>, the floating gate metal layer <NUM>, and the floating gate nitride layer <NUM>, leaving a region of the floating gate oxide layer <NUM> disposed (i) underneath the floating gate metal layer <NUM> and above the trench, and (ii) between the floating gate metal layer <NUM> and a sidewall of the trench. As a result of the etch(es) <NUM>, there is a vertical floating gate <NUM> and an oxide spacer region <NUM> disposed both vertically and horizontally between the floating gate <NUM> and the substrate <NUM>. In some embodiments, a chemical mechanical polishing (CMP) process is used to set the height of the floating gate <NUM>.

Referring to <FIG>, first, coupling oxide <NUM> is deposited. The coupling oxide is sometimes referred to herein as CPOX, and in some embodiments, is similar to other oxides used in the cell (e.g., oxide <NUM>). Then, a protection layer <NUM> (e.g., TiN, 60Å) is deposited to protect the coupling oxide <NUM>. The protection layer <NUM> is sometimes referred to herein as a CPOX protection spacer or coupling oxide protection spacer. The purpose of the protection layer <NUM> is to protect the coupling oxide <NUM> adjacent to the floating gate <NUM> (corresponding to <NUM> in previous figures). The coupling oxide <NUM> has to be extra clean. More specifically, if any impurities enter the coupling oxide <NUM> (e.g., from subsequent etching), this may cause charge leakage issues. Therefore, once the coupling oxide <NUM> is deposited, another layer (<NUM>) is immediately deposited to protect it.

Referring to <FIG>, the TiN protection layer <NUM> and the coupling oxide <NUM> are etched (<NUM>). In some embodiments, the etch is anisotropic, and does not etch the vertical portion of the coupling oxide protection spacer <NUM>, but etches a top portion of the protection spacer <NUM> and proceeds all the way to the silicon substrate <NUM> at the bottom of the trench. As a result, a portion of the trench adjacent to the coupling oxide <NUM> and the coupling oxide protection spacer <NUM> is exposed, and the nitride layer <NUM> over the first stacking oxide layer <NUM> is exposed.

Referring to <FIG>, a source line junction implant is performed, forming source line junction implant region <NUM> in the silicon substrate <NUM>, and the implant is annealed.

Referring to <FIG>, a barrier layer (e.g., TiN) <NUM> is deposited, and then source line gate material <NUM> (e.g., tungsten or polysilicon) is deposited. The additional TiN <NUM>, before the tungsten deposition, prevents direct contact between the tungsten and the silicon, which may cause undesirable behavior.

Referring to <FIG>, the tungsten <NUM> and TiN <NUM> layers are etched back (<NUM>) to form source line <NUM> (<FIG>).

Referring to <FIG>, another layer of oxide <NUM>, sometimes called a second stacking oxide layer, sometimes called a planarizing oxide layer, is deposited; the purpose of this oxide layer is to fill in the gaps left over from the previous etch (<NUM>).

Referring to <FIG>, the oxide <NUM> is etched back (<NUM>) using, e.g., a CMP process, resulting in formation of a flat surface (sometimes referred to as planarizing).

Referring to <FIG>, after planarizing, the nitride <NUM> is removed by, e.g., using a stripping process <NUM>.

Referring to <FIG>, a layer of nitride is deposited in the original location of the nitride <NUM> (which has since been removed). Then, the nitride is etched away (e.g., using an anisotropic etching process) to form a nitride spacer <NUM> (e.g., having a width of 250Å or less). In a later step, nitride space <NUM> is used to form a word line spacer (sometimes called a gate spacer portion of an oxide layer), used to define word line <NUM> of the memory cell.

Referring to <FIG>, the oxide <NUM> and <NUM> (see <FIG>) are etched (<NUM>), leaving behind the nitride spacer <NUM>.

Referring to <FIG>, the nitride spacer <NUM> (see <FIG>) is stripped (<NUM>), exposing a portion of the first stacking oxide layer overlying a portion of the gate conductor material (e.g., poly) <NUM> that will form the word line. This portion of the first stacking oxide layer is sometimes called a gate spacer, word line spacer, first word line spacer, or word line spacer portion of the first stacking oxide layer. Then, a nitride layer <NUM> (e.g., ALD (atomic layer deposition) nitride, 10Å) is optionally deposited in order to seal the floating gate tip <NUM>.

Referring to <FIG>, a tunneling dielectric layer <NUM> (e.g., tunneling oxide) (e.g., having a thickness of 300Å or less, such as 150Å) is deposited. The tunneling dielectric layer is for electron tunneling between the floating gate <NUM> and the erase gate, which will be described below (see <FIG>, erase gate poly <NUM>).

Referring to <FIG>, a protection layer of poly <NUM> is deposited over the oxide layer <NUM>. Since the purity of each oxide layer surrounding the floating gate is critical (as discussed above), the oxide needs to be protected. Here, the oxide <NUM> is protected with poly material <NUM>.

Referring to <FIG>, the protection poly <NUM> is etched <NUM> using, e.g., a resist mask <NUM> (e.g., isotropically etched), leaving a portion of the protection poly <NUM> protected by the resist mask <NUM>.

Referring to <FIG>, while the resist mask <NUM> is still present (e.g., the resist is used as a mask instead of the poly <NUM> because the poly is very thin), the tunnel oxide <NUM> is etched (<NUM>) (e.g., anisotropically) to expose the word line poly <NUM>. The etch also removes exposed portions of nitride <NUM> (i.e., the portions of nitride <NUM> not covered by poly <NUM>). The portion of the tunneling oxide <NUM> remaining over poly material <NUM> is sometimes called a gate spacer, or word line spacer or second word line spacer. The resist mask <NUM> is then removed. In some embodiments, the width of the oxide, sometimes called a combined word line spacer, over the region of poly material <NUM> that will become the word line is approximately 400Å (e.g., 250Å or less of oxide <NUM> (sometimes called the first word line spacer) and approximately 150Å of oxide <NUM> (sometimes called the second word line spacer)). This 400Å of oxide spacer is used as a mask to define the word line later (see <FIG>, 206A).

Referring to <FIG>, another layer of poly <NUM>, sometimes called erase gate polysilicon, is deposited. There are two layers of poly (protection poly layer <NUM> and additional poly layer <NUM>) (e.g., each approximately 150Å thick) over the floating gate tip and the tunneling oxide <NUM>. In some embodiments, combined, the two layers of poly are approximately 300Â thick. These poly layers will eventually become the erase gate (see <FIG>, <NUM>).

Referring to <FIG>, using a mask <NUM> to define the erase gate (<NUM> and <NUM>) and one or more peripheral transistor gates (not shown), the poly gate material <NUM> (<FIG>) is etched (<NUM>) to form word line poly 206A (<FIG>, corresponding to gate <NUM> in <FIG>) and peripheral transistor gate poly <NUM> (<FIG>). The word line gate 206A is defined at this step (until now, there was no definition of the word line gate). The peripheral transistor gate <NUM> (<FIG>) is concurrently defined at this step. The same etch also etches portions of additional poly layer <NUM> exposed by mask <NUM>, thereby defining the lateral extent of the erase gate <NUM> (<FIG>).

In previous fabrication processes (e.g., the process described in <CIT>), the process may have started at the steps shown in <FIG> and continued with the word line poly definition step shown in <FIG>. However, for embodiments described in this application, the steps shown in <FIG> are inserted between the steps described in <FIG> and <FIG> in order to form the rest of the memory cell before the word line poly 206A (<NUM> in <FIG>) is defined and separated from peripheral transistor poly <NUM> (<FIG>). Since the word line is formed using the oxide <NUM> and <NUM> above it as a mask during the etching <NUM>, the word line is self-aligned. On the other hand, the erase gate and peripheral gate are defined by the resist mask <NUM> (<FIG>).

<FIG> and <FIG> include expanded views of <FIG> and <FIG>, including memory cells <NUM>' and <NUM>' (designated as such because the cells <NUM> and <NUM> are not yet fully formed), and the peripheral circuit region <NUM>. In <FIG>, poly layers <NUM> and <NUM> are disposed in both the memory cell region <NUM> and the peripheral circuit region <NUM>. In <FIG>, poly <NUM> has been etched to concurrently form control gate <NUM> of memory cell <NUM>' and gate <NUM> of peripheral transistor <NUM>' (designated as such because the transistor <NUM> is not yet fully formed). Stated another way, a single etch concurrently forms gates <NUM> and <NUM> of the memory cell and the peripheral transistor, respectively.

Referring to <FIG>, a bit line junction halo implant (not shown) is performed. In some embodiments, the halo implant is a boron implant. This increases the concentration of boron underneath the word line, and that high concentration region can block punch-through between the bit line junction <NUM> and the source line junction <NUM>/<NUM>. Punch-through issues may arise during programming due to the high voltage being applied to the source line junction (e.g., <NUM>-6V). As such, a region with high doping (e.g., boron) is placed between the bit line and source line junctions to prevent punch-through. In some embodiments, this step (the bit line junction halo implant) is concurrently performed in the peripheral circuit region <NUM> (see <FIG>).

Referring to <FIG>, the drain <NUM> is formed. In some embodiments, the source and/or the drain of peripheral transistors <NUM> in the peripheral circuit region <NUM> are concurrently formed with drain <NUM> (see <FIG>). In some embodiments, the halo implant is performed in conjunction with an LDD (lightly doped drain) implant. For LDD implantation, a lightly doped region is implanted and spaced out with an LDD spacer (e.g., oxide <NUM>). In some embodiments, the lightly doped drain region is formed using processing steps well known in the semiconductor industry to form drain regions that include lightly doped drain (LDD) sub-regions adjacent neighboring transistor gates and more heavily doped drain sub-regions not adjacent the neighboring transistor gates, one example of which is described in <CIT>, followed by contact formation and the subsequent metallization and other steps to complete the device manufacturing.

The embodiments described herein describe a process in which the memory cell formation steps have been moved to the middle of the overall integrated circuit manufacturing process flow. Stated another way, the steps shown in <FIG> are inserted between the forming of peripheral logic and the steps shown in <FIG>. By doing this, the manufacturing process is simplified and several steps are easier to control. More specifically, referring back to <FIG>, the thin gate oxide <NUM> is used for formation of the memory cell <NUM> as well as for the transistors in the peripheral logic. Before performing steps subsequent to that shown in <FIG>, the gate oxide regions and poly gate material for transistors in the peripheral logic region are already formed. After the logic transistor areas are defined and gate oxide material is formed, the polysilicon gate material <NUM> is deposited (<FIG>). In previous processes (e.g., as described in <CIT>) the process would instead jump to <FIG>, where the erase gate is defined. However, in the currently described embodiments, a resist mask <NUM> (<FIG>) defines the memory cell source line region openings, which in turn are used in later steps to define the poly regions for word line <NUM>. Thus, the word line is self-aligned to an edge of the source line region opening. The etching of poly to form the control gate in the memory cell and the gate in the peripheral logic region is accomplished by the same etching step.

The terminology used in the description of various materials is for the purpose of describing particular embodiments only and is not intended to be limiting. For example, "oxide" is one example of a dielectric material and can be substituted with other dielectrics; "polysilicon" and "tungsten" are examples of gate conductor materials and can be substituted with other conducting materials, and so forth.

Further, the numbers in the axes of the figures have been added for relative reference. Some embodiments of the present disclosure are targeted for <NUM> technology. For such a fabrication process, the specified Angstrom numbers are optimized for <NUM>. However, other process sizes are contemplated and neither "<NUM>" nor the numbers in the axes of the figures are intended to be limiting.

It will also be understood that, although the terms first, second, etc. are, in some instances, used herein to describe various elements, these elements should not be limited by these terms. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, without departing from the scope of the various described embodiments. The first contact and the second contact are both contacts, but they are not the same contact, unless the context clearly indicates otherwise.

The terminology used in the description of the various described embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various described embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the term "if" is, optionally, construed to mean "when," or "upon," or "in response to determining," or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" is, optionally, construed to mean "upon determining," or "in accordance with a determination that," or "in response to determining" or "upon detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]," depending on the context.

Claim 1:
A method of fabricating an electrically erasable programmable nonvolatile memory cell (<NUM>) in a memory cell region (<NUM>) of an integrated circuit, and a logic transistor (<NUM>) in a peripheral region (<NUM>) of the integrated circuit outside the memory cell region (<NUM>), the method comprising:
concurrently, in both the memory cell region (<NUM>) and the peripheral region (<NUM>):
forming a gate dielectric layer (<NUM>) on a top surface of a substrate (<NUM>) of the integrated circuit; and
after forming the gate dielectric layer (<NUM>), depositing a gate conductor material (<NUM>) over the gate dielectric layer (<NUM>);
in the memory cell region (<NUM>), after forming the gate conductor material (<NUM>):
forming a trench (<NUM>) in the substrate (<NUM>);
forming a vertical floating gate (<NUM>) having a portion disposed inside the trench (<NUM>);
forming a source region underneath the trench (<NUM>) in the substrate (<NUM>);
forming a source line (<NUM>) adjacent to the vertical floating gate (<NUM>), the source line (<NUM>) having a portion disposed inside the trench (<NUM>);
forming an erase gate over a portion of a tunneling dielectric layer extending over the vertical floating gate; and
concurrently:
in the memory cell region (<NUM>), forming a word line using a portion of the gate conductor material, the word line including a control gate of the electrically erasable programmable nonvolatile memory cell, and
in the peripheral region (<NUM>), forming a transistor gate of the logic transistor (<NUM>).