Patent Description:
Superconducting qubit devices can have frequencies that are determined at the time of fabrication. The arrangement of frequencies influences the quality of the gate operations and therefore the quantum computation. Some types of frequency collisions can cause gates or qubits to be unusable. Chips whose devices have unacceptable frequencies cannot be used, reducing the yield of good chips.

Furthermore, it may be necessary to encode quantum information to further reduce the errors introduced by gate operations and other noise sources. The encoding must be chosen in such a way that the logical (encoded) qubit yield is high. Existing systems and methods do not enable quantum information to be encoded while also improving yield through reduced frequency collisions. <NPL>, relates to error correction for a quantum processor comprising a qubits arranged in a hexagonal lattice pattern.

According to an embodiment of the present invention, a quantum computer comprising an error correction device and a plurality of superconducting qubits that have frequencies that are determined at the time of fabrication is provided in accordance with independent claim <NUM>.

According to an embodiment of the present invention, a method of correcting data processing on a quantum processor comprising an error correction device and a plurality of superconducting qubits that have frequencies that are determined at the time of fabrication is provided in accordance with independent claim <NUM>.

According to an embodiment of the present invention, a computer-executable medium which when run by a quantum processor comprising an error correction device and a plurality of superconducting qubits that have frequencies that are determined at the time of fabrication causes said quantum processor to perform the steps as defined in appended independent claim <NUM>.

The quantum computer, method, and computer-executable medium achieve the goal of reducing the probability of a frequency collision and therefore increasing chip yield for logical qubits.

<FIG> shows one member of the family of quantum codes mapped onto the heavy hexagonal lattice according to an embodiment of the current invention. Circles denote physical qubit devices. Lines indicate connections between devices, i.e., which devices may interact with one another. We refer to this arrangement of qubits on the vertices and edges of a hexagonal lattice as a "heavy hexagon.

Collections of physical qubits encode a logical qubit. The logical qubit is the subspace of Hilbert space protected by the error-correcting code. The physical qubits are assigned one of two types, data or ancilla, based on their function. The data qubits (diagonally striped circles on the edges of the hexagons in <FIG>, such as data qubits <NUM>, <NUM>, <NUM>, <NUM>) collectively encode the quantum state of a single logical qubit. The ancilla qubits (white and stippled circles in <FIG>, such as ancilla qubits <NUM>, <NUM>, <NUM>, and <NUM>) are used to measure operators that reveal the presence of errors. We refer to the new code as a hybrid subsystem code. It is a so-called gauge-fixing of a Bacon-Shor code, as it uses X-type stabilizers of the surface code and Z-type gauge operators of the Bacon-Shor code.

X-type gauge measurements (horizontally striped regions in the <FIG>, for example, regions <NUM>, <NUM>; also see <FIG>) involve two or four data qubits and yield random but correlated results that are combined along vertical columns to detect phase flip errors. The Z-type gauge operator measurements (vertically striped regions in <FIG>, for example, regions <NUM>, <NUM>; also see <FIG>) involve two data qubits and yield random but correlated results that are combined in pairs around the white spaces in <FIG> to detect bit flip errors. The lattice and measurement operators (quantum code) can be expanded horizontally and vertically to increase the number of detectable and correctable errors.

The cross-resonance interaction is used to apply two-qubit quantum gates. The input qubits to these gates are called the control qubit and the target qubit. The control qubit is driven at the target qubit's frequency. The control qubits are chosen to be the degree <NUM> vertices of the graph (i.e. those qubits with exactly two neighbors, for example, the data qubit <NUM> and the ancilla qubit <NUM> in <FIG>) so that only two drive frequencies are necessary for the neighboring target qubits. The frequency of the control qubit must be distinct from both target qubit frequencies, so a total of three frequencies is used. The frequencies are chosen to optimize the two-qubit gates and reduce the collision probability. Having fewer frequencies allows for larger spacing between the frequencies, thereby decreasing the likelihood of frequency collisions.

<FIG> is a schematic illustration of an example of frequency assignment to the <NUM> qubits in the example hybrid subsystem code according to an embodiment of the current invention. Qubits on the edges of the hexagons, such as ancilla qubits <NUM>, <NUM> and data qubits <NUM>, <NUM> in <FIG>, are assigned as control qubits and given frequency C (C = control). Qubits at the vertices of the hexagons, such as ancilla qubits <NUM>, <NUM> in <FIG>, are assigned as target qubits and given alternating frequencies T1 and T2 (T = target). The frequency assignment generalizes to larger codes and lattices in the natural way.

Each X-type and Z-type operator can be measured using the respective quantum circuits schematically illustrated in <FIG>. The circuits are fault-tolerant in the usual sense. If a gate fails and introduces errors, either those errors do not spread to other qubits or a "flag measurement" detects how the error has spread so it can be corrected.

A CNOT gate's control and target qubits can be swapped and conjugated by single-qubit Hadamard gates to match the roles implied by the frequency assignment.

The Z-measurement circuit, an example of which is illustrated in <FIG>, computes and measures the parity of two data qubits <NUM>, <NUM>. The two data qubits <NUM>, <NUM> are coupled to an ancilla qubit <NUM>, which is measured. One can show that a single fault can affect at most one data qubit in the circuit.

The X-measurement circuit computes and measures the X-type parity of four data qubits <NUM>, <NUM>, <NUM>, <NUM>. Due to the lattice connectivity, faults can lead to X errors that spread to pairs of data qubits. One can show that measurements of the two flag qubits <NUM>, <NUM> can detect when these events occur so the Z-type parity measurements are correctly interpreted and the errors can be corrected. The circuit measures the two flag qubits <NUM>, <NUM> and the ancilla qubit <NUM> that is coupled to the two flag qubits <NUM>, <NUM>.

<FIG> shows a comparison of zero-collision yield for an error-correction lattice according to an embodiment of the current invention and for a conventional error-correction lattice. We use Monte-Carlo simulations to study the expected yield. Device frequencies are sampled from a normal distribution with the given mean and variance. A set of frequency collision conditions and types is defined, and chip samples are rejected if one or more collisions occur. Based on the simulation results, for <NUM>-<NUM> precision of setting frequencies, hybrid codes on heavy-hexagonal lattices (solid curve) yield zero-collision chips about 10x more often than standard surface codes on square lattices (dashed curve).

<FIG> shows definitions of seven cross-resonance gate collision types. The lattice geometry disclosed herein helps mitigate these frequency collisions.

Accordingly, the present invention is directed a quantum computer that includes a quantum processor and an error correction device. <FIG> is a schematic illustration of a quantum computer <NUM> according to an embodiment of the present invention. The quantum computer <NUM> includes a quantum processor <NUM> and an error correction device <NUM>. The quantum processor <NUM> includes a first plurality of superconducting qubits arranged in a hexagonal lattice pattern such that each qubit of the first plurality of superconducting qubits is substantially located at a hexagon apex of the hexagonal lattice pattern For example, qubits <NUM>, <NUM>, and <NUM> are substantially located at a hexagon apex of the hexagonal lattice pattern illustrated in <FIG>. The quantum processor <NUM> includes a second plurality of superconducting qubits each arranged substantially along a hexagon edge of the hexagonal lattice pattern. For example, qubits <NUM>, <NUM>, and <NUM> are each arranged substantially along a hexagon edge of the hexagonal lattice pattern. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits. For example, qubit <NUM> is coupled to a first qubit <NUM>, a second qubit <NUM>, and a third qubit <NUM>. Each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. For example, qubit <NUM> is coupled to a first qubit <NUM>, and a second qubit <NUM>. Each of the second plurality of qubits is a control qubit at a control frequency, and each of the first plurality of qubits is a target qubit at one of a first target frequency determined at fabrication or a second target frequency determined at fabrication. A control qubit couples each first target frequency target qubit to a second target frequency target qubit. The error correction device <NUM> is configured to operate on the hexagonal lattice pattern of the first and second plurality of qubits so as to detect and correct data errors.

According to an embodiment of the present invention, the first plurality of qubits are ancilla qubits and the second plurality of qubits are partially data qubits and partially ancilla qubits. In accordance with the invention, the error correction device includes X-type gauge circuits that measure phase flip errors that involve two or four data qubits. The X-type gauge circuits include two-qubit gates that have as inputs a target qubit and a control qubit. For each of the two-qubit gates, one of the first plurality of qubits is the target qubit and one of the second plurality of qubits is the control qubit. <FIG> is a schematic drawing of an example of an X-type gauge circuit.

In some embodiments, the error correction device includes Z-type gauge circuits that measure bit flip errors that involve two data qubits. The Z-type gauge circuits include two-qubit gates that have as inputs a target qubit and a control qubit. For each of the two-qubit gates, one of the first plurality of qubits is the target qubit and one of the second plurality of qubits is the control qubit. <FIG> is a schematic drawings of an example of a Z-type gauge circuit.

The error correction device encodes a plurality of logical qubits into corresponding pluralities of the first and second pluralities of qubits. For example, the quantum computer <NUM> may include <NUM> qubits comprising the first and second pluralities of qubits, wherein the <NUM> qubits encode a first logical bit. The quantum computer <NUM> may include additional sets of <NUM> qubits that encode additional logical bits.

<FIG> is a flowchart that illustrates a method <NUM> of correcting data processing according to an embodiment of the present invention. The method <NUM> of correcting data processing on a quantum processor that includes a plurality of coupled superconducting qubits arranged in hexagonal lattice pattern according to an embodiment of the current invention includes encoding a plurality of logical qubits into corresponding pluralities of the plurality of coupled qubits <NUM>. The method includes performing an X-type gauge measurement of phase flip errors that involve two or four data qubits out of the plurality of coupled qubits <NUM>. The plurality of coupled qubits are arranged in a hexagonal lattice pattern as noted above.

The method <NUM> can further include performing a Z-type gauge measurement of bit flip errors that involve two data qubits out of the plurality of coupled qubits.

According to the current invention, a method, when run a quantum computer comprising a quantum processor comprising a plurality of coupled qubits arranged in a hexagonal lattice pattern, causes the quantum processor to encode a plurality of logical qubits into corresponding pluralities of the plurality of coupled qubits, and causes the error correction device to perform an X-type gauge measurement of phase flip errors that involve two or four data qubits out of the plurality of coupled qubits. The plurality of coupled qubits are arranged in a hexagonal lattice pattern as noted above.

The method further causes the error correction device to perform a Z-type gauge measurement of bit flip errors that involves two data qubits out of the plurality of coupled qubits.

The invention is ere directed to an arrangement of coupled devices on a hexagonal lattice. Every device on the lattice is coupled to at most three neighbors. The so-called "modified" or "heavy" lattice refers to the additional devices on edges as well as vertices.

Some embodiments of the current invention are directed to a family of quantum codes tailored to heavy octagonal lattice. Quantum codes encode logical qubits into collections of noisy physical qubits such that errors can be detected and corrected. This family of subsystem quantum codes uses Z-type stabilizers of the surface code and X-type stabilizers of the Bacon-Shor code. It is a gauge-fixing of the Bacon-Shor code that adapts to the lattice.

Some embodiments of the current invention are directed to an assignment of frequencies to physical qubits. The assignment allows two-qubit gates to be applied in such a way that only three frequencies are necessary, increasing the total spacing between frequencies and decreasing frequency collisions.

Some embodiments of the current invention are directed to method of error syndrome measurement tailored to the hexagonal lattice. The syndrome is computed from the outcomes the X-type gauge operator and Z-type gauge operator measurements. The method makes use of the available interactions on the lattice. The method is fault-tolerant and uses so-called flag qubits to achieve this.

Some embodiments can reduce the probability of a frequency collision and therefore increase chip yield for logical qubits. Because the plurality of qubits have one of three frequencies, the spacing between each frequency can be larger, reducing the likelihood of frequency collisions, and therefore increasing the qubit chip yield.

Claim 1:
A quantum computer (<NUM>), comprising:
a quantum processor (<NUM>), comprising:
a first plurality of superconducting qubits (<NUM>, <NUM>; <NUM>, <NUM>; <NUM>, <NUM>, <NUM>) arranged in a hexagonal lattice pattern such that each qubit of the first plurality of superconducting qubits is substantially located at a hexagon apex of said hexagonal lattice pattern,
a second plurality of superconducting qubits (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>; <NUM>, <NUM>. <NUM>, <NUM>; <NUM>, <NUM>, <NUM>) each arranged substantially along a hexagon edge of said hexagonal lattice pattern,
wherein each of said first plurality of qubits (<NUM>, <NUM>; <NUM>, <NUM>; <NUM>, <NUM>, <NUM>) is coupled to three nearest-neighbor qubits of said second plurality of qubits (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>; <NUM>, <NUM>. <NUM>, <NUM>; <NUM>, <NUM>, <NUM>),
wherein each of said second plurality of qubits (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>; <NUM>, <NUM>. <NUM>, <NUM>; <NUM>, <NUM>, <NUM>) is coupled to two nearest-neighbor qubits of said first plurality of qubits (<NUM>, <NUM>; <NUM>, <NUM>; <NUM>, <NUM>, <NUM>),
wherein each of said second plurality of qubits (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>; <NUM>, <NUM>. <NUM>, <NUM>; <NUM>, <NUM>, <NUM>) is a control qubit at a control frequency determined at fabrication,
wherein each of said first plurality of qubits (<NUM>, <NUM>; <NUM>, <NUM>; <NUM>, <NUM>, <NUM>) is a target qubit at one of a first target frequency (T1) determined at fabrication or a second target frequency (T2) determined at fabrication such that a control qubit couples each first target frequency target qubit to a second target frequency target qubit; and
an error correction device (<NUM>) configured to operate on said hexagonal lattice pattern of said first and second plurality of qubits (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>; <NUM>, <NUM>. <NUM>, <NUM>; <NUM>, <NUM>, <NUM>) so as to detect and correct data errors,
wherein said error correction device (<NUM>) encodes a plurality of logical qubits into corresponding pluralities of said first and second pluralities of qubits (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>; <NUM>, <NUM>. <NUM>, <NUM>; <NUM>, <NUM>, <NUM>), and wherein said error correction device (<NUM>) comprises X-type gauge circuits that measure phase flip errors that involve two or four data qubits.