Patent Description:
Typical integrated circuit systems (e.g., a power management systems) require startup circuitry to provide biasing signals that must be present even when the product is shut down or in another energy-saving mode (e.g., a sleep mode or deep sleep mode) of operation. The startup circuit triggers a wake-up sequence of the integrated circuit system in response to arrival of a wake-up signal. In general, in an energy-saving mode of operation, the startup circuit is operational, but the remainder of the integrated circuit system is shut down. Since the startup circuitry is always on, it is preferable that the startup circuitry consume low or negligible amounts of power. Typical startup circuitry is coupled to a power-on-reset circuit that resets the integrated circuit system when its supply voltage is too low to guarantee proper operation. Due to its low quiescent current, the startup circuit is sensitive to noise (e.g., noise injected from other circuits like an enabled DC-DC converter after wake-up of the integrated circuit). Such sensitivity to noise may cause a failure of the startup circuit, thereby causing a reset of the integrated circuit system (e.g., a power-on-reset) making the electronic product unusable. Accordingly, improved startup techniques are desired.

<CIT> discloses a clock generation circuit with fast-start-up standby mode. In standby mode, a small bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values (i.e., in ON mode). This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode.

<CIT> discloses an analogue circuit configured for fast, accurate start-up. According to one implementation, a circuit includes a steady-state block including steady-state circuitry, a load coupled to the steady-state circuitry and representing a load condition, and a steady-state bias current source configured to provide a steady-state bias current to the steady-state circuitry during steady-state operation. A startup block includes startup circuitry and a startup bias current source configured to provide a startup bias current to the startup circuitry during a startup mode. The startup bias current is substantially larger than the steady-state bias current. The startup circuitry has operational characteristics substantially similar to the steady-state circuitry but without the load condition such that, during the startup mode, the startup circuitry is configured to drive a common node to which both the startup circuitry and the steady-state circuitry are connected to a desired state. The desired state is substantially the same as achieved by the steady-state circuitry during steady-state operation with the load condition.

Referring to <FIG>, useful for understanding the invention, integrated circuit system <NUM> has a startup mode of operation and at least one energy-saving mode of operation. First circuit <NUM> generates a reference voltage for power-on-reset circuit <NUM>. First circuit <NUM> includes low-power current reference <NUM> and power-on-reset circuit <NUM> that use a very low bias current, which is ideally independent of temperature and voltage supply variations. Power-on-reset circuit <NUM> holds integrated circuit system <NUM> in a reset state until voltage V_LP meets a minimum threshold voltage level. First circuit <NUM> is always enabled and is never turned off from battery power. First circuit <NUM> detects wake-up events and triggers a wake-up sequence of integrated circuit system <NUM>. The low-power circuitry of first circuit <NUM> is sensitive to noise. Second circuit <NUM> includes high-power circuitry (e.g., DC-DC converter <NUM> coupled to a battery (not shown) and high-power current reference <NUM>), which in a normal mode of operation, injects noise into first circuit <NUM>.

In an energy-saving mode of operation, current IBIAS_LP, which is generated by low-power current reference <NUM>, equals current IBIAS_TOTAL, which is the total low-power bias current. Driver <NUM> converts current IBIAS_TOTAL to voltage V_LP that is a low-power reference signal for power-on-reset circuit <NUM>. Power-on-reset circuit <NUM> uses the reference voltage in the normal mode of operation, in addition to in the energy-saving mode. However, in the normal mode of operation, current IBIAS_TOTAL varies with noise injected by second circuit <NUM> into first circuit <NUM>. At times, that variation causes current IBIAS_TOTAL to be approximately zero, which causes power-on-reset circuit <NUM> to trigger a power-on-reset event. Conventional techniques for preventing the unwanted power-on-reset event include using a standby regulator and switching the biasing system (e.g., between a low-power biasing system or a high-power biasing system) in response to whether the product is in an energy-saving mode of operation or a normal mode of operation accordingly.

Referring to <FIG>, the first circuit <NUM> of <FIG> includes startup circuit <NUM>, which provides voltage V_LP to power-on-reset circuit <NUM>. Second circuit <NUM> includes high power circuitry that receives a bias current IBIAS_HP generated based on a reference voltage provided by DC-DC conversion of a voltage provided by a battery. In at least one embodiment, startup circuit <NUM> includes bandgap voltage reference <NUM> and current mirror <NUM>, which provides current IBIAS_LP, although other circuits may be used. Startup circuit <NUM> includes Zener diodes and additional devices (e.g., additional n-type transistors and a resistor) that are configured to convert current IBIAS _TOTAL to voltage V_LP having a predetermined voltage level. In at least one embodiment, bandgap voltage reference <NUM> includes bipolar transistors, which are sensitive to noise. During a wake-up event or normal mode of operation, second circuit <NUM> injects a substantial amount of noise into first circuit <NUM>. At times, that noise is sufficient to cause current IBIAS_LP to drop or equal zero, thereby causing voltage V_LP to drop below a predetermined threshold voltage, which causes power-on-reset circuit <NUM> to trigger a power-on-reset event.

Referring to <FIG>, in at least one embodiment, integrated circuit system <NUM> includes first circuit <NUM> having low-power circuitry including low-power current reference <NUM>, driver <NUM>, power-on-reset circuit <NUM>, and summing circuit <NUM>. Second circuit <NUM> includes a high-power current reference <NUM>, which generates current IBIAS_HP during a wake-up event or in a normal mode of operation. In at least one embodiment, switch <NUM> selectively couples circuit <NUM> to a power supply according to the active mode of operation of system <NUM> (e.g., switch <NUM> is closed during a wake-up event or in a normal mode of operation and is open in an energy-saving mode of operation), although other circuit techniques may be used to configure circuit <NUM> according to the active mode of operation. In at least one embodiment, current IBIAS_HP generates various currents for integrated circuit <NUM> and provides a supplemental current that is dedicated to first circuit <NUM> (i.e., is not used elsewhere in integrated circuit <NUM>). High-power current reference <NUM> does not generate current IBIAS_HP in any energy-saving mode of operation. Current IBIAS_HP is not sensitive to noise. In at least one embodiment, high-power current reference <NUM> (e.g., generating microamps) has a much lower impedance than low-power current reference <NUM> (e.g., generating hundreds of nanoamps). The higher impedance (e.g., at least one order of magnitude) of low-power current reference <NUM> attenuates any noise injected by parasitic capacitors (e.g., due to substrate or conductive routing). In at least one embodiment, high-power current reference <NUM> uses an intermediate regulated or cascaded power supply (e.g., <NUM> V) that rejects noise from the power supply (e.g., <NUM> V). In at least one embodiment, high-power current reference <NUM> includes a current mirror circuit coupled to a bandgap current reference or a bandgap voltage reference coupled to a resistor. In at least one embodiment, low-power current reference <NUM> is coupled directly to the power supply since an intermediate regulated or cascaded power supply would increase power consumption. When second circuit <NUM> is configured in an energy-saving mode of operation, second circuit <NUM> does not generate current IBIAS_HP. High-power current reference IREF_HP <NUM> provides current IBIAS_HP to summing circuit <NUM> in first circuit <NUM>.

In at least one embodiment, summing circuit <NUM> receives current IBIAS_HP from second circuit <NUM>. In at least one embodiment, summing circuit <NUM> is a summing node, although other circuits may be used (e.g., a summing amplifier). In at least one embodiment, summing circuit <NUM> includes an error amplifier biased by current IBIAS_HP coupled in parallel with another error amplifier biased by current IBIAS_LP and provides a current that is the sum of the output currents. Summing circuit <NUM> combines current IBIAS_LP and current IBIAS_HP to generate current IBIAS_TOTAL. Driver <NUM> converts current IBIAS _TOTAL to voltage V_LP and provides voltage V_LP to power-on-reset circuit <NUM>. In a normal mode of operation, current IBIAS_TOTAL is equal to the sum of current IBIAS_LP and current IBIAS_HP. In an energy-saving mode of operation, current IBIAS_TOTAL equals current IBIAS_LP since IBIAS_HP is not generated by second circuit <NUM>. No switching is required to turn off current IBIAS_HP since in the energy-saving mode of operation, second circuit <NUM> is powered-down and high-power current source <NUM> does not generate current IBIAS_HP, making current IBIAS_HP equal to zero.

Referring to <FIG>, in at least one embodiment, second circuit <NUM> provides current IBIAS_HP to startup circuit <NUM>. Current mirror <NUM> provides current IBIAS_HP in a normal mode of operation of second circuit <NUM>. Since second circuit <NUM> is powered-down in any energy-saving modes of operation, current IBIAS_HP is not generated in those modes of operation. Accordingly, no digital control logic or switches are needed to provide current IBIAS_HP to first circuit <NUM> in the normal mode of operation but not in the energy-saving mode of operation and the power consumption of first circuit <NUM> does not increase in the energy-saving mode of operation as compared to the system of <FIG> and <FIG>.

Referring to <FIG>, even if a substantial amount of noise is injected into first circuit <NUM> in a normal mode of operation that at times is sufficient to cause current IBIAS_LP to fall or equal zero, current IBIAS_HP is not sensitive to noise and remains non-zero. Thus, when current IBIAS_LP equals zero, current IBIAS_TOTAL equals current IBIAS_HP and voltage V_LP remains above the predetermined threshold level and powers power-on-reset circuit <NUM>. Accordingly, no power-on-reset event is triggered by noise alone. Power-on-reset circuit <NUM> is exemplary only. In other embodiments, the biasing technique disclosed herein is used to provide current IBIAS_TOTAL to other circuits that are functional in an energy-saving mode of operation and in a normal mode of operation.

In at least one embodiment, first circuit <NUM> and second circuit <NUM> are formed on the same integrated circuit die but operate with different voltage reference levels. In at least one embodiment, first circuit <NUM> and second circuit <NUM> are separate integrated circuit die and each includes a bonding pad dedicated to providing current IBIAS_HP to summing node <NUM>. In at least one embodiment, first circuit <NUM> and second circuit <NUM> are packaged separately and each include a terminal dedicated to providing current IBIAS_HP to summing node <NUM>. Accordingly, absent any noise, current IBIAS_LP and voltage V_LP have the same levels in the energy saving mode as in the normal mode. In at least one embodiment, the battery has a voltage of <NUM> V, DC-DC converter <NUM> provides a voltage of <NUM> V, voltage V_LP is <NUM> V, current IBIAS_HP is approximately <NUM>µA, and current IBIAS_LP is approximately <NUM>µA. However, other operating points may be used.

In at least one embodiment, an integrated circuit system has an energy-saving mode of operation and a normal mode of operation. The integrated circuit system includes a circuit configured to use a reference signal in the energy-saving mode of operation and in the normal mode of operation. The integrated circuit system includes a startup circuit configured to provide the reference signal based on a bias signal. The bias signal is generated based on a first bias signal in the energy-saving mode and is generated based on the first bias signal and a second bias signal in the normal mode. The first bias signal is generated in the energy-saving mode and the normal mode. The second bias signal is generated in the normal mode and is not generated in the energy-saving mode.

In an embodiment, the integrated circuit system further includes a first circuit comprising the circuit and the startup circuit. A second circuit is configured to be powered-down in the energy-saving mode and to operate in the normal mode of the integrated circuit system. The second circuit provides the second bias signal to the startup circuit in the normal mode.

In an embodiment, the second circuit includes a switching circuit, the switching circuit injecting noise into the first circuit in the normal mode.

In an embodiment, the second circuit further includes a current mirror coupled to a bandgap reference circuit. The current mirror is configured to provide the second bias signal in the normal mode.

In an embodiment, the integrated circuit system further includes a power source coupled to the first circuit and coupled to the second circuit.

In an embodiment, the startup circuit includes a summing node configured to combine the first bias signal and the second bias signal.

The first bias signal is generated by a first current reference having a first impedance and the second bias signal is generated by a second current reference having a second impedance, the first impedance being at least one order of magnitude less than the second impedance.

In an embodiment, the first bias signal has a first level and the second bias signal has a second level. The second level is sufficient to maintain a non-zero bias current while maintaining the level of a reference signal at a target level.

In an embodiment, the startup circuit includes a bandgap voltage reference including bipolar transistors susceptible to noise.

In an embodiment, the startup circuit includes a current mirror coupled to the bandgap voltage reference and a Zener diode coupled to a voltage reference node providing the reference signal.

In at least one embodiment, a method for operating an integrated circuit system includes operating a circuit using a reference signal in an energy-saving mode of the integrated circuit system and in a normal mode of the integrated circuit system. The method includes generating the reference signal based on a first bias signal in an energy-saving mode of the integrated circuit system and based on the first bias signal and a second bias signal in a normal mode of the integrated circuit system. The first bias signal is generated in the energy-saving mode and in the normal mode. The second bias signal is generated in the normal mode and not generated in the energy-saving mode.

The method further includes generating the first bias signal using a first current reference having a first impedance and generating the second bias signal using a second current reference having a second impedance. The first impedance is at least one order of magnitude less than the second impedance.

In an embodiment, generating the reference signal comprises combining the first bias signal and the second bias signal using a summing node.

In an embodiment, the method further includes generating the first bias signal in the energy-saving mode and in the normal mode, generating the second bias signal only in the normal mode, and converting a bias current to a reference voltage in the energy-saving mode and in the normal mode.

In an embodiment, the first bias signal has the same level in the energy-saving mode as in the normal mode.

In at least one embodiment, an integrated circuit system includes a first circuit configured to operate in an energy-saving mode of the integrated circuit system and in a normal mode of the integrated circuit system. The first circuit generates a reference signal based on a bias signal. The bias signal is generated based on a first bias signal in the energy-saving mode and is a sum of the first bias signal and a second bias signal in the normal mode. The first bias signal is generated in the energy-saving mode and in the normal mode. The second bias signal is generated in the normal mode and is not generated in the energy-saving mode. The integrated circuit system includes a second circuit configured to be powered-down in the energy-saving mode and to operate in the normal mode of the integrated circuit system, the second circuit providing the second bias signal to the first circuit in the normal mode.

In an embodiment, the first bias signal is generated by a first current reference having a first impedance and the second bias signal is generated by a second current reference having a second impedance, the first impedance being at least one order of magnitude less than the second impedance.

In an embodiment, the first circuit includes a startup circuit configured to generate the reference signal and a power-on-reset circuit configured to initiate a power-on-reset event in response to a level of the reference signal falling below a predetermined threshold level.

Thus, techniques for supplementing a default bias current of a startup circuit increases the immunity of the startup circuit to noise without substantially increasing power consumption in an energy-saving mode of operation. The technique does not require switching between biasing in the energy-saving mode and biasing in the wake-up mode. Rather, a supplemental current that is generated in the normal mode of operation (e.g., a mode of operation after a wake-up sequence and a DC-DC converter is enabled) automatically disappears in the energy-saving mode. The technique uses a supplemental current generated by a source that is external to the startup circuitry, thereby increasing diversity with respect to failure mechanisms.

For example, rather than use a buck converter for DC-DC converter <NUM>, other DC-DC converters may be used. In addition, other circuits may be used for bandgap reference <NUM> or current mirror <NUM>.

Claim 1:
An integrated circuit system (<NUM>) having an energy-saving mode of operation and a normal mode of operation, the integrated circuit system comprising:
a power-on-reset circuit (<NUM>) configured to use a reference signal (V_LP) in the energy-saving mode of operation and in the normal mode of operation to determine whether to trigger a power-on-reset event;
a startup circuit (<NUM>) configured to provide the reference signal based on a bias signal (IBIAS_TOTAL), the bias signal being generated based on a first bias signal (IBIAS_LP) in the energy-saving mode and being generated based on the first bias signal and a second bias signal (IBIAS_HP) in the normal mode, the first bias signal being generated in the energy-saving mode and the normal mode, the second bias signal being generated in the normal mode and not being generated in the energy-saving mode;.
a first current reference circuit having a first impedance and configured to generate the first bias signal; and
a second current reference circuit having a second impedance and configured to generate the second bias signal, the first impedance being at least one order of magnitude less than the second impedance.