Patent Description:
The semiconductor structure may include memory cells. The memory cell usually includes a transistor and a capacitor electrically connected to the transistor. The capacitor stores data information, and the transistor controls the reading and writing of data information in the capacitor. The gate of the transistor is electrically connected to a word line (WL), and the on and off of the transistor is controlled by the voltage on the WL. One of a source and a drain of the transistor is electrically connected to a bit line (BL), and the other of the source and the drain is electrically connected to the capacitor. Data information is stored or outputted by using the BL.

As a size of the semiconductor structure becomes more miniaturized, gate-all-around (GAA) transistors are usually used. In the related art, the GAA transistor includes a first conductive layer, a channel region, and a second conductive layer that are stacked sequentially. One of the first conductive layer and the second conductive layer is a source, and the other is a drain. A dielectric layer surrounds the side surface of the channel region, and a gate is disposed on the dielectric layer. However, the foregoing transistor has a relatively large contact resistance with another structure (for example, a BL or a capacitor), the transistor requires a relatively large current, and the semiconductor structure has poor performance. Background may be found in <CIT>, <CIT> and <CIT>.

The embodiments of the present disclosure provide a manufacturing method of a1T-1C Dram.

In the manufacturing method of the semiconductor structure provided in embodiments of the present application, vertical transistors are formed, and at least one of a source and a drain in the vertical transistor is a semi-metal layer, to reduce a contact resistance between the vertical transistor and another structure, and a contact resistance inside the vertical transistor, thereby improving the performance of the semiconductor structure.

In order to make the objectives, features and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application are described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some rather than all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of present application should fall within the protection scope of the present application.

With reference to <FIG>, an embodiment of the present application provides a manufacturing method of a semiconductor structure, including the following steps:
step S101: Provide a substrate.

A substrate <NUM> may be a semiconductor substrate. For example, the substrate <NUM> may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium nitride substrate, a gallium arsenide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like. The substrate <NUM> may be doped or not. For example, the substrate <NUM> may be a N-type substrate or a P-type substrate.

In some possible examples, with reference to <FIG> and <FIG>, a first cross section shown in <FIG> is a plane perpendicular to a second direction. A second cross section shown in <FIG> is a plane perpendicular to the second direction. A plurality of BLs <NUM> may be also disposed in the substrate <NUM>, are spaced apart from each other, and extend along the second direction. As shown in <FIG>, the plurality of BLs <NUM> extend along a horizontal direction (a direction X shown in <FIG>). As shown in <FIG> and <FIG>, the BLs <NUM> may be exposed on the surface of the substrate <NUM>. The BLs <NUM> are exposed on the upper surface of the substrate <NUM>, to be electrically connected to another structure on the substrate <NUM>.

With reference to <FIG> and <FIG>, a shallow trench isolation (STI) structure <NUM> is also disposed in the substrate <NUM>. The STI structure <NUM> is disposed between adjacent BLs <NUM>, to isolate them. The STI structure <NUM> may be filled with an insulating material such as silicon nitride or silicon oxide.

Step S102: Form a plurality of laminated structures arranged at intervals on the substrate, where each of the laminated structures includes a first conductive layer, an insulating layer, and a second conductive layer that are stacked sequentially, and at least one of the first conductive layer and the second conductive layer is a semi-metal layer.

With reference to <FIG>, a plurality of laminated structures <NUM> are formed on the substrate <NUM>, and are disposed at intervals. The laminated structure <NUM> includes a first conductive layer <NUM>, an insulating layer <NUM>, and a second conductive layer <NUM>. One of the first conductive layer <NUM> and the second conductive layer <NUM> is electrically connected to a capacitor, and the other of the first conductive layer <NUM> and the second conductive layer <NUM> is electrically connected to the BLs <NUM>. For example, the first conductive layer <NUM>, the insulating layer <NUM>, and the second conductive layer <NUM> are stacked sequentially in a vertical direction (a direction Z shown in <FIG>). The first conductive layer <NUM> is electrically connected to BL <NUM>, and the second conductive layer <NUM> is electrically connected to the capacitor.

The insulating layer <NUM> may be an oxide layer. For example, a material of the insulating layer <NUM> may be silicon oxide. At least one of the first conductive layer <NUM> and the second conductive layer <NUM> is a semi-metal layer. For example, the first conductive layer <NUM> is a semi-metal layer, and the second conductive layer <NUM> is also a semi-metal layer. A material of the semi-metal layer is bismuth. The first conductive layer <NUM> and/or the second conductive layer <NUM> are/is disposed as a semi-metal layer, which can reduce a contact resistance between the laminated structure <NUM> and the BL <NUM> and/or a capacitor, thereby improving the performance of the semiconductor structure.

With reference to <FIG>, at least one of laminated structures <NUM> is disposed on each of the BLs <NUM> along a second direction (a direction X shown in <FIG>). The first conductive layer <NUM> is in contact with the BL <NUM>, such that the first conductive layer <NUM> is electrically connected to the BL <NUM>. The laminated structure <NUM> may be in a shape of a column, such as a cylinder, an elliptical column, a square column, or a rectangular column. The laminated structures <NUM> may be arranged in an array.

With reference to <FIG>, in some possible examples, a plurality of laminated structures <NUM> are arranged at intervals on the substrate <NUM>, where the laminated structure <NUM> includes the first conductive layer <NUM>, the insulating layer <NUM>, and the second conductive layer <NUM> that are stacked sequentially, and at least one of the first conductive layer <NUM> and the second conductive layer <NUM> is a semi-metal layer, which includes following steps.

The first conductive layer <NUM>, the insulating layer <NUM>, and the second conductive layer <NUM> that are stacked are formed through deposition on the substrate <NUM>. As shown in <FIG> and <FIG>, the first conductive layer <NUM> is deposited on the substrate <NUM>, the insulating layer <NUM> is deposited on the first conductive layer <NUM>, and the second conductive layer <NUM> is deposited on the insulating layer <NUM>. The deposition may be a chemical vapor deposition (CVD), a physical vapor deposition (PVD), or an atomic layer deposition (ALD).

Then, the first conductive layer <NUM>, the insulating layer <NUM>, and the second conductive layer <NUM> are etched, to form the plurality of laminated structures <NUM> arranged at intervals. As shown in <FIG>, a part of the first conductive layer <NUM>, a part of the insulating layer <NUM>, and a part of the second conductive layer <NUM> are removed through dry etching or wet etching, such that the retained first conductive layer <NUM>, the retained insulating layer <NUM>, the retained second conductive layer <NUM> are separated to form the plurality of laminated structures <NUM> that are spaced apart from each other.

Step S103: Form a channel layer covering the laminated structures, and a dielectric layer covering the channel layer.

With reference to <FIG>, the channel layer <NUM> covers the laminated structures <NUM>. The dielectric layer <NUM> covers the channel layer <NUM>. Specifically, the channel layer <NUM> covers the side surfaces and the top surfaces of the laminated structures <NUM>. The dielectric layer <NUM> covers the side surface and the top surface of the channel layer <NUM>, where the top surface is away from the substrate <NUM>. As shown in <FIG>, the channel layer <NUM> covers an outer peripheral surface of the first conductive layer <NUM>, an outer peripheral surface of the insulating layer <NUM>, and an outer peripheral surface of the second conductive layer <NUM>. The channel layer <NUM> further covers the top surface <NUM> of the second conductive layer.

One of the first conductive layer <NUM> and the second conductive layer <NUM> forms a source, and the other forms a drain. The channel layer <NUM> surrounding the side surface of the laminated structure <NUM> forms a channel region, to provide a conductive channel between the source and the drain, such that carriers can move from the source to the drain or vice versa. The dielectric layer <NUM> may be an oxide layer, and the dielectric layer <NUM> on the side surface of the channel layer <NUM> forms a gate oxide layer.

As shown in <FIG>, the channel region is layered. A material of the channel layer <NUM> may include molybdenum sulfide, such as molybdenum disulfide, transition metal sulfur compounds (TMDs), or the like. There is a band gap in the layered molybdenum sulfide, which forms a field effect transistor with a high on-off ratio. In addition, the layered molybdenum sulfide has a high specific surface area, which is beneficial to overcome the short channel effect. The on-off ratio refers to the ratio of the on-state current to the off-state current of a device. Specifically, in a transistor, when the source-drain voltage remains unchanged, the ratio of the source-drain current measured when the gate voltage is applied to that when the gate voltage is not applied is the on-off ratio.

In some possible embodiments, the material of the channel layer <NUM> is molybdenum sulfide. According to the invention, the material of the semi-metal layer is bismuth. Preferably, the channel layer <NUM> is made of molybdenum sulfide. According to the invention, the first conductive layer <NUM> and the second conductive layer <NUM> are both made of bismuth. Through such a disposal, the energy barriers at the interfaces of molybdenum sulfide and bismuth are reduced, which can reduce the metal-induced gap states (MIGSs) between the channel layer <NUM> and the first conductive layer <NUM>, and between the channel layer <NUM> and the second conductive layer <NUM>, thereby reducing the contact resistances between the channel layer <NUM> and the first conductive layer <NUM> and between the channel layer <NUM> and the second conductive layer <NUM>.

In the embodiments of the present application, the channel layer <NUM> covering the laminated structures <NUM> and the dielectric layer <NUM> covering the channel layer <NUM> are formed in the following steps:
The channel layer <NUM> is deposited on the laminated structure <NUM> and the substrate <NUM>, and the channel layer <NUM> covers the top surfaces and the side surfaces of the laminated structures <NUM>, and the top surface of the substrate <NUM>. With reference to <FIG>, the channel layer <NUM> is formed through a deposition process. The channel layer <NUM> covers the top surfaces and the side surfaces of the laminated structures <NUM>, and the top surface of the substrate <NUM>. Then, the dielectric layer <NUM> is deposited on the channel layer <NUM>. With reference to <FIG>, the dielectric layer <NUM> is formed through a deposition process. The dielectric layer <NUM> covers the entire surface of the channel layer <NUM>.

Step S104: Form WLs extending along a first direction, where the WL includes a plurality of contact parts and a connecting part connecting adjacent contact parts, the contact part surrounds and is in contact with a side surface of the dielectric layer, and the contact part is opposite to at least a part of the insulating layer.

With reference to <FIG>, a plurality of WLs <NUM> are formed between the laminated structures <NUM> after the channel layer <NUM> and the dielectric layer <NUM> are formed, are disposed at intervals, and extend along a first direction (a direction Y shown in <FIG>). As shown in <FIG>, the WL <NUM> includes a plurality of contact parts <NUM> and a connecting part <NUM> connecting adjacent contact parts <NUM>. The contact part <NUM> surrounds and is in contact with a side surface of the dielectric layer <NUM>.

As shown in <FIG>, the contact part <NUM> corresponds to a part of the insulating layer <NUM>. The contact part <NUM> serves as a gate of the transistor, that is, a part of the WL <NUM> serves as a gate. In a direction (a direction Z shown in <FIG>) perpendicular to the substrate <NUM>, the orthographic projection of the insulating layer <NUM> partially overlaps with that of the contact part <NUM>. For example, the top surface of the contact part <NUM> is lower than that of the insulating layer <NUM>, and a bottom of the contact part <NUM> is higher than that of the insulating layer <NUM>.

Along a first direction, the connecting part <NUM> connects two adjacent contact parts <NUM>. The heights of the connecting part <NUM> and the contact part <NUM> may be same or not. The specific structure of the connecting part <NUM> may be determined according to a specific condition.

Above all, in the embodiments of the present application, the first conductive layer <NUM>, the insulating layer <NUM>, and the second conductive layer <NUM> are stacked sequentially to form the laminated structure <NUM>. At least one of the first conductive layer <NUM> and the second conductive layer <NUM> is a semi-metal layer, which can not only reduce a contact resistance between a laminated structure <NUM> and another structure, but a contact resistance between the first conductive layer <NUM> and/or the second conductive layer <NUM> and the channel layer <NUM>, thereby improving the performance of the semiconductor structure. In addition, the first conductive layer <NUM>, the insulating layer <NUM>, the second conductive layer <NUM>, the channel layer <NUM>, the dielectric layer <NUM>, and the contact part <NUM> form a vertical transistor. Adjusting the height of the laminated structure <NUM> can increase the height of the channel layer <NUM>, which facilitates improving the short-channel effects of the transistor, thereby improving the performance of the semiconductor structure.

In a possible embodiment of the present application, with reference to <FIG>, before the WLs <NUM> extending along the first direction are formed, where the WL <NUM> includes the plurality of contact parts <NUM> and the connecting part <NUM> connecting adjacent contact parts <NUM>, the contact part <NUM> surrounds and is in contact with the side surface of the dielectric layer <NUM>, and the contact part <NUM> is opposite to at least a part of the insulating layer <NUM>, the manufacturing method further includes: filling a first support layer <NUM> between the laminated structures <NUM> covered by the channel layer <NUM> and the dielectric layer <NUM>, where a surface of the first support layer <NUM> away from the substrate <NUM> is higher than that of the first conductive layer <NUM> away from substrate <NUM>, and is lower than a surface of the insulating layer <NUM> away from the substrate <NUM>.

As shown in <FIG>, the first support layer <NUM> may be used as a cushion layer to increase the pitch between the WL <NUM> formed subsequently and the substrate <NUM>, such that the bottom surface of the WL <NUM> is higher than the top surface of the first conductive layer <NUM>, that is, the surface of the WL <NUM> facing the substrate <NUM> is higher than the surface of the first conductive layer <NUM> away from the substrate <NUM>. In this case, the surface of the first support layer <NUM> away from the substrate <NUM> is lower than the surface of the insulating layer <NUM> away from the substrate <NUM>, such that the bottom surface of the WL <NUM> is lower than the top surface of the first conductive layer <NUM>, thereby ensuring that the WL <NUM> is opposite to the insulating layer <NUM>. The material of the first support layer <NUM> may be silicon nitride or silicon oxynitride, and the first support layer <NUM> and the dielectric layer <NUM> have a relatively large selectivity. For example, the selectivity of the first support layer <NUM> to the dielectric layer <NUM> is greater than <NUM>, to avoid damaging the dielectric layer <NUM> when the first support layer <NUM> is etched, thereby reducing damage on the gate oxide layer in the transistor.

In a possible implementation of the present application, with reference to <FIG>, the filling a first support layer <NUM> between the laminated structures <NUM> covered by the channel layer <NUM> and the dielectric layer <NUM>, where a surface of the first support layer <NUM> away from the substrate <NUM> is higher than that of the first conductive layer <NUM> away from the substrate <NUM>, and is lower than a surface of the insulating layer <NUM> away from the substrate <NUM> may include the following process:
A first initial support layer <NUM> is formed on the dielectric layer <NUM>, where the first initial support layer <NUM> is filled between the laminated structures <NUM> covered by the channel layer <NUM> and the dielectric layer <NUM>, and the first initial support layer <NUM> covers a top surface of the dielectric layer <NUM>. As shown in <FIG>, the first initial support layer <NUM> is formed through deposition and is filled between the laminated structures <NUM> covered by the channel layer <NUM> and the dielectric layer <NUM>. The first initial support layer <NUM> further covers the top surface of the dielectric layer <NUM>. Specifically, the upper surface of the first initial support layer <NUM> is higher than the upper surface of the dielectric layer <NUM>.

After the first initial support layer <NUM> is formed, a part of the first initial support layer <NUM> is removed, and the retained first initial support layer <NUM> forms the first support layer <NUM>. As shown in <FIG>, along a direction perpendicular to the substrate <NUM>, a part of the first initial support layer <NUM> is removed through dry etching or wet etching. The part of the first initial support layer <NUM> located between the laminated structures <NUM> covered by the channel layer <NUM> and the dielectric layer <NUM> is retained. The retained first initial support layer <NUM> forms the first support layer <NUM>.

Based on the foregoing embodiments, after the first support layer <NUM> is formed, in a possible embodiment, with reference to <FIG>, the WLs <NUM> extending along the first direction are formed, where the WL <NUM> includes the plurality of contact parts <NUM> and the connecting part <NUM> connecting adjacent contact parts <NUM>, the contact part <NUM> surrounds and is in contact with the side surface of the dielectric layer <NUM>, and the contact part <NUM> is opposite to at least a part of the insulating layer <NUM>, which may include the following steps:
Step S1041: Form an initial WL layer covering the first support layer and the dielectric layer.

With reference to <FIG> and <FIG>, the initial WL layer <NUM> is formed through a deposition process, and covers the first support layer <NUM> and the dielectric layer <NUM>. As shown in <FIG> and <FIG>, the initial WL layer <NUM> covers the top surface of the first support layer <NUM>, and covers the side surface and the top surface of the dielectric layer <NUM>. There is also a gap in the initial WL layer <NUM> covering the side surfaces of the dielectric layer <NUM>, that is, the initial WL layer <NUM> is not filled between the laminated structures <NUM> covered by the channel layer <NUM> and the dielectric layer <NUM>.

Step S1042: Remove a part of the initial WL layer located on the first support layer along the first direction, such that the initial WL layer is divided, to form a plurality of intermediate WL layers arranged at intervals.

With reference to <FIG>, the part of the initial WL layer <NUM> located on the first support layer <NUM> is removed, such that the initial WL layer <NUM> is divided, to form the plurality of intermediate WL layers <NUM> arranged at intervals. The intermediate WL layers <NUM> extend along the first direction, that is, a part of the initial WL layer <NUM> on the first support layer <NUM> is removed along the first direction, the retained initial WL layer <NUM> forms the intermediate WL layers <NUM>.

Specifically, as shown in <FIG>, the part of the initial WL layer <NUM> located on the first support layer <NUM> is removed along the first direction, such that the initial WL layer <NUM> forms the plurality of intermediate WL layers <NUM> arranged at intervals, which may further include the following process:
A mask layer <NUM> covering the initial WL layer <NUM> is formed and is filled between the laminated structures <NUM> covered by the channel layer <NUM>, the dielectric layer <NUM>, and the initial WL layer <NUM>. The mask layer <NUM> covers the top surface of the initial WL layer <NUM>. As shown in <FIG> and <FIG>, the mask layer <NUM> is deposited on the initial WL layer <NUM>. The mask layer <NUM> is filled between the laminated structures <NUM> covered by the channel layer <NUM>, the dielectric layer <NUM>, and the initial WL layer <NUM>. The mask layer <NUM> further covers the top surface of the initial WL layer <NUM>. The top surface of the mask layer <NUM> is higher than the top surface of the initial WL layer <NUM>.

After the mask layer <NUM> is formed, a first photoresist layer <NUM> is formed thereon. The first photoresist layer <NUM> is provided with a trench <NUM> extending along the first direction, and orthographic projection of the trench <NUM> on the substrate <NUM> and that of the initial WL layer <NUM> on the side surface of the laminated structure <NUM> on the substrate <NUM> do not overlap. As shown in <FIG> and <FIG>, the first photoresist layer <NUM> is spin-coated on the mask layer <NUM>. The first photoresist layer <NUM> is provided with a trench <NUM> running through the first photoresist layer <NUM>. The trench <NUM> is staggered from the initial WL layer <NUM> on the side surface and the top surface of the dielectric layer <NUM>, and is opposite to a part of the initial WL layer <NUM> on the first support layer <NUM>.

After the first photoresist layer <NUM> is formed, the mask layer <NUM> is etched by using the first photoresist layer <NUM> as a mask. The mask layer <NUM> is etched by using the first photoresist layer <NUM> as a mask. The pattern on the first photoresist layer <NUM> is transferred to the mask layer <NUM>. As shown in <FIG> and <FIG>, the initial WL layer <NUM> is exposed from the pattern formed by the mask layer <NUM>.

After the mask layer <NUM> is etched, the initial WL layer <NUM> is etched by using the etched mask layer <NUM> as a mask, to form the intermediate WL layers <NUM>. A part of the initial WL layer <NUM> on the first support layer <NUM> is removed through anisotropic etching. As shown in <FIG>, the retained initial WL layer <NUM> forms intermediate WL layers <NUM>. Gaps between a plurality of intermediate WL layers <NUM> expose the first support layer <NUM>.

Step S1043: Remove the intermediate WL layer on a top surface of the dielectric layer, and a part of the intermediate WL layer away from the substrate on the side surface of the dielectric layer, and taking the retained intermediate WL layers as the WLs.

The intermediate WL layer <NUM> on a top surface of the dielectric layer <NUM> and a part of the intermediate WL layer <NUM> on the side surface of the dielectric layer <NUM> are removed through etching. The retained intermediate WL layers <NUM> form the WLs <NUM>. As shown in <FIG>, the top surface of the WL <NUM> is lower than the top surface of the insulating layer <NUM>, and the WL <NUM> is opposite to the insulating layer <NUM>.

In another possible embodiment of the present application, after the WLs <NUM> extending along the first direction are formed, where the WL <NUM> includes the plurality of contact parts <NUM> and the connecting part <NUM> connecting adjacent contact parts <NUM>, the contact part <NUM> is connected to the laminated structure <NUM>, and the contact part <NUM> surrounds the side surface of the dielectric layer <NUM>, with reference to <FIG>, the manufacturing method of the semiconductor structure further includes:
forming a second support layer <NUM> covering the WLs <NUM>, the first support layer <NUM>, and the second support layer <NUM> on the dielectric layer <NUM>. As shown in <FIG>, the second support layer <NUM> is deposited. The second support layer <NUM> covers the WLs <NUM>, the first support layer <NUM>, and the dielectric layer <NUM>. The top surface of the second support layer <NUM> is higher than the top surface of the dielectric layer <NUM>. The surface of the second support layer <NUM> away from the substrate <NUM> may be flat. For example, the second support layer <NUM> is flattened, through, for example, chemical mechanical polishing (CMP), to make the top surface of the second support layer <NUM> flat. The second support layer <NUM> and the first support layer <NUM> may be made of a same insulating material, such that the second support layer <NUM> is integrated with the first support layer <NUM>. The second support layer <NUM> and the first support layer <NUM> cover and isolate the WLs <NUM> to insulate the WLs <NUM>.

After the second support layer <NUM> is formed, the second photoresist layer <NUM> is formed on the second support layer <NUM>. The second photoresist layer <NUM> is provided with a plurality of openings <NUM>. The openings <NUM> are opposite to the laminated structures <NUM>. As shown in <FIG>, the second photoresist layer <NUM> is formed on the second support layer <NUM>. The second photoresist layer <NUM> is provided with a plurality of openings <NUM>. The plurality of openings <NUM> correspond to the plurality of laminated structures <NUM> respectively, and the opening <NUM> is opposite to the laminated structure <NUM> corresponding thereto. Orthographic projection of the opening <NUM> on the substrate <NUM> is located within that of the laminated structure <NUM> corresponding thereto on the substrate <NUM>, or the orthographic projection of the opening <NUM> on the substrate <NUM> overlaps with that of the laminated structure <NUM> corresponding thereto on the substrate <NUM>.

After the second photoresist layer <NUM> is formed, the second support layer <NUM>, the dielectric layer <NUM>, and the channel layer <NUM> are etched by using the second photoresist layer <NUM> as a mask, to form the contact hole <NUM>. The contact hole <NUM> exposes the second conductive layer <NUM>. As shown in <FIG>, the contact hole <NUM> runs through the second support layer <NUM>, the dielectric layer <NUM>, and the channel layer <NUM>, to expose the second conductive layer <NUM>. The second photoresist layer <NUM> is removed while the contact hole <NUM> is formed, or the second photoresist layer <NUM> is removed after the contact hole <NUM> is formed. As shown in <FIG>, after the second photoresist layer <NUM> is removed, the top surface of the second support layer <NUM> is exposed.

It should be noted that an area of an opening <NUM> at the contact hole <NUM> is greater than that of a bottom of the contact hole <NUM>, that is, a width of an upper part of the contact hole <NUM> is relatively large while a width of its lower part is relatively small. Through such a disposal, after the third conductive layer <NUM> is formed in the contact hole <NUM>, a width of an upper part of the third conductive layer <NUM> is relatively large. Adding the width of the operation window facilitates the alignment with the capacitor. In addition, the width of the lower part of the third conductive layer <NUM> is relatively small, which can reduce the critical dimension of the transistor.

For example, a plane perpendicular to the substrate <NUM> is used as a cross section. A shape of a cross section of the contact hole <NUM> may be an inverted trapezoid with a large top and a small bottom. As shown in <FIG>, the shape of the cross section of the contact hole <NUM> may be also a rectangle and a trapezoid that are connected to each other. The rectangle is disposed at one side of the trapezoid close to the substrate <NUM>, and a bottom edge of the rectangle coincides with an upper bottom of the trapezoid.

After the contact hole <NUM> is formed, the third conductive layer <NUM> is formed in the contact hole <NUM>, and the third conductive layer <NUM> is electrically connected to the second conductive layer. As shown in <FIG>, the third conductive layer <NUM> is deposited in the contact hole <NUM>, and the third conductive layer <NUM> is in contact with the second conductive layer <NUM>, such that the third conductive layer <NUM> is electrically connected to the second conductive layer <NUM>. The third conductive layer <NUM> may be a capacitive contact pad, and a capacitor is formed on the third conductive layer <NUM>.

With reference to <FIG>, an embodiment of the present application further provides a semiconductor structure, including: laminated structures <NUM>, a channel layer <NUM>, a dielectric layer <NUM>, and a gate. The laminated structures <NUM> are disposed on the substrate <NUM>. The substrate <NUM> is configured to support the laminated structures <NUM>. The substrate <NUM> may be a semiconductor substrate such as a silicon substrate.

A plurality of BLs <NUM> may be also disposed in the substrate <NUM>, are spaced apart from each other, and extend along the second direction (the direction X shown in <FIG>). The BLs <NUM> may be exposed on the surface of the substrate <NUM>, to be electrically connected to another structure on the substrate <NUM>. An STI structure <NUM> may also be disposed between adjacent BLs <NUM>, which are isolated by the STI structure structures <NUM>.

The plurality of laminated structures <NUM> are formed on the substrate <NUM>, and are disposed at intervals. The laminated structure <NUM> includes a first conductive layer <NUM>, an insulating layer <NUM>, and a second conductive layer <NUM> that are stacked. As shown in <FIG>, along the direction away from the substrate <NUM>, the first conductive layer <NUM>, the insulating layer <NUM>, and the second conductive layer <NUM> are disposed sequentially. One of the first conductive layer <NUM> and the second conductive layer <NUM> is a source, the other of the first conductive layer <NUM> and the second conductive layer <NUM> is a drain. At least one of the source and the drain is a semi-metal layer. The material of the semi-metal layer may be bismuth, and the material of the insulating layer <NUM> may be silicon oxide. Disposing at least one of the source or the drain as a semi-metal layer can reduce the contact resistance between the laminated structure <NUM> and another structure (for example, the BL <NUM> and/or the capacitor), thereby improving the performance of the semiconductor structure.

With reference to <FIG>, along the second direction, at least one of the laminated structures <NUM> is disposed on each of the BLs <NUM>, and one of the source and the drain in the laminated structure <NUM> is in contact with the BL <NUM>, such that the source or drain is electrically connected to the BL <NUM>. The laminated structure <NUM> may be in a shape of a column, such as a cylinder, an elliptical column, a square column, or a rectangular column. The laminated structures <NUM> may be arranged in an array.

The channel layer <NUM> covers the side surface of the laminated structure <NUM>. The channel layer <NUM> surrounding the side surface of the laminated structure <NUM> forms a channel region, to provide a conductive channel between the source and the drain, such that carriers can move from the source to the drain or vice versa. The channel region is layered. A material of the channel layer <NUM> may include molybdenum sulfide, such as molybdenum disulfide. There is a band gap in the layered molybdenum sulfide, which forms a field effect transistor with a high on-off ratio. Preferably, the material of the channel layer <NUM> is molybdenum sulfide, and the materials of the source and the drain are both bismuth, to reduce the MIGSs and energy barriers between the channel layer <NUM> and the source, and between the channel layer <NUM> and the drain, thereby reducing the contact resistances between the channel layer <NUM> and the source and between the channel layer <NUM> and the drain.

The dielectric layer <NUM> covers the side surface of the channel layer <NUM> and may be an oxide layer. The dielectric layer <NUM> located on the side surface of the channel layer <NUM> forms a gate oxide layer. For example, the dielectric layer <NUM> is made of silicon oxide.

Withe reference to <FIG>, a gate is annularly provided on the dielectric layer <NUM>. The gate surrounds and is in contact with the side surface of the dielectric layer <NUM>. The gate is opposite to at least a part of the insulating layer <NUM>. Along a direction (the direction Z shown in <FIG>) perpendicular to the substrate <NUM>, the orthographic projection of the dielectric layer <NUM> at least partially overlaps with that of the gate. For example, the top surface of the gate is lower than the top surface of the dielectric layer <NUM>, and the bottom surface of the gate is higher than the bottom surface of the dielectric layer <NUM>.

The semiconductor structure in the embodiments of the present application further includes WLs <NUM>. The WLs <NUM> extend along the first direction. The WL <NUM> includes contact parts <NUM> and a connecting part <NUM> connecting two adjacent contact parts <NUM>. The contact part <NUM> is a gate disposed annularly on the dielectric layer <NUM>, that is, a part of the WL <NUM> is a gate. It can be understood that, along the first direction, the connecting part <NUM> and the gate are arranged at intervals, and the connecting part <NUM> connects the plurality of gates in the first direction into one to form the WLs <NUM>.

In some possible examples, with reference to <FIG>, the WL <NUM> is disposed on the first support layer <NUM>. The first support layer <NUM> is located below the WL <NUM> and is filled between laminated structures <NUM> covered by the dielectric layer <NUM> and the channel layer <NUM>, to elevate the WLs <NUM>. The second support layer <NUM> may further cover the WLs <NUM>, and the second support layer <NUM> and the first support layer <NUM> electrically isolate the WLs <NUM>. The second support layer <NUM> and the first support layer <NUM> may be made of a same material, such that the second support layer <NUM> is integrated with the first support layer <NUM>.

With reference to <FIG>, the second support layer <NUM> also covers the dielectric layer <NUM>. The second support layer <NUM> is provided with a contact hole running through the dielectric layer <NUM> and the channel layer <NUM>, to expose the second conductive layer <NUM> in the laminated structures <NUM>. The third conductive layer <NUM> fills the contact hole, and one end of the third conductive layer <NUM> is in contact with the second conductive layer <NUM>, such that the third conductive layer <NUM> is electrically connected to the second conductive layer <NUM>. The other end of the third conductive layer <NUM> may be connected to a capacitor.

In the semiconductor structure provided by the embodiments of the present application, the first conductive layer <NUM>, the insulating layer <NUM>, and the second conductive layer <NUM> are stacked sequentially to form the laminated structure <NUM>. One of the first conductive layer <NUM> and the second conductive layer <NUM> is the source and the other is the drain. At least one of the first conductive layer <NUM> and the second conductive layer <NUM> is a semi-metal layer, which can not only reduce a contact resistance between a laminated structure <NUM> and another structure, but a contact resistance between the first conductive layer <NUM> and/or the second conductive layer <NUM> and the channel layer <NUM>, thereby improving the performance of the semiconductor structure. In addition, the channel layer <NUM> covers the side surface of the laminated structure <NUM>. The dielectric layer <NUM> covers the side surface of the channel layer <NUM>. A gate is annularly provided on the dielectric layer <NUM>. The laminated structures <NUM>, the channel layer <NUM>, the dielectric layer <NUM>, and the gate form a vertical transistor. Adjusting the height of the laminated structure <NUM> can increase the height of the channel layer <NUM>, which facilitates improving the short-channel effects of the transistor, thereby improving the performance of the semiconductor structure.

The embodiments or implementations of this specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments. The same or similar parts between the embodiments may refer to each other.

In the descriptions of this specification, a description with reference to the term "one implementation", "some implementations", "an exemplary implementation", "an example", "a specific example", "some examples", or the like means that a specific feature, structure, material, or characteristic described in combination with the implementation(s) or example(s) is included in at least one implementation or example of the present application. In this specification, the schematic expression of the above terms does not necessarily refer to the same embodiment or example. Moreover, the described specific feature, structure, material or characteristic may be combined in an appropriate manner in any one or more implementations or examples.

Claim 1:
A manufacturing method of a1T-1C DRAM , comprising:
providing a substrate (<NUM>) (S101);
forming a plurality of laminated structures (<NUM>) arranged at intervals on the substrate (<NUM>), wherein each of the laminated structures (<NUM>) comprises a first conductive layer (<NUM>), an insulating layer (<NUM>), and a second conductive layer (<NUM>) that are stacked sequentially, and at least one of the first conductive layer (<NUM>) and the second conductive layer (<NUM>) is bismuth (S102);
forming a channel layer (<NUM>) covering the laminated structures (<NUM>), and a dielectric layer (<NUM>) covering the channel layer (<NUM>) (S103); and
forming word lines, WLs, (<NUM>) extending along a first direction (Y), wherein the WL (<NUM>) comprises a plurality of contact parts (<NUM>) and a connecting part (<NUM>) connecting adjacent contact parts (<NUM>), the contact part (<NUM>) surrounds and is in contact with a side surface of the dielectric layer (<NUM>), and the contact part (<NUM>) is opposite to at least a part of the insulating layer (<NUM>) (S104).