Patent Description:
Molecules and subatomic particles follow the laws of quantum mechanics, a branch of physics that explores how the physical world works at a fundamental level. At this level, particles behave in strange ways, taking on more than one state at the same time, and interacting with other particles that are very far away. Quantum computing harnesses these quantum phenomena to process information.

Many quantum devices suitable for use in quantum computing require low or extremely low temperatures in order to function. If the temperature rises above those levels, errors are introduced to the quantum computing process. Traditional vapor compression coolers, however, are bulky, expensive, and not completely reliable to maintain the array of devices at those temperatures.

<NPL> shows a microrefrigerator with a comb-like shaped aluminum structure and a Y shaped copper structure. <NPL> shows a double-array NIS cooler. <CIT> states that in a NIS device normal regions can be regions of metal-like conductivity and gives silver as an example. <CIT> shows an assembly of a quantum electric device, a normal-metal-insulator superconductor tunnel junction, and a superconductive lead formed on a substrate or wafer.

According to one or more embodiments, an active cooling structure, comprising a non-superconducting layer, a superconducting layer, and an array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions. The non-superconducting layer may comprise a plurality of non-superconducting traces. The superconducting layer may comprise a plurality of superconducting traces. The array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions may be located between the plurality of non-superconducting traces and the plurality of superconducting traces.

According to one or more embodiments, a quantum processor, comprising a first substrate, a plurality of qubits formed on the first substrate, and an active cooling structure in thermal communication with the qubits. The active cooling structure may comprise a non-superconducting layer, a superconductor layer, and an insulator layer between the non-superconducting layer and the superconductor layer.

The quantum processor may further comprise for example at least one or more of the following features:.

The active cooling structure may comprise a grid of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer may comprise a plurality of non-superconducting traces may run in a first direction; and the superconductor layer may comprise a plurality of superconducting traces running in a second direction. The plurality of superconducting traces and the plurality of non-superconducting traces may intersect at a plurality of locations in the X-Y plane.

The non-superconducting layer may comprise silver, the insulator layer may be chosen from the group consisting of silicon dioxide and hafnium dioxide, and the superconductor layer may be chosen from the group consisting of aluminum and niobium.

In an example, the non-superconducting layer comprises silver, the insulator layer comprises silicon dioxide, and the superconductor layer comprises aluminum. In another example, the non-superconducting layer comprises silver, the insulator layer comprises silicon dioxide, and the superconductor layer comprises niobium. In another example, the non-superconducting layer comprises silver; the insulator layer comprises hafnium dioxide; and the superconductor layer comprises aluminum. In another example, the non-superconducting layer comprises silver, the insulator layer comprises hafnium dioxide, and the superconductor layer comprises niobium.

According to one or more embodiments, a method of cooling a quantum processor to extreme low temperatures, comprising applying a voltage an active cooling structure in thermal communication with a quantum processor. The active cooling structure may comprise a non-superconducting layer, a superconductor layer, and an insulator layer between the non-superconducting layer and the superconductor layer.

According to one or more embodiments, a method for fabricating an active cooling structure, comprising forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer is provided. The non-superconducting layer may comprise a plurality of non-superconducting traces running in a first direction. The superconductor layer may comprise a plurality of superconducting traces running in a second direction.

The method for fabricating the active cooling structure may further comprise for example at least one or more of the following features:.

The fabrication method may comprise forming a first plurality of pads that electrically connect the plurality of superconducting traces in parallel and forming a second plurality of pads that electrically connect the non-superconducting traces in parallel.

The fabrication method may comprise applying a photoresist layer to a substrate, exposing the photoresist layer in a pattern to create exposed photoresist and unexposed photoresist, removing the exposed photoresist layer, applying the metal layer onto the unexposed photoresist and the substrate; and removing the unexposed photoresist.

The fabrication method may comprise forming an insulator layer on the non-superconducting layer.

The fabrication method may comprise applying a lift-off resist layer to the insulator layer, exposing the lift-off resist layer in a pattern to create exposed lift-off resist and unexposed lift-off resist, removing the exposed lift-off resist layer, applying the superconducting layer onto the unexposed lift-off resist layer and the insulator layer, and removing the unexposed lift-off resist.

According to one or more embodiments, a fabrication method for a quantum processor, comprising forming a plurality of qubits formed on a first substrate, and forming an active cooling structure in thermal communication with the qubits is provided. The active cooling structure may comprise a non-superconducting metal layer, an insulator layer formed on top of the non-superconducting layer, and a superconductor layer formed on top of the insulator layer.

The fabrication method for a quantum processor may further comprise for example at least one or more of the following features:.

The fabrication method may comprise applying a photoresist layer to a substrate; exposing the photoresist layer in a pattern to create exposed photoresist and unexposed photoresist; removing the exposed photoresist layer; applying the metal layer onto the unexposed photoresist and the substrate, and removing the unexposed photoresist.

According to one or more embodiments, a semiconductor fabrication system for fabricating a thermalization structure is provided. The semiconductor fabrication system may comprise a computer readable storage media having a set of instructions for a fabrication facility encoded thereon which, when operated by a processor, causes a fabrication method to be performed. The fabrication method may comprise forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer may comprise a plurality of non-superconducting traces running in a first direction and the superconductor layer may comprise a plurality of superconducting traces running in a second direction.

The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

The drawings included in the present application are incorporated into, and form part of, the specification. They illustrate embodiments of the present disclosure and, along with the description, serve to explain the principles of the disclosure. The drawings are only illustrative of certain embodiments and do not limit the disclosure.

While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the invention as defined by the claims.

A "low temperature" range, as used herein, refers to a cryogenic temperature range, which starts at or about <NUM> Kelvin (K). "Extreme low temperature" starts at or about <NUM> Kelvin and extends down to at least <NUM> millikelvin (<NUM>), and in some cases as low as possible using available technology, currently around <NUM>.

A "low temperature device" (LTD) is a device operating in a low or extreme low temperature range. Most LTDs operating at low or extreme temperatures rely on materials that exhibit superconducting properties at those temperatures.

Aspects of the present disclosure relate to a cooling apparatus and fabrication method for low temperature electronic devices, more particular aspects relate to active cooling for low temperature and extremely low temperature superconducting devices. While the present disclosure is not necessarily limited to such applications, various aspects of the disclosure may be appreciated through a discussion of various examples using this context.

LTD devices, including superconducting devices, produce heat when operating. Heat removal in such cryogenic temperature ranges, however, poses unique challenges.

Some embodiments package active, solid state cooling devices near or in contact with the LTD devices in the cooling chamber of a dilution refrigerator to assist in maintaining the LTD devices at low or extremely low temperatures. Some embodiments may also allow for reduction in some of the other cooling structures and may improve overall reliability.

Most of the computers used today are known as classical computers. A classical computer uses a conventional processor fabricated using semiconductor materials and technology, a semiconductor memory, and a magnetic or solid-state storage device, in what is known as a Von Neumann architecture. Particularly, the processors in conventional computers are binary processors, i.e., operating on binary data represented in <NUM> and <NUM>. A quantum processor (q-processor), in contrast, uses the odd nature of entangled qubit devices (compactly referred to herein as "qubit," plural "qubits") to perform computational tasks. In the particular realm where quantum mechanics operates, particles of matter can exist in multiple states-such as an "on" state, an "off" state, and both "on" and "off" states simultaneously. Where binary computing using semiconductor processors is limited to using just the on and off states (equivalent to <NUM> and <NUM> in binary code), a quantum processor harnesses these quantum states of matter to output signals that are usable in data computing.

Classical computers encode information in bits. Each bit can take the value of <NUM> or <NUM>. These <NUM> and <NUM> act as on/off switches that ultimately drive computer functions. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent both a <NUM> and a <NUM> at the same time. Entanglement means that qubits in a superposition can be correlated with each other in a non-classical way; that is, the state of one (whether it is a <NUM> or a <NUM> or both) can depend on the state of another, and that there is more information that can be ascertained about the two qubits when they are entangled than when they are treated individually.

Using these two principles, qubits operate as more sophisticated processors of information, enabling quantum computers to function in ways that allow them to solve difficult problems that are intractable using conventional computers.

Superconducting qubits, in turn, generally use one or more layers of different materials to implement the device properties and function. A layer of material can be superconductive, conductive, semi-conductive, insulating, resistive, inductive, capacitive, or have any number of other properties. Different layers of materials may have to be formed using different methods, given the nature of the material, the shape, size or placement of the material, other materials adjacent to the material, and many other considerations.

Most quantum devices suitable for use as qubits in quantum computing require low or extremely low temperatures in order to function.

<FIG> depicts a block diagram of a network of data processing environment in which illustrative embodiments may be implemented. The data processing environment <NUM> is a network of computers in which the illustrative embodiments may be implemented. The data processing environment <NUM> includes a network <NUM>. The network <NUM> is the medium used to provide a communications links between the various devices and computers connected together within the data processing environment <NUM>. The network <NUM> may include connections, such as wire, wireless communication links, or fiber optic cables.

The data processing environment <NUM> includes a plurality of clients <NUM>, <NUM>, <NUM>, <NUM> and a plurality of servers <NUM>, <NUM> that commutatively couple via the network <NUM> with a storage unit <NUM>. The clients <NUM>, <NUM>, <NUM>, servers <NUM>, <NUM>, and storage unit <NUM> depicted in <FIG> are devices described with only example roles of certain data processing systems connected to the network <NUM> and are not intended to exclude other configurations or roles for these data processing systems. Any of the components in the data processing environment <NUM>, such as server <NUM> or <NUM>, or client <NUM>, <NUM>, <NUM>, or <NUM> may contain data and may have software applications and/or software tools <NUM> executing thereon.

Device <NUM> and client <NUM> are examples of client devices. For example, the devices <NUM> can take the form of a smartphone, a tablet computer, a laptop computer, a wearable computing device, appliance, or as any other suitable device. Software applications and/or tools <NUM> described as executing in another data processing system in <FIG> may, in some embodiments, be configured to execute in the device <NUM> in a similar manner. Data or information stored or produced in another data processing system in <FIG> may, in some embodiments, be configured to be stored or produced in the device <NUM> in a similar manner.

Photolithography application 105a may be used to implement or partially implement some embodiments described herein. In those embodiments, the photolithography application 105a is a software component of a system for fabricating an active planar cooling structure, a Josephson junction, a qubit, and/or other superconducting structures used in quantum computing devices. Photolithography application 105a provides instructions to such a fabrication system for causing the assembly of some novel cryogenic methods and systems contemplated in some embodiments described herein.

<FIG> illustrates a top view of an example active planar cooling structure <NUM> consistent with some embodiments. <FIG> illustrates the example cooling structure <NUM> of <FIG>, sectioned along line B. The cooling structure <NUM> embodiment in <FIG> comprises a superconductor layer <NUM> and a normal metal (i.e., non-superconducting) layer <NUM> separated by an insulator layer <NUM>. The superconductor layer <NUM> in some embodiments is formed into a plurality of generally parallel superconductor traces <NUM> (only some labeled for clarity) running in a first direction (Y direction as depicted). The superconductor traces <NUM> may be electrically connected to common pads 214a and 214b. The normal metal layer <NUM> is similarly formed into a plurality of generally parallel normal metal traces <NUM> (only some labeled for clarity) running in a second direct, orthogonal to the first direction (X direction as depicted). The normal metal traces <NUM> are electrically connected to common pads 224a and 224b. In some embodiments, the superconductor layer <NUM> is formed first, on top of (i.e., adjacent to) a substrate <NUM>, with the normal metal layer <NUM> later formed on top of (i.e., adjacent to) the insulator layer <NUM>. In other embodiments, the normal metal layer <NUM> is formed first, on top of (i.e., adjacent to) the substrate <NUM>, with the superconductor layer <NUM> later formed on top of (i.e., adjacent to) the insulator layer <NUM>.

An array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures <NUM> (only some labeled for clarity) are formed in a grid pattern at the intersections (in the X-Y plane) of the superconductor traces <NUM> and the normal metal traces <NUM>. Example cooling structure <NUM> also comprises a plurality of electrical contacts <NUM> (only some labeled for clarity) and may be created on a surface of a substrate <NUM>.

In some embodiments, when a small potential (bias voltage V) is applied between the superconductor layer <NUM> and the normal metal layer <NUM>, the relatively higher energy ("hot") electrons can traverse the dielectric between the two layers. Relatively lower energy ("cold") electrons, in contrast, are unable to traverse the dielectric. Together, this has the effect of transferring heat energy away from a heat source, such as a quantum device or interface electronics.

In some embodiments, the normal metal layer may be any substance that is compatible with substrate <NUM> and with any manufacturing processes subsequently required to form the rest of the structure <NUM> (see <FIG>) and/or the cooled device (see <FIG>). In some embodiments and for some applications, it may also desirable that the normal metal layer to fail to act as a superconductor at the chosen low and/or extreme low operating temperatures, yet still be a good normal conductor to reduce heat added to the system via resistance, and that the normal metal layer be non-magnetic to avoid interference with the qubits. Suitable normal metals include, but are not limited to, silver, gold, copper, platinum, and palladium.

The superconductor layer <NUM> in some embodiments may be any substance that exhibits superconducting properties at the chosen low and/or extremely low operating temperature, is compatible with the other chosen materials, and with any manufacturing processes used. Suitable superconducting materials for some embodiments and some applications include, but are not limited to, aluminum, niobium, tantalum, titanium, tantalum nitride, titanium nitride, vanadium, lead, tin, and gallium. The insulator layer <NUM> may be any substance that acts as a dielectric between the superconducting metal layer <NUM> and the normal layer <NUM> at the low and/or extremely low operating temperature, as well as being compatible with the other chosen materials and manufacturing processes. For some embodiments and some applications, suitable such substances include silicon dioxide (SiO<NUM>), Hafnium dioxide (HfO<NUM>), and aluminum oxide (Al<NUM>O<NUM>). Various nitrides may also be suitable for some embodiments and some applications, such as silicon nitride, hafnium nitride, aluminum nitride, and zirconium nitride.

<FIG> illustrates another example active planar cooling structure 200c consistent with some embodiments. The active planar cooling structure 200c in <FIG> also comprises a superconductor layer <NUM> and a normal metal (i.e., non-superconducting) layer <NUM> separated by an insulator layer <NUM>. The superconductor layer <NUM> and normal metal layer <NUM> in <FIG>, however, each comprise a single flat plane <NUM>, <NUM> of superconductor material or normal metal, respectively. As with the embodiment in <FIG>, a NIS tunnel structure <NUM> is formed where the two planes <NUM>, <NUM> overlap. This active planar cooling structure embodiment 200c may be desirable for active cooling in space-constrained locations, such as the active planar cooling structure <NUM> in <FIG>.

<FIG> and <FIG> illustrate an example actively cooled quantum processor <NUM>, consistent with some embodiments. The quantum processor 300a in <FIG> comprises four active planar cooling structures <NUM>, elongated and arranged around a periphery of a cooled device, such as quantum processor <NUM>. The quantum circuit <NUM>, in turn, comprises a plurality of quantum devices, such as qubits <NUM> (only some labeled for clarity). The quantum processor 300B in <FIG> comprises five active planar cooling structures <NUM>, <NUM>. Four of the active planar cooling structures <NUM> are elongated and arranged around a periphery of the cooled device, such as quantum processor <NUM>, similar to <FIG>. The fifth active planar cooling structure <NUM> is placed within the periphery of the cooled device, such as between two groups of qubits <NUM>.

In both <FIG> and <FIG>, the active planar cooling structures <NUM> are formed directly on the same surface (e.g., top surface) of a substrate <NUM>, alongside and/or in between the qubits <NUM> that make up the quantum circuit <NUM>. These arrangements may be desirable because the active planar cooling structures <NUM> can be formed at the same time, using the same manufacturing processes, as the quantum circuit <NUM>. This arrangement may also be desirable because the active planar cooling structures <NUM> are physically located in close proximity to the quantum devices.

<FIG> illustrates another example actively cooled quantum processor <NUM>, consistent with some embodiments of the invention. The quantum processor <NUM> comprises a generally square shaped, active planar cooling structure <NUM> formed on one surface (e.g., bottom) of a substrate <NUM>. On the opposite surface (e.g., top), a plurality of quantum devices <NUM> (only some labeled for clarity) have been formed, which may be combined to form a quantum circuit <NUM>.

<FIG> illustrates another example actively cooled quantum processor <NUM>. In this example, the active planar cooling structure <NUM> is formed on one substrate 560a and the quantum devices <NUM> (only one labeled for clarity) that make up the quantum circuit <NUM> are formed on a second substrate 560b. The two substrates 560a and 560b are then bonded, mechanically clamped, or otherwise joined together back-to-back. These quantum processor embodiments <NUM> and <NUM> may be desirable because they can provide wider choices in materials and manufacturing processes.

<FIG> illustrates another example actively cooled quantum processor 600a, consistent with some embodiments of the invention. The quantum processor <NUM> in <FIG> comprises two active planar cooling structures, one 602a formed on one surface (e.g., bottom) of a first substrate 660a and one 602b formed on one surface (e.g., top) of a second substrate 660b. The two substrates 660a and 660b in this embodiment may be bonded, clamped, or otherwise joined together, such that the two substrates 660a, 660b sandwich the quantum devices <NUM> (only one labeled for clarity) that make up a quantum circuit <NUM>. <FIG> illustrates another example actively cooled quantum processor 600b, consistent with some embodiments of the invention. In this quantum processor 600b embodiment, the top active planar cooling structure 602b is on the surface of the substrate 660b that is closest to (i.e., faces toward) the quantum devices <NUM> (only one labeled for clarity) that make up a quantum circuit <NUM>.

<FIG> also includes a plurality of spacers <NUM> that prevent physical contact with the quantum devices <NUM> when the two substrates 660a and 660b are bonded, clamped, or otherwise joined together. The spacers <NUM> may optionally include channels (not shown) to allow passage of refrigerant (e.g., liquid hydrogen or helium) into and through a passageway <NUM> between the quantum circuit <NUM> and the top active planar cooling structures 602b. The embodiments in <FIG> may be desirable because they can also protect the quantum devices <NUM> and the quantum circuit <NUM>.

<FIG> are device cross sections that depict the devices at various stages of an example process for fabrication of an active plan quantum cooling structure, consistent with some embodiments. As shown in <FIG>, a photoresist layer <NUM> is first deposited on a substrate <NUM>, and then a photoresist pattern for a first layer <NUM> (e.g., a normal metal layer) is then exposed onto the photoresist layer <NUM> using a mask and a light source (not shown). After washing away the exposed/developed photoresist, the material for the first layer of the structure (e.g., the chosen normal metal) can be applied. The remaining unexposed/undeveloped photoresist layer <NUM> may then be dissolved by a solvent appropriate for the chosen material and substrate. <FIG> illustrates the resulting structure.

Next, an insulating layer <NUM> (e.g., SiO2 or HfO2) is deposited over the remaining (i.e., patterned) layer <NUM> of the structure (e.g., the normal metal layer). Suitable methods include, but are not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD). The resulting structure is illustrated in <FIG>. A pattern lift-off resist layer <NUM> may be applied for use in forming the next layer <NUM> of the structure (e.g., a superconductor layer). An inverse pattern may then be exposed onto the resist layer <NUM> using a mask and light source (not shown) and material for the second layer (e.g., the chosen superconductor) may be deposited. The resulting structure is shown in <FIG>. Next, the exposed/developed resist layer <NUM> is washed out, together with any material on its surface, to form the second layer (e.g., superconductor) in the desired shape. Last, electrical contacts (not shown) suitable to the normal metal and/or superconductor arrays are created and packaged in a suitable orientation for installation into a cryo-cooling structure.

<FIG> depict an example computer-implemented process <NUM> for manufacturing an active plan quantum cooling structure consistent with some embodiments. Process <NUM> may, in some embodiments, be implemented in the photolithography application 105a in <FIG>. At block <NUM>, the photolithography application 105a creates a pattern for the first layer <NUM> (e.g., the normal metal layer) of a planer active cooling structure, to be deposited on the substrate <NUM>. Next, at block <NUM>, the photolithography application 105a causes a photoresist layer to be deposited on the substrate <NUM> and exposes to the first pattern to the photoresist layer. At block <NUM>, the photolithography application 105a causes the exposed/developed photoresist to be washed out and appropriate material (e.g., the chosen normal metal) to be applied to the resulting structure. The photolithography application 105a then causes the unexposed/undeveloped photoresist, together with any adjacent normal metal, to be removed at block <NUM>, thus forming a patterned layer <NUM>.

At block <NUM>, the photolithography application 105a causes an insulating layer <NUM> to be deposited over the patterned layer <NUM>. At block <NUM>, the photolithography application 105a creates a pattern for the second (e.g., superconducting) layer <NUM>. The photolithography application 105a then directs the application of a pattern lift-off resist layer <NUM> (at block <NUM>) to the current structure, which is subsequently exposed using a mask and light (at block <NUM>). The photolithography application 105a then causes the second layer <NUM> (e.g., the superconductor layer) to be deposited at block <NUM> over the current structure. At block <NUM>, the photolithography application 105a directs the exposed/developed resist layer <NUM> to be washed out, together with any superconductor on its surface, forming the patterned layer <NUM>. Last, at block <NUM>, the photolithography application 105a causes electrical contacts to be attached to the current structure. Then, the photolithography application 105a ends.

Although the present invention has been described in detail with reference to certain examples thereof, it may be also embodied in other specific forms without departing from the essential spirit or attributes thereof. For example, some embodiments are capable of being distributed as a set of instructions for a fabrication facility ("fab") encoded onto a computer readable storage media (e.g., a Release Interface Tape or "RIT," a "tape-out," a "GDS2," etc.). The computer readable storage medium, in turn, may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.

The computer readable instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network.

Embodiments of the present invention may also be delivered as part of a service engagement with a client corporation, nonprofit organization, government entity, internal organizational structure, or the like. Aspects of these embodiments may also include analyzing specifications from the client entity, creating recommendations responsive to the analysis, generating designs for circuitry that implements some or all of recommendations, delivering fabrication instructions for the designs, and testing the resulting circuitry.

Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the invention as defined by the claims. Although various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings, persons skilled in the art will recognize that many of the positional relationships described herein are orientation-independent when the described functionality is maintained even though the orientation is changed. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer "A" over layer "B" include situations in which one or more intermediate layers (e.g., layer "C") is between layer "A" and layer "B" as long as the relevant characteristics and functionalities of layer "A" and layer "B" are not substantially changed by the intermediate layer(s).

Additionally, the term "illustrative" is used herein to mean "serving as an example, instance or illustration. " Any embodiment or design described herein as "illustrative" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms "a plurality" are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term "connection" can include an indirect "connection" and a direct "connection.

References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic.

Claim 1:
An active cooling structure (<NUM>), comprising:
a non-superconducting layer (<NUM>) comprising a plurality of non-superconducting traces (<NUM>);
a superconducting layer (<NUM>) comprising a plurality of superconducting traces (<NUM>); wherein the plurality of non-superconducting traces (<NUM>) run orthogonal to the plurality of superconducting traces (<NUM>); and
an array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions (<NUM>) between the plurality of non-superconducting traces (<NUM>) and the plurality of superconducting traces (<NUM>); wherein the array comprises a grid of NIS tunnel junctions (<NUM>).