Patent Description:
Power converters, for example for SMPS (Switched-Mode Power Supply) applications, traction inverters (for example for automotive applications, for driving a three-phase traction motor), or in general electrical power systems are known, which envisage the use of power switches (for example, made with SiC, GaN, MOSFET, IGBT technology) to implement transfer of power to an electrical load.

In these electrical systems, galvanic isolation is typically required between a corresponding control stage, which, for example, includes a microcontroller or similar processing unit, which is designed to control operation of the power switches according to a desired logic and operates at low voltage, and a corresponding driving stage, which includes the circuit elements required for driving the same power switches and operates at high voltage.

In particular, the microcontroller, which executes an appropriate control algorithm, is generally required to operate at a certain distance from the power stage in order to prevent any malfunctioning caused by an excessive heat dissipation and by electromagnetic interference (EMI) due to the high-power switching activity.

Galvanic isolation is therefore typically required between the control section and the power section so as to minimise the aforesaid undesired effects and moreover guarantee safety of the operators; based on the applications, the isolation may be of a functional, basic, or double/reinforced type.

In such electrical systems, the use of isolated gate driver devices is therefore envisaged, in order to provide the aforesaid galvanic isolation and thus enable control and driving of the power switches, in particular of the corresponding control terminals (gate terminals).

As illustrated schematically in <FIG>, an isolated gate driver device <NUM> is generally configured to receive from a control stage <NUM>, including, for example, a microcontroller, low-voltage switching-control signals, for example pulse-width-modulation (PWM) signals, and to generate (high-voltage) power signals for driving a power stage <NUM>, which includes one or more power switches <NUM>.

In particular, the isolated gate driver device <NUM> is configured to provide a galvanic isolation between the control stage <NUM> and the power stage <NUM>; for example, in a possible embodiment, the isolated gate driver device <NUM> comprises: a low-voltage section 1a, coupled to the control stage <NUM>; and a high-voltage section 1b, coupled to the power stage <NUM> and galvanically isolated from the low-voltage section 1a.

In order to obtain a closed-loop control, the control stage <NUM> is moreover required to receive from the power stage <NUM> suitable feedback signals, preferably acquired in real time. Furthermore, the feedback signals are required not to be affected by switching noise and to be transferred to the control stage <NUM> in a reliable manner, guaranteeing the corresponding integrity.

Known solutions envisage the use of feedback circuit elements, designated as a whole by <NUM> in the aforesaid <FIG>, external to the isolated gate driver device <NUM>, which include, for example (in a way not illustrated), elements for acquisition and amplification of the feedback signals from the power stage <NUM> and isolator elements, for isolated transmission of the feedback signals to the control stage <NUM>.

Such known solutions have, however, the drawbacks of a difficult integration in a limited area and of a reliability that may be less than expected, in particular during the switching operation.

An isolated gate driver device has moreover been proposed, produced by Texas Instruments under the code UCC5870-Q1, which performs in an integrated manner not only a function of driving of a corresponding power stage based on PWM control signals received from a control stage, but also a function of communication of the feedback signals indicative of the operation of the same power stage.

In particular, this isolated gate driver device integrates: an ADC (Analog-to-Digital Converter) for receiving the feedback signals and converting them into digital signals (based on timing commands received from the control stage); and a bi-directional communication module, which in particular implements a communication line of a full-duplex type, for communication of these digital signals from a high-voltage section, coupled to the power stage, to a low-voltage section, coupled to the control stage.

The aforesaid isolated gate driver device has the advantage of not requiring external circuit stages, thus enabling in general a saving of area and a greater freedom in the design of the resulting electrical system.

The present Applicant has, however, realized that the above device has some drawbacks.

In the first place, implementation of the aforesaid bi-directional communication module requires a full-duplex communication in order to constantly update registers of the low-voltage section, preventing any conflicts with possible asynchronous commands arriving from the control stage; the full-duplex communication implies two independent isolation lines (one for transmission and the other for reception) with consequent area occupation.

Moreover, implementation of the bi-directional communication module requires a fast communication protocol for rapidly exchanging the digital signals, before arrival of a new edge of the PWM control signal; a higher speed in general means a higher current consumption.

The possibility of a new sample of the feedback signal not being correctly acquired may moreover arise in the case, for example, where the value of the duty-cycle of the control signal is very small or very high. In particular, this may occur even though an ADC with a very short conversion time (equal to <NUM>) is used; in this regard, it may be noted that a short conversion time leads to a consequent reduced immunity to noise.

To guarantee acquisition as far as possible in real time, the implementation moreover requires transmission of a "timestamp" on the communication line; this implies a higher burden for the communication protocol.

Moreover, the system does not enable conversions on request by the control stage, which would instead be particularly useful for carrying out diagnostic checks upon switching-on, such as measurement of the gate threshold voltage, or for carrying out a so-called HardWare Self Check (HWSC).

The system also has an upper limit for the switching frequency, equal to <NUM>, which may prove insufficient for some applications.

<CIT> discloses a control system and method where a first voltage domain circuit and a power switch operate in a first voltage domain and where a second voltage domain circuit operates in a second voltage domain, where the second voltage domain circuit includes a gate driver circuit for providing a control terminal driving signal to drive the power switch, and also includes a watchdog communication circuit for scheduling watchdog communications between the first and second voltage domain circuits to be temporally separated from noise-inducing signal transitions in the control terminal driving signal.

The aim of the present solution is therefore to provide an isolated gate driver device, which will allow to overcome the problems highlighted previously and will have improved characteristics and performance.

According to the present solution, an isolated gate driver device and a corresponding electrical power system are provided, as defined in the appended claims.

For a better understanding of the present invention preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:.

As shown in <FIG>, an isolated gate driver device <NUM> comprises, according to an embodiment of the present solution:.

In a possible embodiment, the low-voltage section 10a and the high-voltage section 10b are made with two distinct dies of semiconductor material <NUM>', <NUM>", separated from one another by a galvanic-isolation barrier <NUM>.

The aforesaid communication channel <NUM> couples in communication the low-voltage and high-voltage sections 10a, 10b, enabling transfer of information and signals through the aforesaid galvanic-isolation barrier <NUM>.

In particular, a first communication module (a transceiver module, RX/TX) 15a in the low-voltage section 10a (or low-voltage, LV, side) acts as master, sending queries at a given polling frequency fPOL, for example <NUM>, according to a question-and-answer (Q&A) mechanism. A corresponding second communication module (a transceiver module, RX/TX) 15b in the high-voltage section 10b (or high voltage, HV, side) acts, instead, as slave, answering the queries received.

The question-and-answer thread may also be interrupted by asynchronous communication events (so-called interrupts) due to activity by the control stage <NUM>, the communication channel <NUM>, in particular the second communication module 15b, being in any case configured so as to manage the priorities of the threads, preventing any conflicts (as described in greater detail hereinafter).

The aforesaid control stage <NUM>, external to the isolated gate driver device <NUM>, is provided with a microcontroller, or a similar processing unit, and comprises in particular: a PWM controller <NUM>, configured to generate the low-voltage PWM control signals SPWM, as a function of a desired control strategy for the power stage <NUM>; and a reading interface <NUM>, configured to receive the feedback output signals Sout_FB.

The aforesaid power stage <NUM> comprises one or more power switches <NUM>, for example made with SiC, GaN, MOSFET, IGBT technology which are driven in switching mode to obtain transfer of power to an electrical load, for example a three-phase motor (not illustrated herein).

In particular, the power switches <NUM>, of which, by way of example, <FIG> illustrates a high-side switch HS, coupled to a battery power-supply terminal Vbat (in turn coupled to a power-supply battery through a stabilisation capacitor, here not illustrated), and a low-side switch LS, coupled to a reference or ground terminal GND, have a corresponding gate terminal coupled to the driving output OUTDRV, so as to receive the corresponding gate-driving signal VG.

It is noted that, in general, as many isolated gate driver devices <NUM> will be present as are the power switches <NUM> in the power stage <NUM> of the electrical power system <NUM>.

The power stage <NUM> further comprises suitable sensor elements, designated as a whole by <NUM>, for acquisition of the feedback signals SFB, indicative of the operation of the power stage <NUM>, amongst which, for example, temperature signals (TEMP), voltage signals (VDC), and current signals (CSA), required by the control stage <NUM> to implement the desired control strategy.

For instance, in the case where the electrical load is a three-phase electric motor, these feedback signals SFB may comprise: a voltage VDC on the stabilisation capacitor, which may, for example, be detected for applying a correction factor to the phase duty-cycle, according to the control strategy; a phase current CSA, which may be acquired for controlling the torque of the three-phase electric motor; and a temperature TEMP associated with a power switch <NUM>, which may be acquired for safety reasons and for applying a variable-switching-frequency strategy in order to provide thermal relief.

In detail, the aforesaid high-voltage section 10b comprises:.

In detail, the ADC module <NUM> acquires the feedback signals SFB with a conversion time TCONV (for example, <NUM>) suitable for the specific application. The configuration of the ADC module <NUM> is such as to guarantee an acquisition free of noise, albeit satisfying the Nyquist criteria to prevent aliasing. For high-frequency switching applications, it is possible to implement a high-speed ADC (for example, of a flash/SAR type) with a subsequent filtering chain; instead, low-frequency switching applications may benefit from a slower ADC topology, such as a sigma-delta, ΣΔ, modulator.

According to a particular aspect of the present solution, as shown in detail in <FIG>, the conversion-control module <NUM> comprises:.

In greater detail, the control-logic block <NUM> collects information on the operating status of the output from the acquisition block <NUM> and combines the same operating status with the measurements of duration of the ON interval TON and OFF interval TOFF to determine the most convenient instant in time for activating the start of conversion by the ADC module <NUM>.

In particular, given the switching period TPWM_HV (for example, equal to <NUM> in the case of a switching frequency fPWM_HV of <NUM>) associated with the PWM control signal SPWM, the logic implemented by the control-logic block <NUM> envisages that:.

Basically, the conversion is started in a way aligned with the centre of the programmed phase of the duty-cycle; to obtain this, the control-logic block <NUM> observes the state of the output, provided by the status signal VGS_STATUS. When the output evolves into the state programmed for acquisition, the internal timer (timer block <NUM>) is started. If the programmed state of acquisition is 'ON', when the timer reaches the threshold (TON-TCONV)/<NUM> (without considering, for reasons of simplicity, in this case the guard time TGUARD), the logic generates the start-of-conversion (SoC) pulse by the conversion-trigger signal STrig. Instead, if the programmed state of acquisition is 'OFF', the logic generates the start-of-conversion pulse SoC when the timer reaches the threshold (TOFF - TCONV) /<NUM> (without considering once again, for reasons of simplicity, the guard time TGUARD).

In general, acquisition during the ON interval TON is preferable in so far as it guarantees a lower noise coupled to the signal (it is known in fact that the "ringing" effect due to switching-on of the switches <NUM> has a lower intensity than the similar effect due to switching-off of the same switches <NUM>). However, advantageously, when the ON interval TON is not compatible with the conversion time TCONV, the algorithm implemented by the control-logic block <NUM> shifts autonomously to acquisition in the OFF interval TOFF so as to guarantee continuous sampling of the signal, without any loss of samples in any of the switching cycles (i.e., an effective acquisition in real time of the feedback signals SFB).

The time count performed by the timer block <NUM> therefore enables the control-logic block <NUM> to determine the exact instant of activation of the ADC module <NUM> (with adequate approximation, for example equal to <NUM>% of the switching period TPWM_HV).

According to a further aspect of the present solution, the first communication-interface module <NUM> comprises a first accumulator block (HV accumulator) <NUM>, configured to accumulate the samples Sk resulting from the analog-to-digital conversion by the ADC module <NUM>, acting as a moving average filter (with anti-aliasing effect, as also discussed hereinafter).

The size of the first accumulator block <NUM>, NSAMPLES_HV (for example, equal to four) is chosen so as to match the bandwidth of the PWM control signal SPWM (which may even reach <NUM>) to the polling frequency associated with the communication channel <NUM> (which may be different, for example equal to <NUM>) in order to prevent aliasing phenomena.

The first accumulator block <NUM> is reset whenever a polling query arrives from the communication channel <NUM>.

In greater detail, it is pointed out that the conversion time TCONV equal to <NUM> guarantees correct acquisition of the PWM control signal SPWM up to a frequency of <NUM>. Acquisition in fact requires having at least <NUM> available either during the ON interval TON or during the OFF interval TOFF; this is guaranteed for any duty-cycle up to the frequency of <NUM>, since the sum of the intervals TON and TOFF is in this case always equal to <NUM>.

Furthermore, it is pointed out that the use of an ADC of a ΣΔ type with a conversion time TCONV equal to <NUM> means that the result of the conversion is given by the mean value of the signal acquired over a time window equal to the conversion time TCONV; this guarantees a noise-filtering feature, thanks to exploitation of the entire interval TON (or TOFF) for averaging the signal.

In particular, even in the case where the signal is acquired during the OFF interval TOFF, the sampling strategy guarantees the best result possible in terms of noise, acquiring the signal at the middle of the OFF interval TOFF.

The first communication-interface module <NUM> further comprises a first integrity check block <NUM>, configured to perform an integrity check and validate the queries received through the communication channel <NUM> (from the low-voltage section 10a) and activate an answer only in the case of a positive outcome of this integrity check. Otherwise, any query deemed as not conforming (for example, because it is damaged) is eliminated.

The low-voltage section 10a in turn comprises:.

In detail, the second integrity check block <NUM> is configured to reject any packet damaged that is received from the communication channel <NUM> (by the corresponding first communication module 15a, not illustrated herein for reasons of simplicity) and therefore not add it to the second accumulator block <NUM>.

The second accumulator block <NUM> is configured to collect in an internal buffer the data gathered by the polling routine being run over the communication channel <NUM>. In particular, the second accumulator block <NUM> is loaded with a new sample acquired from the ADC module <NUM> and transmitted over the communication channel <NUM> only in case where the data received are considered valid, i.e., not corrupted; the same second accumulator block <NUM> is moreover reset at each new period (of duration <NUM>/fOUT_PWM) of the feedback output signals Sout_FB generated by the PWM generator block <NUM>. The size of the second accumulator block <NUM>, NSAMPLES_LV (for example, equal to two) is suitably chosen based on the aforesaid output frequency FOUT_PWM of the feedback output signals Sout_FB generated by the PWM generator block <NUM>.

The PWM generator block <NUM> is thus configured to encode the data stored in the second accumulator block <NUM>, using a square wave with fixed frequency, fOUT_PWM, the duty-cycle of which is determined directly by the result of the analog-to-digital conversion, in particular according to the following expression: <MAT> where ACCz-<NUM> is the content of the second accumulator block <NUM>, determined at the previous sampling instant (z-<NUM>), and T'ONz-<NUM> is the duration of the ON interval of the aforesaid duty-cycle.

In greater detail, the PWM generator block <NUM> therefore operates in an altogether asynchronous manner and generates a PWM signal with fixed frequency, fOUT_PWM, the duty-cycle of which depends on the average data stored in the second accumulator block <NUM>, according to the expression previously highlighted.

Whenever a new period of the feedback output signal Sout_FB generated by the PWM generator block <NUM> starts, the second accumulator block <NUM> is reset.

The elementary time interval (resolution) of the feedback output signal Sout_FB generated by the PWM generator block <NUM> depends upon encoding of the data deriving from analog-to-digital conversion. If NBIT (for example, <NUM> bits) are used for encoding the conversion data, the time resolution will be fOUT_PWM·<NUM>N.

It is pointed out that the process of acquisition and accumulation in the first accumulator block <NUM> of the high-voltage section 10b is in this way asynchronous with respect to the polling (question-and-answer) thread being executed over the communication channel <NUM>. In fact, the frequency of accumulation in the first accumulator block <NUM> is associated with the switching frequency fPWM_HV of the PWM control signals SPWM generated by the controller stage <NUM>, which is altogether independent of the polling frequency fPOL on the aforesaid communication channel <NUM>.

It is moreover pointed out that the PWM generator block <NUM> can also operate in an altogether asynchronous manner, generating a PWM signal with output frequency fOUT_PWM that may be different from the aforesaid polling frequency fPOL and from the aforesaid switching frequency fPWM_HV.

Operation of the isolated gate driver device <NUM> is now illustrated in further detail with the aid of the timing charts of <FIG> and <FIG>, which relate to acquisition of a new sample Sk of the feedback signals SFB during the ON interval TON and during the OFF interval TOFF, respectively.

In the example of <FIG>, based on the processing operations executed in the previous period (or cycle), the control-logic block <NUM> of the conversion-control module <NUM> has programmed the start of conversion of the ADC module <NUM> during the ON interval TON.

The control stage <NUM> sets to high the PWM control signal SPWM, which is sent at input to the low-voltage section 10a of the isolated gate driver device <NUM>. The signal is then transferred to the high-voltage section 10b of the same isolated gate driver device <NUM> through the isolation barrier <NUM> and is further processed by the driving module <NUM>, which generates the equivalent gate-driving signal VG at a high voltage (for example, with a voltage of <NUM> V).

Consequently, the gate-to-source voltage VGS of the switch evolves, increasing its value based on the gate-driving signal VG.

When the gate-to-source voltage VGS exceeds the pre-set threshold VTH, the analog comparator of the acquisition block <NUM> switches the status signal VGS_STATUS at its output and thus activates the timer block <NUM>. At the same time, the control-logic block <NUM> receives the information that the output (i.e., the coupled power switch <NUM>) is in the ON state.

When the timer reaches the threshold (TON(k-<NUM>) - TCONV)/<NUM> (where TON(k-<NUM>) is the duration of the ON interval of the previous period, and TCONV is, as mentioned previously, the duration of the analog-to-digital conversion), the conversion-trigger signal STrig is generated, which causes start of conversion (SoC) for acquisition of a new sample Sk of the feedback signal SFB present at the feedback input INFB.

In particular, after the interval TCONV, the ADC module <NUM> generates the new sample Sk, which is added to the first accumulator block <NUM>, the previous value of which was ACC(k-<NUM>), thus determining its new value ACC(k).

In an asynchronous manner, a query is arriving from the low-voltage section 10a over the communication channel <NUM>. The first integrity check block <NUM> validates the query and answers with the average content of the first accumulator block <NUM>, ACC(k)/NSAMPLES_HV; then, the first accumulator block <NUM> is reset.

The data propagate over the communication channel <NUM> and reach the low-voltage section 10a, where they are validated by the second integrity check block <NUM> and, if valid, added to the second accumulator block <NUM>, which evolves from the previous value ACC(z-<NUM>) (for example, a value equal to zero) to a new value ACC(z), which is therefore a function of the aforesaid average content of the first accumulator block <NUM>, ACC(k)/NSAMPLES_HV.

The PWM generator block <NUM> then generates the feedback output signal Sout_FB, with fixed frequency fOUT_PWM and duty-cycle determined by the average value of the second accumulator block <NUM> in the previous period, according to the expression: T'ONz-<NUM> = f(ACCz-<NUM>/ NSAMPLES_LV).

According to a further aspect of the present solution, any conflict between the polling routine and possible asynchronous queries (interrupts, INT) coming directly from the control stage <NUM> (and from the corresponding microcontroller), for example for diagnostic purposes, are handled as represented schematically in <FIG> and as described now in detail.

In particular, maximum priority is assigned to the polling routine associated with the analog-to-digital conversion. In the case where the polling query (POL) for reading a new sample of the signal acquired and the asynchronous query (MCU Interrupt) by the control stage <NUM> arrive simultaneously, the polling query is served first; the query coming from the control stage <NUM> is stored in a buffer and delayed until the analog-to-digital conversion routine is completed. This prevents overflow of the first accumulator block <NUM>, since this strategy guarantees that the same first accumulator block <NUM> is constantly emptied within a time interval compatible with the maximum switching frequency (for example, equal to <NUM>).

During the time interval in which the routine originating from the direct query from the control stage <NUM> interrupts the analog-to-digital conversion routine, any polling query is rejected. However, the first accumulator block <NUM> guarantees that no loss of data will occur, accumulating new measurement samples even during the time interval when the aforesaid query originated by the control stage <NUM> is served.

The advantages of the present solution are clear from the foregoing description.

In any case, it is pointed out that the isolated gate driver device <NUM> allows to:.

In particular, as discussed previously, the isolated gate driver device <NUM> is provided internally with the control-logic block <NUM> so as to determine autonomously and without any external interventions the optimal times and modalities for analog-to-digital conversion and acquisition of new samples of the aforesaid feedback signals SFB.

Furthermore, the use of the first and second accumulator blocks <NUM>, <NUM> in the high-voltage section 10b and, respectively, low-voltage section 10a, allows to prevent any loss of data (basically, providing anti-aliasing filters in order to respect the Nyquist criterion), even in the case of asynchronous operation (and therefore different frequencies) of the polling routine, of the ADC routine, and moreover of the PWM generation of the feedback output signals Sout_FB.

The aforesaid advantageous features are moreover obtained within a totally integrated device, with minimum occupation of area, given that the presence of external devices is not required.

Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the appended claims.

In particular, the feedback output signals Sout_FB for the control stage <NUM> could be generated by the second interface module <NUM> with an encoding different from the PWM encoding described previously.

Claim 1:
An isolated gate driver device (<NUM>), comprising:
a low-voltage section (10a), having a control input (INPWM), which is designed to receive from a control stage (<NUM>) a PWM control signal (SPWM) at a switching frequency (fPWM_HV);
a high-voltage section (10b), galvanically isolated from the low-voltage section (10a), having a driving output (OUTDRV), which is designed to provide a gate-driving signal (VG), as a function of said PWM control signal (SPWM), to a power stage (<NUM>) including at least one switch (<NUM>), and a feedback input (INFB), which is designed to receive at least one feedback signal (SFB) indicative of the operation of the power stage (<NUM>); and
a communication channel (<NUM>) configured to implement an isolated communication between the low-voltage section (10a) and the high-voltage section (10b),
wherein the high-voltage section (10b) comprises an ADC module (<NUM>) configured to convert the feedback signal (SFB) into a digital data stream, and said communication channel (<NUM>) is configured to send said digital data stream (Sk) to the low-voltage section (10a) to be fed back to the control stage (<NUM>),
wherein the high-voltage section (10b) further comprising a conversion-control module (<NUM>), coupled to the ADC module (<NUM>) and configured to provide a conversion-trigger signal (STrig) designed to determine the start of conversion for acquisition of a new sample (Sk) of the feedback signal (SFB);
and wherein said conversion-control module (<NUM>) comprises:
an acquisition block (<NUM>), configured to acquire a signal (VGS) indicative of an operating status, either ON or OFF, at said driving output (OUTDRV) and to provide a status signal (VGS_STATUS) indicative of said operating status;
a timer block (<NUM>), configured to receive the status signal (VGS_STATUS) from the acquisition block (<NUM>) and measure the duration of an ON interval (TON) and an OFF interval (TOFF) associated with said operating status; and
a control-logic block (<NUM>), configured to generate said conversion-trigger signal (STrig) at a time instant which is a function of the duration of said ON and OFF intervals (TON, TOFF) and as a function of said status signal (VGS_STATUS).