Patent Description:
<CIT> relates to a galvanically-isolated device including a lead frame with a first die-attach pad, a first led and a second lead. A substrate is disposed on the die-attach pad and a high-voltage semiconductor capacitor is formed on the substrate.

<CIT> relates to a signal isolator having inductive and capacitive coupling. A floating plate can enable a top and bottom capacitive plate to be offset from each other.

<CIT> relates to an integrated circuit including at least two portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions.

The present invention provides methods and apparatus for a signal isolator having reduced parasitics for increasing data signal characteristics. Embodiments can provide capacitively-coupled isolated signal paths and/or inductively-coupled isolated signal paths. Some embodiments can include differential signal paths from a first voltage domain to a second voltage domain of the isolator. In embodiments, a die can include one or more isolated portions to provide multiple data paths from a first die portion to a second die portion.

The invention is defined by independent claims.

The foregoing features of this invention, as well as the invention itself, may be more fully understood from the following description of the drawings in which:.

<FIG> shows an example of a signal isolator <NUM> including first and second die portions <NUM>, <NUM> that form part of an integrated circuit package <NUM> having capacitive and/or inductive signal coupling with at least one isolation island between the first and second die portions in accordance with example embodiments of the invention. In embodiments, the first and second die portions <NUM>, <NUM> are part of a single die and are isolated from each other. In an embodiment, the IC package <NUM> includes a first input signal INA connected to the first die portion <NUM> and a first output signal OUTA connected to the second die portion <NUM>. The IC package <NUM> further includes a second input signal INB connected to the second die portion <NUM> and a second output signal OUTB to the first die portion <NUM>. The first and second die portions <NUM>, <NUM> are separated by a barrier region <NUM>, such as an isolation barrier.

In embodiments, the first die portion <NUM> includes a first transmit module <NUM> and the second die portion <NUM> includes a first receive module <NUM> that provides a signal path from the first input signal INA to the first output signal OUTA across the barrier <NUM>. The second die portion <NUM> includes a second transmit module <NUM> and the first die portion <NUM> includes a second receive module <NUM> that provides a signal path from the second input signal INB to the second output signal OUTB across the barrier <NUM>.

It is understood that any practical number of transmit, receive, and transmit/receive modules can be formed on the first and/or second die portions to meet the needs of a particular application. It is further understood that transmit, receive, and transmit/receive modules can comprise the same or different components. In addition, in embodiments, bidirectional communication is provided across the barrier. Further, circuity in the first and/or second die portions can be provided to process signals, perform routing of signals, and the like. In some embodiments, sensing elements are formed in, on, or about the first and/or second die.

<FIG> and <FIG> show an example single die signal isolator <NUM> having a bulk silicon substrate <NUM>, such as SOI, with a first die portion <NUM> and a second die portion <NUM> separated by an isolation island <NUM>. In example embodiments, the first and second die portions <NUM>, <NUM> comprise epitaxial regions and the isolation region <NUM> comprises an isolated epitaxial island region, which is separated from the first and second die portions <NUM>, <NUM> by respective isolating trenches <NUM>, <NUM> formed in the epitaxial layer <NUM>. In embodiments, the first and second die portions <NUM>, <NUM> and the isolation region <NUM> can be formed from a single die. Further trenches <NUM>, <NUM> can be located on the outer ends of the first and second die portions <NUM>,<NUM>. As seen in <FIG>, further trenches <NUM>, <NUM> can be formed in the 'front' and 'back' of the epitaxial island <NUM>. Trenches can comprise any suitable material, such as SiO2. In embodiments, circuitry to provide signal isolator functionality, such as transmitting and receiving signals, can be provided in the first and second die portions <NUM>, <NUM>.

A first metal region <NUM> and a second metal region <NUM> can be formed within a first metal layer <NUM>. A first via <NUM> couples the first metal region <NUM> to the first die portion <NUM> and a second via <NUM> couples the second metal region <NUM> to the second die portion <NUM>. Within the first metal layer <NUM>, dielectric material <NUM> can isolate the first and second metal regions <NUM>, <NUM>. A third metal region <NUM> can be formed in a second metal layer <NUM>. In embodiments, the third metal region <NUM> is separated from the first and second metal regions <NUM>, <NUM> by an inter-metal dielectric layer (IMD) <NUM>, such as SiO2. The first metal layer <NUM> can be separated from the epitaxial layer <NUM> by a further IMD layer <NUM>. It is understood that first and second metal regions <NUM>, <NUM> do not need to be in the same layer. The third metal region <NUM> can be above or below the first and second metal regions <NUM>, <NUM>.

A first circuit component <NUM>, such as a capacitor, is formed by the first metal region <NUM> and the third metal region <NUM> and a second circuit component <NUM>, such as a capacitor, is formed by the second metal region <NUM> and the third metal region <NUM>. It is understood that the capacitor symbols <NUM>, <NUM> represent the capacitance provided by the respective first and second metal regions <NUM>, <NUM> and the third metal region <NUM>. As best seen in <FIG>, the third metal region <NUM> overlaps a portion of the first metal region <NUM> and a portion of the second metal region <NUM> to form the respective capacitors <NUM>, <NUM>. A passivation layer <NUM> can be provided over the third metal region <NUM> and dielectric layer <NUM>, e.g., SiO2. The epitaxial layer <NUM> can be isolated from the substrate <NUM> by a buried oxide layer <NUM>, for example.

In embodiments, the first and second capacitors <NUM>, <NUM> are connected in a series interconnection to provide a first isolated signal path from the first die portion <NUM> to the second die portion <NUM>. As described in <FIG>, a signal on INA on the first die portion <NUM> can be transmitted across isolation barrier <NUM> and output on OUTA. For example, an input signal is transferred through the conductive first via <NUM> from circuitry on the first die portion <NUM> to the first metal region <NUM>, which can be referred to as a mid-level metal in example embodiments. The first metal region <NUM> and the third metal region <NUM>, which can be referred to as a higher metal layer, are capacitively coupled to effect signal transfer to the second die portion <NUM> via the second capacitor <NUM> formed by the third metal region <NUM> and the second metal region <NUM>. In embodiments, an SiO2 IMD (inter-metal dielectric) layer <NUM> separates the metal layers <NUM>, <NUM>. With this arrangement, the first and second die regions <NUM>, <NUM>, e.g., EPI regions, are capacitively coupled to enable signal transfer via an isolated signal path.

In embodiments, a third capacitance <NUM> is generated between the first metal region <NUM> and the isolation island <NUM>. A fourth capacitance <NUM> is provided between the second metal region <NUM> and the isolation island <NUM>. A second isolated signal path from the first die region <NUM> to the second die region <NUM> is provided by the third and fourth capacitances. The second isolated signal path includes a path from the first metal region <NUM>, which is electrically connected to the first die region <NUM>, to the isolation island <NUM>, from the isolation island <NUM> to the second metal region <NUM>, which is electrically connected to the second die region. Thus, the third and fourth capacitances <NUM>, <NUM> with the isolation island <NUM> provide the second isolated signal path between the first and second die regions <NUM>, <NUM>. It will be appreciated that the first and second isolated signal paths are electrically in parallel so as to improve signal characteristics as data passes between the first and second die regions <NUM>, <NUM>.

<FIG> shows an example signal isolator <NUM>' having similarity with the isolator <NUM> of <FIG> with the addition of a conductive material <NUM>, such as polysilicon or metal, formed on the island <NUM>. The conductive material <NUM> alters the impedance of the parasitic capacitances <NUM>, <NUM>. In the illustrated embodiment of <FIG>, the parasitic capacitance is in parallel with the signal capacitors and the parasitic capacitance carries a portion of that signal to the second metal region <NUM>. In embodiments, the polysilicon <NUM> is more conductive than the isolation island <NUM>, which enhances the signal path characteristics from the first die portion <NUM> to the second die portion via the isolation island <NUM>.

<FIG> shows an example signal isolator <NUM>" having similarity with the isolator <NUM> of <FIG>. In the signal isolator <NUM>" of <FIG>, the first and second die regions <NUM>, <NUM> are connected via an inductively coupled signal path. A first coil <NUM> is coupled to the first die region <NUM> and a second coil <NUM> is coupled to the second die region <NUM>. At least a portion of the first and second coils <NUM>, <NUM> overlap with each other so that they are inductively coupled. A first parasitic capacitance <NUM>' may be generated between the first coil <NUM> and the island <NUM> and a second parasitic capacitance <NUM>' may be formed between the second coil <NUM> and the island <NUM>. The coils <NUM>, <NUM> may be separated by IMD layers for electrical isolation. With this arrangement, a signal from the first die region <NUM> is transmitted to the second die region via the coils <NUM>, <NUM>, and vice-versa. As described above, the isolation island <NUM> modifies the signal through the parasitic capacitances <NUM>', <NUM>' by providing a second isolated signal path from the first die region <NUM> to the second die region <NUM>.

<FIG> shows the signal isolator <NUM>" of <FIG> with example first and second coils <NUM>, <NUM> that are round and overlapping. It is understood that the coils can have any practical geometry to meet the needs of a particular application. Without limitation thereto, example coil shapes include rectangular, polygonal, trapezoidal, circular, ovular, arcuate, etc..

<FIG> shows an example signal isolator having similarity with the isolator <NUM>" of <FIG> having multiple isolation islands 208a,b separated by a trench <NUM>. Multiple isolation islands 208a,b are described more fully below.

It is understood that while example embodiments are shown having circuit components for signal transfer including capacitors for capacitive coupling and coils for inductive coupling, it is understood that an isolation island between die regions can reduce parasitic capacitance effects in other isolator configurations using other signal transfer means.

<FIG> show a further embodiment of a signal isolator <NUM> having low parasitic characteristics provided by multiple epitaxial islands with some commonality with the isolator <NUM> of <FIG> and <FIG>.

A substrate <NUM> has a first die portion <NUM> and a second die portion <NUM> separated by first and second isolation islands 308a,b, which are separated by an isolation trench <NUM>, located in an epitaxial layer <NUM>. In example embodiments, the first and second die portions <NUM>, <NUM> comprise epitaxial regions and the isolation islands 308a,b comprise isolated epitaxial islands, which are separated from the first and second die portions <NUM>, <NUM> by respective isolating trenches <NUM>, <NUM>. In embodiments, the isolation islands <NUM> can be considered die portions of a single die. There is substantially zero current flow between the isolation islands 308a,b so as to provide electrically isolated voltage domains. Further trenches <NUM>, <NUM> can be located on the outer ends of the first and second die portions <NUM>, <NUM>. As seen in <FIG>, further trenches <NUM>, <NUM> can be formed in the 'front' and 'back' of the epitaxial island <NUM>.

A first metal region <NUM> and a second metal region <NUM> can be formed within a first metal layer <NUM>. A first via <NUM> couples the first metal region <NUM> to the first die portion <NUM> and a second via <NUM> coupled the second metal region <NUM> to the second die portion <NUM>. Within the first metal layer <NUM>, dielectric material <NUM> can isolate the first and second metal regions <NUM>, <NUM>. A third metal region <NUM> can be formed in a second metal layer <NUM>. In embodiments, the third metal region <NUM> is separated from the first and second metal regions <NUM>, <NUM> by a dielectric layer <NUM>, such as SiO2.

A first capacitor <NUM> is formed by the first metal region <NUM> and the third metal region <NUM> and a second capacitor <NUM> is formed by the second metal region <NUM> and the third metal region <NUM>. It is understood that the capacitor symbols <NUM>, <NUM> represent the capacitance provided by the respective first and second metal regions <NUM>, <NUM> and the third metal region <NUM>. As best seen in <FIG>, the third metal region <NUM> overlaps a portion of the first metal region <NUM> and a portion of the second metal region <NUM> to form the respective capacitors <NUM>, <NUM>. A passivation layer <NUM> can be provided over the third metal region <NUM> and dielectric layer <NUM>, e.g., SiO2. The epitaxial layer <NUM> can be isolated from the substrate <NUM> by a buried oxide layer <NUM>, for example.

In the illustrated embodiment, first and second parasitic capacitances <NUM>, <NUM> are formed between the respective first metal region <NUM> and isolation island 308a and the second metal region <NUM> and island 308b.

<FIG> shows certain electrical characteristics of the isolator configuration of <FIG> including a series of parasitic capacitances 360a-d with the substrate <NUM>. In the illustrated embodiment, the first die region <NUM> has a parasitic capacitance 360a, isolation island 308a has a parasitic capacitance 360b, isolation island 308b has a parasitic capacitance 360c, and the second die region <NUM> has a parasitic capacitance 360d.

In the illustrated embodiment, for the parasitic capacitances to reduce the desired data signal between the first and second die portions <NUM>, <NUM>, the parasitic path must go from the mid-level metal layer <NUM>, through the oxide layer <NUM> above the isolation island 308a and the oxide layer <NUM> below the isolation island 308a, and then through the buried oxide layer <NUM> again up to the first die region <NUM>. A similar parasitic path may exist for the second die region <NUM>. Thus, with this arrangement, the effects of parasitic capacitances are reduced by having first and second isolation islands 308a,b that are isolated from each other.

In embodiments, a signal isolator may have isolated differential signal paths from a first die portion to a second die portion. The advantages of differential signal paths for a signal isolation IC package will be readily apparent to one skilled in the art.

<FIG> shows a differential implementation <NUM>' of the signal isolators of <FIG> and <FIG>. A first die portion <NUM>' and a second die portion <NUM>' are separated by isolation islands <NUM>', which are separated by isolation trenches <NUM>'. In embodiments, the isolation islands <NUM> can be considered die portions of a single die.

In the illustrated embodiment, a differential signal pair can be formed by parallel, isolated capacitively-coupled signal paths. A first signal in the differential signal pair is provided by first metal region 320a, second metal region 322a, and third metal region 332a. The second signal in the differential signal pair is provided by fourth metal region 320b, fifth metal region 322b, and sixth metal region 332b. As described above, the metal regions 320a, 322a, 332a and 320b, 320b, 332b form respective capacitors for a capacitively coupled isolated signal path.

It is understood that any practical number of isolation islands can be formed to meet the needs of a particular application. For example, <FIG> shows an isolator <NUM> including a silicon substrate <NUM> having a first die portion <NUM> and a second die portion <NUM> separated by isolation islands 408a-n, which are separated by isolation trenches <NUM>, located in an epitaxial layer. In example embodiments, the first and second die portions <NUM>, <NUM> are formed in the epitaxial layer and the isolation islands 408a,n comprise isolated epitaxial islands, which are separated from the first and second die portions <NUM>, <NUM> by respective isolating trenches. There is substantially zero current flow between the isolation islands 408a-n. The multiple isolated islands have the benefit of further reducing the effects of parasitic capacitances by reducing the area of the conductive island and by splitting the total island into multiple, series-connected capacitors at each isolation trench <NUM> between the two die portions <NUM> and <NUM>.

As described above, providing parallel signal paths between first and second die regions with an isolation island enhances the data signal between the die. Providing multiple isolation islands also enhances the data signal between the die but in a different way. The multiple isolation islands reduces the secondary signal path and reduces the parasitic capacitance from the main signal capacitors to it and to ground). One skilled in the art will appreciate that processing techniques may impose certain limitations, such as on the width of a trench and/or maintaining an area of constant voltage potential under a signal path, which provides a type of DC shield for preventing other circuitry from being disturbed by the data signal or by the high voltage transients that can occur.

It is understood that any suitable wafer material and processing techniques can be used in alternative embodiments.

It is understood that die portions can have any combination of drivers and receivers and each driver and receiver data transmission channel can share signal processing, routing, and diagnostic features or have such features for each individual data channel. In embodiments, outputs can be in buffered with a push-pull, open drain or other such output driver, or the output can be a magneto-resistive device with change in resistance indicating logic states.

Having described exemplary embodiments of the invention, it will now become apparent to one of ordinary skill in the art that other embodiments incorporating their concepts may also be used. The embodiments contained herein should not be limited to disclosed embodiments but rather should be limited only by the scope of the appended claims.

Claim 1:
A signal isolator, comprising:
a first die portion (<NUM>);
a first metal region (<NUM>) electrically connected to the first die portion (<NUM>);
a second die portion (<NUM>) isolated from the first die portion (<NUM>);
a second metal region (<NUM>) electrically connected to the second die portion (<NUM>);
a third metal region (<NUM>) electrically isolated from the first and second metal regions;
a third die portio (<NUM>) electrically isolated from the first, second and third metal regions and electrically isolated from the first and second die portions (<NUM>, <NUM>), wherein
the first metal region (<NUM>), the second metal region (<NUM>), and the third metal region (<NUM>) provide a first isolated signal path from the first die portion (<NUM>) to the second die portion (<NUM>);
the first metal region (<NUM>), the second metal region (<NUM>) and the third die portion (<NUM>) provide a second isolated signal path from the first die portion (<NUM>) to the second die portion (<NUM>) in parallel with the first isolated signal path;
the die portions (<NUM>, <NUM>, <NUM>) are arranged in a single layer;
the first isolated signal path comprises a first capacitor (<NUM>) capacitively coupled with a second capacitor (<NUM>), wherein the first capacitor (<NUM>) comprises the first metal region (<NUM>) and the third metal region (<NUM>), and the second capacitor (<NUM>) comprises the third metal region (<NUM>) and the second metal region (<NUM>); and
the second isolated signal path includes a third capacitor (<NUM>) capacitively coupled to a fourth capacitor (<NUM>), wherein the third capacitor (<NUM>) comprises the first metal region (<NUM>) and the third die portion (<NUM>), and the fourth capacitor (<NUM>) comprises the third die portion (<NUM>) and the second metal region (<NUM>).