Patent Description:
A MOSFET device operates by virtue of a field controlled channel established in a semiconductor body or surface. Power MOSFETs are useful in various applications such as synchronous rectifier circuits. Many power MOSFETs exhibit useful features including low on-resistances, fast switching speeds, high withstand voltage capability, bidirectionality for use in AC circuits, and a control electrode isolated from current conducting silicon thereby removing the need for a continuous "on" current. Power MOSFETs have certain advantages over conventional devices such as PN junction rectifiers, Schottky rectifiers, or bipolar transistor synchronous rectifiers.

United States patent publication number <CIT> discloses a bidirectional trench FET device including a semiconductor substrate, a trench in the substrate extending vertically from the surface of the substrate, and a body region laterally adjacent the trench. A source region is disposed in the semiconductor substrate between the body region and the surface of the substrate. A dielectric layer is disposed over the surface and a body electrode is disposed over the dielectric layer. A body contact plug extends through the dielectric layer to interconnect the body region with the body electrode, and the body contact plug is electrically isolated from the source region.

United States patent application publication number <CIT> describes forming a recess at a semiconductor layer of a device to define a plurality of mesas. An active trench portion of the recess residing between adjacent mesas. A termination portion of the trench residing between the end of each mesa and a perimeter of the recess.

United States patent application publication number <CIT> discloses a bi-directional trench field effect power transistor. A layer stalk extends over the top surface of the substrate, in which vertical trenches are present. An electrical path can be selectively enabled or disabled to allow current to flow in opposite directions through a body located laterally between the first and second vertical trenches. The body is provided with a dopant, the concentration of the dopant is at least one order of magnitude higher in a region adjacent to a shallow trench than near the first vertical trench and the second vertical trench.

In a conventional bidirectional power metal-oxide-semiconductor field-effect transistor (MOSFET), parasitic bipolar behavior is limited by a lateral body resistance that generally is improved by using an optimized layout. Conventional techniques attempt to mitigate the parasitic bipolar behavior (such as in unidirectional MOSFETs) by one or more of: reducing the lateral resistance of the body under the source; providing lower route resistance for the impact ionization generated holes (for N-channel MOSFETs); and reducing the minority carrier lifetime in the base region. Similar techniques can be applied to bidirectional MOSFETs but are limited by the performance specifications of the field effect device, especially the on resistance and reverse breakdown.

<FIG> illustrate a device that addresses parasitic bipolar behavior by employing, at least in part, a shorted doped region, of the opposite conductivity type, near a terminal or end of the field effect device, such as the source of a transistor. The shorted doped region can be used irrespective of other enhancements in a field effect device structure. The shorted doped region further improves a device's energy capability.

According to some embodiments, a P+ region abuts an N+ region in a source region for an N-type MOSFET. This P+ region is connected to the source metallization - shorting the P+ region with the source N+ region. The P+ region is isolated from the P-body through a N- drift region or use of a material such as a dielectric material placed in a trench using a shallow trench isolation (STI) or box isolation technique. The P+ region acts as an absorber of holes injected from the P- body of the device into the N- drift region. The P+ region reduces a gain of a parasitic bipolar as the device is turned on. Reduction in parasitic bipolar gain reduces a magnitude of regenerative action and delays the destruction of the device. An additional P+ region can be introduced in all device cells thereby weakening the parasitic bipolar effect in the device.

<FIG> is a diagram illustrating a cross-section view of a field effect device <NUM> employing a cathode short region in accordance with some embodiments. In the depicted example, the field effect device <NUM> is an N-type power metal-oxide-semiconductor field-effect transistor (MOSFET). The field effect device <NUM> comprises a semiconductor substrate <NUM> or semiconductor body having a first surface <NUM> and a second surface <NUM>. The field effect device <NUM> further includes a drain contact <NUM> adjacent or coupled to the first surface <NUM>, and a source contact <NUM> adjacent or coupled to the second surface <NUM>.

The field effect device <NUM> also includes an insulated gate <NUM> that provides turn-on and turn-off control upon the application of an appropriate gate bias. The insulated gate <NUM> includes a gate material <NUM> and insulation material <NUM>. In one embodiment, a gate contact <NUM> is adjacent or coupled to the gate material <NUM>.

The semiconductor substrate <NUM> includes a highly-doped region such as an N+ substrate <NUM> adjacent to the drain contact <NUM>. An N- drift region <NUM> lies adjacent to the N+ substrate <NUM>. A P- body region <NUM> lies adjacent to the N-drift region <NUM>. The P-body region <NUM> includes a highly-doped region such as a P+ region <NUM> adjacent to the body contact <NUM>. The P- body region <NUM> is extended to a final form in order to more easily place a body contact <NUM> or other reasons. Thus, the P- body region <NUM> includes a body extension or extension region. The semiconductor body <NUM> includes an N- drift region <NUM> that separates the P- body region <NUM> from the source contact <NUM>. The separation of the source and body regions allows for the bidirectional operation of the device.

Turn-on in the field effect device <NUM> occurs when a conductive N-type inversion layer is formed in the P-type channel region in response to application of a positive gate bias. In forward operation, the inversion layer electrically connects an N-type source or cathode region <NUM> and an N-type drain or anode region <NUM> in the semiconductor body <NUM> and allows for majority carrier conduction therebetween.

Bidirectional power MOSFETs are prone to early failure in high voltage-high current conditions due to the turning on of the inevitable parasitic bipolar in the structure. To mitigate the parasitic bipolar, as further described herein, a cathode short <NUM> (e.g., a P+ region) abuts a highly-doped region such as an N+ region <NUM> proximate to the source as indicated by the source contact <NUM>. The N+ region <NUM> is of a different conductivity type as the semiconductor body region <NUM>. A region <NUM> is a cathode short region, a first doped region of the same conductivity type as the semiconductor body region <NUM>, adjacent to the source such as adjacent to the source contact <NUM>. According to some embodiments, the cathode short <NUM> is a doped region that is shorted by way of a source contact <NUM>. This P+ region <NUM> can act as an absorber of holes and significantly reduces the gain of the bipolar transistor of the MOSFET (shown for convenience in the P- body region <NUM> of <FIG>) and increases the sustaining voltage. The P+ region <NUM> delays destruction of the field effect device <NUM> and improves its energy capability under the forward operation of the device.

Further, in some embodiments, the illustrated field effect device <NUM> provides the ability to replace multiple back-to-back unidirectional MOSFETs with a single bidirectional power MOSFET device. For bidirectional blocking, the P- body region <NUM> of the device <NUM> is not hard tied to the source <NUM>. Even when the source and body contacts are connected to the same potential outside the device, the parasitic bipolar behavior can be worsened by additional parasitic resistances such as the lateral base resistance as indicated in the P- body region in <FIG> and the external routing resistance (e.g., application of resistive material) coupled to the body contact <NUM>. For sake of convenience, resistive material is not illustrated in <FIG>. Triggering of the parasitic bipolar behavior may cause the field effect device <NUM> to latch up and possibly destroy itself. Reduction in lateral resistance, such as by increased base doping, comes at the cost of increased threshold voltage. Reduction in routing resistance at the body contact <NUM> comes at the cost of reduced source contact area at the second surface <NUM> and hence a higher on-resistance of the field effect device <NUM>.

As may be evident in <FIG>, under forward operation, the parasitic bipolar may be triggered at high-voltage, high-current conditions encountered in inductive load switching or high dV/dt conditions. Impact ionization generated holes can turn on the body-source junction <NUM> - one of the P-N junctions - through a lateral voltage drop combined with a voltage drop on the body routing bus. Electrons back injected from the emitter can multiply at the body-drain junction (e.g., produce more holes), which lead to a higher lateral voltage drop causing a regenerative action. The field effect device <NUM> may heat up during such a regenerative action resulting in an increase of the base resistance and a decrease of the diode forward voltage. Eventually, the device destructs and can do so in localized regions. As described in relation to the various embodiments described herein, a cathode short region, such as the cathode short region <NUM> of <FIG>, can reduce the gain of the parasitic bipolar and makes the bidirectional MOSFET stronger.

<FIG> is a diagram illustrating a cross-section view of field effect device <NUM> employing a cathode short region in accordance with some embodiments. A cathode short region or "cathode short" refers to a cathode region that is shorted with a contact or material with a relatively high conductivity. As illustrated, the device <NUM> includes a semiconductor substrate <NUM> having a first surface <NUM> and a second surface <NUM>. At the first surface <NUM>, the semiconductor substrate <NUM> includes a N-type substrate such as a N+ substrate <NUM> that is adjacent to a drain material or drain contact <NUM>. Adjacent to the N+ substrate <NUM> is an N- drift region or layer <NUM>. A P-type body region <NUM> separates the first N- drift layer <NUM> from a second N- drift region or layer <NUM>.

Along a portion of the N+ substrate <NUM>, the N- drift layer <NUM>, the P-type body region <NUM>, and the N- drift layer <NUM> is an insulation material <NUM> and a gate material <NUM>. The gate material <NUM> and the insulation material <NUM> comprise an insulated gate <NUM>. Application of a voltage at the insulated gate <NUM> causes a field to form in the device <NUM>. A portion of the gate material <NUM> may be coupled to a gate contact <NUM>.

An interlayer dielectric (ILD) layer <NUM> is at the second surface <NUM> and may be formed there during construction of the device <NUM>. Passing through the ILD layer <NUM> may be the gate contact <NUM>, a source contact <NUM>, and a body contact <NUM>. At the ILD layer <NUM>, a first N+ region <NUM> and a P+ region <NUM> are formed in the second N- drift layer <NUM>. The P- body <NUM> includes a P+ region <NUM>. Each of the N+ and P+ regions may be formed in a same step or in separate steps. The P+ region <NUM> acts as a cathode short and is electrically coupled to the source contact <NUM> in <FIG>. Further, the P+ region <NUM> is adjacent N+ material <NUM> that is on a left side and a right side of the P+ region <NUM> in <FIG>. The N+ material <NUM> is of a different conductivity type as the semiconductor body region <NUM>. Other arrangements of one or more N+ regions, such as the N+ region <NUM>, and one or more P+ regions, such as the P+ region <NUM>, are possible. Other example embodiments are shown in other figures and further described herein.

<FIG> are diagrams of a cross-sectional view of the embodiment of the device <NUM> illustrated in <FIG> in various stages of fabrication. In <FIG>, a workpiece <NUM> is illustrated at a first example stage of formation. At this first stage, an ILD layer <NUM> has been formed on a second surface <NUM> of the workpiece <NUM>. A first N- drift region <NUM> has been formed on top of an N-type substrate such as the N+ substrate <NUM>. A first surface <NUM> of the device <NUM> is adjacent to the drain contact <NUM> thereby coupling the N+ substrate <NUM> with the drain contact <NUM>. A body region <NUM> of a P- type has been formed as a layer adjacent to the first N- drift layer <NUM>. A second N- drift layer <NUM> has been formed on the body region <NUM>. An N+ region <NUM> is formed in the second N- drift layer <NUM> adjacent the ILD layer <NUM>. A P+ region <NUM> is formed in a portion of the P-type body region <NUM>. The P+ region <NUM> is adjacent the ILD layer <NUM>. During formation, the body region <NUM> may be formed up to an ILD layer <NUM> in preparation for coupling the body layer or body region <NUM> to a body contact, which is not illustrated in <FIG>. A gate material <NUM> is applied outside of an insulation material <NUM> applied along a surface of the N+ substrate <NUM>, the first N- drift layer <NUM>, the P-type body region <NUM>, and the second N- drift layer <NUM>.

In <FIG>, fabrication of the workpiece <NUM> of <FIG> has advanced to a second stage. At this second example stage, the ILD layer <NUM> of <FIG> has been slightly over-etched through the ILD layer <NUM>. Trenches <NUM> have been formed therein, the trenches passing into the material below including the gate material <NUM>, the N+ region <NUM>, and the P+ region <NUM>. The ILD layer has been transformed into the ILD layer <NUM> first illustrated in <FIG>.

In <FIG>, the workpiece <NUM> of <FIG> has advanced to another stage. At this third example stage, P+ material <NUM> has been added into the trenches <NUM> of <FIG>. The P+ material <NUM> is a same conductivity type as the type of the doping of the body region <NUM>. Accordingly, a first P+ region <NUM> has been formed in the N- drift layer <NUM> and through the N+ region <NUM>. The first P+ region <NUM> is isolated from the gate material <NUM> and the insulation material <NUM> by the N+ region <NUM> and N- layer <NUM>. Further a second P+ region <NUM> has been formed in the P-type body region <NUM>. A subsequent step in a method of formation would place contacts or contact material in the trenches as shown in <FIG>. Thus, <FIG> illustrate a sequence of steps of a method of formation of the device <NUM> of <FIG>.

<FIG> is a diagram that illustrates a top view of a first semiconductor layout using a P+ region proximate a source of a field effect device in accordance with some embodiments. The P+ region of <FIG> is an embodiment of a cathode short region such as the P+ region <NUM> in <FIG> and the P+ region <NUM> in <FIG>.

In <FIG>, the semiconductor layout <NUM> includes several materials applied as layers to create a field effect device of desired size. For example, the layout <NUM> includes a plurality of gate columns <NUM>. According to some embodiments, a gate column <NUM> includes a gate material and an insulative material. The layout <NUM> also includes N+ regions <NUM>. P+ regions <NUM> are inside the N+ regions <NUM>. The P+ regions <NUM> may be P+ implants. The P+ regions <NUM> are cathode shorts - cathode short regions - for the device of the layout <NUM>. Source contacts <NUM> are placed over or at an intersection of the N+ regions <NUM> and the P+ regions <NUM>. One or more source contact layers <NUM> may be placed onto the device of the layout <NUM> in contact with the source contacts <NUM>. While not illustrated, source contacts <NUM> may be coupled to metal traces, vias, and the like thereby routed out to another metal layer.

In <FIG>, the layout <NUM> also includes partially exposed N- drift regions <NUM> outside of STI material <NUM>. Enclosed by the STI material <NUM> are P+ regions <NUM>. The P+ regions <NUM> are of a same conductivity type as the P+ regions <NUM>. Body contacts <NUM> are coupled to a body region portion of the device such as being coupled to the P+ regions <NUM>. One or more body contact layers <NUM> may be placed onto the device of the layout <NUM> in contact with the body contacts <NUM>. A unit or cell <NUM> includes a set of N+ regions <NUM>, a set of P+ regions <NUM>, and a set of source contacts <NUM>. The cell <NUM> also includes a set of body contacts <NUM>, a P+ region <NUM>, STI material <NUM>, and an N- drift region <NUM>.

<FIG> is a diagram that illustrates a cell <NUM> of the semiconductor layout first illustrated in <FIG>. A unit or cell <NUM> includes a set of N+ regions <NUM>, a set of P+ regions <NUM>, and a set of source contacts <NUM>. The cell <NUM> also includes a set of body contacts, a P+ region, STI material, and an N- drift region. Three cross-sectional views are indicated: a first cross-sectional view along line <NUM>-<NUM>' corresponding to <FIG>, a second cross-sectional view along line <NUM>-<NUM>' corresponding to <FIG>, and a third cross-sectional view along line <NUM>-<NUM>' corresponding to <FIG>.

<FIG> is a diagram illustrating a cross-sectional view of the cell <NUM> first illustrated in <FIG>. <FIG> is the cross-section along line <NUM>-<NUM>' as shown in <FIG>. In <FIG>, the device <NUM> includes several layers of a semiconductor substrate, in order from bottom to top: a first N-type substrate such as a first N+ substrate region <NUM>, an N- drift region <NUM>, a P-type body region such as P- body region <NUM>, and a second N- drift region <NUM>. The first N+ substrate region <NUM> includes a first surface <NUM> adjacent to a drain contact <NUM>. An insulator material <NUM> lies adjacent to the first N- drift region <NUM>, the P-body region <NUM>, and the second N- drift region <NUM>. Gate material <NUM> lies next to the insulator material <NUM> within the gate column <NUM>. The insulator material <NUM> may be assembled to the device <NUM> in a separate step from assembling the gate material <NUM>. In <FIG>, two N+ regions <NUM> and a P+ region <NUM> are surrounded by the second N- drift region <NUM>. The N+ regions <NUM> create a ring in which the island of P+ region <NUM> is located. Source contacts <NUM> are positioned adjacent to both the N+ regions <NUM> and the P+ region <NUM> thereby electrically coupling or shorting the P+ region <NUM> with the N+ regions <NUM>. The P+ region <NUM> is of a same conductivity type as the P- body region <NUM>.

<FIG> is a diagram illustrating a cross-sectional view of the cell <NUM> first illustrated in <FIG> in a plane parallel to the cross-sectional plane of the view illustrated in <FIG> is the cross-section along line <NUM>-<NUM>' as shown in <FIG>.

In <FIG>, the device <NUM> includes the layers of the semiconductor substrate, in order from bottom to top: the first N+ substrate region <NUM>, the N- drift region <NUM>, the P-body region <NUM>, and the second N- drift region <NUM>. The first N+ substrate region <NUM> includes the first surface <NUM> adjacent to the drain contact <NUM>. The insulator material <NUM> lies adjacent to the first N- drift region <NUM>, the P- body region <NUM>, and the second N-drift region <NUM>. Gate material <NUM> lies next to the insulator material <NUM> within the gate column <NUM>. In <FIG>, the second N- drift region <NUM> is separated from the body P+ region <NUM> by STI material <NUM>. A body contact <NUM> is positioned adjacent to the P+ region <NUM> at the second surface <NUM>. While not illustrated in <FIG>, an insulating layer may be formed or placed adjacent to the second surface <NUM>.

<FIG> is a diagram illustrating a cross-sectional view of the cell <NUM> first illustrated in <FIG> in a plane perpendicular to the cross-sectional planes of the views illustrated in <FIG>. <FIG> is the cross-section along line <NUM>-<NUM>' as shown in <FIG>.

In <FIG>, the device <NUM> includes the layers of the semiconductor substrate, in order from bottom to top: the first N+ substrate region <NUM>, the N- drift region <NUM>, the P- body region <NUM>, and the second N- drift region <NUM>. The first N+ substrate region <NUM> includes the first surface <NUM> adjacent to the drain contact <NUM>. In <FIG>, the second N-drift region <NUM> is separated from the body P+ region <NUM> by STI material <NUM>. Body contacts <NUM> are positioned adjacent to the P+ region <NUM> at the second surface <NUM>. Two portions of the N+ region <NUM> isolate the P+ region <NUM> at the top surface <NUM>. The two portions of the N+ region <NUM> and the P+ region <NUM> are surrounded by the second N-drift region <NUM>.

<FIG> is a diagram that illustrates a top view of a second example semiconductor layout using a P+ region proximate a source of a field effect device in accordance with some embodiments. In <FIG>, from left to right, various columns <NUM> of material are formed into a field effect device <NUM>. The device <NUM> may extend to an arbitrary first dimension from left to right thereby having an arbitrary number of columns <NUM> of material. That is, a unit <NUM> of the semiconductor device <NUM> may be repeated horizontally in <FIG> one or more times. Further, the device <NUM> may extend to an arbitrary second dimension from top to bottom thereby having an arbitrary number of contacts <NUM>, <NUM> in the device <NUM>. The device <NUM> is comprised of alternating sequences of gate column regions <NUM>, source column regions <NUM>, and body column regions <NUM> according to some embodiments.

In <FIG>, the device <NUM> includes columns of N- drift material <NUM>, source-located P+ material <NUM>, N+ material <NUM>, gate column <NUM>, STI material <NUM>, and body-located P+ material <NUM>. The STI material <NUM> is used to isolate a P- body (via the body-located P+ material <NUM>) from the N- drift material <NUM>. The source-located P+ material <NUM> and the body-located P+ material <NUM> are illustrated in <FIG> as a same black-filled material. In practice, the source-located P+ material <NUM> may be different from the body-located P+ material <NUM> in terms of composition of doping material, amount of doping material, area of application of doping material, volume of doping material, and so forth including combinations of the same.

Columns of source contacts <NUM> are placed along source regions <NUM> of the device <NUM> in various positions. According to some embodiments, and as in <FIG>, the source contacts <NUM> are positioned at regular intervals vertically along the device <NUM>, and positioned horizontally at the intersection of the source-located P+ material <NUM> and the N+ material <NUM>. In <FIG>, columns of body contacts <NUM> are placed along the body-located P+ material <NUM>. Source contacts <NUM> and body contacts <NUM> may be routed out through metal traces, metal vias, and the like to metal or conductive layers of the device <NUM>.

In the device <NUM>, the N+ material <NUM> is positioned adjacent to the source-located P+ material <NUM>. In other embodiments, positions of the N+ material <NUM> may be positioned on an opposite side of the source-located P+ material <NUM>. Columns <NUM> of semiconductor material are created according to epitaxial layer building processes.

<FIG> illustrates a portion and repeatable unit <NUM> of the semiconductor layout first illustrated in <FIG>. The unit <NUM> includes columns of N- drift material, source-located P+ material, N+ material contacting the N- drift material, gates, STI material, and body-located P+ material. Two cross-sectional views are indicated: a first cross-sectional view along line <NUM>-<NUM>' corresponding to <FIG>, and a second cross-sectional view along line <NUM>-<NUM>' corresponding to <FIG>. <FIG> illustrate that source and body contact regions run parallel to each other and to the gate. The gates may be formed by way of gate trenches formed in the device <NUM>.

<FIG> illustrates a cross-sectional view of the unit <NUM> first illustrated in <FIG> and illustrates portions of the device <NUM> at the cross-section along line <NUM>-<NUM>' shown in <FIG>. In <FIG>, the device <NUM> includes a drain contract <NUM> at a first surface <NUM> along the bottom of the semiconductor substrate. The device <NUM> also includes a layer of N-type material such as a N+ substrate <NUM>, an adjacent first N- drift region <NUM>, a P-type material such as the P- body region <NUM>, and a second N- drift region <NUM>. The N-drift region is first shown in <FIG>.

The device <NUM> further includes the source-located P+ material <NUM> and the source-located N+ material <NUM>. The N+ material <NUM> isolates the source-located P+ material <NUM> from the gate <NUM>. The gate <NUM> includes a gate material <NUM> which is isolated by insulation material <NUM> from the first N- drift material, the P- body region <NUM>, the second N- drift material <NUM>, and the N+ material <NUM>. The top surface <NUM> of the device <NUM> is visible in <FIG>. An insulating layer, such as a deposited oxide layer, may be placed adjacent to the top surface <NUM>.

A source contact 1106is coupled to the device <NUM> at an intersection of the source-located P+ material <NUM> and the source-located N+ material <NUM>. While the source contact <NUM> overlays only a portion of the source-located P+ material <NUM> and the source-located N+ material <NUM>, in other embodiments, the source contact <NUM> may completely cover the source-located P+ material <NUM>, the source-located N+ material <NUM>, or both the source-located P+ material <NUM> and the source-located N+ material <NUM>. As previously explained, according to another embodiment, locations of the source-located P+ material <NUM> and the source-located N+ material <NUM> may be reversed as compared to the embodiment illustrated in <FIG>. STI material <NUM> is positioned between the second N- drift material <NUM> and the P+ material <NUM>. A body contact <NUM> is positioned adjacent to the P+ material <NUM>.

<FIG> is a diagram illustrating a cross-sectional view of the unit <NUM> first illustrated in <FIG> and illustrates portions of the device <NUM> at the cross-section along line <NUM>-<NUM>' shown in <FIG>. In <FIG>, the device <NUM> includes the drain contract <NUM> at the first surface <NUM> along the bottom of the semiconductor substrate. The device <NUM> also includes a layer of N-type material such as a N+ substrate <NUM>, an adjacent first N- drift region <NUM>, a P-type material such as the P- body region <NUM>, and a P+ material <NUM> along the top of the device <NUM>. The P+ material <NUM> forms the top surface <NUM> and is used to make the contacts to the P- body. The column of P+ material <NUM> is first shown in <FIG>. Five body contacts <NUM> are positioned adjacent to the body P+ material <NUM>.

<FIG> is a graph <NUM> that illustrates two plots related to parasitic bipolar characteristics for field effect devices as described herein in accordance with some embodiments. The first plot, as indicated along a first vertical axis <NUM>, illustrates the body (or base) current IB versus body-source (base-emitter) voltage VBE applied to two MOSFET devices: line <NUM> for a device with a cathode short P+ region proximate a source and line <NUM> for a device without such a region. In both cases, the gate is electrically connected to the source and the drain (collector) and is at 5V. In the first plot of <FIG>, as voltage VBE is increased, current IB is generally higher for the cathode short device thereby indicating a benefit through an increased contribution of hole current to the base current.

The second plot of <FIG>, as indicated along a second vertical axis <NUM>, illustrates the bipolar gain, i.e., the ratio of drain (collector) current Ic to current IB versus voltage VBE applied to two MOSFET devices: line <NUM> for a device with a cathode short P+ region proximate a source and line <NUM> for a device without such a region. As the voltage VBE is increased, the ratio IC /IB is lower for the cathode short device thereby indicating another benefit through reduction in parasitic bipolar gain. Thus, a field effect device with a cathode short as described herein provides improved performance over other types of structures.

<FIG> is a graph that illustrates latch up voltage of a field effect device in accordance with some embodiments. In <FIG>, the plot <NUM> illustrates current Ic plotted against voltage VCE (drain-source voltage) applied to two MOSFET devices under open body (open base) conditions. In <FIG>, as voltage VCE is increased, current Ic effectively begins to flow at two different values of latch up voltage VCE. The first latch up voltage VCE <NUM> is for a MOSFET device without a P+ region in a second N- drift region. The second latch up voltage VCE <NUM> is for a MOSFET device with a P+ region in the second N- drift region and adjacent to an N+ region, the P+ region shorted by way of a conducting contact to the N+ region. In <FIG>, the second voltage VCE <NUM> is substantively higher than the first voltage VCE <NUM> and thus a field effect device with a cathode short as described herein provides improved parasitic bipolar performance over other types of structures.

<FIG> illustrates a method <NUM> for forming a vertical bidirectional power MOSFET device with a cathode short region according to some embodiments. The method <NUM> includes, at block <NUM>, forming or growing a first N- drift epitaxial layer on top of a N-type substrate. For example, a first forward blocking N- drift epitaxial layer is grown on a heavy N+ substrate. A second N- epitaxial layer may be grown if desired for a layer of a different doping concentration to create a reverse blocking drift region.

At block <NUM>, a body region of a P- type is formed as a layer adjacent to the first N- drift epitaxial layer. For example, a deep P type buried layer may be implanted to create a body region and a channel. Alternatively, a P type buried layer also could be epitaxially grown after the growth of the first forward N- drift epitaxial layer. A chain P implant may be used for extending the body region all the way to a surface where a body contact may be placed, grown or applied.

At block <NUM>, an insulated control gate is formed adjacent to the body region and first epitaxial layer. By way of example, this block <NUM> may include creation of a trench gate by etching trenches and growing a gate oxide or filling with a gate polysilicon pattern or CMP polysilicon. The polysilicon may be slightly recessed to relieve electric field crowding in a gate dielectric during reverse blocking.

At block <NUM>, a second N- drift epitaxial layer is formed adjacent to the body region. Body and source contact regions may be isolated at the N-P body junction such as through an STI technique by application of an appropriate material.

At block <NUM>, an N+ region is formed in the second N- drift epitaxial layer. At block <NUM>, a P+ region is formed in the second N- drift epitaxial layer. At this block <NUM>, the P+ region is shorted such as by contacting the P+ region and the N+ region of block <NUM> with a same metal lead, metal contact, or other element. At block <NUM>, a P+ region is formed in the body region. The formation of P+ regions at blocks <NUM> and <NUM> could be combined together to be in the same step using appropriate mask layers and processes.

Contacts for the MOSFET device may be created through a plug process or other metallization technique such that body and source are routed out separately, which may be required for reverse blocking. A drain contact may be formed by a backside metallization technique. Implants and contact masks may be designed such that the P+ region of block <NUM> is partially or completely overlapped by a source contact and the N+ region of block <NUM> is partially or completely overlapped by the source contact.

There are many applications of the techniques and structures described herein. For example, a bi-directional device, which normally has poor SOA may be commercially viable with use of a cathode short. An improved bidirectional device may be used as: a power switch to control all types of loads including resistive, inductive and capacitive; as a device in an H-bridge configuration for DC and pulse width modulation (PWM) motor control; an LED; a light bulb driver including PWM dimming; and a stop start control unit (CRC mode).

Conclusion. MOSFET devices come in a wide variety of forms and employ other materials besides simple metals and oxides. The use of "metal" in MOSFET as used herein can refer to any form of an electrically conductive material (e.g., simple metals, polysilicon, metal alloys, semi-metals, mixtures, semiconductors, conductive organics, conductive silicides, and conductive nitrides). A wide variety of semiconductors may be used for forming MOSFET devices (e.g., types IV, III-V and II-VI semiconductors, organic semiconductors, layered structures, etc.) such as, for example, semiconductor-on-insulator (SOI) structures. Accordingly, "semiconductor" as used herein is intended to include these and other materials, and arrangements suitable for forming field controlled devices. The word "oxide" in the label MOSFET stands for any of a large number of insulating dielectrics, and is not limited merely to oxides. Accordingly, the terms metal, oxide, semiconductor, and MOSFET are intended to include these and other variations.

Claim 1:
A field effect device (<NUM>), comprising:
a semiconductor body (<NUM>) having a first surface (<NUM>) and a second surface (<NUM>);
a source contact (<NUM>) coupled to the semiconductor body (<NUM>) proximate the second surface (<NUM>);
a drain contact (<NUM>) coupled to the semiconductor body (<NUM>) at the first surface and separated from the source;
a body contact (<NUM>) coupled to the semiconductor body (<NUM>) proximate the second surface (<NUM>);
an insulated control gate (<NUM>) extending through the semiconductor body (<NUM>) from the second surface (<NUM>) toward the first surface (<NUM>), not reaching the drain contact (<NUM>) and configured to control a conductive channel extending between the source and drain contacts (<NUM>, <NUM>);
a body region (<NUM>) of a first conductivity type and having an extension region extending to the body contact (<NUM>);
a first doped region (<NUM>) of a second conductivity type and adjacent to the drain contact (<NUM>);
a first drift region (<NUM>) of the second conductivity type and which forms a N-P junction with the body region (<NUM>) within the semiconductor body (<NUM>), the first drift region (<NUM>) having a doping concentration below that of the first doped region (<NUM>);
a second drift region (<NUM>) of the second conductivity type, the second drift region separating the body region (<NUM>) from the source contact (<NUM>);
a second doped region (<NUM>) of the first conductivity type adjacent and connected to the source contact (<NUM>);
a third doped region (<NUM>) of the second conductivity type different to the first conductivity type, the second doped region (<NUM>) being adjacent and connected to the second doped region (<NUM>) and adjacent to the source contact (<NUM>); and
wherein the second drift region (<NUM>) isolates the second doped region (<NUM>) and the third doped region (<NUM>) from a remainder of the semiconductor body (<NUM>).