Patent Description:
Multi-layered structures comprising a device layer with a device quality surface and a substrate that has a different crystal lattice structure than the material of the device layer are useful for a number of different purposes. These multi-layered structures typically comprise multiple layers of material having differing lattice constants. The lattice mismatch between layers causes the layers to be strained. Misfit dislocations may spontaneously form in the device layer to relax the strain between layers. Such dislocations degrade the quality and usefulness of the multi-layer semiconductor structure.

A continuing need exists for methods for relaxing the strain between lattice-mismatched semiconductor layers and for methods that result in substrates and device layers that are substantially free of dislocations.

One aspect of the present disclosure is directed to a process for relaxing the strain in a heterostructure comprising a substrate, a surface layer disposed on the substrate and an interface between the substrate and the surface layer. The substrate comprises a central axis, a back surface which is generally perpendicular to the central axis, and a diameter extending across the substrate through the central axis. A dislocation source layer is formed in the substrate. The substrate is radially compressed to generate dislocations and glide the dislocations from the dislocation source layer toward the surface layer. This method is not forming part of the claimed invention; however, the invention relates to a corresponding apparatus configured to perform such a method. The inventive apparatus is specified in claim <NUM>.

Another aspect of the present disclosure is directed to a process for preparing a relaxed heterostructure. A surface layer is deposited on a front surface of the semiconductor substrate thereby creating a strain between the surface layer and the substrate. A dislocation source layer is formed in the substrate. The strain in the surface layer and the substrate is relaxed by radially compressing the substrate to generate dislocations and glide the dislocations from the dislocation source layer toward the surface layer. This method is not forming part of the claimed invention.

Another aspect of the present disclosure is directed to a method for radially compressing a semiconductor structure in an apparatus. The structure has a front surface, a back surface and a circumferential edge. The apparatus includes a structure holder comprising a top plate and a back plate for contacting the structure adjacent a circumferential edge of the structure. The top plate is adapted to contact the front surface of the structure and the back plate is adapted to contact the back surface of the structure. A peripheral chamber is formed between the top plate, back plate and circumferential edge of the structure. The pressure in the peripheral chamber is changed to radially compress the structure. This method and corresponding apparatus are not forming part of the claimed invention.

In accordance with one or more aspects of the present disclosure, heterostructures with reduced strain between the substrate and a surface layer having a different lattice constant than the substrate may be prepared such as by the process of <FIG>. The surface layer may also be referred to herein as an "epitaxial layer", "heteroepitaxial layer", "deposited film", "film", "heterolayer" or "deposited layer". A heterostructure having a substantially relaxed surface layer and a reduced concentration of misfit dislocations, also referred to as threading dislocations, may be formed.

In general, the processes of the present disclosure may include forming a dislocation source layer in a semiconductor substrate, depositing a heterolayer on the substrate before or after formation of the dislocation source layer and radially compressing the heterostructure to generate (i.e., "activate") dislocations and glide the dislocations from the dislocation source layer toward the surface layer. The activation of the source layer and the gliding of the dislocations from the source layer toward the interface with the deposited layer occur concurrently by applying compression to the substrate. The stress may be applied in one or more steps and in various combinations to activate and glide the dislocations, thereby plastically compressing the heterostructure.

The heterolayer may have a crystal lattice constant, asi, which differs from the native crystal lattice constant of the substrate, as, to form a film on the surface of the substrate. Generally, the crystal lattice constant, asi, of the heterolayer is less than the native crystal lattice constant of the substrate, aS, such that by controlling the generating and gliding of the dislocation loops in the substrate by compression, the substrate may be plastically deformed and aligned more suitably with the crystal lattice of the film thereby allowing the film to be completely relaxed and having a reduced density of threading dislocations on the substrate.

The methods of the present disclosure have several advantages over conventional methods for relaxing heterolayers. Conventional methods create a large asymmetry in the stresses between the film and the substrate which leads to dislocation generation where the stresses are the greatest, i.e., the film. By confining the dislocation loops to the film, the dislocations leave segments behind which act as degrading threading dislocations. Much effort has been employed in attempting to minimize the density of such threading dislocations.

In contrast, methods of the present disclosure result in an asymmetry of stresses with the dislocation generation occurring in the substrate (e.g., by weakening the substrate and using a relatively thin film to void dislocation generation therein while weakening the substrate). This allows dislocations to be confined to the substrate while forming the misfit dislocation layer at the interface between the substrate and the film. Upon weakening the substrate by introducing dislocations in a variety of controlled ways, external stresses may be applied to the system to activate the dislocations. This differs from conventional methods which result in self-relaxation due to the relatively large intrinsic, internal stresses (i.e., relaxation without application of external stresses). The methods of the present disclosure involve relaxation other than by self-relaxation by weakening and application of external stress at appropriate temperatures with a relatively thin film such that self-relaxation does not occur.

Referring to <FIG>, the semiconductor substrate <NUM> may be any single crystal semiconductor material suitable for use as a substrate for supporting a surface layer such as by deposition of an epitaxial layer by chemical vapor deposition. In general, the semiconductor substrate may be composed of a material selected from the group consisting of silicon, silicon carbide, sapphire, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenic, indium gallium arsenic or any combination thereof. Typically, the semiconductor substrate is composed of silicon.

The semiconductor substrate <NUM> may be in any shape suitable for both use as a substrate for depositing a surface layer and suitable for applying a stress to the substrate material as described in more detail below. Typically, the semiconductor substrate has a central axis <NUM>; an interface <NUM> with the deposited layer <NUM> and a back surface <NUM>, the substrate-surface layer interface <NUM> and back surface <NUM> being generally perpendicular to the central axis <NUM>; a thickness t, corresponding to the distance from the interface to the back surface of the substrate; a circumferential edge <NUM>; and a diameter D, extending across the substrate through the central axis. It should be noted that, for illustrative purposes, the back surface <NUM> will be described as the opposing surface at or near which the dislocation source layer will be formed and as such may be referred to herein as the "opposing surface" and/or the "damaged surface. " In this regard, the heterostructure itself and the deposited layer <NUM> described below are generally concentric with the substrate <NUM> and also include a central axis <NUM>; a circumferential edge <NUM>; and a diameter D, extending across the heterostructure (and also the surface layer) and through the central axis.

The substrate <NUM> may have any suitable diameter for use as a substrate upon which a semiconductor layer will be deposited. In general, the substrate <NUM> has diameter of about <NUM> or more. Typically, the substrate <NUM> has a diameter of about <NUM> or more, about <NUM> or more or even about <NUM> or more. It should be noted that the substrate diameter may be the diameter prior to plastically deforming the heterostructure, in which case, the diameter may increase or decrease from the stated values after plastic deformation as discussed in more detail below. Alternatively, the substrate prior to plastic deformation may have a diameter less than or greater than the stated values such that the diameter after plastic deformation is approximately equal to the stated values.

Similarly, the substrate <NUM> may have any thickness, t, suitable for use as a substrate upon which a semiconductor layer may be deposited. For example, the substrate may have a thickness, t, of from about <NUM> microns to about <NUM> microns, typically from about <NUM> microns to about <NUM> microns, from about <NUM> microns to about <NUM> microns, from about <NUM> microns to about <NUM> microns or even from about <NUM> microns to about <NUM> microns.

In some embodiments, for example, the substrate <NUM> may be a single crystal silicon wafer that has been sliced from a single crystal silicon ingot grown by Czochralski crystal growing methods having a diameter of about <NUM> or more, about <NUM> or more, about <NUM> or more or even about <NUM> or more and a thickness of from about <NUM> microns to about <NUM> microns or even from about <NUM> microns to about <NUM> microns.

The substrate surface upon which the epitaxial layer is deposited may be polished such that it is suitable for depositing the epitaxial layer or may be further conditioned prior to chemical vapor deposition. The opposing surface may also be polished or alternatively may be un-polished, i.e., as-ground, as-lapped or as-lapped and etched, without departing from the scope of the present disclosure. In various embodiments, the opposing surface may be left in an unpolished state, wherein the as-ground, as-lapped or as-lapped and etched surface may be utilized as a dislocation source layer. Alternatively or in addition, the opposing surface may be damaged to form a dislocation source layer as described in more detail below.

It should be noted that Czochralski-grown silicon typically has an oxygen concentration within the range of about <NUM> × <NUM><NUM> to about <NUM> × <NUM><NUM> atoms/cm<NUM> (ASTM standard F-<NUM>-<NUM>). In general, a single crystal silicon wafer used for a substrate in the present disclosure may have an oxygen concentration falling anywhere within or even outside the range typically attainable by the Czochralski process, provided the oxygen concentration is not so excessive as to prevent the activation and gliding of the dislocations.

A surface layer <NUM> may be located on the front surface of the substrate <NUM>. The deposited layer <NUM> may be any single crystal semiconductor material suitable for depositing as an epitaxial layer by chemical vapor deposition. Generally, the heterolayer includes a crystal lattice constant, asl, that is less than the native crystal lattice constant of the substrate, aS. The deposited layer may be composed of any suitable material and, as in some embodiments, is composed of a material selected from the group consisting of silicon, silicon carbide, sapphire, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenic, indium gallium arsenic or any combination thereof. In embodiments in which the substrate is composed of silicon, heterolayers with a smaller lattice constant include, for example, gallium nitride.

Essentially any technique generally known in the art may be used to form the deposited layer, such as one of the known epitaxial deposition techniques. Generally speaking, the thickness of the deposited layer may vary greatly without departing from the scope of the present disclosure. The thickness may have, for example, a substantially uniform thickness, the average thickness thereof being at least about <NUM> microns, at least about <NUM> microns, at least about <NUM> micron, and even at least about <NUM> microns. Alternatively, it may be desirable to express thickness in terms of a range. For example, the average thickness may typically be in the range of from about <NUM> microns to about <NUM> microns, such as from about <NUM> micron to about <NUM> micron.

It should be noted that as the deposited layer is grown on a substrate having a differing lattice constant, an equal, but opposite stress is formed in both the deposited layer and the substrate. The relative amount of stress in the deposited layer and the substrate, just above and just below the interface, is proportional to the relative thicknesses of the deposited layer and the substrate. As a result, the stress in the deposited layer just above the interface may be several orders of magnitude larger than the stress in the substrate just below the interface. The stress in the deposited layer can increase during growth until the layer self-relaxes by forming misfit or threading dislocations in the deposited layer. To avoid self-relaxation of the deposited layer, therefore, it is preferable at least initially to grow a thin deposited layer on the substrate. The thin layer may then be relaxed or partially relaxed to at or near its native lattice constant by activating and expanding dislocations in the substrate as discussed in more detail below. If a thicker deposited layer is desired, additional material may be deposited after the layer has been sufficiently relaxed.

Essentially any technique generally known in the art may be used to form a deposited layer on the substrate. For example, epitaxial deposition techniques (e.g., atmospheric-pressure chemical vapor phase deposition (APCVD); low- or reduced-pressure CVD (LPCVD); ultra-high-vacuum CVD (UHVCVD); molecular beam epitaxy (MBE); or, atomic layer deposition (ALD)) may be used. The epitaxial growth system may comprise a single-wafer or a multiple-wafer batch reactor.

The surface layer <NUM> includes a surface which forms the front surface <NUM> of the heterostructure. The surface layer <NUM> may continuously extend across the entire diameter of the substrate <NUM> as shown in <FIG>. In some embodiments, the surface layer <NUM> does not extend continuously over the substrate <NUM> but rather includes a number of discontinuous segments or "islands" of semiconductor material that are disposed on the substrate as further described below. For example, the surface layer may be disposed over less than about <NUM>% of the substrate or, as in other embodiments, less than about <NUM>%, less than about <NUM>%, less than about <NUM>% or less than about <NUM>% of the substrate.

A dislocation source layer <NUM> is located within the substrate <NUM> and may be spaced from the substrate surface upon which the epitaxial layer is to be deposited. Typically, the dislocation source layer <NUM> is at or near the surface opposing the surface upon which the epitaxial layer has been or will be deposited. For example, if the epitaxial layer is to be deposited on the front surface of the substrate, the dislocation source layer <NUM> will be at or near the back surface <NUM> of the substrate. In such an example, the front surface of the substrate will become the interface between the substrate and the deposited layer <NUM>.

The source layer <NUM> is present or is installed over a substantial radial width of the substrate <NUM>. In the embodiment illustrated in <FIG>, the source layer <NUM> extends across the entire diameter of the substrate <NUM>. Although this embodiment is preferred, in other embodiments the source layer may not extend over the entire diameter. In general, therefore, source layer <NUM> will have a radial width of typically at least about <NUM>%, more typically at least about <NUM>% and still more typically at least about <NUM>% of the radius of the wafer or even at least about <NUM>% of the radius of the wafer. In some embodiments, the source layer <NUM> extends to within a few millimeters of the circumferential edge, for example, to within about <NUM> of the circumferential edge.

In general, the source layer <NUM> may include any portion of the substrate provided the source layer does not include the surface upon which the epitaxial layer is to be deposited. Generally the source layer <NUM> has a thickness of about <NUM> microns or less, about <NUM> microns or less, about <NUM> microns or less or about <NUM> microns or less (e.g., from about <NUM> micron to about <NUM> microns, from about <NUM> micron to about <NUM> microns, from about <NUM> micron to about <NUM> microns or from about <NUM> microns to about <NUM> microns). The source layer <NUM> may include the back surface of the substrate and extend therefrom. It should be noted that the source layer <NUM> need not include the back surface of the wafer and may extend from a depth from the back surface toward the front surface of the substrate.

The dislocation source layer <NUM> may be any layer capable of generating a measurable concentration of dislocations when subjected to sufficiently high stresses at sufficiently high temperatures. In general, the dislocation source layer <NUM> is capable of generating a measurable concentration of dislocations when subjected to a compressive stress of between about <NUM> MPa and about <NUM> MPa, (typically at around about <NUM> MPa at temperatures of between about <NUM> and about <NUM>) as discussed in more detail below with regard to the activation of dislocations within the substrate.

The dislocation source layer <NUM> may be formed in the substrate <NUM> before or subsequent to the deposition of the surface layer <NUM>. In embodiments wherein the substrate is a wafer sliced from a single crystal ingot, the dislocation source layer <NUM> may be mechanical damage caused by the slicing process, grinding process or lapping process included as part of the overall wafering process.

Alternatively or in addition, the dislocation source layer <NUM> may be formed in part or in its entirety by mechanically damaging the back surface of the substrate by one or more processes selected from the group consisting of: grinding the back surface, lapping the back surface, installing soft damage by sandblasting the back surface, forming indentations on the back surface, implanting ions in the back surface and/or combinations thereof.

In some embodiments, the dislocation source layer <NUM> may be formed by pressing an array of pointed pins onto the wafer back surface to form indentations in the back surface. The indentations may be formed non-uniformly across the surface or may be formed in a predetermined pattern. Such a pattern may be arranged in a specific relation to the wafer crystal directions. For example, a square matrix pattern could be arranged at a shallow angle to the <NUM> direction. This may allow for the dislocations generated at these sites to glide along parallel glide planes and not interact with each other. Furthermore, accurate control of the dislocation loop density may be had by such a treatment.

In some embodiments, the source layer <NUM> may be formed by implanting ions through the back surface of the substrate. The implanted ions may be electrically isoelectronic, neutral, or inert to minimize any effect upon the electronic properties of the substrate. For example, the implanted ions may be selected from the group consisting of silicon, germanium, hydrogen, helium, neon, argon, xenon, and combinations thereof.

The ions are implanted to a target depth, Di, relative to the back surface. As a practical matter, however, some of the implanted ions will not travel this distance and others will travel an even greater distance (i.e., reach a greater depth relative to the back surface). The actual ion implantation depth may vary from Di by about <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, or more. This creates a zone or layer of amorphous material containing a relatively high concentration of implanted ions at or near Di, with the concentration of implanted ions decreasing from Di in the direction of front surface <NUM> and in the opposite direction. Target depth, Di, may also be referred to as the projected range of the implanted ions.

Implantation depth may be affected, at least in part, by the ionic species implanted, since lighter ions tend to penetrate further into the substrate for a given implantation energy. Thus, for example, at an implant energy of <NUM> keV, silicon ions will have an average implant depth of about <NUM>Å, whereas germanium ions will have an average implant depth of <NUM>Å. In general, ions are preferably implanted at an energy of at least about <NUM> keV, such as at least about <NUM> keV, or even at least about <NUM> keV. In one application, ions are implanted at an energy of at least about <NUM> keV and less than about <NUM> keV. The ion and the implant energy selected should be sufficient to form an amorphous layer in the substrate which acts as the dislocation source layer.

Generally, dislocation loops form at the end of range of the implanted ions upon subsequent anneal if sufficient energy is used to implant a sufficient concentration of ions to form an amorphous layer of silicon. Typically, the dislocation loops may form at a depth of about <NUM>Å to about <NUM>Å below the implanted ions, although the exact depth may be more or less. In general, it is more difficult to form amorphous material using lower mass elements. Accordingly, a much higher concentration of low mass elements must be used to induce sufficient damage, whereas lower concentrations of high mass elements are sufficient to form amorphous silicon. For example, when the implanted ions are silicon ions, the implanted dose is preferably at least about <NUM> × <NUM><NUM> atoms/cm<NUM>, such as at least about <NUM> × <NUM><NUM> atoms/cm<NUM>, or even at least about <NUM> × <NUM><NUM> atoms/cm<NUM>. In one preferred embodiment, the implanted ion dose is at least about <NUM> × <NUM><NUM> atoms/cm<NUM>. By comparison, when the implanted ions are the higher mass germanium ions, the implanted dose is preferably at least about <NUM> × <NUM><NUM> atoms/cm<NUM>, such as at least about <NUM> × <NUM><NUM> atoms/cm<NUM>, or even at least about <NUM> × <NUM><NUM> atoms/cm<NUM>. In one preferred embodiment, the implanted ion dose is at least about <NUM> × <NUM><NUM> atoms/cm<NUM>.

In some preferred embodiments, the source layer <NUM> is formed by grinding the back surface of the substrate. The surface may be ground using any grinding processes typically used in the semiconductor silicon industry to shape the surface of a silicon wafer after being sliced from a Czochralski-grown single crystal silicon ingot. In a particularly preferred embodiment, the back surface may be ground using a grinding process which uses a grit size of about <NUM>.

The dislocation source layer is activated to form dislocations at or near the source layer which may be glided toward the substrate-surface layer interface. In accordance with embodiments of the present disclosure, activation and gliding of dislocations is performed after the surface layer has been deposited on the substrate such that the substrate and/or surface layer are under strain.

The dislocation source layer is activated by subjecting the dislocation source layer (and typically subjecting the substrate) to a stress by compressing the substrate at an elevated temperature to cause the formation of dislocations. Compression is applied to the entire substrate in a direction perpendicular to the axis, i.e., in the radial direction using one or more suitable apparatus. That is, the wafer is compressed radially inward from the peripheral edge. In this manner, the dislocations will form at or near the source layer and the dislocations will glide towards the opposite surface.

In general, more heavily damaged dislocation source layers will activate at lower stress levels and at lower temperatures whereas less heavily damaged dislocation source layers will activate at higher stress levels and temperatures. In general, stress applied by compression of at least about <NUM> MPa, typically from about <NUM> MPa to about <NUM> MPa or from about <NUM> MPa to about <NUM> MPa is applied to the dislocation source layer at a temperature of between about <NUM> and about <NUM>. More typically, the stress is from about <NUM> MPa to about <NUM> MPa or from about <NUM> MPa to about <NUM> MPa. Typically, the activation and/or gliding of the dislocations is carried out at temperatures from about <NUM> to about <NUM> or even from about <NUM> to about <NUM>. For example, typical stresses that may be applied to activate a dislocation source layer formed by lapping and/or grinding may be about <NUM> MPa at temperatures greater than about <NUM> and even more typically at temperatures greater than about <NUM>. Other, more highly damaged layers may activate at even lower stress levels.

The substrate is maintained under stress at an elevated temperature for duration sufficient to activate and glide dislocations. In general, the substrate is maintained under stress and at an elevated temperature, as described above, for a period of at least about <NUM> seconds and may be maintained under those conditions for a period of at least about <NUM> hours, at least about <NUM> hours or even longer. Typically, the substrate is maintained under stress at an elevated temperature for a period of at least about <NUM> minute, from about <NUM> minutes to about <NUM> minutes, more typically from about <NUM> minutes to about <NUM> minutes and in some embodiments may be from about <NUM> minutes to about <NUM> minutes. It should be noted that the higher stress levels and higher temperatures each tend to reduce the duration required to activate and glide the dislocations.

Compression may be applied to the substrate alone or, as in other embodiments, may be applied to the entire heterostructure (i.e., both the substrate and heterolayer). Further, it is preferred that the stress applied by compression be relatively uniform (in direction and/or magnitude) throughout the heterostructure (e.g., both radially and circumferentially). It should be noted that the degree of uniformity of stress may be limited by the apparatus used to compress the substrate and some variation (radial or circumferential variation) may result from uneven distribution of stress. In some embodiments, at least about <NUM> MPa of stress is applied along the entire circumference of the substrate or, as in other embodiments, at least about <NUM> MPa of stress is applied along the entire circumference of the substrate.

Upon application of sufficient stress, dislocations continually form at the dislocation source layer and glide toward the substrate-surface layer interface. At a given point of time during application of stress, the dislocations may generally be uniformly distributed throughout the thickness of the substrate. Upon reaching the substrate-surface layer interface, the dislocations form misfit interfacial dislocations at the interface. The misfit dislocations increase in density at the interface during compression of the substrate and continue to relax the strain between the surface layer and the substrate. The strain is eventually balanced upon a build-up of sufficient density of misfits.

The dislocations that are generated from the dislocation source layer and which glide toward the substrate-surface layer interface may be substantially parallel to the back and front surfaces of the heterostructure (i.e., are arranged laterally). It is believed that a relatively small amount or even no threading dislocations are generated from the dislocation source layer.

It is preferred that compression of the substrate cease at or near the point at which the strain is balanced as further generation and gliding of dislocations may cause dislocations to penetrate the surface layer. Once compression of the substrate is stopped, the dislocations in transit in the substrate cease to glide to the interface and no further dislocations are generated (i.e., dislocations become frozen-in).

The number of dislocations that may be present in the substrate at any given point of application of stress and heat may be at least about <NUM>×<NUM><NUM> dislocations/cm<NUM> or even at least about <NUM>×<NUM><NUM> dislocations/cm<NUM> (e.g., from about <NUM>×<NUM><NUM> dislocations/cm<NUM> to about <NUM>×<NUM><NUM> dislocations/cm<NUM> or from about <NUM>×<NUM><NUM> dislocations/cm<NUM> to about <NUM>×<NUM><NUM> dislocations/cm<NUM>). The number density of the dislocations may be determined using any dislocation loop detection method including, for example, sampling the substrate and subjecting the sample to a delineating etchant prior to viewing and counting the dislocation loops through a microscope.

In some embodiments, the stress applied to the substrate by compression of the substrate is reduced to a value less than a threshold value at which dislocations are generated from the dislocation source layer but at a sufficient magnitude to allow the existing dislocations to glide further upwards toward the interface. In this manner, a heterostructure having a substrate substantially free of dislocations may be produced. In such embodiments, an initial stress S<NUM> may be applied to the substrate by compression of the substrate to generate and glide dislocations from the source layer to the substrate-surface layer interface. The applied stress is then lowered to S<NUM> (i.e., S<NUM> is less than Si). The stress S<NUM> is a stress less than a threshold value at which dislocations are generated from the dislocation source layer and which allows the existing dislocations to glide further upwards toward the interface to produce a substrate substantially free of dislocations. S<NUM> may be at least about <NUM> MPa, at least about <NUM> MPa or at least about <NUM> MPa (e.g., from about <NUM> MPa to about <NUM> MPa or from about <NUM> MPa to about <NUM> MPa). S<NUM> may be less than about <NUM> MPa, less than about <NUM> MPa or even less than about <NUM> MPa. Typically, even at stresses on the order of about <NUM> MPa, the dislocations will glide at a velocity of about <NUM> micron per second at a temperature of about <NUM> or about <NUM> microns per second at a temperature of about <NUM>.

The magnitude of stress, the time of application of stress and/or the temperature at which stress is applied to the substrate may be varied depending on the difference between the lattice constant, as, of the substrate and the lattice constant, aSL, of the semiconductor material of the surface layer. Depending on the substrate material chosen and the semiconductor material deposited thereon, aSL and as may vary. In general, compression is effective to relax the heterolayer when aSL is less than as, i.e., when the ratio aSL/aS is less than <NUM>. The ratio aSL/as may be from about <NUM> to about <NUM> or, as in other embodiments, from about <NUM> to about <NUM>, from about <NUM> to about <NUM>, from about <NUM> to about <NUM>, from about <NUM> to about <NUM> or from about <NUM> to about <NUM>.

By gliding the dislocations to the interface, the surface layer may be at least about <NUM>% relaxed, at least about <NUM>% relaxed, at least about <NUM>% relaxed or even completely relaxed, i.e., <NUM>% relaxed. The surface layer may be substantially free of threading dislocations or may have a concentration of threading dislocations of less than about <NUM><NUM> threading dislocations/cm<NUM>.

In embodiments in which the surface layer is not continuous but includes discontinuous segments (i.e., islands) disposed on the surface of the substrate, the discontinuous segments become relaxed by generating and gliding dislocations from the dislocation source layer to the interface with the islands to create misfit interfacial dislocations between each island and the substrate. Dislocations which reach the surface of the substrate between islands dissipate at the surface which allows the area between islands to be substantially free of dislocations upon completion of compression. After relaxation of the islands, semiconductor material may be further deposited to produce a surface layer that continuously extends over the entire diameter of the substrate. In such embodiments, the dislocations below the islands propagate laterally at the interface between the newly deposited material and the substrate thereby relaxing the newly deposited material and the continuous surface layer as a whole.

The relaxed heterostructure fabricated by any of the methods described above may be used to fabricate silicon-on-insulator structures for integrated circuits using wafer bonding and layer transfer methods, or to subsequently fabricate strained silicon-on-insulator structures.

Additional layers may be deposited on the relaxed surface layer thereby forming heteroepitaxial structures having a strained layer on top of the relaxed layer on top of a substrate. Such a structure may also be used to transfer both the relaxed layer and strained layer to another substrate, thereby forming a heteroepitaxial structure having a buried strained layer or alternatively a buried strained layer on insulator. That is, the heteroepitaxial structure may have a relaxed layer of semiconductor material on top of a strained layer of semiconductor material on top of either a substrate or an insulating layer on a substrate.

In addition, the structures fabricated by the methods of the present disclosure may be used to fabricate semiconductor devices such as field effect transistor (FET) or modulation-doped field effect transistor (MODFET) layer structures.

In this regard, the processes described herein relating to compression of the substrate may be performed with use of any of the apparatus described below.

Referring now to <FIG>, compression of the substrate may be achieved by use of a substrate holder that includes chambers and/or fluid passageways for applying a differential pressure across the substrate. These apparatus are not forming part of the claimed invention.

Referring now to <FIG>, compression of the structure <NUM> is achieved by use of structure holder <NUM>. The structure holder <NUM> includes a top plate <NUM>. As shown in <FIG>, the top plate <NUM> is a ring. The top plate <NUM> may have other shapes and may extend entirely across the substrate <NUM> without limitation. The top plate <NUM> is adapted to contact the front surface of the structure <NUM> at the circumferential edge <NUM> of the structure.

The structure holder <NUM> includes a back plate <NUM> for contacting the back surface of the structure <NUM> adjacent the circumferential edge <NUM>. The back plate <NUM> includes a peripheral ring <NUM> that extends upward toward the top plate <NUM>. However in other embodiments, the peripheral ring <NUM> may be part of the top plate <NUM> or may be separate from both the top plate <NUM> and back plate <NUM>. The back plate <NUM>, top plate <NUM> and peripheral ring <NUM> are both adapted to form a peripheral chamber <NUM> between the top plate <NUM>, back plate <NUM> (including the peripheral ring) and circumferential edge <NUM> of the structure <NUM>. Generally, the back plate <NUM> and top plate <NUM> form a seal with the structure <NUM> which allows the pressure in the peripheral chamber <NUM> to be increased relative to the pressure exterior to the holder <NUM> as described below. The peripheral chamber <NUM> may be formed by positioning the semiconductor structure <NUM> on the back plate <NUM> and lowering the top plate <NUM> onto the back plate <NUM> until a seal is formed between the top plate <NUM>, back plate <NUM> and circumferential edge <NUM> of the structure <NUM>.

The holder <NUM> includes a vent <NUM> in the back plate <NUM> for adjusting the pressure in the peripheral chamber <NUM>. Alternatively, the vent may extend through the front plate <NUM> and/or peripheral ring <NUM>. The vent <NUM> may be in fluid communication with a pump (not shown) for increasing the pressure in the peripheral chamber <NUM>.

Referring now to <FIG>, the holder <NUM> may be part of an apparatus <NUM> for compressing a structure <NUM>. The apparatus <NUM> may also include a housing <NUM> which defines a main chamber <NUM> in which the holder <NUM> is mounted. The apparatus <NUM> may include a vent <NUM> that is in fluid communication with a pump (not shown) for regulating the pressure P<NUM> in the main chamber. The vent <NUM> within the structure holder <NUM> extends through the housing <NUM>. In this manner, a pressure P<NUM> may be maintained in the main chamber <NUM> and a different pressure, P<NUM>, may be maintained in the peripheral chamber <NUM> of the structure holder <NUM>. By maintaining the pressure P<NUM> in the main chamber <NUM> less than the pressure P<NUM> in the peripheral chamber <NUM>, the structure <NUM> may be compressed (i.e., the relaxed radius of the substrate may be reduced).

In this regard, the arrows associated with pressures P<NUM> and/or P<NUM> in <FIG> are provided for exemplification purposes and should not be considered to limit the apparatus to a particular pressure profile (i.e., use of a vacuum or pressure in the peripheral chamber or main chamber).

During compression of the structure <NUM>, P<NUM> may be at least about <NUM> MPa less than P<NUM> or, as in other embodiments, at least about <NUM> MPa, at least about <NUM> MPa or at least about <NUM> MPa less than P<NUM> (e.g., from about <NUM> MPa to about <NUM> MPa, from about <NUM> MPa to about <NUM> MPa or from about <NUM> MPa to about <NUM> MPa). In some embodiments, P<NUM> is ambient pressure. In such embodiments, the main chamber <NUM> and housing <NUM> may be eliminated and the housing may be exposed to the ambient environment (i.e., atmospheric pressure).

A heating element <NUM> may be used to heat the structure <NUM> during compression to activate the dislocation source layer. As described above, the structure may be heated to a temperature of from about <NUM> to about <NUM> or from about <NUM> to about <NUM>.

Another embodiment of the structure holder <NUM> is shown in <FIG>. It should be noted that the holder components shown in <FIG> that are analogous to those of <FIG> are designated by the corresponding reference number of <FIG> plus "<NUM>" (e.g., part <NUM> becomes part <NUM>). As shown in <FIG>, the top plate <NUM> includes a projection <NUM> for contacting the front surface <NUM> of the structure <NUM>. The projection <NUM> may form a seal with the structure <NUM> to allow the pressure in the peripheral chamber <NUM> to be increased.

In some embodiments and as shown in <FIG>, the structure <NUM> has a coating <NUM> (<FIG>) or coating <NUM> (<FIG>) on at least a portion of the structure surfaces. As shown in <FIG>, the coating <NUM> extends over the circumferential edge <NUM> of the structure <NUM> and a portion of the front surface <NUM> and back surface <NUM> near the peripheral edge <NUM>. As shown in <FIG>, the coating <NUM> also extends over the entire back surface <NUM> of the structure. Alternatively or in addition, a coating may extend over one or more surfaces of the structure holder. The coating <NUM> or coating <NUM> (or coatings which may extend over the structure holder) may be composed of a low-friction material such as graphite, hexagonal boron nitride, MS<NUM>, WS<NUM>, SiCN, AlCr(V)N, TiAl(Y)N, CaF<NUM>, BaF<NUM>, SrF<NUM> or BaCrO<NUM>. In some embodiments, the structure <NUM> has a coating on the front surface of the structure that reduces or even prevents evaporation of volatile film components of the structure. Suitable coatings for reducing evaporation include amorphous silicon.

Another embodiment of the structure holder <NUM> is shown in <FIG>. It should be noted that the holder components shown in <FIG> that are analogous to those of <FIG> are designated by the corresponding reference number of <FIG> plus "<NUM>" (e.g., part <NUM> becomes part <NUM>). The top plate <NUM> of the structure holder <NUM> includes a recess adapted for forming a central chamber <NUM> between the top plate <NUM> and the front surface <NUM> of the structure <NUM> during use of the structure holder <NUM>. The central chamber <NUM> is formed by lowering the top plate <NUM> onto the semiconductor structure <NUM>. The recess is defined by an annular wall <NUM>. The recess has a radius that is less than the strained radius of the structure. As used herein, "strained radius" refers to the radius of the structure prior to radial compression (deformation) of the structure <NUM> by use of the structure holder <NUM>.

The top plate <NUM> includes a vent <NUM> that is in fluid communication with a pump (not shown) to maintain a pressure P<NUM> in the central chamber <NUM>. In this manner a differential pressure may be maintained between the central chamber <NUM> and peripheral chamber <NUM> to cause the structure <NUM> to be radially compressed. By maintaining the pressure P<NUM> in the central chamber <NUM> less than the pressure P<NUM> in the peripheral chamber <NUM>, the structure <NUM> may be compressed. Pressures P<NUM> and/or P<NUM> may be within the ranges described above.

In some embodiments, the structure <NUM> is radially compressed until the radius of the compressed structure is substantially the same (or slightly less) as the radius of the recess in the top plate <NUM>. Upon compressing the structure <NUM> to the radius of the recess, the central chamber <NUM> and peripheral chamber <NUM> may come into fluid communication which allows the pressure between the chambers to equilibrate, thereby limiting compression of the structure <NUM>. As such, the holder <NUM> is self-limiting as the recess of the top plate <NUM> limits the radial compression of the structure <NUM>.

A structure holder for radially compressing a structure may be adapted to compress a plurality of structures concurrently as shown in <FIG>. The holder components shown in <FIG> that are analogous to those of <FIG> are designated by the corresponding reference number of <FIG> plus "<NUM>". The holder <NUM> includes a back plate <NUM> that is adapted to contact the structures 9a, 9b, 9c, 9d adjacent circumferential edges of the structures. The holder <NUM> includes a top plate <NUM> that contacts the structures 9a, 9b, 9c, 9d adjacent circumferential edges of the structures. A peripheral chamber <NUM> is formed between the back plate <NUM>, top plate <NUM> and circumferential edges of the structures 9a, 9b, 9c, 9d. The top plate <NUM> contains chambers <NUM> that extend to the front surface of the structures 9a, 9b, 9c, 9d to allow the structures to be exposed to the pressure P<NUM> in the main chamber (not shown). The peripheral chamber <NUM> is maintained at pressure P<NUM>.

By maintaining P<NUM> less than P<NUM>, the structures 9a, 9b, 9c, 9d may be radially compressed. The difference between P<NUM> and P<NUM> may be at least about <NUM> MPa and within any of the ranges described above. P<NUM> may be atmospheric pressure and, in such embodiments, the top plate <NUM> may be a continuous part that does not contain separate chambers <NUM>. While the substrate holder shown in <FIG> is described and shown as having only one back plate and one top plate, it should be understood that the holder may have a plurality of separate back or top plates that seal individual structures or groups of structures. Further, while the substrate holder <NUM> shown in <FIG> is capable of radially compressing four structures, it should be noted that the holder may be arranged such that more or less structures may be concurrently compressed without limitation.

In addition to the apparatus described above, an apparatus that grips the structure (such as at the peripheral edge by use of clamps or other gripping elements) and allows the structure to be compressed may be used to relax the heterostructure such as in apparatus described below. Referring now to <FIG>, compression of the structure may be achieved by use of a structure holder that is radially movable relative to the structure. In such embodiments, the structure holder may be part of an apparatus for compressing the structure. Such apparatus may be similar to the apparatus <NUM> shown in <FIG> in that the apparatus includes a housing <NUM> which defines a main chamber <NUM> in which the holder <NUM> is mounted. The apparatus may include a heating element <NUM> to heat the structure <NUM> during compression by use of any of structures of <FIG> to activate the dislocation source layer.

Referring now to <FIG>, the structure holder <NUM> may include a plurality of triangular-shaped segments <NUM> that point inward to a central axis A of the holder. Each segment has at least one fluid passageway <NUM> formed therein to pull a vacuum on the substrate. The segments <NUM> may be mounted for movement inward toward the central axis A causing the substrate to compress. This apparatus is not forming part of the claimed invention.

Referring now to <FIG>, the apparatus <NUM> may be a clamp that includes a front plate <NUM> and a back plate <NUM> that exerts a holding force on the substrate <NUM>. As shown in <FIG>, the top plate <NUM> and back plate <NUM> are rings. The top plate <NUM> may have other shapes and may extend entirely across the substrate <NUM> without limitation. The front plate <NUM> and back plate <NUM> may be movable radially inward from the center of the apparatus by any mechanical methods including use of pneumatics, hydraulics, motors and the like. This apparatus is not forming part of the claimed invention.

Referring now to <FIG>, in an embodiment of the claimed invention, the structure holder <NUM> includes a generally planar back plate <NUM> that includes an annular boss <NUM> that is sized and shaped to be received in a groove <NUM> in the back of the structure <NUM>. The boss <NUM> is movable such that it compresses the structure <NUM>.

In some embodiments and as shown in <FIG>, the structure holder <NUM> also includes a front plate <NUM> having an annular ring <NUM> that extends from the front plate. The ring <NUM> exerts a downward force on the structure <NUM> to prevent the structure from dislodging from the boss <NUM> during compression of the structure during heating. Other structures for accomplishing this function are contemplated within the scope of this disclosure.

In other embodiments and as shown in <FIG>, the structure holder <NUM> includes a back plate <NUM> and boss <NUM> similar or identical to that shown in <FIG> and <FIG>. The substrate holder <NUM> also includes a front plate <NUM> and a front boss <NUM> that is sized and shaped to be received in a groove <NUM> in the front surface of the structure <NUM>.

Referring to <FIG>, the structure holder <NUM> of this embodiment includes a planar back plate <NUM> for supporting the structure <NUM> and a generally circular press <NUM> with a circular opening for receiving and compressing the structure. The planar plate may extend only partially toward the center of the structure as in <FIG> or may extend continuously beneath the structure <NUM>. The press <NUM> may continuously encircle the structure or, as shown in <FIG>, may include a plurality of arc-shaped segments <NUM> that form the opening for receiving the structure <NUM>. The press <NUM> and/or segments <NUM> may be movable inward relative to the structure <NUM> to compress the structure. This apparatus is not forming part of the claimed invention.

Referring to <FIG>, a structure holder <NUM> includes a generally planar back plate <NUM> and a flange <NUM>. The structure <NUM> includes a ring <NUM> attached to the back surface of the structure near the peripheral edge of the structure. The flange <NUM> is adapted to engage the ring <NUM>. The support <NUM> and flange <NUM> are movable relative to the structure to compress the structure. This apparatus is not forming part of the claimed invention.

In some embodiments, the stress applied by the apparatus described above is cycled such as by reducing the differential pressure across the structure (e.g., by decreasing or increasing pressure in the peripheral or main chambers) or by reducing the stress applied in apparatus that grip the substrate. Such cycling may release any elastic stress formed in the structure.

As used herein, the terms "about," "substantially," "essentially" and "approximately" when used in conjunction with ranges of dimensions, concentrations, temperatures or other physical or chemical properties or characteristics is meant to cover variations that may exist in the upper and/or lower limits of the ranges of the properties or characteristics, including, for example, variations resulting from rounding, measurement methodology or other statistical variation.

Claim 1:
An apparatus in combination with a structure (<NUM>), the apparatus P being configured for relaxing the strain in said structure (<NUM>), the structure having a central axis, a front surface and a back surface which are perpendicular to the central axis, a peripheral edge extending from the front surface to the back surface, and a groove in the back surface adjacent the peripheral edge, the structure (<NUM>) being a heterostructure comprising a substrate, a surface layer disposed on the substrate, an interface between the substrate and the surface layer, and a dislocation source layer in the substrate, the apparatus comprising:
a structure holder (<NUM>) including:
a planar back plate (<NUM>) having an annular boss (<NUM>) sized and shaped to be received in the groove (<NUM>) in the back surface of the structure, the boss being movable to compress the structure (<NUM>),
wherein the apparatus is configured to activate the dislocation source layer to form dislocations and glide dislocations from the dislocation source layer towards the interface between the substrate and the surface layer, and is configured to grip the structure (<NUM>) to allow the structure (<NUM>) to be compressed and to relax the structure.