Patent Description:
Power electronics modules comprising a plurality of power electronic devices are used in many different application areas. In particular, in the area of power electronics, a plurality of power semiconductor chips may be connected in parallel to form a power electronics module with a relatively high current rating.

<CIT> relates to a power semiconductor device module having a number of sub-modules with at least one semiconducting chip attached to the top of an electrically insulating, and a heat conducting substrate with a thermal expansion coefficient matching that of the chip. Each submodule has a substrate with a cooler made from a good thermal conductor. The cooler is embedded in the underside of the substrate. A solder layer is used for attaching the at least one semiconductor chip to a metallization of the substrate.

<CIT> relates to packaging of electronic components and is concerned with implementation of Ag sintering, and in particular with the challenge that softer parts in an assembly like emitter contacts may be difficult to sinter as they bend along the underlying topology of the substrate and the chip.

<CIT> is concerned with the electrical relocation of device top pads to the bottom of a device, in particular for the fabrication of arrays of devices, such as imaging (viewing) or display devices.

<CIT> discloses that an electronic device package includes a semiconductor chip having a contact pad on a main face of the semiconductor chip, a contact element disposed on the contact pad, a dielectric layer disposed on the semiconductor chip and the contact element, and an encapsulant disposed onto the dielectric layer.

<CIT> relates to a method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.

With increasing demands for power density, it is desirable to increase the current rating of such power electronics modules. Increasing the power density can be achieved, for example, by the development and introduction of new chip technologies providing a reduction of conduction and switching losses of the individual semiconductor power devices during operation. However, the development of new chip technologies and their largescale manufacturing is very time consuming and costly, and therefore provides more of a long-term perspective. Accordingly, other means of increasing a current rating of a power electronics module are desirable.

Embodiments of the disclosure relate to power electronics modules and methods for their manufacturing enabling an increased current rating of a power electronics module with a given size or, a smaller size of a power electronics module with a given current rating. This disclosure shows an alternative method with low effort to enhance or optimize the current capability.

The invention is defined by the attached set of claims. Further details of the disclosed methods, devices and system are provided in the following, which are helpful for understanding the claimed invention.

According to one aspect, a power electronics module comprises a substrate with at least a first metallization area, a first group of power electronic devices arranged in the first metallization area, and a common, uninterrupted joining layer arranged between the first metallization area and the first group of power electronic devices. The first group comprising a plurality of power electronic devices, and the common, uninterrupted joining layer establishes a mechanical and an electrical contact between the first metallization area and the first group of power electronic devices.

Among others, the inventors have found that, by omitting or reducing a distance between power electronic devices and joining a plurality of power electronic devices using a common, uninterrupted joining layer to a single metallization area, a total active area of the power electronic devices arranged on a power electronics module of a given size can be increased, thereby also increasing a current rating of the power electronic devices. While the space on a substrate available for positioning of power electronic devices, such as semiconductor chips, is limited, it can be better utilized by joining multiple power electronic devices using a common, uninterrupted joining layer. This is in contrast to the joining of each power electronic device separately using a separate joining layer, where space is lost due to spaces between individual power electronic devices.

In the claimed power electronics module, each one of the power electronic devices of the first group is arranged directly adjacent to at least one other power electronic device of the first group. In other words, the power electronic devices of the first group are arranged essentially without any gap, or at least a strongly reduced gap, between them, thus maximizing the use of available mounting space. By removing unused space between power electronic devices, the size of the power electronic devices, and consequently the active area can be increased. In particular, when power electronic devices, such as semiconductor chips, can be arranged very close to each other without significant empty space between them, an optimal use of the available surface area of the substrate can be obtained.

In the claimed power electronics module, the power electronic devices are self-aligned and the distance between adjacent power electronic devices of the first group is smaller than <NUM>, for example smaller than <NUM>. Such distances cannot be obtained using conventional mounting techniques, when power electronic devices are aligned and mounted using separate joining layers.

According to at least one implementation, the first metallization area comprises a subarea covering a part of the first metallization area and/or the substrate, and the common, uninterrupted joining layer covers essentially the entire subarea.

The area covered by the common, uninterrupted joining layer may exclude any space required for alignment of the group of power electronic devices. The subarea may represent a substantial part of the first metallization area or the substrate, such as the entire area available for placement of power electronic devices. For example, it may represent more than <NUM>, <NUM> or <NUM> percent of the main surface area of the first metallization area or the substrate. The subarea may be a rectangular area or an area with any other geometry defined by the power electronic devices to be placed on the power module. For example, the subarea may be a largest rectangular part of the first metallization area. The subarea may exclude one or more smaller parts of the first metallization area configured for interconnecting the power electronic devices and/or for further components of the power electronics modules.

According to different implementations, the power electronic devices of the first group may be joined to the first metallization area using different joining techniques, including soldering or diffusion soldering.

In the claimed power electronics module, the power electronic devices are soldered to the substrate, and a solder layer acts as the common, uninterrupted joining layer. Moreover, due to the physical properties of a soldering process, a distance between neighboring power electronic devices of the first group is defined by a solder meniscus. This effectively enables a self-alignment of the power electronic devices.

According to at least one implementation, the power electronic devices of the first group comprise semiconductor chips, such as MOSFETs, MISFETs, JFETs, IGBTs, or diodes.

According to at least one implementation, each one of the semiconductor chips may comprise at least two terminals, and the terminals of each one of the semiconductor chips may be connected electrically in parallel. Combining multiple semiconductor chips in parallel enables a high current rating.

According to different implementations, the power electronic devices of the first group may be of the same type, or may be of two or more different types. For example, a combination of one or more protective or free-wheeling diodes and one or more transistor or switching devices may be arranged on the first metallization area to form a hybrid power electronics module.

According to another aspect, a method for manufacturing a power electronics module according to claim <NUM> is provided.

Depending on the used joining technique, e.g. soldering, diffusion soldering, different processing steps may be performed to process and join the plurality of power electronic devices of the first group together, thereby lowering manufacturing cost and improving yield.

The present disclosure comprises several aspects of a power electronics module and methods for its manufacturing. Every feature described with respect to one of the aspects is also disclosed herein with respect to the other aspects, even if the respective feature is not explicitly mentioned in the context of the specific aspect.

The accompanying figures are included to provide a further understanding. In the figures, elements of the same structure and/or functionality may be referenced by the same reference signs. It is to be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

While the disclosure is amenable to various modifications and alternative forms, specifics thereof are shown by way of example in the figures and will be described in detail below. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended set of claims.

<FIG> shows, in a schematic manner, a cross-section through a power electronics module <NUM>. The power electronics module <NUM> comprises a substrate <NUM> with a first metallization area <NUM> on one of its main surfaces. For example, the substrate <NUM> may be a ceramic substrate with a metallization layer formed on one side. A common, uninterrupted joining layer <NUM> is formed on a surface of the first metallization area opposite the substrate <NUM>. As detailed later, the joining layer <NUM> is a solder layer or a layer prepared by diffusion soldering. On top of the joining layer <NUM>, a group comprising two power electronic devices <NUM> is arranged. The group of power electronic devices <NUM> may comprise at least one semiconductor power diode and/or at least one semiconductor power transistors. The joining layer <NUM> is uninterrupted in the sense that it does not comprise any intentional gaps and/or provides a direct electrical path between the power electronic devices <NUM> of the same group, irrespective of an electrical path provided by the first metallization area <NUM>.

Attention is drawn to the fact that a remaining gap G between the two power electronic devices <NUM> is very small. That is to say, the power electronic devices <NUM> are arranged more or less directly adjacent to one another in the first metallization area <NUM>. In terms of absolute distance, this may mean that the remaining gap G between the two power electronic devices <NUM> is smaller than <NUM>, for example <NUM> or less. In terms of relative distance, this may mean that the remaining gap G between the two power electronic devices <NUM> is smaller than <NUM>% or <NUM> of the width and/or length of the adjacent power electronic devices <NUM>.

Such distances between adjacent power electronic devices <NUM> cannot be achieved using conventional manufacturing methods, wherein each power electronic device <NUM> is joined to a metallization area using a separate joining layer <NUM> as detailed later. Inversely, this means that the joining layer <NUM> is substantially continuous, and preferably has no gap in an area located between two adjacent power electronic devices <NUM>. Put differently, the joining layer <NUM> is formed from a common body of joining material. For example, a single piece of material, such as a single solder preform, may be used. Alternatively, a paste-like joining material, such as solder paste, may be applied by dispensing or printing it in a continuous or patterned shape, such as a cross, snowflake, or multiple dots. A continuous joining layer <NUM> is formed by putting the power electronic devices <NUM> on the previously dispensed joining material.

<FIG> shows a top view of a power electronics module <NUM> with a total of five power electronic devices 14a to 14e, for three IGBTs (or other type of transistors) and two diodes. A first part <NUM>, in <FIG> the lower part, covers a substantial part of the substrate <NUM>, e.g. more than <NUM> percent of the total surface of the substrate <NUM>, and comprises an essentially rectangular subarea <NUM>, indicated using a dashed line, of a first metallization area <NUM>.

In the depicted embodiment, the subarea <NUM> represents the largest rectangular subarea of the first metallization area <NUM>. A large proportion of the subarea <NUM>, e.g. more than <NUM> percent, is covered by the five power electronic devices 14a to 14e. Only a remaining outer area of the subarea <NUM> near the outer edges of the five power electronic devices 14a to 14e is left uncovered. A smaller, second part <NUM> of the substrate <NUM>, in <FIG> the upper part, may comprise further parts of the first metallization area and further metallization areas. For example, metal traces used for connecting contact surfaces on the back side of the power electronic devices 14a to 14e and/or for connecting the power electronics modules <NUM> to other components or for joining of other electronic devices like sensor devices, passive device, control devices may be provided. The proportion of the subarea <NUM> can be at least <NUM> to <NUM> percent in some other variants of the power electronics module, e.g. when the shape of the subarea is other than the rectangular geometrical shape or when the current rating requirement is lower.

In other embodiments, further metallization areas and/or subareas may be provided. For example, in a half-bridge used for an inverter module, two different metallization areas may be provided for placement of one or more high-side group and one or more low-side group of power electronic devices, respectively (not shown). For multi-phase inverters, further metallization areas and corresponding groups of power electronic devices may be provided. In such configurations, one or more respective subareas for placement of power electronic devices may only cover a smaller part of the substrate's surface, but may still represent the largest continuous geometrical shape, such as a rectangle, of the respective metallization.

In the embodiment shown in <FIG>, the individual power electronic devices 14a to 14e touch each other or are separated only by a very narrow gap caused by the respective joining technique, as detailed below. In the embodiment shown in <FIG>, the width of remaining gap G between the individual power electronic devices <NUM> is smaller than a width of a remaining outer edge E between the outside circumference of the first group of power electronic devices <NUM> and the respective outer circumference of the subarea <NUM>.

<FIG> show how such a power electronics module may be formed by soldering. At first, a modified solder fixture <NUM> is explained with reference to <FIG>, before individual phases of a related manufacturing process are explained with reference to <FIG>.

<FIG> show a perspective and a plane view of a first part 18a of the solder fixture <NUM>, respectively. As can be best seen in <FIG>, the first part 18a of the solder fixture <NUM> comprises a number of depressions for holding the components of power electronics module <NUM>. In particular, a larger, relatively shallow first recess <NUM> corresponds to the outer circumference of the substrate <NUM> and/or the metallization areas formed thereon, and serves to hold the substrate <NUM> during soldering.

A smaller, slightly deeper, second recess <NUM> is formed within the first recess <NUM>, and is configured to hold a plurality of power electronic devices <NUM>. In the described example, the second recess <NUM> is configured to hold the five power electronic devices 14a to 14e previously shown in <FIG> and a common solder preform, as explained later. While only a single second recess <NUM> configured for holding a single group of power electronic devices <NUM> is shown in <FIG>, fixtures <NUM> comprising several second recesses <NUM> for multiple groups arranged on the same or different metallization areas <NUM> are also envisioned.

The first part 18a of the solder fixture <NUM> comprises a number of further depressions, openings and other structural features that facilitate insertion and removal of the various components into and out of the solder fixture <NUM>, and for accommodating weights for pushing down any power electronic devices <NUM> placed therein. For the sake of brevity, these are not described in detail here.

In the top view of <FIG>, a rectangular area <NUM> formed by the second recess <NUM> is highlighted using a dashed line. Attention is drawn to the fact that the edges of the second recess <NUM> corresponding to the rectangular area <NUM> serve to align all of the power electronic devices <NUM> and the common solder preform together. In contrast, no internal dividing or alignment features are provided between the positions of the individual power electronic devices 14a to 14e. Avoidance of such internal protrusions increases the space available for placement of the power electronic devices <NUM>. Further attention is drawn to the fact that the rectangular area <NUM> formed within the second recess <NUM> essentially corresponds to or is only smaller by a relatively small fraction, e.g. a distance corresponding to a solder meniscus and/or needed for alignment, than the subarea <NUM> of the first metallization area <NUM>.

<FIG> shows, in a schematic manner, a first stage in the manufacturing of a power electronics module <NUM>. At this stage, multiple power electronic devices <NUM> have been placed in a common recess <NUM>, from which only two are visible in the cross-section of <FIG>. Below each one of the power electronic devices <NUM>, a corresponding weight <NUM> is arranged, which may be a loose part or may be attached to the first part 18a of the solder fixture <NUM> in a movable manner.

In the described embodiment, above the two power electronic devices <NUM>, a single, continuous solder preform <NUM> is placed. Due to its larger size and the fact that only a single solder preform <NUM> needs to be placed in the solder fixture <NUM>, handling of the preform <NUM> and thus the entire manufacturing process may be simplified. The solder preform <NUM> covers corresponding contact surfaces of the two power electronic devices <NUM> and essentially extends over the entire widths of the second recess <NUM>. Accordingly, the same solder preform may be used, irrespective of the individual size of the used power electronic devices <NUM>. For example, the same solder preform <NUM> may be used to attach two full-size or four half-size chips to the same metallization area <NUM>. Attention is drawn once again to the fact that no separating protrusion is present between the two power electronic devices <NUM>.

<FIG> shows a further stage in the manufacturing process. At this stage, a double-sided substrate <NUM> comprising a first metallization area <NUM> on the first side and a second metallization area <NUM> arranged on the opposite, second side of the substrate <NUM> is placed in the first part 18a of the solder fixture <NUM>. For example, in a power module, the first side may correspond to a backside, and the second side may correspond to a front side of the substrate <NUM>. In the depicted embodiment, the first metallization area <NUM> is placed in the first recess <NUM> surrounding the second recess <NUM> such that a subarea of the first metallization area <NUM>, for example the subarea <NUM> shown in <FIG>, is aligned with the power electronic devices <NUM>.

At a next stage, shown in <FIG>, a second part 18b of the solder fixture <NUM> (fixture bottom plate) is placed on top of the substrate <NUM>, i.e. the second metallization area <NUM>, to close the solder fixture <NUM>.

Thereafter, as shown in <FIG>, the closed solder fixture <NUM> comprising the first part 18a and the second part 18b is flipping, such that the weights <NUM> press the respective power electronic devices <NUM> against the first metallization area <NUM>. At this stage, the solder preform <NUM> is heated or otherwise liquefied, resulting in a layer of liquid solder material <NUM>.

Optionally, a process gas or liquid, such as hydrogen, or formic acid may be applied during soldering, to support or enable a chemical reduction of the solder material. For example, hydrogen or formic acid may be used for reduction of the solder material of the solder preform <NUM>. Alternatively, or additionally, an inert gas like nitrogen may be applied during at least phases of the joining process.

Once the soldering process is complete, the solidified solder material <NUM> forms a common, uninterrupted solder layer <NUM> as shown in <FIG>. The thickness of the solder layer <NUM> may vary to a small extend in areas below the power electronic devices <NUM> and neighbouring areas, e.g. by a limited overflow of the soldering material into the gap G or towards the edge E. Nonetheless, such a solder layer <NUM> may be described as homogenous, as it is formed in a single rather than several successive soldering steps.

Thereafter, the solder fixture <NUM> can be removed, with the individual power electronic devices <NUM> being mechanically and electrically attached to the first metallization area <NUM>. Moreover, the solder layer <NUM> may also serve as a thermal connection between the power electronic devices <NUM> and the substrate <NUM>, e.g. for cooling of the power electronic devices <NUM>. Due to the uninterrupted nature of the common joining layer <NUM> and/or the larger total surface area of the power electronic devices <NUM>, the thermal capabilities of the resulting power electronics module <NUM> may also be improved, for example, by achieving a more uniform heat distribution.

As can be seen in <FIG>, due to the surface tension of the liquid solder material, the individual power electronic devices <NUM> are essentially self-aligned by a solder meniscus <NUM> formed at the periphery of power electronic devices <NUM>, e.g. by merging with the meniscus of an adjacent power electronic device <NUM>, indicated by a recess <NUM> in the solder layer <NUM> in a remaining, internal gap between the power electronic devices <NUM>, and a clear meniscus <NUM> on the outer periphery of the group of power electronic devices <NUM>. In this way, the physical properties of the solder material itself provides an alignment aid, further alleviating the need for internal protrusions within the second depression <NUM> of the solder fixture <NUM>.

While a conventional soldering process has been described, more advanced soldering techniques, such as diffusion soldering may also be used accordingly. In this case, rather than weights <NUM>, a controlled pressure may be applied to the power electronic devices <NUM>, e.g. by corresponding fixtures.

Moreover, in another embodiment, instead of placing a solder preform <NUM> in the common recess <NUM>, solder paste is coated on a surface of the first metallization area <NUM>. For example, a subarea intended for the placement of power electronic devices <NUM> may be covered with a patterned layer of a viscous solder paste by printing or coating or dispensing. The power electronic devices <NUM> of the first group are then mounted, for example, using a pick-and-place process and a subsequent thermal process, such as reflow soldering or another bonding technique, resulting in a common, uninterrupted solder layer <NUM> as described above. In this case, use of a fixture for holding the power electronic devices <NUM> is optional, as the power electronic devices <NUM> may be held in place before and during soldering by the solder paste.

Finally, in case more than one group of power electronic devices <NUM> shall be mounted, each group can be mounted separately, as described below with respect to sintering.

<FIG> show an intermediate stage and resulting power electronics module <NUM> formed by an alternative, more conventional method of attaching two power electronic devices <NUM> to a substrate <NUM> with a first metallization area <NUM>.

As shown in <FIG>, each one of the power electronic devices <NUM> is individually aligned on all sides before and during soldering. To this end, a protrusion <NUM> is present in a first part 18a of a solder fixture <NUM>, separating the power electronic devices <NUM> and individual solder preforms from each other. Accordingly, two separate solder preforms 23a and 23b must be placed in each one of two corresponding recesses 20a and 20b. During the soldering process, the power electronic devices <NUM> as well as the solder materials remain separated by the protrusion <NUM>.

Accordingly, as is shown in <FIG>, two separate solder layers 26a and 26b are formed, which are separated from one another (except for unintentional solder overflows) by a corresponding gap G, which typically exceeds <NUM> in width. The surface area of the substrate <NUM> and corresponding part of the first metallization area <NUM> according to the gap G is lost for the placement of active components, so the chip sizes and consequently the active areas of the chips must be smaller. This leads to a lower current rating of the power electronics module <NUM> compared to the power electronics module <NUM> of <FIG>.

That is to say, when using a common, uninterrupted joining layer <NUM>, larger and/or more numerous chips forming the power electronic devices <NUM> may be placed in common metallization area <NUM> of a given size. This results in a larger total active area of the chips, which in turn results in a higher current capability or power density. Inversely, if the number and size of the individual power electronic devices <NUM> is fixed, a smaller substrate <NUM> with a smaller metallization area <NUM> may be used to obtain the same current capability. This may result in a miniaturization and reduction of cost.

<FIG> show, in a schematic manner, different stages of a manufacturing method for a power electronics module <NUM> based on sintering, which is not covered by the attached set of claims.

At a first stage, shown in <FIG>, a layer of sinter material is provided on a first metallization area <NUM> of a double-sided substrate <NUM>. As an example, sintering preform <NUM> may be placed on the first metallization area <NUM>. Alternatively, a layer of sinter material may be applied, for example by printing, in a corresponding area of the first metallization area <NUM>.

At a next stage, shown in <FIG>, multiple power electronic devices <NUM>, forming a group of power electronic devices to be sintered, are placed on the sintering preform <NUM>. For example, a pick and place procedure may be used to place individual power semiconductor chips on the sinter preform <NUM>.

The substrate <NUM> with the aligned power electronic device <NUM> may be placed in a sinter press. In an optional step, a protective foil <NUM> may be placed on top of the power electronic devices <NUM> to provide mechanical protection and/or protection against contaminations during sintering, e.g. to protect corresponding electrodes or other parts of the upper side of the power electronic devices <NUM>. For example, a first part 32a of a sintering fixture <NUM> may be placed over the protective foil <NUM>, the power electronic devices <NUM>, the sintering preform <NUM> and the double-sided substrate <NUM> as shown in <FIG>. As shown in <FIG>, the first part 32a of a sintering fixture <NUM> comprises a recess <NUM> for laterally holding and/or aligning the power electronic device <NUM> before and during sintering. On the opposite side of the double-sided substrate <NUM>, i.e. below the second metallization area <NUM>, a second part 32b of the sintering press or sintering fixture <NUM> is arranged.

While the term "sintering fixture" is used here and a profiled sintering fixture <NUM> is shown for better understanding, attention is drawn to the fact that, in its simplest form, sintering may be performed between two arbitrary, flat surfaces. That is to say, the recess <NUM> represents an optional feature for the sintering process.

As shown in <FIG>, the two opposite surfaces used for sintering are closed and pressed against each other to sinter the material of the sinter preform <NUM> into an essentially uniform sinter layer <NUM> between the power electronic devices <NUM> and the first metallization area <NUM>.

While sintering based on mechanical pressing has been described above, other known sintering processes based on heat and/or a processing atmospheric may also be used or combined with a mechanical sintering process. For example, sintering may be performed in an atmosphere consisting of an inert gas to avoid unwanted chemical reactions.

As detailed above, the sintering layer <NUM> provides both a mechanical and electrical connection between the adjoining parts, and may also provide a thermal connection.

Once the sintering is complete, as shown in <FIG>, the sintering fixture <NUM> may be removed and further processing steps may take place. For example, as also shown in <FIG>, one or more bond wires <NUM> may be connected to electrical contacts arranged on the opposite, upper surface of the individual power electronic devices <NUM>, for example between different power electronic devices <NUM> as shown in <FIG>, or between a power electronic device <NUM> and a metallization area (not shown). In this way, for example, a relatively large number of power electronic devices <NUM> may be connected electrically in parallel.

In the scenario shown in <FIG> and <FIG>, a single, continuous and homogenous preform is used as solder or sinter material layer, respectively, which covers a large part of the outer surface of the first metallization area <NUM>.

However, in other embodiments (not shown), different groups of power electronic devices <NUM> may be soldered tc a common metallization area <NUM> in successive stages. In this case, a single preform or area covered with joining material, such as a solder paste may only cover a part of the first metallization area <NUM>, which corresponds to a respective first group of power electronic devices <NUM>.

Moreover, especially in the case of sintering (which does not fall within the scope of the attached claims), depending on the joining materials and joining processes, a stack of multiple preforms and/or multiple layers of joining materials may be used.

Moreover, although not shown in the drawings, the above solder or sintering processed may be repeated for the second main surface of the substrate, thereby forming power electronics modules <NUM> carrying power electronic devices <NUM> on the two opposite metallization areas <NUM> and <NUM>.

The embodiments shown in <FIG> <FIG> as stated represent examples of improved power electronics modules <NUM> and methods for their manufacturing. Therefore, they do not constitute a complete list of all embodiments according to the improved devices and methods as defined by the attached set of claims. Actual devices and methods may vary from the embodiments shown in terms of arrangements, devices and processing steps, for example.

Claim 1:
A power electronics module (<NUM>), comprising:
- a substrate (<NUM>) with at least a first metallization area (<NUM>);
- a first group of power electronic devices (<NUM>) arranged in the first metallization area (<NUM>), wherein the first group comprises a plurality of power electronic devices (<NUM>); and
- a common, uninterrupted joining layer (<NUM>) of solder material (<NUM>) arranged between the first metallization area (<NUM>) and the first group of power electronic devices (<NUM>), wherein the common, uninterrupted joining layer (<NUM>) establishes a mechanical and an electrical contact between the first metallization area (<NUM>) and the first group of power electronic devices (<NUM>);
- wherein each one of the power electronic devices (<NUM>) of the first group is arranged directly adjacent to at least one other power electronic device (<NUM>) of the first group;
- wherein the individual power electronic devices (<NUM>) are self-aligned during a soldering process for joining the power electronic devices (<NUM>) to the metallization area (<NUM>) by a solder meniscus (<NUM>) formed at the periphery of each power electronic device (<NUM>), the solder meniscus of adjacent ones of the power electronic devices (<NUM>) merging such that the solder layer (<NUM>) comprises a recess (<NUM>) in an internal gap between adjacent ones of the power electronic devices (<NUM>);
- wherein the first group of power electronic devices comprises a clear meniscus (<NUM>) at its outer periphery; and
- wherein a distance between adjacent power electronic devices (<NUM>) of the first group is smaller than <NUM>.