Patent Description:
"<NPL>, and generally relates to network-based clock synchronization for network arbitration, control, and monitoring on a factory floor.

With respect to the discussion to follow and in particular to the drawings, it is stressed that the particulars shown represent examples for purposes of illustrative discussion, and are presented in the cause of providing a description of principles and conceptual aspects of the present disclosure. In this regard, no attempt is made to show implementation details beyond what is needed for a fundamental understanding of the present disclosure. The discussion to follow, in conjunction with the drawings, makes apparent to those of skill in the art how embodiments in accordance with the present disclosure may be practiced. Similar or same reference numbers may be used to identify or otherwise refer to similar or same elements in the various drawings and supporting descriptions. In the accompanying drawings:.

Described herein are techniques for a timing synchronization system. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of some embodiments. Some embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

A slave device, such as a precision time protocol (PTP) slave device, may include a slave clock that is synchronized with a master clock that is located in a master device, such as a PTP master device. A protocol, such as PTP, may be a timing system that may be used in applications such as in a cable network with a remote PHY (RPHY) device. PTP may be implemented based on Institute of Electrical and Electronics Engineers (IEEE) standards, such as IEEE standard <NUM>-<NUM>. The PTP protocol distributes time and frequency through a network, such as a packet network. Time synchronization is a synchronization of time between the slave device in a network and the master device, and frequency synchronization is the synchronization of frequency of the slave clock with the master clock. The protocol creates a master-slave relationship between a grand master clock and slave devices through the network.

In some embodiments, a slave device may lock its slave clock to an operational master clock of an operational master device. Then, to test the lock quality of the slave clock to its master clock, the slave device may communicate with a probe master device that includes a probe master clock. The probe master device may be placed in the network, such as near the slave device (e.g., in the last network hop to the slave device or the last couple of hops). This may reduce the influence of packet delay variation and asymmetry between the slave device and the probe master device. The slave device may receive a sync message from the probe master device with a timestamp, referred to as a T1 time. The slave device may note the time that the sync message is received as a time T2. The slave device sends a delay request message that includes a time stamp, referred to as a T3 time, of the slave clock. The slave device receives a delay response from the probe device with a time stamp, referred to as a T4 time, of the probe master clock. From the delay request and the delay response, the slave device can then calculate the path delay between the slave device and the probe device. For example, the path delay is ((T2-T1)+(T4-T3))/<NUM>.

The slave device then sends a delay request with the T3 time and the path delay to the probe master device. The slave device may insert the path delay a field of the delay request message, such as in the T3 correction field. The probe master device can properly monitor the clock of the slave device using the T3 time and the calculated path delay that is inserted in the delay request. For example, the probe master device can then use the T3 time and the path delay to verify the lock quality of the slave clock with the operational master clock. That is, the T3 time + path delay = the current time of the slave clock. The probe master device can compare the current time of the slave clock to the current time of the probe master clock. The above allows the monitoring of the slave clock without requiring an interface to a PTP probe, such as a one pulse-per-second (PPS) interface to a PTP probe, or requiring the slave device to operate as a master clock to synchronize with a probe slave clock via PTP. Also, the path delay is inserted in a field that exists in the PTP protocol and PTP probe device is configured to calculate the current time of the slave clock using the correction field.

<FIG> depicts a simplified system <NUM> for performing timing synchronization according to some embodiments. System <NUM> includes a PTP operational master device <NUM>, switches <NUM>-<NUM> to <NUM>-N, a PTP slave device <NUM>, and a PTP probe master device <NUM>. Precision time protocol is used to synchronize timing throughout a network. Although precision time protocol is discussed, it will be understood that other protocols may be used that synchronize timing throughout the network.

PTP operational master device <NUM> may be a device that includes a master clock <NUM>-<NUM>. Master clock <NUM>-<NUM> may be based on a reference clock, such as a global navigation satellite system (GNSS) clock or another source of time. Master clock <NUM>-<NUM> may be an operational master clock that is used by PTP slave device <NUM> to synchronize its slave clock <NUM>.

PTP slave device <NUM> may be located in a network. A path #<NUM><NUM>-<NUM> is between PTP slave device <NUM> and PTP operational master device <NUM>. In some embodiments, PTP slave device <NUM> may be located in the network and is remotely located from PTP operational master device <NUM>. Switches <NUM>-<NUM> to <NUM>-N may be network devices that can couple PTP operational master device <NUM> to PTP slave device <NUM> through path #<NUM><NUM>-<NUM> in the network.

PTP probe master device <NUM> may be used to test the quality of the lock of slave clock <NUM> with operational master clock <NUM>-<NUM>. The quality of the lock is measured by the difference of the adjusted time of slave clock <NUM> to the time of a timing source connected to probe master clock <NUM>-<NUM>, which is connected to the timing source used by operational master clock <NUM>-<NUM>. As will be discussed in more detail below, PTP probe master device <NUM> includes a probe master clock <NUM>-<NUM> that is used to check the lock quality of slave clock <NUM>. In some embodiments, PTP probe master device <NUM> is connected to PTP slave device <NUM> in a location that is closer to PTP slave device <NUM> than a location of PTP operational master device <NUM> to PTP slave device <NUM>. For example, PTP probe master device <NUM> may be connected to PTP slave device <NUM> through one of switches <NUM>-<NUM> to <NUM>-N. In some embodiments, PTP probe master device <NUM> is connected to the last hop switch <NUM>-N to PTP slave device <NUM> in a path #<NUM><NUM>-<NUM>. Although PTP probe master device <NUM> may be depicted as being in the last hop in path #<NUM><NUM>-<NUM> or connected to switch <NUM>-N, PTP probe master device <NUM> may be located in other locations and does not have to be located in path #<NUM><NUM>-<NUM>. However, PTP probe master device <NUM> may be located in a location in which packet delay variation and asymmetry in the request and response process is minimized. For example, by locating PTP probe master device <NUM> in switch <NUM>-N, a single hop between switch <NUM>-N and PTP slave device <NUM> may limit packet delay variation and asymmetry in path #<NUM><NUM>-<NUM> compared to path #<NUM><NUM>-<NUM>, which is through multiple switches <NUM>-<NUM> to <NUM>-N that can cause more packet delay variation and asymmetry.

Before checking the lock quality, PTP slave device <NUM> first locks slave clock <NUM> to operational master clock <NUM>-<NUM>. To synchronize slave clock <NUM> with operational master clock <NUM><NUM>-<NUM>, PTP slave device <NUM> may calculate a roundtrip delay between PTP slave device <NUM> and PTP operational master device <NUM>. For example, PTP slave device <NUM> may receive a sync message from PTP operational master device <NUM> with a T1 time from operational master clock <NUM>-<NUM>, which is a timestamp when the sync message is sent. PTP operational master device <NUM> may determine the time based on a timing source, such as a GNSS clock. PTP slave device <NUM> may note the time that the sync message is received as a time T2. PTP slave device <NUM> sends a delay request message that includes a time stamp, referred to as a T3 time, of slave clock <NUM>. PTP slave device <NUM> receives a delay response from PTP operational master device <NUM> with a time stamp of operational master clock <NUM>-<NUM> when the delay request is received, referred to as a T4 time. From the times, the slave device can then calculate the path delay between PTP operational master device <NUM> and PTP slave device <NUM>. For example, the path delay in path #<NUM><NUM>-<NUM> is ((T2-T1) +(T4-T3))/<NUM>. As can be seen, PTP slave device <NUM> assumes the path delay is symmetrical in both directions. Although this method of determining the path delay is described, other methods may be appreciated.

PTP slave device <NUM> can use the path delay to determine the correct time in which slave clock <NUM> should be set. For example, a time of operational master clock <NUM>-<NUM> plus the path delay is the correct time of operational master clock <NUM>-<NUM>. PTP slave device <NUM> may lock slave clock <NUM> to the correct time of operational master clock <NUM>-<NUM>. For example, PTP operational master device <NUM> may send sync messages with a time, which is used by PTP slave device <NUM> to locka time of slave clock <NUM>. Thus, PTP slave device <NUM> may adjust slave clock <NUM> based on the difference between the time of slave clock <NUM> and the time of operational master clock <NUM>-<NUM>. PTP slave device <NUM> eventually locks slave clock <NUM> to operational master clock <NUM>-<NUM>. The phase of the clock frequency may also be adjusted in the locking process. When locked, the time and phase of slave clock <NUM> is locked to the time and frequency of operational master clock <NUM>-<NUM>.

As discussed above, PTP slave device <NUM> should check the lock quality of slave clock <NUM>. That is, PTP slave device <NUM> may check whether the synchronized timing and frequency of slave clock <NUM> is accurate. To perform the check, PTP slave device <NUM> communicates with PTP probe master device <NUM>.

Conventionally, PTP slave device <NUM> may check the lock quality of slave clock <NUM> using different methods. For example, PTP slave device <NUM> may output slave clock <NUM> to an external probe using a dedicated interface, such as a one pulse-per-second interface. The probe compares the time and phase of slave clock <NUM> to its master clock. This is usually done by having the master clock of the probe connected to the same reference clock as operational master clock <NUM>-<NUM>. Although this method may monitor slave clock <NUM>, PTP slave device <NUM> needs to have an external probe interface, such as a <NUM> PPS interface. Also, PTP slave device <NUM> and PTP probe master device <NUM> needs to be accessed to install the connection, which may be hard when PTP slave device <NUM> is remotely located from a headend or core, such as in a remote physical device or small cell devices.

In a second approach, PTP slave device <NUM> may function as a boundary clock wherePTP slave device <NUM> operates slave clock <NUM> as a master clock that communicates with a PTP probe that includes a slave clock. The PTP probe compares the frequency and phase of its slave clock to the master clock of PTP slave device <NUM>. The PTP probe is connected to the same reference clock as operational master clock <NUM>-<NUM> to check the timing of master clock of PTP slave device <NUM>. However, a problem exists in that PTP slave device <NUM> may not support acting as a boundary clock. That is, PTP slave device <NUM> may not be able to act as a master clock. Additionally, the PTP probe is remotely located from PTP slave device <NUM> and the path may suffer from asymmetry and packet delay variation, which would affect the accuracy of the testing of the master clock of PTP slave device <NUM>. Due to the above factors, it is important to monitor the accuracy of the PTP slave clock compared to its PTP master clock and to be able to identify any of the above issues without using a PPS interface and operating PTP slave device <NUM> as a boundary device.

With conventional techniques, there is no implementation for sending timestamp information to monitor slave clocks in an outgoing delay request messages. Similarly, while IEEE <NUM> describes a method for measuring link propagation delay, nowhere does IEEE <NUM> address measuring delay on a path level with intermediate nodes in the path, whereas IEEE <NUM> is limited to measuring delay of a link connecting adjacent nodes.

To overcome the above disadvantages, some embodiments use PTP probe master device <NUM> to test the lock quality of slave clock <NUM>. PTP slave device <NUM> does not attempt to lock slave clock <NUM> to probe master clock <NUM>-<NUM>. Rather, PTP probe master device <NUM> monitors the lock quality of slave clock <NUM> to operational master clock <NUM>-<NUM>. PTP slave device <NUM> can communicate with PTP probe master device <NUM> to calculate the path delay based on T1 time, T2 time, T3 time, and the T4 time. For example, PTP slave device <NUM> may receive a sync message from PTP probe master device <NUM> with a T1 time from probe master clock <NUM>-<NUM>, which is a timestamp when the sync message is sent. PTP probe master device <NUM> may determine the time based on a timing source, such as a GNSS clock. PTP slave device <NUM> may note the time that the sync message is received as a T2 time. PTP slave device <NUM> sends a delay request message that includes a time stamp, referred to as a T3 time, of slave clock <NUM>. PTP slave device <NUM> receives a delay response from PTP probe master device <NUM> with a time stamp of probe master clock <NUM>-<NUM> when the delay request is received, referred to as a T4 time. From the times, PTP slave device <NUM> can then calculate the path delay between PTP probe master device <NUM> and PTP slave device <NUM>. For example, the path delay in path #<NUM><NUM>-<NUM> is ((T2-T1) +(T4-T3))/<NUM>. PTP slave device <NUM> may calculate the path delay over a number of delay request/delay response round trips. The path delay assumes a symmetrical delay in both directions, but since PTP probe master device <NUM> may be located closer to PTP slave device <NUM>, the packet delay variation and the asymmetry may be limited.

Once calculating the path delay, PTP slave device <NUM> adds the path delay between slave clock <NUM> and probe master clock <NUM>-<NUM> to the delay request. In some embodiments, PTP slave device <NUM> adds the path delay to a correction field in the delay request that includes the T3 time. The correction field may be a field that may not typically be used when checking the lock quality. The correction field may be typically used by clocks, such as transparent clocks in <NUM>, to add a correction to the timestamps due to an internal delay in the clock. Transparent clocks may be in switches. The correction field is typically not used by slave clocks. However, PTP probe master device <NUM> may be configured to use the T3 time and the path delay in the correction field to determine the adjusted time for slave device <NUM> to check the quality of the lock for slave clock <NUM>. For example, PTP probe master device <NUM> adds the path delay to the T3 time to calculate a current time of slave clock <NUM>. That is, the time T3 in which the delay request is sent in addition to the path delay should be the current time. Then, PTP probe master device <NUM> compares the current time of probe master clock <NUM>-<NUM> to the calculated current time for slave clock <NUM>. Based on the comparison, PTP probe master device <NUM> can check the quality of slave clock <NUM>. For example, because PTP probe master device <NUM> is connected to the same reference clock as PTP operational master device <NUM>, the comparison may determine any timing inaccuracies in slave clock <NUM>. Because the path delay is used and path #<NUM><NUM>-<NUM> may suffer from minimal packet delay variation or asymmetry, the path delay may be an accurate reading of the path delay. Thus, the adjusted time for slave clock <NUM> may yield an accurate current time that may be close to or exactly the same as the time and phase as probe master clock <NUM>-<NUM>. If the difference between the adjusted current time of slave clock <NUM> and the current time of probe master clock <NUM>-<NUM> meets a threshold (e.g., is below and/or equal to), then PTP probe master device <NUM> can confirm the accuracy of slave clock <NUM>.

Connecting PTP probe master device <NUM> to PTP slave device <NUM> without requiring a direct physical connection relieves a requirement that PTP slave device <NUM> includes an interface of slave clock <NUM> and also does not require PTP slave device <NUM> to operate as a boundary clock to advertise its clock to a remote PTP slave probe. The only requirement is that PTP slave device <NUM> inserts the T3 time in delay request messages along with the path delay in the correction field, which PTP slave devices <NUM> have the capability to perform based on communicating with operational master clock <NUM>-<NUM>. The following will now describe the process in more detail.

<FIG> depicts a more detailed example of PTP slave device <NUM> according to some embodiments. PTP slave device <NUM> includes multiple ports to connect to PTP operational master device <NUM> and PTP probe master device <NUM>. For example, PTP slave device <NUM> includes a slave port #<NUM><NUM>-<NUM> that connects to PTP operational master device <NUM>. Also, PTP slave device <NUM> includes a slave port #<NUM><NUM>-<NUM> that connects to PTP probe master device <NUM>.

Clock performance manager <NUM> may select a port depending on whether PTP slave device <NUM> is locking to operational master clock <NUM>-<NUM> or testing the quality of the lock with probe master clock <NUM>-<NUM>. For example, clock performance manager <NUM> may use slave port #<NUM><NUM>-<NUM> to lock slave clock <NUM> to operational master clock <NUM>-<NUM>. Then, clock performance manager <NUM> may use slave port #<NUM><NUM>-<NUM> to test the lock quality of slave clock <NUM> with probe master clock <NUM>-<NUM>. Clock performance manager <NUM> may be configured such that slave port #<NUM><NUM>-<NUM> is not used in an algorithm to select the best master clock Some methods may be to configure slave port #<NUM><NUM>-<NUM> with a lower priority, or put a clock class/quality value on probe master clock <NUM>-<NUM> such that it will not be selected, etc. Rather, clock performance manager <NUM> uses slave port #<NUM><NUM>-<NUM> to test the quality of the lock of slave clock <NUM> and does not lock the time of slave clock <NUM> to probe master clock <NUM>-<NUM>.

<FIG> depicts a simplified flowchart <NUM> of the process of configuring ports <NUM> on PTP slave device <NUM> to lock to operational master clock <NUM>-<NUM> according to some embodiments. At <NUM>, PTP slave device <NUM> is configured with two PTP slave ports <NUM>-<NUM> and <NUM>-<NUM>. At <NUM>, PTP slave device <NUM> configures slave port #<NUM><NUM>-<NUM> as unselectable as the master clock.

At <NUM>, clock performance manager <NUM> connects slave port #<NUM><NUM>-<NUM> to operational master clock <NUM>-<NUM> to perform the locking process. At <NUM>, clock performance manager <NUM> calculates a path delay for path #<NUM><NUM>-<NUM>. The path delay takes the round-trip time from PTP slave device <NUM> and PTP operational master device <NUM>, and divides the round-trip time by two. After determining the path delay, at <NUM>, PTP slave device <NUM> locks slave clock <NUM> to operational master clock <NUM>-<NUM> using the path delay for path #<NUM><NUM>-<NUM>. When locked to operational master clock <NUM>-<NUM>, a time of slave clock <NUM> is adjusted based on a time of operational master clock <NUM>-<NUM> and the path delay, such as the path delay is added to a time T4 from operational master clock <NUM>-<NUM> (e.g., time T4 + path delay = current time) to determine the correct current time. Slave clock <NUM> may ignore the value in the correction field that the probe master device copies to the correction field from the delay request message when receiving the T4 timestamp from the probe master device in the delay response message, and does not use the correction field to correct the T4 time.

After locking slave clock <NUM> to operational master clock <NUM>-<NUM>, clock performance manager <NUM> my test the lock quality. <FIG> depicts a simplified flowchart <NUM> for testing the lock quality of slave clock <NUM> according to some embodiments. At <NUM>, PTP slave device <NUM> connects to probe master clock <NUM>-<NUM> through slave port #<NUM><NUM>-<NUM>. At <NUM>, PTP slave device <NUM> calculates a path delay in the path #<NUM> between PTP slave device <NUM> and PTP probe master device <NUM>.

At <NUM>, PTP slave device <NUM> adds a T3 time from slave clock <NUM> in a delay request message. At <NUM>, PTP slave device <NUM> updates a correction field in the delay request message to include the path delay. At <NUM>, PTP slave device <NUM> sends the delay request message.

PTP probe master device <NUM> receives the T3 time and the path delay and can test the lock quality of slave clock <NUM>. For example, PTP probe master device <NUM> uses the T3 time and the path delay to adjust the time of slave clock <NUM> to take into account the path delay to send the delay request. This results in the current time of slave clock <NUM>. Then, PTP probe master device <NUM> compares the current time of probe master clock <NUM>-<NUM> to the adjusted T3 time (e.g., the current time of slave clock <NUM>) to determine the accuracy of slave clock <NUM>. For example, if the adjusted T3 time is similar to the time of probe master clock <NUM>-<NUM>, then the lock quality of slave clock <NUM> is high. However, if the adjusted T3 time is not close to the time of probe master clock <NUM>-<NUM>, then PTP probe master device <NUM> determines that the lock quality is low. PTP probe master device <NUM> may use a threshold to test the lock quality. For example, if the difference between the adjusted T3 time and the time of probe master clock <NUM>-<NUM> is above a threshold, PTP probe master device <NUM> may determine the lock quality is not good, and if the difference is below a threshold, PTP probe master device <NUM> may determine the lock quality is good.

PTP probe master device <NUM> may output a result of the comparison. It is noted that the above process may be performed multiple times over time to test the lock quality of slave clock <NUM>. For example, the lock quality check may be performed one or more times. The result may be based on a summary of the comparisons, such as an average of the differences or how many times a difference is above or below the threshold, but various methods may be used. Then, after determining a lock quality, the process may be performed after another interval, such as an hour later.

<FIG> depicts a simplified flowchart <NUM> of a method for testing the quality of slave clock <NUM> at PTP probe master device <NUM> according to some embodiments. At <NUM>, after PTP slave device <NUM> calculates a path delay, PTP probe master device <NUM> receives a delay request message with the T3 time and the path delay in the correction field.

At <NUM>, PTP probe master device <NUM> calculates an adjusted slave clock time based on the T3 time and the path delay that is located in the correction field. For example, PTP probe master device <NUM> may add the path delay to the T3 time to determine the adjusted T3 time. At <NUM>, PTP probe master device <NUM> compares the master clock time with the adjusted time.

At <NUM>, PTP probe master device <NUM> outputs the result of the comparison. For example, PTP probe master device <NUM> may compare a result of the comparison to a threshold to determine the quality or the accuracy of slave clock <NUM>.

The following will describe an example of testing the lock quality of slave clock <NUM>. The test may use the following parameters:.

Assuming there is path asymmetry between slave clock <NUM> and operational master clock <NUM>-<NUM>, PTP slave device <NUM> calculates the path delay from operational master clock <NUM>-<NUM> without knowing the asymmetry factor as per: <MAT>.

PTP slave device <NUM> calculates the nominal mean path delay without the unknown asymmetry value and adjusts its slave clock <NUM> accordingly which leads to a delay asymmetry error with a value of half the path asymmetry: <MAT>.

Note that slave clock <NUM> is inaccurate compared to operational master clock <NUM>-<NUM> with half of the path asymmetry value. This error results due to the two path delays in the upstream direction and the downstream direction being asymmetrical. The calculation of the path delay assumes these delays are symmetrical.

Now, assuming there is a very small path asymmetry between PTP slave device <NUM> and PTP probe master device <NUM>. PTP slave device <NUM> may calculate the path delay from PTP probe master device <NUM> accurately as: <MAT>.

In this example, PTP slave device <NUM> sends its time (T3) to PTP probe master device <NUM> and embeds the calculated path delay in the correction field. PTP probe master device <NUM> can receive the following information from the delay request (T3, correction field), which corresponds to (Ts, D-us-p) with a delay of D-us-p - the actual path delay). Therefore, the time of slave clock <NUM> analyzed by PTP probe master device <NUM> is: <MAT>.

The probe will reflect, the half of the operational asymmetry value as the offset measured between slave clock <NUM> and operational master clock <NUM>-<NUM>.

Thus, the performance of slave clock <NUM>, that is locked to operational master clock <NUM>-<NUM>, can be monitored by a clock probe that exchanges IEEE <NUM> standard messages with the slave clock <NUM>. PTP probe master device <NUM> operates as a master clock and uses the timestamp values in the messages to determine the performance of slave clock <NUM>. The quality of the performance monitoring is increased as the path asymmetry and packet delay variation are minimized. Operational master clock <NUM>-<NUM> and probe master clock <NUM>-<NUM> share a common timing source, such as a GNSS timing source, to triangulate the performance of slave clock <NUM>.

As disclosed, time stamps in standard IEEE <NUM> messages may be used to remotely monitor the performance of the slave clock. Also, PTP probe master device <NUM> may or may not be in the message transfer data path between operational master clock <NUM>-<NUM> and slave clock <NUM>. Operational master clock <NUM>-<NUM> and PTP probe master device <NUM> remotely share a common timing source to triangulate the performance of the slave clock.

Providing a manner for monitoring the performance of clocks may enable troubleshooting the distribution of timing in packet networks. As more packet-based services are deployed, including <NUM> wireless services, it will be valuable to be able to monitor clock performance and detect problems as quickly as possible. The disclosed techniques use timestamps in standard messages to remotely monitor a slave clock with the probe out of the master clock to slave clock data path, enabling remote monitoring of a packet slave clock. With the demand for packet clock performance, monitoring needs continue to expand with <NUM> deployments.

The following Emdodiments are examples suitable for understanding the invention and do not define the scope of protection. The scope of protection is merely defined by the claims.

In some embodiments, a method is performed after locking a first clock of a computing device to synchronize with a second clock associated with a first device, wherein a difference between the first clock and the second clock is determined during the locking, the method comprising: measuring, by the computing device, a path delay to a second device based on sending one or more messages including one or more first timestamps of the first clock to the second device and receiving one or more messages including one or more second timestamps of a third clock from the second device; and sending, by the computing device, a third message to the second device that includes a third timestamp of the first clock that has been locked to the second clock, wherein the third message includes the path delay, and wherein the third timestamp and the path delay allow the second device to analyze a lock quality of the first clock to the second clock based on a time of the third clock.

In some embodiments, the path delay is inserted in the third message in a correction field of the third message.

In some embodiments, the second device adjusts the third timestamp of the first clock that is locked to the second clock by the path delay to generate an adjusted third timestamp and compares the adjusted third timestamp to the time of the third clock.

In some embodiments, the third clock and the second clock are connected to a same timing source.

In some embodiments, the first clock is adjusted by the difference between the first clock and the second clock to lock the first clock to the second clock.

In some embodiments, the second device is located closer to the computing device compared to the first device.

In some embodiments, the second device is located in a last hop between a path between the first device and the computing device.

In some embodiments, the second device is not physically connected via an interface to the computing device.

In some embodiments, the computing device is not acting as a master clock to the third clock of the second device.

In some embodiments, measuring the path delay to the second device comprises: calculating a roundtrip delay between the computing device and the second device; and dividing the roundtrip delay by two.

In some embodiments, the second device analyzes the lock quality of the first clock to the second clock by: adding the path delay to the third timestamp to determine an adjusted third timestamp; and comparing the adjusted third timestamp to the time of the third clock.

In some embodiments, the second device analyzes the lock quality of the first clock to the second clock by: comparing a difference of the adjusted third timestamp to the time of the third clock to a threshold; and outputting a result of the comparison.

In some embodiments, when the difference is above a threshold, outputting an alert.

In some embodiments, a non-transitory computer-readable storage medium contains instructions performed after locking a first clock of a computing device to synchronize with a second clock associated with a first device, wherein a difference between the first clock and the second clock is determined during the locking, the instructions, when executed, control the computing device to be operable for: measuring a path delay to a second device based on sending one or more messages including one or more first timestamps of the first clock to the second device and receiving one or more messages including one or more second timestamps of a third clock from the second device; and sending a third message to the second device that includes a third timestamp of the first clock that has been locked to the second clock, wherein the third message includes the path delay, and wherein the third timestamp and the path delay allow the second device to analyze a lock quality of the first clock to the second clock based on a time of the third clock.

In some embodiments, an apparatus comprises: one or more computer processors; and a computer-readable storage medium comprising instructions for controlling the one or more computer processors after locking a first clock of the apparatus to synchronize with a second clock associated with a first device, wherein a difference between the first clock and the second clock is determined during the locking, to be operable for: measuring a path delay to a second device based on sending one or more messages including one or more first timestamps of the first clock to the second device and receiving one or more messages including one or more second timestamps of a third clock from the second device, and sending a third message to the second device that includes a third timestamp of the first clock that has been locked to the second clock, wherein the third message includes the path delay, and wherein the third timestamp and the path delay allow the second device to analyze a lock quality of the first clock to the second clock based on a time of the third clock.

<FIG> illustrates an example of special purpose computer systems <NUM> according to some embodiments. Computer system <NUM> includes a bus <NUM>, network interface <NUM>, a computer processor <NUM>, a memory <NUM>, a storage device <NUM>, and a display <NUM>.

Bus <NUM> may be a communication mechanism for communicating information. Computer processor <NUM> may execute computer programs stored in memory <NUM> or storage device <NUM>. Any suitable programming language can be used to implement the routines of some embodiments including C, C++, Java, assembly language, etc. Different programming techniques can be employed such as procedural or object oriented. The routines can execute on a single computer system <NUM> or multiple computer systems <NUM>. Further, multiple computer processors <NUM> may be used.

Memory <NUM> may store instructions, such as source code or binary code, for performing the techniques described above. Memory <NUM> may also be used for storing variables or other intermediate information during execution of instructions to be executed by processor <NUM>. Examples of memory <NUM> include random access memory (RAM), read only memory (ROM), or both.

Storage device <NUM> may also store instructions, such as source code or binary code, for performing the techniques described above. Storage device <NUM> may additionally store data used and manipulated by computer processor <NUM>. For example, storage device <NUM> may be a database that is accessed by computer system <NUM>. Other examples of storage device <NUM> include random access memory (RAM), read only memory (ROM), a hard drive, a magnetic disk, an optical disk, a CD-ROM, a DVD, a flash memory, a USB memory card, or any other medium from which a computer can read.

Memory <NUM> or storage device <NUM> may be an example of a non-transitory computer-readable storage medium for use by or in connection with computer system <NUM>. The non-transitory computer-readable storage medium contains instructions for controlling a computer system <NUM> to be configured to perform functions described by some embodiments. The instructions, when executed by one or more computer processors <NUM>, may be configured to perform that which is described in some embodiments.

Computer system <NUM> includes a display <NUM> for displaying information to a computer user. Display <NUM> may display a user interface used by a user to interact with computer system <NUM>.

Computer system <NUM> also includes a network interface <NUM> to provide data communication connection over a network, such as a local area network (LAN) or wide area network (WAN). Wireless networks may also be used. In any such implementation, network interface <NUM> sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.

Computer system <NUM> can send and receive information through network interface <NUM> across a network <NUM>, which may be an Intranet or the Internet. Computer system <NUM> may interact with other computer systems <NUM> through network <NUM>. In some examples, client-server communications occur through network <NUM>. Also, implementations of some embodiments may be distributed across computer systems <NUM> through network <NUM>.

Some embodiments may be implemented in a non-transitory computer-readable storage medium for use by or in connection with the instruction execution system, apparatus, system, or machine. The computer-readable storage medium contains instructions for controlling a computer system to perform a method described by some embodiments. The computer system may include one or more computing devices. The instructions, when executed by one or more computer processors, may be configured to perform that which is described in some embodiments.

As used in the description herein and throughout the claims that follow, "a", "an", and "the" includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of "in" includes "in" and "on" unless the context clearly dictates otherwise.

Claim 1:
A method performed after locking a first clock of a computing device (<NUM>) to synchronize with a second clock associated with a first device (<NUM>), wherein a difference between the first clock and the second clock is determined during the locking, the method comprising:
measuring, by the computing device (<NUM>), a path delay to a second device (<NUM>) based on sending one or more messages including one or more first timestamps of the first clock to the second device (<NUM>) and receiving one or more messages including one or more second timestamps of a third clock from the second device (<NUM>); and
sending, by the computing device (<NUM>), a third message to the second device (<NUM>) that includes a third timestamp of the first clock that has been locked to the second clock by the exchange of messages between the computing device (<NUM>) and the first device (<NUM>) using a timestamp of the first clock and a timestamp of the second clock, wherein the third message includes the path delay, and wherein the third timestamp and the path delay allow the second device (<NUM>) to analyze a lock quality of the first clock to the second clock based on a time of the third clock;
wherein the path delay is inserted in the third message in a correction field of the third message.