Patent Description:
In the related art, chips are bonded through interconnection of metal pads on the chips. The stacked chips need to be transferred before further bonding. If there is vibration or an external force influence, the stacked chips cannot be aligned due to slippage, which may increase the manufacturing difficulty. Background art may be found in <CIT>.

The present disclosure provides a semiconductor structure and a manufacturing method thereof, to improve the performance of the semiconductor structure.

The preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings to make the objectives, features and advantages of the present disclosure more obvious. The drawings are merely exemplary illustrations of the present disclosure, and are not necessarily drawn to scale. The same reference numerals in the drawings always represent the same parts. In the drawings:.

The typical embodiments embodying the features and advantages of the present disclosure are described in detail below. It should be understood that the present disclosure may have various changes in different embodiments, which do not depart from the scope of the present disclosure. The description and drawings herein are essentially used for the purpose of explanation, rather than limiting the present disclosure.

Different exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings. The accompanying drawings form a part of the present disclosure, which show by way of example different exemplary structures, systems and steps that can implement various aspects of the present disclosure. It should be understood that other specific solutions of components, structures, exemplary devices, systems and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms such as "above", "between" and "within" may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience of description, for example, according to the directions of the examples in the drawings. Nothing in this specification should be understood as requiring a specific three-dimensional direction of the structure to fall within the scope of the present disclosure.

An embodiment of the present disclosure provides a semiconductor structure. With reference to <FIG>, the semiconductor structure includes a first chip <NUM> and a second chip <NUM>. The first chip <NUM> includes a first substrate <NUM>, a first conductive connection wire <NUM> and a first conductive contact pad <NUM>, where the first conductive contact pad <NUM> is connected to the first conductive connection wire <NUM> and includes a first conductor <NUM> and a second conductor <NUM>, and a melting point of the first conductor <NUM> is higher than that of the second conductor <NUM>. The second chip <NUM> includes a second substrate <NUM>, a second conductive connection wire <NUM> and a second conductive contact pad <NUM>, where the second conductive contact pad <NUM> is connected to the second conductive connection wire <NUM> and includes a third conductor <NUM> and a fourth conductive <NUM>, and a melting point of the third conductor <NUM> is higher than that of the fourth conductor <NUM>. The first conductor <NUM> is directly opposite to the fourth conductor <NUM>, and the second conductor <NUM> is directly opposite to the third conductor <NUM>, such that a bonding structure is formed between the first conductive contact pad <NUM> and the second conductive contact pad <NUM>.

The semiconductor structure according to the embodiment of the present disclosure includes the first chip <NUM> and the second chip <NUM>. The first conductive connection wire <NUM> of the first chip <NUM> is connected to the first conductive contact pad <NUM>, and the second conductive connection wire <NUM> of the second chip <NUM> is connected to the second conductive contact pad <NUM>. In addition, the first conductive contact pad <NUM> includes the first conductor <NUM> and the second conductor <NUM>, and the second conductive contact pad <NUM> includes the third conductor <NUM> and the fourth conductor <NUM>. The first conductor <NUM> is directly opposite to the fourth conductor <NUM>, and the second conductor <NUM> is directly opposite to the third conductor <NUM>. Moreover, the melting point of the first conductor <NUM> is higher than that of the second conductor <NUM>, and the melting point of the third conductor <NUM> is higher than that of the fourth conductor <NUM>. Therefore, the second conductor <NUM> and the fourth conductor <NUM> may be melted at a first temperature, that is, pre-connection of the first conductive contact pad <NUM> and the second conductive contact pad <NUM> is implemented. After that, the first chip <NUM> and the second chip <NUM> that are pre-connected are transferred to an annealing condition at a second temperature for bonding, so as to implement reliable bonding of the first conductive contact pad <NUM> and the second conductive contact pad <NUM>. Before the transfer, the first chip <NUM> and the second chip <NUM> have been pre-connected, such that relative movement between the first chip <NUM> and the second chip <NUM> is avoided, which ensures reliable alignment of the first chip <NUM> and the second chip <NUM>, thereby improving the performance of the semiconductor structure.

It should be noted that, at the first temperature, the second conductor <NUM> and the fourth conductor <NUM> are melted, while the first conductor <NUM> and the third conductor <NUM> are not melted. At the moment, conductive materials of the first conductive contact pad <NUM> and the second conductive contact pad <NUM> may each be interpenetrated and fused at an interface, as shown in <FIG>. Therefore, an intermetallic compound (IMC) is formed and the pre-connection of the first conductive contact pad <NUM> and the second conductive contact pad <NUM> is implemented. Or, even though the conductive materials of the first conductive contact pad <NUM> and the second conductive contact pad <NUM> are not each interpenetrated and fused at the interface, the melted second conductor <NUM> and fourth conductor <NUM> may also be connected to the third conductor <NUM> and the first conductor <NUM> after cooling. As a result, the pre-connection of the first conductive contact pad <NUM> and the second conductive contact pad <NUM> may also be implemented. The first conductive contact pad <NUM> and the second conductive contact pad <NUM> are pre-connected, such that relative slippage of the first chip <NUM> and the second chip <NUM> does not occur in a subsequent process of transferring the first chip <NUM> and the second chip <NUM>. In this way, it is ensured that the first chip <NUM> and the second chip <NUM> may be bonded to each other under the annealing condition at the second temperature after the first chip <NUM> and the second chip <NUM> are reliably aligned. Therefore, the reliable bonding of the first conductive contact pad <NUM> and the second conductive contact pad <NUM> is implemented, and the reliable bonding structure is formed between the first conductive contact pad <NUM> and the second conductive contact pad <NUM>. In the related art, the first chip <NUM> and the second chip <NUM> need to be directly placed in a high-temperature environment for bonding. In the transfer process, the alignment is influenced by slippage, which may influence the performance of the semiconductor structure. The semiconductor structure in the embodiment can improve the alignment problem in the related art, so as to improve the performance of the semiconductor structure.

After completion of the bonding of the first conductive contact pad <NUM> and the second conductive contact pad <NUM>, an IMC layer is formed on a junction surface of the first conductive contact pad <NUM> and the second conductive contact pad <NUM>, and the IMC layer is as wide as the first conductive contact pad <NUM> and/or the second conductive contact pad <NUM>. The first conductor <NUM> is directly opposite to the fourth conductor <NUM>, and the second conductor <NUM> is directly opposite to the third conductor <NUM>. In addition, the melting point of the first conductor <NUM> is higher than that of the second conductor <NUM>, and the melting point of the third conductor <NUM> is higher than that of the fourth conductor <NUM>. That is, it may be understood that the second conductor <NUM> with a lower melting point is accommodated in the first conductor <NUM>, similarly, a recess is formed in the first conductor <NUM>; and the third conductor <NUM> with a higher melting point is accommodated in the fourth conductor <NUM>, similarly, a recess is formed in the fourth conductor <NUM>. Moreover, if the second conductor <NUM> and the fourth conductor <NUM> are removed, a protrusion of the first conductive contact pad <NUM> corresponds to a recess of the second conductive contact pad <NUM>, and a recess of the first conductive contact pad <NUM> corresponds to a protrusion of the second conductive contact pad <NUM>. A coefficient of thermal expansion of the first conductor <NUM> is higher than that of the second conductor <NUM>, and a coefficient of thermal expansion of the third conductor <NUM> is higher than that of the fourth conductor <NUM>. In this way, the first conductive contact pad <NUM> and the second conductive contact pad <NUM> are maximally matched with thermal expansion of metal, that is, a part with high thermal expansion is matched with a part with low thermal expansion. Therefore, both the first conductive contact pad <NUM> and the second conductive contact pad <NUM> may have redundant spaces for expansion, thereby preventing cracks.

The first conductor <NUM> is directly opposite to the fourth conductor <NUM> and the second conductor <NUM> is directly opposite to the third conductor <NUM>, which actually illustrates a position relationship of the first chip <NUM> and the second chip <NUM> before the bonding. After the bonding, that is, when the bonding structure is formed between the first conductive contact pad <NUM> and the second conductive contact pad <NUM>, there may not always be the position relationship, and a corresponding position relationship may not be determined between the conductive materials due to fusion. However, the position relationship may be judged from material configuration.

In some embodiments, both the first conductive connection wire <NUM> and the first conductive contact pad <NUM> are located in the first substrate <NUM>, and both the second conductive connection wire <NUM> and the second conductive contact pad <NUM> are located in the second substrate <NUM>.

The first conductive connection wire <NUM> and the first conductive contact pad <NUM> may be partially or entirely located in the first substrate <NUM>. Correspondingly, the second conductive connection wire <NUM> and the second conductive contact pad <NUM> may be partially or entirely located in the second substrate <NUM>.

In some embodiments, the first conductive contact pad <NUM> may be located on a surface of the first substrate <NUM>. Correspondingly, the second conductive contact pad <NUM> may be located on a surface of the second substrate <NUM>.

It should be noted that after the first chip <NUM> and the second chip <NUM> are bonded, the first substrate <NUM> and the second substrate <NUM> are bonded to each other. The first substrate <NUM> includes a silicon substrate and an insulating layer formed above the silicon substrate, a part of the first conductive connection wire <NUM> is located in the insulating layer, and the first conductive contact pad <NUM> is formed in the insulating layer. Correspondingly, the second substrate <NUM> includes a silicon substrate and an insulating layer formed above the silicon substrate, a part of the second conductive connection wire <NUM> is located in the insulating layer, and the second conductive contact pad <NUM> is formed in the insulating layer. When the first chip <NUM> and the second chip <NUM> are bonded, the first conductive contact pad <NUM> and the second conductive contact pad <NUM> are bonded to each other, and the insulating layers of the first chip <NUM> and the second chip <NUM> are bonded to each other.

Specifically, the silicon substrates may be made of a silicon-containing material. The silicon substrates may be made of any proper material, for example, including at least one of silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium or carbon-doped silicon.

The insulating layers may include silicon dioxide (SiO<NUM>), silicon oxide carbon (SiOC), silicon nitride (SiN), silicon carbon nitride (SiCN), and other related insulating materials used in an integrated circuit.

In an embodiment, the first conductive connection wire <NUM> is a first through-silicon via, and the second conductive connection wire <NUM> is a second through-silicon via. The first through-silicon via and the second through-silicon via are connected through the first conductive contact pad <NUM> and the second conductive contact pad <NUM>. In some embodiments, the second conductor <NUM> corresponds to a center region of the first through-silicon via. Due to maximal overall expansion of the center region of the first through-silicon via, a thickness of the second conductor <NUM> may be greater than a thickness of the fourth conductor <NUM>, such that an enough redundant space for expansion is retained for the first through-silicon via. In some embodiments, the fourth conductor <NUM> corresponds to a center region of the second through-silicon via, and the second conductor <NUM> may be thinner than the fourth conductor <NUM>.

In some embodiments, a thickness of the second conductor <NUM> may be equal to a thickness of the fourth conductor <NUM>.

In an embodiment, a thickness of the second conductor <NUM> is less than <NUM>, and a thickness of the fourth conductor <NUM> is less than <NUM>.

In an embodiment, as shown in <FIG>, an end of the first conductive contact pad <NUM> facing toward the second conductive contact pad <NUM> is a first contact surface <NUM>, and an end of the second conductive contact pad <NUM> facing toward the first contact surface <NUM> is a second contact surface <NUM>. The first conductor <NUM> and the second conductor <NUM> occupy different parts of the first contact surface <NUM> respectively, and the third conductor <NUM> and the fourth conductor <NUM> occupy different parts of the second contact surface <NUM> respectively. When the first chip <NUM> and the second chip <NUM> are bonded, the first contact surface <NUM> and the second contact surface <NUM> are butted to implement electrical connection of the first conductive contact pad <NUM> and the second conductive contact pad <NUM>.

In some embodiments, the first conductor <NUM> and the second conductor <NUM> occupy a part of the first contact surface <NUM>, that is, the first conductive contact pad <NUM> may also include other conductors. Correspondingly, the third conductor <NUM> and the fourth conductor <NUM> occupy a part of the second contact surface <NUM>, and the second conductive contact pad <NUM> may also include other conductors.

In some embodiments, the first conductor <NUM> and the second conductor <NUM> occupy the whole first contact surface <NUM>, that is, the first conductive contact pad <NUM> may include only the first conductor <NUM> and the second conductor <NUM>. Or the first conductive contact pad <NUM> may include other conductors that are not located at an end of the first conductive contact pad <NUM> away from the first conductive connection wire <NUM>. Correspondingly, the third conductor <NUM> and the fourth conductor <NUM> occupy the whole second contact surface <NUM>, that is, the second conductive contact pad <NUM> may include only the third conductor <NUM> and the fourth conductor <NUM>. Or the second conductive contact pad <NUM> may include other conductors that are not located at an end of the second conductive contact pad <NUM> away from the second conductive connection wire <NUM>.

In an embodiment, an area of the first contact surface <NUM> is equal to that of the second contact surface <NUM>, that is, an area of a fusion surface of the first chip <NUM> is equal to an area of a fusion surface of the second chip <NUM>. When the first conductor <NUM> and the second conductor <NUM> occupy the whole first contact surface <NUM>, and the third conductor <NUM> and the fourth conductor <NUM> occupy the whole second contact surface <NUM>, an area occupied by the first conductor <NUM> on the first contact surface <NUM> is equal to an area occupied by the fourth conductor <NUM> on the second contact surface <NUM>, and an area occupied by the second conductor <NUM> on the first contact surface <NUM> is equal to an area occupied by the third conductor <NUM> on the second contact surface <NUM>. In this way, it is ensured that the first conductor <NUM> is directly opposite to the fourth conductor <NUM>, and the second conductor <NUM> is directly opposite to the third conductor <NUM>.

In some embodiments, when the area of the first contact surface <NUM> is equal to that of the second contact surface <NUM>, the first conductor <NUM> and the second conductor <NUM> occupy a part of the first contact surface <NUM>, and the third conductor <NUM> and the fourth conductor <NUM> occupy a part of the second contact surface <NUM>, it may be ensured that the first conductor <NUM> is directly opposite to the fourth conductor <NUM>, the second conductor <NUM> is directly opposite to the third conductor <NUM>, and the other conductors included by the first conductive contact pad <NUM> are directly opposite to the other conductors included by the second conductive contact pad <NUM>.

In an embodiment, the area of the first contact surface <NUM> is unequal to that of the second contact surface <NUM>, that is, the area of the fusion surface of the first chip <NUM> is unequal to the area of the fusion surface of the second chip <NUM>. When the area of the first contact surface <NUM> is smaller than that of the second contact surface <NUM>, a part of the second contact surface <NUM> is opposite to the first substrate <NUM>. Correspondingly, when the area of the first contact surface <NUM> is greater than that of the second contact surface <NUM>, a part of the first contact surface <NUM> is opposite to the second substrate <NUM>.

It should be noted that when the area of the first contact surface <NUM> is unequal to that of the second contact surface <NUM>, for example, when the area of the first contact surface <NUM> is smaller than that of the second contact surface <NUM>, the first conductor <NUM> and the second conductor <NUM> may occupy the whole the first contact surface <NUM>, and the third conductor <NUM> and the fourth conductor <NUM> may also occupy the whole second contact surface <NUM>. At the moment, it should be ensured that the whole first conductor <NUM> is directly opposite to the fourth conductor <NUM> and the whole second conductor <NUM> is directly opposite to the third conductor <NUM>. Moreover, the other part of at least one of the third conductor <NUM> and the fourth conductor <NUM> of the second conductive contact pad <NUM> may directly correspond to the first substrate <NUM>. Correspondingly, when the area of the first contact surface <NUM> is greater than that of the second contact surface <NUM>, reference may also be made to the embodiment, and details are not described herein.

In an embodiment, a circumferential outer edge of the first contact surface <NUM> includes at least one of a straight line or a curve, and a circumferential outer edge of the second contact surface <NUM> includes at least one of a straight line or a curve. The first contact surface <NUM> may have a shape identical with or different from that of the second contact surface <NUM>, and the shape of the first contact surface <NUM> and the shape of the second contact surface <NUM> may be circular, elliptical, rectangular and the like, which is not limited herein.

It should be noted that, when the area of the first contact surface <NUM> is equal to that of the second contact surface <NUM>, the first conductor <NUM> and the second conductor <NUM> occupy the whole first contact surface <NUM>, and the third conductor <NUM> and the fourth conductor <NUM> occupy the whole second contact surface <NUM>, it may be illustrated that the first contact surface <NUM> has the shape identical with that of the second contact surface <NUM>, and the first contact surface <NUM> exactly coincides with the second contact surface <NUM>.

In the inventive embodiment, a volume occupied by the first conductor <NUM> in the first conductive contact pad <NUM> is greater than a volume occupied by the second conductor <NUM> in the first conductive contact pad <NUM>, and a volume occupied by the third conductor <NUM> in the second conductive contact pad <NUM> is greater than a volume occupied by the fourth conductor <NUM> in the second conductive contact pad <NUM>. That is, proportions of low-melting point conductive materials of the first conductive contact pad <NUM> and the second conductive contact pad <NUM> are relatively low. When the first chip <NUM> and the second chip <NUM> are bonded, the second conductor <NUM> and the fourth conductor <NUM> are used to ensure pre-connection, and the first conductive contact pad <NUM> and the second conductive contact pad <NUM> are electrically connected to other structures mainly through the first conductor <NUM> and the third conductor <NUM>.

In an embodiment, an end of each first conductive connection wire <NUM> is connected to the first conductor <NUM>, and an end of each second conductive connection wire <NUM> is connected to the third conductor <NUM>. That is, the second conductor <NUM> is included only on a side of the first conductive contact pad <NUM> away from the first conductive connection wire <NUM>, and the fourth conductor <NUM> is included only on a side of the second conductive contact pad <NUM> away from the second conductive connection wire <NUM>.

It should be noted that an end of each first conductive connection wire <NUM> is connected to the first conductor <NUM>, and an end of each second conductive connection wire <NUM> is connected to the third conductor <NUM>. It may be further understood that, before the first chip <NUM> and the second chip <NUM> are bonded, an end of each first conductive connection wire <NUM> is connected to the first conductor <NUM> and an end of each second conductive connection wire <NUM> is connected to the third conductor <NUM>. After the bonding structure is formed between the first conductive contact pad <NUM> and the second conductive contact pad <NUM>, there may be a possibility of fusion between the conductive materials. However, a structure relationship may also be judged from material configuration.

In an embodiment, the second conductor <NUM> includes a plurality of first sub-conductive sections <NUM>, and a part of the first conductor <NUM> is clamped between adjacent first sub-conductive sections <NUM>. That is, it may be understood that voids are formed on a side of the first conductor <NUM> away from the first conductive connection wire <NUM>, so as to fill the first sub-conductive sections <NUM>.

In an embodiment, the fourth conductor <NUM> includes a plurality of second sub-conductive sections <NUM>, and a part of the third conductor <NUM> is clamped between adjacent second sub-conductive sections <NUM>. That is, it may be understood that voids are formed on a side of the third conductor <NUM> away from the second conductive connection wire <NUM>, so as to fill the second sub-conductive sections <NUM>.

As shown in <FIG> and <FIG>, the area of the first contact surface <NUM> is equal to that of the second contact surface <NUM>. The first conductor <NUM> and the second conductor <NUM> occupy the whole first contact surface <NUM>, and the third conductor <NUM> and the fourth conductor <NUM> occupy the whole second contact surface <NUM>. In addition, the area occupied by the first conductor <NUM> on the first contact surface <NUM> is smaller than the area occupied by the second conductor <NUM> on the first contact surface <NUM>, and the area occupied by the third conductor <NUM> on the second contact surface <NUM> is greater than the area occupied by the fourth conductor <NUM> on the second contact surface <NUM>. Therefore, it is ensured that the first conductor <NUM> is directly opposite to the fourth conductor <NUM>, and the second conductor <NUM> is directly opposite to the third conductor <NUM>. Moreover, the second conductor <NUM> includes a plurality of first sub-conductive sections <NUM>, and the fourth conductor <NUM> includes a plurality of second sub-conductive sections <NUM>.

As shown in <FIG>, the area of the first contact surface <NUM> is equal to that of the second contact surface <NUM>. The first conductor <NUM> and the second conductor <NUM> occupy the whole first contact surface <NUM>, and the third conductor <NUM> and the fourth conductor <NUM> occupy the whole second contact surface <NUM>. In addition, the area occupied by the first conductor <NUM> on the first contact surface <NUM> is greater than the area occupied by the second conductor <NUM> on the first contact surface <NUM>, and the area occupied by the third conductor <NUM> on the second contact surface <NUM> is smaller than the area occupied by the fourth conductor <NUM> on the second contact surface <NUM>. Therefore, it is ensured that the first conductor <NUM> is directly opposite to the fourth conductor <NUM>, and the second conductor <NUM> is directly opposite to the third conductor <NUM>. Moreover, the second conductor <NUM> includes a plurality of first sub-conductive sections <NUM>, and the fourth conductor <NUM> includes a plurality of second sub-conductive sections <NUM>.

In an embodiment, a material of the first conductor <NUM> may be the same as a material of the third conductor <NUM>, the first conductor <NUM> includes at least one of copper or tungsten, and the third conductor <NUM> includes at least one of copper or tungsten. Certainly, In some embodiments, it is not excluded that the material of the first conductor <NUM> is different from the material of the third conductor <NUM> are different, but the melting point of the first conductor is approximately the same as the melting point of the third conductor.

In an embodiment,a material of the second conductor <NUM> may be the same as a material of the fourth conductor <NUM>, the first conductor <NUM> includes at least one of copper or tungsten, and the second conductor <NUM> includes at least one of bismuth, cadmium, tin, lead, dysprosium or indium. Certainly, In some embodiments, it is not excluded that the material of the second conductor <NUM> is different from the material of the fourth conductor <NUM>, but the melting point of the second conductor is approximately the same as the melting point of the fourth conductor.

It should be noted that the first conductor <NUM> and the third conductor <NUM> may include only single material, for example, both the first conductor <NUM> and the third conductor <NUM> may be copper. The first conductor <NUM> and the third conductor <NUM> may also be alloys, for example, copper-tungsten alloys. The second conductor <NUM> and the fourth conductor <NUM> may include only single material, for example, both the second conductor <NUM> and the fourth conductor <NUM> may be tin. Or, the second conductor <NUM> and the fourth conductor <NUM> may be alloys, for example, bismuth-tin, bismuth-lead, tin-indium and the like.

In an embodiment, the first conductor <NUM> and the third conductor <NUM> may be copper, and the second conductor <NUM> and the fourth conductor <NUM> may be tin. Due to a combination effect of low-melting point metal tin and a thermal expansion effect of metal copper, a copper surface is slightly indented to be smoothly fused with a low-melting point metal tin layer. During low-temperature (such as the first temperature) fusion, on upper and lower layers, tin (Sn) and copper (Cu) are each interpenetrated and fused at the interface, and tin is fused with nearby copper to form a Cu5Sn6 intermetallic compound (IMC). The upper and lower layers are made of different materials and alternately mixed, such that an area of the IMC can be increased to improve the bonding strength, and resistance for slippage of stacked chips caused by external force or movement is provided to the stacked chips (especially alignment accuracy of chips on upper and lower layers). Therefore, benefit is brought to the bonding of the upper and lower layers of first conductive contact pad <NUM> and the second conductive contact pad <NUM> that undergo high-temperature (such as the second temperature) annealing afterwards, so as to improve the product yield.

According to the semiconductor structure of the present disclosure, the upper and lower layers of low-melting point metal/alloys fused at a low temperature may be bonded firstly, and then fused with nearby metal to form intermetallic compounds so as to increase the bonding strength. Therefore, an alignment rate is provided for the bonding of the upper and lower layers of high-fusion point metal/metal that undergo high-temperature annealing afterwards, so as to enhance the yield of the semiconductor structure.

An embodiment of the present disclosure further provides a method of manufacturing a semiconductor structure. With reference to <FIG>, the method of manufacturing a semiconductor includes the following steps.

S101: Provide a first chip <NUM>. The first chip <NUM> includes a first substrate <NUM>, a first conductive connection wire <NUM> and a first conductive contact pad <NUM>, the first conductive contact pad <NUM> is connected to the first conductive connection wire <NUM> and includes a first conductor <NUM> and a second conductor <NUM>, and a melting point of the first conductor <NUM> is higher than that of the second conductor <NUM>.

S103: Provide a second chip <NUM>. The second chip <NUM> includes a second substrate <NUM>, a second conductive connection wire <NUM> and a second conductive contact pad <NUM>, the second conductive contact pad <NUM> is connected to the second conductive connection wire <NUM> and includes a third conductor <NUM> and a fourth conductor <NUM>, and a melting point of the third conductor <NUM> is higher than that of the fourth conductor <NUM>.

S105: Align the first chip <NUM> with the second chip <NUM>. In this way, the first conductor <NUM> is directly opposite to the fourth conductor <NUM> and the second conductor <NUM> is directly opposite to the third conductor <NUM>.

S107: Connect the first chip <NUM> and the second chip <NUM>.

According to the method of manufacturing a semiconductor structure according to the embodiment of the present disclosure, the first conductive connection wire <NUM> of the first chip <NUM> is connected to the first conductive contact pad <NUM>, and the second conductive connection wire <NUM> of the second chip <NUM> is connected to the second conductive contact pad <NUM>. In addition, the first conductive contact pad <NUM> includes the first conductor <NUM> and the second conductor <NUM>, and the second conductive contact pad <NUM> includes the third conductor <NUM> and the fourth conductor <NUM>. The first conductor <NUM> is directly opposite to the fourth conductor <NUM>, and the second conductor <NUM> is directly opposite to the third conductor <NUM>. Moreover, the melting point of the first conductor <NUM> is higher than that of the second conductor <NUM>, and the melting point of the third conductor <NUM> is higher than that of the fourth conductor <NUM>. Therefore, pre-connection of the first conductive contact pad <NUM> and the second conductive contact pad <NUM> may be firstly implemented and then high-temperature bonding is performed to implement reliable bonding of the first conductive contact pad <NUM> and the second conductive contact pad <NUM>. Before the transfer, the first chip <NUM> and the second chip <NUM> have been pre-connected, such that relative movement between the first chip <NUM> and the second chip <NUM> is avoided, which ensures reliable alignment of the first chip <NUM> and the second chip <NUM>, thereby improving the performance of the semiconductor structure.

In the inventive embodiment, S107 includes: melt the second conductor <NUM> and the fourth conductor <NUM> at a first temperature, such that the first chip <NUM> is connected to the second chip <NUM>. The first temperature is lower than the melting point of the first conductor <NUM> and the melting point of the third conductor <NUM>. That is, at the first temperature, the second conductor <NUM> and the fourth conductor <NUM> are melted, while the first conductor <NUM> and the third conductor <NUM> are not melted. At the moment, conductive materials of the first conductive contact pad <NUM> and the second conductive contact pad <NUM> may be each interpenetrated and fused at an interface to form a pre-bonding structure.

In an embodiment, S107 further includes: bond the connected first chip <NUM> and the connected second chip <NUM> under an annealing condition at a second temperature, such that a bonding structure is formed after the first conductive contact pad <NUM> and the second conductive contact pad <NUM> are melted. The first temperature is lower than the second temperature. The first conductive contact pad <NUM> and the second conductive contact pad <NUM> form the pre-bonding structure at the first temperature, so as to move to an environment at the second temperature for bonding. Therefore, the first chip <NUM> and the second chip <NUM> may be prevented from relative slippage, thereby improving the yield of the semiconductor structure.

It should be noted that a specific process of bonding the first chip <NUM> and the second chip <NUM> under the annealing condition at the second temperature is not limited, and reference may be made to a bonding manner in the related art. It is focused herein that the first chip <NUM> and the second chip <NUM> have been pre-connected before the bonding under the annealing condition at the second temperature.

In an embodiment, the second conductor <NUM> is formed on the first conductor <NUM> through electroplating or printing, and the fourth conductor <NUM> is formed on the third conductor <NUM> through electroplating or printing.

It should be noted that, in an embodiment, the method of manufacturing a semiconductor structure is used to form the semiconductor structure. For materials and structures of the first chip <NUM> and the second chip <NUM> involved in the method of manufacturing a semiconductor structure, reference may be made to specification of the semiconductor structure, and details are not described herein.

Those skilled in the art may easily figure out other implementations of the present disclosure after considering the specification and practicing the content disclosed herein. The present disclosure is intended to cover any variations, purposes or applicable changes of the present disclosure. Such variations, purposes or applicable changes follow the general principle of the present disclosure and include common knowledge or conventional technical means in the technical field which is not disclosed in the present disclosure. The specification and implementations are merely considered as illustrative, and the real scope of the present disclosure is directed by the appended claims.

Claim 1:
A semiconductor structure, comprising:
a first chip (<NUM>), wherein the first chip (<NUM>) comprises a first substrate (<NUM>), a first conductive connection wire (<NUM>) and a first conductive contact pad (<NUM>), the first conductive contact pad (<NUM>) is connected to the first conductive connection wire (<NUM>), the first conductive contact pad (<NUM>) comprises a first conductor (<NUM>) and a second conductor (<NUM>), and a melting point of the first conductor (<NUM>) is higher than a melting point of the second conductor (<NUM>); and
a second chip (<NUM>), wherein the second chip (<NUM>) comprises a second substrate (<NUM>), a second conductive connection wire (<NUM>) and a second conductive contact pad (<NUM>), the second conductive contact pad (<NUM>) is connected to the second conductive connection wire (<NUM>), the second conductive contact pad (<NUM>) comprises a third conductor (<NUM>) and a fourth conductor (<NUM>), and a melting point of the third conductor (<NUM>) is higher than a melting point of the fourth conductor (<NUM>);
wherein the first conductor (<NUM>) is directly opposite to the fourth conductor (<NUM>), and the second conductor (<NUM>) is directly opposite to the third conductor (<NUM>), such that a bonding structure is formed between the first conductive contact pad (<NUM>) and the second conductive contact pad (<NUM>);
characterized in that a volume occupied by the first conductor (<NUM>) in the first conductive contact pad (<NUM>) is greater than a volume occupied by the second conductor (<NUM>) in the first conductive contact pad (<NUM>); and
a volume occupied by the third conductor (<NUM>) in the second conductive contact pad (<NUM>) is greater than a volume occupied by the fourth conductor (<NUM>) in the second conductive contact pad (<NUM>).