Patent Description:
Although conventional BGA sockets come in many shapes and sizes, there are typically various industry standard sizes and pin outs. Once settled upon, these standard sizes are used over time, sometimes in multitudes of different devices, such as computers, handheld devices and other electronic devices. One example of a conventional BGA socket is an Nvidia SMX2.

Another conventional multi-chip module technology is 2D wafer-level fan-out (or 2D WLFO). Conventioal 2D WLFO technology is based on embedding die into a molded wafer, also called "wafer reconstitution. " The molded wafer is processed through a standard wafer level processing flow to create the final integrated circuit assembly structure. The active surface of the dies are coplanar with the mold compound, allowing for the "fan-out" of conductive copper traces and solder ball pads into the molded area using conventional redistribution layer (RDL) processing. Conventional 3D WLFO extends the 2D technology into multi-chip stacking where a second package substrate is mounted on the 2D WLFO. The following prior art references are acknowledged: <CIT>: Package Structure and Methods of forming the same); <CIT>: Three-Dimensional IC Formation with Dies Bonded to Formed Redistribution Lines); <CIT>: Fan-out Stacked System in Package (SIP) having Dummy Dies and Methods of Making the Same); <CIT>: Multi-Chip Package with Interconnects Extending Through Logic Chip); and <CIT>: Thermally Enhanced Package-on-Package Structure).

The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings. The embodiments of <FIG> and <FIG> are no longer in accordance with the claimed invention but may be useful in explaining certain technical aspects of the invention. In the drawings:.

One conventional multi-chip module variant includes side-by-side processor and memory chips in a <NUM>. 5D arrangement on a silicon interposer that is, in-turn, mounted on a package substrate. The conventional package substrate is manufactured with a footprint and pin out tailored for a particular type of BGA socket. In other words, the size and shape of the package substrate is, to a large extent, dictated by the mechanical properties, size, etc. of the socket. Performance of a given multi-chip module can be often increased by incorporating additional memory chips into the module that cooperate with processor(s) or system-on-chip chips. However, packing additional memory chips into a multi-chip module designed for a standard socket and attendant package substrate, is a technical challenge. One conventional solution is to simply increase the size of both the interposer and the package. Of course this technique almost always involves a redesign of the socket, which will require the redesign and configuration of the multitudes of different types of circuit boards that use the originally adopted standard socket.

The disclosed embodiments solve the issue of incorporating additional chips in a multi- chip module by stacking the somewhat smaller chips over a larger processor or other type of integrated circuit and at least partially laterally overlapping the upper chips with the lower chip all without having to substantially change the physical footprints of the underlying interposer and the package substrate. In this way, additional memory devices or other types of integrated circuits can be incorporated into a multi chip module while preserving the ability to use existing socket sizes and designs.

According to the invention, a semiconductor device according to claim <NUM> is provided. Additional aspects are outlined in the dependent claims.

In the drawings described below, reference numerals are generally repeated where identical elements appear in more than one figure. Turning now to the drawings, and in particular to <FIG> which is a plan view of an exemplary conventional semiconductor chip package <NUM> mounted in a socket <NUM> of a system board <NUM>. Note that only a portion of the system board <NUM> is depicted. The conventional package includes a processor chip <NUM> and four memory chips <NUM>, <NUM>, <NUM> and <NUM> all mounted on an underlying interposer <NUM>, which is in turn mounted on a package substrate <NUM>. Additional details of the conventional semiconductor chip package <NUM> and the socket <NUM> may be understood by referring now also to <FIG> which is a sectional view of <FIG> taken at section <NUM>-<NUM>. Note that because of the location of section <NUM>-<NUM>, the semiconductor chip <NUM> and the semiconductor chips <NUM> and <NUM> are shown in section along with the underlying interposer <NUM>, the package substrate <NUM>, the socket <NUM> and the system board <NUM>. In this illustrative conventional arrangement, the socket <NUM> can be a BGA socket that has a particular footprint or area and the package substrate <NUM> is sized to fit within the footprint of the socket <NUM>. The conventional package <NUM> only utilizes four memory chips <NUM>, <NUM>, <NUM> and <NUM> in a <NUM>. 5D arrangement and with the use of the interposer <NUM> to provide electrical pathways between the chips <NUM>, <NUM>, <NUM> and <NUM> and the chip <NUM>. The interposer <NUM> is constructed of a silicon substrate and provided with plural interconnects <NUM>, which are typically solder balls or bumps and plural through-substrate conductors or vias <NUM> that are designed to connect from the bumps <NUM> up to respective solder bumps <NUM> of the chips <NUM> and <NUM> and additional solder bumps <NUM> of the semiconductor chip <NUM>. The chip <NUM> and the chips <NUM>, <NUM>, <NUM> and <NUM> have particular sizes and footprints which can be changed over time, albeit at significant effort and expense. The package substrate <NUM> further includes plural interconnects <NUM>, which are solder balls in this illustrative conventional arrangement.

A new exemplary arrangement of a semiconductor chip device <NUM> can be understood by referring now to <FIG> is a plan view like <FIG>, but showing the exemplary new semiconductor chip device <NUM> positioned in the aforementioned socket <NUM> of the system board <NUM> and <FIG> is a sectional view of <FIG> taken at section <NUM>-<NUM>. Note that because of the location of section <NUM>-<NUM>, the chips <NUM> and <NUM>, the dummy component <NUM> as well as the chip <NUM> of the reconstituted package <NUM> are shown in section. Here, the chip device <NUM> includes the semiconductor chip <NUM> (shown in dashed for reasons to be explained in a moment), as well as the semiconductor chips <NUM>, <NUM>, <NUM> and <NUM> and two or more additional chips <NUM> and <NUM> and optional dummy components <NUM> and <NUM> coupled together in a reconstituted package <NUM>. The reconstituted package <NUM> is, in turn, mounted on an underlying circuit board <NUM>, which can be a package substrate <NUM> or other. The circuit board <NUM> is preferably constructed to have a footprint that corresponds to the footprint of the socket <NUM>. However, by using the reconstituted package <NUM>, more than just the four memory chips <NUM>, <NUM>, <NUM> and <NUM>, i.e., the chips <NUM>, <NUM>, <NUM> and <NUM> plus the chips <NUM> and <NUM>, can be grouped together with the chip <NUM> but with the same package footprint as the conventional package <NUM> shown in <FIG>. As noted above briefly, the chip <NUM> is shown in dashed because it is positioned beneath the chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> in the reconstituted package <NUM> and thus is not strictly visible in <FIG>, but of course is visible in section in <FIG>. Note that by positioning the chip <NUM> beneath the chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> and by at least partially overlapping the chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> laterally with the chip <NUM>, the additional memory chips <NUM> and <NUM> can be grouped with the chip <NUM> in the same overall footprint for a package. Here the chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> number six and are arranged symmetrically around the perimeter of the chip <NUM>. However, other numbers and symmetric or asymmetric arrangements are possible.

As shown in <FIG>, the reconstituted package <NUM> includes an interposer <NUM> composed of silicon, germanium, silicon-on-insulator or other interposer materials. The interposer <NUM> electrically interfaces with the circuit board <NUM> by way of plural I/Os <NUM>, which can be solder bumps, balls or other types of interconnect structures. To provide stress relief, a lower surface of the interposer <NUM> can include a polymer layer <NUM> composed of polybenzoxazoles, although other polymeric materials could be used, such as benzocyclobutene, high or low temperature polyimide or other polymers. Plural through substrate vias (TSV) <NUM> are formed in the interposer <NUM> and electrically connected to the I/Os <NUM>. Underbump metallization (UBM) <NUM> is preferably formed on the lower ends of the TSVs <NUM>. The UBM <NUM> can be constructed of a variety of metals that provide solder adhesion, barrier and dielectric adhesion properties. One arrangement includes a barrier/adhesion layer of Ti-W and copper followed by a copper layer, a nickel layer and another copper layer to interface with solder. A metallization stack <NUM> is formed on the interposer <NUM> and consists of one or more layers of conductor traces <NUM> and conductive vias <NUM>. The various traces <NUM> and vias <NUM> are interspersed with plural dielectric layers <NUM> composed of silicon oxide or other types of dielectric materials deposited by CVD with or without plasma enhancement. The semiconductor chip <NUM> is mounted on the metallization stack <NUM> and an interconnect portion <NUM> thereof is bonded to not only some of the dielectric of the metallization stack <NUM> but also to some of the conductor traces <NUM> by way of an oxide hybrid bond process to be described in more detail below.

The semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> can be any of a variety of integrated circuits. A non-exhaustive list of examples includes microprocessors, graphics processing units, application processing units that combines aspects of both, memory devices, an application integrated specific circuit or other. In one arrangement, the semiconductor chip <NUM> can be a processor and the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> can be memory chips, such as DRAM, SRAM or other. The circuit board <NUM> can be organic or ceramic and single, or more commonly, multilayer. Variations include package substrates, system boards, daughter boards, circuit cards and others.

The semiconductor chip <NUM> is encased in a dielectric layer <NUM> which is preferably composed of silicon oxide deposited by low temperature PECVD or another suitable process. Through dielectric vias (TDVs) <NUM> are formed in the dielectric film <NUM> and connected electrically with some of the traces <NUM> of the metallization stack <NUM> and also to respective I/Os <NUM> and <NUM> of the chips <NUM> and <NUM>. Additional details of the metallurgical connection between the I/Os <NUM> and <NUM> and through dielectric vias <NUM> will be described in conjunction with a subsequent figure. The gaps between the semiconductor chips <NUM> and <NUM> and the dielectric film <NUM> can be filled with an underfill <NUM> which can be well-known polymeric underfill materials. The dummy component <NUM> can be a substrate of silicon, germanium, or other type of semiconductor or even a dielectric material and serves as a heat transfer avenue for conducting heat away from the chip <NUM> and other components of the reconstituted package <NUM>. The dummy component <NUM> can be secured to the dielectric film <NUM> by adhesives, oxide-oxide bonds or other types of joining techniques. Finally, the chips <NUM> and <NUM> and the dummy component <NUM> are at least partially encased in a molding layer <NUM> that is roughly coterminous vertically with the upper surfaces of the chips <NUM>, <NUM> and the dummy component <NUM>. In an exemplary arrangement the material(s) for the molding layer <NUM> can have a molding temperature of about <NUM>. Two commercial variants are Sumitomo EME-G750 and G760.

The circuit board <NUM> can interface electrically with the socket <NUM> by way of the illustrated solder balls <NUM>, optionally, pin grid arrays or land grid arrays or even other types of board to socket connections can be used. Indeed, in other arrangements, a socketless connection can be used. The solder balls <NUM>, the I/Os <NUM> and the I/Os <NUM> and <NUM> can be solder structures, conductive pillars or combinations of the two. Well-known solder compositions, such as tin-silver, tin-silver-copper or others could be used. The TSVs <NUM>, the traces <NUM>, the vias <NUM> and the TDVs <NUM> (and any related disclosed conductors, such as pillars and pads) can be composed of various conductor materials, such as copper, aluminum, silver, gold, platinum, palladium or others.

Note the location of the dashed rectangle <NUM> in <FIG>. The portion of the dashed rectangle <NUM> will be shown at greater magnification in <FIG>. Also note the location of the dashed rectangle <NUM> in <FIG>. The portion of <FIG> circumscribed by the dashed rectangle <NUM> will be shown at greater magnification in <FIG>.

Attention is now turned to <FIG>, which as just noted, is the portion of <FIG> circumscribed by the dashed rectangle <NUM>. As noted above, the interconnect portion <NUM> of the semiconductor chip <NUM> is joined to the metallization stack <NUM> by way of a bumpless oxide hybrid bonding technique. In this regard, an interconnect <NUM> between the semiconductor chip <NUM> and the metallization stack <NUM> is made up of a metallurgical bond between a bond pad <NUM> of the metallization stack <NUM> and a bond pad <NUM> of the chip <NUM>. The interconnect <NUM> is bumpless and one of many. The bond pad <NUM> is connected or otherwise part of the trace <NUM>. In addition, an insulating bonding layer <NUM> joins the chip <NUM> to the metallization stack <NUM> and consists of a glass layer <NUM>, such as SiOx, of the semiconductor chip <NUM> and another glass layer <NUM>, such as silicon oxynitride, of the metallization stack <NUM>. The bond pad <NUM> is positioned in the glass layer <NUM> and the bond pad <NUM> is positioned in the glass layer <NUM>. The bond pad <NUM> and the bond pad <NUM> are metallurgically bonded by way of an anneal process. In this regard, the semiconductor chip <NUM> is brought down or otherwise positioned on the metallization stack <NUM> so that the glass layer <NUM> is on or in very close proximity to the glass silicon oxynitride layer <NUM> and the bond pad <NUM> is on or in very close proximity to the bond pad <NUM>. Thereafter, an anneal process is performed, which produces a transitory thermal expansion of the bond pads <NUM> and <NUM> bringing those structures into physical contact and causing them to form a metallurgical bond that persists even after the chip <NUM> and metallization stack <NUM> are cooled and the bond pads <NUM> and <NUM> contract thermally. Copper performs well in this metal bonding process, but other conductors could be used. There is also formed an oxide/oxynitride bond between the glass layer <NUM> and the glass layer <NUM>.

Additional details of the electrical connections between the TDVs <NUM> and the chips <NUM> and <NUM> can be understood by referring now to <FIG>, which as noted above, is the portion of <FIG> circumscribed by the dashed rectangle <NUM>. Note that a portion of one of the TDVs <NUM> as well as the dielectric layer <NUM> are depicted. A conductive pillar <NUM> is formed on and in ohmic contact with one of the TDVs <NUM> and projects vertically upward beyond a dielectric film <NUM> composed of silicon oxide or other materials. The dielectric film <NUM> includes a suitable opening <NUM> formed therein to accommodate the conductive pillar <NUM>. The conductive pillar <NUM> is advantageously formed by plating material into the opening <NUM> through a suitable mask (not shown) or by way of material deposition and lithographic patterning as desired. The I/O <NUM> of the chip <NUM> is preferably a solder bump or micro bump and metallurgically connected to the conductive pillar <NUM> by way of contact and solder reflow. Optionally, the I/O <NUM> can be another conductive pillar that is joined to the conductive pillar <NUM> by thermal bonding or by a solder cap as desired. As noted above, the underfill <NUM> is deposited between the chip <NUM> and the dielectric layer <NUM> using capillary techniques and to alleviate issues of CTE mismatch. Optionally a molded underfill could be used.

An exemplary process flow for fabricating the reconstituted package <NUM> can be understood by referring now to <FIG>, <FIG>, <FIG>, <FIG> and initially to <FIG>, which is a sectional view depicting the interposer <NUM> following the fabrication of the metallization stack <NUM> thereon. This is preferably, though not necessarily, a wafer level process wherein the reconstituted package <NUM> is part of a reconstituted wafer (not shown) that eventually undergoes singulation. Note that the TSVs <NUM> have been fabricated but the interposer <NUM> has not undergone a thinning process at the backside <NUM> thereof to reveal the TSVs <NUM>. The metallization stack <NUM> can be constructed by using well-known material deposition and patterning processes to establish the conductive traces <NUM>, the vias <NUM> and one or more interlevel dielectric films <NUM>. The TSVs <NUM> can be formed in corresponding openings <NUM> formed in the interposer <NUM> by way of suitable masking and etching. The TSVs <NUM> can be formed by well-known plating or sputtering or other material deposition processes and can be constructed of the conductor materials disclosed elsewhere herein. If desired, one or more barrier films can be deposited in the openings <NUM> prior to the deposition or otherwise placement of the bulk conductor materials. Barriers such as titanium nitride or the like can be used.

Next and as shown in <FIG>, the semiconductor chip <NUM> is mounted on the metallization stack <NUM> by way of the hybrid oxide bonding process involving the interconnect portion <NUM> of the chip <NUM> and the process described above in conjunction with <FIG>. The interposer <NUM> remains unthinned at this point. Next and as shown in <FIG>, the dielectric layer <NUM> is formed on the metallization stack <NUM> and encases the semiconductor chip <NUM> at this point. Plural openings <NUM> are formed in the dielectric film <NUM> in anticipation of subsequent fabrication of the TDVs <NUM>. As shown in <FIG>, the TDVs <NUM> are formed in the openings <NUM> of the dielectric film <NUM> using suitable masking and directional dry etching. The formation of the TDVs <NUM> can be very similar to the formation of the TSVs <NUM> described above. In this regard, following the fabrication of the openings <NUM>, one or more barrier layers, such as titanium nitride, Ti-W or the like can be followed by a two-step plating process involving first the application of a copper seed layer and then a copper bulk layer. Of course if other conductor materials are used then corresponding processes as appropriate for those materials should be used. As noted above, the TDVs <NUM> are formed in ohmic contact with some of the traces <NUM> of the metallization stack <NUM>. At this point, the interposer <NUM> has yet to undergo a thinning process to reveal the TSVs <NUM>.

Next and as shown in <FIG>, the dummy component <NUM> and the semiconductor chips <NUM> and <NUM> are mounted on the dielectric layer <NUM>. As noted above, the dummy component <NUM> can be attached by adhesives, oxide bonds or other types of joining techniques. The connections of the chips <NUM> and <NUM> to the dielectric film <NUM> entail forming the metallurgical bonds depicted above and described in conjunction with <FIG> such that the I/Os <NUM> and <NUM> of the chips <NUM> and <NUM> metallurgically connect to respective of the TDVs <NUM>. The chips <NUM> and <NUM> (and the chips <NUM>, <NUM>, <NUM> and <NUM> shown in <FIG>) are positioned with the desired lateral overlap with the underlying chip <NUM>. The underfill <NUM> can be dispensed by capillary action or can be provided by way of the subsequently deposited molding material layer. Next and as shown in <FIG>, the molding layer <NUM> is molded on the dielectric film <NUM> and at least partially encasing the chips <NUM> and <NUM> and the dummy component <NUM>. Of course it should be understood that the molding material <NUM> not only partially encases the chips <NUM> and <NUM> and the dummy component <NUM> visible in <FIG> but also the other chips <NUM>, <NUM>, <NUM>, <NUM> and the other dummy component <NUM> depicted in <FIG>. A subsequent grinding process is performed on the molding layer <NUM> in order to expose upper surfaces of the chips <NUM> and <NUM> and the dummy component <NUM> to, among other reasons, enable a heat spreader (not shown) to be mounted on and in thermal contact with the chips <NUM>, <NUM> and the dummy component <NUM> and dummy component <NUM> shown in <FIG>. Note that at this stage the interposer <NUM> has yet to undergo a thinning process.

Next and as shown in <FIG>, a temporary carrier wafer <NUM> is mounted to the molding layer <NUM> to provide structural support for the thinning of the interposer <NUM> necessary to reveal the TSVs <NUM> thereof. The carrier wafer <NUM> can be constructed of silicon, other semiconductors, various glasses and can be connected to the molding layer <NUM> by way of heat or light activated adhesives or even two-sided tape that can be undone later. Following the thinning of the interposer <NUM> and the reveal of the TSVs <NUM>, the polymer layer <NUM> can be applied using well-known spin deposition and baking techniques. The polymer layer <NUM> can be constructed with photosensitive materials so that suitable openings can be lithographically patterned therein in order to facilitate the subsequent fabrication of the UBMs <NUM> and the connection of the I/Os <NUM> thereto. At this point, the reconstituted package <NUM> can be mounted to the circuit board <NUM> by placement thereon and a metallurgical reflow of the I/Os <NUM>.

Claim 1:
A semiconductor chip device, comprising: a reconstituted semiconductor chip package (<NUM>) including an interposer (<NUM>) having a first side and a second and opposite side and a metallization stack (<NUM>) on the first side, a first semiconductor chip (<NUM>) on the metallization stack and at least partially encased by a dielectric layer (<NUM>) on the metallization stack, plural interconnects (<NUM>) positioned between and electrically connecting the first semiconductor chip and the metallization stack, and plural semiconductor chips (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) positioned over and at least partially laterally overlapping the first semiconductor chip (<NUM>),
characterized in that
the dielectric layer (<NUM>) includes an opening (<NUM>) adapted to have a portion of a heat spreader (<NUM>) positioned therein to thermally contact the first semiconductor chip (<NUM>).