Patent Description:
In "A Ka-band digitally-controlled phase shifter with sub-degree phase precision" (<NUM>, Institute of Electrical and Electronics Engineers (IEEE), Radio Frequency Integrated Circuits (RFIC) Symposium), a digitally-controlled phase shifter for high-frequency signals such as microwaves, quasi-millimeter waves, or millimeter waves (a digital phase shift circuit) is disclosed. A large number of digital phase shift circuits are actually mounted on a semiconductor substrate in a state in which the digital phase shift circuits are connected in cascade. That is, the digital phase shift circuit is a unitary unit in the configuration of an actual digital phase shifter and a desired function is exhibited by connecting several tens of digital phase shift circuits in cascade. Japanese patents <CIT> and <CIT> provide background information concerning the present invention.

When the configuration of the digital phase shifter is a configuration in which the above digital phase shift circuits are connected in a line, the length of the digital phase shifter increases. In order to shorten the length of the digital phase shifter, a configuration in which the configuration of the digital phase shifter is bent using a connection unit such as a bend-type line having a bent structure is conceivable.

Meanwhile, in a digital phase shifter with a configuration in which a large number of digital phase shift circuits are connected in cascade, it is desirable to eliminate a distribution of phase shift amounts. However, a distribution of phase shift amounts is also caused by weak reflections occurring in front of and behind a connection unit in a situation in which suitable input-output impedance matching is achieved in the above-described digital phase shifter configured to be bent using a connection unit such as a bend-type line.

The present invention has been made in view of the above-described circumstances and an objective of the present invention is to provide a digital phase shifter capable of mitigating a distribution of phase shift amounts caused by weak reflections occurring in front of and behind a connection unit.

According to a first aspect of the present invention, there is provided a digital phase shifter including: a plurality of digital phase shift circuit groups in which a plurality of digital phase shift circuits are connected in cascade; and one or more bend-type connection units connected between two digital phase shift circuit groups, wherein each of the digital phase shift circuits includes at least a signal line, a pair of inner lines provided at both sides of the signal line, a pair of outer lines provided outside of the inner lines, a first ground conductor connected to one end of each of the inner lines and the outer lines, a second ground conductor connected to the other end of each of the outer lines, a pair of electronic switches provided between the other ends of the inner lines and the second ground conductor, and a capacitor electrically connected between the signal line and at least one of the first ground conductor and the second ground conductor, wherein each of the digital phase shift circuits is a circuit set in a low-delay mode in which a return current flows through the inner line or a high-delay mode in which a return current flows through the outer line, and wherein at least one of the digital phase shift circuits constituting at least one digital phase shift circuit group is a mitigation circuit configured to mitigate differences in phase shift amounts of the plurality of digital phase shift circuits caused by reflections at the one or more bend-type connection units.

Preferred embodiments are set out in the appendant claims.

According to the present invention, it is possible to mitigate a distribution of phase shift amounts caused by weak reflections occurring in front of and behind a connection unit.

Hereinafter, a digital phase shifter according to an embodiment of the present invention will be described in detail with reference to the drawings. In the drawings referred to below, the dimensions of each member are appropriately changed as necessary and illustrated to facilitate understanding.

<FIG> is a plan view showing a schematic configuration of a digital phase shifter according to an embodiment of the present invention. As shown in <FIG>, a digital phase shifter <NUM> of the present embodiment includes a plurality of digital phase shift circuits <NUM> (<NUM>-<NUM> to <NUM>-<NUM>) and a plurality of connection units <NUM> (<NUM>-<NUM> to <NUM>-<NUM>). In this digital phase shifter <NUM>, the plurality of digital phase shift circuits <NUM> connected in cascade perform a phase shift process for a signal S having a predetermined frequency band. The signal S is a high-frequency signal having a frequency band of microwaves, quasi-millimeter waves, millimeter waves, or the like.

The plurality of digital phase shift circuits <NUM> are electrically connected in cascade. Although an example in which <NUM> digital phase shift circuits <NUM> (<NUM>-<NUM> to <NUM>-<NUM>) are connected in cascade is shown in <FIG>, the number of digital phase shift circuits <NUM> connected in cascade is arbitrary. In the example shown in <FIG>, for convenience of description, the <NUM> digital phase shift circuits <NUM> connected in cascade are referred to as the digital phase shift circuits <NUM>-<NUM>, <NUM>-<NUM>,. , and <NUM>-<NUM> in the order in which the signal S flows. However, a direction in which the signal S flows may be reversed.

Here, the digital phase shift circuits <NUM> constitute a digital phase shift circuit group <NUM> in units of a plurality of digital phase shift circuits <NUM>. Specifically, the <NUM>st to <NUM>th digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> constitute a digital phase shift circuit group <NUM>-<NUM> and the <NUM>th to <NUM>th digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> constitute a digital phase shift circuit group <NUM>-<NUM>. The <NUM>st to <NUM>th digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> constitute a digital phase shift circuit group <NUM>-<NUM> and the <NUM>st to <NUM>th digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> constitute a digital phase shift circuit group <NUM>-<NUM>.

In other words, the digital phase shifter <NUM> includes the digital phase shift circuit group <NUM>-<NUM> in which the plurality of digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> are connected in cascade and the digital phase shift circuit group <NUM>-<NUM> in which the plurality of digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> are connected in cascade. Also, the digital phase shifter <NUM> includes the digital phase shift circuit group <NUM>-<NUM> in which the plurality of digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> are connected in cascade and the digital phase shift circuit group <NUM>-<NUM> in which the plurality of digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> are connected in cascade.

Here, in the present embodiment, at least one of the digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> is a mitigation circuit RC that mitigates a distribution of phase shift amounts caused by weak reflections occurring in front of and behind the connection unit <NUM>. Mitigation circuits RC include a first mitigation circuit RC1 and a second mitigation circuit RC2. The first mitigation circuit RC1 is a digital phase shift circuit <NUM> having a larger phase shift amount than the digital phase shift circuits <NUM> other than the mitigation circuit RC (the first mitigation circuit RC1 and the second mitigation circuit RC2). The first mitigation circuit RC1 is a circuit configured to mitigate a recess portion in the above-described distribution of phase shift amounts (see <FIG>). The second mitigation circuit RC2 is a digital phase shift circuit <NUM> having a smaller phase shift amount than the digital phase shift circuits <NUM> other than the mitigation circuit RC (the first mitigation circuit RC1 and the second mitigation circuit RC2). The second mitigation circuit RC2 is a circuit configured to mitigate a projection portion in the above-described distribution of phase shift amounts (see <FIG>).

In <FIG>, an example in which the digital phase shift circuits <NUM>-<NUM> and <NUM>-<NUM> are used as the mitigation circuit RC is shown. For example, the digital phase shift circuit <NUM>-<NUM> is referred to as the second mitigation circuit RC2 and the digital phase shift circuit <NUM>-<NUM> is referred to as the first mitigation circuit RC1. In addition, details of the specific configuration of the mitigation circuit RC (the first mitigation circuit RC1 and the second mitigation circuit RC2) and which of the digital phase shift circuits <NUM> is the mitigation circuit RC will be described below.

The connection unit <NUM> has a bend-type shape and connects two digital phase shift circuit groups <NUM>. In the example shown in <FIG>, the connection unit <NUM> has a shape of a <NUM>° bend. Specifically, the connection unit <NUM>-<NUM> connects the other end of the digital phase shift circuit group <NUM>-<NUM> to one end of the digital phase shift circuit group <NUM>-<NUM>. The other end of the digital phase shift circuit group <NUM>-<NUM> is opposed to one end to which the signal S of the digital phase shift circuit group <NUM>-<NUM> is input. The connection unit <NUM>-<NUM> connects the other end of the digital phase shift circuit group <NUM>-<NUM> and one end of the digital phase shift circuit group <NUM>-<NUM>. The connection unit <NUM>-<NUM> connects the other end of the digital phase shift circuit group <NUM>-<NUM> and one end of the digital phase shift circuit group <NUM>-<NUM>.

That is, the connection unit <NUM>-<NUM> connects the digital phase shift circuit <NUM>-<NUM> of the digital phase shift circuit group <NUM>-<NUM> to the digital phase shift circuit <NUM>-<NUM> of the digital phase shift circuit group <NUM>-<NUM>. The connection unit <NUM>-<NUM> connects the digital phase shift circuit <NUM>-<NUM> of the digital phase shift circuit group <NUM>-<NUM> to the digital phase shift circuit <NUM>-<NUM> of the digital phase shift circuit group <NUM>-<NUM>. The connection unit <NUM>-<NUM> connects the digital phase shift circuit <NUM>-<NUM> of the digital phase shift circuit group <NUM>-<NUM> to the digital phase shift circuit <NUM>-<NUM> of the digital phase shift circuit group <NUM>-<NUM>.

When the digital phase shift circuit group <NUM>-<NUM> and the digital phase shift circuit group <NUM>-<NUM> are connected by the connection unit <NUM>-<NUM>, the path of the signal S is bent <NUM>°. Also, when the digital phase shift circuit group <NUM>-<NUM> and the digital phase shift circuit group <NUM>-<NUM> are connected by the connection unit <NUM>-<NUM>, the path of the signal S is bent <NUM>°. Likewise, when the digital phase shift circuit group <NUM>-<NUM> and the digital phase shift circuit group <NUM>-<NUM> are connected by the connection unit <NUM>-<NUM>, the path of the signal S is bent <NUM>°. Thus, the digital phase shift circuit groups <NUM>-<NUM> to <NUM>-<NUM> are arranged in parallel to each other and are connected in a meander shape via the connection units <NUM>-<NUM> to <NUM>-<NUM>. In addition, details of the connection unit <NUM> will be described below.

<FIG> is a perspective view showing a configuration of the digital phase shift circuit according to the embodiment of the present invention. As shown in <FIG>, the digital phase shift circuit <NUM> includes a signal line <NUM>, a pair of inner lines <NUM> (a first inner line 2a and a second inner line 2b), a pair of outer lines <NUM> (a first outer line 3a and a second outer line 3b), a pair of ground conductors <NUM> (a first ground conductor 4a and a second ground conductor 4b), a capacitor <NUM>, a plurality of connection conductors <NUM>, four electronic switches <NUM> (a first electronic switch 7a, a second electronic switch 7b, a third electronic switch 7c, and a fourth electronic switch 7d), and a switch control unit <NUM>.

The signal line <NUM> is a linear strip-shaped conductor extending in a predetermined direction. That is, the signal line <NUM> is a long plate-shaped conductor having a certain width W1, a certain thickness, and a predetermined length. In the example shown in <FIG>, the signal S flows through the signal line <NUM> in a direction from the front side to the back side.

The first inner line 2a is a linear strip-shaped conductor. That is, the first inner line 2a is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The first inner line 2a extends in a direction that is the same as the extension direction of the signal line <NUM>. The first inner line 2a is provided parallel to the signal line <NUM> and is separated from one side of the signal line <NUM> (the right side in <FIG>) by a predetermined distance M1.

The second inner line 2b is a linear strip-shaped conductor. That is, the second inner line 2b is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length like the first inner line 2a. The second inner line 2b extends in a direction that is the same as the extension direction of the signal line <NUM>. The second inner line 2b is provided parallel to the signal line <NUM> and is separated from the other side of the signal line <NUM> (the left side in <FIG>) by the predetermined distance M1.

The first outer line 3a is a linear strip-shaped conductor provided at a position farther from the signal line <NUM> than the first inner line 2a at the one side of the signal line <NUM>. The first outer line 3a is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The first outer line 3a is provided parallel to the signal line <NUM> at an interval of a predetermined distance from the signal line <NUM> in a state in which the first inner line 2a is sandwiched between the signal line <NUM> and the first outer line 3a. The first outer line 3a extends in a direction that is the same as the extension direction of the signal line <NUM> like the first inner line 2a and the second inner line 2b.

The second outer line 3b is a linear strip-shaped conductor provided at a position farther from the signal line <NUM> than the second inner line 2b at the other side of the signal line <NUM>. The second outer line 3b is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length like the first outer line 3a. The second outer line 3b is provided in parallel at an interval of a predetermined distance from the signal line <NUM> in a state in which the second inner line 2b is sandwiched between the second outer line 3b and the signal line <NUM>. The second outer line 3b extends in a direction that is the same as the extension direction of the signal line <NUM> like the first inner line 2a and the second inner line 2b.

The first ground conductor 4a is a linear strip-shaped conductor provided at one end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. The first ground conductor 4a is electrically connected to one end of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. The first ground conductor 4a is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length.

The first ground conductor 4a is provided orthogonal to the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b extending in the same direction. The first ground conductor 4a is provided below the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b at an interval of a predetermined distance therefrom.

The first ground conductor 4a is set so that one end (a right end in <FIG>) in the left and right directions has substantially the same position as the right edge of the first outer line 3a. Also, the first ground conductor 4a is set so that the other end (a left end in <FIG>) in the left and right directions has substantially the same position as the left edge of the second outer line 3b.

The second ground conductor 4b is a linear strip-shaped conductor provided at the other end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. The second ground conductor 4b is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length like the first ground conductor 4a.

The second ground conductor 4b is arranged parallel to the first ground conductor 4a and is provided orthogonal to the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b like the first ground conductor 4a. The second ground conductor 4b is provided below the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b at an interval of a predetermined distance therefrom.

The second ground conductor 4b is set so that one end (the right end in <FIG>) in the left and right directions has substantially the same position as the right edge of the first outer line 3a. Also, the second ground conductor 4b is set so that the other end (the left end in <FIG>) in the left and right directions has substantially the same position as the left edge of the second outer line 3b. That is, the second ground conductor 4b has the same position as the first ground conductor 4a in the left and right directions.

The capacitor <NUM> is provided between the other end of the signal line <NUM> and the second ground conductor 4b. For example, the capacitor <NUM> has an upper electrode connected to the signal line <NUM> and a lower electrode electrically connected to the fourth electronic switch 7d. For example, the capacitor <NUM> is a thin film capacitor having a metal insulator metal (MIM) structure. In addition, the capacitor <NUM> has capacitance Ca corresponding to an opposite area of the parallel plate. Here, instead of a parallel flat capacitor, a comb tooth type capacitor may be used as the capacitor <NUM>.

The plurality of connection conductors <NUM> include at least the connection conductors 6a to 6f. The connection conductor 6a is a conductor that electrically and mechanically connects one end of the first inner line 2a and the first ground conductor 4a. For example, the connection conductor 6a is a conductor extending in the up and down direction and has one end (an upper end) connected to the lower surface of the first inner line 2a and the other end (a lower end) connected to the upper surface of the first ground conductor 4a.

The connection conductor 6b is a conductor that electrically and mechanically connects one end of the second inner line 2b and the first ground conductor 4a. For example, the connection conductor 6b is a conductor extending in the up and down direction like the connection conductor 6a. The connection conductor 6b has one end (an upper end) connected to the lower surface of the second inner line 2b and the other end (a lower end) connected to the upper surface of the first ground conductor 4a.

The connection conductor 6c is a conductor that electrically and mechanically connects one end of the first outer line 3a and the first ground conductor 4a. For example, the connection conductor 6c is a conductor extending in the up and down direction. The connection conductor 6c has one end (an upper end) connected to the lower surface at one end of the first outer line 3a and the other end (a lower end) connected to the upper surface of the first ground conductor 4a.

The connection conductor 6d is a conductor that electrically and mechanically connects the other end of the first outer line 3a and the second ground conductor 4b. For example, the connection conductor 6d is a conductor extending in the up and down direction. The connection conductor 6d has one end (an upper end) connected to the lower surface at the other end of the first outer line 3a and the other end (a lower end) connected to the upper surface of the second ground conductor 4b.

The connection conductor 6e is a conductor that electrically and mechanically connects one end of the second outer line 3b and the first ground conductor 4a. For example, the connection conductor 6e is a conductor extending in the up and down direction. The connection conductor 6e has one end (an upper end) connected to the lower surface at one end of the second outer line 3b, and the other end (a lower end) connected to the upper surface of the first ground conductor 4a.

The connection conductor 6f is a conductor that electrically and mechanically connects the other end of the second outer line 3b and the second ground conductor 4b. For example, the connection conductor 6f is a conductor extending in the up and down direction. The connection conductor 6f has one end (an upper end) connected to the lower surface at the other end of the second outer line 3b and the other end (a lower end) connected to the upper surface of the second ground conductor 4b.

The connection conductor <NUM> is a conductor that electrically and mechanically connects the other end of the signal line <NUM> and the upper electrode of the capacitor <NUM>. For example, the connection conductor <NUM> is a conductor extending in the up and down direction. The connection conductor <NUM> has one end (an upper end) connected to the lower surface at the other end of the signal line <NUM> and the other end (a lower end) connected to the upper electrode of the capacitor <NUM>.

The first electronic switch 7a is connected between the other end of the first inner line 2a and the second ground conductor 4b. The first electronic switch 7a is, for example, a metal-oxide-semiconductor (MOS)-type field-effect transistor (FET). The first electronic switch 7a has a drain terminal electrically connected to the other end of the first inner line 2a, a source terminal electrically connected to the second ground conductor 4b, and a gate terminal electrically connected to the switch control unit <NUM>.

The first electronic switch 7a is controlled in a closed state or an open state on the basis of a gate signal input from the switch control unit <NUM> to the gate terminal. The closed state is a state in which the drain terminal and the source terminal are electrically connected. The open state is a state in which the drain terminal and the source terminal are not electrically connected and the electrical connection is disconnected. The first electronic switch 7a, a control of the switch control unit <NUM>, is switched in an electrically connected state in which the other end of the first inner line 2a is electrically connected to the second ground conductor 4b or an electrically disconnected state in which the other end of the first inner line 2a is electrically disconnected to the second ground conductor 4b.

The second electronic switch 7b is connected between the other end of the second inner line 2b and the second ground conductor 4b. The second electronic switch 7b is, for example, a MOS-type FET. The second electronic switch 7b has a drain terminal connected to the other end of the second inner line 2b, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch control unit <NUM>.

The second electronic switch 7b is controlled in a closed state or an open state on the basis of a gate signal input from the switch control unit <NUM> to the gate terminal. The second electronic switch 7b, by a control of the switch control unit <NUM>, is switched in an electrically connected state in which the other end of the second inner line 2b is electrically connected to the second ground conductor 4b or an electrically disconnected state in which the other end of the second inner line 2b is electrically disconnected to the second ground conductor 4b.

The third electronic switch 7c is connected between the other end of the signal line <NUM> and the second ground conductor 4b. The third electronic switch 7c is, for example, a MOS-type FET, and has a drain terminal connected to the other end of the signal line <NUM>, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch control unit <NUM>. Although the third electronic switch 7c is provided on the other end side of the signal line <NUM> in the example shown in <FIG>, the present invention is not limited thereto and the third electronic switch 7c may be provided on one end side of the signal line <NUM>. In addition, the third electronic switch 7c may not be used if it is not necessary.

The third electronic switch 7c is controlled in a closed state or an open state on the basis of a gate signal input from the switch control unit <NUM> to the gate terminal. The third electronic switch 7c, by a control of the switch control unit <NUM>, is switched in an electrically connected state in which the other end of the signal line <NUM> are electrically connected to the second ground conductor 4b or an electrically disconnected state in which the other end of the signal line <NUM> are electrically disconnected to the second ground conductor 4b.

The fourth electronic switch 7d is connected in series to the capacitor <NUM> between the other end of the signal line <NUM> and the second ground conductor 4b. The fourth electronic switch 7d is, for example, a MOS-type FET. In the example shown in <FIG>, the fourth electronic switch 7d has a drain terminal connected to the lower electrode of the capacitor <NUM>, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch control unit <NUM>.

The fourth electronic switch 7d is controlled in a closed state or an open state on the basis of a gate signal input from the switch control unit <NUM> to the gate terminal. The fourth electronic switch 7d, by a control of the switch control unit <NUM>, is switched in an electrically connected state in which the lower electrode of the capacitor <NUM> are electrically connected to the second ground conductor 4b or an electrically disconnected state in which the lower electrode of the capacitor <NUM> are electrically disconnected to the second ground conductor 4b.

The switch control unit <NUM> is a control circuit that controls the first electronic switch 7a, the second electronic switch 7b, the third electronic switch 7c, and the fourth electronic switch 7d, which are a plurality of electronic switches <NUM>. For example, the switch control unit <NUM> includes four output ports. The switch control unit <NUM> individually controls each of the plurality of electronic switches <NUM> in an open state or a closed state by outputting separate gate signals from the output ports and supplying the gate signals to the gate terminals of the plurality of electronic switches <NUM>.

Although a schematic diagram in which the digital phase shift circuit <NUM> is viewed in perspective so that the mechanical structure of the digital phase shift circuit <NUM> is easily understood is shown in <FIG>, the actual digital phase shift circuit <NUM> is formed as a multilayer structure using semiconductor manufacturing technology.

As an example, in the digital phase shift circuit <NUM>, the signal line <NUM>, the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b are formed on the first conductive layer. The first ground conductor 4a and the second ground conductor 4b are formed on a second conductive layer opposed to the first conductive layer in a state in which an insulating layer is sandwiched. A component formed on the first conductive layer and a component formed on the second conductive layer are connected to each other through via-holes. The plurality of connection conductors <NUM> correspond to the via-holes buried inside of the insulating layer.

Next, an operation of the digital phase shift circuit <NUM> in the present embodiment will be described. The digital phase shift circuit <NUM> has a high-delay mode and a low-delay mode as operating modes. The digital phase shift circuit <NUM> operates in the high-delay mode or the low-delay mode.

<FIG> is a diagram for describing the high-delay mode of the digital phase shift circuit according to the embodiment of the present invention. The high-delay mode is a mode in which a first phase difference is generated in the signal S. In the high-delay mode, as shown in <FIG>, the first electronic switch 7a and the second electronic switch 7b are controlled in the open state and the fourth electronic switch 7d is controlled in the closed state.

The first electronic switch 7a is controlled in the open state and therefore the electrical connection between the other end of the first inner line 2a and the second ground conductor 4b is disconnected. The second electronic switch 7b is controlled in the open state and therefore the electrical connection between the other end of the second inner line 2b and the second ground conductor 4b is disconnected. The fourth electronic switch 7d is controlled in the closed state and therefore the other end of the signal line <NUM> is connected to the second ground conductor 4b via the capacitor <NUM>.

When the signal S propagates through the signal line <NUM> in a direction from the input end (the other end) to the output end (one end), the return current R1 flows from the one end to the other end in a direction opposite that of the signal S. In the high-delay mode, because the first electronic switch 7a and the second electronic switch 7b are in the open state, the return current R1 mainly flows through the first outer line 3a and the second outer line 3b as shown in <FIG>.

Because the return current R1 flows through the first outer line 3a and the second outer line 3b in the high-delay mode, the inductance value L is larger than that in the low-delay mode. In the high-delay mode, it is possible to obtain a delay amount larger than that in the low-delay mode. Also, because the other end of the signal line <NUM> and the second ground conductor 4b are electrically connected by the capacitor <NUM> when the fourth electronic switch 7d is in the closed state, the capacitance value C of the digital phase shift circuit <NUM> is also large. Consequently, in the high-delay mode, it is possible to obtain a delay amount larger than that in the low-delay mode.

<FIG> is a diagram for describing the low-delay mode of the digital phase shift circuit according to the embodiment of the present invention. The low-delay mode is a mode in which a second phase difference smaller than a first phase difference is generated in the signal S. In the low-delay mode, as shown in <FIG>, the first electronic switch 7a and the second electronic switch 7b are controlled in a closed state and the fourth electronic switch 7d is controlled in an open state.

When the first electronic switch 7a is controlled in the closed state, the other end of the first inner line 2a and the second ground conductor 4b are electrically connected. When the second electronic switch 7b is controlled in the closed state, the other end of the second inner line 2b and the second ground conductor 4b are electrically connected.

When the signal S propagates through the signal line <NUM> in a direction from the input end (the other end) to the output end (one end), the return current R2 flows from the one end to the other end in a direction opposite that of the signal S. In the low-delay mode, because the first electronic switch 7a and the second electronic switch 7b are in the closed state, the return current R2 mainly flows through the first inner line 2a and the second inner line 2b as shown in <FIG>.

Because the return current R2 flows through the first inner line 2a and the second inner line 2b in the low-delay mode, the inductance value L is smaller than that in the high-delay mode. The delay amount in the low-delay mode is smaller than the delay amount in the high-delay mode. Although the capacitor <NUM> is connected to the other end of the signal line <NUM>, because the fourth electronic switch 7d is in the open state, the capacitance of capacitor <NUM> is non-functional (invisible from the signal line <NUM>) and there is only parasitic capacitance that is significantly less than the capacitance of the capacitor <NUM>. Consequently, in the low-delay mode, it is possible to obtain a delay amount smaller than that in the high-delay mode.

Here, in the low-delay mode, the loss of the signal line <NUM> can be intentionally increased by controlling the third electronic switch 7c in a closed state. This is to make the loss of the high-frequency signal in the low-delay mode substantially equal to the loss of the high-frequency signal in the high-delay mode.

That is, the loss of the high-frequency signal in the low-delay mode is clearly less than the loss of the high-frequency signal in the high-delay mode. This loss difference causes an amplitude difference of the high-frequency signal output from the digital phase shift circuit <NUM> when the operation mode is switched between the low-delay mode and the high-delay mode. In relation to this circumstance, the digital phase shift circuit <NUM> can eliminate the above-described amplitude difference by controlling the third electronic switch 7c in the closed state in the low-delay mode.

<FIG> are diagrams for describing the first mitigation circuit of the mitigation circuits according to the embodiment of the present invention. The basic configuration of the first mitigation circuit RC1 is substantially similar to the digital phase shift circuit <NUM> (hereinafter referred to as a "standard digital phase shift circuit ST") other than the mitigation circuit RC (the first mitigation circuit RC1 and the second mitigation circuit RC2). However, the configuration of the first mitigation circuit RC1 is slightly different from that of the standard digital phase shift circuit ST so that the first mitigation circuit RC1 has a larger phase shift amount than the standard digital phase shift circuit.

Specifically, the first mitigation circuit RC1 has a configuration that satisfies at least one of the conditions listed below.

<FIG> is a diagram showing the first mitigation circuit RC1 satisfying the above "condition <NUM>. " A length Pa of the first mitigation circuit RC1 shown in <FIG> (the length of the signal line <NUM>, the inner line <NUM>, the outer line <NUM>, or the like) is longer than a length P of the standard digital phase shift circuit ST.

<FIG> is a diagram showing the first mitigation circuit RC1 satisfying the above-described "condition <NUM>. " In the first mitigation circuit RC1 shown in <FIG>, a distance Qa between the signal line <NUM> and the inner line <NUM> (the first inner line 2a and the second inner line 2b) is shorter than a distance Q between the signal line <NUM> and the inner line <NUM> (the first inner line 2a and the second inner line 2b) in the standard digital phase shift circuit ST.

<FIG> is a diagram showing the first mitigation circuit RC1 satisfying the above-described "condition <NUM>. " In the first mitigation circuit RC1 shown in <FIG>, a distance Ra between the signal line <NUM> and the outer line <NUM> (the first outer line 3a and the second outer line 3b) is longer than a distance R between the signal line <NUM> and the outer line <NUM> (the first outer line 3a and the second outer line 3b) in the standard digital phase shift circuit ST.

<FIG> is a diagram showing the first mitigation circuit RC1 satisfying the above-described "condition <NUM>. " A size of the capacitor <NUM> in the first mitigation circuit RC1 shown in <FIG> is larger than that of the capacitor <NUM> in the standard digital phase shift circuit ST. Although not shown, sizes of the first electronic switch 7a and the second electronic switch 7b (see <FIG>) of the first mitigation circuit RC1 satisfying the above-described "condition <NUM>" are larger than those of the first electronic switch 7a and the second electronic switch 7b of the standard digital phase shift circuit ST.

As described above, the first mitigation circuit RC1 has a larger phase shift amount than the standard digital phase shift circuit ST. Thus, it is possible to increase the phase shift amount using the first mitigation circuit RC1 instead of the standard digital phase shift circuit ST. Therefore, for example, when a distribution of phase shift amounts caused by weak reflections occurring in front of and behind the connection unit <NUM> has a recess portion (see <FIG>), the first mitigation circuit RC1 can be used to mitigate the recess portion.

<FIG> are diagrams for describing the second mitigation circuit of the mitigation circuits according to the embodiment of the present invention. A basic configuration of the second mitigation circuit RC2 is substantially similar to that of the standard digital phase shift circuit ST like the first mitigation circuit RC1. However, a configuration of the second mitigation circuit RC2 is slightly different from that of the standard digital phase shift circuit ST so that the second mitigation circuit RC2 has a smaller phase shift amount than the standard digital phase shift circuit ST.

Specifically, the second mitigation circuit RC2 has a configuration that satisfies at least one of the conditions listed below.

<FIG> is a diagram showing the second mitigation circuit RC2 satisfying the above "condition <NUM>. " A length Pa of the second mitigation circuit RC2 shown in <FIG> (the length of the signal line <NUM>, the inner line <NUM>, the outer line <NUM>, or the like) is shorter than a length P of the standard digital phase shift circuit ST.

<FIG> is a diagram showing the second mitigation circuit RC2 satisfying the above-described "condition <NUM>. " In the second mitigation circuit RC2 shown in <FIG>, a distance Qa between the signal line <NUM> and the inner line <NUM> (the first inner line 2a and the second inner line 2b) is longer than a distance Q between the signal line <NUM> and the inner line <NUM> (the first inner line 2a and the second inner line 2b) in the standard digital phase shift circuit ST.

<FIG> is a diagram showing the second mitigation circuit RC2 satisfying the above-described "condition <NUM>. " In the second mitigation circuit RC2 shown in <FIG>, a distance Ra between the signal line <NUM> and the outer line <NUM> (the first outer line 3a and the second outer line 3b) is shorter than a distance R between the signal line <NUM> and the outer line <NUM> (the first outer line 3a and the second outer line 3b) in the standard digital phase shift circuit ST.

<FIG> is a diagram showing the second mitigation circuit RC2 satisfying the above-described "condition <NUM>. " A size of the capacitor <NUM> in the second mitigation circuit RC2 shown in <FIG> is smaller than that of the capacitor <NUM> in the standard digital phase shift circuit ST. Although not shown, sizes of the first electronic switch 7a and the second electronic switch 7b (see <FIG>) of the second mitigation circuit RC2 satisfying the above-described "condition <NUM>" are smaller than those of the first electronic switch 7a and the second electronic switch 7b of the standard digital phase shift circuit ST.

As described above, the second mitigation circuit RC2 has a smaller phase shift amount than the standard digital phase shift circuit ST. Thus, it is possible to decrease the phase shift amount using the second mitigation circuit RC2 instead of the standard digital phase shift circuit ST. Therefore, for example, when a distribution of phase shift amounts caused by weak reflections occurring in front of and behind the connection unit <NUM> has a projection portion (see <FIG>), the second mitigation circuit RC2 can be used to mitigate the projection portion.

<FIG> is a plan view showing a main configuration of the connection unit according to the embodiment of the present invention. <FIG> is a cross-sectional view taken along line A-A in <FIG>. In addition, the digital phase shifter <NUM> of the present embodiment includes three connection units <NUM> (connection units <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>). The connection unit <NUM>-<NUM> will be described here because the three connection units <NUM> have similar configurations. As shown in <FIG> and <FIG>, the connection unit <NUM>-<NUM> includes a first connection line <NUM>, a second connection line <NUM>, a third connection line <NUM>, a first ground layer <NUM>, and a second ground layer <NUM>.

The first connection line <NUM> is, for example, a long plate-shaped conductor having a certain width W2, a certain thickness, and a predetermined length. The first connection line <NUM> connects the signal line <NUM> of the digital phase shift circuit <NUM>-<NUM> and the signal line <NUM> of the digital phase shift circuit <NUM>-<NUM>. The signal S output from the signal line <NUM> of the digital phase shift circuit <NUM>-<NUM> is input to the signal line <NUM> of the digital phase shift circuit <NUM>-<NUM> via the first connection line <NUM>. In addition, the width W2 of the first connection line <NUM> may be similar to the width W1 of the signal line <NUM> or may be wider than the width W1.

The second connection line <NUM> is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length. The second connection line <NUM> extends in a direction that is the same as the extension direction of the signal line <NUM>. The second connection line <NUM> is provided parallel to the first connection line <NUM> and is separated by a predetermined distance M2. Specifically, the second connection line <NUM> is arranged at both sides of the first connection line <NUM> at an interval of a predetermined distance M2 from the first connection line <NUM>. In addition, in the following description, the second connection line <NUM> arranged at one side of the first connection line <NUM> may be referred to as a "second connection line 22a" and the second connection line <NUM> arranged at the other side of the first connection line <NUM> may be referred to as a "second connection line 22b.

The predetermined distance M2 may be equivalent to the predetermined distance M1 or may be shorter than the predetermined distance M1. For example, when the predetermined distance M1 is <NUM>, the predetermined distance M2 may be set to less than <NUM>. More preferably, the predetermined distance M2 is, for example, <NUM> or <NUM> or less, and it is desirable to make the second connection line <NUM> as close as possible to the first connection line <NUM>. In the present embodiment, the second connection line <NUM> may be made close to the manufacturing limit or near the manufacturing limit with respect to the first connection line <NUM>.

The second connection line <NUM> connects the inner line <NUM> of the digital phase shift circuit <NUM>-<NUM> and the inner line <NUM> of the digital phase shift circuit <NUM>-<NUM>. In the example shown in <FIG>, the second connection line 22a has one end connected to the first inner line 2a of the digital phase shift circuit <NUM>-<NUM> and the other end connected to the first inner line 2a of the digital phase shift circuit <NUM>-<NUM>. The second connection line 22b has one end connected to the second inner line 2b of the digital phase shift circuit <NUM>-<NUM> and the other end connected to the second inner line 2b of the digital phase shift circuit <NUM>-<NUM>.

The third connection lines <NUM> are strip-shaped conductors provided farther from the first connection line <NUM> than the second connection line <NUM> at both sides that are one side and the other side of the first connection line <NUM>. The third connection line <NUM> is provided parallel to the first connection line <NUM> at an interval of a predetermined distance in a state in which the second connection line <NUM> is sandwiched between the first connection line <NUM> and the third connection line <NUM>. In addition, in the following description, the third connection line <NUM> arranged at the one side of the first connection line <NUM> may be referred to as a "third connection line 23a" and the third connection line <NUM> arranged at the other side of the first connection line <NUM> may be referred to as a "third connection line 23b.

The third connection line <NUM> connects the outer line <NUM> of the digital phase shift circuit <NUM>-<NUM> and the outer line <NUM> of the digital phase shift circuit <NUM>-<NUM>. In the example shown in <FIG>, the third connection line 23a has one end connected to the first outer line 3a of the digital phase shift circuit <NUM>-<NUM> and the other end connected to the first outer line 3a of the digital phase shift circuit <NUM>-<NUM>. The third connection line 23b has one end connected to the second outer line 3b of the digital phase shift circuit <NUM>-<NUM> and the other end connected to the second outer line 3b of the digital phase shift circuit <NUM>-<NUM>.

The first ground layer <NUM> is provided above the first connection line <NUM> and the second connection line <NUM> at an interval of a predetermined distance therefrom. In the first ground layer <NUM>, the width of the first ground layer <NUM> preferably extends to at least one side surface <NUM> of each second connection line <NUM>. The side surface <NUM> is a side surface opposed to the side where the first connection line <NUM> is arranged.

The first ground layer <NUM> is connected to each of the second connection line 22a and the second connection line 22b via via-holes <NUM>. As shown in <FIG>, a plurality of via-holes <NUM> are arrayed along the second connection line 22a and a plurality of via-holes <NUM> are arrayed along the second connection line 22b.

The second ground layer <NUM> is provided below the first connection line <NUM> and the second connection line <NUM> at an interval of a predetermined distance therefrom. In the second ground layer <NUM>, the width of the second ground layer <NUM> preferably extends to at least one side surface <NUM> of each second connection line <NUM>.

The second ground layer <NUM> is connected to each of the second connection line 22a and the second connection line 22b via via-holes <NUM>. Like the via-holes <NUM>, a plurality of via-holes <NUM> are arrayed along the second connection line 22a and a plurality of via-holes <NUM> are arrayed along the second connection line 22b.

<FIG> is a cross-sectional view showing a modified example of the connection unit according to the embodiment of the present invention. As shown in <FIG>, the connection unit <NUM> may have the first ground layer <NUM> extending above the third connection line <NUM> and the second ground layer <NUM> extending below the third connection line <NUM>.

In this modified example, the first ground layer <NUM> is connected to each of the second connection line 22a and the second connection line 22b via the via-holes <NUM> and is connected to each of the third connection line 23a and the third connection line 23b via via-holes <NUM>. In addition, in the configuration illustrated in <FIG>, a plurality of via-holes <NUM> are arrayed along the third connection line 23a and a plurality of via-holes <NUM> are arrayed along the third connection line 23b.

Also, the second ground layer <NUM> is connected to each of the second connection line 22a and the second connection line 22b via via-holes <NUM> and is connected to each of the third connection line 23a and the third connection line 23b via via-holes <NUM>. In addition, in the configuration illustrated in <FIG>, like the via-holes <NUM>, a plurality of via-holes <NUM> are arrayed along the third connection line 23a and a plurality of via-holes <NUM> are arrayed along the third connection line 23b.

Although the connection unit <NUM>-<NUM> has a first ground layer <NUM> and a second ground layer <NUM> in the example shown in <FIG>, the present invention is not limited thereto. At least one of the first ground layer <NUM> and the second ground layer <NUM> may be provided. That is, a ground layer may be arranged in at least one of an upward direction and a downward direction of the first connection line <NUM>.

<FIG> are diagrams showing an example of a distribution of phase shift amounts generated in a digital phase shifter. The phase shift amount distributions shown in <FIG> are for a digital phase shift circuit in which the mitigation circuit RC (the first mitigation circuit RC1 and the second mitigation circuit RC2) is not provided. In addition, in the graphs shown in <FIG>, the horizontal axis represents a number ("<NUM>" to "<NUM>") of the digital phase shift circuit <NUM> and the vertical axis represents a phase shift amount for each digital phase shift circuit <NUM>.

The phase shift amount distributions shown in <FIG> are obtained when switching control is sequentially performed for the low-delay mode in the order of the digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> from the state where all the digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> are set in the high-delay mode. The phase shift amount distribution shown in <FIG> is that of a case where the frequency of the signal S is <NUM> [GHz]. The phase shift amount distribution shown in <FIG> is that of a case where the frequency of the signal S is <NUM> [GHz]. The phase shift amount distribution shown in <FIG> is that of a case where the frequency of the signal S is <NUM> [GHz]. The ideal characteristic of the digital phase shifter <NUM> is that the upper part of each of the graphs shown in <FIG> is flat (there is no distribution of phase shift amounts).

In addition, the control of the digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> starts from the digital phase shift circuit <NUM>-<NUM> and is performed sequentially in the connection order of the digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM>. This is because the capacitor <NUM> is provided on (connected to) (the ground conductor of) a side opposed to the side to which the digital phase shift circuit <NUM>-(n+<NUM>) in the digital phase shift circuit <NUM>-n (n is an integer satisfying <NUM>≤n≤<NUM>) is connected.

That is, among the digital phase shift circuits <NUM> constituting the digital phase shift circuit groups <NUM>-<NUM> to <NUM>-<NUM> connected in a meander shape, digital phase shift circuits located at an outermost side are the digital phase shift circuit <NUM>-<NUM> and the digital phase shift circuit <NUM>-<NUM>. Control is started from the digital phase shift circuit <NUM>-<NUM> in which the capacitor <NUM> is provided on a side opposed to the side to which the digital phase shift circuit <NUM>-<NUM> is connected within the digital phase shift circuit <NUM>-<NUM> and the digital phase shift circuit <NUM>-<NUM>.

In addition, in <FIG>, a dashed line denoted by reference sign P1 indicates the position of the connection unit <NUM>-<NUM>, a dashed line denoted by reference sign P2 indicates the position of the connection unit <NUM>-<NUM>, and a dashed line denoted by reference sign P3 indicates the position of the connection unit <NUM>-<NUM>.

First, referring to <FIG>, it can be seen that a recess portion occurs in the distribution of phase shift amounts between the connection units <NUM> (between the positions P1 and P2 and between the positions P2 and P3). Also, it can be seen that the phase shift amount has increased in front of the connection unit <NUM> (in front of the positions P1, P2, and P3). In addition, the front side of the connection unit <NUM> is the front side in the control direction of the digital phase shift circuit <NUM> (a direction from the digital phase shift circuit <NUM>-<NUM> to the digital phase shift circuit <NUM>-<NUM>).

Thus, when the frequency of the signal S is <NUM> [GHz], it is desirable to designate at least one of the digital phase shift circuits <NUM> constituting at least one digital phase shift circuit group <NUM> (the digital phase shift circuit groups <NUM>-<NUM> and <NUM>-<NUM>) having both ends connected to the connection unit <NUM> as the first mitigation circuit RC1. Also, it is desirable to designate at least one digital phase shift circuit <NUM> (preferably, at least two or more digital phase shift circuit <NUM>) located in front of at least one connection unit <NUM> as the second mitigation circuit RC2.

For example, in the digital phase shifter <NUM> shown in <FIG>, it is desirable to designate the digital phase shift circuits <NUM>-<NUM> and <NUM>-<NUM> constituting the digital phase shift circuit group <NUM>-<NUM> and the digital phase shift circuits <NUM>-<NUM> and <NUM>-<NUM> constituting the digital phase shift circuit group <NUM>-<NUM> as the first mitigation circuit RC1. Also, it is desirable to designate the digital phase shift circuits <NUM>-<NUM> and <NUM>-<NUM> located in front of the connection unit <NUM>-<NUM>, the digital phase shift circuits <NUM>-<NUM> and <NUM>-<NUM> located in front of the connection unit <NUM>-<NUM>, and the digital phase shift circuits <NUM>-<NUM> and <NUM>-<NUM> located in front of the connection unit <NUM>-<NUM> as the second mitigation circuit RC2.

Next, referring to <FIG>, it can be seen that the phase shift amount is significantly decreased behind the connection unit <NUM> (behind the positions P1, P2, and P3) and the phase shift amount is increased in front of the connection unit <NUM> (in front of the positions P1, P2, P3). In addition, the rear side of the connection unit <NUM> is the rear side in the control direction of the digital phase shift circuit <NUM> (a direction from the digital phase shift circuit <NUM>-<NUM> to the digital phase shift circuit <NUM>-<NUM>).

Thus, when the frequency of the signal S is <NUM> [GHz], it is desirable to designate at least one of the digital phase shift circuits <NUM> located behind the connection unit <NUM> as the first mitigation circuit RC1. Also, it is desirable to designate at least one digital phase shift circuit <NUM> (preferably, at least three or more digital phase shift circuits <NUM>) located in front of at least one connection unit <NUM> as the second mitigation circuit RC2.

For example, in the digital phase shifter <NUM> shown in <FIG>, it is desirable to designate the digital phase shift circuit <NUM>-<NUM> located behind the connection unit <NUM>-<NUM>, the digital phase shift circuit <NUM>-<NUM> located behind the connection unit <NUM>-<NUM>, and the digital phase shift circuit <NUM>-<NUM> located behind the connection unit <NUM>-<NUM> as the first mitigation circuit RC1. Also, it is desirable to designate the digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> located in front of the connection unit <NUM>-<NUM>, the digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> located in front of the connection unit <NUM>-<NUM>, and the digital phase shift circuits <NUM>-<NUM> to <NUM>-<NUM> located in front of the connection unit <NUM>-<NUM> as the second mitigation circuit RC2.

Subsequently, referring to <FIG>, it can be seen that the phase shift amount is decreased behind the connection unit <NUM> (behind the positions P1, P2, and P3) as in <FIG>. However, it can be seen that the phase shift amount in front of the connection unit <NUM> (in front of the positions P1, P2, and P3) is not as large as that in <FIG>.

Thus, when the frequency of the signal S is <NUM> [GHz], it is desirable to designate at least one of the digital phase shift circuits <NUM> located behind at least one connection unit <NUM> as the first mitigation circuit RC1. For example, in the digital phase shifter <NUM> shown in <FIG>, it is desirable to designate the digital phase shift circuit <NUM>-<NUM> located behind the connection unit <NUM>-<NUM>, the digital phase shift circuit <NUM>-<NUM> located behind the connection unit <NUM>-<NUM>, and the digital phase shift circuit <NUM>-<NUM> located behind the connection unit <NUM>-<NUM> as the first mitigation circuit RC1.

As described above, in the present embodiment, there are provided a plurality of digital phase shift circuit groups <NUM> in which a plurality of digital phase shift circuits <NUM> are connected in cascade and one or more bend-type connection units <NUM> connected between two digital phase shift circuit groups <NUM>. At least one of the digital phase shift circuits <NUM> constituting at least one digital phase circuit group <NUM> is a mitigation circuit RC that mitigates a distribution of phase shift amounts. Thus, the distribution of phase shift amounts caused by weak reflections occurring in front of and behind the connection unit <NUM> can be mitigated.

Here, the mitigation circuit RC includes at least one of the first mitigation circuit RC1, which is a digital phase shift circuit <NUM> having a larger phase shift amount than the standard digital phase shift circuit ST, and the second mitigation circuit RC2, which is a digital phase shift circuit <NUM> having a smaller phase shift amount than the standard digital phase shift circuit ST. It is possible to mitigate a recess portion in the distribution of phase shift amounts using the first mitigation circuit RC1 and it is possible to mitigate a projection portion in the distribution of phase shift amounts using the second mitigation circuit RC2. Thus, using the first mitigation circuit RC1 and the second mitigation circuit RC2, it is possible to take a countermeasure regardless of whether the distribution of phase shift amounts has a recess portion or a projection portion.

Although an embodiment of the present invention has been described above, the present invention is not limited to the above embodiment and modifications can be freely made within the scope of the present invention. Although a case where the frequency of the signal S is, for example, <NUM>, <NUM>, or <NUM> [GHz] has been described in the above-described embodiment, the frequency of the signal S may be a frequency other than <NUM>, <NUM>, or <NUM> [GHz]. For example, the frequency of the signal S may be any frequency in the frequency band of microwaves, quasi-millimeter waves, millimeter waves, or the like.

Also, an example in which the digital phase shifter <NUM> includes the standard digital phase shift circuit ST, the first mitigation circuit RC1, and the second mitigation circuit RC2 has been described in the above-described embodiment. However, the digital phase shifter <NUM> may include only the standard digital phase shift circuit ST and the first mitigation circuit RC1 or may include only the standard digital phase shift circuit ST and the second mitigation circuit RC2.

While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description, and is only limited by the scope of the appended claims.

Claim 1:
A digital phase shifter (<NUM>) comprising:
a plurality of digital phase shift circuit groups (<NUM>) in which a plurality of digital phase shift circuits (<NUM>) are connected in cascade; and
one or more bend-type connection units (<NUM>) connected between two digital phase shift circuit groups (<NUM>),
wherein each of the digital phase shift circuits (<NUM>) includes at least a signal line (<NUM>), a pair of inner lines (<NUM>) provided at both sides of the signal line, a pair of outer lines (<NUM>) provided outside of the inner lines, a first ground conductor (4a) connected to one end of each of the inner lines and the outer lines, a second ground conductor (4b) connected to the other end of each of the outer lines (<NUM>), a pair of electronic switches (7a, 7b) provided between the other ends of the inner line (<NUM>) and the second ground conductor, and a capacitor (<NUM>) electrically connected between the signal line (<NUM>) and at least one of the first ground conductor (4a) and the second ground conductor (4b) ,
wherein each of the digital phase shift circuits (<NUM>) is a circuit set in a low-delay mode in which a return current flows through the inner line or a high-delay mode in which a return current flows through the outer line (<NUM>), and
wherein at least one of the digital phase shift circuits (<NUM>) constituting at least one digital phase shift circuit group (<NUM>) is a mitigation circuit (RC),characterized in that the mitigation circuit (RC) is configured to mitigate differences in phase shift amounts of the plurality of digital phase shift circuits (<NUM>) caused by reflections at the one or more bend-type connection units (<NUM>).