Patent Description:
As the circuit density for next generation devices increases and transistor dimensions continue to shrink, the properties of the materials used for wire interconnects begins to dominate device performance for major performance metrics including power consumption, resistance-capacitance (RC) delay, and reliability. Copper has been used for wire interconnects in advanced USLI and VSLI technologies for the past two decades because copper generally exhibits relatively low resistivity, and thus high conductivity. However, as the widths of the interconnect wiring of a device shrink to dimensions at or below the electron mean free path (eMFP) of the interconnect wiring material, the effective resistivity of the material is increased as a result of undesirable side-wall electron scattering at the surface of the interconnect wiring and the grain boundary interfaces thereof. Thus, the effective resistivity of copper, the material conventionally used in interconnects, begins to increase for copper interconnects having a width below copper's eMFP of <NUM> and increases dramatically for interconnects having a width of <NUM> or less. In addition, barrier layers used with copper interconnects (to prevent undesirable diffusion of the copper material into surrounding dielectric material) further contribute to an increased overall resistivity of the wire interconnect. One promising replacement for copper as a wire interconnect material is nickel silicide which has comparably low resistivity and an eMFP of less than <NUM> (depending on the nickel to silicon material composition) making it a suitable material for wire interconnects having a trench critical dimension (CD) of <NUM> or less and even of <NUM> or less.

Metal silicides, such as nickel silicide, are widely used in front end of line (FEOL) semiconductor device manufacturing processes where low resistivity and thermally stable conductor materials are desired. For example, metal silicides are commonly used to form ohmic contact with source, drain, and gate device features. Unfortunately, conventional methods of forming metal silicides, such as annealing alternating layers of metal and silicon to cause the interdiffusion thereof and solid state reactions between the metal and silicon atoms, are generally incompatible with the lower thermal budget requirements of back end of line (BEOL) semiconductor device manufacturing processes, including processes for forming wire interconnects.

<CIT> discloses a prior art method of forming an interconnect comprising a metal silicide.

Accordingly, what is needed in the art are improved methods of forming metal silicides and metal silicide wire interconnects at lower temperatures.

Embodiments herein relate to semiconductor device manufacturing, and more particularly, to methods of forming metal silicide interconnects using a physical vapor deposition (PVD) and high pressure anneal process sequence.

According to one aspect of the present disclosure, a method of processing a substrate according to claim <NUM> is provided.

So that the manner in which the features of the present disclosure can be understood in detail, a more particular description of the disclosure may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope.

Embodiments herein relate to semiconductor device manufacturing, and more particularly, to methods of forming metal silicide interconnects using a physical vapor deposition (PVD) and high pressure anneal process sequence. In some embodiments, the process sequence includes depositing a layer of a mixture of metal and silicon on a substrate having a plurality of openings formed therein, depositing a passivation layer, such as a metal nitride layer, on the metal and silicon layer, and annealing the substrate in a high pressure atmosphere. Typically, a multi-cathode PVD chamber is used to deposit both the metal and silicon layer and the passivation layer and a high pressure anneal chamber is used to anneal the metal and silicon layer to form low resistivity metal silicide interconnects.

Using a multi-cathode, i.e., multi-sputtering target, PVD chamber to practice the methods set forth herein allows for smaller target diameters than typically used in conventional single target PVD chambers. A smaller target diameter for some target materials, such as nitrides, oxides, metal and silicon alloys, and metal silicides, beneficially reduces the chances a target formed therefrom from cracking due to uneven erosion of material from the target surface over the target's lifetime. The uneven wear of the target material induces within-target mechanical stresses that cause bending and flexing thereof during the deposition processes. This bending and flexing of the target leads to undesirable cracking. However, because the bending associated with a smaller diameter target is less than the bending associated with a larger diameter target, the smaller diameter targets used herein are desirably less prone to cracking. Further, using a multi-target PVD chamber allows for deposition of the passivation layer without exposing the substrate, and the metal and silicon layer deposited thereon, to atmospheric conditions or requiring a time consuming transfer sequence to a second processing chamber. Using a high pressure (e.g., more than the atmospheric pressure) processing chamber to anneal the metal and silicon layer enables the formation, through low temperature high pressure anneal thereof, of a crystalline phase metal silicide layer at anneal temperatures that are compatible with BEOL thermal budget requirements, herein at anneal temperatures of <NUM> or less. As used herein atmospheric pressure is about <NUM> bar.

<FIG> is a schematic cross-sectional view of an exemplary multi-cathode physical vapor deposition (PVD) chamber used to practice the methods set forth herein, according to one embodiment. The PVD chamber <NUM> features one or more sidewalls <NUM>, a chamber lid <NUM>, and a chamber base <NUM> which together define a processing volume <NUM>. The processing volume <NUM> is fluidly coupled to a vacuum, such as to one or more dedicated vacuum pumps, which maintain the processing volume <NUM> at sub-atmospheric conditions and evacuate processing and other gases therefrom.

A substrate support <NUM>, disposed in the processing volume <NUM>, is disposed on a movable support shaft <NUM> sealingly extending through the chamber base <NUM>, such as being surrounded by a bellows (not shown) in the region below the chamber base <NUM>. Herein, the PVD chamber <NUM> is conventionally configured to facilitate transferring of a substrate <NUM> to and from the substrate support <NUM> through an opening <NUM> in one of the one or more sidewalls <NUM>, which is conventionally sealed with a door or a valve (not shown) during substrate processing. In some embodiments, the support shaft <NUM> is further coupled to an actuator (not shown) which rotates the support shaft <NUM>, and thus the substrate <NUM> disposed on the substrate support <NUM>, about an axis A during substrate processing which, under some process conditions, improves the thickness uniformity of the deposited layers on the surface of the substrate <NUM>.

Herein, the PVD chamber <NUM> features a plurality of cathodes <NUM>. One or more of the cathodes <NUM> features a target assembly <NUM> disposed in the processing volume <NUM>, a cathode housing <NUM> coupled the target assembly <NUM> where the cathode housing <NUM> and the target assembly define a housing volume <NUM>, and a magnet assembly <NUM> disposed in the housing volume <NUM>. In some embodiments, the target assembly <NUM> includes a sputtering target <NUM> disposed on, and bonded to, a target backing plate <NUM>. In other embodiments, the target assembly <NUM> comprises a unitary body formed of a to be sputtered target material. In some embodiments, the magnet assembly <NUM> is coupled to a rotatable shaft <NUM> which rotates the magnet assembly <NUM> about an axis B over the rear non-sputtering side of the target assembly <NUM>. Each of the cathodes <NUM> herein is coupled to a power supply <NUM>, such as to an RF frequency power supply, a DC power supply, or a pulsed DC power supply. In some embodiments, a cooling fluid having a relatively high resistivity is provided to the housing volume <NUM> by a cooling fluid source (not shown) in fluid communication therewith to cool the magnet assembly <NUM> and the adjacent target assembly <NUM>.

Typically, the PVD chamber <NUM> includes a shield assembly (not shown) disposed in the processing volume <NUM> and extending between adjacent target assemblies <NUM> which is positioned to prevent cross-talk (undesirable electrical interference from one cathode's power supply with another cathode's power supply during a co-sputtering process) and cross-target contamination (undesirable deposition of material from one cathode's target onto another cathode's target during co-sputtering, sequential sputtering, or single sputtering processes).

Herein, each of the cathodes <NUM> includes a bellows <NUM> and an angular adjustment mechanism (not shown) coupled to the exterior of the chamber lid <NUM> and to the cathode housing <NUM>. The bellows <NUM> is used to maintain the vacuum condition of the processing volume <NUM> by preventing the passage of atmospheric gases into the processing volume <NUM> and leakage of processing gases from the processing volume <NUM> to the surrounding environment while allowing angular adjustment of the cathode housing <NUM> with respect to the chamber body. The angular adjustment mechanism is used to alter, and then fix, the position the cathode housing <NUM> and thus a sputtering surface of a target <NUM> coupled thereto, at an angle relative to the surface of the substrate <NUM> which is described in further detail with reference to <FIG>.

<FIG> illustrates the relative positions of a target <NUM> of any one of the cathodes <NUM> and a substrate <NUM> when the substrate <NUM> is in a raised substrate processing position, according to one embodiment. The target <NUM> is spaced apart from a plane of a surface of the substrate <NUM> by a vertical distance Z measured from a portion of the target <NUM> closest to the plane of the surface of the substrate. Herein, the vertical distance Z is between about <NUM> and about <NUM>, such as between about <NUM> and about <NUM>, such as between about <NUM> and about <NUM>, for example between about <NUM> and about <NUM>. The sputtering surface of the target <NUM> is angled with respect to the surface of the substrate <NUM> at an angle θ between about <NUM> degrees and about <NUM> degrees, such as between about <NUM> degrees and about <NUM> degrees, for example between about <NUM> degrees and about <NUM> degrees or between about <NUM> degrees and about <NUM> degrees.

Typically, the substrate <NUM> has a diameter of <NUM> or more and the target <NUM> has a diameter less than the diameter of the substrate <NUM>, such as less than <NUM>, such as <NUM> or less, or <NUM> or less, for example between about <NUM> and about <NUM>, such as between about <NUM> and about <NUM>, or about <NUM>. In some embodiments, a thickness of the target, for example a thickness of a metal-silicon alloy forming the target is between about <NUM> and about <NUM>.

<FIG> is a schematic cross-sectional view of an exemplary high pressure anneal chamber used to practice the methods set forth herein, according to one embodiment. The anneal chamber <NUM> features a chamber body <NUM> defining a processing volume <NUM> and a substrate support <NUM> disposed in the processing volume <NUM>. Herein, the anneal chamber is a single substrate processing chamber configured to heat a substrate <NUM> disposed on the substrate support <NUM> to a desired temperature using a heat source, such as a resistive heater <NUM>, embedded in the substrate support <NUM>. In some embodiments, the substrate support is a hot plate. In some other embodiments, the heat source is a radiant heat source, such as a plurality of lamps positioned above, below, or both above and below the substrate <NUM> to radiate heat theretowards. In some other embodiments, the anneal chamber is a batch processing chamber configured to heat a plurality of substrates in a single anneal process sequence.

Herein, the processing volume <NUM> is fluidly coupled to a high pressure gas source <NUM> and to a vacuum source, such as one or more dedicated vacuum pumps or to a common fab exhaust. Herein, the high pressure gas source <NUM> includes one or more high pressure gas cylinders (not shown) having a pressure that is more than the desired processing pressure in the processing volume. In other embodiments, the high pressure gas source <NUM> includes one or more pumps (not shown) that pressurize one or more anneal gases delivered thereto. During substrate processing the processing volume <NUM> is desirably maintained at a pressure above atmospheric pressure, such as between about more than about <NUM> times and about <NUM> times atmospheric pressure, through operation of valves 206a and 206b fluidly coupled to the high pressure gas source <NUM> and the vacuum source respectively. Herein, the anneal chamber <NUM> is capable of heating and maintaining the substrate to temperatures up to <NUM>, typically between <NUM> and <NUM>. Herein, the anneal chamber <NUM> is a standalone chamber or one of a plurality of connected chambers that is not coupled to the multi-cathode PVD chamber <NUM> described in <FIG>. In other embodiments (not shown), the anneal chamber <NUM> and the PVD chamber <NUM> are part of a multi-chamber (i.e., cluster tool) processing system and are coupled by transfer chamber which allows for transfer of a substrate from the PVD chamber <NUM> to the anneal chamber <NUM> without exposing the substrate to atmospheric conditions.

<FIG> is a flow diagram of a method of forming a metal and silicon layer on a substrate, according to one embodiment. <FIG> is a flow diagram of a method of annealing a metal and silicon layer to form low resistivity metal silicide wire interconnects, according to one embodiment. <FIG> illustrate forming metal silicide interconnects using the combined methods set forth in <FIG>, according to one embodiment.

At activity <NUM> the method <NUM> includes flowing a sputtering gas into a processing volume, herein a first processing volume, which is a processing volume of a first processing chamber, such as the processing volume of the multi-cathode PVD chamber described in <FIG>. Typically, the sputtering gas comprises an inert gas, for example Ar, He, Ne, Kr, Xe, or a combination thereof. In some embodiments, the first processing volume is desirably maintained at a pressure less than about <NUM> mTorr, such as less than about <NUM> mTorr, such as less than about 1mTorr, for example between about <NUM> mTorr and about <NUM> mTorr during the deposition process.

At activity <NUM> the method <NUM> includes applying a power to a first target disposed in the first processing volume. Here, the first target comprises a metal-silicon alloy, for example TiSi, NiSi, PtSi, or CoSi. In some embodiments, the first target comprises an amorphous nickel-silicon alloy having an atomic composition of NiXSi(<NUM>-X) where X is between about <NUM> and about <NUM>, for example about <NUM>. Herein, the first target is bonded to a backing plate, e.g., a copper backing plate. In some embodiments, the first target is desirably maintained at a temperature between about <NUM> and about <NUM> during the deposition process.

In some embodiments, the first target further comprises carbon, for example TiSiC. In other embodiments, the first target comprises a metal-metal-silicon alloy or a metal-metal-carbon alloy, for example TiAlSi or TiAlC. In embodiments herein, a sputtering surface of the first target is angled with respect to a surface of the substrate at between about <NUM>° and about <NUM>°, such as between about <NUM>° and about <NUM>°. In some embodiments, a diameter of the first target is less than a diameter of the substrate, such as in embodiments where a diameter of the substrate is <NUM> or more. In some embodiments, the diameter of the first target is between about <NUM> and about <NUM>, or example about <NUM> or less, such as about <NUM> or less. Typically, depending on the chamber configuration material sputtered from the first target may cover between about <NUM>% and about <NUM>% of the substrate surface. Therefore, in some embodiments, the method further includes rotating the substrate during the deposition process.

Typically, the power applied to the first target is delivered from an RF frequency (or other ac frequency) power source, a DC power source, or a pulsed DC power source. Herein, the power source is coupled to the first target, to a backing plate having the first target bonded thereto, and thus electrically coupled thereto. Typically, when used, an RF power applied to the target is between about <NUM> watts and about <NUM> watts or a DC power applied to the target is between about <NUM> watts and about <NUM> watts. In some embodiments, a pulsed DC power applied to the target has a pulse frequency of between about <NUM> and about <NUM> and an on-time duty cycle of between about <NUM>% and about <NUM> %.

At activity <NUM> the method <NUM> includes forming a first plasma in a region proximate to the sputtering surface of the first target.

At activity <NUM> the method <NUM> includes depositing the metal and silicon layer on the surface of the substrate, such the patterned substrate <NUM> illustrated in <FIG>. In some embodiments, the method <NUM> further includes rotating the substrate while depositing the metal and silicon layer on the surface thereof.

In some embodiments, the method <NUM> further includes depositing a passivation layer, such as the passivation layer <NUM> shown in <FIG>, on the metal and silicon layer. Examples of passivation layers include metal-nitride layers or metal-oxide layers where the metal is one or Al, Cr, Zn, Ti, or a combination thereof or silicon oxide or nitride layers. In some embodiments, the passivation layer <NUM> is deposited in the same multi-cathode PVD chamber used to deposit the metal and silicon layer 404a, and thus is deposited without the substrate breaking vacuum. In some embodiments, the passivation layer <NUM> comprises TiN deposited in the same processing chamber as the metal and silicon layer, and thus without the substrate breaking vacuum. In some embodiments, the target comprises TiN and the sputtering gas comprises an inert gas, for example Ar, He, Ne, Kr, Xe, or a combination thereof. Using a TiN target and an inert sputtering gas depositing a TiN passivation layer desirably avoids exposing the substrate, having the metal and silicon layer deposited thereon, to a plasma formed of a nitrogen source gas typically used to form TiN layers which could potentially damage the previously deposited nickel and silicon layer, e.g., buy forming undesirable silicon nitride therein. Therefore, in some embodiments, the sputtering gas used to deposit the TiN layer is nitrogen free meaning that the gases used to form the sputtering gas do not have a nitrogen moiety.

In other embodiments, the TiN layer is deposited by flowing a sputtering gas comprising an inert gas and a nitrogen containing gas, such as N<NUM>, NH<NUM> or combinations thereof, into the processing chamber, applying an RF power to a second target, herein a titanium target, forming a plasma of the sputtering gas in front of the sputtering surface of the second target, and depositing a TiN layer onto the metal and silicon layer. In some embodiments, the passivation layer has a thickness T of about <NUM> or more, such as about <NUM> or more, or about <NUM> or more. Typically, the second target is angled with respect to the surface of the substrate support, and thus an active surface of the substrate positioned thereon, at between about <NUM>° and about <NUM>°, such as between about <NUM>° and about <NUM>°.

<FIG> is a flow diagram of a method of annealing a metal and silicon layer to form low resistivity metal silicide wire interconnects, according to one embodiment. At activity <NUM> the method <NUM> includes pressurizing a first processing volume to a desired pressure of more than about <NUM> times the atmospheric pressure, for example between about <NUM> times and about <NUM> times the atmospheric pressure, such as more than about <NUM> times, more than about <NUM> times, more than about <NUM> times, or more than about <NUM> times the atmospheric pressure. Here, the first processing volume is a processing volume of a first processing chamber, such as the high pressure anneal chamber <NUM> described in <FIG>. Typically, the first volume is pressurized by delivering a high pressure gas thereinto. Examples of high pressure gases, e.g., annealing gases, used herein include Ar, He, forming gas (mixture of H<NUM> and N<NUM>), N<NUM>, O<NUM>, CO, CO<NUM>, and combinations thereof. In some embodiments, the annealing gas is one or a combination of Ar, He, or N<NUM>. Herein, the first processing volume is maintained at the desired pressure through the duration of activities <NUM> and <NUM>, or at least through the duration of activity <NUM>.

At activity <NUM> the method <NUM> includes heating a substrate to an anneal temperature of not more than about <NUM>. In some embodiments, the anneal temperature is not more than about <NUM>, or is between about <NUM> and about <NUM>, for example between about <NUM> and about <NUM>. In other embodiments, the substrate is heated to the anneal temperature before the first processing volume is pressurized at activity <NUM>.

At activity <NUM> the method <NUM> includes maintaining the substrate at the anneal temperature for about <NUM> seconds or more, such as between about <NUM> seconds and about <NUM> hours, such as between about <NUM> seconds and about <NUM> minutes, between about <NUM> seconds and about <NUM> minutes, for example between about <NUM> seconds and about <NUM> minutes, to form a metal silicide layer 404b.

In some embodiments, the substrate is a patterned substrate, such as the patterned substrate 400b shown in <FIG> comprising a dielectric layer <NUM> having a plurality of openings formed therein, such as the openings <NUM> shown in <FIG>, and a metal and silicon layer 404a disposed in the openings to form a plurality of interconnect features, e.g., wire interconnects.

Herein, the plurality of interconnect features were formed using a method which included flowing a first sputtering gas into a second processing volume, such as the processing volume of the multi-cathode PVD chamber <NUM> described in <FIG>, applying a power to a first target disposed in the second processing volume, forming a first plasma in a region proximate to the sputtering surface of the first target, and depositing a metal and silicon layer on the surface of the substrate and in a plurality of openings formed in the dielectric layer.

Further embodiments of the method <NUM> include any of the embodiments set forth in the method <NUM> described in <FIG>. In some embodiments, one or both of the methods <NUM> and <NUM> are used to form a plurality of nickel monosilicide interconnects having a width of less than about <NUM>, a height of <NUM> times width or more, and a resistivity of less than about <NUM> ohm-cm, such as between about <NUM> ohm-cm and about <NUM> ohm-cm.

The methods <NUM> and <NUM> described above beneficially allow for the formation of low resistivity crystalline metal silicide interconnects, such as nickel monosilicide interconnects suitable for use in the sub <NUM> regime, using processing temperatures compatible with back end of line (BOEL) thermal budget requirements.

<FIG> illustrates an exemplary patterned substrate 400a, according to one embodiment. Herein, the patterned substrate 400a includes a substrate <NUM> formed of a semiconductor material, such as silicon, having a dielectric layer <NUM> disposed thereon. Typically, the dielectric layer <NUM> is formed of nitride, carbide, or low-k polymer materials, such as SiO<NUM>, SiN, SiOC, SiC, a polyamide, or combinations thereof and has a plurality of openings <NUM> formed therein. In some embodiments, a width W of each of the openings <NUM> is less than about <NUM>, such as less than about <NUM>, less than about <NUM>, less than about <NUM>, less than about <NUM>, for example less than about <NUM>. Typically, a height H of each of the openings <NUM> is equal to or more than about <NUM> times the width W.

Here, the patterned substrate 400a does not include a barrier layer (a layer of material that prevents undesirable diffusion of some interconnect materials, e.g., copper, into the dielectric layer <NUM>). In other embodiments, the patterned substrate 400a further includes a barrier layer (not shown), such as a layer of Ta, TaN, It, W, WN, or combinations thereof, disposed on the dielectric layer <NUM> and serving as a liner in the openings <NUM>. In some embodiments, a barrier layer is deposited in the same processing chamber as is the subsequently deposited metal and silicon layer, and thus without the substrate breaking vacuum between the deposition of the barrier layer and the to be deposited metal and silicon layer.

<FIG> illustrates a metal and silicon layer 404a, such as a nickel and silicon layer, deposited on the patterned substrate 400a shown in <FIG> using the method <NUM>. Typically, the as deposited metal and silicon layer 404a comprises a mixture, for example a homogenous mixture, of metal and silicon having a substantially uniform stoichiometry. A substantially uniform stoichiometry herein at least means that the atomic ratio of metal to silicon in the mixture varies less than <NUM>% when measured at locations both across the surface of the metal and silicon layer 404a or at locations within the metal and silicon layer 404a such as locations proximate to surface of the dielectric layer <NUM>, distal from surfaces of the dielectric layer <NUM>, and at locations therebetween. In some embodiments, the stoichiometry of the mixture of metal and silicon varies less than about <NUM>%, such as less than <NUM>%, less than <NUM>%, for example less than <NUM>%.

In some embodiments, the as deposited metal and silicon layer 404a comprises an amorphous nickel-silicon alloy having substantially uniform stoichiometry of NiXSi(<NUM>-X), where X is between about <NUM> and about <NUM>, for example about <NUM>. In some embodiments, the as deposited metal and silicon layer 404a comprises a combination of amorphous nickel-silicon alloy and crystalline nickel silicide, the combination having a substantially uniform stoichiometry of NiXSi(<NUM>-X), where X is between about <NUM> and about <NUM>, for example about <NUM>. In some embodiments, the as deposited metal and silicon layer 404a comprises an unsaturated and thermally unstable mixture of metal and silicon. Therefore, embodiments herein provide for low temperature high pressure anneal of the as deposited metal and silicon layer 404a to form crystalline phase metal silicide through solid state reaction. Low temperature high pressure anneal of the as deposited metal and silicon layer 404a ensures complete saturation of otherwise dangling silicon bonds to provide a thermally stable crystalline phase metal silicide, such as crystalline nickel monosilicide (NiSi), suitable for use as low resistivity wire interconnects in a semiconductor device. Herein, low resistivity at least means that the sheet resistance of a metal silicide layer is less than about <NUM>µohm-cm, such as less than about <NUM>µohm-cm, less than about <NUM>µohm-cm, for example less than about <NUM>µohm-cm.

Claim 1:
A method of processing a substrate, comprising:
forming a metal and silicon layer (404a) on a substrate (<NUM>), comprising:
flowing a first sputtering gas into a first processing volume, wherein the first processing volume is a processing volume of a first processing chamber;
applying a power to a first target disposed in the first processing volume, wherein the first target comprises a metal-silicon alloy and a sputtering surface thereof is angled with respect to a surface of a substrate at between <NUM>° and <NUM>°;
forming a first plasma in a region proximate to the sputtering surface of the first target; and
depositing the metal and silicon layer (404a) on the surface of the substrate (<NUM>), annealing the metal and silicon layer (404a) in a second processing volume,
wherein the second processing volume is a processing volume of a second processing chamber, and wherein annealing the metal and silicon layer comprises:
pressurizing the second processing volume to a pressure of more than <NUM> times atmospheric pressure using a pressurized gas delivered thereinto;
heating the substrate (<NUM>) to an anneal temperature of not more than <NUM>; and
maintaining the substrate (<NUM>) at the anneal temperature for <NUM> seconds or more.