Patent Description:
For fabricating conductive deep trenches in conjunction with shallow trench isolations in a semiconductor device, the described techniques introduce an integrated sequence during which a shallow trench is etched and filled before a deep trench is etched and filled. The described techniques advantageously reduce cone defects along a top surface of the shallow trench isolation structures, thereby minimizing the defect density of a semiconductor device. And by integrating the deep trench formation process with the shallow trench formation process, the described techniques advantageously reduce the process complexity of fabricating a semiconductor device.

In one implementation, for example, this description introduces a method according to claim <NUM>.

Preferably, the the dielectric layer is formed by a shallow trench oxide layer and a hard mask layer covers the shallow trench oxide tayer layer.

In yet another implementation, this description introduces a device according to claim <NUM>.

Preferred embodiments of the method and the device are defined in the dependent claims.

The drawings are not drawn to scale.

Deep trench structures can be found in many semiconductor devices, such as high voltage analog devices. In high voltage applications, a deep trench structure may include a conductive filler, which can serve as a field plate for reducing electric field density, or as a gate electrode of a vertical transistor (e.g., a vertical diffused MOS (VDMOS) transistor). Deep trench structures can be formed in conjunction with shallow trench structures. As shown in <FIG>, for example, a semiconductor device <NUM> can be fabricated under a sequence that forms a deep trench <NUM> before forming a shallow trench <NUM>.

Referring to <FIG>, the semiconductor device <NUM> can be a discrete component device (e.g., a single transistor device) or an integrated circuit having multiple transistor devices. At an early stage of the fabrication sequence, a pad oxide layer <NUM>, a nitride cap layer <NUM>, and a hard mask layer <NUM> are sequentially formed on a top surface of a semiconductor substrate <NUM>. The pad oxide layer <NUM> servers the function of stress relief between the silicon and subsequent layers, and it may include silicon dioxide that is grown in a thermal oxidation process. The nitride cap layer <NUM> servers the function of exclusionary film allowing selective oxidation, and it may include silicon nitride (e.g., Si<NUM>N<NUM>) that is deposited under a Low Pressure Chemical Vapor Deposition (LPCVD) furnace process. The hard mask layer <NUM> servers the function of a hard mask during the subsequent Deep Trench etch process, and it may include silicon dioxide that is deposited under a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.

Next, a photoresist mask <NUM> is deposited and patterned with an opening exposing a deep trench (DT) region <NUM> of the substrate <NUM>. The photoresist mask <NUM> servers the function of masking the hard mask layer, and it may include a light sensitive organic material that is coated, exposed, and developed.

Referring to <FIG>, a DT etch process <NUM> is performed to form a deep trench <NUM>. The DT etch process <NUM> may include multiple subsequences. In one implementation, for example, a hard mask etch may be first performed to remove the hard mask layer <NUM> exposed by the patterned photoresist mask <NUM>, and a silicon etch may then be performed to remove the nitride cap layer <NUM>, the pad oxide layer <NUM>, and the substrate <NUM> that are exposed by the etched hard mask layer <NUM>. During the silicon etch, the photoresist mask layer <NUM> is also removed, leaving the hard mask layer <NUM> to prevent the area outside of the DT region <NUM> from being etched.

After the DT etch process <NUM>, a dielectric liner deposition process is performed to cover the sidewalls of the deep trench <NUM>. As shown in <FIG>, for example, a DT oxide liner <NUM> is deposited onto the sidewall of the deep trench <NUM> under a dielectric liner deposition process <NUM>. In one implementation, the dielectric liner deposition <NUM> may include a sub-atmospheric chemical vapor deposition of an oxide target. The dielectric liner deposition process <NUM> may be followed by a deep trench dielectric etch process to achieve uniform liner thickness along the sidewall of the deep trench <NUM>.

Referring to <FIG>, a polysilicon deposition process <NUM> is performed to fill the deep trench <NUM> with a conductive material. As a result, a DT filler structure <NUM> is formed in the deep trench <NUM>. The DT filler structure <NUM> may contact the DT oxide liner <NUM>. Alternatively, the DT filler structure <NUM> may directly contact the sidewall of the deep trench <NUM> where the DT oxide liner <NUM> is absent. During the polysilicon deposition process <NUM>, a DT filler seam <NUM> may be formed along a vertical middle section of the FT filler structure <NUM>. The dimensions of the DT filler seam <NUM> may depend on the aspect ratio of the deep trench <NUM>.

After the DT filler structure <NUM> is formed, a chemical mechanical polish process is performed to remove excessive polysilicon material above the deep trench <NUM>. At this point, a conductive deep trench <NUM> is formed. Then, the remaining nitride cap layer <NUM> and pad oxide layer <NUM> are removed and redeposited to complete the deep trench formation sequence and prepare for the shallow trench formation sequence.

Referring to <FIG>, a photoresist mask <NUM> is deposited and patterned above the nitride cap layer <NUM> to expose a shallow trench (ST) region <NUM> of the semiconductor substrate <NUM>. In general, the ST region <NUM> covers a wider area than the DT region <NUM>, which may position completely within the ST region <NUM>. After the photoresist mask <NUM> is patterned, a shallow trench etch process is performed. Referring to <FIG>, for example, a shallow trench etch process <NUM> may include a silicon etch to remove the nitride cap layer <NUM> and the pad oxide layer <NUM> exposed by the photoresist mask <NUM>. During the silicon etch, the DT filler seam <NUM> may trap residuals from the nitride cap layer <NUM> and the pad oxide layer <NUM>, which may in turn retard the etch rate around the DT filler seam <NUM>. This slower etching may lead to the formation of one or more polysilicon cones <NUM> near the DT filler seam <NUM>.

When the shallow trench etch <NUM> is completed, a shallow trench <NUM> is formed. And as a result of the shallow trench etch <NUM>, the DT structure <NUM> recedes from a first plane <NUM>, which aligns with the top surface of the substrate <NUM>, to a second plane <NUM>, which aligns with the bottom surface of the shallow trench <NUM>. After the shallow trench <NUM> is formed, a dielectric liner may be deposited onto and aligns with the sidewall of the shallow trench <NUM>. Then, as shown in <FIG>, a shallow trench fill process <NUM> is performed to fill the shallow trench <NUM> with a dielectric layer <NUM>. The shallow trench fill process <NUM> may include a thermal oxide growth process or an oxide deposition process. Because of the polysilicon cone <NUM>, the dielectric layer <NUM> may incur a dielectric cone <NUM> protruding from the top surface of the dielectric layer <NUM>.

<FIG> only shows a single dielectric cone <NUM> and a single polysilicon cone <NUM>, but in reality, a semiconductor device (e.g., device <NUM>) fabricated under the process steps as shown above may incur many more dielectric cones and silicon cones in a small area. The dielectric cones may be subsequently removed during a chemical mechanical polish process. Nevertheless, the polysilicon cone <NUM> remains under the dielectric layer <NUM>. As the dielectric layer <NUM> is mostly transparent, the polysilicon cone <NUM> is visible or detectable by one or more inspection devices. Thus, the polysilicon cone <NUM> may obstruct one or more inspection processes for detecting structural defects of the semiconductor device. As a result, yield related issues may remain undetected by the inspection processes. These undetected yield related issues will ultimately impact the yield of a mass production of the semiconductor devices.

To reduce or eliminate inspection issues related to cone formation, this description introduces a method of fabricating a semiconductor device with overlapping shallow trench and deep trench structures that can prevent cone formation. According to an aspect of this description, <FIG> shows a flow chart of an example method <NUM> for fabricating a shallow trench followed by a deep trench free of cone defects. The method <NUM> begins at step <NUM>, which involves forming a shallow trench in a first region of a substrate. Unlike the process as depicted in <FIG>, the method <NUM> arranges the shallow trench to be formed before the deep trench. For illustration, <FIG> show the partial cross-sectional views of an example semiconductor device <NUM> during a fabrication process that implements the method <NUM>.

Referring to <FIG>, for example, the semiconductor device <NUM> is at an early stage of a fabrication process. The semiconductor device <NUM> can be a discrete component device (e.g., a single transistor device) or an integrated circuit having multiple transistor devices. Before step <NUM> is performed, a pad oxide layer <NUM>, and a nitride cap layer <NUM> are sequentially formed on a top surface of a semiconductor substrate <NUM>. The process parameters for forming the pad oxide layer <NUM>, and the cap nitride layer <NUM> are essentially the same as described in association with <FIG>.

During step <NUM>, a photoresist mask <NUM> is deposited and patterned with an opening exposing a shallow trench (ST) region <NUM>, being a first region of the substrate <NUM>. After the photoresist mask <NUM> is patterned, a shallow trench etch process is performed. Referring to <FIG>, for example, a shallow trench etch process <NUM> may include a silicon etch to remove the nitride cap layer <NUM>,and the pad oxide layer <NUM> as exposed by the photoresist mask <NUM>. When the shallow trench etch <NUM> is completed, a shallow trench <NUM> is formed.

Next, the method <NUM> proceeds to step <NUM>, which involves forming a dielectric layer filling the shallow trench and covering the substrate. According to an aspect of this description, the dielectric layer has a substantially planar surface positioned over and extending across the shallow trench. The substantially planar surface advantageously allows the photoresist mask for etching a deep trench to be deposited and patterned more accurately. While step <NUM> can be performed by forming a single dielectric layer that fills the shallow trench (e.g., shallow trench <NUM>), multiple dielectric layers may be formed during step <NUM> as well.

For example, <FIG> shows a method 220A for forming at least two dielectric layers that fills the shallow trench and covering the substrate. The method 220A begins at step <NUM>, which involves forming a shallow trench oxide layer filling the shallow trench. The shallow trench oxide layer may be considered as a first oxide layer that fills the shallow trench, and it may be thermally grown onto the etched surface of the shallow trench. As shown in <FIG>, for example, a first dielectric formation process 134A is performed to formed a first dielectric layer 135A. The first dielectric formation process 134A may be a thermal oxidation process or an oxide deposition process (e.g., high density plasma deposition). The first dielectric layer 135A is a shallow trench oxide layer as it fills the entire shallow trench <NUM>, which is positioned between a first plane <NUM> and a second plane <NUM> of the substrate <NUM>. The first plane <NUM> aligns along a top surface of the substrate <NUM>, whereas the second plane <NUM> aligns along a bottom surface of the shallow trench <NUM>.

After forming the shallow trench oxide layer, the method 220A proceeds to step <NUM>, which involves forming a hard mask layer covering the shallow trench oxide layer. The hard mask layer may be considered as a second oxide layer that covers the first oxide layer. In one implementation, the second oxide layer may have a lower oxide density than the first oxide layer. The cost of forming an oxide layer with a lower oxide density is lower than the cost of forming an oxide layer with a higher oxide density. Advantageously, the two-step approach provided by the method 220A helps reduce the cost of forming a dielectric layer that fills and covers the shallow trench as prescribed by step <NUM> in the method <NUM>.

As shown in <FIG>, for example, a second dielectric formation process 134B is performed to formed a second dielectric layer 135B. The second dielectric formation process 134B may be a thermal oxidation process or an oxide deposition process (e.g., TEOS plasma enhanced chemical vapor deposition). The second dielectric layer 135B is a hard mask layer as it serves the function of a hard mask during a subsequent deep trench etching process. The second dielectric layer (or hard mask layer) 135B has a substantially planar surface <NUM>. According to an aspect of this description, the surface of the second dielectric layer (or hard mask layer) 135B is substantially planar when it is sufficiently flat to allow accurate placement and patterning of a photoresist mask for the purpose of etching a deep trench within the shallow trench <NUM>. In particular, the substantially planar surface <NUM> may have an aspect ratio defined by a height (H) of the surface over a width (W) that is sufficiently wide to serve as a deep trench aperture.

In one implementation, for example, the second dielectric layer (or hard mask layer) 135B has a substantially planar surface <NUM> where the aspect ratio is less than <NUM>. In another implementation, for example, the second dielectric layer (or hard mask layer) 135B has a substantially planar surface <NUM> where the aspect ratio is less than <NUM>. In yet another implementation, for example, the second dielectric layer (or hard mask layer) 135B has a substantially planar surface <NUM> where the aspect ratio is less than <NUM>. The substantially planar surface <NUM> can be achieved by adjusting several process parameters for forming the first and/or second dielectric layers 135A and 135B. For example, the substantially planar surface <NUM> may be achieved where the second dielectric layer 135B has a thickness that is equal to or greater than that of the first dielectric layer 135A.

Referring again to <FIG>, the method <NUM> proceeds to step <NUM>, which involves forming a deep trench in a second region within the first region of the substrate. As shown in <FIG>, for example, a deep trench (DT) etch process <NUM> is performed to form a deep trench 122A within a deep trench region <NUM>, which is a second region within the first region (e.g., <NUM>) of the substrate <NUM>. The DT etch process <NUM> may include multiple subsequences. In one implementation, for example, a hard mask etch may be first performed to remove the second and first dielectric layer 135B and 135A as exposed by the patterned photoresist mask <NUM>, and a silicon etch may then be performed to remove the substrate <NUM> that is exposed by the second dielectric layer 135B, which serves as a hard mask layer. During the silicon etch, the photoresist mask layer <NUM> is also removed, leaving the second dielectric layer (or hard mask layer) 135B to prevent the area outside of the DT region <NUM> from being etched.

As a result of the DT etch process <NUM>, the deep trench 122A extends from and penetrating through the second and first dielectric layers 135B and 135A. The deep trench 122A has a trench depth d2 that is greater than a trench depth d1 of the shallow trench <NUM>, whereas the shallow trench <NUM> has a trench aperture (e.g., less than the width of the ST region <NUM>) that is wider than a trench aperture (e.g., less than the width of the DT region <NUM>) of the deep trench 122A.

According to an aspect of this description, the DT etch process <NUM> is integrated with the shallow trench isolation process (e.g., steps <NUM>-<NUM>; <FIG>). The described integration provides multiple advantages from a process standpoint. First, the described integration reduces the total number of process steps for fabricating a deep trench structure within a shallow trench structure. For instance, the re-depositions of the pad oxide layer <NUM> and the cap nitride layer <NUM> (see, e.g., <FIG>) can be eliminated. This is because the shallow trench dielectric layer (e.g., 135A and 135B) may serve the functions of the pad oxide and cap nitride layers <NUM> and <NUM> during the DT etch process <NUM>.

Second, the sequence of forming a deep trench after a shallow trench also helps prevent cone formation. As shown in subsequent figures, this is because the deep trench filler structure 126A is no longer etched and then covered by the shallow trench dielectric layer (e.g., 135A and 135B), which reduces the chances that the etch contaminants to be trapped and built up within the DT filler seam 127A of the DT structure 129A.

Third, the described integration process overcomes a phenomenon known as deep trench pattern distortion due to photoresist thickness variation over the shallow trench dielectric layer (e.g., 135A and 135B). By forming the photoresist mask <NUM> over a substantially planar surface <NUM> of the second dielectric layer (or hard mask layer) 135B, the deep trench pattern size (e.g., opening exposing the DT region <NUM>) can be critically controlled to achieve deep trench etch depth uniformity.

After forming the deep trench, the method <NUM> proceeds to step <NUM>, which involves forming a dielectric liner interfacing the dielectric layer in the shallow trench and a sidewall of the deep trench. As shown in <FIG>, for example, a DT oxide liner 124A is deposited onto the etched sidewalls of the dielectric layers 135A and 135B and onto the sidewall of the deep trench 122A under a dielectric liner deposition process <NUM>. In one implementation, the dielectric liner deposition <NUM> may include a sub-atmospheric chemical vapor deposition of an oxide target.

Unlike the DT oxide liner <NUM> as shown in <FIG>, which is positioned under the shallow trench <NUM>, the DT oxide liner 124A extends upward to interface the first and second dielectric layers 135A and 135B within and over the shallow trench <NUM>. The dielectric liner deposition process 123A may be followed by a deep trench dielectric etch process to achieve uniform liner thickness along the sidewall of the deep trench 122A.

After the formation of the dielectric liner, the method <NUM> proceeds to step <NUM>, which involves forming a filler structure laterally surrounded by the dielectric layer in the shallow trench and a sidewall of the deep trench. As shown in <FIG>, for example, a polysilicon deposition process <NUM> is performed to fill the deep trench 122A with a conductive material. As a result, a DT filler structure 126A is formed in the deep trench 122A. The DT filler structure 126A may contact the DT oxide liner 124A and be laterally surrounded by the dielectric layers 134A and 135B. During the polysilicon deposition process <NUM>, a DT filler seam 127A is formed along a vertical middle section of the FT filler structure 126A. The dimensions of the DT filler seam 127A may depend on the aspect ratio of the deep trench 122A. Unlike the DT filler seam <NUM> as shown and described in <FIG>, the DT filler seam 127A will not be subjected to further etching. As such, the DT filler seam 127A is unlikely to contribute to subsequent cone formations as shown and described in <FIG>.

After the DT filler structure <NUM> is formed, a chemical mechanical polish process is performed to remove excessive polysilicon material above the deep trench <NUM>. Referring to <FIG>, for example, a chemical mechanical polish process <NUM> is performed to remove the remaining nitride cap layer <NUM> and pad oxide layer <NUM>. After the chemical mechanical polish process <NUM>, the semiconductor device <NUM> includes a deep trench structure 129A extending downward and within a shallow trench structure <NUM>. The shallow trench structure <NUM> includes a shallow trench dielectric layer 135A that extends from a first plane <NUM> that aligns with a top surface of the substrate <NUM>. The shallow trench structure <NUM> further extends into the substrate <NUM> by a first depth d1. The deep trench structure 129A extends from the first plane <NUM> that aligns with a top surface of the substrate <NUM>. The deep trench structure <NUM> penetrates through the shallow trench dielectric layer 135A and a second plane <NUM> that aligns with the bottom surface of the shallow trench <NUM>. The deep trench structure <NUM> further extends into the substrate <NUM> by a second depth d2, which is greater than the first depth d1.

The DT filler structure 126A of the deep trench structure 129A includes a polysilicon plate having an upper portion and a lower portion. The upper portion has a first width, and it is positioned within in the shallow trench <NUM>. The lower portion has a second width, and it is positioned within in the deep trench 122A. In one implementation, the first width is greater than the second width. The DT oxide liner 124A interfaces between the upper portion of the polysilicon plate and the shallow trench dielectric layer 135A. Moreover, the DT oxide liner 124A also interfaces between the lower portion of the polysilicon plate and the substrate <NUM>. In one implementation, the DT oxide liner 124A has a lower oxide density than the shallow trench dielectric layer 135A.

At this stage of the fabrication process (see, e.g., <FIG>), the semiconductor device <NUM> is substantially cone free around the top surface of the deep trench structure <NUM> as well as the shallow trench structure <NUM>. The semiconductor device <NUM> can be prepared for further processing, which may include the formation of one or more dielectric layers above the deep trench structure <NUM> as well as the shallow trench structure <NUM>. Referring to <FIG>, for example, a dielectric deposition process <NUM> may be performed to form a dielectric layer <NUM> that covers a DT top surface 128A as well as a top surface of the substrate <NUM> and the shallow trench structure <NUM>. In the event that the DT filler structure 126A is not further etched, any subsequent deposition of dielectric layer is unlikely to cause any cone formation thereon.

In this description, the term "configured to" describes structural and functional characteristics of one or more tangible non-transitory components. For example, the term "configured to" can be understood as having a particular configuration that is designed or dedicated for performing a certain function. Within this understanding, a device is "configured to" perform a certain function if such device includes tangible non-transitory components that can be enabled, activated or powered to perform that certain function. The term "configured to" may encompass being configurable, but it does not require a described device to be configurable at any given point of time.

In particular regard to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe such components correspond, unless otherwise indicated, to any component that performs the specified function of the described component (e.g., which is functionally equivalent), even though not structurally equivalent to the described structure. Also, while a particular feature of this description may have been described with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.

In this description, terms of relativity, such as "about," "approximately," "substantially," "near," "within a proximity," "sufficient. to," "maximum," and "minimum," as applied to features of an integrated circuit and/or a semiconductor device can be understood with respect to the fabrication tolerances of a particular process for fabricating the integrated circuit and/or the semiconductor device. Also, these terms of relativity can be understood within a framework for performing one or more functions by the integrated circuit and/or the semiconductor device.

More specifically, for example, the terms "substantially the same," "substantially equals," and "approximately the same" describe a quantitative relationship between two objects. This quantitative relationship may prefer the two objects to be equal by design, but understanding that a certain amount of variations can be introduced by the fabrication process. In one aspect, a first resistor may have a first resistance that is substantially equal to a second resistance of the second resistor where the first and second resistors are purported to have the same resistance, yet the fabrication process introduces slight variations between the first resistance and the second resistance. Thus, the first resistance can be substantially equal to the second resistance even when the fabricated first and second resistors demonstrate slight difference in resistance. This slight difference may be within <NUM>% of the design target. In another aspect, a first resistor may have a first resistance that is substantially equal to a second resistance of a second resistor where the process variations are known a priori, such that the first resistance and the second resistance can be preset at slightly different values to account for the known process variations. Thus, the first resistance can be substantially equal to the second resistance even when the design values of the first and second resistance are preset to include a slight difference to account for the known process variations. This slight difference may be within <NUM>% of the design target.

Claim 1:
A method, comprising:
forming a shallow trench (<NUM>) in a first region of a substrate (<NUM>);
forming a dielectric layer (135A) filling the shallow trench (<NUM>) and covering the substrate (<NUM>), the dielectric layer (135A) having a substantially planar surface (<NUM>) over and across the shallow trench (<NUM>);
forming a deep trench (122A) in a second region within the first region of the substrate (<NUM>), the deep trench (122A) extending from and penetrating through the dielectric layer (135A); and
forming a filler structure (126A) laterally surrounded by the dielectric layer (135A) in the shallow trench (<NUM>) and a sidewall of the deep trench (122A), the filler structure (126A) having a filler seam (127A) formed along a vertical middle section of the filler structure (126A), wherein the filler seam (127A) of the filler structure (126A) will not be subjected to further etching, thereby avoiding cone formation.