Patent Description:
Planar semiconductor devices, such as memory cells, are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the semiconductor devices approach a lower limit, planar process and fabrication techniques become challenging and costly. A three-dimensional (3D) semiconductor device architecture can address the density limitation in some planar semiconductor devices, for example, Flash memory devices. <CIT> describes a through array contact structure of three-dimensional memory device with dummy channel regions between memory blocks. <CIT> describes a blockto-block isolation and deep contact using pillars in memory array. <CIT> describes a semiconductor device with a plurality of transistors.

Implementations of 3D memory device and method for forming the same are disclosed herein.

In one aspect, a 3D memory device according to claim <NUM> is disclosed.

In some implementations, the dummy structure includes a plurality of second conductive layers and a plurality of second dielectric layers alternately stacked along the second direction.

In some implementations, the plurality of first conductive layers and the plurality of second conductive layers are same layers, and the plurality of first dielectric layers and the plurality of second dielectric layers are same layer.

In some implementations, the dummy structure further includes a dummy channel structure extending through the plurality of second conductive layers and the plurality of second dielectric layers along the second direction, wherein the dummy channel structure includes a semiconductor channel and a memory film formed over the semiconductor channel.

In some implementations, the dummy structure further includes a contact structure extending through the plurality of second conductive layers and the plurality of second dielectric layers along the second direction.

In some implementations, the contact structure further includes a contact extending through the plurality of second conductive layers and the plurality of second dielectric layers along the second direction, and a third dielectric layer extending along the second direction surrounding the contact.

In some implementations, a third conductive layer is disposed in the semiconductor layer extending along the second direction under the contact, wherein the third conductive layer is in electric contact with the contact and is surrounded by a third dielectric layer.

The trench isolation structure electrically isolates the semiconductor layer under each memory stack.

Trench isolation structure is disposed under the first and the second isolation structures and aligns to the first and the second isolation structures.

In some implementations, the trench isolation structure is disposed under the dummy structure.

In some implementations, the first isolation structure further includes a gate line slit extending along the second direction and the third direction.

In some implementations, the first isolation structure electrically isolates the plurality of first conductive layers and the plurality of second conductive layers.

In another aspect, a system according to claim <NUM> is disclosed.

In still another aspect, a method for forming a 3D memory device according to claim <NUM> is disclosed.

In some implementations, the plurality of channel structures are formed in the first memory region, the second memory region, and the dummy region along the second direction.

In some implementations, the plurality of channel structures are formed in the first memory region and the second memory region. A contact structure is formed in the dummy region along the second direction.

In some implementations, a first gate line slit structure is formed in the first slit and a second gate line slit structure is formed in the second slit.

In some implementations, a second dielectric layer is formed in the first slit and a third dielectric layer is formed in the second slit.

In some implementations, an opening is formed in the semiconductor layer under the first isolation structure and the second isolation structure from a bottom side of the stack structure opposite to the upper side. A fourth dielectric layer is formed in the opening.

In some implementations, the first isolation structure electrically isolates the plurality of conductive layers between the first memory region and the dummy region, and the second isolation structure electrically isolates the plurality of conductive layers between the second memory region and the dummy region.

In some implementations, the third isolation structure electrically isolates the semiconductor layer under the first memory region and the dummy region, and the fourth isolation structure electrically isolates the semiconductor layer under the second memory region and the dummy region.

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present discloses.

The apparatus may be otherwise oriented (rotated <NUM> degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A 3D semiconductor device can be formed by stacking semiconductor wafers or dies and interconnecting them vertically so that the resulting structure acts as a single device to achieve performance improvements at reduced power and a smaller footprint than conventional planar processes. However, the charge lateral migration issue becomes a major issue of the 3D semiconductor device. In some 3D memory devices, such as 3D NAND memory devices, a stack of devices includes memory array devices and peripheral devices. As the shrinkage of the device size and thickness, the distance between the word lines becomes smaller and smaller. Hence, the charge lateral migration issue in the channel structure is one of the bottlenecks of the 3D NAND memory devices.

<FIG> illustrates a plan view of an exemplary 3D memory device <NUM>, according to some aspects of the present disclosure. As shown in <FIG>, 3D memory device <NUM> includes a plurality of planes and a dummy region is formed between two adjacent planes along the y-direction. In some implementations, 3D memory device <NUM> is divided into a first memory region <NUM>, a second memory region <NUM>, and a dummy region <NUM>. A first isolation structure <NUM> is disposed between first memory region <NUM> and dummy region <NUM>, and a second isolation structure <NUM> is disposed between second memory region <NUM> and dummy region <NUM>. First isolation structure <NUM> and second isolation structure <NUM> may extend along the x-direction and the z-direction. A plurality of channel structures <NUM> may be formed in first memory region <NUM> and second memory region <NUM>. Channel structures <NUM> may extend along the z-direction perpendicular to the x-direction and the y-direction. A plurality of dummy channel structures <NUM> may be formed in dummy region <NUM>. Similarly, dummy channel structures <NUM> may extend along the z-direction perpendicular to the x-direction and the y-direction.

<FIG> illustrates a cross-section of 3D memory device <NUM>, according to some aspects of the present disclosure. First memory region <NUM>, dummy region <NUM>, and second memory region <NUM> are arranged along the y-direction on a substrate <NUM>. In some implementations, substrate <NUM> is a semiconductor layer. In some implementations, substrate <NUM> may include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable materials. In some implementations, substrate <NUM> may be a thinned substrate (e.g., a semiconductor layer), which was thinned by grinding, wet/dry etching, chemical mechanical polishing (CMP), or any combination thereof.

First isolation structure <NUM> and second isolation structure <NUM> are formed between first memory region <NUM> and dummy region <NUM>, and between second memory region <NUM> and dummy region <NUM>. Each of first memory region <NUM> and second memory region <NUM> may include a plurality of first conductive layers <NUM> (such as the word lines) and a plurality of first dielectric layers <NUM> alternately stacked along the z-direction. In some implementations, dummy region <NUM> may include a plurality of conductive layers and a plurality of dielectric layers alternately stacked along the z-direction. In some implementations, the plurality of conductive layers and the plurality of dielectric layers formed in dummy region <NUM> may be formed in the same processes with first conductive layers <NUM> and first dielectric layers <NUM> in first memory region <NUM> and second memory region <NUM>. In other words, even though the conductive layers and the dielectric layers are divided in first memory region <NUM>, second memory region <NUM>, and dummy region <NUM>, the conductive layers and the dielectric layers may be formed together during the manufacturing process.

In some implementations, first conductive layers <NUM> may form the word lines and may include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some implementations, first dielectric layers <NUM> may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

In some implementations, channel structures <NUM> may include a semiconductor channel and a memory film formed over the semiconductor channel. The meaning of "over" here, besides the explanation stated above, should also be interpreted "over" something from the top side or from the lateral side. The memory film may be a multilayer structure and is an element to achieve the storage function in 3D memory device <NUM>. The memory film may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO). The ONO structure may be formed on the surface of the semiconductor channel, and the ONO structure (the memory film) is also located between the semiconductor channel and first conductive layers <NUM>, such as word lines. In some implementations, the semiconductor channel may include silicon, such as amorphous silicon, polysilicon, or single crystalline silicon.

In some implementations, dummy channel structures <NUM> may have the same structure with channel structures <NUM>, as shown in <FIG>. In some implementations, dummy channel structures <NUM> and channel structures <NUM> may have different structures, as shown in <FIG> or <FIG>.

In some implementations, first isolation structure <NUM> may extend along the z-direction and the x-direction between first memory region <NUM> and dummy region <NUM>, and second isolation structure <NUM> may extend along the z-direction and the x-direction between second memory region <NUM> and dummy region <NUM>. In some implementations, first isolation structure <NUM> and second isolation structure <NUM> may include a gate line slit structure. The gate line slit structure may extend along the z-direction through the memory stacks and may also extend along the x-direction to separate the memory stacks into multiple blocks. In some implementations, the gate line slit structure may include a slit contact, formed by filling the slit opening with conductive materials including but not limited to W, Co, Cu, Al, polysilicon, silicides, or any combination thereof. The gate line slit structure may further include a composite spacer disposed laterally between the slit contact and first conductive layers <NUM> and first dielectric layers <NUM> to electrically insulate the gate line slit structure from surrounding first conductive layers <NUM> (the gate conductors in the memory stacks). As a result, the gate line slit structure, including first isolation structure <NUM> and second isolation structure <NUM>, electrically separates the memory stacks in first memory region <NUM>, dummy region <NUM>, and second memory region <NUM>.

In some implementations, first isolation structure <NUM> and second isolation structure <NUM> may include a barrier structure formed by dielectric materials. The barrier structure may extend vertically along the z-direction through the memory stacks and may also extend laterally along the x-direction to separate the memory stacks into multiple blocks. In some implementations, the barrier structure may include one or multiple dielectric layers to electrically separates the memory stacks in first memory region <NUM>, dummy region <NUM>, and second memory region <NUM>.

As shown in <FIG>, 3D memory device <NUM> may further include a third isolation structure <NUM>. Third isolation structure <NUM> may be formed in substrate <NUM> extending along the z-direction. Third isolation structure <NUM> is a trench isolation structure formed in substrate <NUM>. In some implementations, third isolation structure <NUM> may be formed by dielectric materials. Third isolation structure <NUM> may electrically isolate substrate <NUM> in first memory region <NUM>, dummy region <NUM>, and second memory region <NUM>. When substrate <NUM> is formed by semiconductor materials, e.g., silicon, the well regions of the semiconductor substrate under different memory stacks need to be electrically isolated. In some implementations, third isolation structure <NUM> may align to first isolation structure <NUM> and second isolation structure <NUM> in the z-direction. In some implementations, third isolation structure <NUM> may not align to first isolation structure <NUM> and second isolation structure <NUM> in the z-direction, and the well regions of the semiconductor substrate under different memory stacks are isolated by third isolation structure <NUM>. By forming second isolation structure <NUM>, the well regions of substrate <NUM> under different memory stacks can be electrically isolated without a complicated structure.

<FIG> illustrates a cross-section of another exemplary 3D memory device <NUM>, according to some aspects of the present disclosure. The structure of 3D memory device <NUM> may be similar to the structure of 3D memory device <NUM>. However, 3D memory device <NUM> may include a fourth isolation structure <NUM>, which does not align to first isolation structure <NUM> or second isolation structure <NUM>.

As shown in <FIG>, fourth isolation structure <NUM> may be formed in substrate <NUM> extending along the z-direction. In some implementations, fourth isolation structure <NUM> may be formed by dielectric materials. Fourth isolation structure <NUM> may electrically isolate substrate <NUM> in first memory region <NUM>, and second memory region <NUM>. In some implementations, fourth isolation structure <NUM> may be formed in dummy region <NUM>. In some implementations, fourth isolation structure <NUM> may align to dummy channel structures <NUM>. In some implementations, fourth isolation structure <NUM> may not align to dummy channel structures <NUM>. By forming fourth isolation structure <NUM>, the well regions of substrate <NUM> under different memory stacks can be electrically isolated without a complicated structure.

<FIG> illustrates a cross-section of still another exemplary 3D memory device <NUM>, according to some aspects of the present disclosure. The structure of 3D memory device <NUM> may be similar to the structure of 3D memory device <NUM>. However, 3D memory device <NUM> does not include the dummy region.

As shown in <FIG>, first memory region <NUM> and second memory region <NUM> are arranged along the y-direction on a substrate <NUM>. In some implementations, substrate <NUM> may include silicon (e.g., single crystalline silicon), SiGe, GaAs, Ge, SOI, GOI, or any other suitable materials. In some implementations, substrate <NUM> may be a thinned substrate (e.g., a semiconductor layer), which was thinned by grinding, wet/dry etching, CMP, or any combination thereof. First isolation structure <NUM> is formed between first memory region <NUM> and second memory region <NUM>. Each of first memory region <NUM> and second memory region <NUM> may include first conductive layers <NUM> (such as the word lines) and first dielectric layers <NUM> alternately stacked along the z-direction. In some implementations, channel structures <NUM> may include a semiconductor channel, and a memory film formed over the semiconductor channel.

In some implementations, first isolation structure <NUM> may extend vertically along the z-direction and the x-direction between first memory region <NUM> and second memory region. In some implementations, first isolation structure <NUM> may include a gate line slit structure. The gate line slit structure may extend vertically along the z-direction through the memory stacks and may also extend laterally along the x-direction to separate the memory stacks into multiple blocks. In some implementations, the gate line slit structure may include a slit contact, formed by filling the slit opening with conductive materials including but not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof. The gate line slit structure may further include a composite spacer disposed laterally between the slit contact and first conductive layers <NUM> and first dielectric layers <NUM> to electrically insulate the gate line slit structure from surrounding first conductive layers <NUM> (the gate conductors in the memory stacks). As a result, the gate line slit structure electrically separates the memory stacks in first memory region <NUM> and second memory region <NUM>.

In some implementations, first isolation structure <NUM> may include a barrier structure formed by dielectric materials. The barrier structure may extend vertically along the z-direction through the memory stacks and may also extend laterally along the x-direction to separate the memory stacks into multiple blocks. In some implementations, the barrier structure may include one or multiple dielectric layers to electrically separates the memory stacks in first memory region <NUM> and second memory region <NUM>.

As shown in <FIG>, third isolation structure <NUM> may be formed in substrate <NUM> extending along the z-direction aligning to first isolation structure <NUM>. In some implementations, third isolation structure <NUM> may be formed in substrate <NUM> extending along the z-direction not aligning to first isolation structure <NUM>. In some implementations, third isolation structure <NUM> may be formed by dielectric material that may electrically isolate the well regions of the semiconductor substrate under different memory stacks. In some implementations, third isolation structure <NUM> may be formed by a conductive structure surrounded by dielectric layer and may electrically isolate the well regions of the semiconductor substrate under different memory stacks. By forming second isolation structure <NUM>, the well regions of substrate <NUM> under different memory stacks can be electrically isolated without a complicated structure.

<FIG> illustrates a cross-section of yet another exemplary 3D memory device <NUM>, according to some aspects of the present disclosure. <FIG> illustrates a plan view of 3D memory device <NUM>, according to some aspects of the present disclosure. For the purpose of better describing the present disclosure, the cross-section and the plan view of 3D memory device <NUM> in <FIG> and <FIG> will be discussed together.

3D memory device <NUM> is divided into first memory region <NUM>, second memory region <NUM>, and a dummy region <NUM>. First isolation structure <NUM> is disposed between first memory region <NUM> and dummy region <NUM>, and second isolation structure <NUM> is disposed between second memory region <NUM> and dummy region <NUM>. First isolation structure <NUM> and second isolation structure <NUM> may extend along the z-direction and the x-direction. Channel structures <NUM> may be formed in first memory region <NUM> and second memory region <NUM>. Channel structures <NUM> may extend along the z-direction perpendicular to the x-direction and the y-direction.

First memory region <NUM>, dummy region <NUM>, and second memory region <NUM> are arranged along the y-direction on substrate <NUM>. In some implementations, substrate <NUM> may include silicon (e.g., single crystalline silicon), SiGe, GaAs, Ge, SOI, GOI, or any other suitable materials. In some implementations, substrate <NUM> may be a thinned substrate (e.g., a semiconductor layer), which was thinned by grinding, wet/dry etching, CMP, or any combination thereof.

First isolation structure <NUM> is formed between first memory region <NUM> and dummy region <NUM>, and second isolation structure <NUM> is formed between second memory region <NUM> and dummy region <NUM>. Each of first memory region <NUM> and second memory region <NUM> may include first conductive layers <NUM> (such as the word lines) and dielectric layers <NUM> alternately stacked along the z-direction. In some implementations, dummy region <NUM> may include a plurality of conductive layers and a plurality of dielectric layers alternately stacked along the z-direction. In some implementations, the plurality of conductive layers and the plurality of dielectric layers formed in dummy region <NUM> may be formed in the same processes with first conductive layers <NUM> and first dielectric layers <NUM> in first memory region <NUM> and second memory region <NUM>. In other words, even though the conductive layers and the dielectric layers are divided in first memory region <NUM>, second memory region <NUM>, and dummy region <NUM>, the conductive layers and the dielectric layers may be formed together during the manufacturing process. In some implementations, the structures and materials of first conductive layers <NUM>, first dielectric layers <NUM>, channel structures <NUM>, first isolation structure <NUM>, and second isolation structure <NUM> of 3D memory device <NUM> may be similar to those of 3D memory device <NUM>.

3D memory device <NUM> further includes contact structures <NUM> formed in dummy region <NUM>. In some implementations, each contact structure <NUM> may include a first conductive contact <NUM> extending along the z-direction through conductive layers <NUM> and dielectric layers <NUM>. In some implementations, first conductive contact <NUM> may include W, Co, Cu, Al, polysilicon, silicides, or other suitable materials. Contact structures <NUM> may further include a spacer <NUM> disposed laterally between first conductive contact <NUM> and first conductive layers <NUM> and first dielectric layers <NUM> to electrically insulate first conductive contact <NUM> from surrounding first conductive layers <NUM> (the gate conductors in the memory stacks).

3D memory device <NUM> further includes a second conductive contact <NUM> formed under contact structures <NUM>. In some implementations, first conductive contact <NUM> is in direct contact with second conductive contact <NUM>. In some implementations, second conductive contact <NUM> may include W, Co, Cu, Al, polysilicon, silicides, or other suitable materials. By forming contact structures <NUM> in dummy block region <NUM>, dummy block region <NUM> may not only be used for electrically isolating first memory region <NUM> and second memory region <NUM> but also be used to provide conductive paths through the memory stacks and the silicon substrate. In some implementations, the conductive paths formed by contact structures <NUM> and second conductive contact <NUM> may be used to connect the peripheral device and 3D memory device <NUM>. For example, the source terminals of 3D memory device <NUM> may be connected to the peripheral device through the conductive paths formed by contact structures <NUM> and second conductive contact <NUM>, and therefore the peripheral device may control the operations of 3D memory device <NUM>. In some implementations, the conductive paths formed by contact structures <NUM> and second conductive contact <NUM> may be used to connected other devices disposed above, below, or aside 3D memory device <NUM>. In some implementations, the peripheral device may include one or more peripheral circuits. In some implementations, the peripheral circuits may be electrically connected to 3D memory device <NUM> through the conductive wires, such as the redistribution layers.

<FIG> illustrates a cross-section along line A in <FIG> of yet another exemplary 3D memory device <NUM>, according to some aspects of the present disclosure. <FIG> illustrates a plan view of 3D memory device <NUM>, according to some aspects of the present disclosure. For the purpose of better describing the present disclosure, the cross-section and the plan view of 3D memory device <NUM> in <FIG> and <FIG> will be discussed together.

3D memory device <NUM> is divided into first memory region <NUM>, second memory region <NUM>, and a dummy region <NUM>. First isolation structure <NUM> is disposed between first memory region <NUM> and dummy region <NUM>, and second isolation structure <NUM> is disposed between second memory region <NUM> and dummy region <NUM>. In addition, one or more than one fifth isolation structure <NUM> is also disposed in dummy region <NUM>, as shown in <FIG>. First isolation structure <NUM>, second isolation structure <NUM>, and fifth isolation structure <NUM> may extend along the x-direction and the z-direction. Channel structures <NUM> may be formed in first memory region <NUM> and second memory region <NUM>. Channel structures <NUM> may extend along the z-direction perpendicular to the x-direction and the y-direction. Dummy channel structures <NUM> may be formed in dummy region <NUM>. Similarly, dummy channel structures <NUM> may extend along the z-direction perpendicular to the x-direction and the y-direction.

First memory region <NUM>, dummy region <NUM>, and second memory region <NUM> are arranged along the y-direction on substrate <NUM>. Each of first memory region <NUM>, dummy region <NUM>, and second memory region <NUM> may include first conductive layers <NUM> (such as the word lines) and dielectric layers <NUM> alternately stacked along the z-direction. In some implementations, the structures and materials of first conductive layers <NUM>, first dielectric layers <NUM>, channel structures <NUM>, first isolation structure <NUM>, second isolation structure <NUM>, and third isolation structure <NUM> of 3D memory device <NUM> may be similar to those of 3D memory device <NUM>.

3D memory device <NUM> further includes a sixth isolation structure <NUM> disposed under dummy channel structures <NUM>. In some implementations, sixth isolation structure <NUM> may be formed in substrate <NUM> extending along the z-direction. In some implementations, the structure and material of sixth isolation structure <NUM> may be similar to those of third isolation structure <NUM>. 3D memory device <NUM> further includes a conductive contact <NUM> disposed under fifth isolation structure <NUM> in dummy block region <NUM>. In some implementations, conductive contact <NUM> is surrounded by a dielectric layer.

In some implementations, fifth isolation structure <NUM> may include a gate line slit structure. The gate line slit structure may extend vertically along the z-direction through the memory stacks, as shown in <FIG>, and may also extend laterally along the x-direction, as shown in <FIG>. In some implementations, the gate line slit structure may include a slit contact <NUM>, formed by filling the slit opening with conductive materials including but not limited to W, Co, Cu, Al, polysilicon, silicides, or any combination thereof. The gate line slit structure may further include a composite spacer <NUM> disposed laterally between the slit contact and first conductive layers <NUM> and first dielectric layers <NUM> to electrically insulate the gate line slit structure from surrounding first conductive layers <NUM> (the gate conductors in the memory stacks). As a result, the gate line slit structure electrically separates the memory stacks in first memory region <NUM>, dummy region <NUM>, and second memory region <NUM>.

By forming conductive contact <NUM> in dummy block region <NUM> in direct contact with fifth isolation structure <NUM>, slit contact <NUM> is in direct contact with conductive contact <NUM>. Hence, in dummy block region <NUM>, fifth isolation structure <NUM> and conductive contact <NUM> may provide conductive paths through the memory stacks and the silicon substrate.

3D memory device <NUM> is divided into first memory region <NUM>, second memory region <NUM>, and a dummy region <NUM>. First isolation structure <NUM> is disposed between first memory region <NUM> and dummy region <NUM>, and second isolation structure <NUM> is disposed between second memory region <NUM> and dummy region <NUM>. In some implementations, first isolation structure <NUM> and second isolation structure <NUM> may extend vertically along the z-direction between first memory region <NUM> and dummy region <NUM>, and between second memory region <NUM> and dummy region <NUM>. In some implementations, first isolation structure <NUM> and second isolation structure <NUM> may include a barrier structure formed by dielectric materials. The barrier structure may extend vertically along the z-direction through the memory stacks and may also extend laterally along the x-direction to separate the memory stacks into multiple blocks. In some implementations, the barrier structure may include one or multiple dielectric layers to electrically separates the memory stacks in first memory region <NUM>, dummy region <NUM>, and second memory region <NUM>.

In some implementations, the structures and materials of first conductive layers <NUM>, first dielectric layers <NUM>, channel structures <NUM>, and third isolation structure <NUM> of 3D memory device <NUM> may be similar to those of 3D memory device <NUM>. 3D memory device <NUM> further includes a seventh isolation structure <NUM> disposed in dummy region <NUM> extending vertically along the z-direction, and a conductive contact <NUM> disposed under seventh isolation structure <NUM> in dummy region <NUM>.

In some implementations, seventh isolation structure <NUM> may include a gate line slit structure. The gate line slit structure may extend vertically along the z-direction through the memory stacks and may also extend laterally along the x-direction. In some implementations, the gate line slit structure may include a slit contact, formed by filling the slit opening with conductive materials including but not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof. The gate line slit structure may further include a composite spacer disposed laterally between the slit contact and first conductive layers <NUM> and first dielectric layers <NUM> to electrically insulate the gate line slit structure from surrounding first conductive layers <NUM>.

Conductive contact <NUM> may be formed in substrate <NUM> under third isolation structure <NUM>. In some implementations, conductive contact <NUM> may be in direct contact with the slit contact of seventh isolation structure <NUM>. In some implementations, conductive contact <NUM> is surrounded by a dielectric layer. By forming conductive contact <NUM> in dummy region <NUM> in direct contact with seventh isolation structure <NUM>, the slit contact is in direct contact with conductive contact <NUM>. Hence, in dummy region <NUM>, seventh isolation structure <NUM> and conductive contact <NUM> may provide conductive paths through the memory stacks and the silicon substrate.

<FIG> illustrate cross-sections of 3D memory device <NUM> at different stages of a manufacturing process, according to some aspects of the present disclosure. <FIG> illustrates a flowchart of an exemplary method <NUM> for forming 3D memory device <NUM>, according to some aspects of the present disclosure. For the purpose of better describing the present disclosure, the cross-sections of 3D memory device <NUM> in <FIG> and method <NUM> in <FIG> will be discussed together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG> and <FIG>.

As shown in <FIG> and operation <NUM> in <FIG>, a stack structure including a plurality of first dielectric layers <NUM> and a plurality of sacrificial layers <NUM> is formed on substrate <NUM>. First dielectric layers <NUM> and sacrificial layers <NUM> are alternatingly arranged on substrate <NUM>. The dielectric/sacrificial layer pairs may extend along the y-direction. In some implementations, each first dielectric layer <NUM> may include a layer of silicon oxide, and each sacrificial layer <NUM> may include a layer of silicon nitride. First dielectric layers <NUM> and sacrificial layers <NUM> may be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some implementations, a pad oxide layer (not shown) is formed between the substrate and the stack structure by depositing dielectric materials, such as silicon oxide, on the substrate.

As shown in <FIG> and operation <NUM> in <FIG>, channel structures <NUM> and dummy channel structures <NUM> are formed in the stack structure along the z-direction. In some implementations, channel structures <NUM> and dummy channel structures <NUM> may have the same structure.

Each channel structure <NUM> or dummy channel structure <NUM> may include a semiconductor channel and a memory film formed over the semiconductor channel. In some implementations, a channel hole is formed in the stack structure along the z-direction. In some implementations, an etch process may be performed to form the channel hole in the stack structure that extends vertically (z-direction) through the interleaved dielectric/sacrificial layers. In some implementations, fabrication processes for forming the channel hole may include wet etching and/or dry etching, such as deep reactive ion etching (DRIE). In some implementations, the channel hole may extend further into the top portion of substrate <NUM>. Then, a blocking layer, a storage layer, a tunneling layer, and a semiconductor channel may be sequentially formed in the channel hole.

As shown in <FIG> and operation <NUM> in <FIG>, a first slit <NUM> and a second slit <NUM> are formed in the stack structure along the y-direction. The stack structure is zoned into first memory region <NUM>, second memory region <NUM>, and dummy region <NUM> by first slit <NUM> and second slit <NUM>. Dummy region <NUM> is disposed between first memory region <NUM> and second memory region <NUM>. First slit <NUM> is disposed between first memory region <NUM> and dummy region <NUM>, and second slit <NUM> is disposed between second memory region <NUM> and dummy region <NUM>. In some implementations, first slit <NUM> and second slit <NUM> may be formed by dry etch, wet etch, or other suitable processes.

As shown in <FIG> and operation <NUM> in <FIG>, the plurality of sacrificial layers <NUM> are replaced with the plurality of word lines (first conductive layers <NUM>). For example, sacrificial layers <NUM> may be removed by dry etch, wet etch, or other suitable processes to form a plurality of cavities. The word lines (first conductive layers <NUM>) may be formed in the cavities by depositing the gate conductor, and the gate conductor made from tungsten. In some implementations, the cavities may be filled with the gate dielectric layer made from high-k dielectric materials, the adhesion layer including titanium/titanium nitride (Ti/TiN) or tantalum/tantalum nitride (Ta/TaN).

Then, as shown in <FIG> and operation <NUM> in <FIG>, first isolation structure <NUM> and second isolation structure <NUM> may be formed in first slit <NUM> and second slit <NUM>. It is understood that first isolation structure <NUM> and second isolation structure <NUM> in <FIG> may be like or the same as first isolation structure <NUM> and second isolation structure <NUM> described above. In some implementations, a spacer <NUM> is formed along a sidewall of first slit <NUM> and second slit <NUM>. In some implementations, spacer <NUM> may include one or multiple layers of dielectric films. Then, a slit contact is formed by filling (e.g., depositing) conductive materials into the remaining space of first slit <NUM> and second slit <NUM> by PVD, CVD, ALD, any other suitable process, or any combination thereof. The slit contact may serve as a common source contact, according to some implementations. In some implementations, the slit contact may include conductive materials including, not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof.

As shown in <FIG>, a portion of substrate <NUM> is removed to form an opening <NUM>. In some implementations, the portion of substrate <NUM> may be removed by dry etch, wet etch, or other suitable processes. In some implementations, a thinning operation may be further performed to thin substrate <NUM> and a carrier wafer <NUM> may be used during the thinning operation. As shown in <FIG> and operation <NUM> in <FIG>, third isolation structure <NUM> is formed in opening <NUM> under first isolation structure <NUM> and second isolation structure <NUM>. In some implementations, third isolation structure <NUM> may be formed by dielectric material, and the dielectric material may also cover substrate <NUM>.

<FIG> illustrates a flowchart of another exemplary method <NUM> for forming 3D memory device <NUM>, according to some aspects of the present disclosure. As shown in operation <NUM> in <FIG>, a stack structure including a plurality of first dielectric layers <NUM> and a plurality of sacrificial layers <NUM> is formed on substrate <NUM>. First dielectric layers <NUM> and sacrificial layers <NUM> are alternatingly arranged on substrate <NUM>. The dielectric/sacrificial layer pairs may extend along the x-direction. In some implementations, each first dielectric layer <NUM> may include a layer of silicon oxide, and each sacrificial layer <NUM> may include a layer of silicon nitride. First dielectric layers <NUM> and sacrificial layers <NUM> may be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some implementations, a pad oxide layer (not shown) is formed between the substrate and the stack structure by depositing dielectric materials, such as silicon oxide, on the substrate.

As shown in operation <NUM> in <FIG>, channel structures <NUM> are formed in the stack structure along the y-direction. Each channel structure <NUM> may include a semiconductor channel and a memory film formed over the semiconductor channel. In some implementations, a channel hole is formed in the stack structure along the y-direction. In some implementations, an etch process may be performed to form the channel hole in the stack structure that extends vertically (y-direction) through the interleaved dielectric/sacrificial layers. In some implementations, fabrication processes for forming the channel hole may include wet etching and/or dry etching, such as DRIE. In some implementations, the channel hole may extend further into the top portion of substrate <NUM>. Then, a blocking layer, a storage layer, a tunneling layer, and a semiconductor channel may be sequentially formed in the channel hole.

As shown in operation <NUM> in <FIG>, a slit may be formed in the stack structure along the y-direction. The stack structure is zoned into first memory block region <NUM> and second memory block region <NUM> by the slit. In some implementations, the slit may be formed by dry etch, wet etch, or other suitable processes.

As shown in operation <NUM> in <FIG>, the plurality of sacrificial layers <NUM> are replaced with the plurality of word lines (first conductive layers <NUM>). For example, sacrificial layers <NUM> may be removed by dry etch, wet etch, or other suitable processes to form a plurality of cavities. The word lines (first conductive layers <NUM>) may be formed in the cavities by depositing the gate conductor, and the gate conductor made from tungsten. In some implementations, the cavities may be filled with the gate dielectric layer made from high-k dielectric materials, the adhesion layer including Ti/TiN or Ta/TaN.

As shown in operation <NUM> in <FIG>, first isolation structure <NUM> may be formed in the slit. In some implementations, a spacer is formed along a sidewall of the slit. In some implementations, the spacer may include one or multiple layers of dielectric films. Then, a slit contact is formed by filling (e.g., depositing) conductive materials into the remaining space of the slit by PVD, CVD, ALD, any other suitable process, or any combination thereof. The slit contact may serve as a common source contact, according to some implementations. In some implementations, the slit contact may include conductive materials including, not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof.

As shown in operation <NUM> in <FIG>, a portion of substrate <NUM> is removed to form an opening <NUM>, and second isolation structure <NUM> is formed in opening <NUM> under first isolation structure <NUM>. In some implementations, second isolation structure <NUM> may be formed by dielectric material, and the dielectric material may also cover substrate <NUM>.

By forming first isolation structure <NUM> and second isolation structure <NUM> between first memory block region <NUM> and second memory block region <NUM>, the word line (first conductive layers <NUM>) of different memory stacks may be isolated, and the well regions of substrate <NUM> under different memory stacks can also be electrically isolated without a complicated structure.

<FIG> illustrates a block diagram of an exemplary system <NUM> having a memory device, according to some aspects of the present disclosure. System <NUM> can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown in <FIG>, system <NUM> can include a host <NUM> and a memory system <NUM> having one or more memory devices <NUM> and a memory controller <NUM>. Host <NUM> can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host <NUM> can be configured to send or receive data to or from memory devices <NUM>.

Memory device <NUM> can be any memory device disclosed in the present disclosure. As disclosed above in detail, memory device <NUM>, such as a NAND Flash memory device, may have a controlled and predefined discharge current in the discharge operation of discharging the bit lines. Memory controller <NUM> is coupled to memory device <NUM> and host <NUM> and is configured to control memory device <NUM>, according to some implementations. Memory controller <NUM> can manage the data stored in memory device <NUM> and communicate with host <NUM>. For example, memory controller <NUM> may be coupled to memory device <NUM>, such as 3D memory device <NUM> described above, and memory controller <NUM> may be configured to control the operations of channel structure <NUM> through the peripheral device. By forming the structure according to the present disclosure, the area of 3D memory device <NUM> may be reduced by using the first isolation structures disclosed.

In some implementations, memory controller <NUM> is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller <NUM> is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller <NUM> can be configured to control operations of memory device <NUM>, such as read, erase, and program operations. Memory controller <NUM> can also be configured to manage various functions with respect to the data stored or to be stored in memory device <NUM> including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller <NUM> is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device <NUM>. Any other suitable functions may be performed by memory controller <NUM> as well, for example, formatting memory device <NUM>. Memory controller <NUM> can communicate with an external device (e.g., host <NUM>) according to a particular communication protocol. For example, memory controller <NUM> may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc..

Memory controller <NUM> and one or more memory devices <NUM> can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system <NUM> can be implemented and packaged into different types of end electronic products. In one example as shown in <FIG>, memory controller <NUM> and a single memory device <NUM> may be integrated into a memory card <NUM>. Memory card <NUM> can include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. Memory card <NUM> can further include a memory card connector <NUM> coupling memory card <NUM> with a host (e.g., host <NUM> in <FIG>). In another example as shown in <FIG>, memory controller <NUM> and multiple memory devices <NUM> may be integrated into an SSD <NUM>. SSD <NUM> can further include an SSD connector <NUM> coupling SSD <NUM> with a host (e.g., host <NUM> in <FIG>). In some implementations, the storage capacity and/or the operation speed of SSD <NUM> is greater than those of memory card <NUM>.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning of the disclosed implementations, based on the teaching and guidance presented herein.

Claim 1:
A three-dimensional (3D) memory device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), comprising:
a plurality of memory stacks comprising a first memory stack and a second memory stack arranged along a first direction, each memory stack comprising:
a plurality of first conductive layers (<NUM>) and a plurality of first dielectric layers (<NUM>) alternately stacked along a second direction perpendicular to the first direction; and
a channel structure (<NUM>) extending through the plurality of first conductive layers (<NUM>) and the plurality of first dielectric layers (<NUM>) along the second direction;
a dummy structure disposed between the first memory stack and the second memory stack, the dummy structure extending along a second direction perpendicular to the first direction and a third direction perpendicular to the first direction and the second direction;
a first isolation structure (<NUM>) disposed between the dummy structure and the first memory stack, the first isolation structure (<NUM>) extending along the second direction and the third direction;
a second isolation structure (<NUM>) disposed between the dummy structure and the second memory stack, the second isolation structure (<NUM>) extending along the second direction and the third direction;
a semiconductor layer disposed under the plurality of memory stacks, the dummy structure, the first isolation structure (<NUM>), and the second isolation structure (<NUM>); and
a trench isolation structure disposed in the semiconductor layer extending along the second direction and the third direction, wherein the trench isolation structure electrically isolates the semiconductor layer under each memory stack and wherein the trench isolation structure is disposed under the first and the second isolation structures (<NUM>) and aligns to the first and the second isolation structures (<NUM>).