Patent Description:
Integrated circuit technology has achieved great strides in advancing computing power through miniaturization of active and passive components. The package devices can be found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, etc. Packaging technology becomes cost-effective in high pin count devices and/or high production volume components. <CIT> discloses a semiconductor apparatus in which a wiring is disposed above operating regions of plural unit transistors arranged on a substrate in a first direction.

In today's radio frequency frontend (RFFE) modules, power amplifiers (PA) can take up substantial amount of real estate of the module. For example, a gallium arsenide (GaAs) PA can occupy about <NUM> X <NUM> area. Accordingly, there is a need for systems, apparatus, and methods that overcome the deficiencies of conventional PA designs including the methods, system and apparatus provided herein.

The following presents a simplified summary relating to one or more aspects and/or examples associated with the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview relating to all contemplated aspects and/or examples, nor should the following summary be regarded to identify key or critical elements relating to all contemplated aspects and/or examples or to delineate the scope associated with any particular aspect and/or example. Accordingly, the following summary has the sole purpose to present certain concepts relating to one or more aspects and/or examples relating to the apparatus and methods disclosed herein in a simplified form to precede the detailed description presented below. The invention concerns a semiconductor device according to claim <NUM> and a method of fabricating a semiconductor device according to claim <NUM>. Preferred aspects are given in the dependent claims.

An exemplary semiconductor device is disclosed. The semiconductor device may comprise a plurality of unit cells comprising a plurality of active devices on a substrate. The plurality of active devices may have a first width in a first direction and be aligned along a first length in a second direction. The semiconductor device may also comprise a first metal layer patterned to form a plurality of thermal pads on the plurality of active devices. The semiconductor device may further comprise a second metal layer patterned to form first and second thermal bump ends and a thermal bump connected therebetween. The thermal bump may have a second width in the first direction and a second length in the second direction. The thermal bump may be formed on the plurality of thermal pads. The semiconductor device may yet comprise a third metal layer patterned to form a thermal bar on the thermal bump. The semiconductor device may yet further comprise a thermal pillar formed on the thermal bar. The plurality of active devices may be thermally coupled to the thermal pillar through the plurality of thermal pads, the thermal bump, and the thermal bar. The first and second thermal bump ends each may have a width greater than the second width. A region between the first and second thermal bump ends may be divided into active and non-active regions. The active region may be a portion of the region occupied by the thermal bump, and the non-active region may be a remainder portion of the region. The second width and the second length of the thermal bump may be oriented such that the active region overlaps the first width and the first length of the plurality of active devices.

A method of fabricating a semiconductor device is disclosed. The method may comprise forming a plurality of unit cells comprising a plurality of active devices on a substrate. The plurality of active devices may have a first width in a first direction and be aligned along a first length in a second direction. The method may also comprise patterning a first metal layer to form a plurality of thermal pads on the plurality of active devices. The method may further comprise patterning a second metal layer to form first and second thermal bump ends and a thermal bump connected therebetween. The thermal bump may have a second width in the first direction and a second length in the second direction. The thermal bump may be formed on the plurality of thermal pads. The method may yet comprise patterning a third metal layer to form a thermal bar on the thermal bump. The method may yet further comprise forming a thermal pillar formed on the thermal bar. The plurality of active devices may be thermally coupled to the thermal pillar through the plurality of thermal pads, the thermal bump, and the thermal bar. The first and second thermal bump ends each may have a width greater than the second width. A region between the first and second thermal bump ends may be divided into active and non-active regions. The active region may be a portion of the region occupied by the thermal bump, and the non-active region may be a remainder portion of the region. The second width and the second length of the thermal bump may be oriented such that the active region overlaps the first width and the first length of the plurality of active devices.

Another exemplary semiconductor device is disclosed. The semiconductor device may comprise a plurality of unit cells comprising a plurality of active devices on a substrate. The plurality of active devices may have a first width in a first direction and be aligned along a first length in a second direction. The semiconductor device may also comprise a first metal layer patterned to form a plurality of thermal pads on the plurality of active devices. The semiconductor device may further comprise a second metal layer patterned to form first and second thermal bump ends and a thermal bump connected therebetween. The thermal bump may have a second width in the first direction and a second length in the second direction. The thermal bump may be formed on the plurality of thermal pads. The semiconductor device may yet comprise a thermal pillar formed on the thermal bump. The plurality of active devices may be thermally coupled to the thermal pillar through the plurality of thermal pads and the thermal bump. The first and second thermal bump ends each may have a width greater than the second width. A region between the first and second thermal bump ends may be divided into active and non-active regions. The active region may be a portion of the region occupied by the thermal bump, and the non-active region may be a remainder portion of the region. The second width and the second length of the thermal bump may be oriented such that the active region overlaps the first width and the first length of the plurality of active devices.

A method of fabricating a semiconductor device is disclosed. The method may comprise forming a plurality of unit cells comprising a plurality of active devices on a substrate. The plurality of active devices may have a first width in a first direction and be aligned along a first length in a second direction. The method may also comprise patterning a first metal layer to form a plurality of thermal pads on the plurality of active devices. The method may further comprise patterning a second metal layer to form first and second thermal bump ends and a thermal bump connected therebetween. The thermal bump may have a second width in the first direction and a second length in the second direction. The thermal bump may be formed on the plurality of thermal pads. The method may yet comprise forming a thermal pillar on the thermal bump. The plurality of active devices may be thermally coupled to the thermal pillar through the plurality of thermal pads and the thermal bump. The first and second thermal bump ends each may have a width greater than the second width. A region between the first and second thermal bump ends may be divided into active and non-active regions. The active region may be a portion of the region occupied by the thermal bump, and the non-active region may be a remainder portion of the region. The second width and the second length of the thermal bump may be oriented such that the active region overlaps the first width and the first length of the plurality of active devices.

Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description.

A more complete appreciation of aspects of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings which are presented solely for illustration and not limitation of the disclosure.

In accordance with common practice, the features depicted by the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily expanded or reduced for clarity. In accordance with common practice, some of the drawings are simplified for clarity. Thus, the drawings may not depict all components of a particular apparatus or method. Further, like reference numerals denote like features throughout the specification and figures.

Aspects of the present disclosure are illustrated in the following description and related drawings directed to specific embodiments. Alternate aspects or embodiments may be devised without departing from the scope of the teachings herein. Additionally, well-known elements of the illustrative embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings in the present disclosure.

In certain described example implementations, instances are identified where various component structures and portions of operations can be taken from known, conventional techniques, and then arranged in accordance with one or more exemplary embodiments. In such instances, internal details of the known, conventional component structures and/or portions of operations may be omitted to help avoid potential obfuscation of the concepts illustrated in the illustrative embodiments disclosed herein.

As indicated above, PAs can take up substantial amount of real estate of an RFFE module. For example, a GaAs PA can occupy about <NUM> X <NUM> area. Such a big design size can be costly as GaAs is more expensive than silicon (Si). To address such issues, it is proposed to reduce the size by patterning a thermal bump only, or substantially only over the active devices.

<FIG> illustrates an X-Y plane view of a conventional power amplifier (PA) <NUM>. As seen, the conventional PA <NUM> comprises a plurality of unit cells <NUM> formed on a substrate <NUM>. The plurality of unit cells <NUM> comprises a plurality of active devices (more on this below). The PA <NUM> also comprises first, second, and third metal layers <NUM>, <NUM>, <NUM> patterned on the substrate <NUM> and on the plurality of active devices. In the conventional PA <NUM>, a thermal bump <NUM> is formed with second and third metal layers <NUM>, <NUM>. A portion of the second metal layer, M2, <NUM> corresponding to the bump <NUM> is connected with the third metal layer, M3, <NUM> through a large via as illustrated in <FIG>.

<FIG> also illustrates an X-Y plane view of the conventional PA <NUM> to illustrate one or more issues associated with the conventional PA. In <FIG>, the thermal bump <NUM> is shown to be connected to first and second thermal bump ends <NUM>, <NUM>. A region between the first and second thermal bump ends <NUM>, <NUM> includes an active region <NUM> and a non-active region <NUM>. In this instance, the second metal layer <NUM>, from which the thermal bump <NUM> is formed, covers or overlaps both the active and non-active regions <NUM>, <NUM>. This means that a long feeding path to a base of a heterojunction bipolar transistor (an example of an active device) becomes necessary. This is mostly a wasted space under thermal bump <NUM>.

<FIG> illustrate an X-Y plane view of a semiconductor device <NUM>, e.g., a power amplifier, that addresses one or more issues of the conventional PA <NUM>. As seen, the semiconductor device <NUM> may comprise a plurality of unit cells <NUM> formed on a substrate <NUM>. The plurality of unit cells <NUM> comprises a plurality of active devices (again, more on this below). The plurality of active devices may have a first width in a first direction (e.g., X direction) and may be aligned along a first length in a second direction (e.g., Y direction) (not shown).

The semiconductor device <NUM> may also comprise first, second, and third metal layers <NUM>, <NUM>, <NUM> patterned on the substrate <NUM> and on the plurality of active devices (e.g., see also <FIG>, <FIG>, etc.). The first metal layer <NUM> may be patterned to form a plurality of thermal pads <NUM> on the plurality of active devices.

The second metal layer <NUM> may be patterned to form a thermal bump <NUM> on the plurality of thermal pads <NUM> (e.g., see <FIG>, <FIG>, etc.). Compared with the conventional PA <NUM>, the thermal bump <NUM> may be connected to the third metal layer <NUM> through a much smaller via as illustrated in <FIG>. The thermal bump <NUM> may have a second width in the first direction and a second length in the second direction.

The second metal layer <NUM> may also patterned to form first and second thermal bump ends <NUM>, <NUM> with the thermal bump <NUM> connected therebetween. The first and second thermal bump ends <NUM>, <NUM> may each have a width greater than the second width. Also, for ease of explanation, a region between the first and second thermal bump ends <NUM>, <NUM> may be divided into active and non-active regions <NUM>, <NUM>. The active region <NUM> may be viewed as being a portion of the region occupied by the thermal bump <NUM>, and the non-active region <NUM> may be viewed as being a remainder portion of the region. The second width and the second length of the thermal bump <NUM> may be oriented such that the active region <NUM> overlaps the first width and the first length of the plurality of active devices <NUM>. Indeed, the thermal bump <NUM> may completely overlap the plurality of active devices <NUM>. At a minimum, the second width of the thermal bump <NUM> may be equal or substantially equal to the first width of the plurality of active devices <NUM>.

The third metal layer, M3, may be patterned to form a thermal bar <NUM> (e.g., see <FIG>, <FIG>, <FIG>, etc.) on the thermal bump <NUM>. In an aspect, the plurality of active devices <NUM> are thermally coupled to the thermal pillar <NUM> through the plurality of thermal pads <NUM>, the thermal bump <NUM>, and the thermal bar <NUM>. For example, they may be in physical contact with each other. For example, the plurality of thermal pads <NUM> may be on and in contact with the plurality of active devices <NUM>. Alternatively, or in addition thereto, the thermal bump <NUM> may be on and in contact with the plurality of thermal pads <NUM>. Also alternatively or in addition thereto, the thermal bar <NUM> maybe on and in contact with the thermal bump <NUM>. Further alternatively or in addition thereto, the thermal pillar <NUM> maybe formed on and in contact with the thermal bar <NUM>.

<FIG> illustrate an X-Y plane view of another example semiconductor device in accordance with one or more aspects of the disclosure. In this example, the semiconductor device may also comprise one or more thermal fingers <NUM> formed from the second metal layer <NUM>. The one or more thermal fingers <NUM> may be connected to and extend from the thermal bump <NUM> in the first direction into the non-active region <NUM>. This can enhance thermal dissipation capabilities and increase mechanical robustness of the semiconductor device <NUM>.

Unit cell will be further described. <FIG> illustrate an X-Y plane view and cross-sectional views of a conventional unit cell <NUM> of a conventional power amplifier. As seen in <FIG>, the conventional unit cell <NUM> comprises a resistor <NUM>, an active device <NUM> and a capacitor <NUM> adjacent in the X direction from the active device <NUM>. Also shown are the active and non-active regions <NUM>, <NUM>. Further, widths of a thermal pillar <NUM>, a thermal bump <NUM>, and a thermal bar <NUM> are also illustrated. Note that in the conventional three metal layer unit cell <NUM>, all of the thermal bump <NUM>, the thermal bar <NUM>, and the thermal pillar <NUM> occupy both active and non-active regions <NUM>, <NUM>.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the non-active region <NUM>. In this cross-section, the conventional unit cell <NUM> comprises a substrate <NUM>, patterned first metal layer <NUM>, dielectric <NUM>, patterned second and third metal layers forming the conventional thermal bump <NUM> and thermal bar <NUM>, final passivation <NUM>, and thermal pillar <NUM>.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the active region <NUM>. In this cross-section, the unit cell <NUM> comprises the substrate <NUM>, transistor <NUM>, thermal pad <NUM>, the dielectric <NUM>, the thermal bump <NUM>, the thermal bar <NUM>, the final passivation <NUM>, and the thermal pillar <NUM>.

<FIG> illustrate an X-Y plane view and cross-sectional views of an example unit cell <NUM> of a semiconductor device <NUM> (e.g., a power amplifier (PA)) in accordance with one or more aspects of the disclosure. As seen in <FIG>, the unit cell <NUM> may comprise an active device <NUM> and a capacitor <NUM> adjacent in the first direction (e.g., X direction) from the active device <NUM>. The unit cell <NUM> may comprise one or more resistors <NUM> in addition to the active device <NUM> and the capacitor <NUM>.

Also shown are the active and non-active regions <NUM>, <NUM>. Further, widths of a thermal pillar <NUM>, a thermal bump <NUM> (e.g., formed from patterning second metal layer <NUM>), and a thermal bar (e.g., formed from patterning third metal layer <NUM>) are also illustrated. Note that unlike the conventional PA <NUM>, the thermal bump <NUM> covers or substantially covers only the active device <NUM>. This implies that the second width of the thermal bump <NUM> is equal to or substantially equal to the first width of the plurality of active devices <NUM>.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the non-active region <NUM>. In this cross-section, the unit cell <NUM> may comprise a substrate <NUM>, patterned first metal layer <NUM>, a dielectric <NUM>, the thermal bar <NUM> (e.g., formed from patterned third metal layer <NUM>), final passivation <NUM>, and thermal pillar <NUM>.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the active region <NUM>. In this cross-section, the unit cell <NUM> may comprise the substrate <NUM>, transistor <NUM>, the patterned first metal layer <NUM> on the substrate <NUM>, thermal pad <NUM> (e.g., formed from first metal layer <NUM>) on the transistor <NUM>, the dielectric <NUM>, the thermal bump <NUM>, the thermal bar <NUM>, the final passivation <NUM>, and the thermal pillar <NUM>.

Note that in <FIG>, the second metal layer <NUM> is still present in the non-active region <NUM> of the conventional unit cell <NUM>. However, in the example unit cell <NUM> of <FIG>, the second metal layer <NUM> is NOT present in the non-active region <NUM>. This enables desirable traits to be realized, as will be described further.

In an aspect, the active devices <NUM> of one or more unit cells <NUM> may be bipolar transistors such as heterojunction bipolar transistor (HBT), high electron mobility transistor (HEMT) such as pHEMT, etc. This is illustrated in <FIG>. The unit cell <NUM> of <FIG> may comprise similar components as the unit cell <NUM> of <FIG>. That is, the unit cell <NUM> of <FIG> may comprise an active device <NUM>, a capacitor <NUM> adjacent in the first direction (e.g., X direction) from the active device <NUM>, and one or more resistors <NUM>. Also shown are the active and non-active regions <NUM>, <NUM> and the widths of the thermal pillar <NUM>, the thermal bump <NUM>, and the thermal bar <NUM>.

In this instance, at least a portion of the capacitor <NUM> may be in the non-active region <NUM>, i.e., much closer to the active device <NUM>. This is enabled since the second metal layer <NUM> is not within the non-active region <NUM>. This enables a reduction in size of the semiconductor device <NUM> in the first direction (e.g., X direction). For example, the size reduction can be <NUM>-<NUM> in the first direction.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the non-active region <NUM>. In this cross-section, the unit cell <NUM> may include the capacitor <NUM>, which may comprise a lower plate <NUM>, an upper plate <NUM>, and a capacitor dielectric <NUM> between the lower and upper plates <NUM>, <NUM>. The first metal layer <NUM> may be patterned to form the lower plate <NUM>. The second metal layer <NUM> or some other metal layer may be patterned to form the upper plate <NUM>. That is, the upper plate <NUM> may be electrically coupled to or patterned from the second metal layer <NUM>. Above the upper plate <NUM>, the unit cell <NUM> may further comprise the thermal bar <NUM>, the final passivation <NUM>, and the thermal pillar <NUM>. A dielectric <NUM> may be formed between the upper plate <NUM> and the thermal bar <NUM>.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the active region <NUM>. This cross-section is similar to the cross-section illustrated in <FIG>.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" outside the active and non-active regions <NUM>, <NUM>. This cross-section illustrates the capacitor <NUM> as described with respect to <FIG>. But in this instance, the patterned third metal layer <NUM> may be electrically coupled with the upper plate <NUM>.

<FIG>, <FIG> illustrate an X-Y plane view and cross-sectional views of another example unit cell <NUM> of a semiconductor device in accordance with one or more aspects of the disclosure. Here, it may be assumed that that the active device <NUM> is a bipolar transistor such as an HBT. As seen in <FIG>, the transistor may comprise an emitter <NUM> and a collector <NUM>.

Again, the active and non-active regions <NUM>, <NUM> as well as the widths of the thermal pillar <NUM>, the thermal bump <NUM>, and the thermal bar <NUM> are shown. In this instance, at least a portion of the of the capacitor <NUM> may be in the non-active region <NUM>, i.e., much closer to the active device <NUM>. Thus, similar to the unit cell of <FIG>, a reduction in size of the semiconductor device <NUM> in the first direction (e.g., X direction) is enabled. In addition, one or more resistors <NUM> (e.g., ballasting resistors) may be in the non-active region <NUM> as well. Again, this is enabled since the second metal layer <NUM> is not within the non-active region <NUM>.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the non-active region <NUM>. This cross-section is similar to the cross-section illustrated in <FIG>, and thus will not be described further.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the region outside of the active and non-active regions <NUM>, <NUM>. This cross-section is similar to the cross-section illustrated in <FIG>, and thus will not be described further.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the active region <NUM>. As seen, the emitter may be thermally coupled to the thermal bump <NUM> through the thermal pad <NUM> corresponding to the active device <NUM>. Also, the collector may not be electrically coupled to the thermal bump <NUM>. A collector pad <NUM> may be formed on and electrically coupled with the collector. The collector pad <NUM> may comprise a first collector pad <NUM>, formed from patterned first metal layer <NUM>, may be on the collector. The collector pad <NUM> may also comprise a second collector pad <NUM>, formed from patterned second metal layer <NUM>, on the first collector pad <NUM>. This enables the current capacity of the collector to be enhanced. This in turn enables a reduction in the size of the semiconductor device <NUM> in the second direction (e.g., Y direction). The unit cell <NUM> may further comprise the dielectric <NUM>, the thermal bar <NUM>, the final passivation <NUM>, and the thermal pillar <NUM>.

Note that in <FIG>, the collector <NUM> may be formed on one or both sides of the emitter <NUM> in the second direction (e.g., in Y direction). This implies that the collector pad <NUM> may also be formed on one or both sides of the emitter <NUM> in the second direction. This means that the size reduction in the second direction can be from one or both sides of the emitter <NUM>.

Also as seen in <FIG>, note that the resistor <NUM> may be adjacent in the first direction (e. g, X direction) to the active device <NUM> of the unit cell <NUM>. At least a portion of the resistor <NUM> may be in the non-active region <NUM>. In an aspect, the capacitor <NUM> may be a ballasting capacitor. Alternatively, or in addition thereto, the resistor <NUM> may be a ballasting resistor.

Thus far, three metal layer semiconductor devices have been described. However, similar issues may also exist for two metal layer power amplifiers. Thus, the proposed solution may also apply to two metal layer semiconductor devices.

<FIG> illustrates an X-Y plane view of a conventional two metal layer power amplifier (PA) <NUM>. As seen, the conventional PA <NUM> comprises a plurality of unit cells <NUM> formed on a substrate <NUM>. The plurality of unit cells <NUM> comprises a plurality of active devices <NUM>. The PA <NUM> also comprises first and second metal layers <NUM>, <NUM> patterned on the substrate <NUM> and on the plurality of active devices. In the conventional PA <NUM>, a thermal bump <NUM> is formed with the second metal layer <NUM>. A portion of the second metal layer <NUM> corresponding to the thermal bump <NUM> is connected with the thermal pillar <NUM> through a large via as illustrated in <FIG>.

<FIG> also illustrates an X-Y plane view of the conventional PA <NUM>. In <FIG>, the thermal bump <NUM> is shown to be connected to first and second thermal bump ends <NUM>, <NUM>. A region between the first and second thermal bump ends <NUM>, <NUM> includes an active region <NUM> and a non-active region <NUM>. In this instance, the second metal layer <NUM> covers or overlaps both the active and non-active regions <NUM>. This means that a long feeding path to a base of a heterojunction bipolar transistor (an example of an active device) becomes necessary. This is mostly a wasted space under thermal bump <NUM>.

<FIG> illustrate an X-Y plane view of a semiconductor device <NUM>, e.g., a power amplifier, that addresses one or more issues of the conventional PA <NUM>. As seen, the semiconductor device <NUM> may comprise a plurality of unit cells <NUM> formed on a substrate <NUM>. The plurality of unit cells <NUM> comprises a plurality of active devices <NUM>. The plurality of active devices <NUM> may have a first width in a first direction (e.g., X direction) and may be aligned along a first length in a second direction (e.g., Y direction) (not shown).

The semiconductor device <NUM> may also comprise first and second metal layers <NUM>, <NUM> patterned on the substrate <NUM> and on the plurality of active devices <NUM>. The first metal layer <NUM> may be patterned to form a plurality of thermal pads <NUM> on the plurality of active devices <NUM>.

The second metal layer <NUM> may be patterned to form a thermal bump <NUM> on the plurality of thermal pads <NUM>. Compared with the conventional PA <NUM>, the thermal bump <NUM> may be connected to the thermal pillar <NUM> through a much smaller via as illustrated in <FIG>. The thermal bump <NUM> may have a second width in the first direction and a second length in the second direction.

The second metal layer <NUM> may also patterned to form first and second thermal bump ends <NUM>, <NUM> with the thermal bump <NUM> connected therebetween. The first and second thermal bump ends <NUM>, <NUM> may each have a width greater than the second width. A region between the first and second thermal bump ends <NUM>, <NUM> may be divided into active and non-active regions <NUM>, <NUM>. The active region may be viewed as being a portion of the region occupied by the thermal bump <NUM>, and the non-active region <NUM> may be viewed as being a remainder portion of the region. The second width and the second length of the thermal bump <NUM> may be oriented such that the active region <NUM> overlaps the first width and the first length of the plurality of active devices <NUM>. The thermal bump <NUM> may completely overlap the plurality of active devices <NUM>. At a minimum, the second width of the thermal bump <NUM> may be equal or substantially equal to the first width of the plurality of active devices <NUM>.

In an aspect, the plurality of active devices <NUM> are thermally coupled to the thermal pillar <NUM> through the plurality of thermal pads <NUM> and the thermal bump <NUM>. For example, they may be in physical contact with each other. For example, the plurality of thermal pads <NUM> may be on and in contact with the plurality of active devices <NUM>. Alternatively, or in addition thereto, the thermal bump <NUM> may be on and in contact with the plurality of thermal pads <NUM>. Also alternatively or in addition thereto, the thermal pillar <NUM> maybe on and in contact with the thermal bump <NUM>.

<FIG> illustrate an X-Y plane view of another example semiconductor device in accordance with one or more aspects of the disclosure. In this example, the semiconductor device may also comprise one or more thermal fingers <NUM> formed from the second metal layer <NUM>. The one or more thermal fingers <NUM> may be connected to and extend from the thermal bump <NUM> in the first direction into the non-active region <NUM>. This can enhance thermal dissipation capabilities and also increase mechanical robustness of the semiconductor device <NUM>.

For description of the unit cell in the two metal layer instance, <FIG> illustrate an X-Y plane view and cross-sectional views of a conventional unit cell <NUM> of a conventional power amplifier. As seen in <FIG>, the conventional unit cell <NUM> comprises a resistor <NUM>, an active device <NUM> and a capacitor <NUM> adjacent in the X direction from the active device <NUM>. Also shown are the active and non-active regions <NUM>, <NUM>. Further, widths of a thermal pillar <NUM> and a thermal bump <NUM> are also illustrated. Note that in the conventional two metal layer unit cell <NUM>, all of the thermal bump <NUM> and the thermal pillar <NUM> occupy both active and non-active regions <NUM>, <NUM>.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the non-active region <NUM>. Note this is also outside the width of the thermal pillar <NUM>. In this cross-section, the conventional unit cell <NUM> comprises a substrate <NUM>, patterned first metal layer <NUM>, thermal pad <NUM>, dielectric <NUM>, patterned second metal layer forming the conventional thermal bump <NUM>, final passivation <NUM>, and thermal pillar <NUM>.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the active region <NUM>. In this cross-section, the unit cell <NUM> comprises the substrate <NUM>, transistor <NUM>, the patterned first metal layer <NUM>, the dielectric <NUM>, the thermal bump <NUM>, the final passivation <NUM>, and the thermal pillar <NUM>.

<FIG> illustrate an X-Y plane view and cross-sectional views of an example unit cell <NUM> of a semiconductor device <NUM> (e.g., a power amplifier (PA)) in accordance with one or more aspects of the disclosure. As seen in <FIG>, the unit cell <NUM> may comprise an active device <NUM> and a capacitor <NUM> adjacent in the first direction (e.g., X direction) from the active device <NUM>. Also shown are the active and non-active regions <NUM>, <NUM> and the widths of the thermal pillar <NUM>, and the thermal bump <NUM>. In this instance, at least a portion of the of the capacitor <NUM> may be in the non-active region <NUM>, i.e., much closer to the active device <NUM>. This is enabled since the second metal layer <NUM> is not within the non-active region <NUM>.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the non-active region <NUM>. In this cross-section, the unit cell <NUM> may include the capacitor <NUM>, which may comprise a lower plate <NUM>, an upper plate <NUM>, and a capacitor dielectric <NUM> between the lower and upper plates <NUM>, <NUM>. The first metal layer <NUM> may be patterned to form the lower plate <NUM>. The second metal layer <NUM> or some other metal layer may be patterned to form the upper plate <NUM>. That is, the upper plate <NUM> may be electrically coupled to or patterned from the second metal layer <NUM>.

<FIG> illustrates a cross-section of the unit cell <NUM> along the line "<NUM>-<NUM>" in the active region <NUM>. In this cross-section, the unit cell <NUM> may comprise the substrate <NUM>, transistor <NUM>, the patterned first metal layer <NUM> on the substrate <NUM>, thermal pad <NUM> (e.g., formed from first metal layer <NUM>) on the transistor <NUM>, the dielectric <NUM>, the thermal bump <NUM>, the final passivation <NUM>, and the thermal pillar <NUM>.

The unit cell of <FIG> may be viewed as two metal layer version of the three metal layer unit cell of <FIG>. Thus, similar size reduction benefits may be achieved.

Plane views of some other example unit cells are illustrated in <FIG>. The unit cell <NUM> of <FIG> may be a two metal layer version of the three metal layer unit cell illustrated in <FIG>. Note that unlike the conventional two metal layer unit cell of <FIG>, the thermal bump <NUM> of the unit cell of <FIG> only over the active devices. It should be relatively straight forward to arrive at the unit cell <NUM> of <FIG>.

The unit cell of <FIG>, which includes a transistor comprising an emitter <NUM> and a collector <NUM>, may be a two metal layer version of the three metal layer unit cell illustrated in <FIG>. That is, at least a portion of the capacitor <NUM> may be in the non-active region <NUM>. As a result, size reduction in the first direction may be achieved. Alternatively, or in addition thereto, one or more resistors <NUM> may be within the non-active region <NUM> as well. Further alternatively or in addition thereto, current capacity of the active device (e.g., HBT) may be enhanced through electrically coupling the collector <NUM> with collector pad formed from first and second metal layers. Again, it should be relatively straight forward to arrive at the unit cell of <FIG>.

<FIG> illustrate example stages of fabricating a three metal layer unit cell of a semiconductor device. Each of these figures may be a view along any one or more of the lines "<NUM>-<NUM>", "<NUM>-<NUM>", or "<NUM>-<NUM>" of <FIG>, <FIG>, <FIG>.

<FIG> illustrates a stage in which transistor <NUM> (or active device <NUM> more generally) may be fabricated on substrate <NUM>.

<FIG> illustrates a stage in which first metal layer <NUM> may be deposited and patterned to form various components. For example, thermal pads <NUM> may be formed on the transistor <NUM>. The first metal layer <NUM> may be gold (Au), Au alloy, copper (Cu), aluminum (Al), etc., or any combination thereof. The first metal layer <NUM> may be formed by evaporation, plating, etch process, lift-off process, etc..

<FIG> illustrates a stage in which dielectric layer may be deposited and patterned to form the capacitor dielectric <NUM>, and a capacitor metal may be deposited and patterned to form the upper plate <NUM>. The capacitor dielectric may be formed from silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), etc., or any combination thereof. The capacitor dielectric may be formed by spin-coating, plasma-enhanced chemical vapor deposition (PECVD), sputtering, atomic layer deposition (ALD), etc. The capacitor metal may be Au, Au alloy, Cu, Al, etc., or any combination thereof. The first metal layer <NUM> may be formed by evaporation, plating, etch process, lift-off process, etc. In one aspect, the capacitor metal may be the second metal layer <NUM>. In another aspect, the capacitor metal may be metal separate from the second metal layer <NUM>.

<FIG> illustrate a stage in which a dielectric layer may be deposited and patterned to form the dielectric <NUM>. The dielectric layer may be SiO2, SiN, SiON, benzocyclobutene (BCB), polyimide, or any combination thereof. A thick layer may be preferable for better parasitic capacitance reduction. The dielectric layer may be formed by spin-coating, plasma-enhanced chemical vapor deposition (PECVD), sputtering, atomic layer deposition (ALD), etc..

<FIG> illustrates a stage in which the second metal layer <NUM> may be deposited and patterned to form the thermal bump <NUM>. The second metal layer <NUM> may be Au, Au alloy, Cu, Al, etc., or any combination thereof. The second metal layer <NUM> may be formed by evaporation, plating, etch process, lift-off process, etc..

<FIG> illustrates a stage in which a dielectric layer may be deposited and patterned to form the dielectric <NUM> in between second and third metal layers <NUM>, <NUM>, e.g., in between the thermal bump <NUM> and the thermal bar <NUM>. The dielectric layer may be SiO2, SiN, SiON, BCB, polyimide, or any combination thereof. A thick layer may be preferable for better parasitic capacitance reduction. The dielectric layer may be formed by spin-coating, PECVD, sputtering, ALD, etc..

<FIG> illustrates a stage in which the third metal layer <NUM> may be deposited and patterned to form various components. For example, the thermal bar <NUM> may be formed. The third metal layer <NUM> may be Au, Au alloy, Cu, Al, etc., or any combination thereof. The third metal layer <NUM> may be formed by evaporation, plating, etch process, lift-off process, etc..

<FIG> illustrates a stage in which a dielectric layer may be deposited and patterned to form the final passivation <NUM>. The final dielectric layer may be SiO2, SiN, SiON, BCB, polyimide, or any combination thereof. A thick layer may be preferable for better parasitic capacitance reduction. The final dielectric layer may be formed by spin-coating, PECVD, sputtering, ALD, etc..

<FIG> illustrates a stage in which the thermal pillar <NUM> may be formed. For example, a thick Cu layer may be electroplated to form the thermal pillar <NUM>. A seed layer <NUM> may be formed before forming the thermal pillar <NUM>, and a cap layer may be plated on the thermal pillar <NUM> to form a cap <NUM>. A high temperature reflow may follow the cap layer plating.

17A - 17J illustrate example stages of fabricating a three metal layer unit cell of a semiconductor device. Each of these figures may be a view along any one or more of the lines "<NUM>-<NUM>", "<NUM>-<NUM>", or "<NUM>-<NUM>" of <FIG>, <FIG>.

<FIG> illustrates a stage in which first metal layer <NUM> may be deposited and patterned to form various components. For example, thermal pads <NUM> may be formed on the transistor <NUM>. The first metal layer <NUM> may be Au, Au alloy, Cu, Al, etc., or any combination thereof. The first metal layer <NUM> may be formed by evaporation, plating, etch process, lift-off process, etc..

<FIG> illustrates a stage in which dielectric layer may be deposited and patterned to form the capacitor dielectric <NUM>, and a capacitor metal may be deposited and patterned to form the upper plate <NUM>. The capacitor dielectric may be formed from SiO2, SiN, SiON, Al2O3, etc., or any combination thereof. The capacitor dielectric may be formed by spin-coating, PECVD, sputtering, ALD, etc. The capacitor metal may be Au, Au alloy, Cu, Al, etc., or any combination thereof. The first metal layer <NUM> may be formed by evaporation, plating, etch process, lift-off process, etc. In one aspect, the capacitor metal may be the second metal layer <NUM>. In another aspect, the capacitor metal may be metal separate from the second metal layer <NUM>.

<FIG> illustrate a stage in which a dielectric layer may be deposited and patterned to form the dielectric <NUM>. The dielectric layer may be SiO2, SiN, SiON, BCB, polyimide, or any combination thereof. A thick layer may be preferable for better parasitic capacitance reduction. The dielectric layer may be formed by spin-coating, PECVD, sputtering, ALD, etc..

<FIG> illustrate a stage in which the second metal layer <NUM> may be deposited and patterned to form various components. For example, the thermal bump <NUM> may be formed. The second metal layer <NUM> may be Au, Au alloy, Cu, Al, etc., or any combination thereof. The second metal layer <NUM> may be formed by evaporation, plating, etch process, lift-off process, etc. In an aspect, the second metal layer <NUM> may be combined with a cap metal.

<FIG> illustrates a flow chart of an example method <NUM> of fabricating a semiconductor device such as a three metal layer power amplifier. Blocks of method <NUM> correspond to stages of <FIG>.

In block <NUM>, a plurality of unit cells may be formed. The plurality of unit cells may comprise a plurality of active devices on a substrate. The plurality of active devices may have a first width in a first direction and being aligned along a first length in a second direction.

In block <NUM>, a first metal layer may be patterned to form a plurality of thermal pads on the plurality of active devices.

In block <NUM>, a second metal layer may be patterned to form first and second thermal bump ends and a thermal bump connected therebetween. The thermal bump may have a second width in the first direction and a second length in the second direction. The thermal bump may be formed on the plurality of thermal pads.

In block <NUM>, a third metal layer may be patterned to form a thermal bar on the thermal bump.

In block <NUM>, a thermal pillar may be formed on the thermal bar. The plurality of active devices may be thermally coupled to the thermal pillar through the plurality of thermal pads, the thermal bump, and the thermal bar. The first and second thermal bump ends each may have a width greater than the second width. A region between the first and second thermal bump ends may be divided into active and non-active regions. The active region may be a portion of the region occupied by the thermal bump, and the non-active region may be a remainder portion of the region. The second width and the second length of the thermal bump may be oriented such that the active region overlaps the first width and the first length of the plurality of active devices.

<FIG> illustrates a flow chart of an example method <NUM> of fabricating a semiconductor device such as a two metal layer power amplifier.

In block <NUM>, a thermal pillar may be formed on the thermal bump. The plurality of active devices may be thermally coupled to the thermal pillar through the plurality of thermal pads, the thermal bump, and the thermal bar. The first and second thermal bump ends each may have a width greater than the second width. A region between the first and second thermal bump ends may be divided into active and non-active regions. The active region may be a portion of the region occupied by the thermal bump, and the non-active region may be a remainder portion of the region. The second width and the second length of the thermal bump may be oriented such that the active region overlaps the first width and the first length of the plurality of active devices.

It will be appreciated that the foregoing fabrication processes and related discussion were provided merely as a general illustration of some of the aspects of the disclosure and is not intended to limit the disclosure. Further, many details in the fabrication process known to those skilled in the art may have been omitted or combined in summary process portions to facilitate an understanding of the various aspects disclosed without a detailed rendition of each detail and/or all possible process variations. Further, it will be appreciated that the illustrated configurations and descriptions are provided merely to aid in the explanation of the various aspects disclosed herein. For example, the number and location of the MIM capacitors and/or inductors, the metallization structure may have more or less conductive and insulating layers, the cavity orientation, size, whether it is formed of multiple cavities, is closed or open, and other aspects may have variations driven by specific application design features, such as the number of antennas, antenna type, frequency range, power, etc. Accordingly, the forgoing illustrative examples and associated figures should not be construed to limit the various aspects disclosed and the scope of the invention is set forth in the claims.

<FIG> illustrates various electronic devices <NUM> that may be integrated with any of the aforementioned semiconductor device in accordance with various aspects of the disclosure. For example, a mobile phone device <NUM>, a laptop computer device <NUM>, and a fixed location terminal device <NUM> may each be considered generally user equipment (UE) and may include the semiconductor device as described herein. The devices <NUM>, <NUM>, <NUM> illustrated in <FIG> are merely exemplary. Other electronic devices may also include the RF filter including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), an Internet of things (IoT) device or any other device that stores or retrieves data or computer instructions or any combination thereof.

The foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc.) stored on computer-readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products may include semiconductor wafers that are then cut into semiconductor die and packaged into an antenna on glass device. The antenna on glass device may then be employed in devices described herein.

As used herein, the terms "user equipment" (or "UE"), "user device," "user terminal," "client device," "communication device," "wireless device," "wireless communications device," "handheld device," "mobile device," "mobile terminal," "mobile station," "handset," "access terminal," "subscriber device," "subscriber terminal," "subscriber station," "terminal," and variants thereof may interchangeably refer to any suitable mobile or stationary device that can receive wireless communication and/or navigation signals. These terms include, but are not limited to, a music player, a video player, an entertainment unit, a navigation device, a communications device, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an automotive device in an automotive vehicle, and/or other types of portable electronic devices typically carried by a person and/or having communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices which communicate with another device that can receive wireless communication and/or navigation signals such as by short-range wireless, infrared, wireline connection, or other connection, regardless of whether satellite signal reception, assistance data reception, and/or position-related processing occurs at the device or at the other device. In addition, these terms are intended to include all devices, including wireless and wireline communication devices, that are able to communicate with a core network via a radio access network (RAN), and through the core network the UEs can be connected with external networks such as the Internet and with other UEs. Of course, other mechanisms of connecting to the core network and/or the Internet are also possible for the UEs, such as over a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE <NUM>, etc.) and so on. UEs can be embodied by any of a number of types of devices including but not limited to printed circuit (PC) cards, compact flash devices, external or internal modems, wireless or wireline phones, smartphones, tablets, tracking devices, asset tags, and so on. A communication link through which UEs can send signals to a RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). A communication link through which the RAN can send signals to UEs is called a downlink or forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). As used herein the term traffic channel (TCH) can refer to either an uplink / reverse or downlink / forward traffic channel.

The wireless communication between electronic devices can be based on different technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), <NUM> New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE <NUM> (WiFi), and IEEE <NUM>. <NUM> (Zigbee/Thread) or other protocols that may be used in a wireless communications network or a data communications network. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Special Interest Group intended to provide considerably reduced power consumption and cost while maintaining a similar communication range. BLE was merged into the main Bluetooth standard in <NUM> with the adoption of the Bluetooth Core Specification Version <NUM> and updated in Bluetooth <NUM>.

" Any details described herein as "exemplary" is not to be construed as advantageous over other examples. Likewise, the term "examples" does not mean that all examples include the discussed feature, advantage or mode of operation. Furthermore, a particular feature and/or structure can be combined with one or more other features and/or structures. Moreover, at least a portion of the apparatus described herein can be configured to perform at least a portion of a method described herein.

It should be noted that the terms "connected," "coupled," or any variant thereof, mean any connection or coupling, either direct or indirect, between elements, and can encompass a presence of an intermediate element between two elements that are "connected" or "coupled" together via the intermediate element unless the connection is expressly disclosed as being directly connected.

Any reference herein to an element using a designation such as "first," "second," and so forth does not limit the quantity and/or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and/or instances of an element. Also, unless stated otherwise, a set of elements can comprise one or more elements.

Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques.

Claim 1:
A semiconductor device (<NUM>), comprising:
a plurality of unit cells (<NUM>) comprising a plurality of active devices (<NUM>) on a substrate, the plurality of active devices having a first width in a first direction and being aligned along a first length in a second direction;
a first metal layer (<NUM>, <NUM>, <NUM>, <NUM>) patterned to form a plurality of thermal pads on the plurality of active devices;
a second metal layer (<NUM>, <NUM>, <NUM>, <NUM>) patterned to form first and second thermal bump ends (<NUM>, <NUM>) and a thermal bump (<NUM>) connected therebetween, the thermal bump having a second width in the first direction and a second length in the second direction, the thermal bump being formed on the plurality of thermal pads (<NUM>); and
a thermal pillar (<NUM>) formed on the thermal bump,
wherein the plurality of active devices are thermally coupled to the thermal pillar through the plurality of thermal pads and the thermal bump,
wherein the first and second thermal bump ends each has a width greater than the second width, a region between the first and second thermal bump ends being divided into active and non-active regions, the active region being a portion of the region occupied by the thermal bump, and the non-active region being a remainder portion of the region, and
wherein the second width and the second length of the thermal bump is oriented such that the active region overlaps the first width and the first length of the plurality of active devices.