Patent Description:
The present application relates to transmitter (TX) side analog front-end (AFE) design, specifically, the output driver implementation.

Modern microprocessors operate on relatively large words. For example, conventionally, some processors process <NUM>-bit words. As the processor clock rate increases more than before, the routing of such relatively wide words on the wide bit bus becomes problematic. At high transmission rates, the inevitable skew associated with propagation on separate traces on a wide bit bus may cause unacceptable bit error rates. Furthermore, such buses may require large amounts of power and may be expensive to design.

Serializer-deserializer (SerDes) systems have been developed to enable high-speed transmission of data words without the skew and distortion problems associated with high-speed wide bit buses. The SerDes transmitter serializes the data word into a high-speed serial data stream. The corresponding SerDes receiver receives the high-speed serial data stream and deserializes it into parallel data words. Serial transmission is usually differential and may include an embedded clock. Thus, the skew and distortion problems associated with high-speed wide bit data buses may be reduced.

A voltage-mode transmitter transmits an output signal by either charging or discharging an output terminal depending upon the binary value of the bit to be transmitted. To prevent reflections and other undesired effects, the voltage-mode transmitter may be impedance matched to the transmission line coupled to the output terminal. Some examples perform this impedance matching by selecting from a number of selectable slices in the voltage-mode transmitter. Each selected slice contributes to the charging and discharging of the output terminal whereas the unselected slices show high impedance to the output terminal.

In high-speed SerDes design, some drivers may calibrate output resistance in a digital way. A unit slice resistance is designed. A digital loop is running to determine how many slice numbers to use. The unit slice resistance is divided by the slice number to obtain, for example, a <NUM> Ohm matching resistance. In this way the slice number can vary over process, voltage, temperature (PVT) corners. Looking at a "slow-slow-slow" (SSS) corner, it may use the maximum number of slices because at this corner, the unit slice resistance is at its maximum value. Thus, the total slice number is set large enough to accommodate expected corner variations. In such driver designs, output capacitance may be large because the number of slices is large enough to cover each expected corner. In very high-speed SerDes design, bandwidth may dominate the driver performance. This may put a heavy burden on pre-driver design, in which a pre-driver may consume a large amount of power because it sends signals to each of the slices.

The unit slice resistance, Req, includes two parts: p-type metal oxide semiconductor (PMOS)/n-type metal oxide semiconductor (NMOS) Ron resistance and real resistance. Req varies over PVT corners. The number of slices is decided by a calibration loop, based on the Req value. The larger the Req value is, the larger the slice number is in use. The output signals may experience a large output capacitance due to a large number of slices. The input signals, which are from pre-driver, may also see a large gate capacitance. All this may induce bandwidth limitation.

When using a four-level pulse amplitude modulation (PAM4) design, the Most-Significant-Bit (MSB) data and Least-Significant-Bit (LSB) data may go to separate driver slices. And the ratio of MSB slice numbers to LSB slice numbers is <NUM>:<NUM>. At each PVT corner, the calibration loop gives different slice numbers in use. The digital calibration loop may not be able to guarantee the slices can be exactly divided into ratio <NUM>:<NUM> over PVT corners. Thus, there may be resistance-matching resolution loss for digital calibration loops.

Attention is drawn to <CIT> relating to a voltage-mode transmitter. The transmitter includes configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice includes driver transistors which drive an output value. The outputs of each driver slice are directly or capacitively coupled with the transmitter's outputs. Each driver slice also includes one or more impedance-matching transistors which are serially coupled to at least some of the driver transistors. The configuration circuitry configures a subset of driver slices so that the down (or up) impedance of the transmitter is within a first tolerance of a desired impedance value. The bias circuitry biases the one or more impedance-matching transistors in each driver slice in the subset of driver slices so that the up (or down) impedance is within a second tolerance of the down (or up) impedance.

Further attention is drawn to <CIT> relating to an output circuit providing an adjustable output amplitude and common-mode voltage. The output circuit includes a driver circuit and a common-mode feedback circuit including a first replica circuit of the at least one driver circuit. The common-mode feedback circuit is coupled to receive a first bias and provide an output coupled to the at least one driver circuit. The output circuit also includes a current circuit having a configurable resistor and a second replica circuit of the at least one driver circuit. The current circuit is coupled to receive a second bias and to provide an output coupled to the driver circuit and the common-mode feedback circuit.

Attention is also drawn to <CIT> relating to a driver circuit including a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

Attention is also drawn to <CIT> relating to reducing the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism is instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.

According to one implementation, a semiconductor chip includes: a driver circuit including a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit and a second signal generator circuit; a first bias circuit replicating the first signal generator circuit, the first bias circuit coupled to a first p-type metal oxide semiconductor (PMOS) transistor of the first signal generator circuit and coupled to a second PMOS transistor of the first signal generator circuit; and a second bias circuit replicating the second signal generator circuit, the second bias circuit coupled to a first n-type metal oxide semiconductor (NMOS) transistor of the second signal generator circuit and coupled to a second NMOS transistor of the second signal generator circuit.

According to yet another implementation, a data transmitter in a semiconductor chip includes: a plurality of driver slices coupled in parallel to a serial data output, each one of the driver slices including: first means for driving a first portion of a differential data signal; and second means for driving a second portion of the differential data signal; and means for matching an output resistance of the data transmitter to a resistance of a transmission line, the matching means including: a first bias circuit replicating a first portion of the first means, the first bias circuit coupled to a first p-type metal oxide semiconductor (PMOS) transistor of the first portion of the first means and coupled to a second PMOS transistor of the first portion of the first means; and a second bias circuit replicating a second portion of the first means, the second bias circuit coupled to a first n-type metal oxide semiconductor (NMOS) transistor of the second portion of the first means and coupled to a second NMOS transistor of the second portion of the first means.

According to principles described herein, a driver circuit for a data transmitter is improved to maintain consistent performance across process, voltage, and temperature (PVT) corners. The driver circuit may be used in a transmitter (TX) side analog front-end (AFE) design. Various modulation schemes may be used for SerDes systems. One such scheme is a <NUM>-Gb/s signaling system using a four-level pulse amplitude modulation (PAM4) format. Different from traditional calibrating on driver termination resistance, an analog technique is described herein to obtain matching resistance. According to some principles described herein the number of active driver slices is fixed over PVT corners. This is in contrast to other methods in which the number of active driver slices is digitally controlled so that different numbers of driver slices can be activated, turned on, or selected at different PVT corners.

In this example, a driver slice includes one unit of a set of identical, parallel pieces of hardware (circuits) that are used to perform the driver function. Simulations using some implementations of the circuits described herein with respect to <FIG> are proven more robust to PVT variations, alleviating output capacitance, as well as saving power and layout routing effort in high-speed pre-driver buffer design.

According to some principles described herein, a driver slice design uses an analog method to calibrate the Req resistance of each slice to provide a desired value for driver output resistance (<NUM> Ohms, for example). For instance, a data transmitter may include a plurality of parallel driver slices. Focusing on one slice first, it has four different signal generator circuits - two signal generator circuits associated with a p portion of the differential signal and two signal generator circuits associated with an n portion of the differential signal.

A first one of the signal generator circuits is implemented using multiple transistors and a resistor. Two of the transistors may be in parallel and coupled to a source of a transistor that receives the input data. The two transistors arranged in parallel may be maintained in their triode region, whereas the transistor that receives the input data is turned on and off according to whether the input data signal is a digital <NUM> or a digital <NUM>. The resistor may be in series with the transistor that receives the data.

A bias circuit includes replica transistors of the transistors in the signal generator circuit and may also include a replica of the resistor. The bias circuit includes an operational amplifier (op amp) arranged in a feedback loop to maintain a resistance of the replica transistors and resistor at a desired level. A gate voltage of one of the replica transistors may be provided as a bias voltage to one of the parallel transistors. The other one of the parallel transistors may be maintained in its triode region by use of another bias voltage generated from a bias circuit.

Of course, that is just one signal generator circuit out of four that are included in the driver slice. Each one of the different signal generator circuits may be biased in the same or similar manner. The result is that the resistance of a given driver slice may be maintained at a desired level. Collectively, the parallel driver slices may each be maintained at the desired resistance to provide a driver output resistance that matches a resistance of the transmission line.

An advantage of some implementations is that they use a fixed number of driver slices and, thus, the number of driver slices may be chosen to provide a desired ratio between most significant bits and least significant bits for a given transmission protocol. Therefore, resolution loss that may be associated with digital loops that turn on or off some of the slices may be minimized or avoided. Another advantage of some implementations is that the number of driver slices may be chosen to balance a desired bandwidth with a parasitic capacitance associated with the number of driver slices.

Another advantage is that the number of driver slices may be chosen to either reduce a size of pre-drivers in the system or to reduce loading on the pre-drivers in the system. By contrast, some systems that might increase a number of slices enabled to operate at some PVT corners may undesirably increase a load on pre-drivers or may require larger pre-drivers at the design stage to accommodate the PVT corners.

<FIG> is an illustration of an example data transmitting and receiving system <NUM>, according to one implementation. System <NUM> includes serializer <NUM>, which receives data as parallel bits and outputs the data as serial bits. In this example, the serializer <NUM> arranges the bits into two serial streams-a stream for the most significant bits (MSBs) and a stream for the least significant bits (LSBs). The use of a MSB stream and a LSB stream may be associated with PAM4, though the scope of implementations may include any modulation technique and thus may include more or fewer streams from serializer <NUM>.

System <NUM> also includes a transmitter <NUM>, which itself includes pre-drivers <NUM>, <NUM> and driver slices <NUM>. Pre-drivers <NUM>, <NUM> raise a signal level of the serial data streams to a first level that is higher than the level received from serializer <NUM>, but lower than the level output by driver slices <NUM>. Driver slices <NUM> may include a plurality of driver slices arranged in parallel. In the example of <FIG>, the MSB data stream is received from pre-driver <NUM>, and the LSB data stream is received from pre-driver <NUM>. Further in this example, the number of parallel data slices associated with the MSB stream is twice the number of parallel data slices associated with the LSB stream. The <NUM>:<NUM> ratio may be associated with PAM4, though the scope of implementations is not limited to any particular modulation technique and, thus, different ratios may be used in different applications.

In one example, the number of parallel data slices coupled with pre-driver <NUM> may include fourteen, and the number of parallel data slices coupled with pre-driver <NUM> may include seven, thereby providing a <NUM>:<NUM> ratio. The scope of implementations is not limited to any number of parallel data slices. For instance, another implementation may use <NUM> parallel data slices total or may use <NUM> parallel data slices total; however, those implementations with more parallel data slices may include a larger parasitic capacitance and may use larger pre-drivers <NUM>, <NUM>. Various other transmitter designs may include an appropriate number of parallel data slices to balance resolution, bandwidth, pre-driver size, and other relevant factors.

Transmitter <NUM> has a termination resistance that matches a characteristic resistance of the transmission channel <NUM>. The scope of implementations is not limited to any transmission channel resistance, though in the examples below, the transmission channel resistance is assumed to be <NUM> Ohms. Therefore, the analog resistance-setting technique for the driver slices is designed to set each of the driver slices so that a collective output resistance of the full set of driver slices in parallel is a matching <NUM> Ohms. Although not shown in <FIG>, implementations described herein include bias circuits, such as those described below with respect to <FIG> and <FIG>, which use analog control loops to set a desired resistance for each of the driver slices <NUM>. The bias circuits may be built proximate the driver slices <NUM> and on a same semiconductor substrate.

Transmitter <NUM> transmits high-speed, serialized digital data to the transmission channel <NUM> as a series of high and low voltage values. In this example, the signal is a differential signal having two parts (Outp and Outn).

Transmission channel <NUM> provides a data link between transmitter <NUM> and receiver <NUM>, which includes equalizer <NUM> and deserializer <NUM>. Transmission channel <NUM> may be embodied in any appropriate structure, for example, a cable, a metal trace on a printed circuit board, a metal wire connecting chips in a package, and the like. In <FIG>, transmission channel <NUM> is shown as a transmission line in order to emphasize its similarities with transmission lines in general, including having a characteristic resistance as well as a Resistance-Capacitance (RC) time constant.

Equalizer <NUM> receives the transmitted data signal from transmission channel <NUM> and acts to reshape the received data signal, where the received data signal may be distorted due to transmission line reflections, RC attenuation, or other phenomena. Equalizer <NUM> is used by the system <NUM> to reshape the digital signal so that it is output from the equalizer <NUM> in a form that more closely matches the approximately square wave shape of the signal at the output of transmitter <NUM>. After being reshaped by equalizer <NUM>, signals go to deserializer <NUM>, after which the serial high-speed data become parallel low speed output.

Digital circuitry <NUM> may include a flip-flop or other data recovery circuit to capture the values of the data signal as it appears at the data output port of the equalizer <NUM>. Use of the equalizer circuit <NUM> to reshape the digital signal, including applying an appropriate gain, may reduce the risk of errors in capturing the data signal.

<FIG> is an illustration of an example application of the signal transmission systems of <FIG> and <FIG>, according to one implementation. <FIG> illustrates a system <NUM> in which a system on a chip (SOC) <NUM> is in communication with a memory chip <NUM>. SOC <NUM> communicates with memory chip <NUM> over transmission channels <NUM>.

SOC <NUM> includes a multitude of processing units (not shown) implemented in a chip. The processing units may include any appropriate computing device, where examples include a mobile station modem, a multi-core central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a <NUM>. 11x modem, and/or the like. In some examples, SOC <NUM> is specifically made for a mobile device, such as a smart phone, such that the cores are designed for low power consumption. However, the scope of implementations is not limited to any specific SOC architecture.

Memory chip <NUM> in this example includes any appropriate memory chip for use in a computing device with SOC <NUM>. Examples include a Static Random Access Memory (SRAM) chip, a Dynamic Random Access Memory (DRAM) chip, a Synchronous Dynamic Random Access Memory (SDRAM), and an electrically erasable programmable read-only memory (Flash memory) chip, although the scope of implementations is not limited to any particular memory chip. During a write operation, memory chip <NUM> receives data from SOC <NUM> over transmission channels <NUM>, and a memory controller at memory chip <NUM> then stores that data in memory cells of the memory chip. During a read operation, memory chip <NUM> receives a read request for specific data from SOC <NUM>, and the memory controller of memory chip <NUM> then accesses the data from various memory cells of the memory chip and transmits those bits of data to the SOC <NUM> over transmission channels <NUM>.

The system of <FIG> may include implementations of the systems shown in <FIG> and <FIG>. In one example, system <NUM> of <FIG> is operated according to one or more DDR standards, where memory chip <NUM> is a DDR SDRAM chip. Memory chip <NUM> includes a multitude of receiver circuits configured to receive data over respective transmission channels <NUM>. It is expected that there would be many receivers and many transmitters at memory chip <NUM>, so the transmitters and receivers are shown collectively at TX/RX circuit <NUM>. Each one of the transmitter circuits operates as described above with respect to <FIG> and <FIG>, including having bias - controlled driver slices that operate as described with respect to method <NUM> of <FIG>. Each one of the individual transmission channels <NUM> are the same as or similar to transmission channel <NUM> of <FIG>, including having a characteristic resistance and a frequency response.

Similarly, SOC <NUM> also has a multitude of receiver circuits configured to receive data over respective transmission channels <NUM>. Transmitters and receivers of SOC <NUM> are shown collectively in this example as TX/RX circuit <NUM>. Each one of the receiver circuits operates as described above with respect to <FIG>. Furthermore, the transmitter circuits in each of TX/RX circuits <NUM> and <NUM> may have a similar structure to transmitter circuit <NUM> of <FIG>.

<FIG> shows an example driver <NUM>, according to one implementation. The driver <NUM> includes a multitude of slices <NUM>-<NUM>, with the circuitry of slice <NUM> shown in detail. It is understood that the other slices <NUM>-<NUM> would be implemented similarly. According to the present example, the number of slices <NUM>-<NUM> may be fixed, for example, at <NUM>. In one example, the number of slices <NUM>-<NUM> is set to be divisible by three so that the number of slices for the MSB data can be twice the number of slices for the LSB data.

In some implementations, the unit slice resistance is fixed to a specific value, for example 1KOhm. It is designed not to change over PVT corners. Thus, the slice number is also fixed, for example, <NUM>. Continuing with the example, <NUM> slices arranged in parallel, where each slice has an output resistance of <NUM> KOhm, provides an output resistance for driver structure <NUM> at approximately <NUM> Ohms to match a transmission line resistance of the channel <NUM>.

Driver slice <NUM> includes four signal generation circuits <NUM>, <NUM>, <NUM>, <NUM>. Signal generation circuits <NUM> and <NUM> are associated with the p portion of the differential signal, whereas signal generation circuits <NUM>, <NUM> are associated with n portion of the differential signal. Looking at signal generation circuit <NUM> first, it includes transistors <NUM>-<NUM> and resistor <NUM>. The resistance through the transistors <NUM>-<NUM> accounts for approximately <NUM>-<NUM> percent of the unit resistance value. The resistance of resistor <NUM> accounts for the remaining resistance of the unit resistance. Nevertheless, the scope of implementations is not limited to any particular resistance contribution from a particular component, as different designs may use different resistance contributions to accommodate expected changes from each of the components due to PVT.

Signal generation circuit <NUM> includes p- type metal oxide semiconductor (PMOS) devices (i.e., transistors <NUM>-<NUM>). Similarly, signal generation circuit <NUM> also includes PMOS devices. By contrast, signal generation circuit <NUM> includes n-type metal oxide semiconductor (NMOS) devices (i.e. transistors <NUM>-<NUM>), as does signal generation circuit <NUM>. While signal generation circuits <NUM> and <NUM> are described in detail, it is understood that the signal generation circuits <NUM>, <NUM> are implemented and operated similarly to signal generation circuits <NUM> and <NUM>, respectively.

Transistors <NUM> and <NUM> receive the p portion of the differential signal (inp) from the pre-driver. When inp is low, transistor <NUM> turns on and transistor <NUM> turns off, which pulls up the signal output providing outp. When inp is high, transistor <NUM> turns on and transistor <NUM> turns off, thereby pulling the output outp pad low. The result is that the output signal outp is at a desired signal level. Signal generator circuits <NUM>, <NUM> work similarly according to the n portion of the differential signal.

The bias signals, Vpres/Vnres, are generated through an analog calibration loop to adaptively tune the Ron resistance of the transistors <NUM>, <NUM>, <NUM>, <NUM>. The transistors <NUM>, <NUM>, <NUM>, <NUM> are intended to be in the triode region. But, due to limited headroom at advanced processes, it may be difficult to guarantee that such devices will be in the triode region over various PVT corners. Accordingly, the design of <FIG> includes parallel transistors <NUM>, <NUM>, <NUM>, <NUM> which are also operated in the triode region. The parallel transistors <NUM>, <NUM>, <NUM>, <NUM> are controlled by bias signals Vpcorner/Vncorner. The bias signals Vpres/Vnres and Vpcorner/Vncorner are generated by the bias circuits described in more detail with respect to <FIG> and <FIG>.

<FIG> illustrates bias circuit <NUM>, adapted according to one implementation. In this example, transistor <NUM> is a replica of transistors <NUM>, <NUM>. Transistor <NUM> is a replica of transistors <NUM>, <NUM>. Transistor <NUM> is a replica of transistors <NUM>, <NUM>. Similarly, resistor <NUM> is a replica of resistors <NUM>, <NUM>. In this example, when a transistor or a resistor is a replica of another transistor or resistor, it is built using the same processes on a same semiconductor substrate and to the same specifications. There might be some differences due to process variation affecting different parts of the semiconductor substrate differently, though it is expected that the transistors and resistors are substantially the same as they are replicas. Therefore, it is expected that they should experience similar variation over a range of voltages and temperatures during operation.

Put another way, the arrangement of transistors <NUM>-<NUM> and resistor <NUM> is designed to be a replica of signal generating circuits <NUM>, <NUM>. The analog tuning loop of bias circuit <NUM> produces Vpres/Vpcorner signals that are used to tune the unit resistances Req of the signal generating circuits <NUM>, <NUM>.

Op amp <NUM> is arranged with its inverting output receiving a reference voltage Vref1. In the example of <FIG>, the reference voltage Vref1 is produced by a voltage drop over resistor <NUM> due to a current produced by current source <NUM>. The scope of implementations is not limited to any particular technique to produce the reference voltage Vref1, as another way would include using a bandgap reference voltage or other appropriate voltage source. The other input of op amp <NUM> is coupled between the resistor <NUM> and the current source <NUM>, and the voltage at that node represents the voltage drop due to resistor <NUM>, transistor <NUM>, and the parallel resistance provided by transistors <NUM>, <NUM>. Such a voltage drop is intended to replicate a voltage drop attributable to transistors <NUM>-<NUM> and resistor <NUM> in signal generating circuit <NUM> and also the voltage drop attributable to transistors <NUM>-<NUM> and resistor <NUM> of signal generating circuit <NUM>.

The feedback loop provided by the arrangement of op amp <NUM> causes the voltage drop from transistors <NUM>-<NUM> and resistor <NUM> to be equal to the reference voltage Vref1. As the bias voltage Vpres increases, it causes the resistance of transistor <NUM> to increase, and as Vpres decreases, it causes the resistance of transistor <NUM> to decrease. This causes the voltage drop attributable to transistors <NUM>-<NUM> and resistor <NUM> to remain constant over PVT corners. The bias voltage Vpres is provided to the transistors <NUM>, <NUM>, which behave the same way. In other words, as the bias voltage Vpres increases, the resistance of transistors <NUM> and <NUM> increase, and as Vpres decreases, the resistance of transistors <NUM> and <NUM> decrease. In this way, the bias voltage Vpres causes the resistance of both signal generating circuit <NUM> and signal generating circuit <NUM> to remain constant over PVT corners as well.

As noted above, it may be difficult to keep transistor <NUM> within the triode region over all or substantially all of the expected PVT corners. Nevertheless, it is desirable that the combined parallel resistance of transistors <NUM> and <NUM> is within a range that can be adjusted to provide a reliable output of bias voltage Vpres. Therefore, transistor <NUM> is selected in accordance with transistor <NUM>, resistor <NUM>, and current source <NUM> so that transistor <NUM> remains in its triode region over all of the expected PVT corners. Thus, transistor <NUM> is a replica of transistor <NUM>, and it is gate-coupled to transistor <NUM> as well. During steady-state operation, the transistor <NUM> is expected to remain in its triode region, thereby causing transistor <NUM> to also operate within its triode region. Since transistor <NUM> is a replica of transistors <NUM>, <NUM>, the bias voltage Vpcorner keeps transistors <NUM>, <NUM> in their triode region.

It is noted that the present example provides specific values for resistances and currents. It is understood that such values are provided for example only, and other implementations may use different values for resistances and currents as appropriate to maintain a driver slice at a desired resistance.

<FIG> illustrates bias circuit <NUM>, adapted according to one implementation. In this example, transistor <NUM> is a replica of transistors <NUM>, <NUM>. Transistor <NUM> is a replica of transistors <NUM>, <NUM>, and resistor <NUM> is a replica of resistors <NUM>, <NUM>. Transistor <NUM> is a replica of transistors <NUM>, <NUM>. In other words, the arrangement of transistors <NUM>-<NUM> and resistor <NUM> is designed to be a replica of signal generating circuits <NUM>, <NUM>. The analog tuning loop of bias circuit <NUM> produces Vnres/Vncorner signals that are used to tune the unit resistance Req of the signal generating circuits <NUM>, <NUM>.

Op amp <NUM> is arranged with its inverting output receiving the reference voltage Vref2, which in the example of <FIG> is produced by a voltage drop between current source <NUM> and resistor <NUM>. However, similarly to the bias circuit of <FIG>, the reference voltage may be produced in any appropriate manner, including being produced by a bandgap reference generator.

The other output of the op amp <NUM> is coupled between current source <NUM> and resistor <NUM>, and the voltage difference between that node and ground represents the voltage difference attributable to resistor <NUM>, transistor <NUM>, and the parallel resistances <NUM>, <NUM> and also the voltage difference attributable to resistor <NUM>, transistor <NUM>, and parallel transistors <NUM>, <NUM> in the signal generating circuit <NUM>, <NUM>.

The feedback loop provided by the arrangement of op amp <NUM> causes the voltage at the node between current source <NUM> and resistor <NUM> to be equal to the reference voltage Vref2. This causes the voltage attributable to resistor <NUM>, transistor <NUM>, and parallel transistors <NUM>, <NUM> to remain stable over PVT corners. The bias voltage Vnres is provided to the transistors <NUM>, <NUM>, which behave the same way. Thus, as the bias voltage Vnres decreases, the resistance of transistors <NUM>, <NUM> increases, and as the bias voltage Vnres increases, the resistance of transistors <NUM>, <NUM> decreases. In this way, the bias voltage Vnres causes the resistance of signal generating circuits <NUM>, <NUM> to remain constant over PVT corners.

Now looking to bias voltage Vncorner, it is a gate voltage generated by the voltage at the node between the current source <NUM> and the resistor <NUM>. Transistor <NUM> is a replica of transistor <NUM>, and since they receive the same gate voltage, they both remain in the triode region over PVT corners. The bias voltage Vncorner is also applied to the gates of transistors <NUM>, <NUM>, to keep transistors <NUM>, <NUM> in their triode regions as well. Just as with <FIG>, the present example provides specific values for resistances and currents. However, those values are for example only, and other implementations may use different values for resistances and currents as appropriate to maintain a driver slice at a desired resistance.

Thus, using the bias circuits <NUM>, <NUM> of <FIG> and <FIG>, the equivalent output resistance for a signal generating circuit <NUM>, <NUM>, <NUM>, <NUM> is calibrated to a preset resistance, for example about <NUM> Ohm here, through a feedback system employing op amps. Specifically, under different conditions, if the unit resistance for a signal generating circuit <NUM>, <NUM>, <NUM>, <NUM> begins to change, the feedback loops shown in <FIG> and <FIG> use the Vnres/Vncorner and Vpres/Vpcorner bias voltages to adjust the resistances of the transistor devices to which they connect in order to keep the unit resistance at the desired level (e.g., <NUM> Ohms).

As elaborated before, in a low power supply and advanced process, it may be difficult to guarantee transistors <NUM>, <NUM> stay in the triode region over PVT corners. But transistors <NUM>, <NUM> are designed to be in the triode region, with their controls generated in a way as shown in <FIG> and <FIG>. Since transistors <NUM>, <NUM> are parallel to transistors <NUM>, <NUM>, the total equivalent resistance is controllable over PVT corners.

<FIG> illustrates the Vpres/Vnres signals over time in one implementation. <FIG> illustrates the Vpcorner/Vncorner signals over time in one implementation. As shown, they remain substantially stable in this example scenario, which is a slow-slow-slow (SSS) PVT corner, such as might be experienced due to low voltage and high temperature. Since voltage Vpres (about <NUM> mV) is higher than voltage Vpcorner (about <NUM> mV), the resistance of transistor <NUM> is larger than the resistance of transistor <NUM>. However, the parallel resistance attributable to transistors <NUM>, <NUM> is relatively low, as the lower resistance of transistor <NUM>, which is still in the triode region, compensates for the larger resistance attributable to transistor <NUM>. Also, Vncorner (about <NUM> mV) is somewhat larger than Vnres (about <NUM> mV) at this corner, so the low resistance of transistor <NUM>, which is in its triode region, compensates for the larger resistance attributable to transistor <NUM>.

<FIG> is an illustration of example method <NUM>, according to one implementation. Method <NUM> may be performed by the driver <NUM> and the bias circuits <NUM>, <NUM> of <FIG>. The driver may include a plurality of slices each having a set resistance so that, in parallel, the driver slices match an impedance of the transmission line.

At action <NUM>, a differential data signal is received at a plurality of driver slices. An example is shown in <FIG>, in which driver <NUM> includes driver slices <NUM>-<NUM>. The differential data signal has a p portion (inp) and an n portion (inn). Each of the driver slices <NUM>-<NUM> receives the differential signal, which is applied to gates of transistors in each of the different driver slices. For instance, <FIG> shows driver slice <NUM> receiving inp at the gates of transistors <NUM>, <NUM> and receiving inn at the gates of transistors <NUM>, <NUM>. The various other driver slices <NUM>-<NUM> operate similarly.

In the example of <FIG>, when inp is low, transistor <NUM> is on and transistor <NUM> is off, which pulls up the outp pad. When inp is low, transistor <NUM> is off and transistor <NUM> is on, which pulls down the outp pad. The signal is differential so that when inn is low, inp is high and vice versa. Further in the example of <FIG>, when inn is low, transistor <NUM> is on, and transistor <NUM> is off, which pulls the outn pad high. When inn is high, transistor <NUM> is off, and transistor <NUM> is on, which pulls the outn pad low.

At action <NUM>, a bias circuit maintaining an output resistance of a first signal generator circuit of a first driver slice to a first resistance value. In some instance, this may result in matching an output resistance of driver to a resistance of the transmission line. Looking at the example of <FIG>, action <NUM> may include biasing transistors <NUM> and <NUM> of the signal generating circuits <NUM>, <NUM>. Biasing the transistors <NUM>, <NUM> may operate to maintain an output resistance of the signal generating circuit to a set resistance (e.g., <NUM> Ohms) to match a resistance of the transmission line (<NUM> Ohms). Transistors <NUM>, <NUM> are biased by the signal Vpres, which is generated by the bias circuit <NUM> of <FIG>, as described above.

In another aspect of action <NUM>, it may include biasing transistors <NUM>, <NUM> to maintain a resistance of the signal generating circuits <NUM>, <NUM> the set resistance. Transistors <NUM>, <NUM> are biased by the signal Vnres, which is generated by the bias circuit <NUM> of <FIG>, as described above.

Action <NUM> may also include adjusting a gate voltage of a transistor that is in parallel with the first transistor. For instance, in the example of <FIG>, transistors <NUM>, <NUM> are parallel to the transistors <NUM>, <NUM>. The transistors <NUM>, <NUM> are maintained in a triode region by the bias voltage Vpcorner, as described above with respect to <FIG>. Also, in the example of <FIG>, transistors <NUM>, <NUM> are parallel to transistors <NUM>, <NUM> and are maintained in a triode region by the bias voltage Vncorner. The bias voltage Vncorner is generated as described above with respect to <FIG>.

Action <NUM> may include applying bias voltages to signal generator circuits in each slice of the multi-slice driver.

At action <NUM>, the differential signal is driven onto the transmission line by the signal generator circuit. Looking at signal generator circuit <NUM> first, it drives the p portion of the differential signal when the p portion is high. Signal generator circuit <NUM> drives the p portion of the differential signal when the p portion is low. Signal generator circuit <NUM> drives the n portion of the differential signal when the n portion is high, and signal generator circuit <NUM> drives the n portion of the differential signal when the n portion is low.

Further in the example of <FIG>, the driver slices <NUM>-<NUM> are arranged in parallel so that their output pads are also arranged in parallel to generate outp and outn together. Thus, the output resistance of the driver circuit is equivalent to the slices <NUM>-<NUM> in parallel.

The scope of implementations is not limited to the actions shown in <FIG>. Rather, various implementations may add, omit, rearrange, or modify actions. For instance, action <NUM> is performed using an analog control loop, so it is performed continuously rather than serially after action <NUM> or before action <NUM>. Furthermore, actions <NUM> and <NUM> may be performed repeatedly as a multi-bit signal is transmitted during normal operation of a device.

Claim 1:
A data transmitter comprising:
a plurality of parallel driver slices (<NUM>, <NUM>, <NUM>), a first driver slice (<NUM>) of the plurality of parallel driver slices having a first signal generator circuit (<NUM>) with a first transistor (<NUM>) and in series with a second transistor (<NUM>) coupled to a first bias signal (Vpres) and with a third transistor (<NUM>) in parallel to the second transistor (<NUM>); wherein a gate of the first transistor is coupled to a p portion (inp) of a differential data signal received at the plurality of parallel driver slices; and
a first bias circuit (<NUM>) configured to maintain an output resistance of the first signal generator circuit to a first resistance value, and including a fourth transistor (<NUM>) and a fifth transistor (<NUM>) in series with a first current source (<NUM>) and a sixth transistor (<NUM>) in parallel with the fourth transistor (<NUM>), wherein the fourth transistor (<NUM>) comprises a replica of the second transistor (<NUM>), the fifth transistor (<NUM>) comprises a replica of the first transistor (<NUM>) and the sixth transistor (<NUM>) comprises a replica of the third transistor (<NUM>), the first bias circuit (<NUM>) further including a first operational amplifier, op amp, (<NUM>) having a first inverting input coupled to a first reference voltage (vref1) and a second non-inverting input coupled between the fifth transistor (<NUM>) and the first current source (<NUM>), an output of the first op amp configured to provide the first bias signal (Vpres) to a gate of the second transistor (<NUM>) and to a gate of the fourth transistor (<NUM>), wherein a gate of the sixth transistor (<NUM>) is coupled to a second current source (<NUM>) and to a gate of the third transistor (<NUM>), wherein said maintaining the output resistance of the first signal generator circuit comprises adjusting gate voltage (Vpcorner) of the third transistor (<NUM>) and the sixth transistor (<NUM>), to operate in a triode region.