Patent Description:
A higher bandwidth requirement between an application processor (AP) and the surrounding peripheral devices on a printed circuit board (PCB) is a trend for <NUM> mobile phones. In order to meet this target, we have to increase the data clock frequency and use a <NUM>-to-N control for communication between the AP and the numerous peripheral devices.

However, signal glitches may happen in the communication. <FIG> shows a waveform of a signal transmitted between the AP and the peripheral devices. The glitches are due to signal reflection. Signal reflection occurs when a signal is transmitted along a trace. Some of the signal power may be reflected back to its origin rather than being carried all the way along the trace to the far end. The binary digits obtained from such a signal may be wrong.

How to enhance signal integrity to deal with the signal reflection problem is an important topic in the field of the present invention.

<CIT> relates to a receiver circuit. <CIT> relates to a high voltage input receiver using a differential pair and a source follower. <CIT> relates to a PECL/LVPECL input buffer that uses a differential pair.

The invention is defined in independent claim <NUM> and relates to a chip whose receiver includes a hysteresis circuit in order to enhance the signal integrity.

A hysteresis circuit in accordance with the present invention comprises a protection circuit, an inverter, and a latch. The hysteresis circuit is powered by an overdrive voltage (2VDD) which is twice the power supply voltage (VDD). The input of the hysteresis circuit is coupled to the inverter through the protection circuit, to be transformed into an output, and the latch is coupled to the inverter for positive feedback control. The protection circuit has a first sub-circuit biased by a first bias voltage that is lower than VDD, and a second sub-circuit biased by a second bias voltage that is greater than VDD. Through the first sub-circuit of the protection circuit, the input is coupled to the inverter to control the pull-up path of the inverter. Through the second sub-circuit of the protection circuit, the input is coupled to the inverter to control the pull-down path of the inverter.

In an exemplary embodiment, the pull-up path of the inverter is biased by a third bias voltage that is less than VDD, and the pull-down path of the inverter is biased by a fourth bias voltage that is greater than the power supply voltage. The third bias voltage may be greater than or equal to the first bias voltage. The fourth bias voltage is less than or equal to the second bias voltage.

In an exemplary embodiment, the latch has a first sub-circuit biased by a fifth bias voltage that is less than VDD, and a second sub-circuit biased by a sixth bias voltage that is greater than VDD. The first sub-circuit of the latch is coupled to the pull-up path of the inverter. The second sub-circuit of the latch is coupled to the pull-down path of the inverter. The fifth bias voltage may be greater than or equal to the first bias voltage. The sixth bias voltage is less than or equal to the second bias voltage.

The following description is made for the purpose of illustrating the general principles of the invention. The scope of the invention is determined by reference to the appended claims.

To enhance the signal integrity, a hysteresis circuit (such as a Schmitt trigger circuit) for signal inversion is used in a receiver of a chip. The hysteresis is implemented by positive feedback control.

<FIG> depicts a Schmitt trigger circuit <NUM>, which includes an inverter CK1 and a latch (including sub-circuits CK2 and CK3). The Schmitt trigger circuit <NUM> is powered by a power supply voltage VDD. An analog signal received by a receiver of a chip is coupled to the Schmitt trigger circuit <NUM> as an input VIN and then transformed into a digital signal as an output VOUT. The sub-circuit CK2 of the latch is coupled to the pull-up path of the inverter CK1, and the sub-circuit CK3 of the latch is coupled to the pull-down path of the inverter CK1. The latch (including sub-circuits CK2 and CK3) applies a positive feedback to the inverter CK1. The output VOUT retains its value until the input VIN changes sufficiently to trigger a change.

<FIG> illustrates a transfer function of the Schmitt trigger circuit <NUM>. With the positive feedback control, the output VOUT retains low when the input VIN has not dropped to the lower threshold level (Vt - Vt+), and the output VOUT retains high when the input VIN has not exceeded the higher threshold level (Vt + Vt-). This dual threshold action is called hysteresis. The hysteresis window defines the threshold levels for switching as the input VIN rises or falls.

As the process technology evolves (e.g., scaling down to <NUM>, <NUM>, <NUM>, or below), the maximum applied voltage is suppressed (e.g., down to <NUM>. 2V, much lower than the <NUM>. 8V applied to the <NUM> products). If there are <NUM> chips as well as the more advanced (<NUM>/<NUM>/<NUM> or below) chips on the same printed circuit board (PCB), an overdrive design is required. An overdrive voltage 2VDD (e.g., <NUM>. 8V) has to be generated to operate the <NUM> chips, and protection circuits for the advanced chips (<NUM>/<NUM>/<NUM> or below) are necessary. <FIG> depicts a Schmitt trigger circuit <NUM> with the overdrive design.

In <FIG>, the Schmitt trigger circuit <NUM> is powered by the overdrive voltage 2VDD (twice the power supply voltage VDD), and a protection circuit (including sub-circuits CK4 and CK5) is required prior to the inverter CK1 to operate the all components in a safe operating area (SOA). Through the sub-circuit CK4 of the protection circuit, the input VIN is coupled to the inverter CK1 to control the pull-up path of the inverter CK1. Through the sub-circuit CK5 of the protection circuit, the input VIN is coupled to the inverter CK1 to control the pull-down path of the inverter CK1. The power supply voltage VDD is used to bias the protection circuit (including the sub-circuits CK4 and CK5), the inverter CK1, and the latch (including the sub-circuits CK2 and CK3). However, the Schmitt trigger circuit <NUM> with the overdrive design may narrow the hysteresis window.

In an exemplary embodiment, the overdrive voltage 2VDD is <NUM>. 8V and the threshold voltage Vt to activate an transistor manufactured by the advanced process is <NUM>. In such a situation, the headroom is only <NUM>. 35V, which is a difference between the power supply voltage VDD (<NUM>. 9V) and the threshold voltage <NUM>. The limited headroom <NUM>. 35V considerably narrows the hysteresis window, and the signal integrity is significantly affected.

To extend the width of the hysteresis window, a novel hysteresis circuit is introduced. <FIG> illustrates a hysteresis circuit <NUM> in accordance with the present invention. The hysteresis circuit <NUM> is powered by an overdrive voltage 2VDD (twice the power supply voltage VDD), and additional bias voltages (e.g., VDDA, VDDB, VDDE, VDDF, VDDY and VDDZ) are required to bias the hysteresis circuit <NUM>. The input VIN and the output VOUT are between 0V~2VDD. The bias voltages VDDA, VDDB, VDDE, VDDF, VDDY and VDDZ are between 0V~2VDD, too. The bias voltages VDDA, VDDE and VDDY are less than VDD, and the bias voltages VDDB, VDDF and VDDZ are greater than VDD.

In comparison with <FIG>, an output node n1 of the sub-circuit CK4 of the protection circuit of the hysteresis circuit <NUM> can reach the lower voltage level (because VDDA < VDD), and an output node n2 of the sub-circuit circuit CK5 of the protection circuit of the hysteresis circuit <NUM> can reach the greater voltage level (because VDDB > VDD). The headroom for operating the transistors of the inverter CK1 is increased. The hysteresis window of the hysteresis circuit <NUM> can be at least four times that of the Schmitt trigger circuit <NUM>.

The design that employs the bias voltages VDDE, VDDF, VDDY and VDDZ has options. The bias voltages VDDE (lower than VDD) and VDDF (greater than VDD) may be fed into the pull-up path and the pull-down path of the inverter CK1, respectively. The bias voltages VDDY (lower than VDD) and VDDZ (greater than VDD) may be fed into the sub-circuit CK2 and the sub-circuit CK3 of the latch, respectively. The hysteresis circuit <NUM> with all of the bias voltages VDDA, VDDB, VDDE, VDDF, VDDY and VDDZ may result in a more significant hysteresis in comparison with a Schmitt trigger circuit that only uses the bias voltages VDDA and VDDB. The bias voltage VDDA may be less than or equal to the bias voltage VDDY, and it may also be less than or equal to the bias voltage VDDE. The bias voltage VDDB may be greater than or equal to the bias voltage VDDZ, and it may also be greater than or equal to the bias voltage VDDF.

There are control signals CTRL_SMTA and CTRL_SMTB for controlling the positive feedback. As the control signal CTRL_SMTA enables the sub-circuit CK2 of the latch, a positive feedback is applied to expand the hysteresis range Vt-. As the control signal CTRL_SMTB enables the sub-circuit CK3 of the latch, a positive feedback is applied to expand the hysteresis range Vt+. The design that employs the control signals CTRL_SMTA and CTRL_SMTB has options.

<FIG> depicts a hysteresis circuit <NUM> in details in accordance with an exemplary embodiment of the present invention. The inverter CK1 has a p-channel metal-oxide-silicon (PMOS) transistor M1 and an n-channel metal-oxide-silicon (NMOS) transistor M2. The gate terminal of the PMOS transistor M1 is coupled to the output node n1 of the sub-circuit CK4. Because the voltage level of the output node n1 of the sub-circuit CK4 is reduced by the bias voltage VDDA (VDDA<VDD), the turned-on PMOS transistor M1 has a stronger capability to pull up the voltage level of the output VOUT. The gate terminal of the NMOS transistor M2 is coupled to the output node n2 of the sub-circuit CK5. Because the voltage level of the output node n2 of the sub-circuit CK5 is increased by the bias voltage VDDB (VDDB>VDD), the turned-on NMOS transistor M2 has a stronger capability to pull down the voltage level of the output VOUT.

The inverter CK1 further has a PMOS transistor M3 and an NMOS transistor M4. The PMOS transistor M1 is coupled to the output VOUT via the PMOS transistor M3. The NMOS transistor M2 is coupled to the output VOUT via the NMOS transistor M4. The bias voltage VDDE (< VDD, and ≥ VDDA) is coupled to the gate terminal of the transistor M3, and the bias voltage VDDF (> VDD, and ≤ VDDB) is coupled to the gate terminal of the transistor M4. By adjusting the bias voltages VDDE and VDDF to their proper levels, the threshold voltage Vt (referring to <FIG>) can be shifted to its ideal value.

The components of the latch (including sub-circuits CK2 and CK3) are described in this paragraph. The sub-circuit CK2 includes PMOS transistors M5 and M6, and an NMOS transistor M7. The PMOS transistor M5 has a source terminal coupled to the drain terminal of the PMOS transistor M1, and a gate terminal coupled to the output VOUT. The PMOS transistor M6 has a source terminal coupled to the drain terminal of the PMOS transistor M5, and a gate terminal biased by the bias voltage VDDY (< VDD, and ≥ VDDA). The NMOS transistor M7 has a drain terminal coupled to the drain terminal of the PMOS transistor M6, a gate terminal controlled by the control signal CTRL_SMTA, and a source terminal coupled to a power ground voltage GND. The sub-circuit CK3 includes NMOS transistors M8 and, M9, and a PMOS transistor M10. The NMOS transistor M8 has a source terminal coupled to the drain terminal of the NMOS transistor M2, and a gate terminal coupled to the output VOUT. The NMOS transistor M9 has a source terminal coupled to the drain terminal of the NMOS transistor M8, and a gate terminal biased by the bias voltage VDDZ (> VDD, and ≤ VDDB). The PMOS transistor M10 has a drain terminal coupled to the drain terminal of the NMOS transistor M9, a gate terminal controlled by the control signal CTRL_SMTB, and a source terminal coupled to the overdrive voltage 2VDD.

The components of the protection circuit (including sub-circuits CK4 and CK5) are described in this paragraph. The sub-circuit CK4 includes PMOS transistors M11 and M12. The input VIN is coupled to the node n1 through the PMOS transistor M11. The gate terminal of the PMOS transistor M11 is biased by the bias voltage VDDA (<VDD). The PMOS transistor M12 has a source terminal biased by the bias voltage VDDA, a gate terminal coupled to the input VIN, and a drain terminal coupled to the node n1. The sub-circuit CK5 includes NMOS transistors M13 and M14. The input VIN is coupled to the node n2 through the NMOS transistor M13. The gate terminal of the NMOS transistor M13 is biased by the bias voltage VDDB (>VDD). The NMOS transistor M14 has a source terminal biased by the bias voltage VDDB, a gate terminal coupled to the input VIN, and a drain terminal coupled to the node n2.

<FIG> depicts a hysteresis circuit <NUM> in details in accordance with another exemplary embodiment of the present invention. In comparison with <FIG>, the inverter CK1 of <FIG> has PMOS transistors M15-M17, and NMOS transistors M18-M20.

The PMOS transistor M15 is coupled between the PMOS transistors M1 and M3. The bias voltage VDDE (< VDD, and ≥ VDDA) is coupled to the gate terminal of the PMOS transistor M3 through the PMOS transistor M16. The gate terminal of the PMOS transistor M16 is coupled to the output VOUT. The gate terminal of the transistor M3 is further coupled to the output VOUT through the PMOS transistor M17. The gate terminal of the PMOS transistor M17 is coupled to the gate terminal of the PMOS transistor M15.

The NMOS transistor M18 is coupled between NMOS transistors M2 and M4. The bias voltage VDDF (> VDD, and ≤ VDDB) is coupled to the gate terminal of the NMOS transistor M4 through the NMOS transistor M19. The gate terminal of the NMOS transistor M19 is coupled to the output VOUT. The gate terminal of the NMOS transistor M4 is further coupled to the output VOUT through the NMOS transistor M20. The gate terminal of the NMOS transistor M20 is coupled to the gate terminal of the NMOS transistor M18.

<FIG> depicts a printed circuit board (PCB) <NUM> in accordance with an exemplary embodiment of the present invention. An application processor (AP) <NUM> and a plurality of peripheral devices 704_1 to 704_N are mounted on the PCB <NUM>. The AP <NUM> has a receiver <NUM> receiving signals transferred from the peripheral devices 704_1 to 704_N, and a core circuit <NUM> coupled to the receiver <NUM>. The receiver <NUM> has the disclosed hysteresis circuit <NUM> that transforms the input VIN into the output VOUT. The AP <NUM> may further includes a voltage regulator <NUM> for providing the hysteresis circuit <NUM> with the overdrive voltage 2VDD and the bias voltages VDDA, VDDB, VDDE, VDDF, VDDY and VDDZ. The hysteresis circuit <NUM> provides strong signal integrity.

In another exemplary embodiment, the hysteresis circuit of the present invention is used in a receiver of a peripheral device.

Claim 1:
A chip, comprising:
a core circuit (<NUM>), wherein the core circuit (<NUM>) is configured to operate from a power supply voltage (VDD); and
a receiver (<NUM>), coupled to the core circuit (<NUM>), wherein the receiver (<NUM>) has an input (VIN);
wherein the receiver (<NUM>) includes a hysteresis circuit (<NUM>, <NUM>, <NUM>, <NUM>) comprising:
an inverter (CK1), wherein the inverter (CK1) is configured to operate from an overdrive voltage (2VDD) that is twice the power supply voltage (VDD), wherein the inverter has an output (VOUT), wherein the inverter (CK1) comprises a pull-up path (M1, M3) between the overdrive voltage (2VDD) and the output (VOUT), and wherein the inverter (CK1) comprises a pull-down path (M2, M4) between the output (VOUT) and a ground (GND);
a latch (CK2, CK3) coupled to the inverter (CK1) for positive feedback control;
a protection circuit (CK4, CK5) comprising a first sub-circuit (CK4) biased by a first bias voltage (VDDA) that is lower than the power supply voltage (VDD), and a second sub-circuit (CK5) biased by a second bias voltage (VDDB) that is greater than the power supply voltage (VDD);
wherein, through the first sub-circuit (CK4) of the protection circuit, the input (VIN) is coupled to the inverter (CK1) to control the pull-up path of the inverter (CK1); and
wherein, through the second sub-circuit (CK5) of the protection circuit, the input (VIN) is coupled to the inverter (CK1) to control the pull-down path of the inverter.