Patent Description:
A semiconductor storage system is a memory component configured to store various kinds of data information. Data input and output are generally needed between the semiconductor storage system and a control system. However, with the development of storage systems, users have increasingly higher requirements for a data transmission rate, and an existing data transmission rate cannot meet the requirements.

<CIT> discloses a data output buffer. The data output buffer includes a pull-up circuit configured to output a pull-up feedback signal by pull-up driving an output node. The data output buffer includes a pull-up driver configured to output the pull-up drive signal by driving a pull-up signal, and selectively activate the pull-up drive signal based on the pull-up feedback signal. The data output buffer includes a pull-down circuit configured to output a pull-down feedback signal by pull-down driving the output node based on a pull-down drive signal. The data output buffer includes a pull-down driver configured to output the pull-down drive signal by driving a pull-down signal, and selectively activate the pull-down drive signal based on the pull-down feedback signal. <CIT> discloses an integrated circuit including an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver includes a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull- down signal.

<CIT> discloses a semiconductor device including a termination driver for driving a data line with a predetermined termination level by using an external power supply voltage and a drive current controller for controlling a drive current flowing into the data line from the termination driver in response to a voltage level of the external power supply voltage.

<CIT> discloses a receiver circuit which receives an input signal. A first restriction circuit provides a first reference voltage or an input signal higher than the first reference voltage to a first node. A second restriction circuit provides a second reference voltage or the input signal lower than the second reference voltage to a second node. A first PMOS transistor pulls up an output node based on a voltage of the first node, and a first NMOS transistor pulls down the output node based on a voltage of the second node. A second PMOS transistor is connected between the output node and the first PMOS transistor, and a second NMOS transistor is connected between the output node and the first NMOS transistor. At least one compensation resistor is connected between a power supply voltage and the first PMOS transistor or between the first NMOS transistor and a ground.

<CIT> discloses a memory device which includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node between a first terminal of the first resistive memory element and a first terminal of the second resistive memory element, and a transistor comprising a gate electrically coupled with the common node.

<CIT> discloses a multiplexer array. The multiplexer array includes (<NUM>) a first multiplexer coupled to a first address line, where the first multiplexer includes a first plurality of memory devices and (<NUM>) a first plurality of input logic devices coupled to the first multiplexer, a first plurality of data lines, and a plurality of bitlines. Each input logic device of the first plurality of input logic devices is coupled to a respective memory device of the first plurality of memory devices and includes a first input terminal and a second input terminal, where, for each input logic device, the first input terminal is coupled to a respective data line of the first plurality of data lines and the second input terminal is coupled to a respective bitline of the plurality of bitlines. Embodiments of methods of programming a multiplexer array are also described.

Therefore, it is an urgent problem to be solved currently to provide a storage system with a high transmission rate.

According to a first aspect there is provided a storage system as set out in claim <NUM>. Embodiments may comprise features as set out in dependent claims <NUM> to <NUM>.

Embodiments of the storage system according to the present disclosure are described in detail below with reference to the accompanying drawings.

<FIG> is a schematic diagram of a framework of an embodiment of a storage system according to the present disclosure. Referring to <FIG>, the storage system according to the present disclosure includes a storage layer <NUM> and a logical layer <NUM>. The storage layer <NUM> and the logical layer <NUM> are each provided with a data port configured to receive and transmit data. Specifically, the storage layer <NUM> is provided with a data port <NUM>, and the logical layer <NUM> is provided with a data port <NUM>. The data port <NUM> is electrically connected to the data port <NUM>, so that the storage layer <NUM> and the logical layer <NUM> transmit data through the data port <NUM> and the data port <NUM>.

<FIG> is a schematic structural diagram of the data port <NUM> arranged on the storage layer <NUM>. Referring to <FIG>, in this embodiment, the data port <NUM> arranged on the storage layer <NUM> includes a data output unit <NUM>. Data of the storage layer <NUM> is transmitted externally through the data output unit <NUM>, for example, to the logical layer <NUM>. Further, the data port <NUM> further includes a data input unit <NUM>. External data is transmitted through the data input unit <NUM> to the storage layer <NUM>. In this embodiment, the data input unit <NUM> includes a buffer, and the external data (for example, data of the logical layer <NUM>) is inputted to the storage system through the buffer.

Further, in this embodiment, the storage system further includes a serializer S, and data of the storage system, after parallel-to-serial conversion by the serializer S, is inputted to the data output unit <NUM> as an input signal. The storage system further includes a deserializer DS, and data outputted by the buffer, after serial-to-parallel conversion by the deserializer DS, is inputted to the storage system.

<FIG> is a schematic diagram of a circuit structure of a first embodiment of the data output unit <NUM>. Referring to <FIG>, the data output unit <NUM> includes a pull-up unit 31A and a pull-down unit 31B.

The pull-up unit 31A has a control terminal, a first terminal and a second terminal. A first input signal of the storage layer <NUM> is inputted to the control terminal, the first terminal is electrically connected to a power supply VDDQ, and the second terminal is connected to an output terminal DQ of the data output unit <NUM>. The output terminal DQ is electrically connected to an external structure; for example, the output terminal DQ is electrically connected to the logical layer <NUM> to transmit data from the storage layer <NUM> to the logical layer <NUM>. The pull-up unit is a first NMOS transistor. In the first NMOS transistor, a gate terminal is the control terminal, one of a source terminal and a drain terminal is the first terminal, and the other of the source terminal and the drain terminal is the second terminal.

The pull-down unit 31B has a control terminal, a first terminal and a second terminal. A second input signal of the storage layer <NUM> is inputted to the control terminal, the first terminal is electrically connected to a ground terminal VSS, and the second terminal is connected to the output terminal DQ of the data output unit. In this embodiment, the pull-down unit 31B and the pull-up unit 31A are transistors of the same type. That is, the pull-down unit 31B is a second NMOS transistor. In the second NMOS transistor, a gate terminal is the control terminal, one of a source terminal and a drain terminal is the first terminal, and the other of the source terminal and the drain terminal is the second terminal.

In this embodiment, the first input signal and the second input signal are complementary signals. For example, the first input signal is a positive input signal Ip, the second input signal is a negative input signal In, and they are complementary to each other, so as to output a complete signal at the output terminal DQ.

Further, the data output unit <NUM> further includes an inverter A. The first input signal is inputted to the control terminal of the pull-up unit 31A through the inverter A, or the second input signal is inputted to the control terminal of the pull-down unit 31B through the inverter A. In this embodiment, the first input signal and the second input signal are complementary signals, the pull-up unit 31A is an NMOS transistor, and the pull-down unit 31B is also an NMOS transistor; therefore, in order to ensure the integrity of an output signal, one of the pull-up unit 31A and the pull-down unit 31B is provided with the inverter A, so as to guarantee the integrity of the signal outputted by the output terminal DQ. In this embodiment, the inverter A is arranged on a branch where the pull-down unit 31B is located; that is, the second input signal is inputted to the control terminal of the pull-down unit 31B through the inverter A. No inverter is arranged on a branch where the pull-up unit 31A is located; that is, the first input signal is directly inputted to the control terminal of the pull-up unit 31A. In other embodiments of the present disclosure, an inverter may be arranged on the branch where the pull-up unit 31A is located, while no inverter is arranged on the branch where the pull-down unit 31B is located.

Further, in this embodiment, a voltage corresponding to a high level of an output signal of the output terminal DQ of the data output unit <NUM> is less than a power supply voltage VDDQ. That is, a voltage of the output terminal DQ is not required to be increased to the power supply voltage VDDQ, which reduces the time of conversion between a low level and a high level and increases a data transmission rate.

Further, a width of the first NMOS transistor is greater than that of the second NMOS transistor, and the first NMOS transistor and the second NMOS transistor operate in a linear region, which can further increase the data transmission rate and improve the performance of the storage system.

The data output terminal of the storage system according to the present disclosure is provided with the pull-up unit 31A and the pull-down unit 31B, where the pull-up unit 31A is an NMOS transistor, so that a voltage of the data output unit can be effectively accelerated from low to high or from high to low; that is, the time of conversion of the voltage of the data output unit from low to high or from high to low is reduced, thereby increasing the data transmission speed and improving the performance of the storage system.

A second embodiment of the data output unit <NUM> is further provided for the storage system according to the present disclosure. <FIG> is a schematic diagram of a circuit structure of a second embodiment of the data output unit <NUM>. Referring to <FIG>, the data output unit <NUM> not only includes the pull-up unit 31A and the pull-down unit 31B, but also includes a first switch unit 31C and a second switch unit 31D.

The first terminal of the pull-up unit 31A is electrically connected to the power supply VDDQ through the first switch unit 31C, and the first terminal of the pull-down unit 31B is electrically connected to the ground terminal VSS through the second switch unit 31D. In the present disclosure, the data output unit <NUM> can be switched between output of data and a high-impedance state (that is, no output of data) by turning on and turning off the first switch unit 31C and the second switch unit 31D. Specifically, when the first switch unit 31C and the second switch unit 31D are turned on, the data output unit <NUM> can output data; and when the first switch unit 31C and the second switch unit 31D are turned off, the data output unit <NUM> cannot output data and presents the high-impedance state.

Further, in this embodiment, the first switch unit 31C is a first transistor. The first transistor includes a control terminal, a first terminal and a second terminal. An enable signal EN is inputted to the control terminal to control ON and OFF of the first switch unit 31C. The first terminal is electrically connected to the power supply VDDQ. The second terminal is electrically connected to the first terminal of the pull-up unit 31A. In this embodiment, the first transistor is a third NMOS transistor. In the third NMOS transistor, a gate terminal is the control terminal, one of a source terminal and a drain terminal is the first terminal, and the other of the source terminal and the drain terminal is the second terminal. In other embodiments of the present disclosure, the first transistor may also be a PMOS transistor. In the PMOS transistor, a gate terminal is the control terminal, one of a source terminal and a drain terminal is the first terminal, and the other of the source terminal and the drain terminal is the second terminal.

Further, in this embodiment, the second switch unit 31D is a second transistor. The second transistor includes a control terminal, a first terminal and a second terminal. The enable signal EN is inputted to the control terminal to control ON and OFF of the second switch unit 31D. The first terminal is electrically connected to the ground terminal VSS. The second terminal is electrically connected to the first terminal of the pull-down unit 31B. In this embodiment, the second transistor is a fourth NMOS transistor. In the fourth NMOS transistor, a gate terminal is the control terminal, one of a source terminal and a drain terminal is the first terminal, and the other of the source terminal and the drain terminal is the second terminal. In other embodiments of the present disclosure, the second transistor may also be a PMOS transistor. In the PMOS transistor, a gate terminal is the control terminal, one of the source terminal and the drain terminal is the first terminal, and the other of the source terminal and the drain terminal is the second terminal.

In this embodiment, the pull-up unit 31A, the pull-down unit 31B, the first switch unit 31C and the second switch unit 31D are all NMOS transistors and may share a semiconductor structure, which greatly simplifies the layout and saves a manufacturing process. Specifically, refer to <FIG>, which is a structural diagram of a process of the data output unit <NUM>.

The power supply VDDQ is electrically connected to the first terminal of the first switch unit 31C, a common region exists between the first switch unit 31C and the pull-up unit 31A, which acts as the second terminal of the first switch unit 31C and the first terminal of the pull-up unit 31A, and the enable signal EN is inputted to the gate terminal of the first switch unit 31C.

A common region exists between the pull-up unit 31A and the pull-down unit 31B, which acts as the second terminal of the pull-up unit 31A and the second terminal of the pull-down unit 31B, and the first input signal is inputted to the gate terminal of the pull-up unit 31A.

A common region exists between the pull-down unit 31B and the second switch unit 31D, which acts as the first terminal of the pull-down unit 31B and the second terminal of the second switch unit 31D, and the second input signal is inputted to the gate terminal of the pull-down unit 31B after passing through the inverter.

The ground terminal VSS is electrically connected to the first terminal of the second switch unit 31D, and the enable signal EN is inputted to the gate terminal of the second switch unit 31D.

In the above embodiment of the present disclosure, the data input unit <NUM> is a buffer. In another embodiment of the present disclosure, the data input unit <NUM> is of the same structure as the data output unit <NUM>.

Specifically, refer to <FIG>, which is a schematic diagram of a circuit structure of an embodiment of the data input unit <NUM> of the storage system according to the present disclosure. The data input unit <NUM> includes a pull-up unit 32A, a pull-down unit 32B, a third switch unit 32C and a fourth switch unit 32D.

The pull-up unit 32A has a control terminal, a first terminal and a second terminal. The first input signal of the external structure (for example, the logical layer <NUM>) is inputted to the control terminal, the first terminal is electrically connected to the power supply VDDQ through the third switch unit 32C, and the second terminal is connected to an output terminal DQ of the data input unit <NUM>. The signal of the output terminal DQ is inputted to the storage layer <NUM>. In this embodiment, the pull-up unit 32A is an NMOS transistor.

The pull-down unit 32B has a control terminal, a first terminal and a second terminal. The second input signal of the external structure (for example, the logical layer <NUM>) is inputted to the control terminal, the first terminal is electrically connected to the ground terminal VSS through the fourth switch unit 32D, and the second terminal is connected to the output terminal DQ of the data input unit. In this embodiment, the pull-down unit 32B is an NMOS transistor. In other embodiments of the present disclosure, the pull-down unit 32B may also be a PMOS transistor.

The first input signal and the second input signal are complementary signals. For example, the first input signal is a positive input signal Ip, the second input signal is a negative input signal In, and they are complementary to each other, so as to output a complete signal at the output terminal DQ.

The data input unit of the storage layer <NUM> of the storage system according to the present disclosure is provided with the pull-up unit 32A and the pull-down unit 32B, and the pull-up unit 32A is an NMOS transistor, so that a voltage of the data input unit can be effectively accelerated from low to high or from high to low; that is, the time of conversion of the voltage of the data input unit from low to high or from high to low is reduced, thereby greatly increasing the data transmission speed and improving the performance of the storage system.

In the present disclosure, the data input unit <NUM> can be switched between input of data and a high-impedance state (that is, no input of data) by turning on and turning off the third switch unit 32C and the fourth switch unit 32D. Specifically, when the third switch unit 32C and the fourth switch unit 32D are turned on, the data input unit <NUM> can input data; and when the third switch unit 32C and the fourth switch unit 32D are turned off, the data input unit <NUM> cannot input data and presents the high-impedance state.

Further, in this embodiment, the third switch unit 32C and the fourth switch unit 32D are both NMOS transistors, and then the pull-up unit 32A, the pull-down unit 32B, the third switch unit 32C and the fourth switch unit 32D can share a semiconductor structure with one another, which greatly simplifies the layout and saves the manufacturing process.

The structure of the data port <NUM> in the storage layer <NUM> is described in the above embodiments. It may be understood that the data port <NUM> located in the logical layer <NUM> may have the same structure as the data port <NUM> located in the storage layer <NUM>. That is, the data output unit of the data port <NUM> located in the logical layer <NUM> may also consist of a pull-up unit and a pull-down unit, thereby greatly increasing a rate at which data is transmitted from the logical layer <NUM> to the storage layer <NUM> or other structural layers. The data input unit of the data port <NUM> located in the logical layer <NUM> may also consist of a pull-up unit and a pull-down unit, thereby greatly increasing a rate at which data is transmitted from the external structure (such as the storage layer or other structural layers) to the logical layer <NUM>.

Claim 1:
A storage system, comprising a data port (<NUM>), the data port (<NUM>) comprising a data output unit (<NUM>), the data output unit (<NUM>) comprising:
a pull-up unit (31A), having a control terminal, a first terminal and a second terminal, a first input signal being inputted to the control terminal, the first terminal being electrically connected to a power supply (VDDQ), the second terminal being connected to an output terminal (DQ) of the data output unit (<NUM>); and
a pull-down unit (31B), having a control terminal, a first terminal and a second terminal, a second input signal being inputted to the control terminal, the first terminal being electrically connected to a ground terminal (VSS), and the second terminal being connected to the output terminal (DQ) of the data output unit (<NUM>);
wherein the pull-up unit is a first NMOS transistor and the pull-down unit is a second NMOS transistor;
characterised in that
the data output unit (<NUM>) further comprises a first switch unit (31C) and a second switch unit (31D), the first terminal of the pull-up unit (31A) is electrically connected to the power supply (VDDQ) through the first switch unit (31C), and the first terminal of the pull-down unit (31B) is electrically connected to the ground terminal (VSS) through the second switch unit (31D);
wherein the first switch unit (31C) is a first transistor, the first transistor comprises a control terminal, a first terminal and a second terminal, an enable signal (EN) is inputted to the control terminal, the first terminal is electrically connected to the power supply (VDDQ), and the second terminal is electrically connected to the first terminal of the pull-up unit (31A);
the second switch unit (31D) is a second transistor, the second transistor comprises a control terminal, a first terminal and a second terminal, the enable signal (EN) is inputted to the control terminal, the first terminal is electrically connected to the ground terminal (VSS), and the second terminal is electrically connected to the first terminal of the pull-down unit (31B); and
wherein the first transistor is a third NMOS transistor and the second transistor is a fourth NMOS transistor.