Patent Description:
<CIT> discloses a host interface controller having a first buffer set and a second buffer set operated in a ping-pong buffer mode by a control module to alternately work as a pre-fetch buffer set. When one buffer set between the first buffer set and the second buffer set works as the pre-fetch buffer set, the control module pre-fetches and buffers data starting from a first address of a storage device into the pre-fetch buffer set and accesses the other buffer set between the first buffer set and the second buffer set to respond to a read request that the central processing unit issues to access data of a second address of the storage device.

This document relates generally to computing systems, and in particular to techniques to prefetch memory data using a smart prefetch buffer that includes logic to decide when to grant a prefetch request and perform the prefetch operation and when to ignore a prefetch request that will negatively impact system performance.

An example of a memory device is provided in accordance with independent claim <NUM>.

An example of a method of operating a memory device is provided in accordance with independent claim <NUM>.

An example of a computing system is provided in accordance with independent claim <NUM>.

This section is intended to provide an overview of subject matter of the present patent application.

<FIG> is a block diagram of an example of a computing system <NUM>. The system may be distributed or centralized. The computing system <NUM> includes multiple host devices <NUM>. The host devices <NUM> each include one or more processors <NUM> and memory <NUM> local to the host device <NUM>. The local memory <NUM> is a fast memory that performs memory requests from the local processor <NUM> with low latency. The local memory may be a level <NUM> (L1) memory. The computer system <NUM> also includes a shared memory. The shared memory is a slower memory device <NUM> than the local memory and memory requests to the memory device <NUM> have a longer latency. The memory device <NUM> may include level <NUM> (L2) memory or level <NUM> (L3) memory.

The memory device <NUM> includes a memory array <NUM> and a memory controller <NUM>. The memory array <NUM> includes memory cells that may be volatile memory cells or non-volatile memory cells. Volatile memory cells can include random-access memory (RAM), dynamic random-access memory (DRAM), and synchronous dynamic random-access memory (SDRAM), among others. Non-volatile memory cells can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random-access memory (RRAM), and magnetoresistive random access memory (MRAM), 3D XPoint™ memory, among others.

The memory controller <NUM> controls access to the memory array <NUM> by memory access requests received from the host devices <NUM>. To improve read bandwidth and reduce read request latency, the memory device <NUM> includes a prefetch buffer <NUM> and prefetch buffer logic circuitry <NUM>. The prefetch buffer <NUM> is a faster memory than memory array <NUM>, and reading data from the prefetch buffer <NUM> involves less latency than reading data from the memory array <NUM>. To reduce latency in read requests to the memory device <NUM>, the memory device <NUM> performs internal pre-fetching of data. Successive read requests to memory are often to memory addresses within a same memory block. When a read request is received, extra read data not requested in the read request is prefetched from memory along with the requested read data and the extra data is stored in the prefetch buffer <NUM> in anticipation of a future read request. The logic circuitry <NUM> identifies the extra data not requested in the read request to load into the prefetch buffer <NUM>.

However, if the read requests are to addresses that are too scattered and random, prefetching of data can degrade the read bandwidth because of extra time needed to perform the prefetch operations. The read bandwidth can also be degraded if one or more of the host devices <NUM> is overly demanding on read requests than other host devices <NUM>. This is because the latency in serving read requests from less demanding host devices <NUM> will be similar to the latency for read requests to addresses that are too random.

To avoid degrading the read performance of the memory device <NUM>, the memory controller <NUM> implements smart prefetching. The logic circuitry <NUM> recognizes when a prefetch operation will degrade read performance of the computer system <NUM> and omits prefetching with these read requests. The logic circuitry <NUM> includes circuit components such as a processor (e.g., a microprocessor) or state machine (e.g., a finite state machine) to control memory operations (e.g., read, write, and erase operations) and to implement the functions described as being performed by the logic circuitry <NUM>. The memory device <NUM> also includes a read address buffer <NUM>. The logic circuitry <NUM> uses information in the read address buffer <NUM> to determine when to perform a prefetch operation.

<FIG> is a block diagram of an example of the read address buffer <NUM>. The read address buffer <NUM> includes multiple memory registers. The example of <FIG> includes <NUM> memory registers for simplicity of the diagram, but the read address buffer <NUM> may include more (e.g., <NUM>) memory registers. The optimum number of memory registers in the read address buffer <NUM> may depend on the configuration of the computer system (e.g., the number of host devices, whether the shared memory is L2 or L3 memory, etc.). The read address buffer <NUM> may be a first-in first-out (FIFO) buffer, or shift-in shift-out (SISO) buffer. When a new memory read request is received from a host device, the memory controller <NUM> adds the address of the read request into the first memory register of the read address buffer <NUM>. Stored addresses are shifted down through the read address buffer <NUM> as subsequent read requests are received from host devices. The example of <FIG> shows new address entries are added to the top of the read address buffer <NUM> and the current contents of the memory registers are shifted down. The read address buffer <NUM> tracks the read transaction history and the pattern of memory accesses that reach the prefetch buffer.

The logic circuitry <NUM> of the memory controller <NUM> determines whether to perform a prefetch operation based on whether an address continuous to the current read address is included in the read address buffer <NUM>. If the read address is a continuous address of a read address previously received and currently stored in the read address buffer <NUM>, the logic circuitry <NUM> performs a prefetch operation with the read request. If the read address is not a continuous address of a read address in the read address buffer <NUM>, the logic circuitry <NUM> omits the prefetch operation.

In the example of <FIG>, the end of the read address buffer <NUM> shows five read addresses A, B, C, D, and E. The comments to the right of the read address buffer <NUM> indicate that these addressed are the first occurrence of the addresses, and the addresses are non-continuous to each other. A prefetch operation is not performed for these addresses. The next three read addresses received were A+x, E+x, and B+x, which are continuous or sequential to addresses A, E, and B, respectively. Because these read addresses are continuous to addresses stored in the read address buffer <NUM>, a prefetch operation is performed for the corresponding read request. The memory contents of A+x, E+x, and B+x are returned to the requesting device or devices and extra prefetched data is retrieved and stored in the prefetch buffer <NUM>. The amount of extra data may be all or a portion of the memory block in which the read address is included.

The next two addresses F, G, are addresses that are non-continuous to another address in the read address buffer <NUM> and a prefetch operation is omitted by the memory controller <NUM>. The next two addresses A+2x and E+3x are deemed to be continuous to addresses A+x and E+x, respectively, and extra prefetch data is retrieved for these read addresses. The logic circuitry <NUM> of the memory controller <NUM> may implement logic rules that deem a new address is a continuous address when the new address is within a certain number of addresses of a stored address. For instance, the logic circuitry <NUM> may include a rule that address E+3x is continuous to address E+x even though address E+2x is between the addresses. Other rules can be used to define continuity. For instance, the logic circuitry <NUM> of the memory controller <NUM> may deem that addresses are continuous when the addresses are within a same memory block of a predetermined size (e.g., the same block of <NUM> (<NUM>) memory addresses).

The last three addresses of the read address buffer <NUM> C+x, D+x, G+x, are continuous to addresses C, D, and G, stored in the read address buffer <NUM> and extra prefetch data is retrieved for the read requests for addresses C+x, D+x, and G+x. It can be seen from the example of <FIG>, that read addresses for both the omitted and the performed prefetch operations are stored in the buffer. This means that a prefetch operation may be performed for a read request with a read address continuous to a previous read request for which a prefetch operation was omitted.

Returning to <FIG>, because the memory device <NUM> is not local to a host device <NUM>, the memory device <NUM> can receive read requests from multiple host devices <NUM>. Each host device <NUM> can issue read requests at a different frequency. The frequency with which a host device sends read requests may depend on different operating characteristics of the host device <NUM> (e.g., the clock domain that the host device <NUM> operates in, the outstanding capability of the host device <NUM>, the configuration of the host device <NUM>, etc.). If different host devices <NUM> are accessing different address ranges of the memory array <NUM>, the asymmetrical memory accesses of the different host devices <NUM> may result in difficulty of prefetch operations being performed for some sequential read requests. This is because less demanding host devices (e.g., peripheral devices) will issue a read request occasionally, but highly demanding host devices (e.g., core processors, direct memory access controllers such as MDMAs, etc.) can issue back-to-back read requests for an extended time. The sequential read requests from the less demanding host devices may be shifted out of the shift register before the logic circuitry can recognize the requests as sequential.

For example, if less-demanding host devices are issuing read requests for continuous addresses but with a low frequency, and during same time duration more demanding host devices are issuing read requests with a high frequency but to an entirely different address space, then the prefetch buffer <NUM> may only perform prefetching with read requests from the more demanding host devices. In this case, the approach in the example of <FIG> may fail to recognize the continuous address accesses from the less demanding host devices <NUM>. As a result, less demanding host devices <NUM> won't see any benefit of prefetching.

<FIG> is a block diagram of another example of a read address buffer <NUM> that can help promote performance of prefetching by the less demanding host devices when the rate of read requests is uneven among the host devices <NUM>. The read address buffer <NUM> includes <NUM> memory registers in the example, but the read address buffer <NUM> may include a different number of memory registers (e.g., <NUM> memory registers). The prefetch logic circuitry <NUM> preserves the contents of a specified number of memory registers under certain conditions. The preservable number of memory registers is some number less than the total number of memory registers in the read address buffer <NUM>.

In the example of <FIG>, the last three memory registers (registers <NUM>-<NUM>) of the read address buffer <NUM> can be preserved, but the read address buffer <NUM> may preserve a different number of memory registers (e.g., <NUM>, <NUM>, or <NUM> memory registers of a <NUM> register read address buffer). The optimum number of memory registers to preserve may depend on the configuration of the computer system. The logic circuitry <NUM> preserves an address stored in a preservable memory register based on the new entries into the read address buffer <NUM>.

For example, the logic circuitry <NUM> may preserve a read address in one of the preservable memory registers until a read address is received that is continuous to the preserved read address stored in the memory register. When a continuous address is received, the prefetch operation is performed and the contents of the preservable memory register are overwritten in the next shifting of the read address buffer <NUM>. In the example of <FIG>, the logic circuitry <NUM> may preserve a read address in one of the preservable memory registers until a read address is received that is within the same <NUM> boundary of memory addresses as the preserved read address.

This technique promotes prefetching for the less demanding host devices. The preserving of read addresses can expire or timeout. In some examples, once a read address is preserved it is preserved for a specified number of read requests (e.g., <NUM> read requests). A different number of read requests can be used for the timeout, but the specified number is preferably greater than the number of memory registers in the read address buffer <NUM>. The optimum number may depend on characteristics of the host devices, such as the number of demanding host devices, the number of less-demanding host devices, the difference in frequency of read requests by the demanding host devices and the less-demanding host devices, etc. When the number of read requests are performed without a continuous address for a preserved address being received, the preserved address is "flushed" or overwritten by shifting of the memory registers of the read address buffer <NUM>.

In the example of <FIG> the logic circuitry includes a multiplexer <NUM>, a comparator <NUM>, and a timeout counter <NUM> for each of the preservable memory registers. The timeout counter <NUM> starts when a read address is stored in the register. When a new read address enters the prefetch buffer (IN), the new address in the first memory register is compared to the stored read address in the memory register (e.g., Register <NUM>), such as by comparing upper tag bits of the new address to the upper tag bits of the stored address using the comparator <NUM> for example. If the new address is not within the same <NUM> boundary as the address stored in register <NUM>, the contents of the Register is preserved (e.g., by recirculating the data via the "NO" input of the multiplexer <NUM>), and the timeout counter <NUM> is advanced (e.g., decremented). If the new address is within the same <NUM> boundary as the address stored in register <NUM>, a prefetch for the new address is performed, new contents are shifted into the Register (e.g., via the "YES" input of the multiplexer) and the timeout counter <NUM> is reset. New contents are also shifted into the register and the previously stored address is overwritten if the timeout counter times out (e.g., by decrementing to zero or incrementing to a specified number), but a read request continuous to the previously stored address is not received.

<FIG> is a diagram that illustrates an example of operation of the read address buffer <NUM>. The read address buffer <NUM> in the example has <NUM> memory registers and the last three registers (Registers <NUM>-<NUM>) are coupled to logic circuitry that makes them preservable. The top row of the diagram shows the contents of the <NUM> registers at a point in time, and the next three rows show three new entries being shifted into the shift register of the prefetch buffer. In the top row, Register <NUM> contains read address B, and none of the contents of Registers <NUM>-<NUM> includes a read address within the <NUM> boundary of B. In the second row of the diagram, address A+12x is shifted into Register <NUM> of the read address buffer <NUM>. Address A+12x is not within the <NUM> boundary of Address B and the contents of Register <NUM> are preserved. Address A+12x is within the <NUM> boundary of address A stored in Register <NUM> and address A+x in Register <NUM>, and the contents of Registers <NUM> and <NUM> are overwritten by shifting of the Registers and not preserved. The presence of any of the addresses A+nx addresses in the read address buffer <NUM> would cause the contents of Registers <NUM> and <NUM> to be overwritten because they are within the <NUM> boundary of the addresses stored in Registers <NUM> and <NUM>.

The same is true in the third row of the diagram. Address A+12x is shifted into Register <NUM> of the read address buffer <NUM>. Address A+13x is not within the <NUM> boundary of address B and the contents of Register <NUM> are preserved. Address A+13x is within the <NUM> boundary of address A+x stored in Register <NUM> and address A+2x in Register <NUM>, and the contents of Registers <NUM> and <NUM> are overwritten by shifting of the Registers and not preserved.

In the fourth row of the diagram, address B+x enters the read address buffer <NUM> and the address is within the <NUM> boundary of address B stored in Register <NUM>. A prefetch operation for the read of address B+x is performed, and the contents of Register <NUM> are flushed or overwritten. Had address B not been preserved, the prefetch for address B+x would have been treated as a non-continuous address and not performed even though address B+x was actually continuous to the previous prefetch request (address B) for that host device. The last three buffer registers will retain the address tag value until at least one in subsequent <NUM> transaction's tag bits matches with one of these three buffers. If none of <NUM> subsequent transaction's tag bits matches with any or all of these last three buffers of the read address buffer <NUM>, then those registers are overwritten.

The techniques of <FIG> and <FIG> improve the overall system performance when the demands for read requests are not even among the host devices. Sequential accesses from less demanding host devices are determined and prefetching is done for the less demanding host devices. So subsequent accesses from less demanding masters will be hit and extra data will be provided from prefetch operations in anticipation of a subsequent read to the same memory block. The timeout count of <NUM> transactions covers the condition of one of the host devices stopping requests to the memory device. The last read address for this host device will be automatically removed on the <NUM>th transaction entering the input of read address buffer <NUM>.

The timeout count value of <NUM> transactions is selected from simulations of the computer system. Prefetching for host devices that do not request read data more than once in <NUM> transactions was determined to be avoided. Prefetching should be avoided for extremely sparse read transactions from any host device (e.g., less often than <NUM> transactions). Instead, simulation showed that the computer system performed better when such sparse memory transactions requesting data were directly provided from the memory device to the host device without prefetching. The optimum counter value may be different for different computer systems. The techniques of <FIG> and <FIG> are flexible to accommodate changes to the parameters of the read address buffer such as the timeout count value.

For completeness, <FIG> is a flow diagram of an example of a method <NUM> of operating a memory device, such as memory device <NUM> in <FIG>. At block <NUM>, a memory read request is received by the memory device <NUM> from a separate device (e.g., at least one host device <NUM> in <FIG>). The read request includes a current read address. At block <NUM>, the current read address is compared to previous read addresses stored in a read address buffer (e.g., any of read address buffers in <FIG>).

At block <NUM>, extra read data is stored in a prefetch buffer. The extra read data is not requested by the current read operation, and is data prefetched in anticipation of a subsequent read request close to the current read address. The extra read data is read from one or more memory addresses contiguous to the current read address when the prefetch logic circuitry determines that the current read address is a continuous address to an address stored in the read address buffer. At block <NUM>, prefetching of the extra read data is omitted when the prefetch logic circuitry determines that the current read address is non-continuous address to an address stored in the read address buffer. The prefetch buffer and the prefetch logic circuitry can be implemented as a stand-alone memory controller, or they can be included in L2 or L3 memory, or included in a host device.

The several examples of systems, devices, and methods described provide techniques for smart prefetching of memory data. The techniques avoid prefetching operations degrading the read performance of memory devices of a computer system. Simulations have shown that the smart prefetching techniques improve bandwidth of memory requests over conventional prefetching techniques.

A first Aspect (Aspect <NUM>) includes subject matter (such as a memory device) comprising a memory array including memory cells to store memory data, and a memory controller. The memory controller includes prefetch buffer, a read address buffer including memory registers to store addresses of memory read requests received from at least one separate device, and logic circuitry. The logic circuitry stores extra read data in the prefetch buffer when an address of a read request is a continuous address of an address stored in the read address buffer, and omits prefetching the extra data when the address of the read request is a non-continuous address of an address stored in the read address buffer.

In Aspect <NUM>, the subject matter of Aspect <NUM> optionally includes a read address buffer with memory registers included in a first-in first-out shift buffer and the logic circuitry is configured to store read addresses of both read requests resulting in prefetching of extra data and read requests for which prefetching was omitted in the first-in first-out shift buffer.

In Aspect <NUM>, the subject matter of one or both of Aspects <NUM> and <NUM> optionally includes a read address buffer that is an M memory register buffer, wherein M is a positive integer. The logic circuitry optionally preserves read addresses stored in N memory registers of the M memory registers, wherein N is a positive integer less than M, and preserves a read address in one of the N memory registers until a read address is received that is continuous to the preserved read address.

In Aspect <NUM>, the subject matter of Aspect <NUM> optionally includes logic circuitry that flushes the preserved read address when the read address that is continuous to the read prefetch address is received, or a read address continuous to the preserved read address is not received within P read requests of a read request corresponding to the preserved read address, where P is a positive integer greater than M.

In Aspect <NUM>, the subject matter of one or both of Aspects <NUM> and <NUM> optionally includes a read address buffer that is a first-in first-out M register shift buffer and the logic circuitry is configured to preserve the read addresses in the last N memory registers of the first-in first-out M register shift buffer.

In Aspect <NUM>, the subject matter of one or any combination of Aspects <NUM>-<NUM> optionally includes a timeout counter for each register of the N-bit registers and logic circuitry that starts the timeout counter for a register of the N-bit registers when a read address is stored in the register, preserves the contents of the register and advance the timeout counter for the register when a read address continuous to the preserved read address is not received, and enables the contents of the register to be overwritten when the corresponding timeout counter for the register times out.

In Aspect <NUM>, the subject matter of one or any combination of Aspects <NUM>-<NUM> optionally includes logic circuitry that prefetches the extra data when the read address is included in a memory block that also includes at least one other address stored in the read address buffer.

In Aspect <NUM>, the subject matter of one or any combination of Aspects <NUM>-<NUM> optionally includes logic circuitry that prefetches the extra data when the address of the prefetch request is within a predetermined address offset from at least one other address stored in the read address buffer,.

Aspect <NUM> includes subject matter (such as a method of operating a memory device) or can optionally be combined with one or any combination of Aspects <NUM>-<NUM> to include such subject matter, comprising receiving, by the memory device from at least one separate device, a memory read request including a current read address; comparing the current read address to previous read addresses stored in a read address buffer; storing, in a prefetch buffer, non-requested extra read data from one or more memory addresses contiguous to the current read address when prefetch logic circuitry determines that the current read address is a continuous address to an address stored in the read address buffer; and omitting prefetching of the extra read data when the prefetch logic circuitry determines that the current read address is non-continuous address to an address stored in the read address buffer.

In Aspect <NUM>, the subject matter of Aspect <NUM> optionally includes storing read addresses in the read address buffer, wherein the read address buffer is a first-in first-out shift buffer; and prefetching the extra data when the current read address is within a specified number of addresses of a read address stored in the first-in first-out shift buffer.

In Aspect <NUM>, the subject matter of one or any combination of Aspects <NUM> and <NUM> optionally includes storing read addresses in an M register buffer (M being a positive integer) and preserving read addresses stored in N registers of the M register buffer (N being a positive integer less than M). A read address is preserved until a read address is received that the prefetch logic circuitry determines is continuous to the preserved prefetch address.

In Aspect <NUM>, the subject matter of Aspect <NUM> optionally includes a preserved read address being flushed from the M register buffer when the read address continuous to the preserved read address is received, or when a continuous read address is not received within P read requests of a read request corresponding to the preserved read address (P being a positive integer greater than M).

In Aspect <NUM>, the subject matter of one or both of Aspects <NUM> and <NUM> optionally includes storing the read addresses stored in the last N registers of a first-in first-out M register shift buffer.

In Aspect <NUM>, the subject matter of one or any combination of Aspects <NUM>-<NUM> optionally includes starting a timeout counter for each register of the N-bit registers when a read address is stored in the register, preserving the contents of the register and advancing the timeout counter for the register when a read address continuous to the preserved read address is not received, and flushing the contents of the register when the corresponding timeout counter for the register times out.

In Aspect <NUM>, the subject matter of one or any combination of Aspects <NUM>-<NUM> optionally includes not prefetching the extra data when the address of the read request corresponds to a memory block that does not include any of the other read addresses stored in the read address buffer.

Aspect <NUM> includes subject matter (such as a computing system) or can optionally be combined with one or any combination of Aspects <NUM>-<NUM> to include such subject matter, comprising multiple host devices and a shared memory device to receive memory requests from the host devices. The memory device includes a memory array including memory cells to store memory data and a memory controller operatively coupled to the memory array. The memory controller includes a read address buffer including memory registers to store addresses of memory read requests received from at least one separate device, a prefetch buffer, and logic circuitry. The logic circuitry is configured to store extra read data in the prefetch buffer when determining an address of the read request is a continuous address of an address stored in a read address buffer, and omit prefetching of the extra read data when determining the address of the read request is a non-continuous address of an address stored in the read address buffer.

In Aspect <NUM>, the subject matter of Aspect <NUM> optionally includes the read address buffer being an M memory register buffer (M being a positive integer), and includes logic circuitry configured to preserve read addresses stored in N memory registers of the M memory registers (N being a positive integer less than M), and preserve a read address in one of the N memory registers until a read address is received that is determined by the logic circuitry to be continuous to the preserved read address.

In Aspect <NUM>, the subject matter of Aspect <NUM> optionally includes logic circuitry configured to flush the preserved read address from the read address buffer when the read address that is continuous to the preserved read address is received, or a read address continuous to the preserved read address is not received within P read requests of a read request corresponding to the preserved read address (P being a positive integer greater than M).

In Aspect <NUM>, the subject matter of one or both of Aspects <NUM> and <NUM> optionally includes a read address buffer of the memory controller that is a first-in first-out M register shift buffer, and logic circuitry configured to preserve the read addresses in the last N memory registers of the first-in first-out M register shift buffer.

In Aspect <NUM>, the subject matter of one or any combination of Aspects <NUM>-<NUM> optionally includes a timeout counter for each register of the N-bit registers, and logic circuitry configured to start the timeout counter for a register of the N-bit registers when a read address is stored in the register, preserve the contents of the register and advance the timeout counter for the register when a read address continuous to the preserved read address is not received, and enable the contents of the register to be overwritten when the corresponding timeout counter for the register times out.

In Aspect <NUM>, the subject matter of one or any combination of Aspects <NUM>-<NUM> optionally includes a read address buffer that is a first-in first-out shift register that stores a record of read addresses for memory read requests.

These non-limiting Aspects can be combined in any permutation or combination. " All publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein. " Also, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim.

Claim 1:
A memory device (<NUM>) comprising:
a memory array (<NUM>) including memory cells to store memory data;
a memory controller operatively coupled to the memory array and including:
a prefetch buffer (<NUM>);
a read address buffer (<NUM>) including memory registers to store addresses of memory read requests received from at least one separate device, wherein the read address buffer is an M memory register buffer, wherein M is a positive integer; and
logic circuitry (<NUM>) configured to:
store extra read data in the prefetch buffer when an address of a read request is a continuous address of an address stored in the read address buffer;
omit prefetching the extra data when the address of the read request is a non-continuous address of an address stored in the read address buffer;
preserve read addresses stored in N memory registers of the M memory registers, wherein N is a positive integer less than M; and
preserve a read address in one of the N memory registers until a read address is received that is continuous to the preserved read address.
wherein the logic circuitry is configured to flush the preserved read address when the read address that is continuous to the read prefetch address is received, or a read address continuous to the preserved read address is not received within P read requests of a read request corresponding to the preserved read address, wherein P is a positive integer greater than M.