Patent Description:
Electronic integration circuits are well-known and readily available for a number of electronic applications. A conventional integrator circuit includes an operational amplifier that provides a desired current response, wave shape, or other signal conditioning functions.

The presence of an amplifier in an integrator circuit may operate under strict time and peak current conditions, which prohibits the circuit from achieving a combination of ideal characteristics in order to integrate a linear current ramp necessary for driving the integrator input.

It is desirable that a simple integrator circuit, for example, comprising few transistors including a follower stage, that is capable of driving a high peak current rise, e.g., 130mA, in a coil in 6ns or less.

<NPL>, discloses MOSFET based on continuous time integrators, including a simple unbalanced passive-saturation integrator in which a current source in the source of the transistor is used when the input signal source cannot handle the input bias current.

European patent application, publication number <CIT>, discloses a circuit to control an inductive load by an N channel MOS power transistor. An N and P-type transistor are included to respectively handled the negative voltage is induced by the inductor and to isolate the gate of the power transistor.

The present invention is illustrated by way of example in the accompanying figures, in which like references indicate similar elements.

In brief overview, embodiments of the present inventive concept include a simple integrator circuit that can drive a small inductor with an integrator amplifier that generates a quadratic shape pulse based on the integration of a linear ramp current. The integrator circuit operates under strict and tight parameters, in particular, providing a bias current to maintain the integrator input at the same voltage with little or no input current with respect to a small inductor, where the signals having a predetermined longer pulse duration (e.g., 6ns compared to conventional 2ns or 4ns pulse durations) and high peak current (e.g., 150mA). The integrator can be implemented in various electronic applications including, but by no means limited to, automotive, industrial, and consumer applications. One example application may include a 10Mbit/s isolated communication bus for a battery management system (BMS), which requires the integrator to drive a 30nH inductive load requiring a pulse producing a 130mA current in 6ns. Other high speed isolated communication network electronic circuits may equally apply, for example, a microcontroller, battery cell controller, transceiver, and so on.

<FIG> is a block diagram of an integrator circuit <NUM> of a communication bus <NUM>, in accordance with some embodiments. The integrator circuit <NUM> can be implemented in various electronic applications including, but by no means limited to, automotive, industrial, and consumer applications including signal processing or battery management systems. One application includes the implementation of a computer chip or related electronic integration circuit for a communication bus.

As shown in <FIG>, the integrator circuit <NUM> can comprise a first stage driver <NUM>, an integrator input element <NUM>, an inductive load driver <NUM>, and an integrator capacitor <NUM>. The first stage driver <NUM>, the integrator input element <NUM>, and the inductive load driver <NUM> are formed of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), and preferably NMOS transistors.

The inductive load driver <NUM> is constructed and arranged to drive an inductive load such as a coil <NUM> as a voltage follower stage. The inductive load driver <NUM> can have a source coupled to both the integrator capacitor <NUM> and the coil <NUM>. The capacitor <NUM> is coupled to the conductive path between the inductive load driver <NUM> and the coil <NUM>. The inductive load driver <NUM> further has a drain and gate each coupled to a current source <NUM>, for example, a 2mA current source.

The first stage driver <NUM> is constructed and arranged to drive the follower stage via the drain of the first stage driver <NUM>, which can be in electrical communication with the gate of the inductive load driver <NUM>. In some embodiments, the first stage driver <NUM> can be formed of a source follower circuit, wherein the source of the first stage driver <NUM> can be coupled to ground. The gate of the first stage driver <NUM> can be coupled between a first current source <NUM> and a source of the integrator input element <NUM>. In a DC state, the gate of the integrator input element <NUM> can be connected to a voltage supply. In some embodiments, the voltage supply can be a <NUM>. 5V voltage supply, for example, provided by a switching device <NUM>. The voltage may range from <NUM>-2V, but not be limited thereto. The input current source <NUM> coupled to the gate of the integrator input element <NUM> can generate a linear current ramp from <NUM> to 700µA in 6ns. The first stage driver <NUM> can be biased, for example, at 2mA but not limited thereto, by a closed loop which controls the drain current of the integrator input <NUM>.

During operation, the first stage driver <NUM>, integrator input element <NUM>, inductive load driver <NUM>, and integrator capacitor <NUM> operate to provide a quadratic output voltage to drive a current in the 30nH coil <NUM> by integrating a linear current ramp in the capacitor <NUM>. Accordingly, the integrator circuit <NUM> requires only three MOS transistors, including the follower stage, to provide a quadratic output voltage of <NUM>. 5V in 6ns and drive 120mA in the 30nH coil by integrating a linear current in the capacitor <NUM>, and produce negligible or no input current (e.g., integrator input element <NUM>) resulting in an integration of the linear input current in the integrator capacitor <NUM>.

<FIG> is a schematic representation of an integrator circuit <NUM>, in accordance with an embodiment. As shown, the integrator circuit <NUM> can be part of an isolated communication bus or the like, for example, a capacitive isolation line at a transmit side of a transformer of a bus. The integrator circuit <NUM> can comprise a first stage driver <NUM>, an integrator input element <NUM>, an inductive load driver <NUM>, and an integrator capacitor <NUM>, which may be the same or similar to those described with reference to <FIG> but may be configured and arranged in the circuit <NUM> in a different manner than the circuit <NUM> of <FIG>. During operation, the first stage driver <NUM>, integrator input element <NUM>, inductive load driver <NUM>, and integrator capacitor <NUM> can operate to generate an integrator current of 0A in a DC state. To achieve a 1mA bias, the circuit <NUM> can provide an integration of the linear input current at the capacitor <NUM>.

In particular, the inductive load driver <NUM> operates as a power MOS transistor, which can be biased at 1mA in the DC state. To achieve the 1mA bias, the circuit <NUM> can include a copy MOS transistor <NUM> having a source coupled to the coil <NUM> and the capacitor <NUM>, a drain coupled to a current source, for example, a 1mA source, and a gate coupled to the gate of the inductive load driver <NUM>, which in turn has a sufficient current to drive a 30nH coil <NUM>. The circuit <NUM> provides a copy of the inductive load driver current to the copy MOS transistor <NUM> at which the copy MOS current can be up to <NUM> times smaller than the inductive load driver current, assuming that the 30mH coil <NUM> can be a short in the DC state. For example, as shown in <FIG>, the copy MOS transistor <NUM> can be set at 10µA, or in a range between <NUM>-20µA so that the inductive load driver current can be <NUM> mA, or in a range between <NUM>-2mA. NMOS transistor <NUM>, and PMOS transistor <NUM> can be in series with the first stage driver <NUM> and drive the gate of the power MOS <NUM>. The first NMOS transistor <NUM> may be set to have a current, e.g., 2mA, at its drain and driven by the first stage driver <NUM>. The first stage driver <NUM> current (e.g., 2mA) can be controlled by a copy of the first stage circuit <NUM>, in particular, a copy NMOS transistor <NUM>, or <NUM> times smaller. In particular, the drain current of the copy NMOS transistor <NUM> can be forced at 200µA, or in a range between at <NUM>-300µA with a 20µA or range between <NUM>-30µA current pulldown current source <NUM> and PMOS mirror transistors <NUM>, <NUM>. The drain of the second PMOS mirror transistor <NUM> can drive the current in the integrator input element <NUM> through a closed loop transistor <NUM>, wherein a control transistor <NUM> controls the current at the drain of the closed loop transistor <NUM> and the mirror transistors <NUM>, <NUM>. Therefore, in the DC state, the integrator current (Iint) can be 0A, or a negligible value between <NUM>-1A, the gate of the integrator input element <NUM> can be connected to the voltage supply, e.g., <NUM>. 5V or a voltage range between <NUM>-5V, and the closed loop controls the current in the integrator input element <NUM>, which in turn can control the first stage driver <NUM> and the power MOS <NUM>, and permits the power MOS <NUM> to drive the 30mH coil <NUM> as a follower stage, for example, driving a 150mA current at the coil <NUM> in 6ns or less.

<FIG> is a schematic representation of an electronic integration "integrator" circuit <NUM>, in accordance with another embodiment. The integrator circuit <NUM> can include components constructed and arranged in a similar manner as those of the integrator circuit <NUM> of <FIG>, details of which are not repeated for brevity. In addition, the integrator circuit <NUM> can include a first switch <NUM>, e.g., an NMOS transistor and a second switch <NUM>, e.g., an NMOS transistor <NUM>. The first switch <NUM> can be coupled between the copy NMOS transistor <NUM> and the source of the integrator input element <NUM>. The second switch <NUM> can be coupled between the gate of the integrator input element <NUM>, the voltage source (e.g., <NUM>. 5V) and the current source (Iint).

During an operation involving voltage driven pulse commands (see <FIG>), at the pulse starting point (see <FIG>), the integrator input element <NUM> can be attached at a predetermined voltage such as <NUM> V, or <NUM>-3V, with a current range of. <NUM>- 2mA, preferably 1mA in the inductive load driver <NUM>, which functions as a final power stage NMOS transistor. When the power command can be initiated, the switch signals S1, S2 may be applied to the first switch <NUM> and second switch <NUM>, respectively, to cause the first and second switches to <NUM>, <NUM> to be in an open state, or inactivated, whereby the first power switch <NUM> can be turned off by the signal S1 transitioning from <NUM>. 5V to 0V to preserve the DC state of the copy NMOS transistor <NUM> for the pulse duration. The capacitor <NUM> connected between the gate of the copy NMOS transistor <NUM> and the drain of the first switch transistor <NUM> can allow the DC state current to be maintained at the integrator input element <NUM>.

The second switch transistor <NUM> can be turned off when the signal S2 transitions from a higher voltage, e.g., 3V to a lower voltage, e.g., <NUM>. The input switch command (S) begins with the integration current (Iint). As the totality of the current Iint, e.g., up to 700µA, flows in the integrator capacitor <NUM>, e.g., a 1pF capacitor, the output can have a t<NUM> shape from <NUM>-<NUM>. 5V in 6ns, as shown in <FIG>. According, the S2 signal can drive the t<NUM> shape.

At time tend (see <FIG>), when the signal S2 increases, the current in the coil <NUM> reaches a value of around <NUM> to 150mA with a t<NUM> shape. The integration stops when the S2 signal increases and the linear Iint current can be reduced to 0A. The signal S2 increases, or changes state, when the coil current can be reduced to 0A, or a negligible current for example, <NUM>-1mA in the DC state. At the end of the coil command, i.e., the rightmost shape shown in <FIG>, the current may return to 0A, or negligible current for example, <NUM>- 1mA at the final power stage <NUM> in a DC state.

<FIG> illustrate various voltages and currents across the coil <NUM>. As shown in <FIG>, the quadratic pulse can be selected over a square pulse and a linear pulse as the preferred command option because it allows the longer pulse of 6ns to provide the same coil current. The t<NUM> shape voltage source across the inductor allows for a longer command to achieve the same maximum current in the coil. As U=ldI/dt, the current may have a t<NUM> shape due to the current derivation in t<NUM> providing a voltage shown in the t<NUM> shape.

During an operation involving current integration (see <FIG>), a perfect integration circuit requires no input current at the integrator input so that the current will flow to an integrator capacitor <NUM>. Also, a perfect integration circuit requires the frequency or the periodic time of the input wave to be less than the circuit time constant. %To comply with a desired threshold of 6ns, the integrator operates with few components, i.e., NMOS transistors <NUM>, <NUM> and no operational amplifier. Components <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may be the same as or similar to those components described in the circuits of <FIG> so details thereof are not repeated for brevity.

During the linear current ramp integration including the generation of a t<NUM> shape voltage across the coil <NUM>, the maximum current at the gate of the inductive load driver transistor <NUM> ranges from <NUM>-2mA, preferably <NUM>. 5mA, which activates the inductive load driver <NUM>. Here, the bias current of the first stage driver transistor <NUM> may be greater than <NUM>. 5mA, for example, configured to operate at 2mA. The gate current of the inductive load driver <NUM> may be linear. Accordingly, the drain current of the first stage driver transistor <NUM> can drop from 2mA to <NUM>.

In doing so, the gate-source voltage (Vgs) of the first stage driver transistor <NUM> (Vg1) decreases. To achieve an integration, the gate current of the integrator input element <NUM>, e.g., including an NMOS transistor or the like, may be 0A or a negligible current between <NUM>-1mA. In other words, to achieve a 0uA input current, Vinc = Vg1 + Vg2 of the integrator may be constant during the time integration, for example, Vinc=Vg1+Vg2, where Vg2 is the gate-source voltage of the NMOS transistor <NUM>. However, a significant amount of the bias current of the first stage driver transistor <NUM> can be applied to the gate of the follower <NUM>. Therefore, the current at the first stage driver transistor <NUM> may not be constant, resulting in a drop of gate-source voltage (Vg1) of the first stage driver transistor <NUM>.

The addition of a linear current ramp at the source of the NMOS transistor <NUM> allows the DC bias current to contribute to the maintaining of the integrator input voltage, where little or no current is injected into the integrator input and all the linear input current instead flows into the capacitor <NUM> to be integrated and achieve the t<NUM> voltage shape at the opposite side of the capacitor <NUM>. In doing so, gate-source voltage of the NMOS transistor <NUM> (Vg2) increases to compensate for a commensurate decrease in the gate-source voltage of the first stage driver transistor <NUM> (Vg1). However, since NMOS transistor <NUM> can be substantially less than that of the first stage driver transistor <NUM>, the gate current of the NMOS transistor <NUM>, for example, 1nA-100nA. As shown in <FIG>, the gate current of the NMOS transistor <NUM> (A) has an average of about 5nA.

<FIG> and <FIG> also illustrate a circuit <NUM> and its impact of the linear ramp current (B) of the NMOS transistor <NUM> of 140µA in 6ns. Also shown is a plot of the integrator input with (C) and without (D) the linear current of the NMOS transistor <NUM>. To maintain a constant voltage (Vinc), the bias current of the integrator input element <NUM> may increase. As shown in <FIG>, the voltage shown at region ( inc) can be provided with a constant current <NUM> (G) and with the current <NUM> having a current ramp to allow the voltage (Vinc) to be constant. If the gate current at integrator input element <NUM> is <NUM>, the voltage (Vinc) can be flat (V). Otherwise the voltage decreases, which affects the output voltage. For example, when the drain current of NMOS transistor <NUM> changes, the voltage (Vg1) decreases. In DC state the current source <NUM> can be adjusted to arrive at Vg1+Vg2 = <NUM>. But when voltage Vg2 goes low, the current <NUM> may increase to increase voltage Vg2 and maintain Vg1+Vg2 = <NUM>.

Also shown is the impact on the output voltage. With the linear current of the NMOS transistor <NUM> at the current source <NUM>, the output voltage may be close to the ideal t2 shape, e.g., reference curve (E). In contrast, curve (F) pertains to an output without the linear current ramp. Here, about <NUM>. 7V of the peak amplitude can be lost because a significant amount of the integration current can be applied to the integrator input. With the additional linear current at the NMOS transistor <NUM>, which keeps the integrator input constant, a fast integrator of 6ns pulse can be obtained with the four components (<NUM>, <NUM>, <NUM>, and <NUM>) collectively driving 150mA in the 30mH coil <NUM>.

<FIG> illustrate an operation that includes generating a linear current ramp from <NUM>-140µA in 6ns, for example, how a linear current <NUM> can be added to an integrator input element <NUM>, e.g., including an NMOS transistor or the like. Reference can also be made to the circuit shown in <FIG>. A first closed loop DC current <NUM> goes in the NMOS mirror current transistors <NUM>, <NUM> with a gain of <NUM>. Here, a ramp current may increase from <NUM>-80µA in 6ns. As shown in <FIG>, to accommodate this short timing, the active components may be biased, i.e., not in an off state with 0A current. This is illustrated in <FIG>. The capacitor <NUM> can be shorted by the integrator input element <NUM>, e.g., including a NMOS transistor or the like so there is no current in the capacitor <NUM>. For example, when NMOS transistor <NUM> is open (driven by signal A), the bias current given by the closed loop can flow in the capacitor <NUM> and generates the linear B signal from <NUM> to 550mV. However, the NMOS mirror transistors <NUM>, <NUM> may be biased with the same current as the current <NUM>, through a closed loop formed by current source <NUM> and NMOS transistors <NUM>, <NUM>, and <NUM>.

Although NMOS transistors are described by way of example, other electromagnetic signal switching electronic devices may equally apply. Therefore, in a DC state, when NMOS transistor <NUM> coupled to be parallel capacitor <NUM> is closed, the RC node formed between capacitor <NUM> and resistor <NUM> has the same voltage as the voltage (Vgs) of mirror transistor <NUM> and NMOS mirror current transistor <NUM>, where the resistor <NUM> has no current. When the signal (A) at the gate of the NMOS transistor <NUM> is low, the capacitor <NUM> can be driven by the closed loop formed by current source <NUM> and NMOS transistors <NUM>, <NUM>, and <NUM> to receive a constant current equal to currents <NUM>, <NUM>. As the NMOS transistor <NUM> drives the voltage node (RC), it forces a linear voltage across the capacitor <NUM> to generate a constant current equal to I(<NUM>)=C dV/dt, where C is the capacitance of capacitor <NUM>. The resistor <NUM> in parallel with the capacitor <NUM> can receive the same linear voltage transformed in a current ramp by the equation I=U/R. The linear voltage ramp of the capacitor <NUM> can be applied to the resistance of the resistor <NUM>. As shown in <FIG>, the NMOS transistor <NUM> of <FIG> can create the current source <NUM>.

As shown in <FIG>, the main currents and voltage of the circuit <NUM> of <FIG> provide a linear current ramp from <NUM>-80µA in 6ns (see line IRramp). A digital command (A) can drive the linear voltage ramp (VCramp) from <NUM>-550mV in 6ns, or a range of 4ns-8ns but not limited thereto.

As will be appreciated, embodiments as disclosed include at least the following embodiments. In one embodiment, an electronic integration circuit can comprise a first stage driver; an integrator input element coupled between a voltage source, an input current source, and the first stage driver, the integrator input element that provides a final power stage of the electronic integration circuit and provides a constant drain current in a direct current state that controls a current of the first stage driver; an inductive load driver constructed and arranged to drive an inductive element as a voltage follower stage, wherein the inductive load driver processes a linear gate current to control a current output to the inductive element; and a capacitor between the first stage driver and the integrator input element, wherein a sum of a gate-source voltage of the first stage driver and a gate-source voltage of the integrator input element is provided as an integrator input to the capacitor, and wherein the capacitor performs a linear current ramp integration operation to provide a t<NUM> voltage shape across the inductive element required for driving the inductive element in accordance with the controlled current output in a t<NUM> shape.

The integrator input element can provide an additional linear current to maintain a constant integrator input voltage at the integrator input.

The first stage driver, the integrator input element, the inductive load driver, and the capacitor can collectively produce a 6ns pulse that drives 150mA in the inductive element, and wherein the inductive element can include a 30mH coil.

The integrator input element can include an NMOS transistor having a source coupled between a current source and a gate of the first stage driver, a drain coupled to the voltage source, and a gate coupled to the input current source.

At least one of the input current source or a voltage source coupled to the gate of the integrator input element can be constructed and arranged to generate a linear current ramp from <NUM> to 700µA in 6ns.

The electronic integration circuit can further comprise a voltage switch that places the electronic integration circuit in a direct current state when the integrator input element is connected to a voltage supply by the voltage switch.

The electronic integration circuit can further comprise a first switching device coupled to a copy NMOS transistor connected to the first stage driver; and a second switching device coupled between the gate of the integrator input element, a voltage source, and a current source, wherein the first and second switching devices are constructed and arranged to maintain a DC state current at the integrator input element for generating an integration of a linear input current in the capacitor.

The inductive load drive can have a source coupled to both the capacitor and the inductive element.

The linear current ramp operation can output a linear input current to the capacitor to be integrated and to generate the t<NUM> voltage shape and injects little or no current at the integrator input element.

The first stage driver and the integrator input element can provide an integration function so that no input current is in an integrator input signal.

In another embodiment, an electronic integration circuit can comprise an integrator input element coupled to a voltage source and an input current source; a switching device that receives a pulse command that open the switching device to control a current at a gate of the integrator input element and preserve a direct current state of a voltage for a duration of the pulse command; an inductive load driver constructed and arranged to drive an inductive element, wherein the inductive load driver processes a linear gate current to control a current output to the inductive element; and a capacitor at the integrator input element that maintains the DC state at the integrator input element and performs a linear current ramp integration operation according to the pulse command.

The electronic integration circuit can further comprise a copy NMOS transistor; and another switching device coupled between the copy NMOS transistor and the source of the integrator input element, wherein the other power switch is inactivated by a signal to preserve the DC state of the copy NMOS transistor for the pulse duration.

The capacitor can be connected between the gate of the copy NMOS transistor and a drain of the other switching device to permit the DC state current to be maintained at the integrator input element.

The switching device can be turned off when a signal applied to the switching device transitions from a first voltage to a second voltage lower than the first voltage, wherein an input switch command is initiated with an integration current, and as the integration current is received by the capacitor, the electronic integration circuit generates an output having a t<NUM> shape driven by the signal.

The t<NUM> shape can drive the inductive element in accordance with a controlled current output in a t<NUM> shape.

The integrator input element can be constructed and arranged to generate a linear current ramp from <NUM> to 700µA. When the linear current ramp is formed whereby a current of up to 700µA flows in the capacitor, an output is generated that drives a current at the inductive element in 6ns or less.

In another embodiment, a driver for a communication bus can comprise an electronic integration circuit, comprising: a first stage driver; an integrator input element coupled between a voltage source, an input current source, and the first stage driver, the integrator input element that provides a final power stage of the electronic integration circuit and provides a constant drain current in a direct current state that controls a current of the first stage driver; an inductive load driver constructed and arranged to drive an inductive element as a voltage follower stage, wherein the inductive load driver processes a linear gate current to control a current output to the inductive element; and a capacitor between the first stage driver and the integrator input element that performs a linear current ramp integration operation for the inductive element.

The integrator input element can provide an additional linear current to maintain a constant integrator input voltage at the integrator input. When the capacitor forms linear current ramp up to 700µA, an output can be generated that drives a current at the inductive element in 6ns or less.

Claim 1:
An electronic integration circuit (<NUM>), comprising:
a MOSFET first stage driver (<NUM>) configured to drive a voltage follower stage;
a MOSEFT integrator input element (<NUM>) having a drain coupled to a voltage source, a gate coupled to an input current source (<NUM>) configured to provide a linear current ramp, and a source coupled to both the MOSFET first stage driver (<NUM>) and a current source, the MOSFET integrator input element (<NUM>) configured to provide a constant drain current in a direct current state that controls a current of the MOSFET first stage driver (<NUM>);
an inductive element (<NUM>);
a MOSFET inductive load driver (<NUM>) constructed and arranged to provide a final power stage of the electronic integration circuit to drive the inductive element (<NUM>) as the voltage follower stage, wherein the MOSFET inductive load driver (<NUM>) is configured to process a linear gate current to control a current output to the inductive element (<NUM>); and
a capacitor (<NUM>) between the MOSFET first stage driver (<NUM>) and the MOSFET integrator input element (<NUM>), wherein a sum of a gate-source voltage of the MOSFET first stage driver (<NUM>) and a gate-source voltage of the MOSFET integrator input element (<NUM>) is provided as an integrator input to the capacitor (<NUM>), and wherein the capacitor (<NUM>) performs a linear current ramp integration operation to provide a first quadratic voltage shape across the inductive element (<NUM>) required for driving the inductive element (<NUM>) in accordance with the controlled current output in a second quadratic voltage shape.