Patent Description:
A diffractive optical element (DOE) may be used for directing a beam. For example, a DOE, such as a diffractive lens, a spot array illuminator, a spot array generator, a Fourier array generator, and/or the like, may be used to split a beam, shape a beam, focus a beam, and/or the like. A DOE may be integrated into a multicast switch, a wavelength selective switch, a gesture recognition system, a motion sensing system, a depth sensing system, and/or the like.

A two-level surface relief profile (sometimes termed a "binary surface relief profile") may be selected for a surface relief DOE. For example, the two-level surface relief profile may be selected to approximate a continuous surface relief profile and to enable use of a photolithographic procedure and/or an etching procedure to manufacture the DOE. A two-level thin film stack may be used to create a single order binary DOE, such as a diffractive lens, and may be associated with a diffraction efficiency of approximately <NUM>% for a single order binary DOE. The two-level thin film stack may be used for a spot array generator, and may provide a symmetrical spot array. For example, utilizing a two-level thin film stack may provide an axis of symmetry such that intensity of spots is associated with a <NUM> degree axis of symmetry. Some materials used for DOEs may require a relief depth of greater than a threshold, thereby resulting in a threshold etch time to manufacture the DOE.

According to some possible implementations of the present invention, a transmissive surface relief diffractive optical element configured to provide an anti-reflectance functionality in a particular wavelength range of incident light and having etched regions and un-etched regions comprises a substrate. The transmissive surface relief diffractive optical element comprises a first anti-reflectance structure for a particular wavelength range formed on the substrate. The transmissive surface relief diffractive optical element comprises a second anti-reflectance structure for the particular wavelength range formed on the first anti - reflectance structure. The transmissive surface relief diffractive optical element comprises a third anti-reflectance structure for the particular wavelength range formed on the second anti-reflectance structure. The transmissive surface relief diffractive optical element comprises at least one layer disposed between the first anti-reflectance structure and the second anti-reflectance structure or between the second anti-reflectance structure and the third anti-reflectance structure. A first relief depth between a first surface of the first anti-reflectance structure and a second surface of the second anti-reflectance structure and a second relief depth between the first surface and a third surface of the third anti-reflectance structure are configured to form the surface relief diffractive optical element associated with a first phase delay and a second phase delay, respectively, for the particular wavelength range. The first anti-reflectance structure comprises a first top layer and the second anti-reflectance structure comprises a second top layer, each of the first top layer and the second top layer being an etch stop layer to enable etching to form a phase delay. Each of the first anti-reflectance structure including the first top layer, the second anti-reflectance structure including the second top layer, and the third anti-reflectance structure comprises alternating layers of two materials, and thereby forming a three-level relief profile having anti-reflectance structures built into each etched stack of the surface relief diffractive optical element and built into the un-etched stack without requiring additional anti-reflectance coatings or structures on the top surface of the three-level relief profile.

The first phase delay may be a π/<NUM> phase delay and the second phase delay may be a π phase delay.

The first anti-reflectance structure, the second anti-reflectance structure, and the third anti-reflectance structure may be formed from alternating layers of silicon and silicon dioxide.

The first anti-reflectance structure and the second anti-reflectance structure may be formed from alternating layers of hydrogenated silicon and silicon dioxide.

The first anti-reflectance structure may be formed from a first layer of a first material and a second layer of a second material; wherein the at least one layer may be formed from a third layer of the first material; wherein the second anti-reflectance structure may be formed from a fourth layer of the second material and a fifth layer of the first material; and wherein the third anti-reflectance structure may be formed from a sixth layer of the second material and a seventh layer of the first material.

The first anti-reflectance structure may be formed on a first side of the substrate; and the surface relief diffractive optical element may further comprise: a plurality of other anti-reflectance structures for the particular wavelength range formed on a second side of the substrate.

The particular wavelength range may be between <NUM> nanometers and <NUM> nanometers.

According to some possible implementations of the present invention, a method of forming a transmissive surface relief diffractive optical element providing an anti-reflection functionality in a particular wavelength range comprises depositing a plurality of layers onto a wafer, wherein the depositing forms three or more anti-reflectance structures for the particular wavelength range, each anti-reflectance structure comprising at least one pair of layers, wherein a first anti-reflectance structure, of the three or more anti-reflectance structures, is formed on the wafer and beneath a second anti-reflectance structure of the three or more anti-reflectance structures, and wherein the second anti-reflectance structure is formed beneath a third anti-reflectance structure of the three or more anti-reflectance structures. At least one layer is formed between two of the three or more anti-reflectance structures. The first anti-reflectance structure comprises a first top layer and the second anti-reflectance structure comprises a second top layer, each of the first top layer and the second top layer being an etch stop layer to enable etching to form a phase delay. Each of the first anti-reflectance structure including the first top layer, the second anti-reflectance structure including the second top layer, and the third anti-reflectance structure comprises alternating layers of two materials. The method comprises etching a subset of layers of the plurality of layers to form a three or more-level relief profile. The three-level relief profile comprises a first relief depth between a first surface of the first anti-reflectance structure and a second surface of the second anti-reflectance structure and a second relief depth between the first surface and a third surface of the third anti-reflectance structure, said first relief depth and said second relief depth being configured to form a surface relief diffractive optical element associated with a first phase delay and a second phase delay, respectively, for the particular wavelength range, the surface relief diffractive optical element being configured to provide an anti-reflectance functionality in the particular wavelength range of incident light and having etched regions and un-etched regions, and thereby forming the three-level relief profile having anti-reflectance structures built into each etched stack of the surface relief diffractive optical element and built into the un-etched stack without requiring additional anti-reflectance coatings or structures on the top surface of the three-level relief profile.

The method may further comprise: dividing the wafer into a plurality of surface relief diffractive optical elements.

The plurality of layers may include at least one of: a silicon layer, a silicon dioxide layer, a tantalum pentoxide layer, or a silicon nitride layer.

The method may further comprise: forming another surface relief diffractive optical element including another three or more stacked anti-reflectance structures on another side of the wafer with the particular phase delay for the particular wavelength range.

A diffractive optical element (DOE) may be manufactured using a photolithographic procedure and/or an etching procedure. For example, to approximate a continuous surface relief profile, a two-level surface relief profile may be selected for the DOE, and a surface of the DOE may be etched or patterned to form the two-level surface relief profile. The two-level surface relief profile may be used to create a phase delay for a beam passing through the DOE. For a single order binary DOE, such as a diffractive lens, a diffractive efficiency of approximately <NUM>% may be achieved using the two-level surface relief profile. However, this diffractive efficiency may be less than a threshold for utilization of a DOE in an optical system, such as an optical communications system, a gesture recognition system, a motion detection system, a depth sensing system, and/or the like. Moreover, a spot array pattern or diffraction pattern created by the DOE may be symmetrical, and an asymmetric diffraction pattern may be desired for a particular optical system.

Some implementations, described herein, may provide a multi-level DOE with a threshold diffractive efficiency. For example, some implementations, described herein, provide a multi-level DOE (e.g., greater than two levels) to provide a particular phase delay at a particular wavelength of incident light between portions of the DOE and an anti-reflectance at the particular wavelength of incident light. Moreover, some implementations, described herein, may provide a DOE associated with an asymmetric spot array pattern or diffraction pattern.

In some implementations, described herein, a DOE may be associated with a relief depth to fabricate a selected surface relief profile of less than a threshold, thereby resulting in a reduced aspect ratio, a reduced etch time, and/or a reduced fabrication cost for the DOE (relative to other techniques for manufacturing a DOE). Furthermore, layers of the DOE may provide an integrated etch stop for the DOE. Some implementations, described herein, may provide a method for manufacturing a DOE. For example, a DOE may be manufactured using a thin film deposition procedure, an etching procedure, and/or the like, which may provide improved layer thickness accuracy and improved manufacturability relative to other techniques for manufacturing a DOE.

<FIG> is a diagram of an overview of an example implementation <NUM> described herein. <FIG> shows an example of spot array generation using a surface relief DOE grating and a converging lens as a spot array illuminator (sometimes termed a spot array generator or dot array generator).

As shown in <FIG>, an incident plane wave <NUM>, with a wavelength of λ<NUM>, is directed toward a surface relief DOE grating <NUM>. In some implementations, surface relief DOE grating <NUM> may be a DOE with a multi-level surface relief profile, such as a four-level DOE, an eight-level DOE, a <NUM>"-level DOE (where n > <NUM>), a k-level DOE (e.g., where k > <NUM>), and/or the like. In some implementations, surface relief DOE grating <NUM> may include, for example, alternating layers of silicon (Si) and silicon dioxide (SiO<NUM>), alternating layers of hydrogenated silicon (Si:H) and silicon dioxide, and/or the like.

In the implementations according to the claimed invention, layers of surface relief DOE grating <NUM> are configured to provide an anti-reflectance functionality at a particular wavelength of incident light. In the implementations according to the claimed invention, a layer of surface relief DOE grating <NUM> (e.g., a silicon dioxide layer) provides an etch stop functionality during manufacture of surface relief DOE grating <NUM>. In some implementations, incident plane wave <NUM> may have a wavelength in a range from approximately <NUM> nanometers (nm) to approximately <NUM>, approximately <NUM> to approximately <NUM>, approximately <NUM> to approximately <NUM>, approximately <NUM> to approximately <NUM>, approximately <NUM> to approximately <NUM>, approximately <NUM> to approximately <NUM>, approximately <NUM> to approximately <NUM>, and/or the like. In some implementations, incident plane wave <NUM> may have a wavelength in a range from approximately <NUM> to approximately <NUM>, approximately <NUM> to approximately <NUM>, approximately <NUM> to approximately <NUM>, approximately <NUM> to approximately <NUM>, and/or the like. Additional details regarding surface relief DOE grating <NUM> are described herein.

As further shown in <FIG>, surface relief DOE grating <NUM> diffracts incident plane wave <NUM>, and directs wavefront <NUM> (e.g., diffracted orders of incident plane wave <NUM>) toward a converging lens <NUM>. Converging lens <NUM> is separated by a focal distance <NUM> from a focal plane <NUM>. In some implementations, example implementation <NUM> may be used for a gesture recognition system, and focal plane <NUM> may be a target for gesture recognition. Additionally, or alternatively, focal plane <NUM> may be an object (e.g., for an object sensing system), a communications target (e.g., for an optical communication system), and/or the like.

As further shown in <FIG>, based on converging lens <NUM> altering an orientation of wavefront <NUM> to form wavefront <NUM>, wavefront <NUM> is directed toward focal plane <NUM> causing a multiple spot array pattern to be formed at focal plane <NUM>. In some implementations, the multiple spot array pattern may be asymmetric. In some implementations, surface relief DOE grating <NUM> may be used to create a two-dimensional spot array. In this way, surface relief DOE grating <NUM> may be used as a spot array illuminator to create a spot array at focal plane <NUM> from incident plane wave <NUM>, thereby enabling a gesture recognition system, a motion sensing system, an optical communications system, and/or the like.

<FIG> and <FIG> are diagrams relating to an example implementation described herein. As shown in <FIG>, and by diagram <NUM>, a continuous relief profile can be quantized into a set of discrete levels to enable a photolithographic and/or an etching procedure to be used for manufacturing a DOE.

As further shown in <FIG>, and by reference number <NUM>, a continuous relief profile may be associated with a diffractive efficiency of approximately <NUM>% (for a single order configuration) and may provide a continuously increasing phase delay of 2π from a second pitch position, dx, relative to a first pitch position, <NUM>. As shown by reference number <NUM>, the continuous relief profile may be approximated by a two-level relief profile (sometimes termed a binary relief profile). The two-level relief profile may be associated with a diffractive efficiency of approximately <NUM>% (for a single order configuration) and may provide a π phase delay at a second region of a DOE, from pitch position <NUM>. 5dx to pitch position dx, relative to a first region of the DOE, from pitch position <NUM> to pitch position <NUM>.

As further shown in <FIG>, and by reference number <NUM>, the continuous relief profile may be approximated by a <NUM>-level relief profile. The <NUM>-level relief profile may be associated with a diffractive efficiency of approximately <NUM>% (for a single order configuration), and may provide a π/<NUM> phase delay at a second region of the DOE, from pitch position <NUM>. 25dx to pitch position <NUM>. 5dx, relative to a first region of the DOE, from <NUM> to <NUM>. 25dx; a π phase delay at a third region of the DOE, from <NUM>. 5dx to <NUM>. 75dx, relative to the first region of the DOE; and a 3π/<NUM> phase delay at a fourth region of the DOE, from <NUM>. 75dx to dx, relative to the first region of the DOE.

As further shown in <FIG>, and by reference number <NUM>, the continuous relief profile may be approximated by an <NUM>-level relief profile. The <NUM>-level relief profile may be associated with a diffractive efficiency of approximately <NUM>% (for a single order configuration), and may provide phase delays in increments of π/<NUM> at regions of the DOE (e.g., π/<NUM> at a second region from <NUM>. 125dx to <NUM>. 25dx; π/<NUM> at a third region, from <NUM>. 25dx to <NUM>. 375dx; 3π/<NUM> at a fourth region, from <NUM>. 375dx to <NUM>. 5dx; etc. relative to a first region of the DOE, from <NUM> to <NUM>. In some implementations, another configuration with another diffraction efficiency may be used. For example, a configuration using <NUM> orders, <NUM> orders, <NUM> orders, <NUM> orders, and/or the like may be used to increase a diffraction efficiency relative to the single order configuration. In this case, such as for +/- <NUM> orders, a diffraction efficiency of approximately <NUM>% to <NUM>% may be achieved for a two-level relief profile. Based on using a multi-level DOE with greater than <NUM> levels, diffractive efficiency may be improved to greater than a threshold (for a single order configuration and/or the like), such as greater than <NUM>%, greater than <NUM>%, greater than <NUM>%, greater than <NUM>%, greater than <NUM>%, greater than <NUM>%, greater than <NUM>%, greater than <NUM>%, and/or the like.

Although some implementations, described herein, are described in terms of a <NUM>n level DOE (where n > <NUM>) (e.g., a <NUM>-level DOE, an <NUM>-level DOE, etc.), other types of k-level DOEs are possible (where k > <NUM>), such as a <NUM>-level DOE, a <NUM>-level DOE, a <NUM>-level DOE, etc. Additionally, or alternatively, although some implementations, described herein, are described in terms of a regular distribution of levels (e.g., for a <NUM>-level DOE, phase delays of kπ/<NUM> for k = [<NUM>, <NUM>]), other non-regular distributions of levels are possible (e.g., for a <NUM>-level DOE, phase delays of <NUM>, π/<NUM>, π/<NUM>, 3π/<NUM>, and 7π/<NUM>). Additionally, or alternatively, although some implementations described herein are described in terms of DOEs having regions with a regular distribution of the pitch (e.g. for a <NUM>-level DOE, the pitch (1dx) is split equally with each region spanning <NUM>. 25dx), other non-regular distributions of pitch are possible (e.g. for a <NUM>-level DOE, a first phase delay region may span <NUM>. 1dx, while second, third and fourth phase delay regions may span <NUM>. 2dx, <NUM>. 4dx and <NUM>. 3dx respectively). In this way, a multi-level DOE may enable additional quantities of phase delays and/or values of phase delays.

As shown in <FIG>, a DOE <NUM> may include a substrate <NUM>. In some implementations, substrate <NUM> may be a glass substrate, a fused silica substrate, and/or the like. For example, substrate <NUM> may be a fused silica substrate with a thickness of approximately <NUM> micrometers, and with a refractive index, nsub, of <NUM>. For example, as shown in <FIG>, a set of alternating silicon and silicon dioxide layers may be disposed onto a top surface of substrate <NUM> and patterned to form a relief profile, as described herein, and anti-reflectance coating <NUM> may cover the bottom surface of substrate <NUM>. In some implementations, anti-reflectance coating <NUM> may be absent or may be substituted with another anti-reflectance structure such as the anti-reflectance structure formed on the top surface. In some implementations, an anti-reflectance structure may include a thin film, a thin film structure, an anti-reflectance coating, a deposited thin layer, a deposited thin film layer, and/or the like.

As further shown in <FIG>, the set of alternating silicon and silicon dioxide layers may include a set of silicon layers <NUM> and a set of silicon dioxide layers <NUM>. For example, silicon layer <NUM>-<NUM> may be disposed on substrate <NUM>, and silicon dioxide layer <NUM>-<NUM> may be disposed on silicon layer <NUM>-<NUM>. Silicon layer <NUM>-<NUM> and silicon dioxide layer <NUM>-<NUM> may form a pair of matched layers <NUM>-<NUM>, which provide a first anti-reflectance structure. Similarly, silicon dioxide layer <NUM>-<NUM> may be disposed on silicon layer <NUM>-<NUM>, and may form a pair of matched layers <NUM>-<NUM>, which provide a second anti-reflectance structure; silicon dioxide layer <NUM>-<NUM> may be disposed on silicon layer <NUM>-<NUM>, and may form a pair of matched layers <NUM>-<NUM>, which provide a third anti-reflectance structure; silicon layer <NUM>-<NUM> may be disposed on silicon dioxide layer <NUM>-<NUM>, and may form a pair of matched layers <NUM>-<NUM>, which provide a fourth anti-reflectance structure. As shown, silicon layer <NUM>-<NUM> may be disposed between matched layers <NUM>-<NUM> and matched layers <NUM>-<NUM>. Silicon layer <NUM>-<NUM> may be configured to provide a particular functionality for DOE <NUM>, and may be configured independent of the anti-reflectance structures, thereby improving flexibility in DOE design.

In some implementations, DOE <NUM> may be exposed to an air or gaseous interface. For example, a first surface of DOE <NUM> (e.g., surfaces of matched layers <NUM>) and a second surface of DOE <NUM> (e.g., a surface of anti-reflectance coating <NUM>) may be exposed to an air interface with a refractive index, nair, of <NUM>. A relief depth, h, may be calculated based on the equation: <MAT> where λ<NUM> is a nominal illuminating wavelength for a DOE, such as DOE <NUM> and K represents a quantity of levels. To reduce a relief depth, a material with a relatively large refractive index may be selected, such as silicon dioxide, which may result, in some implementations, in a relief depth, h, of an etch (e.g., etch <NUM>) of approximately <NUM> micrometers (µm). In some implementations, the relief depth may be a relief depth of between <NUM> and <NUM>, between <NUM> and <NUM>, between <NUM> and <NUM>, and/or the like. In some implementations, layers may be index matched to increase transmittance of DOE <NUM>. For example, silicon layers <NUM> and silicon dioxide layers <NUM> may be selected based on respective refractive indices of <NUM> and <NUM> being within a threshold amount of between <NUM> and <NUM>.

In some implementations, other materials may be selected for a thin film coating material, such as tantalum pentoxide (Ta<NUM>O<NUM>) and silicon nitride (Si<NUM>N<NUM>), which may have a refractive index of approximately <NUM>. Based on using silicon thin film for layers of DOE <NUM>, a relief depth for a <NUM>-level relief profile is reduced relative to other material selections. For example, for a 3π/<NUM> phase delay in a <NUM>-level relief profile at a nominal illuminating wavelength of <NUM>, silicon dioxide may be associated with a relief depth of approximately <NUM>, tantalum pentoxide and silicon nitride may be associated with a relief depth of approximately <NUM>, and silicon may be associated with a relief depth of approximately <NUM>. Other materials with similar refractive indices, such as a refractive index range of between <NUM> and <NUM>, a refractive index of <NUM>, and/or the like may be used. Similarly, for an <NUM>-level relief profile, silicon dioxide may be associated with a relief depth of approximately <NUM>, tantalum pentoxide and silicon nitride may be associated with a relief depth of approximately <NUM>, and silicon may be associated with a relief depth of approximately <NUM>. In some implementations, hydrogenation may be used to improve optical performance of a coating material. For example, hydrogenated silicon may be used for silicon layers <NUM>. In this way, hydrogenation may be used to reduce an absorption edge of silicon to enable use for a wavelength of between <NUM> and <NUM> and to reduce the desired relief depth of the DOE to improve manufacturing (e.g. increase quality and/or yield). In some implementations, Argon may be used in a deposition chamber to form a low absorption coating (e.g., less than a threshold amount of absorption). In some implementations, a silicon carbide may be used with a refractive index of approximately <NUM> for use with visible light wavelengths and/or the like, such as for a DOE lens for a camera.

As indicated above, <FIG> and <FIG> are provided merely as examples. Other examples are possible and may differ from what was described with regard to <FIG> and <FIG>.

<FIG> and <FIG> are diagrams of example implementations of DOEs <NUM> and <NUM>'. As shown in <FIG>, DOE <NUM> includes a substrate <NUM>, an anti-reflectance coating <NUM>, a set of silicon layers <NUM>-<NUM> through <NUM>-<NUM>, and a set of silicon dioxide layers <NUM>-<NUM> through <NUM>-<NUM>.

As further shown in <FIG>, and by reference number <NUM>, silicon dioxide layers <NUM>-<NUM> and <NUM>-<NUM> may be etch stop layers to enable etching to more accurately form a 2π(K-<NUM>)/K phase delay for a quantity of levels K. For example, an etching procedure may be performed such that un-etched stack <NUM> remains un-etched and etched stacks <NUM>-<NUM> and <NUM>-<NUM> are etched to relief depths <NUM>-<NUM> and <NUM>-<NUM>, respectively. Relief depth <NUM>-<NUM> may provide a 2π(K-<NUM>)/K phase delay between etched stack <NUM>-<NUM> and un-etched stack <NUM>. Relief depth <NUM>-<NUM> may provide a phase delay between <NUM> and 2π/K between etched stack <NUM>-<NUM> and un-etched stack <NUM>. In some implementations, multiple etching procedures using multiple tools may be performed to etch DOE <NUM>. For example, DOE <NUM> may be manufactured using multiple silicon dioxide etch tools, multiple silicon etch tools, multiple etching techniques (e.g., a deep reactive ion (DRIE) etch tool technique, a reactive-ion etching (RIE) tool technique, a sputter etching tool technique, and/or the like), and/or the like.

In the implementations according to the claimed invention, layers of DOE 300may form a set of anti-reflectance structures. For example, layers <NUM>-<NUM> and <NUM>-<NUM> form a first anti-reflectance structure for a particular wavelength range (e.g. the wavelength of incident light), layers <NUM>-<NUM> and <NUM>-<NUM> may form a second anti-reflectance structure for the particular wavelength range, and layers <NUM>-<NUM> and <NUM>-<NUM> form a third anti-reflectance structure for the particular wavelength range, thereby forming a three-level relief profile having anti-reflectance structures built into each etched stack of the DOE <NUM> and built into the un-etched stack <NUM>. Accordingly, the DOE <NUM> does not require additional anti-reflectance coatings or structures on the top surface.

In some implementations, described herein, the second anti-reflectance structure may be formed on the first anti-reflectance structure, and an adjacent surface of the first anti-reflectance structure (e.g., a top surface of layer <NUM>-<NUM>) may be an etch stop for etching to form etched stack <NUM>-<NUM>. Similarly, the third anti-reflectance structure may be formed on the second anti-reflectance structure, and an adjacent surface the second anti-reflectance structure (e.g., a top surface of layer <NUM>-<NUM>) may be an etch stop when forming etched stack <NUM>-<NUM>.

In some implementations, at least one layer, such as layer <NUM>-<NUM> and/or the like, may be between a set of anti-reflectance structures (e.g., between the first anti-reflectance structure and the second anti-reflectance structure, between the second anti-reflectance structure and the third anti-reflectance structure, and/or the like). In this way, an alteration to the relief depths <NUM>-<NUM> and/or <NUM>-<NUM> may be performed to alter a characteristic of DOE <NUM> without altering transmission characteristics of DOE <NUM>. In some implementations, the first anti-reflectance structure, the second anti-reflectance structure, and/or the third anti-reflectance structure may not be separated by a layer.

In some implementations, each layer may be associated with a particular thickness. For example, the particular thickness may correspond to a wavelength of light for which the particular phase delay is caused and for which DOE <NUM> is transmissive (e.g., greater than a threshold percentage of transmissivity, such as greater than <NUM>%, greater than <NUM>%, greater than <NUM>%, greater than <NUM>%, greater than <NUM>%, and/or the like). In some implementations, DOE <NUM> may be associated with a particular pitch <NUM> (sometimes termed a period), dx, which may correspond to a wavelength of light for which the particular phase delay is caused and for which DOE <NUM> is transmissive. In some implementations, a capping layer may be formed onto the seventh layer (e.g., another silicon dioxide layer), which may improve robustness during dicing of a wafer that includes DOE <NUM>.

In some implementations, thicknesses of layers of DOE <NUM>, a size of pitch <NUM>, an index of refraction of the anti-reflectance structures and/or the layers thereof, and/or the like may be selected to cause a particular phase delay (e.g., the 2π(K-<NUM>)/K phase delay) at a particular wavelength for which the anti-reflectance structures provide an anti-reflectance functionality. For example, the first anti-reflectance structure may be associated with a first index of refraction of a particular amount, the second anti-reflectance structure may be associated with a second index of refraction of <NUM>, the third anti-reflectance structure may be associated with a third index of refraction of <NUM> for a <NUM> three level thin film DOE. In some implementations, the particular wavelength may include a wavelength range of between approximately <NUM> and <NUM>, <NUM> to <NUM>, and/or the like. As shown by reference number <NUM>, based on incident light being directed at a first side of substrate <NUM>, a set of intensity orders (e.g., intensity orders -<NUM>, -<NUM>, <NUM>, <NUM>, <NUM>, etc.) are provided by DOE <NUM>. In some implementations, DOE <NUM> may provide greater than <NUM> intensity orders, greater than <NUM> intensity orders, greater than <NUM> intensity orders, greater than <NUM> intensity orders, greater than <NUM> intensity orders, greater than <NUM> intensity orders, and/or the like.

As shown in <FIG>, DOE <NUM>' includes a first diffractive (transmissive) optical element formed on a first side of substrate <NUM> and a second diffractive (transmissive) optical element formed on a second side of substrate <NUM>. Each diffractive optical element includes a set of silicon layers <NUM>-<NUM> through <NUM>-<NUM> and a set of silicon dioxide layers <NUM>-<NUM> through <NUM>-<NUM>. As shown by reference numbers <NUM>-<NUM> and <NUM>-<NUM>, based on incident light being directed toward DOE <NUM>', the second diffractive optical element causes a first set of intensity orders to be directed through substrate <NUM> to the first diffractive optical element, which causes a second set of intensity orders to be provided from DOE <NUM>'. In this way, substrate <NUM> maintains an alignment of the first diffractive optical element and the second diffractive optical element, thereby reducing a difficulty in maintaining alignment relative to another technique, such as free space optics or using a pick-and-place machine to independently align two separate DOEs. Moreover, based on disposing DOEs onto both sides of a substrate, an amount of mechanical stress may be balanced for the DOEs, thereby improving durability, increasing flatness of the DOEs across operating temperature ranges, reducing warping or bowing of the DOEs, and/or the like.

Although some implementations, described herein, are described in terms of a particular quantity of layers, such as <NUM> layers, other quantities of layers are possible, such as <NUM> layers (e.g., <NUM> alternating silicon/silicon dioxide layers), <NUM> layers, <NUM> layers, <NUM> layers, and/or the like.

<FIG> is a flow chart of an example process <NUM> for manufacturing a DOE. Examples of some manufacturing steps of process <NUM> are shown in more detail with regard to <FIG> and <FIG>.

As shown in <FIG>, process <NUM> may include depositing a set of layers onto a substrate (block <NUM>). For example, during manufacture, a deposition procedure may be used to deposit the set of layers onto the substrate. In some implementations, one or more of the set of layers may be a thin film deposited using a thin film deposition procedure, such as a sputter deposition procedure using a pulsed magnetron sputtering system. In some implementations, the set of layers may a set of silicon layers, a set of silicon dioxide layers, and/or the like. In some implementations, the set of layers may be deposited onto the substrate with a threshold tolerance. For example, the set of layers may be deposited within <NUM>% of a specified thickness, within <NUM>% of a specified thickness, within <NUM>% of a specified thickness, within <NUM>% of a specified thickness, within <NUM>% of a specified thickness, within <NUM>% of a specified thickness, and/or the like. In this way, layers for forming a first anti-reflectance structure for a particular wavelength, a second anti-reflectance structure for the particular wavelength,. , and an nth anti-reflectance structure for the particular wavelength may be deposited. In some implementations, the high accuracy in thickness when depositing thin film coatings may improve accuracy in the relief depth(s) of a DOE.

In some implementations, the substrate may be a glass substrate, a fused silica substrate, a substrate that is transparent for a particular wavelength of incident light, and/or the like. In some implementations, the set of layers may include multiple sets of silicon and silicon dioxide layers. For example, for a <NUM>-level DOE, a first set of silicon and silicon dioxide layers may be deposited onto the substrate, a second set of silicon and silicon dioxide layers may be deposited onto the first set, a third set of silicon and silicon dioxide layers may be deposited onto the second set, and a fourth set of silicon and silicon dioxide layers may be deposited onto the third set. In this case, another silicon layer may be deposited onto the fourth set, and a set of three mask layers may be deposited onto the other silicon layer, as described in more detail herein, to enable etching and mask removal to form the <NUM>-level DOE. In some implementations, other quantities of DOE levels may be possible, such as a <NUM>-level DOE, a <NUM>-level DOE, a <NUM>-level DOE, a <NUM>-level DOE, and/or the like.

In some implementations, an anti-reflectance coating layer may be formed using the set of layers. For example, the anti-reflectance coating may be a DOE anti-reflectance coating to stress balance the substrate and the DOEs, thereby reducing warping of the substrate over an operating temperature range. Additionally, or alternatively, an anti-reflectance layer may be deposited on a back side of the substrate (and layers to form a DOE may be deposited on a front side of the substrate). In some implementations, the set of layers may be deposited onto multiple sides of the substrate. For example, the set of layers may be deposited to form anti-reflectance structures on a first side of the substrate and on a second side of the substrate, which may result in the substrate supporting multiple DOEs. In some implementations, another set of materials may be used for at least one of the layers, such as a hydrogenated silicon based material, a tantalum pentoxide based material, a silicon nitride based material, and/or the like.

As further shown in <FIG>, process <NUM> may include depositing a set of masks onto a surface of the set of layers (block <NUM>). For example, during manufacture, a deposition procedure may be used to deposit the set of masks onto surfaces of the set of layers. In some implementations, multiple masks may be deposited. For example, to form a <NUM>-level DOE, a first mask may be deposited onto a portion of a top layer of the set of layers, a second mask may be deposited onto a portion of the top layer and onto the first mask, a third mask may be deposited onto a portion of the top layer and onto the second mask. In this case, a patterning of the masks (e.g., a portion of the top layer that is covered by each of the masks, may be selected to enable forming of the <NUM>-level DOE during etching and mask removal.

In some implementations, a material for the mask may be selected such that the mask is associated with a threshold selectivity or a threshold resistivity to silicon etching and/or silicon dioxide etching. In some implementations, the masks may be formed using multiple materials. For example, a first mask may be an aluminum mask and a second mask may be a photoresist mask. In this way, the masks may be configured such that removal of the first mask does not result in removal of the second mask, thereby enabling formation of a DOE. In this way, based on depositing multiple masks before etching, an accuracy of manufacture is improved, a manufacturability is improved, and an alignment tolerance is improved relative to other techniques, such as depositing mask layers onto etched layers of a DOE after one or more etching steps.

As further shown in <FIG>, process <NUM> may include etching the set of layers (block <NUM>), and removing a mask of the set of masks (block <NUM>). For example, during manufacture, an etching procedure and a mask removal procedure may be performed to form a DOE. In this case, the etching procedure may include multiple etching steps and the mask removal procedure may include multiple mask removal steps. For example, for a <NUM>-level DOE, a first etching step may be performed, a first mask removal step may be performed, a second etching step may be performed, a second mask removal step may be performed, a third etching step may be performed, and a third mask removal step may be performed, as described in more detail herein. In some implementations, multiple different types of mask removal steps may be performed for multiple different material masks. For example, an aluminum mask removal step may be performed to remove a first mask of aluminum and a photoresist mask removal step may be performed to remove a second mask of photoresist. In some implementations, the etch step may be performed to remove a subset of layers of the set of layers. For example, based on silicon dioxide layers being configured as etch stops, a single etch step may include a silicon dioxide etch to remove a first silicon dioxide layer followed by a silicon etch to remove a first silicon layer, such that a second silicon dioxide layer disposed below the first silicon layer etch stops the silicon etch to maintain the second silicon dioxide layer and/or a second silicon layer disposed below the second silicon dioxide layer. In this way, a set of anti-reflectance structures may be formed for the DOE.

As further shown in <FIG>, process <NUM> may include performing wafer finishing (block <NUM>). For example, the DOE may be tested, the DOE may be diced into multiple discrete DOEs (e.g., a wafer onto which multiple DOEs were patterned may be diced into the multiple discrete DOEs), and the DOE may be packaged for inclusion in an optical device. In some implementations, the wafer may be diced to form multiple <NUM> millimeter (mm) x <NUM> wafers.

<FIG> are diagrams of an example implementation <NUM> relating to example process <NUM> shown in <FIG>. As shown, <FIG> illustrate examples of etching a set of layers and removing a set of masks from the set of layers as described, above, with regard to blocks <NUM> and <NUM>.

As shown in <FIG>, and from reference line <NUM> to reference line <NUM>, example implementation <NUM> may include a set of layers <NUM> to <NUM>. The set of layers <NUM> to <NUM> may be planar and unetched. For example, example implementation <NUM> may include a substrate layer <NUM>. A set of alternating silicon layers <NUM>, <NUM>, <NUM>, and <NUM> and silicon dioxide layers <NUM>, <NUM>, and <NUM> are deposited on one surface of substrate layer <NUM>. An optional anti-reflectance coating or structure <NUM> is provided on an opposite surface of the substrate layer <NUM>.

As further shown with regard to <FIG>, mask layers <NUM> and <NUM> may be deposited and patterned onto portions of silicon layer <NUM>, such that mask layers <NUM> and <NUM> cover portions of silicon layer <NUM>. The materials used for each mask may be dissimilar so that the removal of mask <NUM> does not affect the pattern of mask <NUM>. Mask layer <NUM> is deposited to cover silicon layer <NUM> between reference lines <NUM> and <NUM> to protect the set of layers <NUM>-<NUM> during etching thereby enabling etching to form a third anti-reflectance structure between reference lines <NUM> and <NUM>. Mask layer <NUM> is deposited to cover silicon layer <NUM> between reference line <NUM> and reference line <NUM> to protect the set of layers <NUM> to <NUM> during etching thereby enabling etching to form a second anti-reflectance structure between reference lines <NUM> and <NUM>. Mask layers <NUM> and <NUM> do not cover silicon layer <NUM> between reference lines <NUM> and <NUM> leaving the set of layers <NUM> to <NUM> unprotected during etching, thereby enabling etching to form a first anti-reflectance structure between reference lines <NUM> and <NUM>, as described in more detail herein.

As shown in <FIG>, a first etching step of an etching procedure may be performed to remove a portion of silicon layer <NUM>, silicon dioxide layer <NUM>, and silicon layer <NUM> that is not covered by mask layer <NUM> (e.g., between reference lines <NUM> and <NUM>). In this case, silicon dioxide layer <NUM> may perform an etch stop functionality for the first etching step.

As shown in <FIG>, a first mask removal step of a mask removal procedure may be performed to remove mask layer <NUM>, thereby exposing a portion of silicon layer <NUM> (e.g., between reference lines <NUM> and <NUM>) and a portion of mask layer <NUM> (e.g., between reference lines <NUM> and <NUM>).

As shown in <FIG>, a second etching step of the etching procedure may be performed to remove silicon dioxide layer <NUM> and silicon layer <NUM> between reference lines <NUM> and <NUM>, and to remove silicon layer <NUM>, silicon dioxide layer <NUM>, and silicon layer <NUM> between reference lines <NUM> and <NUM>. In this case, silicon dioxide layer <NUM> may perform an etch stop functionality for the second etch step between reference lines <NUM> and <NUM>, and silicon dioxide layer <NUM> may perform an etch stop functionality for the second etch step between reference lines <NUM> and <NUM>.

As shown in <FIG>, a second mask removal step of the mask removal procedure may be performed to remove mask layer <NUM>, thereby exposing silicon layer <NUM> between reference lines <NUM> and <NUM>. In this way, a <NUM>-level relief profile may be formed with a first anti-reflectance structure for a particular wavelength between reference lines <NUM> and <NUM>, a second anti-reflectance structure for the particular wavelength between reference lines <NUM> and <NUM>, and a third anti-reflectance structure and another silicon layer (e.g., silicon layer <NUM>) between reference lines <NUM> and <NUM>. In this case, a phase delay between the first anti-reflectance structure between reference lines <NUM> and <NUM> and the third anti-reflectance structure between reference lines <NUM> and <NUM> may be a π phase delay.

As indicated above, <FIG> are provided merely as an example.

As shown in <FIG>, example implementation <NUM> from reference line <NUM> to reference line <NUM> may include a set of layers <NUM> to <NUM>. The set of layers <NUM> to <NUM> may be planar and unetched. For example, example implementation <NUM> may include a substrate layer <NUM>. An anti-reflectance layer <NUM> may be deposited onto a first side of substrate layer <NUM> and a set of alternating silicon layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> and silicon dioxide layers <NUM>, <NUM>, <NUM>, and <NUM> may be deposited onto a second side of substrate layer <NUM>.

As further shown in <FIG>, mask layers <NUM>, <NUM>, and <NUM> are deposited and patterned to cover portions of silicon layer <NUM> to enabling an etching procedure and a mask removal procedure to be performed to form a set of four anti-reflectance structures between reference lines <NUM> and <NUM>. The materials used for each mask <NUM>, <NUM>, <NUM> may be dissimilar so that the removal of one does not affect the pattern of the remaining mask(s).

As shown in <FIG>, a first etch step of an etching procedure may be performed to remove a portion of silicon layer <NUM>, silicon dioxide layer <NUM>, and silicon layer <NUM> not covered by mask layer <NUM> (e.g., between reference lines <NUM> and <NUM>). In this case, silicon dioxide layer <NUM> may perform an etch stop functionality for the first etching step.

As shown in <FIG>, a first mask removal step of a mask removal procedure may performed to remove mask layer <NUM>, thereby exposing a portion of silicon layer <NUM> between reference lines <NUM> and <NUM> and a portion of mask layer <NUM> between reference lines <NUM> and <NUM>.

As shown in <FIG>, a second etch step of the etching procedure may be performed to remove silicon dioxide layer <NUM> and silicon layer <NUM> between reference lines <NUM> and <NUM>, and to remove silicon layer <NUM>, silicon dioxide layer <NUM>, and silicon layer <NUM> between reference lines <NUM> and <NUM>. In this case, silicon dioxide layer <NUM> may perform an etch stop functionality for the second etch step between reference lines <NUM> and <NUM>, and silicon dioxide layer <NUM> may perform an etch stop functionality for the second etch step between reference lines <NUM> and <NUM>.

As shown in <FIG>, a second mask removal step of the mask removal procedure may be performed to remove mask layer <NUM>, thereby exposing silicon layer <NUM> between reference lines <NUM> and <NUM> and a portion of mask layer <NUM> between reference lines <NUM> and <NUM>.

As shown in <FIG>, a third etch step of the etching procedure may be performed to remove silicon dioxide layer <NUM> and silicon layer <NUM> between reference lines <NUM> and <NUM>; silicon dioxide layer <NUM> and silicon layer <NUM> between reference lines <NUM> and <NUM>; and silicon layer <NUM>, silicon dioxide layer <NUM>, and silicon layer <NUM> between reference lines <NUM> and <NUM>. In this case, silicon dioxide layer <NUM> may perform an etch stop functionality for the third etch step between reference lines <NUM> and <NUM>, silicon dioxide layer <NUM> may perform an etch stop functionality for the third etch step between reference lines <NUM> and <NUM>, and silicon dioxide layer <NUM> may perform an etch stop functionality for the third etch step between reference lines <NUM> and <NUM>.

As shown in <FIG>, a third mask removal step of the mask removal procedure may be performed to remove mask layer <NUM>, thereby exposing silicon layer <NUM> between reference lines <NUM> and <NUM>.

In this way, a <NUM>-level relief profile may be formed with a first anti-reflectance structure for a particular wavelength between reference lines <NUM> and <NUM>, a second anti-reflectance structure for the particular wavelength between reference lines <NUM> and <NUM>, a third anti-reflectance structure for the particular wavelength between reference lines <NUM> and <NUM>, and a fourth anti-reflectance structure and another silicon layer (e.g., silicon layer <NUM>) between reference lines <NUM> and <NUM>. In this case, a phase delay between the first anti-reflectance structure between reference lines <NUM> and <NUM> and the fourth anti-reflectance structure between reference lines <NUM> and <NUM> may be a π phase delay.

In this way, a DOE with a thin film stack including alternating silicon layers (e.g., hydrogenated silicon layers) and silicon dioxide layers etched into a multi-level (e.g., three or more level) relief profile is configured and manufactured. Moreover, layers of the DOE may be designed to provide anti-reflectance properties, integrated etch stop properties, and/or the like. Furthermore, design may be performed using thin film process deposition, which may control zero order power. Furthermore, based on using thin film deposition and etching, a quantity of manufacture steps to manufacture the DOE may be reduced, thereby reducing time and cost relative to other techniques for manufacturing a DOE.

In the example embodiments illustrated in, for example, <FIG>, <FIG>, and/or the like, the relief depths and anti-reflection structures have been illustrated as a periodic or repeating pattern and with a constant cross-section, such as found in a diffraction grating. Other, non-periodic relief depths and anti-reflection structures with irregular or variable cross-sections are equally contemplated, such as, but not limited to, DOEs for pattern generation, depth mapping dot projection, and structured light.

Some implementations are described herein in connection with thresholds. As used herein, satisfying a threshold may refer to a value being greater than the threshold, more than the threshold, higher than the threshold, greater than or equal to the threshold, less than the threshold, fewer than the threshold, lower than the threshold, less than or equal to the threshold, equal to the threshold, or the like.

Even though particular combinations of features are recited in the claims and/or disclosed in the specification, these combinations are not intended to limit the disclosure of possible implementations. Although each dependent claim listed below may directly depend on only one claim, the disclosure of possible implementations includes each dependent claim in combination with every other claim in the claim set.

Claim 1:
A transmissive surface relief diffractive optical element (<NUM>, <NUM>') configured to provide an anti-reflectance functionality in a particular wavelength range of incident light and having etched regions (<NUM>-<NUM>, <NUM>-<NUM>) and un-etched regions (<NUM>), comprising:
a substrate (<NUM>);
a first anti-reflectance structure (<NUM>-<NUM>, <NUM>-<NUM>) for the particular wavelength range formed on the substrate;
a second anti-reflectance structure (<NUM>-<NUM>, <NUM>-<NUM>) for the particular wavelength range formed on the first anti-reflectance structure;
a third anti-reflectance structure (<NUM>-<NUM>, <NUM>-<NUM>) for the particular wavelength range formed on the second anti-reflectance structure; and
at least one layer (<NUM>-<NUM>) disposed between the first anti-reflectance structure and the second anti-reflectance structure or between the second anti-reflectance structure and the third anti- reflectance structure,
wherein a first relief depth between a first surface of the first anti-reflectance structure and a second surface of the second anti-reflectance structure and a second relief depth between the first surface and a third surface of the third anti-reflectance structure (<NUM>-<NUM>) are configured to form the surface relief diffractive optical element associated with a first phase delay and a second phase delay, respectively, for the particular wavelength range;
wherein the first anti-reflectance structure comprises a first top layer (<NUM>-<NUM>) and the second anti-reflectance structure comprises a second top layer (<NUM>-<NUM>), each of the first top layer and the second top layer being an etch stop layer to enable etching to form a phase delay,
wherein each of the first anti-reflectance structure including the first top layer, the second anti-reflectance structure including the second top layer, and the third anti-reflectance structure comprises alternating layers of two materials, and
thereby forming a three-level relief profile having anti-reflectance structures built into each etched stack (<NUM>-<NUM>, <NUM>-<NUM>) of the surface relief diffractive optical element and built into the un-etched stack (<NUM>) without requiring additional anti-reflectance coatings . or structures on the top surface of the three-level relief profile.