Patent Description:
High electron mobility transistors (HEMTs) employ a heterojunction defined by semiconductor materials having different bandgap energy levels. A gate provides an applied electric field to the heterojunction, which causes a conductive channel to be formed between the source and drain of the HEMT. Another electrical field applied across the source and drain causes an electrical current to flow through the conductive channel. When the applied field of the gate is removed, the electrical current between the source and drain will cease flowing, even when the applied field between the source and drain is not removed. High voltage HEMTs are used in a variety of devices and applications, including power supplies, electric cars, solar cells, and large solid state transistors, to name a few.

The breakdown voltage of a high voltage device is proportional to the amount of parasitic electrical current that leaks away from the current flowing between the source and the drain. When a voltage larger than the breakdown voltage is applied, parasitic current will flow regardless of whether there is an applied field provided by the gate (i.e., when the device is in an off state). This parasitic current limits device performance, including the maximum operational voltage.

<CIT> describes a specific method for making an array of LEDs, comprising the steps of: providing a sapphire growth substrate having a receiving surface; providing a sacrificial layer on the receiving surface of the sapphire growth substrate; generating a GaN multilayer on the sacrificial layer via epitaxial growth; the GaN multilayer comprising at least one p-type GaN layer in electrical contact with at least one n-type GaN layer; the GaN multilayer having a contact surface; patterning the contact surface of the GaN multilayer with a mask, thereby generating exposed regions and one or more masked regions of the GaN multilayer; removing material from the exposed regions by etching the exposed regions, thereby exposing a portion of the sacrificial layer and generating one or more LED device structures; at least partially releasing the one or more LED device structures from the growth substrate by removing at least a portion of the sacrificial layer using directional etching, electrochemical etching or photoelectrochemical etching; and transferring at least a portion of the one or more LED device structures from the sapphire growth substrate to a device substrate via dry transfer contact printing, thereby making the array of LEDs.

In <CIT>, a method of forming a light emitting diode is provided. The method includes providing a growth substrate; sequentially forming a sacrificial layer and an epitaxial layer on the growing substrate; forming one or more epitaxial layer openings penetrating the epitaxial layer and exposing the sacrificial layer; forming a supporting layer on the epitaxial layer, the supporting layer having one or more supporting layer openings penetrating the supporting layer and joining the epitaxial layer openings; and selectively etching the sacrificial layer to separate the growth substrate from the epitaxial layer.

<CIT> describes means and methods for obtaining the separation of large area semiconductor epitaxial device layers from the substrates on which they are grown, the transfer of the grown epi layers to a new host substrate for mounted alignment with features of the new host, and reuse of the original substrate.

In the following figures, <FIG> show embodiments of the invention.

The further figures are not in accordance with the invention, however illustrate aspects which may aid understanding of the invention.

Specific details of methods for making semiconductor devices are described herein along with related devices and systems. The term "semiconductor device" generally refers to a solid-state device that includes semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. Furthermore, the term "semiconductor device" can refer to a finished device or to an assembly or other structure at various stages of processing before becoming a finished device. Depending upon the context in which it is used, the term "substrate" can refer to a wafer-level substrate or to a singulated, die-level substrate. A person having ordinary skill in the relevant art will recognize that suitable steps of the methods described herein can be performed at the wafer-level or at the die-level. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic material deposition, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques. Further, features can be formed in structures, for example, by forming a patterned mask (e.g., a photoresist mask or a hard mask) on one or more semiconductor materials and depositing materials or removing materials in combination with the patterned mask.

Many embodiments of the present technology are applicable to power transistors having high operating voltages (e.g., high electron mobility transistors (HEMTs)). A person having ordinary skill in the relevant art will recognize, however, that the present technology may apply to other types of semiconductor devices, including bipolar transistors or solid state transducer devices that emit light (e.g., light emitting diodes (LEDs), laser diodes, etc.). Also, while described herein in the context of compound semiconductor devices (e.g., III-nitride-based semiconductor devices), embodiments of the present technology are not so limited and can include other types of materials. For example, semiconductor devices can be manufactured in Silicon (Si).

For ease of reference, throughout this disclosure identical reference numbers are used to identify similar or analogous components or features, but the use of the same reference number does not imply that the parts should be construed to be identical. Indeed, in many examples described herein, the identically-numbered parts are distinct in structure and/or function. Furthermore, the same shading may be used to indicate materials in a cross section that can be compositionally similar, but the use of the same shading does not imply that the materials should be construed to be identical.

As discussed above in the background section, parasitic conduction can limit semiconductor device performance. Parasitic current can flow between active regions of the device as well as through the bulk material of the semiconductor device (e.g., the substrate region adjacent to or below the active regions). In a conventional compound semiconductor device, the bulk substrate usually includes a portion of the substrate used to form the device. This substrate, commonly referred to as a "handle" substrate, can provide a support surface for epitaxial growth. The handle substrate is typically not removed because removal requires additional processing steps that complicate manufacturing and increase manufacturing costs. Rather, the handle substrate is singulated along with the other semiconductor materials to form the semiconductor device.

Methods and devices in accordance with embodiments of the present technology, however, can provide several advantages over these and other manufacturing techniques. The method includes removing a portion of an intermediary material (e.g., a sacrificial material) located between a semiconductor structure and a handle substrate to provide mechanical and electrical isolation from the handle substrate. Only a portion of the intermediary material is removed to form a gap between the semiconductor structure and the handle substrate. The semiconductor structure and the handle substrate remain coupled together through intermediary material.

The intermediary material is removed via openings formed in the semiconductor structure (e.g., by removing the intermediary material away from the structure through the openings and/or dissolving the intermediary material adjacent the openings). The openings extend through an active region of the device to provide access to the intermediary material through the opening in the active region. In further embodiments, other openings can extend partially through the semiconductor structure to mechanically isolate active regions of the structure from one another.

<FIG> are cross-sectional side views of a semiconductor device assembly <NUM> in various stages of manufacture. <FIG> shows the semiconductor device assembly <NUM> after a semiconductor structure <NUM> has been formed on a support structure <NUM>. The semiconductor structure <NUM> can have a plurality of dies or other structures that include integrated circuitry or other types of semiconductor devices. As such, the semiconductor structure <NUM> can include a single semiconductor material, a stack of different semiconductor materials, as well as other suitable materials. Although omitted for purposes of clarity, a person having ordinary skill in the art will appreciate that the semiconductor structure <NUM> can include a variety of materials. For example, in addition to materials that are semiconductive, the semiconductor structure <NUM> can include conductive materials (e.g., metallic materials) and insulative materials (e.g., dielectric materials). Also, the semiconductor structure <NUM> can include a variety of features formed throughout the structure. For example, the semiconductor structure <NUM> can include a through-substrate interconnect (not shown) that extends through the semiconductor structure <NUM>. Such a through-substrate interconnect can electrically connect opposite sides of a finished semiconductor device, for example.

The support structure <NUM> includes a handle substrate <NUM> and an intermediary material <NUM> between the handle substrate <NUM> and the semiconductor structure <NUM>. The handle substrate <NUM> can mechanically support the semiconductor structure <NUM> during manufacturing. The handle substrate <NUM> can also facilitate formation of one or more materials, features, or other aspects of the semiconductor structure <NUM>. For example, the handle substrate <NUM> can facilitate the growth of epitaxial semiconductor materials on the handle substrate <NUM>. In some embodiments, the handle substrate <NUM> can include ceramic, glass, poly-Aluminum Nitride (p-AlN), or other suitable materials. P-AlN-based handle substrates, for example, can have a coefficient of thermal expansion (CTE) that is similar to the CTE of Gallium Nitride (GaN)-based materials.

The intermediary material <NUM> is between the semiconductor structure <NUM> and the handle substrate <NUM>. As discussed above, the intermediary material <NUM> is a sacrificial material that can be removed (or at least partially removed) from between the semiconductor structure <NUM> and the handle substrate <NUM>. For example, the intermediary material <NUM> can include a deposited oxide material and/or a native oxide. In some embodiments, oxide materials can be fused together to attach the semiconductor structure <NUM> with the handle substrate <NUM>. For example, the native oxide of the semiconductor structure <NUM> can be fused with an oxide material of the handle substrate <NUM>. The intermediary material <NUM> can also include a different material in addition to or in lieu of an oxide material. For example, the intermediary material <NUM> can include a nitride-based material.

<FIG> shows the semiconductor device assembly <NUM> after removing material from the semiconductor structure <NUM> to form openings <NUM> in the semiconductor structure <NUM>. In particular, the openings <NUM> can extend from a first side <NUM> of the semiconductor structure <NUM> to a second side <NUM> of the semiconductor structure <NUM> to expose surfaces <NUM> of the intermediary material <NUM> through the openings <NUM>. The exposed surfaces <NUM>, for example, can be flush with the semiconductor structure <NUM> at the second side <NUM> of the structure. In other examples, the exposed surfaces <NUM> can be recessed in the intermediary material <NUM>, or the openings <NUM> can extend completely through the intermediary material <NUM> (not shown) such that the exposed surfaces <NUM> are just the remaining sidewalls of the intermediary material <NUM>. For example, the openings <NUM> can be configured to expose a portion of the handle substrate <NUM> through the openings <NUM>. The openings <NUM> can at least partially define individual mesas <NUM> in the semiconductor structure <NUM>. For example, as described in further detail below with reference to <FIG>, the openings <NUM> can include trenches that isolate the individual mesas <NUM> from one another. Each mesa <NUM> can define a die having one or more integrated circuits or other features.

<FIG> shows the semiconductor device assembly <NUM> after a transfer structure <NUM> is attached to the semiconductor structure <NUM>. The transfer structure <NUM> can include an adhesive (not shown) for at least temporarily binding the individual mesas <NUM> with the transfer structure <NUM>. The transfer structure <NUM> is configured to support the individual mesas <NUM> of the semiconductor structure <NUM> after the handle substrate <NUM> has been removed. The transfer structure <NUM> can include a die-attach tape, a carrier substrate (e.g., a wafer), or other suitable structure that is configured to support the individual mesas <NUM> in subsequent processing stages. The transfer structure <NUM> can be used to shield the active surfaces of the semiconductor structure <NUM> from contamination and debris associated with operator handling. The transfer structure <NUM> can also provide a diffusion barrier that mitigates oxidation at the active surfaces of the individual mesas <NUM>. However, the transfer structure <NUM> can be omitted, and thus the manufacturing stage at <FIG> can likewise be omitted. For example, the transfer structure <NUM> can be omitted when the semiconductor structure <NUM> is not decoupled from the support structure <NUM> (see, e.g., <FIG> and <FIG>).

<FIG> shows the semiconductor device assembly <NUM> after a portion of the intermediary material <NUM> adjacent the openings <NUM> has been removed via the openings <NUM> of the semiconductor structure <NUM>. In particular, the removed intermediary material forms a gap S<NUM> that undercuts the individual mesas <NUM> of the semiconductor structure <NUM> at the second side <NUM>. The semiconductor device assembly <NUM> can be placed into a chemical etchant (e.g., a chemical bath) to submerge or at least partially submerge the semiconductor structure <NUM> in the etchant. As shown by arrows "E", the etchant undercuts the portions of the semiconductor structure <NUM> adjacent the openings <NUM> in the semiconductor structure <NUM>. The transfer structure <NUM> can be configured such that it does not substantially degrade in an acidic (or basic) solution of the chemical etchant.

<FIG> shows the semiconductor device assembly <NUM> after the semiconductor structure <NUM> has been decoupled from the handle substrate <NUM>. In particular, the semiconductor structure <NUM> is decoupled by removing the intermediary material <NUM> (<FIG>) until the handle substrate <NUM> is released from the semiconductor structure <NUM>. Once released, the handle substrate <NUM> can be recycled and used to form other semiconductor structures. Alternatively, the handle substrate <NUM> can be discarded depending on the life-cycle of the handle substrate <NUM>. For example, the handle substrate <NUM> can be discarded if it has become too thin, contaminated, and/or cycled more than a pre-determined number of times.

<FIG> is an isometric view of a semiconductor device assembly <NUM>. The semiconductor device assembly <NUM> can be similar to the semiconductor device assembly <NUM> after the processing stage of <FIG>, but in <FIG> the semiconductor device assembly <NUM> is inverted. In <FIG>, the openings <NUM> between the individual mesas <NUM> are trenches <NUM> (identified individually as first through third trenches 222a-222c) that extend to the intermediary material <NUM> of the support structure <NUM>. In the illustrated example, the first and second trenches 222a and 222b are generally in parallel with one another and are generally perpendicular with the third trench 222c. In this configuration, the trenches <NUM> separate the semiconductor structure <NUM> to form discrete semiconductor devices <NUM>. Although the Figures show the trenches <NUM> in a linear arrangement, in other examples one or more of the trenches <NUM> can have a non-linear arrangement (e.g., curved, sloped, etc.).

The semiconductor devices <NUM> can include electrical contacts <NUM> (e.g., metal contact pads). The semiconductor structure <NUM> (<FIG>) can be formed to include the electrical contacts <NUM>. Alternatively, the electrical contacts <NUM> can be formed on the semiconductor structure <NUM> at a later processing stage. The electrical contacts <NUM> can include a variety of suitable conductive materials that are electrically coupled to one or more active regions of the semiconductor devices <NUM>. In the illustrated example, the semiconductor devices <NUM> are "direct-attach" devices in which the electrical contacts can be directly bonded (e.g., via eutectic bonding) to a printed circuit board (not shown) or other suitable substrates. Direct-attach configurations can simplify assembly of semiconductor devices on such a substrate.

<FIG> is a schematic cross-sectional side view of a semiconductor device <NUM>. The semiconductor device <NUM>, for example, can be similar to one of the semiconductor devices <NUM> of <FIG> after the support structure <NUM> has been removed. The semiconductor structure <NUM> of the semiconductor device <NUM> includes a stack of semiconductor materials <NUM> (identified individually as first through third semiconductor materials 328a-c). For clarity, active regions of the semiconductor structure <NUM> are identified as source "S," gate "G," and drain "D" regions of a transistor device (e.g., of a HEMT power transistor device). Further, the active regions can be located in another type device, such as a bipolar transistor device, a capacitor, etc..

The semiconductor device <NUM> further includes electrical contacts <NUM> (identified individually as first through third electrical contacts 226a-226c) and a dielectric material <NUM> (e.g., Silicon Nitride (SiN)) that separates the individual electrical contacts <NUM> from one another. The first and second electrical contacts 226a and 226b are coupled, respectively, to the source S and drain D regions of the semiconductor structure <NUM> through Ohmic contact regions <NUM> (e.g., locally doped regions of the first semiconductor material 328a). The third electrical contact 226c is coupled to the gate region G of the semiconductor device <NUM> without an intermediary Ohmic contact region. The first semiconductor material 328a of the semiconductor device <NUM> can include Aluminum GaN (AlGaN) and the second semiconductor material 328b can include GaN. In several embodiments, the third semiconductor material 328c can include AlGaN. The semiconductor device <NUM> can include different materials and/or features.

In operation, the gate region G provides a conductive channel (e.g., a two-dimensional electron gas channel) that extends between the source region S and the drain region D of the semiconductor device <NUM>. As discussed above, the semiconductor device <NUM> can have less parasitic conduction (or no parasitic conduction) relative to conventional semiconductor devices. In particular, the handle substrate <NUM> (<FIG>) has been decoupled to remove parasitic conduction paths.

<FIG> is a schematic cross-sectional side view of another semiconductor device <NUM>. The semiconductor device <NUM>, for example, can be similar to the semiconductor device <NUM> of <FIG>. However, the semiconductor device <NUM> is different than the semiconductor device <NUM> of <FIG> in that the semiconductor device <NUM> includes first and second trenches 432a and 432b formed in the semiconductor structure <NUM>. In particular, the first and second trenches 432a and 432b mechanically isolate the source and drain regions S and D from the gate region G. Such mechanical isolation can, for example, decrease parasitic conduction between the source region S and the gate region G and/or the drain region D and the gate region G.

The first and second trenches 432a and 432b can be formed in the semiconductor structure <NUM> by one or more etch processes. For example, the second semiconductor material 328b can be configured as an etch stop material. Alternatively, the etch processes can be timed to form the first and second trenches 432a and 432b to a depth that does not substantially extend (or extend at all) into the second semiconductor material 328b. In one case, the first and second trenches 432a and 432b are formed in the semiconductor structure <NUM> at stage before the stage of <FIG>. In other cases, the first and second trenches are formed at a different manufacturing stage. For example, the first and second trenches 432a and 432b can be formed in semiconductor device assembly that incorporates a portion of the handle substrate into the finished device.

<FIG> is a schematic cross-sectional side view of a semiconductor device <NUM>. The semiconductor device <NUM>, for example, can be similar to the semiconductor device <NUM> of <FIG>. However, the semiconductor device <NUM> includes an electrical contact <NUM> at the second side <NUM> of the semiconductor device <NUM> (rather than between the source and drain regions S and D at a first side <NUM> of the semiconductor device). The electrical contact <NUM> can be formed, for example, by depositing a conductive material on the third semiconductor material 328c at the second side <NUM> of the semiconductor device <NUM>. In this example, the third semiconductor material 328c can be the gate region G. A dimension d<NUM> (e.g., a length or a surface area) can be configured to achieve a certain capacitance at the gate region G. Such a configuration has several advantages over conventional devices in that the dimension d<NUM> does not change the overall footprint of the semiconductor device <NUM> (so long as the dimension d<NUM> of the gate region G is smaller than the combined dimensions of the first and second electrical contacts 226a and 226b). By contrast, a gate region in a conventional transistor device is typically constrained to a particular range of dimensions. In particular, because the source, gate, and drain regions of a conventional device are all located at the same side of the device, each region contributes to the overall footprint. For example, to retain a certain footprint size, the gate region can only be increased in size if one or both of the source and drain regions S and D are decreased in size.

The semiconductor device <NUM> is also different than the semiconductor device <NUM> of <FIG> in that the semiconductor device <NUM> includes a trench <NUM> between the source region S and the drain region D (rather than between the gate region G and each of the source region S and the drain region D). The trench <NUM> includes a first sidewall 533a adjacent the source region S and a second sidewall 533b adjacent the drain region D. However, the trench <NUM> can be omitted and the source region S can be isolated from the drain region D differently. For example, the source region S and the drain region D can include semiconductor material with different doping types (e.g., P-type or N-type) to form a reverse-biased diode between these regions.

<FIG> is a schematic cross-sectional side view of a semiconductor device <NUM> configured in accordance with an embodiment of the present invention. The semiconductor device <NUM> is different than the semiconductor devices <NUM> of <FIG> in that the semiconductor device <NUM> remains coupled to the handle substrate <NUM> via the intermediary material <NUM>. As illustrated, the semiconductor device <NUM> includes an opening <NUM> formed through the gate region G of the semiconductor device <NUM>. In this configuration, the opening <NUM> provides a passageway through which an etchant can remove a portion of the intermediary material <NUM> to undercut the gate region G. The amount of undercut can be configured to mechanically isolate the gate region G from the handle substrate <NUM> by an undercut distance d<NUM> of the gap S<NUM>. The undercut distance d<NUM> can be selected to achieve a certain amount of isolation. For example, the undercut distance d<NUM> can extend beyond the gate region G and beneath the source and drain regions S and D (not shown).

The amount of undercut is configured to provide mechanical isolation, but also retain a sufficient amount of the intermediary material <NUM> at the second side of <NUM> of the semiconductor device <NUM> such that the semiconductor device <NUM> does not readily decouple from the handle substrate <NUM>. For example, the source region S and/or the drain region D can be undercut by the gap S<NUM> (e.g., adjacent the opening <NUM>; <FIG>), with the undercut distance d<NUM> selected such that the third semiconductor material 328c does not readily decouple from the handle substrate <NUM>. In another, non-illustrated example, one or both of the source and drain regions S and D have no undercut at all or are only an undercut at one side (e.g., at the side adjacent the gate region G).

<FIG> is an isometric view of a semiconductor device assembly <NUM> configured in accordance with a selected embodiment of the present invention. The semiconductor device assembly <NUM> can be similar to the semiconductor device assembly <NUM> after the processing stage of <FIG> (shown without the transfer structure <NUM> on the first side <NUM> of the semiconductor structure <NUM> in <FIG>). However, the semiconductor device assembly <NUM> is different than the semiconductor device assembly <NUM> in that individual semiconductor devices <NUM> include the opening <NUM> through the semiconductor device <NUM>. As shown, the openings <NUM> can be cylindrical; however, in other embodiments the openings <NUM> can have different shapes. For example, the openings <NUM> can be elongated trenches that are parallel with the first and second trenches 222a and 222b.

Also, the semiconductor device assembly <NUM> can be similar to the semiconductor device assembly <NUM> of <FIG>. However, the semiconductor device assembly <NUM> is different than the semiconductor device assembly <NUM> in that the semiconductor devices <NUM> are configured to be singulated such that they include a portion of the handle substrate <NUM>. In one embodiment, for example, the trenches <NUM> can provide locations for dicing streets, which can be subsequently cut to singulate the individual semiconductor devices <NUM> (e.g., via a dicing saw). In another embodiment, however, the trenches <NUM> can be omitted and the semiconductor devices <NUM> can be separated by conventional singulation techniques known in the art.

Any one of the semiconductor devices and semiconductor device assemblies having the features described above with reference to <FIG> can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system <NUM> shown schematically in <FIG>. The system <NUM> can include a processor <NUM>, a memory <NUM> (e.g., SRAM, DRAM, flash, and/or other memory devices), input/output devices <NUM>, and/or other subsystems or components <NUM>. The semiconductor devices and semiconductor device assemblies described above with reference to <FIG> can be included in any of the elements shown in <FIG>. The resulting system <NUM> can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of the system <NUM> include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system <NUM> include lights, cameras, vehicles, etc. With regard to these and other examples, the system <NUM> can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of the system <NUM> can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media.

Claim 1:
A method, comprising:
forming a semiconductor device assembly (<NUM>) that includes:
a handle substrate (<NUM>);
a semiconductor structure (<NUM>) having a first side (<NUM>), a second side (<NUM>) opposite the first side, and active regions of a transistor device, wherein the active regions include a source region (S), a drain region (D), and a gate region (G) between the source and drain regions; and
an intermediary material (<NUM>) between the second side (<NUM>) of the semiconductor structure and the handle substrate;
removing material from the gate region of the semiconductor structure to form an opening ( <NUM>) extending from the first side (<NUM>) of the semiconductor structure through an active region of the semiconductor structure to at least the intermediary material (<NUM>) at the second side (<NUM>) of the semiconductor structure; and
removing a first portion of the intermediary material via the opening in the gate region of the semiconductor structure to undercut the second side of the semiconductor structure, wherein a second portion of the intermediary material remains between the semiconductor structure and the handle substrate;
wherein the active regions are at the first side (<NUM>) of the semiconductor structure.