Patent Description:
A phase locked loop (PLL) generates an output signal with a defined phase relationship to an input reference signal. The output signal is matched to the phase of the input reference signal by a feedback loop in which the phase difference between the input reference signal and the output signal is determined by a phase detector. In a digital phase locked loop, the phase detector outputs a digital signal. The output from the phase detector (indicating phase error) is received by a loop filter. The loop filter in turn provides an output signal to a frequency-controlled oscillator. In an all-digital phase locked loop (ADPLL), the phase detector outputs a digital signal, the loop filter is a digital loop filter, and the frequency-controlled oscillator is a digitally controlled oscillator.

An integer ADPLL includes a reference phase generator configured to integrate an input frequency control word (FCW), a phase detector, a loop filter, a digitally controlled oscillator (DCO), and a feedback path including a counter and a time-to-digital converter (TDC). The FCW of an integer ADPLL is a constant integer value that describes the ratio between the DCO frequency and a reference frequency. The DCO frequency can only be an integer multiple of the reference frequency in an integer ADPLL.

Document <CIT> relates to phase locked loop circuits, and in particular to a sampling digital phase locked loop that operates on frequency, rather than phase, error.

Document <CIT> relates to an integrated circuit for preventing a fractional spur from occurring due to non-linearity of a digital-time converter, and an electronic device including the same, and an operating method thereof.

By dithering the FCW, an integer ADPLL can function as a fractional-N ADPLL. For example, addition of a delta-sigma modulator can produce a fractional-N frequency resolution in the parts per million (ppm) range. However, dithering the FCW with a delta-sigma modulator generates an offset to an integer frequency which causes the phase to move over the entire phase range. By moving over the phase range, quantization effects cause a regular pattern that leads to spurious tones (also referred to as spurs) in the feedback path. Furthermore, the shaped noise with contributions mainly at high frequencies generated by the delta-sigma modulator can negatively impact the ADPLL performance. Phase locked loops are often required to achieve a specific noise performance and the maximum allowable phase noise may be determined by an intended application for a phase locked loop. Depending on the application of the phase locked loop, spurious tones can lead to serious performance degradation of an entire system. For example, if the phase locked loop is used as a local oscillator in a transceiver, spurious tones lead to unwanted mixing of side channels and result in a reduced signal to noise ratio. If the phase locked loop is used as a clock source of a digital circuit, spurious tones lead to additional clock uncertainty and can cause timing violations. If the phase locked loop is used in highspeed interfaces, spurious tones degrade the jitter performance and can lead to an increased bit error rate. Fractional-N ADPLLs and fractional-N PLLs in general are particularly prone to exhibiting spurs in their output spectrum when the ratio of output to input frequency is close to an integer value, severely limiting their application in such cases.

<FIG> illustrate techniques for reducing spurious tones introduced by delta sigma modulation of the FCW to implement a fractional-N ADPLL. By adding a randomly modulated delay having a triangular distribution to a frequency reference at an input of the fractional-n ADPLL, spurious tones are reduced for multiple TDC resolutions without requiring active control or calibration. In some embodiments, the randomly modulated delay is added via a delay line. The delay line is analog in some embodiments and digital in other embodiments and is controlled by a digital signal. The range of the randomly modulated delay spans at least q to -q, where q is the quantization step (sometimes referred to as the "quantization step size") of the TDC.

In some embodiments, the delay line generates the randomly modulated delay based on a uniformly distributed random number with a flat spectrum that is shaped by a high pass filter. The high pass filtering is performed by a first order high pass filter that differentiates the uniformly distributed random number in some embodiments. After differentiation, the random number follows a triangular distribution which still covers the range of at least spans at least q to -q, where q is the quantization step of the TDC. Due to high-pass filtering, low frequency components of the noise added by the delay line are rejected. In addition, the PLL acts as a low-pass filter that rejects most of the high-pass shaped dither signal added by the delay line. As a result, the dither signal does not add significant noise to the PLL's output spectrum.

In some embodiments in which the delay line is implemented in an analog manner, the delay line includes a number of unit delay cells and a delay line controller varies either the delay of each unit delay cell or the number of unit delay cells that the dither signal traverses. In some embodiments in which the delay line implements digital control, the delay line includes dynamic element matching to increase linearity. To facilitate both expanded range and resolution of the randomly modulated delay, in some embodiments the delay line is split into a fine delay line and a coarse delay line with differing unit delays.

<FIG> illustrates a system <NUM> including an example fractional-N ADPLL <NUM> with single delay line reference dithering in accordance with some embodiments. The fractional-N ADPLL <NUM> receives a system clock signal CKR <NUM>. Based on the system clock signal CKR <NUM>, the system <NUM> produces an output signal CLK_OUT <NUM>. The output signal CLK_OUT <NUM> includes an output frequency labeled and an output phase. Upon receiving a new system clock signal CKR <NUM> having one or more of a new frequency reference and a new phase reference, the fractional-N ADPLL <NUM> first tunes to, and locks to, a new output signal CLK_OUT <NUM> having a new output frequency and a new output phase. The system <NUM> includes a fractional-N ADPLL <NUM> and a variable delay line <NUM>, a high pass filter <NUM>, and a random number source <NUM>. The fractional-N ADPLL <NUM> includes a reference phase generator <NUM>, a phase detector <NUM>, a loop filter <NUM>, a digitally controlled oscillator (DCO) <NUM>, a counter <NUM>, and a time-to-digital converter (TDC) <NUM>. Components in the fractional-N ADPLL <NUM> that are analog are illustrated with shading. Other components in the fractional-N ADPLL <NUM> are digital and are illustrated without shading.

The reference phase generator <NUM> includes an adder <NUM> and a register <NUM> arranged to integrate an input integer frequency control word signal having FCW. i <NUM> and FCW. f <NUM> which are dithered by a delta-sigma modulator <NUM> with a fractional frequency control word signal. Both are added at <NUM>. The system clock signal CKR <NUM> is derived from a reference signal FREF <NUM> by sampling the reference signal FREF <NUM> with the DCO <NUM> clock, and provides an output signal with a stable frequency that is used to clock the register <NUM> of the reference phase generator <NUM>. The reference phase generator <NUM> is configured to convert the FCW. i <NUM> and FCW. f <NUM> from the frequency domain to the phase domain and provide a reference phase ramp PHI_REF. The phase detector <NUM> compares the reference phase ramp PHI_REF with a feedback ramp PHV derived from the output of the DCO <NUM>, and outputs a phase error signal PHE. The feedback ramp PHV is determined by combining (e.g., by fixed point concatenation) the output from the counter <NUM> and the TDC <NUM>.

The loop filter <NUM> is controlled by an ADPLL control block (not shown) and receives the phase error signal PHE and performs a filtering operation. The loop filter <NUM> provides three output signals for controlling the DCO <NUM>: a process voltage temperature control signal PVT, an acquisition control signal ACQ, and a tracking signal TR. Each of these control signals controls a switched capacitor bank of the DCO <NUM> to vary the output frequency of the DCO <NUM>, which is an integer multiple of the reference frequency FREF <NUM> when the fractional-N ADPLL <NUM> is operated in integer mode and the loop is settled. Other frequency control mechanisms, such as digital to analog converters with varactors, or a current-controller oscillator controlled by a current digital-to-analog converter (DAC), are used in alternative arrangements.

The output from the DCO <NUM> is received as an input signal at the TDC <NUM>. The TDC <NUM> measures and quantizes the timing difference between transitions of the output signal from the system clock signal CKR <NUM> and the transitions in the output from the DCO <NUM>. The TDC <NUM> produces a TDC output labeled PHV_F. The counter <NUM> accumulates a count of the transitions in the output from the DCO <NUM> and produces an output labeled as PHV_I. The combination of the signals from the TDC <NUM> and the counter <NUM> results in an input PHV to the phase detector <NUM>. The phase detector <NUM> sums a signal from the reference phase generator <NUM> and a negative value of a phase based on the TDC <NUM> output PHV_F and the counter <NUM> output PHV_I to produce a phase difference signal labeled PHE which serves as an input to the loop filter <NUM>.

To facilitate the reduction of spurious tones that can be caused by regular quantization patterns in the feedback path from dithering of the fractional frequency control word FCW. f <NUM> by the delta-sigma modulator <NUM> and adding it to the integer frequency control word FCW_i <NUM>, the system <NUM> introduces a randomly modulated delay <NUM> (also referred to as a dithering signal) with controlled properties to dither the phase of the reference frequency <NUM> at the input to the fractional-N ADPLL <NUM>. For example, if the reference frequency FREF <NUM> is <NUM> megahertz and the ratio of the output frequency CLK_OUT <NUM> to the input frequency is <NUM>, an offset of <NUM> kilohertz will appear as a spur in the output frequency CLK-OUT <NUM> signal and additional spurs will occur at multiples of the calculated offset frequency. To reduce such spurs, the system <NUM> dithers the phase error by adding noise in the form of a randomly modulated delay <NUM> (also referred to as a dithering signal) to the feedback signal (also referred to as a frequency reference or reference clock signal) of the fractional-N ADPLL <NUM>. The randomly modulated delay <NUM> is added via a variable delay line <NUM> that receives a uniformly distributed random number <NUM> generated by a random number source <NUM> such as a linear feedback shift register (LFSR) that is shaped by a high pass filter <NUM>. In some embodiments, the variable delay line <NUM> is implemented in the analog domain and in other embodiments the variable delay line <NUM> is implemented in the digital domain.

After filtering by the high pass filter <NUM>, the random number has a triangular distribution and is used as a delay control <NUM> for the variable delay line <NUM>. The amplitude of the randomly modulated delay <NUM> is large enough to cover more than the least significant bits (LSB) of the feedback path. In some embodiments, the dither range is selected to be larger because spur suppression is relatively insensitive to large dither ranges and smaller dither ranges lead to less effective spur suppression. In some embodiments, the variable delay line <NUM> is divided into a coarse resolution portion (not shown) and a fine resolution portion (not shown) to enable a high dithering signal amplitude with high timing resolution. In addition, in some embodiments the dithering signal <NUM> is noise shaped to prevent impact to inband phase noise of the fractional-N ADPLL <NUM>.

<FIG> is a graph <NUM> of a probability distribution of a uniformly distributed random number generated by the random number source <NUM> in accordance with some embodiments. The value range of the uniformly distributed random number is normalized to have a value range from -<NUM> to <NUM>. Because the random number is uniformly distributed, the probability P of the random number having any value within the range of -<NUM> to <NUM> is the same, giving the probability distribution a flat shape or spectrum.

<FIG> is a graph <NUM> of a probability distribution of the uniformly distributed random number after high pass filtering with a first order high pass filter such as high pass filter <NUM> in accordance with some embodiments. The high pass filter <NUM> differentiates the uniformly distributed random number such that the graph <NUM> of the probability distribution of the differences between the normalized values of the uniformly distributed random number follows a triangular distribution. The range of the triangular distribution covers at least spans at least q to -q, where q is the quantization step of the TDC <NUM>. In the illustrated example, the minimum and maximum differences between normalized values of the uniformly distributed random number range from -<NUM> to <NUM>. The probability P of the difference between normalized values of the uniformly distributed random number being zero is high, whereas the probability P of the differences between normalized values of the uniformly distributed random number having a value within the range of -<NUM> to <NUM> diminishes linearly as the differences approach the extents of the range.

Due to high pass filtering by the high pass filter <NUM>, low frequency components of the noise are rejected. Further, because the phase locked loop acts as a low-pass filter, most of the high-pass shaped dither signal is rejected such that the dither signal does not add significant noise to the output spectrum of the fractional-N ADPLL <NUM>. The order of the low pass loop filter <NUM> is selected such that the noise introduced by the delta-sigma modulator <NUM> is cancelled and contributes only -<NUM> dB/decade to the overall noise characteristics of the fractional-N ADPLL <NUM>. In some embodiments, the delta-sigma modulator <NUM> is implemented as a multi-stage noise shaping (MASH <NUM>-<NUM>-<NUM>) structure with a noise shaping characteristic of +<NUM> dB/decade and the loop filter <NUM> is implemented as at least a third order filter. In other embodiments, other implementations of the delta-sigma modulator <NUM> are used, and characteristics of the loop filter <NUM> are selected to reject delta-sigma quantization noise from the output.

<FIG> is a block diagram <NUM> of the fractional-N ADPLL <NUM> having the reference frequency <NUM> dithered by the variable delay line <NUM> in accordance with some embodiments. The random number <NUM> generated by the random number source <NUM> is filtered by the high pass filter <NUM> to produce noise <NUM> having a triangular distribution. The noise <NUM> is added to the reference frequency <NUM> at the variable delay line <NUM> to produce the randomly modulated delay <NUM> that is input to the fractional-N ADPLL <NUM>. The resulting randomly modulated delay <NUM> produces a triangularly distributed and noise shaped non-subtractive reference dither that reduces fractional-N spurs in the fractional-N ADPLL <NUM> without adversely affecting the overall phase noise. The randomly modulated delay <NUM> in conjunction with the higher order loop filter <NUM> cancels the delta-sigma quantization noise without requiring active control or calibration.

<FIG> is a diagram of a variable delay line <NUM> in accordance with some embodiments. In some embodiments in which the variable delay line <NUM> is implemented in an analog manner, the variable delay line includes a plurality of unit delay cells <NUM>, <NUM>. In other embodiments, the analog variable delay line <NUM> is implemented using non-unit weighted delays (not shown). The variable delay line <NUM> varies either the delay of each unit delay cell <NUM>, <NUM>, or the number of cells that a signal that is to be delayed traverses. In some embodiments, the variable delay line <NUM> varies the delay of a logic gate by limiting the supply current <NUM> and increasing the load capacitance <NUM> at the output of the unit delay cell <NUM>, <NUM>. Varying the delay of the logic gate is achieved in either the analog domain or the digital domain. For example, to increase the load, a varactor can be used for analog control, while switched capacitances can be used to provide digital control. As another example, varying the supply current is performed in some embodiments via voltage-controlled current sources to provide analog control, while switching the amount of fixed current source provides digital control. In the illustrated example, latches are used as noninverting buffers, the delays of which are modulated by switching capacitive loads using CMOS transmission gates.

<FIG> is a diagram of a delay line <NUM> with unit delay cells <NUM>, <NUM> applying constant delays in accordance with some embodiments. In the illustrated example, the delays of the unit delay cells <NUM>, <NUM> are not varied. Instead, the number of elements the reference traverses is varied by tapping the delay line at different points.

<FIG> is a block diagram of a system <NUM> including the fractional-N ADPLL <NUM> having a frequency reference dithered by the variable delay line <NUM> with digital control and a dynamic element matching module <NUM> in accordance with some embodiments. To generate the control signal for the variable delay line <NUM> with analog control, in some embodiments thermal noise serves as a uniform random source and the triangularly distributed random signal, such as noise <NUM> in <FIG>, is generated by high-pass filtering the output from the uniform random source.

To generate a digital control signal, in some embodiments the system <NUM> includes a linear-feedback shift register (LFSR) <NUM> as a uniform pseudo-random source and a simple finite impulse response high-pass filter <NUM> with a z-domain transfer function <NUM> - z-<NUM> to generate the triangularly distributed random signal. The LFSR <NUM> produces a statistically even predictable stream of bits having approximately the same number of zeros as ones on average. In the illustrated example, the system <NUM> includes the dynamic element matching module <NUM> to increase linearity when using a digitally controlled variable delay line <NUM>. In some embodiments, the dynamic element matching module <NUM> includes one or more dynamic element matching circuits. Mismatches among nominally identical circuit elements cause non-linear distortion that appears as spurs caused by the delay line. The spurs become visible in the output clock and can therefore be measured in the phase error signal. By randomizing the mismatches, the dynamic element matching module <NUM> causes the error resulting from the mismatches to be pseudo-random noise that eliminates the spurs from the delay line.

In some embodiments that implement the variable delay line <NUM> with digital control, the system <NUM> monitors the timing relationship between the control signal and the reference propagating through the variable delay line <NUM>. The system <NUM> ensures that the control signals do not change while a reference clock edge propagates through the variable delay line <NUM>. In some embodiments, the system <NUM> clocks the control signal generation circuitry with the output of the variable delay line <NUM>.

<FIG> is a block diagram of a delay line <NUM> divided into a coarse resolution variable delay line <NUM> and a fine resolution variable delay line <NUM> in accordance with some embodiments. Splitting the delay line <NUM> into the coarse resolution variable delay line <NUM> and the fine resolution variable delay line <NUM> enables a large dithering amplitude with high timing resolution. The coarse resolution variable delay line <NUM> receives a random number <NUM> generated by a random number source <NUM> that is filtered by a high pass filter <NUM>, while the fine resolution variable delay line <NUM> receives a random number <NUM> generated by a random number source <NUM> that is filtered by a high pass filter <NUM>. In the illustrated example, the fine resolution variable delay line <NUM> is controlled independently of the coarse resolution variable delay line <NUM>. In some embodiments, the fine resolution variable delay line <NUM> introduces a variable delay on the order of <NUM> femtoseconds, while the coarse resolution variable delay line <NUM> introduces a variable delay on the order of <NUM> picoseconds. Whereas a single variable delay line such as that illustrated in <FIG> includes on the order of <NUM> stages in some embodiments, a divided variable delay line such as that illustrated in <FIG> includes on the order of <NUM> stages for each of the coarse resolution variable delay line <NUM> and the fine resolution variable delay line <NUM> in some embodiments while achieving similar suppression of tones in the quantization noise.

<FIG> is a graph <NUM> illustrating noise in a fractional-N ADPLL without dithering by a delay line. The graph <NUM> depicts the output noise spectrum of an example fractional-N ADPLL with a ratio of output to input frequency of <NUM> without dither enabled. The spectrum contains large spurs, for example, at <NUM> kilohertz, which limit the usage of the fractional-N ADPLL.

<FIG> is a graph <NUM> illustrating noise reduction in a fractional-N ADPLL having a frequency reference dithered by a delay line in accordance with some embodiments. The graph <NUM> depicts the output noise spectrum of an example fractional-N ADPLL with a ratio of output to input frequency of <NUM> with dither enabled. The spectrum is free of any visible spurs.

<FIG> is a flow diagram of a method <NUM> of dithering a phase of a reference clock signal at an input of a fractional-n ADPLL with a dithering signal having a triangular distribution in accordance with some embodiments. The method <NUM> is described with respect to an example implementation of the system <NUM> of <FIG>. The system <NUM> includes the fractional-N ADPLL <NUM> in which the frequency control word is modulated by the delta-sigma modulator <NUM>, which introduces spurious tones due to regular quantization patterns in the feedback path. At block <NUM>, the random number source <NUM> generates a uniformly distributed random number <NUM> having a flat spectrum. In some embodiments, the random number source <NUM> is implemented as the LFSR <NUM>.

At block <NUM>, the high pass filter <NUM> high-pass filters the uniformly distributed random number <NUM> to produce a random number having a triangular distribution to use as the delay control <NUM> input to the variable delay line <NUM>. In some embodiments, the high pass filter <NUM> is a first order high pass filter that differentiates the uniformly distributed random number <NUM> such that the probability distribution of the differences between the normalized values of the uniformly distributed random number follows a triangular distribution. At block <NUM>, the triangularly distributed random number is input to the variable delay line <NUM>.

At block <NUM>, the variable delay line <NUM> generates a randomly modulated delay <NUM> having a triangular distribution. In some embodiments, the variable delay line <NUM> is controlled by a digital signal and is implemented in either the analog domain or the digital domain. In some embodiments in which the variable delay line <NUM> is implemented in the analog domain, the variable delay line <NUM> includes a plurality of unit delay cells <NUM>, <NUM> and varies either the delay of each unit delay cell <NUM>, <NUM> or the number of unit delay cells <NUM>, <NUM> that the signal that is to be delayed traverses. In some embodiments in which the variable delay line <NUM> is implemented in the digital domain, a dynamic element matching module <NUM> is included to randomize mismatch to eliminate spurs from the variable delay line <NUM>. Further, in some embodiments the variable delay line <NUM> is implemented as a single delay line, while in other embodiments the variable delay line <NUM> is split into a coarse resolution variable delay line <NUM> and a fine resolution variable delay line <NUM>.

At block <NUM>, the randomly modulated delay <NUM> is input to the fractional-N ADPLL <NUM> to reduce spurious tones resulting from delta-sigma modulation of the frequency control word <NUM>. In some embodiments, additional control signals can be added to control the amount of dither to support dithering for multiple TDC resolutions.

Claim 1:
A method comprising:
dithering an input frequency control word (FCW.I) of an integer all-digital phase locked loop, ADPLL, such that the ADPLL functions as a fractional-n ADPLL (<NUM>), wherein the ADPLL comprising: a delta-sigma modulator (<NUM>) configured to dither the input frequency control word (FCW.I) with a fractional frequency control word signal (FCW.F),
a reference phase generator <NUM>) configured to integrate the dithered input frequency control word to generate a reference phase (PHI_REF),
a phase detector (<NUM>) configured to compare the reference phase (PHI_REF) with a feedback phase (PHV),
a loop filter (<NUM>) configured to receive the phase comparison result (PHE) from the phase detector (<NUM>) and generate control signals (PVT,ACQ,TR),
a digitally controlled oscillator, DCO, (<NUM>), configured to receive control signals (PVT,ACQ,TR) and generate an output signal (CLK_OUT),
a feedback path including a counter (<NUM>) and a time-to-digital converter, TDC, (<NUM>), configured to receive a delay-modulated frequency reference (<NUM>) and the output signal (CLK_OUT), and generate the feedback phase (PHV), and
a delay line (<NUM>) configured to receive a frequency reference (FREF) and generate the delay-modulated frequency reference (<NUM>); and
generating a randomly modulated delay based on a uniformly distributed random number with a flat spectrum shaped by a high pass filter (<NUM>), wherein the random number has the triangular distribution spanning at least q to -q after shaping by the high pass filter;
adding the randomly modulated delay having a triangular distribution to the frequency reference at an input of the fractional-n ADPLL, by modulating the delay of the delay line (<NUM>) to generate the delay-modulated frequency reference (<NUM>) provided to the input of the fractional-n ADPLL, wherein a range of the randomly modulated delay spans at least q to -q, wherein q is a quantization step of the time-to-digital converter (<NUM>) of the ADPLL.