Patent Description:
Many designers utilize libraries of standard cells to build circuit designs for electronic devices. The standard cells in these libraries typically include descriptions of digital circuitry and their various characteristics, such as timing information, power estimation, functionality, operating conditions, or the like, which can be specified using a Liberty format. For example, the Liberty format can include lookup tables populated with timing information of the standard cells in the libraries, such as cell delays, transition times and setup and hold constraints, or the like.

Since timing and power characteristics of digital circuits can vary in manufactured electronic devices, often called on-chip variation (OCV), the standard cell descriptions can also include statistical variation information, for example, specified in a Liberty Variation Format (LVF) extension to the Liberty format, which models the impacts of manufacturing-related variation associated with on-chip variation. The designers typically utilize the statistical variation information during a Statistical Timing Analysis (STA) to account for the impact that manufacturing-related variation has on delays in timing paths of the circuit designs during functional verification.

A common technique used to characterize standard cells and generate the statistical variation information includes identifying random samples of manufacturing-related variation, for example, through Monte Carlo sampling, and then individually applying the characteristics of the random samples to the digital circuitry of the standard cell and simulating the digital circuitry of the standard cell using an analog simulator. In order to have an accurate estimate of the impact of the variation, for example, a +/- <NUM> sigma value, the analog simulator would have to perform approximately <NUM>,<NUM> simulations per measurement, which can be processing intensive and impractical to characterize the millions of different measurements in a standard cell library. For that reason, some designers elect to perform <NUM>,<NUM>-<NUM>,<NUM> simulations, at most, and then extrapolate the results. As the size of the electronic devices has become smaller, the extrapolated results have become less accurate causing issues with timing closure and silicon failure. Other designers have attempted to speed up the characterization process by generating models of the standard cells, which can be simulated more quickly, and then simulating the model rather than the standard cells. While this characterization approach can reduce overall simulation time, it remains processing intensive and can still consumes weeks of the development timeframe.

Document "<NPL>, discloses yield analysis methods for SRAM cells combining importance sampling and boundary searching methods, including finding all likely failure regions and then, do importance sampling on these regions.

Document <CIT> discloses a method and a system to estimate failure rates in electric circuit designs that have performance influenced by variation, where the variation is modeled at least in part by a probability distribution, and the probability of failing specifications is significantly lower than the probability of passing.

Document "<NPL>of, discloses background information on efficiently designing circuits accounting for statistical process variation with target yields of two to three sigma.

The invention is defined by the enclosed claims. This application discloses a computing system implementing a design characterization tool can sample a distribution of values describing manufacturing variation for an integrated circuit described by a circuit design. The samples can be divided into training samples and characterization samples. The design characterization tool can utilize the training samples to generate a surrogate model of the circuit design, for example, by prompting simulation of the circuit design utilizing the training samples and then generating the surrogate model of the circuit design based on the results of the simulation of the circuit design with the training samples.

The design characterization tool can order the characterization samples by utilizing the surrogate model to predict outputs of the circuit design during simulation utilizing the samples. The design characterization tool can simulate the surrogate model or the circuit design utilizing the ordered samples, and stop the simulations prior to all of the samples from the distribution having been utilized in the simulations. The design characterization tool can utilize at least one of a confidence interval stopping condition or a drought stopping condition to determine when to stop the simulations. The design characterization tool can utilize results of the simulations to characterize operational variation of the circuit design to the manufacturing variation described in the distribution of the values. Embodiments of will be described below in greater detail.

Various examples may be implemented through the execution of software instructions by a computing device <NUM>, such as a programmable computer. Accordingly, <FIG> shows an illustrative example of a computing device <NUM>. As seen in this figure, the computing device <NUM> includes a computing unit <NUM> with a processor unit <NUM> and a system memory <NUM>. The processor unit <NUM> may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory <NUM> may include both a read-only memory (ROM) <NUM> and a random access memory (RAM) <NUM>. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) <NUM> and the random access memory (RAM) <NUM> may store software instructions for execution by the processor unit <NUM>.

The processor unit <NUM> and the system memory <NUM> are connected, either directly or indirectly, through a bus <NUM> or alternate communication structure, to one or more peripheral devices <NUM>-<NUM>. For example, the processor unit <NUM> or the system memory <NUM> may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive <NUM>, which can be magnetic and/or removable, a removable optical disk drive <NUM>, and/or a flash memory card. The processor unit <NUM> and the system memory <NUM> also may be directly or indirectly connected to one or more input devices <NUM> and one or more output devices <NUM>. The input devices <NUM> may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices <NUM> may include, for example, a monitor display, a printer and speakers. With various examples of the computing device <NUM>, one or more of the peripheral devices <NUM>-<NUM> may be internally housed with the computing unit <NUM>. Alternately, one or more of the peripheral devices <NUM>-<NUM> may be external to the housing for the computing unit <NUM> and connected to the bus <NUM> through, for example, a Universal Serial Bus (USB) connection.

With some implementations, the computing unit <NUM> may be directly or indirectly connected to a network interface <NUM> for communicating with other devices making up a network. The network interface <NUM> can translate data and control signals from the computing unit <NUM> into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface <NUM> may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

It should be appreciated that the computing device <NUM> is illustrated as an example only, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device <NUM> illustrated in <FIG>, which include only a subset of the components illustrated in <FIG>, or which include an alternate combination of components, including components that are not shown in <FIG>. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and/or multiprocessor computers arranged into a network, or some combination of both.

With some implementations, the processor unit <NUM> can have more than one processor core. Accordingly, <FIG> illustrates an example of a multi-core processor unit <NUM> that may be employed with various embodiments. As seen in this figure, the processor unit <NUM> includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and/or instructions for execution.

Each processor core 201A and 201B is connected to an interconnect <NUM>. The particular construction of the interconnect <NUM> may vary depending upon the architecture of the processor unit <NUM>. With some processor cores 201A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect <NUM> may be implemented as an interconnect bus. With other processor units 201A and 201B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect <NUM> may be implemented as a system request interface device. In any case, the processor cores 201A and 201B communicate through the interconnect <NUM> with an input/output interface <NUM> and a memory controller <NUM>. The input/output interface <NUM> provides a communication interface to the bus <NUM>. Similarly, the memory controller <NUM> controls the exchange of information to the system memory <NUM>. With some implementations, the processor unit <NUM> may include additional components, such as a high-level cache memory accessible shared by the processor cores 201A and 201B. It also should be appreciated that the description of the computer network illustrated in <FIG> and <FIG> is provided as an example only, and is not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments.

<FIG> illustrates an example design characterization tool <NUM> to characterize manufacturing variability using truncated ordered sample simulation that may be implemented according to various embodiments. <FIG> illustrates a flowchart showing an example implementation of characterizing manufacturing variability using truncated ordered sample simulation according to various examples. Referring to <FIG> and <FIG>, a design characterization tool <NUM>, for example, implemented with the computing device <NUM> described in <FIG>, can receive a circuit design <NUM> describing an electronic device, such as an integrated circuit, in a transistor-level netlist format. The circuit design <NUM> can correspond to transistor-level netlists describing electronic circuits using metal-oxide-semiconductor (MOS) transistors, resistances, capacitors, inductances, or the like, for example, in a Simulation Program with Integrated Circuit Emphasis (SPICE) file format. In some embodiments, the circuit design <NUM> can be a standard cell design, for example, within a library of standard cells for the design characterization tool <NUM> to characterize.

The design characterization tool <NUM> can receive process variation information <NUM> describing manufacturing parameters, such as oxide thickness, oxide length, or the like, and how those parameters can vary during manufacturing. In some embodiments, the process variation information <NUM> can describe statistical conditions for manufacturing the circuit design <NUM> by defining a distribution of values for the manufacturing parameters, for example, having ranges of different potential oxide thicknesses, oxides lengths, or the like, and probabilities that a manufactured integrated circuit associated with the circuit design <NUM> falls at different locations in the ranges. The design characterization tool <NUM>, in some embodiments, can receive at least a portion of the process variation information <NUM> from an analog simulation system <NUM>. For example, the analog simulation system <NUM> can receive the circuit design <NUM>, identify process variables, such as the manufacturing parameters, from the circuit design <NUM>, and generate measurements for various portions of transistors in the circuit design <NUM>. The identified process variables and the measurements can correspond to at least a portion of the process variation information <NUM>. In some embodiments, the process variation information <NUM> can be specified in a SPICE file format.

The design characterization tool <NUM> can include a surrogate modeling system <NUM> to build a surrogate model <NUM> that approximates an output response of the circuit design <NUM> to variability of the manufacturing parameters described in the process variation information <NUM>. The surrogate model <NUM>, when simulated with different sets of manufacturing variations, can provide an output response similar to an output response of the circuit design <NUM> simulated with the same sets of the manufacturing variations, and the analog simulation system <NUM> can simulate the surrogate model <NUM> more quickly than the circuit design <NUM>. In some embodiments, the surrogate model <NUM> can be a simple linear regression model, polynomial model, a piece-wise linear regression model, or the like.

The surrogate modeling system <NUM> can receive training samples of a manufacturing variation distribution, for example, from a sampling system <NUM>. The sampling system <NUM> can include a sample generator <NUM> to sample the distribution of values for the manufacturing parameters in the process variation information <NUM>. In some embodiments, each of the training samples can be a Monte Carlo sample randomly drawn from the distribution of values for the manufacturing parameters.

The surrogate modeling system <NUM> can direct the analog simulation system <NUM> to iteratively set the manufacturing parameters of a standard cell design, such as circuit design <NUM>, to correspond to the different training samples and, in a block <NUM> of <FIG>, simulate the standard cell design set with the different training samples utilizing a test bench <NUM>. The test bench <NUM> can define test stimulus, for example, clock signals, activation signals, power signals, control signals, data signals, or the like, that, when grouped, may form test bench transactions capable of prompting operation of the circuit design <NUM> in an analog simulation environment. In some embodiments, the test bench <NUM> can be written in an object-oriented programming language, for example, SystemVerilog or the like, that, when executed during elaboration, can dynamically generate test bench components for verification of the circuit design <NUM>. A methodology library, for example, a Universal Verification Methodology (UVM) library, an Open Verification Methodology (OVM) library, an Advanced Verification Methodology (AVM) library, a Verification Methodology Manual (VMM) library, or the like, can be utilized as a base for creating the test bench <NUM>. The surrogate modeling system <NUM> can generate the surrogate model <NUM> of the standard cell design based, at least in part, on the results of the simulation of the standard cell design set with the different training samples.

The sample generator <NUM>, in a block <NUM> of <FIG>, can also select the samples from the manufacturing variation distribution for simulation of the standard cell design. In some embodiments, the sample generator <NUM> can sample the distribution of values for the manufacturing parameters in the process variation information <NUM>, for example, utilizing a Monte Carlo random sampling process.

The sampling system <NUM> can include an ordering system <NUM>, in a block <NUM> of <FIG>, to order the samples based, at least in part, on the surrogate model for the standard cell design. The ordering system <NUM> can compute predicted outputs by the surrogate model <NUM> having variations set based on the samples and utilize the predicted outputs to order the samples corresponding to the variations. For example, when manufacturing variations described in the samples have more extreme predicted output values, e.g., in one of the tails of a range of an output distribution, the ordering system <NUM> can order those samples ahead of other sample having less extreme predicted output values, e.g., towards the center of the range of an output distribution. By ordering the samples based on the predicted output values from the surrogate model <NUM>, the design characterization tool <NUM> can direct the analog simulation system <NUM> to simulate the surrogate model <NUM> with samples of manufacturing variation more likely to generate simulation results exceeding a predetermined threshold variation, for example, +/- <NUM> sigma deviation.

The surrogate modeling system <NUM> can provide the surrogate model <NUM> to the analog simulation system <NUM> for simulation with ordered samples <NUM> of the manufacturing variation distribution, for example, from the sampling system <NUM>. The design characterization tool <NUM> can include a variation determination system <NUM> to direct the analog simulation system <NUM>, in a block <NUM> of <FIG>, to simulate the surrogate model <NUM> with the ordered samples <NUM> of manufacturing variation and receive back simulation results <NUM>. In some embodiments, the variation determination system <NUM> can provide the analog simulation system <NUM> with separate combinations of the input variables from the ordered samples <NUM> to utilize when simulating the surrogate model <NUM>.

The variation determination system <NUM> can correlate the simulation results <NUM> to the ordered samples <NUM> utilized by the analog simulation system <NUM> used to generate the simulation results and, in a block <NUM> of <FIG>, determine whether to stop simulating the ordered samples <NUM>. In some embodiments, the variation determination system <NUM> can determine whether a set of the worst of the ordered samples <NUM>, for example, samples associated with simulation results <NUM> falling outside of +/- <NUM> sigma deviation, have already been simulated and decide whether to stop simulating more of the ordered samples <NUM> based on the determination. Embodiments of stopping simulation the surrogate model <NUM> with the ordered samples <NUM> will be described below in greater detail with reference to <FIG> and <FIG>.

When, in the block <NUM>, the variation determination system <NUM> determines to not stop simulating, execution returns to the block <NUM>, where the variation determination system <NUM> can continue simulating the surrogate model <NUM> with the ordered samples <NUM> of manufacturing variation and continue to receive corresponding simulation results <NUM>. When, in the block <NUM>, the variation determination system <NUM> determines to stop simulating, execution proceeds to a block <NUM> in Figure <NUM>, where the variation determination system <NUM> can determine a variance measurement for the standard cell design based on the simulation results <NUM> using the ordered samples, which the variation determination system <NUM> can output as a variability characterization <NUM>. In some embodiments, the variation determination system <NUM> can utilize the simulation results <NUM> corresponding to the worst simulated samples, such as those falling outside of +/- <NUM> sigma range, to determine the variability characterization <NUM> for the circuit design <NUM>. The variation determination system <NUM> can specify the variability characterization <NUM> in a Liberty Variability Format (LVF), which can be an extension of a characterized circuit design <NUM> specified in a Liberty format.

<FIG> illustrates a flowchart showing an example confidence interval stopping condition while characterizing manufacturing variability using truncated ordered sample simulation according to various examples. Referring to <FIG>, in a block <NUM>, a computing system implementing an analog simulation tool can simulate a standard cell design utilizing samples from a manufacturing variation distribution. In some embodiments, the computing system implementing the analog simulation tool can simulate a surrogate model of the standard cell design utilizing samples from the manufacturing variation distribution. The analog simulation tool can set combinations of process variables for the standard cell design or the surrogate model to correspond to the samples of the manufacturing variation distribution, and generate simulation results that correspond to the operation of the standard cell design or the surrogate model having been configured according to the samples of the manufacturing variation distribution.

In a block <NUM>, the computing system implementing a design characterization tool can determine whether a preset number of samples have been simulated. When the preset number of samples has not been simulated, execution returns to the block <NUM>, where the analog simulation tool continues to simulate the standard cell design or the surrogate model with the samples.

When the preset number of samples has been simulated, execution can proceed to the block <NUM>, where the computing system implementing the design characterization tool can identify which of the samples correspond to extreme simulated values. In some embodiments, the design characterization tool can identify a preset number of the samples having simulation results at a tail of a distribution of the simulation results. For example, when attempting to obtain a +/- <NUM> sigma deviation in <NUM> samples, the <NUM> samples having the simulation results at the tail of the distribution of the simulation results can be the samples having the extreme simulated values.

In a block <NUM>, the computing system implementing the design characterization tool can estimate an upper boundary of simulation values for the samples remaining to be simulated. In some embodiments, the design characterization tool can estimate the upper boundary for simulation values of the remaining samples by identifying a sample window corresponding to at least a subset of the previously simulated samples. The design characterization tool can identify the simulation results corresponding to the samples in the sample window and calculate a median of the simulation results. The design characterization tool can identify a sample in the middle of the sample window and determine the simulation result associated with the middle sample in the sample window. The design characterization tool can determine a difference between the median value of the simulation results in the sample window and the simulation value of the middle sample, called a maximum difference. When previous sample windows have been considered by the design characterization tool, the design characterization tool can identify the maximum difference as the largest determined difference between the median and middle simulation values for all of those sample windows.

The design characterization tool can also determine a simulation value corresponding to a start of an upper quartile of the sample window. The design characterization tool can combine the simulation value corresponding to the upper quartile with the maximum difference to obtain the estimate of the upper boundary of simulation values for the samples remaining to be simulated.

In a block <NUM>, the computing system implementing the design characterization tool can determine whether the extreme simulated values exceed the estimate of the upper boundary. For example, when attempting to obtain a +/- <NUM> sigma deviation in <NUM> samples, the simulation value corresponding to the <NUM>th most extreme sample can be compared with the upper boundary to determine which one is greater. When the extreme simulation results do not exceed the estimate of the upper boundary, execution can return to the block <NUM>, where the computing system implementing the design characterization tool can simulate a standard cell design utilizing additional samples.

When the extreme simulation results exceed the estimate of the upper boundary, execution can proceed to the block <NUM>, the computing system implementing the design characterization tool can stop simulating the standard cell design or the surrogate model of the standard cell design utilizing the samples. Since the samples have been ordered in an attempt to identify the worst simulation results early in the analog simulation of the samples, the value of the upper boundary relative to the values of the extreme samples can be utilized by the design characterization tool to determine when additional simulation of the standard cell design or the surrogate model of the standard cell design will not generate a simulation result that supplants the identified samples in the block <NUM>. By ceasing the analog simulation of the standard cell design or the surrogate model of the standard cell design early, for example, before all of the samples have been simulated, the design characterization tool can reduce overall simulation time and consumption of processing resources. For example, when attempting to obtain a +/- <NUM> sigma deviation in <NUM> samples, the design characterization tool may be able to stop simulating after <NUM> or so samples, providing an order of magnitude reduction in overall simulation time without jeopardizing an accuracy of the +/- <NUM> sigma deviation determination.

<FIG> illustrates a flowchart showing an example drought stopping condition while characterizing manufacturing variability using truncated ordered sample simulation according to various examples. Referring to <FIG>, in a block <NUM>, a computing system implementing an analog simulation tool can simulate a standard cell design or utilizing samples from a manufacturing variation distribution. In some embodiments, the computing system implementing the analog simulation tool can simulate a surrogate model of the standard cell design utilizing samples from the manufacturing variation distribution. The analog simulation tool can set combinations of process variables for the standard cell design or the surrogate model to correspond to the samples of the manufacturing variation distribution, and generate simulation results that correspond to the operation of the standard cell design or the surrogate model having been configured according to the samples of the manufacturing variation distribution.

In a block <NUM>, the computing system implementing the design characterization tool can determine whether a preset number of samples have been simulated. When the preset number of samples has not been simulated, execution returns to the block <NUM>, where the analog simulation tool continues to simulate the standard cell design or the surrogate model with the samples.

When the preset number of samples has been simulated, execution can proceed to the block <NUM>, the computing system implementing the design characterization tool can identify which of the samples correspond to simulated values falling in a tail of the simulation results. For example, when attempting to obtain a variability characterization of +/- <NUM> sigma deviation in <NUM> samples, the computing system implementing the design characterization tool can identify which of the simulation results fall in a +/- <NUM> sigma deviation, which can correspond to the <NUM> samples having the most extreme simulation results.

In a block <NUM>, the computing system implementing the design characterization tool can determine whether the identified samples have changed, for example, compared to a previous identification of the samples. When the identified samples have changed, execution can proceed to a block <NUM>, where the computing system implementing the design characterization tool can reset a drought counter. The drought counter can store a number corresponding to a number of samples that have been simulated without causing the identified tail samples to change. Execution can then return to the block <NUM>, where the computing system implementing the design characterization tool can simulate a standard cell design utilizing additional samples.

When the identified samples have not changed, execution can proceed to a block <NUM>, where the computing system implementing the design characterization tool can increment a drought counter. The incrementing of the drought counter can indicate that the most recent simulation using one of the samples did not generate a change to the identified tail samples.

In a block <NUM>, the computing system implementing the design characterization tool can determine whether the drought counter value exceeds a threshold value. The drought counter value can correspond to a number of simulations of the standard cell design or corresponding surrogate model with different samples that have occurred since the last change in the tail samples was identified. When the drought counter value does not exceed the threshold, execution can return to the block <NUM>, where the computing system implementing the design characterization tool can simulate a standard cell design utilizing additional samples.

When the drought counter value exceeds the threshold, execution can proceed to the block <NUM>, the computing system implementing the design characterization tool can stop simulating the standard cell design utilizing the samples. By stopping the analog simulation of the standard cell design or corresponding surrogate model after there has been no change in an extreme group of simulation results, such as those simulation results falling in the +/- <NUM> sigma tail of the result distribution, the design characterization tool can determine when additional simulation of the standard cell design or the surrogate model of the standard cell design will not generate a simulation result that supplants an even more extreme group of simulation results, such as those simulation results falling in the +/- <NUM> sigma tail of the result distribution. By ceasing the analog simulation of the standard cell design or the surrogate model of the standard cell design early, for example, before all of the samples have been simulated, the design characterization tool can reduce overall simulation time and consumption of processing resources. For example, when attempting to obtain a +/- <NUM> sigma deviation in <NUM> samples, the design characterization tool may be able to stop simulating after <NUM> or so samples, providing an order of magnitude reduction in overall simulation time without jeopardizing an accuracy of the +/- <NUM> sigma deviation determination. Further, the stopping conditions described with reference to <FIG> and <FIG> can be combined or used together to determine when to stop simulating the standard cell design or the surrogate model with ordered samples.

The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and/or methods described herein may be performed by an apparatus, a device, and/or a system substantially similar to those as described herein and with reference to the illustrated figures.

The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

The processor memory may be integrated together with the processing device, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I/O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine-readable" and may be readable by a processing device.

Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. "Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini-computer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and/or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

A program stored in a computer-readable storage medium may comprise a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries.

While the application describes specific examples of carrying out embodiments of the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the scope of the invention as set forth in the appended claims. For example, while specific terminology has been employed above to refer to design processes, it should be appreciated that various examples of the invention may be implemented using any desired combination of electronic design automation processes.

One of skill in the art will also recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

Claim 1:
A method comprising:
sampling, by a computing system, a distribution of values describing manufacturing variation for an integrated circuit described by a circuit design;
simulating (<NUM>; <NUM>), by an analog simulation system (<NUM>) of the computing system, the circuit design utilizing the samples of the distribution of the values;
determining, by the computing system, when to stop the simulations of the circuit design prior to all of the samples from the distribution having been utilized in the simulations,
wherein determining when to stop the simulations of the circuit design further comprises estimating (<NUM>) an upper boundary for simulation values for the samples that are remaining to be simulated, and stopping (<NUM>) the simulations of the circuit design when the results of the simulations for a current set of the samples exceeds the estimated upper boundary for the simulation values for the samples that are remaining to be simulated; or
wherein determining when to stop the simulations of the circuit design comprises identifying (<NUM>), after each simulation of the circuit design, which of the samples have corresponding simulation values falling in a tail of the simulation results, and stopping (<NUM>) the simulations after a predetermined number of the simulations having occurred without changing the identification of which of the samples have corresponding simulation values falling in a tail of the simulation results; and
utilizing, by the computing system, results of the simulations to characterize operational variation of the circuit design to the manufacturing variation described in the distribution of the values.