Patent Description:
Side walls of semiconductor chips are prone to mechanical and chemical damage during and after separating the semiconductor chips from the semiconductor wafer. In particular, metal plating and/or soldering processes applied after chip separation (e.g. during packaging) may have a negative impact on chip side wall integrity and may, e.g., cause chip-cracks.

<CIT> describes a method of manufacturing a semiconductor chip. The side walls of the chip are coated with an isolation layer by means of anodic oxidation.

<CIT> describes a method including etching trenches through an epitaxial layer and anodizing the structure by bringing an anodizing solution in contact with a heavily doped layer in the trenches.

<CIT> describes a method of forming a semiconductor device including carrying out an anodic oxidation of a surface region of the substrate.

<CIT> describes a method of forming an electrical structure at a main surface of a semiconductor substrate. An anodic oxidation is carried out at a backside region of the semiconductor substrate.

According to an aspect of the disclosure, a method of manufacturing semiconductor chips having a side wall sealing includes forming dicing trenches in a semiconductor wafer. The side walls of the dicing trenches are anodized to generate an anodic oxide layer at the side walls of the dicing trenches, wherein a temperature of an electrolyte during anodizing is equal to or higher than <NUM>. The semiconductor chips are separated from the semiconductor wafer.

It is to be understood that the features of the various exemplary embodiments and examples described herein may be combined with each other, unless specifically noted otherwise.

Wafer dicing is a process to singularize a semiconductor wafer into chips, also referred to as dies in the art. Various techniques have been developed for wafer dicing. In particular the manufacturing of thin chips destined for, e.g., power applications from semiconductor wafers is a challenging task. Conventional dicing methods typically produce unprotected chip edges and may further cause chipping at the edges (side walls) of the separated chips.

Referring to <FIG>, a method of manufacturing semiconductor chips having a side wall sealing is described by way of example. At S1 dicing trenches are formed in a semiconductor wafer. The dicing trenches may, e.g., be formed mechanically, e.g. by blade dicing, chemically, e.g. by etching, and/or by laser beam ablation.

At S2 the side walls of the dicing trenches are anodized to generate an anodic oxide layer at the side walls of the dicing trenches. Anodizing the side walls produces the side wall sealing. As will be described further below, the side wall sealing produced by such electrochemical process has a high quality in terms of uniformity, conformity, and sealing capability.

At S3 the semiconductor chips are separated from the semiconductor wafer. Separating the semiconductor chips from the semiconductor wafer may involve various different techniques, e.g. including thinning, laser-separation, etc..

Referring to <FIG>, the process of anodizing the side walls of dicing trenches at S2 is described in more detail by way of example. In <FIG> a semiconductor wafer <NUM> (of which only a portion is shown in <FIG>) is immersed in an electrolyte <NUM> contained in an electrolytic cell <NUM>. The electrolytic cell <NUM> further contains a cathode <NUM> (negative electrode) and an anode <NUM> (positive electrode), whereat the semiconductor wafer <NUM> is acting as the anode <NUM>.

As already mentioned, dicing trenches <NUM> have been formed in the semiconductor wafer <NUM> before carrying out the anodizing process. The dicing trenches <NUM> may have a depth D (as measured between an upper surface 210A of the semiconductor wafer <NUM> and a bottom surface 220A of the dicing trench <NUM>) of equal to or less than <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>. In particular, D may be equal to or greater than the thickness of the semiconductor chips to be produced from the semiconductor wafer <NUM>.

The semiconductor wafer <NUM> may be front-end processed, i.e. integrated circuits (not shown) may be monolithically integrated in each of the semiconductor wafer regions bordered by the dicing trenches <NUM>. The integrated circuits (IC) may represent power ICs. In particular the ICs may comprise or represent power transistors, power diodes, etc..

Electrodes such as, e.g., a gate electrode <NUM> and/or a source electrode <NUM> may be arranged at the upper surface 210A of the semiconductor wafer <NUM>. It is to be noted that the gate and source electrodes <NUM>, <NUM> depicted in <FIG> are merely an example and other electrodes, such as, e.g., a drain electrode and/or electrodes of logic or analog ICs may be provided at the upper surface 210A of the semiconductor wafer <NUM>.

In the example shown in <FIG>, the electrode(s) (e.g. gate and source electrodes <NUM>, <NUM>) is (are) covered by a mask material <NUM>, e.g. a photoresist.

The mask material <NUM> may cover surface areas of the semiconductor wafer <NUM> which are intended not to be exposed to the electrochemical anodizing process. In the example shown in <FIG>, the mask material <NUM> completely covers the upper surface 210A of the semiconductor wafer <NUM> laterally outside of the dicing trenches <NUM> and may completely cover the electrode(s) (e.g. gate and source electrodes <NUM>, <NUM>) at the upper surface 210A of the semiconductor wafer <NUM>. However, as will be described in more detail further below, it is also possible that the layer of mask material <NUM> ends at a certain offset from the rim of the dicing trenches <NUM> so as to provide for a frame-shaped exposed area at the upper surface 210A of the semiconductor wafer <NUM> adjacent to the rim of the dicing trenches <NUM>.

Apart from covering the upper surface 210A and the electrodes during the anodizing process, the mask material <NUM> may have one or more further functions. According to a first possibility, a mask layer of mask material <NUM> may be generated over the semiconductor wafer <NUM> before forming the dicing trenches <NUM>. The mask layer may then be patterned to expose dicing trench streets on the semiconductor wafer <NUM>. The dicing trenches <NUM> may then be formed by plasma dicing using the patterned mask layer. In this case, the patterned mask layer may also act as a dicing mask.

For instance, plasma dicing may be performed by deep reactive ion etching (DRIE). DRIE is a dry plasma process which can etch very narrow, deep vertical dicing trenches <NUM> into the semiconductor wafer <NUM>.

According to a second possibility, a mask layer of mask material <NUM> may be generated over the semiconductor wafer <NUM> after forming the dicing trenches <NUM>. The mask layer may then be patterned to expose at least the dicing trenches <NUM>. As mentioned, it is also possible that the mask layer is patterned to additionally expose a frame-like area of the upper surface 210A of the semiconductor wafer adjacent to the dicing trenches <NUM>. The patterned mask layer is then used to anodize all exposed surfaces of the semiconductor wafer <NUM> which are not covered by the patterned mask layer. That is, the side walls of the dicing trenches <NUM> and optionally the frame-like areas adjacent dicing trenches <NUM> are anodized by using the patterned mask layer.

Returning to <FIG>, the dicing trenches <NUM> (which, e.g., may have been produced by half-cut blade dicing or plasma dicing) are then anodized to generate an anodic oxide layer <NUM>. The anodic oxide layer <NUM> may partly or completely cover the side walls of the dicing trenches <NUM>.

The anodic oxide layer <NUM> is generated by anodic oxidation of the wafer material. The wafer material may, e.g., be silicon (Si) or other materials such as SiGe, SiC, etc. In the following, without loss of generality and merely for ease of explanation, Si is used as an example for the semiconductor wafer material.

During anodic oxidation, Si-Si bonds of the Si semiconductor wafer <NUM> are broken and replaced by Si-O bonds. The following chemical equation may describe the anodizing of Si:.

Si + <NUM><NUM>O + nh → SiO<NUM> + <NUM>+ + (<NUM>-n)e,.

where h denotes holes, e denotes an electron, and n is an integer.

That is, the direct current applied between the cathode <NUM> and the anode <NUM> passes through the electrolyte <NUM> and releases hydrogen at the cathode <NUM> and oxygen at the exposed upper surface 210A of the semiconductor wafer <NUM> (i.e. at the anode <NUM>). The oxygen creates a build-up of silicon oxide, namely the anodic oxide layer <NUM>. Further, it appears from the chemical equation that anodic oxidation is a hole-driven process.

The electrolyte <NUM> contains water, i.e. is an aqueous solution. In aqueous solutions the anodizing process does not much depend on the dissolved salts in the electrolyte <NUM>. Therefore, a variety of different electrolytes <NUM> may be used, in particular deionized water, HNO<NUM>, H<NUM>PO<NUM>, NH<NUM>OH, etc..

It is to be noted that the anodic oxide layer <NUM> generated by electrochemical anodizing is different in structure from semiconductor oxide layers produced by deposition processes such as, e.g., by pyrolysis of silane, TEOS (tetraethyl orthosilicate) deposition, or LTO (low temperature oxide) deposition. Anodic oxide has a higher density than deposited oxide. Further, the generation process is self-adjusting and highly conformal. This guarantees that the exposed surfaces of the semiconductor wafer <NUM> (and in particular the side walls of the dicing trenches <NUM>) are completely and hermetically sealed without any defects or weak points in the anodic oxide layer <NUM>. Briefly put, the anodized oxide layer <NUM> is different in structure and better in quality than deposited oxide layers.

Further it is to be noted that high temperature oxide generation processes cannot be used to seal the side walls of the dicing trenches <NUM> since the semiconductor wafer <NUM> can no more be heated to high temperatures at that late stage of wafer processing (i.e. after wafer metallization).

Another advantage of anodic oxide over deposited oxide is that anodic oxide is generated selectively, while deposited oxide fully coats the semiconductor wafer <NUM>.

<FIG> schematically illustrates characteristics of the generation of the anodic oxide layer <NUM> in the electrolytic cell <NUM>. The left side diagrams in <FIG> relate to an n-type semiconductor wafer <NUM>, while the right side diagrams relate to a p-type semiconductor wafer <NUM>. Referring to an n-type semiconductor wafer <NUM>, given the semiconductor wafer <NUM> does not have a very high dopant concentration of, e.g., equal to or less than about <NUM><NUM> cm-<NUM> or <NUM><NUM> cm-<NUM>, the anodic oxide layer <NUM> defines a metal-oxide-semiconductor (MOS) structure during anodic oxidation, with the electrolyte representing the metal. After the generation of an initial layer thickness of a few nm of the anodic oxide layer <NUM>, a space charge zone (SCZ) is generated in the n-type semiconductor wafer <NUM> (see (a) and (b) of the left portion of <FIG>), which inhibits further oxidation even if the voltage is increased. Only upon reaching the breakdown voltage, further anodic oxide is generated, however, by an uncontrolled process. Therefore, unlike the case of a p-type semiconductor wafer <NUM> (see (a) and (b) of the right portion of <FIG>) where virtually no SCZ is formed upon initial anodic oxide layer generation, it is difficult to produce anodic oxide layers <NUM> of greater thickness in n-type semiconductor wafers <NUM> having a dopant concentration of, e.g., equal to or less than about <NUM><NUM> cm-<NUM> or <NUM><NUM> cm-<NUM> by anodic oxidation.

The electrochemically generated anodic oxide acts as an insulator between the applied voltage. During the anodizing process, the thinner the anodic oxide layer <NUM> is at a specific location, the higher is the electrical field E at that location. As a result, thinner areas of the anodic oxide layer <NUM> are more strongly anodized, since the process is controlled by the electrical field-driven movement of ions. This self-adjustment of the anodizing process provides for a high conformity (e.g. in thickness and/or structure) of the generated anodic oxide layer <NUM>, which is even better than the conformity of thermal oxides which are generated by a diffusion controlled reaction.

Approaches to produce thicker anodic oxide layers <NUM> in n-type semiconductor wafers <NUM> which do not have a very high dopant concentration are described below.

According to a first approach, the anodic oxide layer formation process may be boosted by implanting an n-type dopant or a p-type dopant into the side walls of the dicing trenches <NUM> before anodizing. This approach is illustrated in <FIG>. The arrows indicate a shallow implantation of a donor (e.g. phosphor, arsenic, antimony, etc.) in the side walls of the dicing trenches <NUM>. The dopant inhibits the formation of a SCZ and thereby allows further anodic oxide growth. An acceptor such as, e.g. boron, may also be used as a p-type dopant.

As it is no more possible to activate the dopants at high temperature, the concentration of the dopants (i.e. the implantation dose) should be relatively high.

Alternatively or in addition, thermal donors may be induced by hydrogen implantation. An advantage of thermal donors is that temperatures of only about <NUM> are sufficient for activation. Such temperatures are compliant with wafer processing at that stage of wafer fabrication, in particular with the front side metallization (electrodes <NUM>, <NUM>) which may have already been applied to the semiconductor wafer <NUM>. Thus, hydrogen implantation (which may also be indicated by the arrows of <FIG>) may be followed by an annealing process at modest temperatures of, e.g., about <NUM>.

As shown in <FIG>, the mask material <NUM> (which may or may not have been previously used for trench dicing) may be used as an implantation mask for one or more of the implantation processes described above. The thickness of the mask layer of mask material <NUM> may be equal to or more than a few <NUM>. Such mask layer thickness is sufficient for plasma dicing and is also sufficient for acting as an implantation mask layer during the implantation process.

The implantation of an n-type dopant or a p-type dopant or hydrogen into the side walls of the dicing trenches <NUM> may not only allow further anodic oxide layer generation, but could, in addition, serve as a field stop region at the semiconductor chip edge. As known in the art, semiconductor chips and, in particular, power semiconductor chips are equipped with a field stop region in order to prevent the generation of an electrical field at the chip edge. Thus, the mask layer of the mask material <NUM> may also be used as the implantation mask for generating the lateral field stop region, thereby avoiding the application of separate masks and further lithography for generating the field stop region.

According to a second approach, the generation of a SCZ in an n-type semiconductor wafer <NUM> could be inhibited by illuminating the side walls of the dicing trenches <NUM> during anodizing. In an n-type semiconductor wafer <NUM>, the oxidation rate will be sensitive to illumination because holes are the minority carrier. Illumination does not affect the oxidation rate when a p-type semiconductor wafer <NUM> is used.

Referring to <FIG>, one or more light sources <NUM> may be accommodated in the electrolytic cell <NUM>. The light source(s) is (are) configured to completely illuminate the side walls of the dicing trenches <NUM>, thereby generating electron-hole pairs in the semiconductor wafer <NUM> in a region adjacent to the side walls. The electron-hole pairs are generated by the photons emitted by the light source(s) and have the effect that the electrical field E is not depleted by the SCZ (compare with left side diagram (d) of <FIG> where the electrical field E is depleted by the SCZ without illumination). This allows the generation of anodic oxide layers <NUM> in n-type doped semiconductor material having a limited dopant concentration of a similar thickness than in p-type semiconductor material or than in n-type semiconductor material of a very high dopant concentration.

The light source(s) <NUM> may be arranged under a short distance above the upper surface 210A of the semiconductor wafer <NUM>. The light source(s) <NUM> may be realized, e.g., by a diode array or any other light emitting device, e.g. by a light emitting foil or by an array of light emitting devices.

In <FIG> the light source(s) <NUM> is (are) located between the cathode <NUM> and the semiconductor wafer <NUM>. However, it is also possible that the light source(s) <NUM> is (are) arranged above the cathode <NUM>, which then may be transparent (e.g. may be formed by a transparent electrically conductive foil or by an electrically conductive mesh).

Though described for the example of n-type semiconductor wafers <NUM> which do not have a very high dopant concentration, the first approach and second approach may, e.g., be applied in general to all semiconductor wafers.

Further, it has been found that anodic oxide layers <NUM> of sufficient thickness can be formed on damaged surfaces of a semiconductor wafer <NUM>, e.g. on a silicon surface that was damaged during the wafer sawing process by, e.g., blade dicing for producing the dicing trenches <NUM>. In this case, no implantation and/or illumination processes are needed for the generation of an anodic oxide layer <NUM> of sufficient thickness. The generation of an anodic oxide layer <NUM> of sufficient thickness on damaged surfaces is also possible even for undoped (i.e. intrinsic) semiconductor wafers <NUM>. In all cases it is possible to combine blade dicing (which produces damaged trench side walls) and the aforementioned implantation and/or illumination processes.

Further, it has been found that for all anodizing processes described herein the temperature during the anodizing treatment plays an important role for the structural quality of the generated anodic oxide layer <NUM>. At a temperature of the electrolyte <NUM> of equal to or higher than <NUM> or <NUM> or <NUM>, the anodizing process provides for a fully closed and sealed anodic oxide layer <NUM> which allows for high quality side wall sealing, while the anodic oxide layer <NUM> may become increasingly porous at electrolyte temperatures lower than <NUM>.

Throughout this description, the anodic oxide layer <NUM> may have a thickness of equal to or greater than <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>. The anodic oxide layer <NUM> may comprise or be of SiO<NUM> or another oxide composition generated by anodizing the semiconductor bulk material of the semiconductor wafer <NUM> at the side walls of the dicing trenches <NUM>.

<FIG> illustrates exemplary processes which could be used in a method of manufacturing semiconductor chips having an anodic oxide layer <NUM> as a side wall sealing. At <NUM> a so-called half-cut dicing (e.g. blade dicing or plasma-dicing) is carried out. Dicing trenches <NUM> and optional electrode(s) <NUM>, <NUM> are depicted in <FIG>.

Subsequently, at <NUM> the side walls of the dicing trenches <NUM> are anodized. To build-up the anodic oxide layer <NUM>, any of the aforementioned processes may be used. Briefly, at 620_1 the half-cut diced semiconductor wafer <NUM> is illustrated (as it is already shown at <NUM>). At 620_2 a mask layer of mask material <NUM> was generated over the semiconductor wafer <NUM> and had then been patterned to expose the dicing trenches <NUM>. In the example shown in <FIG>, not only the dicing trenches <NUM> are exposed but also a certain frame-like surface area of the semiconductor wafer <NUM> adjacent to the dicing trenches <NUM>. The patterned mask layer may completely cover the electrode(s) <NUM>, <NUM> (or, in general, the metallization) on the semiconductor wafer <NUM>. The process shown at 620_2 may also be referred to as "lithography on kerf". As mentioned above, the patterned mask layer of mask material <NUM> may further be used as an implantation mask.

At 620_3 the side walls of the dicing trenches <NUM> are anodized and the anodic oxide layers <NUM> at the side walls of the dicing trenches <NUM> are formed. Any of the above specified methods could be used. Further to 620_3 the mask material <NUM> may then be removed.

It is to be noted that the exemplary processes 620_1, 620_2, 620_3 shown at <NUM> may be replaced or supplemented by any of the aforementioned processes and variations thereof to arrive at a semiconductor wafer <NUM> with dicing trenches <NUM> having side walls which are coated by a low temperature anodic oxide layer <NUM>.

At <NUM> the dicing trenches <NUM> are (optionally) filled with an organic resin <NUM>. The organic resin <NUM> may form a continuous layer covering the upper surface 210A of the semiconductor wafer <NUM>. Filling the dicing trenches <NUM> with organic resin <NUM> may be followed by carrying out a lithography process on the layer of organic resin <NUM>, if desired.

At <NUM> the semiconductor wafer <NUM> may be attached to a temporary carrier <NUM>. The temporary carrier <NUM> may, e.g., include a holder or support member 642_1 (e.g. a glass plate) and an adhesive film 642_2.

The temporary carrier <NUM> with the attached semiconductor wafer <NUM> may then be flipped upside down. At <NUM> the semiconductor wafer <NUM> may be thinned at a semiconductor wafer surface 210B opposite the dicing trenches <NUM>, i.e. thinning may be carried out from the backside of the semiconductor wafer <NUM>. Thinning may include grinding and/or etching. The thinning process is illustrated by arrows at <NUM>. As a result of the thinning process, chips embedded in an organic resin matrix are generated. That is, the thinning process may completely separate the semiconductor wafer <NUM> into single semiconductor chips which are, however, still connected to one another by the organic resin matrix.

The process from <NUM> to <NUM> may be referred to as a dicing before grinding (DBG) process.

At <NUM> an electrode metal material <NUM> may be deposited on the backside (e.g. on the lower surface 210B) of the semiconductor wafer <NUM> (which now, however, may also be referred to as an artificial wafer since it may comprise separated semiconductor chips embedded in the organic resin matrix). The deposition of electrode metal material <NUM> may be carried out by electroless or galvanic plating. By way of example, a Ti/Cu seed layer <NUM> may be applied to the surface of the (artificial) semiconductor wafer <NUM> and copper or any other electrode metal may be deposited on the seed layer <NUM> to provide for the layer of electrode metal material <NUM>.

At <NUM> the layer of electrode metal material <NUM> may be structured. Structuring may be accomplished by any available process, e.g. etching.

It is to be noted that the exemplary steps illustrated at <NUM> and <NUM> may be replaced or supplemented by other method steps such as, e.g., deposition of solder material over the (artificial) semiconductor wafer <NUM>. In this case, the solder material may be directly deposited (e.g. printed) on the backside of the (artificial) semiconductor wafer <NUM> to form a patterned electrode metal material layer as shown at <NUM>. For instance, solder materials which are configured for diffusion soldering, such as, e.g., AuSn or other solder materials may be used.

During the application of the electrode metal material <NUM> and/or solder material at <NUM>, <NUM>, the side walls of the dicing trenches <NUM> are protected not only by the (optional) organic resin <NUM> but in addition by the anodic oxide layer <NUM>. While the organic resin <NUM> typically does not provide for a reliable protection of the side walls of the dicing trenches <NUM>, an effective side wall sealing is obtained by the anodic oxide layer <NUM>. Therefore, the risk of contaminating the side walls of the semiconductor chips by metal (e.g. solder) during or after the process of chip manufacturing is greatly reduced or completely ruled out.

The temporary carrier <NUM> may then be removed from the (artificial) semiconductor wafer <NUM>. The (artificial) semiconductor wafer <NUM> may be flipped upside down and placed on a support member <NUM>. A laser beam <NUM> may be used to separate the (artificial) semiconductor wafer <NUM> into individual semiconductor chips by organic resin laser separation. At <NUM> the left side fill of organic resin <NUM> is shown to be separated by the laser beam <NUM> while the right side fill of the organic resin <NUM> is still intact.

<FIG> is a magnified view of the encircled detail in <FIG>at <NUM>. As apparent from <FIG>, the semiconductor wafer <NUM> is now separated in single semiconductor chips comprising an anodic oxide layer <NUM> side wall protection and an (optional) organic resin <NUM> side wall protection.

Referring to <FIG>, an exemplary semiconductor chip <NUM> comprises an anodic oxide layer <NUM> at its side walls. The semiconductor chip <NUM> may be provided with backside electrodes formed by the electrode metal material <NUM> and/or with front side electrodes (such as, e.g., a gate electrode <NUM> and/or a source electrode <NUM>). The thickness T of the anodic oxide layer <NUM> may be equal to or greater than <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>. The thickness D of the semiconductor chip <NUM> may be equal to or less than <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>. The semiconductor chip <NUM> may be a power semiconductor chip, e.g. power transistor or power diode.

As shown in <FIG>, the anodic oxide layer <NUM> may completely cover the entire surface of the side walls of the semiconductor chip <NUM>.

Referring to <FIG>, a semiconductor chip <NUM> may be designed identical to the semiconductor chip <NUM> except that the semiconductor chip <NUM> is provided with regions <NUM> adjacent to the side walls of the semiconductor chip <NUM> that are n-doped or p-doped. As mentioned previously, n-type dopant implantation and/or p-type dopant implantation at the side walls of the semiconductor chip <NUM> may provide for a sufficient thickness T of the anodic oxide layer <NUM> in case of an n-type semiconductor wafer (which does not have a very high dopant concentration) and may, optionally, further be used as a field stop for device fabrication. The regions <NUM> may also be intrinsic and damaged by blade-cutting.

Further, <FIG> illustrates the deposition of solder material <NUM> over the backside and/or front side of the semiconductor chip <NUM>. The side walls of the semiconductor chip <NUM> are effectively sealed against solder material contamination during this process or subsequent processes such as, e.g., solder reflow.

The following examples pertain to further aspects of the disclosure:.

Example <NUM> is a method of manufacturing semiconductor chips having a side wall sealing, the method including forming dicing trenches in a semiconductor wafer; anodizing side walls of the dicing trenches to generate an anodic oxide layer at the side walls of the dicing trenches, wherein a temperature of an electrolyte during anodizing is equal to or higher than <NUM>; and separating the semiconductor chips from the semiconductor wafer.

In Example <NUM>, the subject matter of Example <NUM> can optionally include implanting an n-type dopant or a p-type dopant into the side walls of the dicing trenches before anodizing.

In Example <NUM>, the subject matter of Example <NUM> or <NUM> can optionally include implanting hydrogen into the side walls of the dicing trenches before anodizing.

In Example <NUM>, the subject matter of any of the preceding Examples can optionally include illuminating the side walls of the dicing trenches during anodizing.

In Example <NUM>, the subject matter of any of the preceding Examples can optionally include wherein the temperature of the electrolyte during anodizing is equal to or higher than <NUM> or <NUM>.

In Example <NUM>, the subject matter of any of the preceding Examples can optionally include wherein separating comprises thinning the semiconductor wafer after anodizing at a semiconductor wafer surface opposite the dicing trenches.

In Example <NUM>, the subject matter of any of the preceding Examples can optionally further include filling the dicing trenches with an organic resin after anodizing.

In Example <NUM>, the subject matter of any of the preceding Examples can optionally further include wherein separating comprises singulating the semiconductor chips by laser cutting through the organic resin.

In Example <NUM>, the subject matter of any of the preceding Examples can optionally include depositing an electrode metal material or a solder material over the semiconductor wafer after anodizing.

In Example <NUM>, the subject matter of any of the preceding Examples can optionally include wherein forming the dicing trenches comprises blade dicing or plasma dicing.

In Example <NUM>, the subject matter of any of the preceding Examples can optionally include generating a mask layer over the semiconductor wafer after forming the dicing trenches; patterning the mask layer to expose the dicing trenches; and anodizing side walls of the dicing trenches by using the patterned mask layer.

Claim 1:
A method of manufacturing semiconductor chips having a side wall sealing, the method comprising:
forming dicing trenches (<NUM>) in a semiconductor wafer (<NUM>);
anodizing side walls of the dicing trenches (<NUM>) to generate an anodic oxide layer (<NUM>) at the side walls of the dicing trenches (<NUM>), wherein a temperature of an electrolyte during anodizing is equal to or higher than <NUM>; and
separating the semiconductor chips from the semiconductor wafer (<NUM>).