Patent Description:
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

Memory devices may be coupled to a host (e.g., a host computing device) to store data, commands, and/or instructions for use by the host while the computer or electronic system is operating. For example, data, commands, and/or instructions can be transferred between the host and the memory device(s) during operation of a computing or other electronic system.

<CIT> discloses memory-addressed mapping in a semiconductor apparatus to define a memory-mapped input/output region for a physical memory space with a direct mapping between addresses for the physical memory space and logical block addresses for a persistent storage media.

<CIT> discloses a hybrid storage system with multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution.

<CIT> discloses systems and methods for enhancing the handling of interrupts in a virtual computing environment.

In a first aspect of the invention there is provided an apparatus comprising logic circuitry according to independent claim <NUM>.

In a second aspect of the invention there is provided a method according to independent claim <NUM>.

Further features of embodiments of the invention are defined in the dependent claims.

Systems, apparatuses, and methods related to hierarchical memory are described herein. A hierarchical memory apparatus in accordance with the present disclosure can be part of a memory system that can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example apparatus includes logic circuitry configured to receive a command indicating that an access to a base address register coupled to the logic circuitry has occurred. The command can be indicative of a data access involving a persistent memory device, a non-persistent memory device, or both. The logic circuitry can determine that the access command corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device, generate, responsive to receipt of the access command and the determination, an interrupt signal, and cause the interrupt signal to be asserted on a host coupleable to the logic circuitry as part of the operation to divert data from the non-persistent memory device to the persistent memory device.

Computing systems utilize various types of memory resources during operation. For example, a computing system may utilize a combination of volatile (e.g., random-access memory) memory resources and non-volatile (e.g., storage) memory resources during operation. In general, volatile memory resources can operate at much faster speeds than non-volatile memory resources and can have longer lifespans than non-volatile memory resources; however, volatile memory resources are typically more expensive than non-volatile memory resources. As used herein, a volatile memory resource may be referred to in the alternative as a "non-persistent memory device" while a non-volatile memory resource may be referred to in the alternative as a "persistent memory device.

However, a persistent memory device can more broadly refer to the ability to access data in a persistent manner. As an example, in the persistent memory context, the memory device can store a plurality of logical to physical mapping or translation data and/or lookup tables in a memory array in order to track the location of data in the memory device, separate from whether the memory is non-volatile. Further, a persistent memory device can refer to both the non-volatility of the memory in addition to using that non-volatility by including the ability to service commands for successive processes (e.g., by using logical to physical mapping, look-up tables, etc.).

These characteristics can necessitate trade-offs in computing systems in order to provision a computing system with adequate resources to function in accordance with ever-increasing demands of consumers and computing resource providers. For example, in a multi-user computing network (e.g., a cloud-based computing system deployment, a software defined data center, etc.), a relatively large quantity of volatile memory may be provided to provision virtual machines running in the multi-user network. However, by relying on volatile memory to provide the memory resources to the multi-user network, as is common in some approaches, costs associated with provisioning the network with memory resources may increase, especially as users of the network demand larger and larger pools of computing resources to be made available.

Further, in approaches that rely on volatile memory to provide the memory resources to provision virtual machines in a multi-user network, once the volatile memory resources are exhausted (e.g., once the volatile memory resources are allocated to users of the multi-user network), additional users may not be added to the multi-user network until additional volatile memory resources are available or added. This can lead to potential users being turned away, which can result in a loss of revenue that could be generated if additional memory resources were available to the multi-user network.

Volatile memory resources, such as dynamic random-access memory (DRAM) tend to operate in a deterministic manner while non-volatile memory resources, such as storage class memories (e.g., NAND flash memory devices, solid-state drives, resistance variable memory devices, etc.) tend to operate in a non-deterministic manner. For example, due to error correction operations, encryption operations, RAID operations, etc. that are performed on data retrieved from storage class memory devices, an amount of time between requesting data from a storage class memory device and the data being available can vary from read to read, thereby making data retrieval from the storage class memory device non-deterministic. In contrast, an amount of time between requesting data from a DRAM device and the data being available can remain fixed from read to read, thereby making data retrieval from a DRAM device deterministic.

In addition, because of the distinction between the deterministic behavior of volatile memory resources and the non-deterministic behavior of non-volatile memory resources, data that is transferred to and from the memory resources generally traverses a particular interface (e.g., a bus) that is associated with the type of memory being used. For example, data that is transferred to and from a DRAM device is typically passed via a double data rate (DDR) bus, while data that is transferred to and from a NAND device is typically passed via a peripheral component interconnect express (PCI-e) bus. As will be appreciated, examples of interfaces over which data can be transferred to and from a volatile memory resource and a non-volatile memory resource are not limited to these specific enumerated examples, however.

Because of the different behaviors of non-volatile memory device and volatile memory devices, some approaches opt to store certain types of data in either volatile or non-volatile memory. This can mitigate issues that can arise due to, for example, the deterministic behavior of volatile memory devices compared to the non-deterministic behavior of non-volatile memory devices. For example, computing systems in some approaches store small amounts of data that are regularly accessed during operation of the computing system in volatile memory devices while data that is larger or accessed less frequently is stored in a non-volatile memory device. However, in multi-user network deployments, the vast majority of data may be stored in volatile memory devices. In contrast, embodiments herein can allow for data storage and retrieval from a non-volatile memory device deployed in a multi-user network.

As described herein, some embodiments of the present disclosure are directed to computing systems in which data from a non-volatile, and hence, non-deterministic, memory resource is passed via an interface that is restricted to use by a volatile and deterministic memory resource in other approaches. For example, in some embodiments, data may be transferred to and from a non-volatile, non-deterministic memory resource, such as a NAND flash device, a resistance variable memory device, such as a phase change memory device and/or a resistive memory device (e.g., a three-dimensional Crosspoint (3D XP) memory device), a solid-sate drive (SSD), a self-selecting memory (SSM) device, etc. via an interface such as a DDR interface that is reserved for data transfer to and from a volatile, deterministic memory resource in some approaches. Accordingly, in contrast to approaches in which volatile, deterministic memory devices are used to provide main memory to a computing system, embodiments herein can allow for non-volatile, non-deterministic memory devices to be used as at least a portion of the main memory for a computing system.

In some embodiments, the data may be intermediately transferred from the non-volatile memory resource to a cache (e.g., a small static random-access memory (SRAM) cache) or buffer and subsequently made available to the application that requested the data. By storing data that is normally provided in a deterministic fashion in a non-deterministic memory resource and allowing access to that data as described here, computing system performance may be improved by, for example, allowing for a larger amount of memory resources to be made available to a multi-user network at a substantially reduced cost in comparison to approaches that operate using volatile memory resources.

In order to facilitate embodiments of the present disclosure, visibility to the non-volatile memory resources may be obfuscated to various devices of the computing system in which the hierarchical memory system is deployed. For example, host(s), a network interface card, which may be referred to herein in the alternative as a network interface controller (NIC), virtual machine(s), etc. that are deployed in the computing system or multi-user network may be unable to distinguish between whether data is stored by a volatile memory resource or a non-volatile memory resource of the computing system. For example, hardware circuitry may be deployed in the computing system that can register addresses that correspond to the data in such a manner that the host(s), NIC(s), virtual machine(s), etc. are unable to distinguish whether the data is stored by volatile or non-volatile memory resources.

As described in more detail herein, a hierarchical memory system may include hardware circuitry (e.g., logic circuitry) that can receive redirected data requests, register an address in the logic circuitry associated with the requested data (despite the hardware circuitry not being backed up by its own memory resource to store the data), and map, using the logic circuitry, the address registered in the logic circuitry to a physical address corresponding to the data in a non-volatile memory device.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and structural changes may be made without departing from the scope of the present disclosure.

As used herein, designators such as "N," etc., particularly with respect to reference numerals in the drawings, indicate that a number of the particular feature so designated can be included. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" can include both singular and plural referents, unless the context clearly dictates otherwise. In addition, "a number of," "at least one," and "one or more" can refer to one or more of such things (e.g., a number of memory banks can refer to one or more memory banks), whereas a "plurality of' is intended to refer to more than one of such things.

Furthermore, the words "can" and "may" are used throughout this application in a permissive sense (e.g., having the potential to, being able to), not in a mandatory sense (e.g., must). The term "include," and derivations thereof, means "including, but not limited to. " The terms "coupled" and "coupling" mean to be directly or indirectly connected physically or for access to and movement (transmission) of commands and/or data, as appropriate to the context. The terms "data" and "data values" are used interchangeably herein and can have the same meaning, as appropriate to the context.

The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify an element or component in the figure. A group or plurality of similar elements or components may generally be referred to herein with a single element number. For example, a plurality of reference elements <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-N (e.g., <NUM>-<NUM> to <NUM>-N) may be referred to generally as <NUM>. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportion and/or the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present disclosure and should not be taken in a limiting sense.

<FIG> is a functional block diagram in the form of a computing system <NUM> including a hierarchical memory apparatus <NUM> in accordance with a number of embodiments of the present disclosure. The hierarchical memory apparatus <NUM> can be part of a computing system, as will be further described herein. As used herein, an "apparatus" can refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuitry, a die or dice, a module or modules, a device or devices, or a system or systems, for example. In some embodiments, the hierarchical memory apparatus <NUM> can be provided as a field programmable gate array (FPGA), application-specific integrated circuit (ASIC), a number of discrete circuit components, etc., and can be referred to herein in the alternative as "logic circuitry.

The hierarchical memory apparatus <NUM> can, as illustrated in <FIG>, include a memory resource <NUM>, which can include a read buffer <NUM>, a write buffer <NUM>, and/or an input/output (I/O) device access component <NUM>. In some embodiments, the memory resource <NUM> can be a random-access memory resource, such as a block RAM, which can allow for data to be stored within the hierarchical memory apparatus <NUM> in embodiments in which the hierarchical memory apparatus <NUM> is a FPGA. However, embodiments are not so limited, and the memory resource <NUM> can comprise various registers, caches, memory arrays, latches, and SRAM, DRAM, EPROM, or other suitable memory technologies that can store data such as bit strings that include registered addresses that correspond to physical locations in which data is stored external to the hierarchical memory apparatus <NUM>. The memory resource <NUM> is internal to the hierarchical memory apparatus <NUM> and is generally smaller than memory that is external to the hierarchical memory apparatus <NUM>, such as persistent and/or non-persistent memory resources that can be external to the hierarchical memory apparatus <NUM>.

The read buffer <NUM> can include a portion of the memory resource <NUM> that is reserved for storing data that has been received by the hierarchical memory apparatus <NUM> but has not been processed by the hierarchical memory apparatus <NUM>. For instance, the read buffer <NUM> can store data that has been received by the hierarchical memory apparatus <NUM> in association with (e.g., during and/or as a part of) a sense (e.g., read) operation being performed on memory (e.g., persistent memory) that is external to the hierarchical memory apparatus <NUM>. In some embodiments, the read buffer <NUM> can be around <NUM> Kilobytes (KB) in size, although embodiments are not limited to this particular size. The read buffer <NUM> can buffer data that is to be registered in one of the address registers <NUM>-<NUM> to <NUM>-N.

The write buffer <NUM> can include a portion of the memory resource <NUM> that is reserved for storing data that is awaiting transmission to a location external to the hierarchical memory apparatus <NUM>. For instance, the write buffer <NUM> can store data that is to be transmitted to memory (e.g., persistent memory) that is external to the hierarchical memory apparatus <NUM> in association with a program (e.g., write) operation being performed on the external memory. In some embodiments, the write buffer <NUM> can be around <NUM> Kilobytes (KB) in size, although embodiments are not limited to this particular size. The write buffer <NUM> can buffer data that is registered in one of the address registers <NUM>-<NUM> to <NUM>-N.

The I/O access component <NUM> can include a portion of the memory resource <NUM> that is reserved for storing data that corresponds to access to a component external to the hierarchical memory apparatus <NUM>, such as the I/O device <NUM> and <NUM> illustrated in <FIG> and <FIG>, herein. The I/O access component <NUM> can store data corresponding to addresses of the I/O device, which can be used to read and/or write data to and from the I/O device. In addition, the I/O access component <NUM> can, in some embodiments, receive, store, and/or transmit data corresponding to a status of a hypervisor (e.g., the hypervisor <NUM> illustrated in <FIG>), as described in more detail in connection with <FIG>, herein.

The hierarchical memory apparatus <NUM> can further include a memory access multiplexer (MUX) <NUM>, a state machine <NUM>, and/or a hierarchical memory controller <NUM> (or, for simplicity, "controller"). As shown in <FIG>, the hierarchical memory controller <NUM> can include a plurality of address registers <NUM>-<NUM> to <NUM>-N and/or an interrupt component <NUM>. The memory access MUX <NUM> can include circuitry that can comprise one or more logic gates and can be configured to control data and/or address bussing for the hierarchical memory apparatus <NUM>. For example, the memory access MUX <NUM> can transfer messages to and from the memory resource <NUM>, as well as communicate with the hierarchical memory controller <NUM> and/or the state machine <NUM>, as described in more detail below.

In some embodiments, the memory access MUX <NUM> can redirect incoming messages and/or commands from a host (e.g., a host computing device, virtual machine, etc.) received to the hierarchical memory apparatus <NUM>. For example, the MUX <NUM> can redirect an incoming message corresponding to an access (e.g., read) or program (e.g., write) request from an input/output (I/O) device (e.g., the I/O device <NUM> or <NUM> illustrated in <FIG> and <FIG>, herein) to one of the address registers (e.g., the address register <NUM>-N, which can be a BAR4 region of the hierarchical memory controller <NUM>, as described below) to the read buffer <NUM> and/or the write buffer <NUM>.

In addition, the memory access MUX <NUM> can redirect requests (e.g., read requests, write requests) received by the hierarchical memory apparatus <NUM>. In some embodiments, the requests can be received by the hierarchical memory apparatus <NUM> from a hypervisor (e.g., the hypervisor <NUM> illustrated in <FIG>, herein), a bare metal server, or host computing device communicatively coupled to the hierarchical memory apparatus <NUM>. Such requests can be redirected by the memory access MUX <NUM> from the read buffer <NUM>, the write buffer <NUM>, and/or the I/O access component <NUM> to an address register (e.g., the address register <NUM>-<NUM>, which can be a BAR2 region of the hierarchical memory controller <NUM>, as described below).

The memory access MUX <NUM> can redirect such requests as part of an operation to determine an address in the address register(s) <NUM> that is to be accessed. In some embodiments, the memory access MUX <NUM> can redirect such requests as part of an operation to determine an address in the address register(s) that is to be accessed in response to assertion of a hypervisor interrupt (e.g., an interrupt asserted to a hypervisor coupled to the hierarchical memory apparatus <NUM> that is generated by the interrupt component <NUM>).

In response to a determination that the request corresponds to data associated with an address being written to a location external to the hierarchical memory apparatus <NUM> (e.g., to a persistent memory device such as the persistent memory device <NUM> or <NUM> illustrated in <FIG> and <FIG>, herein), the memory access MUX <NUM> can facilitate retrieval of the data, transfer of the data to the write buffer <NUM>, and/or transfer of the data to the location external to the hierarchical memory apparatus <NUM>. In response to a determination that the request corresponds to data being read from a location external to the hierarchical memory apparatus <NUM> (e.g., from the persistent memory device), the MUX <NUM> can facilitate retrieval of the data, transfer of the data to the read buffer <NUM>, and/or transfer of the data or address information associated with the data to a location internal to the hierarchical memory apparatus <NUM>, such as the address register(s) <NUM>.

As a non-limiting example, if the hierarchical memory apparatus <NUM> receives a read request from the I/O device, the memory access MUX <NUM> can facilitate retrieval of data from a persistent memory device via the hypervisor by selecting the appropriate messages to send from the hierarchical memory apparatus <NUM>. For example, the memory access MUX <NUM> can facilitate generation of an interrupt using the interrupt component <NUM>, cause the interrupt to be asserted on the hypervisor, buffer data received from the persistent memory device into the read buffer <NUM>, and/or respond to the I/O device with an indication that the read request has been fulfilled. In a non-limiting example in which the hierarchical memory apparatus <NUM> receives a write request from the I/O device, the memory access MUX <NUM> can facilitate transfer of data to a persistent memory device via the hypervisor by selecting the appropriate messages to send from the hierarchical memory apparatus <NUM>. For example, the memory access MUX <NUM> can facilitate generation of an interrupt using the interrupt component <NUM>, cause the interrupt to be asserted on the hypervisor, buffer data to be transferred to the persistent memory device into the write buffer <NUM>, and/or respond to the I/O device with an indication that the write request has been fulfilled. Examples of such retrieval and transfer of data in response to receipt of a read and write request, respectively, will be further described herein.

The state machine <NUM> can include one or more processing devices, circuit components, and/or logic that are configured to perform operations on an input and produce an output. In some embodiments, the state machine <NUM> can be a finite state machine (FSM) or a hardware state machine that can be configured to receive changing inputs and produce a resulting output based on the received inputs. For example, the state machine <NUM> can transfer access info (e.g., "I/O ACCESS INFO") to and from the memory access MUX <NUM>, as well as interrupt configuration information (e.g., "INTERRUPT CONFIG") and/or interrupt request messages (e.g., "INTERRUPT REQUEST") to and from the hierarchical memory controller <NUM>. In some embodiments, the state machine <NUM> can further transfer control messages (e.g., "MUX CTRL") to and from the memory access multiplexer <NUM>.

The ACCESS INFO message can include information corresponding to a data access request received from an I/O device external to the hierarchical memory apparatus <NUM>. In some embodiments, the ACCESS INFO can include logical addressing information that corresponds to data that is to be stored in a persistent memory device or addressing information that corresponds to data that is to be retrieved from the persistent memory device.

The INTERRUPT CONFIG message can be asserted by the state machine <NUM> on the hierarchical memory controller <NUM> to configure appropriate interrupt messages to be asserted external to the hierarchical memory apparatus <NUM>. For example, when the hierarchical memory apparatus <NUM> asserts an interrupt on a hypervisor coupled to the hierarchical memory apparatus <NUM> as part of fulfilling a redirected read or write request, the INTERRUPT CONFIG message can be generated by the state machine <NUM> to generate an appropriate interrupt message based on whether the operation is an operation to retrieve data from a persistent memory device or an operation to write data to the persistent memory device.

The INTERRUPT REQUEST message can be generated by the state machine <NUM> and asserted on the interrupt component <NUM> to cause an interrupt message to be asserted on the hypervisor (or bare metal server or other computing device). As described in more detail herein, the interrupt <NUM> can be asserted on the hypervisor to cause the hypervisor to prioritize data retrieval or writing of data to the persistent memory device as part of operation of a hierarchical memory system.

The MUX CTRL message(s) can be generated by the state machine <NUM> and asserted on the memory access MUX <NUM> to control operation of the memory access MUX <NUM>. In some embodiments, the MUX CTRL message(s) can be asserted on the memory access MUX <NUM> by the state machine <NUM> (or vice versa) as part of performance of the memory access MUX <NUM> operations described above.

The hierarchical memory controller <NUM> can include a core, such as an integrated circuit, chip, system-on-a-chip, or combinations thereof. In some embodiments, the hierarchical memory controller <NUM> can be a peripheral component interconnect express (PCIe) core. As used herein, a "core" refers to a reusable unit of logic, processor, and/or co-processors that receive instructions and perform tasks or actions based on the received instructions.

The hierarchical memory controller <NUM> can include address registers (e.g., a base address register) <NUM>-<NUM> to <NUM>-N and/or an interrupt component <NUM>. The address registers <NUM>-<NUM> to <NUM>-N can be base address registers (BARs) that can store memory addresses used by the hierarchical memory apparatus <NUM> or a computing system (e.g., the computing system <NUM> or <NUM> illustrated in <FIG> and <FIG>, herein). At least one of the address registers (e.g., the address register <NUM>-<NUM>) can store memory addresses that provide access to the internal registers of the hierarchical memory apparatus <NUM> from an external location such as the hypervisor <NUM> illustrated in <FIG>.

A different address register (e.g., the address register <NUM>-<NUM>) can be used to store addresses that correspond to interrupt control, as described in more detail herein. In some embodiments, the address register <NUM>-<NUM> can map direct memory access (DMA) read and DMA write control and/or status registers. For example, the address register <NUM>-<NUM> can include addresses that correspond to descriptors and/or control bits for DMA command chaining, which can include the generation of one or more interrupt messages that can be asserted to a hypervisor as part of operation of a hierarchical memory system, as described in connection with <FIG>, herein.

Yet another one of the address registers (e.g., the address register <NUM>-<NUM>) can store addresses that correspond to access to and from a hypervisor (e.g., the hypervisor <NUM> illustrated in <FIG>, herein). In some embodiments, access to and/or from the hypervisor can be provided via an Advanced extensible Interface (AXI) DMA associated with the hierarchical memory apparatus <NUM>. In some embodiments, the address register can map addresses corresponding to data transferred via a DMA (e.g., an AXI DMA) of the hierarchical memory apparatus <NUM> to a location external to the hierarchical memory apparatus <NUM>.

In some embodiments, at least one address register (e.g., the address register <NUM>-N) can store addresses that correspond to I/O device (e.g., the I/O device <NUM>/<NUM> illustrated in <FIG>/<FIG>) access information (e.g., access to the hierarchical memory apparatus <NUM>). The address register <NUM>-N can store addresses that are bypassed by DMA components associated with the hierarchical memory apparatus <NUM>. The address register <NUM>-N can be provided such that addresses mapped thereto are not "backed up" by a physical memory location of the hierarchical memory apparatus <NUM>. That is, in some embodiments, the hierarchical memory apparatus <NUM> can be configured with an address space that stores addresses (e.g., logical addresses) that correspond to a persistent memory device and/or data stored in the persistent memory device (e.g., the persistent memory device <NUM> or <NUM> illustrated in <FIG> and <FIG>), and not to data stored by the hierarchical memory apparatus <NUM>. Each respective address can correspond to a different location in the persistent memory device and/or the location of a different portion of the data stored in the persistent memory device. For example, the address register <NUM>-N can be configured as a virtual address space that can store logical addresses that correspond to the physical memory locations (e.g., in a memory device) to which data could be programed or in which data is stored.

In some embodiments, the address register <NUM>-N can include a quantity of address spaces that correspond to a size of a memory device (e.g., the persistent memory device <NUM> or <NUM> illustrated in <FIG> and <FIG>, herein). For example, if the memory device contains one terabyte of storage, the address register <NUM>-N can be configured to have an address space that can include one terabyte of address space. However, as described above, the address register <NUM>-N does not actually include one terabyte of storage and instead is configured to appear to have one terabyte of storage space.

As an example, hierarchical memory apparatus <NUM> (e.g., memory access MUX <NUM> and/or state machine <NUM>) can receive a command indicating that an access to a base register coupled to the state machine <NUM> (e.g., logic circuitry included in the state machine) has occurred. In some examples, the logic circuitry of the state machine <NUM> can be resident on a controller (e.g., the hierarchical memory controller <NUM>). In other examples, the logic circuitry of the state machine <NUM> can be external to the controller <NUM>. The command can be indicative of data access involving a persistent memory device, a non-persistent memory device, or both. In some embodiments, the persistent memory device can be external to the hierarchical memory apparatus <NUM>. For instance, the persistent memory device can be persistent memory device 316or <NUM> illustrated in <FIG> and <FIG>. However, in some embodiments, the persistent memory device can be included in (e.g., internal to) the hierarchical memory apparatus <NUM>.

Hierarchical memory apparatus <NUM> can receive the command, for example, from memory management circuitry via an interface (e.g., from memory management circuitry <NUM> or <NUM> via interface <NUM> or <NUM> illustrated in <FIG> and <FIG>, herein). The command can be, for example, a redirected request from an I/O device (e.g., I/O device <NUM> or <NUM> illustrated in <FIG> and <FIG>, herein).

In response to receiving the command, the state machine <NUM> can determine that the access command corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device. The address in the persistent memory device corresponding to the portion of data (e.g., the location of the data in the persistent memory device) using address register <NUM>-N. For instance, memory access MUX <NUM> and/or state machine <NUM> can access register <NUM>-N to retrieve (e.g., capture) the address from register <NUM>-N. Hierarchical memory apparatus <NUM> (e.g., memory access MUX <NUM> and/or state machine <NUM>) can also detect access to the I/O device in response to receiving the access command, and receive (e.g., capture) I/O device access information corresponding to the access command from the I/O device, including for instance, virtual I/O device access information. The I/O device access information can be stored in register <NUM>-N and/or I/O access component <NUM> (e.g., the virtual I/O device access information can be stored in I/O access component <NUM>). Further, in some embodiments, hierarchical memory apparatus <NUM> can associate information with the portion of data that indicates the portion of data is inaccessible by a non-persistent memory device (e.g., non-persistent memory device <NUM>/<NUM> illustrated in <FIG> and <FIG>, herein).

The hierarchical memory apparatus <NUM> (e.g., the memory access MUX <NUM> and/or state machine <NUM>) can then generate a request to access (e.g., read) the portion of the data. The request can include the address in the persistent memory device determined to correspond to the data (e.g., the address indicating the location of the data in the persistent memory device). Along with the request, hierarchical memory apparatus <NUM> (e.g., memory access MUX <NUM> and/or state machine <NUM>) can also generate, responsive to the receipt of the access command, an interrupt signal (e.g., message) using address register <NUM>-<NUM>. For instance, memory access MUX <NUM> and/or state machine <NUM> generates, in the present invention, the interrupt signal by accessing address register <NUM> and using interrupt component <NUM>.

Hierarchical memory apparatus <NUM> (e.g., MUX <NUM> and/or state machine <NUM>) can then send the interrupt signal and the request to access the portion of the data to the persistent memory device. The MUX <NUM> and/or the state machine <NUM> can cause the interrupt signal to be asserted on a host coupleable to the logic circuitry (e.g., the state machine <NUM>) as part of the operation to divert data from the non-persistent memory device to the persistent memory device. For instance, the interrupt signal can be sent, by the hierarchical memory apparatus <NUM> (e.g., memory access MUX <NUM> and/or state machine <NUM>) as part of the request to access data from the non-persistent memory device to the persistent memory device.

In embodiments in which the persistent memory device is external to the hierarchical memory apparatus <NUM>, the interrupt signal and the request to access data from the non-persistent memory device to the persistent memory device can be sent via the interface through which the access command to divert data from the non-persistent memory device to the persistent memory device was received (e.g., via interface <NUM> or <NUM> illustrated in <FIG> and <FIG>, herein). As an additional example, in embodiments in which the persistent memory device is included in the hierarchical memory apparatus <NUM>, the interrupt signal can be sent via the interface, while the request to access data from the non-persistent memory device to the persistent memory device can be sent directly to the persistent memory device. Further, hierarchical memory apparatus <NUM> (e.g., memory access MUX <NUM> and/or state machine <NUM>) can also send, via the interface, the I/O device access information from register <NUM>-N and/or virtual I/O device access information from I/O access component <NUM> as part of the request.

After sending the interrupt signal and the request to access the base address register, hierarchical memory apparatus <NUM> can receive the portion of the data from (e.g., read from) the persistent memory device. For instance, in embodiments in which the persistent memory device is external to hierarchical memory apparatus <NUM>, the data can be received from the persistent memory device via the interface, and in embodiments in which the persistent memory device is included in the hierarchical memory apparatus <NUM>, the data can be received directly from the persistent memory device. After receiving the portion of the data, hierarchical memory apparatus <NUM> can send the data to the I/O device (e.g., I/O device <NUM> or <NUM> illustrated in <FIG> and <FIG>, herein). Further, hierarchical memory apparatus <NUM> can store the data in read buffer <NUM> (e.g., prior to sending the data to the I/O device).

Although not explicitly shown in <FIG>, the hierarchical memory apparatus <NUM> can be coupled to a host computing system. In some embodiments, the host can be communicatively coupled to a hypervisor. The host computing system can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The host and the hierarchical memory apparatus <NUM> can be, for instance, a server system and/or a high-performance computing (HPC) system and/or a portion thereof. In some embodiments, the computing system can have a Von Neumann architecture, however, embodiments of the present disclosure can be implemented in non-Von Neumann architectures, which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

<FIG> is a functional block diagram of a hierarchical memory apparatus <NUM> in accordance with a number of embodiments of the present disclosure. Hierarchical memory apparatus <NUM> can be part of a computing system, and/or can be provided as an FPGA, an ASIC, a number of discrete circuit components, etc., in a manner analogous to hierarchical memory apparatus <NUM> previously described in connection with <FIG>.

The hierarchical memory apparatus <NUM> can, as illustrated in <FIG>, include a memory resource <NUM>, which can include a data buffer <NUM> and/or an input/output (I/O) device access component <NUM>. Memory resource <NUM> can be analogous to memory resource <NUM> previously described in connection with <FIG>, except that data buffer <NUM> can replace read buffer <NUM> and write buffer <NUM>. For instance, the functionality previously described in connection with read buffer <NUM> and write buffer <NUM> can be combined into that of data buffer <NUM>. In some embodiments, the data buffer <NUM> can be around <NUM> KB in size, although embodiments are not limited to this particular size.

The memory access MUX <NUM> can include circuitry analogous to that of memory access MUX <NUM> previously described in connection with <FIG>, and can redirect incoming messages, commands, and/or requests (e.g., read and/or write requests), received by the hierarchical memory apparatus <NUM> (e.g., from a host, an I/O device, or a hypervisor), in a manner analogous to that previously described for memory access MUX <NUM>. For example, the memory access MUX <NUM> can redirect such requests as part of an operation to determine an address in the address register(s) <NUM> that is to be accessed, as previously described in connection with <FIG>. For instance, in response to a determination that the request corresponds to data associated with an address being written to a location external to the hierarchical memory apparatus <NUM>, the memory access MUX <NUM> can facilitate retrieval of the data, transfer of the data to the data buffer <NUM>, and/or transfer of the data to the location external to the hierarchical memory apparatus <NUM>, as previously described in connection with <FIG>. Further, in response to a determination that the request corresponds to data being read from a location external to the hierarchical memory apparatus <NUM>, the memory access MUX <NUM> can facilitate retrieval of the data, transfer of the data to the data buffer <NUM>, and/or transfer of the data or address information associated with the data to a location internal to the hierarchical memory apparatus <NUM>, such as the address register(s) <NUM>, as previously described in connection with <FIG>.

The state machine <NUM> can be coupled to the controller <NUM> and can include one or more processing devices, circuit components, and/or logic that are configured to perform operations on an input and produce an output in a manner analogous to that of the state machine <NUM> previously described in connection with <FIG>. For example, the state machine <NUM> can transfer access info (e.g., "I/O ACCESS INFO") and control messages (e.g., "MUX CTRL") to and from the memory access multiplexer <NUM>, and/or interrupt request messages (e.g., "INTERRUPT REQUEST") to and from the hierarchical memory controller <NUM>, as previously described in connection with <FIG>. However, in contrast to the state machine <NUM>, it is noted that the state machine <NUM> may not transfer interrupt configuration information (e.g., "INTERRUPT CONFIG") to and from controller <NUM>.

The hierarchical memory controller <NUM> can include a core, in a manner analogous to that of the controller <NUM> previously described in connection with <FIG>. In some embodiments, the hierarchical memory controller <NUM> can be a PCIe core, in a manner analogous to the controller <NUM>.

The hierarchical memory controller <NUM> can include address registers <NUM>-<NUM> to <NUM>-N and/or an interrupt component <NUM>. The address registers <NUM>-<NUM> to <NUM>-N can be BARs that can store memory addresses used by the hierarchical memory apparatus <NUM> or a computing system (e.g., the computing system <NUM>/<NUM> illustrated in <FIG> and <FIG>, herein). The controller <NUM> can comprise the BAR and be coupled to a persistent memory device.

At least one of the address registers (e.g., the address register <NUM>-<NUM>) can store memory addresses that provide access to the internal registers of the hierarchical memory apparatus <NUM> from an external location such as the hypervisor <NUM> illustrated in <FIG>, in a manner analogous to that of the address register <NUM>-<NUM> previously described in connection with <FIG>. Yet another one of the address registers (e.g., the address register <NUM>-<NUM>) can store addresses that correspond to access to and from a hypervisor, in a manner analogous to that of address register <NUM>-<NUM> previously described in connection with <FIG>. Further, at least one address register (e.g., the address register <NUM>-N) can store addresses and include address spaces in a manner analogous to that of address register <NUM>-N previously described in connection with <FIG>.

The state machine <NUM> can receive a command indicating that an access to a register <NUM> (e.g., a BAR) has occurred, the command can be indicative of a data access involving the persistent memory device, and/or the non-persistent memory device, which can be coupled to the controller <NUM>. The state machine <NUM> can determine that the access command corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device.

As shown in <FIG> (and in contrast to hierarchical memory apparatus <NUM>), hierarchical memory apparatus <NUM> can include a clear interrupt register <NUM> and a hypervisor done register <NUM>. Clear interrupt register <NUM> can store an interrupt signal generated by interrupt component <NUM> as part of a request to read or write data, as previously described herein, and the hypervisor done register <NUM> can provide an indication (e.g., to the state machine <NUM>) that the hypervisor (e.g., hypervisor <NUM> illustrated in <FIG>) is accessing the internal registers of hierarchical memory apparatus <NUM> to map the addresses to read or write the data, as previously described herein. Once the read or write request has been completed, the interrupt signal can be cleared from register <NUM>, and the hypervisor done register <NUM> can provide an indication (e.g., to state machine <NUM>) that the hypervisor is no longer accessing the internal registers of hierarchical memory apparatus <NUM>.

Although not explicitly shown in <FIG>, the hierarchical memory apparatus <NUM> can be coupled to a host computing system, in a manner analogous to that described for hierarchical memory apparatus <NUM>. The host can be coupled to a hypervisor. The host and the hierarchical memory apparatus <NUM> can be, for instance, a server system and/or a HPC system and/or a portion thereof, as described in connection with <FIG>. The state machine <NUM> can generate an interrupt signal responsive to the receipt of the access command and the determination that the access command corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device.

The state machine <NUM> can cause the interrupt signal to be asserted on a host couplable to the state machine <NUM> as part of the operation to divert data from the non-persistent memory device to the persistent memory device. Further, the state machine <NUM> can receive an indication that the data was received by the host. For example, because the host can be coupled to a hypervisor, the hypervisor done register <NUM> can transmit a signal to the state machine <NUM> that the hypervisor is no longer accessing the address register <NUM>.

As shown in <FIG> (and in contrast to hierarchical memory apparatus <NUM>), hierarchical memory apparatus <NUM> can include an access hold component <NUM>. Access hold component <NUM> can limit the address space of address register <NUM>-N. For instance, access hold component <NUM> can limit the addresses of address register <NUM>-N to lower than <NUM>.

<FIG> is a functional block diagram in the form of a computing system <NUM> including a hierarchical memory apparatus <NUM> in accordance with a number of embodiments of the present disclosure. Hierarchical memory apparatus <NUM> can be analogous to the hierarchical memory apparatus <NUM> and/or <NUM> illustrated in <FIG> and <FIG>, respectively. In addition, the computing system <NUM> can include an input/output (I/O) device <NUM>, a persistent memory device <NUM>, a non-persistent memory device <NUM>, an intermediate memory component <NUM>, and a memory management component <NUM>. Communication between the hierarchical memory apparatus <NUM>, the I/O device <NUM> and the persistent memory device <NUM>, the non-persistent memory device <NUM>, and the memory management component <NUM> can be facilitated via an interface <NUM>.

The I/O device <NUM> can be a device that is configured to provide direct memory access via a physical address and/or a virtual machine physical address. In some embodiments, the I/O device <NUM> can be a NIC, a storage device, a graphics rendering device, or other I/O device. The I/O device <NUM> can be a physical I/O device or the I/O device <NUM> can be a virtualized I/O device <NUM>. For example, in some embodiments, the I/O device <NUM> can be a physical card that is physically coupled to a computing system via a bus or interface such as a PCIe interface or other suitable interface. In embodiments in which the I/O device <NUM> is a virtualized I/O device <NUM>, the virtualized I/O device <NUM> can provide I/O functionality in a distributed manner. In some embodiments, a NIC can operate as an input/output coupled to a state machine (e.g., the state machine <NUM> or <NUM> of <FIG> and <FIG>). The state machine, via the NIC, can transmit a command indicative of the data access involving the persistent memory device, the non-persistent memory device, or both.

The persistent memory device <NUM> can include a number of arrays of memory cells. The arrays can be flash arrays with a NAND architecture, for example. However, embodiments are not limited to a particular type of memory array or array architecture. The memory cells can be grouped, for instance, into a number of blocks including a number of physical pages. A number of blocks can be included in a plane of memory cells and an array can include a number of planes.

The persistent memory device <NUM> can include volatile memory and/or non-volatile memory. In a number of embodiments, the persistent memory device <NUM> can include a multi-chip device. A multi-chip device can include a number of different memory types and/or memory modules. For example, a memory system can include non-volatile or volatile memory on any type of a module. In embodiments in which the persistent memory device <NUM> includes non-volatile memory, the persistent memory device <NUM> can be a flash memory device such as NAND or NOR flash memory devices.

Embodiments are not so limited, however, and the persistent memory device <NUM> can include other non-volatile memory devices such as non-volatile random-access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM), "emerging" memory devices such as resistance variable memory devices (e.g., resistive and/or phase change memory devices such as a 3D Crosspoint (3D XP) memory device), memory devices that include an array of self-selecting memory (SSM) cells, etc., or combinations thereof. A resistive and/or phase change array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, resistive and/or phase change memory devices can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. In contrast to flash-based memories, self-selecting memory cells can include memory cells that have a single chalcogenide material that serves as both the switch and storage element for the memory cell.

The persistent memory device <NUM> can provide a storage volume for the computing system <NUM> and can therefore be used as additional memory or storage throughout the computing system <NUM>, main memory for the computing system <NUM>, or combinations thereof. Embodiments are not limited to a particular type of memory device, however, and the persistent memory device <NUM> can include RAM, ROM, SRAM DRAM, SDRAM, PCRAM, RRAM, and flash memory, among others. Further, although a single persistent memory device <NUM> is illustrated in <FIG>, embodiments are not so limited, and the computing system <NUM> can include one or more persistent memory devices <NUM>, each of which may or may not have a same architecture associated therewith. As a non-limiting example, in some embodiments, the persistent memory device <NUM> can comprise two discrete memory devices that are different architectures, such as a NAND memory device and a resistance variable memory device.

The non-persistent memory device <NUM> can include volatile memory, such as an array of volatile memory cells. In a number of embodiments, the non-persistent memory device <NUM> can include a multi-chip device. A multi-chip device can include a number of different memory types and/or memory modules. In some embodiments, the non-persistent memory device <NUM> can serve as the main memory for the computing system <NUM>. For example, the non-persistent memory device <NUM> can be a dynamic random-access (DRAM) memory device that is used to provide main memory to the computing system <NUM>. Embodiments are not limited to the non-persistent memory device <NUM> comprising a DRAM memory device, however, and in some embodiments, the non-persistent memory device <NUM> can include other non-persistent memory devices such as RAM, SRAM DRAM, SDRAM, PCRAM, and/or RRAM, among others.

The non-persistent memory device <NUM> can store data that can be requested by, for example, a host computing device as part of operation of the computing system <NUM>. For example, when the computing system <NUM> is part of a multi-user network, the non-persistent memory device <NUM> can store data that can be transferred between host computing devices (e.g., virtual machines deployed in the multi-user network) during operation of the computing system <NUM>.

In some approaches, non-persistent memory such as the non-persistent memory device <NUM> can store all user data accessed by a host (e.g., a virtual machine deployed in a multi-user network). For example, due to the speed of non-persistent memory, some approaches rely on non-persistent memory to provision memory resources for virtual machines deployed in a multi-user network. However, in such approaches, costs can be become an issue due to non-persistent memory generally being more expensive than persistent memory (e.g., the persistent memory device <NUM>).

In contrast, as described in more detail below, embodiments herein can allow for at least some data that is stored in the non-persistent memory device <NUM> to be stored in the persistent memory device <NUM>. This can allow for additional memory resources to be provided to a computing system <NUM>, such as a multi-user network, at a lower cost than approaches that rely on non-persistent memory for user data storage.

The computing system <NUM> can include a memory management component <NUM>, which can be communicatively coupled to the non-persistent memory device <NUM> and/or the interface <NUM>. In some embodiments, the memory management component <NUM> can be an input/output memory management unit (IO MMU) that can communicatively couple a direct memory access bus such as the interface <NUM> to the non-persistent memory device <NUM>. Embodiments are not so limited, however, and the memory management component <NUM> can be other types of memory management hardware that facilitates communication between the interface <NUM> and the non-persistent memory device <NUM>.

The memory management component <NUM> can map device-visible virtual addresses to physical addresses. For example, the memory management component <NUM> can map virtual addresses associated with the I/O device <NUM> to physical addresses in the non-persistent memory device <NUM> and/or the persistent memory device <NUM>. In some embodiments, mapping the virtual entries associated with the I/O device <NUM> can be facilitated by the read buffer, write buffer, and/or I/O access buffer illustrated in <FIG>, herein, or the data buffer and/or I/O access buffer illustrated in <FIG>, herein.

In some embodiments, the memory management component <NUM> can read a virtual address associated with the I/O device <NUM> and/or map the virtual address to a physical address in the non-persistent memory device <NUM> or to an address in the hierarchical memory apparatus <NUM>. In embodiments in which the memory management component <NUM> maps the virtual I/O device <NUM> address to an address in the hierarchical memory apparatus <NUM>, the memory management component <NUM> can redirect a read request (or a write request) received from the I/O device <NUM> to the hierarchical memory apparatus <NUM>, which can store the virtual address information associated with the I/O device <NUM> read or write request in an address register (e.g., the address register <NUM>-N) of the hierarchical memory apparatus <NUM>, as previously described in connection with <FIG> and <FIG>. In some embodiments, the address register <NUM>-N can be a particular base address register of the hierarchical memory apparatus <NUM>, such as a BAR4 address register.

The redirected read (or write) request can be transferred from the memory management component <NUM> to the hierarchical memory apparatus <NUM> via the interface <NUM>. In some embodiments, the interface <NUM> can be a PCIe interface and can therefore pass information between the memory management component <NUM> and the hierarchical memory apparatus <NUM> according to PCIe protocols. Embodiments are not so limited, however, and in some embodiments the interface <NUM> can be an interface or bus that functions according to another suitable protocol.

After the virtual NIC address is stored in the hierarchical memory apparatus <NUM>, the data corresponding to the virtual NIC address can be written to the persistent memory device <NUM>. For example, the data corresponding to the virtual NIC address stored in the hierarchical memory apparatus <NUM> can be stored in a physical address location of the persistent memory device <NUM>. In some embodiments, transferring the data to and/or from the persistent memory device <NUM> can be facilitated by a hypervisor, as described in connection with <FIG>, herein.

When the data is requested by, for example, a host computing device, such as a virtual machine deployed in the computing system <NUM>, the request can be redirected from the I/O device <NUM>, by the memory management component <NUM>, to the hierarchical memory apparatus <NUM>. Because the virtual NIC address corresponding to the physical location of the data in the persistent memory device <NUM> is stored in the address register <NUM>-N of the hierarchical memory apparatus <NUM>, the hierarchical memory apparatus <NUM> can facilitate retrieval of the data from the persistent memory device <NUM>, as previously described herein. For instance, hierarchical memory apparatus <NUM> can facilitate retrieval of the data from the persistent memory device <NUM> in connection with a hypervisor, as described in more detail in connection with <FIG>, herein.

In some embodiments, when data that has been stored in the persistent memory device <NUM> is transferred out of the persistent memory device <NUM> (e.g., when data that has been stored in the persistent memory device <NUM> is requested by a host computing device), the data can be transferred to the intermediate memory component <NUM> and/or the non-persistent memory device <NUM> prior to being provided to the host computing device. For example, because data transferred to the host computing device can be transferred in a deterministic fashion (e.g., via a DDR interface), the data can be transferred temporarily to a memory that operates using a DDR bus, such as the intermediate memory component <NUM> and/or the non-persistent memory device <NUM>, prior to a data request being fulfilled.

<FIG> is another functional block diagram in the form of a computing system <NUM> including a hierarchical memory apparatus <NUM> in accordance with a number of embodiments of the present disclosure. As shown in <FIG>, the computing system <NUM> can include a hierarchical memory apparatus <NUM>, which can be analogous to the hierarchical memory apparatus <NUM>, <NUM>, and/or <NUM> illustrated in <FIG>, <FIG>, and <FIG>. In addition, the computing system <NUM> can include an I/O device <NUM>, a persistent memory device <NUM>, a non-persistent memory device <NUM>, an intermediate memory component <NUM>, a memory management component <NUM>, and a hypervisor <NUM>.

In some embodiments, the computing system <NUM> can be a multi-user network, such as a software defined data center, cloud computing environment, etc. In such embodiments, the computing system can be configured to have one or more virtual machines <NUM> running thereon. For example, in some embodiments, one or more virtual machines <NUM> can be deployed on the hypervisor <NUM> and can be accessed by users of the multi-user network.

The I/O device <NUM>, the persistent memory device <NUM>, the non-persistent memory device <NUM>, the intermediate memory component <NUM>, and the memory management component <NUM> can be analogous to the I/O device <NUM>, the persistent memory device <NUM>, the non-persistent memory device <NUM>, the intermediate memory component <NUM>, and the memory management component <NUM> illustrated in <FIG>. Communication between the hierarchical memory apparatus <NUM>, the I/O device <NUM> and the persistent memory device <NUM>, the non-persistent memory device <NUM>, the hypervisor <NUM>, and the memory management component <NUM> can be facilitated via an interface <NUM>, which can be analogous to the interface <NUM> illustrated in <FIG>.

As described above in connection with <FIG>, the memory management component <NUM> can cause a read request or a write request associated with the I/O device <NUM> to be redirected to the hierarchical memory apparatus <NUM>. The hierarchical memory apparatus <NUM> can generate and/or store a logical address corresponding to the requested data. As described above, the hierarchical memory apparatus <NUM> can store the logical address corresponding to the requested data in a base address register, such as the address register <NUM>-N of the hierarchical memory apparatus <NUM>.

As shown in <FIG>, the hypervisor <NUM> can be in communication with the hierarchical memory apparatus <NUM> and/or the I/O device <NUM> via the interface <NUM>. The hypervisor <NUM> can transmit data between the hierarchical memory apparatus <NUM> via a NIC access component (e.g., the NIC access component <NUM> or <NUM> illustrated in <FIG> and <FIG>) of the hierarchical memory apparatus <NUM>. In addition, the hypervisor <NUM> can be in communication with the persistent memory device <NUM>, the non-persistent memory device <NUM>, the intermediate memory component <NUM>, and the memory management component <NUM>. The hypervisor can be configured to execute specialized instructions to perform operations and/or tasks described herein.

For example, the hypervisor <NUM> can execute instructions to monitor data traffic and data traffic patterns to determine whether data should be stored in the non-persistent memory device <NUM> or if the data should be transferred to the persistent memory device <NUM>. That is, in some embodiments, the hypervisor <NUM> can execute instructions to learn user data request patterns over time and selectively store portions of the data in the non-persistent memory device <NUM> or the persistent memory device <NUM> based on the patterns. This can allow for data that is accessed more frequently to be stored in the non-persistent memory device <NUM> while data that is accessed less frequently to be stored in the persistent memory device <NUM>.

Because a user can access recently used or viewed data more frequently than data that has been used less recently or viewed less recently, the hypervisor can execute specialized instructions to cause the data that has been used or viewed less recently to be stored in the persistent memory device <NUM> and/or cause the data that has been accessed or viewed more recently in the non-persistent memory device <NUM>. In a non-limiting example, a user can view photographs on social media that have been taken recently (e.g., within a week, etc.) more frequently than photographs that have been taken less recently (e.g., a month ago, a year ago, etc.). Based on this information, the hypervisor <NUM> can execute specialized instructions to cause the photographs that were viewed or taken less recently to be stored in the persistent memory device <NUM>, thereby reducing an amount of data that is stored in the non-persistent memory device <NUM>. This can reduce an overall amount of non-persistent memory that is necessary to provision the computing system <NUM>, thereby reducing costs and allowing for access to the non-persistent memory device <NUM> to more users.

In operation, the computing system <NUM> can be configured to intercept a data request from the I/O device <NUM> and redirect the request to the hierarchical memory apparatus <NUM>. In some embodiments, the hypervisor <NUM> can control whether data corresponding to the data request is to be stored in (or retrieved from) the non-persistent memory device <NUM> or in the persistent memory device <NUM>. For example, the hypervisor <NUM> can execute instructions to selectively control if the data is stored in (or retrieved from) the persistent memory device <NUM> or the non-persistent memory device <NUM>.

As part of controlling whether the data is stored in (or retrieved from) the persistent memory device <NUM> and/or the non-persistent memory device <NUM>, the hypervisor <NUM> can cause the memory management component <NUM> to map logical addresses associated with the data to be redirected to the hierarchical memory apparatus <NUM> and stored in the address registers <NUM> of the hierarchical memory apparatus <NUM>. For example, the hypervisor <NUM> can execute instructions to control read and write requests involving the data to be selectively redirected to the hierarchical memory apparatus <NUM> via the memory management component <NUM>.

The memory management component <NUM> can map contiguous virtual addresses to underlying fragmented physical addresses. Accordingly, in some embodiments, the memory management component <NUM> can allow for virtual addresses to be mapped to physical addresses without the requirement that the physical addresses are contiguous. Further, in some embodiments, the memory management component <NUM> can allow for devices that do not support memory addresses long enough to address their corresponding physical memory space to be addressed in the memory management component <NUM>.

Due to the non-deterministic nature of data transfer associated with the persistent memory device <NUM>, the hierarchical memory apparatus <NUM> can, in some embodiments, be configured to inform the computing system <NUM> that a delay in transferring the data to or from the persistent memory device <NUM> can be incurred. As part of initializing the delay, the hierarchical memory apparatus <NUM> can provide page fault handling for the computing system <NUM> when a data request is redirected to the hierarchical memory apparatus <NUM>. In some embodiments, the hierarchical memory apparatus <NUM> (e.g., a state machine <NUM> or <NUM> of <FIG> and <FIG>) can generate and assert an interrupt to the hypervisor <NUM>, as previously described herein, to initiate an operation to transfer data into or out of the persistent memory device <NUM>. For example, due to the non-deterministic nature of data retrieval and storage associated with the persistent memory device <NUM>, the hierarchical memory apparatus <NUM> (e.g., and/or a state machine <NUM> or <NUM> of <FIG> and <FIG>) can generate a hypervisor interrupt <NUM> when a transfer of the data that is stored in the persistent memory device <NUM> is requested.

In response to the page fault interrupt generated by the hierarchical memory apparatus <NUM>, the hypervisor <NUM> can retrieve information corresponding to the data from the hierarchical memory apparatus <NUM> (e.g., and/or the state machine <NUM> or <NUM> of <FIG> and <FIG>). For example, the hypervisor <NUM> can receive NIC access data from the hierarchical memory apparatus, which can include logical to physical address mappings corresponding to the data that are stored in the address registers <NUM> of the hierarchical memory apparatus <NUM>, as previously described herein.

Once the data has been stored in the persistent memory device <NUM>, a portion of the non-persistent memory device <NUM> (e.g., a page, a block, etc.) can be marked as inaccessible by the hierarchical memory apparatus <NUM>, as previously described herein, so that the computing system <NUM> does not attempt to access the data from the non-persistent memory device <NUM>. This can allow a data request to be intercepted with a page fault, which can be generated by the hierarchical memory apparatus <NUM> and asserted to the hypervisor <NUM> when the data that has been stored in the persistent memory device <NUM> is requested by the I/O device <NUM>.

In contrast to approaches in which a page fault exception is raised in response to an application requesting access to a page of memory that is not mapped by a memory management unit (e.g., the memory management component <NUM>), in embodiments of the present disclosure, the page fault described above can be generated by the hierarchical memory apparatus <NUM> (e.g., and/or the state machine <NUM> or <NUM> of <FIG> and <FIG>) in response to the data being mapped in the memory management component <NUM> to the hierarchical memory apparatus <NUM>, which, in turn maps the data to the persistent memory device <NUM>.

In some embodiments, the intermediate memory component <NUM> can be used to buffer data that is stored in the persistent memory device <NUM> in response to a data request initiated by the I/O device <NUM>. In contrast to the persistent memory device <NUM>, which can pass data via a PCIe interface, the intermediate memory component <NUM> can employ a DDR interface to pass data. Accordingly, in some embodiments, the intermediate memory component <NUM> can operate in a deterministic fashion. For example, in some embodiments, data requested that is stored in the persistent memory device <NUM> can be temporarily transferred from the persistent memory device <NUM> to the intermediate memory component <NUM> and subsequently transferred to a host computing device via a DDR interface coupling the intermediate memory component <NUM> to the I/O device <NUM>.

In some embodiments, the intermediate memory component can comprise a discrete memory component (e.g., an SRAM cache) deployed in the computing system <NUM>. However, embodiments are not so limited and, in some embodiments, the intermediate memory component <NUM> can be a portion of the non-persistent memory device <NUM> that can be allocated for use in transferring data from the persistent memory device <NUM> in response to a data request.

In a non-limiting example, memory management circuitry (e.g., the memory management component <NUM>) can be coupled to the hierarchical memory component <NUM> (e.g., logic circuitry of a state machine <NUM> or <NUM> of <FIG> and <FIG>). The memory management circuitry can be configured to receive a request to write data having a corresponding virtual NIC address associated therewith to a non-persistent memory device (e.g., the non-persistent memory device <NUM>). The memory management circuitry can be further configured to redirect the request to write the data to the logic circuitry, based, at least in part, on characteristics of the data. The characteristics of the data can include how frequently the data is requested or accessed, an amount of time that has transpired since the data was last accessed or requested, a type of data (e.g., whether the data corresponds to a particular file type such as a photograph, a document, an audio file, an application file, etc.), among others.

In some embodiments, the memory management circuitry can be configured to redirect the request to the logic circuitry (e.g., the logic circuitry of a state machine <NUM> or <NUM> of <FIG> and <FIG>) based on commands generated by and/or instructions executed by the hypervisor <NUM>. For example, as described above, the hypervisor <NUM> can execute instructions to control whether data corresponding to a data request (e.g., a data request generated by the I/O device <NUM>) is to be stored in the persistent memory device <NUM> or the non-persistent memory device <NUM>.

In some embodiments, the hypervisor <NUM> can facilitate redirection of the request by writing addresses (e.g., logical addresses) to the memory management circuitry. For example, if the hypervisor <NUM> determines that data corresponding to a particular data request is to be stored in (or retrieved from) the persistent memory device <NUM>, the hypervisor <NUM> can cause an address corresponding to redirection of the request to be stored by the memory management circuitry such that the data request is redirected to the logic circuitry.

Upon receipt of the redirected request, the logic circuitry (e.g., the logic circuitry of a state machine <NUM> or <NUM> of <FIG> and <FIG>) can be configured to determine (e.g., generate) an address corresponding to the data in response to receipt of the redirected request and/or store the address in an address register <NUM> within the logic circuitry, as previously described herein. In some embodiments, the logic circuitry can be configured to associate an indication with the data that indicates that the data is inaccessible to the non-persistent memory device <NUM> based on receipt of the redirected request, as previously described herein.

The logic circuitry can be configured to cause the data to be written to a persistent memory device (e.g., the persistent memory device <NUM>) based, at least in part, on receipt of the redirected request. In some embodiments, the logic circuitry can be configured to generate an interrupt signal and assert the interrupt signal to a hypervisor (e.g., the hypervisor <NUM>) coupled to the logic circuitry as part of causing the data to be written to the persistent memory device <NUM>, as previously described herein. As described above, the persistent memory device <NUM> can comprise a 3D XP memory device, an array of self-selecting memory cells, a NAND memory device, or other suitable persistent memory, or combinations thereof.

In some embodiments, the logic circuitry can be configured to receive a redirected request from the memory management circuitry to retrieve the data from the persistent memory device <NUM>, transfer a request to retrieve the data from the persistent memory device <NUM> to hypervisor <NUM>, and/or assert an interrupt signal to the hypervisor <NUM> as part of the request to retrieve the data from the persistent memory device <NUM>, as previously described herein. The hypervisor <NUM> can be configured to retrieve the data from the persistent memory device <NUM> and/or transfer the data to the non-persistent memory device <NUM>. Once the data has been retrieved from the persistent memory device <NUM>, the hypervisor <NUM> can be configured to cause an updated address associated with the data to be transferred to the memory management circuitry <NUM>.

In another non-limiting example, the computing system <NUM> can be a multi-user network such as a software-defined data center, a cloud computing environment, etc. The multi-user network can include a pool of computing resources that include a non-persistent memory device <NUM> and a persistent memory device <NUM>. The multi-user network can further include an interface <NUM> coupled to hierarchical memory component <NUM> (e.g., logic circuitry) comprising a plurality of address registers <NUM>. In some embodiments, the multi-user network can further include a hypervisor <NUM> coupled to the interface <NUM>.

The hypervisor <NUM> can be configured to receive a request to access data corresponding to the non-persistent memory component <NUM>, determine that the data is stored in the persistent memory device, and cause the request to access the data to be redirected to the logic circuitry. The request to access the data can be a request to read the data from the persistent memory device or the non-persistent memory device or a request to write the data to the persistent memory device or the non-persistent memory device.

In some embodiments, the logic circuitry can be configured to transfer a request to the hypervisor <NUM> to access the data from the persistent memory device <NUM> in response to the determination that the data is stored in the persistent memory device <NUM>. The logic circuitry can be configured to assert an interrupt to the hypervisor as part of the request to the hypervisor <NUM> to access the data corresponding to the persistent memory device <NUM>, as previously described herein.

The hypervisor <NUM> can be configured to cause the data to be accessed using the persistent memory device <NUM> based on the request received from the logic circuitry. As described above, the persistent memory device <NUM> can comprise a resistance variable memory device such as a resistive memory, a phase change memory, an array of self-selecting memory cells, or combinations thereof. In some embodiments, the hypervisor <NUM> can be configured to cause the data to be transferred to a non-persistent memory device <NUM> as part of causing the data to be accessed using the persistent memory device <NUM>.

The hypervisor <NUM> can be further configured to update information stored in a memory management component <NUM> associated with the multi-user network in response to causing the data to be accessed using the persistent memory device <NUM>. For example, the hypervisor <NUM> can be configured to cause updated virtual addresses corresponding to the data to be stored in the memory management component <NUM>.

The multi-user network can, in some embodiments, include an I/O device <NUM> coupled to the logic circuitry. In such embodiments, the logic circuitry can be configured to send a notification to the I/O device <NUM> in response to the hypervisor <NUM> causing the data to be accessed using the persistent memory device <NUM>.

<FIG> is a flow diagram representing an example method <NUM> for a hierarchical memory apparatus in accordance with a number of embodiments of the present disclosure. The hierarchical memory apparatus can be, for example, hierarchical memory apparatus <NUM>, <NUM>, <NUM>, and/or <NUM> previously described in connection with <FIG>, <FIG>, <FIG>, and <FIG>.

At block <NUM>, the method <NUM> can include receiving, by logic circuitry, NIC access information corresponding to a request to access data included in a persistent memory device (e.g., the persistent memory device <NUM> of <FIG>), a non-persistent memory device (e.g., the non-persistent memory device <NUM> of <FIG>), or both. The state machine can be the state machine <NUM> or <NUM> described in connection with <FIG> and <FIG>. The NIC can be similar to input/output device as previously described herein in connection with I/O device <NUM> or <NUM> described in connection with <FIG> and <FIG>. In some embodiments, the logic circuitry can receive read or write requests of the data responsive to receiving the access information from the NIC.

In a non-limiting example, the state machine (e.g., the logic circuitry) can determine if a write buffer (e.g., the write buffer <NUM> of <FIG>) is full, responsive to the received write operation and receive, via the NIC, an affirmative write operation responsive to the write buffer not being full, and receive, by the logic circuitry, an indication from a hypervisor (e.g., a host coupled to the hypervisor <NUM> of <FIG>) that the hypervisor has completed the write operation. The indication from the hypervisor can be transmitted from a hypervisor done register (e.g., <NUM> previously described in connection with <FIG>).

In another non-limiting example, the state machine (e.g., the logic circuitry) can further transmit the interrupt signal to notify the hypervisor of the read operation responsive to the received read request, and receive, via the NIC, an affirmative read operation responsive to the hypervisor accessing the data to be read from a DRAM portion of the hierarchical memory apparatus.

At block <NUM>, the method <NUM> can include accessing, by the logic circuitry, a base address register coupled to the logic circuitry to determine a logical address corresponding to the requested data. The base address register can be, for example, address register <NUM>-N or <NUM>-N previously described in connection with <FIG> and <FIG> and can be used to determine the address corresponding to the data in a manner analogous to that described in connection with <FIG> and <FIG>.

At block <NUM>, the method <NUM> can include determining, by the logic circuitry, that the requested data corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device. In some embodiments, the logic circuitry can be configured to transfer the request to the hypervisor to access the data from the persistent memory device in response to the determination that the data is stored in the persistent memory device. The logic circuitry can be configured to assert an interrupt to the hypervisor as part of the request to the hypervisor to access the data corresponding to the persistent memory device, as previously described herein.

At block <NUM>, the method <NUM> can include generating, by the logic circuitry, responsive to receipt of the NIC access information and the determination that the requested data correspond to an operation to divert data from the non-persistent memory, an interrupt signal.

At block <NUM>, the method <NUM> can include transferring the interrupt signal to a hypervisor coupleable to the logic circuitry as part of the operation to divert data form the non-persistent memory device to the persistent memory device. In some embodiments, transferring the interrupt signal to the hypervisor coupleable to the logic circuitry prompts the hypervisor to retrieve data from the persistent memory device, and transfer the data to the non-persistent memory device. For example, when the hierarchical memory apparatus asserts an interrupt on a hypervisor coupled to the hierarchical memory apparatus as part of fulfilling a redirected read or write request, an INTERRUPT CONFIG message can be generated by the state machine to generate an appropriate interrupt message based on whether the operation is an operation to retrieve data from a persistent memory device or an operation to write data to the persistent memory device. In some non-limiting embodiments, the logic circuitry can receive subsequent NIC access information.

Claim 1:
An apparatus, comprising:
logic circuitry configured to:
receive, from a state machine (<NUM>, <NUM>), a command indicating that an access to a base address register (<NUM>, <NUM>, <NUM>, <NUM>) deployed on a memory controller (<NUM>, <NUM>) coupled to the logic circuitry has occurred, the command indicative of a data access involving a persistent memory device (<NUM>, <NUM>), a non-persistent memory device (<NUM>, <NUM>), or both;
determine, by the logic circuitry, that the access command corresponds to an operation to divert data from the non-persistent memory device (<NUM>, <NUM>) to the persistent memory device (<NUM>, <NUM>);
generate, by the logic circuitry and responsive to receipt of the access command and the determination, an interrupt signal, wherein the interrupt signal is generated by accessing a second base address register and using an interrupt component (<NUM>); and
cause, by the state machine (<NUM>, <NUM>), the interrupt signal to be asserted on a host coupleable to the logic circuitry as part of the operation to divert data from the non-persistent memory device (<NUM>, <NUM>) to the persistent memory device (<NUM>, <NUM>).