Patent Description:
An unmanned vehicle (UV) is a vehicle having no onboard pilot. Typically, UVs such as unmanned aerial vehicles (UAVs) are controlled remotely by a pilot, by onboard control systems, or by a combination of a remote pilot and onboard control system. Most unmanned aerial vehicles include a control system to control vehicle operations. Often, a control system for a UAV includes one or more vehicle control systems including onboard navigation systems such as inertial navigation systems and satellite navigation systems. Unmanned aerial vehicles may use inertial navigation sensors such as accelerometers and gyroscopes for flight positioning and maneuvering and satellite-based navigation for general positioning and wayfinding. Most control systems additionally include one or more mission control systems for performing one or more mission control functions, such as capturing images or delivering a payload. Typically, individual hardware components are provided onboard a UAV for each vehicle control system and each mission control system.

<CIT> discloses a system for facilitating virtualization of a heterogeneous processor pool includes a processor allocation component and a hypervisor, each executing on a host computer. The processor allocation component identifies a plurality of physical processors available for computing and determines a set of flags, each of the set of flags identifying a type of functionality provided by each of a subset of the plurality of physical processors. The hypervisor, in communication with the processor allocation component, allocates, to at least one virtual machine, access to one of the subset of the plurality of physical processors.

<CIT> discloses a processor having a flag indicating whether time consuming instructions should be executed. When the flag has a first value, the instructions are executed. When the flag has a second value, an exception is generated if the processor attempts to execute one of the instructions. The instructions may be non-interruptible instructions, which take a large number of clock cycles, such as floating point square root instructions, a divide instructions, multiple load instructions or multiple store instructions.

<CIT> discloses architecture having a computing device for execution of electronic data processing. A first virtual machine is provided with infotainment operating system and second virtual machine is provided with real-time automotive operating system. A virtualization layer is adapted in the infotainment and real-time automotive operating systems which are operated in parallel with a head unit.

<CIT> discloses a method for controlling a graphic processing unit, GPU, in a control unit, in particular of a vehicle, the control unit comprising at least one central processing unit, CPU, the at least one CPU having access to at least one memory; the GPU being connected to and controlled by the at least one CPU, wherein the GPU is adapted to provide frames to at least one display having a predetermined output display frame rate.

Aspects and advantages of the disclosed technology will be set forth in part in the following description, or may be obvious from the description, or may be learned through practice of the disclosure.

According to example aspects of the present disclosure, there is provided a processing system for an unmanned vehicle (UV), comprising a first processing unit of an integrated circuit, a second processing unit of the integrated circuit, and a first operating system provisioned using the first processing unit. The first operating system is configured to execute a first vehicle control process. The processing system comprises a virtualization layer configured using at least the second processing unit, and a second operating system provisioned using the virtualization layer. The second operating system is configured to execute a second vehicle control process.

According to example aspects of the present disclosure, there is provided a computer-implemented method for controlling an unmanned vehicle (UV), that comprises provisioning a first operating system using a first processor of an integrated circuit, configuring the first operating system to execute a first vehicle control process using the first processor, provisioning at least one virtual machine using a second processor of the integrated circuit, and configuring the at least one virtual machine to execute a second vehicle control process. The at least one virtual machine is isolated from the first operating system.

According to example aspects of the present disclosure, there is provided a processing system for an unmanned vehicle (UV), comprising an integrated circuit comprising a first processor and a second processor, a first operating environment provisioned using the first processor, a virtualization layer configured using at least the second processor, and a first virtual machine provisioned using the virtualization layer. The first virtual machine is configured to execute at least one vehicle control process in a second operating environment. The second operating environment is isolated from the first operating environment. The processing system includes a second virtual machine provisioned using the virtualization layer. The second virtual machine is configured to execute at least one mission control process in a third operating environment. The third operating environment is isolated from the second operating environment and the first operating environment.

These and other features, aspects and advantages of the disclosed technology will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate aspects of the disclosed technology and, together with the description, serve to explain the principles of the disclosed technology.

Reference now will be made in detail to embodiments of the disclosure, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation, not limitation of the disclosed embodiments. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the scope or spirit of the claims. For instance, features illustrated or described as part of example embodiments can be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present disclosure covers such modifications and variations as come within the scope of the appended claims and their equivalents.

As used in the specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. The use of the term "about" in conjunction with a numerical value refers to within <NUM>% of the stated amount.

Example aspects of the present disclosure are directed to systems and methods for controlling unmanned vehicles (UV), and more particularly, to systems and methods for controlling unmanned vehicles and vehicle devices of the unmanned vehicles using a control system to provide integrated vehicle and mission management control. In example embodiments, the control system may include one or more processing systems. For example, a control board including a processing system having a first processing unit and a second processing unit may be provided. The processing system may additionally include a programmable logic array such as a field programmable gate array (FPGA). Multiple partitioned operating environments are provided using the various processing elements in order to provide a reliable, configurable, and certifiable software configuration suitable to the operating needs of a UV.

In accordance with example embodiments of the disclosed technology, a first operating system can be provisioned from the first processing unit in order to execute a first vehicle control process. A virtualization layer is configured from at least the second processing unit. A second operating system can then be provisioned from the virtualization layer. The second operating system can be configured to execute a second vehicle control process. The second operating system may additionally be configured to execute mission control processes. A third operating system can also be provisioned from the virtualization layer. The third operating system can be configured to execute vehicle and/or mission control processes.

In a particular aspect, a first virtual machine can be provisioned from the virtualization layer and a second virtual machine can be provisioned from the virtualization layer. In example embodiments, the first virtual machine can be a real-time virtual machine including the second operating system and the second virtual machine can be a non-real-time virtual machine including the third operating system. More particularly in some examples, the first operating system can be provisioned using a real-time processing unit and the first and third virtual machines configured using an application processing unit.

The first operating system includes a high integrity partitioned operating environment in some examples. The first operating system may include a hardware and software partition isolating the first operating system from other virtual machines and operating systems of the control system. For instance, the first operating system may be configured using a real-time processing unit while other operating systems are configured using other processing units. In various aspects, vehicle control processes and/or mission control processes can be configured for execution in the high integrity partitioned operating environment. For example, critical vehicle control processes and/or mission control processes may be configured in the high integrity partition. Additional vehicle control processes and/or mission control processes can be configured for other operating environments such as in one or more virtual machines provisioned using an application processing unit. In this manner, the critical vehicle and/or mission control processes can be isolated from other processes using hardware and software. By way of example, a vehicle control process associated with controlling at least one propulsion and movement device of the UV may be configured in a high integrity partitioned operating environment. More specifically, an autopilot process can be configured in a high integrity partition.

According to some aspects, at least one computational accelerator is configured in a field programmable gate array of the processing system. At least one interface for the computational accelerator can be configured in a virtualization layer in order to provide access to the computational accelerator from other processing elements of the system.

In example embodiments, the control system includes a housing defining an interior and one or more circuit boards disposed within the interior. More particularly, the control system can include a first circuit board having one or more integrated circuits that provide a first processing system and a second processing system. In example embodiments, the first and second processing systems have heterogeneous field programmable gate array architectures to provide diverse, configurable, and certifiable UV applications.

In some examples, the first circuit board forms a control module for a control box and is configured to control vehicle and mission functions for a UV. For example, the second processing system can control a first vehicle device or function of the UV based on execution of a first mission or vehicle control process by the first processing system and execution of a second mission or vehicle control process by the second processing system.

In example embodiments, the first processing system can include one or more first processing units and a volatile programmable logic array such as a RAM based field programmable gate array. A second processing system can include one or more second processing units and a nonvolatile programmable logic array such as a flash-based field programmable gate array. In some implementations, the flash-based field programmable gate array manages control of one or more vehicle devices of the UAV based on a first vehicle process executed by the one or more first processing units and a second vehicle process executed by the one or more second processing units. In example embodiments, the second processing system can be configured with multiple operating systems including standalone operating systems and virtual machines as described with respect to the first operating system. Each processing system may include one or more processing units such as central processing units (CPU), application processing units (APU), real-time processing units (RPU), co-processing processing units, and graphics processing units (GPU). Additionally, each processing system may include an embedded programmable logic array such as a field programmable gate array (FPGA) forming an integrated part of the respective processing system.

In some examples, the first processing system and/or the second processing system may each be provided as a multi-processing core system-on-a-chip. Together, two or more systems on chip configured with processing systems as described may provide a heterogeneous processing system for a UV.

In example embodiments of the disclosed technology, the first processing system and the second processing system cooperate to provide more reliable, robust, and/or certifiable UV applications. For example, the first processing system of the first circuit board can be configured to execute a first process for the UV. The first process may be associated with a first vehicle device of the UV. The second processing system can be configured to monitor execution of the first process by the first processing system. Similarly, the first processing system can be configured to monitor execution of a process by the second processing system.

Embodiments of the disclosed technology provide a number of technical benefits and advantages, particularly in the area of unmanned vehicles such as unmanned aerial vehicles. As one example, the technology described herein enables control of an unmanned vehicle (UV) using compact and lightweight electronic solutions. Circuit boards having integrated heterogeneous processing systems enable reduced hardware implementations that provide multiple vehicle control processes and mission management processes for a UV. Additionally, such solutions provide backup functions and multiple fail point implementations that can meet the high certification requirements of airborne applications. Moreover, the integration of such heterogeneous processing systems into a housing with one or more circuit boards that provide input/output (I/O) interfaces further enables reduced space and weight requirements. Furthermore, the disclosed software system enables partitioned operating environments to be used to meet the requirements of code certifications for computer readable instructions in UV applications.

Embodiments of the disclosed technology also provide a number of technical benefits and advantages in the area of computing technology. For example, the disclosed system can provide diverse computing environments to meet the various demands of UV applications. Multiple processing units spread across multiple integrated circuits provide a range of high speed processing options for application integration. Vehicle and mission control processes can be allocated to various hardware and/or software partitions according to criticality and performance needs. Moreover, embedded field programmable gate arrays tightly coupled to these processing units via integration on a single integrated circuit with corresponding processing units provides additional diversity and reliability.

<FIG> is a schematic view of an example unmanned aerial vehicle (UAV) UAV <NUM>. UAV <NUM> is a vehicle capable of flight without an onboard pilot. For example, and without limitation, UAV <NUM> may be a fixed wing aircraft, a tilt-rotor aircraft, a helicopter, a multirotor drone aircraft such as a quadcopter, a blimp, a dirigible, or other aircraft.

UAV <NUM> includes a plurality of vehicle devices including at least one propulsion and movement (PM) device <NUM>. A PM device <NUM> produces a controlled force and/or maintains or changes a position, orientation, or location of UAV <NUM>. A PM device <NUM> may be a thrust device or a control surface. A thrust device is a device that provides propulsion or thrust to UAV <NUM>. For example, and without limitation, a thrust device may be a motor driven propeller, jet engine, or other source of propulsion. A control surface is a controllable surface or other device that provides a force due to deflection of an air stream passing over the control surface. For example, and without limitation, a control surface may be an elevator, rudder, aileron, spoiler, flap, slat, air brake, or trim device. Various actuators, servo motors, and other devices may be used to manipulate a control surface. PM device <NUM> may also be a mechanism configured to change a pitch angle of a propeller or rotor blade or a mechanism configured to change a tilt angle of a rotor blade.

UAV <NUM> may be controlled by systems described herein including, without limitation, an onboard control system including a control box <NUM>, a ground control station (not shown in <FIG>), and at least one PM device <NUM>. UAV <NUM> may be controlled by, for example, and without limitation, real-time commands received by UAV <NUM> from the ground control station, a set of pre-programmed instructions received by UAV <NUM> from the ground control station, a set of instructions and/or programming stored in the onboard control system, or a combination of these controls.

Real-time commands can control at least one PM device <NUM>. For example, and without limitation, real-time commands include instructions that, when executed by the onboard control system, cause a throttle adjustment, flap adjustment, aileron adjustment, rudder adjustment, or other control surface or thrust device adjustment.

In some embodiments, real-time commands can further control additional vehicle devices of UAV <NUM>, such as one or more secondary devices <NUM>. A secondary device <NUM> is an electric or electronic device configured to perform one or more secondary functions to direct propulsion or movement of the UAV. Secondary devices may be related to propulsion or movement of the UAV, but typically provide one or more vehicle or mission functions independent of direct control of vehicle propulsion or motion control. For example, secondary devices may include mission- related devices such as cameras or other sensors used for object detection and tracking. Other examples of secondary devices <NUM> may include sensors such as LIDAR/SONAR/RADAR sensors, GPS sensors, communication devices, navigation devices, and various payload delivery systems. For example, and without limitation, real-time commands include instructions that when executed by the onboard control system cause a camera to capture an image, a communications system to transmit data, or a processing component to program or configure one or more processing elements.

UAV <NUM> is depicted by way of example, not limitation. Although much of the present disclosure is described with respect to unmanned aerial vehicles, it will be appreciated that embodiments of the disclosed technology may be used with any unmanned vehicle (UV), such as unmanned marine vehicles and unmanned ground vehicles. For example, the disclosed control systems may be used with unmanned boats, unmanned submarines, unmanned cars, unmanned trucks, or any other unmanned vehicle capable of locomotion.

<FIG> is a block diagram depicting an example of a typical control system <NUM> for a UAV. In this example, a control system is formed using a backplane <NUM> having a plurality of card slots <NUM>, <NUM>, <NUM>, <NUM>, <NUM>. Each card slot is configured to receive a card meeting a predefined set of mechanical and electrical standards. Each card includes one or more circuit boards, typically including one or more integrated circuits configured to perform specific vehicle or mission control functions. The card slot provides structural support for the card, as well as an electrical connection between the card and an underlying bus. A particular example is depicted having a CPU card <NUM> installed in a first card slot <NUM>, a co-processor card <NUM> installed in a second card slot <NUM>, and add-on cards <NUM>, <NUM>, <NUM> installed in card slots <NUM>, <NUM>, <NUM>, respectively. By way of example, CPU card <NUM> may include a circuit board having a processor, PCI circuitry, switching circuitry, and an electrical connector configured to both structurally and electrically connect card <NUM> to card slot <NUM>. Similarly, co-processor card <NUM> may include a processor, PCI circuitry, switching circuitry, and a connector.

Add-on cards <NUM>, <NUM>, <NUM> may include any number and type of cards configured to perform one or more vehicle and/or mission functions. Examples of add-on cards include input/output (I/O) cards, network cards, piloting and navigation function cards, sensor interface cards (e.g., cameras, radar, etc.), payload delivery systems control cards, graphics processing unit (GPU) cards, and any other card for a particular type of vehicle and/or mission function.

Typical backplane architectures like that in <FIG> include a switch <NUM> that allows each card to communicate with cards in any other slot. Numerous examples including various standards exist to define different types of backplane architectures. For example, although switch <NUM> is shown separate from the card slots <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, some architectures may place a central switch in a particular slot of the backplane. In each case, the node devices can communicate with one another via the switch. While five card slots are depicted in <FIG>, a backplane may include any number of card slots.

An onboard control system for a UAV utilizing a backplane architecture like that of <FIG> may be effective in providing some function control. Additionally, such an architecture may provide some configurability through hardware changes. However, traditional backplane architectures may have a number of drawbacks in implementations for UAVs. For example, the structural performance of a backplane coupling to a plurality of cards through a combined electrical and mechanical connection may not be well-suited to the high-stress environments of some UAVs. Mechanical and/or electrical failures may occur for one or more cards in the backplane due to vibrations, temperatures, and other factors. Additionally, such architectures provide a limited processing capability, while requiring considerable space and weight. Each card typically includes its own circuit board including connectors, switching circuitry, communication circuitry, etc. Because each circuit board requires its own circuitry for these common functions, a backplane architecture may provide relatively high weight and space requirements. Moreover, the computing ability and capacity of these types of systems is typically limited by a multiple card approach. Communication between the cards, and between the various processing elements may lead to reduced computational abilities.

<FIG> is a block diagram depicting an unmanned aerial vehicle (UAV) <NUM> including a control system <NUM> in accordance with embodiments of the disclosed technology. Control system <NUM> includes a control box <NUM> that provides centralized control of vehicle and mission functions. The control box includes a housing <NUM> defining an interior. A first circuit board <NUM> and second circuit board <NUM> are disposed within the interior of housing <NUM>, and an I/O connector <NUM> extends from the second circuit board <NUM> through the housing <NUM> as described hereinafter. Control box <NUM> includes a heat sink <NUM> provided to dissipate heat from the electric components of the control box <NUM>. In example embodiments, heat sink <NUM> may form at least a portion of housing <NUM> as described hereinafter. Control system <NUM> may include additional components such as additional control units or other elements that perform vehicle or mission control processes.

In some implementations, first circuit board <NUM> comprises a control module for controlling vehicle and mission control processes of UAV <NUM>, and second circuit board <NUM> comprises a carrier module for providing a communication interface between the control unit and various PM devices and secondary devices of the UAV.

In some examples, the first circuit board includes multiple heterogeneous processing systems, each having a reconfigurable processing architecture to provide management of the various vehicle and mission functions. The multiple heterogeneous processing systems with reconfigurable functionality are suited to the diverse functions performed by unmanned airborne vehicles, as well as the high level of certifications typically needed for these vehicles.

In example embodiments, the second circuit board <NUM> is a carrier module providing an interface between the first circuit board <NUM> and the various PM devices and secondary devices of UAV <NUM>. For example, <FIG> depicts a set of PM devices including a thrust device <NUM>, control surface <NUM>, and positioning system <NUM>. Additionally, <FIG> depicts a set of secondary devices including an image sensor <NUM>, a radar sensor <NUM>, a LIDAR sensor <NUM>, a sonar sensor <NUM>, a GPS sensor <NUM>, a payload delivery system <NUM>, and a communication system <NUM>. The second circuit board <NUM> may include an I/O connector that connects to a corresponding I/O connector of the first circuit board, as well as an I/O connector that extends from the housing. Additionally, the second circuit board may include a plurality of sensor connectors that extend from the housing. The second circuit board may provide a communications or input/output (I/O) interface including associated electronic circuitry that is used to send and receive data. More specifically, the communications interface can be used to send and receive data between any of the various integrated circuits of the second circuit board, and between the second circuit board and other circuit boards. For example, the item interface may include I/O connector <NUM>, I/O connector <NUM>, and/or I/O connector <NUM>. Similarly, a communications interface at any one of the interface circuits may be used to communicate with outside components such as another aerial vehicle, a sensor, other vehicle devices, and/or ground control. A communications interface may be any combination of suitable wired or wireless communications interfaces.

In some examples, control box <NUM> may include additional components. For example, a third circuit board such as a mezzanine card can be provided within control box <NUM> in another embodiment. The third circuit board may include one or more nonvolatile memory arrays in some examples. For example, a solid-state drive (SSD) may be provided as one or more integrated circuits on a mezzanine card. Moreover, control box <NUM> may include additional circuit boards to form a control module as well as additional circuit boards to form additional carrier modules.

<FIG> is a block diagram describing a first circuit board <NUM> in accordance with example embodiments of the disclosed technology. In <FIG>, first circuit board <NUM> is configured as a control module (e.g., control board) for an unmanned aerial vehicle (UAV). In example embodiments, first circuit board <NUM> is a system-on-module (SOM) card. First circuit board <NUM> includes a first processing system <NUM>, second processing system <NUM>, memory blocks <NUM>, and an I/O connector <NUM>.

The first and second processing systems can include or be associated with, any suitable number of individual microprocessors, power supplies, storage devices, interfaces, and other standard components. The processing systems can include or cooperate with any number of software programs (e.g., vehicle and mission control processes) or instructions designed to carry out the various methods, process tasks, calculations, and control/display functions necessary for operation of the aerial vehicle <NUM>. Memory blocks <NUM> may include any suitable form of memory such as, without limitation, SDRAM, configured to support a corresponding processing system. For example, a first memory block <NUM> may be configured to support first processing system <NUM> and a second memory block <NUM> may be configured to support second processing system <NUM>. Any number and type of memory block <NUM> may be used. By way of example, four memory blocks each comprising an individual integrated circuit may be provided to support the first processing system <NUM> and two memory blocks may be provided to support the second processing system <NUM>.

I/O connector <NUM> extends from a first surface of first circuit board <NUM> to provide an operative communication link to second circuit board <NUM>.

First processing system <NUM> and second processing system <NUM> form a heterogeneous and reconfigurable computing architecture in example embodiments of the disclosed technology, suitable to the diverse and stable needs of UAV <NUM>. First processing system <NUM> includes one or more processing units <NUM> forming a first processing platform and one or more programmable logic circuits <NUM> forming a second processing platform. By way of example, one or more processing units <NUM> may include a central processing unit and programmable logic circuit <NUM> may include a volatile programmable logic array such as a RAM-based field programmable gate array (FPGA). Any number and type of processing unit may be used for processing units <NUM>. Multiple processing units <NUM> and programmable logic circuit <NUM> may be provided within a first integrated circuit, referred to generally as a processing circuit in some embodiments.

Second processing system <NUM> includes one or more processing units <NUM> forming a third processing platform and one or more programmable logic circuits <NUM> forming a fourth processing platform. By way of example, one or more processing units <NUM> may include a co-processing unit and programmable logic circuit <NUM> may include a flash-based FPGA. Any number and type of processing unit may be used for processing units <NUM>. One or more processing units <NUM> and programmable logic circuit <NUM> may be provided within the second integrated circuit, also referred to as a processing circuit in some embodiments.

By providing different processing unit types as well as different programmable logic circuit types in each processing system, first circuit board <NUM> provides a heterogeneous computing system uniquely suited to the processing, reliability, and operational requirements of high-stress application UAVs. For example, the RAM-based and flash-based FPGA technologies are combined to leverage the strengths of both for UAV applications. The unique abilities of heterogeneous processing units <NUM> and <NUM> and heterogeneous programmable logic circuits <NUM> and <NUM> support both hardware and software-partitioned operating environments. Vehicle and mission management functions can be allocated to different partitions according to criticality and performance needs. This provides a control and monitor architecture suitable for critical operations. For example, an on/off or red/green architecture for control of irreversible critical functions is provided. By way of further example, one or more of the field programmable gate arrays may be configured to provide a fabric accelerator for onboard sensor processing.

<FIG> is a block diagram describing additional details of first processing system <NUM> in accordance with example embodiments of the disclosed technology. In <FIG>, first processing system <NUM> includes three processing units <NUM> as described in <FIG>. More particularly, first processing system <NUM> includes an application processing unit (APU) <NUM>, a graphics processing unit (GPU) <NUM>, and a real-time processing unit (RPU) <NUM>. Each of processing units <NUM>, <NUM>, <NUM> may be supported by memory <NUM> which may include any number and type of memory such as an SDRAM. Each processing unit is implemented on an individual integrated circuit referred to as a processing circuit. In one example, APU <NUM> is formed on a first processing circuit and includes a quad core processing unit comprising four processors. RPU <NUM> is formed on a third processing circuit and includes a dual core processing unit comprising two processors. GPU <NUM> is formed on a fourth processing circuit and includes a single core processing unit. A second processing unit is provided for the second processing system as described below. A switch fabric <NUM> connects the various components of processing system <NUM>. Switch fabric <NUM>, for example, may include a low-power switch and a central switch in some examples. Communication interface <NUM> couples first processing system <NUM> to first circuit board <NUM>.

Programmable logic circuit <NUM> includes a volatile programmable logic array <NUM>. In example embodiments, logic array may include a RAM-based programmable logic array such as a RAM-based floating point gate array including RAM logic blocks or memory cells. Volatile programmable logic array <NUM> can be programmed with configuration data provided to the first processing system through communication interface <NUM>. For example, a RAM-based FPGA can store configuration data in the static memory of the array, such as in an organization comprising an array of latches. The logic blocks are programmed (configured) when programmable logic circuit <NUM> is started or powered up. The configuration data can be provided to logic array <NUM> from an external memory (e.g., nonvolatile memory of first circuit board <NUM> or a mezzanine board as described hereinafter) or from an external source of UAV <NUM> (e.g., using second circuit board <NUM>). A RAM-based FPGA provides high levels of configurability and re-configurability. Although not shown, logic array <NUM> may include various programmed circuits such as ethernet interfaces and PCI interfaces, and the various vehicle and mission management processes described herein.

<FIG> is a block diagram describing additional details of second processing system <NUM> accordance with example embodiments of the disclosed technology. In <FIG>, second processing system <NUM> includes an application processing unit (APU) <NUM> and memory <NUM>. In one example, APU <NUM> is formed on a second processing circuit and includes a quad core processing unit comprising four processors. Memory <NUM> may include any number and type of memory such as SDRAM. A switch fabric <NUM> connects the various components of processing system <NUM>. Communications interface <NUM> couples first processing system <NUM> to first circuit board <NUM>.

Programmable logic circuit <NUM> includes a nonvolatile programmable logic array <NUM>. In example embodiments, logic array <NUM> may include a flash-based programmable logic array such as a flash-based floating point gate array including flash logic blocks or memory cells. Nonvolatile programmable logic array <NUM> can be programmed with configuration data provided to the second processing system through communication interface <NUM>. For example, a flash-based FPGA can store configuration data in the nonvolatile memory of the array. Flash memory is used as the primary resource for storage of the configuration data such that RAM-based memory is not required. Because the configuration data is stored within the nonvolatile memory, there is no requirement for reading the configuration data to the logic array upon startup or power up. As such, the flash-based logic array may execute applications immediately upon power up. Moreover, external storage of configuration data is not required. The flash-based logic array can be reprogrammed or reconfigured by providing updated configuration data to override the configuration data presently stored in the logic array. The flash-based logic array may consume less power than the RAM-based logic array, as well as provide more protection against interference. Although not shown, logic array <NUM> may include various programmed circuits, such as for the various vehicle and mission management processes described herein. In one example, logic array <NUM> may include at least one FPGA fabric accelerator for onboard sensor processing.

<FIG> is a block diagram depicting additional details of second circuit board <NUM> in accordance with example embodiments of the disclosed technology. In <FIG>, second circuit board <NUM> is configured as a carrier module (e.g., carrier card) for an unmanned aerial vehicle (UAV). Second circuit board <NUM> includes a plurality of integrated circuits such as interface circuits providing I/O capabilities for control box <NUM>. The interface circuits are configured to receive outputs of the plurality of vehicle devices of the UAV via the sensor connectors. The interface circuits provide vehicle device data based on outputs of the vehicle devices to the first circuit board via I/O connector <NUM>. Second circuit board <NUM> includes an I/O connector <NUM> that extends from a housing of control unit <NUM> to provide an operative communication link to PM devices and secondary devices of UAV <NUM>. Additionally, second circuit board <NUM> includes an I/O connector <NUM> extending from a first surface of second circuit board <NUM> to provide an operative communication link to first circuit board <NUM>. Although not shown, second circuit board <NUM> may include an additional I/O connector for coupling to a mezzanine card including a solid-state drive, for example. Any one or a combination of I/O connectors <NUM>, <NUM>, and <NUM> may form an I/O interface between the interface circuits of the second circuit board and the first and second processing systems of the first circuit board.

<FIG> describes a particular set of interface circuits as may be used in the particular implementation of control box <NUM>. It will be appreciated, however, that any number and type of interface circuit may be used as suited for a particular implementation. Second circuit board <NUM> includes a plurality of interface circuits such as a LIDAR/SONAR interface <NUM>, a Pitot/static interface <NUM>, an electro-optical grid reference system (EOGRS) receiver interface <NUM>, and a first circuit board interface <NUM> for communicating with first circuit board <NUM>. Second circuit board <NUM> also includes interface circuits such as a software defined radio <NUM>, a navigation system <NUM>, a controller area network bus (CANBUS) <NUM>, and a power supply <NUM>. In some embodiments, navigation system <NUM> is an integrated circuit providing an integrated navigation sensor suite, including various sensors such as inertial measurement sensors. Additionally, second circuit board <NUM> includes a number of interface circuits in operative communication with a plurality of vehicle devices (e.g., PM devices or secondary devices) of the UAV <NUM>. A plurality of sensor connectors <NUM> extend from the housing of control unit <NUM> for coupling to the vehicle devices of UAV <NUM>.

In the specific example of <FIG>, one or more pulse width modulators (PWM) <NUM> are in operative communication with one or more servos <NUM> via a first sensor connector <NUM>. Although a PWM servo command interface is depicted, other types of servo command interfaces may be used. For example, analog voltage, current loop, RS-<NUM>, RS-<NUM>, MII,-STD-<NUM> are all examples of possible servo control signals. A GPS receiver <NUM> is in operative communication with one or more GPS antennas <NUM> via a second sensor connector <NUM>. GPS antennas <NUM> are one example of a GPS sensor <NUM>. A datalink receiver <NUM> is in operative communication with one or more datalink antennas <NUM> via a third sensor connector <NUM>. A serial receiver link (SRXL) input <NUM> is in operative communication with a Pilot in Command (PIC) receiver <NUM> via a fourth sensor connector <NUM>. A programmable power supply unit (PSU) <NUM> is in operative communication with a servo power <NUM> via a fifth sensor connector <NUM>. One or more comparators <NUM> are in operative communication with one or more discrete inputs <NUM> via a sixth sensor connector <NUM>. One or more drivers <NUM> are in operative communication with one or more discrete outputs <NUM> via a seventh sensor connector <NUM>. One or more analog-to-digital converters (ADC) <NUM> are in operative communication with one or more analog inputs <NUM> via an eighth sensor connector <NUM>.

<FIG> is a block diagram depicting an example of first circuit board <NUM> in accordance with embodiments of the disclosed technology. <FIG> depicts a specific implementation of first circuit board <NUM>, as may be configured for a particular flight or mission. <FIG> depicts first processing system <NUM> second processing system <NUM> as previously described. For clarity of description, only a subset of the components of processing systems <NUM> and <NUM> are depicted. A simplified version of first processing system <NUM> is depicted including processing unit <NUM> and volatile programmable logic array <NUM>. Second processing system <NUM> is depicted with processing units <NUM> and programmable logic array <NUM>.

<FIG> depicts a plurality of partitioned operating environments POEO-POE <NUM> created across the heterogeneous processing system. <FIG> also depicts a specific allocation of vehicle and mission control processes to further illustrate the disclosed subject matter. Specifically, a first partitioned operating environment POE0, a second partitioned operating environment POE1, and a third partitioned operating environment POE2 are allocated at the one or more processing units <NUM>. In some examples, the partitioned operating environments are hardware partitions. For example, POEO may be allocated at APU <NUM>, POE1 may be allocated at RPU <NUM>, and POE2 may be allocated at GPU <NUM>. In other examples, the partitioned operating environments are software partitions, such as different virtual machines virtualized from one or more processing units. For example, one or more of APU <NUM>, GPU <NUM>, and RPU <NUM> may be virtualized to create the three partitioned operating environments. A fourth partitioned operating environment POE3 is allocated to programmable logic array <NUM>. Although a single operating environment is depicted in <FIG>, multiple operating environments may also be created within a programmable logic array. In one example individual partitioned operating environments with her programmable logic array represent different hardware elements such as different logic blocks. In other examples, virtualization or other software techniques may be used to create individual partitioned operating environments. Moreover, some embodiments include a combined virtualization of both processing unit <NUM> and programmable logic array <NUM>. Any number and combination of hardware processors and virtual machines may be used to create individual partitioned operating environments as depicted in <FIG>.

In <FIG>, one or more first vehicle control processes (VCP) <NUM> and one or more first mission control processes (MCP) <NUM> are allocated to the first partitioned operating environment POE0. One or more VCPs <NUM> and one or more MCPs <NUM> are allocated to the second partitioned operating environment POE1. One or more MCPs <NUM> are allocated to the third partitioned operating environment POE2. One or more MCPs <NUM> are allocated to the fourth partitioned operating environment POE3.

<FIG> illustrates that a plurality of vehicle control processes and mission control processes may be allocated across multiple partitioned operating environments to meet the needs of a particular implementation. For example, control processes may be categorized and the categories used to assign control processes to particular partitioned operating environments. In some implementations, the first processing system can provide at least two partitioned operating environments. Similarly, the second processing system can provide at least two partitioned operating environments. For example, the first processing system may include a high integrity partition and a cluster partition. The high integrity partition may include real-time operating environment. Such an operating environment may be configured for execution of one or more critical vehicle navigation processes for example. Other processes may be placed into the high integrity partition as well. The cluster partition may include non-real-time operating environment. Such an operating environment may be configured for execution of one or more mission control processes. Other processes may be placed into the cluster partition as well.

By way of specific example, POEO may be used to execute critical control processes. For instance, POEO can be a high integrity partitioned including autopilot, guidance, and navigation processes with auto-generated code from a model based design flow. In one example, a standalone operating system can be used for a first partitioned operating environment allocated for critical processes. POE1 may be used to execute less critical, but time sensitive vehicle and mission control processes. For example, mission navigation processes, datalink management processes, sensor data management processes, and/or ground station/other C2 processes may be allocated to the second partitioned operating environment. By way of further example, sensor processing and backend parameter analysis of health and/or other parameters, etc. may be allocated to the third partitioned operating environment POE2. Finally, a fourth partitioned operating environment POE3 may be allocated to high processing requirement applications such as image analysis and object detection and tracking. For example, sensor-relative navigation and robotic perception/cognition may be performed in the fourth partitioned operating environment. In other examples geo-registration of sensor collection including targeting and alternate navigation sources may be allocated to POE <NUM>. Additionally, software defined radio including signal intelligence collection and flexible data links for payload data dissemination may be allocated. In some examples, one or more of POE1, POE2, and POE3 may be a virtualized computing cluster form for mission control processes that are isolated from the high integrity partition. It will be appreciated that the examples are provided by way of explanation only and numerous other options allocations may be made according to the requirements of a particular implementation.

Referring to the second processing system <NUM>, a fifth partitioned operating environment POE4 may be allocated for additional vehicle control processes. In some examples, POE4 may be used to execute critical and/or time sensitive vehicle control processes such as backup navigation and piloting processes. The sixth partitioned operating environment POE5 may be allocated for additional mission control processes. In some examples, POE5 may be used to execute less critical or time sensitive mission control processes. The seventh partitioned operating environment POE6 is allocated to programmable logic array <NUM>. In this example, POE6 is allocated for execution of one or more vehicle control processes. By way of particular example, navigation monitoring and/or control processes may be configured in the seventh partitioned operating environment POE6 in one embodiment. As described in more detail hereinafter, one or more monitoring and/or control processes may be implemented in POE6 in one implementation.

The heterogeneous processing system provided by first circuit board <NUM> is uniquely situated to handle the diverse and high reliability requirements of UAV's. More particularly, the heterogeneous processing system enables joint processing by two disparate processing systems to provide monitoring, correction, and backup functions. For example, one or more components of first processing system <NUM> may monitor execution of one or more processes at the second processing system <NUM> and generate control actions based on the monitor execution. Similarly, one or more components of the second processing system <NUM> may monitor execution of one or more processes at the first processing system <NUM> and generate control actions based on the monitored execution. By way of example, the second processing system may detect one or more anomalies associated with execution of a process by the first processing system and restart the process and/or the first processing system. By way of additional example, the second processing system may execute a backup process in response to a detected anomaly associated with the first processing system. In yet another example, the second processing system may monitor an output of the first processing system and check for a concurrence with an output of the second processing system. In response to a concurrence, a control action such as enabling a vehicle device may be initiated.

<FIG> is a flowchart describing a process <NUM> of joint processing of a management processes by a heterogeneous processing system in accordance with embodiments of the disclosed technology. Although process <NUM> describes monitoring by the second processing system execution of a process by the first processing system, it will be appreciated that the process may be similarly used by the first processing system to monitor execution of the process by the second processing system. In one example, process <NUM> can be performed by a dedicated process within a programmable logic array of the processing system. In another example, process <NUM> may be performed by one or more processing units.

At (<NUM>), a first process is executed by the first processing system. For example, an application or other set of instructions can be executed by one or more processing units and/or the volatile programmable logic array of the first processing system.

At (<NUM>), the second processing system monitors execution of the first process at the first processing system. In some implementations, monitoring execution of a process includes monitoring an output of the first processing system. In other examples, monitoring execution of a process includes monitoring for one or more anomalies associated with execution of the process by the first processing system.

At (<NUM>), the second processing system determines whether the output of the first processes is valid. In some examples , determining whether the output is valid includes determining whether the first processing systems is generating the output. If the first processing system is generating an output, the second processing system determines that the output is valid. In another example, monitoring the output includes determining whether the output includes a valid signal. For example, the second processing system can determine whether the output includes a signal consistent with the first process being executed at the first processing system. In another example, the second processing system can determine whether the output matches or shares a concurrence with another output. For instance, the second processing system can determine whether the output of the first processing system matches or is the same as an output of the second processing system in one example.

At (<NUM>), process <NUM> branches based on whether the output of the first process was determined to be valid and/or shared a concurrence with another output. If the output of the first process is determined to be valid, a first control action is generated for the unmanned aerial vehicle at (<NUM>). If the output of the first process is determined to be invalid, a second control action is generated for the unmanned aerial vehicle at (<NUM>). As described in more detail hereinafter, the first control action may include providing the output of the first process. The second control action may include restarting the first process or the first processing system, executing a backup process, configuring a new process, or other suitable actions.

<FIG> is a flowchart describing a process <NUM> of initiating control actions based on monitoring execution of a first processing system by a second processing system or vice versa. More particularly, process <NUM> describes second control actions that may be generated based on invalid output of the first processing system. For example, process <NUM> may be performed by second processing system <NUM> at (<NUM>) of process <NUM> shown in <FIG>.

At (<NUM>), process <NUM> determines whether the first process associated with the invalid output signal is associated with a high criticality function of the UAV. For example, the second processing unit may take different actions based on type of process for which an invalid output was detected. In this manner, the second processing system may be adapted to the particular requirements of various implementations. In a particular example, all vehicle control processes may be considered to be associated with high criticality vehicle functions. Similarly, a subset of mission management processes such as navigation or certain sensor data management may be considered to be associated with high criticality functions.

If the control action is being initiated in response to a high criticality function, process <NUM> continues at (<NUM>). At (<NUM>), a backup process for the first process is executed by the second processing system. In some examples, the second processing system executes the backup process in one or more processing units <NUM>. In other examples, the second processing system executes the backup process in programmable logic circuit <NUM>.

At (<NUM>), function control is transferred to the backup process. For example, the second processing system can transfer control of the high criticality function from the first process to the backup process. It will be appreciated that the backup process may be executed by the second processing system prior to detecting an invalid output. For example the backup process may already be executing in the second processing system. In response to an invalid output from the first processing system, function control can be transferred to the backup process.

After transferring function control to the backup process, or in response to determining that the function is not a high criticality function, process <NUM> continues at <NUM>. At (<NUM>), process <NUM> determines whether the first processing system has been compromised. For example, the second processing system can determine whether the invalid output is associated with an unauthorized modification of the first process at the first processing system. In some examples, the second processing system may detect an unauthorized modification in response to unexpected outputs of the first processing system. In other examples, the second processing system may detect an unauthorized modification by the presence of malicious code.

If the first processing system has been compromised, process <NUM> continues at (<NUM>). At (<NUM>), the second processing system obtains updated configuration data and/or an updated instruction set for the primary process. The updated configuration data may be obtained locally from memory <NUM> for example, or remotely from information transmitted by a ground station for example.

At (<NUM>), the first processing system is reconfigured and/or preprogrammed based on the updated configuration data and/or instruction set. For example, the second processing system may transmit an updated configuration data file and/or instruction set to the first processing system. One or more processing units of the first processing system can be reprogrammed and/or the programmable logic array can be reconfigured. In some examples, the primary process can be reconfigured to avoid a subsequent unauthorized modification of the first processing system. For example, the primary process can be modified to avoid a subsequent exploit of a vulnerability that may have been used to have initially compromised the first processing system.

At (<NUM>), function control is transferred back to the first processing system. In some examples, (<NUM>) includes transferring function control from the backup process to the reconfigured primary process.

If the first processing system is not compromised, process <NUM> continues at (<NUM>). At (<NUM>), process <NUM> restarts the first processing system or restarts execution of the first process by the first processing system. For example, the second processing system may restart execution of the first process or restart the first processing system in its entirety in an effort to alleviate the cause of the invalid output. For example, the invalid output may be detected as a loss of the output signal due to a power or other failure of the first processing system. Restarting the first processing system or the first process may again cause the output to be validly generated. At (<NUM>), function control is transferred to the primary process if function control was earlier transferred to the backup process at (<NUM>).

<FIG> is a block diagram depicting first circuit board <NUM> and a monitoring process that can be performed by second processing system <NUM> in accordance with example embodiments of the disclosed technology. In another example, a similar process may be performed by first processing system <NUM>.

First processing system <NUM> is depicted with real-time processing unit (RPU) <NUM> executing a primary control process for a first UAV function. By way of example, the primary control process may include a first instruction set stored in memory and executed by RPU <NUM>. Primary control process <NUM> generates an output <NUM> that is provided to one or more support processes <NUM>. Support processes <NUM> are associated with the first UAV function. By way of example, the primary control process may be an autopilot process configured to generate output commands for navigating of piloting the UAV based on sensor data. The one or more support processes <NUM> may include a pulse width modulation (PWM) servo command generation unit. The PWM servo command generation unit may receive the commands from output <NUM> of the autopilot process and generate as an output <NUM>, the appropriate PWM servo commands. In another example, the primary control process <NUM> may be a payload delivery control process. Although PWM servo commands are described, any type of servo command signal and servo command generation unit may be used, such as serial data bus, analog phase/amplitude, etc..

Second processing system <NUM> includes one or more support processes <NUM> that are also associated with the first UAV function. By way of example, support processes <NUM> may include a de-serializer process in some examples. The de-serializer process may receive serial PWM servo commands and generate PWM commands that can be stored in the buffer. Support processes <NUM> provide an output <NUM> to process monitor/controller <NUM>. Process monitor/controller <NUM> is configured to determine whether primary control process <NUM> is generating a valid output. In one example, process monitor/controller <NUM> is configured to determine whether an output <NUM> is received from support processes <NUM> in order to determine whether the primary control process <NUM> is generating a first output <NUM>. In another example, process monitor/controller <NUM> is configured to determine whether an output <NUM> is received by support processes <NUM> in order to determine whether the primary control process <NUM> is generating a first output <NUM> that is valid. In another example, process monitor/controller <NUM> is configured to determine whether the content of output <NUM> is valid in order to determine whether first output <NUM> is valid. If process monitor/controller <NUM> determines that the first output <NUM> is valid, an output <NUM> is provided. In one example, output <NUM> includes PWM servo commands received from support processes <NUM>.

Support processes <NUM> are further configured to receive a second output <NUM> from a backup control process <NUM> executed by APU <NUM> of the second processing system <NUM>. For example, backup control process <NUM> may be a backup autopilot process or a backup payload delivery process. Support processes <NUM> may receive commands from the backup autopilot process and generate PWM servo commands in one example. Support processes <NUM> generate an output <NUM> which is provided to process monitor/controller <NUM>. If process monitor/controller <NUM> determines that the output <NUM> of the primary control process <NUM> is invalid, it can generate an output <NUM> including the output <NUM> of the backup control process.

In some implementations, processor monitor/controller <NUM> may determine whether the first output <NUM> of the first processing system <NUM> is valid based on comparing the first output to the second output <NUM> from the second processing system. For example, process monitor/controller <NUM> can determine whether the first output <NUM> and the second output <NUM> match or are otherwise have a concurrence. If there is a concurrence between the first output <NUM> and the second output <NUM>, the processor monitor/controller <NUM> may determine that the first output <NUM> is valid.

<FIG> is a specific example where process monitor/controller <NUM> enables a backup control process <NUM> in response to an invalid output associated with the primary control process <NUM>. In other examples, process monitor/controller <NUM> can be configured to enable a vehicle device or initiate a particular function based on the output of a process executed by each processing system. For example, a payload delivery system may be enabled or activated based on a concurrence between an output generated by the first processing system and an output generated by the second processing system.

Referring now to <FIG>, additional details of processing system <NUM> of control box <NUM> are described in accordance with example embodiments of the disclosed technology. More particularly, <FIG> is a block diagram depicting a subset of the hardware components of first processing system <NUM>, along with an example of a software architecture used to control the hardware components.

<FIG> depicts the various processing elements of processing system <NUM> as hardware layer <NUM>. More specifically, hardware layer <NUM> includes the volatile programmable logic array <NUM>, real-time processing unit (RPU) <NUM>, and application processing unit (APU) <NUM>. Although not shown, hardware layer <NUM> may also include graphics processing unit <NUM> and other computing elements. <FIG> additionally depicts an operating system layer <NUM> provisioned from the hardware layer <NUM>. A virtual machine layer <NUM> is provisioned using a hypervisor <NUM> or other virtualization layer to virtualize one or more processors.

A standalone operating system (OS) <NUM> is provisioned in operating system layer <NUM> using at least a first processor of processing system <NUM>. In the particular example of <FIG>, the standalone OS <NUM> is provisioned using real-time processing unit (RPU) <NUM>. The standalone OS <NUM> may be provisioned to control one or more processors of RPU <NUM>. In some examples, standalone OS <NUM> is a lightweight or simple operating system configured to manage critical processes or applications of UAV <NUM>. For instance, <FIG> depicts one or more critical vehicle control processes <NUM> and one or more critical mission control processes <NUM> that been configured for execution by standalone OS <NUM>. In some examples, OS <NUM> is configured to only execute critical vehicle control processes <NUM>. In other examples, OS <NUM> is configured to only execute critical mission control processes <NUM>.

In various examples, critical vehicle control processes may refer to a category or class of control processes that are critical to safe operation of UAV <NUM>. Various criteria may be used to classify different processes. For example, certain aviation standards may specify that vehicle and/or mission processes including computer readable instructions be subject to various levels of certification. These levels of certification may be applied in order to guarantee or to increase safe operation of UAV <NUM>. Thus, critical vehicle control process <NUM> and critical mission control processes <NUM> may refer in some examples to control processes that are subject to a highest level certification. However, it will be appreciated that other control processes at lower levels of certification may also be deemed critical for placement in standalone OS <NUM> in various implementations. In examples, a primary autopilot process is a critical vehicle control process <NUM>. In examples, a process for controlling at least one propulsion and movement device of the UAV is a critical vehicle control process.

A hypervisor <NUM> is provisioned using the application processing unit (APU) <NUM>. In another example, hypervisor <NUM> may be used to virtualize APU <NUM> and/or volatile programmable logic array <NUM>. For example, the FPGA may be used as computational resources for the virtualized APU <NUM>. Hypervisor <NUM> may be executed by APU <NUM> in some examples. While a hypervisor <NUM> is depicted in <FIG>, other techniques for virtualizing hardware processing elements may be used.

Multiple domains including domain <NUM> (DOMO), domain <NUM> (DOM1), and domain <NUM> (DOM2) are provisioned in virtual machine layer <NUM> using hypervisor <NUM>. It will be appreciated that three domains are depicted by way of example only, as any number of domains may be provisioned in accordance with a particular implementation. In <FIG>, domain <NUM> is a host domain provisioned to manage the other virtual machines and virtual machine layer <NUM>. Domain <NUM> includes a virtual machine (VM) manager <NUM>, an input output (I/O) mediator <NUM>, and a host operating system (OS) <NUM>. VM manager <NUM> can manage provisioning of virtual machines using hypervisor <NUM>. I/O mediator <NUM> can mediate communications such as packets, objects, or other data between virtual machines and between a virtual machine and the underlying layers of computing system <NUM>.

Domain <NUM> is a first guest domain configured using hypervisor <NUM>. In <FIG>, domain <NUM> hosts a first virtual machine (VM) <NUM>. In the example depicted, the first virtual machine <NUM> is a real-time virtual machine. For instance, domain <NUM> can be configured to execute real-time processes. Real-time processes may include processes that need fast execution to deliver results for vehicle and/or mission control functions. In some examples, domain <NUM> may be provisioned using RPU <NUM>. In other examples, domain <NUM> may be provisioned using APU <NUM>. A first guest operating system (OS1) <NUM> is provisioned for the real-time virtual machine <NUM>. Domain <NUM> configures real-time VM <NUM> to execute vehicle control processes <NUM> and first mission control processes <NUM>. In some examples, vehicle control processes <NUM> are at a lower certification level than critical vehicle control processes <NUM>. Similarly, first mission control processes <NUM> may be at a lower certification level than critical mission control processes <NUM>. In some examples, a primary navigation process may be a vehicle control process <NUM>. For example, an overall navigation process including an autopilot navigation process may be configured in domain <NUM>. A primary autopilot process may be configured in the standalone operating system.

Domain <NUM> is a second guest domain configured using hypervisor <NUM>. In <FIG>, domain <NUM> hosts a second virtual machine (VM) <NUM>. In the example depicted, the second virtual machine <NUM> is a non-real-time virtual machine. For instance, domain <NUM> can be configured to execute less time critical processes. Less time critical processes may include high intensive computing requirements in some examples. For example, sensor processing of dense sensor data such as may be acquired by various image, radar, lidar, or other sensors may be executed in virtual machine <NUM>. In some examples, domain <NUM> may be provisioned using RPU <NUM>, APU <NUM>, and/or volatile programmable logic array <NUM>. A second guest operating system (OS2) <NUM> is provisioned for the non-real-time virtual machine <NUM>. <FIG> depicts a set of second mission control processes <NUM> executed by virtual machine <NUM>. In some examples, second mission control processes <NUM> are at a lower certification level than mission control processes <NUM>. Although not shown, vehicle control processes may also be configured for execution by domain <NUM>.

Standalone OS <NUM> is an example of a first partitioned operating environment. More particularly, standalone OS <NUM> is part of a first hardware partition <NUM> corresponding to RPU <NUM>. Domain <NUM> is an example of a second partitioned operating environment. More particularly, domain <NUM> is part of a second hardware partition <NUM> corresponding to APU <NUM>. Hardware partition <NUM> includes software partitions <NUM>, <NUM>, and <NUM> from a virtualization of APU <NUM>. Domain <NUM> is a part of software partition <NUM>. Domain <NUM> is an example of a third partitioned operating environment. More particularly, domain <NUM> is part of the second hardware partition <NUM> and the second software partition <NUM>. Domain <NUM> is an example of a fourth partitioned operating environment. More particularly, domain <NUM> is part of the second hardware partition <NUM> and the third software partition <NUM>.

Accordingly, standalone OS <NUM>, domain <NUM>, domain <NUM>, and domain <NUM> are isolated from one another using hardware partitions and/or software partitions. Specifically, standalone OS <NUM> is in its own hardware partition and thus, it is isolated from operating systems <NUM>, <NUM>, and <NUM>, including virtual machines <NUM> and <NUM>. Domains <NUM>, <NUM>, and <NUM> including virtual machines <NUM> and <NUM> are in the same hardware partition <NUM>. However, each domain and corresponding virtual machine are in isolated software partitions.

In the specific example of <FIG>, standalone OS <NUM> can be a high integrity partition configured for critical processes. By isolating (also referred to as partitioning) standalone OS <NUM> from other domains, high levels of certifications as may be required for critical vehicle control processes <NUM> and critical mission control processes <NUM> may not be required for processes executed in the other domains. In one example, standalone OS <NUM> is provisioned from RPU <NUM>. On the other hand, the other domains <NUM>, <NUM>, <NUM> are provisioned using APU <NUM>. In this manner, standalone OS <NUM> is a hardware partitioned operating environment. That is, standalone OS <NUM> is provisioned using different hardware than the other domains as well as using a separately provisioned operating system.

<FIG> depicts one example of a software system configured for processing system <NUM>. It will be appreciated that a similar software system may be configured for processing system <NUM>, although this is not required.

<FIG> is a flowchart describing a process <NUM> of configuring a software system for a control system in accordance with example embodiments of the disclosed technology. Process <NUM> may be performed by any one of the processing units and/or programmable logic arrays of processing systems <NUM> or <NUM>. In other examples, process <NUM> may be performed by another computing system.

At (<NUM>), a first operating system is provisioned using a first processing unit of an integrated circuit. For example, a standalone operating system <NUM> may be provisioned at RPU <NUM> as shown in <FIG>. The standalone operating system may be a high integrity partition in some examples. For example, the standalone operating system may be a high integrity partitioned operating environment isolated from other operating environments.

At (<NUM>), one or more critical vehicle control processes and/or critical mission control processes are configured in the standalone operating system. For example, the standalone operating system may be configured to execute critical vehicle and/or mission control processes. In some examples, critical vehicle control processes are used to control at least one propulsion and movement device the UAV.

At (<NUM>), a virtualization layer is created using a second processing unit. For example, a hypervisor can be configured using an application processing unit such as APU <NUM> as shown in <FIG>.

At (<NUM>), other processing elements can be virtualized. It is noted that (<NUM>) is optional and is not required to be performed. By way of example, (<NUM>) may include virtualizing a portion of programmable logic array <NUM>.

At (<NUM>), a first virtual machine is provisioned from the virtualization layer. For example, a first virtual machine such as real-time VM <NUM> can be provisioned in a first domain <NUM> as shown in <FIG>. Provisioning the first virtual machine may include provisioning the first virtual machine using the second processing unit. For example, the first virtual machine may be provisioned using APU <NUM>. The first virtual machine is a partitioned operating environment isolated from the standalone operating system in example embodiments. More particularly, the first virtual machine is in a different hardware partition relative to the standalone operating system. For example, the first virtual machine may be associated with APU <NUM> while the standalone operating system is associated with RPU <NUM>. In this manner, standalone operating system <NUM> may be considered a high integrity partition due to its hardware and software isolation from other operating environments.

At (<NUM>), additional vehicle and/or mission control processes are configured in the first virtual machine. For example the first virtual machine can be configured to execute one or more vehicle control processes and/or mission control processes. It examples, the vehicle and mission control processes configured for execution at (<NUM>) are at a lower certification level than those configured at (<NUM>). The first virtual machine can be isolated from the standalone operating system. In this manner, computer readable instructions associated with the vehicle and/or mission control processes at (<NUM>) may not be subject to the same level of certification as vehicle and/or mission control processes at (<NUM>).

At (<NUM>), a second virtual machine is provisioned from the virtualization layer. For example, a second virtual machine such as non-real-time VM <NUM> can be provisioned at a second domain <NUM> as shown in <FIG>. The second virtual machine may include a second operating system. For example, a guest operating system such as guest OS1 <NUM> as shown in <FIG> may be provisioned in the second virtual machine. Provisioning the second virtual machine may include provisioning the second virtual machine using the second processing unit. For example, the second virtual machine may be provisioned using APU <NUM>.

At (<NUM>), additional vehicle and/or mission control processes may be configured at the second virtual machine. For example, the second virtual machine can be configured to execute one or more vehicle control processes and/or mission control processes at a lower certification level than those of (<NUM>). The second virtual machine can be isolated from the standalone operating system and the first virtual machine. In this manner, computer readable instructions associated with the vehicle and/or mission control processes at (<NUM>) may not be subject to the same level of certification as vehicle and/or mission control processes at (<NUM>). The second virtual machine is in a different hardware partition relative to the standalone operating system. The second virtual machine is in a different software partition relative to the first virtual machine.

In accordance with example embodiments, programmable logic array <NUM> and/or <NUM> may be configured with one or more computational accelerators for onboard sensor processing and other vehicle control and/or mission control processes. One or more memory blocks <NUM> can be dedicated to the programmable logic arrays in order to facilitate accelerated processing. Such processes may be suitable for image classification, object detection and tracking, sensor relative navigation, robotic perception/cognition, geo-registration of sensor collection for targeting and alternative navigation sources for example, as well as software defined radio including signal interference collection and flexible data links for payload data dissemination.

<FIG> is a flowchart describing a process <NUM> for virtualizing at least a portion of the programmable logic array in accordance with example embodiments of the disclosed technology to configure a computational accelerator. For example, process <NUM> may be used to configure a flash-based FPGA and/or a RAM-based FPGA.

At (<NUM>), one or more computational accelerators are configured in a programmable logic array. For example, (<NUM>) may include providing configuration data to an FPGA for configuring the FPGA as a computational accelerator.

At (<NUM>), at least a portion of the computational accelerator is virtualized. In various examples, (<NUM>) may include virtualizing an FPGA and configuring the FPGA in accordance with configuration data for a computational accelerator. Block <NUM> may include virtualizing an instance of the computational accelerator without virtualizing the entire FPGA.

At (<NUM>), at least one interface for accessing the virtualized computational accelerator is provided. For example, one or more protocols for exchanging objects and or other data units may be established for interfacing with the computational accelerator. In this manner, the computational accelerator can be configured to receive objects from other processing elements such as a processing unit and generate an output based on accelerated computations performed on the object. Accordingly, a first process executing at a processing unit may interface with a second process executing in the FPGA. The first process may pass objects or other data to the FPGA for faster computational processing. Results may then be received and used within the first process at the processing unit. In this manner, a processing system may provide a uniquely situated architecture for handling the unique processing needs of a UAV.

<FIG> is a flowchart describing a process <NUM> of using a virtualized architecture for accessing a computational accelerator for onboard sensor processing associated with the UAV in accordance with example embodiments of the disclosed technology. At (<NUM>), an object including an output from a process executing in a virtual machine of the processing system is received at a programmable logic array. For example, the object may be received from a first vehicle control process executing in a virtual machine provisioned at APU <NUM>.

At (<NUM>), the object is input to a computational accelerator configured in the programmable logic array. The object can be input to the computational accelerator using an interface configured for accessing the accelerator. In one example, the interface is provided by virtualizing the computational accelerator in the FPGA. In another example, the interface is provided without virtualizing the computational accelerator.

At (<NUM>), and output is generated using the computational accelerator in the FPGA. In one example the output includes an object including a value calculated using the computational accelerator. In another example, the output includes a value which is then placed into an object by the interface configured for the computational accelerator.

At (<NUM>), an object including an output from the computational accelerator is provided to the virtual machine from which the original object was received at (<NUM>). At (<NUM>), the object from the FPGA is accessed and the output from the computational accelerator processed at the virtual machine. In this manner, an object from the virtual machine can be passed to the FPGA and an output return from the computational accelerator. The output from the computational accelerator can then be used again by the process executing the virtual machine.

Referring now to <FIG>, further embodiments of improved control boxes <NUM> and components thereof are generally provided. As discussed, control box <NUM> in accordance with the present disclosure generally houses the various electrical/computing components which control operation of an unmanned aerial vehicle ("UAV"), and the control box <NUM> is thus generally mounted on the UAV. Control boxes <NUM> in accordance with the present disclosure are particularly advantageous due to their modular design, wherein various components of the control boxes <NUM> such as the heat sink, cover, and/or stiffener, as discussed herein, are each interchangeable with various different designs for each such component. Certain features as discussed herein help to facilitate such modularity. Additionally, as discussed herein, various features of such control boxes <NUM> such as the heat sink, the stiffener, and the system on module ("SOM") circuit board include advantageous heat transfer features for transferring heat from the SOM circuit board and from the control box <NUM> generally. Other advantageous features will be discussed herein.

A control box <NUM> in accordance with the present disclosure may define a lateral direction <NUM>, a longitudinal direction <NUM>, and a transverse direction <NUM>, as shown. Such directions <NUM>, <NUM>, <NUM> may together define an orthogonal coordinate system for the control box <NUM>.

Control box <NUM> may include a housing <NUM> which defines an interior <NUM>. The housing <NUM> in exemplary embodiments includes a cover <NUM> and one or more stiffeners <NUM>. In some embodiments, only a single stiffener <NUM> is utilized in a control box <NUM>, although in alternative embodiments more than one stiffener <NUM> may be utilized. In embodiments wherein the housing <NUM> includes a cover <NUM> and stiffener(s) <NUM>, at least one such stiffener <NUM> is removably connected in contact with the cover <NUM>, and the stiffeners <NUM> are stacked on each other and the housing <NUM> along the transverse direction <NUM>. Control box <NUM> may further include a heat sink <NUM>. The heat sink <NUM> may be removably connected to the housing <NUM>, such as in contact with one of the plurality of stiffeners <NUM>. The heat sink <NUM> may further be stacked on the stiffeners <NUM> and the housing <NUM> along the transverse direction <NUM>.

One or more circuit boards may be disposed within the interior <NUM>. For example, a first circuit board <NUM> may be disposed in the interior <NUM>. In exemplary embodiments, the first circuit board <NUM> is a system on module ("SOM") circuit board such as the example SOM circuit board <NUM> as discussed herein. Such first circuit board <NUM> may in exemplary embodiments be positioned between the housing <NUM> and the heat sink <NUM>, such as between a stiffener <NUM> and the heat sink <NUM>. Further, the first circuit board <NUM> may be in contact with the heat sink <NUM> such that heat from the first circuit board <NUM> is dissipated from the first circuit board <NUM> through the heat sink <NUM>. Additionally, the first circuit board <NUM> may be in contact with a stiffener <NUM>.

For example, the first circuit board <NUM> may include one or more computing components. Such computing components may include a first processing system <NUM>, a second processing system <NUM>, and/or one or more memory blocks <NUM>, all of which are discussed in detail herein, such as in the context of SOM circuit board <NUM>. Further, a thermal interface material <NUM> (discussed in detail below in the context of SOM circuit board <NUM>) may be disposed on one or more of such computing components. In exemplary embodiments, the first circuit board <NUM>, such as the thermal interface material <NUM> disposed on one or more of the computing components, may contact the heat sink <NUM> and/or a stiffener <NUM>.

In some embodiments, the thermal interface material <NUM> may be in contact with the heat sink <NUM>. In particular, the thermal interface material <NUM> that is disposed on one or more computing components (such as first processing system <NUM>, a second processing system <NUM>, and/or one or more memory blocks <NUM> that are mounted on a first face surface <NUM> of the circuit board <NUM> as discussed below in the context of the SOM circuit board <NUM>) may be in contact with the heat sink <NUM>, such as a base <NUM> thereof.

Additionally or alternatively, the stiffener <NUM> may include a plurality of fingers <NUM>. Fingers <NUM> are generally planer inner surfaces of the stiffener <NUM> which contact other components for support and heat transfer purposes. The first circuit board <NUM> may contact such fingers <NUM>. In particular, the thermal interface material <NUM> that is disposed on one or more computing components (such as one or more memory blocks <NUM> that are mounted on a second face surface <NUM> of the circuit board <NUM> as discussed below in the context of the SOM circuit board <NUM>) may be in contact with the fingers <NUM>.

In exemplary embodiments, the stiffener <NUM> includes an outer frame <NUM> and one or more cross-members <NUM>. Stiffener <NUM> may additionally include fingers <NUM>. When first circuit board <NUM> contacts stiffener <NUM>, the first circuit board <NUM> may contact the outer frame <NUM> and/or one or more of the cross-members <NUM>, and may further contact fingers <NUM> as discussed above.

In exemplary embodiments, heat sink <NUM> is formed from a metal. Heat sink <NUM> may include a base <NUM>. Base may in exemplary embodiments be in contact with the first circuit board <NUM>, such as components thereof as discussed above. Further, in some exemplary embodiments (not shown), heat sink <NUM> may include a plurality of fins <NUM> which extend externally from the base <NUM>. In these embodiments, heat sink <NUM> may provide convective heat transfer from the control box <NUM> via fins <NUM>. In other embodiments, as illustrated in <FIG>, no fins <NUM> may be provided and heat sink <NUM> may provide conductive heat transfer from the control box <NUM> via contact of the base <NUM> with other components in, for example, the subject UAV to which the control box <NUM> is mounted. In still other embodiments, heat sink <NUM> may further include single use or reversible phase change materials, liquid cooling materials, and/or other suitable components for facilitating heat transfer.

Control box <NUM> may further include a second circuit board <NUM>. Second circuit board <NUM> may, for example, be a carrier card-type circuit board which generally includes communications related components, such as sonar, radar, GPS, radio, etc. related components, including various integrated circuits forming interface circuits. The second circuit board may be disposed within the interior <NUM>. For example, such second circuit board <NUM> may in exemplary embodiments be positioned between the cover <NUM> and the stiffener <NUM>. Further, the second circuit board <NUM> may be in contact with the stiffener <NUM>.

In example embodiments, second circuit board <NUM> is in operative communication with first circuit board <NUM>. For example, second circuit board <NUM> may further include one or more input/output connectors <NUM> which are positioned on the second circuit board <NUM> to operatively contact mating input/output connectors (such as connectors <NUM> in SOM circuit board <NUM> embodiments) of the first circuit board <NUM>.

In some embodiments, second circuit board <NUM> may further include one or more sensor connectors <NUM>. Such sensor connectors <NUM> may extend from the housing <NUM>, such as along the longitudinal direction <NUM> as shown in <FIG> or in another suitable direction. These sensor connectors <NUM> may be ports for connection of the second circuit board <NUM> to suitable external sensors or other secondary devices <NUM> (such as those discussed herein) which may, for example, be mounted on the UAV on which the control box <NUM> is mounted.

Control box <NUM> may additionally include one or more input/output connectors <NUM> which extend from the housing <NUM>. In exemplary embodiments, one or more of such connector(s) <NUM> are components of the second circuit board <NUM>. Such input/output connectors <NUM> may connect the control box <NUM> and components thereof to other components of, for example, the UAV on which the control box <NUM> is mounted. In some embodiments, as illustrated in <FIG>, the input/output connector(s) <NUM> extend from the housing <NUM> along the longitudinal direction <NUM>, such as through an end faceplate <NUM> of the housing <NUM>. In other embodiments, the input/output connector(s) <NUM> extend from the housing <NUM> along the transverse direction <NUM>, such as through the cover <NUM>.

In some embodiments, control box <NUM> may further include a mezzanine card <NUM>. Mezzanine card <NUM> may be disposed within interior <NUM>, and may be in operative communication with the second circuit board <NUM>. Mezzanine card <NUM> may, for example, be disposed between second circuit board <NUM> and cover <NUM>. In some embodiments, one or more of the input/output connectors <NUM> are components of the mezzanine card <NUM>.

As shown, the heat sink <NUM> and components of the housing <NUM> may include through-holes. The various through-holes may advantageously align to facilitate the modularity of the various components of control box <NUM>. For example, a plurality of through holes <NUM> may extend through the base <NUM> of heat sink <NUM>, such as along the transverse direction <NUM>. Such through holes <NUM> may be arranged in a pattern. Further, a plurality of through holes may extend through the housing <NUM>, such as along the transverse direction <NUM>. Such through holes may be arranged in a pattern. Such through holes may, for example, include through holes <NUM> which extend through the cover <NUM> along the transverse direction <NUM> and in a pattern, and through holes <NUM> which extend through the stiffener <NUM> along the transverse direction <NUM> and in a pattern. In exemplary embodiments, the patterns of through holes in the base <NUM> and housing <NUM>, such as the through holes <NUM>, <NUM>, and <NUM>, are identical. Accordingly, fasteners may be inserted through the through holes <NUM>, <NUM>, <NUM> to fasten such components of the control box <NUM> together. Notably, such identical pattern may extend to a variety of different types of heat sinks <NUM> and housings <NUM> (and covers <NUM> and stiffeners <NUM> thereof), such that different versions of such components can be swapped with each other in a module fashion.

When the heat sink <NUM> contacts the housing <NUM>, such as the stiffener <NUM> thereof, such components may fit together using a "tongue-and-groove" type feature. Such feature advantageously orients the components relative to one another to ensure a proper fit, and also advantageously acts as an electro-magnetic interference ("EMI") filter.

Referring now to <FIG>, a control box <NUM> in accordance with the present disclosure may include a system on module ("SOM") circuit board <NUM>, which may be the first circuit board <NUM> as discussed above. The SOM circuit board <NUM> may define a lateral direction <NUM>, a longitudinal direction <NUM>, and a transverse direction <NUM>, as shown. Such directions <NUM>, <NUM>, <NUM> may together define an orthogonal coordinate system for the SOM circuit board <NUM>. When the SOM circuit board <NUM> is installed in a control box <NUM>, the directions <NUM>, <NUM>, <NUM> may correspond to the respective directions <NUM>, <NUM>, <NUM>.

SOM circuit board <NUM> may have a main body <NUM> which includes a plurality of outer surfaces. For example, main body <NUM> includes a first face surface <NUM> and a second opposing face surface <NUM>, both of which generally extend within planes defined by the lateral direction <NUM> and longitudinal direction <NUM>. Main body <NUM> further includes a first end surface <NUM> and an opposing second end surface <NUM>, both of which generally extend within planes defined by the lateral direction <NUM> and the transverse direction <NUM>. Main body <NUM> further includes a first side surface <NUM> and an opposing second side surface <NUM>, both of which generally extend within planes defined by the longitudinal direction <NUM> and the transverse direction <NUM>.

In generally, the SOM circuit board <NUM> and main body <NUM> thereof has a hyperrectangular shape, as shown. Accordingly, first and second end surface <NUM>, <NUM> also each have a length <NUM>, which is a maximum length along the lateral direction <NUM>. First and second side surfaces <NUM>, <NUM> each also have a length <NUM>, which is a maximum length along the longitudinal direction <NUM>. As shown, in exemplary embodiments, the maximum lengths <NUM> are greater than the maximum lengths <NUM>.

The SOM circuit board <NUM> may further include a plurality of computing components. Each computing component may be mounted on the main body <NUM>, such as on the first face surface <NUM> or second face surface <NUM>. For example, the computing components may include a first processing system <NUM>, a second processing system <NUM>, and a plurality of memory blocks <NUM>. Notably, the first and second processing systems <NUM>, <NUM> and the memory blocks <NUM> may in exemplary embodiments be integrated together in a cohesive computing system with the two processing systems <NUM>, <NUM> operating together. Accordingly, for example, the first processing system <NUM> can monitor and back up the second processing system <NUM> and the second processing system <NUM> can monitor and back up the first processing system <NUM>.

In some embodiments, for example, the first processing system <NUM> may be a random access memory ("RAM") based processing system. Additionally or alternatively, the second processing system <NUM> may in some embodiments be a flash memory-based processing system. Additionally or alternatively, the memory blocks <NUM> may be RAM memory blocks.

As shown, in exemplary embodiments, the first and second processing systems <NUM>, <NUM> may be mounted on the first face surface <NUM> of the main body <NUM>. Alternatively, however, one or both of the first and second processing systems <NUM>, <NUM> may be mounted on the second face surface <NUM> of the main body <NUM>. Further, in some embodiments, at least one or more of the memory blocks <NUM> may be mounted on the first face surface <NUM>. Additionally or alternatively, at least one or more of the memory blocks <NUM> may be mounted on the second face surface <NUM>.

In some embodiments, a thermal interface material <NUM> may be disposed on one or more of the computing components. The thermal interface material <NUM> may facilitate heat transfer from such computing components to other components of the control box <NUM>, as discussed herein. Suitable thermal interface materials <NUM> may, for example, be relatively compliant materials which may for example be curable. In exemplary embodiments, such materials <NUM> may be thixotropic materials. In exemplary embodiments, such materials <NUM> may have a thermal conductivity of between <NUM> and <NUM> W/m-K, such as between <NUM> and <NUM> W/m-K, such as <NUM> W/m-K. One suitable materials is Gap Filler 3500S35, which is commercially available from The Bergquist Company.

In exemplary embodiments, the thermal interface material <NUM> may be disposed on the memory blocks <NUM>, such as one or more of the memory blocks <NUM> mounted on the first face surface <NUM> and/or one or more of the memory blocks <NUM> mounted on the second face surface <NUM>. Additionally or alternatively, the thermal interface material <NUM> may be disposed on the first processing system <NUM> and/or the second processing system <NUM>.

One or more input/output connectors <NUM> may additionally be mounted on the main body <NUM>. These connectors <NUM> may connect the SOM circuit board <NUM> to other circuit boards, as discussed herein, in the control box <NUM>, thus allowing communication between the SOM circuit board <NUM> and such other circuit boards. The connectors <NUM> may, for example, be mounted on the second face surface <NUM> as shown, or alternatively may be mounted on the first face surface <NUM>. In some embodiments, the connectors <NUM> may be disposed proximate the first side surface <NUM>, and thus closer to the first side surface <NUM> than the second side surface <NUM> along the lateral direction <NUM>. In some of these embodiments, no connectors <NUM> may be provided proximate the second side surface <NUM>. Further, longitudinal axes of the connectors <NUM> may be aligned along the longitudinal direction <NUM>, as shown.

As further illustrated, a plurality of mounting holes <NUM> may extend through the main body <NUM>. One or more of these mounting holes <NUM> may, for example, be utilized to connect the SOM circuit board <NUM> to other components in the control box <NUM>. Each mounting hole <NUM> may extend along the transverse direction <NUM> through and between the first face surface <NUM> and the second face surface <NUM>.

The locations of the mounting holes <NUM> in the main body may be particularly advantageous. For example, a first array <NUM> of the mounting holes <NUM> may be disposed proximate the first side surface <NUM>, and in exemplary embodiments between the connectors <NUM> and the first side surface <NUM> along the lateral direction <NUM>. The mounting holes <NUM> of the first array <NUM> may be spaced apart from each other along the longitudinal direction <NUM>. In exemplary embodiments, the first array <NUM> may include three or more mounting holes, although in alternative embodiments two mounting holes may be utilized. A second array <NUM> of the mounting holes <NUM> may be disposed proximate the second side surface <NUM>, and in exemplary embodiments may be spaced along the lateral direction <NUM> an equal distance from the second side surface <NUM> as the first array <NUM> is from the first side surface <NUM>. The mounting holes <NUM> of the second array <NUM> may be spaced apart from each other along the longitudinal direction <NUM>. In exemplary embodiments, the second array <NUM> may include three or more mounting holes, although in alternative embodiments two mounting holes may be utilized. The first and second arrays may advantageously both connect the SOM circuit board <NUM> to other components in the control box <NUM> and minimize any relative motion of the SOM circuit board <NUM> with respect to such components.

Additionally, one or more third mounting holes <NUM> may be disposed between the first array <NUM> and the second array <NUM> along the lateral direction <NUM>. In exemplary embodiments, the one or more third mounting holes <NUM> may be positioned generally centrally between the first side surface <NUM> and the second side surface <NUM>, such as along the lateral direction <NUM>. The third mounting holes <NUM> may this be equally spaced from the first array <NUM> and the second array 244along the lateral direction <NUM>. Further, in embodiments wherein only a single third mounting hole <NUM> is utilized, the third mounting hole <NUM> may be positioned generally centrally between the first end surface <NUM> and the second end surface <NUM>, such as along the longitudinal direction <NUM>. The third mounting hole(s) <NUM> may be particularly advantageous, as such hole(s) <NUM> reduce resonant frequency issues during use of the SOM circuit board <NUM> and provide improved stiffness to the SOM circuit board <NUM>. In some embodiments, a plurality of vias <NUM> may be provided in SOM circuit board <NUM>. Each via may extend through the body <NUM> along the transverse direction <NUM>, and may protrude from the first face surface <NUM> and/or second face surface <NUM>. Vias <NUM> may be located proximate the first side surface <NUM> and/or the second side surface <NUM>. Vias <NUM> may in exemplary embodiments be formed from a metallic material, such as gold or copper, and may serve as heat transfer conduits to transfer heat from within the main body <NUM> and transfer this heat from the main body <NUM> and SOM circuit board <NUM> generally.

In some embodiments, one or more metallic coatings may be plated on the main body <NUM>, such as on the first face surface <NUM> and/or second face surface <NUM> thereof. The metallic coatings may serve as heat transfer conduits to transfer heat from the main body <NUM> and SOM circuit board <NUM> generally.

For example, a first metallic coating <NUM> may be plated on portions of the body <NUM> (such as on the first face surface <NUM> and/or second face surface <NUM> thereof) defining the plurality of mounting holes <NUM> (including those mounting holes in the first and second arrays <NUM>, <NUM> as well as the third mounting hole(s) <NUM>. Such coating <NUM> may be discretely plated on such portions of the body <NUM>, such that the various platings are not connected. In exemplary embodiments, such first metallic coating <NUM> is a copper coating, although in alternative embodiments gold or other suitable metals may be utilized.

Additionally or alternatively, a second metallic coating <NUM> may be plated the body <NUM> (such as on the first face surface <NUM> and/or second face surface <NUM> thereof). Such coating <NUM> may be located proximate the first and second side surfaces <NUM>, <NUM>, and may extend to such surfaces <NUM>, <NUM>, such as entirely along the length <NUM>. In embodiments wherein both first and second metallic coatings <NUM>, <NUM> are utilized, the second metallic coating <NUM> may be plated over the first metallic coating <NUM>. In exemplary embodiments, such second metallic coating <NUM> is a gold coating, although in alternative embodiments copper or other suitable metals may be utilized.

Some embodiments of the disclosed technology may be implemented as hardware, software, or as a combination of hardware and software. The software may be stored as processor readable code and implemented in a processor, as processor readable code for programming a processor for example. In some implementations, one or more of the components can be implemented individually or in combination with one or more other components as a packaged functional hardware unit (e.g., one or more electrical circuits) designed for use with other units, a portion of program code (e.g., software or firmware) executable by a processor that usually performs a particular function of related functions, or a self-contained hardware or software component that interfaces with a larger system, for example. Each hardware unit, for example, may include an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof. Alternatively or in addition, these components may include software stored in a processor readable device (e.g., memory) to program a processor to perform the functions described herein, including various mission and vehicle control processes.

Processing units can include any number and type of processor, such as a microprocessor, microcontroller, or other suitable processing device. Memory device(s) can include one or more computer-readable media, including, but not limited to, non-transitory computer-readable media, RAM, ROM, hard drives, flash drives, or other memory devices.

Memory blocks <NUM> and other memory described herein may can store information accessible by one or more processing units or logic array, including computer-readable instructions that can be executed by the one or more processor(s). The instructions can be any set of instructions that when executed by a processor, cause the processor to perform operations. The instructions can be software written in any suitable programming language or can be implemented in hardware. In some embodiments, the instructions can be executed by a processor to cause the processor to perform operations, such as the operations for controlling vehicle and/or mission functions, and/or any other operations or functions of a computing device.

Claim 1:
A computer-implemented method for controlling an unmanned vehicle (<NUM>) (UV), comprising:
provisioning a first operating system using a first processor (<NUM>) of an integrated circuit (<NUM>);
configuring the first operating system to execute a first vehicle control process (<NUM>) using the first processor (<NUM>);
provisioning at least one virtual machine using a second processor (<NUM>) of the integrated circuit (<NUM>), the at least one virtual machine is isolated from the first operating system; and
configuring the at least one virtual machine to execute a second vehicle control process (<NUM>).