Patent Description:
A nonvolatile memory device includes a plurality of memory cells which retain data even when power is blocked or stopped, and thus, are able to use the stored data again when power is supplied. A nonvolatile memory device may be used in one or more of a cellular phone, a digital camera, a portable digital assistant (PDA), a mobile computer device, a stationary computer device, and other devices.

Recently, research into using a three-dimensional (or vertical) NAND (or VNAND) structure in a chip for forming a next-generation neuromorphic computing platform or neural network has been conducted. An example of prior art may be found in document <CIT>. The document discloses a non-stoichiometric metal oxide and the metal oxide has an insufficient amount of oxygen to metal. However, no details are given about the oxygen deficient ratio.

Provided are a variable resistance memory device including a resistance change layer which may include many oxygen vacancies and/or an electronic device including the variable resistance memory device.

Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of variously described example embodiments.

According to various example embodiments, a variable resistance memory device includes: a resistance change layer including a metal oxide including a first metal element and a second metal element, the metal oxide having an oxygen deficient ratio greater than or equal to about <NUM>%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer and spaced apart from each other.

By way of example, embodiments may provide a Vertical Variable Resistance Device Using Transition Metal Oxide with High Oxygen Deficient Ratio.

In order to improve the oxygen vacancy content of an oxide resistive variable layer, it is proposed to use a metal oxide with a large oxygen deficient ratio as a variable resistance layer. Since a large oxygen deficient ratio means that there are fewer oxygen ions compared to the same metal cations, an oxide with a large oxygen deficient ratio is likely to have a high oxygen vacancy content. If there is a lot of oxygen vacancy in the variable resistance layer, the resistance state of the variable resistance layer can be easily changed, and thus the characteristics of the variable resistance device can be improved. In addition, if there is a lot of oxygen vacancies, the oxygen vacancy filament is easily formed when a voltage is applied. Thus, the forming voltage is lowered, so there is an advantage in that the operating voltage of the device is lowered.

According to an exemplary embodiment, there is provided a vertical variable resistance device using transition metal oxide with an oxygen deficient ratio of <NUM>% or more. Examples of the transition metal oxide may include Rb<NUM>O, TiO<NUM>, BaO, ZrO<NUM>, CaO, HfO<NUM>, SrO, SC<NUM>O<NUM>, MgO, Al<NUM>O<NUM>, SiO<NUM>, BeO, Nb<NUM>O<NUM>, NiO, Ta<NUM>O<NUM>, WO<NUM>, V<NUM>O<NUM>, La<NUM>O<NUM>, Gd<NUM>O<NUM>, CuO, MoO<NUM>, Cr<NUM>O<NUM>, MnO<NUM>, etc..

A content of the first metal element with respect to an entire metal of the resistance change layer may be greater than or equal to about <NUM> at%.

A content of the second metal element with respect to an entire metal of the resistance change layer may be less than or equal to about <NUM> at%.

The first metal element may include at least one of Ta, Ti, Sn, Cr, and Mn.

The second metal element may include at least one of Hf, Al, Nb, La, Zr, Sc, W, V, and Mo.

The variable resistance change layer may further include Si.

The semiconductor layer may be configured to receive a write voltage having an absolute value less than or equal to about 4V applied thereto.

The variable resistance memory device may further include an oxide layer between the semiconductor layer and the resistance change layer.

A thickness of the oxide layer may be less than a thickness of the resistance change layer.

The variable resistance change layer may include a first resistance change layer and a second resistance change layer sequentially arranged in a direction away from the semiconductor layer, and an oxygen deficient ratio of the first resistance change layer may be greater than an oxygen deficient ratio of the second resistance change layer.

At least three of the plurality of gate electrodes may be arranged periodically, and a pitch of the at least three of the plurality of gate electrodes may be less than or equal to about <NUM>.

The variable resistance memory device may further include a pillar, wherein the resistance change layer, the semiconductor layer, and the gate insulating layer may sequentially surround the pillar in a shell shape, and the plurality of gate electrodes and an insulating element may surround the gate insulating layer in a shell shape.

The pillar may include an insulating material.

The pillar may include a conductive material.

The pillar may be configured to receive a voltage that is greater than or equal to a voltage applied to the semiconductor layer.

According to various example embodiments, a variable resistance memory device includes: a resistance change layer including silicon and including a metal oxide having an oxygen deficient ratio that is greater than or equal to about <NUM>%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.

The variable resistance change layer may include at least one of Ta, Ti, Sn, Cr, and Mn.

A content of silicon with respect to a sum of metals and silicon of the resistance change layer may be less than or equal to about <NUM> at%.

According to various example embodiments, a variable resistance memory device includes: a resistance change layer including a first metal oxide having an oxygen deficient ratio that is greater than or equal to about <NUM>% and a second metal oxide having an oxygen deficient ratio that is less than <NUM>%, wherein a content of the first metal oxide is greater than a content of the second metal oxide; a semiconductor layer arranged on the resistance change layer; a gate insulating layer arranged on the semiconductor layer; and a plurality of gate electrodes arranged on the gate insulating layer to be apart from each other.

A content of a metal included in the second metal oxide with respect to entire metal included in the resistance change layer may be less than or equal to about <NUM> at%.

These and/or other aspects will become apparent and more readily appreciated from the following description of various example embodiments, taken in conjunction with the accompanying drawings in which:.

Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. Accordingly, example embodiments are merely described below, by referring to the figures, to explain aspects.

Expressions such as "in some embodiments," "according to various example embodiments," and the like, described in various parts of this specification do not necessarily refer to the same element as one another.

One or more example embodiments may be described as functional block components and various processing operations. All or part of such functional blocks may be realized by any number of hardware and/or software components configured to perform the specified functions. For example, the functional blocks of the disclosure may be implemented with one or more micro-processors or with circuit structures for certain functions. Also, for example, the functional blocks of the disclosure may be implemented with various programming or scripting languages. The functional blocks may be implemented with algorithms executed by one or more processors. Furthermore, the disclosure could employ conventional techniques for electronics configuration, signal processing and/or data control. Terms such as "mechanism," "element," "component," etc. are not limited to mechanical and physical components.

Furthermore, the connecting lines, or connectors shown in the drawings are intended to represent example functional relationships and/or physical or logical couplings between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may be present in a practical device.

Terms such as "comprise" or "include" used in this specification shall not be interpreted such that all of various components or various operations described in the specification are necessarily included. Rather, it shall be understood that some of the components or some of the operations may not be included, or additional components or operations may further be included.

Hereinafter, it will be understood that when an element is referred to as being "on" or "above" another element, the element can be directly over or under or on the right side or on the left side to the other element, or intervening elements may also be present therebetween. Hereinafter, various example embodiments will be described in detail with reference to the accompanying drawings.

Although terms such as "first," "second," etc. may be used herein to describe various elements, these terms do not limit the elements.

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

<FIG> is a diagram showing a schematic structure of a variable resistance memory device <NUM> according to various example embodiments, <FIG> is a circuit diagram of the variable resistance memory device <NUM> of <FIG>, and <FIG> is an example conceptual diagram showing an operation of the variable resistance memory device <NUM> of <FIG>.

Referring to <FIG>, the variable resistance memory device <NUM> may include a resistance change layer <NUM>, a semiconductor layer <NUM> arranged on the resistance change layer <NUM>, a gate insulating layer <NUM> arranged on the semiconductor layer <NUM>, and a plurality of gate electrodes <NUM> arranged on the gate insulating layer <NUM>. An insulating element <NUM> for insulating the plurality of gate electrodes <NUM> that are adjacent to each other may further be arranged between the plurality of gate electrodes <NUM>. However, it is only an example, and the insulating element <NUM> may be omitted.

The resistance change layer <NUM> may include a material having a resistance that varies according to an applied voltage. The resistance change layer <NUM> may change from a high-resistance state to a low-resistance state or from a low-resistance state to a high-resistance state according to one or more voltages applied to the gate electrodes <NUM>.

The resistance change layer <NUM> may realize a range of change that is desired with a less thickness than another charge trap-based variable resistance memory devices and/or other variable resistance memory device using a phase-change material. The thickness of the resistance change layer <NUM> may be less than or equal to <NUM> or less than or equal to <NUM>. The thickness of the resistance change layer <NUM> may be greater than or equal to <NUM>.

The resistance change layer <NUM> may include a material having a hysteresis characteristic. For example, the resistance change layer <NUM> may include a metal oxide. The resistance change layer <NUM> may include at least two of TaOx, TiOx, SnOx, CrOx, MnOx, HfOx, AlOx, SiOx, NbOx, LaOx, ZrOx, ScOx, WOx, VOx, and MoOx.

In some example embodiments, a resistance change of the resistance change layer <NUM> may be a phenomenon due to oxygen vacancies. When there are many oxygen vacancies in the resistance change layer <NUM>, a conductive filament may be formed, e.g. may be easily formed. The conductive filament may change the resistance change layer <NUM> to a low-resistance state so that current may flow through the resistance change layer <NUM>, and thus, the variable resistance memory device <NUM> may operate, e.g. to store logical data such as logical '<NUM>' or logical '<NUM>'. When the resistance change layer <NUM> includes a material in which oxygen vacancies may be easily formed, the variable resistance memory device <NUM> may operate well, for example even when an absolute value of a voltage applied to the resistance change layer <NUM> or the semiconductor layer <NUM> is decreased. The material of the resistance change layer <NUM> in which oxygen vacancies may be more easily formed will be described below.

The semiconductor layer <NUM> may include poly-Si or polysilicon such as doped or undoped polysilicon. Materials of the semiconductor layer <NUM> are not limited to poly-Si. For example, various semiconductor materials, such as one or more Ge, IGZO, GaAs, and the like, may be alternatively or additionally included in the semiconductor layer <NUM>.

A source electrode S and a drain electrode D may be connected to both ends of the semiconductor layer <NUM>, respectively.

The gate insulating layer <NUM> may include various types of insulating materials. For example, silicon oxide, silicon nitride, or silicon oxynitride may be included in the gate insulating layer <NUM>.

A voltage, e.g. the same or different voltages, for turning on/off the semiconductor layer <NUM> may be selectively applied to each of the plurality of gate electrodes <NUM>.

The variable resistance memory device <NUM> as illustrated may have a structure in which a plurality of memory cells MC are arrayed, wherein each of the memory cells MC may have a form in which a transistor and a variable resistance are connected in parallel, as shown in an equivalent or corresponding circuit of <FIG>.

An operation of the variable resistance memory device <NUM> is described below with reference to <FIG>.

In order to select a memory cell, e.g. to select a memory cell for reading, a control logic (not shown) may perform a control operation to apply a turn-off voltage OFF to the gate electrode <NUM> of a specific memory cell MC2 and a turn-on voltage ON to the gate electrodes <NUM> of the remaining memory cells MC1 and MC2. The turn-off voltage OFF may be configured to turn off a transistor and control a current may not flow through the semiconductor layer <NUM> of a transistor included in the selected memory cell MC2. The turn-on voltage ON may be configured to turn on a transistor and control a current to flow through the semiconductor layer <NUM> of transistors included in the non-selected memory cells MC1 and MC3. Thus, the semiconductor layer <NUM> corresponding to the selected memory cell MC2 may have an insulating property, and the semiconductor layers <NUM> corresponding to the non-selected memory cells MC1 and MC3 may have a conductive property.

The turn-off voltage OFF and the turn-on voltage ON may vary according to one or more of a type, a thickness, etc. of a material included in the resistance change layer <NUM>, the semiconductor layer <NUM>, the gate insulating layer <NUM>, and the gate electrodes <NUM>. For example, when the turn-off voltage OFF is a negative voltage, the turn-off voltage OFF may be greater than or equal to about -<NUM> V and less than or equal to about -<NUM> V. When the turn-on voltage ON is a positive voltage, the turn-on voltage ON may be about greater than or equal to about <NUM> V and less than or equal to about <NUM> V. The turn-on voltage ON of the same value may be applied to the non-selected memory cells MC1 and MC3, and the turn-on voltages ON of different values may be applied to the non-selected memory cells MC1 and MC3.

In a write operation, when a write voltage is applied between the source electrode S and the drain electrode D, a current path may be formed as shown by arrow A, so that a resistance of the resistance change layer <NUM> may be changed. By using this principle, information may be stored in the resistance change layer <NUM>. The reason that the resistance of the resistance change layer <NUM> is changed may be because when a current flows in the resistance change layer <NUM>, an oxygen vacancies Vo and/or interstitial oxygen ions may be formed, and the oxygen vacancies may gather to form a conductive filament. The conductive filament formed of the oxygen vacancies may have a low resistance, and thus, the resistance of the resistance change layer <NUM> may be changed.

In order to use the variable resistance memory device <NUM>, it may be desirable that there is a large difference between a resistance of a high-resistance state and a resistance of a low-resistance state of the resistance change layer <NUM>, and to this end, it may be desirable that oxygen vacancies may be easily formed in the resistance change layer <NUM>. In particular, desirably, oxygen vacancies may be more easily formed in the resistance change layer <NUM>, in order to prevent or reduce deterioration of the semiconductor layer <NUM>, by lowering an absolute value of an operating voltage, for example, a write voltage or an erase voltage, that may be applied to the variable resistance memory device <NUM>.

The resistance change layer <NUM> according to various example embodiments may include a metal oxide having a high oxygen deficient ratio. For example, the resistance change layer <NUM> may be or may include a metal oxide having an oxygen deficient ratio greater than or equal to <NUM> at%. The oxygen deficient ratio may be defined by Equation <NUM> below.

Here, M1, M2, M3, M4, M5, and O respectively indicate a monatomic metal element content, a bivalent metal element content, a trivalent metal element content, a tetravalent metal element content, a pentavalent metal element content, and an oxygen content.

A high oxygen deficient ratio may denote that there are relatively fewer oxygen ions compared to metal positive ions, and thus, a metal oxide having a high oxygen deficient ratio may have an increased oxygen vacancy content. When there are many oxygen vacancies in the resistance change layer <NUM>, a resistance state of the resistance change layer may be more easily changed, and thus, the characteristics of the variable resistance memory device <NUM> may be improved. Alternatively or additionally, when there are many oxygen vacancies, a conductive filament may be more easily formed when a voltage is applied, and thus, a forming voltage may be decreased to decrease an operating voltage of the variable resistance memory device <NUM>.

The resistance change layer <NUM> according to various example embodiments may include a binary metal oxide having an oxygen deficient ratio greater than or equal to <NUM>% or a ternary metal oxide having an oxygen deficient ratio greater than or equal to <NUM>%.

The binary metal oxide included in the resistance change layer <NUM> may include at least one of TaOx, TiOx, SnOx, CrOx, and MnOx.

The resistance change layer <NUM> may be or include a ternary metal oxide and may include a first metal element and a second metal element that are different from each other, and an oxygen element. A content of the first metal element may be greater than a content of the second metal element in the metal oxide. For example, the content of the first metal element with respect to the entire metal in the resistance change layer <NUM> may be greater than or equal to <NUM> at%, and the content of the second metal element with respect to the entire metal in the resistance change layer <NUM> may be less than or equal to <NUM> at%. The first metal element may include one of Ta, Ti, Sn, Cr, and Mn, and the second metal element may include one of or at least one of Hf, Al, Nb, La, Zr, Sc, W, V, and Mo.

Alternatively or additionally, the resistance change layer <NUM> may be or may include a ternary metal oxide and may include a metal element, a silicon element, and an oxygen element. A content of the metal element may be greater than a content of the silicon element in the resistance change layer <NUM>. The content of the metal element with respect to a sum of the metal element and the silicon element in the resistance change layer <NUM> may be greater than or equal to <NUM> at%, and the content of the silicon element with respect to the sum of the metal element and the silicon element in the resistance change layer <NUM> may be less than or equal to <NUM> at%. The metal element may include one of or at least one of Ta, Ti, Sn, Cr, and Mn.

Alternatively or additionally, the resistance change layer <NUM> may include a first metal oxide having an oxygen deficient ratio greater than or equal to <NUM>% and a second metal oxide having an oxygen deficient ratio less than <NUM>%. A content of the first metal oxide may be greater than a content of the second metal oxide. A metal content of the first metal oxide with respect to the entire metal content of the resistance change layer <NUM> may be greater than or equal to <NUM> at%, and a metal content of the second metal oxide with respect to the entire metal content of the resistance change layer <NUM> may be less than or equal to <NUM> at%. The first metal oxide may include at least one of TaOx, TiOx, SnOx, CrOx, and MnOx. The second metal oxide may include at least one of HfOx, AlOx, SiOx, NbOx, LaOx, ZrOx, ScOx, WOx, VOx, and MoOx.

<FIG> is a diagram showing a relationship between an oxygen deficient ratio and a forming voltage of a metal oxide, according to various example embodiments. Referring to <FIG>, hafnium oxide (HfOx), which is a binary oxide, may have an oxygen deficient ratio that is low as about <NUM>%, and may have a forming voltage Vforming that is high as about <NUM> V. HfOx is a representative variable resistance material, but has a high forming voltage, and thus, when HfOx is applied to the variable resistance memory device <NUM>, the semiconductor layer <NUM> of the variable resistance memory device <NUM> may be deteriorated.

Tantalum oxide (TaOx) may have an oxygen deficient ratio that is high as about <NUM>% and a forming voltage Vforming that is low as about <NUM> V. It may be predicted that the variable resistance memory device <NUM> may be realized to have a low operating voltage, when TaOx is used as the material of the resistance change layer <NUM> according to various example embodiments.

Although HfOx may not be solely used as the material of the resistance change layer <NUM> because of its low oxygen deficient ratio, HfOx may be used as a material of the resistance change layer <NUM> with Ta having a high oxygen deficient ratio. As illustrated in <FIG>, the oxygen deficient ratio and the forming voltage may vary according to types of materials included in a metal oxide. For example, while an oxygen deficient ratio of TaSiO having a silicon content of <NUM> at% may be about <NUM>% and a forming voltage of TaSiO may be about <NUM> V, an oxygen deficient ratio of TaAlO having an aluminum content of <NUM> at% may be about <NUM>% and a forming voltage of TaAlO may be about <NUM> V. When TaOx includes more aluminum than silicon, it may be identified that the oxygen deficient ratio may increase, and the forming voltage may decrease. Generally, as the oxygen deficient ratio increases, the forming voltage may decrease.

When the resistance change layer <NUM> includes a metal oxide including a plurality of different metals, the forming voltage may vary according to a content ratio of the metals. For example, when an aluminum content with respect to the entire metal of TaAlO is <NUM> at%, the forming voltage of TaAlO may be about <NUM> V, and when the aluminum content with respect to the entire metal of TaAlO is <NUM> at%, the forming voltage of TaAlO may be about <NUM> V. It may be identified that when the aluminum content is increased, the forming voltage may be reduced. However, the forming voltage of TaAlO having an aluminum content of <NUM> at% is about <NUM> V, and thus, it is identified that when the aluminum content is too high, the forming voltage may be increased.

The resistance change layer <NUM> according to various example embodiments may include a first metal element and a second metal element which are different from each other, and may include an oxygen deficient ratio greater than or equal to <NUM>%. A content of the first metal element may be greater than a content of the second metal element in a metal oxide. Alternatively, the content of the first metal element with respect to the entire metal in the resistance change layer <NUM> may be greater than or equal to <NUM> at%, and the content of the second metal element with respect to the entire metal in the resistance change layer <NUM> may be less than or equal to <NUM> at%. The first metal element may include one of or at least one of Ta, Ti, Sn, Cr, and Mn, and the second metal element may include one of or at least one of Hf, Al, Nb, La, Zr, Sc, W, V, and Mo.

From another perspective, the resistance change layer <NUM> may have a metal oxide having a high oxygen deficient ratio as a matrix, and may be doped with a metal or a metal oxide having a low oxygen deficient ratio, to reduce the forming voltage. However, when the content of the doped metal or metal oxide is too high, the forming voltage may be rather increased, and thus, the content of the doped metal with respect to the entire metal in the resistance change layer <NUM> may be less than or equal to about <NUM> at%.

An absolute value of an operating voltage, for example, a write voltage or an erase voltage, of the variable resistance memory device <NUM> according to various example embodiments may be less than or equal to about <NUM> V. Alternatively, the absolute value of the write voltage or the erase voltage of the variable resistance memory device <NUM> according to various example embodiments may be less than or equal to about <NUM> V.

<FIG> is a diagram showing a relationship between an oxygen deficient ratio and a forming voltage of a metal oxide, according to various example embodiments. Referring to <FIG>, it may be identified that as the oxygen deficient ratio increases, the forming voltage may decrease. However, the relationship between the oxygen deficient ratio and the forming voltage may be approximately inversely proportionate and may not be completely inversely proportionate. Types and/or contents of metal oxides of the resistance change layer <NUM> may be appropriately adjusted to reduce the forming voltage.

The oxygen deficient ratio of the metal oxide may be in connection with a difference in oxygen formation energy between a plurality of metal oxides having different atomic values of the same metal.

<FIG> is a diagram showing a relationship between an oxygen formation energy and an oxygen deficient ratio of a metal oxide, according to various example embodiments. Referring to <FIG>, a difference in oxygen formation energy between multiple tantalum oxides having different atomic values, for example, Ta2O5 and TaO2, may be about <NUM> kJ/mol, which is relatively small. However, the oxygen deficient ratio of the plurality of tantalum oxides may be about <NUM> %, which is relatively large. However, while a difference in oxygen formation energy between aluminum oxides is about <NUM>, which is relatively large, the oxygen deficient ratio of the aluminum oxides may be about <NUM> %, which is relatively small. It may be identified that the difference in oxygen formation energy between metal oxides may be inversely proportionate to the oxygen deficient ratio.

Although the oxygen deficient ratio of AlOx and the oxygen deficient ratio of HfOx are the same as about <NUM>%, the difference in oxygen formation energy with respect to AlOx is about <NUM> kJ/mol, which is greater than the difference in oxygen formation energy with respect to HfOx that is about <NUM> kJ/mol. For example, even when the oxygen deficient ratio may be the same as each other, the difference in oxygen formation energy may be different from each other. Thus, according to various example embodiments, a metal oxide having the difference in oxygen formation energy greater than or equal to about <NUM> kJ/mol may be used as a matrix of the resistance change layer <NUM>, and a metal oxide or a metal having the difference in oxygen formation energy less than about <NUM> kJ/mol may be used as a dopant of the resistance change layer <NUM>.

<FIG> is a diagram showing a difference in oxygen formation energy with respect to various metal oxides, according to various example embodiments. Referring to <FIG>, the difference in oxygen formation energy with respect to MnOx, TiOx, SnOx, and CrOx may be less than <NUM> kJ/mol. The MnOx, TiOx, SnOx, and CrOx may be used as a dopant of the resistance change layer <NUM> according to various example embodiments.

The difference in oxygen formation energy with respect to MoOx, VOx, ScOx, WOx, LaOx, and ZrOx may be greater than or equal to <NUM> kJ/mol. The MoOx, VOx, ScOx, WOx, LaOx, and ZrOx may be used as a matrix of the resistance change layer <NUM> according to various example embodiments.

<FIG> is a diagram showing the current-voltage (IV) characteristics of a variable resistance memory device using HfOx as a resistance change layer, and <FIG> is a diagram showing the IV characteristics of a variable resistance memory device using TaOx as a resistance change layer. The variable resistance memory device including HfOx may have the absolute value of a forming voltage that is about <NUM> V to about <NUM> V, as illustrated in <FIG>. As described above, the oxygen deficient ratio of HfOx may be relatively low as about <NUM>%.

The variable resistance memory device including TaOx may have the absolute value of a forming voltage that is less than about 2V, as illustrated in <FIG>. As described above, the oxygen deficient ratio of TaOx may be relatively high as about <NUM>%. This may indicate that as the oxygen deficient ratio increases, more oxygen vacancies may be formed in the resistance change layer <NUM>, and thus, a conductive filament may be easily formed at a low operating voltage.

<FIG> is a structural diagram of a variable resistance memory device 100a according to various example embodiments, and <FIG> is a circuit diagram of the variable resistance memory device 100a of <FIG>.

The variable resistance memory device 100a according to various example embodiments may correspond to a vertical NAND (VNAND) memory in which a plurality of memory cells MC including a variable resistance material are vertically arrayed.

Referring to <FIG>, a plurality of cell strings CS may be formed on a substrate <NUM>.

The substrate <NUM> may include a silicon material doped with a first-type impurity. For example, the substrate <NUM> may include a silicon material doped with a p-type impurity. For example, the substrate <NUM> may include a p-type well (for example, a pocket p well). Hereinafter, it is assumed that the substrate <NUM> includes p-type silicon. However, the substrate <NUM> is not limited to p-type silicon.

A doped area <NUM>, which is a source area, may be provided on the substrate <NUM>. The doped area <NUM> may include an n-type area, which is different from the substrate <NUM>. Hereinafter, it is assumed that the doped area <NUM> includes an n-type area. However, the doped area <NUM> is not limited to the n-type area. The doped area <NUM> may be connected to a common source line CSL.

With K and n integers, K*n cell strings CS may be provided as indicated in the equivalent circuit diagram of <FIG> and may be arranged in the matrix form. The cell strings CS may be referred to as CSij (<NUM>≤i≤k, <NUM>≤j≤n) according to a location of a column and a row. Each cell string CSij may be connected to a bit line BL, a string selection line SSL, a word line WL, and the common source line CSL.

Each cell string CSij may include the memory cells MC and a string selection transistor SST. The memory cells MC and the string selection transistor SST of each cell string CSij may be stacked in a height direction.

Rows of the plurality of cell strings CS may be connected to different string selection lines SSL1 through SSLk, respectively. For example, the string selection transistors SST of the cell strings CS11 through CS1n may be commonly connected to the string selection line SSL1. The string selection transistors SST of the cell strings CSk1 through CSkn may be commonly connected to the string selection line SSLk.

Columns of the plurality of cell strings CS may be connected to different bit lines BL1 through BLn, respectively. For example, the memory cells and the string selection transistors SST of the cell strings CS11 through CSk1 may be commonly connected to the bit line BL1, and the memory cells MC and the string selection transistors SST of the cell strings CS1n through CSkn may be commonly connected to the bit line BLn.

Rows of the plurality of cell strings CS may be connected to different common source lines CSL1 through CSLk, respectively. For example, the string selection transistors SST of the cell strings CS11 through CS1n may be commonly connected to the common source line CSL1, and the string selection transistors SST of the cell strings CSk1 through CSkn may be commonly connected to the common source line CSLk.

Gate electrodes <NUM> of the memory cells MC located in the same height from the substrate <NUM> or the string selection transistors SST may be commonly connected to one word line WL. Also, gate electrodes <NUM> of the memory cells MC located in different heights from the substrate <NUM> or the string selection transistors SST may be connected to different word lines WL1 through WLm, respectively.

The illustrated circuit structure is an example. For example, the number of rows of the cell strings CS may increase or decrease. When the number of rows of the cell strings CS is changed, the number of string selection lines connected to the rows of the cell strings CS and the number of cell strings CS connected to one bit line may also be changed. When the number of rows of the cell strings CS is changed, the number of common source lines connected to the rows of the cell strings CS may also be changed.

The number of columns of the cell strings CS may also increase or decrease and is not limited to <FIG>. When the number of columns of the cell strings CS is changed, the number of bit lines connected to the columns of the cell strings CS and the number of cell strings CS connected to one string selection line may also be changed.

The height of the cell strings CS may also increase or decrease and is not limited to <FIG>. For example, the number of memory cells MC stacked in each of the cell strings CS may increase or decrease. When the number of memory cells MC stacked in each cell string CS is changed, the number of word lines WL may also be changed. For example, the number of string selection transistors included in each cell string CS may increase. When the number of string selection transistors included in each cell string CS is changed, the number of string selection lines or the common source lines may also be changed. When the number of string selection transistors SSTs is increased, the string selection transistors SSTs may be stacked in a shape that is the same as the shape in which the memory cells MC are stacked.

For example, a writing operation and a reading operation may be performed for each row of the cell strings CS. The cell strings CS may be selected for each row by the common source line CSL, and the cell strings CS may be selected for each row by the string selection lines SSL. Also, a voltage may be applied to the common source lines CSL by a unit of at least two common source lines. A voltage may be applied to the common source lines CSL by a unit of the entire common source lines CSL.

The writing operation and the reading operation may be performed for each page in a selected row of the cell strings CS. A page may correspond to one row of the memory cells connected to one word line WL. The memory cells may be selected for each page by the word lines WLs, in a selected row of the cell strings CSs.

As illustrated in <FIG>, the cell string CS may include a channel hole CH having a cylindrical shape and the plurality of gate electrodes <NUM> and a plurality of insulating elements <NUM> surrounding the channel hole CH in a ring shape. The plurality of insulating elements <NUM> may be provided to isolate between the plurality of gate electrodes <NUM>. The plurality of gate electrodes <NUM> and the plurality of insulating elements <NUM> may be alternately stacked in a vertical direction (a z direction). The channel hole CH having the cylindrical shape may include an insulating pillar <NUM> having a cylindrical shape extending in a vertical direction and the resistance change layer <NUM>, the semiconductor layer <NUM>, and the gate insulating layer <NUM> having a shape sequentially surrounding the insulating pillar <NUM> in a cylindrical shell shape.

The gate electrodes <NUM> may include a metal material, and/or a silicon material doped in a high concentration. Each gate electrode <NUM> may be connected to either of a word line WL and a string selection line SSL.

The insulating elements <NUM> may include various insulating materials, such as one or more of silicon oxide, silicon nitride, or the like.

The channel hole CH may include a plurality of layers. The outermost layer of the channel hole CH may be the gate insulating layer <NUM>. For example, the gate insulating layer <NUM> may include various insulating materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, or the like. The gate insulating layer <NUM> may be conformally deposited on the channel hole CH.

The semiconductor layer <NUM> may be conformally deposited along an inner surface of the gate insulating layer <NUM>. The semiconductor layer <NUM> may include a semiconductor material doped with a first-type material. The semiconductor layer <NUM> may include a silicon material doped with a material of the same-type as the substrate <NUM>. For example, when the substrate <NUM> includes a p-type doped silicon material, the semiconductor layer <NUM> may also include a p-type doped silicon material. Alternatively or additionally, the semiconductor layer <NUM> may include materials, such as one or more of Ge, IGZO, GaAs, etc..

The resistance change layer <NUM> may be arranged along an inner surface of the semiconductor layer <NUM>. The resistance change layer <NUM> may be arranged to contact the semiconductor layer <NUM> and may be conformally deposited on the semiconductor layer <NUM>.

The resistance change layer <NUM> may be changed to a high-resistance state or a low-resistance state according to an applied voltage and may include a metal oxide having a high oxygen deficient ratio.

The resistance change layer <NUM> may have substantially the same materials and characteristics as the resistance change layer <NUM> described above. The resistance change layer <NUM> may include a binary metal oxide having an oxygen deficient ratio greater than or equal to <NUM>% or a ternary metal oxide having an oxygen deficient ratio greater than or equal to <NUM>%.

The binary metal oxide included in the resistance change layer <NUM> may be or include at least one of TaOx, TiOx, SnOx, CrOx, and MnOx.

The ternary metal oxide included in the resistance change layer <NUM> may include a first metal element and a second metal element that are different from each other, and an oxygen element. A content of the first metal element may be greater than a content of the second metal element in the metal oxide. For example, the content of the first metal element with respect to the entire metal in the resistance change layer <NUM> may be greater than or equal to <NUM> at%, and the content of the second metal element with respect to the entire metal in the resistance change layer <NUM> may be less than or equal to <NUM> at%. The first metal element may include one of or at least one of Ta, Ti, Sn, Cr, and Mn, and the second metal element may include one of or at least one of Hf, Al, Nb, La, Zr, Sc, W, V, and Mo.

A content of the metal element may be greater than a content of the silicon element in the resistance change layer <NUM>. The content of the metal element with respect to the sum of the metal element and the silicon element in the resistance change layer <NUM> may be greater than or equal to <NUM> at%, and the content of the silicon element with respect to the sum of the metal element and the silicon element in the resistance change layer <NUM> may be less than or equal to <NUM> at%. The metal element may include one of or at least one of Ta, Ti, Sn, Cr, and Mn.

Alternatively, the resistance change layer <NUM> may include a first metal oxide having an oxygen deficient ratio greater than or equal to <NUM>% and a second metal oxide having an oxygen deficient ratio less than <NUM>%. A content of the first metal oxide may be greater than a content of the second metal oxide. A metal content of the first metal oxide with respect to the entire metal content of the resistance change layer <NUM> may be greater than or equal to <NUM> at%, and a metal content of the second metal oxide with respect to the entire metal content of the resistance change layer <NUM> may be less than or equal to <NUM> at%. The first metal oxide may be or include at least one of TaOx, TiOx, SnOx, CrOx, and MnOx. The second metal oxide may be or include at least one of HfOx, AlOx, SiOx, NbOx, LaOx, ZrOx, ScOx, WOx, VOx, and MoOx.

The variable resistance memory device 100a may include the resistance change layer <NUM> in which oxygen vacancies may be easily formed, and thus, a difference between a resistance value of a high-resistance state and a resistance value of a low-resistance state may be increased, and the characteristics of a low set voltage and a low reset voltage may be realized.

The insulating pillar <NUM> may be deposited along an inner surface of the resistance change layer <NUM>. The insulating pillar <NUM> may fill the innermost space of the channel hole CH.

The resistance change layer <NUM> and the semiconductor layer <NUM> may contact the doped area <NUM>, that is, the common source area.

A drain area <NUM> may be arranged in the channel hole CH of the cell string CS. The drain area <NUM> may include a second-type doped silicon material. For example, the drain area <NUM> may include a silicon material doped with an n-type material.

A bit line <NUM> may be provided on the drain area <NUM>. The drain area <NUM> and the bit line <NUM> may be connected to each other via contact plugs.

Each gate electrode <NUM> and the gate insulating layer <NUM>, the semiconductor layer <NUM>, and the resistance change layer <NUM> facing the gate electrode <NUM> in a horizontal direction (an x direction) may form the memory cell MC. For example, the memory cell MC may have a circuit structure in which a transistor including the gate electrode <NUM>, the gate insulating layer <NUM>, and the semiconductor layer <NUM> is connected in parallel with a variable resistance due to the resistance change layer <NUM>.

The parallel connection structure may be continually arranged in the vertical direction (the z direction) to form the cell string CS. Also, both ends of the cell string CS may be connected to the common source line CSL and the bit line BL as illustrated in the circuit diagram of <FIG>. By applying a voltage to the common source line CSL and the bit line BL, programming, reading, and erasing may be performed on a plurality of memory cells MC.

For example, when a memory cell MC on which a program operation is to be performed is selected, a gate voltage value of the selected cell may be adjusted such that the selected cell is in a channel-off state, and a gate voltage value of non-selected cells may be adjusted such that the non-selected cells are in a channel-on state. Accordingly, a current path due to the voltage applied to the common source line CSL and the bit line BL may pass through an area of the resistance change layer <NUM> of the selected memory cell MC. Here, the applied voltage may be set as Vset or Vreset to form an LRS or an HRS and to write data of logical "<NUM>" or logical "<NUM>" in the selected memory cell MC as desired.

With respect to a read operation, reading may be performed on a selected cell according to a similar method. For example, a gate voltage applied to each gate electrode <NUM> may be adjusted such that a selected memory cell MC is in a channel-off state and non-selected memory cells MC are in a channel-on state. Then, a current flowing through the corresponding cell MC due to an applied voltage Vread between the common source line CSL and the bit line BL may be measured to identify a cell state, e.g.logical"<NUM>" or logical "<NUM>".

As described above, according to the variable resistance memory device 100a according to various example embodiments, the memory cell MC may be formed by using the resistance change layer <NUM> including a material for easily forming a conductive filament based on oxygen vacancies, and the memory cells MC may be arrayed to form the memory device. Thus, compared to other structures, for example, a phase-change material-based memory device or a charge-trap-based memory device, the resistance change layer <NUM> may be formed to have a decreased thickness, and the variable resistance memory device 100a may have a low operating voltage. For example, the variable resistance memory device 100a may have an operating voltage, for example, a write voltage or an erase voltage, an absolute value of which is less than or equal to about <NUM> V. Alternatively, the variable resistance memory device 100a may have an operating voltage, for example, a write voltage or an erase voltage, an absolute value of which is less than or equal to about <NUM> V.

In a VNAND structure, due to a packaging feature or limit according to a height of the cell string CS, there is a limit to increase the number of gate electrodes <NUM> included in the cell string CS. Moreover, in the case of a charge-trap based memory device, there may be a limit to reduce a distance between adjacent gate electrodes <NUM> due to interference. For example, it may be difficult to reduce a pitch of gate electrodes adjacent to each other in the vertical direction (the z direction) to be less than or equal to about <NUM>, and thus, there is a limit of the memory capacity.

The variable resistance memory device 100a according to various example embodiments may use the resistance change layer <NUM> described above, and thus, may reduce or minimize a pitch between the gate electrodes <NUM>, e.g. a pitch of at least three of the gate electrodes <NUM> which may be arranged in a periodic manner. According to various example embodiments, the pitch may be reduced to be less than or equal to <NUM>, for example, to be about <NUM>, and in this case, the memory capacity may be increased two times or more.

Based on this structure, the variable resistance memory device 100a may address or at least partly address a scaling issue between the memory cells in next-generation VNAND memories, to increase the density and/or to realize low power consumption.

<FIG> is a diagram of a portion of a variable resistance memory device 100b including a plurality of resistance change layers <NUM> according to various example embodiments. Referring to <FIG> and <FIG>, the variable resistance memory device 100b of <FIG> may include a plurality of resistance change layers 122a. For example, the resistance change layers 122a may include a first resistance change layer RS1 and a second resistance change layer RS2 sequentially arranged in a direction away from the semiconductor layer <NUM>.

At least one of the first and second resistance change layers RS1 and RS2 may include a metal oxide having an oxygen deficient ratio greater than or equal to <NUM>%. For example, the first resistance change layer RS1 may include a first metal oxide having an oxygen deficient ratio greater than or equal to <NUM>% as a matrix and may be doped with a second metal oxide having an oxygen deficient ratio less than <NUM>%. The oxygen deficient ratio of the first metal oxide included in the first resistance change layer RS1 may be greater than an oxygen deficient ratio of a first metal oxide included in the second resistance change layer RS2. Oxygen vacancies may be easily or more easily formed in the first resistance change layer RS1 adjacent to the semiconductor layer <NUM>, and thus, an operating voltage of the variable resistance memory device <NUM> may be reduced.

<FIG> is a diagram of a portion of a variable resistance memory device 100c further including an oxide layer <NUM>, according to various example embodiments. Referring to <FIG> and <FIG>, the variable resistance memory device 100c of <FIG> may further include the oxide layer <NUM> between the semiconductor layer <NUM> and the resistance change layer <NUM>. The oxide layer <NUM> may include silicon oxide, but is not limited thereto. The oxide layer <NUM> may include an oxide of a material contacting the oxide layer <NUM>, for example, an oxide of a material included in the semiconductor layer <NUM>, in a device implementing the variable resistance memory device 100c. A thickness of the oxide layer <NUM> may be less than a thickness of the resistance change layer <NUM>. For example, the thickness of the oxide layer <NUM> may be less than or equal to about <NUM>.

<FIG> is a diagram of a variable resistance memory device 100d including a conductive pillar <NUM>, according to various example embodiments. To compare <FIG> with <FIG>, the variable resistance memory device 100d of <FIG> may include the conductive pillar <NUM> rather than an insulating pillar.

The conductive pillar <NUM> may contact the resistance change layer <NUM>. The conductive pillar <NUM> may be conformally deposited on the resistance change layer <NUM>. The conductive pillar <NUM> may include a material having an improved or excellent electrical conductive property. For example, the conductive pillar <NUM> may include at least one of W, Ti, TiN, Ru, RuO2, Ta, and TaN. The conductive pillar <NUM> may include the same material as the gate electrodes <NUM>.

The entire area of the conductive pillar <NUM> may become spatially apart from the entire area of the semiconductor layer <NUM> by the resistance change layer <NUM>. Because the conductive pillar <NUM> is electrically insulated from the semiconductor layer <NUM>, voltages may be separately applied to the conductive pillar <NUM> and the semiconductor layer <NUM>.

The variable resistance memory device 100d may further include a first bit line (not shown) electrically connected to the conductive pillar <NUM> and providing a voltage to the conductive pillar <NUM> and a second bit line (not shown) electrically insulated from the first bit line and electrically connected to the semiconductor layer <NUM> and providing a voltage to the semiconductor layer <NUM>.

When the variable resistance memory device 100d operates, a voltage may also be applied to the conductive pillar <NUM>. The voltage applied to the conductive pillar <NUM> may be greater than a gate voltage of a selected memory cell, that is a turn-off voltage, and may be greater than or equal to the voltage applied to the semiconductor layer <NUM>. Thus, a horizontal electric field toward the semiconductor layer <NUM> may be formed in the resistance change layer <NUM> corresponding to the selected memory cell. Oxygen vacancies in the resistance change layer <NUM> corresponding to the selected memory cell may be concentrated in an area of the resistance change layer <NUM> that is adjacent to the semiconductor layer <NUM>, and thus, a conductive filament may be relatively more easily formed.

<FIG> is a schematic block diagram of an electronic device <NUM> including a nonvolatile memory device according to various example embodiments.

Referring to <FIG>, the electronic device <NUM> according to various example embodiments may be one of a personal digital assistant (PDA), a laptop computer, a portable computer, a web tablet computer, a wireless telephone, a cellular phone, a digital music player, a wired or wireless electronic device, or a complex electronic device including at least two thereof. The electronic device <NUM> may include a controller <NUM>, an input and output device <NUM>, such as one or more of a keypad, a keyboard, and a display, a memory <NUM>, and a wireless interface <NUM>, which are connected with each other through a bus <NUM>.

The controller <NUM> may include, for example, one or more microprocessors, a digital signal processor, a micro-controller, or components similar thereto. The memory <NUM> may be used, for example, to store instructions executed by the controller <NUM>.

The memory <NUM> may be used to store user data. The memory <NUM> may include at least one of nonvolatile memory devices according to various example embodiments.

The electronic device <NUM> may use the wireless interface <NUM> to transmit data or receive data to or from a wireless communication network performing communication via a radio frequency (RF) signal. For example, the wireless interface <NUM> may include an antenna, a wireless transceiver, etc. The electronic device <NUM> may be used in communication interface protocols, such as the third-generation (<NUM>) communication systems, such as one or more of CDMA, GSM, NADC, E-TDMA, WCDAM, and CDMA2000.

<FIG> is a schematic block diagram of a memory system <NUM> including a nonvolatile memory device according to various example embodiments.

Referring to <FIG>, nonvolatile memory devices according to various example embodiments may be used to realize the memory system <NUM>. The memory system <NUM> may include a memory <NUM> storing a large volume of data and a memory controller <NUM>. The memory controller <NUM> may control the memory <NUM> such that the data stored in the memory <NUM> may be read or written, in response to a read/write request of a host <NUM>. The memory controller <NUM> may configure the host <NUM>, for example, an address mapping table for mapping an address provided from a mobile device or a computer system into a physical address of the memory <NUM>. The memory <NUM> may include at least one of semiconductor memory devices according to various example embodiments.

The nonvolatile memory device according to various example embodiments described above may be realized in the form of a chip and may be used as a neuromorphic computing platform.

<FIG> is a schematic diagram of a neuromorphic apparatus <NUM> including a memory device, according to various example embodiments. Referring to <FIG>, the neuromorphic apparatus <NUM> may include processing circuitry <NUM> and/or a memory <NUM>. The memory <NUM> of the neuromorphic apparatus <NUM> may include the memory system according to various example embodiments.

The processing circuitry <NUM> may be configured to control functions for driving the neuromorphic apparatus <NUM>. For example, the processing circuitry <NUM> may be configured to control the neuromorphic apparatus <NUM> by executing programs stored in the memory <NUM> of the neuromorphic apparatus <NUM>.

The processing circuitry <NUM> may include hardware such as logic circuits; a hardware/software combination, such as a processor executing software; or a combination thereof. For example, a processor may include, but is not limited to, one or more of a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic apparatus <NUM>, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), or the like. the processing circuitry <NUM> may be configured to read/write a variety of data from/in an external device <NUM> and/or execute the neuromorphic apparatus <NUM> by using the read/written data. The external device <NUM> may include an external memory and/or sensor array with an image sensor (e.g., a CMOS image sensor circuit).

The neuromorphic apparatus <NUM> in <FIG> may be applied to a machine learning system. The machine learning system may utilize a variety of artificial neural network organizational and processing models, such as one or more of convolutional neural networks (CNN), de-convolutional neural networks, recurrent neural networks (RNN) optionally including long short-term memory (LSTM) units and/or gated recurrent units (GRU), stacked neural networks (SNN), state-space dynamic neural networks (SSDNN), deep belief networks (DBN), generative adversarial networks (GANs), and/or restricted Boltzmann machines (RBM).

Such machine learning systems may include other forms of machine learning models, such as, for example, linear and/or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and/or combinations thereof, including ensembles such as random forests. Such machine learning models may be used to provide various services, for example, an image classify service, a user authentication service based on bio-information or biometric data, an advanced driver assistance system (ADAS) service, a voice assistant service, an automatic speech recognition (ASR) service, or the like, and may be mounted and executed by other electronic devices.

The variable resistance memory device according to various example embodiments may operate even when a voltage, an absolute value of which is relatively small, is applied thereto.

Alternatively or additionally, the variable resistance memory device according to various example embodiments may be advantageous for realizing lower power consumption and/or higher integration.

It should be understood that various example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, and example embodiments are not necessarily mutually exclusive with one another.

Any of the elements and/or functional blocks disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc..

When the terms "about" or "substantially" are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical value. Moreover, when the words "generally" and "substantially" are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Moreover, when the words "generally" and "substantially" are used in connection with material composition, it is intended that exactitude of the material is not required but that latitude for the material is within the scope of the disclosure.

Further, regardless of whether numerical values or shapes are modified as "about" or "substantially," it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical values or shapes. Thus, while the term "same," "identical," or "equal" is used in description of example embodiments, it should be understood that some imprecisions may exist. Thus, when one element or one numerical value is referred to as being the same as another element or equal to another numerical value, it should be understood that an element or a numerical value is the same as another element or another numerical value within a desired manufacturing or operational tolerance range (e.g., <NUM>%).

Claim 1:
A variable resistance memory device (<NUM>) comprising:
a resistance change layer (<NUM>) comprising a metal oxide that includes a first metal element and a second metal element;
a semiconductor layer (<NUM>) on the resistance change layer;
a gate insulating layer (<NUM>) on the semiconductor layer; and
a plurality of electrodes (<NUM>) on the gate insulating layer to be apart from each other, characterized in that, the metal oxide has an oxygen deficient ratio greater than or equal to <NUM>%.