Patent Description:
Processor-based computer systems can include a vast array of integrated circuits (ICs). Each IC has a complex layout design comprised of multiple IC devices. Standard cell circuits are often employed to assist in making the design of ICs less complex and more manageable. In particular, standard cell circuits provide a designer with pre-designed cells corresponding to commonly used IC devices that conform to specific design rules of a chosen technology. As non-limiting examples, standard cell circuits may include gates, inverters, multiplexers, and adders. Using standard cell circuits enables a designer to create ICs having consistent layout designs, thereby creating a more uniform and less complex layout design across multiple ICs, as compared to custom designing each circuit.

Conventional standard cell circuits employ voltage rails configured to receive supply voltages, such as VDD and VSS supply voltages, which are used to power corresponding circuit devices in a standard cell circuit. For example, voltage rails can be configured to receive VDD and VSS supply voltages, wherein the voltage rails are coupled to drain and source regions of transistors within a conventional standard cell circuit such that the transistors receive the corresponding supply voltages. Voltage rails employed in conventional standard cell circuits can be sized to have a width that minimizes the resistance of the voltage rails. For example, a voltage rail formed from a conductive material with a defined resistivity has a resistance that is inversely proportional to the cross-sectional area of the voltage rail. In this manner, a voltage rail having a larger width, and thus having a larger cross-sectional area, has a smaller resistance. A lower resistance corresponds to a lower current-resistance (IR) drop (i.e., voltage drop) of each voltage rail. In this manner, a higher percentage of voltage is provided to each circuit device such that the performance of the standard cell circuit increases, wherein the performance is inversely correlated to the IR drop.

The width of signal lines and/or voltage rails in the standard cell circuits are scaled down to decrease the size of the standard cell circuits. However, because the signal lines and voltage rails are formed from metal (i.e., a conductive material), a decrease in width of such signal lines and voltage rails results in a decrease in cross-sectional area that causes an increase in resistance. For example, signal lines and/or voltage rails formed from a metal, such as copper (Cu), experience an increase in resistance as the width, and thus the cross-sectional area, decreases. Additionally, signal lines and/or voltage rails formed from copper (Cu) require a layer of copper (Cu) barrier and liner. Such barrier and liner layers limit the cross-sectional area available for the actual copper (Cu) signal line and/or voltage rail, thus reducing the area available for current flow and causing an even higher resistance. Alternatively, metals that may not need a barrier and/or liner layer such as aluminum (Al), cobalt (Co), or ruthenium (Ru) may be employed instead of copper (Cu), wherein the absence of a barrier and/or liner layer provides more cross-sectional area available for the signal line and/or voltage rail, thus limiting an increase in resistance attributable to reduced cross-sectional area of the conductive material. However, such metals have a higher resistivity, and thus a higher resistance than copper (Cu) at a conventional voltage rail width, resulting in a higher IR drop compared to copper (Cu). Higher IR drops in voltage rails may reduce voltage delivered by the voltage rail to a voltage level below circuit activation voltage levels (e.g., threshold voltages) that can unintendedly prevent activation of circuit elements, thus causing the standard cell circuit to produce erroneous output.

<CIT> relates to an improved standard cell architecture to achieve high density and improved power distribution. <CIT> relates to the routing of power rails for a standard cell that is used to design integrated circuits. <CIT> relates to an architecture for providing a customized application specific device having high functional density with high operational speed. Stanley Wolf: "Multilevel Interconnects for ULSI" is a handbook discussing the challenges related to the performance and density issues of ULSI interconnects. <NPL>" relates to global wiring layers and interconnect tuning issues related to bus routing, repeater insertion and choice of shielding/spacing rules for signal integrity and performance. <NPL>" relates to multilevel interconnection technology for the ULSI/GSI era of the silicon integrated circuits, with emphasis on the materials and processes that will lead to an acceptable multilevel interconnection scheme.

<CIT> discloses a standard cell circuit with a first voltage rail and a second voltage rail and a circuit device coupled between both voltage rails; the document discloses also that the width of the power rails is larger than the width of the signal lines and that the power rails are made of a material other than copper (e.g. tungsten or aluminum).

Aspects disclosed herein include standard cell circuits employing high aspect ratio voltage rails for reduced resistance. In one aspect, a standard cell circuit is provided. As used herein, a standard cell circuit is a collection of circuit devices that provides an integrated circuit (IC) function and that conforms to specific design rules of a chosen fabrication technology. The standard cell circuit employs a first high aspect ratio voltage rail configured to receive a first supply voltage (e.g., VDD). The standard cell circuit also employs a second high aspect ratio voltage rail extending substantially parallel to the first high aspect ratio voltage rail that may be configured to receive a second supply voltage (e.g., VSS) or coupled to ground. In this manner, a voltage differential between the first and second high aspect ratio voltage rails is used to power a circuit device in the standard cell circuit. As used herein, a high aspect ratio is a height-to-width ratio greater than <NUM>, wherein the first and second high aspect ratio voltage rails each have a height-to-width ratio greater than <NUM>. In other words, the height of the first high aspect ratio voltage rail is greater than the width of the first high aspect ratio voltage rail. Similarly, the height of the second high aspect ratio voltage rail is greater than the width of the second high aspect ratio voltage rail. Employing the first and second high aspect ratio voltage rails with a greater height than width in this manner allows each of the first and second high aspect ratio voltage rails to have a cross-sectional area large enough to achieve a lower resistance corresponding to a particular, lower current-resistance (IR) drop (i.e., voltage drop) compared to voltage rails of a similar width but which do not have a high aspect ratio. Thus, even if a metal material with a relatively higher resistivity is employed for first and second high aspect ratio voltage rails in a standard cell circuit, the first and second high aspect ratio voltage rails can be designed to each have a cross-sectional area that limits the resistance and corresponding IR drop to reduce or avoid errors in the standard cell circuit resulting from unintended reduced voltages levels due to IR drop energy losses.

In accordance with the present invention, there is provided an apparatus as set out in claim <NUM> and a method as set out in claim <NUM>. Other aspects of the invention can be found in the dependent claims.

The embodiments of <FIG> and <FIG> form part of the claimed invention, whereas the embodiment of <FIG> does not form part of the claimed invention.

Before discussing a standard cell circuit employing high aspect ratio voltage rails for reduced resistance for reducing IR drop beginning in <FIG>, a conventional standard cell circuit is first described. In this regard, <FIG> illustrate a conventional standard cell circuit <NUM> employing standard voltage rails. <FIG> illustrates a top-view diagram of the conventional standard cell circuit <NUM>, while <FIG> illustrates a cross-sectional view of the conventional standard cell circuit <NUM> taken generally along line A-A in <FIG>.

With reference to <FIG>, the conventional standard cell circuit <NUM> includes first voltage rail <NUM> extending along a first longitudinal axis A1 in a first direction X. The conventional standard cell circuit <NUM> also includes a second voltage rail <NUM> extending along a second longitudinal axis A2 in the first direction X substantially parallel to the first voltage rail <NUM>. The conventional standard cell circuit <NUM> also includes a circuit device <NUM> formed from multiple circuit elements (e.g., transistor elements) disposed below the first and second voltage rails <NUM>, <NUM> in a second direction Z. Further, a voltage differential between the first and second voltage rails <NUM>, <NUM> is used to power the circuit device <NUM>. For example, the first voltage rail <NUM> may receive a first supply voltage (e.g., VDD), while the second voltage rail <NUM> may receive a second supply voltage (e.g., VSS) or be coupled to ground. Further, connection elements within the conventional standard cell circuit <NUM> may be employed to distribute the first and second supply voltages VDD, VSS from the first and second voltage rails <NUM>, <NUM> to the circuit device <NUM>. In particular, the first voltage rail <NUM> is electrically coupled to a first power input <NUM> by way of a via <NUM> and a contact layer interconnect <NUM>. Additionally, the second voltage rail <NUM> is electrically coupled to a second power input <NUM> by way of a via <NUM> and a contact layer interconnect <NUM>. The first and second power inputs <NUM>, <NUM> are electrically coupled to corresponding elements <NUM>(<NUM>), <NUM>(<NUM>) of the circuit device <NUM> so as to distribute the first and second supply voltages VDD, VSS to the circuit device <NUM>.

With continuing reference to <FIG>, the first and second voltage rails <NUM>, <NUM> each have a width W1 approximately equal to three (<NUM>) times a width of metal lines in the conventional standard cell circuit <NUM>, such as metal lines <NUM>(<NUM>), <NUM>(<NUM>) extending along axes A3, A4, respectively, along the first direction X substantially parallel to the first and second voltage rails <NUM>, <NUM>. In this manner, the width of the metal lines <NUM>(<NUM>), <NUM>(<NUM>) may be approximately equal to a critical dimension (CD) of a process technology used to fabricate the conventional standard cell circuit <NUM>. As used herein, the critical dimension (CD) of a process technology is the smallest width in which a metal line can be fabricated in the process technology while still satisfying corresponding design rules so as to avoid erroneous circuit function. Additionally, the first and second voltage rails <NUM>, <NUM> each have a height H1 that is less than the width W1. In this manner, a height-to-width ratio of the first and second voltage rails <NUM>, <NUM> is less than <NUM> (i.e., height-to-width ratio (H1:W1) < <NUM>). In this example, because the first and second voltage rails <NUM>, <NUM> each have a height H1 such that each corresponds to a metal layer M0, vias in a via level V0, interconnects in a metal layer M1, and vias in a via level V1 would need to be employed to electrically couple the first and second voltage rails <NUM>, <NUM>, respectively, to routing interconnects in a metal layer M2 so as to route the first and second supply voltages VDD, VSS throughout the conventional standard cell circuit <NUM>. It is worth noting that elements used to electrically couple the first and second voltage rails <NUM>, <NUM> to routing interconnects in the metal layer M2 add corresponding resistance to the conventional standard cell circuit <NUM>, thus increasing IR drop and reducing performance.

With continuing reference to <FIG>, the IR drop of the first and second voltage rails <NUM>, <NUM> is also affected by a resistivity of the material used to form the first and second voltage rails <NUM>, <NUM>, as well as the width W1 and height H1. In this manner, the first and second voltage rails <NUM>, <NUM> may be employed using a metal more scalable than copper (Cu), such as ruthenium (Ru) or cobalt (Co). However, if the more scalable metals have a higher resistivity than copper (Cu), employing the first and second voltage rails <NUM>, <NUM> using such metals results in the first and second voltage rails <NUM>, <NUM> each having a higher resistance as compared to using copper (Cu). Further, reducing the width W1 to decrease area consumption of the standard cell circuit <NUM> reduces the conductive area of the first and second voltage rails <NUM>, <NUM>, which further increases the resistance, and thus the IR drop, of the first and second voltage rails <NUM>, <NUM>. An increased IR drop can reduce the voltage distributed by the first and second voltage rails <NUM>, <NUM> to a level low enough to prevent activation of the circuit device <NUM>, thus causing the conventional standard cell circuit <NUM> to produce erroneous output resulting from unintended reduced voltages levels due to IR drop energy losses.

In this regard, <FIG> illustrate an exemplary standard cell circuit <NUM> employing high aspect ratio voltage rails for reduced resistance for reducing IR drop. <FIG> illustrates a top-view diagram of the standard cell circuit <NUM>, while <FIG> illustrates a cross-sectional view of the standard cell circuit <NUM> taken generally along line B-B in <FIG>.

With reference to <FIG>, the standard cell circuit <NUM> employs a first high aspect ratio voltage rail <NUM> extending along a first longitudinal axis A1 in a first direction X and configured to receive a first supply voltage (e.g., VDD). The standard cell circuit <NUM> also employs a second high aspect ratio voltage rail <NUM> extending along a second longitudinal axis A2 in the first direction X substantially parallel to the first high aspect ratio voltage rail <NUM>. The second high aspect ratio voltage rail <NUM> may be configured to receive a second supply voltage (e.g., VSS) or be coupled to ground. In this manner, a voltage differential between the first and second high aspect ratio voltage rails <NUM>, <NUM> is used to power the circuit device <NUM> in the standard cell circuit <NUM>. For example, the first and second high aspect ratio voltage rails <NUM>, <NUM> are configured to receive the first supply voltage VDD and the second supply voltage VSS, respectively, and distribute the first and second supply voltages VDD, VSS to the circuit device <NUM> formed from multiple circuit elements (e.g., transistor elements) disposed below the first and second high aspect ratio voltage rails <NUM>, <NUM> in a second direction Z. In this aspect, the first high aspect ratio voltage rail <NUM> is electrically coupled to a first power input <NUM> by way of a contact layer interconnect <NUM>, and the second high aspect ratio voltage rail <NUM> is electrically coupled to a second power input <NUM> by way of a contact layer interconnect <NUM>. The first and second power inputs <NUM>, <NUM> are electrically coupled to corresponding elements <NUM>(<NUM>), <NUM>(<NUM>) of the circuit device <NUM> so as to distribute the first and second supply voltages VDD, VSS to the circuit device <NUM>.

With continuing reference to <FIG>, the first and second high aspect ratio voltage rails <NUM>, <NUM> each have a width W2 approximately equal to three (<NUM>) times a width of a metal line of one or more metal lines in a metal layer in the standard cell circuit <NUM>, such as metal lines <NUM>(<NUM>), <NUM>(<NUM>) extending along axes A3, A4, respectively, along the first direction X substantially parallel to the first and second high aspect ratio voltage rails <NUM>, <NUM>. As illustrated in <FIG>, the longitudinal axes A3, A4 are different from the first and second longitudinal axes A1, A2. The width of the metal lines <NUM>(<NUM>), <NUM>(<NUM>) is approximately equal to a critical dimension (CD) of a process technology used to fabricate the standard cell circuit <NUM>. Further, the first and second high aspect ratio voltage rails <NUM>, <NUM> each have a height-to-width ratio greater than <NUM>. More specifically, a height H2 of the first high aspect ratio voltage rail <NUM> is greater than the width W2 of the first high aspect ratio voltage rail <NUM>. Similarly, the height H2 of the second high aspect ratio voltage rail <NUM> is greater than the width W2 of the second high aspect ratio voltage rail <NUM>. In this example, the height H2 is two (<NUM>) times the width W2 such that the height-to-width ratio of the first and second high aspect ratio voltage rails <NUM>, <NUM> is equal to two (<NUM>). As a result, the first and second high aspect ratio voltage rails <NUM>, <NUM> each extend from a metal layer M0 into a via level V0 and a metal layer M1. In other words, due to the height H2 of the first and second high aspect ratio voltage rails <NUM>, <NUM>, elements in the via level V0 and the metal layer M1 are not needed in addition to vias in a via level V1 to electrically couple the first and second high aspect ratio voltage rails <NUM>, <NUM> to routing interconnects in a metal layer M2. Additionally, in this aspect, elements in a via level V-<NUM> below the metal layer M0 are not needed to couple the first and second high aspect ratio voltage rails <NUM>, <NUM> to the corresponding contact layer interconnects <NUM>, <NUM>.

With continuing reference to <FIG>, the absence of elements in the via levels V-<NUM> and V0, and the metal layer M1 reduces the resistance of the standard cell circuit <NUM>, which reduces the IR drop and increases performance compared to the conventional standard cell circuit <NUM> in <FIG>. Additionally, employing the first and second high aspect ratio voltage rails <NUM>, <NUM> with a greater height H2 than width W2 in this manner allows each to have a cross-sectional area large enough to achieve a relatively lower resistance corresponding to a particular IR drop (e.g., voltage drop). Thus, as a metal with a higher resistivity than copper (Cu) is employed, such as ruthenium (Ru) or cobalt (Co), for example, the first and second high aspect ratio voltage rails <NUM>, <NUM> can be designed to each have a height H2 such that the resulting cross-sectional area limits the resistance and corresponding IR drop to reduce or avoid errors in the standard cell circuit <NUM> resulting from unintended reduced voltages levels due to IR drop energy losses.

<FIG> illustrates an exemplary fabrication process <NUM> for the standard cell circuit <NUM> employing the first and second high aspect ratio voltage rails <NUM>, <NUM> for reduced resistance in <FIG>. The fabrication process <NUM> includes disposing the first high aspect ratio voltage rail <NUM> along the first longitudinal axis A1 in the first direction X, wherein the first high aspect ratio voltage rail <NUM> has a height-to-width ratio greater than <NUM> and is configured to receive the first supply voltage (e.g., VDD) (block <NUM>). The fabrication process <NUM> also includes disposing the second high aspect ratio voltage rail <NUM> extending along the second longitudinal axis A2 in the first direction X substantially parallel to the first high aspect ratio voltage rail <NUM> (block <NUM>). The second high aspect ratio voltage rail <NUM> has a height-to-width ratio greater than <NUM>. The fabrication process <NUM> also includes forming the circuit device <NUM> that is electrically coupled to the first high aspect ratio voltage rail <NUM> and the second high aspect ratio voltage rail <NUM> (block <NUM>). The voltage differential between the first high aspect ratio voltage rail <NUM> and the second high aspect voltage rail <NUM> provides power to the circuit device <NUM>. Additionally, the fabrication process <NUM> can include steps to employ the metal lines <NUM>(<NUM>), <NUM>(<NUM>). For example, the fabrication process <NUM> can include disposing the metal lines <NUM>(<NUM>), <NUM>(<NUM>) along the corresponding longitudinal axes A3, A4, in the first direction X substantially parallel to the first and second high aspect ratio voltage rails <NUM>, <NUM>, wherein each metal line <NUM>(<NUM>), <NUM>(<NUM>) has a width approximately equal to the critical dimension (CD) of the process technology of the standard cell circuit <NUM> (block <NUM>). As discussed above, the first and second high aspect ratio voltage rails <NUM>, <NUM> can each have a width W2 approximately equal to three (<NUM>) times the width (e.g., CD) of the metal lines <NUM>(<NUM>), <NUM>(<NUM>), two (<NUM>) times the width (e.g., CD) of the metal lines <NUM>(<NUM>), <NUM>(<NUM>), approximately equal to the width (e.g., CD) of the metal lines <NUM>(<NUM>), <NUM>(<NUM>), or of any value in a range between width (e.g., CD) of the metal lines <NUM>(<NUM>), <NUM>(<NUM>) and three (<NUM>) times the width (e.g., CD).

In an example not forming part of the claimed invention and in addition to the standard cell circuit <NUM> in <FIG>, other aspects may employ high aspect ratio voltage rails with a reduced width to reduce area consumption while also achieving a reduction in resistance. In this regard, <FIG> illustrate an exemplary standard cell circuit <NUM> employing high aspect ratio voltage rails for reduced resistance. <FIG> illustrates a top-view diagram of the standard cell circuit <NUM>, while <FIG> illustrate cross-sectional views of different instances of the standard cell circuit <NUM> taken generally along line C-C in <FIG>. As discussed in further detail below, <FIG> each illustrate the standard cell circuit <NUM> employing high aspect ratio voltage rails at varying heights according to particular design choices. Further, the standard cell circuit <NUM> includes certain common components with the standard cell circuit <NUM> in <FIG>, as shown by similar element numbers between <FIG>, and <FIG>, and thus will not be re-described herein.

With reference to <FIG>, the standard cell circuit <NUM> employs a first high aspect ratio voltage rail <NUM> extending along a first longitudinal axis A1 in a first direction X and configured to receive a first supply voltage (e.g., VDD). The standard cell circuit <NUM> also employs a second high aspect ratio voltage rail <NUM> extending along a second longitudinal axis A2 in the first direction X substantially parallel to the first high aspect ratio voltage rail <NUM>. The second high aspect ratio voltage rail <NUM> may be configured to receive a second supply voltage (e.g., VSS) or be coupled to ground. In this manner, a voltage differential between the first and second high aspect ratio voltage rails <NUM>, <NUM> is used to power the circuit device <NUM> in the standard cell circuit <NUM>. The first and second high aspect ratio voltage rails 402B, 402D, 404B, 404D in the aspects illustrated in <FIG> and <FIG> are electrically coupled to the first and second power inputs <NUM>, <NUM> by way of the contact layer interconnects <NUM>, <NUM>, respectively. However, the first and second high aspect ratio voltage rails 402C, 404C in the aspect illustrated in <FIG> are electrically coupled to the first and second power inputs <NUM>, <NUM> by way of vias <NUM>, <NUM> and the contact layer interconnects <NUM>, <NUM>, respectively.

With continuing reference to <FIG>, the first and second high aspect ratio voltage rails <NUM>, <NUM> each have a width W3 less than three (<NUM>) times a critical dimension (CD) (e.g., width) of a metal line of one or more metal lines disposed in a metal layer in the standard cell circuit <NUM>, such as the metal lines <NUM>(<NUM>), <NUM>(<NUM>). In this example, the width W3 is approximately equal to two (<NUM>) times the critical dimension (CD) of the metal lines <NUM>(<NUM>), <NUM>(<NUM>). For example, if the standard cell circuit <NUM> has a metal line pitch approximately equal to twenty-eight (<NUM>) nanometers (nm), the critical dimension (CD) of the metal line <NUM>(<NUM>) may be approximately equal to fourteen (<NUM>) nm. Thus, the width W3 is approximately equal to <NUM>. However, other aspects may employ the first and second high aspect ratio voltage rails <NUM>, <NUM> having a width approximately equal to the critical dimension (CD) (e.g., <NUM>).

With reference to <FIG>, the first and second high aspect ratio voltage rails 402B-402D, 404B-404D can be designed with different heights according to design specifications of a particular instance of the standard cell circuit <NUM>. To distinguish between each instance of the first and second high aspect ratio voltage rails <NUM>, <NUM> in <FIG>, a B, C, or D is appended to the element number in <FIG>, respectively.

In this regard, with particular reference to <FIG>, a height H3B of the first and second high aspect ratio voltage rails 402B, 404B is two (<NUM>) times the width W3, such that the height-to-width ratio of the first and second high aspect ratio voltage rails 402B, 404B is equal to two (<NUM>). Because the first and second high aspect ratio voltage rails 402B, 404B have a height H3B, vias in a via level V0 and interconnects in a metal layer M1 would be needed in addition to vias in a via level V1 to electrically couple the first and second high aspect ratio voltage rails 402B, 404B to routing interconnects in a metal layer M2. Alternatively, with particular reference to <FIG>, a height H3C of the first and second high aspect ratio voltage rails 402C, 404C is three (<NUM>) times the width W3, such that the height-to-width ratio of the first and second high aspect ratio voltage rails 402C, 404C is equal to three (<NUM>). Because the first and second high aspect ratio voltage rails 402C, 404C have a height H3C, no elements in the via level V0 and the metal layer M1 would be needed in addition to vias in the via level V1 to electrically couple the first and second high aspect ratio voltage rails 402C, 404C to routing interconnects in the metal layer M2. Additionally, with particular reference to <FIG>, a height H3D of the first and second high aspect ratio voltage rails 402D, 404D is four (<NUM>) times the width W3, such that the height-to-width ratio of the first and second high aspect ratio voltage rails 402D, 404D is equal to four (<NUM>). Because the first and second high aspect ratio voltage rails 402D, 404D have a height H3D, no elements in the via level V0 and the metal layer M1 would be needed in addition to vias in the via level V1 to electrically couple the first and second high aspect ratio voltage rails 402D, 404D to routing interconnects in the metal layer M2.

Although each instance of the standard cell circuit <NUM> illustrated in <FIG> includes differing attributes, employing the first and second high aspect ratio voltage rails <NUM>, <NUM> with the width W3 less than three (<NUM>) times the critical dimension (CD) and the height-to-width ratio of greater than <NUM> in this manner reduces the footprint of the standard cell circuit <NUM>. Additionally, employing the first and second high aspect ratio voltage rails <NUM>, <NUM> with the height-to-width ratio of greater than <NUM> allows the first and second high aspect ratio voltage rails <NUM>, <NUM> to have a cross-sectional area large enough to achieve a resistance corresponding to a particular IR drop. Thus, even with the reduced width W3 and/or a metal with a relatively high resistivity, such as ruthenium (Ru) or cobalt (Co), for example, the first and second high aspect ratio voltage rails <NUM>, <NUM> can be designed to each have a respective height H3B, H3C, H3D that minimizes the corresponding IR drop to reduce or avoid errors in the standard cell circuit <NUM>, while also limiting area consumption.

Additionally, with continuing reference to <FIG>, the standard cell circuit <NUM> also avoids the need to employ copper (Cu) for the first and second high aspect ratio voltage rails <NUM>, <NUM> to achieve a particular IR drop, while using an alternative, more scalable metal for other portions of the standard cell circuit <NUM>. Instead, the standard cell circuit <NUM> may employ a single metal for the first and second high aspect ratio voltage rails <NUM>, <NUM>, as well as for other portions of the standard cell circuit <NUM> and still achieve a desired IR drop due to the height-to-width ratio of the first and second high aspect ratio voltage rails <NUM>, <NUM> being greater than <NUM>. More specifically, the standard cell circuit <NUM> may employ a metal that is more scalable than copper (Cu) for the first and second high aspect ratio voltage rails <NUM>, <NUM> and other portions of the standard cell circuit <NUM> (e.g., the metal lines <NUM>(<NUM>), <NUM>(<NUM>)) even if such a metal has a higher resistivity than copper (Cu), because of the reduced resistance achieved by the height-to-width ratio of greater than <NUM>. Employing a single metal in this manner allows the standard cell circuit <NUM> to be fabricated with limited process complexity and wafer costs.

The elements described herein are sometimes referred to as means for performing particular functions. In this regard, the first high aspect ratio voltage rails <NUM>, <NUM> are sometimes referred to herein as "a means for providing a first supply voltage to the standard cell circuit extending along a first longitudinal axis in a first direction, wherein the means for providing the first supply voltage has a height-to-width ratio greater than <NUM>. " Additionally, the second high aspect ratio voltage rails <NUM>, <NUM> are sometimes referred to herein as "a means for providing a second supply voltage to the standard cell circuit extending along a second longitudinal axis in the first direction substantially parallel to the means for providing the first supply voltage, wherein the means for providing the second supply voltage has a height-to-width ratio greater than <NUM>. " The circuit device <NUM> is sometimes referred to herein as "a means for providing a circuit function electrically coupled to the means for providing the first supply voltage and the means for providing the second supply voltage, wherein a voltage differential between the means for providing the first supply voltage and the means for providing the second supply voltage provides power to the means for providing the circuit function.

The standard cell circuits employing high aspect ratio voltage rails for reduced resistance according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

In this regard, <FIG> illustrates an example of a processor-based system <NUM> that can include elements employing the standard cell circuits <NUM>, <NUM> employing the high aspect ratio voltage rails <NUM>, <NUM>, <NUM>, <NUM> for reduced resistance in <FIG> and <FIG>, respectively. In this example, the processor-based system <NUM> includes one or more central processing units (CPUs) <NUM>, each including one or more processors <NUM>. The CPU(s) <NUM> may have cache memory <NUM> coupled to the processor(s) <NUM> for rapid access to temporarily stored data. The CPU(s) <NUM> is coupled to a system bus <NUM> and can intercouple master and slave devices included in the processor-based system <NUM>. As is well known, the CPU(s) <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the CPU(s) <NUM> can communicate bus transaction requests to a memory controller <NUM> as an example of a slave device. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus <NUM> constitutes a different fabric.

Other master and slave devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include a memory system <NUM>, one or more input devices <NUM>, one or more output devices <NUM>, one or more network interface devices <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device(s) <NUM> can be any device configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, or the Internet. The network interface device(s) <NUM> can be configured to support any type of communications protocol desired. The memory system <NUM> can include one or more memory units <NUM>(<NUM>)-<NUM>(M).

The CPU(s) <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display controller(s) <NUM> sends information to the display(s) <NUM> to be displayed via one or more video processors <NUM>, which process the information to be displayed into a format suitable for the display(s) <NUM>. The display(s) <NUM> can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc..

<FIG> illustrates an exemplary wireless communications device <NUM> that includes radio frequency (RF) components formed in an integrated circuit (IC) <NUM>, wherein the RF components can include elements employing the standard cell circuits <NUM>, <NUM> employing the high aspect ratio voltage rails <NUM>, <NUM>, <NUM>, <NUM> for reduced resistance in <FIG> and <FIG>, respectively. In this regard, the wireless communications device <NUM> may be provided in the IC <NUM>. The wireless communications device <NUM> may include or be provided in any of the above referenced devices, as examples. As shown in <FIG>, the wireless communications device <NUM> includes a transceiver <NUM> and a data processor <NUM>. The data processor <NUM> may include a memory to store data and program codes. The transceiver <NUM> includes a transmitter <NUM> and a receiver <NUM> that support bi-directional communication. In general, the wireless communications device <NUM> may include any number of transmitters and/or receivers for any number of communication systems and frequency bands. All or a portion of the transceiver <NUM> may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc..

A transmitter <NUM> or a receiver <NUM> may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between RF and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for the receiver <NUM>. In the direct-conversion architecture, a signal is frequency-converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the wireless communications device <NUM> in <FIG>, the transmitter <NUM> and the receiver <NUM> are implemented with the direct-conversion architecture.

In the transmit path, the data processor <NUM> processes data to be transmitted and provides I and Q analog output signals to the transmitter <NUM>. In the exemplary wireless communications device <NUM>, the data processor <NUM> includes digital-to-analog-converters (DACs) <NUM>(<NUM>), <NUM>(<NUM>) for converting digital signals generated by the data processor <NUM> into the I and Q analog output signals, e.g., I and Q output currents, for further processing.

Within the transmitter <NUM>, lowpass filters <NUM>(<NUM>), <NUM>(<NUM>) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the prior digital-to-analog conversion. Amplifiers (AMP) <NUM>(<NUM>), <NUM>(<NUM>) amplify the signals from the lowpass filters <NUM>(<NUM>), <NUM>(<NUM>), respectively, and provide I and Q baseband signals. An upconverter <NUM> upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals through mixers <NUM>(<NUM>), <NUM>(<NUM>) from a TX LO signal generator <NUM> to provide an upconverted signal <NUM>. A filter <NUM> filters the upconverted signal <NUM> to remove undesired signals caused by the frequency upconversion as well as noise in a receive frequency band. A power amplifier (PA) <NUM> amplifies the upconverted signal <NUM> from the filter <NUM> to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch <NUM> and transmitted via an antenna <NUM>.

In the receive path, the antenna <NUM> receives signals transmitted by base stations and provides a received RF signal, which is routed through the duplexer or switch <NUM> and provided to a low noise amplifier (LNA) <NUM>. The duplexer or switch <NUM> is designed to operate with a specific receive (RX)-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by the LNA <NUM> and filtered by a filter <NUM> to obtain a desired RF input signal. Downconversion mixers <NUM>(<NUM>), <NUM>(<NUM>) mix the output of the filter <NUM> with I and Q RX LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator <NUM> to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers (AMP) <NUM>(<NUM>), <NUM>(<NUM>) and further filtered by lowpass filters <NUM>(<NUM>), <NUM>(<NUM>) to obtain I and Q analog input signals, which are provided to the data processor <NUM>. In this example, the data processor <NUM> includes analog-to-digital-converters (ADCs) <NUM>(<NUM>), <NUM>(<NUM>) for converting the analog input signals into digital signals to be further processed by the data processor <NUM>.

In the wireless communications device <NUM> of <FIG>, the TX LO signal generator <NUM> generates the I and Q TX LO signals used for frequency upconversion, while the RX LO signal generator <NUM> generates the I and Q RX LO signals used for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. A TX phase-locked loop (PLL) circuit <NUM> receives timing information from the data processor <NUM> and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from the TX LO signal generator <NUM>. Similarly, an RX PLL circuit <NUM> receives timing information from the data processor <NUM> and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from the RX LO signal generator <NUM>.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The master and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system.

Claim 1:
A standard cell circuit (<NUM>), comprising:
a first high aspect ratio voltage rail (<NUM>) extending along a first longitudinal axis perpendicular to the vertical axis in a first direction, the first high aspect ratio voltage rail (<NUM>) having a height-to-width ratio defined as a ratio between a respective height (H2) and a respective width (W2) of the first high aspect ratio voltage rail (<NUM>) greater than <NUM> and configured to receive a first supply voltage;
a second high aspect ratio voltage rail (<NUM>) extending along a second longitudinal axis perpendicular to the vertical axis in the first direction substantially parallel to the first high aspect ratio voltage rail (<NUM>), the second high aspect ratio voltage rail (<NUM>) having a height-to-width ratio defined as a ratio between a respective height (H2) and a respective width (W2) of the second high aspect ratio voltage rail (<NUM>) greater than <NUM>; and
a circuit device (<NUM>) electrically coupled to the first high aspect ratio voltage rail (<NUM>) and the second high aspect ratio voltage rail (<NUM>), wherein a voltage differential between the first high aspect ratio voltage rail (<NUM>) and the second high aspect ratio voltage rail (<NUM>) provides power to the circuit device (<NUM>), wherein:
the respective widths (W2) of the first high aspect ratio voltage rail (<NUM>) and the second high aspect ratio voltage rail (<NUM>) are of any value in a range between a critical dimension of a process technology of the standard cell circuit and three times the critical dimension, the critical dimension of the process technology being a smallest width in which a metal line is fabricated in the process technology; and
the first high aspect ratio voltage rail (<NUM>) and the second high aspect ratio voltage rail (<NUM>) both consist of a metal with a higher resistivity than copper;
characterized in that:
the respective heights (H2) of the first high aspect ratio voltage rail (<NUM>) and the second high aspect ratio voltage rail (<NUM>) are such that the first high aspect ratio voltage rail (<NUM>) and the second high aspect ratio voltage rail (<NUM>) extend from a lower level of a first via layer (V-<NUM>) up through a first metal layer (M0) and a second via level (V0) to an upper level of a second metal layer (M1).