Patent Description:
Within a SoC, different hardware and software components (also referred to as IP blocks and modules) are combined to implement specific functionality. One complication with designing a SoC is that some of the components may be designed to operate at different power requirements, including different voltages and/or different operating frequencies. Additionally, it may be useful in some situations to be able to independently control different groups of components, for example, to place certain components in a sleep mode when full functionality of the components is not required.

Given the prospect of consuming a lot of power by operating all of the components within a SoC, many SoC designers are concerned about power efficient technologies. One power management design approach combines components with similar power requirements into groups, which are referred to as power islands or, in some instances, voltage islands. All of the components within a power island typically have similar power characteristics that are unique from the power characteristics of other power islands. Using power islands, the components within each group may be independently switched on or off. By turning off power to a power island during a time that the power island is not required for operation of a device, the total power consumption of the device can be reduced. Then, when the components of that power island are needed again, the power for that power island can be turned on again. In this way, the battery life of a portable electronic device may be significantly increased by suppressing leakage current of components that are temporarily unused.

While conventional SoC implementations that use power islands to implement dynamic voltage and frequency scaling (DVFS) can save a substantial amount of power, there are still limitations on the amount of power that can be saved using conventional power island designs. In particular, some memory components on an island do not scale to the same degree as logic components and, hence, the memory components of the power island can limit the range that the logic can be scaled. More specifically, internal memory typically has a very narrow voltage range, while logic components typically have a wider voltage range. Hence, the narrow voltage range of the memory limits the voltage range that can be applied to the logic components in the same power island. Accordingly, the memory components which limit the amount of logic scaling also limit the ability to save power through DVFS.

In contrast to embodiments which limit the voltage range of the logic to match the voltage range of the memory, some conventional embodiments may use memory designed for a wider range of voltages. However, designing memory for a wider voltage range prevents optimal memory design and generally results in memory with inferior power and/or speed performance. Also, memory that is designed for a wider voltage range generally uses larger memory cells, which increases the size of the power island.

<CIT> discloses a microcomputer which has a clock generator capable of changing the frequency of an output clock signal and a power circuit capable of changing the level of an operating voltage to be outputted.

<CIT> discloses a system-on-a-chip with a nested voltage island architecture.

The invention is as defined in and by the appended claims. Embodiments of an apparatus are described. In one embodiment, the apparatus is a power island for a system-on-a-chip (SoC). An embodiment of the power island includes a first segment, a second segment, and a supply line. The first segment includes a hardware device which operates at first power characteristics indicative of at least a first voltage. The second segment includes scalable logic which operates at second power characteristics indicative of at least a second voltage. The second power characteristics of the scalable logic are different from the first power characteristics of the hardware device. The supply line receives an external supply signal, VDD, and directs the external supply signal to both the first segment and the second segment. The second segment changes at least one power characteristic of the external supply signal to operate the scalable logic according to the second power characteristics. Other embodiments of the apparatus are also described.

Embodiments of a system are also described. In one embodiment, the system is a SoC. An embodiment of the SoC includes a plurality of power controls and a plurality of power islands. Each power island is coupled to a corresponding power control. Each power control supplies a unique supply signal, VDD, having a supply voltage. Each power island receives a single unique supply signal from the corresponding power control. Each power island includes a first segment and a second segment. The first segment includes a first module which operates at first power characteristics. The first power characteristics include the supply voltage of the unique supply signal from the corresponding power control. The second segment includes a second module which operates at second power characteristics that are at least partially different from the first power characteristics of the first segment. Other embodiments of the system are also described.

Embodiments of a method are also described. In one embodiment, the method is a method for making a power island for a SoC. An embodiment of the method includes coupling a memory device to a supply line of the power island. The supply line receives an external supply signal, VDD, from an external power control to operate the memory device according to first power characteristics. The method also includes coupling a supply power converter to the supply line of the power island. The supply power converter changes at least one power characteristic of the external supply signal to supply an internal supply signal, VDDi, to a logic module on the power island according to second power characteristics that are at least partially different from the first power characteristics. Other embodiments of the method are also described.

Other aspects and advantages of embodiments of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrated by way of example of the principles of the invention.

The present invention may be embodied in other specific forms without departing from its essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims.

Reference throughout this specification to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

While many embodiments are described herein, at least some of the described embodiments relate to implementations of a system-on-a-chip (SoC). In general, embodiments of the SoC include at least one power island which has multiple components. Each of the components operates at specific power characteristics, including a supply voltage and an operating frequency. Alternatively, some of the components may be capable of operating within a range of power characteristics. In certain embodiments, some of the components of the power island operate at a first set of power characteristics, while other components of the power island operate at a second set of power characteristics. In other words, different components of the same power island can be operated at different supply voltages and/or operating frequencies. As one example, one embodiment of a power island operates a memory device (e.g., random access memory (RAM)) using a supply signal provided from an external signal source, while logic on the power island is operated using an adjustable voltage derived from, but different than, the external supply signal. Thus, the memory device is directly supplied by the external signal, while the logic is fed from a different internal signal which is derived from the external signal. Consequently, in some embodiments, the RAM and logic do not need level shifters (despite being at different voltages) because the switching threshold is at half the absolute supply voltage for both of them, for example. The half supply voltage switching threshold is a result of a symmetric voltage drop and voltage rise at the header and footer of the logic, respectively. Without this, logic level conversion would be cumbersome.

For reference, it should also be noted that the power requirements of different components can vary based on the frequency at which the components operate. Although an ideal supply is a direct current (DC) voltage, the supply voltage typically changes in a dynamic way, which is referred to as a frequency. Hence, the supply voltage changes to match the power that is required for each component. Further details of various embodiments are described below, with reference to the appended drawings.

<FIG> depicts a schematic block diagram of one embodiment of a circuit <NUM> with a SoC <NUM> and a power supply integrated circuit (IC) <NUM>. In general, the power supply IC <NUM> provides power to various components of the SoC <NUM>. Although the circuit <NUM> is shown and described with certain components and functionality, other embodiments of the circuit <NUM> may include fewer or more components to implement less or more functionality.

The illustrated power supply IC <NUM> includes multiple DC/DC power controls <NUM>. In one embodiment, DC/DC power controls <NUM> are implemented as DC-to-DC converters, which generate supply signals with specific supply voltages. In one embodiment, the DC/DC power controls <NUM> each generate a unique supply signal (VDD) having a specific supply voltage. For example, the three DC/DC power controls <NUM> shown in <FIG> are depicted as generating three different supply signals: VDD1, VDD2, and VDD3. In other embodiments, different DC/DC power controls <NUM> may generate supply signals with the same or similar supply voltages. Also, in some embodiments, a single DC/DC power control <NUM> may supply multiple components on the SoC <NUM>.

The power supply IC <NUM> also includes a power controller <NUM>. In one embodiment, the power controller <NUM> is coupled to each of the DC/DC power controls <NUM>. The power controller <NUM> controls when each DC/DC power control <NUM> supplies the corresponding supply signal to the SoC <NUM>. Additionally, the power controller <NUM> may control the supply voltage of the supply signal generated by each of the DC/DC power controls <NUM>. In some embodiments, the power controller <NUM> may vary over time the supply voltage of a supply signal generated by one of the DC/DC power controls <NUM>.

The illustrated SoC <NUM> includes several individual power islands <NUM>. Each power island <NUM> may have separate power characteristics, or requirements, for operation of the components specific to each power island <NUM>. For example, each power island <NUM> may have specific requirements for the supply voltage at various operating frequencies for the individual islands. In the illustrated embodiment, each of the three power islands <NUM> receives a separate supply signal (e.g., VDD1, VDD2, or VDD3) from corresponding DC/DC power controls <NUM> of the power supply IC <NUM>. Also, each of the power islands <NUM> is connected to a reference signal, VSS. Although the illustrated power islands <NUM> connect to separate nodes of the same reference signal, VSS, other embodiments of the SoC <NUM> may implement two or more distinct reference sources. Alternatively, multiple power islands <NUM> may connect to the same node of a single reference signal, VSS.

In the depicted embodiment, one of the power islands <NUM> includes a memory segment <NUM> and a logic segment <NUM>. Both the memory segment <NUM> and the logic segment <NUM> are connected to the same supply line <NUM> from one of the DC/DC power controls <NUM> of the power supply IC <NUM>. By virtue of this common supply line <NUM>, both the memory segment <NUM> and the logic segment <NUM> of the power island <NUM> receive the same supply signal. Hence, the same supply voltage is supplied to both the memory segment <NUM> and the logic segment <NUM> of the power island <NUM>.

In one embodiment, the memory segment <NUM> operates at a first set of power characteristics, including a specific supply voltage for a specific operating frequency, either alone or in combination with other power requirements. In contrast, at least a portion of the logic segment <NUM> operates at a second set of power characteristics, which is at least partially different from the first power characteristics of the memory segment <NUM>. For example, the logic segment <NUM> may operate at a supply voltage that is different from the supply voltage of the memory segment <NUM>. As another example, the logic segment <NUM> may operate at an operating frequency that is different from the operating frequency of the memory segment <NUM>. Other embodiments may have other distinct power characteristics.

Although the segments of the power island <NUM> shown in <FIG> are specifically designated as a memory segment <NUM> and a logic segment <NUM>, other embodiments of the power island <NUM> may implement other segments, or components, which may be considered other types of hardware, components, modules, blocks, etc. Thus, the references herein to the memory segment <NUM> and the logic segment <NUM> should be understood as representative examples of specific types of segments, although other embodiments of the power island <NUM> may implement other types of segments.

Some embodiments of the logic segment <NUM> are scalable logic which scales the performance of the logic segment <NUM> according to the voltage level. As an example, scalable logic is faster and consumes more power at higher voltage levels, but can also perform more slowly and consume less power at lower voltage levels. Additionally, although some embodiments of the logic segment <NUM> are described herein as scalable logic, other embodiments of the logic segment <NUM> may include other types of logic.

As described above, the supply line <NUM> provides the same supply voltage to both the memory segment <NUM> and the logic segment <NUM> of the power island <NUM>. However, in some embodiments, the logic segment <NUM> includes functionality to change at least one power characteristic of the external supply signal, VDD, to operate the scalable logic according to the second power characteristics. Furthermore, in some embodiments, the first power characteristics of the memory segment <NUM> are variable to operate the memory segment <NUM> over a first range of power characteristics, and the second power characteristics of the logic segment <NUM> are separately variable, independent of the first power characteristics, to operate at least a portion of the logic segment <NUM> over a second range of power characteristics. For example, the first power characteristics of the memory segment <NUM> may be externally controlled from outside the power island <NUM> (e.g., by one of the DC/DC power controls <NUM>), and the second power characteristics of the logic segment <NUM> may be internally controlled from inside the power island <NUM>, as explained below. Additionally, in some embodiments, the switching threshold of the segment with the lower supply voltage is at the same switching threshold voltage as the other segment as a result of simultaneously lowering a power supply and raising a ground potential.

<FIG> depicts a schematic block diagram of another embodiment of the power island <NUM> of the SoC <NUM> of <FIG>. The illustrated power island <NUM> includes the memory segment <NUM>, the logic segment <NUM>, the common supply line <NUM>, and a conversion controller <NUM>. More specifically, the memory segment <NUM> includes a memory device <NUM>. Also, the logic segment <NUM> includes a supply power converter <NUM>, scalable logic <NUM>, and a reference power converter <NUM>. Although the power island <NUM> is shown and described with certain components and functionality, other embodiments of the power island <NUM> may include fewer or more components to implement less or more functionality.

In one embodiment, the memory device <NUM> used in the power island <NUM> is a self-contained buffer, similar to a first-in first-out (FIFO) block that is in common use and is often used internal to logic blocks to buffer data. Another example of the memory device <NUM> is a video line buffer or frame buffer. Other embodiments may implement other types of memory devices <NUM>.

In one embodiment, within the context of a video decoder that buffers a frame of video, the scalable logic <NUM> is used for the decode operation, while the memory device <NUM> is used for buffering the line. In another example, a disk drive with a read buffer may be implemented, in which the buffer itself is implemented in the memory device <NUM>, and the control logic, error correction, pre-read and other functions could be implemented in the scalable logic <NUM> within the same power island <NUM>.

In one embodiment, the supply power converter <NUM> is coupled between the supply line <NUM> of the power island <NUM> and the scalable logic <NUM>. The supply power converter <NUM> may convert a supply voltage of the external supply signal, VDD, from the first power characteristics to the second power characteristics. For example, the supply power converter <NUM> may generate an internal supply signal, VDDi, which has a supply voltage that is different from the supply voltage of the external supply signal, VDD. Similarly, the reference power converter <NUM> coupled between the reference line of the power island <NUM> and the scalable logic <NUM> converts a reference voltage, VSS, of the reference signal from the first power characteristics to the second power characteristics. For example, the reference power converter <NUM> may generate an internal reference voltage, VSSi, which has a reference voltage or another power characteristic that is different from the corresponding power characteristics of the reference signal, VSS. Thus, the supply and reference power converters <NUM> and <NUM> convert the first power requirements to the second power requirements by altering the power supplied at VDD and VSS. Optionally, the supply and reference power converters <NUM> and <NUM> also alter the frequency supplied to the scalable logic <NUM>.

In one embodiment, the conversion controller <NUM> is coupled to each of the supply and reference power converters <NUM> and <NUM>. In general, the conversion controller <NUM> controls when and how the supply and reference power converters <NUM> and <NUM> change the power characteristics of the supply and reference signals, respectively. Although the conversion controller <NUM> is shown on the power island <NUM> with the memory segment <NUM> and the logic segment <NUM>, other embodiments of the power island <NUM> may exclude the conversion controller <NUM>, in which case another component or device outside of the power island <NUM> may control the operation of the supply and reference power converters <NUM> and <NUM>.

<FIG> depicts a schematic block diagram of another embodiment of the power island <NUM> of the SoC <NUM> of <FIG>. Specifically, the power island <NUM> shown in <FIG> is substantially similar to the power island <NUM> shown in <FIG> and described above. However, the power island <NUM> of <FIG> specifically includes a static RAM (SRAM) as the memory device <NUM> of the memory segment <NUM>. Also, the logic segment <NUM> includes switches as specific types of power converters. In particular, the supply power converter <NUM> of <FIG> is implemented in <FIG> as a VDD switch, and the reference power converter <NUM> of <FIG> is implemented in <FIG> as a VSS switch. Hence, the conversion controller <NUM> of <FIG> is implemented in <FIG> as a switch controller.

In one embodiment, the VDD and VSS switches <NUM> and <NUM> include added resistance which causes corresponding voltage drops and changes the supply and reference voltages according to the first and second power characteristics.

This adds communication between the various components internal to the power island <NUM>. As one example, if the power island is at <NUM> V, then the halfway point, where the complementary metal-oxide semiconductor (CMOS) logic typically switches, will be at about <NUM> V. Signals greater than <NUM> V represent a <NUM>, and signals less than <NUM> V represent a <NUM>. In one embodiment, if both switches (VDD and VSS) drop <NUM> V, then the high and low voltages would be <NUM> V and <NUM> V, respectively. The middle of this new range is still <NUM> V, so signals above <NUM> V still represent a <NUM>, and signals below <NUM> V still represent a <NUM>. By retaining a common switch point, communication between the scalable logic <NUM> and the memory device <NUM> (e.g., RAM) is maintained for multiple voltage settings, and communication between islands of different voltages is simplified because level translators are not necessarily required.

In one embodiment, the switch controller <NUM> controls the VDD switch <NUM> and the VSS switch <NUM> to change the unique supply signal, VDD, and the reference signal, VSS, according to the second power characteristics of the scalable logic <NUM>. In this way, the switch controller <NUM> can vary the second power characteristics of the logic segment <NUM> from inside the power island <NUM>.

<FIG> depicts a schematic voltage diagram <NUM> of operating voltage levels for one embodiment of the power island <NUM> of <FIG>. The illustrated power island <NUM> includes the memory device <NUM> (e.g., RAM), the scalable logic <NUM>, and the switches <NUM> and <NUM> which are depicted as variable resistors. The illustrated power island <NUM> also includes a data bus <NUM> coupled between the memory device <NUM> and the scalable logic <NUM>. The voltage levels on the right side of the memory device <NUM> correspond to operating voltages of the memory device <NUM>, while the voltage levels on the left side of the scalable logic <NUM> correspond to operating voltages of the scalable logic <NUM>. As one example, during a write operation the scalable logic <NUM> may drive the memory device <NUM> with voltages of <NUM> V and <NUM> V. This works because the memory device <NUM> has a voltage threshold of <NUM>. In another embodiment, the memory device <NUM> drives the scalable logic <NUM> with voltages of <NUM> V and <NUM> V. This works because the scalable logic <NUM> also has a voltage threshold of <NUM> V.

<FIG> depicts a schematic block diagram of one embodiment of a system <NUM> for controlling the power island <NUM> of <FIG>. The illustrated system <NUM> includes the power island <NUM>, a DC/DC power control <NUM>, and a power control module <NUM>.

<FIG> depicts a schematic block diagram of one embodiment of a system <NUM> for controlling multiple power islands <NUM>. In the illustrated embodiment, a single DC/DC power control <NUM> is coupled to a plurality of power islands <NUM>. In this way, the DC/DC power control <NUM> may provide the same or different supply signals to multiple power islands <NUM>.

<FIG> depicts a flow chart diagram of one embodiment of a method <NUM> for making a power island <NUM> for a SoC <NUM>. Although the method <NUM> is described in conjunction with the power island <NUM> of the SoC <NUM> of <FIG>, embodiments of the method <NUM> may be implemented with other types of power islands and/or SoC implementations.

At block <NUM>, a memory device <NUM> is coupled to a supply line <NUM> of the power island <NUM>. As explained above, the supply line <NUM> receives an external supply signal, VDD, from a DC/DC power control <NUM> (e.g., an external power control). The power island <NUM> uses the supply signal, VDD, to operate the memory device <NUM> according to first power characteristics. At block <NUM>, a supply power converter <NUM> is coupled to the supply line <NUM> of the power island <NUM>. The supply power converter <NUM> is configured to change at least one power characteristic of the external supply signal, VDD, to generate an internal supply signal, VDDi, according to second power characteristics that are at least partially different from the first power characteristics.

At block <NUM>, scalable logic <NUM> (e.g., a logic module) is coupled to the supply power converter <NUM>. The scalable logic <NUM> receives the internal supply signal, VDDi, and operates according to the second power characteristics. At block <NUM>, a reference power converter <NUM> is coupled to the scalable logic <NUM>. The reference power converter <NUM> changes at least one power characteristic of a reference signal, VSS, to generate an internal reference signal, VSSi, according to the second power characteristics. At block <NUM>, a conversion controller <NUM> is coupled to the supply power converter <NUM> and to the reference power converter <NUM>. As explained above, the conversion controller <NUM> controls the supply power converter <NUM> and the reference power converter <NUM> to generate the internal supply signal, VDDi, and the internal reference signal, VSSi, respectively, according to the second power characteristics. The depicted method <NUM> then ends.

In the above description, specific details of various embodiments are provided. However, some embodiments may be practiced with less than all of these specific details. In other instances, certain methods, procedures, components, structures, and/or functions are described in no more detail than to enable the various embodiments of the invention, for the sake of brevity and clarity.

Claim 1:
A system-on-a-chip, SoC, (<NUM>) comprising:
a first segment (<NUM>), wherein the first segment (<NUM>) includes a memory device (<NUM>) which operates at a first voltage;
a second segment (<NUM>), wherein the second segment (<NUM>) includes scalable logic (<NUM>) which operates at a second voltage;
a supply line (<NUM>) to receive an external supply signal and to direct the external supply signal to both the first segment (<NUM>) and the second segment (<NUM>), wherein the supply line is a common supply line, and wherein by virtue of the common supply line (<NUM>) both the first segment (<NUM>) and the second segment (<NUM>) receive the same supply signal;
a supply power converter (<NUM>) coupled between the supply line (<NUM>) and the scalable logic (<NUM>), wherein the supply power converter (<NUM>) is configured to convert the external supply signal to an internal supply signal;
a conversion controller (<NUM>) coupled to the supply power converter (<NUM>), wherein the conversion controller (<NUM>) is configured to control the supply power converter (<NUM>) to generate the internal supply signal and to thereby vary, independently of the first voltage, the second voltage; and
a power island (<NUM>) including the first segment (<NUM>), the second segment (<NUM>), the supply line (<NUM>), the supply power converter (<NUM>), and the conversion controller (<NUM>);
wherein the first voltage is variable to operate the memory device (<NUM>) over a range of voltages, and the second voltage is separately variable, independent of the first voltage, to operate the scalable logic (<NUM>) over a second range of voltages; and
wherein the first voltage is externally controlled from outside the power island (<NUM>) and the second voltage is internally controlled from inside the power island (<NUM>).