Patent Description:
Hybrid switched-mode converters using both capacitors and inductors as temporary energy reservoirs represent a highly power-efficient and cost-efficient energy supply alternative for lighting systems, and in particular for bus-based lighting systems. They require inductive components of smaller form factor and may thus enable monolithic integration.

When operated by frequency modulation, however, a modulation frequency may become audible for relatively low light outputs (i.e., extensive dimming), such that not the full range of light output is available for dimming.

The document<NPL> discloses an on-chip LED driver based on a DC/DC resonant hybrid-switched capacitor converter operating in the MHz range with and without output capacitor.

In view of the above-mentioned limitations, the present disclosure aims to provide power-efficient and cost-efficient conversion offering dimming across the full range of light output (i.e., down to <NUM>% of a full light output).

The objective is achieved by the embodiments as defined by the appended independent claims. Preferred embodiments are set forth in the dependent claims and in the following description and drawings.

A first aspect of the present disclosure relates to a hybrid switched-mode converter for an LED load. The converter comprises a first decoupling element, a second decoupling element, a third decoupling element and a fourth decoupling element connected in series across an input port of the converter connectable to a DC power source. The converter further comprises a first capacitive storage element connected in parallel to the series connection of the second decoupling element and the third decoupling element. The converter further comprises an inductive storage element and a second capacitive storage element connected in parallel to the series connection of the third decoupling element and the fourth decoupling element. The second capacitive storage element is connected in parallel to an output port of the converter connectable to the LED load. The converter further comprises a control logic being configured to: alternatingly open the first decoupling element and the second decoupling element in accordance with a modulation frequency with an intermediate time lag; preserve a duration of the time lag in a first dimming range of the LED load; and modulate the duration of the time lag in a second dimming range of the LED load.

The first decoupling element and the second decoupling element may respectively comprise an electronic switch.

The third decoupling element and the fourth decoupling element may respectively comprise an electronic switch.

The control logic may further be configured to open the third decoupling element and/or the fourth decoupling element in dependence of respective opening states of the first decoupling element and the second decoupling element.

The third decoupling element and the fourth decoupling element may respectively comprise a diode; and the diodes respectively may be arranged to prevent shorting the DC voltage source.

The first dimming range may extend from a full light output of the LED load to a reduced light output of the LED load achieved at a minimum modulation frequency.

The minimum modulation frequency may comprise a frequency being inaudible to a human ear.

The minimum modulation frequency may comprise <NUM>, more preferably <NUM>, and most preferably <NUM>.

The second dimming range may extend from the reduced light output of the LED load to a minimum light output of the LED load achieved at a minimum duration of the time lag.

The minimum light output of the LED load may comprise <NUM>% of the full light output of the LED load.

The control logic may form part of an integrated circuit, preferably a monolithically integrated circuit.

The control logic may further be configured to operate the first decoupling element in an opened state in first, second and third phases of an operating cycle of the converter, and in a closed state in a fourth phase of the operating cycle. The control logic may further be configured to operate the second decoupling element in an opened state in the first, third and fourth phases of the operating cycle, and in a closed state in the second phase of the operating cycle. A respective duration of the first and third phases may correspond to the intermediate time lag.

A second aspect of the present disclosure relates to a lighting system, comprising a lighting bus; a DC power source being configured to supply DC power to the lighting bus; and a number of hybrid switched-mode converters of the first aspect or any of its implementations. The respective converter is configured to supply DC power to a respective LED load off the lighting bus.

A third aspect of the present disclosure relates to a method of operating a hybrid switched-mode converter of the first aspect or any of its implementations. The method comprises: alternatingly opening the first decoupling element and the second decoupling element with an intermediate time lag in accordance with a modulation frequency; preserving a duration of the time lag in a first dimming range of the LED load; and modulating the duration of the time lag in a second dimming range of the LED load.

The present disclosure provides hybrid switched-mode conversion which enables dimming across the full range of light output by accompanying frequency modulation with an additional form of modulation for relatively low light outputs (i.e., extensive dimming). The additional modulation further reduces a duration of an intermediate time lag between alternating decoupling actions of serially connected decoupling elements (i.e., switches).

During the intermediate time lag, both of the serially connected decoupling elements are conductive. Owing to the overlapping operation, the intermediate time lag may also be termed overlap time or overlap period. During said time lag, a current may flow from a supply side through the serially connected decoupling elements to a load side. Decreasing a (modulation) frequency of decoupling (switching) actions reduces an average current provided to the load side. When a further decrease of the (modulation) frequency would become audible, the frequency is fixated and the average current flowing through the series connection and supplying the load side is further reduced by shortening the duration of the intermediate time lag.

Therefore, the additional duration modulation of the overlap time of the serially connected decoupling elements enables dimming down to a lower end of the full range of light output.

The technical effects and advantages described above in relation with the hybrid switched-mode conversion equally apply to the converter itself, to the method of operating the same having corresponding features, and to the lighting system comprising such converters.

The above-described aspects and implementations will now be explained with reference to the accompanying drawings, in which the same or similar reference numerals designate the same or similar elements.

The features of these aspects and implementations may be combined with each other unless specifically stated otherwise.

The drawings are to be regarded as being schematic representations, and elements illustrated in the drawings are not necessarily shown to scale. Rather, the various elements are represented such that their function and general purpose become apparent to those skilled in the art.

<FIG> illustrates a hybrid switched-mode step-down converter <NUM> in accordance with the present disclosure.

As indicated in <FIG>, the converter <NUM> is suitable for an LED load <NUM> connectable to an output port of the converter <NUM>.

The converter <NUM> comprises a first decoupling element <NUM>, a second decoupling element <NUM>, a third decoupling element <NUM> and a fourth decoupling element <NUM> connected in series across an input port of the converter <NUM> connectable to a DC power source <NUM>. A voltage supplied by the DC power source <NUM> is identified as U<NUM>.

The converter <NUM> further comprises a control logic <NUM> configured to operate the respective decoupling element <NUM>-<NUM> provided that this is warranted, as will be explained below in more detail. The control logic <NUM> may form part of an integrated circuit, preferably a monolithically integrated circuit.

The first decoupling element <NUM> and the second decoupling element <NUM> may respectively comprise an electronic switch, as shown in <FIG>. As such, the control logic <NUM> is configured to operate the respective decoupling element <NUM>, <NUM>. Drive currents of the respective decoupling element <NUM>-<NUM> are identified as IG11 and IG12, respectively.

The third decoupling element <NUM> and the fourth decoupling element <NUM> may respectively comprise a diode, as shown in <FIG>, in which case the control logic <NUM> is not configured to operate the respective decoupling element <NUM>, <NUM>. The diodes arranged to prevent shorting the DC voltage source (i.e., the cathodes oriented towards a high-side potential, and the anodes oriented towards a low-side potential).

Alternatively, the third decoupling element <NUM> and the fourth decoupling element <NUM> may also comprise respective electronic switches, in which case the control logic <NUM> may further be configured to operate the respective decoupling element <NUM>, <NUM>. More specifically, the control logic <NUM> may be configured to open the third decoupling element <NUM> and/or the fourth decoupling element <NUM> in dependence of respective opening states of the first decoupling element <NUM> and the second decoupling element <NUM>. In other words, the third decoupling element <NUM> and the fourth decoupling element <NUM> may be operated in accordance with a well-known synchronous operation for reduction of switching loss.

The converter <NUM> further comprises a first capacitive storage element <NUM> (flying capacitor) connected in parallel to the series connection of the second decoupling element <NUM> and the third decoupling element <NUM>. A voltage across the first capacitive storage element <NUM> is identified as U<NUM>.

The converter <NUM> further comprises an inductive storage element <NUM> (having an inductance of L<NUM>) and a second capacitive storage element <NUM> (smoothing capacitor) connected in parallel to the series connection of the third decoupling element <NUM> and the fourth decoupling element <NUM>. The second capacitive storage element <NUM> is connected in parallel to the output port of the converter <NUM> connectable to the LED load <NUM>. A current of the inductive storage element <NUM> is identified as I<NUM>, and a load current of the LED load <NUM> is identified as I<NUM>, and a voltage across the LED load <NUM> is identified as U<NUM>.

The control logic <NUM> is configured to alternatingly open the first decoupling element <NUM> and the second decoupling element <NUM> in accordance with a modulation frequency with an intermediate time lag, wherein in a first dimming range of the LED load <NUM>, the control logic <NUM> is configured to preserve a duration of the time lag; and in a second dimming range of the LED load <NUM>, the control logic <NUM> is configured to modulate the duration of the time lag.

A more detailed explanation of the operation of the hybrid switched-mode converter <NUM> will be provided next.

<FIG> illustrate operation phases of the converter of <FIG>.

In a first operation phase depicted in <FIG>, both the first decoupling element <NUM> and the second decoupling element <NUM> are operated in a closed (conducting) state. The DC power source <NUM> directly charges the inductive storage element <NUM>. The current I<NUM> of the inductive storage element <NUM> therefore increases almost linearly over time: <MAT>.

In a second operation phase depicted in <FIG>, the first decoupling element <NUM> is maintained in the closed (conducting) state, and the second decoupling element <NUM> is operated in an open (non-conducting) state. The DC power source <NUM> now directly charges the first capacitive storage element <NUM>, and a resonant current between the first capacitive storage element <NUM> and the inductive storage element <NUM> emerges until the latter is charged. The current I<NUM> of the inductive storage element <NUM> decreases until it reaches zero. A maximum drop of the voltage U<NUM> across the first capacitive storage element <NUM> is clamped by the fourth decoupling element <NUM>. So when increasing a capacitance of the first capacitive storage element <NUM>, the current I<NUM> of the inductive storage element <NUM> increases as long as the voltage U<NUM> across the first capacitive storage element <NUM> is smaller as or equal to U<NUM>.

In a third operation phase depicted in <FIG>, the first decoupling element <NUM> is maintained in the closed (conducting) state and the second decoupling element <NUM> is operated in the closed (conducting) state. That is to say, with reference to the operating states of the first and second decoupling elements <NUM>, <NUM>, the third operation phase corresponds to the first operation phase, but the state of charge of the first capacitive storage element <NUM> has changed. Again, the DC power source <NUM> directly charges the inductive storage element <NUM>.

In a fourth operation phase depicted in <FIG>, the first decoupling element <NUM> is operated in the open (non-conducting) state, and the second decoupling element <NUM> is maintained in the closed (conducting) state state. Therefore, the first capacitive storage element <NUM> is discharged via the inductive storage element <NUM>, and the converter <NUM> completes the quasi-resonant cycle started in the second operation phase.

<FIG> illustrates waveforms of the operation phases of the converter of <FIG>.

In the first operation phase indicated in <FIG> as (<NUM>), both the first decoupling element <NUM> and the second decoupling element <NUM> are operated in a closed (conducting) state (i.e., the drive currents IG11 and IG12 are non-zero). The DC power source <NUM> directly charges the inductive storage element <NUM>. The current I<NUM> of the inductive storage element <NUM> therefore increases almost linearly over time (note the sharply rising edge of current I<NUM>).

In the second operation phase indicated in <FIG> as (<NUM>), the first decoupling element <NUM> is maintained in the closed (conducting) state (the drive current IG11 remains non-zero), and the second decoupling element <NUM> is operated in an open (non-conducting) state (the drive current IG12 becomes zero). The DC power source <NUM> now directly charges the first capacitive storage element <NUM> (note the rising edge of voltage U<NUM>), and a resonant current between the first capacitive storage element <NUM> and the inductive storage element <NUM> emerges until the former is charged. The current I<NUM> of the inductive storage element <NUM> decreases until it reaches zero (note the sharply falling edge of current I<NUM>).

In the third operation phase indicated in <FIG> as (<NUM>), the first decoupling element <NUM> is maintained in the closed (conducting) state (the drive current IG11 remains non-zero) and the second decoupling element <NUM> is operated in the closed (conducting) state (the drive current IG12 becomes non-zero). Again, the DC power source <NUM> directly charges the inductive storage element <NUM>, and the current I<NUM> of the inductive storage element <NUM> increases almost linearly over time (note the sharply rising edge of current I<NUM>).

In the fourth operation phase indicated in <FIG> as (<NUM>), the first decoupling element <NUM> is operated in the open (non-conducting) state (the drive current IG11 becomes zero), and the second decoupling element <NUM> is maintained in the closed (conducting) state (the drive current IG12 remains non-zero). Therefore, the first capacitive storage element <NUM> is discharged (note the falling edge of voltage U<NUM>) via the inductive storage element <NUM>, and the converter <NUM> completes the quasi-resonant cycle started in the second operation phase (note the sharply falling edge of current I<NUM>).

In summary, the control logic <NUM> is configured to alternatingly open the first decoupling element <NUM> and the second decoupling element <NUM> in accordance with the modulation frequency indicated asf in <FIG>. An average value of the current I<NUM> of the LED load may be increased or decreased by increasing or decreasing the modulation frequency. That is to say, the LED load may be dimmed by decreasing the modulation frequency.

When a further decrease of the modulation frequency would become audible, the frequency f may be fixated and the average value of the load current I<NUM> may further be reduced by shortening the duration of the intermediate time lag, which is indicated as d in <FIG>.

<FIG> illustrates a modulation frequency of the converter of <FIG> as a function of light output, and <FIG> illustrates a duration of the first and third operating phases of the converter of <FIG> as a function of light output.

<FIG> shows the first and second dimming ranges of the LED load <NUM>. The first (moderate) dimming range may extend from a full i.e., <NUM>% light output of the LED load <NUM> to a reduced (X%) light output of the LED load <NUM> achieved at a minimum modulation frequency. In particular, the minimum modulation frequency may comprise a frequency being inaudible to a human ear, such as <NUM>, more preferably <NUM>, and most preferably <NUM>. The second (more extensive) dimming range may extend from the reduced (X%) light output of the LED load <NUM> to a minimum light output of the LED load <NUM> achieved at a minimum duration of the time lag. in particular, the minimum light output of the LED load <NUM> may comprise <NUM>% of the full light output of the LED load <NUM>.

Generally, the control logic <NUM> is configured to alternatingly open the first decoupling element <NUM> and the second decoupling element <NUM> in accordance with the modulation frequency f.

In the first (moderate) dimming range, the control logic <NUM> is configured to perform the frequency modulation and to maintain a duration J of the intermediate time lag between alternating decoupling actions of the serially connected first and second decoupling elements <NUM>, <NUM> constant. Therefore, the LED load <NUM> may be dimmed by linearly decreasing the modulation frequency f (see <FIG>) and keeping the duration of the intermediate time lag d constant (see <FIG>).

In the second (more extensive) dimming range, the control logic <NUM> is configured to maintain the frequency modulation constant and to modulate the duration J of the intermediate time lag. As such, the LED load <NUM> may be dimmed further by linearly decreasing the duration d of the intermediate time lag (see <FIG>) and keeping the modulation frequency f constant (see <FIG>).

For example, given certain component values a full (<NUM>%) light output of 350mA may be achieved for an intermediate time lag of <NUM> ns. Upon dimming, the modulation frequency f may be decreased down to a minimum frequency of e.g. <NUM>, which defines the X% point in <FIG>. In the example, the lowest reachable LED current I<NUM> achievable by frequency modulation amounts to <NUM> mA (X = <NUM>/<NUM> ≈ <NUM>%).

To achieve even lower light outputs, the duration d of the intermediate time lag requires reduction as well. Upon continued dimming, the duration d may be decreased down to the Y% point in <FIG>, which corresponds to the minimum (<NUM>%) light output of the LED load <NUM>. In the example, this minimum duration amounts to <NUM> ns (Y% = <NUM>/<NUM> ≈ <NUM>%).

Accordingly, the minimum (<NUM>%) light output of the LED load <NUM> achieved at the minimum duration of the time lag and the minimum modulation frequency amounts to an LED current I<NUM> of <NUM>,<NUM> mA (<NUM>,<NUM>/<NUM> = <NUM>%). That is to say, dimming down to <NUM>% of the full light output of the LED load <NUM> may be achieved.

<FIG> illustrates a lighting system <NUM> in accordance with the present disclosure.

The lighting system <NUM> comprises a lighting bus <NUM>.

The lighting system <NUM> further comprises a DC power source <NUM> being configured to supply DC power to the lighting bus <NUM>.

The lighting system <NUM> further comprises a number of hybrid switched-mode converters <NUM> of the first aspect or any of its implementations.

The respective converter is connected to the lighting bus <NUM>, and configured to supply DC power to a respective LED load <NUM> off the lighting bus <NUM>.

<FIG> illustrates a flow chart of a method <NUM> in accordance with the present disclosure of operating the converter of <FIG>.

The method <NUM> is suitable of operating a hybrid switched-mode converter <NUM> of the first aspect or any of its implementations.

The method <NUM> comprises a step of alternatingly opening <NUM> the first decoupling element <NUM> and the second decoupling element <NUM> with an intermediate time lag in accordance with a modulation frequency.

The method <NUM> further comprises a step of preserving <NUM> a duration of the time lag in a first dimming range of the LED load <NUM>.

Claim 1:
A hybrid switched-mode converter (<NUM>) for an LED load (<NUM>), comprising
a first decoupling element (<NUM>), a second decoupling element (<NUM>), a third decoupling element (<NUM>) and a fourth decoupling element (<NUM>) connected in series across an input port of the converter (<NUM>) connectable to a DC power source (<NUM>);
a first capacitive storage element (<NUM>) connected in parallel to the series connection of the second decoupling element (<NUM>) and the third decoupling element (<NUM>);
a series connection comprising an inductive storage element (<NUM>) and a second capacitive storage element (<NUM>) connected in parallel to the series connection of the third decoupling element (<NUM>) and the fourth decoupling element (<NUM>), wherein the second capacitive storage element (<NUM>) is connected in parallel to an output port of the converter (<NUM>) connectable to the LED load (<NUM>); and
a control logic (<NUM>) being configured to
alternatingly open the first decoupling element (<NUM>) and the second decoupling element (<NUM>) in accordance with a modulation frequency with an intermediate time lag in which the first decoupling element (<NUM>) and the second decoupling element (<NUM>) are closed;
and characterised in that the control logic is further configured to
preserve a duration of the time lag and linearly decrease the modulation frequency in a first dimming range of the LED load (<NUM>); and
modulate the duration of the time lag and maintain the frequency modulation constant in a second dimming range of the LED load (<NUM>).