Patent Description:
<CIT> discloses thermal vias arranged on an upper surface of a printed circuit board (PCB).

<CIT> discloses that a multi-layer substrate is mounted on a PCB, an integrated circuit (IC) die is flip-chip mounted to the substrate, a solderable pad is placed on the PCB underneath the IC die, and the back side of the IC die is metalized with a metal component.

As known in the art, a semiconductor chip package typically comprises an integrated circuit (IC) die and a molding compound that encapsulates the IC die. During operation, the IC die generates significant amount of heat, which can cause damage to the IC die or reduce the IC reliability. In a hybrid chip scale package (hybrid CSP), for example, the heat generated from one IC die such as an SoC die can be detrimental to the proximate IC die such as a DRAM die stacked on the SoC die, which leads to reduced overall chip performance.

To dissipate heat away from the IC die, the semiconductor chip package is often connected with an external heat spreading structure such as a heat spreader or heat sink attached to the IC die. To spread heat to the ambient environment, the heat spreading structure is often mounted onto a contact surface of the semiconductor chip package by applying a thermal interface material (TIM) such as thermal greases or conductive polymers on the contact surface.

However, the conventional thermal solution involving the use of TIM is not satisfactory. The conventional design using the TIM has problems such as thermal bottleneck and poor adhesion. It is desirable to have low contact resistance and good thermal interface between the IC die and the heat spreading structures for efficient heat conduction from the IC die through the heat spreading structures. It is also desirable to provide an improved heat transfer mechanism/medium employed between the components to effectively transfer heat away from the IC die.

The above-mentioned objectives are achieved by a printed circuit board assembly according to independent claim <NUM>. The dependent claims define preferred embodiments thereof.

According to one embodiment not forming part of the present invention but useful to understand the invention, a semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) structure embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of solder ball pads disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in direct contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

Preferably, the RF structure comprises a top antenna layer and a bottom antenna layer spaced apart from the top antenna layer, and at least one dielectric layer interposed between the top antenna layer and the bottom antenna layer.

Preferably, the backside metal layer comprises Au.

Preferably, the solder paste comprises lead-free solder comprising tin, copper, silver, bismuth, indium, zinc, or antimony.

Preferably, the base comprises metal traces and vias for interconnection.

Preferably, the solder ball pads are electrically connected to the RF structure of the base through the metal traces and vias.

Preferably, the semiconductor package further comprises an underfill disposed in the gap between the IC die and the lower surface of the base.

Preferably, a combined thickness of the underfill, the IC die, and the metal thermal interface layer is substantially equal to a ball height of the solder balls measured from the lower surface of the base.

Preferably, the solder paste is thicker than the backside metal layer.

An embodiment of the invention provides a printed circuit board assembly including a printed circuit board having an upper surface directly facing the lower surface of the base, wherein the printed circuit board comprises an array of copper thermal pads on the upper surface of the printed circuit board, a plurality of thermal vias within the printed circuit board under the array of copper thermal pads, a heat spreading structure mounted onto a lower surface of the printed circuit board, wherein the heat spreading structure is in thermal contact with the plurality of thermal vias. The semiconductor package as described above is mounted on the array of copper thermal pads.

Preferably, the plurality of thermal vias comprises plated though holes.

Preferably, the heat spreading structure comprises a heat sink.

According to the present invention, the solder paste is in direct contact with the array of copper thermal pads.

Further, according also to the present invention, the array of copper thermal pads comprises slits between the thermal pads and the slits are filled with the solder paste.

The scope of the invention is determined by reference to the appended claims.

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.

In general, the present disclosure pertains to a semiconductor package comprising at least one integrated circuit (IC) die attached to a substrate in, for example, a "flip chip" configuration. In such a flip chip configuration, bumps are formed on signal pads or terminals of the IC die, and the IC die may be inverted ("flipped") and attached to substrate by reflowing bumps so that they attach to corresponding pads on the surface of substrate. The IC die may be one of the many types of IC dies. For example, IC die may be a radio-frequency (RF) IC die, a microprocessor die, an application-specific integrated circuit (ASIC), or a memory die according to various embodiments useful to understand the invention.

The substrate may be one of the different types of substrates known to those skilled in the relevant arts (e.g., organic or inorganic substrates). The substrate may be made from one or more conductive layers bonded with a dielectric material. For example, the dielectric material may be made from various substances, such as bismaleimide triazine (BT). The conductive layers may be made from a metal, or combination of metals, such as copper and aluminum, that facilitate coupling between IC die and solder balls. Trace or routing patterns may be made in the conductive layer by, for example, etching the conductive layer. The substrate may be a single-layer, a two-layer, or multi-layer substrate.

The exemplary semiconductor package may be a RFIC chip package with antenna array structure that is particularly suited for millimeter wave (mmW) applications or radar systems. However, it is to be appreciated that the principles of the present invention should not be limited to any particular package type or IC die. Rather, the principles of the invention are directed broadly to techniques for improved thermal interface material application in the fabrication process of a printed circuit board (PCB) assembly that includes an integrated circuit package and a heat transfer device.

<FIG> is a schematic, cross-sectional diagram showing an exemplary semiconductor package in accordance with one embodiment not forming part of the present invention but useful to understand the invention. As shown in <FIG>, the semiconductor package <NUM> comprises a base <NUM> having a radio-frequency (RF) structure <NUM> embedded near an upper surface 10a of the base <NUM>. In some embodiments useful to understand the invention, the base <NUM> could be a package substrate, a silicon interposer or a printed circuit board (PCB). In other embodiments useful to understand the invention, the radio-frequency (RF) structure <NUM> may comprise an antenna array, for example, the radio-frequency (RF) structure <NUM> may comprise a top antenna layer <NUM> and a bottom antenna layer <NUM> spaced apart from the top antenna layer <NUM>. For example, at least one dielectric layer <NUM> may be interposed between the top antenna layer <NUM> and the bottom antenna layer <NUM>. Preferably, the top antenna layer <NUM> and the bottom antenna layer <NUM> may be formed in the upper metal layers of the base <NUM>, but not limited thereto. The base <NUM> may comprise metal traces <NUM> and vias <NUM> for interconnection.

Preferably, for example, the semiconductor package <NUM> may further comprise an IC die <NUM> such as an RFIC die mounted on the lower surface 10b of the base <NUM>. The IC die <NUM> is mounted on the lower surface 10b in a flip-chip manner so that the backside 20b of the IC die <NUM> is exposed and available for heat dissipation. The flip-chip type connection is a method for interconnecting a flipped IC die <NUM> to external circuitry with bumps <NUM> such as micro bumps or copper pillar bumps disposed on the chip pads of the IC die <NUM>. The bumps <NUM> are aligned with and electrically connected to the copper pads <NUM> disposed at the lower surface 10b of the base <NUM>. Optionally, an underfill <NUM> may be applied to the gap between the IC die <NUM> and the lower surface 10b of the base <NUM>.

Preferably, for example, the semiconductor package <NUM> may further comprise a plurality of conductive pads <NUM> disposed on the lower surface 10b of the base <NUM> and arranged around the IC die <NUM>. The conductive pads <NUM> may be electrically connected to the circuit including the RF structure <NUM> of the base <NUM> through the metal traces <NUM> and vias <NUM>. A plurality of conductive structures <NUM> such as ball grid array (BGA) balls may be disposed on the conductive pads <NUM>, respectively, for electrically connecting the circuit including the RF structure <NUM> of the base <NUM> with the external circuit device such as a printed circuit board (PCB).

Preferably, for example, the semiconductor package <NUM> may further comprise a metal thermal interface layer <NUM>. The metal thermal interface layer <NUM> may be a metal bi-layer structure comprising a backside metal layer <NUM> that is in direct contact with the backside 20b of the IC die <NUM>, and a solder paste <NUM> conformally printed on the backside metal layer <NUM>. Preferably, the backside metal layer <NUM> may comprise Au, but not limited thereto. For example, the backside metal layer <NUM> may be Au layer that is sputtered onto the backside 20b of the IC die <NUM>.

For example, the solder paste (or pre-solder) <NUM> may be formed by stencil printing methods, but not limited thereto. For example, the solder paste <NUM> may comprise any lead-free solders in commercial use, which may contain tin, copper, silver, bismuth, indium, zinc, antimony, and traces of other metals. Preferably, for example, the solder paste <NUM> may be thicker than the backside metal layer <NUM>. It is noteworthy that the metal thermal interface layer <NUM> does not comprise a conventional thermal interface material (TIM) such as thermal grease or conductive polymer.

Preferably, the combined thickness of the underfill <NUM>, the IC die <NUM>, and the metal thermal interface layer <NUM> is substantially equal to the ball height h of the conductive structures <NUM> measured from the lower surface 10b of the base <NUM>.

Please refer to <FIG> is a schematic, cross-sectional diagram showing an exemplary PCB assembly including the semiconductor package in <FIG> according to one embodiment of the invention. As shown in <FIG>, the exemplary PCB assembly <NUM> comprises a PCB <NUM> having an upper surface 4a directly facing the lower surface 10b of the base <NUM>. Preferably, an array of copper thermal pads <NUM> may be disposed within a solder resist opening 402a in the solder resist layer <NUM> on the upper surface 4a of the PCB <NUM>.

Preferably, the span of the array of conductive thermal pads <NUM> may be in commensurate with the area of the backside 20b of the IC die <NUM>. Preferably, the span of the array of conductive thermal pads <NUM> may be slightly greater than the area of the backside 20b of the IC die <NUM>. For example, the distance from the edge of the IC die <NUM> to the perimeter of the array of conductive thermal pads <NUM> may be about <NUM> micrometers, but not limited thereto.

According to the present invention, slits or gaps <NUM> are formed between the adjacent conductive thermal pads <NUM>. According to the present invention, a plurality of thermal vias <NUM> is formed within the PCB <NUM> under the array of the conductive thermal pads <NUM>. The thermal vias <NUM> are in thermal contact with the conductive thermal pads <NUM>, respectively. Preferably, the thermal vias <NUM> are plated though holes. According to the present invention, a heat spreading structure <NUM> such as a heat sink is mounted onto the lower surface 4b of the PCB <NUM>. The heat spreading structure <NUM> is in thermal contact with the thermal vias <NUM>.

The semiconductor package <NUM> as depicted in <FIG> is mounted onto the upper surface 4a of the PCB <NUM> such that the solder paste <NUM> is laminated onto the array of conductive thermal pads <NUM>. With suitable pressing force, the solder paste <NUM> is forced (or squeezed) into the slits <NUM>. By providing such configuration, more heat dissipating surface area is produced. The conductive structures <NUM> are aligned with matching pads <NUM> on the upper surface 4a of the PCB <NUM>. The solder paste <NUM> and the conductive structures <NUM> may be subjected to a reflow process so as to form permanent bond. The metal thermal interface layer <NUM> is used as a high-efficiency heat transfer medium that allows heat energy to rapidly move from the IC die <NUM> to the conductive thermal pads <NUM> and plated thermal vias <NUM> of the PCB <NUM> to the heat spreading structure <NUM>. Further, it is advantageous to use the present invention because the adhesion between the semiconductor package <NUM> and the PCB <NUM> can be significantly improved.

Please refer to <FIG> are schematic, cross-sectional diagrams showing semiconductor packages in accordance with various embodiments not forming part of the present invention but useful to understand the invention. For example, the illustrative semiconductor packages may be a hybrid CSP having a flip-chip die and a wire-bonded die stacked on the flip-chip die.

As shown in <FIG>, the semiconductor package 3a comprises a base <NUM> having a top surface 100a and a bottom surface 100b. A plurality of connecting elements <NUM> such as solder balls may be disposed on the bottom surface 100b for further connection. A semiconductor chip <NUM> is mounted on the top surface 100a of the base <NUM>. In a non-limiting example, the semiconductor chip <NUM> may be a system-on-a-chip (SoC) and may generate heat during operation.

Preferably, the semiconductor chip <NUM> may be mounted on the top surface 100a in a flip-chip manner by aligning and connecting the bumps (micro bumps or copper pillar bumps) <NUM> on the active surface of the semiconductor chip <NUM> with the matching pads <NUM> on the top surface 100a of the base <NUM>. An optional underfill <NUM> may be applied to fill the gap between the semiconductor chip <NUM> and the top surface 100a of the base <NUM>.

Preferably, a semiconductor chip (or package) <NUM> may be stacked directly on the semiconductor chip <NUM> and may be electrically coupled to the base <NUM> by using wire bonding WB. In a non-limiting example, the semiconductor chip <NUM> may be a memory chip; In another example, the semiconductor chip <NUM> may be a Known Good Die (KGD) chip, but is not limited thereto. Preferably, the semiconductor chip <NUM> may be adhered to the top surface of the semiconductor chip <NUM> by using a die attach film (DAF) <NUM> comprising, for example, an epoxy adhesive layer. Preferably, for example, the DAF <NUM> has thermal conductivity of about <NUM> W/m-K.

Preferably, the semiconductor package 3a further comprises an in-package heat dissipating element <NUM> such as a dummy silicon die that is adhered on the top surface of the semiconductor chip <NUM> by using a high-thermal conductive die attach film (high-thermal conductive DAF) <NUM>. Preferably, the high-thermal conductive DAF <NUM> is an adhesive film with high thermal conductive property. Preferably, the high-thermal conductive DAF <NUM> has a higher thermal conductivity than that of the DAF <NUM>. Preferably, for example, the high-thermal conductive DAF <NUM> may have thermal conductivity of about <NUM>-<NUM> W/m-K.

Preferably, the semiconductor package 3a further comprises a molding compound <NUM> that encapsulates the semiconductor die <NUM>, the semiconductor die <NUM>, and the heat dissipating element <NUM>. Preferably, for example, the molding compound <NUM> may have thermal conductivity of about <NUM>-<NUM> W/m-K; for another example, the molding compound <NUM> may have thermal conductivity of 1W/m-K.

In <FIG>, likewise, the semiconductor package 3b comprises a base <NUM>, a semiconductor chip <NUM> such as an SoC mounted on the base <NUM> in a flip-chip manner, a semiconductor chip <NUM> such as a DRAM chip adhered onto the semiconductor chip <NUM> by using a DAF <NUM>, a heat dissipating element <NUM> such as a dummy silicon die adhered onto the semiconductor chip <NUM> by using a high-thermal conductive DAF <NUM>. The difference between the semiconductor package 3a in <FIG> and the semiconductor package 3b in <FIG> is that the top surface 105a of the heat dissipating element <NUM> is exposed to air. To form such configuration, the molding compound <NUM> may be subjected to a polishing or grinding process. After removing a portion of the molding compound <NUM>, the top surface 105a of the heat dissipating element <NUM> may be flush with the top surface of the molding compound <NUM>.

In <FIG>, instead of attaching the heat dissipating element <NUM> onto the semiconductor die <NUM>, the heat dissipating element <NUM> of the semiconductor package 5a is attached to the top surface of the semiconductor die <NUM> by using a high-thermal conductive DAF <NUM> as previously described. Therefore, the semiconductor die <NUM> and the heat dissipating element <NUM> are both attached onto the top surface of the semiconductor die <NUM> in a side-by-side manner.

In <FIG>, likewise, the semiconductor package 5b comprises a base <NUM>, a semiconductor chip <NUM> such as an SoC mounted on the base <NUM> in a flip-chip manner, a semiconductor chip <NUM> such as a DRAM chip adhered onto the semiconductor chip <NUM> by using a DAF <NUM>, a heat dissipating element <NUM> such as a dummy silicon die adhered onto the semiconductor chip <NUM> by using a high-thermal conductive DAF <NUM>. The difference between the semiconductor package 5a in <FIG> and the semiconductor package 5b in <FIG> is that the top surface 105a of the heat dissipating element <NUM> is exposed to air.

Preferably, the semiconductor chip <NUM> is a major heat source of the semiconductor package 3a and the heat needs to be rapidly removed from the semiconductor package 3a to the ambient environment. By providing the configuration through <FIG>, the thermal performance is significant improved (~<NUM>% improvement). For example, the measured theta JC (θJC) of the illustrative semiconductor package 5b in <FIG> may be about <NUM>.

Claim 1:
A printed circuit board assembly (<NUM>), comprising:
a semiconductor package (<NUM>); and
a print circuit board, in the following also referred to as PCB (<NUM>);
wherein the semiconductor package (<NUM>) comprises:
a base (<NUM>) comprising an upper surface (10a) and a lower surface (10b) that is opposite to the upper surface (10a);
a radio-frequency, in the following also referred to as RF, structure (<NUM>) embedded near the upper surface (10a) of the base (<NUM>);
an integrated circuit, in the following also referred to as IC, die (<NUM>) mounted on the lower surface (10b) of the base (<NUM>) in a flip-chip manner so that a backside (20b) of the IC die (<NUM>) is available for heat dissipation;
a plurality of conductive structures (<NUM>, <NUM>) disposed on the lower surface (10b) of the base (<NUM>) and arranged around the IC die (<NUM>); and
a metal thermal interface layer (<NUM>) comprising a backside metal layer (<NUM>) that is in direct contact with the backside (20b) of the IC die (<NUM>), and a solder paste (<NUM>) conformally printed on the backside metal layer (<NUM>); and
wherein the PCB (<NUM>) comprises:
an upper surface (4a) directly facing the lower surface (10b) of the base (<NUM>);
a plurality of thermal vias (<NUM>) within the PCB (<NUM>);
a heat spreading structure (<NUM>) mounted onto a lower surface (4b) of the PCB (<NUM>), wherein the heat spreading structure (<NUM>) is in thermal contact with the plurality of thermal vias (<NUM>);
characterized in that
the PCB (<NUM>) further comprises an array of conductive thermal pads (<NUM>) on the upper surface (4a) of the PCB (<NUM>);
wherein the plurality of thermal vias (<NUM>) is under the array of conductive thermal pads (<NUM>);
wherein the semiconductor package (<NUM>) is mounted on the array of conductive thermal pads (<NUM>);
wherein the solder paste (<NUM>) is in direct contact with the array of conductive thermal pads (<NUM>); and
wherein the array of conductive thermal pads (<NUM>) comprises slits (<NUM>) between the thermal pads (<NUM>) and the slits (<NUM>) are filled with the solder paste (<NUM>).