Patent Description:
A resolver, also referred to as a motor resolver, is an electrical transformer that measures angle of rotation. Resolvers are made up of a rotor and a stator. The rotor is mounted on a shaft of a device (e.g., motor, turbine engine, etc.) to be monitored, for example. The stator includes multiple transformers (also referred to as "windings"), for example, an input transformer and two output transformers. As an input signal (also referred to as a "reference" signal or an "excitation" signal) is applied to the input transformer, one of the output transformers generates a sine output and the other of the output transformers generates a cosine output.

In one exemplary embodiment, a method is provided. The method includes storing, in a first buffer associated with a first analog to digital converter (ADC) of a digital signal processor (DSP), resolver sine values collected from a first resolver, a second resolver, and a third resolver. The method further includes storing, in a second buffer associated with a second ADC of the DSP, resolver cosine values collected from the first resolver, the second resolver, and the third resolver. The method further includes storing, in a third buffer associated with a third ADC of the DSP, resolver excitation values collected from the first resolver, the second resolver, and the third resolver. The method further includes determining a midpoint value of the resolver excitation values. The method further includes determining a sine amplitude based at least in part on the resolver sine values and the midpoint value. The method further includes determining a cosine amplitude based at least in part on the resolver sine values and the midpoint value. The method further includes identifying a quadrant of a resolver position.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the method may include determining a quadrant position based at least in part on the quadrant.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the method may include that the resolver sine values, the resolver cosine values, and the resolver excitation values are collected simultaneously.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the method may include that the resolver sine values, the resolver cosine values, and the resolver excitation values are collected relative to a zero crossing.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the method may include that the resolver sine values, the resolver cosine values, and the resolver excitation values are collected relative to a zero crossing for a half period.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the method may include that identifying the quadrant of the resolver position includes doubling the sine amplitude and the cosine amplitude.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the method may include that identifying the quadrant is based on a sign of an excitation signal applied to the first resolver, the second resolver, and the third resolver.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the method may include that the first buffer is a first circular buffer, wherein the second buffer is a second circular buffer, and wherein the third buffer is a third circular buffer.

In another exemplary embodiment a digital signal processor (DSP) includes a first analog to digital converter (ADC) having a first buffer associated therewith, the first buffer storing resolver sine values collected from a first resolver, a second resolver, and a third resolver. The DSP further includes a second ADC having a second buffer associated therewith, the second buffer storing resolver cosine values collected from the first resolver, the second resolver, and the third resolver. The DSP further includes a third ADC having a third buffer associated therewith, the third buffer storing resolver excitation values collected from the first resolver, the second resolver, and the third resolver. The DSP further includes a first integrator to determine a sine amplitude based at least in part on the resolver sine values and a midpoint of a resolver excitation signal. The DSP further includes a second integrator to determine a cosine amplitude based at least in part on the resolver cosine values and the midpoint of the resolver excitation signal. The DSP further includes a quadrant identifier to identifies a quadrant of a resolver position based at least in part on the sine amplitude and the cosine amplitude.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the DSP may include an angle determining module to determine a quadrant position based at least in part on the quadrant.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the DSP may include that the resolver sine values, the resolver cosine values, and the resolver excitation values are collected simultaneously.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the DSP may include that the resolver sine values, the resolver cosine values, and the resolver excitation values are collected relative to a zero crossing.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the DSP may include that the resolver sine values, the resolver cosine values, and the resolver excitation values are collected relative to a zero crossing for a half period.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the DSP may include that identifying the quadrant of the resolver position includes doubling the sine amplitude and the cosine amplitude.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the DSP may include that the quadrant identifier identifies the quadrant based on a sign of an excitation signal applied to the first resolver, the second resolver, and the third resolver.

In addition to one or more of the features described herein, or as an alternative, further embodiments of the DSP may include that the first buffer is a first circular buffer, wherein the second buffer is a second circular buffer, and wherein the third buffer is a third circular buffer.

Other embodiments described herein implement features of the above-described method in computer systems and computer program products.

The above features and advantages, and other features and advantages, of the disclosure are readily apparent from the following detailed description when taken in connection with the accompanying drawings.

It will nevertheless be understood that no limitation of the scope of this disclosure is thereby intended. The following description is merely illustrative in nature and is not intended to limit the present disclosure, its application or uses. As used herein, the term controller refers to processing circuitry that may include an application specific integrated circuit (ASIC), an electronic circuit, an electronic processor (shared, dedicated, or group) and memory that executes one or more software or firmware programs, a combinational logic circuit, and/or other suitable interfaces and components that provide the described functionality.

Additionally, the term "exemplary" is used herein to mean "serving as an example, instance or illustration. " Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms "a plurality" are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term "connection" can include an indirect "connection" and a direct "connection.

Turning to an overview of technologies that are more specifically relevant to aspects of the present disclosure, a resolver or multiple resolvers can be used to measure rotation, such as of a motor, turbine engine, etc. In some cases, three resolvers may be used. Resolvers are excited with an excitation signal. The resolver provides three analog feedback signals, which take the form of sinusoids, as follows: the excitation signal, a sine signal, and a cosine signal. Demodulation of the resolver sine and cosine signals is utilized in many signal processing applications. In the demodulation of the resolver sine and cosine signals, a quadrant of the resolver position is determined based on the signs of the excitation, sine, and cosine signals. <FIG> show the resolver quadrants and the sign of the feedback signals in each quadrant. Particularly, <FIG> depicts a graphical representation <NUM> of resolver signals phase relationships across four quadrants. <FIG> depicts a graphical representation <NUM> of resolver signals phase relationships across four quadrants where the amplitude of the excitation signal is positive (i.e., greater than zero). <FIG> depicts a graphical representation <NUM> of resolver signals phase relationships across four quadrants where the amplitude of the excitation signal is negative (i.e., less than zero).

Many existing demodulation algorithms for determining a quadrant of the resolver position are time consuming, resource intensive, and/or inaccurate. Conventionally, the feedback signals are fed into the three separate analog to digital converters (ADCs), and the digitally converted data from the ADCs is fed into a digital signal processor (DSP). More particularly, resolver feedback signals sample data are collected into buffers, such as one buffer per resolver (e.g., three buffers for three resolvers): one for the excitation signal (ExcitationRAMBuffer), one for sine signal (SineRAMBuffer), and one for cosine signal (CosineRAMBuffer). These buffers are used to demodulate the feedback signals and determine the rotational position of the resolver. Once a required number of samples are collected, the resolver signal demodulation is performed using an integral demodulation algorithm. The integral demodulation is performed by integrating at least one full period of the sine and cosine feedback samples rectified about their respective midpoints and calculating the angular position using trigonometric relationships and the excitation reference to determine the quadrant of the angular position. This approach has several disadvantages. First, to determine a more accurate resolver position, each of the three feedback signals must be sampled simultaneously; however, conventional approaches acquire the three feedback signals using three different ADCs. This results in a phase delay of minimum one sample and hence produces less accurate results. Second, this approach uses more processing time/resources for the integral demodulation and quadrant determination because the resolver signals integration is done for the full period of the feedback signals and because each excitation sample is compared to identify the quadrant information.

One or more embodiments described herein address these and other shortcomings by implementing a DSP with internal ADCs for each of the three resolver feedback signals (e.g., excitation, sine, and cosine) simultaneously. <FIG> depicts an example of a digital signal processor <NUM> that includes three ADCs: ADC1 <NUM>, ADC2 <NUM>, and ADC3 <NUM>. In this example, each of the ADCs <NUM>-<NUM> receive respective cosine, sine, and excitation signals from resolvers <NUM>, which may represent multiple (e.g., three) resolvers. For example, the ADC1 <NUM> receives resolver cosine signals <NUM> from the resolvers <NUM> (e.g., resolver1 cosine, resolver2 cosine, and resolver3 cosine); the ADC2 <NUM> receives resolver sine signals <NUM> from the resolvers <NUM> (e.g., resolver1 sine, resolver2 sine, and resolver3 sine); and the ADC3 <NUM> receives resolver excitation signals <NUM> from the resolvers <NUM> (e.g., resolver1 excitation, resolver2 excitation, and resolver3 excitation). Each of the ADCs <NUM>-<NUM> includes an integral or associated buffer (e.g., a random access memory (RAM) buffer) for storing sample data from the feedback signals, and the DSP is capable of detecting zero crossings for the feedback signals. This is shown in <FIG>, which is now described.

Particularly, <FIG> depicts a flow diagram of a method <NUM> for determining resolver position according to one or more embodiments described herein. In <FIG>, each of the buffers are shown. Particularly, a cosine RAM buffer <NUM> (associated with the ADC1 <NUM>) stores resolver cosine sample data, a sine RAM buffer <NUM> (associated with the ADC2 <NUM>) stores resolver sine sample data, and an excitation RAM buffer <NUM> (associated with the ADC3 <NUM>) stores resolver excitation sample data.

Data from the cosine RAM buffer <NUM> is fed into a first integral demodulation and quadrant identification block <NUM> along with a sign of a midpoint of a sample from the excitation RAM buffer <NUM>. The first integral demodulation and quadrant identification block <NUM> determines and outputs a cosine amplitude into an angle calculation block <NUM>.

Similarly, data from the sine RAM buffer <NUM> is fed into a second integral demodulation and quadrant identification block <NUM> along with the sign of a midpoint of a sample from the excitation RAM buffer <NUM>. The second integral demodulation and quadrant identification block <NUM> determines and outputs a sine amplitude into the angle calculation block <NUM>.

More particularly, the first and second integral demodulation and quadrant identification blocks <NUM>, <NUM> respectively integrate half periods of the cosine and sine feedback samples. Once a threshold number of samples are collected, resolver signal demodulation is performed using an integral demodulation approach. Pseudcode of an example of such an integral demodulation approach is as follows:
<IMG>.

The angle calculation block <NUM> determines an angle of the device being evaluated (e.g., a shaft of a motor, turbine engine, etc.).

According to one or more embodiments described herein, the first and second integral demodulation and quadrant identification blocks <NUM>, <NUM> and/or the angle calculation block <NUM> can be implemented as instructions stored on a computer-readable storage medium, as hardware modules, as special-purpose hardware (e.g., application specific hardware, application specific integrated circuits (ASICs), application specific special processors (ASSPs), field programmable gate arrays (FPGAs), as embedded controllers, hardwired circuitry, etc.), or as some combination or combinations of these. According to aspects of the present disclosure, one or more of the components described herein can be a combination of hardware and programming. The programming can be processor executable instructions stored on a tangible memory, and the hardware can include the processing device for executing those instructions. Thus a system memory can store program instructions that when executed by the processing device implement the engines described herein. Other engines can also be utilized to include other features and functionality described in other examples herein.

<FIG> depicts a flow diagram of a method <NUM> for determining resolver position according to one or more embodiments described herein. In this example, the method <NUM> performs feedback sample data acquisition using zero crossing points and quadrant identification using the excitation signal.

Cosine ADC channel <NUM>, sine ADC channel <NUM>, and excitation ADC channel <NUM> feed buffers <NUM>, <NUM>, <NUM> respectively with sample data acquired from the feedback signals. In this example, the buffers <NUM>-<NUM> are circular buffers, although other types of buffers can be implemented. The sample data acquired by the excitation ADC channel <NUM> can also feed an excitation frequency measurement block <NUM> that outputs a frequency monitoring signal.

A first integration module <NUM> uses the zero crossing triggers from the excitation ADC channel <NUM> and sample data from the buffer <NUM> to determine a cosine amplitude. Similarly, a second integration module <NUM> uses the zero crossing triggers from the excitation ADC channel <NUM> and sample data from the buffer <NUM> to determine a sine amplitude.

A quadrant identification block <NUM> determines, based on the sine amplitude and the cosine amplitude, a quadrant of the resolver (see, e.g., <FIG>). An angle determination module <NUM> uses the identified quadrant to determine a resolver position.

According to one or more embodiments described herein, the excitation frequency measurement <NUM>, the integration module <NUM>, the integration module <NUM>, the quadrant identification <NUM>, and/or the angle calculation <NUM> can be implemented as instructions stored on a computer-readable storage medium, as hardware modules, as special-purpose hardware (e.g., application specific hardware, application specific integrated circuits (ASICs), application specific special processors (ASSPs), field programmable gate arrays (FPGAs), as embedded controllers, hardwired circuitry, etc.), or as some combination or combinations of these. According to aspects of the present disclosure, one or more of the components described herein can be a combination of hardware and programming. The programming can be processor executable instructions stored on a tangible memory, and the hardware can include the processing device for executing those instructions. Thus a system memory can store program instructions that when executed by the processing device implement the engines described herein. Other engines can also be utilized to include other features and functionality described in other examples herein.

<FIG> depicts a flow diagram of a method <NUM> for performing integral demodulation using a zero crossing point of the excitation signal according to one or more embodiments described herein. The method starts at block <NUM> and proceeds to decision block <NUM>, where it is determined (such as by the DSP <NUM> and/or one or more of the ADCs <NUM>-<NUM>) whether a zero crossing is detected. This determination repeats until a zero crossing is detected at which point the method <NUM> proceeds to blocks <NUM>, <NUM>, <NUM>. At block <NUM>, excitation signal samples are acquired, such as for a half period. At block <NUM>, sine signal samples are acquired, such as for a half period. At block <NUM>, cosine signal samples are acquired, such as for a half period. The method <NUM> proceeds to block <NUM>, where values for "index1," "sinesum," and "cosine sum" are set to zero.

The method <NUM> proceeds to decision block <NUM> where it is determined whether the excitation sample midpoint is positive (i.e., greater than zero). If it is determined at decision block <NUM> that the excitation sample midpoint is positive, the method <NUM> proceeds to decision block <NUM>, where it is determined whether the index (e.g., "index1" from block <NUM>) is less than a value n. If so, the method <NUM> proceeds to blocks <NUM> and <NUM>. At block <NUM>, a value Sinesum is set to a previous Sinesum value plus a sine sample for the current index. Similarly, at block <NUM>, a value Cosinesum is set to a previous Cosinesum value plus a cosine sample for the current index. After blocks <NUM>, <NUM>, the method <NUM> proceeds to block <NUM> where the index is incremented and the method <NUM> returns to decision block <NUM>.

Returning to the decision block <NUM>, if it is determined at decision block <NUM> that the excitation sample midpoint is not positive, the method <NUM> proceeds to decision block <NUM>, where it is determined whether the index (e.g., "index1" from block <NUM>) is less than a value n. If so, the method <NUM> proceeds to blocks <NUM> and <NUM>. At block <NUM>, a value Sinesum is set to the negative (opposite) of a quantity represented by a previous Sinesum value plus a sine sample for the current index. Similarly, at block <NUM>, a value Cosinesum is set to the negative (opposite) of a quantity represented by a previous Cosinesum value plus a cosine sample for the current index. After blocks <NUM>, <NUM>, the method <NUM> proceeds to block <NUM> where the index is incremented and the method <NUM> returns to decision block <NUM>.

If, at decision block <NUM> and/or if at decision block <NUM> it is determined that the index is not less than the value n, the method <NUM> proceeds to block <NUM> where the SineSum and CosineSum values are calculated, respectively, by doubling the previous SineSum and CosineSum values.

At block <NUM>, the position is determined using the SineSum and CosineSum values from block <NUM>. For example, the position is determined using the arctan of the SineSum and CosineSum values from block <NUM>. The method <NUM> then ends at block <NUM>.

Additional processes also may be included, and it should be understood that the process depicted in <FIG> represents an illustration, and that other processes may be added or existing processes may be removed, modified, or rearranged without departing from the scope of the present disclosure.

It is understood that one or more embodiments described herein is capable of being implemented in conjunction with any other type of computing environment now known or later developed.

One or more embodiments described herein provide improvements over conventional approaches for demodulation algorithms for determining a quadrant of the resolver position. For example, according to one or more embodiments described herein, the excitation signal is sinusoidal, which has three zero crossing points per full cycle; hence, the signal frequency can be calculated as the number of zero crossing points per second divided by three.

One or more embodiments described herein also provide improved accuracy. For example, in conventional approaches, because of the external ADC arrangement, each of the resolver signals (excitation, sine and cosine) are not sampled simultaneously. At least one sample delay is introduced between the samples and hence the sine to cosine ratio is not accurately represented. In contrast, one or more embodiments described herein sample the three resolver signals simultaneously using three ADCs that are in-built to processor (e.g., DSP). As the processors are running in Mhz frequency, the phase delay between the signals will only be the order of microseconds. Hence the sine to cosine ratio is accurately represented.

One or more embodiments described herein also provide improved processor (e.g., DSP) utilization. To calculate the amplitude, conventional approaches process samples for a full period of the signal which is time consuming. Also such approaches use each excitation sample to identify the quadrant of sine and cosine feedback signals. In contrast, one or more embodiments described herein collect samples from a zero crossing point such that samples only for a half period need to be integrated, and the integral output is multiplied by two to get the amplitude. Also the quadrant of the sine and cosine can be identified using only the sign of excitation signal that corresponds to the midpoint value of the excitation signal.

The present embodiments may be a system, a method, and/or a computer program product at any possible technical detail level of integration.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments.

Claim 1:
A method comprising:
storing, in a first buffer associated with a first analog to digital converter, ADC, of a digital signal processor, DSP, resolver sine values collected from a first resolver, a second resolver, and a third resolver;
storing, in a second buffer associated with a second ADC of the DSP, resolver cosine values collected from the first resolver, the second resolver, and the third resolver;
storing, in a third buffer associated with a third ADC of the DSP, resolver excitation values collected from the first resolver, the second resolver, and the third resolver;
determining a midpoint value of the resolver excitation values;
determining a sine amplitude based at least in part on the resolver sine values and the midpoint value;
determining a cosine amplitude based at least in part on the resolver cosine values and the midpoint value; and
identifying a quadrant of a resolver position.