Patent Description:
The controlled and successful manufacture of integrated circuits requires evaluations, including measurement, testing, reliability and predictability of various parameters and behavior in the manufactured devices. One particular parameter example is capacitance, including the capacitance of structures that are intended to be capacitors in the circuit function itself. Variations in capacitance may be affected or caused by manufacturing variations, temperature dependence, voltage dependence, device structure and other manufacturing parameters and operating conditions, both in a given structure and over a population of manufactured integrated circuits, including variations in capacitance among capacitors within a given integrated circuit.

Capacitance variations and capacitor mismatch have been addressed in the design of modem analog-to-digital converters. Examples of calibration and correction techniques are described in <CIT>, <CIT> and<CIT>, all three of which are commonly assigned herewith, and in<NPL>.

For purposes of calibration, trimming and process control, measurement of capacitor behavior is useful in manufactured devices, such as in wafer form along with functional and parametric electrical test. For such purposes, and for additional considerations such as circuit longevity, viability and operational limit determination, stress testing of circuit elements also may be useful.

<FIG> illustrates a conventional circuit for measuring mismatch between capacitors C<NUM> and C<NUM>, such as by evaluating the capacitance of one (or each) capacitor relative to the other. Capacitors C<NUM> and C<NUM> are connected in series between terminals V<NUM> and V<NUM>. In practice, capacitor C<NUM> may be a "reference" capacitor, against which the capacitance of capacitor C<NUM> is to be measured. A node VINT between capacitors C<NUM> and C<NUM> is connected to the gate of a p-channel metal oxide semiconductor (MOS) transistor <NUM>, the drain of which is at ground and the source of which is connected through a current source <NUM> to a bias voltage VDD. In this example, the body of transistor <NUM> is connected to its source.

In operation, current source <NUM> is biased to produce a constant current I<NUM>, and bias voltage VDD is sufficiently positive (relative to the ground voltage at the drain of transistor <NUM>) to place transistor <NUM> in saturation. Transistor <NUM> operates as a "source follower" under those conditions, because transistor <NUM> is in saturation, and the constant source-drain current I<NUM> forces the transistor gate-to-source voltage VGS to be constant. Accordingly, ideally output voltage VOUT (or VOUT(t) as designated over time) at the source of transistor <NUM> follows changes in the voltage at its gate, which is at node VINT.

To perform measurement of the relative capacitances of capacitors C<NUM> and C<NUM>, the voltage at node V<NUM> is held constant (e.g., at ground), and the voltage at node V<NUM> is ramped over time by increasing linearly from a starting voltage (e.g., ground) to a higher voltage. The voltage at intermediate node VINT will respond to the ramped voltage V<NUM> by also ramping, but at a flatter slope according to the voltage divider of capacitors C<NUM> and C<NUM>, as shown in: <MAT> Accordingly, Equation <NUM> defines the slope the expected increasing voltage at node VINT as <MAT>. Moreover, and also ideally, the slope of the output voltage VOUT from the source follower of transistor <NUM> increases with this same slope as the ramping voltage VINT(t), so the expected slope for the rise of VOUT is as shown in: <MAT>.

As a result of the preceding, in response to the ramped voltage at node V<NUM>, the voltage VOUT(t) may be measured and its slope determined, from which the capacitances of capacitors C<NUM> and C<NUM> can be determined according to: <MAT>.

From Equation <NUM>, if nominally the capacitances of capacitors C<NUM> and C<NUM> are equal, then ideally the ratio of Equation <NUM> will equal one. Or, if the nominal capacitances are accurate, then the ideal ratio thereof should be confirmed by Equation <NUM> and by evaluating the slope of VOUT(t). However, in practice, the behavior of the source follower circuit of <FIG> is not ideal, especially in modern sub-micron transistors. In the circuit of <FIG>, the drain-to-source voltage of transistor <NUM> changes as the voltage at node VINT (and VOUT at the transistor source) increases. This modulation of the drain-to-source voltage causes some of the changes in the gate voltage to be consumed in charging or discharging parasitic junction capacitances in the device. Furthermore, because of the mechanism of drain-induced barrier lowering, transistor threshold voltages modulate in response to changes in drain-to-body node voltage. These effects cause the slope of output voltage VOUT(t) to not solely reflect the relative capacitances of capacitors C<NUM> and C<NUM>, but the ratio also will reflect capacitive effects and also variations in the threshold voltage of transistor <NUM> over the duration of the measurement. The resulting output voltage VOUT(t) will thus include non-linearities, which can be substantial. The resulting inaccuracy in capacitance measurement is incompatible with capacitors such as those intended for certain precision circuits.

<CIT>, which is co-owned with this application, describes at least one example that also connects a node (existing between two series-connected capacitors) to a source follower transistor configuration, for purposes of testing for a mismatch in the capacitance value of the two capacitors. More specifically, a first ramping voltage source is applied across the two capacitors, while a second ramping voltage source (which increases at one half the rate of the first voltage source) is applied to the drain of the source follower. At the same time, the output of the source follower is monitored, which will provide a first slope proportional to a first of the two capacitors. The ratio of the first slope to the second slope may be evaluated to determine whether a match exists between the capacitance values of the two capacitors.

The documents <CIT>, <CIT> and <CIT> also disclose methods and circuits for measuring capacitors.

Capacitor reliability is an additional consideration in circuit design, use and establishing of operational specifications. Various models and testing have been used in view of these considerations, where certain such models are typically based on dielectric breakdown. Testing also is sometimes attempted, but accurate measurement of small capacitance shift under electrical stress is difficult, and very limited data is available on how capacitors degrade over time.

The present invention is directed to a method according to claim <NUM> and to a circuit according to claim <NUM>. Embodiments of the invention are described in the dependent claims.

<FIG> is a block diagram of a capacitor evaluation configuration <NUM>, which includes a capacitive network <NUM> and buffer <NUM> formed as part of an integrated circuit <NUM>, where integrated circuit <NUM> may represent any of various different devices and may include configuration <NUM> for purposes of design, testing and specification confirmation. Integrated circuit <NUM> is further connected in various ways to automated test equipment <NUM>, as may be achieved during circuit design or later at verification or operational testing. In an example embodiment, automated test equipment <NUM> may be embodied by internal circuitry within an integrated circuit (e.g., apart or including integrated circuit <NUM>), or laboratory bench equipment similarly may interface with integrated circuit <NUM>. Also, in an example embodiment, capacitive network <NUM> includes at least three capacitors C<NUM>, C<NUM> and C<NUM>, each with a same nominal capacitance (although differing values could be used, given the teachings with respect to ratios and other aspects of this document). Each of these capacitors has a first terminal coupled to a mutual intermediate node VINT, and node VINT is also connected as an input to buffer <NUM>. Buffer <NUM> provides an output terminal VOUT, which is coupled to and monitored by automated test equipment <NUM>. Automated test equipment <NUM> also has respective connections to the second terminal of each of capacitors C<NUM>, C<NUM> and C<NUM>, and for ease of reference each such second terminal is referred to herein as an input by receiving a respective voltage V<NUM>, V<NUM> and V<NUM> from automated test equipment <NUM>. For example, capacitor C<NUM> has one terminal connected to VINT and an opposing terminal V<NUM> receiving that voltage from automated test equipment <NUM>. Similarly, capacitor C<NUM> has an input terminal/voltage V<NUM>, and capacitor C<NUM> has an input terminal/voltage V<NUM>. Also, terminals V<NUM>, V<NUM>, V<NUM> and VOUT may be realized by test pads for coupling to equipment <NUM>.

<FIG> is a flowchart of an example method <NUM> of operation of evaluation configuration <NUM> of <FIG>. The method <NUM> permits automated test equipment <NUM> to control the electrical configuration of capacitors in capacitive network <NUM>, to selectively bias them in alternative ways, and to test the resultant voltage and effects of the configurations and biases. More particularly, such parameters are evaluated at node VINT, which is isolated by buffer <NUM> to reduce effects of the testing equipment during such evaluations, so the parameters are also comparably testable via terminal VOUT, while reducing the effects of the testing on the voltage that appears at node VINT.

According to method <NUM>, a first process <NUM> measures the nominal capacitance (relative) of each of capacitors C<NUM>, C<NUM> and C<NUM> or certain types of tunnel-FETs. As discussed below in connection with <FIG>, in one example, process <NUM> is performed by pairing two of the three capacitors in capacitive network <NUM> at a time and measuring the capacitance of each capacitor in such a pair under a nominal voltage, and then repeating until all capacitors are at least one time measured. Next, a second process <NUM> applies a stress voltage, in excess of the nominal voltage, to at least one capacitor in capacitive network <NUM>. For example, the nominal voltage of process <NUM> may be a part/device/circuit specified value for which a certain percentage of yield is expected (e.g., an operational specification), while the stress voltage of process <NUM> is some greater percentage (e.g., one hundred percent) more than the nominal voltage. Accordingly, the process <NUM> stress voltage is intended to "stress" the limits of design and operation of the stressed capacitor. The method <NUM> concludes with a third process <NUM>, where observations and analyses occur with respect to the voltage increase across the one stressed capacitor from process <NUM>, such as an additional nominal measurement of its capacitance. Also, other parameters associated with the stressed capacitor from process <NUM> may be evaluated. In any event, with the repeated nominal evaluation of process <NUM>, an example embodiment evaluates and observes any change in parameter behavior of the stressed capacitor as compared to the comparable parameter from process <NUM>. Any such change may evidence or suggest optional additional testing, to determine any failure of the stressed capacitor. For example, the capacitance of the stressed capacitor may increase or decrease. As another example, the stressed capacitor may develop a decreased resistance through its dielectric, such as manifested by leakage across the capacitor after it has been stressed.

<FIG> illustrates the evaluation configuration <NUM> of <FIG>, with additional schematic details for buffer <NUM>. In the example embodiment of <FIG>, buffer <NUM> includes devices and connections from the above-cited <CIT>. In this example, the devices and connections include a p-channel MOS transistor <NUM>, having its gate connected to intermediate node VINT. The drain of transistor <NUM> is connected to a reference voltage terminal VR, and the source of transistor <NUM> is connected to terminal VOUT and connected through a current source <NUM> to a power supply voltage VDD. The body node of transistor <NUM> is connected to its source node, or alternatively to a substrate connection if desired. Current source <NUM> is a conventional current source device, such as a MOS transistor biased by a reference voltage to conduct a substantially constant current; a current mirror or other circuit for providing a substantially constant current also may be used. While not shown in the above-discussed <FIG>, <FIG> also provides a connection of automated test equipment <NUM> to buffer <NUM> (e.g., to reference terminal VR) to facilitate the buffering effect.

Transistor <NUM> alternatively may be realized as an n-channel MOS transistor, in which case output terminal VOUT would be connected to the source of that n-channel device.

In operation of buffer <NUM>, transistor <NUM> is biased into its saturation region and operates as a source follower device by virtue of current source <NUM> providing a substantially constant source-drain current I<NUM>. This constant source-drain current I<NUM> causes transistor <NUM> to have a constant gate-to-source voltage. Changes in the voltage at the gate of transistor <NUM> (presented at intermediate node VINT) are thus reflected directly at output terminal VOUT. The precision with which the voltage at output terminal VOUT tracks the voltage at intermediate node VINT is better than the approach of <FIG> and depends on the operation of current source <NUM> to provide constant current I<NUM>. Accordingly, for purposes of this description, the "substantially constant" current I<NUM> to be provided by current source <NUM> refers to a current that is sufficiently constant to meet the desired precision of the capacitance testing and evaluation described herein.

<FIG> illustrate the application of various voltages by automated test equipment <NUM> to capacitive network <NUM> of <FIG>, although the dotted rectangle and designation of <NUM> are removed in these latter Figures to simplify the illustration and discussion. Moreover, <FIG>, <FIG> and <FIG> further elaborate on processes <NUM>, <NUM> and <NUM>, respectively, of <FIG>, and correspond to various illustrations of FIGS. 5a through 5f.

<FIG> illustrates process <NUM> from <FIG> in more detail, and starts with a step <NUM> in which two of the three capacitors in capacitive network <NUM> are selected by equipment <NUM>. This capacitor selection may be achieved by establishing the connection of <FIG>, where the selected capacitors in that example are C<NUM> and C<NUM>. Accordingly, in this example, capacitor C<NUM> is allowed to float (or, alternatively, its terminal V<NUM> could be connected to the reference voltage, VR).

Next in <FIG>, step <NUM> measures the capacitance of the two capacitors selected in step <NUM>, either in absolute or relative manner, using equipment <NUM> and at a nominal voltage range. An example of this step is shown in <FIG>, and the operation associated with <FIG> is similar to the two-capacitor configuration and operation in <CIT>. More particularly, terminal V<NUM> is biased to a reference voltage such as ground (shown in <FIG> as <NUM> volts), and power supply voltage VDD is applied to current source <NUM>. Meanwhile, measurement of the relative capacitances of capacitors C<NUM> and C<NUM> is performed by automated test equipment <NUM> ramping the voltage applied to bias terminal V<NUM> at a selected time rate of change, beginning from a low voltage (such as that applied to terminal V<NUM>) and increasing to a nominal voltage (shown in <FIG> as <NUM> volts). Simultaneously, and over the same period of the ramped voltage at terminal V<NUM>, automated test equipment <NUM> applies a ramping voltage to bias reference terminal VR, also beginning from a low voltage such as ground. The time rate of change of the voltage applied to terminal VR relative to that of the voltage applied to terminal V<NUM> is selected to maintain a substantially constant drain-to-source voltage drop across transistor <NUM>, preferably by ramping the voltage at terminal VR to equal the expected voltage increase at node VINT, shown in step <NUM> as E{VINT}. Assuming that capacitors C<NUM> and C<NUM> are expected to have an equal nominal capacitance, then they should equally divide the ramping <NUM> to <NUM> volts being applied to terminal V<NUM>, thereby causing the voltage at node VINT (i.e., across capacitor C<NUM>) to ramp from <NUM> to <NUM> volts; thus, the ramping voltage at terminal VR (as applied by equipment <NUM>) is also preferably applied to ramp from <NUM> to <NUM> volts, at the same time that the voltage applied to V<NUM> ramps from <NUM> to <NUM> volts (i.e., at the same time the voltage divided to VINT is expected, based on the equal capacitance of C<NUM> and C<NUM>, to ramp from <NUM> to <NUM> volts).

Looking at the preceding operation in additional detail, the nominal capacitor voltage divider ratio CP (presented by capacitors C<NUM> and C<NUM>) is determined (preferably a priori), such as from the circuit design or as based on actual measurements of dielectric properties and feature sizes for the lot or wafer of the instance of evaluation configuration <NUM>. The voltage divider ratio CP determines the rate the voltage at intermediate node VINT will ramp relative to the ramping of the applied voltage at terminal V<NUM>. Particularly, and according to circuit analysis, the voltage at intermediate node VINT between capacitors C<NUM> and C<NUM> can be derived as shown in: <MAT> where V<NUM>(t) is the time-dependent (i.e., ramping) voltage at terminal V<NUM>, VINT(t) is the time-dependent voltage at intermediate node VINT, and C<NUM> and C<NUM> are the nominal capacitances values of the respective capacitors. Accordingly, the capacitor voltage divider ratio CP can be readily derived from the nominal capacitances C<NUM> and C<NUM>, as shown in: <MAT> From Equation <NUM>, when (as in the example embodiment) the capacitors C<NUM> and C<NUM> (or C<NUM>, discussed below) have the same capacitance, then the voltage divider ratio CP is readily calculable per Equation <NUM>, as shown in: <MAT> Thus, Equation <NUM> confirms that, for equal value capacitors, the voltage divider ratio is anticipated to be one half. Accordingly, for a ramping voltage range applied across the series connection of those capacitors, the voltage divided to the intermediate node (VINT) between them should be one half of the range.

Further, the reference voltage applied to terminal VR (by equipment <NUM>) is selected to match, in value and time, the voltage expected to occur at VINT. After the time rate of change (i.e., slope) of the voltage to be applied to terminal V<NUM> is selected or otherwise identified, the time rate of change (i.e., slope) of the voltage to be applied to terminal VR is then determined as the product of voltage divider ratio CP and the slope of the voltage ramp at terminal V<NUM>.

The effects of the above aspects are further discussed in connection with the example of <FIG> and the plot in <FIG>, where <FIG> shows time across its horizontal axis and voltage across its vertical axis. As described above, the voltage divider ratio CP corresponds to the fraction of the voltage at terminal V<NUM> that appears at intermediate node VINT. Accordingly, if the slope over time of the voltage at terminal V<NUM> is S, then the slope of the voltage at intermediate terminal VINT will correspond to the product of the voltage divider ratio CP and the slope S. And, in the example embodiment, the example CP=½ (see Equation <NUM>). Thus, the voltage expected at VINT will be ½(V<NUM>), and (as mentioned above) this voltage is therefore applied to terminal VR. Therefore, the voltage at reference terminal VR is ramped by automated test equipment <NUM> at the same rate of change as expected of the voltage at terminal VINT. Accordingly, in the example of <FIG>, the capacitor input voltage applied by equipment <NUM> to terminal V<NUM> ramps over a period of time from <NUM> to <NUM> volts, and the voltage applied by equipment <NUM> to reference terminal VR ramps from <NUM> to <NUM> volts over that same period. Both of these signals are also shown in the plot of <FIG>.

As described above, transistor <NUM> operates as a source follower, given that a constant source-drain current is being supplied by current source <NUM>. With transistor <NUM> in its saturation region, which occurs upon application of a sufficiently high supply voltage VDD, the gate-to-source voltage of transistor <NUM> will remain constant. As the voltage at intermediate node VINT increases over time as the voltage at terminal V<NUM> is ramped, the output voltage at terminal VOUT increases over time. And because the voltage at terminal VR at the drain of transistor <NUM> is ramping at the same rate as the expected voltage at intermediate node VINT, the drain-to-source voltage of transistor <NUM> will remain constant. Thus, the voltages at terminals V<NUM> and VR are simultaneously ramped by equipment <NUM>, during which time the voltage at terminal VOUT is measured. Thus, ramping of the applied voltage at terminal VR simultaneously with the voltage at terminal V<NUM> (VR at the reduced slope relative to V<NUM> corresponding to voltage divider ratio CP) causes the drain-to-source voltage of transistor <NUM> to remain substantially constant, even as the source voltage (at terminal VOUT) rises with the rising voltage at intermediate node VINT. By maintaining both the drain-to-source voltage and the gate-to-source voltage constant, the parasitic capacitances presented by transistor <NUM> to intermediate node VINT remain constant over the applied voltage range, thereby accomplishing the intended isolating or buffering effect of buffer <NUM>. Accordingly, the resulting source voltage at terminal VOUT, as shown in the plot of <FIG>, is thus not non-linearly affected by the charging and discharging of these device parasitic capacitance. Also, shifting of the threshold voltage of transistor <NUM> due to drain effects is greatly reduced. Consequently, the following measurement of capacitive match (or mismatch) is more precise as compared to other techniques.

The slope of time-dependent voltage VOUT(t) in response to the ramped voltage at terminal V<NUM> is used by equipment <NUM> to determine the relative capacitances of C<NUM> and C<NUM> as shown in: <MAT> In operation, automated test equipment <NUM> (or other alternative circuitry or methodology) determines the slope S of the measured output voltage VOUT(t). From that slope S, equipment <NUM> solves for the relative ratio of capacitances C<NUM>/C<NUM>. To the extent that this ratio deviates from that expected based on the nominal capacitances C<NUM> and C<NUM>, such deviation will correspond to the capacitive mismatch between capacitors C<NUM> and C<NUM>. For example, in this embodiment where C<NUM>=C<NUM>, the expected slope would be is readily calculable per Equation <NUM>, as shown in: <MAT> From Equation <NUM>, when C<NUM>=C<NUM>, the expected slope S of the output voltage VOUT(t) would be ½, and a capacitive mismatch is detected between capacitors C<NUM> and C<NUM> (i.e., with respect to capacitance, C<NUM>≠C<NUM>) to the extent that the measured slope differs from ½.

<FIG> illustrates an additional or alternative nominal measurement, where the capacitor input voltages are reversed for terminals V<NUM> and V<NUM>. Accordingly, equipment <NUM> applies <NUM> volts to terminal V<NUM> and the ramping voltage of <NUM> to <NUM> volts to terminal V<NUM>. The aspects described above will again apply to <FIG>, with VINT here representing (relative to ground) the voltage across C<NUM>. If the configuration of <FIG> is conducted in addition to that of <FIG>, then the final value at VOUT should be the same for both configurations, thereby confirming that C<NUM>=C<NUM>. If the values of VOUT differ for each, then a mismatch exists between those capacitance values, as again may be determined from the slope of VOUT for either configuration.

Returning to <FIG>, and having extensively detailed its step <NUM> in connection with the illustrations of <FIG>, a next step <NUM> may cause additional iterations to be made, preferably for all different pairings of potential capacitors in capacitive network <NUM>. For example, with <FIG> having paired capacitors C<NUM> and C<NUM>, step <NUM> will determine that not all capacitors in the network (e.g., having three capacitors) have been paired, in which case method <NUM> repeats steps <NUM> and <NUM>, with respect to another pair of capacitors. <FIG> illustrates the pairing by equipment <NUM> of capacitors C<NUM> and C<NUM>, with capacitor C<NUM> floating. Again, one capacitor (e.g., C<NUM>) receives a fixed terminal voltage, while during a period of time the other in the pair (e.g., C<NUM>) receives a ramped voltage, while during the same period reference VR is ramped at E{VINT}. Moreover, equipment <NUM> monitors VOUT(t) during this time and determines its slope S, from which a determination is made whether that slope represents the expected relative ratio of capacitances C<NUM>/C<NUM>. To the extent (if any) that this ratio deviates from that expected based on the nominal capacitances C<NUM> and C<NUM>, such deviation will correspond to the capacitive mismatch between capacitors C<NUM> and C<NUM>. The above steps also may be repeated with respect to capacitors C<NUM> and C<NUM>.

Completing <FIG>, after evaluating each pair of capacitors in network <NUM> as described above, step <NUM> determines that no other capacitors require such evaluation, and process <NUM> completes. As shown in <FIG>, after process <NUM> completes, a next process <NUM> is undertaken.

<FIG> illustrates additional steps in connection with the capacitor stress process <NUM> of <FIG>, as further discussed in connection with <FIG>. In step <NUM>, equipment <NUM> configures capacitors in network <NUM>, so that a capacitor to be stress tested has a lesser amount of capacitance than the combined (or equivalent) capacitance of other capacitors that will be included in the stress testing. For example, in <FIG>, assume capacitor C<NUM> is to be stress tested; accordingly, step <NUM> configures two other capacitors in network <NUM>, which in this example includes only two other capacitors C<NUM> and C<NUM>, so that the capacitance of these two configured capacitors collectively exceeds the to-be stressed capacitor C<NUM>. In an example embodiment, this relative capacitance is achieved by connecting the configured capacitors C<NUM> and C<NUM> in parallel, which is electrically achieved by connecting a same potential to their respective terminals V<NUM> and V<NUM>. Thus, in <FIG>, a common voltage of <NUM> volts is shown connected by equipment <NUM> to terminals V<NUM> and V<NUM>. Also, equipment <NUM> may include switching circuitry (not expressly shown) to connect terminals V<NUM> and V<NUM> directly to one another, while applying a common voltage to that connection, or each terminal may individually receive the mutual voltage level.

Next, in process <NUM>, step <NUM> applies a ramped voltage level across capacitors, including the to-be stressed capacitor, where the voltage range is selected to nominally bias the stressed capacitor beyond its nominal value. In this example, capacitor C<NUM> was nominally biased to <NUM> volts described above. Thus, in the example embodiment, and for purposes of stressing that capacitor, step <NUM> causes a bias greater than <NUM> volts. In one embodiment, the increased bias is achieved by the change in capacitance by configuring C<NUM> and C<NUM> as a parallel capacitance in series with C<NUM>. Accordingly, C<NUM> will necessarily drop additional voltage in this changed configuration. Moreover, the stressed voltage can be further increased by increasing the ramping voltage applied to V<NUM> (e.g., greater than that used in step <NUM> of process <NUM>). For example, in <FIG>, a nominal voltage range of <NUM> to <NUM> volts was applied to terminal V<NUM> of capacitor C<NUM>, resulting in a nominal bias across it of <NUM> volts. In contrast, in <FIG> an increased (i.e., stressing) voltage range of <NUM> to <NUM> volts is applied to terminal V<NUM> of capacitor C<NUM>, which will drop approximately <NUM> volts across capacitor C<NUM>, to place it in a stressed condition.

Step <NUM>, consistent in part with the preceding discussion of buffer <NUM>, also applies a second ramped voltage to terminal VR. However, step <NUM> differs from the earlier step <NUM> by taking into account that the configuration of <FIG> no longer has solely two equal capacitors in series. More specifically (e.g., referring to <FIG>), the resultant capacitive network is C<NUM> connected in series with the parallel connection of C<NUM> and C<NUM>. Thus, a voltage divider is thereby created, and the voltage drop across a series capacitance in the divider is inversely proportional to the total capacitance value of the divider. As a result, the voltage ramp of node VINT (i.e., the voltage across capacitor C<NUM> and the parallel C<NUM>) is as shown in: <MAT> Moreover, because all three capacitance values are nominally equal (and were confirmed in process <NUM>) in this example, the expected voltage VINT will rise to <NUM> volts, after the voltage to terminal V<NUM> reaches its maximum of <NUM> volts, as shown in: <MAT> With the expectation that VINT will ramp from <NUM> to <NUM> volts during the same period that V<NUM> ramps from <NUM> to <NUM> volts, equipment <NUM> likewise ramps the reference voltage VR from <NUM> to <NUM> volts (i.e., to E{VINT}). If the earlier steps determine a mismatch in any of capacitors C<NUM>, C<NUM> and C<NUM>, then adjustments can be made, given the teachings herein, to adjust the ramping of VR accordingly.

Continuing with the example of <FIG>, if the biasing of terminals V<NUM> and VR cause node VINT to ramp from <NUM> to <NUM> volts, then the remainder of the voltage is across the divider. Accordingly, the voltage across the stressed capacitor C<NUM> will ramp to a total of <NUM> volts. Thus, whereas capacitor C<NUM> dropped <NUM> volts during nominal measurement process <NUM>, stress process <NUM> (and step <NUM> thereof) doubles that drop voltage to <NUM> volts, thereby stressing the capacitor to twice its nominal bias. While the example demonstrates a stress of a <NUM>% increase in bias, other values (greater than the nominal bias value) could be implemented.

<FIG> illustrates additional steps in connection with the observation and analyses of process <NUM> of <FIG>, as further discussed in connection with the configuration of <FIG> and the plots of <FIG>.

In step <NUM>, equipment <NUM> monitors VOUT(t) as the ramped capacitor input voltage is applied (e.g., to terminal V<NUM>) and the ramped reference voltage is applied to terminal VR. Generally, and without any catastrophic failure of the post-stressed capacitor (e.g., C<NUM>), the signals will take the form shown in <FIG>, which (like <FIG>) shows time across its horizontal axis and voltage across its vertical axis. Therefore, <FIG> confirms various aspects of the discussion above. For example, during a same time period, V<NUM> ramps from <NUM> to <NUM> volts, while both VR and VINT ramp from <NUM> to approximately <NUM> volts. Moreover, because both the gate-to-source and source-to-drain potentials are held relatively constant due to the ramp at VR tracking the ramp at VINT, VOUT has approximately the same slope as VINT (and VR), but is higher by approximately <NUM> volts due to the threshold voltage of transistor <NUM>. In all events, any significant departure (either in slope or amplitude) from the expected VOUT of <FIG> could indicate a catastrophic failure of the stressed capacitor.

In step <NUM>, equipment <NUM> repeats the nominal measure discussed earlier in connection with step <NUM> of <FIG>, but the step <NUM> is taken with respect to the now post-stressed capacitor, which is the capacitor that was stressed by process <NUM> (and step <NUM> thereof). For example, refer to the earlier discussion and <FIG>. However, in an example embodiment, the nominal measure is taken twice, applying the nominal capacitor input voltage (e.g., <NUM> to <NUM> volts) in a first instance to the stressed capacitor (to C<NUM>, through terminal V<NUM>, as shown in <FIG>) to produce a corresponding output indicated herein as VOUT1, and in a second instance by applying it to the non-stressed capacitor (e.g., to C<NUM>, through terminal V<NUM>) to produce a corresponding output indicated herein as VOUT2. Both VOUT1 for the resultant voltage across the non-stressed capacitor and VOUT1 for the resultant voltage across the post-stressed capacitor are shown by example in the plot of <FIG>.

In step <NUM>, equipment <NUM> compares the slope of VOUT1 and VOUT2, as may be appreciated again by the example plot in <FIG>. Therefore, if the post-stressed capacitor has had a change in its operational parameters due to the stress process <NUM>, its slope should differ from that measured in the earlier nominal process <NUM>. Moreover, assuming that the post-stressed and non-stressed capacitors originally had the same capacitance before the stress process <NUM>, then the slopes of VOUT1 and VOUT2 should be substantially the same if no change occurred in the post-stressed capacitor. However, in the plot of <FIG>, the slopes of VOUT1 and VOUT2 diverge, particularly as the input voltage (V<NUM> or V<NUM>) increases. This difference, or delta, is evaluated by equipment <NUM>, as shown by the example plot in <FIG>. A greater delta indicates a greater change in the post-stressed capacitor, as resulting from the stress process <NUM>.

In step <NUM>, equipment <NUM> determines whether the post-stressed capacitor parameters evaluated in any of steps <NUM> through <NUM> fall within expected ranges. Such ranges may be established, given various considerations including the parameter(s) tested, design specification, process variation, capacitor sizing and type. For example, equipment <NUM> may compare the delta of <FIG> to some threshold, so a delta below the threshold indicates no or little device failure, while a delta above the threshold indicates a failure, such as an increase or decrease in capacitance value as a result of the stress, or the formation of leakage resistance in the capacitor. Other parameters likewise may be considered. If all parameters are within expectation, method <NUM> may complete.

In step <NUM>, if one or more parameters are outside of expectation (e.g., beyond a threshold), method <NUM> may continue to a step <NUM> for additional testing. In one example embodiment, an additional such test repeats the nominal measure for the post-stressed capacitor (e.g., with the terminal for the post-stressed capacitor (e.g., V<NUM>) set to <NUM> volts, and the terminal of the non stressed capacitor (e.g., V<NUM>) ramping from <NUM> to <NUM> volts), to evaluate the voltage dropped across the post-stressed capacitor. However, step <NUM> further changes the ramping reference voltage VR to a lesser value than used in step <NUM>, where the reduction may be in an amount X, as shown in step <NUM>. Thus, where step <NUM> applies (to terminal VR) a range starting from <NUM> volts up to E{VINT}, step <NUM> applies VR in a range starting from <NUM>-X volts up to E{VINT}-X. As a result, the highest voltage applied to terminal VR in the step <NUM> repeated nominal measure should be less (i.e., X less) than the expected value that intermediate node VINT will reach. For example, <FIG> illustrates this step, where X=<NUM>, so instead of equipment <NUM> ramping VR from <NUM> to <NUM> volts as described above (in connection with <FIG>), it ramps terminal VR from -<NUM> to <NUM> volts. The basis for applying this lower ramping reference voltage VR is further discussed below.

In step <NUM>, equipment <NUM> determines whether VOUT changes, or changes beyond some threshold, as between the step <NUM> nominal measure using VR= E{VINT} and the step <NUM> nominal measure using VR= E{VINT}-X. If such a change in VOUT does not occur, method <NUM> continues to step <NUM>, which concludes that the change in VOUT slope of the post-stressed capacitor (detected in step <NUM>), as compared to its value before stress, is primarily a change that has occurred in capacitance of the stressed capacitor. In contrast, if such a change in VOUT does occur, method <NUM> continues to step <NUM>, which concludes that the change in VOUT slope of the post-stressed capacitor as compared to its value before stress, is primarily a change that has occurred in resistance of the stressed capacitor. The basis for the alternative determinations of steps <NUM> and <NUM> is further discussed below.

The conclusions in steps <NUM> and <NUM> are understood with reference to an additional discussion of <FIG>, given the values of V<NUM>(t) and VR in that Figure. Specifically, as V<NUM> and VR both ramp upward, if the post-stressed capacitor C<NUM> is relatively unaffected by the stress process <NUM>, then the expectation is: as V<NUM> reaches its top <NUM> volts, <NUM> volts are dropped across C<NUM>, so VINT will be at approximately <NUM> volts, and VOUT will therefore be at least <NUM> volts, if not up to one threshold voltage (e.g., in this example <NUM> volts) higher than the voltage dropped across C<NUM>. However, if stress process <NUM> causes a sufficient resistive leak to be formed in capacitor C<NUM> (e.g., tunnel resistance), then after V<NUM> reaches its top <NUM> volts, the resistive leak through capacitor C<NUM> provides a leakage path to ground, so VINT will drop from <NUM> volts, and VOUT will drop correspondingly. However, in this case, because transistor <NUM> is in saturation mode, then VOUT cannot fall below the top voltage of VR, namely <NUM> volts in this example. In any event, with the leakage resistance, the value of VOUT will (over time) drop toward the upper value of VR. Accordingly, a change in VOUT of this level, as detected by step <NUM> which compares VOUT of steps <NUM> and <NUM>, causes method <NUM> to continue to step <NUM>, concluding that the dominant change in the stressed capacitor is due to a resistance change. For example, <FIG> illustrate a plot of the various voltage signals for what might be expected from resistive changes in a stressed capacitor, as indicated by the nominal test from step <NUM> of that circuit, where the time illustrated (or the duration of the imposed stress) is shorter in <FIG> than in <FIG>. Therefore, in <FIG>, VINT fails to rise to the expected level of <NUM> volts, which in <FIG> is further shown as a brief rise to approximately <NUM> volts followed by a drop-off to <NUM> volts. This failure of VINT to rise to <NUM> volts is further reflected and observable in the fact that VOUT fails to rise to the expected value of approximately <NUM> volts. Thus, the additional testing per step <NUM> and analyses of steps <NUM> and <NUM> may identify this drop in VINT, as evident from the low value of VOUT, as a post-stress resistive change in the capacitor. On the other hand, if step <NUM> determines the VOUT of steps <NUM> and <NUM> are comparable to one another, such as within a threshold voltage of transistor <NUM> difference, then method <NUM> continues to step <NUM> to conclude that the dominant change in the stressed capacitor is due to a capacitance change.

Accordingly, various embodiments provide improvements to integrated circuit capacitor testing and measurement. Example embodiments may be applied to analyze various capacitor types, such as metal or junction or gate capacitors, but additional practical factors may be considered in determining the efficacy of example embodiment for certain capacitors, such as capacitors that are not well-matched or that have voltage variances (which could make the analysis either unrealistic or less useful). Example embodiments also may be used for comparing capacitors against each other.

Claim 1:
A method of evaluating at least one parameter of a first capacitor (C<NUM>), the method comprising:
coupling a number of capacitors in a capacitor network (<NUM>) to a common node, the number of capacitors comprising at least three capacitors (C<NUM>, C<NUM>, C<NUM>);
coupling an input of a buffer (<NUM>) to the common node, wherein the buffer (<NUM>) comprises a transistor (<NUM>) in a source follower configuration and wherein the buffer has an output first,
applying a first voltage range to the capacitor network for causing a first voltage drop across the first capacitor;
while applying the first voltage range, applying a first reference voltage range to the drain of the transistor, wherein the first reference range approximates an expected voltage increase at the common node; and
evaluating the at least one parameter in response to the first voltage range; second,
applying a second voltage range to the capacitor network for causing a second voltage drop across the first capacitor, the second voltage drop greater than the first voltage drop;
while applying the second voltage range, applying a second reference voltage range to a drain of the transistor, wherein the second reference range approximates an expected voltage increase at the common node; and
evaluating the at least one parameter in response to the second voltage range at the output of said buffer; and third,
while applying a third reference voltage range to a drain of the transistor, the third reference voltage range reduced relative to the second reference voltage range, re-applying the first voltage range to the capacitor network for causing the first voltage drop across the first capacitor; and
evaluating the at least one parameter in response to the re-applied first voltage range at the output of said buffer.