Patent Description:
The disclosure relates to the technical field of semiconductors, in particular, to a semiconductor structure and a method for forming the semiconductor structure.

Semiconductor devices have been widely used in integrated circuits. For example, dynamic random access memories are a type of semiconductor memories widely used in the integrated circuits. With a continuous decrease of characteristic sizes of semiconductor integrated circuit devices, semiconductor devices are also constantly developing towards a high integration density, and therefore, more severe challenges are presented to the semiconductor forming technology.

With a continuous increase of the integration density of the semiconductor devices, the semiconductor devices may generate leakage current, which will affect storage performance thereof.

Thus, how to effectively reduce the leakage current and improve the storage performance of the semiconductor devices is a technical problem urgent to be solved currently.

Document <CIT> discloses a semiconductor structure and a method for forming the same. The semiconductor structure includes a substrate and at least a gate trench extending along a first direction formed in the substrate. A gate dielectric layer is formed conformally covering the gate trench. A gate metal is formed on the gate dielectric layer and filling the gate trench. A plurality of intervening structures are arranged along the first direction in a lower portion of the gate trench and disposed between the gate metal and the gate dielectric layer.

Document <CIT> discloses the utility model relates to the technical field of memories, and relates to a semiconductor structure and a semiconductor memory. The semiconductor structure comprises a substrate, an isolation structure, a word line trench and a word line, the isolation structure is formed in the substrate, and a plurality of active regions are defined in the substrate; wherein the word line groove is formed in the substrate and the isolation structure; a word line is arranged in the word line groove, and the word line penetrates through the active region and the isolation structure; wherein in the depth direction of the word line groove, the height of the word line located on the active region is larger than the height of at least part of the word line located on the isolation structure. According to the semiconductor structure provided by the utility model, the influence of the word line of the active isolation region on the electrical property of the storage transistor of the adjacent active region in a working state can be reduced, and the leakage current is reduced.

The technical problem to be solved by the disclosure is to provide a method for forming the semiconductor structure, which can reduce the leakage current of the semiconductor structure and improve the storage performance of a semiconductor device.

The present disclosure has the advantages that for the semiconductor structure formed by the method for forming a semiconductor structure of the present disclosure, if a thickness of each shallow trench isolation area between the respective second word line and the respective adjacent active area is large enough, when the second word lines are powered to work, an inversion layer, on the active areas, induced by the second word lines has a small or no thickness, which is not enough to form a parasitic transistor structure, so that there is no leakage current generated, and the storage performance of the semiconductor device is greatly improved.

In order to describe the technical solutions of the embodiments in the disclosure more clearly, reference will now be made to the accompanying drawings required for the embodiments of the disclosure. It is apparent that the accompanying drawings in the following descriptions are only some embodiments of the disclosure. Other drawings may be obtained by those ordinary skilled in the art according to these accompanying drawings without involving any inventive work.

In order to make the objectives, technical manners, and effects of the disclosure clearer, the disclosure will be described further below in conjunction with the accompany drawings. It should to be understood that the embodiments described here are only part of the embodiments of the disclosure, not all of the embodiments, and not intended to limit the disclosure. All other embodiments obtained by those skilled in the art on the basis of the embodiments of the disclosure without involving any inventive work shall fall within the disclosure.

With a continuous increase of an integration density of a semiconductor device, the semiconductor device may generate leakage current. Through research, the applicant found that a cause of the leakage current is that a parasitic transistor structure is formed in a semiconductor structure. The parasitic transistor structure may generate the leakage current in the semiconductor device.

Through further research, the applicant found that in the semiconductor structure, a buried Word Line (WL) may simultaneously pass through an Active Area (AA) and a Shallow Trench Isolation (STI) area; and when working, the buried word line in the shallow trench isolation area may induce an inversion layer on the active area adjacent the shallow trench isolation area so as to form the parasitic transistor structure, thereby generating the leakage current.

Therefore, the disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure, which can avoid the formation of the parasitic transistor structure so as to avoid generating the leakage current in the semiconductor structure.

<FIG> is a schematic diagram of steps of a method for forming a semiconductor structure according to an embodiment of the disclosure. Referring to <FIG>, the method for forming a semiconductor structure includes steps S10 to S <NUM>. At S <NUM>, a semiconductor substrate is provided, and the semiconductor substrate has multiple separate active areas that are isolated from each other by shallow trench isolation areas. At S11, the trenches are formed by etching the active areas and the shallow trench isolation areas, herein the trenches include first trenches and second trenches, the first trenches are located in the active areas, the second trenches are located in the shallow trench isolation areas, and the first trenches have a width greater than a width of the second trenches. At S12, the word lines are formed in the trenches, herein the word lines include first word lines and second word lines, each first word line is located in a respective first trench, each second word line is located in a respective second trench, and the first word lines have a width greater than a width of the second word lines.

<FIG> are flowcharts of the process of a method for forming a semiconductor structure according to an embodiment of the disclosure.

Referring to S10, and <FIG> and <FIG>, herein <FIG> is a top view, and <FIG> is a cross-sectional diagram along a line A-A in <FIG>. A semiconductor substrate is provided. The semiconductor substrate has multiple separate active areas <NUM> that are isolated from each other by shallow trench isolation areas <NUM>.

The material of the semiconductor substrate may be such as Silicon (Si), Germanium (Ge), Silicon Germanium (GeSi), or Silicon Carbide (SiC), or may be Silicon on Insulator (SOI) or Germanium on Insulator (GOI), or may be other materials, e.g., III-V compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate is Silicon. Certain foreign ions are doped in the semiconductor substrate according to requirements. The foreign ions may be N-type foreign ions or P-type foreign ions. In an embodiment, the doping includes well area doping and source/drain area doping.

A method for forming the active areas <NUM> is provided in the disclosure and the method includes the following steps. Multiple shallow trenches are formed by etching on the semiconductor substrate by means of lithography. The shallow trench isolation areas <NUM> are formed by filling the shallow trenches with an isolation material. The isolation material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable isolation materials. In the embodiment, the isolation material refers to silicon oxide. Portions, isolated by the shallow trench isolation areas <NUM>, of the semiconductor substrate are the active areas <NUM>. In the embodiment, as illustrated in <FIG>, the active areas <NUM> extend along a direction B1. The active areas <NUM> in adjacent rows may be staggered to a certain degree in location.

In the embodiment, when the shallow trenches are filled with the isolation material, the isolation material also covers an upper surface of the semiconductor substrate. That is, upper surfaces of the active areas <NUM> are also covered with the isolation material. In <FIG>, since the active areas <NUM> are covered by the isolation material, the active areas <NUM> are drawn with dotted lines. In other embodiments of the disclosure, after the shallow trenches are filled with the isolation material, the isolation material on the upper surface of the semiconductor substrate is removed, and only the isolation material located inside the shallow trenches is remained. Or in the process of filling the shallow trenches with the isolation material, only insides of the shallow trenches are filled with the isolation material, and the upper surface of the semiconductor substrate is not covered with the isolation material.

Optionally, after the step of S10, the following steps are included. Referring to <NUM> and <FIG>, a sacrificial layer <NUM> is formed on a surface of the semiconductor substrate, and the sacrificial layer <NUM> covers the active areas <NUM> and the shallow trench isolation areas <NUM>. The material of the sacrificial layer <NUM> includes one or more of silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, monocrystalline silicon, and carbon.

Referring to S11, and <FIG>, the active areas <NUM> and the shallow trench isolation areas <NUM> are etched to form the trenches. The trenches <NUM> include a first trench 203A and a second trench 203B; the first trench 203A is located in the active area <NUM>, and the second trench 203B is located in the shallow trench isolation area <NUM>; and a width of the first trench 203A is greater than a width of the second trench 203B.

In the embodiment, since there is also a sacrificial layer <NUM> on the surface of the semiconductor substrate, the sacrificial layer <NUM> may be correspondingly etched to form the trench <NUM> during performing of the step S11.

In this step, the trenches <NUM> can be formed using lithography and etching processes. During etching, the widths of the first trench <NUM> and the second trench 203B are controlled by changing an etch rate of an etching substance on the shallow trench isolation areas <NUM> and an etch rate of an etching substance on the active areas <NUM>. That is, the widths of the first trench 203A and the second trench 203B are controlled by controlling an etch selection ratio of the etching substance on the shallow trench isolation areas <NUM> and on the active areas <NUM>. Specifically, the etch rate of the etching substance on the shallow trench isolation areas <NUM> is less than the etch rate of the etching substance on the active areas <NUM>, so that the width of the first trench 203A is greater than the width of the second trench 203B.

An embodiment of a method for forming the trenches is set forth as below. In the embodiment, the shallow trench isolation areas <NUM> are silicon dioxide isolation areas, and the active areas <NUM> are silicon active areas. The method for forming the trench includes the following steps.

Referring to <FIG>, a mask layer <NUM> and a photoresist layer <NUM> are formed on the sacrificial layer <NUM>. The mask layer <NUM> may be a single layer or multiple layers. In the embodiment, the mask layer <NUM> includes a carbon layer <NUM> and a silicon oxynitride (SION) layer <NUM> which are arranged in sequence.

Referring to <FIG>, the photoresist layer <NUM> is patterned to form a window <NUM>. Specifically, in this step, the photoresist layer <NUM> is patterned using an ashing method.

Referring to <FIG>, the mask layer <NUM> is etched along the window <NUM> to expose the sacrificial layer <NUM>. In this step, HBr and CF<NUM> may be used as etching gases to remove the SION layer <NUM>, and O<NUM>, SO<NUM>, and Ar may be used as etching gases to remove the carbon layer <NUM>.

Referring to <FIG>, the sacrificial layer <NUM> is continued to be etched to expose the active areas and the shallow trench isolation areas. In this step, CF<NUM>, CH<NUM>F<NUM> and He are used as etching gases to remove the sacrificial layer <NUM> to expose the active areas and the shallow trench isolation areas.

Referring to <FIG>, Cl<NUM>, HBr, CF<NUM>, and CHF<NUM> are used as gas sources, and the active areas <NUM> and the shallow trench isolation areas <NUM> are etched for the first time using a plasma process for a certain period of time. In this step, the etch rate of Cl<NUM>, HBr, CF<NUM>, and CHF<NUM> on silicon is greater than the etch rate of Cl<NUM>, HBr, CF<NUM>, and CHF<NUM> on silicon dioxide. Accordingly, the etching parameters, such as an etching time, may be controlled in this step to initially form the first trench <NUM> with a preset width. It should be understood that in this step, the shallow trench isolation areas may also be etched, with an etching amount much less than that of silicon.

The photoresist layer <NUM> and the mask layer <NUM> may be gradually removed by etching during an etching process. If the photoresist layer <NUM> and the mask layer <NUM> are not completely removed before the step of forming the first trench 203A as illustrated in <FIG>, the remaining photoresist layer <NUM> and mask layer <NUM> will be removed using processes such as ashing and etching.

Referring to <FIG> and <FIG>, <FIG> is a top view, and <FIG> is a cross-sectional diagram along a line A-A in <FIG>. CF<NUM> and CHF<NUM> are used as gas sources, the active areas <NUM> and the shallow trench isolation areas <NUM> are etched for the second time using the plasma process for a certain period of time. In this step, an etch rate of CF<NUM> and CHF<NUM> on silicon dioxide is greater than the etch rate of CF<NUM> and CHF<NUM> on silicon. Accordingly, the etching parameters such as an etching time may be controlled in this step to form the second trench 203B with a preset width. It should be understood that, in this step, the active areas <NUM> may be continued to be etched, with an etching amount much less than that of silicon dioxide.

Further, after etching, a step of cleaning by-products is further included. For example, O<NUM> is used to act on the first trench 203A and the second trench 203B for a certain period of time to clean the by-products.

A width W1 of the first trench 203A formed using the above method is greater than a width W2 of the second trench 203B formed using the above method. It should be understood that those skilled in the art may adopt other methods to form the trenches. Since the width W1 of the first trench 203A is greater than the width W2 of the second trench 203B, widths of a first word line and second lines subsequently formed are also different.

Further, the width W1 of the first trench 203A ranges from <NUM> to <NUM>, and the width W2 of the second trench 203B ranges from <NUM> to <NUM>. A difference between the width W1 of the first trench 203A and the width W2 of the second trench 203B ranges from <NUM> to <NUM>. If a size of the second trench 203B is too small, a width of a second word line 270B (shown in <FIG>) subsequently formed in the second trench 203B may be too small, resulting in a large word line resistance and slow switch-on of a transistor.

Further, in the embodiment, a depth D1 of the first trench 203A is less than a depth D2 of the second trench 203B, and thus depths of the first word line and the second word line subsequently formed are also different.

Referring to S12, the word lines are formed in the trenches <NUM>. The word lines include a first word line and a second word line. The first word line is located in the first trench, and the second word line is located in the second trench. The width of the first word line is greater than a width of the second word line.

An embodiment of a method for forming the word lines is set forth as below.

Referring to <FIG>, a dielectric layer <NUM>, an adhesion layer <NUM>, and a conductive layer <NUM> are formed in the trench <NUM> in sequence. The dielectric layer <NUM> covers at least an internal surface of the trenches <NUM>, the adhesion layer <NUM> covers at least the dielectric layer <NUM>, and the conductive layer <NUM> fills at least the trenches <NUM>. In this embodiment, the dielectric layer <NUM> and the adhesion layer <NUM> are only formed in the trenches <NUM>. In other embodiments of the disclosure, under influences of preparation processes, the dielectric layer <NUM> and the adhesion layer <NUM> are also formed on the upper surface of the sacrificial layer <NUM> in sequence. Before forming the conductive layer <NUM>, the dielectric layer <NUM> and the adhesion layer <NUM> on the surface of the sacrificial layer <NUM> are removed. In the embodiment, the conductive layer <NUM> also covers the upper surface of the sacrificial layer <NUM>.

The dielectric layer <NUM> may be an oxide layer, which may serve as a gate oxide layer. The dielectric layer <NUM> may be formed using an In-Situ Steam Generation (ISSG) process. It should be understood that if the dielectric layer <NUM> is formed by the ISSG process, due to the fact that the material of the shallow trench isolation areas <NUM> cannot be oxidized, the dielectric layer <NUM> may be only formed in the first trench 203A of the active area <NUM>, and may not be formed in the second trench 203B of the shallow trench isolation area <NUM>. If the dielectric layer <NUM> is formed using a deposition method or the like, the dielectric layer <NUM> may be formed in both the first trench 203A and the second trench 203B.

The adhesion layer <NUM> may be a titanium nitride layer, and the conductive layer <NUM> may be a metal tungsten layer.

Referring to <FIG> and <FIG>, <FIG> is a top view, and <FIG> is a cross-sectional diagram along a line A-A in <FIG>. The word lines <NUM> are formed by removing part of the adhesion layer <NUM> and the conductive layer <NUM>. An upper surface of the word lines <NUM> is lower than the surface of the semiconductor substrate. In the step, the conductive layer <NUM> is etched to a preset height, and part of the adhesion layer <NUM> which is not covered by the conductive layer <NUM> is removed, so that the word lines <NUM> are formed. A first word line 270A is formed in the first trench 203A, and a second word line 270B is formed in the second trench 203B. Because the dielectric layer <NUM> and the adhesion layer <NUM> are thin, in order to avoid line overlapping in the figures, the dielectric layer <NUM> and the adhesion layer <NUM> are not illustrated in <FIG>. It should be understood that in this step, the dielectric layer <NUM> may be partially removed or thinned with performing of the etching process.

Further, in a formed word lines structure, an upper surface of the adhesion layer <NUM> is lower than an upper surface of the conductive layer <NUM> to reduce a Gate Induce Drain Leakage (GIDL) effect.

Referring to <FIG>, since the width W1 of the first trench 203A is greater than the width W2 of the second trench 203B, a width C1 of the first word line 270A is greater than a width C2 of the second word line 270B. Since a thickness H of the shallow trench isolation area <NUM> between the second word line 270B and the active area <NUM> adjacent thereto is large enough, when the second word line 270B is powered to work, an inversion layer, on the active area <NUM>, induced by the second word line 270B has a small or no thickness, which is not enough to form a parasitic transistor structure, so that the leakage current will not be generated, and the storage performance of the semiconductor device is greatly improved. In certain technical solutions, the first word line and the second word line have the same width. When the second word line is powered to work, an inversion layer, on the active area adjacent thereto, induced by the second word line has a large thickness, so that a parasitic transistor structure can be formed, and the leakage current may be generated.

Further, since a depth D1 of the first trench 203A is less than a depth D2 of the second trench 203B, a distance H1 from the bottom of the first word line 270A to the surface of the semiconductor substrate is less than a distance H2 from the bottom of the second word line 270B to the surface of the semiconductor substrate, so that a fin-shaped structure is formed to increase a channel width and improve performance of the transistor of the semiconductor device formed subsequently. Further, the distance H1 from the bottom of the first word line 270A to the surface of the semiconductor substrate ranges from <NUM> to <NUM>, and the distance H2 from the bottom of the second word line 270B to the surface of the semiconductor substrate ranges from <NUM> to <NUM>.

Further, the upper surfaces of the first word line 270A and the second word line 270B are flush, and a distance H3 from the upper surfaces of the first word line 270A and the second word line 270B to the surface of the semiconductor substrate ranges from <NUM> to <NUM>. Further, after the step of S12, the method further includes the following step: referring to <FIG>, a protective layer <NUM> is filled. The protective layer <NUM> covers at least the word lines <NUM> to avoid the conductive layer <NUM> being oxidized. The protective layer <NUM> may be a SiN layer. In this embodiment, the protective layer <NUM> also covers the surface of the sacrificial layer <NUM>.

The disclosure further provides a semiconductor structure formed by using the above fabrication methods. <FIG> and <FIG> are structural schematic diagrams of a semiconductor structure according to an embodiment of the disclosure. <FIG> is a top view, and <FIG> is a cross-sectional diagram along a line A-A in <FIG>. Referring to <FIG> and <FIG>, the semiconductor structure includes a semiconductor substrate and word lines <NUM>.

The semiconductor substrate has multiple separate active areas <NUM> that are isolated from each other by shallow trench isolation areas <NUM>.

The word lines <NUM> include a first word line 370A and a word line 370B. The first word line 370A is located in the active area <NUM>, and the second word line 370B is located in the shallow trench isolation area <NUM>. A width C1 of the first word line 370A is greater than a width C2 of the second word line 370B. Further, the width C1 of the first word line 370A ranges from <NUM> to <NUM>, and the width C2 of the second word line 370B ranges from <NUM> to <NUM>. A difference between the width of the first word line 370A and the width of the second word line 370B ranges from <NUM> to <NUM>. Herein, if the width of the second word line 370B is too small, word line resistance may be large and switch-on of a transistor may be slow.

Further, a distance H1 from the bottom of the first word line 370A to the surface of the semiconductor substrate is less than a distance H2 from the bottom of the second word line 370B to the surface of the semiconductor substrate, so that a fin-shaped structure is formed to increase a channel width and improve performance of the transistor of the semiconductor device formed subsequently. Further, the distance H1 from the bottom of the first word line 370A to the surface of the semiconductor substrate ranges from <NUM> to <NUM>, and the distance H2 from the bottom of the second word line 370B to the surface of the semiconductor substrate ranges from <NUM> to <NUM>.

Further, upper surfaces of the first word line 370A and the second word line 370B are flush, and a distance H3 from the upper surfaces of the first word line 370A and the second word line 370B to the surface of the semiconductor substrate ranges from <NUM> to <NUM>.

<FIG> is a structural schematic diagram of a semiconductor structure according to another embodiment of the disclosure.

In the disclosure, a thickness H of each shallow trench isolation area <NUM> between the respective second word line 370B and the respective active area <NUM> adjacent thereto is large enough, when the second word line 370B is powered to work, an inversion layer, on the active area <NUM>, induced by the second word line 370B has a small or no thickness, which is not enough to form a parasitic transistor structure, so that leakage current will not be generated, and storage performance of the semiconductor device is greatly improved.

Claim 1:
A method for forming a semiconductor structure, comprising:
providing (S10) a semiconductor substrate, the semiconductor substrate having a plurality of separate active areas (<NUM>) that are isolated from each other by shallow trench isolation areas (<NUM>);
forming (S11) trenches by etching the active areas (<NUM>) and the shallow trench isolation areas (<NUM>), wherein the trenches comprise first trenches (203A) and second trenches (203B), the first trenches (203A) are located in the active areas (<NUM>), the second trenches (203B) are located in the shallow trench isolation areas (<NUM>), and the first trenches (203A) have a width greater than a width of the second trenches (203B); and
forming (S12) word lines (<NUM>) in the trenches, wherein the word lines (<NUM>) comprise first word lines (270A) and second word lines (270B), each first word line (270A) is located in a respective first trench, each second word line (270B) is located in a respective second trench, and the first word lines (270A) have a width greater than a width of the second word lines (270B),
wherein in the step of forming (S11) the trenches by etching the active areas (<NUM>) and the shallow trench isolation areas (<NUM>), an etch rate of an etching substance on the shallow trench isolation areas (<NUM>) is less than an etch rate of the etching substance on the active areas (<NUM>), so that the first trenches (203A) have the width greater than the width of the second trenches (203B),
wherein the shallow trench isolation areas (<NUM>) are silicon dioxide isolation areas, the active areas (<NUM>) are silicon areas, and forming (S11) the trenches by etching the active areas (<NUM>) and the shallow trench isolation areas (<NUM>) comprises:
forming a mask layer and a photoresist layer on the semiconductor substrate;
forming a window by patterning the photoresist layer;
exposing the active areas (<NUM>) and the shallow trench isolation areas (<NUM>) by etching the mask layer along the window;
using Cl<NUM>, HBr, CF<NUM>, and CHF<NUM> as gas sources, and etching, for a first time, the active areas (<NUM>) and the shallow trench isolation areas (<NUM>) using a plasma process for a period of time; and
using CF<NUM> and CHF<NUM> as gas sources, and etching, for a second time, the active areas (<NUM>) and the shallow trench isolation areas (<NUM>) using the plasma process for a period of time to form the first trenches (203A) and the second trenches (203B).