Patent Description:
At present, in the field of multi-chip cluster parallel computing, the collective communication solutions are commonly used in the industry to realize data sharing and data transmission operations among multiple nodes. In collective communication, the process of "chip A of node <NUM> sending data to chip B of node <NUM>" currently may be divided into four steps. Step <NUM>: The chip A on the node <NUM> sends data to the system memory of the node <NUM>. Step <NUM>: The chip A on the node <NUM> sends a network request to the network interface controller (NIC) on the node <NUM>, and the NIC on the node <NUM> reads the "data copied from chip A to system memory in step <NUM>" from the system memory of the node <NUM> and sends this data to the NIC of the node <NUM>. Step S3: The NIC of the node <NUM> receives the data of the NIC of the node <NUM> and stores this data in the system memory of the node <NUM>. Step <NUM>: The chip B of the node <NUM> reads the "data from chip A of node <NUM>" from the system memory of the node <NUM>. Regarding the above steps, how to simplify these steps and further optimize the performance of collective communication is an important technical issue in this field.

Patent literature <CIT> relates to a mechanism, method and computer usable medium provided for each root node of a multiple root node system and its own independent address space, allowing multiple system images within the same root node to have their own independent address spaces, for incorporating legacy root node and input/output adapters that are non-aware of the mechanisms.

Non-patent literature "Anonymous: "AI accelerator",
(https://en. org/w/index. php?title=AI_accelerator&oldid=<NUM>) relates to an AI accelerator that is a class of specialized hardware accelerator or computer system designed to accelerate artificial intelligence and machine learning applications, including artificial neural networks and machine vision.

Patent literature <CIT> relates to a peer-to-peer special purpose processor architecture and method, including special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the special purpose processors to other of the special purpose processors and a memory controller coupled to the special purpose processors, wherein the memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.

Patent literature <CIT> relates to system and method for migration of stateless virtual functions from one virtual plane to another, in which when a migration of a source virtual function to a destination virtual function in another virtual plane is to be performed, a source single root PCI manager is first interrupted by a multiple root PCI manager. Configuration information that defines the source virtual function is then redefined on the destination virtual function for this stateless migration. A function level reset may then be performed on the source virtual function. The destination SR-PCIM may be interrupted by the MR-PCIM with an interrupt for the destination virtual function. A function level reset may then be performed on the destination virtual function. The destination virtual function state may then be changed to an active state such that the migrated virtual function begins processing transactions.

Patent literature <CIT> relates to a flexible address mapping method and mechanism that allows mapping regions of a microcontroller's memory and I/O address spaces for a variety of applications by defining memory regions which are mapped to one of a set of physical devices by a programmable address mapper controlled by a set of programmable address registers. The mapping allows setting attributes for a memory region to prohibit writes, caching, and code execution. A deterministic priority scheme allows memory regions to overlap, mapping addresses in overlapping regions to the device specified by the highest priority programmable address register.

The disclosure provides an artificial intelligence chip and an operation mode thereof capable of efficiently performing collective communication.

The disclosure provides an artificial intelligence chip suitable for receiving a command carrying first data and address information. In an embodiment of the disclosure, the artificial intelligence chip includes a chip memory, a computing processor, a base address register, and an extended address processor. The computing processor is coupled to the chip memory. The base address register is configured to access an extended address space of the chip memory. The extended address space is greater than a physical memory address space of the chip memory. The extended address processor is coupled between the computing processor and the base address register. The extended address processor receives the command. The base address register is coupled between the extended address processor and a bus connected to a network interface controller. The computing processor is coupled between the extended address processor and chip memory. The address information points to one among a plurality of sections comprised in the extended address space. The extended address processor determines an operation mode of the first data according to the one pointed to by the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data. The first section corresponds to the physical memory address space.

The disclosure further provides a data operation method configured for an artificial intelligence chip. In an embodiment of the disclosure, the artificial intelligence chip includes a chip memory, a base address register, an extended address processor, and a computing processor. The data operation method includes the following steps. An extended address space for accessing the chip memory is allocated to the base address register. The base address register is coupled between the extended address processor and a bus connected to a network interface controller. The computing processor is coupled between the extended address processor and chip memory. The extended address space is greater than a physical memory address space of the chip memory. The extended address processor receives a command carrying first data and address information. The extended address processor is coupled between the computing processor and the base address register. The address information points to one among a plurality of sections comprised in the extended address space. The extended address processor determines an operation mode of the first data according to the one pointed to by the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data. The first section corresponds to the physical memory address space.

To sum up, in the embodiments of the disclosure, the artificial intelligence chip receives the command carrying the first data and the address information and determines the collective communication operation of the first data according to the extended address pointing to one among the sections of the extended address space. Therefore, the artificial intelligence chip may efficiently perform the collective communication operation.

Descriptions of the disclosure are given with reference to the exemplary embodiments illustrated by the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

The term "coupled to (or connected to)" used in the entire specification (including claims) refers to any direct or indirect connecting means. For example, if the disclosure describes a first apparatus is coupled to (or connected to) a second apparatus, the description should be explained as the first apparatus is connected directly to the second apparatus, or the first apparatus, through connecting other apparatus or using certain connecting means, is connected indirectly to the second apparatus. In addition, terms such as "first" and "second" in the entire specification (including claims) are used only to name the elements or to distinguish different embodiments or scopes and should not be construed as the upper limit or lower limit of the number of any element and should not be construed to limit the order of the elements. Moreover, elements/components/steps with the same reference numerals represent the same or similar parts in the figures and embodiments where appropriate. Elements/components/steps having same reference numerals or same terms are used as cross reference in different embodiments.

<FIG> is a schematic view of a collective communication system according to an embodiment of the disclosure. In this embodiment, the collective communication system shown in <FIG> includes nodes <NUM> and <NUM>. The nodes <NUM> and <NUM> may be computers or other computing platforms. In a collective communication solution provided by the related art, a process of sending data to an artificial intelligence chip <NUM> of the node <NUM> from an artificial intelligence chip <NUM> of the node <NUM> may be divided into four steps. Step S1: The artificial intelligence chip <NUM> on the node <NUM> sends data stored in a chip memory <NUM> to a system memory <NUM> of the node <NUM> through a chip set <NUM> and a central processing unit (CPU) <NUM>. In this embodiment, the artificial intelligence chip <NUM> may include a graphics processing unit (GPU) and/or a chip exhibiting other data computing functions. The chip memory <NUM> may include a GPU memory and/or other chip memories. Step S2: The artificial intelligence chip <NUM> on the node <NUM> sends a network request to a network interface controller (NIC) <NUM> on the node <NUM>. The NIC <NUM> on the node <NUM> reads the data copied to the system memory <NUM> in the above step S1 from the system memory <NUM> of the node <NUM>, and the NIC <NUM> sends this data to a NIC <NUM> of the node <NUM>. Step S3: The NIC <NUM> of the node <NUM> receives the data of the NIC <NUM> of the node <NUM> and stores this data in a system memory <NUM> of the node <NUM>. Step S4: The artificial intelligence chip <NUM> of the node <NUM> reads the data from the artificial intelligence chip <NUM> of the node <NUM> from the system memory <NUM> of the node <NUM>. These four steps essentially experience <NUM> time of data transmission and <NUM> times of data copying.

<FIG> is a schematic view of another collective communication system according to an embodiment of the disclosure. In order to reduce the transmission delay of collective communication, the remote direct memory access (RDMA) technique may be applied to the collective communication system shown in <FIG>. When data transmission is required, the NIC directly accesses the artificial intelligence chip (e.g., GPU) to shorten the data communication delay between the chips of different nodes, and performance may thus be improved in this way. To be specific, based on the collective communication system architecture shown in <FIG>, the RDMA technique may be divided into two steps. Step S5: The artificial intelligence chip (e.g., GPU) <NUM> on the node <NUM> sends a data transmission request to the NIC <NUM>. The NIC <NUM> of the node <NUM> reads the data required to be transmitted by the artificial intelligence chip <NUM> from the chip memory <NUM> according to the data transmission request and sends the data to the NIC <NUM> of the node <NUM>. Step S6: The NIC <NUM> of the node <NUM> receives the data of the NIC <NUM> of the node <NUM> and writes the data directly into a chip memory <NUM> of the artificial intelligence chip <NUM> of the node <NUM>. It thus can be seen that when the RDMA technique is applied, <NUM> times of data copying may be omitted, and the steps required for data transmission may be decreased to <NUM> steps.

The above paragraph describes the data transmission merely between <NUM> artificial intelligence chips (e.g., GPU) <NUM> and <NUM>. In practical applications, especially in the computation of weight values in artificial intelligence computing, after receiving the data from the NIC <NUM>, the artificial intelligence chip <NUM> of the node <NUM> needs to perform a collective communication operation on both the received data and local data before allowing the data to be used. Therefore, the cross-node collective communication based on RDMA technique needs to go through the following three steps. Step S5: The artificial intelligence chip (e.g., GPU) <NUM> of the node <NUM> sends a data transmission request (e.g., a read request) to the NIC <NUM>, and the NIC <NUM> of the node <NUM> reads the data required to be transmitted by the artificial intelligence chip <NUM> from the chip memory <NUM> according to the data transmission request and sends the data to the NIC <NUM> of the node <NUM>. Step S6: The NIC <NUM> of the node <NUM> receives the data of the NIC <NUM> of the node <NUM> and writes the data directly into the chip memory <NUM> of the artificial intelligence chip <NUM> (e.g., GPU) of the node <NUM>. Step S7 (not shown): The artificial intelligence chip <NUM> of the node <NUM> performs collective communication processing on the data from the node <NUM> and the data stored in the chip memory <NUM> (according to the type of collective communication, the artificial intelligence chip <NUM> performs different corresponding processing), and saves result data in the chip memory <NUM> of the artificial intelligence chip <NUM>.

Herein, after step S6 is completed, synchronization is required to be performed before execution of step S7. In step S7, collective communication processing is required to be performed once again on both the data of reading the node <NUM> from the chip memory <NUM> and the local data. There is an additional operation in step S6 and step S7, that is, the data of the node <NUM> is written into the chip memory <NUM> and then is read from the chip memory <NUM>, so as to go through collective communication processing with the local data. This additional operation brings the following overheads: <NUM>. The time of the entire process is increased (synchronization is required after step S6 is completed, which greatly increases the delay); <NUM>. A write operation is performed once on the chip memory <NUM> of the node <NUM> in step S6 (the data of node <NUM> is written into the chip memory <NUM>). In step S7, it is necessary to perform a read operation (read the data of the node <NUM> from the chip memory <NUM>) and a write operation (write the result data of the collective communication processing into the chip memory <NUM>) on the chip memory <NUM> again. Therefore, the burden of reading and writing of the chip memory <NUM> may grow, and increased memory reading and writing operation bandwidth may be occupied. In thus can be seen that regarding the collective communication processing performed on both the data of reading the node <NUM> from the chip memory <NUM> and the local data, the cross-node RDMA technique still needs to be improved.

In this embodiment, a data operation technique based on address extension is provided. In such a data operation technique, the three steps required in the foregoing embodiments (that is, the application of the RDMA technique to the cross-node collective communication operation) may be decreased to two steps, namely the following step A and step B. Step A: The artificial intelligence chip <NUM> of the node <NUM> sends a data transmission request (e.g., a read request) to the NIC <NUM>. The NIC <NUM> of the node <NUM> reads the data required to be transmitted by the artificial intelligence chip <NUM> from the chip memory <NUM> according to the data transmission request and sends the data required to be transmitted to the NIC <NUM> of the node <NUM>. Step B: the artificial intelligence chip <NUM> of the node <NUM> receives first data from the artificial intelligence chip <NUM> of the node <NUM> through the NIC <NUM> and writes the data from the artificial intelligence chip <NUM> of the node <NUM> to the chip memory <NUM> of the node <NUM>. The artificial intelligence chip <NUM> may also process the first data from the node <NUM> and second data stored in the chip memory <NUM> and then writes computed data generated after the processing into the chip memory <NUM>.

In this embodiment, step S6 and step S7 in the abovementioned cross-node RDMA technique are combined into a single step B. In order to achieve step B, a universal problem needs to be solved because of a plurality of different operations that may be applied to the node <NUM> and the node <NUM>. In this embodiment, the various operations described above are classified into a first operation and a second operation. Taking the artificial intelligence chip <NUM> of the node <NUM> as an example, the first operation of the artificial intelligence chip <NUM> is to receive data from the artificial intelligence chip <NUM> and write the data from the artificial intelligence chip <NUM> directly into the chip memory <NUM> without any operation on the data stored in the chip memory <NUM>. In other words, the first operation may be, for example, an operation of directly writing data from an external node.

Taking the artificial intelligence chip <NUM> of the node <NUM> as an example again, the second operation of the artificial intelligence chip <NUM> is to receive the first data from the artificial intelligence chip <NUM> and process the first data from the artificial intelligence chip <NUM> as well as the second data stored in the chip memory <NUM>. Based on the different data types of the first data and the second data, such as float (floating point number), half (half-precision floating point number) data types and the like, the above processing items may be one or more.

In this embodiment, the above operations may be distinguished in step B and may be dynamically supported at the same time. Therefore, in this embodiment, steps S6 and S7 in the above-mentioned cross-node RDMA technique may be supported, and processing of different data types may also be supported. In addition, in this embodiment, the above various operations may also be supported among multiple artificial intelligence chips in the same node.

To be specific, with reference to <FIG> is a circuit block schematic diagram of an artificial intelligence chip according to an embodiment of the disclosure. The architecture of <FIG> is equivalent to at least a part of one of the node <NUM> and the node <NUM> of <FIG>. In this embodiment, a single node includes artificial intelligence chips 100_1, 100_2, and 100_3. In the embodiment shown in <FIG>, the artificial intelligence chips 100_1, 100_2, and 100_3 receive external data from the a NIC <NUM>. The artificial intelligence chips 100_1, 100_2, and 100_3 may also perform communication. In addition, the artificial intelligence chip 100_1, 100_2, and 100_3 may also provide data to the NIC <NUM>. For instance, the artificial intelligence chips 100_1, 100_2, and 100_3 may be connected to the NIC <NUM> through a bus <NUM>. According to the actual design, the bus <NUM> may be a high-speed peripheral component interconnect express (PCIe) bus or other buses. The artificial intelligence chips 100_1, 100_2, and 100_3 may receive data from the NIC <NUM> through the bus <NUM>. The artificial intelligence chips 100_1, 100_2, and 100_3 may also perform communication through the bus <NUM>. Besides, the artificial intelligence chip 100_1, 100_2, and 100_3 may also provide data to the NIC <NUM> through the bus <NUM>. The NIC <NUM> is equivalent to the NIC <NUM> (or the NIC <NUM>) shown in <FIG>. The artificial intelligence chips 100_1, 100_2, and 100_3 are equivalent to the artificial intelligence chip <NUM> (or the artificial intelligence chip <NUM>) shown in <FIG>.

In the disclosure, the number of artificial intelligence chips in a single node may be one or more, which is not limited to the number provided in this embodiment.

In this embodiment, taking the artificial intelligence chip 100_1 as an example, the artificial intelligence chip 100_1 is suitable for receiving a command carrying the first data and address information. The artificial intelligence chip 100_1 includes a base address register (BAR) <NUM>, an extended address processor <NUM>, a computing processor <NUM>, and a chip memory <NUM>. The computing processor <NUM> is coupled to the chip memory <NUM>. The extended address processor <NUM> is coupled to the computing processor <NUM> and the base address register <NUM>. In this embodiment, the extended address processor <NUM> and the computing processor <NUM> may be implemented in hardware (physical circuits). In other embodiments, a collective communication engine <NUM> may be implemented in firmware (or software).

With reference to <FIG> and <FIG> together, <FIG> is a schematic flow chart of a data operation method according to an embodiment of the disclosure. In step S <NUM>, the base address register <NUM> is configured to access an extended address space of the chip memory <NUM>. In this embodiment, the extended address space is greater than a physical memory address space of the chip memory <NUM>.

In this embodiment, it is assumed that the physical memory address space of the chip memory <NUM> of the artificial intelligence chip 100_1, a physical memory address space of a chip memory (not shown) of the artificial intelligence chip 100_2, and a physical memory address space of a chip memory (not shown) of the artificial intelligence chip 100_3 are all SZ. Therefore, definition of the physical memory address spaces of the chip memories is shown in Table <NUM>.

As shown in Table <NUM>, the starting address of the chip memory <NUM> is GPU1_BA. The ending address of the chip memory <NUM> is GPU1_BA + SZ - <NUM>. The starting address of the chip memory of the artificial intelligence chip 100_2 is GPU2_BA. The ending address of the chip memory of the artificial intelligence chip 100_2 is GPU2_BA + SZ - <NUM>. The starting address of the chip memory of the artificial intelligence chip 100_3 is GPU3_BA. The ending address of the chip memory of the artificial intelligence chip 100_3 is GPU3_BA + SZ - <NUM>.

The artificial intelligence chips 100_1, 100_2, and 100_3 occupy a system address space of SZ. In addition, the system address space ensures the exclusiveness of the address spaces. That is, there is no overlap in any two system address spaces. Therefore, when a processing unit other than the NIC or the artificial intelligence chips 100_1, 100_2, and 100_3 uses a given address for accessing, the command corresponding to the given address may be correctly sent to the chip memory corresponding to the given address.

Generally, a X86 central processing unit uses a <NUM>-bit or <NUM>-bit address bus. Taking the <NUM>-bit address bus as an example, the central processing unit has 256TB addresses. But the address space actually used by all hardware in the existing system is far less than 256TB. A large number of addresses are not used.

When operations on N data types are required, the memory address space SZ of the base address register <NUM> is extended to an expanded address space greater than or equal to (N + <NUM>) x SZ, as shown in Table <NUM>. N is an integer greater than or equal to <NUM>. Therefore, in step S110, the base address register <NUM> is set to extend a first address space definition of the base address register <NUM> to a second address space definition. The first address space definition corresponds to physical memory address space of the chip memory. The second address space definition corresponds to the extended address space. The extended address space is an integer multiple, (e.g., N + <NUM>) of the physical memory address space. In this way, the unused address space in the original 256TB may be used. Besides, the extended system address space also ensures the exclusiveness of the address spaces. That is, there is no overlap in any two extended system address spaces.

Herein, N is associated with the data type of the collective communication operation that needs to be supported. If two data types of data reduction (REDUCE) operations are required to be supported, N is greater than or equal to <NUM>. The two data types are, for example, float (first data type) and half (second data type). For instance, taking the REDUCE operation of float and half supported by N=<NUM> as an example, the plan for the extended address space is shown in Table <NUM>.

In Table <NUM>, the extended address space includes <NUM> sections. These <NUM> sections are section <NUM>, section <NUM>, section <NUM>, and section <NUM>. Section <NUM> to section <NUM> may be used to identify different operations. For instance, the extended address space of section <NUM> is GPU_BA to GPU_BA + SZ-<NUM>. Section <NUM> applies to the existing normal read and write operations. The extended address space of section <NUM> is GPU_BA + SZ to GPU_BA + <NUM> x SZ - <NUM>. Section <NUM> applies to the REDUCE operation of the first data type (e.g., float data type). The extended address space of section <NUM> is GPU_BA + <NUM> x SZ to GPU_BA + <NUM> x SZ - <NUM>. Section <NUM> applies to the REDUCE operation of the second data type (e.g., half data type). Further, the extended address space of section <NUM> is GPU_BA + <NUM> x SZ to GPU_BA + <NUM> x SZ - <NUM>. Section <NUM> is reserved for other operations, such as a REDUCE operation of other data types (e.g., INT32 data type) or an illegal operation on an undefined data type. Any one of section <NUM>, section <NUM>, section <NUM>, and section <NUM> does not overlap with the remaining sections.

Therefore, through step S110, the extent of address space extension is determined by the number of types of operations that need to be operated, and extension may be performed while maintaining backward compatibility.

In step S120, the extended address processor <NUM> receives the command carrying the first data and the address information. In step S130, the extended address processor <NUM> determines an operation mode of the first data according to the address information pointing to one among a plurality of sections (e.g., section <NUM> to section <NUM> in Table <NUM>) of the extended address space.

Taking the data type REDUCE operation supported by Table <NUM> as an example, the specific behavior of the extended address processor <NUM> after parsing the address information is shown in Table <NUM> below.

When the address information points to a first section (e.g., section <NUM>) of the extended address space, the extended address processor <NUM> performs the first operation on the first data in step S140. The first section corresponds to the physical memory address space. In this embodiment, the first operation includes, for example, directly storing the first data in the chip memory <NUM> without processing the first data by the computing processor <NUM>, that is, a direct writing operation. When the address information points to a section other than the first section of the extended address space (i.e., one of sections <NUM> to <NUM>), the computing processor <NUM>
performs the second operation on the first data in step S150. Further, in step S150, the extended address processor <NUM> notifies the computing processor <NUM> of the operation mode. Therefore, the computing processor <NUM> may learn the operation mode based on the notification from the extended address processor <NUM> and performs the second operation on the first data accordingly. In this embodiment, the second operation includes, for example, computing the first data to generate computed data and storing the computed data in the chip memory <NUM>.

Taking Table <NUM> as an example, the second operation may be a REDUCE operation. Further taking the REDUCE operation as an example, the computing processor <NUM> may extract the second data from the chip memory according to the extended address in step S150 and computes the first data and the second data to generate the computed data. Next, the computing processor <NUM> stores the computed data in the chip memory <NUM> at one time.

In some embodiments, the operation type of the second operation is not limited to the REDUCE operation. In these operations, the operation type of the second operation may include at least one of a COMPARE operation, a REDUCE operation, and a non-collective communication operation. In these operations, the computing processor <NUM> may, for example, perform a COMPARE operation on the first data and the second data to obtain comparison results such as greater than, less than, and equal to, and records the comparison results in the local chip memory <NUM>. For instance, the multiple sections of the extended address space may correspond to different operation types. Therefore, the extended address processor <NUM> may determine the operation type performed on the first data through the address information pointing to one among the sections of the extended address space.

For ease of description, the extended address space in this embodiment includes <NUM> sectors as an example. The number of sections in the disclosure may be multiple, and is not limited to the number provided in this embodiment.

For another example, in an embodiment, the number of sections may be (M+<NUM>). M different operation types are supported in this embodiment. Therefore, when the address information points to a (M+<NUM>)th section of the extended address space, the extended address processor <NUM> may determine that the operation type performed on the first data is a Mth operation type, where M is an integer greater than or equal to <NUM>. Incidentally, the artificial intelligence chip 100_1 receives the command carrying the first data and the address information and determines the collective communication operation of the first data according to the extended address pointing to one among the sections of the extended address space. Therefore, the artificial intelligence chip 100_1 may efficiently perform the collective communication operation. Further, the collective communication operation based on address extension provided in this embodiment may greatly improve the cross-node operation performance in a large-scale clustering scenario, including support for REDUCE operations of different data types. For applications such as artificial intelligence training, a large number of REDUCE operations are executed, and in addition, full REDUCE operations across nodes may be executed. Based on the above operations of this embodiment, performance of the REDUCE operations and cross-node full REDUCE operations may be effectively improved, and the overall system computing performance may thus be enhanced.

The extended address processor <NUM> further determines the data type corresponding to the first data through the extended address pointing to one among the sections of the extended address space. When the extended address points to the second section (section <NUM>) of the extended address space, the first data may be determined as the first data type (e.g., float data type). Therefore, the first data and the second data of the float data type are sent to the computing processor <NUM>. The computing processor <NUM> performs the REDUCE operation on the first data and the second data of the float data type to generate computed data. Next, the computing processor <NUM> writes the computed data to the local chip memory <NUM> at one time.

When the extended address points to the third section (section <NUM>) of the extended address space, the first data may be determined as the second data type (e.g., half data type). Therefore, the first data and the second data of the half data type are sent to the computing processor <NUM>. The computing processor <NUM> performs the REDUCE operation on the first data and the second data of the half data type to generate computed data. Next, the computing processor <NUM> writes the computed data to the local chip memory <NUM> at one time. In an embodiment, the number of sections may be (N+<NUM>). Therefore, N different data types may be supported in this embodiment. Therefore, when the address information points to a (N+<NUM>)th section of the extended address space, the extended address processor <NUM> may determine that the first data is a Nth data type, where N is an integer greater than or equal to <NUM>.

In the disclosure, the sections other than the first section of the extended address space may be defined as different data types, defined as different operation types, or defined as different data types and different operation types. For instance, the second section is determined to be the first data type and the first operation is performed, and the third section is determined to be the second data type and multiple combinations such as the second operation are executed.

For another instance, for N data types and M operation types, plus the operation of the first section, a total of (<NUM>+N×M) possible combinations may be supported in the disclosure.

In addition, when the extended address points to the fourth section (section <NUM>) of the extended address space, the first data may be determined as the undefined data type. The undefined data type is an unrecognizable data type or an unacceptable data type. Therefore, the first data of the undefined data type may be sent to the reserved section. With reference to <FIG> and Table <NUM> together, <FIG> is a circuit block schematic diagram of an artificial intelligence chip according to another embodiment of the disclosure. In this embodiment, an artificial intelligence chip <NUM> includes a base address register <NUM>, an extended address processor <NUM>, a computing processor <NUM>, a chip memory <NUM>, and an address exception handling module <NUM>. The address exception handling module <NUM> is coupled to the extended address processor <NUM>. In this embodiment, when the extended address points to the fourth section (section <NUM>) of the extended address space, the first data may be determined as the undefined data type and is sent to the address exception handling module <NUM>. The address exception handling module <NUM> may perform the illegal operation on the first data. In this embodiment, sufficient teachings on collaborative operations among the base address register <NUM>, the extended address processor <NUM>, the computing processor <NUM>, and the chip memory <NUM> may be obtained in the embodiments of <FIG> and <FIG>, and description thereof is thus not repeated herein.

Claim 1:
An artificial intelligence chip (100_1, 100_2, 100_3, <NUM>), suitable for receiving a command carrying first data and address information, wherein the artificial intelligence chip (100_1, 100_2, 100_3, <NUM>) is part of a node (<NUM>, <NUM>) of a collective communication system, said node comprising also a network interface controller (<NUM>), and the artificial intelligence chip (100_1, 100_2, 100_3, <NUM>) comprises:
a chip memory (<NUM>, <NUM>);
a computing processor (<NUM>, <NUM>), coupled to the chip memory (<NUM>, <NUM>);
a base address register (<NUM>, <NUM>), configured to access an extended address space of the chip memory (<NUM>, <NUM>), wherein the extended address space is greater than a physical memory address space of the chip memory (<NUM>, <NUM>); and
an extended address processor (<NUM>, <NUM>), coupled between the computing processor (<NUM>, <NUM>) and the base address register (<NUM>, <NUM>), configured to receive the command,
wherein the base address register (<NUM>, <NUM>) is coupled between the extended address processor (<NUM>, <NUM>) and a bus (<NUM>) connected to the network interface controller (<NUM>), the network interface controller being external to the artificial intelligence chip, the computing processor (<NUM>, <NUM>) is coupled between the extended address processor (<NUM>, <NUM>) and the chip memory (<NUM>, <NUM>), the address information points to a section among a plurality of sections comprised in the extended address space, and upon receiving the command via the network interface controller, the extended address processor (<NUM>, <NUM>) determines an operation mode of the first data according to the section pointed to by the address information,
wherein the extended address processor (<NUM>, <NUM>) performs a first operation on the first data when the address information points to a first section of the extended address space,
wherein the extended address processor (<NUM>, <NUM>) notifies the computing processor (<NUM>, <NUM>) of the operation mode and the computing processor (<NUM>, <NUM>) performs a second operation on the first data when the address information points to a section other than the first section of the extended address space,
wherein the first section corresponds to the physical memory address space.