Patent Description:
The present disclosure relates generally to high-speed data links and, more particularly, to terminating high-frequency transmission lines.

Mobile communication devices may include a variety of components including circuit boards, integrated circuit (IC) devices and/or System-on-Chip (SoC) devices. The components may include processing devices, user interface components, storage and other peripheral components that communicate through a shared data communication bus, which may include a multi-drop serial bus or a parallel bus.

General-purpose serial interfaces known in the industry include the Inter-Integrated Circuit (I2C or I<NUM>C) serial interface and its derivatives and alternatives. An I2C interface may provide bandwidth measurable in kilobits per second (Kbps). Multimedia standards such as standards and specifications defined by the Mobile Industry Processor Interface (MIPI) Alliance including the Display System Interface (DSI) and DigRF, and standards defined by Electronic Industries Alliance (EIA) and/or the Consumer Electronics Association (CEA) including High-Definition Multimedia Interface (HDMI), and standards defined by the Video Electronics Standards Association (VESA) including DisplayPort.

The MIPI Alliance defines standards for the Improved Inter-Integrated Circuit (<NUM> C) serial interface, the Radio Frequency Front-End (RFFE) interface, the System Power Management Interface (SPMI) and other interfaces, including the C-PHY, D-PHY, M-PHY interfaces. These interface standards may be used to connect processors, sensors and other peripherals, for example. In some configurations, multiple bus masters are coupled to the serial bus such that two or more devices can serve as bus master for different types of messages transmitted on the serial bus. The RFFE interface standard defines communication protocols that can be used for controlling various radio frequency (RF) front-end devices, including power amplifier (PA), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, etc. These devices may be collocated in a single IC device or located in multiple IC devices. In a mobile communication device, multiple antennas and radio transceivers may support multiple concurrent RF links. SPMI protocols define a hardware interface that may be implemented between baseband or application processors and peripheral components. In some examples, SPMI protocols are implemented to support power management operations within a device.

Improved physical interfaces are needed to support the implementation of higher-speed, more complex applications, which drive the demand for ever-increasing performance from multi-drop serial buses.

Attention is drawn to <CIT> relating to an attenuator for attenuating a signal. The attenuator comprises a differential input port with a positive input node and a negative input node to receive the signal; and a differential output port with a positive output node and a negative output node to output the attenuated signal. The attenuator further comprises a first switched resistor network connected between the positive input node and the positive output node; and a second switched resistor network connected between the negative input node and the negative output node. Further a pair of compensation paths is connected to the first and second switched resistor networks for cancellation their parasitic leakages, where a first compensation path is connected between the positive input node and the negative output node, and a second compensation path is connected between the negative input node and the positive output node. The attenuator further comprises a control circuit to generate control signals for controlling the first and second switched resistor networks.

Further attention is drawn to <CIT> relating to a signal interconnect including a transmission line, a termination circuit coupled to the transmission line, and a high pass filter circuit coupled in series along the transmission line. The high pass filter circuit includes a first resistive circuit and a first capacitive circuit coupled in parallel. The first resistive circuit has a resistance based on a difference between a resistance of the transmission line at a high frequency and a resistance of the transmission line at a low frequency.

Attention is also drawn to <CIT> relating to communication systems and electrical circuits. An input termination circuit includes a first attenuation resistor and a second attenuation resistor. The resistance values of these two resistors are adjusted in opposite directions to maintain a stable output impedance.

Further attention is drawn to <CIT> relating to data communication over a multi-wire, multi-phase interface. A method includes equalizing three-phase signals received from two wires of the interface to provide equalized signals, providing first and second difference signals by comparing voltage differences between the equalized signals with first and second reference voltage levels respectively, capturing delayed and undelayed versions of the second difference signal using flipflops triggered by different edges in the first difference signal, and adjusting an equalizing circuit until outputs of the first flipflops indicate that a ratio of low-frequency attenuation to high-frequency amplification has been achieved. The three-phase signal received from a first of the two wires is in a different phase than the three-phase signal received from a second of the two wires.

Further attention is drawn to <CIT> relating to a circuit for implementing a differential input receiver / transmitter for matching line impedance. The circuit permits multiple splits in resistor and allows multiple injection points along the resistor string for input current to generate multiple values of offset voltage.

Certain aspects of the disclosure relate to systems, apparatus, methods and techniques that can be used to terminate transmission lines. Terminations are disclosed that can reduce impedance mismatches, minimize interference arising from reflections and improve transmitter and receiver performance.

Several aspects of the invention will now be presented with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements").

According to certain aspects, a serial data link may be used to interconnect electronic devices that are subcomponents of an apparatus such as a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a laptop, a notebook, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a global positioning system (GPS) device, a smart home device, intelligent lighting, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a game console, an entertainment device, a vehicle component, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), an appliance, a sensor, a security device, a vending machine, a smart meter, a drone, a multicopter, or any other similar functioning device.

<FIG> illustrates an example of an apparatus <NUM> that may employ a data communication bus. The apparatus <NUM> may include a processing circuit <NUM> having multiple circuits or devices <NUM>, <NUM> and/or <NUM>, which may be implemented in one or more ASIC devices or in a System-on-chip (SoC) device. In one example, the apparatus <NUM> may be configured for use as a communication device and the processing circuit <NUM> may include a processing device provided in an ASIC <NUM>, one or more peripheral devices <NUM>, and a transceiver <NUM> that enables the apparatus to communicate through an antenna <NUM> with a radio access network, a core access network, the Internet and/or another network.

The ASIC <NUM> may have one or more processors <NUM>, one or more modems <NUM>, on-board memory <NUM>, a bus interface circuit <NUM> and/or other logic circuits or functions. The processing circuit <NUM> may be controlled by an operating system that provides an application programming interface (API) layer that enables the one or more processors <NUM> to execute software modules residing in the on-board memory <NUM> or other processor-readable storage <NUM> provided on the processing circuit <NUM>. The software modules may include instructions and data stored in the on-board memory <NUM> or processor-readable storage <NUM>. The ASIC <NUM> may access its on-board memory <NUM>, the processor-readable storage <NUM>, and/or storage external to the processing circuit <NUM>. The on-board memory <NUM>, the processor-readable storage <NUM> may include read-only memory (ROM) or random-access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. The processing circuit <NUM> may include, implement, or have access to a local database or other parameter storage that can maintain operational parameters and other information used to configure and operate the apparatus <NUM> and/or the processing circuit <NUM>. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, soft or hard disk, or the like. The processing circuit <NUM> may also be operably coupled to external devices such as the antenna <NUM>, a display <NUM>, operator controls, such as switches or buttons <NUM>, <NUM> and/or an integrated or external keypad <NUM>, among other components. A user interface module may be configured to operate with the display <NUM>, external keypad <NUM>, etc. through a dedicated communication link or through one or more serial data interconnects.

The processing circuit <NUM> may include or be coupled to one or more buses 118a, 118b, <NUM> that enable certain devices <NUM>, <NUM>, and/or <NUM> to exchange messages and other information. In one example, the ASIC <NUM> may have a bus interface circuit <NUM> that includes a combination of circuits, counters, timers, control logic and other configurable circuits or modules. In one example, the bus interface circuit <NUM> may be configured to operate in accordance with communication specifications or protocols. The processing circuit <NUM> may include or control a power management function that configures and manages the operation of the apparatus <NUM>.

<FIG> illustrates certain aspects of an apparatus <NUM> that includes multiple devices <NUM>, and <NUM><NUM>-<NUM>N coupled to a serial bus <NUM>. The devices <NUM> and <NUM><NUM>-<NUM>N may be implemented in one or more semiconductor IC devices, such as an application processor, SoC or ASIC. In various implementations the devices <NUM> and <NUM><NUM>-<NUM>N may include, support or operate as a modem, a signal processing device, a display driver, a camera, a user interface, a sensor, a sensor controller, a media player, a transceiver, RFFE devices, and/or other such components or devices. In some examples, one or more of the slave devices <NUM><NUM>-<NUM>N may be used to control, manage or monitor a sensor device. Communication between devices <NUM> and <NUM><NUM>-<NUM>N over the serial bus <NUM> is controlled by a bus master <NUM>. Certain types of bus can support multiple bus masters <NUM>.

In one example, a master device <NUM> may include an interface controller <NUM> that manages access to the serial bus, configures dynamic addresses for slave devices <NUM><NUM>-<NUM>N and/or causes a clock signal <NUM> to be transmitted on a clock line <NUM> of the serial bus <NUM>. The master device <NUM> may include configuration registers <NUM> or other storage <NUM>, and other control logic <NUM> configured to handle protocols and/or higher level functions. The control logic <NUM> may include a processing circuit such as a state machine, sequencer, signal processor or general-purpose processor. The master device <NUM> includes a transceiver <NUM> and line drivers/receivers 214a and 214b. The transceiver <NUM> may include receiver, transmitter and common circuits, where the common circuits may include timing, logic and storage circuits and/or devices. In one example, the transmitter encodes and transmits data based on timing in the clock signal <NUM> provided by a clock generation circuit <NUM>. Other timing clocks <NUM> may be used by the control logic <NUM> and other functions, circuits or modules.

At least one device <NUM><NUM>-<NUM>N may be configured to operate as a slave device on the serial bus <NUM> and may include circuits and modules that support a display, an image sensor, and/or circuits and modules that control and communicate with one or more sensors that measure environmental conditions. In one example, a slave device <NUM><NUM> configured to operate as a slave device may provide a control function, module or circuit <NUM> that includes circuits and modules to support a display, an image sensor, and/or circuits and modules that control and communicate with one or more sensors that measure environmental conditions. The slave device <NUM><NUM> may include configuration registers <NUM> or other storage <NUM>, control logic <NUM>, a transceiver <NUM> and line drivers/receivers 244a and 244b. The control logic <NUM> may include a processing circuit such as a state machine, sequencer, signal processor or general-purpose processor. The transceiver <NUM> may include receiver, transmitter and common circuits, where the common circuits may include timing, logic and storage circuits and/or devices. In one example, the transmitter encodes and transmits data based on timing in a clock signal <NUM> provided by clock generation and/or recovery circuits <NUM>. The clock signal <NUM> may be derived from a signal received from the clock line <NUM>. Other timing clock signals <NUM> may be used by the control logic <NUM> and other functions, circuits or modules.

The serial bus <NUM> may be operated in accordance with an I2C, 13C, RFFE, SPMI, C-PHY, D-PHY protocol or another suitable protocol. At least one device <NUM>, <NUM><NUM>-<NUM>N may be configured to selectively operate as either a master device or a slave device on the serial bus <NUM>. Two or more devices <NUM>, <NUM><NUM>-<NUM>N may be configurable to operate as a master device on the serial bus <NUM>.

In one example, the serial bus <NUM> may be operated in accordance with an I3C protocol. Devices that communicate using the 13C protocol can coexist on the same serial bus <NUM> with devices that communicate using I2C protocols. The I3C protocols may support different communication modes, including a single data rate (SDR) mode that is compatible with I2C protocols. High-data-rate (HDR) modes may provide a data transfer rate between <NUM> megabits per second (Mbps) and <NUM> Mbps, and some HDR modes may be provide higher data transfer rates. I2C protocols may conform to de facto I2C standards providing for data rates that may range between <NUM> kilobits per second (kbps) and <NUM> Mbps. I2C and I3C protocols may define electrical and timing aspects for signals transmitted on the <NUM>-wire serial bus <NUM>, in addition to data formats and aspects of bus control. In some aspects, the I2C and I3C protocols may define direct current (DC) characteristics affecting certain signal levels associated with the serial bus <NUM>, and/or alternating current (AC) characteristics affecting certain timing aspects of signals transmitted on the serial bus <NUM>. In some examples, a <NUM>-wire serial bus <NUM> transmits data on a data line <NUM> and a clock signal on the clock line <NUM>. In some instances, data may be encoded in the signaling state, or transitions in signaling state of the data line <NUM> and the clock line <NUM>.

<FIG> illustrates an example of a device <NUM> adapted for connection to one or more links or lanes of a serial bus <NUM>. The device <NUM> may be implemented as a processing circuit and/or as an ASIC or SoC. An application processor <NUM> may serve as a data source and/or data sink. The application processor <NUM> may include or be coupled to a protocol controller <NUM> that is configured to format data and commands in accordance with a desired or selected communications protocol. In one example, the protocol controller <NUM> may be configured to generate datagrams that are formatted in accordance with the desired or selected communications protocol. The protocol controller <NUM> may include or be implemented using a microprocessor, a microcontroller, a sequencer, a state machine or some other processing device. In certain examples, the protocol controller <NUM> may be configured to encode data in messages to be sent in accordance with an I3C, D-PHY, M-PHY, C-PHY, RFFE, SPMI or other protocol.

In some implementations, the protocol controller <NUM> includes or cooperates with an encoder/decoder <NUM> that receives data generated using the application processor <NUM>, and encodes the data for transmission on the serial bus <NUM>. The encoder/decoder <NUM> may receive data from the serial bus <NUM> and provide decoded information for delivery to the application processor <NUM>. Serializer/deserializer circuits (e.g., the SERDES circuit <NUM>) and media access circuits <NUM> convert data to bitstreams for transmission in accordance with signaling specifications defined for the serial bus <NUM>. The SERDES circuit <NUM> and the media access circuits <NUM> convert bitstreams from signals received from the serial bus <NUM> to data that can be decoded and provided for processing by the application processor <NUM>. The media access circuits <NUM> may include transceivers, clock generators, clock recovery circuits phase-locked loop (PLL) circuits, and the like.

<FIG> illustrates an example of a system <NUM> that includes communication links used to couple an application processor <NUM> with an image sensor <NUM>, camera or other imaging device. In one example, the system may be embodied in an SoC. In one example, the system may be configured as a MIPI Camera Serial Interface <NUM> (CSI-<NUM>) <NUM>. The image sensor <NUM> may produce large volumes of pixel data and other data representative of an image captured by the image sensor. Data may be transmitted by the image sensor <NUM> in bursts when the image sensor <NUM> is capturing individual images or frames, and/or in continuous flow when the image sensor <NUM> is operated in a video mode or a multi-image mode. In certain implementations, a unidirectional high-speed image data link <NUM> is provided to communicate image data from the image sensor <NUM> to the application processor <NUM>. The application processor <NUM> may include bus interface circuits (D-PHY or C-PHY Rx <NUM>) that is configured to receive data from the image data link <NUM>. Bus interface circuits (D-PHY or C-PHY Tx <NUM>) in the image sensor <NUM> may enable the image sensor <NUM> to communicate over the image data link <NUM>.

A low-speed bidirectional control data bus <NUM> may be provided to support communication of command and control information between the application processor <NUM> and the image sensor <NUM>. A control data bus interface <NUM> in the application processor <NUM> may transmit commands and receive responses to the commands that amount to a fraction of the image data transmitted when the image sensor <NUM> is active. The control data bus interface <NUM> may exchange other types of information with the image sensor <NUM>. A control data bus interface <NUM> in the image sensor <NUM> may receive commands and transmit responses to the commands and may exchange other types of information with the application processor <NUM>.

The image sensor <NUM> may include a controller that may be configured by the application processor <NUM>. The controller may control certain aspects of the operation of the image sensor <NUM>. The control data bus <NUM> may couple other peripheral devices to the application processor <NUM> and/or the controller of the image sensor <NUM>. Protocols and specifications governing the high-speed image data link <NUM> and the control data bus <NUM> may be defined by the MIPI Alliance, by another standards body, or by a system designer. For the purposes of this disclosure, an architecture based on the CSI-<NUM> standards defined by the MIPI Alliance will be used as an example.

<FIG> illustrates a C-PHY interface <NUM> that may be operated in accordance with specifications or protocols defined by the MIPI Alliance. The C-PHY physical layer interface technology uses <NUM>-phase polarity encoding. The illustrated C-PHY interface <NUM> is implemented using a three-wire link <NUM>. At the transmitter, physical layer drivers <NUM> may each drive a wire of the three-wire link <NUM>. Data is encoded in a sequence of symbols transmitted on the three-wire link <NUM>, where each symbol defines signaling state of the three-wire link <NUM> for one symbol interval. In each symbol interval, one wire of the three-wire link <NUM> is undriven and the other two wires of the three-wire link <NUM> are driven with opposite polarity. C-PHY interface <NUM> can provide for high-speed data transfer and may consume half or less of the power of other interfaces because fewer than <NUM> drivers are active in each symbol interval.

In the illustrated C-PHY interface <NUM>, each wire of the <NUM>-wire link <NUM> may be undriven, driven positive, or driven negative. An undriven signal wire may be in a high-impedance state. An undriven signal wire may be driven or pulled to a voltage level that lies substantially halfway between the positive and negative voltage levels provided on driven signal wires. An undriven signal wire may have no current flowing through it. The signaling states may be denoted as {+<NUM>, -<NUM>, <NUM>}, and the line drivers <NUM> may be adapted to provide each of the three signaling states. In one example, drivers <NUM> may include unit-level current-mode drivers. In another example, drivers <NUM> may drive opposite polarity voltages on two signals transmitted on two wires of the three-wire link <NUM> while the third wire is at high impedance and/or pulled to ground. For each symbol interval, at least one signal is in the undriven (<NUM>) state, while the number of signals driven positive (+<NUM> state) is equal to the number of signals driven negative (-<NUM> state), such that the sum of current flowing to the receiver is zero. For each symbol, the state of at least one signal wire is changed from the symbol transmitted in the preceding transmission interval.

The C-PHY interface <NUM> can encode multiple bits per transition on the three-wire link <NUM>. In one example, a mapper/serializer <NUM> may map <NUM>-bit data <NUM> to a set of seven <NUM>-bit symbols which are provided in a serialized <NUM>-bit sequence of raw symbols <NUM> to a symbol encoder <NUM>. The symbol encoder <NUM> provides a sequence of control signals <NUM> corresponding to transmitted symbols that determine the signaling state of the three-wire link <NUM> for each of seven symbol intervals. The symbol encoder selects each transmitted symbol based on the immediately preceding transmitted symbol and a current raw symbol <NUM>. The symbol encoder <NUM> operates such that, for each symbol interval, the signaling state of at least one wire (the A, B, C wires) of the three-wire link <NUM> changes with respect to the signaling state in the immediately preceding symbol interval.

The use of <NUM>-wire, <NUM>-phase encoding permits a number of bits to be encoded in a plurality of symbols where the bits per symbol is not an integer. In the example of a three-wire, three-phase system, there are <NUM> available combinations of <NUM> wires, which may be driven simultaneously, and <NUM> possible combinations of polarity on any pair of wires that is driven simultaneously, yielding <NUM> possible states. Since each transition occurs from a current state to a different state, <NUM> of the <NUM> states are available at every transition such that the signaling state of at least one wire changes at each transition. With <NUM> states, log<NUM>(<NUM>) ≅ <NUM> bits may be encoded per symbol. Accordingly, a mapper may accept a <NUM>-bit word and convert it to <NUM> symbols, because <NUM> symbols carrying <NUM> bits per symbol can encode <NUM> bits. In other words, a combination of seven symbols that encodes five states has <NUM><NUM> (<NUM>,<NUM>) permutations. Accordingly, the <NUM> symbols may be used to encode the <NUM><NUM> (<NUM>,<NUM>) permutations of <NUM> bits.

At the receiver, a set of comparators <NUM> and symbol decoders <NUM> are configured to provide a digital representation of the state of each wire of the three-wire link <NUM>. Each of the comparators <NUM> compares signaling state of two wires of the three-wire link <NUM> to produce a set of difference signals <NUM>, including AB, BC and CA difference signals. The symbol decoder <NUM> may include a clock and data recovery (CDR) circuit <NUM> that generates a clock signal using transitions detected in the state of the three-wire link <NUM> between successive symbol intervals, where the clock signal is used to capture symbol values that represent signaling state of the three-wire link <NUM>. A deserializer/demapper <NUM> receives a set of <NUM> symbols <NUM>, which is demapped to obtain <NUM> bits of output data <NUM>.

<FIG> illustrates different configurations of drivers, receivers and/or transceivers that may be used to drive a serial bus and to receive signals from the serial bus. Certain of the configurations may be used to support general purpose serial communications, or may be operated in accordance with an I3C, D-PHY, M-PHY, C-PHY, RFFE, SPMI or other protocol.

Differential signaling typically involves transmitting information electrically using two complementary signals sent on a pair of wires 610a, 610b or 610c, which may be referred to as a differential pair. The use of differential pairs can significantly reduce electromagnetic interference (EMI) by canceling the effect of common-mode interference that affects both wires in a differential pair. On the forward channel <NUM>, a pair of wires 610a may be driven by a host differential driver <NUM>. The differential driver <NUM> receives a stream of input data <NUM> and generates positive and negative versions of the input data <NUM>, which are then provided to the pair of wires 610a. The differential receiver <NUM> on the client side generates an output data stream <NUM> by performing a comparison of the signals carried on the pair of wires 610a.

On the reverse channel <NUM>, one or more pairs of wires 610c may be driven by a client-side differential driver <NUM>. The differential driver <NUM> receives a stream of input data <NUM> and generates positive and negative versions of the input data <NUM>, which are provided to the pair of wires 610c. The differential receiver <NUM> on the host generates an output data stream <NUM> by performing a comparison of the signals carried on the pair of wires 610c.

In a bidirectional channel <NUM>, the host and client may be configured for half-duplex mode and may transmit and receive data on the same pair of wires 610b. A bidirectional bus may alternatively or additionally be operated in full-duplex mode using combinations of the forward and reverse differential drivers <NUM>, <NUM> to drive multiple pairs of wires 610a, 610c. In the half-duplex bidirectional implementation depicted for the bidirectional channel <NUM>, the differential drivers <NUM> and <NUM>' may be prevented from driving the pair of wires 610b simultaneously using, for example, a respective output enable (OE) control 630a, 630b to force the differential drivers <NUM> and <NUM>' into a high impedance state. The differential receiver <NUM>' may be prevented from driving the input/output <NUM> while the differential driver <NUM> is active, typically using an OE control 630b to force the differential receiver <NUM>' into a high impedance state. The differential receiver <NUM> may be prevented from driving the input/output <NUM> while the differential driver <NUM>' is active, typically using an input enable (IE) control 632b to force the differential receiver <NUM> into a high impedance state. In some instances, the outputs of the differential drivers <NUM> and <NUM>' and the differential receivers <NUM> and <NUM>' may be in a high-impedance state when the interface is not active. Accordingly, the OE controls 630a, 630b of the differential drivers <NUM>, <NUM>' and the IE controls 632a, 632b of the differential receivers <NUM>, <NUM>' may be operated independently of one another.

Each of the differential drivers <NUM>, <NUM>, <NUM>' and <NUM> may include a pair of amplifiers, one receiving at one input the inverse of the input of the other amplifier. The differential drivers <NUM>, <NUM>, <NUM>' and <NUM> may each receive a single input and may have an internal inverter that generates an inverse input for use with a pair of amplifiers. The differential drivers <NUM>, <NUM>, <NUM>' and <NUM> may also be constructed using two separately controlled amplifiers, such that their respective outputs can be placed in high impedance mode independently of one another.

In one example, the differential drivers <NUM>, <NUM>, and/or <NUM> may be reconfigured or controlled such that only one of the wires in a pair of wires 610a, 610b or 610c of an active lane is driven. In other examples, the differential drivers <NUM>, <NUM>, and/or <NUM> may be turned off or placed in a high-impedance output mode. In other examples, a single-ended channel <NUM> may employ separate, single-ended line drivers <NUM> and receivers <NUM> to provide communications over a single-wire, single-ended link 610d. The single-ended line drivers <NUM> and receivers <NUM> may be used in a C-PHY interface for example. In some instances, the input <NUM> and output <NUM> of the single-ended link 610d may be bidirectional, and both transmitting and receiving devices may employ a transceiver that includes both a line driver <NUM> and a receiver <NUM> that is controlled in accordance with one or more protocols.

Certain aspects of this disclosure relate to a SERDES physical layer circuits (SERDES PHY) that are configured for high-frequency transmissions. The SERDES PHY may be used to implement communication links within or between integrated circuits, semiconductor die and/or device packages. Improved reliability can be obtained for a SERDES PHY that has been adapted to include impedance matching techniques provided in accordance with certain aspects of this disclosure.

<FIG> illustrates a communication link <NUM> that may be implemented using a SERDES physical layer. In a conceptual communication link <NUM>, a voltage source <NUM> drives an ideal transmission line <NUM> that has a characteristic impedance (Z<NUM>), which may be defined as the ratio of the amplitudes of voltage and current of a signal propagating along the transmission line <NUM>. In the illustrated example, the transmission line <NUM> is terminated by terminating resistors <NUM>, <NUM> that match the characteristic impedance of the transmission line <NUM>.

A resistor may be defined as a two-terminal electrical component that has a configured or configurable electrical resistance and/or that dissipates electrical power. Other components may present a resistance to electrical current and may dissipate power. For example, the transmission line <NUM> may have a relatively low resistance that is proportional to the physical length, cross-sectional area, temperature and/or other characteristics or factors. In certain aspects of this disclosure, resistors may have a resistance of at least <NUM> ohms. In various examples provided in this disclosure, terminating resistors or resistors used in terminating circuits have <NUM> ohm, and <NUM> ohm resistors. Resistors of other values of resistance can be used in different implementations. Resistors may be provided as discrete components, deposited structures and/or structures fabricated in an IC device.

A first terminating resistor <NUM> couples the voltage source <NUM> to a first end of the transmission line <NUM>, and a second terminating resistor <NUM> is coupled between a second end of the transmission line <NUM> and circuit ground. The terminating resistors <NUM>, <NUM> have a value that is selected to match the characteristic impedance of the transmission line <NUM>. When the terminating resistors <NUM>, <NUM> match the characteristic impedance of the transmission line <NUM>, signal reflections are suppressed. A signal reflection may occur when a signal received from the transmission line <NUM> is not totally absorbed at the receiving end and unabsorbed energy bounces back along the transmission line <NUM>. For example, a major proportion of the energy in a signal arriving at an unterminated transmission line may be reflected when a line receiver in the receiving device presents a high impedance input to the unterminated transmission line. The voltage reflection coefficient of the transmission line <NUM> may be defined as the ratio of the voltage of the reflected signal at the terminating point <NUM> of the transmission line <NUM> to the voltage of the arriving signal (or incident signal) at the terminating point <NUM>. The voltage reflection coefficient may be expressed as: <MAT> where ZL is the impedance of the load at the terminating point <NUM> (here a resistor RL), and where Z<NUM> is the characteristic impedance of the transmission line <NUM>. In some instances, the characteristic impedance and the terminating resistors <NUM>, <NUM> have resistance value of <NUM>Ω (<NUM> ohms).

<FIG> also illustrates a model of a real-world communication link <NUM> where parasitic pad capacitances <NUM>, <NUM> are present at termination nodes, which are represented as input/output (I/O) pads <NUM>, <NUM> respectively. In the illustrated real-world communication link <NUM>, a voltage source <NUM> drives a transmission line <NUM> that has a nominal characteristic impedance (Z<NUM>). The transmission line <NUM> is terminated by terminating resistors <NUM>, <NUM> that are selected to match the characteristic impedance of the transmission line <NUM>. A first terminating resistor <NUM> couples the voltage source <NUM> to a first end of the transmission line <NUM>, and a second terminating resistor <NUM> is coupled between a second end of the transmission line <NUM> and circuit ground. Reflections can occur when the terminating resistors <NUM>, <NUM> do not closely match the characteristic impedance of the transmission line <NUM>.

The parasitic pad capacitances <NUM>, <NUM> alter the termination impedances by adding reactance. Altered terminations can cause an impedance mismatch with respect to the characteristic impedance of the transmission line <NUM>. Consequently, signal reflections can be expected at both ends of the transmission line <NUM>. In some instances, parasitic capacitance present at the input of a receiving device may be observed at the I/O pad <NUM>.

Mobile communication devices and other devices are used in applications that demand greater data throughput from serial interfaces. Demands for increased data throughput have been addressed in many applications by increasing the frequency of operation of the serial interfaces. In some instances, serial interfaces are operated at frequencies of <NUM> and more. The reactance introduced by parasitic pad capacitance at the termination points of a transmission line is inversely proportional to the frequency of signals transmitted over the transmission line and the operation of a serial bus at higher frequency produces lower reactance. Furthermore, the wavelength of higher frequency signals transmitted over a copper transmission line may be comparable to the physical length of the transmission line in a mobile communication device, which can exacerbate interference caused by reflections when reflected edges in a digital signal arrive coincide with the arrival of a subsequent edge in the digital signal.

<FIG> illustrates the effect of impedance mismatch on signaling <NUM> in a channel <NUM> of a communication link <NUM> that employs a SERDES PHY. The communication link <NUM> includes a source device <NUM> and load device <NUM> coupled by a transmission line that provides the channel <NUM>. An impedance mismatch is present at each end of the channel. The impedance mismatch at the source device <NUM> may be attributable to parasitic capacitance and/or other capacitances present at the transmitting pad <NUM>. The impedance mismatch at the load device <NUM> may be attributable to parasitic capacitance and/or other capacitances present at the receiving pad <NUM>.

A pulse <NUM> is launched into the channel <NUM> in a signal originating at a transmitter in the source device <NUM>. The fundamental frequency of the pulse may correspond to a wavelength in the channel <NUM> that is of the same order of magnitude as the physical length of the channel <NUM>. In one example, the pulse <NUM> may correspond to a half-cycle of a <NUM> clock signal and the pulse <NUM> may be transmitted over a wire, connector or other transmission line that is approximately <NUM> long. In the illustrated example, the transmission time of a pulse over the channel <NUM> closely matches the pulse width <NUM>.

The launch of the pulse <NUM> introduces energy into the channel. In an ideal, lossless, impedance-matched channel, all of the energy introduced into the channel <NUM> at the source device <NUM> is absorbed at the load device <NUM>. In real-world implementations, some energy is lost in transmission through the channel <NUM> and parasitic capacitance can cause interfering reflections. When the channel <NUM> is long enough, the transmission loss may be sufficiently large that the reflected waveforms are attenuated to the extent that reflected energy has little effect on the receiver in the load device <NUM>. In mobile communication devices, serial bus transmission lines have a length in the order of <NUM> and reflections can have a deleterious effect on the receiver.

As illustrated generally in the flow diagram <NUM>, the pulse <NUM> produces a voltage <NUM> at the transmitting pad <NUM> that has a launch amplitude <NUM> when the pulse <NUM> is launched into the channel <NUM>. The pulse <NUM> traverses the channel <NUM> and produces a voltage <NUM> with an attenuated amplitude <NUM> when the arriving pulse <NUM> reaches the receiving pad <NUM> at the receiver. The receiver sees an arriving pulse <NUM> that has been attenuated due to the effect of losses in the channel <NUM>. The receiver absorbs most of the energy <NUM> in the arriving pulse <NUM>. Some energy is retained in the channel <NUM> in a reflected pulse <NUM> that bounces from the receiving pad <NUM> and returns toward the transmitter. The voltage <NUM> at the receiving pad <NUM> that is attributable to the reflected pulse <NUM> has an initial amplitude <NUM>.

The reflected pulse <NUM> traverses the channel <NUM> and arrives as an attenuated reflected pulse <NUM> that produces a voltage <NUM> with a further attenuated amplitude <NUM> when the attenuated reflected pulse <NUM> reaches the transmitting pad <NUM>. The transmitter absorbs most of the energy <NUM> in the attenuated reflected pulse <NUM>. Some energy is retained in the channel <NUM> in a twice-reflected pulse <NUM> that bounces from the transmitting pad <NUM> and returns toward the receiver. The voltage <NUM> at the transmitting pad <NUM> that is attributable to the twice-reflected pulse <NUM> has an initial amplitude <NUM>. The twice-reflected pulse <NUM> is added to the signal that originates at the transmitter in the source device <NUM>.

The twice-reflected pulse <NUM> traverses the channel <NUM> and contributes a voltage <NUM> that is added to the voltage produced by the transmitter-originated signal. In the illustrated example, the twice-reflected pulse <NUM> combines with the low-voltage state of the transmitter-originated signal. The receiver sees an attenuated twice-reflected pulse <NUM>. When the attenuated twice-reflected pulse <NUM> interferes with a second pulse transmitted by the receiver, the receiver sees an arriving second pulse <NUM> with an increased amplitude.

The attenuated twice-reflected pulse <NUM> can cause errors in data reception. The attenuated twice-reflected pulse <NUM> may have an effect on one or more edges of the arriving second pulse <NUM> at the receiver. The presence of the attenuated twice-reflected pulse <NUM> at the receiver may be interpreted as a valid pulse when the amplitude of the attenuated twice-reflected pulse <NUM> exceeds a threshold level <NUM> used to distinguish between logic levels. In another example, the addition of the attenuated twice-reflected pulse <NUM> to the arriving second pulse <NUM> may alter the time at which the voltage level at the receiver crosses the threshold level <NUM> used to distinguish between logic levels. Differences in timing of threshold crossings causes jitter in the received signals. Jitter can affect a clock signal and/or may require increased timing tolerances that allow the receiver to ignore reflected signals. Jitter can limit the maximum frequency of signals transmitted through the channel <NUM>. Jitter can be particularly troublesome when pulses have durations that are close in length to the transition time of edges through the channel <NUM>.

Attenuation and loss during transmission through a physically short channel may be lower than attenuation through a physically long channel. High-frequency signals transmitted through a short channel <NUM> may be affected by multiple reflections when attenuation in the channel is low. Multiply-reflected waveforms can significantly interfere with incoming signals.

<FIG> includes a graph <NUM> that illustrates the effect of multiple reflections on a signal transmitted through a lossy channel that has mis-matched terminations. A first curve <NUM> illustrates insertion loss (primarily channel attenuation) for the channel over a range of frequencies. The first curve <NUM> relates to a channel that is terminated with matching impedances. A second curve <NUM> relates to a channel that has mismatched terminations. The second curve <NUM> illustrates insertion loss and reflection loss, where reflection loss corresponds to power that was reflected rather than being received and absorbed at the receiver. The second curve <NUM> illustrates the effect of resonance, which may be caused by standing waves that occur when transitions in the signal occur just as reflections of previously transmitted transitions arrive at the transmitter and/or receiver.

The resonating insertion loss illustrated in the second curve <NUM> can result in configurations where loss at a higher frequency can be less than loss at a lower frequency. Such insertion loss behavior can be referred to as non-monotonic and/or non-linear with respect to the frequency. The resonating insertion loss illustrated in the second curve <NUM> may indicate that conventional methods of combatting reflections may not be effective when the frequency of transmitted signals results in pulse durations that are multiples of the transition time through the channel.

<FIG> includes tables <NUM>, <NUM> that illustrate the effect of signaling frequency on terminating impedance and the voltage reflection coefficient (Γ) when parasitic capacitance is present at the terminations of a channel that has a <NUM> ohm characteristic impedance. Capacitive reactance may be calculated as <NUM>/(ω × C), where ω is the angular frequency of the signal received at the termination. The first table <NUM> relates to an interface in which the parasitic capacitance has a value of <NUM> pF and the second table <NUM> relates to an interface in which the parasitic capacitance has a value of <NUM> pF. Each table includes reactance (XC), resultant termination impedance (R ∥ XC) and reflection coefficient, which may be used to calculate power loss due to reflections.

Continuous Time Linear Equalizer (CTLE) is used in certain interfaces to combat channel losses caused by parasitic capacitance. CTLE provides a simple, low-cost equalization solution that is effective when channel loss has a linear relationship with frequency. However, CTLE can be ineffective in the presence of non-linear interference, including when the resonating channel loss is not linear. For example, CTLE may provide over-equalization and/or under-equalization at different frequencies.

<FIG> illustrates an example of inductive termination <NUM> in which two inductors <NUM>, <NUM> are added to the termination circuits in a high-frequency interface. Each end of the transmission line <NUM> includes a transmission circuit that has a resistor <NUM> or <NUM>, parasitic capacitance <NUM> or <NUM> and inductor <NUM> or <NUM>. The inductors <NUM>, <NUM> have an inductance value selected to cancel the effect of the corresponding parasitic capacitance <NUM> or <NUM>. Inductive reactance may be calculated as ω × L, where ω is the angular frequency of the signal received at the termination. Inductive reactance increases as capacitive reactance decreases, and inductive termination circuits are tuned to a design frequency. Inductive termination circuits may perform sub-optimally when signaling frequency varies.

The characteristics of an impedance-mismatched transmission line in the communication link may also be attributed to individual transmission lines in differential communication links. <FIG> illustrates a two-wire differential link <NUM> in which a signal is transmitted in opposite-polarity versions on two physically-close wires. Each wire may be characterized as a transmission line <NUM>, <NUM>. The resistors <NUM>, <NUM> in the transmitter and the resistors <NUM>, <NUM> in the receiver that are used to terminate respective transmission lines <NUM>, <NUM> have resistance values that match the nominal characteristic impedances of the transmission lines <NUM>, <NUM>. Parasitic capacitances <NUM>, <NUM>, <NUM>, <NUM> in the transmitter and receiver are coupled to respective transmission lines <NUM>, <NUM>.

<FIG> also illustrates a three-wire differential link <NUM>, which may be used in a C-PHY interface, for example. In a C-PHY interface, a three-phase signal is transmitted in different phases on each of three wires. Each wire may be characterized as a transmission line 1146a, 1146b 1146c. A set of switched resistors <NUM> in the transmitter and a set of resistors <NUM> in the receiver are used to terminate respective transmission lines 1146a, 1146b 1146c and have resistance values that match the nominal characteristic impedances of the transmission lines 1146a, 1146b 1146c. Parasitic capacitances <NUM>, <NUM> affecting the transmitter and receiver are also coupled to the respective transmission lines 1146a, 1146b 1146c.

Certain aspects of this disclosure relate to a termination scheme that can operate at high signaling frequencies and can reduce resonance effects including interference caused by multiply-reflected waveforms. The presently disclosed termination scheme is effective in terminating short channels at the transmitting end and at the receiving end. A cost-effective approach to suppressing the effects of parasitic capacitance includes splitting the termination resistance between two resistors. A first resistor is coupled to the transmission line and to the connection pad of a device and second resistor is provided after the connection pad of the device, including when the parasitic capacitance is sourced in the pad and/or coupled to the pad. The first resistor may be provided external to the IC device that includes the transmitter or receiver. In one example, the first resistor is provided on a chip carrier, printed circuit board or a substrate that carries the IC device that includes the transmitter or receiver. The proposed termination scheme can improve impedance matching and suppress multi-reflection interference in short channels. The proposed termination scheme can linearize the response of the channel to changing signal frequency, and can enable optimal performance of a CTLE.

<FIG> illustrates an example of communication link <NUM> that has been adapted in accordance with certain aspects of this disclosure. As illustrated, a voltage source <NUM> drives a transmission line <NUM> that has a nominal characteristic impedance (Z<NUM>). The voltage source <NUM> may represent a line driver in a transmitting device. In the illustrated example, the transmission line <NUM> is terminated by a pair of terminating resistors <NUM>, <NUM> at the transmitting end and by a pair of terminating resistors <NUM>, <NUM> at the receiving end. At the transmitting end, the terminating resistors <NUM>, <NUM> couple the voltage source to the transmission line <NUM>, and provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line <NUM>. At the receiving end, the terminating resistors <NUM>, <NUM> couple the transmission line <NUM> to circuit ground and provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line <NUM>.

In a transmitting device, the terminating resistors <NUM>, <NUM> are coupled to one another at or through an I/O pad <NUM>. In one example, the terminating resistors <NUM>, <NUM> each have a resistance equal to about half the nominal value of the characteristic impedance of the transmission line <NUM>. One or more parasitic capacitances <NUM> are shown as being coupled to the I/O pad <NUM> which is located at the connecting point of the pair of terminating resistors <NUM>, <NUM> at the transmitting end of the transmission line <NUM>. In some examples, a first terminating resistor <NUM> is provided on the same IC device that includes the transmitting device. The second terminating resistor <NUM> may be provided on the same IC device that includes the transmitting device. In some examples, the second terminating resistor <NUM> is provided external to the IC device that includes the transmitting device. For example, the second terminating resistor <NUM> can be provided on a chip carrier, printed circuit board or a substrate that carries the IC device that includes the transmitting device.

In a receiving device, the terminating resistors <NUM>, <NUM> are coupled to one another at or through an I/O pad <NUM>. One or more parasitic capacitances <NUM> are shown as being coupled to the I/O pad <NUM> and thereby also coupled at the connecting point of the pair of terminating resistors <NUM>, <NUM> at the receiving end of the transmission line <NUM>. An input of a line receiver circuit may be coupled to the I/O pad <NUM> and may present a high-impedance to the I/O pad <NUM>. The input of the line receiver circuit may contribute to the parasitic capacitance at the I/O pad <NUM>. In one example, the terminating resistors <NUM>, <NUM> each have a resistance equal to about half the nominal value of the characteristic impedance of the transmission line <NUM>. In some examples, a first terminating resistor <NUM> may be provided within the same IC device that includes the receiving device. In other examples, the first terminating resistor <NUM> may be provided external to the IC device that includes the receiving device. For example, the first terminating resistor <NUM> may be provided on a chip carrier, printed circuit board or a substrate that carries the IC device that includes the receiving device.

<FIG> includes an receiver terminating circuit <NUM> configured in accordance with the scope of the claims. An IC device <NUM> is coupled to a transmission line <NUM> through the receiver terminating circuit <NUM>. The transmission line <NUM> may provide a single ended lane of a serial bus or parallel bus. The receiver terminating circuit <NUM> has a first resistor <NUM> and a second resistor <NUM> coupled at a center point <NUM> of the receiver terminating circuit <NUM>.

In the illustrated example, the first resistor <NUM> is physically located outside the IC device <NUM> and is configured to couple an I/O pad <NUM> of the IC device <NUM> to the transmission line <NUM>. In some examples, the first resistor <NUM> is provided on a chip carrier, printed circuit board or a substrate that carries the IC device <NUM>. The center point <NUM> of the receiver terminating circuit <NUM> lies within the IC device <NUM> and is coupled to the I/O pad <NUM> and to the first resistor <NUM> through the I/O pad <NUM>. The center point <NUM> may be further coupled to a high-impedance input of a line receiver, comparator or other such device within the IC device <NUM>. The second resistor <NUM> is further coupled to circuit ground.

The first resistor <NUM> and the second resistor <NUM> are connected in series and the combination terminates the transmission line <NUM> to circuit ground through a combined resistance of R. The resistance values of the first resistor <NUM> and the second resistor <NUM> are selected to match the nominal value of the characteristic impedance (Z<NUM>) of the transmission line <NUM>. The nominal value of the characteristic impedance of the transmission line <NUM> may be defined as the designed impedance of the transmission line <NUM>, where some variance from the nominal value may be observed in some systems. The characteristic impedance for an ideal transmission line is purely resistive. In some examples, the first resistor <NUM> and the second resistor <NUM> that have equal resistance values (R/<NUM>), where R = Z<NUM>.

A parasitic capacitor <NUM> is represented as being coupled to the center point <NUM> of the series-connected first resistor <NUM> and second resistor <NUM>. The parasitic capacitor <NUM> may account for a parasitic capacitance associated with, or resulting from the structure of the I/O pad <NUM> and connectors coupled to the I/O pad <NUM> or the center point <NUM>. The parasitic capacitance may also include gate capacitance of one or more transistors in a line receiver coupled to the I/O pad <NUM> or center point <NUM>.

The configuration of the receiver terminating circuit <NUM> limits the effect of the capacitive reactance corresponding to the parasitic capacitor <NUM> with respect to a conventional line termination. The parallel arrangement of the parasitic capacitor <NUM> with the second resistor <NUM> produces a lower impedance (R/<NUM> ∥ XC) than the impedance of a combination of the parasitic capacitor <NUM> with a resistor that matches the characteristic impedance (R ∥ XC). The parallel configuration of the second resistor <NUM> and the parasitic capacitor <NUM> limits the mismatch effect of the parasitic capacitor <NUM> on the termination impedance (Rterm). The termination impedance may be calculated as: <MAT>.

<FIG> includes an example of a transmitter terminating circuit <NUM> configured in accordance with certain aspects of this disclosure. An IC device <NUM> is coupled to a transmission line <NUM> through the transmitter terminating circuit <NUM>. The transmission line <NUM> may provide a single ended lane of a serial bus or parallel bus. The transmitter terminating circuit <NUM> has a first resistor <NUM> and a second resistor <NUM> that are coupled at a center point <NUM> of the transmitter terminating circuit <NUM>.

In the illustrated example, the first resistor <NUM> is physically located outside the IC device <NUM> and is configured to couple an I/O pad <NUM> of the IC device <NUM> to the transmission line <NUM>. In some examples, the first resistor <NUM> is provided on a chip carrier, printed circuit board or a substrate that carries the IC device <NUM>. The center point <NUM> of the transmitter terminating circuit <NUM> lies within the IC device <NUM> and is coupled to the I/O pad <NUM> and to the first resistor <NUM> through the I/O pad <NUM>. The center point <NUM> is further coupled to the output of a line driver.

The first resistor <NUM> and the second resistor <NUM> are connected in series and the combination terminates the transmission line <NUM> through a combined resistance of R. The resistance values of the first resistor <NUM> and the second resistor <NUM> are selected to match the nominal value of the characteristic impedance (Z<NUM>) of the transmission line <NUM>. In some examples, the first resistor <NUM> and the second resistor <NUM> that have equal resistance values (R/<NUM>), where R = Z<NUM>.

A parasitic capacitor <NUM> is represented as being coupled to the center point <NUM> of the series-connected first resistor <NUM> and second resistor <NUM>. The parasitic capacitor <NUM> may account for a parasitic capacitance associated with, or resulting from the structure of the I/O pad <NUM> and connectors coupled to the I/O pad <NUM> or the center point <NUM>. The parasitic capacitance may also include parasitic capacitances of a line driver coupled to the I/O pad <NUM> or center point <NUM>.

The configuration of the transmitter terminating circuit <NUM> limits the effect of the capacitive reactance corresponding to the parasitic capacitor <NUM> with respect to a conventional line termination. The parallel arrangement of the parasitic capacitor <NUM> with the second resistor <NUM> produces a lower impedance (R/<NUM> ∥ XC) than the impedance of a combination of the parasitic capacitor <NUM> with a resistor that matches the characteristic impedance (R ∥ XC). The parallel configuration of the second resistor <NUM> and the parasitic capacitor <NUM> limits the mismatch effect of the parasitic capacitor <NUM> on the termination impedance.

The parallel configuration of the second resistor <NUM> and the parasitic capacitor <NUM> limits the mismatch effect of the parasitic capacitor <NUM> on the termination impedance (Rterm). The termination impedance may be calculated as: <MAT>.

<FIG> includes tables <NUM>, <NUM> that illustrate the effect of signaling frequency on terminating impedance and the voltage reflection coefficient (Γ) when parasitic capacitance is present at the I/O pads <NUM>, <NUM> of <FIG> or the I/O pads <NUM>, <NUM> of <FIG>. The tables <NUM>, <NUM> relate to a transmission line that has a <NUM> ohm characteristic impedance. The tables <NUM>, <NUM> may be compared and contrasted with the tables <NUM> and <NUM> provided in <FIG>.

Capacitive reactance may be calculated as <NUM>/(ω × C), where ω is the angular frequency of the signal received at the termination. The first table <NUM> relates to an interface in which the parasitic capacitance has a value of <NUM> pF and the second table <NUM> relates to an interface in which the parasitic capacitance has a value of <NUM> pF. Each table includes reactance (XC), resultant termination impedances <NUM>, <NUM> (R || XC) and reflection coefficients <NUM>, <NUM>. The reflection coefficients <NUM>, <NUM> show significant improvements over corresponding reflection coefficients provided in tables <NUM> and <NUM>, with improvements being measurable as a factor of <NUM> or more.

The improved reflection coefficients <NUM>, <NUM> reduce the reflected power on the transmission line <NUM>, <NUM>, <NUM>. Furthermore, each pair of the resistors <NUM> and <NUM>, <NUM> and <NUM>, <NUM> and <NUM>, <NUM> and <NUM> is configured as a voltage divider from the perspective of the respective I/O pads <NUM>, <NUM>, <NUM>, <NUM>. The effect of the voltage dividers is to halve the amplitude of the reflections that originate at the I/O pads <NUM>, <NUM>, <NUM>, <NUM>. Reflections emanating from the I/O pads <NUM>, <NUM>, <NUM>, <NUM> are further reduced in amplitude due to the voltage dividing effect of the impedance of the transmission line <NUM>, <NUM>, <NUM> and by the first resistor <NUM>, <NUM>, <NUM>, <NUM>. Reflected signals arriving at the transmitter I/O pad <NUM>, <NUM> are further attenuated by a voltage divider and reflected at half the amplitude of the received reflected signals. In some instances, the voltage dividers operate to quickly suppress reflected energy on the transmission line <NUM>, <NUM>, <NUM>.

The suppression of reflected energy and improved reflection coefficients <NUM>, <NUM> can eliminate or minimize the resonance effects that result from multiply-reflected waveforms. The frequency response of the presently disclosed terminating circuits <NUM>, <NUM> may approach linearity, including at frequencies of <NUM> or more. The linearity or near-linearity of the frequency response enables conventional equalizers to obtain optimal equalization. In some instances, the receiver terminating circuit <NUM> can linearize the frequency response of the channel to a variable signal frequency and the receiver terminating circuit <NUM> may be used with a CTLE or other equalizer. In one example, the CTLE may be coupled to the I/O pad <NUM> at the receiver when the configuration of the resistors <NUM>, <NUM> provide a linearized frequency response to signals received at the I/O pad <NUM>.

Benefits may be accrued from the use of the terminating circuits <NUM>, <NUM> in differential communication links. <FIG> illustrates a two-wire differential link <NUM> adapted in accordance with the scope of the claims. In the two-wire differential link <NUM>, a signal is transmitted in opposite-polarity versions on two physically-close wires. Each wire may be characterized as a transmission line <NUM>, <NUM>. In the illustrated example, a first transmission line <NUM> is terminated by a pair of terminating resistors (RS <NUM>) at the transmitting end and by a pair of terminating resistors <NUM>, <NUM> at the receiving end. At the transmitting end, the terminating resistors provide a combined resistance that matches the nominal value of the characteristic impedance of the first transmission line <NUM>. At the receiving end, the terminating resistors <NUM>, <NUM> provide a combined resistance that matches the nominal value of the characteristic impedance of the first transmission line <NUM>. A second transmission line <NUM> is terminated by a pair of terminating resistors (RS <NUM>) at the transmitting end and by a pair of terminating resistors <NUM>, <NUM> at the receiving end. At the transmitting end, the terminating resistors provide a combined resistance that matches the nominal value of the characteristic impedance of the second transmission line <NUM>. At the receiving end, the terminating resistors <NUM>, <NUM> provide a combined resistance that matches the nominal value of the characteristic impedance of the second transmission line <NUM>. Each of the I/O pads 1530b, 1530d at the receiving end is coupled to an input of a differential receiver <NUM>. At the receiving end, the pair of terminating resistors <NUM>, <NUM> for the first transmission line <NUM> and the pair of terminating resistors <NUM>, <NUM> for the second transmission line <NUM> are coupled a common capacitor <NUM> configured to couple AC components to circuit ground. The point at which the pair of terminating resistors <NUM>, <NUM> for the first transmission line <NUM> and the pair of terminating resistors <NUM>, <NUM> for the second transmission line <NUM> are coupled provides a common mode voltage level.

The resistors in each pair of terminating resistors are coupled to one another at an I/O pad 1530a-1530d of a transmitting or receiving device. In one example, each of the terminating resistors has a resistance equal to about half the nominal value of the characteristic impedance of the transmission line <NUM>, <NUM>. Parasitic capacitances <NUM>, <NUM>, <NUM>, <NUM> are represented as capacitors coupled to the I/O pads 1530a-1530d, which are also coupled at the center point of a pair of terminating resistors. Two terminating resistors are coupled to one another at each I/O pad 1530a-1530d. In one example, the terminating resistors each have a resistance equal to about half the nominal value of the characteristic impedance of the transmission lines <NUM>, <NUM>.

<FIG> also illustrates a three-wire differential link <NUM>, which may be used in a C-PHY interface, and which is adapted in accordance with certain aspects of this disclosure. In the C-PHY interface, a three-phase signal is transmitted in different phases on each of three wires. Each wire may be characterized as a transmission line 1546a, 1546b, 1546c. A set of switched resistors <NUM> in the transmitter and two sets of resistors <NUM>, <NUM> in the receiver are used to terminate respective transmission lines 1546a, 1546b, 1546c consistent with the terminating circuits <NUM>, <NUM> illustrated in <FIG>. For example, the resistors in the two sets of resistors <NUM>, <NUM> are configured as voltage dividers that can attenuate reflections on the transmission lines 1546a, 1546b, 1546c including reflections from the I/O pads <NUM> that may be attributable to the effect of parasitic capacitances, for example. In a C-PHY interface, zero net current is transmitted to the receiver and one end of each resistor in the set of resistors <NUM> is coupled to a common capacitor <NUM> that can shunt transients to circuit ground. Direct coupling to circuit ground is not required since received current and return currents are expected to cancel.

<FIG> is a diagram illustrating an example of a hardware implementation for an apparatus <NUM>. In some examples, the apparatus <NUM> may perform one or more functions disclosed herein. In accordance with various aspects of the disclosure, an element, or any portion of an element, or any combination of elements as disclosed herein may be implemented using a processing circuit <NUM>. The processing circuit <NUM> may include one or more processors <NUM> that are controlled by some combination of hardware and software modules. Examples of processors <NUM> include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. The one or more processors <NUM> may include specialized processors that perform specific functions, and that may be configured, augmented or controlled by one of the software modules <NUM>. The one or more processors <NUM> may be configured through a combination of software modules <NUM> loaded during initialization, and further configured by loading or unloading one or more software modules <NUM> during operation.

In the illustrated example, the processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The bus <NUM> links together various circuits including the one or more processors <NUM>, and storage <NUM>. Storage <NUM> may include memory devices and mass storage devices and may be referred to herein as computer-readable media and/or processor-readable media. The bus <NUM> may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A bus interface <NUM> may provide an interface between the bus <NUM> and one or more transceivers 1612a, 1612b. A transceiver 1612a, 1612b may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in a transceiver 1612a, 1612b. Each transceiver 1612a, 1612b provides a means for communicating with various other apparatus over a transmission medium. In one example, a transceiver 1612a may be used to couple the apparatus <NUM> to a multi-wire bus. In another example, a transceiver 1612b may be used to connect the apparatus <NUM> to a radio access network. Depending upon the nature of the apparatus <NUM>, a user interface <NUM> (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and may be communicatively coupled to the bus <NUM> directly or through the bus interface <NUM>.

One or more processors <NUM> in the processing circuit <NUM> may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the storage <NUM> or in an external computer-readable medium. The external computer-readable medium and/or storage <NUM> may include a non-transitory computer-readable medium. A non-transitory computer-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a "flash drive," a card, a stick, or a key drive), RAM, ROM, a programmable read-only memory (PROM), an erasable PROM (EPROM) including EEPROM, a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The computer-readable medium and/or storage <NUM> may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. The computer-readable medium and/or the storage <NUM> may reside in the processing circuit <NUM>, in the processor <NUM>, external to the processing circuit <NUM>, or be distributed across multiple entities including the processing circuit <NUM>. The computer-readable medium and/or storage <NUM> may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

The storage <NUM> may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules <NUM>. Each of the software modules <NUM> may include instructions and data that, when installed or loaded on the processing circuit <NUM> and executed by the one or more processors <NUM>, contribute to a run-time image <NUM> that controls the operation of the one or more processors <NUM>. When executed, certain instructions may cause the processing circuit <NUM> to perform functions in accordance with certain methods, algorithms and processes described herein.

Some of the software modules <NUM> may be loaded during initialization of the processing circuit <NUM>, and these software modules <NUM> may configure the processing circuit <NUM> to enable performance of the various functions disclosed herein. For example, some software modules <NUM> may configure internal devices and/or logic circuits <NUM> of the processor <NUM> and may manage access to external devices such as a transceiver 1612a, 1612b, the bus interface <NUM>, the user interface <NUM>, timers, mathematical coprocessors, and so on. The software modules <NUM> may include a control program and/or an operating system that interacts with interrupt handlers and device drivers, and that controls access to various resources provided by the processing circuit <NUM>. The resources may include memory, processing time, access to a transceiver 1612a, 1612b, the user interface <NUM>, and so on.

The one or more processors <NUM> may additionally be adapted to manage background tasks initiated in response to inputs from the user interface <NUM>, the transceiver 1612a, 1612b, and device drivers, for example.

<FIG> is a flowchart <NUM> of a method of configuring a coupling between a device and a transmission line. At block <NUM>, a first terminal of a first resistor may be coupled to an end of a first transmission line. At block <NUM>, a second terminal of the first resistor may be coupled to a first I/O pad. A first terminal of a second resistor is coupled to the first I/O pad. The first resistor and the second resistor may be selected to provide a combined resistance that matches a nominal value of a characteristic impedance of the first transmission line.

In one example, an input of a receiving circuit is coupled to the first I/O pad. A second terminal of the second resistor may be coupled to circuit ground or a common mode voltage level or low-impedance rail. In another example, an output of a line driving circuit is coupled to the second terminal of the second resistor.

In certain examples, the second resistor and the first I/O pad are provided on an integrated circuit device. The first resistor and the end of the first transmission line may be located external to the integrated circuit device. Parasitic capacitance in the integrated circuit device may be measurable or manifest at the first I/O pad and the second resistor may be effectively coupled in parallel with the parasitic capacitance observed at the first I/O pad.

In certain examples, the first resistor and the second resistor form a voltage divider with the first I/O pad at the output or center of the voltage divider. Signals received at the first input/output pad may be attenuated representations of signals received at the end of the first transmission line. Reflections from the first I/O pad that are conducted to the end of the first transmission line are attenuated by the first resistor.

In certain examples, a first terminal of a third resistor is coupled to an end of a second transmission line, and a second terminal of the third resistor is coupled to a second I/O pad. A first terminal of a fourth resistor is coupled to the second I/O pad and a second terminal of the fourth resistor is coupled to a second terminal of the third resistor. The third resistor and the fourth resistor may be selected to provide a combined resistance that matches the nominal value of the characteristic impedance of the second transmission line. The first I/O pad and the second I/O pad are coupled to differential inputs of a receiver circuit. The first I/O pad and the second I/O pad are coupled through corresponding resistors to differential outputs of a driving circuit.

<FIG> is a diagram illustrating a simplified example of a hardware implementation for an apparatus <NUM> employing a processing circuit <NUM>. The processing circuit typically has a controller or processor <NUM> that may include one or more microprocessors, microcontrollers, digital signal processors, sequencers and/or state machines. The processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The bus <NUM> links together various circuits including one or more processors and/or hardware modules, represented by the controller or processor <NUM>, the modules or circuits <NUM>, <NUM> and <NUM> and the processor-readable storage medium <NUM>. One or more physical layer circuits and/or modules <NUM> may be provided to support communication over a communication link implemented using a multi-wire bus <NUM>, through an antenna or antenna array <NUM> (to a radio access network for example), and so on. The bus <NUM> may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The processor <NUM> is responsible for general processing, including the execution of software, code and/or instructions stored on the processor-readable storage medium <NUM>. The processor-readable storage medium <NUM> may include a non-transitory storage medium. The software, when executed by the processor <NUM>, causes the processing circuit <NUM> to perform the various functions described supra for any particular apparatus. The processor-readable storage medium <NUM> may be used for storing data that is manipulated by the processor <NUM> when executing software. The processing circuit <NUM> further includes at least one of the modules <NUM>, <NUM> and <NUM>. The modules <NUM>, <NUM> and <NUM> may be software modules running in the processor <NUM>, resident/stored in the processor-readable storage medium <NUM>, one or more hardware modules coupled to the processor <NUM>, or some combination thereof. The modules <NUM>, <NUM> and <NUM> may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

In one configuration, the apparatus <NUM> includes modules and/or circuits <NUM> adapted to encode data in signals to be transmitted over a transmission line and/or to decode data from signals received from the transmission line, and modules and/or circuits <NUM> configured to equalize signals received from the transmission line. The apparatus <NUM> may include line termination modules and/or circuits <NUM>.

In some examples, portions of the line termination modules and/or circuits <NUM> may be included in physical layer circuits and/or modules <NUM> that implement an interface circuit adapted to couple the apparatus <NUM> to a serial bus. The apparatus <NUM> may have a first resistor having a first terminal coupled to an end of a first transmission line, and a second terminal coupled to a first I/O pad, and a second resistor having a first terminal coupled to the first I/O pad. The first resistor and the second resistor may be selected to provide a combined resistance that matches a nominal value of a characteristic impedance of the first transmission line. In one example, the apparatus <NUM> includes a receiving circuit having an input coupled to the first I/O pad. A second terminal of the second resistor may be coupled to circuit ground or a common mode voltage level. In another example, the apparatus <NUM> may include a line driving circuit having an output coupled to the second terminal of the second resistor.

In certain examples, the second resistor and the first I/O pad are provided on an IC device. The first resistor and the end of the first transmission line may be located external to the IC device. Parasitic capacitance in the integrated circuit device may be measurable or manifest at the first I/O pad and the second resistor may be effectively coupled in parallel with the parasitic capacitance observed at the first I/O pad.

In certain examples, the first resistor and the second resistor form a voltage divider with the first I/O pad at the center of the voltage divider. Signals received at the first I/O pad are attenuated representations of signals received at the end of the first transmission line. Reflections from the first I/O pad and conducted to the end of the first transmission line are attenuated by the first resistor.

In some examples, the apparatus <NUM> includes a CTLE coupled to the first I/O pad. The first resistor and the second resistor may be configured as a frequency response linearizing terminating circuit.

In some examples, the apparatus <NUM> includes a third resistor having a first terminal coupled to an end of a second transmission line, and a second terminal coupled to a second I/O pad and a fourth resistor having a first terminal coupled to the second I/O pad and a second terminal coupled to a second terminal of the second resistor. The third resistor and the fourth resistor may be selected to provide a combined resistance that matches the nominal value of the characteristic impedance of the second transmission line. In one example, the first I/O pad and the second I/O pad are coupled to differential inputs of a receiver circuit. In another example, the first I/O pad and the second I/O pad are coupled through corresponding resistors to differential outputs of a driving circuit.

In some examples, the apparatus <NUM> is included in a system that has a data communication link, a first IC device coupled to a first end of the data communication link through a first terminating circuit and a second integrated circuit device coupled to a second end of the data communication link through a second terminating circuit. The first terminating circuit may include a first resistor having a first terminal coupled to a first end of a first transmission line in the data communication link, and a second terminal coupled to a first I/O pad. The first terminating circuit may include a second resistor having a first terminal coupled to the first I/O pad and a receiving circuit having a first input coupled to the first I/O pad. A second terminal of the second resistor may be coupled to circuit ground or a common mode voltage level. The resistor and the second resistor may be selected to provide a combined resistance that matches a nominal value of a characteristic impedance of the first transmission line.

In one example, the second resistor and the first I/O pad are provided on the first IC device. The first resistor and the first end of the first transmission line may be located external to the first integrated circuit device. Parasitic capacitance in the integrated circuit device may be measurable or manifest at the first I/O pad and the second resistor may be effectively coupled in parallel with the parasitic capacitance observed at the first I/O pad.

In some examples, the first resistor and the second resistor form a voltage divider with the first I/O pad at the center of the voltage divider. Signals received at the first I/O pad are attenuated representations of signals received at the first end of the first transmission line. Reflections from the first I/O pad that are conducted to the first end of the first transmission line may be attenuated through the first resistor.

In one example, a CTLE equalizer is coupled to the first I/O pad. The first resistor and the second resistor may be configured as a frequency response linearizing terminating circuit.

In one example, the data communication link includes a second transmission line. The first terminating circuit may include a third resistor having a first terminal coupled to an end of the second transmission line and a second terminal coupled to a second I/O pad. The first terminating circuit may include a fourth resistor having a first terminal coupled to the second I/O pad and a second terminal coupled to a second terminal of the second resistor. The third resistor and the fourth resistor may provide a combined resistance that matches the nominal value of the characteristic impedance of the second transmission line. The first I/O pad may be coupled to a second input of the receiver circuit. The receiving circuit may include or operate as a differential receiver.

In one example, the second terminating circuit includes a fifth resistor having a first terminal coupled to a second end of the first transmission line, and a second terminal coupled to a third I/O pad. The second terminating circuit may include a sixth resistor having a first terminal coupled to the third I/O pad, and a line driving circuit having an output coupled to the second terminal of the sixth resistor. The fifth resistor and the sixth resistor may provide a combined resistance that matches a nominal value of a characteristic impedance of the first transmission line. The line driving circuit may include or operate as a differential line driver.

It is understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. The accompanying method claims present elements of the various steps in a sample order and are not meant to be limited to the specific order or hierarchy presented.

Claim 1:
An apparatus comprising:
a first input/output pad (<NUM>, 1530b);
a first resistor (<NUM>, <NUM>) having a first terminal coupled to an end of a first transmission line (<NUM>, <NUM>), and a second terminal coupled to the first input/output pad (<NUM>, 1530b);
a second resistor (<NUM>, <NUM>) having a first terminal coupled to the first input/output pad,
wherein the first resistor and the second resistor are configured to provide a combined resistance that matches a nominal value of a characteristic impedance of the first transmission line;
a receiving circuit (<NUM>) having an input coupled to the first input/output pad, wherein a second terminal of the second resistor is coupled to circuit ground or a common mode voltage level.