Patent Description:
Emerging applications, such as cloud computing, artificial intelligence, and machine learning, are driving demand for faster and faster data processing. With the increasing number of cores per socket running at higher clock frequencies, and the aid of accelerators, such as graphic processing units (GPU's), field-programmable gate arrays (FPGA's), data processing units (DPU's), etc., processor speed, and/or the number of active threads per socket, has been doubling every two years. The increasing processor power places increasing demand on memory capacity and memory speed or bandwidth, which unfortunately do not increase at the same rate. Often, higher memory speed means lower memory capacity, and, as memory capacity increases to keep up with the increase in processor speed, memory latency, which is a measure of how long it takes to complete a memory operation, is also increasing at a rate of about <NUM> times every two years. Thus, solving the problem of memory capacity and bandwidth gaps is critical in the performance of data processing systems.

Software-defined memory (SDM) expansion using Non-Volatile Memory Express Solid-State Drives (NVMe SSD) provides better economics but has various performance issues, such as lack of efficiency across different workloads, poor quality of predictive prefetching due to high latency, large latency penalty for page faults, and lack of efficiency in moving data into coherent host memory. <CIT> discloses a non-volatile memory express device. Wherein the device receives a non-volatile memory express (NVMe) command written into a submitted queue by a host and the command within the SQ is sent to a solid state disk (SSD) controller (HH) when a SQ control module (FF) detects change in the SQ in a SQ cache (DD). The command is executed and a generated command response is written into a completion queue (CQ) by the SSD controller. The host is informed to read the CQ by triggering interruption such that the host processes the command response within the CQ.

In some embodiments, a high density, high bandwidth, and low cost memory expansion device includes non-volatile memory (NVM, e.g., NAND Flash) as tier <NUM> memory for low-cost virtual memory capacity expansion, optional device DRAM as tier <NUM> coherent memory for physical memory capacity and bandwidth expansion, and device cache as tier <NUM> coherent memory for low latency.

In some embodiments, a memory expansion device is operable in a computer system, the computer system including a host computer (host) and a dedicated bus. The memory expansion device comprises interface circuitry configured to communicate with the host via the dedicated bus based on a predefined protocol, a non-volatile memory (NVM) subsystem, cache memory, and control logic coupled to the interface circuitry the cache memory, and the NVM subsystem. The control logic is configurable to receive a first submission from the host, the first submission including a first read command and specifying a first payload in the NVM subsystem. In response to the first submission being of first priority, the control logic is further configured to request ownership of first cache lines corresponding to the first payload, indicate completion of the first submission after acquiring ownership of the first cache lines, and load the first payload to the cache memory, the first cache lines corresponding to cache lines in a first coherent destination memory space accessible by the host.

In some embodiments, the memory expansion device is coupled to the host via a Computer Express Link (CXL) bus, wherein the interface circuitry provides a CXL interface between the control logic and the CXL bus, and wherein the first coherent destination memory space is accessible by the host using a CXL protocol.

In some embodiments, the control logic is further configured to request ownership of the first cache lines from a home agent at the host computer.

In some embodiments, the first submission further specifies demand data in the first payload. The control logic is configured to, before loading the first payload into the cache memory issue first NVM read commands to read the first payload from the NVM subsystem, the first NVM read commands being written into a command queue associated with the NVM subsystem. The control logic is further configured to prioritize reading the demand data from the NVM subsystem when issuing the first NVM read commands such that a logic block address in the NVM subsystem corresponding to a logic block including the demand data is read before logic block addresses corresponding to other logic blocks in the payload.

In some embodiments, the control logic is configured to indicate completion of the first submission before determining that the first payload has been loaded in the cache memory.

In some embodiments, the control logic is further configured to, after indicating completion of the first submission and in response to a memory read request from the host to read demand data in the payload, determine whether the demand data has been loaded in the cache memory, and in response to the demand data having been loaded in the cache memory, return the demand data from the cache memory.

In some embodiments, the control logic is further configured to, after returning the demand data, transfer at least an unread portion of the first payload, to corresponding cache lines in the first cache lines.

In some embodiments, the memory expansion device further comprises device memory providing the first coherent destination memory space.

The memory expansion device of claim <NUM>, wherein the first cache lines correspond to address ranges in a host memory and the rest of first payload, is transferred to the host via the interface circuitry.

In some embodiments, the control logic is further configured to receive a second submission from the host, the second submission including a second read command and specifying a second payload in the NVM subsystem, in response to the second submission being of second priority, load the second payload into a second coherent destination memory space or corresponding to the second payload, and indicate completion of the second submission after the second payload has been loaded into the second coherent destination memory space.

In some embodiments, the control logic is configured to issue first NVM read commands to read the first payload from the NVM subsystem before loading the first payload into the cache memory and to issue second NVM read commands to read the second payload from the NVM subsystem before loading the second payload into the second coherent destination memory space. In some embodiments, the first NVM read commands are written into a first command queue associated with the NVM subsystem, and the second NVM read commands are written into a second command queue associated with the NVM subsystem, the first command queue being of higher priority than the second command queue.

In some embodiments, the memory expansion device further comprises a controller memory buffer (CMB) including submission queues, accessible by the host, the submission queues including at least a first submission queue for queuing submissions of the first priority and at least a second submission queue for queuing submissions of the second priority, wherein the first submission is queued in the first submission queue, and the second submission is queued in the second submission queue.

In some embodiments, the memory expansion device further comprises device memory coupled to the control logic, wherein the CMB occupies designated memory locations in the device memory. In some embodiments, the cache memory includes a CMB cache that is synchronized with the CMB and includes mirrored submission queues corresponding, respectively, to the submission queues in the CMB, and the control logic is further configured to synchronize the CMB cache with the CMB.

In some embodiments, the control logic is configured to maintain selected portions of the CMB memory space in a shared state, so that in response to a cache line of the selected portions being modified by the host causing a shared state corresponding to the cache line being invalidated, the control logic is configured to re-acquire the cache line to reinstate its shared state.

In some embodiments, the control logic further includes a coherent NVM express (cNVMe) controller configured to read the first submission in the first mirrored submission queue in the cache memory in response to the value being written into the register, and to control transferring of the first payload into the cache memory. In some embodiments, the control logic is configured to indicate completion of a submission by writing into a completion queue of the CMB and updating a pointer associated with the completion queue.

In some embodiments, the control logic is further configured to receive the second submission from the host by reading the second submission that has been written into a second submission queue of the one or more submission queues by the host. In some embodiments, the control logic is further configured to determine the first submission being of the first priority based on the first submission having been written into the first submission queue by the host, and to determine the second submission being of the second priority based on the second submission having been written into the second submission queue by the host.

In some embodiments, the memory expansion device further comprises local memory coupled to the control logic, wherein one or both of the first coherent destination memory space and the second coherent destination memory space is provided by the device memory.

In some embodiments, in response to the submission being of the second priority and including one or more hints, the control logic is configured to prepare the second cache lines using the one or more hints. In some embodiments, in response to the submission being of the second priority and including one or more hints, the control logic is configured to write the payload into the second cache lines using the one or more hints.

In some embodiments, the control logic is further configured to receive a third submission from the host, the third submission including a third read command and specifying a third payload. In response to the third submission being of a third priority lower than the second priority, the control logic is further configured to determine whether to fetch the third payload based on predefined criteria, and in response to the determination that the third payload is to be fetched, fetch the third payload, and load the third payload into a private memory space that is hidden from the CPU. In some embodiments, the control logic is further configured to indicate completion of the third submission whether or not it is determined that the third payload is to be fetched based on the predetermined criteria.

In some embodiments, the private memory space is provided by the local memory and is distinct from the first coherent destination memory space and from the second coherent destination memory space.

In some embodiments, the control logic is configured to before loading the first payload into the cache memory, determine whether the first payload has been prefetched and stored in the private memory space, and/or before loading the second payload into the second cache lines, determine whether the second payload has been prefetched and stored in the private memory space. In some embodiments, the control logic is configured to copy the first payload from the private memory space to the cache memory in response to determination that the first payload has been prefetched and stored in the private memory space, and/or copy the second payload from the private memory space to the second coherent destination memory space in response to determination that the second payload has been prefetched and stored in the private memory space. In some embodiments, the control logic is further configured to read the first payload from the NVM subsystem in response to determination that the first payload has not been prefetched and stored in the private memory space, and/or read the second payload from the NVM subsystem in response to determination that the second payload has not been prefetched and stored in the private memory space.

In some embodiments, the local memory includes double data rate (DDR) dynamic random access memory (DRAM).

In some embodiments, the memory expansion device further comprises a controller memory buffer (CMB) accessible by the host, the CMB including submission queues. The control logic is configured to determine the first submission being of the first priority based on the first submission having been written into a first submission queue for queuing submissions of the first priority, determine the second submission being of the second priority based on the second submission having been written into a second submission queue for queuing submissions of the second priority, and determine the third submission being of the third priority based on the third submission having been written into a third submission queue for queuing submissions of the third priority.

In some embodiments, the control logic includes logic circuitry on an integrated circuit chip. In some embodiments, the cache memory includes static random access memory (SRAM) on the integrated circuit chip. In some embodiments, the cache memory includes high bandwidth memory (HBM) coupled to the integrated circuit chip.

In some embodiments, a memory expansion device is operable in a computer system, the computer system including a host computer (host) and a dedicated bus. The memory expansion device comprises interface circuitry configured to communicate with the host via the dedicated bus based on a predefined protocol, a non-volatile memory (NVM) subsystem, local memory providing a coherent memory space accessible by the host, cache memory, and control logic coupled to the interface circuitry the cache memory, and the NVM subsystem. The control logic is configurable to:.

In some embodiments, the control logic is configured to indicate completion of the submission before determining that the demand data has been loaded in the cache memory.

In some embodiments, a method comprises, at a memory expansion device coupled to a host computer (host) via a dedicated bus, the memory expansion device comprising interface circuitry configured to communicate with the host via the dedicated bus based on a predefined protocol, a non-volatile memory (NVM) subsystem, local memory providing a coherent memory space accessible by the host, cache memory, and control logic coupled to the interface circuitry the cache memory, and the NVM subsystem:.

In some embodiments, the completion of the submission is indicated before determining that the demand data has been loaded in the cache memory.

Thus, in some embodiment, a Computer Express Link (CXL) memory expansion device optimizes a Software-Defined Memory (SDM) communication layer by using an NVMe baseline communication layer to minimize software development/porting effort, while providing new mechanisms for SDM virtual memory management, including SDM predictive algorithms, SDM data migration and coherent cache management, and SDM quality of service (QoS). In some embodiments, the CXL memory expansion device also optimizes data pipelines to minimize critical latencies, resulting in improved page fault recovery time and improved NVM read latency.

In some embodiments, the CXL memory expansion device uses CXL coherency protocols to implement coherent hybrid data transfers, and supports direct cache-to-cache transfers between a host cache and the device cache. Caching is managed by the SDM software to improve the predictive behavior of the SDM software. The optional device DRAM appears as additional coherent host memory accessible by the host processor (or CPU). In some embodiments, the CXL memory further includes control logic configurable to control data transfers in/out of various memory resources in a computer system.

In some embodiments, the memory expansion device supports NVMe extensions, such as central NVMe express (cNVMex) extension, which is a proprietary extension to the NVMe protocol that tightly couples coherent host memory with NVM prefetch hints. This allows the SDM to influence data and cache management across memory tiers, reduces prefetch loaded latency, and improves the quality and effectiveness of SDM predictive algorithms. It also provides QoS for coherent memory transfers, where the SDM software indicates data priority, and a cDMA engine optimizes cache line access patterns. As a result, low priority data is retained in device memory tiers, medium priority data is transferred to host memory or device DRAM without overloading the CPU data/coherency fabric, and high priority demand data is transferred cache-to-cache, providing improved performance.

The present embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:.

<FIG> is a block diagram of computer system <NUM> including a host computer (or host) <NUM> and a coherent memory expansion device (CMX device) <NUM> coupled to the host via a dedicated bus <NUM> (e.g., a CXL bus), via which the CPU <NUM> accesses the memory expansion device <NUM>, in accordance with some embodiments. As shown, host <NUM> includes one or more central processing units (CPU) <NUM> (which includes one or more CPU cache <NUM>), and may further include host memory <NUM>, e.g., double data rate (DDR) dynamic random access memory (DRAM), coupled to the CPU <NUM> via a system bus <NUM>. The host <NUM> may further include storage devices <NUM> (e.g., Serial Advanced Technology Attachment or SATA drive(s) and/or NVMe SSD) coupled to the CPU via, for example, one or more Peripheral Component Interconnect express or PCIe links <NUM>.

As shown in <FIG>, the CMX device <NUM> includes a coherent memory expansion controller (CMXC) <NUM> (which includes cache memory or device cache <NUM>), and may further include or has access to local memory <NUM> (e.g., DDR DRAM), and/or non-volatile memory (NVM) <NUM> (e.g., NAND Flash memory). <FIG> also shows that CMXC <NUM> includes a bus interface <NUM> configured to interface with the host via the dedicated bus <NUM>, and control logic (e.g., logic circuitry) <NUM> coupled to the bus interface <NUM> and configurable to control communication of commands (or requests) and data between the CPU and local memory <NUM>, and between local memory <NUM> and NVM <NUM>, and to maintain coherency of the device cache <NUM> and other caches (e.g., CPU cache <NUM>) in the computer system <NUM>, and the coherency of a memory space mapped to at least part of the local memory <NUM>. Herein, "coherency" or "coherent" may mean uniformity of shared resource data that may end up being stored in different caches. CMXC may <NUM> further include a memory controller (e.g., a DDR memory controller) configured to interface between the control logic <NUM> and the device DRAM <NUM>, and/or an NVM media controller128 configured to interface between the control logic <NUM> and the NVM <NUM>.

In some embodiments, CMXC <NUM> can be implemented in an Application Specific Integrated Circuit (ASIC) chip, and device cache <NUM> includes Static Random Access Memory (SRAM) on the ASIC chip. In some embodiments, CMX device <NUM> further includes a circuit board <NUM> (e.g., a printed circuit board or PCB) having a connector <NUM> including edge connections that can be inserted into an expansion slot (not shown) of the computer system <NUM> to provide electrical connections between the bus interface <NUM> with the dedicated bus <NUM>. In some embodiments, the CMXC <NUM>, the NVM <NUM>, and the DRAM are mounted on the circuit board <NUM>, and coupled with each other and to connector <NUM> via conducting wires in and/or on the circuit board.

<FIG> illustrates a software-defined memory (SDM) map <NUM> in accordance with some embodiments. As shown in <FIG>, SDM software <NUM> running on the CPU <NUM> pools various memory and/or storage resources in the computer system <NUM> together and presents them as a virtual memory space <NUM> accessible by Uniform Memory Access (UMA) applications running on the CPU <NUM>. Part of virtual memory space <NUM> is mapped to a physical memory space <NUM> associated with the SATA and/or a physical memory space <NUM> associated with the NVME SSD through host memory <NUM>, while another part of the virtual memory space <NUM> is mapped to a physical memory space <NUM> associated with NVM <NUM> through local memory <NUM> (and/or cache memory <NUM>). For example, the NVM <NUM> may correspond to a <NUM> terabyte (TB) or <NUM> TB virtual memory space that is managed by the SDM software <NUM>, and data can be moved between the NVM <NUM> and local memory <NUM> or the host memory <NUM> under the control of the control logic <NUM>, as discussed below.

<FIG> is a schematic diagram of memory expansion controller <NUM> in accordance with some embodiments. As shown, in some embodiments, the dedicated bus <NUM> is a Computer Express Link (CXL) bus <NUM> and CMX device <NUM> is implemented as a CXL memory expansion device or a CXL card to be inserted into a CXL expansion slot of the computer system <NUM>. Compute Express Link™ (CXL™) is an industry-supported Cache-Coherent Interconnect for Processors, Memory Expansion and Accelerators. CXL technology provides a link level data transport mechanism while maintaining memory coherency between a central processing unit (CPU) memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. This permits users to simply focus on target workloads as opposed to the redundant memory management hardware in their accelerators. CXL bus <NUM> is a high-speed CPU-to-device and CPU-to-memory interconnect or link based on the CXL protocol, including sub-protocols CXL. cache and CXL. memory, which can be used concurrently. io is backward compatible with Peripheral Component Interconnect Express (PCIe) Interface Standard Gen <NUM>. cache connects a host CPU (e.g., CPU <NUM>) to cached memory (e.g., demand read cache 327B) in external processing devices such as the CXL card <NUM> and/or other types of accelerators, dedicated storage processors, etc. It can also be used to link computational storage devices to a host server. mem enables a host CPU (e.g., CPU <NUM>) to the memory resources on the CXL card <NUM>.

As shown in <FIG>, in some embodiments, bus interface <NUM> is configured to interface with the CXL bus <NUM> and includes a physical layer <NUM>, e.g., CXL physical layer, and a protocol layer <NUM>, which is configured to communicate with the host <NUM> via the CXL bus <NUM> via a CXL protocol, and which includes a set of interfaces corresponding, respectively, to a set of sub-protocols, e.g., CXL. cache, and CXL. mem, as specified in the CXL Specification <NUM> Evaluation Copy and CXL <NUM> Errata, which are accessible at https://www. computeexpresslink.

As shown in <FIG>, control logic <NUM> in CMXC <NUM> includes a CXL bridge <NUM>, a device coherency engine (DCOH) <NUM>, a bias table <NUM>, a snooping unit <NUM>, one or more cache controllers <NUM>, a direct memory access (DMA) channel <NUM> including one or more DMA engines, and a coherent NVMe (cNVMe) controller <NUM>. As also shown in <FIG>, cache memory <NUM> may include a controller memory buffer (CMB) cache 327A and a demand read cache 327B, local memory <NUM> may include one or more DRAM modules or units, e.g., DRAM modules 130A, 130B, memory controller <NUM> may include one or more memory controllers, e.g., memory controllers 336A, 336B, coupled, respectively, to the one or more DRAM modules 130A, 130B, and NVM media controller <NUM> may include or is coupled to associated NVM command queues <NUM>. In some embodiments, the combination of NVM media controller <NUM>, its associated NVM command queues <NUM> and NVM <NUM> is sometimes referred to herein as an NVM subsystem <NUM>.

In some embodiments, as shown in <FIG>, CXL bridge <NUM>, device coherency engine (DCOH) <NUM>, bias table <NUM>, snooping unit <NUM>, and cache controller(s) <NUM> are embedded in a coherent interconnect fabric (CIF) <NUM> of the computer system <NUM>, and communicate with each other and with other caching agents (e.g., a home agent for the host) using a cache coherence protocol, so as to maintain coherency of cache memory <NUM> and at least part of local memory <NUM>, and other caches and memories such as caches <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n of one or more processor cores <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n in the CPU, and the system memory <NUM>.

In some embodiments, CXL bridge <NUM> includes a requesting and caching agent configured to handle CXL credit management and to perform conversions between the low latency CXL protocol of the CXL protocol layer <NUM> and the cache coherence protocol of the CIF <NUM>. In some embodiments, DCOH <NUM> is configured to provide a Point of Coherency and Point of Serialization for the CIF <NUM> so that, for any given access by the host to the memory resources on the CMX device <NUM>, the DCOH <NUM> is configured to resolve a state of each caching agent on the CIF and to maintain a consistent view of the memory. In some embodiments, if multiple agents are trying to access the same cache line, DCOH <NUM> is configured to serialize the accesses to ensure that only one access is allowed at a time and coherency is maintained for each access.

In some embodiments, a processor core <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n may access physical memory by paging (e.g., having a page moved in and out of memory), where a page is the smallest partition of memory mapped by the processor from a virtual address to a physical address and may include multiple cache lines. In some embodiments, bias table <NUM> is configured to maintain a page-level granularity tracker that tracks whether the host <NUM> owns one or more cache lines of a page. In some embodiments, the DCOH <NUM> is further configured to snoop a caching agent in the CIF <NUM> for a cache line that it has not acquired, and the snooping unit <NUM> includes snoop filters configured to track which caching agents have acquired which cache lines in a coherent memory space. The snooping unit <NUM> may include a remote snoop filter configured to track which cache lines are owned by the host <NUM>, and a local snoop filter configured to track which cache lines are owned by a caching agent (e.g., the cache memory <NUM> via the cache controller(s) <NUM>) on the CMX device <NUM>.

In some embodiments, CMX device <NUM> allows the host <NUM> to access its storage resources (e.g., NVM <NUM>) and presents them as memory using, for example, the Non-Volatile Memory (NVM) Express Protocol (NVMe) protocol to simplify adoption by SDM software developers. NVM Express (NVMe) is an interface that allows host software to communicate with a non-volatile memory subsystem. The current NVMe Specification Version, i.e., NVMe <NUM>. 4a Specification, which defines how host software communicates with non-volatile memory across a PCI Express® (PCIe®) bus, is available at https://nvmexpress. org/developers/nvme-specification/. In addition to the NVMe protocol, CMX device <NUM> also provides additional coherency mechanisms and allows the SDM software to include additional extensions (or hints) in host NVMe submissions. In some embodiments, the SDM software <NUM> initiates data transfers into and out of the NVM <NUM> by writing submissions into one or more submission queues in a controller memory buffer (CMB) on the CMX device <NUM>, the CMX device <NUM> indicates completion of the submissions by writing completions into one or more completion queues in the CMB.

In some embodiments, cNVMe controller <NUM> is configured to provide an interface between the CMXC <NUM> and SDM software <NUM> through NVMe queuing mechanism, to receive NVMe commands from submission queues and return NVMe completions for those commands, which are written into the completion queues, and to construct and send NVM commands to the NVM subsystem <NUM>, which are written into one or more command queues associated with the NVM subsystem <NUM>, and to receive completion status back from the NVM subsystem <NUM> through one or more completion queues associated with the NVM subsystem <NUM>. cNVMe controller <NUM> is further configured to facilitate movement of data between the NVM subsystem <NUM> and device cache <NUM> and/or local memory <NUM> using the DMA channel <NUM>.

In some embodiments, part or all of CMXC <NUM> includes an application specific integrated circuit (ASIC) die or chip, and part or all of control logic <NUM> can be implemented as logic circuitry on the chip. In some embodiments, CMB cache 127A and/or demand read cache 327B includes static random access memory (SRAM) on the chip. In some embodiments, CMB cache 127A and/or demand read cache 327B include high bandwidth memory (HBM) coupled to the ASIC chip.

<FIG> illustrates various memory spaces in computer system <NUM> in accordance with some embodiments. As shown, the memory spaces include a coherent host memory space <NUM> provided by host memory <NUM>, a coherent device memory space <NUM> provided by local memory <NUM> and a private memory space <NUM> also provided by local memory <NUM>. Memory spaces <NUM> and <NUM> are in a coherent memory space <NUM> accessible by the host <NUM>. In some embodiments, a controller memory buffer (CMB) including submission queues <NUM> and completion queues <NUM> occupies a CMB space <NUM> in the coherent device memory space <NUM>. In some embodiments, coherent memory space <NUM> includes cache lines, e.g., cache lines <NUM> and cache lines <NUM>, for storing demand and predictive data and other application data. In some embodiments, private memory space <NUM> is hidden from the host <NUM> so that it is accessible by control logic <NUM> but not by the CPU <NUM>. Private memory space <NUM> can be used to store speculative read data, as discussed further below.

<FIG> illustrates memory spaces associated with local memory <NUM> and accessible by control logic <NUM>, in accordance with some embodiments. As shown, local memory <NUM> provides the coherent device memory space <NUM> and the private memory space <NUM>. <FIG> also shows the CMB space <NUM> as including spaces corresponding to a plurality submission queues, e.g., one or more demand queues <NUM>, one or more predictive queues <NUM> and one or more speculative queues <NUM>, and one or more completion queues <NUM>. The CMB space <NUM> further includes spaces corresponding to head and tail pointers associated with each of the plurality of submission or completion queues, e.g., head pointer <NUM> and tail pointer 531T associated with demand queue <NUM>, head pointer <NUM> and tail pointer 532T associated with predictive queue <NUM>, head pointer <NUM> and tail pointer 533T associated with speculative queue <NUM>, and head pointer <NUM> and tail pointer 560T associated with one of the one or more completion queues <NUM>. In some embodiments, a head pointer associated with a queue is updated to indicate new available space in the queue, and a tail pointer associated with the queue is updated to indicate a new item is written into the queue.

<FIG> is a diagram illustrating a submission <NUM> from the host <NUM> in accordance with some embodiments. As shown, in some embodiments, the submission includes a set of data bits of a certain size (e.g., <NUM> byte) organized in a plurality of fields, including, standard fields <NUM> and customizable (or vendor specified) fields <NUM>. In some embodiments, the standard fields <NUM> include a command field for a command <NUM> (e.g., an NVMe read or write command), one or more fields for payload specification <NUM> specifying a payload <NUM> in the NVM subsystem <NUM> associated with the command, and one or more fields for memory location specification <NUM> specifying cache lines in a coherent memory space where the payload is to be transferred to or from. In some embodiments, customizable fields <NUM> include one or more fields <NUM> for communicating one or more hints that can be used to improve performance during data transfers. In some embodiments, the payload <NUM> corresponds to a plurality of logical blocks at corresponding logical block addresses (LBA-<NUM>, LBA-<NUM>,. , LBA-n) in the NVM <NUM> and can be specified by an LBA of a starting logical block (e.g., LBA-<NUM>) and a number of logical blocks n starting at the starting logical block.

In some embodiments, a submission from the host <NUM> is for a demand read (e.g., an NVM read in response to a page fault having occurred at the host <NUM>) and can specify which block among the number of logical blocks includes demand data <NUM> (e.g., data needed by the Host <NUM> to resolve the page fault). In some embodiments, an LBA size can be, for example, at least <NUM> bytes, and the least significant <NUM> bits of the starting LBA are usually zero and are therefore ignored by the NVM subsystem <NUM>. These least significant bits can be used to specify the logical block containing the demand data <NUM> so that reading the logical block from the NVM subsystem <NUM> is prioritized over reading the other logical blocks from the NVM subsystem <NUM>. For example, if the payload includes four logical blocks, using two least significant bits of the starting LBA: LBA[<NUM>:<NUM>] = <NUM> can be used to indicate that the <NUM>st Logical Block is of higher priority and is to be transferred first, followed by the others that are of lower priority; LBA[<NUM>:<NUM>] = <NUM> can be used to indicate that the 2nd Logical Block is of higher priority and is to be transferred first, followed by the others that are of lower priority; LBA[<NUM>:<NUM>] = <NUM> can be used to indicate that the 3rd Logical Block is of higher priority and is to be transferred first, followed by the others that are of lower priority; and LBA[<NUM>:<NUM>] = <NUM> can be used to indicate that the 4th Logical Block is of higher priority and is to be transferred first, followed by the others that are of lower priority.

In addition to demand read (e.g., an operation to resolve page fault at the host), CMX device <NUM> also facilitates predictive read (e.g., an operation to load a payload in a coherent memory space <NUM> or <NUM> based on prediction that the payload may be needed in a predictive time frame) and speculative read (e.g., an operation to load a payload in the private memory space <NUM> based on speculation that the payload may be needed in a speculative time frame. In some embodiments, control logic control logic <NUM> is configured to process a submission from the host <NUM> with a certain priority based on whether the submission is for demand read, predictive read, or speculative read.

In some embodiments, as shown in <FIG>, CMB cache 327A is synchronized with the CMB space <NUM> and includes one or more synchronized (or mirrored) submission queues <NUM>, <NUM>, <NUM>, corresponding, respectively, to the one or more submission queues, e.g., demand queue <NUM>, predictive queue <NUM>, speculative queue speculative queue speculative queue speculative queue <NUM>, in the CMB. In some embodiments, CMB cache 327A further includes synchronized head/tail pointers, e.g., head/tail pointers <NUM>/1231T, <NUM>/1232T, <NUM>/1233T, corresponding, respectively, to the head/tail pointers <NUM>/531T, <NUM>/532T, <NUM>/533T, in the CMB. In some embodiments, CMB cache 327A further includes one or more synchronized (or mirrored) completion queues <NUM>, and their respective head/tail pointers <NUM>/2160T, corresponding, respectively, to the one or more completion queue <NUM> and their respective head/tail pointers <NUM>/560T in the CMB.

In some embodiments, cache controller(s) <NUM> is configured to maintain selected portions of the CMB memory space in a shared state. If any cache line of the selected portions of the CMB memory space is modified by the CPU <NUM>, the shared state in the cache controller(s) <NUM> is invalidated and the cache controller(s) <NUM> would re-acquire the cache line in a shared state once again. If the data in the cache line that has been re-acquired has changed from its previous value, it is an indication the CPU has written to the cache line in a process to update a submission entry or a head or tail pointer. In some embodiments, the cNVMe controller <NUM> includes registers 322R corresponding, respectively, to the head/tail pointers in the CMB, and cache controller(s) <NUM> is further configured to alert the cNVMe controller <NUM> when a new submission is written into the CMB or mirrored in the CMB cache 327A by, for example, writing into a corresponding register 322R of the cNVMe controller <NUM>. In response, cNVMe controller <NUM> would read the NVMe submission from the CMB cache 327A and start transfers of data to or from the NVM <NUM> by, for example, issuing NVM read or write commands to the NVM subsystem <NUM>, and instructing the DMA channel <NUM> to move the data between the different memory and storage resources, in accordance with the NVMe submission. In some embodiments, cache controller(s) <NUM> is further configured to acquire ownership of cache lines requested by the cNVMe controller <NUM> and to control the demand read cache 327B, which is used to buffer demand read data, as discussed above and further below.

In some embodiments, as shown in <FIG>, the NVM queues <NUM> include one or more NVM command queues, e.g., NVM command queues <NUM>, <NUM>, <NUM>, corresponding, respectively, to the one or more submission queues, e.g., demand queue <NUM>, predictive queue <NUM>, speculative queue speculative queue <NUM>, in the CMB, or to the one or more mirrored submission queues in the CMB cache 327A. in some embodiments, NVM commands queued in NVM command queue <NUM> is processed by the NVM subsystem <NUM> with a higher priority than NVM command queued in the NVM command queue <NUM>, and NVM commands queued in NVM command queue <NUM> is processed by the NVM subsystem <NUM> with a higher priority than NVM command queued in the NVM command queue <NUM>. Thus, the cNVMe controller <NUM> can prioritize demand read over an on-going predictive read or speculative read, and prioritize predictive read over an on-going speculative read, by writing the NVM commands associated with the demand read into NVM command queue <NUM>, the NVM commands associated with the predictive read into NVM command queue <NUM>, and the NVM commands associated with the speculative read into NVM command queue <NUM>. In some embodiments, the NVM queues <NUM> further include one or more completion queues <NUM>, and the NVM subsystem <NUM> can indicate completion of an NVM read or write command by writing the completion into one of the completion queues <NUM>. As shown, NVM queues <NUM> further includes head/tail pointers <NUM>/751T, <NUM>/752T, <NUM>/753T, <NUM>/780T, associated, respectively with the NVM queues <NUM>, <NUM>, <NUM>, <NUM>.

In some embodiments, in response to a submission for demand read and specifying demand data, cNVMe controller <NUM> is further configured to prioritize transfer of the demand data from the NVM subsystem <NUM> to the demand read cache 327B over the rest of the payload. For example, cNVMe controller <NUM> may do so by writing the NVM read command corresponding to the logical block including the demand data into the NVM command queue <NUM> before writing the NVM read commands corresponding to the other logical blocks in the payload data into the NVM command queue <NUM>.

In some embodiments, control logic control logic <NUM> is configured to process a submission differently depending on whether the submission is for demand read, predictive read, or speculative read. As shown in <FIG>, in response to a first submission <NUM> for demand read, control logic <NUM> is configured to transfer a payload <NUM> specified in submission <NUM> from the NVM <NUM> to the demand read cache 327B, and to return demand data <NUM> specified in the submission <NUM> in response to a request <NUM> for the demand data from the CPU <NUM>. The request <NUM> can be, for example, in the form of a memory read command using the CXL. mem protocol. In some embodiments, control logic <NUM> is further configured to transfer at least an unread portion <NUM> of the payload <NUM> to the device memory <NUM>. Subsequent read/write operations <NUM> related to at least the portion <NUM> of the payload <NUM> can be between the CPU and the device memory <NUM> via the CXL. mem protocol.

In some embodiments, as shown in <FIG>, in response to a second submission <NUM> for predictive read, control logic <NUM> is configured to transfer a payload <NUM> specified in submission <NUM> from the NVM <NUM> to the device memory <NUM>. Subsequent read/write operations <NUM> related to the payload <NUM> can be between the CPU and the device memory <NUM> via the CXL. mem protocol.

In some embodiments, as shown in <FIG>, a physical memory space <NUM> associated with the local memory <NUM> includes a coherent memory space <NUM> accessible by the CPU <NUM> and a private memory space <NUM> hidden from the CPU <NUM>. As shown in <FIG>, the local memory <NUM> can be considered to include a memory portion (or device memory) <NUM> corresponding to the coherent memory space <NUM> and a memory portion (or private memory) <NUM> corresponding to the private memory space. In some embodiments, in response to a third submission <NUM> for speculative read, control logic <NUM> is configured to transfer a payload <NUM> specified in submission <NUM> from the NVM <NUM> to the private memory <NUM>. Subsequently, when part or all of the payload <NUM> is specified in a submission for demand read, the part or all of the payload <NUM> is transferred from the private memory <NUM> to the demand read cache 327B. When part or all of the payload <NUM> is specified in a submission for predictive read, the part of all of the payload <NUM> is transferred from the private memory <NUM> to the device memory <NUM>.

<FIG> is a flowchart illustrating quality of service (QoS) process <NUM> carried out by control logic <NUM> in response to a submission for a payload by the host <NUM> in accordance with some embodiments. As shown, QoS process <NUM> includes receiving (<NUM>) a submission (e.g., submission <NUM>) including a read command (e.g., read command <NUM>) and specifying a payload (e.g., payload <NUM>). In some embodiments, receiving (<NUM>) a submission includes the cNVMe controller <NUM> reading (<NUM>) the submission (e.g., from the CMB cache 327A) to determine the command, payload specification (e.g., starting logical block address, and number of logical blocks), and hints included in the submission. cNVMe controller <NUM> then initiates one of at least two different processes depending on a priority of the submission. In some embodiments, the priority of the submission is determined based on which submission queue the submission has been written into.

For example, if the submission is determined to be of a first priority (e.g., the submission is to resolve a page fault at the host <NUM>), a demand read process <NUM> is carried out by control logic <NUM>, and if the submission is determined to be of a second priority (e.g., the submission is to predictively fetch data from storage), a predictive read process <NUM> is carried out by control logic <NUM>. In some embodiments, CMX device <NUM> also facilitates a speculative read process <NUM> in response to the submission being of a third priority (e.g., the submission is to prefetch data based on speculation that the data might be needed in a predetermined speculative time period in the future). In some embodiments, the submission is determined to be of the first priority, the second priority, or the third priority based on whether the submission is queued in a demand queue <NUM>, a predictive queue <NUM>, or a speculative queue <NUM>.

<FIG> is a flowchart illustrating a demand read process <NUM> according to certain embodiments. As shown, process <NUM> includes requesting (<NUM>) ownership of pending cache lines (e.g., cache lines <NUM>) corresponding to the payload <NUM>, as specified in the submission (e.g., submission <NUM>). In some embodiments, cNVMe controller <NUM> is configured to determine the pending cache lines after reading the submission and cache controller(s) <NUM> is configured to request ownership of the pending cache lines from home agent <NUM> using the cache coherency protocol of the coherent interconnect fabric <NUM>. As shown in <FIG>, after acquiring the ownership of the pending cache lines, process <NUM> proceeds to indicating (<NUM>) completion of the submission by, for example, writing into a completion queue <NUM> of the CMB space <NUM>. Process <NUM> further includes opening (<NUM>) tracker entries to track the pending cache lines, and loading (<NUM>) the payload into the device cache. In some embodiments, cache controller(s) <NUM> includes and manages tracker entries associated, respectively, with the pending cache lines. In some embodiments, each logical block in the payload corresponds to one or more of the pending cache lines. In some embodiments, the pending cache lines correspond to cache lines (e.g., cache lines <NUM>) in a coherent destination memory space accessible by the host <NUM>, which could be the coherent memory space <NUM> provided by local memory <NUM>, or, when local memory <NUM> is not available or provided, the coherent memory space <NUM> corresponding to host memory <NUM>.

In some embodiments, as shown in <FIG>, loading (<NUM>) the payload <NUM> into cache memory (or device cache) <NUM> (e.g., the demand read cache 327B) includes, optionally, determining if the payload has been prefetched and stored in private memory <NUM>, and in response to the payload having been stored in private memory <NUM>, copying the data from the private memory <NUM> to the demand read cache 327B. Otherwise, or if no such determination is made, loading (<NUM>) the payload <NUM> includes reading the payload from the NVM subsystem <NUM> and writing the payload into the demand read cache <NUM>.

As shown in <FIG>, process <NUM> further includes closing (<NUM>) tracker entries after corresponding portions of the payload are loaded in the device cache (e.g., demand read cache 327B). In some embodiments, the payload <NUM> is read from the NVM subsystem <NUM> logical block by logical block, and written into the demand read cache 327B cache line by cache line. Cache controller(s) <NUM> may close the tracker entries one by one as portions of the load corresponding to the pending cache lines are loaded into the demand read cache 327B one cache line at a time. Cache controller(s) <NUM> may alco close the tracker entries one set at a time, so that cache controller(s) <NUM> would close one or more track entries associated with one or more pending cache lines corresponding to a logical block after the logical block is read from the NVM subsystem <NUM> and loaded into the demand read cache 327B.

As shown in <FIG>, indicating (<NUM>) completion of the submission may trigger the CPU to send a request for at least the demand data, which could be sent before the demand data is loaded into the demand read cache 327B because indicating (<NUM>) completion of the submission often occurs before the demand data is loaded in the demand read cache 327B. The CPU request for at least demand data in turn would trigger another process <NUM>, in which control logic <NUM>, in response to receiving from the host <NUM> the request for at least the demand data, which could correspond to one or more cache lines, and would check whether one or more tracker entries associated with the one or more cache lines have been closed, indicating that the data corresponding to the one or more cache lines have been loaded in the demand read cache 327B. Based on whether the one or more tracker entries have been closed, control logic <NUM> would either return the data corresponding to the one or more cache lines in response to the request, or continue checking the one or more tracker entries and return the data once the one or more tracker entries are closed.

<FIG> is a flowchart illustrating a predictive read process <NUM> according to certain embodiments. As shown, process <NUM> includes loading (<NUM>) the payload (e.g., payload <NUM>) into corresponding cache lines (e.g., cache lines <NUM>) in a destination coherent memory space (e.g., memory space <NUM>), as specified in the submission. In some embodiments, the submission may include one or more first hints specifying how the corresponding cache lines should be prepared before the payload in loaded therein for increased performance. Thus, loading (<NUM>) the payload into corresponding cache lines optionally includes preparing the cache lines using the one or more first hints. In some embodiments, CMX device <NUM> further facilitate speculative read processes and the payload for the current submission may have been prefetched in a prior speculative read process. Thus, process <NUM> optionally includes determining whether part or all of the payload has been prefetched and stored in the private memory <NUM>, and in response to an affirmative determination, copying part or all of the payload from the private memory into the cache lines in the destination coherent memory space. Otherwise, or if no such determination is made, or if only part of the payload is copied from the private memory, process <NUM> includes reading (<NUM>) part or all of the payload from the NVM subsystem <NUM>, and writing the data into the corresponding cache lines. In some embodiments, the submission may include one or more second hinds regarding how the payload should be read from the NVM subsystem <NUM> and/or written into the corresponding cache lines for increased performance, and reading (<NUM>) part or all of the payload from the NVM subsystem <NUM>, and/or writing the data into the corresponding cache lines are performed using the one or more second hints. Once the payload has been loaded into the cache lines specified in the submission, process <NUM> further includes indicating completion for the submission by, for example, writing into a completion queue <NUM> of the CMB.

<FIG> is a flowchart illustrating a speculative read process <NUM> according to certain embodiments. As shown, process <NUM> includes indicating (<NUM>) completion for the submission by, for example, writing into a completion queue <NUM> of the CMB, and determining (<NUM>) whether the payload should be fetched based on predefine criteria. In some embodiments, the predefined criteria may include, for example, whether the payload can be fetched from the NVM subsystem <NUM> and loaded into the private memory <NUM> within a predetermined time period without significant negative impact on the performance of higher-priority processes pending at the CMX device <NUM>. If the answer is affirmative, process <NUM> proceeds to loading (<NUM>) the payload into the private memory <NUM>, which may include, fetching (<NUM>) the payload from the NVM subsystem <NUM> by placing NVM read commands in a NVM command queue <NUM> for low priority operations and receiving the payload from the NVM subsystem <NUM>, and writing (<NUM>) the payload into the private memory <NUM>.

<FIG> is a flow diagram illustrating a page fault recovery process 1100A with reduced demand fetch latency using CMX device <NUM>, in accordance with some embodiments. As shown in <FIG>, when a thread (e.g., Thread A) of an application running on CPU <NUM> requests (<NUM>) data (e.g., a cache line or CL 'z') that is not in the CPU cache <NUM> or host memory <NUM>, a page handler <NUM> running at the CPU <NUM> issues (<NUM>) a page fault and puts (<NUM>) the thread to sleep. In response, the SDM software (SW) SDM software <NUM> sends (<NUM>) a request for the page (e.g., page x) containing CL 'z' by, for example, writing a submission into the demand queue <NUM> in the CMB space <NUM>. Upon receiving the request, the CMXC <NUM> at the CMX device <NUM> starts two sub-processes concurrently or in parallel, a first sub-process to load page x into the device cache and a second sub-process to wake up Thread A. At least part of the first sub-process overlaps with at least part of the second sub-process during a time period T. So, instead of waiting until page x is loaded into the CPU cache before waking up the Thread A, the sub-process of waking up Thread A can be running while at least a portion of page x is being loaded from the NVM subsystem <NUM> to the demand read cache 327B.

The first sub-process is started by the control logic <NUM> commanding (<NUM>) the NVM <NUM> to output page x, which includes the requested data or demand data (e.g., cache line 'z') and other cache lines. As page 'x' is being transferred (<NUM>) from the NVM <NUM> to the demand read cache 327B, the control logic <NUM> performs the second sub-process by requesting (<NUM>) ownership of the cache lines associated with page 'x', including CL 'z' from the home agent <NUM> at the CPU <NUM>. Upon receiving (<NUM>) acknowledgment from the CPU <NUM> that the ownership is granted, the control logic <NUM> notifies the SDM software <NUM> that the page is ready by, for example, writing (<NUM>) a completion for submission in a completion queue in the CMB. In response, the SDM software <NUM> closes the loop by indicating (<NUM>) to the page handler <NUM> that the page is ready, causing the page handler <NUM> to wake up (<NUM>) Thread A, which then sends (<NUM>) out a request to the control logic <NUM> to return the requested data (e.g., CL 'z'). In some embodiments, the requested data CL 'z' is transferred (<NUM>) directly from the device cache to the CPU cache <NUM> using, for example, CXL. mem or CXL. At least an unread portion of the page x can be subsequently transferred (<NUM>) to the device memory <NUM> at low priority in a background process. The CPU can then access any of the other cache lines via the CXL bus <NUM>.

<FIG> is a flow diagram illustrating a page fault recovery process 1100B with further reduced demand fetch latency using CMX device <NUM>, in accordance with some embodiments. As shown in <FIG> and <FIG>, process 1100B is similar to process 1100A except that in process 1100B, when issuing commands to the NVM subsystem <NUM> to read the page from the NVM subsystem <NUM>, control logic <NUM> would issue (1110A) the command corresponding to the high priority LBA for the logical block including the requested cache line "z" first, followed by the commands (<NUM>) for the other LBA's. As a result, the logical block corresponding to the high priority LBA is output from the NVM subsystem <NUM> and loaded (<NUM>) into the demand read cache 327B before the other logical blocks in page 'x.

Thus, as shown in <FIG>, a requested page <NUM> (e.g., a <NUM> kB page fill payload) is moved to the coherent demand read cache 327B, which is used to serve up critical demand data <NUM> (e.g., a 64B cache line) via low latency cache-to-cache transfer to make the demand data immediately available to the CPU <NUM>, while deprioritizing remaining low-priority data <NUM> to prevent CPU data/coherency fabric congestion. As also shown in <FIG>, all or a remainder of the page <NUM> can be moved to the device memory <NUM>, and memory access for the demand data (hot data) can be served <NUM> from the demand read cache 327B while less critical data (warm data) is served <NUM> from the device memory <NUM> with low latency, as shown in <FIG>. In comparison, as shown in <FIG>, a conventional NVMe-based memory expansion controller has no virtual memory and no device cache or memory. All data is fetched from the NVM coupled to an NVMe controller, and transferred to the host memory before the CPU can then access the data from the host memory, resulting in increased latency for the demand data and CPU data/coherency fabric congestion.

<FIG> is a timing diagram illustrating some of the advantages of CMX device <NUM>, in accordance with some embodiments. As shown, using process 1100A or 1100B, the time required to obtain demand data by a thread after the page fault is reduced by about <NUM>% when message signal interrupt (MSI) is used to wake up the thread, if the page has not been prefetched and stored in private memory <NUM>. In the case when the page has been prefetched and stored in private memory <NUM>, the time required to obtain demand data by a thread after the page fault is reduced by about <NUM>%, especially when mWake - a mechanism in the CPU that allows software to monitor a submission queue and wake up the thread when there is an update of a head/tail pointer - is used to wake up the thread.

<FIG> illustrates an operation of a CMX device <NUM> having a CMXC <NUM>, which includes or is coupled to a device cache (or demand read cache) <NUM>, in accordance with some embodiments. In some embodiments, CMX device <NUM> is similar to CMX device <NUM> except that CMX device <NUM> does not provide a local DRAM memory to store payloads and/or related logic controlling data transfers to or from the local DRAM memory. In some embodiments, the control logic in the CMXC <NUM> is configurable to: receive a submission <NUM> from the CPU <NUM> via the CXL bus <NUM>; read the payload <NUM> from the non-volatile memory <NUM>; load the payload <NUM> into the device cache <NUM>; and transfer at least requested portion <NUM> of the payload from the device cache <NUM> to the CPU <NUM> via the CXL bus <NUM>; and transfer at least an unrequested portion <NUM> of the payload to a dynamic random access memory (DRAM) (e.g., host memory <NUM>) accessible by the CPU <NUM> for memory read and write operations via a memory channel. The requested data <NUM> is transferred from the device cache to the CPU <NUM> via the dedicated link (e.g., CXL bus <NUM>) without going through a memory channel (e.g., the system bus <NUM>).

In some embodiments, the at least unrequested portion <NUM> of the payload is transferred to the host memory <NUM> in one or more background operations without specific requests from the CPU <NUM>. The CPU <NUM> can subsequently access the at least unrequested portion <NUM> of the payload if needed by issuing a read command (<NUM>) to the host memory <NUM>, which causes the host memory <NUM> to output the data to the CPU via the memory channel or system bus <NUM>.

Thus, CMX device <NUM> provides improved SDM request path and dedicated backchannel between the demand read cache <NUM> and the NVM <NUM>. Demand data can be transferred directly between the demand read cache <NUM> and the CPU <NUM>, while low priority data is opportunistically moved into the host DRAM <NUM>. In some embodiments, CMX device <NUM> can be used as a direct replacement for a conventional SDM (e.g., NVMe) expansion device and to provide improved performance over the conventional SDM expansion device for all supported workloads. The CMX device <NUM> also supports additional workloads not viable with the conventional SDM expansion device.

<FIG> illustrates a memory map <NUM> of a computer system including CMX device <NUM> in accordance with some embodiments. As shown in <FIG>, SDM software <NUM> pools the memory and storage resources in the computer system together and presents them to the CPU <NUM> as virtual memory <NUM> accessible by one or more unified memory access (UMA) applications <NUM> running at the CPU <NUM>. For example, the NVM <NUM> may correspond to a <NUM> TB virtual memory space that is managed by the SDM software <NUM>, and data can be moved between the NVM <NUM> and the Host DRAM <NUM> via the coherent demand read cache <NUM>. Thus, the CMX device <NUM> allows the SDM to migrate data from the NVM <NUM> into host memory <NUM> through the device cache <NUM>. As discussed below, the CMXC controller <NUM>, together with the local coherent demand read cache <NUM>, provides enhanced performance through SDM intelligent pre-fetching, and overlapping of a data fetch process with a process of waking up the request thread.

In some embodiments, as shown in <FIG>, a process <NUM> of transferring data from the NVM <NUM> to the CPU comprises receiving (<NUM>) from the SDM <NUM> running on the CPU <NUM> a request to access data at a location in a memory map or to retire an NVM payload. In some embodiments, the request can be sent as one or more cDMA commands based on the CXL. mem protocol or an NVMe submission. As shown in <FIG>, process <NUM> further comprises loading (<NUM>) an NVM page (or NVM payload) including the demand data into the coherent demand read cache <NUM> by, for example, the CMXC <NUM> using, for example, a cDMA cache fill process. Process <NUM> further comprises conducting (<NUM>) a direct cache-to-cache transfer of the demand data to a CPU cache <NUM> (e.g., L1-L3 cache) based on, for example, the CXL. cache protocol, and syncing (<NUM>) additional unused data in the NVM page to the host memory <NUM> in a low-priority background writeback process. The additional data can then be read (<NUM>) by the CPU <NUM> via a memory channel (e.g., system bus <NUM>).

In some embodiments, as shown in <FIG>, a near hit latency t1 (e.g., the latency of fetching the demand data directly from host memory <NUM>) is about, for example, <NUM> nano seconds (ns), a far hit latency t2 (e.g., the latency of fetching the demand data directly from the demand read cache <NUM>) is about, for example, <NUM> ns, and a far miss latency t3 (e.g., the latency of transferring the data from the NVM <NUM> to the demand read cache <NUM> and from the demand read cache <NUM> to the CPU cache <NUM>) is about, for example, <NUM> ns. Assuming a <NUM>% probability that the demand data is readily available in the host memory <NUM>, a <NUM>% probability that the demand data is readily available in the demand read cache <NUM>, and a <NUM>% probability that the demand data is in neither the host memory <NUM> nor the demand read cache <NUM> and thus has to be transferred from the NVM <NUM>, a resulting average latency for fetching the demand data would be about, for example, <NUM> ns.

<FIG> is a flow diagram illustrating a page fault recovery process 1800A with reduced demand fetch latency using CMX device <NUM>, in accordance with some embodiments. As shown in <FIG>, when a thread (e.g., Thread A) of an application running on CPU <NUM> requests (<NUM>) data (e.g., a cache line or CL 'z') that is not in the CPU cache <NUM> or host memory <NUM>, a page handler <NUM> running at the CPU <NUM> issues (<NUM>) a page fault and puts (<NUM>) the thread to sleep. In response, the SDM software (SW) SDM software <NUM> sends (<NUM>) a request for the page (e.g., page x) containing CL 'z' by, for example, writing a submission into a demand queue in CMX device <NUM>. In some embodiments, in addition to the demand read cache <NUM>, CMX device <NUM> further includes additional cache memory (e.g., SRAM or HBM) for storing demand queues or submission queues (e.g., one or more demand queues <NUM>, one or more predictive queues <NUM> and one or more speculative queues <NUM>, and one or more completion queues completion queue <NUM>) accessible by CPU <NUM>. Upon receiving the request, the CMXC <NUM> at the CMX device <NUM> starts two sub-processes concurrently or in parallel, a first sub-process to load page x into the device cache <NUM> and a second sub-process to wake up Thread A. At least part of the first sub-process overlaps with at least part of the second sub-process. So, instead of waiting until page x is loaded into the CPU cache before waking up the Thread A, the sub-process of waking up Thread A can be running while at least a portion of page x is being loaded from the NVM <NUM> to the demand read cache <NUM>.

The first sub-process is started by CMXC <NUM> commanding (<NUM>) the NVM <NUM> to output page x, which includes the requested data or demand data (e.g., cache line 'z') and other cache lines. As page 'x' is being transferred (<NUM>) from the NVM <NUM> to the demand read cache 327B, the CMXC <NUM> performs the second sub-process by requesting (<NUM>) ownership of the cache lines associated with page 'x', including CL 'z' from the home agent <NUM> at the CPU <NUM>. Upon receiving (<NUM>) acknowledgment from the CPU <NUM> that the ownership is granted, CMXC <NUM> notifies the SDM software <NUM> that the page is ready by, for example, writing (<NUM>) a completion for submission in a completion queue in the CMB. In response, the SDM software <NUM> closes the loop by indicating (<NUM>) to the page handler <NUM> that the page is ready, causing the page handler <NUM> to wake up (<NUM>) Thread A, which then sends (<NUM>) out a request to CMXC <NUM> to return the requested data (e.g., CL 'z'). In some embodiments, the requested data CL 'z' is transferred (<NUM>) directly from the device cache to the CPU cache <NUM> using, for example, CXL. mem or CXL. At least an unread portion of the page x can be subsequently transferred (<NUM>) to the host memory <NUM> at low priority in a background process. The CPU <NUM> can then access any of the other cache lines via the system bus <NUM>.

<FIG> is a flow diagram illustrating a page fault recovery process 1800B with further reduced demand fetch latency using CMX device <NUM>, in accordance with some embodiments. As shown in <FIG> and <FIG>, process 1800B is similar to process 1800A except that in process 1800B, when issuing commands to the NVM subsystem <NUM> to read the page from the NVM subsystem <NUM>, CMXC <NUM> would issue (1810A) the command corresponding to the high priority LBA for the logical block including the requested cache line "z" first, followed by the commands (<NUM>) for the other LBA's. As a result, the logical block corresponding to the high priority LBA is output from the NVM subsystem <NUM> and loaded (<NUM>) into the demand read cache <NUM> before the other logical blocks in page 'x.

The CMX device <NUM> has several advantages over conventional software-defined memory (SDM) based on NVMe. For example, as shown in <FIG>, the coherent device cache <NUM> is used to serve up critical demand data <NUM> via low latency cache-to-cache transfer, while deprioritizing remaining low-priority data <NUM> to prevent CPU data/coherency fabric congestion. In comparison, as shown in <FIG>, conventional NVMe based solution requires the full <NUM> kB page from a NVM be transferred from the NVM to the host DRAM before the application requesting the demand data can access the demand data via the host memory channel, resulting in increased latency for the demand data and CPU data/coherency fabric congestion.

It will be understood that, although the terms first, second, etc., are, in some instances, used herein to describe various elements, these elements should not be limited by these terms. For example, a first UV lamp could be termed a second UV lamp, and, similarly, a second UV lamp could be termed a first UV lamp, without departing from the scope of the various described embodiments. The first widget and the second widget are both widget, but they are not the same condition unless explicitly stated as such.

The terminology used in the description of the various described embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various described embodiments and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Claim 1:
A memory expansion device (<NUM>) operable in a computer system, the computer system including a host computer (host) (<NUM>) and a dedicated bus (<NUM>), the memory expansion device (<NUM>) comprising:
interface circuitry (<NUM>) configured to communicate with the host (<NUM>) via the dedicated bus (<NUM>) based on a predefined protocol;
a non-volatile memory (NVM) subsystem (<NUM>);
cache memory (<NUM>/327B); and
control logic (<NUM>) coupled to the interface circuitry (<NUM>), the cache memory (<NUM>/327B), and the NVM subsystem (<NUM>), wherein the control logic (<NUM>) is configurable to:
receive a first submission from the host (<NUM>), the first submission including a first read command and specifying a first payload (<NUM>) in the NVM subsystem (<NUM>); and
in response to the first submission being of first priority, request ownership of first cache lines (<NUM>) corresponding to the first payload, indicate completion of the first submission after acquiring ownership of the first cache lines, and load the first payload (<NUM>) to the cache memory (<NUM>/327B), the first cache lines corresponding to cache lines in a first coherent destination memory space (<NUM>) accessible by the host (<NUM>).