Patent Description:
The demands of storage capacity of host memory, e.g., DRAM, is growing, but the cost of host memory is still high. Using part of external memory, e.g., SSD, to make up the short of the host memory is a feasible solution. How to design the external memory to fit the additional function is worth to pay attention to. <CIT> (<NUM>-<NUM>-<NUM>) discloses determining one or more attributes associated with data and determining whether to store data in a second set of non-volatile memory cells based on one or more attributes.

<CIT> (<NUM>-<NUM>-<NUM>) discloses a controller selecting either a first mode or a second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

The invention is defined by appended set of claims. In one aspect, a memory system, coupled to a host memory, comprising:.

In some implementations, wherein the memory controller comprising:.

In some implementations, wherein the processor further configured to:
based on a logical to physical address mapping table, transfer a logical address of the first address signal and/or a second address signal to a physical address.

In some implementations, wherein the processor further configured to:.

In some implementations, wherein the processor further configured to write the second data to the first memory cells.

In some implementations, wherein the memory cells of the second memory cells are single level cells(SLC).

In some implementations, wherein the memory cells of the first memory cells are multi level cells(MLC), trinary level cells(TLC), or quad level cells(QLC).

In another aspect, a method for operating a memory system, the memory system is coupled to a host memory, the method comprising:.

In some implementations, further comprising:.

In some implementations, further comprising:
based on a logical to physical address mapping table, transfer a logical address of the first address signal and/or the second address signal to a physical address.

In some implementations, further comprising:
writing the second data to the first memory cells.

In another aspect, a memory system, coupled to a host memory, comprising:.

In some implementations, wherein the memory controller comprising:
a processor, configured to, in response to a command of reading, read the first data from the first memory cells according to a first address signal, and/or read the second data from the second memory cells according to a second address signal.

In some implementations, wherein the processor further configured to:
based on a logical to physical address mapping table, transfer a logical address of the first address signal and/or the second address signal to a physical address.

The method of claim <NUM>, further comprising:.

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

Aspects of the present disclosure will be described with reference to the accompanying drawings.

Although specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosure can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

<FIG> illustrates a block diagram of an exemplary system <NUM> having a memory device, according to some aspects of the present disclosure. System <NUM> can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown in <FIG>, system <NUM> can include a host <NUM> having a host memory <NUM> and a host processor <NUM>, and a memory system <NUM> having one or more memory devices <NUM> and a memory controller <NUM>.

Host <NUM> can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host <NUM> can be coupled to memory controller <NUM> and configured to send or receive data to or from memory devices <NUM> through memory controller <NUM>. For example, host <NUM> may send the program data in a program operation or receive the read data in a read operation. Host processor <NUM> can be a control unit (CU), or an arithmetic & logic unit (ALU). Host memory <NUM> can be memory units including register or cache memory. Host <NUM> is configured to receive and transmit instructions and command to and from memory controller <NUM> of memory device <NUM>, and execute or perform multiple functions and operations provided in the present disclosure, which will be described later.

Memory device <NUM> can be any memory device disclosed in the present disclosure, such as a NAND Flash memory device, which includes a page buffer having multiple portions, for example, four quarters. It is noted that the NAND Flash is only one example of the memory device for illustrative purposes. It can include any suitable solid-state, non-volatile memory, e.g., NOR Flash, Ferroelectric RAM (FeRAM), Phase-change memory (PCM), Magnetoresistive random-access memory (MRAM), Spin-transfer torque magnetic random-access memory (STT-RAM), or Resistive random-access memory (RRAM), etc. In some implementations, memory device <NUM> includes a three-dimensional (3D) NAND Flash memory device.

Memory controller <NUM> can be implemented by microprocessors, microcontrollers (a. microcontroller units (MCUs)), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware, firmware, and/or software configured to perform the various functions described below in detail.

Memory controller <NUM> is coupled to memory device <NUM> and host <NUM> and is configured to control memory device <NUM>, according to some implementations. Memory controller <NUM> can manage the data stored in memory device <NUM> and communicate with host <NUM>. In some implementations, memory controller <NUM> is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller <NUM> is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller <NUM> can be configured to control operations of memory device <NUM>, such as read, erase, and program operations, by providing instructions, such as read instructions, to memory device <NUM>. For example, memory controller <NUM> may be configured to provide a read instruction to the peripheral circuit of memory device <NUM> to control the read operation. Memory controller <NUM> can also be configured to manage various functions with respect to the data stored or to be stored in memory device <NUM> including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller <NUM> is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device <NUM>. Any other suitable functions may be performed by memory controller <NUM> as well, for example, formatting memory device <NUM>.

Memory controller <NUM> can communicate with an external device (e.g., host <NUM>) according to a particular communication protocol. For example, memory controller <NUM> may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc..

Memory controller <NUM> and one or more memory devices <NUM> can be integrated into various types of storage devices, for example, being included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system <NUM> can be implemented and packaged into different types of end electronic products. In one example as shown in <FIG>, memory controller <NUM> and a single memory device <NUM> may be integrated into a memory card <NUM>. Memory card <NUM> can include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. Memory card <NUM> can further include a memory card connector <NUM> coupling memory card <NUM> with a host (e.g., host <NUM> in <FIG>). In another example as shown in <FIG>, memory controller <NUM> and multiple memory devices <NUM> may be integrated into an SSD <NUM>. SSD <NUM> can further include an SSD connector <NUM> coupling SSD <NUM> with a host (e.g., host <NUM> in <FIG>). In some implementations, the storage capacity and/or the operation speed of SSD <NUM> is greater than those of memory card <NUM>.

Memory control <NUM> is configured to receive and transmit command to and from host <NUM>, and execute or perform multiple functions and operations provided in the present disclosure, which will be described later.

<FIG> illustrates a schematic circuit diagram of an exemplary memory device <NUM> including peripheral circuits, according to some aspects of the present disclosure. Memory device <NUM> can be an example of memory device <NUM> in <FIG>. It is noted that the NAND Flash disclosed herein is only one example of the memory device for illustrative purposes. It can include any suitable solid-state, non-volatile memory, e.g., NOR Flash, FeRAM, PCM, MRAM, STT-RAM, or RRAM, etc. Memory device <NUM> can include a memory cell array <NUM> and peripheral circuits <NUM> coupled to memory cell array <NUM>. Memory cell array <NUM> can be a NAND Flash memory cell array in which memory cells <NUM> are provided in the form of an array of NAND memory strings <NUM> each extending vertically above a substrate (not shown). In some implementations, each NAND memory string <NUM> includes a plurality of memory cells <NUM> coupled in series and stacked vertically. Each memory cell <NUM> can hold a continuous, analog value, such as an electrical voltage or charge, which depends on the number of electrons trapped within a region of memory cell <NUM>. Each memory cell <NUM> can be either a floating gate type of memory cell including a floating-gate transistor or a charge trap type of memory cell including a charge-trap transistor.

In some implementations, each memory cell <NUM> is a single-level cell (SLC) that has two possible memory states and thus, can store one bit of data. For example, the first memory state "<NUM>" can correspond to a first range of voltages, and the second memory state "<NUM>" can correspond to a second range of voltages. In some implementations, each memory cell <NUM> is a multi-level cell (MLC) that is capable of storing more than a single bit of data in more than four memory states. For example, the MLC can store two bits per cell, three bits per cell (also known as triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, then the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

As shown in <FIG>, each NAND memory string <NUM> can include a source select gate (SSG) transistor <NUM> at its source end and a drain select gate (DSG) transistor <NUM> at its drain end. SSG transistor <NUM> and DSG transistor <NUM> can be configured to activate selected NAND memory strings <NUM> (columns of the array) during read and program operations. In some implementations, the sources of NAND memory strings <NUM> in the same block <NUM> are coupled through a same source line (SL) <NUM>, e.g., a common SL. In other words, all NAND memory strings <NUM> in the same block <NUM> have an array common source (ACS), according to some implementations. The drain of DSG transistor <NUM> of each NAND memory string <NUM> is coupled to a respective bit line <NUM> from which data can be read or written via an output bus (not shown), according to some implementations. In some implementations, each NAND memory string <NUM> is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of DSG transistor <NUM>) or a deselect voltage (e.g., <NUM> V) to the gate of respective DSG transistor <NUM> through one or more DSG lines <NUM> and/or by applying a select voltage (e.g., above the threshold voltage of SSG transistor <NUM>) or a deselect voltage (e.g., <NUM> V) to the gate of respective SSG transistor <NUM> through one or more SSG lines <NUM>.

As shown in <FIG>, NAND memory strings <NUM> can be organized into multiple blocks <NUM>, each of which can have a common source line <NUM>, e.g., coupled to the ACS. In some implementations, each block <NUM> is the basic data unit for erase operations, i.e., all memory cells <NUM> on the same block <NUM> are erased at the same time. To erase memory cells <NUM> in a selected block <NUM>, source lines <NUM> coupled to selected block <NUM> as well as unselected blocks <NUM> in the same plane as selected block <NUM> can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., <NUM> V or more). Memory cells <NUM> of adjacent NAND memory strings <NUM> can be coupled through word lines <NUM> that select which row of memory cells <NUM> is affected by the read and program operations. In some implementations, each word line <NUM> is coupled to a page <NUM> of memory cells <NUM>, which is the basic data unit for the program and read operations. The size of one page <NUM> in bits can relate to the number of NAND memory strings <NUM> coupled by word line <NUM> in one block <NUM>. Each word line <NUM> can include a plurality of control gates (gate electrodes) at each memory cell <NUM> in respective page <NUM> and a gate line coupling the control gates. Peripheral circuits <NUM> can be coupled to memory cell array <NUM> through bit lines <NUM>, word lines <NUM>, source lines <NUM>, SSG lines <NUM>, and DSG lines <NUM>. Peripheral circuits <NUM> can include any suitable analog, digital, and mixed-signal circuits for facilitating the operations of memory cell array <NUM> by applying and sensing voltage signals and/or current signals to and from each target memory cell <NUM> through bit lines <NUM>, word lines <NUM>, source lines <NUM>, SSG lines <NUM>, and DSG lines <NUM>. Peripheral circuits <NUM> can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technologies.

<FIG> illustrates a block diagram of an exemplary memory system <NUM> including a memory controller <NUM> and a memory device <NUM>, according to some aspects of the present disclosure. As shown in <FIG>, memory controller <NUM> can include a controller processor <NUM>, such as a memory chip controller (MCC) or a memory controller unit (MCU). Controller processor <NUM> is configured to control modules to execute commands or instructions to perform functions disclosed in the present disclosure. Controller processor <NUM> can also be configured to control the operations of each peripheral circuit by generating and sending various control signals, such as read commands for read operations. Controller processor <NUM> can also send clock signals at desired frequencies, periods, and duty cycles to other peripheral circuits <NUM> to orchestrate the operations of each peripheral circuit <NUM>, for example, for synchronization. Memory controller <NUM> can further include a volatile controller memory <NUM> and a non-volatile controller memory. Volatile controller memory <NUM> can include a register or cache memory such that it allows a faster access and process speed to read, write, or erase the data stored therein, while it may not retain stored information after power is removed. In some implementations, volatile controller memory <NUM> includes dynamic random access memory (DRAM), Static random access memory (SRAM). Non-volatile controller memory <NUM> can retain the stored information even after power is removed. In some implementations, non-volatile controller memory <NUM> includes NAND, NOR, FeRAM, PCM, MRAM, STT-RAM, or RRAM. Memory device <NUM> can include a memory cell array such as memory cell array <NUM> in <FIG>. In some implementations, non-volatile controller memory <NUM> can be not provided in the memory controller <NUM>, for example, non-volatile controller memory <NUM> is deposed outside of the memory controller <NUM> but is coupled to the memory controller <NUM>. In some implementations, the controller memory (e.g., <NUM> or <NUM>) is configured to store the L2P address mapping table (e.g., <NUM>, <NUM>) corresponding to the file (e.g., <NUM>).

<FIG> illustrates a block diagram of an exemplary host <NUM> including a host memory <NUM> and a host processor <NUM>, according to some aspects of the present disclosure. The host memory <NUM> can be a volatile memory, such as random access memory (RAM), e.g., DRAM, SRAM. The host memory <NUM> also can be a non-volatile memory, such as NAND, NOR, FeRAM, PCM, MRAM, STT-RAM, or RRAM. The host memory <NUM> includes a main RAM <NUM> and a ZRAM <NUM>. In some implementations, the main RAM <NUM> and the ZRAM <NUM> can be different logic zones of the host memory <NUM>. In other words, the memory cells of the main RAM <NUM> and the memory cells of the ZRAM <NUM> can be distinguished by logical addresses of the memory cells. In some implementations, the main RAM <NUM> and the ZRAM <NUM> can be separated memories. For example, the main RAM <NUM> can be belong to a first host memory <NUM>, the ZRAM <NUM> can be belong to a second host memory <NUM> which is independent to the first host memory <NUM>. And the first host memory <NUM> and the second host memory <NUM> can be same or different types of memory. In some implementations, the host processor <NUM> can be a control unit (CU), or an arithmetic & logic unit (ALU).

In some implementations, the data of the main RAM <NUM> can be transferred to the ZRAM <NUM>, and the transferred data can be software program. Further, the operation of data transfer can be triggered when the main RAM <NUM> is full, or anytime the host processor <NUM> depends. In some implementations, the operation of data transfer can be controlled by the host processor <NUM>. In some implementations, the transferred data to the ZRAM <NUM> can be compressed data. The operation of data compression can be conducted in anytime, for example, before the data sent out from the main RAM <NUM>, or during the process of transfer(after the data sent out from the main RAM <NUM> and before the data received by the ZRAM <NUM>),or after the data received by the ZRAM <NUM>. The compression operation can be controlled by the host processor <NUM>. In some implementations, the process of the operation can be: when the main RAM <NUM> is full, the host processor <NUM> controls the main RAM <NUM> transfer the data of main RAM <NUM> to the ZRAM <NUM>, and the transferred data is compressed before it received by the ZRAM <NUM>. In some implementations, the data transferred from main RAM <NUM> can be the data with lower access frequency than the data remained in the main RAM <NUM>. In this case, the inactive data can be compressed and the storage capacity of the host memory <NUM> can be saved. For example, in an implementation of smart phone, presuming <NUM> applications are running and the programs of the <NUM> applications are stored in the main RAM <NUM>, if <NUM> of the <NUM> applications are inactive, the programs of the <NUM> inactive applications can be compressed and stored in the ZRAM <NUM>. So that, part of the storage capacity of the main RAM <NUM> can be released so that more programs can be stored in the host memory <NUM> which means more apps can run in the same time. In this case, the <NUM> inactive applications are still run in the background, and the programs of the <NUM> inactive applications can be decompressed when the <NUM> inactive applications are called.

The data in the host memory <NUM> also can be transferred to the memory device <NUM>, and the data can be transferred from the ZRAM <NUM> or the main RAM <NUM>. Further, the operation of data transfer can be triggered when the main RAM <NUM> or the main RAM <NUM> is full, or anytime the host processor <NUM> depends. In some implementations, the operation of data transfer can be controlled by the host processor <NUM>. In some implementations, the ZRAM <NUM> transfers swap data to the memory system (e.g., SSD, UFS, eMMC), the swap data can be the compressed software program. The memory system can stores the swap data, memory system can also send the swap data back to the host memory <NUM> (e.g., the ZRAM <NUM>), so that the memory system can be a supplementary of the host memory <NUM>. In some implementations, after the ZRAM <NUM> transfers the swap data to the memory system, the swap data in the ZRAM <NUM> can be deleted for releasing the storage capacity of the ZRAM <NUM>. In some implementations, when the storage capacity of the ZRAM <NUM> is tight, the swap data corresponding to the inactive software or application can be transferred to the memory system from the ZRAM <NUM>; when the inactive software or application is called, the corresponding swap data can be transferred to the ZRAM <NUM> from the memory system. In this case, more softwares or applications can be ran in the same time.

The host processor <NUM> can send a command to the memory system to instruct the memory system to input or output the swap data. Further, the memory system can comprise the memory controller <NUM> and the memory device <NUM>, the memory device <NUM> can be the NAND flash memory. The command and the swap data can be sent to the memory controller <NUM>, and the memory controller <NUM> can write the swap data to the memory device <NUM> according to the command. In some implementations, the host processor <NUM> also can send address signal to the memory controller, wherein the address signal comprise a logical address, and the controller can transfer the logical address to a physical address based on a L2P address mapping table. The L2P address mapping table can be stored in a DRAM of the memory system, the NAND flash, or the host memory <NUM>. The physical address points to the memory cells of the memory device <NUM>, so that the memory controller <NUM> can write the swap data to the target memory cells, and the memory controller <NUM> can read the swap data from the target memory cells. In some implementations, when the storage capacity of the ZRAM <NUM> is tight, the swap data corresponding to the inactive software or application can be transferred to the memory device <NUM> from the ZRAM <NUM>; when the inactive software or application is called, the corresponding swap data can be transferred to the ZRAM <NUM> from the memory device <NUM>. In this case, more softwares or applications can be ran in the same time.

<FIG> illustrates a block diagram of an exemplary memory device <NUM> including a memory cell array <NUM>, according to some aspects of the present disclosure. The memory cell array <NUM> can be divided into multiple logical units according to the logical address of the memory cells, e.g., big LUN <NUM> (logic unit number), swap LUN <NUM>, BOOT A <NUM>, BOOT B <NUM>. In some implementations, the host <NUM> can access the big LUN <NUM>, swap LUN <NUM>, BOOT A <NUM> or BOOT B <NUM> by sending the command and the address signal of the memory cells. Further, the address signal including the logical address of the memory cells, and the memory controller <NUM> transfers the logical address to the physical address according to the L2P mapping table.

In some implementations, big LUN <NUM>, BOOT A <NUM> and BOOT B <NUM> can store user data, and the swap LUN <NUM> can store swap data. The user data can be the data received by the host <NUM> or the data generated in the host <NUM>. For example, in a smart phone with a UFS (the memory system), the user data can be the data input by user of the computer, or the data generated during the operation of the host <NUM>. In some implementations, BOOT A <NUM> and BOOT B <NUM> also can store system data, wherein the system data can be the system programs of an operation system. For example, in a smart phone with a UFS (the memory system), the system data stored in the BOOT A <NUM> or BOOT B <NUM> of the SSD can be the programs of Windows system. The memory controller <NUM> can write the user data to the memory cells corresponding to the big LUN <NUM>, BOOT A <NUM> and BOOT B <NUM>, and the memory controller <NUM> can read the user data from the memory cells corresponding to the big LUN <NUM>, BOOT A <NUM> and BOOT B <NUM>. The memory controller <NUM> can write the swap data to the memory cells corresponding to the swap LUN <NUM>, and the memory controller <NUM> can read the swap data from the memory cells corresponding to the swap LUN <NUM>. In other words, the memory cells for storing the swap data are separated from the memory cells for storing the user data. Due to the swap data is accessed more frequently than the user data, the memory cells corresponding to the swap LUN <NUM> are wear out earlier than the memory cells corresponding to the big LUN <NUM>, BOOT A <NUM> or BOOT B <NUM>. Because the swap LUN <NUM> is separated from the big LUN <NUM>, BOOT A <NUM> or BOOT B <NUM>, the big LUN <NUM>, BOOT A <NUM> and BOOT B <NUM> are not be influenced by the frequently accesses of the swap LUN <NUM>. If the memory cells corresponding to the swap LUN <NUM> is wear out, the memory cells corresponding to the big LUN <NUM>, BOOT A <NUM> and BOOT B <NUM> are still programmable and readable.

<FIG> illustrates a block diagram of an exemplary memory system including a memory controller <NUM> and a memory device <NUM>, according to some aspects of the present disclosure. In some implementations, the memory device <NUM> can comprise first memory cells <NUM> and second memory cells <NUM>. The first memory cells <NUM> are configured to store a first data, wherein the first data is user data. The second memory cells <NUM> are configured to store a second data, wherein the second data is swap data from a host memory <NUM>. Further, a memory controller <NUM> is coupled between a host <NUM> and the memory device <NUM>, and the memory controller <NUM> is configured to write a first data to the first memory cells <NUM> and/or a second data to the second memory cells <NUM>. In some implementations, the first memory cells <NUM> can be the memory cells corresponding to big LUN <NUM>, BOOT A <NUM> and BOOT B <NUM>, and the second memory cells <NUM> can be the memory cells corresponding to swap LUN <NUM>. Due to the swap data is accessed more frequently than the user data, the second memory cells <NUM> are wear out earlier than the first memory cells <NUM>. Because the second memory cells <NUM> is separated from the first memory cells <NUM>, the first memory cells <NUM> are not be influenced by the frequently accesses of the second memory cells <NUM>. If the second memory cells <NUM> are wear out, the second memory cells <NUM> are still programmable and readable.

In some implementations, the second memory cells <NUM> can be single level cells(SLC). Due to each memory cell stores one bit data, SLC can have better performance than multi level cells(MLC), trinary level cells(TLC), and quad level cells(QLC), e.g., less program time, less reading time, and more program/erase cycle times. Because the swap LUN <NUM> is accessed more frequently than the big LUN <NUM>, BOOT A <NUM> and BOOT B <NUM>, the second memory cells <NUM> demands better performance than the first memory cells <NUM>. And the SLC can satisfy the performance demands of the second memory cells <NUM>.

In some implementations, the first memory cells <NUM> can be MLC, TLC or QLC. Due to each memory cell stores <NUM>/<NUM>/<NUM> bits data, MLC, TLC and QLC can have larger storage capacity than SLC. Because the big LUN <NUM>, BOOT A <NUM> and BOOT B <NUM> is accessed less frequently than the swap LUN <NUM> and demand for larger storage capacity, the first memory cells <NUM> demand for lower cost than the second memory cells <NUM>. And the MLC, TLC and QLC can satisfy the low cost demands of the first memory cells <NUM>.

In some implementations, the memory controller <NUM> comprises a cache <NUM> and a controller processor <NUM>. The cache <NUM> can be SRAM, DRAM, NAND flash, NOR flash or any other types of memory or electrical device. The controller processor <NUM> can be a control unit (CU), or an arithmetic & logic unit (ALU). For a writing operation, based on a command of wrting, the cache <NUM> is configured to receive the first data and/or the second data, and controller processor <NUM> is configured to write the first data to the first memory cells <NUM> according to a first address signal, and/or write the second data to the second memory cells <NUM> according to a second address signal. In some implementations, the first address signal can comprise a first logical address points to the big LUN <NUM>, BOOT A <NUM> and BOOT B <NUM>. The controller processor <NUM> can transfer the first logical address to a first physical address based on a L2P address mapping table, and the first physical address is corresponding to the first memory cells <NUM>. Thus, the memory controller <NUM> writes user data to the first memory cells <NUM> according to the first address signal. In some implementations, the second address signal can comprise a second logical address points to the swap LUN <NUM>. The controller processor <NUM> can transfer the second logical address to a second physical address based on a L2P address mapping table, and the second physical address is corresponding to the second memory cells <NUM>. Thus, the memory controller <NUM> writes swap data to the second memory cells <NUM> according to the second address signal. For a reading operation, based on a command of reading, the cache <NUM> is configured to receive the first data and/or the second data, and controller processor <NUM> is configured to read the first data from the first memory cells <NUM> according to a second address signal, and/or read the second data from the second memory cells <NUM> according to a second address signal. In some implementations, the second address signal can comprise a first logical address points to the big LUN <NUM>, BOOT A <NUM> and BOOT B <NUM>. The controller processor <NUM> can transfer the first logical address to a first physical address based on a L2P address mapping table, and the first physical address is corresponding to the first memory cells <NUM>. Thus, the memory controller <NUM> reads user data from the first memory cells <NUM> according to the second address signal. In some implementations, the second address signal can comprise a second logical address points to the swap LUN <NUM>. The controller processor <NUM> can transfer the second logical address to a second physical address based on a L2P address mapping table, and the second physical address is corresponding to the second memory cells <NUM>. Thus, the memory controller <NUM> reads swap data from the second memory cells <NUM> according to the second address signal.

In some implementations, for a writing operation, the memory processor can count the cycle times of the second memory cells <NUM>, and compare the cycle times with a lifetime threshold, when the writing time reaches the lifetime threshold, the processor can prohibit to write the second data to the second memory cells <NUM>. The cycle times can be the program/erase times. The swap LUN <NUM> is accessed more frequently than the big LUN <NUM>, BOOT A <NUM> and BOOT B <NUM>, so that the second memory cells <NUM> may be wear out earlier than the first memory cells <NUM>. Counting cycle times of the SLC can monitor the rest life of the second memory cells <NUM>. When the second memory cells <NUM> are wear out, the second memory cells <NUM> will be disabled in case of swap data loss. In some implementations, after the second memory cells <NUM> are disabled, the host <NUM> will not transfer swap data to the memory system. In other implementations, after the second memory cells <NUM> are disabled, the host <NUM> will still transfer swap data to the memory system, and the memory controller <NUM> will write the swap data to the first memory cells <NUM> according to the command provided by the host <NUM>. In some implementations, for a reading operation, the memory processor can count the cycle times of the second memory cells <NUM>, and compare the cycle times with a lifetime threshold, when the reading time reaches the lifetime threshold, the processor can prohibit to read the second data from the second memory cells <NUM>. The cycle times can be the program/erase times. The swap LUN <NUM> is accessed more frequently than the big LUN <NUM>, BOOT A <NUM> and BOOT B <NUM>, so that the second memory cells <NUM> may be wear out earlier than the first memory cells <NUM>. Counting cycle times of the SLC can monitor the rest life of the second memory cells <NUM>. When the second memory cells <NUM> are wear out, the second memory cells <NUM> will be disabled in case of swap data loss. In some implementations, after the second memory cells <NUM> are disabled, the host <NUM> will not transfer swap data to the memory system. In other implementations, after the second memory cells <NUM> are disabled, the host <NUM> will still transfer swap data to the memory system, and the memory controller <NUM> will read the swap data from the first memory cells <NUM> according to the command provided by the host <NUM>.

<FIG> illustrates a flowchart of an exemplary method for operating a memory system, according to some aspects of the present disclosure. The memory system may be any suitable memory system disclosed herein, e.g., memory system <NUM> in <FIG> and <FIG>. Method <NUM> may be implemented partially or fully by memory system <NUM> as in <FIG> and <FIG>. It is understood that the operations shown in method may not be exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

Referring to <FIG>, method <NUM> starts at operation <NUM> in which a memory system (e.g., memory system <NUM> as in <FIG> and <FIG>) receives a first data and/or a second data from a host (e.g., host <NUM> in <FIG> and <FIG>). In some implementations, the first data is user data, and the second data is swap data from a host memory.

In some implementations, the memory system can comprise the memory controller and the memory device, the memory device can be the NAND flash memory. The memory device can comprise first memory cells and second memory cells.

In the operation <NUM>, as illustrated in <FIG>, writing the first data to the first memory cells of a memory device and/or a second data to the second memory cells of the memory device.

In some implementations, the memory controller is coupled between a host and the memory device, and the memory controller is configured to write a first data to the first memory cells and/or a second data to the second memory cells. In some implementations, the first memory cells can be the memory cells corresponding to big LUN, BOOT A and BOOT B, and the second memory cells can be the memory cells corresponding to swap LUN.

In some implementations, a command and the swap data can be sent to the memory controller, and the memory controller can write the swap data to the memory device according to the command of writing. In some implementations, the host processor also can send address signal to the memory controller, wherein the address signal can comprise a logical address, and the controller can transfer the logical address to a physical address based on a L2P address mapping table. The L2P address mapping table can be stored in a DRAM of the memory system, the NAND flash, or the host memory. The physical address points to the memory cells of the memory device, so that the memory controller can write the swap data to the target memory cells, and the memory controller can read the swap data from the target memory cells. In some implementations, when the storage capacity of the ZRAM is tight, the swap data corresponding to the inactive software or application can be transferred to the memory device from the ZRAM; when the inactive software or application is called, the corresponding swap data can be transferred to the ZRAM from the memory device. In this case, more softwares or applications can be ran in the same time.

In some implementations, the memory controller comprises a cache and a controller processor. The cache can be SRAM, DRAM, NAND flash, NOR flash or any other types of memory or electrical device. The controller processor can be a control unit (CU), or an arithmetic & logic unit (ALU). The cache is configured to receive the first data and/or the second data, and controller processor is configured to write the first data to the first memory cells according to a first address signal, and/or write the second data to the second memory cells according to a address signal. In some implementations, the address signal can comprise a first logical address points to the big LUN, BOOT A and BOOT B. The controller processor can transfer the first logical address to a first physical address based on a L2P address mapping table, and the first physical address is corresponding to the first memory cells. Thus, the memory controller writes user data to the first memory cells according to the address signal. In some implementations, the address signal can comprise a second logical address points to the swap LUN. The controller processor can transfer the second logical address to a second physical address based on a L2P address mapping table, and the second physical address is corresponding to the second memory cells. Thus, the memory controller writes swap data to the second memory cells according to the address signal.

In some implementations, the memory processor can count the cycle times of the second memory cells, and compare the cycle times with a lifetime threshold, when the writing time reaches the lifetime threshold, the processor can prohibit to write the second data to the second memory cells. The cycle times can be the program/erase times. The swap LUN is accessed more frequently than the big LUN, BOOT A and BOOT B, so that the second memory cells may be wear out earlier than the first memory cells. Counting cycle times of the SLC can monitor the rest life of the second memory cells. When the second memory cells are wear out, the second memory cells will be disabled in case of swap data loss. In some implementations, after the second memory cells are disabled, the host will not transfer swap data to the memory system. In other implementations, after the second memory cells are disabled, the host will still transfer swap data to the memory system, and the memory controller will write the swap data to the first memory cells according to the command provided by the host.

Referring to <FIG>, method <NUM> starts at operation <NUM> in which a memory system (e.g., memory system <NUM> as in <FIG> and <FIG>) receives a command of reading, a first address signal and/or a second address signal from a host (e.g., host <NUM> in <FIG> and <FIG>).

In the operation <NUM>, as illustrated in <FIG>, reading the first data from first memory cells of a memory device and/or a second data from second memory cells of the memory device, wherein the first data is user data, and the second data is swap data from a host memory.

In some implementations, the memory controller is coupled between a host and the memory device, and the memory controller is configured to read a first data from the first memory cells and/or a second data from the second memory cells. In some implementations, the first memory cells can be the memory cells corresponding to big LUN, BOOT A and BOOT B, and the second memory cells can be the memory cells corresponding to swap LUN.

In some implementations, a command and the swap data can be sent to the memory controller, and the memory controller can read the swap data from the memory device according to the command of reading. In some implementations, the host processor also can send address signal to the memory controller, wherein the address signal can comprise a logical address, and the controller can transfer the logical address to a physical address based on a L2P address mapping table. The L2P address mapping table can be stored in a DRAM of the memory system, the NAND flash, or the host memory. The physical address points to the memory cells of the memory device, so that the memory controller can read the swap data from the target memory cells, and the memory controller can read the swap data from the target memory cells. In some implementations, when the storage capacity of the ZRAM is tight, the swap data corresponding to the inactive software or application can be transferred to the memory device from the ZRAM; when the inactive software or application is called, the corresponding swap data can be transferred to the ZRAM from the memory device. In this case, more softwares or applications can be ran in the same time.

In some implementations, the memory controller comprises a cache and a controller processor. The cache can be SRAM, DRAM, NAND flash, NOR flash or any other types of memory or electrical device. The controller processor can be a control unit (CU), or an arithmetic & logic unit (ALU). The cache is configured to receive the first data and/or the second data, and controller processor is configured to read the first data from the first memory cells according to a first address signal, and/or read the second data from the second memory cells according to a address signal. In some implementations, the address signal can comprise a first logical address points to the big LUN, BOOT A and BOOT B. The controller processor can transfer the first logical address to a first physical address based on a L2P address mapping table, and the first physical address is corresponding to the first memory cells. Thus, the memory controller reads user data from the first memory cells according to the address signal. In some implementations, the address signal can comprise a second logical address points to the swap LUN. The controller processor can transfer the second logical address to a second physical address based on a L2P address mapping table, and the second physical address is corresponding to the second memory cells. Thus, the memory controller reads swap data from the second memory cells according to the address signal.

In some implementations, the memory processor can count the cycle times of the second memory cells, and compare the cycle times with a lifetime threshold, when the reading time reaches the lifetime threshold, the processor can prohibit to read the second data from the second memory cells. The cycle times can be the program/erase times. The swap LUN is accessed more frequently than the big LUN, BOOT A and BOOT B, so that the second memory cells may be wear out earlier than the first memory cells. Counting cycle times of the SLC can monitor the rest life of the second memory cells. When the second memory cells are wear out, the second memory cells will be disabled in case of swap data loss. In some implementations, after the second memory cells are disabled, the host will not transfer swap data to the memory system. In other implementations, after the second memory cells are disabled, the host will still transfer swap data to the memory system, and the memory controller will read the swap data from the first memory cells according to the command provided by the host.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

Claim 1:
A memory system (<NUM>), coupled to a host memory (<NUM>), comprising:
a memory device (<NUM>, <NUM>), comprising first memory cells (<NUM>) and second memory cells (<NUM>);
a memory controller (<NUM>), coupled to a host (<NUM>) and the memory device (<NUM>, <NUM>), configured to write a first data to the first memory cells (<NUM>) and/or a second data to the second memory cells (<NUM>), wherein the first data comprises user data, and the second data comprises swap data from the host memory (<NUM>), wherein the memory controller (<NUM>) comprising:
a cache (<NUM>), configured to receive the first data and/or the second data;
a processor, configured to, in response to a command of writing, write the first data to the first memory cells (<NUM>) according to a first address signal, and/or write the second data to the second memory cells (<NUM>) according to a second address signal,
wherein the processor further configured to: count cycle times of the second memory cells (<NUM>); characterized by:
when the cycle times is greater than or equal to a lifetime threshold, the operation (<NUM>, <NUM>, <NUM>, <NUM>) of writing the second data to the second memory cells (<NUM>) is prohibited.