Patent Description:
Error-correcting code (ECC) protection of dynamic random access memory (DRAM) is traditionally implemented using extra "out-of-band" data bits (e.g., <NUM> bits of data plus <NUM> bits of parity). This approach is costly due to the requirement for one or more DRAM components for storing the ECC data and the additional interface input/output (IO) pins.

In addition, bus structures have been found to be unsuitable for some system on chip (SoC) integrated circuits (SoCs). With increases in circuit integration, transactions can become blocked and increased capacity can create signaling problems. In place of a bus structure, a network on chip (NoC) can be used to support data communications between components of the SoC.

A NoC generally includes a collection of switches that route packets from source circuits ("sources") on the chip to destination circuits ("destinations") on the chip. The layout of the switches in the chip supports packet transmission from the desired sources to the desired destinations. A packet may traverse multiple switches in transmission from a source to a destination. Each switch can be connected to one or more other switches in the network and routes an input packet to one of the connected switches or to the destination.

<CIT>) describes an apparatus for transfer of data elements between a bus controller, such as a CPU, and a memory controller. An address translator is arranged to receive a write address from the CPU, to modify the write address and to send the modified write address to the memory controller. An ECC calculator is arranged to receive write input data associated with the write address, from the CPU, and to generate an error correction code on the basis of the write input data. A concatenator is arranged to receive the write input data from the CPU, and to receive the error correction code from the ECC calculator, and to concatenate the write input data and the error correction code to obtain write output data, and to send the write output data to the memory controller.

Techniques for an inline error-correcting code (ECC) function for a system-on-chip (SoC) are described. According to a first aspect of the disclosure, there is provided an integrated circuit (IC) comprising: a network-on-chip (NoC), the NoC including NoC master units, NoC slave units, and a network connecting the NoC master units to the NoC slave units; a master device coupled to the NoC; a memory controller coupled to the NoC configured to control a memory coupled to the IC, and wherein the NoC is configured to route memory transactions between the master device and the memory controller; and an inline error-correcting code (ECC) circuit coupled to the NoC and to the master device and the memory controller via the NoC, the ECC circuit configured to receive read and write transactions from the master device that target the memory via the NoC, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller via the NoC.

According to a second aspect of the disclosure, there is provided a method of memory management in an integrated circuit (IC) having a network-on-chip, NoC, the NoC including NoC master units, NoC slave units, and a network connecting the NoC master units to the NoC slave units, the method comprising: receiving a transaction from a master device at an inline error-correcting code (ECC) circuit through the network-on-chip (NoC), the transaction targeting a memory coupled to the IC, wherein a memory controller is configured to control the memory, and wherein the master device and the memory controller are coupled to the NoC, and the ECC circuit is coupled to the master device and the memory controller via the NoC; determining ECC data based on the transaction at the inline ECC circuit; and providing, from the ECC circuit, one or more outgoing transactions to a memory controller through the NoC.

In an example, an integrated circuit (IC) includes a processing system; a programmable logic region; a network-on-chip (NoC) coupling the processing system and the programmable logic region; a master device coupled to the NoC; a memory controller coupled to the NoC configured to control a memory coupled to the IC; and an inline error-correcting code (ECC) circuit coupled to the NoC, the ECC circuit configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.

These and other aspects may be understood with reference to the following detailed description.

So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope.

It is contemplated that elements of one example may be beneficially incorporated in other examples.

Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. In addition, an illustrated example need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated or if not so explicitly described.

<FIG> is a block diagram depicting a system-on-chip (SoC) <NUM> according to an example. The SoC <NUM> is an integrated circuit (IC) comprising a processing system <NUM>, a network-on-chip (NoC) <NUM>, inline error-correcting code (ECC) circuitry <NUM>, and one or more programmable regions <NUM>. The SoC <NUM> can be coupled to external circuits, such as a nonvolatile memory (NVM) <NUM> and dynamic random access memory (DRAM) <NUM>. In an example, the processing system <NUM> includes one or more memory controllers <NUM> for controlling the NVM <NUM> and/or the DRAM <NUM>. In another example, the programmable logic region(s) <NUM> include one or more memory controller(s) <NUM>, implemented as either hardened circuits or as configurable logic, for controlling the NVM <NUM> and/or the DRAM <NUM>. In still other examples, the SoC <NUM> includes both the memory controller(s) <NUM> and the memory controller(s) <NUM>.

The NVM <NUM> can store data that can be loaded to the SoC <NUM> for configuring the SoC <NUM>, such as configuring the NoC <NUM> and the programmable logic region(s) <NUM>. The DRAM <NUM> can store data used by the various circuits in the SoC <NUM>, including the processing system <NUM> and any circuits configured in the programmable logic regions <NUM>. Examples of the processing system <NUM>, the NoC <NUM>, and the programmable logic region(s) <NUM> are described below. In general, the processing system <NUM> is connected to the programmable logic region(s) <NUM> through the NoC <NUM>.

The inline ECC circuitry <NUM> provides an inline ECC function such that an additional ECC component is not required on the DRAM <NUM>. In some techniques, an inline ECC function can be implemented as part of the memory controller(s) <NUM> and/or the memory controller(s) <NUM>. However, in examples described herein, the inline ECC function is implemented as a separate circuit (the inline ECC circuitry <NUM>) attached to the NoC <NUM>. This provides for a modular approach, which decouples the complex DRAM controller circuitry from the inline ECC function. This technique can be used with hardened DRAM controllers, soft DRAM controllers (e.g., DRAM controllers configured in the programmable logic region(s) <NUM>), as well as with other types of memories (e.g., static RAM (SRAM) or any other type of RAM. The inline ECC circuitry <NUM> can be added or removed from any system implementation used in the SoC <NUM> with minimal impact. The inline ECC circuitry <NUM> also provides more flexibility as to where and how the ECC data is stored.

<FIG> is a block diagram depicting the NoC <NUM> according to an example. The NoC <NUM> includes NoC master units (NMUs) <NUM>, NoC slave units (NSUs) <NUM>, a network <NUM>, NoC peripheral interconnect (NPI) <NUM>, and registers (Regs) <NUM>. Each NMU <NUM> is an ingress circuit that connects a master endpoint to the NoC <NUM>. Each NSU <NUM> is an egress circuit that connects the NoC <NUM> to a slave endpoint. The NMUs <NUM> are connected to the NSUs <NUM> through the network <NUM>. In an example, the network <NUM> includes NoC packet switches <NUM> and routing <NUM> between the NoC packet switches <NUM>. Each NoC packet switch <NUM> performs switching of NoC packets. The NoC packet switches <NUM> are connected to each other and to the NMUs <NUM> and NSUs <NUM> through the routing <NUM> to implement a plurality of physical channels. The NoC packet switches <NUM> also support multiple virtual channels per physical channel. The NPI <NUM> includes circuitry to program the NMUs <NUM>, NSUs <NUM>, and NoC packet switches <NUM>. For example, the NMUs <NUM>, NSUs <NUM>, and NoC packet switches <NUM> can include registers <NUM> that determine functionality thereof. The NPI <NUM> includes interconnect coupled to the registers <NUM> for programming thereof to set functionality. Configuration data for the NoC <NUM> can be stored in the NVM <NUM> and provided to the NPI <NUM> for programming the NoC <NUM>.

<FIG> is a block diagram depicting a memory system <NUM> according to an example. The memory system <NUM> includes one or more master device(s) <NUM>, the NoC <NUM>, one or more memory controllers <NUM>, the inline ECC circuitry <NUM>, and memory <NUM>. The master device(s) <NUM> are circuits in the SoC <NUM>, such as circuits in the processing system <NUM> or circuits in the programmable logic region(s) <NUM> (e.g., hardened circuits or configured circuits). The master device(s) <NUM> are coupled to NMUs <NUM> in the NoC <NUM>. The memory controller(s) <NUM> are disposed in the processing system <NUM> and/or the programmable logic region(s) <NUM>. The memory controller(s) <NUM> are configured to control the memory <NUM>. The memory <NUM> can include one or more memory modules, such as one or more DRAM modules, SRAM modules, and/or other types of memory modules. The NoC <NUM> routes memory transactions (e.g., read and write transactions) between the master device(s) <NUM> and the memory controller(s) <NUM>.

In operation, one or more address ranges in the address space of the SoC <NUM> may be selected to be ECC-protected, while other portions of the address space can remain unprotected. Memory transactions to the unprotected regions may be routed directly between the master device(s) <NUM> and the memory controller(s) <NUM> via the NoC <NUM>. Memory transactions to the ECC-protected regions are routed via the inline ECC circuitry <NUM>, which manages the generation and checking of the ECC data in a manner that is transparent to both the master device(s) <NUM> and the memory controller(s) <NUM> (i.e., slave devices).

<FIG> is a method <NUM> of processing an ECC write transaction according to an example. The method <NUM> begins at step <NUM>, where the inline ECC circuitry <NUM> receives the write transaction from a master device <NUM>. The write transaction includes data to be written to an addressed location in the memory <NUM>. At step <NUM>, the inline ECC circuitry <NUM> computes ECC data based on the data to be written (e.g., ECC parity data). At step <NUM>, the inline ECC circuitry <NUM> generates one or more outgoing transactions to write both the original data and the ECC data to one or more destinations. In an example, at step <NUM>, the inline ECC circuitry <NUM> intersperses the ECC data with the original data in the same memory region of the memory <NUM>. In such case, the inline ECC circuitry <NUM> can generate a single outgoing transaction. For example, if the memory <NUM> is accessed in pages, both the original data and the ECC data can be stored in the same page(s).

In another example, at step <NUM>, the inline ECC circuitry <NUM> stores the ECC data in a separate memory region in the same memory or separate memory module from the original data. In such case, the inline ECC circuitry <NUM> generates one transaction for the original data and another transaction to write the ECC data. For example, separate memory regions can be separate pages in the same memory. If a separate memory module is used, the separate memory module can be of the same type or a different type than the memory module used to store the original data.

<FIG> is a flow diagram depicting a method <NUM> of processing a read transaction according to an example. The method <NUM> begins at step <NUM>, where the inline ECC circuitry <NUM> receives the read transaction from a master device <NUM>. The read transaction includes an address in the memory <NUM> from which to read data. At step <NUM>, the line ECC circuitry <NUM> generates one or more outgoing transactions to read both the original data and the ECC data from their respective storage locations. As noted above, the ECC data can be stored in the same memory region as the original data, in a different memory region, or in a different memory module. The inline ECC circuitry <NUM> generates one or more transactions for reading both the original data and the ECC data.

At step <NUM>, the line ECC circuitry <NUM> computes the ECC syndromes used to detect and correct errors based on the ECC data and the original data. At step <NUM>, the ECC circuitry <NUM> handles any errors in the original data based on the computed ECC syndromes. At step <NUM>, the inline ECC circuitry <NUM> generates a response to the read transaction that includes only the requested data and sends the response to the master device <NUM>. The ECC function is transparent to the master device <NUM> and the memory controller <NUM>.

<FIG> is a block diagram depicting a programmable IC <NUM> according to an example in which the inline ECC circuitry <NUM> described herein can be used. The programmable IC <NUM> includes programmable logic <NUM>, configuration logic <NUM>, and configuration memory <NUM>. The programmable IC <NUM> can be coupled to external circuits, such as nonvolatile memory <NUM>, DRAM <NUM>, and other circuits <NUM>. The programmable logic <NUM> includes logic cells <NUM>, support circuits <NUM>, and programmable interconnect <NUM>. The logic cells <NUM> include circuits that can be configured to implement general logic functions of a plurality of inputs. The support circuits <NUM> include dedicated circuits, such as transceivers, input/output blocks, digital signal processors, memories, and the like. The logic cells and the support circuits <NUM> can be interconnected using the programmable interconnect <NUM>. Information for programming the logic cells <NUM>, for setting parameters of the support circuits <NUM>, and for programming the programmable interconnect <NUM> is stored in the configuration memory <NUM> by the configuration logic <NUM>. The configuration logic <NUM> can obtain the configuration data from the nonvolatile memory <NUM> or any other source (e.g., the DRAM <NUM> or from the other circuits <NUM>). In some examples, the programmable IC <NUM> includes a processing system <NUM>. The processing system <NUM> can include microprocessor(s), memory, support circuits, IO circuits, and the like.

<FIG> is a block diagram depicting a System-on-Chip (SoC) implementation of the programmable IC <NUM> according to an example. In the example, the programmable IC <NUM> includes the processing system <NUM> and the programmable logic <NUM>. The processing system <NUM> includes various processing units, such as a real-time processing unit (RPU) <NUM>, an application processing unit (APU) <NUM>, a graphics processing unit (GPU) <NUM>, a configuration and security unit (CSU) <NUM>, a platform management unit (PMU) <NUM>, and the like. The processing system <NUM> also includes various support circuits, such as on-chip memory (OCM) <NUM>, transceivers <NUM>, peripherals <NUM>, interconnect <NUM>, DMA circuit <NUM>, memory controller <NUM>, peripherals <NUM>, and multiplexed IO (MIO) circuit <NUM>. The processing units and the support circuits are interconnected by the interconnect <NUM>. The PL <NUM> is also coupled to the interconnect <NUM>. The transceivers <NUM> are coupled to external pins <NUM>. The PL <NUM> is coupled to external pins <NUM>. The memory controller <NUM> is coupled to external pins <NUM>. The MIO <NUM> is coupled to external pins <NUM>. The PS <NUM> is generally coupled to external pins <NUM>. The APU <NUM> can include a CPU <NUM>, memory <NUM>, and support circuits <NUM>. The APU <NUM> can include other circuitry, including L1 and L2 caches and the like. The RPU <NUM> can include additional circuitry, such as L1 caches and the like. The interconnect <NUM> can include cache-coherent interconnect or the like.

Referring to the PS <NUM>, each of the processing units includes one or more central processing units (CPUs) and associated circuits, such as memories, interrupt controllers, direct memory access (DMA) controllers, memory management units (MMUs), floating point units (FPUs), and the like. The interconnect <NUM> includes various switches, busses, communication links, and the like configured to interconnect the processing units, as well as interconnect the other components in the PS <NUM> to the processing units.

The OCM <NUM> includes one or more RAM modules, which can be distributed throughout the PS <NUM>. For example, the OCM <NUM> can include battery backed RAM (BBRAM), tightly coupled memory (TCM), and the like. The memory controller <NUM> can include a DRAM interface for accessing external DRAM. The peripherals <NUM>, <NUM> can include one or more components that provide an interface to the PS <NUM>. For example, the peripherals <NUM> can include a graphics processing unit (GPU), a display interface (e.g., DisplayPort, high-definition multimedia interface (HDMI) port, etc.), universal serial bus (USB) ports, Ethernet ports, universal asynchronous transceiver (UART) ports, serial peripheral interface (SPI) ports, general purpose IO (GPIO) ports, serial advanced technology attachment (SATA) ports, PCle ports, and the like. The peripherals <NUM> can be coupled to the MIO <NUM>. The peripherals <NUM> can be coupled to the transceivers <NUM>. The transceivers <NUM> can include serializer/deserializer (SERDES) circuits, MGTs, and the like.

<FIG> illustrates a field programmable gate array (FPGA) implementation of the programmable IC <NUM> that includes a large number of different programmable tiles including transceivers <NUM>, configurable logic blocks ("CLBs") <NUM>, random access memory blocks ("BRAMs") <NUM>, input/output blocks ("IOBs") <NUM>, configuration and clocking logic ("CONFIG/CLOCKS") <NUM>, digital signal processing blocks ("DSPs") <NUM>, specialized input/output blocks ("I/O") <NUM> (e.g., configuration ports and clock ports), and other programmable logic <NUM> such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. The FPGA can also include PCle interfaces <NUM>, analog-to-digital converters (ADC) <NUM>, and the like.

In some FPGAs, each programmable tile can include at least one programmable interconnect element ("INT") <NUM> having connections to input and output terminals <NUM> of a programmable logic element within the same tile, as shown by examples included at the top of <FIG>. Each programmable interconnect element <NUM> can also include connections to interconnect segments <NUM> of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element <NUM> can also include connections to interconnect segments <NUM> of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments <NUM>) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments <NUM>) can span one or more logic blocks. The programmable interconnect elements <NUM> taken together with the general routing resources implement a programmable interconnect structure ("programmable interconnect") for the illustrated FPGA.

In an example implementation, a CLB <NUM> can include a configurable logic element ("CLE") <NUM> that can be programmed to implement user logic plus a single programmable interconnect element ("INT") <NUM>. A BRAM <NUM> can include a BRAM logic element ("BRL") <NUM> in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile <NUM> can include a DSP logic element ("DSPL") <NUM> in addition to an appropriate number of programmable interconnect elements. An lOB <NUM> can include, for example, two instances of an input/output logic element ("IOL") <NUM> in addition to one instance of the programmable interconnect element <NUM>. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element <NUM> typically are not confined to the area of the input/output logic element <NUM>.

In the pictured example, a horizontal area near the center of the die (shown in <FIG>) is used for configuration, clock, and other control logic. Vertical columns <NUM> extending from this horizontal area or column are used to distribute the clocks and configuration signals across the breadth of the FPGA.

Some FPGAs utilizing the architecture illustrated in <FIG> include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic.

Note that <FIG> is intended to illustrate only an exemplary FPGA architecture. For example, the numbers of logic blocks in a row, the relative width of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top of <FIG> are purely exemplary. For example, in an actual FPGA more than one adjacent row of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA.

An integrated IC is provided. Such an IC includes: a network-on-chip (NoC), the NoC including NoC master units, Noc slave units, and a network connecting the NoC master units to the NoC slave units;.

Some such IC, the inline ECC circuit may be configured to: receive a write transaction from the master device; compute ECC data based on data in the write transaction; and generate one or more outgoing transactions to write both the data and the ECC data to one or more destinations in the memory.

In some such IC, the one or more outgoing transactions may include a single outgoing transaction to write both the data and the ECC data to a region in a module of the memory.

In some such IC, the one or more outgoing transactions may include a first outgoing transaction to write the data to a first region of a module of the memory and a second outgoing transaction to write the data to a second region in the module of the memory.

In some such IC, the one or more outgoing transactions may include a first outgoing transaction to write the data to a first module of the memory and a second outgoing transaction to write the data to a second module of the memory.

In some such IC, the inline ECC circuitry may be configured to: receive a read transaction from the master device; generate one or more outgoing transactions to read both data and the ECC data from respective storage locations in the memory; compute ECC syndromes from the ECC data; and generate a response to the read transaction that includes the data.

In some such IC, the inline ECC circuitry may be configured to: handle one or more errors in the data using the ECC syndromes.

A method of memory management in an IC having a network-on-chip (NoC) is provided, the NoC including NoC master units, NoC slave units, and a network connecting the NoC master units to the NoC slave units. The method comprises:.

In some such method, the transaction may be a write transaction, wherein the ECC data may be determined based on data in the write transaction, and wherein the one or more outgoing transactions may be configured to write both the data and the ECC data to one or more destinations in the memory.

In some such method, the one or more outgoing transactions may include a single outgoing transaction to write both the data and the ECC data to a region in a module of the memory.

In some such method, the one or more outgoing transactions may include a first outgoing transaction to write the data to a first region of a module of the memory and a second outgoing transaction to write the data to a second region in the module of the memory.

In some such method, the one or more outgoing transactions may include a first outgoing transaction to write the data to a first module of the memory and a second outgoing transaction to write the data to a second module of the memory.

In some such method, the transaction may be a read transaction, and wherein the one or more outgoing transactions may be configured to read both data and the ECC data from respective storage locations in the memory, and wherein the method further comprises: computing ECC syndromes from the ECC data; and
generating a response to the read transaction that may include the data. In some such method, the method further comprises: handling one or more errors in the data using the ECC syndromes.

In yet another example, an IC may be provided. Such an IC may include), comprising: a processing system; a programmable logic region; a network-on-chip (NoC) coupling the processing system and the programmable logic region; a master device coupled to the NoC; a memory controller coupled to the NoC configured to control a memory coupled to the IC; and an inline error-correcting code (ECC) circuit coupled to the NoC, the ECC circuit configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.

In such an IC, the master device may be disposed in the processing system.

In such an IC, the master device may be disposed in the programmable logic region.

In such an IC, the master device may be configured in the programmable logic region.

In such an IC, the inline ECC circuit may be configured to: receive a write transaction from the master device; compute ECC data based on data in the write transaction; and generate one or more outgoing transactions to write both the data and the ECC data to one or more destinations in the memory.

Claim 1:
An integrated circuit, IC, comprising:
a network-on-chip, NoC (<NUM>), the NoC (<NUM>) including NoC master units (<NUM>), NoC slave units (<NUM>), and a network (<NUM>) connecting the NoC master units (<NUM>) to the NoC slave units (<NUM>);
a master device (<NUM>) coupled to a NoC master unit (<NUM>) of the NoC (<NUM>);
a memory controller (<NUM>) coupled to the NoC (<NUM>) and configured to control a memory coupled to the IC, and wherein the NoC is configured to route memory transactions between the master device and the memory controller; and
an inline error-correcting code, ECC, circuit (<NUM>) coupled to the NoC (<NUM>) and to the master device and the memory controller via the NoC, the ECC circuit (<NUM>) configured to receive read and write transactions from the master device (<NUM>) that target the memory via the NoC, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller (<NUM>) via the NoC.