Patent Description:
Accordingly, it may be understood that these statements are to be read in this light, and not as admissions of prior art.

Integrated circuit devices may be utilized for a variety of purposes or applications and programmable logic devices may be utilized to perform these functions. The design of a programmable logic device may be limited by the amount of hardware resources available. For example, an FPGA device may be used to emulate an ASIC device with non-destructive readback and writeback capabilities. One way of doing this involves adding dedicated shadow registers to the FPGA. These dedicated shadow registers, however, may increase power cost and take up significant area on the integrated circuit.

<CIT> relates to an apparatus and method for synchronizing and tracking an input data stream and for generating a synchronous clock therefrom. Th apparatus comprises means for generating a plurality of clock signals oscillating at substantially the same frequency, but with different phases; a plurality of delay lines having a common data input for receiving said input data stream, each delay line having multiple delay elements connected in series and having a common clock input for receiving one of said clock signals for clocking data of said data stream along said delay line in a direction away from said common data input; means for detecting which of said plurality of delay lines said data from said data stream is propagating therein; and means for generating the synchronous clock based on one of said clock signals that clocks the delay line that data from said data stream is propagating therein.

<CIT> discloses a digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.

The dissertation submitted by <NPL>, demonstrates that hardware debugging systems for FPGA-based designs can be realized by developing such a system for FPGA-based custom computing machines (FCCMs) using the JHDL design environment and other tools such as JBits and JRoute. This dissertation also demonstrates the use of FPGA configuration readback for providing FPGA design observability support for hardware debuggers as well as the use of design modification or instrumentation to improve design observability, controllability, and execution control.

Advantageous embodiments are subject to the dependent claims.

The terms "including" and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to "some embodiments," "embodiments," "one embodiment," or "an embodiment" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. Furthermore, the phrase A "based on" B is intended to mean that A is at least partially based on B. Moreover, the term "or" is intended to be inclusive (e.g., logical OR) and not exclusive (e.g., logical XOR). In other words, the phrase A "or" B is intended to mean A, B, or both A and B.

Programmable logic fabric of an integrated circuit device may be programmed to implement a programmable circuit design to perform a wide range of functions and operations. The programmable logic fabric may include configurable blocks of programmable logic (e.g., sometimes referred to as logic array blocks (LABs) or configurable logic blocks (CLBs)) that have lookup tables (LUTs) that can be configured to operate as different logic elements based on the configuration data programmed into memory cells in the blocks.

As used herein, "ASIC emulation" refers to implementing at least a portion of an application-specific integrated circuit (ASIC) circuit design into another programmable logic device (e.g., an FPGA) in order to validate the functionality of the ASIC circuit design. The present systems and techniques relate to embodiments of systems and methods for non-destructive readback and writeback for programmable logic devices during ASIC emulation. Integrated circuit devices may be utilized for a variety of purposes or applications and programmable logic devices may be utilized to perform these functions. The design of a programmable logic device may be limited by the amount of hardware resources available. For example, an FPGA device may be used to emulate an ASIC device with non-destructive readback and writeback capabilities. Shadow registers store data and dedicated shadow registers may be added to the FPGA which increase power cost and take up significant area. As such, techniques which do not require dedicated shadow registers may increase power savings and available hardware resources on the FPGA.

With this in mind, <FIG> illustrates a block diagram of a system <NUM> that may implement arithmetic operations using components of an integrated circuit device, such as components of a programmable logic device (e.g., a configurable logic block, an adaptive logic module, a DSP block). A designer may desire to implement functionality, such as the implementation operations of this disclosure, on an integrated circuit device <NUM> (such as a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a programmable logic array (PLA), and so forth. ) In some cases, the designer may specify a high-level program to be implemented, such as an OpenCL program, which may enable the designer to more efficiently and easily provide programming instructions to configure a set of programmable logic cells for the integrated circuit device <NUM> without specific knowledge of low-level hardware description languages (e.g., Verilog or VHDL). For example, because OpenCL is quite similar to other high-level programming languages, such as C++, designers of programmable logic familiar with such programming languages may have a reduced learning curve by avoiding learning unfamiliar low-level hardware description languages to implement new functionalities in the integrated circuit device <NUM>.

The designers may implement their high-level designs using design software <NUM>, such as a version of Intel Quartus by INTEL CORPORATION. The design software <NUM> may use a compiler <NUM> to convert the high-level program into a lower-level description. The compiler <NUM> may provide machine-readable instructions representative of the high-level program to a host <NUM> and the integrated circuit device <NUM>. The host <NUM> may receive a host program <NUM> which may be implemented by the kernel programs <NUM>. To implement the host program <NUM>, the host <NUM> may communicate instructions from the host program <NUM> to the integrated circuit device <NUM> via a communications link <NUM>, which may be, for example, direct memory access (DMA) communications or peripheral component interconnect express (PCIe) communications. In some embodiments, the kernel programs <NUM> and the host <NUM> may enable configuration of one or more DSP blocks <NUM> on the integrated circuit device <NUM>. The DSP block <NUM> may include circuitry to implement, for example, operations to perform matrix-matrix or matrix-vector multiplication for AI or non-AI data processing. The integrated circuit device <NUM> may include many (e.g., hundreds or thousands) of the DSP blocks <NUM>. Additionally, DSP blocks <NUM> may be communicatively coupled to another such that data outputted from one DSP block <NUM> may be provided to other DSP blocks <NUM>.

While the techniques described above refer to the application of a high-level program, in some embodiments, the designer may use the design software <NUM> to generate and/or to specify a low-level program, such as the low-level hardware description languages described above. Further, in some embodiments, the system <NUM> may be implemented without a separate host program <NUM>. Moreover, in some embodiments, the techniques described herein may be implemented in circuitry as a non-programmable circuit design. Thus, embodiments described herein are intended to be illustrative and not limiting.

Turning now to a more detailed discussion of the integrated circuit device <NUM>, <FIG> illustrates an example of the integrated circuit device <NUM> as a programmable logic device, such as a field-programmable gate array (FPGA). Further, it should be understood that the integrated circuit device <NUM> may be any other suitable type of integrated circuit device (e.g., an application-specific integrated circuit and/or application-specific standard product). As shown, the integrated circuit device <NUM> may have input/output circuitry <NUM> for driving signals off device and for receiving signals from other devices via input/output pins <NUM>. Interconnection resources <NUM>, such as global and local vertical and horizontal conductive lines and buses, may be used to route signals on integrated circuit device <NUM>. Additionally, interconnection resources <NUM> may include fixed interconnects (conductive lines) and programmable interconnects (e.g., programmable connections between respective fixed interconnects). Programmable logic <NUM> may include combinational and sequential logic circuitry. For example, programmable logic <NUM> may include look-up tables, registers, and multiplexers. In various embodiments, the programmable logic <NUM> may be configured to perform a custom logic function. The programmable interconnects associated with interconnection resources may be considered to be a part of the programmable logic <NUM>.

Programmable logic devices, such as the integrated circuit device <NUM>, may contain programmable elements <NUM> within the programmable logic <NUM>. For example, as discussed above, a designer (e.g., a customer) may program (e.g., configure) the programmable logic <NUM> to perform one or more desired functions. By way of example, some programmable logic devices may be programmed by configuring their programmable elements <NUM> using mask programming arrangements, which is performed during semiconductor manufacturing. Other programmable logic devices are configured after semiconductor fabrication operations have been completed, such as by using electrical programming or laser programming to program their programmable elements <NUM>. In general, programmable elements <NUM> may be based on any suitable programmable technology, such as fuses, antifuses, electrically-programmable read-only-memory technology, random-access memory cells, mask-programmed elements, and so forth.

Many programmable logic devices are electrically programmed. With electrical programming arrangements, the programmable elements <NUM> may be formed from one or more memory cells. For example, during programming, configuration data is loaded into the memory cells using pins <NUM> and input/output circuitry <NUM>. In one embodiment, the memory cells may be implemented as random-access-memory (RAM) cells. The use of memory cells based on RAM technology is described herein is intended to be only one example. Further, because these RAM cells are loaded with configuration data during programming, they are sometimes referred to as configuration RAM cells (CRAM). These memory cells may each provide a corresponding static control output signal that controls the state of an associated logic component in programmable logic <NUM>. For instance, in some embodiments, the output signals may be applied to the gates of metal-oxide-semiconductor (MOS) transistors within the programmable logic <NUM>.

<FIG> is a block diagram of an adaptive logic element <NUM> of the integrated circuit device <NUM> of <FIG>, in accordance with an embodiment of the present disclosure. The adaptive logic element <NUM> may include any suitable number of registers. As shown, the adaptive logic element <NUM> includes four user registers <NUM>, <NUM>, <NUM>, and <NUM>. Each register may be a storage unit and may store a single bit of data. Additionally, each register may receive a clock signal that may change the output of the register. In some embodiments, the clock signal may be a low-to-high transition of the clock signal. Registers <NUM>, <NUM> may form a first register pair and registers <NUM>, <NUM> may form a second register pair. Each register pair may function as a single register during ASIC emulation. In some embodiments, any suitable number (e.g., three registers, four registers, and so forth) may function as a single register during ASIC emulation. Register <NUM> and register <NUM> may be fast registers and registers <NUM>, <NUM> may be slow registers. As used herein, a "fast register" may be utilized for ASIC device-under-test (DUT) logic during ASIC emulation and a "slow register" may function as a shadow register by providing non-destructive register readback. According to the invention, the fast registers support a higher maximum frequency than a maximum frequency of the slow registers. According to the invention, the fast register operates at a higher frequency than a frequency of the slow register. The slow registers may be formed using circuitry that may take up less die space or may be less expensive than the fast registers. The slow registers are designed using high-VT (e.g., high threshold voltage) transistors for less power leakage, thereby reducing power consumption when compared to the fast registers. Hence, as will be discussed below, using register pairs that use a slow register (e.g., <NUM>) and a fast register (e.g., <NUM>) may efficiently enable non-destructive readback and writeback. However, if desired, the register pairs may be formed from two or more fast registers or two or more slow registers. According to the invention, the slow registers operate at a frequency less than a frequency of the fast registers.

The adaptive logic element <NUM> includes LAB clock signal <NUM> and design for test (DFT) clock signal <NUM>. Fast registers <NUM>, <NUM> receive the LAB clock signal <NUM> as a clock source. Each slow register, (e.g., slow register <NUM>, <NUM>) is connected to a corresponding multiplexer <NUM>. According to the invention, the multiplexer <NUM> receives the LAB clock signal <NUM> and the DFT clock signal <NUM> and selects the DFT clock signal <NUM> to provide as clock source for the slow registers <NUM>, <NUM>. Each register of the adaptive logic element <NUM> may be connected to a multiplexer to provide test data as input, such as multiplexer <NUM> connected to register <NUM>.

<FIG> is a block diagram of the adaptive logic element <NUM> of <FIG> performing a user data sampling operation during emulation readback, in accordance with an embodiment of the present disclosure. During the data sampling operation, data output from the fast registers <NUM>, <NUM> may be stored in the corresponding slow registers <NUM>, <NUM>. The fast registers <NUM>, <NUM> may receive the LAB clock signal <NUM> as a clock source. The fast registers <NUM>, <NUM> may be connected to multiplexers <NUM> that receive DFT unload signal <NUM> and select user data input signals <NUM>, <NUM>, respectively as output from the multiplexers <NUM>. The multiplexers <NUM> may receive an emulation signal <NUM> and the emulation signal <NUM> may instruct the multiplexers <NUM> to select the DFT clock signal <NUM> as output <NUM> received by the slow registers <NUM>, <NUM>. Test data output <NUM> from the fast register <NUM> may be received by the multiplexer <NUM> connected to the slow register <NUM>. The multiplexer <NUM> may receive DFT load signal <NUM> and may select the test data output <NUM> from the fast register <NUM> as input to the slow register <NUM>. The multiplexer <NUM> may receive the DFT load signal <NUM> and may select the test data output <NUM> from the fast register <NUM> as input to the slow register <NUM>. As such, the slow register <NUM> may store the test data output <NUM> and the slow register <NUM> may store the test data output <NUM>. The control and clock signals supplied to the registers of the adaptive logic element <NUM> during a data sampling operation may be based on a logic table, such as Table <NUM>. While Table <NUM> describes specific bit values for the DFT load signal <NUM>, DFT unload signal <NUM>, and emulation signal <NUM>, any suitable bit values, signal states, and/or polarities may be used.

<FIG> is a block diagram of the adaptive logic element <NUM> of <FIG> performing a shifting operation during emulation readback, in accordance with an embodiment of the present disclosure. The multiplexers <NUM> may select the DFT clock signal <NUM> as output <NUM> and the slow registers <NUM>, <NUM> may receive the DFT clock signal <NUM>. The fast registers <NUM>, <NUM> may include a multiplexer that receives DFT unload signal <NUM> and selects user data input signal <NUM>, <NUM>, respectively as output from the multiplexer. The multiplexer <NUM> may receive the DFT load signal <NUM> and select the test data output signal <NUM> from another slow register as data input signal for the slow register <NUM>. As such, the adaptive logic element <NUM> may shift data from another slow register to slow register <NUM>. The multiplexer <NUM> may select the test data output signal <NUM> from the slow register <NUM> and the slow register <NUM> may receive the test data output signal <NUM> as a test data input signal. Data previously stored in the slow register <NUM> may be shifted out as output signal <NUM>. As such, the adaptive logic element <NUM> may shift data from slow register <NUM> to slow register <NUM> and data from slow register <NUM> may be shifted out as output signal <NUM>. The control and clock signals supplied to the registers of the adaptive logic element <NUM> may be based on a logic table, such as Table <NUM>. While Table <NUM> describes specific bit values for the DFT load signal <NUM>, DFT unload signal <NUM>, and emulation signal <NUM>, any suitable bit values, signal states, and/or polarities may be used.

<FIG> is a block diagram of the adaptive logic element of <FIG> performing a shifting operation during emulation writeback, in accordance with an embodiment of the present disclosure. The multiplexers <NUM> may select the DFT clock signal <NUM> as output <NUM> and the slow registers <NUM>, <NUM> may receive the DFT clock signal <NUM>. The fast registers <NUM>, <NUM> may include a multiplexer that receives DFT unload signal <NUM> and selects user data input signal <NUM>, <NUM>, respectively as output from the multiplexer. The multiplexer <NUM> may receive the DFT load signal <NUM> and select the test output data signal <NUM> from another slow register as data input signal for the slow register <NUM>. As such, the adaptive logic element <NUM> may shift data from another slow register to slow register <NUM>. The multiplexer <NUM> may select the test data output signal <NUM> from the slow register <NUM> and the slow register <NUM> may receive the test data output signal <NUM> as a test data input signal. Data previously stored in the slow register <NUM> may be shifted out as output signal <NUM>. As such, the adaptive logic element <NUM> may shift data from slow register <NUM> to slow register <NUM> and data from slow register <NUM> may be shifted out as output signal <NUM>. As a result of the shifting operations in <FIG> and <FIG>, data previously stored in slow registers <NUM>, <NUM> may be shifted out. The control and clock signals supplied to the registers of the adaptive logic element <NUM> may be based on a logic table, such as Table <NUM>. While Table <NUM> describes specific bit values for the DFT load signal <NUM>, DFT unload signal <NUM>, and emulation signal <NUM>, any suitable bit values, signal states, and/or polarities may be used.

<FIG> is a block diagram of the adaptive logic element of <FIG> performing a writing operation during emulation writeback, in accordance with an embodiment of the present disclosure. The fast registers <NUM>, <NUM> may receive the LAB clock signal <NUM> as a clock source. The multiplexer <NUM> may receive DFT load signal <NUM> and the multiplexer <NUM> may select test data output signal <NUM> from the slow register <NUM> as test data input for the fast register <NUM>. As such, data stored in the slow register <NUM> may be output as test data output signal <NUM> and the adaptive logic element <NUM> writes the data to the fast register <NUM>. The multiplexer <NUM> may receive DFT load signal <NUM> and the multiplexer <NUM> may select test data output signal <NUM> from the slow register <NUM> as test data input for the fast register <NUM>. As such, data stored in the slow register <NUM> may be output as test data output signal <NUM> and the adaptive logic element <NUM> writes the data to the fast register <NUM>. The control and clock signals supplied to the registers of the adaptive logic element <NUM> during a writing operation may be based on a logic table, such as Table <NUM>. While Table <NUM> describes specific bit values for the DFT load signal <NUM>, DFT unload signal <NUM>, and emulation signal <NUM>, any suitable bit values, signal states, and/or polarities may be used.

<FIG> is a block diagram of a system <NUM> for ASIC emulation on an FPGA device, in accordance with an embodiment of the present disclosure. The system <NUM> may include readback/writeback peripheral <NUM> including register access interface <NUM>, control register <NUM>, and any number of additional registers <NUM>. The readback/writeback peripheral <NUM> may be communicatively coupled to readback/writeback controller <NUM>. For example, the readback/writeback controller <NUM> may communicate with control register <NUM> via register access interface <NUM>. The system <NUM> may also include pulse generator <NUM> and pulse generator <NUM> may generate single wave pulses. The pulse generator <NUM> may be communicatively coupled to the readback/writeback peripheral <NUM> via the control register <NUM>. In some embodiments, the system <NUM> may include pipeline registers <NUM>, <NUM> in core fabric <NUM>. The pipeline registers <NUM>, <NUM> may receive single wave pulses from the pulse generator <NUM> and may ensure sample request pulse <NUM> and DUT clock signal <NUM> generated by the DUT clock <NUM> have the same frequency. In some embodiments, the DUT clock signal <NUM> generated by the DUT clock <NUM> may have a frequency of up to six hundred MHz (e.g., up to one hundred MHz, up to two hundred MHz, up to three hundred MHz, and so forth). The DUT clock <NUM> may be communicative coupled to the pulse generator <NUM> and the core fabric <NUM> via clock distribution network <NUM>. The logic array block core fabric <NUM> may include multiplexer <NUM>, clock gate <NUM>, multiplexer <NUM>, first user register <NUM>, second user register <NUM>, first shadow register <NUM>, and second shadow register <NUM>. Multiplexer <NUM> may provide DUT clock signal to the first user register <NUM> and the second user register <NUM>. Local emulation manager <NUM> may include observation register <NUM> and first control register <NUM>, second control register <NUM>, and third control register <NUM>. First control register <NUM> may generate a clock override signal <NUM> and third control register <NUM> may generate a shift/load signal <NUM>. Configuration clock <NUM> may generate the emulation clock signal <NUM>.

The readback/writeback controller <NUM> may communicate with the control register <NUM> via the register access interface <NUM>. The readback/writeback controller <NUM> may set a sample request bit in the control register <NUM> to <NUM>. The pulse generator <NUM> may detect a rising edge of the sample request bit and may generate a sample request pulse <NUM>. The sample request pulse <NUM> may be synchronous with the DUT clock <NUM>. Additionally, the sample request pulse <NUM> may be high for one cycle. The clock gate <NUM> may receive the sample request pulse <NUM> and may generate a single DUT clock <NUM> pulse that multiplexer <NUM> may receive as input. As such, the shadow registers <NUM>, <NUM> may receive the single DUT clock <NUM> pulse as output <NUM> from multiplexer <NUM> and the shadow registers <NUM>, <NUM> may sample data from user registers <NUM>, <NUM>, respectively and the shadow registers <NUM>, <NUM> may operate at the same frequency as the user registers <NUM>, <NUM>. In certain embodiments, the shadow registers <NUM>, <NUM> may operate at a frequency equal to or less than a frequency of the user registers <NUM>, <NUM>.

Local emulation manager <NUM> may receive sample request pulse <NUM>, such as at observation register <NUM>. In response, local emulation manager <NUM> may generate clock override signal <NUM> via control register <NUM>. The multiplexer <NUM> may receive the clock override signal <NUM> and may select emulation clock <NUM> as output <NUM>. Additionally, the local emulation manager <NUM> may generate shift/load signal <NUM> via control register <NUM> and the shadow registers <NUM>, <NUM> may receive the shift/load signal <NUM>. As such, the shadow registers <NUM>, <NUM> may be configured into shift register mode and data stored in shadow register <NUM> may be shifted out as output <NUM>. The data stored in shadow register <NUM> may be shifted to shadow register <NUM> on a first pulse of the shadow register clock <NUM> and may be shifted out of shadow register <NUM> on a subsequent pulse of the shadow register clock <NUM>.

<FIG> is a timing diagram <NUM> of the system of <FIG>, in accordance with an embodiment of the present disclosure. Timing diagram <NUM> includes waveforms <NUM>, <NUM>. Waveform <NUM> depicts a state of a user register, such as user register <NUM> and waveform <NUM> depicts a state of a shadow register, such as shadow register <NUM>. As shown in timing diagram <NUM>, the shadow register may sample a state of the user register. For example, the sample request pulse <NUM> may be received by clock gate <NUM> and the clock gate <NUM> may generate a single pulse that multiplexer <NUM> may receive and provide as output <NUM>. The shadow register may sample the data, State A0, of the user register at the rising edge of the single pulse of the output <NUM>. The local emulation manager <NUM> may generate the clock override signal <NUM>. The shadow register may then receive shift/load signal <NUM> and the shift/load signal <NUM> may configure the shadow register into the shift register mode. As such, the shadow register may shift out the data stored in the shadow register.

The integrated circuit device <NUM> may be a data processing system or a component included in a data processing system. For example, the integrated circuit device <NUM> may be a component of a data processing system <NUM> shown in <FIG>. The data processing system <NUM> may include a host processor <NUM> (e.g., a central-processing unit (CPU)), memory and/or storage circuitry <NUM>, and a network interface <NUM>. The data processing system <NUM> may include more or fewer components (e.g., electronic display, user interface structures, application specific integrated circuits (ASICs)). The host processor <NUM> may include any suitable processor, such as an INTEL Xeon processor or a reduced-instruction processor (e.g., a reduced instruction set computer (RISC), an Advanced RISC Machine (ARM) processor) that may manage a data processing request for the data processing system <NUM> (e.g., to perform debugging, data analysis, encryption, decryption, machine learning, video processing, voice recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, spatial navigation, or the like). The memory and/or storage circuitry <NUM> may include random access memory (RAM), read-only memory (ROM), one or more hard drives, flash memory, or the like. The memory and/or storage circuitry <NUM> may hold data to be processed by the data processing system <NUM>. In some cases, the memory and/or storage circuitry <NUM> may also store configuration programs (bitstreams) for programming the integrated circuit device <NUM>. The network interface <NUM> may allow the data processing system <NUM> to communicate with other electronic devices. The data processing system <NUM> may include several different packages or may be contained within a single package on a single package substrate.

In one example, the data processing system <NUM> may be part of a data center that processes a variety of different requests. For instance, the data processing system <NUM> may receive a data processing request via the network interface <NUM> to perform ASIC emulation, debugging, error detection, data analysis, encryption, decryption, machine learning, video processing, voice recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, spatial navigation, digital signal processing, or some other specialized task.

Claim 1:
A method, comprising:
providing a first clock signal (<NUM>) having a first frequency from a first clock and a second clock signal (<NUM>) having a second frequency from a second clock on an adaptive logic element (<NUM>), providing the first clock signal (<NUM>) as a first clock source for a first register (<NUM>);
sampling first data from the first register (<NUM>); and
storing the first sampled data on a second register (<NUM>).
characterized by
selecting, at a multiplexer (<NUM>), the second clock signal (<NUM>) as a second clock source for the second register (<NUM>) out of the first clock signal (<NUM>) and the second clock signal (<NUM>), wherein the second frequency of the second clock signal is lower than the first frequency of the first clock signal; and
wherein sampling first data from the first register (<NUM>) and storing the first sampled data on the second register (<NUM>) is based on selecting the second clock signal (<NUM>) as the second clock source.