Patent Description:
Gallium nitride (GaN) and other wide band-gap nitride III based direct transitional semiconductor materials exhibit high break-down electric fields and avail high current densities. In this regard GaN based semiconductor devices are actively researched as an alternative to silicon based semiconductor devices in power and high frequency applications. For instance, a GaN HEMT may provide lower specific on resistance with higher breakdown voltage relative to a silicon power field effect transistor of commensurate area.

Power field effect transistors (FETs) can be enhancement mode or depletion mode. An enhancement mode device may refer to a transistor (e.g., a field effect transistor) which blocks current (i.e., which is off) when there is no applied gate bias (i.e., when the gate to source bias is zero). In contrast, a depletion mode device may refer to a transistor which allows current (i.e., which is on) when the gate to source bias is zero.

<CIT> describes field-plate structures for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact. A field-plate dielectric is disposed over the semiconductor substrate. An encapsulating dielectric is disposed over the gate contact, wherein the encapsulating dielectric covers a top surface of the gate contact. The source field plate is disposed over the field-plate dielectric in a field plate region, from which the encapsulating dielectric is absent.

<CIT> describes resistive field structures that provide electric field profiles when used with a semiconductor device. In one example, the structure is a field cage that is configured to be resistive, in which the potential changes significantly over the distance of the cage.

The present invention relates to a HEMT semiconductor device as defined by claim <NUM>.

Non-limiting and non-exhaustive embodiments of capacitance networks for enhancing high voltage operation of high electron mobility transistors (HEMTs) are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

It is noted that only the embodiments of <FIG> and <FIG> falls within the scope of the claimed invention. The other embodiments are however useful to understand it.

Corresponding reference characters indicate corresponding components throughout the several views of the drawings. For example, the dimensions of some of the elements and layers in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the teachings herein. Also, common but well-understood elements, layers, and/or process steps that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of capacitance networks for enhancing high voltage operation of high electron mobility transistors.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of capacitance networks for enhancing high voltage operation of high electron mobility transistors. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the teachings herein. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present disclosure.

In the context of the present application, when a transistor is in an "off-state" or "off' the transistor blocks current and/or does not substantially conduct current. Conversely, when a transistor is in an "on-state" or "on" the transistor is able to substantially conduct current. By way of example, in one embodiment, a high-voltage transistor comprises an N-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET) with the high-voltage being supported between the first terminal, a drain, and the second terminal, a source. In some embodiments an integrated controller circuit may be used to drive a power switch when regulating energy provided to a load. Also, for purposes of this disclosure, "ground" or "ground potential" refers to a reference voltage or potential against which all other voltages or potentials of an electronic circuit or Integrated circuit (IC) are defined or measured.

As described above, a HEMT and/or a GaN HEMT may provide lower specific on resistance with higher breakdown voltage relative to a silicon power field effect transistor of commensurate area. It has been found, however, that breakdown voltage of HEMTs and/or GaN HEMTs may be limited by non-uniform electric fields in a drift region. Thus, it may be desirable to find ways to distribute an electric field in the drift region so that it becomes uniform and/or substantially uniform.

Traditional approaches to distributing an electric field include using field plates. However, a traditional field plate design for a high voltage HEMT (e.g., a lateral high voltage HEMT) may be limited to providing a square electric field distribution along the drift region; moreover, the traditional field plate design may necessitate a thick dielectric to support a high breakdown voltage. This, in turn, may increase process cost and complexity. Accordingly, it may also be desirable to find ways to distribute an electric field without increasing process cost and complexity.

Capacitance networks for enhancing high voltage operation of high electron mobility transistors (HEMTs) are presented herein. A capacitance network, integrated and/or external, may be provided with a fixed number of capacitively coupled field plates to distribute the electric field in the drift region. The capacitively coupled field plates may advantageously be fabricated on the same metal layer to lower cost; and the capacitance network may be provided to control field plate potentials. The potentials on each field plate may be pre-determined through the capacitance network, resulting in a uniform, and/or a substantially uniform electric field distribution along the drift region.

<FIG> illustrates a simplified schematic 100a of a device cross section including a capacitance network <NUM>. The simplified schematic 100a depicts a semiconductor layer <NUM> which may comprise aluminum gallium nitride (AlGaN), gallium nitride (GaN), and/or a combination of both AlGaN and GaN. The simplified schematic 100a further depicts interconnect to a source, gate, and a drain. In one embodiment, interconnect layers may be identified as ohmic contacts <NUM>-<NUM>, a source field plate (SFP) <NUM>, a drain field plate (DFP) <NUM>, vias <NUM>-<NUM>, a first metal layer <NUM> (i.e., to the source), a first metal layer <NUM> (i.e., to the drain), vias <NUM>-<NUM>, a second metal layer <NUM> (i.e., to the source), and a second metal <NUM> (i.e., to the drain). Additionally, the gate interconnect may include a gate field plate <NUM>, a via <NUM>, and a first metal layer <NUM> (i.e., to the gate).

A drift region may exist along and/or near the surface (i.e., top) of semiconductor layer <NUM> between the gate (GATE) and the drain (DRAIN). Along the drift region, field plates <NUM>-<NUM> can be fabricated using the first metal layer so that the field plates <NUM>-<NUM> are disposed above the drift region of semiconductor layer <NUM>. The field plates <NUM>-<NUM> may advantageously be formed on the same metal layer (i.e., metal <NUM>) as first metal layers <NUM>-<NUM>, <NUM> so as to reduce process steps and/or cost.

The capacitance network <NUM> may be electrically connected to the field plates <NUM>-<NUM>, to ground (GND), and/or to the drain at one or more layer (e.g., at via <NUM>). Although the embodiment of <FIG> shows four field plates <NUM>-<NUM>, there may be greater or fewer than four field plates <NUM>-<NUM>. For instance, there may be just one field plate <NUM>.

The capacitance network <NUM> may be an external network and/or an internal (i.e., integrated) network which may be provided to adjust field plate potentials (i.e., field plate voltages). By adjusting the field plate potentials to known (i.e., selected) values, an electric field within the drift region of semiconductor layer <NUM> may be adjusted (i.e., distributed) in a controlled manner. In this way, the electric field may be distributed to be substantially uniform.

<FIG> illustrates a schematic 100b of a device cross section including a capacitance network <NUM>. Schematic 100b illustrates parasitic field plate capacitances C1-C4 and C11-C15. The parasitic field plate capacitances C1-C4 and C11-C15 may give rise to coupling such that field plates <NUM>-<NUM> are capacitively coupled. The capacitance network <NUM> may provide capacitors C21-C24 tailored to control and/or select field plate potentials (i.e., field plate voltages). The capacitors C21-C24 may be determined, at least in part, by simulation and/or by experiment so as to select the field plate potentials.

<FIG> illustrates a schematic 100c of a device cross section including a capacitance network <NUM> according to an embodiment. The capacitance network <NUM> includes additional impedances R1-R6 electrically coupled between ground (GND) and the drain (i.e., to via <NUM>). The impedances R1-R6 may be resistors, passive elements, and/or non-linear components (e.g., active field effect transistors) tailored to connect to the field plates <NUM>-<NUM>. In some embodiments the impedances R1-R6 may advantageously provide a discharge feature allowing charge on the field plates <NUM>-<NUM> to be removed and/or controlled.

<FIG> illustrates a schematic 200a of a device including a capacitance network <NUM>. Schematic 200a includes a transistor <NUM> having a gate G, source S, and drain D; and as schematically illustrated, field plates <NUM> may be electrically coupled between the gate G and drain D. Schematic 200a also shows additional information relating to system voltages. For instance, the capacitance network <NUM> may be coupled to ground (GND) and to the field plates <NUM> to provide field plate potentials VFP1-VFP4. In addition, a drain to source voltage VDS may be applied at the drain D. Also, a gate to source voltage VGS may be applied at the gate G; and the source S may be connected to ground (GND).

<FIG> illustrates a schematic 200b of a device including a capacitance network <NUM>. Field plates <NUM> include field plates <NUM>-<NUM> coupled with parasitic capacitances C30-C34. The capacitance network includes capacitors C35-C38 connected to the field plates <NUM>-<NUM>, respectively. The values of capacitors C35-C38 may be selected so as to control (i.e., to select) the field plate potentials VFP1-VFP4; and by selecting the field plate potentials VFP1-VFP4, one may control an electric field along a drift region of transistor <NUM>. The drift region of transistor <NUM> may be between the gate G and drain D; and there may be greater or fewer than four field plates <NUM>-<NUM>. Accordingly, there may also be greater or fewer than four capacitors C35-C38.

<FIG> illustrates a schematic 200c of a device including a capacitance network <NUM>. Schematic 200c illustrates an embodiment including a discharge network <NUM>. The discharge network <NUM> may also connect to field plates <NUM>.

<FIG> illustrates a schematic of a device 200d including a capacitance network <NUM>. As illustrated, the discharge network <NUM> may include impedances Z1-Z5 electrically coupled between the drain D and the gate G. The impedances are also electrically coupled to the field plates <NUM>-<NUM> so as to provide a discharge feature. In some embodiments the impedances Z1-Z5 may be implemented by active devices (e.g., field effect transistors). In other embodiments the impedances Z1-Z5 may be implemented by resistors and/or by passive components.

<FIG> illustrates a device cross section 300a including potential contours. The device cross section 300a may be that of a HEMT device including a source (S) <NUM>, a gate (G) <NUM>, and a drain (D) <NUM>. The device cross section 300a also shows field plates <NUM>-<NUM> located between the gate <NUM> and drain <NUM> along an "X" axis. The potential contours may be derived from a simulation of the device cross section 300a.

<FIG> illustrates a device cross section 300b including potential contours. The potential contours are illustrated with lines and may also be derived using a device simulator.

<FIG> illustrates a device cross section 300c including potential contours. Device cross section 300c shows additional details relating to device materials and drift region. For instance, device cross section 300c shows a high voltage region <NUM> corresponding to where the field plates <NUM>-<NUM> are formed over a drift region (i.e., a high voltage region). The field plates <NUM>-<NUM> may also labelled as field plates f1-f3.

The device cross section 300c also delineates a GaN buffer layer <NUM> and an aluminum oxide (Al2O3) layer <NUM>. In device cross section 300c, simulation values of electrostatic potential (V) may be illustrated according to a color coded key (e.g., with values ranging between <NUM> and <NUM>,<NUM> volts).

<FIG> may correspond with a simulated potential contour for a 1200V device with three capacitively coupled field plates <NUM>-<NUM> (f1-f3). Assigning an adjusting external capacitance to each field plate, as means to emulate capacitance network, the device of <FIG> may be shown to support 1200V with a uniform 2DEG electric field in the extended HV region (see, e.g., <FIG>).

<FIG> illustrates plots <NUM>, <NUM> of potential and electric field as a function of distance along a drift region. The embodiment may correspond with the simulation results of device cross sections 300a-c. Additionally, plot <NUM> may correspond with potential and plot <NUM> may correspond with electric field. As illustrated, between about seventeen microns and thirty five microns, plot <NUM> is substantially uniform so as to improve plot <NUM> as a function of distance. In this way the maximum value of potential (i.e., plot <NUM>) reaches approximately <NUM> volts (V).

<FIG> illustrates plots <NUM>, <NUM> of potential and electric field as a function of distance along a drift region. <FIG> further delineates the location of the high voltage region <NUM> corresponding with the high voltage region <NUM>. As illustrated by plot <NUM>, electric field is substantially uniform within the high voltage region <NUM> (e.g., within the drift region).

<FIG> illustrates plots <NUM>, <NUM> of potential and electric field as a function of distance along a drift region. <FIG> can be similar to <FIG> except it includes additional labels showing the locations of the field plates <NUM>-<NUM> (f1-f3). For instance, plot <NUM>, corresponding to potential, shows plateaus <NUM>-<NUM> corresponding to the locations of field plates <NUM>-<NUM> (f1-f3).

As discussed above, the device may support <NUM> volts with uniform 2DEG electric field in the extended high voltage (HV) region <NUM>. A uniform electrical field in the two-dimensional electron gate (2DEG) region can advantageously provide a stable dynamic on-resistance (Rdson) in a GaN device.

<FIG> illustrates plots corresponding to field plate potentials <NUM>-<NUM> as a function of drain voltage. The embodiment may also correspond with the simulation results of device cross sections 300a-c. The field plate potentials <NUM>-<NUM> are provided as a function of drain voltage Vdrain and may show how a coupling ratio of each field plate <NUM>-<NUM> (e.g., field plates f1-f3) can be calculated by a ratio of a field plate potential to drain voltage.

<FIG> illustrates a top layout view <NUM> of a device. The top layout view <NUM> shows an active region <NUM> with stripes oriented parallel to a direction YP. As one of skill in the art may understand, transistors and/or semiconductor devices may be fabricated to have active regions wherein current, voltage, and/or power may be actively controlled; additionally there may be interconnect layers including pad layers adjacent to the active region(s). In this regard, the top layout view <NUM> also shows where interconnect (e.g., metallization and/or pad layers) may be located to connect to a drain D and a source S. For instance, pads <NUM>-<NUM> may be drain pads <NUM>-<NUM> allowing connection (i.e., electrical connection) to drain stripes and/or segments within the active region <NUM>; and pad <NUM> may be a source pad <NUM> allowing connection (i.e., electrical connection) to source stripes and/or segments within the active region <NUM>. Additionally, pad <NUM> may be a gate pad <NUM> allowing connection (i.e., electrical connection) to gate regions within the active region <NUM>.

In one embodiment a capacitance network (e.g., capacitance network <NUM> and/or capacitance network <NUM>) may be placed outside of the active region <NUM>. For instance, as shown in <FIG>, capacitance network <NUM> may be placed outside of the active region <NUM> near the drain pad <NUM>. Additionally, field plates (e.g., field plates <NUM>-<NUM>, field plates <NUM>, and/or field plates <NUM>-<NUM>) may be placed inside the active region <NUM>. For instance, field plates, such as field plates <NUM>-<NUM>, may be positioned parallel to the direction YP and within (i.e., inside) the active region <NUM>. Although <FIG> shows capacitance network <NUM> as being placed near the drain pad <NUM>, other placements are possible. For instance, the capacitance network <NUM> may be placed near or within the source pad <NUM>. Alternatively, a device may use a layout with multiple capacitance networks and/or integrated capacitance networks as described below with regards to <FIG> and <FIG>.

<FIG> illustrates a conceptual flow diagram <NUM> for distributing an electric field in a drift region (e.g., a high voltage region <NUM> and/or <NUM>). Step <NUM> may correspond with forming at least one field plate (e.g., any one of field plates <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and/or f1-f3) above the drift region. Step <NUM> may correspond with coupling a capacitance network (e.g., capacitance network <NUM>, <NUM>) to the at least one field plate so as to establish a select potential (e.g., any one of field plate potentials VFP1-VFP4) on the at least one field plate. Step <NUM> may correspond with providing the select potential such that an electric field (see, e.g., plot <NUM> of electric field) is substantially uniform (see, e.g., plot <NUM> within high voltage region <NUM>).

<FIG> illustrates a traditional field plate design for a high voltage lateral gallium nitride device; and <FIG> illustrates a lateral gallium nitride device cross-section and electrical schematic according to the teachings herein. <FIG> may further illustrate parasitic capacitance, resistor static discharge network elements, and a capacitance network for coupling ratio establishment. A capacitance network can be realized by a metal-insulator-metal (MIM) structure; a MIM structure can be inherent to a GaN process. The MIM structure can be realized through vertical metal plates and/or adjacent metal comb plates.

<FIG> illustrates a top layout view <NUM> of a device. Similar to top layout view <NUM>, the top layout view <NUM> shows an active region <NUM> with stripes oriented parallel to the direction YP. Additionally, the top layout view <NUM> also shows where interconnect (e.g., metallization and/or pad layers) may be located to connect to the drain D and the source S. For instance, pads <NUM>-<NUM> may be drain pads <NUM>-<NUM> allowing connection (i.e., electrical connection) to drain stripes and/or segments within the active region <NUM>; and pad <NUM> may be a source pad <NUM> allowing connection (i.e., electrical connection) to source stripes and/or segments within the active region <NUM>. Additionally, pad <NUM> may be a gate pad <NUM> allowing connection (i.e., electrical connection) to gate regions within the active region <NUM>.

In the embodiment of top layout view <NUM> a capacitance network (e.g., capacitance network <NUM> and/or capacitance network <NUM>) may include a capacitor <NUM> and a capacitor <NUM> placed outside of the active region <NUM>. Field plates, such as field plates <NUM>-<NUM>, may be positioned parallel to the direction YP and within (i.e., inside) the active region <NUM>.

For instance, <FIG> illustrates a top layout view of the stripe region <NUM> according to the embodiment of <FIG> and shows a field plate pattern <NUM> and field plate pattern <NUM>. Field plate pattern <NUM> may electrically couple to capacitor <NUM> (or capacitor <NUM>); and field plate pattern <NUM> may electrically couple to capacitor <NUM> (or capacitor <NUM>). In one embodiment, capacitors <NUM> and <NUM> may have capacitance values in the range of one to ten picoFarads (pF); for instance, capacitor <NUM> may have a value of <NUM>. 4pF and capacitor <NUM> may have a value of <NUM>.

<FIG> illustrates a top layout view <NUM> of a device. Similar to top layout view <NUM> and top layout view <NUM>, the top layout view <NUM> shows an active region <NUM> with stripes oriented parallel to the direction YP. However, unlike the embodiments shown in top layout views <NUM> and <NUM>, the device of top layout view <NUM> realizes a capacitor network (e.g., capacitance network <NUM> and/or capacitance network <NUM>) using an embedded capacitor distributed within the active region <NUM>.

For instance, <FIG> illustrates a top layout view and <FIG> illustrates a cross sectional view of the stripe region <NUM> according to the embodiment of <FIG>. <FIG> illustrates a field plate pattern <NUM> is electrically coupled with an embedded capacitor pattern <NUM> by an interconnect link <NUM>.

A cross section line <NUM> delineated between points A (source S) and B (drain D) of top layout view may correspond with the cross sectional view of <FIG>. Point A may align (and be electrically coupled) with source interconnect <NUM>; and point B may align (and be electrically coupled) with drain interconnect <NUM>. The embedded capacitor pattern <NUM> may be electrically coupled with embedded capacitor <NUM>; and the field plate pattern <NUM> may be electrically coupled with field plate <NUM>.

A problem solved by capacitance networks for enhancing high voltage operation of high electron mobility transistors (HEMTs) may include enabling high voltage operation of a lateral gallium nitride (GaN) device without adding process complexity and cost.

Ideal (i.e., traditional) field plate design for a lateral HV device may have a nearly square e-field distribution along drift region. This may be achieved by increasing level of field plates with increasing dielectric thickness as breakdown voltage increases (see, e.g., <FIG>); but this adds process cost and complexity. The teachings herein may be applicable to a lateral GaN device with a number of capacitively coupled field plates; and the field plates may preferably built on the same metal layer for lower cost, whereby the potential on each field plate may be pre-determined through a capacitance network, resulting in a uniform e-field distribution along drift region at maximum operating voltage.

Claim 1:
A high electron mobility transistor "HEMT" semiconductor device (<NUM>) comprising:
a drift region formed laterally between a gate and a drain, wherein the drift region is configured to support an electric field;
a plurality of field plates (<NUM>, <NUM>, <NUM>, <NUM>) disposed above the drift region, the plurality of field plates comprising:
a first field plate (<NUM>) configured to support a first potential; and
a second field plate (<NUM>) configured to support a second potential; and
a capacitance network (<NUM>) electrically coupled to the plurality of field plates, wherein the capacitance network is configured to establish the first potential on the first field plate and the second potential on the second field plate so as to distribute the electric field supported by the drift region, wherein the capacitance network comprises
a first capacitor (C21) electrically coupled to the first field plate and between the first field plate and a DC potential,
a second capacitor (C24) electrically coupled to the second field plate and between the second field plate and the DC potential,
characterized in that the capacitance network of the HEMT semiconductor device further comprises
a first impedance (R1) electrically coupled between the DC potential and the first field plate,
a second impedance (R6) electrically coupled between the drain and the second field plate, and
one or more additional impedances (R2, R3, R4, R5) electrically coupled between the first field plate and the second field plate.