Patent Description:
UPS systems are commonly used in installations such as data centers, medical centers and industrial facilities. UPS systems may be used in such installations to provide backup power to maintain operation in event of failure of the primary utility supply. These UPS systems common have an "on-line" configuration including a rectifier and inverter coupled by a DC link that is also coupled to an auxiliary power source, such as a battery, fuel cell or other energy storage device.

UPS systems, motor drives and other power conversion devices commonly use an inverter that generates an AC output from a DC power source, such as a rectifier and/or battery. A "two level" bridge inverter may be used to selectively connect these DC buses to the output of the inverter to generate an AC voltage waveform. Multilevel inverters may provide for additional voltages between the DC bus voltages. Various multilevel inverter circuits are described, for example, in <CIT>, <CIT>, <CIT>, <CIT> and <CIT>.

Inverters are disclosed by <CIT>; <CIT>, <CIT>, <CIT> and <CIT>.

During operation, inverters may experience overcurrent conditions caused by output shorts and/or overloads. Conventional inverters may respond to overcurrent conditions by turning off bridge transistors while the overcurrent is present, which may result in current passing back to a DC bus via body diodes of the bridge transistors.

The invention relates to an inverter comprising a multilevel bridge circuit comprising first and second switches having first terminals coupled to an output of the bridge circuit and first and second neutral clamping diodes coupled between a neutral and second terminals of the first and second switches.

The inverter further comprises a control circuit operatively coupled to the multilevel bridge circuit and configured to generate a first overcurrent indication signal indicating an overcurrent at the output of the multilevel bridge circuit having a first direction, a second overcurrent indication signal indicating an overcurrent at the output of the multilevel bridge circuit having a second direction and an overcurrent characterization signal indicating a duration of the first overcurrent indication signal and a duration of the second overcurrent indication signal and to selectively operate the first and second switches to provide a first impedance between the output of the multilevel bridge circuit and the neutral or a second impedance between the output of the multilevel bridge circuit and the neutral based on the first overcurrent indication signal, the second overcurrent indication signal and the overcurrent characterization signal.

Specific systems, methods and features now will be described with reference to the accompanying drawings. As used herein the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive subject matter. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless expressly stated otherwise. It will be further understood that the terms "includes," "comprises," "including" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

<FIG> illustrates an inverter <NUM> The inverter <NUM> includes a multilevel bridge circuit <NUM> coupled to first and second DC busses 115a, 115b and to an output inductor Lout. A first pair of serially connected transistors Q1, Q3 of the bridge circuit <NUM> is coupled between the first DC bus 115a and an inductor Lout. A second pair of serially connected transistors Q2, Q4 of the bridge circuit <NUM> is coupled between the second DC bus 115b and the inductor Lout. Respective first and second neutral clamping diodes D1, D2 couple respective nodes between the transistors of the respective pairs to a neutral node N. Respective capacitors C1, C2 are coupled between respective ones of the first and second DC busses 115a, 115b and the neutral node N.

It will be appreciated that the arrangement of the transistors Q1, Q2, Q3, Q4 illustrated in <FIG> is one conventionally used to implement a three-level inverter in which three voltages, i.e., the DC bus voltages VDC+, VDC- and the voltage at the neutral node N, are applied to the output filter inductor Lout. The inverter arrangement illustrated in <FIG> is provided for purposes of illustration. It will be appreciated that embodiments of the inventive subject matter may be embodied in higher-order multilevel inverter arrangements.

As further illustrated, the inverter <NUM> further includes an inverter control circuit <NUM>, which is configured to drive the first, second, third and fourth transistors Q1, Q2, Q3, Q4. In some embodiments, the inverter control circuit <NUM> may be configured to apply pulse-width modulated drive signals to the first, second, third and fourth transistors Q1, Q2, Q3, Q4 such an AC waveform vout is produced at an output terminal of the inverter <NUM>. The inverter control circuit <NUM> is further configured to provide a variable overcurrent response based on a output current iout of the inverter <NUM>, here shown as sensed by a current sensor <NUM> (e.g., a current transformer (CT) or similar device), which produces a current sense signal CS. In some embodiments, the inverter control circuit <NUM> may be configured to detect an overcurrent for an output of the inverter <NUM> based on the current sense signal CS, to generate a measure of the overcurrent and to responsively control the bridge circuit <NUM> to selectively put an output node <NUM> of the bridge circuit <NUM> in a first impedance state or a second impedance state based on the measure of the overcurrent.

For example, if the measure of magnitude indicates a relatively large overcurrent, the inverter control circuit <NUM> may turn off all of the transistors Q1, Q2, Q3, Q4 such that a relatively large impedance is provided between the bridge circuit output node <NUM> and the neutral N. Putting the bridge circuit <NUM> in such an "open" state may support a relatively low RMS current with a high peak current, with current decaying relatively quickly. If the measure of magnitude indicates a relatively smaller overcurrent, however, the inverter control circuit <NUM> may turn on the inside transistors Q1, Q2, thus providing current paths through the neutral clamping diodes D1, D2 such that a relatively lower impedance is provided between the inverter output node <NUM> and the neutral N. Such a "grounded" state may support relatively higher RMS current, but with controlled peak current and slower current decay.

It will be appreciated that the bridge circuit <NUM> shown in <FIG> is provided for purposes of illustration, and that any of a variety of other multilevel bridge circuits may be used in various embodiments of the inventive subject matter. These may include multilevel bridge circuits employing other types of switching devices than the insulated-gate bipolar transistors (IGBT's) shown in <FIG> and multilevel bridge circuits providing more levels than the three-level arrangement shown in <FIG>, e.g., bridge circuits configured to support three or higher level operation. It will be further understood that the inverter control circuit <NUM> may, in general, be implemented using analog circuitry, digital circuitry (e.g., logic circuitry and/or computing circuitry, such as a microprocessor, microcontroller, digital signal processor (DSP) or the like) and combinations thereof.

<FIG> illustrates an exemplary implementation of an inverter control circuit <NUM>. The control circuit <NUM> includes a processor, such as a DSP-based microcontroller, which is configured to generate a PWM command signal PWM and a polarity control signal PC. A bridge driver circuit <NUM>, here shown implemented as a digital state machine in a complex programmable logic device (CPLD) <NUM>, is configured to receive the PWM command signal PWM and the polarity control signal PC and to responsively generate gate drive signals, e.g., signals to be applied to gate terminals of the transistors Q1, Q2, Q3, Q4 of the bridge circuit <NUM> of <FIG>. In particular, the bridge driver circuit <NUM> may drive the bridge circuit transistors using duration information provided by the PWM command signal PWM, with the polarity command signal PC indicating which devices are to be active in various phase of multi-level operation. Examples of pulse-width modulated multi-level inverter operations are described, for example, in the aforementioned <CIT>, <CIT>, <CIT>, <CIT>. and <CIT> Some embodiments may also use variable level inverter control techniques described in copending <CIT>.

The control circuit <NUM> also includes an overcurrent detector circuit, here shown as including a comparator circuit <NUM> configured to receive a current sense signal CS representative of the output current of the inverter. The comparator circuit <NUM> generates an overcurrent indication signal OCI based on a comparison of the current sense signal CS to an overcurrent threshold reference signal Vref. The overcurrent indication signal OCI indicates whether the inverter current is above or below the overcurrent threshold.

The control circuit <NUM> further includes an overcurrent characterization circuit <NUM>, here shown as also implemented in the CPLD <NUM>. The overcurrent characterization circuit <NUM> is configured to generate an overcurrent characterization signal OCC indicating whether the detected overcurrent is a "high" overcurrent or a "low" overcurrent. As explained in detail below with reference to <FIG> and <FIG>, this signal may be generated by, for example, measuring a pulse width of the overcurrent indication signal OCI produced by the comparator circuit <NUM>, which serves as a measure of the amount of overcurrent. Responsive to the overcurrent indication signal OCI indicating the presence of an overcurrent, the bridge driver circuit <NUM> may control the manner in which it generates the gate drive signals based on the overcurrent characterization signal OCC produced by the overcurrent characterization circuit <NUM> to select between, for example, one of the "open" and "grounded" states described above with reference to <FIG>.

<FIG> is a state diagram illustrating operations of the bridge driver circuit <NUM> of <FIG>. The bridge driver circuit <NUM> may begin in a "normal" state <NUM> in which it operates responsive to the PWM command signal and polarity control signal produced by the DSP <NUM>. Responsive to the overcurrent indication signal OCI indicating the presence of an overcurrent, the bridge driver circuit <NUM> transitions to a second state <NUM> in which it determines the appropriate gate drive signals to apply to the bridge circuit transistors. If the overcurrent characterization signal OCC indicates a high overcurrent, the bridge driver circuit <NUM> transitions to state <NUM> in which it applies the appropriate gate drive signals to provide a relatively high impedance between the bridge circuit output and neutral (e.g., referring to <FIG>, the bridge driver circuit <NUM> turns off all of the first, second, third and fourth transistors Q1, Q2, Q3, Q4). If the overcurrent characterization signal OCC indicates a relatively low overcurrent, the bridge driver circuit <NUM> transitions to a state <NUM> in which applies the appropriate gate drive signals to provide a relatively low impedance between the bridge circuit output and neutral ((e.g., referring to <FIG>, the bridge driver circuit <NUM> turns on the first and second transistors Q1, Q2 to support conduction via the neutral clamping diodes D1, D2). If an end of the overcurrent condition is indicated by the overcurrent indication signal OCI while in either of these states, the bridge driver circuit <NUM> transitions back to the normal PWM operation state <NUM>.

A measure of an overcurrent may be generated by determining a pulse width of the overcurrent indication signal OCI, which represents a duration for which the inverter output current exceeds a threshold level. Referring to <FIG>, for example, in response to detecting a change in the state of the current sense signal CS indicating a current exceeding the threshold Vref of the comparator circuit <NUM> (block <NUM>), a counter may be started (block <NUM>) to accumulate a count for a time interval until the current sense signal CS again falls below the comparator threshold (block <NUM>). If the accumulated count is greater than or equal to a limit N, the overcurrent characterization signal OCI may be put in a logic high state indicating a high overcurrent (block <NUM>). If the accumulated count is less than the limit N, the overcurrent characterization signal OCC may be put in a logic low state indicating a low overcurrent (block <NUM>).

Operations along these lines are illustrated in <FIG>. Referring to <FIG> in conjunction with <FIG>, at a time t0, the overcurrent characterization signal OCC may be at a high level or a low level, either as the result of a prior overcurrent episode or as a default state. At the time t0, an excursion of the current sense signal CS above the threshold Vref is detected, driving the overcurrent indication signal OCI to a logic high state and initiating a count that proceeds until the current sense signal again falls below the overcurrent indication threshold Vref at a time t1, driving the overcurrent indication signal OCI to a logic low. In the illustrated example, the count thus produced exceeds the limit N, resulting in driving the overcurrent characterization signal OCC high. Upon a subsequent excursion of the current sense signal CS above the threshold Vref at a time t2, the overcurrent indication signal OCI is again driven high, causing the bridge driver circuit <NUM> to put the bridge circuit in an "open" (high impedance to neutral) state due to the current state of the overcurrent characterization signal OCC. A count is also initiated, terminating when the current sense signal CS again falls below the threshold Vref at a time t3. As shown, the count still exceeds the limit N, thus causing the overcurrent characterization signal OCC to remain in the logic high state.

Upon a succeeding excursion of the current sense signal CS above the threshold Vref at a time t4, the bridge driver circuit <NUM> again puts the bridge circuit in an "open" state based on the current state of the overcurrent characterization signal OCC. A new count is initiated at time t4, and terminates at a subsequent time t5 when the current sense signal CS again falls below the threshold Vref and the overcurrent indication signal OCI is again deasserted. As shown, this count is now below the limit N, causing the overcurrent characterization signal OCC to be driven to a logic low value. In a next overcurrent interval from a time t6 to a time t7, the bridge driver circuit <NUM> puts the bridge circuit in a "grounded" (low impedance to neutral) state due to the low state of the overcurrent characterization signal OCC. During the intervals between the overcurrent states, the bridge driver circuit <NUM> may operate normally in response to the PWM command signal PWM and the polarity control signal PC received from the processor <NUM>.

It may be desirable to limit the duration for which the inverter output is maintained in an "open" high-impedance state. In particular, referring to <FIG>, when current through the output inductor Lout approaches zero while in the "open" state, severe overvoltages for the transistors of the bridge circuit <NUM> can arise due to oscillations. This discontinuous mode may be avoided by limiting the time in which the bridge circuit <NUM> is in the "open" mode, and switching the bridge circuit <NUM> to the low-impedance "grounded" state before the inductor current reaches zero.

A time period T that it takes for the inductor current to reach zero can be estimated as: <MAT> where I represents the inductor current at the time the "open" state is entered, Lout is the inductance of the output inductor Lout, V0ut is the output voltage at the right terminal of the output inductor Lout, and Vx is the voltage at the left terminal of the output inductor Lout (the bridge circuit output node <NUM>). According to some embodiments of the inventive subject matter, a bridge driver circuit may use a time limit based on the estimated time T, and may switch from the "open" state to the "grounded" state when that time limit reached.

<FIG> illustrates a modification of the state machine of <FIG> that incorporates such a timeout limitation. The bridge driver circuit <NUM> of <FIG> may move among states <NUM>, <NUM>, <NUM>, <NUM> as described above with reference to <FIG> except that, when in the high impedance "open" state <NUM>, the bridge driver circuit <NUM> may monitor the duration for which it is in this state, transitioning to the low impedance "grounded " state <NUM> when it has reached a timeout limit.

The inverter control circuit according to the invention uses current direction information to control overcurrent response. As illustrated in <FIG>, an inverter control circuit <NUM> includes a processor, such as a DSP-based microcontroller, which is configured to generate a PWM command signal PWM and a polarity control signal PC. A bridge driver circuit722 implemented as a digital state machine in a complex programmable logic device (CPLD) <NUM> is configured to receive the PWM command signal PWM and the polarity control signal PC and to responsively generate gate drive signals for a multi-level bridge circuit.

The control circuit <NUM> also includes an overcurrent detector circuit, here shown as including first and second comparator circuits 730a, 730b configured to receive a current sense signal CS representative of the output current of the inverter. The first comparator circuit 730a generates a positive overcurrent indication signal OCI+ based on a comparison of the current sense signal CS to a positive overcurrent threshold reference signal Vref+. The second comparator circuit 730b generates a negative overcurrent indication signal OCI- based on a comparison of the current sense signal CS to a negative overcurrent threshold reference signal Vref-.

The control circuit <NUM> further includes an overcurrent characterization circuit <NUM> also implemented in the CPLD <NUM>. The overcurrent characterization circuit <NUM> is configured to generate an overcurrent characterization signal OCC indicating whether the detected overcurrent is a "high" overcurrent or a "low" overcurrent by, for example, measuring a pulse width of the overcurrent indication signals OCI+, OCI- produced by the comparator circuits 731a, 730b. Responsive to the overcurrent indication signals OCI+, OCI-indicating the presence of an overcurrent, the bridge driver circuit <NUM> may control the manner in which it generates the gate drive signals based on the overcurrent characterization signal OCC produced by the overcurrent characterization circuit <NUM> to selectively put the bridge circuit into one of the "open" and "grounded" states described above.

Such an arrangement is particularly advantageous for overcurrent control in backfeed situations in which current is flowing in a direction opposite to the current polarity of the bridge circuit. For example, referring to <FIG>, when the inverter <NUM> is providing a positive voltage with the upper transistors Q1, Q3 on, in the presence of an overcurrent flowing out of the bridge circuit <NUM>, the bridge driver circuit <NUM> may put the bridge circuit <NUM> in an "open" state (all of the transistors Q1, Q2, Q3, Q4 off) or a "grounded" state (inner transistors Q1, Q2 on) based on the overcurrent magnitude, as described above. However, if, while the bridge circuit <NUM> is in the positive voltage driving state, current is flowing into the bridge circuit <NUM>, it may be desirable to constrain the bridge circuit <NUM> to go to the "open" state, irrespective of the magnitude of the overcurrent. Table <NUM> illustrates desirable overcurrent responses for different combinations of bridge circuit polarity and overcurrent polarity:.

<FIG> is a state diagram illustrating operations of the bridge driver circuit <NUM> of <FIG>. Starting at a "normal" state <NUM> in which the bridge driver circuit <NUM> operates responsive to the PWM command signal and polarity control signal produced by the DSP <NUM>, upon assertion of either the positive overcurrent indication signal OCI+ or the negative overcurrent indication signal OCI- indicating the presence of an overcurrent, the bridge driver circuit <NUM> transitions to a second state <NUM> in which it determines the appropriate gate drive signals to apply to the bridge circuit transistors. If the overcurrent characterization signal OCC indicates a high overcurrent, the bridge driver circuit <NUM> transitions to a high impedance "open" state <NUM>. If the overcurrent characterization signal OCC indicates a relatively low overcurrent and a backfeed condition I not present based on the state of the bridge circuit and which of the positive overcurrent indication signal OCI+ or the negative overcurrent indication signal OCI- is asserted, the bridge driver circuit <NUM> transitions to a low impedance "grounded" state <NUM>. If, however, a low overcurrent is indicated but a backfeed condition is also present, the bridge driver circuit <NUM> transitions to the "open" state <NUM>. As also shown, a timer may be provided to monitor the duration of the "open" state, forcing transition to the "grounded" state when the timer expires and no backfeed is present. When an end of the overcurrent condition is indicated by the overcurrent indication signals OCI+, OCI-, the bridge driver circuit <NUM> transitions back to the normal PWM operation state <NUM>.

Embodiments of the inventive subject matter may be used in variety of different applications, including in inverters used for producing AC power from batteries, solar generators or wind generators, and in uninterruptible power supply (USP) systems. For example, <FIG> illustrates a UPS system <NUM> including a rectifier <NUM>, which is configured to be coupled to a three-phase AC power source, such as a utility source, which provides A,B and phase voltages vina, vinb, vinc. The rectifier <NUM> produces DC voltages VDC+, VDC- on positive and negative DC busses 915a, 915b, which are coupled to a neutral N by respective storage capacitors C1, C2. An auxiliary DC power source, such as a battery and/or a battery converter, is coupled to the positive and negative DC busses 915a, 915b and is configured to maintain the positive and negative DC voltage VDC+, VDC- in the event of a failure of the AC power source and/or the rectifier <NUM>. An inverter <NUM> comprising three bridge circuits 922a, 922b, 922c and associated inductors Lout is coupled to the positive and negative DC busses 915a, 915b and is configured to produce three phase voltages vouta, voutb, voutc from the DC bus voltages VDC+, VDC-. The inverter <NUM> may provide variable overcurrent response along the lines discussed above with reference to <FIG>. It will be appreciated that embodiments of the inventive subject matter are applicable to wide variety of other applications.

Claim 1:
An inverter (<NUM>) comprising:
a multilevel bridge circuit (<NUM>) comprising first and second switches (Q1, Q2) having first terminals coupled to an output of the bridge circuit and first and second neutral clamping diodes (D1, D2) coupled between a neutral and second terminals of the first and second switches; and
a control circuit (<NUM>, <NUM>) operatively coupled to the multilevel bridge circuit (<NUM>) and configured to generate a first overcurrent indication signal indicating an overcurrent at the output of the multilevel bridge circuit (<NUM>) having a first direction, a second overcurrent indication signal indicating an overcurrent at the output of the multilevel bridge (<NUM>) circuit having a second direction and an overcurrent characterization signal indicating a duration of the first overcurrent indication signal and a duration of the second overcurrent indication signal and to selectively operate the first and second switches (Q1, Q2) to provide a first impedance between the output of the multilevel bridge circuit (<NUM>) and the neutral or a second impedance between the output of the multilevel bridge circuit (Q1, Q2) and the neutral based on the first overcurrent indication signal, the second overcurrent indication signal and the overcurrent characterization signal.