Patent Description:
With fast evolution of wireless communications, it is predicted that a future <NUM> communications system will have some new features. Three most typical communication scenarios include enhanced mobile broadband (enhanced Mobile Broadband, eMBB), massive machine type communications (massive Machine Type Communications, mMTC), and ultra-reliable and low latency communications (Ultra-Reliable and Low Latency Communications, URLLC). Requirements of the communication scenarios pose new challenges to a Long Term Evolution (Long Term Evolution, LTE) technology. Channel coding that is used as a most basic radio access technology is one of important research objects to meet <NUM> communication requirements.

Polar coding (Polar Coding) is novel channel coding proposed by E. Ar<IMG>kan in <NUM>. Designed based on channel polarization (Channel Polarization), the polar coding is the first code construction scheme that provably achieves a channel capacity by using a strict mathematical method. A polar code is a linear block code.

However, in the prior art, there is still no definite solution to a coding mode that can improve efficiency of coding and decoding and improve channel detection latency performance.

3GPP contribution "<NPL>) discloses a CRC mask scheme to differentiate different DCIs with group RNTI.

3GPP contribution "<NPL>) discloses a scheme of performing UEID (or RNTI) masking during a polar encoding procedure.

This application provides a coding method, a coding apparatus, and a computer readable storage medium according to the independent claims, to improve efficiency of coding and decoding and improve channel detection latency performance.

A first claimed aspect of this application provides a coding method, where the method includes:.

In this solution, the to-be-scrambled bit set may be determined based on the fixed bits and/or the assistant bits. The sending device may select several bits from the fixed bits in a specific manner to constitute the to-be-scrambled bit set, or may select several bits from the assistant bits in a manner to form the to-be-scrambled bit set, or may select several bits from the fixed bits and the assistant bits respectively to constitute the to-be-scrambled bit set. The selection manner may be determined by the sending device through negotiation with a receiving device, or may be specified in a protocol.

In this solution, the sending device configures corresponding bit values in the to-be-coded sequence based on the determined positions of the information bits, positions of the fixed bits, and positions of the assistant bits, in other words, configures all of the information bits, the fixed bits, and the assistant bits in the to-be-coded sequence. Then, the sending device obtains at least one bit from the fixed bits and/or the assistant bits as the to-be-scrambled bit set, determines the scrambling sequence, scrambles the bit in the to-be-scrambled bit set to obtain the scrambled sequence, and performs coding and subsequent processing for sending. In this way, in a decoding process, the receiving device can eliminate a signal that does not come from the sending device in advance based on the scrambled bit, to shorten a coding latency, and accelerate channel detection.

In a specific implementation, the scrambling a bit in the to-be-scrambled bit set based on the scrambling sequence to obtain a scrambled sequence includes:
performing, by the sending device, an exclusive-OR operation on the scrambling sequence and a corresponding bit in the to-be-scrambled bit set, and allocating an obtained bit in a corresponding position to obtain the scrambled sequence.

A second example provides a decoding method, including:.

In this solution, a decoding device performs decoding and checking after receiving, detecting, and obtaining the to-be-decoded sequence. In the decoding process, when decoding a scrambled bit scrambled by a sending device, the decoding device checks the scrambled bit, and if the check fails, does not perform subsequent decoding. In this way, a signal that does not come from the sending device is eliminated in advance, to shorten a decoding latency, and accelerate channel detection.

Optionally, the scrambled bit is a fixed bit, and the checking the scrambled bit includes:
performing checking based on a scrambled bit value obtained through decoding and a scrambled bit value obtained in advance, where if the scrambled bit value obtained through decoding is different from the scrambled bit value obtained in advance, the check fails.

A specific check manner is as follows: When the scrambled bit is the fixed bit, the scrambled bit value obtained through decoding is compared with the scrambled bit value obtained in advance. If the two bit values are different, the decoding is directly terminated, and there is no need to decode a subsequent bit. To be specific, in the decoding process, if the scrambled bit value obtained through decoding is different from the scrambled bit value obtained in advance, it is determined that the check fails, and the decoding is terminated.

The scrambling sequence is an RNTI of the sending device.

Optionally, the scrambled bit set includes any one of the following sets:.

In a specific implementation, the decoding and checking, by the receiving device, the to-be-decoded sequence in sequence includes:.

A third example provides a coding method, including:.

Optionally, the position of the to-be-scrambled bit includes any one of the following positions:.

A fourth claimed aspect of this application provides a coding apparatus, where the apparatus includes:.

Optionally, the processing module is configured to:
perform an exclusive-OR operation on the scrambling sequence and a corresponding bit in the to-be-scrambled bit set, and allocate an obtained bit in a corresponding position to obtain the scrambled sequence.

A fifth example provides a decoding apparatus, including:.

Optionally, the scrambled bit is a fixed bit, and the processing module is configured to:
perform checking based on a scrambled bit value obtained through decoding and a scrambled bit value obtained in advance, where if the scrambled bit value obtained through decoding is different from the scrambled bit value obtained in advance, the check fails.

Optionally, the processing module is configured to:.

A sixth example provides a coding apparatus, including:.

A seventh example provides a sending device, including:
a memory, a processor, a transmitter, and a computer program, where the computer program is stored in the memory, and the processor runs the computer program to perform the coding method provided in any implementation of the first aspect.

In a specific implementation of the sending device, there is at least one processor that is configured to execute an executable instruction stored in the memory, namely, the computer program. Therefore, by exchanging data with a receiving device by using a communications interface, the sending device performs the coding method provided in the first aspect or each implementation of the first aspect. Optionally, the memory may be further integrated in the processor.

An eighth example provides a receiving device, including:
a memory, a processor, and a computer program, where the computer program is stored in the memory, and the processor runs the computer program to perform the decoding method provided in any implementation of the second example.

In a specific implementation of the receiving device, there is at least one processor that is configured to execute an executable instruction stored in the memory, namely, the computer program. Therefore, by exchanging data with a sending device by using a communications interface, the receiving device performs the decoding method provided in the second example or any implementation of the second example. Optionally, the memory may be further integrated in the processor.

A ninth claimed aspect of this application provides a storage medium, configured to store a computer program, wherein the computer program is used to implement the coding method provided in any implementation of the first aspect.

A tenth example provides a storage medium, configured to store a computer program, wherein the computer program is used to implement the decoding method provided in any implementation of the second example.

An eleventh aspect of this application provides a program product, where the program product includes a computer program (in other words, an executable instruction), and the computer program is stored in a readable storage medium. At least one processor of a sending device may read the computer program from the readable storage medium, and the at least one processor executes the computer program, so that the sending device implements the coding method provided in the first aspect or each implementation of the first aspect.

A twelfth example provides a program product, where the program product includes a computer program (in other words, an executable instruction), and the computer program is stored in a readable storage medium. At least one processor of a receiving device may read the computer program from the readable storage medium, and the at least one processor executes the computer program, so that the receiving device implements the decoding method provided in the second example or each implementation of the second example.

According to the coding/decoding method, apparatus, and device provided in this application, the sending device configures corresponding bit values in the to-be-coded sequence based on the determined positions of the information bits, positions of the fixed bits, and positions of the assistant bits, in other words, configures all of the information bits, the fixed bits, and the assistant bits in the to-be-coded sequence. Then, the sending device obtains at least one bit from the fixed bits and/or the assistant bits as the to-be-scrambled bit set, determines the scrambling sequence, scrambles the bit in the to-be-scrambled bit set to obtain the scrambled sequence, and performs coding and subsequent processing for sending. A decoding device performs decoding and checking after receiving, detecting, and obtaining the to-be-decoded sequence. In the decoding process, when decoding a scrambled bit scrambled by the sending device, the decoding device checks, based on the bit value in the position that is obtained in advance in the scrambling sequence, the scrambled bit value in the position that is obtained through decoding, and if the check fails, does not need to decode a subsequent bit. In this way, a signal that does not come from the sending device is eliminated in advance, to shorten a decoding latency, and accelerate channel detection.

The technical solutions in the embodiments of this application may be applied to a <NUM> communications system or a future communications system, or may be applied to various other communications systems, for example, a Global System for Mobile Communications (Global System for Mobile Communications, GSM) system, a Code Division Multiple Access (CDMA, Code Division Multiple Access) system, a Wideband Code Division Multiple Access (Wideband Code Division Multiple Access, WCDMA) system, a general packet radio service (General Packet Radio Service, GPRS) system, a Long Term Evolution (Long Term Evolution, LTE) system, an LTE frequency division duplex (Frequency Division Duplex, FDD) system, an LTE time division duplex (Time Division Duplex, TDD) system, and a Universal Mobile Telecommunications System (Universal Mobile Telecommunications System, UMTS).

<FIG> is a basic schematic flowchart of common wireless communication. As shown in <FIG>, at a transmit end, a signal source successively undergoes signal source coding, channel coding, and digital modulation, and then is transmitted. At a receive end, a signal destination successively undergoes digital demodulation, channel decoding, and signal source decoding, and then is output. Polar coding may be used during channel coding. However, SC decoding, SCL decoding, or the like may be used during channel decoding. To improve performance of polar coding, many technologies improved based on polar coding, for example, CA-polar coding, PC-polar coding, and CA+PC-polar, are also proposed currently.

<FIG> is a schematic diagram of a system to which a coding method and a decoding method are applied according to this application. As shown in <FIG>, this solution is applied to a process of information interaction between a network device and a terminal. An encoder, namely, a sending device, may be either a network device or a terminal. Correspondingly, a decoder, namely, a receiving device, may be either a terminal or a network device. Optionally, this solution may be applied to a process of information interaction between terminals. In other words, both the sending device and the receiving device are terminals. This is not limited in this solution.

<FIG> is a flowchart of Embodiment <NUM> of a coding method according to this application. As shown in <FIG>, this solution is applied to a transmitter, namely, a sending device. The sending device may be a network device or a terminal device. The coding method provided in this embodiment includes the following specific implementation steps.

A sending device obtains positions of information bits, positions of fixed bits, and positions of assistant bits.

The sending device configures the information bits, the fixed bits, and the assistant bits in a to-be-coded sequence based on the positions of the information bits, the positions of the fixed bits, and the positions of the assistant bits.

In the foregoing step, the sending device determines an initial sequence such as a construction sequence, and determines the positions of the information bits, the positions of the fixed bits, and the positions of the assistant bits in the initial sequence, to allocate corresponding bits in corresponding positions.

The assistant bits include at least one of the following bits: a cyclic redundancy check (Cyclic Redundancy Check, CRC) bit, a parity check (Parity Check, PC) bit, and a hash bit. For example, the assistant bits include J CRC bits and J' assistant bits in total, and the J' assistant bits may be PC bits or CRC bits.

The sending device obtains a scrambling sequence, and scrambles a bit in a to-be-scrambled bit set based on the scrambling sequence to obtain a scrambled sequence, where the to-be-scrambled bit set is determined based on the fixed bits and/or the assistant bits.

In this step, the sending device may first determine the to-be-scrambled bit set, or may first determine the scrambling sequence. This is not limited in this solution. The scrambling sequence is used to scramble a corresponding bit in the selected to-be-scrambled bit set.

The to-be-scrambled bit set includes at least one bit, and the at least one bit may be all fixed bits, or may be all assistant bits, or may be some fixed bits and some assistant bits. This is not limited in this solution. In a specific implementation of the to-be-scrambled bit set, the to-be-scrambled bit set may be any one of the following sets:.

The sending device may determine a specific to-be-scrambled bit set according to a solution negotiated with a receiving device or in a manner specified in a protocol, then separately scramble bits in the selected to-be-scrambled bit set, and allocate the scrambled bits in corresponding positions to obtain a scrambled sequence.

The sending device performs polar coding on the scrambled sequence to obtain a coded sequence.

The sending device transmits the coded sequence.

In the foregoing two steps, the sending device performs polar coding processing on the scrambled sequence to obtain the coded sequence for sending, so that the receiving device performs reception and detection.

In an actual implementation, rate matching may be further performed on the obtained coded sequence after the polar coding, then modulation is performed, and the coded sequence is mapped to a corresponding resource for sending.

In the coding method provided in this embodiment, the sending device configures corresponding bits in the to-be-coded sequence based on the determined positions of the information bits, positions of the fixed bits, and positions of the assistant bits, in other words, configures all of the information bits, the fixed bits, and the assistant bits in the to-be-coded sequence. Then, the sending device obtains at least one bit from the fixed bits and/or the assistant bits as the to-be-scrambled bit set, determines the scrambling sequence, scrambles the bit in the to-be-scrambled bit set to obtain the scrambled sequence, and performs coding and subsequent processing for sending. Therefore, in a decoding process, the receiving device may perform checking in advance based on the scrambled bit, and eliminate a signal that does not come from the sending device or a signal with a transmission error. In this way, a coding latency is shortened, and channel detection is accelerated.

<FIG> is a flowchart of Embodiment <NUM> of a decoding method according to this application. As shown in <FIG>, this solution is applied to a receiver, namely, a receiving device. The receiving device may be a network device or a terminal device. The decoding method provided in this embodiment includes the following specific implementation steps.

A receiving device obtains a to-be-decoded sequence.

It should be noted that a descrambling operation at a receive end and a scrambling operation at a transmit end are a same operation in essence, and are both exclusive-OR operations performed on a scrambling sequence and an original sequence. Therefore, the two operations are not distinguished in this application, and scrambling is used for description.

In this step, the receiving device performs operations such as receiving, demapping, and demodulation to obtain a signal sent by a sending device, and then performs detection to obtain the to-be-decoded sequence. The sequence includes to-be-decoded information bits, fixed bits, and assistant bits, the assistant bits and/or the fixed bits include at least one bit scrambled by the sending device, and the scrambled bits constitute a scrambled bit set. In this solution, the assistant bits include at least one of the following bits: a CRC bit, a PC bit, and a hash bit. For example, the assistant bits include J CRC bits and J' assistant bits in total, and the J' assistant bits may be PC bits or CRC bits.

The receiving device determines positions of the information bits, positions of the fixed bits, and positions of the assistant bits in the to-be-decoded sequence. The determining manner is similar to that of the sending device.

The receiving device may determine the scrambled bit set based on the positions of the assistant bits and/or the positions of the fixed bits in the to-be-decoded sequence. All the bits in the scrambled bit set may be in the positions of the fixed bits, or may be in the positions of the assistant bits, or some are in the positions of the assistant bits and others are in the positions of the fixed bits. This is not limited in this solution. The positions of the bits in the scrambled bit set may be determined through negotiation between the transmit end and the receive end or specified in a protocol. In a specific implementation, the scrambled bit set includes any one of the following sets:.

In the foregoing implementation, the fixed bits and the assistant bits are merely used to indicate positions in the to-be-decoded sequence, and the scrambled bit set is a set including a bit in any position in the to-be-decoded sequence.

The receiving device decodes and checks the to-be-decoded sequence in sequence, and when decoding a scrambled bit, checks the scrambled bit, and if the check fails, terminates the decoding, where the scrambled bit is obtained after a bit in a scrambled bit set is scrambled by using a scrambling sequence, and the scrambled bit set is determined based on the fixed bits and/or the assistant bits.

In an optional implementation, if the scrambled bit is a fixed bit, the checking the scrambled bit includes:
performing checking based on a scrambled bit value obtained through decoding and a scrambled bit value obtained in advance, where if the scrambled bit value obtained through decoding is different from the scrambled bit value obtained in advance, the check fails.

It indicates that if the scrambled bit is a fixed bit, when the scrambled bit is decoded, checking is performed based on the scrambled bit value obtained through decoding and the scrambled bit value obtained in advance, and if the scrambled bit value obtained through decoding is different from the scrambled bit value obtained in advance, the decoding process is terminated. In this solution, the scrambled bit value obtained in advance is a value of the scrambled bit in the scrambling sequence.

A value of an assistant bit in a coding process is determined based on at least one information bit (sometimes another assistant bit needs to be added). Therefore, when the scrambled bit is an assistant bit, the receiving device needs to perform descrambling after performing decoding, then may perform checking after descrambling, and if the check fails, terminate the decoding.

In this step, the receiving device decodes the to-be-decoded sequence. In the decoding process, the receiving device considers the scrambled fixed bit and/or assistant bit as an information bit for decoding, and when decoding the scrambled bit, checks, based on the scrambled bit set determined in any one of the foregoing manners, the value of the scrambled bit obtained through decoding; and if the check fails, the receiving device terminates the decoding, in other words, does not decode a bit after the scrambled bit in the to-be-decoded sequence, but exits the decoding process and performs next detection.

If the scrambled bit value obtained in advance is the same as the scrambled bit value obtained through decoding in the position, the receiving device continues to decode a next bit in the to-be-decoded sequence, and performs a check in the foregoing manner every time a scrambled bit is decoded.

In the decoding method provided in this embodiment, a decoding device performs decoding and checking after receiving, detecting, and obtaining the to-be-decoded sequence. In the decoding process, when decoding a scrambled bit scrambled by the sending device, the decoding device checks, based on the bit value in the position that is obtained in advance in the scrambling sequence, the scrambled bit value in the position that is obtained through decoding, and if the check fails, the decoding is directly terminated, and there is no need to decode a subsequent bit. To be specific, in the decoding process, if the scrambled bit value obtained through decoding is different from the scrambled bit value obtained in advance, subsequent decoding is no longer performed. In this way, a signal that does not come from the sending device is eliminated in advance, to shorten a decoding latency, and accelerate channel detection.

<FIG> is a flowchart of Embodiment <NUM> of a coding method according to this application. As shown in <FIG>, this embodiment further provides a coding method, applied to a transmit end. The method includes the following specific steps.

A sending device determines positions of information bits and assistant bits and positions of fixed bits.

In this step, a difference from the embodiment shown in <FIG> lies in that, in this solution, after the sending device determines an initial sequence (namely, an initial construction sequence), the sending device determines the positions of the fixed bits and the positions of the assistant bits and the information bits based on parameters such as a quantity of information bits and a coding length. In other words, only general positions of all the assistant bits and all the information bits need to be determined, and specific positions of the information bits do not need to be determined in detail. The information bits may be determined after subsequent scrambling is completed.

The sending device determines a position of a to-be-scrambled bit based on the positions of the information bits and the assistant bits.

In this step, the sending device first selects, from the positions of the information bits and the assistant bits, the position of the to-be-scrambled bit according to a rule. In a specific implementation, the position of the to-be-scrambled bit includes any one of the following positions:.

In a specific implementation of this solution, a receiving device also determines a position of a scrambled bit in a same manner as the sending device, to determine scrambled bits in a subsequent decoding process.

The sending device configures the information bits, the fixed bits, and the assistant bits in a to-be-coded sequence based on the position of the to-be-scrambled bit, the positions of the information bits and the assistant bits, and the positions of the fixed bits.

In this step, the sending device determines the positions of the assistant bits and the positions of the information bits based on the determined position of the to-be-scrambled bit. In an implementation, the positions of the assistant bits include positions of all to-be-scrambled bits. In other words, only one or more bits in the assistant bits are scrambled, and the information bits are not scrambled. In another implementation, positions of to-be-scrambled bits not only include the positions of the assistant bits but also include the positions of the information bits. In other words, some (or all) information bits and some (or all) assistant bits are scrambled. In another implementation, the positions of the information bits include positions of all to-be-scrambled bits. In other words, the information bits are subsequently scrambled.

After positions of other bits are determined, the information bits, the fixed bits, and the assistant bits are configured in corresponding positions.

The sending device obtains a scrambling sequence, and scrambling, based on the scrambling sequence, the to-be-scrambled bit to obtain a scrambled sequence.

In this step, the sending device selects a proper scrambling sequence, and then scrambles, based on the scrambling sequence, the bit corresponding to the position of the selected to-be-scrambled bit to obtain the scrambled sequence.

The sending device performs polar coding on the scrambled sequence to obtain a coded sequence.

The sending device sends the coded sequence.

In the foregoing step, the sending device performs polar coding on the scrambled sequence, and if processing such as rate matching is further required, performs corresponding processing, then performs modulation, and maps the sequence to a corresponding resource for sending.

In the coding method provided in this embodiment, the sending device scrambles on at least one bit in the assistant bits and the information bits based on the selected scrambling sequence, and then performs coding and sending. The receiving device determines the position of the scrambled bit in the to-be-decoded sequence in a same manner as the sending device. In the decoding process, when decoding the scrambled bit, the receiving device performs checking, and determines in advance whether the information is information of the sending device or determines in advance whether a transmission error occurs, to effectively shorten a decoding latency, and accelerate channel detection.

Based on the foregoing several embodiments, the coding method and decoding method provided in this application are described below in detail by using some specific implementations.

<FIG> is a schematic flowchart of polar code-based coding performed by a transmit end according to this application. <FIG> is a schematic flowchart of polar code-based decoding performed by a receive end according to this application.

As shown in <FIG>, a sending device determines a construction sequence, determines positions of information bits, positions of fixed bits, and positions of other assistant bits based on the construction sequence, configures the corresponding information bits, and loads the corresponding bits in the positions of the fixed bits and the positions of the assistant bits (the assistant bits and/or the fixed bits include to-be-scrambled bits). The sending device determines a scrambling sequence and a to-be-scrambled bit set, and scrambles a bit in the to-be-scrambled bit set based on the determined scrambling sequence to obtain a scrambled bit. Then, the sending device configures the obtained scrambled bit in a corresponding position, performs polar coding, rate matching, and modulation, and maps the sequence to a corresponding resource for sending.

As shown in <FIG>, a receiving device determines positions of information bits, positions of assistant bits, and positions of fixed bits based on a construction sequence, determines a position of a scrambled bit in a to-be-decoded sequence in a same manner as a sending device, and determines a scrambling sequence. In a process of performing polar decoding on the to-be-decoded sequence, the receiving device decodes the determined scrambled bit as an information bit, and when decoding a position of the scrambled bit, performs checking based on a decoding result and a bit in the scrambling sequence. To be specific, every time a scrambled bit is decoded, the scrambled bit and a bit obtained in advance in a corresponding position in the scrambling sequence need to be compared for checking. If the check succeeds, the receiving device continues decoding; otherwise, if the check fails, the receiving device exits decoding and performs next detection until detection of all received data is completed.

Based on the coding and decoding procedures shown in <FIG> and <FIG>, assuming that the sending device is UE, the following describes the coding method and the decoding method in this application by using some specific implementations.

First implementation: to-be-scrambled bits are several fixed bits of the highest reliability.

A specific process of implementing coding and sending by the sending device is as follows:.

A specific process of implementing decoding and checking by the receiving device is as follows:.

Second implementation: to-be-scrambled bits are several fixed bits before a first information bit.

Third implementation: to-be-scrambled bits are several fixed bits of the lowest reliability in fixed bits.

Fourth implementation: to-be-scrambled bits are several fixed bits in foremost positions in fixed bits.

A specific implementation process of this manner is similar to those of the foregoing several manners. For determining a to-be-scrambled bit set by the sending device or determining a scrambled bit set by the receiving device, several fixed bits in foremost positions in a sequence are selected from a fixed bit set. Specific scrambling, coding, decoding, and checking processes are consistent with those in the foregoing solutions.

Fifth implementation: to-be-scrambled bits are several bits in fixed bits in descending order of row weights or Hamming weights of a corresponding polar coding matrix, starting from the highest.

A specific implementation process of this manner is similar to those of the foregoing several manners. For determining a to-be-scrambled bit set by the sending device or determining a scrambled bit set by the receiving device, several fixed bits of the highest row weights or Hamming weights of a corresponding polar coding matrix in a sequence are selected from a fixed bit set. Specific scrambling, coding, decoding, and checking processes are consistent with those in the foregoing solutions.

Sixth implementation: to-be-scrambled bits are several assistant bits in foremost positions in assistant bits.

Seventh implementation: to-be-scrambled bits are several assistant bits of the highest reliability in assistant bits.

Eighth implementation: to-be-scrambled bits are several assistant bits of the lowest reliability in assistant bits.

A specific implementation process of this manner is similar to those of the foregoing manners. For determining a to-be-scrambled bit set by the sending device or determining a scrambled bit set by the receiving device, several assistant bits of the lowest reliability are selected from an assistant bit set. Specific scrambling, coding, decoding, and checking processes are consistent with those in the foregoing solutions.

Ninth implementation: to-be-scrambled bits are several bits in assistant bits in descending order of row weights or Hamming weights of a corresponding polar coding matrix, starting from the highest.

A specific implementation process of this manner is similar to those of the foregoing manners. For determining a to-be-scrambled bit set by the sending device or determining a scrambled bit set by the receiving device, several assistant bits in descending order of row weights or Hamming weights of a corresponding polar coding matrix, starting from the highest are selected from an assistant bit set. Specific scrambling, coding, decoding, and checking processes are consistent with those in the foregoing solutions.

In addition to the foregoing nine implementations, in a specific application, the sending device and the receiving device may further determine, from a union set of fixed bits and assistant bits, a to-be-scrambled bit set or a scrambled bit set. The to-be-scrambled bit set or the scrambled bit set may be any one of the following:
a set including at least one of the fixed bits and the assistant bits in ascending order of positions, starting from the foremost; a set including at least one of the fixed bits and the assistant bits in ascending order of reliability, starting from the lowest; a set including at least one of the fixed bits and the assistant bits in descending order of reliability, starting from the highest; and a set including at least one of the fixed bits and the assistant bits in descending order of row weights of a corresponding polar coding matrix, starting from the highest.

A manner in which the sending device performs scrambling and coding processing after determining the to-be-scrambled bit set, and then maps a sequence to a corresponding resource for sending is similar to those of the foregoing solutions, and is not described herein again. Likewise, a manner in which the receiving device performs decoding and checking after scrambling the bit set is similar to those in the foregoing solutions, and is not described herein again.

Tenth implementation: In addition to determining positions of scrambled bits from assistant bits and/or fixed bits described above, the sending device may further determine positions of to-be-scrambled bits from positions of information bits and assistant bits, and the receiving device may further determine positions of scrambled bits from positions of information bits and assistant bits. Using the sending device as an example, determining positions of to-be-scrambled bits includes the following several manners:.

The positions of the to-be-scrambled bits are some of the positions of the information bits and the assistant bits in ascending order of positions, starting from the foremost; the positions of the to-be-scrambled bits are some of the positions of the information bits and the assistant bits in descending order of reliability, starting from the highest; the positions of the to-be-scrambled bits are some of the positions of the information bits and the assistant bits in ascending order of reliability, starting from the lowest; and the positions of the to-be-scrambled bits are some of the positions of the information bits and the assistant bits in descending order of row weights or Hamming weights of a corresponding polar coding matrix, starting from the highest.

Assuming that the positions of the to-be-scrambled bits are some of the positions of the information bits and the assistant bits in ascending order of positions, starting from the foremost, a specific implementation of a coding method of the sending device is as follows:.

A specific implementation of a decoding method on the receiving device is as follows:.

Other manners of determining the positions of the scrambled bits in the positions of the information bits and the assistant bits are similar to those in the forgoing implementations, and are not described herein again.

A specific implementation of a coding method on the sending device is:.

In any one of the foregoing implementations, the assistant bits include at least one of the following bits: a CRC bit, a PC bit, and a hash bit.

In the coding method and decoding method provided in any one of the foregoing implementations, in a coding process using polar coding, some bits are selected from the fixed bits and the assistant bits and scrambled, and then polar coding is performed for sending; in a decoding process, when a scrambled bit is decoded, checking may be performed based on a scrambled bit obtained in advance. In this way, a to-be-detected signal that does not come from target UE is eliminated in advance, to shorten a decoding latency, and accelerate channel detection.

In a specific implementation of the foregoing solution, a specific implementation of a scrambling method or determining a position of a scrambled bit further includes the following implementations:.

Even check: Binary sum of a check equation + Binary value of an RNTI in a check bit position = Binary <NUM>. Operation on an encoder: adding a binary value meeting the check equation in a check bit directly to the binary value of the RNTI in the check bit position to obtain a check bit value for sending.

Odd check: Binary sum of a check equation + Binary value of an RNTI in a check bit position = Binary <NUM>. Operation on an encoder: adding a binary value meeting the check equation in a check bit directly to the binary value of the RNTI in the check bit position and performing negation to obtain a check bit value for sending.

Objective: Different from the prior art in which scrambled (check) bits are configured in last several unfrozen bit positions, in this application, provided that a false alarm rate meets a requirement, a scrambled (check) bit position is set forward as far as possible to obtain an advantage of early stopping (early stopping means terminating decoding as soon as possible when decoding cannot succeed, to achieve power saving).

Preliminary step: Determine a rate matching scheme, and obtain a reliability sequence.

Step <NUM>: Select an unfrozen bit position set based on reliability.

Unfrozen bits include an information bit, an RNTI scrambled bit, and a check bit (such as a parity check, a CRC check, or a hash check).

Step <NUM>: Segment unfrozen bit positions according to a specific proportion in a sequence of sub-channel indexes (sub-channel index). A specific segmenting manner is shown in the following table:.

The segment <NUM> includes J<NUM> check bits, and the segment <NUM> includes J<NUM> check bits (values of J<NUM> and J<NUM> are pending).

Step <NUM>: Calculate a false alarm rate (False Alarm Rate, FAR) in the segment based on a formula (<NUM>). <MAT> where BLER<NUM> is a block error rate under a given SNR input in the segment <NUM>, that is, a probability of incorrectly decoding at least one bit. BLER<NUM> is a block error rate under a given SNR input in the segment <NUM>. The block error rate may be obtained through Gaussian approximation or density evolution (GA/DE) calculation or by using another method such as Monte Carlo simulation.

Based on simple conversion, a range of the FAR may be obtained: <MAT>.

Step <NUM>: Calculate J<NUM> and J<NUM> allocated when the false alarm rate meets the requirement.

Because the objective is to maximally obtain the advantage of early stopping when the false alarm rate meets the requirement, scrambled (check) bits need to be configured in the segment <NUM> as many as possible.

Constraints of a system are (<NUM>) FAR < FARrequirement , and (<NUM>) J<NUM> + J<NUM> = Jtotal , where FARrequirement is a maximal tolerable false alarm rate, and Jtotal is a total quantity of check (scrambled) bits included in a polar code. Therefore, under the constraints, a maximal J<NUM> value obtained through calculation is a foremost check (scrambled) bit allocation result for early stopping.

Actually, a position of each check (scrambled) bit may be determined by using the following simplified procedure:
Number unfrozen bits from <NUM> to K'.

Output positions of all check (scrambled) bits.

Another manner of determining a scrambled bit: Actually, a position of each check (scrambled) bit may be determined by using the following simplified procedure.

Through calculation of positions of check (scrambled) bits in various code lengths and code rates, it is found that positions of first three check (scrambled) bits are approximately in first <NUM>%, <NUM>%, and <NUM>% unfrozen bit positions. Therefore, this application provides the following simpler method:.

Step <NUM>: Obtain percentages (P<NUM>%, P<NUM>%, P<NUM>%,. ) of several first check/scrambled bit positions, and convert them into K<NUM>th, K<NUM>th, and K<NUM>th positions. For example, P<NUM>%×K'≈K<NUM>/K'. P<NUM>%, P<NUM>%, and P<NUM>% may be preset values such as <NUM>%, <NUM>%, and <NUM>%, or <NUM>%, <NUM>%, and <NUM>%, or <NUM>/<NUM>, <NUM>/<NUM>, and <NUM>/<NUM>.

Step <NUM>: As shown in <FIG>, configure check/scrambled bits in given positions. <FIG> is a schematic diagram of positions of check/scrambled bits according to this application.

Another method for determining a scrambled (check) bit position: Searching for a scrambled (check) bit position according to wmin and a proportion.

Step <NUM>: As shown in <FIG>, configure unfrozen bit positions in a sequence of sub-channel indexes (sub-channel index), and select a region of scrambled/check bit positions by using a foregoing method. <FIG> is another schematic diagram of positions of check/scrambled bits according to this application.

Step <NUM>: In the selected region, select a position of a specific row weight as a scrambled/check bit position.

Another method for determining a scrambled (check) bit position:.

(Option <NUM>) All assistant bits are generated by using a same set of shift registers.

Values of J CRC bits are obtained from final states of the registers.

Values of J' PC bits are obtained from intermediate states of the registers.

(Option <NUM>) Use two sets of shift registers.

J CRC bits are generated by a set of shift registers (values are obtained from final states of the registers).

J' PC bits are generated by another set of shift registers (values are obtained from intermediate states of the registers).

<FIG> is another schematic diagram of positions of check/scrambled bits according to this application. <FIG> is another flowchart of determining a position of a check/scrambled bit according to this application. A specific implementation of step <NUM> of this solution is shown in <FIG> and <FIG>.

Values of KJ', K<NUM>, K<NUM>, and K<NUM> may be obtained by using a simplified method, for example: <MAT> and <MAT>.

Specific positions of PC bits are positions meeting a specific row weight in a selected region, for example:
Initialization:
Preset a quantity of PC bits in a selected region, and prepare a first in first out buffer (FIFO Buffer) of a corresponding size to store PC bit positions.

Initialize a minimum row weight wmin to a maximum value.

Check row weights and determine PC bit positions:
Check a row weight corresponding to each position backward according to a sub-channel index (j).

Set a current sub-channel index k to a PC position, and push (push) the PC position into the buffer from the beginning.

Update a minimum row weight wmin = min(wmin, current row weight wj).

<FIG> is a schematic diagram of a register according to this application. A specific method for obtaining a value of the register in step <NUM> is as follows: A value needs to be obtained from a position in the register when a scrambled/check bit is decoded. A structure of the register is shown in <FIG>, and information bits are input from a right side.

Two possible methods for operating the register are as follows:
Register mode <NUM>: Shift only for pure information bits (not including frozen bits and various assistant bits), and when a scrambled/check bit position is encountered, obtain a value from an ith position in the register, where i = mod((<NUM>-k+C), lengthof the register).

The length of the register may be J+J', in other words, a total quantity of scrambled/check bits, where <NUM> means that a first scrambled/check bit is encountered currently, and k means that k pure information bits are already decoded currently. Mod is a modulo operation, and a result thereof is a non-negative integer from <NUM> to (the length of the register minus <NUM>). C is an offset and may be any constant.

Register mode <NUM>: Shift for all bits (including pure information bits, frozen bits, and various assistant bits), and when a scrambled/check bit position is encountered, obtain a value from an ith position in the register, where i=mod((<NUM>-n+C), lengthof the register).

The length of the register may be J+J', in other words, a total quantity of scrambled/check bits, where <NUM> means that a first scrambled/check bit is encountered currently, and n means a position of a current bit in a mother code (including pure information bits, frozen bits, and various assistant bits). Mod is a modulo operation, and a result thereof is a non-negative integer from <NUM> to (the length of the register minus <NUM>). C is an offset and may be any constant.

<FIG> is a schematic structural diagram of a coding apparatus according to this application. As shown in <FIG>, the coding apparatus <NUM> includes:.

The coding apparatus provided in this embodiment is configured to implement the technical solution on the sending device side according to any one of the foregoing method embodiments. Implementation principles and technical effects thereof are similar, and are not described herein again.

The scrambling sequence obtained by the processing module is a radio network temporary identifier RNTI of the coding apparatus.

Optionally, the to-be-scrambled bit set determined by the processing module <NUM> includes any one of the following sets:.

Optionally, the processing module <NUM> is configured to:
perform an exclusive-OR operation on the scrambling sequence and a corresponding bit in the to-be-scrambled bit set, and allocate an obtained bit in a corresponding position to obtain the scrambled sequence.

Optionally, the assistant bits include at least one of the following bits:
a CRC bit, a PC bit, and a hash bit.

Optionally, when a length of the scrambling sequence is greater than a quantity of bits in the to-be-scrambled bit set, the processing module <NUM> is further configured to:
obtain, from the scrambling sequence, a quantity of bits the same as that of bits in the to-be-scrambled bit set to serve as a new scrambling sequence.

The coding apparatus provided in any one of the foregoing solutions is configured to implement the technical solution on the sending device side according to any one of the foregoing method embodiments. Implementation principles and technical effects thereof are similar, and are not described herein again.

In another embodiment of the coding apparatus provided in this application, the processing module <NUM> is configured to determine positions of information bits and assistant bits and positions of fixed bits;.

Optionally, the position of the to-be-scrambled bit that is determined by the processing module <NUM> includes any one of the following positions:.

<FIG> is a schematic structural diagram of a decoding apparatus according to this application. As shown in <FIG>, the decoding apparatus <NUM> includes:.

The decoding apparatus provided in this embodiment is configured to implement the technical solution on the receiving device side according to any one of the foregoing method embodiments. Implementation principles and technical effects thereof are similar, and are not described herein again.

Optionally, the scrambling sequence is an RNTI of a sending device.

Optionally, the scrambled bit set determined by the obtaining module <NUM> includes any one of the following sets:.

Optionally, the processing module <NUM> is configured to:.

The decoding apparatus provided in any one of the foregoing implementations is configured to implement the technical solution on the receiving device side according to any one of the foregoing method embodiments. Implementation principles and technical effects thereof are similar, and are not described herein again.

It should be understood that in an implementation of the coding apparatus or the decoding apparatus, the processing module may be implemented as a processor, and the sending module may be implemented as a transmitter.

This application further provides a sending device, including a memory, a processor, a transmitter, and a computer program. The computer program is stored in the memory, and the processor runs the computer program to perform the coding method provided in any one of the foregoing embodiments.

In a specific implementation of the sending device, there is at least one processor that is configured to execute an executable instruction stored in the memory, namely, the computer program. Therefore, by exchanging data with a receiving device by using a communications interface, the sending device performs the coding method provided in any one of the foregoing implementations. Optionally, the memory may be further integrated in the processor.

This application further provides a receiving device, including a memory, a processor, and a computer program. The computer program is stored in the memory, and the processor runs the computer program to perform the decoding method provided in any one of the foregoing embodiments.

In a specific implementation of the receiving device, there is at least one processor that is configured to execute an executable instruction stored in the memory, namely, the computer program. Therefore, by exchanging data with a sending device by using a communications interface, the receiving device performs the decoding method provided in any one of the foregoing implementations. Optionally, the memory may be further integrated in the processor.

This application further provides a storage medium, including a readable storage medium and a computer program. The computer program is used to implement the coding method provided in any one of the foregoing embodiments.

This application further provides a storage medium, including a readable storage medium and a computer program. The computer program is used to implement the decoding method provided in any one of the foregoing embodiments.

This application further provides a program product. The program product includes a computer program (in other words, an executable instruction), and the computer program is stored in a readable storage medium. At least one processor of a sending device may read the computer program from the readable storage medium, and the at least one processor executes the computer program, so that the sending device implements the coding method provided in the foregoing implementations.

This application further provides a program product. The program product includes a computer program (in other words, an executable instruction), and the computer program is stored in a readable storage medium. At least one processor of a receiving device may read the computer program from the readable storage medium, and the at least one processor executes the computer program, so that the receiving device implements the decoding method provided in the foregoing implementations.

In the foregoing implementation of the sending device or the receiving device, it should be understood that the processor may be a central processing unit (Central Processing Unit, CPU for short), or may be another general-purpose processor, a digital signal processor (Digital Signal Processor, DSP for short), an application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC for short), or the like. The general purpose processor may be a microprocessor, or the processor may be any conventional processor or the like. The steps of the methods disclosed with reference to this application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and a software module in a processor.

Claim 1:
A coding method, wherein the method comprises:
obtaining (S101), by a sending device, positions of information bits, positions of fixed bits, and positions of assistant bits, wherein the assistant bits comprise at least one of the following bits: cyclic redundancy check, CRC, bits, parity check, PC, bits, and hash bits;
allocating (S102), by the sending device, the information bits, the fixed bits, and the assistant bits in a to-be-coded sequence based on the positions of the information bits, the positions of the fixed bits, and the positions of the assistant bits;
obtaining (S103), by the sending device, a scrambling sequence, and scrambling bits in a to-be-scrambled bit set based on the scrambling sequence to obtain a scrambled sequence, wherein the scrambling sequence is a radio network temporary identifier, RNTI, sequence of the sending device, and wherein the to-be-scrambled bit set comprises a set comprising the at least one of the fixed bits before an information bit;
performing (S <NUM>), by the sending device, polar coding on the scrambled sequence to obtain a coded sequence; and
sending (S105), by the sending device, the coded sequence;
wherein the method is characterized in that the to-be-scrambled bit set comprises at least one of the assistant bits and at least one of the fixed bits.