Patent Description:
The invention is defined as set forth in independent apparatus claim <NUM>.

The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

Some embodiments describe an apparatus for adaptively adjusting and compensating impedance by monitoring an output of a driver. In some embodiments, digital techniques are used by the apparatus to provide a solution to mitigate ringing or to correct AC impedance mismatch induced ringing. In some embodiments, the apparatus samples data at an output of a driver using a multiphase clock during rising edge of the data and compares the data with pre-define references (e.g., Vrefhi and VrefLow). In some embodiments, the compared sampled data information is stored and loaded into a decision logic. In some embodiments, the decision logic sends increment, decrement, and/or lock codes for adaptively adjusting an already compensated output impedance of the driver (e.g., pull-up and/or pull-down impedance of the driver). As such, ringing, overshoot, and/or undershoot caused by AC impedance mismatches at the output of the driver is reduced.

There are many technical effects of the various embodiments. For example, the apparatus of various embodiments provides auto correction of driver output impedance without impacting power and with minor area increment (e.g., around <NUM>%). The apparatus of various embodiments is a digital scheme which is insensitive towards supply noise level and is scalable to other process technology nodes. The apparatus of various embodiments provides additional timing margin (e.g., by widening the data eye) which helps in catering for wider platform loss and range. The apparatus of various embodiments can be executed during a training period of the driver and as such the operation of the apparatus does not impact the functional operation of the driver. Other technical effects will be evident from the description of various embodiments and the figures.

In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction.

Throughout the specification, and in the claims, the term "connected" means a direct electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means either a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on.

The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- <NUM>% (unless otherwise specified) of a target value. Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B).

For purposes of the embodiments, the transistors in various circuits, modules, and logic blocks are metal oxide semiconductor (MOS) transistors, which include drain, source, gate, and bulk terminals. The transistors also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors or other devices implementing transistor functionality like carbon nano tubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors-BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure.

<FIG> illustrates system <NUM> for adaptively adjusting compensated impedance by monitoring an output of a driver, according to some embodiments of the disclosure. In some embodiments, system <NUM> comprises impedance calibration logic (RCOMP calibration Logic) <NUM>, apparatus <NUM> for adaptively adjusting compensated impedance, driver <NUM> (e.g., a high speed driver with pre-driver), bias generator <NUM>, transmission line <NUM>, and receiver termination resistors (e.g., <NUM> Ohm resistors). In this example, the impedance of transmission line <NUM> is assumed to be <NUM> Ohms to <NUM> Ohms so as to match with the impedance of receiver termination resistors. However, other impedance values may also be used and matched with the impedances of driver <NUM> and the receiver. In this example, the receiver on the other side of transmission line <NUM> is modeled by the receiver termination resistors.

In some embodiments, impedance calibration logic <NUM> provides pull-up and pull-down compensated impedance codes (e.g., Rcomp_Rpull[<NUM>:<NUM>] and Rcomp_Rpd[<NUM>:<NUM>] codes, respectively) to apparatus <NUM>. In some embodiments, pull-up and pull-down compensated impedance codes are obtained from a compensation driver that determines these codes to compensate for DC (or low frequency) based process, voltage, and temperature (PVT) variations. However, these compensated codes are not compensated for AC changes to impedance seen by driver <NUM>. For example, when driver <NUM> is packaged within an integrated circuit (IC) package with impedance different than impedance of driver <NUM>, ringing, overshoot, undershoot, etc. may be caused at the output of driver <NUM>. In some embodiments, apparatus <NUM> compensates for these AC changes to impedance at the output of driver <NUM>.

In some embodiments, apparatus <NUM> includes detector 102a, clock generator 102b, decision logic 102c, and increment/decrement/bypass logic 102d. In some embodiments, detector 102a is coupled to an output of driver <NUM>. In some embodiments, detector 102a receives a multi-phase clock (e.g., a four bit clock CLK[<NUM>:<NUM>]), a first reference voltage (e.g., VrefHi_1), and a second reference voltage (e.g., VrefLow_1). In some embodiments, detector 102a senses the signal levels at the output of driver <NUM> using the multi-phase clock and compares it with the first and second reference voltages to generate Up and/or Down indicators (e.g., a four bit up code UP[<NUM>:<NUM>] and/or a four bit down code DN[<NUM>:<NUM>]). In some embodiments, detector 102a is implemented using one or more strong arm latches or clocked comparator latches. One such embodiments is described with reference to <FIG>.

Referring back to <FIG>, in some embodiments, clock generator 102b comprises a multi-phase signal generator (not shown) that provides a first clock (e.g., CLK0) and also generates a multi-phase clock output (e.g., a four bit clock CLK[<NUM>:<NUM>])). In some embodiments, the multi-phase signal generator (not shown) comprises a plurality of delay stages that generate the multi-phase clock output from a reference clock (not shown). In some embodiments, the plurality of delay stages comprises flip-flops coupled together in series, where the reference clock is received as data input to the first flip-flop, and a faster clock is used to sample that data for all flip-flops. Any other suitable circuit may be used for implementing the multi-phase signal generator for clock generator 102b. In some embodiments, first clock CLK0 is provided as Calib_Clock to impedance calibration logic <NUM>.

In some embodiments, decision logic 102c is coupled to detector 102a and increment/decrement/bypass logic 102d. In some embodiments, decision logic 102c gets Up/Down indication (e.g., codes UP[<NUM>:<NUM>] and DN[<NUM>:<NUM>]) from detector 102a and generates a set of codes for increment/decrement/bypass logic 102d. In some embodiments, these set of codes include increment up (INCR_UP), increment down (INCR_DN), decrement up (DEC_UP), decrement down (DEC_DN), lock pull-up impedance code (Lock_UP) and lock pull-down impedance code (Lock_DN). In some embodiments, decision logic 102c filters the output of detector 102a.

In some embodiments, INCR_UP is generated when there is a down indicator (e.g., when DN[<NUM>:<NUM>] has at least one high bit). This is because the pull-up impedance legs are generally implemented as p-type devices, and when fewer pull-up impedance legs are requested to be turned on (e.g., in the down case), then INCR_UP bit is high. However, a person skilled in the art can modify the functional control by adding an inverter in the logic path to switch the logic such that a down indicator causes INCR_DN to be high instead of INCR_UP being high. In some embodiments, DEC_UP is generated (e.g., asserted to logic high) when there is an UP indicator (e.g., when UP[<NUM>:<NUM>] has at least one high bit). Just as the logic for generating INCR_UP can be inverted, the logic for DEC_UP can also be inverted. In some embodiments, increment/decrement/bypass logic 102d can bypass itself. In one such case, the impedance codes from RCOMP calibration Logic <NUM> are directly provided to Driver <NUM>. One embodiment of a state machine generating the increment, decrement, and lock signals is described with reference to <FIG>.

Referring back to <FIG>, Increment/Decrement/Bypass Logic 102d receives control signals (e.g., INCR_UP, INCR_DN, DEC_UP, DEC_DN, Lock_UP, Lock_DN), and based on those control signals it adjusts the compensated pull-up impedance code (e.g., Rcomp_Rpull[<NUM>:<NUM>]) and/or compensated pull-down impedance code (e.g., Rcomp_Rpd[<NUM>:<NUM>]) and provides them as pull-up impedance code (e.g., Rpull[<NUM>:<NUM>]) and/or pull-down impedance code (e.g., Rpd[<NUM>:<NUM>]) to driver <NUM>. In some embodiments, when Increment/Decrement/Bypass Logic 102d receives a lock signal (e.g., Lock_UP or Lock_DN), then it freezes (or locks) the pull-up and/or pull-down impedance codes.

For example, when Increment/Decrement/Bypass Logic 102d receives Lock_UP (e.g., when Lock_UP is asserted), then Rpull[<NUM>:<NUM>] is frozen for at least one clock cycle. In another example, when Increment/Decrement/Bypass Logic 102d receives Lock_DN (e.g., when Lock_DN is asserted), then Rpd[<NUM>:<NUM>] is frozen for at least one clock cycle. The locked codes are then sent to driver <NUM>, in accordance with some embodiments. In some embodiments, pull-up and pull-down impedance codes after being locked are then provided to driver <NUM>.

In some embodiments, bias generator <NUM> generates first and second reference voltages (e.g., VrefHi_1 and VrefLow_1) for Detector 102a. In some embodiments, bias generator <NUM> also generates bias voltage Vref_comp for RCOMP calibration logic <NUM>. In some embodiments, first and second reference voltages (e.g., VrefHi_ and VrefLow_1) are nearer (e.g., <NUM>% to <NUM>%) to logic high level of the data driven by driver <NUM> such that the voltage level of the first reference voltage VrefHi_1 is higher than the voltage level of the second reference voltage VrefLow_1. In some embodiments, the difference between VrefHi_1 and VrefLow_1 determines the overshoot or ringing level thresholds when the data is rising to high level or is at high level. In some embodiments, when data driven by driver <NUM> rises above VrefHi_1, or below VrefLow_1, then detector 102a detects a ringing or overshoot condition and generates the appropriate UP/DN codes to adjust the pull-up impedance codes (e.g., Rpull[<NUM>:<NUM>] code).

In some embodiments, bias generator <NUM> generates third and fourth reference voltages (e.g., VrefHi_O and VrefLow_O) for detector 102a. In some embodiments, third and fourth reference voltages (e.g., VrefHi_O and VrefLow_O) are nearer (<NUM>% to <NUM>%) to logic low level of the data driven by driver <NUM> such that the voltage level of the third reference voltage VrefHi_0 is higher than the voltage level of the second reference voltage VrefLow_0. In some embodiments, the difference between VrefHi_0 and VrefLow_0 determines the undershoot or ringing level thresholds when the data is falling to low level or is at low level. In some embodiments, when data driven by driver <NUM> rises above VrefHi_0, or below VrefLow_0, then detector 102a detects a ringing or undershoot condition and generates the appropriate UP/DN codes to adjust pull-down impedance codes (e.g., Rpd[<NUM>:<NUM>] code).

<FIG> illustrates plot <NUM> showing output of driver <NUM> before and after adaptive adjustment of compensated impedance, according to some embodiments of the disclosure. Here, x-axis is time and y-axis is voltage. Plot <NUM> shows two waveforms <NUM> and <NUM> at the output of driver <NUM>, and control signals including multi-phase clocks CLK0, CLK1, CLK2, and CLK4, and Up/Down signals UP0, UP1, UP2, UP3, UP4, DN0, DN1, DN2, DN3, and DN4. In this example, the multi-phase signals are separated by <NUM> picoseconds (ps). Here, waveform <NUM> (gray shaded) is the output of driver <NUM> before adaptive adjustment of compensated impedance while waveform <NUM> (black) is the output of driver <NUM> after adaptive adjustment of compensated impedance. While waveforms <NUM> and <NUM> are superimposed on one another, waveform <NUM> is achieved after a clock cycle (unit interval), in accordance with some embodiments. In this case, the adjusted codes are applied at least one cycle after change in code is detected, according to some embodiments.

In some embodiments, each unit interval (UI) of the data is sampled using the multiple phase clocks and compared with first, second, third, and fourth reference voltages (VrefHi_1, VrefLow_1, VrefHi_0, and VrefLow <NUM>, respectively). In response to comparing, Up/Down indicators are generated. In this example, overshoot or ringing is sampled at CLK1 and CLK3 edges. As such, UP1 and UP3 edges are asserted while other edges for UP (e.g., UP0 and UP4) and DN (e.g., DN0, DN1, DN2, DN3, and DN4) remain de-asserted.

<FIG> illustrates plot <NUM> showing operation of apparatus <NUM>, according to some embodiments of the disclosure. Plot <NUM> shows 'N' clock cycles (Cycle-<NUM>, Cycle-<NUM>, Cycle-<NUM>,. Cycle-N) <NUM>, state <NUM> of detector 102a, decision update clock CLK0 (or Calib_Clock), and state <NUM> of Increment/Decrement/Bypass logic 102d. State <NUM> illustrates the sampling of data from the output of driver <NUM> and then comparing that data against the reference voltages. This sampling and comparing is done after every clock cycle, in accordance with some embodiments. State <NUM> illustrates the clock for updating states of a finite state machine (e.g., discussed with reference to <FIG>). Referring back to <FIG>, state <NUM> illustrates the various possible states of the finite state machine during the clock cycle of decision logic 102c. In some embodiments, during decision update clock <NUM>, output of code <NUM> is available (e.g., increment/decrement/no change) based on the sampled and compared output. In some embodiments, after every decision update clock <NUM>, code <NUM> change depends on the sampled and compared output <NUM>.

<FIG> illustrates apparatus <NUM> for adaptively adjusting compensated impedance by monitoring an output of a driver, according to some embodiments of the disclosure. It is pointed out that those elements of <FIG> having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Apparatus <NUM> includes the details of various system components of <FIG>. Apparatus <NUM> comprises RCOMP logic <NUM>, Increment/decrement/lock logic 102d, logic <NUM>, driver <NUM>/<NUM>, detector <NUM>/102a, bias generator <NUM>/<NUM>, and decision block <NUM>/102c. In some embodiments, Logic <NUM> is any suitable logic providing Data and Datab (e.g., an inverse of Data).

In some embodiments, driver <NUM>/<NUM> comprises logic for propagating data and its associated impedance codes. In some embodiments, an AND gate 402a (or its equivalent) is provided which receives Data and the pull-up impedance codes Rpull[<NUM>:<NUM>] and provides an output for pre-driver 402c. In some embodiments, an AND gate 402b (or its equivalent) is provided which receives Datab and the pull-down impedance codes Rpd[<NUM>:<NUM>] and provides an output for pre-driver 402d. Pre-drivers 402c/d can be implemented with any suitable pre-driver design. In this example, the inputs and outputs of pre-drivers 402c/d are a five-bit bus. In some embodiments, driver 402e comprises pull-up and pull-down drivers coupled between supply nodes Vdd (e.g., power) and Vss (e.g., ground). In some embodiments, driver 402e is a Universal Serial Bus (USB) compliant driver. The output of driver 402e are USBDP and USBDM. Here, reference to node names and signal names are interchangeably used. For example, clock "CLK0" may refer to node CLK0 or clock signal CLK0 depending on the context of the sentence.

In some embodiments, detector <NUM>/102a comprises a plurality of comparator latches (e.g., Strong Arm Latches (SAL), clocked comparators, etc.) that are coupled to the outputs USBDP and USBDM, and to reference voltages VrefHi_1 and VrefLow_1. So as not to obscure the embodiments, reference voltages for detecting overshoot/ringing when data on nodes USBDP and USBDM rises to a high level are disclosed. Reference voltages for detecting undershoot/ringing when data on nodes USBDP and USBDM falls to a low level can also be added to another set of comparator latches (not shown). In some embodiments, detector <NUM>/102a is part of a high speed receiver (RX).

In some embodiments, comparator latch 403a receives inputs USBDP and USBDM and compares them with reference voltages VrefHi_1 and VrefLow_1 and samples inputs USBDP and USBDM using clock CLK0. The sampled output of comparator latch 403a are UP0 and DN0 which are provided to logic <NUM>/102c, in accordance with some embodiments. In some embodiments, comparator latch 403b receives inputs USBDP and USBDM and compares them with reference voltages VrefHi_1 and VrefLow_1 and samples inputs USBDP and USBDM using clock CLK1. The sampled output of comparator latch 403b are UP1 and DN1 which are provided to logic <NUM>/102c, in accordance with some embodiments. In some embodiments, comparator latch 403c receives inputs USBDP and USBDM and compares them with reference voltages VrefHi_1 and VrefLow_1 and samples inputs USBDP and USBDM using clock CLK2. The sampled output of comparator latch 403c are UP2 and DN2 which are provided to logic <NUM>/102c, in accordance with some embodiments. In some embodiments, comparator latch 403d receives inputs USBDP and USBDM and compares them with reference voltages VrefHi_1 and VrefLow_1 and samples inputs USBDP and USBDM using clock CLK3. The sampled output of comparator latch 403d are UP3 and DN3 which are provided to logic <NUM>/102c, in accordance with some embodiments.

While the embodiments illustrate four comparator latches that sample and compare data using four multi-phase clocks, other number of comparator latches and multi-phase clocks may be used for sampling and comparing data against reference voltages to achieve a desired level of AC impedance calibration.

In some embodiments, bias generator <NUM>/<NUM> is implemented as a voltage divider (e.g., using a resistor ladder). In other embodiments, other suitable implementations for bias generator <NUM>/<NUM> may be used. In some embodiments, bias generator <NUM>/<NUM> is shared with detector <NUM>/102a and RCOMP <NUM>. In some embodiments, different bias generators are used for detector <NUM>/102a and RCOMP <NUM>.

In some embodiments, logic <NUM>/102c comprises a plurality of sequential logics (e.g., flip-flops) that sample Up and Down signals (e.g., UP0, DN0, UP1, DN1, UP2, DN2, and UP3 and DN3). One purpose of the plurality of sequential logics is to filter any possible noise in the Up and Down signals before impedance codes are adjusted by decision logic 102c and Increment/Decrement/Lock logic 102d. <FIG> illustrates one possible decision making process for generating impedance codes.

<FIG> illustrates a finite state machine (FSM) <NUM> for adaptively adjusting compensated impedance by monitoring an output of a driver, according to some embodiments of the disclosure. It is pointed out that those elements of <FIG> having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. In this example, a four state FSM is illustrated. In other embodiments, more states can be added to enhance the capability of FSM <NUM>. These four states are the Start state <NUM>, Decrement (DEC) state <NUM>, Lock state <NUM>, and Increment (INC) state <NUM>.

In some embodiments, FSM <NUM> starts at the Start state <NUM>. When detector 102a indicates an up or a down case (e.g., when UP=<NUM>, DN=<NUM>, or when UP=<NUM>, DN=<NUM>) then FSM <NUM> moves to one of the DEC state <NUM> or INC state <NUM> in the next clock cycle. FSM <NUM> then remains in that state so long as the indicators of up and down signals are the same. For example, when UP=<NUM> and DN=<NUM>, and FSM <NUM> is in DEC state <NUM>, then FSM <NUM> remains in DEC state <NUM>. Likewise, when UP=<NUM> and DN=<NUM>, and FSM <NUM> is in INC state <NUM>, then FSM <NUM> remains in INC state <NUM>.

In some embodiments, when FSM <NUM> is the DEC state <NUM> and the state of up and down indicators changes such that one of the indicators is in an asserted state, then FSM <NUM> moves back to the Start state <NUM>. For example, when UP changes from <NUM> to <NUM>, and DN changes from <NUM> to <NUM> while FSM <NUM> is in the DEC state <NUM>, then FSM <NUM> moves to Start state <NUM>. In some embodiments, when FSM <NUM> is the INC state <NUM> and the state of up and down indicators changes such that one of the indicators is in an asserted state, then FSM <NUM> moves back to the Start state <NUM>. For example, when UP changes from <NUM> to <NUM>, and DN changes from <NUM> to <NUM> while FSM <NUM> is in the INC state <NUM>, then FSM <NUM> moves to Start state <NUM>.

In some embodiments, when FSM <NUM> is in one of the Start state <NUM>, DEC state <NUM>, or INC state <NUM>, and up/down indicators become zero (e.g., indicating that that further changes to the impedance codes is not needed), then FSM <NUM> moves to the Lock state <NUM>. In this state, the impedance codes (e.g., Rpull[<NUM>:<NUM>] and Rpd[<NUM>:<NUM>]) are locked or frozen till Resetb is asserted. For example, when in Lock state <NUM> and Resetb is asserted, FSM moves from Lock state <NUM> to Start state <NUM>.

FSM <NUM> generates increment and decrement codes to cater for AC impedance mismatch, in accordance with some embodiments. In some embodiments, FSM <NUM> increments or decrements by one code per clock cycle to cater impedance mismatch. Finding the correct codes continues till the time UP/DN indication goes to <NUM>, in accordance with some embodiments. In some embodiments, the locked impedance codes are used for actual data transmission. In some embodiments, FSM <NUM> operates during a training Sequence (e.g., sequence <NUM>) of Data. In some embodiments, once the impedance codes are locked, those codes are used during actual data transmission. A person skilled in the art would appreciate that the state machine logic for INC and DEC logic may change if the logic to implement the machine is reversed or opposite polarity control signals (Up and Down) are used. In some cases, logic for UP/DN may change too when INC and DEC logic is changed.

<FIG> illustrates flowchart <NUM> of a method for adaptively adjusting compensated pull-up impedance by monitoring an output of a driver when data is driving high, according to some embodiments of the disclosure. It is pointed out that those elements of <FIG> having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

Flowchart <NUM> begins at the "Start" block and then moves to block <NUM>. At block <NUM>, a determination is made whether data on the output of driver <NUM> is High or Low. If the Data is High, then the process proceeds to block <NUM>, otherwise the process proceeds to block <NUM> as described with reference to <FIG>. Referring back to <FIG>, at block <NUM>, detector 102a samples data using multi-phase clock signals and compares it with the reference voltages VrefHi_1 and VrefLow_1. The output of this block are Up and Down indicators associated with overshoot/ringing.

At block <NUM>, a determination is made whether consecutive Up and Down data are high. One reason for checking consecutive Up and Down data (generated by detector 102a) is to filter any noise on the Up and Down data before impedance codes are adjusted. If a determination is made that consecutive sampled data is high (e.g., an overshoot condition is indeed captured) then pull-up impedance codes are incremented at block <NUM> (e.g., Rup=Rup-<NUM>). The process then proceeds to block <NUM>. At block <NUM>, if a determination is made that consecutive sampled data are not high, then the process proceeds to block <NUM> where pull-up impedance codes are locked (e.g., Rup is defined). The process then proceeds to block <NUM> where the pull-up impedance codes are loaded to driver <NUM> to adjust impedance code for addressing AC impedance mismatch.

At block <NUM>, a determination is made whether consecutive Up and Down data are low. One reason for checking consecutive Up and Down data (generated by detector 102a) is to filter any noise on the Up and Down data before impedance codes are adjusted. If a determination is made that consecutive sampled data is low then pull-up impedance codes are decremented at block <NUM> (e.g., Rup=Rup+<NUM>). The process then proceeds to block <NUM>. At block <NUM>, if a determination is made that consecutive sampled data are not low, then the process proceeds to block <NUM> where pull-up impedance codes are locked (e.g., Rup is defined). The process then proceeds to block <NUM> where the pull-up impedance codes are loaded to driver <NUM> to adjust impedance code for addressing AC impedance mismatch.

<FIG> illustrates flowchart <NUM> of a method for adaptively adjusting compensated pull-down impedance by monitoring an output of a driver when data is driving low, according to some embodiments of the disclosure. It is pointed out that those elements of <FIG> having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

Flowchart <NUM> begins at the "Start" block and then moves to block <NUM>. At block <NUM>, a determination is made whether data on the output of driver <NUM> is High or Low. If the Data is High, then the process proceeds to block <NUM> of <FIG>, otherwise the process proceeds to block <NUM>. Referring back to <FIG>, at block <NUM>, detector 102a samples data using multi-phase clock signals and compares with the reference voltages VrefHi_0 and VrefLow_0. The output of this block are Up and Down indicators associated with undershoot/ringing.

At block <NUM>, a determination is made whether consecutive Up and Down data are high. One reason for checking consecutive Up and Down data (generated by detector 102a) is to filter any noise on the Up and Down data before impedance codes are adjusted. If a determination is made that consecutive sampled data is low (e.g., an undershoot condition is indeed captured) then pull-down impedance codes are incremented at block <NUM> (e.g., Rdn=Rdn-<NUM>). The process then proceeds to block <NUM>. At block <NUM>, if a determination is made that consecutive sampled data are not high, then the process proceeds to block <NUM> where pull-down impedance codes are locked (e.g., Rdn is defined). The process then proceeds to block <NUM> where the pull-down impedance codes are loaded to driver <NUM> to adjust impedance code for addressing AC impedance mismatch.

At block <NUM>, a determination is made whether consecutive Up and Down data are low. One reason for checking consecutive Up and Down data (generated by detector 102a) is to filter any noise on the Up and Down data before impedance codes are adjusted. If a determination is made that consecutive sampled data is high then pull-down impedance codes are decremented at block <NUM> (e.g., Rdn=Rdn+<NUM>). The process then proceeds to block <NUM>. At block <NUM>, if a determination is made that consecutive sampled data are not low, then the process proceeds to block <NUM> where pull-down impedance codes are locked (e.g., Rdn is defined). The process then proceeds to block <NUM> where the pull-dn impedance codes are loaded to driver <NUM> to adjust impedance code for addressing AC impedance mismatch.

Although the blocks in the flowchart with reference to <FIG> are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in <FIG> are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

<FIG> illustrates a smart device or a computer system or a SoC (System-on-Chip) with an apparatus for adaptively adjusting compensated impedance by monitoring an output of a driver, according to some embodiments. It is pointed out that those elements of <FIG> having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

<FIG> illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device <NUM> represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device <NUM>.

In some embodiments, computing device <NUM> includes a first processor <NUM> with an apparatus for adaptively adjusting compensated impedance by monitoring an output of a driver, according to some embodiments discussed. Other blocks of the computing device <NUM> may also include an apparatus for adaptively adjusting compensated impedance by monitoring an output of a driver, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within <NUM> such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

In one embodiment, processor <NUM> (and/or processor <NUM>) can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor <NUM> include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device <NUM> to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, computing device <NUM> includes audio subsystem <NUM>, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device <NUM>, or connected to the computing device <NUM>. In one embodiment, a user interacts with the computing device <NUM> by providing audio commands that are received and processed by processor <NUM>.

Display subsystem <NUM> represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device <NUM>. Display subsystem <NUM> includes display interface <NUM>, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface <NUM> includes logic separate from processor <NUM> to perform at least some processing related to the display. In one embodiment, display subsystem <NUM> includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller <NUM> represents hardware devices and software components related to interaction with a user. I/O controller <NUM> is operable to manage hardware that is part of audio subsystem <NUM> and/or display subsystem <NUM>. Additionally, I/O controller <NUM> illustrates a connection point for additional devices that connect to computing device <NUM> through which a user might interact with the system. For example, devices that can be attached to the computing device <NUM> might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller <NUM> can interact with audio subsystem <NUM> and/or display subsystem <NUM>. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device <NUM>. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem <NUM> includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller <NUM>. There can also be additional buttons or switches on the computing device <NUM> to provide I/O functions managed by I/O controller <NUM>.

In one embodiment, I/O controller <NUM> manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device <NUM>. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

In one embodiment, computing device <NUM> includes power management <NUM> that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem <NUM> includes memory devices for storing information in computing device <NUM>. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem <NUM> can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device <NUM>.

Elements of embodiments are also provided as a machine-readable medium (e.g., memory <NUM>) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory <NUM>) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

Connectivity <NUM> includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device <NUM> to communicate with external devices. The computing device <NUM> could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Connectivity <NUM> can include multiple different types of connectivity. To generalize, the computing device <NUM> is illustrated with cellular connectivity <NUM> and wireless connectivity <NUM>. Cellular connectivity <NUM> refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) <NUM> refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

In some embodiments, Peripheral connections <NUM> include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device <NUM> could be a peripheral device ("to" <NUM>) to other computing devices, as well as have peripheral devices ("from" <NUM>) connected to it. The computing device <NUM> commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device <NUM>. Additionally, a docking connector can allow computing device <NUM> to connect to certain peripherals that allow the computing device <NUM> to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, the computing device <NUM> can make peripheral connections <NUM> via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures e.g., Dynamic RAM (DRAM) may use the embodiments discussed. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

Claim 1:
An apparatus (<NUM>;<NUM>) comprising:
a driver (<NUM>;<NUM>) having pull-up impedance legs, wherein a number of active pull-up impedance legs is to determine a pull-up output impedance of the driver (<NUM>;<NUM>); further comprising
a detector (102a;<NUM>) coupled to an output of the driver (<NUM>;<NUM>), wherein the detector (102a;<NUM>) is to receive a multiphase clock, the detector (102a;<NUM>) is to sample data at the output at least two clock edges separated by a delay, the detector (102a;<NUM>) to compare the sampled data with a first threshold voltage and a second threshold voltage, wherein the first and second threshold voltages are nearer to a logic high level of the data than to a logic low level of the data, or wherein the first and second threshold voltages are nearer to a logic low level of the data than to a logic high level of the data;
decision logic (102c;<NUM>) coupled to the detector (102a;<NUM>), the decision logic (102c;<NUM>) to generate a code based on an indication from the detector (102a;<NUM>); and
logic (102d) to receive the code from the decision logic (102c;<NUM>) and to further receive a base number of process, voltage, and temperature, PVT, compensated active number of pull-up impedance legs, and wherein the logic (102d) is to turn on or turn off one or more pull-up impedance legs over the base number to change the number of active pull-up impedance legs according to the code.