Patent Description:
Numerous embodiments are disclosed for a non-volatile memory cell array formed in a p-well in a deep n-well in a p-substrate. During an erase operation, a negative voltage is applied to the p-well, which reduces the peak positive voltage required to erase the cells in the array.

<CIT> discribes that in an array of nonvolatile memory cells, as many memory cells as desired and indeed even the entire array of memory cells may be placed in a single region of the bulk, illustratively a p-well. Peripheral circuitry is used to in effect section the memory array into blocks and groups of blocks, and to establish suitable biasing and counter-biasing within those blocks and groups during page or block erase operations to limit erase disturb. Each group is provided with its own set of voltage switches, which furnishes the bias voltages for the various modes of operation, including erase. Each of the voltage switches furnish either a large positive voltage when its group is selected, or a large negative voltage when its group is unselected. The size of the group is established as a compromise between degree of erase disturb and substrate area required for the voltage switches.

<CIT> describes NAND architecture Flash memory strings, memory arrays, and memory devices that utilize depletion mode floating gate memory cells. Depletion mode floating gate memory cells allegedly allow for increased cell current through lower channel rdS resistance and decreased "narrow width" effect, allegedly allowing for increased scaling of NAND memory cell strings.

<CIT> describes a method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

<CIT> describes that a nonvolatile memory array has nonvolatile memory cells arranged in rows and columns where each column has a bit line and source line associated with and in parallel with the nonvolatile memory cells. In programming the nonvolatile memory cell, approximately equal program voltage levels are applied to a drain and a source of a selected charge retaining transistor such that the difference in the voltage between the drain and the source of the selected charge retaining transistor is less than a drain to source breakdown voltage of the selected charge retaining transistor to prevent drain-to-source punch through. In programming or erasing the nonvolatile memory cell a control gate and a bulk program voltage level is applied to a control gate and bulk such that the magnitude of the control gate and bulk program voltage levels is less than a breakdown voltage level of peripheral circuitry.

<CIT> describes that during a program, read, or erase operation of one or more non-volatile flash memory cells in an array of non-volatile flash memory cells, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected non-volatile flash memory cells. The negative voltage is generated by a negative high voltage level shifter using one of several embodiments disclosed herein.

<CIT> describes that the negative supply voltage (<NUM>) and isolation well bias (<NUM>) used by the wordline drivers (<NUM>) during erase are decoded separately from the decoding of the inputs of the individual wordline drivers. The wordline drivers selectively drive wordlines with a wordline voltage from either a first supply voltage source or a second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors (<NUM>, <NUM>). Each supply voltage selector in the set is coupled with a subset of the set of drivers.

Different types of non-volatile memories are well known. For example, <CIT> ("the "<NUM> patent"), discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell <NUM> is shown in <FIG>. Each memory cell <NUM> includes source region <NUM> and drain region <NUM> formed in semiconductor substrate <NUM>, with channel region <NUM> there between. Floating gate <NUM> is formed over and insulated from (and controls the conductivity of) a first portion of channel region <NUM>, and over a portion of source region <NUM>. Word line terminal <NUM> (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of channel region <NUM>, and a second portion that extends up and over the floating gate <NUM>. Floating gate <NUM> and word line terminal <NUM> are insulated from substrate <NUM> by a gate oxide. Bitline <NUM> is coupled to drain region <NUM>.

Memory cell <NUM> is erased (where electrons are removed from the floating gate) by placing a high positive voltage (with respect to substrate <NUM>) on word line terminal <NUM>, which causes electrons on floating gate <NUM> to tunnel through the intermediate insulation from floating gate <NUM> to word line terminal <NUM> via Fowler-Nordheim (FN) tunneling.

Memory cell <NUM> is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage (with respect to substrate <NUM>) on word line terminal <NUM>, and a positive voltage on source region <NUM>. Electron current will flow from drain region <NUM> towards source region <NUM>. The electrons will accelerate and become heated when they reach the gap between word line terminal <NUM> and floating gate <NUM>. Some of the heated electrons will be injected through the gate oxide onto the floating gate <NUM> due to the attractive electrostatic force from floating gate <NUM>.

Memory cell <NUM> is read by placing positive read voltages (with respect to substrate <NUM>) on drain region <NUM> and word line terminal <NUM> (which turns on the portion of the channel region <NUM> under the word line terminal). If floating gate <NUM> is positively charged (i.e. erased of electrons), then the portion of channel region <NUM> under floating gate <NUM> is turned on as well, and current will flow across channel region <NUM>, which is sensed as the erased or "<NUM>" state. If floating gate <NUM> is negatively charged (i.e., programmed with electrons), then the portion of the channel region <NUM> under floating gate <NUM> is mostly or entirely turned off, and current will not flow (or there will be little flow) across channel region <NUM>, which is sensed as the programmed or "<NUM>" state.

Table No. <NUM> depicts typical voltage and current ranges that can be applied to the terminals of memory cell <NUM> for performing read, erase, and program operations:.

The voltages of Table No. <NUM> are with reference to substrate <NUM>, to which 0V is applied during a read, erase, or program operation.

Other split gate memory cell configurations, which are other types of flash memory cells, are known.

For example, <FIG> depicts a four-gate memory cell <NUM> comprising source region <NUM>, drain region <NUM>, floating gate <NUM> over a first portion of channel region <NUM>, select gate <NUM> (typically coupled to a word line, WL) over a second portion of the channel region <NUM>, control gate <NUM> over the floating gate <NUM>, and erase gate <NUM> over the source region <NUM>. Programming is performed by heated electrons from the channel region <NUM> injected through the gate oxide onto floating gate <NUM> due to the attractive electrostatic force from the floating gate <NUM>. Erasing is performed by electrons tunneling from floating gate <NUM> to erase gate <NUM>.

A voltage of 0V is be applied to substrate <NUM> during a read, erase, or program operation.

<FIG> depicts a three-gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is identical to memory cell <NUM> of <FIG> except that memory cell <NUM> does not have a separate control gate. The erase operation (whereby erasing occurs through use of the erase gate) and read operation are similar to that of memory cell <NUM> of <FIG> except that no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage must be applied on the source line during a program operation to compensate for a lack of control gate bias.

A voltage of 0V is applied to substrate <NUM> during a read, erase, or program operation.

Space within a semiconductor die is precious. In the prior art systems described above, substantial space is required for circuits external to the array that are necessary for read, program, and/or erase operations. For example, the high voltages required for erase operations require special high voltage generation and regulation circuitry, which in turns requires high voltage transistors that require large areas on the semiconductor die due to thicker gate oxide, longer channel length, and wider physical spacing.

What is needed is a new architecture for an array of non-volatile memory cells that reduces the voltage required for erase operations, which would then reduce the space required for high voltage generation and regulation circuitry.

The invention relates to a non-volatile memory system according to independent claim <NUM>.

The embodiments described herein enable a negative-voltage to be applied to a p-well surrounding certain components to enable a lower voltage to be used during erase operations of non-volatile memory cells.

<FIG> depicts a block diagram of non-volatile memory system <NUM>. Non-volatile memory system <NUM> comprises array <NUM>, row decoder <NUM>, high voltage decoder <NUM>, column decoders <NUM>, bit line drivers (also known as column drivers) <NUM> (for controlling program (current) on bitline terminals), output circuit <NUM>, control logic <NUM>, and bias generator <NUM>. Non-volatile memory system <NUM> further comprises high voltage generation block <NUM>, which comprises charge pump <NUM>, charge pump regulator <NUM>, and high voltage level generator <NUM>. Non-volatile memory system <NUM> further comprises (program/erase, or weight tuning) algorithm controller <NUM>, analog circuitry <NUM>, control engine <NUM> (that may include special functions such as arithmetic functions, activation functions, or embedded microcontroller logic, without limitation), and test control logic <NUM>.

Output circuit <NUM> may include circuits such as digital sensing circuitry to convert cell current into a logic '<NUM>' or '<NUM>', or analog sensing circuitry such as a ADC (analog to digital converter) to convert neuron analog output to digital bits), AAC (analog to analog converter) such as a current to voltage converter, logarithmic converter, APC (analog to pulse(s) converter), analog to time modulated pulse converter, or any other type of converters. The output circuit <NUM> may implement an activation function such as a rectified linear activation function (ReLU) or sigmoids. Output circuit <NUM> may implement statistic normalization, regularization, up/down scaling/gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs. Output circuit <NUM> may implement a temperature compensation function for bitline outputs.

In the embodiments described below with reference to <FIG>, the array, and optionally other components, are placed within a p-well surrounded by, and on top of, a deep n-well. A negative voltage, in relation to p-substrate, is then be applied to the p-well, by bias generator <NUM> or another voltage source, during certain operations such as erase operations of non-volatile memory cells. This reduces the maximum voltage required for the erase operation, thereby reducing the overall size and power of the high voltage generation block <NUM>.

<FIG> depicts a top view of non-volatile memory system <NUM>. Non-volatile memory system <NUM> comprises array <NUM>, row decoder <NUM> (an example of row decoder <NUM> in <FIG>), and high voltage decoder <NUM> (an example of high voltage decoder <NUM> in <FIG>). Array <NUM> is formed within p-well <NUM>, which is formed within deep n-well <NUM>, and deep n-well <NUM> is formed within p-substrate <NUM>. P-well <NUM> hence can receive a different voltage (including but not limited to a negative voltage) due to its isolation from p-substrate <NUM> by deep n-well <NUM>. For example, p-substrate <NUM> can be biased at 0V, deep n-well <NUM> can be biased at <NUM>-2V, and p-well <NUM> can be biased at -<NUM>. 1V to - 10V. These bias voltages can be generated by bias generator <NUM> or another voltage source.

<FIG> depicts non-volatile memory system <NUM>. Non-volatile memory system <NUM> comprises array <NUM>, row decoder <NUM> (an example of row decoder <NUM> in <FIG>), and high voltage decoder <NUM> (an example of high voltage decoder <NUM> in <FIG>).

Array <NUM> is formed within p-well <NUM>, and p-well <NUM> is formed within deep n-well <NUM>.

Row decoder <NUM> is formed within p-well <NUM>, which p-well <NUM> is formed within deep n-well <NUM>.

High voltage decoder <NUM> is formed within p-well <NUM>, and p-well <NUM> is formed within deep n-well <NUM>.

Deep n-wells <NUM>, <NUM>, and <NUM> are respectively formed within (and on top of) p-substrate <NUM>. Optionally, deep n-wells <NUM>, <NUM>, and <NUM> can be separate deep n-wells or part of a common deep n-well.

P-well <NUM> containing array <NUM> hence can be driven with a negative voltage, in relation to p-substrate <NUM>, by bias generator <NUM> or another voltage source due to its isolation from p-substrate <NUM> by deep n-well <NUM>.

P-well <NUM> containing high voltage decoder <NUM> hence can be driven with a negative voltage, in relation to p-substrate <NUM>, by bias generator <NUM> or another voltage source due to its isolation from p-substrate <NUM> by deep n-well <NUM>.

For example, p-substrate <NUM> can be biased at 0V, deep n-wells <NUM>, <NUM>, and <NUM> can be biased at <NUM>-3V, and p-wells <NUM>, <NUM>, and <NUM> can be biased at -<NUM>. 1V to -10V. These bias voltages can be generated by bias generator <NUM> or another voltage source.

<FIG> depicts non-volatile memory system <NUM> according to the invention. Non-volatile memory system <NUM> comprises array <NUM>, array <NUM>, low voltage decoder <NUM>, and high voltage decoder <NUM>. Array <NUM> is formed within p-well <NUM>, and p-well <NUM> is formed within deep n-well <NUM>. Array <NUM> is formed within p-well <NUM>, and p-well <NUM> is formed within deep n-well <NUM>. Low voltage decoder <NUM> is formed within p-well <NUM>, and p-well <NUM> is formed within deep n-well <NUM>. High voltage decoder <NUM> is formed within p-well <NUM>, and p-well <NUM> is formed within deep n-well <NUM>. Optionally, deep n-wells <NUM>, <NUM>, <NUM>, and <NUM> can be separate deep n-wells or part of a common deep n-well. The p substrate PSUB <NUM> is the substrate that all circuits, i.e., array <NUM>, array <NUM>, low voltage decoder <NUM>, and high voltage decoder <NUM>, are formed upon.

<FIG> depicts non-volatile memory system <NUM> according to the invention. Non-volatile memory system <NUM> comprises array <NUM>, array <NUM>, low voltage decoder <NUM>, low voltage decoder <NUM>, high voltage decoder <NUM>, and high voltage decoder <NUM>. Array <NUM> is formed within p-well <NUM>, and p-well 807is formed within deep n-well <NUM>. Array <NUM> is formed within p-well <NUM>, and p-well <NUM> is also formed within deep n-well <NUM>. Low voltage decoder <NUM> is formed within p-well <NUM>, and p-well <NUM> is formed within deep n-well <NUM>. Low voltage decoder <NUM> is formed within p-well <NUM>, and p-well 812is formed within deep n-well <NUM>. High voltage decoder <NUM> is formed within p-well <NUM>, and p-well 814is formed within deep n-well <NUM>. High voltage decoder <NUM> is formed within p-well <NUM>, and p-well <NUM> is formed within deep n-well <NUM>. Optionally, deep n-wells <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> can be separate deep n-wells or part of a common deep n-well. P-substrate <NUM> is the substrate that all circuits, i.e., array <NUM>, array <NUM>, low voltage decoder <NUM>, low voltage decoder <NUM>, high voltage decoder <NUM>, and high voltage decoder <NUM>, are formed upon.

P-well <NUM> or <NUM> hence can go be driven to a negative voltage, in respect to p-substrate <NUM>, independently, by bias generator <NUM> or another voltage source, due to its isolation from p-substrate <NUM> by deep n-well <NUM>. Similarly, p-wells <NUM>, <NUM>, <NUM>, <NUM> hence can be driven to a negative voltage independently, in respect to p-substrate <NUM>, by bias generator <NUM> or another voltage source, due to their isolation from p-substrate <NUM> by respective deep n-wells <NUM>, <NUM>, <NUM>, and <NUM>.

<FIG> depicts cross-section <NUM>. Array <NUM> or low voltage decoder, row decoder <NUM>, or high voltage decoder <NUM> (which are representative of the arrays, row decoders, and high voltage decoders, respectively, depicted in <FIG>) is formed within p-well <NUM>, p-well <NUM> is formed within deep n-well <NUM>, and deep n-well <NUM> is formed within p-substrate <NUM>. P-well terminal <NUM> provides access to p-well <NUM> and can be used, for example, to apply a negative voltage (in relation to p-substrate <NUM>) to p-well <NUM> by bias generator <NUM> or another voltage source during an erase operation. N-well terminal <NUM> is used to apply a bias voltage to deep n-well <NUM>, and p-substrate terminal <NUM> is used to apply a bias voltage (which can include 0V) to p-substrate <NUM>. P- substrate <NUM> is the substrate that all circuits, i.e., array <NUM> or low voltage decoder, row decoder <NUM>, or high voltage decoder <NUM>, are formed upon.

Optionally, p-substrate <NUM> in <FIG> can be biased by bias generator <NUM> or another voltage source at a negative voltage such as - <NUM>. 1V to -3V instead of 0V.

Using the architectures of <FIG>, the following operating voltages can be used to perform read, program, and erase operations on non-volatile memory cells <NUM>, <NUM>, and <NUM> of <FIG>, with the understanding that substrate <NUM> (which is a p-substrate) in <FIG> is modified to include a p-well within a deep n-well, such as shown in cross-section <NUM> of <FIG>, where substrate <NUM> then becomes p-substrate <NUM>, deep n-well <NUM> is formed within substrate <NUM>, and p-well <NUM> is formed within deep n-well <NUM>, where arrays of memory cells <NUM>, <NUM>, and <NUM> are formed within p-well <NUM>. In addition, p-well <NUM> is accessed using p-well-terminal <NUM>, deep n-well <NUM> is accessed using n-well terminal <NUM>, and p-substrate <NUM> is accessed using p-substrate <NUM> as in <FIG>. In this configuration, p-well <NUM> acts as a (virtual) p-substrate for the memory cells of the array and for the other components.

<NUM>-<NUM> that follow contain exemplary operating voltages to be applied to memory cells <NUM>, <NUM>, and <NUM> when configured as in <FIG>. In these examples, a voltage of 0V is applied to p-substrate <NUM> (substrate <NUM>) through p-substrate terminal <NUM>, a voltage of <NUM>-2V is applied to deep n-well <NUM> through n-well terminal <NUM>, and a voltage of -<NUM>. 1V to -12V is applied to p-well <NUM> through p-well terminal <NUM> by bias generator <NUM> or another voltage source.

Table No. <NUM> depicts a first set of operating voltages (defined with respect to substrate <NUM>) for memory cell <NUM> of <FIG> when the substrate <NUM> is modified to include p-well <NUM> within deep n-well <NUM> within substrate <NUM>:.

Table No. <NUM> depicts a second set of operating voltages for memory cell <NUM> of <FIG> when the substrate includes a p-well within a deep n-well:.

P-well <NUM> is particularly advantageous in a situation where a negative voltage is applied to one or more terminals of the cell during an erase operation, because in that situation, applying a negative voltage to p-well <NUM> using bias generator <NUM> or another voltage source will reduce stress on the gate oxide regions when the negative voltage is applied to the terminal, as p-well <NUM> will serve as a virtual substrate for the cell that is biased to a negative voltage.

Table No. <NUM> is appropriate if stress on gate oxide regions is not a concern, while Table No. <NUM> is appropriate if stress on gate oxide regions is a concern. In Table No. <NUM>, a word line voltage of 0V is applied to un-selected cells during an erase operation, while in Table No. <NUM>, a word line voltage of -<NUM>. 5V is applied to unselected cells during an erase operation, due to the fact that it is desired to reduce stress on the gate oxide regions of memory cell <NUM> as well as the peripheral (decoding) transistor for the <NUM>. 5V gate oxide. In the operation of Table No. <NUM>, stress on the gate oxide regions of the decoding circuits is not a concern because the absolute voltage required will not cause the voltage across a gate oxide region to exceed the gate oxide break down voltage for both the decoding circuitry and the cells, and as a result, an isolated p-sub well <NUM> is not needed for the decoding circuitry. By contrast, in the implementation of Table <NUM>, bias generator <NUM> or another voltage source applies negative voltages to certain terminals to reduce stress on the gate oxide regions, and as a result, an isolated p-sub well <NUM> is advantageous for the decoding circuitry.

Table No. <NUM> depicts a first set of operating voltages for memory cell <NUM> of <FIG> when the substrate includes a p-well within a deep n-well:.

For the same reasons discussed above with respect to Table Nos. <NUM> and <NUM>, the use of p-well <NUM> would be particularly advantageous for Table No. <NUM> and to a greater extent than for Table No. <NUM>.

Claim 1:
A non-volatile memory system (<NUM>), comprising:
a deep n-well (<NUM>) formed in a p-substrate (<NUM>) in a semiconductor die;
a first p-well (<NUM>) formed within the deep n-well;
a second p-well (<NUM>) formed within the deep n-well;
a first array (<NUM>) of non-volatile split-gate flash memory cells formed within the first p-well, each non-volatile split-gate flash memory cell in the first array comprising a floating gate and a plurality of terminals;
a second array (<NUM>) of non-volatile split gate flash memory cells formed within the second p-well, each non-volatile split-gate flash memory cell in the second array comprising a floating gate and a plurality of terminals;
a bias generator (<NUM>) to apply a negative voltage to the first p-well during an erase operation of one or more of the non-volatile split-gate flash memory cells in the first array and to apply independently a negative voltage to the second p-well during an erase operation of one or more of the non-volatile split-gate flash memory cells in the second array;
a low voltage decoder (<NUM>, <NUM>) formed within a third p-well (<NUM>, <NUM>) formed within a second deep n-well (<NUM>, <NUM>); and
a high voltage decoder circuit (<NUM>, <NUM>) formed within a fourth p-well (<NUM>, <NUM>) formed within a third deep n-well (<NUM>, <NUM>).