Patent Description:
Mobile radio frequency (RF) chips (e.g., mobile RF transceivers) have migrated to a deep sub-micron process node due to cost and power consumption considerations. Designing mobile RF transceivers is further complicated by added circuit functions for supporting communication enhancements, such as carrier aggregation. Further design challenges for mobile RF transceivers include using passive devices, which directly affect analog/RF performance considerations, including mismatch, noise, and other performance considerations.

Passive devices may involve high performance capacitor components. For example, analog integrated circuits use various types of passive devices, such as integrated capacitors. These integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, p-n junction capacitors, metal-insulator-metal (MIM) capacitors, poly-to-poly capacitors, metal-oxide-metal (MOM) capacitors, and other like capacitor structures. MOM capacitors are also known as vertical parallel plate (VPP) capacitors, natural vertical capacitors (NVCAP), lateral flux capacitors, comb capacitors, as well as interdigitated finger capacitors. MOM capacitors exhibit beneficial characteristics including high capacitance density, low parasitic capacitance, superior RF characteristics, and good matching characteristics without additional masks or process steps relative to other capacitor structures.

MOM capacitors are one of the most widely used capacitors due to their beneficial characteristics. MOM capacitor structures realize capacitance by using the fringing capacitance produced by sets of interdigitated fingers. For example, MOM capacitors harness lateral capacitive coupling between plates formed by metallization layers and wiring traces.

The design of mobile RF transceivers may include integrating MOM capacitors with inductors and/or transformers. Unfortunately, integrating MOM capacitors with inductors and/or transformers may degrade a performance of the inductors and/or transformers.

<CIT> ("Metal-Oxide-Metal (Mom) Capacitor With Reduced Magnetic Coupling To Neighboring Circuit And High Series Resonance Frequency") discloses metal-oxide-metal (MOM) type capacitors which include a first terminal configured to receive a first voltage, the first terminal being formed on a first dielectric layer; a first set of fingers formed on the first dielectric layer, the first set of fingers being coupled to the first terminal via a conductive trace formed on a second dielectric layer; a second terminal configured to receive second voltage, the second terminal being formed on the first dielectric layer; and a second set of fingers formed on the first dielectric layer, the second set of fingers being coupled to the second terminal, wherein the fingers of the second set are interspersed with the fingers of the first set.

<CIT> ("BEOL Wiring Structures That Include an On-Chip Inductor and an On-Chip Capacitor, and Design Structures for a Radiofrequency Integrated Circuit") relates to back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor.

<CIT> ("Vertically Oriented Semiconductor Device And Shielding Structure Thereof') discloses a semiconductor device which includes a substrate; a capacitor disposed over the substrate; an inductor disposed over the substrate and having a coil feature surrounding the capacitor; and a shielding structure over the substrate and configured around the coil feature.

<CIT> ("Vertically Oriented Semiconductor Device And Shielding Structure Thereof") discloses a semiconductor device which includes a substrate having a horizontal surface. The semiconductor device includes an interconnect structure formed over the horizontal surface of the substrate. The interconnect structure includes an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate. The interconnect structure includes a capacitor disposed proximate to the inductor coil. The capacitor has an anode component and a cathode component. The inductor coil and the capacitor each include a plurality of horizontally extending elongate members.

<CIT> ("Inductive And Capacitive Elements For Semiconductor Technologies With Minimum Pattern Density Requirements") relates to a semiconductor device comprising a plurality of layers, the semiconductor device comprising: - a substrate having a first major surface, - an inductive element fabricated on the first major surface of the substrate, the inductive element comprising at least one conductive line, and - a plurality of tilling structures in at least one layer, wherein the plurality of tilling structures are electrically connected together and are arranged in a geometrical pattern so as to substantially inhibit an inducement of an image current in the tilling structures by a current in the inductive element. It is an advantage of the above semiconductor device that, by using such tilling structures, an inductive element with improved quality factor is obtained. The present invention also provides a method for providing an inductive element in a semiconductor device comprising a plurality of layers.

<CIT> discloses a multilayer capacitor structure having an array of concentric ringshaped plates for deep sub-micron CMOS.

An integrated circuit includes a capacitor in one or more back-end-of-line (BEOL) interconnect levels. The capacitor includes multiple folded capacitor fingers having multiple sides and a pair of manifolds on a same side of the folded capacitor fingers. Each of the pair of manifolds is coupled to one or more of the folded capacitor fingers. The integrated circuit also includes an inductive trace having one or more turns in one or more different BEOL interconnect levels. The inductive trace overlaps one or more portions of the capacitor.

A method of fabricating an integrated circuit includes fabricating a capacitor in one or more back-end-of-line (BEOL) interconnect levels. The capacitor includes multiple folded capacitor fingers having multiple sides and a pair of manifolds on a same side of the multiple sides of the folded capacitor fingers. Each of the pair of manifolds is coupled to one or more of the folded capacitor fingers. The method also includes fabricating an inductive trace having one or more turns in one or more different BEOL interconnect levels. The inductive trace overlaps one or more portions of the capacitor.

An integrated circuit includes a capacitor in one or more back-end-of-line (BEOL) interconnect levels. The capacitor includes multiple folded capacitor fingers having multiple sides and a pair of manifolds on a same side of the folded capacitor fingers. Each of the pair of manifolds is coupled to one or more of the folded capacitor fingers. The integrated circuit also includes means for storing electrical energy in a magnetic field within one or more different BEOL interconnect levels. The electrical energy storing means overlaps one or more portions of the capacitor.

This has outlined, rather broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the present disclosure will be described below.

For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

It will be apparent, however, to those skilled in the art that these concepts may be practiced without these specific details.

As described herein, the use of the term "and/or" is intended to represent an "inclusive OR", and the use of the term "or" is intended to represent an "exclusive OR". As described herein, the term "exemplary" used throughout this description means "serving as an example, instance, or illustration," and should not necessarily be construed as preferred or advantageous over other exemplary configurations. As described herein, the term "coupled" used throughout this description means "connected, whether directly or indirectly through intervening connections (e.g., a switch), electrical, mechanical, or otherwise," and is not necessarily limited to physical connections. Additionally, the connections can be such that the objects are permanently connected or releasably connected. The connections can be through switches. As described herein, the term "proximate" used throughout this description means "adjacent, very near, next to, or close to. " As described herein, the term "on" used throughout this description means "directly on" in some configurations, and "indirectly on" in other configurations.

Passive devices in mobile RF transceivers may include high performance capacitor components. For example, analog integrated circuits use various types of passive devices, such as integrated capacitors. These integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, p-n junction capacitors, metal-insulator-metal (MIM) capacitors, poly-to-poly capacitors, metal-oxide-metal (MOM) capacitors, and other like capacitor structures. Capacitors are generally passive elements used in integrated circuits for storing an electrical charge. For example, parallel plate capacitors are often made using plates or structures that are conductive with an insulating material between the plates. The amount of storage, or capacitance, for a given capacitor is contingent upon the materials used to make the plates and the insulator, the area of the plates, and the spacing between the plates. The insulating material is often a dielectric material.

These parallel plate capacitors consume a large area on a semiconductor chip because many designs place the capacitor over the substrate of the chip. Unfortunately, this approach reduces the available area for active devices. Another approach is to create a vertical structure, which may be known as a vertical parallel plate (VPP) capacitor. VPP capacitor structures may be created through stacking interconnect layers on a chip.

VPP capacitors structures, however, have lower capacitive storage, or lower "density," in that these structures do not store much electrical charge. In particular, the interconnect and via layer interconnect traces used to fabricate VPP capacitors may be very small in size. The spacing between the interconnects and via layer conductive traces in VPP structures is limited by design rules, which often results in a large area for achieving certain desired capacitance for such structures. Although described as "vertical," these structures can be in any direction that is substantially perpendicular to the surface of the substrate, or at other angles that are not substantially parallel to the substrate.

A MOM capacitor as well as a MOS capacitor are examples of VPP capacitors. MOM capacitors are one of the most widely used capacitors due to their beneficial characteristics. In particular, MOM capacitors are typically used for providing high quality capacitors in semiconductor processes without incurring the cost of an extra processing step relative to other capacitor structures. MOM capacitor structures realize capacitance by using the fringing capacitance produced by sets of interdigitated fingers. That is, MOM capacitors harness lateral capacitive coupling between plates formed by metallization layers and wiring traces.

The design of mobile RF transceivers may include integrating MOM capacitors with inductors and/or transformers. Unfortunately, integrating MOM capacitors with inductors and/or transformers may degrade performance of the inductors and/or transformers. Consequently, conventional arrangements for implementing multi-turn inductors continue to consume unused area in RF integrated circuit (RFIC) analog devices.

Various aspects of the present disclosure provide a capacitor integrated within an inductor area, which is conventionally unused. The process flow for fabrication of the capacitor and inductor may include front-end-of-line (FEOL) processes, middle-of-line (MOL) processes, and back-end-of-line (BEOL) processes.

As described, the back-end-of-line interconnect layers may refer to the conductive interconnect layers (e.g., a first interconnect layer (M1) or metal one M1, metal two (M2), metal three (M3), metal four (M4), etc.) for electrically coupling to front-end-of-line active devices of an integrated circuit. The various back-end-of-line interconnect layers are formed at corresponding back-end-of-line interconnect levels, in which lower back-end-of-line interconnect levels use thinner metals layers relative to upper back-end-of-line interconnect levels. The back-end-of-line interconnect layers may electrically couple to middle-of-line interconnect layers, for example, to connect M1 to an oxide diffusion (OD) layer of an integrated circuit. The middle-of-line interconnect layer may include a zero interconnect layer (M0) for connecting M1 to an active device layer of an integrated circuit. A back-end-of-line first via (V2) may connect M2 to M3 or others of the back-end-of-line interconnect layers. It will be understood that the term "layer" includes film and is not to be construed as indicating a vertical or horizontal thickness unless otherwise stated. As described, the term "substrate" may refer to a substrate of a diced wafer or may refer to a substrate of a wafer that is not diced. Similarly, the terms chip and die may be used interchangeably.

In practice, inductors/transformers are commonly used in radio frequency integrated circuits (RFICs). These inductors/transformers are generally formed at the upper back-end-of-line (BEOL) interconnect levels because the upper BEOL interconnect levels provide thick metal layers for achieving a desired inductance. These inductors/transformers, however, occupy significant semiconductor area due to the thick metal layers provided by the upper BEOL interconnect levels. Unfortunately, adding circuits/capacitors below these inductors/capacitors normally decreases an inductor quality (Q)-factor.

Aspects of the present disclosure describe a capacitor formed in an area below the inductors/transformers, while maintaining an inductor's Q-factor. For example, the inductor may be fabricated at the upper BEOL interconnect level (e.g., M5). Conventionally, the area in a lower BEOL interconnect level (e.g., M1-M4) is unused because occupying this area generally degrades the inductor's Q-factor.

According to aspects of the present disclosure, a capacitor (e.g., a folded metal-oxide-metal (MOM) capacitor) may be formed in the lower BEOL interconnect levels, without degrading the inductor's Q-factor. In some aspects, an integrated circuit may include the capacitor in at least one back-end-of-line (BEOL) interconnect level. The capacitor may have a pair of capacitor routing terminals (or capacitor terminals) on a same side of the capacitor. For example, the capacitor may have four sides and a fourth side of the capacitor may include the pair of capacitor routing terminals. Each of the pair of capacitor routing terminals may be coupled to multiple folded capacitor routing traces (or folded capacitor fingers). The integrated circuit includes an inductive trace (e.g., an inductor trace or a transformer trace) that has one or more turns in at least one different BEOL interconnect level. The inductive trace overlaps one or more portions of the capacitor. For example, a perimeter defined by the inductive trace of the inductor may include the multiple folded capacitor routing traces while the inductive trace overlaps the pair of capacitor routing terminals (e.g., endcaps or manifolds).

In one aspect of the disclosure, a capacitor terminal of a first polarity (e.g., positive) is coupled to a first set of folded capacitor routing traces of the multiple folded capacitor routing traces. Some of the traces may directly contact the capacitor terminal while other traces may connect through one or more vias. A capacitor terminal of a second polarity (e.g., negative) is coupled to a second set of folded capacitor routing traces of the multiple folded capacitor routing traces by one or more vias.

A first folded capacitor routing trace of the first set of folded capacitor routing traces is coupled to a second folded capacitor routing trace of the first set of folded capacitor routing traces on a different interconnect level by at least one first via. A third folded capacitor routing trace of the second set of folded capacitor routing traces is coupled to a fourth folded capacitor routing trace of the second set of folded capacitor routing traces on a different interconnect level by at least one second via.

In one aspect of the disclosure, a first capacitor terminal of the first polarity (e.g., positive) is coupled to one or more folded capacitor routing traces of the first set of folded capacitor routing traces only on a first side facing a first direction. A second capacitor terminal of the second polarity (e.g., negative) is coupled to one or more folded capacitor routing traces of the second set of folded capacitor routing traces only on a first side facing the first direction.

<FIG> is a schematic diagram of a radio frequency (RF) front end (RFFE) module <NUM> employing passive devices including a capacitor <NUM> (e.g., a folded metal-oxide-metal capacitor) integrated within an inductor area of an inductor <NUM>. The RF front end module <NUM> includes power amplifiers <NUM>, duplexer/filters <NUM>, and a radio frequency (RF) switch module <NUM>. The power amplifiers <NUM> amplify signal(s) to a certain power level for transmission. The duplexer/filters <NUM> filter the input/output signals according to a variety of different parameters, including frequency, insertion loss, rejection, or other like parameters. In addition, the RF switch module <NUM> may select certain portions of the input signals to pass on to the rest of the RF front end module <NUM>.

The radio frequency (RF) front end module <NUM> also includes tuner circuitry <NUM> (e.g., first tuner circuitry 112A and second tuner circuitry 112B), the diplexer <NUM>, a capacitor <NUM>, an inductor <NUM>, a ground terminal <NUM>, and an antenna <NUM>. The tuner circuitry <NUM> (e.g., the first tuner circuitry 112A and the second tuner circuitry 112B) includes components such as a tuner, a portable data entry terminal (PDET), and a house keeping analog-to-digital converter (HKADC). The tuner circuitry <NUM> may perform impedance tuning (e.g., a voltage standing wave ratio (VSWR) optimization) for the antenna <NUM>. The RF front end module <NUM> also includes a passive combiner <NUM> coupled to a wireless transceiver (WTR) <NUM>. The passive combiner <NUM> combines the detected power from the first tuner circuitry 112A and the second tuner circuitry 112B. The wireless transceiver <NUM> processes the information from the passive combiner <NUM> and provides this information to a modem <NUM> (e.g., a mobile station modem (MSM)). The modem <NUM> provides a digital signal to an application processor (AP) <NUM>.

As shown in <FIG>, the diplexer <NUM> is between the tuner component of the tuner circuitry <NUM> and the capacitor <NUM>, the inductor <NUM>, and the antenna <NUM>. The diplexer <NUM> may be placed between the antenna <NUM> and the tuner circuitry <NUM> to provide high system performance from the RF front end module <NUM> to a chipset including the wireless transceiver <NUM>, the modem <NUM>, and the application processor <NUM>. The diplexer <NUM> also performs frequency domain multiplexing on both high band frequencies and low band frequencies. After the diplexer <NUM> performs its frequency multiplexing functions on the input signals, the output of the diplexer <NUM> is fed to an optional LC (inductor/capacitor) network including the capacitor <NUM> and the inductor <NUM>. The LC network may provide extra impedance matching components for the antenna <NUM>, when desired. Then, a signal with the particular frequency is transmitted or received by the antenna <NUM>. Although a single capacitor and inductor are shown, multiple components are contemplated.

<FIG> is a schematic diagram of a wireless local area network (WLAN) (e.g., WiFi) module <NUM> including a first diplexer <NUM>-<NUM> and an RF front end (RFFE) module <NUM> including a second diplexer <NUM>-<NUM> for a chipset <NUM>, including a folded MOM capacitor integrated within an inductor area. The WiFi module <NUM> includes the first diplexer <NUM>-<NUM> communicably coupling an antenna <NUM> to a wireless local area network module (e.g., WLAN module <NUM>). The RF front end module <NUM> includes the second diplexer <NUM>-<NUM> communicably coupling an antenna <NUM> to the wireless transceiver (WTR) <NUM> through a duplexer <NUM>. The wireless transceiver <NUM> and the WLAN module <NUM> of the WiFi module <NUM> are coupled to a modem (MSM, e.g., baseband modem) <NUM> that is powered by a power supply <NUM> through a power management integrated circuit (PMIC) <NUM>. The chipset <NUM> includes capacitors <NUM> and <NUM>, as well as an inductor(s) <NUM> to provide signal integrity.

The PMIC <NUM>, the modem <NUM>, the wireless transceiver <NUM>, and the WLAN module <NUM> each include capacitors (e.g., <NUM>, <NUM>, <NUM>, and <NUM>) and operate according to a clock <NUM>. In addition, the inductor <NUM> couples the modem <NUM> to the PMIC <NUM>. The geometry and arrangement of the various capacitors and inductor in the chipset <NUM> may consume substantial chip area. The design of the chipset <NUM> likely includes integrating MOM/MIM/MOS capacitors with inductors and/or transformers. Unfortunately, integrating MOM/MIM/MOS capacitors with inductors and/or transformers may degrade performance of the inductors and/or transformers. Consequently, conventional arrangements for implementing multi-turn inductors continue to consume unused area in RF integrated circuit (RFIC) analog devices.

Capacitors are widely used in analog integrated circuits. <FIG> is a block diagram illustrating a cross-section of an analog integrated circuit (IC) device <NUM> including an interconnect stack <NUM>. The interconnect stack <NUM> of the IC device <NUM> includes multiple conductive interconnect layers (M1,. , M9, M10) on a semiconductor substrate (e.g., a diced silicon wafer) <NUM>. The semiconductor substrate <NUM> support a metal-oxide-metal (MOM) capacitor <NUM> and/or a metal-oxide-semiconductor (MOS). In this example, the MOM capacitor <NUM> is formed in the M3 and M4 interconnect layers, below the M5 and M6 interconnect layers. The MOM capacitor <NUM> is formed from lateral conductive fingers of different polarities using the conductive interconnect layers (M3 and M4) of the interconnect stack <NUM>. A dielectric (not shown) is provided between the conductive fingers.

In this example, the MOM capacitor <NUM> is formed within the lower conductive interconnect layers (e.g., M1 - M4) of the interconnect stack <NUM>. The lower conductive interconnect layers of the interconnect stack <NUM> have smaller interconnect widths and spaces. For example, the dimensions of the conductive interconnect layers M3 and M4 are half the size of the dimensions of the conductive interconnect layers M5 and M6. Likewise, the dimensions of the conductive interconnect layers M1 and M2 are half the size of the dimensions of the conductive interconnect layers M3 and M4. The small interconnect widths and spaces of the lower conductive interconnect layers enable the formation of MOM capacitors with increased capacitance density.

As shown in <FIG>, the MOM capacitor <NUM> makes use of a lateral (intra layer) capacitive coupling <NUM> between fingers (e.g., <NUM>, <NUM>) formed by standard metallization of the conductive interconnects (e.g., wiring lines and vias). In aspects of the present disclosure, the folded MOM capacitor may be integrated within an inductor area, as shown in <FIG>.

<FIG> is a schematic diagram illustrating a top view of a folded metal-oxide-metal (MOM) capacitor that overlaps an on-chip inductor/transformer, according to aspects of the present invention. An integrated circuit <NUM> (e.g., a radio frequency integrated circuit (RFIC)) includes an on-chip inductor/transformer that is shown as a one turn inductive trace (e.g., inductor trace) <NUM> formed in an upper back-end-of-line (BEOL) interconnect level (e.g., M5-M8). For example, the upper BEOL interconnect level may begin at a fifth BEOL interconnect level (M5). A capacitor <NUM> is fabricated in lower BEOL interconnect levels (e.g., M1-M4). For example, the lower BEOL interconnect levels may begin at a first BEOL interconnect level (M1). Although the upper and lower BEOL interconnect levels are described with reference to particular BEOL interconnect levels, it should be understood that other ranges are contemplated, according to aspects of the present disclosure.

The capacitor <NUM> may have a pair of capacitor routing terminals or manifolds <NUM> on a same side of the capacitor <NUM>. For example, the capacitor <NUM> may have four sides (e.g., a first side <NUM>, a second side <NUM>, a third side <NUM>, and a fourth side <NUM>) where the fourth side <NUM> of the capacitor <NUM> includes the pair of capacitor routing terminals <NUM>. Each of the pair of capacitor routing terminals <NUM> may be coupled to multiple folded capacitor routing traces <NUM> (or folded capacitor fingers).

The integrated circuit <NUM> includes the inductive trace <NUM> (e.g., an inductor trace or a transformer trace) that has one or more turns in at least one different BEOL interconnect level. The inductive trace <NUM> overlaps one or more portions of the capacitor <NUM>. For example, a perimeter defined by the inductive trace <NUM> of the inductor may include the multiple folded capacitor routing traces <NUM> while the inductive trace <NUM> overlaps the pair of capacitor routing terminals <NUM>. The capacitor terminals <NUM> and <NUM> (e.g., endcaps or manifolds) can be above, below or on a same layer as the inductor trace <NUM>. For example, a majority of the inductor trace <NUM> can be on a same level as the capacitor terminals <NUM> and <NUM>. A layer cross or bridge at another layer could be employed in the small overlapping area. For example, the inductor traces can change from M5 to M6, allowing the manifolds to remain on layer M5.

In one aspect of the disclosure, a first capacitor terminal <NUM> of a first polarity (e.g., positive) is coupled to a first set of folded capacitor routing traces (e.g., a first folded capacitor routing trace 405a and a second folded capacitor routing trace 405b) of the multiple folded capacitor routing traces <NUM> by one or more vias (not shown). A second capacitor terminal <NUM> of a second polarity (e.g., negative) is coupled to a second set of folded capacitor routing traces (e.g., a third folded capacitor routing trace 405c and a fourth folded capacitor routing trace 405d) of the multiple folded capacitor routing traces <NUM> by one or more vias (not shown). It should be recognized that the number of multiple folded capacitor routing traces <NUM> shown is merely exemplary, as more or fewer folded capacitor routing traces are contemplated, according to aspects of the present disclosure.

In addition to or instead of being connected with vias, the first capacitor terminal <NUM> of the first polarity (e.g., positive) is coupled to one or more folded capacitor routing traces (e.g., the first folded capacitor routing trace 405a and the second folded capacitor routing trace 405b) of the first set of folded capacitor routing traces on a first side <NUM> facing a first direction <NUM>. The second capacitor terminal <NUM> of the second polarity (e.g., negative) is coupled to one or more folded capacitor routing traces (e.g., the third folded capacitor routing trace 405c and the fourth folded capacitor routing trace 405d) of the second set of folded capacitor routing traces on a second side <NUM> facing the first direction <NUM>. For example, a third side <NUM> of the first capacitor terminal <NUM> facing a direction <NUM> is not coupled to the folded capacitor routing traces <NUM>. Similarly, a fourth side <NUM> of the second capacitor terminal <NUM> facing the direction <NUM> is not coupled to the folded capacitor routing traces <NUM>.

This arrangement of the capacitor terminals (e.g., <NUM>, <NUM>) prevents the capacitor <NUM> from negatively affecting the Q-factor of the inductor trace <NUM> by avoiding formation of a loop current (e.g., loop eddy current) within the capacitor <NUM> when the first capacitor terminal <NUM> of the first polarity (e.g., positive) and the second capacitor terminal <NUM> of the second polarity (e.g., negative) are proximate to each other on a same side (e.g., the fourth side <NUM> of the capacitor <NUM>). The formation of the loop current can also be avoided by preventing one side of each of the capacitor terminals (e.g., <NUM>, <NUM>) from contacting the folded capacitor routing traces. For example, the fourth side <NUM> of the second capacitor terminal <NUM> facing the direction <NUM> is not coupled to the folded capacitor routing traces <NUM>. Similarly, the third side <NUM> of the first capacitor terminal <NUM> facing a direction <NUM> is not coupled to the folded capacitor routing traces <NUM>.

<FIG> illustrate a top view and various cross sectional views of a folded metal-oxide-metal (MOM) capacitor <NUM>, according to aspects of the present invention. For illustrative purposes, some of the labelling and numbering of the devices and features of <FIG> are similar to those of <FIG>.

The multiple cross-sectional views include a first cross-section and second cross-section (<FIG>), a third cross-section (<FIG>), a fourth cross-section (<FIG>), a fifth cross-section and a sixth cross-section (<FIG>). For example, the first cross-section (upper portion of <FIG>) may correspond to a first cross-sectional line <NUM> in the direction <NUM> after the first capacitor terminal <NUM>. Similarly, the second cross-section (lower portion of <FIG>) illustrates an alternative implementation of the first cross-section and may also correspond to the first cross-sectional line <NUM> in the direction <NUM> after the first capacitor terminal <NUM>. The third cross-section (<FIG>) corresponds to a cross-sectional line <NUM> through the first capacitor terminal <NUM>. The fourth cross-section (<FIG>) corresponds to a cross-sectional line <NUM> through the second capacitor terminal <NUM>. The fifth cross-section (upper portion of <FIG> )may correspond to the cross-sectional line(s) <NUM> in the direction <NUM> after the second capacitor terminal <NUM>. The sixth cross-section (lower portion of <FIG>) illustrates an alternative implementation of the fifth cross-section and may also correspond to the cross-sectional line(s) <NUM> in the direction <NUM> after the second capacitor terminal <NUM>.

Each of the cross-sections illustrates multiple conductive interconnect layers (e.g., a first conductive interconnect layer Mx, a second conductive interconnect layer Mx-<NUM>, and/or a third conductive interconnect layer Mx-<NUM>). A first conductive interconnect layer for one cross section may be the same or different from a first conductive interconnect layer of a different cross section. For example, the first conductive interconnect layer Mx of the first, second, fifth, and sixth cross-sections are the same. This also applies to subsequent conductive interconnect layers (e.g., Mx-<NUM> and Mx-<NUM>) of the first, second, fifth, and sixth cross-sections. The first conductive interconnect layer Mx of the third and fourth cross-sections are the same. This also applies to subsequent conductive interconnect layers (e.g., Mx-<NUM> and Mx-<NUM>) of the third and fourth cross-sections.

The first cross-section, the second cross-section, the fifth cross-section and the sixth cross-section (<FIG>) include the first set of folded capacitor routing traces (e.g., the first folded capacitor routing trace 405a and the second folded capacitor routing trace 405b) within the first conductive interconnect layer Mx. The first cross-section, the second cross-section, the fifth cross-section and the sixth cross-section also include the second set of folded capacitor routing traces (e.g., the third folded capacitor routing trace 405c and the fourth folded capacitor routing trace 405d) within the first conductive interconnect layer Mx.

The first cross-section, the second cross-section, the fifth cross-section and the sixth cross-section (<FIG>) also include the first set of folded capacitor routing traces (e.g., a first folded capacitor routing trace 507a and a second folded capacitor routing trace 507b) within the second conductive interconnect layer Mx-<NUM>. The first cross-section, the second cross-section, the fifth cross-section and the sixth cross-section also include the second set of folded capacitor routing traces (e.g., a third folded capacitor routing trace 507c and a fourth folded capacitor routing trace 507d) within the second conductive interconnect layer Mx-<NUM>.

The first cross-section, the second cross-section, the fifth cross-section, and the sixth cross-section (<FIG>) further include the first set of folded capacitor routing traces (e.g., a first folded capacitor routing trace 509a and a second folded capacitor routing trace 509b) within the third conductive interconnect layer Mx-<NUM>. The first cross-section, the second cross-section, the fifth cross-section, and the sixth cross-section also include the second set of folded capacitor routing traces (e.g., a third folded capacitor routing trace 509c and a fourth folded capacitor routing trace 509d) within the third conductive interconnect layer Mx-<NUM>.

The third cross-section (<FIG>) includes the first capacitor terminal <NUM> of the first polarity (e.g., positive) within the first layer Mx and the fourth cross-section (<FIG>) includes the second capacitor terminal <NUM> of the second polarity (e.g., negative) within the first layer Mx. The third cross-section (<FIG>) includes the first set of folded capacitor routing traces (e.g., the first folded capacitor routing trace 405a and the second folded capacitor routing trace 405b) within the second conductive interconnect layer Mx-<NUM>. The third cross-section and the fourth cross-section include the second set of folded capacitor routing traces (e.g., the third folded capacitor routing trace 405c and the fourth folded capacitor routing trace 405d) within the second conductive interconnect layer Mx-<NUM>.

The third cross-section (<FIG>) further includes the first set of folded capacitor routing traces (e.g., the first folded capacitor routing trace 507a and the second folded capacitor routing trace 507b) within the third conductive interconnect layer Mx-<NUM>. The third cross-section and the fourth cross-section (<FIG>) include the second set of folded capacitor routing traces (e.g., the third folded capacitor routing trace 507c and the fourth folded capacitor routing trace 507d) within the third conductive interconnect layer Mx-<NUM>.

One or more vias V1, V2, and/or V3 may couple the traces and/or terminals between the various conductive interconnect layers. In some aspects, the first set of folded capacitor routing traces of the first polarity are coupled to each other by vias while the second set of folded capacitor routing traces of the second polarity are coupled to each other by vias. The first set of folded capacitor routing traces of the first polarity are coupled to the first capacitor terminal <NUM> of the first polarity by vias and also directly at the first side <NUM> in layer Mx. The second set of folded capacitor routing traces of the second polarity are coupled to the second capacitor terminal <NUM> of the second polarity by vias and also directly at the second side <NUM> in layer Mx. After a small distance in the direction of <NUM>, the layer Mx is diverted or rerouted to other layers using vias, for example, to bypass obstacles (e.g., the first capacitor terminal <NUM>) and to allow negative traces on layers Mx-<NUM> and Mx-<NUM> to pass under the first capacitor terminal <NUM>, as shown in <FIG>. The diversion or routing may be achieved using vias that couple traces from one layer to traces in another layer.

In case the manifolds extend to multiple levels (e.g., Mx and Mx-<NUM>) the multiple levels can be connected with vias. In this case, the traces at the same level as the manifold connect to the manifolds directly at that level. The via connections underneath the manifolds from the traces at lower levels are optional.

For example, the first cross-section and the fifth cross-section (<FIG> upper sections) illustrate the first folded capacitor routing trace 405a of the first conductive interconnect layer Mx is coupled to the first folded capacitor routing trace 507a of the second conductive interconnect layer Mx-<NUM> by a via V2. The first cross-section and the fifth cross-section also illustrate that the first folded capacitor routing trace 507a of the second conductive interconnect layer Mx-<NUM> is coupled to the first folded capacitor routing trace 509a of the third conductive interconnect layer Mx-<NUM> by a via V3.

Similarly, the first cross-section and the fifth cross-section illustrate that the third folded capacitor routing trace 405c of the first conductive interconnect layer Mx is coupled to the third folded capacitor routing trace 507c of the second conductive interconnect layer Mx-<NUM> by a via (e.g., via V2). The first cross-section and the fifth cross-section also illustrate that the third folded capacitor routing trace 507c of the second conductive interconnect layer Mx-<NUM> is coupled to the third folded capacitor routing trace 509c of the third conductive interconnect layer Mx-<NUM> by a via (e.g., via V3).

Alternatively, as illustrated by the second cross-section (lower portion of <FIG>) and the sixth cross-section (lower portion of <FIG>), the first folded capacitor routing trace 405a of the first conductive interconnect layer Mx, the first folded capacitor routing trace 507a of the second conductive interconnect layer Mx-<NUM> and the first folded capacitor routing trace 509a of the third conductive interconnect layer Mx-<NUM> may not be coupled to each other with vias, except when under the manifold <NUM>.

Alternatively, as illustrated by the sixth cross-section, the third folded capacitor routing trace 405c of the first conductive interconnect layer Mx, the third folded capacitor routing trace 507c of the second conductive interconnect layer Mx-<NUM> and the third folded capacitor routing trace 509c of the third conductive interconnect layer Mx-<NUM> may not be coupled to each other with vias, except when under the manifolds <NUM>, <NUM>.

The first set of folded capacitor routing traces of the first polarity are coupled to the first capacitor terminal <NUM> by vias. For example, the third cross-section (<FIG>) illustrates that the first folded capacitor routing trace 405a of the second conductive interconnect layer Mx-<NUM> and the first folded capacitor routing trace 507a of the third conductive interconnect layer Mx-<NUM> are coupled to the first capacitor terminal <NUM> of the first conductive interconnect layer Mx by vias (e.g., V1 and V2). The third folded capacitor routing trace 405c of the second conductive interconnect layer Mx-<NUM> and the third folded capacitor routing trace 507c of the third conductive interconnect layer Mx-<NUM>, however, are not coupled to the first capacitor terminal <NUM>.

The second set of folded capacitor routing traces of the second polarity are coupled to the second capacitor terminal <NUM> by vias. For example, the fourth cross-section (<FIG>) illustrates that the third folded capacitor routing trace 405c of the second conductive interconnect layer Mx-<NUM> and the third folded capacitor routing trace 507c of the third conductive interconnect layer Mx-<NUM> are coupled to the second capacitor terminal <NUM> of the first conductive interconnect layer Mx by vias (e.g., V1 and V2).

<FIG> is a process flow diagram illustrating a method <NUM> for fabricating a capacitor (e.g., metal-oxide-metal (MOM) capacitor) that overlaps an on-chip inductor/transformer, according to an aspect of the present invention. In block <NUM>, a capacitor in one or more back-end-of-line (BEOL) interconnect levels is fabricated. The capacitor includes multiple folded capacitor fingers and a pair of manifolds. The manifolds are on a same side of the folded capacitor fingers. For example, the fingers are folded into multiple sides and the manifolds are on one of those sides. Each of the pair of manifolds is coupled to one or more of the folded capacitor fingers. For example, as shown in <FIG>, one or more portions of the capacitor <NUM> is fabricated within an inductor area defined by a perimeter of an inductive trace <NUM>.

In block <NUM>, an inductive trace having one or more turns is fabricated in one or more different BEOL interconnect levels. The inductive trace overlaps one or more portions of the capacitor. As shown in <FIG>, the inductive trace <NUM> overlaps the pair of capacitor routing terminals or manifolds <NUM> of the capacitor <NUM>.

According to a further aspect of the present disclosure, an integrated circuit includes a capacitor within an inductor area defined by a perimeter of an inductive trace. In one configuration, the integrated circuit has means for storing electrical energy in a magnetic field. In one configuration, the electrical energy storing means may be the inductive trace <NUM>, as shown in <FIG>. In another aspect, the aforementioned means may be any structure or any material configured to perform the functions recited by the aforementioned means.

<FIG> is a block diagram showing an exemplary wireless communication system <NUM> in which an aspect of the present disclosure may be advantageously employed. For purposes of illustration, <FIG> shows three remote units <NUM>, <NUM>, and <NUM> and two base stations <NUM>. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units <NUM>, <NUM>, and <NUM> include IC devices 725A, 725C, and 725B that include the disclosed on-chip inductor/transformer that overlaps the capacitor having multiple capacitor fingers and the pair of manifolds. It will be recognized that other devices may also include the disclosed on-chip inductor/transformer that overlaps the capacitor having multiple capacitor fingers and the pair of manifolds, such as the base stations, switching devices, and network equipment. <FIG> shows forward link signals <NUM> from the base station <NUM> to the remote units <NUM>, <NUM>, and <NUM> and reverse link signals <NUM> from the remote units <NUM>, <NUM>, and <NUM> to base stations <NUM>.

In <FIG>, remote unit <NUM> is shown as a mobile telephone, remote unit <NUM> is shown as a portable computer, and remote unit <NUM> is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit, such as a personal data assistant, a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit, such as a meter reading equipment, or other device that stores or retrieves data or computer instructions, or combinations thereof. Although <FIG> illustrates remote units, according to the aspects of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Aspects of the present disclosure may be suitably employed in many devices, which include the disclosed on-chip inductor/transformer that overlaps the capacitor having multiple capacitor fingers and the pair of manifolds.

<FIG> is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the capacitors disclosed above. A design workstation <NUM> includes a hard disk <NUM> containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation <NUM> also includes a display <NUM> to facilitate design of a circuit <NUM> or an RF component <NUM> such as an on-chip inductor/transformer that overlaps the capacitor having multiple capacitor fingers and the pair of manifolds. A storage medium <NUM> is provided for tangibly storing the design of the circuit <NUM> or the RF component <NUM> (e.g., the on-chip inductor/transformer that overlaps the capacitor having multiple capacitor fingers and the pair of manifolds). The design of the circuit <NUM> or the RF component <NUM> may be stored on the storage medium <NUM> in a file format such as GDSII or GERBER. The storage medium <NUM> may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation <NUM> includes a drive apparatus <NUM> for accepting input from or writing output to the storage medium <NUM>.

Data recorded on the storage medium <NUM> may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium <NUM> facilitates the design of the circuit <NUM> or the RF component <NUM> by decreasing the number of processes for designing semiconductor wafers.

For a firmware and/or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. A machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein. For example, software codes may be stored in a memory and executed by a processor unit. Memory may be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" refers to types of long term, short term, volatile, nonvolatile, or other memory and is not to be limited to a particular type of memory or number of memories, or type of media upon which memory is stored.

If implemented in firmware and/or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be an available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

In addition to storage on computer readable medium, instructions and/or data may be provided as signals on transmission media included in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the technology of the present disclosure as defined by the appended claims. For example, relational terms, such as "above" and "below" are used with respect to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. Additionally, if oriented sideways, above and below may refer to sides of a substrate or electronic device. Moreover, the scope of the present application is not intended to be limited to the particular configurations of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding configurations described herein may be utilized, according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the present disclosure herein may be implemented as electronic hardware, computer software, or combinations of both.

The various illustrative logical blocks, modules, and circuits described in connection with the present disclosure herein may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store specified program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. In addition, any connection is properly termed a computer-readable medium.

Claim 1:
An integrated circuit (<NUM>), comprising:
a capacitor (<NUM>) in at least one back-end-of-line, BEOL, interconnect level, the capacitor (<NUM>) having a plurality of folded capacitor conductor traces (<NUM>) having multiple sides (<NUM>, <NUM>, <NUM>, <NUM>) and a pair of terminals (<NUM>) on a same side (<NUM>) of the multiple sides of the folded capacitor conductor traces (<NUM>), each of the pair of terminals (<NUM>) coupled to at least one of the plurality of folded capacitor conductor traces (<NUM>); and
an inductive trace (<NUM>) having at least one turn in at least one different BEOL interconnect level, wherein a perimeter defined by the inductive trace (<NUM>) includes the plurality of folded capacitor conductor traces (<NUM>) and the inductive trace (<NUM>) overlaps the pair of terminals (<NUM>).