Patent Description:
Bluetooth (BT) is based on phase modulation, e. on Gaussian Frequency Shift Keying (GFSK) for basic rate (BR) or on Differential Phase Shift Keying (DPSK) for enhanced data rate (EDR). The BT standard may permit large variations within a modulation of a packet that may result in an increased time consumption for further processing (e.g. performing a specific test) of the packet performed by a BT receiver. Thus, a BT receiver with improved packet processing capabilities may be desired.

<CIT> discloses a front-end system for a radio device. The front-end system comprises a converter, the converter comprising a mixer configured for down-converting a radio frequency signal into a baseband signal by using a local oscillator signal generated by a signal generator. The converter further comprises a quantizer arranged for quantizing the baseband signal into a digital signal. Further, the signal generator may be configured for generating, based on the digital signal, the local oscillator signal such that it is synchronized with the radio frequency signal.

<CIT> discloses a radio receiver. The receiver substitutes a phase offset compensator with a simple and cost-effective structure for the conventional carrier recovery unit which is relatively complex and expensive, so as to decrease the complexity of the receiver and to provide cost savings. The digital radio receiver includes means arranged to filter and timing recover a received signal to produce timing corrected symbols, means arranged to differentially detect the timing corrected symbols, means arranged to compensate a phase offset of the detected symbol and decoding means arranged to decode the phase offset compensated symbols into a bit stream.

<CIT> discloses a receiving apparatus for a mobile communications system which can be modulated using different modulation types at the transmitter end. In the middle of a data burst of a Bluetooth communications system, a GFSK modulation method is switched to an M-DPSK modulation method, which is used for the payload data. A frequency offset estimation unit is provided for GFSK-modulated signals in a first receiving section and estimates the frequency offset by averaging over a bit sequence of a trailer of a data burst. The frequency offset is corrected in a second receiving section, by means of a frequency correction unit which operates on the basis of the CORDIC algorithm.

<CIT> discloses a BLE device, having a demodulator configured to translate in-phase and quadrature components of a received BLE signal into a differential phase, an estimator configured to estimate a frequency offset of the differential phase signal and a detector configured to detect information in the differential phase signal corrected by the estimated frequency offset.

Accordingly, while further examples are capable of various modifications and alternative forms, some particular examples thereof are shown in the figures and will subsequently be described in detail. Like numbers refer to like or similar elements throughout the description of the figures, which may be implemented identically or in modified form when compared to one another while providing for the same or a similar functionality.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the elements may be directly connected or coupled or via one or more intervening elements. If two elements A and B are combined using an "or", this is to be understood to disclose all possible combinations, i.e. only A, only B as well as A and B. An alternative wording for the same combinations is "at least one of the group A and B". The same applies for combinations of more than <NUM> Elements.

Whenever a singular form such as ''a,'' "an" and "the" is used and using only a single element is neither explicitly or implicitly defined as being mandatory, further examples may also use plural elements to implement the same functionality.

<FIG> shows a block schema of an example of a BT receiver <NUM>. The BT receiver <NUM> comprises processing circuitry <NUM> configured to receive a receive signal and to determine receive symbols based on the receive signal. Further, the BT receiver <NUM> comprises control circuitry <NUM> configured to determine a frequency offset and/or a modulation index of the receive signal based on the receive signal. Further, the control circuitry <NUM> is configured to control an operation mode of the processing circuitry <NUM> based on the determined frequency offset and/or the modulation index of the receive signal. For example, the control circuitry <NUM> may be adapted to adaptive/on-the-fly control the operation mode of the processing circuitry <NUM>. Adjusting the operation mode of the processing circuitry <NUM> based on at least one of the determined frequency offset and the modulation index of the receive signal may allow to adapt the signal processing within the processing circuitry <NUM> to the condition/state of the receive signal. Accordingly, processing of the receive signal by the processing circuitry <NUM> may be improved. For example, by determining the frequency offset a tracking loop, e.g. a frequency tracking loop, may be advantageously adapted to the determined frequency offset. By determining the frequency offset the frequency tracking loop of the BT receiver <NUM> may be improved by adapting a parameter for the frequency tracking loop. For example, a frequency tracking loop may be adapted for a dirty signal (e.g. BGB test) or for a clean signal (e.g. desired operation mode). By determining the modulation index the phase tracking loop of the BT receiver <NUM> may be improved by adapting a parameter for the phase tracking loop. Thus, the performance of the BT receiver <NUM> may be improved by adapting the operation mode of the BT receiver based on at least one of the frequency offset and the modulation index.

The receive signal may be a signal transmitted from a BT transmitter. Thus, the receive signal may be a modulated signal according to the BT standard, e.g. modulated by GFSK or DPSK. For example, the processing circuitry <NUM> may be configured to demodulate the receive signal.

The processing circuitry <NUM> may comprise a frequency estimator configured to estimate a frequency of the receive signal. For example, the frequency estimator may estimate for every symbol a frequency. An estimated frequency determined by the frequency estimator may be send to the control circuitry <NUM>.

The control circuitry <NUM> may comprise a phase lock detector circuitry configured to determine the frequency offset of the receive signal based on a frequency of the receive signal. For example, the determination may be based on the estimated frequency. The frequency offset may be determined by comparison of the estimated frequency of two symbols, e.g. by a difference of the frequencies of these symbols.

The phase lock detector circuitry may be further configured to determine the frequency offset of the receive signal based on a maximum frequency and a minimum frequency of the receive signal. For example, the phase lock detector circuitry may determine the frequency offset based on the maximum frequency value of all symbols and on the minimum frequency value of all symbols, e.g. by subtraction of these both values.

The phase lock detector circuitry may be further configured to determine the frequency offset of the receive signal based on a frequency drift of the receive signal over time. The phase lock detector circuitry may operate in three different operation modes for determining the frequency offset over time. The operation modes may differ by a number of symbols used for determining the frequency offset. For example, the phase lock detector circuitry may use <NUM>, <NUM> or <NUM> symbols, for determining the frequency offset. Thus, the phase lock detector circuitry may determine the frequency offset over different time periods, e.g. over a time period of <NUM> symbols. The frequency offset may be determined by subtracting the minimum frequency value of all symbols from the maximum frequency value of all symbols for a given period. Hence, a likelihood for an increased frequency offset may increase with the number of symbols used for the time period. For example, a higher frequency offset may be more probable for a period comprising <NUM> symbols than for a period comprising <NUM> symbols.

The phase lock detector circuitry may be further configured to compare the frequency offset with a threshold and if the frequency offset is larger than the threshold, send the determined frequency offset to the processing circuitry <NUM>. Thus, a use of the threshold may increase a sensitivity for sending the frequency offset to the processing circuitry <NUM>. For example, the threshold may depend on the time period used for determining the frequency offset, e.g. the threshold may be larger for a time period with more symbols as for a time period with less symbols.

The phase lock detector circuitry may estimate the transmitter frequency drift by determining the frequency offset. Thus, by determining the frequency offset a performance of the BT receiver <NUM> may be improved by improving a frequency tracking loop, e.g. by adapting a parameter of the frequency tracking loop. To adapt the parameter of the frequency tracking loop the phase lock detector circuitry may send information, e.g. about the frequency offset, to the control circuitry <NUM>, e.g. to a differential demodulator circuitry and/or a phase tracker circuitry, and their operation mode may be changed accordingly. The phase lock detector circuitry may be used to improve the performance of a BT receiver <NUM> for receiving the receive signal which may be modulated based on GFSK or DPSK.

The control circuitry <NUM> may comprise a modulation index tracker circuitry configured to determine the modulation index of the receive signal. When the modulation index may be unknown, the BT receiver <NUM> may have to go through an adaptation period to search for the modulation index. By determining the modulation index this adaption period may be omitted and thus the phase tracking loop may be adapted to the determined modulation index. This may improve the BT receiver <NUM> performance, e.g. by decreasing a time consumption of the phase tracking loop.

To overcome the issue with the adaption period an initial modulation error η based on Access Code may be applied. The modulation index tracker circuitry may be further configured to determine the modulation index based on a modulation error of the receive signal.

Further, to reduce an η estimation error a supplement η track may be used in a demodulator (e.g. the differential demodulator circuitry). The modulation index tracker circuitry may be further configured to determine the modulation index based on a phase error of the received signal. The modulation error may be translated to a phase error (residual error) which may be data depending. The modulation index tracker circuitry may be further configured to determine the phase error of the received signal based on the modulation error of the received signal. The η track may apply an offset to η proportional to a deviation of the estimated phase error from its average. The modulation index tracker circuitry may be further configured to determine the modulation index based on an averaging factor.

For η track with an applied offset proportional to the phase error for a GFSK signal, a next transmitter phasor may be <MAT> with bs,t [n] ∈ {-<NUM>; <NUM>}, bit transition from source state (index "s") to target state (index "t").

Assuming a modulation index error ηer may lead to <MAT> <MAT> where <MAT>.

The phase error due to ηer may be <MAT> where other sources for the phase error e. carrier frequency offset (CFO), phase noise (PN) were neglected.

To compensate for other phase error sources, average ωt, <MAT> may be subtracted: <MAT>.

Applying an averaging factor α leads to an estimator of the modulation index: <MAT>.

The estimator of the modulation index may be stored in Look up Tables (LUTs). For example, in the LUTs may be stored πη, the real part of the estimator of the modulation index hReal and the imaginary par of the estimator of the modulation index hImag in LUTs for each modulation index (e.g. for BR: η range from <NUM> to <NUM> with increments of <NUM>; for BLE: η range from <NUM> to <NUM> with increments of <NUM>). By storing the estimator of the modulation index in LUTs an access and/or use of the estimator of the modulation index may be facilitated.

The processing circuitry <NUM> may comprise differential demodulator circuitry configured to generate a demodulated receive signal by demodulating the receive signal and the control circuitry <NUM> may be configured to adjust an operation mode of the differential demodulator circuitry based on the determined frequency offset and/or the modulation index. The differential demodulator circuitry may be a circuitry with different operation modes, thus the operation mode of the differential demodulator circuitry may be adjustable, e.g. by the controlling circuitry. The different operation modes may be optimized for different frequency offsets. The differential demodulator circuitry may observe a number of previous symbols L to determine a current operation mode. With an increasing number of previous symbols L the SNR may increase, especially for the clean signal. The differential demodulator circuitry may be configured to demodulate the receive signal using a multi-symbol-differential (MSD) algorithm mode and a number of differential phases used by the multi-symbol-differential algorithm for demodulating the receive signal may depend on the operation mode adjusted by the control circuitry <NUM>. Several different phases may be calculated for the MSD algorithm as follows <MAT> where θ is the received phase, φ̂k is the estimated differential phase and L is the number of previous symbols. L may be any number of desired previous symbols, e.g. <NUM>, <NUM> or <NUM>.

The current differential phase may be extracted by averaging the terms to <MAT>.

This may average the noise resulting in an increase of the performance of the differential demodulator circuity with growing L. For example, the performance of the differential demodulator may tend to optimality with growing L.

However, the frequency offset may depend on L too. An error caused by the frequency offset may be given by <MAT>.

Thus, the error caused by the frequency offset may also grow with L. Therefore, the achievable SNR may depend on the frequency offset of the receive signal. For example, for the clean signal (e.g. small frequency drift) the operation mode of the differential demodulator circuitry may be chosen to L = <NUM>, resulting in the improved SNR. Alternatively, for the dirty signal (e.g. large frequency drift) the operation mode of the differential demodulator circuitry may be chosen to L=<NUM>, resulting in the improved SNR. Thus, the SNR may crucially depend on the operation mode of the differential demodulator circuitry and the frequency offset. With the determined frequency offset and/or the modulation index the operation mode of the differential demodulator circuitry may be adjusted, which may improve the performance of the BT receiver <NUM>. The differential demodulator circuitry may change the operation mode dynamically based on the information of the frequency offset from the phase lock detector circuitry.

The processing circuitry <NUM> may comprise demapper circuitry configured to determine the receive symbols and a phase error of the receive signal based on the demodulated receive signal. Further, the processing circuitry <NUM> may comprise phase tracker circuitry configured to determine a phase correction signal for the demodulated receive signal based on the phase error of the receive signal. Further the control circuitry <NUM> may be configured to adjust an operation mode of the phase tracker based on the determined frequency offset.

The BT receiver <NUM> may further comprise a signal combiner circuitry coupled between the differential demodulator circuitry and the demapper circuitry, wherein the signal combiner circuitry is configured to combine the demodulated receive signal with the phase correction signal.

The phase tracker circuitry may be a circuitry with different operation modes, thus the operation mode of the phase lock track circuitry may be adjustable, e.g. by the controlling circuitry. The different operation modes may be optimized for different frequency drifts. For example, the phase tracker circuitry may perform a tracking loop, e.g. a second order tracking loop. The tracking loop may depend on tracking parameters, e.g. an integral gain (also referred to as k-proportional, KP) and/or an integral proportional gain (also referred to as k-integrated proportional, KIP). KP and KIP may determine a speed of the tracking loop. For small tracking loop speed the SNR may be increased, because due to the slow tracking loop speed the noise may be averaged, but the small tracking loop speed may be not sensitive for the frequency drift. For high tracking loop speed the SNR may be decreased, because the high tracking loop speed may add noise to the signal, but therefore it may be sensitive for the frequency drift. The control circuitry <NUM> is configured to adjust the operation mode of the phase tracker circuitry by adjusting at least one of an integral gain and an integral proportional gain of the phase tracker circuitry based on the determined frequency offset. The integral gain and the integral proportional gain may be dynamically changed by the control circuitry <NUM>. For example, the operation mode of the phase tracker circuitry may be chosen based e.g. on the frequency drift determined by the phase lock detector.

An electronic device <NUM> may comprise a BT receiver <NUM> as described above. The electronic device <NUM> may be a mobile device such as, e.g., a mobile phone, a smart phone, a tablet-computer or a laptop-computer.

More details and aspects are mentioned in connection with the examples described below. The example shown in <FIG> may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described below (e.g. <FIG>).

<FIG> shows a block diagram of a flow chart of an example of a method <NUM> for improving a performance of a BT receiver. The method <NUM> for improving the performance of the BT receiver comprises receiving <NUM> a receive signal, determining <NUM> receive symbols based on the receive signal and determining <NUM> a frequency offset and/or a modulation index of the receive signal based on the receive signal. Further the method comprises controlling <NUM> an operation mode of a processing circuitry based on the determined frequency offset and/or the modulation index of the receive signal.

More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in <FIG> may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above (e.g. <FIG>) and/or below (e.g. <FIG>).

<FIG> shows a block schema of an example of a BT receiver <NUM>. The BT receiver <NUM> comprises a differential demodulator circuitry <NUM>, a demapper circuitry <NUM>, a phase tracker circuitry <NUM> and a phase lock detector circuitry <NUM>. The BT receiver <NUM> may comprises further circuitry - conventional or custom.

The differential demodulator circuitry <NUM> be configured to demodulate a received receive signal. The demodulated receive signal may be send from the demodulator circuitry <NUM> to the demapper circuitry <NUM>. The demapper circuitry <NUM> may be configured to determine receive symbols and a phase error of the demodulated receive signal. The phase error determined by the demapper circuitry <NUM> may be send to the phase tracker circuitry <NUM>. The phase tracker circuitry <NUM> may perform a tracking loop on the demodulated received signal to determine a phase correction, e.g. a frequency offset or a frequency drift. A differential phase as seen by the phase tracker circuitry may represent the frequency offset. The phase correction may be sent to the phase lock detector circuitry <NUM>. The phase lock detector circuitry <NUM> may determine a variation of the frequency offset over time, e.g. the frequency drift. Information belonging the variation of the frequency offset may be sent to the differential demodulator circuitry <NUM> and the phase tracker circuitry <NUM> and may be used to adjust an operation mode of each. Thus, a performance of the BT receiver may be improved.

The processing circuitry may comprise the demodulator circuitry <NUM>, the demapper circuitry <NUM> and the phase tracker circuitry <NUM>. For example, the demodulator circuitry <NUM>, the demapper circuitry <NUM> and the phase tracker circuitry <NUM> may be sub-circuitry of the processing circuitry. The control circuitry may comprise the phase lock detector circuitry <NUM>. For example, the phase lock detector circuitry may be sub-circuitry of the control circuitry.

<FIG> shows a flow-chart of an example of an operation of a phase tracker circuitry. The phase tracker circuitry may determine a phase correction based on a phase error. The determination of the phase correction may be performed by a first tracking loop. For the first tracking loop predefined values of the tracking parameters KP and KIP may be utilized. For example, the phase tracker circuitry may operate in an acquisition mode, where the tracking parameters may be reduced, until they may reach a specific predefined value. The first tracking loop may comprise all action related to the numbers <NUM> - <NUM>. The numbers <NUM> - <NUM> may illustrates action.

After receiving information about a frequency drift from the phase lock detector circuitry (see number <NUM> and <NUM>) a second tracking loop may be performed. For the second tracking loop the values for KP and/or KIP may be dynamically changed (compare numbers <NUM> - <NUM>), e.g. based on the determined frequency drift. For example, the operation mode of the phase tracker circuitry may be adapted by dynamically changing the values of KP and/or KIP. The second tracking loop may comprise all actions related to the numbers <NUM> - <NUM>. Note "reg" and "cnt" may be desired regulator and counter values.

More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in <FIG> may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above (e.g. <FIG> and/or below (e.g. <FIG>).

<FIG> shows an example of a determination of a k-integrated proportional parameter. The KIP is determined for a signal with stable frequency <NUM> (e.g. a clean signal) and for a BQB signal with large frequency drift <NUM> as defined by standard qualification test (e.g. a dirty signal). For the clean signal <NUM> the KIP may be adjusted to a value of <NUM> by the (adaptive) phase tracker circuitry. For the dirty signal <NUM> the KIP may be adjusted to a value of <NUM> by the (adaptive) phase tracker circuitry. Thus, an operation mode of the (adaptive) phase tracker circuitry may be improved by the dynamical change of the KIP parameter.

<FIG> shows a flow-chart of an example of a determination of a frequency offset by a phase lock detector circuitry. The phase lock detector circuitry may determine a frequency offset, e.g. the frequency offset over time (frequency drift), based on a phase correction send by a phase tracker circuitry. The phase lock detector circuitry may determine a minimum (min_val) and a maximum frequency value (Max_val) based on the phase correction (numbers <NUM> - <NUM>). The min_val and the Max_val may be used to determine the frequency offset and to generate an output signal comprising information about the frequency offset (numbers <NUM> - <NUM>). The output signal may be sent to the phase tracker circuitry and a differential demodulator circuitry to adjust an operation mode of these circuitries. The min_val and the Max_val may be determined for a predefined time period, e.g. for <NUM> symbols of a receive signal. After determination of the min_val and the Max_val for a first time period, these values may be reset (number <NUM> and <NUM>) and may be determined for a second time period, analog to the determination for the first time period. Further, a counter may be updated after each time period (number <NUM>).

<FIG> shows a flow-chart of an example of a determination of a modulation index by a modulation index tracker circuitry. The mathematic formalism behind the modulation index tracker circuitry is described above.

<FIG> shows a performance of an example of a BT receiver for different signals. The BT receiver is an adaptive BT receiver as described above, with a differential demodulator circuitry and a phase tracker circuitry, each with different operation modes. In <FIG> is the performance shown for an EDR-<NUM> clean signal <NUM>, EDR-<NUM> BQB signal (ppm = <NUM>; parts per million) and EDR-<NUM> BQB (ppm =<NUM>). In comparison to a non-adaptive BT receiver with a single operation mode the adaptive BT receiver shows an increased performance (see Tab.

For the clean signal, an improvement of <NUM>. 4dB may be achieved by larger L value in the differential demodulator circuitry (<NUM> instead of <NUM>) and optimized tracking parameters for slow tracking. Better performance may also be reported for BQB signal as the tracking parameters of a tracking loop may be changed to match fast tracking. It may also be seen that for the non-adaptive receiver there may be only <NUM>. 4dB difference between the clean and BQB test, where the adaptive receiver has <NUM>. 4dB difference. Thus, the adaptive BT receiver may have improved performance in comparison to the non-adaptive BT receiver.

<FIG> shows a bit error rate (BER) as a function of the signal to noise ratio of an example of a BT receiver. The BER decreases for a BT BR signal for an adaptive BT receiver by adjusting parameters of a tracking loop.

<FIG> shows a block diagram of an example of a wireless communication device <NUM>. In accordance with various examples, wireless communication device <NUM> may include, among other things, a transmit/receive element <NUM> (for example an antenna), a transceiver <NUM>, physical (PHY) circuitry <NUM>, and media access control (MAC) circuitry <NUM>. The PHY circuitry <NUM> and MAC circuitry <NUM> may be compliant with one or more wireless standards such as IEEE <NUM> standards and/or BT™ (Low Energy). The PHY circuitry <NUM> may include circuitry for modulation/demodulation, upconversion/downconversion, filtering, amplification, etc. In some examples, the transmit/receive elements <NUM> may be two or more antennas that may be coupled to the PHY circuitry <NUM> and arranged for sending and receiving signals.

Wireless communication device <NUM> may also include processing circuitry <NUM> and memory <NUM> configured to perform the various operations described herein. The circuitry <NUM> may be configured to perform functions based on instructions being stored in a RAM or ROM, or based on special purpose circuitry. The circuitry <NUM> may include one or more processors, such as a general-purpose processor or special purpose processor, and/or processing circuitry in accordance with some examples. The circuitry <NUM> may implement one or more functions associated with the transceiver <NUM>, the PHY circuitry <NUM>, the MAC circuitry <NUM>, and/or the memory <NUM>. The circuitry <NUM> may be coupled to the transceiver <NUM>, which may be coupled to the transmit/receive element <NUM>. While <FIG> depicts the circuitry <NUM> and the transceiver <NUM> as separate components, the circuitry <NUM> and the transceiver <NUM> may be integrated together in an electronic package or chip.

In some examples, a wireless communication device <NUM> may be part of a portable wireless communication device, such as a personal digital assistant (PDA), a laptop or portable computer with wireless communication capability, a web tablet, a wireless telephone, a smartphone, a wireless headset, a pager, an instant messaging device, a digital camera, an access point, a television, a medical device (e.g., a heart rate monitor, a blood pressure monitor, etc.), an access point, a base station, a transmit/receive device for a wireless standard such as BT or IEEE <NUM>, or other device that may receive and/or transmit information wirelessly. In some examples, the wireless communication device may include one or more of a keyboard, a display, anon-volatile memory port, multiple antennas, a graphics processor, an application processor, speakers, and other mobile device elements. The display may be an LCD screen including a touch screen.

Although the Wireless communication device <NUM> is illustrated as having several separate functional elements, one or more of the functional elements may be combined and may be implemented by combinations of software-configured elements, such as processing elements including digital signal processors (DSPs), and/or other hardware elements. For example, some elements may comprise one or more microprocessors, DSPs, field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), radio-frequency integrated circuits (RFICs) and combinations of various hardware and logic circuitry for performing at least the functions described herein. In some examples, the functional elements may refer to one or more processes operating on one or more processing elements.

Some examples may be implemented fully or partially in software and/or firmware. This software and/or firmware may take the form of instructions contained in or on a non-transitory computer-readable storage medium. Those instructions may then be read and executed by one or more processors to enable performance of the operations described herein. Those instructions may then be read and executed by one or more processors to cause the device <NUM> to perform the methods and/or operations described herein. The instructions may be in any suitable form, such as but not limited to source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. Such a computer-readable medium may include any tangible non-transitory medium for storing information in a form readable by one or more computers, such as but not limited to read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; a flash memory, etc..

More details and aspects are mentioned in connection with the examples described above. The example shown in <FIG> may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above (e.g. <FIG>).

Furthermore, in further examples, a single step, function, process or operation may include and/or be broken up into several sub-steps, - functions, -processes or -operations.

Claim 1:
A Bluetooth receiver (<NUM>; <NUM>), comprising:
processing circuitry (<NUM>) configured to receive a receive signal and to determine receive symbols based on the receive signal; and
control circuitry (<NUM>) configured to determine a frequency offset and a modulation index related to a frequency of the receive signal based on the receive signal, and to control an operation mode of the processing circuitry (<NUM>) based on the determined frequency offset and the modulation index of the receive signal, wherein
the control circuitry (<NUM>) comprises:
phase lock detector circuitry (<NUM>) configured to determine the frequency offset of the receive signal based on a frequency of the receive signal; and
modulation index tracker circuitry configured to determine the modulation index of the receive signal.