Patent Description:
An event counter is a device that can be used for multiple applications. An event counter can be, for example, frequency counters that count signal cycles. As another example, the event counter can be a radiation counter that counts particle impacts. In yet another example, the event counter can be a full-time counter that detects atomic events.

In counting events, conditioning of the events may be performed to place the events into a form that can be counted by the event counter. The conditioning of the events can include amplification, filtering, digitizing, or other types of conditioning depending on the type of event counter being used. The conditioning can also include converting mechanical energy to electrical energy or atomic excitation to photon detections using a transducer.

Events may occur at a substantially even rate. In other cases, burst of events may occur. Regardless of the rate at which the events occur, an event counter should be able to handle these different frequencies and which events can occur. As the rate at which events occur, counting these events may become more challenging. In some cases, the rate of events may increase to a level that cannot be counted by an event counter.

Document by <NPL>, according to its abstract, states a rough counting algorithm using Deutsch-Jozsa's algorithm to roughly estimate the number of items satisfying some search conditionsb by reconstructing the output distribution.

For example, it would be desirable to have a method and apparatus that overcome a technical problem with counting events as the rate of the events increases.

The presently claimed invention is set out in the appended set of claims. On a more general level, an embodiment of the present disclosure provides an event counting system comprising a computer system and a quantum processor in the computer system. The quantum processor is configured to reset a set of quantum registers. The quantum processor is configured to apply a Hadamard operator to the set of quantum registers. The quantum processor is configured to execute a quantum instruction on the set of quantum registers. The quantum instruction incorporates a function for an event vector comprising events identified by bits. The quantum processor is configured to apply the Hadamard operator to the set of quantum registers after executing the quantum instruction. The quantum processor is configured to measure the set of quantum registers to form a measurement of the set of quantum registers. The quantum processor is configured to determine an approximate count of the events using the measurement of the set of quantum registers.

Another embodiment of the present disclosure provides an event counting system comprising a computer system, a first set of quantum registers in the computer system, a second set of quantum registers in the computer system, and a quantum processor in the computer system. The quantum processor is configured to reset the first set of quantum registers and the second set of quantum registers. The quantum processor is configured to apply a Hadamard operator to the first set of quantum registers and the second set of quantum registers. The quantum processor is configured to execute a quantum instruction on the set of quantum registers. The quantum instruction incorporates a function for an event vector comprising events identified by bits in the event vector. The quantum processor is configured to execute a complementary quantum instruction on the second set of quantum registers. The complementary quantum instruction incorporates a complementary function that is complementary to the function for the event vector comprising the events identified by the bits in the event vector. The quantum processor is configured to apply the Hadamard operator to the first set of quantum registers after executing the quantum instruction. The quantum processor is configured to apply the Hadamard operator to the second set of quantum registers after executing the complementary quantum instruction. The quantum processor is configured to measure the first set of quantum registers and the second set of quantum registers to form a measurement of the first set of quantum registers and the second set of quantum registers. The quantum processor is configured to determine an approximate count of the events using the measurement.

Still another embodiment of the present disclosure provides a method for counting events. A set of quantum registers is reset. A Hadamard operator is applied to the set of quantum registers. A quantum instruction is executed on the set of quantum registers, wherein the quantum instruction incorporates a function for an event vector comprising events identified by bits. The Hadamard operator is applied to the set of quantum registers after executing the quantum instruction. The set of quantum registers is measured to form a measurement of the set of quantum registers. An approximate count of the events is determined using the measurement of the set of quantum registers.

The illustrative embodiments recognize and take into account one or more different considerations. For example, the illustrative embodiments recognize and take into account that events occurring at frequencies greater than <NUM> gigahertz can be challenging to count by currently available event counters. The illustrative embodiments recognize and take into account that with sequentially recurring events, proper accounting of these events involves using an event counter that operates as fast as the shortest time between these events. The illustrative embodiments recognize and take into account that currently available digital event counters currently cannot run faster than about <NUM>.

Thus, the illustrative examples provide a method, apparatus, and system for counting events at a faster rate than possible with current event counters. For example, an event counter can implement quantum techniques to produce approximate event counts at a rate that is much faster as compared to current event counters.

In one illustrative example, a computer system can include a quantum processor. This quantum processor can comprise a quantum arithmetic logic unit (QALU). In one illustrative example, the quantum arithmetic logic unit can include a set of quantum registers and a quantum logic. The quantum logic can implement any number of independent unitary instructions that can be processed in parallel for the set of quantum registers. In other words, the quantum logic can process unitary instructions in one or more quantum registers in the set of quantum registers in parallel.

As used herein, a "set of" when used with reference to items, means one or more items. For example, a "set of quantum registers" is one or more quantum registers.

The illustrative examples provide a method, apparatus, and system for counting events. In one illustrative example, a set of quantum registers is reset. A Hadamard operator is applied to the set of quantum registers. A quantum instruction is executed on the set of quantum registers, wherein the quantum instruction incorporates a function for an event vector comprising events identified by bits. The Hadamard operator is applied to the set of quantum registers after executing the quantum instruction. The set of quantum registers is measured to form a measurement of the set of quantum registers. An approximate count of the events is determined using the measurement of the set of quantum registers.

With reference now to the figures and, in particular, with reference to <FIG>, an illustration of a block diagram of an event counting environment is depicted in accordance with an illustrative embodiment. As depicted, event counting environment <NUM> is an environment in which events <NUM> can be generated by a set of event detectors <NUM>. The set of event detectors <NUM> can be hardware, software, or a combination of the two. In this example, the set of event detectors <NUM> can be selected from at least one of a sensor, an event detector, a simulator detector, a virus scanner, a network scanner, a biosensor, an image sensor, a seismometer, or some other source that can generate events <NUM>.

As used herein, the phrase "at least one of," when used with a list of items, means different combinations of one or more of the listed items can be used, and only one of each item in the list may be needed. In other words, "at least one of" means any combination of items and number of items may be used from the list, but not all of the items in the list are required. The item can be a particular object, a thing, or a category.

Event counting system <NUM> can count events <NUM> generated by the set of event detectors <NUM> to create count <NUM> of events <NUM>. In this illustrative example, count <NUM> is approximate count <NUM> of events <NUM>.

As depicted, events <NUM> are encoded into event vectors <NUM> for processing. In this illustrative example, event vector <NUM> in event vectors <NUM> comprises bits <NUM> with length <NUM>. Event vector <NUM> can also be referred to as "E" in these examples. Length <NUM> indicates the number of bits <NUM> and can also be referred to as "n" in these illustrative examples with event vector being referred to as E(n).

In this illustrative example, event counting system <NUM> comprises a number of different components. As depicted, event counting system <NUM> includes computer system <NUM> and quantum processor <NUM>. In this illustrative example, quantum processor <NUM> is located in computer system <NUM>.

Quantum processor <NUM> can be implemented in software, hardware, firmware, or a combination thereof. When software is used, the operations performed by quantum processor <NUM> can be implemented in program code configured to run on hardware, such as a processor unit. When firmware is used, the operations performed by quantum processor <NUM> can be implemented in program code and data and stored in persistent memory to run on a processor unit. When hardware is employed, the hardware can include circuits that operate to perform the operations in quantum processor <NUM>.

In the illustrative examples, the hardware can take a form selected from at least one of a circuit system, an integrated circuit, an application specific integrated circuit (ASIC), a programmable logic device, or some other suitable type of hardware configured to perform a number of operations. With a programmable logic device, the device can be configured to perform the number of operations. The device can be reconfigured at a later time or can be permanently configured to perform the number of operations. Programmable logic devices include, for example, a programmable logic array, a programmable array logic, a field programmable logic array, a field programmable gate array, and other suitable hardware devices. Additionally, the processes can be implemented in organic components integrated with inorganic components and can be comprised entirely of organic components excluding a human being. For example, the processes can be implemented as circuits in organic semiconductors.

Computer system <NUM> is a physical hardware system and includes one or more data processing systems. When more than one data processing system is present in computer system <NUM>, those data processing systems are in communication with each other using a communications medium. The communications medium can be a network. The data processing systems can be selected from at least one of a computer, a server computer, a tablet computer, or some other suitable data processing system.

As depicted, when hardware or hardware and software are used for quantum processor <NUM>, the components in quantum processor <NUM> can be implemented using semiconductors may include quantum-based components such as quantum bits, quantum registers, quantum gates, and other components. Further, these quantum components used for quantum processor <NUM> can be a model running in computer system <NUM>. Quantum processor <NUM> can perform quantum processes and can also perform non-quantum processes.

As depicted, quantum processor <NUM> is configured to configured perform a number of different operations that may include both quantum and non-quantum operations to determine approximate count <NUM> for events <NUM> in event vector <NUM>.

In the illustrative example, quantum processor <NUM> can reset set <NUM> of quantum registers <NUM> in computer system <NUM>. A quantum register can be comprised of qubits. A qubit can also be referred to as a quantum bit. Qubits can be a two-state or two-level quantum mechanical system. For example, qubits may have electrons at two levels that can be spin up and spin down. As another example, a polarization of a photon at two states can also be used in which a vertical polarization in a horizontal polarization is present. In this illustrative example, quantum mechanics enables a qubit to be in a coherent super position of both states simultaneously. A quantum register enables the performance of calculations through the manipulation of qubits in the quantum register.

As depicted, quantum processor <NUM> can apply Hadamard operator <NUM> to set <NUM> of quantum registers <NUM>. Quantum processor <NUM> can execute quantum instruction <NUM> on set <NUM> of quantum registers <NUM>. In executing quantum instruction <NUM>, function <NUM> can be applied to the contents of each quantum register in set <NUM> of quantum registers <NUM>.

In this illustrative example, function <NUM> can be a function performed on set <NUM> of quantum registers <NUM> and can be based on the content of event vector <NUM>. In other words, function <NUM> performed on set <NUM> of quantum registers <NUM> can be based on the values for bits <NUM> in event vector <NUM>. As a result, function <NUM> can be different for each event vector in event vectors <NUM> when the dates in event vectors <NUM> are different from each other.

Function <NUM> is applied to perform a logic AND of first set of bits, qubits <NUM>, in quantum register <NUM> in set <NUM> of quantum registers <NUM> that corresponds to a second set of bits, bits <NUM>, in event vector <NUM> that indicate a presence of an event. Function <NUM> is as follows: <MAT> wherein Ei is an ith bit in event vector <NUM>, n is a number of bits <NUM> in the event vector <NUM>, Xi is the ith bit in quantum register <NUM>, and i is an index value.

In this illustrative example, quantum instruction <NUM> incorporates function <NUM> for event vector <NUM> comprising events <NUM> identified by bits <NUM>. Quantum instruction <NUM> can comprise function <NUM> encoded in unitary operator <NUM> that can be executed by quantum processor <NUM>.

Unitary operator <NUM> is an instruction that can be used in a quantum computer. In other words, function <NUM> can be incorporated into quantum instruction <NUM> enabling function <NUM> to be performed by quantum processor <NUM> when quantum instruction <NUM> is executed.

In this illustrative example, unitary operator <NUM> is a surjective bounded operator on a Hilbert space preserving the inner product. For example, unitary operator <NUM> can be a bounded linear operator U : H → H on a Hilbert space H that satisfies U*U = UU* = I, where U* is the adjoint of U, and I : H → H is the identity operator. Unitary operator <NUM> also can be a unitary operator that is a bounded linear operator U : H → H on a Hilbert space H for which the following hold: U is surjective and U preserves the inner product of the Hilbert space, H. In other words, for all vectors x and y in H, (Ux,Uy)H = (x,y).

As depicted, quantum processor <NUM> can apply Hadamard operator <NUM> to set <NUM> of quantum registers <NUM> after executing quantum instruction <NUM>. Quantum processor <NUM> can then measure set <NUM> of quantum registers <NUM> to form measurement <NUM> of set <NUM> of quantum registers <NUM>.

Quantum processor <NUM> can then determine approximate count <NUM> of events <NUM> using measurement <NUM> of set <NUM> of quantum registers <NUM>. In determining approximate count <NUM> from measurements <NUM>, quantum processor <NUM> determines approximate count <NUM> of events <NUM> as follows: <MAT> where C(r) is a count of logic ones in a measurement vector in the measurement, and M is a number of quantum registers. F-<NUM> is the inverse of F(c) which is as follows: <MAT> where L(E) is the length of the event vector, i is an index value, n is the number of qbits, c is the event count.

In another illustrative example, quantum processor <NUM> can determine approximate count <NUM> of events <NUM> using lookup table <NUM>. For example, quantum processor <NUM> can be configured to determine approximate count <NUM> of events <NUM> using lookup table <NUM>. In this example, lookup table <NUM> can be used to identify approximate count <NUM> of events <NUM> from a number of logic <NUM> in measurement vector <NUM> in measurement <NUM>. In other words, the number of logic ones in measurement vector <NUM> are used to find approximate count <NUM> for those input bits in lookup table <NUM>. For example, measurement vector <NUM> can be used as an input into lookup table <NUM>. The bits in measurement vector <NUM> can be used to obtain approximate count <NUM> in lookup table <NUM> that corresponds to the bits in measurement vector <NUM>.

In this illustrative example, each bit is the result of measuring a quantum register in quantum registers <NUM>. For example, if the number of output bits is <NUM>, then the number of quantum registers <NUM> measured is <NUM>.

In illustrative example, quantum processor <NUM> can also perform other operations including, for example, encoding events <NUM> into event vector <NUM>. As another example, quantum processor <NUM> can generate function <NUM> for event vector <NUM> based on event vector <NUM>, which comprises bits <NUM> that identify events <NUM>. As yet another example, quantum processor <NUM> can generate quantum instruction <NUM> incorporating function <NUM> for event vector <NUM> comprising events <NUM> identified by bits <NUM>.

In yet another example, set <NUM> of quantum registers <NUM> is first set <NUM> of quantum registers <NUM>. In this example, second set <NUM> of quantum registers is present. With second set <NUM> of quantum registers <NUM>, the same operations performed on first set <NUM> of quantum registers <NUM> can be performed on second set <NUM> of quantum registers <NUM>.

For example, quantum processor <NUM> can reset second set <NUM> of quantum registers <NUM> and apply Hadamard operator <NUM> to second set <NUM> of quantum registers <NUM>.

In this example, quantum processor <NUM> can execute complementary quantum instruction <NUM> on second set <NUM> of quantum registers <NUM> instead of quantum instruction <NUM>. As depicted, complementary quantum instruction <NUM> incorporates complementary function <NUM> that is complementary to function <NUM> for event vector <NUM> comprising events <NUM> identified by bits <NUM> in event vector <NUM>. For example, complementary function <NUM> can be as follows: <MAT> where Ei is an ith bit in event vector <NUM>, n is a number of bits <NUM> in event vector <NUM>, Xi is the ith bit in quantum register <NUM>, and i is an index value.

With this example, quantum processor <NUM> can apply Hadamard operator <NUM> to second set <NUM> of quantum registers <NUM> after executing complementary quantum instruction <NUM>. Quantum processor <NUM> can also measure second set <NUM> of quantum registers <NUM> to form second measurement <NUM> of second set <NUM> of quantum registers <NUM>. Measurement of each quantum register in second set <NUM> of quantum registers <NUM> results in a bit. The results of the measurement of second set <NUM> of quantum registers <NUM> is second measurement vector <NUM>.

In this example, measurement <NUM> is first measurement <NUM> of first set <NUM> of quantum registers <NUM>. Further, measurement vector <NUM> forms second measurement vector <NUM> when two sets of quantum registers are used in determining approximate count <NUM>.

In determining approximate count <NUM> of events <NUM>, quantum processor <NUM> can determine approximate count <NUM> of events <NUM> using first measurement <NUM> of first set <NUM> of quantum registers <NUM> and second measurement <NUM> of second set <NUM> of quantum registers <NUM>. In this example, approximate count <NUM> of events <NUM> using first measurement <NUM> of first set <NUM> of quantum registers <NUM> and second measurement <NUM> of second set <NUM> of quantum registers <NUM> can be determined by quantum processor <NUM> as follows: <MAT> where G-<NUM> is the inverse of: <MAT> and has inverse G-<NUM> that produces approximate count <NUM> of events <NUM> given the probabilities as in C(E) = G-<NUM>(p(E)-pc(E)), where n is a number of qubits used in quantum registers <NUM>, c(r1) is a first count of logic <NUM> in first measurement vector <NUM> in first measurement <NUM>, c(r2) is a second count of logic <NUM> in second measurement vector <NUM> in second measurement <NUM>, M is a number of quantum registers <NUM>, L(E) is length <NUM> of event vector <NUM>, c is the event count, and i is an index value. The event count is the number of events an event vector <NUM> and is determined by the number of <NUM> in event vector <NUM>.

In this illustrative example, the bits in first measurement vector <NUM> and second measurement vector <NUM> can be used to obtain approximate count <NUM> in lookup table <NUM>. The bits in first measurement vector <NUM> and second measurement vector <NUM> can be used to identify approximate count <NUM> in lookup table <NUM> that corresponds to the bits in these two measurement vectors.

The illustration of event counting environment <NUM> in <FIG> is not meant to imply physical or architectural limitations to the manner in which an illustrative embodiment may be implemented. Other components in addition to or in place of the ones illustrated may be used. Some components may be unnecessary. Also, the blocks are presented to illustrate some functional components. One or more of these blocks may be combined, divided, or combined and divided into different blocks when implemented in an illustrative embodiment.

For example, quantum registers <NUM> can be considered to be part of quantum processor <NUM> in some illustrative examples. As another example, event vectors <NUM> can be received serially or in parallel. When event vectors <NUM> are received in parallel, multiple approximate counts are output for event vectors <NUM> received in parallel.

With reference next to <FIG>, an illustration of a quantum processor is depicted in accordance with an illustrative embodiment. In the illustrative examples, the same reference numeral may be used in more than one figure. This reuse of a reference numeral in different figures represents the same element in the different figures.

In this illustrative example, a quantum processor can comprise quantum arithmetic logic unit (QALU) <NUM>. As depicted in this example, quantum arithmetic logic units <NUM> includes controller <NUM>, quantum instruction generator <NUM>, quantum instruction processor <NUM>, count generator <NUM>, instruction queue <NUM>, quantum registers <NUM>, and output bit register <NUM>. Although shown as a separate functional component in <FIG>, quantum registers <NUM> are part of quantum processor <NUM> implemented as part of quantum arithmetic logic unit <NUM> in this particular example.

As depicted, quantum arithmetic logic unit <NUM> receives event vector <NUM> as an input and outputs approximate count <NUM>. In this illustrative example, controller <NUM> controls the operation of functional components such as quantum instruction generator <NUM>, quantum instruction processor <NUM>, and count generator <NUM>.

As shown in this figure, quantum instruction generator <NUM> receives event vector <NUM> for processing to determine approximate count <NUM>. Event vector <NUM> is processed by quantum instruction generator <NUM> to generate quantum instruction <NUM> that incorporates function <NUM> in a manner that function <NUM> can be applied by quantum instruction processor <NUM> to the content of set <NUM> in <FIG> of quantum registers <NUM>. As depicted, quantum instruction generator <NUM> can also generate function <NUM> based on events <NUM> identified by bits <NUM> in <FIG> in event vector <NUM>. In other words, the logic <NUM> and logic <NUM> in bits <NUM> as well as the order of these logic <NUM> and logic <NUM> can determine function <NUM>.

In this illustrative example, quantum instruction <NUM> is placed into quantum instructions <NUM> in instruction queue <NUM>. Instruction queue <NUM> holds quantum instructions <NUM> which can include other quantum instructions incorporating functions based on bits in the event vectors in addition to quantum instruction <NUM>. Additionally, quantum instructions <NUM> can also include other instructions that do not incorporate function <NUM>. These other types of quantum instructions can include, for example, quantum instructions <NUM> for Hadamard operator <NUM> in <FIG>, measurement <NUM> in <FIG>, and other types quantum instructions that can cause operations to be performed on qubits <NUM> in quantum registers <NUM>.

As depicted, controller <NUM> controls the execution of quantum instructions <NUM> in instruction queue <NUM>. For example, controller <NUM> directing execution of quantum instructions <NUM> in instruction queue <NUM> can reset quantum registers <NUM> and apply Hadamard operator <NUM> to quantum registers <NUM>.

Further, the execution of quantum instructions <NUM> can then apply function <NUM> in quantum instruction <NUM> on quantum registers <NUM>. In this illustrative example, quantum instruction <NUM> is dictated to apply function <NUM> to each quantum register in quantum registers <NUM>. In other words, the same quantum instruction is executed on each of quantum registers <NUM> in the illustrative example "M" times, with M being the number of quantum registers <NUM> that are used.

The execution of quantum instructions <NUM> can apply Hadamard operator <NUM> to quantum registers <NUM> after executing quantum instruction <NUM> and measure quantum registers <NUM> to form measurement bits <NUM> in event vector <NUM> stored in output bit register <NUM>. These bits in output bit register <NUM> form measurement vector <NUM> when one set of quantum registers <NUM> is used.

As depicted, each measurement bit in measurement bits <NUM> in event vector <NUM> is a result of a measurement of a quantum register in quantum registers <NUM>. In this illustrative example, count generator <NUM> can generate approximate count <NUM> using measurement bits <NUM> in event vector <NUM>. The number of measurement bits <NUM> corresponds to the number of quantum registers <NUM> in this depicted example.

With reference next to <FIG>, an illustration of quantum instructions is depicted in accordance with an illustrative embodiment. Examples of quantum instructions <NUM> that can be located in instruction queue <NUM> in <FIG> are depicted.

As depicted, quantum instructions <NUM> can include a number of different types of instructions. In this illustrative example, quantum instructions <NUM> include reset <NUM>, Hadamard <NUM>, and quantum function <NUM>.

In this particular example, reset <NUM> is a quantum instruction that can be executed to reset quantum registers <NUM> in <FIG>. In this example, a reset of quantum registers <NUM> is performed prior to processing a new event vector in the set of quantum registers <NUM>. With a reset of the set of quantum registers <NUM>, the values of <NUM> can be put into the set of quantum registers <NUM>. The value of <NUM> is placed into a number of qubits <NUM> in <FIG> equal to the number of bits and event vector <NUM>. Additionally, a <NUM> can also be placed into an additional qubit. This additional qubit is a qubit in qubits <NUM> in addition to the number of bits in event vector <NUM>. The use of the additional qubit set to a <NUM> enables reversing a superposition in the set of quantum registers <NUM>. The ability to reverse the supervision enables measuring the contents of the set of quantum registers <NUM> in this example.

Hadamard <NUM> is a quantum instruction that applies a Hadamard operator to create superposition in qubits <NUM> in the set of quantum registers <NUM>. Hadamard <NUM> can be executed again to enable the desired result from measuring qubits <NUM> in the set of quantum registers <NUM>. A second execution of Hadamard <NUM> can be performed after the set of quantum registers <NUM> has been manipulated through other instructions.

Quantum function <NUM> is an example of quantum instruction <NUM> in <FIG> that incorporates function <NUM> in <FIG> and can be executed to apply function <NUM> on the set of quantum registers <NUM>. In other words, quantum function <NUM> is a quantum instruction that incorporates function <NUM> for execution by quantum instruction processor <NUM> in quantum processor <NUM> as shown in block form in <FIG>. As depicted, function <NUM> is a function for event vector <NUM> that comprises events <NUM> identified by bits <NUM>.

Turning to <FIG>, an illustration of data flow for determining an approximate count of events using quantum instructions and complementary quantum instructions is depicted in accordance with an illustrative embodiment. In this depicted example, an example of data flow occurring during operations performed by quantum arithmetic logic unit <NUM> in counting system <NUM> in <FIG> are depicted.

In this illustrative example, event sensor <NUM> detects events <NUM> to generate bits <NUM>, which as placed into event vector <NUM>. Event sensor <NUM> is an example of an event detector in event detectors <NUM> in <FIG>.

As depicted, quantum arithmetic logic unit <NUM> receives event vector <NUM> and generates M number of quantum instructions <NUM> and M number of complementary quantum instructions <NUM> using event vector <NUM>. In this example <NUM> quantum registers are present. Additionally, in this illustrative example, all of quantum instructions <NUM> are the same and all of complementary quantum instructions <NUM>.

As shown in this example, quantum arithmetic logic unit <NUM> resets the <NUM> quantum registers using column vectors |<NUM>> <NUM> for n bits in each quantum register and a column vector |<NUM>> <NUM> for the n+<NUM> bit in each quantum register. In this example, n is the number of bits in event vector <NUM>. Next, quantum arithmetic logic unit <NUM> applies Hadamard operators (Hn+<NUM>) <NUM> to n+<NUM> bits in the <NUM> quantum registers.

Quantum arithmetic logic unit <NUM> applies quantum instructions <NUM> and complementary quantum instructions <NUM> to the <NUM> quantum registers. In this example, quantum instructions <NUM> are applied to M quantum registers in which a quantum instruction in quantum instructions <NUM> is applied to each of the M quantum registers. As a result, the same quantum instruction is applied to each of the M quantum registers.

Further, complementary quantum instructions <NUM> are applied to M quantum registers, which are different quantum registers from the M quantum registers to which quantum instructions <NUM> are applied. In this example, a complementary quantum instruction in complementary quantum instructions <NUM> is applied to each of the M quantum registers. As a result, the same complementary quantum instruction is applied to each of the M quantum registers.

After applying the M number of quantum instructions <NUM> and the M number of complementary quantum instructions <NUM> to the quantum registers, quantum arithmetic logic unit <NUM> applies Hadamard operators (Hn+<NUM>) <NUM> to n bits in the <NUM> quantum registers.

Next, quantum arithmetic logic unit <NUM> measures the <NUM> quantum registers to obtain output bits <NUM>. In this example, output bits <NUM> are grouped into <NUM> measurement vectors, measurement vector <NUM> and measurement vector <NUM>. Each bit in output bits <NUM> in measurement vector <NUM> are from a quantum register on which a quantum instruction was applied, and each bit in output bits <NUM> in measurement vector <NUM> are from a quantum register on which a complementary quantum instruction was applied.

Measurement vector <NUM> and measurement vector <NUM> can be used to determine approximate count <NUM> of events <NUM>. As depicted, measurement vector <NUM> and measurement vector <NUM> are used as inputs into lookup table <NUM> to obtain approximate count <NUM> that corresponds to measurement vector <NUM> and measurement vector <NUM> in lookup table <NUM>.

With reference next to <FIG>, an illustration of a timing diagram for counting events is depicted in accordance with an illustrative embodiment. In this illustrative example, clock period <NUM> in timing diagram <NUM> identifies clock periods during which processing of events occurs to obtain an approximate count. In this example, an event can be processed every five clock cycles by quantum processor <NUM> in <FIG>.

Event vector <NUM> in timing diagram <NUM> identify event vectors that are processed during different clock cycles. Encode <NUM> identifies the clock cycles when encoding occurs to generate quantum instructions that incorporate functions based on the event vectors. As claimed, function <NUM> in <FIG> performs a logic AND of a first set of bits in a quantum register that corresponds to a second set of bits in the event vector that indicate a presence of an event. The function as follows: <MAT> wherein Ei is an ith bit in the event vector, n is a number of bits in the event vector, Xi is the ith bit in the quantum register, and i is an index value.

The quantum instruction encoded during each encode in encode <NUM> using the function is as follows: <MAT> where L(E) is the vector length, x is an index value, y is an index value, and f(x) is the function. This quantum instruction can be executed to operate on a quantum register of length L(E) +<NUM> = n+<NUM>.

The complementary function can be as follows: <MAT> where Ei is an ith bit in the event vector, n is a number of bits in the event vector, Xi is the ith bit in the quantum register, and i is an index value. In this case, Ufc can be encoded from the function fc(x)at the same time as Uf from function f(x).

Instructions <NUM> in timing diagram <NUM> identify instructions that are executed at the different clock periods in clock period <NUM>. As depicted, instructions <NUM> show a sequence of instructions that are performed during the different clock periods in clock period <NUM>. In this illustrative example, the sequence of instructions can be Reset, Hn+<NUM>, Uf, Ufc, and Hn. In this example, instructions Uf and Ufc can be executed parallel. This parallel execution can occur such that an additional clock period is unnecessary.

Reset in instructions <NUM> is an example of reset <NUM> in <FIG>. Hn+<NUM> is an example of Hadamard <NUM> in <FIG> performed on n+<NUM> qubits in the set of quantum registers <NUM> in which n is the number of bits in event vector <NUM> in <FIG><NUM>. In this example, a quantum register has more than n qubits. In this example, each quantum register has least n+<NUM> qubits. The measurements are made from the first n bits.

As depicted, Uf in instructions <NUM> is an example of quantum function <NUM> in <FIG>. In this illustrative example, Uf and Ufc are executed in the clock period after the function f(x) is encoded into the quantum instruction, Uf, and fc(x) is encoded into the quantum instruction, Ufc. Hn in instructions <NUM> is another example of Hadamard <NUM> that is performed on a quantum register in the set of quantum registers <NUM>. In this example, Hn is performed on qubits in a quantum register.

In this illustrative example, measurement <NUM> identifies when measurements are of the set of quantum registers. Output <NUM> indicates the time during which event output is generated to output an approximate count of events in an event vector.

As can be seen in this depicted example, an event output operation in output <NUM> begins after a measurement, measure |<NUM>> occurs in measurement <NUM> to measure the contents of set <NUM> of quantum registers <NUM> to generate output bits for measurement vector <NUM>. In this illustrative example, each bit is the result of a measurement of a quantum register. In other words, measurement of the qubits in a quantum register results in a single bit in the output bits that form measurement vector <NUM>. These output bits in measurement vector <NUM> can be used to determine approximate count <NUM>.

As depicted in this example, a reset is executed on the set of quantum registers during clock period <NUM>, and a Hn+<NUM> is executed during clock period <NUM>. During these two clock periods, the processing event vector <NUM> and the encoding of function f(x) is completed. Next, in clock period <NUM>, Uf is executed. In clock period <NUM>, Hn is executed. Measurement of the set of quantum registers <NUM> is performed in clock period <NUM>. The process then repeats as can be seen in timing diagram <NUM>. Thus, an approximate count can be determined from an event vector in five clock periods in this illustrative example.

In one illustrative example, one or more technical solutions are present that overcome a technical problem with counting events when the frequency or speed at which events occur increases. In the illustrative examples, one or more technical solutions take into account that current event counting systems have difficulty can events occurring at frequencies over <NUM>. As a result, one or more technical solutions can provide a technical effect of counting events using a quantum processing system. In the illustrative examples, a computer system including a quantum processor can provide approximate counts for events occurring at much higher rates as compared to current event counting systems.

Computer system <NUM> in <FIG> can be configured to perform at least one of the steps, operations, or actions described in the different illustrative examples using software, hardware, firmware, or a combination thereof. As a result, computer system <NUM> operates as a special purpose computer system in which quantum components such as quantum processor <NUM> in computer system <NUM> enables counting events <NUM>. In particular, quantum processor <NUM> transforms computer system <NUM> into a special purpose computer system as compared to currently available general computer systems that do not have quantum processor <NUM>.

In the illustrative example, the use of quantum processor <NUM> in computer system <NUM> integrates processes into a practical application for a method for counting events that increases the performance of computer system <NUM> in which computer system <NUM> is able to count events at much higher frequencies as compared to current computers or devices that count events. In other words, quantum processor <NUM> in computer system <NUM> is directed to a practical application of processes integrated into quantum processor <NUM> in computer system <NUM> that execute quantum instructions in quantum registers using a process that provides an approximate count of events. In this manner, quantum processor <NUM> in computer system <NUM> provides a practical application of operations to count events in a manner that increases the speed at which the events can be counted as an approximate count of the events such that the functioning of computer system <NUM> is has an improved ability to count events at increasing frequencies as compared to current events counting systems.

Turning next to <FIG>, an illustration of a flowchart of a process for counting events is depicted in accordance with an illustrative embodiment. The process in <FIG> can be implemented in hardware, software, or both. When implemented in software, the process can take the form of program code that is run by one or more processor units located in one or more hardware devices in one or more computer systems. For example, the process can be implemented in component quantum processor <NUM> in computer system <NUM> in <FIG>.

The process begins by resetting a set of quantum registers (operation <NUM>). The process applies a Hadamard operator to the set of quantum registers (operation <NUM>).

The process executes a quantum instruction on the set of quantum registers (operation <NUM>). In operation <NUM>, the quantum instruction incorporates a function for an event vector comprising events identified by bits.

The process applies the Hadamard operator to the set of quantum registers after executing the quantum instruction (operation <NUM>). The process measures the set of quantum registers to form a measurement of the set of quantum registers (operation <NUM>). The process determines an approximate count of events using the measurement of the set of quantum registers (operation <NUM>). The process terminates thereafter. In operation <NUM>, approximate count of the events is determined as follows: <MAT> where C(r) is a count of logic ones in a measurement vector in the measurement, and M is a number of quantum registers. F-<NUM> is the inverse of F(c) which is as follows: <MAT> where L(E) is the length of the event vector, i is an index value, n is the number of qbits, c is the event count.

Turning next to <FIG>, an illustration of a flowchart of a process for encoding events is depicted in accordance with an illustrative embodiment. The operation illustrated in <FIG> is an example of an additional operation that can be performed in the flowchart in <FIG> to count events.

The process begins by encoding events into an event vector with bits (operation <NUM>). The process terminates thereafter. In operation <NUM>, the process creates an event vector in which each bit indicates whether an event is present. For example, a logic <NUM> in the event vector indicates that an event was detected while a logic <NUM> indicates that an event was not detected. In other words, the bits can be generated periodically and indicate whether an event was detected at that particular period of time.

With reference next to <FIG>, an illustration of a flowchart of a process for receiving events is depicted in accordance with an illustrative embodiment. The operation illustrated in <FIG> is an example of an additional operation that can be performed in the flowchart in <FIG> to count events.

The process receives events from event detectors (operation <NUM>). In this illustrative example, these event detectors can be a hardware system such as sensor systems. A sensor system can contain one or more sensors and can generate signals in response to detecting events. In other words, the sensors transform the detection of events in an environment into at least one of electrical or optical signals that represent the detection of events in the environment.

The process generates an event vector using the events received from the event detectors (<NUM>). The process terminates thereafter. The signals received from the event detectors can be interpreted as a logic <NUM> or logic <NUM>. In other illustrative examples, the event vector can be a vector of binary digits in which a logic <NUM> indicates the absence of an event and a logic <NUM> indicates the presence of an event. In another illustrative example, a logic <NUM> can indicate an absence of the event with a logic <NUM> indicating the presence of an event.

With reference next to <FIG>, an illustration of a flowchart of a process for generating a function is depicted in accordance with an illustrative embodiment. The operation illustrative in <FIG> is an example of an additional operation that can be performed in the flowchart in <FIG> to count events.

The process generates a function for an event vector based on the event vector comprising events identified by bits (operation <NUM>). The process terminates thereafter.

With reference next to <FIG>, an illustration of a flowchart of a process for generating a quantum instruction is depicted in accordance with an illustrative embodiment. The operation illustrated in <FIG> is an example of an additional operation that can be performed in the flowchart in <FIG> to count events.

The process generates a quantum instruction incorporating a function for an event vector comprising events identified by bits (operation <NUM>). The process terminates thereafter.

Turning to <FIG>, an illustration of a flowchart of a process for determining an approximate count is depicted in accordance with an illustrative embodiment. The operation illustrative in <FIG> is an example of one implementation for operation <NUM> in <FIG>. In this example, the measurement of the set of quantum registers is a measurement vector that is `M' bits long. In this example, M is how many quantum registers are present in the set of quantum registers.

The process determines an approximate count of events using a lookup table that identifies the approximate count of the events from a number of logic <NUM> in a measurement vector in a measurement (operation <NUM>). The process terminates thereafter.

In <FIG>, an illustration of a flowchart of a process for determining an approximate count of events using two sets of quantum registers is depicted in accordance with an illustrative embodiment. The operations illustrated in <FIG> are examples of additional operations that can be performed in the process in <FIG> in determining an approximate count using two sets of quantum registers. In the illustrative example, the operations performed on the second set of quantum registers in this flowchart can be performed at the same time as corresponding operations to the first set of quantum registers.

In this example, the set of quantum registers is a first set of quantum registers. Further, the measurement of the set of quantum registers is a first measurement of the first set of quantum registers.

The process resets a second set of quantum registers (operation <NUM>). The process applies a Hadamard operator to the second set of quantum registers (operation <NUM>).

The process executes a complementary quantum instruction on the second set of quantum registers (operation <NUM>). The complementary quantum instruction incorporates a complementary function that is complementary to the function for the event vector comprising the events identified by the bits. The process applies the Hadamard operator to the second set of quantum registers after executing the complementary quantum instruction.

The process measures the second set of quantum registers to form a second measurement of the second set of quantum registers (operation <NUM>). The process terminates thereafter.

Turning to <FIG>, an illustration of determining an approximate count of events is depicted in accordance with an illustrative embodiment. The process illustrated in <FIG> is an example of an implementation for operation <NUM> in <FIG> when two sets of quantum registers are measured as described in <FIG>.

The process determines an approximate count of events using a first measurement of a first set of quantum registers and a second measurement of a second set of quantum registers (operation <NUM>). The process terminates thereafter.

The flowcharts and block diagrams in the different depicted embodiments illustrate the architecture, functionality, and operation of some possible implementations of apparatuses and methods in an illustrative embodiment. In this regard, each block in the flowcharts or block diagrams can represent at least one of a module, a segment, a function, or a portion of an operation or step. For example, one or more of the blocks can be implemented as program code, hardware, or a combination of the program code and hardware. When implemented in hardware, the hardware can, for example, take the form of integrated circuits that are manufactured or configured to perform one or more operations in the flowcharts or block diagrams. When implemented as a combination of program code and hardware, the implementation may take the form of firmware. Each block in the flowcharts or the block diagrams can be implemented using special purpose hardware systems that perform the different operations or combinations of special purpose hardware and program code run by the special purpose hardware.

In some alternative implementations of an illustrative embodiment, the function or functions noted in the blocks may occur out of the order noted in the figures. For example, in some cases, two blocks shown in succession may be performed substantially concurrently, or the blocks may sometimes be performed in the reverse order, depending upon the functionality involved. Also, other blocks may be added in addition to the illustrated blocks in a flowchart or block diagram.

In the Deutsch-Jozsa problem, two classes of functions are present. These classes are constant functions and balanced functions. In this example, f(x) is a function from n bits to <NUM> bit. For a balanced function, f(x) is constant if its output is the same for all inputs, and f(x) is a balanced function if the function is zero on half of the possible inputs and one on the other half of the possible inputs.

In this example, f(x) itself is not a reversible function. The illustrative example can be to create a reversible function that can be implemented in a quantum processor. The illustrative examples recognize and take into account that it is often a problem that internal bits are necessary to implement functions in a quantum computer and these "garbage" bits must be present as part of the quantum register. However, these "garbage" bits can be an issue if the "garbage" bits are present in the rest of the computation.

The illustrative examples recognize and take into account that one manner to handle this issue can be to start with the function f(x) from n bits to m bits. The illustrative examples recognize and take into account that a reversible operation can be created using n + m input bits which act as (x,y) → (x,y ⊕ f(x)) where ⊕ is a bitwise XOR. This is reversible but does introduce m garbage bits. Since f(x) is made up of reversible circuits, f(x)-<NUM> can be implemented by reversing the order of the circuit elements and then implementing the inverse of each of these elements.

Making any function reversible allows that function to be turned into reversible quantum gates for implementation in a quantum processor. For example, if h: <NUM>, <NUM>n → <NUM>, <NUM>n is a reversible function, then: <MAT> where h(x) is a reversible function, x is an n qbit input, and n is the number of qbits on which the reversible function operates.

This expression can be implemented using unitary gates on n qubits and, on the computational basis, it will compute the reversible function h.

Using the approach above, the reversible quantum instruction can be generated by constructing both parts of the function (x, y ⊕ f(x)) in the two parenthetical terms: <MAT> where n is, x is an n qbit input, and y is a single qbit input. Together, x and y comprise n+<NUM> qbits.

In this example, if the function is queried using computational basis states such as |x, y>, the value |x, y⊕ f(x)〉can be obtained. If y = <NUM>, f(x) has been computed. Also, if y = <NUM>, f(x) has been computed in which f(x). is the complement of f(x).

The Deutsch-Jozsa algorithm can use phase kickback to transfer the phase of qubit amplitudes into the probabilities of the states. In this example, a single qubit example is depicted. Then <MAT>.

If f(x) = <NUM>, then the value is <MAT> and if f(x) = <NUM>, the value is <MAT>. Thus, <MAT>.

As a result, the internal qubit phase is kicked back into the final phase of the output in the (-<NUM>)f(x) term.

This concept can be applied an n qubit register. The input <MAT>.

If the Hadamard operation is performed n times to Uf|ψ〉, the following is obtained: <MAT> wherein x is an n qbit input, y is a single qbit input, n is n is the number of qbits on which the reversible function operates.

In this example, H⊗n will produce a superposition over all possible states if applied to the zero state (here the zero state |<NUM>〉 is now n qubits): <MAT>.

If function f(x) is constant and the Hadamard operation are applied to the state produced after the phase kickback, then the new state is: <MAT>.

Thus, the output state will be |<NUM>〉. Conversely, if we apply to a balanced function f(x), then the calculation shows that <MAT>.

If a measurement is made along the |<NUM>〉 direction, the probability of getting |<NUM>〉 is <MAT>.

Since f is balanced, this sum is <NUM>. Thus, indication of constant or balanced is present if the result is |<NUM>〉 or not |<NUM>〉 respectively (these are n qubit values).

With reference next to <FIG>, an illustration of operations performed for a Deutsch Josza process is depicted in accordance with an illustrative embodiment. As depicted, operations <NUM> comprises performing reset operations <NUM> and Hadamard operations <NUM> on quantum registers. Next, Uf operations <NUM> are performed on the quantum registers. Hadamard operations <NUM> are performed on the quantum registers after Uf operations <NUM>. Measurement operations <NUM> are performed to obtain an output bit from each quantum register. The output bits can be used to determine the approximate count of events.

Thus, the illustrative examples provide a process that can be implemented in a quantum arithmetic logic unit. The different operations illustrated in the flowcharts can be part of a quantum event counting algorithm (QEUCA) that includes use of a Deutsch-Jozsa Algorithm and Hadamard operations.

For example, E can an event vector of length n = L(E) consisting of <NUM>'s and <NUM>'s. A quantum event counting algorithm can take E as input and produce an approximate count of the number of <NUM>'s in the event vector C(E). The process in the illustrative example can be based on a Deutsch-Jozsa function. For example, the Deutsch-Jozsa function f : {<NUM>,<NUM>}n → {<NUM>,<NUM>} for event counting can be defined as follows: Let n = L(E) + <NUM> and define f(x) = <NUM> where x = [x<NUM>,. , xL(E), xn] if and only if xi = <NUM> when Ei = <NUM> for i = <NUM>, <NUM>,. , L(E) and xn = <NUM>. Otherwise, f(x) = <NUM>. Thus f(x) is <NUM> precisely when the vector x agrees with E at every event and the last entry xn = <NUM>. This can be written using Boolean logic as follows: <MAT> Here, Λ denotes Boolean AND the factor <MAT> denotes the Boolean AND of all components of x where events are present (there is a <NUM> in the event vector). This Boolean AND operation can be constructed as part of a unitary instruction on a qubit register since it consists of quantum logic operations. The full instruction Uf is defined using f and is the quantum instruction defined by <MAT> where x is an n qbit value, y a single qbitindex value, f(x) is the function based on the event vector, and L(E) is a length of the event vector. In this example, Uf operations can be performed on n+<NUM> qbits [x,y]. This quantum instruction can be executed to operate on a qubit register of length L(E) +<NUM> = n+<NUM>, wherein L(E) is the length of the event vector and n is the number of measured qbits in a quantum register. Together with the Hadamard operations Hn+<NUM> before and Hn after Uf this allows for the computation as in Deutsch-Jozsa above and gives a result which, when measured along the <NUM>) direction (in other words, when all qubit states are measure as zero), gives the probability of getting |<NUM>〉 as <MAT> where f(x) is the function, n is the number of measured qbits in a quantum register, and x an n qbit value. In other words, the measured result is a bit which is <NUM> if the register is not in the <NUM>) state and <NUM> if it is. The probability of getting a <NUM> can be calculated and depends only the event count C(E): <MAT> where C(E) is the number of logic <NUM> in an event vector, L(E) is the length of the event vector, n is the number of measured qbits in a quantum register, and i is an index value.

The equation can be rewritten in a functional form as follows: <MAT> where L(E) is the length of the event vector, i is an index value, n is the number of qbits in a quantum register, and c is the event count.

F(c) is defined as for a integer event count c where <NUM> ≤ c ≤ L(E): Then p(E) = F(C(E)): This function F(c) is monotonic in c and so it has an inverse function F-<NUM> which takes the probability p(E) and produces the corresponding count c =C(E); as with C(E) = F-<NUM>(p(E)).

As a result, an event vector E can be processed to produce a measured qbit result that is probabilistically related to the event count C(E) of E. This processing can include using quantum operations on an n + <NUM> quantum qubit register comprising qubits. In this example, c is the event count for an event vector and is the number of ones the event vector.

The same quantum operations can be performed on M different quantum registers. This can result in producing a measurement vector that is M bits long. In other words, the length of the measurement vector is the number of quantum registers. The number of <NUM>'s in the measurement vector can be c. This number of <NUM>'s can be used to approximate p(E) ≈ C(r)/M. This approach can be performed without counting c. From the approximation, the event count could be approximated by using the inverse function F-<NUM> and computing: <MAT> where C(r) is a count of logic ones in a measurement vector and M is the number of quantum registers.

Instead, the M measured non-quantum output bits in the measurement vector can be used with a lookup table (LUT) to identify an approximate count C(E) based on the inverse function that computes C(E) from p(E) using conventional electronic circuits. This inverse function can invert the relationship between C(E) and p(E) given in equation <NUM> so that looking up an input with a p(E) value would give the corresponding C(E) value. For example, the total number of <NUM>'s in the measurement vector can be used to identify approximate count C(E) in the lookup table.

While the approach can produce an approximate event count, the accuracy can be improved to reach desired levels using a second Deutsch-Jozsa function. We can define a complementary Deutsch-Jozsa function f : c {<NUM>,<NUM>}n→ {<NUM>,<NUM>} so that f c (x) = <NUM> where x = [x<NUM>,. , xL(E) , xn] if and only if xi = <NUM> when Ei = <NUM> for i = <NUM>,<NUM>,. , L(E) and xn = <NUM>. This encoding of a complementary function fc(x) is as follows: <MAT> where Ei is an ith bit in the event vector, n is a number of bits in the event vector, Xi is the ith bit in the quantum register, and i is an index value.

In this example, fc(x) is <NUM> precisely when the bits of the vector x agree with E at every non-event. It then follows that the quantum instructions Ufc and the Hadamard operations can be used such that the measurement provides the following: <MAT>.

Combining these approaches using another set of M registers can provide two measurement vectors that are M bit vectors r<NUM> and r<NUM> as measured outputs. In this example c(r<NUM>) and c(r<NUM>) are the counts of <NUM>'s in the measurement vectors. The two counts of <NUM>'s can be used to approximate p(E) - pc (E) ≈ c(r<NUM>)/M - c(r<NUM>)/M. Therefore, the approximate event count can be expressed as: <MAT> where G-<NUM> is the inverse of: <MAT> and in which G-<NUM> produces an approximate count of the events given the probabilities as in C(E) = G-<NUM>(p(E)-pc(E)), where n is a number of qubits used in set of quantum registers, c(r1) is a first count of logic <NUM> in a first measurement vector in a first measurement, c(r2) is a second count of logic <NUM> in a second measurement vector in a second measurement <NUM>, M is a number of quantum registers, L(E) is a length <NUM> the event vector, c is an event count, and i is an index value.

In this example, a lookup table that takes <NUM> bits [r<NUM>; r<NUM>] as input and produces a stored value of G-<NUM>((C(r1)-C(r2))/M can produce the final approximate event count. In the illustrative example, using both F(x) and Fc(x)results in a more accurate approximate count of events as compared to using f alone. In other words, the inputs are used to find the approximate count to those input bits in the lookup table.

In the illustrative example, the events are sensed by a sensor that creates high and low voltage signals. These signals are then processed to create a binary vector E of length L(E) where a value of <NUM> denotes an event and a value of <NUM> denotes a non-event. In one illustrative example, <NUM>M qubit quantum registers are used. Additionally, each quantum register can have at least L(E)+<NUM> = n+<NUM> bits that are programmable as part of a quantum arithmetic logic unit such as quantum arithmetic logic unit <NUM> in <FIG>. The process performed by the quantum events counting algorithm (QECA) in one illustrative example can be summarized as follows:.

In the illustrative example, a direct mapping of algorithm to quantum arithmetic logic unit (QALU) can require quantum registers of width L(E)+<NUM>. If this register length is bigger than the available quantum register width (b), the illustrative example can be modified to accommodate this situation. For example, an event vector can be split into P equal sub vectors of length L(E)/P, wherein L(E) is the length of the event vector. In this example, assume that b ≥ L(E)=P+<NUM>. Then, the illustrative example can operate on these smaller event vectors in the available register widths and produce a final approximate count. This operation can be performed by an encoding function that would operate in parallel on each P event sub vector {Ep}p=<NUM>,. ,p to produce a collection of P encoded functions {fp} g and <MAT> for p = <NUM>,.

The quantum algorithm would be implemented on P collections of <NUM> registers which would produce P sub counts for each of the <NUM> registers. The final count can be determined by adding the P sub counts together as part of the output programmable logic.

Turning now to <FIG>, an illustration of a block diagram of a data processing system is depicted in accordance with an illustrative embodiment. Data processing system <NUM> can also be used to implement computer system <NUM> in <FIG>. In this illustrative example, data processing system <NUM> includes communications framework <NUM>, which provides communications between processor unit <NUM>, memory <NUM>, persistent storage <NUM>, communications unit <NUM>, input/output (I/O) unit <NUM>, and display <NUM>. In this example, communications framework <NUM> takes the form of a bus system.

Processor unit <NUM> serves to execute instructions for software that can be loaded into memory <NUM>. Processor unit <NUM> includes one or more processors. For example, processor unit <NUM> can be selected from at least one of a multicore processor, a central processing unit (CPU), a graphics processing unit (GPU), a physics processing unit (PPU), a digital signal processor (DSP), a network processor, or some other suitable type of processor. Further, processor unit <NUM> can may be implemented using one or more heterogeneous processor systems in which a main processor is present with secondary processors on a single chip. As another illustrative example, processor unit <NUM> can be a symmetric multi-processor system containing multiple processors of the same type on a single chip.

Memory <NUM> and persistent storage <NUM> are examples of storage devices <NUM>. A storage device is any piece of hardware that is capable of storing information, such as, for example, without limitation, at least one of data, program code in functional form, or other suitable information either on a temporary basis, a permanent basis, or both on a temporary basis and a permanent basis. Storage devices <NUM> may also be referred to as computer-readable storage devices in these illustrative examples. Memory <NUM>, in these examples, can be, for example, a random-access memory or any other suitable volatile or non-volatile storage device. Persistent storage <NUM> can take various forms, depending on the particular implementation.

For example, persistent storage <NUM> may contain one or more components or devices. For example, persistent storage <NUM> can be a hard drive, a solid-state drive (SSD), a flash memory, a rewritable optical disk, a rewritable magnetic tape, or some combination of the above. The media used by persistent storage <NUM> also can be removable. For example, a removable hard drive can be used for persistent storage <NUM>.

Communications unit <NUM>, in these illustrative examples, provides for communications with other data processing systems or devices. In these illustrative examples, communications unit <NUM> is a network interface card.

Input/output unit <NUM> allows for input and output of data with other devices that can be connected to data processing system <NUM>. For example, input/output unit <NUM> can provide a connection for user input through at least one of a keyboard, a mouse, or some other suitable input device. Further, input/output unit <NUM> can send output to a printer. Display <NUM> provides a mechanism to display information to a user.

Instructions for at least one of the operating system, applications, or programs can be located in storage devices <NUM>, which are in communication with processor unit <NUM> through communications framework <NUM>. The processes of the different embodiments can be performed by processor unit <NUM> using computer-implemented instructions, which can be located in a memory, such as memory <NUM>.

These instructions are referred to as program code, computer usable program code, or computer-readable program code that can be read and executed by a processor in processor unit <NUM>. The program code in the different embodiments can be embodied on different physical or computer-readable storage media, such as memory <NUM> or persistent storage <NUM>.

Program code <NUM> is located in a functional form on computer-readable media <NUM> that is selectively removable and can be loaded onto or transferred to data processing system <NUM> for execution by processor unit <NUM>. Program code <NUM> and computer-readable media <NUM> form computer program product <NUM> in these illustrative examples. In the illustrative example, computer-readable media <NUM> is computer-readable storage media <NUM>.

In these illustrative examples, computer-readable storage media <NUM> is a physical or tangible storage device used to store program code <NUM> rather than a media that propagates or transmits program code <NUM>. Computer readable storage media <NUM>, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

Alternatively, program code <NUM> can be transferred to data processing system <NUM> using a computer-readable signal media. The computer-readable signal media can be, for example, a propagated data signal containing program code <NUM>. For example, the computer-readable signal media can be at least one of an electromagnetic signal, an optical signal, or any other suitable type of signal. These signals can be transmitted over connections, such as wireless connections, optical fiber cable, coaxial cable, a wire, or any other suitable type of connection.

Further, as used herein, "computer-readable media" <NUM> can be singular or plural. For example, program code <NUM> can be located in computer-readable media <NUM> in the form of a single storage device or system. In another example, program code <NUM> can be located in computer-readable media <NUM> that is distributed in multiple data processing systems. In other words, some instructions in program code <NUM> can be located in one data processing system while other instructions in program code <NUM> can be located in one data processing system. For example, a portion of program code <NUM> can be located in computer-readable media <NUM> in a server computer while another portion of program code <NUM> can be located in computer-readable media <NUM> located in a set of client computers.

The different components illustrated for data processing system <NUM> are not meant to provide architectural limitations to the manner in which different embodiments can be implemented. In some illustrative examples, one or more of the components may be incorporated in or otherwise form a portion of, another component. For example, memory <NUM>, or portions thereof, can be incorporated in processor unit <NUM> in some illustrative examples. The different illustrative embodiments can be implemented in a data processing system including components in addition to or in place of those illustrated for data processing system <NUM>. Other components shown in <FIG> can be varied from the illustrative examples shown. The different embodiments can be implemented using any hardware device or system capable of running program code <NUM>.

Illustrative embodiments of the disclosure may be described in the context of aircraft manufacturing and service method <NUM> as shown in <FIG> and aircraft <NUM> as shown in <FIG>. Turning first to <FIG>, an illustration of an aircraft manufacturing and service method is depicted in accordance with an illustrative embodiment. During pre-production, aircraft manufacturing and service method <NUM> may include specification and design <NUM> of aircraft <NUM> in <FIG> and material procurement <NUM>.

During production, component and subassembly manufacturing <NUM> and system integration <NUM> of aircraft <NUM> in <FIG> takes place. Thereafter, aircraft <NUM> in <FIG> can go through certification and delivery <NUM> in order to be placed. While in service <NUM> by a customer, aircraft <NUM> in <FIG> is scheduled for routine maintenance and service <NUM>, which may include modification, reconfiguration, refurbishment, and other maintenance or service.

Each of the processes of aircraft manufacturing and service method <NUM> may be performed or carried out by a system integrator, a third party, an operator, or some combination thereof.

With reference now to <FIG>, an illustration of an aircraft is depicted in which an illustrative embodiment may be implemented. In this example, aircraft <NUM> is produced by aircraft manufacturing and service method <NUM> in <FIG> and may include airframe <NUM> with plurality of systems <NUM> and interior <NUM>. Examples of systems <NUM> include one or more of propulsion system <NUM>, electrical system <NUM>, hydraulic system <NUM>, and environmental system <NUM>. Any number of other systems may be included. Although an aerospace example is shown, different illustrative embodiments may be applied to other industries, such as the automotive industry.

Apparatuses and methods embodied herein may be employed during at least one of the stages of aircraft manufacturing and service method <NUM> in <FIG>. For example, event can systems such as event counting system <NUM> can be implemented in aircraft <NUM>. This implementation can be performed as part of the manufacturing of aircraft <NUM>. In another illustrative example, event counting system <NUM> in <FIG> can be implemented during maintenance and service <NUM>, which may include modification, reconfiguration, refurbishment, and other maintenance or service. The use of event counting system <NUM> can improve the ability to count events for at least one of systems in aircraft <NUM> or the environment around aircraft <NUM> during in service <NUM>.

Claim 1:
A computer-implemented method (<NUM>) for counting events (<NUM>, <NUM>), the method comprising:
resetting (<NUM>) a set (<NUM>) of quantum registers (<NUM>);
applying (<NUM>)a Hadamard operator (<NUM>) to the set (<NUM>) of quantum registers (<NUM>);
executing (<NUM>) a quantum instruction (<NUM>) on the set (<NUM>) of quantum registers (<NUM>), wherein the quantum instruction (<NUM>) incorporates a function (<NUM>) for an event vector (<NUM>, <NUM>) comprising events (<NUM>, <NUM>) identified by bits (<NUM>, <NUM>), wherein said function (<NUM>) is as follows: <MAT> wherein Λ denotes Boolean AND, the factor <MAT> denotes the Boolean AND of all components of x where events are present, Ei is an ith bit in the event vector (<NUM>, <NUM>), n is a number of bits (<NUM>, <NUM>) in the event vector (<NUM>, <NUM>), Xi is the ith bit in the quantum register, and i is an index value, said quantum instruction (<NUM>) being defined by <MAT> where x is an n qbit value, y a single qbitindex value, f(x) is the function based on the event vector, and L(E) is a length (<NUM>) of the event vector (<NUM>, <NUM>);
applying (<NUM>) the Hadamard operator (<NUM>) to the set (<NUM>) of quantum registers (<NUM>) after executing the quantum instruction (<NUM>);
measuring (<NUM>) the set (<NUM>) of quantum registers (<NUM>) to form a measurement (<NUM>) of the set (<NUM>) of quantum registers (<NUM>); and
determining (<NUM>) an approximate count (<NUM>) of the events (<NUM>, <NUM>) using the measurement (<NUM>) of the set (<NUM>) of quantum registers (<NUM>), wherein determining (<NUM>) the approximate count (<NUM>) of the events (<NUM>, <NUM>) using the measurement (<NUM>) of the set (<NUM>) of quantum registers (<NUM>) comprises:
determining the approximate count (<NUM>) of the events (<NUM>, <NUM>) as follows: <MAT> where C(r) is a count of logic ones in a measurement (<NUM>) vector in the measurement (<NUM>), M is a number of quantum registers (<NUM>) and F-<NUM> is an inverse of F(c) which is as follows: <MAT> where i is an index value, n is a number of qbits, c is an event count.