Patent Description:
Growing demand for miniaturization of semiconductor devices has introduced a nanosheet transistor characterized by multiple nanosheet layers bridging source/drain regions formed at both ends thereof and a gate structure that entirely wraps around all sides of the nanosheet layers. These nanosheet layers function as multiple channels for current flow between the source/drain regions of the nanosheet transistor. Due to this structure, improved control of current flow through the multiple channels is enabled in addition to higher device density in a semiconductor device including the nanosheet transistor. The nanosheet transistor is also referred to as various different names such as multi-bridge channel FET (MBCFET), nanobeam, nanoribbon, superimposed channel device, etc..

<FIG> illustrates a related art nanosheet structure for a semiconductor device. A nanosheet structure <NUM> shown in <FIG> includes two or more nanosheet layers <NUM> which are vertically stacked above a substrate <NUM> in an overlapping manner in a D3 direction. The nanosheet layers <NUM>, functioning as channels of a transistor formed by the nanosheet structure <NUM>, are completely surrounded by a gate structure <NUM> except at their open ends formed at two opposite sides of the gate structure <NUM> where source/drain regions are to be grown to complete the nanosheet structure <NUM> as a single transistor such as a nanosheet metal-oxide-semiconductor FET (MOSFET). That is, the nanosheet structure of <FIG> enables a single transistor having multiple channels between source/drain regions unlike the conventional planar FET or finFET having a single layer or a single fin channel structure. In <FIG>, source/drain regions are intentionally omitted from the nanosheet structure <NUM> only to show how the nanosheet layers <NUM> take a form of respectively penetrating the gate structures <NUM> in a D2 direction which is a channel length direction of the nanosheet structure <NUM>.

The substrate <NUM> may be a bulk substrate of a semiconductor material, for example, silicon (Si), or a silicon-on-insulator (SOI) substrate, the nanosheet layers <NUM> may also be formed of Si, and the gate structure <NUM> may be formed of a conductor metal and a gate dielectric layer. The conductor metal may be tungsten (W) or aluminum (Al), and the dielectric may include silicon oxide (SiO) or metal silicate for electrical insulation from the nanosheet layers <NUM>.

However, technology to reduce the size of a single transistor is limited even if the transistor is formed of multiple channel layers like the nanosheet layers <NUM>.

Information disclosed in this Background section has already been known to the inventors before achieving the embodiments of the present application or is technical information acquired in the process of achieving the embodiments. Therefore, it may contain information that does not form prior art that is already known to the public.

From document <CIT> it is known a three-dimensional CMOS circuit having at least a first N-conductivity field-effect transistor and a second P-conductivity field-effect transistor respectively formed on first and second crystalline substrates. The first field-effect transistor is oriented, in the first substrate, with a first secondary crystallographic orientation. The second field-effect transistor is oriented, in the second substrate, with a second secondary crystallographic orientation. The orientations of the first and second transistors form a different angle from the angle formed, in one of the substrates, by the first and second secondary crystallographic directions. The first and second substrates are assembled vertically.

Furthermore, document <CIT> discloses in <FIG> a stacked CMOS field-effect transistor (FET) device wherein the orientation of the bottom level FET is rotated <NUM> or -<NUM> degrees with respect to the top level FET, such that, for example, fins corresponding to the bottom and top level FETs are perpendicular to each other. It is also disclosed that this can be applied to nanosheet FET devices. A p-n source/drain contact exploits an overlap of top and bottom source/drain regions to connect source/drain regions of the PFET and the NFET.

The present invention provides a semiconductor device that includes a multi-stack nanosheet structure having two or more nanosheet stacks having different channel directions and a method of manufacturing such a semiconductor device.

The invention is set out by the appended set of claims.

The semiconductor device according to the invention enables to have source/drain contact structures to land on top surfaces of source/drain regions of a lower nanosheet stack instead of side surfaces thereof, and reduce parasitic capacitance between the source/drain contact structures and source/drain regions of an upper nanosheet stack.

Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:.

The embodiments described herein are all example embodiments, and thus, the inventive concept is not limited thereto, and may be realized in various other forms. Each of the embodiments provided in the following description is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the inventive concept. For example, even if matters described in a specific example or embodiment are not described in a different example or embodiment thereto, the matters may be understood as being related to or combined with the different example or embodiment, unless otherwise mentioned in descriptions thereof. In addition, it should be understood that all descriptions of principles, aspects, examples, and embodiments of the inventive concept are intended to encompass structural and functional equivalents thereof. In addition, these equivalents should be understood as including not only currently well-known equivalents but also equivalents to be developed in the future, that is, all devices invented to perform the same functions regardless of the structures thereof. For example, a MOSFET described herein may take a different type or form of a transistor as long as the inventive concept can be applied thereto.

It will be understood that when an element, component, layer, pattern, structure, region, or so on (hereinafter collectively "element") of a semiconductor device is referred to as being "over," "above," "on," "below," "under," "beneath," "connected to" or "coupled to" another element the semiconductor device, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or an intervening element(s) may be present. In contrast, when an element of a semiconductor device is referred to as being "directly over," "directly above," "directly on," "directly below," "directly under," "directly beneath," "directly connected to" or "directly coupled to" another element of the semiconductor device, there are no intervening elements present. Like numerals refer to like elements throughout this disclosure.

Spatially relative terms, such as "over," "above," "on," "upper," "below," "under," "beneath," "lower," and the like, may be used herein for ease of description to describe one element's relationship to another element(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of a semiconductor device in use or operation in addition to the orientation depicted in the figures. For example, if the semiconductor device in the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the term "below" can encompass both an orientation of above and below. The semiconductor device may be otherwise oriented (rotated <NUM> degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Herein, when a term "same" is used to compare a dimension of two or more elements, the term may cover a "substantially same" dimension.

It will be understood that, although the terms first, second, third, fourth etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept.

It will be also understood that, even if a certain step or operation of manufacturing an inventive apparatus or structure is described later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

Many embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of the embodiments (and intermediate structures). Thus, the embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present inventive concept. Further, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

For the sake of brevity, conventional elements to semiconductor devices including nanosheet transistors may or may not be described in detail herein.

The nanosheet structure <NUM> shown in <FIG> can also be stacked vertically to constitute a multi-stack nanosheet structure to achieve an increased device density gain.

<FIG> illustrates a perspective view of a semiconductor device formed of a plurality of nanosheet layers, according to a comparative example.

A semiconductor device 200A shown in <FIG> is in a state before the semiconductor device 200A is formed as two nanosheet transistors. The semiconductor device 200A has a <NUM>st channel set of a plurality of <NUM>st nanosheet layers <NUM> and a <NUM>nd channel set of a plurality of <NUM>nd nanosheet layers <NUM>. The <NUM>st and <NUM>nd channel sets are stacked above a substrate <NUM> in a vertically overlapping manner in the D3 direction to constitute a multi-stack nanosheet structure. An isolation layer <NUM> is interposed between the <NUM>st and <NUM>nd channel sets.

<FIG> also shows that <NUM>st and <NUM>nd gate structures <NUM> and <NUM> completely surround channel regions (not seen) of the <NUM>st and <NUM>nd nanosheet layers <NUM> and <NUM>, respectively, except their open ends at two opposite sides of the <NUM>st and <NUM>nd gate structures <NUM> and <NUM> where source/drain regions may be epitaxially grown to constitute two nanosheet transistors as shown in <FIG>. Thus, the <NUM>st and <NUM>nd nanosheet layers <NUM> and <NUM> take a form of penetrating the gate structures <NUM> and <NUM> in the D2 direction, which is a channel length direction.

<FIG> illustrates a perspective view of a semiconductor device after source/drain regions are formed at the semiconductor device 200A of <FIG>.

Referring to <FIG>, a semiconductor device 200B includes a lower transistor <NUM> having <NUM>st and <NUM>nd source/drain regions <NUM> and <NUM> at both ends of channel regions (not seen) of the <NUM>st nanosheet layers <NUM>, and an upper transistor <NUM> having <NUM>rd and <NUM>th source/drain regions <NUM> and <NUM> at both ends of the channel regions (not seen) of the <NUM>nd nanosheet layers <NUM>. These source/drain regions <NUM> to <NUM> will be respectively connected to power sources or other circuit elements (not shown) for internal routing through <NUM>st to <NUM>th source/drain contact structures <NUM> to <NUM>. Further, the <NUM>nd gate structure <NUM> is configured to receive a gate input signal through a gate contact structure <NUM>.

However, it is noted that because the <NUM>rd and <NUM>th source/drain regions <NUM> and <NUM> of the upper transistor <NUM> vertically overlap the <NUM>st and <NUM>nd source/drain regions <NUM> and <NUM> of the lower transistor <NUM>, respectively, the <NUM>st and <NUM>nd source/drain contact structures <NUM> and <NUM> extended straight downward from upper metal patterns (not shown) are bent to make respective lateral contacts with the side surfaces of the <NUM>st and <NUM>nd source/drain regions <NUM> and <NUM> of the lower transistor <NUM>. Otherwise, the <NUM>st and <NUM>nd source/drain contact structures <NUM> and <NUM> can be connected from below, in which case corresponding lower metal patterns connected to the <NUM>st and <NUM>nd source/drain contact structures <NUM> and <NUM> may be buried in the substrate <NUM>.

However, it is very difficult to implement the aforementioned lateral connection to a source/drain region with a bent-shaped source/drain contact structure and the upward connection using a substrate-buried metal pattern during a manufacturing process of a nanosheet-based semiconductor device.

Thus, according to an embodiment, a new structure of a semiconductor device formed of a plurality of nanosheet layers and a method of manufacturing the same are provided as following.

<FIG> illustrates a perspective view of a semiconductor device formed of a crossing multi-stack nanosheet structure according to an embodiment.

A semiconductor device 300A shown in <FIG> according to an embodiment is in a state before the semiconductor device 300A is formed as two nanosheet transistors, like the semiconductor device 200A of <FIG>. Similar to the semiconductor device 200A of <FIG>, the semiconductor device 300A shown in <FIG> has a <NUM>st channel set of a plurality of <NUM>st nanosheet layers <NUM> and a <NUM>nd channel set of a plurality of <NUM>nd nanosheet layers <NUM>. The <NUM>st and <NUM>nd channel sets are stacked above a substrate <NUM> in a vertically overlapping manner in the D3 direction to constitute a multi-stack nanosheet structure. An isolation layer <NUM> is interposed between the <NUM>st and <NUM>nd channel sets.

Further, <NUM>st and <NUM>nd gate structures <NUM> and <NUM> completely surround channel regions (not seen) of the <NUM>st and <NUM>nd nanosheet layers, respectively, except their open ends at two opposite sides of the <NUM>st and <NUM>nd gate structures <NUM> and <NUM> where source/drain regions may be epitaxially grown to constitute two nanosheet transistors as shown in <FIG>.

However, the semiconductor device 300A is different from the semiconductor device 200A in that the <NUM>nd nanosheet layers <NUM> are extended in the D1 direction while the <NUM>st nanosheet layers <NUM> structure are extended in the D2 direction. That is, the channel length direction and the channel width direction of the <NUM>st nanosheet layers are at an angle, such as perpendicular, to the channel length direction and the channel width direction of the <NUM>nd nanosheet layers, respectively. This structural difference of the semiconductor device 300A from the semiconductor device 200A is intended so that source/drain regions formed from the <NUM>nd nanosheet layers <NUM> do not vertically overlap source/drain regions formed from the <NUM>st nanosheet layers <NUM> as described below with reference to <FIG>.

<FIG> illustrates a semiconductor device after source/drain regions are formed on the semiconductor device 300A of <FIG>.

Referring to <FIG>, a semiconductor device 300B according to an embodiment includes a lower transistor <NUM> having <NUM>st and <NUM>nd source/drain regions <NUM> and <NUM> at both ends of its channel regions (not seen) of the <NUM>st nanosheet layers <NUM>, and an upper transistor <NUM> having <NUM>rd and <NUM>th source/drain regions <NUM> and <NUM> at both ends of channel regions (not seen) of the <NUM>nd nanosheet layers <NUM>. These source/drain regions <NUM> to <NUM> will be respectively connected to power sources or other circuit elements (not shown) for internal routing through <NUM>st to <NUM>th source/drain contact structures <NUM> to <NUM>. Further, the <NUM>nd gate structure <NUM> is configured to receive a gate input signal through a gate contact structure <NUM>.

The above-described structural aspects of the semiconductor device 300B are similar to those of the semiconductor device 200B of <FIG> except that the <NUM>rd and <NUM>th source/drain regions formed on channel ends of the <NUM>nd nanosheet layers do not vertically overlap the <NUM>st and <NUM>nd source/drain regions formed on channel ends of the <NUM>st nanosheet layers. Thus, the semiconductor device 300B, unlike the semiconductor device 200B of <FIG>, does not require <NUM>st and <NUM>nd source/drain contact structures <NUM> and <NUM> extended straight downward from upper metal patterns or a metal layer (not shown) to be bent to make respective lateral contacts with the side surfaces of the <NUM>st and <NUM>nd source/drain regions <NUM> and <NUM> of the lower transistor <NUM>, respectively. Thus, the <NUM>st and <NUM>nd source/drain contact structures can be configured to land on top surfaces of the <NUM>st and <NUM>nd source/drain regions without being bent like in the semiconductor device 200B of <FIG>.

The above structural characteristics of the semiconductor device 300B enables far simpler formation of source/drain contact structures compared to the related art semiconductor device. In addition, as the distance between the <NUM>rd or <NUM>th source/drain region <NUM> or <NUM> and the <NUM>st or <NUM>nd source/drain contact structure <NUM> or <NUM> in the semiconductor device 300B of <FIG> becomes greater, it is possible to reduce a parasitic capacitance that may occur between the <NUM>rd or <NUM>th source/drain region <NUM> or <NUM> and the <NUM>st or <NUM>nd source/drain contact structure <NUM> or <NUM>, compared to the structure of the semiconductor device 200B of <FIG>.

In the semiconductor device 300B, the lower transistor <NUM> may be one of a p-type MOSFET and an n-type MOSFET, while the upper transistor <NUM> may be the other of the p-type MOSFET and the n-type MOSFET, in which case the <NUM>st and <NUM>nd source/drain regions may be differently doped from the <NUM>rd and <NUM>th source/drain regions, and the <NUM>st gate structure <NUM> may have a different work function material or characteristic from the <NUM>nd gate structure <NUM>.

Herebelow, a method of manufacturing a semiconductor device having a structure corresponding to the structure of the above-described semiconductor device 300B is described.

<FIG> through <FIG> illustrate a method of manufacturing a semiconductor device having a multi-stack nanosheet structure, according to embodiments. In the drawings, the reference numbers indicating the same elements in different drawings may be omitted in one or more of the drawings for brevity.

<FIG> illustrate two cross-sectional views and a plan view of a semiconductor device, respectively, in a state where a plurality of nanosheet stacks are formed on a substrate, according to an embodiment.

<FIG> is a cross-sectional view of a semiconductor device <NUM> taken along a line X-X' in <FIG> which is a top plan view of the semiconductor device <NUM>, and <FIG> is a cross-sectional view of a semiconductor device <NUM> taken along a line Y-Y' in <FIG>. It is noted here that the scale used to show the semiconductor device <NUM> used in <FIG> is not the same as that used in <FIG>. This scale difference applies to all of the other drawings referred to herebelow.

Referring to <FIG>, a <NUM>st nanosheet stack <NUM> and a <NUM>nd nanosheet stack <NUM> are sequentially stacked on a substrate <NUM> with <NUM>st and <NUM>nd isolation layers <NUM> and <NUM> therebetween, respectively, and entirely enclosed by a <NUM>rd isolation layer <NUM>, according to an embodiment. The <NUM>st nanosheet stack <NUM> includes three <NUM>st sacrificial layers <NUM> and two <NUM>st nanosheet layers 410C formed alternatingly above the substrate <NUM>, and the <NUM>nd nanosheet stack <NUM> includes three <NUM>nd sacrificial layers <NUM> and two <NUM>nd nanosheet layers 420C formed alternatingly above the <NUM>st nanosheet stack <NUM>.

Although <FIG> show that the <NUM>st and <NUM>nd nanosheet stacks <NUM> and <NUM> each have only two nanosheet layers and three sacrificial layers, the number of the nanosheet layers and the sacrificial layers in each nanosheet stack is not limited thereto. According to an embodiment, the <NUM>st sacrificial layers <NUM> and the <NUM>st nanosheet layers 410C may be formed by epitaxially growing one layer and then another until a desired number of the sacrificial layers and the nanosheet layers are alternatingly stacked. In the same manner as the <NUM>st nanosheet stack <NUM>, the <NUM>nd sacrificial layers <NUM> and the <NUM>nd nanosheet layers 420C may be formed to build the <NUM>nd nanosheet stack <NUM>. According to an embodiment, the number of nanosheet layers and the number of sacrificial layers of the <NUM>st nanosheet stack <NUM> may differ from those of the <NUM>nd nanosheet stack <NUM>.

According to an embodiment, the <NUM>st isolation layer <NUM> may be epitaxially grown on the substrate <NUM> before the <NUM>st nanosheet stack <NUM> is formed on the substrate <NUM> to isolate the <NUM>st nanosheet stack <NUM> from the substrate <NUM>. After the <NUM>st nanosheet stack <NUM> is formed, the <NUM>nd isolation layer <NUM> may be formed to separate the <NUM>st nanosheet stack <NUM> from the <NUM>nd nanosheet stack <NUM> to be formed thereafter. After the <NUM>nd nanosheet stack <NUM> is formed on the <NUM>nd isolation layer <NUM>, the <NUM>rd isolation layer <NUM> is formed to entirely enclose the <NUM>st and <NUM>nd nanosheet stacks <NUM> and <NUM> above the substrate <NUM>.

On the substrate <NUM>, shallow trench isolation (STI) regions <NUM> are formed to isolate the semiconductor device <NUM> from neighboring circuit elements or semiconductor devices.

Each of the <NUM>st nanosheet layers 410C of the <NUM>st nanosheet stack <NUM> has a same length L1 in a Y direction, a same width W1 in a X direction, and may have a same thickness T1 in a Z direction, and each of the <NUM>nd nanosheet layers 420C of the <NUM>nd nanosheet stack <NUM> has a same length L2 in the X direction, the same width W2 in the Y direction, and may have the same thickness T2 in the Z direction. Further, according to an embodiment, the length L1, the width W1, the length L2, and the width W2 may be equal to one another. Thus, the <NUM>st and <NUM>nd nanosheet stacks <NUM> and <NUM> may have a same square shape in a plan view (not shown). However, these dimensions may differ between the <NUM>st nanosheet layers 410C and between the <NUM>nd nanosheet layers 420C, and between the <NUM>st nanosheet stack <NUM> and the <NUM>nd nanosheet stack <NUM>, according to embodiments. For example, the length L1 may not equal to the width W1 but may be equal to the width W2, and thus, the <NUM>st and <NUM>nd nanosheet stacks <NUM> and <NUM> may have a same rectangular shape. Still, however, the channel length direction and the channel width direction of the <NUM>st nanosheet layers 410C is different from the channel length direction and the channel width direction of the <NUM>nd nanosheet layers 420C, and the width W1 is equal to the length L2.

The substrate <NUM> may be formed of silicon (Si), the STI regions <NUM> may be formed of silicon oxide (SiOx), the <NUM>st to <NUM>rd isolation layers <NUM> to <NUM> may also be formed of SiOx the same as or different from the STI region <NUM>, the <NUM>st and <NUM>nd sacrificial layers <NUM> and <NUM> may be formed of silicon-germanium (SiGe), and the <NUM>st and <NUM>nd nanosheet layers 410C and 420C may be formed of Si. The <NUM>st and <NUM>nd sacrificial layers <NUM> and <NUM> may be SiGe <NUM>%, which indicates that the SiGe compound consists of <NUM>% of Ge and <NUM>% of Si, according to an embodiment.

<FIG> illustrate two cross-sectional views and a plan view of a semiconductor device, respectively, with dummy gates formed thereon, according to an embodiment.

<FIG> is a cross-sectional view of a semiconductor device <NUM> taken along a line X-X' in <FIG> which is a top plan view of the semiconductor device <NUM>, and <FIG> is a cross-sectional view of a semiconductor device <NUM> taken along a line Y-Y' in <FIG>.

Referring to <FIG>, <NUM>st and <NUM>nd dummy gates 414D and 424D, and an interlayer dielectric (ILD) layer <NUM> are formed on the semiconductor device <NUM> of <FIG>. The <NUM>st and <NUM>nd dummy gates 414D and 424D are termed as such because they are to be replaced with real gate structures in a later step.

The <NUM>st dummy gate 414D is formed, for example, by lithography and etching, on the <NUM>st nanosheet stack <NUM> to cover all side flanks of the <NUM>st nanosheet stack <NUM> formed below the <NUM>nd nanosheet stack <NUM>. Specifically, the <NUM>st dummy gate 414D encloses the <NUM>rd isolation layer <NUM> formed on all side surfaces of the <NUM>st nanosheet stack <NUM>. Next, the <NUM>nd dummy gate 424D is formed on the <NUM>st dummy gate 414D, for example, also by lithography and etching, to cover not only all side flanks but also a top of the <NUM>nd nanosheet stack <NUM>. Specifically, the <NUM>nd dummy gate 424D encloses the <NUM>rd isolation layer <NUM> formed on all side surfaces and top surface of the <NUM>nd nanosheet structure <NUM>.

The <NUM>st dummy gate 414D may include amorphous silicon (a-Si) or polycrystalline silicon (poly-Si), and the <NUM>nd dummy gate 424D may include the same or different a-Si or poly-Si.

Once the <NUM>st and <NUM>nd dummy gates 414D and 424D are formed as described above, the ILD layer <NUM> is formed to enclose all side surfaces of the <NUM>st and <NUM>nd dummy gates. The ILD layer <NUM> may be formed by depositing an oxide material in bulk (e.g., silicon dioxide having a low-k dielectric). According to an embodiment, the ILD layer <NUM> may be formed before the <NUM>st and <NUM>nd dummy gates 414D and 424D are formed.

After the <NUM>st and <NUM>nd dummy gates 414D, 424D and the ILD layer <NUM> are formed as described above, the <NUM>nd dummy gates 424D and the ILD layer <NUM> are planarized at their top surfaces, for example, by a chemical mechanical polishing (CMP) process.

Like <FIG>, <FIG> show the same structure of the semiconductor device <NUM> because its X-direction cross section has the same structural dimensions as its Y-direction cross section.

<FIG> illustrate two cross-sectional views and a plan view of a semiconductor device, respectively, in which parts of a dummy gate enclosing an upper nanosheet stack are patterned, according to an embodiment.

Referring to <FIG>, the <NUM>nd dummy gate 424D, the ILD layer <NUM> and the <NUM>rd isolation layer <NUM> are partially patterned, for example, by dry etching, at each of the four sides of the <NUM>nd nanosheet stack from top only by a predetermined length W, for example, by dry etching. Here, the predetermined length W may not be greater than each of the width W2 and the length L2 of the <NUM>nd nanosheet layer.

This patterning operation is performed from top to bottom to reach a level of a top surface of the uppermost <NUM>st sacrificial layer <NUM> of the <NUM>st nanosheet stack <NUM>. In order to facilitate this patterning, an etch stop layer (not shown) may have been layered in the ILD layer <NUM>, the <NUM>st dummy gate 414D, and the <NUM>rd isolation layer <NUM> at the level of the top surface of the uppermost <NUM>st sacrificial layer <NUM> in the step shown in <FIG>, according to an embodiment. By this patterning operation, all four sides of the <NUM>nd nanosheet stack are exposed, and the <NUM>st dummy gate 414D, the ILD layer <NUM> and the <NUM>rd isolation layer <NUM> enclosing four sides of the <NUM>st nanosheet stack are exposed upward before a top channel passivation layer <NUM> is formed on the exposed four sides of the <NUM>nd nanosheet stack <NUM> and the exposed the <NUM>rd isolation layer <NUM>.

According to an embodiment, this patterning operation may be performed by forming a mask layer (not shown) above the <NUM>nd dummy gate 424D corresponding to <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM> of the <NUM>nd dummy gate 424D as shown in <FIG>. According to an embodiment, the <NUM>th section <NUM>-<NUM> of the <NUM>nd dummy gate 424D may have a square or rectangular shape having a horizontal length of which is the same as the width of the <NUM>nd nanosheet layers and the length of the <NUM>nd nanosheet layer. Further, the <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM> may take a shape of four protrusions from four edges of the <NUM>th section <NUM>-<NUM> as shown in the top plan view of the semiconductor device <NUM> in <FIG>.

It is noted here that the <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM> are patterned around the <NUM>th section <NUM>-<NUM>, which is a main body section, in the <NUM>nd dummy gate 424D to obtain a hole or trench (hereafter "hole") penetrating into at least one of the <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM> through which at least the <NUM>st dummy gate 414D and the <NUM>st sacrificial layer <NUM> of the <NUM>st nanosheet stack <NUM> are removed, and a replacement metal gate (RMG) to surround the <NUM>st nanosheet layers of the <NUM>st nanosheet stack <NUM> crossing the <NUM>nd nanosheet layers of the <NUM>nd nanosheet stack <NUM> can be deposited at a later step. Although <FIG> shows that the <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM> are formed by the above-described patterning, only one, two or three sections of the <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM> may be patterned to serve the aforementioned purposes. Further, the sizes of the <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM> with respect to that of the <NUM>th section <NUM>-<NUM> shown in <FIG> are not to exact scale. Further, according to embodiments, the <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM> may have different sizes from one another.

Next, the top channel passivation layer <NUM> is formed on the exposed four sides of the <NUM>nd nanosheet stack <NUM> and the exposed <NUM>rd isolation layer <NUM> from the above-described patterning. The top channel passivation layer <NUM> is formed to protect the <NUM>nd nanosheet layers 420C of the <NUM>nd nanosheet stack <NUM> when source/drain regions are epitaxially grown on the <NUM>st nanosheet layers 410C of the <NUM>st nanosheet stack <NUM> in a later step. The top channel passivation layer <NUM> at two sides of the <NUM>nd nanosheet stack as shown in <FIG> along with the <NUM>th section <NUM>-<NUM> of the <NUM>nd dummy gate 424D are to be used as a mask to remove the <NUM>st dummy gate 414D, the ILD layer <NUM> and the <NUM>rd isolation layer <NUM> at two sides of the <NUM>st nanosheet stack where source/drain regions are to be epitaxially grown in the next step.

<FIG> illustrate two cross-sectional views and a top plan view of a semiconductor device, respectively, in which source/drain regions are grown on a lower nanosheet stack, according to an embodiment.

Referring to <FIG>, the <NUM>st dummy gate 414D, the ILD layer <NUM> and the <NUM>rd isolation layer <NUM> enclosing the <NUM>st nanosheet stack are partially removed at two sides of the <NUM>st nanosheet stack <NUM> to expose two ends of the <NUM>st nanosheet stack <NUM> in the channel length direction, for example, by dry etching and/or wet etching, and then, source/drain regions <NUM> and <NUM> are formed at the two sides of the <NUM>st nanosheet stack <NUM>, that is, two sides along the Y-Y' axis of <FIG>, but not along the sides of the X-X' axis of <FIG>. These source/drain regions <NUM> and <NUM> correspond to the source/drain regions <NUM> and <NUM> of the lower transistor <NUM> shown in <FIG>. The source/drain region <NUM> and <NUM> may be formed through epitaxial growth process on the exposed two ends of the <NUM>st nanosheet stack <NUM>, specifically, the <NUM>st nanosheet layers 410C, in the channel length direction. In-situ doping (ISD) may be applied to dope the source/drain regions <NUM> and <NUM>.

<FIG> illustrate two cross-sectional views and a top plan view of a semiconductor device, respectively, in which source/drain regions are grown on an upper nanosheet stack, according to an embodiment.

Referring to <FIG>, the top channel passivation layer <NUM> formed at both ends of the <NUM>nd nanosheet stack <NUM> in its channel length direction and the <NUM>rd isolation layer <NUM> therebelow are removed along the X-X' direction in <FIG>, for example, by dry etching, and a <NUM>th isolation layer <NUM> is formed on the exposed ILD layer <NUM> and the <NUM>st dummy gate 414D at both ends of the <NUM>st nanosheet stack in its channel length direction. The <NUM>th isolation layer <NUM> may be formed of SiO, SiN or its equivalents to further isolate the <NUM>st and <NUM>nd source/drain regions <NUM> and <NUM> from <NUM>rd and <NUM>th source/drain regions <NUM> and <NUM> to be formed. The thickness of this <NUM>th isolation layer <NUM> may be the same as the <NUM>nd isolation layer <NUM>.

Next, the <NUM>rd and <NUM>th source/drain regions <NUM> and <NUM> are formed on the <NUM>th isolation layer <NUM> at both ends of the <NUM>nd nanosheet stack <NUM> in its channel length direction along the X-X' direction as shown in <FIG> in the same manner as the <NUM>st and <NUM>nd source/drain regions <NUM> and <NUM> are formed in the previous step.

<FIG> illustrate two cross-sectional views and a top plan view of a semiconductor device, respectively, in which an additional ILD layer is formed above an upper nanosheet stack, according to an embodiment.

<FIG> is a cross-sectional view of a semiconductor device <NUM> taken along a line X-X' in <FIG> which is a top plan view of the semiconductor device <NUM>, and <FIG> is a cross-sectional view of a semiconductor device <NUM> taken along a line Y-Y' in <FIG>. It is noted here that the lines X-X' and Y-Y' shown in <FIG> are not center lines of the semiconductor device <NUM> in the top plan view as the lines X-X' and Y-Y' shown in <FIG> are. In <FIG>, the lines X-X' and Y-Y' are drawn to show cross sections of the <NUM>st section <NUM>-<NUM>, the <NUM>nd section <NUM>-<NUM> and the <NUM>th section <NUM>-<NUM> of the <NUM>nd dummy gate 424D and abutting elements.

Referring to <FIG>, the cross sections at the lines X-X' and Y-Y' still show the <NUM>rd isolation layer <NUM>, the <NUM>st and <NUM>nd dummy gates 414D, 424D and the ILD layer <NUM> enclosing these two dummy gates, similarly to the semiconductor device <NUM> shown in <FIG>. However, the <NUM>nd dummy gate 424D above the <NUM>nd nanosheet stack <NUM>, specifically, above the <NUM>rd isolation layer <NUM> on the <NUM>nd nanosheet stack <NUM>, is partially removed, and an additional ILD layer <NUM> is filled therein instead. Next, the top portion of the additional ILD layer <NUM> is planarized, for example, by CMP, to be coplanar with the top surfaces of the existing ILD layer <NUM> and the <NUM>nd dummy gate 424D.

<FIG> illustrate two cross-sectional views and a top plan view of a semiconductor device, respectively, in which a replacement metal gate is formed to surround nanosheet layers of a lower nanosheet stack, according to an embodiment.

<FIG> is a cross-sectional view of a semiconductor device <NUM> taken along a line X-X' in <FIG> which is a top plan view of the semiconductor device <NUM>, and <FIG> is a cross-sectional view of a semiconductor device <NUM> taken along a line Y-Y' in <FIG>. It is noted here that the lines X-X' and Y-Y' shown in <FIG> are drawn at the same positions at the lines X-X' and Y-Y' shown in <FIG>.

Referring to <FIG>, the <NUM>st section <NUM>-<NUM> is partially removed downward from top in order to form a hole <NUM> reaching the <NUM>st dummy gate 414D. Then, through this hole <NUM>, the <NUM>st dummy gate 414D and the <NUM>st sacrificial layers <NUM> of the <NUM>st nanosheet stack <NUM> are removed in their entirety. At this time, the <NUM>rd isolation layer <NUM> at the side of the <NUM>st nanosheet stack <NUM> is also removed. Next, the space including the hole <NUM> void from this removal operation is filled in with a <NUM>st replacement metal gate <NUM>. This removal operation may be performed by dry etching, wet etching, reactive ion etching (RIE) and/or a chemical oxide removal (COR) process. When the <NUM>st replacement metal gate <NUM> is filled in the void space, a hafnium (Hf) based high-k dielectric layer and a work function metal layer of Titanium (Ti), Tantalum (Ta) or their compound may be first deposited, and then, a conductor metal such as tungsten (W) or aluminum (Al) may be deposited to form the <NUM>st replacement metal gate <NUM> surrounding the <NUM>st nanosheet layers.

It is noted here that, as shown in <FIG>, the hole <NUM> formed in the <NUM>nd dummy gate 424D used for the above removal operation may be filled with the <NUM>st replacement metal gate <NUM> so that this part <NUM>-<NUM> of the <NUM>st replacement metal gate <NUM> may be used for connection with a replacement metal gate to surround the <NUM>nd nanosheet layers in the next step.

Although <FIG> show that only the <NUM>st section <NUM>-<NUM> of the second dummy gate 424D is partially removed to form the hole <NUM> for the above removal and filling operations, one or more of the <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM> may be used for the same purposes, according to embodiments. Thus, the <NUM>st replacement metal gate <NUM> may be partially formed by filling in one or more of holes or trenches formed at one or more of the <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM>, according to embodiments.

<FIG> illustrate two cross-sectional views and a top plan view of a semiconductor device, respectively, in which a replacement metal gate is formed to surround nanosheet layers of an upper nanosheet stack, according to an embodiment.

<FIG> is a cross-sectional view of a semiconductor device <NUM> taken along a line X-X' in <FIG> which is a top plan view of the semiconductor device <NUM>, and <FIG> is a cross-sectional view of a semiconductor device <NUM> taken along a line Y-Y' in <FIG>. It is noted here that the lines X-X' and Y-Y' shown in <FIG> are drawn at the same positions as the lines X-X' and Y-Y' shown in <FIG> and <FIG>.

Referring to <FIG>, the <NUM>nd dummy gate 424D is now completely removed along with the <NUM>nd sacrificial layers <NUM> of the <NUM>nd nanosheet stack <NUM> and the remaining <NUM>rd isolation layer <NUM>. Instead, a space generated from this removal operation is filled in with a <NUM>nd replacement metal gate <NUM>. Similar to the operations performed in the previous step, this removal operation may be performed by the RIE or COR process, and the <NUM>nd replacement metal gate formation is performed by first depositing an Hf based high-k dielectric layer and a work function metal layer of Ti, Ta or their compound followed by depositing a conductor metal such as tungsten (W) or aluminum (Al). It is noted here that the <NUM>st replacement metal gate <NUM> and the <NUM>nd replacement metal gate <NUM> may be insulated from each other by another isolation layer (not shown) including, for example, a high-k dielectric material.

<FIG> show that the <NUM>nd dummy gate 424D including the remaining <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM> of the <NUM>nd dummy gate 424D shown in <FIG> are removed in their entirety and replaced with the <NUM>nd replacement metal gate <NUM> in the semiconductor device <NUM>. Thus, the semiconductor device <NUM> now has the <NUM>nd replacement metal gate <NUM> at not only a section corresponding to the <NUM>th section <NUM>-<NUM> but also four sections corresponding to the <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM>. It is noted here that the section corresponding to the section <NUM>-<NUM> now includes the part <NUM>-<NUM> of the <NUM>st replacement metal gate <NUM> as well as a part of the <NUM>nd replacement metal gate <NUM> side by side as shown in <FIG>. According to embodiments, however, one or more of the sections corresponding to the <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM> may be formed to include a part of the <NUM>st replacement metal gate <NUM> as well as a part of the <NUM>nd replacement metal gate <NUM>. This structure of the semiconductor device <NUM> is different from that of the semiconductor device 300B shown in <FIG>.

Next, top portions of the <NUM>nd replacement metal gate <NUM> at the sections corresponding to the <NUM>st to <NUM>th sections <NUM>-<NUM> to <NUM>-<NUM> are recessed and filled in with respective metal patterns <NUM> for connection of the <NUM>nd replacement metal gate <NUM> with other circuit elements (not shown). A metal pattern filled in the section corresponding to the <NUM>st section <NUM>-<NUM> of the <NUM>nd dummy gate 424D connects the <NUM>nd replacement metal gate <NUM> with the part <NUM>-<NUM> of the <NUM>st replacement metal gate <NUM> filled in the hole <NUM> formed in the previous step of <FIG>. This connection of the <NUM>st and <NUM>nd replacement metal gates <NUM> and <NUM> may be implemented for a transistor having a common gate such as an inverter circuit, but may be omitted in other circuits.

Next, a <NUM>st cap dielectric material <NUM> may be formed on the metal patterns <NUM> and planarized according to an embodiment.

<FIG> illustrate two cross-sectional views and a top plan view of a semiconductor device, respectively, in which source/drain contact structures are formed, according to an embodiment.

<FIG> is a cross-sectional view of a semiconductor device <NUM> taken along a line X-X' in <FIG> which is a top plan view of the semiconductor device <NUM>, and <FIG> is a cross-sectional view of a semiconductor device <NUM> taken along a line Y-Y' in <FIG>. It is noted here that the lines X-X' and Y-Y' shown in <FIG> correspond to cross-sections at center lines of the semiconductor device <NUM> in the top plan view like the lines X-X' and Y-Y' of <FIG>.

Referring to <FIG>, the <NUM>st and <NUM>nd nanosheet layers 410C and 420C are now completely surrounded by the <NUM>st and <NUM>nd replacement metal gates <NUM> and <NUM>, respectively, to build a <NUM>st nanosheet transistor <NUM> and a <NUM>nd nanosheet transistor <NUM>. Further, <NUM>st to <NUM>th source/drain contact structures <NUM> to <NUM> are formed on the <NUM>st to <NUM>th source/drain regions <NUM> to <NUM>, respectively, to connect the <NUM>st and <NUM>nd nanosheet transistors <NUM> and <NUM> to other circuit elements or power sources. In addition, a gate metal contact <NUM>, a <NUM>nd cap dielectric material <NUM> and a gate contact structure <NUM> are formed above the <NUM>nd replacement metal gate <NUM>. An additional ILD layer <NUM> is also formed to insulate the 1st and <NUM>nd source/drain contact structures <NUM>, <NUM>, and the gate contact structure <NUM> from one another.

The steps of manufacturing the multi-stack nanosheet structure for the semiconductor device <NUM> with reference to <FIG> to <FIG> may not be performed in the aforementioned sequence. For example, although the <NUM>st and <NUM>nd replacement metal gates <NUM> and <NUM> are formed after the <NUM>st to <NUM>th source/drain regions <NUM> to <NUM> are formed, the <NUM>st and <NUM>nd replacement metal gates <NUM> and <NUM> may be formed before the <NUM>st to <NUM>th source/drain regions <NUM> to <NUM> are formed, according to embodiments. Further, the multi-stack nanosheet structure described above has the <NUM>st and <NUM>nd nanosheet stacks <NUM> and <NUM> with their channel sets perpendicularly crossing each other, the two channel sets may cross at different angles, according to embodiments.

Hence, the inventive concept is directed to multi-stack nanosheet structures and a method for manufacturing the same.

<FIG> illustrates a flowchart describing a method of manufacturing a semiconductor device having a multi-stack transistor structure with reference to <FIG> to 12A-12C, according to an embodiment.

In operation S10, a semiconductor device structure including a substrate, a <NUM>st transistor stack formed on the substrate, and a <NUM>nd transistor stack formed on the <NUM>st transistor stack is provided, where the <NUM>st transistor stack may include a plurality of <NUM>st channel structures, and the <NUM>nd transistor stack may include a plurality of <NUM>nd channel structures (see, e.g., <FIG>).

In operation S20, a <NUM>st dummy gate is formed to surround the <NUM>st transistor stack, and a <NUM>nd dummy gate is formed on the <NUM>st dummy gate to surround the <NUM>nd transistor stack and a top surface of the <NUM>nd transistor stack (see, e.g., <FIG>).

In operation S30, the <NUM>st dummy gate on at least parts of at least <NUM>st and <NUM>nd sides among four sides of the <NUM>st transistor stack is removed, and <NUM>st and <NUM>nd source/drain regions are formed on the <NUM>st and <NUM>nd sides of the <NUM>st transistor stack, respectively, where the <NUM>st dummy gate is removed (see, e.g., <FIG> and <FIG>).

In operation S40, the <NUM>nd dummy gate on at least parts of at least <NUM>rd and <NUM>th sides among four sides of the <NUM>nd transistor stack is removed, and then, <NUM>rd and <NUM>th source/drain regions are formed on the <NUM>rd and <NUM>th sides of the <NUM>nd transistor stack, respectively, where the <NUM>nd dummy gate is removed (see, e.g., <FIG> and <FIG>). Here, the <NUM>nd dummy gate may be removed before the <NUM>st dummy gate is removed, while the <NUM>st and <NUM>nd source/drain regions may be formed before the <NUM>rd and <NUM>th source/drain regions are formed (see, e.g., <FIG> and <FIG>).

In operation S50, the <NUM>st and <NUM>nd source/drain regions of the <NUM>st transistor stack are isolated from the <NUM>rd and <NUM>th source/drain regions by an isolation layer (see, e.g., <FIG>).

In operation S60, an ILD layer is formed on a top surface of the <NUM>nd transistor stack (see, e.g., <FIG>).

In operation S70, the remaining <NUM>st and <NUM>nd dummy gates are removed (see, e.g., <FIG> and <FIG>). At this time, the <NUM>st dummy gate may be first removed, and then, the <NUM>st dummy gate may be removed. Specifically, a hole may be formed at one of the at least one edge area of the <NUM>nd dummy gate to expose the <NUM>st dummy gate though the hole, and the <NUM>st dummy gate may be removed though the hole.

In operation S80, a space void by the removal of the <NUM>st and <NUM>nd dummy gates is filled out with <NUM>st and <NUM>nd replacement metal gates, respectively, to form <NUM>st and <NUM>nd gate structures surrounding the <NUM>st and <NUM>nd channel structures included in the <NUM>st and <NUM>nd transistor stacks, respectively (see, e.g., <FIG> and <FIG>). Specifically, the <NUM>st replacement metal gate may fill in the space through the hole formed in the previous operation to surround the <NUM>st channel structures to form the <NUM>st gate structure. This hole may also be filled with the <NUM>st replacement metal gate. And then, the <NUM>nd replacement metal gate may fill in the remaining space to surround the <NUM>nd channel structures to form the <NUM>nd gate structure. As a result of this operation, the <NUM>st to <NUM>th source/drain regions may be formed such that the <NUM>rd source/drain region does not overlap the <NUM>st source/drain region or the <NUM>nd source/drain region, and the <NUM>th source/drain region does not overlap the <NUM>st source/drain region or the <NUM>nd source/drain region.

In operation S90, a gate contact structure is formed on at least the <NUM>nd gate structure, and <NUM>st to <NUM>th source/drain contact structures are formed to land on the <NUM>st to <NUM>th source/drain regions, respectively. (see, e.g., <FIG>). By this method, the <NUM>st and <NUM>nd source/drain contact structures do not need to be bent to be connected to the <NUM>st and <NUM>nd source/drain regions, or do not need to land on side surfaces of the <NUM>st and <NUM>nd source/drain regions, respectively. Instead, the <NUM>st to <NUM>th source/drain contact structures may be formed to land on top surfaces of the <NUM>st to <NUM>th source/drain regions, respectively, from a structure, such as an upper metal pattern, formed above the <NUM>nd transistor stack.

<FIG> illustrates a schematic plan view of a semiconductor module according to an embodiment.

Referring to <FIG>, a semiconductor module <NUM> according to an embodiment may include a processor <NUM> and semiconductor devices <NUM> that are mounted on a module substrate <NUM>. The processor <NUM> and/or the semiconductor devices <NUM> include one or more multi-stack transistor structures described in the above embodiments.

<FIG> illustrates a schematic block diagram of an electronic system according to an embodiment.

Referring to <FIG>, an electronic system <NUM> in accordance with an embodiment may include a microprocessor <NUM>, a memory <NUM>, and a user interface <NUM> that perform data communication using a bus <NUM>. The microprocessor <NUM> may include a central processing unit (CPU) or an application processor (AP). The electronic system <NUM> may further include a random access memory (RAM) <NUM> in direct communication with the microprocessor <NUM>. The microprocessor <NUM> and/or the RAM <NUM> may be implemented in a single module or package. The user interface <NUM> may be used to input data to the electronic system <NUM>, or output data from the electronic system <NUM>. For example, the user interface <NUM> may include a keyboard, a touch pad, a touch screen, a mouse, a scanner, a voice detector, a liquid crystal display (LCD), a micro light-emitting device (LED), an organic light-emitting diode (OLED) device, an active-matrix light-emitting diode (AMOLED) device, a printer, a lighting, or various other input/output devices without limitation. The memory <NUM> may store operational codes of the microprocessor <NUM>, data processed by the microprocessor <NUM>, or data received from an external device. The memory <NUM> may include a memory controller, a hard disk, or a solid state drive (SSD).

At least the microprocessor <NUM>, the memory <NUM> and/or the RAM <NUM> in the electronic system <NUM> includes one or more multi-stack transistor structures described in the above embodiments.

Due to the above-described crossing multi-stack transistor structures having different channel directions, a semiconductor device structure may dispense with bent source/drain contact structures for lateral connection to source/drain regions of a lower-stack transistor structure, thereby enabling easier manufacturing of the semiconductor device structure having source/drain contact structures landing on top surfaces of corresponding source/drain regions. In addition, the disclosed structure enables reduction of parasitic capacitance between source/drain regions of a lower-stack (upper-stack) transistor structure and source/drain contact structures of a upper-stack (lower-stack).

Claim 1:
A semiconductor device comprising:
a substrate (<NUM>);
a <NUM>st transistor (<NUM>) formed above the substrate (<NUM>), and having a <NUM>st transistor stack comprising a plurality of <NUM>st channel structures (<NUM>), a <NUM>st gate structure (<NUM>) surrounding the <NUM>st channel structures (<NUM>), and <NUM>st and <NUM>nd source/drain regions (<NUM>, <NUM>) at both ends of the <NUM>st transistor stack in a <NUM>st channel length direction; and
a <NUM>nd transistor (<NUM>) formed above the <NUM>st transistor (<NUM>) in a vertical direction, and having a <NUM>nd transistor stack comprising a plurality of <NUM>nd channel structures (<NUM>), a <NUM>nd gate structure (<NUM>) surrounding the <NUM>nd channel structures (<NUM>), and <NUM>rd and <NUM>th source/drain regions (<NUM>, <NUM>) at both ends of the <NUM>nd transistor stack in a <NUM>nd channel length direction,
wherein the <NUM>rd source/drain region (<NUM>) does not vertically overlap the <NUM>st source/drain region (<NUM>) or the <NUM>nd source/drain region (<NUM>), and the <NUM>th source/drain region (<NUM>) does not vertically overlap the <NUM>st source/drain region (<NUM>) or the <NUM>nd source/drain region (<NUM>),
wherein the <NUM>st transistor stack is a <NUM>st nanosheet stack and the plurality of <NUM>st channel structures (<NUM>) comprises a plurality of <NUM>st nanosheet layers (<NUM>),
wherein the <NUM>nd transistor stack is a <NUM>nd nanosheet stack and the plurality of <NUM>nd channel structures (<NUM>) comprises a plurality of <NUM>nd nanosheet layers (<NUM>),
wherein widths of the <NUM>st nanosheet layers (<NUM>) in a <NUM>st channel width direction are the same, and widths of the <NUM>nd nanosheet layers (<NUM>) in a <NUM>nd channel width direction are the same,
wherein lengths of the <NUM>st nanosheet layers (<NUM>) in the <NUM>st channel length direction are the same, and lengths of the <NUM>nd nanosheet layers (<NUM>) in the <NUM>nd channel length direction are the same,
wherein the widths of the <NUM>st nanosheet layers (<NUM>) in the <NUM>st channel width direction are the same as the lengths of the <NUM>nd nanosheet layers (<NUM>) in the <NUM>nd channel length direction, and
wherein the <NUM>st and <NUM>nd channel length directions are different from each other.