Patent Description:
These systems may employ technologies such as code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiple access (OFDMA), or discrete Fourier transform-spread-OFDM (DFT-S-OFDM).

Wireless communications systems may use channel coding to increase reliability and robustness of wireless transmissions, particularly in the presence of noise or interference in wireless channels. One category of codes that may be suitable for channel coding includes LDPC codes, and improved systems and methods for using LDPC decoding may be desired.

<NPL> discusses some considerations for LDPC codes design, as well as the LDPC codes with flexibility of code block sizes, code rates and IR-HARQ. Document <NPL> discloses a partially decoding scheme for the rate compatible Raptor-like LDPC code, wherein BP decoding is carried out for the LDPC part and if the information has been recovered successfully, the decoding is stopped. Document <NPL> and document <NPL> are the documents of the prior art in the technical field in question.

The described techniques relate to improved methods, systems, devices, or apparatuses that support scheduling for low-density parity-check (LDPC) codes in layered decoding. Generally, the described techniques provide for decoding a message encoded as an LDPC code by completing a first number of partial decoding iterations and a second number of full decoding iterations. In some examples, a base graph of an LDPC code may include bit nodes and check nodes. The connections between a check node and the bit nodes may be used to determine a degree of a check node. In some examples of a base graph of LDPC codes, the first two bit nodes may be punctured. Thus, a check node connected to any one or both of the punctured bit nodes may be decoded less reliably than a check node not connected to the punctured bit nodes during a single decoding iteration. Additionally, the present techniques provide for decoding LDPC codes according to a scheduling order and for determining the scheduling order. The scheduling order is based on a degree associated with a check node. Lower degree check nodes are updated prior to updating higher degree check nodes. In some examples, check nodes associated with a portion of the base graph are decoded prior to decoding check nodes associated with the remaining portion of the base graph. The scheduling order is based on a number of punctured bits that a check node is connected to. In some cases, the determined scheduling order may also be based on an extrinsic information transfer (EXIT) chart optimization.

In the following, each of the described methods, apparatuses, systems, examples and aspects which does not correspond to the invention as defined in the claims is present for illustration purposes or to highlight specific aspects or features of the claims.

Wireless communications systems may use channel coding to increase reliability and robustness of wireless transmissions, particularly in the presence of noise or interference in wireless channels. In some examples, wireless communications systems may use various channel coding techniques, such as low-density parity-check (LDPC) coding, to overcome noisy channel conditions and interference. For example, wireless devices may send information bits to one another (e.g., from a base station to a user equipment (UE), or vice versa), which may be encoded to generate a codeword. In some cases, additional bits are included in an attempt to control errors caused by interference from unreliable or noisy channels. A receiver may then use the additional bits to recover the transmitted information bits.

An LDPC code may use a parity check matrix, where each row of the parity check matrix may introduce a parity check constraint on a codeword vector. For example, when using the parity check matrix to decode an LDPC codeword, for every row of the parity check matrix, the product of the codeword vector and each respective row of the parity check matrix should be equal to zero. The receiver may use this information to identify the information bits within the codeword. In other words, each row of the parity check matrix provides a respective parity check for individual bits of the codeword. In some cases, the parity check matrix may include a base graph.

The base graph includes bit nodes and check nodes. In some examples, each check node may be connected to a set of bit nodes. The connections between the check node and the bit nodes may be used to determine a degree of the check node. Using prior techniques, LDPC decoding may be performed by serially updating a first row of the base graph through the last row. Thus, a decoder employing traditional means of layered decoding may, during a first iteration, first update a first check node. Then, the decoder may move on to the second check node, and so on. This may lead to inefficient decoding, as each check node may be associated with a different degree, and lower degree check nodes being typically more easily resolved (through fewer iterations) than higher degree check nodes.

Further, in some examples of a base graph of LDPC codes, the first two bit nodes may be punctured. Thus, a check node connected to any one or both of the punctured bit nodes may be decoded less reliably than a check node not connected to the punctured bit nodes. In some examples, the conventional techniques of LDPC decoding may not account for connection of a check node to known punctured bit nodes. An LDPC decoder may benefit from the knowledge regarding known punctured bit nodes by altering a predetermined scheduling order. The altered scheduling order is based on a degree associated with a check node. The decoder is configured to update lower degree check nodes prior to updating the remaining check nodes of a base graph. The scheduling order is based on a number of punctured bits that a check node is connected to. In some cases, the scheduling order may be based on an extrinsic information transfer (EXIT) chart optimization. The decoder partially decodes a portion of the base graph during some initial iterations prior to applying full decoding iterations. The process of initially using partially decoding iterations, followed by the use of full decoding iterations, as well as an updated decoding schedule, may reduce decoding complexity and improve decoding efficiency.

Aspects of the disclosure are initially described in the context of a wireless communications system and efficient techniques for LDPC decoding. Aspects of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts that relate to decoding LDPC codes.

<FIG> illustrates an example of a wireless communications system <NUM> in accordance with various aspects of the present disclosure. The wireless communications system <NUM> includes base stations <NUM>, UEs <NUM>, and a core network <NUM>. In some examples, the wireless communications system <NUM> may be a Long Term Evolution (LTE) network, an LTE-Advanced (LTE-A) network, an LTE-A Pro network, or a New Radio (NR) network. In some cases, wireless communications system <NUM> may support enhanced broadband communications, ultra-reliable (e.g., mission critical) communications, low latency communications, or communications with low-cost and low-complexity devices.

In some examples, half-duplex communications may be performed at a reduced peak rate.

In one example, a base station <NUM> may use multiple antennas or antenna arrays to conduct beamforming operations for directional communications with a UE <NUM>. For instance, some signals (e.g., synchronization signals, reference signals, beam selection signals, or other control signals) may be transmitted by a base station <NUM> multiple times in different directions, which may include a signal being transmitted according to different beamforming weight sets associated with different directions of transmission. Transmissions in different beam directions may be used to identify (e.g., by the base station <NUM> or a receiving device, such as a UE <NUM>) a beam direction for subsequent transmission and/or reception by the base station <NUM>. Some signals, such as data signals associated with a particular receiving device, may be transmitted by a base station <NUM> in a single beam direction (e.g., a direction associated with the receiving device, such as a UE <NUM>). In some examples, the beam direction associated with transmissions along a single beam direction may be determined based at least in in part on a signal that was transmitted in different beam directions. For example, a UE <NUM> may receive one or more of the signals transmitted by the base station <NUM> in different directions, and the UE <NUM> may report to the base station <NUM> an indication of the signal it received with a highest signal quality, or an otherwise acceptable signal quality. Although these techniques are described with reference to signals transmitted in one or more directions by a base station <NUM>, a UE <NUM> may employ similar techniques for transmitting signals multiple times in different directions (e.g., for identifying a beam direction for subsequent transmission or reception by the UE <NUM>), or transmitting a signal in a single direction (e.g., for transmitting data to a receiving device).

For example, a receiving device may try multiple receive directions by receiving via different antenna subarrays, by processing received signals according to different antenna subarrays, by receiving according to different receive beamforming weight sets applied to signals received at a number of antenna elements of an antenna array, or by processing received signals according to different receive beamforming weight sets applied to signals received at a number of antenna elements of an antenna array, any of which may be referred to as "listening" according to different receive beams or receive directions. In some examples, a receiving device may use a single receive beam to receive along a single beam direction (e.g., when receiving a data signal). The single receive beam may be aligned in a beam direction determined based on listening according to different receive beam directions (e.g., a beam direction determined to have a highest signal strength, highest signal-to-noise ratio, or otherwise acceptable signal quality based on listening according to multiple beam directions).

In some cases a subframe may be the smallest scheduling unit of the wireless communications system <NUM>, and may be referred to as a transmission time interval (TTI).

Devices of the wireless communications system <NUM> (e.g., base stations <NUM> or UEs <NUM>) may have a hardware configuration that supports communications over a particular carrier bandwidth, or may be configurable to support communications over one of a set of carrier bandwidths. In some examples, the wireless communications system <NUM> may include base stations <NUM> and/or UEs that can support simultaneous communications via carriers associated with more than one different carrier bandwidth.

Wireless communications systems such as an NR system may utilize any combination of licensed, shared, and unlicensed spectrum bands, among others. The flexibility of eCC symbol duration and subcarrier spacing may allow for the use of eCC across multiple spectrums. In some examples, NR shared spectrum may increase spectrum utilization and spectral efficiency, specifically through dynamic vertical (e.g., across frequency) and horizontal (e.g., across time) sharing of resources.

A UE <NUM> or a base station <NUM> receives a message encoded as an LDPC code. The LDPC code includes a number of check nodes and a number of bit nodes. Upon receiving the LDPC code, the UE <NUM> or the base station <NUM> may identify a portion of the number of check nodes as low-degree check nodes having a degree that is less than a threshold. The UE <NUM> or the base station <NUM> may then identify an order for decoding the portion of the number of check nodes during a first number of decoding iterations. The UE <NUM> or the base station <NUM> applies the first number of decoding iterations to decoding the message. Only a portion of the number of check nodes is decoded during each of the first number of decoding iterations. The UE <NUM> or the base station <NUM> may then identify another order for decoding all of the number of check nodes during a second number of decoding iterations. The UE <NUM> or the base station <NUM> applies a second number of decoding iterations to decoding the message after the first number of decoding iterations are applied. All of the number of check nodes are decoded during each of the second number of decoding iterations. The UE <NUM> or the base station <NUM> decodes the message through completion of both the first number of decoding iterations and the second number of decoding iterations.

<FIG> illustrates an example of a diagram <NUM> that supports scheduling for LDPC codes in accordance with various aspects of the present disclosure. In some examples, diagram <NUM> includes a sparse parity check matrix <NUM> and an associated bipartite graph <NUM>. In some examples, the diagram <NUM> may implement aspects of wireless communication system <NUM>.

In some implementations, the bipartite graph <NUM> may include bit nodes b0 through b7 and check nodes c0 through c5. Each bit node b0-b7 may represent a corresponding column in the parity check matrix <NUM>, and each check node c0-c5 may represent a corresponding row in the parity check matrix <NUM>. The example parity check matrix <NUM> is not an actual LDPC parity check matrix, and is provided for illustrative purposes only. In the example of <FIG>, each "<NUM>" represents a bit involved in a parity check. Thus, for each received code word a=[a<NUM>, a<NUM>,. a<NUM>], the parity checks may be based on: <MAT> and so on. In some examples, the received code word may be represented by soft information, the values of which may be used to initialize a matrix according to the parity check matrix <NUM> for iterative decoding. For example, if the soft information generated from a received code word is [<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>], then an initialized matrix X according to the parity check matrix <NUM> would be: <MAT>.

In some examples, each connection between a bit node and a check node is referred to as an edge, and corresponds to a "<NUM>" in the parity check matrix. Because the parity check matrix <NUM> has a column weight of <NUM> and a row weight of <NUM>, each bit node is connected to three edges and each check node is connected to four edges. During the iterative decoding process, each check node may provide a bit node estimate to a bit node based on information from other related bit nodes. Each bit node, in return, may provide an estimate of its own value based on information from other related check nodes. The process may continue until all parity check equations are satisfied, indicating a valid decode, or until a maximum number of iterations is reached without satisfying all parity check equations, indicating a decoding failure. In some cases, the maximum number of iterations may be dynamically adjusted to control the rate at which a valid decode and a decoding failure are determined.

In some cases during decoding, a value may be assigned to each edge of the bipartite graph <NUM> that is representative of a channel value associated with a bit node to which the edge is connected. Check nodes may then be updated by accumulating the edge values according to a log-likelihood operation G: <MAT>.

Bit nodes may thereafter be updated with the update edge values by summing the edge values associated with the bit node. Thereafter, the system determines if all parity equations are satisfied or if a maximum number of iterations has been reached if all parity equations are not satisfied.

The interconnection between the bit nodes and check nodes in an LDPC code is typically pseudo-random. To facilitate high-speed decoding with reasonable complexity, a structure is often imparted in the code design so that the connections to the check nodes for a group of bit nodes are a linear translation of each other, (e.g., some or all of the parity equations may be expressed as a linear combination or a linear translation of one particular parity equation). For example, a parity check matrix may define the following sets of linearly shifted parity check equations (<NUM>) and (<NUM>): <MAT> <MAT> and so on. Thus, in the linearly shifted parity check equation (<NUM>), operands a<NUM>, a<NUM> and a<NUM> correspond to the first operand ap, operands a<NUM>, a<NUM> and a<NUM> correspond to the second operand ap+<NUM>, and so on.

<FIG> illustrates an example of a wireless communications system <NUM> that supports scheduling for LDPC codes in accordance with various aspects of the present disclosure. In some examples, wireless communications system <NUM> may implement aspects of wireless communication system <NUM>.

Wireless communications system <NUM> includes a base station <NUM>-a and UE <NUM>-a, which may be examples of the corresponding devices as described with reference to <FIG>. Wireless communications system <NUM> may illustrate an example of wireless devices that support scheduling for LDPC codes according to predetermined scheduling order.

Base station <NUM>-a and UE <NUM>-a may be in communication with each other, and may encode uplink and/or downlink transmissions using LDPC coding at a transmitter to transmit to a receiver. Accordingly, one or both UE <NUM>-a and base station <NUM>-a may include a receiver <NUM> used to receive LDPC codewords from the transmitting device, and these LDPC codewords may in turn be decoded at a decoder <NUM> of the receiving device, whether UE <NUM>-a or base station <NUM>-a. For example, time-frequency resources over which an LDPC encoded signal are sent may be identified at receiver <NUM>-a of UE <NUM>-a. UE <NUM>-a may demodulate the transmission over those time-frequency resources and, at decoder <NUM>-a, decode the demodulated transmission to obtain information bits that indicate the downlink transmission. The processes described as being performed by receiver <NUM>-a and decoder <NUM>-a of UE <NUM>-a may be similarly performed for uplink transmissions at base station <NUM>-a (e.g., by receiver <NUM>-b and decoder <NUM>-b, respectively).

To decode received LDPC codewords according to techniques described in the present disclosure, decoder <NUM>-a may use a parity check matrix <NUM>, which may be a matrix having dimensions of Nchecks rows and N columns. In such cases, N may correspond to a length of an LDPC codeword and Nchecks may correspond to a number of check bits, or parity bits, used to decode a codeword. Parity check matrix <NUM> may include K systematic bits <NUM> (e.g., a sequence of information bits) and N - K parity bits <NUM>.

In some cases, as previously discussed, the parity check matrix <NUM> may be representative of a base graph used for LDPC decoding, where the parity check matrix <NUM> may include a high-rate core graph in addition to a degree one extension (e.g., used for HARQ or incremental redundancy (IR)-HARQ). A degree of a check node in parity check matrix <NUM> refers to the number of bit nodes (columns) attached to a check node (row) in parity check matrix <NUM>. Thus, a degree one of a check node corresponds to a connection between the check node and one bit node. In some examples, certain columns within the parity check matrix <NUM> may include entries corresponding to nodes that have various degrees. The parity check matrix <NUM> also includes one or more punctured bit columns (e.g., corresponding to bits that are removed from the codeword).

Using an LDPC decoding algorithm, a decoder <NUM>-a receives a message encoded as an LDPC code that includes a number of check nodes and a number of bit nodes, apply a number of partial decoding iterations to decode the message, apply a number of full decoding iterations to decode the message after the partial decoding iterations are applied, and decode the message through completion of both partial decoding iterations and the full decoding iterations.

<FIG> illustrates an example of a diagram <NUM> that supports scheduling for LDPC codes in accordance with various aspects of the present disclosure. In some examples, diagram <NUM> may include a base graph <NUM>.

In some implementations, the base graph <NUM> may include bit nodes <NUM> A through AI and check nodes <NUM><NUM> through <NUM>. As depicted in the example of <FIG>, each bit node <NUM> represents a corresponding column in the base graph <NUM>, and each check node <NUM> represents a corresponding row in the base graph <NUM>. As previously discussed, the base graph <NUM> may be an example of a parity check matrix. The example base graph <NUM> is not an actual LDPC parity check matrix, and is provided for illustrative purposes only.

In some examples, each check node <NUM> may be connected to a set of bit nodes <NUM>. For example, a message may be delivered using the set of bit nodes <NUM>. In some cases, the message may include a code word as well as one or more parity bits to protect the message. In some examples, each "<NUM>" in the base graph <NUM> may represent a connection between a check node <NUM> and a bit node <NUM>. Referring to <FIG>, the check node "<NUM>" has connections with bit nodes <NUM> "A," "B," "C," "D," "F," and "G. " Although not shown in <FIG>, the base graph <NUM> may include more bit nodes <NUM>. Similarly, the connections between the check node "<NUM>" and the bit nodes <NUM> may be different. In conventional techniques, a decoder may decode a base graph <NUM> from the first row to the last row. For example, a decoder may be configured to decode all columns associated with a first row. The decoder may then move on to decode all columns associated with a second row, and so on. With respect to the example of <FIG>, a decoder may first decode all bit nodes <NUM> connected to the check node "<NUM>" during a first iteration. After the first iteration, the decoder may decode all bit nodes <NUM> connected to the check node "<NUM>. " During the third iteration, the decoder may further decode all bit nodes <NUM> connected to the check node "<NUM>. " Thus, conventional techniques allow a decoder to serially decode a base graph <NUM>. However, this may lead to inefficient decoding. This is because a degree or number of degrees associated with each check node <NUM> may be different from one another.

In one example, a degree associated with a check node <NUM> may be determined based on a number of "<NUM>" associated with that check node <NUM>. In the example of <FIG>, the degree of check node "<NUM>" is greater than or equal to <NUM>. That is, a minimum degree associated with the check node "<NUM>" is <NUM>. Similarly, the degree of check node "<NUM>" is greater than or equal to <NUM>, the degree of check node "<NUM>" is greater than or equal to <NUM>, and the degree of check node "<NUM>" is greater than or equal to <NUM>. Further, the degree of check node "<NUM>" is greater than or equal to <NUM>, the degree of check node "<NUM>" is greater than or equal to <NUM>, the degree of check node "<NUM>" is greater than or equal to <NUM>, the degree of check node "<NUM>" is greater than or equal to <NUM>, the degree of check node "<NUM>" is greater than or equal to <NUM>, the degree of check node "<NUM>" is greater than or equal to <NUM>, the degree of check node "<NUM>" is greater than or equal to <NUM>, the degree of check node "<NUM>" is greater than or equal to <NUM>, and the degree of check node "<NUM>" is greater than or equal to <NUM>. In some examples, the degree associated with a check node <NUM> is greater than the previously calculated value, when a check node <NUM> is connected to more bit nodes <NUM> (not shown).

In some implementations, a first row of the base graph <NUM> may be denser than a second row of the base graph <NUM>. For example, the first four rows of the base graph <NUM> may be considered as dense. As previously discussed, a degree associated with the check nodes "<NUM>," "<NUM>," "<NUM>," and "<NUM>" are <NUM>, <NUM>, <NUM>, and <NUM> respectively. This means that the first four rows of the base graph <NUM> are denser than the remaining rows. In some examples, a denser portion of the base graph <NUM> may be referred to as a core portion <NUM>. In some cases, an output of a check node <NUM> may depend on the least reliable message of one or more incoming messages. More specifically, if one message is erased from a stream of incoming messages associated with a check node <NUM>, then the output from that check node <NUM> may not be reliable. As a result, if a check node <NUM> is connected to a higher number of bit nodes <NUM>, then the output message from decoding that check node <NUM> may not be reliable. On the other hand, if a check node <NUM> is connected to one bit node <NUM>, then the outgoing message associated with that check node <NUM> is correct if the message from one bit node <NUM> is correctly decoded. Thus, a check node <NUM> having a lower degree may have higher reliability than a check node <NUM> having a higher degree. In other words, a check node <NUM> connected to more bit nodes <NUM> may have lesser reliability than a check node <NUM> connected to lesser number of bit nodes <NUM>. Under such circumstances, decoding using a natural order (e.g., decoding serially from row <NUM> to row <NUM>), may result in inefficient decoding.

In some examples, the conventional techniques of decoding may result in updating a core portion of the base graph <NUM> during the first several iterations. Thus, there may be a need for decoding the base graph <NUM> according to a predetermined scheduling order. The scheduling order of the invention as claimed is based on a degree associated with a check node. In some examples, the base graph <NUM> is more efficiently decoded by updating lower degree check nodes <NUM> (or, by check nodes belonging to a non-core portion of the base graph <NUM>) prior to updating the remaining portion of the base graph <NUM>. Further, the updated messaged from the non-core portion of the base graph <NUM> may be used to improve the reliability of updated the core portion <NUM> of the base graph <NUM>. Thus, the method of partial decoding prior to decoding the entire base graph <NUM> may reduce the decoding complexity.

In some examples of LDPC codes, the first two bit nodes <NUM> may be punctured. In the example of <FIG>, the bit node "A" and the bit node "B" may be punctured. Thus, a check node <NUM> connected to any one (or both) of the punctured bit nodes <NUM> may be less reliable than a check node <NUM> not connected to the punctured bit nodes <NUM>. As depicted in <FIG>, the check node "<NUM>" has one connection in the first two bit nodes <NUM>. Further, check node "<NUM>" also has one connection in the first two bit nodes <NUM>. Such check nodes <NUM> connected to one of the two punctured bits may be referred to as type <NUM> check nodes <NUM>. Additionally, a check node <NUM> connected to both punctured bits may be referred to as a type <NUM> check node <NUM>. In the example of <FIG>, check node "<NUM>" has two connections in the first two bit nodes <NUM>. More specifically, as depicted in the <FIG>, the check node "<NUM>" is connected to the first bit node "A" and the second bit node "B. " Thus, check nodes "<NUM>" and "<NUM>" in the example of <FIG> may be referred to as type <NUM> check node and check node "<NUM>" in the example of <FIG> may be referred to as a type <NUM> check node. In some examples, a scheduling order may be based on a type of a check node <NUM>. In some cases, it is more efficient to update type <NUM> check nodes <NUM> prior to updating type <NUM> check nodes.

According to the invention as claimed, a decoding scheme to decode the base graph <NUM> includes a partial decoding of check nodes <NUM> associated with a predetermined scheduling order. For example, a decoder may partially decode check nodes <NUM> associated with degrees less than a predefined threshold. In some cases, the decoder may perform a full decoding of all the check nodes <NUM> according to a predetermined scheduling order. In some cases, the predetermined scheduling order may be based on a degree of a check node <NUM>. For example, the predetermined scheduling order may range from a lowest degree to a highest degree. That is, a check node <NUM> associated with the lowest degree may be updated first, followed by a check node <NUM> associated with the next lowest degree. The predetermined scheduling order is based on a number of punctured bits that a check node <NUM> is connected to. As an example, a decoder may be configured to update type <NUM> check nodes <NUM> prior to updating type <NUM> check nodes. In further implementations, the predetermined scheduling order may be based on an EXIT chart optimization. In some cases, the EXIT chart optimization may be used to determine a check node <NUM> which minimizes bit error rate of the code. Thus, the decoding scheme described herein may result in performance enhancement while significantly saving on decoding complexity.

<FIG> illustrates an example of a scheduling order <NUM> that supports scheduling for LDPC codes in accordance with various aspects of the present disclosure, not falling under the scope of the claimed invention. In some examples, scheduling order <NUM> may implement aspects of wireless communication system <NUM>.

<FIG> describes a scheduling order <NUM> of check nodes of the base graph <NUM> (as described with reference to <FIG>) according to conventional techniques. The conventional technique allows a decoder to serially decode the check nodes of a base graph. Referring back to <FIG>, the base graph <NUM> may include bit nodes <NUM> A through AI and check nodes <NUM><NUM> through <NUM>. As previously discussed, each check node <NUM> of the base graph <NUM> may be connected to a set of bit nodes <NUM>. In the example of <FIG>, each "<NUM>" in the base graph <NUM> represents a connection between a check node <NUM> and a bit node <NUM>. According to <FIG>, the check node "<NUM>" has connections with bit nodes <NUM> "A," "B," "C," "D," "F," and "G. " Similarly, the check node "<NUM>" has connections with bit nodes <NUM> "A," "C," "D," "E," "F," and "H," the check node "<NUM>" has connections with bit nodes <NUM> "A," "B," "C," "E," "F," "G," and "H," the check node "<NUM>" has connections with bit nodes <NUM> "A," "B," "D," "E," "G," and "H," and so on.

As previously discussed, a degree associated with a check node is determined based on a number of "<NUM>" associated with that check node. Referring to the base graph <NUM> of <FIG>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, and the degree of check node "<NUM>" is <NUM>. In some examples, the degree associated with a check node <NUM> may be greater than the previously calculated value in cases where a check node is connected to more bit nodes (more than the number of bit nodes shown in <FIG>).

In the example of <FIG>, during a first iteration, a decoder may decode a base graph from the first row to the last row. For example, a decoder may be configured to decode all columns associated with check node "<NUM>. " Then the decoder may decode all columns associated with a check node "<NUM>. " Similarly, as described in <FIG>, using conventional techniques, the decoder may sequentially decode check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," and check node "<NUM>. " Thus, conventional techniques allow a decoder to serially decode all check nodes of a base graph (such as base graph <NUM> of <FIG>). However, as previously discussed, this may lead to inefficient decoding, as a first row of a base graph may be denser than a second row of the base graph. With reference to <FIG>, a first row associated with check node <NUM>, a second row associated with check node <NUM>, a third row associated with check node <NUM>, and a fourth row associated with check node <NUM>, may be denser than the remaining rows of the base graph <NUM>. In some examples, a check node connected to more bit nodes may have lesser reliability than a check node connected to lesser number of bit nodes. Thus, decoding using conventional techniques as described with reference to <FIG> (i.e., decoding serially from check node <NUM> to check node <NUM>), may result in inefficient decoding.

The scheduling order <NUM> is provided as an example, not falling under the scope of the claimed invention, based on the example base graph <NUM> of <FIG>.

<FIG> illustrates an example of a scheduling order <NUM> that supports scheduling for LDPC codes in accordance with various aspects of the present invention as claimed. In some examples, scheduling order <NUM> may implement aspects of wireless communication system <NUM>.

<FIG> describes a scheduling order <NUM> of check nodes of the base graph <NUM> (as described with reference to <FIG>) according to techniques described in the present disclosure. The decoding scheme described in the present disclosure allows a decoder to decode a base graph by partial decoding of check nodes using a predetermined scheduling order. Then, the decoder performs a full decoding of all the check nodes according to a predetermined scheduling order.

Referring back to <FIG>, the base graph <NUM> may include bit nodes <NUM> A through AI and check nodes <NUM><NUM> through <NUM>. As previously discussed, each check node <NUM> of the base graph <NUM> may be connected to a set of bit nodes <NUM>. In the example of <FIG>, each "<NUM>" in the base graph <NUM> represents a connection between a check node <NUM> and a bit node <NUM>. According to <FIG>, the check node "<NUM>" has connections with bit nodes <NUM> "A," "B," "C," "D," "F," and "G. " Similarly, the check node "<NUM>" has connections with bit nodes <NUM> "A," "C," "D," "E," "F," and "H," the check node "<NUM>" has connections with bit nodes <NUM> "A," "B," "C," "E," "F," "G," and "H," the check node "<NUM>" has connections with bit nodes <NUM> "A," "B," "D," "E," "G," and "H," and so on.

Further, in the example of <FIG>, the bit node "A" and the bit node "B" are punctured. In some embodiments, a check node connected to any one of the punctured bit nodes or both of the punctured bit nodes may be less reliable than a check node not connected to the punctured bit nodes. In some implementations, check nodes connected to one of the two punctured bits may be referred to as type <NUM> check nodes. Additionally, check nodes connected to both punctured bits may be referred to as type <NUM> check nodes. Referring to <FIG>, the check node "<NUM>" has a connection with the bit node "A" and does not have a connection with the bit node "B. " Additionally, check node "<NUM>" has a connection with the bit node "B" but does not have a connection with bit node "A. " Thus, the check node "<NUM>" and the check node "<NUM>" each have one connection with a punctured bit node and may be referred to as type <NUM> check nodes. Further, the check node "<NUM>" has two connections in the first two bit nodes <NUM>. More specifically, as depicted in the <FIG>, the check node "<NUM>" is connected to the first bit node "A" and the second bit node "B. " Thus, check node "<NUM>" may be referred to as a type <NUM> check node.

Referring back to <FIG>, a scheduling order may be based on a type of a check node. In some cases, the scheduling order may also be based on a degree of a check node. For example, check node may be updated according to an ascending degree associated with the check node. In some other cases, the scheduling order may configure a decoder to update type <NUM> check nodes prior to updating type <NUM> check nodes. In some alternative cases, the order may configure a decoder to update type <NUM> check nodes prior to updating type <NUM> check nodes. In further implementations, the scheduling order may be based on an EXIT chart optimization.

Referring to the base graph <NUM> of <FIG>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, and the degree of check node "<NUM>" is <NUM>. In some examples, the degree associated with a check node may be greater than the previously calculated value when a check node is connected to more bit nodes (e.g., more than the number of bit nodes shown in <FIG>).

In the example of <FIG>, during a first iteration <NUM>, a decoder may begin decoding a base graph from check node "<NUM>. " For example, a decoder may decode check node "<NUM>," followed by check node "<NUM>," check node "<NUM>," check node "<NUM>," and check node "<NUM>. " After completing updating check node <NUM>, the decoder may advance to the second iteration <NUM>. More specifically, as described in the scheduling order of <FIG>, "-<NUM>" indicates the decoder did not update any check node during that instance. For example, the decoder may perform a partial decoding during the first iteration <NUM>. Similarly, during the second iteration <NUM>, the decoder may decode check node "<NUM>," followed by check node "<NUM>," check node "<NUM>," check node "<NUM>," and check node "<NUM>. " After completing updating check node <NUM>, the decoder may advance to the third iteration <NUM>. As described in the example of <FIG>, the first iteration <NUM>, the second iteration <NUM>, the third iteration <NUM>, and the fourth iteration <NUM> are partial iterations. The decoder may use values of the updated check nodes from one iteration during a following iteration.

Further, during a fifth iteration <NUM>, a decoder may update check node "<NUM>," followed by check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," and check node "<NUM>. " After completing updating check node "<NUM>," the decoder may advance to the sixth iteration <NUM>. Further, during the sixth iteration <NUM>, the decoder may update check node "<NUM>," followed by check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," and check node "<NUM>. " After completing updating check node <NUM>, the decoder may advance to the seventh iteration <NUM>. As described in the example of <FIG>, the fifth iteration <NUM>, the sixth iteration <NUM>, the seventh iteration <NUM>, the eighth iteration <NUM>, the ninth iteration <NUM>, the tenth iteration <NUM>, the eleventh iteration <NUM>, and the twelfth iteration <NUM> are full iterations. As described in the example of <FIG>, the decoder is configured to update type <NUM> check nodes prior to updating type <NUM> check nodes. For example, in <FIG>, the decoder updates check node "<NUM>" prior to updating check node "<NUM>" and check node "<NUM>.

The scheduling order <NUM> is provided as an example based on the example base graph <NUM> of <FIG>.

As previously described with reference to <FIG>, the base graph <NUM> may include bit nodes <NUM> A through AI and check nodes <NUM><NUM> through <NUM>. Each check node <NUM> of the base graph <NUM> may be connected to a set of bit nodes <NUM>. In the example of <FIG>, each "<NUM>" in the base graph <NUM> represents a connection between a check node <NUM> and a bit node <NUM>. Further, in the example of <FIG>, the bit node "A" and the bit node "B" are punctured. As previously discussed, check nodes connected to one of the two punctured bits may be referred to as type <NUM> check nodes, and check nodes connected to both punctured bits may be referred to as type <NUM> check nodes. Referring <FIG>, the check node "<NUM>" has a connection with the bit node "A" and does not have a connection with the bit node "B. " Additionally, check node "<NUM>" has a connection with the bit nodes "B" but does not have a connection with bit node "A. " Thus, the check node "<NUM>" and the check node "<NUM>" each have one connection with a punctured bit node and may be referred to as type <NUM> check nodes. Further, the check node "<NUM>" has two connections in the first two bit nodes <NUM>. More specifically, as depicted in the <FIG>, the check node "<NUM>" is connected to the first bit node "A" and the second bit node "B. " Thus, check node "<NUM>" may be referred to as a type <NUM> check node.

Referring back to <FIG>, the scheduling order for updating one or more check nodes is based on a type of a check node. In some cases, the scheduling order may also be based on a degree of a check node. In some cases, the degree of a check node may be based on a number of bit nodes it is connected to. As discussed with reference to <FIG>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, the degree of check node "<NUM>" is <NUM>, and the degree of check node "<NUM>" is <NUM>. In some examples, the degree associated with a check node may be greater than the previously calculated value, when a check node is connected to more bit nodes (more than the number of bit nodes shown in <FIG>). In some cases, a check node may be updated according to an ascending degree associated with the check node. In some other cases, the scheduling order may configure a decoder to update type <NUM> check nodes prior to updating type <NUM> check nodes. In some cases, the scheduling order may be based on an EXIT chart optimization.

In the example of <FIG>, during a first iteration <NUM>, a decoder may begin decoding a base graph from check node "<NUM>. " For example, a decoder may decode check node "<NUM>," followed by check node "<NUM>," check node "<NUM>," check node "<NUM>," and check node "<NUM>. " After completing updating check node <NUM>, the decoder may advance to the second iteration <NUM>. In some cases, "-<NUM>" as described in the scheduling order of <FIG>, may indicate that there are no more check nodes available for the decoder to update. For example, the decoder may perform a partial decoding during the first iteration <NUM>. Similarly, during the second iteration <NUM>, the decoder may decode check node "<NUM>," followed by check node "<NUM>," check node "<NUM>," check node "<NUM>," and check node "<NUM>. " After completing updating check node "<NUM>," the decoder may advance to the third iteration <NUM>. As described in the example of <FIG>, the first iteration <NUM>, the second iteration <NUM>, the third iteration <NUM>, and the fourth iteration <NUM> are partial iterations. The decoder may be configured to use values the updated check nodes from one iteration during a following iteration.

Further, during a fifth iteration <NUM>, the decoder may update check node "<NUM>," followed by check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," and check node "<NUM>. " After completing updating check node "<NUM>," the decoder may advance to the sixth iteration <NUM>. As described in the example of <FIG> during the sixth iteration <NUM>, the decoder may update check node "<NUM>," followed by check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," check node "<NUM>," and check node "<NUM>. " After completing updating check node <NUM>, the decoder may advance to the seventh iteration <NUM>. As described in the example of <FIG>, the fifth iteration <NUM>, the sixth iteration <NUM>, the seventh iteration <NUM>, the eighth iteration <NUM>, the ninth iteration <NUM>, the tenth iteration <NUM>, the eleventh iteration <NUM>, and the twelfth iteration <NUM> are full iterations. As described in the example of <FIG>, the decoder may update type <NUM> check nodes prior to updating type <NUM> check nodes. For example, in <FIG>, the decoder may update check node "<NUM>" and check node "<NUM>" prior to updating check node "<NUM>.

<FIG> shows a block diagram <NUM> of a wireless device <NUM> that supports scheduling for LDPC codes in accordance with aspects of the present disclosure. Wireless device <NUM> may be an example of aspects of a user equipment (UE) <NUM> or base station <NUM> as described herein. Wireless device <NUM> may include receiver <NUM>, communications manager <NUM>, and transmitter <NUM>. Wireless device <NUM> may also include a processor. Each of these components may be in communication with one another (e.g., via one or more buses).

Receiver <NUM> may receive information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, and information related to scheduling for LDPC codes, etc.). Information may be passed on to other components of the device. The receiver <NUM> may be an example of aspects of the transceiver <NUM> described with reference to <FIG>. The receiver <NUM> may utilize a single antenna or a set of antennas. Receiver <NUM> may receive a message encoded as an LDPC code that includes a set of check nodes and a set of bit nodes.

Communications manager <NUM> may be an example of aspects of the communications manager <NUM> described with reference to <FIG>. Communications manager <NUM> and/or at least some of its various sub-components may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions of the communications manager <NUM> and/or at least some of its various sub-components may be executed by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. The communications manager <NUM> and/or at least some of its various sub-components may be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations by one or more physical devices. In some examples, communications manager <NUM> and/or at least some of its various sub-components may be a separate and distinct component in accordance with various aspects of the present disclosure. In other examples, communications manager <NUM> and/or at least some of its various sub-components may be combined with one or more other hardware components, including but not limited to an I/O component, a transceiver, a network server, another computing device, one or more other components described in the present disclosure, or a combination thereof in accordance with various aspects of the present disclosure.

Communications manager <NUM> applies a first number of decoding iterations to decoding the message, where only a portion of the set of check nodes is decoded during each of the first number of decoding iterations. Communications manager <NUM> further applies a second number of decoding iterations to decoding the message after the first number of decoding iterations are applied, where all of the set of check nodes are decoded during each of the second number of decoding iterations. Communications manager <NUM> then decodes the message through completion of both the first number of decoding iterations and the second number of decoding iterations.

<FIG> shows a block diagram <NUM> of a wireless device <NUM> that supports scheduling for LDPC codes in accordance with aspects of the present disclosure. Wireless device <NUM> may be an example of aspects of a wireless device <NUM> or a UE <NUM> or base station <NUM> as described with reference to <FIG>. Wireless device <NUM> may include receiver <NUM>, communications manager <NUM>, and transmitter <NUM>. Wireless device <NUM> may also include a processor. Each of these components may be in communication with one another (e.g., via one or more buses).

Receiver <NUM> may receive information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, and information related to scheduling for LDPC codes, etc.). Information may be passed on to other components of the device. The receiver <NUM> may be an example of aspects of the transceiver <NUM> described with reference to <FIG>. The receiver <NUM> may utilize a single antenna or a set of antennas.

Communications manager <NUM> may be an example of aspects of the communications manager <NUM> described with reference to <FIG>. Communications manager <NUM> may also include decoding component <NUM>.

Decoding component <NUM> applies a first number of decoding iterations to decoding the message, where only a portion of the set of check nodes is decoded during each of the first number of decoding iterations. Decoding component <NUM> also applies a second number of decoding iterations to decoding the message after the first number of decoding iterations are applied, where all of the set of check nodes are decoded during each of the second number of decoding iterations. The message is decoded through completion of both the first number of decoding iterations and the second number of decoding iterations.

<FIG> shows a block diagram <NUM> of a communications manager <NUM> that supports scheduling for LDPC codes in accordance with aspects of the present disclosure. The communications manager <NUM> may be an example of aspects of a communications manager <NUM>, a communications manager <NUM>, or a communications manager <NUM> described with reference to <FIG>, <FIG>, and <FIG>. The communications manager <NUM> may include decoding component <NUM>, check node component <NUM>, order component <NUM>, reordering component <NUM>, scheduling component <NUM>, and punctured bits component <NUM>. Each of these modules may communicate, directly or indirectly, with one another (e.g., via one or more buses).

Check node component <NUM> may identify the portion of the set of check nodes as low-degree check nodes having a degree that is less than a threshold.

Order component <NUM> may identify an order for decoding the portion of the set of check nodes during the first number of decoding iterations, where the first number of decoding iterations are applied according to the identified order. Order component <NUM> may also identify an order for decoding all of the set of check nodes during the second number of decoding iterations, where the second number of decoding iterations are applied according to the identified order.

Reordering component <NUM> reorders the set of check nodes for decoding during one or both of the first number of decoding iterations and the second number of decoding iterations based on a scheduling configuration. Reordering component <NUM> may also reorder the set of check nodes for decoding during one or both of the first number of decoding iterations and the second number of decoding iterations based on a degree of each of the set of check nodes. Reordering component <NUM> reorders the set of check nodes for decoding during one or both of the first number of decoding iterations and the second number of decoding iterations based on the number of punctured bits connected to each of the set of check nodes. Additionally, reordering component <NUM> may reorder the set of check nodes for decoding during one or both of the first number of decoding iterations and the second number of decoding iterations based on an EXIT chart optimization.

Scheduling component <NUM> may identify the scheduling configuration based on a rate of the LDPC code and select the scheduling configuration from a set of scheduling configurations which vary uniformly from supporting a high rate of the LDPC code to a low rate of the LDPC code.

Punctured bits component <NUM> determines a number of punctured bits connected to each of the set of check nodes. In some cases, the number of punctured bits is limited to a number of punctured bits within a range of the set of bit nodes. In some cases, the number of punctured bits is limited to the number of punctured bits within a first bit node and a second bit node of the set of bit nodes, where a number of bits in each bit node is based on a lifting size of the LDPC code.

<FIG> shows a diagram of a system <NUM> including a device <NUM> that supports scheduling for LDPC codes in accordance with aspects of the present disclosure. Device <NUM> may be an example of or include the components of wireless device <NUM>, wireless device <NUM>, or a UE <NUM> as described herein, e.g., with reference to <FIG> and <FIG>. Device <NUM> may include components for bi-directional voice and data communications including components for transmitting and receiving communications, including UE communications manager <NUM>, processor <NUM>, memory <NUM>, software <NUM>, transceiver <NUM>, antenna <NUM>, and I/O controller <NUM>. These components may be coupled with one or more buses (e.g., bus <NUM>). Device <NUM> may communicate wirelessly with one or more base stations <NUM>.

Processor <NUM> may include an intelligent hardware device, (e.g., a general-purpose processor, a DSP, a central processing unit (CPU), a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some cases, processor <NUM> may be configured to operate a memory array using a memory controller. In other cases, a memory controller may be integrated into processor <NUM>. Processor <NUM> may be configured to execute computer-readable instructions stored in a memory to perform various functions (e.g., functions or tasks supporting scheduling for LDPC codes).

Memory <NUM> may include random-access memory (RAM) and read-only memory (ROM).

Software <NUM> may include code to implement aspects of the present disclosure, including code to support scheduling for LDPC codes. Software <NUM> may be stored in a non-transitory computer-readable medium such as system memory or other memory. In some cases, the software <NUM> may not be directly executable by the processor but may cause a computer (e.g., when compiled and executed) to perform functions described herein.

Transceiver <NUM> may communicate bi-directionally, via one or more antennas, wired, or wireless links as described herein.

<FIG> shows a diagram of a system <NUM> including a device <NUM> that supports scheduling for LDPC codes in accordance with aspects of the present disclosure. Device <NUM> may be an example of or include the components of wireless device <NUM>, wireless device <NUM>, or a base station <NUM> as described herein, e.g., with reference to <FIG> and <FIG>. Device <NUM> may include components for bi-directional voice and data communications including components for transmitting and receiving communications, including base station communications manager <NUM>, processor <NUM>, memory <NUM>, software <NUM>, transceiver <NUM>, antenna <NUM>, network communications manager <NUM>, and inter-station communications manager <NUM>. These components may be coupled with one or more buses (e.g., bus <NUM>). Device <NUM> may communicate wirelessly with one or more UEs <NUM>.

Processor <NUM> may include an intelligent hardware device, (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some cases, processor <NUM> may be configured to operate a memory array using a memory controller. In other cases, a memory controller may be integrated into processor <NUM>. Processor <NUM> may be configured to execute computer-readable instructions stored in a memory to perform various functions (e.g., functions or tasks supporting scheduling for LDPC codes).

Inter-station communications manager <NUM> may manage communications with other base station <NUM>, and may include a controller or scheduler for controlling communications with UEs <NUM> in cooperation with other base stations <NUM>. In some examples, inter-station communications manager <NUM> may provide an X2 interface within an Long Term Evolution (LTE)/LTE-A wireless communication network technology to provide communication between base stations <NUM>.

<FIG> shows a flowchart illustrating a method <NUM> for scheduling for LDPC codes in accordance with aspects of the present disclosure. The operations of method <NUM> may be implemented by a UE <NUM> or base station <NUM> or its components as described herein. For example, the operations of method <NUM> may be performed by a communications manager as described with reference to <FIG>. In some examples, a UE <NUM> or base station <NUM> may execute a set of codes to control the functional elements of the device to perform the functions described herein. Additionally or alternatively, the UE <NUM> or base station <NUM> may perform aspects of the functions described herein using special-purpose hardware.

At <NUM> the UE <NUM> or base station <NUM> receives a message encoded as an LDPC code that includes a number of check nodes and a number of bit nodes. The operations of <NUM> is performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed by a receiver as described with reference to <FIG>.

At <NUM> the UE <NUM> or base station <NUM> applies a first number of decoding iterations to decoding the message, where only a portion of the number of check nodes is decoded during each of the first number of decoding iterations. The operations of <NUM> is performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> is performed by a decoding component as described with reference to <FIG>.

At <NUM> the UE <NUM> or base station <NUM> applies a second number of decoding iterations to decoding the message after the first number of decoding iterations are applied, where all of the number of check nodes are decoded during each of the second number of decoding iterations. The operations of <NUM> is performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> is performed by a decoding component as described with reference to <FIG>.

At <NUM> the UE <NUM> or base station <NUM> decodes the message through completion of both the first number of decoding iterations and the second number of decoding iterations. The operations of <NUM> is performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> is performed by a decoding component as described with reference to <FIG>.

At <NUM> the UE <NUM> or base station <NUM> may receive a message encoded as an LDPC code that includes a number of check nodes and a number of bit nodes. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed by a receiver as described with reference to <FIG>.

At <NUM> the UE <NUM> or base station <NUM> identifies an order for decoding the portion of the number of check nodes during a first number of decoding iterations. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed by an order component as described with reference to <FIG>.

At <NUM> the UE <NUM> or base station <NUM> applies the first number of decoding iterations to decoding the message, where only a portion of the number of check nodes is decoded during each of the first number of decoding iterations. In some cases, the first number of decoding iterations are applied according to the identified order. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed by a decoding component as described with reference to <FIG>.

At <NUM> the UE <NUM> or base station <NUM> may identify an order for decoding all of the number of check nodes during a second number of decoding iterations. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed by an order component as described with reference to <FIG>.

At <NUM> the UE <NUM> or base station <NUM> may apply the second number of decoding iterations to decoding the message after the first number of decoding iterations are applied, where all of the number of check nodes are decoded during each of the second number of decoding iterations. In some cases, the second number of decoding iterations are applied according to the identified order. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed by a decoding component as described with reference to <FIG>.

At <NUM> the UE <NUM> or base station <NUM> decodes the message through completion of both the first number of decoding iterations and the second number of decoding iterations. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed by a decoding component as described with reference to <FIG>.

By way of example, and not limitation, non-transitory computer-readable media may include random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory, compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

For example, an exemplary step that is described as "based on condition A" may be based on both a condition A and a condition B.

Claim 1:
A method for layered decoding of a low-density parity-check, LDPC, code for wireless communication, comprising:
receiving (<NUM>) a message encoded as a LDPC code that includes a plurality of check nodes and a plurality of bit nodes;
applying (<NUM>) a first number of decoding iterations to decoding the message, wherein only a portion of the plurality of check nodes is decoded during each of the first number of decoding iterations;
applying (<NUM>) a second number of decoding iterations to decoding the message after the first number of decoding iterations are applied, wherein all of the plurality of check nodes are decoded during each of the second number of decoding iterations;
determining a number of punctured bits connected to each of the plurality of check nodes;
reordering the plurality of check nodes to identify a decoding scheduling order for check nodes used during one or both of the first number of decoding iterations and the second number of decoding iterations based at least in part on the number of punctured bits connected to each of the plurality of check nodes; and
decoding (<NUM>) the message through completion of both the first number of decoding iterations and the second number of decoding iterations, wherein the check nodes of the portion of the plurality of check nodes have lower associated degrees compared to the remaining plurality of check nodes.