Patent Description:
Semiconductor memory devices include a volatile memory and a nonvolatile memory. Data stored in the volatile memory may be lost after a power-off. Data stored in the nonvolatile memory are retained even after a power-off. A flash memory device is an example of the nonvolatile memory. A flash memory device has a mass storage capability, relatively high noise immunity, and performs operations with relatively little power. Therefore, flash memory devices are employed in various fields. For example, a mobile system such as a smart-phone, or a tablet personal computer (PC) may employ flash memory as a storage medium.

A three-dimensional (3D) memory device may be fabricated by stacking non-volatile memory cells onto a substrate. However, due to the stacking, data retention characteristic of some of the memory cells may become degraded.

<CIT> discloses: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.

<CIT> discloses: A method for operating non-volatile multilevel memory cells. The method includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states.

<CIT> discloses: A memory device includes: a memory area including a first memory area including first memory cells storing N-bit data and a second memory area including second memory cells storing M-bit data, where 'M' and 'N' are natural numbers and M is greater than N, and a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

At least one example embodiment of the disclosure may provide a nonvolatile memory device with enhanced performance. At least one example embodiment of the disclosure may provide a storage device with enhanced performance.

According to an example embodiment, a nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of word-lines stacked on a substrate, a plurality of memory cells provided in a plurality of channel holes extending in a vertical direction with respect to the substrate and a word-line cut region extending in a first horizontal direction and dividing the plurality of word-lines into a plurality of memory blocks. The control circuit controls the memory cell array. A plurality of target memory cells coupled to an each of the plurality of word-lines are grouped into outer cells and inner cells based on a location index of each of the plurality of memory cells, and a distance between the outer cell and the word-line cut region is smaller than a distance between the inner cell and the word-line cut region. The control circuit controls performance of a program operation on target memory cells coupled to a target word-line of the plurality of word-lines such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits. The first number is a natural number greater than zero and the second number is a natural number greater than the first number. The control circuit adjusts levels of read voltages associated with a read operation performed on the target memory cell such that at least one of first threshold voltage distributions of the outer cells and at least one of second threshold voltage distributions of the inner cells are discriminated by a same read voltage.

According to an example embodiment, a storage device includes a nonvolatile memory device and a storage controller. The nonvolatile memory device includes a memory cell array which includes a plurality of word-lines stacked on a substrate, a plurality of memory cells provided in a plurality of channel holes extending in a vertical direction with respect to the substrate and a word-line cut region extending in a first horizontal direction and dividing the plurality of word-lines into a plurality of memory blocks. The storage controller groups a plurality of target memory cells coupled to a target word-line of the plurality of word-lines into a first group of cells and a second groups of cells based on a relative distance from the word-line cut region to the target memory cells and includes a program manager. The program manager controls performance of a program operation on the target memory cells such that each of the first group of cells stores a first number of bits and each of the second group of cells stores a second number of bits. The first number is a natural number greater than zero and the second number is a natural number greater than the first number. The nonvolatile memory device adjusts levels of read voltages associated with a read operation performed on the target memory cell such that at least one of first threshold voltage distributions of the first group of cells and at least one of second threshold voltage distributions of the second group of cells have a same read voltage.

Accordingly, the nonvolatile memory device and the storage device according to at least one example embodiment may group memory cells coupled to a target word-lines into outer cells and inner cells based on a relative distance from a word-line cut region to the memory cells and program different number of bits in the outer cells and the inner cells. Therefore, the nonvolatile memory device and the storage device may reduce degradation due to difference of threshold voltage distributions between the outer cells and the inner cells.

Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown.

<FIG> is a block diagram illustrating a storage system according to example an embodiment.

Referring to <FIG>, a storage system <NUM> may include a host <NUM> (e.g., a host device) and a storage device <NUM>. The host <NUM> may include a storage interface (I/F) <NUM> (e.g., an interface circuit).

The storage device <NUM> may be any kind of storage device.

The storage device <NUM> may include a storage controller <NUM>, a plurality of nonvolatile memory devices 400a to <NUM> (where k is an integer greater than two), a power management integrated circuit (PMIC) <NUM> and a host interface <NUM>. The host interface <NUM> may include a signal connector <NUM> and a power connector <NUM>. The storage device <NUM> may further include a buffer memory BM <NUM>.

The plurality of nonvolatile memory devices 400a to <NUM> may be used as a storage medium of the storage device <NUM>. In some example embodiments, each of the plurality of nonvolatile memory devices 400a to <NUM> may include a flash memory or a vertical NAND memory device. The storage controller <NUM> may be coupled to the plurality of nonvolatile memory devices 400a to <NUM> through a plurality of channels CHG1 to CHGk, respectively.

The storage controller <NUM> may be configured to receive a request REQ (e.g., a request signal such as read or write request) from the host <NUM> and communicate data DTA with the host <NUM> through the signal connector <NUM>. The storage controller <NUM> may write the data DTA to the plurality of nonvolatile memory devices 400a to <NUM> or read the data DTA from plurality of nonvolatile memory devices 400a to <NUM> based on the request REQ.

The storage controller <NUM> may communicate the data DTA with the host <NUM> using the buffer memory <NUM> as an input/output buffer. In an example embodiment, the buffer memory <NUM> includes a dynamic random access memory (DRAM).

The PMIC <NUM> may be configured to receive a plurality of power supply voltages (i.e., external supply voltages) VES1 to VESt from the host <NUM> through the power connector <NUM>. For example, the power connector <NUM> may include a plurality of power lines P1 to Pt, and the PMIC <NUM> may be configured to receive the plurality of power supply voltages VES1 to VESt from the host <NUM> through the plurality of power lines P1 to Pt, respectively. Here, t represents a positive integer greater than one.

The PMIC <NUM> may generate at least one first operating voltage VOP1 used by the storage controller <NUM>, at least one second operating voltage VOP2 used by the plurality of nonvolatile memory devices 400a to <NUM>, and at least one third operating voltage VOP3 used by the buffer memory <NUM> based on the plurality of power supply voltages VES1 to VESt.

For example, when the PMIC <NUM> receives all of the plurality of power supply voltages VES1 to VESt from the host <NUM>, the PMIC <NUM> may generate the at least one first operating voltage VOP1, the at least one second operating voltage VOP2, and the at least one third operating voltage VOP3 using all of the plurality of power supply voltages VES1 to VESt. On the other hand, when the PMIC <NUM> receives less than all of the plurality of power supply voltages VES1 to VESt from the host <NUM>, the PMIC <NUM> may generate the at least one first operating voltage VOP1, the at least one second operating voltage VOP2, and the at least one third operating voltage VOP3 using all of the part of the plurality of power supply voltages VES1 to VESt that is received from the host <NUM>.

<FIG> is a block diagram illustrating the host in <FIG> according to an example embodiment.

Referring to <FIG>, the host <NUM> may include a central processing unit (CPU) <NUM>, a read-only memory (ROM) <NUM>, a main memory <NUM>, a storage interface (I/F) <NUM> (e.g., interface circuit), a user interface (I/F) <NUM> and a bus <NUM>.

The bus <NUM> may refer to a transmission channel via which data is transmitted between the CPU <NUM>, the ROM <NUM>, the main memory <NUM>, the storage interface <NUM> and the user interface <NUM> of the host <NUM>. The ROM <NUM> may store various application programs. For example, the application programs may support storage protocols such as Advanced Technology Attachment (ATA), Small Computer System Interface (SCSI), embedded Multi Media Card (eMMC), and/or Universal flash storage (UFS) protocols are stored.

The main memory <NUM> may temporarily store data or programs. The user interface <NUM> may be a physical or virtual medium for exchanging information between a user and the host <NUM>, a computer program, etc., and may include physical hardware and logical software. For example, the user interface <NUM> may include an input device for allowing the user to manipulate the host <NUM> or provide input to the host <NUM>, and an output device for outputting a result of processing an input of the user.

The CPU <NUM> may control overall operations of the host <NUM>. The CPU <NUM> may generate a command and the power supply voltages VES1 to VESt for storing data in the storage device <NUM> or a request (or a command) and the power supply voltages VES1 to VESt for reading data from the storage device <NUM> by using an application stored in the ROM <NUM>, and transmit the request and the power supply voltages VES1 to VESt to the storage device <NUM> via the storage interface <NUM>.

<FIG> is a block diagram illustrating an example of the storage controller in the storage device in <FIG> according to an example embodiment.

Referring to <FIG>, the storage controller <NUM> may include a processor <NUM>, an error correction code (ECC) engine <NUM> (e.g., a logic circuit), an on-chip memory <NUM>, randomizer <NUM> (e.g., a logic circuit), a host interface <NUM> (e.g., an interface circuit), a ROM <NUM>, a buffer controller <NUM> (e.g., a control interface), and a memory interface <NUM> (e.g., an interface circuit) which are connected via a bus <NUM>.

The processor <NUM> controls an overall operation of the storage controller <NUM>. The processor <NUM> may control the ECC engine <NUM>, the on-chip memory <NUM>, the randomizer <NUM>, the host interface <NUM>, the ROM <NUM>, the buffer controller <NUM> and the memory interface <NUM>.

The processor <NUM> may include one or more cores (e.g., a homogeneous multi-core or a heterogeneous multi-core). The processor <NUM> may be or include, for example, at least one of a central processing unit (CPU), an image signal processing unit(ISP), a digital signal processing unit (DSP), a graphics processing unit(GPU), a vision processing unit (VPU), and a neural processing unit (NPU). The processor <NUM> may execute various application programs (e.g., a flash translation layer (FTL) <NUM> and firmware) loaded onto the on-chip memory <NUM>.

The on-chip memory <NUM> may store various application programs that are executable by the processor <NUM>. The on-chip memory <NUM> may operate as a cache memory adjacent to the processor <NUM>. The on-chip memory <NUM> may store a command, an address, and data to be processed by the processor <NUM> or may store a processing result of the processor <NUM>. The on-chip memory <NUM> may be, for example, a storage medium or a working memory including a latch, a register, a static random access memory (SRAM), a dynamic random access memory (DRAM), a thyristor random access memory (TRAM), a tightly coupled memory (TCM), etc..

The processor <NUM> may execute the FTL <NUM> loaded onto the on-chip memory <NUM>. The FTL <NUM> may be loaded onto the on-chip memory <NUM> as firmware or a program stored in the one of the nonvolatile memory devices 400a to <NUM>. The FTL <NUM> may manage mapping between a logical address provided from the host <NUM> and a physical address of the nonvolatile memory devices 400a to <NUM> and may include an address mapping table manager managing and updating an address mapping table. The FTL <NUM> may further perform a garbage collection operation, a wear leveling operation, and the like, as well as the address mapping described above. The FTL <NUM> may be executed by the processor <NUM> for addressing one or more of the following aspects of the nonvolatile memory devices 400a to <NUM>: overwrite-or in-place write-impossible, a life time of a memory cell, a limited number of program-erase (PE) cycles, and an erase speed slower than a write speed.

In an embodiment, the FTL <NUM> generates a location index LIDX that is used to group a plurality of memory cells included in each page of each of the nonvolatile memory devices 400a to <NUM> into outer cells and inner cells. In an embodiment, a distance between the outer cell and a word-line cut region is smaller than a distance between the inner cell and the word-line cut region. The outer cells may be referred to as a first group of cells and the inner cell may be referred to as a second group of cells.

The processor <NUM> may execute a program manager <NUM> loaded onto the on-chip memory <NUM>.

The program manager <NUM> may group a plurality of memory cells coupled to each of a plurality of word-lines in a memory cell array of each of the nonvolatile memory devices 400a to <NUM> into the outer cells and the inner cells based on the location index LIDX and may control a program operation performed on target memory cells coupled to a target word-line of the plurality of word-lines such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits. Here, the first number may be a natural number greater than zero and the second number may be a natural number greater than the first number.

Memory cells of the nonvolatile memory devices 400a to <NUM> may have a physical characteristic in which a threshold voltage distribution varies due to causes, such as a program elapsed time, a temperature, program disturbance, read disturbance and etc. For example, data stored at the nonvolatile memory devices 400a to <NUM> may become erroneous due to the above causes.

The storage controller <NUM> may utilize a variety of error correction techniques to correct such errors. For example, the storage controller <NUM> may include the ECC engine <NUM>. The ECC engine <NUM> may correct errors which occur in the data stored in the nonvolatile memory devices 400a to <NUM>. The ECC engine <NUM> may include an ECC encoder <NUM> (e.g., an encoder circuit) and an ECC decoder <NUM> (e.g., a decoder circuit). The ECC encoder <NUM> may perform an ECC encoding operation on data to be stored in the nonvolatile memory devices 400a to <NUM>. The ECC decoder <NUM> may perform an ECC decoding operation on data read from the nonvolatile memory devices 400a to <NUM>.

The ROM <NUM> may store a variety of information used for operating the storage controller <NUM>, in firmware.

The randomizer <NUM> may randomize data to be stored in one of the nonvolatile memory devices 400a to <NUM>. For example, the randomizer <NUM> may randomize data to be stored in one of the nonvolatile memory devices 400a to <NUM> by a word-line.

Data randomizing may include processing data such that program states of memory cells connected to a word-line have the same ratio. For example, if memory cells connected to one word-line are quadruple-level cells (QLC) each storing <NUM>-bit data, each of the memory cells may have one of an erase state and first through fifteenth program states. In this case, the randomizer <NUM> may randomize data such that in memory cells connected to one word-line, the number of memory cells having the erase state, and each of the number of memory cells having the first through fifteenth program states may be substantially the same as one another. For example, memory cells in which randomized data is stored have program states of which the number is equal to one another.

The randomizer <NUM> may randomize page data. An example of an operation of the randomizer <NUM> is described below. However, the embodiments are not limited thereto. For example, the randomizer <NUM> may randomize data such that in memory cells connected to one word-line, the number of memory cells having the erase state and each of the number of memory cells having the first through fifteenth program states are approximately the same value. For example, memory cells in which randomized data is stored have program states of which the number may be similar to one another.

In embodiments, when the number of memory cells having the erase state and each of the number of memory cells having the first through fifteenth program states are approximately the same value, this may mean that the number of the number of memory cells having the erase state and each of the number of memory cells having the first through fifteenth program states are within a particular threshold number of each other.

The buffer controller <NUM> may control an operation of the buffer memory <NUM>.

The storage controller <NUM> may communicate with the host <NUM> through the host interface <NUM>. For example, the host interface <NUM> may include Universal Serial Bus (USB), Multimedia Card (MMC), embedded-MMC, peripheral component interconnection (PCI), PCI-express, Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), Integrated Drive Electronics (IDE), Mobile Industry Processor Interface (MIPI), Nonvolatile memory express (NVMe), Universal Flash Storage (UFS), and etc..

The storage controller <NUM> may communicate with the nonvolatile memory devices 400a to <NUM> through the memory interface <NUM>. The memory interface <NUM> may include a data converter <NUM>.

<FIG> is a block diagram illustrating a connection relationship between the storage controller and one nonvolatile memory device in the storage device of <FIG>.

In <FIG> the buffer memory <NUM> connected to the storage controller <NUM> is also illustrated.

Referring to <FIG>, the nonvolatile memory device 400a may operate based on the first operating voltage VOP1.

The nonvolatile memory device 400a may perform an erase operation, a program operation, and/or a write operation under control of the storage controller <NUM>. The nonvolatile memory device 400a may receive a command CMD and an address ADDR through input/output lines from the storage controller <NUM> and may receive a data DTA through the buffer memory <NUM> for performing such operations. In addition, the nonvolatile memory device 400a may receive a control signal CTRL through a control line and receives power PWR1 through a power line from the storage controller <NUM>. In addition, the nonvolatile memory device 400a may provide the storage controller <NUM> with the data DTA using the buffer memory <NUM>.

The data DTA may include first through M-th page data PD1 to PDM and a (M+<NUM>)-th page data PD(M+<NUM>). Here, M is a natural number greater than two. For example, the first through M-th page data PD1 to PDM may be data for several pages and the (M+<NUM>)-th page data PD(M+<NUM>) may be data for a single page different from the several pages.

The storage controller <NUM> may include the program manager <NUM>. The program manager <NUM> may assign the program operation to be performed on the target memory cells associated with the data DTA to one of a first program operation and a second program operation and may assign the data DTA to one of the first through M-th page data PD1 to PDM and the (M+<NUM>)-th page data PD(M+<NUM>).

The buffer memory <NUM> may temporarily store the first through M-th page data PD1 to PDM from the host <NUM>, may provide the first through M-th page data PD1 to PDM to the storage controller <NUM>, may be released after the first program operation has completed, may temporarily store the (M+<NUM>)-th page data PD(M+<NUM>) from the host <NUM> and may provide the (M+<NUM>)-th page data PD(M+<NUM>) to the storage controller <NUM>.

<FIG> is a block diagram illustrating the nonvolatile memory device in <FIG> according to an example embodiment.

Referring to <FIG>, the nonvolatile memory device 400a may include a memory cell array <NUM>, an address decoder <NUM>, a page buffer circuit <NUM>, a data input/output (I/O) circuit <NUM>, a control circuit <NUM>, and a voltage generator <NUM>.

The memory cell array <NUM> may be coupled to the address decoder <NUM> through a string selection line SSL, a plurality of word-lines WLs, and a ground selection line GSL. In addition, the memory cell array <NUM> may be coupled to the page buffer circuit <NUM> through a plurality of bit-lines BLs.

The memory cell array <NUM> may include a plurality of memory cells coupled to the plurality of word-lines WLs and the plurality of bit-lines BLs.

In an example embodiment, the memory cell array <NUM> may be or include a three-dimensional memory cell array, which is formed on a substrate in a three-dimensional structure (e.g., a vertical structure). In this case, the memory cell array <NUM> may include vertical cell strings that are vertically oriented such that at least one memory cell is located over another memory cell.

<FIG> is a block diagram illustrating the memory cell array in the nonvolatile memory device of <FIG>.

Referring to <FIG>, the memory cell array <NUM> may include a plurality of memory blocks BLK1 to BLKz. Here, z is a natural number greater than two. The memory blocks BLK1 to BLKz extend along a first horizontal direction HD1, which may be for example an X-axis direction, a second horizontal direction HD2, which may be for example a Y-axis direction, and a vertical direction VD, which may be for example a Z-axis direction. In an example embodiment, the memory blocks BLK1 to BLKz are selected by the address decoder <NUM> in <FIG>. For example, the address decoder <NUM> may select a memory block BLK corresponding to a block address among the memory blocks BLK1 to BLKz.

<FIG> is a circuit diagram illustrating one of the memory blocks of <FIG>.

The memory block BLKia of <FIG> may be formed on a substrate SUB in a three-dimensional structure (or a vertical structure). For example, a plurality of memory cell strings included in the memory block BLKia may be formed in the vertical direction VD perpendicular to the substrate SUB.

Referring to <FIG>, the memory block BLKia may include memory cell strings NS <NUM> to NS33 (e.g., NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33) coupled between bit-lines BL1, BL2 and BL3 and a common source line CSL. Each of the memory cell strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. In <FIG>, each of the memory cell strings NS11 to NS33 is illustrated to include eight memory cells MC1 to MC8. However, embodiments are not limited thereto. In some example embodiments, each of the memory cell strings NS11 to NS33 may include any number of memory cells.

The string selection transistor SST may be connected to corresponding string selection lines SSL1 to SSL3. The plurality of memory cells MC1 to MC8 may be connected to corresponding word-lines WL1 to WL8, respectively. The ground selection transistor GST may be connected to corresponding ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to corresponding bit-lines BL1, BL2 and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

Word-lines (e.g., word-line WL1) having the same height may be commonly connected, and the ground selection lines GSL1 to GSL3 and the string selection lines SSL1 to SSL3 may be separated. In <FIG>, the memory block BLKi is illustrated to be coupled to eight word-lines WL1 to WL8 and three bit-lines BL1 to BL3. However, embodiments are not limited thereto. In some example embodiments, the memory cell array <NUM> may be coupled to any number of word-lines and bit-lines.

<FIG> illustrates an example of a structure of a NAND cell string CS in the memory block of <FIG>.

Referring to <FIG> and <FIG>, a pillar PL is provided on the substrate SUB such that the pillar PL extends in a direction perpendicular to the substrate SUB, for example a vertical direction VD, to make contact with the substrate SUB. Each of the ground selection line GSL, the word lines WL1 to WL8, and the string selection lines SSL illustrated in <FIG> may be formed of a conductive material parallel with the substrate SUB, for example, a metallic material. The pillar PL may be in contact with the substrate SUB through the conductive materials forming the string selection lines SSL, the word lines WL1 to WL8, and the ground selection line GSL.

A sectional view taken along a line V-V' is also illustrated in <FIG>. In some example embodiments, a sectional view of a first memory cell MC1 corresponding to a first word line WL1 is illustrated. The pillar PL may include a cylindrical body BD. An air gap AG may be defined in the interior of the body BD.

The body BD may include P-type silicon and may be an area where a channel will be formed. The pillar PL may further include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trap layer CT surrounding the tunnel insulating layer TI. A blocking insulating layer BI may be provided between the first word line WL and the pillar PL. The body BD, the tunnel insulating layer TI, the charge trap layer CT, the blocking insulating layer BI, and the first word line WL may constitute or be included in a charge trap type transistor that is formed in a direction perpendicular to the substrate SUB or to an upper surface of the substrate SUB. A string selection transistor SST, a ground selection transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

Referring to <FIG>, a memory block BLKib may include a plurality of cell strings CS11, CS12, CS21, and CS22. The plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged in a first horizontal direction (i.e., a row direction) and a second horizontal direction (i.e., a column direction). Each of the plurality of cell strings CS11, CS12, CS21, and CS22 may be referred to as a NAND cell string.

Cell strings positioned at the same column from among the plurality of cell strings CS11, CS12, CS21, and CS22 may be connected with the same bit-line. For example, the cell strings CS11 and CS21 may be connected with a first bit-line BL1, and the cell strings CS12 and CS22 may be connected with a second bit-line BL2. Each of the plurality of cell strings CS11, CS12, CS21, and CS22may include a plurality of cell transistors. Each of the plurality of cell transistors may include a charge trap flash (CTF) memory cell. The plurality of cell transistors may be stacked in a height direction that is perpendicular to a plane (e.g., a semiconductor substrate (not illustrated)) defined by the row direction and the column direction.

The plurality of cell transistors may be connected in series between a relevant bit-line (e.g., BL1 or BL2) and a common source line CSL. For example, the plurality of cell transistors may include string selection transistors SSTa and SSTb, dummy memory cells DMC1 and DMC2, memory cells MC1 to MC8, and ground selection transistors GSTa and GSTb. The serially-connected string selection transistors SSTa and SSTb may be provided between the serially-connected memory cells MC1 to MC8 and the relevant bit-line (e.g., BL1 and BL2). The serially-connected ground selection transistors GSTa and GSTb may be provided between the serially-connected memory cells MC1 to MC8 and the common source line CSL. In an embodiment, the second dummy memory cell DMC2 may be provided between the serially-connected string selection transistors SSTa and SSTb and the serially-connected memory cells MC1 to MC8, and the first dummy memory cell DMC1 may be provided between the serially-connected memory cells MC1 to MC8 and the serially-connected ground selection transistors GSTa and GSTb.

In the plurality of cell strings CS11, CS12, CS21, and CS22, memory cells positioned at the same height from among the memory cells MC1 to MC8 may share the same word-line. For example, the first memory cells MC1of the plurality of cell strings CS11, CS12, CS21, and CS22 may be positioned at the same height from the substrate (not illustrated) and may share a first word-line WL1. The second memory cells MC2 of the plurality of cell strings CS11, CS12, CS21, and CS22 may be positioned at the same height from the substrate (not illustrated) and may share a second word-line WL2.

In the plurality of cell strings CS11, CS12, CS21, and CS22, the dummy memory cells DMC1 or DMC2 positioned at the same height may share the same dummy word-line. For example, the first dummy memory cells DMC1of the plurality of cell strings CS11, CS12, CS21, and CS22 may share a first dummy word-line DWL1, and the second dummy memory cells DMC2 of the plurality of cell strings CS11, CS12, CS21, and CS22 may share a second dummy word-line DWL2.

In the plurality of cell strings CS11, CS12, CS21, and CS22, string selection transistors positioned at the same height and the same row from among the string selection transistors SSTa and SSTb may be connected with the same string selection line. For example, the string selection transistors SSTb of the cell strings CS11 and CS12 may be connected with a string selection line SSL1b, and the string selection transistors SSTa of the cell strings CS11 and CS12 may be connected with a string selection line SSL1a. The string selection transistors SSTb of the cell strings CS21 and CS22 may be connected with a string selection lineSSL2b, and the string selection transistors SSTa of the cell strings CS21and CS22 may be connected with a string selection line SSL2a. Although not illustrated, string selection transistors positioned at the same row from among the string selection transistors SSTa and SSTb of the plurality of cell strings CS11, CS12,CS21, and CS22 may share the same string selection line. For example, the string selection transistors SSTa and SSTb of the cell strings CS11 andCS12 may share a first string selection line, and the string selection transistors SSTa and SSTb of the cell strings CS21 and CS22 may share a second string selection line different from the first string selection line.

Ground selection transistors positioned at the same height and the same row from among the ground selection transistors GSTa and GSTb of the plurality of cell strings CS11, CS12, CS21, and CS22 may be connected with the same ground selection line. For example, the ground selection transistors GSTb of the cell strings CS11 and CS12 may be connected with a ground selection line GSL1b, and the ground selection transistors GSTa of the cell strings CS11 and CS12 may be connected with a ground selection line GSL1a. The ground selection transistors GSTb of the cell strings CS21 and CS22 may be connected with a ground selection lineGSL2b, and the ground selection transistors GSTa of the cell strings CS21and CS22 may be connected with a ground selection line GSL2a. Although not illustrated in the drawings, the ground selection transistors GSTa and GSTb of the plurality of cell strings CS11, CS12,CS21, and CS22 may share the same ground selection line. Alternatively, in the plurality of cell strings CS11, CS12, CS21, and CS22, ground selection transistors positioned at the same height from among the ground selection transistors GSTa and GSTb may share the same ground selection line. Alternatively, ground selection transistors positioned at the same row from among the ground selection transistors GSTa and GSTb of the plurality of cell strings CS11, CS12, CS21, and CS22 may share the same ground selection line.

Referring back to <FIG>, the control circuit <NUM> may receive a command signal including the command CMD and an address signal including the address ADDR from the storage controller <NUM>, and may control an erase loop, a program loop and/or a read operation of the nonvolatile memory device 400a based on the command CMD and the address ADDR. The program loop may include a program operation and a program verification operation. The erase loop may include an erase operation and an erase verification operation.

For example, the control circuit <NUM> may generate control signals CTLs, which are used for controlling the voltage generator <NUM>, based on at least one of the command signal and the command CMD, and generate a row address R_ADDR and a column address C_ADDR based on at least one of the address signal and the address signal ADDR. The control circuit <NUM> may provide the row address R_ADDR to the address decoder <NUM> and may provide the column address C_ADDR to the data I/O circuit <NUM>.

The address decoder <NUM> may be coupled to the memory cell array <NUM> through the string selection line SSL, the plurality of word-lines WLs, and the ground selection line GSL. During the program operation or the read operation, the address decoder <NUM> may determine one of the plurality of word-lines WLs as a first word-line (e.g., a selected word-line) and determine the rest of the plurality of word-lines WLs except for the first word-line as unselected word-lines based on the row address R_ADDR.

The voltage generator <NUM> may generate word-line voltages VWLs, which are used for the operation of the nonvolatile memory device 400a, based on the control signals CTLs. The voltage generator <NUM> may receive the power PWR1 from the storage controller <NUM>. The word-line voltages VWLs may be applied to the plurality of word-lines WLs through the address decoder <NUM>.

For example, during the erase operation, the voltage generator <NUM> may apply an erase voltage to a well of the memory block and may apply a ground voltage to entire word-lines of the memory block. During the erase verification operation, the voltage generator <NUM> may apply an erase verification voltage to the entire word-lines of the memory block or sequentially apply the erase verification voltage to word-lines in a word-line basis.

For example, during the program operation, the voltage generator <NUM> may apply a program voltage to the first word-line and may apply a program pass voltage to the unselected word-lines. In addition, during the program verification operation, the voltage generator <NUM> may apply a program verification voltage to the first word-line and may apply a verification pass voltage to the unselected word-lines.

Furthermore, during the read operation, the voltage generator <NUM> may apply a read voltage to the first word-line and may apply a read pass voltage to the unselected word-lines.

The page buffer circuit <NUM> may be coupled to the memory cell array <NUM> through the plurality of bit-lines BLs. The page buffer circuit <NUM> may include a plurality of page buffers. In an example embodiment, one page buffer of the page buffers is connected to one bit-line. In an example embodiment, one page buffer of the page buffers is connected to two or more bit-lines.

The page buffer circuit <NUM> may temporarily store data to be programmed in a selected page or data read out from the selected page.

The data I/O circuit <NUM> may be coupled to the page buffer circuit <NUM> through data lines DLs. During the program operation, the data I/O circuit <NUM> may receive the first through M-th page data PD1 to PDM and the (M+<NUM>)-th page data PD(M+<NUM>) from the storage controller <NUM>, and provide the first through M-th page data PD1 to PDM and the (M+<NUM>)-th page data PD(M+<NUM>) to the page buffer circuit <NUM> based on the column address C_ADDR received from the control circuit <NUM>.

During the read operation, the data I/O circuit <NUM> may provide the first through M-th page data PD1 to PDM and the (M+<NUM>)-th page data PD(M+<NUM>), which are stored in the page buffer circuit <NUM>, to the storage controller <NUM> based on the column address C_ADDR received from the control circuit <NUM>.

The control circuit <NUM> may control the page buffer circuit <NUM> and data I/O circuit <NUM>.

The control circuit <NUM> may include a status signal generator <NUM> and the status signal generator <NUM> may generate a status signal RnB indicating whether each of the program operation, the erase operation and the read operation has completed and/or is in progress.

The storage controller <NUM> may determine an idle state or a busy state of each of the nonvolatile memory devices 400a to <NUM> based on the status signal RnB. For example, if the status signal RnB indicates that none of the program operation, the erase operation and the read operation are in progress for the nonvolatile memory devices 400a, the storage controller <NUM> may determine that the nonvolatile memory device 400a is in an idle state. For example, if the status signal RnB indicates that one of the program operation, the erase operation and the read operation is in progress for the nonvolatile memory device 400a, the storage controller <NUM> may determine that the nonvolatile memory devices 400a is in a busy state.

<FIG> is a perspective view illustrating one of the memory blocks in <FIG>.

Referring to <FIG>, the memory block BLKi may be implemented such that at least one ground selection line GSL, a plurality of word-lines WLs and at least one string selection line SSL are stacked on a substrate between word-line cut regions WLC. Doping regions DOP may be formed in top portions of the substrate of the word-line cut regions WLC. The doping region may be used as common source lines CSL or common source nodes CSN to which a common source voltage is applied. The at least one string selection line SSL may be divided by a string selection line cut region SSLC extending in the first horizontal direction HD1.

A plurality of vertical channels or channel holes penetrate the at least one ground selection lines GSL, the plurality of word-lines WLs and the at least one string selection lines SSL. The at least one ground selection lines GSL, the plurality of word-lines WL and the at least one string selection lines SSL may be formed in the shape of planks, rectangular prisms, rectangular cuboids, etc. Bit-lines BL are connected to top surfaces of the channel holes.

<FIG> are top views of examples of the memory block of <FIG>, respectively and <FIG> is a circuit diagram illustrating connection relationship of NAND strings in the memory block in <FIG>.

In <FIG>, white circles represent inner cells or inner channel holes and shaded circles represent outer cells or outer channel holes. The common source lines corresponding to the doping region DOP in <FIG> are disposed in the word-line cut regions WLC.

Referring to <FIG>, the channel holes may be formed in a zig-zag arrangement in the memory block BLKi. Through the zig-zag arrangement, the area of the memory block BLKi may be reduced. Outer channel holes and inner channel holes are disposed in the second horizontal direction HD2 between two adjacent word-line cut regions WLC in the memory block BLKi. One of the inner channel holes and the outer channel holes may be connected to an even-numbered bit-line and the other may be connected to an odd-numbered bit-line. For convenience of illustration, only one bit-line pair BLot and BLin are illustrated and the other bit-lines are omitted in <FIG>.

As illustrated in <FIG>, the outer cells may be formed in the outer channel holes and the inner cells may be formed on the inner channel holes where a distance Do between the outer channel hole and the word-line cut region WLC is smaller than a distance Di between the inner channel hole and the word-line cut region WLC.

Referring to <FIG>, an inner NAND string NSi is formed in the inner channel hole and an outer NAND string NSo is formed in the outer channel hole. One end of the inner NAND string NSi is connected to the inner bit-line BLi and the other end of the inner NAND string NSi is connected to the common source line CSL through an inner resistor Ri. One end of the outer NAND string NSo is connected to the outer bit-line BLo and the other end of the outer NAND string NSo is connected to the common source line CSL through an outer resistor Ro.

Because the distance Do between the outer channel hole and the word-line cut region WLC is smaller than a distance Di between the inner channel hole and the word-line cut region WLC as illustrated in <FIG>, the resistance value of the inner resistor Ri is greater than the resistance value of the outer resistor Ro.

As such, in an embodiment, the inner NAND string NSi and the outer NAND string NSo are connected to the common source line CSL through the resistors Ri and Ro of different resistance values. The inner cells in the inner NAND string NSi and the outer cells in the outer NAND string NSo may have different electrical characteristics due to the asymmetric connection structure of the inner NAND string NSi and the outer NAND string NSo. Such different electrical characteristics may result in a difference in error bit levels. That is, a probability of error occurrence in the outer cells which are closer to the word-line cut region WLC than the inner cells is greater than a probability of error occurrence in the inner cells.

Referring to <FIG>, the storage controller <NUM> of <FIG> may group a plurality of memory cells in a memory block into outer cells disposed within a first distance D11 from the word-line cut region WLC, inner cells disposed outside the first distance D11 and within a second distance D12 and mid cells disposed between the inner cells based on a distance from the word-line cut region WLC. The mid cells may be referred to as a third group of cells.

Referring to <FIG>, the storage controller <NUM> of <FIG> may group a plurality of memory cells in a memory block into outer cells disposed within a first distance D21 from the word-line cut region WLC and inner cells disposed outside of the first distance D21 and within a second distance D22 based on a distance from the word-line cut region WLC. The storage controller <NUM> may further group each of the outer cells and the inner cells into at least two groups based on the distance from the word-line cut region WLC.

<FIG> is a graph showing a threshold voltage distribution of memory cells when a memory cell included in the memory cell array in <FIG> is a <NUM>-bit quadruple level cell (QLC).

Referring to <FIG>, a horizontal axis represents a threshold voltage Vth and the vertical axis represents the number of memory cells. When each of the memory cells is a <NUM>-bit quadrature level cell programmed to store <NUM> bits, the memory cell may have one from among an erase state E and first through fifteenth program states P1 through P15. When a memory cell is a multi-level cell, unlike a single-level cell, because an interval between threshold voltages distributions is small, a small change in the threshold voltage Vth may cause a large problem.

A first read voltage Vr1 has a voltage level between a distribution of a memory cell having the erase state E and a distribution of a memory cell having the first program state P1. Each of second through fifteenth read voltages Vr2 through Vr15 have a voltage level between distributions of memory cells having adjacent program states.

In example embodiments, assuming that the first read voltage Vr1 is applied, when a memory cell is turned on, data ' <NUM>' may be stored, and when the memory cell is turned off, data '<NUM>' may be stored. However, embodiments are not limited thereto. For example, in embodiments, assuming that the first read voltage Vr1 is applied, when a memory cell is turned on, data '<NUM>' may be stored, and when the memory cell is turned off, data ' <NUM>' may be stored. As such, a logic level of data may vary according to the present disclosure.

<FIG> and <FIG> are graphs showing examples in which a threshold voltage of memory cells in the graph of <FIG> is changed, respectively.

<FIG> shows that a threshold voltage of inner cells is changed and <FIG> shows that a threshold voltage of outer cells is changed.

Referring to <FIG> and <FIG>, memory cells respectively programmed to the erase state E and the first through fifteenth program states P1 through P15 may have a changed distribution as shown in <FIG> and <FIG> according to a read environment. In <FIG> and <FIG>, memory cells belonging to hatched portions may have read errors, thereby reducing the reliability of a nonvolatile memory device. A number of read errors in <FIG> may be greater than a number of read errors in <FIG>.

For example, when a read operation is performed on a memory device by using the first read voltage Vr1, although memory cells included in a hatched portion are programmed to the first program state P1, the memory cells may be determined to have the erase state E due to a decrease in the threshold voltage Vth. Accordingly, an error may occur in the read operation, thereby reducing the reliability of the nonvolatile memory device.

When data is read from the nonvolatile memory device 400a, a raw bit error rate (RBER) may vary according to a voltage level of a read voltage. An optimum or, alternatively, desirable voltage level of a read voltage maybe determined according to a distribution pattern of the memory cells. Accordingly, as a distribution of the memory cells changes, an optimum or, alternatively, desirable voltage level of a read voltage needed to read data from the nonvolatile memory device may change.

<FIG> illustrates a table for explaining bit mapping for programming memory cells according to an example embodiment.

For convenience of explanation, the present embodiment relates a QLC memory cell. However, in other embodiments the memory cell may be a different type other than a QLC type.

Referring to <FIG>, when memory cells are QLCs, each of the memory cells may store a least significant bit (LSB), an extra significant bit (ESB), an upper significant bit (USB), and a most significant bit (MSB). Further referring to <FIG>, LSBs stored in memory cells in a first row from among the memory cells connected to the word-line WL1 may form a first page, and MSBs stored therein may form a fourth page. USBs stored in the memory cells in the first row from among the memory cells connected to the word-line WL1 may form a third page, and ESB stored therein may form a second page.

<FIG> illustrates an example of a page of a target word-line according to an example embodiment.

Referring to <FIG>, a target word-line WL_S may include first, second, third and fourth pages PG1, PG2, PG3 and PG4, and the target word-line WL_S is coupled to memory cells MCa, MCb, MCc, MCd, MCe, MCf, MCg, MCh, MCi, MCj, MCk, MCl, MCm, MCn, MCo and MCp coupled to bit-lines BLa, BLb, BLc, BLd, BLe, BLf, BLg, BLh, BLi, BLj, BLk, BLl, BLm, BLn, BLo and BLp, respectively.

Each of the memory cells MCa, MCb, MCc, MCd, MCe, MCf, MCg, MCi, MCj, MCk, MCl, MCm, MCn and MCo is programmed to store <NUM>-bits (i.e., quadruple cell bit (QCB)) and each of the memory cells MCh and MCp is programmed to store <NUM>-bits (i.e., multi-cell bit (MCB)). Therefore, each of the first through fourth pages PG1, PG2, PG3 and PG4 may store a null bit NB (or null bits). In an embodiment, the null bit NB (or null bits) does not store any information that can be removed from a page after it is processed. The memory cells MCa, MCb, MCc, MCd, MCe, MCf, MCg, MCi, MCj, MCk, MCl, MCm, MCn and MCo may correspond to the inner cells and the memory cells MCh and MCp may correspond to the outer cells.

<FIG> illustrates an example of a page of a target word-line according to an example embodiments.

Each of the memory cells MCa, MCb, MCc, MCd, MCe, MCf, MCg, MCk, MCl, MCm and MCn is programmed to store <NUM>-bits (i.e., QLC), each of the memory cells MCh and MCo is programmed to store <NUM>-bits (i.e., triple cell bit (TCB)) and each of the memory cells MCi and MCp is programmed to store <NUM>-bit (i.e., single cell bit (SCB). Therefore, each of the first through fourth pages PG1, PG2, PG3 and PG4 may store a null bit NB and at least two of the first through fourth pages PG1, PG2, PG3 and PG4 may store a different number of bits with respect to each other. The memory cells MCa, MCb, MCc, MCd, MCe, MCf, MCg, MCh, MCi, MCj, MCk, MCl, MCm, MCn, MCo and MCp may correspond to the inner cells, the memory cells MCh and MCo may correspond to the mid cells and the MCi and MCp may correspond to the outer cells.

<FIG> illustrates threshold voltage distributions of single-level cells (SLC)s and threshold voltage distributions of triple-level cells (TLC)s.

In <FIG>, a reference numeral <NUM> illustrates threshold voltage distributions of SLCs including an erase state E and a first program state P11 and a reference numeral <NUM> illustrates threshold voltage distributions of TLCs including an erase state E and first through seventh program state P1, P2, P3, P4, P5, P6 and P7.

In <FIG>, when a first read voltage Vr11 for discriminating between the erase state E and the first program state P11 of the SLCs is used to discriminate between the second program state P2 and the third program state P3 of the TLCs, many errors may occur in reading the TLCs.

<FIG> illustrates threshold voltage distributions of SLCs and threshold voltage distributions of TLCs.

In <FIG>, when a first read voltage Vr21 that discriminates between the erase state E and the first program state P11 of the SLCs is used to discriminate between the third program state P3 and the fourth program state P4 of the TLCs, errors should not occur in reading the TLCs. For reducing errors in reading the TLCs, the threshold voltage distributions of TLCs may be aligned with the threshold voltage distributions of SLCs in programming the TLCs or a level of the first read voltage Vr21 may be adjusted such that at least one of the threshold voltage distributions of SLCs and at least one of the threshold voltage distributions of TLCs are discriminated by a same read voltage. That is, the program manager <NUM> or the control circuit <NUM> may adjust the level of the first read voltage Vr21 such that at least one of the threshold voltage distributions of the outer cells and at least one of the threshold voltage distributions of the inner cells are discriminated by a same read voltage.

<FIG> is a block diagram of a program manager in the storage controller of <FIG> according to an example embodiment.

Referring to <FIG>, the program manager <NUM> may include a program type assigner <NUM>, a first address assigner <NUM> and a second address assigner <NUM>.

The program manager <NUM> may assign a program operation associated with the data DTA, to be performed on target memory cells in each of the nonvolatile memory devices 400a to <NUM>, to one of a first program operation and a second program operation based on excepted retention time information ETRI of the data DTA and user request information URI on the data DTA, may assign the data DTA (program data) to first through M-th page data PD1 to PDM and a (M+<NUM>)-th page data PD(M+<NUM>), may provide the first address assigner <NUM> with a first program type signal PTS1 indicating that the program operation is assigned to the first program operation, and may provide the second address assigner <NUM> with a second program type signal PTS2 indicating that the program operation is assigned to the second program operation.

The excepted retention time information ETRI may correspond to an expected storing time associated with the data DTA to be programmed and the user request information URI may include performance, latency associated with the program operation and reliability associated with the data DTA to be programmed.

The first address assigner <NUM> may receive the first program type signal PTS1 and the first through M-th page data PD1 to PDM, may assign a logical address LADDRa of the target word-line to a physical address PADDRa based on the location index LIDX and may provide the physical address PADDRa and the first through M-th page data PD1 to PDM to the nonvolatile memory device 400a through the memory interface <NUM>.

The second address assigner <NUM> may receive the second program type signal PTS2 and the (M+<NUM>)-th page data PD(M+<NUM>), may assign a logical address LADDRb of the target word-line to the physical address PADDRa based on the location index LIDX and may provide the physical address PADDRa and the (M+<NUM>)-th page data PD(M+<NUM>) to the nonvolatile memory device 400a through the memory interface <NUM>.

Here, the first program operation may correspond to a TLC program operation to program memory cells of a first memory block to have an erase state and first through <NUM>M-<NUM> program states and the second program operation may correspond to a QLC program operation to program memory cells of a second memory block to have one of an erase state and first through <NUM>M+<NUM>-<NUM> program states.

<FIG> illustrates that a first program operation is performed on a plurality of word-lines in the nonvolatile memory device of <FIG>.

Referring to <FIG>, memory cells are coupled to a plurality of word-lines WLa, WLb, WLc and WLd and a plurality of bit-lines BLa, BLb, BLc, BLd, BLe, BLf, BLg, BLh, BLi, BLj, BLk, BLl, BLm, BLn, BLo and BLp. The first program operation is sequentially performed on the memory cells word-line by word-lines and each of the memory cells stores <NUM>-bits. That is each of the memory cells is a TLC.

<FIG> illustrates that a second program operation is performed on a portion of the memory cells in <FIG>.

Referring to <FIG>, a second program operation is performed on first memory cells coupled to plurality of word-lines WLa, WLb, WLc and WLd and the bit-lines BLa, BLb, BLc, BLd, BLe, BLf, BLg, BLi, BLj, BLk, BLl, BLm, BLn and BLo and each of the second memory cells stores <NUM>-bits and the second program operation is not performed on second memory cells coupled to plurality of word-lines WLa, WLb, WLc and WLd and the bit-lines BLh and BLp. That is, each of the first memory cells is a QLC. A program inhibit voltage is applied to the bit-lines BLh and BLp when the second program operation is performed.

That is, the control circuit <NUM> may apply first bias voltages (a first program voltage to the word-lines, a program permission voltage to the bit-lines) to the word-lines WLa, WLb, WLc and WLd and the bit-lines BLa, BLb, BLc, BLd, BLe, BLf, BLg, BLh, BLi, BLj, BLk, BLl, BLm, BLn, BLo and BLp such that each of the memory cells coupled to the word-lines WLa, WLb, WLc and WLd and the bit-lines BLa, BLb, BLc, BLd, BLe, BLf, BLg, BLh, BLi, BLj, BLk, BLl, BLm, BLn, BLo and BLp stores a first number of bits (i.e., <NUM>-bits) in the first program operation. The control circuit <NUM> may apply second bias voltages (a second program voltage whose level is greater than the first program voltage to the word-lines, a program inhibit voltage to the bit-lines BLh and BLp and a program permission voltage to the bit-lines BLa, BLb, BLc, BLd, BLe, BLf, BLg, BLi, BLj, BLk, BLl, BLm, BLn and BLo) to the word-lines WLa, WLb, WLc and WLd and the bit-lines BLa, BLb, BLc, BLd, BLe, BLf, BLg, BLi, BLj, BLk, BLl, BLm, BLn and BLo such that each of memory cells coupled to the word-lines WLa, WLb, WLc and WLd and the bit-lines BLa, BLb, BLc, BLd, BLe, BLf, BLg, BLi, BLj, BLk, BLl, BLm, BLn and BLo stores a second number of bits (i.e., <NUM>-bits). The memory cells coupled to the WLa, WLb, WLc and WLd and the bit-lines BLh and BLp may correspond to the outer cells. The memory cells coupled to the word-lines WLa, WLb, WLc and WLd and the bit-lines BLa, BLb, BLc, BLd, BLe, BLf, BLg, BLi, BLj, BLk, BLl, BLm, BLn and BLo may correspond to the inner cells.

<FIG> is a graph showing enlarged first and second program states of <FIG>.

Referring to <FIG>, a read window RDW between the first and second program states P1 and P2 may be defined as a difference between a fall voltage VF corresponding to the first program state P1 and a rise voltage VR corresponding to the second program state P2. Here, the fall voltage VF may represent a threshold voltage where the number of "off" cells corresponds to a reference number REF, based on an "off" cell count result for memory cells programmed to the first program state P1. The rise voltage VR may represent a threshold voltage where the number of "off" cells corresponds to the reference number REF, based on an "off" cell count result for memory cells programmed to the second program state P2. A read voltage Vr2 for determining the second program state P2 should have a voltage level within the read window RDW, and in order to decrease a read error, the read window RDW should be sufficiently widely secured.

<FIG> illustrates a cell region in which the memory cell array of <FIG> is formed according to an example embodiment.

Referring to <FIG>, a cell region CR includes a plurality of channel holes CH.

A channel hole size, for example, a channel hole diameter, may be varied according to positions within the cell region CR. For example, channel holes CH adjacent to the first and second edges EDG1 and EDG2 have a low peripheral density, and thus may have a different diameter from those of other channel holes CH. A memory block BLK11 may be adjacent to the first edge EDG1, and may be spaced apart from the first edge EDG1 by a first distance d1. A memory block BLK12 is not adjacent to the first and second edges EDG1 and EDG2, and may be in a center of the cell region CR, and may be spaced apart from the first edge EDG1 by a second distance d2. In an embodiment, the second distance d2 is greater than the first distance d1. In an embodiment, a first diameter D1 of a first channel hole CHa included in the memory block BLK11 may be smaller than a second diameter D2 of a second channel hole CHb included in the memory block BLK12.

<FIG> illustrate cross-sections of strings of the memory blocks BLK11 and BLK12 of <FIG>, respectively.

Referring to <FIG>, a pillar including a channel layer <NUM> and an internal layer <NUM> may be formed in the first channel hole CHa included in the memory block BLK11, and a charge storage layer CS may be formed around the first channel hole CHa, and the charge storage layer CS may have an (oxide-nitride-oxide) ONO structure.

Referring to <FIG>, a pillar including a channel layer <NUM> and an internal layer <NUM> may be formed in the second channel hole CHb included in the memory block BLK12, and a charge storage layer CS may be formed around the second channel hole CHb, and the charge storage layer CS may have an ONO structure.

In an example embodiment, a thickness of the charge storage layer CS included in the memory block BLK12 is different from a thickness of the charge storage layer CS included in the memory block BLK11. Characteristics of memory cells may vary due to the difference in the channel hole diameters. For example, in a NAND flash nonvolatile memory device having a gate all around structure in which a gate electrode is disposed around a circumference of a channel hole, if a channel hole diameter is reduced, the magnitude of an electric field formed between a gate electrode and a channel layer <NUM> is increased. Thus, program and erase speeds of a memory cell having a relatively small channel hole diameter like the first channel hole CHa may be higher than those of a memory cell having a relatively large channel hole diameter like the second channel hole CHb.

Referring back to <FIG>, a memory block is formed in the cell region CR to include all memory cells corresponding to one page in the first horizontal direction HD1, that is, in a word-line direction, and to include some strings in the second horizontal direction HD2, that is, in a bit-line direction. Thus, each memory block extends in the first horizontal direction HD1, and channel hole sizes, that is, channel hole diameters may differ in units of memory blocks. Thus, program and erase speeds of memory cells included in the memory block BLK11 may be higher than program and erase speeds of memory cells included in the memory block BLK12.

<FIG> illustrates an example of a vertical structure of one of the channel holes in <FIG>.

Referring to <FIG>, a channel hole CH1 corresponding to a string included in a nonvolatile memory device is illustrated. As described above, the channel hole CH1 is formed by etching portions of gate electrodes and insulation layers stacked on a substrate, and thus, the channel hole CH1 may have a tapered etching profile where a diameter of the channel hole CH1 becomes downwardly smaller. Thus, a diameter of the channel hole CH1 may be smaller towards the substrate.

In an example embodiment, the channel hole CH1 may be divided into three zones according to channel hole diameters. For example, a zone in which a channel hole diameter is smaller than a first value may be referred to as a first zone Z1, and a zone in which a channel hole diameter is equal to or greater than the first value and smaller than a second value may be referred to as a second zone Z2, and a zone in which a channel hole diameter is equal to or greater than the second value and smaller than a third value may be referred to as a third zone Z3. Therefore, characteristic of memory cells included in one channel hole may be different according to positions along the vertical direction VD.

A word-line WLb1 is provided in the first zone Z1, a word-line Wla1 is provided in the second zone Z2, and a word-line WLc1 is provided in the third zone Z3. Because the word-line WLb1 is adjacent to a lower edge of the channel hole CH1, the word-line WLb1 is adjacent to a ground selection line or the substrate, a bridge may occur between the word-line WLb1 and the channel. When the bridge occurs between the word-line WLb and the channel, a current leakage may occur through the bridge and a program/read operation or an erase operation may operate abnormally in the word-line WLb1 due to the bridge.

Because the word-line WLc1 is adjacent to an upper edge of the channel hole CH1, the word-line WLc1 is adjacent to a string selection line or the substrate, a bridge may occur between the word-line WLc1 and the channel.

Error occurrence probability of pages coupled to the word-line WLc1 which is adjacent to an upper edge of the channel hole CH1 or coupled to the word-line WLb1 which is adjacent to the lower edge of the channel hole CH1 may be greater than error occurrence probability of pages coupled to the word-line Wla1 which is disposed at a center region of the channel hole CH1.

<FIG> relate to embodiments in which an error attribute of the target page may be different based on a location of the target word-line and error occurrence probability of the target page may be different based on the error attribute.

The processor <NUM> in the storage controller <NUM> according to an example embodiment, may assign different location indices to the plurality of NAND strings, respectively. In addition, the processor <NUM> may apply the same location index to at least two NAND strings sharing a same channel hole from among the plurality of channel holes, from among the plurality of NAND strings. In addition, the processor <NUM> may assign individual location indices to the plurality of memory blocks, respectively. In addition, the processor <NUM> may assign the location index to at least one word-line or a portion of word-lines including the inner cells and outer cells having a different error occurrence probability.

<FIG> is a block diagram of a storage device according to an example embodiment.

Referring to <FIG>, a storage device 200a may include a storage controller 300a and a nonvolatile memory device 400a.

The storage controller 300a may include an ECC engine <NUM> and a memory interface <NUM> and the memory interface <NUM> may include a bit cell table <NUM> and a data converter <NUM>. The nonvolatile memory device 400a may include a memory cell array <NUM> and a page buffer circuit <NUM>.

During a read operation on a target word-line WL_S of the nonvolatile memory device 400a, first through fourth page data PD1~PD4 read from the target word-line WL_S may be temporarily stored in the page buffer circuit <NUM> as a read data RD. The read data RD may include QCBs read from the QLCs, SCB read from the SLCs and null bits that do not include information. The nonvolatile memory device 400a may provide the read data RD stored in the page buffer circuit <NUM> to the memory interface <NUM> through the data I/O circuit (<NUM> in <FIG>).

The data converter <NUM> in the memory interface <NUM> may generate a converted read data CRD by removing null bits NB in the read data read based on bit cell information BCI provided from the bit cell table <NUM> and may provide the converted read data CRD to the ECC engine <NUM>. The ECC engine <NUM> may perform ECC decoding on the converted read data CRD to correct errors in the converted read data CRD.

<FIG> is a block diagram of a storage device according to example embodiments.

Referring to <FIG>, a storage device 200b may include a storage controller 300b and a nonvolatile memory device 400aa.

The storage controller 300b may include an ECC engine <NUM> and a memory interface <NUM> and may store a bit cell table <NUM>. The nonvolatile memory device 400a may include a memory cell array <NUM> and a page buffer circuit 430a. The page buffer circuit 430a may include a data converter <NUM>.

During a read operation on a target word-line WL_S of the nonvolatile memory device 400a, first through fourth page data PD1~PD4 read from the target word-line WL_S may be temporarily stored in the page buffer circuit <NUM> as a read data RD. The read data RD may include QCBs read from the QLCs, SCB read from the SLCs and null bits that do not include information. The data converter <NUM> may generate a converted read data CRD by removing null bits NB in the read data read based on bit cell information BCI provided from the bit cell table <NUM>. The nonvolatile memory device 400a may provide the converted read data CRD to the memory interface <NUM> through the data I/O circuit (<NUM> in <FIG>).

The memory interface <NUM> may provide the converted read data CRD to the ECC engine <NUM>. The ECC engine <NUM> may perform ECC decoding on the converted read data CRD to correct errors in the converted read data CRD.

<FIG> and <FIG> are timing diagrams for describing a program operation of the storage device according to an example embodiment.

Referring to <FIG>, <FIG> and <FIG>, the nonvolatile memory device 400a may receive the first through third page data PD1, PD2 and PD3 from the storage controller <NUM>. During an interval INT11, the nonvolatile memory device 400a may receive a command CMD1, a first address ADDR1, the first page data PD1, and a command CMD11 through I/O lines. The commands CMD1 and CMD11 may be a command set for setting up the first page data PD1. The nonvolatile memory device 400a may dump (e.g., transfer) the first page data PD1 in response to the command CMD11 and a status signal RnB may be in a busy state while the first page data PD1 is dumped.

During an interval INT12, the nonvolatile memory device 400a may receive the command CMD1, the first address ADDR1, the second page data PD2, and a command CMD12 through the I/O lines. The commands CMD1 and CMD12 may be a command set for setting up the second page data PD2. The nonvolatile memory device 400a may dump (e.g., transfer) the second page data PD2 in response to the command CMD12 and the status signal RnB may be in a busy state while the second page data PD2 is dumped.

During an interval INT13, the nonvolatile memory device 400a may receive the command CMD1, the first address ADDR1, the third page data PD3, and a command CMD13 through the I/O lines. The commands CMD1 and CMD13 may be a command set for setting up the third page data PD3. The nonvolatile memory device 400a may dump (e.g., transfer) the third page data PD3 in response to the command CMD13 and the status signal RnB may be in a busy state while the third page data PD3 is dumped.

During an interval INT14, the nonvolatile memory device 400a may receive a command CMD21 and the second address ADDR2, and a command CMD22 through the I/O lines. The commands CMD1 and CMD22 may be a command set for initiating a program operation. The second address ADDR2 may include information about a program order.

During a program time tPROG1, the nonvolatile memory device 400a may perform a first program operation to program the first, second, and third page data PD1, PD2, and PD3 in response to the command CMD22. During the program time tPROG1, the status signal RnB may be in a busy state (i.e., in a low state).

An interval INT2 may elapse after the first program operation has completed. During the interval INT2, the nonvolatile memory device 400a may receive a read command CMDr and the first address ADDR1, may read the first, second, and third pages PD1, PD2, and PD3 from the memory cell array <NUM> in response to the read command CMDr as a read data DTAr and may provide the CMDr to the storage controller <NUM>. During the read data DTAr are read from the memory cell array <NUM> the status signal RnB may be in a busy state (i.e., in a low state).

During an interval INT31, the nonvolatile memory device 400a may receive the command CMD1, the first address ADDR1, the fourth page data PD4, and a command CMD14 through the I/O lines. The commands CMD1 and CMD14 may be a command set for setting up the fourth page data PD4. The nonvolatile memory device 400a may dump (e.g., transfer) the fourth page data PD4 in response to the command CMD14 and the status signal RnB may be in a busy state while the fourth page data PD4 is dumped.

During an interval INT32, the nonvolatile memory device 400a may receive a command CMD31 and the second ADDR2, and a command CMD32 through the I/O lines. The commands CMD31 and CMD32 may be a command set for initiating a program operation. The second address ADDR2 may include information about a program order.

During a program time tPROG2, the nonvolatile memory device 400a may perform a second program operation to program the fourth page data PD4 in response to the command CMD32. During the program time tPROG2, the status signal RnB may be in a busy state (i.e., in a low state).

<FIG> is a flow chart illustrating a method of operating a storage device according to an example embodiment.

Referring to <FIG>, there is provided a method of operating a nonvolatile memory device 400a which includes a memory cell array, where the memory cell array includes a plurality of word-lines stacked on a substrate, a plurality of memory cells provided in a plurality of channel holes extending in a vertical direction with respect to the substrate and a word-line cut region extending in a first horizontal direction and dividing the plurality of word-lines into a plurality of memory blocks.

According to the method, the nonvolatile memory device 400a receives a first program command (e.g., a PGM command), a physical address and first through M-th page data PD1 to PDM from a storage controller (operation S110).

The nonvolatile memory device 400a performs a first program operation on a first memory block of the memory cell array based on the first through M-th page data PD1 to PDM such that memory cells of a target word-line designated by the physical address have an erase state and first through <NUM>M-<NUM>-th target program states (operation S130). Location index information may indicate the physical address.

After a reference time interval elapses from completion of the first program operation, the nonvolatile memory device 400a receives a second program command, the physical address and a (M+<NUM>)-th page data PD(M+<NUM>) from the storage controller (operation S150).

The nonvolatile memory device 400a performs a second program operation on the first memory block based on the (M+<NUM>)-th page data PD(M+<NUM>) such that a portion of the memory cells of the target word-line have an erase state and first through <NUM>M+<NUM>-<NUM>-th target program states (operation S170).

The first program operation may correspond to a TLC program operation and the second program operation may correspond to a QLC program operation.

Therefore, the nonvolatile memory device and the storage device may group memory cells coupled to target word-lines into outer cells and inner cells based on a relative distance from a word-line cut region to the memory cells and program different numbers of bits in the outer cells and the inner cells. Accordingly, the nonvolatile memory device and the storage device may reduce degradation due to a difference of threshold voltage distributions between the outer cells and the inner cells.

<FIG> is a cross-sectional view of a nonvolatile memory device according to an example embodiment.

Referring to <FIG>, a nonvolatile memory device <NUM>, which may be referred to as a memory device, may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a memory cell region or a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer, separate from the first wafer, and then bonding the upper chip and the lower chip to each other. Here, the bonding process may include a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metals may include copper (Cu) using a Cu-to-Cu bonding. The example embodiment, however, is not limited thereto. For example, the bonding metals may also be formed of aluminum (Al) or tungsten (W).

Each of the peripheral circuit region PERI and the cell region CELL of the memory device <NUM> may include an external pad bonding area PA, a word-line bonding area WLBA, and a bit-line bonding area BLBA.

The peripheral circuit region PERI may include a first substrate <NUM>, an interlayer insulating layer <NUM>, a plurality of circuit elements 2220a, 2220b, and 2220c formed on the first substrate <NUM>, first metal layers 2230a, 2230b, and 2230c respectively connected to the plurality of circuit elements 2220a, 2220b, and 2220c, and second metal layers 2240a, 2240b, and 2240c formed on the first metal layers 2230a, 2230b, and 2230c. In an example embodiment, the first metal layers 2230a, 2230b, and 2230c may be formed of tungsten having relatively high electrical resistivity, and the second metal layers 2240a, 2240b, and 2240c may be formed of copper having relatively low electrical resistivity.

In an example embodiment illustrated in <FIG>, although only the first metal layers 2230a, 2230b, and 2230c and the second metal layers 2240a, 2240b, and 2240c are shown and described, the example embodiment is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers 2240a, 2240b, and 2240c. At least a portion of the one or more additional metal layers formed on the second metal layers 2240a, 2240b, and 2240c may be formed of aluminum or the like having a lower electrical resistivity than those of copper forming the second metal layers 2240a, 2240b, and 2240c.

The interlayer insulating layer <NUM> may be disposed on the first substrate <NUM> and cover the plurality of circuit elements 2220a, 2220b, and 2220c, the first metal layers 2230a, 2230b, and 2230c, and the second metal layers 2240a, 2240b, and 2240c. The interlayer insulating layer <NUM> may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b in the word-line bonding area WLBA. In the word-line bonding area WLBA, the lower bonding metals 2271b and 2272b in the peripheral circuit region PERI may be electrically bonded to upper bonding metals 2371b and 2372b of the cell region CELL. The lower bonding metals 2271b and 2272b and the upper bonding metals 2371b and 2372b may be formed of aluminum, copper, tungsten, or the like. Further, the upper bonding metals 2371b and 2372b in the cell region CELL may be referred as first metal pads and the lower bonding metals 2271b and 2272b in the peripheral circuit region PERI may be referred as second metal pads.

The cell region CELL may include at least one memory block. The least one memory block may include a first region and a second region. The first region may store compensation data set and may correspond to SLC block. The cell region CELL may include a second substrate <NUM> and a common source line <NUM>. On the second substrate <NUM>, a plurality of word-lines <NUM>, which may include word-line <NUM>, word-line <NUM>, word-line <NUM>, word-line <NUM>, word-line <NUM>, word-line <NUM>, word-line <NUM>, and word-line 2338may be stacked in a vertical direction VD (e.g., a Z-axis direction), perpendicular to an upper surface of the second substrate <NUM>. At least one string selection line and at least one ground selection line may be arranged on and below the plurality of word-lines <NUM>, respectively, and the plurality of word-lines <NUM> may be disposed between the at least one string selection line and the at least one ground selection line.

In the bit-line bonding area BLBA, a channel structure CH may extend in the vertical direction VD, perpendicular to the upper surface of the second substrate <NUM>, and pass through the plurality of word-lines <NUM>, the at least one string selection line, and the at least one ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer and a second metal layer. For example, the first metal layer may be a bit-line contact 2350c, and the second metal layer may be a bit-line 2360c. In an example embodiment, the bit-line 2360c may extend in a second horizontal direction HD2 (e.g., a Y-axis direction), parallel to the upper surface of the second substrate <NUM>.

In an example embodiment illustrated in <FIG>, an area in which the channel structure CH, the bit-line 2360c, and the like are disposed may be defined as the bit-line bonding area BLBA. In the bit-line bonding area BLBA, the bit-line 2360c may be electrically connected to the circuit elements 2220c providing a page buffer circuit <NUM> in the peripheral circuit region PERI. The bit-line 2360c may be connected to upper bonding metals 2371c and 2372c in the cell region CELL, and the upper bonding metals 2371c and 2372c may be connected to lower bonding metals 2271c and 2272c connected to the circuit elements 2220c of the page buffer circuit <NUM>.

In the word-line bonding area WLBA, the plurality of word-lines <NUM> may extend in a first horizontal direction HD1 (e.g., an X-axis direction), parallel to the upper surface of the second substrate <NUM> and perpendicular to the second horizontal direction HD2, and may be connected to a plurality of cell contact plugs <NUM>, which may include cell contact plug <NUM>, cell contact plug <NUM>, cell contact plug <NUM>, cell contact plug <NUM>, cell contact plug <NUM>, cell contact plug <NUM>, and cell contact plug <NUM>. The plurality of word-lines <NUM> and the plurality of cell contact plugs <NUM> may be connected to each other in pads provided by at least a portion of the plurality of word-lines <NUM> extending in different lengths in the first horizontal direction HD1. A first metal layer 2350b and a second metal layer 2360b may be connected to an upper portion of the plurality of cell contact plugs <NUM> connected to the plurality of word-lines <NUM>, sequentially. The plurality of cell contact plugs <NUM> may be connected to the peripheral circuit region PERI by the upper bonding metals 2371b and 2372b of the cell region CELL and the lower bonding metals 2271b and 2272b of the peripheral circuit region PERI in the word-line bonding area WLBA.

The plurality of cell contact plugs <NUM> may be electrically connected to the circuit elements 2220b forming an address decoder <NUM> in the peripheral circuit region PERI. In an example embodiment, operating voltages of the circuit elements 2220b forming the address decoder <NUM> may be different than operating voltages of the circuit elements 2220c forming the page buffer circuit <NUM>. For example, operating voltages of the circuit elements 2220c forming the page buffer circuit <NUM> may be greater than operating voltages of the circuit elements 2220b forming the address decoder <NUM>.

A common source line contact plug <NUM> may be disposed in the external pad bonding area PA. The common source line contact plug <NUM> may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line <NUM>. A first metal layer 2350a and a second metal layer 2360a may be stacked on an upper portion of the common source line contact plug <NUM>, sequentially. For example, an area in which the common source line contact plug <NUM>, the first metal layer 2350a, and the second metal layer 2360a are disposed may be defined as the external pad bonding area PA.

Input/output pads <NUM> and <NUM> may be disposed in the external pad bonding area PA. A lower insulating film <NUM> covering a lower surface of the first substrate <NUM> may be formed below the first substrate <NUM>, and a first input/output pad <NUM> may be formed on the lower insulating film <NUM>. The first input/output pad <NUM> may be connected to at least one of the plurality of circuit elements 2220a, 2220b, and 2220c disposed in the peripheral circuit region PERI through a first input/output contact plug <NUM>, and may be separated from the first substrate <NUM> by the lower insulating film <NUM>. In addition, a side insulating film may be disposed between the first input/output contact plug <NUM> and the first substrate <NUM> to electrically separate the first input/output contact plug <NUM> and the first substrate <NUM>.

An upper insulating film <NUM> covering the upper surface of the second substrate <NUM> may be formed on the second substrate <NUM> and a second input/output pad <NUM> may be disposed on the upper insulating film <NUM>. The second input/output pad <NUM> may be connected to at least one of the plurality of circuit elements 2220a, 2220b, and 2220c disposed in the peripheral circuit region PERI through a second input/output contact plug <NUM>. In the example embodiment, the second input/output pad <NUM> is electrically connected to a circuit element 2220a.

According to an embodiment, the second substrate <NUM> and the common source line <NUM> are not disposed in an area in which the second input/output contact plug <NUM> is disposed. Also, the second input/output pad <NUM> may not overlap the word-lines <NUM> in the vertical direction HD. The second input/output contact plug <NUM> may be separated from the second substrate <NUM> in the direction, parallel to the upper surface of the second substrate <NUM>, and may pass through the interlayer insulating layer <NUM> of the cell region CELL to be connected to the second input/output pad <NUM>.

According to an embodiment, the first input/output pad <NUM> and the second input/output pad <NUM> are selectively formed. For example, the memory device <NUM> may include only the first input/output pad <NUM> disposed on the first substrate <NUM> or the second input/output pad <NUM> disposed on the second substrate <NUM>. In an embodiments, the storage device <NUM> includes both the first input/output pad <NUM> and the second input/output pad <NUM>.

A metal pattern provided on an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit-line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI.

In the external pad bonding area PA, the memory device <NUM> may include a lower metal pattern 2273a, corresponding to an upper metal pattern 2372a formed in an uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern 2372a of the cell region CELL so as to be connected to each other, in an uppermost metal layer of the peripheral circuit region PERI. In the external pad bonding area PA, the memory device <NUM> may include lower bonding metals 2271a and 2271b connected to the lower metal pattern 2273a. In the peripheral circuit region PERI, the lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern 2372a, corresponding to the lower metal pattern 2273a formed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal pattern 2273a of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. Similarly, in the external pad bonding area PA, an upper bonding metal 2371a may be formed and may be electrically connected to the upper metal pattern 2372a. The upper metal pattern 2372a may be included in upper bonding metals 2371a and 2372a.

The lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b in the word-line bonding area WLBA. In the word-line bonding area WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit region PERI may be electrically connected to the upper bonding metals 2371b and 2372b of the cell region CELL by a Cu-to-Cu bonding.

Further, in the bit-line bonding area BLBA, an upper metal pattern <NUM>, corresponding to a lower metal pattern <NUM> formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same cross-sectional shape as the lower metal pattern <NUM> of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. A contact may not be formed on the upper metal pattern <NUM> formed in the uppermost metal layer of the cell region CELL. The lower metal pattern <NUM> may be included in lower bonding metals <NUM> and <NUM>.

In an example embodiment, corresponding to a metal pattern formed in an uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI, a reinforcement metal pattern having the same cross-sectional shape as the metal pattern may be formed in an uppermost metal layer in the other one of the cell region CELL and the peripheral circuit region PERI. In an embodiment, a contact is not formed on the reinforcement metal pattern.

The word-line voltages may be applied to at least one memory block in the cell region CELL through the lower bonding metals 2271b and 2272b in the peripheral circuit region PERI and upper bonding metals 2371b and 2372b of the cell region CELL.

<FIG> is a block diagram illustrating an electronic system including a semiconductor device according to an example embodiment.

Referring to <FIG>, an electronic system <NUM> may include a semiconductor device <NUM> and a controller <NUM> electrically connected to the semiconductor device <NUM>. The electronic system <NUM> may be a storage device including one or a plurality of semiconductor devices <NUM> or an electronic device including a storage device. For example, the electronic system <NUM> may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device that may include one or a plurality of semiconductor devices <NUM>.

The semiconductor device <NUM> may be a nonvolatile memory device, for example, the nonvolatile memory device illustrated with reference to <FIG>. The semiconductor device <NUM> may include a first structure 3100F and a second structure <NUM> on the first structure 3100F. The first structure 3100F may be a peripheral circuit structure including a decoder circuit <NUM>, a page buffer circuit <NUM>, and a logic circuit <NUM>. The second structure <NUM> may be a memory cell structure including a bit-line BL, a common source line CSL, word-lines WL, first and second upper gate lines UL1 and UL2, first and second lower gate lines LL1 and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure <NUM>, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit-line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be varied in accordance with example embodiments.

In an example embodiment, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, respectively, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 that may be connected with each other in serial. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation for erasing data stored in the memory cell transistors MCT through gate induced drain leakage (GIDL) phenomenon.

The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit <NUM> through first connection wirings <NUM> extending to the second structure <NUM> in the first structure 3100F. The bit-lines BL may be electrically connected to the page buffer circuit <NUM> through second connection wirings <NUM> extending to the second structure <NUM> in the first structure 3100F.

In the first structure 3100F, the decoder circuit <NUM> and the page buffer circuit <NUM> may perform a control operation for at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit <NUM> and the page buffer circuit <NUM> may be controlled by the logic circuit <NUM>. The semiconductor device <NUM> may communicate with the controller <NUM> through an input/output pad <NUM> electrically connected to the logic circuit <NUM>. The input/output pad <NUM> may be electrically connected to the logic circuit <NUM> through an input/output connection wiring <NUM> extending to the second structure <NUM> in the first structure 3100F.

The controller <NUM> may include a processor <NUM>, a NAND controller <NUM>, and a host interface <NUM>. The electronic system <NUM> may include a plurality of semiconductor devices <NUM>, and in this case, the controller <NUM> may control the plurality of semiconductor devices <NUM>.

The processor <NUM> may control operations of the electronic system <NUM> including the controller <NUM>. The processor <NUM> may be operated by firmware, and may control the NAND controller <NUM> to access the semiconductor device <NUM>. The NAND controller <NUM> may include a NAND interface <NUM> for communicating with the semiconductor device <NUM>. Through the NAND interface <NUM>, control command for controlling the semiconductor device <NUM>, data to be written in the memory cell transistors MCT of the semiconductor device <NUM>, data to be read from the memory cell transistors MCT of the semiconductor device <NUM>, etc., may be transferred. The host interface <NUM> may provide communication between the electronic system <NUM> and an outside host. When control command is received from the outside host through the host interface <NUM>, the processor <NUM> may control the semiconductor device <NUM> in response to the control command.

A nonvolatile memory device or a storage device according to an example embodiment may be packaged using various package types or package configurations.

The present disclosure may be applied to various electronic devices including a nonvolatile memory device. For example, the present disclosures may be applied to systems such as be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, etc..

Claim 1:
A nonvolatile memory device (400a-k) comprising:
a memory cell array (<NUM>), wherein the memory cell array (<NUM>) includes a plurality of word-lines (WL) stacked on a substrate (SUB), a plurality of memory cells (MC) provided in a plurality of channel holes (CH) extending in a vertical direction with respect to the substrate (SUB) and a word-line cut region (WLC) extending in a first horizontal direction and dividing the plurality of word-lines (WL) into a plurality of memory blocks (BLK); and
a control circuit (<NUM>) configured to control the memory cell array (<NUM>),
wherein a plurality of target memory cells coupled to each of the plurality of word-lines (WL) are grouped into outer cells and inner cells based on a location index of each of the plurality of memory cells (MC), a distance (D11) between the outer cell and the word-line cut region (WLC) being smaller than a distance (D12) between the inner cell and the word-line cut region (WLC), and
wherein the control circuit (<NUM>) is configured to control performance of a program operation on target memory cells coupled to a target word-line of the plurality of word-lines (WL) such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits, the first number being a natural number greater than zero and the second number being a natural number greater than the first number, and
wherein the control circuit (<NUM>) is configured to adjust levels of read voltages associated with a read operation performed on the target memory cell such that at least one of first threshold voltage distributions of the outer cells and at least one of second threshold voltage distributions of the inner cells are discriminated by a same read voltage.