Patent Description:
Document <CIT>proposes a quadrature signal generator including a polyphase filter outputting an IQ signal. The output of the polyphase filter is equipped with variable capacities to control the output behavior.

Document <CIT> proposes a quadrature LC tank based digitally controlled ring oscillator (DCO). The oscillator structure incorporates a plurality of stages, each stage including a buffer and a series LC tank. Four stages are coupled together to create a <NUM> degree phase shift around a loop. The high efficiency exhibited by these amplifiers results in very good phase noise performance of this oscillator. The oscillator utilizes a startup circuit to launch oscillation upon power on.

Document <CIT> proposes a quadrature clock generation with inverting electronic devices producing a Quadrature clock signal.

Document <CIT> proposes an integrated circuit comprising an inductor arrangement, the arrangement comprising four inductors adjacently located in a group and arranged to define two rows and two columns. The integrated circuit is configured to cause two of those inductors diagonally opposite from one another in the arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase.

Document <CIT> proposes a system and a method for distributing a clock signal. The systems for distributing the clock signal includes a plurality of resonant oscillators, each comprising an inductor. The system further comprises a differential clock grid that distributes the clock signal. The differential clock grid is coupled to the plurality of resonant oscillators and the clock signal, and the inductances of the inductors are configured such that a resonant frequency of the plurality of resonant oscillators is substantially equal to the frequency of the clock signal.

Exclusively passive multiphase clock generation using passive RC polyphase filters requires a sinusoidal input signal and buffers between each passive stage. Therefore, the phase accuracy of the exclusively passive multiphase clock generation is degraded.

Exclusively active multiphase clock generation using active circuits exhibits a higher power consumption than passive circuitry. Further, the active circuits suffer from a higher random variation than passive circuitry.

In other words, conventional multiphase clock generation suffers from high power consumption and phase inaccuracy.

Hence, there may be a desire for improved multiphase clock generation.

Accordingly, some particular examples are shown in the figures and will subsequently be described in detail.

<FIG> illustrates an example of apparatus <NUM> for generating a plurality of phase-shifted clock signals <NUM>-<NUM>,. The plurality of phase-shifted clock signals <NUM>-<NUM>,. , <NUM>-M may be any number M ≥ <NUM> of phase-shifted clock signals. For example, the plurality of phase-shifted clock signals <NUM>-<NUM>,. , <NUM>-M may be four or more phase-shifted clock signals (i.e. M may be four).

The apparatus <NUM> comprises a first input node <NUM> configured to receive a first reference clock signal <NUM>, and a second input node <NUM> configured to receive a second reference clock signal <NUM>. Additionally, the apparatus <NUM> comprises a plurality of output nodes <NUM>-<NUM>,. , <NUM>-M each configured to output one of the plurality of phase-shifted clock signals <NUM>-<NUM>,.

The first reference clock signal <NUM> and the second reference clock signal <NUM> are input clock signals for the apparatus. The apparatus <NUM> is configured to generate the plurality of phase-shifted clock signals <NUM>-<NUM>,. , <NUM>-M based on the first reference clock signal <NUM> and the second reference clock signal <NUM>. The first reference clock signal <NUM> and the second reference clock signal <NUM> are identical signals that are phase-shifted with respect to each other (the phase shift may be any value > <NUM> ° and < <NUM> °). For example, the first reference clock signal <NUM> and the second reference clock signal <NUM> may be sinusoidal signals or square wave signals. The second reference clock signal <NUM> may be inverted with respect to the first reference clock signal <NUM> (i.e. the signals may be phase-shifted by <NUM> °).

A cascade of coupled clock generation circuits <NUM>-<NUM>,. , <NUM>-N is coupled between the input nodes <NUM>, <NUM> and the output nodes <NUM>-<NUM>,. The cascade of coupled clock generation circuits <NUM>-<NUM>,. , <NUM>-N is configured to generate the plurality of phase-shifted clock signals <NUM>-<NUM>,. , <NUM>-M based on the first reference clock signal <NUM> and the second reference clock signal <NUM>. The cascade of coupled clock generation circuits <NUM>-<NUM>,. , <NUM>-N may be any number N ≥ <NUM> of clock generation circuits coupled in series.

Each of the plurality of clock generation circuits <NUM>-<NUM>,. , <NUM>-N comprises a respective plurality of input nodes for receiving a plurality of input clock signals, and a respective plurality of output nodes for outputting a plurality of output clock signals. Each of the plurality of clock generation circuits <NUM>-<NUM>,. , <NUM>-N is configured to generate its respective output clock signals based on the respectively received input clock signals. For each of the plurality of clock generation circuits <NUM>-<NUM>,. , <NUM>-N, the respective plurality of input nodes may be any number L ≥ <NUM> of input nodes. For each of the plurality of clock generation circuits <NUM>-<NUM>,. , <NUM>-N, the respective plurality of output nodes may be any number K ≥ <NUM> of input nodes. In some examples, the respective number of input nodes and/or the respective number of output nodes of each of the plurality of clock generation circuits <NUM>-<NUM>,. , <NUM>-N may be equal to the number M of phase-shifted clock signals <NUM>-<NUM>,.

As can be seen from <FIG>, input nodes <NUM>-<NUM>-<NUM>,. , <NUM>-<NUM>-L of the first clock generation circuit <NUM>-<NUM> of the cascade of clock generation circuits <NUM>-<NUM>,. , <NUM>-N are coupled to the first input node <NUM> and the second input node <NUM>. Output nodes <NUM>-N-<NUM>,. , <NUM>-N-K of the last clock generation circuit <NUM>-N of the cascade of clock generation circuits <NUM>-<NUM>,. , <NUM>-N are coupled to the plurality of output nodes <NUM>-<NUM>,.

At least one of the plurality of clock generation circuits <NUM>-<NUM>,. , <NUM>-N is an active circuit, and at least one of the plurality of clock generation circuits <NUM>-<NUM>,. , <NUM>-N is a passive circuit. A passive clock generation circuit comprises exclusively passive electronic elements (components, devices). In other words, a passive clock generation circuit does not comprise any active electronic elements (components, devices). On the other hand, an active clock generation circuit comprises at least one active electronic element. A passive electronic component is a component incapable of controlling a current of an electrical signals by means of another electrical signal (an example for a passive device may be a resistor or a capacitor).

An active component is a component capable of electrically control electric charge flow (an example for an active device may be a transistor or a circuit based on transistors).

The apparatus <NUM>, hence, uses a combination of active and passive circuits to generate the plurality of phase-shifted clock signals <NUM>-<NUM>,. , <NUM>-M based on the first reference clock signal <NUM> and the second reference clock signal <NUM>. Compared to conventional exclusively active multiphase clock generation, the apparatus <NUM> may exhibit reduced power consumption and improved phase accuracy. Compared to conventional exclusively passive multiphase clock generation, the apparatus <NUM> may exhibit improved phase accuracy. Hence, the apparatus <NUM> may enable improved multiphase clock generation.

Within the cascade of clock generation circuits <NUM>-<NUM>,. , <NUM>-N, active and passive clock generation circuits may be arranged in any desired order (sequence). For example, the cascade of clock generation circuits <NUM>-<NUM>,. , <NUM>-N may comprise a plurality of passive clock generation circuits and a plurality of active clock generation circuits coupled alternatingly in series (e.g. two passive clock generation circuits and two active clock generation circuits may be coupled alternatingly in series). In some examples, the cascade of clock generation circuits <NUM>-<NUM>,. , <NUM>-N may comprise at least two passive clock generation circuits coupled in series. In other examples, the cascade of clock generation circuits <NUM>-<NUM>,. , <NUM>-N may comprise at least two active clock generation circuits coupled in series.

In some examples, the cascade of coupled clock generation circuits <NUM>-<NUM>,. , <NUM>-N may comprise two clock generation circuits (i.e. N = <NUM>). In this configuration, the first clock generation circuit <NUM>-<NUM> of the cascade of clock generation circuits <NUM>-<NUM>,. , <NUM>-N is a passive circuit, and the last clock generation circuit <NUM>-<NUM> of the cascade of clock generation circuits <NUM>-<NUM>,. , <NUM>-N is an active circuit.

In other examples, the cascade of coupled clock generation circuits <NUM>-<NUM>,. , <NUM>-N may comprise at least three, four, five, six, seven, eight, sixteen or more clock generation circuits.

The thus generated plurality of phase-shifted clock signals <NUM>-<NUM>,. , <NUM>-M may be phase shifted by a predetermined phase shift with respect to each other. For example, the phase shift may be equal to <MAT>.

An example for an active clock generation circuit is an injection-locked oscillator. However, the proposed architecture is not limited to using injection-locked oscillators as active clock generation circuits. In general, any active clock generation circuit comprising at least one active electronic element may be used.

An example for a passive clock generation circuit is a RC polyphase filter, wherein the number of polyphases of the RC polyphase filter is equal to the number the plurality of phase-shifted clock signals. The RC polyphase filter comprises for each polyphase a resistive element (R) and a capacitive element (C) coupled in parallel between the respective input node and the respective output node for the polyphase. However, the proposed architecture is not limited to using RC polyphase filters as passive clock generation circuits. In general, any active clock generation circuit free from active electronic elements may be used.

Another example of an apparatus <NUM> for generating a plurality of phase-shifted clock signals is illustrated in <FIG>. The apparatus <NUM> is an N-stages hybrid multiphase clock generator.

The apparatus <NUM> comprises a cascade of clock generation circuits <NUM>-<NUM>,. The cascade of clock generation circuits <NUM>-<NUM>,. , <NUM>-N comprises a plurality of passive clock generation circuits and a plurality of active clock generation circuits coupled alternatingly in series. The active clock generation circuits <NUM>-i ( <MAT> & i ≤ N - <NUM>) are injection-locked oscillators, whereas the passive clock generation circuits <NUM>-j ( <MAT> & <NUM> ≤ N) are RC polyphase filters.

The apparatus <NUM> comprises a first input node <NUM> configured to receive a first reference clock signal <NUM>, and a second input node <NUM> configured to receive a second reference clock signal <NUM>. The second reference clock signal <NUM> is inverted with respect to the first reference clock signal <NUM>.

The input nodes of the first active clock generation circuit <NUM>-<NUM> are coupled to the first input node <NUM> and the second input node <NUM>. The output nodes of the first active clock generation circuit <NUM>-<NUM> are coupled to the input nodes of the first passive clock generation circuit <NUM>-<NUM>. The output nodes of the first passive clock generation circuit <NUM>-<NUM> are coupled to the input nodes of the next active clock generation circuit (not illustrated).

The output nodes of the last active clock generation circuit <NUM>-N-<NUM> are coupled to the input nodes of the last passive clock generation circuit <NUM>-N. The output nodes of the of the last passive clock generation circuit <NUM>-N are coupled to the output nodes <NUM>-<NUM>,. , <NUM>-M of the apparatus <NUM>. Accordingly, the apparatus <NUM> allows to output M phase-shifted clock signals <NUM>-<NUM>,. , <NUM>-M with high phase accuracy.

<FIG> illustrates an apparatus <NUM> for generating four phase-shifted clock signals. The apparatus <NUM> is similar to the above described apparatus <NUM>. In contrast to the apparatus <NUM>, the number of generated phase-shifted clock signals is set to four.

The apparatus <NUM> comprises a cascade of clock generation circuits <NUM>-<NUM>,. The cascade of clock generation circuits <NUM>-<NUM>,. , <NUM>-N comprises a plurality of passive clock generation circuits and a plurality of active clock generation circuits coupled alternatingly in series. The active clock generation circuits <NUM>-i ( <MAT> & i ≤ N - <NUM>) are tetrahedral injection-locked oscillators, whereas the passive clock generation circuits <NUM>-j (j = <MAT> & <NUM> ≤ N) are RC polyphase filters for four polyphases.

The output nodes of the last active clock generation circuit <NUM>-N-<NUM> are coupled to the input nodes of the last passive clock generation circuit <NUM>-N. The output nodes of the of the last passive clock generation circuit <NUM>-N are coupled to the output nodes <NUM>-<NUM>,. , <NUM>-<NUM> of the apparatus <NUM>. Accordingly, the apparatus <NUM> allows to output four phase-shifted clock signals <NUM>-<NUM>,. , <NUM>-<NUM> with high phase accuracy.

<FIG> illustrates another apparatus <NUM> for generating four phase-shifted clock signals. The apparatus <NUM> is similar to the above described apparatus <NUM>. In contrast to the apparatus <NUM>, number of clock generation circuits is set to four in the apparatus <NUM>.

The apparatus <NUM> comprises a cascade of four clock generation circuits <NUM>-<NUM>,. , <NUM>-<NUM>. The cascade of clock generation circuits <NUM>-<NUM>,. , <NUM>-<NUM> comprises two passive clock generation circuits and two active clock generation circuits coupled alternatingly in series. The active clock generation circuits <NUM>-<NUM> and <NUM>-<NUM> are tetrahedral injection-locked oscillators, whereas the passive clock generation circuits <NUM>-<NUM> and <NUM>-<NUM> are RC polyphase filters for four polyphases.

The input nodes of the first active clock generation circuit <NUM>-<NUM> are coupled to the first input node <NUM> and the second input node <NUM>. The output nodes of the first active clock generation circuit <NUM>-<NUM> are coupled to the input nodes of the first passive clock generation circuit <NUM>-<NUM>. The output nodes of the first passive clock generation circuit <NUM>-<NUM> are coupled to the input nodes of the second active clock generation circuit <NUM>-<NUM>. The output nodes of the second active clock generation circuit <NUM>-<NUM> are coupled to the input nodes of the second passive clock generation circuit <NUM>-<NUM>.

The output nodes of the of the second passive clock generation circuit <NUM>-<NUM> are coupled to the output nodes <NUM>-<NUM>,. , <NUM>-<NUM> of the apparatus <NUM>. Accordingly, the apparatus <NUM> allows to output four phase-shifted clock signals <NUM>-<NUM>,. , <NUM>-<NUM> with high phase accuracy.

An example of an implementation using multiphase clock signal generation according to one or more aspects of the architecture described above in connection with <FIG> or one or more examples described above in connection with <FIG> is illustrated in <FIG> schematically illustrates an example of a radio base station <NUM> (e.g. for a femtocell, a picocell, a microcell or a macrocell) comprising an apparatus <NUM> for generating a plurality of phase-shifted clock signals as proposed.

The apparatus <NUM> for generating a plurality of phase-shifted clock signals is part of a receiver <NUM> (being an example for an electronic system). The receiver <NUM> additionally comprises at least one electronic device <NUM> coupled to at least part of the plurality of output nodes of the apparatus <NUM> for receiving at least part of the plurality of phase-shifted clock signals. For example, the at least one electronic device <NUM> may be one of an analog-to-digital converter or a Radio Frequency (RF) mixer. If the electronic device <NUM> is a RF mixer such as a quadrature mixer or an image rejection mixer, the apparatus <NUM> may allow to supply the plurality of phase-shifted clock signals with very precise phase alignment to the RF mixer and, hence, meet the requirements of the RF mixer.

The receiver <NUM> is coupled to an antenna element <NUM> of the base station <NUM> (either directly or indirectly via one or more intermediate elements such as a filter or a Low Noise Amplifier, LNA).

Further, the base station <NUM> comprises a transmitter <NUM> configured to generate a RF transmit signal. The transmitter <NUM> may use the antenna element <NUM> or another antenna element (not illustrated) of the base station <NUM> for radiating the RF transmit signal to the environment. Alternatively or additionally, the transmitter <NUM> (being another example for an electronic system) may comprise an apparatus for generating a plurality of phase-shifted clock signals as proposed. For example, a digital-to-analog converter or a RF mixer of the transmitter <NUM> may receive and use at least part of the plurality of phase-shifted clock signals generated by the apparatus for generating a plurality of phase-shifted clock signals.

To this end, a base station with improved multiphase clock signal generation may be provided.

The base station <NUM> may comprise further elements such as, e.g., a baseband processor, an application processor, memory, a network controller, a user interface, power management circuitry, a satellite navigation receiver, a network interface controller or power tee circuitry.

In some aspects, the application processor may include one or more Central Processing Unit CPU cores and one or more of cache memory, a Low-DropOut (LDO) voltage regulator, interrupt controllers, serial interfaces such as Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I<NUM>C) or universal programmable serial interface module, Real Time Clock (RTC), timer-counters including interval and watchdog timers, general purpose Input-Output (IO), memory card controllers such as Secure Digital (SD)/ MultiMedia Card (MMC) or similar, Universal Serial Bus (USB) interfaces, Mobile Industry Processor Interface Alliance (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports.

In some aspects, the baseband processor may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip module containing two or more integrated circuits.

In some aspects, the memory may include one or more of volatile memory including Dynamic Random Access Memory (DRAM) and/or Synchronous Dynamic Random Access Memory (SDRAM), and Non-Volatile Memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), Phase change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM) and/or a three-dimensional crosspoint (3D XPoint) memory. The memory may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.

In some aspects, the power management integrated circuitry may include one or more of voltage regulators, surge protectors, power alarm detection circuitry and one or more backup power sources such as a battery or capacitor. Power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions.

In some aspects, the power tee circuitry may provide for electrical power drawn from a network cable to provide both power supply and data connectivity to the base station using a single cable.

In some aspects, the network controller may provide connectivity to a network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection which is one of electrical (commonly referred to as copper interconnect), optical or wireless.

In some aspects, the satellite navigation receiver module may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the Global Positioning System (GPS), GLObalnaya NAvigatSionnaya Sputnikovaya Sistema (GLONASS), Galileo and/or BeiDou. The receiver may provide data to the application processor which may include one or more of position data or time data. The application processor may use time data to synchronize operations with other radio base stations.

In some aspects, the user interface may include one or more of physical or virtual buttons, such as a reset button, one or more indicators such as Light Emitting Diodes (LEDs) and a display screen.

Another example of an implementation using multiphase clock signal generation according to one or more aspects of the architecture described above in connection with <FIG> or one or more examples described above in connection with <FIG> is illustrated in <FIG> schematically illustrates an example of a mobile device <NUM> (e.g. mobile phone, smartphone, tablet-computer, or laptop) comprising an apparatus <NUM> for generating a plurality of phase-shifted clock signals as proposed.

The apparatus <NUM> for generating a plurality of phase-shifted clock signals is part of a receiver <NUM> (being an example for an electronic system). The receiver <NUM> additionally comprises at least one electronic device <NUM> coupled to at least part of the plurality of output nodes of the apparatus <NUM> for receiving at least part of the plurality of phase-shifted clock signals. For example, the at least one electronic device <NUM> may be one of an analog-to-digital converter or a RF mixer. If the electronic device <NUM> is a RF mixer such as a quadrature mixer or an image rejection mixer, the apparatus <NUM> may allow to supply the plurality of phase-shifted clock signals with very precise phase alignment to the RF mixer and, hence, meet the requirements of the RF mixer.

The receiver <NUM> is coupled to an antenna element <NUM> of the mobile device <NUM> (either directly or indirectly via one or more intermediate elements such as a filter or an LNA).

Further, the mobile device <NUM> comprises a transmitter <NUM> configured to generate a RF transmit signal. The transmitter <NUM> may use the antenna element <NUM> or another antenna element (not illustrated) of the mobile device <NUM> for radiating the RF transmit signal to the environment. Alternatively or additionally, the transmitter <NUM> (being another example for an electronic system) may comprise an apparatus for generating a plurality of phase-shifted clock signals as proposed. For example, a digital-to-analog converter or a RF mixer of the transmitter <NUM> may receive and use at least part of the plurality of phase-shifted clock signals generated by the apparatus for generating a plurality of phase-shifted clock signals.

To this end, a mobile device with improved multiphase clock signal generation may be provided.

The mobile device <NUM> may comprise further elements such as, e.g., a baseband processor, memory, a connectivity module, a Near Field Communication (NFC) controller, an audio driver, a camera driver, a touch screen, a display driver, sensors, removable memory, a power management integrated circuit or a smart battery.

In some aspects, the application processor may include, for example, one or more CPU cores and one or more of cache memory, LDO regulators, interrupt controllers, serial interfaces such as SPI, I<NUM>C or universal programmable serial interface module, RTC, timer-counters including interval and watchdog timers, general purpose input-output (IO), memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces and JTAG test access ports.

In some aspects, the baseband module may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and/or a multi-chip module containing two or more integrated circuits.

The wireless communication circuits using multiphase clock signal generation according to the proposed architectures or one or more of the examples described above may be configured to operate according to one of the 3GPP-standardized mobile communication networks or systems. The mobile or wireless communication system may correspond to, for example, a <NUM> NR, a Long-Term Evolution (LTE), an LTE-Advanced (LTE-A), High Speed Packet Access (HSPA), a Universal Mobile Telecommunication System (UMTS) or a UMTS Terrestrial Radio Access Network (UTRAN), an evolved-UTRAN (e-UTRAN), a Global System for Mobile communication (GSM), an Enhanced Data rates for GSM Evolution (EDGE) network, or a GSM/EDGE Radio Access Network (GERAN). Alternatively, the wireless communication circuits may be configured to operate according to mobile communication networks with different standards, for example, a Worldwide Inter-operability for Microwave Access (WI-MAX) network IEEE <NUM> or Wireless Local Area Network (WLAN) IEEE <NUM>, generally an Orthogonal Frequency Division Multiple Access (OFDMA) network, a Time Division Multiple Access (TDMA) network, a Code Division Multiple Access (CDMA) network, a Wideband-CDMA (WCDMA) network, a Frequency Division Multiple Access (FDMA) network, a Spatial Division Multiple Access (SDMA) network, etc..

Claim 1:
An apparatus (<NUM>) for generating a plurality of phase-shifted clock signals, comprising:
a first input node (<NUM>) configured to receive a first reference clock signal (<NUM>);
a second input node (<NUM>) configured to receive a second reference clock signal (<NUM>);
a plurality of output nodes (<NUM>-<NUM>, ..., <NUM>-M) each configured to output one of the plurality of phase-shifted clock signals (<NUM>-<NUM>, ..., <NUM>-M); and
a cascade of coupled clock generation circuits (<NUM>-<NUM>, ..., <NUM>-N) configured to generate the plurality of phase-shifted clock signals (<NUM>-<NUM>, ..., <NUM>-M) based on the first reference clock signal (<NUM>) and the second reference clock signal (<NUM>), wherein input nodes of the first clock generation circuit (<NUM>-<NUM>) of the cascade of clock generation circuits (<NUM>-<NUM>, ..., <NUM>-N) are coupled to the first input node (<NUM>) and the second input node (<NUM>), wherein output nodes of the last clock generation circuit (<NUM>-N) of the cascade of clock generation circuits (<NUM>-<NUM>, ..., <NUM>-N) are coupled to the plurality of output nodes (<NUM>-<NUM>, ..., <NUM>-M), wherein at least one of the plurality of clock generation circuits (<NUM>-<NUM>, ..., <NUM>-N) is an active circuit, and wherein at least one of the plurality of clock generation circuits (<NUM>-<NUM>, ..., <NUM>-N) is a passive circuit.