Patent Description:
Integrated device technologies have exponentially advanced over the past <NUM> years. More specifically directed to the microprocessor fields, starting with <NUM>-bit, single instruction, <NUM>-micrometer devices, the advances in semiconductor fabrication technologies have enabled designers to provide increasingly more complex devices in terms of architecture and density. In the <NUM>'s and <NUM>'s, so-called pipeline microprocessors and superscalar microprocessors were developed comprising millions of transistors on a single die. And now <NUM> years later, <NUM>-bit, <NUM>-nanometer devices are being produced that have billions of transistors on a single die, and which comprise multiple microprocessor cores for the processing of data.

One requirement that has persisted since these early microprocessors were produced is the need to initialize these devices with configuration data when they are powered up or when they are reset. For example, many architectures enable devices to be configured to execute at one of many selectable frequencies and/or voltages. Other architectures require that each device have a serial number and other information that can be read via execution of an instruction. Yet other devices require initialization data for internal registers and control circuits. Still other microprocessors, particularly that with on-board cache memories, utilize repair data to implement redundant circuits within these memories to correct for fabrication errors.

As one skilled in the art will appreciate, designers have traditionally employed semiconductor fuse arrays on-die to store and provide initial configuration and repair data. These fuse arrays are generally programmed by blowing selected fuses therein after a part has been fabricated, and the arrays contain thousands of bits of information which are read by a corresponding device upon power-up/reset to initialize and configure the device for operation.

As device complexity has increased over the past years, the amount of configuration/repair data that is required for a typical device has proportionately increased. Yet, as one skilled in the art will appreciate, though transistor size shrinks in proportion to the semiconductor fabrication process employed, semiconductor fuse size increases due to the unique requirements for programming fuses on die. This phenomenon, in and of itself, is a problem for designers, who are prevalently constrained by real estate and power considerations. In other words, there is just not enough real estate on a given die to fabricate a huge fuse array.

In addition, the ability to fabricate multiple device cores on a single die has geometrically exacerbated the problem, because configuration requirements for each of the cores result in a requirement for a number of fuses on die, in a single array or distinct arrays, that is proportional to the number of cores disposed thereon.

Furthermore, as one skilled in the art will appreciate, multiple-core devices utilize complex power-saving modes of operation that result in one or more of the cores being powered down in a so-called power gating event (or, "sleep mode") when not in use. Consequently, when a core is powered up following a power gating event, the same requirement for initialization, configuration, and repair persists, except that initialization speed requirements are much more stringent.

Therefore, what is needed is apparatus and methods that enable configuration/repair data to be stored and provided to a multi-core device that require significantly less real estate and power on a single die than that which has heretofore been provided.

In addition, what is needed is a fuse array mechanism that can store and provide significantly more configuration/repair data than current techniques while requiring the same or less real estate on a multi-core die.

Furthermore, what is needed is a technique that facilitates prompt initialization, configuration, and repair of a multi-core device following a power gating event.

<CIT> discloses an integrated circuit employing a plurality of functional blocks, such as but not limited to, processors (e.g., cores), and an on-die distributed programmable passive variable resistance memory array configured to provide configuration information for each of the plurality of functional blocks. A corresponding sub-portion of the on-die distributed programmable passive variable resistance memory array is fabricated in layers above each respective plurality of functional blocks. The on-die distributed programmable passive variable resistance memory array is used as either non-volatile prepackage configuration information store, or a non-volatile post-package configuration information store that may allow dynamic changing of hardware configuration of the functional blocks both during normal operation and prior to die packaging. A method for making the same is also disclosed.

The present invention provides a superior technique for restoring configuration data following a power gating event. An apparatus for providing configuration data to an integrated circuit is defined in the claims as well as a method for configuring an integrated circuit. Optional embodiments are set out in the dependent claims.

Regarding industrial applicability, the present invention is implemented within a MICROPROCESSOR which may be used in a general purpose or special purpose computing device.

These and other objects, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings where:.

Exemplary and illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification, for those skilled in the art will appreciate that in the development of any such actual embodiment, numerous implementation specific decisions are made to achieve specific goals, such as compliance with system-related and business related constraints, which vary from one implementation to the next. In addition, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. Various modifications to the preferred embodiment will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

The present invention will now be described with reference to the attached figures. Various structures, systems, and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present invention with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase (i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art) is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning (i.e., a meaning other than that understood by skilled artisans) such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.

In view of the above background discussion on device fuse arrays and associated techniques employed within present day integrated circuits for providing configuration data during initial power-up, a discussion of the limitations and disadvantages of those techniques will be presented with reference to <FIG>. Following this, a discussion of arrangements useful for understanding the invention will be presented with reference to <FIG>. The present invention overcomes all of the limitations and disadvantages discussed below by providing apparatus and methods for employing compressed configuration in a multi-core die which utilize less power and real estate on the multi-core die, which provide for expeditious restoral of configuration and repair data following power gating events, and which are more reliable than that which has heretofore been provided.

Integrated Circuit (IC): A set of electronic circuits fabricated on a small piece of semiconductor material, typically silicon. An IC is also referred to as a chip, a microchip, or a die.

Central Processing Unit (CPU): The electronic circuits (i.e., "hardware") that execute the instructions of a computer program (also known as a "computer application," "application program," "program," or "application") by performing operations on data that include arithmetic operations, logical operations, and input/output operations.

Microprocessor: An electronic device that functions as a CPU on a single integrated circuit. A microprocessor receives digital data as input, processes the data according to instructions fetched from a memory (either on-die or off-die), and generates results of operations prescribed by the instructions as output. A general purpose microprocessor may be employed in devices including, but not limited to, a desktop, mobile, or tablet computer, and may be utilized for tasks such as, but not limited to, computation, text editing, multimedia display, and Internet browsing. A microprocessor may also be disposed in an embedded system to control a wide variety of devices that include appliances, mobile telephones, smart phones, and industrial control devices.

Multi-Core Processor: Also known as a multi-core microprocessor, a multi-core processor is a microprocessor having multiple CPUs (also known as "cores") fabricated on a single integrated circuit.

Instruction Set Architecture (ISA) or Instruction Set: A part of a computer architecture related to programming that includes data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and input/output. An ISA includes a specification of the set of opcodes (i.e., machine language instructions), and the native commands implemented by a particular CPU.

x86-Compatible Microprocessor: A microprocessor capable of executing computer applications that are programmed according to the x86 ISA.

Microcode: A term employed to refer to a plurality of micro instructions. A micro instruction (also referred to as a "native instruction") is an instruction at the level that a microprocessor sub-unit executes. Exemplary sub-units include integer units, floating point units, MMX units, and load/store units. For example, micro instructions are directly executed by a reduced instruction set computer (RISC) microprocessor. For a complex instruction set computer (CISC) microprocessor such as an x86-compatible microprocessor, x86 instructions are translated into associated micro instructions, and the associated micro instructions are directly executed by a sub-unit or sub-units within the CISC microprocessor.

Fuse: A conductive structure typically arranged as a filament which can be broken at select locations by applying a voltage across the filament and/or current through the filament. Fuses may be deposited at specified areas across a die topography using well known fabrication techniques to produce filaments at all potential programmable areas. A fuse structure is blown (or unblown) subsequent to fabrication to provide for desired programmability of a corresponding device disposed on the die.

Turning to <FIG>, a block diagram <NUM> is presented illustrating a present day microprocessor core <NUM> that includes a fuse array <NUM> for providing configuration data to the microprocessor core <NUM>. The fuse array <NUM> comprises a plurality of semiconductor fuses (not shown) typically arranged in groups known as banks. The fuse array <NUM> is coupled to reset logic <NUM> that includes both reset circuits <NUM> and reset microcode <NUM>. The reset logic <NUM> is coupled to control circuits <NUM>, microcode registers <NUM>, microcode patches elements <NUM>, and cache correction elements <NUM>. An external reset signal RESET is coupled to the microprocessor core <NUM> and is routed to the reset logic <NUM>.

As one skilled in the art will appreciate, fuses (also called "links" or "fuse structures") are employed in a vast number of present day integrated circuit devices to provide for configuration of the devices after the devices have been fabricated. For example, consider that the microprocessor core <NUM> of <FIG> is fabricated to provide functionality selectively either as a desktop device or a mobile device. Accordingly, following fabrication, prescribed fuses within the fuse array <NUM> may be blown to configure the device as, say, a mobile device. Accordingly, upon assertion of RESET, the reset logic <NUM> reads the state of the prescribed fuses in the fuse array <NUM> and the reset circuits <NUM> (rather than reset microcode <NUM>, in this example) enable corresponding control circuits <NUM> that deactivate elements of the core <NUM> exclusively associated with desktop operations and activate elements of the core <NUM> exclusively associated with mobile operations. Consequently, the core <NUM> is configured upon power-up reset as a mobile device. In addition, the reset logic <NUM> reads the state of the other fuses in the fuse array <NUM> and the reset circuits <NUM> (rather than reset microcode <NUM>, in this example) enable corresponding cache correction circuits <NUM> provide corrective mechanisms for one or more cache memories associated (not shown) with the core <NUM>. Consequently, the core <NUM> is configured upon power-up reset as a mobile device and corrective mechanisms for its cache memories are in place.

The above example is merely one of many different uses for configuration fuses in an integrated circuit device such as a microprocessor core <NUM> of <FIG>. One skilled in the art will appreciate that other uses for configuration fuses include, but are not limited to, configuration of device specific data (e.g., serial numbers, unique cryptographic keys, architecture mandated data that can be accessed by users, speed settings, voltage settings), initialization data, and patch data. For example, many present day devices execute microcode and often require initialization of registers <NUM> that are read by the microcode. Such initialization data may be provided by microcode register fuses (not shown) within the fuse array <NUM>, which are read upon reset and provided to the microcode registers <NUM> by the reset logic <NUM> (using either the reset circuits <NUM>, the reset microcode <NUM>, or both elements <NUM>-<NUM>). For purposes of the present application, the reset circuits <NUM> comprise hardware elements that provide certain types of configuration data, which cannot be provided via the execution of the reset microcode <NUM>. The reset microcode <NUM> comprises a plurality of micro instructions disposed within an internal microcode memory (not shown) that is executed upon reset of the core <NUM> to perform functions corresponding to initialization of the core <NUM>, those functions including provision of configuration data that is read from the fuse array <NUM> to elements such as microcode registers <NUM> and microcode patch mechanisms <NUM>. The criteria for whether certain types of configuration data provided via fuses can be distributed to the various elements <NUM>-<NUM> in the core <NUM> via reset microcode <NUM> or not is a function primarily of the specific design of the core <NUM>. It is not the intent of the present application to provide a comprehensive tutorial on specific configuration techniques that are employed to initialize integrated circuit devices, for one skilled in the art will appreciate that for a present day microprocessor core <NUM> the types of configurable elements <NUM>-<NUM> generally fall into four categories as are exemplified in <FIG>: control circuits, microcode registers, microcode patch mechanisms, and cache correction mechanisms. Furthermore, one skilled will appreciate that the specific values of the configuration data significantly vary based upon the specific type of data. For instance, a <NUM>-bit control circuit <NUM> may include ASCII data that prescribes a serial number for the core <NUM>. Another <NUM>-bit control register may have <NUM> different speed settings, only one of which is asserted to specify an operating speed for the core <NUM>. Microcode registers <NUM> may typically be initialized to all zeros (i.e. logic low states) or to all ones (i.e., logic high states). Microcode patch mechanisms <NUM> may include an approximately uniform distribution of ones and zeros to indicate addresses in a microcode ROM (not shown) along with replacement microcode values for those addresses. Finally, cache correction (i.e., "repair") mechanisms may comprise very sparse settings of ones to indicate substitution control signals to replace a certain cache sub-bank element (i.e., a row or a column) with a particular replacement sub-bank element to enable the repair of one or more cache memories.

Fuse arrays <NUM> provide an excellent means for configuring a device such as a microprocessor core <NUM> subsequent to fabrication of the device. By blowing selected fuses in the fuse array <NUM>, the core <NUM> can be configured for operation in its intended environment. Yet, as one skilled in the art will appreciate, operating environments may change following programming of the fuse array <NUM>. Business requirements may dictate that a device <NUM> originally configured as, say, as desktop device <NUM>, be reconfigured as a mobile device <NUM>. Accordingly, designers have provided techniques that utilize redundant banks of fuses within the fuse array <NUM> to provide for "unblowing" selected fuses therein, thus enabling the device <NUM> to be reconfigured, fabrication errors to be corrected, and etc. These redundant array techniques will now be discussed with reference to <FIG>.

Referring now to <FIG>, a block diagram <NUM> is presented depicting a fuse array <NUM> within the microprocessor core <NUM> of <FIG> including redundant fuse banks <NUM> RFB1-RFBN that that may be blown subsequent to blowing first fuse banks <NUM> PFB1-PFBN within the fuse array <NUM>. Each of the fuse banks <NUM> PFB1-PFBN, RFB1-RFBN comprises a prescribed number of individual fuses <NUM> corresponding to specific design of the core <NUM>. For example, the number of fuses <NUM> in a given fuse bank <NUM> may be <NUM> fuses <NUM> in a <NUM>-bit microprocessor core <NUM> to facilitate provision of configuration data in a format that is easily implemented in the core <NUM>.

The fuse array <NUM> is coupled to a set of registers <NUM>-<NUM> that are typically disposed within reset logic in the core <NUM>. A primary register PR1 is employed to read one of the first fuse banks PFB1-PFBN (say, PFB3 as is shown in the diagram <NUM>) and a redundant register RR1 is employed to read a corresponding one of the redundant fuse banks RFB1-RFBN. The registers <NUM>-<NUM> are coupled to exclusive-OR logic <NUM> that generates an output FB3.

In operation, subsequent to fabrication of the core <NUM>, the first fuse banks PFB1-PFBN are programmed by known techniques with configuration data for the core <NUM>. The redundant fuse banks RFB1-RFBN are not blown and remain at a logic low state for all fuses therein. Upon power-up/reset of the core <NUM>, both the first fuse banks PFB1-PFBN and the redundant fuse banks RFB1-RFBN are read as required for configuration into the primary and redundant registers <NUM>-<NUM>, respectively. The exclusive-OR logic <NUM> generates the output FB3 that is a logical exclusive-OR result of the contents of the registers <NUM>-<NUM>. Since all of the redundant fuse banks are unblown (i.e., logic low states), the output FB3 value is simply that which was programmed into the first fuse banks PFB1-PFBN subsequent to fabrication.

Consider now, though, that design or business requirements dictate that some of the information that was programmed into the first fuse banks PFB1-PFBN needs to change. Accordingly, a programming operation is performed to blow corresponding fuses <NUM> within the redundant fuse banks RFB1-RFBN in order to change the information that is read at power-up. By blowing a fuse <NUM> in a selected redundant bank RFB1-RFBN, the value of a corresponding fuse <NUM> in the primary fuse bank PFB1-PFBN is logically complemented.

The mechanism of <FIG> may be employed to provide for "reblow" of fuses <NUM> within a device <NUM>, but as one skilled in the art will appreciate, a given fuse <NUM> may only be reblown one time as there is only one set of redundant fuse banks RFB1-RFBN. To provide for additional reblows, a corresponding number of additional fuse banks <NUM> and registers <NUM>-<NUM> must be added to the part <NUM>.

Heretofore, the fuse array mechanisms as discussed above with reference to <FIG> has provided enough flexibility to sufficiently configure microprocessor cores and other related devices, while also allowing for a limited number of reblows. This is primarily due to the fact that former fabrication technologies, say <NUM> nanometer and <NUM> nanometer processes, allow ample real estate on a die for the implementation of enough fuses to provide for configuration of a core <NUM> disposed on the die. However, the present inventors have observed that present day techniques are limited going forward due to two significant factors. First, the trend in the art is to dispose multiple device cores <NUM> on a single die to increase processing performance. These so-called multi-core devices may include, say, <NUM>-<NUM> individual cores <NUM>, each of which must be configured with fuse data upon power-up/reset. Accordingly, for a <NUM>-core device, four fuse arrays <NUM> are required in that some of the data associated with individual cores may vary (e.g., cache correction data, redundant fuse data, etc.). Secondly, as one skilled in the art will appreciate, as fabrication process technologies shrink to, say, <NUM> nanometers, while transistor size shrinks accordingly, fuse size increases, thus requiring more die real estate to implement the same size fuse array on a <NUM>-nanometer die opposed to that on a <NUM>-nanometer die.

Both of the above limitations, and others, pose significant challenges to device designers, and more specifically to multi-core device designers, and the present inventors note that significant improvements over conventional device configuration mechanisms can be implemented in accordance with the present invention, which allows for programming of individual cores in a multi-core device along with substantial increases in cache correction and fuse reprogramming ("reblow") elements. Arrangements useful for understanding the invention will be discussed with reference to <FIG>. The present invention will be discussed with reference to <FIG>.

Turning to <FIG>, a block diagram is presented featuring a system <NUM> that provides for compression and decompression of configuration/repair data for a multi-core device. The multi-core device comprises a plurality of cores <NUM> disposed on a die <NUM>. For illustrative purposes, four cores <NUM> CORE <NUM>-CORE <NUM> are depicted on the die <NUM>, although this arrangement contemplates various numbers of cores <NUM> disposed on the die <NUM>. In one embodiment, all the cores <NUM> share a single cache memory <NUM> that is also disposed on the die <NUM>. A single programmable fuse array <NUM> is also disposed on the die <NUM> and each of the cores <NUM> are configured to access the fuse array <NUM> to retrieve and decompress configuration data as described above during power-up/reset.

In one embodiment, the cores <NUM> comprise microprocessor cores configured as a multi-core microprocessor <NUM>. In another embodiment, the multi-core microprocessor <NUM> is configured as an x86-compatible multi-core microprocessor. In yet another embodiment, the cache <NUM> comprises a level <NUM> (L2) cache <NUM> associated with the microprocessor cores <NUM>. In one embodiment, the fuse array <NUM> comprises <NUM> (<NUM>) individual fuses (not shown), although other numbers of fuses are contemplated. In a single-core embodiment, only one core <NUM> is disposed on the die <NUM> and the core <NUM> is coupled to the cache <NUM> and physical fuse array <NUM>. The present inventors note that although features and functions of the present invention will henceforth be discussed in the context of a multi-core device <NUM>, these features and functions are equally applicable to a single-core embodiment as well.

The system <NUM> also includes a device programmer <NUM> that includes a compressor <NUM> that is coupled to a virtual fuse array <NUM>. In one embodiment, the device programmer <NUM> may comprise a CPU (not shown) that is configured to process configuration data and to program the fuse array <NUM> following fabrication of the die <NUM> according to well known programming techniques. The CPU may be integrated into a wafer test apparatus that is employed to test the device die <NUM> following fabrication. In one embodiment, the compressor <NUM> may comprise an application program that executes on the device programmer <NUM> and the virtual fuse array <NUM> may comprise locations within a memory that is accessed by the compressor <NUM>. The virtual fuse array <NUM> includes a plurality of virtual fuse banks <NUM>, that each comprise a plurality of virtual fuses <NUM>. In one embodiment the virtually fuse array <NUM> comprises <NUM> virtual fuse banks <NUM> that each comprise <NUM> virtual fuses <NUM>, resulting in a virtual array <NUM> that is <NUM> Kb in size.

Operationally, configuration information for the device <NUM> is entered into the virtual fuse array <NUM> as part of the fabrication process, and as is described above with reference to <FIG>. Accordingly, the configuration information comprises control circuits configuration data, initialization data for microcode registers, microcode patch data, and cache correction data. Further, as described above, the distributions of values for associated with each of the data types is substantially different from type to type. The virtual fuse array <NUM> is a logical representation of a fuse array (not shown) that comprises configuration information for each of the microprocessor cores <NUM> on the die <NUM> and correction data for each of the caches <NUM> on the die <NUM>.

After the information is entered into the virtual fuse array <NUM>, the compressor <NUM> reads the state of the virtual fuses <NUM> in each of the virtual fuse banks <NUM> and compresses the information using distinct compression algorithms corresponding to each of the data types to render compressed fuse array data <NUM>. In one embodiment, system data for control circuits is not compressed, but rather is transferred without compression. To compress microcode register data, a microcode register data compression algorithm is employed that is effective for compressing data having a state distribution that corresponds to the microcode register data. To compress microcode patch data, a microcode patch data compression algorithm is employed that is effective for compressing data having a state distribution that corresponds to the microcode patch data. To compress cache correction data, a cache correction data compression algorithm is employed that is effective for compressing data having a state distribution that corresponds to the cache correction data.

The device programmer <NUM> then programs the uncompressed and compressed fuse array data into the physical fuse array <NUM> on the die <NUM>.

Upon power-up/reset, each of the cores <NUM> may access the physical fuse array <NUM> to retrieve the uncompressed and compressed fuse array data, and reset circuits/microcode (not shown) disposed within each of the cores <NUM> distributes the uncompressed fuse array data, and decompresses the compressed fuse array data according to distinct decompression algorithms corresponding to each of the data types noted above to render values originally entered into the virtual fuse array <NUM>. The reset circuits/microcode then enter the configuration information into control circuits (not shown), microcode registers (not shown), patch elements (not shown), and cache correction elements (not shown).

Advantageously, the fuse array compression system <NUM> according to the present invention enables device designers to employ substantially fewer numbers of fuses in a physical fuse array <NUM> over that which has heretofore been provided, and to utilize the compressed information programmed therein to configure a multi-core device <NUM> during power-up/reset.

Turning now to <FIG>, a block diagram <NUM> is presented showing a fuse decompression mechanism. The decompression mechanism may be disposed within each of the microprocessor cores <NUM> of <FIG>. For purposes of clearly teaching the present invention, only one core <NUM> is depicted in <FIG> and each of the cores <NUM> disposed on the die comprise substantially equivalent elements as the core <NUM> shown. A physical fuse array <NUM> disposed on the die as described above is coupled to the core <NUM>. The physical fuse array <NUM> comprises compressed microcode patch fuses <NUM>, compressed register fuses <NUM>, compressed cache correction fuses <NUM>, and compressed fuse correction fuses <NUM>. The physical fuse array <NUM> may also comprise uncompressed configuration data (not shown) such as system configuration data as discussed above and/or block error checking and correction (ECC) codes (not shown). The inclusion of ECC features will be discussed in further detail below.

The microprocessor core <NUM> comprises a reset controller <NUM> that receives a reset signal RESET which is asserted upon power-up of the core <NUM> and in response to events that cause the core <NUM> to initiate a reset sequence of steps. The reset controller <NUM> includes a decompressor <NUM>. The decompressor <NUM> has a patch fuses element <NUM>, a register fuses element <NUM>, and a cache fuses element <NUM>. The decompressor also comprises a fuse correction element <NUM> that is coupled to the patch fuses element <NUM>, the register fuses element <NUM>, and the cache fuses element <NUM> via bus <NUM>. The patch fuses decompressor is coupled to microcode patch elements <NUM> in the core <NUM>. The register fuses element <NUM> is coupled to microcode registers <NUM> in the core <NUM>. And the cache fuses element <NUM> is coupled to cache correction elements <NUM> in the core <NUM>. In one embodiment, the cache correction elements <NUM> are disposed within an on-die L2 cache (not shown) that is shared by all the cores <NUM>, such as the cache <NUM> of <FIG>. Another embodiment contemplates cache correction elements <NUM> disposed within an L1 cache (not shown) within the core <NUM>. A further embodiment considers cache correction elements <NUM> disposed to correct both the L2 and L1 caches described above. Other embodiments contemplate a plurality of on-core caches and a shared cache that is not on-core.

In operation, upon assertion of RESET the reset controller <NUM> reads the states of the fuses <NUM>-<NUM> in the physical fuse array <NUM> and distributes the states of the compressed system fuses <NUM> to the decompressor <NUM>. After the fuse data has been read and distributed, the fuse correction element <NUM> of the decompressor <NUM> decompresses the compressed fuse correction fuses states to render data that indicates one or more fuse addresses in the physical fuse array <NUM> whose states are to be changed from that which was previously programmed. The data may also include a value for each of the one or more fuse addresses. The one or more fuse addresses (and optional values) are routed via bus <NUM> to the elements <NUM>-<NUM> so that the states of corresponding fuses processed therein are changed prior to decompression of their corresponding compressed data.

In one embodiment, the patch fuses element <NUM> comprises microcode that operates to decompress the states of the compressed microcode patch fuses <NUM> according to a microcode patch decompression algorithm that corresponds the microcode patch compression algorithm described above with reference to <FIG>. In one embodiment, the register fuses element <NUM> comprises microcode that operates to decompress the states of the compressed register fuses <NUM> according to a register fuses decompression algorithm that corresponds to the register fuses compression algorithm described above with reference to <FIG>. In one embodiment, the cache fuses element <NUM> comprises microcode that operates to decompress the states of the compress cache correction fuses <NUM> according to a cache correction fuses decompression algorithm that corresponds to the cache correction fuses compression algorithm described above with reference to <FIG>. After each of the elements <NUM>-<NUM> change the states of any fuses whose addresses (and optional values) are provided via bus <NUM> from the fuse correction element <NUM>, their respective data is decompressed according to the corresponding algorithm employed. As will be described in further detail below, the arrangement contemplates multiple "reblows" of any fuse address within the physical fuse array prior to the initiation of the decompression process executed by any of the decompressors <NUM>-<NUM>. In one embodiment bus <NUM> may comprise conventional microcode programming mechanisms that are employed to transfer data between respective routines therein. The arrangement further contemplates a comprehensive decompressor <NUM> having capabilities to recognize and decompress configuration data based upon its specific type. Accordingly, the recited elements <NUM>-<NUM> within the decompressor <NUM> are presented in order to teach relevant aspects of the arrangement, however, contemplated implementations of the arrangement may not necessarily include distinct elements <NUM>-<NUM>, but rather a comprehensive decompressor <NUM> that provides functionality corresponding to each of the elements <NUM>-<NUM> discussed above.

In one embodiment, the reset controller <NUM> initiates execution of microcode within the patch fuses element <NUM> to decompress the states of the compressed microcode patch fuses <NUM>. The reset controller <NUM> also initiates execution of microcode within the register fuses element <NUM> to decompress the states of the compressed register fuses <NUM>. And the reset controller <NUM> further initiates execution of microcode within the cache fuses element <NUM> to decompress the states of the compressed cache correction fuses <NUM>. The microcode within the decompressor <NUM> also operates to change the states of any fuses addressed by fuse correction data provided by the compressed fuse correction fuses <NUM> prior to decompression of the compressed data.

The reset controller <NUM>, decompressor <NUM>, and elements <NUM>-<NUM> therein are configured to perform the functions and operations as discussed above. The reset controller <NUM>, decompressor <NUM>, and elements <NUM>-<NUM> therein may comprise logic, circuits, devices, or microcode, or a combination of logic, circuits, devices, or microcode, or equivalent elements that are employed to execute the functions and operations as noted. The elements employed to accomplish these operations and functions within the reset controller <NUM>, decompressor <NUM>, and elements <NUM>-<NUM> therein may be shared with other circuits, microcode, etc., that are employed to perform other functions and/or operations within the reset controller <NUM>, decompressor <NUM>, and elements <NUM>-<NUM> therein or with other elements within the core <NUM>.

After the states of the fuses <NUM>-<NUM> within the physical fuse array <NUM> have been changed and decompressed, the states of the decompressed "virtual" fuses are then routed, as appropriate to the microcode patch elements <NUM>, the microcode registers <NUM>, and the cache correction elements <NUM>. Accordingly, the core <NUM> is configured for operation following completion of a reset sequence.

The present inventors note that the decompression functions discussed above need not necessarily be performed in a particular order during a reset sequence. For example, microcode patches may be decompressed following decompression of microcode registers initialization data. Likewise, the decompression functions may be performed in parallel or in an order suitable to satisfy design constraints.

Furthermore, the present inventors note that the implementations of the elements <NUM>-<NUM> need not necessarily be implemented in microcode versus hardware circuits, since in a typical microprocessor core <NUM> there exist elements of the core <NUM> which can more easily be initialized via hardware (such as a scan chain associated with a cache) as opposed to direct writes by microcode. Such implementation details are left up to designer judgment. However, the present inventors submit that the prior art teaches that cache correction fuses are conventionally read and entered into a cache correction scan chain by hardware circuits during reset prior to initiating the execution of microcode, and it is a feature of the arrangement to implement the cache fuses decompressor <NUM> in microcode as opposed to hardware control circuits since a core's caches are generally not turned on until microcode runs. By utilizing microcode to implement the cache fuses element <NUM>, a more flexible and advantageous mechanisms is provided for entering cache correction data into a scan chain, and significant hardware is saved.

Now referring to <FIG>, a block diagram is presented illustrating an exemplary format <NUM> for compressed configuration data <NUM>. The compressed configuration data <NUM> is compressed by the compressor <NUM> of <FIG> from data residing in the virtual fuse array <NUM> and is programmed (i.e., "blown") into the physical fuse array <NUM> of the multi-core device <NUM>. During a reset sequence, as is described above, the compressed configuration data <NUM> is retrieved from the physical fuse array <NUM> by each of the cores <NUM> and is decompressed and corrected by the elements <NUM>-<NUM> of the decompressor <NUM> within each of the cores <NUM>. The decompressed and corrected configuration data is then provided to the various elements <NUM>-<NUM> within the core <NUM> to initialize the core <NUM> for operation.

The compressed configuration data <NUM> comprises one or more compressed data fields <NUM> for each of the configuration data types discussed above and are demarcated by end-of-type fields <NUM>. Programming events (i.e., "blows") are demarcated by an end-of-blow field <NUM>. The compressed data fields <NUM> associated with each of the data types are encoded according to a compression algorithm that is optimized to minimize the number of bits (i.e., fuses) that are required to store the particular bit patterns associated with each of the data types. The number of fuses in the physical fuse array <NUM> that make up each of compressed data fields <NUM> is a function of the compression algorithm that is employed for a particular data type. For example, consider a core that comprises sixty-four <NUM>-bit microcode registers which must be initialized to, say, all ones or all zeros. An optimum compression algorithm may be employed to yield <NUM> compressed data fields <NUM> for that data type, where each of the compressed data fields <NUM> comprises initialization data for a particular microcode register where the compressed data fields <NUM> are prescribed in register number order (i.e., <NUM>-<NUM>). And each of the compressed data fields <NUM> comprises a single fuse which is blown if a corresponding microcode register is initialized to all ones, and which is not blown if the corresponding microcode register is initialized to all zeros.

The elements <NUM>-<NUM> of the decompressor <NUM> in the core <NUM> are configured to utilize the end-of-type fields <NUM> to determine where their respective compressed data is located within the physical fuse array <NUM> and the fuse correction decompressor <NUM> is configured to utilize the end-of-blow fields <NUM> to locate compressed fuse correction data that has been programmed (i.e., blown) subsequent to an initial programming event. It is a feature of the arrangement to provide a substantial amount of spare fuses in the physical fuse array <NUM> to allow for a significant number of subsequent programming events, as will be discussed in more detail below.

The exemplary compressed type format discussed above is presented to clearly teach aspects that are associated with compression and decompression of configuration data. However, the manner in which specific type data is compressed, demarcated, and the number and types of data to be compressed within the fuse array <NUM> is not intended to be restricted to the example of <FIG>. Other numbers, types, and formats are contemplated that allow for tailoring to various devices and architectures extant in the art.

Turning now to <FIG>, a block diagram is presented illustrating an exemplary format for decompressed microcode patch configuration data <NUM>. During a reset sequence, compressed microcode patch configuration data is read by each core <NUM> from the physical fuse array <NUM>. The compressed microcode patch configuration data is then corrected according to fuse correction data provided via bus <NUM>. Then, the corrected compressed microcode patch configuration data is decompressed by the patch fuses decompressor <NUM>. The result of the decompression process is the decompressed microcode patch configuration data <NUM>. The data <NUM> comprises a plurality of decompressed data blocks <NUM> corresponding to the number of microcode patch elements <NUM> within the core <NUM> that require initialization data. Each decompressed data block <NUM> comprises a core address field <NUM>, a microcode ROM address field <NUM>, and a microcode patch data field <NUM>. The sizes of the fields <NUM>-<NUM> are a function of the core architecture. As part of the decompression process, the patch fuses decompressor <NUM> creates a complete image of the target data required to initialize the microcode patch elements <NUM>. Following decompression of the microcode patch configuration data <NUM>, conventional distribution mechanisms may be employed to distribute the data <NUM> to respectively addressed core and microcode ROM substitution circuits/registers in the microcode patch elements <NUM>.

Now turning to <FIG>, a block diagram is presented depicting an exemplary format for decompressed microcode register configuration data <NUM>. During a reset sequence, compressed microcode register configuration data is read by each core <NUM> from the physical fuse array <NUM>. The compressed microcode register configuration data is then corrected according to fuse correction data provided via bus <NUM>. Then, the corrected compressed microcode register configuration data is decompressed by the register fuses decompressor <NUM>. The result of the decompression process is the decompressed microcode register configuration data <NUM>. The data <NUM> comprises a plurality of decompressed data blocks <NUM> corresponding to the number of microcode registers <NUM> within the core <NUM> that require initialization data. Each decompressed data block <NUM> comprises a core address field <NUM>, a microcode register address field <NUM>, and a microcode register data field <NUM>. The sizes of the fields <NUM>-<NUM> are a function of the core architecture. As part of the decompression process, the register fuses decompressor <NUM> creates a complete image of the target data required to initialize the microcode registers <NUM>. Following decompression of the microcode register configuration data <NUM>, conventional distribution mechanisms may be employed to distribute the data <NUM> to respectively addressed core and microcode registers <NUM>.

Referring now to <FIG>, a block diagram is presented featuring an exemplary format for decompressed cache correction data <NUM>. During a reset sequence, compressed cache correction data is read by each core <NUM> from the physical fuse array <NUM>. The compressed cache correction data is then corrected according to fuse correction data provided via bus <NUM>. Then, the corrected compressed cache correction data is decompressed by the cache fuses decompressor <NUM>. The result of the decompression process is the decompressed cache correction data <NUM>. Various cache mechanisms may be employed in the multi-core processor <NUM> and the decompressed cache correction data <NUM> is presented in the context of a shared L2 cache <NUM>, where all of the cores <NUM> may access a single cache <NUM>, utilizing shared areas. Accordingly, the exemplary format is provided according to the noted architecture. The data <NUM> comprises a plurality of decompressed data blocks <NUM> corresponding to the number of cache correction elements <NUM> within the core <NUM> that require corrective data. Each decompressed data block <NUM> a sub-unit column address field <NUM> and a replacement column address field <NUM>. As one skilled in the art will appreciate, memory caches are fabricated with redundant columns (or rows) in sub-units of the caches to allow for a functional redundant column (or row) in a particular sub-unit to be substituted for a non-functional column (or row). Thus, the decompressed cache correction data <NUM> allows for substitution of functional columns (as shown in <FIG>) for non-functional columns. In addition, as one skilled in the art will concur, conventional fuse array mechanisms associated with cache correction include fuses associated with each sub-unit column that are blown when substitution is required by redundant sub-unit columns. Accordingly, because such a large number of fuses are required (to address all sub-units and columns therein), only a portion of the sub-units are typically covered, and then the resulting conventional cache correction fuses are very sparsely blown. And the present inventors note that it is a feature of the arrangement to address and compress sub-unit column addresses and replacement column addresses only for those sub-unit columns that require replacement, thus minimizing the number of fuses that are required to implement cache correction data. Consequently, the arrangement, as limited by physical fuse array size and the amount of additional configuration data that is programmed therein, provides the potential for expanding the number of sub-unit columns (or rows) in a cache <NUM> that can be corrected over that which has heretofore been provided. In the embodiment shown in <FIG>, it is noted that the associated cores <NUM> are configured such that only one of the cores <NUM> sharing the L2 cache <NUM> would access and provide the corrective data <NUM>-<NUM> to its respective cache correction elements <NUM>. The sizes of the fields <NUM>-<NUM> are a function of the core architecture. As part of the decompression process, the cache correction fuses decompressor <NUM> creates a complete image of the target data required to initialize the cache correction elements <NUM>. Following decompression of the cache correction data <NUM>, conventional distribution mechanisms in the responsible core <NUM> may be employed to distribute the data <NUM>-<NUM> to respectively addressed cache correction elements <NUM>.

Turning to <FIG>, a block diagram is presented featuring an alternative exemplary format for decompressed cache correction data <NUM>. The embodiment of <FIG> may be employed in a multi-core processor configuration such as that of <FIG>, where each of the cores <NUM> comprise one or more on-core caches (not shown) including, but not limited to, a level one (L1) data cache and an L1 instruction cache. During a reset sequence, compressed cache correction data is read by each core <NUM> from the physical fuse array <NUM>. The compressed cache correction data is then corrected according to fuse correction data provided via bus <NUM>. Then, the corrected compressed cache correction data is decompressed by the cache fuses decompressor <NUM>. The result of the decompression process is the decompressed cache correction data <NUM>. The data <NUM> comprises a plurality of decompressed data blocks <NUM> corresponding to the number of cache correction elements <NUM> within the core <NUM> that require corrective data. Each decompressed data block <NUM> has a core address field <NUM>, a cache address (CAD) field <NUM>, a sub-unit column address field <NUM>, and a replacement column address field <NUM>. Thus, the decompressed cache correction data <NUM> allows for substitution of functional columns (or rows) for non-functional columns (or rows) within a cache specified by the CAD field <NUM>, within a core <NUM> specified by the core address field <NUM>. A predefined core address value in the core address field <NUM> may specify a shared cache, such as an L2 cache, that is not on-core. The sizes of the fields <NUM>-<NUM>, <NUM> are a function of the core architecture. As part of the decompression process, the cache correction fuses decompressor <NUM> creates a complete image of the target data required to initialize the cache correction elements <NUM>. Following decompression of the cache correction data <NUM>, conventional distribution mechanisms in the responsible core <NUM> may be employed to distribute the data <NUM>-<NUM>, <NUM> to respectively addressed cache correction elements <NUM>.

Turning now to <FIG>, a block diagram is presented showing an exemplary format for decompressed fuse correction data <NUM>. As has been discussed above, during reset the fuse correction decompressor <NUM> accesses compressed fuse correction data <NUM> within the physical fuse array <NUM>, decompresses the compressed fuse correction data, and supplies the resulting decompressed fuse correction data <NUM> to the other decompressors <NUM>-<NUM> within the core <NUM>. The decompressed fuse correction data comprises one or more end-of-blow fields <NUM> that indicate the end of successively programming events in the physical fuse array <NUM>. If a subsequent programming event has occurred, a reblow field <NUM> is programmed to indicate that a following one or more fuse correction fields <NUM> indicate fuses within the physical fuse array <NUM> that are to be reblown. Each of the fuse correction fields comprises an address of a specific fuse within the physical fuse array <NUM> that is to be reblown along with a state (i.e., blown or unblown) for the specific fuse. Only those fuses that are to be reblown are provided in the fuse correction blocks fields <NUM>, and each group of fields <NUM> within a given reblow event is demarcated by an end-of-blow field <NUM>. If reblow field <NUM>, properly encoded, is present after a given end-of-blow field <NUM>, then subsequent one or more fuse fuses may be configured reblown as indicated by corresponding fuse correction fields. Thus, the arrangement provides the capability for a substantial number of reblows for the same fuse, as limited by array size and other data provided therein.

The present inventors have also observed that the real estate and power gains associated with utilization of a shared physical fuse array within which compressed configuration data is stored presents opportunities for additional features disposed on a multi-core die. In addition, the present inventors have noted that, as one skilled in the art will appreciate, present day semiconductor fuse structures often suffer from several shortcomings, one of which is referred to as "growback. " Growback is the reversal of the programming process such that a fuse will, after some time, reconnect after it has been blown, that is, it goes from a programmed (i.e., blown) state back to an unprogrammed (i.e., unblown) state.

In another aspect, as alluded to above, the present inventors have noted that there may exist challenges when power gating techniques are employed to minimize power consumption across a multi-core die, such as the die <NUM> of <FIG>. Such techniques, which are beyond the scope of the present application, are employed to detect when one or more cores <NUM> are not being utilized, and in a varying number of ways, the one or more cores <NUM> are powered-down (also known as a power gating event). When a power-gated core <NUM> is required for execution, power is restored to the core <NUM> and it begins execution. Of specific interest to the present inventors is the case where a core <NUM> comprises one or more on-core caches, as is discussed with reference to <FIG>, where power is removed from these caches under a power gating event. As one skilled in the art will appreciate, in order to power up the one or more caches following the power gating event, the one or more caches must first be configured using fuse correction data as is described above. However, one skilled will also appreciate that excessive reading of fuse arrays decreases the lifetime of the fuses therein. Another issue associated with power gating is the excessive time that may be required for each core to read cache correction fuses, to decompress compressed fuse repair data, and to configure corrections for each of its respective on-core caches. Accordingly, an embodiment of the present invention is provided to <NUM>) decrease the amount of time required for all cores to decompress and configure their respective on-core caches following a power gating event, and <NUM>) increase the overall lifetime of the fuse array by decreasing the number of accesses by the cores under power gating conditions.

Attention is now directed to <FIG>, where a block diagram is presented detailing a mechanism according to the present invention for rapidly loading cache correction data into a multi-core device <NUM>, initially and following a power gating event. The device <NUM> includes a plurality of cores <NUM> that are configured substantially as described above with reference to <FIG>. In addition, each of the cores <NUM> includes one or more on-core caches CACHE1-CACHEN <NUM>, a cache repair stores <NUM>, a configuration data stores <NUM>, reset logic <NUM>, and sleep logic <NUM>. Each of the cores <NUM> is coupled to a physical fuse array <NUM> that is configured as described above with reference to <FIG>, and to a stores (e.g., random access memory (RAM)) <NUM> that is disposed on the same die as the cores <NUM>, but which is not disposed within any of the cores <NUM>. Hence, the stores <NUM> is henceforth referred to as "uncore" stores <NUM>. The uncore stores <NUM> includes designated sub-stores <NUM>-<NUM> that each correspond to each of the cores <NUM>. The multi-core device <NUM> further includes power control <NUM> that is coupled to each of the cores <NUM>. A sync bus SYNC is coupled to each of the cores <NUM> to provide for synchronization communications there between during power-up, reset, and power gating events.

For purposes of illustration, only four cores <NUM>, a single physical fuse array <NUM>, and a single uncore stores <NUM> are shown, however the present inventors note that the novel and inventive concepts according to the present invention can be extended to a plurality of cores <NUM>, fuse arrays <NUM>,and uncore stores <NUM> of any number. In one embodiment, the uncore stores <NUM> comprises a random access memory (RAM) that retains power during a power gating event. In one embodiment, the uncore stores <NUM> comprises a <NUM> KB RAM, though other sizes are contemplated.

In operation, the power control <NUM> is configured to perform power gating in order to remove and restore power to one or more of the cores <NUM>. During power-up/reset, the reset logic <NUM> on each of the cores <NUM> is configured to perform, among other operations, configuration of the cores <NUM> as is described above. In addition, the reset logic <NUM> is configured to read the configuration data register <NUM> to determine if a core <NUM> is a master core or a slave core. If the configuration data indicates that a core <NUM> is a slave core, as part of the reset process, the slave core waits until the master core signals over the synchronization bus SYNC that decompressed cache repair data for each of the cores <NUM> has been read from the fuse array <NUM> and has been written into corresponding sub-stores <NUM>-<NUM> within the uncore stores <NUM>. Upon indication over SYNC that the corresponding sub-stores <NUM>-<NUM> have been written, each of the slave cores reads their respective decompressed repair data from the corresponding sub-stores <NUM>-<NUM> and proceeds to configure their respective on-core caches as is described above. If the configuration data indicates that a core <NUM> is a master core, then as part of power-up/reset, the master core reads cache correction data for all of the cores <NUM> from the fuse array <NUM>, decompresses the compressed correction data for all of the cores <NUM>, and writes the decompressed cache repair data to the sub-stores <NUM>-<NUM> corresponding to each of the cores <NUM>. The master core then signals to the other cores <NUM> over SYNC that writing of the decompressed cache repair data is completed.

During a power gating event, the power control <NUM> removes power from one or more of the cores <NUM> to the extent that power is also removed from the core's on-core caches <NUM>. However, power is not removed from the uncore stores <NUM>, thus preserving the decompressed repair data for each of the cores <NUM>. The sleep logic <NUM> is configured to determine when power is restored to a respective core <NUM> following a power gating event, to directly read cache repair data for its on-core caches from its respective sub-stores <NUM>-<NUM>, and to configure its respective repair data stores <NUM> for correction of its on-core caches <NUM>, thus drastically reducing the time required to return to operations following the power gating event, while concurrently substantially increasing the lifetime of the fuse array <NUM>.

Portions of the present invention and corresponding detailed description are presented in terms of software, or algorithms and symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the ones by which those of ordinary skill in the art effectively convey the substance of their work to others of ordinary skill in the art. An algorithm, as the term is used here, and as it is used generally, is conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of optical, electrical, or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated.

Unless specifically stated otherwise, or as is apparent from the discussion, terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, a microprocessor, a central processing unit, or similar electronic computing device, that manipulates and transforms data represented as physical, electronic quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Note also that the software implemented aspects of the invention are typically encoded on some form of program storage medium or implemented over some type of transmission medium. The program storage medium may be electronic (e.g., read only memory, flash read only memory, electrically programmable read only memory), random access memory magnetic (e.g., a floppy disk or a hard drive) or optical (e.g., a compact disk read only memory, or "CD ROM"), and may be read only or random access. Similarly, the transmission medium may be metal traces, twisted wire pairs, coaxial cable, optical fiber, or some other suitable transmission medium known to the art. The invention is not limited by these aspects of any given implementation.

Claim 1:
An apparatus for providing configuration data to an integrated circuit, the apparatus comprising:
a device programmer, coupled to a semiconductor fuse array (<NUM>) disposed on a die, configured to program said semiconductor fuse array (<NUM>) with compressed configuration data; and
a plurality of cores (<NUM>), disposed on said die, wherein each of said plurality of cores (<NUM>) is coupled to said semiconductor fuse array (<NUM>), and wherein one of said plurality of cores (<NUM>) is configured to access said semiconductor fuse array (<NUM>) upon power-up/reset to read and decompress said compressed configuration data, and to store decompressed configuration data sets for one or more cache memories (<NUM>) within said each of said plurality of cores (<NUM>) in a stores (<NUM>) that is disposed on the same die as the plurality of cores but not within any of said plurality of cores and coupled to said plurality of cores (<NUM>), said each of said plurality of cores (<NUM>) comprising:
reset logic (<NUM>), configured to employ said decompressed configuration data sets to initialize said one or more cache memories (<NUM>) upon power-up/reset, wherein the reset logic (<NUM>) is also configured to read a configuration data register (<NUM>) to determine if one of the plurality of cores (<NUM>) is a master core or a slave core; and
sleep logic (<NUM>), configured to determine that power is restored following a power gating event, and configured to subsequently access said stores (<NUM>) to retrieve and employ said decompressed configuration data sets to initialize said one or more caches (<NUM>) following said power gating event.