Patent Description:
After the development of gallium nitride (GaN) based light emitting diodes, GaN-based LEDs have been applied to various fields such as natural color LED display devices, LED signboards, white LEDs, and the like.

In general, a gallium nitride based light emitting diode is formed by growing epitaxial layers on a substrate such as a sapphire substrate, and include an N-type semiconductor layer, a P-type semiconductor layer, and an active layer interposed therebetween. Then, an N-electrode pad is formed on the N-type semiconductor layer and a P-electrode pad is formed on the P-type semiconductor layer. For operation, the light emitting diode is electrically connected to an external power source through the electrode pads. At this time, current flows from the P-electrode pad to the N-electrode pad through the semiconductor layers.

On the other hand, in order to improve heat dissipation while preventing light loss by the P-electrode pad, a light emitting diode having a flip chip structure is used in the art, and various electrode structures have been suggested to help current spreading in a large area flip chip type light emitting diode (see <CIT>). For example, a reflective electrode is formed on the P-type semiconductor layer, and extensions for current spreading are formed on a region of the N-type semiconductor layer exposed by etching the P-type semiconductor layer and the active layer.

The reflective electrode formed on the P-type semiconductor layer reflects light generated in the active layer to enhance light extraction efficiency and assists in current spreading in the P-type semiconductor layer. On the other hand, the extensions connected to the N-type semiconductor layer assist in current spreading in the N-type semiconductor layer such that light can be uniformly generated in a wide active area. Particularly, a light emitting diode having a large area of about <NUM><NUM> or more requires current spreading not only in the P-type semiconductor layer but also in the N-type semiconductor layer.

However, conventional techniques employ linear extensions causing limitation in current spreading due to high resistance thereof. Moreover, since a reflective electrode is disposed only on the P-type semiconductor layer, significant light loss occurs due to the pads and the extensions instead of being reflected by the reflective electrode.

Further, in the flip chip structure, light is emitted through a substrate.

Accordingly, after semiconductor layers are formed on the substrate, a metallic reflective layer is formed above the semiconductor layers or a current spreading layer such that light can be reflected by the reflective layer.

<FIG> is a partial sectional view of a light emitting diode including a reflective layer in the related art.

Referring to <FIG>, an ohmic layer <NUM> and a reflective layer <NUM> are disposed on a mesa layer <NUM>. In addition, a barrier layer <NUM> surrounds a side surface of the ohmic layer <NUM> while surrounding an upper portion and side surface of the reflective layer <NUM>.

The mesa layer <NUM> is a semiconductor area grown by epitaxial growth, and the ohmic layer <NUM> is composed of a conductive metal or a conductive oxide. In addition, the reflective layer <NUM> reflects light generated in the mesa layer <NUM> or a stack below the mesa layer. The reflective layer <NUM> is formed of sliver (Ag) or aluminum (Al).

The barrier layer <NUM> surrounding the upper portion and side surface of the reflective layer <NUM> has a structure wherein first barrier layers 14A and second barrier layers 14B are alternately stacked one above another. The first barrier layers 14A include nickel and the second barrier layers 14B include tungsten (W) or tungsten titanium (TiW). The barrier layer <NUM> prevents diffusion of metal elements constituting the reflective layer <NUM>. On the other hand, the reflective layer <NUM> has a higher coefficient of thermal expansion than the barrier layer <NUM>. For example, Ag has a coefficient of thermal expansion at room temperature of <NUM>·m-<NUM>·K-<NUM>, and W has a coefficient of thermal expansion at room temperature of <NUM>·m-<NUM>·K-<NUM>. Namely, there is a significant difference in coefficient of thermal expansion between the reflective layer <NUM> and the barrier layer <NUM>.

Such a significant difference in coefficient of thermal between the reflective layer <NUM> and the barrier layer <NUM> induces stress in the reflective layer <NUM>. Accordingly, the reflective layer <NUM> is separated from the ohmic layer <NUM> or the mesa layer <NUM> under the ohmic layer <NUM> due to stress generated in the reflective layer <NUM> at the same temperature.

On the other hand, various techniques have been developed to improve performance of the light emitting diode, that is, internal quantum efficiency and external quantum efficiency. Among various attempts to improve external quantum efficiency, a technique for improving light extraction efficiency has been developed in the art. Document <CIT> discloses a light emitting diode comprising: diode region having first and second opposing faces and including therein an n-type and a p-type layer; an anode contact that ohmically contacts the p-type layer; a transparent insulating layer formed over the mesa structure; and a reflective cathode contact that electrically contacts the n-type layer via a current spreading layer through the transparent insulating layer.

The present invention is aimed at providing a light emitting diode having improved current spreading performance.

In addition, the present invention is aimed at providing a light emitting diode having improved light extraction efficiency by improving reflectivity.

Further, the present invention is aimed at providing a method of manufacturing a light emitting diode, which can improve current spreading performance while preventing a complicated manufacturing process.

Further, the present invention is aimed at providing a light emitting diode capable of relieving stress caused by a reflective layer, and a method of manufacturing the same.

Further, the present invention is aimed at providing a technique for improving light extraction efficiency through surface texturing by an inexpensive and simple process.

According to one aspect of the present invention, a light emitting structure comprising a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer is disclosed. Mesa-etched areas are formed from the surface of the second conductivity type semiconductor layer to the first conductivity type semiconductor layer. A reflective electrode is formed on the second conductivity type semiconductor layer. The reflective electrode may include a reflective metal layer, a barrier metal layer and a stress relieving layer formed between the reflective metal layer and the barrier metal layer, wherein the stress relieving layer has a coefficient of thermal expansion between the coefficient of thermal expansion of the reflective metal layer and the coefficient of thermal expansion of the barrier metal layer. A lower insulation layer covers an overall surface of the structure formed by the first conductivity type semiconductor layer, the active layer, the second conductivity type semiconductor layer, the mesa-etched areas and the reflective electrode, with the lower insulation layer allowing an upper surface of the reflective electrode to be partially exposed therethrough and further allowing the surface of the first conductivity type semiconductor layer to be exposed therethrough in the mesa-etched areas. A current spreading layer is formed on the lower insulation layer covering the first conductivity type semiconductor layer and is electrically connected to the first conductivity type semiconductor layer. An upper insulation layer is formed on the current spreading layer, with both the current spreading layer and the reflective electrode being partially exposed through the upper insulation layer. A first pad is electrically connected to the current spreading layer exposed through the upper insulation layer exposed within an upper region of the mesas M, and a second pad is electrically connected to the reflective electrode exposed through the upper insulation layer.

In accordance with another aspect of the present invention, a light emitting diode includes a first conductive type semiconductor layer; a plurality of mesas separated from each other on the first conductive type semiconductor layer and each including an active layer and a second conductive type semiconductor layer; reflective electrodes each disposed on the corresponding mesa area and in ohmic contact with the second conductive type semiconductor layer; and a current spreading layer covering the plurality of mesas and the first conductive type semiconductor layer to be electrically isolated from the mesas, and including first openings formed in upper regions of the mesas to expose the reflective electrodes therethrough, respectively, the current spreading layer being in ohmic contact with the first conductive type semiconductor layer.

Since the current spreading layer covers the plurality of mesas and the first conductive type semiconductor layer, the light emitting diode has improved current spreading performance through the current spreading layer.

The first conductive (conductivity) type semiconductor layer is continuously formed. In addition, the plurality of mesas may have a longitudinally elongated shape and extend parallel to each other towards one side of the substrate, and the first openings may be biased towards the same ends of the plurality of mesas. Accordingly, it is possible to achieve easy formation of pads connecting the reflective electrodes exposed through the openings of the current spreading layer.

The current spreading layer may include a reflective metal such as Al.

Accordingly, the light emitting diode allows light reflection not only by the reflective electrodes, but also by the current spreading layer, whereby light travelling through side surfaces of the plurality of mesas and the first conductive type semiconductor layer can be reflected.

Each of the reflective electrodes may include a reflective metal layer and a barrier metal layer. Further, the barrier metal layer may cover an upper surface and a side surface of the reflective metal layer. As such, the light emitting diode prevents the reflective metal layer from being exposed outside, thereby preventing deterioration of the reflective metal layer.

Each of the reflective electrodes may further include a stress relieving layer formed between the reflective metal layer and the barrier metal layer and having a coefficient of thermal expansion between the coefficient of thermal expansion of the reflective metal layer and the coefficient of thermal expansion of the barrier metal layer. The stress relieving layer relieves stress applied to the reflective metal layer, thereby preventing the reflective metal layer from being delaminated from the second conductive type semiconductor layer.

The light emitting diode may further include an upper insulation layer covering at least part of the current spreading layer and including second openings formed in upper regions of the mesas to expose the reflective electrodes therethrough, respectively; and a second pad disposed on the upper insulation layer and electrically connected to the reflective electrodes exposed through the first and second openings. The light emitting diode may further include a first pad connected to the current spreading layer. The first pad and the second pad may have the same shape and the same size, thereby facilitating flip-chip bonding.

The light emitting diode may further include a lower insulation layer disposed between the plurality of mesas and the current spreading layer and electrically isolating the current spreading layer from the plurality of mesas. The lower insulation layer may include third openings formed in upper regions of the mesas to expose the reflective electrodes therethrough, respectively.

In addition, the first openings may have a greater width than the third openings to allow all of the third openings to be exposed. In other words, the first openings have sidewalls disposed on the lower insulation layer. In addition, the light emitting diode may further include an upper insulation layer covering at least part of the current spreading layer and including second openings through which the reflective electrodes are exposed. The upper insulation layer covers the sidewalls of the first openings.

The lower insulation layer may be a reflective dielectric layer, for example, a distributed Bragg reflector (DBR).

The light emitting diode may further include a substrate including the first conductive semiconductor formed on one surface thereof and a ground texture formed on the other surface thereof.

The ground texture may be formed by grinding the other surface of the substrate, followed by treatment with phosphoric acid or a mixture of sulfuric acid and phosphoric acid.

The substrate may include a chamfered structure at corners of the other surface thereof. In addition, the substrate may further include an anti-reflective layer on the other surface thereof.

The reflective metal layer may include one of Al, Al alloys, Ag, and Ag alloys, and the barrier metal layer may include one of W, TiW, Mo, Ti, Cr, Pt, Rh, Pd, and Ni. Further, the stress relieving layer may be formed as a single layer of Ag, Cu, Ni, Pt, Ti, Rh, Pd or Cr, or as a composite layer of a plurality of metals selected from Cu, Ni, Pt, Ti, Rh, Pd or Au.

In one embodiment, the reflective metal layer is formed of Al or Al alloys; the barrier metal layer includes one of Ti, Cr, Pt, Rh, Pd and Ni; the stress relieving layer may be formed as a single layer of Ag or Cu, or as a composite layer of a plurality of metals selected from Ni, Au, Cu or Ag.

In another embodiment, the reflective metal layer may include one of Ag and Ag alloys; the barrier metal layer may include W, TiW or Mo; the stress relieving layer may be formed as a single layer of Cu, Ni, Pt, Ti, Rh, Pd or Cr, or as a composite layer of a plurality of metals selected from Cu, Ni, Pt, Ti, Rh, Pd, Cr or Au.

In a further embodiment, the reflective metal layer may be formed of anyone of Ag or Ag alloys; the barrier metal layer may include Pt or Ni; the stress relieving layer may be formed as a single layer of Cu, Cr, Rh, Pd, TiW or Ti, or as a composite layer of a plurality of metals selected from Ni, Au or Cu.

In accordance with another aspect of the present invention, a method of manufacturing a light emitting diode includes: forming a semiconductor stack including a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer on a substrate; patterning the second conductive type semiconductor layer and the active layer to form a plurality of mesas on the first conductive type semiconductor layer, followed by forming reflective electrodes on the plurality of mesas; and forming a current spreading layer covering the plurality of mesas and the first conductive type semiconductor layer, the current spreading layer being electrically isolated from the plurality of mesas while exposing at least part of the reflective electrodes.

Forming reflective electrodes may include: forming a reflective metal layer on the second conductive type semiconductor layer, and forming a barrier metal layer to cover an upper surface and a side surface of the reflective metal layer.

The reflective electrodes may be formed after the plurality of mesas is formed. However, the present invention is not limited thereto, and the mesas may be formed after the reflective electrodes are formed.

Forming reflective electrodes may further include forming a stress relieving layer having a coefficient of thermal expansion between the coefficient of thermal expansion of the reflective metal layer and the coefficient of thermal expansion of barrier metal layer, before forming the barrier metal layer.

The method of manufacturing a light emitting diode may further include, before forming the current spreading layer, forming a lower insulation layer between the plurality of mesas and the current spreading layer to expose at least part of the reflective electrodes therethrough while electrically isolating the current spreading layer from the plurality of mesas and the reflective electrodes.

The method of manufacturing a light emitting diode may further include forming a ground texture on a surface of the substrate, wherein the semiconductor stack is formed on one surface of the substrate and the ground texture is formed on the other surface thereof.

Forming a ground texture may include grinding the other surface of the substrate, followed by treating the ground other surface with phosphoric acid or a mixture of sulfuric acid and phosphoric acid.

Embodiments of the present invention may provide a light emitting diode, particularly, a flip-chip type light emitting diode, which has improved current spreading performance. In addition, the light emitting diode has improved reflectivity, thereby providing improved light extraction efficiency. Further, the light emitting diodes has a simple structure of plural mesas, thereby simplifying a process of manufacturing the light emitting diode.

Further, according to the embodiments of the invention, the light emitting diode can relieve stress due to difference in coefficient of thermal expansion between a reflective metal layer and a barrier metal layer using a stress relieving layer which has a coefficient of thermal expansion, which is lower than that of the reflective metal layer and higher than that of the barrier metal layer, thereby preventing separation of the reflective metal layer from the semiconductor layer or the ohmic layer.

Furthermore, the light emitting diode according to the embodiments of the invention allows continuous formation of the reflective metal layer, the stress relieving layer and the barrier metal layer using a photoresist pattern, thereby enabling reduction of process costs.

Furthermore, the light emitting diode according to the embodiments of the invention allows surface texturing through a simple process at low cost, thereby providing improved light extraction efficiency.

It should be understood that the present invention is not limited to the above advantageous effects and other aspects, features and advantageous effects of the present invention will become apparent to those skilled in the art from the following descriptions.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. It should be understood that the following embodiments are given by way of illustration only to provide a thorough understanding of the invention to those skilled in the art. Therefore, the present invention is not limited to the following embodiments and may be embodied in different ways. Further, the widths, lengths, and thicknesses of certain elements, layers or features may be exaggerated for clarity, and like components will be denoted by like reference numerals throughout the specification.

Herein, it will be understood that, when a layer is referred to as being "on" another layer or substrate, it can be directly formed on the other layer or substrate, or an intervening layer(s) may also be present therebetween. In addition, spatially relative terms, such as "above," "upper (portion)," "upper surface," and the like may be understood as meaning "below," "lower (portion)," "lower surface," and the like according to a reference orientation. In other words, the expressions of spatial orientations are to be construed as indicating relative orientations instead of absolute orientations.

In addition, it will be understood that, although the terms "first", "second", etc. may be used herein to distinguish various elements, components, regions, layers and/or sections from one another, these elements, components, regions, layers and/or sections should not be limited by these terms.

<FIG> is a sectional view of a substrate which may be used in manufacture of a light emitting diode in accordance with one embodiment of the present invention.

Referring to <FIG> , a substrate according to one embodiment of the invention is a patterned substrate <NUM>. The patterned substrate <NUM> includes a substrate <NUM> and an anti-reflective layer <NUM>.

The substrate <NUM> has recessed depressions <NUM>. The depressions <NUM> may have a circular or elliptical shape. Particularly, the depressions <NUM> may be formed in a regular pattern. For example, the depressions <NUM> may be island type or line type depressions arranged at constant intervals.

The substrate <NUM> may be a sapphire (Al 2O <NUM>) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, an indium gallium nitride (InGaN) substrate, an aluminum gallium nitride (AlGaN) substrate, an aluminum nitride (AIN) substrate, a gallium oxide (Ga <NUM><NUM>) substrate, or a silicon substrate. Specifically, the substrate <NUM> may be a sapphire substrate.

The anti-reflective layer <NUM> may be disposed between the depressions <NUM>. The anti-reflective layer <NUM> is formed to minimize reflection of light traveling towards the substrate <NUM>. When the substrate <NUM> is a sapphire substrate, the anti-reflective layer <NUM> may be formed of materials having an index of refraction ranging from <NUM> to <NUM>. Particularly, the anti-reflective layer <NUM> may be a silicon nitride layer having an index of refraction ranging from <NUM> to <NUM>.

In addition, when incident light has a wavelength of λ, the thickness of the anti-reflective layer <NUM> may set to an integer multiple of λ/<NUM>. Here, the thickness of the anti-reflective layer <NUM> may have a variation of ±<NUM>% from the integer multiple of λ/<NUM>.

<FIG> are sectional views illustrating a method of manufacturing a patterned substrate shown in <FIG>.

Referring to <FIG> , an anti-reflective layer <NUM> is formed on a substrate <NUM>. The anti-reflective layer <NUM> may be a silicon nitride layer and has a thickness of an integer multiple of λ/<NUM> when incident light has a wavelength of λ. Here, the thickness of the anti-reflective layer <NUM> may have a variation of ±<NUM>% of the integer multiple of λ/<NUM>.

Referring to <FIG> , a photoresist is deposited onto the anti-reflective layer <NUM> to form a photoresist pattern <NUM>. The photoresist pattern <NUM> may have substantially a semi-spherical shape. The shape of the depressions <NUM> shown in <FIG> may be adjusted according to the shape of the photoresist pattern <NUM>. To form the semi-spherical photoresist pattern <NUM>, the photoresist deposited on the anti-reflective layer is subjected to exposure and development processes. As a result, a photoresist pattern having a substantially rectangular cross-section is formed. Next, the photoresist pattern is subjected to a reflow process. By the reflow process, the photoresist having viscosity is formed into a substantially semi-spherical photoresist pattern <NUM> by cohesion between molecules.

Next, etching is performed using the semi-spherical photoresist pattern <NUM> as an etching mask. Herein, etching may be anisotropic dry etching. As a result, etching is intensively carried out in open areas through the photoresist pattern <NUM>. Here, since the photoresist pattern <NUM> has a semi-spherical shape, the degree of etching is gradually weakened from an edge of the semi-spherical shape to the central region of the semi-spherical shape. Further, as etching proceeds, the semi-spherical photoresist pattern <NUM> is gradually removed. Accordingly, a semi-spherical pattern may be formed on an upper surface of the substrate.

Alternatively, after semi-spherical depressions are formed on the anti-reflective layer <NUM> on the substrate <NUM> or on another sacrificial layer by isotropic etching, anisotropic etching may be performed on the substrate <NUM> using the anti-reflective layer <NUM> or the sacrificial layer as an etching mask, so that the semi-spherical depressions <NUM> can be formed on an upper surface of the substrate <NUM>.

Referring to <FIG> , as described above, patterned substrate <NUM> having the semi-spherical depressions <NUM> are formed through etching. The surface of the substrate is exposed inside the depressions <NUM>, and the anti-reflective layer <NUM> is disposed between the depressions <NUM>. The photoresist pattern remaining upon etching of <FIG> can be removed, whereby the anti-reflective layer <NUM> can be exposed.

In addition, the remaining anti-reflective layer <NUM> may also be removed, as needed.

Through the aforementioned process, the substrate having the depressions <NUM> formed on the surface thereof in a regular pattern may be formed.

Further, according to this embodiment, the depressions may be formed in various shapes according to the shape of the photoresist pattern. For example, the photoresist pattern may be formed in a triangular shape or a trapezoidal shape instead of the semi-spherical shape by adjusting an exposure angle, with the photoresist deposited on the substrate. When etching is performed using the photoresist pattern having a triangular shape or a trapezoidal shape as an etching mask, the depressions formed on the substrate have an inversed triangular shape or an inversed trapezoidal shape recessed from the surface of the substrate.

In this embodiment, the depressions may be formed to various shapes recessed from the surface of the substrate. Here, the depressions are arranged in a pattern of regular arrangement.

<FIG> are sectional views illustrating a method of manufacturing a light emitting diode in accordance with one embodiment of the present invention, and in each of the figures, (a) is a plan view and (b) is a sectional view taken along line A-A.

First, referring to <FIG> , a first conductive type semiconductor layer <NUM> is formed on a substrate <NUM>, and a plurality of mesas M separated from each other is formed on the first conductive type semiconductor layer <NUM>. Each of the mesas M includes an active layer <NUM> and a second conductive type semiconductor layer <NUM>. The active layer <NUM> is disposed between the first conductive type semiconductor layer <NUM> and the second conductive type semiconductor layer <NUM>. In addition, reflective electrodes <NUM> are disposed on the plurality of mesas M, respectively.

The plural mesas M may be formed by growing epitaxial layers including the first conductive type semiconductor layer <NUM>, the active layer <NUM> and the second conductive type semiconductor layer <NUM> on the substrate <NUM> by metal organic chemical vapor deposition, followed by patterning the second conductive type semiconductor layer <NUM> and the active layer <NUM> such that the first conductive type semiconductor layer <NUM> is exposed. Side surfaces of the plural mesas M may be obliquely formed by photoresist reflow and the like. An oblique profile of the side surfaces of the mesas M enhances efficiency of extracting light generated in the active layer <NUM>.

The plural mesas M may extend parallel to each other towards one side of the substrate and have a longitudinally elongated shape. Such configuration allows easy formation of the plurality of mesas M having the same shape on a plurality of chip areas on the substrate <NUM>.

After the plurality of mesas is formed, the reflective electrodes <NUM> may be formed on the mesas M, respectively. However, the present invention is not limited thereto. Alternatively, the reflective electrodes <NUM> may be formed on the second conductive type semiconductor layer <NUM> after forming the second conductive type semiconductor layer <NUM> and before forming the mesas M. The reflective electrode <NUM> covers most of an upper surface of the corresponding mesa M and has substantially the same shape as that of the mesa M in plan view.

Each of the reflective electrodes <NUM> may include a reflective layer <NUM>, and may also include a barrier layer <NUM>. The barrier layer <NUM> may cover an upper surface and a side surface of the reflective layer <NUM>. For example, by forming a pattern of the reflective layer <NUM> and forming the barrier layer <NUM> thereon, the barrier layer <NUM> may be formed to cover the upper surface and the side surface of the reflective layer <NUM>. For example, the reflective layer <NUM> may be formed through deposition and patterning of Ag, Ag alloys, Ni/Ag, NiZn/Ag or TiO/Ag. On the other hand, the barrier layer <NUM> may be formed of Ni, Cr, Ti, Pt or combinations thereof, and prevent diffusion or contamination of metallic materials of the reflective layer.

After the plurality of mesas M is formed, an edge of the first conductive type semiconductor layer <NUM> may also be etched. As a result, the upper surface of the substrate <NUM> may be exposed. The side surface of the first conductive type semiconductor layer <NUM> may also be obliquely formed.

As shown in <FIG> , the plurality of mesas M may be formed to be disposed only within an upper region of the first conductive type semiconductor layer <NUM>. That is, the plurality of mesas M may be disposed in an island shape on the upper region of the first conductive type semiconductor layer <NUM>. Alternatively, as shown in <FIG> , the mesas M may extend in one direction to reach an upper edge of the first conductive type semiconductor layer <NUM>. Namely, one edge of a lower surface of each of the mesas M coincides with one edge of the first conductive type semiconductor layer <NUM> in one direction. Accordingly, the upper surface of the first conductive type semiconductor layer <NUM> is divided by the plurality of mesas M.

Referring to <FIG> , a lower insulation layer <NUM> is formed to cover the plurality of mesas M and the first conductive type semiconductor layer <NUM>. The lower insulation layer <NUM> has openings 31a, 31b which allow electrical connection to the first conductive type semiconductor layer <NUM> and the second conductive type semiconductor layer <NUM> in specific areas. For example, the lower insulation layer <NUM> may have openings 31a through which the first conductive type semiconductor layer <NUM> is exposed, and openings 31b through which the reflective electrodes <NUM> are exposed.

The openings 31a may be disposed in a region between the mesas M and near an edge of the substrate <NUM>, and may have an elongated shape that extends along the mesa M. On the other hand, the openings 31b are disposed only on the mesas M to be biased towards the same ends of the mesas.

The lower insulation layer <NUM> may be formed as an oxide layer such as SiO<NUM> and the like, a nitride layer such as SiNx and the like, or an insulation layer such as MgF<NUM>, by chemical vapor deposition (CVD) and the like. The lower insulation layer <NUM> may be formed as a single layer or as multiple layers. Furthermore, the lower insulation layer <NUM> may be formed as a distributed Bragg reflector (DBR), which is formed by alternately stacking a low refractivity material layer and a high refractivity material layer. For example, the lower insulation layer <NUM> may be formed as a reflective insulation layer having high reflectivity by stacking SiO<NUM> / TiO<NUM> , SiO<NUM> / Nb<NUM>O<NUM>, or the like.

Referring to <FIG> , a current spreading layer <NUM> is formed on the lower insulation layer <NUM>. The current spreading layer <NUM> covers the plurality of mesas M and the first conductive type semiconductor layer <NUM>. Further, the current spreading layer <NUM> is disposed on an upper region of each of the mesas M, and has the openings 33a through which the reflective electrodes are exposed. The current spreading layer <NUM> may be in ohmic contact with the first conductive type semiconductor layer <NUM> through the openings 31a of the lower insulation layer <NUM>. The current spreading layer <NUM> is isolated from the plurality of mesas M and the reflective electrodes <NUM> by the lower insulation layer <NUM>.

Each of the openings 33a of the current spreading layer <NUM> has a larger area than the openings 31b of the lower insulation layer <NUM> to prevent connection of the current spreading layer <NUM> to the reflective electrodes <NUM>. Accordingly, the openings 33a have sidewalls disposed on the lower insulation layer <NUM>.

The current spreading layer <NUM> is formed substantially over the entirety of the upper surface of the substrate <NUM> excluding the openings 33a. With this structure, current can be easily spread through the current spreading layer <NUM>. The current spreading layer <NUM> may include a high reflectivity metal layer, such as an Al layer. The high reflectivity metal layer may be formed on a bonding layer of Ti, Cr or Ni. In addition, a protective layer may be formed of Ni, Cr, Au, or combinations thereof as a single layer or a composite layer on the high reflectivity metal layer. The current spreading layer <NUM> may have, for example, a multilayer structure of Ti/Al/Ti/Ni/Au.

Referring to <FIG> , an upper insulation layer <NUM> is formed on the current spreading layer <NUM>. The upper insulation layer <NUM> has openings 35a through which the current spreading layer <NUM> is exposed, and openings 35b through which the reflective electrodes <NUM> are exposed. The openings 35a may have an elongated shape in a perpendicular direction with respect to the longitudinal direction of the mesas M, and a larger area than the openings 35b. The openings 35b expose the reflective electrodes <NUM>, which are exposed through the openings 33a of the current spreading layer <NUM> and the openings 31b of the lower insulation layer <NUM>. The openings 35b have a narrower area than the openings 33a of the current spreading layer <NUM> and have a larger area than the openings 31b of the lower insulation layer <NUM>. Accordingly, sidewalls of the openings 33a of the current spreading layer <NUM> may be covered by the upper insulation layer <NUM>.

The upper insulation layer <NUM> may be formed of an oxide insulation layer, a nitride insulation layer, or a polymer layer of polyimides, Teflon, Parylene, and the like.

Referring to <FIG> , a first pad 37a and a second pad 37b are formed on the upper insulation layer <NUM>. The first pad 37a is connected to the current spreading layer <NUM> through the openings 35a of the upper insulation layer <NUM>, and the second pad 37b is connected to the reflective electrodes <NUM> through the openings 35b of the upper insulation layer <NUM>. The first pad 37a and the second pad 37b may be used as pads for SMT(Surfac-mount technology) or connection of bumps in order to mount the light emitting diode on a sub-mount, a package, a printed circuit board, and the like.

The first and second pads 37a, 37b may be formed at the same time by the same process, for example, photolithography, lift-off, and the like. The first and second pads 37a, 37b may include, for example, a bonding layer of Ti, Cr, Ni, and the like, and a highly conductive metal layer of Al, Cu, Ag, Au, and the like.

Thereafter, the substrate <NUM> is divided into individual light emitting diode chips, thereby providing final light emitting diodes. The substrate <NUM> may be removed from the light emitting diode before or after division of the substrate into individual light emitting diode chips.

Next, the structure of the light emitting diode according to the embodiment of the invention will be described in detail with reference to <FIG>.

The light emitting diode includes the first conductive type semiconductor layer <NUM>, the mesas M, the reflective electrodes <NUM>, and the current spreading layer <NUM>, and the light emitting diode may include the substrate <NUM>, the lower insulation layer <NUM>, , the upper insulation layer <NUM>, the first pad 37a, and the second pad 37b.

The substrate <NUM> may be a growth substrate for growing gallium nitride epitaxial layers, and may be, for example, a sapphire substrate, a carbon nitride substrate, a silicon substrate, or a gallium nitride substrate. In addition, the substrate <NUM> may be a patterned substrate, as described with reference to <FIG>.

The first conductive type semiconductor layer <NUM> is continuously formed and the plural mesas M separated from each other are disposed on the first conductive type semiconductor layer <NUM>. As shown in <FIG> , each of the mesas M includes the active layer <NUM> and the second conductive type semiconductor layer <NUM>, and extends towards one side to be parallel to other mesas. Here, the mesas M have a stack of gallium nitride-based compound semiconductors. As shown in <FIG> , the mesas M may be disposed only within an upper region of the first conductive type semiconductor layer <NUM>. Alternatively, as shown in <FIG> , the mesas M may extend to an edge of an upper surface of the first conductive type semiconductor layer <NUM> in one direction, whereby the upper surface of the first conductive type semiconductor layer <NUM> may be divided into plural areas. As a result, this structure relieves current crowding near corners of the mesas M, thereby improving current spreading performance.

Each of the reflective electrodes <NUM> is disposed on the corresponding mesa M to be in ohmic contact with the second conductive type semiconductor layer <NUM>. As described with reference to <FIG> , each of the reflective electrodes <NUM> may include the reflective layer <NUM> and the barrier layer <NUM>, which may cover an upper surface and a side surface of the reflective layer <NUM>.

The current spreading layer <NUM> covers the plurality of mesas M and the first conductive type semiconductor layer <NUM>. The current spreading layer <NUM> has openings 33a, each of which is disposed within an upper region of each of the mesas M, and through which the reflective electrodes <NUM> are exposed. In addition, the current spreading layer <NUM> is in ohmic contact with the first conductive type semiconductor layer <NUM> and is isolated from the plurality of mesas M. The current spreading layer <NUM> may include a reflective metal such as Al.

The current spreading layer <NUM> may be isolated from the plurality of mesas M by the lower insulation layer <NUM>. For example, the lower insulation layer <NUM> may be disposed between the plurality of mesas M and the current spreading layer <NUM> to isolate the current spreading layer <NUM> from the plurality of mesas M. In addition, the lower insulation layer <NUM> may include openings 31b which are disposed on upper regions of the respective mesas M and through which the reflective electrodes <NUM> are exposed, and openings 31a through which the first conductive type semiconductor layer <NUM> is exposed. The current spreading layer <NUM> may be connected to the first conductive type semiconductor layer <NUM> through the openings 31a. The openings 31b of the lower insulation layer <NUM> are narrower than the openings 33a of the current spreading layer <NUM> and all of the openings 31b are exposed through the openings 33a.

The upper insulation layer <NUM> covers at least part of the current spreading layer <NUM>. In addition, the upper insulation layer <NUM> has openings 35b through which the reflective electrodes <NUM> are exposed. Further, the upper insulation layer <NUM> may include openings 35a through which the current spreading layer <NUM> is exposed. The upper insulation layer <NUM> may cover sidewalls of the openings 33a of the current spreading layer <NUM>.

The first pad 37a may be disposed on the current spreading layer <NUM>, and may be connected to the current spreading layer <NUM>, for example, through the openings 35a of the upper insulation layer <NUM>. In addition, the second pad 37b is connected to the reflective electrodes <NUM> exposed through the openings 35b.

According to this invention, the current spreading layer <NUM> covers substantially an overall area of the first conductive type semiconductor layer <NUM> between the mesas M. As a result, current can be easily spread through the current spreading layer <NUM>.

Furthermore, as the current spreading layer <NUM> includes the reflective layer formed of a reflective metal such as Al or as the lower insulation layer is formed as a reflective insulation layer, the light emitting diode allows light that is not reflected by the reflective electrodes <NUM> to be reflected by the current spreading layer <NUM> or the lower insulation layer <NUM>, thereby improving light extraction efficiency.

On the other hand, when the reflective metal layer <NUM> and the barrier metal layer <NUM> of the reflective electrode <NUM> have a significant difference in coefficient of thermal expansion, stress occurs on the reflective metal layer <NUM>, thereby causing the reflective metal layer <NUM> to be separated from the mesas M. Accordingly, a stress relieving layer may be interposed between the reflective metal layer <NUM> and the barrier metal layer <NUM> to relieve stress due to difference in coefficient of thermal expansion therebetween.

<FIG> is a partial sectional view of a light emitting diode having a reflective electrode including a stress relieving layer.

Referring to <FIG> , a first semiconductor layer <NUM>, an active layer <NUM>, a second semiconductor layer <NUM>, and a reflective electrode <NUM> are formed on a substrate <NUM>.

The substrate <NUM> may be any substrate so long as the substrate permits growth of the first semiconductor layer <NUM> thereon. For example, the substrate <NUM> may be a sapphire (Al<NUM>O<NUM>) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, an indium gallium nitride (InGaN) substrate, an aluminum gallium nitride (AlGaN) substrate, an aluminum nitride (AIN) substrate, a gallium oxide (Ga<NUM>O<NUM>) substrate, or a silicon substrate. Specifically, the substrate <NUM> maybe a sapphire substrate.

In addition, the substrate <NUM> may be a substrate which is not subjected to surface patterning, or may be a patterned substrate as shown in <FIG>.

The first semiconductor layer <NUM> is disposed on the substrate <NUM>. For example, the first semiconductor layer <NUM> may be an n-type conductive type semiconductor layer.

In addition, the active layer <NUM> formed on the first semiconductor layer <NUM> may have a single quantum well structure in which a well layer and a barrier layer are stacked, or may be a multi-quantum well structure in which well layers and barrier layers are alternately stacked one above another.

The second semiconductor layer <NUM> is disposed on the active layer <NUM>. For example, the second semiconductor layer <NUM> may be a p-type conductive type semiconductor layer.

Further, the first semiconductor layer <NUM>, the active layer <NUM>, and the second semiconductor layer <NUM> may include GaN, AIN, InGaN or AlInGaN. If the first semiconductor layer <NUM> includes GaN, it is desirable that the active layer <NUM> and the second semiconductor layer <NUM> also include GaN.

Here, since the second semiconductor layer <NUM> has a conductive type in complementary relation with the first semiconductor layer <NUM>, the second semiconductor layer <NUM> is implanted with different types of dopants than those of the first semiconductor layer <NUM>. Specifically, when dopants having donor functions are implanted into the first semiconductor layer <NUM>, dopants having acceptor functions are implanted in the second semiconductor layer <NUM>. Further, the active layer <NUM> preferably includes a material capable of creating a band gap for formation of the barrier layer and the well layer.

The reflective electrode <NUM> is formed on the second semiconductor layer <NUM>.

The reflective electrode <NUM> includes an ohmic connection layer <NUM>, a reflective metal layer <NUM>, a stress relieving layer <NUM>, and a barrier metal layer <NUM>.

The ohmic connection layer <NUM> may be formed of any material capable of achieving ohmic contact between the reflective metal layer <NUM> and the second semiconductor layer <NUM>. Thus, the ohmic connection layer <NUM> may include a metal including Ni or Pt, and may also include a conductive oxide such as ITO, ZnO, and the like. In some embodiments, the ohmic connection layer <NUM> may be omitted.

The reflective metal layer <NUM> is formed on the ohmic connection layer <NUM>. The reflective metal layer <NUM> reflects light generated in the active layer <NUM>. Accordingly, the reflective metal layer is formed of a material having high conductivity and high reflectivity with respect to light. The reflective metal layer <NUM> may include Ag, Ag alloys, Al or Al alloys.

Further, the stress relieving layer <NUM> is formed on the reflective metal layer <NUM>. The stress relieving layer <NUM> has a coefficient of thermal expansion, which is greater than or equal to the coefficient of thermal expansion of the barrier metal layer <NUM> and is lower than or equal to the coefficient of thermal expansion of the reflective metal layer <NUM>. With this structure, stress caused by difference in coefficient of thermal expansion between the reflective metal layer <NUM> and the barrier metal layer <NUM> can be relieved. Accordingly, the material of the stress relieving layer <NUM> is selected depending on the materials of the reflective metal layer <NUM> and the barrier metal layer <NUM>.

The barrier metal layer <NUM> is formed on the stress relieving layer <NUM>. The barrier metal layer <NUM> is formed to surround at least a side surface of the reflective metal layer <NUM> while surrounding an upper portion and a side surface of the stress relieving layer <NUM>. With this structure, it is possible to prevent diffusion of metal elements or ions constituting the reflective metal layer <NUM>. Further, stress caused by difference in coefficient of thermal expansion between the reflective metal layer <NUM> and the barrier metal layer <NUM> is absorbed by the stress relieving layer <NUM>.

For example, when the reflective metal layer <NUM> includes Al or Al alloys and the barrier metal layer <NUM> includes W, TiW or Mo, the stress relieving layer <NUM> may be formed as a single layer of Ag, Cu, Ni, Pt, Ti, Rh, Pd or Cr, or as a composite layer of Cu, Ni, Pt, Ti, Rh, Pd or Au. In addition, when the reflective metal layer <NUM> includes Al or Al alloys and the barrier metal layer <NUM> includes Cr, Pt, Rh, Pd or Ni, the stress relieving layer <NUM> may be formed as a single layer of Ag or Cu or as a composite layer of Ni, Au, Cu or Ag.

In addition, when the reflective metal layer <NUM> includes Ag or Ag alloys and the barrier metal layer <NUM> includes W, TiW or Mo, the stress relieving layer <NUM> may be formed as a single layer of Cu, Ni, Pt, Ti, Rh, Pd or Cr, or as a composite layer of Cu, Ni, Pt, Ti, Rh, Pd, Cr or Au. Further, when the reflective metal layer <NUM> includes Ag or Ag alloys and the barrier metal layer <NUM> includes Cr or Ni, the stress relieving layer <NUM> may be formed as a single layer of Cu, Cr, Rh, Pd, TiW or Ti, or as a composite layer of Ni, Au or Cu.

<FIG> are sectional views illustrating a method of manufacturing the light emitting diode shown in <FIG> , in accordance with one embodiment of the present invention.

Referring to <FIG> , a first semiconductor layer <NUM>, an active layer <NUM> and a second semiconductor layer <NUM> are sequentially formed on a substrate <NUM> to form a semiconductor stack.

The substrate <NUM> may be formed of sapphire (Al 2O <NUM>), silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AIN), gallium oxide (Ga <NUM><NUM>), or silicon. Specifically, the substrate <NUM> may be a sapphire substrate. Further, the substrate <NUM> may be a patterned substrate, as shown in <FIG>.

Further, the first semiconductor layer <NUM> is formed on the substrate <NUM>. The first semiconductor layer <NUM> may be an n-type conductive type semiconductor layer.

The second semiconductor layer <NUM> is disposed on the active layer <NUM>. The second semiconductor layer <NUM> may be a p-type conductive type semiconductor layer.

Further, the first semiconductor layer <NUM>, the active layer <NUM>, and the second semiconductor layer <NUM> are the same as those described with reference to <FIG> in terms of materials and configuration, and detailed descriptions thereof will be omitted.

Further, the first semiconductor layer <NUM>, the active layer <NUM>, and the second semiconductor layer <NUM> are formed through epitaxial growth. For example, the first semiconductor layer <NUM>, the active layer <NUM>, and the second semiconductor layer <NUM> may be formed through metal organic chemical vapor deposition (MOCVD).

Referring to <FIG> , part of the active layer <NUM> and part of the second semiconductor layer <NUM> are removed by typical etching. As a result, the first semiconductor layer <NUM> is partially exposed. Through the etching process, an upper surface of the first semiconductor layer <NUM> is exposed, and side surfaces of the active layer <NUM> and the second semiconductor layer <NUM> are exposed. As a result, the active layer <NUM> and the second semiconductor layer <NUM> are partially removed to form trenches and holes through the etching process. In other words, the mesa-etched areas <NUM> formed from the surface of the second semiconductor layer <NUM> of <FIG> to the surface of the first semiconductor layer <NUM> may be a trench-shaped stripe type or a hole type.

In addition, when the mesa-etched areas <NUM> are formed in a stripe type, a perpendicular profile or an oblique profile may be formed from the surface of the first semiconductor layer <NUM>. Preferably, an oblique profile slanted at an angle of <NUM>° to <NUM>° from the surface of the first semiconductor layer <NUM> is provided. In addition, when the mesa-etched areas <NUM> are formed in a hole type of a substantially circular shape, a perpendicular profile or an oblique profile may be formed from the surface of the first semiconductor layer <NUM>. Preferably, an oblique profile slanted at an angle of <NUM>° to <NUM>° from the surface of the first semiconductor layer <NUM> is provided. If the profile has an angle of less than <NUM>°, a distance between the mesa-etched areas <NUM> significantly increases in an upward direction. In this case, there is a problem of deterioration in concentration of light generated by a light emitting structure. Further, if the profile has an angle of greater than <NUM>°, the mesa-etched areas <NUM> have a substantially perpendicular profile. In this case, reflection of light by sidewalls of the mesa-etched areas becomes insignificant.

Referring to <FIG> , a photoresist pattern <NUM> is formed on exposed areas of the first semiconductor layer <NUM>, which are exposed to the mesa-etched areas <NUM>. The first semiconductor layer <NUM> constitutes lower surfaces of the mesa-etched areas <NUM>. The photoresist pattern <NUM> may have a perpendicular profile from the surface of the first semiconductor layer <NUM>, and may be formed in an overhang structure, a lower surface of which has a narrower width than an upper surface thereof, according to implementation. The photoresist pattern <NUM> may be formed using a negative type photoresist. Accordingly, the exposed portion has cross-linked characteristics. To form an overhang structure, the photoresist pattern <NUM> is preferably subjected to exposure at a predetermined inclination. For the overhang structure, a separation between lower surfaces of the photoresist pattern <NUM> may be greater than a separation between upper surfaces thereof by a distance of <NUM> or more.

Referring to <FIG> , a reflective metal layer <NUM> and a stress relieving layer <NUM> are sequentially stacked on the second semiconductor layer <NUM>.

The reflective metal layer <NUM> includes Al, Al alloys, Ag or Ag alloys. The reflective metal layer <NUM> may be formed through typical metal deposition. Preferably, the reflective metal layer <NUM> is formed by e-beam evaporation, by which most metal elements or ions can be moved onto the surface of the second semiconductor layer <NUM> in a perpendicular direction. By this process, the metal elements or ions are introduced in an anisotropic manner into a space between the photoresist patterns <NUM> to form the reflective metal layer <NUM>.

The reflective metal layer <NUM> preferably has a thickness of <NUM> to <NUM>. If the thickness of the reflective metal layer <NUM> is less than <NUM>, there is a problem of inefficient reflection of light generated in the active layer <NUM>. On the other hand, if the thickness of the reflective metal layer <NUM> is greater than <NUM>, there is a problem of processing loss due to excess processing time.

Optionally, an ohmic connection layer <NUM> may be formed. The ohmic connection layer <NUM> may include Ni, Pt, ITO, or ZnO. In addition, the ohmic connection layer <NUM> may have a thickness of <NUM> to <NUM>. If the thickness of the ohmic connection layer <NUM> is less than <NUM>, it is difficult to secure sufficient ohmic characteristics due to a very thin thickness. If the thickness of the ohmic connection layer is greater than <NUM>, there is a problem of reduction in amounts of light reflected by the reflective metal layer <NUM> due to reduction in transmission amount of light.

A stress relieving layer <NUM> is formed on the reflective metal layer <NUM>. The stress relieving layer <NUM> may be formed through a typical metal deposition process. Preferably, e-beam evaporation exhibiting high directionality is used. In other words, metal elements or ions evaporated by electron beams have directionality and anisotropy in the space between the photoresist patterns <NUM>, and form a metal layer. Further, the stress relieving layer <NUM> has a coefficient of thermal expansion which is lower than that of the reflective metal layer <NUM> and higher than that of the barrier metal layer <NUM> of <FIG>. Accordingly, the material of the stress relieving layer <NUM> may be selected depending upon the materials of the reflective metal layer <NUM> and the barrier metal layer <NUM>. The material of the stress relieving layer <NUM> will be described below.

When the reflective metal layer <NUM> and the stress relieving layer <NUM> are formed by e-beam evaporation, side surfaces of the reflective metal layer <NUM> and the stress relieving layer <NUM> are exposed. In addition, the reflective metal layer <NUM> and the stress relieving layer <NUM> are formed corresponding to open upper regions of the photoresist pattern <NUM> by anisotropic deposition.

Further, in <FIG> , a metal deposition formed on the photoresist pattern <NUM> during formation of the reflective metal layer <NUM> and the stress relieving layer <NUM> is omitted.

Referring to <FIG> , a barrier metal layer <NUM> is formed through the open areas of the photoresist pattern <NUM>.

The barrier metal layer <NUM> includes W, TiW, Mo, Cr, Ni, Pt, Rh, Pd or Ti. Specifically, the material of the barrier metal layer <NUM> is selected dependent upon the material of the reflective metal layer <NUM> and the stress relieving layer <NUM>.

The barrier metal layer <NUM> is formed on the stress relieving layer <NUM> and shields the side surfaces of the reflective metal layer <NUM> and the stress relieving layer <NUM>. With this structure, it is possible to prevent diffusion of metal elements constituting the reflective metal layer <NUM> into the second semiconductor layer <NUM> through the side surfaces thereof. The barrier metal layer <NUM> is formed through typical metal deposition. Here, the barrier metal layer <NUM> is preferably formed through isotropic deposition. This is because the barrier metal layer <NUM> surrounds the side surfaces of the stress relieving layer <NUM> and the reflective metal layer <NUM>. For example, the barrier metal layer <NUM> may be formed by sputtering.

In addition, the barrier metal layer <NUM> may be formed of a specific metal to have a single layer of <NUM> or more. Further, the barrier metal layer <NUM> may be formed by alternately stacking two or more metal layers each having a thickness of <NUM> or more one above another. For example, the barrier metal layer <NUM> may be formed by alternately stacking a TiW layer having a thickness of <NUM> and a Ni or Ti layer having a thickness of <NUM>.

Further, Ni/Au/Ti layers may be additionally formed on the barrier metal layer <NUM> to secure stable contact with subsequent materials.

As described above, the material of the stress relieving layer <NUM> is selected depending upon the materials of the reflective metal layer <NUM> and the barrier metal layer <NUM>. This is because the stress relieving layer <NUM> has a coefficient of thermal expansion that is higher than that of the barrier metal layer <NUM> and lower than that of the reflective metal layer <NUM>. Thus, when the reflective metal layer <NUM> includes Al or Al alloys and the barrier metal layer <NUM> includes W, TiW or Mo, the stress relieving layer <NUM> is formed as a single layer of Ag, Cu, Ni, Pt, Ti, Rh, Pd or Cr, or as a composite layer of Cu, Ni, Pt, Ti, Rh, Pd or Au. Further, when the reflective metal layer <NUM> includes Al or Al alloys and the barrier metal layer <NUM> includes Ti, Cr, Pt, Rh, Pd or Ni, the stress relieving layer <NUM> may be a single layer of Ag or Cu or as a composite layer of Ni, Au, Cu or Ag. Further, when the reflective metal layer <NUM> includes Ag or Ag alloys and the barrier metal layer <NUM> includes W, TiW or Mo, the stress relieving layer <NUM> is formed as a single layer of Cu, Ni, Pt, Ti, Rh, Pd or Cr, or as a composite layer of Cu, Ni, Pt, Ti, Rh, Pd, Cr or Au. Further, when reflective metal layer <NUM> includes Ag or Ag alloys and the barrier metal layer <NUM> includes Pt or Ni, the stress relieving layer <NUM> is formed as a single layer of Cu, Cr, Rh, Pd, TiW or Ti, or as a composite layer of Ni, Au or Cu.

Referring to <FIG> , the photoresist pattern is removed by a lift-off process. As a result, the first semiconductor layer <NUM> at a lower side and reflective electrodes <NUM> at an upper side are exposed. In addition, the mesa-etched areas <NUM> are exposed through removal of the photoresist pattern. As described above, the mesa-etched areas <NUM> may be formed in a stripe type or hole type.

Through the above process, the reflective electrodes <NUM> are formed on the second semiconductor layer <NUM>. Each of the reflective electrodes <NUM> includes the reflective metal layer <NUM>, the stress relieving layer <NUM> and the barrier metal layer <NUM>. The stress relieving layer <NUM> has a coefficient of thermal expansion that is lower than that of the reflective metal layer <NUM> and higher than that of the barrier metal layer <NUM>. Accordingly, stress caused by difference in coefficient of thermal expansion between the reflective metal layer <NUM> and the barrier metal layer <NUM> is absorbed by the stress relieving layer <NUM>.

<FIG> are plan views and sectional views illustrating a method of manufacturing the light emitting diode having the structure of <FIG> in accordance with another embodiment of the present invention.

Referring to <FIG> , it is assumed that the mesa-etched areas <NUM> of <FIG> have a stripe shape. Then, a lower insulation layer <NUM> is formed on an overall surface of the structure shown in <FIG>. The lower insulation layer <NUM> allows an upper surface of the reflective electrode <NUM> to be partially exposed therethrough while allowing a surface of the first semiconductor layer <NUM> to be exposed therethrough. To form the lower insulation layer <NUM>, an oxide layer such as SiO<NUM> and the like, a nitride layer such as SiNx and the like, an insulation layer such as MgF<NUM>, or a DBR (distributed Bragg reflector) of SiO<NUM>/TiO<NUM>, and the like is formed on the structure of <FIG>. Thereafter, part of the reflective electrodes <NUM> and the surface of the first semiconductor layer <NUM> are exposed by typical photolithography.

In <FIG> , a lower figure is a sectional view taken along line A-A' of the plan view of <FIG>. In this sectional view, line A-A' is discontinuous and a portion depicted by a dotted line is not shown. In this regard, it should be noted that a discontinuous line is illustrated as a continuous line in the sectional view. This is also applied to <FIG>.

Further, although three reflective electrodes <NUM> are exposed in this embodiment, it should be understood that this structure is provided for illustration only, and the number of exposed reflective electrodes <NUM> can be changed, as needed.

In some areas, the reflective electrodes <NUM> are exposed, and in the mesa-etched areas <NUM>, the first semiconductor layer <NUM> is exposed. Further, in a region where the reflective electrodes <NUM> are not exposed, the lower insulation layer <NUM> completely shields the reflective electrodes <NUM>.

Referring to <FIG> , the current spreading layer <NUM> is formed on the lower insulation layer <NUM>. The current spreading layer <NUM> is formed of a conductive material. Further, the current spreading layer <NUM> exposes part of the reflective electrodes <NUM>.

The current spreading layer <NUM> may include Al. As a result, the first semiconductor layer <NUM> and the current spreading layer <NUM> are electrically connected to each other, and the reflective electrodes <NUM> are electrically isolated from the current spreading layer <NUM> by the lower insulation layer <NUM>.

This can be confirmed through a lower sectional view. Specifically, in the sectional view taken along line A-A', two reflective electrodes <NUM> are exposed in a portion intersecting the two exposed reflective electrodes <NUM>, and in a portion taken along a line intersecting a region buried only by the incurrent spreading layer <NUM>, the lower insulation layer <NUM> is formed on the reflective electrodes <NUM> and the current spreading layer <NUM> is formed on the lower insulation layer <NUM>. Further, in <FIG> , the current spreading layer <NUM> is formed on the surface of the first semiconductor layer <NUM> exposed in a stripe shape.

Since the current spreading layer <NUM> includes Al, it is possible to reflect light generated in the active layer. Accordingly, the current spreading layer <NUM> acts as a reflective layer for reflecting light while achieving electrical connection to the first semiconductor layer <NUM>. Before formation of the current spreading layer <NUM>, a separate bonding layer having the same shape as that of the current spreading layer <NUM> may be formed. The bonding layer includes Ti, Cr or Ni. The bonding layer facilitates ohmic connection between the current spreading layer <NUM> and the first semiconductor layer <NUM>.

Further, a passivation layer may be formed on the current spreading layer <NUM>. The passivation layer may be a single layer of Ni, Cr or Au, or a composite layer thereof. The passivation layer is preferably a composite layer of Ti/Al/Ti/Ni/Au.

Referring to <FIG> , an upper insulation layer <NUM> is formed on the structure of <FIG>. Both the current spreading layer <NUM> and the reflective electrode <NUM> are partially exposed through the upper insulation layer <NUM>. The reflective electrodes <NUM> are electrically connected to the second semiconductor layer <NUM>, and the current spreading layer <NUM> is electrically connected to the first semiconductor layer <NUM>. Thus, an electric path between the first semiconductor layer <NUM> and the second semiconductor layer <NUM> is open through the upper insulation layer <NUM>.

The upper insulation layer <NUM> may be formed of any insulation material, for example, oxide insulation materials, nitride insulation materials, polymers such as polyimide, Teflon, Parylene, and the like.

Referring to <FIG> , a first pad <NUM> and a second pad <NUM> are formed on the structure of <FIG>. The first pad <NUM> is electrically connected to the current spreading layer <NUM> exposed in <FIG>. Accordingly, the first pad <NUM> is electrically connected to the first semiconductor layer <NUM>. This means that the first semiconductor layer <NUM> is electrically connected to an external power source or power supply through the first pad <NUM>. Further, the second pad <NUM> is electrically connected to the reflective electrodes <NUM> exposed in <FIG>. Thus, the second pad <NUM> is electrically connected to the second semiconductor layer <NUM>. This means that the second semiconductor layer <NUM> is electrically connected to an external power source or power supply through the second pad <NUM>.

The first pad <NUM> and the second pad <NUM> may be formed as a double-layer structure including a layer of Ti, Cr or Ni and a layer of Al, Cu, Ag or Au. In addition, the first pad <NUM> and the second pad <NUM> may be formed by patterning a photoresist, depositing a metal into a space between patterned areas, followed by a lift-off process for removing the photoresist pattern. Alternatively, after forming a double-layer or single layer metal film, a pattern may be formed through typical photolithography, and used as an etching mask to form the first pad and the second pad through dry etching or wet etching. Here, the etchant for dry etching and wet etching may vary depending upon the kind of metal to be etched.

<FIG> shows a sectional view taken along line B-B' of <FIG> and a sectional view taken along line C-C' of <FIG>.

First, line B-B' corresponds to a region in which the first pad <NUM> is formed. The first pad <NUM> is electrically connected to the exposed current spreading layer <NUM>.

Next, line C-C' corresponds to a region in which the second pad <NUM> is formed. The second pad <NUM> is electrically connected to the exposed reflective electrode <NUM>.

As a result, it can be seen that the first pad <NUM> is electrically connected to the semiconductor layer <NUM> and the second pad <NUM> is electrically connected to the second semiconductor layer <NUM>.

In their respective regions the first pad <NUM> and the second pad <NUM> both cover the overall structure formed by the first conductivity type semiconductor layer <NUM>, the active layer <NUM>, the second conductivity type semiconductor layer <NUM>, the mesa-etched areas <NUM>, the reflective electrode <NUM>, the lower insulation layer <NUM>, the current spreading layer <NUM>, and the upper insulation layer <NUM>.

<FIG> are plan views and sectional views illustrating a method of manufacturing the light emitting diode having the structure of <FIG> in accordance with a further embodiment of the present invention.

<FIG> are plan views and sectional views of a light emitting diode module having the structure of <FIG> in accordance with a fourth embodiment of the invention.

Referring to <FIG> , in this embodiment, mesa-etched areas <NUM> of <FIG> are formed in a hole type. Accordingly, a first semiconductor layer <NUM> is exposed in a substantially circular shape.

Next, a lower insulation layer <NUM> is formed on an overall surface of the structure of <FIG>. The lower insulation layer <NUM> exposes part of an upper surface of each of the reflective electrodes <NUM> while exposing a surface of the first semiconductor layer <NUM>. The lower insulation layer <NUM> is formed in the same manner as in <FIG> , and detailed descriptions thereof will be omitted.

In <FIG> , a lower figure is a sectional view taken along line D-D' of the plan view of <FIG>. In this sectional view, line D-D' is discontinuous along a dotted line and is provided by connecting solid lines. Thus, the sectional view does not include a dotted line section and shows only a solid line section.

Further, in <FIG> , the hole type mesa-etched areas <NUM> are exaggerated for convenience in description. Thus, the number and shape of the hole type mesa-etched areas <NUM> may vary according to implementation.

Referring to <FIG> , a current spreading layer <NUM> is formed on the lower insulation layer <NUM>. The current spreading layer <NUM> is formed of a conductive material. In addition, the current spreading layer <NUM> exposes part of the reflective electrodes <NUM>.

This can be confirmed through a lower sectional view. Specifically, in the sectional view taken along line D-D', two reflective electrodes <NUM> are exposed in a portion intersecting the two exposed reflective electrodes <NUM>, and in a portion taken along line intersecting a region buried only by the incurrent spreading layer <NUM>, the lower insulation layer <NUM> is formed on the reflective electrodes <NUM> and the current spreading layer <NUM> is formed on the lower insulation layer <NUM>. Further, in <FIG> , the current spreading layer <NUM> is formed on the surface of the first semiconductor layer <NUM> exposed in a hole shape.

Since the current spreading layer <NUM> includes Al, it is possible to reflect light generated in the active layer. Accordingly, the current spreading layer <NUM> acts as a reflective layer for reflecting light while achieving electrical connection to the first semiconductor layer <NUM>.

Before formation of the current spreading layer <NUM>, a separate bonding layer having the same shape as that of the current spreading layer <NUM> may be formed. The bonding layer includes Ti, Cr or Ni. The bonding layer facilitates ohmic connection between the current spreading layer <NUM> and the first semiconductor layer <NUM>.

The material and formation of the upper insulation layer <NUM> are the same as those described with reference to <FIG> , and detailed descriptions thereof will be omitted.

Next, as described in <FIG> , a first pad <NUM> and a second pad <NUM> are formed. The first pad <NUM> is electrically connected to the current spreading layer <NUM> exposed in <FIG>. Accordingly, the first pad <NUM> is electrically connected to the first semiconductor layer <NUM>. This means that the first semiconductor layer <NUM> is electrically connected to an external power source or power supply through the first pad <NUM>. Further, the second pad <NUM> is electrically connected to the reflective electrodes <NUM> exposed in <FIG>. Thus, the second pad <NUM> is electrically connected to the second semiconductor layer <NUM>. This means that the second semiconductor layer <NUM> is electrically connected to an external power source or power supply through the second pad <NUM>.

<FIG> is a sectional view of a light emitting device in accordance with a further embodiment not forming part of the present invention. In the aforementioned embodiments, the other surface of the substrate opposite to the surface of the substrate on which the semiconductor stack is formed is not subjected to texturing. In this embodiment, the other surface of the substrate is subjected to texturing to improve light extraction efficiency. Such a process of texturing the surface of the substrate may be applied to a flip chip type light emitting diode as well as the aforementioned embodiments.

Referring to <FIG> , a light emitting device <NUM> includes a substrate <NUM>, a light emitting structure <NUM>, a passivation layer <NUM>, pads <NUM>, bumps <NUM>, and a sub-mount <NUM>.

The substrate <NUM> may be a growth substrate. The growth substrate may be any substrate, for example, a sapphire substrate, a silicon carbide substrate, a silicon substrate, and the like, without being limited thereto.

The light emitting structure <NUM> is formed on one surface of the substrate <NUM>.

The substrate <NUM> has a ground texture <NUM> formed on the other surface thereof, and a converse patterned sapphire substrate (PSS) pattern <NUM> formed on the one surface thereof.

Further, the substrate <NUM> may include an anti-reflective layer <NUM> on the other surface thereof, and a chamfered edge <NUM>.

The ground texture <NUM> is formed on the other surface of the substrate <NUM>, and may be formed by grinding the other surface of the substrate <NUM> using a grinder (not shown), removing particles from the other surface of the substrate roughened by grinding through treatment using phosphoric acid or a mixture of sulfuric acid and phosphoric acid, and rounding sharp corners. As a result, the ground texture <NUM> may include a surface having irregular roughness, and round corners or protrusions subjected to rounding through treatment using phosphoric acid or a mixture of sulfuric acid and phosphoric acid.

The converse PSS pattern <NUM> may be formed on the one surface of the substrate <NUM>. The converse PSS pattern <NUM> may include a plurality of grooves having a semi-spherical shape, a conical shape, or a faceted conical shape. In other words, the converse PSS pattern <NUM> may be provided in a structure wherein a plurality of semi-spherical grooves, a plurality of conical grooves, or a plurality of faceted conical grooves is formed on the one surface of the substrate <NUM>.

Here, the interior of the converse PSS pattern <NUM>, that is, the grooves of the PSS pattern, may be filled with a buffer layer (not shown) described below, or, a first conductive type semiconductor layer <NUM>. In addition, although not shown in <FIG> , the grooves of the PSS pattern <NUM> may be filled with an insulation material, such as silicon oxide or silicon nitride, such that semiconductor layers formed on the substrate <NUM> are selectively grown to form the light emitting structure <NUM>, preferably, through epitaxial growth, thereby reducing dislocation density.

The anti-reflective layer <NUM> may be formed of silicon oxide, an oxide such as TiO<NUM>, AlTiO<NUM>, CeO<NUM> and the like, a nitride such as silicon nitride, or an insulation material such as MgF<NUM> and the like, and may have a multilayer structure including at least one of these insulation materials.

In <FIG> , the anti-reflective layer <NUM> is illustrated as being disposed not only on the ground texture <NUM> but also on the chamfered corners <NUM>. However, it should be understood that the anti-reflective layer <NUM> may be disposed only on the ground texture <NUM> without being disposed on the chamfered corners <NUM>.

The chamfered corners <NUM> may be formed by chamfering corners of the substrate <NUM>.

Therefore, the light emitting device <NUM> according to the embodiment of the invention includes the substrate <NUM>, which is formed on one surface thereof with the converse PSS pattern <NUM>, and on the other surface thereof with the ground texture <NUM>, the anti-reflective layer <NUM> and the chamfered corner <NUM>, whereby light generated in the light emitting structure <NUM> formed on the one surface of the substrate <NUM> can be efficiently emitted to the other surface of the substrate <NUM>.

That is, the ground texture <NUM> serves to allow light to efficiently travel to the outside through the substrate <NUM> instead of being reflected inside the substrate <NUM>. The converse PSS pattern <NUM> serves to allow light to efficiently travel through the substrate instead of being reflected towards the light emitting structure <NUM> when the light is generated in the light emitting structure <NUM> and travels through the substrate <NUM>. Further, the anti-reflective layer <NUM> suppresses total reflection of the substrate by relieving a difference in index of refraction between the substrate <NUM> and the outside, that is, air. On the other hand, the chamfered corner <NUM> serves to allow light, which travels towards side surfaces of the substrate <NUM>, to be efficiently emitted to the outside.

Here, as shown in <FIG> , when the anti-reflective layer <NUM> is not formed on the substrate <NUM>, the substrate has a light transmittance in percent in the mid-<NUM> over a wide wavelength band. On the contrary, when the anti-reflective layer <NUM> is formed thereon, the substrate has a light transmittance in percent in the mid-<NUM> and exhibits significant variation according to wavelengths. For example, the substrate has a significantly improved light transmittance of <NUM>% or higher in a certain wavelength band, near about <NUM>, about <NUM>, or about <NUM>.

At this time, the material and thickness of the anti-reflective layer <NUM> may be selected according to wavelengths of light emitted from the light emitting structure <NUM>, or according to desired wavelengths, thereby providing a maximum transmittance at a corresponding wavelength, that is, maximum luminous efficacy.

The light emitting structure <NUM> may include a first conductive type semiconductor layer <NUM>, an active layer <NUM>, a second conductive type semiconductor layer <NUM>, and a transparent electrode layer <NUM>. Further, the light emitting structure <NUM> may include a buffer layer (not shown), a super-lattice layer (not shown), or an electron blocking layer (not shown).

In the light emitting structure <NUM>, the first conductive type semiconductor layer <NUM> is partially exposed by mesa-etching at least part of the second conductive type semiconductor layer <NUM> and the active layer <NUM>.

The first conductive type semiconductor layer <NUM> may be a first conductive impurity-doped, for example, N-type impurity-doped, III-N-based compound semiconductor, for example, an (Al, Ga, In)N-based Group III nitride semiconductor layer. The first conductive type semiconductor layer <NUM> may be an N-type impurity doped GaN layer, that is, an N-GaN layer. Further, the first conductive type semiconductor layer <NUM> may be formed as a single layer or as multiple layers. For example, when the first conductive type semiconductor layer <NUM> is formed as multiple layers, the first conductive type semiconductor layer <NUM> may have a super-lattice layer.

The active layer <NUM> may be formed of a III-N-based compound semiconductor, for example, an (Al, Ga, In)N semiconductor layer. The active layer <NUM> may be formed as a single layer or as multiple layers, and emit light at a predetermined wavelength. Further, the active layer <NUM> may have a single quantum well structure including a single well layer (not shown), or a multi-quantum well structure in which well layers (not shown) and barrier layers (not shown) are alternately stacked one above another. Here, each of the well layer (not shown) and the barrier layer (not shown), or both may have a super-lattice structure.

The second conductive type semiconductor layer <NUM> may be a second conductive impurity, for example, P-type impurity-doped III-N-based compound semiconductor, for example, an (Al, Ga, In)N-based Group III nitride semiconductor layer. The second conductive type semiconductor layer <NUM> may be a P-type impurity doped GaN layer, that is, a P-GaN layer. Further, the second conductive type semiconductor layer <NUM> may be formed as a single layer or as multiple layers. For example, the second conductive type semiconductor layer <NUM> may have a super-lattice structure.

The transparent electrode layer <NUM> may include ITO, TCO such as ZnO or IZO, or a contact material such as Ni/Au, and makes ohmic contact with the second conductive type semiconductor layer <NUM>.

The buffer layer (not shown) may be formed to relieve lattice mismatch between the substrate <NUM> and the first conductive type semiconductor layer <NUM>. In addition, the buffer layer (not shown) may be formed as a single layer or as multiple layers. When the buffer layer is formed as multiple layers, the buffer layer may be composed of a low temperature buffer layer and a high temperature buffer layer. The buffer layer (not shown) may be composed of AIN.

The super-lattice layer (not shown) may be disposed between the first conductive type semiconductor layer <NUM> and the active layer <NUM>, and may have a structure in which a plurality of III-N-based compound semiconductors, for example, (Al, Ga, In)N semiconductor layers, is stacked one above another. For example, the super-lattice layer may have a structure in which InN layers and InGaN layers are repeatedly stacked one above another. The super-lattice layer (not shown) may be formed before formation of the active layer <NUM> to prevent transfer of dislocations or defects to the active layer <NUM>, thereby relieving formation of dislocations or defects in the active layer <NUM> while improving crystallinity of the active layer <NUM>.

The electron blocking layer (not shown) may be disposed between the active layer <NUM> and the second conductive type semiconductor layer <NUM>. The electron blocking layer may be provided to improve efficiency in recombination of electrons and holes, and may be formed of a material having a relatively wide band gap. The electron blocking layer (not shown) may be formed of an (Al, In, Ga)N-based Group III nitride semiconductor, and may be, for example, a Mg-doped P-AlGaN layer.

The passivation layer <NUM> may be disposed on the substrate <NUM> including the light emitting structure <NUM>. The passivation layer <NUM> serves to protect the light emitting structure <NUM> under the passivation layer from external environments, and may be formed of an insulation layer including a silicon oxide layer.

The passivation layer <NUM> may include a first opening <NUM> through which part of the surface of the first conductive type semiconductor layer <NUM> exposed by mesa etching is exposed, and a second opening <NUM> through which part of the surface of the second conductive type semiconductor layer <NUM> is exposed.

The pads <NUM> may include a first pad <NUM> and a second pad <NUM>. The first pad <NUM> may be disposed on the substrate <NUM> including the passivation layer <NUM> thereon, and may contact the first conductive type semiconductor layer <NUM> exposed through the first opening <NUM>. The second pad <NUM> may be disposed on the substrate <NUM> including the passivation layer <NUM> thereon, and may contact the second conductive type semiconductor layer <NUM> exposed through the second opening <NUM>.

The pads <NUM> may include Ni, Cr, Ti, Al, Ag, or Au.

The bumps <NUM> may include a first bump <NUM> and a second bump <NUM>. The first bump <NUM> may be disposed on the first pad <NUM> and the second bump <NUM> may be disposed on the second pad <NUM>. The bumps <NUM> serve to support the substrate <NUM> including the light emitting structure <NUM> on the sub-mount <NUM>, and are disposed between the sub-mount <NUM> and the light emitting structure <NUM> to separate the light emitting structure <NUM> and the substrate from the sub-mount <NUM>. The bumps <NUM> may include Au.

The sub-mount <NUM> may include a first electrode <NUM> and a second electrode <NUM> disposed on one surface thereof. The first electrode <NUM> and the second electrode <NUM> may be respectively connected to the first pad <NUM> and the second pad <NUM> when the substrate <NUM> including the light emitting structure <NUM> is mounted on the sub-mount <NUM>.

<FIG> are sectional views illustrating a method of manufacturing the light emitting device of <FIG>.

Referring to <FIG> , a substrate <NUM> is prepared.

The substrate <NUM> may be a growth substrate. The growth substrate may be a sapphire substrate, a silicon carbide substrate, or a silicon substrate. In this embodiment, the substrate <NUM> may be a sapphire substrate.

Next, a plurality of semiconductor layers is formed on one surface of the substrate <NUM>. The plurality of semiconductor layers may include a first conductive type semiconductor layer <NUM>, an active layer <NUM>, and a second conductive type semiconductor layer <NUM>.

The plurality of semiconductor layers may be formed through epitaxial growth using chemical vapor deposition such as MOCVD and the like.

Before forming the plurality of semiconductor layers, a converse PSS pattern <NUM> may be formed on one surface of the substrate <NUM>. When the plurality of semiconductor layers is formed on the substrate <NUM> including the converse PSS pattern <NUM> thereon, the semiconductor layers may be selectively grown on a region of the substrate <NUM> on which the converse PSS pattern <NUM> is not formed, that is, on a predetermined area of the surface of the substrate <NUM>, thereby enabling control of dislocation density in the semiconductor layers.

The converse PSS pattern <NUM> may be formed by forming a photoresist pattern (not shown) having a plurality of open regions through which a predetermined area of one surface of the substrate <NUM> is exposed, followed by etching the one surface of the substrate <NUM> to a predetermined thickness using the photoresist pattern (not shown) as a mask. Etching of the substrate <NUM> may be realized by wet etching or dry etching. Wet etching may be performed using a wet etching solution which contains phosphoric acid and sulfuric acid, and dry etching may be performed by ICP etching using an ICP device.

The shape of the converse PSS pattern <NUM> may be determined depending upon the shape of the open regions of the photoresist pattern (not shown). That is, when the open regions of the photoresist pattern (not shown) have a circular shape, the converse PSS pattern <NUM> may be realized in the form of a plurality of grooves having a semi-spherical or conical shape, and when the open regions of the photoresist pattern (not shown) have a polygonal shape including a triangular shape, the converse PSS pattern <NUM> may be realized in the form of a plurality of grooves having a faceted conical shape including a triangular pyramidal shape.

Referring to <FIG> , next, a protective layer <NUM> is formed on the plurality of semiconductor layers. The protective layer <NUM> serves to protect the semiconductor layers upon grinding and treatment using phosphoric acid or a mixture of sulfuric acid and phosphoric acid described below. The protective layer <NUM> may be formed of a synthetic resin, such as a photoresist, or may be formed of insulation materials such as silicon oxide, nitride oxide, and the like.

Next, the other surface of the substrate <NUM> is subjected to grinding using a grinder.

In this operation, the substrate <NUM> is ground to a constant thickness. That is, the thickness of the substrate <NUM> is reduced as compared with the substrate <NUM> shown in <FIG>. For example, when the substrate <NUM> shown in <FIG> has a thickness of about <NUM>, the substrate <NUM> subjected to grinding may have a thickness of <NUM> or less, preferably <NUM>. In this regard, since the substrate <NUM> described with reference to <FIG> must endure thermal impact or stress due to formation of the plurality of semiconductor layers on the one surface of the substrate <NUM>, the substrate <NUM> described with reference to <FIG> preferably has a high thickness. However, it is desirable that the substrate <NUM> of the light emitting device <NUM> have a relatively thin thickness to allow light to pass through the substrate <NUM>. For this reason, the thickness of the substrate <NUM> is reduced.

Thereafter, the other surface of the substrate <NUM> subjected to grinding is subjected to treatment using a phosphoric acid solution or a solution of sulfuric acid and phosphoric acid to form a ground texture on the other surface of the substrate <NUM>, as shown in <FIG>. Thus, the ground texture <NUM> means a surface shape formed by treating the other surface of the substrate <NUM> using phosphoric acid or a mixture of sulfuric acid and phosphoric acid after grinding the other surface of the substrate <NUM>.

Here, surface roughness of the ground texture <NUM> may be adjusted by suitably adjusting conditions for grinding and treatment with phosphoric acid solution or a solution of sulfuric acid and phosphoric acid.

Specifically, the other surface of the substrate <NUM> subjected to grinding has irregular protrusions and depressions as shown in <FIG>. Here, surface roughness of the substrate <NUM> subjected to grinding may be adjusted by adjusting roughness of a blade or pad of the grinder or a grinding time. In addition, surface roughness of the substrate <NUM> may be adjusted by adjusting a processing time upon treatment of the ground substrate <NUM> with phosphoric acid solution or a solution of sulfuric acid and phosphoric acid. For example, when the grinder pad has high roughness and phosphoric acid or sulfuric-phosphoric acid treatment is performed in a short period of time, the ground texture <NUM> may have high surface roughness. Alternatively, when the grinder pad has low roughness and phosphoric acid or sulfuric-phosphoric acid treatment is performed in a relatively long period of time, the ground texture <NUM> may have relatively low surface roughness.

Referring to <FIG> , next, a photoresist pattern <NUM> is formed on the other surface of the substrate <NUM>.

The photoresist pattern <NUM> may include a plurality of open regions 374a through which a predetermined area of the other surface of the substrate <NUM> is exposed. The photoresist pattern <NUM> may be used as a hard mask (not shown). That is, a hard mask comprising a silicon oxide layer, a nitride layer, a metal layer, or the like may be formed on the other surface of the substrate <NUM>.

Thereafter, a plurality of parathion grooves <NUM> is formed on the other surface of the substrate <NUM> using the photoresist pattern <NUM> or the hard mask (not shown). In this case, the photoresist pattern <NUM> may be formed using a photoresist.

Each of the dividing groove <NUM> serves to define a region that separates the substrate <NUM>, and are preferably disposed corresponding to a region between the light emitting structures <NUM> described below.

Here, the dividing grooves <NUM> preferably have slanted sidewalls. This is because sidewalls of the dividing grooves <NUM> form the chamfered corners <NUM> after division of the substrate <NUM>.

The dividing grooves <NUM> may be formed by wet etching or dry etching. Wet etching may be performed using a wet etching solution which contains phosphoric acid and sulfuric acid, and dry etching may be performed by ICP etching using an ICP device.

Referring to <FIG> , light emitting structures <NUM> may be formed by removing the protective layer <NUM> from the one surface of the substrate <NUM>, followed by etching the plurality of semiconductor layers. this case, etching of the plurality of semiconductor layers may include two processes. That is, etching of the plurality of semiconductor layers may include divisional etching to divide the plurality of semiconductor layers into a plurality of light emitting structures <NUM> through etching, and mesa etching for exposing the first conductive type semiconductor layer.

Divisional etching means a process of etching all of the plurality of semiconductor layers to divide the plurality of semiconductor layers into the plurality of light emitting structures <NUM>. In addition, mesa etching means a process of partially etching the second conductive type semiconductor layer <NUM> and the active layer <NUM> to expose the first conductive type semiconductor layer <NUM>. Here, divisional etching may be performed prior to mesa etching, or vice versa.

In divisional etching of the semiconductor layers, the regions of the semiconductor layers corresponding to the dividing grooves <NUM> are etched.

On the other hand, the transparent electrode layer <NUM> may be formed on the second conductive type semiconductor layer <NUM> after divisional etching and mesa etching. Alternatively, the transparent electrode layer <NUM> may be formed on the second conductive type semiconductor layer <NUM> before divisional etching and mesa etching, followed by etching together with the second conductive type semiconductor layer <NUM> upon divisional etching and mesa etching.

Referring to <FIG> , after the etching process to form the light emitting structures <NUM>, a passivation layer <NUM> is formed to protect the light emitting structure <NUM>.

The passivation layer <NUM> may be formed of an insulation material including silicon nitride or silicon oxide.

The passivation layer <NUM> may include a first opening <NUM> and a second opening <NUM> which partially expose the first conductive type semiconductor layer <NUM> and the transparent electrode layer <NUM> of the light emitting structure <NUM>, respectively.

Next, a first pad <NUM> and a second pad <NUM> are formed on the passivation layer <NUM> to be connected to the first conductive type semiconductor layer <NUM>.

The first pad <NUM> and the second pad <NUM> may be formed by forming a pad material on the passivation layer <NUM>, followed by patterning the pad material.

On the other hand, an anti-reflective layer <NUM> may be formed on the other surface of the substrate <NUM>. In this embodiment, the anti-reflective layer <NUM> is formed on the other surface of the substrate <NUM> after the dividing grooves <NUM> are formed thereon. However, it should be understood that the anti-reflective layer <NUM> may be formed at any time after the ground texture <NUM> is formed. That is, the anti-reflective layer <NUM> may be formed at any time after forming the ground texture <NUM> described with reference to <FIG> and before forming a first bump <NUM> and a second bump <NUM> shown in <FIG>.

In the method for manufacturing the light emitting device according to the embodiment of the invention, the other surface of the substrate <NUM> is subjected to treatment with phosphoric acid or a mixture of sulfuric acid and phosphoric acid to form the ground texture <NUM>, followed by etching the plurality of semiconductor layers to form the light emitting structure <NUM>. Alternatively, however, the light emitting structure <NUM> may be first formed by etching the plurality of semiconductor layers, and then, the ground texture <NUM> may be formed on the other surface of the substrate <NUM> through treatment of the other surface of the substrate <NUM> with phosphoric acid or a mixture of sulfuric acid and phosphoric acid.

Referring to <FIG> , after forming the first pad <NUM> and the second pad <NUM>, a bump forming process to form a first bump <NUM> and a second bump <NUM> on the first pad <NUM> and the second pad <NUM>, respectively, and a substrate dividing process to divide the substrate <NUM> are performed.

The bump forming process may be performed prior to the substrate dividing process, or vice versa.

The substrate <NUM> may be divided by scribing on the dividing grooves <NUM> using a diamond wheel or a laser.

Referring to <FIG> , a sub-mount <NUM> having a first electrode <NUM> and a second electrode <NUM> on one surface thereof is prepared.

Thereafter, after the sub-mount <NUM> is aligned with the substrate <NUM> such that the first bump <NUM> faces the first electrode <NUM> and the second bump <NUM> faces the second electrode <NUM>, the first bump <NUM> and the second bump <NUM> are bonded to the first electrode <NUM> and the second electrode <NUM>, respectively. As a result, a plurality of flip chip-bonded light emitting devices <NUM> is provided.

Claim 1:
A light emitting diode comprising:
a light emitting structure comprising a first conductivity type semiconductor layer (<NUM>), an active layer (<NUM>) and a second conductivity type semiconductor layer (<NUM>);
mesa-etched areas (<NUM>) formed from the surface of the second conductivity type semiconductor layer (<NUM>) to the first conductivity type semiconductor layer (<NUM>);
a reflective electrode (<NUM>) formed on the second conductivity type semiconductor layer (<NUM>);
a lower insulation layer (<NUM>) covering an overall surface of the structure formed by the first conductivity type semiconductor layer (<NUM>), the active layer (<NUM>), the second conductivity type semiconductor layer (<NUM>), the mesa-etched areas (<NUM>) and the reflective electrode (<NUM>), with the lower insulation layer (<NUM>) allowing an upper surface of the reflective electrode (<NUM>) to be partially exposed therethrough and further allowing the surface of the first conductivity type semiconductor layer (<NUM>) to be exposed therethrough in the mesa-etched areas (<NUM>);
a current spreading layer (<NUM>) formed on the lower insulation layer (<NUM>) covering the first conductivity type semiconductor layer (<NUM>) and being electrically connected to the first conductivity type semiconductor layer (<NUM>);
an upper insulation layer (<NUM>) formed on the current spreading layer (<NUM>) being partially exposed through an opening in the upper insulation layer (<NUM>);
a second pad (<NUM>) electrically connected to the reflective electrode (<NUM>) exposed through the upper insulation layer (<NUM>), characterized in that a first pad (<NUM>) is electrically connected to the current spreading layer (<NUM>) on the upper surface of a mesa M through the opening.