Patent Description:
Vertical junction field-effect transistors (JFETs) made from materials such as silicon carbide (SiC) and gallium nitride (GaN) are useful in power electronic circuits, such as power factor correction (PFC) devices, DC-DC converters, DC-AC inverters, and motor drives. Vertical JFET devices may include active cell regions and termination regions. <CIT> discloses a trench JFET that is created by etching trenches into the topside of a substrate of a first doping to to form mesas. The substrate is made up of a backside drain layer, a middle drift layer and topside source layer. The etching goes through the source layer and partly into the drift later. Gate regions are formed on the sides and bottoms of the trenches using doping of the second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first type. <CIT> discloses a JFET provided with a gate region of a second conductivity type provided on a surface of a semiconductor substrate, a source region of a first conductivity type, a channel region of the first conductivity type that adjoins the source region, a confining region of the second conductivity type that adjoins the gate region and confines the channel region, a drain region of the first conductivity type provided on a reverse face, and a drift region of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain. A concentration of an impurity of the first conductivity type in the drift region and the channel region is lower than a concentration of an impurity of the first conductivity type in the source region and the drain region and a concentration of an impurity of the second conductivity type in the confining region. <CIT> discloses a junction FET of a normally-off type. In particular, in a junction FET using silicon carbide as a substrate material, impurities are doped to a vicinity of a p-n junction between a gate region and a channel-formed region, the impurities having a conductive type which is reverse to that of impurities doped in the gate region and same as that of impurities doped in the channel-formed region. In this manner, an impurity profile of the p-n junction becomes abrupt, and further, an impurity concentration of a junction region forming the p-n junction with the gate region in the channel-formed region is higher than those of a center region in the channel-formed region and of an epitaxial layer.

Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type. The substrate is made up of a backside drain layer, a middle drift layer, and topside source layer. Mesas result between the trenches. The etching goes through the source layer and may extend partly into the drift layer. Gate regions are formed on the sides and bottoms of the trenches using doping of a second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first kind, providing improved threshold voltage control. Optionally the substrate may include a lightly doped channel layer between the drift and source layers, such that the mesas include a lightly doped channel region that more strongly contrasts with the implanted vertical channel reg10ns. The substrate may be made from SiC, GaN, and/or other semiconductor materials.

Furthermore, the claimed subject matter is not limited to limitations that solve any or all disadvantages noted in any part of this disclosure.

The summary, as well as the following detailed description, is further understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings exemplary embodiments of the invention; however, the invention is not limited to the specific methods, compositions, and devices disclosed.

The present invention may be understood more readily by reference to the following detailed description taken in connection with the accompanying figures and examples, which form a part of this disclosure. It is to be understood that this invention is not limited to the specific devices, methods, applications, conditions or parameters described and/or shown herein, and that the terminology used herein is for the purpose of describing particular embodiments by way of example only and is not intended to be limiting of the claimed invention. Also, as used in the specification including the appended claims, the singular forms "a," "an," and "the" include the plural, and reference to a particular numerical value includes at least that particular value, unless the context clearly dictates otherwise. The term "plurality", as used herein, means more than one. When a range of values is expressed, another embodiment includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another embodiment. All ranges are inclusive and combinable.

It is to be appreciated that certain features of the invention which are, for clarity, described herein in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Further, reference to values stated in ranges include each and every value within that range.

Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type. The substrate is made up of a backside drain layer, a middle drift layer, and topside source layer. Mesas result between the trenches. The etching goes through the source layer and may extend partly into the drift layer. Gate regions are formed on the sides and bottoms of the trenches using doping of a second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first kind, providing improved threshold voltage control. Optionally, the substrate may include a lightly doped channel layer between the drift and source layers, such that the mesas include a lightly doped channel region that more strongly contrasts with the implanted vertical channel regions. The substrate may be made from SiC, GaN, and/or other semiconductor materials.

<FIG> is a vertical cross-sectional view of an exemplary prior art trench JFET. Such devices commonly comprise a multiple epitaxial layer structure including a substrate <NUM>, and a drift layer <NUM> doped with a first kind of doping (n or p) to withstand the desired blocking voltage. Atop the drift layer is a channel layer <NUM>, which is usually more heavily doped with the first kind of doping than the drift layer. The topmost layer <NUM> is the heavily doped source region of the first kind of doping. Trenches are etched through the source <NUM> and into, but not all the way through, the channel layer <NUM>. The bottom and sidewalls of these trenches are implanted using vertical and angled implants <NUM> respectively to form the gate region <NUM>. The gate doping type is opposite the doping type of the source, channel, drift and substrate regions. In practice, contacts (not shown) include source contacts made to the source region <NUM>, a drain contact made to the bottom of the substrate region <NUM>, and gate contact is made to the gate region <NUM>.

The threshold voltage of such a JFET is set by the voltage difference that needs to be applied between the gate and source in order to deplete the channel region lying between the gate regions <NUM>. It therefore depends critically on the doping of the channel layer <NUM> and the width of the etched trenches, which in turn determines the spacing between the gate regions <NUM>. In practice, these factors lead to a large variation in the charge resident between adjacent gate regions <NUM>, which is the product of the doping level, and the space between regions <NUM>. In turn, this leads to large variations in device threshold voltage. This is due in part to the fact that the doping level may fluctuate a great deal due to the limited level of control possible with epitaxial layer growth. +/- <NUM>% to <NUM>% variation is common. The space between the gate regions <NUM> also fluctuates due to photolithography and etch profile variations of the mesas between trenches. Such fluctuation can be several <NUM> without use of sophisticated equipment.

<FIG> is a vertical cross-sectional view of an exemplary trench JFET with an angle-implanted vertical channel region. Since the device threshold voltage is determined by the charge resident between the gate regions <NUM>, this structure is devised to precisely control this charge. This is achieved by changing the epitaxial structure and using an angled implant to dope the channel. Like the device depicted in <FIG>, the JFET of <FIG> has a drift region <NUM> atop a substrate <NUM>. Rising from the drift region <NUM> are active cell mesas. Atop the mesas is source layer <NUM>. The substrate <NUM>, the drift <NUM>, and the source <NUM> are doped with a doping of a first kind. In <FIG>, these regions and channel regions are depicted with a first kind of doping being n-type, and a second doping kind for the gate regions is shown as being p-type, such that the structures form NPN devices. In practice, the doping types can be switched to use the same structures to form PNP devices.

In <FIG>, the trenches are depicted as being etched through the source layer <NUM> and all the way through a lightly doped channel core layer <NUM> into the drift layer <NUM>. Therefore, compared to the channel layer <NUM> of <FIG>, the channel core layer <NUM> of <FIG> is shallower than the trench. The channel core layer <NUM> is as lightly doped as possible to minimize its charge. The channel core layer <NUM> is doped with the first doping type. For a 1200V SiC JFET, for example, it may be possible to use a drift layer doping of lel6 cm-<NUM> along with a channel core layer doping of lel5 cm-<NUM>.

The bottom and sidewalls of the trenches are implanted using vertical and angled implants <NUM> to form the gate regions <NUM>. The gate doping type is of a second type (p or n) which is opposite the doping type of the source, channel, drift and substrate regions.

Vertical channel regions <NUM> may then be angle implanted along the directions <NUM>. The vertical channel doping type is of the first doping type, i.e., the same doping type as the source and the opposite of the doping type of the gate. This implantation may be done at a high energy to achieve a deeper implant than the gate sidewall implant. Hence the vertical channel regions <NUM> may be formed after forming the gate regions <NUM>.

In practice, contacts (not shown) include a source contact made to the source region <NUM>, a drain contact made to the bottom of the substrate region <NUM>, and a gate contact made to the gate regions <NUM>.

The charge between the gate regions <NUM> is controlled by the charge pockets <NUM> which determine the device threshold voltage. The background charge contribution of the region <NUM> is minimized by its light doping level, and so does not significantly impact threshold. As an example, the charge contribution of the channel core region <NUM> between the gate regions <NUM> can be made to be less than <NUM>% of the charge resident in the pockets <NUM>. In such a case, if there is a variation in the doping level of region <NUM> on the order of <NUM>%, that variation will therefore have less than a <NUM>% impact in the total charge between the gate regions <NUM>, and so will not cause any significant threshold variation. Similarly, if the photolithographic and etch processes used to form the trenches lead to significant variations in the mesa width between the gate regions <NUM>, this will lead to a variation only in the charge contributed by layer <NUM>. Again, this effect can be made very small. Since the depths of the gate regions <NUM> and implanted channel pockets <NUM> with respect to the trench sidewalls are accurately determined by implant angle and energy, which can be controlled to better than <NUM>% accuracy, the charge between the gate regions <NUM> is substantially invariant even if mesa width (i.e., the width between the trench regions) changes. By these means, the effect of both the epitaxial layer doping variations and mesa width variations resulting from photolithographic and etch process variations is essentially negated.

For example, to create a 1200V SiC JFET, a drift layer doping of 1e16 cm-<NUM> may be used, along with a channel core layer doping at 1e15 cm-<NUM>, and a source region doping at 2e19 cm-<NUM> in doping. If the mesa is <NUM> wide, the channel layer charge is: <MAT>.

The vertical channel implant charge pocket depends on the desired threshold. Typical numbers may be a doping of 1e17 cm-<NUM>, for each of two regions <NUM> in width. With one of these charge pockets on each side, the total charge in the pockets is: <MAT>.

In other words, there will be forty times more charge in the implanted channel regions than in the channel core layer. Hence, the implanted charge dominates the voltage threshold effect.

<FIG> and <FIG> are vertical cross-sectional views of the trench JFET of <FIG> at different points during its manufacture. In <FIG>, a gate implant <NUM> is applied after the trenches are etched through a lightly doped channel layer <NUM>. The implantation is done with a hard masking layer <NUM> in place. The hard masking layer <NUM> may comprise oxide, metal, or both. This hard masking layer <NUM> is also used, as it is in a standard vertical JFET process, to prevent the gate implant from counter doping the source regions <NUM>, since the gate implant dopant is of opposite polarity to the source. The gate implant <NUM> includes implantation at an angle α. Angle α is selected based on the worst case assessment of: trench depth, hard masking layer <NUM> thickness, and trench width. This is to ensure the angled implant beam is not shadowed by adjacent mesas. Implant energy and charge are set to ensure there is sufficient charge to supply the gate side of the depletion region to support a gate-source breakdown well above the maximum gate-source voltage rating of the device. The gate dopant <NUM> at the bottom may be disposed deeper and doped to a higher level than the sidewalls, e.g., by including a vertical or less steep implantation in gate implant <NUM>. A higher dopant level at the bottom of the trenches is helpful since this is the place where the gate contact is usually made.

In <FIG>, the hard masking layer <NUM> is removed, and then the channel implant <NUM> is performed at an angle β. In practice, the channel implant <NUM> can be performed with the hard masking <NUM> in place. However, first removing the hard masking layer <NUM> allows the channel implant <NUM> to be applied at a larger angle β. This in turn makes it easier to dispose the charge pockets <NUM> deeper than the gate without resorting to very high implantation energies.

Not shown in <FIG>, during the channel implant, the edge areas of the device, e.g., termination regions, may need to be shielded from the channel implant <NUM>, so that it does not affect any region other than the active JFET cells where the current conduction in the on-state is to occur.

The structure of <FIG> shows that the desired depth of the channel implant along the sidewall is close to the depth of the gate regions. In practice it may be slightly shallower or deeper. If it is too shallow, it will lead to higher on-resistance but better off-state blocking, while being deeper will do the opposite. It is also allowable to make this channel implant so deep that it wraps around the gate regions <NUM> both along the sides and the bottoms. The drop in blocking capability must then be compensated by reducing the drift region <NUM> doping, so that the target breakdown rating can still be met.

It is typically (but not always) preferred to modify the channel layer <NUM> to be as lightly doped as possible, and decrease its depth, so that the trenches will be etched all the way through it, accounting for normal process variations of epitaxial thickness and trench etch depth control. At higher blocking voltages (e.g. greater than 3300V for <NUM>-SiC) the drift region doping is light enough that the channel layer <NUM> doping may be made the same as the drift layer doping.

<FIG> shows the outcome of the precision of threshold voltage control with fluctuations in implant, epitaxial growth and mesa width parameters. The lines show the sensitivity to mesa width variations with all other parameters held constant. The shaded regions surrounding the lines indicate the additional fluctuation that results from epitaxial layer doping and implant control variations.

The geometries of the trench JFETS described herein may vary considerably. For example in <FIG>, <FIG>, and <FIG>, the typical vertical thickness of source regions <NUM> may between <NUM> and <NUM>, and the depth of the trench beyond source regions <NUM> may be in the range of <NUM> to <NUM>. The width of the mesas and trenches may generally be between <NUM>. 3and <NUM>, for example. The p+ gate region <NUM> that extends below the trench bottom may extend from <NUM> to <NUM>, generally. The channel implant regions <NUM> may extend beyond the p+ gate regions <NUM> by, for example, <NUM> to <NUM>. Other geometries are possible, of course, depending on desired operating characteristics.

The geometry and doping of the n- region <NUM> at the core of the mesa affects operations of trench JFETs such as those shown in <FIG>, <FIG>, and <FIG>. To optimize control of the threshold voltage, the doping level of region <NUM> should be much lower than that of the drift region <NUM> and of the implanted channel regions <NUM>. For example, the doping level of region <NUM> may be at least 10X lower than that of the drift region <NUM> and <NUM> to 100X lower than the peak concentration in the implanted channels <NUM>. For example, for a <NUM> V normally-on device, the drift region <NUM> may be doped in the range of 2e16 to 3e16 cm-<NUM>, and the n- region <NUM> may be doped at 1e15cm-<NUM>, while the peak concentration in the implanted channel regions <NUM> may be between 4e17 and 4e18 cm-<NUM>. Due to the very low level of the doping in region <NUM>, variations in mesa width have almost no effect on the net N-charge in the Mesa regions, and this in turn makes the threshold voltage (Vth) invariant to such process variations.

In the formation of a normally-on JFET, the channel peak concentration may be quite high, e.g., 4e17 to 4e18 cm-<NUM>. Since it may require a gate-source Vgs = -15V to -20V to fully turn-off such a device, it may be necessary to have a gate-source breakdown voltage, e.g., of at least <NUM>-40V, so that such a reverse bias can in fact be applied with low leakage current. For this reason, the P-gate sidewall concentration may be reduced, and the peak of the channel implant <NUM> may be spaced away from the junction, deeper into the mesa region. This in turn creates a graded junction with higher breakdown voltage. In fact, in this device, even the source region <NUM> is doped such that the lower portion near the junction with the p-gate forms a similarly graded junction.

<FIG> shows an example doping profile along section B-B' of <FIG>. In the p-gate region between points B and <NUM> on the graph, corresponding to the portion of section line B-B' within region <NUM> of <FIG>, the impurity concentration may be, for example, between 2el8 and <NUM> el8 cm-<NUM>. Entering the implanted channel region <NUM> of <FIG>, corresponding to region between point <NUM> to <NUM> on <FIG>, the concentration dips, and at point <NUM> changes over to n-type, then rises to a peak at point <NUM>, before dipping again to the lower value found at the core of the mesa at point B', corresponding to the region <NUM> of <FIG>. The peak n-type concentration in channel <NUM> at point <NUM> is <NUM> to <NUM> times greater than that at point B', thus ensuring that the doping of the implanted channel <NUM> dominates the threshold voltage determination for the vertical JFET <NUM>.

For optimum performance, the n- region <NUM> is kept shallower than the channel implant region <NUM>. If the region <NUM> is defined by epi growth, while the depth of the channel implant <NUM> is determined by the implant conditions as well as trench depth, some process tolerance should be part of the design of the trench JFET. According to the invention, the regions <NUM> is between <NUM> to <NUM> shallower than the bottom the implanted region <NUM>.

<FIG> illustrates a trench JFET where the implanted channel regions <NUM> do not extend far enough for optimal performance. As in <FIG>, the trench JFET <NUM> of <FIG> has a substrate <NUM> and a drift region <NUM> of a first doping type. Atop the mesas are source regions <NUM> of the first doping type. On the sides of the mesas and bottoms of the trenches is a gate material <NUM> that is of a second doping type. Within the mesas adjacent to the gate material <NUM> are implanted channel regions <NUM> of the first doping type, and at the core of the mesas are lightly doped regions <NUM>. In this example, there are regions <NUM> within the mesa beneath the implanted channel regions <NUM>. This may lead to a second JFET region formed in regions <NUM> between the gate regions <NUM>. In a normally-on JFET, since the region <NUM> shares the same doping as region <NUM> based, which may be selected for a target Vds breakdown voltage of> <NUM> V, the JFET may pinch off at a much lower voltage than the target set by the channel implanted portion <NUM>. For example, in a <NUM> V normally-on JFET, if the epi doping is 8el5cm-<NUM> in regions <NUM> and <NUM>, while the channel <NUM> peak doping is lel8cm-<NUM> for a target Vth of -<NUM> to - 8V, the lower region <NUM> may have a Vth of -<NUM> to -4V, which is far from the desired value. That may also lead to a much higher on- resistance and lower saturation current.

To address prevent such problems, in embodiments not forming part of the claimed invention, the channel implants <NUM> may be are arranged, e.g., by using both angled and vertical implants of specific energies, to ensure that the n-implant wraps around the portions of p-gate region <NUM> at the bottoms of the mesas. This ensures that the Vth at the bottom of the channel is more negative than the upper part of the channel <NUM> in the vicinity of mesa core region <NUM>, and does not control the device Vth. This minimizes variations in device Vth, on-resistance and saturation current.

The precise doping levels can be adjusted in accordance with particular design goals such as, for example, standoff and/or threshold voltages. In general, the backside drain region is more heavily doped than the drift region. This is done to facilitate backside ohmic contact or ohmic region formation. Similarly the source regions are heavily doped, relative to the drift region, also for the purpose of creating contacts or contact regions. The gate regions are also heavily doped, but with a doping type opposite of that of the drain, drift and source regions. The channel core regions at the middle of the mesas may be more lightly doped than the drift region.

The concepts herein may be embodied in methods of fabricating trench JFETs from a substrate of a first doping type, where, for example, the substrate comprises: a heavily doped backside drain region; a center medium doped drift region; and a topside heavily doped source region. The methods, which do not form part of the claimed invention, may include: etching trenches into the substrate from the topside to form mesas comprising drift region material and source region material; implanting dopant of a second doping type on the bottoms and sides of the trenches to form gate regions; implanting dopant of the first doping past the gate regions on the sides of the trenches and into the mesas. The substrate may comprise silicon carbide, gallium nitride, and/or other semiconductor materials. Methods may further include the use of a substrate that further comprises, between the drift region and the source region, a lightly doped channel region. In such case, the processes may further include, when etching trenches into the substrate from the topside, etching through both the source region and the channel region, such that the mesas further comprise a section of channel region material between drift region material and the source region material. The implanting of dopant of the first kind may be designed to create vertical angle implant doped channel regions that are doped several times higher, e.g., five or ten times higher, or more, than is the drift region.

Claim 1:
A trench JFET, comprising:
a substrate (<NUM>) comprising a backside drain region and a topside drift region (<NUM>), the backside drain region and the topside drift region being of a first doping type;
active cell mesas extending from the topside drift region, wherein the active cell mesas are separated by trenches cut into the topside drift region;
source regions (<NUM>) at the tops of the mesas, the source regions being of the first doping type;
gate regions (<NUM>) on the surfaces of the trenches, the gate regions being of a second doping type, the second doping type being the opposite of the first doping type;
vertical channel regions (<NUM>, <NUM>), the vertical channel regions extending substantially the height of the mesas and being of the first doping type; and
mesa core regions (<NUM>), the mesa core regions being of the first doping type and extending from the centers of the mesas, wherein the doping concentration at the center of the mesa core regions is at least ten times lower than that of the topside drift region;
wherein:
the vertical channel regions (<NUM>, <NUM>) extend laterally between the portion of the gate regions on the vertical walls of the trenches and the mesa core regions,
the mesa core regions (<NUM>) are between <NUM> to <NUM> shallower than the bottom of the vertical channel regions (<NUM>, <NUM>), and
the peak doping concentration of the vertical channel regions (<NUM>, <NUM>) is at least ten times higher than the doping level of the centers of the mesa core regions.