Patent Description:
Laterally diffused MOSFETs (LDMOSFETs) are widely used in power management integrated circuits, owing to their high breakdown voltage and their compatibility with standard complementary metal-oxide-semiconductor (CMOS) processes.

LDMOSFET transistors particularly suffer from hot-carrier degradation caused by larger electric fields leading to the generation of interface traps in the Si/SiO<NUM> interface within the drift region, which in turn causes the degradation of the electrical parameters (e.g., saturation-region drain current (Idsat), linear-region drain current (Idlin) and drain-source on-state resistance (Rds-on)) limiting the device lifetime. <CIT> describes a MOS electronic device including: a drain region; a field insulating layer, covering the drain region; an opening in the field insulating layer delimiting an active area; a body region housed in the active area; a source region housed in the body region. A portion of the body region comprised between the drain region and the source region forms a channel region. A polycrystalline silicon structure extends along the edge of the opening delimiting the active area, partially on top of the field insulating layer and partially on top of the active layer. The polycrystalline silicon structure comprises a gate region extending along a first portion of the edge on top of the channel region and partially surrounding the source region and a non-operative region extending along a second portion of the edge, electrically insulated and at a distance from the gate region, so as to reduce the drain/gate capacity and to increase the cutoff frequency of the MOS device. In "<NPL>, the electrostatic discharge (ESD) robustness of n-channel LDMOS devices is addressed. <CIT> describes a device including a semiconductor substrate including a surface, a drain region in the semiconductor substrate having a first conductivity type, a well region in the semiconductor substrate on which the drain region is disposed, the well region having the first conductivity type, a buried isolation layer in the semiconductor substrate extending across the well region, the buried isolation layer having the first conductivity type, a reduced surface field (RESURF) region disposed between the well region and the buried isolation layer, the RESURF region having a second conductivity type, and a plug region in the semiconductor substrate extending from the surface of the substrate to the RESURF region, the plug region having the second conductivity type. <CIT> describes a method for forming an extended drain metal-oxide-semiconductor transistor. In "<NPL>, approaches to enhance the IO overdrive circuit (IP) reliability are investigated. An LDMOS with good reliability is provided. The reverse body bias effect is used to reduce HCI damage on IP level, which can be achieved by implementing deep N-well. <CIT> describes a semiconductor device having a first region with a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region. <CIT> describes a semiconductor device including a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a high-voltage doped region having the first conductivity type and disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart from the high-voltage doped region, a source region disposed in the high-voltage doped region, a first gate structure disposed above a first side portion of the high-voltage doped region between the source region and the drain region, and a second gate structure disposed above a second and opposite side portion of the high-voltage doped region. <CIT> describes a semiconductor device, which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity.

The invention is defined by the independent claim. Advantageous embodiments of the invention are given in the dependent claims.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:.

Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and/or after a disclosed method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.

<FIG> shows a semiconductor device structure 10A according to an embodiment of the invention. AP-type well region <NUM> and an N-type well region <NUM> are formed over a semiconductor substrate <NUM>. In some embodiments, the semiconductor substrate <NUM> is a Si substrate. In some embodiments, the material of the semiconductor substrate <NUM> is selected from a group consisting of bulk-Si, SiP, SiGe, SiC, SiPC, Ge, SOI-Si, SOI-SiGe, III-VI material, and a combination thereof. In some embodiments, a deep N-type well (not shown) is formed over the semiconductor substrate <NUM>, and the P-type well region <NUM> and the N-type well region <NUM> are formed over the deep N-type well. A well region <NUM> is formed over the semiconductor substrate <NUM> and between the P-type well region <NUM> and the N-type well region <NUM>. In some embodiments, the well region <NUM> is no dopant, i.e. the well region <NUM> is not a P-type well region or an N-type well region. In some embodiments, the semiconductor device structure 10A includes a laterally diffused metal oxide semiconductor (LDMOS) transistor.

The shallow trench isolation (STI) regions 140a and 140b are formed in the P-type well region <NUM>. A P-type doping region 130a is formed in the P-type well region <NUM> and between the STI regions 140a and 140b. The STI regions 140c and 140d are formed in the N-type well region <NUM>. The P-type doping region 130c is formed in the N-type well region <NUM> and between the STI regions 140c and 140d. The P-type doping region 130b is formed in the N-type well region <NUM> and adjacent to the STI region 140c. Furthermore, the P-type doping region 130b further includes a lightly doped region 132b. It should be noted that the size of the P-type doping region 130a is greater than that of the P-type doping regions 130b and 130c.

A gate structure 160A is formed in the semiconductor device structure 10A. The gate structure 160A includes a gate electrode <NUM>, a gate dielectric <NUM> under the gate electrode <NUM>, and the spacers <NUM> formed on opposite sides of the gate electrode <NUM>. The spacers <NUM> may be formed by a single layer or multiple layers. In some embodiments, one or more work-function layers (not shown) are formed between the gate dielectric <NUM> and the gate electrode <NUM>. The gate dielectric <NUM> is disposed on the well region <NUM> and partially over the P-type well region <NUM> and the N-type well region <NUM>. The space <NUM> formed on the left side of the gate electrode <NUM> is disposed over the lightly doped region 132b, and the space <NUM> formed on the right side of the gate electrode <NUM> is disposed over the STI region 140b. A resist protective oxide (RPO) <NUM> is formed over a portion of the gate structure 160A, the STI region 140b and a portion of the P-type doping region 130a.

The gate dielectric <NUM> may include a silicon dioxide (referred to as silicon oxide) layer. The gate dielectric <NUM> may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxide, other suitable processes, or combinations thereof. Furthermore, the core oxide is used for healing gate application, so as to gain better gate control ability.

The gate electrode <NUM> is configured to be coupled to metal interconnects. The gate electrode <NUM> may include a doped or non-doped polycrystalline silicon (or polysilicon). Alternatively, the gate electrode <NUM> may include a metal such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof. The gate electrode <NUM> may be formed by CVD, PVD, ALD, plating, and other proper processes. The gate electrode <NUM> may have a multilayer structure and may be formed in a multiple-step process.

In the semiconductor device structure 10A, a P-type transistor including the gate structure 160A is formed. In some embodiments, the P-type transistor is a P-type LDMOS transistor. The P-type doping region 130a forms the drain region of the P-type transistor, and the P-type doping region 130b forms the source region of the P-type transistor. The gate structure 160A is separated from the drain region of the P-type transistor by the STI region 140b. The channel region of the P-type transistor is formed between the P-type doping region 130b and the well region <NUM> and under the gate dielectric <NUM>. Furthermore, the P-type doping region 130c forms the bulk region of the P-type transistor. In some embodiments, the bulk region of the P-type transistor is formed by an N-type doping region.

The P-type transistor further includes a gate structure 165A. The gate structure 165A is an additional healing gate for the PMOS transistor, and the gate structure 165A includes a gate electrode <NUM>, a gate dielectric <NUM> under the gate electrode <NUM>, and the spacers <NUM> formed on opposite sides of the gate electrode <NUM>. The spacers <NUM> may be formed by a single layer or multiple layers. In some embodiments, one or more work-function layers (not shown) are formed between the gate dielectric <NUM> and the gate electrode <NUM>. The gate dielectric <NUM> is disposed on the N-type well region <NUM>. As described above, the gate electrode <NUM> is configured to be coupled to interconnects. The space <NUM> formed on the left side of the gate electrode <NUM> is disposed over the P-type doping region 130e, and the space <NUM> formed on the right side of the gate electrode <NUM> is disposed over the P-type doping region 130d. Furthermore, no interconnect is coupled to the P-type doping regions 130d and 130e. It should be noted that no channel region is formed under the gate structure 165A. In some embodiments, only the gate structure 165A is formed in the semiconductor device structure 10A without the P-type doping regions 130d and 130e. It should be noted that the gate length L1 of the gate structure 160A is greater than the gate length L2 of the gate structure 165A.

<FIG> shows a healing mechanism in the semiconductor device structure 10A of <FIG> according to an embodiment of the invention. During hot-carrier instability (HCI) stress, vertical and horizontal electrical fields <NUM> will accelerate hot hole/electron to break Si-H bonds. The dangling bonds become charged to cause mobility degradation, threshold voltage shift, and channel current degradation. By using the healing gate (i.e. the gate structure 165A), the healing field <NUM> which reverse to the stress field <NUM> during the HCI stress suppresses impact ionization and also de-traps the HCI-induced trapped charge in the gate dielectric <NUM>. By applying the healing field <NUM>, stability against HCI is improved for higher voltage application without enlarging channel length.

<FIG> shows a semiconductor device structure 10B according to an embodiment of the invention. The P-type well region <NUM> and the N-type well region <NUM> are formed over a semiconductor substrate <NUM>. In some embodiments, a deep N-type well (not shown) is formed over the semiconductor substrate <NUM>, and the P-type well region <NUM> and the N-type well region <NUM> are formed over the deep N-type well. A well region <NUM> is formed over the semiconductor substrate <NUM> and between the P-type well region <NUM> and the N-type well region <NUM>. In some embodiments, the well region <NUM> is no dopant, i.e. the well region <NUM> is not a P-type well region or an N-type well region. In some embodiments, the semiconductor device structure 10B includes a LDMOS transistor.

The STI regions 140e and 140f are formed in the N-type well region <NUM>. An N-type doping region 135a is formed in the N-type well region <NUM> and between the STI regions 140e and 140f. The STI regions <NUM> and <NUM> are formed in the P-type well region <NUM>. The N-type doping region 135c is formed in the P-type well region <NUM> and between the STI regions <NUM> and <NUM>, and the N-type doping region 135b is formed in the P-type well region <NUM> and adjacent to the STI region <NUM>. Furthermore, the N-type doping region 135b further includes a lightly doped region 137b. It should be noted that the size of the N-type doping region 135a is greater than that of the N-type doping regions 135b and 135c.

A gate structure 160B is formed in the semiconductor device structure 10B. The gate structure 160B includes a gate electrode <NUM>, a gate dielectric <NUM> under the gate electrode <NUM>, and the spacers <NUM> formed on opposite sides of the gate electrode <NUM>. The spacers <NUM> may be formed by a single layer or multiple layers. In some embodiments, one or more work-function layers (not shown) are formed between the gate dielectric <NUM> and the gate electrode <NUM>. The gate dielectric <NUM> is disposed on the well region <NUM> and partially over the P-type well region <NUM> and the N-type well region <NUM>. The space <NUM> formed on the left side of the gate electrode <NUM> is disposed over the lightly doped region 137b, and the space <NUM> formed on the right side of the gate electrode <NUM> is disposed over the STI region 140f. A resist protective oxide (RPO) <NUM> is formed over a portion of the gate structure 160B, the STI region 140f and a portion of the N-type doping region 135a.

In the semiconductor device structure 10B, an N-type transistor including the gate structure 160B is formed. In some embodiments, the N-type transistor is an N-type LDMOS transistor. The N-type doping region 135a forms the drain region of the N-type transistor, and the N-type doping region 135b forms the source region of the N-type transistor. The channel region of the N-type transistor is formed between the N-type doping region 135b and the well region <NUM> and under the gate dielectric <NUM>. Furthermore, the N-type doping region 135c forms the bulk region of the N-type transistor. In some embodiments, the bulk region of the N-type transistor is formed by a P-type doping region.

The N-type transistor further includes a gate structure 165B. The gate structure 165B is an additional healing gate for the N-type transistor, and the gate structure 165B includes a gate electrode <NUM>, a gate dielectric <NUM> under the gate electrode <NUM>, and the spaces <NUM> formed on opposite sides of the gate electrode <NUM>. The spacers <NUM> may be formed by a single layer or multiple layers. In some embodiments, one or more work-function layers (not shown) are formed between the gate dielectric <NUM> and the gate electrode <NUM>. The gate dielectric <NUM> is disposed on the P-type well region <NUM>. As described above, the gate electrode <NUM> is configured to be coupled to interconnects. The space <NUM> formed on the left side of the gate electrode <NUM> is disposed over the N-type doping region 135e, and the space <NUM> formed on the right side of the gate electrode <NUM> is disposed over the N-type doping region 135d. Furthermore, no interconnect is coupled to the N-type doping regions 135d and 135e. It should be noted that no channel region is formed under the gate structure 165B. In some embodiments, only the gate structure 165B is formed in the semiconductor device structure 10B without the P-type doping regions 135d and 135e.

Referring to <FIG> and <FIG> together, the configuration of the semiconductor device structure 10A of <FIG> is similar to the configuration of the semiconductor device structure 10B of <FIG>. The difference between the semiconductor device structure 10A including the P-type transistor and the semiconductor device structure 10B including the N-type transistor is that the well regions and the doping regions in the semiconductor device structures 10A and 10B have different type (e.g., opposite type) of conductivity.

<FIG> shows a semiconductor device structure 10C according to an embodiment of the invention. The semiconductor device structure 10C includes a P-type transistor with the gate structures 160C and 165C. The configuration of the semiconductor device structure 10C of <FIG> is similar to the configuration of the semiconductor device structure 10A of <FIG>. The difference between the semiconductor device structure 10C and the semiconductor device structure 10A is that no well region <NUM> is formed between the P-type well region <NUM> and the N-type well region <NUM> in the semiconductor device structure 10C. In other words, the P-type well region <NUM> is in direct contact with the N-type well region <NUM> in the semiconductor device structure 10C. Similarly, by changing the type of conductivity of the well regions and the doping regions in the semiconductor device structure 10C, an N-type transistor is obtained in the semiconductor device structure 10C. In some embodiments, the N-type transistor is an N-type LDMOS transistor.

<FIG> shows a semiconductor device structure 10D according to an embodiment of the invention. The semiconductor device structure 10D includes a P-type transistor with the gate structures 160D and 165D. In some embodiments, the P-type transistor is a P-type LDMOS transistor, The configuration of the semiconductor device structure 10D of <FIG> is similar to the configuration of the semiconductor device structure 10C of <FIG>. The difference between the semiconductor device structure 10D and the semiconductor device transistor structure 10C is that no STI region 140b is formed in the semiconductor device structure 10D, and the P-type doping region 130a extends to the space of the gate structure 160D to formed a P-type doping region 130f in the P-type well region <NUM> of the semiconductor device structure 10D. The P-type doping region 130f is adjacent to the STI region 140a and under a portion of the RPO <NUM>. Furthermore, the P-type doping region 130f further includes a lightly doped region 132f, and the lightly doped region 132f is formed under the right side of the gate electrode <NUM> of the gate structure 160D. Similarly, by changing the type of conductivity of the well regions and the doping regions in the semiconductor device structure 10D, an N-type transistor is obtained in the semiconductor device structure 10D. In some embodiments, the N-type transistor is an N-type LDMOS transistor.

The semiconductor device structures with the healing gate in the embodiments have better ability to protect against HCI degradation in high-voltage applications. <FIG> shows the linear/saturation current (Idlin/Idsat) degradation after the HCI stress as a function of the healing gate voltage according to an embodiment of the invention. In <FIG>, Idsat and Idlin current degradation is efficiently suppressed once a healing bias is applied during the HCI stress. The healing effect is stronger with increasing healing gate voltage and around <NUM>% of HCI degradation can be healed with a healing gate voltage of <NUM>. However, a healing voltage higher than a specific value (e.g., 3V) is avoid to prevent breakdown problems at the healing gate structure.

The substrate current is also monitored with and without healing gate application during the HCI stress. HCI degradation is typically attributed to hot hole/electron injection which induce Si-H bond breaking. Once created, the dangling bond will become charged and consequently induce threshold voltage shift, channel current degradation, and substrate current increase. <FIG> shows the substrate currents with and without healing gate voltage as a function of gate voltage according to an embodiment of the invention. Under the same stress condition, the substrate current is decreased once the healing gate structure is applied. The substrate current is typically attributed to high-energy carriers in the channel causing impact ionization and therefore often correlated with HCI. With increasing healing voltage, Si-H bond breaking is suppressed as well.

<FIG> shows a metal oxide semiconductor (MOS) transistor structure <NUM> according to an example of the present application, not falling under the scope of the claims. The N-type well region <NUM> is formed over the semiconductor substrate <NUM>. In some examples, a deep N-type well (not shown) is formed over the semiconductor substrate <NUM>, and the N-type well region <NUM> is formed over the deep N-type well.

The STI regions 140_1, 140_2 and 140_3 are formed in the N-type well region <NUM>. The P-type doping regions 130_1 and 130_2 are formed in the N-type well region <NUM>. The P-type doping region 130_1 is formed in the N-type well region <NUM> and adjacent to the STI region 140_1, and the P-type doping region 130_1 further includes a lightly doped region 132_1. The P-type doping region 130_2 is formed in the N-type well region <NUM> and adjacent to the STI region 140_2, and the P-type doping region 130_2 further includes a lightly doped region 132_2. It should be noted that the size of the P-type doping region 130_1 is equal to that of the P-type doping region 130_2.

A gate structure 160_1 is formed in the MOS transistor structure <NUM>. The gate structure 160_1 includes a gate electrode <NUM>, a gate dielectric <NUM> under the gate electrode <NUM>, and the spaces <NUM> formed on opposite sides of the gate electrode <NUM>. The spacers <NUM> may be formed by a single layer or multiple layers. In some examples, one or more work-function layers (not shown) are formed between the gate dielectric <NUM> and the gate electrode <NUM>. The gate dielectric <NUM> is disposed on the N-type well region <NUM>. The space <NUM> formed on the left side of the gate electrode <NUM> is disposed over the lightly doped region 132_2, and the space <NUM> formed on the right side of the gate electrode <NUM> is disposed over the lightly doped region 132_1. As described above, the gate electrode <NUM> is configured to be coupled to interconnects.

In the MOS transistor structure <NUM>, a P-type MOS transistor including the gate structure 160_1 is formed. The P-type doping region 130_1 forms the drain region of the P-type MOS transistor, and the P-type doping region 130_2 forms the source region of the P-type MOS transistor. The channel region of the P-type MOS transistor is formed between the P-type doping region 130_1 and the P-type doping region 130_2 and under the gate dielectric <NUM>. Furthermore, an N-type doping region 135_1 forms the bulk region of the P-type MOS transistor.

The P-type MOS transistor further includes a gate structure 165_1. The gate structure 165_1 is an additional healing gate for the P-type MOS transistor, and the gate structure 165_1 includes a gate electrode <NUM>, a gate dielectric <NUM> under the gate electrode <NUM>, and the spaces <NUM> formed on opposite sides of the gate electrode <NUM>. The spacers <NUM> may be formed by a single layer or multiple layers. In some examples, one or more work-function layers (not shown) are formed between the gate dielectric <NUM> and the gate electrode <NUM>. The gate dielectric <NUM> is disposed on the N-type well region <NUM>. As described above, the gate electrode <NUM> is configured to be coupled to interconnects. The space <NUM> formed on the left side of the gate electrode <NUM> is disposed over the P-type doping region 130_4, and the space <NUM> formed on the right side of the gate electrode <NUM> is disposed over the P-type doping region 130_3. Furthermore, no interconnect is coupled to the P-type doping regions 130_3 and 130_4. It should be noted that no channel region is formed under the gate structure 165_1. In some examples, only the gate structure 165_1 is formed in the MOS transistor structure <NUM> without the P-type doping regions 130_3 and 130_4. In some examples, the gate length L3 of the gate structure 160_1 is greater than the gate length L4 of the gate structure 165_1. In some examples, the gate length L3 of the gate structure 160_1 is equal to the gate length L4 of the gate structure 165_1. Similarly, by changing the type of conductivity of the well regions and the doping regions in the MOS transistor structure <NUM>, an N-type MOS transistor is obtained in the MOS transistor structure <NUM>.

According to the embodiments, the self-healing MOSFETs are provided. By adding the healing gate structure, hot-carrier instability (HCI) degradation can be efficiently suppressed without the drawback of increasing leakage. Substrate current and time dependence of the HCI degradation (N-factor) are improved in the healing mechanism. With healing gate bias, the HCI stress injected hot carriers can be recovered and consequently the current degradation suppressed. In some embodiments, <NUM>% reduction of HCI degradation can be achieved.

According to one aspect of this disclosure, a semiconductor device structure is provided, comprising: a semiconductor substrate; a first well region over the semiconductor substrate and having a first type of conductivity; a second well region over the semiconductor substrate and having a second type of conductivity that is different from the first type of conductivity; a well region over the semiconductor substrate and between the first and second well regions, wherein the well region has a third type of conductivity that is different from the first type of conductivity and the second type of conductivity; a first gate structure of a transistor disposed on the well region and partially over the first and second well regions; a drain region of the transistor in the first well region and having the first type of conductivity; a source region of the transistor in the second well region and having the first type of conductivity; a bulk region of the transistor in the second well region and having the first type of conductivity; and a second gate structure of the transistor disposed on the second well region, wherein the second gate structure is separated from the first gate structure by the source region and the bulk region. The semiconductor device structure comprises: a first shallow trench isolation (STI) region in the second well region, wherein the second gate structure is separated from the bulk region by the first STI region; and a second STI region in the second well region and between the source region and the bulk region.

In one of more variants of this aspect, the semiconductor device is such that a gate length of the first gate structure is greater than that of the second gate structure; it comprises: a third STI region in the first well region, wherein the first gate structure is separated from the drain region by the third STI region; it comprises: a resist protect oxide (RPO) formed over a portion of the first gate structure and a portion of the drain region; the first type of conductivity is N-type, and the second type of conductivity is P-type, and the transistor is an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor; and/or the first type of conductivity is P-type, and the second type of conductivity is N-type, and the transistor is a P-type LDMOS transistor.

According to one aspect of this disclosure, a semiconductor device structure is provided, comprising: a semiconductor substrate; a first well region over the semiconductor substrate and having a first type of conductivity; a second well region over the semiconductor substrate and having a second type of conductivity that is different from the first type of conductivity; a first gate structure disposed partially over the first and second well regions; a drain region of the first type of conductivity in the first well region; a source region of the first type of conductivity in the second well region; a bulk region in the second well region; and a second gate structure disposed on the second well region, wherein the second gate structure is separated from the first gate structure by the source region and the bulk region, wherein gate length of the first gate structure is greater than that of the second gate structure. The semiconductor device structure comprises a first shallow trench isolation (STI) region in the second well region, wherein the second gate structure is separated from the bulk region by the first STI region; and a second STI region in the second well region and between the source region and the bulk region.

In one of more variants of this aspect, the semiconductor device is such that it comprises: a third STI region in the first well region, wherein the first gate structure is separated from the drain region by the third STI region; it comprises: a resist protect oxide (RPO) formed directly over a portion of the first gate structure, a portion of the drain region, and a portion of third STI region; it comprises: a resist protect oxide (RPO) formed directly over a portion of the first gate structure, and a portion of the drain region; the bulk region has the first type of conductivity; and/or it comprises: a doping region in the second well region and having the first type of conductivity, wherein the second gate structure is separated from the bulk region by the doping region.

According to one aspect of this disclosure, a semiconductor device structure is provided, comprising: a semiconductor substrate; a first well region over the semiconductor substrate and having a first type of conductivity; a second well region over the semiconductor substrate and having a second type of conductivity that is different from the first type of conductivity; a first gate structure disposed partially over the first and second well regions; a drain region of the first type of conductivity in the first well region; a source region of the first type of conductivity in the second well region; a lightly doped region of the first type of conductivity in the second well region and under the first gate structure; and a second gate structure disposed on the second well region, wherein the second gate structure is separated from the first gate structure by the source region, wherein the lightly doped region is in direct contact with the source region. The semiconductor device comprises a bulk region of the first type of conductivity in the second well region, a first shallow trench isolation (STI) region in the second well region, wherein the second gate structure is separated from the bulk region by the first STI region, and a second STI region in the second well region and between the source region and the bulk region.

Claim 1:
A semiconductor device structure (10A), comprising:
a semiconductor substrate (<NUM>);
a first well region (<NUM>) over the semiconductor substrate (<NUM>) and having a first type of conductivity;
a second well region (<NUM>) over the semiconductor substrate (<NUM>) and having a second type of conductivity that is different from the first type of conductivity;
a first gate structure (160A) of an LDMOS transistor disposed partially over the first and second well regions (<NUM>, <NUM>);
a drain region (130a) of the transistor in the first well region (<NUM>) and having the first type of conductivity;
a source region (130b) of the transistor in the second well region (<NUM>) and having the first type of conductivity; a bulk region (130c) of the transistor in the second well region (<NUM>); and
a second gate structure (165A) of the transistor disposed on the second well region (<NUM>),
wherein the second gate structure (165A) is separated from the first gate structure (160A) by the source region (130b) and the bulk region (130c); and characterized in that the bulk region (130c) has the first type of conductivity; and in that the semiconductor device structure (10A) further comprises
a first shallow trench isolation, STI, region (140d) in the second well region (<NUM>), wherein the second gate structure (165A) is separated from the bulk region (130c) by the first STI region (140d); and
a second STI region (140c) in the second well region (<NUM>) and between the source region (130b) and the bulk region (130c).