Patent Description:
A dual-controller disk array system (which is referred to as a dual-controller disk array system for short) includes two controllers and a disk array separately connected to the two controllers. The two controllers communicate with each other by using an external bus, for example, communicating with each other by using a peripheral component interconnect express (Peripheral Component Interconnect Express, PCIE) bus. In an operating process of the dual-controller disk array system, data of one of the two controllers is synchronized to the other controller as a backup. When one of the two controllers is faulty, the data may be recovered from the other controller, so as to avoid loss of the data. The disk array includes a plurality of physical disks, and the two controllers manage the disk array together.

An existing dual-controller disk array system further includes a shared cache apparatus connected to two controllers, and each controller communicates with the shared cache apparatus by using an external bus, for example, communicating with the shared cache apparatus by using a peripheral component interconnect express (Peripheral Component Interconnect Express, PCIE) bus. When data synchronization between the two controllers is implemented, after one controller receives, by using an internal bus, information carrying data, the controller converts a communication format of the information into an external bus format, and sends, to the shared cache apparatus by using the external bus, the information whose communication format is converted into the external bus format, so as to implement data synchronization between the two controllers. Transmission efficiency of a manner in which a controller converts a communication format to send information to the shared cache apparatus is low, and a speed of accessing the shared cache apparatus is slow. As a result, a speed at which a host stores, in the disk array, data that is in the shared cache apparatus is slow. Document <CIT> discloses an array controller, including a communications interface and a processor. The communications interface is configured to communicate with a solid state disk. The processor is configured to receive information about a logical block sent by the solid state disk, where the information about the logical block includes a size of the logical block and indication information of the logical block, and the logical block includes one or more blocks. The processor is further configured to send multiple write data requests to the solid state disk, where each write data request carries target data, each write data request is used to instruct the solid state disk to write the target data into the logical block indicated by the indication information of the logical block, and a sum of lengths of the target data carried in the multiple write data requests is equal to the size of the logical block. Document <CIT> discloses a controller connected to a cache device via a switching device, an input/output manager connected to the controller via the switching device, and the input/output manager is connected to a cache device via the switching device. The controller obtains a cache address from the cache device for to-be-written data according to the write data request, the controller sends an identifier of the cache device and the cache address to the input/output manager via the switching device, and the input/output manager writes the to-be-written data to the cache address via the switching device. Document <CIT> a method for transmitting data between an information processing device and a storage device, in which the storage device includes a buffer memory and flash chips, includes: receiving a first write request including data to be written and an address used for the flash chip of the storage device; allocating a first memory unit in the information processing device for the first write request; sending a write command including data, the address used for the flash chip of the storage device and address used for the buffer memory, to the storage device, in which the address used for the buffer memory corresponds to the first memory unit; receiving a message indicating the performing of the write command by the storage device has been completed, from the storage device; and releasing the first memory unit. Document <CIT> discloses a method including an operation for detecting a plurality of streams writing to the SSD, each stream writing in sectors, a page including a plurality of sectors and a block including a plurality of pages. A write operation includes writing at least one complete page, and an erase operation includes erasing at least one complete block. The method further includes operations for allocating a write buffer for each stream in RAM memory, and for storing each received sector of a stream in the corresponding write buffer. When a write buffer stores enough sectors to fill a page, content of the write buffer is written to a page in flash memory such that the page is filled. Further, the write buffer is freed after writing the content of the write buffer to the flash memory.

Embodiments of this application provide a data access method and an apparatus, to improve a speed of accessing a shared cache device by a host.

According to a first example, a data access method is provided, where the data access method is applied to a storage system, the storage system includes a first controller, the storage system further includes at least one shared cache apparatus, the first controller is connected to each of the at least one shared cache apparatus by using an internal bus, the method is applied to the first controller, and the method includes: receiving a destination address sent by each shared cache apparatus, where the destination address is used to indicate an address at which data is to be written into the shared cache apparatus; receiving information carrying the data; and sending the destination address and the data to the shared cache apparatus that sends the destination address, so that each shared cache apparatus stores the data in storage space to which the destination address points.

According to the present invention, the internal bus includes at least any one of the following internal buses: a quick path interconnect (Quick Path Interconnect, QPI) bus, an ultra path interconnect (Ultra Path Interconnect, UPI) bus, a hyper transport (Hyper Transport, HT) bus, or a global memory interconnect (Global Memory Interconnect, GMI) bus.

Therefore, a controller (for example, the first controller) is connected to the shared cache apparatus by using an internal bus, so that a host can access the shared cache apparatus in a memory access manner, thereby improving a speed of accessing the shared cache apparatus by the host.

With reference to the first example, in a possible implementation of the first example, the sending the destination address and the data to the shared cache apparatus that sends the destination address includes: generating a write data instruction, where the write data instruction includes the data and the destination address; and sending the write data instruction to the shared cache apparatus that sends the destination address.

With reference to the first example, in a possible implementation of the first example, the first controller includes a control cache module, and the sending the destination address and the data to the shared cache apparatus that sends the destination address includes: storing the data in the control cache module; generating a write data instruction, where the write data instruction includes a source address and the destination address, and the source address is an address of the data stored in the control cache module; and sending the write data instruction to the shared cache apparatus that sends the destination address, so that each shared cache apparatus reads the data from the control cache module based on the source address and stores the data in the storage space to which the destination address points.

According to a second example, a data access method is provided, where the data access method is applied to a storage system, the storage system includes a first controller, the storage system further includes at least one shared cache apparatus, the first controller is connected to each of the at least one shared cache apparatus by using an internal bus, the method is applied to any one of the at least one shared cache apparatus, and the method includes: sending a destination address to the first controller, where the destination address is used to indicate an address at which data is to be written into the shared cache apparatus; receiving the destination address and the data that are sent by the first controller; and storing the data in storage space to which the destination address points.

According to the present invention, the internal bus includes at least any one of the following internal buses: a quick path interconnect (Quick Path Interconnect, QPI) bus, an ultra path interconnect (Ultra Path Interconnect, UPI) bus, a hyper transport (Hyper Transport, HT) bus, and a global memory interconnect (Global Memory Interconnect, GMI) bus.

With reference to the second example, in a possible implementation of the second example, the receiving the destination address and the data that are sent by the first controller includes: receiving a write data instruction sent by the first controller, where the write data instruction includes the data and the destination address.

With reference to the second example, in a possible implementation of the second example, the first controller includes a control cache module, and the receiving the destination address and the data that are sent by the first controller includes: receiving a write data instruction sent by the first controller, where the write data instruction includes a source address and the destination address, and the source address is an address of the data stored in the control cache module; reading the data from the control cache module based on the source address; and storing the data at the destination address.

With reference to the second example, in a possible implementation of the second example, the shared cache apparatus includes a processing module and a non-volatile cache module, the non-volatile cache module includes a non-volatile memory (Non-Volatile Memory, NVM) medium, and the non-volatile cache module is connected to the processing module; the receiving the destination address and the data that are sent by the first controller includes: receiving, by using the processing module, the destination address and the data that are sent by the first controller; and the storing the data in storage space to which the destination address points includes: storing the data in the non-volatile cache module by using the processing module, where the non-volatile cache module includes the storage space to which the destination address points.

The non-volatile storage medium is configured in the shared cache apparatus, so as to avoid a data loss problem caused by an abnormal power failure.

With reference to the second example, in a possible implementation of the second example, the shared cache apparatus includes a processing module, a non-volatile cache module, and a shared memory, the non-volatile cache module includes an NVM medium, and the shared memory and the non-volatile cache module are separately connected to the processing module; the receiving the destination address and the data that are sent by the first controller includes: receiving, by using the processing module, the destination address and the data that are sent by the first controller; and the storing the data in storage space to which the destination address points includes: storing the data in the shared memory by using the processing module; and when a data volume of the shared memory reaches a threshold, storing, in the non-volatile cache module by using the processing module, the data that is in the shared memory, where the cache unit includes the storage space to which the destination address points.

The shared memory is configured in the shared cache apparatus, and the shared memory may be used as a buffer storage medium of the non-volatile cache module, so as to reduce a frequency of accessing the non-volatile cache module, and further reduce internal wear of the NVM storage medium.

Optionally, the shared memory is a dynamic random access memory.

According to a third example, a controller is provided, where the controller is configured in a storage system, the storage system includes at least one shared cache apparatus, the controller is connected to each of the at least one shared cache apparatus by using an internal bus, and the controller includes: a receiving module, configured to receive a destination address sent by each shared cache apparatus, and further configured to receive information carrying the data, where the destination address is used to indicate an address at which the data is to be written into the shared cache apparatus; and a sending module, configured to send the destination address and the data to the shared cache apparatus that sends the destination address, so that each shared cache apparatus stores the data in storage space to which the destination address points. The controller is configured to perform the data access method performed by the controller according to any one of the first example or the possible implementations of the first example.

According to a fourth example, a controlling device is provided, where the controlling device is configured in a storage system, the storage system includes at least one shared cache apparatus, the controlling device is connected to each of the at least one shared cache apparatus by using an internal bus, and the controlling device includes: a receiver, configured to receive a destination address sent by each shared cache apparatus, and receive information carrying the data, where the destination address is used to indicate an address at which the data is to be written into the shared cache apparatus; and a transmitter, configured to send the destination address and the data to the shared cache apparatus that sends the destination address, so that each shared cache apparatus stores the data in storage space to which the destination address points. The controlling device is configured to perform the data access method performed by the controller according to any one of the first example or the possible implementations of the first example.

According to a fifth example, a computer readable storage medium is provided, where the computer readable storage medium stores a computer program, and when the program is executed by a processor, the method according to any one of the first example or the possible implementations of the first example is implemented.

According to a sixth example, a shared cache apparatus is provided, where the shared cache apparatus is configured in a storage system, the storage system includes a first controller, the first controller is connected to the shared cache apparatus by using an internal bus, and the shared cache apparatus includes: a transceiver module, configured to: send a destination address to the first controller; receive the destination address and the data that are sent by the first controller, where the destination address is used to indicate an address at which the data is to be written into the apparatus; and a processing module, configured to store the data in storage space to which the destination address points. The shared cache apparatus is configured to perform the data access method performed by the shared cache apparatus according to any one of the first example or the possible implementations of the first example.

According to a seventh example, a shared cache device is provided, where the shared cache device is configured in a storage system, the storage system includes a first controller, the first controller is connected to the shared cache device by using an internal bus, and the shared cache device includes: a transceiver, configured to send a destination address to the first controller, and further configured to receive the destination address and the data that are sent by the first controller, where the destination address is used to indicate an address at which the data is to be written into the apparatus; and a processor, configured to store the data in storage space to which the destination address points. The shared cache device is configured to perform the data access method performed by the shared cache apparatus according to any one of the first example or the possible implementations of the first example.

According to an eighth example, a computer readable storage medium is provided, where the computer readable storage medium stores a computer program, and when the program is executed by a processor, the method according to any one of the first example or the possible implementations of the first example is implemented.

According to a ninth example, a storage system is provided, where the storage system includes the controller in the third example and implementations of the third example, where the controller is a first controller; the storage system further includes at least one shared cache apparatus in the sixth example and implementations of the sixth example, where the first controller is connected to each of the at least one shared cache apparatus by using an internal bus.

With reference to the ninth example, in a possible implementation of the ninth example, the storage system further includes a second controller, the second controller is connected to each of the at least one shared cache apparatus by using an internal bus, and the shared cache apparatus is configured to: when the first controller is faulty, receive a read data instruction sent by the second controller; query the data; and send the data to the second controller.

As shown in <FIG>, a storage system <NUM> includes at least a host <NUM>, a first controller <NUM>, a second controller <NUM>, and at least one shared cache apparatus <NUM>. The host <NUM> is separately connected to the first controller <NUM> and the second controller <NUM>, and the first controller <NUM> and the second controller <NUM> are separately connected to each of the at least one shared cache apparatus <NUM> by using an internal bus <NUM>.

In the present invention, the internal bus includes at least any one of the following internal buses: a quick path interconnect (Quick Path Interconnect, QPI) bus, an ultra path interconnect (Ultra Path Interconnect, UPI) bus, a hyper transport (Hyper Transport, HT) bus, and a global memory interconnect (Global Memory Interconnect, GMI) bus.

The host <NUM> may be any computing device such as a server or a desktop computer. The server may be a high-density server, a rack server, or a blade server.

Optionally, as shown in <FIG>, the first controller <NUM> includes a receiving module <NUM>, a sending module <NUM>, and a processing module <NUM>. The processing module <NUM> is separately connected to the receiving module <NUM> and the sending module <NUM>.

In the first controller <NUM> shown in <FIG>, the receiving module <NUM> is configured to receive a destination address sent by the shared cache apparatus <NUM>. The destination address is used to indicate an address at which data is to be written into the shared cache apparatus <NUM>.

The receiving module <NUM> is further configured to receive information carrying the data.

The processing module <NUM> is configured to parse the information carrying the data, to obtain the data.

The sending module <NUM> is configured to send the data and the destination address to the shared cache apparatus <NUM>, so as to instruct the shared cache apparatus <NUM> to write the data into storage space to which the destination address points.

Optionally, as shown in <FIG>, based on the first controller <NUM> shown in <FIG>, the first controller <NUM> may further include a control cache module <NUM>. The control cache module <NUM> is connected to the processing module <NUM>, and the processing module <NUM> first stores, in the control cache module <NUM>, the data to be written into the shared cache apparatus <NUM>.

The sending module <NUM> is further configured to send a source address and the destination address to the shared cache apparatus <NUM>. The source address is an address of the data stored in the control cache module <NUM>. The shared cache apparatus <NUM> reads the data from the control cache module <NUM> based on the source address, and writes the data into the storage space that is of the shared cache apparatus <NUM> and to which the destination address of the data points.

Optionally, as shown in <FIG>, the shared cache apparatus <NUM> includes a transceiver module <NUM>, a processing module <NUM>, and a non-volatile cache module <NUM>. The processing module <NUM> is separately connected to the transceiver module <NUM> and the non-volatile cache module <NUM>. The transceiver module <NUM> is configured to send a destination address in the shared cache apparatus <NUM> to the first controller <NUM>, and is further configured to receive the data and the destination address of the data that are sent by the first controller <NUM>. The processing module <NUM> is configured to: determine the destination address, of the data, that is received by the transceiver module <NUM>, and store the data in storage space that is of the non-volatile cache module <NUM> and to which the destination address points.

Optionally, as shown in <FIG>, based on the shared cache apparatus <NUM> shown in <FIG>, the shared cache apparatus <NUM> further includes a shared memory <NUM>, and the shared memory <NUM> is connected to the processing module <NUM>. After receiving the data and the destination address, the processing module <NUM> is configured to store the data in the shared memory <NUM>. When a volume of data stored in the shared memory <NUM> reaches a data volume threshold, all the data stored in the shared memory <NUM> is written, at one time, into the storage space that is of the non-volatile cache module <NUM> and to which the destination address points.

Optionally, the shared memory <NUM> is a dynamic random access memory (Dynamic Random Access Memory, DRAM).

The DRAM has a problem that storage data is lost due to a power failure. Therefore, when the shared cache apparatus <NUM> is configured with the DRAM, to avoid the data loss problem caused by an abnormal power failure, the shared cache apparatus <NUM> may be configured with a backup power supply. The backup power supply is used to supply power to the DRAM when the abnormal power failure occurs. As an example instead of a limitation, the DRAM may be a super capacitor.

The shared cache apparatus <NUM> is configured with the shared memory <NUM>. The shared memory <NUM> may be used as a buffer storage medium of the non-volatile cache module <NUM>, so as to reduce a frequency of accessing the non-volatile storage medium, and further reduce internal wear of the NVM storage medium.

Optionally, as shown in <FIG>, the transceiver module <NUM> in the shared cache apparatus <NUM> may further include a first interface <NUM> and a second interface <NUM>. The first controller <NUM> is connected to the shared cache apparatus <NUM> by using the first interface <NUM> of the shared cache apparatus <NUM>, and the second controller <NUM> is connected to the shared cache apparatus <NUM> by using the second interface <NUM> of the shared cache apparatus <NUM>. The first interface <NUM> is configured to: receive the data and the destination address of the data that are sent by the first controller <NUM>, and send the data and the destination address of the data to the processing module <NUM> in the shared cache apparatus <NUM>. The processing module <NUM> processes the data and the destination address of the data that are received, determines, based on the destination address, that the data needs to be stored in the storage space of the shared cache apparatus <NUM>, and stores the data in the storage space that is of the non-volatile cache module <NUM> and to which the destination address points.

The following uses communication between the shared cache apparatus <NUM> and the first controller <NUM> as an example to describe a data access method provided in the embodiments of this application.

<FIG> is a schematic flowchart of a data access method according to an embodiment of this application. As shown in <FIG>, step S201 in the data access method may be performed by the shared cache apparatus <NUM> shown in <FIG>, <FIG>, or may be performed by the transceiver module <NUM> in the shared cache apparatus <NUM> shown in <FIG>. Step S202 in the data access method may be performed by the first controller <NUM> or the second controller <NUM> shown in <FIG>, or may be performed by the receiving module <NUM> shown in <FIG>. Step S203 in the data access method may be performed by the first controller <NUM> or the second controller <NUM> shown in <FIG>, or may be performed by the sending module <NUM> shown in <FIG>, or may be performed through cooperation by the processing module <NUM> and the sending module <NUM> shown in <FIG>. Step S204 in the data access method may be performed by the shared cache apparatus <NUM> shown in <FIG>, <FIG>, or may be performed by the processing module <NUM> of the shared cache apparatus <NUM> shown in <FIG>. This is not specifically limited in this embodiment of this application.

The shared cache apparatus <NUM> sends a destination address to the first controller <NUM>, where the destination address is used to indicate an address at which data is to be written into the shared cache apparatus <NUM>.

The first controller <NUM> maps, to global storage space of a storage system based on the destination address, storage space to which the destination address in the shared cache apparatus <NUM> points, and stores a mapping relationship between the destination address in the shared cache apparatus <NUM> and a logical address of the shared cache apparatus <NUM>. The logical address of the shared cache apparatus <NUM> indicates an address layout, in the global storage space of the storage system, of the storage space corresponding to the destination address in the shared cache apparatus <NUM>.

The destination address includes a start address and an end address of storage space to which a continuous physical address points or an identifier of the shared cache apparatus <NUM>.

Specifically, as an example instead of a limitation, the storage space corresponding to the destination address is the storage space to which the continuous physical address points.

When the system is powered on or restarted, the shared cache apparatus <NUM> sends the destination address to the first controller <NUM>. The destination address includes a start address and an end address of the storage space of the shared cache apparatus <NUM>. The first controller <NUM> maps the storage space of the shared cache apparatus <NUM> to the global storage space of the system based on the start address and the end address. When the first controller <NUM> maps the storage space corresponding to the destination address in the shared cache apparatus <NUM> to the global storage space of the storage system, the first controller <NUM> creates the logical address of the shared cache apparatus <NUM>, and stores the mapping relationship between the logical address of the shared cache apparatus <NUM> and the destination address of the shared cache apparatus <NUM>. In this way, the destination address is a physical address of the storage space of the shared cache apparatus <NUM>. After each controller stores a mapping relationship table, the physical address of the storage space of the shared cache apparatus <NUM> is visible to each controller, and each controller may perform storage processing by using the physical address of the storage space of the shared cache apparatus <NUM>.

For example, the start address included in the destination address is <NUM>, and the end address included in the destination address is <NUM>. The first controller <NUM> maps, to the global storage space of the system based on the destination address, storage space corresponding to a range from <NUM> to <NUM>. For example, the storage space, of the shared cache apparatus <NUM>, that is corresponding to the range from <NUM> to <NUM> is mapped by the first controller <NUM> to storage space, of the global storage space, that is corresponding to a range from <NUM> to <NUM>, and an address corresponding to the range from <NUM> to <NUM> is the logical address of the shared cache apparatus <NUM>.

It should be noted that the foregoing performs description by using an example in which the destination address includes the start address and the end address of the storage space of the shared cache apparatus <NUM>. However, this embodiment of this application is not limited thereto.

Optionally, the destination address includes the identifier of the shared cache apparatus <NUM> and a storage capacity of the storage space of the shared cache apparatus <NUM>. The first controller <NUM> maps the storage space of the shared cache apparatus <NUM> to the global storage space based on the storage capacity of the storage space of the shared cache apparatus <NUM>.

After the first controller <NUM> creates the mapping relationship between the logical address of the shared cache apparatus <NUM> and the destination address of the shared cache apparatus <NUM>, the first controller <NUM> may configure the mapping relationship table for the shared cache apparatus <NUM> by using a basic input/output system (basic input/output system, BIOS) of the first controller <NUM>. In this way, the address layout, in the global storage space of the storage system, of the storage space of the shared cache apparatus <NUM> is visible to the shared cache apparatus <NUM>.

Optionally, the destination address includes the identifier of the shared cache apparatus <NUM>. The identifier of the shared cache apparatus <NUM> may be either a number of the shared cache apparatus <NUM> or a communication address of the shared cache apparatus <NUM>. This is not specifically limited in this embodiment of this application. The first controller <NUM> prestores the storage capacity of the shared cache apparatus <NUM>. The first controller <NUM> may obtain, based on the identifier of the shared cache apparatus <NUM>, the prestored storage capacity of the shared cache apparatus <NUM> through querying. After mapping the storage space of the shared cache apparatus <NUM> to the global storage space based on the storage capacity of the shared cache apparatus <NUM>, the first controller <NUM> stores a mapping relationship between the identifier of the shared cache apparatus <NUM> and the logical address of the shared cache apparatus <NUM>.

It should be noted that in this embodiment of this application, the foregoing performs description by using an example in which the first controller <NUM> obtains information about the storage space of the shared cache apparatus <NUM> by receiving the destination address sent by the shared cache apparatus <NUM>. However, this embodiment of this application is not limited thereto.

For example, the first controller <NUM> can further obtain, by using the basic input/output system (BIOS) of the first controller <NUM>, the destination address of the shared cache apparatus <NUM> when the system is powered on or restarted.

The first controller <NUM> receives information carrying the data.

Specifically, after the first controller <NUM> receives the destination address through step S201, the first controller <NUM> receives the information that carries the data and that is sent by a host <NUM>, and the data is data to be written into the shared cache apparatus <NUM>.

After receiving the information carrying the data, the first controller <NUM> parses the information carrying the data to obtain the data. The first controller <NUM> determines the logical address at which the data is to be stored in the global storage space of the storage system, and determines, based on the mapping relationship table between the logical address of the shared cache apparatus <NUM> and the identifier of the shared cache apparatus <NUM>, the shared cache apparatus <NUM> into which the data is to be written.

Optionally, based on step S201, after the first controller <NUM> receives the destination address including the start address and the end address, if the first controller <NUM> creates the mapping relationship table between the logical address of the shared cache apparatus <NUM> and the destination address of the shared cache apparatus <NUM>, the first controller <NUM> may determine, based on the mapping relationship table between the logical address of the shared cache apparatus <NUM> and the destination address of the shared cache apparatus <NUM>, the storage space to which the destination address at which the data is to be stored in the shared cache apparatus <NUM> points. The storage space to which the destination address of the shared cache apparatus <NUM> points is storage space within a range from the start address to the end address.

Specifically, the first controller <NUM> first determines, based on the mapping relationship table between the logical address of the shared cache apparatus <NUM> and the destination address of the shared cache apparatus <NUM> in step S201, that the logical address at which the data is to be stored in the global storage space of the storage system is located within the range from <NUM> to <NUM>, and determines, based on a mapping relationship between the logical address, of the shared cache apparatus <NUM>, that is corresponding to the range from <NUM> to <NUM> and the destination addresses, of the shared cache apparatus <NUM>, that is corresponding to the range from <NUM> to <NUM>, that the storage space to which the destination address of the shared cache apparatus <NUM> in which the data is to be stored points is storage space within the address range, of the shared cache apparatus <NUM>, that is from <NUM> to <NUM>.

The first controller <NUM> sends the destination address and the data to the shared cache apparatus <NUM>, so that the shared cache apparatus <NUM> stores the data in the storage space to which the destination address points.

Specifically, in step S203, the first controller <NUM> sends, to the shared cache apparatus <NUM>, information carrying the destination address, so as to implement sending of the destination address. Based on description of step S201, the destination address includes the start address and the end address of the storage space to which the continuous physical address points, or includes the identifier of the shared cache apparatus <NUM>.

In addition to sending the destination address and the data, the first controller <NUM> further sends an effective length of the data to the shared cache apparatus <NUM>, where the effective length of the data indicates a size of storage space that the data needs to occupy, so as to instruct the shared cache apparatus <NUM> to allocate the storage space corresponding to the size indicated by the effective length of the data to store the data.

Optionally, in another implementation of step S203, the first controller <NUM> generates a write data instruction, where the write data instruction includes the data and the destination address of the data (for example, the destination address of the data is the start address and the end address of the storage space or the identifier of the shared cache apparatus <NUM>), and the first controller <NUM> sends the write data instruction to the first shared cache apparatus <NUM>.

Optionally, in another implementation of step S203, the first controller <NUM> may further generate a write data instruction, where the write data instruction includes the data, the destination address of the data (for example, the destination address of the data is the start address of the storage space or the identifier of the shared cache apparatus <NUM>), and the effective length of the data. The first controller <NUM> sends the write data instruction to the first shared cache apparatus <NUM>.

Optionally, in another implementation of step S203, an optional implementation in which the first controller <NUM> sends the data to the shared cache apparatus <NUM> is as follows: The first controller <NUM> first stores the data in the control cache module <NUM>, and generates a write data instruction, where the write data instruction includes a source address and the destination address at which the data is to be written into the shared cache apparatus <NUM>, the source address is a storage location of the data in the control cache module <NUM>; and the first controller <NUM> sends the write data instruction to the shared cache apparatus <NUM>, so that the shared cache apparatus <NUM> reads the data from the control cache module <NUM> based on the source address.

The shared cache apparatus <NUM> stores the data in the storage space to which the destination address points.

After receiving the destination address and the data that are sent by the first controller <NUM>, the shared cache apparatus <NUM> stores the data in the storage space to which the destination address points.

Specifically, the shared cache apparatus <NUM> stores, by using the following four implementation methods, the data in the storage space to which the destination address points.

When the destination address sent by the first controller <NUM> to the shared cache apparatus <NUM> includes the identifier of the shared cache apparatus <NUM>, the shared cache apparatus <NUM> stores the data in the shared cache apparatus <NUM> upon determining that the received identifier of the shared cache apparatus <NUM> is consistent with the identifier stored by the shared cache apparatus <NUM>.

When the destination address of the data includes the start address and the end address of the storage space to which the continuous physical address points, the shared cache apparatus <NUM> directly stores the data in the storage space, of the shared cache apparatus <NUM>, that is indicated by the destination address.

If the destination address of the shared cache apparatus <NUM> includes the start address and the end address of the storage space to which the continuous physical address points, and includes the identifier of the shared cache apparatus <NUM>, the shared cache apparatus <NUM> directly stores, upon determining, based on the identifier, that the identifier is consistent with the identifier stored by the shared cache apparatus <NUM>, the data in the storage space, of the shared cache apparatus <NUM>, that is indicated by the destination address.

Based on step S201, if the first controller <NUM> configures the mapping relationship table between the logical address of the shared cache apparatus <NUM> and the destination address of the shared cache apparatus <NUM> for the shared cache apparatus <NUM> by using the basic input/output system (Basic Input Output System, BIOS) of the first controller <NUM>, when the destination address sent by the first controller <NUM> to the shared cache apparatus <NUM> includes the identifier and the logical address that are of the shared cache apparatus <NUM>, the shared cache apparatus <NUM> may first query the mapping relationship table upon determining, based on the identifier, that the identifier is consistent with the identifier stored by the shared cache apparatus <NUM>, determine the corresponding destination address based on the logical address of the shared cache apparatus <NUM>, and store the data in the storage space to which the destination address of the shared cache apparatus <NUM> points.

Optionally, the destination address sent by the first controller <NUM> to the shared cache apparatus <NUM> includes the identifier of the shared cache apparatus <NUM>. In addition to sending the destination address to the shared cache apparatus <NUM>, the first controller <NUM> further sends, to the shared cache apparatus <NUM>, the logical address at which the data is to be stored in the global storage space. When the shared cache apparatus <NUM> first determines, based on the identifier, that the identifier is consistent with the identifier stored in the shared cache apparatus <NUM>, the shared cache apparatus <NUM> further determines, based on the foregoing mapping relationship table that is between the logical address of the shared cache apparatus <NUM> and the destination address of the shared cache apparatus <NUM> and that is configured by the first controller <NUM> for the shared cache apparatus <NUM>, an offset, relative to a start logical address, of the logical address at which the data is to be stored in the global storage space, and determines, based on the offset, the physical address at which the data is to be stored in the shared cache apparatus <NUM>, and finally stores the data in the storage space, of the shared cache apparatus <NUM>, to which the physical address points.

It should be noted that the start logical address may be a start logical address of the global storage space (for example, the start logical address of the global storage space is <NUM>), or the start logical address may be a start logical address obtained after the destination address of the shared cache apparatus <NUM> is mapped to the global storage space (for example, the start logical address obtained after the destination address of the shared cache apparatus <NUM> is mapped to the global storage space is <NUM>). This is not specifically limited in this application.

Optionally, the host <NUM> may be connected to a plurality of shared cache apparatuses <NUM>, and any two of the plurality of shared cache apparatuses <NUM> form mirrored shared cache apparatuses. To be specific, reading and writing access performed by the host <NUM> on one of the two shared cache apparatuses <NUM> may also occur between the host <NUM> and the other shared cache apparatus <NUM>, so that same data may be stored in one of the two shared cache apparatuses <NUM>, and may also be stored in the other shared cache apparatus <NUM>. In this way, a data loss problem caused by a fault of one of the two shared cache apparatuses <NUM> is avoided. In other words, data storage reliability is improved.

Two interfaces of one of the two shared cache apparatuses <NUM> are respectively connected to the first controller <NUM> and the second controller <NUM>. Similarly, two interfaces of the other shared cache apparatus <NUM> are also respectively connected to the first controller <NUM> and the second controller <NUM>. In other words, each controller is connected to two interfaces, and the two interfaces are one interface of one of the two shared cache apparatuses <NUM> and one interface of the other shared cache apparatus <NUM>.

It should be noted that in this embodiment of this application, example description is performed by using an example in which the first controller <NUM> configures the mapping relationship table between the logical address of the shared cache apparatus and the physical address of the shared cache apparatus for the shared cache apparatus <NUM> by using the basic input/output system (Basic Input Output System, BIOS) of the first controller <NUM>. However, this embodiment of this application is not limited thereto. For example, the first controller <NUM> may further send the mapping relationship table and the information carrying the data to the shared cache apparatus <NUM> together.

An embodiment of this application provides a controller (for example, the first controller <NUM>), and a schematic block diagram of the controller is shown in <FIG> and <FIG>. For brevity, details are not described herein again. The following only describes operations performed by modules shown in <FIG> and <FIG>.

The receiving module <NUM> is configured to receive a destination address sent by each shared cache apparatus <NUM>, where the destination address is used to indicate an address at which data is to be written into the shared cache apparatus <NUM>.

The receiving module <NUM> is further configured to:
receive information carrying the data.

The sending module <NUM> is configured to:
send the destination address and the data to the shared cache apparatus <NUM> that sends the destination address, so that each shared cache apparatus <NUM> stores the data in storage space to which the destination address points.

Optionally, the controller <NUM> further includes:.

Optionally, the controller <NUM> further includes the control cache module <NUM>, and the processing module <NUM> is further configured to:.

It should be understood that the processing module <NUM> in this embodiment of the present application may be implemented by a processor or a processor-related circuit component, the receiving module <NUM> may be implemented by a receiver or a receiver-related circuit component, and the sending module <NUM> may be implemented by a transmitter or a transmitter-related circuit component.

As shown in <FIG>, an embodiment of this application further provides a controlling device <NUM>. The controlling device <NUM> includes a processor <NUM>, a memory <NUM>, and a transceiver <NUM>. The memory <NUM> stores an instruction or a program, the memory <NUM> is further configured to perform an operation performed by the control cache module <NUM> in the foregoing embodiment, and the processor <NUM> is configured to execute the instruction or the program stored in the memory <NUM>. When the instruction or the program stored in the memory <NUM> is executed, the processor <NUM> is configured to perform an operation performed by the processing module <NUM> in the foregoing embodiment, and the transceiver <NUM> is configured to perform an operation performed by the receiving module <NUM> or the sending module <NUM> in the foregoing embodiment.

An embodiment of this application provides a shared cache apparatus <NUM>, and a schematic block diagram of the shared cache apparatus <NUM> is shown in <FIG>. For brevity, details are not described herein again. The following only describes operations performed by modules shown in <FIG>. The transceiver module <NUM> is configured to send a destination address to the first controller <NUM>, where the destination address is used to indicate an address at which data is to be written into the shared cache apparatus <NUM>.

The transceiver module <NUM> is further configured to:
receive the destination address and the data that are sent by the first controller.

The processing module <NUM> is configured to store the data in storage space to which the destination address points.

Optionally, the transceiver module <NUM> is further configured to:
receive a write data instruction sent by the first controller, where the write data instruction includes the data and the destination address.

Optionally, the first controller includes a control cache module <NUM>, and the transceiver module <NUM> is specifically configured to:.

Optionally, the shared cache apparatus <NUM> further includes the non-volatile cache module <NUM>, the non-volatile cache module <NUM> includes an NVM medium, and the non-volatile cache module <NUM> is connected to the processing module <NUM>;
the transceiver module <NUM> is further configured to:.

Optionally, the apparatus further includes the non-volatile cache module <NUM> and the shared memory <NUM>, where the non-volatile cache module <NUM> includes an NVM medium, and the shared memory <NUM> and the non-volatile cache module <NUM> are separately connected to the processing module <NUM>;
the transceiver module <NUM> is further configured to:.

It should be understood that the processing module <NUM> in this embodiment of the present application may be implemented by a processor or a processor-related circuit component, and the transceiver module <NUM> may be implemented by a transceiver or a transceiver-related circuit component.

As shown in <FIG>, an embodiment of this application further provides a shared cache device <NUM>. The shared cache device <NUM> includes a processor <NUM>, a memory <NUM>, and a transceiver <NUM>. The memory <NUM> stores an instruction or a program, the memory <NUM> is further configured to perform operations performed by the non-volatile cache module <NUM> and the shared memory <NUM> in the foregoing embodiment, and the processor <NUM> is configured to execute the instruction or the program stored in the memory <NUM>. When the instruction or the program stored in the memory <NUM> is executed, the processor <NUM> is configured to perform an operation performed by the processing module <NUM> in the foregoing embodiment, and the transceiver <NUM> is configured to perform an operation performed by the transceiver module <NUM> in the foregoing embodiment.

It may be clearly understood by a person skilled in the art that, for the purpose of convenient and brief description, for a detailed working process of the foregoing system, apparatus, and unit, reference can be made to a corresponding process in the foregoing method embodiments.

The units described as separate components may or may not be physically separate, and components displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units.

Claim 1:
A data access method, wherein the data access method is applied to a storage system, the storage system comprises a first controller (<NUM>), the storage system further comprises at least one shared cache apparatus (<NUM>), wherein the first controller (<NUM>) is connected to each of the at least one shared cache apparatus (<NUM>) by using an internal bus, the method is applied to the first controller (<NUM>), and the method comprises:
Receiving (S201) a destination address sent by each shared cache apparatus (<NUM>), wherein the destination address is used to indicate an address at which data is to be written into the shared cache apparatus (<NUM>);
Receiving (S202) information carrying the data; and
Sending (S203) the destination address and the data to the shared cache apparatus (<NUM>) that sends the destination address, so that each shared cache apparatus (<NUM>) stores the data in storage space to which the destination address points; characterized in that the internal bus is one of the following internal buses: a quick path interconnect bus, an ultra path interconnect bus, a hyper transport bus, and a global memory interconnect bus.