Patent Description:
As described in Unexamined <CIT>, an inversely staggered structure is generally adopted for a thin film transistor used as a switching element of an active matrix liquid crystal display device. A thin film transistor of this structure is constructed such that a gate electrode is formed on an insulating substrate, a gate insulating film is formed on the upper surface of the gate electrode and insulating substrate, a semiconductor thin film made of intrinsic amorphous silicon is formed on the upper surface of the gate insulating film that is on the gate electrode, a channel protection film is formed on the center portion of the upper surface of the semiconductor thin film, ohmic contact layers made of n-type amorphous silicon are formed on both sides of the upper surface of the channel protection film and on the semiconductor thin film at both sides of the channel protection film, and source and drain electrodes are formed on the upper surfaces of the respective ohmic contact layers.

Recently, there is an idea of using zinc oxide (ZnO) instead of amorphous silicon, because a higher mobility than that of amorphous silicon can be obtained from zinc oxide. In a case where a zinc oxide film is formed by CVD (Chemical Vapor Deposition), the film property is unstable in the initial state. Therefore, if the inversely staggered structure is adopted, the zinc oxide film in this unfavorable initial state is placed opposite to the gate electrode, i.e., the zinc oxide film in the unfavorable state forms the channel region, making it harder to achieve excellent properties as a thin film transistor. A cure for this that is now being considered is to make a thin film transistor of a top gate type, in which the upper surface of the zinc oxide film serves as the channel region. A conceivable manufacturing method of a thin film transistor of the top gate type using zinc oxide is to, for example, form a semiconductor thin film forming layer made of intrinsic zinc oxide on a gate insulating film, form a patterned channel protection film made of silicon nitride on the upper surface of the semiconductor thin film forming layer, form an ohmic contact layer forming layer made of n-type zinc oxide on the upper surface of the semiconductor thin film forming layer including the channel protection film, sequentially pattern the ohmic contact layer forming layer and the semiconductor thin film forming layer to form an ohmic contact layer and a semiconductor thin film in the device area, and form source and drain electrodes by patterning on the upper surface of each patterned ohmic contact layer.

<NPL>, <CIT>, <CIT>, <CIT>, <CIT> and <CIT> are relevant prior art.

However, according to the above-described manufacturing method, it has been turned out that since zinc oxide easily melts in both acid and alkali and has a greatly low etching resistance, the semiconductor thin film and ohmic contact layer made of zinc oxide formed in the device area suffer a relatively large side etching in the manufacturing steps to follow, lowering the process accuracy. Hence, an object of the present invention is to provide a liquid crystal display comprising a thin film transistor formed with a fine process accuracy.

To achieve the above object, a liquid crystal display device is provided as defined in claim <NUM>. Further embodiments are defined in dependent claims.

These objects and other objects and advantages of the present invention will become more apparent upon reading of the following detailed description and the accompanying drawings in which:.

<FIG> shows a see-through plan view of the principal part of a liquid crystal display device comprising a thin film transistor and not forming part of the claimed invention. <FIG> shows an expanded see-through plan view of a part of <FIG>, and <FIG> shows a cross sectional view as sectioned along a line IIB-IIB of <FIG>. The liquid crystal display device has a glass substrate <NUM>.

Explanation will first be given with reference to <FIG>. Scanning lines <NUM> and data lines <NUM> are formed in a matrix form on the upper surface of the glass substrate <NUM>. A pixel electrode <NUM> is formed in the region surrounded by the scanning lines <NUM> and data lines <NUM>, so as to be connected to a scanning line <NUM> and a data line <NUM> via a thin film transistor <NUM>. A latticed auxiliary capacitor electrode <NUM> is formed in parallel with the scanning lines <NUM> and data lines <NUM>. Note that hatching of angled short solid lines is used at the edges of the pixel electrode <NUM>, throughout the drawings including <FIG>, for the purposes of making the plan- view structure clear.

In <FIG>, the pixel electrode <NUM> has its lower-left corner cut away, and the principal part of the thin film transistor <NUM> is arranged at the cut-away region. All the surrounding edges of the pixel electrode <NUM> overlap the auxiliary capacitor electrode <NUM> having the latticed shape formed therearound. The auxiliary capacitor electrode <NUM> having the latticed shape comprises a first auxiliary capacitor electrode portion 6a formed of a portion including a region overlapping the data line <NUM>, a second auxiliary capacitor electrode portion 6b formed of a portion including a region overlapping the scanning line <NUM>, and a third auxiliary capacitor electrode portion 6c formed of a portion including a region overlapping the principal part of the thin film transistor <NUM>. In this case, as will be described later, the auxiliary capacitor electrode <NUM> is formed on a different layer from that of the scanning lines <NUM>, and particularly, the first auxiliary capacitor electrode portion 6a of the auxiliary capacitor electrode <NUM> is formed to be insulated from the data line <NUM> and the pixel electrode <NUM> by insulating films respectively, in its thickness direction, i.e., in the direction vertical to the drawing sheet of <FIG>.

The width of the first auxiliary capacitor electrode portion 6a is larger than the width of the data line <NUM> by some degree. This enables the first auxiliary capacitor electrode portion 6a to securely cover the data line <NUM> so as not to permit the data line <NUM> to directly face the pixel electrode <NUM> even if a positional displacement occurs in a direction perpendicular to the direction in which the data line <NUM> extends. The first auxiliary capacitor electrode 6a is arranged almost all over the area where the data lines <NUM> are arranged. This makes the first auxiliary capacitor electrode portion 6a securely overlap the left and right edges of the pixel electrode <NUM> even if the first auxiliary capacitor electrode portion 6a is positionally displaced with respect to the pixel electrode <NUM> in a direction parallel with the data lines <NUM>, making it possible to securely prevent fluctuation in the auxiliary capacitance due to positioning misplacement in this direction.

The width of the second auxiliary capacitor electrode portion 6b is larger than the width of the scanning line <NUM> by some degree. This makes the second auxiliary capacitor electrode portion 6b securely cover the scanning line <NUM> even if a positional displacement occurs in a direction perpendicular to the direction in which the scanning line <NUM> extends. The second auxiliary capacitor electrode portion 6b is arranged almost all over the area where the scanning lines <NUM> are arranged. This makes the second auxiliary capacitor electrode portion 6b securely overlap the upper and lower edges of the pixel electrode <NUM> even if the second auxiliary capacitor electrode portion 6b is positionally displaced with respect to the pixel electrode <NUM> in a direction parallel with the scanning lines <NUM>, making it possible to securely prevent fluctuation in the auxiliary capacitance due to positional displacement in this direction.

Next, the specific structure of the present liquid crystal display device will be explained with reference to <FIG>. A source electrode <NUM>, a drain electrode <NUM>, and the data line <NUM> connected to the drain electrode <NUM>, which are made of aluminum, chromium, ITO, or the like, are formed at predetermined positions on the upper surface of the glass substrate <NUM>. An ohmic contact layer <NUM> on one side made of n type zinc oxide is formed on the upper surface of the source electrode <NUM> at a side closer to the drain electrode <NUM>. An ohmic contact layer <NUM> on the other side made of n type zinc oxide is formed on the upper surface of the drain electrode <NUM> including a part of the data line <NUM> at a side closer to the source electrode <NUM>. End surfaces 13a and 14a of the ohmic contact layers <NUM> and <NUM> facing each other have the same shape as that of end surfaces 11a and 12a of the source electrode <NUM> and drain electrode <NUM> facing each other. Here, zinc oxide means not only ZnO, but also all ZnO-based materials including Mg, Cd, <NUM> etc. in addition to ZnO.

A semiconductor thin film <NUM> made of intrinsic zinc oxide is formed on entirely the two ohmic contact layers <NUM> and <NUM>, and on the upper surface of the grass substrate <NUM> that appears between the contact layers <NUM> and <NUM>. A protection film <NUM> made of silicon nitride is formed on the entire surface of the semiconductor thin film <NUM>. The semiconductor thin film <NUM> and the protection film <NUM> have the same plan-view shape, as shown in <FIG>. The surrounding end surfaces of the two ohmic contact layers <NUM> and <NUM>, except the end surfaces 13a and 14a facing each other, have the same shape as that of the surrounding end surfaces of the semiconductor thin film <NUM> and protection film <NUM>. The interval between the end surfaces 13a and 14a of the two ohmic contact layers <NUM> and <NUM> is the channel length L, and the dimension of the ohmic contact layers <NUM> and <NUM> in the direction perpendicular to the channel length L is the channel width W.

An insulating film <NUM> made of silicon nitride is formed on the upper surface of the grass substrate <NUM> including the protection film <NUM>, the source electrode <NUM>, and the data line <NUM>. A gate electrode <NUM> and the scanning line <NUM> connected to the gate electrode <NUM>, which are made of aluminum, chromium, ITO, or the like are formed at predetermined positions on the upper surface of the insulating film <NUM>.

The source electrode <NUM>, the drain electrode <NUM>, the ohmic contact layers <NUM> and <NUM>, the semiconductor thin film <NUM>, the protection film <NUM>, the insulating film <NUM>, and the gate electrode <NUM> form the thin film transistor <NUM> of a top gate structure. In this case, the gate insulating film of the thin film transistor <NUM> is formed by the protection film <NUM> and the insulating film <NUM>.

An upper insulating film <NUM> made of silicon nitride is formed on the upper surface of the insulating film <NUM> including the gate electrode <NUM> and the scanning line <NUM>. The auxiliary capacitor electrode <NUM> having a mostly latticed shape made of a light blocking metal such as aluminum, chromium, etc. is formed at a predetermined position on the upper surface of the upper insulating film <NUM>. An overcoat film <NUM> made of silicon nitride is formed on the upper surface of the upper insulating film <NUM> including the auxiliary capacitor electrode <NUM>. A contact hole <NUM> is formed in the overcoat film <NUM>, the upper insulating film <NUM>, and the insulating film <NUM> at a portion corresponding to predetermined position on the source electrode <NUM>. The pixel electrode <NUM> made of a transparent conductive material such as ITO, etc. is formed at a predetermined position on the upper surface of the overcoat film <NUM>, so as to be connected to the source electrode <NUM> through the contact hole <NUM>.

Next, an example of a manufacturing method of the region around the thin film transistor <NUM> in the present liquid crystal- display will be explained. First, as shown in <FIG>, the source electrode <NUM>, the drain electrode <NUM>, and the data line connected to the drain electrode <NUM> are formed on the respective predetermined positions on the upper surface of the grass substrate <NUM>, by photolithographically patterning a metal film made of aluminum, chromium, ITO, or the like formed by sputtering.

Next, a first ohmic contact layer forming layer <NUM> made of n type zinc oxide is formed on the upper surface of the grass substrate <NUM> including the source electrode <NUM>, the drain electrode <NUM>, and the data line <NUM>, by facing-target sputtering. In this case, the first ohmic contact layer forming layer <NUM> can be formed by reactive sputtering using oxygen gas, and using indium and zinc as the targets, or gallium and zinc as the targets. Alternatively, indium-zinc oxide (InZnO) or gallium-zinc oxide (GaZnO) may be used as the targets.

Next, resist patterns 32a and 32b are formed on respective predetermined positions on the upper surface of the first ohmic contact layer forming layer <NUM>, by photolithography including rear exposure (exposure from the lower surface of the grass substrate <NUM>). In this case, because of the rear exposure, one resist pattern 32a is formed on the source electrode <NUM>, and the other resist pattern 32b is formed on the drain electrode <NUM> and the data line <NUM>.

Next, the first ohmic contact layer forming layer <NUM> is etched by using the resist patterns 32a and 32b as masks, to form second ohmic contact layer forming layers <NUM> a and 31b under the resist patterns 32a and 32b, as shown in <FIG>. In this case, an alkaline aqueous solution is used as the etching liquid for the first ohmic contact layer forming layer <NUM> made of n type zinc oxide. For example, an aqueous solution containing less than <NUM> wt% sodium hydroxide (NaOH), preferably, containing <NUM> to <NUM> wt% sodium hydroxide. The temperature of the etching liquid is <NUM> to <NUM> <<NUM>>C, preferably, a room temperature (<NUM> to <NUM>).

In a case where an aqueous solution containing <NUM> wt% sodium hydroxide (NaOH) (whose temperature is a room temperature (<NUM> to <NUM>) was used, the etching rate was about <NUM>/minute. When taking the etching process controllability into consideration, a too high etching rate makes it difficult to control the etching end due to factors such as variations in film thickness, density, etc., while, needless to say, a too low etching rate decreases the productivity. Hence, it is generally said that the etching rate should preferably be <NUM> to <NUM>/minute. Thus, it can be said that the aqueous solution containing <NUM> wt% sodium hydroxide (NaOH), which achieved the etching rate of about <NUM>/minute is within a range of satisfaction.

However, the density of sodium may be increased- to further improve the manufacturing efficiency. In a case where an etching liquid such as phosphoric acid aqueous solution, that has a high etching rate, is used, the liquid needs to have a very low density of about <NUM>% with a concern for the etching process controllability. However, such a low density liquid is quick to deteriorate while it is being used, causing the same problem of process control difficulties. Hence, if a sodium hydroxide aqueous solution is used, the aqueous solution can be less than <NUM> wt%, preferably about <NUM> to <NUM> wt%, proving its usefulness in this respect. In a case where the amount of side etching caused in the first ohmic contact layer forming layer <NUM> by wet etching affects the interval between the end surfaces 13a and 14a of the ohmic contact layers <NUM> and <NUM>, i.e., the channel length L, dry etching may be employed.

Next, the resist patterns 32a and 32b are separated by using a resist separation liquid. Here, the inventor has confirmed that the resist separation can finely be performed even by using, as the resist separation liquid, a liquid showing neither acidity nor alkalinity (including no electrolyte), such as a single organic solvent (for example, dimethylsulfoxide (DMSO)). In this case, the resist separation liquid etches the second ohmic contact layer forming layers 31a and 31b made of n type zinc oxide, but the amount of accompanying side etching is not so large, not to an extent that the channel length L would be affected. Furthermore, the resist etching liquid also etches out the top surfaces of the second ohmic contact layer forming layers 31a and 31b, but there will be no trouble because a film thinning of the ohmic contact layers will not influence the properties of the thin film transistor. ITO may be used instead of n type zinc oxide, as the ohmic contact layers.

Next, a semiconductor thin film forming film 15a made of intrinsic zinc oxide and a protection film forming film 16a made of silicon nitride are continuously formed by plasma CVD on the upper surface of the grass substrate <NUM> including the second ohmic contact layer forming layers 31a and 31b, as shown in <FIG>. Next, a resist pattern <NUM> for forming a device area is formed by photolithography at a predetermined position on the upper surface of the protection film forming film 16a.

Next, the protection film forming film 16a is etched by using the resist pattern <NUM> as a mask, to form the protection film <NUM> under the resist pattern <NUM> as shown in <FIG>. In this case, the surface of the semiconductor thin film forming film 15a is exposed, except under the resist pattern <NUM>. Hence, reactive plasma etching (dry etching) using sulferhexafluoride (SF6) is preferable as the etching method for the protection film forming film 16a made of silicon nitride, because this etching method has a high etching rate and because it is needed to leave the semiconductor thin film forming film 15a made of intrinsic zinc oxide the least eroded.

Next, the resist pattern <NUM> is separated by using a resist separation liquid, hi this case, the surface of the semiconductor thin film forming film 15a except under the protection film <NUM> is exposed to the resist separation liquid, but no trouble will occur since the exposed surface is not the device area. That is, the properties of the thin film transistor will be greatly influenced if the channel region experiences a side etching or the upper surface of the channel region undergoes etching unlike the above-described case of forming the ohmic contact layers, but the semiconductor thin film forming film 15a under the protection film <NUM> is protected by the protection film <NUM>. In this case, a resist separation liquid showing neither acidity nor alkalinity (including no electrolyte), for example, a single organic solvent (for example, dimethylsulfoxide (DMSO) may be used.

Next, the semiconductor thin film forming film 15a and the second ohmic contact layer forming layers 31a and 31b are continuously etched by using the protection film <NUM> as a mask, to form the semiconductor thin film <NUM> under the protection film <NUM>, and both the ohmic contact layers <NUM> and <NUM> under the semiconductor thin film <NUM>, as shown in <FIG>.

In this case, since the semiconductor thin film forming film 15a and the second ohmic contact layer forming layers 31a and 31b are made of intrinsic zinc oxide and n type zinc oxide, the process controllability will be fine if the above-described sodium hydroxide aqueous solution is used as the etching liquid. Here, the interval between the two ohmic contact layers <NUM> and <NUM> is the channel length L, and the dimension of the ohmic contact layers <NUM> and <NUM> in the direction perpendicular to the channel length L is the channel width W.

In the above description, it is after the resist pattern <NUM> is separated when the semiconductor thin film forming film 15a and the second ohmic contact layer forming layers 31a and 31b are etched by using the protection film <NUM> as the mask. However, the resist pattern <NUM> may be separated after the semiconductor thin film forming film 15a and the ohmic contact layer forming layers 31a and 31b are etched.

Next, the insulating film <NUM> made of silicon nitride is formed by plasma CVD on the upper surface of the grass substrate <NUM> including the protection film <NUM>, the source electrode <NUM>, and the data line <NUM>, as shown in <FIG>. Next, the gate electrode <NUM> and the scanning line <NUM> connected to the gate- electrode <NUM> are formed at predetermined positions on the upper surface of the insulating film <NUM>, by photolithographically patterning a metal film made of chromium, aluminum, ITO, or the like formed by sputtering.

Next, the upper insulating film <NUM> made of silicon nitride is formed by plasma CVD on the upper surface of the insulating film <NUM> including the gate electrode <NUM> and the scanning line <NUM>, as shown in <FIG>. Next, the auxiliary capacitor electrode <NUM> is formed at a predetermined position on the upper surface of the upper insulating film <NUM>, by photolithographically patterning a light blocking metal film made of chromium, aluminum, or the like formed by sputtering.

Next, the overcoat film <NUM> made of silicon nitride is formed by plasma CVD on the upper surface of the upper insulating film <NUM> including the auxiliary capacitor electrode <NUM>, as shown in <FIG> A and <FIG>. Next, the contact hole <NUM> is formed by photolighography through the overcoat film <NUM>, the upper insulating layer <NUM>, and the insulating layer <NUM> sequentially, in a portion corresponding to a predetermined position on the source electrode <NUM>. Next, the pixel electrode <NUM> is formed at a predetermined position on the upper surface of the overcoat film <NUM> so as to be connected to the source electrode <NUM> through the contact hole <NUM>, by photolithographically patterning a pixel electrode forming film made of a transparent conductive material such as ITO formed by sputtering. Thus, the liquid crystal display device shown in <FIG> are obtained.

As described above, according to this manufacturing method, the resist pattern <NUM> for forming the protection film <NUM> on the upper surface of the semiconductor thin film forming film 15a is separated while a part of the semiconductor thin film forming film 15a is protected by the protection film <NUM>, then the semiconductor thin film forming film 15a and the second ohmic contact layer forming layers 31a and 31b are continuously etched by using the protection film <NUM> as the mask, thereby to form the semiconductor thin film <NUM> under the protection film <NUM>, and the ohmic contact layers <NUM> and <NUM> at both sides under the semiconductor thin film <NUM>, with the protection film <NUM> left untouched on the entire upper surface of the semiconductor thin film <NUM>. Accordingly, the process accuracy can be improved.

Further, in the thin film transistor <NUM> obtained by the above-described manufacturing method, since the interval between the two ohmic contact layers <NUM> and <NUM> is the channel length L and the dimension of the ohmic contact layers <NUM> and <NUM> in the direction perpendicular to the channel length L is the channel width W, this dimension can be made equal or similar to the dimension of a thin film transistor of a channel etch type having a bottom-gate structure, which leads to downsizing of the transistor.

Further, in the liquid crystal display device obtained by the above-described manufacturing method, since the first and second auxiliary capacitor electrode portions 6a and 6b having a larger width than that of the scanning line <NUM> and data line <NUM> are formed between the pixel electrode <NUM>, and the scanning line <NUM> and the data line <NUM>, it is possible to prevent occurrence of coupling capacitance between the pixel electrode <NUM>, and the scanning line <NUM> and the data line <NUM> by these first and second auxiliary capacitor electrode portions 6a and 6b, thereby to ensure that no vertical crosstalk occurs and improve the display characteristics.

In the earlier manufacturing steps, it may be such that a source/drain electrode forming film and the first ohmic contact layer forming layer <NUM> are continuously formed on the upper surface of the grass substrate <NUM>, the resist patterns 32a and 32b as shown in, for example, <FIG> are formed on the upper surface of the first ohmic contact layer forming layer <NUM>, the first ohmic contact layer forming layer <NUM> and the source/drain electrode forming film are continuously etched by using the resist patterns 32a and 32b as masks, thereby to form the second ohmic contact layer forming layers 31a and 31b under the resist patterns 32a and 32b, and the source electrode <NUM> and the drain electrode <NUM> under the second ohmic contact layer forming layers 32a and 32b, as shown in, for example, <FIG>.

<FIG> shows a see-through plan view of a principal part of a liquid crystal display device comprising a thin film transistor, and not forming part of the claimed invention. <FIG> shows a cross sectional view as sectioned along an XB-XB line of <FIG>. The difference between the present liquid crystal display device and the liquid crystal display device shown in <FIG> is that one ohmic contact layer <NUM> is formed at a predetermined position on the upper surface of the source electrode <NUM> at a side closer to the drain electrode <NUM> and on the neighboring upper surface of the grass substrate <NUM>, and the other ohmic contact layer <NUM> is formed at a predetermined position on the upper surface of the drain electrode <NUM> including a part of the data line <NUM> at a side closer to the source electrode <NUM> and on the neighboring upper surface of the grass substrate <NUM>. That is, the ohmic contact layers <NUM> and <NUM> are formed on the upper surfaces of the source electrode <NUM> and drain electrode <NUM> respectively, so as to have their facing end surfaces 13a and 14a protrude from the facing end surfaces 11a and 12a of the source electrode <NUM> and drain electrode <NUM>.

Next, one example of a manufacturing method of a region around the thin film transistor <NUM> in the present liquid crystal display device will be explained. First, the source electrode <NUM>, the drain electrode <NUM>, and the data line <NUM> connected to the drain electrode <NUM> are formed on respective predetermined positions on the upper surface of the grass substrate <NUM>, as shown in <FIG>, by photolithographically patterning a metal film made of aluminum, chromium, ITO, or the like formed by sputtering.

Next, a first ohmic contact layer forming layer <NUM> made of n type zinc oxide is formed on the upper surface of the grass substrate <NUM> including the source electrode <NUM>, the drain electrode <NUM>, and the data line <NUM>, by facing-target sputtering. Next, resist patterns 32a and 32b are formed on respective predetermined positions on the upper surface of the first ohmic contact layer forming layer <NUM>, by photolithography.

In this case, one resist pattern 32a is formed to be larger than the source electrode <NUM> by some degree in order to fully cover the source electrode <NUM>. The other resist pattern 32b is formed to be larger than the drain electrode <NUM> including a part of the data line <NUM> by some degree so as to fully cover the drain electrode <NUM> including the part of the data line <NUM>.

The resist patterns 32a and 32b are formed as described above, because, to explain with reference to <FIG>, the interval between the end surface I la of the source electrode <NUM> and the end surface 13a of the one ohmic contact layer <NUM> is the margin for keeping these end surfaces I la and 13a at a desired positional relation and needs generally to be <NUM> to <NUM>, though might vary depending on process accuracy.

Next, the first ohmic contact layer forming layer <NUM> is etched by using the resist patterns 32a and 32b as masks, to form second ohmic contact layer forming layers 31a and 31b under the resist patterns 32a and 32b as shown in <FIG>. In this case, since the first ohmic contact layer forming layer <NUM> is made of n type zinc oxide, the process controllability can be fine if the above-described sodium hydroxide is used as the etching liquid.

Next, the resist pattern 32a and 32b are separated by using a resist separation liquid. In this case, the surfaces of the second ohmic contact layer forming layers 31a and 31b are exposed. Thus, a resist separation liquid showing neither acidity nor alkalinity (including no electrolyte), for example, a single organic solvent (for example, dimethylsulfoxide (DMSO)), is used.

Next, as shown in <FIG>, a semiconductor thin film forming film 15a made of intrinsic zinc oxide and a protection film forming film 16a made of silicon nitride are continuously formed by plasma CVD on the upper surface of the grass substrate <NUM> including the second ohmic contact layer forming layers 31a and 31b and the data line <NUM>. Next, a resist pattern <NUM> for forming a device area is formed by photolithography at a predetermined position on the upper surface of the protection film forming film 16a.

Next, the protection film forming film 16a is etched by using the resist pattern <NUM> as a mask, to form the protection film <NUM> under the resist pattern <NUM> as shown in <FIG>. In this case, the surface of the semiconductor thin film forming film 15a, except under the resist pattern <NUM> is exposed. Accordingly, reactive plasma etching (dry etching) using sulferhexafluoride (SF<NUM>) is preferable as the etching method for forming the protection film <NUM> made of silicon nitride.

Next, the resist pattern <NUM> is separated by using a resist separation liquid. In this case, the surface of the semiconductor thin film forming film 15a except under the protection film <NUM> is exposed to the resist separation liquid, but there will be no trouble because the exposed surface is not the device area. That is, the semiconductor thin film forming film 15a under the protection film <NUM> is protected by the protection film <NUM>. In this case, a resist separation liquid showing neither acidity nor alkalinity (including no electrolyte), such as a single organic solvent (for example, dimethylsulfoxide (DMSO)) may be used.

Next, the semiconductor thin film forming film 15a and the second ohmic contact layer forming layers 31a and 31b are continuously etched by using the protection film <NUM> as a mask, to form the semiconductor thin film <NUM> under the protection film <NUM>, and the ohmic contact layers <NUM> and <NUM> at both sides under the semiconductor thin film <NUM>, as shown in <FIG>.

In this case, since the semiconductor thin film forming film 15a and the second ohmic contact layer forming layers 31a and 31b are made of intrinsic zinc oxide and n type zinc oxide, the process controllability can be fine if the above-described sodium hydroxide aqueous solution is used as the etching liquid. Here, the interval between the end surfaces 13a and 14a of the two ohmic contact layers <NUM> and <NUM> is the channel length L, and the dimension of the ohmic contact layers <NUM> and <NUM> in the direction perpendicular to the channel length L is the channel width W. Hereafter, the similar manufacturing steps to those of the first example are gone through to obtain the liquid crystal display device shown in <FIG>.

<FIG> shows a see-through plan view of a principal part of a liquid crystal display device comprising a thin film transistor, as an embodiment of the present invention. <FIG> shows a cross-sectional view as sectioned along a ling XVIB-XVIB of <FIG>. The difference between the present liquid crystal display device and the liquid crystal display device shown in <FIG> is that no upper insulating film <NUM> is formed but the gate electrode <NUM>, the scanning line <NUM> connected to the gate electrode <NUM>, and the auxiliary capacitor electrode <NUM>, which are made of a light blocking metal such as aluminum, chromium, etc., are formed at respective predetermined positions on the upper surface of the insulating film <NUM>, and the gate electrode <NUM>, the scanning line <NUM>, and the auxiliary capacitor electrode <NUM> are covered with the overcoat film (insulating film) 20a.

In this case, the auxiliary capacitor electrode <NUM> comprises a first auxiliary capacitor electrode portion 6d including a region overlapping a part of the data line <NUM>, a second auxiliary capacitor electrode portion 6e arranged near the scanning line <NUM> in parallel with the scanning line <NUM>, and a third auxiliary capacitor electrode portion 6f arranged along a predetermined edge of the pixel electrode <NUM>. To make the plan-view shape of the auxiliary capacitor electrode <NUM> clear, the edges of the auxiliary capacitor electrode <NUM> are drawn by bolder solid lines than those for the other components.

According to a manufacturing method of a region around the thin film transistor <NUM> of the present liquid crystal display device, it is possible to simultaneously form the gate electrode <NUM>, the scanning line <NUM> connected to the gate electrode <NUM>, and the auxiliary capacitor electrode <NUM>, which are made of a light blocking metal such as aluminum, chromium, etc. at the respective predetermined positions on the upper surface of the insulating film <NUM>. Therefore, as compared with the case shown in <FIG>, it is possible to omit the step of forming the upper insulating film, the step of forming an auxiliary capacitor electrode forming film, the step of forming a resist pattern for forming the auxiliary capacitor electrode, the step of forming the auxiliary capacitor electrode by etching the auxiliary capacitor electrode forming film by using the resist pattern as a mask, and the step of separating the resist pattern, enabling the number of manufacturing steps to be reduced.

The semiconductor thin film forming film 15a and the ohmic contact layer forming layer <NUM> may be formed not only by plasma CVD, but by sputtering, vapor deposition, casting, plating, etc. The ohmic contact layers <NUM> and <NUM> may be not only made of n type zinc oxide, but of p type zinc oxide, and further, of zinc oxide whose conductivity has been altered by an oxygen vacancy.

A base insulating film may be formed between the glass substrate <NUM>, and the source electrode <NUM> and drain electrode <NUM>. In a case where the base insulating film is made of, for example, an ion barrier material, it is possible to reduce impurity diffusion from the glass substrate <NUM> and to suppress reaction of the glass substrate <NUM> with the zinc oxide film. In a case where a material having similar lattice constant and crystalline structure to those of zinc oxide is selected as the material of the base insulating film, it is possible to improve the crystallinity of the zinc oxide film.

According to the present invention, it is possible to improve the process accuracy, by forming a protection film on entirely the upper surface of the semiconductor thin film made of intrinsic zinc oxide, that is, by protecting the semiconductor thin film forming film made of intrinsic zinc oxide, that is under the protection film, with the protection film when separating the resist pattern for forming the protection film on the upper surface of the semiconductor thin film forming film, then forming the semiconductor thin film under the protection film by etching the semiconductor thin film forming film by using the protection film as the mask, and leaving the protection film on the entire upper surface of the semiconductor thin film. Various embodiments and changes may be made thereunto without departing from the invention as defined by the appended claims.

Claim 1:
A liquid crystal display device, comprising:
a thin film transistor which includes:
a semiconductor thin film (<NUM>) including zinc oxide;
a protection film (<NUM>) on entirely an upper surface of the semiconductor thin film (<NUM>);
a gate insulating film (<NUM>) on the protection film (<NUM>);
a gate electrode (<NUM>) on the gate insulating film (<NUM>) above the semiconductor thin film (<NUM>); and
a source electrode (<NUM>) and a drain electrode (<NUM>) under the semiconductor thin film (<NUM>) and electrically connected to the semiconductor thin film (<NUM>);
the liquid crystal display device further comprising:
an overcoat film (20a) covering the gate electrode (<NUM>);
a pixel electrode (<NUM>) on an upper surface of the overcoat film (20a) and connected to the source electrode (<NUM>);
an auxiliary capacitor electrode (<NUM>) disposed on an upper surface of the gate insulating film (<NUM>);
a data line (<NUM>) connected to the drain electrode (<NUM>) and disposed on a same layer as that of the drain electrode (<NUM>);and
a scanning line (<NUM>) connected to the gate electrode (<NUM>) and disposed on a same layer as that of the auxiliary capacitor electrode (<NUM>) and the gate electrode (<NUM>),
wherein the auxiliary capacitor electrode (<NUM>) comprises a portion (6d) which includes a region overlapping the data line (<NUM>), a portion (6e) which is arranged near the scanning line (<NUM>) in parallel with the scanning line (<NUM>), and a portion (6f) arranged along a predetermined edge of the pixel electrode (<NUM>),
wherein a width of the portion (6d) of the auxiliary capacitor electrode (<NUM>) including the region overlapping the data line (<NUM>) is larger than a width of the data line (<NUM>).