Patent Description:
<CIT> discloses an integrated circuit (IC) die according to the preamble of claim <NUM>.

Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. An IC die includes a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.

The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. As used herein, a "package" and an "IC package" are synonymous. When used to describe a range of dimensions, the phrase "between X and Y" represents a range that includes X and Y. For convenience, the phrase "<FIG>" may be used to refer to the collection of drawings of <FIG>, the phrase "<FIG>" may be used to refer to the collection of drawings of <FIG>, etc.
In three-dimensional (3D) ICs, conductive interconnects (e.g., metal layers) are present on both the frontside and the backside of a device layer. Conventional approaches to electrically coupling the device layer to the backside interconnects, or electrically coupling the frontside interconnects to the backside interconnects, have incurred significant area penalties and/or undesirable electrical performance (e.g., excessive capacitive coupling that limits the speed at which signaling may be performed). Various ones of the embodiments disclosed herein may and readily fabricated device layer interconnects that achieve good electrical performance for modern computing applications.

The structures disclosed herein may be formed on a substrate. The substrate may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The substrate may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the substrate. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation for an IC device may be used. The substrate may be part of a singulated die (e.g., the dies <NUM> of <FIG>) or a wafer (e.g., the wafer <NUM> of <FIG>).

A plurality of transistors may be formed in a device layer on the substrate. These transistors may include one or more metal oxide semiconductor field-effect transistors (MOSFETs). To provide these transistors, the device layer may include, for example, one or more source and/or drain (S/D) regions, one or more gates to control current flow in the transistors between the S/D regions, and one or more S/D contacts to route electrical signals to/from the S/D regions. The transistors may include planar transistors, nonplanar transistors, or a combination of both. Planar transistors may include bipolar junction transistors (BJT), heterojunction bipolar transistors (HBT), or high-electron-mobility transistors (HEMT). Nonplanar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors. Although the accompanying drawings may illustrate only nonplanar transistors, it should be noted that the techniques and structures disclosed herein may also be applied to planar transistors, as suitable. According to the invention, the device layer includes a transistor array along a semiconductor fin.

Each transistor may include a gate formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.

The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor <NUM> is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

In some embodiments, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

The S/D regions may be formed within the substrate adjacent to the gate of each transistor. The S/D regions may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the S/D regions. An annealing process that activates the dopants and causes them to diffuse farther into the substrate may follow the ion-implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the SID regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions. In some implementations, the S/D regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions.

One or more interlayer dielectrics (ILD) are deposited over the transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than ten metal layers may be added in the BEOL.

Various embodiments described herein are directed to techniques for device layer interconnects in a 3D IC. In various embodiments, the 3D IC may include a device layer that includes logic transistors (e.g., in a transistor array). In some embodiments, the logic transistors may be nonplanar transistors (e.g., FinFETs). For example, a plurality of fins may be formed in the device layer, and gate stacks and S/D electrodes (e.g., source or drain electrodes) may be formed on the fins to form transistors.

The 3D IC may further include frontside interconnects in one or more metal layers on a frontside of the 3D IC (e.g., above the substrate on which the logic transistors are formed) and backside interconnects in one or more metal layers on a backside of the 3D IC (e.g., below the substrate on which the logic transistors are formed). In some embodiments, the substrate may be partially or completely removed after formation of the logic transistors.

In various embodiments, the 3D IC further includes one or more device layer interconnects that extend through the device layer of the 3D IC to provide a conductive connection between one or more of the frontside interconnects and one or more of the backside interconnects. According to the invention, the individual device layer interconnects are formed in a gate region of a dummy transistor (e.g., dummy FinFET) of the transistor array. For example, FinFETS may be at least partially formed in the device layer, including semiconductor fins, and gate stacks and S/D electrodes on the semiconductor fins in respective gate regions and diffusion regions. Then, a trench is formed in some of the gate regions and filled with a metal, thereby forming the device layer interconnects between the backside and frontside of the 3D IC. In some embodiments, the fins may also be removed from the trench. In other embodiments, the fins may remain in the trench, and the metal of the device layer interconnects may be disposed between and/or around the fins.

The device layer interconnects as described herein may enable a high-density and low-capacitance connection for signal routing between the frontside and backside of the 3D IC (e.g., between circuit devices and/or interconnects on the frontside and backside of the 3D IC). In some embodiments, the device layer interconnects disclosed herein may be used for routing power and/or ground signals from the backside of a 3D IC to the device layer of the 3D IC in a dense manner.

<FIG> illustrates a top view of an IC structure <NUM> including a device layer interconnect <NUM> in accordance with various examples not forming part of the claimed invention. <FIG> illustrates a side cross-sectional view along the line B-B in <FIG>, and <FIG> illustrates a side cross-sectional view along the line C-C in <FIG>. For ease of illustration, <FIG> is not a complete cross-sectional view, but represents a cross-sectional view of a portion of the IC structure <NUM> including three gate stacks <NUM>; others of the accompanying "B" sub-figures utilizes the same limited view. Similarly, <FIG> illustrates a cross-sectional view through three fins <NUM> (instead of the two fins <NUM> of <FIG>) to provide a fuller picture of the accompanying structure; others of the accompanying "C" sub-figures utilize the same expanded view. The IC structure <NUM> of <FIG> may be incorporated into a 3D IC.

The IC structure <NUM> may include a device layer <NUM> including a plurality of fins <NUM> of a semiconductor material (e.g., silicon and/or another suitable material). The IC structure <NUM> may further include a gate stack <NUM> on a top surface and sidewalls of the fins <NUM> in respective gate regions, and S/D electrodes <NUM> on a top surface and sidewalls of the fins <NUM> in respective diffusion regions. Between the fins <NUM>, a dielectric material <NUM> may be present. A number of elements of <FIG> are shared with others of the accompanying figures; for ease of discussion, a description of these elements is not repeated, and these elements may take the form of any of the examples or embodiments disclosed herein unless otherwise indicated.

The IC structure <NUM> of <FIG> (and the IC structures <NUM> of <FIG>) may include a device layer <NUM> including a plurality of fins <NUM> of a semiconductor material (e.g., silicon and/or another suitable material). The IC structure <NUM> of <FIG> (and the IC structures <NUM> of <FIG>) may further include gate stacks <NUM> on a top surface and sidewalls of the fins <NUM> in respective gate regions, and S/D electrodes <NUM> on a top surface and sidewalls of the fins <NUM> in respective diffusion regions. In some embodiments, the IC structure <NUM> of <FIG> (and the IC structures <NUM> of <FIG>) may further include spacers (e.g., sidewall spacers) <NUM> between the S/D electrodes <NUM> and the gate stacks <NUM>. Additionally, or alternatively, a dielectric <NUM> may be between the fins <NUM>, above the device layer <NUM>, and/or below the device layer <NUM>.

The gate stack <NUM> may include a gate electrode including one or more layers, such as gate electrode layer <NUM>, gate electrode layer <NUM>, and/or gate electrode layer <NUM>. The gate electrode layers <NUM>, <NUM>, and/or <NUM> may include any suitable material or materials, as described herein. The gate stack <NUM> may further include a gate dielectric <NUM> between the gate electrode and the fin <NUM>. The gate dielectric <NUM> may include any suitable material or materials, as described herein. The S/D electrodes <NUM> may include one or more layers, such as S/D electrode layer <NUM> and/or S/D electrode layer <NUM>. The SID electrode layers <NUM> and/or <NUM> may include any suitable materials as described herein for source/drain contacts.

In various embodiments, the device layer interconnect <NUM> may extend through the device layer <NUM>. an example not forming part of the claimed invention and shown in <FIG>, <FIG>, the device layer interconnect <NUM> may be in a diffusion region of the device layer <NUM> (e.g., of a dummy transistor in the device layer <NUM>) that would normally include an S/D electrode <NUM> (e.g., for a logic transistor in the transistor array). The device layer interconnect <NUM> may provide a conductive connection between a frontside interconnect <NUM> and a backside interconnect <NUM>. In some examples, one or more vias (e.g., via <NUM>) may couple the device layer interconnect <NUM> to the frontside interconnect <NUM> and/or the backside interconnect <NUM>. Although illustrated herein as having substantially parallel sidewalls, any of the device layer interconnects <NUM> disclosed herein may have tapered sidewalls (e.g., narrowing toward the backside interconnect <NUM> and widening toward the frontside interconnect <NUM>).

Spacers <NUM> may be between the device layer interconnect <NUM> and adjacent gate stacks <NUM>. Additionally, the dielectric <NUM> may be between the device layer interconnect <NUM> and adjacent fins <NUM> that form transistors of the transistor array.

The device layer interconnect <NUM> may include any suitable conductor, such as one or more metals, including, but not limited to, copper, tungsten, tantalum, ruthenium, titanium, tantalum and nitrogen (e.g., TaN), titanium and nitrogen (e.g., TiN), etc. The device layer interconnect <NUM> may be formed of the same material or a different material from the frontside interconnect <NUM>, the backside interconnect <NUM>, and/or the via <NUM>. Additionally, or alternatively, the device layer interconnect <NUM> may be formed of the same material or a different material as a material of the S/D electrode <NUM> (e.g., the S/D electrode layer <NUM> and/or <NUM>).

In some examples not forming part of the claimed invention, the device layer interconnect <NUM> may include a first portion <NUM> and a second portion <NUM>, with the first portion <NUM> having a larger width than the second portion <NUM> (e.g., in a direction that is transverse to the orientation of the fins <NUM>), as shown in <FIG>. The first portion <NUM> may be coplanar with the S/D electrodes <NUM> of adjacent transistors in the device layer <NUM>. The second portion <NUM> may be below the first portion <NUM>, and may couple the first portion <NUM> to the backside interconnect <NUM>. In some examples, the first portion <NUM> and second portion <NUM> may be formed by separate deposition processes, during formation of the device layer interconnect <NUM>. The first portion <NUM> and second portion <NUM> may be the same or different materials.

In various examples not forming part of the claimed invention, a device layer interconnect <NUM> may extend across multiple fins <NUM>. For example, in some examples, the transistors formed by the fins <NUM> may be tri-gate transistors, and the device layer interconnect <NUM> may extend across three fins <NUM>. In some examples, a portion or all of the fins may be preserved within the device layer interconnect <NUM>, as shown in <FIG>. The conductive material of the device layer
interconnect <NUM> may be between the fins <NUM>. The selective epitaxial growth of fins <NUM> in a typical junction is blocked by a patterned resist layer, thereby allowing the conductive material filled between the fins <NUM> to electrically couple the frontside interconnect <NUM> and the backside interconnect <NUM>.

Any suitable technique may be used to form the IC structures <NUM> disclosed herein. For example, in some examples, the transistors and device layer interconnects <NUM> may be formed, and then the frontside interconnects <NUM> may be formed. After the frontside structures have been fabricated, the remaining substrate (e.g., a semiconductor wafer) at the backside may be thinned, exposing the bottom faces of the device layer interconnects <NUM>. The backside interconnects <NUM>, and any other backside structures, may then be formed (and may, for example, couple to the exposed bottom faces of the device layer interconnects <NUM>).

In other examples not forming part of the claimed invention, the fins may be removed from the trench in which the device layer interconnect is formed, enabling more conductive material to be filled in the trench and thereby providing lower resistance for the device layer interconnect. For example, <FIG>, <FIG> illustrate an IC structure <NUM> in which the fins <NUM> have been removed from the region occupied by the device layer interconnect <NUM>. <FIG> illustrates a top view of the IC structure <NUM>, <FIG> illustrates a side cross-sectional view along the line B-B in <FIG>, and <FIG> illustrates a side cross-sectional view along the line C-C in <FIG>. The IC structure <NUM> of <FIG> may be included in a 3D IC. The device layer interconnect <NUM> of IC structure <NUM> may provide a lower resistance than the device layer interconnect <NUM> of IC structure <NUM>, but at the cost of increased manufacturing complexity.

In some embodiments, a device layer interconnect <NUM> may be formed in the gate region of the device layer in a 3D IC. For example, <FIG> illustrates a top view of an IC structure <NUM> including a device layer interconnect <NUM> in a gate region of a device layer <NUM>, in accordance with various examples not forming part of the claimed invention. <FIG> illustrates a side cross-sectional view along the line B-B in <FIG>, and <FIG> illustrates a side cross-sectional view along the line C-C in <FIG>. The IC structure <NUM> of <FIG> may be included in a 3D IC.

In the example of <FIG>, the device layer interconnect <NUM> may be formed in a gate region of the transistor array in the device layer <NUM> that would otherwise have a gate stack <NUM>. Spacers <NUM> may be between the device layer interconnect <NUM> and adjacent S/D electrodes <NUM>. Additionally, the dielectric <NUM> may be between the device layer interconnect <NUM> and adjacent fins <NUM> that form transistors of the transistor array.

The device layer interconnect <NUM> may electrically couple a frontside interconnect <NUM> with a backside interconnect <NUM> (e.g., via a via <NUM>). In some examples, the device layer interconnect <NUM> may have the same width across the entire device layer <NUM>. In some IC dies, different sets of transistors on a single fin <NUM> may be electrically isolated from each other by trenches filled with a dielectric (or "isolation") material. These isolation trenches may be oriented perpendicular to a fin <NUM>, and may "cut across" multiple fins <NUM>. In some examples, an isolation trench takes the place of a gate; such isolation trenches may thus be referred to as "dummy gates. " For example, <FIG> illustrates a top view of an IC structure <NUM> including a device layer interconnect <NUM> in a dummy gate region of a device layer <NUM>, in accordance with the present invention. <FIG> illustrates a side cross-sectional view along the line B-B in <FIG>, and <FIG> illustrates a side cross-sectional view along the line C-C in <FIG>. The IC structure <NUM> of <FIG> may be included in a 3D IC, and may be particularly useful for delivering power from the backside of a die to the device layer <NUM> (through the backside interconnect <NUM> and the device layer interconnect <NUM>).

In the embodiment of <FIG>, the device layer interconnect <NUM> is formed in a dummy gate region of the transistor array in the device layer <NUM> that would otherwise have an isolation material <NUM>; that isolation material <NUM> may be disposed in a trench in an area that may itself otherwise have been a gate region. An IC structure <NUM> like the IC structure <NUM> of <FIG> may be fabricated in any suitable manner; for example, after the gate stacks <NUM> are formed, trenches may be formed and filled with isolation material <NUM>, then portions of that isolation material <NUM> (and the underlying fin <NUM> and any underlying dielectric <NUM>) may be etched away and filled with a conductive material to form the device layer interconnects <NUM>.

<FIG> illustrates an isolation material <NUM> on opposite faces of the device layer interconnect <NUM> in a direction perpendicular to the fins <NUM>. The S/D electrodes <NUM> may make contact with S/D regions <NUM> (e.g., diffusion regions) in the fin <NUM>; as shown in <FIG>, the device layer interconnect <NUM> may make contact with the S/D regions <NUM> on opposite faces of the device layer interconnect <NUM> along the fin <NUM>. Further, the device layer interconnect <NUM> may make contact with the S/D electrodes <NUM> on opposite faces of the device layer interconnect <NUM> along the fin <NUM>. Thus, the device layer interconnect <NUM> of <FIG> may be electrically coupled to the adjacent S/D regions <NUM> and S/D electrodes <NUM>. When the device layer interconnect <NUM> takes the place of isolation material <NUM> that would have otherwise separated different logic cells (e.g., as discussed below with reference to <FIG>), the device layer interconnect <NUM> may electrically couple the different logic cells. In the embodiment of <FIG> (and <FIG>), the S/D electrodes <NUM> may be local interconnect trenches (LITs) that span multiple fins <NUM>.

In some embodiments, the device layer interconnect <NUM> of <FIG> may electrically couple a frontside interconnect <NUM> with a backside interconnect <NUM> (e.g., via a via <NUM>). In other embodiments, the device layer interconnect <NUM> may couple the adjacent S/D regions <NUM> and S/D electrodes <NUM> to a backside interconnect <NUM>, but may not couple the S/D regions <NUM> and S/D electrodes <NUM> to any frontside interconnect <NUM>. In some embodiments, a single device layer interconnect <NUM> like that illustrated in <FIG> may span multiple fins <NUM> or a single fin <NUM> (e.g., as illustrated in <FIG> and as discussed below with reference to <FIG>).

In some embodiments in which the device layer interconnect <NUM> is located in a dummy gate region, the conductive material of the device layer interconnect <NUM> (e.g., a metal) may extend up to and beyond the top of the fin <NUM> (e.g., as illustrated in <FIG>) or may stop at the top surface of the fin <NUM>. In some of the latter embodiments, the S/D electrode <NUM> may be disposed at the top surface of the fin <NUM>. For example, <FIG> illustrates a top view of an IC structure <NUM> similar to that of <FIG>, but in which an S/D electrode <NUM> is disposed at the top surface of the device layer interconnect <NUM>, in accordance with various embodiments. <FIG> illustrates a side cross-sectional view along the line B-B in <FIG>, and <FIG> illustrates a side cross-sectional view along the line C-C in <FIG>. The IC structure <NUM> of <FIG> may be included in a 3D IC, and may be particularly useful for delivering power from the backside of a die to the device layer <NUM> (through the backside interconnect <NUM> and the device layer interconnect <NUM>). An IC structure <NUM> like the IC structure <NUM> of <FIG> may be fabricated in any suitable manner; for example, after the gate stacks <NUM> are formed, but before the S/D electrodes <NUM> are formed, trenches may be formed and filled with isolation material <NUM>, portions of that isolation material <NUM> (and the fin <NUM> and any underlying dielectric material <NUM>) may be etched away and filled with a conductive material to form the device layer interconnects <NUM>, and then the S/D electrodes <NUM> may be formed above the fin <NUM> and the device layer interconnects <NUM>. In some embodiments, forming the device layer interconnects <NUM> of <FIG> and <FIG> may include etching the underlying fin <NUM> to a depth between <NUM> nanometers and <NUM> nanometers (e.g., between <NUM> nanometers and <NUM> nanometers) and then filling the resulting trench with a conductive material. The device layer interconnects <NUM> of <FIG> and <FIG> may be readily integrated into existing process flows (e.g., in accordance with the fabrication techniques described above).

<FIG> illustrates an IC structure <NUM> including multiple different logic cells <NUM> (indicated by dashed boxes). A single fin <NUM> may span multiple logic cells <NUM>, and different logic cells <NUM> may be separated by isolation material <NUM> ("dummy gates"). Further, various frontside interconnects <NUM> may span multiple logic cells <NUM>; in <FIG>, interconnects 128A may selectively couple to S/D regions <NUM> (not shown) and the interconnects 128B may selectively couple to gate stacks <NUM> (not shown). For example, the interconnects 128A may be LITs. For ease of illustration, the detailed structure of most of the logic cells <NUM> is omitted, and only an example detailed structure for the cell <NUM>-<NUM> is shown in <FIG>. In particular, the cell <NUM>-<NUM> is shown as having an inverter structure in which one transistor 101A is a PMOS transistor having a S/D region <NUM> (not shown) coupled to an S/D region <NUM> (not shown) of an NMOS transistor 101B by vias <NUM> and an interconnect 128A-<NUM>. The gate stacks <NUM> of the PMOS transistor 101A and the NMOS transistor 101B are coupled by vias <NUM> and an interconnect 128B-<NUM>, another S/D region <NUM> (not shown, but under the interconnect 128A-<NUM>) of the transistor 101A is coupled to a positive voltage supply plane (e.g., Vcc) at the backside by a device layer interconnect 102A, and another S/D region <NUM> (not shown, but under the interconnect 128A-<NUM>) of the NMOS transistor 101B is coupled to a negative voltage supply plane (e.g., Vss) at the backside by a device layer interconnect 102B. The device layer interconnects <NUM> of <FIG> takes any of the forms discussed above with reference to <FIG> and <FIG>. During operation, an input to the logic cell <NUM>-<NUM> may be provided on the interconnect 128A-<NUM>, and the output of the logic cell <NUM>-<NUM> may be read at the interconnect 128B-<NUM>. In some embodiments in which a device layer interconnect <NUM> is positioned in a dummy gate region (one that would otherwise include an isolation material <NUM>), the device layer interconnect <NUM> may electrically couple two adjacent cells; for example, <FIG> illustrates that the logic cells <NUM>-<NUM> and <NUM>-<NUM> may be electrically coupled by their shared contact with the device layer interconnects <NUM>.

<FIG> illustrates a cross-sectional side view of a 3D IC <NUM> that includes a device layer interconnect <NUM>, in accordance with various embodiments.

The device layer interconnect <NUM> may be in a device layer <NUM> of the 3D IC, along with logic transistors. The device layer interconnect <NUM> is formed in a dummy gate region.

The 3D IC <NUM> may further include frontside interconnects <NUM> and backside interconnects <NUM> on opposite sides of the device layer <NUM>. The frontside interconnects <NUM> may be in respective interconnect layers, e.g., M1, M2, M3, M4, M5, and the backside interconnects <NUM> may be in respective backside interconnect layers, e.g., M-<NUM>, M-<NUM>, M-<NUM>. It will be apparent that other embodiments may have a different number of frontside interconnect layers and/or backside interconnect layers than the numbers of layers illustrated in <FIG>. The device layer interconnect <NUM> may electrically couple a frontside interconnect <NUM> (e.g., in frontside metal layer M1) with a backside interconnect <NUM> (e.g., in backside metal layer M-<NUM>). In some embodiments, a via <NUM> may electrically couple the device layer interconnect <NUM> to the frontside interconnect <NUM>, as shown. Additional vias <NUM> may electrically couple frontside interconnects <NUM> or backside interconnects <NUM> to other frontside interconnects <NUM> or backside interconnects <NUM> in different metal layers. Although a single device layer interconnect <NUM> is shown in <FIG>, the 3D IC <NUM> may include a plurality of device layer interconnects <NUM> in some embodiments. Further, a 3D IC <NUM> (or any other IC) may include any combination of the different types of device layer interconnects <NUM> disclosed herein. The 3D IC <NUM> (or any other IC) includes device layer interconnects in respective dummy gate regions.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors and/or device layer interconnects <NUM> of the device layer <NUM> through the front- and backside interconnect layers disposed on the device layer <NUM>. For example, electrically conductive features of the device layer <NUM> (e.g., the gate and the S/D contacts of a transistor, or the device layer interconnects <NUM>) may be electrically coupled with the interconnect structures of the interconnect layers. The device layer interconnects <NUM> may provide a conductive path between frontside interconnects and/or circuit devices and backside interconnects and/or circuit devices. The conductive path may be area-efficient while still providing a low resistance and capacitance. The device layer interconnects <NUM> may enable efficient high speed input/output (I/O) signals to be transferred across the device layer <NUM> of the 3D IC <NUM>. Interconnect structures may be arranged within the interconnect layers to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures depicted in <FIG>). In some embodiments, the interconnect structures may include lines and/or vias filled with an electrically conductive material such as a metal. The lines may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate upon which the device layer <NUM> is formed. For example, the lines may route electrical signals in a direction in and out of the page from the perspective of <FIG>. The vias may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate upon which the device layer <NUM> is formed. In some embodiments, the vias may electrically couple lines of different interconnect layers together. The interconnect layers may include one or more dielectric materials disposed between the interconnect structures. In some embodiments, the dielectric material disposed between the interconnect structures in different ones of the interconnect layers may have different compositions. Although the lines and the vias are structurally delineated with a line within each interconnect layer for the sake of clarity, the lines and the vias may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

The 3D IC <NUM> may include a solder resist material (e.g., polyimide or similar material) and one or more conductive contacts formed on the interconnect layers. In <FIG>, chip-level contacts <NUM> are illustrated as taking the form of solder bumps. The chip-level contacts <NUM> may be electrically coupled with the interconnect structures and configured to route the electrical signals of the transistors and the device layer interconnects <NUM> to other external devices (e.g., a circuit board or another IC).

The structures disclosed herein (e.g., the IC structures <NUM> or 3D ICs <NUM>) may be included in any suitable electronic component. <FIG> illustrate various examples of apparatuses that may include any of the structures disclosed herein.

<FIG> is a top view of a wafer <NUM> and dies <NUM> that may include one or more IC structures <NUM> or others of the structures disclosed herein. The wafer <NUM> may be composed of semiconductor material and may include one or more dies <NUM> having IC structures formed on a surface of the wafer <NUM>. Each of the dies <NUM> may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer <NUM> may undergo a singulation process in which the dies <NUM> are separated from one another to provide discrete "chips" of the semiconductor product. The die <NUM> may include one or more device layer interconnects <NUM> (e.g., in accordance with any of the embodiments disclosed herein), one or more transistors (e.g., in accordance with any of the embodiments disclosed herein), supporting circuitry to route electrical signals to the transistors and the device layer interconnects <NUM>, as well as any other IC components. In some embodiments, the wafer <NUM> or the die <NUM> may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die <NUM>. For example, a memory array formed by multiple memory devices may be formed on a same die <NUM> as a processing device (e.g., the processing device <NUM> of <FIG>) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

<FIG> is a cross-sectional side view of an example IC package <NUM> that may include a die that includes one or more device layer interconnects <NUM>, in accordance with any of the embodiments disclosed herein. The IC package <NUM> may include a die <NUM> coupled to the package substrate <NUM> via conductive contacts <NUM> of the die <NUM>, first-level interconnects <NUM>, and conductive contacts <NUM> of the package substrate <NUM>. The conductive contacts <NUM> may be coupled to conductive pathways <NUM> through the package substrate <NUM>, allowing circuitry within the die <NUM> to electrically couple to various ones of the conductive contacts <NUM> (or to other devices included in the package substrate <NUM>, not shown). The first-level interconnects <NUM> illustrated in <FIG> are solder bumps, but any suitable first-level interconnects <NUM> may be used. As used herein, a "conductive contact" may refer to a portion of conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket). The package substrate <NUM> may be formed of a dielectric material, and may have conductive pathways (including, e.g., vias and lines) extending through the dielectric material between the surface <NUM> and the surface <NUM>, or between different locations on the surface <NUM>, and/or between different locations on the surface <NUM>.

In some embodiments, an underfill material <NUM> may be disposed between the die <NUM> and the package substrate <NUM> around the first-level interconnects <NUM>, and a mold compound <NUM> may be disposed around the die <NUM> and in contact with the package substrate <NUM>. In some embodiments, the underfill material <NUM> may be the same as the mold compound <NUM>. Example materials that may be used for the underfill material <NUM> and the mold compound <NUM> are epoxy mold materials, as suitable. Second-level interconnects <NUM> may be coupled to the conductive contacts <NUM>. The second-level interconnects <NUM> illustrated in <FIG> are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects <NUM> may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects <NUM> may be used to couple the IC package <NUM> to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to <FIG>.

The die <NUM> may take the form of any of the embodiments of the die <NUM> discussed herein (e.g., may include any of device layer interconnects <NUM>, IC structures <NUM>, or 3D ICs <NUM> disclosed herein).

Although the IC package <NUM> illustrated in <FIG> is a flip chip package, other package architectures may be used. For example, the IC package <NUM> may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package <NUM> may be a wafer-level chip scale package (WLCSP) or a panel fanout (FO) package. Although a single die <NUM> is illustrated in the IC package <NUM> of <FIG>, an IC package <NUM> may include multiple dies <NUM>. An IC package <NUM> may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first surface <NUM> or the second surface <NUM> of the package substrate <NUM>. More generally, an IC package <NUM> may include any other active or passive components known in the art.

<FIG> is a cross-sectional side view of an IC device assembly <NUM> that may include one or more dies including one or more device layer interconnects <NUM>, IC structures <NUM>, or 3D ICs <NUM>, in accordance with any of the embodiments disclosed herein. The IC device assembly <NUM> includes a number of components disposed on a circuit board <NUM> (which may be, e.g., a motherboard). The IC device assembly <NUM> includes components disposed on a first surface <NUM> of the circuit board <NUM> and an opposing second surface <NUM> of the circuit board <NUM>; generally, components may be disposed on one or both faces <NUM> and <NUM>. Any of the IC packages discussed below with reference to the IC device assembly <NUM> may take the form of any of the embodiments of the IC package <NUM> discussed above with reference to <FIG>.

In some embodiments, the circuit board <NUM> may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board <NUM>. In other embodiments, the circuit board <NUM> may be a non-PCB substrate.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-interposer structure <NUM> coupled to the first surface <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may electrically and mechanically couple the package-on-interposer structure <NUM> to the circuit board <NUM>, and may include solder balls (as shown in <FIG>), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure <NUM> may include an IC package <NUM> coupled to an interposer <NUM> by coupling components <NUM>. The coupling components <NUM> may take any suitable form for the application, such as the forms discussed above with reference to the coupling components <NUM>. Although a single IC package <NUM> is shown in <FIG>, multiple IC packages may be coupled to the interposer <NUM>; indeed, additional interposers may be coupled to the interposer <NUM>. The interposer <NUM> may provide an intervening substrate used to bridge the circuit board <NUM> and the IC package <NUM>. The IC package <NUM> may be or include, for example, a die (the die <NUM> of <FIG>), an IC device (e.g., the IC device <NUM> of <FIG>), or any other suitable component. Generally, the interposer <NUM> may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer <NUM> may couple the IC package <NUM> (e.g., a die) to a set of BGA conductive contacts of the coupling components <NUM> for coupling to the circuit board <NUM>. In the embodiment illustrated in <FIG>, the IC package <NUM> and the circuit board <NUM> are attached to opposing sides of the interposer <NUM>; in other embodiments, the IC package <NUM> and the circuit board <NUM> may be attached to a same side of the interposer <NUM>. In some embodiments, three or more components may be interconnected by way of the interposer <NUM>.

In some embodiments, the interposer <NUM> may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer <NUM> may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer <NUM> may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The interposer <NUM> may further include embedded devices <NUM>, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer <NUM>. The package-on-interposer structure <NUM> may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly <NUM> may include an IC package <NUM> coupled to the first surface <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may take the form of any of the embodiments discussed above with reference to the coupling components <NUM>, and the IC package <NUM> may take the form of any of the embodiments discussed above with reference to the IC package <NUM>.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-package structure <NUM> coupled to the second surface <NUM> of the circuit board <NUM> by coupling components <NUM>. The package-on-package structure <NUM> may include an IC package <NUM> and an IC package <NUM> coupled together by coupling components <NUM> such that the IC package <NUM> is disposed between the circuit board <NUM> and the IC package <NUM>. The coupling components <NUM> and <NUM> may take the form of any of the embodiments of the coupling components <NUM> discussed above, and the IC packages <NUM> and <NUM> may take the form of any of the embodiments of the IC package <NUM> discussed above. The package-on-package structure <NUM> may be configured in accordance with any of the package-on-package structures known in the art.

<FIG> is a block diagram of an example electrical device <NUM> that may include one or more device layer interconnects <NUM>, IC structures <NUM>, or 3D ICs <NUM>, in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the electrical device <NUM> may include one or more of the IC packages <NUM>, IC devices <NUM>, or dies <NUM> disclosed herein. A number of components are illustrated in <FIG> as included in the electrical device <NUM>, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device <NUM> may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the electrical device <NUM> may not include one or more of the components illustrated in <FIG>, but the electrical device <NUM> may include interface circuitry for coupling to the one or more components. For example, the electrical device <NUM> may not include a display device <NUM>, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device <NUM> may be coupled. In another set of examples, the electrical device <NUM> may not include an audio input device <NUM> or an audio output device <NUM>, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device <NUM> or audio output device <NUM> may be coupled.

The electrical device <NUM> may include a processing device <NUM> (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device <NUM> may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device <NUM> may include a memory <NUM>, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory <NUM> may include memory that shares a die with the processing device <NUM>. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, the electrical device <NUM> may include a communication chip <NUM> (e.g., one or more communication chips). For example, the communication chip <NUM> may be configured for managing wireless communications for the transfer of data to and from the electrical device <NUM>. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium.

The communication chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE <NUM> family), IEEE <NUM> standards (e.g., IEEE <NUM>-<NUM> Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE <NUM> compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE <NUM> standards. The communication chip <NUM> may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip <NUM> may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip <NUM> may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The communication chip <NUM> may operate in accordance with other wireless protocols in other embodiments. The electrical device <NUM> may include an antenna <NUM> to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication chip <NUM> may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip <NUM> may include multiple communication chips. For instance, a first communication chip <NUM> may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip <NUM> may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip <NUM> may be dedicated to wireless communications, and a second communication chip <NUM> may be dedicated to wired communications.

The electrical device <NUM> may include battery/power circuitry <NUM>. The battery/power circuitry <NUM> may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device <NUM> to an energy source separate from the electrical device <NUM> (e.g., AC line power).

The electrical device <NUM> may include a display device <NUM> (or corresponding interface circuitry, as discussed above). The display device <NUM> may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device <NUM> may include an audio output device <NUM> (or corresponding interface circuitry, as discussed above). The audio output device <NUM> may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.

The electrical device <NUM> may include an audio input device <NUM> (or corresponding interface circuitry, as discussed above). The audio input device <NUM> may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The electrical device <NUM> may include a GPS device <NUM> (or corresponding interface circuitry, as discussed above). The GPS device <NUM> may be in communication with a satellite-based system and may receive a location of the electrical device <NUM>, as known in the art.

The electrical device <NUM> may include an other output device <NUM> (or corresponding interface circuitry, as discussed above). Examples of the other output device <NUM> may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The electrical device <NUM> may include an other input device <NUM> (or corresponding interface circuitry, as discussed above). Examples of the other input device <NUM> may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader. an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

Claim 1:
An integrated circuit ,IC, die (<NUM>; <NUM>), comprising:
a device layer (<NUM>) including a transistor array along a semiconductor fin (<NUM>);
a backside interconnect (<NUM>) on a backside of the device layer (<NUM>);
a device layer interconnect (<NUM>) in the device layer (<NUM>), electrically coupled to the backside interconnect (<NUM>), wherein the device layer interconnect (<NUM>) is in conductive contact with a first source/drain region (<NUM>) at a first surface of the device layer interconnect (<NUM>) and a second source/drain region (<NUM>) at a second, opposite surface of the device layer interconnect (<NUM>) along the semiconductor fin (<NUM>); and
S/D electrodes (<NUM>) on the first and second surfaces of the device layer interconnect (<NUM>) along the semiconductor fin (<NUM>);
characterized in that
the device layer interconnect (<NUM>) is in an isolation trench taking the place of a gate of the transistor array.