Patent Description:
MIS-BGA packaging architecture may be attractive for two factors. First, MIS-BGA architecture may have a relatively low profile (otherwise referred to as "z-height"). Additionally, MIS-BGA architecture may be a relatively low cost architecture as compared to architectures that use Prepreg or Ajinomoto Build-up Film (ABF) because MIS-BGA architecture may not require laser drilling and may use a low cost mold compound rather than the Prepreg or ABF materials.

In some legacy MIS-BGA packages, the process of manufacturing the MIS-BGA package may have included depositing a dry film resist (DFR) to serve as a mask, forming traces and/or pads on a substrate, and then removing the DFR. Subsequently, the process may have included at least partially covering the traces and/or pads with a second layer of dry film resist (DFR), for example, through lamination or some other process. A via may have then been lithe-defined through the DFR to the pad to at least partially expose the pad, and then copper may have been plated in the opening to form a plated copper via. Subsequent to this plating, the DFR may have been stripped and a mold compound may have been formed on the pads, traces, and copper via, which would then have to be ground and/or treated so that the surface of the mold was flush with the surface of the via for the subsequent layer formation.

While this technique may offer some cost advantages over ABF- based high density interconnection (HDI) substrate processing, the above described process may use two lithe-defined steps, one to create an underlying pad and the 2nd to create the via metal. Further, this process may limit the ability to create fine line and spacing (FLS) of copper traces, especially in all layers of the package. For example, it may be difficult to mass produce traces with a width of less than <NUM> microns and/or that are spaced less than <NUM> microns apart from one another (referred to herein as <NUM>/<NUM> LIS), since grinding of dielectric material of the package may be necessary to expose an embedded via inside of a mold compound of the package. Additionally, the above described grinding or surface treatment process may negatively impact reliability or structural stability of the MIS-BGA package. <CIT> discloses a circuit board fabrication method including forming first conductive interconnections onto an insulator substrate, and applying a resin film which is to be an interlevel insulator layer for electrically insulating the first conductive interconnection and a second conductive interconnection. <CIT> relates to a method of redistribution or rewiring a functional element. It discloses forming electrode pads on a functional element, forming a sacrificial layer pillar on the pad, and forming an insulating layer around the sacrificial layer pillars. <CIT> relates a hole formation method for producing an electronic circuit on a base material. It discloses a pillar formed on a first wiring base material, and an insulating film formed on the base material. D3 further discloses removing the pillar to form an opening.

Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

Embodiments herein may relate to an MIS-BGA package that has an FLS of less than <NUM>/<NUM> LIS. Generally, such a package may be the result of a manufacturing technique that includes the formation of one or more pads and/or traces on a substrate. A sacrificial element may be provided on at least one of the pads. A mold compound may be compression molded onto the package such that the face of the sacrificial element is generally flush with the face of the mold compound. The package may then be thermally treated such that the sacrificial element cleanly decomposes to gas to form a via.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that the description is not meant to be limiting, and that the invention is defined by the appended claims.

For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, Band C).

The term "coupled with," along with its derivatives, may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other.

In various embodiments, the phrase "a first layer formed on a second layer" may mean that the first layer is formed over the second layer, and at least a part of the first layer may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other layers between the first layer and the second layer) with at least a part of the second layer.

In various embodiments, the phrase "a first feature formed, deposited, or otherwise disposed on a second feature" may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

<FIG> is a top-down example of pads, traces, and vias, in accordance with various embodiments. Specifically, <FIG> depicts a top-down view of one layer of a package <NUM>. The package <NUM> may include a plurality of traces such as traces <NUM>, <NUM>, and <NUM>. In embodiments, the traces <NUM>/<NUM>/<NUM> may be copper, while in other embodiments the traces may be some other electrically and/or thermally conductive material. In embodiments, some of the traces such as traces <NUM> and <NUM> may be coupled with a pad such as <NUM> and <NUM>. In embodiments, the pads <NUM>/<NUM> may be constructed of a same or similar materials as the traces <NUM>/<NUM>/<NUM>. For example, the pads <NUM>/<NUM> may be constructed of copper. In other embodiments the pads <NUM>/<NUM> may be constructed of a different material than the traces <NUM>/<NUM>/<NUM>, for example, some other electrically and/or thermally conductive material.

As shown in <FIG>, in embodiments the pads <NUM>/<NUM> may have a larger footprint than the traces <NUM>/<NUM>/<NUM>, as will be discussed below. As discussed herein, footprint may generally refer to the lateral size of the element. Similarly, it can be seen that not all traces may be directly coupled with a pad. For example, trace <NUM> may not be coupled with a pad.

In some embodiments, the pads <NUM>/<NUM> may be coupled with one or more conductive vias such as vias <NUM> and <NUM>. As shown in <FIG>, in embodiments the vias <NUM>/<NUM> may have a smaller footprint than the pads <NUM>/<NUM>. That is, the vias <NUM>/<NUM> may have a smaller diameter than the pads <NUM>/<NUM>. The smaller diameter of the vias may be to provide a small margin of error during manufacturing such that if the via is not placed directly on the center of the pad, the via may not extend beyond the perimeter of the pad.

As shown in <FIG>, the package <NUM> may include a variety of measurements that may be referred to herein. For example, the distance between the center of the pads <NUM> and <NUM> may be a value depicted in <FIG> as "X. " Similarly, the traces <NUM>/<NUM>/<NUM> may have a width depicted in <FIG> as "Y. " Finally, the distance between the pads <NUM>/<NUM> and the trace <NUM> may be a value depicted in <FIG> as "Z. " Generally, the values for X, Y, and Z may be given on the order of microns. It will be understood that although the traces <NUM>/<NUM>/<NUM> are depicted as generally linear, and the pads <NUM>/<NUM> and vias <NUM>/<NUM> are depicted as generally circular, in other embodiments the traces, pads, and/or vias may have a different shape.

As discussed above, in legacy MIS-BGA packages, the values for Y and Z may be <NUM> microns, respectively, giving an FLS of <NUM>/<NUM> LIS. However, embodiments herein may have smaller values for Y and/or Z, which in turn may allow the value of X to decrease. For example, various embodiments may have a value for Y and/or Z on the order of approximately <NUM> microns or less.

Being able to achieve these smaller values for X, Y, and/or Z may provide significant benefits. For example, as performance demands on the MIS-BGA packages increase, it may be useful to provide more input/output (<NUM>/<NUM>) ports. However, with legacy MIS-BGA packages, the way to achieve these increased ports may be to add more layers to a package so that the number of traces and/or pads may be increased. However, adding more layers to a package may increase the cost and/or z-height of a package, which may be undesirable based on space and/or sales considerations. However, embodiments herein that allow for a smaller FLS may allow for more traces and/or pads to be placed in a layer of a package, thereby allowing an increased number of <NUM>/<NUM> ports without increasing cost and/or z-height.

<FIG> depicts various stages of manufacturing a package is such as package <NUM>, in accordance with various embodiments. Similar elements are numbered similarly through <FIG>, and every element of a given Figure may not be referred to herein with respect to each Figure for the sake of clarity and ease of explanation.

Initially, as shown in <FIG>, the package 290a may include a carrier panel <NUM> that may be referred to as a "peelable core". This carrier panel <NUM> may have different configurations in various embodiments.

In some embodiments, the carrier panel may include two copper layers that are separated by a weak layer that may allow for separation of a manufactured MIS-BGA substrate from the carrier. In the foregoing manner, at the end of the process a copper etch process may be used to remove the sacrificial copper layer, i.e. the copper layer that remains attached to the manufactured MIS-BGA substrate subsequent to separation of the substrate from the carrier. However, other embodiments may include two dielectric layers, or a dielectric layer and a copper layer to allow for peeling. In embodiments where the sacrificial material after peel is a dielectric material, a removal process such as wet-blast or some other removal process may be used to remove this dielectric material instead of the above-described copper etch process.

Initially, a seed layer <NUM> may be provided on the carrier panel <NUM>. The seed layer <NUM> may be copper or some other electrically and/or thermally conductive material. Dry film resist (DFR) portions <NUM>/<NUM> may then be provided on the seed layer <NUM>. In some embodiments, the DFR portions <NUM>/<NUM> may be laminated, deposited, etched, and/or formed according to some other process. In some embodiments, the DFR portions <NUM>/<NUM> may be laminated onto the seed layer, then masked and photo-defined.

Next, as shown in <FIG>, one or more pads such as pad <NUM> and one or more traces such as traces <NUM> may be formed on the package 290b. The pad <NUM> may be similar to pads <NUM> and <NUM>, and the traces <NUM> may be similar to traces <NUM>/<NUM>/<NUM>. In embodiments, the pad <NUM> and/or traces <NUM> may be formed via a plating process such as elytic plating. In embodiments the pad <NUM> and/or traces <NUM> may be formed of copper and/or some other electrically and/or thermally conductive material. In embodiments, the pad <NUM> and/or traces <NUM> may be formed of the same material or a different material than the seed layer <NUM>. Although the pad <NUM> and the traces <NUM> are shown as having roughly the same z-height in <FIG>, in other embodiments the pad <NUM> and one or more of the traces <NUM>, or the two traces <NUM>, may have different z-heights than one another.

Next, as shown in <FIG>, the DFR portions <NUM>/<NUM> may be exposed and developed from the package 290c to expose the pad <NUM> and the traces <NUM>. In embodiments, DFR portions <NUM>/<NUM> may be removed via various techniques such as etching, chemical removal, photo removal, drilling, or some other technique.

Subsequently, as shown in <FIG>, a sacrificial element <NUM> may be formed on the pad <NUM> of package 290d. In embodiments, the sacrificial element <NUM> may be shaped similarly to that of a via that is to be formed on pad <NUM>. For example, the sacrificial element <NUM> may have a shape similar to that of vias <NUM>/<NUM>. In embodiments, the sacrificial element <NUM> may be formed of Polynorbornene and/or a poly carbonate based polymer. Generally, the sacrificial element <NUM> may be a material that decomposes to a gas when exposed to a relatively high temperature. Such a temperature may be at or above <NUM>° Celsius (C) in some embodiments. In other embodiments, the temperature may be at or above <NUM>° C. Generally, the temperature may be based on considerations such as thermal requirements of other elements of the package, manufacturing processes for the package, or some other consideration.

The sacrificial element <NUM> may be provided on the pad <NUM> via stencil printing in embodiments that are related to low cost applications where there may be a margin for alignment of a via to the pad <NUM>. The sacrificial element <NUM> may be curtain coated, photo exposed, and developed in embodiments where very precise via to pad alignment is desired. In other embodiments the sacrificial element <NUM> may be provided on the pad according to one or more other processes or techniques.

Next, a mold compound <NUM> may be provided on the package 290e via compression molding as shown in <FIG>. The mold material used for the mold compound <NUM> may be an epoxy mold compound (EMC). In embodiments, the formulation of the EMC may be chosen as desired for a specific targeted application. In embodiments, compression molding may refer to providing the mold compound on the package 290e, and then compressing the package 290e in one or more directions. For example, as discussed below, in one embodiment the package 290e may be compressed at least by application of force to both the top and bottom (as depicted in <FIG>) of the package 290e. Compression molding is described in further detail below.

An advantage to compression molding may be that doing so may allow the surface of the mold compound <NUM> to be generally flush with the sacrificial element <NUM>, thereby reducing or eliminating the need for grinding of the mold compound <NUM> to expose the sacrificial element <NUM>. Reducing or eliminating the need for grinding may lower the cost and manufacturing complexity of the overall package.

As shown in <FIG> with respect to package 290f, the sacrificial element <NUM> may be thermally decomposed as described above (e.g., by application of heat) to a gas, leaving via <NUM>. For example, as described above, the thermal decomposition may include application of heat at or above <NUM>° C. In other embodiments, the thermal decomposition may include application of heat at or above <NUM>° C. In some embodiments, an additional cleaning step may be necessary to remove remnants of the sacrificial element <NUM> from the via <NUM>. In other embodiments, the sacrificial element <NUM> may fully decompose so the additional cleaning step may be un-necessary. In embodiments, the thermal decomposition may be the result of application of a directed heat source, while in other embodiments the thermal decomposition may be the result of generally heating the package 290e.

Subsequently, as shown in <FIG>, an additional seed layer <NUM>, which may be similar to seed layer <NUM>, may be applied to the package <NUM>. In embodiments, the seed layer <NUM> may be formed of the same material as seed layer <NUM>, traces <NUM>, and/or pad <NUM>. In other embodiments, the seed layer <NUM> may be formed of a different electrical and/or thermally conductive material.

As shown in <FIG>, additional DFR portions <NUM> and <NUM> may be formed on the package <NUM>. The DFR portions <NUM> and <NUM> may be similar to DFR portions <NUM> and/or <NUM>. In embodiments, the DFR portions <NUM> and <NUM> may be formed via lamination, masking with a photoresist material, and then photo exposure and development. In other embodiments, the DFR portions <NUM> and <NUM> may be formed via one or more different processes and/or techniques as described above with respect to DFR portions <NUM> and/or <NUM>.

Next, as shown in <FIG>, one or more pads such as pad <NUM> and one or more traces such as traces <NUM> may be formed on the package 290i. Similarly, the via <NUM> may be filled such that pad <NUM> and pad <NUM> are electrically and/or thermally coupled with one another by way of via <NUM>.

The pad <NUM> may be similar to pad <NUM> or pads <NUM> and <NUM>, and the traces <NUM> may be similar to traces <NUM> or traces <NUM>/<NUM>/<NUM>. In embodiments, the pad <NUM>, via <NUM>, and/or traces <NUM> may be formed via a plating process such as elytic plating. In embodiments the pad <NUM>, via <NUM>, and/or traces <NUM> may be formed of copper and/or some other electrically and/or thermally conductive material. In embodiments, the pad <NUM>, via <NUM>, and/or traces <NUM> may be formed of the same material or a different material than the seed layer <NUM>. Although the pad <NUM> and the traces <NUM> are shown as having roughly the same z-height in <FIG>, in other embodiments the pad <NUM> and one or more of the traces <NUM>, or the two traces <NUM>, may have different z-heights than one another.

Next, as shown in <FIG>, the DFR portions <NUM>/<NUM> may be stripped from the package 290j to expose the pad <NUM> and the traces <NUM>. As described above, the DFR portions <NUM>/<NUM> may be removed via various techniques such as etching, chemical removal, photo removal, drilling, or some other technique. Subsequently, as shown in <FIG>, the seed layer <NUM> may be at least partially removed from the package <NUM> such that the pad <NUM> and/or one or more of the traces <NUM> are electrically and/or thermally isolated from one another. Subsequently, further techniques such as those shown and discussed with respect to <FIG> may be performed to add additional layers to the package <NUM>. The number of iterations of adding a layer to a package may be based on various factors such as desired use, z-height specifications, the number of <NUM>/<NUM> ports necessary, or the lateral footprint of the package.

Once the desired number of layers are formed, at the Peelable interface of the Peelable core, followed by copper etch. Desired surface finish on the pads may then be performed, followed by bumping to finish the final package.

<FIG> depicts an example of compression molding such as that discussed above with respect to <FIG>. Specifically, <FIG> depicts a package 390e that may be similar to package 290e. The package 390e may be positioned between at least a top plate <NUM> and a bottom plate <NUM> of a mold chase. Release tape <NUM> may be positioned between the top plate <NUM> and the package 390e. As discussed above, the mold compound <NUM>, which may be similar to mold compound <NUM>, may be provided on the package 390e. The package 390e may then be compressed between the top and bottom plates <NUM>/<NUM> and the mold com pound <NUM> may then be cured or otherwise hardened while the package 390e is being compressed.

This compression may cause the surface of the mold compound <NUM> to be generally flush with the surface of the sacrificial element <NUM> when the package 390e is removed from between the mold plates <NUM>/<NUM>. In some embodiments, the compression molding process may also ensure that the sacrificial element <NUM> remains relatively still during the curing of the mold, thereby forming a good profile for a resultant via such as via <NUM>/<NUM>.

<FIG> depicts an alternate example structure of an MIS-BGA package <NUM>, in accordance with various embodiments. The package <NUM> may include a carrier panel <NUM> and seed layer <NUM>, which may be respectively similar to carrier panel <NUM> and seed layer <NUM>. The package <NUM> may further include a trace <NUM> and pads <NUM>, which may be respectively similar to trace(s) <NUM> and pad <NUM>. The package <NUM> may include a sacrificial element <NUM>, which may be similar to sacrificial element <NUM>, disposed on the pads <NUM>. The package <NUM> may further include a mold compound <NUM>, which may be similar to mold compound <NUM>.

As discussed with reference to <FIG>, the distance between the centers of the two pads <NUM> may be denoted herein as "X. " The width of the trace <NUM> may be denoted as "Y. " The distance between two elements, for example, pad <NUM> and trace <NUM>, may be denoted as "Z.

As discussed above, in legacy MIS-BGA packages, the pad to via alignment tolerances in lithe processes may require that any pad onto which a via is patterned has to be larger than the tolerance of alignment of the patterning process to ensure that the entire via lands on the pad. As a result large pads may be required, however the use of such large pads may limit the number of traces that can be routed on any given layer, thereby preventing the use of FLS interconnect layers. Consequently, depending on the alignment capability of lithe process, the number of FLS traces may be inherently limited in traditional MIS-BGA packages.

However, in embodiments described herein, a high precision inkjet printer may be used to place the sacrificial element similar to <NUM> and/or <NUM> precisely at the desired location using unit level alignment, thereby resulting in a tighter via to pad tolerance. This tighter tolerance may enable a smaller value of X as described herein. As a result, the underlying pad size may then be significantly reduced to enable FLS interconnects.

In other embodiments, sacrificial element similar to <NUM> and/or <NUM> can be curtain coated, photo exposed, and developed, which may result result in a tighter via to pad tolerance than was available in legacy packages. Further since the current embodiment may not require grinding of the mold compound to expose the via metal, the surface of the mold compound may not be inherently damaged thereby enabling significantly higher reliability and ability to pattern finer lines and spaces. Similarly, because multiple DFR stripping techniques may not be necessary for each layer, the overall cost and manufacturing complexity of the package may be reduced.

<FIG> depicts an example of one arrangement of a sacrificial element <NUM> and a pad <NUM>, in accordance with various embodiments. The sacrificial element <NUM> may be similar to sacrificial element <NUM> and/or <NUM>. The pad <NUM> may be similar to pad <NUM> and/or <NUM>.

In embodiments, the sacrificial element <NUM> may have walls that are entirely vertical. However, in other embodiments as shown in <FIG>, the walls of the sacrificial element <NUM> may be at least partially slanted such that the sacrificial element <NUM> tapers from the pad <NUM> to the face of the sacrificial element that is farthest from the pad <NUM>. The sacrificial element <NUM> of <FIG> is one such example of a tapered sacrificial element. The amount of tapering, if any, may be defined by process optimization. For example, if the sacrificial element <NUM> is stencil printed and/or photo-defined, then the resultant sacrificial element <NUM> may not be tapered at all.

<FIG> depicts an alternate example structure of an MIS-BGA package <NUM>, in accordance with various embodiments. The package <NUM> may include a substrate <NUM>, a seed layer <NUM>, one or more pads <NUM>, and a trace <NUM>, which may be respectively similar to substrate <NUM>, seed layer <NUM>, pads <NUM>, and/or trace <NUM>. Package <NUM> may further include a mold compound <NUM>, which may be similar to mold compound <NUM>. Package <NUM> may further include one or more pads <NUM> and a trace <NUM>, which may be respectively similar to pad <NUM> and traces <NUM>. In some embodiments, the package <NUM> may include one or more plated vias <NUM>, which may be similar to via <NUM>.

<FIG> depicts an example process flow for generating an MIS BGA package such as MIS-BGA packages <NUM>, <NUM>, and/or <NUM>. Specifically, <FIG> may relate to an iterative process for generating a plurality of layers of a package. Generally, the process flow of <FIG> will be described with reference to the packages depicted in <FIG>.

Initially, a mask may be provided on a substrate at <NUM>. The mask may include DFR portions such as DFR portions <NUM> or <NUM> that are included on seed layer <NUM> and/or carrier panel <NUM>.

Next, pads and/or traces such as pad <NUM> and traces <NUM> may be formed at <NUM>. In iterations, vias such as via <NUM> may additionally be formed at <NUM>. The pad(s), trace(s), and/or via(s) may be formed via a plating process as described above.

Subsequently, the mask may be removed at <NUM>. For example, DFR portions <NUM> and/or <NUM> may be removed as shown with respect to package 290c in <FIG>.

Next, sacrificial element such as sacrificial element <NUM> may be provided at <NUM>, as described above.

A mold compound such as mold compound <NUM> may be provided at <NUM>. The mold compound may be compression molded to the package as described above. Subsequently, the sacrificial element may be thermally decomposed at <NUM> as described above. Such thermal decomposition may result in the formation of a via such as via <NUM>.

A seed layer such as seed layer <NUM> may then be formed on the package at <NUM>, and then the process may iterate. A mask such as DFR portions <NUM> and <NUM> may be provided at <NUM>, and then further pads, traces, and/or vias such as pad <NUM>, traces <NUM>, and via <NUM> may be formed at <NUM>, and the DFR portions <NUM> and <NUM> may be removed at <NUM>.

The above described process may continue to iterate to generate further layers of a package. In other embodiments, the process may end with the removal of the DFR portions <NUM> and <NUM>. In some embodiments, a seed layer such as seed layer <NUM> and/or <NUM> may be removed subsequent to removing the mask at <NUM>. In some embodiments, pads and/or traces such as pad <NUM> and traces <NUM> may not be formed, and the process may end with the formation of the plated via <NUM> and removal of the mask at <NUM>.

As discussed above, once the desired number of layers are formed, the package may be released from the carrier panel at the Peelable interface of the Peelable core, followed by copper etch. Desired surface finish on the pads may then be performed, followed by bumping to finish the final package. <FIG> depicts one example of a <NUM>-layer MIS-BGA package <NUM>. It will be noted that not every element of <FIG> is labeled for the sake of clarity and legibility of the Figure, however where one element such as a contact <NUM> is described, it will be recognized that <FIG> may depict three such contacts <NUM>.

The package <NUM> may include three layers of a mold compound <NUM>, which may be similar to mold compound <NUM>. The package <NUM> may have a series of contacts <NUM> and <NUM> on opposite sides of the package <NUM>. In embodiments, the contacts <NUM> and <NUM> may be formed of solder which may include tin, lead, silver, copper, alloys thereof, or some other material. As shown in <FIG>, in some embodiments the contacts <NUM> may be larger than the contacts <NUM> (or vice-versa in other embodiments). Additionally, in some embodiments the contacts <NUM> and <NUM> may have a different pitch than one another. The different pitches may be due to a desired use of the package <NUM> as an interposer or some similar use. In other embodiments the contacts <NUM> and <NUM> may be the same size as one another, or have an identical pitch.

The package <NUM> may include one or more interconnects <NUM> that may extend through one or more of the three layers of mold compound <NUM> of the package. The interconnects may include, for example, a series of pads such as pads <NUM> or <NUM>, which may be electrically and/or thermally coupled by via <NUM>. Pads <NUM> and <NUM> and via <NUM> may be respectively similar to pads <NUM> and <NUM>, and via <NUM>. In some embodiments the package <NUM> may further include one or more traces such as trace <NUM>, which may be similar to trace <NUM>.

The interconnects such as interconnect <NUM> may electrically and/or thermally couple one or more of contacts <NUM> to one or more of contacts <NUM> through a series of pads and traces such as those described herein. Although a total of nine contacts <NUM>/<NUM> and three interconnects <NUM> are depicted in <FIG>, other embodiments may have more or less contacts or interconnects. Additionally, other embodiments may have more or less layers of mold compound835.

Generally, it will be understood that the specific configuration of pads and traces, including their number and relative position with respect to one another, is merely intended as one example. In other embodiments, a pad such as pad <NUM> may be directly coupled with a trace such as trace <NUM> by way of plated via <NUM>.

Embodiments of the present disclosure may be implemented into a system using any MIS-BGA packages that may benefit from the various manufacturing techniques disclosed herein. <FIG> schematically illustrates a computing device <NUM>, in accordance with some implementations, which may include one or more MIS-BGA packages such as packages <NUM>, <NUM>, and/or <NUM>. For example, various elements such as processor <NUM>, communication chip <NUM>, and/or some other component of the computing device <NUM> may be coupled with motherboard <NUM> by way of the above-described MIS-BGA packages.

The computing device <NUM> may be, for example, a mobile communication device or a desktop or rack-based computing device. The computing device <NUM> may house a board such as a motherboard <NUM>. The motherboard <NUM> may include a number of components, including (but not limited to) a processor <NUM> and at least one communication chip <NUM>. Any of the components discussed herein with reference to the computing device <NUM> may be arranged in or coupled with an MIS-BGA such as discussed herein. In further implementations, the communication chip <NUM> may be part of the processor <NUM>.

The computing device <NUM> may include a storage device <NUM>. In some embodiments, the storage device <NUM> may include one or more solid state drives. Examples of storage devices that may be included in the storage device <NUM> include volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory, ROM), flash memory, and mass storage devices (such as hard disk drives, compact discs (CDs), digital versatile discs (DVDs), and so forth).

Depending on its applications, the computing device <NUM> may include other components that may or may not be physically and electrically coupled to the motherboard <NUM>. These other components may include, but are not limited to, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and a camera.

The communication chip <NUM> and the antenna may enable wireless communications for the transfer of data to and from the computing device <NUM>. The communication chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE <NUM> family), IEEE <NUM> standards (e.g., IEEE <NUM>-<NUM> Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra-mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE <NUM> compatible broadband wide region (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE <NUM> standards. The communication chip <NUM> may operate in accordance with a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip <NUM> may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TOMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The communication chip <NUM> may operate in accordance with other wireless protocols in other embodiments.

For instance, a first communication chip <NUM> may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip <NUM> may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV -D0, and others. In some embodiments, the communication chip <NUM> may support wired communications. For example, the computing device <NUM> may include one or more wired servers.

The processor <NUM> and/or the communication chip <NUM> of the computing device <NUM> may include one or more dies or other components in an IC package. Such an IC package may be coupled with an interposer or another package using any of the techniques disclosed herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, an ultra-book, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data. In some embodiments, the recessed conductive contacts disclosed herein may be implemented in a high-performance computing device.

The following examples are provided as additional information. They are not to be construed as defining the invention. The invention is defined in the claims.

A provided example includes a method. The method includes providing, on a pad coupled with a carrier panel, a sacrificial element. The method further includes providing, on the pad, a mold compound, wherein the mold compound is at least partially adjacent to the sacrificial element. The method further includes removing, subsequent to the providing of the mold compound, the sacrificial element to form a via in the mold compound to at least partially expose the pad.

An example may include the method of other examples, wherein providing the mold compound includes providing the mold compound by way of compression molding.

An example may include the method of other examples, wherein the removing includes thermally decomposing the sacrificial element.

An example may include the method of other examples, wherein thermally decomposing the sacrificial element includes exposing the sacrificial element to a temperature sufficient to cause the sacrificial element to transition to a gas.

An example may include the method of other examples, wherein thermally decomposing the sacrificial element includes exposing the sacrificial element to a temperature above <NUM>° Celsius.

An example may include the method of other examples, wherein the pad is a first pad, the sacrificial element is a first sacrificial element, and the via is a first via. The method may include providing, on a further pad that is coupled with the carrier panel and adjacent to the first pad, a further sacrificial element that is adjacent to the first sacrificial element. The method may further include removing the further sacrificial element to form a further via in the mold compound to at least partially expose the further pad.

An example may include the method of other examples, wherein the pad is less than <NUM> microns from a trace that is coupled with the carrier panel and separate from the pad.

An example may include the method of other examples, wherein the trace has a width that is less than <NUM> microns as measured in a direction parallel to a face of the carrier panel that is coupled with the pad.

An example may include the method of other examples, wherein the pad and the trace include copper.

An example may include the method of other examples, wherein the sacrificial element is a poly carbonate based polymer.

An example may include the method of other examples, wherein the sacrificial element is Polynorborene based polymer.

An example may include the method of other examples, wherein the pad is a first pad, the sacrificial element is a first sacrificial element, the via is a first via, and the mold compound is a first mold compound. The method may further include providing a second pad such that the first mold compound is at least partially between the second pad and the carrier panel. The method may further include providing, on the second pad, a second sacrificial element; providing, on the second sacrificial element, a second mold compound wherein the second mold compound is at least partially adjacent to the second sacrificial element. The method may further include and removing the second sacrificial element to form a second via in the second mold compound to at least partially expose the second pad.

An example may include the method of other examples, further including at least partially filling the first via with an electrically conductive material via a plating process. The method may further include providing the second pad at least partially on the electrically conductive material.

An example may include the method of other examples, wherein providing the sacrificial element includes stencil printing, photo defining, ink jet placing, spin-on coating, or dry etch patterning the sacrificial element on the pad.

An example may include a package. The package includes a pad and a trace that is separate from, and adjacent to, the pad such that the pad and the trace are less than <NUM> microns from each other. The package further includes a mold compound at least partially disposed on the pad, and the trace. The package further includes a plated via coupled with the pad through the mold compound.

An example may include the package of other examples, wherein the mold s compound includes epoxy.

An example may include the package of other examples, wherein the trace has a width of less than <NUM> microns as measured in a plane parallel to a face of the mold compound.

An example may include the package of other examples, wherein the package is a mold interconnect system (MIS) ball grid array (BGA) package.

An example may include the package of other examples, wherein the pad and the trace include copper.

Claim 1:
A method for forming a mold interconnect system ball grid array package, MIS-BGA, the method comprising:
providing (<NUM>) a sacrificial element on a pad of the MIS-BGA package to be formed, the pad coupled with a carrier panel;
providing (<NUM>), on the pad, a mold compound of the MIS-BGA package to be formed, wherein the mold compound is at least partially adjacent to the sacrificial element; and
removing (<NUM>), subsequent to the providing of the mold compound, the sacrificial element to form a via in the mold compound to at least partially expose the pad;
at least partially filling the via with an electrically conductive material via a plating process to form a plated via interconnect of the MIS-BGA package to be formed, the plated via interconnect coupled with the pad through the mold compound; and
releasing the MIS-BGA package to be formed from the carrier panel.