Patent Description:
The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

<CIT> discloses that a nonvolatile semiconductor memory device, is formed in particular parallel pattern of the control gate electrode and the source region, the pattern of the erase gate electrodes and intersect with these patterns according to EEPROM having the formed memory cells.

<CIT> A1 discloses that a semiconductor memory device includes a memory cell array, first bit lines, second bit lines, a first precharge circuit, a sense amplifier, and a read control circuit. The memory cell array has a first cell array including first memory cells arranged in a matrix and a second cell array including second memory cells. The first bit line electrically connects the first memory cells in a same column. The second bit line electrically connects the second memory cells in a same column. The first precharge circuit precharges the first bit lines in a read operation. The sense amplifier amplifies the data read from the first memory cells in a read operation. The read control circuit precharges and discharges the second bit lines in a read operation and, on the basis of the time required to precharge and discharge the second bit lines, controls the first precharge circuit and the sense amplifier.

<CIT> A1 discloses a method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.

<CIT> discloses that a row decoder circuit includes a decoding unit and first and second wordline driving units. The decoding unit generates a first driving signal and a second driving signal based on a selection signal and wordline voltages. A voltage level of the first driving signal and a voltage level of the second driving signal depend on an operation mode. The first wordline driving unit is connected to a first wordline and outputs one of the first driving signal and the second driving signal as a first wordline driving signal based on first driving control signals. The second wordline driving unit is connected to a second wordline and outputs one of the first driving signal and the second driving signal as a second wordline driving signal based on second driving control signals.

<CIT> discloses a non- volatile memory device that a semiconductor substrate of a first conductivity type. An array of non- volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.

<CIT> discloses a nonvolatile semiconductor memory device which comprises a memory cell array having a plurality of memory blocks each divided into a plurality of segments, each of which has a plurality of word lines, a plurality of bit lines arranged to intersect the word lines, and a plurality of memory cells connected to the word lines and the bit lines. The device has means for decoding segment select signals to generate a decode signal that selects one of the segments, and means connected to a first power node, for receiving word line select signals to select one of the word lines in the selected segment to output a first voltage applied to the first power node. In the nonvolatile semiconductor memory device, furthermore, a word line driver, which is connected to a second power node, applies the first voltage to the selected word line during read, write, and test modes of operation, and applies a second voltage supplied to the second power node to the selected word line during an erase mode of operation, in response to the decoded signal from the decoding means.

Non-volatile memory cells are well known in the art. One prior art non-volatile split gate memory cell <NUM>, which contains five terminals, is shown in <FIG>. Memory cell <NUM> comprises semiconductor substrate <NUM> of a first conductivity type, such as P type. Substrate <NUM> has a surface on which there is formed a first region <NUM> (also known as the source line SL) of a second conductivity type, such as N type. A second region <NUM> (also known as the drain line) also of N type is formed on the surface of substrate <NUM>. Between the first region <NUM> and the second region <NUM> is channel region <NUM>. Bit line BL <NUM> is connected to the second region <NUM>. Word line WL <NUM> is positioned above a first portion of the channel region <NUM> and is insulated therefrom.

<NUM> has little or no overlap with the second region <NUM>. Floating gate FG <NUM> is over another portion of channel region <NUM>. Floating gate <NUM> is insulated therefrom, and is adjacent to word line <NUM>. Floating gate <NUM> is also adjacent to the first region <NUM>. Floating gate <NUM> may overlap the first region <NUM> to provide coupling from the first region <NUM> into floating gate <NUM>. Coupling gate CG (also known as control gate) <NUM> is over floating gate <NUM> and is insulated therefrom. Erase gate EG <NUM> is over the first region <NUM> and is adjacent to floating gate <NUM> and coupling gate <NUM> and is insulated therefrom. The top corner of floating gate <NUM> may point toward the inside corner of the T-shaped erase gate <NUM> to enhance erase efficiency. Erase gate <NUM> is also insulated from the first region <NUM>. Memory cell <NUM> is more particularly described in <CIT>.

One exemplary operation for erase and program of prior art non-volatile memory cell <NUM> is as follows. Memory cell <NUM> is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on erase gate <NUM> with other terminals equal to zero volt. Electrons tunnel from floating gate <NUM> into erase gate <NUM> causing floating gate <NUM> to be positively charged, turning on the cell <NUM> in a read condition. The resulting cell erased state is known as '<NUM>' state.

Memory cell <NUM> is programmed, through a source side hot electron programming mechanism, by applying a high voltage on coupling gate <NUM>, a high voltage on source line <NUM>, a medium voltage on erase gate <NUM>, and a programming current on bit line <NUM>. A portion of electrons flowing across the gap between word line <NUM> and floating gate <NUM> acquire enough energy to inject into floating gate <NUM> causing the floating gate <NUM> to be negatively charged, turning off the cell <NUM> in a read condition. The resulting cell programmed state is known as '<NUM>' state.

Memory cell <NUM> is read in a Current Sensing Mode as following: A bias voltage is applied on bit line <NUM>, a bias voltage is applied on word line <NUM>, a bias voltage is applied on coupling gate <NUM>, a bias or zero voltage is applied on erase gate <NUM>, and a ground is applied on source line <NUM>. There exists a cell current flowing from bit line <NUM> to source line <NUM> for an erased state and there is insignificant or zero cell current flow from the bit line <NUM> to the source line <NUM> for a programmed state. Alternatively, memory cell <NUM> can be read in a Reverse Current Sensing Mode, in which bit line <NUM> is grounded and a bias voltage is applied on source line <NUM>. In this mode the current reverses the direction from source line <NUM> to bitline <NUM>.

Memory cell <NUM> alternatively can be read in a Voltage Sensing Mode as following: A bias current (to ground) is applied on bit line <NUM>, a bias voltage is applied on word line <NUM>, a bias voltage is applied on coupling gate <NUM>, a bias voltage is applied on erase gate <NUM>, and a bias voltage is applied on source line <NUM>. There exists a cell output voltage (significantly >0V) on bit line <NUM> for an erased state and there is insignificant or close to zero output voltage on bit line <NUM> for a programmed state. Alternatively, memory cell <NUM> can be read in a Reverse Voltage Sensing Mode, in which bit line <NUM> is biased at a bias voltage and a bias current (to ground) is applied on source line <NUM>. In this mode, memory cell <NUM> output voltage is on the source line <NUM> instead of on the bit line <NUM>.

In the prior art, various combinations of positive or zero voltages were applied to word line <NUM>, coupling gate <NUM>, and floating gate <NUM> to perform read, program, and erase operations.

In response to the read, erase or program command, the logic circuit <NUM> (in <FIG>) causes the various voltages to be supplied in a timely and least disturb manner to the various portions of both the selected memory cell <NUM> and the unselected memory cells <NUM>.

For the selected and unselected memory cell <NUM>, the voltage and current applied are as follows. As used hereinafter, the following abbreviations are used: source line or first region <NUM> (SL), bit line <NUM> (BL), word line <NUM> (WL), and coupling gate <NUM> (CG).

In a recent application by the applicant-<CIT>, the applicant disclosed an invention whereby negative voltages could be applied to word line <NUM> and/or coupling gate <NUM> during read, program, and/or erase operations. In this embodiment, the voltage and current applied to the selected and unselected memory cell <NUM>, are as follows.

In another embodiment of <CIT>, negative voltages can be applied to word line <NUM> when memory cell <NUM> is unselected during read, erase, and program operations, and negative voltages can be applied to coupling gate <NUM> during an erase operation, such that the following voltages are applied:.

The CGINH signal listed above is an inhibit signal that is applied to the coupling gate <NUM> of an unselected cell that shares an erase gate <NUM> with a selected cell.

<FIG> depicts an embodiment recently developed by applicant of an architecture for a flash memory system comprising die <NUM>. Die <NUM> comprises: memory array <NUM> and memory array <NUM> for storing data, memory arrays <NUM> and <NUM> comprising rows and columns of memory cells of the type described previously as memory cell <NUM> in <FIG>, pad <NUM> and pad <NUM> for enabling electrical communication between the other components of die <NUM> and, typically, wire bonds (not shown) that in turn connect to pins (not shown) or package bumps that are used to access the integrated circuit from outside of the packaged chip or macro interface pins (not shown) for interconnecting to other macros on a SOC (system on chip); high voltage circuit <NUM> used to provide positive and negative voltage supplies for the system; control logic <NUM> for providing various control functions, such as redundancy and built-in self-testing; analog circuit <NUM>; sensing circuits <NUM> and <NUM> used to read data from memory array <NUM> and memory array <NUM>, respectively; row decoder circuit <NUM> and row decoder circuit <NUM> used to access the row in memory array <NUM> and memory array <NUM>, respectively, to be read from or written to; column decoder circuit <NUM> and column decoder circuit <NUM> used to access bytes in memory array <NUM> and memory array <NUM>, respectively, to be read from or written to; charge pump circuit <NUM> and charge pump circuit <NUM>, used to provide increased voltages for program and erase operations for memory array <NUM> and memory array <NUM>, respectively; negative voltage driver circuit <NUM> shared by memory array <NUM> and memory array <NUM> for read and write operations; high voltage driver circuit <NUM> used by memory array <NUM> during read and write operations and high voltage driver circuit <NUM> used by memory array <NUM> during read and write operations.

With flash memory systems becoming ubiquitous in all manner of computing and electronic devices, it is increasingly important to create designs that reduce the amount of die space required per memory cell and to reduce the overall complexity of decoders use in flash memory systems. What is needed is flash memory cell design that utilizes fewer terminals than in the prior art and simplified circuitry for operating flash memory cells that follow that design.

The present invention is defined in independent device claim <NUM>.

Preferred embodiments are defined in dependent claims <NUM>-<NUM>.

<FIG> depicts an embodiment of an improved flash memory cell <NUM>. As with prior art flash memory cell <NUM>, flash memory cell <NUM> comprises substrate <NUM>, first region (source line) <NUM>, second region <NUM>, channel region <NUM>, bit line <NUM>, word line <NUM>, floating gate <NUM>, and erase gate <NUM>. Unlike prior art flash memory cell <NUM>, flash memory cell <NUM> does not contain a coupling gate or control gate and only contains four terminals - bit line <NUM>, word line <NUM>, erase gate <NUM>, and source line <NUM>. This significantly reduces the complexity of the circuitry, such as decoder circuitry, required to operate an array of flash memory cells.

The erase operation (erasing through erase gate) and read operation are similar to that of the <FIG> except there is no control gate bias. The programming operation also is done without the control gate bias, hence the program voltage on the source line is higher to compensate for lack of control gate bias.

Table No. <NUM> depicts typical voltage ranges that can be applied to the four terminals for performing read, erase, and program operations:.

<FIG> depicts a symbolic representation <NUM> of flash memory cell <NUM>. Symbolic representation <NUM> comprises symbols for the four terminals of flash memory cell <NUM>, namely, bit line <NUM>, word line <NUM>, erase gate <NUM>, and source line <NUM>.

<FIG> depicts an embodiment of an architecture for a flash memory system comprising die <NUM>. Die <NUM> comprises memory arrays <NUM>, <NUM>, <NUM>, and <NUM>, for storing data, each of memory arrays <NUM>, <NUM>, <NUM>, and <NUM> comprising rows and columns of memory cells of the type described previously as flash memory cell <NUM> in <FIG>. Die <NUM> further comprises sensing circuit <NUM> used to read data from memory arrays <NUM>, <NUM>, <NUM>, and <NUM>; row decoder circuit <NUM> used to access the selected row in memory arrays <NUM> and <NUM> and row decoder circuit <NUM> used to access the selected row in memory arrays <NUM> and to be read from or written to; column decoder circuits <NUM>, <NUM>, <NUM>, and <NUM> used to access bytes in memory arrays <NUM>, <NUM>, <NUM>, and <NUM>, respectively, to be read from or written to; high voltage row decoder WSHDR <NUM>, <NUM>, <NUM>, and <NUM> used to provide high voltage to one or more terminals of the selected memory cell within memory arrays <NUM>, <NUM>, <NUM>, and <NUM>, respectively, depending on the operation being performed.

Die <NUM> further comprises the following functional structures and sub-systems: macro interface pins ITFC pin <NUM> for interconnecting to other macros on a SOC (system on chip); low voltage generation (including a low voltage charge pump circuit) circuits <NUM> and high voltage generation (including a high voltage charge pump circuit) circuit <NUM> used to provide increased voltages for program and erase operations for memory arrays <NUM>, <NUM>, <NUM>, and <NUM>; analog circuit <NUM> used by analog circuitry on die <NUM>; digital logic circuit <NUM> used by digital circuitry on die <NUM>.

<FIG> depicts row decoder <NUM> for <NUM> word lines in a sector within a memory array (such as memory array <NUM>, <NUM>, <NUM>, and <NUM>). Row decoder <NUM> can be part of row decoder circuits <NUM> and <NUM> in die <NUM>. Row decoder <NUM> comprises NAND gate <NUM>, which receives pre-decoded address signals, here shown as lines XPA, XPB, XPC, and XPD, which select a sector within a memory array. When XPA, XPB XPC, and XPD are all "high," then the output of NAND gate <NUM> will be "low" and this particular sector will be selected.

Row decoder <NUM> further comprises inverter <NUM>, decoder circuit <NUM> to generate word line WL0, decoder circuit <NUM> to generate WL7, as well as additional decoder circuits (not shown) to generate word lines WL1, WL2, WL3, WL4, WL5, and WL6.

Decoder circuit <NUM> comprises PMOS transistors <NUM>, <NUM>, and <NUM> and NMOS transistors <NUM> and <NUM>, configured as shown. Decoder circuit <NUM> receives the output of NAND gate <NUM>, the output of inverter <NUM>, and pre-decoded address signal XPZB0. When this particular sector is selected and XPZB0 is "low," then WL0 will be asserted. When XPZB0 is "high," then WL0 will not be asserted.

Similarly, decoder circuit <NUM> comprises PMOS transistors <NUM>, <NUM>, and <NUM> and NMOS transistors <NUM> and <NUM>, configured as shown. Decoder circuit <NUM> receives the output of NAND gate <NUM>, the output of inverter <NUM>, and pre-decoded address signal XPZ70. When this particular sector is selected and XPZB7 is "low," then WL7 will be asserted. When XPZB7 is "high," then WL7 will not be asserted.

It is to understood that the decoder circuits (now shown) for WL1, WL2, and WL3, WL4, WL5, and WL6 will follow the same design as decoder circuits <NUM> and <NUM> except that they will receive the inputs XPZB1, XPZB2, XPZB3, XPZB4, XPZB5, and XPZB6, respectively, instead of XPZB0 or XPZB7.

In the situation where this sector is selected and it is desired for WL0 to be asserted, the output of NAND gate <NUM> will be "low," and the output of inverter will be "high. " PMOS transistor <NUM> will be turned on, and the node between PMOS transistor <NUM> and NMOS transistor <NUM> will receive the value of XPZB0, which will be "low" when word line WL0 is to be asserted. This will turn on PMOS transistor <NUM>, which will pull WL0 "high" to ZVDD which indicates an asserted state. In this instance, XPZB7 is "high," signifying that WL7 is to be not asserted, which will pull the node between PMOS transistor <NUM> and NMOS transistor <NUM> to the value of XPZB7 (which is "high"), which will turn on NMOS transistor <NUM> and cause WL to be "low," which indicates a non-asserted state. In this manner, one of the word lines WL0. WL7 can be selected when this sector is selected.

<FIG> depicts high voltage row decoder <NUM>. It will be recalled that in the embodiments of this invention, high voltage signals (e.g., <NUM>-9V for the source line during a programming operation) are required to compensate for the lack of a coupling gate in the flash memory cells. High voltage decoder <NUM> comprises high voltage level shift enable circuit <NUM>, erase gate decoder <NUM>, and source line decoder <NUM>.

High voltage level shift enable circuit <NUM> comprises high voltage level shift circuit <NUM> and low voltage latch <NUM>. Low voltage latch <NUM> receives word line (WL), enable (EN), and reset (RST) as input signals and outputs sector enable signal (SECEN) and sector enable signal bar (SECEN_N). Sector enable signal (SECEN) is provided as an input to high voltage level shift circuit <NUM>, which outputs sector enable signal high voltage (SECEN_HV0. SECEN_HVN for N sectors) and sector enable signal high voltage bar (SECEN_HV0_N. SECEN_HVN_N for N sectors).

Erase gate decoder <NUM> comprises erase gate decoder <NUM> for row <NUM> in the sector, and similar erase gate decoders (not shown) for rows <NUM>,. ,N in the sector. Here, erase gate decoder <NUM> receives the sector enable signal high voltage (SECEN_HV0) from high voltage level shift circuit <NUM>, its complement (SECEN_HV0_N), a voltage erase gate supply (VEGSUP), a low voltage erase gate supply (VEGSUP_LOW),sector enable signal (SECEN), and its complement (SECEN_N). Thus, the output EG0 of erase gate decoder <NUM> can be at one of three different voltage levels: SECEN_HV0 (high voltage), VEGSUP (normal voltage), or VEGSUP_LOW (low voltage).

Similarly, source line decoder <NUM> comprises source line decoder <NUM> for row <NUM> in the sector, and similar source line decoders (not shown) for rows <NUM>,. ,N in the sector. Here, source line decoder <NUM> receives sector enable signal high voltage (SECEN_HV0) from high voltage level shift circuit <NUM>, its complement (SECEN_HV0_N), a voltage source line supply (VSLSUP), a low voltage source line supply (VSLSUP_LOW), sector enable signal (SECEN), and its complement (SECEN_N). Thus, the output SL0 of source line decoder <NUM> can be at one of three different voltage levels: SECEN_HV0 (high voltage), VSLSUP (normal voltage), or VSLSUP_LOW (low voltage).

<FIG> shows erase gate decoder <NUM>, which is an embodiment of erase gate decoder <NUM>. Erase gate decoder <NUM> comprises NMOS transistor <NUM> and PMOS transistors <NUM> and <NUM>, configured as shown. PMOS transistor <NUM> is a current limiter with EGHV_BIAS as a current mirror bias level. When this erase gate signal (EG) is to be asserted, EN_HV_N will be low (e.g., 0V or <NUM>. 2V or <NUM>. 5V), which will turn on PMOS transistor <NUM> and turn off NMOS transistor <NUM>, which will cause erase gate (EG) to be high (i.e. = VEGSUP, for example <NUM>. When this erase gate signal (EG) is to be not asserted, EN_HV_N will be high, which will turn off PMOS transistor <NUM> and turn on NMOS transistor <NUM>, which will cause erase gate (EG) to be low (i.e., = VEGSUP_LOW level, for example 0v or <NUM>. 2V or <NUM>.

<FIG> shows erase gate decoder <NUM>, which another embodiment of erase gate decoder <NUM>. Erase gate decoder <NUM> comprises NMOS transistor <NUM> and PMOS transistor <NUM>. Erase gate decoder <NUM> in this example does not contain a current limiter. When this erase gate signal (EG) is to be asserted, EN_HV_N will be low (e.g., 0V or <NUM>. 2V), which will turn on PMOS transistor <NUM> and turn off NMOS transistor <NUM>, which will cause erase gate (EG) to be high. When this erase gate signal (EG) is to be not asserted, EN_HV_N will be high, which will turn off PMOS transistor <NUM> and turn on NMOS transistor <NUM>, which will cause erase gate (EG) to be low (e.g., 0V or <NUM>. 2V or <NUM>.

<FIG> shows erase gate decoder <NUM>, which is another embodiment of erase gate decoder <NUM> that uses only PMOS transistors. Erase gate decoder <NUM> comprises PMOS transistors <NUM> and <NUM>, which share a common well. Erase gate decoder <NUM> in this example does not contain a current limiter. When this erase gate signal (EG) is to be asserted, EN_HV_N will be low and EN_HV will be high, which will turn on PMOS transistor <NUM> and turn off PMOS transistor <NUM>, which will cause erase gate (EG) to be high. When this erase gate signal (EG) is to be not asserted, EN_HV_N will be low and EN_HV will be high, which will turn off PMOS transistor <NUM> and turn on PMOS transistor <NUM>, which will cause erase gate (EG) to be low (e.g., 0V or <NUM>. 2V or <NUM>.

<FIG> shows source line decoder <NUM>, which is an embodiment of source line decoder <NUM>. Source line decoder <NUM> comprises NMOS transistors <NUM>, <NUM>, <NUM>, and <NUM>, configured as shown. NMOS transistor <NUM> pulls the source line (SL) low during a read operation in response to the SLRD_EN signal. NMOS transistor <NUM> pulls the source line (SL) low during a programming operation in response to the SLP_EN signal. NMOS transistor <NUM> performs a monitoring function, through output VSLMON. NMOS transistor <NUM> provides a voltage to source line (SL) in response to the EN_HV signal.

<FIG> shows source line decoder <NUM>, which is another embodiment of source line decoder <NUM>. Source line decoder <NUM> comprises NMOS transistors <NUM>, <NUM>, and <NUM>, configured as shown. NMOS transistor <NUM> pulls the source line (SL) low during a programming operation in response to the SLP_EN signal. NMOS transistor <NUM> performs a monitoring function, through output VSLMON. NMOS transistor <NUM> provides a voltage to source line (SL) in response to the EN_HV signal.

<FIG> shows source line decoder <NUM>, which is another embodiment of source line decoder <NUM>. Source line decoder <NUM> comprises NMOS transistors <NUM> and <NUM>, configured as shown. NMOS transistor <NUM> pulls the source line (SL) low during a programming operation in response to the SLP_EN signal. NMOS transistor <NUM> provides a voltage to source line (SL) in response to the EN_HV signal.

<FIG> shows source line decoder <NUM>, which is another embodiment of source line decoder <NUM> that uses only PMOS transistors. Source line decoder <NUM> comprises PMOS transistors <NUM>, <NUM>, and <NUM>, configured as shown. PMOS transistor <NUM> pulls the source line (SL) low during a programming operation in response to the EN_HV signal. PMOS transistor <NUM> performs a monitoring function, through output VSLMON. PMOS transistor <NUM> provides a voltage to source line (SL) in response to the EN_HV_N signal.

<FIG> depicts source line decoder <NUM>, which is another embodiment of source line decoder <NUM> that is a variation of source line decoder <NUM> in <FIG>. Source line decoder comprises source line decoder <NUM>. The source line (SL) of source line decoder <NUM> is connected to the source line <NUM> of selected memory cell <NUM> and source line <NUM> of a dummy memory cell <NUM> during read operations. Dummy memory cell <NUM> follows the same construction as selected memory cell <NUM>, which can be based on the design of memory cell <NUM>, except that dummy memory cell <NUM> is not used to store data.

<FIG> shows additional detail regarding selected memory cell <NUM> and dummy memory cell <NUM>. When selected memory cell <NUM> is in read mode or erase mode, source line <NUM> and source line <NUM> are coupled to ground through dummy memory cell <NUM> and dummy bitline <NUM> which is coupled to ground. Dummy memory cell <NUM> is required to be erased before read operation. This will pull source line <NUM> and source line <NUM> to ground.

When selected memory cell <NUM> is in program mode, bitline <NUM> is coupled to an inhibit voltage such as VDD. This will place dummy memory cell <NUM> in a program inhibit mode which will maintain dummy memory cell <NUM> in am erased state. A plurality of the dummy cells, such as dummy memory cell <NUM>, can be connected to memory cell <NUM> through their source lines to strengthen the pull down of the source line <NUM> to ground.

<FIG> depicts control gate decoder <NUM>, which is a control gate decoder that can be used with the prior art design of <FIG>, and which is not needed in the embodiments of <FIG>. Control gate decoder <NUM> comprises NMOS transistor <NUM> and PMOS transistor <NUM>. NMOS transistor <NUM> will pull down the control gate signal (CG) in response to the signal EN_HV_N. PMOS transistor <NUM> will pull up the control gate signal (CG) in response to the signal EN_HV_N.

<FIG> depicts control gate decoder <NUM> that uses only PMOS transistors, which is another embodiment of a control gate decoder that can be used with the prior art design of <FIG>, and which is not needed in the embodiments of <FIG>. Control gate decoder <NUM> comprises PMOS transistors <NUM> and <NUM>. PMOS transistor <NUM> will pull down the control gate signal (CG) in response to the signal EN_HV. PMOS transistor <NUM> will pull up the control gate signal (CG) in response to the signal EN_HV_N.

<FIG> depicts EG/CG/SL gate decoder <NUM>, that can be used with the prior art design of <FIG>, and in the embodiments of <FIG>, thus showing the amount of space saved through the present invention. Gate decoder <NUM> comprises PMOS transistors <NUM>. PMOS transistor <NUM> will pull low the gate signal (EG/CG/SL) high in response to the signal EN_HV_N. If EN_HV_N is not asserted, then the value of EG/CG/SL will float. The EG/CG/SL gate is pre-charged to a low bias level first before being enabled to a high voltage level.

<FIG> depicts latch voltage level shifter <NUM> with adaptive high voltage VH and low VL supplies. Latch voltage level shifter comprises a latch comprising inverters <NUM> and <NUM> and NMOS transistors <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, in the configuration shown. Latch voltage level shifter receives input <NUM> to reset (input RST_SECDEC) and input <NUM> to set, meaning enabling, (inputs WL0 and SET_SECDEC) and produces output <NUM> and <NUM>. Latch voltage level shifter will adaptively change the magnitudes of a "high" voltage or a "low" voltage to minimize the voltage stress. The latch inverters <NUM> and <NUM> received power supply high VH and power supply low VL. Initially when enabling by the inputs <NUM>/<NUM>, VH is Vdd, e.g. <NUM>. 2V, and VL is gnd. Then VH starts to ramp up to an intermediate VH level, e.g. 5V. At this VH level, VL then ramps to an intermediate VL level, e.g., <NUM>. After VL reached the intermediate VL level, VH then ramps to final high voltage supply VHVSUP level, e.g., <NUM>. At this point, the voltage across the inverters is only <NUM>. 5V=9V, hence reducing the voltage stress across them.

<FIG> depicts latch voltage shifter <NUM>. Latch voltage shifter <NUM> comprises low voltage latch inverter <NUM>, NMOS transistors <NUM>, <NUM>, <NUM>, and <NUM>, and PMOS transistors <NUM>, <NUM>, <NUM>, and <NUM>, in the configuration shown. Latch voltage shifter <NUM> receives EN_SEC as an input and outputs EN_HV and EN_HV_N, which have a larger voltage swing than EN_SEC and ground.

<FIG> depicts high voltage current limiter <NUM>, which comprises a PMOS transistor that receives VEGSUP_LOC and outputs VEGSUP with a limited current (acting as a current bias) This circuit can be used with the circuits that do not have local current limiter such as in <FIG>,<FIG>,<FIG>,<FIG>,<FIG> to limit current.

<FIG> depicts latch voltage shifter <NUM> with a current limiter for read operations. Latch voltage shifter <NUM> comprises latch voltage shifter <NUM> from <FIG>. It also comprises current limiter <NUM> comprising PMOS transistor <NUM> and current source <NUM>. Current limiter <NUM> is connected to current limiter <NUM> through switch <NUM>. Latch voltage shifter <NUM> also is connected to the signal HVSUP_GLB through switch <NUM>. During a read operation, latch voltage level shifter <NUM> will be connected to current limiter <NUM> through switch <NUM>. The outputs (e.g., approximately one Vt threshold voltage below Vdd2.5V) of the latch voltage level shifter <NUM> control the gate of the EG and CG decoders as in <FIG>,<FIG>,<FIG>,<FIG>,<FIG>,<FIG>. When not in a read operation, latch voltage level shifter <NUM> will be connected to HVSUP_GLB through switch <NUM>.

<FIG> depicts an array with source line pulldown <NUM>, which utilizes the designs of <FIG> and <FIG>. Array with source line pulldown <NUM> comprises a plurality of memory cells organized into rows (indicated by word lines WL0,. WL7) and columns (indicated by bit lines BL0,. An exemplary memory cell pair is memory cell pair <NUM>, which comprises one cell coupled to word line <NUM> (WL0) and another cell coupled to word line <NUM> (WL1). The two cells share erase gate <NUM> (EG0) and source line <NUM> (SL0). A column of dummy memory cells also is present, here shown attached to bit line BL_PWDN1. An exemplary dummy memory cell pair is dummy memory cell pair <NUM>, which comprises one cell coupled to word line <NUM> (WL0) and another cell coupled to word line <NUM> (WL1). The two cells share erase gate <NUM> (EG0) and source line <NUM> (SL0). The selected memory cells and dummy memory cells can be configured during read operations as discussed previously for <FIG> and <FIG>.

Claim 1:
A device comprising:
an array (<NUM>) of non-volatile split-gate flash memory cells organized in rows along word lines (WL), erase gate lines (EG) and source lines (SL), and in columns along bit lines (BL),
wherein each non-volatile split-gate flash memory cell is a four-terminal cell comprising a bit line terminal, a word line terminal, an erase gate terminal, and a source line terminal;
a high voltage row decoder (<NUM>) configured to receive select signals, select one of a plurality of different voltages to generate read, erase, and programming voltages, and apply the selected voltage to one or more source lines (SL)(SL) coupled to source line terminals of a first plurality of non-volatile four-terminal split-gate flash memory cells (<NUM>, <NUM>) in the array during a program operation; and
a second plurality of non-volatile four-terminal split-gate flash memory cells in the array being in an erased state and operating as dummy memory cells (<NUM>, <NUM>) not used to store data and arranged, during a read operation, to pull down, through one or more dummy bit lines (<NUM>, BL_PWDN) and one or more switches, one or more source lines to ground,
and arranged , during the program operation, to connect, through the one or more dummy bit lines and the one or more switches, the one or more source lines to an inhibit voltage (VDD),
wherein the one or more source lines are connected to the source terminals of the first plurality of non-volatile four-terminal split-gate flash memory cells in the respective one or more rows in the array and to the source terminals of the second plurality of non-volatile four-terminal split-gate flash memory cells operating as dummy cells in the respective one or more rows in the array.