Patent Description:
Non-volatile memory is a semiconductor memory device capable of retaining stored data even when power supply is terminated. Examples of non-volatile memory device may include programmable read only memory (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), flash memory device, etc..

Recently, according to the technical demands for high integration and low power consumption characteristics and random access to memory cells, next-generation semiconductor memory devices such as magnetic random access memory (MRAM) and phase-change random access memory (PRAM) have been developed.

Such next generation semiconductor memory devices use variable resistance devices having resistance values that vary according to a current or a voltage applied thereto and are capable of maintaining the resistance values even when current or voltage supply is cut off. In order to realize high integration and low power consumption, it is desired that a resistance variation characteristic of a variable resistance device occurs at a low application voltage, and a resistance variable range is increased.

Variable resistance layers comprising two layers of materials having different valence are described by <CIT>, <CIT>, <CIT> and <CIT>. There is no disclosure of a channel layer as further defined by the independent claim in these four documents. On the other hand, <CIT> describes a vertically stacked structure of variable resistance memory layers with a vertical channel layer. This latter publication, however, lacks a two-layered structure of the variable resistance layer. The disclosures of<CIT>, <CIT>, <CIT> and <CIT>on the one hand and<CIT> on the other hand have mutually different current paths in operation.

Provided are variable resistance memory devices according to claim <NUM>.

According to an embodiment of the invention, a device according to claim <NUM> is provided.

Expressions such as "at least one of," when preceding a list of elements (e.g., A, B, and C), modify the entire list of elements and do not modify the individual elements of the list. For example, "at least one of A, B, and C," "at least one of A, B, or C," "one of A, B, C, or a combination thereof," and "one of A, B, C, and a combination thereof," respectively, may be construed as covering any one of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C.

The disclosure will be described in detail below with reference to accompanying drawings. The embodiments of the disclosure are capable of various modifications and may be embodied in many different forms. In the drawings, like reference numerals denote like components, and sizes of components in the drawings may be exaggerated for convenience of explanation.

When a layer, a film, a region, or a panel is referred to as being "on" another element, it may be directly on the other layer or substrate, or intervening layers may also be present.

It will be understood that although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another. The terms do not define that the components have different materials or structures from each other.

Throughout the specification, when a portion "includes" an element, another element may be further included, rather than excluding the existence of the other element, unless otherwise described.

In addition, the terms such as ". unit", "module", etc. provided herein indicates a unit performing at least one function or operation, and may be realized by hardware, software, or a combination of hardware and software.

As used herein, in particular, terms such as "the" and demonstratives similar thereto used herein may be to indicate both the singular and the plural.

Also, the steps of all methods described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or example language (e.g., "such as") provided herein, is intended merely to better illuminate the present disclosure and does not pose a limitation on the scope of the present disclosure unless otherwise claimed.

<FIG> is a cross-sectional view of a variable resistance memory device <NUM> according to an example outside the invention, and <FIG> is a conceptual diagram for illustrating a principle of resistance variation occurring in a variable resistance layer included in the variable resistance memory device of <FIG>.

Referring to <FIG>, the variable resistance memory device <NUM> includes a variable resistance layer <NUM> including a first layer <NUM> and a second layer <NUM>, and a first conductive element E1 and a second conductive element E2 for applying a voltage to the variable resistance layer <NUM>.

The variable resistance layer <NUM> includes the first layer <NUM> including a first material, and the second layer <NUM> on the first layer <NUM>, the second layer <NUM> including a second material having a different valence from that of the first material. The first layer <NUM> may have a valence that is greater or less than that of the second layer <NUM>.

The first conductive element E1 and the second conductive element E2 are at opposite ends on the variable resistance layer <NUM>, and may be arranged to form a current path in the variable resistance layer <NUM> in a horizontal direction, that is, a direction perpendicular to a direction in which the first layer <NUM> and the second layer <NUM> are stacked, when a voltage is applied thereto. The first conductive element E1 and the second conductive element E2 may be formed in contact with opposite ends on the second layer <NUM>. However, the disclosure is not limited to the above example, that is, the first and second conductive elements E1 and E2 may be formed in contact with opposite ends on the first layer <NUM>.

The variable resistance layer <NUM> represents a resistance characteristic that varies depending on an applied voltage. The resistance characteristic of the variable resistance layer <NUM> is dependent upon whether a conductive filament is formed by behavior of oxygen in the variable resistance layer <NUM> according to the voltage applied to the first conductive element E1 and the second conductive element E2 on the variable resistance layer <NUM>. According to whether the conductive filament is formed, the variable resistance layer <NUM> may represent a low-resistive state or a high-resistive state, and accordingly, information of '<NUM>' or '<NUM>' may be recorded. An applied voltage that changes the variable resistance layer <NUM> from a high resistive state to a low resistive state is referred to as a set voltage Vset and an applied voltage that changes the variable resistance layer <NUM> from the low resistive state to the high resistive state is referred to as a reset voltage Vreset. The variable resistance memory device <NUM> according to the embodiment suggests the variable resistance layer <NUM> capable of implementing a low set voltage.

As in the example, when the variable resistance layer <NUM> includes multiple layers, in which the first layer <NUM> and the second layer <NUM> including materials having different valences from each other are stacked adjacent to each other, as shown in <FIG>, an oxygen vacancy Vo is formed at an interface between the first and second layers <NUM> and <NUM> in order to balance charges.

For example, when a first material included in the first layer <NUM> is HfO<NUM> having a valence of <NUM> and a second material included in the second layer <NUM> is Al<NUM>O<NUM> having a valence of <NUM>, Al enters Hf site to form the oxygen vacancy at the interface between the first layer <NUM> and the second layer <NUM>. The above atom behavior may be expressed by a formula below.

Al<NUM>O<NUM> + HfO<NUM> → 2AlHf' + VO¨ + 3OOx.

In the formula above, AlHf' denotes a structure in which some Al occupies Hf site in HfO<NUM> in the structure of Al<NUM>O<NUM>. VO¨ denotes a structure in which O site is empty and OOx denotes a structure in which O is located in O site.

The oxygen vacancies Vo formed as above are collected to form the conductive filament, and the resistance of the variable resistance layer <NUM> is lowered by the conductive filament.

When the conductive filament is sufficiently formed even at a low applied voltage and a difference between resistances in the low resistive state and the high resistive state generated by the applied voltage is increased, the variable resistance performance is excellent. To this end, the variable resistance layer <NUM> includes a structure in which oxide materials having different valences are arranged adjacent to each other, and a difference between the valences of the first layer <NUM> and the second layer <NUM> may be <NUM> or greater such that the oxygen vacancies Vo may be sufficiently formed.

When the variable resistance layer <NUM> is configured as in the embodiment, a desired range of resistance variation may be implemented with a less thickness as compared with a variable resistance device based on charge-trapping or a variable resistance device using a phase change material. The first layer <NUM> and the second layer <NUM> in the variable resistance layer <NUM> may each have a thickness, for example, of about <NUM> or less.

The first material and the second material included in the variable resistance layer <NUM> may include various oxide materials. For example, the first material and the second material may include an oxide material of at least one atom selected from the group consisting of zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), proseodymium (Pr), rubidium (Rb), barium (Ba), magnesium (Mg), beryllium (Be), niobium (Nb), vanadium (V), gadolunium (Gd), scandium (Sc), and silicon (Si). The first material and the second material may each include an oxide material having a band gap energy of <NUM> eV or greater, for example, one of Rb<NUM>O, TiO<NUM>, BaO, ZrO<NUM>, CaO, HfO<NUM>, SrO, Sc<NUM>O<NUM>, MgO, Li<NUM>O, Al<NUM>O<NUM>, SiO<NUM>, BeO, Sc<NUM>O<NUM>, Nb<NUM>O<NUM>, NiO, Ta<NUM>O<NUM>, WO<NUM>, V<NUM>O<NUM>, La<NUM>O<NUM>, Gd<NUM>O<NUM>, CuO, MoO<NUM>, Cr<NUM>O<NUM>, MnO<NUM>.

Valences of the above materials are shown in Table <NUM> below.

Referring to Table <NUM> above, two materials having different valences may be selected and applied to the first layer <NUM> and the second layer <NUM>. A difference between the valences of the first layer <NUM> and the second layer <NUM> may be set so that replacement between atoms easily occurs due to the difference in the valences and oxygen vacancies may be sufficiently formed. For example, materials used in the first layer <NUM> and the second layer <NUM> may be selected so that the difference between valences of the first layer <NUM> and the second layer <NUM> may be <NUM> or greater. For example, the first layer <NUM> may include HfO<NUM> having a valence of <NUM>, and the second layer <NUM> may include Al<NUM>O<NUM> having a valence of <NUM>. In addition, following combinations may be used.

As illustrated in the combinations above, the first material and the second material may be selected from among materials having a valence difference of <NUM>. However, one or more embodiments are not limited thereto, and other combinations having a valence difference of <NUM> or greater may be selected.

Even when the valence difference between the first material and the second material is constant, the oxygen vacancies may be sufficiently formed as a density difference between the first material and the second material increases. Since the oxide having a low density has a larger space between atoms than that of the oxide having a high density, diffusion of oxygen ions (O<NUM>-) may occur sufficiently towards the oxide having the low density. In this regard, the first material and the second material may be selected so that the difference between densities of the first layer <NUM> and the second layer <NUM> is, for example, <NUM>/cm<NUM> or greater. Among the combinations in Table <NUM> above, a combination of Al<NUM>O<NUM>/HfO<NUM> has the largest density difference between two materials, and it may be estimated that the oxygen vacancies may be sufficiently formed. However, one or more embodiments are not limited to the above combination.

<FIG> is a cross-sectional view of a variable resistance memory device <NUM> according to another example outside the invention. <FIG> is a conceptual diagram for illustrating a principle of a variable resistance in a variable resistance layer included in the variable resistance memory device of <FIG>.

A variable resistance layer <NUM> of the variable resistance memory device <NUM> includes the first layer <NUM>, the second layer <NUM>, and a third layer <NUM>, and the first conductive element E1 and the second conductive element E2 may be arranged in contact with opposite ends on the third layer <NUM>.

The variable resistance layer <NUM> has a structure in which two or more materials having different valences are stacked, and two adjacent layers from among the first to third layers <NUM>, <NUM>, and <NUM> may have materials having different valences from each other. That is, a first material in the first layer <NUM> and a second material in the second layer <NUM> may have different valences, and the second material in the second layer <NUM> and a third material in the third layer <NUM> may have different valences. The first material and the third material may be the same as or different from each other.

A difference between the valences of the first material in the first layer <NUM> and the second material in the second layer <NUM> may be <NUM> or greater. A difference between the valences of the second material in the second layer <NUM> and the third material in the third layer <NUM> may be <NUM> or greater.

The second material in the second layer <NUM> that is an intermediate layer in the variable resistance layer <NUM> is not particularly restricted, provided that the valence thereof is different from those of the first and third materials. For example, the valences of the first layer <NUM>, the second layer <NUM>, and the third layer <NUM> may be in an increasing or decreasing order, or the valence of the second material in the second layer <NUM> may be the greatest or the smallest.

Each of the first to third materials may be selected such that the oxygen vacancies that generate at interfaces among the first to third layers <NUM>, <NUM>, and <NUM> due to the valence difference may be sufficiently generated. The first layer <NUM> and the third layer <NUM> may include HfO<NUM> and the second layer may include Al<NUM>O<NUM>. The first layer <NUM> and the third layer <NUM> may include the first material, and the second layer <NUM> may include the second material. For example, combinations of the first and second materials as illustrated in Table <NUM> above may be selected. Also, materials having a density difference of <NUM>/cm<NUM> or greater may be selected as the first and second materials, or materials having a density difference of <NUM>/cm<NUM> or greater from among the combinations having different valences may be selected as the first and second materials.

The first to third layers <NUM>, <NUM>, and <NUM> may each have a thickness of <NUM> or less. The second layer <NUM> may have the smallest thickness, for example, a thickness of <NUM> or less.

In the example, the variable resistance layer <NUM> is configured to have a triple-layered structure, in which materials having difference valences are adjacent to each other, and thus, the interfaces where the oxygen vacancies caused by the difference in the valences are generated may be increased. As shown in <FIG>, when the oxygen vacancies Vo and interstitial oxygen ions O<NUM>- are formed in the variable resistance layer <NUM> due to the application of voltage, replacement of atoms may occur at the interface between the two materials having different valences, that is, an interface between the first and second layers <NUM> and <NUM> and an interface between the second and third layers <NUM> and <NUM>, and thus, the oxygen vacancies Vo are sufficiently formed and the conductive filament caused by the oxygen vacancies Vo may be easily generated. For example, the conductive filament may be more sufficiently formed than the structure shown in <FIG>.

<FIG> is a cross-sectional view of a variable resistance memory device <NUM> according to another example outside the invention.

In the variable resistance memory device <NUM> according to the example, a variable resistance layer <NUM> includes the first layer <NUM>, the second layer <NUM>, the third layer <NUM>, and a fourth layer <NUM>.

Two or more materials from among a first material, a second material, a third material, and a fourth material respectively included in the first to fourth layers <NUM>, <NUM>, <NUM>, and <NUM> may have different valences from each other. Also, adjacent layers may have materials having different valences from each other. That is, the first material and the second material have different valences, the second material and the third material have different valences, and the third material and the fourth material have different valences. The first material may be the same as the third material. The second material may be the same as the fourth material. For example, the first and third layers <NUM> and <NUM> may include the first material, and the second and fourth layers <NUM> and <NUM> may include the second material. Combinations of the first and second materials as illustrated in Table <NUM> above may be selected. Also, materials having a density difference of <NUM>/cm<NUM> or greater may be selected as the first and second materials, or materials having a density difference of <NUM>/cm<NUM> or greater from among the combinations having different valences may be selected as the first and second materials. However, one or more examples are not limited to the above example.

The materials included in the first to fourth layers <NUM>, <NUM>, <NUM>, and <NUM> of the variable resistance layer <NUM> are not particularly restricted provided that materials in the adjacent layers have different valences from each other. For example, the valences of the first to fourth layers <NUM>, <NUM>, <NUM>, and <NUM> may be in an increasing or decreasing order, or the second layer <NUM> or the third layer <NUM> may include a material having the greatest or the smallest valence.

The first to fourth materials may be set such that the difference between valences of the adjacent layers is <NUM> or greater, and such that the oxygen vacancies generated due to the difference between the valences at the interfaces may be sufficiently generated.

Various oxides each having a band gap energy of <NUM> eV or greater may be included in each of the first to fourth layers <NUM>, <NUM>, <NUM>, and <NUM>, and as described above, may be selected such that the difference between the valences at the interface between the adjacent layers is as large as possible.

Due to the setting of the materials, the difference between the valences may be as large as possible at the interfaces among the plurality of layers, and the oxygen vacancies caused by the replacement among atoms may be easily formed.

The variable resistance layer <NUM> has a structure in which the interface between the materials having different valences is further added. In addition, since the interfaces where the conductive filaments are formed by the oxygen vacancies increase, the variable resistance range may be also increased.

<FIG> are cross-sectional views of a sample that is produced to test a variable resistance performance with respect to a configuration in which variable resistance materials having difference valences are adjacently stacked.

As shown in <FIG>, a SiO<NUM> having a thickness of <NUM>, an N-type Si layer having a thickness of <NUM>, a SiO<NUM> layer having a thickness of <NUM>, and an N-type Si layer having a thickness of <NUM> are sequentially stacked on a Si wafer, and then a patterning process and an etching process are performed to form a cylindrical device having N-Si (<NUM>)/SiO<NUM> (<NUM>)/N-Si (<NUM>) structure. A variable resistance material, e.g., HfO<NUM> is deposited to <NUM> on a side surface of the cylindrical device, and then, when a voltage is applied between an upper electrode, e.g., N-Si, and a lower electrode, e.g., N-Si, an electric current flows from the upper N-Si to the lower N-Si along a HfO<NUM>/SiO<NUM> layer. Here, Ti (<NUM>)/Pt (<NUM>) are deposited on the upper electrode, e.g., N-Si, in order to improve a contact resistance between the upper electrode, e.g., N-Si, and a probe station terminal.

<FIG> shows a structure, in which the HfO<NUM> layer of the structure of <FIG> is formed to a thickness of <NUM>, and additionally, Al<NUM>O<NUM> is deposited to <NUM> and HfO<NUM> is deposited to <NUM> on the HfO<NUM> layer. When the voltage is applied between the upper electrode, e.g., N-Si, and the lower electrode, e.g., N-Si, the electric current flows from the upper N-Si to the lower N-Si along the SiO<NUM>/HfO<NUM>/Al<NUM>O<NUM> layers.

The structures of <FIG> are provided to simulate the variable resistance performance of a multi-layered structure, in which materials having different valences are adjacent to one another.

In the above two structures, a set voltage Vset by which the high-resistive state is changed to the low-resistive state was measured, and in <NUM> samples having the structure of <FIG>, an average set voltage Vset was measured as <NUM> V, and in <NUM> samples having the structure of <FIG>, an average set voltage Vset was measured as <NUM> V.

When being compared with a set voltage Vset that is generally shown to be <NUM> V or greater in a variable resistance device using a charge trap layer according to the related art, it is recognized that there is an effect of reducing the set voltage in a structure in which two layers having different valences are arranged adjacent to each other.

In the above examples, the variable resistance layers <NUM>, <NUM>, and <NUM> have the double-layered, triple-layered, and quadruple-layered structures, but one or more embodiments are not limited thereto, that is, a structure including five or more layers, to which an interface where the valences are different is added, may be used.

<FIG> is a cross-sectional view of a variable resistance memory device <NUM> according to an embodiment of the invention, and <FIG> is an equivalent circuit diagram of the variable resistance memory device <NUM> of <FIG>. <FIG> is a conceptual diagram for illustrating example operations of the variable resistance memory device <NUM> of <FIG>.

Referring to <FIG>, the variable resistance memory device <NUM> includes an insulating layer <NUM>, a variable resistance layer <NUM> on the insulating layer <NUM>, a channel layer <NUM> on the variable resistance layer <NUM>, a gate insulating layer <NUM> on the channel layer <NUM>, and a plurality of gate electrodes <NUM> on the gate insulating layer <NUM>. Spaces among the plurality of gate electrodes <NUM> may be filled with an insulating layer <NUM>. However, one or more embodiments are not limited thereto, that is, the insulating layer <NUM> may be omitted.

The variable resistance layer <NUM> includes the first layer <NUM> including a first material and the second layer <NUM> including a second material having a valence that is different from that of the first material. The second layer <NUM> may have a greater valence than that of the first layer <NUM>. Materials in the variable resistance layer <NUM> and characteristics of the variable resistance layer <NUM> are substantially the same as the above descriptions about the variable resistance layer <NUM> with reference to <FIG>. When materials having different valences are mixed, the replacement among atoms occurs and the oxygen vacancies are generated. Accordingly, the oxygen vacancies Vo are actively generated at the interface between the first layer <NUM> and the second layer <NUM>, and thus, the conductive filaments may be easily formed.

Although it is shown that the second layer <NUM> having the greater valence is on the first layer <NUM> having the less valence in the variable resistance layer <NUM>, one or more embodiments are not limited thereto, that is, a stacking order of the first layer <NUM> and the second layer <NUM> may be changed. That is, the first layer <NUM> having the less valence may be formed on the second layer <NUM> having the greater valence, and the first layer <NUM> may be in contact with the channel layer <NUM>.

The channel layer <NUM> may include a semiconductor material. The channel layer <NUM> may include, for example, poly-Si. A source electrode S and a drain electrode D may be connected to opposite ends of the channel layer <NUM>.

The gate insulating layer <NUM> may include various kinds of insulating materials. For example, the gate insulating layer <NUM> may include silicon oxide, silicon nitride, or silicon oxynitride.

A voltage for turning on/turning off the channel layer <NUM> may be selectively applied to each of the plurality of gate electrodes <NUM>.

The variable resistance memory device <NUM> has a structure including an array of a plurality of memory cells MC, and each of the memory cells MC may have a structure in which a transistor and a variable resistor are connected in parallel as shown in the equivalent circuit diagram of <FIG>. Respective variable resistance may be set by the voltage applied to each gate electrode and the voltage between the source electrode S and the drain electrode D, and may have a value corresponding to information <NUM> or <NUM>.

Operations of the variable resistance memory device <NUM> will be described below with reference to <FIG>.

When a memory cell to be recorded is selected, a gate voltage value of the corresponding memory cell is adjusted so as not to form a channel, that is, so that the channel is turned off, and gate voltage values of unselected memory cells are adjusted so that channels in the unselected memory cells are turned on.

<FIG> shows an example, in which a gate voltage is applied to the gate electrode <NUM> in each memory cell so that a memory cell MC2 at a center is turned off (OFF) and two memory cells MC1 and MC3 at opposite sides of the memory cell MC2 are turned on (ON). When the voltage is applied between the source electrode S and the drain electrode D, a conductive path denoted by the arrow A is formed. Desired information of <NUM> or <NUM> may be recorded on the selected memory cell MC2 by applying a voltage having a value of the set voltage Vset or the reset voltage Vreset.

In a reading operation, reading of the selected memory cell may be performed similarly as above. That is, a gate voltage applied to each of the gate electrodes <NUM> is adjusted so that the channel of the selected memory cell MC2 is turned off and the channels of the unselected memory cells MC1 and MC3 are turned on, and after that, an electric current flowing in the corresponding memory cell MC2 due to an applied voltage Vread between the source electrode S and the drain electrode D is measured to identify the memory cell state (<NUM> or <NUM>).

<FIG> is a cross-sectional view of a variable resistance memory device <NUM> according to another embodiment.

The variable resistance memory device <NUM> of the embodiment is different from the variable resistance memory device <NUM> shown in <FIG> in that a variable resistance layer <NUM> includes the first layer <NUM>, the second layer <NUM>, and the third layer <NUM>, and the other components of the variable resistance memory device <NUM> are substantially the same as those of the variable resistance memory device <NUM> shown in <FIG>.

The variable resistance layer <NUM> includes the first to third layers <NUM>, <NUM>, and <NUM>. The second layer <NUM> at the center of the variable resistance layer <NUM> may include a material having the higher valence than those of the first and third layers <NUM> and <NUM>. Alternatively, the second layer <NUM> may include a material having lower valence than those of the first and third layers <NUM> and <NUM>. The first layer <NUM> and the third layer <NUM> may include the same material. However, one or more embodiments are not limited thereto, that is, the first layer <NUM> and the third layer <NUM> may include different materials from each other.

The variable resistance layer <NUM> of the variable resistance memory device <NUM> according to the embodiment sets the materials included in the first layer <NUM>, the second layer <NUM>, and the third layer <NUM>, so that a plurality of interfaces among the materials having different valences are generated and the valence difference at each interface may be as large as possible, like in the variable resistance layer <NUM> of <FIG>. First to third materials may be selected so that the second material in the second layer <NUM> at the center of the variable resistance layer <NUM> may be the smallest or the greatest. Accordingly, the replacement among atoms may be actively generated, and then, the oxygen vacancies may be easily generated and the conductive filament may be easily formed. The variable resistance memory device <NUM> according to the embodiment may have a low set voltage, for example, a set voltage less than that of the variable resistance memory device <NUM> of <FIG>.

The variable resistance memory device <NUM> of the embodiment has the substantially same structure as that of the variable resistance memory device <NUM> of <FIG>, except that a variable resistance layer <NUM> has a quadruple-layered structure including the first layer <NUM>, the second layer, the third layer <NUM>, and the fourth layer <NUM>.

Two or more materials from among a first material, a second material, a third material, and a fourth material respectively included in the first to fourth layers <NUM>, <NUM>, <NUM>, and <NUM> may have different valences from each other. Also, adjacent layers may have materials having different valences from each other. That is, the first material and the second material have different valences, the second material and the third material have different valences, and the third material and the fourth material have different valences. The first material may be the same as the third material. The second material may be the same as the fourth material.

The variable resistance layer <NUM> of the variable resistance memory device <NUM> according to the embodiment sets the materials included in the first layer <NUM>, the second layer <NUM>, the third layer <NUM>, and the fourth layer <NUM>, so that a plurality of interfaces among the materials having different valences are generated and the valence difference at each interface may be as large as possible, like in the variable resistance layer <NUM> of <FIG>.

Due to the setting of the materials, the difference between the valences may be as large as possible at the interfaces among the plurality of layers, and the oxygen vacancies caused by the replacement among atoms may be sufficiently formed.

<FIG> is a cross-sectional view of a variable resistance memory device <NUM> according to another embodiment, and <FIG> is a perspective view of a memory string included in the variable resistance memory device <NUM> of <FIG>. <FIG> is an equivalent circuit diagram of the variable resistance memory device <NUM> of <FIG>.

The variable resistance memory device <NUM> according to the embodiment includes a vertical NAND (VNAND) memory in which a plurality of memory cells MC each including a variable resistance material are arrayed in a vertical direction.

Referring to <FIG>, detailed structure of the variable resistance memory device <NUM> will be described below.

Referring to <FIG>, a plurality of cell strings CS are formed on a substrate <NUM>.

The substrate <NUM> may include a silicon material doped with first type impurities. For example, the substrate <NUM> may include a silicon material doped with p-type impurities. For example, the substrate <NUM> may include a p-type well (e.g., a pocket p-well). Hereinafter, it will be assumed that the substrate <NUM> includes p-type silicon. However, the substrate <NUM> is not limited to the p-type silicon.

A doping region <NUM> is provided in the substrate <NUM>. For example, the doping region <NUM> may be of a second type that is different from that of the substrate <NUM>. For example, the doping region <NUM> may be of an n-type. Hereinafter, it will be assumed that the doping region <NUM> is of the n-type. However, the doping region <NUM> is not limited to the n-type. The doping region <NUM> may be a common source line CSL.

There may be k*n cell strings CS that are arranged in a matrix as shown in the circuit diagram of <FIG>, and may each be named as CSij (<NUM>≤i≤k, <NUM>≤j≤n) according to a location thereof in each row and column. Each of the cell strings CSij is connected to a bit line BL, a string selection line SSL, a word line WL, and the common source line CSL.

Each of the cell strings CSij includes memory cells MC and a string selection transistor SST. The memory cells MC and the string selection transistors SST in each of the cell strings CSij may be stacked in a height direction.

The plurality of rows of the cell strings CSij are respectively connected to different string selection lines SSL1 to SSLk. For example, the string selection transistors SST in cell strings CS11 to CS1n are commonly connected to a string selection line SSL1. The string selection transistors SST in the cell strings CSk1 to CSkn are commonly connected to the string selection line SSLk.

The plurality of columns of the cell strings CS are respectively connected to different bit lines BL1 to BLn. For example, the memory cells MC and the string selection transistors SST in the cell strings CS11 to CSk1 may be commonly connected to the bit line BL1, and the memory cells MC and the string selection transistors SST in the cell strings CS1n to CSkn may be commonly connected to the bit line BLn.

The plurality of rows of the cell strings CS may be respectively connected to different common source lines CSL1 to CSLk. For example, the string selection transistors SST in the cell strings CS11 to CS1n may be commonly connected to the common source line CSL1 and the string selection transistors SST of the cell strings CSk1 to CSkn may be commonly connected to the common source line CSLk.

The memory cells MC at the same height from the substrate <NUM> (or the string selection transistors SST) are commonly connected to one word line WL and the memory cells MC at different heights from the substrate <NUM> (or the string selection transistors SST) may be respectively connected to different word lines WL1 to WLm.

The circuit structure shown in <FIG> is an example. For example, the number of rows of the cell strings CS may be increased or decreased. As the number of rows of the cell strings CS varies, the number of string selection lines connected to the rows of the cell strings CS and the number of cell strings CS connected to one bit line may also vary. As the number of rows of the cell strings CS varies, the number of common source lines connected to the rows of the cell strings CS may also vary.

The number of columns of the cell strings CS may be increased or decreased. As the number of columns of the cell strings CS varies, the number of bit lines connected to the columns of the cell strings CS and the number of cell strings CS connected to one string selection line may also vary.

The height of the cell strings CS may increase or decrease. For example, the number of memory cells MC stacked in each of the cell strings CS may increase or decrease. As the number of memory cells MC stacked in each of the cell strings CS varies, the number of word lines WL may also vary. For example, the number of string selection transistors provided to each of the cell strings CS may increase. As the number of string selection transistors provided to each of the cell strings CS varies, the number of the string selection lines or the common source lines may also vary. As the number of string selection transistors increases, the string selection transistors may be stacked like the memory cells MC.

For example, writing and reading operations may be performed in units of rows of the cell strings CS. The cell strings CS are selected by the common source lines CSL in units of one row and may be selected by the string selection lines SSL in units of one row. Also, the voltage may be applied to the common source lines CSL in units of at least two common source lines CSL. The voltage may be applied to the common source lines CSL in units of total common source lines CSL.

In a selected row of the cell strings CS, the writing and reading operations may be performed in units of pages. A page may denote one row of memory cells MC connected to one word line WL. In the selected row of the cell strings CS, the memory cells MC may be selected by the word lines WL in units of pages.

The cell string CS may include a cylindrical pillar PL and a plurality of gates <NUM> and a plurality of insulators <NUM> which surround the cylindrical pillar PL in a ring shape, as shown in <FIG>. That is, the plurality of gates <NUM> and the plurality of insulators <NUM> may be stacked alternately with each other along a vertical direction (Z-direction).

Each of the gates <NUM> may include a metal material or a silicon material doped at a high concentration. Each of the gates <NUM> is connected to one of the word line WL and the string selection line SSL.

Each of the insulators <NUM> may include one or more of various insulating materials, e.g., silicon oxide, silicon nitride, etc..

The pillar PL may include a plurality of layers. An outermost layer of the pillar PL may include a gate insulating layer <NUM>. For example, the gate insulating layer <NUM> may include various insulating materials, e.g., one or more of silicon oxide, silicon nitride, silicon oxynitride, etc. The gate insulating layer <NUM> may be conformally deposited on the pillar PL.

A channel layer <NUM> may be conformally deposited on an internal surface of the gate insulating layer <NUM>. The channel layer <NUM> may include a semiconductor material doped with the first type impurities. The channel layer <NUM> may include a silicon material doped with the same type as that of the substrate <NUM>. For example, when the substrate <NUM> includes the silicon material doped with p-type impurities, the channel layer <NUM> may also include the silicon material doped with the p-type impurities. Alternatively, the channel layer <NUM> may include a material such as Ge, IGZO, GaAs, etc..

A variable resistance layer <NUM> may be arranged along the internal surface of the channel layer <NUM>. The variable resistance layer <NUM> may be arranged to be in contact with the channel layer <NUM>, and may be conformally deposited on the channel layer <NUM>.

The variable resistance layer <NUM> changes into a high-resistive state or a low-resistive state according to a voltage applied thereto, and may include the first layer <NUM>, the second layer <NUM>, and the third layer <NUM> which include oxide materials having different valences from one another.

The first layer <NUM>, the second layer <NUM>, and the third layer <NUM> of the variable resistance layer <NUM> may each include an oxide material of at least one atom selected from the group consisting of Zr, Hf, Al, Ni, Cu, Mo, Ta, Ti, W, Cr, Sr, La, Mn, Ca, Pr, and Si. The first to third layers <NUM>, <NUM>, and <NUM> may each include an oxide material having a band gap energy of <NUM> eV or greater, for example, one of Rb<NUM>O, TiO<NUM>, BaO, ZrO<NUM>, CaO, HfO<NUM>, SrO, Sc<NUM>O<NUM>, MgO, Li<NUM>O, Al<NUM>O<NUM>, SiO<NUM>, and BeO.

The variable resistance layer <NUM> has a structure in which two or more materials having different valences are stacked, and two adjacent layers from among the first to third layers <NUM>, <NUM>, and <NUM> may have materials having different valences from each other. As described above with reference to the variable resistance layer <NUM> of <FIG> and the variable resistance layer <NUM> of <FIG>, the variable resistance layer <NUM> may set a first material in the first layer <NUM>, a second material in the second layer <NUM>, and a third material in the third layer <NUM>, so that the oxygen vacancies may be sufficiently generated due to the replacement among atoms at each interface. Accordingly, the variable resistance memory device <NUM> may have characteristics of low set voltage and low reset voltage.

Although the variable resistance layer <NUM> has a triple-layered structure as an example, one or more embodiments are not limited thereto, that is, the variable resistance layer may include two or more layers in which layers having different valences are arranged adjacent to each other. For example, in some embodiments, the variable resistance layer <NUM> may have a double-layer structure with only the first layer <NUM> and the second layer <NUM>. Alternatively, in other embodiments, the variable resistance layer <NUM> may have four or more layers, such as further including the fourth layer <NUM> surrounding the third layer <NUM>.

The channel layer <NUM> and the variable resistance layer <NUM> may be in contact with the doping region <NUM>, that is, the common source region.

A drain <NUM> may be provided on the pillar PL. The drain <NUM> may include a silicon material doped as the second type. For example, the drain <NUM> may include the silicon material doped as n-type.

A bit line <NUM> may be provided on the drain <NUM>. The drain <NUM> and the bit line <NUM> may be connected to each other via contact plugs.

Each of the gates <NUM> and regions in the gate insulating layer <NUM>, the channel layer <NUM>, and the variable resistance layer <NUM>, the regions facing each gate <NUM> in a horizontal direction (X-direction), configure the memory cell MC. That is, the memory cell MC has a circuit structure, in which the transistor including the gate <NUM>, the gate insulating layer <NUM>, and the channel layer <NUM> and a variable resistor provided by the variable resistance layer <NUM> are connected in parallel.

The above parallel connection structure is continuously arranged in the vertical direction (Z-direction) to form the cell string CS. In addition, opposite ends of the cell string CS may be connected to the common source line CSL and the bit line BL as shown in the circuit diagram of <FIG>. When the voltage is applied to the common source line CSL and the bit line BL, the programming, reading, and erasing operations may be performed on the plurality of memory cells MC.

For example, when a memory cell MC to be recorded on is selected, a gate voltage value of the corresponding memory cell is adjusted so as not to form a channel, that is, so that the channel is turned off, and gate voltage values of unselected memory cells are adjusted so that channels in the unselected memory cells are turned on. Accordingly, the current path formed by the voltage applied to the common source line CSL and the bit line BL passes through the region of the variable resistance layer <NUM> in the selected memory cell MC. At this time, a low-resistive state or a high-resistive state may be obtained by changing the applied voltage to have the set voltage Vset or the reset voltage Vreset value, and desired information of <NUM> or <NUM> may be recorded on the selected memory cell MC.

In a reading operation, reading of the selected memory cell may be performed similarly as above. That is, a gate voltage applied to each of the gates <NUM> is adjusted so that the channel of the selected memory cell MC is turned off and the channels of the unselected memory cells MC are turned on, and after that, an electric current flowing in the corresponding memory cell MC due to an applied voltage Vread between the common source line CSL and the bit line BL is measured to identify the memory cell state (<NUM> or <NUM>).

As described above, the variable resistance memory device <NUM> according to the embodiment configure the memory cells MC to include the variable resistance layer <NUM>, in which the conductive filament may be easily formed due to the oxygen vacancies, and form the memory device by arranging the memory cells MC. Therefore, the variable resistance layer <NUM> may be relatively thin as compared with a memory device based on, for example, a phase-change material or a charge-trap, and the variable resistance memory device <NUM> may have a low operating voltage. The variable resistance memory device <NUM> may increase a density and may implement a low power consumption by addressing a scaling issue among the memory cells in a next-generation VNAND.

The variable resistance memory device <NUM> according to the disclosure may be implemented in a memory system and/or as a chip-type memory block to be used as a neuromorphic computing platform or used to construct a neural network.

<FIG> is a block diagram of a memory system wherein an embodiment of the invention can be used.

Referring to <FIG>, the memory system <NUM> may include a memory controller <NUM> and a memory device <NUM>. The memory controller <NUM> performs a control operation with respect to the memory device <NUM>, for example, the memory controller <NUM> provides the memory device <NUM> with an address ADD and a command CMD to perform a programming (or writing), a reading, and/or an erasing operation with respect to the memory device <NUM>. Also, data for the programming operation and read data may be transmitted between the memory controller <NUM> and the memory device <NUM>.

The memory device <NUM> may include a memory cell array <NUM> and a voltage generator <NUM>. The memory cell array <NUM> may include a plurality of memory cells that are arranged on regions where a plurality of word lines and a plurality of bit lines intersect with each other. The memory cell array <NUM> includes non-volatile memory cells based on the embodiments in <FIG> and <FIG> of the present application.

The memory controller <NUM> may include processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU) , an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The memory controller <NUM> may operate in response to requests from a host (not shown) and may be configured to access the memory device <NUM> and control operations discussed above (for example for the write/read operations in <FIG>), thereby transforming the memory controller <NUM> into a special purpose controller. The memory controller <NUM> may generate an address ADD and a command CMD for performing programming/reading/erasing operations on the memory cell array <NUM>. Also, in response to commands from the memory controller <NUM>, the voltage generator <NUM> (e.g., power circuit) may generate a voltage control signal for controlling at least one voltage level used in the non-volatile memory device <NUM>. As an example, the voltage generator <NUM> may generate the voltage control signal for controlling a voltage level of a word line for reading data from or programming data on the memory cell array <NUM>.

In addition, memory controller <NUM> may perform a determination operation on the data read from the non-volatile memory device <NUM>. For example, by determining the data read from the memory cells, the number of on-cells and/or off-cells from among the memory cells may be determined. The memory device <NUM> may provide the memory controller <NUM> a pass/fail signal P/F according to a read result with respect to the read data. The memory controller <NUM> may refer to the pass/fail signal P/F and thus control write and read operations of the memory cell array <NUM>.

<FIG> is a diagram illustrating a neuromorphic apparatus wherein an embodiment of the invention can be used and an external device connected to the apparatus.

Referring to <FIG> a neuromorphic apparatus <NUM> may include processing circuitry <NUM> and/or memory <NUM>. The neuromorphic apparatus <NUM> may include a memory based on the examples in <FIG> and embodiments in <FIG> of the present description.

In some examples or embodiments, processing circuitry <NUM> may be configured to control functions for driving the neuromorphic apparatus <NUM>. For example, the processing circuitry <NUM> may be configured to control the neuromorphic apparatus <NUM> by executing programs stored in the memory <NUM> of the neuromorphic apparatus <NUM>. In some examples or embodiments, the processing circuitry may include hardware such as logic circuits; a hardware/software combination, such as a processor executing software; or a combination thereof. For example, a processor may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic apparatus <NUM>, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), or the like. In some example embodiments, the processing circuitry <NUM> may be configured to read/write various data from/in the external device <NUM> and/or execute the neuromorphic apparatus <NUM> by using the read/written data. In some embodiments, the external device <NUM> may include an external memory and/or sensor array with an image sensor (e.g., CMOS image sensor circuit).

In some examples or embodiments, the neuromorphic apparatus in <FIG> may be applied in a machine learning system. The machine learning system may utilize a variety of artificial neural network organizational and processing models, such as convolutional neural networks (CNN), deconvolutional neural networks, recurrent neural networks (RNN) optionally including long short-term memory (LSTM) units and/or gated recurrent units (GRU), stacked neural networks (SNN), state-space dynamic neural networks (SSDNN), deep belief networks (DBN), generative adversarial networks (GANs), and/or restricted Boltzmann machines (RBM).

Alternatively or additionally, such machine learning systems may include other forms of machine learning models, such as, for example, linear and/or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and/or combinations thereof, including ensembles such as random forests. Such machine learning models may also be used to provide various services and/or applications, e.g., an image classify service, a user authentication service based on bio-information or biometric data, an advanced driver assistance system (ADAS) service, a voice assistant service, an automatic speech recognition (ASR) service, or the like, may be performed, executed or processed by electronic devices.

While the variable resistance memory device have been particularly shown and described with reference to examples or embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the invention as defined by the following claims. In the specification, many details are described in detail, but they are not provided to limit the scope of the disclosure, and should be interpreted as illustrating.

The variable resistance memory device may change the resistance under a low applied voltage.

The variable resistance memory device may show a large variable resistance range.

The variable resistance memory device may be easy to implement low power consumption and high integration density.

Claim 1:
A variable resistance memory device (<NUM>, <NUM>, <NUM>, <NUM>) comprising
a variable resistance layer (<NUM>, <NUM>, <NUM>, <NUM>) including a first layer (<NUM>) and a second layer (<NUM>), the second layer (<NUM>) on the first layer (<NUM>), the first layer (<NUM>) including a first material, the second layer (<NUM>) including a second material having a valence different from a valence of the first material;
a first conductive element (E1) and a second conductive element (E2) on the variable resistance layer (<NUM>, <NUM>, <NUM>, <NUM>) and separated from each other so that an electric current path is formed in the variable resistance layer (<NUM>, <NUM>, <NUM>, <NUM>) in a direction perpendicular to a direction in which the first layer (<NUM>) and the second layer (<NUM>) are stacked:
a support layer including an insulating material (<NUM>, <NUM>) and supporting the first layer (<NUM>);
a channel layer (<NUM>, <NUM>) on the second layer (<NUM>);
a gate insulating layer (<NUM>, <NUM>) on the channel layer (<NUM>, <NUM>); and
a plurality of gate electrodes (<NUM>, <NUM>) on the gate insulating layer (<NUM>, <NUM>), the plurality of gate electrodes (<NUM>, <NUM>) being separated from one another,
wherein the first conductive element (E1) and the second conductive element (E2) are connected to opposite ends of the channel layer (<NUM>, <NUM>).