Patent Description:
Remote direct memory access (RDMA) is a feature used in computing platforms having networked high bandwidth accelerators. A RDMA technique can be used to offload the process of DMA reads and writes over a network out of a memory buffer without the involvement of a host processor or invoking an operating system. Such technique helps to circumvent system bottlenecks by giving direct access to memory through a previously registered user space mapped address range.

When such RDMA flows are directed to a device other than the host processor such as to an accelerator device having coherent memory locally attached, complexities can arise in that oftentimes such transactions still involve the host processor. This interaction can increase latency and reduce useful bandwidth, among other issues. <CIT> describes a method and system based on high-speed direct memory exchange between GPU and NIC. <CIT> describes a method, apparatus, and system supporting improved DMA writes. Embodiments of the invention are described in the dependent claims. In an example not forming part of the literal wording of the claims granted, a system comprises: a host processor having at least one core, at least one cache memory and a coherence circuit coupled to the at least one cache memory, where the coherence circuit comprises a DMA circuit to receive a RDMA write request, and based at least in part on an address of the RDMA write request, to directly send the RDMA write request to a device, where the RDMA write request has a relaxed ordering indicator associated therewith; the device coupled to the host processor Via a first bus, where in response to the RDMA write request, the device is to store data of the RDMA write request to a device-attached memory and to set a bias of the data to a device bias; and the device-attached memory locally coupled to the device. In an example, the coherence circuit comprises an address range decoder, and the DMA circuit is to access the address range decoder using the address of the RDMA write request to determine that the write request is directed to the device-attached memory, where the system comprises a server platform having an allocating default setting. In an example, in response to a second write request directed to a host memory coupled to the host processor, the host processor is to store second data of the second write request to the least one cache memory based on the allocating default setting. In an example, in response to a second RDMA write request directed to the device-attached memory, the host processor is to send an invalidation message to the device, and in response to the invalidation message, the device is to send a use once response to the host processor to grant a temporary host bias for the second data. In an example, the host processor, in response to the use once response, is to use second data of the second RDMA write request one time, and thereafter send a write request to the device to cause the device to store the second data in the device-attached memory, and thereafter the host processor is to perform a self-invalidation of the second data to relinquish the temporary host bias. In an example not forming part of the literal wording of the claims granted, a computer readable medium including data is to be used by at least one machine to fabricate at least one integrated circuit to perform the method of any one of the above examples.

In various embodiments, an automatic selection of whether incoming data to a host processor from a network device is to be stored according to an allocating or non-allocating flow may proceed based on address range information. The host processor identifies, based on an address range mechanism, incoming RDMA transactions as being directed to system memory (coupled to the host processor) or device-attached memory (coupled to an accelerator device in turn coupled to the host processor). The host processor may perform such address decoding without hints, either included in the original RDMA request from a source input/output (I/O) device, or appended to the request by a network interface card (NIC) or other intervening network circuitry. Still further as described herein, incoming Peripheral Component Interconnect Express (PCIe) transactions having relaxed ordered (RO) semantics and directed to a device-attached destination are sent directly from the host processor to the device (for delivery to the device-attached memory) as a direct store without a prefetch operation by the host processor, which would trigger an ownership or bias flip for data of the transaction. In addition, a bias flip flow may be optimized such that it is part of a response from the device, instead of a new request from the device that would trigger additional messages.

Embodiments may be used in connection with a variety of different RDMA communications. In a particular embodiment, an accelerator device may be a graphics accelerator that may leverage graphics processing unit (GPU) direct flows as described herein. Understand that embodiments apply equally to clustered accelerators. Further, while an example embodiment described herein is in connection with a Compute Express Link (CXL) specification-based link such as in accordance with the CXL Specification version <NUM>. In yet other embodiments, communication may be accordance with other coherent interconnect technologies such as an IBM XBus protocol, an Nvidia NVLink protocol, an AMD Infinity Fabric protocol, cache coherent interconnect for accelerators (CCIX) protocol or coherent accelerator processor interface (OpenCAPI).

<FIG> is a block diagram of a system in accordance with an embodiment. In <FIG>, a system <NUM> may be any type of computing device; however for purposes of illustration assume that system <NUM> is a server system (or portion thereof) in which various devices may be coupled in a networked arrangement. As shown one or more I/O devices <NUM> couple to a NIC <NUM>, in turn coupled to a host processor <NUM> via a first interconnect <NUM>. In embodiments, interconnect <NUM> may operate using an Ethernet-based communication protocol; of course other implementations are possible.

As illustrated, I/O devices <NUM> couple to NIC <NUM> via a network <NUM>. Network <NUM> may take the form of any suitable computer network, including an internet-based network. With an arrangement herein, incoming high speed communications from I/O devices <NUM> may be received that may be directed to an accelerator memory <NUM> in turn coupled to a device <NUM>, which may be some type of accelerator device. Such communications may be RDMA communications that may be handled with an optimized processing flow according to embodiments.

As illustrated in <FIG>, NIC <NUM> includes an RDMA circuit <NUM>. In embodiments herein, RDMA circuit <NUM> may be configured to receive incoming RDMA requests from one or more I/O devices <NUM> and direct them onto host processor <NUM> without performing any analysis of the request for purposes of appending TLP hints or so forth. As such, these communications may pass through NIC <NUM> and onto host processor <NUM> in an optimized manner. Furthermore, the complexity of packet processing performed in NIC <NUM> may be reduced.

As shown in <FIG> device <NUM> may be an accelerator or processor device coupled to host processor <NUM> via an interconnect <NUM>, which may be single interconnect, bus, trace, and so forth. Device <NUM> and host processor <NUM> may communicate over link <NUM> to enable data and messages to pass therebetween. In some embodiments, link <NUM> may be operable to support multiple protocols and communication of data and messages via the multiple interconnect protocols, including a CXL protocol as described herein. For example, link <NUM> may support various interconnect protocols, including a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Non-limiting examples of supported interconnect protocols may include PCI, PCIe, USB, IDI, IOSF, SMI, SMI3, SATA, CXL. cache, and CXL. mem, and/or the like.

In embodiments, device <NUM> may include accelerator logic <NUM> including circuitry <NUM>. In some instances, accelerator logic <NUM> and circuitry <NUM> may provide processing and memory capabilities. Examples of device <NUM> may include producer-consumer devices such as a graphics or other specialized accelerator, producer-consumer plus devices, software-assisted device memory devices, autonomous device memory devices, and giant cache devices. In some cases, accelerator logic <NUM> may couple to an optional accelerator memory <NUM>. Accelerator logic <NUM> and circuitry <NUM> may provide the processing and memory capabilities based on the device such as graphics functionality. For example, accelerator logic <NUM> and circuitry <NUM> may communicate using, for example, a coherent interconnect protocol for various functions, such as coherent requests and memory flows with host processor <NUM> via interface logic <NUM> and circuitry <NUM>. Interface logic <NUM> and circuitry <NUM> may determine an interconnect protocol based on the messages and data for communication.

In addition, circuitry <NUM> may be configured to handle incoming RDMA requests in an optimized manner. For example, where such incoming RDMA write requests are directed to accelerator memory <NUM>, circuitry <NUM> may be configured to perform direct writes into accelerator memory <NUM>, without the need for updating a bias for one more cache lines associated with the write request from a device bias to a host bias, as described further herein. Still further, circuitry <NUM> may be configured, in response to an incoming memory invalidation request from host processor <NUM>, to issue a use once response that informs host processor <NUM> that device <NUM> is to desirably use data associated with the memory invalidation request in the near future, such that host processor <NUM> uses the data once and then relinquishes ownership of the data to device <NUM>, as described further herein. In some embodiments, interface logic <NUM> may be coupled to a multi-protocol multiplexer <NUM> having one or more protocol queues <NUM> to send and receive messages and data with host processor <NUM>. Protocol queue <NUM> may be protocol specific such that each interconnect protocol may be associated with a particular protocol queue. Multiplexer <NUM> may also implement arbitration circuitry to arbitrate between communications of different protocols and provide selected communications to a physical layer <NUM>.

In various embodiments, host processor <NUM> may be a main processor such as a CPU. Host processor <NUM> is coupled to a host memory <NUM> and includes coherence logic (or coherence and cache logic) <NUM>, which may include a cache hierarchy. Coherence logic <NUM> may communicate using various interconnects with interface logic <NUM> including circuitry <NUM> and one or more cores 165a-n. In some embodiments, coherence logic <NUM> may enable communication via one or more of a coherent interconnect protocol and a memory interconnect protocol. As further illustrated, coherence logic <NUM> includes a DMA circuit <NUM>. In embodiments herein, DMA circuit <NUM> is configured to automatically select between allocating and non-allocating flows for handling incoming write requests, e.g., RDMA write requests, based on an address range decode. Such automatic selection may occur without hint information being provided, either by I/O device <NUM> or NIC <NUM>. In addition, when incoming requests such as incoming PCIe requests have relaxed ordering semantics, DMA circuit <NUM> sends direct stores to device <NUM> for storage in accelerator memory <NUM>, without performing a prefetch operation to obtain ownership. In this way, embodiments may avoid a bias flip from device bias to host bias for data of such incoming write requests, optimizing processing flow and reducing traffic between host processor <NUM> and device <NUM>.

In various embodiments, host processor <NUM> may include a device <NUM> to communicate with a bus logic <NUM> over an interconnect. In some embodiments, device <NUM> may be an I/O device, such as a PCIe I/O device. In other cases, one or more external devices such as PCIe devices (which may be one or more of I/O devices <NUM>) may couple to bus logic <NUM>.

In embodiments, host processor <NUM> may include interface logic <NUM> and circuitry <NUM> to enable multi-protocol communication between the components of host processor <NUM> and device <NUM>. Interface logic <NUM> and circuitry <NUM> may process and enable communication of messages and data between host processor <NUM> and device <NUM> in accordance with one or more interconnect protocols, e.g., a non-coherent interconnect protocol, a coherent interconnect, protocol, and a memory interconnect protocol, dynamically. For example, interface logic <NUM> and circuitry <NUM> may determine a message type for each message and determine which interconnect protocol of a plurality of interconnect protocols to process each of the messages. Different interconnect protocols may be utilized to process the messages.

In some embodiments, interface logic <NUM> may be coupled to a multi-protocol multiplexer <NUM> having one or more protocol queues <NUM> to send and receive messages and data with device <NUM>. Protocol queue <NUM> may be protocol specific such that each interconnect protocol may be associated with a particular protocol queue. Multiplexer <NUM> may also implement arbitration circuitry to arbitrate between communications of different protocols and provide selected communications to a physical layer <NUM>.

Referring now to <FIG>, shown is a flow diagram of a method in accordance with an embodiment of the present invention. As shown in <FIG>, method <NUM> is a method for routing an incoming write request to an appropriate destination. Method <NUM> may be performed by circuitry within a host processor, such as coherence circuitry that receives the incoming write requests. As such, method <NUM> may be performed by hardware circuitry, firmware, software and/or combinations thereof.

As illustrated, method <NUM> begins by receiving a write request in the host processor (block <NUM>). In an embodiment this request may be received within coherence circuitry. Assume that this write request is incoming from a NIC that in turn received the write request from a networked device, such as an I/O device. In any event, it is determined at diamond <NUM> whether this write request has a set transaction layer processing (TLP) processing hint (TPH). Typically, the NIC would apply this TPH as part of the network processing. However with embodiments herein, the NIC overhead of determining an appropriate destination and applying a TPH can be avoided.

Thus as illustrated, in typical use cases, control passes from diamond <NUM> to diamond <NUM> where it is determined whether an address of the incoming write request is within device memory. In an embodiment, this determination may be based on information present in one or more address range decoders of the coherence circuitry. If it is determined that the address is located in device memory, control passes to block <NUM> where the write request can be directly sent to the device for writing into the device memory. In an embodiment, this write request may be communicated to the device via a CXL bus.

Still with reference to <FIG>, otherwise if it is determined that the address is not in device memory, control passes to diamond <NUM> to determine whether a platform default setting is for allocating or non-allocating writes. That is for an allocating setting, data of the write request is allocated directly into a cache memory of the host processor, such as a last level cache (LLC). One example of such an allocating write arrangement may be implemented using an Intel® Direct Data Input/Output (DDIO) technique. With this or similar technique, incoming write requests are directly written into the host LLC, avoiding the overhead of writing such data out to memory. This operation may proceed, as it is presumed that such data will likely be accessed within the host processor in the near future. In contrast for a non-allocating setting, data of the write request may be written into host memory.

If it is determined that the platform default setting is for allocating writes, control passes to block <NUM> where the data of the write request may be allocated into a host cache memory, e.g., the LLC. Otherwise, control passes to block <NUM> where data of the write request is sent to host memory for storage.

Still with reference to <FIG>, if it is determined that the TPH of the incoming write request is set, control passes to diamond <NUM> where it is determined whether the TPH indicates an allocating transaction. If so, control passes to block <NUM> where the data is stored in host cache memory. Otherwise, control passes to diamond <NUM> where it is determined whether the address is in device memory. If so, the data is written to device memory at block <NUM>. Otherwise, control passes to block <NUM> where the data is written to host memory. Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

With embodiments having automatic selection of destination of incoming RDMA transactions, improved performance may be realized. Instead without an embodiment, typical server platforms that implement Intel® DDIO or similar technique would cause DMA writes to be stored into internal cache memory of the host processor. While this works well if the consumer of the data is in a processor core, it is sub-optimal if the consumer of the data is an accelerator device. In such cases, the ideal location for DMA write data is the device-attached memory itself. In theory, a NIC may be able to control where data is written using PCIe TPH. However, since the NIC does not operate on host physical addresses and further does not contain a system address map, it has no way of differentiating different writes without considerable overhead. Thus with an embodiment, there is no need for a NIC or other hardware to make a runtime decision on DMA data location (e.g., based on work descriptors). Embodiments instead enable automatic selection without any hint information in the incoming transactions. Instead without automatic selection, to determine whether a PCIe write allocates to cache memory (allocating) or memory (non-allocating) requires a hint, e.g., a TPH bit that is sent on a transaction-by-transaction basis. Note that the host processor may choose to honor or ignore this hint. If no hint is sent, the host processor processes the transaction based on a platform default setting, which can either be allocating or non-allocating. With an embodiment, there is no need for setting the TPH bit or other hint. And, even in a platform having an allocating default policy, RDMA transactions may be directly written to device-attached memory, which is optimal.

Referring now to <FIG>, shown is a flow diagram of a method in accordance with another embodiment of the present invention. As shown in <FIG>, method <NUM> is a method for routing an incoming write request having relaxed ordering. Method <NUM> may be performed by circuitry within a host processor, such as coherence circuitry. As such, method <NUM> may be performed by hardware circuitry, firmware, software and/or combinations thereof. As shown in <FIG>, method <NUM> begins by receiving a write request from an I/O device (block <NUM>). As described above, such request is received by coherence circuitry of the host processor. Next it is determined at diamond <NUM> whether a relaxed ordering indicator of the write request is set. If not, this write request is to be handled in an ordered manner. As such, control passes to block <NUM> where the write request may be ordered with respect to earlier transactions. In this way, the processor ensures that this write request is not completed until previous memory requests have first been performed.

Still referring to <FIG>, instead if it is determined that the relaxed ordering indicator is set, control passes to block <NUM> where it is determined whether the write request is directed to device memory. In an embodiment, an address decoder may be accessed to determine the destination of the write request. If directed to device memory, at block <NUM> the write request is sent to a device as a direct store to device memory, avoiding the need for first performing a host prefetch for ownership of the line to which this data is to be stored. As a result, a simplified transaction flow is realized for incoming write requests that are directed to a device memory. Still further, the device itself also benefits, as it is not impacted by blocking entries as a result of a loss of device bias for this data due to the host prefetch and ownership of the line, which would otherwise occur. As a result, improved efficiency of incoming device write requests is realized.

Still with reference to <FIG>, if it is determined that the request is not directed to device memory (namely it is directed to a location within host memory), control passes to block <NUM> where the data may be stored in the appropriate location. More specifically, depending upon whether the platform default setting is for allocating or non-allocating writes, the data may be stored in host cache memory (in case of an allocating default setting) or host memory (in case of a non-allocating default setting). Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

As described above, with a host processor prefetch for ownership of a line and consequent loss of device bias, undesirable effects such as blocking entries may occur within the device until it can flip the bias back to device bias. With an embodiment as in <FIG>, for PCIe traffic with a set relaxed ordered indicator, the host processor skips prefetch, which leads to a direct store to the device memory. And with no prefetch, the device does not transition the line from device to host bias. Embodiments may thus save communication of a number of messages, leading to more efficient transfer across a physical interface. Such operation may be ideal for large data transfers (e.g., bulk transfers) from I/O device to device memory.

Referring now to <FIG>, shown is a timing diagram illustrating operation of a direct store operation in accordance with an embodiment of the present invention. As shown in <FIG> in a computing system <NUM> such as server platform, an incoming memory write request is received in a NIC <NUM>. NIC <NUM> forwards this memory request, which has a set relaxed ordering indicator, to a host processor <NUM>. Processor <NUM> may be a multicore processor or other SoC. Assume that this write transaction targets a device memory <NUM> coupled to a device <NUM>, which may be an accelerator device coupled to host processor <NUM> via a CXL bus.

With embodiments herein, host processor <NUM> directly forward s this memory write request to device <NUM> without performing a prefetch process, leading to a direct store to device memory <NUM> by device <NUM>. Note that this direct store is issued in connection with a snoop invalidate message to maintain coherency. This is so, since in this flow host processor <NUM> issues the direct store without first performing a prefetch process. This snoop invalidate message may be used to cause the device to snoop its caches and merge any corresponding data with the data received from host processor <NUM>. In this way, there is reduced messaging between host processor <NUM> and device <NUM>. After the data has been written to the requested location in device memory <NUM>, a completion is sent back to host processor <NUM> via device <NUM>.

With a flow as in <FIG>, device coherency management is eased. That is, in embodiments, incoming RDMA transactions directed to device-attached memory may proceed directly to the device (via the host processor) without the host processor obtaining ownership of data of the transactions. Instead without an embodiment when a PCIe device sends a write request targeting device-attached memory, to maintain coherence the host processor first acquires ownership of the line. Such operation incurs a bias flip in the device for the page, from device bias to host bias. Thus without an embodiment before the device can consume the data that was written to at this page, it would require an update of bias to device bias. This is sub-optimal for performance since it leads to pipeline delays at the device. And with embodiments, instead of a device sending a separate dedicated request to the host processor to flip the line back to device bias, which consumes bandwidth and latency, the device may issue the request as a response to a write message from the host processor.

Referring now to <FIG>, shown is a flow diagram of a method in accordance with another embodiment of the present invention. More specifically, method <NUM> of <FIG> is a method for performing a bias flip operation in an optimized manner. In embodiments herein, method <NUM> may be performed at least in part by circuitry within an accelerator device such as coupled to a host processor via a CXL bus and having a device-attached memory. As such method <NUM> may be performed by hardware circuitry, firmware, software and/or combinations thereof.

As illustrated, method <NUM> begins by receiving a memory invalidation request from a host processor within the device (block <NUM>). More specifically, this memory invalidation request may be a request from the host processor for the device to invalidate a data block that comprises a cache line of data that the host processor seeks to use. In implementations herein, understand that this cache line may be the subject of an incoming write request such as an RDMA request from a remote device coupled to the host processor. In response to this memory invalidation request, control next passes to diamond <NUM> to determine whether a bias for this cache line is set for a device bias. Note that such bias status may be stored in a coherency structure within the device (e.g., within circuitry <NUM> in device <NUM> of <FIG>) that stores, for each data block (which may be in cache line granularity, page granularity or even higher) in device-attached memory a bias indicator to indicate whether the corresponding data block is owned by the device or by the host.

If it is determined at diamond <NUM> that the bias is currently set for device bias, control passes to block <NUM> where the bias may be changed. More specifically, the device may update the bias for this data block to set it to temporary host bias so that the data block can be used by the host processor. In an embodiment, this temporary host bias may be indicated by adding an entry to a blocking structure for the data block (e.g., cache line). This blocking structure may include entries to identify cache lines acquired by the host processor. Stored entries correspond to cache lines within the device-attached memory that have a host bias. Such blocking entries may remain in place until the device has successfully flipped the bias of that cache line back to device bias. Note that a blocking entry prevents any device-initiated request to that address from making forward progress to ensure coherency. Entries in this blocking structure thus may be used to identify a temporary host bias.

Still with reference to <FIG>, next control passes to block <NUM> where the device may send a use once response to the host processor. In an embodiment, the device may send a completion message having a use once indicator to indicate to the host processor that it is allowed to use the data only once and thereafter to return the data to the device. Understand that in response to this use once indicator of the completion message, the host processor may set a status for the data block to a use once status such that the host processor may use the data once, e.g., to update the data block and thereafter to return the data block to the device.

Thus as further illustrated in <FIG>, control next passes to block <NUM> where at a later time (after the single use by the host processor) a memory write request is received in the device for this data block. In response to this memory write request, the device may cause the device-attached memory to store the data block (block <NUM>). Also in response to this storage of the data block, a completion may be sent back to the host processor to indicate successful storage.

Still referring to <FIG>, in response to this completion, the host processor may send a memory read forward message that is received in the device for the data block (block <NUM>). Finally, at block <NUM> in response to this memory read forward message, the device may change the bias for this data block to device bias. Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

With an embodiment as in <FIG>, a more optimized handling of a bias flip occurs, with reduced message traffic with reduced latency such that the device gains faster ownership of the data block. Note that the use once semantic response causes the host processor to self-invalidate the line once it has used it once and written it back to the device, thus allowing the device to retain the line in device bias. Such lines may be located in pages in device memory for which the device wants to retain device bias. These are typically the buffers that the PCIe device is producing into that the accelerator device intends to consume.

Referring now to <FIG>, shown is a timing diagram illustrating operation of a ordered store operation in accordance with another embodiment of the present invention. As shown in <FIG> in a computing system <NUM>, which may be a server platform configured similarly as platform <NUM> of <FIG>, an incoming memory write request may be received in a NIC <NUM>. NIC <NUM> forwards this memory request, which does not have a set relaxed ordering indicator, to a host processor <NUM>. Instead assume that this write transaction is strongly ordered, such as a flag write operation to indicate that a plurality of prior RDMA write operations have completed. This flag may set to indicate to a device <NUM> that data of prior bulk RDMA writes into a device-attached memory <NUM> may be consumed. As a strongly ordered write, host processor <NUM> may ensure that all preceding writes have made it to device-attached memory <NUM> before setting the flag.

In this example, host processor <NUM> may perform a prefetch process by issuing a memory invalidation request to device <NUM>. However in an embodiment, device <NUM> may respond to this memory invalidation request with a special command, namely a use once command. This command grants a time-limited permission for the host processor to use the data only once and then provide the data for storage in device memory <NUM>.

As further shown in <FIG>, after host processor <NUM> uses this data once, it sends a memory write request to device <NUM>, leading to a store of the data (possibly updated by host processor <NUM>) to device memory <NUM> by device <NUM>. After the data has been written to the requested location in device memory <NUM>, a completion is sent back to host processor <NUM> via device <NUM>. In turn, this completion causes host processor <NUM> to release the temporary host bias by sending a memory read forward message. As seen, this message causes device <NUM> to update bias back to device bias.

Thus with embodiments, DMA transactions from a PCIe device to an accelerator device may result in a selective non-allocating flow without hints on the incoming transactions. And, DMA transactions from a PCIe device to the accelerator device may occur without causing a bias flip.

Referring now to <FIG>, shown is a block diagram of a system in accordance with another embodiment of the present invention. As shown in <FIG>, a system <NUM> may be any type of computing device, and in one embodiment may be a server system. In the embodiment of <FIG>, system <NUM> includes multiple CPUs 710a,b that in turn couple to respective system memories 720a,b which in embodiments may be implemented as double data rate (DDR) memory. Note that CPU <NUM> may couple together via an interconnect system <NUM> such as an Intel® Ultra Path Interconnect or other processor interconnect technology.

To enable coherent accelerator devices and/or smart input/output (IO) devices to couple to CPUs <NUM> by way of potentially multiple communication protocols, a plurality of interconnects 730a1-b2 may be present. In an embodiment, each interconnect <NUM> may be a given instance of a CXL bus to enable RDMA communications to occur in an optimized manner as described herein.

In the embodiment shown, respective CPUs <NUM> couple to corresponding field programmable gate arrays (FPGAs)/accelerator devices 750a,b and smart I/O devices 760a,b. As further illustrated in <FIG>, device-attached memories 770a,b may couple to FPGA/accelerator devices <NUM>. With an arrangement as in <FIG>, CPUs <NUM> may perform direct writes of incoming RDMA write requests into device-attached memories <NUM> using the techniques described herein, and without the benefit of hint information provided in the incoming requests.

Turning next to <FIG>, an embodiment of a SoC design in accordance with an embodiment is depicted. As a specific illustrative example, SoC <NUM> may be configured for insertion in any type of computing device, ranging from portable device to server system. Here, SoC <NUM> includes <NUM> cores <NUM> and <NUM>. Cores <NUM> and <NUM> may conform to an Instruction Set Architecture, such as an Intel® Architecture Core™-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or adopters. Cores <NUM> and <NUM> are coupled to cache controller <NUM> that is associated with bus interface unit <NUM> and L2 cache <NUM> to communicate with other parts of system <NUM> via an interconnect <NUM>. As seen, bus interface unit <NUM> includes a DMA circuit <NUM> configured to optimize incoming RDMA write requests (even in the absence of associated hint information) such that they are directly forwarded to an external device-attached memory (not shown in <FIG>), without seeking a prefetch or otherwise obtaining ownership of data of the requests, as described herein.

Interconnect <NUM> provides communication channels to the other components, such as a Subscriber Identity Module (SIM) <NUM> to interface with a SIM card, a boot ROM <NUM> to hold boot code for execution by cores <NUM> and <NUM> to initialize and boot SoC <NUM>, a SDRAM controller <NUM> to interface with external memory (e.g., DRAM <NUM>), a flash controller <NUM> to interface with non-volatile memory (e.g., flash <NUM>), a peripheral controller <NUM> (e.g., an eSPI interface) to interface with peripherals, video codec <NUM> and video interface <NUM> to display and receive input (e.g., touch enabled input), GPU <NUM> to perform graphics related computations, etc. In addition, the system illustrates peripherals for communication, such as a Bluetooth module <NUM>, <NUM> modem <NUM>, GPS <NUM>, and WiFi <NUM>. Also included in the system is a power controller <NUM>. Further illustrated in <FIG>, system <NUM> may additional include interfaces including a MIPI interface <NUM>, e.g., to a display and/or an HDMI interface <NUM> also which may couple to the same or a different display.

Referring now to <FIG>, shown is a block diagram of a system in accordance with an embodiment of the present invention. As shown in <FIG>, multiprocessor system <NUM> includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. As shown in <FIG>, each of processors <NUM> and <NUM> may be many core processors including representative first and second processor cores (i.e., processor cores 974a and 974b and processor cores 984a and 984b).

In the embodiment of <FIG>, processors <NUM> and <NUM> further include point-to point interconnects <NUM> and <NUM>, which couple via interconnects <NUM> and <NUM> (which may be CXL buses) to accelerator devices <NUM> and <NUM> (respectively coupled to device-attached memories <NUM> and <NUM>). In this way, processors <NUM> and <NUM> optimize incoming RDMA write request handling by directly forwarding such requests to device-attached memories <NUM> and <NUM>, without seeking a prefetch or otherwise obtaining ownership of data of the requests, as described herein.

Still referring to <FIG>, first processor <NUM> further includes a memory controller hub (MCH) <NUM> and point-to-point (P-P) interfaces <NUM> and <NUM>. Similarly, second processor <NUM> includes a MCH <NUM> and P-P interfaces <NUM> and <NUM>. As shown in <FIG>, MCH's <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of system memory (e.g., DRAM) locally attached to the respective processors. First processor <NUM> and second processor <NUM> may be coupled to a chipset <NUM> via P-P interconnects <NUM> and <NUM>, respectively. As shown in <FIG>, chipset <NUM> includes P-P interfaces <NUM> and <NUM>.

Furthermore, chipset <NUM> includes an interface <NUM> to couple chipset <NUM> with a high performance graphics engine <NUM>, by a P-P interconnect <NUM>. As shown in <FIG>, various input/output (I/O) devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. Various devices may be coupled to second bus <NUM> including, for example, a keyboard/mouse <NUM>, communication devices <NUM> and a data storage unit <NUM> such as a disk drive or other mass storage device which may include code <NUM>, in one embodiment. In an embodiment, one such communication device may be a NIC that can receive incoming RDMA write requests from one or more I/O devices <NUM> and direct along to one of processors <NUM> and <NUM> without performing the overhead of analyzing the request to determine destination and applying a TPH or other hint information, as described herein. Further, an audio I/O <NUM> may be coupled to second bus <NUM>.

Note that the terms "circuit" and "circuitry" are used interchangeably herein. As used herein, these terms and the term "logic" are used to refer to alone or in any combination, analog circuitry, digital circuitry, hard wired circuitry, programmable circuitry, processor circuitry, microcontroller circuitry, hardware logic circuitry, state machine circuitry and/or any other type of physical hardware component. Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to a communication device, and instead other embodiments can be directed to other types of apparatus for processing instructions, or one or more machine readable media including instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.

Claim 1:
A processor comprising:
one or more cores to execute instructions;
at least one cache memory; and
a coherence circuit (<NUM>) coupled to the at least one cache memory, the coherence circuit (<NUM>) having a direct memory access, DMA, circuit (<NUM>) to receive a write request from a network interface card, NIC (<NUM>), and based at least in part on an address of the write request, to directly send the write request to an accelerator device (<NUM>) coupled to the processor via a first bus, to cause the accelerator device (<NUM>) to store data of the write request to a device-attached memory (<NUM>), wherein when the write request has a set relaxed ordering indicator, the DMA circuit (<NUM>) is to directly send the write request to the accelerator device without a prefetch operation by the processor to obtain ownership.