Patent Description:
The use of power devices, such as uninterruptible power supplies (UPS), to provide regulated, uninterrupted power for sensitive and/or critical loads, such as computer systems and other data processing systems, is known. Known uninterruptible power supplies include on-line UPS's, off-line UPS's, line interactive UPS's as well as others. On-line UPS's provide conditioned AC power as well as back-up AC power upon interruption of a primary source of AC power. Off-line UPS's typically do not provide conditioning of input AC power but do provide back-up AC power upon interruption of the primary AC power source. Line interactive UPS's are similar to off-line UPS's in that they switch to battery power when a blackout occurs but also typically include a multi-tap transformer for regulating the output voltage provided by the UPS.

A prior art switching circuit used in such devices is disclosed in <CIT>.

The invention is directed to a power switching circuit as claimed in independent claim <NUM> and to the corresponding method as claimed in independent claim <NUM>.

According to one embodiment, the unipolar diode of each switching device of the plurality of switching devices has an anode coupled to the second source and a cathode coupled to the first drain.

According to another embodiment, each switching device of the plurality of switching devices is configured such that the first gate is coupled to the second source. In one embodiment, the first transistor of each switching device is a depletion mode transistor and the second transistor of each switching device is an enhancement mode transistor. In another embodiment, the first transistor of each switching device is a GaN HEMT and the second transistor of each switching device is a low-voltage FET. In one embodiment, the unipolar diode of each switching device is a Schottky Barrier diode. In another embodiment, the GaN HEMT and the low-voltage FET are contained on at least one substrate in a single package. In one embodiment, each switching device is fabricated such that the Schottky Barrier diode is connected externally to the package containing the GaN HEMT and the low-voltage FET. IN another embodiment, each switching device is fabricated such that the Schottky Barrier diode is included on the at least one substrate in the package containing the GaN HEMT and the low-voltage FET.

According to one embodiment, the third terminal is configured to be coupled to an AC power source, the first terminal and the second terminal are configured to be coupled to a DC bus, and the power switching circuit is configured to be operated as a power converter in a UPS. In another embodiment, the first terminal and the second terminal are configured to be coupled to a DC bus, the third terminal is configured to be coupled to a load, and the power switching circuit is configured to operate as a power inverter in a UPS.

According to one embodiment, diverting the transition current through the unipolar diode prevents the transition voltage from exceeding the degradation threshold of the first transistor by reducing a forward recovery voltage of the bipolar body diode of the second transistor. In one embodiment, the first transistor is a GaN HEMT, the second transistor is a low-voltage FET, and the unipolar diode is a Schottky Barrier diode.

According to one embodiment, regulating the transition voltage via the unipolar diode reduces a forward recovery voltage of the bipolar body diode of the second transistor to prevent the transition voltage from exceeding the degradation threshold of the first transistor. In one embodiment, the first transistor is a GaN HEMT, the second transistor is a low-voltage FET, and the unipolar diode is a Schottky Barrier diode.

The figures are included to provide illustration and a further understanding of the various aspects and embodiments and are incorporated in and constitute a part of this specification but are not intended as a definition of the limits of the invention. In the figures:.

Examples of the methods and systems discussed herein are not limited in application to the details of construction and the arrangement of components set forth in the following description or illustrated in the accompanying drawings. The methods and systems are capable of implementation in other embodiments and of being practiced or of being carried out in various ways. Examples of specific implementations are provided herein for illustrative purposes only and are not intended to be limiting. In particular, acts, components, elements and features discussed in connection with any one or more examples are not intended to be excluded from a similar role in any other examples.

Any references to examples, embodiments, components, elements or acts of the systems and methods herein referred to in the singular may also embrace embodiments including a plurality, and any references in plural to any embodiment, component, element or act herein may also embrace embodiments including only a singularity. References in the singular or plural form are not intended to limit the presently disclosed systems or methods, their components, acts, or elements. The use herein of "including," "comprising," "having," "containing," "involving," and variations thereof is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. References to "or" may be construed as inclusive so that any terms described using "or" may indicate any of a single, more than one, and all of the described terms.

As discussed above, power devices, such as uninterruptible power supplies (UPS), are oftentimes used to provide regulated, uninterrupted power to sensitive and/or critical loads. A conventional online UPS rectifies input AC power provided by an electric utility using a Power Factor Correction circuit (PFC) to provide DC power to at least one DC bus. The rectified DC power on the DC busses is typically used to charge a battery while mains power is available. In the absence of mains power, the battery discharges and provides DC power to the DC buses. From the DC power on the DC buses, an inverter generates an AC output voltage that is provided to a load. Since the DC bus is powered either by mains or the battery, the output power of the UPS is uninterrupted if the mains fails and the battery is sufficiently charged. Typical online UPS's may also operate in a bypass mode where unconditioned power with basic protection is provided directly from an AC power source to a load via a bypass line.

<FIG> is a block diagram of one embodiment of a UPS <NUM> that provides regulated power from input AC power received at an input <NUM>, as well as back-up power from a battery <NUM>, to an output <NUM>. The UPS <NUM> includes a converter <NUM>, a DC bus <NUM>, an inverter <NUM>, and a controller <NUM> for controlling the converter and the inverter. The converter <NUM> is coupled to the input <NUM>, the inverter <NUM> is coupled to the output <NUM>, and the DC bus <NUM> is coupled between the converter <NUM> and the inverter <NUM>.

The input <NUM> is configured to receive input AC power having an input voltage level from an AC power source. The controller <NUM> monitors the input AC power received by the input <NUM> and is configured to operate the UPS <NUM> in different modes of operation based on the status of the input AC power received by the input <NUM>. When AC power provided to the input <NUM> is acceptable (i.e., above an input power threshold), the controller <NUM> operates the UPS <NUM> in an online mode of operation.

In the online mode of operation, AC power from the input <NUM> can be provided to the converter <NUM>. According to one embodiment, the converter <NUM> is a Power Factor Correction (PFC) converter <NUM>; however, in other embodiments, other types of converters may be utilized. The controller <NUM> operates the converter <NUM> to convert the AC power into DC power and provide the DC power to the DC bus <NUM>. DC power from the DC bus <NUM> is provided to the inverter <NUM>. The controller <NUM> operates the inverter <NUM> to convert the DC power into regulated AC power and provide the regulated AC power to a load coupled to the output <NUM>.

When AC power provided to the input <NUM> is not acceptable (i.e., below an input power threshold), the controller <NUM> operates the UPS <NUM> in a backup mode of operation. In the backup mode of operation, DC power from the battery <NUM> is provided to the DC bus <NUM>. The inverter <NUM> receives the DC power from the DC bus <NUM>, and the controller <NUM> operates the inverter <NUM> to convert the DC power from the DC bus <NUM> into regulated AC power and provide the regulated AC power to the output <NUM>.

As described above, a UPS can include various types of power converters for converting AC power to DC power, DC power to AC power, and DC power from one DC voltage level to another. For example, a conventional UPS typically includes two quadrant and/or four quadrant converters such as inverters, synchronous buck converters, boost converters, etc. These various power converters are known to include power switching circuits utilizing switching devices such as Field-Effect Transistors (FETs) and Insulated-Gate Bipolar Transistors (IGBTs). Gallium Nitrate (GaN) is a common wide-bandgap material used in the fabrication of FETs for power switching applications. GaN FETs, compared to Silicon FETs or IGBTs, can offer very high switching speeds, and thus reduce switching losses, enabling high frequency power converter designs. GaN FETs also can experience a much lower on-resistance at high voltages, even at high temperatures, compared to alternative switching devices.

One type of GaN technology commonly used in conventional power switching circuits is enhancement mode GaN (e-GaN). e-GaN FETs are normally-off devices, and can provide benefits such as lower on resistance, faster switching speeds, lower power consumption, and smaller packages compared to alternative switching devices such as Silicon FETs. However, with respect to power switching applications, e-GaN FETs can exhibit limitations such as low reliability, low gate voltage margins, and insufficient thermal performance.

Another type of GaN technology is Cascode GaN. Cascode GaN includes the utilization of a depletion mode GaN High-Electron-Mobility Transistor (HEMT). The GaN HEMT is a normally-on device. In a conventional Cascode GaN device, a normally-off, enhancement mode low-voltage Silicon FET is connected to a GaN HEMT in a cascode structure such that, in combination, the GaN HEMT and the low-voltage FET function as a normally-off device. For example, <FIG> is a schematic diagram illustrating a conventional Cascode GaN device <NUM>. As illustrated in <FIG>, the source <NUM> of the GaN HEMT <NUM> is coupled to the drain <NUM> of the low-voltage FET <NUM>. The low-voltage FET <NUM> includes a body diode <NUM> having an anode <NUM> coupled to the source <NUM> and a cathode <NUM> coupled to the drain <NUM>. The source <NUM> of the low-voltage FET <NUM> is also coupled to the gate <NUM> of the GaN HEMT <NUM>. The Cascode GaN device <NUM> is turned on and off by applying a voltage across the gate <NUM> and the source <NUM> of the low-voltage FET <NUM>.

Cascode GaN technology can address many of the limitations of e-GaN, as the utilization of GaN HEMTs and low-voltage FETs improves reliability at a lower cost. Cascode GaN devices also turn on fully at 10V and can tolerate ± 20V, providing a much higher gate voltage margin than the 1V margin of e-GaN devices. In addition, Cascode GaN devices are typically produced in standard transistor outline (TO) packages which provide additional clearance from printed circuit boards compared to the surface mount device (SMD) packages of e-GaN devices. The additional clearance from the printed circuit board surface provided by the TO package results in improved thermal performance.

However, despite the advantages discussed above, conventional Cascode GaN devices can experience poor-efficiency in power switching applications. The gates of GaN HEMTs included in Cascode GaN devices are typically designed for +5V/-40V operation with a pinch-off voltage of -20V. If the gate-to-source voltage applied to the GaN HEMT exceeds +5V, charges are injected into the GaN HEMT and the drain-to-source on-resistance (Rds(on)) of the GaN HEMT increases. The injected charge will only begin to dissipate when the gate-to-source voltage of the GaN HEMT is negatively biased below -20V for an extended period of time. In some cases, the GaN HEMT is required to be held in the pinch-off region for multiple hours to fully recover. When used in power switching applications, conventional Cascode GaN devices are often susceptible to this increasing Rds(on) effect and as a result device efficiency is degraded.

For example, <FIG> is a schematic diagram of a typical half-bridge inverter <NUM> including a high-side Cascode GaN device <NUM> coupled to a low-side Cascode GaN device <NUM>. A positive input terminal +VDC is coupled to the drain <NUM> of the GaN HEMT <NUM> of the high-side device <NUM> and a negative input terminal -VDC is coupled to the source <NUM> of the low-voltage FET <NUM> of the low-side device <NUM>. A common load <NUM> is shared between the high-side device <NUM> and the low-side device <NUM>.

is a graph illustrating the current and voltage waveforms of the body diode <NUM> of the low-voltage FET <NUM> during a transition period (Ttr) <NUM> of the half-bridge inverter <NUM>. When the high-side device <NUM> is turned on, the low-side device <NUM> is turned off and current from the positive input terminal +VDC is switched through the high-side device <NUM> to the load <NUM>. While the high-side device <NUM> is on, a reverse voltage <NUM> is applied to the body diode <NUM> of the low-voltage FET <NUM>. Subsequently, when the high-side device <NUM> is turned off, a transition current <NUM> is transferred to the low-side device <NUM>, which remains turned off. The transition current <NUM> transferred to the low-side device <NUM> begins to follow leakage path <NUM> through the body diode <NUM> of the low-voltage FET <NUM> and the GaN HEMT <NUM> in the reverse direction, as illustrated in <FIG>.

Due to the transition current <NUM> resulting from the turn-off speed of the high-side device <NUM>, the body diode <NUM> of the low-voltage FET <NUM> develops a forward recovery voltage <NUM>. The amplitude of the forward recovery voltage <NUM> depends on the transition current <NUM>, the p-n junction structure of the body diode <NUM> of the low-voltage FET <NUM>, and any inductance incurred from bonding wires, leads, and contacts. The forward recovery voltage <NUM> results in a significant voltage drop across the body diode <NUM> of the low-voltage FET <NUM>, and thus a positive gate-to-source voltage is applied to the GaN HEMT <NUM>. Once the positive gate-to-source voltage applied to the GaN HEMT <NUM> exceeds +5V, charges are injected into the GaN HEMT <NUM> and as a result the Rds(on) of the GaN HEMT <NUM> increases.

The transition current <NUM> following leakage path <NUM> through the body diode <NUM> of the low-voltage FET <NUM> stabilizes at a normal forward current <NUM> and the body diode <NUM> of the low-voltage FET <NUM> begins to operate with a normal forward voltage <NUM>. However, the Rds(on) of the GaN HEMT <NUM> remains higher than normal until the GaN HEMT <NUM> is pinched-off such that the injected charge is permitted to dissipate. This increase in Rds(on) degrades the efficiency of the low-side device <NUM> and thus the half-bridge inverter <NUM>. Accordingly, conventional Cascode GaN devices are typically restricted to low-current, low-speed power switching applications in order to maintain operational efficiency.

A more efficient, cost-effective, and reliable switching device for use in high-current, high-speed power switching applications is provided. In at least one embodiment, current provided to a Cascode GaN switching device is managed to maintain high operational efficiency in high-speed power switching applications across an expanded range of high-current loads. More specifically, current is diverted through a unipolar diode such that the GaN HEMT of the Cascode GaN switching device never develops a forward recovery voltage.

<FIG> is a block diagram of one embodiment of a power switching circuit <NUM> in accordance with aspects described herein. The power switching circuit <NUM> may be used, for example, in the converter <NUM> in a UPS similar to the UPS <NUM> shown in <FIG>. The power switching circuit <NUM> includes a first switching device <NUM> coupled between an input <NUM> and a positive output <NUM>, and a second switching device <NUM> coupled between the input <NUM> and a negative output <NUM>. In one embodiment, the input <NUM> may be configured to receive AC power from an AC power source, and the power switching circuit <NUM> may be operated as a half-bridge converter to convert the received AC power into DC power, and to provide the DC power to the positive output <NUM> and the negative output <NUM>. In other embodiments, the power switching circuit <NUM> may include a third and a fourth switching device and be configured to operate as a full-bridge converter. In some embodiments, the negative output <NUM> may be coupled to a ground or neutral connection.

<FIG> is a block diagram of one embodiment of a power switching circuit <NUM> in accordance with aspects described herein. The power switching circuit <NUM> may be used, for example, in the inverter <NUM> in a UPS similar to the UPS <NUM> shown in <FIG>. The power switching circuit <NUM> is configured such that the first switching device <NUM> is coupled between a positive input <NUM> and an output <NUM>, and the second switching device <NUM> is coupled between a negative input <NUM> and the output <NUM>. In one embodiment, the positive input <NUM> and the negative input <NUM> may be configured to receive DC power from a DC power source, such as a DC bus or a battery, and the power switching circuit <NUM> may be operated as a half-bridge inverter to convert the received DC power into AC power, and to provide the AC power to the output <NUM>. In other embodiments, the power switching circuit <NUM> may include a third and a fourth switching device and be configured to operate as a full-bridge inverter. In some embodiments, the negative input <NUM> may be coupled to a ground or neutral connection.

In another embodiment, the power switching circuit <NUM> may be configured to operate as a half-bridge inverter similar to the half-bridge inverter <NUM> shown in <FIG>. For example, the first switching device <NUM> may be configured to operate as the high-side device <NUM> and second switching device <NUM> may be configured to operate as the low-side device <NUM>.

<FIG> is a schematic diagram of one embodiment of a switching device <NUM> in accordance with aspects described herein. The switching device <NUM> may be used, for example, as the first switching device <NUM> or the second switching device <NUM> of power switching circuit <NUM> as shown in <FIG>, or any other switching device in a power switching circuit.

The switching device <NUM> includes a normally-on, depletion mode GaN HEMT <NUM>. The source <NUM> of the GaN HEMT <NUM> is coupled to the drain <NUM> of a normally-off, enhancement mode low-voltage FET <NUM>. The GaN HEMT <NUM> and the low-voltage FET <NUM> are coupled in a cascode structure such that, in combination, the GaN HEMT <NUM> and the low-voltage FET <NUM> function as a normally-off device. The low-voltage FET <NUM> includes a body diode <NUM> having an anode <NUM> coupled to the source <NUM> and a cathode <NUM> coupled to drain <NUM>. A Schottky Barrier diode (SBD) <NUM> is coupled across the GaN HEMT <NUM> and low-voltage FET <NUM>. The anode <NUM> of the SBD <NUM> is coupled to the source <NUM> of the low-voltage FET <NUM> and the gate <NUM> of the GaN HEMT <NUM>. The cathode <NUM> of the SBD <NUM> is coupled to the drain <NUM> of the GaN HEMT <NUM>. In one embodiment, the SBD <NUM> is a Silicon Carbide (SiC) Schottky Barrier diode; however, in other embodiments, a different type of Schottky Barrier diode, or any other unipolar diode, can be utilized.

In at least one embodiment, the switching device <NUM> may experience a transition current during a transition period of a power switching circuit, similar to the transition period <NUM> and transition current <NUM> as discussed above in regard to <FIG>. The body diode <NUM> of the low-voltage FET <NUM> is a bipolar device having a p-n junction, and thus will develop a forward recovery voltage during the transition period when the transition current is applied to the source <NUM> of the low-voltage FET <NUM>. However, the SBD <NUM> is a unipolar device which does not have a p-n junction and thus becomes forward biased before the body diode <NUM> of the low-voltage FET <NUM> develops a forward recovery voltage. Being that the anode <NUM> of the SBD <NUM> is coupled to the source <NUM> of the low-voltage FET <NUM>, a majority of the transition current is diverted through the SBD <NUM>, bypassing the low-voltage FET <NUM> and the GaN HEMT <NUM>. By diverting current through the SBD <NUM>, the forward recovery voltage of the body diode <NUM> of the low-voltage FET <NUM> is reduced during the transition period.

Once the transition period is over, the GaN HEMT <NUM> is turned on by enabling the low-voltage FET <NUM>, and current is shared between the GaN HEMT <NUM> and the SBD <NUM>. In one embodiment, a controller, such as controller <NUM>, may be utilized to determine that the transition period is over and to enable the low-voltage FET <NUM>. While the GaN HEMT <NUM> is turned on, the voltage drop of the SBD <NUM> becomes much higher than the GaN HEMT <NUM>, and as a result a majority of the current is switched through the GaN HEMT <NUM> and the low-voltage FET <NUM>. By diverting the transition current through the SBD <NUM> during the transition period and avoiding the forward recovery voltage of the body diode <NUM> of the low-voltage FET <NUM>, the switching device <NUM> is able to maintain a high-level of efficiency in high-speed, high current power switching applications.

According to at least one embodiment the switching device <NUM> is fabricated such that the SBD <NUM> is connected externally to a substrate <NUM> containing the GaN HEMT <NUM> and the low-voltage FET <NUM>. In one embodiment, the substrate containing the GaN HEMT <NUM> and the low-voltage FET <NUM> is a Cascode GaN device. In another embodiment, as illustrated in <FIG>, a switching device <NUM> is shown that is similar to switching circuit <NUM>, except that THE switching device <NUM> is fabricated such that the SBD <NUM> is included on the same substrate <NUM> containing the GaN HEMT <NUM> and the low-voltage FET <NUM>. By including the SBD <NUM>, GaN HEMT <NUM>, and low-voltage FET <NUM> on the same substrate <NUM>, any additional voltage drops associated with boding wires and leads can be minimized to further improve operational efficiency. In other embodiments, the SBD <NUM>, GaN HEMT <NUM>, and low-voltage FET <NUM> may be fabricated on multiple substrates included in a single package or chip. In one embodiment, the single package is a transistor outline (TO) package.

In at least one embodiment, current provided to a Cascode GaN switching device is managed to maintain high operational efficiency in high-speed power switching applications across an expanded range of high-current loads. More specifically, current is managed such that a forward recovery voltage is not applied to the GaN HEMT of the Cascode GaN switching device in a manner which degrades the Cascode GaN switching device.

<FIG> is a schematic diagram of another embodiment of a switching device <NUM> in accordance with aspects described herein. The switching device <NUM> may be used, for example, as the first switching device <NUM> or the second switching device <NUM> of power switching circuit <NUM> as shown in <FIG>, or any other switching device in a power switching circuit.

The switching device <NUM> includes a normally-on, depletion mode GaN HEMT <NUM>. The source <NUM> of the GaN HEMT <NUM> is coupled to the drain <NUM> of a normally-off, enhancement mode low-voltage FET <NUM>. The GaN HEMT <NUM> and the low-voltage FET <NUM> are coupled in a cascode structure such that, in combination, the GaN HEMT <NUM> and the low-voltage FET <NUM> function as a normally-off device. The low-voltage FET <NUM> includes a body diode <NUM> having an anode <NUM> coupled to the source <NUM> and a cathode <NUM> coupled to the drain <NUM>. A Schottky Barrier diode (SBD) <NUM> is coupled across the GaN HEMT <NUM>. The anode <NUM> of the SBD <NUM> is coupled to the gate <NUM> of the GaN HEMT <NUM> and the source <NUM> of the low-voltage FET <NUM>. The cathode <NUM> of the SBD <NUM> is coupled to the source <NUM> of the GaN HEMT <NUM>. In one embodiment, the SBD <NUM> is a Silicon (Si) Schottky Barrier diode; however, in other embodiments, a different type of Schottky Barrier diode, or any other unipolar diode, can be utilized.

In at least one embodiment, the switching device <NUM> may experience a transition current during a transition period of a power switching circuit, similar to the transition period <NUM> and transition current <NUM> as discussed above in regard to <FIG>. The body diode <NUM> of the low-voltage FET <NUM> is a bipolar device having a p-n junction, and thus will develop a forward recovery voltage during a transition period when a transition current is applied to the source <NUM> of the low-voltage FET <NUM>. However, the SBD <NUM> is a unipolar device which does not have a p-n junction and thus becomes forward biased before the body diode <NUM> of the low-voltage FET <NUM> develops a forward recovery voltage. Being that anode <NUM> of the SBD <NUM> is coupled to the gate <NUM> of the GaN HEMT <NUM> and the cathode <NUM> of the SBD <NUM> is coupled to the source <NUM> of the GaN HEMT <NUM>, the gate-to-source voltage applied to the GaN HEMT <NUM> cannot exceed the forward voltage drop of the SBD <NUM>. The forward voltage drop of the SBD <NUM> is typically less than 1V, thus the gate-to-source voltage of the GaN HEMT <NUM> is protected from exceeding +5V and charges will not be injected into the GaN HEMT <NUM>.

Once the transition period is over, the GaN HEMT <NUM> is turned on by enabling the low-voltage FET <NUM>, and current is shared between the low-voltage FET <NUM> and the SBD <NUM>. In one embodiment, a controller, such as controller <NUM>, may be utilized to determine that the transition period is over and to enable the low-voltage FET <NUM>. While the low-voltage FET <NUM> is enabled, the voltage drop of the SBD <NUM> becomes much higher than the low-voltage FET <NUM>, and as a result a majority of the current is switched through the GaN HEMT <NUM> and the low-voltage FET <NUM>. By regulating the forward recovery voltage of the body diode <NUM> and preventing the gate-to-source voltage of the GaN HEMT <NUM> from exceeding +5V, the switching device <NUM> is able to maintain a high-level of efficiency in high-speed, high-switching applications.

According to at least one embodiment, the switching device <NUM> is fabricated such that the SBD <NUM> is connected externally to a substrate <NUM> containing the GaN HEMT <NUM> and the low-voltage FET <NUM>. In one embodiment, the substrate <NUM> containing the GaN HEMT <NUM> and the low-voltage FET <NUM> is a Cascode GaN device. In another embodiment, the switching device <NUM> is fabricated such that the SBD <NUM> is included on the substrate <NUM> containing the GaN HEMT <NUM> and the low-voltage FET <NUM>. By including the SBD <NUM>, GaN HEMT <NUM>, and low-voltage FET <NUM> on the same substrate <NUM>, any additional voltage drops associated with bonding wires and leads can be minimized to further improve operational efficiency. In other embodiments, the SBD <NUM>, GaN HEMT <NUM>, and low-voltage FET <NUM> may be fabricated on multiple substrates included in a single package or chip. In one embodiment, the single package is a transistor outline (TO) package.

As discussed above, the controller <NUM> is configured to monitor and control operation of the UPS <NUM>. Using data stored in associated memory, the controller <NUM> is operable to execute one or more instructions that may result in the manipulation of one or more switching devices' conductive states. In some examples, the controller <NUM> can include one or more processors or other types of controllers. The controller <NUM> may perform a portion of the functions described herein on a processor, and perform another portion using an Application-Specific Integrated Circuit (ASIC) tailored to perform particular operations. Examples in accordance with the present invention may perform the operations described herein using many specific combinations of hardware and software and the invention is not limited to any particular combination of hardware and software components.

As described above, a more efficient, cost-effective, and reliable switching device for use in high-current, high-speed power switching applications is provided herein. The switching device can manage a transition current to prevent a transition voltage applied to the switching device from exceeding a degradation threshold. By preventing the applied transition voltage from exceeding the degradation threshold, the switching device can maintain high operational efficiency in high-speed power switching applications across an expanded range of high-current loads.

Claim 1:
A power switching circuit, comprising:
a first terminal (<NUM>);
a second terminal (<NUM>);
a third terminal (<NUM>); and
a plurality of switching devices (<NUM>, <NUM>), each switching device having:
a first GaN transistor (<NUM>) having a first gate, a first source (<NUM>), and a first drain;
a second transistor (<NUM>) having a second gate, a second source, a second drain coupled to the first source, and a bipolar body diode (<NUM>) coupled between the second drain and the second source; and
a unipolar diode (<NUM>) having an anode coupled to the first gate of the first GaN transistor and having a cathode coupled to the first source to regulate a transition voltage applied across the first gate and the first source during a transition period such that the transition voltage remains below a degradation threshold of the first GaN transistor during the transition period,
wherein a first switching device of the plurality of switching devices is coupled to the first terminal via the first drain and the third terminal via the second source, and a second switching device of the plurality of switching devices is coupled to the second terminal via the second source and the third terminal via the first drain.