Patent Description:
Vertical Field Effect Transistors (FETs) are suitable for high voltage applications due to their relatively high breakdown voltage, compared to FETs with shorter conduction channels. A trench field plate power Metal Oxide Semiconductor FET (MOSFET) is a type of vertical FET that typically employs reduced surface field (RESURF) action under the influence of field plates (shield electrodes) inside gate trenches. RESURF can achieve a lower on resistance (RDS(on)) while still maintaining a high breakdown voltage (BV). While the RESURF action can enable improvements in the BV- RDS(on) tradeoff, the sensitivity to variations in doping and/or dimensions is greatly increased. Further, the termination structures of trench field plate power MOSFET devices are especially significant since an improperly designed termination can cause the breakdown voltage to be low, thus forcing the MOSFET device to be under-designed so that the optimal BV- RDS(on) tradeoff cannot be achieved.

United States Patent Application, publication number <CIT>, discloses power semiconductor devices with features providing increased breakdown voltage. Disclosed is a Semiconductor device having a perimeter trench that encircles an array of trenches and mesas. (The perimeter trench may be discontinuous with one or more breaks of relatively small breaks, which may not significantly affect its effects. ) The perimeter trench comprises a dielectric layer lining its opposing side walls, and a conductive electrode disposed in the trench. Conductive electrode may be electrically coupled to a conductive layer, such as the shield runner, to receive a ground potential, or may be decoupled from any conductive layer bearing a potential, thereby being at a floating potential. Perimeter shield is spaced from the trench by a distance that is on the order of the spacing between adjacent trenches. A gap region is disposed between the perimeter shield and trench. No electrical potentials are coupled to the top of gap region by any conductive layer, and the potential in gap region is floating. When the perimeter trench electrode is at a floating potential, the potentials on it and the floating gap region can float to set equalizing potentials with respect to the drain potential, and can thereby reduce sensitivity to charge imbalances in gap region.

United States patent application, publication the <CIT> discloses termination implant enrichment for shielded gate MOSFETs, according to which a power semiconductor device can include a first trench shield electrode and a second trench shield electrode defined in a semiconductor region, the first and second trench shield electrodes each having a first portion disposed in an active region and a second portion disposed in a termination region. A trench of the first trench shield electrode and a trench of the second trench shield electrode can define a mesa of the semiconductor region therebetween. The device can further include an implant enrichment region disposed in the termination region, the implant enrichment region can be intersected by the first trench shield electrode and the second trench shield electrode, and can have a portion disposed in the mesa of the semiconductor region, the portion extending from the trench of the first trench shield electrode to the trench of the second trench shield electrode.

The accompanying figures in which like reference numerals refer to identical or functionally similar elements throughout the separate views, the figures are not necessarily drawn to scale, and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention. It is further noted that, in the following, the embodiments relating to <FIG> are not parts of the invention and are present for illustration purposes only.

In overview, the present disclosure concerns a semiconductor device with improved breakdown voltage characteristics and methodology for fabricating such a semiconductor device. In particular, embodiments entail a trench field plate power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a set of floating body segments formed between device trenches of the MOSFET. The floating body segments break up or otherwise isolate an active body area of the semiconductor device from a termination area of the semiconductor device. Further, the floating body segments are able to self-bias to an appropriate positive voltage. Accordingly, an electric field at a triple point region of the termination area can be effectively suppressed so that breakdown voltage roll-off at the termination area can be avoided. In some embodiments, the floating body segments are formed using the same body implant/diffusion process as the active body area of the device. Such an approach can circumvent the need for additional masks/process steps to create the floating body segments and thereby achieve enhancements in fabrication efficiency and cost savings.

The instant disclosure is provided to further explain in an enabling fashion at least one embodiment in accordance with the present invention. The disclosure is further offered to enhance an understanding and appreciation for the inventive principles and advantages thereof, rather than to limit in any manner the invention.

It should be understood that the use of relational terms, if any, such as first and second, top and bottom, and the like are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, some of the figures may be illustrated using various shading and/or hatching to distinguish the different elements. These different elements may be produced utilizing current and upcoming microfabrication techniques. Accordingly, although different shading and/or hatching is utilized in the illustrations, the different elements within the structural layers may be formed out of the same material.

Referring to <FIG>, <FIG> shows a plan view of a prior art trench power MOSFET <NUM>, <FIG> shows a cross-sectional view of prior art trench power MOSFET <NUM> taken along section line <NUM>-<NUM> of <FIG>, and <FIG> shows a cross-sectional view of prior art trench power MOSFET <NUM> taken along section line <NUM>-<NUM> of <FIG>. In this prior art example, MOSFET <NUM> includes a substrate <NUM> having opposed first and second major surfaces <NUM>, <NUM>, an active area <NUM> (e.g., generally denoted by a dashed line box), and a termination area <NUM> surrounding active area <NUM> (e.g., the area outside of the dashed line box).

Parallel insulated trenches <NUM> extend from first major surface <NUM> toward second major surface <NUM>. Each of trenches <NUM> includes a conductive field plate <NUM> (e.g., a first polysilicon layer) and a gate electrode <NUM> (e.g., a second polysilicon layer) overlying the shield plate <NUM>, with gate electrode <NUM> being separated from field plate <NUM> by a gate-field plate insulator <NUM> (see <FIG>). Field plate <NUM>, which may alternatively be referred to herein as shield plate <NUM>, extends longitudinally in each of trenches <NUM> in both of active and termination areas <NUM>, <NUM>. Whereas, gate electrode <NUM> extends longitudinally in each of trenches <NUM> in active area <NUM>, but is absent from trenches <NUM> in termination area <NUM>. Thus, the cross-sectional view of <FIG> shows trenches <NUM> in active area <NUM> lined with an insulator <NUM> (e.g., shield oxide), and with both shield plate <NUM> and gate electrode <NUM> separated by gate-field plate insulator <NUM>. Conversely, the cross-sectional view of <FIG> shows show trenches <NUM> in termination area <NUM> lined with insulator <NUM>, but with only shield plate <NUM>.

An insulated termination trench loop <NUM> surrounds termination area <NUM>. Termination trench <NUM> is also lined with insulator <NUM> and shield plate <NUM> (e.g., the first polysilicon layer) also resides in insulated termination trench loop <NUM>. Although both shield plates <NUM> and gate electrodes <NUM> may be formed of the same polysilicon material, shield plates <NUM> are illustrated with a light stippled pattern and gate electrodes <NUM> are illustrated with a darker stippled pattern to distinguish one from the other.

In the prior art trench power MOSFET <NUM>, a continuous body region <NUM> is formed in both active and termination areas <NUM>, <NUM> above an epitaxial layer <NUM> of substrate <NUM>. Body region <NUM> extends in the silicon mesas between trenches <NUM>, and a source implant region <NUM> may be formed overlying body region <NUM> between the pairs of trenches <NUM> in active area <NUM>. Source contacts <NUM> may be formed on first major surface <NUM> of substrate <NUM> overlying source implant region <NUM> and a drain contact <NUM> may be formed on second major surface <NUM> of substrate <NUM> underlying a drain region <NUM> of substrate <NUM>. For clarity, source implant region <NUM> and source contacts <NUM> are not shown in <FIG> so that continuous body region <NUM> may be more readily visualized. However, source implant region <NUM> and source contacts <NUM> are presented in <FIG>, with source contacts <NUM> positioned between pairs of trenches <NUM>.

In the example of <FIG>, drain region <NUM> may be an N++ doped substrate and insulated trenches <NUM> (with shield plates <NUM> and gate electrodes <NUM> formed therein) are etched into an N-epitaxial layer <NUM>. N-epitaxial layer <NUM> between pairs of insulated trenches <NUM> is also a lightly doped N-drift region <NUM> of MOSFET <NUM>, with body region <NUM> being formed of a P-type dopant (e.g., PHV) formed for a MOSFET channel, and gate electrodes <NUM> being formed between shield plates <NUM> and first major surface <NUM>. In this n-channel example, under reverse bias, a depletion region in drift region <NUM> (e.g., the epitaxial layer <NUM> between pairs of trenches <NUM>) grows under the influence of both a PN junction <NUM> (e.g., the junction between body region <NUM> and epitaxial layer <NUM>) and shield plates <NUM>.

Breakdown takes place at the bottom of drift region <NUM> in over-depletion situations where the charge in the silicon pillar between pairs of trenches <NUM> is low (e.g., narrow silicon pillar, low doping, thin insulator <NUM>). Breakdown takes place at the top of drift region <NUM> in under-depletion situations where the charge in the silicon pillar between pairs of trenches <NUM> is high (e.g., wide silicon pillar, high doping). As long as the breakdown occurs at the bottom of the drift region, the breakdown voltage (BV) increases with an increasing width <NUM> between trenches <NUM>. At a sufficiently high width <NUM>, the electric field at the top of drift region <NUM> increases and the breakdown voltage drops.

In the typical layout of trench MOSFET <NUM>, active area <NUM> of MOSFET <NUM> experiences generally two-dimensional reduced surface field (RESURF) action and the charge balance may be readily optimized. However, termination area <NUM> may have regions which experience a different RESURF action than active area <NUM>, and may therefore have a different breakdown voltage (BV). That is, the conventional layout of MOSFET <NUM> that includes termination trench loop <NUM> enclosing all of trenches <NUM> experiences a generally three-dimensional RESURF.

<FIG> shows a partial plan view of the prior art trench power MOSFET <NUM>. At termination area <NUM>, triple-point regions <NUM> (one shown) are formed. Triple-point regions <NUM> are approximately triangular locations defined by intersections of the depletion fronts extending into the silicon pillars from insulated trenches <NUM>. In this example, shield plate <NUM> is located in each of the pair of trenches <NUM> as well in the surrounding termination trench loop <NUM>. Depletion of drift region <NUM> (<FIG>) in MOSFET <NUM> grows under the influence of shield plates <NUM>. At termination area <NUM> there is an asymmetric growth of the depletion region at triple-point regions <NUM> because the "triple point" effectively acts as a wider region than width <NUM> between pairs of insulated trenches <NUM>. That is, triple-point regions <NUM> can become too wide to suppress the electric field at the top of the drift region at the location in triple-point regions <NUM> thereby causing the RESURF action to degrade which, in turn, can lead to a reduction in the breakdown voltage of MOSFET <NUM>. Accordingly, the breakdown voltage of the prior art trench MOSFET <NUM> is limited by triple-point regions <NUM> in termination area <NUM> instead of by the pairs of trenches <NUM> in active area <NUM>.

The electric field at the top of the drift region at the triple-point regions <NUM> may be suppressed if body region <NUM> at triple-point regions <NUM> is biased to a sufficiently positive voltage. However, continuous body region <NUM> in prior art trench MOSFET <NUM> is connected throughout both active and termination areas <NUM>, <NUM> through the PHV implant/diffusion region. Accordingly, embodiments disclosed herein implement a set of floating body segments, formed between device trenches, which break up the continuous body region of a trench MOSFET. Further, the floating body segments can self-bias to an appropriate positive voltage to obtain a positive bias on the triple-point regions. As such, the electric field in the triple-point region can be effectively suppressed and a breakdown voltage reduction at the triple-point region can be avoided.

Referring to <FIG> and <FIG>, <FIG> shows a plan view of a semiconductor device <NUM> in accordance with an embodiment and <FIG> shows a cross-sectional view of semiconductor device <NUM> taken along section line <NUM>-<NUM>' of <FIG>. Semiconductor device <NUM> may be, or may otherwise include, a trench field plate power MOSFET. As such, semiconductor device <NUM> may alternatively be referred to herein as MOSFET <NUM> or trench power MOSFET <NUM>. MOSFET <NUM> includes a semiconductor substrate <NUM> having opposed first and second major surfaces <NUM>, <NUM> (see <FIG>), an active area <NUM>, and a termination area <NUM> surrounding active area <NUM>. In <FIG>, active area <NUM> is generally surrounded by a dashed line box. In <FIG>, a dashed line delineates active area <NUM> from termination area <NUM>. For clarity of exposition, the following embodiments are based on an N-channel FET (NFET). However, the teachings are also applicable to embodiments based on a P-channel FET (PFET), where the doping polarities of the PFET are reversed from the NFET.

Semiconductor substrate <NUM> may include a number of epitaxial layers <NUM> supported by an original substrate <NUM>. In this example, semiconductor substrate <NUM> includes a single n-type epitaxial layer <NUM>, and original substrate <NUM> may be an n-type heavily or moderately doped substrate. Original substrate <NUM> may function as a drain region, and hence may alternatively be referred to herein as drain region <NUM>. Epitaxial layer <NUM> and drain region <NUM> are not necessarily drawn to scale in <FIG>. For example, in some cases drain region <NUM> may be thinned from an initial thickness after growth of epitaxial layer(s) <NUM> and other fabrication procedures. The structural, material, and other characteristics of semiconductor substrate <NUM> may vary from the example shown. For example, additional, fewer, or alternative layers may be included in semiconductor substrate <NUM>.

MOSFET <NUM> further includes parallel insulated trenches <NUM> extending from first major surface <NUM> toward second major surface <NUM> in semiconductor substrate <NUM>. Each of trenches <NUM> includes a conductive field plate <NUM> (e.g., a first polysilicon layer) and a gate electrode <NUM> (e.g., a second polysilicon layer) overlying the conductive field plate <NUM>, with gate electrode <NUM> being separated from conductive field plate <NUM> by a gate-field insulator (not visible, but corresponding to gate-field insulator plate <NUM> shown in <FIG>). Conductive field plate <NUM>, which may alternatively be referred to herein as shield plate <NUM>, extends longitudinally in each of trenches <NUM> in both of active and termination areas <NUM>, <NUM>. In some embodiments, distal ends <NUM>, <NUM> of gate electrode <NUM> in each of insulated trenches <NUM> define an outer perimeter <NUM> of active area <NUM>. As such, gate electrode <NUM> extends longitudinally in each of trenches <NUM> to outer perimeter <NUM> of active area <NUM> (defined by distal ends <NUM>, <NUM>) of gate electrode <NUM>, but is absent from trenches <NUM> in termination area <NUM>. Thus, trenches <NUM> in active area <NUM> are lined with an insulator <NUM> (e.g., shield oxide), with gate electrode <NUM> separated from conductive field plate <NUM> by the gate-field insulator. Conversely, trenches <NUM> in termination area <NUM> are lined with insulator <NUM>, but only include conductive field plate <NUM>, alternatively referred to as a shield plate <NUM> herein. Only a few trenches <NUM> are shown herein for simplicity. However, it should be understood that MOSFET <NUM> may have more or less than the quantity of trenches <NUM> shown.

An insulated termination trench loop <NUM> surrounds termination area <NUM>. Termination trench loop <NUM> is also lined with insulator <NUM> and conductive field plate <NUM> (e.g., the first polysilicon layer) also resides in insulated termination trench loop <NUM>. Again, although both conductive field plates <NUM> and gate electrodes <NUM> may be formed of the same polysilicon material, conductive field plates <NUM> are illustrated with a light stippled pattern and gate electrodes <NUM> are illustrated with a darker stippled pattern to distinguish one from the other.

A body region <NUM> extends laterally between pairs of insulated trenches <NUM> above epitaxial layer <NUM> of semiconductor substrate <NUM>. Body region <NUM> extends into the silicon mesas between trenches <NUM>. A drift region <NUM> is located under body region <NUM> between trenches <NUM> and a source implant region <NUM> (shown in the cross-sectional view of <FIG>) is formed overlying body region <NUM> between the pairs of trenches <NUM> in active area <NUM>. Thus, source region <NUM>, body region <NUM>, drift region <NUM>, and drain region <NUM> extend in that order from first major surface <NUM> toward second major surface <NUM>. Source contacts <NUM> may be formed on first major surface <NUM> of substrate <NUM> overlying source implant region <NUM> and a drain contact <NUM> may be formed on second major surface <NUM> of substrate <NUM> underlying drain region <NUM> of substrate <NUM>. For clarity, source implant region <NUM> and source contacts <NUM> are not shown in <FIG> so that body region <NUM> may be more readily visualized. A channel is formed in each section of body region <NUM> between insulated trenches <NUM> during operation for conduction of charge carriers between source contacts <NUM> and drain contact <NUM>.

As shown in <FIG>, body region <NUM> is generally present in active area <NUM> and in termination area <NUM>, extending to insulated trench loop <NUM>. However, spacer regions <NUM> extend laterally between pairs of insulated trenches <NUM> at termination area <NUM> produced by segments <NUM> between spacer regions <NUM> that are isolated from body region <NUM>. The phrase "at termination area <NUM>" is meant to encompass spacer regions <NUM> and/or segments <NUM> that are located outside of outer perimeter <NUM> of active area <NUM> and are thus in termination area <NUM>, to encompass spacer regions <NUM> and/or segments <NUM> that are located inside of outer perimeter <NUM> and are thus in active area <NUM> but near distal ends <NUM>, <NUM> and adjacent to gate electrodes <NUM> (but separated from gate electrodes <NUM> by insulator <NUM>), and to encompass spacer regions <NUM> and/or segments <NUM> that span across outer perimeter <NUM>.

Body region <NUM> is of a first conductivity type and epitaxial layer <NUM> is of a second conductivity type. In this n-channel example, body region <NUM> is a p-type doped region, and more particularly, a high voltage P-region (PHV), and as mentioned previously, epitaxial layer <NUM> is an n-type doped region. In accordance with an embodiment, spacer regions <NUM> are of the second conductivity type, e.g., n-type doped regions, and segments <NUM> are of the first conductivity type, e.g., p-type doped regions. In some embodiments, segments <NUM> are formed using the same body implant/diffusion process as the active body area (e.g., body region <NUM>) of MOSFET <NUM> in order to circumvent the need for additional masks/process steps to create the segments <NUM>. As such, body region <NUM> and segments <NUM> may extend the same depth <NUM> (<FIG>) into substrate <NUM>.

Segments <NUM> extend laterally between pairs of trenches <NUM> (e.g., perpendicular to a longitudinal dimension <NUM> of trenches <NUM>) and laterally between spacer regions <NUM> (e.g., parallel to longitudinal dimension <NUM> of trenches <NUM>). Further, these segments <NUM> are isolated from body region <NUM> and from one another. As particularly shown in <FIG>, p-type segments <NUM> are separated from body region <NUM> and from one another by n-type spacer regions <NUM> (e.g., the portion of epitaxial layer <NUM> between segments <NUM>). Accordingly, segments <NUM> are not connected to one another or to body region <NUM> via a direct contact or through a region of similar doping type. Since segments <NUM> have the same doping type as body region <NUM>, they are formed using the same body implant/diffusion process as the active body area, and they are not connected to one another or to body region <NUM>, segments <NUM> may be referred to herein as floating body segments <NUM>.

Each of insulated trenches <NUM> includes first and second end portions <NUM>, <NUM> and a middle portion <NUM> extending longitudinally between first and second end portions <NUM>, <NUM>. In this example configuration, spacer regions <NUM> extending between the pairs of insulated trenches <NUM> at first ends <NUM> include spacer regions <NUM><NUM>, <NUM><NUM>, and <NUM><NUM>. Spacer region <NUM><NUM> is adjacent to body region <NUM>. Floating body segments <NUM><NUM> reside between spacer regions <NUM><NUM> and <NUM><NUM>. Further, floating body segments <NUM><NUM> reside between spacer regions <NUM><NUM> and <NUM>. Still further, a floating body segment <NUM><NUM> resides between spacer region <NUM> and insulated trench loop <NUM>. Similarly, spacer regions <NUM> extending between the pairs of insulated trenches <NUM> at second ends <NUM> include spacer regions <NUM><NUM>, <NUM><NUM>, and <NUM><NUM>. Spacer region <NUM><NUM> is adjacent to body region <NUM>. Floating body segments <NUM><NUM> reside between spacer regions <NUM><NUM> and <NUM>. Further, floating body segments <NUM><NUM> reside between spacer regions <NUM><NUM> and <NUM><NUM>. Still further, a floating body segment <NUM><NUM> resides between spacer region <NUM><NUM> and insulated trench loop <NUM>. In the illustrated configurations, floating body segments <NUM><NUM> and <NUM><NUM> form a continuous structure with one another. However, in other embodiments, they may be discontinuous structures so that floating body segment <NUM><NUM> is isolated from floating body segment <NUM><NUM>.

Floating body segments <NUM> introduced between pairs of insulated trenches <NUM> effectively disconnect termination area <NUM> from active area <NUM>. Accordingly, when a bias is applied on drain region <NUM> with respect to body region <NUM>, epitaxial layer <NUM> starts getting depleted. As the depletion region expands, the depletion region may eventually touch, for example, floating body segment <NUM><NUM>. At that point, floating body segment <NUM><NUM> acquires the potential "touching" it. Subsequently, the depletion region starts to expand from floating body segment <NUM><NUM> and reaches floating body segment <NUM><NUM>. At that point, floating body segment <NUM><NUM> acquires the potential "touching" it. Finally, in this example, the depletion region starts to expand from floating body segment <NUM><NUM> and reaches floating body segment <NUM><NUM>, and at that point, floating body segment <NUM><NUM> acquires the potential "touching" it. Although floating body segments <NUM><NUM>, <NUM><NUM>, and <NUM><NUM> are mentioned herein with this explanation, the equivalent behavior occurs at <NUM><NUM>, <NUM><NUM>, and <NUM><NUM>. Accordingly, the depletion region expands when drain region <NUM> is biased appropriately which in turn causes floating body segments <NUM> to pick up positive potential.

There may be a slight enhancement of the electrical field at curvature regions <NUM> (see <FIG>) of floating body segments <NUM> due to the curvature of the PN junction (e.g., junction between n-type epitaxial layer <NUM> and p-type floating body segments <NUM>). However, in the configuration of multiple floating body segments <NUM>, curvature regions <NUM> may be effectively shielded by the adjacent floating body segments <NUM>. Accordingly, the enhancement of the electrical field at curvature regions can be controlled.

The example of <FIG> includes spacer regions <NUM><NUM> and <NUM><NUM> adjacent to gate electrodes <NUM> in trenches <NUM>, separated by insulator <NUM>. Further, at least portions of floating body segments <NUM><NUM> and <NUM><NUM> are adjacent to gate electrodes <NUM> in trenches <NUM>. Positioning floating body segments <NUM><NUM> and <NUM><NUM> adjacent to gate electrodes <NUM> may mitigate the effect of the electrical field enhancement at curvature regions <NUM>. That is, the electric field at the curvature regions <NUM> in this scenario may be lower as compared to the electric field at curvature regions when floating body segments <NUM> are in termination area <NUM> next to conductive field plate <NUM>. However, since gate electrodes <NUM> are physically closer to the silicon epitaxial layer <NUM>, relative to conductive field plates <NUM>, the depletion region may spread out quickly such that the depletion region may reach the next segment <NUM> at relatively low voltage on the drain.

Accordingly, some embodiments (such as the one shown) utilize a combination of segments <NUM> adjacent to gate electrodes <NUM> (separated by insulator <NUM>) in active area <NUM> and segments <NUM> adjacent to conductive field plates <NUM> (separated by insulator <NUM>) in termination area <NUM>. In such a configuration, the first segments <NUM> may be more susceptible to the electric field enhancement at curvature regions <NUM>, so that their placement adjacent to gate electrodes <NUM> may effectively suppress the electric field at curvature regions <NUM>. The later segments <NUM> adjacent to conductive field plates <NUM> may have a higher voltage drop for the same distance and may therefore be utilized to obtain the desired voltage.

In the configuration of <FIG>, simulations reveal that the breakdown voltage at termination area <NUM> experiences an increase followed by a decrease. However, there is a wide range of the Sxt (e.g., the distance between the end of one of trenches <NUM> and insulated trench loop <NUM>) where the breakdown voltage remains almost constant for a combination of Sxa (e.g., the distance between trenches <NUM>) and a given doping of epitaxial layer <NUM>. Accordingly, there may be insignificant impact ionization in the triple-point regions such that the impact ionization effectively moves into active area <NUM>. Therefore, the breakdown voltage is not limited by either Sxt (e.g., the distance between the end of one of trenches <NUM> and insulated trench loop <NUM>) or the triple-point region (e.g., triple-point regions <NUM> shown in <FIG>).

<FIG> shows a graphical view of simulation results for a segment voltage <NUM> as a function of drain voltage <NUM> for trench power MOSFET <NUM> (<FIG>). A solid line trace <NUM> represents a main source voltage. A dashed line trace <NUM> represents segment voltage <NUM> at floating body segment <NUM><NUM> as a function of drain voltage <NUM>. A dash-dot line trace <NUM> represents segment voltage <NUM> at floating body segment <NUM><NUM> as a function of drain voltage <NUM>. And, a dash-dot-dot trace <NUM> represents segment voltage <NUM> at floating body segment <NUM><NUM> as a function of drain voltage <NUM>. Although the following discussion is directed to floating body segments <NUM><NUM>, <NUM><NUM>, and <NUM>, it should be understood that this discussion applies equivalently to floating body segments <NUM><NUM>, <NUM><NUM>, and <NUM><NUM>.

As a drain voltage <NUM> increases, floating body segments <NUM> pick up potential. In this example, the triple-point body region (e.g., floating body segment <NUM><NUM>) acquires a voltage potential of approximately thirty volts. The thirty volt potential may be sufficient to suppress the electric field in the triple-point region (e.g., triple-point regions <NUM> shown in <FIG>) and move the impact ionization to active area <NUM>. <FIG> is provided to show that a reasonable positive potential (e.g., thirty volts) may be acquired by the termination body (e.g., termination area <NUM>). The thirty voltage potential may be sufficient to suppress the electric field in triple-point regions <NUM> in the case under consideration. However, in general, the minimum voltage needed to achieve such an effect can vary between different designs, and is dependent upon the values of Sxa, Sxt, doping, trench oxide thickness, and so forth.

In the prior art design of <FIG>, the breakdown voltage falls off rapidly beyond a critical value of Sxt. In comparison, the floating body segment design of <FIG> extends the rising phase and converts it into a plateau. Thus, the optimum breakdown voltage values for the floating body segment design are higher than the breakdown voltage values of prior art design so that the breakdown voltage values are limited by the device core (e.g., active area <NUM>) even for high pillar charge (e.g., high doping, wider Sx) scenarios. In other words, utilization of a floating body segment at the termination area may suppress the electric field in the triple-point regions to avoid the breakdown voltage roll off at wider values of Sxt. The breakdown voltage can, therefore, be made higher and may be limited by the active area even for high epitaxial layer doping and wide values of Sx (Sxa and Sxt), thus achieving a better breakdown voltage - lower on resistance (BV-RDS(on)) tradeoff. Further, the floating body segment design can be extended by employing a larger number of floating body segments along with larger spacing to attain a higher potential at the triple-point regions, if needed. Thus, the floating body segment design may allow a wide design and process margin (e.g., doping and/or dimensions).

<FIG> shows a cross-sectional view of a trench power MOSFET <NUM> in accordance with another embodiment. The location of cross-sectional view of MOSFET <NUM> corresponds to the location of cross-sectional view <NUM>-<NUM>' shown in <FIG>. Further, MOSFET <NUM> includes many of the elements of MOSFET <NUM> (<FIG>), such as a body area, termination area, epitaxial layer, drift region, drain region, parallel insulated trenches, conductive field plate, gate electrodes, and so forth. As such, a description of these elements will not be repeated herein for brevity.

In this example, MOSFET <NUM> includes spacer regions <NUM><NUM>, <NUM><NUM>, and <NUM><NUM> of a second conductivity type (e.g., n-type doping) extending laterally between pairs of the insulated trenches produced by floating body segments <NUM><NUM>, <NUM><NUM>, and <NUM><NUM> of a first conductivity type (e.g., p-type doping). Spacer region <NUM><NUM> is adjacent to a body region <NUM> of MOSFET <NUM>. Floating body segment <NUM><NUM> resides between spacer regions <NUM><NUM> and <NUM><NUM>. Further, floating body segment <NUM><NUM> resides between spacer regions <NUM><NUM> and <NUM>. Still further, floating body segment <NUM><NUM> resides between spacer region <NUM><NUM> and an insulated termination trench loop (not shown).

A higher or lower voltage in the triple-point region can be acquired by modifying the configuration of the floating body segments. In this example illustration, floating body segment <NUM><NUM> exhibits a first segment width <NUM> parallel to the longitudinal dimension of the insulated trenches (see <FIG>) and floating body segment <NUM><NUM> exhibits a second segment width <NUM> parallel to the longitudinal dimension of the insulated trenches that is different from first segment width <NUM>. Further, spacer regions <NUM><NUM>, <NUM><NUM> exhibits a first spacer width <NUM> parallel to the longitudinal dimension of the insulated trenches (again, see <FIG>) and spacer region <NUM><NUM> exhibits a second spacer width <NUM> parallel to the longitudinal dimension of the insulated trenches that differs from first spacer width <NUM>. In this generalized example, second spacer width <NUM> is greater than first spacer width <NUM>. In general, if the floating body segments are farther apart, it may allow them to have a higher difference in potential, leading to the final segment (e.g., floating body segment <NUM><NUM>) reaching an even higher voltage potential.

<FIG> is provided to demonstrate that the widths of the spacer regions and/or the widths of the floating body segments may be readily modified to attain a desired voltage at the triple-point regions since no additional mask is required to produce the desired doping patterns. Further, although three body segments are provided in the illustrated configuration, the design can be modified to include less than or more than the three body segments.

<FIG> shows a flowchart representation of a method <NUM> for fabricating a semiconductor device in accordance with another embodiment. Fabrication method <NUM> may be performed to produce a semiconductor device having floating body segments that break up or otherwise isolate the active body area of the semiconductor device from the termination area of the semiconductor device, and are able to self-bias to an appropriate positive voltage. Accordingly, an electric field at a triple point region of the termination area can be effectively suppressed so that breakdown voltage roll-off at the termination area can be avoided.

At a block <NUM>, a drain region (e.g., drain region <NUM>, <FIG>) is formed with a doped semiconductor substrate. At a block <NUM>, an epitaxial layer (e.g., epitaxial layer <NUM>, <FIG>) is grown on the drain region such that an exterior surface of the epitaxial layer defines a first major surface (e.g., first major surface <NUM>, <FIG>) of the semiconductor device and a second major surface (e.g., second major surface <NUM>, <FIG>) opposes the first major surface.

At a block <NUM>, insulated trenches (e.g., insulated trenches <NUM> and insulated trench loop <NUM>, <FIG>) are formed in the epitaxial layer. The insulated trenches are disposed in parallel with one another and extend from the first major surface toward the second major surface. At a block <NUM>, a first polysilicon layer is formed in each of trenches <NUM>, <NUM> to form a shield (e.g., conductive field plate <NUM>, <FIG>) separated by the epitaxial layer by an insulator (e.g., insulator <NUM>). At a block <NUM>, a second polysilicon layer is formed in each of trenches <NUM> over the first polysilicon layer to form a gate electrode (e.g., gate electrodes <NUM>, <FIG>) separated from the shield by a gate-field plate insulator (e.g., gate-field plate insulator <NUM>, <FIG>). The semiconductor device has an active area (e.g., active area <NUM>, <FIG>) and a termination area (e.g., termination area <NUM>, <FIG>) surrounding the active area. The gate electrode is absent in the termination area and the conductive field plate extends longitudinally in both of the active and termination areas.

At a block <NUM>, a body region (e.g., body region <NUM>, <FIG>) is formed and segments (e.g., floating body segments <NUM>, <FIG>) are produced in the epitaxial layer between at least two of the insulated trenches at the termination area and between at least two spacer regions. The body region are formed and the segments are produced concurrently utilizing the same implantation process. The body region and segments are of a first conductivity type (e.g., p-type dopant) and the epitaxial layer and the spacer regions are of a second conductivity type (e.g., n-type dopant). A configuration may include any suitable number of segments isolated from the other segments and from the body region, and one or more segments may be formed between the spacer regions and the insulated termination trench (e.g., insulated trench loop <NUM>, <FIG>). Further, the spacer regions and/or segments may be located outside of the outer perimeter of the active area and are thus in the termination area, may be located inside of the outer perimeter <NUM> and are thus in the active area <NUM> adjacent to gate electrodes <NUM>, and/or may span across the outer perimeter of the active area. Still further, the spacer regions and/or segments may be any suitable width and may be different widths relative to one another.

At a block <NUM>, a source contact (e.g., source contact <NUM>, <FIG>) may be formed in a silicon mesa above the body region and between the insulated trenches. Of course, other continuing operations may include forming a drain contact (e.g., drain contact <NUM>, <FIG>), forming buildup layers above the first major surface, packaging, testing, and the like. Thereafter, method fabrication method <NUM> may end.

It should be understood that certain ones of the process blocks depicted in <FIG> may be performed in parallel with each other or with performing other processes. In addition, the particular ordering of the process blocks depicted in <FIG> may be modified while achieving substantially the same result. Accordingly, such modifications are intended to be included within the scope of the inventive subject matter.

<FIG> shows another plan view of trench power MOSFET <NUM> to demonstrate issues that may arise at corner regions <NUM> of trench power MOSFET <NUM>. The material of termination area <NUM> is the same as that for body region <NUM> (e.g., epitaxial layer <NUM>, see <FIG>). In the configuration of MOSFET <NUM>, corner regions <NUM> have a relatively small radius of curvature, R. This relatively small radius of curvature, R, may cause the breakdown voltage to be lower at termination area <NUM> due to electric field crowding. An undesirably low breakdown voltage may occur in either a standard termination design (e.g., without floating body segments <NUM>) or in a floating body segment design.

An undesirably low breakdown voltage at corner regions <NUM> may be alleviated by increasing a width of Sxc (e.g., the distance between the edge of the closes one of trenches <NUM> and insulated trench loop <NUM> at corner regions <NUM>) and/or by increasing the radius of curvature, R, at corner regions <NUM>. The presence of floating body segments <NUM> can enable the feasibility of fabricating a wider Sxc in order to effectively increase the breakdown voltage at corner regions <NUM>. However, if the wider Sxc does not sufficiently increase the breakdown voltage at corner regions <NUM>, the radius of curvature, R, at corner regions <NUM> may need to be increased. <FIG> demonstrate example embodiments for effectively increasing the radius of curvature, R, while maintaining the integrity of other regions. It should be understood, however, that other design configurations may be envisioned for increasing the radius of curvature, R, at corner regions <NUM>.

<FIG> shows a partial plan view of a trench power MOSFET <NUM> at a corner region <NUM> in accordance with another embodiment. MOSFET <NUM> includes parallel insulated trenches <NUM>, each of which includes a conductive field plate <NUM> (also referred to as a shield plate <NUM>) and a gate electrode <NUM> overlying shield plate <NUM>, with gate electrode <NUM> being separated from shield plate <NUM> by a gate-field insulator (not visible). An active area <NUM> of MOSFET <NUM> is defined by the outermost insulated trenches <NUM> and corresponding ends of trenches <NUM> and a termination area <NUM> surrounds active area <NUM>. MOSFET <NUM> further includes insulated trenches <NUM> arranged parallel to trenches <NUM> and located outside of active area <NUM>. Each of insulated trenches <NUM> includes shield plate <NUM>. However, gate electrodes <NUM> are not included in insulated trenches <NUM>. In a rectangular configuration, MOSFET <NUM> includes four corner regions <NUM> and insulated trenches <NUM> positioned on opposing sides of active area <NUM>.

Insulated trenches <NUM> are offset or arranged in a stepped fashion at corner region <NUM> to enable a larger radius of curvature, R, to be achieved at corner region <NUM>, relative to the radius of curvature of MOSFET <NUM> shown in <FIG>. In this configuration, the body regions between the final few trenches <NUM> are connected to termination area <NUM>, represented by a dash-dot-dash curve. Thus, the body regions between the active trenches <NUM> and a termination trench loop <NUM>, between trenches <NUM>, and between the endmost trench <NUM> and termination trench loop <NUM> will acquire the positive potential, thereby allowing them to have a wider spacing Sx (denoted by bidirectional arrows) between the trenches and a higher local breakdown voltage.

MOSFET <NUM> further includes spacer regions <NUM> and floating body segments <NUM>, as discussed in detail in connection with spacer regions <NUM> and floating body segments <NUM> of MOSFET <NUM> (<FIG>). The combination of floating body segments <NUM> as well as the effective increase in the radius of curvature, R, by the implementation of trenches <NUM> in termination area <NUM> may enable a higher local breakdown voltage at corner regions <NUM>. However, increasing the radius of curvature, R, by the implementation of trenches <NUM> in the termination area of a standard termination layout (i.e., a layout without floating body segments <NUM>) may also yield a sufficiently high local breakdown voltage at the corner regions.

<FIG> shows a partial plan view of a trench power MOSFET <NUM> at a corner region <NUM> in accordance with another embodiment. MOSFET <NUM> includes parallel insulated trenches <NUM>, each of which includes a conductive field plate <NUM> (also referred to as a shield plate <NUM>) and a gate electrode <NUM> overlying shield plate <NUM>, with gate electrode <NUM> being separated from shield plate <NUM> by a gate-field insulator (not visible). An active area <NUM> of MOSFET <NUM> is defined by the outermost insulated trenches <NUM> and corresponding ends of trenches <NUM> and a termination area <NUM> surrounds active area <NUM>. A termination trench loop <NUM> surrounds termination area <NUM>. In a rectangular configuration, MOSFET <NUM> includes four corner regions <NUM>.

Insulated trenches <NUM> are offset or arranged in a stepped fashion at corner region <NUM> to enable a larger radius of curvature, R, to be achieved at corner region <NUM>, relative to the radius of curvature of MOSFET <NUM> shown in <FIG>. MOSFET <NUM> further includes spacer regions <NUM> and floating body segments <NUM>, as discussed in detail in connection with spacer regions <NUM> and floating body segments <NUM> of MOSFET <NUM> (<FIG>). Floating body segments <NUM> are present between all of insulated trenches <NUM> including those that are offset or arranged in a stepped fashion. Again, due to a positive potential at corner regions <NUM> resulting from floating body segments <NUM>, a wider spacing Sx (denoted by bidirectional arrows) may be achieved between trenches <NUM> and termination trench loop <NUM> and hence yield a higher local breakdown voltage.

<FIG> shows a plan view of a trench power MOSFET <NUM> having four corner regions <NUM> in accordance with yet another embodiment. MOSFET <NUM> includes parallel insulated trenches <NUM>, each of which includes a conductive field plate <NUM> (also referred to as a shield plate <NUM>) and a gate electrode <NUM> overlying shield plate <NUM>, with gate electrode <NUM> being separated from shield plate <NUM> by a gate-field insulator (not visible). An active area <NUM> of MOSFET <NUM> is defined by the outermost insulated trenches <NUM> and corresponding ends of trenches <NUM> and a termination area <NUM> surrounds active area <NUM>. A primary termination trench loop <NUM> surrounds termination area <NUM>.

In this example embodiment, secondary termination loops <NUM> are arranged on opposing sides of the outermost insulated trenches <NUM> to enable a larger radius of curvature, R, at each of corner regions <NUM>. Thus, in this example, there are no "triple-point" regions wherein the trenches curve. The Sxc at corner regions <NUM> can be larger or equal to Sxt, depending on a particular design requirement. Although size of active area <NUM> may be sacrificed by the additional secondary termination loops <NUM>, the larger radius of curvature may yield a higher local breakdown voltage.

MOSFET <NUM> further includes spacer regions <NUM> and floating body segments <NUM> between insulated trenches <NUM>, as discussed in detail in connection with spacer regions <NUM> and floating body segments <NUM> of MOSFET <NUM> (<FIG>). The combination of floating body segments <NUM> as well as the effective increase in the radius of curvature, R, by the implementation of secondary termination loops <NUM> in termination area <NUM> may enable a higher local breakdown voltage at corner regions <NUM>. However, increasing the radius of curvature, R, by the implementation of secondary termination loops <NUM> in the termination area of a standard termination layout (i.e., a layout without floating body segments <NUM>) may also yield a sufficiently high local breakdown voltage at the corner regions.

Embodiments described herein entail a semiconductor device with improved breakdown voltage characteristics and methodology for fabricating such a semiconductor device. In particular, embodiments entail a trench field plate power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a set of floating body segments formed between device trenches of the MOSFET. The floating body segments break up or otherwise isolate an active body area of the semiconductor device from a termination area of the semiconductor device. Further, the floating body segments are able to self-bias to an appropriate positive voltage. Accordingly, an electric field at a triple point region of the termination area can be effectively suppressed so that breakdown voltage roll-off at the termination area can be avoided. In some embodiments, the floating body segments may be formed using the same body implant/diffusion process as the active body area of the device. Such an approach can circumvent the need for additional masks/process steps to create the floating body segments and thereby achieve enhancements in fabrication efficiency and cost savings.

Claim 1:
A semiconductor device comprising:
a substrate having opposed first (<NUM>) and second (<NUM>) major surfaces, an active area (<NUM>), and a termination area (<NUM>) surrounding the active area;
insulated trenches (<NUM>) extending from the first major surface toward the second major surface, and having a longitudinal direction, each of the insulated trenches including a conductive field plate (<NUM>) and a gate electrode (<NUM>) overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator (<NUM>), wherein the conductive field plate extends longitudinally in both of the active and termination areas and the gate electrode extends longitudinally in the active area and is absent in the termination area; and
a body region (<NUM>) of a first conductivity type extending laterally between pairs of the insulated trenches;
characterised by
first (112i) and second (<NUM><NUM>) spacer regions of a second conductivity type extending laterally between the pairs of the insulated trenches and perpendicularly to the longitudinal direction thereof, at the termination area defined by segments (<NUM>) of the first conductivity type, between the first and second spacer regions and that are isolated from the body region.