Patent Description:
Depending on the peak currents during inrush and short circuit conditions, either a single MOSFET or several MOSFETs in parallel are typically used as a disconnect switch. If standard MOSFETs are used as disconnect switches, the inrush current is not limited during system power on. Furthermore, when standard MOSFETs are connected in parallel, unequal current sharing occurs during inrush current transients. This results in coupling more standard MOSFETs in parallel to compensate for unequal current sharing.

Another method is to carefully select standard MOSFETs with matching Vth (threshold voltage) values which is expensive. Also, standard MOSFETs are typically selected as disconnect switches with the assumption that a single MOSFET will take over the entire inrush current as equal current sharing among MOSFETs cannot be guaranteed which represents an additional cost. For these reasons and others, Linear FETs have been proposed for limiting inrush current and equal current sharing during inrush transients when paralleled. Linear FET technology combines the low RDSon (on-state resistance) of a trench MOSFET with the wide safe operating area (SOA) of a planar MOSFET. Linear FETs have faster turn off compared to standard MOSFETs. However, faster turn off can lead to avalanching of the device which can result in failure and adversely affect system reliability.

<CIT> discloses a hybrid switch apparatus that includes a standard semiconductor switch and a fast semiconductor switch electrically arranged in parallel to form a joint output current path for carrying a load current. The standard switch may be a silicon (Si) MOSFET while the fast switch may be a GaN high electron mobility transistor (HEMT). <CIT> further discloses a means for producing first and second gate drive signals that includes a pulse former. The first gate drive signal is applied the standard switch for selectively turning the standard switch on and off. The pulse former outputs the second gate drive signal for driving the fast switch, where the pulse former generates the second gate drive signal as a switch-on pulse starting synchronously with each transition of the first gate drive signal and which generates the second gate drive signal in an OFF state in between pulses to avoid incurring a conduction loss in the fast switch.

<CIT> discloses an apparatus with a first plurality of power switch devices. Each of the first plurality of power switch devices includes a delay line having a programmable time delay, and a power switch coupled between a supply rail and a circuit block, wherein the power switch has a control input coupled to the delay line. The apparatus also includes a switch manager configured to program the time delays of the delay lines in the first plurality of power switch devices based on a number of active circuit blocks in a system.

<CIT> discloses a switched-mode power supply device including an AC power supply, a transformer having a primary winding and a secondary winding, a switching element electrically connected to the primary winding, a secondary-side rectifying and smoothing circuit that generates an output voltage by rectifying and smoothing the pulse voltage, a load ratio detection circuit that detects if a load ratio is not greater than a load ratio threshold value during steady load, and outputs a drive switch signal based on the detection, and a drive circuit that, on the basis of the drive switch signal, causes the switching element to perform switching operation in one of a normal drive in which a speed of charging agate voltage is faster and a soft drive in which the speed of charging the gate voltage is slower.

<CIT> discloses a power control system for a power domain on an integrated circuit. The power control system includes a power supply; a plurality of power switches, each having a first terminal connected to said power supply, a second terminal connected to a power supply input of the power domain and an input for control of conduction between said first terminal and said second terminal; and a power supply controller having a plurality of outputs. Each output is connected to the input of a corresponding power switch. The power supply controller is operable to power up the power domain by supplying signals on the outputs to inputs of corresponding power switches to sequentially cause the power switches to conduct until all power switches are turned conduct, and power up the power domain by supplying signals on the outputs to inputs of corresponding power switches to conduct via at least two power switches simultaneously.

There is a need for an improved disconnect switch approach for power electronic systems.

One embodiment relates to a gate driver circuit according to claim <NUM>. Further embodiments relate to a power conversion system according to claim <NUM> and a method according to claim <NUM>.

The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.

The embodiments described herein provide a gate driver circuit with two or more outputs and having configurable turn on and/or configurable turn off delay introduced between the outputs such that a first power disconnect switch turns on first to limit the inrush current during power on events and a second power disconnect switch with a delayed turn on time relative to the first power disconnect switch to reduce system power losses during normal operation. Similar delayed sequencing may occur during turn off events in that the first power disconnect switch may turn off first followed by the second power disconnect switch to provide a controlled turn off at high currents which avoids avalanching of the disconnect switch.

The delay may be introduced in the gate driver by analog or digital implementation and may be programmable or defined by measurement, calibration, etc. or may be fixed. For example, in the case of a measurement-based implementation, inrush current sensing may be implemented via a series resistor or RDSon sensing using a comparator. After a certain threshold is reached, the second power disconnect switch may be turned on. The turn-on delay implemented by the gate driver circuit instead may be a constant value such that no additional sense circuitry is needed. During turn off, the first power disconnect switch is turned off immediately in response to system or controller protection or a normal shutdown sequence. The second power disconnect switch may be turned off in a controlled manner after a delay from when the first power disconnect switch is turned off, to avoid avalanching. In some cases, just the turn on delay may be implemented. In other cases, just the turn off delay may be implemented. In yet other cases, both the turn on delay and the turn off delay may be implemented.

Described next with reference to the figures are embodiments of the improved disconnect switch approach, and corresponding power conversion circuits, electronic systems, and methods of power disconnect switch control.

<FIG> illustrates an embodiment of an electronic system <NUM> that includes a load <NUM>, a power source <NUM>, and power conversion circuit <NUM> coupled between the load <NUM> and the power source <NUM>. Whether power inversion or conversion occurs between the power source <NUM> and the load <NUM> depends on the type of electronic system <NUM>. In one embodiment, the power source <NUM> is a battery 'VBAT', the load <NUM> is a multi-phase motor 'M', and the power conversion circuit <NUM> inverts a DC voltage from the battery VBAT to an ac voltage applied to the multi-phase motor M. For example, the motor may be a <NUM>-phase motor and the power conversion circuit <NUM> may include three half bridges each including a high-side power transistor HSn coupled in series to a low-side power transistor LSn between a power input node PIN of an inverter/converter <NUM> and ground to form a respective phase input φn to the <NUM>-phase motor M. In this case, the inverter/converter <NUM> functions as an inverter. However, if the power source <NUM> is instead an ac source, the inverter/converter <NUM> functions as a converter. The inverter/converter <NUM> may have other configurations such as full bridge, synchronous rectifier, etc., depending on the type of application.

In general, the power conversion circuit <NUM> also includes a bulk or dc bus capacitor CDC electrically coupled to the power input node PIN of the inverter/converter <NUM>. The power conversion circuit <NUM> further includes at least one first transistor T1a electrically coupled between the power source <NUM> and the power input node PIN of the inverter/converter <NUM>, and at least one second transistor T2a in parallel with the at least one first transistor T1a and electrically coupled between the power source <NUM> and the power input node PIN of the inverter/converter <NUM>.

The power conversion circuit <NUM> further includes a controller <NUM> such as a microcontroller, CPU (central processing unit), etc. that operates the at least one first transistor T1a and the at least one second transistor T2a as respective first and second disconnect switches <NUM>, <NUM> when disconnecting the power source <NUM> from the load <NUM>, e.g., as part of hot swap, electronic fuse and/or battery protection applications.

The at least one first transistor T1a that forms the first disconnect switch <NUM> is a different type of transistor or a transistor with a different type of operating characteristic (e.g., gate charge) compared to the at least one second transistor T2a that forms the second disconnect switch <NUM>. For example, the at least one first transistor T1a that forms the first disconnect switch <NUM> is better suited for limiting the inrush current flowing into the power input node PIN of the inverter/converter <NUM> during power on of the load <NUM> whereas the at least one second transistor T2a that forms the second disconnect switch <NUM> provides lower RDSon during normal operation of the load <NUM>.

In one embodiment, the first power disconnect switch <NUM> is realized by a plurality of first transistors T1a. T1n coupled in parallel and controlled by the same first gate control signal 'A'. The second power disconnect switch <NUM> similarly may be realized by a plurality of second transistors T2a. T2m coupled in parallel and controlled by the same second gate control signal 'B'. The first power disconnect switch <NUM> and the second power disconnect switch <NUM> may have an equal or different number of transistors. That is, m = n or m ≠ n where m ≥ <NUM> and n ≥ <NUM>. Depending on the type of application in which the electronic system <NUM> is deployed, one or both of the power disconnect switches <NUM>, <NUM> may only include a single transistor.

A gate driver circuit <NUM> of the power conversion circuit <NUM> generates the first gate control signal A for each first transistor T1a. T1n that forms the first power disconnect switch <NUM> and generates the second gate control signal B for each second transistor T2a. T2m that forms the second power disconnect switch <NUM>. When powering up the load <NUM>, the gate driver circuit <NUM> generates the gate control signals A, B such that the second gate control signal B has a delayed turn on time compared to the first gate control signal A. Accordingly, each first transistor T1a. T1n of the first power disconnect switch <NUM> turns on before each second transistor T2a. T2m of the second power disconnect switch <NUM>.

<FIG> illustrates various waveforms associated with powering-up the load <NUM>. <FIG> shows the first gate control signal A in volts (V), the second gate control signal B in volts (V), the gate-to-source voltage VGS1 of the first power disconnect switch <NUM> in volts (V), the gate-to-source voltage VGS2 of the second power disconnect switch <NUM> in volts (V), the drain-to-source voltage VDS1 of the first power disconnect switch <NUM> in volts (V), and the current I_PIN flowing into the power input node PIN of the inverter/converter <NUM> in amperes (A).

As shown in <FIG>, the gate driver circuit <NUM> generates the gate control signals A, B such that the second gate control signal B has a delayed turn on time compared to the first gate control signal A when powering up the load <NUM>. Accordingly, the gate-to-source voltage VGS1 of the first power disconnect switch <NUM> rises before the gate-to-source voltage VGS2 of the second power disconnect switch <NUM>, causing the first power disconnect switch <NUM> to turn on and begin conducting current before the second power disconnect switch <NUM>. When the first power disconnect switch <NUM> turns on, current I_PIN begins flowing into the power input node PIN of the inverter/converter <NUM> as the bulk or dc bus capacitor CDC charges.

The delay imparted by the gate driver circuit <NUM> to the second gate control signal B may be fixed, programmable, calculated, calibrated, etc. such that the inrush current I_inrush flowing into the power input node PIN of the inverter/converter <NUM> reaches a peak I_pk and then begins to drop to a lower level (On_delay_I_level) before the second power disconnect switch <NUM> is turned on. In one embodiment, each first transistor T1a. T1n of the first power disconnect switch <NUM> is a Linear FET and each second transistor T2a. T2m of the second power disconnect switch <NUM> is a transistor type other than a Linear FET like standard MOSFETs, e.g., a planar MOSFET or a trench MOSFET.

Trench MOSFETs have a significantly smaller RDSon compared to planar MOSFETs for the same chip area and significantly reduce overall conduction losses. Trench MOSFETs also have substantially steeper transfer characteristics which results in a narrowing of the safe operating area (SOA) which exhibits clear limitations during the linear mode operation of the device, which can be in the millisecond range. For example, hot swap applications require a disconnect switch to slowly turn on in the few hundreds of microseconds to few tens of millisecond range with currents as high as the MOSFET can withstand, i.e., wide SOA capable. Hot swap applications also require low RDSon for the normally-on operating condition. Linear FETs such as the OptiMOS™ Linear FET manufactured and sold by Infineon Technologies and which combine the low RDSon of a trench MOSFET with the broad safe operating area SOA of a planar MOSFET.

<FIG> plots gate charge characteristics for a typical trench MOSFET whereas <FIG> plots gate charge characteristics for a Linear FET. The x-axis in both graphs represents gate charge (Qgate) in nano coulombs (nC) and the y-axis in both graphs represents gate-to-source voltage (VGS) in volts (V). The gate charge characteristics are plotted for three different operating voltages: 20V, 50V and 80V. As <FIG> demonstrate, the Linear FET has a higher plateau voltage (~7V versus ~<NUM>. 5V in this example) and a wider gate to drain charge capability. That is, the Miller plateau can be reached for the Linear FET with a much lower charge (approximately <NUM> nC vs. approximately <NUM> nC) and the Linear FET enters linear mode more effortlessly. The Linear FET then stays in the plateau region longer due to higher gate to drain charge needed to completely charge the MOSFET (more than <NUM> nC vs. approximately <NUM> nC).

Implementing the first power disconnect switch <NUM> as one or more Linear FETs provides for a controlled turn-on, thereby limiting the inrush current I_inrush flowing into the power input node PIN of the inverter/converter <NUM>. This is, however, just one example. Other transistor types may be used for the first power disconnect switch <NUM> to provide better inrush current control compared to the second power disconnect switch <NUM>.

The second power disconnect switch <NUM> may be optimized for low RDSon during normal operation. For example, a plurality of trench MOSFETs may be coupled in parallel to reduce RDSon during normal operation. Any threshold variation between the paralleled trench MOSFETs should have no effect on inrush current limiting capability during power on, since the gate driver circuit <NUM> delays the second gate control signal B applied to the second power disconnect switch <NUM> relative to the first gate control signal A applied to the first power disconnect switch <NUM>. Accordingly, the first power disconnect switch <NUM> is switched on before the second power disconnect switch <NUM> and therefore handles/limits the inrush current I_inrush without contribution from the second power disconnect switch <NUM>. The delay in the activation of the second gate control signal B is implemented such that the second power disconnect switch <NUM> turns on via the second gate control signal B after the peak inrush current I_pk subsides, e.g., as shown in <FIG>.

In addition to or separately from the delayed turn on embodiments described herein, the gate driver circuit <NUM> may generate the gate control signals A, B such that the second gate control signal B has a delayed turn off time compared to the first gate control signal A when powering down the load <NUM>. According to this aspect, each first transistor T1a. T1n of the first power disconnect switch <NUM> turns off before each second transistor T2a. T2m of the second power disconnect switch <NUM> when powering down the load <NUM>. Such turn off sequencing ensures that the second power disconnect switch <NUM> may have a controlled turn off when powering down the load <NUM>.

In the case of implementing the first power disconnect switch <NUM> as one or more Linear FETs and implementing the second power disconnect switch <NUM> as one or more standard MOSFETs like trench MOSFETs, each Linear FET is turned off first when powering down the load <NUM> so as to avoid fast turn off avalanching and/or excessive ringing across the drain-to-source voltage of the Linear FET(s). Turning off the second power disconnect switch <NUM> after the first power disconnect switch <NUM> has been turned off allows for a safe and controlled turn-off process. Implementing both the turn on delay and the turn off delay approaches in conjunction allows for inrush current control during power on of the load <NUM> and for safe/controlled powering down of the load <NUM>.

<FIG> illustrates various waveforms associated with powering-down the load <NUM>. <FIG> shows the first gate control signal A in volts (V), the second gate control signal B in volts (V), the gate-to-source voltage VGS1 of the first power disconnect switch <NUM> in volts (V), the gate-to-source voltage VGS2 of the second power disconnect switch <NUM> in volts (V), the drain-to-source voltage VDS1 of the first power disconnect switch <NUM> in volts (V), and the current I_PIN flowing into the power input node PIN of the inverter/converter <NUM> in amperes (A).

As shown in <FIG>, the gate driver circuit <NUM> generates the gate control signals A, B such that the second gate control signal B has a delayed turn off time compared to the first gate control signal A when powering down the load <NUM>. Initiating a controlled turn off of the second power disconnect switch <NUM> after first turning off the first power disconnect switch <NUM> provides for improved control of the drain-to-source voltage VDS1 of the first power disconnect switch <NUM> which in turn avoids VDS ringing at the first power disconnect switch <NUM> and avoids avalanche. In one embodiment, the delayed turn off time is such that the first power disconnect switch <NUM> is completely turned off before the second power disconnect switch <NUM> begins to turn off.

As explained above, the delay between the gate control signals A, B may be fixed, programmable, calculated, calibrated, etc. Described next are various embodiments of determining the delay between the gate control signals A, B.

Referring to <FIG>, the gate driver circuit <NUM> may implement the delayed turn on time for the second gate control signal B based on a programmed delay value <NUM> which may be fixed (i.e., programmed once) or re-programmable. In one embodiment, the gate driver circuit <NUM> includes a first driver <NUM> for driving the gate of each first transistor T1a. T1n that forms the first power disconnect switch <NUM> and a second driver <NUM> for driving the gate of each second transistor T2a. T2m that forms the second power disconnect switch <NUM>.

Logic <NUM> included in the gate driver circuit <NUM> applies a switching control signal PWM received from the controller <NUM> as input to the first driver <NUM> which in turn generates the first gate control signal A without adding any intentional delay. The gate driver circuit logic <NUM> applies the delayed turn on time indicated by the corresponding programmed delay value <NUM> to the switching control signal PWM as input to the second driver <NUM> which in turn generates the second gate control signal B with the intentionally added delay. Accordingly, the first power disconnect switch <NUM> turns on before the second power disconnect switch <NUM> when powering up the load <NUM> such that the first power disconnect switch <NUM> limits the inrush current I_inrush while the second power disconnect switch <NUM> remains switched off. The programmed delay value <NUM> may be programmed or determined such that the inrush current I_inrush reaches a peak I_pk and begins to drop to a lower level On_delay_I_level before the second power disconnect switch <NUM> is turned on, e.g., as shown in <FIG>.

Regarding delayed turn-off of the second power disconnect switch <NUM> when powering down the load <NUM>, the gate driver circuit <NUM> may implement the delayed turn off time for the second gate control signal B based on a corresponding programmed delay value <NUM> which may be fixed or re-programmable. For example, the gate driver circuit logic <NUM> applies the switching control signal PWM received from the controller <NUM> as input to the first driver <NUM> without adding any intentional delay. The gate driver circuit logic <NUM> applies the delayed turn on time indicated by the corresponding programmed delay value <NUM> to the switching control signal PWM for input to the second driver <NUM>. Accordingly, the first power disconnect switch <NUM> turns off before the second power disconnect switch <NUM> when powering down the load <NUM> so as to avoid fast turn off avalanching and/or excessive VDS ringing at the first power disconnect switch <NUM>.

The programmed turn-off delay value <NUM> may be programmed or determined to allow for a controlled turn off of the second power disconnect switch <NUM>. For example, gate resistance may be added to the second power disconnect switch <NUM> and/or the second driver <NUM> may include a controlled-current gate driver circuit for turning off the second power disconnect switch <NUM> in a controlled manner. Controlled turn-off of the second power disconnect switch <NUM> includes slowly decreasing the gate-to-source voltage (VGS2) of the second power disconnect switch <NUM> in a controlled manner as shown in <FIG>. When the gate-to-source voltage VGS2 of the second power disconnect switch <NUM> is low enough, the current I_PIN is switched off as shown in <FIG>. For example, the slew rate of the gate-to-source voltage (VGS2) of each second transistor T2a. T2m that forms the second power disconnect switch <NUM> may be in a range of <NUM> to <NUM> to turn off the second power disconnect switch <NUM> in a controlled manner.

Regarding delayed turn-on of the second power disconnect switch <NUM> when powering up the load <NUM>, <FIG> illustrates an embodiment of implementing the delayed turn-on time <NUM> for the second power disconnect switch <NUM> that includes a sensor <NUM> for sensing the drain-to-source voltage (VDS1) of the first power disconnect switch <NUM> or a current flowing through the first power disconnect switch <NUM>. The gate driver circuit logic <NUM> implements the delayed turn on time based on the sensed drain-to-source voltage VDS1 or the sensed current. For example, the second gate control signal B may be activated when the sensed drain-to-source voltage VDS1 drops below a certain voltage level, e.g., 'On_delay_V_ level' in <FIG> or when the sensed transistor current drops below a certain current level, e.g., similar to what is shown in <FIG> for I_PIN.

<FIG> illustrates another embodiment of an electronic system <NUM> that includes the power conversion circuit <NUM> coupled between the load <NUM> and the power source <NUM>. According to this embodiment, a sensor <NUM> is provided for sensing a current I_RSEN flowing through a resistor RSEN coupled between the power source <NUM> and the first power disconnect switch <NUM>. The gate driver circuit logic <NUM> implements the delayed turn on time for the second power disconnect switch <NUM> based on the sensed current I_RSEN flowing through the resistor RSEN. For example, the second gate control signal B may be activated when the sensed current I_RSEN drops below a certain level, e.g., similar to what is shown in <FIG> for I_PIN.

<FIG> illustrates another embodiment of an electronic system <NUM> that includes the power conversion circuit <NUM> coupled between the load <NUM> and the power source <NUM>. According to this embodiment, a sensor <NUM> is provided for sensing the voltage VDC of the bulk or dc bus capacitor CDC that is electrically coupled to the power input node PIN of the inverter/converter <NUM>. The gate driver circuit logic <NUM> implements the delayed turn on time for the second power disconnect switch <NUM> based on the sensed voltage VDC of the capacitor CDC. For example, the second gate control signal B may be activated when the sensed capacitor voltage VDC rises about a certain level, e.g., <NUM>% or more and which indicates sufficient charging of the capacitor CDC and thus a reduction in the inrush current I_inrush from the peak I_pk.

<FIG> illustrates another embodiment of an electronic system <NUM> that includes the power conversion circuit <NUM> coupled between the load <NUM> and the power source <NUM>. The embodiment shown in <FIG> is similar to the embodiment shown in <FIG>. Different, however, a resistor divider R1, R2 is used to sense a reduced (lower) voltage VDIV which corresponds to the voltage VDC of the bulk or dc bus capacitor CDC. The gate driver circuit logic <NUM> implements the delayed turn on time for the second power disconnect switch <NUM> based on the lower sensed voltage VDIV. For example, the second gate control signal B may be activated when the lower sensed voltage VDIV rises about a certain level which indicates sufficient charging of the capacitor CDC and thus a reduction in the inrush current I_inrush from the peak I_pk.

<FIG> illustrates another embodiment of an electronic system <NUM> that includes the power conversion circuit <NUM> coupled between the load <NUM> and the power source <NUM>. According to this embodiment, the gate driver circuit <NUM> implements the delayed turn-on time <NUM> for the second power disconnect switch <NUM> but not the delayed turn-off time <NUM> via a single driver <NUM>. The single driver <NUM> outputs the first gate control signal A without any intentional delay, e.g., based on a switching control signal PWM received from the controller <NUM> as previously described herein. The gate driver circuit <NUM> generates the second gate control signal B by applying the delayed turn on time <NUM> to the output of the single driver <NUM>.

<FIG> illustrates another embodiment of an electronic system <NUM> that includes the power conversion circuit <NUM> coupled between the load <NUM> and the power source <NUM>. According to this embodiment, the gate driver circuit <NUM> implements the delayed turn-on time <NUM> for the second power disconnect switch <NUM> but not the delayed turn-off time <NUM> via two separate drivers <NUM>, <NUM>. The first driver <NUM> outputs the first gate control signal A without any intentional delay, e.g., based on a switching control signal PWM received from the controller <NUM> as previously described herein. The gate driver circuit <NUM> applies the delayed turn on time <NUM> to the same signal input to the first driver <NUM>. The second driver <NUM> outputs the second gate control signal B with the added delay.

<FIG> illustrates another embodiment of an electronic system <NUM> that includes the power conversion circuit <NUM> coupled between the load <NUM> and the power source <NUM>. The embodiment shown in <FIG> is similar to the embodiment illustrated in <FIG>. Different, however, the first power disconnect switch <NUM> is monolithically integrated with the gate driver circuit <NUM>, e.g., in a common semiconductor die (chip) or module. The second power disconnect switch <NUM> may be a discrete device, e.g., a different semiconductor die or module separate from the first power disconnect switch <NUM> and the gate driver circuit <NUM>.

<FIG> illustrates another embodiment of an electronic system <NUM> that includes the power conversion circuit <NUM> coupled between the load <NUM> and the power source <NUM>. The embodiment shown in <FIG> is similar to the embodiment shown in <FIG>. Different, however, the sensor <NUM> for sensing the drain-to-source voltage VDS1 of the first power disconnect switch <NUM> or a current flowing through the first power disconnect switch <NUM> is also monolithically integrated with the gate driver circuit <NUM> and the first power disconnect switch <NUM>.

Although the present disclosure is not so limited, the following numbered examples demonstrate one or more aspects of the disclosure.

However, the invention is solely defined by the appended claims.

Example <NUM>. A gate driver circuit, comprising: at least one driver configured to generate a first gate control signal for a first power disconnect switch and a second gate control signal for a second power disconnect switch in parallel with the first power disconnect switch; and logic configured to implement a delayed turn on time for the second gate control signal compared to the first gate control signal such that the first power disconnect switch turns on before the second power disconnect switch when powering up a load coupled to the first and the second power disconnect switches.

Example <NUM>. The gate driver circuit of example <NUM>, wherein the logic is configured to implement the delayed turn on time based on a sensed drain-to-source voltage of the first power disconnect switch or a sensed current flowing through the first power disconnect switch.

Example <NUM>. The gate driver circuit of example <NUM> or <NUM>, wherein the logic is configured to implement the delayed turn on time based on a programmed delay value.

Example <NUM>. The gate driver circuit of any of examples <NUM> through <NUM>, wherein the logic is configured to implement the delayed turn on time based on a sensed current flowing through a resistor coupled between a power source and the first power disconnect switch.

Example <NUM>. The gate driver circuit of any of examples <NUM> through <NUM>, wherein the logic is configured to implement the delayed turn on time based on a sensed voltage of a capacitor between the first power disconnect switch and ground.

Example <NUM>. The gate driver circuit of any of examples <NUM> through <NUM>, wherein the load is a power conversion system, and wherein the logic is configured to implement the delayed turn on time based on a sensed voltage of a decoupling bulk capacitor or a dc bus capacitor at an input of the power conversion system that is being charged when the first power disconnect switch is being turned on.

Example <NUM>. The gate driver circuit of any of examples <NUM> through <NUM>, wherein the gate driver circuit comprises a single driver, wherein the single driver is configured to output the first gate control signal, and wherein the logic is configured to generate the second gate control signal by applying the delayed turn on time to the output of the single driver.

Example <NUM>. The gate driver circuit of any of examples <NUM> through <NUM>, wherein the gate driver circuit comprises a first driver and a second driver, wherein the first driver is configured to generate the first gate control signal based on a switching control signal received from a controller, and wherein the logic is configured to apply the delayed turn on time to the switching control signal for input to the second driver.

Example <NUM>. The gate driver circuit of any of examples <NUM> through <NUM>, wherein the logic is further configured to implement a delayed turn off time for the second gate control signal compared to the first gate control signal such that the first power disconnect switch turns off before the second power disconnect switch when powering down the load coupled to the first and the second power disconnect switches.

Example <NUM>. The gate driver circuit of example <NUM>, wherein the delayed turn off time is such that the first power disconnect switch is completely turned off before the second power disconnect switch begins to turn off.

Example <NUM>. The gate driver circuit of example <NUM> or <NUM>, wherein the delayed turn off time is such that the second power disconnect switch has a controlled turn off when powering down the load coupled to the first and the second power disconnect switches.

Example <NUM>. The gate driver circuit of any of examples <NUM> through <NUM>, wherein the logic is configured to implement the delayed turn off time based on a programmed delay value.

Example <NUM>. The gate driver circuit of any of examples <NUM> through <NUM>, wherein the first power disconnect switch is monolithically integrated with the gate driver circuit.

Example <NUM>. The gate driver circuit of any of examples <NUM> through <NUM>, wherein the first power disconnect switch comprises a plurality of first transistors coupled in parallel and controlled by the same first gate control signal, and wherein the second power disconnect switch comprises a plurality of second transistors coupled in parallel and controlled by the same second gate control signal.

Example <NUM>. A power conversion circuit, comprising: an inverter/converter; a capacitor electrically coupled to a power input node of the inverter/converter; a first transistor electrically coupled between a power input node of the power conversion circuit and the power input node of the inverter/converter; a second transistor in parallel with the first transistor and electrically coupled between the power input node of the power conversion circuit and the power input node of the inverter/converter; a controller configured to operate the first transistor and the second transistor as disconnect switches when disconnecting the power input node of the power conversion circuit from the power input node of the inverter/converter; and a gate driver circuit configured to generate a first gate control signal for the first transistor and a second gate control signal for the second transistor, the second gate control signal having a delayed turn on time compared to the first gate control signal such that the first transistor turns on before the second transistor when powering up a load coupled to the first and the second power disconnect switches.

Example <NUM>. The power conversion circuit of example <NUM>, further comprising: a sensor configured to sense a drain-to-source voltage of the first transistor or a current flowing through the first transistor, wherein the gate driver circuit is configured to implement the delayed turn on time based on the sensed drain-to-source voltage of the first transistor or the sensed current flowing through the first transistor.

Example <NUM>. The power conversion circuit of example <NUM> or <NUM>, wherein the gate driver circuit is configured to implement the delayed turn on time based on a programmed delay value.

Example <NUM>. The power conversion circuit of any of examples <NUM> through <NUM>, further comprising: a sensor configured to sense a current flowing through a resistor coupled between a power source and the first transistor, wherein the gate driver circuit is configured to implement the delayed turn on time based on the sensed current flowing through the resistor.

Example <NUM>. The power conversion circuit of any of examples <NUM> through <NUM>, further comprising: a sensor configured to sense a voltage of the capacitor, wherein the gate driver circuit is configured to implement the delayed turn on time based on the sensed voltage of the capacitor.

Example <NUM>. The power conversion circuit of any of examples <NUM> through <NUM>, wherein the gate driver circuit is further configured to generate the first gate control signal and the second gate control signal such that the second gate control signal has a delayed turn off time compared to the first gate control signal and the first transistor turns off before the second transistor when powering down the load coupled to the first and the second power disconnect switches.

Example <NUM>. The power conversion circuit of any of examples <NUM> through <NUM>, wherein the first transistor has a different gate charge characteristic and a different plateau voltage compared to the second transistor.

Example <NUM>. The power conversion circuit of any of examples <NUM> through <NUM>, further comprising: one or more additional first transistors coupled in parallel with the first transistor and controlled by the first gate control signal; and one or more additional second transistors coupled in parallel with the second transistor and controlled by the second gate control signal.

Example <NUM>. The power conversion circuit of any of examples <NUM> through <NUM>, wherein the first transistor is monolithically integrated with the gate driver circuit, and wherein the second transistor is a discrete device separate from the first transistor and the gate driver circuit.

Example <NUM>. An electronic system, comprising: a load; an inverter/converter coupled to the load; a capacitor electrically coupled to a power input node of the inverter/converter; a power source; a first transistor electrically coupled between the power source and the power input node of the inverter/converter; a second transistor in parallel with the first transistor and electrically coupled between the power source and the power input node of the inverter/converter; a controller configured to operate the first transistor and the second transistor as disconnect switches when disconnecting the power source from the load; and a gate driver circuit configured to generate a first gate control signal for the first transistor and a second gate control signal for the second transistor, the second gate control signal having a delayed turn on time compared to the first gate control signal such that the first transistor turns on before the second transistor when powering up the load.

Example <NUM>. The electronic system of example <NUM>, wherein the load is a multi-phase motor and the power source is a battery.

Example <NUM>. The electronic system of example <NUM> or <NUM>, wherein the gate driver circuit is further configured to generate the first gate control signal and the second gate control signal such that the second gate control signal has a delayed turn off time compared to the first gate control signal and the first transistor turns off before the second transistor when powering down the load.

Example <NUM>. A method of driving a first power disconnect switch and a second power disconnect switch coupled in parallel with the first power disconnect switch, the method comprising: generating a first gate control signal for the first power disconnect switch and a second gate control signal for the second power disconnect switch; and implementing a delayed turn on time for the second gate control signal compared to the first gate control signal such that the first power disconnect switch turns on before the second power disconnect switch when powering up a load coupled to the first and the second power disconnect switches.

Example <NUM>. The method of example <NUM>, further comprising: implementing a delayed turn off time for the second gate control signal compared to the first gate control signal such that the first power disconnect switch turns off before the second power disconnect switch when powering down the load.

Example <NUM>. The method of example <NUM> or <NUM>, wherein the delayed turn off time is implemented such that the first transistor is completely turned off before the second transistor begins to turn off.

Example <NUM>. The method of example <NUM> or <NUM>, wherein the second gate control signal is generated such that the second transistor has a controlled turn off when powering down the load.

Example <NUM>. A power conversion circuit, comprising: an inverter/converter; a bulk capacitor electrically coupled to a power input node of the inverter/converter; a first transistor electrically coupled between a power input node of the power conversion circuit and the power input node of the inverter/converter; a second transistor in parallel with the first transistor and electrically coupled between the power input node of the power conversion circuit and the power input node of the inverter/converter; a controller configured to operate the first transistor and the second transistor as disconnect switches when disconnecting the power input node of the power conversion circuit from the power input node of the inverter/converter; and a gate driver circuit configured to generate a first gate control signal for the first transistor and a second gate control signal for the second transistor, the second gate control signal having a delayed turn on time compared to the first gate control signal such that the first transistor turns on before the second transistor and the capacitor begins to draw an inrush current through the first transistor but not the second transistor.

Claim 1:
A gate driver circuit, comprising:
at least one driver (<NUM>, <NUM>; <NUM>) configured to generate a first gate control signal (A) for a first power disconnect switch (<NUM>) and a second gate control signal (B) for a second power disconnect switch (<NUM>) in parallel with the first power disconnect switch (<NUM>); and
logic (<NUM>) configured to implement a delayed turn on time for the second gate control signal (B) compared to the first gate control signal (A) such that the first power disconnect switch (<NUM>) turns on before the second power disconnect switch (<NUM>) when powering up a load (<NUM>) coupled to the first and the second power disconnect switches (<NUM>, <NUM>),
characterized in that
the logic (<NUM>) is configured to implement the delayed turn on time based on one of
a sensed drain-to-source voltage of the first power disconnect switch (<NUM>) or a sensed current flowing through the first power disconnect switch (<NUM>),
a sensed current flowing through a resistor (RSEN) coupled between a power source (<NUM>) and the first power disconnect switch (<NUM>),
a sensed voltage of a capacitor (CDC) between the first power disconnect switch (<NUM>) and ground, or,
if the load (<NUM>) is a power conversion system (<NUM>), based on a sensed voltage of a decoupling bulk capacitor or a dc bus capacitor (CDC) at an input of the power conversion system (<NUM>) that is being charged when the first power disconnect switch (<NUM>) is being turned on.