Patent Description:
A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices.

<CIT> generally relates to a reference voltage generating circuit that receives a power supply voltage and generates a reference voltage. A reference voltage level guarantee circuit generates a sense signal when the circuit senses that a value of the reference voltage has reached a predetermined value. A power supply voltage sensing circuit has a voltage comparator circuit which compares a voltage obtained by dividing a power supply voltage with the reference voltage and outputs a power ON reset signal. An operation of the voltage comparator circuit is controlled based on a sense signal. When the value of the power supply voltage increases and the value of the reference voltage reaches a predetermined value, the voltage comparator circuit operates, and a power ON reset signal is outputted in response to a result of comparison between a divisional voltage and the reference voltage.

<CIT>generally relates to a power on reset (POR) generator circuit including a modified bandgap POR circuit in series with a modified RC POR circuit. During a fast or slow power up, the circuit behaves like a traditional bandgap POR circuit, providing a POR signal when the voltage on an internal node rises higher than a reference voltage.

<CIT> generally relates to a power detecting device, a power supply device using the same, and a reference voltage generator. The power detecting device adapted to detect a power voltage of a display device includes a bandgap voltage generating circuit, a voltage regulating circuit, and a power-on reset circuit. The bandgap voltage generating circuit provides a reference voltage via an output terminal thereof. The voltage regulating circuit and the power-on reset circuit are coupled to the output terminal of the bandgap voltage generating circuit. When the power voltage doesn't reach a threshold voltage, the voltage regulating circuit increases the reference voltage referred by the power-on reset circuit. When the power voltage reaches the reference voltage, the power-on reset circuit generates a reset signal to reset the display device.

In a first aspect, a system is provided according to claim <NUM>. In a second aspect, a method is provided according to claim <NUM>.

Aspects of the present disclosure are directed to a memory sub-system, in particular to memory sub-systems that include a power-on-reset (POR) component. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with <FIG>, et alibi. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

Power-on-reset (POR) circuitry (e.g., component) is often used in memory sub-systems to ensure proper functionality of the sub-systems when power (e.g., power supply voltage) is initially applied to the sub-systems. For example, the POR circuitry can prevent various internal logic circuitries, such as latches, flip-flops, and/or registers, of the sub-systems from functioning until after the POR circuitry determines that the power supply voltage has reached a particular voltage level.

However, various POR circuitries can have drawbacks. For example, some POR circuitries (e.g., resistor-capacitor (RC)-based POR circuitries) can be limited in its capability of using a wide range of resistance and/or capacitance values due to a limited size of the POR circuitries and/or a limited speed at which the power supply voltage increases. For example, some POR circuitries (e.g., diode-based POR circuitries) may not function properly when the power supply voltage being supplied to the POR circuitries is of a relatively small value compared to a voltage being forwarded from the diode, which can lead to difficulties in monitoring the power supply voltage accurately. Due to these drawbacks, the POR circuitries in various approaches can be vulnerable to process-voltage-temperature (PVT) variation effects, which can lead to falsely indicating that the power supply voltage is sufficiently high to power on (e.g., reset) the memory sub-system, when the power supply voltage is actually not sufficiently high to do so.

In contrast, embodiments herein can provide a plurality of voltage generators configured to generate respective voltages based on a power supply voltage and utilize one of the generated voltages that is relatively insensitive to the PVT variation effects to indicate that another one (e.g., reference voltage) of the generated voltages is reliable as a measurement with respect to a voltage level of the power supply voltage. The capability to indicate that the other one of the voltages is reliable can reduce/eliminate instances in which the voltage level of the power supply voltage is falsely measured due to the PVT variation effects, among other benefits.

<FIG> illustrates an example computing system <NUM> that includes a memory sub-system <NUM> in accordance with some embodiments of the present disclosure. The memory sub-system <NUM> can include media, such as one or more volatile memory devices (e.g., memory device <NUM>), one or more non-volatile memory devices (e.g., memory device <NUM>), or a combination of such.

A memory sub-system <NUM> can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory module (NVDIMM).

The computing system <NUM> can be a computing device such as a desktop computer, laptop computer, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), Internet of Things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device.

The computing system <NUM> can include a host system <NUM> that is coupled to one or more memory sub-systems <NUM>. In some embodiments, the host system <NUM> is coupled to different types of memory sub-system <NUM>. <FIG> illustrates one example of a host system <NUM> coupled to one memory sub-system <NUM>. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc..

The host system <NUM> can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system <NUM> uses the memory sub-system <NUM>, for example, to write data to the memory sub-system <NUM> and read data from the memory sub-system <NUM>.

The host system <NUM> can be coupled to the memory sub-system <NUM> via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., DIMM socket interface that supports Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transmit data between the host system <NUM> and the memory sub-system <NUM>. The host system <NUM> can further utilize an NVM Express (NVMe) interface to access the components (e.g., memory devices <NUM>) when the memory sub-system <NUM> is coupled with the host system <NUM> by the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system <NUM> and the host system <NUM>. <FIG> illustrates a memory sub-system <NUM> as an example. In general, the host system <NUM> can access multiple memory sub-systems via a same communication connection, multiple separate communication connections, and/or a combination of communication connections.

The memory devices <NUM>, <NUM> can include any combination of the different types of non-volatile memory devices and/or volatile memory devices. The volatile memory devices (e.g., memory device <NUM>) can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

Some examples of non-volatile memory devices (e.g., memory device <NUM>) include negative-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

Each of the memory devices <NUM> can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), and quad-level cells (QLCs), can store multiple bits per cell. In some embodiments, each of the memory devices <NUM> can include one or more arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, or any combination of such. In some embodiments, a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory devices <NUM> can be grouped as pages that can refer to a logical unit of the memory device used to store data. With some types of memory (e.g., NAND), pages can be grouped to form blocks.

Although non-volatile memory components such as 3D cross-point array of non-volatile memory cells and NAND types memory (e.g., 2D NAND, 3D NAND) are described, the memory device <NUM> can be based on any other type of non-volatile memory or storage device, such as such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto random access memory (MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), negative-or (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

The memory sub-system controller <NUM> (or controller <NUM> for simplicity) can communicate with the memory devices <NUM> to perform operations such as reading data, writing data, or erasing data at the memory devices <NUM> and other such operations. The memory sub-system controller <NUM> can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (e.g., hard-coded) logic to perform the operations described herein. The memory sub-system controller <NUM> can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

The memory sub-system controller <NUM> can include a processor <NUM> (e.g., processing device) configured to execute instructions stored in a local memory <NUM>. In the illustrated example, the local memory <NUM> of the memory sub-system controller <NUM> includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system <NUM>, including handling communications between the memory sub-system <NUM> and the host system <NUM>.

In some embodiments, the local memory <NUM> can include memory registers storing memory pointers, fetched data, etc. The local memory <NUM> can also include read-only memory (ROM) for storing micro-code. While the example memory sub-system <NUM> in <FIG> has been illustrated as including the memory sub-system controller <NUM>, in another embodiment of the present disclosure, a memory sub-system <NUM> does not include a memory sub-system controller <NUM>, and can instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

In general, the memory sub-system controller <NUM> can receive commands or operations from the host system <NUM> and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device <NUM> and/or the memory device <NUM>. The memory sub-system controller <NUM> can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices <NUM>. The memory sub-system controller <NUM> can further include host interface circuitry to communicate with the host system <NUM> via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory device <NUM> and/or the memory device <NUM> as well as convert responses associated with the memory device <NUM> and/or the memory device <NUM> into information for the host system <NUM>.

The memory sub-system controller <NUM> includes a power reset component <NUM> that can operate in combination with a POR component <NUM> to provide a reset signal to various components and/or circuitries of the memory sub-system <NUM>. For example, the power reset component <NUM> can receive a reset signal from the POR component <NUM> and operate to transfer (e.g., provide) the received signal to the components and/or circuitries of the memory sub-system <NUM>. As described herein, the POR component can be located internal to the power reset component <NUM> and/or the memory sub-system controller <NUM>, although embodiments are not so limited.

The memory sub-system <NUM> can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system <NUM> can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory sub-system controller <NUM> and decode the address to access the memory device <NUM> and/or the memory device <NUM>.

In some embodiments, the memory device <NUM> includes local media controllers <NUM> that operate in conjunction with memory sub-system controller <NUM> to execute operations on one or more memory cells of the memory devices <NUM>. An external controller (e.g., memory sub-system controller <NUM>) can externally manage the memory device <NUM> (e.g., perform media management operations on the memory device <NUM>). In some embodiments, a memory device <NUM> is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller <NUM>) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

The memory sub-system <NUM> includes a POR component <NUM> that can be configured to determine when to provide a reset signal to various components of the memory sub-system <NUM>, such as memory sub-system controller <NUM>, memory device <NUM>, and/or memory device <NUM>, as well as other components/circuitries, such as internal circuitries including, and not limited to, fuse circuits, reference voltage circuits, and/or charge pump circuits, among other internal circuitries that can be used to perform operations on the memory devices <NUM> and/or <NUM>. Embodiments are not limited to a particular location of the memory sub-system <NUM> where the POR component <NUM> can be located. In one example, the POR component <NUM> can be located in a power management unit, such as a power management integrated circuit (PMIC), of the memory sub-system <NUM>. In another example, the POR component <NUM> can be located internal to the memory sub-system <NUM>, such as in the power reset component <NUM>, and operate in combination with the power reset component <NUM> to perform the operations described herein.

In some embodiments, the POR component <NUM> can monitor a voltage level of a power supply voltage (e.g., from the host system <NUM>), and in response to determining that the voltage level of the power supply voltage has increased to and/or reached an initial threshold voltage level, the POR component <NUM> can switch its power state from, for example, a reduced power state (e.g., powered-down state) to an active state. During the active state, the POR component <NUM> can generate a plurality of voltages based on the power supply voltage that can be utilized as measurements for indicating and/or ensuring that the power supply is high sufficient to reset the memory sub-system <NUM> properly. In response to determining that a voltage level of the power supply voltage has reached a threshold, the POR component <NUM> can provide a reset signal to various components and/or circuitries of the memory sub-system <NUM> that switch their power states based on the reset signal. Various sub-components and/or circuitries of the POR component <NUM> are further illustrated in <FIG>, <FIG>, <FIG>, and <FIG>.

<FIG> illustrates example circuitry of a POR component <NUM> in accordance with some embodiments of the present disclosure. As shown in <FIG>, the POR component <NUM> can include a plurality of voltage (e.g., and/or signal) generators, such as a reference voltage generator <NUM>, a power-up voltage generator <NUM>, and a ready signal generator <NUM> that are coupled to a logic sub-component <NUM>. The POR component <NUM> can be analogous to the POR component <NUM> illustrated in <FIG>.

The reference voltage generator <NUM> can be configured to receive a power supply voltage (e.g., from the host system <NUM>) as an input and generate a reference voltage (e.g., shown as VREF in <FIG>) based on the received power supply. In some embodiments, the reference voltage generated at the reference voltage generator <NUM> can be a bandgap reference voltage. As used herein, the term "bandgap reference voltage" refers to a voltage generated at circuitry that is configured to generate a fixed and constant voltage regardless of power supply variations, temperature changes, and circuit loading of the circuitries.

The power-up voltage generator <NUM> can be configured to receive the power supply voltage as an input and generate a power-up voltage (e.g., shown as VPU in <FIG>) based on the received power supply. As described herein, the power-up voltage generated at the power-up voltage generator <NUM> can be compared to the reference voltage generated at the reference voltage generator <NUM> for partially indicating whether the power supply voltage has reached a threshold voltage level.

The ready signal generator <NUM> can be configured to provide a ready signal (e.g., shown as READY in <FIG>). As further illustrated in <FIG>, the ready signal generator <NUM> includes a current mirror that can replicate a voltage based on the power supply voltage and output the ready signal when the replicated voltage has reached a threshold voltage level of a logic gate (e.g., inverter) coupled to an output of the ready signal generator <NUM>.

That the power supply voltage is high sufficient to reset various internal components and/or circuitries of the memory sub-system (e.g., the memory sub-system <NUM> illustrated in <FIG>) can be indicated at least partially based on a determination that the reference voltage has reached the power-up voltage. However, while a voltage level of the power supply voltage is relatively low, the reference voltage can be subject to a substantially large degree of a slew rate. As used herein, the term "slew rate" refers to a change of an electrical quantity, such as voltage or current, per unit of time (e.g., volts/second or amperes/second).

For example, while the power supply voltage is not high sufficient to properly operate the memory sub-system (e.g., memory sub-system <NUM> illustrated in <FIG>), the reference voltage can temporarily reach a voltage level of the power-up voltage, and can possibly decrease again below the voltage level of the power-up voltage. Therefore, the reset signal that has been triggered when the reference voltage has temporarily reached the threshold voltage level may indeed misdirect to the memory sub-system to reset. Embodiments described herein can operate, therefore, the ready signal generator <NUM> to ensure that the reference voltage being output from the reference voltage generator <NUM> is steady, which indicates that the power supply voltage is indeed high sufficient to operate the memory sub-system properly.

The logic sub-component <NUM> can be configured to receive voltages/signals from the reference voltage generator <NUM>, the power-up voltage generator <NUM>, and the ready signal generator <NUM> as respective inputs, and provide a reset signal (e.g., shown as POR_OUT) based on comparisons among those inputs. For example, the logic sub-component <NUM> can be configured to output the reset signal based on a comparison of the reference voltage to the power-up voltage and an indication that the reference voltage has entered a steady state and is reliable as a measurement with respect to a voltage level of the power supply voltage. As described further in connection with <FIG>, the indication can be determined based on a comparison of the replicated voltage generated at the ready signal generator <NUM> to a threshold voltage level of the logic gate coupled to the output of the ready signal generator <NUM>. Further details of the logic sub-component <NUM> are illustrated in connection with <FIG>.

<FIG> illustrates an example reference voltage generator <NUM> of a POR component (e.g., the POR component <NUM> and <NUM> illustrated in <FIG> and <FIG>) in accordance with some embodiments of the present disclosure. The reference voltage generator <NUM> can be analogous to the reference voltage generator <NUM> illustrated in <FIG>.

The reference voltage generator <NUM> can include reference circuitry <NUM> that is configured to generate a voltage based on a power supply voltage (e.g., VDD as shown in <FIG>). The reference circuity <NUM> can include an operational amplifier, resistors, and diodes. Although embodiments are not so limited, the voltage generated utilizing the reference circuitry <NUM> can be a bandgap reference voltage. An output voltage of the reference circuitry <NUM> can be analogous to a voltage on a resistor <NUM>.

The reference voltage generator <NUM> can include start-up circuitry <NUM> that is configured to provide, while the voltage being generated at the reference circuitry <NUM> has not reached a threshold (e.g., desired) voltage level, a signal (e.g., voltage) to the reference circuitry <NUM> such that the reference circuitry <NUM> can maintain increasing of the voltage. In some embodiments, the start-up circuitry can be configured to provide an input voltage to the reference circuitry <NUM> that helps, along with the power supply voltage, the reference circuitry <NUM> to generate and increase the reference voltage. When the voltage from the reference circuitry <NUM> has reached the threshold voltage level, the start-up circuitry <NUM> can turn off.

The start-up circuitry <NUM> can also include a power-down (PD) channel coupled to a transistor (e.g., M3 as shown in <FIG>) that can be enabled to put the POR component (e.g., the POR component <NUM> and <NUM> illustrated in <FIG> and <FIG>) into the powered-down state. Although embodiments are not so limited, two inverters can be coupled to the PD channel in series.

At its output, the reference voltage generator <NUM> can include a low pass (LP) filter <NUM> and an operational amplifier <NUM>. The reference voltage generator <NUM> can operate the LP filter to filter noise from high frequency of the voltage provided from the reference circuitry <NUM>. The filtered voltage can be output to the comparator (e.g., the comparator <NUM> illustrated in <FIG>) as a reference voltage (e.g., shown as VREF in <FIG>) via the operational amplifier <NUM>, which can operate as a unity gain buffer that is an operational amplifier having a voltage gain of <NUM>. In some embodiments, the operational amplifier <NUM> and the operational amplifier of the reference circuitry <NUM> can be structurally cascaded.

<FIG> illustrates an example power-up voltage generator <NUM> of a POR component (e.g., the POR component <NUM> and <NUM> illustrated in <FIG> and <FIG>) in accordance with some embodiments of the present disclosure. The power-up voltage generator <NUM> can be analogous to the power-up voltage generator <NUM> illustrated in <FIG>.

As described herein, the power-up voltage generator <NUM> can receive a power supply voltage (e.g., VDD shown in <FIG>), and generate and output a power-up voltage using transistors and resistors, such as a transistor <NUM>, resistor <NUM>, and a resistor <NUM>. For example, the power-up voltage generator <NUM> can be configured to enable the transistor <NUM> having a gate coupled to an input configured to receive the power supply voltage (e.g., as well as to the PD channel). In some embodiments, the PD channel can be enabled to put the POR component in the powered-down state.

As described herein, the power-up voltage generated at the power-up voltage generator <NUM> can be compared to the reference voltage (e.g., generated at the reference voltage generator <NUM> and <NUM> illustrated in <FIG> and <FIG>, respectively) to partially indicate whether the power supply voltage is high sufficient to reset the memory sub-system properly. A relatively simple structural aspects of the power-up voltage generator <NUM> can provide benefits such as being insensitive to PVT variation effects without experiencing sheet resistance effect.

<FIG> illustrates an example ready signal generator <NUM> of a POR component (e.g., the POR component <NUM> and <NUM> illustrated in <FIG> and <FIG>) in accordance with some embodiments of the present disclosure. The ready signal generator <NUM> can be analogous to the ready signal generator <NUM> illustrated in <FIG>. The ready signal generator <NUM> can include various circuitries, such as transistors, resistors, diodes, and/or logic gates. For example, the ready signal generator <NUM> can include a diode <NUM>, resistor <NUM>, a first logic gate <NUM>, and a second logic gate <NUM>, among others. The ready signal generator <NUM> can also include the PD channel, which can be enabled to put the POR component into the powered-down state.

The ready signal generator <NUM> includes a current mirror, formed as a diode-based current mirror. As used herein, the term "current mirror" can refer to a device that can copy a current by replicating a voltage of its own or other devices. The ready signal generator <NUM> can receive a power supply voltage (e.g., shown as VDD) as an input that can also increase a voltage on a diode <NUM>. When the voltage on the diode <NUM> has reached a threshold voltage level of the diode <NUM>, the diode <NUM> can conduct an amount of current through itself, which results in a current flow over a resistor <NUM>. The ready signal generator <NUM> can initiate replicating, in response to the diode <NUM> being enabled, a voltage on the resistor <NUM> that is coupled to the first inverter <NUM>.

Based on a voltage level of the replicated voltage, the first inverter <NUM> can provide an output signal that is binary in nature and representing binary logic values such as a logical high "<NUM>" or logical low "<NUM>". For example, the first inverter <NUM> can provide an output signal with the logical low when the voltage level of the replicated voltage reaches and/or exceeds a threshold voltage level of the first inverter <NUM>, which can be analogous to a half of its output voltage, although embodiments are not so limited. In response to receipt of the signal from the first inverter <NUM>, the ready signal generator <NUM> can provide, via the second inverter <NUM>, a ready signal with having a logical high value to a logic gate, such as the logic gate <NUM> illustrated in <FIG>.

<FIG> illustrates an example logic sub-component <NUM> of a POR component (e.g., the POR component <NUM> and <NUM> illustrated in <FIG> and <FIG>) in accordance with some embodiments of the present disclosure. As illustrated in <FIG>, the logic sub-component <NUM> includes a comparator <NUM>, a first logic gate <NUM>, and a second logic gate <NUM>. The comparator <NUM> can receive (e.g., continuously monitor) a reference voltage (e.g., shown as VREF generated at the reference voltage generator <NUM> illustrated in <FIG>) and a power-up voltage (e.g., shown as VPU generated at the reference voltage generator <NUM> illustrated in <FIG>) as respective inputs as the input voltages are being increased in response to the power supply voltage increasing. In response to the inputs, the comparator <NUM> can be configured to compare the reference voltage and the power-up voltage to determine, for example, whether the reference voltage has reached the power-up voltage and provide a feedback signal based on the determination. For example, the feedback signal can indicate that the reference voltage level at a particular time has reached a voltage level of the power-up voltage at the particular time.

The first logic gate <NUM> can receive, as respective inputs, the feedback signal and the ready signal (e.g., shown as READY) respectively from the comparator <NUM> and the ready signal generator (e.g., the ready signal generator <NUM> illustrated in <FIG>). The feedback signal and the ready signal can be binary in nature and can represent binary logic values such as a logical high "<NUM>" or logical low "<NUM>". For example, the feedback signal and the ready signal can be of a logical high to enable the first logic gate <NUM>.

In response to the inputs, the logic sub-component <NUM> can provide, via the first logic gate <NUM> and the second logic gate <NUM>, a reset signal (e.g., shown as POR_OUT) to various components and/or circuitries of the memory sub-system (e.g., memory sub-system <NUM> illustrated in <FIG>). Although embodiments are not so limited, the first logic gate <NUM> can be a NAND gate and the second logic gate can be an inverter. For example, the first logic gate <NUM> as a NAND gate can provide an output signal having a logical low value when both of the signals received at the first logic gate <NUM> are of a logical high. In response to the output signal having a logical low value from the NAND gate, the second logic gate as an inverter can provide an output signal having a logical high value, which can be utilized as a reset signal.

Embodiments described herein can reduce the PVT variation effects on the POR component. For example, where the POR component described herein is implemented in <NUM> nanometer (nm) CMOS technology, the feedback signal ranges from <NUM> V to <NUM> V when measured under all PVT corners (e.g., fast-fast-fast to slow-slow-slow) over a temperature from -<NUM> to <NUM> with a slew rate of <NUM> microseconds (µs). Under the same PVT corners with the slew rate of <NUM>, the ready signal ranges from <NUM> V to <NUM> V. Utilizing the feedback signal in combination with the ready signal results in a reset signal ranging from <NUM> V to <NUM> V with the slew rate from <NUM> to <NUM>.

<FIG> illustrates an example of a graph <NUM> illustrating changes in voltage levels of respective voltages/signals generated at each one of a plurality of voltage generators as a power supply voltage increases in accordance with some embodiments of the present disclosure. A voltage <NUM> (e.g., shown as VDD in <FIG>) can be analogous to the power supply voltage described herein. Further, a voltage <NUM> (e.g., shown as VREF in <FIG>) and a voltage <NUM> (e.g., shown as VPU in <FIG>) can be analogous to the reference voltage (e.g., generated at the reference voltage generator <NUM> and <NUM> illustrated in <FIG> and <FIG>) and the power-up voltage (e.g., generated at the power-up voltage generator <NUM> and <NUM> illustrated in <FIG> and <FIG>), respectively. Further, a voltage corresponding to a signal <NUM> (e.g., shown as POR_OUT_pre in <FIG>), a voltage corresponding to a signal <NUM> (e.g., shown as READY in <FIG>), and a voltage corresponding to a signal <NUM> (e.g., shown as POR_OUT in <FIG>) can be analogous to a voltage corresponding to the feedback signal (e.g., generated at the comparator <NUM> illustrated in <FIG>), a voltage corresponding to the ready signal (e.g., generated at the ready signal generator <NUM> and <NUM> illustrated in <FIG> and <FIG>), and a voltage corresponding to the reset signal (e.g., generated at the logic sub-component <NUM> and <NUM> illustrated in <FIG> and <FIG>), respectively.

As shown in the graph <NUM>, as the power supply voltage <NUM> increases, the power-up voltage <NUM> and the reference voltage <NUM> that are generated based on the power supply voltage <NUM> increase as well. During an interval <NUM>, a slew rate of the reference voltage <NUM> can be relatively large due to the reference voltage <NUM> being not steady (e.g., unstable) while the power supply voltage is relatively low, which increases and decreases the reference voltage <NUM>, for example, above or below a voltage level of the power-up voltage <NUM> during the interval <NUM>. Therefore, the feedback signals triggered at <NUM> and <NUM> (e.g., during the interval <NUM>) are not reliable as a measurement for indicating that a voltage level of the power supply voltage is high sufficient to reset. To prevent the reset signal from being triggered in these instances, the ready signal can be utilized to filter the feedback signal <NUM> by ignoring the feedback signals at <NUM> and <NUM>. For example, as illustrated in <FIG>, the reset signal can be prevented from being output until the ready signal is triggered a time <NUM> despite the feedback signals <NUM> and <NUM>. Accordingly, the reset signal is triggered at a time <NUM> (e.g., subsequent to the time <NUM>).

<FIG> illustrates a flow diagram <NUM> of an example method for operating a POR component in accordance with some embodiments of the present disclosure. At block <NUM>, the POR component (e.g., the POR component <NUM> and <NUM> illustrated in <FIG> and <FIG>) can receive a power supply voltage as an input. As illustrated in <FIG>, the POR component can be coupled to (e.g., included in) a memory sub-system (e.g., memory sub-system <NUM> illustrated in <FIG>). In response to the power supply voltage, the POR component can further generate a reference voltage (e.g., a voltage generated at the reference voltage generator <NUM> and <NUM> illustrated in <FIG> and <FIG>) and a power-up voltage (e.g., a voltage generated at the power-up voltage generator <NUM> and <NUM> illustrated in <FIG> and <FIG>).

At block <NUM>, the POR component can generate a replicated voltage at a current mirror (the ready signal generator <NUM> and <NUM> illustrated in <FIG> and <FIG>). The current mirror can include a diode (e.g., diode <NUM> illustrated in <FIG>) and a logic gate (e.g., inverter <NUM> illustrated in <FIG>) coupled to an output of the current mirror. In some embodiments, the replicated voltage can be generated in response to a voltage on the diode having reached a threshold voltage level of the diode. In some embodiments, the replicated voltage can be a voltage on a resistor coupled to the diode and the logic gate of the current mirror.

At block <NUM>, the POR component can provide the reset signal to the memory sub-system in response to the reference voltage having reached the power-up voltage and the replicated voltage having reached a threshold voltage level of the logic gate of the current mirror. Stated alternatively, the POR component can prevent the reset signal from being provided to the memory sub-system in response to at least one of the reference voltage having not reached the power-up voltage or the replicated voltage having not reached the threshold voltage level. As described herein, the replicated voltage having reached the threshold voltage of the logic gate coupled to the output of the current mirror can indicate that the reference voltage has entered a steady state and is reliable as a measurement with respect to a voltage level of the power supply voltage.

<FIG> illustrates an example machine of a computer system <NUM> within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system <NUM> can correspond to a host system (e.g., the host system <NUM> of <FIG>) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system <NUM> of <FIG>) or can be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to the power reset <NUM> of <FIG>). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system <NUM> includes a processing device <NUM>, a main memory <NUM> (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory <NUM> (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system <NUM>, which communicate with each other via a bus <NUM>.

The processing device <NUM> represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device <NUM> can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device <NUM> is configured to execute instructions <NUM> for performing the operations and steps discussed herein. The computer system <NUM> can further include a network interface device <NUM> to communicate over the network <NUM>.

The data storage system <NUM> can include a machine-readable storage medium <NUM> (also known as a computer-readable medium) on which is stored one or more sets of instructions <NUM> or software embodying any one or more of the methodologies or functions described herein. The instructions <NUM> can also reside, completely or at least partially, within the main memory <NUM> and/or within the processing device <NUM> during execution thereof by the computer system <NUM>, the main memory <NUM> and the processing device <NUM> also constituting machine-readable storage media. The machine-readable storage medium <NUM>, data storage system <NUM>, and/or main memory <NUM> can correspond to the memory sub-system <NUM> of <FIG>.

In one embodiment, the instructions <NUM> include instructions to implement functionality corresponding to a power reset component (e.g., the power reset component <NUM> of <FIG>). While the machine-readable storage medium <NUM> is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

The present invention can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present invention. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc..

Claim 1:
A system, comprising:
a reference voltage generator (<NUM>; <NUM>) configured to generate a reference voltage (<NUM>) based on a power supply voltage (<NUM>), a power-up voltage generator (<NUM>; <NUM>) configured to generate a power-up voltage (<NUM>) based on the power supply voltage (<NUM>), and a ready signal generator (<NUM>; <NUM>) configured to generate a replicated voltage based on the power supply voltage (VDD), wherein the ready signal generator (<NUM>; <NUM>) comprises a current mirror configured to generate the replicated voltage, the current mirror comprising a diode (<NUM>); and
a logic sub-component (<NUM>; <NUM>) coupled to the reference voltage generator (<NUM>; <NUM>) and configured to output a reset signal (<NUM>) based on:
determination that the reference voltage (<NUM>) has reached a voltage level of the power-up voltage (<NUM>); and
an indication that the reference voltage (<NUM>) has entered a steady state and is reliable as a measurement with respect to a voltage level of the power supply voltage (<NUM>), wherein the indication is determined based on a comparison of the replicated voltage to a particular threshold voltage level, and wherein the particular threshold voltage level corresponds to a threshold voltage level of a logic gate (<NUM>) coupled to an output of the current mirror.