Patent Description:
An Organic Light-Emitting Diode (OLED) display device comprises an anode, an organic layer, and a cathode. The organic layer includes a hole transport layer, an electron transport layer, and an organic light-emitting layer located between the hole transport layer and the electron transport layer. Compared with an Liquid-Crystal Display (LCD) device, the OLED display device has advantages such as thin, light, wide visual angle, actively emitting light, continuous and adjustable color of emitting light, low cost, high response speed, low energy consumption, low driving voltage, wide working temperature range, simple production process, high light emitting efficiency, and capable of being flexibly displayed and the like. Because of these incomparable advantages and good application prospect compared to other displays, the OLED display has obtained great attention from industry and the scientific community.

<CIT> discloses an organic EL (OEL) device comprising two or more first banks extending in a line state; a plurality of second banks defining pixel regions by dividing a region between adjacent first banks and having a height lower than that of the first bank; a hole transport layer provided independently for each pixel region; and an insulating inorganic film provided on edges of the pixel region, which edges extend along side faces of the two first banks facing each other and defining the pixel regions. <CIT> discloses an organic light emitting diode display including pixel electrodes formed on a substrate; a pixel definition layer between the pixel electrodes and partitioning a pixel area; organic emission layers of a plurality of colors on the pixel electrodes; and a common electrode on the organic emission layers. The pixel definition layer includes a first pattern and a second pattern having different formation materials, thicknesses, and extension directions.

Accordingly, one example of the present disclosure is an array substrate according to claim <NUM>. The array substrate includes a base substrate and a pixel define layer on the base substrate. The pixel define layer comprises a plurality of thickness thinning regions. The thickness thinning regions have a smaller height than other areas of the pixel define layer on the base substrate, and the plurality of the thickness thinning regions are configured to guide flow of fillers to form an encapsulating layer on the pixel define layer.

The pixel define layer comprises a plurality of first spacing parts and a plurality of second spacing parts intersecting the plurality of the first spacing parts. Each of the plurality of the second spacing parts includes a plurality of second spacing sub-parts. A height of each of the plurality of the second spacing sub-parts is smaller than that of each of the plurality of the first spacing parts. Each of the thickness thinning regions comprises a plurality of the second spacing sub-parts between two adjacent first spacing parts. Each of the plurality of the first spacing parts has a rectangular strip shape. A length direction of the first spacing parts is a first direction. The plurality of the first spacing parts are distributed at intervals in a second direction. One of the first direction and the second direction may be a length direction of the base substrate, and the other may be a width direction of the base substrate.

The pixel define layer defines a plurality of pixel grids arranged in an array, and at least some of the pixel grids are located between two adjacent second spacing parts. Each of the pixel grids may have two pairs of opposite sides. One pair of the opposite sides may be respectively in contact with two adjacent first spacing parts, and the other pair of the opposite sides may be respectively in contact with two adjacent second spacing sub-parts. In one embodiment, a surface of each of the plurality of the first spacing parts is an arc-shaped surface. In another embodiment, a surface of each of the plurality of the first spacing parts is a flat surface. A surface of each of the plurality of the second spacing sub-parts may be an arc-shaped surface or a flat surface.

Heights of the plurality of the second spacing sub-parts in a same thickness thinning region gradually decrease or increase along the first direction. In one embodiment, a distance between any two adjacent second spacing sub-parts in a same thickness thinning region may gradually increase or decrease along the first direction. In another embodiment, a distance between any two adjacent second spacing sub-parts in a same thickness thinning region is the same along the first direction. A thickness of each of the plurality of the second spacing parts may be larger than or equal to <NUM> micrometers.

Another example of the present disclosure is a display panel. The Display panel includes an array substrate according to claim <NUM>. The display panel includes a cover plate stacked above the array substrate. The encapsulating layer may be arranged between the cover plate and the array substrate. Spacers may be arranged on one side of the cover plate facing the array substrate, and orthographic projection of the spacers on the array substrate may not overlap the thickness thinning regions. The display panel may be an OLED display panel.

Another example of the present disclosure is a method of fabricating a display panel. The method of fabricating a display panel includes forming a pixel define layer on a base substrate. The pixel define layer defines a plurality of pixel grids arranged in an array mode. The pixel define layer further includes a plurality of thickness thinning regions. The thickness thinning regions have a smaller height than other areas of the pixel define layer. The thickness thinning regions are configured to guide flow of fillers to form an encapsulating layer on the pixel define layer. The pixel define layer may be formed by masking and exposure.

Another example of the present disclosure is a display apparatus. The display apparatus includes an array substrate according to claim <NUM>.

The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:.

The present disclosure will be described in further detail with reference to the accompanying drawings and embodiments in order to provide a better understanding by those skilled in the art of the technical solutions of the present disclosure. Throughout the description of the disclosure, reference is made to <FIG>. When referring to the figures, like structures and elements shown throughout are indicated with like reference numerals.

In the description of the disclosures, the terms "length," "width," "thickness," "upper," "lower," and "inner," which indicate orientation or positional relation, are based on the orientation or positional relation shown in the figures. They are only for facilitating describing the present disclosure and simplifying the description. They do not indicate or imply the indicated device or element must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they cannot be construed as a limitation on the present disclosure. In addition, a "first" or a "second" feature can be explicitly or implicitly include one or more features. In the description of the present disclosure, unless otherwise indicated, "a plurality" means two or more than two.

In the description of the present disclosure, unless stated otherwise, the terms "installing," "connected" and "connection" should be construed broadly. For example, they can be construed as fixedly connected or detachably connected or integrally connected. They can be mechanically connected or electrically connected and can be directly connected or indirectly connected through an intermediate medium. There can also be an internal connection between two elements. A person of ordinary skill in the art would understand the specific meaning of the terms in the disclosure in specific situations.

Water vapor, oxygen and other components in the air have a great impact on the service life of OLEDs. The main reasons are as follows: during operation of the OLED, electrons need to be injected from the cathode. This requires the work function of the cathode to be as low as possible. Examples of the cathode material are aluminum, magnesium, calcium and other metal materials. However, these metal materials are all relatively active and easily react with penetrating water vapor. In addition, water vapor can chemically react with the hole transport layer and the electron transport layer so that the OLED can fail. Therefore, effective encapsulation of the OLED, so that functional layers of the device are isolated from water vapor, oxygen and other components in the atmosphere, can greatly extend service life of the device.

In the prior art, for a top-emitting OLED device, during the encapsulating process, fluidity of fillers for the filling encapsulating layer is usually low, thereby causing fillers for the filling encapsulating layer to be excessively filled or insufficiently filled. As a result, part of the device may not be sufficiently filled with fillers for the encapsulating layer, and accordingly bubbles are generated. Alternatively, part of the device is excessively filled with fillers for the encapsulating layer, and accordingly the auxiliary cathode fails. In some cases, the two problems occur in a same product.

An array substrate <NUM> is described according to embodiments of the present disclosure with reference to <FIG> as below.

In one embodiment, as shown in <FIG>, the array substrate <NUM> includes a base substrate <NUM> and a pixel define layer <NUM>.

Specifically, as shown in <FIG>, the pixel define layer <NUM> is arranged on the base substrate <NUM>. The pixel define layer <NUM> defines a plurality of pixels <NUM> arranged in an array. The pixel define layer <NUM> may have through holes <NUM>. The pixels <NUM> may be located in the through holes <NUM> respectively. The thickness at different areas of the pixel define layer <NUM> may be inconsistent. The pixel define layer <NUM> further comprises a plurality of thickness thinning regions <NUM>. The thickness thinning region <NUM> is suitable for guiding fillers for an encapsulating layer to flow. A pixel define layer <NUM> can be laid on a surface of one side of the base substrate <NUM>. The pixel define layer <NUM> includes a plurality of thickness thinning regions <NUM>. The thicknesses or heights of the areas defined by the thickness thinning regions <NUM> on the array substrate <NUM> are smaller than those of the other areas of the array substrate <NUM>. The "thickness" or "height" of the pixel define layer as used herein is measured from the surface of the base substrate facing the pixel define layer.

An array substrate <NUM> is provided according to one embodiment of the present disclosure. A pixel definition layer <NUM> is laid on the substrate <NUM>. A plurality of pixel grids <NUM> is defined by the pixel define layer <NUM>. The pixel define layer <NUM> further comprises a plurality of thickness thinning regions <NUM>. When the encapsulating layer <NUM> is filled to the array substrate <NUM>, the thickness thinning regions <NUM> can guide flow direction of fillers for the encapsulating layer <NUM> so that fillers for the encapsulating layer <NUM> can be more uniformly filled, thereby preventing situations in which fillers for the encapsulating layer <NUM> are excessively filled or not fully filled, which cause poor performance of an OLED or other devices on the array substrate.

In one embodiment, as shown in <FIG> and <FIG>, the pixel define layer <NUM> includes a plurality of first spacing parts <NUM> and a plurality of second spacing parts <NUM> intersecting the plurality of the first spacing parts. That is, the first spacing parts <NUM> are arranged along direction a and the second spacing parts <NUM> are arranged along direction b. Direction a and direction b are perpendicular to each other. The portion of the second spacing part between two adjacent first spacing parts is termed as a second spacing sub-part <NUM>. Each of the second spacing parts <NUM> includes a plurality of second spacing sub-parts <NUM> along direction b. The plurality of first spacing parts <NUM> defines a plurality of arrangement regions <NUM>. The arrangement region <NUM> is defined by any of two adjacent first spacing parts <NUM>. The second spacing sub-parts <NUM> form thickness thinning regions <NUM>. At least one of the plurality of the arrangement regions <NUM> includes a plurality of second spacing sub-parts <NUM> and a plurality of pixels along direction a. The plurality of first spacing parts <NUM> may be distributed at intervals. The plurality of the second spacing parts <NUM> form thickness thinning regions <NUM> of the array substrate <NUM>. That is, a thickness thinning region includes a plurality of second spacing sub-parts <NUM> along direction a. In one embodiment, the pixels <NUM> may be located between every two adjacent second spacing sub-parts <NUM>. In accordance with the claimed invention, some of the pixels <NUM> are located between two adjacent second spacing sub-parts <NUM>. Therefore, the positions of the pixels <NUM> are defined by the plurality of the first spacing parts <NUM> and the second spacing sub-parts <NUM>.

In one embodiment, the height of the second spacing part <NUM> is smaller than the height of the first spacing part <NUM>. That is, the distance between the side of the second spacing part <NUM> away from the base substrate <NUM> and the base substrate <NUM> is smaller than the distance between the side of the first spacing part <NUM> away from the base substrate <NUM> and the base substrate <NUM>. As such, fillers for the encapsulating layer <NUM> can flow along the thickness thinning regions <NUM> defined by the first spacing parts <NUM>.

In one embodiment as shown in <FIG>, the surface of a free end of the first spacing part <NUM> may have an arc-shaped surface. That is, the surface of one side of the first spacing part <NUM> away from the base substrate <NUM> may be formed as an arc-shaped surface. As such, fillers for the encapsulating layer <NUM> can smoothly flow through the arc-shaped surface, thereby facilitating fillers for the encapsulating layer <NUM> being fully filled in the whole area needed to be filled. Further, the arc-shaped surface protrudes in a direction away from the base substrate <NUM>. In other words, along a width direction of the first spacing part <NUM>, from the middle to the two sides of the arc-shaped surface, the distance between the arc-shaped surface and the base substrate <NUM> is gradually reduced. If the first spacing part <NUM> is cut in a direction perpendicular to the extension direction of the first spacing part <NUM>, the shape of the cross section of the first spacing part <NUM> at any position may be the same.

In another embodiment, the surface of the free end of the first spacing part <NUM> may be a plane or a flat surface. That is, the surface of the side of the first spacing part <NUM> away from the base substrate <NUM> is formed as a plane or a flat surface. In other words, the distance between any position on the surface of the first spacing part <NUM> away from the base substrate <NUM> to the base substrate <NUM> is equal. Resistance of a plane to a fluid is small, so fillers for the encapsulating layer <NUM> can quickly flow on the plane, thereby increasing filling rate. Meanwhile, a transition from the first spacing part <NUM> to the base substrate <NUM> is not smooth, thereby facilitating fillers for the encapsulating layer <NUM> being filled into designated areas.

In one embodiment of the present disclosure, a surface of a free end of the second spacing part <NUM> may be an arc surface or a plane. As shown in <FIG>, the surface of the side of the second spacing part <NUM> away from the base substrate <NUM> may be formed as a plane or a flat surface, thereby facilitating fillers for the encapsulating layer <NUM> being filled into designated areas. The surface of the second spacing part <NUM> away from the side of the base substrate <NUM> may also be formed as an arc-shaped surface. As such, fillers for the encapsulating layer <NUM> can smoothly flow through the arc-shaped surface, thereby facilitating the fillers for the encapsulating layer <NUM> being filled into the whole area needed to be filled.

In one embodiment as shown in <FIG>, the first spacing part <NUM> is a rectangular strip. A length direction of the first spacing part <NUM> is a first direction a. A plurality of the first spacing parts <NUM> is distributed in parallel at intervals along a second direction b. One of the first direction a and the second direction b is the length direction of the substrate <NUM> and the other is the width direction of the base substrate <NUM>. In one embodiment, the plurality of first spacing parts <NUM> can be arranged in parallel at intervals along the width direction of the substrate <NUM>. Any one of the first spacing parts <NUM> may be rectangular. The length direction of the rectangle may extend along the length direction of the base substrate <NUM>. In another embodiment, the plurality of the first spacing parts <NUM> may be arranged in parallel at intervals along the length direction of the base substrate <NUM>. Any one of the first spacing parts <NUM> may be rectangular. The length direction of the rectangle may extend along the width direction of the base substrate <NUM>. As such, fillers for the encapsulating layer <NUM> can be guided to flow along straight lines.

In one embodiment, along the second direction b, the distance between the two adjacent first spacing parts <NUM> may be gradually changed, for example, increased or decreased. That is, from one end to the other end of the array substrate along the second direction b, the distance between every two adjacent first spacing parts <NUM> can be gradually increased or gradually decreased. As such, first spacing parts <NUM> can be arranged according to an arrangement of the pixel grids.

In one embodiment, as shown in <FIG>, the distance between any two adjacent first spacing parts <NUM> may be equal. A plurality of first spacing parts <NUM> are uniformly distributed on the substrate <NUM> at intervals, thereby facilitating uniform arrangement of the pixel grids.

In one embodiment, as shown in <FIG>, a plurality of the second spacing parts <NUM> located in the same arrangement region <NUM> are distributed at intervals along the first direction a. In the same arrangement region <NUM>, the plurality of the second spacing parts <NUM> form a plurality of rows. Among the plurality of second spacing parts <NUM>, there are intervals between every two adjacent second spacing parts <NUM>. As such, the plurality of second spacing parts <NUM> can guide the encapsulating layer <NUM> to flow along a straight line.

In one embodiment, among the plurality of second spacing parts <NUM> located in the same arrangement region <NUM>, in the first direction a, the distance between the two adjacent second spacing parts <NUM> is gradually increased. As shown in <FIG>, from one end to the other end of the base substrate along the first direction a, the distance between every two adjacent second spacing parts <NUM> can be gradually increased or gradually decreased. As such, the arrangement mode of the pixel grids can be increased.

In one embodiment, among the plurality of the second spacing parts <NUM> located in the same arrangement region <NUM>, in the first direction a, the height of the plurality of the second spacing parts <NUM> is gradually decreased, as shown in <FIG>. From one end to the other end of the base substrate along the first direction a, the heights of the second spacing parts <NUM> are gradually decreased or gradually increased. Fillers for the encapsulating layer <NUM> are adapted to flow from one end to the other end of the base substrate along the first direction a. In a flow direction of the encapsulating layer <NUM>, for any two adjacent second spacing parts <NUM>, the height of the second spacing part <NUM> located downstream is lower than the height of the second spacing part <NUM> located upstream. As such, fillers for the encapsulating layer <NUM> can be better guided to flow from one side of the base substrate <NUM> to the other side of the base substrate <NUM> along the first direction a. In one embodiment, among the plurality of second spacing parts <NUM> located in the same arrangement region <NUM>, in the first direction a, the height of the second spacing parts <NUM> is distributed in a stepped mode.

In one embodiment, as shown in <FIG>, among a plurality of the second spacing parts <NUM> located in the same arrangement region <NUM>, the distance between any two of the adjacent second spacing parts <NUM> is equal. The plurality of the second spacing parts <NUM> is uniformly distributed in the arrangement region <NUM>, thereby, improving uniformity of the pixel define layer and facilitating arrangement uniformity of the pixel grids.

In one embodiment, as shown in <FIG> and <FIG>, the base substrate <NUM> may be a rectangular flat plate. The first spacing part <NUM> may be in a strip shape. The plurality of first spacing part parts <NUM> may extend along the length direction (or width direction) of the base substrate <NUM> and may be arranged in parallel at equal intervals. The length extension direction of any of the first spacing parts <NUM> may be the same as the width direction (or length direction) of the base substrate <NUM> so that a plurality of strip-shaped arrangement regions <NUM> can be defined on the base substrate <NUM>.

Further, in one embodiment as shown in <FIG> and <FIG>, the plurality of second spacing parts <NUM> may be in a strip shape. The length extension direction of the second spacing part <NUM> may be perpendicular to the length extension direction of the arrangement region <NUM>. The plurality of the second spacing parts <NUM> may be distributed at equal intervals on the arrangement region <NUM>. The pixel grids <NUM> may be located in the intervals of either of the two second spacing parts <NUM>. As shown in <FIG> and <FIG>, the pixel grid <NUM> may be rectangular.

The pixel grid <NUM> has two pairs of opposite sides. One pair of opposite sides may be respectively in contact with two adjacent first spacing parts <NUM>. The other pair of opposite sides may be respectively in contact with two adjacent second spacing parts <NUM>. In one embodiment, the thickness of the pixel define layer <NUM> may be greater than or equal to <NUM> micrometers. The thicknesses of the first spacing part <NUM> and the second spacing part <NUM> are greater than or equal to <NUM> micrometers. As such, light emitting elements above the pixel define layer <NUM> can be prevented from contacting the anode below the pixel define layer <NUM>.

A display panel is provided according to one embodiment of the present disclosure. The display panel includes an array substrate and a cover plate. The array substrate may be any one of the array substrates <NUM> according to one embodiment of the present disclosure.

In one embodiment, as shown in <FIG>, the cover plate is stacked on the base substrate <NUM>. An encapsulating layer <NUM> is arranged between the cover plate and the array substrate <NUM>. The side of the substrate <NUM> provided with a pixel define layer <NUM> is opposite to the cover plate. The encapsulating layer <NUM> can be arranged between the array substrate <NUM> and the cover plate so that the array substrate <NUM> is isolated from the cover plate. Fillers for the encapsulating layer <NUM> can have fluidity. Fillers for the encapsulating layer <NUM> can flow to any gap between the array substrate <NUM> and the cover plate. The encapsulating layer <NUM> may have adhesion capability so that the array substrate <NUM> and the cover plate can be packaged together.

In one embodiment of the display panel, the pixel define layer <NUM> is laid on the base substrate <NUM>. A plurality of pixel grids <NUM> are defined by the pixel define layer <NUM>. The pixel define layer <NUM> further comprises a plurality of thickness thinning regions <NUM>. When fillers for the encapsulating layer <NUM> fill the array substrate <NUM>, the thickness thinning regions <NUM> can guide the flow direction of the fillers for the encapsulating layer <NUM>, so that fillers for the encapsulating layer <NUM> can be filled uniformly, thereby preventing fillers for the encapsulating layer <NUM> from being filled excessively or not fully, which causes invalid or poor performance of the display panel.

In one embodiment, as shown in <FIG>, spacers may be disposed on a side of the cover plate facing the array substrate <NUM>. Orthographic projections of the spacers on the array substrate <NUM> do not overlap the thickness thinning regions <NUM>. In another embodiment, the spacers (PS pattern) are disposed toward the first spacing parts <NUM>. The spacers (PS pattern) may be opposite to the first spacing parts <NUM>. Further, the spacer (PS pattern) may be in a circular truncated cone shape. In one embodiment, a surface of a free end of the circular truncated cone may protrude towards the first spacing part <NUM>. As such, a packaging height of the OLED can be easily realized.

In one embodiment, the display panel may be an OLED display panel. The OLED display panel has advantages such as thin, light, wide viewing angle, active light emitting, continuous and adjustable color of emitting light, low cost, fast response speed, low energy consumption, low driving voltage, wide working temperature range, simple production process, high light emitting efficiency, and flexible display and the like.

Another example of the present disclosure is a manufacturing method of the display panel. The manufacturing method includes the following steps. A color filter is formed on the base substrate <NUM>. A pixel define layer <NUM> is then formed on the base substrate <NUM>. The pixel define layer <NUM> defines a plurality of pixel grids <NUM> arranged in an array. The pixel define layer <NUM> further comprises a plurality of thickness thinning regions <NUM>. The thicknesses or heights of the thickness thinning regions <NUM> are smaller than those of other regions of the pixel define layer <NUM>. The thickness thinning regions <NUM> are suitable for guiding fillers for the encapsulating layer <NUM> to flow. A cover plate and the base substrate are arranged in a layered structure. Fillers for the encapsulating layer <NUM> are filled between the cover plate and the array substrate <NUM>.

In the method of manufacturing the display panel according to the embodiment of present disclosure, a pixel define layer <NUM> is laid on the substrate <NUM>. A plurality of pixel grids <NUM> is defined by the pixel define layer <NUM>. The pixel define layer <NUM> further comprises a plurality of thickness thinning regions <NUM>. When fillers for the encapsulating layer <NUM> are filled into the array substrate <NUM>, the thickness thinning regions <NUM> can guide flow direction of the fillers for the encapsulating layer <NUM> so that the fillers for the encapsulating layer <NUM> can be more uniformly filled, thereby preventing fillers for the encapsulating layer <NUM> from being filled excessively or not fully, which causes poor performance of the display panel such as an OLED display panel.

According to one embodiment of the present disclosure, the manufacturing method comprises the following steps: A color filter is formed on the base substrate. A pixel define layer <NUM> is manufactured on the base substrate <NUM>. As shown in <FIG>, an electroluminescence (EL) and a cathode are manufactured on the pixel define layer <NUM>. Separately, a black matrix (BM) pattern, a color film (CF) graph, an optical adhesive (OC) graph, a metal graph, a PS graph and an ITO graph are manufactured on the cover plate. The base substrate <NUM> and the cover plate are then packaged. The ITO pattern on the PS pattern is connected with the cathode to form an auxiliary cathode. Then, fillers for an encapsulating layer <NUM> are filled between the base substrate <NUM> and the cover plate.

In one embodiment, a color filter is laid on the surface of the substrate <NUM>. Then, a pixel define layer <NUM> is laid on the color filter. The pixel define layer <NUM> can define positions of the pixel grids <NUM>. Then, an Electroluminescence (EL) and a cathode are formed on the pixel define layer <NUM>. Separately, a black matrix (BM) pattern and a color film (CF) pattern are manufactured on the cover plate. An Optical Adhesive (OC) pattern is laid on the BM pattern and the CF pattern for encapsulating. Then a metal pattern (metal layer) is manufactured on the surface of OC pattern. Then, a plurality of spacers (PS patterns) is arranged at intervals on the metal pattern (metal layer), and an Indium Tin Oxide (ITO) pattern is formed on the spacer (PS pattern) in a sleeved mode. Finally, the side of the base substrate <NUM> on which the cathode is formed may face the ITO pattern formed on the cover plate so that the cathode may be connected to the ITO. The encapsulating layer <NUM> is then filled in the interval between the array substrate <NUM> and the cover plate.

In one embodiment, the pixel define layer <NUM> may be formed by masking and exposure. In other words, the first spacing part <NUM> and the second spacing part <NUM> can both be formed by masking and exposure. The masking is to mask a processed image by a selected image, pattern or object, partly or in whole, so as to control the area or process of the image processing, thereby improving manufacturing accuracy of the pixel define layer <NUM>.

A display apparatus is provided according to one embodiment of the present disclosure. The display apparatus comprises an array substrate <NUM> according to one embodiment of the present disclosure. In one embodiment, in the display apparatus, the pixel define layer <NUM> is laid on the base substrate <NUM>. A plurality of pixel grids <NUM> is defined by the pixel define layer <NUM>. The pixel define layer <NUM> further comprises a plurality of thickness thinning regions <NUM>. When the encapsulating layer <NUM> is filled into the array substrate <NUM>, the thickness thinning regions <NUM> can guide the flow direction of the fillers for the encapsulating layer <NUM>, so that the fillers for the encapsulating layer <NUM> can be more uniformly filled, thereby preventing fillers for the encapsulating layer <NUM> from being filled excessively or not fully, which causes poor performance of the display panel.

The array substrate <NUM> is described in detail below with reference to <FIG> according to one embodiment of the present disclosure.

As shown in <FIG>, the array substrate <NUM> comprises a base substrate <NUM> and a pixel define layer <NUM>.

In one embodiment, as shown in <FIG>, the base substrate <NUM> may be a rectangular flat plate. The pixel define layer <NUM> can be formed by masking and polishing. The pixel define layer <NUM> may include a plurality of first spacing parts <NUM> and a plurality of second spacing parts <NUM>. The first spacing part <NUM> is in a strip shape. The plurality of the first spacing parts <NUM> may be arranged in parallel along the length direction of the base substrate <NUM> at equal intervals. The length extension direction of any of the first spacing parts <NUM> may be consistent with the width direction of the base substrate <NUM>, so that a plurality of strip-shaped thickness thinning regions <NUM> can be defined on the base substrate <NUM>. The surface of the free end of the first spacing part <NUM> may be an arc-shaped surface. The arc-shaped surface protrudes in a direction away from the base substrate <NUM>. The shape of a cross section of the first spacing part <NUM> cut at any position along the width direction of the base substrate <NUM> is the same.

As shown in <FIG>, the plurality of the second spacing parts <NUM> may be in a strip shape. The length extension direction of the second spacing parts <NUM> may be perpendicular to the length extension direction of the thickness thinning regions <NUM>. The plurality of the second spacing parts <NUM> may be distributed at equal intervals in the thickness thinning regions <NUM>. The surfaces of the free ends of the second spacing parts <NUM> may be arc-shaped surfaces or planes. A plurality of pixel grids <NUM> are arranged in the thickness thinning regions <NUM> and located in intervals between any two second spacing parts <NUM>. The pixel grids <NUM> may be rectangular. The pixel grid <NUM> has two pairs of opposite sides. One pair of opposite sides may be respectively in contact with two adjacent first spacing parts <NUM>, and the other pair of opposite sides may be respectively in contact with two adjacent second spacing parts <NUM>.

The thickness of the area where the pixel grids <NUM> are located is smaller than the thickness of the area where the second spacing parts <NUM> are located. The thickness of the area where the second spacing parts <NUM> are located is smaller than the thickness of the area where the first spacing parts <NUM> are located. The thicknesses of the first spacing parts <NUM> and the thickness of the second spacing parts <NUM> are both greater than <NUM> micrometers. When the array substrate <NUM> is filled with fillers for an encapsulating layer <NUM>, the fillers for the encapsulating layer <NUM> can flow along a plurality of the long strip-shaped thickness thinning regions <NUM>. After the thickness thinning regions <NUM> are fully filled, fillers for the encapsulating layer <NUM> can flow to the first spacing parts <NUM> along the arc surfaces formed by the first spacing parts <NUM>.

The array substrate <NUM> is provided according to one embodiment of the present disclosure. In this embodiment, a pixel define layer <NUM> is laid on the base substrate <NUM>. A plurality of pixel grids <NUM> is defined by the pixel define layer <NUM>. The pixel define layer <NUM> further comprises a plurality of thickness thinning regions <NUM>. When fillers for the encapsulating layer <NUM> are filled into the array substrate <NUM>, the thickness thinning regions <NUM> can guide the flow direction of the fillers for the encapsulating layer <NUM>, so that fillers for the encapsulating layer <NUM> can be more uniformly filled, thereby preventing the encapsulating layer <NUM> from being excessively filled or not fully filled, which will cause poor performance of components on the array substrate such as an OLED or other devices.

Claim 1:
An array substrate comprising:
a base substrate (<NUM>); and
a pixel define layer (<NUM>) on the base substrate, the pixel define layer comprising a plurality of thickness thinning regions (<NUM>),
wherein the thickness thinning regions (<NUM>) have a smaller height than other areas of the pixel define layer (<NUM>) on the base substrate, and the plurality of the thickness thinning regions (<NUM>) are configured to guide flow of fillers to form an encapsulating layer (<NUM>) on the pixel define layer (<NUM>);
the pixel define layer (<NUM>) comprises:
a plurality of first spacing parts (<NUM>); and
a plurality of second spacing parts (<NUM>) intersecting the plurality of the first spacing parts (<NUM>), each of the plurality of the second spacing parts (<NUM>) comprising a plurality of second spacing sub-parts (<NUM>), wherein a height of each of the plurality of the second spacing sub-parts (<NUM>) is smaller than that of each of the plurality of the first spacing parts (<NUM>), and each of the thickness thinning regions (<NUM>) comprises a plurality of the second spacing sub-parts (<NUM>) between two adjacent first spacing parts (<NUM>); each of the plurality of the first spacing parts (<NUM>) has a rectangular strip shape, a length direction of the first spacing parts (<NUM>) is a first direction (a), and the plurality of the first spacing parts (<NUM>) are distributed at intervals in a second direction (b); and
the pixel define layer (<NUM>) defines a plurality of pixel grids (<NUM>) arranged in an array, and at least some of the pixel grids (<NUM>) are located between two adjacent second spacing parts (<NUM>), wherein heights of the plurality of the second spacing sub-parts (<NUM>) in a same thickness thinning region (<NUM>) gradually decrease or increase along the first direction (a).