Patent Description:
There are many different DC-DC converter topologies. The available topologies differ with regard to the components used, the amount of power handled, the input voltage(s), the output voltage(s), efficiency, reliability, size and/or other characteristics. One example DC-DC converter topology is a buck converter. The switching slew rate of a buck converter affects efficiency and input supply voltage ringing. For example, a faster switching slew rate is more efficient, but results in more input supply voltage ringing. In some scenarios, input supply voltage ringing can result in an input supply voltage that exceeds the breakdown voltage for at least one switch of a buck converter. Efforts to improve switching converters are ongoing. <CIT> relates to a system and method for controlling a power switch in a power supply system. <CIT> discloses an adaptive controller for a voltage converter.

The invention is defined by the features of claim <NUM>. The dependent claims recite advantageous embodiments of the invention.

Disclosed herein are switching converter topologies with multiple drive stages and drive modes. The drive stages are coupled to a switch set of the switching converter, where the switch set includes at least one switch and a switch node. With the disclosed switching converter topologies, the switching converter adjusts its operations based on the input supply voltage. For example, if the input supply voltage is less than a threshold level, two of two drive stages are used to provide a drive signal to the switch set of a switching converter (e.g., to drive a high-side switch or a low-side switch). When two of two drive stages are used to provide a drive signal to the switch set, the switching slew rate is increased, which increases the efficiency of the switching converter and increases input supply voltage ringing. Because the input supply voltage is less than the threshold level, such ringing will not exceed a maximum voltage target (e.g., a breakdown voltage of at least one transistor of a switching converter). On the other hand, if the input supply voltage is greater than or equal to the threshold level, only one of two drive stages are used to provide a drive signal to the switch set of a switching converter (e.g., to drive a high-side switch or a low-side switch). When only one of two drive stages are used to provide a drive signal to the switch set, the switching slew rate is decreased, which decreases the efficiency of the switching converter and decreases input supply voltage ringing. Because the input supply voltage is greater than or equal to the threshold level, such ringing should be minimized to avoid exceeding a maximum voltage target (e.g., a breakdown voltage of at least one transistor of a switching converter).

In some examples, a switching converter includes a controller that supports multiple modes, where the modes are selected based on the output of an input supply voltage detector. For example, if the output of the input supply voltage detector indicates the input supply voltage for the switching converter is greater than or equal to the threshold level, the controller is configured to select a first drive mode that uses only one of a first drive stage and a second drive stage to provide a drive signal to the switch set. On the other hand, if the output of the input supply voltage detector indicates the input supply voltage for the switching converter is less than the threshold level, the controller is configured to select a second drive mode that uses both of the first drive stage and the second drive stage to provide a drive signal to the switch set. In some examples, the controller includes the supply voltage detector circuit and a level shifter, where the level shifter is coupled between the supply voltage detector circuit and the second drive stage.

In some examples, the first drive stage is configured to provide a first drive signal contribution to the switch set and the second drive stage is configured to provide a second drive signal contribution to the switch set, where the second drive signal contribution is larger than the first drive signal contribution. As desired, the controller may support additional modes (e.g., only the first drive stage is used, only the second drive stage is used, both the first and the second drive stages are used). Also, in some examples, more than two drive stages are possible. With the switching converter topologies described herein, switching converter efficiency and ringing management are performed based on an input supply voltage detector and related thresholds. To provide a better understanding, various switching converter options and current monitor circuit options are described using the figures as follows.

<FIG> is a block diagram showing a system <NUM> in accordance with some examples. The system <NUM> represents an integrated circuit (IC), a multi-die module (MDM), discrete components, or combinations thereof. In some examples, an IC, MDM, and/or discrete components are coupled together using a printed circuit board (PCB). As shown, the system <NUM> includes a switching converter device <NUM> with a plurality of drive stages 108A-108N coupled to a switch set <NUM>. The switch set <NUM> includes one or more switches and a switch node. In one example, the drive stages 108A-108N are coupled to a high-side switch of the switch set <NUM>, where each of the drive stages 108A-108N is configured to provide a respective drive signal contribution to the high-side switch. In another example, the drive stages 108A-108N are coupled to a low-side switch of the switch set <NUM>, where each of the drive stages 108A-108N is configured to provide a respective drive signal contribution to the high-side switch. In some examples, each drive signal contribution is equal to each other (e.g., <NUM>% contribution for two drive signals, <NUM>% contribution for four drive signals, etc.). In other examples, each drive signal contribution is different from each other (e.g., <NUM>% and <NUM>% contributions for two drive signals, etc.). In some examples, some of the drive stages 108A-108A are coupled to a high-side switch of the switch set <NUM>, while others of the drive stages 108A are coupled to a low-side switch of the switch set <NUM>.

In the example of <FIG>, the drive stages 108A-108N are coupled to a controller <NUM>. The controller <NUM> directs the drive stages 108A-108N based on the input supply voltage for the switch converter <NUM>. As shown, the controller <NUM> includes an input supply voltage detector <NUM> configured to detect the input supply voltage level. In some examples, the input supply voltage detector <NUM> uses one or more comparators and thresholds to perform input supply voltage detection. In other examples, the input supply voltage detector <NUM> is configured to measure the input supply voltage. Regardless of the particular input supply voltage detection mechanism that is used, the input supply voltage detector <NUM> is configured to provide a detection signal (DS) that indicates the input supply voltage level.

In some examples, the controller <NUM> also includes a level shifter <NUM> configured to receive the detection signal from the input supply voltage detector <NUM>. The level shifter <NUM> adjusts the detection signal to another voltage domain to enable the controller <NUM> to enable or disable at least one of the drive stages 108A-108N. In the example of <FIG>, the controller <NUM> also includes selection logic <NUM> configured to select one of multiple modes. In some examples, the modes are selected based on the detection signal output from the input supply voltage detector <NUM>. For example, if the detection signal indicates the input supply voltage for the switching converter <NUM> is greater than or equal to a threshold level, the controller <NUM> is configured to select a first drive mode that uses only one (or only a subset) of the drive stages 108A-108N to provide a drive signal to the switch set <NUM>. On the other hand, if the detection signal from the input supply voltage detector <NUM> indicates the input supply voltage for the switching converter <NUM> is less than the threshold level, the controller <NUM> is configured to select a second drive mode that uses more (or all) the drive stages 108A-108N (compared to the first drive mode) to provide a drive signal to the switch set.

In one example, there are two drive stages. When the input supply voltage is greater than or equal to a threshold level, the detection signal output from the input supply voltage detector <NUM> is low. In response, the level shifter <NUM> is not used and the controller <NUM> directs a first of the two drive stages to provide a drive signal to the switch set <NUM>. When the input supply voltage is less than the threshold level, the detection signal output from the input supply voltage detector <NUM> is higher. In response, the level shifter <NUM> changes the voltage domain of the detection signal, resulting in the controller <NUM> directing both of the two drive stages to provide a drive signal to the switch set <NUM>.

In a buck converter example, the switch set <NUM> includes a high-switch switch and a low-side switch coupled in series between an input supply voltage node and a ground node. In this example, a node between the high-side switch and the low-side switch corresponds to a switch node or output inductor node, which is coupled to an output inductor (e.g., one of the output components <NUM> for the system <NUM>). In this example, the output components <NUM> also include an output capacitor, where charge stored by the output capacitor is provided to a load <NUM>. In some examples, the controller <NUM> uses different modes to direct the drive stages 108A-108N to provide a drive signal to a high-side switch based on an input supply voltage level. In other examples, the controller <NUM> uses different modes to direct the drive stages 108A-108N to provide a drive signal to a low-side switch based on an input supply voltage level. In some examples, a first set of drive stages are used to provide a drive signal to a high-side switch based on an input supply voltage level, and a second set of drive stages are used to provide a drive signal to a low-side switch based on an input supply voltage level.

<FIG> is a chart <NUM> showing input supply voltages for a switching converter (e.g., the switching converter <NUM> in <FIG>) and related modes in accordance with some examples. As shown, the chart <NUM> represents a voltage range from approximately 11V to 21V with different modes assigned to different portions of the represented voltage range. More specifically, the different modes include a maximize efficiency mode <NUM>, an intermediate mode <NUM>, and a minimize ring mode <NUM>. In the example of <FIG>, the maximum efficiency mode <NUM> corresponds to 11V-15V, the intermediate node <NUM> corresponds to 15V-17V, and the minimize ring mode <NUM> corresponds to 17V-21V. Also, example values for a customer input supply voltage <NUM> (e.g., 12V), a maximum recommended input supply voltage (e.g., 17V) <NUM>, an absolute maximum input supply voltage (e.g., 19V) <NUM>, and a design target input supply voltage (e.g., 21V) <NUM> are represented. In other examples, the voltages assigned to the maximize efficiency mode <NUM>, the intermediate mode <NUM>, and the minimize ring mode <NUM> may vary from the example of <FIG>. Also, the customer input supply voltage <NUM>, the maximum recommended input supply voltage <NUM>, the absolute maximum input supply voltage <NUM>, and the design target input supply voltage <NUM> may vary.

<FIG> are timing diagrams showing switching node voltage waveforms in accordance with some examples. In the timing diagram <NUM> of <FIG>, a switch node voltage waveform <NUM> is represented. As shown, the switch node voltage waveform <NUM> shows a falling edge scenario, where the switch node voltage drops from a high level <NUM> to a low level <NUM>. In the example of <FIG>, the slew rate of the falling edge is measured as the change in voltage / change in time (dv/dt) from points <NUM> to <NUM>. The switch node voltage waveform <NUM> also shows that the switch node voltage reaches a minimum value <NUM> with an offset <NUM> between the minimum value <NUM> and the low level <NUM>. In the example of <FIG>, the slew rate for the switch node voltage is approximately 3V/ns. Such a slew rate reduces ringing issues, buts results in inefficient switching operations (more switching losses compared to faster slew rates).

In the timing diagram <NUM> of <FIG>, another switch node voltage waveform <NUM> is represented. As shown, the switch node voltage waveform <NUM> shows a falling edge scenario, where the switch node voltage drops from a high level <NUM> to a low level <NUM>. In the example of <FIG>, the slew rate of the falling edge is measured as the change in voltage / change in time (dv/dt) from points <NUM> to <NUM>. The switch node voltage waveform <NUM> also shows that the switch node voltage reaches a minimum value <NUM> with an offset <NUM> between the minimum value <NUM> and the low level <NUM>. In the example of <FIG>, the slew rate for the switch node voltage is approximately 10V/ns. Such a slew rate is more efficient (compared to the slew rate of the switch node voltage waveform <NUM>), but increases ringing issues. In other words, the offset <NUM> represented in <FIG> is larger than the offset <NUM> represented in <FIG>. Depending on the input supply voltage level relative to the breakdown voltage of components used for a switching converter (e.g., the switching converter <NUM> in <FIG>), different offsets are permissible (the input supply voltage plus the offset should not extend beyond the breakdown voltage of switching converter components).

<FIG> is a schematic diagram showing a system <NUM> in accordance with some examples. As shown, the system <NUM> includes a switching converter <NUM> (an example of the switching converter <NUM> in <FIG>) with a switch set <NUM> (an example of the switch set <NUM> in <FIG>), drive stages <NUM> and <NUM> (examples of the drive stages 108A-108N in <FIG>), selection logic <NUM> (an example of the selection logic <NUM> in <FIG>), a level shifter <NUM> (an example of the level shifter <NUM> in <FIG>), and an input supply voltage detector <NUM> (an example of the input supply voltage detector <NUM> in FIG.

As shown, the switch set <NUM> includes a high-side switch (M2) and a low-side switch (M3). Between M2 and M3 is a switch node <NUM>. In the example of <FIG>, M2 includes a control terminal coupled to a first drive stage <NUM> and a second drive stage <NUM>. The first current terminal of M2 is coupled to an input supply node <NUM> via a first inductor (L1), and the second current terminal of M2 and the first current terminal of M3 are coupled to the switch node <NUM>. Also, the control terminal of M3 is coupled to a low-side drive signal (XDRVL) node <NUM> via buffers <NUM>. The second current terminal of M3 is coupled to a ground node <NUM> via a second inductor (L2). In the example of <FIG>, L1 and L2 represent parasitic inductance (e.g., from a printed circuit board or "PCB"), which is a consideration for driver design.

As shown, the switch node <NUM> is also coupled to a first end of an output inductor (LOUT). The second end of LOUT is coupled to an output node <NUM>. As shown, the output node <NUM> is also coupled to a first terminal of an output capacitor (COUT). The second terminal of COUT is coupled to the ground node <NUM>. In the example of <FIG>, a load <NUM> is coupled between the output node <NUM> and the ground node <NUM>, where the load <NUM> is powered by the output voltage (VOUT) at the output node <NUM>. Comparing <FIG> and <FIG>, LOUT and COUT in <FIG> are examples of the output components <NUM>, and the load <NUM> in <FIG> is an example of the load <NUM> in <FIG>.

In operation, the first drive stage <NUM> is configured to provide a first drive signal <NUM> to the control terminal of M2 (the high-side switch) in response to a high-side drive signal (XDRVH) from node <NUM>. More specifically, the first drive stage <NUM> includes two transistors, MP1 and MN1, having their control terminals coupled to the node <NUM> via respective buffers <NUM> and <NUM>. Also, the first current terminal of MP1 is coupled to an input supply (BST) node <NUM>. In some examples, BST is a power supply which is about 5V higher than the switching node <NUM>. In one example, the voltage level for BST is obtained by placing a capacitor (C1) between the BST node <NUM> and the switch node <NUM>. More specifically, a first (e.g., top) plate of C1 is coupled to the BST node <NUM> and a second (e.g., bottom) plate of C1 is coupled to the switch node <NUM>.

The second current terminal of MP1 is coupled to the first current terminal of MN1, and the second current terminal of MN1 is coupled to the switch node <NUM>. In response to VOUT dropping below a threshold or another trigger, XDRVH transitions from high-to-low, which causes MP1 and MN1 to provide the first drive signal <NUM> to turn M2 on (increasing VOUT). Once VOUT reaches a threshold value or another trigger, XDRVH transitions from low-to-high, which causes MP1 and MN1 to stop providing the first drive signal <NUM>, which results in M2 being turned off. In some examples, the first drive stage <NUM> is used in multiple drive modes.

In operation, the second drive stage <NUM> is configured to provide a second drive signal <NUM> to the control terminal of M2 (the high-side switch) in response to an indication from the input supply voltage detector <NUM> that the input supply voltage is less than a threshold value. More specifically, the input supply voltage detector <NUM> includes a voltage divider with R1 and R2 in series between an input voltage supply (PVIN) node <NUM> and a ground (PGND) node <NUM>. The value at the node <NUM> between R1 and R2 is provided to one of the input nodes of a comparator <NUM>. The other input node of the comparator <NUM> receives a reference voltage (VBG). In some examples, PVIN = N*VGB and R1 = (N-<NUM>)*R2. When the voltage at node <NUM> is greater than or equal to VBG, the output of the comparator <NUM> is low (when VIN is high, the output of the comparator <NUM> is high), resulting in the second drive stage <NUM> not being used when XDRVH is low (e.g., only the first drive stage <NUM> is used when the input supply voltage is greater than a threshold). On the other hand, when the voltage at node <NUM> is less than VBG, the output of the comparator <NUM> is low, resulting in the second drive stage <NUM> being used when XDRVH is low (XDRVH high results in M2 being turned off and XDRVH low results in M2 being turned on) (e.g., both the first drive stage <NUM> and the second drive stage <NUM> are used when the input supply voltage is less than a threshold).

As shown, the output of the comparator <NUM> provides a control signal to the level shifter <NUM>, which includes R3, M1, and R4 between a BST node <NUM> and the ground node <NUM>. Also, the control terminal of M1 is coupled to the output of the comparator <NUM>, the first current terminal of M1 is coupled to R3, and the second current terminal of M1 is coupled to R4. More specifically, a first end of R3 is coupled to the BST node <NUM> and a second end of R3 is coupled to the first current terminal of M1. Meanwhile, the first end of R4 is coupled to the second current terminal of M1, while the second end of R4 is coupled to the ground node <NUM>. In the example of <FIG>, component <NUM> (e.g., a Schmitt comparator) adjusts the voltage level at the second end of R3 to another voltage level.

As shown, the output of the component <NUM> is provided to selection logic <NUM>. In the example of <FIG>, the selection logic <NUM> includes an OR gate <NUM>, an inverter <NUM>, and a AND gate <NUM>. More specifically, the output of the component <NUM> is provided to an input node of the OR gate <NUM>, where the output node of the OR gate is coupled to the control terminal of MP2. The other input node of the OR gate <NUM> is coupled to the high-side drive signal node <NUM>. The output of the component <NUM> is also an input to the inverter <NUM>. The output of the inverter <NUM> is coupled to an input node of the AND gate <NUM>. The other input node of the AND gate <NUM> is coupled to the high-side drive signal node <NUM>. The output node of the AND gate <NUM> is coupled to the control terminal of MN2. In the first drive mode, only the first drive state <NUM> is used. In some examples, the control of MP1 and MN1 in the first drive mode is a function of XDRVH. More specifically, when XDRVH is low in the first drive mode, MN1 turns off, MP1 turns on, and M2 is turned on. In contrast, when XDRVH is high in the first drive mode, MN1 turns on, MP1 turns off, M2 is turned off. In the second drive mode, both the first drive stage <NUM> and the second drive stage <NUM> are used. In some examples, the control of MP1, MN1, MP2, and MN2 in the second drive mode is a function of XDRVH. More specifically, when XDRVH is low in the second drive mode, MP1 and M2 are turned on. If the output of component <NUM> is low (indicating VIN is lower than a threshold), MP2 will also turn on (causing M2 to turn on faster). On the other hand, if the output of component <NUM> is high (indicating VIN is higher than the threshold), MP2 will not be turned on. Also, when XDRVH is high in the second drive mode, MN1 is turned on, and M2 is turned off. If the output of component <NUM> is low (indicating VIN is lower than the threshold), MN2 will also turn on (causing M2 turn off faster). In contrast, if the output of component <NUM> is high (indicating VIN is higher than the threshold), MN2 will not turn on.

In the example of <FIG>, the operations of the switching converter <NUM> are adjusted based on the input supply voltage. If the input supply voltage is less than a threshold level (detected by the input supply voltage detector <NUM>), both of the first and second drive stages <NUM> and <NUM> are used to provide a drive signal to M2. When both of the first and second drive stages <NUM> and <NUM> are used to provide a drive signal to M2, the switching slew rate is increased, which increases the efficiency of the switching converter <NUM> and increases input supply voltage ringing. Because the input supply voltage is less than the threshold level, such ringing will not exceed a maximum voltage target (e.g., a breakdown voltage of at least one transistor of the switching converter <NUM>). On the other hand, if the input supply voltage is greater than or equal to the threshold level, only the first drive stage <NUM> is used to provide a drive signal to M2. When only the first drive stage <NUM> is used to provide a drive signal to M2, the switching slew rate is decreased, which decreases the efficiency of the switching converter <NUM> and also decreases input supply voltage ringing. Because the input supply voltage is greater than or equal to the threshold level, such ringing should be minimized to avoid exceeding a maximum voltage target (e.g., a breakdown voltage of at least one transistor of the switching converter <NUM>).

In some examples, the input supply voltage detector <NUM>, the level shifter <NUM>, and the selection logic <NUM> of <FIG> are an example of a signal path coupled to the first drive stage <NUM> and the second drive stage <NUM>, where the signal path is configured to selectively trigger a first drive mode and a second drive mode. In the first drive mode, either the first drive stage or the second drive stage is selected to provide a drive signal (e.g., to M2 in <FIG>). In the second drive mode, both the first drive stage and the second drive stage are selected to provide a drive signal (e.g., to M2).

<FIG> is a timing diagram <NUM> showing input supply voltage waveforms and switching node voltage waveforms in accordance with some examples. In the timing diagram <NUM>, various input supply voltage waveforms <NUM>, <NUM>, and <NUM> are represented. The input supply voltage waveform <NUM> has a base value of around 21V and a maximum value of around 25V at time <NUM> due to ringing. The input supply voltage waveform <NUM> has a base value of around 17V and a maximum value of around 24V at time <NUM> due to ringing. The input supply voltage waveform <NUM> has a base value of around 17V and a maximum value of around 21V at time <NUM> due to ringing.

In the timing diagram <NUM>, various switch node voltage waveforms <NUM>, <NUM>, <NUM> are also represented. The switch node voltage waveform <NUM> corresponds to the input supply voltage waveform <NUM>. As shown, the switch node voltage for the switch node voltage waveform <NUM> starts at around 21V before being reduced to approximately 0V, where the transition from 21V to 0V mostly occurs during a falling edge interval <NUM> corresponding to the ringing in the input supply voltage waveform <NUM>. The switch node voltage waveform <NUM> corresponds to the input supply voltage waveform <NUM>. As shown, the switch node voltage for the switch node voltage waveform <NUM> starts at around 17V before being reduced to approximately 0V, where the transition from 17V to 0V mostly occurs during a falling edge interval <NUM> corresponding to the ringing in the input supply voltage waveform <NUM>.

The switch node voltage waveform <NUM> corresponds to the input supply voltage waveform <NUM>. As shown, the switch node voltage for the switch node voltage waveform <NUM> starts at around 17V before being reduced to approximately 0V, where the transition from 17V to 0V mostly occurs during a falling edge interval <NUM> corresponding to the ringing in the input supply voltage waveform <NUM>. As shown, the falling edge interval <NUM> is smaller than the falling edge intervals <NUM> and <NUM>, which indicates that the slew rate and related efficiency for the switch node voltage waveform <NUM> is higher than the respective slew rates of the switch node voltage waveforms <NUM> and <NUM>. In the timing diagram <NUM>, the input supply voltage waveform <NUM> and the switch node voltage waveform <NUM> represent a scenario where the input supply voltage is determined to be less than a threshold level. In response, multiple drive stages are used to drive a switching converter switch to increase efficiency when there is a voltage budget available for ringing as described herein.

<FIG> is a timing diagram <NUM> showing drive stage control signals corresponding to various waveform represented in <FIG> in accordance with some examples. As shown, the timing diagram <NUM> includes a set of waveforms <NUM> corresponding to the on/off state of MP1 and MN1, where the set of waveforms <NUM> results in the falling edge interval <NUM> represented in <FIG>. The timing diagram <NUM> also includes a set of waveforms <NUM> corresponding to on/off states for MP1 and MN1, where the set of waveforms <NUM> results in the falling edge interval <NUM> represented in <FIG>. In some examples, the control signals for MP2 and MN2 are is an off state during the falling edge intervals <NUM> and <NUM>. The timing diagram <NUM> also includes a set of waveforms <NUM> corresponding to the on/off states for MP1, MP2, MN1, and MN2, where the set of waveforms <NUM> results in the falling edge interval <NUM> represented in <FIG>.

<FIG> are charts <NUM> and <NUM> showing maximum differential voltage values as a function of input supply voltages in accordance with some examples. In the chart <NUM> of <FIG>, line <NUM> corresponds to a previous drive strategy, where PVIN-PGND increases linearly as VIN increases. As used herein, PVIN and PGND include the ringing on this node (PVIN - PGND = VIN (dc) + VIN (ringing) + GND (ringing)). Meanwhile, line <NUM> in the chart <NUM> corresponds to a new drive strategy, where PVIN-PGND for line <NUM> is higher than PVIN-PGND for line <NUM>. As shown, line <NUM> increases linearly as VIN increases up to a predetermined threshold VIN (e.g., 17V in the example of <FIG>). Above the threshold VIN, line <NUM> dips lower such that PVIN-PGND for the line <NUM> matches PVIN-PGND for the line <NUM> at VIN values of 18V or more. In the example of <FIG>, line <NUM> corresponds to a 2x value, which indicates the second stage driver is equal in strength to the first stage driver. In some examples, equal strength refers to having the same channel width, such that when both stage drivers are on, the channel width is doubled, Thus, when VIN is below the threshold, both the first and second stage drivers turn on, resulting in the line <NUM> being a 2x value relative to the line <NUM>.

In the chart <NUM> of <FIG>, line <NUM> corresponds to a previous drive strategy, where PVIN-PGND increases linearly as VIN increases. Meanwhile, line <NUM> in the chart <NUM> corresponds to a new drive strategy, where PVIN-PGND for line <NUM> is higher than PVIN-PGND for line <NUM>. As shown, line <NUM> increases linearly as VIN increases up to a predetermined threshold VIN (e.g., 17V in the example of <FIG>). Above the threshold VIN, line <NUM> dips lower such that PVIN-PGND for the line <NUM> matches PVIN-PGND for the line <NUM> at VIN valued of 18V or more. In the example of <FIG>, line <NUM> corresponds to a 4x value, which indicates the second stage driver is <NUM> times the strength to the first stage driver. Thus, when VIN is below the threshold, both the first and second stage drivers turn on, resulting in the line <NUM> being a 4x value relative to the line <NUM>.

<FIG> is a chart <NUM> showing efficiency as a function of loading in accordance with some examples. In chart <NUM>, line <NUM> corresponds to an existing drive strategy, where efficiency reaches around <NUM>% before dropping as a function of loading to around <NUM>%. Meanwhile, line <NUM> corresponds to a new drive strategy, where efficiency reaches around <NUM>% before dropping as a function of loading to around <NUM>%. For the chart <NUM>, assumed values includes VIN=12V, VOUT = 1V, and L= 1µH.

<FIG> is a flowchart showing a switching converter control method <NUM> in accordance with some examples. As shown, the method <NUM> includes monitoring VIN at block <NUM>. If VIN is greater than or equal to a threshold level (determination block <NUM>), one of two drive stages (e.g., the first drive stage <NUM> in <FIG>) is used to provide a drive signal at block <NUM>. On the other hand, if VIN is not greater than or equal to the threshold level (determination block <NUM>), two of two drive stages (e.g., the first and second drive stages <NUM> and <NUM> in <FIG>) are used to provide a drive signal at block <NUM>. In some examples, the method <NUM> is used to control the high-side switch of a switching converter (as in the example switch converter <NUM> of <FIG>). In other examples, the method <NUM> is used to control the low-side switch of a switching converter.

In some examples, one or more of the disclosed switching converters (e.g., the switching converter <NUM> of <FIG>, or the switching converter <NUM> of <FIG>) is used in a battery-operated device, such as a laptop or tablet. As an example, a switching converter may be used in a battery-operated device, where VIN for the switching converter is provided by the battery or an AC/DC adapter. The switching converter reduces VIN to VOUT (e.g., a VIN of 6V or more, and a VOUT of <NUM>. 3V or 5V) for use in powering electronic components of the battery-operated device.

The term "couple" is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

Claim 1:
A system, comprising:
a switching converter (<NUM>), configured to receive an input supply voltage (Vin) and provide an output voltage (Vout) for powering a load (<NUM>), with:
an output inductor;
a switch set (<NUM>) with a switch node coupled to the output inductor;
a first drive stage (<NUM>) coupled to the switch set (<NUM>);
a second drive stage (<NUM>) coupled to the switch set (<NUM>); and
a controller (<NUM>) coupled to the second drive stage (<NUM>), wherein the controller (<NUM>) comprises:
a supply voltage detector circuit (<NUM>);
a level shifter (<NUM>)
coupled to an output of the supply voltage detector circuit (<NUM>); and
a selection circuit (<NUM>) coupled between the level shifter and the second drive stage (<NUM>); wherein the controller (<NUM>) is configured to select one of a first drive mode that enables only the first drive stage (<NUM>)
if the input supply voltage (Vin) is greater than or equal to a threshold level; and a second drive mode that enables both the first and second drive stages (<NUM>) if the input supply voltage is less than a threshold level to increase the switching slew-rate.