Patent Description:
Since the split-gate device structure was put forward, due to the advantages of the split-gate structure with low resistance and low gate capacitance etc., there is a trend that the products of medium and low voltage ordinary trench type VDMOS (vertical double diffused metal oxide semiconductor field-effect transistor) are gradually replaced by the trench split-gate VDMOS devices.

At present, after a thin oxide layer is grown using thermal oxidation method or thermal oxidation, the lower part of the oxide layer in the trench can be realized by growing an oxide layer on the surface of the thin oxide layer using furnace tube oxidation method or deposition method. With the oxide layer grown by the above methods, the thickness of the oxide layer at the bottom of the trench is usually thinner than that of the oxide layer on the side wall of the trench. With the increase of the thickness of the oxide layer at the bottom of the trench and the increase of the depth of the trench, the ratio of the thickness of the oxide layer at the bottom and the thickness of the oxide layer on the side wall of the trench trends to decrease. When a reverse voltage is applied across the source end and drain end of VDMOS, a thicker oxide layer at the bottom of the trench is required to adapt to withstand voltage. Because the thickness of the oxide layer at the bottom of the trench is less than that of the oxide layer on the side wall oxide layer of the trench, the oxidation process is increased in order to achieve a thicker oxide layer at the bottom of the trench, which causes the thickness of the oxide layer on the side wall of the trench is thicker and a wider trench is required to adapt to the thicker oxide layer on the side wall of the trench. Accordingly, the area of chip is larger and the specific on resistance is higher.

<CIT> describes a semiconductor device which including: a first semiconductor region; a second semiconductor region selectively provided on the first semiconductor region; a third semiconductor region selectively provided on the second semiconductor region; a first electrode provided on the third semiconductor region and connected to the third semiconductor region; a second electrode electrically connected to the first semiconductor region; a third electrode provide via an insulating film on the first semiconductor region, the second semiconductor region, and the third semiconductor region; and a fourth electrode provided on the second electrode side of the third electrode, the fourth electrode being provided via the insulating film on the first semiconductor region. The insulating film has three or more regions between the fourth electrode and the first semiconductor region. Width of each of the regions in a direction crossing a direction from the third electrode toward the second electrode is different.

<CIT> describes a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a first electrode surrounded by the first semiconductor region and including a first electrode portion and a second electrode portion provided on the first electrode portion, and a first insulating section including first and second insulating portions. The second insulating portion is arranged side by side with the second electrode portion in a second direction perpendicular to a first direction from the first semiconductor region to the second semiconductor region. The first insulating portion is arranged side by side with the first electrode portion in the second direction. A length and a thickness of the first insulating portion in the first direction are greater than a length and a thickness of the second insulating portion in the first direction, respectively.

According to various embodiments of the present disclosure, a trench split-gate device and a method for manufacturing the same are provided.

According to one aspect of the present disclosure, a method for manufacturing a trench split-gate device is provided, which comprises: etching a semiconductor substrate to form a trench; depositing oxide in the trench to form a floating gate oxide layer, in which the floating gate oxide layer is gradually thickened from top to bottom along a side wall of the trench, and a thickness of the floating gate oxide layer at a lower part of the side wall of the trench is the same as that of the floating gate oxide layer at a bottom of the trench; depositing polysilicon into the trench to form a floating gate polycrystalline layer; growing an insulating medium on an upper surface of the floating gate polycrystalline layer to form an isolation layer; and forming a control gate on the isolation layer in the trench.

According to another aspect of the present disclosure, a trench split-gate device is provided, which includes: a semiconductor substrate in which a trench is provided; a floating gate oxide layer provided on an inner wall of the trench, a thickness of the floating gate oxide layer being gradually increased along the side wall of the trench to a bottom of the trench, and the thickness of the floating gate oxide layer at a lower part of the side wall of the trench being the same as that of the floating gate oxide layer at the bottom of the trench; a floating gate polycrystalline layer provided on a surface of the floating gate oxide layer; an isolation layer provided on the floating gate polycrystalline layer, and a control gate provided on the isolation layer to control the on and off of the device.

In order to better describe and explain the embodiments or examples of those applications disclosed herein, reference can be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered to limit the scope of any of the disclosed inventions, the embodiments and/or examples currently described, and the best model of these applications as currently understood.

As shown in <FIG>, a method for manufacturing a trench split-gate device is provided by the present disclosure, which comprises the following steps:.

In the above method for manufacturing a trench split-gate device, a gradually changing floating gate oxide layer is grown on the trench side wall, in order that the thickness of the floating gate oxide layer is gradually increased from the isolation layer position to the bottom position of the trench and the thickness of the floating gate oxide layer at the lower part of the side wall of the trench is the same as that of the floating gate oxide layer at the bottom of the trench. The thickness of the floating gate oxide gradually changing can reduce the width of the trench and further reduce the cell area and the specific on resistance of the device. In addition, the thickness of the floating gate oxide layer is gradually increased from the side wall of the trench, and the thickness of the floating gate oxide at the lower part of the side wall of the trench is the same as that at the bottom of the trench. Said floating gate oxide layer also adapts to the continually increasing voltage from the control gate to the bottom of the trench, such that the device will not be broken down due to a non-adaptive voltage.

In one of embodiments, etching the semiconductor substrate to form a trench specifically comprises: etching the semiconductor substrate vertically to make the side wall of the trench vertical up and down. The step of depositing an oxide into the trench to form a floating gate oxide layer comprises: forming a first oxide layer on the inner surface of the trench; forming a second oxide layer on the first oxide layer using high density plasma chemical vapor deposition process in which the thickness of the second oxide layer is controlled to gradually increase from top to bottom along the trench side wall and the thickness of the second oxide layer at the lower part of the side wall of the trench is the same as that of the second oxide layer at the bottom of the trench. In the example, by controlling the pressure of the reaction chamber and the flow rate of the reaction gas flowing into the reaction chamber, the thickness of the second oxide layer along the side wall of the trench can be controlled to gradually increase.

Specifically, referring to <FIG>, the method for manufacturing the trench split-gate device according to the embodiment specifically comprises the following steps:
At S200: a semiconductor substrate is etched to form a trench.

A semiconductor substrate is a kind of semiconductor material, which provides mechanical supports and electrical properties for manufacturing a transistor and an integrated circuit. In the present embodiment, the semiconductor substrate can include semiconductor elements such as monocrystal, polycrystalline, or amorphous silicon or germanium, and can also include a mixed semiconductor structure such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof.

Specifically, referring to <FIG>, the semiconductor substrate includes a highly doped bulk layer <NUM> and a lightly doped epitaxial layer <NUM>. The doping types of the bulk layer <NUM> and the epitaxial layer <NUM> are the same, which can be N-type impurity. In this disclosure, the epitaxial layer <NUM> is etched vertically from top to bottom using dry etching process in order that the side wall of the trench <NUM> formed by etching is vertical up and down.

At S210: a first oxide layer is formed on the inner surface of the trench.

In the embodiment, a first oxide layer can be formed on the inner surface of the trench using the furnace tube oxidation method, and the first oxide layer can be silicon oxide.

Specifically, the semiconductor substrate can be placed in a certain gas atmosphere and a certain temperature range to have the semiconductor substrate react with oxygen or water vapor to generate silicon dioxide during the preparation. The gas atmosphere refers to nitrogen and/or oxygen and/or hydrogen, and the temperature range is from about <NUM> raised to about <NUM> and then back to about <NUM>. As shown in <FIG>, in the embodiment, the thickness of the first oxide layer <NUM> in the trench <NUM> is the same everywhere.

At S220: a second oxide layer is formed on the first oxide layer using high density plasma chemical vapor deposition process. By controlling the pressure of the reaction chamber and the flow rate of the reaction gas flowing into the reaction chamber, the thickness of the second oxide layer is gradually increased from top to bottom along the side wall of the trench, and the thickness of the second oxide layer at the lower part of the side wall of the trench is the same as that of the second oxide layer at the bottom of the trench.

As shown in <FIG>, after the preparation of the first oxide layer <NUM> is completed, a second oxide layer <NUM> is deposited on the surface of the first oxide layer <NUM> at the bottom of the trench <NUM> using high density plasma chemical vapor deposition (HDP CVD) process, in which the second oxide layer <NUM> can be silicon oxide. During the preparation, silane, oxygen, hydrogen, helium and the like reaction gases flow into the reaction chamber. During the deposition process, by controlling the pressure of the reaction chamber and the flow rate of the reaction gas flowing into the reaction chamber, the amount of silicon dioxide attached to the side wall and the bottom of the trench <NUM> generated by the reaction is controlled. Firstly, a certain amount of reaction gas flows into the reaction chamber under a certain pressure. The reaction gas reaches the bottom of the trench <NUM> under the pressure of the cavity, and reacts at the bottom of the trench <NUM> to generate oxidation products with thicker thickness. Then, the pressure is reduced at regular intervals and the flow rate of the reaction gas flowing into the reaction chamber is reduced. At a lower pressure, the reaction gas is gradually raised and a deposition reaction is taken place on the side wall of the trench <NUM> to generate oxidation products with thinner thickness. Further, the thickness of the second oxide layer <NUM> deposited on the side wall of the trench <NUM> is gradually reduced from bottom to up. The thickness of the second oxide layer <NUM> at the lower part of the side wall of the trench <NUM> is the same as that of the second oxide layer <NUM> deposited at the bottom the trench <NUM>. Therefore, the thickness of the floating gate oxide constituted of the first oxide layer <NUM> and the second oxide layer <NUM> is gradually increased from top to bottom along the side wall of the trench, and the thickness of the floating gate oxide layer at the lower part of the side wall of the trench is the same as that of the floating gate oxide layer at the bottom of the trench. In the present embodiment, the flow rate of the reaction gas can be <NUM>% - <NUM>% for silane, <NUM>% - <NUM>% for oxygen, <NUM>% - <NUM>% for hydrogen and <NUM>% - <NUM>% for helium.

Compared with the ordinary atmospheric pressure chemical vapor deposition method, the thickness of the second oxide layer <NUM> formed by the deposition can be controlled by the HDP CVD process used in the embodiment of present disclosure, such that the thickness of the second oxide layer <NUM> deposited on the side wall of the trench <NUM> is gradually increased from the top to the bottom, and the thickness of the second oxide layer <NUM> at the bottom of the trench <NUM> is the same as that of the second oxide layer <NUM> at the lower part of the side wall of the trench <NUM>. On the one hand, increasing the thickness of the floating gate oxide at the bottom of the trench can make the device adapt to withstand voltage and avoid the device to be broken down by high voltage. On the other hand, under the condition that the thickness of the floating gate oxide at the bottom of the trench is the same, the floating gate oxide layer on the side wall of the trench in the present disclosure is thinner than the floating gate oxide layer on the side wall of the trench in a traditional process, and the width of the trench is smaller than that of the trench in a traditional process. Therefore the cell area is reduced, the number of cell per unit area on the chip is increased and the specific on resistance of the device is reduced.

At S230: polysilicon is deposited into the trench to form a floating gate polycrystalline layer.

Referring to <FIG>, in the embodiment, polysilicon can be deposited in the trench using low-pressure chemical vapor deposition method to form a floating gate polycrystalline layer <NUM>. After the polysilicon is filled in the trench <NUM>, the polysilicon can be etched back or ground in order that the upper surface of the floating gate polycrystalline layer <NUM> is lower than the lower surface of the P-type well region formed in the subsequent process.

At S240: an insulating medium is grown on the surface of floating gate polycrystalline layer to form an isolation layer.

Referring to <FIG>, in this embodiment, insulating medium may be grown on the surface of the floating gate polycrystalline layer <NUM> using thermal oxidation method or chemical vapor deposition method to form an isolation layer <NUM>, in which the insulating medium can be silicon nitride, silicon oxide or silicon oxynitride, and the isolation layer <NUM> is used to isolate the floating gate polycrystalline layer <NUM> from the control gate formed in the subsequent process.

Further, before the step of forming the isolation layer <NUM> on the upper surface of the floating gate polycrystalline layer <NUM>, the method further comprises a step of removing the first oxide layer <NUM> above the floating gate polycrystalline layer <NUM>. Specifically, the first oxide layer <NUM> above the floating gate polycrystalline layer <NUM> can be removed using dry etching technology.

At S250: a control gate is formed on the isolation layer in the trench.

Further, referring to <FIG>, the step of forming a control gate on the isolation layer <NUM> in the trench <NUM> specifically includes: forming a control gate oxide layer <NUM> on the trench side wall above the isolation layer <NUM>; forming a control gate polycrystalline layer <NUM> by depositing the polysilicon on the isolation layer <NUM> in the trench <NUM> where the control gate polycrystalline layer <NUM> is adjacent to the control gate oxide layer <NUM>; etching back or grinding the control gate polycrystalline layer <NUM>. The control gate is constituted by the control gate oxide layer <NUM> and the control gate polycrystalline layer <NUM> together.

Specifically, in the present embodiment, the polysilicon can be deposited in the trench <NUM> using low-pressure chemical vapor deposition method, and the polysilicon is doped at the same time. The polysilicon outside the trench <NUM> can be etched using dry etching process to form a control gate.

In the method for manufacturing a trench split-gate device provided by the embodiment, by using the high-density plasma chemical vapor deposition process, the thickness of the second oxide layer at the bottom and on the side wall of the trench can be adjusted by adjusting the pressure of the reaction chamber and the flow rate of the reaction gas. The thickness of the floating gate oxide on the side wall of the trench is gradually increased from top to bottom, and the thickness of the floating gate oxide at the lower part of the side wall of the trench is the same as that of the floating gate oxide at the bottom of the trench. Therefore, on the one hand, it can meet the requirement of withstanding the gradually changing voltage, and at the same time, the width of the trench can be reduced by the gradually changing thickness of the floating gate oxide, thereby further reducing the cell area, increasing the number of cell receivable per unit area on the chip, and reducing the specific on resistance of the device.

Referring to <FIG>, after the step of forming a control gate on the isolation layer in the trench, the method further comprises: forming a P-type well region <NUM> by injecting the P-type impurity to both sides of the trench <NUM>. An N-type heavily doped region <NUM> is formed in the P-well region <NUM> on both sides of the trench <NUM> by injecting a highly doped N-type impurity. Then, an isolation oxide layer <NUM> is formed on the control gate using thermal oxidation method. The isolated oxide layer <NUM> is etched to form a contact hole <NUM> penetrating the P-type well region, and the N-type heavily doped region <NUM> is located between the contact hole <NUM> and the trench <NUM>. Heavily doped P-type impurity is injected into P-well region through the contact hole <NUM> to form a P-type heavily doped region <NUM>. After that, the contact hole <NUM> is filled, and finally a source electrode is formed on the isolation oxide layer <NUM>, and a drain electrode is formed on the lower surface of the bulk layer <NUM>, and thus the basic structure of the trench split-gate device is formed.

A trench split-gate device is also provided by the embodiment, which is manufactured according to the steps of the method shown in <FIG>. Specifically, as shown in <FIG>, the trench split-gate device includes a semiconductor substrate, which includes a bulk layer <NUM> and an epitaxial layer <NUM>. A trench <NUM> is provided in the semiconductor substrate, the trench <NUM> is arranged in the epitaxial layer <NUM>, and the side wall of the trench <NUM> is vertical up and down. The inner wall of the trench <NUM> is provided with a floating gate oxide layer. The floating gate oxide includes a first oxide layer <NUM> on the inner wall of the trench <NUM> and a second oxide layer <NUM> on the first oxide layer <NUM>. The thickness of the first oxide layer <NUM> on the side wall of the trench <NUM> is uniform everywhere, the thickness of the second oxide layer <NUM> is gradually increased from top to bottom along the side wall of the trench <NUM>, and the thickness of the second oxide layer <NUM> at the lower part of the side wall of the trench <NUM> is the same as that of the second oxide layer <NUM> at the bottom of the trench <NUM>. Therefore, the total thickness of the floating gate oxide constituted of the first oxide layer <NUM> and the second oxide layer <NUM> is gradually increased from top to bottom along the side wall of the trench <NUM>, and the thickness of the floating gate oxide layer at the lower part of the side wall of the trench <NUM> is the same as that of the floating gate oxide layer at the bottom of the trench <NUM>. A floating gate polycrystalline layer <NUM> is provided on the surface of the floating gate oxide layer. A floating gate structure is constituted of floating gate polycrystalline layer <NUM> and floating gate oxide layer together. The upper surface of the floating gate polycrystalline layer <NUM> is provided with an isolation layer <NUM>. A control gate polycrystalline layer <NUM> and a control gate oxide layer <NUM> are provided on the isolation layer <NUM>. A control gate structure is constituted of the control gate polycrystalline layer <NUM> and the control gate oxide layer <NUM> together.

In the trench split-gate device provided by the embodiment of the disclosure, the second oxide layer is formed using HDP CVD process at the bottom and on side wall of the trench, such that the thickness of the second oxide layer is gradually increased from top to bottom along the side wall of the trench, and the thickness of the second oxide layer at the lower part of the side wall of the trench is the same as that of the second oxide layer at the bottom of the trench. Furthermore, the total thickness of the floating gate oxide constituted of the first oxide layer and the second oxide layer is gradually increased from top to bottom along the side wall of the trench, and the thickness of the floating gate oxide layer at the lower part of the side wall of the trench is the same as that of the floating gate oxide layer at the bottom of the trench. Therefore, on the one hand, it can meet requirement of withstanding the gradually changing voltage, and at the same time, the width of the trench can be reduced by the gradually changing thickness of the floating gate oxide, and thus the cell area is further reduced and the specific on resistance of the device is reduced.

In another embodiment, the step of etching a semiconductor substrate to form a trench specifically comprises: etching the semiconductor substrate to form a vertical upper half trench. The semiconductor substrate is etched obliquely downward from the bottom of the upper half trench to form a lower half trench extending downward from the bottom of the half trench and with a width gradually increased from the top to the bottom. And the bottom of the lower half trench is concave arc-shaped. The step of depositing oxide into the trench to form a floating gate oxide layer includes: forming a first oxide layer on the inner surface of the trench; etching the first oxide layer to make the side wall of the first oxide layer vertical up and down; forming a second oxide layer on the first oxide layer at the bottom of the lower half trench using high density plasma chemical vapor deposition process, in which the thickness of the floating gate oxide layer constituted of the first oxide layer and the second oxide layer is gradually increased from top to bottom along the side wall of the trench. The thickness of the floating gate oxide at the lower part of the side wall of the lower half of the trench is the same as that of the floating gate oxide at the bottom of the lower half of the trench.

Specifically, referring to <FIG>, in the present embodiment, the method for manufacturing the trench split-gate device specifically includes the following steps:
At S300: a semiconductor substrate is etched to form a vertical upper half trench.

Referring to <FIG>, the semiconductor substrate includes a bulk layer <NUM> and an epitaxial layer <NUM>. In this embodiment, the semiconductor substrate is vertically etched using dry etching technique to form a vertically downward upper half trench <NUM> in the epitaxial layer <NUM>. During the etching process, the polymer generated by the reaction of the etching gas and the silicon substrate is reserved to protect the upper half trench <NUM>, so that the surface of the upper half trench <NUM> will not be etched when proceeding with the next step.

At S310: the semiconductor substrate is etched obliquely downward from the bottom of the upper half trench to form a lower half trench extending downward from the bottom of the upper half trench and with a width gradually increased from the top to the bottom.

Referring to <FIG>, similarly using the dry etching technology, the epitaxial layer <NUM> is etched obliquely downward from the bottom of the vertical upper trench <NUM> to form the lower half trench <NUM> extending downward from the bottom of the upper half trench <NUM> and with a width gradually increased from the top to the bottom, and the bottom of the lower half trench <NUM> is concave arc-shaped. The trench <NUM> is constituted of the upper half trench <NUM> and the lower half trench <NUM> together. After the etching of trench <NUM> is completed, the step of acid pickling is carried out to remove the polymer attached on the surface of trench <NUM> generated by etching.

At S320: a first oxide layer is formed on the inner surface of the trench.

Referring to <FIG>, a first oxide layer <NUM> can be oxidizedly formed on the inner surface of trench <NUM> using furnace tube oxidation method or CVD process. Specifically, in the present embodiment, the first oxide layer <NUM> is grown by oxidizing on the surface of trench <NUM> using furnace tube oxidation method.

At S330: the first oxide layer is etched to enable the side wall of the first oxide layer vertical up and down.

After the growing process is completed, the first oxide layer <NUM> is dry etched, so that the side wall of the first oxide layer <NUM> of the inner wall of the trench is vertical up and down, and the thickness of the first oxide layer <NUM> of the side wall of the lower half trench <NUM> is gradually increased from top to bottom.

At S340: a second oxide layer is formed on the first oxide layer at the bottom of the lower half trench using high density plasma chemical vapor deposition process, in which the thickness of the floating gate oxide layer formed by the combination of the first oxide layer and the second oxide layer gradually increased from top to bottom along the side wall of the trench, and the thickness of the floating gate oxide layer at the lower part of the side wall of the trench is the same as that of the floating gate oxide layer at the bottom of the trench.

Referring to <FIG>, a second oxide layer <NUM> is deposited on the first oxide layer <NUM> at the bottom of the lower half trench <NUM> using HDP CVD deposition method to thicken the floating gate oxide layer at the bottom of the lower half trench <NUM> and enhance the performance of the device withstanding voltage. Since the thickness of the first oxide layer <NUM> on the side wall of the lower half trench <NUM> gradually increases from top to bottom along the lower half trench <NUM>, and the second oxide layer <NUM> is located on the first oxide layer <NUM> at the bottom of the lower half trench <NUM>, the total thickness of the floating gate oxide layer formed by the first oxide layer <NUM> and the second oxide layer <NUM> gradually increases from top to bottom along the side wall of the lower half trench <NUM>, and the thickness of the floating gate oxide layer at the lower part of the side wall of the lower half trench <NUM> is the same as that of the floating gate oxide at the bottom of half trench <NUM>.

At S350: polysilicon is deposited into the trench to form a floating gate polycrystalline layer.

As shown in <FIG>, in the present embodiment, polysilicon can be deposited in the trench <NUM> using low-pressure chemical vapor deposition method to form a floating gate polycrystalline layer <NUM>. Furthermore, after the polysilicon is filled in the trench <NUM>, the polysilicon can be etched back or ground in order that the upper surface of the floating gate polycrystalline layer <NUM> is lower than the lower surface of the P-type well region formed in the subsequent processes.

At S360: an insulating medium is grown on the surface of the floating gate polycrystalline layer to form an isolation layer.

As shown in <FIG>, insulating medium can be deposited on the surface of floating gate polycrystalline layer <NUM> using thermal oxidation method or chemical vapor deposition method to form an isolation layer <NUM>. The insulating medium can be silicon nitride or silicon oxide or silicon oxynitride, which is used for isolating the floating gate polycrystalline layer <NUM> and the control gate formed in subsequent processes.

Further, before the step of forming an isolation layer <NUM> on the upper surface of the floating gate polycrystalline layer <NUM>, the method can further include the step of removing the first oxide layer <NUM> above the floating gate polycrystalline layer <NUM>. Specifically, the first oxide layer <NUM> above the floating gate polycrystalline layer <NUM> can be removed using dry etching technology.

At S370: a control gate is formed on the isolation layer in the trench.

Further, as shown in <FIG>, forming a control gate on the isolation layer <NUM> in the trench <NUM> specifically includes: forming a control gate oxide layer <NUM> on the side wall of the trench above the isolation layer <NUM>; depositing polysilicon on the isolation layer <NUM> in the trench <NUM> to form a control gate polycrystalline layer <NUM> in which the control gate polycrystalline layer <NUM> is adjacent to the control gate oxide layer <NUM>; and etching back or grinding the control gate polycrystalline layer <NUM> to form the control gate, where the control gate includes a control gate oxide layer <NUM> and a control gate polycrystalline layer <NUM>.

Specifically, in this embodiment, polysilicon can be deposited in trench <NUM> using low-pressure chemical vapor deposition method, and polysilicon is doped at the same time. The polysilicon outside the trench <NUM> can be etched using dry etching process to form the control gate.

In the method for manufacturing the trench split-gate device provided by the present embodiment, the lower half trench with the width gradually increased from the top to the bottom is formed by etching the vertical upper half trench firstly and then etching obliquely downward from the bottom of the upper half trench. The trench is constituted by the upper half trench and the lower half trench together. Then a first oxide layer is grown on the inner side of the trench, in which the thickness of the first oxide layer in the lower half trench gradually increases from top to bottom along the side wall of the lower half trench. Next, a second oxide layer is deposited on the first oxide layer at the bottom of the lower half trench to increase the thickness of the floating gate oxide layer at the bottom of the lower half trench, in order that the total thickness of the floating gate oxide layer constituted of the first oxide layer and the second oxide layer is gradually increase from top to bottom along the side wall of the lower half trench, and the thickness of the floating gate oxide layer at the lower part of the lower half trench is the same as that of the floating gate oxide layer at the bottom of the lower half trench. Therefore, on the one hand, it can meet the requirement of withstanding the gradually changing voltage, and at the same time, it can reduce the cell area and the specific on resistance of the device.

Referring to <FIG>, after the step of forming a control gate on the isolation layer in the trench, the method further includes: forming a P-type well region <NUM> by injecting the P-type impurity to both sides of the trench <NUM>. An N-type heavily doped region <NUM> is formed in the P-type well region <NUM> on both sides of the trench <NUM> by injecting highly doped N-type impurity. An isolated oxide layer <NUM> can be formed on the control gate using thermal oxidation method. A contact hole <NUM> penetrating the P-type well region is formed by etching the isolated oxide layer <NUM>. The N-type heavily doped region <NUM> is located between the contact hole <NUM> and the trench <NUM>. A P-type heavily doped region <NUM> is formed by injecting heavily doped P-type impurity into P-well region through contact hole <NUM>. After that, the contact hole <NUM> is filled, and finally a source electrode is formed on the isolation oxide layer <NUM>, a drain electrode is formed on the lower surface of the bulk layer <NUM>, and thus a basic structure of the split-gate device is formed.

The present embodiment also provides a trench split-gate device, which is manufactured according to the steps of the method shown in <FIG>. Specifically, as shown in <FIG>, the trench split-gate device includes a semiconductor substrate. The semiconductor substrate includes a bulk layer <NUM> and an epitaxial layer <NUM>. A trench <NUM> is provided in the epitaxial layer <NUM>. The trench <NUM> includes an upper half trench <NUM> with side wall vertical up and down and a lower half trench <NUM> extending downward from the bottom of the upper half trench and with a width gradually increased from the top to the bottom. The bottom of the lower half trench is concave arc-shaped. The inner wall of the trench <NUM> is provided with an oxide layer, which includes a first oxide layer <NUM> on the inner wall of the trench and a second oxide layer <NUM> on the first oxide layer <NUM> at the bottom of the trench. The thickness of the first oxide layer <NUM> on the inner wall of the lower half trench <NUM> is gradually increased from top to bottom along the side wall of the lower half trench <NUM>, and the second oxide layer <NUM> is used to increase the thickness of the floating gate oxide layer at the bottom of the lower half trench <NUM>. Therefore, the total thickness of the floating gate oxide constituted of the first oxide layer <NUM> and the second oxide layer <NUM> is gradually increased from top to bottom along the side wall of the lower half trench <NUM>, and the thickness of the floating gate oxide layer at lower part of the side wall of the lower half trench <NUM> is the same as that of the floating gate oxide layer at the bottom half trench <NUM>. A floating gate polycrystalline layer <NUM> is provided on the surface of the floating gate oxide layer. The upper surface of the floating gate polycrystalline layer <NUM> is provided with an isolation layer <NUM>. The side wall of the upper half trench <NUM> above the isolation layer <NUM> is provided with a control gate oxide layer <NUM>. The control gate polycrystalline layer <NUM> is located on the isolation layer <NUM> and adjacent to the control gate oxide layer <NUM>. The control gate of the trench split-gate device is constituted by the control gate oxide layer <NUM> and the control gate polycrystalline layer <NUM> together.

In the trench split-gate device provided by the embodiment of the invention, the width of the lower half trench is gradually increased from top to bottom, and the thickness of the first oxide layer which is grown on the inner wall of the lower half trench is gradually increased from top to bottom, and the second oxide layer is used to thicken the bottom of the trench, such that the total thickness of the floating gate oxide layer constituted by the first oxide layer and the second oxide layer is gradually increased from top to bottom along the side wall of the lower half trench. The thickness of floating gate oxide at the lower part of the sided wall of the lower half trench is the same as that of the floating gate oxide at the bottom of the lower half trench. Therefore, on the one hand, it can meet the requirement of withstanding the gradually changing voltage. At the same time, the gradually changing thickness of the floating gate oxide can reduce the width of the trench, and further reduce the cell area and the specific on resistance of the device.

Claim 1:
A method for manufacturing a trench split-gate device, comprising:
etching (S300) a semiconductor substrate to form a vertical upper half trench (<NUM>);
etching (S310) the semiconductor substrate obliquely downward from a bottom of the upper half trench (<NUM>) to form a lower half trench (<NUM>) extending downward from the bottom of the upper half trench (<NUM>) and with a width that increases from top to bottom, and a bottom of the lower half trench (<NUM>) being concave arc-shaped, and a trench (<NUM>) being constituted by the upper half trench (<NUM>) and the lower half trench (<NUM>)together;
forming (S320) a first oxide layer (<NUM>) on an inner surface of the trench (<NUM>);
etching (S330) the first oxide layer (<NUM>) to enable a side wall of the first oxide layer (<NUM>)vertical up and down;
forming (S340) a second oxide layer (<NUM>) on the first oxide layer (<NUM>) at the bottom of the lower half trench (<NUM>) using high density plasma chemical vapor deposition process, so that a floating gate oxide layer formed by combination of the first oxide layer (<NUM>) and the second oxide layer (<NUM>) thickens from top to bottom along a side wall of the lower half trench (<NUM>), and the thickness of the floating gate oxide layer at a lower part of the side wall of the lower half trench (<NUM>) is the same as that of the floating gate oxide layer at the bottom of the lower half trench (<NUM>;
depositing (S350) polysilicon into the trench (<NUM>) to form a floating gate polycrystalline layer (<NUM>);
growing (S360) an insulating medium on an upper surface of the floating gate polycrystalline layer (<NUM>) to form an isolation layer (<NUM>); and
forming a control gate on the isolation layer in the trench (<NUM>).