Patent Description:
Today, many integrated circuit (IC) and system-on-a-chip (SoC) devices for advanced automotive radar systems, for example, require high speed and high accuracy operation. The IC and SoC devices often include sophisticated circuitry for controlling these radar systems. As radar systems advance, requirements of the control circuits advance to meet performance targets. However, challenges exist in balancing product costs while meeting these performance targets.

<CIT>discloses a DAC using current mirrors suitable for use in a modulator.

<CIT> discloses a time delay generator apparatus and method.

The invention is defined in the accompanying claims.

According to the invention, there is provided a circuit comprising: a phase rotator core having a first input coupled to receive a first radio frequency (RF) signal, a second input coupled to receive a first phase control signal, and an output for providing an output signal; and a phase control block coupled to the phase rotator core. The phase control block comprises: a first transistor having a control electrode coupled to receive a first control signal; a second transistor having a control electrode coupled to receive a second control signal and a first current electrode coupled to a first current electrode of the first transistor; a third transistor having a control electrode and a first current electrode coupled to the first current electrodes of the first and second transistors; a first filter having first terminal coupled to the control electrode and the first current electrode of the third transistor; and a fourth transistor having a control electrode coupled to a second terminal of the first filter and a first current electrode coupled to the second input of the phase rotator core to provide the first phase control signal and a first switch having a first terminal coupled to the first current electrodes of the first and second transistors, a second terminal coupled to the control electrode and the first current electrode of the third transistor, and a control terminal coupled to receive a third control signal; wherein the first switch is configured to be: closed based on a first state of the third control signal in order to define a sample mode; and open based on a second state of the third control signal in order to define a hold mode.

In one or more embodiments, the phase control block may further comprise: a first current source having a first terminal coupled to a first voltage supply and a second terminal coupled to a second current electrode of the first transistor; and a second current source having a first terminal coupled to the first voltage supply and a second terminal coupled to a second current electrode of the second transistor.

In one or more embodiments, the first filter may comprise: a first resistor having a first terminal coupled to the control electrode and the first current electrode of the third transistor and a second terminal coupled to the control electrode of the fourth transistor; and a first capacitor having a first terminal coupled to the second terminal of the first resistor and the control electrode of the fourth transistor.

In one or more embodiments, the phase control block may further comprise: a multi-stage noise shaping (MASH) block coupled to provide the first control signal and the second control based on a main control signal.

In one or more embodiments, the phase control block may further comprise: a fifth transistor having a control electrode coupled to receive a first complement signal, the first complement signal characterized as an inverted version of the first control signal; a sixth transistor having a control electrode and a first current electrode coupled to a first current electrode of the fifth transistors; a second filter having a first terminal coupled to the control electrode and the first current electrode of the sixth transistor; and a seventh transistor having a control electrode coupled to a second terminal of the second filter and a first current electrode coupled to a third input of the phase rotator core to provide a second phase control signal.

In one or more embodiments, the first phase control signal and the second phase control signal together may comprise a differential phase control signal, and the second and third inputs of the phase rotator core together may be characterized as a differential input for receiving the differential phase control signal.

In one or more embodiments, the phase control block may further comprise: an eighth transistor having a control electrode coupled to receive a second complement signal and a first current electrode coupled to the first current electrode of the fifth transistor, the second complement signal characterized as an inverted version of the second control signal.

In a second aspect, there is provided a circuit comprising: a phase rotator core having a first input coupled to receive a first radio frequency (RF) signal, a second input coupled to receive a first phase control signal, and an output for providing an output signal; and a phase control block coupled to the phase rotator core. The phase control block comprises: a first transistor having a control electrode coupled to receive a first control signal, a first current electrode, and a second current electrode; a second transistor having a control electrode coupled to receive a second control signal and a first current electrode coupled to the first current electrode of the first transistor; a first switch having a first terminal coupled to the first current electrodes of the first and second transistors, and a control terminal coupled to receive a third control signal; a third transistor having a control electrode and a first current electrode coupled to a second terminal of the first switch; a first filter having a first terminal coupled to the control electrode and the first current electrode of the third transistor; and a fourth transistor having a control electrode coupled to a second terminal of the first filter and a first current electrode coupled to the second input of the phase rotator core to provide the first phase control signal.

In one or more embodiments, the phase control block may further comprise: a first current source having a first terminal coupled to a first voltage supply and a second terminal coupled to the second current electrode of the first transistor; and a second current source having a first terminal coupled to the first voltage supply and a second terminal coupled to a second current electrode of the second transistor.

In one or more embodiments, the phase control block may further comprise a first variable current source having a first terminal coupled to the first voltage supply and a second terminal coupled to the second current electrode of the first transistor.

According to the invention, the first switch is configured to be closed during a sample phase of the phase control block and open during a hold phase of the phase control block.

In one or more embodiments, the phase control block may further comprise a multi-stage noise shaping (MASH) block coupled to provide the first control signal and the second control based on a main control signal.

Generally, there is provided, a phase rotator control system including analog control signals generated by digital-to-analog converter (DAC) with embedded filter circuitry. A multi-stage noise shaping (MASH) circuit block provides a reduced set of digital control signals to the DAC circuitry. A sample-and-hold circuit arrangement within the DAC circuitry allows for low noise and power efficient operation of a radar system during chirp time periods, for example, and allows for new phase values to be updated during inter-chirp time periods.

<FIG> illustrates, in simplified block diagram form, an example phase rotator <NUM> in accordance with an embodiment. Phase rotator <NUM> includes an input labeled IN for receiving a radio frequency (RF) signal, an output labeled OUT for providing an output signal OUT, a sample and hold control signal labeled SH, and a multi-bit control signal labeled CTRL. In this example, phase rotator <NUM> includes a quadrature splitter circuit block <NUM> labeled IQ, a phase rotator core circuit block <NUM>, and a phase control circuit block <NUM>. The phase control circuit block <NUM> includes a first digital-to-analog converter (DAC) with integrated filter circuit sub-block <NUM> labeled DACFI, a second DAC with integrated filter circuit sub-block <NUM> labeled DACFQ, a first multi-stage noise shaping (MASH) circuit sub-block <NUM> labeled MASHI, and a second MASH circuit sub-block <NUM> labeled MASHQ.

The IQ circuit block <NUM> is configured and arranged to receive an RF signal and in turn, generate a corresponding complex (IQ) RF signal consisting of a first (I) signal component labeled RFDI and a second (Q) signal component labeled RFDQ. In this embodiment, the RFDI signal component is characterized as an in-phase signal being substantially in phase with the received RF signal and the RFDQ signal component is characterized as a quadrature signal being substantially <NUM> degrees out of phase with the received RF signal. For example, the RFDI signal may have a cosine waveform and the RFDQ signal may have a sine waveform. In this embodiment, each of the RFDI and RFDQ signals is formed as a differential signal pair having a "+" component and a "-" complementary component.

The phase rotator core circuit block <NUM> is configured and arranged to receive the complex RF signal (e.g., RFDI and RFDQ signals) at a first set of inputs, a complex control signal (e.g., DII and DIQ signals) at a second set of inputs, and in turn, generate the OUT signal at the output labeled OUT. In this embodiment, the RFDI and RFDQ signals are modulated by the respective DII and DIQ controls signals and subsequently combined to generate the OUT signal.

The phase control circuit block <NUM> is configured and arranged to receive the SH control signal at inputs of the DACFI and DACFQ circuits, the CTRL control signal (e.g., CTRLI and CTRLQ control signals) at inputs of the MASHI and MASHQ circuits, and in turn, generate the complex control signal (e.g., DII and DIQ signals) at outputs of the DACFI and DACFQ circuits. In this embodiment, the CTRL control signal consists of a first (I) control signal labeled CTRLI and a second (Q) control signal labeled CTRLQ. For example, the multibit CTRL control signal may include the CTRLI control signal formed as a first <NUM>-bit control signal and the CTRLQ formed as a second <NUM>-bit control signal.

The MASHI and MASHQ circuits (<NUM>, <NUM>) are configured and arranged to receive the CTRLI and CTRLQ control signals respectively at inputs and in turn, generate control signals labeled C2BI and C2BQ respectively at outputs. For example, each of the MASHI and MASHQ circuits receives a multi-bit control signal (e.g., CTRLI and CTRLQ control signals) which is quantized into a <NUM>-bit control signal (e.g., C2BI and C2BQ control signals). In this embodiment, each of the MASHI and MASHQ circuits includes two first-order sigma delta converters coupled in series to generate a second-order quantized sigma delta output signal (e.g., <NUM>-bit C2BI and C2BQ control signals).

The DACFI and DACFQ circuits (<NUM>, <NUM>) are configured and arranged to receive the C2BI and C2BQ control signals respectively at inputs and in turn, generate the DII and DIQ controls signals respectively at outputs. In this embodiment, each of the DACFI and DACFQ circuits receives a <NUM>-bit control signal (e.g., C2BI and C2BQ control signals) which is converted into an analog control signal (e.g., C2BI and C2BQ control signals). In this embodiment, each of the analog DII and DIQ control signals may be characterized as a differential control signal.

<FIG> illustrates, in simplified schematic diagram form, an example DACFI implementation <NUM> of the circuit block <NUM> included in the phase control block <NUM> in accordance with an embodiment. In this embodiment, the DACFI circuit <NUM> includes current sources <NUM>-<NUM>, P-channel transistors <NUM>-<NUM>, N-channel transistors <NUM>-<NUM>, switches <NUM>-<NUM>, and filter circuits <NUM>-<NUM>. The DACFI circuit <NUM> is configured to receive the digital <NUM>-bit C2BI control signals labeled C2BI_0 and C2BI_1 and their respective complement or inverted signal versions labeled C2BI_0N and C2BI_1N, the SH control signal, and generates the analog differential DII control signals labeled DII+ and DII- at corresponding differential outputs. In this embodiment, the DACFI circuit <NUM> generates the analog differential DII control signals based on the digital <NUM>-bit C2BI control signals.

A first current source <NUM> and a second current source <NUM> are coupled in parallel between a first voltage supply terminal labeled VDD and node A. In this embodiment, a normal operating voltage is supplied at the VDD supply terminal. A first terminal of variable current source <NUM> and a first terminal of current source <NUM> are connect to the VDD supply terminal and second terminals of current sources <NUM> and <NUM> are connected at node A. A third current source <NUM> is coupled between the VDD supply terminal and node B. Current source <NUM> is configured to provide a first current I1 and current source <NUM> is configured to provide a second current I2. In this embodiment, the current I2 is substantially equal to <NUM> times the current I1 (e.g., a ratio of current I2 to current I1 is <NUM>:<NUM>). In other embodiments, the relationship of current I2 to current I1 may have other ratios. In this embodiment, current source <NUM> may be configured to provide an adjustable trim current for improving accuracy by compensating for integral nonlinearity, for example.

A first current electrode of transistor <NUM> is connected to current sources <NUM> and <NUM> at node A, a second current electrode of transistor <NUM> is connected to a first terminal of switch <NUM> at node C, and a control electrode of transistor <NUM> is configured to receive the C2BI_0 control signal. A first current electrode of transistor <NUM> is connected to the first current electrode of transistor <NUM> and current sources <NUM> and <NUM> at node A, a second current electrode of transistor <NUM> is connected to a first terminal of switch <NUM> at node D, and a control electrode of transistor <NUM> is configured to receive the C2BI_0N complement control signal.

A first current electrode of transistor <NUM> is connected to current source <NUM> at node B, a second current electrode of transistor <NUM> is connected to the second current electrode of transistor <NUM> and the first terminal of switch <NUM> at node C, and a control electrode of transistor <NUM> is configured to receive the C2BI_1 control signal. A first current electrode of transistor <NUM> is connected to the first current electrode of transistor <NUM> and current source <NUM> at node B, a second current electrode of transistor <NUM> is connected to the first terminal of switch <NUM> at node D, and a control electrode of transistor <NUM> is configured to receive the C2BI_1N complement control signal.

A first current mirror is formed including transistors <NUM> and <NUM> coupled together by way of a first filter circuit <NUM>. A first current electrode and a control electrode of transistor <NUM> is connected to a second terminal of switch <NUM> and a first terminal of filter circuit <NUM> at node E, and a second current electrode of transistor <NUM> is connected to a second voltage supply terminal labeled VSS. A first current electrode of transistor <NUM> is coupled to provide the DII+ signal component of the differential DII control signal, a second current electrode of transistor <NUM> is connected to the VSS supply terminal, and a control electrode of transistor <NUM> is connected to a second terminal of filter circuit <NUM> at node G. In this embodiment, the first filter circuit <NUM> includes a first resistor <NUM> and a first capacitor <NUM>. A first terminal of resistor <NUM> is connected at node E, a second terminal of resistor <NUM> is connected to a first terminal of capacitor <NUM> at node G, and a second terminal of capacitor <NUM> is connected at the VSS supply terminal. In this embodiment, a ground voltage (e.g., <NUM> volts) is supplied at the VSS supply terminal.

A second current mirror is formed including transistors <NUM> and <NUM> coupled together by way of a second filter circuit <NUM>. A first current electrode and a control electrode of transistor <NUM> is connected to a second terminal of switch <NUM> and a first terminal of filter circuit <NUM> at node F, and a second current electrode of transistor <NUM> is connected to the VSS supply terminal. A first current electrode of transistor <NUM> is coupled to provide the DII-signal component of the differential DII control signal, a second current electrode of transistor <NUM> is connected to the VSS supply terminal, and a control electrode of transistor <NUM> is connected to a second terminal of filter circuit <NUM> at node H. In this embodiment, the second filter circuit <NUM> includes a second resistor <NUM> and a second capacitor <NUM>. A first terminal of resistor <NUM> is connected at node F, a second terminal of resistor <NUM> is connected to a first terminal of capacitor <NUM> at node H, and a second terminal of capacitor <NUM> is connected at the VSS supply terminal. Control terminals of switches <NUM> and <NUM> are configured to receive the SH control signal.

In operation, the <NUM>-bit C2BI control signals C2BI_0 and C2BI_1 and their respective complement signals C2BI_0N and C2BI_1N are received at the control electrodes of transistors <NUM>-<NUM>. When the SH control signal is at a first state (i.e., sample mode), switches <NUM>-<NUM> are closed allowing corresponding currents (e.g., I1 and I2) selected by way of the C2BI control signals to propagate to the first and second current mirrors accordingly. For example, when C2BI_0 is at a logic low and C2BI_1 is at a logic low, the current generated for DII+ is substantially equal to I1+I2 and the current generated for DII- is substantially equal to <NUM>; when C2BI_0 is at a logic high and C2BI_1 is at a logic low, the current generated for DII+ is substantially equal to I2 and the current generated for DII- is substantially equal to I1; when C2BI_0 is at a logic low and C2BI_1 is at a logic high, the current generated for DII+ is substantially equal to I1 and the current generated for DII- is substantially equal to I2; and when C2BI_0 is at a logic high and C2BI_1 is at a logic high, the current generated for DII+ is substantially equal to <NUM> and the current generated for DII- is substantially equal to I1+I2. In this embodiment, the first state of the SH control signal may occur during inter-chirp time periods (e.g., between consecutive chirps) of a radar system. During these inter-chirp periods, the capacitors <NUM>-<NUM> of the filter circuits <NUM>-<NUM> are refreshed or charged to new values based on the C2BI control signals.

When the SH control signal is at a second state (i.e., hold mode), switches <NUM>-<NUM> are open allowing charged values to be stored on the capacitors <NUM>-<NUM> of the filter circuits <NUM>-<NUM>. For example, values of the DII+ and DII- signal components are held based on the charge values of the capacitors <NUM>-<NUM>. In this embodiment, the second state of the SH control signal may occur during chirp time periods (e.g., active portions of radar modulation) of the radar system. Because the DII+ and DII- signal components are held based on the charge values of the capacitors <NUM>-<NUM> during these chirp time periods, noise and power consumption are reduced.

<FIG> illustrates, in simplified schematic diagram form, an example DACFQ implementation <NUM> of the circuit block <NUM> included in the phase control block <NUM> in accordance with an embodiment. In this embodiment, the DACFQ circuit <NUM> includes current sources <NUM>-<NUM>, P-channel transistors <NUM>-<NUM>, N-channel transistors <NUM>-<NUM>, switches <NUM>-<NUM>, and filter circuits <NUM>-<NUM>. The DACFQ circuit <NUM> is configured to receive the <NUM>-bit C2BQ control signals labeled C2BQ_0 and C2BQ_1 and their respective complement or inverted signal versions labeled C2BQ_0N and C2BQ_1N, the SH control signal, and generates the differential DIQ control signals labeled DIQ+ and DIQ- at corresponding differential outputs. In this embodiment, the DACFQ circuit <NUM> generates the analog differential DIQ control signals based on the digital <NUM>-bit C2BQ control signals.

A fourth current source <NUM> and a fifth current source <NUM> are coupled in parallel between the VDD supply terminal and node AA. A first terminal of variable current source <NUM> and a first terminal of current source <NUM> are connect to the VDD supply terminal and second terminals of current sources <NUM> and <NUM> are connected at node AA. A sixth current source <NUM> is coupled between the VDD supply terminal and node BB. Current source <NUM> is configured to provide a third current I11 and current source <NUM> is configured to provide a fourth current I22. In this embodiment, the current I11 is substantially equal to the current I1, and the current I22 is substantially equal to <NUM> times the current I11 (e.g., a ratio of current I22 to current I11 is <NUM>:<NUM>). In other embodiments, the relationship of current I22 to current I11 may have other ratios. In this embodiment, current source <NUM> may be configured to provide an adjustable trim current for improving accuracy by compensating for integral nonlinearity, for example.

A first current electrode of transistor <NUM> is connected to current sources <NUM> and <NUM> at node AA, a second current electrode of transistor <NUM> is connected to a first terminal of switch <NUM> at node CC, and a control electrode of transistor <NUM> is configured to receive the C2BQ_0 control signal. A first current electrode of transistor <NUM> is connected to the first current electrode of transistor <NUM> and current sources <NUM> and <NUM> at node AA, a second current electrode of transistor <NUM> is connected to a first terminal of switch <NUM> at node DD, and a control electrode of transistor <NUM> is configured to receive the C2BQ_0N complement control signal.

A first current electrode of transistor <NUM> is connected to current source <NUM> at node BB, a second current electrode of transistor <NUM> is connected to the second current electrode of transistor <NUM> and the first terminal of switch <NUM> at node CC, and a control electrode of transistor <NUM> is configured to receive the C2BQ_1 control signal. A first current electrode of transistor <NUM> is connected to the first current electrode of transistor <NUM> and current source <NUM> at node BB, a second current electrode of transistor <NUM> is connected to the first terminal of switch <NUM> at node DD, and a control electrode of transistor <NUM> is configured to receive the C2BQ_1N complement control signal.

A third current mirror is formed including transistors <NUM> and <NUM> coupled together by way of a third filter circuit <NUM>. A first current electrode and a control electrode of transistor <NUM> is connected to a second terminal of switch <NUM> and a first terminal of filter circuit <NUM> at node EE, and a second current electrode of transistor <NUM> is connected to the VSS supply terminal. A first current electrode of transistor <NUM> is coupled to provide the DIQ+ signal component of the differential DIQ control signal, a second current electrode of transistor <NUM> is connected to the VSS supply terminal, and a control electrode of transistor <NUM> is connected to a second terminal of filter circuit <NUM> at node GG. In this embodiment, the third filter circuit <NUM> includes a third resistor <NUM> and a third capacitor <NUM>. A first terminal of resistor <NUM> is connected at node EE, a second terminal of resistor <NUM> is connected to a first terminal of capacitor <NUM> at node GG, and a second terminal of capacitor <NUM> is connected at the VSS supply terminal.

A fourth current mirror is formed including transistors <NUM> and <NUM> coupled together by way of a fourth filter circuit <NUM>. A first current electrode and a control electrode of transistor <NUM> is connected to a second terminal of switch <NUM> and a first terminal of filter circuit <NUM> at node FF, and a second current electrode of transistor <NUM> is connected to the VSS supply terminal. A first current electrode of transistor <NUM> is coupled to provide the DIQ- signal component of the differential DIQ control signal, a second current electrode of transistor <NUM> is connected to the VSS supply terminal, and a control electrode of transistor <NUM> is connected to a second terminal of filter circuit <NUM> at node HH. In this embodiment, the fourth filter circuit <NUM> includes a fourth resistor <NUM> and a fourth capacitor <NUM>. A first terminal of resistor <NUM> is connected at node FF, a second terminal of resistor <NUM> is connected to a first terminal of capacitor <NUM> at node HH, and a second terminal of capacitor <NUM> is connected at the VSS supply terminal. Control terminals of switches <NUM> and <NUM> are configured to receive the SH control signal.

In operation, the <NUM>-bit C2BQ control signals C2BQ_0 and C2BQ_1 and their respective complement signals C2BQ_0N and C2BQ_1N are received at the control electrodes of transistors <NUM>-<NUM>. When the SH control signal is at the first state (i.e., sample mode), switches <NUM>-<NUM> are closed allowing corresponding currents (e.g., I11 and I22) selected by way of the C2BQ control signals to propagate to the third and fourth current mirrors accordingly. For example, when C2BQ_0 is at a logic low and C2BQ_1 is at a logic low, the current generated for DIQ+ is substantially equal to I11+I22 and the current generated for DIQ- is substantially equal to <NUM>; when C2BQ_0 is at a logic high and C2BQ_1 is at a logic low, the current generated for DIQ+ is substantially equal to I22 and the current generated for DIQ- is substantially equal to I11; when C2BQ_0 is at a logic low and C2BQ_1 is at a logic high, the current generated for DIQ+ is substantially equal to I11 and the current generated for DIQ- is substantially equal to I22; and when C2BQ_0 is at a logic high and C2BQ_1 is at a logic high, the current generated for DIQ+ is substantially equal to <NUM> and the current generated for DIQ- is substantially equal to I11+I22. In this embodiment, the first state of the SH control signal may occur during inter-chirp time periods of the radar system. During these inter-chirp periods, the capacitors <NUM>-<NUM> of the filter circuits <NUM>-<NUM> are refreshed or charged to new values based on the C2BQ control signals.

When the SH control signal is at the second state (i.e., hold mode), switches <NUM>-<NUM> are open allowing charged values to be stored on the capacitors <NUM>-<NUM> of the filter circuits <NUM>-<NUM>. For example, values of the DIQ+ and DIQ- signal components are held based on the charge values of the capacitors <NUM>-<NUM>. In this embodiment, the second state of the SH control signal may occur during chirp time periods of the radar system. Because the DIQ+ and DIQ- signal components are held based on the charge values of the capacitors <NUM>-<NUM> during these chirp time periods, noise and power consumption are reduced.

<FIG> illustrates, in simplified block diagram form, an example phase rotator core implementation <NUM> of the circuit block <NUM> of <FIG> in accordance with an embodiment. The phase rotator core <NUM> is configured and arranged to receive the RFDI and RFDQ differential signal pairs, the DII and DIQ differential control signal pairs, and in turn, generate the output signal OUT. In this embodiment, the phase rotator core <NUM> includes multiplication mixer circuits <NUM> and <NUM> and summing circuit <NUM>.

A first input of mixer <NUM> is configured to receive the RFDI differential signal pair, a second input of mixer <NUM> is configured to receive the DII differential control signal pair, and an output of mixer <NUM> is configured to provide a first differential product signal labeled DPI. A first input of mixer <NUM> is configured to receive the RFDQ differential signal pair, a second input of mixer <NUM> is configured to receive the DIQ differential control signal pair, and an output of mixer <NUM> is configured to provide a second differential product signal labeled DPQ. A first input of mixer <NUM> is configured to receive the DPI differential signal pair, a second input of mixer <NUM> is configured to receive the DPQ differential signal pair, and an output of mixer <NUM> is configured to provide a summed differential output signal labeled OUT.

<FIG> illustrates, in simplified block diagram form, an example MASH implementation <NUM> corresponding to circuit blocks <NUM> and <NUM> of <FIG> in accordance with an embodiment. The MASH circuit block <NUM> is configured and arranged to receive a multi-bit (e.g., <NUM>-bit) control signal labeled MIN (e.g., corresponding to CTRLI and CRTLQ) at a first input, a MASH clock labeled MCLK at a second input, and in turn, generate a <NUM>-bit output control signal MOUT (e.g., corresponding to C2BI and C2BQ) at an output. In this embodiment, the MASH circuit block <NUM> includes a first sigma-delta modulator <NUM> labeled SDM1, a second sigma-delta modulator <NUM> labeled SDM2, a first filter circuit <NUM> labeled F1, a second filter circuit <NUM> labeled F2, and a combining circuit <NUM>.

A first input of the sigma-delta modulator <NUM> is configured to receive the MIN control signal (e.g., CTRLI, CRTLQ), a second input of the sigma-delta modulator <NUM> is configured to receive the MCLK clock signal, and in turn, a first converted signal labeled C1 is generated at a first output and a noise error signal labeled E1 is generated at a second output. A first input of filter circuit <NUM> is configured to receive the C1 signal, a second input of the filter circuit <NUM> is configured to receive the MCLK clock signal, and in turn, a first decimated signal labeled Q1 is generated at an output. In this embodiment, filter circuit <NUM> is characterized as a decimation filter having a transfer function of z^-<NUM>. A first input of the sigma-delta modulator <NUM> is configured to receive the E1 signal, a second input of the sigma-delta modulator <NUM> is configured to receive the MCLK clock signal, and in turn, a second converted signal labeled C2 is generated at an output. A first input of filter circuit <NUM> is configured to receive the C2 signal, a second input of the filter circuit <NUM> is configured to receive the MCLK clock signal, and in turn, a second decimated signal labeled Q2 is generated at an output. In this embodiment, filter circuit <NUM> is characterized as a decimation filter having a transfer function of <NUM>-z^-<NUM>. A first input of the combining circuit <NUM> is configured to receive the Q1 signal, a second input of the combining circuit <NUM> is configured to receive the Q2 signal, and in turn, generate the <NUM>-bit control signal MOUT (e.g., C2BI, C2BQ) at an output. In this embodiment, the Q2 signal is subtracted from the Q1 signal to generate the MOUT signal.

Generally, there is provided, a circuit including a phase rotator core having a first input coupled to receive a first radio frequency (RF) signal, a second input coupled to receive a first phase control signal, and an output for providing an output signal; a phase control block coupled to the phase rotator core, the phase control block comprising: a first transistor having a control electrode coupled to receive a first control signal; a second transistor having a control electrode coupled to receive a second control signal and a first current electrode coupled to a first current electrode of the first transistor; a third transistor having a control electrode and a first current electrode coupled to the first current electrodes of the first and second transistors; a first filter having first terminal coupled to the control electrode and the first current electrode of the third transistor; and a fourth transistor having a control electrode coupled to a second terminal of the first filter and a first current electrode coupled to the second input of the phase rotator core to provide the first phase control signal. The phase control block may further include a first current source having a first terminal coupled to a first voltage supply and a second terminal coupled to a second current electrode of the first transistor; and a second current source having a first terminal coupled to the first voltage supply and a second terminal coupled to a second current electrode of the second transistor. The first filter may include a first resistor having a first terminal coupled to the control electrode and the first current electrode of the third transistor and a second terminal coupled to the control electrode of the fourth transistor; and a first capacitor having a first terminal coupled to the second terminal of the first resistor and the control electrode of the fourth transistor. The phase control block further includes a first switch having a first terminal coupled to the first current electrodes of the first and second transistors, a second terminal coupled to the control electrode and the first current electrode of the third transistor, and a control terminal coupled to receive a third control signal. The first switch is configured to be closed based on a first state of the third control signal and open based on a second state of the third control signal. The phase control block may further include a multi-stage noise shaping (MASH) block coupled to provide the first control signal and the second control based on a main control signal. The phase control block may further include a fifth transistor having a control electrode coupled to receive a first complement signal, the first complement signal characterized as an inverted version of the first control signal; a sixth transistor having a control electrode and a first current electrode coupled to a first current electrode of the fifth transistors; a second filter having a first terminal coupled to the control electrode and the first current electrode of the sixth transistor; and a seventh transistor having a control electrode coupled to a second terminal of the second filter and a first current electrode coupled to a third input of the phase rotator core to provide a second phase control signal. The first phase control signal and the second phase control signal together may form a differential phase control signal, and wherein the second and third inputs of the phase rotator core together are characterized as a differential input for receiving the differential phase control signal. The phase control block may further include an eighth transistor having a control electrode coupled to receive a second complement signal and a first current electrode coupled to the first current electrode of the fifth transistor, the second complement signal characterized as an inverted version of the second control signal.

In another embodiment, there is provided, a circuit including a phase rotator core having a first input coupled to receive a first radio frequency (RF) signal, a second input coupled to receive a first phase control signal, and an output for providing an output signal; a phase control block coupled to the phase rotator core, the phase control block comprising: a first transistor having a control electrode coupled to receive a first control signal, a first current electrode, and a second current electrode; a second transistor having a control electrode coupled to receive a second control signal and a first current electrode coupled to the first current electrode of the first transistor; a first switch having a first terminal coupled to the first current electrodes of the first and second transistors, and a control terminal coupled to receive a third control signal; a third transistor having a control electrode and a first current electrode coupled to a second terminal of the first switch; a first filter having a first terminal coupled to the control electrode and the first current electrode of the third transistor; and a fourth transistor having a control electrode coupled to a second terminal of the first filter and a first current electrode coupled to the second input of the phase rotator core to provide the first phase control signal. The phase control block may further include a first current source having a first terminal coupled to a first voltage supply and a second terminal coupled to the second current electrode of the first transistor; and a second current source having a first terminal coupled to the first voltage supply and a second terminal coupled to a second current electrode of the second transistor. The phase control block may further include a first variable current source having a first terminal coupled to the first voltage supply and a second terminal coupled to the second current electrode of the first transistor. The first filter may include a first resistor having a first terminal coupled to the control electrode and the first current electrode of the third transistor and a second terminal coupled to the control electrode of the fourth transistor; and a first capacitor having a first terminal coupled to the second terminal of the first resistor and the control electrode of the fourth transistor. The first switch is configured to be closed during a sample phase of the phase control block and open during a hold phase of the phase control block. The phase control block may further include a multi-stage noise shaping (MASH) block coupled to provide the first control signal and the second control based on a main control signal. The phase control block may further include a fifth transistor having a control electrode coupled to receive a first complement signal and a first current electrode coupled to the second current electrode of the first transistor, the first complement signal characterized as an inverse of the first control signal; a second switch having a first terminal coupled to a first current electrode of the fifth transistor, and a control terminal coupled to receive the third control signal; a sixth transistor having a control electrode and a first current electrode coupled to a second terminal of the second switch; a second filter having a first terminal coupled to the control electrode and the first current electrode of the sixth transistor; and a seventh transistor having a control electrode coupled to a second terminal of the second filter and a first current electrode coupled to a third input of the phase rotator core to provide a second phase control signal. The first phase control signal and the second phase control signal together may form a differential phase control signal, and wherein the second and third inputs of the phase rotator core together are characterized as a differential input for receiving the differential phase control signal.

In yet another embodiment, there is provided, a circuit including a phase rotator core having a first input coupled to receive a first radio frequency (RF) signal, a second input coupled to receive a first phase control signal, and an output for providing an output signal; a phase control block coupled to the phase rotator core, the phase control block comprising: a first transistor having a control electrode coupled to receive a first control signal and a first current electrode coupled at a first node; a second transistor having a control electrode coupled to receive a second control signal and a first current electrode coupled at a second node, the second control signal a complement signal of the first control signal; a third transistor having a control electrode and a first current electrode coupled to the first current electrode of the first transistor; a first filter having first terminal coupled to the control electrode and the first current electrode of the third transistor; a fourth transistor having a control electrode coupled to a second terminal of the first filter and a first current electrode coupled to the second input of the phase rotator core to provide the first phase control signal; and a first current source having a first terminal coupled to a first voltage supply and a second terminal coupled to a second current electrode of the first transistor and a second current electrode of the second transistor. The phase control block may further include a first switch having a first terminal coupled to the first current electrode of the first transistor at the first node, a second terminal coupled to the control electrode and the first current electrode of the third transistor, and a control terminal coupled to receive a third control signal; and a second switch having a first terminal coupled to the first current electrode of the second transistor at the second node and a control terminal coupled to receive the third control signal. The first filter may include a first resistor having a first terminal coupled to the control electrode and the first current electrode of the third transistor at the first terminal of the first filter and a second terminal coupled to the control electrode of the fourth transistor at the second terminal of the first filter; and a first capacitor having a first terminal coupled to the second terminal of the first resistor and the control electrode of the fourth transistor.

By now it should be appreciated that there has been provided, a phase rotator control system including analog control signals generated by digital-to-analog converter (DAC) with embedded filter circuitry. A multi-stage noise shaping (MASH) circuit block provides a reduced set of digital control signals to the DAC circuitry. A sample-and-hold circuit arrangement within the DAC circuitry allows for low noise and power efficient operation of a radar system during chirp time periods, for example, and allows for new phase values to be seamlessly updated during inter-chirp time periods.

A phase rotator control circuit is provided. The phase rotator control circuit is coupled to a phase rotator core and includes a first set of transistors coupled to receive digital control signals. The first set of transistors is coupled to a second set of transistors configured and arranged to form a filtered current mirror. An output of the filtered current mirror is coupled to provide an analog phase control signal to the phase rotator core.

Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

The term "coupled," as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.

Claim 1:
A circuit comprising:
a phase rotator core (<NUM>) having a first input coupled to receive a first radio frequency (RF) signal, a second input coupled to receive a first phase control signal, and an output for providing an output signal;
a phase control block (<NUM>) coupled to the phase rotator core, the phase control block comprising:
a first transistor (<NUM>) having a control electrode coupled to receive a first control signal;
a second transistor (<NUM>) having a control electrode coupled to receive a second control signal and a first current electrode coupled to a first current electrode of the first transistor;
a third transistor (<NUM>) having a control electrode and a first current electrode coupled to the first current electrodes of the first and second transistors;
a first filter (<NUM>) having first terminal coupled to the control electrode and the first current electrode of the third transistor;
a fourth transistor (<NUM>) having a control electrode coupled to a second terminal of the first filter and a first current electrode coupled to the second input of the phase rotator core to provide the first phase control signal
characterized in that the phase control block is comprising:
a first switch (<NUM>) having a first terminal coupled to the first current electrodes of the first and second transistors (<NUM>, <NUM>), a second terminal coupled to the control electrode and the first current electrode of the third transistor (<NUM>), and a control terminal coupled to receive a third control signal;
wherein the first switch (<NUM>) is configured to be:
closed based on a first state of the third control signal in order to define a sample mode; and
open based on a second state of the third control signal in order to define a hold mode.