Patent Description:
Many typical radio frequency receivers comprise functionality to down-convert a received radio frequency signal (e.g., by application of mixing) and to perform analog-to-digital conversion of the received radio frequency signal (e.g., by application of a successive approximation register analog-to-digital converter - SAR ADC).

If down-conversion is performed in the digital domain, the analog-to-digital converter (ADC) typically needs to have a relatively large bandwidth, which may entail high ADC complexity and/or inefficient use of the ADC resources (e.g., ADC hardware such as circuitry and/or subsystems of the ADC) and/or high power consumption.

If down-conversion is performed in the analog domain, the down-converter can be implemented with a harmonic rejection mixer (HRM) or corresponding functionality, which may entail high down-conversion complexity and/or high power consumption.

Therefore, there is a need for alternative approaches for down-conversion and analog-to-digital conversion (e.g., for radio frequency receivers).

The invention is defined by the appended independent claims and the preferred embodiments are defined by the appended dependent claims.

An advantage of the invention is that alternative approaches are provided for down-conversion and analog-to-digital conversion.

An advantage of the invention is that combined down-conversion and analog-to-digital conversion is achieved.

An advantage of the invention is that the functionality of a harmonic rejection mixer (HRM) is embedded within a SAR ADC.

An advantage of the invention is that the complexity of down-conversion and/or analog-to-digital conversion (i.e., individual complexity and/or combined complexity) is improved (e.g., reduced) compared to other approaches for down-conversion and analog-to-digital conversion.

An advantage of the invention is that the power consumption of down-conversion and/or analog-to-digital conversion (i.e., individual complexity and/or combined complexity) is improved (e.g., reduced) compared to other approaches for down-conversion and analog-to-digital conversion.

An advantage of the invention is that the ADC resources are more efficiently used compared to other approaches for down-conversion and analog-to-digital conversion.

An advantage of the invention is that, since mixing is inherently performed on analog samples so that the ADC functionality acts on down-converted signal material, a noise shaping (NS) functionality may be included for the SAR ADC. Application of NS can reduce the ADC resolution requirement and/or increase the ADC accuracy, compared to other ADC approaches.

As already mentioned above, typical radio frequency receivers comprise functionality to down-convert a received radio frequency signal and to perform analog-to-digital conversion of the received radio frequency signal.

The analog-to-digital converter (ADC) typically needs to have a relatively large bandwidth when down-conversion is performed in the digital domain.

For example, using a conventional ADC to convert an intermediate frequency (IF) signal may be very inefficient because - since the IF signal typically has a bandwidth which corresponds to a small fraction of the IF frequency - the ADC bandwidth would typically need to have a Nyquist frequency which is much larger than the IF frequency. Furthermore, a conventional ADC would typically provide roughly the same signal-to-noise ratio (SNR) across the entire frequency range up to the Nyquist frequency of the ADC, while only a small fraction of that spectrum is used by the signal under consideration.

When down-conversion is performed in the analog domain, the down-converter typically needs to be a harmonic rejection mixer (HRM) or implement corresponding functionality, which may entail high down-conversion complexity and/or high power consumption.

For example, a HRM may require additional circuitry (buffers and/or amplifiers) for terminating the mixer ports to reach the desired level of harmonic rejection.

In the following, embodiments will be described where alternative approaches are provided for down-conversion and analog-to-digital conversion.

Some embodiments suggest that a SAR ADC (e.g., a noise shaping, NS, ADC) is combined with the HRM function.

Some embodiments are based on the observation that a SAR ADC provides a highly matched system (the capacitive digital-to-analog converter, C-DAC, of the SAR ADC) that can double as an HRM. Thus, the linearity of the C-DAC may be used for HRM functionality as well as for ADC functionality.

In some embodiments, down-conversion and analog-to-digital conversion are combined by manipulation of SAR ADC inputs.

These approaches may have one or more of the following (or other) advantages: relatively low complexity, relatively low power consumption, and efficient use of ADC resources.

Even though embodiments are described herein by exemplification using differential architectures, it should be noted that corresponding non-differential (single-ended) architectures may be equally applicable for some embodiments.

Generally, all switches described herein may be seen as exemplifications of selectors, and it should be noted that a selector may be implemented in other ways that through a switch.

<FIG> schematically illustrates an example SAR ADC <NUM>, which may be used as a starting point for exemplification of some embodiments. The example SAR ADC <NUM> is based on capacitive digital-to-analog converter (C-DAC) technology; a well proven ADC technique that can operate at high sampling rates, is power efficient, and scales well with aggressively scaled complementary metal oxide semiconductor (CMOS) technologies. The variant of C-DAC-based SAR ADC shown in <FIG> is based on so-called bottom-plate sampling.

It should be noted that there are various ways to implement a C-DAC-based SAR ADC, all of which may be applicable for some embodiments. Generally, a C-DAC-based SAR ADC has one or more capacitive digital-to-analog converters, each of which comprises a capacitor bank (e.g., an array of capacitors) that doubles as sampling capacitor.

The SAR ADC <NUM> is configured to receive an analog input signal and provide a digital output signal as is well known in the art.

The signals used by the SAR ADC <NUM> comprises a common mode voltage signal (Vcm) <NUM>, the analog input signal (Vip) <NUM> and an opposed version of the analog input signal (Vim) <NUM>, a first reference voltage signal (Vref_p) <NUM> and a second reference voltage signal (Vref_m) <NUM>.

Generally, the opposed version of the analog input signal has a voltage that is opposite to that of the analog input signal in relation to a pre-determined voltage level. For example, the opposed version of the analog input signal may be a reversed polarity version of the analog input signal. Alternatively or additionally, the analog input signal and the opposed version of the analog input signal may be centered around Vcm (i.e., Vip = Vcm + b and Vim = Vcm - b).

Generally, the analog input signal and the opposed version of the analog input signal together form a differential signal.

Generally, the first reference voltage signal has a higher voltage than the second reference voltage signal. For example, the second reference voltage signal may be a reversed polarity version of the first reference voltage signal. Alternatively or additionally, the first and second reference voltage signals may be centered around Vcm (i.e., Vref_p = Vcm + c and Vref_m = Vcm - c).

Generally, the first and second reference voltage signals together form a differential signal.

The SAR ADC comprises two capacitor banks <NUM>, <NUM>. Typically, each capacitor of the capacitor banks <NUM>, <NUM> has a capacitance which equals a base capacitance (C) multiplied by two to the power of a non-negative integer (i.e., <NUM>xC, <MAT>). Also typically, the capacitors of a capacitor bank have different capacitances; including the base capacitance and successively increasing by a factor of two. Thus, the capacitors <NUM>, <NUM>,. , <NUM> of the capacitor bank <NUM> may have the capacitances C, 2C,. , <NUM>xC (e.g., C, 2C,. , 32C, when the capacitor bank comprises six capacitors; i.e., providing a six-bit ADC), and correspondingly for the capacitors <NUM>, <NUM>,. , <NUM> of the capacitor bank <NUM>.

As is well known in the art, the capacitor banks may be used for successively providing a plurality of (respective) signal levels <NUM>, <NUM> based on a sample value of the analog input signal, wherein each provided signal level is an indicator for a corresponding bit in a corresponding sample of the digital output signal <NUM>. The SAR ADC <NUM> comprises a comparator <NUM> configured to determine a bit value <NUM> of the digital output signal <NUM> based on the signal levels <NUM>, <NUM> provided by the capacitor banks.

The SAR ADC also comprises controlling circuitry (e.g., SAR logic) <NUM> configured to cause the capacitor banks <NUM>, <NUM> to provide the plurality of signal levels <NUM>, <NUM> representing a sample value of the analog input signal. This may be achieved by providing control signals <NUM>, <NUM> to switching arrays <NUM>, <NUM>, wherein each switching array controls the charging of the capacitors of a corresponding one of the capacitor banks <NUM>, <NUM>.

The SAR ADC <NUM> is fully differential, so the operation of the two sides (upper and lower part of <FIG>) are complementary, as will be explained below.

At the sampling phase, the analog input signal <NUM> is sampled on the capacitor bank <NUM>. This is achieved by connecting the bottom plate (upper capacitor side in <FIG>) of the capacitors <NUM>, <NUM>,. , <NUM> to Vip <NUM> and the top plate (lower capacitor side in <FIG>) of the capacitors <NUM>, <NUM>,. , <NUM> to the common mode voltage signal Vcm <NUM>. Connecting the bottom plate of the capacitors <NUM>, <NUM>,. , <NUM> to Vip <NUM> is achieved by closing - in the switching array <NUM> - the leftmost switch for each of the capacitors <NUM>, <NUM>,. , <NUM> and leaving the other switches of the switching array <NUM> open. Connecting the top plate of the capacitors <NUM>, <NUM>,. , <NUM> to the common mode voltage signal Vcm <NUM> is achieved by closing the switch <NUM>.

Also at the sampling phase, the opposed version of the analog input signal <NUM> is sampled on the capacitor bank <NUM>. This is achieved by connecting the bottom plate (lower capacitor side in <FIG>) of the capacitors <NUM>, <NUM>,. , <NUM> to Vim <NUM> and the top plate (upper capacitor side in <FIG>) of the capacitors <NUM>, <NUM>,. , <NUM> to the common mode voltage signal Vcm <NUM>. Connecting the bottom plate of the capacitors <NUM>, <NUM>,. , <NUM> to Vim <NUM> is achieved by closing - in the switching array <NUM> - the leftmost switch for each of the capacitors <NUM>, <NUM>,. , <NUM> and leaving the other switches of the switching array <NUM> open. Connecting the top plate of the capacitors <NUM>, <NUM>,. , <NUM> to the common mode voltage signal Vcm <NUM> is achieved by closing the switch <NUM>.

In a following stage (conversion phase), the bottom plate of the capacitors <NUM>, <NUM>,. , <NUM> are switched to Vcm <NUM> while the top plates are disconnected from Vcm <NUM>. Connecting the bottom plate of the capacitors <NUM>, <NUM>,. , <NUM> to Vcm <NUM> is achieved by closing - in the switching array <NUM> - the rightmost switch for each of the capacitors <NUM>, <NUM>,. , <NUM> and leaving the other switches of the switching array <NUM> open. Disconnecting the top plate of the capacitors <NUM>, <NUM>,. , <NUM> from Vcm <NUM> is achieved by opening the switch <NUM>. Thereby, the analog input signal sample is applied to the comparator input, resulting in a voltage Vcm - b = 2Vcm - Vip at the positive input <NUM> of the comparator when Vip = Vcm + b.

Also in the following stage, the bottom plate of the capacitors <NUM>, <NUM>,. , <NUM> are switched to Vcm <NUM> while the top plates are disconnected from Vcm <NUM>. Connecting the bottom plate of the capacitors <NUM>, <NUM>,. , <NUM> to Vcm <NUM> is achieved by closing - in the switching array <NUM> - the rightmost switch for each of the capacitors <NUM>, <NUM>,. , <NUM> and leaving the other switches of the switching array <NUM> open. Disconnecting the top plate of the capacitors <NUM>, <NUM>,. , <NUM> from Vcm <NUM> is achieved by opening the switch <NUM>. Thereby, the opposed version of the analog input signal sample is applied to the comparator input, resulting in a voltage Vcm + b = <NUM>Vcm - Vim at the negative input <NUM> of the comparator when Vim = Vcm - b.

Then, the comparator <NUM> is triggered and outputs a decision <NUM> based on the differential input <NUM>, <NUM>. Typically, the decision is a bit decision. The bit decision may be "<NUM>" when the differential input is positive, and the bit decision may be "<NUM>" when the differential input is negative (a differential input of zero may be mapped to either "<NUM>" or "<NUM>" in various implementations). The first comparator decision for an analog input signal sample may correspond to a most significant bit (MSB) for a digital representation <NUM> of the analog input signal sample value.

After each comparator decision, the bottom plate of one of the capacitors <NUM>, <NUM>,. , <NUM> are switched to either Vref_p <NUM> or Vref_m <NUM> while the top plates stay disconnected from Vcm <NUM>. Connecting the bottom plate of one of the capacitors <NUM>, <NUM>,. , <NUM> to either Vref_p <NUM> or Vref_m <NUM> is achieved by closing - in the switching array <NUM> - the third or second switch from the right for the relevant one of the capacitors <NUM>, <NUM>,. , <NUM> and leaving the other switches of the switching array <NUM> open. Thereby, the voltage manifested at the positive input <NUM> of the comparator is changed accordingly.

Correspondingly after each comparator decision, the bottom plate of one of the capacitors <NUM>, <NUM>,. , <NUM> are switched to either Vref_m <NUM> or Vref_p <NUM> while the top plates stay disconnected from Vcm <NUM>. Connecting the bottom plate of one of the capacitors <NUM>, <NUM>,. , <NUM> to either Vref_m <NUM> or Vref_p <NUM> is achieved by closing - in the switching array <NUM> - the third or second switch from the left for the relevant one of the capacitors <NUM>, <NUM>,. , <NUM> and leaving the other switches of the switching array <NUM> open. Thereby, the voltage manifested at the negative input <NUM> of the comparator is changed accordingly.

Thus, the differential input of the comparator <NUM> has changed, and the comparator <NUM> is triggered again and outputs a new decision <NUM> based on the differential input <NUM>, <NUM>. The second comparator decision for an analog input signal sample may correspond to the bit following the MSB (i.e., MSB-<NUM>) for a digital representation <NUM> of the analog input signal sample value.

The process of alternatingly connecting bottom plate(s) of relevant capacitor(s) to Vref_m or Vref_p and triggering the comparator to take a decision is iterated until a last decision has been taken for the analog input signal sample; typically corresponding to a least significant bit (LSB) for a digital representation <NUM> of the analog input signal sample value. Then, the capacitor banks may be reset and a new sample of the analog input signal may be loaded for processing.

<FIG> schematically illustrates an example SAR ADC <NUM> according to some embodiments, which is based on the SAR ADC <NUM> of <FIG>.

In similarity with <FIG>, the SAR ADC <NUM> is configured to receive an analog input signal and provide a digital output signal. However, while the SAR ADC of Figure <NUM> was configured to provide the digital output signal <NUM> as a sampled and quantized representation of the analog input signal, the SAR ADC <NUM> is configured to provide - for each sample of the analog input signal -the digital output signal as a quantized representation of a scaled version of the analog input signal sample. Thus, each sample of the digital output signal is a quantized representation of the corresponding sample of the dynamically scaled version of the sample value of the analog input signal.

The scaling is achieved by a modification and control of the switching arrays, as elaborated on in the following.

By dynamically controlling the scaling and selection of suitable scaling values, the SAR ADC <NUM> may be configured to provide the digital output signal as a sampled and quantized representation of an analog input signal mixed with an oscillator signal. Thus, a mixing functionality is embedded in the SAR ADC <NUM>.

In similarity with <FIG>, the signals used by the SAR ADC <NUM> comprises a common mode voltage signal (Vcm) <NUM>, the analog input signal (Vip) <NUM> and an opposed version of the analog input signal (Vim) <NUM>, a first reference voltage signal (Vref_p) <NUM> and a second reference voltage signal (Vref_m) <NUM>.

Also in similarity with <FIG>, the SAR ADC <NUM> comprises two capacitor banks <NUM>, <NUM>. The capacitor banks <NUM>, <NUM> are completely corresponding to the capacitor banks <NUM>, <NUM> of <FIG>. Thus, the capacitors <NUM>,. , <NUM> of the capacitor bank <NUM> may have the capacitances C, 2C,. , <NUM>xC, and correspondingly for the capacitors <NUM>,. , <NUM> of the capacitor bank <NUM>. The SAR ADC <NUM> is fully differential, so the operation of the two sides (upper and lower part of <FIG>) are complementary, similarly to the previous explanation in connection with <FIG>.

Also in similarity with <FIG>, the SAR ADC <NUM> comprises a comparator <NUM> configured to determine a bit value <NUM> of the digital output signal <NUM> based on the signal levels <NUM>, <NUM> provided by the capacitor banks.

Further in similarity with <FIG>, the SAR ADC <NUM> also comprises controlling circuitry <NUM> configured to cause the capacitor banks <NUM>, <NUM> to provide a plurality of signal levels based on the analog input signal. In contrast to <FIG>, the controlling circuitry <NUM> is configured to cause the capacitor banks <NUM>, <NUM> to provide the plurality of signal levels representing a dynamically scaled version of the sample value of the analog input signal.

This may be achieved by providing control signals <NUM>, <NUM> to switching arrays <NUM>, <NUM>, wherein each switching array controls the charging of the capacitors of a corresponding one of the capacitor banks <NUM>, <NUM>. Notably, the switching arrays <NUM>, <NUM> differ from the switching arrays of <FIG> in that the leftmost switch <NUM>,. , <NUM> for each of the capacitors <NUM>,. , <NUM>; <NUM>,. , <NUM> is operable to supply either of the analog input signal (Vip) <NUM> and the opposed version of the analog input signal (Vim) <NUM> to its corresponding capacitor.

The scaling of the sample value of the analog input signal is achieved by letting a digital representation of a scaling value s control - at the sampling phase -the positions of the leftmost switches for each of the capacitors.

For example, if the scaling value s can be represented as <NUM>, all of the switches <NUM>,. , <NUM> may be set such that the bottom plate of all of the capacitors <NUM>,. , <NUM> is connected to Vip <NUM>, and all of the corresponding switches in the switching array <NUM> may be set such that the bottom plate of all of the capacitors <NUM>,. , <NUM> is connected to Vim <NUM>.

Then, if the scaling value s can be represented as <NUM>, the switches <NUM>,. , <NUM> may be set such that the bottom plate of all of the capacitors <NUM>,. , <NUM> is connected to Vip <NUM> except for the capacitor <NUM> which is connected to Vim <NUM>, and all of the corresponding switches in the switching array <NUM> may be set such that the bottom plate of all of the capacitors <NUM>,. , <NUM> is connected to Vim <NUM>, except for the capacitor <NUM> which is connected to Vip <NUM>.

Corresponding settings for the switching arrays may be applicable for other scaling value representations.

Thus, the controlling circuitry <NUM> is configured to control a respective selector (e.g., switches <NUM>,. , <NUM>) of each capacitor of the capacitor banks to charge the capacitor using either the sample value of the analog input signal Vip <NUM> or the sample value of the opposed version of the analog input signal Vim <NUM>, such that a setting of the respective selectors corresponds to a digital representation of the scaling value s for the sample value of the analog input signal.

In some embodiments, the scaling values are selected as digital representations of samples of an oscillator signal (e.g., a sinusoid signal). Typically, the sampling times correspond to sampling times of the analog input signal. Preferably, the oscillator signal has a frequency which satisfies the Nyquist limit in relation to the sampling frequency (i.e., a collection of sample values of the oscillator signal comprises at least three distinct values).

Then, the dynamically scaled version of the sample value of the analog input signal represents a sample of the analog input signal multiplied by a sample value of the oscillator signal; thereby providing mixing of the analog input signal with the oscillator signal. Thus, each sample of the digital output signal is a quantized representation of a corresponding sample of the analog input signal mixed with the oscillator signal. It may be noted that the mixing functionality is applied for analog domain samples (before quantization), which might be beneficial for the accuracy of the mixing operation.

At the sampling phase, the dynamically scaled version of the analog input signal is sampled on the capacitor bank <NUM>. This is achieved by connecting the bottom plate (upper capacitor side in <FIG>) of the capacitors <NUM>,. , <NUM> to either Vip <NUM> or Vim <NUM> - depending on the applicable scaling value - and the top plate (lower capacitor side in <FIG>) of the capacitors <NUM>,. , <NUM> to the common mode voltage signal Vcm <NUM>. Connecting the bottom plate of the capacitors <NUM>,. , <NUM> to either Vip <NUM> or Vim <NUM> is achieved by controlling the positions of switches <NUM>,. , <NUM> for each of the capacitors <NUM>,. , <NUM> and leaving the other switches of the switching array <NUM> open. Connecting the top plate of the capacitors <NUM>,. , <NUM> to the common mode voltage signal Vcm <NUM> is achieved by closing the switch <NUM>.

Also at the sampling phase, the dynamically scaled version of the opposed version of the analog input signal is sampled on the capacitor bank <NUM>. This is achieved by connecting the bottom plate (lower capacitor side in <FIG>) of the capacitors <NUM>,. , <NUM> to either Vip <NUM> or Vim <NUM> - depending on the applicable scaling value (flipping the polarity for each capacitor compared to the capacitor bank <NUM>) - and the top plate (upper capacitor side in <FIG>) of the capacitors <NUM>,. , <NUM> to the common mode voltage signal Vcm <NUM>. Connecting the bottom plate of the capacitors <NUM>,. , <NUM> to either Vip <NUM> or Vim <NUM> is achieved by controlling - in the switching array <NUM> - the position of the leftmost switch for each of the capacitors <NUM>,. , <NUM> and leaving the other switches of the switching array <NUM> open. Connecting the top plate of the capacitors <NUM>,. , <NUM> to the common mode voltage signal Vcm <NUM> is achieved by closing the switch <NUM>.

In a following stage (conversion phase), the bottom plate of the capacitors <NUM>,. , <NUM> are switched to Vcm <NUM> while the top plates are disconnected from Vcm<NUM>. Connecting the bottom plate of the capacitors <NUM>,. , <NUM> to Vcm <NUM> is achieved by closing - in the switching array <NUM> - the rightmost switch for each of the capacitors <NUM>,. , <NUM> and leaving the other switches of the switching array <NUM> open. Disconnecting the top plate of the capacitors <NUM>,. , <NUM> from Vcm <NUM> is achieved by opening the switch <NUM>. Thereby, the scaled analog input signal sample is applied to the comparator input, resulting in a voltage Vcm - sb = Vcm - s(Vip - Vcm) at the positive input <NUM> of the comparator when Vip = Vcm + b.

Also in the following stage, the bottom plate of the capacitors <NUM>,. , <NUM> are switched to Vcm <NUM> while the top plates are disconnected from Vcm <NUM>. Connecting the bottom plate of the capacitors <NUM>,. , <NUM> to Vcm <NUM> is achieved by closing - in the switching array <NUM> - the rightmost switch for each of the capacitors <NUM>,. , <NUM> and leaving the other switches of the switching array <NUM> open. Disconnecting the top plate of the capacitors <NUM>,. , <NUM> from Vcm <NUM> is achieved by opening the switch <NUM>. Thereby, the scaled opposed version of the analog input signal sample is applied to the comparator input, resulting in a voltage Vcm + sb = Vcm - s(Vim - Vcm) at the negative input <NUM> of the comparator when Vim = Vcm - b.

Then, the comparator <NUM> is triggered and outputs a decision <NUM> based on the differential input <NUM>, <NUM>, in the same manner as explained above in connection with <FIG>.

After each comparator decision, the bottom plate of one of the capacitors <NUM>,. , <NUM> are switched to either Vref_p <NUM> or Vref_m <NUM> while the top plates stay disconnected from Vcm <NUM>.

Connecting the bottom plate of one of the capacitors <NUM>,. , <NUM> to either Vref_p <NUM> or Vref_m <NUM> is achieved by closing - in the switching array <NUM> - the third or second switch from the right for the relevant one of the capacitors <NUM>,. , <NUM> and leaving the other switches of the switching array <NUM> open. Thereby, the voltage manifested at the positive input <NUM> of the comparator is changed accordingly.

Correspondingly after each comparator decision, the bottom plate of one of the capacitors <NUM>,. , <NUM> are switched to either Vref_m <NUM> or Vref_p <NUM> while the top plates stay disconnected from Vcm <NUM>. Connecting the bottom plate of one of the capacitors <NUM>,. , <NUM> to either Vref_m <NUM> or Vref_p <NUM> is achieved by closing - in the switching array <NUM> - the third or second switch from the left for the relevant one of the capacitors <NUM>,. , <NUM> and leaving the other switches of the switching array <NUM> open. Thereby, the voltage manifested at the negative input <NUM> of the comparator is changed accordingly.

Then, the comparator <NUM> is triggered again and outputs a new decision <NUM> based on the differential input <NUM>, <NUM>, and the process of alternatingly connecting bottom plate(s) of relevant capacitor(s) to Vref_m or Vref_p and triggering the comparator to take a decision is iterated until a last decision has been taken for the analog input signal sample, in the same manner as explained above in connection with <FIG>. Then, the capacitor banks may be reset and a new dynamically scaled sample of the analog input signal may be loaded for processing.

If it is desirable to be able to represent a zero-valued dynamically scaled sample of the analog input signal (i.e., scaling value and/or analog input signal sample value equal to zero), one suitable approach comprises using an additional capacitor <NUM>, <NUM> for each of the capacitor banks <NUM>, <NUM>. Typically, each of the additional capacitors <NUM>, <NUM> has the base capacitance (C) of the corresponding capacitor bank.

A purpose of the additional capacitors is to shift the quantization levels of the scaling (e.g., by shifting the grid of quantization levels) such that a particular quantization level represents the zero-valued dynamically scaled sample of the analog input signal. This may be achieved by controlling the additional capacitors <NUM>, <NUM> such that they bias (i.e., shift) the scaling of the sample value of the analog input signal.

At the sampling phase, Vim <NUM> is sampled on the additional capacitor <NUM> and Vip <NUM> is sampled on the additional capacitor <NUM>. This is achieved by connecting the bottom plate (upper capacitor side in <FIG>) of the capacitor <NUM> to Vim <NUM> and the top plate (lower capacitor side in <FIG>) of the capacitor <NUM> to the common mode voltage signal Vcm <NUM>, and by connecting the bottom plate (lower capacitor side in <FIG>) of the capacitor <NUM> to Vip <NUM> and the top plate (upper capacitor side in <FIG>) of the capacitor <NUM> to the common mode voltage signal Vcm <NUM>. Connecting the bottom plate of the capacitors <NUM>, <NUM> to Vim <NUM> and Vip <NUM>, respectively, is achieved by closing the switch <NUM> for the capacitor <NUM> (and correspondingly for the capacitor <NUM>), and leaving the other switches for the capacitors <NUM>, <NUM> open. Connecting the top plate of the capacitors <NUM>, <NUM> to the common mode voltage signal Vcm <NUM> is achieved by closing the switch <NUM>.

Thus, the controlling circuitry is configured to control selectors (e.g., switches <NUM>) of the additional capacitors to charge the additional capacitors <NUM>, <NUM> using either the sample value of the analog input signal Vip <NUM> or the sample value of the opposed version of the analog input signal Vim <NUM>.

During the following stages (conversion phase; alternatingly connecting bottom plate(s) of relevant capacitor(s) of the capacitor banks to Vref_m or Vref_p and triggering the comparator to take a decision), the bottom plate of the capacitors <NUM>, <NUM> are switched to Vcm <NUM> while the top plates are disconnected from Vcm <NUM>. Connecting the bottom plate of the capacitors <NUM>, <NUM> to Vcm <NUM> is achieved by closing the rightmost switch for each of the capacitors <NUM>, <NUM> and leaving the other switches of the capacitors <NUM>, <NUM> open. Disconnecting the top plate of the capacitors <NUM>, <NUM> from Vcm <NUM> is achieved by opening the switch <NUM>.

By application of the additional capacitors as described above, the voltage at the positive input <NUM> of the comparator becomes Vcm - (s - β)(Vip - Vcm) instead of Vcm - s(Vip - Vcm) for the first readout (MSB), and the voltage at the negative input <NUM> of the comparator becomes Vcm - (s - β)(Vim - Vcm) instead of Vcm - s(Vim - Vcm). Thus, the scaling used for providing the signal levels <NUM>, <NUM> to the comparator <NUM> are shifted, and the differential input to the comparator is changed by <NUM>β(Vip - Vim), which enables inclusion of a zero-values sample among the quantization levels.

The parameter β is proportional to the size of the additional capacitors <NUM>, <NUM>. For example, for a N-bit binary-scaled SAR ADC, the parameter may be defined as β = α/<NUM>N, where α represents a proportionality constant.

For example, a scaling value of +<NUM> may be represented by <NUM> (assuming a <NUM>-bit ADC), the switches <NUM>,. , <NUM> are connected - respectively - to <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and the charge of the capacitors <NUM>,. , <NUM> and the additional capacitor <NUM> will correspond to <NUM>Vip + <NUM>Vim + Vim = <NUM>Vip, for Vim = -Vip, where <NUM>Vip is due to the capacitors connected to <NUM>, <NUM>Vim is due to the capacitors connected to <NUM>, and Vim is due to the additional capacitor.

Thus, according to some embodiments, one or more additional capacitor is introduced with reduced switching capabilities compared to the capacitors of the capacitor bank(s), which are used as both sampling capacitors and DAC capacitors.

It should be noted that the additional capacitors <NUM>, <NUM> are optional and may not be present according to some embodiments.

In some embodiments, the SAR ADC <NUM> may be operable in either a mixing mode or a non-mixing mode. The mixing mode may be achieved by operating the SAR ADC as described above, while the non-mixing mode may be achieved by application of a static (i.e., non-dynamic, not differing between samples) scaling value.

If there are additional capacitors <NUM>, <NUM>, the non-mixing mode may comprise leaving them in operation to shift the scaling of the sample value of the analog input signal, as described above, or the non-mixing mode may comprise statically (i.e., at the sampling phase as well as during the conversion phase) connecting the bottom plate of the capacitors <NUM>, <NUM> to Vcm <NUM>. Connecting the bottom plate of the capacitors <NUM>, <NUM> to Vcm <NUM> is achieved by closing the rightmost switch for each of the capacitors <NUM>, <NUM> and leaving the other switches of the capacitors <NUM>, <NUM> open.

Thus, according to some embodiments, the C-DAC weights of a SAR ADC, which are typically designed to be well matched, are reused for performing harmonic rejection mixing as part of the sampling phase of the SAR ADC. Different mixing frequencies may be obtained by changing the oversampling rate of the equivalent oscillator frequency and/or by changing the sampling rate of the SAR ADC.

Additional capacitor(s) may be added for activation during sampling, according to some embodiments. The additional capacitor(s) are not used in the conversion phase. The additional capacitor(s) shift the grid of quantization levels, which may, for example, be used to enable a suitable representation of a sinusoidal sampling gain sequence to ensure efficient harmonic rejection.

Combining the technique according to some embodiments with noise shaping in the SAR ADC may further improve the effective resolution without addition of more cycles in the SAR ADC conversion phase.

<FIG> schematically illustrates some example control signal generators according to some embodiments.

In part (a) of <FIG>, a binary code generator <NUM> is presented with control signal outputs <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, which output a collection bits when trigged by a sampling signal <NUM>. The collection of bits of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may correspond to the scaling value and may be used for controlling the position of switches <NUM>,. , <NUM> (and correspondingly for the switching array <NUM>) at the sampling phase. For example, the bit of <NUM> may control the switch <NUM>, and the bit of <NUM> may be used to control the switch <NUM>; and correspondingly for the bits and switches there between. If a capacitor bank has another number of capacitors than six, the size of the collection of bits (i.e., the number of control signals <NUM>,. , <NUM>) may be adjusted accordingly.

In part (b) of <FIG>, a possible implementation of using a scaling bit <NUM> (e.g., a bit from any of the outputs <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) to control a corresponding one of the switches <NUM>,. , <NUM> of the switching array <NUM>, represented by the switch <NUM> in part (b) of <FIG>.

When the value of the scaling bit <NUM> is "<NUM>" and the AND-gates <NUM>, <NUM> are triggered by the sampling signal <NUM>, the output <NUM> of the AND-gate <NUM> is "<NUM>" and the output <NUM> of the AND-gate <NUM> is "<NUM>". Thereby, the switch <NUM> is disconnected from the analog input signal Vip <NUM> and connected to the opposed version of the analog input signal Vim <NUM>.

When the value of the scaling bit <NUM> is "<NUM>" and the AND-gates <NUM>, <NUM> are triggered by the sampling signal <NUM>, the output <NUM> of the AND-gate <NUM> is "<NUM>" and the output <NUM> of the AND-gate <NUM> is "<NUM>". Thereby, the switch <NUM> is connected to the analog input signal Vip <NUM> and disconnected from the opposed version of the analog input signal Vim <NUM>.

To control the switches of switching array <NUM>, the corresponding arrangement may be used with <NUM> and <NUM> interchanged (or - equivalently - with <NUM> and <NUM> interchanged).

Thus, the control signals <NUM>,. , <NUM> may be used to connect each capacitor of the capacitor bank(s) to either of the analog input signal and the opposed version of the analog input signal by gating an asynchronous sampling signal <NUM> (which may, for example, come from the SAR logic <NUM>) and the binary codes which are generated by a binary code generator block <NUM>.

<FIG> illustrates example control signals according to some embodiments, in the form of a timing diagram. The signal <NUM> represents a sampling signal (compare with the sampling signal <NUM>, <NUM> of <FIG>). The signals <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may represent a dynamically changing scaling value and may be used for controlling the position of switches <NUM>,. , <NUM> (and correspondingly for the switching array <NUM>) at the sampling phase. The signals <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may, for example, correspond to the collection of bits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> in part (a) of <FIG>. If a capacitor bank has another number of capacitors than six, the number of signals <NUM>,. , <NUM> may be adjusted accordingly. The particular example illustrated in <FIG> corresponds to the following scaling values (e.g., sample values of a sinusoid signal):.

The scaling values of the table above exemplify a sampling gain varying in relation to a sinusoid signal (e.g., a local oscillator, LO, signal) with frequency fLO and sampled Ns times per period (i.e., a sampling frequency of fLONs; equal to the sampling rate of the SAR ADC). The ideal scaling values <MAT>, where G is largest coefficient value are quantized to the scaling values of the above table (i.e., possible scaling values are restricted by the sampling gain levels available from the capacitor array in the SAR ADC). To find quantized scaling values suitable for providing efficient harmonic rejection, both ϕ and G may be swept in search for configurations that fulfill HR requirements under consideration.

By applying the scaling values to the SAR ADC input signal as explained above (e.g., in a discrete time sequence synchronously aligned with the SAR ADC sampling), a frequency translation fLO of the SAR ADC input signal is synthesized.

Part (a) of <FIG> illustrates an overview of the SAR ADC <NUM>. Reference numbers of <FIG> that have corresponding reference numbers in <FIG> are not elaborated on further. It should be understood that the description in connection with <FIG> of the features corresponding to such reference numbers is applicable for <FIG> as well.

In contrast to <FIG>, the SAR ADC <NUM> comprises noise shaping networks <NUM>, <NUM> configured to provide an integration <NUM>, <NUM> of the signal levels <NUM>, <NUM> provided by the capacitor bank <NUM>, <NUM>. The integration is provided for adjustment of the digital output signal <NUM>.

The SAR ADC <NUM> comprises a comparator <NUM> configured to determine a bit value <NUM> of the digital output signal <NUM> based on the signal levels <NUM>, <NUM> provided by the capacitor banks <NUM>, <NUM>; but also based on the integrations <NUM>, <NUM> provided by the noise shaping networks <NUM>, <NUM>.

Part (b) of <FIG> illustrates one example implementation of the noise shaping network <NUM>. The other noise shaping network <NUM> may be implemented in a corresponding manner. Part (c) of <FIG> shows a timing diagram comprising a sampling signal <NUM> (compare with sampling signals <NUM>, <NUM> of <FIG> and <NUM> of <FIG>) with period <NUM>, a comparator trigger signal <NUM>, and control signals <NUM>, <NUM> for the switches <NUM>, <NUM> of the noise shaping networks <NUM>.

A sampling period starts with the operation as described for a sample in connection with <FIG>. The switch <NUM> is controlled by the sampling signal <NUM> and is closed at the sampling phase. This will discharge the capacitor <NUM>.

After the conversion cycles, indicated by the multiple pulses of the comparator trigger signal <NUM>, a residue voltage Vres remains in the capacitor bank <NUM>. The switch <NUM> is subsequently closed as illustrated by <NUM>. While <NUM> is closed, the capacitor <NUM> with capacitance CNS<NUM> is connected to <NUM> and is charged by the capacitor bank <NUM>, with an overall capacitance Cbank. When the switch <NUM> is opened again, the capacitor <NUM> will have a charge corresponding to a voltage of Vres Cbank/(CNS<NUM> + Cbank).

Thereafter, the switch <NUM> is closed as illustrated by <NUM>, and the capacitor <NUM> dumps its charge onto the capacitor <NUM> with capacitance CNS<NUM>, effectively realizing a passive integration. The voltage Vint integrated on the capacitor <NUM> is fed to the comparator <NUM> as illustrated by <NUM>, and is used by the comparator <NUM> during bit-conversion of the next sample.

The use of Vint by the comparator <NUM> may be in accordance with any suitable approach. For example, compensation may be performed by designing the amplifying stage of the comparator inputs receiving the signal <NUM>, <NUM> to have different (e.g., larger) gain than the amplifying stage of the comparator inputs receiving the signal <NUM>, <NUM>. Such differing gain may be implemented by sizing the input transistors of the comparator <NUM>. Alternatively or additionally, dynamic or passive gain enhancing circuit(s) may be used in input paths <NUM>, <NUM>.

Thus, the comparator <NUM> has two input types; one input type <NUM>, <NUM> connectable (e.g., connected) to the capacitor banks as described in connection with <FIG>, and another input type connectable (e.g., connected) to the noise shaping networks <NUM>, <NUM> for receiving the integrations <NUM>, <NUM>.

A limitation with passive integration that only a fraction of Vres is integrated on the capacitor <NUM> (i.e., the capacitor <NUM> carries an integrated and attenuated version of Vres). This attenuation κ may be compensated for (e.g., by considering a relative gain between Vint and the voltage of <NUM>, <NUM> when input transistors of the comparator <NUM> are dimensioned, as indicated above).

Part (d) of <FIG> illustrates a functional representation of the operation of the noise shaping networks <NUM>, <NUM> combined with the comparator <NUM>. The signal levels <NUM>, <NUM> provided by the capacitor banks are represented by Vinput <NUM> and the ADC output is represented by Dout <NUM>.

Studying the functional representation of part (d) of <FIG> in z-domain, the ADC output Dout(z) <NUM> is subtracted from the input Vinput(z) <NUM> by the adder <NUM>. While switch <NUM> is closed, the output Vres(z) <NUM> of the adder <NUM> is amplified by (<NUM> - a) in amplifier <NUM>.

While switch <NUM> is closed, the passive integrator <NUM> amplifies the output of amplifier <NUM> by α in amplifier <NUM> and then input to an adder <NUM>, which also receives the adder output <NUM> passed through the feedback block <NUM> which implements (<NUM> - a)z-<NUM>.

The output Vint(z) <NUM> of the passive integrator <NUM> enters a <NUM>-path comparator <NUM> together with the input Vinput(z) <NUM>. The output Vint(z) <NUM> of the passive integrator <NUM> is passed through the block <NUM> which implements κz-<NUM>, and then added to the input Vinput(z) <NUM> in adder <NUM>. The result is added to the quantization noise Q(z) <NUM> in adder <NUM> and provided as the ADC output Dout(z) <NUM>.

The output <NUM> is a result of quantizing the input voltage <NUM> and previous sample of Vint, which can be written as <MAT> where Dout is the ADC output after bit conversion and before closing the noise shaping loop, and Q(z) represents the quantization noise of the ADC before noise shaping.

While switch <NUM> is closed, the capacitor <NUM> is loaded as <MAT>.

While switch <NUM> is closed, <MAT> which results in <MAT> or <MAT>.

If κ = <NUM>/a, the pole is removed and first order noise shaping is realized. The zero is located at <NUM> - a, and α = CNS<NUM>/(CNS<NUM> + Cbank). Values as CNS<NUM> = Cbank = C and CNS<NUM> = C/<NUM> entails a = <NUM>/<NUM> and zero located at <NUM>. A bode-plot for this example can show that the implementation has a noise transfer function of -<NUM> dB at low frequencies; resulting in about <NUM> dB reduction of the quantization noise - depending on bandwidth.

<FIG> schematically illustrates an example apparatus <NUM> according to some embodiments. The apparatus comprises a SAR ADC <NUM> (e.g., any of the SAR ADCs described in connection with <FIG> and <FIG>). The apparatus <NUM> may, for example, be a receiver or a wireless communication device (e.g., a user device - such as a user equipment, UE, or a station, STA - or a network node - such as a base station, BS, or an access point, AP).

<FIG> schematically illustrates an example receiver (RX) <NUM> according to some embodiments. The apparatus comprises a SAR ADC <NUM> (e.g., any of the SAR ADCs described in connection with <FIG> and <FIG>) which implements mixing with an oscillator signal <NUM>, wherein the mixing functionality is embedded within the analog-to-digital conversion as described otherwise herein.

<FIG> illustrates an example method <NUM> according to some embodiments. The method <NUM> is for operating a SAR ADC (e.g., any of the SAR ADCs described in connection with <FIG> and <FIG>).

As illustrated by step <NUM>, the method comprises causing the capacitor bank(s) to provide the plurality of signal levels for the comparator as representing a dynamically scaled version of the sample value of the analog input signal. This may be achieved by controlling a respective selector of each capacitor of the capacitor bank(s) to charge the capacitor using either the sample value of the analog input signal or the sample value of the opposed version of the analog input signal, as illustrated by optional sub-step <NUM>. Typically, the respective selectors are set to correspond to a digital representation of the scaling value.

The SAR ADC may be operated in either a mixing mode or a non-mixing mode according to some embodiments, as illustrated by optional steps <NUM>, <NUM>.

When operated in the mixing mode, the scaling may correspond to sample values of an oscillator signal, as illustrated by optional step <NUM>. Thus, the dynamically scaled version of the sample value of the analog input signal comprises a representation of the sample value of the analog input signal multiplied by a sample value of an oscillator signal.

When operated in the non-mixing mode, a static scaling value may be used, as illustrated by optional step <NUM>.

If it is desirable to offset the quantization levels (e.g., to represent a zero-valued dynamically scaled sample of the analog input signal), the method may further comprise controlling additional capacitor(s) to shift the scaling of the sample value of the analog input signal, as illustrated by optional step <NUM>.

<FIG> is a collection of signal plots illustrating various principles and results according to some embodiments.

The technique according to some embodiments has been simulated using a state-of-the-art CMOS process design kit with critical components like switches and capacitors being represented by accurate electrical models. A <NUM>-bit SAR ADC was implemented with functionality added to implement the approach presented herein: the additional capacitor <NUM>, <NUM>, the binary code generator <NUM>, and the signal gating <NUM>, <NUM> using the binary code generator output; but without noise shaping capabilities.

Parts (a) and (b) of <FIG> show the power spectral density and the sample points <NUM>, <NUM>, <NUM>, <NUM> of the ADC output when the ADC input is a direct current (DC) signal. The sampling frequency is <NUM>, Ns = <NUM>, and the synthesized LO frequency - corresponding to the frequency of the ADC output is <NUM>/<NUM> = <NUM>. For the plot of part (a), the x-axis ranges from <NUM> to <NUM> · <NUM><NUM> Hz and the y-axis ranges from -<NUM> dB to <NUM> dB. The power spectrum in part (a) shows that the third harmonic <NUM> is roughly <NUM> dB below the fundamental, desired, component <NUM>.

The simulation was also performed for a <NUM> sinusoidal input. The resulting ADC output frequencies becomes <NUM> ± <NUM>. Part (c) of <FIG> shows the power spectral density of the ADC output. The x-axis ranges from <NUM> to <NUM> · <NUM><NUM> Hz and the y-axis ranges from -<NUM> dB to <NUM> dB. The power spectrum in part (c) shows that the third harmonic <NUM> is well below the fundamental, desired, components <NUM>, <NUM>.

The described embodiments and their equivalents may be realized in hardware. For example, the embodiments may be performed by specialized circuitry, such as application specific integrated circuits (ASIC). The specialized circuitry may, for example, be associated with or comprised in an apparatus such as a wireless communication device (e.g., a user device or a network node).

Embodiments may appear within an electronic apparatus (such as a wireless communication device) comprising arrangements, circuitry, and/or logic according to any of the embodiments described herein. Alternatively or additionally, an electronic apparatus (such as a wireless communication device) may be configured to perform methods according to any of the embodiments described herein.

Claim 1:
A successive approximation register, SAR, analog-to-digital converter, ADC, configured to receive an analog input signal (<NUM>) and provide a digital output signal (<NUM>), the SAR ADC comprising:
a capacitor bank (<NUM>, <NUM>) for successively providing a plurality of signal levels (<NUM>, <NUM>) based on a sample value of the analog input signal, wherein each signal level of the plurality is an indicator for a corresponding bit in a corresponding sample of the digital output signal; and
controlling circuitry (<NUM>) configured to cause the capacitor bank to provide the plurality of signal levels representing a dynamically scaled version of the sample value of the analog input signal,
wherein the controlling circuitry is configured to dynamically control a respective selector (<NUM>, <NUM>) of each capacitor (<NUM>, <NUM>, <NUM>, <NUM>) of the capacitor bank to charge the capacitor using either the sample value of the analog input signal (<NUM>) or an opposed version of the sample value of the analog input signal (<NUM>) by connecting, at a sampling phase, a first plate of each capacitor to the analog input signal or to the opposed version of the analog input signal,
wherein a setting of the respective selectors, at the sampling phase, is controlled by a digital representation of a scaling value for the dynamically scaled version of the sample value of the analog input signal such that the setting of the respective selectors corresponds to the digital representation of the scaling value in that the analog input signal and the opposed version of the analog input signal represent respective binary values of the digital representation, and
wherein the scaling value is selected as a digital representation of a sample value of an oscillator signal, to perform down-conversion on the analog input signal (<NUM>).