Patent Description:
DTOF image sensors use time-of-flight (ToF) techniques to determine distance towards a target to provide, e.g., 3D-depth maps. <FIG> shows a schematic diagram of DTOF system <NUM>. DTOF system <NUM> includes illumination source <NUM>, single photon avalanche diode (SPAD) array <NUM>, time to digital converters (TDCs) <NUM>, and processor <NUM>. Routing block <NUM> couple SPAD array <NUM> to TDCs <NUM> (e.g., via metal traces and logic circuits). SPAD array <NUM>, routing block <NUM> and TDCs <NUM> are generally implemented in the same integrated circuit (IC).

A DTOF sensor generally includes an image capture mechanism, data converter(s), frequency and timing generation circuits, and at least a portion of digital signal processing and data compression/storage. Therefore, in some cases, TDCs <NUM>, SPAD array <NUM>, timing generator circuit <NUM>, and routing block <NUM> are jointly referred to as a DTOF sensor. In some cases, the DTOF sensor also includes processor <NUM> (or a portion of processor <NUM>).

During normal operation, illumination source <NUM> emits light pulses <NUM> towards object <NUM>, e.g., at times controlled by timing generator circuit <NUM>. Reflected light pulses <NUM> are sensed by SPAD array <NUM> and routed to TDCs <NUM> (which are outside SPAD array <NUM>). TDCs <NUM> generate digital representations of the time between the emissions of light pulses <NUM> and receptions of reflected light pulses <NUM>. Processor <NUM> then determines the distance to object <NUM>, e.g., by generating ToF histograms in a known manner based on the outputs of TDCs <NUM>.

SPAD array <NUM> may be formed by a plurality of pixels arranged in rows and columns, where each pixel includes one or more SPADs. For each pixel, a conventional DTOF signal chain is shown in <FIG>. As shown in <FIG>, SPADs <NUM> (of SPAD array <NUM>) are coupled to TDC <NUM> (of TDCs <NUM>) via routing block <NUM> (where routing block <NUM> may optionally include an OR tree). Even though SPADs <NUM> includes <NUM> SPADs, a different number of SPADs, such as <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or other may also be used.

<CIT> informs about an integrated circuit (IC) including an array of pixels arranged in rows and columns, each pixel of the array of pixels configured to generate event signals, the array of pixels including a subset of pixels. The IC further comprises a routing bus coupled to the subset of pixels, the routing bus further this document discloses a plurality of time-capture circuits coupled to the routing bus and a controller. <CIT> describes a method, an imaging unit and a system for increasing tolerance of sensor-scanner misalignment of the 3d camera with epipolar line laser point scanning.

<CIT> describes a spad detector having modulated sensitivity.

<CIT> describes an optoelectronic sensor and method for measuring a distance.

In accordance with an embodiment, a time-of-flight (ToF) sensor includes: an array of pixels arranged in rows and columns, the array of pixels including first and second subsets of pixels, each pixel of the array of pixels configured to generate event signals; a first plurality of time to digital converters (TDCs); a second plurality of TDCs; a first routing bus coupled to the first and second pluralities of TDCs and to the first and second subsets of pixels, the first routing bus including a first plurality of bus drivers associated with the first subset of pixels and a second plurality of bus drivers associated with the second subset of pixels, the first plurality of bus drivers coupled to the second plurality of TDCs via the second plurality of bus drivers, and the second plurality of bus drivers coupled to the first plurality of TDCs via the first plurality of bus drivers; and a controller configured to: when the first subset of pixels is active and the second subset of pixels is not active, control the first plurality of bus drivers to route event signals from half of the pixels of the first subset of pixels to the first plurality of TDCs and control the first and second plurality of bus drivers to route event signals from the other half of the pixels of the first subset of pixels to the second plurality of TDCs, and when the first subset of pixels is not active and the second subset of pixels is active, control the first plurality of bus drivers to route event signals from the second subset of pixels to the first plurality of TDCs.

In accordance with an embodiment, a method includes: activating a first subset of pixels of an array of pixels of a time-of-flight (ToF) sensor, the array of pixels being arranged in rows and columns; when the first subset of pixels is active, controlling a first plurality of bus drivers of a first routing bus to route event signals from half of the pixels of the first subset of pixels to a first plurality of TDCs and controlling the first plurality of bus drivers and a second plurality of bus drivers to route event signals from the other half of the pixels of the first subset of pixels to a second plurality of TDCs, where the first plurality of bus drivers is coupled to the second plurality of TDCs via the second plurality of bus drivers, where the second plurality of bus drivers is coupled to the first plurality of TDCs via the first plurality of bus drivers, where the first plurality of bus drivers is associated with the first subset of pixels, and where the second plurality of bus drivers associated with a second subset of pixels of the array of pixels; activating the second subset of pixels; and when the second subset of pixels is active, controlling the first plurality of bus drivers to route event signals from the second subset of pixels to the first plurality of TDCs.

In accordance with an embodiment, an integrated circuit (IC) includes: an array of pixels arranged in rows and columns, the array of pixels including a first subset of pixels, each pixel of the array of pixels configured to generate event signals; a top plurality of time to digital converters (TDCs) physically disposed at the top of the array of pixels; a bottom plurality of TDCs physically disposed at the bottom of the array of pixels; a routing bus coupled to the top and bottom pluralities of TDCs and to the first subset of pixels, the routing bus including a plurality of bus drivers associated with the first subset of pixels; and a controller configured to: when the first subset of pixels is active, control the plurality of bus drivers to route event signals from a top half of the pixels of the first subset of pixels to the top plurality of TDCs and to route event signals from a bottom half of the pixels of the first subset of pixels to the bottom plurality of TDCs, and when the first subset of pixels is not active, control all of the plurality of bus drivers to route event signals of the routing bus to the top plurality of TDCs.

In accordance with an embodiment, a time-of-flight (ToF) sensor includes: an array of pixels arranged in rows and columns, each pixel of the array of pixels configured to generate event signals, the array of pixels including a subset of pixels; a routing bus coupled to the subset of pixels; a plurality of time-capture circuits coupled to the routing bus; and a controller configured to: when the subset of pixels is in integration mode, route event signals from a first pixel of the subset of pixels to a first time-capture circuit of the plurality of time-capture circuits via a first routing line of the routing bus, and when the subset of pixels is in readout mode, route data from the first time-capture circuit to a reading circuit via the first routing line.

In accordance with an embodiment, a method includes: setting a subset of pixels of an array of pixels of a time-of-flight (ToF) sensor to integration mode, the array of pixels being arranged in rows and columns; when the subset of pixels is in integration mode, routing event signals from a first pixel of the subset of pixels to a first time-capture circuit of a plurality of time-capture circuits via a first routing line of a routing bus; setting the subset of pixels to readout mode; and when the subset of pixels is in readout mode, routing data from the first time-capture circuit to a reading circuit via the first routing line.

In accordance with an embodiment, an integrated circuit (IC) includes: an array of pixels arranged in rows and columns, each pixel of the array of pixels configured to generate event signals, the array of pixels including a subset of pixels; a routing bus coupled to the subset of pixels, the routing bus including J routing lines, where J is a positive integer greater than <NUM>, where each routing line of the J routing lines is coupled to more than <NUM> pixels of the subset of pixels; a plurality of time-capture circuits coupled to the routing bus; and a controller configured to: when the subset of pixels is in integration mode, route event signals from a first pixel of the subset of pixels to a first time-capture circuit of the plurality of time-capture circuits via a first routing line of the routing bus, and when the subset of pixels is in readout mode, route data from the first time-capture circuit to a reading circuit via the first routing line.

The making and using of the embodiments disclosed are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

The description below illustrates the various specific details to provide an in-depth understanding of several example embodiments according to the description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials and the like. In other cases, known structures, materials or operations are not shown or described in detail so as not to obscure the different aspects of the embodiments. References to "an embodiment" in this description indicate that a particular configuration, structure or feature described in relation to the embodiment is included in at least one embodiment. Consequently, phrases such as "in one embodiment" that may appear at different points of the present description do not necessarily refer exactly to the same embodiment. Furthermore, specific formations, structures or features may be combined in any appropriate manner in one or more embodiments.

Embodiments of the present invention will be described in a specific context, routing for (e.g., high density) DTOF image sensors. Embodiments of the present invention may be used in other types of sensors, such as other types of SPAD-based image sensors, as well as non-SPAD based sensors, such as a CMOS sensor (where, e.g., the SPAD is replaced by a CMOS sensor, and logic and tri-state buffering is replaced, e.g., by a source-follower-based readout circuit, for example).

DTOF image sensors are generally data-heavy, with many signals to be routed. For example, the routing between SPADs <NUM> and TDC <NUM> may include metal traces formed, e.g., in the metal layers of the IC that includes SPAD array <NUM> and TDCs <NUM>. For example, each SPAD or group of SPADs <NUM> may be connected with a tri-stated buffer to a full height column line connected to TDC <NUM>.

Some of the signals, such as signals between SPADs <NUM> and TDC <NUM>, are sensitive to timing. For such signals, it may be desirable to maintain timing precision across the routing as well as over process, voltage, and temperature (PVT) variations. Some of the signals, such as the signals between TDC <NUM> and processor <NUM>, carry high frequency data, thereby impacting power consumption. In a high resolution DTOF sensor (e.g., with hundreds or thousands of SPADs, or more), routing the DTOF sensor signals may be challenging.

Some embodiments advantageously reduce the number of routes and/or the length of the routes in a DTOF image sensor, e.g., to improve timing precision, and/or reduce power consumption, and/or reduce area, and/or achieve higher density of pixels, and/or achieve higher resolution, for example.

<FIG> shows a diagram illustrating a top view of a layout of a possible implementation of pixel array <NUM> of DTOF image sensor <NUM> (not to scale), according to an embodiment of the present invention. Pixel array <NUM> includes M columns and N rows of pixels <NUM>. Each pixel <NUM> includes <NUM> or more SPADs. Pixel array <NUM> includes a plurality of subset of pixels <NUM> (only <NUM> subset of pixels, active subset of pixels <NUM>, is shown in <FIG> for clarity purposes).

During normal operation, different subsets of pixels are activated sequentially to sense light to allow for ToF determinations. For example, <FIG> shows active subset of pixels <NUM>. Pixels <NUM> inside active subset of pixels <NUM> are active while pixels <NUM> outside active subset of pixels <NUM> are inactive. It is understood that active subset <NUM> represents the subset of pixels <NUM> that is currently active, and that the location of active subset <NUM> may dynamically change (e.g., sequentially in the vertical direction over each subset of pixels) during the integration process.

Pixels <NUM> inside active subset of pixels <NUM> (also referred to as active pixels) sense reflected light pulses <NUM>. Corresponding TDC(s) (not shown in <FIG>) sense events produced by the active pixels <NUM> when the active pixels <NUM> are excited by light. The TDC(s) then generate corresponding timestamps (based on the received events) that are then used to generate ToF histograms in a known manner. The process of sensing light by active pixels <NUM>, and the generation of corresponding timestamps and ToF histograms may be referred to as an integration process.

Once the integration process is complete (e.g., over all subset of pixels of pixel array <NUM>), data associated with pixels <NUM> (e.g., the corresponding timestamps or ToF histograms) are read (e.g., by processor <NUM>) in a data readout process.

In some embodiments, M and N may be greater than <NUM>, such as <NUM>, <NUM>, or <NUM> for example. Other values for M and N, such as higher than <NUM> or lower than <NUM> may also be used. In some embodiments M may be different than N.

In some embodiments, each subset of pixels of pixel array <NUM> (e.g., such as active subset of pixels <NUM>) may have M columns and N/k rows, where k is a positive integer greater than or equal to <NUM>. In some embodiments, each subset of pixels may have less than M columns, such as M/<NUM>, M/<NUM>, or a different number, for example.

As a non-limiting example, in an embodiment, N is equal to <NUM>, M is equal to <NUM>, and k is equal to <NUM>. In such embodiment, each subset of pixels includes <NUM> pixels per column, and <NUM> columns of pixels <NUM>.

During the integration process of such embodiment, events generated by active pixels <NUM> in each column Col; of active subset of pixels <NUM> (<NUM> active pixels divided into <NUM> columns in this example) may be processed by dedicated TDC(s) and histogram generation circuits (not shown). Once active pixels <NUM> inside subset of pixels <NUM> finish the integration process, such active pixels become inactive and the next subset of pixels (such as a subset of pixels immediately below subset of pixels <NUM>) becomes active.

Once all subsets of pixels <NUM> of pixel array <NUM> have been (e.g., sequentially) activated during the integration process, data associated with each pixel <NUM> (e.g., the corresponding timestamps or ToF histograms) is read in the data readout process.

In some embodiments, array of pixels <NUM> is implemented in a single monolithic substrate inside an IC. In some embodiments, the single monolithic substrate may also include the TDCs, histogram generation circuits, and illumination source. In some embodiments, processor <NUM>, or portions of processor <NUM> may also be integrated inside the IC.

In an embodiment of the present invention, routing inside a DTOF sensor is reduced by disposing TDCs above and below a subset of SPADs. A split bus routes half of the SPADs of the subset of SPADs to corresponding top TDCs and the other half of the SPADs to corresponding bottom TDCs. In some embodiments, the split bus advantageously allows for twice more SPADs to be routed when compared to implementations that route each column of SPADs to TDCs in a single location (e.g., all TDCs above the subset of SPADs or all TDCs below the subset of SPADs).

<FIG> show different levels of detail of column Coli of subset of pixels <NUM>, according to an embodiment of the present invention. Each subset of pixels of pixel array <NUM> (such as active subset of pixels <NUM>) may be implemented as subset of pixels <NUM>. It is understood that column Coli could be any column of the M columns of pixel array <NUM>.

As shown in <FIG>, column Coli of subset of pixels <NUM> includes a plurality of pixels <NUM> coupled to respective bus driving circuits <NUM>. Each pixel includes SPAD front-end circuit <NUM>, SPAD <NUM>, and buffer <NUM>. Each bus driving circuit <NUM> includes a plurality of bus drivers (<NUM> or <NUM>) coupled to routing bus <NUM>. As shown in <FIG>, routing bus <NUM> is coupled to a top plurality of TDCs <NUM> and to a bottom plurality of TDCs <NUM>. Each bus driver (<NUM> or <NUM>) may route a signal received up to the respective TDC of the top plurality of TDCs <NUM> or down to the respective TDC of the bottom plurality of TDCs <NUM>.

Even though <FIG> shows each pixel <NUM> including a single SPAD <NUM> coupled to buffer <NUM>, it us understood that some embodiments may replace single SPAD <NUM> and buffer <NUM> with a plurality of SPADs (such as SPADs <NUM>) coupled to an OR tree.

As shown in <FIG> and <FIG>, each SPAD <NUM> is coupled to at least one bus driver circuit <NUM>.

Bus driver <NUM> is configured to propagate the signal at the output of buffer <NUM> up (via buffer <NUM>) or down (via buffer <NUM>) routing bus <NUM>, e.g., when select signal Sel is equal to <NUM>. When select signal Sel is equal to, e.g., <NUM>, signal S<NUM> is buffered by multiplexer (MUX) <NUM> into the input of buffer <NUM>, which propagates it down via buffer <NUM>. When select signal Sel is equal to, e.g., <NUM>, signal S<NUM> is buffered by MUX <NUM> into the input of buffer <NUM>, which propagates it up via buffer <NUM>. In other words, when select signal Sel is equal to, e.g., <NUM>, bus driver <NUM> propagates the signal from the corresponding SPAD <NUM> (up or down), e.g., depending on the location of the SPAD with respect to the subset of pixels <NUM>. And when select signal Sel is equal to, e.g., <NUM> or <NUM>, bus driver <NUM> behaves as a buffer that buffers up (e.g., when Sel = <NUM>) or down (e.g., when Sel = <NUM>) the signals coming from routing bus <NUM>.

Buffers <NUM> and <NUM> may be implemented in any way known in the art. For example, in some embodiments, buffers <NUM> and <NUM> may be implemented with one or more inverters.

Bus driver <NUM> is configured to propagate signals from routing bus <NUM> either up or down. As shown, bus drivers <NUM> are capable of dynamically reconfiguring the direction of buffering. In some embodiments, bus driver <NUM> may be implemented as bus driver <NUM>.

Controller <NUM> is configured to generate select signals Sel for each of bus drivers <NUM> and <NUM> of subset of pixels <NUM> to configure them as up-buffers (e.g., Sel = <NUM>), down-buffers (e.g., Sel = o), or for buffering event signals of their respective SPADs (e.g., Sel = <NUM>).

Some embodiments include one controller <NUM> per subset of pixels <NUM>. Other embodiments include a single controller <NUM> for all subset of pixels of pixel array <NUM>. Other implementations are also possible.

Controller <NUM> may be implemented, for example, using combinatorial logic (such as a finite state machine, for example), e.g., coupled to a memory (such as registers, OTP, ROM, or RAM, for example).

In some embodiments, routing bus <NUM> includes L/<NUM> routing lines when column Coli of subset of pixels <NUM> includes L pixels <NUM>. For example, when column Col; of subset of pixels <NUM> has <NUM> pixels <NUM>, routing bus <NUM> has <NUM> routing lines (which are respectively coupled to <NUM> TDCs <NUM> and <NUM> TDCs <NUM>). In some embodiments, L may be higher than <NUM>, such as <NUM>, or higher, or lower than <NUM>, such as <NUM> or lower.

As shown in <FIG>, each routing line of routing bus <NUM> is shared by two pixels <NUM> of column Coli of subset of pixels <NUM> to propagate signals associated with their respective SPADs (as illustrated by the presence bus driver <NUM>).

<FIG> shows a top view of pixel array <NUM> column Coli of pixel array <NUM> showing the physical placement of pixels <NUM>, routing bus <NUM> and corresponding bus driver circuits <NUM>, and top and bottom TDCs <NUM> and <NUM>, respectively, according to an embodiment of the present invention.

During normal operation, when subset of pixels <NUM> is active, controller <NUM> configures bus drivers <NUM> and <NUM> so that each pixel <NUM> propagates event signals associated with their respective SPADs <NUM> using bus driver <NUM>. The top half of pixels <NUM> propagate their respective event signals up to top TDCs <NUM> via the bus drivers <NUM> coupled between the respective bus driver <NUM> and top TDCs <NUM>. The bottom half of pixels propagate their respective event signals down to bottom TDCs <NUM> via the bus drivers <NUM> between the respective bus driver <NUM> and bottom TDCs <NUM>.

During normal operation, subset of pixels that are below the active subset of pixels operate their bus drivers <NUM> and <NUM> as buffers that buffer down signals of routing bus <NUM> to bottom TDCs <NUM>. In a similar manner, subset of pixels that are above the active subset of pixels operate their bus drivers <NUM> and <NUM> as buffers that buffer up signals of routing bus <NUM> to top TDCs <NUM>.

In some embodiments, using bus drivers <NUM> advantageously allows for preserving timing precision of the event signals generated by SPADs <NUM>. In some embodiments, additional buffers and/or inverters may be used to balance the event signals from SPADs <NUM>.

In some embodiments, the placement of bus drivers <NUM> with respect to the location of pixel <NUM> in subset of pixels <NUM> may be selected to balance timing. For example, in some embodiments, the pixel <NUM> closest to the top of subset of pixel <NUM> (and the one closest to the bottom) has its corresponding bus driver <NUM> farthest to the right, while the pair of pixel <NUM> closest to the center of subset of pixels <NUM> have their corresponding bus driver <NUM> closest to the left, e.g., to compensate for the longer routing of the pixels closest to the center of subset of pixels <NUM> when compared to those at the edge of subset of pixels <NUM>.

SPAD front-end circuit <NUM> is configured to bias SPAD <NUM>. In some embodiments, SPAD front-end circuit has an enable input configured to receive a spad_enable signal (not shown). In such embodiments, SPAD front-end circuit may enable SPAD <NUM> when the spad_enable signal is asserted. In some embodiments, activating a SPAD includes asserting the spad_enable signal. In some embodiments, activating a subset of SPAD includes asserting the spad_enable signal of each SPAD in the subset of SPADs. SPAD front-end circuit <NUM> may be implemented in any way known in the art.

As shown in <FIG>, some embodiments include top TDCs <NUM> at the top of column Coli, and bottom TDCs <NUM> at the bottom of column Coli. Some embodiments may have additional rows of TDCs embedded in pixel array <NUM>. For example, <FIG> shows a column Coli of pixel array <NUM>, according to an embodiment of the present invention.

The embodiment of <FIG> operates in a similar manner as the embodiment illustrated in <FIG>. The embodiment of <FIG>, however, includes two split routing buses <NUM> in a column Coli of pixels <NUM>. In such embodiments, two active subset of pixels <NUM> may perform the integration process simultaneously. Some embodiments may include more than two split routing buses <NUM>.

In an embodiment of the present invention, routing inside a DTOF sensor is reduced by sharing a bus for routing SPAD events (e.g., SPAD pulses) from each subset of SPADs to corresponding, in-array, TDCs and histogram generation circuits, and for data readout.

As shown in <FIG>, column Coli of subset of pixels <NUM> includes a plurality of pixels <NUM> coupled to routing bus <NUM> via respective bus driving circuits <NUM>. As shown in <FIG>, Routing bus <NUM> has J routing lines, where J is a positive integer greater than or equal to <NUM>. Routing line <NUM>j could be any of the J routing lines of routing bus <NUM>.

Each pixel <NUM> includes SPAD front-end circuit <NUM>, SPAD <NUM>, and buffer <NUM>. Each bus driving circuit <NUM> includes MUX <NUM> and tri-state buffer <NUM> coupled to a routing line <NUM>j of routing bus <NUM>. As shown in <FIG>, routing line <NUM>j is coupled to a plurality of time-capture circuits <NUM>, where each time-capture circuit <NUM> includes TDC <NUM> and histogram generation circuit <NUM>.

The plurality of time-capture circuits <NUM> are shared across all subset of pixels of column Colj, and each column of pixels has its corresponding plurality of time-capture circuits <NUM>.

During the integration process of subset of pixels <NUM> (when subset of pixels <NUM> is active and in integration mode) read_histogram signal is deasserted (e.g., logic low), buffer_enable signal is asserted (e.g., logic high) and spad_enable signal is asserted (e.g., logic_high), and section_enable signal is deasserted (e.g., logic low). During this state, routing line <NUM>j is configured to propagate event signals generated by SPAD <NUM> via buffer <NUM>, MUX <NUM>, and tri-state buffer <NUM> into routing line <NUM>j. TDC <NUM> receives the generated event signals from routing line <NUM>j and histogram generation circuit <NUM> generates ToF histograms based on the output of TDC <NUM>. Since tri-state buffers <NUM> are disabled, each pixel <NUM> that is coupled to routing line 620j is isolated from each other so that each pixel <NUM> may perform the integration operation in cooperation with the corresponding time-capture circuit <NUM>.

During the readout process (when subset of pixels <NUM> is in readout mode), read_histogram signal is asserted (e.g., logic high), spad_enable signal is deasserted (e.g., logic_low), and section_enable signal is asserted (e.g., logic high). During this state, buffer_enable signal is sequentially asserted (e.g., logic high) so that data from each histogram generation circuit <NUM> (e.g., ToF histogram data, such as counts per bin) are sequentially propagated via an array bus (e.g., where the array bus includes the (e.g., vertical) routing lines connecting tri-state buffers <NUM>, <NUM>, and TDC <NUM>) to MUX <NUM>, and then to tri-state buffer <NUM> into routing line <NUM>j. Processor <NUM> then sequentially receives the data from each histogram generation circuit <NUM> and, e.g., may perform further processing.

In some embodiments, the J (e.g., vertical) routing lines of routing bus <NUM> repeat in a (e.g., vertical) pattern. For example, if subset of pixels <NUM> has <NUM> pixels <NUM> per column, and J is <NUM>, then there are <NUM> pixels coupled to each routing line of routing bus <NUM> per subset of pixels <NUM>. The pattern repeats for each subset of pixels of column Coli.

In such example, there are <NUM> TDCs <NUM> (and corresponding histogram generation circuits) associated to column Col; and coupled to the routing bus <NUM> (<NUM> TDCs coupled to each of the <NUM> routing lines of routing bus <NUM>).

As shown in <FIG>, each column Col; includes a column of pixels <NUM> and a column of time-capture circuits <NUM>. In some embodiments, pixels array <NUM> includes M columns of pixels <NUM> alternating with M columns of time-capture circuits <NUM>, wherein M is a positive integer greater than <NUM>. Other arrangements are also possible. For example, in some embodiments, pixel array <NUM> includes M/<NUM> pairs of columns of pixels <NUM> alternating with M/<NUM> pairs of columns of time-capture circuits <NUM> (e.g., in a mirror image arrangement).

Controller <NUM> is configured to generate read_histogram, buffer_enable, spad_enable, and section_enable signals to configure subset of pixels <NUM>, e.g., for integration or for readout.

Advantages of some embodiments include allowing the reduction of routing by sharing the routing bus to route SPAD pulses during the integration process and to route histogram data during data readout. In some embodiments, the reduction in routing may allow for the implementation of higher resolution DTOF sensors since, e.g., the complexities of routing congestion associated with coupling routing lines to histogram generation circuits that may be substantially larger than a pixel (e.g., may be spread over the height of multiple pixels) may be mitigated or avoided. Some embodiments may advantageously achieve a very compact implementation since there is no additional area for histogram generation circuits outside the array.

Claim 1:
An integrated circuit (IC) including:
an array of pixels arranged in rows and columns, each pixel of the array of pixels configured to generate event signals, the array of pixels including a subset of pixels;
a routing bus coupled to the subset of pixels, the routing bus including J routing lines, where J is a positive integer greater than <NUM>, where each routing line of the J routing lines is coupled to more than <NUM> pixels of the subset of pixels; a plurality of time-capture circuits coupled to the routing bus; and characterized by
a controller configured to: when the subset of pixels is in integration mode, route event signals from a first pixel of the subset of pixels to a first time-capture circuit of the plurality of time-capture circuits via a first routing line of the routing bus, and when the subset of pixels is in readout mode, route data from the first time-capture circuit to a reading circuit via the first routing line.