Patent Description:
As is known in the art, microwave circuits may suffer from performance issues due to higher order coupling modes. In a stripline architecture these are dealt with using plated vias that connect ground plane to ground plane. In a microstrip assembly with a conductive lid it is not possible to use plated through hole vias. Prior attempts to deal with the high-order mode coupling include inserting thin absorber layers into the microwave PCB assembly, introducing absorber blocks, increasing the separation between microwave and MMICs, and reducing amplifier gain. These methods can provide some performance improvements, but have disadvantages in that they are trial-and-error methods that are not deterministic. As a result, complex microwave circuits often encounter coupling problems that delay design and manufacturing cycles. Absorber blocks may introduce loss in critical circuits, have considerable unit-to-unit variability, and may not be completely effective. Increasing separation between critical MMICs is generally not practical for high frequency or advanced circuits because of limited real estate, creates new overcrowding PCB layout conditions, and is not always effective. Reducing the amplifier gain degrades overall system performance, increases the risk of manufacturing defects, and limits performance improvements. <CIT> describes a micro-patch antenna connected to circuit chips. <CIT> describes a communication system. <CIT> describes methods and systems of attaching a radio transceiver to an antenna. <CIT> describes a wireless package and fabrication method thereof.

Embodiments of the invention provide methods and apparatus for a reactive field array having front-end microwave components within a radiator, such as a patch radiator. The connection from the radiating element and circuitry is essentially lossless. In embodiments, circuitry is provided in MMICs, which may be bare die configurations eliminating package cost and loss. In embodiments, the electrical path length from the radiator port to the first receive amplifier is essentially zero thereby achieving minimal front-end loss. Housing front-end MMICs within the radiator's reactive fields reduces size and weight reduce to unprecedented levels.

In some embodiments, known mode suppression techniques can be used. In some embodiments, radiators include high-order mode suppression by including shorting posts in a cavity beneath the patch conductor having MMICs or other circuits.

In embodiments, a cavity containing a PCB includes a series of shorting posts located to achieve high order mode suppression in the cavity. The cavity can include a first ground plane that can be considered a bottom ground plane and a second ground plane that can be considered a top ground plane. The cavity can be defined by conductive walls at edges of the cavity. One or more ICs can be mounted on a surface of the PCB. The shorting posts can extend from the second ground plane into the cavity for suppressing higher order modes.

In one aspect, a radiator comprises: an antenna comprising a patch antenna layer and a first ground plane layer, wherein the antenna has a reactive field region of the radiator between the patch antenna layer and the first ground plane layer; and an integrated circuit located in the active region; and a second ground layer, wherein the second ground layer is connected to the patch antenna layer by a via.

A radiator can include one or more of the following features: the integrated circuit comprises a monolithic microwave integrated circuit (MMIC), the MMIC is bare die, the MMIC does not have any wirebond connections, the integrated circuit comprises a (MMIC), wherein the MMIC can comprise a power amplifier, RF switch, low noise amplifier, phase shifter, and/or digital attenuator, a logic layer, wherein the logic layer is connected to the MMIC, the logic layer is connected to the MMIC with a via, the radiator has a thickness of less than or equal to about <NUM>, the radiator comprises the antenna, a paint layer on the patch antenna, the integrated circuit including at least one MMIC, a bond film, a laminate layer, a second ground plane layer, a logic layer, and a structural carrier layer, and/or the radiator has a density of less than about <NUM>/m<NUM>.

In another aspect, a method comprises: employing an antenna comprising a patch antenna layer and a first ground plane layer, wherein the antenna has a reactive field region of the radiator between the patch antenna layer and the first ground plane layer, wherein the antenna forms part of a radiator; and employing an integrated circuit located in the active region; and employing a second ground layer, wherein the second ground plane is connected to the patch antenna layer by a via.

A method can include one or more of the following features: the integrated circuit comprises a monolithic microwave integrated circuit (MMIC), the MMIC is bare die, the MMIC does not have any wirebond connections, the integrated circuit comprises a (MMIC), wherein the MMIC can comprise a power amplifier, RF switch, low noise amplifier, phase shifter, and/or digital attenuator, a logic layer, wherein the logic layer is connected to the MMIC, the logic layer is connected to the MMIC with a via, the radiator has a thickness of less than or equal to about <NUM>, the radiator comprises the antenna, a paint layer on the patch antenna, the integrated circuit including at least one MMIC, a bond film, a laminate layer, a second ground plane layer, a logic layer, and a structural carrier layer, and/or the radiator has a density of less than about <NUM>/m<NUM>.

The foregoing features of this invention, as well as the invention itself, may be more fully understood from the following description of the drawings in which:.

<FIG> show an example radiator <NUM> having circuitry within the reactive field region of the radiator. Integrated circuits <NUM> can include one or more MMICs (Monolithic microwave integrated circuits) in a cavity <NUM> under a patch antenna layer <NUM>. The patch antenna layer <NUM> may be covered by a material <NUM>, such as paint having desired characteristics. As is known in the art, MMICs refer to integrated circuits (ICs) that operate at microwave frequencies, e.g., (<NUM> to <NUM>). Example MMICs include signal mixers, power amplifiers, low noise amplifiers (LNAs), and high-frequency switches. Inputs and outputs on MMIC devices are typically matched to a <NUM> Ohm impedance.

In the illustrated embodiment, a ground layer <NUM>, which can be provided in stripline, is under the MMICs <NUM> and separated by a layer <NUM> of dielectric material. A radiator substrate layer <NUM>, which can be provided as dielectric material, is located between ground layer <NUM> and a further ground layer <NUM>, which can comprise copper, for example. A logic layer <NUM> under the ground layer <NUM> can include digital circuitry and DC power distribution. The logic layer <NUM> can be located on top of a carrier layer <NUM>.

In embodiments, the patch layer <NUM> and ground layer <NUM> provide the patch antenna. The fringing fields from the antenna are responsible for the radiation. The fringing E-fields on the edge of the antenna add up in phase and produce the radiation of the antenna. The current adds up in phase on the patch antenna and an equal current in opposite direction is on the ground plane, which cancels the radiation. The antenna radiation arises from the fringing fields, which are due to the advantageous voltage distribution. That is, the radiation arises due to the voltage and not the current. The patch antenna can be considered a voltage radiator. In embodiments, MMICs <NUM> are located in the active region between the patch <NUM> and ground layer <NUM>.

A first via <NUM> provides a connection from ground layer <NUM> to the patch radiator <NUM> and a second via <NUM> provides a connection from the logic layer <NUM> to the MMICs <NUM>. In example embodiments, multiple vias are connected to the MMICs <NUM>.

In embodiments, a component module <NUM> can include various circuit components, such as passive components like resistors, inductors and/or capacitors (RLCs), and can be provided proximate the logic layer <NUM>. It is understood that a variety of circuit components known to one skilled in the art can form a part of the component module <NUM>.

In embodiments, the MMICs <NUM> comprise bare die components, e.g., the MMICs do not include packages (encapsulant), which significantly reduces the area and height needed for the MMICs. The MMICs <NUM> may have printed base connections instead of wirebonds.

<FIG> shows example layers and layer thicknesses for the logic layer <NUM> of <FIG> and <FIG> shows example layer thicknesses for the example radiator <NUM> of <FIG>. As can be seen, in the illustrated embodiment the total thickness of the example radiator <NUM> is less than about <NUM> inch (<NUM>). This thickness is less than any known radiator. In embodiments, an array having radiator embodiments described above can have a weight of less than <NUM>/m<NUM>. It is readily understood that such a low weight is highly desirable, for example in weight critical applications including spaced-based and airborne radars. No conventional arrays are known having such a low weight density.

It is understood that TLY-<NUM> in the illustrated embodiment refers to TLY-<NUM> from TACONIC as one example laminate layer material having a dielectric constant in the order of about <NUM> that can be used. Suitable laminates can comprise glass-filled, PTFE composites with woven fiberglass reinforcement. Materials should be low density for low weight requirements.

<FIG> shows an example circuit <NUM> that can form a part of the radiator <NUM> of <FIG>. A first area <NUM> provides a via interface into a cavity for the MMICs, such as the MMICs <NUM> in the cavity <NUM> of the patch radiator <NUM> shown in <FIG>. In the illustrated embodiment, a <NUM> port assembly <NUM> brings <NUM> transmission lines into the patch area from the microwave PWB. These represent transmit and receive for two polarizations. The RX ports pass through a two port LNA <NUM> and then to RF Switches <NUM>,<NUM> before connecting to the radiator feed. The TX ports connect directly to the RF switches. In example embodiments, the via interface includes four vias. First and second connections <NUM>,<NUM> provide an interface to a patch antenna, such as patch antenna <NUM> of <FIG>, which can include V and H polarizations. RF switches <NUM>, <NUM> are controlled to select between transmit and receive operation for the radiator. A LNA <NUM> can be selectively coupled to the patch antenna via the switches <NUM>,<NUM> in receive mode. In transmit mode a signal from a power amplifier (not shown) is fed to the patch antenna via the switches <NUM>,<NUM> for transmission into air. The radiator may include mode suppression in the cavity. Example mode suppression configurations can include shorting posts in the cavity, a thin absorber layer above the MMIC circuits, absorber blocks on the PCB, increase MMIC separation, limit amplifier gain, and the like.

<FIG> shows an illustrative array <NUM> having example radiator embodiments described above within a tile or sub-array <NUM> of radiators shown detached from the array. It is understood that embodiments of the radiators can be used in wide variety of antenna arrays.

Example embodiments of a reactive field array can include radiators with integrated bare-die MMICs. In embodiments, circuitry in the MMICs may be relatively simple in order to limit the real estate needed with a patch radiator, for example. Some radiator embodiments are surface mount technology (SMT) compatible and can be integrated into know PCB layout processes.

It will be appreciated that radiator embodiments described above achieve significant weight reduction for phased arrays as compared with conventional radiators, such as in X to Ku Band phased arrays. Such weight reduction enables wearable sensors and communications, desirable aircraft sensors, and new classes of space-based arrays, radars, CubeSATs, and nanoSATs.

It is understood that with regard to embodiments of a radiator reference is sometimes made herein to an array antenna having a particular array shape and/or size (e.g., a particular number of antenna elements) or to an array antenna comprised of a particular number of antenna elements. One of ordinary skill in the art will appreciate, however, that the concepts, circuits and techniques described herein are applicable to various sizes, shapes and types of array antennas.

Thus, although the description provided herein describes the concepts, systems and circuits sought to be protected in the context of a array antenna having a substantially square or rectangular shape and comprised of a elements, each having a substantially square or rectangular-shape, those of ordinary skill in the art will appreciate that the concepts equally apply to other sizes and shapes of array antennas and antenna elements having a variety of different sizes, shapes.

Reference is also sometimes made herein to an array antenna including an antenna element of a particular type, size and/or shape configured for operation at certain frequencies. Those of ordinary skill in the art will recognize, of course, that other antenna shapes may also be used and that the size of one or more antenna elements may be selected for operation at any frequency in the RF frequency range.

It should also be appreciated that the antenna elements can be provided having any one of a plurality of different antenna element lattice arrangements including periodic lattice arrangements (or configurations) such as rectangular, circular square, triangular (e.g. equilateral or isosceles triangular), and spiral configurations as well as non-periodic or other geometric arrangements including arbitrarily shaped lattice arrangements.

<FIG> shows an example cavity <NUM> having a shorting post <NUM> located to achieve high order mode suppression in the cavity. In the illustrated embodiment, the cavity <NUM> includes a first ground plane <NUM> that can be considered a bottom ground plane and a second ground plane <NUM> that can be considered a top ground plane. The cavity <NUM> is defined by conductive walls <NUM> at edges of the cavity. An IC <NUM> is mounted on a surface of a PCB <NUM> which includes a dielectric layer <NUM>. In the illustrated embodiment, a microstrip feed line <NUM> is connected to the IC <NUM>. The shorting post <NUM> extends from the first ground plane <NUM> by a plated through hole or via <NUM> into the cavity <NUM>.

<FIG> shows an example microwave printed circuit board (PCB) <NUM> with an example 2x2 unit cell so there are four unit cells 502a-d as indicated by the dashed lines. As shown in <FIG>, the PCB can be located in a cavity surrounded by conductive walls. The PCB includes a number of ICs and components, such as capacitors, resistors, and the like. A first IC <NUM> is located at the intersection of the unit cells <NUM>. The ICs can include any practical device suited to meet the needs of a particular application. In one particular embodiment, the first IC <NUM> comprises a beamformer device, such as a <NUM>-<NUM> beamformer, coupled to switches and power and/or low noise amplifiers, for example. A series of plated through holes <NUM> are shown at various locations. As described more fully herein, shorting posts (not shown) can be located at various locations to reduce higher order mode coupling.

<FIG> shows a simulated E-field <NUM> for a PCB in a cavity without mode suppression. As can be seen, there are a number of regions <NUM> in which there is higher order mode coupling. <FIG> shows a simulated E-field for a PCB in a cavity, such as the PCB shown in <FIG>, with high order mode suppression provided by a series of shorting posts. In the illustrated embodiment, a 30dB improvement is shown for adjacent unit cell isolation. In the illustrated example mode suppression, there are eight receivers <NUM> that surround a field generating IC or other source. There are shorting posts <NUM> located at edges of the unit cells to achieve desired high order mode suppression.

In embodiments, cutoff boundaries are used to place the shorting posts for suppressing high order mode coupling. Such coupling modes are responsible for unexpected electrical problems including impedance mismatch, dispersion, amplifier oscillations, and poor isolation. These problems occur because the cavity mode is often not considered and is difficult to accurately model. As a result, these modes intrude on otherwise expensive and carefully designed circuits, often producing unacceptable electrical performance.

Prior attempts to deal with the high-order mode coupling include inserting thin absorber layers into the microwave PCB assembly, introducing absorber blocks, increasing the separation between microwave and MMICs, and reducing amplifier gain. These methods can provide some performance improvements, but have disadvantages in that they are trial-and-error methods that are not deterministic. As a result, complex microwave circuits often encounter coupling problems that delay design and manufacturing cycles. Absorber blocks may introduce loss in critical circuits, have considerable unit-to-unit variability, and may not be completely effective.

Increasing separation between critical MMICs is generally not practical for high frequency or advanced circuits because of limited real estate, creates new overcrowding PCB layout conditions, and is not always effective. Reducing the amplifier gain degrades overall system performance, increases the risk of manufacturing defects, and limits performance improvements.

Example embodiments of high order mode suppression reduce coupling with minimal effect on the intended TEM propagation. In embodiments, shorting posts are formed using surface mount technology (SMT) techniques that can readily integrate into PCB layout processes.

In embodiments, the PCB design is analyzed using a FEM (finite element method) full wave solver to identify higher order cavity modes. The overall size of the cavity determines the mode composition that forms low loss coupling mechanisms. Conductive shorting posts cut off the cavity mode coupling with little effect on the intended microstrip TEM fields.

By using shorting or grounding posts to create an edge wall around the unit cell, a smaller effect unit cell is generated thereby increasing the minimum resonant frequency of the cavity. In general, the 'wall' created by shorting posts does not need to be continuous. In embodiments, a wall can have a gap, as described more fully below. The size of this gap determines the allowed inter-unit-cell coupling. The shorting posts can be placed within the unit cell to suppress higher-order resonant modes, as well as to address direct, point-to-point coupling due to reactive fields.

<FIG> shows an example until cell <NUM> having a series of shorting posts <NUM> around a perimeter of the until cell. In the illustrated embodiment, the cavity <NUM> includes a center shorting post <NUM>. Each side of the cavity <NUM> can include a gap <NUM> in which shorting posts <NUM> are not placed. The gaps <NUM> should be dimensioned to achieve a desired level of mode suppression. The cavity <NUM> can include a connector <NUM>, such as a port for a coaxial connection.

<FIG> shows an example layout for a PCB <NUM> having a series of shorting posts <NUM> for high order mode suppression. In the illustrated embodiment, a 2x2 unit cell U1, U2, U3, U4 structure is defined. A number of MMICs <NUM>, which may comprise SMT ICs, are placed on the PCB <NUM>. Output ports <NUM> can provide external connections for the PCB <NUM>. Traces <NUM> interconnect the MMICs.

In the illustrated embodiment, the shorting posts <NUM> are located to form a 'soft' circle for creating a smaller effective cavity to prevent leakage between sets of unit cells. In embodiments, the shorting posts <NUM> provide a generally circular formation around the ICs <NUM>. In embodiments, the spacing between shorting posts <NUM>, which is shown as dimension A, is approximately λ/<NUM>. In embodiments, a mode suppression pin spacing of lambda/<NUM> achieves a <NUM> dB isolation between unit cells. A lambda/<NUM> or less spacing rule may be applied to a real circuit where the pins must be placed around components and microstrip traces.

The shorting posts <NUM> within the unit cell reduce coupling within the 2x2 unit cell structure by creating boundary conditions that do not support a low-order/in-band modal field structure and prevent direct reactive field coupling by blocking line-of-sight between points of high coupling, e.g., chip interfaces, transitions to output, etc. The shorting posts <NUM> can be formed using any suitable technology.

In one embodiment shown in <FIG> shorting posts are formed using wirebonding systems to form stud bumps. A wire <NUM> is fed through a needle-like tool <NUM> which may be referred to as a capillary. A high-voltage electric charge is applied to the wire <NUM> to melt the wire at the tip of the capillary <NUM>. The tip of the wire <NUM> forms into a ball <NUM> because of the surface tension of the molten metal. The ball <NUM> quickly solidifies and the capillary <NUM> is lowered to the surface of the chip, which is typically heated to at least <NUM>. The machine then pushes down on the capillary <NUM> and applies ultrasonic energy with an attached transducer. The combined heat, pressure, and ultrasonic energy create a weld between the metal ball and the surface of the chip. A series of balls, which may be referred to as stud bumps, may be stacked on top of each other. The stud bumps can be formed having any practical dimensions to meet the requirements of a particular application. In embodiments, stud bumps can have a diameter in the order of <NUM> mils.

<FIG> shows an example sequence of steps for providing higher order mode suppression in a cavity in accordance with example embodiments of the invention. In step <NUM>, the dimensions of a cavity containing a PCB are received. Example dimensions include length, width, and height of the cavity. In embodiments, the cavity is defined by conductive walls. In step <NUM>, layout of the PCB is received. For example, the layout can include the location of ICs, components, and the like, on the PCB. In step <NUM>, locations of shorting posts are determined. In step <NUM>, the shorting posts are formed at the determined locations to provide the desired higher order mode suppression.

While relative terms, such as "vertical," "above," "below," "lower," "upper," "left," "right," and the like, may be used to facilitate an understanding of example embodiments, such terms are not to limit the scope of the claimed invention in any way. These terms, and any similar relative terms, are not to construed as limiting in any way, but rather, as terms of convenience in describing embodiments of the invention.

Applications of at least some embodiments of the concepts, systems, circuits and techniques described herein include, but are not limited to, military and non-military (i.e. commercial) applications including, but not limited to radar, electronic warfare (EW) and communication systems for a wide variety of applications including ship-based, airborne (e.g. plane, missile or unmanned aerial vehicle (UAV)), and space and satellite applications. It should thus be appreciated that the circuits described herein can be used as part of a radar system or a communications system.

Claim 1:
A radiator (<NUM>), comprising:
an antenna comprising a patch antenna layer (<NUM>) and a first ground plane layer (<NUM>), wherein the antenna has a reactive field region of the radiator between the patch antenna layer and the first ground plane layer;
an integrated circuit (<NUM>) located in the reactive field region; and
a second ground layer (<NUM>), wherein the second ground layer is connected to the patch antenna layer by a via (<NUM>).