Patent Description:
Superconducting quantum interference devices are utilized heavily in superconducting circuits. However, the superconducting quantum interference devices have large footprints due to a size of a loop area. Further, superconducting quantum interference devices can only detect fields orthogonal to the loop, which may be limiting for some circuits, especially if the loops are laid out on the substrate plane.

For example,<CIT>) discusses "[a] superconducting structure that can operate, for example, as a qubit or a superconducting switch. " See Abstract. Zagoskin et al. also discusses that a "junction [] is preferably a grain boundary junction". See, for example, column <NUM>, line <NUM>. In addition, Zagoskin et al. discusses ". a grain boundary junction, such as [a] junction [ ] between two unconventional superconductors. " See column <NUM>, lines <NUM>-<NUM>. In Zagoskin et al. , an insulating material is "aluminum oxide (Al<NUM>O<NUM>) and silicon dioxide (SiO<NUM>). " See column <NUM>, lines <NUM> and <NUM>. However, aluminum oxide and silicon dioxide insulators cannot provide adequate performance for quantum computing applications because of the low loss requirements. Further, unconventional superconductors contribute to additional costs and fabrication complexity. US Patent Number <CIT>) discloses a process for constructing a superconducting Josephson-based nonvolatile quantum memory device comprising: sequentially depositing on a silicon substrate a thermal oxide buffer layer, a superconductor bottom-electrode thin film, and an oxide isolation layer; patterning an active window having dimensions smaller that <NUM> nanometers in the oxide isolation layer; then sequentially depositing a bottom tunnel oxide layer, a charge-trapping layer, a top cap, and a top superconductor electrode layer; defining an active region by dry etching down to the oxide isolation layer while protecting the active region from etch chemistry; depositing a device passivation layer; defining and patterning vias from a top of the device passivation layer to the superconductor bottom-electrode thin film and to the top superconductor electrode of the active region; and depositing metal interconnect into the vias. International publication<CIT> describes a SQUID structure. In this known SQUID structure, the Josephson junctions are not arranged in wires as defined by the independent claims.

Therefore, there is a need in the art to address the aforementioned problem.

Viewed from a first aspect, the present invention provides a superconducting quantum interference device (SQUID) structure, comprising: a silicon-on-metal substrate comprising a first superconducting layer between a first crystalline silicon layer and a second crystalline silicon layer, the first superconducting layer comprising a first superconducting material; a first via between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer, the first via comprises a first Josephson junction, and the second superconducting layer is over the second crystalline silicon layer and comprises a second superconducting material; and a second via between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer, the second via comprises a second Josephson junction, wherein an electrical loop around a defined area of the second crystalline silicon layer comprises the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.

Viewed from a further aspect the present invention provides a method for forming a superconducting interference device (SQUID) structure, comprising: forming a silicon-on-metal substrate comprising a first superconducting layer between a first crystalline silicon layer and a second crystalline silicon layer, the first superconducting layer comprising a first superconducting material; forming a first via between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer, the first via comprises a first Josephson junction, and the second superconducting layer is over the second crystalline silicon layer and comprises a second superconducting material; and forming a second via between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer, the second via comprises a second Josephson junction, wherein an electrical loop around a defined area of the second crystalline silicon layer comprises the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.

The following presents a summary to provide a basic understanding of one or more embodiments of the invention. The purpose of this summary is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, systems, computer-implemented methods, methods, apparatuses, devices, and/or computer program products that facilitate vertical silicon-on-metal superconducting quantum interference devices. Also provided are associated flux control and biasing circuitry for vertical silicon-on-metal superconducting quantum interference devices.

According to an embodiment, a superconducting structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer between a first crystalline silicon layer and a second crystalline silicon layer. The first superconducting layer can comprise a first superconducting material. The superconducting structure can also comprise a first via between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer. The first via can comprise a first Josephson junction. The second superconducting layer can be over the second crystalline silicon layer and can comprise a second superconducting material. The superconducting structure can also comprise a second via between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer. The second via can comprise a second Josephson junction. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.

In an example, a first side of the second superconducting layer can be flush with a first edge of the silicon-on-metal substrate and a second side of the second superconducting layer can be flush with a second edge of the silicon-on-metal substrate. According to some implementations, a shape of the second superconducting layer can be selected based on a defined shape of the electrical loop.

In accordance with some implementations, the superconducting structure can comprise a first trench that can extend through the second crystalline silicon layer a first distance from, and adjacent to, the first via comprising the first Josephson junction. The superconducting structure can also comprise a second trench that extends through the second crystalline silicon layer a second distance from, and adjacent to, the second via comprising the second Josephson junction. Further to these implementations, the first trench and the second trench can electrically isolate the superconducting structure from one or more circuits.

According to some implementations, the superconducting structure can comprise a first external electrical connection terminal at the first superconducting layer and a second external electrical connection terminal at the second superconducting layer. In some implementations, the superconducting structure can comprise a coupling capacitor over the second crystalline silicon layer and at a first distance from the electrical loop and near an interconnect for an external electrical connection.

In other implementations, the superconducting structure can comprise a first loop contact that can extend perpendicular from the second superconducting layer. The first loop contact can provide a first terminal for an electrical connection. The superconducting structure can also comprise a second loop contact over the second crystalline silicon layer and opposite the first loop contact. The second loop contact can provide a second terminal for the electrical connection.

In accordance with some implementations, the superconducting structure can comprise a wire over at least a portion of the second crystalline silicon layer and parallel to the electrical loop. According to some implementations, the superconducting structure can comprise a wire over at least a portion of the first crystalline silicon layer and parallel to the electrical loop. In other implementations, the superconducting structure can comprise two or more wires in parallel and over the first superconducting layer. The two or more wires can form parallel electrical loops.

Another embodiment can relate to a method that can comprise forming a silicon-on-metal substrate comprising a first superconducting layer between a first crystalline silicon layer and a second crystalline silicon layer. The first superconducting layer can comprise a first superconducting material. The method can also comprise forming a first via between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer. The first via can comprise a first Josephson junction. The second superconducting layer can be over the second crystalline silicon layer and can comprise a second superconducting material. In addition, the method can comprise forming a second via between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer. The second via can comprise a second Josephson junction. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.

In an example, the method can comprise etching a first side of the second superconducting layer flush with a first edge of the silicon-on-metal substrate and a second side of the second superconducting layer flush with a second edge of the silicon-on-metal substrate.

In another example, the method can comprise forming a first trench through the second crystalline silicon layer a first distance from, and adjacent to, the first via comprising the first Josephson junction. Further to this example, the method can comprise forming a second trench through the second crystalline silicon layer a second distance from, and adjacent to, the second via comprising the second Josephson junction.

In some implementations, the method can comprise providing at least one of a first external electrical connection at the first superconducting layer or a second electrical connection at the second superconducting layer. According to some implementations, the method can comprise providing a wire parallel to the electrical loop. The wire can be provided over the second crystalline silicon layer for control of the magnetic flux through the electrical loop, or over the first crystalline silicon layer for control of the magnetic flux through the electrical loop. In an additional, or alternative implementation, the method can comprise providing two or more wires in parallel over the first superconducting layer, wherein the two or more wires form parallel electrical loops.

Another embodiment provided herein is a superconducting device that can comprise a silicon-on-metal substrate comprising a first superconducting layer between a first crystalline silicon layer and a second crystalline silicon layer. The first superconducting layer can comprise a first superconducting material. The superconducting device can also comprise a first via between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer. The first via can comprise a first Josephson junction. The second superconducting layer can be over the second crystalline silicon layer and can comprise a second superconducting material. Further, the superconducting device can comprise a second via between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer. The second via can comprise a second Josephson junction. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.

In an implementation, the superconducting device can also comprise a first trench that extends through the second crystalline silicon layer a first distance from, and adjacent to, the first via comprising the first Josephson junction. Further, the superconducting device can comprise a second trench that extends the second crystalline silicon layer a second distance from, and adjacent to, the second via comprising the second Josephson junction.

According to some implementations, the superconducting device can comprise a first loop contact that can extend perpendicular from the second superconducting layer. The first loop contact can provide a first terminal for an electrical connection. Further, the superconducting device can comprise a second loop contact over the second crystalline silicon layer and opposite the first loop contact. The second loop contact can provide a second terminal for the electrical connection.

According to some implementations, the superconducting device can comprise two or more wires in parallel and over the first superconducting layer. The two or more wires can form parallel electrical loops.

Another embodiment relates to a superconducting structure that can comprise a silicon-on-metal substrate comprising a first superconducting layer between a first crystalline silicon layer and a second crystalline silicon layer. The first superconducting layer can comprise a first superconducting material. The superconducting structure can also comprise a first via between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer. The first via can comprise a first Josephson junction. The second superconducting layer can be over the second crystalline silicon layer and can comprise a second superconducting material. In addition, the superconducting structure can comprise a second via between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer. The second via can comprise a second Josephson junction. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.

A further embodiment provided herein relates to a superconducting device that can comprise a silicon-on-metal substrate comprising a first superconducting layer between a first crystalline silicon layer and a second crystalline silicon layer. The first superconducting layer can comprise a first superconducting material. The superconducting device can also comprise a first via and a second via. The first via can be between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer. The first via can comprise a first Josephson junction. The second superconducting layer can be over the second crystalline silicon layer and can comprise a second superconducting material. The second via can be between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer. The second via can comprise a second Josephson junction. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer. The superconducting device can also comprise a first trench that can extend through the second crystalline silicon layer a first distance from, and adjacent to, the first via comprising the first Josephson junction and a second trench that can extend through the second crystalline silicon layer a second distance from, and adjacent to, the second via comprising the second Josephson junction.

In an example, the superconducting device can comprise a first external electrical connection terminal at the first superconducting layer and a second external electrical connection terminal at the second superconducting layer. In another example, the superconducting device can comprise two or more wires in parallel and over the first superconducting layer, wherein the two or more wires form parallel electrical loops.

Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings in which:.

One or more embodiments are now described with reference to the drawings, wherein like referenced numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of the one or more embodiments. It is evident, however, in various cases, that the one or more embodiments can be practiced without these specific details.

Provided herein is a vertical silicon-on-metal superconducting quantum interference device (abbreviated as SQUID). Also provided herein are associated flux control (also referred to as magnetic flux control) and biasing circuitry for vertical silicon-on-metal superconducting quantum interference devices. The various aspects can reduce a footprint of superconducting quantum interference devices through the use of one or more vertical Josephson junction devices. In addition, electrical loops can reside mostly on the plane orthogonal to the substrate as discussed herein. If an electrical loop comprises a SQUID, it can also be referred to as a SQUID loop.

<FIG> illustrates an example, non-limiting, side cross-sectional view of a structure for an embodiment of a silicon-on-metal substrate <NUM> during a fabrication process wherein a first wafer <NUM> and a second wafer <NUM> are formed in accordance with one or more embodiments described herein.

The first wafer <NUM> can comprise a first layer of silicon. According to an implementation, the first layer of silicon can be a first crystalline silicon layer <NUM>. The first wafer <NUM> can also comprise a superconductor (e.g., a first superconducting metal <NUM>) that can be attached to the first crystalline silicon layer <NUM>. The superconductor layer can be deposited (e.g., sputtering, evaporation, Atomic Layer Deposition, electroplating, or another deposition technique) on the first crystalline silicon layer <NUM>.

The second wafer <NUM> can comprise a second layer of silicon. The second layer of silicon can be a second superconducting layer, which can be a crystalline silicon layer (e.g., a second crystalline silicon layer <NUM>).

Further, the second wafer <NUM> can also comprise a superconductor (e.g., a second superconducting metal <NUM>) that can be attached to the second crystalline silicon layer <NUM>. Similar to the first wafer <NUM>, the second superconductor layer can be deposited (e.g., sputtering, evaporation, Atomic Layer Deposition, electroplating, or another deposition technique) on the second crystalline silicon layer <NUM>. Superconducting material utilized for the first superconducting metal <NUM> and the second superconducting metal <NUM> can be a same superconducting material, a similar superconducting material, or a different superconducting material.

<FIG> illustrates an example, non-limiting, side cross-sectional view of the structure of the silicon-on-metal substrate <NUM> of <FIG> during a fabrication process wherein the second wafer <NUM> is positioned for bonding to the first wafer <NUM> in accordance with one or more embodiments described herein. Further, <FIG> illustrates an example, non-limiting, side cross-sectional view of the structure of the silicon-on-metal substrate <NUM> of <FIG> during a fabrication process wherein the second wafer <NUM> is attached to the first wafer <NUM> in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

As illustrated in <FIG>, the second wafer <NUM> can be turned such that the first superconducting metal <NUM> and the second superconducting metal <NUM> are facing one another (e.g., face-to-face). For example, the second wafer <NUM> can be turned upside down over the first wafer <NUM>. In such a manner, the first superconducting metal <NUM> and the second superconducting metal <NUM> can be aligned with one another.

The substrates (e.g., the first wafer <NUM> and the second wafer <NUM>) can be pressed against one another, as illustrated in <FIG>. According to some implementations, heat can be applied to bond the two substrates together. However, according to some implementations, heat is not utilized. Upon or after bonding of the first wafer <NUM> and the second wafer <NUM>, the first superconducting metal <NUM> and the second superconducting metal <NUM> can create a first superconducting layer <NUM>. The first superconducting layer <NUM> can be a single superconducting layer based on the bonding of the first wafer <NUM> and the second wafer <NUM> and, thus, the silicon-on-metal substrate <NUM> is created.

<FIG> illustrates an example, non-limiting, side cross-sectional view of the silicon-on-metal substrate <NUM> of <FIG> during a fabrication process wherein a thickness of the second wafer <NUM> is reduced in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

The second crystalline silicon layer <NUM> (which can be referred to as an insulator or top insulator) can be thinned to a defined height. Therefore, upon or after the thinning of the second crystalline silicon layer <NUM>, the first crystalline silicon layer <NUM> and the second crystalline silicon layer <NUM> can comprise different heights.

To visualize the thinning of the second crystalline silicon layer <NUM>, refer to <FIG> where the second crystalline silicon layer <NUM> comprises a first height <NUM>. As illustrated in <FIG>, the second crystalline silicon layer <NUM> can be thinned or reduced in height to a second height <NUM>.

To thin the second crystalline silicon layer <NUM>, the exposed silicon surface (e.g., a top surface <NUM>) can be ground down. According to some implementations, the second crystalline silicon layer <NUM> can be thinned down prior to the bonding of the first wafer <NUM> and the second wafer <NUM>. However, in some implementations, the second crystalline silicon layer <NUM> can be thinned down upon or after the bonding of the first wafer <NUM> and the second wafer <NUM>.

According to some implementations, the top surface <NUM> can be polished after being thinned down. Various polishing techniques can be utilized, including, but not limited to, Chemical-Mechanical Polishing (CMP). CMP is a polishing process that can be utilized to smooth surfaces. For example, CMP can utilize a chemical slurry formation and a mechanical polishing process to obtain the smooth surfaces. As illustrated, the CMP can create a level surface across the top surface <NUM> of the second wafer <NUM>. The polishing of the top surface <NUM> is optional. However, in some cases, polishing can be better for lithography.

According to an implementation, the second crystalline silicon layer <NUM> can be thinned to an example, non-limiting, thickness range (e.g., the second height <NUM>) of between around <NUM> to around <NUM>. However, other thickness ranges can be utilized with the disclosed aspects.

<FIG> illustrates an example, non-limiting, side cross-sectional view of a structure of a superconducting quantum interference device <NUM> during a fabrication process wherein an electrical loop is created in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

Upon or after the thinning down of the second crystalline silicon layer <NUM>, one or more vias can be etched in the second crystalline silicon layer <NUM>. For example, a first via <NUM> and a second via <NUM> can be formed at defined areas of the superconducting quantum interference device <NUM>.

The first via <NUM> and the second via <NUM> can comprise respective Josephson junctions. For example, the first via <NUM> can comprise a first Josephson junction <NUM> that can comprise a first superconductor layer <NUM>, a tunnel barrier layer <NUM>, and a second superconducting layer <NUM>. The first Josephson junction <NUM> is identified by the oval area <NUM>. Further, the second via <NUM> can comprise a second Josephson junction <NUM> that can comprise a first superconductor layer <NUM>, a tunnel barrier layer <NUM>, and a second superconducting layer <NUM>. As illustrated the first Josephson junction <NUM> and the second Josephson junction <NUM> can be vertical Josephson junctions.

According to some implementations, the superconducting material utilized for the second superconducting layer <NUM> can be utilized to fill the first via <NUM> to the top surface <NUM> and the superconducting material utilized for the second superconducting layer <NUM> can be utilized to fill the second via <NUM> to the top surface <NUM>.

A second superconducting layer <NUM> can be deposited over the top surface <NUM> of the second crystalline silicon layer <NUM>. The second superconducting layer <NUM> can comprise a superconducting metal, which can be a same metal, a similar metal, or a different metal than the metals utilized for the first via <NUM>, the second via <NUM>, the first Josephson junction <NUM>, the second Josephson junction <NUM>, and/or the first superconducting layer <NUM>. Further, the second superconducting layer <NUM> can be patterned and etched. The second superconducting layer <NUM> (a top contact) and the first superconducting layer <NUM> (e.g., a bottom contact) can be utilized to control properties of the superconducting quantum interference device <NUM>, for example.

An electrical loop can be formed from the first via <NUM> comprising the first Josephson junction <NUM>, the second via <NUM> comprising the second Josephson junction <NUM>, the first superconductor layer (e.g., the first superconducting layer <NUM>), and the second superconductor layer (e.g., the second superconducting layer <NUM>). Accordingly, the loop can be formed by superconducting material. The electrical loop can allow for the circulation of supercurrent.

An area of the second crystalline silicon layer <NUM> (e.g., a defined area <NUM>) can be defined within the electrical loop. For example, the area of the second crystalline silicon layer <NUM> surrounded by the first via <NUM> comprising the first Josephson junction <NUM>, the second via <NUM> comprising the second Josephson junction <NUM>, the first superconductor layer (e.g., the first superconducting layer <NUM>), and the second superconductor layer (e.g., the second superconducting layer <NUM>) can be the defined area <NUM>.

<FIG> illustrates an example, non-limiting, side cross-sectional view of the structure of the superconducting quantum interference device <NUM> of <FIG> during a fabrication process wherein one or more trenches are etched in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

As illustrated, a first trench <NUM> can be etched (e.g., formed) through the second crystalline silicon layer <NUM> at a first distance from, and adjacent to, the first via <NUM> comprising the first Josephson junction <NUM>. Further, a second trench <NUM> can be etched (e.g., formed) through the second crystalline silicon layer <NUM> at a second distance from, and adjacent to, the second via <NUM> comprising the second Josephson junction <NUM>. The first trench <NUM> and the second trench <NUM> can be utilized to electrically isolate the superconducting quantum interference device <NUM> from the surrounding region and/or other circuits. The second crystalline silicon layer <NUM> can be patterned and etched such that the one or more trenches (e.g., the first trench <NUM> and the second trench <NUM>) penetrate the silicon-on-metal substrate <NUM>.

<FIG> illustrates an example, non-limiting, electrical schematic diagram of an electrical loop <NUM> of the superconducting quantum interference device <NUM> of <FIG> in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

For purposes of explanation, the left side of the electrical loop <NUM> represents the first via <NUM>, wherein the "X" designates the position of the first Josephson junction <NUM> and the right side of the electrical loop <NUM> represents the second via <NUM>, wherein the "X" designates the position of the second Josephson junction <NUM>. Further, the bottom of the electrical loop <NUM> represents the first superconducting layer <NUM> (e.g., the bottom contact) and the top of the electrical loop <NUM> represents the second superconducting layer <NUM> (e.g., the top contact). Thus, the loop can be formed by superconducting material.

The superconducting quantum interference device <NUM> can comprise two or more Josephson junctions with an enclosed loop. The loop can be biased between two electrical potentials. For example, a first electrical potential (V1) can be applied to a first terminal (e.g., the second superconducting layer <NUM>) and a second electrical potential (V2) can be applied to a second terminal (e.g., the first superconducting layer <NUM>). Thus, the potential difference across the loop is V1-V2, which can happen statically or dynamically, such as at high frequencies.

The total supercurrent flowing through the loop is a sum of a first current flowing through the first Josephson junction <NUM> plus the second current flowing through the second Josephson junction <NUM> (Ic1+Ic2). The current flow can be from the first terminal (V1) to the second terminal (V2). An application of a magnetic field perpendicular to the plane of the loop creates a magnetic flux through the loop and can change the supercurrent flowing between the two electrical terminals. The magnetic flux perpendicular to the page (and loop) and coming out of it is ϕ1.

<FIG> illustrates an example, non-limiting, top view of the structure of a first embodiment <NUM> of the electrical loop of the superconducting quantum interference device <NUM> of <FIG> in accordance with one or more embodiments described herein. <FIG> illustrates an example, non-limiting, top view of the structure of a second embodiment <NUM> of the electrical loop of the superconducting quantum interference device <NUM> of <FIG> in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

It is noted that <FIG> and <FIG> do not provide an indication of how contact is made to the top metal (e.g., the second superconducting layer <NUM>) and the bottom metal (e.g., the first superconducting layer <NUM>) in the structures. In addition, the two areas marked by "X" indicate the location of the respective Josephson junctions within the vias. Thus, under the areas marked by "X" is where the tunnel barriers (e.g., the tunnel barrier layer <NUM>, the tunnel barrier layer <NUM>) exist. The "X" does not form a part of the structure of the superconducting quantum interference device <NUM> but is provided for purposes of explaining the various aspects provided herein.

As illustrated, in the first embodiment <NUM> of <FIG>, the second superconducting layer <NUM> can comprise a configuration wherein the top layer, including the portions over the one or more vias (e.g., the first via <NUM> and the second via <NUM>) are substantially the same shape, width and length. However, other configurations can be utilized, such as the second embodiment <NUM> of <FIG>, wherein the second superconducting layer <NUM> is formed in a "dumbbell" type shape. In the second embodiment, a portion of the second superconducting layer <NUM> between the one or more vias is thinner than (e.g., not as wide as) other portions of the second superconducting layer <NUM> over the one or more vias.

Thus, as illustrated in <FIG> and <FIG>, the electrical loop can be shaped differently. It is noted that the one of more Josephson junctions that comprise the tunnel barrier, in cross section, can be designed to be a defined dimension. However, other elements of the electrical loop can be modified. Further, other variations for the shape of the electrical loop can be employed in accordance with various aspects, while maintaining the one or more tunnel barriers at the defined dimension.

With reference again to <FIG>, although illustrated with a first area <NUM> of the second crystalline silicon layer <NUM> and a first section <NUM> of the second superconducting layer <NUM> between the first via <NUM> and the first trench <NUM> and a second area <NUM> of the second crystalline silicon layer <NUM> and a second section <NUM> of the second superconducting layer <NUM> between the second via <NUM> and the second trench <NUM>, the disclosed aspects are not limited to this implementation.

<FIG> illustrates an example, non-limiting, side cross-sectional view of a structure of another superconducting quantum interference device1000 during a fabrication process wherein one or more portions of a second superconducting layer are removed in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

In the embodiment of <FIG>, the first section <NUM> of the second superconducting layer <NUM> between the first via <NUM> and the first trench <NUM> and second section <NUM> of the second superconducting layer <NUM> between the second via <NUM> and the second trench <NUM> can be removed. Accordingly, the area of the second superconducting layer <NUM> overhanging on either side of the first via <NUM> and the second via <NUM> can be removed. Thus, the top superconducting metal (e.g., the second superconducting layer <NUM>) does not extend beyond the vias (e.g., the first via <NUM> and the second via <NUM>). It is noted that in the example of <FIG>, the silicon on either side (e.g., the first area <NUM> and the second area <NUM> of the second crystalline silicon layer <NUM>) remains next to the first via <NUM> (e.g., the first Josephson junction <NUM>) and the second via <NUM> (e.g., the second Josephson junction <NUM>).

Further, the disclosed aspects are not limited to the examples illustrated in <FIG> and <FIG>. In some implementations, the first area <NUM> of the second crystalline silicon layer <NUM> between the first via <NUM> and the first trench <NUM> and the second area <NUM> of the second crystalline silicon layer <NUM> between the second via <NUM> and the second trench <NUM> can also be removed. For example, at substantially the same time, the first section <NUM> and first area <NUM> can be removed, and the second section <NUM> and the second area <NUM> can be removed. Thus, the second superconducting layer and respective portions of the second crystalline silicon layer <NUM> can be etched flush with the respective edges of the one or more vias (e.g., the first via <NUM> and the second via <NUM>).

According to this implementation, respective sides (e.g., one side) of the one or more Josephson junctions can be exposed. For example, one side of the first Josephson junction <NUM> can be exposed by the first trench <NUM> and one side of the second Josephson junction <NUM> can be exposed by the second trench <NUM>.

Advantages of retaining the silicon (e.g., the first area <NUM> and/or the second area <NUM> of the second crystalline silicon layer <NUM>) includes not exposing the structure (e.g., the electrical loop) that includes the one or more Josephson junctions (e.g., the first Josephson junction <NUM> and the second Josephson junction <NUM>) to air. Another advantage of retaining the silicon can be to prevent the one or more Josephson junctions and/or other elements of the electrical loop from being oxidized and/or from being chemically modified.

According to some implementations, there can be multiple superconducting quantum interference devices located on a chip. Thus, if the superconducting quantum interference devices should not be at the same electrical potential, one or more superconducting quantum interference devices can be electrically isolated from one another by etching the respective areas around the superconducting quantum interference devices (e.g., the first trench <NUM> and the second trench <NUM>). Additionally, or alternatively, as discussed herein the top terminal (e.g., the second superconducting layer <NUM>) and the bottom terminal (e.g., the first superconducting layer <NUM>) are discussed as different terminals. However, one of the terminals could be a common terminal for other circuits. For example, a terminal could be a ground terminal for the other circuits and, thus, is not electrically isolated from the other circuits. However, to make the circuits isolated from one another, the etched areas are formed on either side of the superconducting quantum interference device.

<FIG> illustrates an example, non-limiting, top view of a biasing circuit <NUM> for connecting a superconducting quantum interference device through a top and bottom superconducting layer in accordance with one or more embodiments described herein. <FIG> illustrates an example, non-limiting, side cross-sectional view of the biasing circuit <NUM> of <FIG> in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

In the embodiments where the superconducting quantum interference device is isolated from surrounding circuits, to isolate the bottom contact (e.g., the first superconducting layer <NUM>), material around the bottom contact can be etched away. However, once the material is etched (e.g., removed), at every place where there is a top contact (e.g., the second superconducting layer <NUM>), there is a corresponding bottom contact underneath. For example, in order to gain access to the bottom contact, the device has to be etched from the top contact (e.g., the second superconducting layer <NUM>) down to the bottom contact (e.g., through the second crystalline silicon layer <NUM>).

The dashed line <NUM> in <FIG> represents the side cross-sectional area of <FIG>, which is through the middle of the electrical loop. Therefore, as illustrated in <FIG>, the second superconducting layer <NUM> on the top surface <NUM> has a corresponding first superconducting layer <NUM> on the bottom. After the trench (e.g., the first trench <NUM>) is etched, the first superconducting layer <NUM> has two portions, illustrated as a first superconducting layer portion <NUM> (illustrated to the left of the first trench <NUM>) and a second first superconducting layer portion <NUM> (illustrated to the right of the first trench <NUM>).

<FIG> illustrates an example, non-limiting, top view of another biasing circuit <NUM> for creating a transmon qubit utilizing a superconducting quantum interference device in accordance with one or more embodiments described herein. <FIG> illustrates an example, non-limiting, side cross-sectional view of the biasing circuit <NUM> of <FIG> in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

The first arrow <NUM> of <FIG> points towards the superconducting quantum interference device (e.g., toward the bottom of the dashed line <NUM>) and the second arrow <NUM> points towards an interconnect or readout resonator. A transmon with superconducting quantum interference device can use wiring or parallel plates at the end to provide a shunting capacitance, and asymmetric capacitive coupling to resonators using different lengths (of the wires or parallel plates). In the example of <FIG> and <FIG>, the coupling is stronger between the bottom wire of the qubit and the interconnect or readout resonator through a coupling capacitor <NUM>. In this embodiment, a transmon qubit can be created that comprises a shunting capacitor (e.g., between the second superconducting layer <NUM> and the first superconducting layer <NUM> underneath the second crystalline silicon layer <NUM>) in conjunction with the Josephson junction. In some embodiments, the shunting capacitor can be utilized in conjunction with two Josephson junctions.

Beginning from the bottom of the dashed line <NUM> in <FIG> and extending away from the loop and into the top of dashed line <NUM> of <FIG>, the shunting capacitor ends where there is an etch that disconnects the shunting capacitor from another circuit through the dashed line. Accordingly, in an example embodiment, to make the capacitance different, a portion of the second superconducting layer, indicated at <NUM>, can be removed. Therefore, there is an area of the first superconducting layer <NUM>, near the superconducting quantum interference device side, that does not have a corresponding second superconducting layer above it. Thus, the top contact (e.g., the second superconducting layer <NUM>) and the first superconducting layer <NUM> on the superconducting quantum interference device side of the first trench <NUM> can comprise different lengths.

<FIG> illustrates an example, non-limiting, top view of a further biasing circuit <NUM> for a superconducting quantum interference device in accordance with one or more embodiments described herein. <FIG> illustrates an example, non-limiting, side cross-sectional view of the biasing circuit <NUM> of <FIG> in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

The biasing circuit <NUM> is a variation wherein a shape of the termination is changed. The shunting capacitor can be made into a parallel plate capacitor, which can have a variety of shapes (e.g., rectangles, circles, lines, and so on). Two different layers can be utilized to make a capacitor by changing the shape on the top layer (e.g., the second superconducting layer <NUM>). Making the shape slightly different can allow for different coupling to the outside circuits. In this example, the transmon with superconducting quantum interference device can use wiring or parallel plates at the end for the capacitance, and asymmetric capacitive coupling to resonators using different lengths (of the wires or parallel plates). In the example of <FIG> and <FIG>, coupling is stronger between the bottom wire of the qubit and the interconnect or readout resonator through a coupling capacitor <NUM>. The shunting capacitor is illustrated as a rectangular shape on both top and bottom to increase total capacitance.

<FIG> illustrates an example, non-limiting, top view of another biasing circuit <NUM> for a superconducting quantum interference device in accordance with one or more embodiments described herein. <FIG> illustrates an example, non-limiting, side cross-sectional view of the biasing circuit <NUM> of <FIG> in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

The biasing circuit <NUM> can be utilized for a superconducting quantum interference device embodiment (e.g., not necessarily for use as a qubit) and, thus, is a superconducting quantum interference device specific embodiment. In this case, the top and bottom wires can be separated in order to make a contact to the wires for biasing the loop. This can be accomplished by bonding (e.g., wire bond, bump bond) or probing.

A wire (e.g., a piece of metal <NUM>, which can be superconducting metal) can be deposited to provide a pad for bonding and/or probing. The arrow <NUM> is pointing towards the pad for bonding and/or probing. The piece of metal <NUM> can be made in different configurations, such as wider in one or more places such that a probe can be placed directly on it for biasing.

Silicon <NUM> (from the second crystalline silicon layer <NUM>) can remain on top of the indicated section for surface protection against oxidation, according to some implementations. Further, provided is a bottom loop contact <NUM> and a top loop contact <NUM>. Thus, there can be access to the top layer (e.g., the second superconducting layer <NUM>) and access to the bottom layer (e.g., the first superconducting layer <NUM> or the second superconducting metal <NUM>). In such a manner, an electrical bias can be placed on the bottom loop contact <NUM> and the top loop contact <NUM> (e.g., a bias between the two terminals of the superconducting quantum interference device).

<FIG> illustrates an example, non-limiting, electrical schematic diagram of a first embodiment of flux control with a single wire <NUM> in accordance with one or more embodiments described herein. <FIG> illustrates an example, non-limiting, electrical schematic diagram of a second embodiment of flux control with a single wire <NUM> in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

To exert flux control, if there is a current flowing through a wire, the current generates a magnetic field around the wire. Given a defined distance from the wire, the magnetic field has a given magnitude (usually a constant for a given distance). That magnitude can be constant around a circle around the loop. While looking into a cross-sectional cut through the wire, a circle around the center of the wire would have a magnetic field flowing around that circle. Some of the magnetic field can be intercepted if there is a plane near it (e.g., some of the magnetic field gets intercepted into that plane; the component of that field that is perpendicular to that plane is the relevant quantity for those skilled in the art). One way for exerting magnetic flux control is to pass a current through a wire next to the plane. Thus, there is a superconducting quantum interference device loop, which can be vertical on the left, and there is a wire <NUM> with coordinates X, Y, and Z. The superconducting quantum interference device loop is mostly contained in the X and Z plane of the coordinate system. The wire <NUM> can be completely contained in the X and Y plane. In <FIG>, the wire <NUM> is drawn close to the superconducting quantum interference device loop in the Y direction. Therefore, the portion of the wire <NUM> that is parallel to the top of the superconducting quantum interference device loop (e.g., near the second superconducting layer <NUM>) generates a magnetic field that penetrates the area of the SQUID loop. This would be a source of the magnetic flux through the SQUID loop and this would be the purpose of the wire that is put there. <FIG> illustrates a similar situation where the wire <NUM> is drawn near the bottom of the superconducting quantum interference device loop.

As indicated, the current (I) through the wire (e.g., the wire <NUM>, the wire <NUM>) produces a circular magnetic field around the wire. The magnetic field from the wire threads the superconducting quantum interference device loop, producing the magnetic flux ϕ1 through the superconducting quantum interference device. The horizontal portion of the wire is parallel to the top horizontal edge of the superconducting quantum interference device loop, but at a different Y coordinate. The horizontal portion of the wire can also be parallel to the bottom horizontal edge of the superconducting quantum interference device loop, as illustrated in <FIG>, and in <FIG> and <FIG> below.

<FIG> illustrates an example, non-limiting, top view of a flux control circuit <NUM> for control through a top superconducting layer of a superconducting quantum interference device in accordance with one or more embodiments described herein. <FIG> illustrates an example, non-limiting, side cross-sectional view of the flux control circuit <NUM> of <FIG> at line <NUM> in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

As illustrated, there can be a metal layer (e.g., a wire <NUM>) that can be parallel to the superconducting quantum interference device loop. As illustrated in <FIG>, the wire <NUM> is parallel and closest to the top of the second superconducting layer <NUM>. The wire <NUM> can be made in the second superconducting layer <NUM>. Thus, the control of the superconducting quantum interference device is through a top superconductor. This would be one way of applying magnetic flux through the SQUID loop.

<FIG> illustrates an example, non-limiting, top view of another embodiment of a flux control circuit <NUM> for flux control through a bottom superconducting layer of a superconducting quantum interference device in accordance with one or more embodiments described herein. <FIG> illustrates an example, non-limiting, side cross-sectional view of the flux control circuit <NUM> of <FIG> at line <NUM> in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

As illustrated, a wire <NUM> can be parallel to the superconducting quantum interference device loop near the first crystalline silicon layer <NUM>. The wire <NUM> can be utilized to generate a magnetic flux through the SQUID loop.

It is noted that the top view of <FIG> does not illustrate the second crystalline silicon layer <NUM> over the wire <NUM> for purposes of describing the invention, while the side cross-sectional view shows the second crystalline silicon layer <NUM> over the wire <NUM>. However, according to some implementations, the second crystalline silicon layer <NUM> can be removed from over the wire <NUM>. Benefits of retaining the second crystalline silicon layer <NUM> can be to protect the device from oxidation and/or exposure to elements. Benefits of removing the second crystalline silicon layer <NUM> include simplifying the fabrication of the device because the second crystalline silicon layer <NUM> can be etched down and the wire <NUM> can be completely exposed.

<FIG> illustrates an example, non-limiting, electrical schematic diagram of a third embodiment of flux control with a single wire <NUM> in accordance with one or more embodiments described herein. <FIG> illustrates an example, non-limiting, electrical schematic diagram of a fourth embodiment of flux control with a single wire <NUM> in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

Instead of the wire with bends, as illustrated in <FIG> and <FIG>, the wire (e.g., wire <NUM> of <FIG> and wire <NUM> of <FIG>) can be a straight wire, preserving the porting that is parallel to the horizontal edge of the superconducting quantum interference device loop. The horizontal wire (e.g., the wire <NUM>, the wire <NUM>) is still at the same height (Z-coordinate) as the horizontal edge of the superconducting quantum interference device loop, but offset in the Y-direction.

<FIG> illustrates an example, non-limiting, electrical schematic diagram of a fifth embodiment of flux control with a single wire <NUM> in accordance with one or more embodiments described herein. A wire <NUM> can carry a current I and can produce a magnetic field. In this embodiment, both horizontal portions (X) parallel to the loop and the vertical portion (Z) of the wire <NUM> can generate the magnetic flux through the loop.

The magnetic field from the wire <NUM> threads the superconducting quantum interference device loop, producing the magnetic flux ϕ1 through the superconducting quantum interference device. The vertical and horizontal edges of the wire are parallel to the vertical and horizontal edges of the superconducting quantum interference device loop, respectively, just shifted in the Y coordinate (into the depth of the page).

<FIG> illustrates an example, non-limiting, electrical schematic diagram of an embodiment of flux control with a multiple (parallel) wires <NUM> in accordance with one or more embodiments described herein.

Illustrated are three wires, namely, a first wire <NUM>, a second wire <NUM>, and a third wire <NUM>. Respective wires carry a current and produce respective magnetic fields. Thus, the first wire <NUM> carries a first current and produces a first magnetic field, the second wire <NUM> carries a second current and produces a second magnetic field, and the third wire <NUM> carries a third current and produces a third magnetic field.

The total magnetic field adds up from the multiple wires. The magnetic field from the wires threads the superconducting quantum interference device loop, producing the magnetic flux ϕ1 through the superconducting quantum interference device. Multiple wires can generate a larger magnetic field than can be produced by a single wire carrying the same current. It is noted that the wires (e.g., the first wire <NUM>, the second wire <NUM>, and the third wire <NUM>) are offset in the Y direction.

<FIG> illustrates an example, non-limiting, top view of an embodiment of a flux control circuit <NUM> using multiple wires for flux control of a superconducting quantum interference device in accordance with one or more embodiments described herein. <FIG> illustrates an example, non-limiting, side cross-sectional view of the flux control circuit <NUM> of <FIG> at cross-section line <NUM> in accordance with one or more embodiments described herein. <FIG> illustrates an example, non-limiting, side cross-sectional view of the flux control circuit <NUM> of <FIG> at cross-section line two <NUM> in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

Control of a superconducting quantum interference device can be through multiple wires in parallel (e.g., the first wire <NUM>, the second wire <NUM>, and the third wire <NUM>) that form loops in parallel, for added flux applied to the superconducting quantum interference device. Further, etching a region around the superconducting quantum interference device (e.g., shaping a bottom wire) can be a last step.

<FIG> illustrates an example, non-limiting electrical schematic diagram of an embodiment <NUM> of a tunable transmon qubit using a superconducting quantum interference device in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

To form a (tunable) transmon qubit, the superconducting quantum interference device loop can be shunted by a capacitor <NUM> (in parallel with the superconducting quantum interference device). The total capacitance in parallel with the Josephson junctions should be of a specific value to form a transmon qubit. The capacitor <NUM> can be implemented either by utilizing substantially parallel elongated wires, as illustrated in <FIG> and <FIG>, or substantially parallel plates (with larger area to increase the total capacitance), as illustrated in <FIG> and <FIG>.

The two junctions (e.g., the first Josephson junction <NUM>, the second Josephson junction <NUM>) in the superconducting quantum interference device loop can have the same or different critical currents, making it a symmetric or an asymmetric superconducting quantum interference device. The superconducting quantum interference device can be flux biased with a magnetic flux as discussed above. The transmon qubit can be coupled to other qubits as well as external circuitry (read/write) according to some implementations.

As discussed herein, according to some implementations, a vertical superconducting quantum interference device is provided that is oriented differently from traditional superconducting quantum interference devices, allows for different coupling and biasing geometries, and occupies minimal footprint as compared to traditional superconducting quantum interference devices. Also provided is the capability of magnetically controlling the device through nearby/local superconducting wires and interconnects. In addition, fields parallel to the substrate can be used or detected as compared to traditional superconducting quantum interference devices.

Further, a crystalline dielectric enables superior loss characteristics and circuit performance for qubits as compared to conventional techniques in which superconducting quantum interference device loops orthogonal to the surface can utilize deposited dielectrics and therefore are not useful as qubits.

<FIG> illustrates a flow diagram of an example, non-limiting, method <NUM> for fabricating a superconducting quantum interference device in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

The method <NUM> can include, at <NUM>, forming a silicon-on-metal substrate comprising a first superconducting layer (e.g., the first superconducting layer <NUM>) between a first crystalline silicon layer (e.g., the first crystalline silicon layer <NUM>) and a second crystalline silicon layer (e.g., the second crystalline silicon layer <NUM>). The first superconducting layer can comprise a first superconducting material. A shape of the second superconducting layer can be selected based on a defined shape of the electrical loop.

Further, at <NUM>, the method <NUM> can comprise forming a first via (e.g., the first via <NUM>) and a second via (e.g., the second via <NUM>). The first via can be formed between, and in contact with, a first section of the first superconducting layer and a first portion of a second superconducting layer. The first via can comprise a first Josephson junction (e.g., the first Josephson junction <NUM>). Further, the second superconducting layer can be over the second crystalline silicon layer and can comprise a second superconducting material.

A second via can be formed between, and in contact with, a second section of the first superconducting layer and a second portion of the second superconducting layer. The second via can comprise a second Josephson junction (e.g., the second Josephson junction <NUM>). An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.

<FIG> illustrates a flow diagram of an example, non-limiting, method <NUM> for forming a second superconducting layer of a superconducting quantum interference device in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

At <NUM> of the method, a first side of the second superconducting layer can be etched flush with a first edge of the silicon-on-metal substrate and a second side of the second superconducting layer can be flush with a second edge of the silicon-on-metal substrate. For example, the first side of the second superconducting layer, can be a first portion of the second superconducting layer that extends in an outward direction to the left of the first via as illustrated in <FIG>. Further, the second side of the second superconducting layer, can be a second portion of the second superconducting layer that extends in an outward direction to the right of the first via as illustrated in <FIG>.

According to an example, the first edge can be the first side of the second superconducting layer that is flush with a first trench (e.g., the first trench <NUM>), as illustrated in <FIG>. The second edge of the second superconducting layer can be the second side of the second superconducting layer that is flush with a second trench (e.g., the second trench <NUM>), as illustrated in <FIG>.

In another example, the first edge can be can be the first side of the second superconducting layer that is flush with the first via and the second edge of the second superconducting layer that is flush with a second via, as illustrated in <FIG>. According to this example, a first section (e.g., the first section <NUM>) of the second superconducting layer between the first via and the first trench and a second section (e.g., the second section <NUM>) of the second superconducting layer between the second via and the second trench can be removed.

<FIG> illustrates a flow diagram of an example, non-limiting, method <NUM> for electrically isolating a superconducting quantum interference device in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

At <NUM>, a first trench (e.g., the first trench <NUM>) can be formed through the second crystalline silicon layer a first distance from, and adjacent to, the first via comprising the first Josephson junction. According to some implementations, the first distance can comprise at least a portion of silicon (e.g., the second crystalline silicon layer <NUM>) between the first Josephson junction and the first trench. However, in accordance with other implementations, there is no silicon between the first Josephson junction and the first trench (e.g., a side of the first Josephson junction is exposed).

Further, at <NUM>, a second trench (e.g., the second trench <NUM>) can be formed through the second crystalline silicon layer a second distance from, and adjacent to, the second via comprising the second Josephson junction. According to some implementations, the second distance can comprise at least a portion of silicon (e.g., the second crystalline silicon layer <NUM>) between the second Josephson junction and the second trench. However, in accordance with other implementations, there is no silicon between the second Josephson junction and the second trench (e.g., a side of the second Josephson junction is exposed).

<FIG> illustrates a flow diagram of an example, non-limiting, method <NUM> for providing a biasing circuit for a superconducting quantum interference device in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

At <NUM> of the method <NUM>, providing at least one of a first external electrical connection at the first superconducting layer or a second electrical connection at the second superconducting layer. For example, electrical biasing can be provided through both the first superconducting layer and the second superconducting layer. In another example, a coupling capacitor (e.g., the coupling capacitor <NUM>) can be placed over the second crystalline silicon layer and at a first distance from the electrical loop and near an interconnect for an external electrical connection.

<FIG> illustrates a flow diagram of an example, non-limiting, method <NUM> for providing flux control circuitry for a superconducting quantum interference device in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

At <NUM> of the method <NUM>, a wire can be provided parallel to the electrical loop. For example, a wire (e.g., the wire <NUM>) can be provided over the second crystalline silicon layer for control of the magnetic flux through the electrical loop of the superconducting quantum interference devices. Alternatively, or additionally, a wire (e.g., the wire <NUM>) can be provided over the first crystalline silicon layer for control of the magnetic flux through the electrical loop of the superconducting quantum interference device.

<FIG> illustrates a flow diagram of an example, non-limiting, method <NUM> for providing multiple parallel wires for flux control circuitry for a superconducting quantum interference device in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

At <NUM> of the method <NUM>, two or more wires (e.g., the first wire <NUM>, the second wire <NUM>, the third wire <NUM>) can be provided in parallel over the first superconducting layer. The two or more wires can form parallel electrical loops. Respective wire carries its own current and produces a magnetic field. Thus, a first wire can carry a first current and produces a first magnetic field, a second wire can carry a second current and produces a second magnetic field, and a third wire can carry a third current and produces a third magnetic field.

Disclosed embodiments and/or aspects should neither be presumed to be exclusive of other disclosed embodiments and/or aspects, nor should a device and/or structure be presumed to be exclusive to its depicted elements in an example embodiment or embodiments of this disclosure, unless where clear from context to the contrary. The scope of the disclosure is generally intended to encompass modifications of depicted embodiments with additions from other depicted embodiments, where suitable, interoperability among or between depicted embodiments, where suitable, as well as addition of a component(s) from one embodiment(s) within another or subtraction of a component(s) from any depicted embodiment, where suitable, aggregation of elements (or embodiments) into a single devices achieving aggregate functionality, where suitable, or distribution of functionality of a single device into multiple device, where suitable. In addition, incorporation, combination or modification of devices or elements depicted herein or modified as stated above with devices, structures, or subsets thereof not explicitly depicted herein but known in the art or made evident to one with ordinary skill in the art through the context disclosed herein are also considered within the scope of the present disclosure.

For simplicity of explanation, the computer-implemented methodologies are depicted and described as a series of acts. It is to be understood and appreciated that the subject innovation is not limited by the acts illustrated and/or by the order of acts, for example acts can occur in various orders and/or concurrently, and with other acts not presented and described herein. Furthermore, not all illustrated acts can be required to implement the computer-implemented methodologies in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that the computer-implemented methodologies could alternatively be represented as a series of interrelated states via a state diagram or events. Additionally, it should be further appreciated that the computer-implemented methodologies disclosed hereinafter and throughout this specification are capable of being stored on an article of manufacture to facilitate transporting and transferring such computer-implemented methodologies to computers. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage media.

In order to provide a context for the various aspects of the disclosed subject matter, <FIG> as well as the following discussion are intended to provide a general description of a suitable environment in which the various aspects of the disclosed subject matter can be implemented. <FIG> illustrates a block diagram of an example, non-limiting operating environment in which one or more embodiments described herein can be facilitated. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity. With reference to <FIG>, a suitable operating environment <NUM> for implementing various aspects of this invention can also include a computer <NUM>. The computer <NUM> can also include a processing unit <NUM>, a system memory <NUM>, and a system bus <NUM>. The system bus <NUM> couples system components including, but not limited to, the system memory <NUM> to the processing unit <NUM>. The processing unit <NUM> can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit <NUM>. The system bus <NUM> can be any of several types of bus structure(s) including the memory bus or memory controller, a peripheral bus or external bus, and/or a local bus using any variety of available bus architectures including, but not limited to, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE <NUM>), and Small Computer Systems Interface (SCSI). The system memory <NUM> can also include volatile memory <NUM> and nonvolatile memory <NUM>. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer <NUM>, such as during start-up, is stored in nonvolatile memory <NUM>. By way of illustration, and not limitation, nonvolatile memory <NUM> can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory <NUM> can also include random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM.

Computer <NUM> can also include removable/non-removable, volatile/non-volatile computer storage media. <FIG> illustrates, for example, a disk storage <NUM>. Disk storage <NUM> can also include, but is not limited to, devices like a magnetic disk drive, floppy disk drive, tape drive, Jaz drive, Zip drive, LS-<NUM> drive, flash memory card, or memory stick. The disk storage <NUM> also can include storage media separately or in combination with other storage media including, but not limited to, an optical disk drive such as a compact disk ROM device (CD-ROM), CD recordable drive (CD-R Drive), CD rewritable drive (CD-RW Drive) or a digital versatile disk ROM drive (DVD-ROM). To facilitate connection of the disk storage <NUM> to the system bus <NUM>, a removable or non-removable interface is typically used, such as interface <NUM>. <FIG> also depicts software that acts as an intermediary between users and the basic computer resources described in the suitable operating environment <NUM>. Such software can also include, for example, an operating system <NUM>. Operating system <NUM>, which can be stored on disk storage <NUM>, acts to control and allocate resources of the computer <NUM>. System applications <NUM> take advantage of the management of resources by operating system <NUM> through program modules <NUM> and program data <NUM>, e.g., stored either in system memory <NUM> or on disk storage <NUM>. It is to be appreciated that this invention can be implemented with various operating systems or combinations of operating systems. A user enters commands or information into the computer <NUM> through input device(s) <NUM>. Input devices <NUM> include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit <NUM> through the system bus <NUM> via interface port(s) <NUM>. Interface port(s) <NUM> include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device(s) <NUM> use some of the same type of ports as input device(s) <NUM>. Thus, for example, a USB port can be used to provide input to computer <NUM>, and to output information from computer <NUM> to an output device <NUM>. Output adapter <NUM> is provided to illustrate that there are some output devices <NUM> like monitors, speakers, and printers, among other output devices <NUM>, which require special adapters. The output adapters <NUM> include, by way of illustration and not limitation, video and sound cards that provide a method of connection between the output device <NUM> and the system bus <NUM>. It should be noted that other devices and/or systems of devices provide both input and output capabilities such as remote computer(s) <NUM>.

Computer <NUM> can operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s) <NUM>. The remote computer(s) <NUM> can be a computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device or other common network node and the like, and typically can also include many or all of the elements described relative to computer <NUM>. For purposes of brevity, only a memory storage device <NUM> is illustrated with remote computer(s) <NUM>. Remote computer(s) <NUM> is logically connected to computer <NUM> through a network interface <NUM> and then physically connected via communication connection <NUM>. Network interface <NUM> encompasses wire and/or wireless communication networks such as local-area networks (LAN), wide-area networks (WAN), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring and the like. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL). Communication connection(s) <NUM> refers to the hardware/software employed to connect the network interface <NUM> to the system bus <NUM>. While communication connection <NUM> is shown for illustrative clarity inside computer <NUM>, it can also be external to computer <NUM>. The hardware/software for connection to the network interface <NUM> can also include, for exemplary purposes only, internal and external technologies such as, modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

The present invention may be a system, a method, an apparatus and/or a computer program product at any possible technical detail level of integration. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium can also include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing.

These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create method for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks. The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational acts to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

While the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on a computer and/or computers, those skilled in the art will recognize that this invention also can be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and/or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive computer-implemented methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, mini-computing devices, mainframe computers, as well as computers, hand-held computing devices (e.g., PDA, phone), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all aspects of this invention can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

As used in this application, the terms "component," "system," "platform," "interface," and the like, can refer to and/or can include a computer-related entity or an entity related to an operational machine with one or more specific functionalities. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between two or more computers. In another example, respective components can execute from various computer readable media having various data structures stored thereon. The components can communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems via the signal). As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts, wherein the electronic components can include a processor or other method to execute software or firmware that confers at least in part the functionality of the electronic components. In an aspect, a component can emulate an electronic component via a virtual machine, e.g., within a cloud computing system.

As it is employed in the subject specification, the term "processor" can refer to substantially any computing processing unit or device comprising, but not limited to, single-core processors; single-processors with software multithread execution capability; multi-core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, processors can exploit nano-scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. A processor can also be implemented as a combination of computing processing units. In this specification, terms such as "store," "storage," "data store," data storage," "database," and substantially any other information storage component relevant to operation and functionality of a component are utilized to refer to "memory components," entities embodied in a "memory," or components comprising a memory. It is to be appreciated that memory and/or memory components described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of illustration, and not limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM). Volatile memory can include RAM, which can act as external cache memory, for example. By way of illustration and not limitation, RAM is available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of systems or computer-implemented methods herein are intended to include, without being limited to including, these and any other suitable types of memory.

Claim 1:
A superconducting quantum interference device, SQUID, structure comprising:
a silicon-on-metal substrate comprising a first superconducting layer (<NUM>) between a first crystalline silicon layer (<NUM>) and a second crystalline silicon layer (<NUM>), the first superconducting layer comprising a first superconducting material;
a first via (<NUM>) between, and in contact with, a first section of the first superconducting layer and a first portion (<NUM>) of a second superconducting layer (<NUM>), the first via comprises a first Josephson junction (<NUM>), and the second superconducting layer is over the second crystalline silicon layer and comprises a second superconducting material; and
a second via (<NUM>) between, and in contact with, a second section of the first superconducting layer and a second portion (<NUM>) of the second superconducting layer, the second via comprises a second Josephson junction (<NUM>), wherein an electrical loop around a defined area of the second crystalline silicon layer comprises the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.