Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit. <CIT> discloses a three-dimensional memory device is provided, which comprises: a lower-interconnect-level dielectric material layer located over a substrate and embedding lower-interconnect level metal interconnect structures and <CIT> discloses a method of forming a semiconductor structure with through stair contacts.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

The invention provides a method for forming a three-dimensional memory device according to claim <NUM>, and a three-dimensional memory device according to claim <NUM>.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

A layer can extend laterally, vertically, and/or along a tapered surface.

In some 3D memory devices, through stair contacts (TSCs) are used for providing vertical interconnects between a memory device and a peripheral device. In addition, dummy channel structures are used for providing structural support for the memory device. In existing fabrication processes, TSCs and dummy channel structures are formed in separate steps using different patterns. Because each pattern consumes its own share of real estate on a die, the available area on the die for other patterns becomes limited.

<FIG> illustrate related art using different patterns to form dummy channel structures and TSCs in separate fabrication steps. As shown in <FIG>, a memory device <NUM> includes a memory stack <NUM> above a substrate <NUM>. Memory stack <NUM> may include an array of memory strings <NUM> and may include a staircase structure <NUM>. An array of dummy channel structures <NUM> can be formed by first etching an array of dummy holes using a dummy pattern, and then filling the dummy holes with a dielectric layer to form the dummy channel structure <NUM>. After forming dummy channel structure <NUM>, sacrificial layer <NUM> that are initially formed as part of a dielectric stack including interleaved dielectric layer <NUM> and sacrificial layer <NUM> can be replaced by conductor layers to form word lines. After the word lines are formed, a TSC pattern can be used to etch an array of TSC holes, which are subsequently filled by a conductor layer to form TSC <NUM>. The above-described fabrication processes utilize different patterns (a dummy channel structure pattern and a TSC pattern) to form dummy channel structure <NUM> and TSC <NUM>, respectively, in separate fabrication steps.

Various embodiments in accordance with the present disclosure provide a 3D memory device having TSCs sharing the same pattern for forming the dummy channel structures, which improves the efficiency of die usage. For example, by combining two separate patterns into a single pattern, the available area on the die may be increased, allowing placement of additional patterns. Moreover, various embodiments of methods for forming the 3D memory device disclosed herein can allow TSCs to be formed in the same fabrication process(es) for making other structures (e.g., peripheral contacts) and thus, further simplify the fabrication flow and reduce process cost.

<FIG> illustrates a cross-section of an exemplary 3D memory device <NUM>, according to some embodiments of the present disclosure. 3D memory device <NUM> can include a substrate <NUM>, which can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable materials. In some embodiments, substrate <NUM> is a thinned substrate (e.g., a semiconductor layer), which was thinned from a normal thickness by grinding, wet/dry etching, chemical mechanical polishing (CMP), or any combination thereof.

3D memory device <NUM> can include a memory stack <NUM> above substrate <NUM>. Memory stack <NUM> can be a stacked storage structure through which memory strings (e.g., NAND memory strings <NUM>) are formed. In some embodiments, memory stack <NUM> includes a plurality of conductor/dielectric layer pairs stacked vertically above substrate <NUM>. Each conductor/dielectric layer pair can include a conductor layer <NUM> and a dielectric layer <NUM>. That is, memory stack <NUM> can include interleaved conductor layers <NUM> and dielectric layers <NUM> stacked vertically. As shown in <FIG>, each NAND memory string <NUM> extends vertically through interleaved conductor layers <NUM> and dielectric layers <NUM> in memory stack <NUM>. In some embodiments, 3D memory device <NUM> is a NAND Flash memory device in which memory cells are provided at intersections of NAND memory strings <NUM> and conductor layers <NUM> (functioning as word lines) of 3D memory device <NUM>. The number of conductor/dielectric layer pairs in memory stack <NUM> (e.g., <NUM>, <NUM>, <NUM>, or <NUM>) can set the number of memory cells in 3D memory device <NUM>.

Conductor layers <NUM> can each have the same thickness or have different thicknesses. Similarly, dielectric layers <NUM> can each have the same thickness or have different thicknesses. Conductor layers <NUM> can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicides, or any combination thereof. Dielectric layers <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, conductor layers <NUM> include metals, such as W, and dielectric layers <NUM> include silicon oxide. It is understood that a silicon oxide film (not shown), such as an in-situ steam generation (ISSG) silicon oxide, can be formed between substrate <NUM> (e.g., a silicon substrate) and memory stack <NUM>, according to some embodiments.

It is noted that x, y, and z axes are added to <FIG> to further illustrate the spatial relationship of the components in 3D memory device <NUM> (y-direction points into the page). The x-, y-, and z-directions are perpendicular to one another. Substrate <NUM> includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction and y-direction (the lateral direction) in the x-y plane. As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D memory device <NUM>) is determined relative to the substrate (e.g., substrate <NUM>) of the semiconductor device in the z-direction (the vertical direction) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing spatial relationship is applied throughout the present disclosure.

In some embodiments, 3D memory device <NUM> is part of a monolithic 3D memory device, in which the components of the monolithic 3D memory device (e.g., memory cells and peripheral devices) are formed on a single substrate (e.g., substrate <NUM>). Peripheral devices <NUM>, such as any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM>, can be formed on substrate <NUM> as well, outside of memory stack <NUM>. Peripheral device <NUM> can be formed "on" substrate <NUM>, where the entirety or part of peripheral device <NUM> is formed in substrate <NUM> (e.g., below the top surface of substrate <NUM>) and/or directly on substrate <NUM>. Peripheral device <NUM> can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors). Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of the transistors) can be formed in substrate <NUM> as well, outside of memory stack <NUM>. It is understood that in some embodiments, peripheral devices <NUM> are formed above or below NAND memory strings <NUM>, as opposed to on the side of NAND memory strings <NUM> as shown in <FIG>. It is further understood that in some embodiments, 3D memory device <NUM> is part of a non-monolithic 3D memory device, in which the components are formed separately on different substrates and then bonded in a face-to-face manner, a face-to-back manner, or a back-to-back manner. Peripheral devices <NUM> can be formed on a separate substrate different from substrate <NUM>.

As shown in <FIG>, memory stack <NUM> can include an inner region <NUM> (also known as a "core array region") and an outer region <NUM> (also known as a "staircase region"). In some embodiments, inner region <NUM> is the center region of memory stack <NUM> where an array of NAND memory strings <NUM> are formed through the conductor/dielectric layer pairs, and outer region <NUM> is the remaining region of memory stack <NUM> surrounding inner region <NUM> (including the sides and edges) without NAND memory strings <NUM>.

As shown in <FIG>, each NAND memory string <NUM> can include a channel structure <NUM> extending vertically through the conductor/dielectric layer pairs in inner region <NUM> of memory stack <NUM>. Channel structure <NUM> can include a channel hole filled with semiconductor materials (e.g., forming a semiconductor channel) and dielectric materials (e.g., forming a memory film). In some embodiments, the semiconductor channel includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, the memory film is a composite layer including a tunneling layer, a storage layer (also known as a "charge trap/storage layer"), and a blocking layer. Each NAND memory string <NUM> can have a cylinder shape (e.g., a pillar shape). The semiconductor channel, tunneling layer, storage layer, and blocking layer are arranged along a direction from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof.

In some embodiments, NAND memory strings <NUM> include a plurality of control gates (each being part of a word line/conductor layer <NUM>) for NAND memory strings <NUM>. Conductor layer <NUM> in each conductor/dielectric layer pair can function as a control gate for memory cells of NAND memory string <NUM>. Conductor layer <NUM> can include multiple control gates for multiple NAND memory strings <NUM> and can extend laterally as a word line ending in outer region <NUM> of memory stack <NUM>.

In some embodiments, NAND memory string <NUM> includes two plugs <NUM> and <NUM> at a respective end in the vertical direction. Each plug <NUM> or <NUM> can be in contact with a respective end of channel structure <NUM>. Plug <NUM> can include a semiconductor material, such as silicon, that is epitaxially grown from substrate <NUM>. Plug <NUM> can function as the channel controlled by a source select gate of NAND memory string <NUM>. Plug <NUM> can be at the lower end of NAND memory string <NUM> and in contact with channel structure <NUM> (e.g., on the lower end of channel structure <NUM>). As used herein, the "upper end" of a component (e.g., NAND memory string <NUM>) is the end father away from substrate <NUM> in the z-direction, and the "lower end" of the component (e.g., NAND memory string <NUM>) is the end closer to substrate <NUM> in the z-direction when substrate <NUM> is positioned in the lowest plane of 3D memory device <NUM>.

Plug <NUM> can include semiconductor materials (e.g., polysilicon) or conductor materials (e.g., metals). In some embodiments, plug <NUM> includes an opening filled with titanium/titanium nitride (Ti/TiN as a barrier layer) and tungsten (as a conductor). By covering the upper end of channel structure <NUM> during the fabrication of 3D memory device <NUM>, plug <NUM> can function as an etch stop layer to prevent etching of dielectrics filled in channel structure <NUM>, such as silicon oxide and silicon nitride. In some embodiments, plug <NUM> functions as the drain of NAND memory string <NUM>.

As shown in <FIG>, at least on one side in the lateral direction (e.g., in the x-direction), outer region <NUM> of memory stack <NUM> can include a staircase structure <NUM>. In some embodiments, another staircase structure (not shown) is disposed on the opposite side of memory stack <NUM> in the x-direction. Each "level" of staircase structure <NUM> can include one or more conductor/dielectric layer pairs, each including conductor layer <NUM> and dielectric layer <NUM>. The top layer in each level of staircase structure <NUM> can be conductor layer <NUM> for interconnection in the vertical direction. In some embodiments, each two adjacent levels of staircase structure <NUM> are offset by a nominally same distance in the vertical direction and a nominally same distance in the lateral direction. For each two adjacent levels of staircase structure <NUM>, the first level (and conductor layer and dielectric layer therein) that is closer to substrate <NUM> can extend laterally further than the second level (and conductor layer and dielectric layer therein), thereby forming a "landing area" on the first level for interconnection in the vertical direction.

Staircase structure <NUM> can be used for landing word line contacts <NUM>. The lower end of each word line contact <NUM> can be in contact with top conductor layer <NUM> (word line) in a respective level of staircase structure <NUM> to individually address a corresponding word line of 3D memory device <NUM>. Word line contact <NUM> can include an opening (e.g., a via hole or a trench) extending vertical through one or more dielectric layers and filled with conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof.

As shown in <FIG>, <FIG> memory device <NUM> further includes TSCs <NUM> each extending vertically through the conductor/dielectric layer pairs in staircase structure <NUM>. Each TSC <NUM> can extend vertically through interleaved conductor layers <NUM> and dielectric layers <NUM>. In some embodiments, TSC <NUM> can extend through the entire thickness of staircase structure <NUM> (e.g., all the conductor/dielectric layer pairs in the vertical direction at a lateral position of staircase structure <NUM>) and reach substrate <NUM>. In some embodiments, TSC <NUM> further extends through at least part of substrate <NUM>. TSC <NUM> can carry electrical signals from and/or to 3D memory device <NUM>, such as part of the power bus, with shorten interconnect routing. In some embodiments, TSC <NUM> can provide electrical connections between 3D memory device <NUM> and peripheral device <NUM> and/or between back-end-of-line (BEOL) interconnects (not shown) and peripheral device <NUM>. TSC <NUM> can also provide mechanical support to staircase structure <NUM>.

TSC <NUM> can be formed by filling materials in a vertical opening through staircase <NUM>. In some embodiments, TSC <NUM> includes a conductor layer <NUM> surrounded by a spacer <NUM>. For example, the sidewall of TSC <NUM> may be in contact with spacer <NUM>. Conductor layer <NUM> can include conductive materials, including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. Spacer <NUM> can electrically insulate conductor layer <NUM> of TSC <NUM> from surrounding conductor layers <NUM> in staircase structure <NUM>. In some embodiments, TSC <NUM> has a substantially circular shape in the plan view, and conductor layer <NUM> and spacer <NUM> are disposed radially from the center of TSC <NUM> in this order. Spacer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in <FIG>, <FIG> memory device <NUM> further includes peripheral contacts <NUM> extending vertically through one or more dielectric layers and in contact with peripheral devices <NUM> outside of memory stack <NUM>. Peripheral contact <NUM> can provide electrical connections with peripheral devices <NUM>. Peripheral contact <NUM> can be formed by filling materials in a vertical opening. According to the invention, similar to TSC <NUM>, peripheral contact <NUM> includes a conductor layer <NUM> surrounded by a spacer <NUM>. Conductor layer <NUM> can include conductive materials, including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. In some embodiments, peripheral contact <NUM> has a substantially circular shape in the plan view, and conductor layer <NUM> and spacer <NUM> are disposed radially from the center of peripheral contact <NUM> in this order. Spacer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, spacer <NUM> and spacer <NUM> have nominally the same thickness in the lateral direction (e.g., radial direction). In some embodiments, both spacer <NUM> and spacer <NUM> include silicon oxide. It is understood that peripheral devices <NUM> may not be formed on substrate <NUM>, and peripheral contacts <NUM> may be in a different configuration in some embodiments, for example, in which 3D memory device <NUM> is a non-monolithic 3D memory device.

It is understood that 3D memory device <NUM> can include additional components and structures not shown in <FIG> including, but not limited to, other local contacts and interconnects in one or more BEOL interconnect layers above memory stack <NUM> and/or below substrate <NUM>.

<FIG> illustrate an exemplary fabrication process for forming channel structures and staircase structures of a 3D memory device, according to some embodiments of the present disclosure. <FIG> illustrate an exemplary fabrication process for forming TSCs, peripheral contacts, and word line contacts of a 3D memory device, according to various embodiments of the present disclosure. <FIG> illustrate another exemplary fabrication process for forming TSCs, peripheral contacts, and word line contacts of a 3D memory device, according to some embodiments of the present disclosure. <FIG> are flowcharts of exemplary methods <NUM>, <NUM>', and <NUM>" for forming a 3D memory device, according to some embodiments. Examples of the 3D memory device depicted in <FIG> include 3D memory device <NUM> depicted in <FIG>. <FIG> will be described together. It is understood that the operations shown in methods <NUM>, <NUM>', and <NUM>" are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which a dielectric stack including a plurality of interleaved dielectric layers and sacrificial layers is formed on a substrate. The substrate can be a silicon substrate. Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a channel structure extending vertically through the dielectric stack is formed. Method <NUM> proceeds to operation <NUM>, in which a staircase structure is formed on one side of the dielectric stack.

As illustrated in <FIG>, a dielectric deck <NUM> including a plurality of interleaved dielectric layers and sacrificial layers is formed on a silicon substrate <NUM>. In some embodiments, sacrificial layers <NUM> and dielectric layers <NUM> are alternatingly deposited by one or more thin film deposition processes including, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, sacrificial layers <NUM> include silicon nitride, and dielectric layers <NUM> include silicon oxide. It is understood that the sequence of depositing sacrificial layers <NUM> and dielectric layers <NUM> is not limited. The deposition can start with sacrificial layer <NUM> or dielectric layer <NUM> and can end with sacrificial layer <NUM> or dielectric layer <NUM>.

As illustrated in <FIG>, an array of channel structures <NUM> are formed, each of which extends vertically through interleaved sacrificial layers <NUM> and dielectric layers <NUM> in dielectric deck <NUM>. In some embodiments, fabrication processes to form channel structure <NUM> include forming a channel hole through interleaved sacrificial layers <NUM> and dielectric layers <NUM> in dielectric deck <NUM> using dry etching/and or wet etching, such as deep reactive-ion etching (DRIE), followed by filling the channel hole with a plurality of layers, such as a dielectric layer and a semiconductor layer, using thin film deposition processes. In some embodiments, the dielectric layer is a composite dielectric layer, such as a combination of multiple dielectric layers including, but not limited to, a tunneling layer, a storage layer, and a blocking layer. The tunneling layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The storage layer can include materials for storing charge for memory operation. The storage layer materials can include, but not limited to, silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride, or any combination thereof. The blocking layer can include dielectric materials including, but not limited to, silicon oxide or a combination of silicon oxide/silicon oxynitride/silicon oxide (ONO). The blocking layer can further include a high-k dielectric layer, such as an aluminum oxide (Al<NUM>O<NUM>) layer. The semiconductor layer can include polysilicon, serving as a semiconductor channel. The semiconductor layer and dielectric layer can be formed by processes such as ALD, CVD, PVD, or any combination thereof.

In some embodiments, dielectric stack <NUM> may be a joined by another dielectric stack to form a multi-stack structure through a joint layer <NUM>. As illustrated in <FIG>, joint layer <NUM> can be formed on dielectric deck <NUM> by depositing a dielectric layer, such as a silicon oxide layer, using thin film deposition processes, such as ALD, CVD, PVD, or any combination thereof. An array of inter-deck plugs <NUM> can be formed in joint layer <NUM> and in contact with the array of channel structures <NUM>, respectively. Inter-deck plugs <NUM> can be formed by patterning and etching openings through joint layer <NUM>, followed by deposition of semiconductor materials, such as polysilicon, using thin film deposition processes, such as ALD, CVD, PVD, or any combination thereof. In the following, embodiments of the present disclosure are described with respect to a single-stack structure for conciseness and simplicity. It is understood that technical solutions disclosed herein are applicable to multi-stack structure as well.

As illustrated in <FIG>, staircase structures <NUM> are formed on the sides of dielectric stack <NUM>. Staircase structure <NUM> can be formed by the so-called "trim-etch" processes, which, in each cycle, trim (e.g., etching incrementally and inwardly, often from all directions) a patterned photoresist layer, followed by etching the exposed portions of the dielectric/sacrificial layer pair using the trimmed photoresist layer as an etch mask to form one step of staircase structure <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a dummy channel structure extending vertically through the staircase structure is formed. In some embodiments, dummy channel structures are formed as intermediate structures that are later replaced by TSCs. As illustrated in <FIG>, an array of dummy channel structures <NUM> are formed through a staircase structure <NUM> of a dielectric stack <NUM>. Dielectric stack <NUM> includes interleaved dielectric layers <NUM> and sacrificial layers <NUM>.

Dummy channel structure <NUM> can extend vertically through staircase structure <NUM> and have a vertical opening filled with the same materials as those in channel structure <NUM>. Different from channel structures <NUM>, a contact is not formed on dummy channel structure <NUM> to provide electrical connections with other components of a 3D memory device such as 3D memory device <NUM>, according to some embodiments. In some embodiments, dummy channel structure <NUM> is fully filled with dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Dummy channel structure <NUM> can be used for balancing load in certain processes during fabrication (e.g., etching and chemical mechanical polishing (CMP)) and for providing mechanical support to memory array structures, e.g., staircase structure <NUM>. Embodiments of the present disclosure can form TSCs from dummy channel structures, thereby using the same pattern to form both the dummy channel structures and TSCs. The resulting TSCs can provide the balancing and supporting functions of the dummy channel structures.

As shown in <FIG>, dummy channel structure <NUM> can be formed by first etching a dummy hole <NUM> through one or more dielectric layers in staircase structure <NUM> using wet etching and/or dry etching, such as DRIE. In some embodiments, dummy hole <NUM> may extend vertically through all of the dielectric layers in staircase structure <NUM> and expose part of silicon substrate <NUM> (e.g., dummy hole <NUM> may extend to silicon substrate <NUM>). In some embodiments, dummy hole <NUM> may extend into silicon substrate <NUM> (e.g., part of silicon substrate <NUM> may be etched away during the etching process).

According to the invention, a dummy hole <NUM> outside dielectric stack <NUM> is formed simultaneously (e.g., in the same fabrication steps) with forming dummy hole <NUM>. Dummy hole <NUM> is used to form a peripheral contact providing interconnect to a peripheral device <NUM>. In some embodiments, dummy holes <NUM> and <NUM> may have a nominally circular shape in plan view, as shown in <FIG>. In some embodiments, the size of dummy holes <NUM> and <NUM> may be nominally the same.

Referring back to <FIG>, dummy holes <NUM> shown in <FIG> may be filled (deposited) with a dielectric layer <NUM>, such as a silicon oxide layer, to form dummy channel structures <NUM> using one or more thin film deposition processes, such as ALD, CVD, PVD, or any combination thereof. In some embodiments, dummy channel structures <NUM> are formed simultaneously with channel structures <NUM> in the same fabrication steps, such that dummy holes <NUM> is filled with at least some of the materials filling in channel structures <NUM>.

According to the invention, a dummy channel structure <NUM> outside dielectric stack <NUM> is formed simultaneously (e.g., in the same fabrication steps) with forming dummy channel structure <NUM> by depositing a dielectric layer <NUM> in dummy hole <NUM>. Dielectric layer <NUM> may have the same material as dielectric layer <NUM>.

In some embodiments, dummy holes <NUM>/<NUM> may be fully filled with dielectric layer <NUM>/<NUM>, respectively. In other embodiments, dummy holes <NUM> or <NUM> may be partially filled, as shown in <FIG>. In such cases, the resulting dummy channel structure <NUM>/<NUM> may have the top, bottom, and sidewall portions deposited with dielectric layer <NUM>/<NUM>. The center region may not be fully filled.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a plurality of word lines are formed by replacing the sacrificial layers in the dielectric stack with conductor layers. As shown in <FIG>, sacrificial layers <NUM> are replaced by conductor layers (functioned as word lines) <NUM>. The replacement of sacrificial layers <NUM> with conductor layers <NUM> can be performed by wet etching sacrificial layers <NUM> (e.g., silicon nitride) selective to dielectric layers <NUM> (e.g., silicon oxide) and filling the structure with conductor layers <NUM> (e.g., W). Conductor layers <NUM> can be deposited by PVD, CVD, ALD, electrochemical depositions, or any combination thereof. Conductor layers <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof. As a result, after the gate replacement processes, dielectric stack <NUM> in <FIG> becomes a memory stack <NUM> including the conductor/dielectric layer pairs, i.e., interleaved conductor layers <NUM> and dielectric layers <NUM>, on silicon substrate <NUM>.

Method <NUM> proceeds to operation <NUM>, in which an opening extending vertically through a center portion of the dummy channel structure is etched to form a spacer. Referring to <FIG>, an opening <NUM> (TSC hole) is etched through dummy channel structure <NUM> (shown in <FIG>) to form a spacer <NUM>. According to the invention, opening <NUM>/spacer <NUM> extends vertically through the interleaved dielectric layers <NUM> and conductor layer <NUM> in staircase structure <NUM> to reach silicon substrate <NUM>.

According to the invention, a second opening <NUM> (peripheral contact hole) is simultaneously formed from dummy channel structure <NUM> (shown in <FIG>). Opening <NUM>/<NUM> may be etched using wet etching and/or drying etching process, such as DRIE. For example, a center portion of dummy channel structure <NUM>/<NUM> may be removed by etching to form spacer <NUM>/<NUM> with a hollow core, as shown in <FIG>. In some embodiments, the sidewalls of spacers <NUM> and <NUM> may have a nominally same thickness. The depths of TSC hole <NUM> and peripheral contact hole <NUM> in the vertical direction can be nominally the same. The lateral dimensions of TSC hole <NUM> and peripheral contact hole <NUM>, such as the diameters, can be nominally the same or different in various embodiments. For example, the diameter of TSC hole <NUM> can be greater than the diameter of peripheral contact hole <NUM>, according to some embodiments.

As shown in <FIG>, TSC hole <NUM> and peripheral contact hole <NUM> can reach to silicon substrate <NUM>, and the lower end of peripheral contact hole <NUM> can be in contact with peripheral device <NUM> formed on silicon substrate <NUM>. In some embodiments, peripheral device <NUM> includes transistors, which can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in silicon substrate <NUM> by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of the transistors. In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate <NUM> by wet etching and/or dry etching and thin film deposition processes. The fabrication process for forming peripheral device <NUM> can occur at any fabrication stage prior to the etching of peripheral contact hole <NUM>.

Because opening <NUM>/<NUM> is etched from dummy channel structure <NUM>/<NUM> by removing part of the dielectric layer deposited thereon, the remaining portion, including the sidewall of the dummy channel structure <NUM>/<NUM> after opening <NUM>/<NUM> is formed, becomes spacer <NUM>/<NUM>. Spacer <NUM>/<NUM> can provide mechanical support to memory stack <NUM>, including staircase structure <NUM>, similar to dummy channel structure <NUM>/<NUM>. In addition, spacer <NUM>/<NUM> can function as an insulation layer surround the conductor layer deposited into opening <NUM>/<NUM> to form a TSC/peripheral contact.

In some embodiments, opening <NUM>/<NUM> (defined by the inner wall of spacer <NUM>/<NUM>) may have a nominally circular shape in plan view, as shown in <FIG>. In some embodiments, the sidewalls of spacer <NUM> and <NUM> may have a nominally same thickness. In some embodiments, spacer <NUM> and <NUM> may have the same or different size. For example, the diameter of spacer <NUM> (e.g., measured from the inner or outer sidewall) may be smaller than the diameter of spacer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which word line contacts and TSCs are simultaneously formed. In some embodiments, a conductor layer is deposited in an opening to form a TSC. In some embodiments, the conductor layer is a composite layer including an adhesion/barrier layer and a conductor. As illustrated in <FIG>, a conductor layer <NUM> is deposited in opening <NUM> (as shown in <FIG>) to fill the remaining space of opening <NUM>, thereby forming a TSC <NUM> extending vertically through staircase structure <NUM>. In some embodiments, a conductor can be formed in the remaining space of opening <NUM> by depositing metals, such as tungsten, using one or more thin film deposition processes, such as ALD, CVD, PVD, electrochemical depositions, or any combination thereof. A conductor layer <NUM> can be simultaneously formed in opening <NUM> (as shown in <FIG>) to form a peripheral contact <NUM> in contact with peripheral device <NUM>, using the same deposition processes. In some embodiments, conductor layers <NUM> and <NUM> may use the same material (e.g., tungsten (W)). The excess conductor layer after deposition can be removed by CMP.

Word line contacts <NUM> can be formed simultaneously (e.g., in the same fabrication steps) with TSCs. Each word line contact <NUM> is in contact with a respective one of conductor layers <NUM> of the conductor/dielectric layer pairs in staircase structure <NUM>. Word line contacts <NUM> are formed through one or more dielectric layers by first etching vertical openings (e.g., by wet etching and/or dry etching), followed by filling the openings with conductive materials using ALD, CVD, PVD, electrochemical depositions, or any combination thereof. In some embodiments, other conductive materials are filled in the openings to function as an adhesion/barrier layer. Etching of dielectric layers to form the openings of word line contacts <NUM> can be controlled by etch stop at a different material. For example, etching of dielectric layers can be stopped when reaching to conductor layers <NUM> in staircase structure <NUM>.

In some embodiments, TSC <NUM>, word line contact <NUM>, and peripheral contact <NUM> may have a nominally circular shape in a plan view, as shown in <FIG>. TSC <NUM>, word line contact <NUM>, and peripheral contact <NUM> may have the same or different sizes. For example, TSC <NUM> and peripheral contact <NUM> may have a larger diameter than that of word line contact <NUM>, according to some embodiments.

<FIG> is a flowchart of another exemplary method <NUM>' for forming a 3D memory device, according to some embodiments of the present disclosure. Operations <NUM>', <NUM>', <NUM>', and <NUM>' are similar to operations <NUM>, <NUM>, <NUM>, and <NUM>, respectively, and thus are not repeated. Method <NUM>' proceeds to operation <NUM>, as illustrated in <FIG>, in which an opening is etched extending vertically through a center portion of the dummy channel structure to form a spacer. Operation <NUM> is similar to operation <NUM>, with a difference that etching of the opening in operation <NUM> is performed before forming word lines. As illustrated in <FIG>, opening <NUM>/<NUM> are etched before sacrificial layer <NUM> are replaced by conductor layer <NUM>.

Method <NUM>' proceeds to operation <NUM>, as illustrated in <FIG>, in which a TSC is formed extending vertically through the staircase structure by depositing a conductor layer in the opening. Operation <NUM> is similar to <NUM> in terms of forming the TSC. Unlike operation <NUM>, in which word line contacts are formed simultaneously with TSCs, in operation <NUM>, word line contacts are not formed because word lines are not yet formed prior to operation <NUM>. Referring to <FIG>, TSCs <NUM> is formed before sacrificial layers <NUM> are replaced by conductor layer <NUM>.

Method <NUM>' proceeds to operation <NUM>, as illustrated in <FIG>, in which word lines are formed by replacing the sacrificial layers in the dielectric stack with conductor layers. Operation <NUM> is similar to operation <NUM>. Referring to <FIG>, word lines <NUM> are formed by replacing sacrificial layer <NUM> with conductor layer <NUM>. Note that in <FIG>, TSC <NUM> and peripheral contact <NUM> have been formed.

Method <NUM>' proceeds to operation <NUM>, as illustrated in <FIG>, in which word line contacts are formed. Operation <NUM> is similar to operation <NUM> in terms of forming word lines. As illustrated in <FIG>, word line contacts <NUM> are formed after TSC <NUM> and peripheral contact <NUM> are formed.

<FIG> is a flowchart of a further exemplary method <NUM>" for forming a 3D memory device, according to some embodiments of the present disclosure. Operations <NUM>", <NUM>", and <NUM>" are similar to operations <NUM>, <NUM>, and <NUM>, respectively, and thus are not repeated. Method <NUM>" proceeds to operation <NUM>, as illustrated in <FIG>, in which a dummy hole is formed extending vertically through the staircase structure. As shown in <FIG>, dummy hole <NUM> may be formed through one or more dielectric layers in staircase structure <NUM> using wet etching and/or dry etching, such as DRIE. In some embodiments, dummy hole <NUM> may extend vertically through all of the dielectric layers in staircase structure <NUM> and reach silicon substrate <NUM>. According to the invention, dummy hole <NUM> extends into silicon substrate <NUM> (e.g., part of silicon substrate <NUM> may be etched away during the etching process).

Method <NUM>" proceeds to operation <NUM>, as illustrated in <FIG>, in which a spacer having a hollow core is formed in the dummy hole. As shown in <FIG>, spacer <NUM> may be formed by depositing a dielectric layer <NUM> into dummy hole <NUM>, followed by removing part of the dielectric layer <NUM> to form spacer <NUM>, as described above in connection with steps <NUM> and <NUM>. In some embodiments, spacer <NUM> may be formed directly by depositing dielectric layer <NUM> into dummy hole <NUM>, without an additional etching operation to remove part of the deposited dielectric material to form spacer <NUM>. Spacer <NUM> may be formed in a similar manner.

Method <NUM>" proceeds to operation <NUM>, as illustrated in <FIG>, in which a TSC is formed extending vertically through the staircase structure by depositing a conductor layer in the hollow core of the spacer. Operation <NUM> is similar to operation <NUM>.

Method <NUM>" proceeds to operation <NUM>, as illustrated in <FIG>, in which word lines are formed by replacing the sacrificial layers in the dielectric stack with conductor layers. Operation <NUM> is similar to operation <NUM>. Referring to <FIG>, word lines <NUM> are formed by replacing sacrificial layer <NUM> with conductor layer <NUM>. Note that in <FIG>, TSC <NUM> and peripheral contact <NUM> have been formed.

Method <NUM>" proceeds to operation <NUM>, as illustrated in <FIG>, in which word line contacts are formed. Operation <NUM> is similar to operation <NUM>. As illustrated in <FIG>, word line contacts <NUM> are formed after TSC <NUM> and peripheral contact <NUM> are formed.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure.

It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Claim 1:
A method (<NUM>) for forming a three-dimensional (3D) memory device (<NUM>), comprising:
forming a dielectric stack (<NUM>) on a substrate (<NUM>), the dielectric stack (<NUM>) comprising a plurality of interleaved dielectric layers (<NUM>) and sacrificial layers (<NUM>);
forming a staircase structure (<NUM>, <NUM>) on at least one side of the dielectric stack (<NUM>); the method further comprises:
- forming a first dummy hole (<NUM>) extending vertically through the staircase structure (<NUM>, <NUM>) and reaching the substrate (<NUM>) as well as forming a first spacer (<NUM>) in the first dummy hole (<NUM>), the first spacer (<NUM>) having a hollow core,
or
- forming a dummy channel structure (<NUM>, <NUM>) reaching the substrate (<NUM>), the dummy channel structure (<NUM>, <NUM>) extending vertically through the staircase structure (<NUM>, <NUM>), comprises forming a first spacer (<NUM>) by removing part of the dummy channel structure (<NUM>, <NUM>), the first spacer (<NUM>) having a hollow core;
wherein the method (<NUM>) for forming a three-dimensional (3D) memory device (<NUM>) is characterized by further comprising:
forming a through stair contact, TSC, (<NUM>) in contact with the substrate (<NUM>) by depositing a first conductor layer (<NUM>) in the hollow core of the first spacer (<NUM>), the TSC (<NUM>) extending vertically through the staircase structure (<NUM>, <NUM>); and
forming a second dummy hole (<NUM>) outside the dielectric stack (<NUM>) simultaneously with forming the first dummy hole (<NUM>) or the dummy channel structure (<NUM>, <NUM>) and
forming a second spacer (<NUM>) in the second dummy hole (<NUM>) outside the dielectric stack (<NUM>) simultaneously with forming the first spacer (<NUM>), the second spacer (<NUM>) having a hollow core, and
forming a peripheral contact (<NUM>) by depositing a second conductor layer (<NUM>) in the second spacer (<NUM>) simultaneously with forming the TSC (<NUM>), wherein the peripheral contact (<NUM>) is in contact with the substrate (<NUM>), and
forming channel structures (<NUM>) extending through the dielectric stack (<NUM>) and in contact with the substrate (<NUM>).