Patent Description:
<CIT> describes ESD protection for field effect transistors of analog input circuits.

According to a first aspect of the present disclosure there is provided an integrated circuit, IC, comprising one or more DC blocking modules connected to a respective input/output, IO, pin of the IC, each DC blocking module comprising:.

a test mode in which the conduction path is in a conducting state and short circuits the capacitor.

The dual mode ESD protection circuit advantageously provides ESD protection for the capacitor in the operational mode, while enabling DC test measurements in the test mode.

In one or more embodiments the ESD protection circuit of each DC blocking module may comprise a transistor. A conduction channel of the transistor may form the conduction path of the ESD protection circuit. A control terminal of the transistor may form the control terminal of the ESD protection circuit. The transistor may be a field effect transistor.

In one or more embodiments the ESD protection circuit of one or more DC blocking modules may comprise a plurality of transistors. Conduction channels of the transistors may be connected in series to form the conduction path of the ESD protection circuit. Control terminals of the transistors may be connected together to form the control terminal of the ESD protection circuit. The plurality of transistors may comprise a plurality of field effect transistors.

In one or more embodiments the control terminal of the ESD protection circuit of each DC blocking module may be configured to receive the control signal to switch the ESD protection circuit from the operational mode to the test mode.

In one or more embodiments the ESD protection circuit of each DC blocking module may be configured to operate in the operational mode in the absence of a control signal.

In one or more embodiments the IC may be a radio frequency IC, RFIC.

In one or more embodiments the IC may further comprise a control circuit. The control circuit may be configured to provide the control signal to the control terminal of the ESD protection circuit of each DC blocking module.

In one or more embodiments the control circuit may comprise one or more test pads. The one or more test pads may be accessible to an automated test machine prior to packaging of the IC.

In one or more embodiments the control circuit may be configured to provide the control signal to the control terminal of the ESD protection circuit of one or more DC blocking modules in response to receiving a test enable signal at one or more test pads.

According to a second aspect of the present disclosure, there is provided a IC package comprising:.

According to a third aspect of the present disclosure, there is provided a switch circuit for a radio frequency front end, RFFE, module, comprising any of the ICs disclosed herein or any of the IC packages disclosed herein, wherein the IC is an RFIC.

According to a fourth aspect of the present disclosure there is provided a RFFE module comprising any of the ICs disclosed herein, any of the IC packages disclosed herein or any of the switch modules disclosed herein, wherein the IC is an RFIC.

According to a fifth aspect of the present disclosure, there is provided a method of processing a semiconductor wafer comprising a plurality of any of the ICs disclosed herein, the method comprising:
for one or more DC blocking modules of each IC:.

In one or more embodiments, the method further comprises:.

In one or more embodiments, the steps of providing the control signal to the control terminal and performing the DC test are performed in response to applying a test enable signal to a test pad of the IC using an automated test machine. Packaging each compliant IC may comprise making the test pad inaccessible.

It should be understood, however, that other embodiments, beyond the particular embodiments described, are possible as well.

The figures and Detailed Description that follow also exemplify various example embodiments. Various example embodiments may be more completely understood in consideration of the following Detailed Description in connection with the accompanying Drawings.

Many integrated circuits (ICs) have a series connected capacitor in one or more of their input/output paths. The provision of this DC blocking capacitor is usually to satisfy a system requirement that the die will connect to other circuitry operating at a different DC voltage and / or connect to an antenna which is exposed and should not carry a DC voltage other than the ground potential.

Two particular issues can arise from having series connected capacitors at the input or outputs of an IC. Firstly, the capacitors are susceptible to electrostatic discharge (ESD). Most capacitors are (quite) weak under ESD and may be irreversibly damaged. Secondly, the provision of the capacitors at input / output (IO) pins (or IO pads) may prevent DC testing at those IO pins of the IC.

As described herein, an IO pin or pad may refer to a node in the IC that can be coupled to an external circuit or device. For example, the IO pin / pad may be a wire-bonding pad or a terminal connected to the wire-bonding pad. An IO pad may be a physical connection point (for example, a metal plate at the top metal layer) which can connect the IC to an external circuit or a device (a leadframe, a package, a PCB etc.), for example via a bondwire, a copper pillar, a conductive bump or other suitable connecting means. An IO pin may refer to a node of an IC which can be connected to an external circuit or device. In some examples, an IO pin or pad may receive a RF signal from the IC and pass it to another device. In other examples, the IO pin or pad may receive a RF signal from an external source and provide it to the IC. For example, in a near-field communication IC, an IO pad of an IC may receive an RF signal from an external source and provide the RF signal to a voltage supply of the IC for powering the IC.

In industrial wafer testing, there can be thousands of ICs on a single wafer. Each IC can require testing to determine whether it meets a performance specification. Following testing the wafer may be diced into individual ICs. ICs that pass the test process may proceed to packaging; ICs that fail may be discarded.

DC tests can be performed in a short timescale. As a result, an automated test machine can scan a probe across the wafer measuring all IC dies and marking those that work or not. DC testing provides a simple and efficient test procedure.

Radio frequency ICs (RFICs) (or high frequency circuits more generally) may also require high frequency testing to determine RF performance parameters. RF testing has several disadvantages compared to DC testing. RF testing is more complex, expensive, time consuming and error prone. Furthermore, the RF measurement on a bare wafer may be a poor indicator of the final performance parameter for the packaged end product.

Some RF test parameters can be accurately determined or correlated to DC test parameters (as discussed below in relation to <FIG>). Therefore, where possible, it is preferrable to perform a DC test to measure a circuit parameter rather than a high frequency test. As a result, the number of required high frequency tests should be minimized. However, the provision of the blocking capacitor at an IO pin can prevent the use of the simpler DC tests.

The first issue identified above, the ESD susceptibility of the capacitors, may be overcome in a number of ways. <FIG> illustrate two different approaches to overcoming ESD susceptibility in series connected capacitors at IO pins of an IC.

In <FIG>, an IC <NUM> includes a DC blocking capacitor <NUM> connected in series between an IO pin (PAD) <NUM> and a node of the remaining circuitry (CIRCUIT) <NUM> of the IC <NUM>. An ESD protection device <NUM> is connected in parallel to the capacitor <NUM> to provide a required level of ESD robustness to the IC <NUM>. In this example, the ESD protection device <NUM> comprises antiparallel diodes (D1, D2, D3, D4) which will protect the DC blocking capacitor <NUM> during an ESD event. Depending on the blocked DC level, a higher number of diodes may be required which results in a higher silicon area and additional parasitic capacitance to the substrate. In other examples, the ESD protection device <NUM> may comprise clamp devices other than diodes, such as field-effect-transistor (FET) pairs or FET-diode pairs.

<FIG> illustrates a rail-based protection circuit which can be useful in low power applications. Similar to <FIG>, an IC <NUM> includes a DC blocking capacitor <NUM> connected in series between an IO pin (PAD) <NUM> and the remaining circuitry (CIRCUIT) <NUM> of the IC <NUM>. Diodes (D5, D6) connect a node between the IO pin <NUM> and the capacitor <NUM> to high and low voltage rails which are coupled with a supply clamp. However, the rail-based protection circuit is not suitable for applications where high voltage swings are required at the IO pin <NUM> because the diodes will turn on.

Both ESD protection examples illustrated in <FIG> fail to address the second issue identified above, namely the inability to perform DC circuit testing at IO pins having a blocking capacitor. DC testing remains partially or fully blocked by the DC-blocking capacitor <NUM>. In the example of <FIG>, DC testing may be possible in some cases by taking into account a voltage drop of the diodes. However, RFIC circuit testing typically involves measuring a small resistance and the error introduced by the voltage drop of the diodes would render the measurement of such a resistance inaccurate. In the example of <FIG>, the DC blocking capacitor <NUM>, by definition, prevents current passing between the IO pin <NUM> and the remaining circuitry. As a result, DC testing of the IC <NUM> is simply not possible.

<FIG> illustrates a block diagram of an RF front-end (RFFE) module <NUM> for base stations. The RFFE module <NUM> comprises multiple sub-modules that may each be formed on different dies and connected to each other in the RFFE package <NUM>. The sub-modules can operate at different DC voltages and therefore a DC blocking capacitor may be required on one or more of the sub-modules. The sub-modules of an RFEE module <NUM> are examples of RFICs that require wafer testing.

In this example, the sub-modules comprise a single pole double throw (SPDT) switch module <NUM>, a low noise amplifier (LNA) <NUM> and a power amplifier (PA) <NUM>. The PA <NUM> may receive transmission signals, TXIN, from a main circuit (not shown), for transmission via an antenna (not shown). The PA <NUM> can amplify the transmission signals, TXIN, and provide amplified transmission signals to a transmission terminal, TX_SW, <NUM>-<NUM> of the SPDT switch module <NUM>. The transmission terminal <NUM>-<NUM> is an example of an IO pin of the SPDT switch module <NUM>. The SPDT switch module <NUM> can operate in a first mode to couple the amplified transmission signals to an antenna terminal, ANT, <NUM>-<NUM> coupled to the antenna. The antenna terminal, <NUM>-<NUM> is an example of an IO pin of the SPDT switch module <NUM>.

The SPDT switch module <NUM> can operate in a second mode to couple received signals received at the antenna terminal <NUM>-<NUM> to a receiver terminal, RX_SW, <NUM>-<NUM>. The receiver terminal <NUM>-<NUM> is an example of an IO pin of the SPDT switch module <NUM>. The LNA <NUM> can amplify the received signals and pass amplified received signals, RXOUT, to the main circuit.

Complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology may often be used for implementing the SPDT switch module <NUM> because of high voltage swings required at the antenna terminal <NUM>-<NUM> the transmission terminal <NUM>-<NUM> and the receiver terminal, RX_SW <NUM>-<NUM>.

<FIG> illustrates a schematic of an example series shunt SPDT switch circuit <NUM> built from MOSFETS. CMOS SOI technology can enable a large number of MOSFETs to be stacked depending on the power handling requirements of the module <NUM>. The switch circuit <NUM> comprises four branches of stacked MOSFETS: (i) a first shunt branch <NUM> of stacked FETs (Ma_1. Ma_K) is connected between the transmission terminal <NUM>-<NUM> and a reference terminal <NUM>; (ii) a first series branch <NUM> of stacked FETs (Mb_1. Mb_L) is connected between the transmission terminal <NUM>-<NUM> and the antenna terminal <NUM>-<NUM>; (iii) a second series branch <NUM> of stacked FETs (Mc_1. Ma_M) is connected between the antenna terminal <NUM>-<NUM> and the receiver terminal <NUM>-<NUM>; and (iv) a second shunt branch <NUM> of stacked FETs (Md_1. Ma_N) is connected between the receiver terminal <NUM>-<NUM> and the reference terminal <NUM>.

In this example, each of the stacked FETs may comprise a biasing arrangement such as that illustrated in the Figure inset. The biasing arrangement may include a first biasing resistor coupling a drain terminal of the FET to a source terminal of the FET. The first biasing resistor may provide a resistance of a few kohms between the drain and the source terminals. A gate biasing resistor may be connected to a gate terminal of the FET for biasing received control signals. A body biasing resistor may be coupled to a body terminal of the FET to provide a body bias to the FET.

In this example, the switch circuit <NUM> also comprises a control circuit <NUM>. The control circuit <NUM> is coupled to the gate biasing resistor of each FET and provides corresponding control signals. The control circuit <NUM> is also coupled to the body biasing resistor of each FET to control the overall bias of each FET.

Two important performance test parameters of the switch circuit <NUM> are its insertion loss and port isolation. There is a strong correlation between the ON resistance of a series branch <NUM>, <NUM> and the insertion loss of the corresponding signal path. Similarly, the isolation between two terminals or IO pins <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> is a strong function of the ON resistance of the corresponding shunt branch <NUM>, <NUM>. Therefore, a test pass/fail criteria can be defined based on the DC ON resistances, Rds,on, of the series/shunt branches <NUM>, <NUM>, <NUM>, <NUM> rather than actually measuring an insertion loss and isolation between the respective IO pins <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> which can require costly, time-consuming high-frequency measurements. The Rds,on measurements can be conducted by activating one of the four series/shunt branches <NUM>, <NUM>, <NUM>, <NUM> and injecting a small DC current to the relevant terminal and measuring the voltage drop over the branch under test.

As shown, the switch module <NUM> of <FIG> is compatible with Rds,on measurements with DC testing and is self-protecting from ESD provided that the FETs are large enough to pass the required ESD current levels. However, all RF IO pins <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> of this circuit are DC coupled, which poses a problem when the switch die is to be connected to the other dies on the RFFE module.

As explained above, for RFFE modules such as the one shown in <FIG>, the sub-modules connected to the switch module (the LNA and the PA) are typically implemented on different dies, possibly using different technologies. This allows cost reduction and performance improvement. As a result, a DC blocking capacitor is placed between the switch module <NUM> and each of the LNA and PA to allow for different DC operating points of each separate die. For example, the output of the switch module may be at 0V and the input of the LNA may be at <NUM> V. The DC blocking capacitor can be implemented on either the LNA/PA die or on the switch module die <NUM>. Implementing the DC blocking capacitor on the switch module <NUM> can be advantageous because:.

Due to abovementioned noise contributions, the noise figure (NF) of the RX chain can deteriorate by <NUM>-<NUM> dB if the DC blocking capacitor is placed on the LNA die instead of the switch module die (likewise, the linearity of a PA would degrade by a similar amount), the exact amount depending on the technologies used. Therefore, it is advantageous to implement the DC blocking capacitor on the switch module <NUM>.

However, if a DC blocking capacitor is placed in series at either the receiver terminal <NUM>-<NUM> or the transmission terminal <NUM>-<NUM> of the switch circuit <NUM>, it will no longer be possible to measure Rds,on for the corresponding branch <NUM>, <NUM>, <NUM>, <NUM> using a DC test set-up. In addition, the IO pins <NUM>-<NUM>, <NUM>-<NUM> will no longer be ESD compatible. ESD compatibility could be implemented by connecting an ESD protection device such as the anti-parallel diodes of <FIG>. However, with such an arrangement, the DC ON resistance, Rds,on, measurement will not be possible because Rds,on of each branch of the RF switch module <NUM> is relatively low, typically in the range of <NUM> to <NUM> ohms. Therefore, injection of a small test current (<10mA) will result in a voltage drop across the branch of only a few millivolts. If a diode voltage drop of ~<NUM>. 7V is included in the Rds,on measurement, the accuracy of the measurement will reduce drastically, particularly in view of the process and temperature dependency of the diode voltage drop. Furthermore, in most circuits, a stack of diodes is needed to block the DC current in normal circuit operation and the resulting inaccuracy is even higher (N x <NUM>. 7V, where N is the number of stacked diodes).

<FIG> illustrates an example RFIC <NUM> according to an embodiment of the present disclosure. In this example, the RFIC <NUM> is a SPDT switch module <NUM> similar to that of <FIG>. Features of <FIG> that are also present in <FIG> have been given corresponding reference numbers in the <NUM> series and will not necessarily be described again here.

The RFIC <NUM> comprises a (DC blocking) capacitor, CDC-block, <NUM> having a first terminal connected to an IO pin (receiver terminal) <NUM>-<NUM> and a second terminal connected to a node of the remaining circuitry of the RFIC <NUM>. The RFIC also comprises an ESD protection circuit <NUM> connected in parallel to the capacitor <NUM>. In this example, the ESD protection circuit <NUM> comprises a MOSFET, MESD. The capacitor <NUM> and the ESD protection circuit <NUM> together form a DC blocking module of the RFIC. The ESD protection circuit <NUM> comprises a conduction path connected between the first terminal of the capacitor <NUM> and the second terminal of the capacitor <NUM>. In this example, the conduction channel of the FET, MESD, that is the channel between a drain and a source of the FET, forms the conduction path of the ESD protection device <NUM>. The ESD protection circuit <NUM> also comprises a control terminal configured to receive a control signal. In this example, the gate terminal of the FET forms the control terminal of the ESD protection circuit. The control terminal may receive the control signal and in response switch the ESD protection circuit <NUM> between: (i) an operational mode in which the conduction path of the ESD protection circuit <NUM> is in a non-conducting state and provides ESD protection to the capacitor <NUM>; and (ii) a test mode in which the conduction path of the ESD protection circuit <NUM> is in a conducting state and provides a DC path that short-circuits the capacitor <NUM>.

The ESD protection circuit <NUM> of the DC blocking module of the RFIC <NUM> is advantageously controllable and can be put into a test mode to enable DC testing of the RFIC with the associated manufacturing advantages described above. Following fabrication of the RFIC, the ESD protection circuit <NUM> of the DC blocking module can reside in an operational mode providing ESD protection functionality. As defined herein, the test/operational modes of the ESD protection circuit may be referred to as the test/operational modes of the corresponding DC blocking module.

The dual mode ESD protection circuit or FET <NUM> provides ESD protection for the capacitor <NUM> in the operational mode, while enabling DC test measurements, such as Rds,on measurements, in the test mode. The operational mode may be considered as an OFF mode during which there is no impact on circuit operation and the FET <NUM> provides ESD protection functionality for the series capacitor <NUM> at the IO pin <NUM>-<NUM>. The test mode may be considered as an ON mode during which the FET <NUM> shorts the DC blocking capacitor <NUM> and provides a DC path for DC testing.

During the operational mode, the FET <NUM> functions like a capacitor in parallel with the DC blocking capacitor <NUM>. The DC blocking capacitor <NUM> may have a sufficiently high capacitance such that there will be a negligible voltage swing across the capacitor <NUM> due to the presence of an RF signal. As a result, the FET <NUM> will remain OFF (non-conducting) during normal operation. Therefore, the FET <NUM> will have negligible impact on the RF performance of the switch module <NUM>. The FET <NUM> may introduce a parasitic capacitance to the substrate, however this is negligible in a SOI platform. In some examples, the FET <NUM> may be sized to pass a specified or rated ESD current.

During the test mode, the FET <NUM> is switched ON and functions like a low-ohmic resistor. The FET <NUM> may be arranged to remain in a linear region of operation. For the switch module <NUM> of <FIG>, DC testing can be performed to measure Rds,on for all branches connected to the receiver IO pin <NUM>-<NUM>. In this way, a DC test process, such as the one described below with reference to <FIG>, can conclude whether the RFIC <NUM> is a pass or a fail. Advantageously, a RF high-frequency test process is not required to measure insertion loss and isolation at radio frequencies. The FET <NUM> may contribute a nominal resistance of less than <NUM> ohm to a Rds,on measurement of one of the series and shunt branches. Advantageously, this nominal resistance can easily be accounted for when defining the pass/fail criteria.

In this example, the FET of the ESD protection circuit <NUM> comprises a biasing arrangement as illustrated in the Figure inset. The biasing arrangement may include a gate biasing resistor connected to the gate terminal of the FET <NUM> for biasing the received control signal. A body biasing resistor may be coupled to a body terminal of the FET <NUM> to provide a bulk bias to the FET <NUM>. The FET of the ESD protection circuit <NUM> does not include any biasing resistor (or any other coupling) coupling the drain terminal to the source terminal of the FET <NUM>. Such an arrangement would provide a permanent DC path in both the test mode and operational modes of the ESD protection circuit and is therefore not envisaged.

The control terminal of the ESD protection circuit <NUM> may receive the control signal to switch the ESD protection circuit <NUM> from the operational mode to the test mode. In this way, the ESD protection circuit <NUM> may operate in the operational mode as a default mode or in the absence of a control signal. Typically, DC testing will only be performed during manufacture of the IC, such as at a wafer testing stage. Therefore, the test mode may only be utilised at a beginning of life of the IC after which the ESD protection circuit <NUM> will operate in the operational mode.

The RFIC <NUM> may comprise a control circuit <NUM>. The control circuit <NUM> may provide the functionality of the control circuit described above in relation to <FIG>. In addition, the control circuit <NUM> may provide the control signal to the control terminal of the ESD protection circuit <NUM>. The control circuit <NUM> may control the FET <NUM> by providing the control signal to increase or decrease a gate bias voltage of the gate terminal. The control circuit <NUM> may provide the control signal as a two-level bias signal with a first bias level corresponding to the operational mode and a second bias level corresponding to the test mode. In some examples, the FET <NUM> may be an NMOS transistor. The first bias level may correspond to a value less than or equal to zero volts or to a ground voltage and the second bias level may correspond to an asserted positive voltage. In this way, the NMOS transistor will remain switched off and in the operational mode while the control signal corresponds to zero volts or in the absence of a control signal.

The control circuit <NUM> may comprise one or more test pads. The test pads may be accessible by an automated test machine prior to packaging of the RFIC <NUM>. For example, the test pads may be accessible during wafer testing. The control circuit <NUM> may provide the control signal to the control terminal of the ESD protection circuit <NUM> in response to receiving a test enable signal at a test pad. For example, the control circuit <NUM> may provide the control signal to switch the ESD protection circuit <NUM> into the test mode for DC testing.

The automated test machine may then probe the IO pin <NUM>-<NUM> and another terminal of the remaining circuitry, such as the antenna pin <NUM>-<NUM> or the reference terminal <NUM>, to measure a test parameter of a signal path between two terminals. For example, the automated test machine may measure Rds,on of the second series branch <NUM> or the second shunt branch <NUM> by injecting a current through the branch and measuring a voltage drop between the receiver pin <NUM>-<NUM> and the antenna pin <NUM>-<NUM> or the reference terminal <NUM> respectively.

Although the switch module <NUM> of <FIG> is illustrated with only one DC blocking module coupled to the receiver pin <NUM>-<NUM>, the switch module <NUM> may also comprise a DC blocking module coupled to the antenna pin <NUM>-<NUM> and / or the transmission pin <NUM>-<NUM>. Such DC blocking modules would comprise a further capacitor in parallel with a further ESD protection circuit as described above. As the signal levels can be higher at the antenna pin <NUM>-<NUM> and the transmission pin <NUM>-<NUM>, the corresponding further DC blocking capacitor at each pin may be larger than the capacitor <NUM> coupled to the receiver pin <NUM>. This can ensure that the RF voltage swing across the corresponding further capacitor remains low and that any FETs in the further ESD protection circuits do not turn ON during normal operation.

In this example, the ESD protection circuit <NUM> comprises a single FET, MESD. In other examples, the ESD protection circuit <NUM> may comprise a plurality of FETs. The conduction channels of the FETS may be connected in series to form the conduction path of the ESD protection circuit <NUM>. The gate terminals of the plurality of FETS may be connected together to form the control terminal of the ESD protection circuit <NUM>. In this way, a plurality of FETs can be stacked together to allow a higher DC voltage to be blocked. An advantage of using the FETs in the ESD protection circuit <NUM> rather than the diodes of <FIG> is that a fewer number of FETs are required in a stack compared to the number of diodes required to block the same level of DC voltage. This is because the breakdown drain-source (BVDS) of the RF switch MOSFETs are generally <NUM> to <NUM> times larger than a diode ON voltage. As a result, the ESD protections circuit has a lower parasitic capacitance / loss and occupies a smaller silicon area compared to the diode approach. In yet further examples, the ESD protection circuit <NUM> may comprise a bipolar junction transistor or a plurality of bipolar junction transistors.

Although the example RFIC of <FIG> is a SPDT switch module <NUM> implemented on a SOI CMOS technology, the DC blocking module, comprising the DC blocking capacitor <NUM> with ESD protection circuit <NUM> in parallel, is neither application constrained, nor technology constrained. The DC blocking module can be coupled to an IO pin of any IC that requires a DC blocking capacitor and DC testing capability. For example, the DC blocking module may be incorporated on a high voltage (non-RF) IC. The DC blocking module can be used in technologies other than SOI with FET devices suitable for ESD events, though the performance benefit of having the DC-blocking capacitor on the switch die may be reduced.

<FIG> illustrates a method of processing a semiconductor wafer comprising a plurality of any of the ICs disclosed herein according to an embodiment of the present disclosure.

The process <NUM> is performed on an IC having one or more DC blocking modules connected to a respective IO pin and comprising a controllable ESD protection circuit as described above, for example the RFIC of <FIG>.

The illustrated process <NUM> is performed for one or more DC blocking modules of each IC on the wafer. The process may be performed for a first DC blocking module of a first IC to perform a first DC test on circuitry of the first IC coupled to the first DC blocking module. The process may then be performed for a second DC blocking module of the first IC to perform a second DC test on circuitry of the first IC coupled to the second DC blocking module, and so on. Each DC test may then be performed on a second IC, and so on until each IC on the wafer has been fully tested. In some examples, the process <NUM> may be performed simultaneously for a plurality of DC modules and / or a plurality of ICs on the wafer using multi-site testing.

Firstly, considering the process <NUM> for a first DC blocking module of a first IC, a first optional step <NUM> comprises enabling a test mode for the IC. Enabling the test mode may be achieved in a number of ways such as applying a test enable signal to a test pad of the IC using an automated test machine. In other examples, enabling the test mode of the IC may be achieved by running a dedicated test interface or using test-features from a functional interface. A second step <NUM> of providing a control signal to the control terminal of the ESD protection circuit of the first DC blocking module to operate the ESD protection circuit in the test mode, may be performed in response to the first step <NUM>.

In some examples, each DC blocking module will have a corresponding test pad and providing the test enable signal to the test pad will provide <NUM> the control signal to the ESD protection device of the corresponding DC blocking module to enable the test mode. In other examples, the test pad may be connected to a control circuit of the IC. The control circuit can receive the test enable signal and process information in the test enable signal to determine one or more DC blocking modules to put into the test mode. The control circuit can then provide <NUM> the control signal to the ESD protection device of the one or more DC blocking modules to enable the test mode.

A third step <NUM> comprises performing a DC test on a signal path between the IO terminal corresponding to the first DC blocking module and a further terminal of the remaining circuitry of the IC. In some examples, the further terminal may comprise a reference terminal such as ground or a voltage rail. In other examples, the further terminal may comprise a further IO pin with a further DC blocking module. In such examples, the process may further comprise providing a control signal to the control terminal of the ESD protection circuit of the further blocking module to operate the further blocking module in the test mode. In this way, the signal path under test will comprise a DC conduction path suitable for DC testing.

The DC test may comprise any suitable test such as an Rds,on measurement for a series or shunt branch in a SPDT switch module as described above in relation to <FIG> and <FIG>. If the first DC blocking module corresponds to the receiver pin or the transmission pin, the further terminal may comprise a reference terminal for DC testing a shunt branch or the further terminal may comprise the antenna IO pin for DC testing a series branch. The antenna IO pin may have a further DC blocking module and the process <NUM> may therefore comprise providing a control signal to enable the test mode of the further DC blocking module.

Performing the DC test may comprise the automated test machine probing the IO pin and the further terminal of the remaining circuitry, such as the antenna pin <NUM>-<NUM> or the reference terminal <NUM>, to measure a test parameter of a signal path between two terminals. For example, the automated test machine may measure Rds,on of the second series branch or the second shunt branch by injecting a current through the branch and measuring a voltage drop between the receiver pin and the antenna pin or the reference terminal respectively.

A fourth step <NUM> may comprise removing the control signal from the control terminal of the ESD protection circuit of the first DC blocking module to operate the ESD protection circuit in an operational mode.

The process <NUM> may be repeated for one or more other DC blocking modules of the first IC to perform further DC tests on the first IC. The process may then be repeated for the same DC blocking modules of each IC on the wafer. In some examples, the process <NUM> may be performed simultaneously for a plurality of DC blocking modules of an IC and / or a plurality of ICs on a wafer.

The process may further comprise identifying compliant ICs that pass a test requirement of each DC test performed on the IC. The process may further comprise dicing the semiconductor wafer into individual ICs, packaging each compliant IC and discarding non-compliant ICs that failed one or more DC tests. Packaging the compliant ICs may include blocking access to the one or more test pads of the IC. For example, the test pads may not be wire bonded to any package pins. In this way, all ESD protection circuits of the IC will remain in the operational mode following packaging and provide ESD protection to their respective DC blocking capacitors.

The disclosed ICs include a ESD protection circuit, such as a MOSFET switch, placed in parallel to a DC blocking capacitor at an IO pin. The ESD protection circuit has a dual purpose: during normal operation and ESD testing, the MOSFET is off, and works as an ESD protection. During testing, the MOSFET is on, and provides a DC path via which DC tests can be carried out in an industrial environment.

Claim 1:
An integrated circuit, IC, comprising one or more DC blocking modules connected to a respective input/output, IO, pin (<NUM>-<NUM>) of the IC, each DC blocking module comprising:
a capacitor (<NUM>) having a first terminal connected to the respective IO pin (<NUM>-<NUM>) and a second terminal connected to a node (<NUM>-<NUM>) of the circuitry of the IC; characterised in that each DC blocking module further comprising
an electrostatic discharge, ESD, protection circuit (<NUM>) connected in parallel to the capacitor (<NUM>) , the ESD protection circuit comprising:
a conduction path connected between the first terminal of the capacitor (<NUM>) and the second terminal of the capacitor (<NUM>) ; and
a control terminal configured to receive a control signal to switch the ESD protection circuit between:
an operational mode in which the conduction path is in a non-conducting state and provides ESD protection to the capacitor; and
a test mode in which the conduction path is in a conducting state and short circuits the capacitor.