Patent Description:
Microelectromechanical systems enable integration of both microelectronic circuits and mechanical structures on a single chip or device, thereby significantly lowering fabrication costs and/or chip size. For instance, compared with their bulk piezoelectric counterparts, MEMS ultrasound transducers (MUT) can have applications not possible in conventional bulk piezoelectric devices, e.g., medical imaging, such as intravascular guiding and diagnosis, fingerprint detection, etc. For example, traditional manufacturing methods are ineffective in creating area array interconnection and reduced transducer sizes.

However, MUT devices, as an alternative method for fingerprint detection typically require MUT devices to be manufactured in the resolution of at least <NUM> dots per inch (dpi) or higher e.g., approximately <NUM> micrometer (µm) pixel size. Conventional manufacturing process flows, e.g., with traditional polishing and sawing from bulk piezoelectric materials have not been able to achieve required resolutions, whereas a capacitive MUT (CMUT) linear array can provide such resolution. However, CMUT linear arrays are subject to skin condition and sensor contamination, which can deteriorate the accuracy of fingerprint detection devices employing CMUT linear arrays.

It is thus desired to provide integrated piezoelectric MEMS transducers (PMUTs) on integrated circuit (IC) for fingerprint sensing that improve upon these and other deficiencies. The above-described deficiencies are merely intended to provide an overview of some of the problems of conventional implementations, and are not intended to be exhaustive. Other problems with conventional implementations and techniques, and corresponding benefits of the various aspects described herein, may become further apparent upon review of the following description.

<CIT> discloses a fingerprint sensor built on a CMOS structure that is provided with an insulating layer through which contacts to fingerprint sensor electrodes are formed.

<CIT> discloses MEMS devices, including CMOS wafers bonded to MEMS wafers, with electrical connections therebetween, aluminum-germanium eutectic bonds, and piezoelectric materials employed therein.

It is the object of the present invention to provide an improved MEMS device.

The object is solved by the subject matter of the independent claim which defines the present invention.

The following presents a simplified summary of the specification to provide a basic understanding of some aspects of the specification. This summary is not an extensive overview of the specification. It is intended to neither identify key or critical elements of the specification nor delineate any scope particular to any embodiments of the specification, or any scope of the claims. Its sole purpose is to present some concepts of the specification in a simplified form as a prelude to the more detailed description that is presented later.

An exemplary MEMS device can comprise a MEMS ultrasound transducer (MUT) structure and a piezoelectric material disposed within the MEMS device comprising a piezoelectric MUT (PMUT) array of a fingerprint sensor adapted to sense a characteristic of a fingerprint placed adjacent to the MUT structure. An exemplary MEMS device can further comprise a first metal conductive layer disposed on the piezoelectric material and a plurality of metal electrodes configured to form electrical connections between the first metal conductive layer, the piezoelectric material, and a complementary metal oxide semiconductor (CMOS) structure, wherein the pMUT structure and the CMOS structure are vertically stacked.

An exemplary MEMS device can comprise a CMOS device wafer associated with an integrated PMUT array of a fingerprint sensor and having a plurality of cavities configured in an array. An exemplary MEMS device can further comprise a first metal conductive layer disposed on the CMOS device wafer and over the plurality of cavities, a piezoelectric material disposed on the first metal conductive layer, and a second metal conductive layer, disposed on the piezoelectric material, electrically coupling the second metal conductive layer and at least one CMOS device wafer electrode, and electrically coupling the first metal conductive layer to at least one other CMOS device wafer electrode, wherein the plurality of cavities, the piezoelectric material, the first metal conductive layer, and the second metal conductive layer are configured as a plurality of PMUT structures.

Exemplary methods are described directed to PMUTs suitable for integration with CMOS integrated circuits (ICs), as well as PMUT arrays having high fill factor for fingerprint sensing.

The following description and the annexed drawings set forth certain illustrative aspects of the specification. These aspects are indicative, however, of but a few of the various ways in which the principles of the specification may be employed. Other advantages and novel features of the specification will become apparent from the following detailed description of the specification when considered in conjunction with the drawings.

<FIG> depict particular aspects of the appended set of claims, whereas figures which depict examples not falling under the scope of the appended set of claims are present for illustration purposes.

Various non-limiting aspects as well as further illustrative examples are further described with reference to the accompanying drawings, in which.

While a brief overview is provided, certain aspects of the subject disclosure are described or depicted herein for the purposes of illustration and not limitation.

One or more embodiments and examples are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It may be evident, however, that the various embodiments can be practiced without these specific details, e.g., variations in configurations, processes, and/or materials. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the embodiments in additional detail.

In the described embodiments microelectromechanical systems (MEMS) refers to a class of structures or devices fabricated using semiconductor-like processes and exhibiting mechanical characteristics such as the ability to move or deform. MEMS often, but not always interact with electrical signals. MEMS devices include but are not limited to gyroscopes, accelerometers, magnetometers, pressure sensors, and radio-frequency components. Silicon wafers containing MEMS structures are referred to as MEMS wafers.

In the described embodiments, MEMS device may refer to a semiconductor device implemented as a microelectromechanical system. MEMS structure may refer to any feature that may be part of a larger MEMS device. An engineered silicon-on-insulator (ESOI) wafer may refer to a SOI wafer with cavities beneath the silicon device layer or substrate. Handle wafer typically refers to a thicker substrate used as a carrier for the thinner silicon device substrate in a silicon-on-insulator wafer. Handle substrate and handle wafer can be interchanged.

In the described embodiments, a cavity may refer to an opening or recession in a substrate wafer and enclosure may refer to a fully enclosed space. Bond chamber may be an enclosure in a piece of bonding equipment where the wafer bonding process takes place. The atmosphere in the bond chamber determines the atmosphere sealed in the bonded wafers.

Additionally, a system and method in accordance with the present disclosure describes a class of RF MEMS devices, sensors, and actuators including but not limited to switches, resonators and tunable capacitors that are hermetically sealed and bonded to integrated circuits that may use capacitive sensing and electrostatic, magnetic, or piezoelectric actuation.

<FIG> illustrates a cross-section view of a MEMS structure <NUM> in accordance with a first example. <FIG> shows a MEMS structure with addition of metal on the silicon structural layer. The structure includes a CMOS wafer <NUM> bonded to a MEMS wafer <NUM>. The MEMS wafer <NUM> comprises a silicon device layer <NUM> fusion bonded to a handle wafer <NUM> through an oxide layer <NUM>. A MEMS aluminum <NUM> metal layer is added to the silicon device layer <NUM>. Adding a metal layer lowers the resistivity of the MEMS structure over that of just the silicon device layer <NUM> making it more attractive for applications requiring low parasitics (ex. RF MEMS, Lorentz force sensors, etc.). In this example, the connection between CMOS wafer <NUM> and MEMS wafer <NUM> is created through the silicon stand-offs <NUM> using an aluminum-germanium eutectic bond formed by germanium <NUM> and aluminum <NUM>. Apart from the stand-offs <NUM> the bulk of the current is carried by the metal layers <NUM>. In an example, spacers <NUM> composed of an insulating material such as Silicon Oxide or Silicon Nitride may be placed on bottom metal layer <NUM> to reduce stiction and control the gap between the top metal layer <NUM> and the bottom metal layer <NUM>.

<FIG> illustrates a cross-section view of a MEMS structure <NUM>' in accordance with a second example. <FIG> shows a MEMS structure with additional insulating layer 112a deposited onto the MEMS aluminum <NUM> and insulating layer 112b deposited onto the bottom electrode <NUM> to prevent shorting and create a well-defined capacitive gap when the movable MEMS structure consisting of the silicon device layer <NUM>, MEMS aluminum <NUM>, and insulating layer 112a are brought into contact with the electrodes on the CMOS wafer <NUM>.

<FIG> illustrates a cross-section view of a MEMS structure <NUM> in accordance with a third example. <FIG> shows a MEMS structure similar to <FIG>. However, in this example the electrical connection between the CMOS wafer <NUM>' and the MEMS wafer <NUM>' occurs through physical contact between the CMOS aluminum <NUM> on the CMOS wafer <NUM>' and the MEMS aluminum <NUM>' on the MEMS wafer <NUM>' connected by an Aluminum-Germanium layer created by the eutectic reaction between germanium <NUM> and CMOS aluminum <NUM>' on the CMOS wafer <NUM>' and the MEMS aluminum <NUM>' on the MEMS wafer <NUM>'. One possible risk of this example is a preferential reaction of the germanium <NUM> with the MEMS aluminum <NUM>' (since that is the layer it is directly deposited on) with a possibly insufficient reaction with the CMOS aluminum <NUM>'. The insufficient reaction may lead to poor bonds and marginal electrical connections.

<FIG> illustrates a cross-section view of a MEMS structure <NUM> in accordance with a fourth example. <FIG> shows a MEMS structure identical to <FIG> with the exception of a barrier layer <NUM> deposited between the MEMS aluminum <NUM>" and germanium <NUM>'. The barrier layer <NUM> is electrically conductive and makes an electrical contact with aluminum upon physical contact. The objective of the barrier layer <NUM> is to prevent a eutectic reaction between the MEMS aluminum <NUM>" and germanium <NUM>', leaving germanium <NUM>'to eutectically react with the CMOS aluminum <NUM>". One such barrier layer may be Titanium Nitride. During the eutectic reaction, the CMOS aluminum <NUM>" will mix with germanium <NUM>' creating an electrical contact and physical bond to the barrier layer <NUM> on the MEMS aluminum <NUM>", thereby creating an electrical contact between the CMOS wafer <NUM>" and MEMS wafer <NUM>".

<FIG> illustrates a cross-section view of a MEMS structure <NUM> in accordance with a fifth example. <FIG> shows a MEMS structure identical to <FIG>, but with an insulating layer <NUM> deposited between the MEMS aluminum <NUM>‴ and silicon device layer <NUM>‴ thereby electrically insulating the silicon from the metal. The insulating layer <NUM> is needed in cases where it is not desirable to carry any electrical signal in the silicon layer (for example in RF applications where signal transmission in the silicon would produce a power loss). In this example, at RF frequencies the MEMS aluminum <NUM>‴ is still capacitively coupled to the silicon device layer <NUM>‴ through the insulating layer <NUM>. To achieve sufficient isolation the insulating layer must be sufficiently thick to minimize capacitance or the silicon must be sufficiently resistive so as to minimize electrical signal coupling into it.

<FIG> is a flowchart of a process for adding metal and piezoelectric layers to a MEMS structure. The process starts with an Engineered SOI <NUM>. A first metal layer (metal <NUM>) is deposited onto the device silicon surface via step <NUM> followed by the piezoelectric layer deposition (e.g., Aluminum Nitride or PZT) pattern and etch via step <NUM>. Next a second metal layer (Metal <NUM>) deposited onto the wafer to serve as a top electrode for the piezoelectric layer as well as to provide electrical contact between Metal <NUM> and the CMOS substrate via step <NUM>. A germanium layer is deposited onto Metal <NUM> and patterned to define germanium pads in regions where bonding to CMOS will take place via step <NUM>. Next, the MEMS wafer is bonded to a CMOS wafer such that germanium pads eutectically react with aluminum pads on the CMOS creating electrical and physical contact between the CMOS aluminum and MEMS Metal <NUM> via step <NUM>.

<FIG> illustrates a cross-section view of a MEMS structure <NUM> in accordance with a sixth example that utilizes a piezoelectric layer. Adding a piezoelectric layer <NUM> enables a range of applications including acoustic resonators and filters and piezo-actuated devices. To operate, the piezoelectric layer <NUM> typically requires a bottom electrode <NUM> and top electrodes <NUM>. The bottom electrode <NUM> may comprise a first metal layer (metal <NUM>) (Ex. Aluminium, Ruhtenium, Tungsten, Molybdenum or Platinum). In another example, a silicon device layer can be used as a bottom electrode <NUM>. The top electrode <NUM> and interconnect <NUM> are composed of a second metal layer (metal <NUM>) (Ex. The top electrode <NUM> and interconnect <NUM> make physical and electrical contact to the CMOS aluminum pads <NUM> using an Aluminum Germanium bond. The bottom electrode <NUM> may make physical and electrical contact to the interconnect <NUM> thereby connecting to the CMOS wafer. Electrical potentials may be applied between top electrodes <NUM> and the bottom electrode <NUM> or between individual top electrodes <NUM>. These potentials create electric fields to induce strains within the piezoelectric material.

<FIG> illustrates a cross-section view of a MEMS structure <NUM> in accordance with a seventh example. <FIG> shows the same structure as in <FIG> with an addition of a silicon dioxide layer <NUM> between the device layer silicon <NUM> and metal layer, <NUM>". The silicon dioxide layer, <NUM> serves as a temperature stabilization layer that improves frequency stability of the resonator or filter over temperature by offsetting the positive Young's modulus temperature coefficient of silicon with the negative Young's modulus temperature coefficient of silicon oxide.

<FIG> illustrates a cross-section view of a MEMS structure <NUM> in accordance with a eighth example. <FIG> shows the same structure as in <FIG> with an addition of a patterned bottom electrode <NUM>". By patterning the bottom electrode <NUM>", multiple potentials may be applied to different sections of the bottom surface of the piezoelectric material <NUM>, leading to more design flexibility and potentially more efficient devices. For resonator applications, for example, the ability to input electrical signals on both the bottom and top of the piezoelectric structure can lead to higher coupling efficiency. In further examples, the subject application provides disclosure of a microelectromechanical system (MEMS) integration flow to incorporate aluminum nitride (AlN) on an engineering substrate and a top electrode layer combined with aluminum germanium (AlGe) with complementary metal-oxide-semiconductor (CMOS) wafers/layers/substrates.

In addition to the foregoing, the subject application further describes a MEMS integration flow that comprises starting wafers/layers/substrates (e.g., complementary metal-oxide-semiconductor (CMOS) wafers/layers/substrates, MEMS handle wafers/layers/substrates, and/or MEMS device wafers/layers/substrates) and a plurality of masking layers, for example, ten masking layers, though, as will be appreciated by those of ordinary skill, a fewer or a greater number of masking layers can be utilized without unduly departing from the generality and scope of the subject disclosure.

Typically, the MEMS handle wafers/layers/substrates can be patterned with back-side alignment mark layers used for front-to-back alignment after fusion bonding. Cavities that define suspended MEMS structures can also be etched in a front-side of the MEMS handle wafers/layers/substrates. The MEMS handle layers/wafers/substrates can then be oxidized and fusion-bonded to MEMS device layers/wafers/substrates.

The MEMS device layers/wafers/substrates can, for example, comprise silicon (Si) structural layers that can be ground and polished to target thicknesses, at which point aluminum nitride seed layers can be disposed over a surface of the silicon structural layers, molybdenum layers can be deposited over the aluminum nitride seed layers, aluminum nitride stacking layers can be deposited over the molybdenum layers, and/or silicon dioxide standoff layers can be disposed on the aluminum nitride stacking layers.

The silicon dioxide standoff layers can be etched on the MEMS device layers/wafers/substrates to provide separations between the MEMS structures and the complementary metal-oxide-semiconductor wafers/layers/substrates. The aluminum nitride (AlN) stacking layers can then be patterned through a silicon dioxide hard mask with structures, bottom contacts, and/or aluminum nitride top contact masks. Additionally, aluminum, titanium, and germanium can then be deposited in sequence from bottom to top and patterned with germanium pads and electrodes. The silicon device layer can then be patterned and etched using, for instance an anisotropic etch process used to create deep penetration, steep-sided holes and trenches in layers/wafers/substrates, typically with high aspect ratios, such as deep reactive-ion etching (DRIE), to define release structures. Generally, the combination of the structures and release layers that define the fully released structure are formed on the upper cavity.

A bottom cavity can be etched in the complementary metal-oxide-semiconductor layer/wafer to allow clearance for out-of-plane moving of the MEMS structures (e.g., combinations of silicon and aluminum nitride stacking layers) or damping control. The MEMS and complementary metal-oxide-semiconductor wafers/layers/substrates can then be bonded using aluminum-germanium (Al-Ge) eutectic bonding to create hermetic seals around the MEMS structures as well as electrical interconnects between the MEMS structures and complementary metal-oxide-semiconductor circuits. Thereafter, the bonded wafer/layer can be thinned on the MEMS side to a desired thickness and a port can be formed on the polished side of the MEMS wafer/layer to create access to the surrounding environment. Silicon tabs on the MEMS wafer/layer can thereafter be removed using, for example, a dicing process to expose the complementary metal-oxide-semiconductor wire-bond pads.

In accordance with the foregoing and with reference to <FIG>, a cross-section of a MEMS device <NUM> is illustrated. The MEMS <NUM> can comprise a handle wafer/layer/substrate <NUM> that can have been patterned with back-side alignment mark layers to be employed for front-to-back alignment after fusion bonding. Further, a front side of handle wafer/layer/substrate <NUM> can have been etched to form cavities <NUM>. As depicted handle wafer/layer/substrate <NUM> can be formed of a silicon layer/substrate into which cavities <NUM> can have been etched. To the handle wafer/layer/substrate <NUM> inclusive of cavities <NUM> a silicon dioxide layer/substrate <NUM> can be deposited on the silicon layer/substrate <NUM> thereby overlaying silicon layer/substrate <NUM> and cavities <NUM> formed therein. Disposed and/or deposited over silicon dioxide layer/substrate <NUM> and fusion bonded to the silicon dioxide layer/substrate <NUM> can be a substrate/layer formed of silicon <NUM>. In accordance with an embodiment, the handle wafer/layer/substrate <NUM> inclusive of formed cavities <NUM> and silicon dioxide layer <NUM> can be referred to as an engineered substrate, and for purposes of this disclosure can be referred to a the MEMS handle layer.

With reference to <FIG> that depicts a further cross-sectional view of MEMS device <NUM>, in addition to the above noted silicon layer/substrate <NUM> inclusive of etched cavities <NUM>, silicon dioxide layer/substrate <NUM> (silicon layer/substrate <NUM> inclusive of etched cavities <NUM> and silicon dioxide layer/substrate <NUM> can form and be referred to as the MEMS handle layer/wafer/substrate), and a substrate/layer <NUM> formed of silicon, silicon dioxide standoffs <NUM> can be formed on the MEMS handle layer/wafer/substrate by, for example, successively depositing aluminum nitride seed layers <NUM>, molybdenum layers <NUM>, and aluminum nitride stacking layers <NUM> over silicon substrate/layer <NUM>, prior to etching and/or forming silicon dioxide standoffs <NUM>. The additional deposited or disposed layers comprising the aluminum nitride seed layers <NUM>, molybdenum layers <NUM>, aluminum nitride stacking layers <NUM>, and silicon dioxide standoffs <NUM> over silicon substrate/layer <NUM> can be referred to the MEMS device layer/wafer/substrate and/or piezoelectric layer/wafer/substrate.

Silicon substrate layer <NUM> can be the silicon structural layer of the MEMS device layer to which the MEMS handle layer (e.g., silicon layer/substrate <NUM> inclusive of etched cavities <NUM> and silicon dioxide layer/substrate <NUM>) can have been fusion bonded to the MEMS device layer/wafer/substrate (e.g., silicon structural substrate/layer <NUM>, aluminum nitride seed layers <NUM>, molybdenum layers <NUM>, aluminum nitride stacking layers <NUM>, and standoffs <NUM>). It should be noted that the MEMS handle layer, prior to fusion bonding of the MEMS handle layer to the MEMS device layer, can typically have been oxidized and the silicon structural layer/substrate <NUM> of the MEMS device layer can have been ground and polished to a target or defined thickness prior to deposition of the aluminum nitride seed layers <NUM>, molybdenum layers <NUM>, aluminum nitride stacking layers <NUM>, and standoffs <NUM> formed of silicon dioxide. Standoffs <NUM> are typically formed on the MEMS device layer to provide separation between the MEMS structure and a CMOS wafer/layer/substrate.

<FIG> provide illustration of a further cross-sectional view of MEMS device <NUM> including the layers described above in connection with <FIG>. In <FIG>, structure can be defined and separate bottom electrodes <NUM> can be carved out by first disposing or depositing a silicon dioxide hard mask <NUM> over the aluminum nitride stacking layers <NUM> and standoffs <NUM> and thereafter etching through silicon dioxide hard mask <NUM> to define the structure and carve out separate bottom electrodes <NUM>. As will be observed, the etching process etches through layers/substrates respectively formed of silicon dioxide hard mask <NUM>, aluminum nitride <NUM>, molybdenum <NUM>, and aluminum nitride seed layer <NUM>, to the silicon structural layer/substrate <NUM>. In <FIG>, a bottom electrodes contact <NUM> can be created. In <FIG> a opening etch on silicon dioxide layer <NUM> can be performed to define aluminum nitride top contacts <NUM> and avoids unnecessary HBAR resonance from the pad. Defining the structure and carving out the bottom electrodes <NUM>, creating bottom electrode contacts <NUM>, and defining aluminum nitride top contacts <NUM>, as depicted in <FIG>, can be undertaken by patterning the aluminum nitride stacking layers through silicon dioxide hard mark <NUM>.

As illustrated in <FIG> aluminum and titanium layers <NUM> are deposited for the purposes of top electrode material deposition and then germanium layers <NUM> are deposited over the aluminum and titanium layers <NUM> so that germanium pads <NUM> and electrodes <NUM> can be patterned as depicted in <FIG>. The device layer can be overlaid with a layer of photo-resist <NUM> and patterned and etched using deep reactive-ion etching (DRIE) to define release structures, as depicted in <FIG>. Only the combination of the structure and release layer can define the fully released structure <NUM> (See <FIG>) in the cavity <NUM>.

As depicted in <FIG>, a cavity <NUM> is etched into a CMOS wafer <NUM> to allow clearance for out-of-plane moving MEMS structures <NUM> and/or damping control, and thereafter the CMOS wafer <NUM> and MEMS device wafer <NUM> are bonded using an Aluminum-Germanium eutectic bond to create a hermetic seal around MEMS structure <NUM> and CMOS circuits and form a bonded wafer <NUM>. The eutectically bonded wafer <NUM> can then be thinned, for instance, on the MEMS wafer side, to a defined or desired thickness and a port <NUM> can be formed on a polished side of the MEMS wafer <NUM> to create access to the surrounding environment, as illustrated in <FIG>. Additionally, silicon tabs on the MEMS wafer <NUM> can be removed using a dicing process to expose CMOS wire bond pads.

In accordance with the foregoing and in an additional example as illustrated in <FIG>, subsequent to defining structure and carving out separate bottom electrodes <NUM>, as illustrated in <FIG>, but prior to creating bottom electrode contacts <NUM>, as depicted in <FIG>, a partial silicon etch can be performed wherein structural silicon layer <NUM> (e.g., the structural silicon layer of the MEMS device wafer) can partially be further etched <NUM>. The partial etch <NUM> can be performed to partially thin down the silicon device layer (e.g., structural silicon layer <NUM>). The partial etch <NUM> can be accomplished with a structure layer mask through silicon etch or silicon deep reactive-ion etching. It should be noted that the partial etch <NUM> can be an additional etch to that previously performed to define structure and carve out separate bottom electrodes <NUM> as elucidated above in connection with <FIG>. Additionally and/or alternatively, partial etch <NUM> and the etch performed to define structure and carve out separate bottom electrodes <NUM>, as depicted in <FIG>, can be accomplished in a single act without unduly and/or unnecessarily departing from the intent and generality of the subject disclosure.

In a further additional aspect or example, as illustrated in <FIG>, an additional act of can be performed subsequent to etching port <NUM> on a polished side of the MEMS wafer <NUM> (see e.g., <FIG>). In accordance with this aspect, an infra-red (IR) absorption layer <NUM> can be deposited on the back of the MEMS handle wafer <NUM>. The infra-red (IR) absorption layer <NUM>, as illustrated, can be disposed not only on the back of the MEMS handle wafer <NUM> but also in the previously etched port <NUM>.

In accordance with a further disclosed aspect or example, as illustrated in <FIG> additional and/or alternative standoff <NUM> formations techniques can be employed. As illustrated in <FIG> a layer of silicon <NUM> can be deposited over the MEMS handle layer/wafer/substrate (e.g., silicon layer/wafer/substrate <NUM> inclusive of cavities <NUM> and silicon dioxide layer/substrate <NUM>) and thereafter the deposited layer of silicon <NUM> can be partially etched to form standoffs <NUM>, thus, referring back to <FIG> and as illustrated in <FIG>, standoffs <NUM> can have been formed from the structural silicon layer <NUM> of the MEMS device layer or piezoelectric layer/wafer/substrate. Alternatively, as depicted in <FIG> rather than partially etching into structural silicon layer <NUM>, structural silicon layer <NUM> can be overlaid with a silicon dioxide layer and thereafter the deposited silicon dioxide layer can be patterned to create or form standoffs <NUM>, as illustrated in <FIG>.

Thereafter, and still with reference to <FIG>, deposition of piezoelectric stacking layers <NUM>, as described and illustrated in connection with.

<FIG>, can be carried out as respectively depicted in <FIG>. In the context of <FIG> it will be observed that the subsequent piezoelectric stacking layers <NUM>, as described in relation to <FIG>, overlay silicon standoffs <NUM>, whereas, in connection with <FIG>, the successive layers that comprise the piezoelectric stacking layers <NUM>, as disclosed with respect to <FIG>, are deposited over silicon dioxide standoffs <NUM>.

<FIG> illustrates an additional and/or alternative process flow than that described and disclosed in connection with <FIG>. In this instance, and as depicted in <FIG>, and as has been described above in relation to <FIG>, silicon standoffs <NUM> can have been formed by patterning and/or partially etching structural silicon layer <NUM>. Thereafter, the piezoelectric layer stacking (e.g., aluminum nitride seed layers <NUM>, molybdenum layer <NUM>, and aluminum nitride stacking layer <NUM>) described earlier with respect to <FIG> can be reduced to only an aluminum nitride layer <NUM>, wherein an aluminum nitride layer <NUM> is overlaid and patterned <NUM> on top of the structural silicon layer <NUM> inclusive of the formed silicon standoffs <NUM>. As illustrated in <FIG>, the structural silicon layer <NUM> inclusive of the silicon standoffs <NUM> can be used as bottom electrodes. In <FIG> the aluminum nitride layer <NUM> can be overlaid with aluminum and titanium layers <NUM>. As will be noted in relation to <FIG>, patterning in aluminum nitride layer <NUM> at <NUM> will be filled by the aluminum and titanium layers <NUM>.

In <FIG> germanium pads <NUM> can be defined, wherein a germanium layer can be overlaid aluminum and titanium layers <NUM> to form the germanium pads <NUM>. Further, in <FIG> the previously deposited aluminum and titanium layers <NUM> can be selectively patterned to define aluminum and titanium pads <NUM> and to expose the underlying aluminum nitride layer <NUM>. In <FIG> a silicon dioxide hard mask <NUM> can be deposited over defined germanium pads <NUM>, aluminum and titanium pads <NUM>, and exposed aluminum nitride layer <NUM> and an etch or patterning performed to define the structure <NUM>.

Once structure <NUM> has been defined, a CMOS wafer <NUM> can be eutectically bonded to the MEMS device wafer <NUM>, in a manner similar to that described in the context of <FIG> and illustrated in <FIG>. Further, on completion of the eutectic bonding of the CMOS wafer <NUM> to the MEMS device wafer <NUM>, a port <NUM> can be formed on a polished side or surface of the MEMS device wafer <NUM>, as illustrated in <FIG>.

With reference now to <FIG>, and initially in reference to <FIG>, in order to provide protection to sidewalls <NUM> during the various etching and/or patterning phases that can be employed to construct the described micro-electrical-mechanical device, in accordance with an embodiment, and as illustrated in <FIG> a silicon dioxide layer <NUM> can be deposited to overlay the layers previously described in the context of <FIG>. It will be observed on examination of <FIG> that the silicon dioxide layer <NUM> has been disposed to cover the sidewalls <NUM> as well as bottom electrodes <NUM> and the bottom electrodes contact <NUM>. Additionally, as will also have been observed on inspection of <FIG>, the deposited silicon dioxide layer <NUM> will also have covered the aluminum nitride top contact <NUM>. The deposition and patterning of silicon dioxide layer <NUM> provides isolation Once the silicon dioxide layer <NUM> has been deposited as illustrated in <FIG>, the silicon dioxide layer <NUM> can undergo a blank reactive-ion etch to create sidewall protection <NUM>.

In accordance with the foregoing, the subject application discloses in one or more various examples a MEMS device, comprising: a first silicon substrate comprising: a handle layer comprising a first surface and a second surface, the second surface comprises a cavity; an insulating layer deposited over the second surface of the handle layer; a device layer having a third surface bonded to the insulating layer and a fourth surface; a piezoelectric layer deposited over the fourth surface of the device layer; a metal conductivity layer disposed over the piezoelectric layer; a bond layer disposed over a portion of the metal conductivity layer; and a stand-off formed on the first silicon substrate; wherein the first silicon substrate is bonded to a second silicon substrate, comprising: a metal electrode configured to form an electrical connection between the metal conductivity layer formed on the first silicon substrate and the second silicon substrate.

In accordance with the foregoing, the stand-off can be formed on the piezoelectric layer and can be formed as a silicon layer or as a silicon dioxide layer deposited on the device layer. Additionally and/or alternatively, the stand-off can be formed of silicon dioxide deposited on the piezoelectric layer.

Further, the piezoelectric layer can be patterned and etched to form a sidewall in the piezoelectric layer, wherein a first dielectric layer can be interposed between the piezoelectric layer and the metal conductive layer, and a second dielectric layer can be disposed on the sidewall of the piezoelectric layer. In addition, an opening in the handle layer can be exploited to expose the device layer, an orifice in the device layer can be used to expose the piezoelectric layer, and the device layer can include an aperture.

The device layer can be selectively or partially removed, the piezoelectric layer can in an example comprise aluminum nitride or in another example can comprise: an aluminum nitride (AlN) seed layer, a bottom metal layer, and an aluminum nitride (AlN) layer. Further, an infra-red (IR) absorption layer can be deposited on a portion of the device layer and/or the infra-red (IR) absorption layer can be deposited on a portion of the piezoelectric layer.

In accordance with a further example, a method is described and disclosed. The method can comprise a sequence of machine executable operations that can include depositing an insulation layer over a handle layer that comprises a first surface and a second surface, wherein the second surface comprises a cavity and the insulation layer is formed on the second surface of the handle layer; bonding a first surface of a device layer to the insulation layer; depositing a piezoelectric layer on a second surface of the device layer; depositing a metal conductivity layer over the piezoelectric layer; partially depositing a bond layer over the metal conductivity layer; forming a stand-off on the second surface of the device layer; and establishing an electrical connection between the metal conductivity layer and a silicon substrate.

Further machine executable method operations can include: depositing a silicon layer or a silicon dioxide layer to form the stand-off; depositing a silicon dioxide layer to form a stand-off positioned on the piezoelectric layer; patterning and etching of the piezoelectric layer to form a sidewall; interposing a first dielectric layer between the piezoelectric layer and the metal conductive layer; disposing a second dielectric layer on the sidewall of the piezoelectric layer; exposing the device layer via a first opening in the handle layer; and exposing the piezoelectric layer through the first opening and a second opening in the device layer.

Additional machine executed method acts can also include: selectively removing a portion of the device layer; depositing an infra-red (IR) absorption layer on a selected portion of the device layer; and depositing an infra-red (IR) absorption layer on a selected portion of the piezoelectric layer.

In accordance with further examples the disclosure describes a microelectromechanical device that can comprise: a first silicon substrate bonded to a second silicon substrate, comprising: an electrode on the second silicon substrate that electrically contacts a conductivity layer disposed on the first silicon substrate; the conductivity layer on the first silicon substrate is disposed over a piezoelectric layer on the first silicon substrate; the piezoelectric layer on the first silicon substrate is deposited over a device layer that comprises a stand-off formed on the first silicon substrate; and the device layer on the first silicon substrate is bonded to an dielectric layer that is deposited over a surface of a handle layer on the first silicon substrate that comprises a cavity.

In addition to the foregoing, the subject application further describes MEMS devices and fingerprint sensing. There are two kinds of finger print sensors, namely swipe-based and area-based. For mobile applications, optical method is too bulky and expensive; thermal and swipe-based RF method are not the favored due to user experience; area-based ultrasound and RF sensors have challenges to lower the manufacturing cost. In general, above conventional fingerprint sensor technologies are subject to errors due to finger contamination, sensor contamination, imaging errors, etc. Various examples disclosed herein provide for improved fingerprint sensor performance by measuring a frequency response of a piezoelectric acoustic resonator.

For example, a device can include an array of piezoelectric transducers, and an array of cavities that has been attached to the array of piezoelectric transducers to form an array of resonators, e.g., an array of MEMS piezoelectric acoustic resonators. A resonator, e.g., a membrane resonator, a Helmholtz resonator, etc. of the array of resonators can be associated with a first frequency response, e.g., a resonant frequency of the resonator, a Q factor of the resonator, etc. corresponding to a determination that the resonator has a non-touch baseline condition. Then a second frequency response, e.g., increase in resonant frequency of the resonator, decrease in Q factor of the resonator, etc. corresponding to a determination that the resonator has been touched, e.g., by the finger ridge. Thus the finger print map can be determined according to the frequency response changes of resonators in the resonator array.

In an example, the array of piezoelectric transducers can include a piezoelectric material; a first set of electrodes that has been formed a first side of the piezoelectric material; and a second set of electrodes that has been formed on second side of the piezoelectric material - a piezoelectric transducer of the array of piezoelectric transducers corresponding to the resonator including a first electrode of the first set of electrodes and a second electrode of the second set of electrodes.

In another example, the piezoelectric transducer comprises a portion of the resonator, e.g., a membrane resonator, that has been touched. In yet another embodiment, a first end of a cavity of array of cavities corresponding to a portion of the resonator, e.g., a Helmholtz resonator, that has been touched is smaller than a second end of the cavity. In an example, the first end of the cavity is open to the environment, e.g., air adjacent to the device, etc. In another example, the cavity has been filled with a first material corresponding to a first acoustic velocity that is different from a second acoustic velocity corresponding to a second material that is adjacent to, surrounding, etc. the cavity.

Another example can include a system, e.g., a piezoelectric acoustic resonator based fingerprint sensor, etc. that can include an array of piezoelectric transducers; an array of cavities that has been attached to the array of piezoelectric transducers to form an array of resonators; a memory to store instructions; and a processor coupled to the memory, that facilitates execution of the instructions to perform operations, comprising: determining a frequency response of a resonator of the array of resonators - the resonator including a piezoelectric transducer of the array of piezoelectric transducers and a cavity of the array of cavities; and determining that the resonator has been touched, e.g., by a finger, etc. in response determining that a change in the frequency response satisfies a defined condition, e.g., a resonant frequency of the resonator has increased, a Q factor of the resonator has decreased, etc..

In one example, a first portion of the cavity, e.g., corresponding to a portion of the resonator that has been touched, is smaller than a second portion of the cavity. In another example, the first portion of the cavity is open to the environment. In yet another example, the cavity has been filled with a first material corresponding to a first acoustic velocity that is different from a second acoustic velocity corresponding to a second material that is adjacent to the cavity.

One example can include a method including forming an array of piezoelectric transducers on a first substrate; forming one or more portions of an array of cavities using a second substrate; and attaching the array of piezoelectric transducers to the second substrate to form an array of resonators. A resonator, e.g., a membrane resonator, a Helmholtz resonator, etc. of the array of resonators can be associated with a first frequency response with respect to, e.g., a resonant frequency of the resonator, a Q factor of the resonator, etc. corresponding to a determined non-touch of the resonator. Further, the resonator can be associated with a second frequency response with respect to, e.g., the resonant frequency, the Q factor, etc. corresponding to a determined touch of the resonator. Furthermore, the method can include removing the first substrate from the array of piezoelectric transducers.

In an example, the forming of the array of piezoelectric transducers can include forming a first set of electrodes on a first side of a piezoelectric material, and forming a second set of electrodes on a second side of the piezoelectric material - a piezoelectric transducer of the array of piezoelectric transducers corresponding to the resonator can include a first electrode of the first set of electrodes and a second electrode of the second set of electrodes.

In another example, the method can include filling a cavity of the array of cavities corresponding to the resonator, e.g., the Helmholtz resonator, with a material having a first acoustic velocity that is different from a second acoustic velocity of the second substrate.

Referring now to <FIG>, a block diagram of a piezoelectric acoustic resonator based sensor <NUM> is illustrated. Piezoelectric acoustic resonator based sensor <NUM> includes control component <NUM> and array of piezoelectric acoustic resonators <NUM>. Control component <NUM>, e.g., a system, an application specific integrated circuit (ASIC), etc. can include computing device(s), memory device(s), computing system(s), logic, etc. for generating stimuli, e.g., via TX component <NUM>, detecting a response to the stimuli, e.g., via RX component <NUM>, and determining, e.g., via processing component <NUM> based on the stimuli and the response to the stimuli, a frequency response, e.g., a change in a resonant frequency, a change in a Q factor, etc. of a piezoelectric acoustic resonator (<NUM>, <NUM> (see below), <NUM> (see below), etc.) of array of piezoelectric acoustic resonators <NUM>. In this regard, processing component <NUM> can determine, based on the frequency response, whether the piezoelectric acoustic resonator has been touched, e.g., by a ridge of a finger, and further derive a fingerprint based on determining which piezoelectric acoustic resonator(s) <NUM> of array of piezoelectric acoustic resonators <NUM> have been touched.

<FIG> illustrates a block diagram of a cross section of MEMS piezoelectric acoustic resonator 1605MEMS piezoelectric acoustic resonator <NUM>, e.g., a Helmholtz resonator, includes cavity <NUM> that has been formed by, within, etc. substrate <NUM>, e.g., a silicon based material, etc. In the embodiment illustrated by <FIG>, cavity <NUM> includes an opening that is exposed to the environment, e.g., air. Further, a cross section of a first end, or top portion, of cavity <NUM> is smaller than a cross section of a second end, or bottom portion, of cavity <NUM>, e.g., enabling cavity <NUM> to experience a resonant frequency (fH), or Helmholtz resonance, e.g., as defined by Equation (<NUM>) below: <MAT> where A is the cross-sectional area of the top portion, or "neck", of cavity <NUM>, V<NUM> is the static volume of cavity <NUM>, Leq is the equivalent length of the neck with end correction, and v is the speed of sound in a gas as given by Equation (<NUM>) below: <MAT> where ϑ is the ambient temperature in degree Celsius.

MEMS piezoelectric acoustic resonator <NUM> includes piezoelectric transducer <NUM>, which includes top electrode <NUM>, piezoelectric material <NUM>, e.g., piezoelectric membrane, polyvinylidene fluoride (PVDF), etc. and bottom electrode <NUM>. In one embodiment, top electrode <NUM> and bottom electrode <NUM> can be manufactured from a conductive material, e.g., metal, and control component <NUM> can generate and apply a stimulus, e.g., a pulse signal, a frequency sweep, an alternating current (AC) voltage, an AC current, etc. to piezoelectric transducer <NUM> via top electrode <NUM> and bottom electrode <NUM>. As illustrated by <FIG>, control component <NUM> can measure, e.g., utilizing a network analyzer, etc. based on the stimulus, e.g., based on a Fourier transform analysis, resonant frequency <NUM>, e.g., corresponding to a non-touch of piezoelectric acoustic resonator <NUM>, and resonant frequency <NUM>, e.g., corresponding to a touch of piezoelectric acoustic resonator <NUM>. In this regard, in response to determining that the resonant frequency of piezoelectric acoustic resonator <NUM> has increased, e.g., to resonant frequency <NUM>, control component <NUM> can determine that MEMS piezoelectric acoustic resonator <NUM> has been touched, e.g., by a ridge of a finger.

<FIG> illustrates a block diagram of a cross section a MEMS piezoelectric acoustic resonator including material <NUM>. As illustrated by <FIG>, cavity <NUM> can be filled with material <NUM>, e.g., rubber, gel, etc. that is associated with a first acoustic velocity that is different from a second acoustic velocity corresponding to substrate <NUM>. In this regard, a resonant frequency of MEMS piezoelectric acoustic resonator <NUM> can be modified in a predetermined manner by selecting material <NUM> of a predetermined acoustic velocity with respect to an acoustic velocity of substrate <NUM>. Further, including material <NUM> in cavity <NUM> can prevent debris, contaminants, etc. from entering cavity <NUM> and subsequently introducing errors in measurements of the resonant frequency of MEMS piezoelectric acoustic resonator <NUM>.

<FIG> illustrates a block diagram of a cross section of a portion of an array (<NUM>) of MEMS piezoelectric acoustic resonators (<NUM>) being contacted by finger <NUM>. Control component <NUM> can determine that finger ridge <NUM> has touched a MEMS piezoelectric acoustic resonator (<NUM>) of the portion of the array based on a determination that a resonant frequency of the MEMS piezoelectric acoustic resonator has increased. Further, control component <NUM> can determine that other MEMS piezoelectric acoustic resonators (<NUM>) of the portion of the array have not been touched, e.g., by finger ridge <NUM> and finger ridge <NUM>, based on respective determinations that resonant frequencies of the other MEMS piezoelectric acoustic resonators has not changed. In this regard, control component <NUM> can derive, based on such determinations, a fingerprint corresponding to finger <NUM>.

Now referring to <FIG>, a block diagram of a cross section of MEMS piezoelectric acoustic resonator <NUM> is illustrated. MEMS piezoelectric acoustic resonator <NUM>, e.g., a membrane resonator, includes cavity <NUM> that has been formed by, within, etc. substrate <NUM>, e.g., a silicon based material, and has been enclosed by bottom electrode <NUM> of piezoelectric transducer <NUM>. Control component <NUM> can generate and apply a stimulus, e.g., a pulse signal, a frequency sweep, an alternating AC voltage, an AC current, etc. to piezoelectric transducer <NUM> via top electrode <NUM> and bottom electrode <NUM>.

As illustrated by <FIG>, control component <NUM> can measure, based on the stimulus, Q factor <NUM>, e.g., corresponding to a non-touch of piezoelectric acoustic resonator <NUM>, and Q factor <NUM>, e.g., corresponding to a touch of piezoelectric acoustic resonator <NUM>. In this regard, in response to determining that the Q factor of piezoelectric acoustic resonator <NUM> has decreased, e.g., to Q factor <NUM>, control component <NUM> can determine that MEMS piezoelectric acoustic resonator <NUM> has been touched, e.g., by a ridge of a finger.

<FIG> illustrates a block diagram of a cross section of a portion of an array (<NUM>) of MEMS piezoelectric acoustic resonators (<NUM>) being contacted by finger <NUM>. Control component <NUM> can determine that finger ridge <NUM> has touched a MEMS piezoelectric acoustic resonator (<NUM>) of the portion of the array based on a determination that a Q factor of the MEMS piezoelectric acoustic resonator has decreased. Further, control component <NUM> can determine that other MEMS piezoelectric acoustic resonators (<NUM>) of the portion of the array have not been touched, e.g., by finger ridge <NUM> and finger ridge <NUM>, based on respective determinations that Q factors of the other MEMS piezoelectric acoustic resonators have not changed. In this regard, control component <NUM> can derive, based on such determinations, a fingerprint corresponding to finger <NUM>.

In an example illustrated by <FIG>, top electrode <NUM> can form a square shape that can be smaller, and located above, a square shape of bottom electrode <NUM>. In yet another example illustrated by <FIG>, top electrode <NUM> can form a shape of a regular polygon that can be smaller, and located above, a regular polygon shape of bottom electrode <NUM>. In this regard, it should be appreciated by a person of ordinary skill in MEMS technologies having the benefit of the instant disclosure that embodiments of devices disclosed herein can comprise electrodes of various shapes. As a non-limiting example, <FIG> provides further shapes and configurations of exemplary PMUT arrays having high fill factor, in accordance with further non-limiting embodiments.

Referring now to <FIG>, a block diagram (<NUM>) representing a method for manufacturing, assembling, etc. a MEMS piezoelectric acoustic resonator, e.g., MEMS piezoelectric acoustic resonator <NUM>, is illustrated. At <NUM>, an array of piezoelectric transducers (<NUM>) can be formed on substrate <NUM>. For example, bottom electrodes (<NUM>) can be formed on substrate <NUM>; dielectric material <NUM> can be formed on, placed on, etc. the bottom electrodes; and top electrodes (<NUM>) can be formed on, placed on, etc. dielectric material <NUM>.

At <NUM>, portions(s) of an array of cavities (<NUM>) can be formed on substrate <NUM>. At <NUM>, the portion(s) of the array of cavities can be placed on, attached to, etc. the array of piezoelectric transducers (<NUM>). In another embodiment (not shown), one or more cavities of the array of cavities can be filled with a material having a first acoustic velocity that is different from a second acoustic velocity of substrate <NUM>. At <NUM>, substrate <NUM> can be removed from the bottom electrodes.

<FIG> illustrates a block diagram (<NUM>) representing another method for manufacturing, assembling, etc. a MEMS piezoelectric acoustic resonator, e.g., MEMS piezoelectric acoustic resonator <NUM>, is illustrated. At <NUM>, an array of piezoelectric transducers (<NUM>) can be formed on substrate <NUM>. For example, top electrodes can be formed on substrate <NUM>; dielectric material <NUM> can be formed on, placed on, etc. the top electrodes and substrate <NUM>; and bottom electrodes (<NUM>) can be formed on, placed on, etc. dielectric material <NUM>.

At <NUM>, portions(s) of an array of cavities (<NUM>) can be formed on substrate <NUM>. At <NUM>, the portion(s) of the array of cavities can be placed on, attached to, etc. the array of piezoelectric transducers (<NUM>). At <NUM>, substrate <NUM> can be removed from dielectric material <NUM> and the top electrodes.

The order in which some or all of the manufacturing, assembling, etc. steps described above with respect to block diagrams <NUM> and <NUM> should not be deemed limiting. Rather, it should be understood by a person of ordinary skill in MEMS technologies having the benefit of the instant disclosure that some of the steps can be executed in a variety of orders not illustrated.

In addition to the foregoing, the subject application further describes PMUTs for fingerprint sensing. As described above, MUT devices, as an alternative method for fingerprint detection typically require MUT devices to be manufactured in the resolution of at least <NUM> dpi or higher e.g., approximately <NUM> pixel size. In addition, for mobile applications, optical method can be too bulky or expensive; thermal and capacitive sensing swipe-based method are not the favored due to user experience. As area-based fingerprint sensor is convenient in usage, it is suitable for adoption in mobile devices and can provide a sufficient level of security. Moreover, ultrasonic fingerprint detection can overcome deficiencies associated with skin condition and/or sensor contamination that afflict the accuracy of fingerprint detection devices employing CMUT linear arrays. For example, existing fingerprint sensors are mostly based on capacitive sensing. Their detection ability is readily compromised by excessively dry or wet fingerprints and/or contamination from sweat or oil. Ultrasonic detection does not rely on electrical property, instead, it relies on physical contact and acoustic impedance difference and is proven to be able to detect ridges and valleys and also sweat pores which are not so easily detectable with capacitive sensing.

Various embodiments disclosed herein provide integrated PMUTs on IC for fingerprint sensing. Additionally, various embodiments can provide an efficient way of creating electrical coupling and mechanical anchoring of ultrasonic transducer pMUT directly on CMOS for reduced parasitics and fully utilize the routing capability on CMOS metal layers.

In addition, in order to achieve a compact PMUT array with good resolution, it is desirable to achieve a high fill factor for a PMUT array that can provide a desired output pressure for the ultrasound transducer array. Various embodiments described herein can thus increase the increase the signal to noise ratio (SNR) of PMUT arrays during detection and the array gain, which is the ratio of the array's output pressure to that of a single PMUT device. However, increasing fill factor can suppress mechanical coupling between adjacent PMUT pixels. Thus, to achieve proper mechanical coupling or anchor while achieving a high fill factor, it is desired to minimize the anchor occupation ratio compared to the PMUT "active" area. Thus, various embodiments disclosed herein provide integrated PMUTs on IC for fingerprint sensing where the PMUT structures and the array of PMUT structures are configured in a rhombus configuration, a hexagonal configuration, and/or a combination of rhombus configuration and hexagonal configuration.

For example, <FIG> depicts a cross-section of an exemplary PMUT <NUM> for fingerprint sensing, in accordance with various embodiments. As a non-limiting example, exemplary PMUT <NUM> can comprise an engineered silicon-on-insulator (ESOI) wafer that can comprise a SOI wafer with one or more cavities beneath the silicon device layer or substrate. For instance, exemplary PMUT <NUM> can comprise cavity <NUM> in PMUT wafer/layer/substrate <NUM>, to which a silicon dioxide layer/substrate <NUM> can be deposited on PMUT wafer/layer/substrate <NUM> thereby overlaying PMUT wafer/layer/substrate <NUM>. Disposed and/or deposited over silicon dioxide layer/substrate <NUM> and/or fusion bonded to the silicon dioxide layer/substrate <NUM> can be a substrate/layer formed of silicon <NUM> or silicon structural substrate/layer <NUM>. As described above regarding <FIG>, for example, the PMUT wafer/layer/substrate <NUM> inclusive of one or more formed cavity <NUM> and silicon dioxide layer/substrate <NUM> can be referred to as an engineered substrate, and for purposes of this disclosure can be referred to as MEMS handle layer.

<FIG> further depicts, in inset <NUM>, exemplary PMUT <NUM> further comprising successively deposited exemplary aluminum nitride (AlN) seed layer <NUM>, molybdenum (Mo) layer <NUM>, and AlN stacking layer <NUM>, upon which silicon dioxide standoffs <NUM> can be formed to prepare a movable space of exemplary PMUT <NUM>. The additional deposited or disposed layers comprising the aluminum nitride seed layer <NUM>, molybdenum layer <NUM>, aluminum nitride stacking layer <NUM> and silicon dioxide standoffs <NUM> over substrate/layer formed of silicon <NUM> can be referred to as PMUT device layer/wafer/substrate and/or piezoelectric layer/wafer/substrate.

Substrate/layer formed of silicon <NUM> can be the silicon structural layer of the PMUT device layer to which the MEMS handle layer (e.g., PMUT wafer/layer/substrate <NUM> inclusive of cavities <NUM> and silicon dioxide layer/substrate <NUM>) can have been fusion bonded to the PMUT device layer/wafer/substrate (e.g., silicon structural substrate/layer <NUM>, aluminum nitride seed layer <NUM>, molybdenum layer <NUM>, aluminum nitride stacking layer <NUM>, and standoffs <NUM>). It should be noted that, if fusion bonded to the PMUT device layer, the fusion bonding of the MEMS handle layer to the PMUT device layer can comprise the MEMS handle layer being oxidized and the silicon structural layer/substrate <NUM> of the PMUT device layer being ground and polished to a target or defined thickness prior to deposition of the aluminum nitride seed layer <NUM>, molybdenum layer <NUM>, aluminum nitride stacking layer <NUM>, and standoffs <NUM> formed of silicon dioxide. Standoffs <NUM> are typically formed on the PMUT device layer to provide separation between the MEMS structure and a CMOS wafer/layer/substrate, for example, as depicted in <FIG>.

<FIG> further depicts exemplary PMUT <NUM> further comprising structures defined for one or more bottom electrodes <NUM> that can be carved out by first disposing or depositing a silicon dioxide hard mask (not shown) over the aluminum nitride stacking layer <NUM> and standoffs <NUM> and thereafter etching through silicon dioxide hard mask (not shown) to define the structure and carve out one or more bottom electrodes <NUM>, for example, as described above regarding <FIG>, for example. As can be understood, the etching process can etch through layers/substrates respectively formed of silicon dioxide hard mask (not shown), aluminum nitride stacking layer <NUM>, and molybdenum layer <NUM>.

One or more bottom electrode <NUM> contacts <NUM> can be created, as depicted in <FIG>. In addition, an opening etch on silicon dioxide hard mask (not shown) can be performed to define aluminum top electrode <NUM> contacts, thus forming electrical contacts to the molybdenum layer <NUM> and aluminum nitride stacking layer <NUM>. The defined structure and carved out one or more bottom electrodes <NUM>, the bottom electrode <NUM> contact <NUM>, and the aluminum top electrode <NUM> contacts, as depicted in <FIG>, can be undertaken by patterning the aluminum or other suitable material through a silicon dioxide hard mark (not shown).

In addition, aluminum and titanium layers (not shown) can be deposited for the purposes of top electrode material deposition and then germanium layers <NUM> can be deposited over the aluminum and titanium (not shown) so that pads and electrodes can be patterned, as described above regarding <FIG>, for example, as well as forming a barrier layer and eutectic bonding layer.

<FIG> depicts a cross-section <NUM> of exemplary PMUT <NUM> for fingerprint sensing on IC comprising exemplary PMUT <NUM> bonded to an exemplary CMOS wafer <NUM>, in accordance with further non-limiting embodiments. For example, an exemplary CMOS wafer <NUM> can comprise exemplary source/drain regions <NUM>, gate <NUM>, one or more vias <NUM>, and one or more metal layers including a first metal layer <NUM> and an exemplary top metal layer <NUM>. In a non-limiting aspect, an exemplary top metal layer <NUM> of exemplary CMOS wafer <NUM> can comprise aluminum.

Thus, as described above regarding <FIG>, for example, exemplary CMOS wafer <NUM> and exemplary PMUT <NUM> can be bonded using an aluminum-germanium eutectic bond between exemplary top metal layer <NUM> of exemplary CMOS wafer <NUM> and germanium layers <NUM> on standoffs <NUM> of exemplary PMUT <NUM>. The Aluminum-Germanium eutectic bond can create a hermetic seal around desired MEMS structures and/or CMOS wafer <NUM> circuits and form a bonded wafer comprising exemplary CMOS wafer <NUM> and exemplary PMUT <NUM>. As can be understood the single bonding process using an Aluminum-Germanium eutectic bond provides hermetic sealing, mechanical anchoring, and electrical connection in one step. The eutectically bonded wafer comprising exemplary CMOS wafer <NUM> and exemplary PMUT <NUM> can then be thinned, for instance, on the PMUT wafer/layer/substrate <NUM> side, to a defined or desired thickness. In addition, a port or cavity (e.g., cavity <NUM> or other) can be formed on a polished side of the PMUT wafer/layer/substrate <NUM> to create access to the surrounding environment, as describe above regarding <FIG>, for example. For instance, an etch can be performed on the top side of the bonded wafer to form an acoustic port or cavity for sound propagation.

As described above, achieving high fill factor for a PMUT array can provide a desired output pressure for the ultrasound transducer array, increasing the PMUT array gain. However, increasing fill factor can suppress mechanical coupling between adjacent PMUT pixels. Thus, to achieve proper mechanical coupling or anchor while achieving a high fill factor is desired to minimize the anchor occupation ratio compared to the PMUT "active" area. Thus, various embodiments disclosed herein provide integrated PMUTs on IC for fingerprint sensing where the PMUT structures and the array of PMUT structures are configured in a rhombus configuration, a hexagonal configuration, and/or a combination of rhombus configuration and hexagonal configuration.

Accordingly, <FIG> depicts cross-sections of exemplary PMUT arrays (<NUM>, <NUM>, <NUM>) having high fill factor, in accordance with further non-limiting embodiments. As non-limiting examples, <FIG> depicts exemplary PMUT arrays (<NUM>, <NUM>, <NUM>) comprising PMUT structures in the exemplary PMUT arrays (<NUM>, <NUM>, <NUM>) of PMUT structures that are configured in a rhombus configuration (<NUM>, <NUM>) or a hexagonal configuration (<NUM>, <NUM>). As depicted in <FIG>, the exemplary PMUT arrays (<NUM>) of PMUT structures can comprise PMUT structures that are configured in a rhombus configuration (<NUM>), the exemplary PMUT arrays (<NUM>) of PMUT structures can comprise PMUT structures that are configured in a hexagonal configuration (<NUM>), or the exemplary PMUT arrays (<NUM>) of PMUT structures can comprise PMUT structures that are configured in a combination of rhombus configuration (<NUM>) and hexagonal configuration (<NUM>) arranged as a unit cell.

Note that, according to a non-limiting aspect, edges of the PMUT structures between neighboring PMUT structures of the exemplary PMUT arrays (<NUM>, <NUM>, <NUM>) can correspond to mechanical anchor <NUM> points for the PMUT structure, for example, such as provided by aluminum-germanium eutectic bond between exemplary top metal layer <NUM> of exemplary CMOS wafer <NUM> and germanium layers <NUM> on standoffs <NUM> of exemplary PMUT <NUM>, as described above, regarding <FIG>, for example. As described above, to achieve proper mechanical coupling or mechanical anchor <NUM> while achieving a high fill factor, it is desired to minimize the anchor occupation ratio compared to the PMUT structure active area <NUM>. Exemplary PMUT arrays (<NUM>, <NUM>, <NUM>), as described herein, can provide high fill factor, thus increasing the array gain of exemplary PMUT arrays (<NUM>, <NUM>, <NUM>).

In another non-limiting aspect, exemplary PMUT arrays (<NUM>) of PMUT structures comprising PMUT structures configured in a hexagonal configuration (<NUM>) can be formed in quadrilateral shape having angles of about <NUM> degrees. In a further non-limiting aspect, exemplary PMUT arrays (<NUM>) of PMUT structures comprising PMUT structures configured in a rhombus configuration (<NUM>) can be formed in quadrilateral shape having angles of about <NUM> degrees and about <NUM> degrees.

While the foregoing can provide exemplary PMUTs on IC for fingerprint sensing comprising compact PMUT arrays with good resolution, silicon fabrication cost of exemplary PMUT <NUM> bonded to an exemplary CMOS wafer <NUM>, as described above regarding <FIG>, can be improved, for example, by integrating exemplary PMUTs on IC (e.g., an exemplary CMOS wafer) for fingerprint sensing. Accordingly, <FIG> depicts a cross-section of exemplary PMUT for fingerprint sensing on IC comprising exemplary PMUT <NUM> integrated on an exemplary CMOS wafer. As a non-limiting example, an exemplary PMUT <NUM> can be integrated on an exemplary CMOS wafer, as described below regarding <FIG>.

For example, <FIG> depicts a cross-section <NUM> of an exemplary CMOS wafer <NUM> suitable for incorporation of aspects of the subject disclosure directed to fabrication of exemplary PMUT and PMUT arrays for fingerprint sensing on IC comprising exemplary one or more exemplary PMUTs integrated on exemplary CMOS wafer <NUM>. As a non-limiting example, exemplary CMOS wafer <NUM> can comprise exemplary source/drain regions <NUM>, gate <NUM>, one or more vias <NUM>, and one or more metal layers including a first metal layer <NUM> and an exemplary top metal layer <NUM>. In a non-limiting aspect, an exemplary top metal layer <NUM> of exemplary CMOS wafer <NUM> can comprise aluminum. In addition, exemplary CMOS wafer <NUM> can comprise an exemplary silicon dioxide layer <NUM> disposed over the exemplary top metal layer <NUM> and an exemplary passivation layer <NUM> disposed over the exemplary silicon dioxide layer <NUM>.

<FIG> depicts a cross-section <NUM> of an exemplary CMOS wafer <NUM> comprising one or more exemplary cavities <NUM>, in accordance with further aspects described herein directed to a non-limiting cavity deposition etch process. As a non-limiting example, exemplary passivation layer <NUM> and exemplary silicon dioxide layer <NUM> can be etched in a desired pattern with a timed etch is then performed to create the one or more exemplary cavities <NUM>. In a further non-limiting aspect, the one or more exemplary cavities <NUM> can be created by employing a timed etch , resulting in an exemplary cavity depth of less than <NUM> (+/-<NUM>%).

<FIG> depicts a cross-section <NUM> of an exemplary CMOS wafer <NUM> comprising one or more exemplary sacrificial materials <NUM>, in accordance with further aspects described herein directed to non-limiting amorphous silicon deposition and subsequent chemical-mechanical planarizing processes. As a non-limiting example, one or more exemplary sacrificial materials <NUM>, e.g., such as amorphous silicon, etc. can be deposited in the one or more exemplary cavities <NUM>. In a non-limiting aspect, the one or more exemplary sacrificial materials <NUM> can comprise amorphous silicon. In a further non-limiting aspect, the one or more exemplary sacrificial materials <NUM> can comprise silicon-germanium (SiGe) or tungsten (W), which including amorphous silicon are all CMOS foundry compatible materials and can be removed with xenon difluoride (XeF<NUM>) or sulfur hexafluoride (SF<NUM>). In another non-limiting aspect, exemplary CMOS wafer <NUM> comprising one or more exemplary sacrificial materials <NUM> can be polished (e.g., chemical-mechanical planarizing) to planarize the surface, resulting in a sacrificial material film thickness of about less than <NUM> to prevent cracking and peeling of the sacrificial material film.

<FIG> depicts a cross-section <NUM> of an exemplary CMOS wafer <NUM> comprising one or more exemplary silicon dioxide (SiO<NUM>) layers <NUM>, in accordance with further aspects described herein directed to a non-limiting silicon dioxide deposition process. As a non-limiting example, one or more exemplary silicon dioxide (SiO<NUM>) layers <NUM> can be deposited to cover the surface of the exemplary CMOS wafer <NUM> comprising one or more exemplary sacrificial materials <NUM> and serve as a structure material in the fabrication of one or more exemplary PMUTs integrated on exemplary CMOS wafer <NUM>.

<FIG> depicts a cross-section <NUM> of an exemplary CMOS wafer <NUM> comprising one or more exemplary seal holes <NUM>, in accordance with further aspects described herein directed to a non-limiting release hole opening process. Accordingly, in a further non-limiting aspect, exemplary CMOS wafer <NUM> comprising one or more exemplary silicon dioxide (SiO<NUM>) layers <NUM> can be etched to create one or more seal holes. In another non-limiting aspect, for example, as depicted inset <NUM>, a seal hole profile having an aspect ratio greater than <NUM> can facilitate providing adequate sealing of the one or more exemplary cavities <NUM>. In addition, in a further non-limiting aspect, layout for the one or more exemplary cavities <NUM> and one or more exemplary seal holes <NUM> can comprise the one or more exemplary seal holes <NUM> placed at the respective edges of the one or more exemplary cavities <NUM>, such that sealing of the one or more exemplary seal holes <NUM> does not create an obstruction if the area in the one or more exemplary cavities <NUM> directly underneath the one or more exemplary seal holes <NUM> is fully filled, for example, as depicted in <FIG>.

<FIG> depicts a cross-section <NUM> of an exemplary CMOS wafer <NUM> comprising one or more exemplary cavities <NUM>, in accordance with further aspects described herein directed to a non-limiting release etch process. Accordingly, in a further non-limiting aspect, exemplary CMOS wafer <NUM> comprising the one or more exemplary seal holes <NUM> and one or more exemplary sacrificial materials <NUM> can be exposed to a sacrificial release etch to remove the one or more exemplary sacrificial materials <NUM> (e.g., amorphous silicon, etc.). Exemplary CMOS wafer <NUM> comprising the one or more exemplary seal holes <NUM> and one or more exemplary sacrificial materials <NUM> can be exposed to a sacrificial release etch employing either a dry etch or a wet etch. As a non-limiting example, an exemplary dry etch can employ XeF2 or SF6 as etching gas. In a further non-limiting example, an exemplary wet etch can employ poly-etch (e.g., H:N:A, or a solution of Hydrofluoric Acid (HF):Nitric Acid (HNO<NUM>):Acetic acid (CH<NUM>COOH) in a desired ratio), potassium hydroxide (KOH) or tetramethyl ammonium hydroxide (TMAH), with care taken to prevent stiction of the membrane created from the one or more exemplary silicon dioxide (SiO<NUM>) layers <NUM>. The one or more exemplary sacrificial materials <NUM> thus removed, <FIG> depicts exemplary CMOS wafer <NUM> comprising one or more exemplary cavities <NUM> and one or more exemplary unsealed seal holes <NUM>, for example, in inset <NUM>.

<FIG> depicts a cross-section <NUM> of an exemplary CMOS wafer <NUM> comprising one or more exemplary seal hole seals <NUM>, in accordance with further aspects described herein directed to non-limiting seal deposition and etch back processes. As a non-limiting example, exemplary CMOS wafer <NUM> comprising one or more exemplary cavities <NUM> and one or more exemplary unsealed seal holes <NUM> can be exposed to a plasma-enhanced chemical vapor deposition (PECVD) process for SiO<NUM> deposition to create the one or more exemplary seal hole seals <NUM> as depicted in inset <NUM>. As can be understood, the PECVD of SiO<NUM> can create additional thickness of silicon dioxide which can be subject to an etch back process to control the final structure membrane thickness. It is further noted that, SiO<NUM> is defect tolerable for subsequent AlN deposition.

<FIG> depicts a cross-section <NUM> of an exemplary CMOS wafer <NUM>, in inset <NUM>, for example, comprising an exemplary aluminum nitride (AlN) seed layer <NUM>, molybdenum (Mo) layer <NUM>, and AlN stacking layer <NUM>, in accordance with further aspects described herein directed to AlN Seed/Mo/AlN deposition processes, for example, as further describe above regarding <FIG>, <FIG>, etc..

One or more exemplary bottom contacts <NUM> to molybdenum (Mo) layer <NUM> and one or more exemplary vias <NUM> contact to exemplary top metal layer <NUM> of exemplary CMOS wafer <NUM> can then be created by employing a hard mask on top of AlN stacking layer <NUM>. Thus, <FIG> depicts a cross-section <NUM> of an exemplary CMOS wafer <NUM> comprising one or more exemplary SiO<NUM> layers <NUM>, in accordance with further aspects described herein directed to a non-limiting hard mask deposition process. In addition, <FIG> depicts a cross-section <NUM> of an exemplary CMOS wafer <NUM>, in inset <NUM> comprising one or more exemplary bottom contacts <NUM>, in accordance with further aspects described herein directed to a non-limiting bottom contact to molybdenum fabrication process. In a non-limiting aspect, in addition to etching one or more exemplary bottom contacts <NUM> to molybdenum (Mo) layer <NUM>, areas comprising AlN (e.g., selected areas of AlN stacking layer <NUM>) over the one or more exemplary vias <NUM> contact to exemplary top metal layer <NUM> can also be etched to reduce etch difficulty in fabricating the one or more exemplary vias <NUM> contact to exemplary top metal layer <NUM>. Thus, <FIG> depicts a cross-section <NUM> of an exemplary CMOS wafer comprising <NUM> one or more exemplary vias <NUM>, in accordance with further aspects described herein directed to a non-limiting wafer via etch process. Subsequently, the hard mask comprising one or more exemplary SiO<NUM> layers <NUM> can be removed as shown in <FIG>, which depicts a cross-section <NUM> of an exemplary CMOS wafer <NUM> comprising an exposed AlN surface <NUM> (e.g., AlN stacking layer <NUM>), in accordance with further aspects described herein directed to a non-limiting hard mask removal process.

<FIG> depicts a cross-section of an exemplary CMOS wafer comprising one or more exemplary SiO<NUM> spacers <NUM>, in accordance with further aspects described herein directed to a non-limiting SiO<NUM> spacer fabrication process. As a non-limiting example, a layer of SiO<NUM> (not shown) can be deposited and blank etched (e.g., without a mask material such as a photo resistive layer described above) to remove the top surface oxide completely while preserving the one or more exemplary SiO<NUM> spacers <NUM>. <FIG> depicts a cross-section <NUM> of an exemplary CMOS wafer <NUM> comprising one or more exemplary top electrodes <NUM>, in accordance with further aspects described herein directed to a non-limiting top electrode fabrication process. As a non-limiting example, one or more exemplary top electrodes <NUM> material (e.g., aluminum, etc.) can be deposited and patterned to form the one or more exemplary top electrodes <NUM> for exemplary PMUT and PMUT arrays and to form electrical connection to exemplary top metal layer <NUM> of exemplary CMOS wafer <NUM>. As can be seen <FIG>, preserving the one or more exemplary SiO<NUM> spacers <NUM> can prevent shorting of the one or more exemplary top electrodes <NUM> and the one or more exemplary bottom contacts <NUM> to the bottom electrode and exemplary aluminum nitride (AlN) seed layer <NUM>.

<FIG> depicts exemplary PMUT for fingerprint sensing on IC comprising exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM> as described above regarding <FIG>, for which exemplary CMOS <NUM> wafer comprises one or more exemplary passivation layers <NUM>, in accordance with further aspects described herein directed to a non-limiting passivation process. As a non-limiting example, one or more exemplary passivation layers <NUM> can be deposited on exemplary CMOS <NUM> wafer and patterned to open one or more wire bond pads <NUM> and/or one or more vias <NUM> of exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>. As described above, inset <NUM> depicts various non-limiting aspects of exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, for example, as described above regarding <FIG>.

Accordingly, various non-limiting embodiments of the subject disclosure can comprise an exemplary MEMS device (e.g., exemplary PMUT <NUM> for fingerprint sensing on IC comprising exemplary PMUT <NUM> bonded to an exemplary CMOS wafer <NUM>, exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.), comprising a MUT structure (e.g., exemplary PMUT <NUM> or portions thereof, exemplary PMUT <NUM> or portions thereof, etc.) and a piezoelectric material (e.g., one or more of aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3)) disposed within the MEMS device (e.g., exemplary PMUT <NUM> for fingerprint sensing on IC comprising exemplary PMUT <NUM> bonded to an exemplary CMOS wafer <NUM>, exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) comprising a PMUT array of a fingerprint sensor adapted to sense a characteristic of a fingerprint placed adjacent to the MUT structure.

Further non-limiting examples can comprise an exemplary MEMS device (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) comprising a MUT structure (e.g., exemplary PMUT <NUM> or portions thereof, etc.) formed integrally to the CMOS structure (e.g., exemplary CMOS wafer <NUM> or portions thereof, etc.) having a plurality of cavities (e.g., one or more exemplary cavities <NUM>, etc.) formed within the CMOS structure and the piezoelectric material (e.g., one or more of aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3)) disposed on the CMOS structure.

In a non-limiting aspect, exemplary MEMS device (e.g., exemplary PMUT <NUM> for fingerprint sensing on IC comprising exemplary PMUT <NUM> bonded to an exemplary CMOS wafer <NUM>, exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) can further comprise a first metal conductive layer (e.g., such as described regarding aluminum top electrode <NUM>, regarding one or more exemplary top electrodes <NUM>, etc., in reference to <FIG> and <FIG>) disposed on the piezoelectric material (e.g., one or more of aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3)).

In a further non-limiting aspect, exemplary MEMS device (e.g., exemplary PMUT <NUM> for fingerprint sensing on IC comprising exemplary PMUT <NUM> bonded to an exemplary CMOS wafer <NUM>, exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) can further comprise a plurality of metal electrodes (e.g., one or more of aluminum top electrodes <NUM>, one or more bottom electrodes <NUM>, one or more exemplary top electrodes <NUM>, one or more exemplary bottom contacts <NUM>, etc.) configured to form electrical connections between the first metal conductive layer (e.g., such as described regarding aluminum top electrode <NUM>, regarding one or more exemplary top electrodes <NUM>, etc., in reference to <FIG> and <FIG>), the piezoelectric material (e.g., one or more of aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3)), and a CMOS structure (e.g., exemplary CMOS wafer <NUM> or portions thereof, exemplary CMOS wafer <NUM> or portions thereof, etc.), wherein the pMUT structure and the CMOS structure are vertically stacked, for example, as depicted in <FIG>, <FIG>, etc..

In a further non-limiting aspect, exemplary MEMS device (e.g., exemplary PMUT <NUM> for fingerprint sensing on IC comprising exemplary PMUT <NUM> bonded to an exemplary CMOS wafer <NUM>, exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) can further comprise a second metal conductive layer (e.g., molybdenum (Mo) layer <NUM>, molybdenum (Mo) layer <NUM>, etc.) disposed on the piezoelectric material (e.g., one or more of aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3)) and opposite the first metal conductive layer. (e.g., such as described regarding aluminum top electrode <NUM>, regarding one or more exemplary top electrodes <NUM>, etc., in reference to <FIG> and <FIG>).

In addition, exemplary MEMS device (e.g., exemplary PMUT <NUM> for fingerprint sensing on IC comprising exemplary PMUT <NUM> bonded to an exemplary CMOS wafer <NUM>) can further comprise a stand-off (e.g., one or more silicon dioxide standoffs <NUM>, etc.) formed on the piezoelectric material (e.g., one or more of aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3)), according to further non-limiting aspects. For example, an exemplary stand-off (e.g., one or more silicon dioxide standoffs <NUM>, etc.) can comprise a silicon dioxide layer deposited over the piezoelectric material. In other non-limiting aspects, exemplary MEMS device (e.g., exemplary PMUT <NUM> for fingerprint sensing on IC comprising exemplary PMUT <NUM> bonded to an exemplary CMOS wafer <NUM>) can further comprise the MUT structure (e.g., exemplary PMUT <NUM> or portions thereof, etc.) bonded to the CMOS structure (e.g., exemplary CMOS wafer <NUM> or portions thereof, etc.) at the standoff (e.g., one or more silicon dioxide standoffs <NUM>, etc.) via at least one of a eutectic bonding layer (e.g., comprising an aluminum-germanium eutectic bonding layer, etc.), a compression bond, or a conductive epoxy and/or the MUT structure electrically coupled to the CMOS structure at the standoff, for example, as further described herein.

In further non-limiting aspect, exemplary MEMS device (e.g., exemplary PMUT <NUM> for fingerprint sensing on IC comprising exemplary PMUT <NUM> bonded to an exemplary CMOS wafer <NUM>, exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) can further comprise a piezoelectric layer comprising an aluminum nitride (AlN) seed layer, a bottom metal layer, and an aluminum nitride (AlN) layer, for example, as further described herein. In still another non-limiting aspect, exemplary MEMS device (e.g., exemplary PMUT <NUM> for fingerprint sensing on IC comprising exemplary PMUT <NUM> bonded to an exemplary CMOS wafer <NUM>, exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) can further comprise a PMUT array, as described herein, comprising the MUT structure (e.g., exemplary PMUT <NUM> or portions thereof, exemplary PMUT <NUM> or portions thereof, etc.) in an array of MUT structures (e.g., exemplary PMUT arrays (<NUM>, <NUM>, <NUM>), etc.), wherein the MUT structure in the array of MUT structures are configured in a rhombus configuration (<NUM>), in a hexagonal configuration (<NUM>), and/or any combination thereof (e.g., exemplary PMUT arrays <NUM>). As a non-limiting example, an exemplary MUT structure (e.g., exemplary PMUT <NUM> or portions thereof, exemplary PMUT <NUM> or portions thereof, etc.) and the array of MUT structures (e.g., exemplary PMUT arrays <NUM>, etc.) can comprise a first two of the array of MUT structures in the rhombus configuration <NUM> and a second two of the array of MUT structures in the hexagonal configuration <NUM> arranged as a unit cell (e.g., exemplary PMUT arrays <NUM>, etc.).

In addition, further examples can comprise an exemplary MEMS device (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.), comprising a CMOS device wafer (e.g., exemplary CMOS wafer <NUM>) associated with a PMUT array of a fingerprint sensor and having a plurality of cavities (e.g., cavities <NUM>) configured in an array.

Exemplary MEMS device (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) can further comprise a first metal conductive layer (e.g., such as described regarding one or more exemplary top electrodes <NUM>, etc., in reference to <FIG>) disposed on the CMOS device wafer (e.g., exemplary CMOS wafer <NUM>) and over the plurality of cavities (e.g., cavities <NUM>).

Exemplary MEMS device (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) can further comprise a piezoelectric material (e.g., one or more of aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3)) disposed on the first metal conductive layer (e.g., such as described regarding one or more exemplary top electrodes <NUM>, etc., in reference to <FIG>). In still another non-limiting aspect, exemplary MEMS device (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) can further comprise one or more bottom electrodes (e.g., one or more exemplary bottom contacts <NUM>, etc.) electrically coupled to one or more top electrodes (e.g., one or more exemplary top electrodes <NUM>, etc.) via the piezoelectric material. In addition, further non-limiting embodiments of exemplary MEMS device (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) can further comprise an acoustic propagation layer over the one or more top electrodes (e.g., one or more exemplary top electrodes <NUM>, etc.), for example, as further described above, for example, regarding <FIG>. As a non-limiting example, an exemplary acoustic propagation layer comprising a liquid, a polymer, or an acoustic impedance matching material configured to provide acoustic impedance matching between a PMUT device associated with the one or more top electrodes and the cover layer, can be deposited over the one or more top electrodes (e.g., one or more exemplary top electrodes <NUM>, etc.).

Exemplary MEMS device (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) can further comprise a second metal conductive layer (e.g., molybdenum (Mo) layer <NUM>, etc.), disposed on the piezoelectric material (e.g., one or more of aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3)), electrically coupling the second metal conductive layer and one or more CMOS device wafer electrode (e.g., associated with exemplary top metal layer <NUM>), and electrically coupling the first metal conductive layer (e.g., such as described regarding one or more exemplary top electrodes <NUM>, etc., in reference to <FIG>) to one or more other CMOS device wafer electrode (e.g., associated with exemplary top metal layer <NUM>), wherein the plurality of cavities (e.g., cavities <NUM>), the piezoelectric material, the first metal conductive layer, and the second metal conductive layer are configured as a plurality of PMUT structures (e.g., a plurality of exemplary PMUTs <NUM>, or portions thereof, integrated on exemplary CMOS wafer <NUM>, etc.).

The plurality of PMUT structures (e.g., a plurality of exemplary PMUTs <NUM>, or portions thereof, integrated on exemplary CMOS wafer <NUM>, etc.) can be formed integrally to a CMOS structure (e.g., exemplary CMOS wafer <NUM>, or portions thereof, etc.), and wherein the fingerprint sensor is adapted to sense a characteristic of a fingerprint placed adjacent to the PMUT array and opposite the plurality of cavities (e.g., cavities <NUM>). In a further non-limiting example, the plurality of PMUT structures (e.g., a plurality of exemplary PMUTs <NUM>, or portions thereof, integrated on exemplary CMOS wafer <NUM>, etc.) can comprise the plurality of PMUT structures in a rhombus configuration (<NUM>), in a hexagonal configuration (<NUM>), and/or in any combination thereof (e.g., exemplary PMUT arrays <NUM>). As a non-limiting example, an exemplary PMUT structure (e.g., exemplary PMUT <NUM> or portions thereof, etc.) and the plurality of PMUT structures (e.g., exemplary PMUT arrays <NUM>, etc.) can comprise a first two of the plurality of PMUT structures in the rhombus configuration <NUM> and a second two of the plurality of MUT structures in the hexagonal configuration <NUM> arranged as a unit cell (e.g., exemplary PMUT arrays <NUM>, etc.).

In view of the subject matter described supra, methods that can be implemented in accordance with the subject disclosure will be better appreciated with reference to the flowcharts of <FIG>. While for purposes of simplicity of explanation, the methods are shown and described as a series of blocks, it is to be understood and appreciated that such illustrations or corresponding descriptions are not limited by the order of the blocks, as some blocks may occur in different orders and/or concurrently with other blocks from what is depicted and described herein. Any non-sequential, or branched, flow illustrated via a flowchart should be understood to indicate that various other branches, flow paths, and orders of the blocks, can be implemented which achieve the same or a similar result. Moreover, not all illustrated blocks may be required to implement the methods described hereinafter.

<FIG> depicts an exemplary flowchart of non-limiting methods <NUM> associated with a various non-limiting examples of the subject disclosure. For instance, exemplary methods <NUM> can comprise, at <NUM>, forming a plurality of cavities (e.g., cavities <NUM>) in a CMOS device wafer (e.g., exemplary CMOS wafer <NUM>). As a non-limiting example, forming the plurality of cavities at <NUM> can comprise forming a PMUT (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) array of a fingerprint sensor adapted to sense a characteristic of a fingerprint placed adjacent to the PMUT array and opposite the plurality of cavities (e.g. cavities <NUM>). In a further non-limiting example, forming the PMUT array comprises forming a plurality of PMUT devices in a rhombus configuration (<NUM>), in a hexagonal configuration (<NUM>), and/or in any combination thereof (e.g., exemplary PMUT arrays <NUM>), for example, as further described above regarding <FIG>. In yet another non-limiting example, exemplary methods <NUM> can further comprise forming a first two of the plurality of PMUT devices (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) in the rhombus configuration <NUM> and a second two of the plurality of PMUT devices (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) in the hexagonal configuration <NUM> arranged as a unit cell (e.g., exemplary PMUT arrays <NUM>, etc.).

Exemplary methods <NUM> can further comprise, at <NUM>, depositing and patterning a piezoelectric layer (e.g., comprising aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3), etc.) over the plurality of cavities (e.g., cavities <NUM>). In addition, exemplary methods <NUM> can comprise, at <NUM>, forming a plurality of openings in the piezoelectric layer (e.g., comprising aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3), etc.) over the plurality of cavities (e.g., cavities <NUM>) to expose a first conductive material layer (e.g., molybdenum (Mo) layer <NUM>, etc.) under the piezoelectric layer and to expose at least one CMOS device wafer (e.g., exemplary CMOS wafer <NUM>) electrode (e.g., associated with exemplary top metal layer <NUM>).

In addition, exemplary methods <NUM>, at <NUM>, can further comprise depositing and patterning a second conductive material layer (e.g., such as described regarding one or more exemplary top electrodes <NUM>, etc., in reference to <FIG>) over the piezoelectric layer (e.g., comprising aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3), etc.) to establish an electrical connection between the one or more CMOS device wafer (e.g., exemplary CMOS wafer <NUM>) electrode (e.g., associated with exemplary top metal layer <NUM>) and the second conductive material layer. As a non-limiting example, exemplary methods <NUM> can further comprise, at <NUM>, forming one or more bottom electrodes (e.g., one or more exemplary bottom contacts <NUM>, etc.) electrically coupled to one or more top electrodes (e.g., one or more exemplary top electrodes <NUM>, etc.) via the piezoelectric layer.

Exemplary methods <NUM>, at <NUM>, can further comprise depositing an acoustic propagation layer over the one or more top electrodes (e.g., one or more exemplary top electrodes <NUM>, etc.), for example, as further described above, for example, regarding <FIG>. As a non-limiting example, an exemplary acoustic propagation layer comprising a liquid, a polymer, or an acoustic impedance matching material configured to provide acoustic impedance matching between a PMUT device (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) associated with the one or more top electrodes and the cover layer, can be deposited over the one or more top electrodes (e.g., one or more exemplary top electrodes <NUM>, etc.), for example, as described above regarding <FIG>. In addition, exemplary methods <NUM>, at <NUM>, can further comprise depositing a cover layer over the acoustic propagation layer, to facilitate providing further protection to the PMUT device (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.) from debris, contaminants, etc. from introducing errors in measurements associated with PMUT device (e.g., exemplary PMUT <NUM> integrated on exemplary CMOS wafer <NUM>, etc.).

<FIG> depicts another exemplary flowchart of non-limiting methods associated with a various non-limiting examplesof the subject disclosure. For instance, exemplary methods <NUM>, can comprise forming a plurality of cavities (e.g., cavities <NUM>) in a CMOS device wafer (e.g., exemplary CMOS wafer <NUM>). As a non-limiting example, exemplary methods <NUM>, at <NUM>, can comprise filling the plurality of cavities (e.g., cavities <NUM>) in the CMOS device wafer (e.g., exemplary CMOS wafer <NUM>) with sacrificial material (e.g., one or more exemplary sacrificial materials <NUM>, amorphous silicon, etc.). In a further non-limiting example, exemplary methods <NUM>, at <NUM>, can comprise planarizing the sacrificial material (e.g., one or more exemplary sacrificial materials <NUM>, amorphous silicon, etc.) on the CMOS device wafer (e.g., exemplary CMOS wafer <NUM>), and at <NUM>, can further comprise depositing a capping layer (e.g., one or more exemplary silicon dioxide (SiO<NUM>) layers <NUM>, etc.) over the sacrificial material (e.g., one or more exemplary sacrificial materials <NUM>, amorphous silicon, etc.).

Exemplary methods <NUM>, at <NUM>, can further comprise forming one or more openings (e.g., one or more exemplary seal holes <NUM>) in the capping layer (e.g., one or more exemplary silicon dioxide (SiO<NUM>) layers <NUM>, etc.) to expose the sacrificial material (e.g., one or more exemplary sacrificial materials <NUM>, amorphous silicon, etc.), and at <NUM>, can further comprise selectively removing the sacrificial material. In addition, exemplary methods <NUM>, at <NUM>, can further comprise sealing the one or more openings in the capping layer (e.g., one or more exemplary silicon dioxide (SiO<NUM>) layers <NUM>, etc.), in addition to depositing the first conductive material layer (e.g., molybdenum (Mo) layer <NUM>, etc.) comprising a metal conductive layer over the capping layer (e.g., one or more exemplary silicon dioxide (SiO<NUM>) layers <NUM>, etc.).

As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. In addition, the word "coupled" is used herein to mean direct or indirect electrical or mechanical coupling. In addition, the words "example" and/or "exemplary" are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example" and/or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word exemplary is intended to present concepts in a concrete fashion.

What has been described above includes examples of the subject disclosure. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the subject matter, but it is to be appreciated that many further combinations and permutations of the subject disclosure are possible within the scope of the appended claims.

The aforementioned systems have been described with respect to interaction between several components. Any components described herein may also interact with one or more other components not specifically described herein. Furthermore, to the extent that the terms "includes," "including," "has," "contains," variants thereof, and other similar words are used in either the detailed description or the claims, these terms are intended to be inclusive in a manner similar to the term "comprising" as an open transition word without precluding any additional or other elements.

Reference throughout this specification to "one embodiment," or "an embodiment," means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment," or "in an embodiment," in various places throughout this specification are not necessarily all referring to the same embodiment.

Claim 1:
A microelectromechanical system, MEMS, device, comprising:
a piezoelectric MEMS ultrasound transducer, PMUT, structure <NUM> including a piezoelectric material disposed on a PMUT substrate (<NUM>), wherein the PMUT structure comprises a fingerprint sensor adapted to sense a characteristic of a fingerprint placed adjacent to the PMUT structure;
a first metal conductive layer (<NUM>) disposed on the piezoelectric material;
a plurality of metal electrodes (<NUM>, <NUM>) configured to form electrical connections between the first metal conductive layer, the piezoelectric material, and a complementary metal oxide semiconductor, CMOS, (<NUM>) structure, wherein the PMUT structure and the CMOS structure are vertically stacked;
a stand-off (<NUM>) formed on the piezoelectric material, wherein the PMUT structure is bonded to the CMOS structure at the stand-off via an aluminum-germanium eutectic bonding layer; and
a second metal conductive layer (<NUM>) disposed on the piezoelectric material and opposite the first metal conductive layer, wherein the second metal conductive layer is electrically connected to the CMOS structure via another stand-off (<NUM>).