Patent Description:
MOCVD-grown p-(Al,In)GaN forms Mg-H complexes that reduce the number of free holes available for conduction and thereby increase the resistivity of the p-(Al,In)GaN layer. The introduction of hydrogen into the p-(Al,In)GaN layer is unavoidable during MOCVD growth because even if the deposition carrier gas does not include H<NUM>, the dissociation of NH<NUM> provides sufficient H<NUM> for Mg-H complexes to form.

After the passivated p-(Al,In)GaN layer is formed, Mg-H complexes can be removed by thermally annealing the p-(Al,In)GaN layer in a H<NUM>-free environment such as in an N<NUM> and/or O<NUM> environment. The annealing process breaks Mg-H bonds, removes H<NUM> from the p-(Al,In)GaN layer and results in a decreased resistivity. The process of conditioning a passivated p-(Al,In)GaN layer to decrease the resistivity is referred to as activating the p-(Al,In)GaN layer, and the resulting p-(Al,In)GaN layer is referred to as an activated p-(Al,In)GaN layer.

Re-exposing an activated p-(Al,In)GaN layer to a H<NUM> and NH<NUM> environment can cause Mg-H complexes to re-form and thus re-passivate the p-(Al,In)GaN layer.

In general, it is not possible to activate a passivated p-(Al,In)GaN layer after an overlying semiconductor layer such as an n-(Al,In)GaN layer has been deposited on the passivated p-(Al,In)GaN layer. Because H<NUM> cannot diffuse vertically through an overlying n-(Al,In)GaN layer, the buried p-(Al,In)GaN layer cannot be thermally activated when annealed at high temperatures in a H<NUM>-free environment.

To activate a buried passivated p-(Al,In)GaN layer, trenches can be etched into the semiconductor structure to expose the edges of the buried p-(Al,In)GaN layer to enhance the ability of H<NUM> to laterally diffuse and escape from the sidewalls of the trench during an annealing step.

Alternatively, activated p-(Al,In)GaN layers can be directly grown using certain semiconductor growth methods in which H<NUM> is not present during the growth process. For example, molecular beam epitaxy (MBE) in which the H<NUM> partial pressure is low, can be used to grow high-quality activated p-(Al,In)GaN layers. However, an activated p-(Al,In)GaN layer can become passivated when exposed to H<NUM> at high temperature, for example, when semiconductor layers are grown over the activated p-(Al,In)GaN layer at higher growth pressure. This can occur, for example, when an activated p-(Al,In)GaN layer is part of a semiconductor device and subsequently deposited semiconductor layers are grown using MOCVD, which employs H<NUM> and/or NH<NUM> as a carrier gas. For these reasons, it has not been possible to grow a semiconductor structure incorporating a buried activated p-(Al,In)GaN layer where the semiconductor layers immediately above the p-(Al,In)GaN layer are grown using metal organic chemical vapor deposition (MOCVD).

Although this can be achieved using RFMBE. and possibly NH<NUM> molecular beam epitaxy (MBE), using these growth methods is undesirable due to the complexities of ultra-high vacuum (UHV) and the difficulty in scaling.

Because semiconductors can be grown in a H<NUM>-free environment using RPCVD it should, in principle, be possible to overgrow an activated p-(Al,In)GaN layer using RPCVD without passivating the underlying activated p-(Al,In)GaN layer. However, it has been demonstrated that semiconductor layers grown in a predominantly H<NUM>-free environment using RPCVD including p-(Al,In)GaN and n-(Al,In)GaN layers exhibit inferior quality compared to those grown in the presence of H<NUM> and NH<NUM>, and consequently viable devices cannot be readily grown using RPCVD without using H<NUM> and NH<NUM>. It has also been shown that the levels of H<NUM> and NH<NUM> required during the growth of semiconductor layers by RPCVD to achieve high-quality layers are sufficient to passivate a previously activated p-(Al,In)GaN layer.

Therefore, although semiconductor layers overlying an activated p-(Al,In)GaN layer can be grown in a H<NUM>-free environment such as by using RPCVD and can be expected to retain the activation state of the p-(Al,In)GaN layer, the reduced quality of the overlying semiconductor layers due to the growth conditions will negatively affect device performance. In contrast, the quality of the overlying layers can be improved through the use of sufficient amounts H<NUM> and NH<NUM> during the RPCVD growth. However the levels of H<NUM> and NH<NUM> that are required to achieve the highest quality would then be expected to passivate any underlying p-(Al,In)GaN layers. It would therefore be expected that for any device comprising a buried p-(Al,In)GaN layer with overlying layers grown using an optimized RPCVD process, the buried p-(Al,In)GaN will not be fully activated.

<CIT> describes a method of fabricating a p-down light emitting diode (LED) structure comprises depositing a high crystal quality p type contact layer, depositing an active region on top of the p type contact layer, and depositing an n type contact layer on top of the active region using a hydride vapor phase epitaxy (HVPE) process. The high crystal quality p type contact layer is deposited at high temperature to ensure the high crystal quality of the p type film. Then type contact layer is formed on top of the active region in a HVPE chamber at a low temperature to prevent thermal damage to the quantum wells in the active region below the n type contact layer. The processing chamber used to form the p type contact layer is a separate processing chamber than the processing chamber used to form the n type contact layer.

It is desirable to have a semiconductor growth process in which semiconductor layers can be grown overlying an activated p-(Al,In)GaN layer in a high H<NUM> environment such as using MOCVD without passivating the underlying p-(Al,In)GaN layer and without having to undertake post-fabrication steps to re-activate the buried passivated p-(Al,In)GaN layer.

According to the present invention, there is disclosed a method of fabricating a semiconductor structure as recited in claim <NUM>.

Further aspects of the invention are specified by the dependent claims.

Also described herein are semiconductor devices that comprise a semiconductor structure fabricated by methods according to the present invention.

Also described herein are n/p-(Al,In)GaN tunnel junctions that comprise a semiconductor structure fabricated by methods according to the present invention.

Also described herein are semiconductor devices that comprise the tunnel junction according to the present invention.

The drawings described herein are for illustration purposes only. The drawings are not intended to limit the scope of the present disclosure.

For purposes of the following detailed description, it is to be understood that embodiments provided by the present disclosure may assume various alternative variations and step sequences, except where expressly specified to the contrary. Moreover, other than in any operating examples, or where otherwise indicated, all numbers expressing, for example, quantities of ingredients used in the specification and claims are to be understood as being modified in all instances by the term "about. " Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and attached claims are approximations that may vary depending upon the desired properties to be obtained by the present invention. At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the scope of the claims, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques.

Reference is now made to certain methods and semiconductor devices. The disclosed methods and semiconductor devices are not intended to be limiting of the claims.

Semiconductor structures including metal or metalloid-containing films, such as gallium nitride (GaN) films, have applications in a range of devices from light emitting diodes (LEDs) to ultraviolet detectors to transistor devices. These films have commonly been produced by techniques including molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD) and remote plasma-enhanced chemical vapor deposition (RPECVD or RPCVD).

MOCVD is a widely used process for the production of high-quality LEDs and the like, but MOCVD relies on high temperatures and the use of significant amounts of NH<NUM>. While this may not be particularly problematic for the growth of, for example, n-type GaN, it can create challenges when growing p-type layers, such as p-GaN, because the hydrogen present due to the pyrolysis of the NH<NUM> forms complexes with the acceptor dopants reducing the free carrier concentration and increasing the resistivity of the layer.

<FIG> shows a basic example of such a device, for example an LED <NUM>. The LED <NUM> comprises a substrate layer <NUM> which may be sapphire or other commonly used substrate material. There may be a buffer layer <NUM>, grown on the substrate layer <NUM>, to assist with achieving structural quality in the device by reducing defects in the epitaxial growth in moving away from the substrate layer <NUM>. The buffer layer <NUM> may, for example, be formed from GaN although AlGaN or other semiconductor material as appropriate, depending on the nature of the layers to be overgrown.

On top of the buffer layer <NUM> is an n-GaN layer <NUM> which may have been doped with silicon, for example. The n-GaN layer <NUM> would typically be grown under high temperature conditions using MOCVD.

The device <NUM> next has an active layer <NUM> formed by one or more InGaN layers. Active layer <NUM> may comprise a quantum well (QW) or may form a multiple quantum well (MQW) structure and is responsible for light generation.

In the example shown in <FIG>, the next layer is a p-GaN layer <NUM>. To achieve a p-type layer requires doping with an acceptor atom, such as magnesium. During growth of such a p-type layer <NUM>, using MOCVD, the epitaxial p-type layers will have hydrogen present within the structure due to the pyrolysis of the NH<NUM> and also the presence of H<NUM> typically used in the MOCVD process. Upon cooling of the device this hydrogen is known to bind to and passivate the magnesium atoms in the p-type layer. This prevents the magnesium atoms from acting as effective acceptor atoms and results in a highly resistive layer.

Various solutions have been proposed to deal with this issue, including thermal annealing, but while it is possible to at least temporarily re-activate the p-GaN layer the p-GaN will once again become passivated upon cooling, unless the environment can be kept hydrogen-free.

A particular challenge is created when a further semiconductor layer is grown on top of this p-type layer, such as an n-type layer, as shown in <FIG> as n-GaN layer <NUM>. When this layer is grown under MOCVD conditions, the p-GaN layer has a hydrogen content. Once the n-GaN layer <NUM> is complete and the device is cooled, this already present hydrogen will form a complex with the magnesium acceptor atoms, as discussed. The additional problem now is that the n-GaN layer <NUM> serves to effectively trap any hydrogen within the p-GaN layer <NUM> and therefore, even if the device is cooled under a hydrogen-free environment, the already trapped hydrogen cannot escape. While a subsequent high temperature treatment may dissociate the Mg-H complexes temporarily, because the hydrogen cannot escape vertically from the buried p-GaN layer <NUM>, the complexes will always reform upon cooling and therefore the device is inherently limited by the high resistivity of this buried p-GaN layer <NUM>.

One solution to this problem is proposed in <CIT> which suggests etching of the upper n-type layer. This results in a trench exposing sides of the p-type layer to the environment. This allows for the use of a subsequent annealing step to facilitate hydrogen migration out of the exposed sides of the p-type GaN layer. While this may achieve a local activation of the buried p-GaN layer between the trenches, it clearly does not solve the problem of protecting the buried p-GaN layer from further exposure to a hydrogen environment, which would allow hydrogen to enter the exposed sides of the p-type GaN layer. Therefore, precautions must be taken if such a structure is exposed to additional MOCVD growth conditions. It is also something of a compromise in that, while the resistivity of the p-type GaN layer may be lowered, a portion of the p-type GaN layer and the overgrown n-type layer need to be removed to fabricate the trench.

It is therefore desirable to provide an approach which allows for buried p-type GaN layers to be overgrown, particularly with immediately adjacent or subsequent n-type layers in a H<NUM> or NH<NUM> and H<NUM> environment, while in a substantially activated state.

In a first aspect, although it need not be the only or indeed the broadest form, the invention resides in a method for the growth of an n-type Group III nitride semiconductor layer over a p-type Group III nitride semiconductor layer, wherein the p-type Group III nitride semiconductor layer has been grown in a hydrogen environment, including the steps of: exposing the p-type Group III nitride semiconductor layer to a Group V plasma, a Group III reagent and an n-type dopant reagent; and allowing the n-type Group III nitride semiconductor layer to grow at a pressure of between <NUM> to <NUM> Torr to thereby grow an n-type Group III nitride semiconductor layer over a p-type Group III nitride semiconductor layer.

In embodiments, the p-type Group III nitride semiconductor layer grown in the hydrogen environment can be at least partially grown under MOCVD conditions. MOCVD, as previously discussed, involves growth in a hydrogen-rich environment and so results in hydrogen incorporation into the as-grown p-type layer. The p-type Group III nitride semiconductor layer can be grown in an atmosphere of NH<NUM> and/or a mixture of NH<NUM> and H<NUM>.

In embodiments wherein the p-type Group III nitride semiconductor layer comprises more than one individual p-type Group III nitride semiconductor layer, then at least one of those layers can be grown under MOCVD conditions. The majority of individual p-type Group III nitride semiconductor layers can be grown under MOCVD conditions. Substantially all of the individual p-type Group III nitride semiconductor layers can be grown under MOCVD conditions.

Alternatively, the p-type Group III nitride semiconductor layer grown in the hydrogen environment can be at least partially grown under RPCVD conditions.

In one embodiment, the method may further include the step of growing one or more additional semiconductor layers between the p-type Group III nitride semiconductor layer grown in the hydrogen environment and the n-type Group III nitride semiconductor layer grown over it. That is, the n-type Group III nitride semiconductor is not in direct abutment with or grown directly onto the surface of the p-type Group III nitride semiconductor layer grown in the hydrogen environment.

Each of the one or more additional semiconductor layers may independently be undoped, doped n-type, highly doped n-type, doped p-type or highly doped p-type semiconductor layers. In one embodiment, and as indicated above, an additional p-type Group III nitride semiconductor layer may be grown directly onto the p-type Group III nitride semiconductor layer or may be considered to be a continuation of that layer.

In embodiments, one or more of the additional semiconductor layers may form an active region. The active region may comprise a quantum well (QW) or multiple quantum wells (MQWs).

The Group III element of the p-type and n-type Group III nitride semiconductor layers, and any additional semiconductor layers, may be independently selected from one or more of gallium, indium and aluminum. The active region may be formed from semiconductor materials known to be useful as active regions for light generation, such as InGaN and InAlGaN.

In one embodiment, the p-type Group III nitride semiconductor layer is p-GaN.

In another embodiment, the n-type Group III nitride semiconductor layer is n-GaN.

In embodiments, the Group V plasma is a nitrogen plasma.

Suitably, the Group III reagent is a Group III metal organic reagent.

The Group III metal organic reagent can be a Group III metal alkyl reagent.

The Group III metal alkyl reagent can be selected from the group consisting of trimethylgallium, triethylgallium, trimethylindium and trimethylaluminum.

In certain embodiments, the n-type dopant of any n-type layer within the semiconductor structure formed by the method of the first aspect comprises one or more of silicon, germanium or oxygen. Suitable reagents that contain certain of these elements include silane, disilane, di-tert-butylsilane and molecular oxygen. The n-type dopant can be silicon.

In embodiments, the p-type dopant of any p-type layer within the semiconductor structure formed by the method comprises one or more of magnesium or zinc. Suitable reagents that contain these elements, such as diethyl zinc (DEZn) and bis(cyclopentadienyl)magnesium (Cp<NUM>Mg), can be selected from those known in the art for p-type doping. The p-type dopant can be magnesium.

In certain embodiments, the n-type Group III nitride semiconductor layer may be grown immediately on top of and in contact with the p-type Group III nitride semiconductor layer which is grown in the hydrogen-rich environment.

In embodiments, the method may result in the formation of a tunnel junction. The tunnel junction may simply be formed by the n-type Group III nitride semiconductor layer and p-type Group III nitride semiconductor layer interface or each of these layers may itself be formed from two or more individual layers and one or more of these layers may be a highly doped semiconductor layer. That is, in one embodiment, the junction of the n-type Group III nitride semiconductor layer and p-type Group III nitride semiconductor layer may be an interaction between a highly doped n-type Group III nitride semiconductor layer and a highly doped p-type Group III nitride semiconductor layer. Any of the highly doped p-type or n-type layers described herein may be defined as having atomic dopant concentrations greater than 5E19/cm<NUM>.

The exposing of the p-type Group III nitride semiconductor layer to the Group V plasma, Group III reagent and n-type dopant reagent is an exposure to RPCVD growth conditions. That is, the p-type Group III nitride semiconductor layer is exposed to a Group V plasma which is provided by a remote plasma source. Such plasma sources are well known in the art.

Suitably, the RPCVD conditions for overgrowth of the n-type layer can include NH<NUM> and/or H<NUM>. It has been found that suitable RPCVD growth can be achieved with NH<NUM> and/or H<NUM> and passivation of the p-type layer avoided. In certain embodiments, the RPCVD conditions include substantially no H<NUM> in the growth chamber. While MOCVD growth may potentially be performed with relatively low levels of hydrogen, the presence of ammonia is required which is pyrolyzed to thereby generate hydrogen and a variety of radical species. It is the combination of the presence of plasma and relatively low overpressure of NH<NUM> and/or H<NUM> which provide the present benefits of RPCVD n-type layer overgrowth. Therefore, in certain embodiments, the RPCVD conditions for n-type layer overgrowth include substantially no NH<NUM> in the growth chamber.

The RPCVD growth procedures may be carried out using the processes, conditions and apparatus as generally described in any one or more embodiments of the applicant's earlier international publication, <CIT>.

In general terms, the RPCVD apparatus will comprise a growth chamber inside which semiconductor layer growth will occur. Located within the growth chamber is a substrate which is supported by a substrate holder which may include or be connected to a heater to allow the substrate to be adjusted to growth temperatures. The substrate may comprise sapphire, SiC, silica, soda lime glass, borosilicate glass, Pyrex®, silicon, glass, synthetic sapphire, quartz, zinc oxide, nitride coated substrates and other materials as are well known in the art including free standing bulk semiconductor substrates and nitride templates. A plasma inlet, located at a distance from the substrate, allows for entry of the Group V plasma formed in, for example, a high frequency generator, into the growth chamber. The high frequency generator acts on a region of the apparatus receiving nitrogen from a nitrogen source. A Group III reagent source, which is usually also at a distance from the substrate, introduces the metal organic into a flow path which delivers the reagent to a metal organic injector for dispersion into the growth chamber.

The plasma enters an area of the growth chamber directly above the metal organic injector and so, in operation, the plasma containing active neutral nitrogen species and the metal organic reagent mix and react to form the particular metal nitride, such as gallium nitride, which is deposited on the substrate to form the film. Doping reagents can be introduced in a similar manner. Excess reagents, carrier gases, contaminants etc. are removed via a waste outlet.

In one embodiment, the method further includes the step of growing the p-type Group III nitride semiconductor layer under MOCVD conditions, as described above and as will be generally known in the art. In this embodiment, the MOCVD growth of the p-type Group III nitride semiconductor layer and the RPCVD growth of the n-type Group III nitride semiconductor layer occur in the same growth chamber. This is created by the same hybrid apparatus being switched between an MOCVD relatively high pressure, high temperature growth mode in the presence of NH<NUM> and H<NUM> and an RPCVD comparatively low pressure and low temperature. The RPCVD apparatus may be generally arranged as already described but with simple modifications to allow switching to a high pressure environment and with appropriate gas supply. It has been found that the use of a hybrid apparatus which can be alternately run in MOCVD and RPCVD modes provides significant advantages in operation.

For example, hybrid growth enables an MOCVD to RPCVD transition in situ and without cooling of the substrate. This can improve the quality of the transition interface. Typically a structure grown using two such techniques will contain a re-growth interface. This interface will often have impurities or contaminants that form on the first layer during the transfer from the environment of the first process to that of the second process and thereby remain buried by the second layer. Therefore, a clean transition between two processes at a critical interface, such as a tunnel junction interface for example, may be difficult to achieve unless the two processes are truly hybrid and can be run in the same reactor with only nominal changes to process parameters, such as pressure. Additionally, such a hybrid approach also provides for growth at high temperatures in NH<NUM> and H<NUM>, where appropriate such as during MOCVD growth, and growth at low temperatures with low flows of H<NUM> or NH<NUM> where required, such as with RPCVD growth.

Therefore, in one embodiment, the hybrid growth requires only a change in certain process parameters and not a change in physical location of the substrate/growing film between the first growth process and second growth process. That is, the growth of all of the layers of the semiconductor device may occur in the same chamber. The parameters which may be changed include pressure, temperature and NH<NUM> and/or H<NUM> concentrations and or flow rates per growth chamber volume.

In one embodiment, neither the p-type Group III nitride semiconductor layer nor the n-type Group III nitride semiconductor layers are grown by molecular beam epitaxy (MBE). Preferably, none of the semiconductor layers of the semiconductor structure formed by the first aspect are grown by MBE. While MBE may be used to attempt to avoid forming a buried and passivated p-type layer, the process has a number of significant commercial drawbacks. Particularly, the throughput rate in MBE is relatively low which more or less precludes extensive commercial use in semiconductor device formation. The ultra-high vacuum conditions greatly increase costs and require significant preparation and maintenance time. The process growth window for nitrides is also narrower than growth using RPCVD. Further, MBE will not provide all of the advantages, discussed below, which RPCVD growth can provide.

As will be clear from the discussion herein, the n-type overgrown semiconductor layer of the first aspect is not grown under MOCVD or HVPE or related relatively high temperature and high H<NUM>/NH<NUM> environment processes.

The one or more additional semiconductor layers grown between the p-type Group III nitride semiconductor layer grown in the hydrogen environment and the n-type Group III nitride semiconductor layer may be grown under MOCVD or RPCVD conditions. In one embodiment, it may be desirable to firstly overgrow an additional p-type Group III nitride semiconductor layer on top of the p-type Group III nitride semiconductor layer, as was discussed above, but to do so under RPCVD conditions. This approach can provide a number of advantages including the ability to grow a highly doped p-type layer at low temperatures and potentially achieving a lower resistivity p-type layer at those temperatures than can be achieved using MOCVD.

The method may further include the step of controlling the temperature in the growth chamber, during RPCVD growth, to be between about <NUM> to about <NUM>,<NUM>, about <NUM> to about <NUM>,<NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>,<NUM>; or between about <NUM> to <NUM>, about <NUM> to <NUM>, about <NUM> to <NUM>, about <NUM> to about <NUM>, or even between about <NUM> to <NUM>, about <NUM> to <NUM>, about <NUM> to <NUM> or about <NUM> to <NUM>. The broader temperature ranges are inclusive of a temperature of about <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. A growth temperature range can be between about <NUM> to about <NUM>.

The use of RPCVD conditions for the growth of at least the n-type Group III semiconductor layer provides for significant advantages in operation, many of which can be linked to growth at lower temperatures compared with MOCVD. Growth at lower temperature may prevent damage, or limit diffusion, to previously deposited layers such as indium-rich quantum wells forming active layers in the case of LEDs and solar cells. RPCVD can be used to produce better film quality than MOCVD films grown at the same temperature, with lower background impurities and in particular lower levels of carbon. Further, the lower temperature growth of RPCVD can reduce the back diffusion of Mg from existing p-GaN layers into the layers beneath. For example, it may prevent Mg diffusion from p-GaN layers into multi-quantum well (MQW) layers which may be located below. This can result in improvements in internal quantum efficiency (IQE) due to less defect-related carrier transport from less Mg diffusion into the MQWs. Similarly, lower growth temperatures will prevent the forward diffusion of Mg from the as-grown p-GaN layer up into the next layer being grown. For example, in the case of a tunnel junction, preventing the Mg diffusing upwards from a p-GaN layer into the highly-doped n-GaN layer above. This creates a sharp n-p junction that will minimize the depletion width and maximize the tunneling probability, thus reducing the voltage drop across the tunnel junction and increasing the semiconductor device efficiency.

The use of RPCVD conditions also results in usefully high carrier concentrations in the semiconductor layers. It can be difficult to achieve high carrier concentration with low resistivity at the low growth temperatures which are required for overgrowing on indium-rich MQWs. For p-GaN growth, for example, growth temperature and Mg levels both contribute to the degree of diffusion and so the higher the doping concentration the lower the growth temperature required to prevent diffusion. RPCVD growth conditions can deliver this combination of low growth temperature with high carrier concentration and provide semiconductor layer interfaces sharp enough to achieve low tunneling resistance. This may be extremely advantageous in a range of applications such as for LEDs, solar cells, HEMT and the like.

It is a further advantage of the use of an overgrowth step to grow an n-type Group III nitride semiconductor layer under RPCVD conditions such that a separate dedicated activation step, such as exposing the layer to a H<NUM> free or low H<NUM> environment at high temperature, as is often employed in MOCVD growth alone, is unnecessary. The temperatures employed in the RPCVD cleaning and chamber preparation are sufficient to activate the p-type GaN layer and/or keep the p-type GaN layer activated prior to overgrowth of the n-type Group II nitride semiconductor layer.

The method may further include the step of controlling the pressure in the growth chamber, during RPCVD growth of the overgrown n-type layer, to be between about <NUM> Torr to <NUM> Torr, between about <NUM> Torr to <NUM> Torr, more between about <NUM> Torr to <NUM> Torr, even more y between about <NUM> Torr to <NUM> Torr or <NUM> Torr to <NUM> Torr. In embodiments, the pressure in the growth chamber, during RPCVD growth of the overgrown n-type layer, may be between about <NUM> Torr to <NUM> Torr, between about <NUM> Torr to <NUM> Torr, more between about <NUM> Torr to <NUM> Torr, even more between about <NUM> Torr to <NUM> Torr or <NUM> Torr to <NUM> Torr. Typical growth pressures are between about <NUM> Torr to about <NUM> Torr.

In one embodiment, one or more further semiconductor layers may be grown on top of the n-type Group III nitride semiconductor layer in an MOCVD growth environment. The further layers are can be Group III nitride semiconductor layers. This ability stems from the fact, previously discussed, that once the p-type Group III nitride semiconductor layer has been overgrown by the n-type Group III nitride semiconductor layer and left in an activated state, then further growth in a hydrogen-rich environment cannot passivate this buried layer. It is therefore possible, for example, to grow an LED in MOCVD conditions and then grow a tunnel junction on top of this, using RPCVD conditions according to the method of the first aspect, and then grow a further LED structure on top of this tunnel junction. This can be repeated, as desired, to generate a multi-junction device. Advantageously, this MOCVD-RPCVD-MOCVD repetitive growth cycle can all be performed in the one growth chamber when using a hybrid apparatus, as discussed above. Electrical contacts and the like can be added to the device by methods commonly known in the art to thereby form the final semiconductor device. It may be advantageous to end the growth of semiconductor layers with an n-type layer, optionally grown under RPCVD conditions, as an n-type layer has a higher conductivity and is therefore beneficial to attach a metal contact to as an effective current spreading layer. Additionally, it is also more straightforward to form an ohmic contact to an n-type GaN layer than to a p-type GaN layer. An ohmic contact is the desired contact that is made between the semiconductor and a metal and is required to form semiconductor devices.

In one embodiment, the method of the first aspect does not require an etching step to activate a buried p-type semiconductor layer.

Reference will now be made to a number of examples of semiconductor structures which can be made using the method of the first aspect. <FIG> are schematic representations of a number of representative semiconductor structures which may be formed according to the method of the first aspect. It will be understood that these structures merely assist with understanding the invention and are not limiting upon the scope thereof. In these embodiments, the substrate and buffer layers may be selected from those materials previously discussed as suitable for such layers. In all embodiments, the buffer layer may be optional.

<FIG> shows an embodiment of a semiconductor structure <NUM> analogous to that of <FIG>. Again, additional semiconductor layers <NUM> have been grown in between the n-GaN layer <NUM> and p-GaN layer <NUM>. In the embodiment shown, the additional semiconductor layers <NUM> represent an active layer formed by one or more InGaN layers <NUM>. Layer <NUM> may comprise a QW or may form an MQW structure. In forming this structure, the substrate <NUM> may have a buffer layer, for example a GaN layer <NUM>, grown under MOCVD conditions on top of the substrate <NUM>. An n-GaN layer <NUM> has been overgrown on the buffer layer <NUM>, again in MOCVD mode. The InGaN layer <NUM> can then be grown on top of this using MOCVD to form a high quality active layer followed by growth a further p-GaN layer <NUM> which, if grown under MOCVD conditions will be passivated as discussed above. At this point, the apparatus can be switched to RPCVD growth conditions for overgrowth of the final n-GaN layer <NUM>. In this manner a relatively simple LED or solar cell structure can be formed which results in an activated buried p-GaN layer <NUM> with an n-GaN overgrowth layer <NUM>, grown by RPCVD, to prevent hydrogen ingress into the buried p-GaN layer <NUM>.

<FIG> shows an embodiment of a semiconductor structure <NUM> which closely corresponds to structure <NUM> of <FIG> but with an additional p-type layer <NUM> which is grown under low or no hydrogen RPCVD conditions. As was discussed previously, any semiconductor layer described herein may, in fact, be constructed from multiple layers. In <FIG> the p-GaN layer <NUM> of <FIG> can be considered to have been divided into two layers. However, the layers are grown under different conditions to provide the benefits of the present approach. The substrate <NUM>, buffer layer <NUM>, n-GaN layer <NUM>, InGaN active layer <NUM> and p-GaN layer <NUM> correspond with those layers in <FIG> and n-GaN layer <NUM>, InGaN active layer <NUM> and p-GaN layer <NUM> may be grown in MOCVD mode or other hydrogen rich growth environment. For example, in an alternative embodiment, p-GaN layer <NUM> may be grown by RPCVD but subjected to a hydrogen rich growth environment. In any event, at this point p-GaN layer <NUM> is grown under RPCVD low hydrogen conditions. The exposure to RPCVD plasma conditions for the growth of p-GaN layer <NUM> causes activation of the underlying MOCVD or other hydrogen-rich environment grown p-GaN layer <NUM>. The final n-GaN layer <NUM> is then overgrown over both of these p-type layers to cap them and maintain their activated state through any further processing or growth the structure <NUM> may be subjected to.

<FIG> shows an embodiment of a semiconductor structure <NUM> which generally corresponds to <FIG> but with an additional semiconductor layer <NUM> in the form of a highly doped p+-GaN layer <NUM>. The p+-GaN layer <NUM> may be grown under RPCVD low hydrogen conditions to provide a thin p-type layer on which to overgrow the subsequent active layers <NUM> and the final capping n-GaN layer <NUM>. The buffer layer <NUM>, the n-GaN layer <NUM> and the p-GaN layer <NUM> are grown on the substrate <NUM>, under MOCVD conditions, as discussed for <FIG>.

<FIG> shows an embodiment of a semiconductor structure <NUM> wherein an n-GaN layer <NUM> and a p-GaN layer <NUM> are grown on a substrate <NUM>, all under MOCVD conditions. The hybrid apparatus can then be switched to RPCVD growth conditions for growth of a highly doped p+-GaN layer <NUM>. The use of RPCVD conditions allows for higher doping levels and a lower resistivity to be achieved than if the layer had been grown at the same temperature using MOCVD conditions. A highly doped n+-GaN layer <NUM> is then grown under RPCVD conditions to thereby form a tunnel junction on top of the lower MOCVD grown n-GaN layer <NUM> and p-GaN layer <NUM>. Finally, the uppermost n-GaN layer <NUM> is grown under RPCVD growth conditions to again leave a buried MOCVD-grown p-GaN layer <NUM> with an overgrown n-GaN layer <NUM> (and doped n+-GaN layer <NUM>). The uppermost n-GaN layer <NUM> also provides for a useful uniform current spreading and carrier injection layer. As with all of the embodiments shown herein, the standard metal contacts have not been shown.

<FIG> shows an embodiment of a semiconductor structure <NUM> which is essentially identical to the structure <NUM> in <FIG> but with an active layer <NUM>, grown under MOCVD conditions, located between the MOCVD-grown n-GaN layer <NUM> and p-GaN layer <NUM>. As for <FIG>, in the embodiment shown, the active layer <NUM> is formed by one or more InGaN layers which may comprise single or multiple QWs. The remaining highly doped p+-GaN layer <NUM>, highly doped n+-GaN layer <NUM> and the uppermost n-GaN layer <NUM> are all grown under RPCVD growth conditions. This results in a simple LED type structure, having been grown under MOCVD conditions and therefore presenting high quality layers <NUM>, <NUM> and <NUM>, with a tunnel junction (formed from layers <NUM> and <NUM>) on top and the final n-GaN layer <NUM> to provide for a semiconductor structure having a buried activated p-GaN layer <NUM>. The use of RPCVD conditions, as previously discussed, is highly beneficial in terms of employing a relatively low growth temperature to prevent damage to the already grown indium-containing active layer <NUM>.

<FIG> indicates how the structures exemplified previously can be built into multi-junction devices. Semiconductor structure <NUM> resembles the structure <NUM> of <FIG> with layers <NUM>-<NUM> being identical. In addition to those of structure <NUM>, however, a further active layer <NUM> has been grown on top of the RPCVD-grown n-GaN layer <NUM>. This active layer <NUM> may be formed from any active semiconductor material but, in the embodiment shown is InGaN and may comprise QW or MQW structures as for active layer <NUM>. The hybrid apparatus can advantageously be switched back to MOCVD mode for the growth of the active layer <NUM>. This will not negatively impact upon the activation of the buried p-GaN layer <NUM> due to the capping n-GaN layer <NUM>. The active layer <NUM> and an adjacent p-GaN layer <NUM> can therefore be grown under MOCVD conditions, if desired. Another tunnel junction, comprising a highly doped p+-GaN layer <NUM> and a highly doped n+-GaN layer <NUM>, can then be grown under RPCVD growth conditions on top of the p-GaN layer <NUM> with a final RPCVD grown n-GaN layer <NUM> grown as the uppermost layer. This provides for a semiconductor structure <NUM> having two active regions, two tunnel junctions and two buried, but activated, MOCVD grown p-GaN layers. This provides for a device demonstrating useful efficiency when employed within a solar cell or other optoelectronic device. The semiconductor structure <NUM> shown in <FIG> includes substrate <NUM>, n-GaN layer <NUM>, InGaN layer <NUM>, p-GaN layer <NUM>, p+-GaN layer <NUM>, n+-GaN layer <NUM>, n-GaN layer <NUM>, InGaN layer <NUM>, p-GaN layer <NUM>, p+-GaN layer <NUM>, n+-GaN layer <NUM>, and n-GaN layer <NUM>.

It will be appreciated that while the layers of the semiconductor structures shown in <FIG>, and other structures described herein, are generally discussed as discrete layers, in practice they may be constructed from a number of individual layers of the same or different Group III nitride composition. For example, the MOCVD-grown p-type or n-type layers may be formed from any number of individual layers which, while all being p- or n-type, may have varying Group III nitride compositions.

In one embodiment, the method may further include the step of growing, under MOCVD conditions, a thin p-type Group III nitride semiconductor layer on top of an existing Group III nitride semiconductor layer prior to growing the immediately adjacent semiconductor layer under RPCVD conditions. This can be looked at as the forming of a seed layer, under MOCVD conditions, prior to subsequent RPCVD growth which may have advantages in operation.

Without wishing to be bound by any particular theory, it is postulated that the overgrown RPCVD will mimic the crystal that it is grown on. If the underlying crystal is a high quality MOCVD-grown GaN layer, then RPCVD may continue the growth with equal quality. As previously mentioned, the regrowth interface will often contain impurities or contaminants and this may prevent the continuation of quality between the two differently grown layers. By starting the growth using MOCVD conditions, the regrowth interface is buried using MOCVD conditions and the transition from MOCVD to RPCVD is then performed in situ in a single reactor thereby improving the coherency between the two processes.

Alternatively, in between any MOCVD grown p-type Group III nitride semiconductor layer and a subsequent RPCVD grown highly doped p+-type Group III nitride layer the method may include the step of growing an additional thin RPCVD grown p-type Group III nitride semiconductor layer directly on top of the MOCVD grown p-type Group III nitride semiconductor layer. The further RPCVD grown layers can then be grown on top of this thin layer.

In a second aspect, the invention resides in a semiconductor structure made by the method of the first aspect.

The details of the structure and the various conditions for growth are as already described for the first aspect.

In a third aspect, the invention resides in the use of a semiconductor structure of the second aspect in a semiconductor device. The semiconductor device may be any already known in the art to require the use of semiconductor structures, as have been described herein. Common examples as LEDs, solar cells, HEMTs and other transistors, laser diodes, vertical cavity surface emitting lasers and the like.

By exposing a p-(Al,In)GaN layer to a composition comprising NH<NUM> and H<NUM> before growing overlying semiconductor layers, a semiconductor tunnel junction structure with a lower resistance can be grown.

A method of fabricating a semiconductor structure comprising a buried activated p-(Al,In)GaN layer comprises providing a p-(Al,In)GaN layer, treating the p-(Al,In)GaN layer with a gaseous composition, and growing one or more semiconductor layers overlying the treated p-(Al,In)GaN layer, to provide a buried activated p-(Al,In)GaN layer.

Methods of fabricating a semiconductor structure comprising a buried activated p-(Al,In)GaN layer can comprise (a) exposing a magnesium-doped p-(Al,In)GaN layer to H<NUM>, NH<NUM>, or both H<NUM> and NH<NUM>, wherein a partial pressure of H<NUM> is less than <NUM> Torr, to provide an exposed magnesium-doped p-(Al,In)GaN layer; and (b) growing an n-(Al,In)GaN layer on the exposed magnesium-doped p-(Al,In)GaN layer in an environment comprising H<NUM>, NH<NUM>, or both H<NUM> and NH<NUM>, to provide a semiconductor structure comprising a buried activated p-(Al,In)GaN layer.

Methods of fabricating a semiconductor structure can comprising a buried activated p-(Al,In)GaN layer, can comprise: (a) exposing a magnesium-doped p-(Al,In)GaN layer to a gaseous mixture comprising H<NUM>, NH<NUM>, or a combination thereof, wherein a partial pressure of H<NUM> is less than <NUM> Torr, to provide an exposed magnesium-doped p-(Al,In)GaN layer; and (b) growing an n-(Al,In)GaN layer on the exposed magnesium-doped p-(Al,In)GaN layer in an environment comprising H<NUM>, NH<NUM>, or a combination thereof, to provide a semiconductor structure comprising a buried activated p-(Al,In)GaN layer. The methods can consist of steps (a) and (b). In step (a) the gaseous mixture may not comprise N<NUM>.

After step (a) the temperature can be reduced to within a range from <NUM> to <NUM>,<NUM> while maintaining the partial pressure of H<NUM> within a range from <NUM> Torr to <NUM> Torr.

In step (b) growing the n-(Al,In)GaN layer can comprise growing an n-(Al,In)GaN layer on the exposed magnesium-doped p-(Al,In)GaN layer by RPCVD in an environment wherein the partial pressure of H<NUM> can be greater than the partial pressure of N<NUM>.

In step (b) growing the n-(Al,In)GaN layer can consist of growing an n-(Al,In)GaN layer on the exposed magnesium-doped p-(Al,In)GaN layer by RPCVD in an environment wherein the partial pressure of H<NUM> can be greater than the partial pressure of N<NUM>.

In step (b) growing the n-(Al,In)GaN layer can comprise (i) growing a first n-(Al,In)GaN layer on the exposed magnesium-doped p-(Al,In)GaN layer by RPCVD in an environment, wherein the partial pressure of N<NUM> is greater than the partial pressure of H<NUM>; and (ii) growing a second n-(Al,In)GaN layer on the first n-(Al,In)GaN layer by RPCVD in an environment wherein the partial pressure of H<NUM> is greater than the partial pressure of N<NUM>. In step (b) growing the n-(Al,In)GaN layer can consist of step (i) and step (ii).

The thickness of the first n-(Al,In)GaN layer can be, for example, less than <NUM>, less than <NUM>, less than <NUM>, less than <NUM>, or less than <NUM>. The thickness of the second n-(Al,In)GaN layer can be, for example, greater than <NUM>, greater than <NUM>, or greater than <NUM>.

In step (i) growing the first n-(Al,In)GaN layer can comprise growing at a pressure, for example, from <NUM> Torr to <NUM> Torr and a temperature from <NUM> to <NUM>,<NUM>.

In step (ii) growing the second n-(Al,In)GaN layer can comprise growing in the presence of H<NUM> and NH<NUM> at a pressure, for example, from <NUM> Torr to <NUM> Torr and a temperature from <NUM> to <NUM>,<NUM>.

A p-(Al,In)GaN layer can comprise p-GaN, p-AlGaN, p-InGaN, or p-AlInGaN. The p-(Al,In)GaN layer can have a concentration of a p-type dopant such as Mg or Zn, within a range, for examples, from 1E19 cm-<NUM> to 5E21 cm-<NUM>, from 5E19 cm-<NUM> to 1E21 cm-<NUM>, or from 1E20 cm-<NUM> to 5E20 cm-<NUM>. The p-type dopant can be magnesium and the p-(Al,In)GaN layer can be a magnesium-doped p-(Al,In)GaN layer such as a magnesium-doped p-GaN layer. A p-(Al,In)GaN layer can comprise two or more p-(Al,In)GaN layers, with each layer having a different composition, a different concentration of a p-type dopant, and/or a different p-type dopant concentration.

A p-(Al,In)GaN layer can comprise one or more p-(Al,In)GaN layers. When a p-(Al,In)GaN layer comprises two or more p-(Al,In)GaN layers each of the p-(Al,In)GaN layers can be grown under different conditions, such as a different gaseous composition, a different pressure, different partial pressures of gases, different wafer/carrier temperatures, and/or different durations. For example, a p-(Al,In)GaN layer can comprise a first layer having a first p-type dopant concentration, and a second layer having a higher p-type dopant concentration, such as a p++-(Al,In)GaN layer.

A p-(Al,In)GaN layer can be grown on a substrate using any suitable deposition method such as by MBE, MOCVD, or RPCVD. The substrate may be an active substrate such as a top surface of an optoelectronic structure. The p-(Al,In)GaN layer can be grown in the presence of H<NUM> and/or NH<NUM> and/or can be exposed to H<NUM> and/or NH<NUM> such that the p-(Al,In)GaN layer is passivated. The substrate can be any suitable material.

A p-(Al,In)GaN layer can be an activated p-(Al,In)GaN layer, can be a fully activated p-(Al,In)GaN layer, can be a partially activated p-(Al,In)GaN layer, can be an at least partially activated p-(Al,In)GaN layer, or can be a passivated p-(Al,In)GaN layer.

The p-(Al,In)GaN layer can be exposed to a gaseous composition comprising H<NUM> and NH<NUM>. The ratio of the H<NUM> flow rate to the NH<NUM> flow rate in a chamber can be, for examples, from <NUM>:<NUM> to <NUM>:<NUM>, from <NUM>:<NUM> to <NUM>:<NUM>, from <NUM>:<NUM> to <NUM>:<NUM> or from <NUM>:<NUM> to <NUM>:<NUM>. The pressure in the exposure chamber can be, for example, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, or from <NUM> Torr to <NUM> Torr. For example, the chamber pressure can be up to <NUM> Torr, up to <NUM> Torr, up to <NUM> Torr, up to <NUM> Torr, or up to <NUM> Torr. The exposure temperature can be, for example, greater than <NUM>, greater than <NUM>, greater than <NUM>, greater than <NUM>, greater than <NUM>, greater than <NUM>. greater than <NUM>, greater than <NUM>, greater than <NUM> or greater than <NUM>. For example, the exposure temperature can be from <NUM> to <NUM>, from <NUM> to <NUM>, from <NUM> to <NUM>, from <NUM> to <NUM>,<NUM>, from <NUM> to <NUM>,<NUM>, or from <NUM> to <NUM>,<NUM>. The exposure can be, for example, less than <NUM> minutes, less than <NUM> minutes, less than <NUM> minutes, or less than <NUM> minute. For example, the exposure can be from <NUM> minutes to <NUM> minutes, from <NUM> minute to <NUM> minutes or from <NUM> minute to <NUM> minutes.

For example, the p-(Al,In)GaN layer can be exposed to a gaseous composition comprising H<NUM> and NH<NUM>, wherein the ratio of the H<NUM> flow rate to the NH<NUM> flow rate can be from <NUM>:<NUM> to <NUM>:<NUM>, the chamber pressure can be from <NUM> Torr to <NUM> Torr, and the exposure temperature can be greater than <NUM> such as from <NUM> to <NUM>, or from <NUM> to <NUM>. For example, the p-(Al,In)GaN layer can be exposed to a gaseous composition comprising H<NUM> and NH<NUM>, wherein the ratio of the H<NUM> flow rate to the NH<NUM> flow rate can be from <NUM>:<NUM> to <NUM>:<NUM>, the chamber pressure can be, for example, from <NUM> Torr to <NUM> Torr, and the exposure temperature can be greater than <NUM> such as from <NUM> to <NUM>,<NUM>. For example, the magnesium-doped p-(Al,In)GaN layer can be exposed to a partial pressure of H<NUM> less than <NUM> Torr and to a temperature less than <NUM>.

During exposure, the partial pressure of H<NUM> can be, for example, less than <NUM> Torr, less than <NUM> Torr, less than <NUM> Torr, less than <NUM> Torr, less than <NUM> Torr or less than <NUM> Torr. During exposure, the partial pressure of H<NUM> can be, for example, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, or from <NUM> Torr to <NUM> Torr.

The exposure at these conditions can be, for example, greater than <NUM> sec, greater than <NUM> sec, greater than <NUM> sec, or greater than <NUM> sec. The exposure at these conditions can be, for example, from <NUM> sec to <NUM> sec, from <NUM> sec to <NUM> sec, or from <NUM> sec to <NUM> sec. The exposure can be, for example, less than <NUM> minutes, less than <NUM> minutes, less than <NUM> minutes, less than <NUM> minutes, less than <NUM> minutes, or less than <NUM> minute.

After the surface of the p-(Al,In)GaN layer is exposed to the H<NUM> and NH<NUM> environment at modest pressures and elevated temperatures, the temperature of the p-(Al,In)GaN layer can be decreased to a temperature, for example, less than <NUM>,<NUM>, less than <NUM>, less than <NUM>, less than <NUM>, less than <NUM>, or less than <NUM>. For example, the temperature can be reduced to from <NUM> to <NUM>, from <NUM> to <NUM>, from <NUM> to <NUM>, from <NUM> to <NUM>, or from <NUM> to <NUM>. The temperature can be reduced to a typical RPCVD growth temperature such as from <NUM> to <NUM>.

The temperature can be reduced from the NH<NUM>:H<NUM>-exposure temperature within, for example, less than <NUM>, less than <NUM>, less than <NUM>, less than <NUM>, or less than <NUM>.

While the substrate/wafer is cooling, the p-(Al,In)GaN layer can be exposed to H<NUM> and NH<NUM> with the relative flow ratio and chamber pressures as in the NH<NUM>:H<NUM>-exposure step. For example, while the substrate/wafer is cooling the ratio of the H<NUM> flow rate to the NH<NUM> flow rate can be from <NUM>:<NUM> to <NUM>:<NUM>, and the chamber pressure can be from <NUM> Torr to <NUM> Torr. For example, while the substrate/wafer is cooling the ratio of the H<NUM> flow rate to the NH<NUM> flow rate can be from <NUM>:<NUM> to <NUM>:<NUM>, and the chamber pressure can be from <NUM> Torr to <NUM> Torr.

While the temperature of the p-Al,In)GaN layer is reduced, the partial pressure of H<NUM> can be, for example, less than <NUM> Torr, less than <NUM> Torr, less than <NUM> Torr, less than <NUM> Torr, less than <NUM> Torr, less than <NUM> Torr, less than <NUM> Torr or less than <NUM> Torr. During exposure, the partial pressure of H<NUM> can be, for example, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, or from <NUM> Torr to <NUM> Torr.

The cooled, NH<NUM>:H<NUM>-exposed p-(Al,In)GaN layer can then be exposed to a N<NUM> plasma at a chamber pressure, for example, from <NUM> Torr to <NUM> Torr, such as from <NUM> Torr to <NUM> Torr, in a H<NUM> and/or NH<NUM> environment. The duration of the N<NUM> plasma exposure can be, for example, greater than <NUM> sec, greater than <NUM> sec, greater than <NUM> sec, or greater than <NUM> sec. The duration of N<NUM> plasma exposure can be, for example, from <NUM> sec to <NUM> sec, from <NUM> sec to <NUM> sec, from <NUM> sec to <NUM> sec, or from <NUM> sec to <NUM> sec. The chamber pressure during the N<NUM> plasma exposure can be, for example, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, or from <NUM> Torr to <NUM> Torr.

After the temperature is reduced, an n-(Al,In)GaN layer can be grown on the exposed p-(Al,In)GaN layer. The n-(Al,In)GaN layer is grown in an environment comprising H<NUM>, NH<NUM>, or both H<NUM> and NH<NUM>.

The n-(Al,In)GaN layer is grown in an environment in which the partial pressure of H<NUM> is less than <NUM> Torr, for example less than <NUM> Torr, less than <NUM> Torr, less than <NUM> Torr, or less than <NUM> Torr. The n-(Al,In)GaN layer is emrbegrown in an environment in which the partial pressure of H<NUM> is from <NUM> Torr to <NUM> Torr, for example from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, or from <NUM> Torr to <NUM> Torr.

Growing a n-(Al,In)GaN layer can comprise (i) growing a first n-(Al,In)GaN layer; and (ii) growing a second n-(Al,In)GaN layer overlying the first n-(Al,In)GaN layer. Growing an n-(Al,In)GaN layer can comprise (i) growing a first n-(Al,In)GaN layer in an environment wherein a partial pressure of H<NUM> is from <NUM> Torr to <NUM> Torr; and (ii) growing a second n-(Al,In)GaN layer overlying the first n-(Al,In)GaN layer in an environment wherein the partial pressure of H<NUM> is greater than <NUM> Torr.

The first n-(Al,In)GaN layer can have a thickness, for example, less than <NUM>, less than <NUM>, less than <NUM>, less than <NUM>, less than <NUM>, less than <NUM>, or less than <NUM>. The first n-(Al,In)GaN layer can have a thickness, for example, from <NUM> to <NUM>, from <NUM> to <NUM>, from <NUM> to <NUM>, from <NUM> to <NUM>, or from <NUM> to <NUM>. The first n-(Al,In)GaN layer can be deposited at a partial pressure of N<NUM>, for example, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, or from <NUM> Torr to <NUM> Torr. The n-(Al,In)GaN layer growth temperature can be, for example, less than <NUM>,<NUM>, less than <NUM>, less than <NUM>, less than <NUM>, less than <NUM>, or less than <NUM>. For example, the temperature for growing the first n-(Al,In)GaN layer can be from <NUM> to <NUM>, from <NUM> to <NUM>, from <NUM> to <NUM>, from <NUM> to <NUM>, or from <NUM> to <NUM>. The first n-(Al,In)GaN layer can be grown in a H<NUM> environment. The growth conditions for the first n-(Al,In)GaN layer can be typical RPCVD growth conditions. The first n-(Al,In)GaN layer can be grown, for example, at a partial pressure of N<NUM> from <NUM> Torr to <NUM> Torr or from <NUM> Torr to <NUM> Torr and at a temperature from <NUM> to <NUM>,<NUM>.

After the first n-(Al,In)GaN layer is grown, a second, thicker n-(Al,In)GaN layer can be grown on the thin n-(Al,In)GaN layer. Both layers can be grown in the presence of H<NUM> and NH<NUM>, in a high H<NUM> environment, at a chamber pressure from <NUM> Torr to <NUM> Torr, and at a temperature less than <NUM>,<NUM>. For example, the second n-(Al,In)GaN layer can be grown at a chamber pressure from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, from <NUM> Torr to <NUM> Torr, or from <NUM> Torr to <NUM> Torr. The growth temperature can be, for example, less than <NUM>, less than <NUM>, less than <NUM>, or less than <NUM>. For example, the temperature for growing the second n-(Al,In)GaN layer can be from <NUM> to <NUM>,<NUM>, from <NUM> to <NUM>, from <NUM> to <NUM>, from <NUM> to <NUM>, or from <NUM> to <NUM>. The second n-(Al,In)GaN layer can be grown in a high H<NUM> environment where the H<NUM> concentration can be, for example, greater than <NUM> Torr, greater than <NUM> Torr, or greater than <NUM> Torr. The growth conditions for the second n-(Al,In)GaN layer can be typical RPCVD growth conditions with the exception that a high H<NUM> environment can be used. The second n-(Al,In)GaN layer can also be grown in a low H<NUM> environment.

The first n-(Al,In)GaN layer can be thinner than the capping layer typically used to protect an underlying activated p-(Al,In)GaN layer from in-diffusion of H<NUM> that would otherwise cause the p-(Al,In)GaN layer to become passivated.

Alternatively, the second n-(Al,In)GaN layer can be grown by any suitable semiconductor deposition method such as by MOCVD, by RPCVD, or by MBE. The n-(Al,In)GaN layer can be grown in in the absence of H<NUM>, in the presence of a low H<NUM> environment, or in the presence of a high H<NUM> environment.

For example, a method of fabricating a semiconductor structure comprising a buried activated p-(Al,In)GaN layer can comprise (a) exposing a magnesium-doped p-(Al,In)GaN layer to a gaseous mixture comprising H<NUM>, NH<NUM>, or a combination thereof, wherein the gaseous mixture has a partial pressure of H<NUM> less than <NUM> Torr, to provide an exposed magnesium-doped p-(Al,In)GaN layer; (b) growing a first n-(Al,In)GaN layer on the exposed magnesium-doped p-(Al,In)GaN layer by RPCVD in an environment wherein the partial pressure of N<NUM> is greater than the partial pressure of H<NUM>, and (c) growing a second n-(Al,In)GaN layer on the first n-(Al,In)GaN layer by RPCVD in an environment wherein the partial pressure of H<NUM> is greater than the partial pressure of N<NUM>; to provide a semiconductor structure comprising a buried activated p-(Al,In)GaN layer.

The method can consist of steps (a), (b), and (c). In step (a) the gaseous mixture can comprise N<NUM>, or in certain embodiments the gaseous mixture does not comprise N<NUM>.

An n-(Al,In)GaN layer can be grown in the presence of H<NUM>, NH<NUM>, or a combination thereof.

An n-(Al,In)GaN layer can comprise one or more layers. When the n-(Al,In)GaN layer comprises two or more n-(Al,In)GaN layer, each of the layers can be grown using a different deposition process, using different gas compositions, at different temperatures, for different durations, or a combination of any of the foregoing. For example, an n-(Al,In)GaN layer can comprise a first layer having a first n-type dopant concentration, and a second layer having a higher n-type dopant concentration such as an n+(Al,In)GaN layer. The n-(Al,In)GaN layer can have different elemental compositions.

Following growth of the n-(Al,In)GaN layers, the p-(Al,In)GaN layer is buried beneath the overlying n-(Al,In)GaN layers and is an activated p-(Al,In)GaN layer; hence, the p-(Al,In)GaN layer is a buried activated p-(Al,In)GaN layer.

As a result of these process steps, beginning with either a passivated, a partially passivated, or an activated p-(Al,In)GaN layer, which can be grown by any suitable method, a semiconductor structure having a buried activated p-(Al,In)GaN layer is formed. The process does not include a separate step of annealing the p-(Al,In)GaN layer in a low H<NUM> environment at high temperature to activate the p-(Al,In)GaN layer. For example, the process does not include exposing the p-(Al,In)GaN layer to a temperature of greater than <NUM> in a low H<NUM> environment that would cause H<NUM> to diffuse out of the p-(Al,In)GaN layer.

An n-(Al,In)GaN layer can comprise n-GaN, n-AlGaN, n-InGaN, or n-AlInGaN. The n-(Al,In)GaN layer can have a concentration of an n-type dopant such as Si or Ge, within a range, for example, from 1E18 cm-<NUM> to 5E20 cm-<NUM>, from 5E18 cm-<NUM> to 1E20 cm-<NUM>, or from 1E19 cm-<NUM> to 1E20 cm-<NUM>. An n-(Al,In)GaN layer can comprise two or more n-(Al,In)GaN layers, with each layer having, for example, a different concentration of an n-type dopant and/or different n-type dopant concentration.

A p-(Al,In)GaN can comprise a p++-(Al,In)GaN and a p-(Al,In)GaN layer, and an p-(Al,In)GaN can comprise an n++-(Al,In)GaN and an n-(Al,In)GaN layer.

Tunnel junctions can have a total thickness, for example, from about <NUM> to <NUM>, and each of the p++-(Al,In)GaN layer and the n++-(Al,In)GaN layer can have a thickness, for example, from <NUM> to <NUM>. For example, each of the p++ -(Al,In)GaN layer and the n++-(Al,In)GaN layer can have a thickness from <NUM> to <NUM>. A p++-(Al,In)GaN layer and an n++-(Al,In)GaN layer can have the same thickness or can have a different thickness. A p++-(Al,In)GaN layer and an n++-(Al,In)GaN layer may have a graded dopant concentration. For example, a portion of a p++-(Al,In)GaN layer adjacent to the underlying p-type layer can have a dopant concentration that is graded from the dopant concentration of the underlying p-type layer to the desired dopant concentration in the p++-(Al,In)GaN layer. Similarly, an n++-(Al,In)GaN layer can have a dopant concentration that is graded from a maximum adjacent to the p++-(Al,In)GaN layer to a minimum adjacent to an n-type layer formed over a tunnel junction. The thickness, doping concentration, doping profile and number of layers of a tunnel junction can be selected to exhibit a low series voltage drop when conducting current in reverse-biased mode. For example, a voltage drop across a tunnel junction can be, for example, less than <NUM> V at <NUM> A/cm<NUM> or less than <NUM>. 1V at <NUM> A/cm<NUM>. Other suitable layers can be included between a p++-(Al,In)GaN layer and an n++-(Al,In)GaN layer to leverage the polarization field in III-nitrides to help align the bands for tunneling. This polarization effect may reduce the doping requirement in the n++-(Al,In)GaN and p++-(Al,In)GaN layers and reduce the tunneling distance required and thereby allow higher current flow. The composition of a layer or layers between a p++-(Al,In)GaN layer and an n++-(Al,In)GaN layer may be different from the composition of the p++-(Al,In)GaN layer and the n++-(Al,In)GaN layer, and/or may be selected to cause band re-alignment due to the polarization charge that exists between dissimilar material interface in the III-nitride material system. Examples of suitable tunnel junctions are described, for example, in <CIT>.

Additional semiconductor layers can be grown overlying the n-(Al,In)GaN layer.

After a semiconductor layer is grown on the processed p-(Al,In)GaN layer, such as an n-(Al,In)GaN layer, additional semiconductor layers can be grown using any suitable semiconductor growth method such as MOCVD, RPCVD, or MBE.

After growing the n-(Al,In)GaN layer, one or more semiconductor layers can be grown overlying the n-(Al,In)GaN layer to provide a buried activated p-(Al,In)GaN layer. For example, the one or more semiconductor layers can be grown in the presence of H<NUM>, NH<NUM>, or a combination thereof. Growing the one or more semiconductor layers does not result in the passivation of the buried activated p-(Al,In)GaN layer.

This result is not expected. First, if the starting p-(Al,In)GaN layer is passivated, the method does not include a high temperature anneal step in the absence of H<NUM> or in a low H<NUM> environment. Second, if the starting p-(Al,In)GaN layer is already activated, exposure of the p-(Al,In)GaN to hydrogen during the H<NUM>:NH<NUM> exposure and/or during growth of the subsequent n-(Al,In)GaN layer(s) and the one or more semiconductor layers, would be expected to passivate the p-(Al,In)GaN layer.

To demonstrate the ability of methods provided by the present disclosure to produce high-quality buried activated p-(Al,In)GaN layers, p-(Al,In)GaN layer tunnel junctions were fabricated. n/p-(Al,In)GaN tunnel junctions fabricated using methods provided by the present disclosure can exhibit an voltage drop, for example, across the n/p-(Al,In)GaN tunnel junction of less than <NUM> V at <NUM> A/cm<NUM>, less than <NUM> V at <NUM> A/cm<NUM>, less than <NUM> V at <NUM> A/cm<NUM>, or less than <NUM> V at <NUM> A/cm<NUM>. n/p-(Al,In)GaN tunnel junctions fabricated using methods provided by the present disclosure exhibit an voltage drop, for example, across the n/p-(Al,In)GaN tunnel junction from <NUM> V to <NUM> V at <NUM> A/cm<NUM>, from <NUM> V to <NUM> V at <NUM> A/cm<NUM>, or from <NUM> V to <NUM> V at <NUM> A/cm<NUM>.

Therefore, despite the presence of H<NUM> during growth of the n/p-(Al,In)GaN tunnel junction the method produces a high-quality n/p-(Al,In)GaN tunnel junction having a low voltage drop.

Methods of fabricating a semiconductor structure having a buried activated p-(Al,In)GaN layer or a device such as an n/p-(Al,In)GaN tunnel junction do not include a p-(Al,In)GaN activation step, where the activation step comprises, for example, exposing the p-(Al,In)GaN layer to a H<NUM>-free environment at elevated temperature. In other words, methods provided by the present disclosure do not comprise exposing the p-(Al,In)GaN layer to an environment capable of passivating the p-(Al,In)GaN layer and/or subjecting the p-(Al,In)GaN layer to a separate activation step.

Methods provided by the present disclosure also do not include a lateral activation step. Structures or chips having a buried activated p-(Al,In)GaN layer provided by the present disclosure can have a minimum lateral dimensions greater than <NUM> × <NUM>, greater than <NUM> × <NUM>, greater than <NUM>× <NUM>, or greater than <NUM> × <NUM>, or a chip can have dimensions a × b, where each of a and b is greater than <NUM>, greater than <NUM>, greater than <NUM>, or greater than <NUM>.

In a typical RPCVD process semiconductors are grown at low pressures, such as at pressures less than <NUM> Torr. In methods provided by the present disclosure, semiconductor growth process involves using a wide range of pressures such as at pressures greater than <NUM> Torr, and at pressures from <NUM> Torr to <NUM> Torr. The high pressure range facilitates pre-growth surface cleaning and modification, steps that are well suited to a higher pressure, while subsequently exposing the wafer to RPCVD conditions for low temperature growth. This combination of low and high pressure ranges is able to provide high quality tunnel junctions with superior compared to those fabricated using other growth techniques. For example, exposing a p-(Al,In)GaN layer to H<NUM>, NH<NUM>, or a combination thereof at a partial pressure of H<NUM> less than <NUM> Torr and a substrate temperature of less than <NUM> can serve as a cleaning step that can help produce high quality tunnel junctions. Using an RPCVD reactor that is capable of use at high pressures, and without a plasma, and can be switched to low pressure can improve the performance of tunnel junctions.

Methods provided by the present disclosure can be used to fabricate structures having a high-quality buried activated p-(Al,In)GaN layer.

The buried activated p-(Al,In)GaN layers and structures comprising buried activated p-(Al,In)GaN layers such as n/p-(Al,In)GaN tunnel junctions can be incorporated into any suitable semiconductor device.

For example, n/p-(Al,In)GaN tunnel junctions provided by the present disclosure can be incorporated into a device comprising two or more diodes and can be used to interconnect diodes.

For example, LEDs, laser diodes, photovoltaic devices, optoelectronic devices, multijunction solar cells, transistors, and power converters can incorporate one or more n/p-(Al,In)GaN tunnel junctions provide by the present disclosure.

A semiconductor device comprising an n/p-(Al,In)GaN tunnel junction provided by the present disclosure can include a stacked optoelectronic device such as a stacked LED structure, a stacked laser diode structure, a multijunction solar cell, a stacked transistor, or a stacked power converter. By stacked is meant that the optoelectronic device has two or more diodes or junctions that can be interconnected using an n/p-(Al,In)GaN tunnel junction provided by the present disclosure.

Thus, semiconductor devices provided by the present disclosure can comprise a buried activated p-(Al,In)GaN layer fabricated using the methods disclosed herein and/or an n/p-(Al,In)GaN fabricated using the methods disclosed herein.

n/p-(Al,In)GaN tunnel junctions can be used to replace conductive films such as conductive indium tin oxide (ITO) films used to interconnect to a semiconductor layer. Accordingly, semiconductor devices provided by the present disclosure can comprise an electrically conductive layer comprising an n/p-(Al,In)GaN tunnel junction.

Embodiments provided by the present disclosure are further illustrated by reference to the following examples, which describe semiconductors, semiconductor devices, and methods provided by the present disclosure. It will be apparent to those skilled in the art that many modifications, both to materials, and methods, may be practiced without departing from the scope of the disclosure.

The RPCVD layers described herein are generally grown with a lower relative growth rate and at lower temperatures (compared with e.g., MOCVD) and under nitrogen plasma. The growth environment can be a mixture of hydrogen, nitrogen and other gases but with (i) predominantly NH<NUM>, or (ii) predominantly H<NUM>, and or (iii) a mixture of predominantly NH<NUM> and H<NUM>. Further details are provided below.

The following experiment was designed to demonstrate the use of RPCVD for growing a buried but activated p-GaN layer for a Tunnel Junction (TJ) application. The TJ structures were grown on commercially-obtained, MOCVD-grown blue LEDs on <NUM>-inch patterned sapphire substrates using both RPCVD and MOCVD (forming the three structures as shown in <FIG> and <FIG> representing, respectively, the structures with and without an InGaN cap). Such MOCVD-grown blue LEDs may be obtained from a number of commercial sources including Veeco, AMEC, Lumileds and the like.

The final devices were measured using on-wafer electroluminescence (EL) quick test methods. The n-contact was made by scribing through the layers to expose the lower n-GaN layer and filling with indium-tin solder. The top contact was made using an indium sphere and annealed on a hot plate for <NUM> sec. A gentle square scribe (<NUM> × <NUM>) was made surrounding the top contact to isolate the contacts, such that the only electrical connection between the top and bottom contacts was via the lower n-GaN layer. This prevented current from conducting laterally between the two contacts via the top n-GaN layers.

The EL measurements were made by sweeping the forward bias current from <NUM> mA to <NUM> mA and recording the light output power (LOP) using a power meter located underneath the substrate. The EL was compared for the structures grown by MOCVD and RPCVD and also against the original source wafer. The contacts for the original source wafer were prepared in the same way as for the TJ structures.

The commercial LEDs were available with two different terminations. The first was terminated with a highly doped (p++) GaN:Mg layer (as is typically used in the industry). The second had an additional <NUM>-thick InGaN:Si contact layer to improve the contact resistance of the bare LED (as is typically used for an ITO contact in the industry). For completeness, the TJ overgrowths were tested on both structures (with and without the n-InGaN contact layer).

The results of the testing are shown graphically in <FIG> (results for the structures of <FIG>) and <FIG> (results for the structures of <FIG>) and Table <NUM> and Table <NUM> present the data for the structures of <FIG> and <FIG>, respectively. The text colours in the table correspond to the colour of the line traces in the graphs of <FIG> and <FIG>.

The results shown in <FIG> and <FIG>, and in Tables <NUM> and <NUM>, indicate that the TJ structure grown under RPCVD conditions according to the present invention (Structure <NUM> in each experiment) displays comparable LOP compared to the bare LED (Structure <NUM>) and also displays low comparable Vf. The comparable LOP indicates a sufficient number of holes were injected into the active region for recombination while the low Vf indicates the voltage drop across the TJ and the voltage drop across the buried p-GaN layer is small. Both of these observations indicate that the buried p-GaN layer remained fully activated during the TJ growth.

<FIG> show graphical representations of the results of the testing of the structures represented in <FIG>, having an n-InGaN cap, wherein the solid lines relate to the MOCVD grown blue LED of the structure shown in <FIG>, the broken lines relate to the MOCVD completed structure shown in <FIG> and the dashed lines relate to the RPCVD completed structure shown in <FIG>.

<FIG> show graphical representations of the results of the testing of the structures represented in <FIG>, without an n-InGaN cap, wherein the solid lines relate to the MOCVD grown blue LED of the structure shown in <FIG> and the dashed relate to the RPCVD completed structure shown in <FIG>.

In contrast, the TJ structure grown solely by MOCVD (Structure <NUM> in each experiment) can be seen, in <FIG> and Table <NUM>, to display higher Vf and lower LOP indicating poor hole injection efficiency and high series resistance which are associated with a passivated or partially passivated buried p-GaN layer. Further, the LOP and Vf was unstable during measurements which is typical of LED devices with passivated or partially passivated p-GaN layers.

The RPCVD TJ structure displays good LOP and Vf compared to the bare LED (structure <NUM>) for both experiments with and without the n-InGaN contact layer. The MOCVD grown TJ was only tested on the structure without the n-InGaN layer.

The structures shown in <FIG> are examples of a single RPCVD n-GaN layer overgrown on an MOCVD-grown p-GaN layer such that the p-GaN layer becomes and/or remains activated at the end of the growth. The first structure (on the left) represents overgrowth on a complete MOCVD LED. The second structure (on the right) represents overgrowth on a simplified structure containing only the buffer layers and the p-GaN layers (no active region). The process conditions used for growth of these structures formed by methods provided by the present disclosure are provided in Table <NUM>.

The present invention provides a number of significant benefits due to the use of a hybrid MOCVD/RPCVD growth approach. Particularly, the use of RPCVD allows high carrier concentrations and high carrier mobility to be achieved in the as-grown doped semiconductor layers at temperatures which are not damaging to potentially temperature sensitive layers, such as indium-containing active layers. A sharp magnesium profile can also be achieved at tunnel junctions grown under RPCVD conditions due to low dopant diffusion achieved at the low growth temperatures, as compared with MOCVD growth. Finally, this approach allows for buried p-type semiconductor layers to be in an activated state and to remain this way, due to n-type layer RPCVD overgrowth, even if subsequent structures are to be grown under MOCVD hydrogen-rich conditions.

The quality of buried activated p-GaN layers fabricated according to methods provided by the present disclosure was determined by growing n/p-GaN tunnel junctions and measuring the device performance.

<FIG> show device structures used to evaluate the performance of n/p-(Al,In)GaN tunnel junctions and buried activated p--(Al,In)GaN layers fabricated using methods provided by the present disclosure.

<FIG> shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate <NUM>, u-GaN layer <NUM>, n-GaN layer <NUM>, multi-quantum well layer <NUM>, p-GaN layer <NUM>, and p++-GaN cap layer <NUM>. Electrical contacts 807A and 807B are interconnected to the n-GaN layer <NUM> and to the p++-GaN cap layer <NUM>, respectively.

<FIG> shows a cross-sectional view of a device structure that includes the commercial MQW LED structure of <FIG>, and which was overgrown with a <NUM>-thick n++-GaN layer and a <NUM>-thick n-GaN layer to form a tunnel junction B. Before growing the n-doped GaN layers, the p++-GaN layer was exposed to a NH<NUM>:H<NUM> environment followed by a N<NUM> plasma according to methods provided by the present disclosure, and the n-doped GaN layers were then grown under RPCVD conditions.

<FIG> shows the layers of the commercial blue MQW LED including sapphire substrate <NUM>, u-GaN layer <NUM>, n-GaN layer <NUM>, multi-quantum well layer <NUM>, p-GaN layer <NUM>, and p++-GaN cap layer <NUM>. A <NUM>-thick RP-CVD-grown n++-GaN layer <NUM> overlies the p++-GaN layer and a <NUM>-thick RP-CVD grown n-GaN layer <NUM> overlies the n++-GaN layer <NUM>. Electrical contacts 907A and 907B are interconnected to the buried n-GaN layer <NUM> and to uppermost n-GaN layer <NUM>, respectively.

The device structures shown in <FIG> include identical layers up to the top p++-GaN layer, and therefore any differences in the device performance can be attributed to the layers above the p++-GaN layer.

Ideally one would like to measure the performance of the entire LED structure. However, this requires that an ohmic contact be made to the p++-GaN surface, which is difficult to accomplish and is expected to result in a non-insignificant contact resistance. On the other hand, measuring the properties of the tunnel junction directly requires that an ohmic contact be made to the uppermost n-GaN surface, which is typically easier and less likely to contribute to a significant contact resistance, and also minimizes the number of device processing steps.

Nevertheless, if the Vf and light output (LOP) of the device with the n/p-GaN tunnel junction are as good as or better than the Vf and LOP of the same LED device without the n/p-GaN tunnel junction, then it can be inferred that the buried p-GaN layer must be active. The converse, however, is not necessarily true. A tunnel junction that displays poor Vf and LOP may be the result of a passivated p-GaN layer and/or may be due to a poor quality n/p-GaN tunnel junction with a low tunnelling probability.

<FIG> shows an IV curve for the devices shown in <FIG>. The LED having a tunnel junction exhibited a voltage of <NUM> V at a current density of <NUM> A/cm<NUM> compared to a voltage of <NUM> V at a current density of <NUM> A/cm<NUM> for the commercial LED without the overlying n/p-GaN tunnel junction. This result indicates that the buried p-GaN layer is activated.

The effect of various pre-growth treatment conditions was evaluated using the semiconductor structures shown in <FIG>.

Starting with a commercial blue MQW LED as described in Example <NUM>, the uppermost p++-GaN layer was first exposed under various conditions.

A <NUM>-thick n++-GaN layer (dopant concentration ~ <NUM>. 0E20 cm-<NUM>) was grown over the exposed p++-GaN layer by RPCVD under the indicated process conditions. To complete the n/p-GaN tunnel junction, a <NUM>-thick n-GaN layer (dopant concentration about <NUM>. 0E19 cm-<NUM>) was grown over the n++-GaN layer, also by RPCVD under the indicated process conditions. The structure of the overlying n++/n-GaN layers is shown in <FIG>.

The process conditions used to fabricate the n/p-GaN tunnel junctions are shown in <FIG> (Table <NUM>). <FIG> (Table <NUM>) also shows the LOP, Vf, and the change in the Vf (ΔV f) compared to the respective LED without the overlying n/p-GaN tunnel junction.

The full commercial LED had an ITO layer over the p+-GaN layer.

<FIG> shows IV curves for a full commercial MQW LED (dashed line) with an ITO layer and a MQW LED with a TJ (solid line). Before growing the n++- and n-GaN layers, the uppermost p-GaN layer of the LED was exposed to NH<NUM> and N<NUM>.

<FIG> shows IV curves for a partial MQW LED with p+/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid line) deposition of n++/n-GaN layers. Before growing the n++/n-GaN layers, the uppermost p-GaN layer was exposed to NH<NUM> and N<NUM>. The process conditions and performance characteristics are shown in <FIG> (Table <NUM>) and correspond to Process conditions A.

<FIG> shows IV curves for commercial full LEDs including exposure of the p-GaN layer to a NH<NUM>:H<NUM> environment and overgrowth of an n++/n-GaN layer using RPCVD.

<FIG> shows IV curves for 1TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a NH<NUM>:H<NUM> environment and overgrowth of an n++/n-GaN layer using RPCVD. The process conditions and performance characteristics are shown in <FIG> (Table <NUM>) and correspond to Process conditions B.

<FIG> shows IV curves for commercial full LEDs including exposure of the p-GaN layer to a N<NUM> environment and overgrowth of an n++/n-GaN layer using RPCVD.

<FIG> shows IV curves for 1TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N<NUM> environment and overgrowth of an n++/n-GaN layer using RPCVD. The process conditions and performance characteristics are shown in <FIG> (Table <NUM>) and correspond to Process conditions C.

The results shown in <FIG> demonstrate that exposure to NH<NUM> and H<NUM> environment performed better that the MQW LED at higher currents thereby confirming that the underlying buried p-GaN layer was activated and that even when grown under MOCVD conditions expected to produce a passivated p-GaN layer, a high-quality buried activated p-GaN layer was produced using the methods provided by the present disclosure.

<FIG> shows the LOP with current for LED devices processed according to process conditions B (<FIG>, Table <NUM>), and corresponding to the devices having the IV curves shown in <FIG>. The results shown in <FIG> demonstrate that tunnel junctions fabricated using process conditions B and fabricated according to methods provided by the present disclosure exhibited a slightly higher LOP at the same current compared to an LED n-GaN layers grown over an ITO film.

<FIG> show photographs of electroluminescence images of an LED with an overlying n/p-GaN tunnel junction fabricated according to methods provided by the present disclosure and using process conditions B, and without an overlying n/p-GaN tunnel junction, respectively. The images shown in <FIG> were obtained for the devices shown in <FIG>, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the performance of the LED and thereby confirming that the p-GaN layer is activated.

Claim 1:
A method of fabricating a semiconductor structure (<NUM>) comprising a buried activated p-(Al,ln)GaN layer (<NUM>), comprising:
(a) exposing a magnesium-doped p-(Al,ln)GaN layer (<NUM>) to a gaseous mixture comprising H<NUM>, NH<NUM>, or a combination thereof, wherein the gaseous mixture has a partial pressure of H<NUM> less than <NUM> Torr, to provide an exposed magnesium-doped p-(Al,In)GaN layer (<NUM>); and
(b) growing an n-(Al,ln)GaN layer (<NUM>) on the exposed magnesium-doped p-(Al,ln)GaN layer (<NUM>) in an environment comprising H<NUM>, NH<NUM>, or a combination thereof, wherein the partial pressure of H<NUM> is from <NUM> Torr to <NUM> Torr,
to provide a semiconductor structure comprising a buried activated p-(Al,ln)GaN layer.