Patent Description:
Embodiments of the present disclosure relate to the field of semiconductors, and in particular to a manufacturing method of a semiconductor structure and a semiconductor structure.

With the development of semiconductor manufacturing technologies, the critical dimension of the semiconductor process has shrunk to the order of deep submicron. Due to the continuous shrinking of the critical dimension, a distance between interconnection lines in a semiconductor structure is getting closer, and parasitic capacitance is getting larger and larger. The parasitic capacitance can seriously affect the performance of the semiconductor structure, and especially reduce the operating speed and reliability of the semiconductor structure.

Therefore, how to reduce the parasitic capacitance in the semiconductor structure is currently an urgent technical problem to be solved. Related technologies are known from <CIT>, <CIT>, <CIT> and <CIT>.

Compared with a prior art, the technical solution according to the embodiments of the present disclosure has the following advantages.

In the manufacturing method of a semiconductor structure according to the embodiment of the present disclosure, the first isolation layer covering the surface of the sidewall layer is formed, that is, also covers a top of the sidewall layer; after the sidewall layer is removed to form the gap, the first isolation layer completely seals the gap, and a step of sealing the gap is no longer required, thereby avoiding the formation of a deposition layer in the gap during the sealing process, or situations such as improper sealing, and then effectively reducing the parasitic capacitance of the semiconductor structure.

In addition, the method for removing the sidewall layer includes: providing a plasma source, causing an ion beam generated by the plasma source to react with the sidewall layer after passing through the first isolation layer and form reaction byproducts, and discharging at least part of the reaction byproducts through the first isolation layer. Compared with a wet process, in this method, fewer residues are generated, and the sidewall layer can be removed more thoroughly.

One or more embodiments are exemplified by pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the accompanying drawings do not constitute a scale limitation.

<FIG> are schematic structural diagrams corresponding to various steps of a manufacturing method of a semiconductor structure according to an embodiment of the present disclosure.

It can be seen from the Background section that the parasitic capacitance in a semiconductor structure needs to be further reduced. A method for reducing the parasitic capacitance may include: forming a sacrificial layer between a conducting layer and an insulating layer which are adjacent, removing the sacrificial layer to form a gap, and sealing the gap. Since there is air in the gap and a dielectric constant of the air is low, the parasitic capacitance can be reduced. In a process step of sealing the gap, part of reaction gas can enter the gap and form a deposition layer at a bottom of the gap, thereby reducing the size of the gap. In addition, if improper sealing occurs, during subsequent deposition of a conducting material, the conducting material is likely to enter the gap, thereby causing electrical conduction between interconnection lines that should be isolated from each other. Therefore, the above method has a poor effect of reducing parasitic capacitance, and may also affect the yield of the semiconductor structure.

In order to solve the above problem, embodiments of the present disclosure provide a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a base with an electrical contact layer therein; forming an insulating layer on the base, the insulating layer having a through hole penetrating the insulating layer, and the through hole exposing a surface of the electrical contact layer; forming a sidewall layer on a sidewall of the through hole; forming a first isolation layer, the first isolation layer covering a surface of the sidewall layer and an exposed surface of the insulating layer; removing the sidewall layer to form a gap between the first isolation layer and the insulating layer; and forming a conducting layer filling the through hole, the conducting layer being electrically connected to the electrical contact layer. Since the first isolation layer covers the entire surface of the sidewall layer, the gap formed after the removal of the sidewall layer is completely surrounded by the first isolation layer and does not need to be sealed, thereby ensuring that the parasitic capacitance can be reduced to a great extent and improving the yield of the semiconductor structure.

In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, various embodiments of the present disclosure will be detailed below in combination with the accompanying drawings. However, a person of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are provided for readers to better understand the present disclosure. However, even if these technical details are not provided and based on variations and modifications of the following embodiments, the technical solutions sought for protection in the present disclosure can also be implemented.

<FIG> are schematic structural diagrams corresponding to various steps of a manufacturing method of a semiconductor structure according to a first embodiment of the present disclosure. A detailed description will be given below in conjunction with the drawings.

Referring to <FIG>, a base <NUM> with an electrical contact layer <NUM> therein is provided. The base <NUM> may include structures such as wordlines, bitlines, sources, drains and the like. The base <NUM> may be made of silicon, sapphire, silicon carbide, gallium arsenide, aluminum nitride, zinc silicon oxide, or the like.

The electrical contact layer <NUM> is configured to achieve electrical connection between an internal structure of the base <NUM> and a conducting layer formed subsequently. In an example, the subsequently-formed conducting layer may be electrically connected to the bitlines in the base <NUM> through the electrical contact layer. In the present embodiment, the electrical contact layer <NUM> is made of copper. In other embodiments, the electrical contact layer <NUM> may also be made of a conducting material, such as polysilicon, tungsten, titanium, or the like.

In the present embodiment, the base <NUM> further has isolation structures <NUM> therein, and the isolation structure <NUM> is configured to isolate adjacent electrical contact layers <NUM>. In the present embodiment, the isolation structure <NUM> is made of silicon oxide. In other embodiments, the isolation structure <NUM> may also be made of an insulating material such as silicon carbide, silicon nitride, or the like.

Referring to <FIG>, an insulating layer <NUM> is formed on the base <NUM>. The insulating layer <NUM> has a through hole <NUM> penetrating the insulating layer <NUM>, and the through hole <NUM> exposes a surface of the electrical contact layer <NUM>.

The insulating layer <NUM> is configured to isolate the conducting layer formed in the through hole <NUM> subsequently.

The insulating layer <NUM> is located on the isolation structure <NUM>, and in a direction parallel to a surface of the base <NUM>, the isolation structure <NUM> is wider than the insulating layer <NUM> for the following reason: a gap, a first isolation layer and a second isolation layer will be formed subsequently on a sidewall of the insulating layer <NUM>, the isolation structure <NUM> is wider than the insulating layer <NUM>, and when a width difference meets a certain value range, the gap, the first isolation layer and the second isolation layer can directly face the isolation structure <NUM>, so that the entire surface of the electrical contact layer <NUM> is exposed to increase a contact area between the subsequently-formed conducting layer and the electrical contact layer <NUM>, thereby reducing contact resistance.

A width of the insulating layer <NUM> is greater than or equal to one-half of a width of the isolation structure <NUM> and less than or equal to the width of the isolation structure <NUM>. When the width of the insulating layer <NUM> is within the above range, the first and second isolation layers to be formed subsequently can be well supported and the stability of the semiconductor structure can be improved; and moreover enough space can also be reserved for the gap, the first isolation layer and the second isolation layer to be formed subsequently, so that the gap, the first isolation layer and the second isolation layer can be located on the isolation structure <NUM>, and the entire surface of the electrical contact layer <NUM> can be exposed to increase the contact area between the subsequently-formed conducting layer and the electrical contact layer <NUM>.

In the present embodiment, the insulating layer <NUM> and the isolation structure <NUM> are made of a same material, which can improve the tightness of adhesion between the insulating layer <NUM> and the isolation structure <NUM>, thereby improving the stability of the semiconductor structure. For example, the insulating layer <NUM> and the isolation structure <NUM> are both made of silicon dioxide. In other embodiments, the insulating layer <NUM> may also be made of a different material from the isolation layer; for example, the insulating layer <NUM> may be made of an insulating material such as silicon carbide, silicon nitride, or the like.

Specifically, the process step for forming the insulating layer <NUM> and the through hole <NUM> is as follows. Referring to <FIG>, an initial insulating layer 103a is formed on the base <NUM>, and a patterned photoresist layer <NUM> is formed on the initial insulating layer 103a; referring to <FIG>, using the patterned photoresist layer <NUM> (see <FIG>) as a mask, the initial insulating layer 103a (see <FIG>) is etched to form the insulating layer <NUM>.

In the present embodiment, a chemical vapor deposition process is carried out to form the initial insulating layer 103a. The chemical vapor deposition process has a high deposition rate and can shorten a process time.

In the present embodiment, a dry etching method is carried out to etch the initial insulating layer 103a until the electrical contact layer <NUM> is exposed, thus forming the insulating layer <NUM> and the through hole <NUM> exposing the electrical contact layer <NUM>.

Referring to <FIG>, a sidewall layer <NUM> is formed on the sidewall of the through hole <NUM>.

The sidewall layer <NUM> is configured to occupy a spatial position for the subsequent formation of the gap; that is, the position of the sidewall layer <NUM> is the position of the subsequently-formed gap.

The sidewall layer <NUM> should be made of a material which can be decomposed easily. In this way, during the subsequent removal of the sidewall layer <NUM> to form the gap, under the action of oxygen plasma, the sidewall layer <NUM> can be discharged as a gas after being decomposed. The sidewall layer <NUM> is made of amorphous carbon, hydrocarbon or a polymer, for example, CxHy.

In the present embodiment, in a direction perpendicular to the surface of the base <NUM>, a ratio of a height of the sidewall layer <NUM> to a height of the insulating layer <NUM> is greater than or equal to <NUM>. That is, a top surface of the sidewall layer <NUM> may be flush with a top surface of the insulating layer <NUM> or may be lower than the top surface of the insulating layer <NUM>.

When the ratio of the height of the sidewall layer <NUM> to the height of the insulating layer <NUM> is greater than or equal to <NUM>, the greater the height of the sidewall layer <NUM>, the greater the height of the gap to be formed subsequently, so that the parasitic capacitance can be reduced to a great extent.

Preferably, the top surface of the sidewall layer <NUM> is lower than the top surface of the insulating layer <NUM>, and the ratio of the height of the sidewall layer <NUM> to the height of the insulating layer <NUM> is less than or equal to <NUM>. In this way, the subsequently-formed first isolation layer can be located on the sidewall of the insulating layer <NUM> exposed by the sidewall layer <NUM>; that is, the subsequently-formed first isolation layer can be well supported by the sidewall of the insulating layer <NUM>, so that the first isolation layer is not likely to collapse and has a good stability.

The step of forming the sidewall layer <NUM> will be described in detail below.

Referring to <FIG>, an initial sidewall layer 105a is formed on a surface of the insulating layer <NUM> and a bottom of the through hole <NUM>. In the present embodiment, an atomic layer deposition process is carried out to form the initial sidewall layer 105a. The initial sidewall layer 105a formed by the atomic layer deposition process has a relatively even thickness. In other embodiments, a chemical vapor deposition process or a physical vapor deposition process may also be carried out to form the initial sidewall layer 105a.

Referring to <FIG>, the initial sidewall layer 105a located at the bottom of the through hole <NUM> and the top surface of the insulating layer <NUM> is removed (see <FIG>), and part of the initial sidewall layer 105a located on the sidewall of the through hole <NUM> is also removed; the remaining initial sidewall layer 105a serves as the sidewall layer 105a.

That is, the top surface of the sidewall layer <NUM> is lower than the top surface of the insulating layer <NUM>, so that the first isolation layer formed subsequently also covers the sidewall of the insulating layer <NUM> exposed by the sidewall layer <NUM>. In this way, after the sidewall layer <NUM> is removed, since the first isolation layer is still supported by the sidewall of the insulating layer <NUM>, the first isolation layer has the good stability.

In other embodiments, the initial sidewall layer 105a located on the sidewall of the through hole <NUM> may not be removed; that is, the top surface of the formed sidewall layer <NUM> is flush with the top surface of the insulating layer <NUM>, and the first isolation layer formed subsequently can not cover the sidewall of the insulating layer <NUM>.

In the present embodiment, part of the initial insulating layer 105a is removed by dry etching (see <FIG>).

Referring to <FIG>, a first isolation layer <NUM> is formed, and the first isolation layer <NUM> covers the surface of the sidewall layer <NUM> and an exposed surface of the insulating layer <NUM>.

Compared with the sidewall layer <NUM>, the first isolation layer <NUM> is required to be decomposed hardly. Therefore, the first isolation layer <NUM> is unlikely to be damaged during the subsequent removal of the sidewall layer <NUM> and thus achieves a better stability.

In addition, the first isolation layer <NUM> is relatively thin; for example, the thickness thereof may be less than <NUM>, so that an ion beam can more easily pass through the first isolation layer <NUM> and remove the sidewall layer <NUM>.

In addition, the first isolation layer <NUM> has holes, so that the ion beam can directly pass through the holes, and therefore the sidewall layer <NUM> can be removed more thoroughly.

In the present embodiment, the first isolation layer <NUM> is made of silicon dioxide. In other embodiments, the first isolation layer <NUM> may also be made of a silicon-oxyhydrocarbon. The silicon dioxide or silicon-oxyhydrocarbon is hardly decomposed under the action of oxygen plasma and has the good stability.

In the present embodiment, the first isolation layer <NUM> is formed by a low-temperature atomic layer deposition process. In this way, a thin first isolation layer <NUM> can be formed, so that the sidewall layer <NUM> completely covered by the first isolation layer <NUM> can be more easily removed later. A temperature range of the low-temperature atomic layer deposition process is in a low-temperature range of <NUM> to <NUM>. Through the low-temperature atomic layer deposition process, the thickness of the first isolation layer <NUM> can be more accurately controlled to obtain a homogeneous thin first isolation layer <NUM>, and the first isolation layer <NUM> can have the characteristics of a flatter surface.

Referring to <FIG>, the sidewall layer <NUM> is removed (see <FIG>) to form a gap <NUM> between the first isolation layer <NUM> and the insulating layer <NUM>.

A method for removing the sidewall layer <NUM> (see <FIG>) includes: providing a plasma source, causing an ion beam generated by the plasma source to react with the sidewall layer <NUM> after passing through the first isolation layer <NUM> and form reaction byproducts, and discharging at least part of the reaction byproducts through the first isolation layer <NUM>. Compared with a wet process, the above method has the advantages of fewer residues and higher cleanliness when used for removing the sidewall layer <NUM>.

In the present embodiment, oxygen is used as the plasma source, and the process steps for removing the sidewall layer <NUM> include: generating an ion beam based on the oxygen plasma source, and causing the ion beam to pass through the first isolation layer <NUM> through the holes in the first isolation layer <NUM> and react with the sidewall layer <NUM> (see <FIG>), so that the sidewall layer <NUM> is thermally decomposed to produce reaction byproducts such as carbon dioxide, carbon monoxide, water, methane and the like. Gases such as carbon dioxide, carbon monoxide, water and methane can pass through the holes in the first isolation layer <NUM> to be discharged.

A flow rate of oxygen is within a range of <NUM> sccm to <NUM> sccm. When the flow rate of oxygen is within the above range, oxygen can react sufficiently with the material of the sidewall layer <NUM>, so that the sidewall layer <NUM> can be more completely removed; and the first isolation layer <NUM> can be prevented from major damage, thus ensuring that the first isolation layer <NUM> has a high stability.

A radio frequency power is within a range of 500W to 1000W. When the radio frequency power is within the above range, the ion beam has sufficient energy to completely remove the sidewall layer <NUM>; and major damage to the first isolation layer <NUM> can also be prevented, ensuring that the first isolation layer <NUM> has a high stability.

Referring to <FIG>, a second isolation layer <NUM> is formed on the surface of the first isolation layer <NUM>. A density of the second isolation layer <NUM> is greater than that of the first isolation layer <NUM>.

It can be understood that, in order to make more ion beams pass through the first isolation layer <NUM>, so that the sidewall layer <NUM> is removed more completely, and the first isolation layer <NUM> has a lower density; after the removal of the sidewall layer <NUM>, formation of the denser second isolation layer <NUM> on the surface of the first isolation layer <NUM> can increase the density of the first isolation layer <NUM>, thereby improving the firmness and stability of the first isolation layer <NUM>.

The thickness of the second isolation layer <NUM> is greater than the thickness of the first isolation layer <NUM>, which can further improve the firmness of the first isolation layer <NUM>. Preferably, a ratio of the thickness of the second isolation layer <NUM> to the thickness of the first isolation layer <NUM> is within a range of <NUM>:<NUM> to <NUM>:<NUM>. When the ratio of the thickness of the second isolation layer <NUM> to the thickness of the first isolation layer <NUM> is within the above range, the second isolation layer <NUM> can well reinforce the first isolation layer <NUM>. In addition, the second isolation layer <NUM> can occupy a reasonable area on the isolation structure <NUM>, so that the second isolation layer <NUM> can completely expose the surface of the electrical contact layer <NUM>, so as to increase the contact area between the electrical contact layer <NUM> and the subsequently-formed conducting layer.

In the present embodiment, the second isolation layer <NUM> and the first isolation layer <NUM> are made of a same material, which can ensure that the second isolation layer <NUM> and the first isolation layer <NUM> can be more closely attached, thereby further improving the reinforcement effect of the second isolation layer <NUM>. For example, the second isolation layer <NUM> and the first isolation layer <NUM> are both made of silicon dioxide. In other embodiments, the second isolation layer <NUM> may also be made of a different material from the first isolation layer <NUM>; for example, the second isolation layer <NUM> may be made of silicon nitride.

The second isolation layer <NUM> is formed by an atomic layer deposition process or a chemical vapor deposition process with better step coverage.

Referring to <FIG>, the first isolation layer <NUM> and the second isolation layer <NUM> located at the bottom of the through hole <NUM> and the top surface of the insulating layer <NUM> are removed.

In the present embodiment, a dry etching method is carried out to remove part of the first isolation layer <NUM> and part of the second isolation layer <NUM>.

After the removal of the part of the first isolation layer <NUM> and the part of the second isolation layer <NUM>, the remaining first isolation layer <NUM> and the remaining second isolation layer <NUM> expose the entire surface of the electrical contact layer <NUM>, thereby increasing the contact area between the subsequently-formed conducting layer and the electrical contact layer <NUM> and reducing the contact resistance.

In other embodiments, the remaining first isolation layer <NUM> and the remaining second isolation layer <NUM> may also expose only part of the surface of the electrical contact layer <NUM>.

Referring to <FIG>, a barrier layer <NUM> covering the sidewall of the through hole <NUM> is deposited.

The barrier layer <NUM> is configured to block mutual diffusion between atoms in the subsequently-formed conducting layer and atoms in the second isolation layer <NUM>, and meanwhile can also increase the adhesion between the conducting layer and the second isolation layer <NUM>, thereby improving the stability and firmness of the subsequently-formed conducting layer.

In the present embodiment, the barrier layer <NUM> is also located at the bottom of the through hole <NUM>. The barrier layer <NUM> can also block the mutual diffusion between the atoms in the subsequently-formed conducting layer and atoms in the electrical contact layer <NUM>, and meanwhile can also increase the adhesion between the conducting layer and the electrical contact layer <NUM>.

The barrier layer <NUM> is made of tantalum, tantalum nitride, ruthenium, or rhenium.

In the present embodiment, the barrier layer <NUM> is formed by an atomic layer deposition process.

Referring to <FIG>, a conducting layer <NUM> filling the through hole <NUM> (see <FIG>) is formed, and the conducting layer <NUM> is electrically connected to the electrical contact layer <NUM>. The conducting layer <NUM> is also higher than the top of the insulating layer <NUM>.

As an interconnection line in the semiconductor structure, the conducting layer <NUM> connects the structures in the base <NUM> together according to design requirements to achieve specific functions.

In the present embodiment, the conducting layer <NUM> is made of copper, gold, silver, titanium or tungsten.

In the present embodiment, the conducting layer <NUM> is formed by a chemical vapor deposition process. In other embodiments, a physical vapor deposition process may also be carried out to form the conducting layer <NUM>.

Referring to <FIG>, planarization is performed to remove part of the conducting layer <NUM>, part of the insulating layer <NUM>, part of the first isolation layer <NUM> and part of the second isolation layer <NUM> which are higher than the gap <NUM>.

It should be noted that during the planarization, the process should be stopped at a position higher than the gap <NUM>, so as to ensure that the gap <NUM> is still in a sealed state.

In the present embodiment, the planarization is performed by chemical mechanical polishing.

In other embodiments, if the gap formed is located on the entire sidewall of the insulating layer <NUM>; that is, in a direction perpendicular to the surface of the base <NUM>, the gap is as high as the insulating layer <NUM>; then, during the planarization, in order to ensure the tightness of the gap, only the conducting layer <NUM> higher than the gap may be removed, while the insulating layer <NUM>, the first isolation layer <NUM>, the second isolation layer <NUM>, and the barrier layer <NUM> are retained.

In summary, in the present embodiment, the sidewall layer covered by the first isolation layer is removed by a plasma process, thereby forming a gap. A process step of sealing the gap is not required, so that the gap has a larger size and high stability, which can effectively reduce the parasitic capacitance of the semiconductor structure.

A second embodiment of the present disclosure provides a semiconductor structure. <FIG> is a schematic diagram of the semiconductor structure according to the second embodiment of the present disclosure. Referring to <FIG>, the semiconductor structure includes: a base <NUM> with an electrical contact layer <NUM> therein; an insulating layer <NUM> located on the base <NUM>, the insulating layer <NUM> having a conducting layer <NUM> therein, and the conducting layer <NUM> being electrically connected to the electrical contact layer <NUM>; and a first isolation layer <NUM>, the first isolation layer being located between the insulating layer <NUM> and the conducting layer <NUM>, the first isolation layer <NUM> being also located on part of sidewalls of the insulating layer <NUM>, a gap <NUM> existing between the insulating layer <NUM> and the first isolation layer <NUM>, and the gap <NUM> being sealed by the first isolation layer <NUM>.

A detailed description will be given below in conjunction with the drawings.

Referring to <FIG>, the base <NUM> may include structures such as wordlines, bitlines, sources, drains and the like. The base <NUM> may be made of silicon, sapphire, silicon carbide, gallium arsenide, aluminum nitride, zinc silicon oxide, or the like.

The electrical contact layer <NUM> is configured to achieve electrical connection between an internal structure of the base <NUM> and the conducting layer <NUM>. In an example, the conducting layer <NUM> may be electrically connected to the bitlines in the base <NUM> through the electrical contact layer <NUM>. In the present embodiment, the electrical contact layer <NUM> is made of copper. In other embodiments, the electrical contact layer <NUM> may also be made of a conducting material, such as polysilicon, tungsten, titanium, or the like.

The base <NUM> further has isolation structures <NUM> therein, and the isolation structure <NUM> is configured to isolate adjacent electrical contact layers <NUM>. In the present embodiment, the isolation structure <NUM> is made of silicon oxide. In other embodiments, the isolation structure <NUM> may also be made of an insulating material such as silicon carbide, silicon nitride, or the like.

The insulating layer <NUM> is configured to isolate adjacent conducting layers <NUM>.

A width of the insulating layer <NUM> is greater than or equal to one-half of a width of the isolation structure <NUM> and less than or equal to the width of the isolation structure <NUM>. When the width of the insulating layer <NUM> is within the above range, the first isolation layer <NUM> and the second isolation layer <NUM> can be well supported and the stability of the semiconductor structure can be improved; and moreover enough space can also be reserved for the gap <NUM>, the first isolation layer <NUM> and the second isolation layer <NUM>, so that the gap <NUM>, the first isolation layer <NUM> and the second isolation layer <NUM> can be located on the isolation structure <NUM>, and the entire surface of the electrical contact layer <NUM> can be exposed to increase the contact area between the conducting layer <NUM> and the electrical contact layer <NUM>.

The insulating layer <NUM> is made of silicon dioxide, silicon nitride, or silicon carbide.

The conducting layer <NUM> is made of copper, gold, silver, titanium, or tin.

The first isolation layer <NUM> is configured to seal the gap <NUM>. Since the first isolation layer <NUM> is also located on the top of the gap <NUM>, the gap <NUM> does not need other isolation layers for sealing.

The first isolation layer <NUM> is also located on the isolation structure <NUM> and exposes the entire surface of the electrical contact layer <NUM> to increase the contact area between the electrical contact layer <NUM> and the conducting layer <NUM> and reduce the contact resistance.

The second isolation layer <NUM> covers the surface of the first isolation layer <NUM>, and a density of the second isolation layer <NUM> is greater than that of the first isolation layer <NUM>.

It can be understood that, during the formation of the gap <NUM>, in order to make more ion beams pass through the first isolation layer <NUM>, so that the first isolation layer <NUM> has a lower density; after the formation of the gap <NUM>, the denser second isolation layer <NUM> can increase the density of the first isolation layer <NUM>, thereby improving the firmness and stability of the first isolation layer <NUM>.

In a direction parallel to the surface of the base <NUM>, the thickness of the second isolation layer <NUM> is greater than the thickness of the first isolation layer <NUM>. In this way, the stability of the first isolation layer <NUM> can be improved, and problems such as collapse of the first isolation layer <NUM> can be avoided. Preferably, a ratio of the thickness of second isolation layer <NUM> to the thickness of the first isolation layer <NUM> is within a range of <NUM>:<NUM> to <NUM>:<NUM>. When the ratio of the thickness of the second isolation layer <NUM> to the thickness of the first isolation layer <NUM> is within the above range, the second isolation layer <NUM> can well reinforce the first isolation layer <NUM>. In addition, the second isolation layer <NUM> can occupy a reasonable area on the isolation structure <NUM>, so that the second isolation layer <NUM> can completely expose the surface of the electrical contact layer <NUM>, so as to increase the contact area between the electrical contact layer <NUM> and the conducting layer <NUM>.

The first isolation layer <NUM> and the second isolation layer <NUM> are both located on the base <NUM> other than the electrical contact layer <NUM> and expose the entire surface of the electrical contact layer <NUM>. In this way, the contact area between the conducting layer <NUM> and the electrical contact layer <NUM> can be increased, thereby reducing the contact resistance and increasing the operating speed of the semiconductor structure.

In the present embodiment, the first isolation layer <NUM> is made of silicon dioxide. In other embodiments, the first isolation layer <NUM> may also be made of a silicon-oxyhydrocarbon. The silicon dioxide or silicon-oxyhydrocarbon is hardly decomposed under the action of oxygen plasma and has good stability.

In the present embodiment, a width of the gap <NUM> may be within a range of <NUM> to <NUM>. When the width of the gap <NUM> is within the above range, the parasitic capacitance can be effectively reduced, and the stability of the first isolation layer <NUM> and the second isolation layer <NUM> can be ensured.

In a direction perpendicular to the surface of the base <NUM>, a ratio of a height of the gap <NUM> to a height of the insulating layer <NUM> is greater than or equal to <NUM>. The height of the gap <NUM> is within the above range; that is, the gap <NUM> occupies a large space and can reduce the parasitic capacitance to a great extent.

Further, in the direction perpendicular to the surface of the base <NUM>, the ratio of the height of the gap <NUM> to the height of the insulating layer <NUM> is greater than or equal to <NUM>. That is, the contact area between the first isolation layer <NUM> and the insulating layer <NUM> is greater than or equal to <NUM> of a total area of the sidewall of the insulating layer <NUM>. If the contact area is within the above range, the first isolation layer <NUM> can be more closely attached to the sidewall of the insulating layer <NUM>, thereby ensuring that the first isolation layer <NUM> can completely seal the top of the gap <NUM>, so that the gap <NUM> has good airtightness and stability. In this way, the parasitic capacitance can be reduced effectively.

The semiconductor structure further includes a barrier layer <NUM> located between the first isolation layer <NUM> and the conducting layer <NUM>. In the present embodiment, the barrier layer <NUM> covers the surface of the second isolation layer <NUM>. The barrier layer <NUM> is configured to block mutual diffusion between atoms of the conducting layer <NUM> and atoms in the second isolation layer <NUM> and increase the adhesion between the barrier layer <NUM> and the second isolation layer <NUM>.

In the present embodiment, the barrier layer <NUM> also covers the surface of the electrical contact layer <NUM>. The barrier layer <NUM> is also configured to block the mutual diffusion between the atoms in the conducting layer <NUM> and atoms in the electrical contact layer <NUM> and increase the adhesion between the barrier layer <NUM> and the electrical contact layer <NUM>.

Claim 1:
A manufacturing method of a semiconductor structure, comprising:
providing a base (<NUM>) with an electrical contact layer (<NUM>) therein;
forming an insulating layer (<NUM>) on the base (<NUM>), the insulating layer (<NUM>) having a through hole (<NUM>) penetrating the insulating layer (<NUM>), and the through hole (<NUM>) exposing a surface of the electrical contact layer (<NUM>);
forming a sidewall layer (<NUM>) on a sidewall of the through hole (<NUM>), a top surface of the sidewall layer (<NUM>) being lower than a top surface of the insulating layer (<NUM>);
forming a first isolation layer (<NUM>), the first isolation layer (<NUM>) covering a surface of the sidewall layer (<NUM>) and an exposed surface of the insulating layer (<NUM>);
removing the sidewall layer (<NUM>) to form a gap (<NUM>) between the first isolation layer (<NUM>) and the insulating layer (<NUM>);
forming a second isolation layer (<NUM>) on a surface of the first isolation layer (<NUM>), a density of the second isolation layer (<NUM>) being greater than that of the first isolation layer (<NUM>);
removing the first isolation layer (<NUM>) and the second isolation layer (<NUM>) located at the bottom of the through hole (<NUM>) and the top surface of the insulating layer (<NUM>); and
forming a conducting layer (<NUM>) filling the through hole (<NUM>), the conducting layer (<NUM>) being electrically connected to the electrical contact layer (<NUM>).