Patent Description:
<FIG> illustrates a cross-sectional view of a related art BEOL interconnect structure of a semiconductor device.

The BEOL interconnect structure shown in <FIG> includes a plurality of metal structures formed in a plurality of inter-metal layers stacked in a vertical direction. These metal structures include a <NUM>st via <NUM> formed in a <NUM>st inter-metal layer <NUM>, a metal pattern <NUM> formed in a <NUM>nd inter-metal layer <NUM> layered above the <NUM>st inter-metal layer <NUM> with an etch stop layer <NUM> therebetween, and a <NUM>nd via <NUM> formed above the metal pattern <NUM> in the <NUM>nd inter-metal layer <NUM>. The metal structures also include a supervia <NUM> penetrating the <NUM>st and <NUM>nd inter-metal layers <NUM> and <NUM>. A barrier metal pattern <NUM> is formed in the <NUM>st and <NUM>nd inter-metal layers to contact outer surfaces of the metal structures to facilitate adhesion of the metal structures with the <NUM>st and <NUM>nd inter-metal layers <NUM> and <NUM>, respectively.

The BEOL interconnect structure of <FIG> is provided in a semiconductor device to connect circuit elements (not shown) formed above, in-between and/or below the <NUM>st and <NUM>nd inter-metal layers <NUM> and <NUM>.

It is known that a supervia such as the supervia <NUM> has an advantage over a combination of a metal pattern and regular vias such as the metal pattern <NUM> and the <NUM>st and <NUM>nd vias <NUM> and <NUM>, in terms of area gain and reduced barrier metal resistance. This is because the supervia is able to interconnect two circuit elements at one connection penetrating through one or more layers such as the inter-metal layer <NUM> and <NUM>.

However, the supervia is formed in a supervia hole having a higher aspect ratio of width and depth compared to a regular via hole, and thus, it is difficult to form the supervia without concerns of misalignment with a lower metal pattern and sufficient metal-fill in the supervia hole.

<CIT> discloses metal interconnections formed integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

<CIT> discloses a conductive interconnect including trenches and vias are formed in a workpiece by applying a dielectric film stack over the workpiece, and thereafter applying photoresist over the film stack. Trenches are patterned in the photoresist, wherein the trenches are in segments disposed end-to-end to each other. The segments are longitudinally spaced apart from each other at locations where the vias are to be located. The trenches are etched into the dielectric film stack, and then filled with conductive material to form metal line segments. Vias are patterned in the gaps separating the adjacent ends of the longitudinally-related lines. The patterned vias are etched and then filled with a conductive material, with the ends of the adjacent line segments serving to accurately locate the vias, in a direction along the lengths of the trenches.

Thus, there is demand of an improved supervia structure and a method of forming the same.

Information disclosed in this Background section has already been known to the inventors before achieving the embodiments of the present application or is technical information acquired in the process of achieving the embodiments described herein. Therefore, it may contain information that does not form prior art that is already known to the public.

The disclosure provides semiconductor device structures having via structures for a via and a supervia having improved alignment and metal fill characteristics and a method of designing the via structures.

According to embodiments, there is provided a via structure according to claim <NUM>.

According to embodiments, there is provided a method of forming a via structure according to claim <NUM>.

The via structure such as a via or a supervia formed according to the above embodiments is characterized in that one vertical side of the via structure does not contact a barrier metal pattern while an opposite vertical side of the via structure contacts a barrier metal pattern formed in an inter-metal layer. The method of forming this via structure according to the above embodiments is characterized in that a wide-width trench having a lower width/depth aspect ratio is used to form a via metal from which the via structure is patterned, and a self-aligned via structure can be achieved by using an additional photolithography masking process as described in the following descriptions, thereby enabling easy formation of the via structure preventing insufficient metal fill and misalignment with a lower metal pattern in a BEOL interconnect structure.

Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:.

The embodiments described herein are all example embodiments, and thus, the inventive concept is not limited thereto, and may be realized in various other forms. Each of the embodiments provided in the following description is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the inventive concept. For example, even if matters described in a specific example or embodiment are not described in a different example or embodiment thereto, the matters may be understood as being related to or combined with the different example or embodiment, unless otherwise mentioned in descriptions thereof. In addition, it should be understood that all descriptions of principles, aspects, examples, and embodiments of the inventive concept are intended to encompass structural and functional equivalents thereof. In addition, these equivalents should be understood as including not only currently well-known equivalents but also equivalents to be developed in the future, that is, all devices invented to perform the same functions regardless of the structures thereof. For example, a MOSFET described herein may take a different type or form of a transistor as long as the inventive concept can be applied thereto.

It will be understood that when an element, component, layer, pattern, structure, region, or so on (hereinafter collectively "element") of a semiconductor device is referred to as being "over," "above," "on," "below," "under," "beneath," "connected to" or "coupled to" another element the semiconductor device, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or an intervening element(s) may be present. In contrast, when an element of a semiconductor device is referred to as being "directly over," "directly above," "directly on," "directly below," "directly under," "directly beneath," "directly connected to" or "directly coupled to" another element of the semiconductor device, there are no intervening elements present. Like numerals refer to like elements throughout this disclosure.

Spatially relative terms, such as "over," "above," "on," "upper," "below," "under," "beneath," "lower," and the like, may be used herein for ease of description to describe one element's relationship to another element(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of a semiconductor device in use or operation in addition to the orientation depicted in the figures. For example, if the semiconductor device in the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the term "below" can encompass both an orientation of above and below. The semiconductor device may be otherwise oriented (rotated <NUM> degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It will be understood that, although the terms first (<NUM>st), second (<NUM>nd), third (<NUM>rd), fourth (<NUM>th) etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept.

It will be also understood that, even if a certain step or operation of manufacturing an inventive apparatus or structure is described later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

Many embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of the embodiments (and intermediate structures). Thus, the embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present inventive concept. Further, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

For the sake of brevity, conventional elements of semiconductor devices including BEOL elements may or may not be described in detail herein.

<FIG> illustrate a method of manufacturing a supervia for a semiconductor device structure of a semiconductor device, according to embodiments.

Referring to <FIG>, a BEOL interconnect structure includes <NUM>st to <NUM>rd inter-metal layers <NUM>, <NUM> and <NUM> stacked in this order from bottom. The BEOL interconnect structure further include a lower metal pattern <NUM> formed in the <NUM>st inter-metal layer and a plurality of vias <NUM> formed in the <NUM>st and <NUM>nd inter-metal layers <NUM> and <NUM> to connect semiconductor circuit elements (not shown) formed above, in between and/or below the <NUM>st to <NUM>rd inter-metal layers <NUM>, <NUM> and <NUM>. A barrier metal pattern <NUM> is formed in the <NUM>st and <NUM>nd inter-metal layers to contact outer surfaces of the lower metal pattern <NUM> and the vias <NUM> to support adhesion of these metal structures with the <NUM>st and <NUM>nd inter-metal layers <NUM> and <NUM>. The barrier metal pattern may be formed of at least one of titanium (Ti), titanium oxide (TiO) and tantalum (Ta), not being limited thereto.

Each of the <NUM>st to <NUM>rd inter-metal layers <NUM> to <NUM> may include a dielectric material such as a low-k material, and thus, may be referred to as an inter-metal dielectric (IMD) layer. The low-k material includes at least Si, C, O, H (SiCOH). However, the inventive concept is not limited thereto, and thus, different types of material may be used for the inter-metal layer.

<NUM>st to <NUM>rd etch stop layers <NUM>, <NUM> and <NUM> are formed underneath the <NUM>st inter-metal layer <NUM> and between the <NUM>st to <NUM>rd inter-metal layers <NUM>, <NUM> and <NUM>, respectively, to stop a later etching processes performed thereat. Each of the <NUM>st to <NUM>rd etch stop layers <NUM>, <NUM> and <NUM> may include two layers respectively formed of aluminum nitride (AlN) and oxide doped carbide (ODC), not being limited thereto, according to an embodiment. The ODC layer may be used as a hermetic barrier against moisture.

<FIG> shows a photolithography masking process in which a <NUM>st mask <NUM> is deposited above a top surface of the initial semiconductor device structure, which is a top surface of the <NUM>rd inter-metal layer <NUM>, and then, a section of the <NUM>st mask <NUM> is patterned to provide a space for a follow-on etching process on the <NUM>rd inter-metal layer <NUM>.

The <NUM>st mask <NUM> may be formed of, for example, a metal hard mask layer of titanium nitride (TiN) and a block cut hard mask layer of silicon oxynitride (SiON) or silicon dioxide (SiO<NUM>) above the metal hard mask layer.

Referring to <FIG>, a section of the <NUM>rd inter-metal layer <NUM> is etched down from its top surface using the <NUM>st mask <NUM> remaining after the photolithography masking process is performed thereon as shown in <FIG>. For this etching process, dry etching may be used for example, not being limited thereto. The dry etching on the <NUM>rd inter-metal layer <NUM> may stop at the <NUM>rd etch stop layer <NUM>, and then, wet etching may be performed to remove the <NUM>rd etch stop layer <NUM> formed below the etched section of the <NUM>rd inter-metal layer <NUM>, thereby to form a <NUM>st trench T1 exposing a section of a top surface of the <NUM>nd inter-metal layer <NUM>.

<FIG> shows that the <NUM>st trench T1 formed in the previous step of <FIG> is filled with a <NUM>nd mask <NUM> that may be formed of silicon carbide (SiC), not being limited thereto. The <NUM>nd mask <NUM> is extended to and above top surfaces of the <NUM>st mask <NUM> remaining after the etching process in <FIG>, and then planarized by, for example, chemical mechanical planarization (CMP). This <NUM>nd mask <NUM> is formed to etch at least two supervia holes as describe below. According to an embodiment, the <NUM>nd mask <NUM> is formed using a spin-on-hardmask (SOH) process.

After the planarization of the <NUM>nd mask <NUM>, another photolithography masking is performed, in which a <NUM>rd mask <NUM> is layered on the <NUM>nd mask <NUM>, and then, is patterned to form two openings H1 and H2 through which two sections of a top surface of the <NUM>nd mask <NUM> are exposed. Here, like the <NUM>st mask <NUM>, the <NUM>rd mask <NUM> may also be formed of, for example, a metal hard mask layer of TiN and a block cut hard mask layer of SiON or SiO<NUM> above the metal hard mask layer.

Referring to <FIG>, the <NUM>nd mask <NUM> and the <NUM>nd inter-metal layer <NUM> are etched down from the two openings H1 and H2 using the <NUM>rd mask <NUM>, remaining after the photolithography masking process in <FIG>, and the <NUM>st mask <NUM> remaining after the photolithography masking process in <FIG>. This etching process, referred to as supervia etching, may also be performed by dry etching and/or wet etching like the previous etching process described in reference to <FIG>. As shown in <FIG>, this supervia etching may be performed on two sections at the <NUM>nd mask <NUM> below the two openings H1 and H2, and continue to etch corresponding two sections at the <NUM>nd inter-metal layer <NUM> and corresponding two sections at the <NUM>nd etch stop layer <NUM> until a top surface of the lower metal pattern <NUM> is exposed. By this supervia etching, two supervia holes SH1 and SH2 are formed to penetrate the <NUM>rd inter-metal layer <NUM>, the <NUM>nd inter-metal layer <NUM> and the <NUM>nd etch stop layer <NUM> below the two openings H1 and H2. Further, this supervia etching forms two small holes R1 and R2 connected to the two supervia holes SH1 an SH2 to expose the top surface of the lower metal pattern <NUM> therethrough. It is understood here that the <NUM>nd etch stop layer <NUM> can be etched by wet etching.

<FIG> shows that, after forming the two supervia holes SH1 and SH2, the remaining section of the <NUM>nd mask <NUM> is removed by an ashing process such as plasma ashing, not being limited thereto, leaving the <NUM>nd inter-metal layer <NUM> between the two supervia holes SH1 and SH2 and below <NUM>nd mask <NUM> prior to its removal. For this ashing process, the <NUM>st mask <NUM> on the <NUM>rd inter-metal layer <NUM> is used for masking the <NUM>rd inter-metal layer <NUM> therebelow. The <NUM>rd mask <NUM> may also be removed in this ashing process and/or additional etching or an equivalent process.

<FIG> shows that, using the <NUM>st mask <NUM> on the <NUM>rd inter-metal layer <NUM>, the <NUM>nd inter-metal layer <NUM> between the two supervia holes SH1 and SH2 left from the ashing process in <FIG> is etched away, for example, by dry etching, and then, the <NUM>st mask <NUM> is stripped off. While the <NUM>nd inter-metal layer <NUM> between the two supervia holes SH1 and SH2 is etched away, the <NUM>nd etch stop layer <NUM> formed therebelow is left to facilitate self-aligning of a via metal to form supervias in a later step, according to an embodiment. Thus, through the etching process in <FIG>, a <NUM>nd trench T2 including the space corresponding to the supervia holes SH1 and SH2 at both sides is formed with its bottom surface including the <NUM>nd etch stop layer <NUM> and the top surface of the lower metal pattern <NUM> exposed through the two holes R1 and R2 in the etch stop layer <NUM> formed by the etching process in <FIG>.

<FIG> shows that a barrier metal pattern <NUM> is layered on the surface of the <NUM>nd trench T2 and extended to top surfaces of the <NUM>rd inter-metal layer <NUM> where the <NUM>st mask <NUM> is removed in the previous ashing and/or etching process of <FIG>, and then, a via metal <NUM> is deposited on the barrier metal pattern <NUM> to fill in the <NUM>nd trench T2 and cover the top surfaces of the <NUM>rd inter-metal layer <NUM>. Due to the apparently lower aspect ratio of width and depth of the <NUM>nd trench T2 than that of the related art supervia hole, the via metal <NUM> is easily filled in the <NUM>nd trench T2. Further, due to the two holes R1 and R2 in the etch stop layer <NUM> formed by the etching process in <FIG>, the space corresponding to supervia hole SH1 and SH2 in the <NUM>nd trench T2 are filled in with the via metal <NUM> in a self-aligning manner. According to embodiments, the barrier metal pattern <NUM> and the via metal <NUM> may be filled in the <NUM>nd trench T2 by metal chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), not being limited thereto.

According to an embodiment, the via metal <NUM> may be formed of at least one of ruthenium (Ru) and molybdenum (Mo) for a direct etching thereon to be performed in a later step.

The via metal <NUM> is further formed on the top surfaces of the <NUM>rd inter-metal layer <NUM> remaining after the etching process shown in <FIG>, and planarized at the top.

In <FIG>, a <NUM>th mask <NUM> is formed, for example, by photolithography masking, at two sections at the top surface of the via metal <NUM> corresponding to two sections where supervias are to be formed. And then, using the <NUM>th mask <NUM>, the via metal <NUM> and the barrier metal pattern <NUM> formed above the etch stop layer <NUM> are direct-etched, for example, by dry etching, to form a <NUM>rd trench T3 with desired supervias 204S1 and 204S2, below the <NUM>th mask <NUM>, self-aligned in the two holes R1 and R2, and expose the top surface of the <NUM>nd etch stop layer <NUM> layered on the lower metal pattern <NUM> between the two holes R1 and R2.

According to an embodiment, after the direct-etching process performed on the via metal <NUM> without using the conventional damascene process, a vertical side S1 of the supervia 204S1 and a vertical side S3 of the supervia 204S2 facing the <NUM>rd trench T3 do not contact any barrier metal pattern while another vertical side S2 of the supervia 204S1 and another vertical side S4 of the super via 204S2 contact the barrier metal pattern <NUM> formed in the <NUM>nd trench T2.

In <FIG>, the <NUM>rd trench T3 is filled by, for example, flowable CVD (FCVD) using SiCOH to form another inter-metal layer <NUM>, and the <NUM>th mask <NUM> is removed by, for example, dry etching, according to an embodiment.

The inter-metal layer <NUM> formed herein between the two supervias 204S1 and 204S2 may be a single layer, in which case the vertical side S1 of the supervia 204S1 and the vertical side S3 of the supervia 204S2 face a single inter-metal layer while the other vertical side S2 of the supervia 204S1 and the other vertical side S4 of the supervia 204S2 face two inter-metal layers, that is, the <NUM>nd and <NUM>rd inter-metal layers <NUM> and <NUM>, through the barrier metal pattern <NUM>, according to an embodiment.

According to the above-described method, the supervias 204S1 and 204S2 having a high aspect ratio are easily formed without a concern of reaching down to the lower metal pattern <NUM> to which the supervias 204S1 and 204S2 are intended to be connected. Further, due to the additional masking and etching process including the supervia etching step shown in <FIG> and <FIG>, the supervias 204S1 and 204S2 are self-aligned to prevent misalignment with the lower metal pattern <NUM>.

Referring back to <FIG> and <FIG>, the two openings H1 and H2 are patterned in the <NUM>rd mask <NUM> by a photolithography masking process and used to form the two supervia holes SH1 and SH2 where the two supervias 204S1 and 204S2 are formed through the following steps shown in <FIG>, according to an embodiment. However, the inventive concept is not limited thereto. According to embodiments, only one or more than two openings may be patterned in the <NUM>rd mask <NUM> and used to form only one or more than two supervia holes, thereby forming one supervia or more than two supervias.

<FIG> illustrates a semiconductor device structure having three supervias, according to an embodiment.

According to an embodiment, the supervia etching step performed in reference to <FIG> and <FIG> may be extended such that three openings instead of the two openings H1 and H2 are patterned in the <NUM>rd mask <NUM> by a photolithography masking process, and the <NUM>nd mask <NUM> and the <NUM>nd inter-metal layer <NUM> are etched using the three openings in the <NUM>rd mask <NUM> to form three supervia holes penetrating the <NUM>nd inter-metal layer <NUM> and three holes at the etch stop layer <NUM> opening the top surface of the lower metal pattern <NUM> through the three holes. After this supervia etching, the <NUM>st to <NUM>rd masks <NUM> to <NUM> may be removed by similar processes described above in reference to <FIG> and <FIG>. Next, the via metal <NUM> may be filled in the <NUM>nd trench T2 having the three holes at the etch stop layer <NUM> in a similar manner described above in reference to <FIG>. Subsequently, the <NUM>th mask <NUM> may be formed on three sections above the via metal <NUM> to correspond to the three holes at the etch stop layer <NUM>, and then, direct etching is applied to the via metal <NUM> from its top surface exposed between the three sections of the <NUM>th mask <NUM>, in a similar manner described above in reference to <FIG>.

As a result of the above process, an additional supervia 204S3 in addition to the two supervias 204S1 and 204S2 with two trenches T4 and T5 therebetween may be obtained as shown in <FIG>, according to an embodiment.

Meantime, as the direct etching is applied to the via metal <NUM> from its top surface exposed between the three sections of the <NUM>th mask <NUM> as describe above, the additional supervia 204S3 obtained by the direct etching does not contact any barrier metal pattern <NUM> at its two vertical sides S4 and S5 facing the two trenches T4 and T5, respectively.

After the three supervias 204S1 to 204S3 and the two trenches T4 and T5 are formed, an inter-metal layer <NUM> having low conformality such as silicon carbon nitride (SiCN) may be deposited in the two trenches T4 and T5 by plasma enhanced chemical vapor deposition (PECVD), according to an embodiment. Due to its less conformal characteristics, the inter-metal layer <NUM> may not fill the two trenches T4 and T5 entirely, and thus, an air gap AIR may be formed between the inter-metal layer <NUM> and the etch stop layer <NUM> at the bottom of the two trenches T4 and T5, according to an embodiment. With this air gap AIR formed between the supervias 204S1 to 204S3, possible capacitance between the supervias 204S1 to 204S3 may be lowered than when the two trenches T4 and T5 are filled in with other low-k materials such as SiCOH.

As the inter-metal layer <NUM> formed in the two trenches T4 and T5 may be a single layer, in which case the two vertical sides S4 and S5 of the supervia 204S3 faces a single inter-metal layer and the air gap AIR, according to an embodiment.

According to an embodiment, the above methods for forming supervias may also be applied to forming regular vias such as the vias <NUM> and <NUM> shown in <FIG>.

In the previous embodiments described in reference to <FIG>, the supervias 204S1 to 204S3 penetrating the <NUM>st and <NUM>nd inter-metal layers <NUM> and <NUM> are obtained for connection with the lower metal pattern <NUM>. However, when the <NUM>st to <NUM>rd masks <NUM> to <NUM> used for the supervia etching in <FIG> are formed on the <NUM>nd inter-metal layer <NUM>, instead of the <NUM>rd inter-metal layer <NUM>, to go through similar processes described in reference to <FIG>, a via <NUM>, which has a regular via structure, may be obtained as shown in <FIG>, according to an embodiment.

<FIG> illustrates a flowchart of a method of forming a via structure in reference to <FIG>, according to an embodiment.

In operation S20, a BEOL interconnect structure is provided on a substrate, where the BEOL interconnect structure includes <NUM>st to <NUM>rd inter-metal layers <NUM>, <NUM> and <NUM> stacked in this order, a lower metal pattern <NUM> formed in the <NUM>st inter-metal layer, and an etch stop layer <NUM> formed on a top surface of the lower metal pattern <NUM>, as shown in <FIG>.

In operation S30, photolithography masking process is performed such that a <NUM>st mask <NUM> is formed above the <NUM>rd inter-metal layer <NUM>, of which a section is patterned to provide a space for etching down the <NUM>rd inter-metal layer <NUM>, as shown in <FIG>.

In operation S40, a section of the <NUM>rd inter-metal layer <NUM> is etched down using the <NUM>st mask <NUM> patterned in the previous operation to form a <NUM>st trench T1, of which bottom and side surfaces are defined by a top surface of the <NUM>nd inter-metal layer <NUM>, the patterned <NUM>st mask <NUM> and the etched <NUM>rd inter-metal layer <NUM>, as shown in <FIG>.

In operation S50, the <NUM>st trench T1 is filled with a <NUM>nd mask <NUM> extended to and above top surfaces of the patterned <NUM>st mask <NUM> and then planarized, after which another photolithography masking process is performed to layer a <NUM>rd mask <NUM> on the <NUM>nd mask <NUM> and pattern the <NUM>rd mask <NUM> to have two openings H1 and H2 through which two sections of a top surface of the <NUM>nd mask <NUM> are exposed, as shown in <FIG>.

In operation S60, supervia etching is performed on the <NUM>nd mask <NUM> and the <NUM>nd inter-metal layer <NUM> from the two openings H1 and H2 using the patterned <NUM>rd mask <NUM> and the patterned <NUM>st mask <NUM> to form two supervia holes SH1 and SH2 penetrating the <NUM>rd inter-metal layer <NUM> and the <NUM>nd inter-metal layer <NUM>, and two small holes R1 and R2 connected to the two supervia holes SH1 and SH2 and penetrating the <NUM>nd etch stop layer <NUM> to expose a top surface of the lower metal pattern <NUM> through the two small holes R1 and R2, as shown in <FIG>.

In operation S70, the <NUM>nd and <NUM>rd masks <NUM>, <NUM> are removed by an ashing and/or etching process leaving the <NUM>nd inter-metal layer <NUM> between the two supervia holes SH1 and SH2 and below <NUM>nd mask <NUM> after its removal, as shown in <FIG>.

In operation S80, using the <NUM>st mask <NUM>, the <NUM>nd inter-metal layer <NUM> between the two supervia holes SH1 and SH2 and above the <NUM>nd etch stop layer <NUM> between the small holes R1 and R2 is etched away, and then, the <NUM>st mask <NUM> is stripped off, by which a <NUM>nd trench T2 including the supervia holes SH1 and SH2 is formed with its bottom surface defined by the <NUM>nd etch stop layer <NUM> and the top surface of the lower metal pattern <NUM> exposed through the two small holes R1 and R2 at the <NUM>nd etch stop layer <NUM>, as shown in <FIG>.

In operation S90, a barrier metal pattern <NUM> is layered on the <NUM>nd trench T2, and then, a via metal <NUM> is deposited on the barrier metal pattern <NUM> to fill in the <NUM>nd trench T2. Due to the apparently lower aspect ratio of width and depth of the <NUM>nd trench T2 than that of the related art supervia hole, the via metal <NUM> is easily filled in the <NUM>nd trench T2. Further, due to the two holes R1 and R2 at the etch stop layer <NUM> formed by the etching process in <FIG>, the supervia hole SH1 and SH2 in the <NUM>nd trench T2 are also filled in with the via metal <NUM> in a self-aligning manner, as shown in <FIG>.

In operation S100, a <NUM>th mask <NUM> is formed on two sections at the top surface of the via metal <NUM>, and then, using the <NUM>th mask <NUM>, the via metal <NUM> is direct-etched to form a <NUM>rd trench T3 having supervias 204S1 and 204S2, below the <NUM>th mask <NUM>, self-aligned in the two holes R1 and R2, as shown in <FIG>.

In operation S110, the <NUM>rd trench T3 is filled out with another inter-metal layer <NUM>, and the <NUM>th mask <NUM> is removed to finish the BEOL interconnect structure including the two supervias 204S1 and 204S2, as shown in <FIG>.

The above operations of forming two supervias may also apply to forming three or more supervias as shown in <FIG>. That is, when the <NUM>rd mask <NUM> is patterned to have three openings instead of the two openings H1 and H2 in above operation S50, three supervias 204S1, 204S2 and 204S3 may be obtained through the subsequent operations, according to an embodiment. Similarly, when the <NUM>rd mask <NUM> is pattered to have only one opening in above operation S50, only one supervia may be obtained, according to an embodiment. Further, when the BEOL interconnect structure provided in operation S20 includes only the <NUM>st inter-metal layer <NUM>, instead of the <NUM>st to <NUM>rd inter-metal layers <NUM>, <NUM> and <NUM>, for the subsequent operations, a via structure formed according to the embodiment will be a regular via, according to an embodiment.

According to the above-described embodiments, a wide trench having a lower aspect ratio of width and depth is used to form a supervia structure from which a number of desired supervias can be obtained. Further, by using an additional photolithography masking process, a self-aligned supervia can be formed. In addition, by forming an air gap between supervias, occurrence of unwanted capacitance between the supervias may be prevented. The foregoing method of forming supervias may also apply to regular via structures.

<FIG> illustrates a schematic plan view of a semiconductor module according to an embodiment.

Referring to <FIG>, a semiconductor module <NUM> according to an embodiment may include a processor <NUM> and semiconductor devices <NUM> that are mounted on a module substrate <NUM>. The processor <NUM> and/or the semiconductor devices <NUM> may include one or more via or supervia structures described in the above embodiments.

<FIG> illustrates a schematic block diagram of an electronic system according to an embodiment.

Referring to <FIG>, an electronic system <NUM> in accordance with an embodiment may include a microprocessor <NUM>, a memory <NUM>, and a user interface <NUM> that perform data communication using a bus <NUM>. The microprocessor <NUM> may include a central processing unit (CPU) or an application processor (AP). The electronic system <NUM> may further include a random access memory (RAM) <NUM> in direct communication with the microprocessor <NUM>. The microprocessor <NUM> and/or the RAM <NUM> may be implemented in a single module or package. The user interface <NUM> may be used to input data to the electronic system <NUM>, or output data from the electronic system <NUM>. For example, the user interface <NUM> may include a keyboard, a touch pad, a touch screen, a mouse, a scanner, a voice detector, a liquid crystal display (LCD), a micro light-emitting device (LED), an organic light-emitting diode (OLED) device, an active-matrix light-emitting diode (AMOLED) device, a printer, a lighting, or various other input/output devices without limitation. The memory <NUM> may store operational codes of the microprocessor <NUM>, data processed by the microprocessor <NUM>, or data received from an external device. The memory <NUM> may include a memory controller, a hard disk, or a solid state drive (SSD).

At least the microprocessor <NUM>, the memory <NUM> and/or the RAM <NUM> in the electronic system <NUM> may include one or more via or supervia structures described in the above embodiments.

Claim 1:
A via structure comprising:
at least one <NUM>st inter-metal layer (<NUM>, <NUM>); and
a <NUM>st via structure (<NUM>) penetrating the at least one inter-metal layer (<NUM>, <NUM>, <NUM>; <NUM>, <NUM>, <NUM>),
wherein, in the at least one inter-metal layer (<NUM>, <NUM>, <NUM>; <NUM>, <NUM>, <NUM>), a <NUM>st vertical side (S1) of the <NUM>st via structure (<NUM>) does not contact a barrier metal pattern (<NUM>) while a <NUM>nd vertical side (S2) of the <NUM>st via structure (<NUM>) opposite to the <NUM>st vertical side (S1) of the <NUM>st via structure (<NUM>) contacts the barrier metal pattern (<NUM>) , wherein the at least one <NUM>st inter-metal layer (<NUM>, <NUM>) comprises at least two <NUM>st inter-metal layers (<NUM>, <NUM>) stacked in a vertical direction,
wherein the <NUM>st vertical side (S1) of the <NUM>st via structure (204S1) contacts only a single <NUM>nd inter-metal layer (<NUM>; <NUM>) other than the at least two <NUM>st inter-metal layers, and
wherein the <NUM>nd vertical side (S2) of the <NUM>st via structure (204S1) contacts the at least two <NUM>st inter-metal layers (<NUM>, <NUM>) through the barrier metal pattern (<NUM>),
further comprising a lower metal pattern (<NUM>) and an etch stop layer (<NUM>) formed on a top surface of the lower metal pattern (<NUM>),
wherein the etch stop layer (<NUM>) comprises a hole (R1) through which the top surface of the lower metal pattern (<NUM>) is exposed,
wherein the <NUM>st via structure (<NUM>) vertically lands on the top surface of the lower metal pattern (<NUM>) exposed through the hole (R1),
wherein the single <NUM>nd inter-metal layer (<NUM>; <NUM>) is formed on the etch stop layer (<NUM>).