Patent Description:
A bit line structure of a DRAM device may have a stacked structure including a first conductive pattern including doped polysilicon and a second conductive pattern including metal. The bit line structure may contact a recess of an active pattern to be electrically connected thereto, and a lower portion of a spacer structure on a sidewall of the bit line structure may be formed in the recess. If the bit line structure has a narrow width, current flowing therethrough may not be enough for proper operations of the device. However, increasing the width of the bit line structure may be limited due to the size of the recess.

United States Patent Application Publication <CIT> relates to a method of manufacturing a semiconductor device including forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact.

Various aspects and embodiments of the present invention are set out in the appended claims.

Example embodiments provide semiconductor devices having improved characteristics and methods of forming the same.

A semiconductor device according to the invention is presented in the independent claim. Embodiments of the invention are presented in the dependent claims.

In the semiconductor devices, currents may easily flow through the bit line structure, and thus the semiconductor devices including the bit line structure may have enhanced electrical characteristics.

The above and other aspects and features of methods of cutting a fine pattern, methods of forming active patterns using the same, and methods of manufacturing a semiconductor device using the same in accordance with example embodiments of the inventive concepts will become readily understood from detail descriptions that follow, with reference to the accompanying drawings. It will be understood that, although the terms "first," "second," and/or "third" may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Thus, a first element, component, region, layer or section discussed below could be termed a second or third element, component, region, layer or section without departing from the teachings of inventive concepts.

<FIG> and <FIG> are a plan view and a cross-sectional view, respectively, illustrating a semiconductor device in accordance with example embodiments of the inventive concepts. <FIG> includes cross-section views taken along lines A-A' and B-B' of <FIG>.

Hereinafter, in the specifications (and not necessarily in the claims), two directions substantially parallel to an upper surface of a substrate <NUM> and substantially perpendicular to each other may be referred to as first and second directions, respectively, a direction substantially parallel to the upper surface of the substrate <NUM> and having an acute angle with respect to the first and second directions may be referred to as a third direction, and a direction substantially parallel to the upper surface of the substrate <NUM> and substantially perpendicular to the third direction may be referred to as a fourth direction.

Referring to <FIG> and <FIG>, the semiconductor device includes a gate structure <NUM>, a bit line structure <NUM>, a first lower spacer structure <NUM>, an upper spacer structure, a contact plug structure, and a capacitor <NUM>. Additionally, the semiconductor device may include a second capping pattern <NUM>, an insulation structure, an etch stop layer <NUM>, and first to third insulating interlayers <NUM>, <NUM> and <NUM>.

For example, the substrate <NUM> may include silicon, germanium, silicon-germanium, or a III- V group compound semiconductor, such as GaP, GaAs, or GaSb. In some example embodiments, the substrate <NUM> may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

An isolation pattern <NUM> may be formed on the substrate <NUM>, and an active pattern <NUM> of which a sidewall is covered by the isolation pattern <NUM> may be defined on the substrate <NUM>. The isolation pattern <NUM> may include, for example, an oxide, e.g., silicon oxide. As used herein, "an element A covers an element B" (or similar language) may mean that the element A is on and overlaps the element B but does not necessarily mean that the element A covers the element B entirely. For example, the element A may cover only a portion of the element B.

In example embodiments, a plurality of active patterns <NUM> may be spaced apart from each other in each of the first and second directions, and each of the active patterns <NUM> may extend in the third direction to a certain length (e.g., a predetermined length). As used herein, "an element A extends in a direction X" (or similar language) may mean that the element A extends longitudinally in the direction X. In other words, the direction X is a length direction of the element A. In some embodiments, each of the active patterns <NUM> may extend in the third direction as illustrated in <FIG>.

The gate structure <NUM> may extend in the first direction through upper portions of the active pattern <NUM> and the isolation pattern <NUM>, and a plurality of gate structures <NUM> may be spaced apart from each other in the second direction. That is, the gate structure <NUM> may be buried at upper portions of the active pattern <NUM> and the isolation pattern <NUM>. The gate structure <NUM> may include a gate insulation layer <NUM>, a gate electrode <NUM> and a gate mask <NUM> sequentially stacked in a vertical direction that is substantially perpendicular to the upper surface of the substrate <NUM>.

The gate insulation layer <NUM> may be formed on a surface of the active pattern <NUM>, the gate electrode <NUM> may extend in the first direction on the gate insulation layer <NUM> and the isolation pattern <NUM>, and the gate mask <NUM> may cover an upper surface of the gate electrode <NUM>.

For example, the gate insulation layer <NUM> may include an oxide, e.g., silicon oxide, the gate electrode <NUM> may include a metal, e.g., tungsten, titanium, tantalum, etc., or a metal nitride, e.g., tungsten nitride, titanium nitride, tantalum nitride, etc., and the gate mask <NUM> may include a nitride, e.g., silicon nitride.

In example embodiments, the bit line structure <NUM> may extend in the second direction on the active pattern <NUM>, the isolation pattern <NUM> and the gate structure <NUM>, and a plurality of bit line structures <NUM> may be spaced apart from each other in the first direction. Each of the bit line structures <NUM> may contact a portion (e.g., a central or middle portion in the third direction) of an upper surface of the active pattern <NUM> and may contact portions of upper surfaces of the isolation pattern <NUM> and the gate structure <NUM> adjacent thereto in the second recess <NUM>. A portion of the bit line structure <NUM> in the second recess <NUM> may have a bottom surface lower than those of other portions of the bit line structure <NUM> at an outside of the second recess <NUM>, and the portion of the bit line structure <NUM> in the second recess <NUM> may be referred to as a lower portion thereof.

The bit line structure <NUM> includes a conductive structure <NUM>. The conductive structure <NUM> includes second and third conductive patterns <NUM> and <NUM> sequentially stacked (shown in, for example, <FIG>) or first and third conductive patterns <NUM> and <NUM> sequentially stacked (shown in, for example, <FIG>). A plurality of second conductive patterns <NUM> may be spaced apart from each other in each of the first and second directions. That is, most portions of each of the second conductive patterns <NUM> may be formed in the second recess <NUM>, and a portion thereof may protrude from the second recess <NUM> upwardly. Thus, most portions of each of the second conductive patterns <NUM> may form the lower portion of the bit line structure <NUM>. The first conductive pattern <NUM> may be formed at an outside of the second recess <NUM>.

The bit line structure <NUM> further includes a diffusion barrier <NUM>, a fourth conductive pattern <NUM> and a capping pattern <NUM>. The third conductive pattern <NUM> may extend in the second direction on the first and second conductive patterns <NUM> and <NUM> disposed in the second direction. In example embodiments, each of the first to third conductive patterns <NUM>, <NUM> and <NUM> may include, e.g., polysilicon doped with n-type impurities, and thus may be merged with each other. As used herein, "an element A is merged with an element B" (or similar language) may mean that the element A is physically connected to the element B.

Each of the diffusion barrier <NUM>, the fourth conductive pattern <NUM> and the first capping pattern <NUM> may extend in the second direction on the third conductive pattern <NUM>. For example, the diffusion barrier <NUM> may include a metal silicon nitride, e.g., titanium silicon nitride (TiSiN), the fourth conductive pattern <NUM> may include a metal, e.g., tungsten, copper, aluminum, titanium, tantalum, etc., and the first capping pattern <NUM> may include a nitride, e.g., silicon nitride.

The first lower spacer structure <NUM> may be formed in the second recess <NUM> and covers the lower portion of the bit line structure <NUM>, that is, most portions of a sidewall in the first direction of the second conductive pattern <NUM> included in the conductive structure <NUM>. The first lower spacer structure <NUM> includes a first lower spacer <NUM> contacting most portions of the sidewall of the second conductive pattern <NUM> and a bottom of the second recess <NUM>, second and third lower spacers <NUM> and <NUM> sequentially stacked on the first lower spacer <NUM>, and a fourth lower spacer <NUM> on the third lower spacer <NUM> and filling a remaining portion of the second recess <NUM>. Thus, a sidewall of the fourth lower spacer <NUM> may be covered by the third lower spacer <NUM>, a sidewall of the third lower spacer <NUM> may be covered by the second lower spacer <NUM>, a sidewall of the second lower spacer <NUM> may be covered by the first lower spacer <NUM>. The first lower spacer <NUM> separates the second, third, and fourth lower spacers <NUM>, <NUM>, <NUM> from the lower portion of the bit line structure <NUM>, and each of the second, third, and fourth lower spacers <NUM>, <NUM>, <NUM> is spaced apart from the lower portion of the bit line structure <NUM> as illustrated in <FIG>. As used herein, "an element A fills an element B" (or similar language) may mean that the element A is in the element B but does not necessarily mean that the element A fills the element B entirely.

The first lower spacer <NUM> includes a material not containing nitrogen, e.g., an oxide such as silicon oxide or silicon oxycarbide. The first lower spacer <NUM> is devoid of nitrogen. The second and fourth lower spacers <NUM> and <NUM> include a material different from the first lower spacer <NUM>, e.g., a nitride such as silicon nitride, and the third spacer <NUM> may include a material having a high etching selectivity with respect to the fourth lower spacer <NUM>, e.g., an oxide such as silicon oxide.

The upper spacer structure is formed on each of opposite sidewalls of other portions of the bit line structure <NUM> except for the lower portion thereof, and thus may extend in the second direction. That is, the first lower spacer structure <NUM> and the upper spacer structure are sequentially stacked in the vertical direction on the second recess <NUM>.

In example embodiments, the upper spacer structure may include a first upper spacer <NUM>, an air spacer <NUM>, a third upper spacer <NUM> and a fourth upper spacer <NUM> sequentially stacked in the first direction on each of opposite sidewalls of the bit line structure <NUM>. The opposite sidewalls of the bit line are spaced part from each other in the first direction. The first upper spacer <NUM> may contact each of the opposite sidewalls in the first direction of the bit line structure <NUM> except for the lower portion thereof, the air spacer <NUM> may contact a portion of an outer sidewall of the first upper spacer <NUM>, the third upper spacer <NUM> may contact an outer sidewall of the air spacer <NUM>, and the fourth upper spacer <NUM> may contact an upper surface of the first capping pattern <NUM>, an upper surface and an upper outer sidewall of the first upper spacer <NUM>, a top of the air spacer <NUM>, and an upper surface and an upper outer sidewall of the third upper spacer <NUM>. In some embodiments, the air spacer <NUM> is defined and surrounded by the first upper spacer <NUM> and the third upper spacer <NUM> as illustrated in <FIG>.

However, in an area where the sidewall extending in the first direction of the bit line structure <NUM> is covered by the second capping pattern <NUM>, the air spacer <NUM> and the third upper spacer <NUM> may be sequentially stacked in the first direction on the outer sidewall of the first upper spacer <NUM> and the fourth upper spacer <NUM> may not be formed.

In example embodiments, the first upper spacer <NUM> may have a cross-section in the first direction of an "L" shape. Thus, a lower surface of the first upper spacer <NUM> may contact an upper surface of the first lower spacer structure <NUM> and a bottom of the air spacer <NUM> may not contact the upper surface of the first lower spacer structure <NUM> due to the first upper spacer <NUM> on the second recess <NUM>. A lower surface of the third upper spacer <NUM> may contact an edge of an upper surface of the first lower spacer structure <NUM>.

In example embodiments, uppermost surfaces of the air spacer <NUM> and the third upper spacer <NUM> may be lower than an uppermost surface of the first upper spacer <NUM> and may be higher than an upper surface of the fourth conductive pattern <NUM>. As used herein, "a surface V is higher than a surface W" (or similar language) may mean that the surface W is closer than the surface V to a substrate, and the surface W is lower than the surface V relative to the substrate.

The first upper spacer <NUM> includes a material different from that of the first lower spacer <NUM>, e.g., a nitride such as silicon nitride. The air spacer <NUM> may include, for example, air. The third upper spacer <NUM> may include a nitride, e.g., silicon nitride. The fourth upper spacer <NUM> may include a nitride, e.g., silicon nitride, or an oxide, e.g., silicon oxide. In some embodiments, the air spacer <NUM> may not include a liquid or solid material therein and may be a void or cavity. In some embodiments, the air spacer <NUM> may include an inert gas (e.g., argon gas) or may be a vacuum.

The insulation structure including first, second and third insulation patterns <NUM>, <NUM> and <NUM> sequentially stacked in the vertical direction may be formed between the bit line structure <NUM> and portions of the active pattern <NUM> and the isolation pattern <NUM> at an outside of the second recess <NUM>. The second insulation pattern <NUM> may contact a lower surface of the first upper spacer <NUM> having a cross-section of an "L" shape, and the third insulation pattern <NUM> may contact a lower surface of the bit line structure <NUM>.

For example, each of the first and third insulation patterns <NUM> and <NUM> may include a nitride, e.g., silicon nitride, and the second insulation pattern <NUM> may include an oxide, e.g., silicon oxide.

The second capping pattern <NUM> may extend in the first direction to overlap the gate structure <NUM> in the vertical direction and may partially cover an outer sidewall of the upper spacer structure on the sidewall of the bit line structure <NUM> in the first direction. In example embodiments, a plurality of second capping patterns <NUM> may be spaced apart from each other in the second direction. For example, the second capping pattern <NUM> may include a nitride, e.g., silicon nitride.

The contact plug structure may include a lower contact plug <NUM>, an ohmic contact pattern <NUM>, a barrier layer <NUM> and an upper contact plug <NUM> sequentially stacked in the vertical direction.

The lower contact plug layer <NUM> may be formed on the third recess <NUM> on the active pattern <NUM> and the isolation pattern <NUM> between the bit line structures <NUM> neighboring in the first direction and the second capping patterns <NUM> neighboring in the second direction and may contact an outer sidewall of the third upper spacer <NUM> of the upper spacer structure and a sidewall of each of the second capping patterns <NUM>. Thus, a plurality of lower contact plugs <NUM> may be formed to be spaced apart from each other in each of the first and second directions. In example embodiments, the lower contact plug <NUM> may contact each of opposite ends in the third direction of each of the active patterns <NUM>. In example embodiments, an uppermost surface of the lower contact plug <NUM> may be lower than uppermost surfaces of the air spacer <NUM> and the third upper spacer <NUM>.

For example, the lower contact plug <NUM> may include polysilicon doped with impurities. An air gap (not shown) may be formed in the lower contact plug <NUM>.

The ohmic contact pattern <NUM> may be formed on the lower contact plug <NUM>. The ohmic contact pattern <NUM> may include, e.g., cobalt silicide, nickel silicide, etc..

The barrier layer <NUM> may be formed on an upper surface of the ohmic contact pattern <NUM> and a sidewall and an upper surface of the fourth upper spacer <NUM>. The barrier layer <NUM> may include a metal nitride, e.g., titanium nitride, tantalum nitride, tungsten nitride, etc..

The upper contact plug <NUM> may be formed on the barrier layer <NUM>. An upper surface of the upper contact plug <NUM> may be higher than upper surfaces of the bit line structure <NUM> and the second capping pattern <NUM>.

In example embodiments, a plurality of upper contact plugs <NUM> may be formed to be spaced apart from each other in the first and second directions and may be spaced apart from each other by the first and second insulating interlayers <NUM> and <NUM> sequentially stacked. The first insulating interlayer <NUM> may partially penetrate through an upper portion of the first capping pattern <NUM> of the bit line structure <NUM> and an upper portion of the upper spacer structure on the sidewall of the bit line structure <NUM>. For example, the first insulating interlayer <NUM> may include an insulation material having low gap-filling characteristics, and the second insulating interlayer <NUM> may include a nitride, e.g., silicon nitride.

In example embodiments, the upper contact plugs <NUM> may be arranged in a honeycomb pattern in a plan view. Each of the upper contact plugs <NUM> may have a shape of a circle, an ellipse, or a polygon in a plan view. The upper contact plug <NUM> may include a low resistance metal, e.g., tungsten, aluminum, copper, etc..

The capacitor <NUM> may include a lower electrode <NUM>, a dielectric layer <NUM> and an upper electrode <NUM> sequentially stacked on the upper contact plug <NUM>. In some embodiments, the lower and upper electrodes <NUM> and <NUM> may include the same material, e.g., doped polysilicon and/or a metal. For example, the dielectric layer <NUM> may include silicon oxide, a metal oxide, and/or a nitride such as silicon nitride, a metal nitride, and the metal may include, e.g., aluminum, zirconium, titanium, hafnium, etc..

The etch stop layer <NUM> may be formed between the dielectric layer <NUM> and the first and second insulating interlayers <NUM> and <NUM>, and may include, for example, a nitride, e.g., silicon nitride.

The third insulating interlayer <NUM> may be formed on the first and second insulating interlayers <NUM> and <NUM> and may cover the capacitor <NUM>. The third insulating interlayer <NUM> may include, for example, an oxide, e.g., silicon oxide.

The conductive structure <NUM> in the bit line structure <NUM> of the semiconductor device may include, e.g., polysilicon doped with n-type impurities, and the first lower spacer <NUM> covering at least a portion of the sidewall of the conductive structure <NUM>, that is, most portions of the sidewall of the second conductive pattern <NUM> (shown in, for example, <FIG>) may not include nitrogen but include an oxide such as silicon oxide or silicon oxycarbide. If the first lower spacer <NUM> includes nitrogen, electrons in the conductive structure <NUM> may be trapped in the first lower spacer <NUM>, and thus depletion regions may be generated at opposite sides of the conductive structure <NUM>. Thus, a portion of the conductive structure <NUM> through which currents may flow may be reduced so that the currents may not easily flow in the conductive structure <NUM>.

However, the first lower spacer <NUM> does not include nitrogen, and thus electrons may not be trapped in the first lower spacer <NUM> so that currents may easily flow in the conductive structure <NUM>.

<FIG> are views illustrating a method of manufacturing a semiconductor device, the method not being part of the present invention. Specifically, <FIG>, <FIG>, <FIG> and <FIG> are plan views, and each of <FIG>, <FIG>, <FIG> and <FIG> are cross-sectional views. <FIG>, <FIG>, <FIG>, <FIG>and <FIG> includes cross-sections taken along lines A-A' and B-B' of a corresponding plan view, and <FIG> are enlarged cross-sectional views of a region X of <FIG>.

Referring to <FIG> and <FIG>, active patterns <NUM> may be formed on a substrate <NUM>, and an isolation pattern <NUM> may be formed to cover sidewalls of the active patterns <NUM>.

An ion implantation process may be performed on the substrate <NUM> to form an impurity region (not shown), and the active pattern <NUM> and the isolation pattern <NUM> may be partially etched to form a first recess extending in the first direction.

A gate structure <NUM> may be formed in the first recess. The gate structure <NUM> may include a gate insulation layer <NUM> on a surface of the active pattern <NUM> exposed by the first recess, a gate electrode <NUM> on the gate insulation layer <NUM> to fill a lower portion of the first recess, and a gate mask <NUM> on the gate electrode <NUM> to fill an upper portion of the first recess. The gate structure <NUM> may extend in the first direction, and a plurality of gate structures <NUM> may be spaced apart from each other in the second direction.

For example, the gate insulation layer <NUM> may be formed by performing a thermal oxidation process on the surface of the active pattern <NUM> exposed by the first recess.

Referring to <FIG> and <FIG>, an insulation layer structure <NUM>, a first conductive layer <NUM> and a first mask <NUM> may be sequentially formed on the substrate <NUM>, and the first conductive layer <NUM> and the insulation layer structure <NUM> may be etched using the first mask <NUM> as an etching mask to form a first hole <NUM> exposing the active pattern <NUM>.

In example embodiments, the insulation layer structure <NUM> may include first, second and third insulation layers <NUM>, <NUM> and <NUM> sequentially stacked.

For example, the first conductive layer <NUM> may include, e.g., polysilicon doped with n-type impurities, and the first mask <NUM> may include a nitride, e.g., silicon nitride.

During the etching process, upper portions of the active pattern <NUM> and the isolation pattern <NUM> adjacent thereto exposed by the first hole <NUM>, and an upper portion of the gate mask <NUM> may be also etched to form a second recess. That is, a bottom of the first hole <NUM> may be referred to as a second recess.

In example embodiments, the first hole <NUM> may expose a portion (e.g., a central or middle portion in the third direction) of an upper surface of each of the active patterns <NUM> extending in the third direction, and thus a plurality of first holes <NUM> may be formed to be spaced apart from each other in the first and second directions. In some embodiments, a middle portion of the active pattern <NUM> in the third direction (i.e., a length direction of the active pattern <NUM>) may include an upper surface that is recessed toward the substrate <NUM> and defines the recess <NUM> as illustrated in <FIG> and <FIG>.

A second conductive layer <NUM> may be formed to fill the first hole <NUM>.

In example embodiments, the second conductive layer <NUM> may be formed by forming a preliminary second conductive layer on the active pattern <NUM>, the isolation pattern <NUM>, the gate mask <NUM> and the first mask <NUM> to fill the first hole <NUM> and by removing an upper portion of the preliminary second conductive layer through, for example, a CMP process and/or an etch back process. Thus, the second conductive layer <NUM> may have an upper surface substantially coplanar with an upper surface of the first conductive layer <NUM>. As used herein the term "and/or" includes any and all combinations of one or more of the associated listed items.

In example embodiments, a plurality of second conductive layers <NUM> may be spaced apart from each other in each of the first and second directions. The second conductive layer <NUM> may include, for example, polysilicon doped with n-type impurities, and may be merged to the first conductive layer <NUM>.

Referring to <FIG>, after removing the first mask <NUM>, a third conductive layer <NUM>, a diffusion barrier layer <NUM>, a fourth conductive layer <NUM> and a first capping layer <NUM> may be sequentially formed on the first and second conductive layers <NUM> and <NUM>.

The third conductive layer <NUM> may include, for example, polysilicon doped with n-type impurities, and may be merged with the first and second conductive layers <NUM> and <NUM>. The fourth conductive layer <NUM> may include, for example, a metal, e.g., tungsten.

Referring to <FIG> and <FIG>, the first capping layer <NUM> may be patterned to form a first capping pattern <NUM>, and the fourth conductive layer <NUM>, the diffusion barrier layer <NUM>, the third conductive layer <NUM>, the first and second conductive layers <NUM> and <NUM>, and the third insulation layer <NUM> may be sequentially etched using the first capping pattern <NUM> as an etching mask.

In example embodiments, the first capping pattern <NUM> may extend in the second direction on the substrate <NUM>, and a plurality of first capping patterns <NUM> may be formed to be spaced apart from each other in the first direction.

By the etching process, a second conductive pattern <NUM>, a third conductive pattern <NUM>, a diffusion barrier <NUM>, a fourth conductive pattern <NUM> and the first capping pattern <NUM> sequentially stacked may be formed on the active pattern <NUM>, the isolation pattern <NUM> and the gate mask <NUM> in the first hole <NUM>, and a third insulation pattern <NUM>, a first conductive pattern <NUM>, the third conductive pattern <NUM>, the diffusion barrier <NUM>, the fourth conductive pattern <NUM>, and the first capping pattern <NUM> may be sequentially stacked on the second insulation layer <NUM> of the insulation layer structure <NUM> at an outside of the first hole <NUM>.

As illustrated above, the first to third conductive layers <NUM>, <NUM> and <NUM> may be merged with each other, and thus the second and third conductive patterns <NUM> and <NUM> sequentially stacked and the first and third conductive patterns <NUM> and <NUM> sequentially stacked may each form one conductive structure <NUM>. Hereinafter, the conductive structure <NUM>, the diffusion barrier <NUM>, the fourth conductive pattern <NUM>, and the first capping pattern <NUM> sequentially stacked may be referred to as a bit line structure <NUM>.

In example embodiments, the bit line structure <NUM> may extend in the second direction on the substrate <NUM>, and a plurality of bit line structures <NUM> may be spaced apart from each other in the first direction. Each of the bit line structures <NUM> may contact a portion (e.g., a central or middle portion in the third direction) of each of the active patterns <NUM> through the first hole <NUM>, and thus may be electrically connected thereto.

Referring to <FIG>, a first spacer layer <NUM> may be formed on upper surfaces of the active pattern <NUM>, the isolation pattern <NUM> and the gate mask <NUM> exposed by the first hole <NUM>, a sidewall of the first hole <NUM>, and an upper surface of the second insulation layer <NUM> to cover the bit line structure <NUM>, second and third insulation layers <NUM> and <NUM> may be sequentially formed on the first spacer layer <NUM>, and a fourth lower spacer layer <NUM> may be formed on the third lower spacer layer <NUM> to fill the first hole <NUM>.

In example embodiments, the first lower spacer layer <NUM> may be formed by an atomic layer deposition (ALD) process. The first lower spacer layer <NUM> may include a material not containing nitrogen, e.g., silicon oxide, silicon oxycarbide, etc..

The second and fourth lower spacer layers <NUM> and <NUM> may include a material including nitride, e.g., silicon nitride, and the third lower spacer layer <NUM> may include a material having a high etching selectivity with respect to the fourth lower spacer layer <NUM>, e.g., an oxide such as silicon oxide.

Referring to <FIG>, first and second wet etching processes may be performed to partially etch the first to fourth lower spacer layers <NUM>, <NUM>, <NUM> and <NUM>.

In example embodiments, the first wet etching process may be performed using phosphoric acid (H<NUM>PO<NUM>) and SC1 solution. Thus, the fourth lower spacer layer <NUM> may be etched, and the third lower spacer layer <NUM> may serve as a stopper for the first wet etching process. The third lower spacer layer <NUM> may be partially etched by the SC1 solution, however, the second lower spacer layer <NUM> is formed under the third lower spacer layer <NUM>, and thus the sidewall of the bit line structure <NUM> may not be exposed by the first wet etching process.

If the first wet etching process is performed after forming the third and fourth lower spacer layers <NUM> and <NUM> without forming the first and second lower spacer layers <NUM> and <NUM>, the third lower spacer layer <NUM> may be removed by the SC1 solution to expose the sidewall of the bit line structure <NUM>, and the fourth conductive pattern <NUM> including a metal may be also damaged.

Additionally, during a high temperature process for forming the fourth lower spacer layer <NUM> on the sidewall of the bit line structure <NUM> having the third lower spacer layer <NUM> thereon, the metal such as tungsten included in the fourth conductive pattern <NUM> may move through the third lower spacer layer <NUM> including an oxide to the fourth lower spacer layer <NUM> including a nitride, and when an upper portion of the fourth lower spacer layer <NUM> is removed by the first wet etching process, the metal included in the fourth conductive pattern <NUM> may corrupt a chamber in which the first wet etching process is performed.

However, in example embodiments, the first lower spacer layer <NUM> including an oxide and the second lower spacer layer <NUM> including a nitride may be stacked between the sidewall of the bit line structure <NUM> and the third lower spacer layer <NUM>, and the second lower spacer layer <NUM> including a nitride may prevent the sidewall of the bit line structure <NUM> from being exposed by the SC1 solution. Additionally, the first lower spacer layer <NUM> and the second lower spacer layer <NUM> may prevent the metal included in the fourth conductive pattern <NUM> from moving to the fourth lower spacer layer <NUM>.

The second wet etching process may be performed using hydrogen fluoride (HF), and thus the first to third lower spacer layers <NUM>, <NUM> and <NUM> may be etched.

As the first and second wet etching processes are performed, the first to fourth lower spacer layers <NUM>, <NUM>, <NUM> and <NUM> may remain only in the first hole <NUM> and may form first to fourth lower spacers <NUM>, <NUM>, <NUM> and <NUM>, respectively. The first to third lower spacers <NUM>, <NUM> and <NUM> sequentially stacked on an inner wall of the first hole <NUM> and the fourth lower spacer <NUM> on the third lower spacer <NUM> and filling a remaining portion of the first hole <NUM> may form a first lower spacer structure <NUM>, and a sidewall of a lower portion of the bit line structure <NUM> in the first hole <NUM> may be covered by the first lower spacer structure <NUM>.

A first upper spacer layer <NUM> may be formed on the first lower spacer structure <NUM> and the second insulation layer <NUM> to cover a sidewall of other portions of the bit line structure <NUM> not covered by the first lower spacer structure <NUM> and a sidewall of the third insulation pattern <NUM> under a portion of the bit line structure <NUM> at an outside of the first hole <NUM>, and a second upper spacer layer <NUM> may be formed on the first upper spacer layer <NUM>.

For example, the first upper spacer layer <NUM> may include a nitride, e.g., silicon nitride, and the second spacer layer <NUM> may include a material having a high etching selectivity with respect to the first upper spacer layer <NUM>, e.g., an oxide such as silicon oxide.

Referring to <FIG>, the first and second upper spacer layers <NUM> and <NUM> may be anisotropically etched to form first and second upper spacers <NUM> and <NUM>, respectively, covering an upper sidewall of the bit line structure <NUM> on the first hole <NUM> and a sidewall of the portion of the bit line structure <NUM> at an outside of the first hole <NUM>.

Referring to <FIG>, the first and second insulation layers <NUM> and <NUM> may be also etched, and first and second insulation patterns <NUM> and <NUM> may remain under the portion of the bit line structure <NUM> at an outside of the first hole <NUM> and the first and second upper spacers <NUM> and <NUM> on the sidewall thereof.

Accordingly, upper surfaces of the active pattern <NUM> and the isolation pattern <NUM> may be partially exposed, and the first to third insulation patterns <NUM>, <NUM> and <NUM> sequentially stacked between the bit line structure <NUM> and the substrate <NUM> may form an insulation structure.

During the etching process, an edge upper portion of the first lower spacer structure <NUM> may be partially etched.

In example embodiments, the first upper spacer <NUM> may be formed on the sidewall of the bit line structure <NUM> and an upper surface of the first lower spacer structure <NUM> on the first hole <NUM> and may have a cross-section in the first direction of an "L" shape. Additionally, the first upper spacer <NUM> may be formed on the sidewall of the bit line structure <NUM>, a sidewall of the third insulation pattern <NUM> and an upper surface of the second insulation pattern <NUM> at an outside of the first hole <NUM> and may have a cross-section in the first direction of an "L" shape. In some embodiments, the first upper spacer <NUM> may include a vertical portion extending in the vertical direction and a horizontal portion protruding from a lower end of the vertical portion and extending in the first direction as illustrated in <FIG>.

Referring to <FIG>, a third upper spacer layer may be formed on the bit line structure <NUM>, the first and second upper spacers <NUM> and <NUM>, the first and second insulation patterns <NUM> and <NUM>, the active pattern <NUM> and the isolation pattern <NUM>, and may be anisotropically etched to form a third upper spacer <NUM> covering sidewalls of the first and second upper spacers <NUM> and <NUM> and an edge upper surface of the first lower spacer structure <NUM>.

For example, the third upper spacer <NUM> may include a material having a high etching selectivity with respect to the second upper spacer <NUM>, e.g., a nitride such as silicon nitride.

The first to third upper spacers <NUM>, <NUM> and <NUM> sequentially stacked in a horizontal direction substantially parallel to an upper surface of the substrate <NUM> on a sidewall of an upper portion of the bit line structure <NUM> on the first hole <NUM> and a sidewall of the portion of the bit line structure <NUM> at an outside of the first hole <NUM> may be referred to as a preliminary upper spacer structure.

Referring to <FIG>, an upper portion of the active pattern <NUM> and an upper portion of the isolation pattern <NUM> adjacent thereto may be partially removed by an etching process using the bit line structure <NUM>, the first to third insulation patterns <NUM>, <NUM> and <NUM> and the preliminary upper spacer structure as an etching mask to form a third recess <NUM>.

Referring to <FIG>, a lower contact plug layer <NUM> may be formed to fill the third recess <NUM> on the substrate <NUM> and a space between the bit line structures <NUM>, and an upper portion of the lower contact plug layer <NUM> may be planarized until an upper surface of the first capping pattern <NUM> is exposed.

In example embodiments, the lower contact plug layer <NUM> may extend in the second direction, and a plurality of lower contact plug layers <NUM> may be formed to be spaced apart from each other in the first direction by the bit line structures <NUM>.

Referring to <FIG> and <FIG>, a second mask (not shown) including first openings, each of which may extend in the first direction, spaced apart from each other in the second direction may be formed on the first capping pattern <NUM> and the lower contact plug layer <NUM>, and the lower contact plug layer <NUM> may be etched using the second mask as an etching mask.

In example embodiments, each of the first openings may overlap the gate structure <NUM> in a vertical direction substantially perpendicular to the upper surface of the substrate <NUM>. By the etching process, a second opening may be formed to expose the upper surface of the gate mask <NUM> of the gate structure <NUM> between the bit line structures <NUM> on the substrate <NUM>.

After removing the second mask, a second capping pattern <NUM> may be formed on the substrate <NUM> to fill the second opening. The second capping pattern <NUM> may extend in the first direction between the bit line structures <NUM>, and a plurality of second capping patterns <NUM> may be formed in the second direction.

Thus, the lower contact plug layer <NUM> extending in the second direction between the bit line structures <NUM> may be divided into a plurality of lower contact plugs <NUM> spaced apart from each other in the second direction by the second capping patterns <NUM>. Each of the lower contact plugs <NUM> may contact a corresponding one of opposite ends in the third direction of a corresponding one of the active patterns <NUM> and may be electrically connected thereto.

Referring to <FIG>, an upper portion of the lower contact plug <NUM> may be removed to expose an upper portion of the preliminary spacer structure on the sidewall of the bit line structure <NUM>, and upper portions of the second and third upper spacers <NUM> and <NUM> of the exposed preliminary spacer structure may be removed. Thus, an upper sidewall of the first upper spacer <NUM> may be exposed.

An upper portion of the lower contact plug <NUM> may be further removed by, e.g., an etch back process. Thus, the upper surface of the lower contact plug <NUM> may be lower than uppermost surfaces of the second and third upper spacers <NUM> and <NUM>.

A fourth upper spacer layer may be formed on the bit line structure <NUM>, the preliminary upper spacer structure, the second capping pattern <NUM>, and the lower contact plug <NUM>, and may be anisotropically etched so that a fourth upper spacer <NUM> may be formed to cover the preliminary upper spacer structure on each of opposite sidewalls of the bit line structure <NUM> in the first direction and that an upper surface of the lower contact plug <NUM> may be exposed.

An ohmic contact pattern <NUM> may be formed on the exposed upper surface of the lower contact plug <NUM>. In example embodiments, the ohmic contact pattern <NUM> may be formed by forming a metal layer on the lower contact plug <NUM>, the fourth upper spacer <NUM>, and the first and second capping patterns <NUM> and <NUM>, thermally treating the metal layer, and removing an unreacted portion of the metal layer.

Referring to <FIG>, a barrier layer <NUM> may be formed on the fourth upper spacer <NUM>, the ohmic contact pattern <NUM>, and the first and second capping patterns <NUM> and <NUM>, an upper contact plug layer <NUM> may be formed on the barrier layer <NUM> to fill a space between the bit line structures <NUM>, and an upper portion of the upper contact plug layer <NUM> may be planarized.

In example embodiments, an upper surface of the upper contact plug layer <NUM> may be higher than upper surfaces of the first and second capping patterns <NUM> and <NUM>.

Referring to <FIG>, an upper portion of the upper contact plug layer <NUM>, a portion of the barrier layer <NUM>, an upper portion of the first capping pattern <NUM>, and upper portions of the first, third and fourth lower spacers <NUM>, <NUM> and <NUM> may be removed to form a second hole <NUM>, and thus an upper surface of the second upper spacer <NUM> may be exposed.

As the second hole <NUM> is formed, the upper contact plug layer <NUM> may be transformed into an upper contact plug <NUM>. In example embodiments, a plurality of upper contact plugs <NUM> may be formed to be spaced apart from each other in each of the first and second directions and may be arranged in a honeycomb pattern in a plan view. Each of the upper contact plugs <NUM> may have a shape of a circle, ellipse, or polygon in a plan view.

The lower contact plug <NUM>, the ohmic contact pattern <NUM>, the barrier layer <NUM>, and the upper contact plug <NUM> sequentially stacked on the substrate <NUM> may form a contact plug structure.

The exposed second spacer <NUM> may be removed to form an air gap <NUM> connected to the second hole <NUM>. The second spacer <NUM> may be removed by, e.g., a wet etching process.

In example embodiments, not only a portion of the second spacer <NUM> on the sidewall of the bit line structure <NUM> extending in the second direction directly exposed by the second hole <NUM> but also other portions of the second spacer <NUM> parallel to the directly exposed portion thereof in the horizontal direction may be removed. That is, not only the portion of the second spacer <NUM> exposed by the second hole <NUM> not to be covered by the upper contact plug <NUM> but also a portion of the second spacer <NUM> adjacent to the exposed portion in the second direction to be covered by the second capping pattern <NUM> and a portion of the second spacer <NUM> adjacent to the exposed portion in the second direction to be covered by the upper contact plug <NUM> may be all removed.

First and second insulating interlayers <NUM> and <NUM> may be sequentially stacked to fill the second hole <NUM>. The first and second insulating interlayers <NUM> and <NUM> may be also sequentially stacked on the second capping pattern <NUM>.

The first insulating interlayer <NUM> may include a material having a low gap filling characteristic, and thus the air gap <NUM> under the second hole <NUM> may not be filled. The air gap <NUM> may be also referred to as an air spacer <NUM> and may form an upper spacer structure together with the first, third and fourth upper spacers <NUM>, <NUM> and <NUM>. That is, the air gap <NUM> may be a spacer including, for example, an air.

Referring to <FIG> and <FIG> again, a capacitor <NUM> may be formed to contact the upper surface of the upper contact plug <NUM>.

Particularly, an etch stop layer <NUM> and a mold layer (not shown) may be sequentially formed on the upper contact plug <NUM> and the first and second insulating interlayers <NUM> and <NUM>, and partially etched to form a third hole partially exposing the upper surface of the upper contact plug <NUM>.

A lower electrode layer (not shown) may be formed on a sidewall of the third hole, the exposed upper surface of the upper contact plug <NUM> and the mold layer, a sacrificial layer (not shown) may be formed on the lower electrode layer to fill the third hole, and the lower electrode layer and the sacrificial layer may be planarized until an upper surface of the mold layer is exposed to divide the lower electrode layer. The sacrificial layer and the mold layer may be removed by, e.g., a wet etching process, and thus a lower electrode <NUM> having a cylindrical shape may be formed on the exposed upper surface of the upper contact plug <NUM>. Alternatively, the lower electrode <NUM> may have a pillar shape filling the third hole.

A dielectric layer <NUM> may be formed on a surface of the lower electrode <NUM> and the etch stop layer <NUM>, and an upper electrode <NUM> may be formed on the dielectric layer <NUM> so that the capacitor <NUM> including the lower electrode <NUM>, the dielectric layer <NUM> and the upper electrode <NUM> may be formed.

A third insulating interlayer <NUM> may be formed to cover the capacitor <NUM> on the substrate <NUM> to complete the fabrication of a portion of the semiconductor device. For example, the third insulating interlayer <NUM> may include an oxide, e.g., silicon oxide.

<FIG> are cross-sectional views of a region X of <FIG> in accordance with example embodiments of the inventive concepts. These semiconductor devices may be substantially the same as or similar to that of <FIG> and <FIG>, except for some elements. Thus, like reference numerals refer to like elements, and detailed descriptions on several elements may be omitted herein.

Referring to <FIG>, the upper spacer <NUM> included in the upper spacer structure may have a cross-section in the first direction, which may not have an "L" shape. Thus, not only a lower surface of the first upper spacer <NUM> but also a bottom of the air spacer <NUM> may contact an upper surface of the first lower spacer structure <NUM>. In some embodiments, the upper spacer <NUM> may have a line shape as illustrated in <FIG>.

In the processes illustrated with reference to <FIG> and <FIG>, instead of sequentially stacking the first and second upper spacer layers <NUM> and <NUM> and anisotropically etching the first and second spacer layers <NUM> and <NUM>, the first upper spacer layer <NUM> may be formed and anisotropically etched, and the second upper spacer layer <NUM> may be formed and anisotropically etched, so that the upper spacer <NUM> may have the shape shown in <FIG>.

Referring to <FIG>, the semiconductor device may include a second lower spacer structure <NUM> instead of the first lower spacer structure <NUM>, and the second lower spacer structure <NUM> may not include the second and third lower spacers <NUM> and <NUM> but may include only the first and fourth lower spacers <NUM> and <NUM>.

The first lower spacer <NUM> may not include nitrogen, and thus, as the semiconductor device shown in <FIG> and <FIG>, currents may easily flow through the conductive structure <NUM> of the bit line structure <NUM>.

Referring to <FIG>, unlike that of <FIG>, the cross-section in the first direction of the first upper spacer <NUM> included in the upper spacer structure may not have an "L" shape, and thus not only a lower surface of the first upper spacer <NUM> but also a bottom of the air spacer <NUM> may contact an upper surface of the first lower spacer structure <NUM>. In some embodiments, the upper spacer <NUM> may have a line shape as illustrated in <FIG>.

Referring to <FIG>, the semiconductor device may include a first spacer <NUM> on the sidewall of the conductive structure <NUM> of the bit line structure <NUM>, a second spacer <NUM> on the sidewall of the bit line structure <NUM>, an outer sidewall of the first spacer <NUM> and the inner wall of the second recess <NUM>, the first and fourth lower spacers <NUM> and <NUM> on the second spacer <NUM> in the second recess <NUM>, the air spacer <NUM> on the first and fourth lower spacers <NUM> and <NUM> and covering a portion of the outer sidewall of the second spacer <NUM>, the third upper spacer <NUM> covering the outer sidewall of the air spacer <NUM>, and the fourth upper spacer <NUM> contacting the upper surface of the first capping pattern <NUM>, an upper surface and an upper outer sidewall of the second spacer <NUM>, the top of the air spacer <NUM>, and the upper surface and the upper outer sidewall of the third upper spacer <NUM>.

In example embodiments, the first spacer <NUM> may include, e.g., silicon oxide, and may be formed not only on the sidewall of the conductive structure <NUM> but also on the edge upper surface of the active pattern <NUM> in the second recess <NUM>.

The second spacer <NUM> may cover the upper sidewall of the bit line structure <NUM> not covered by the first spacer <NUM> and the outer sidewall of the first spacer <NUM> and may also cover the bottom of the second recess <NUM>. The second spacer <NUM> may include a nitride, e.g., silicon nitride.

An entire sidewall of the conductive structure <NUM> including, e.g., polysilicon doped with n-type impurities may be covered by the first spacer <NUM> not containing nitrogen, and thus electrons may not be trapped in the first spacer <NUM>. Accordingly, currents may easily flow through the conductive structure <NUM>.

<FIG> are cross-sectional views of a region X of <FIG> illustrating a method of manufacturing a semiconductor device in accordance with example embodiments. This method may include several processes substantially the same as or similar to those illustrated with reference to <FIG> and <FIG> and <FIG> and thus repeated explanations may be omitted herein.

Referring to <FIG>, processes substantially the same as or similar to those illustrated with reference to <FIG> may be performed, and an oxidation process may be performed on the sidewall of the conductive structure <NUM> of the bit line structure <NUM>.

Thus, a first spacer <NUM> may be formed on each of opposite sidewalls in the first direction of the conductive structure <NUM> that may include polysilicon doped with n-type impurities, and the first spacer <NUM> may be formed on a portion of the upper surface of the active pattern <NUM> including silicon.

Referring to <FIG>, a second spacer layer <NUM> may be formed on the sidewall and the upper surface of the bit line structure <NUM>, the first spacer <NUM>, the inner wall of the first hole <NUM>, the upper surface of the second insulation layer <NUM>, and the sidewall of the third insulation pattern <NUM>, the first and fourth lower spacer layers <NUM> and <NUM> may be sequentially formed on the second spacer layer <NUM>, and a wet etching process may be performed on the first and fourth lower spacer layers <NUM> and <NUM>, and thus the first and fourth lower spacers <NUM> and <NUM> may be formed in the first hole <NUM>.

The second upper spacer layer <NUM> may be formed on the second spacer layer <NUM>, the first and fourth lower spacers <NUM> and <NUM>, the second insulation layer <NUM> and the third insulation pattern <NUM>.

Referring to <FIG>, the second upper spacer layer <NUM> and the second spacer layer <NUM> may be anisotropically etched to form the second upper spacer <NUM> and a second spacer <NUM>, respectively.

Processes substantially the same as or similar to those illustrated with reference to <FIG> may be performed to form the third upper spacer <NUM>.

processes substantially the same as or similar to those illustrated with reference to <FIG> and <FIG> and <FIG> may be performed to complete the fabrication of a portion of the semiconductor device.

Claim 1:
A semiconductor device comprising:
an active pattern (<NUM>) on a substrate (<NUM>);
a gate structure (<NUM>) in an upper portion of the active pattern;
a bit line structure (<NUM>) on the active pattern, wherein the bit line structure includes a first conductive pattern (<NUM>), a diffusion barrier (<NUM>), a second conductive pattern (<NUM>) and a capping pattern (<NUM>) sequentially stacked on the substrate, wherein the first conductive pattern includes polysilicon doped with n-type impurities, and wherein the second conductive pattern includes a metal;
a lower spacer structure (<NUM>) extending on a lower portion of a sidewall of the bit line structure;
an upper spacer structure extending on an upper portion of the sidewall of the bit line structure, wherein the upper spacer structure is on the lower spacer structure;
a contact plug structure on the active pattern adjacent to the bit line structure; and
a capacitor (<NUM>) on the contact plug structure,
wherein the lower spacer structure includes a first lower spacer (<NUM>) and a second lower spacer (<NUM>) sequentially stacked on the lower portion of the sidewall of the first conductive pattern of the bit line structure, the first lower spacer contacts the lower portion of the sidewall of the first conductive pattern of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from that of the first lower spacer,
wherein the lower spacer structure further includes third (<NUM>) and fourth <NUM> lower spacers sequentially stacked between the first and second lower spacers,
wherein the first lower spacer includes an oxide, the second lower spacer includes a nitride, the third lower spacer includes a nitride, and the fourth lower spacer includes an oxide; and
wherein a portion of the upper spacer structure contacts the upper portion of the sidewall of the bit line structure and includes a material different from that of the first lower spacer, and wherein the first lower spacer does not contact the upper portion of the sidewall of the bit line structure.