Patent Description:
To improve an integration level of a semiconductor structure, at least one memory chip may be placed in a same package structure. A high bandwidth memory, HBM is a new type of memory. In a memory chip stacking technology represented by the HBM, an original one-dimensional memory layout is extended to a three-dimensional one. That is, a plurality of memory chips are stacked together and packaged, thereby greatly improving density of the memory chips, and achieving a large capacity and high bandwidth.

However, with increase of number of stacked layers, performance of the HBM needs to be improved. Background may be found in <CIT>, <CIT>, <CIT>, <CIT>, <CIT> and <CIT>. In particular, document <CIT> discloses: a semiconductor structure comprising: a substrate having a power supply port ; a module positioned on an upper surface of the substrate , the module comprising a plurality of chips stacked in a first direction, the first direction being parallel to the upper surface of the substrate, each of the plurality of chips having a power supply signal line, at least one of the plurality of chips having a power supply wiring layer, the power supply signal line being electrically connected to the power supply wiring layer, the power supply wiring layer being positioned in the module, an end surface of the power supply wiring layer far away from the substrate being exposed by the module, a bump being further provided on the end surface; and a lead frame electrically connected to the bump and to the power supply port.

Embodiments of the present application provide a semiconductor structure and a method for fabricating the same, which is at least beneficial to improve the performance of the semiconductor structure.

The technical solutions provided by the embodiments of the present application at least have the following advantages. A plurality of memory chips are stacked in a direction parallel to the substrate. Therefore, the plurality of memory chips have an equal communication distance, which is advantageous to unifying communication delay and increasing operating speed. In addition, the power supply wiring layer in the memory chip can lead the power supply signal lines out of the memory chip, so as to achieve wired power supply. The stability and reliability of wired power supply is relatively high. Moreover, the solder bump is connected to the lead frame, so as to improve the strength of the structure.

The accompanying drawings herein are incorporated in and constitute a part of this specification, illustrate embodiments conforming to the present application and, together with the specification, serve to explain the principles of the present application.

Referring to <FIG>, a high bandwidth memory, HBM adopts a parallel stacking mode where front surfaces of a plurality of memory chips <NUM> are parallel to an upper surface of a substrate <NUM>. That is, an arrangement direction of the plurality of memory chips <NUM> is perpendicular to the upper surface of the substrate <NUM>. When number of stacked layers is larger, a communication distance between the memory chip <NUM> at the uppermost layer and a logic chip <NUM> has larger difference from a communication distance between the memory chip <NUM> at the lowermost layer and the logic chip <NUM>, resulting in larger difference between communication delay of different memory chips <NUM> and communication delay the logic chip <NUM>, which has a negative effect on an operating speed of a product. In addition, a power supply mode of a semiconductor structure may also have an effect on its performance.

Embodiments of the present application provide a semiconductor structure, where a plurality of memory chips are stacked in a direction parallel to an upper surface of a substrate. That is, an arrangement direction of the plurality of memory chips is parallel to the upper surface of the substrate. Therefore, the plurality of memory chips have an equal communication distance, which is advantageous to unifying communication delay and increasing operating speed. In addition, a power supply wiring layer changes a layout of power supply signal lines and lead the power supply signal lines out of a memory module. That is, reliability of power supply can be improved by means of wired power supply. In addition, a solder bump causes connection between a lead frame and a memory module to be firmer, and the lead frame specifies a layout of a power supply path, thereby ensuring stability of power supply.

The embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, a person of ordinary skill in the art may understand that in the embodiments of the present application, many technical details are put forward such that a reader may better understand the embodiments of the present application. However, the technical solutions of the present invention are only limited by the scope of the appended claims.

As shown in <FIG>, an embodiment of the present application provides a semiconductor structure, which includes: a substrate <NUM> having a power supply port <NUM>; a memory module <NUM> positioned on an upper surface of the substrate <NUM>; and a lead frame <NUM>. The memory module <NUM> includes a plurality of memory chips <NUM> stacked in a first direction X, where the first direction X is parallel to the upper surface of the substrate <NUM>. Each of the memory chips <NUM> has a power supply signal line <NUM>, at least one of the memory chips <NUM> has a power supply wiring layer <NUM>, and the power supply signal line <NUM> is electrically connected to the power supply wiring layer <NUM>. The power supply wiring layer <NUM> is positioned in the memory module <NUM>, and an end surface <NUM> of the power supply wiring layer <NUM> far away from the substrate <NUM> is exposed by the memory module <NUM>. A solder bump <NUM> is further provided on the end surface <NUM>, and the lead frame <NUM> is connected to the solder bump <NUM> and is also electrically connected to the power supply port <NUM>.

Such design at least includes following effects.

First, the power supply wiring layer <NUM> may lead out the power supply signal line <NUM>, to provide wired power supply to the memory chip <NUM>, thereby improving the stability of power supply. In some embodiments, the surface of the memory chip <NUM> includes a front surface and a back surface opposite to each other, and a side surface connected between the front surface and the back surface, where an area of the front surface and an area of the back surface are larger than that of the side surface. A plane where the power supply wiring layer <NUM> is positioned is perpendicular to the upper surface of the substrate <NUM>. That is, the power supply wiring layer <NUM> may be positioned on the front surface or the back surface of the memory chip <NUM> to connect the power supply signal line <NUM>.

Second, the solder bump <NUM> not only can electrically connect the power supply wiring layer <NUM> to the lead frame <NUM>, but also can fix the lead frame <NUM>, thereby improving structural strength.

Third, the lead frame <NUM> is not easily deformed due to higher strength, such that a direction of a wired power supply path can be specified.

Fourth, the plurality of memory chips <NUM> are stacked along the first direction X. That is, the arrangement direction of the plurality of memory chips <NUM> is parallel to the substrate <NUM>. In this way, the side surface of the memory chip <NUM> faces toward the substrate <NUM>. Because the area of the side surface of the memory chip <NUM> is smaller, an occupied area of the upper surface of the substrate <NUM> is smaller, which is advantageous to increasing number of the memory chips <NUM> stacked.

The semiconductor structure will be described in detail below with reference to the accompanying drawings.

First, it is to be noted that the semiconductor structure has the first direction X, a second direction Y, and a third direction Z. The first direction X is the stacking direction of the memory chips <NUM>, the second direction Y is perpendicular to the first direction X and is parallel to the upper surface of the substrate <NUM>, and the third direction Z is perpendicular to the upper surface of the substrate <NUM>.

Referring to <FIG>, the plurality of memory chips <NUM> may be stacked in a hybrid bonding manner. For example, a dielectric layer <NUM> is further provided on the surface of each of the memory chips <NUM>, and the dielectric layers <NUM> of the adjacent memory chips <NUM> may be connected together by an acting force such as a molecular force. In addition, a bonding portion <NUM> may also be provided on the surface of each of the memory chips <NUM>, and the adjacent bonding portions <NUM> are bonded and connected together under a heating condition. That is, the dielectric layer <NUM> is made of an insulating material and can play an isolation role; and the bonding portion <NUM> is made of a conductive material and can play an electrical connection role. In addition, the dielectric layer <NUM> also exposes an end surface <NUM> of the power supply wiring layer <NUM> facing away from the substrate <NUM> and covers the surface of the power supply wiring layer <NUM> except the end surface <NUM>.

The memory chip <NUM> may be a chip such as a dynamic random access memory, DRAM, or a static random-access memory, SRAM. In some embodiments, the adjacent memory chips <NUM> may all be stacked in the manner that the front surface faces the back surface, which is advantageous to unifying the step of bonding the memory chips <NUM>, such that the production process is simpler. In some embodiments, the adjacent memory chips <NUM> may also be stacked in a manner where the front surface faces the front surface or the back surface faces the back surface. The front surface of the memory chip <NUM> may also be understood as an active surface <NUM>, and the back surface of the memory chip <NUM> may be understood as an inactive surface opposite to the active surface <NUM>.

The power supply wiring layer <NUM> and the power supply signal line <NUM> will be described in detail below.

Referring to <FIG>, the power supply wiring layer <NUM> may be positioned on the front surface of the memory chip <NUM>. That is, the power supply wiring layer <NUM> extends along the active surface <NUM> of the memory chip <NUM>. Therefore, the power supply wiring layer <NUM> may be fabricated by means of the original back-end process after the fabrication of the components in the memory chip <NUM> is completed, such that the process is simpler. In addition, the power supply wiring layer <NUM> may extend only at the edge position close to a side of the active surface <NUM> of the memory chip <NUM> without covering the active surface <NUM> of the entire memory chip <NUM>, so the contact area between the power supply wiring layer <NUM> and the memory chip <NUM> is small, which reduces the influence of heat generation of the power supply wiring layer <NUM> on the memory chip <NUM>.

Referring to <FIG> that is the schematic diagram of the active surface <NUM> of the memory chip <NUM>, each memory chip <NUM> has the plurality of power supply signal lines <NUM>, and the power supply signal line <NUM> extends from the inside of the memory chip <NUM> to the active surface <NUM> to be connected to the power supply wiring layer <NUM>. Different power supply signal lines <NUM> provide different voltage signals for the components in the memory chip <NUM>. The power supply signal line <NUM> may be the ground signal line <NUM> or the power signal line 12P. Different ground signal lines <NUM> have different voltage signals, and different power signal lines 12P have different voltage signals.

Each power supply wiring layer <NUM> includes the plurality of power supply wirings <NUM> arranged at intervals, where a power supply wiring <NUM> is electrically connected to a power supply signal line <NUM>, different power supply signal lines <NUM> have different voltage signals, and correspondingly, different power supply wirings <NUM> have different voltage signals. The power supply wiring layer <NUM> includes a ground wiring <NUM> and a power wiring 20P, where the ground wiring <NUM> is electrically connected to the ground signal line <NUM>, and the power wiring 20P is electrically connected to the power signal line 12P.

In some embodiments, referring to <FIG> and <FIG> to <FIG>, each memory chip has one power supply wiring layer <NUM>, and the power supply wiring layer <NUM> in each memory chip <NUM> is correspondingly connected to the power supply signal line <NUM>. That is, the power supply signal lines <NUM> of different memory chips <NUM> are independent of each other and do not need to be electrically connected together by means of a conductive via <NUM> and the bonding portion <NUM>; and the power supply signal line <NUM> in each memory chip <NUM> may be led out by the power supply wiring layer <NUM> of the memory chip <NUM> without the power supply wiring layer <NUM> of other memory chip <NUM>. Because the power supply signal line <NUM> of each memory chip <NUM> may be separately led out, it is advantageous to improving the stability of power supply. In addition, the step of fabricating the conductive via <NUM> (referring to <FIG>) may be omitted, thereby reducing production costs. In addition, because the plurality of memory chips are independent of each other, no bonding portion <NUM> may be arranged between the adjacent memory chips <NUM>.

<FIG> is a vertical view of the semiconductor structure shown in <FIG> and <FIG> to <FIG>. To be more intuitive, only the lead frame <NUM> and the solder bump <NUM> are shown in <FIG>. Referring to <FIG>, because each memory chip <NUM> has the power supply wiring layer <NUM>, correspondingly, each memory chip <NUM> also has the solder bump <NUM>. That is, number of the solder bumps <NUM> is larger, so strength of connection between the lead frame <NUM> and the memory module <NUM> may be enhanced, thereby improving the stability of the structure.

In some other embodiments, referring to <FIG>, the number of the power supply wiring layers <NUM> may also be less than that of the memory chips <NUM>. In some embodiments, the conductive via <NUM> is provided in the memory chip <NUM>, where the conductive via <NUM> is connected to the power supply signal line <NUM>; and the bonding portion <NUM> is provided between the adjacent memory chips <NUM>, where the bonding portion <NUM> is connected to the conductive via <NUM> in the adjacent memory chips <NUM>. That is, the power supply signal lines <NUM> having the same voltage signal in different memory chips <NUM> may be connected together by means of the conductive vias <NUM> and the bonding portions <NUM>. For example, the power supply signal lines <NUM> having the same voltage signal in two adjacent memory chips <NUM> are electrically connected to each other, such that only one of the two memory chips <NUM> needs to have the power supply wiring layer <NUM>.

That is, the plurality of memory chips <NUM> may share one power supply wiring layer <NUM>. When one memory chip <NUM> has the power supply wiring layer <NUM>, the power supply signal line <NUM> of the memory chip <NUM> may be directly connected to its own power supply wiring layer <NUM>. That is, the power supply signal line <NUM> is led out by its own power supply wiring layer <NUM>. When one memory chip <NUM> does not have the power supply wiring layer <NUM>, the memory chip <NUM> may be electrically connected to other memory chip <NUM> by means of the conductive via <NUM> and the bonding portion <NUM>, such that the power supply signal line <NUM> is led out by the power supply wiring layer <NUM> of the other memory chip <NUM>.

<FIG> is a vertical view of the semiconductor structure shown in <FIG>. To be more intuitive, <FIG> only shows the lead frame <NUM> and the solder bump <NUM>. Referring to <FIG>, because the plurality of memory chips <NUM> may share one power supply wiring layer <NUM>, the number of the power supply wiring layers <NUM> is smaller, and correspondingly, the number of the solder bumps <NUM> is smaller, such that spacing between the adjacent solder bumps <NUM> may be increased to avoid wrong electrical connection between the adjacent solder bumps <NUM>.

The lead frame <NUM> will be described in detail below.

Referring to <FIG> and <FIG>, the lead frame <NUM> includes a plurality of frame strips <NUM> arranged at intervals, and the plurality of frame strips <NUM> are arranged in the second direction Y, where the second direction Y is perpendicular to the first direction X and is parallel to the upper surface of the substrate <NUM>. Each of the power supply wiring layers <NUM> comprises a plurality of power supply wirings <NUM>, and different power supply wirings <NUM> have different voltages. Different frame strips <NUM> are connected to the power supply wirings <NUM> having the different voltages.

The solder bumps <NUM> having the same voltage signal may be aligned in the first direction X. That is, the power supply wirings <NUM> having the same voltage signal in the plurality of power supply wiring layers <NUM> directly face each other in the first direction X. In this way, orthographic projections of the frame strips <NUM> on the substrate <NUM> may be linear, thereby facilitating the alignment of the frame strips <NUM> to the solder bumps <NUM>, simplifying the soldering processes, and saving materials of the frame strips <NUM>.

With continued reference to <FIG> and <FIG>, each of the plurality of frame strips <NUM> includes a ground frame strip <NUM> and a power frame strip 70P, where the ground frame strip <NUM> is electrically connected to the ground wiring <NUM>, and the power frame strip 70P is electrically connected to the power wiring 20P. In some embodiments in accordance with the claimed invention, the ground frame strip <NUM> and the power frame strip 70P are alternately arranged in the second direction Y. Accordingly, the ground wiring <NUM> and the power wiring 20P are alternately arranged in the second direction Y. In this way, it is advantageous to reducing electromagnetic interference between adjacent power supply wiring <NUM> and adjacent frame strips <NUM>.

In some embodiments, the plurality of frame strips <NUM> are arranged at equal intervals, which is advantageous to improving structural uniformity and avoiding erroneous electrical connection between adjacent frame strips <NUM> due to smaller distance.

Referring to <FIG>, the lead frame <NUM> includes support frames <NUM> and a solder frame <NUM> connected to each other, where the support frames <NUM> extend in a direction perpendicular to the upper surface of the substrate <NUM>, and the solder frame <NUM> extends in a direction parallel to the upper surface of the substrate <NUM> and is soldered to the solder bump <NUM>. That is, the solder bump <NUM> may fix the solder frame <NUM> above the memory module <NUM>, such that the memory module <NUM> can support the lead frame <NUM> to improve the stability of the structure.

In some embodiments, there are at least two support frames <NUM>, which are respectively positioned on opposite two sides of the memory module <NUM> and are connected to opposite two ends of the solder frame <NUM>, respectively. The plurality of support frames <NUM> are advantageous to improving the stability of the lead frame <NUM>, thereby improving the reliability of power supply. In some other embodiments, the lead frame <NUM> may also have one support frame <NUM>, which is advantageous to saving materials.

Referring to <FIG>, a groove 7a may also be provided in the lead frame <NUM>, and the solder bump <NUM> directly faces and is soldered to the groove 7a. That is, the groove 7a is positioned in the solder frame <NUM>. It is to be noted that a solder layer <NUM> is further provided on the top surface of the solder bump <NUM> to connect the solder bump <NUM> and the lead frame <NUM>. The groove 7a may accommodate more solders to improve the soldering strength and reduce the resistance of contact between the solder bump <NUM> and the lead frame <NUM>.

In some embodiments, a width of the solder frame <NUM> in the second direction Y may be greater than that of the solder bump <NUM> in the second direction Y, and an opening area of the groove 7a is larger than a top surface area of the solder bump <NUM>. In this way, solder capacity is larger and soldering firmness is better; and in addition, the larger opening facilitates the alignment of the solder bump <NUM> to the groove 7a. In some other embodiments, the width of the solder frame <NUM> in the second direction Y may also be less than or equal to that of the solder bump <NUM>.

In some embodiments, referring to <FIG>, each frame strip <NUM> has a plurality of grooves 7a, and the plurality of grooves 7a are in one-to-one correspondence with the plurality of solder bumps <NUM>. In this way, the groove 7a may guide a flow direction of the solder during soldering. That is, the groove 7a guides the solder to flow toward inside the groove 7a, thereby avoiding electrical connection between the adjacent solder bumps <NUM>.

In some other embodiments, referring to <FIG>, each frame strip <NUM> has one groove 7a, one groove 7a corresponds to the plurality of solder bumps <NUM>, and the groove 7a extends in the first direction X. In this way, the production process is simpler.

In addition, in some embodiments, the groove 7a may penetrate through the lead frame <NUM>, such that the groove 7a accommodates more solders. In some other embodiments, a bottom surface of the groove 7a may be positioned in the lead frame <NUM>. That is, the groove 7a does not penetrate through the lead frame <NUM>, such that the bottom surface of the groove 7a may also be in contact with the solder, thereby increasing the contact area to reduce the contact resistance.

Referring to <FIG> and <FIG>, the lead frame <NUM> further includes extension frames <NUM> connected to side surfaces of the support frames <NUM> far away from the solder frame <NUM>. A sectional area of each of the extension frames <NUM> is larger than that of each of the support frames <NUM>, and both sections of the extension frames <NUM> and sections of the support frames <NUM> are parallel to the upper surface of the substrate <NUM>. The semiconductor structure further comprises lead wires <NUM> connected between the extension frames <NUM> and the power supply port <NUM>.

That is, the extension frame <NUM> extends in a direction parallel to the upper surface of the substrate <NUM>, and the extension frame <NUM> is advantageous to increasing the soldering area between the lead wires <NUM> and the lead frame <NUM> to facilitate soldering. In addition, the lead wires <NUM> can improve flexibility of connection between the lead frame <NUM> and the power supply port <NUM>.

In some embodiments, head and tail ends of the extension frame <NUM>, of the support frame <NUM>, and of the solder frame <NUM> are connected in sequence. That is, one strip-shaped conductive material is bent into a plurality of sections to respectively serve as the extension frame <NUM>, the support frame <NUM>, and the solder frame <NUM>, such that the production process is simpler.

In some other embodiments, referring to <FIG>, the semiconductor structure further includes power supply lines <NUM> respectively connected to side surfaces of the support frames <NUM> far away from the solder frame <NUM>. The substrate <NUM> further has a first via <NUM> penetrated, the first via <NUM> serves as the power supply port <NUM>, and the power supply lines <NUM> are arranged in the first via <NUM>. In this way, a mode of connection between the lead frame <NUM> and the power supply port <NUM> is simpler. In addition, because the side surfaces of the power supply lines <NUM> are surrounded by the first via <NUM>, the area of contact between the power supply lines <NUM> and the first via <NUM> is larger, and thus the contact resistance is smaller.

The sectional area of the power supply line <NUM> is smaller than that of the support frame <NUM>, and the section of the power supply line <NUM> and the section of the support frame <NUM> are both parallel to the upper surface of the substrate <NUM>. When the sectional area of the support frame <NUM> is larger, it is advantageous to improving the structural strength of the lead frame <NUM>; and when the sectional area of the power supply line <NUM> is smaller, it is advantageous to reducing the volume occupied by the power supply line <NUM> in the substrate <NUM>, thereby avoiding occupying spatial position of other component in the substrate <NUM>.

It is worth noting that because the lead frame <NUM> includes a plurality of frame strips <NUM> arranged at intervals, it is to be understood that each frame strip <NUM> may include a structure such as the solder frame <NUM>, the support frame <NUM>, or the extension frame <NUM>.

Referring to <FIG>, the solder bump <NUM> includes a first bump <NUM> and a second bump <NUM> arranged in stack, where the first bump <NUM> is connected to the power supply wiring layer <NUM>, and the second bump <NUM> is soldered to the lead frame <NUM>. A sectional area of the first bump <NUM> is larger than a sectional area of the second bump <NUM>, and both a section of the first bump <NUM> and a section of the second bump <NUM> are parallel to the upper surface of the substrate <NUM>.

The first bump <NUM> has a larger sectional area, which is advantageous to increasing the area of contact between the solder bump <NUM> and the power supply wiring layer <NUM>, to reduce the contact resistance. The second bump <NUM> has a smaller sectional area, which is advantageous to increasing the distance between the adjacent solder bumps <NUM> to avoid an erroneous electrical connection between the adjacent solder bumps <NUM>.

For example, in the first direction X, a ratio of a width of the first bump <NUM> to a width of each of the plurality of memory chips <NUM> ranges from <NUM> to <NUM>. When the width of the first bump <NUM> and the width of each of the plurality of memory chips <NUM> are kept within the above range, it is advantageous to ensuring that the solder bumps <NUM> have a sufficient contact area with the power supply wiring layer <NUM>, and that a proper distance is provided between the adjacent solder bumps <NUM>, to avoid wrong electrical connection between the adjacent solder bumps <NUM>.

With continued reference to <FIG>, the semiconductor structure further includes a first sealing layer <NUM>, which surrounds the memory module <NUM> and exposes a surface of the memory module <NUM> away from the substrate <NUM>. The first sealing layer <NUM> can protect the memory module <NUM> from being adversely affected by external environment such as external moisture or solvent, and can resist thermal shock and mechanical vibration when the semiconductor structure is installed.

The semiconductor structure further includes a second sealing layer <NUM>, which may cover the memory module <NUM>, the lead frame <NUM>, the solder bump <NUM>, and the first sealing layer <NUM>. The second sealing layer <NUM> may fix the solder bump <NUM> and the lead frame <NUM> to ensure structural strength. That is, the second sealing layer <NUM> can improve protection and isolation effects to ensure the performance of the semiconductor structure.

In one embodiment, a material of the first sealing layer <NUM> may be the same as a material of the second sealing layer <NUM>. For example, the first sealing layer <NUM> and the second sealing layer <NUM> may be epoxy resin.

In one embodiment, the material of the first sealing layer <NUM> may be different from the material of the second sealing layer <NUM>. For example, a thermal conductivity of the second sealing layer <NUM> is higher than that of the first sealing layer <NUM>. Based on such arrangement, heat introduced into the second sealing layer <NUM> through the lead frame <NUM> may be transferred to the external environment more quickly, such that adverse effects of high temperature environment on the memory module <NUM> are reduced.

Referring to <FIG>, the semiconductor structure further includes: a logic chip <NUM> positioned between the substrate <NUM> and the memory module <NUM>, where the logic chip <NUM> has a first wireless communication portion <NUM>, each of the plurality of memory chip <NUM> has a second wireless communication portion <NUM>, and the second wireless communication portion <NUM> is configured to perform wireless communication with the first wireless communication portion <NUM>.

Because distances between the plurality of memory chips <NUM> and the logic chip <NUM> are equal, delays of wireless communication between the plurality of memory chips <NUM> and the logic chip <NUM> are kept consistent. In some embodiments, the second wireless communication portion <NUM> is positioned on a side of the memory chip <NUM> facing the logic chip <NUM>. In this way, the distance between the first wireless communication portion <NUM> and the second wireless communication portion <NUM> may be reduced, thereby improving the quality of wireless communication.

It is to be noted that when the arrangement direction of the plurality of memory chips <NUM> is perpendicular to the upper surface of the logic chip <NUM>, the communication delays between the memory chips <NUM> at different layers and the logic chip <NUM> have larger difference. In addition, with the increase of the number of layers, the number of through-silicon vias, TSV for communication may increase in direct proportion, thereby sacrificing an area of a wafer. In the embodiments of the present application, the stacking direction and the communication mode of the memory chip <NUM> are changed, which is advantageous to improving the communication quality and saving the area of the wafer.

With continued reference to <FIG>, the side surface of the memory chip <NUM> is arranged close to the logic chip <NUM>, and the area of the side surface is smaller. In the wireless communication mode, the wired communication portion does not need to be arranged between the memory chip <NUM> and the logic chip <NUM>, such that the process difficulty may be reduced, and sufficient spatial position may be provided for the connection structure between the memory chip <NUM> and the logic chip <NUM>, to improve the structural strength between the memory chip <NUM> and the logic chip <NUM>. In addition, a lower side of the memory module <NUM> is configured for performing wireless communication, and an upper side of the memory module <NUM> is configured for arranging the wired power supply path, such that the electromagnetic interference caused by the current in the wired power supply path to a coil in the wireless communication portion can be reduced to avoid signal loss.

In some embodiments, a bonding layer <NUM> is further provided between the memory module <NUM> and the logic chip <NUM>. That is, the memory module <NUM> and the logic chip <NUM> are connected together by means of gluing to constitute one memory core. For example, the bonding layer <NUM> may be a die attach film, DAF. The bonding process is simpler, and the costs can be saved. In addition, metal ions may be doped in the bonding layer <NUM> to improve a heat dissipation effect of the memory module <NUM> and the logic chip <NUM>. In some other embodiments, a soldered layer (not shown in figure) may be provided between the memory module <NUM> and the logic chip <NUM>. That is, the memory module <NUM> and the logic chip <NUM> are connected together by means of soldering.

That is, the power supply signal line <NUM> is led out from an upper part of the memory module <NUM>, such that the sufficient spatial position can be left below the memory module <NUM> to connect the logic chip <NUM>, thereby improving the structural strength.

With continued reference to <FIG>, a bonding pad <NUM> and a solder paste layer <NUM> are further provided between the logic chip <NUM> and the substrate <NUM>. That is, the logic chip <NUM> is soldered on the substrate <NUM> by means of flip-chip bonding. In this way, the substrate <NUM> may perform power supply and signal exchange on the logic chip <NUM> in the wired mode with higher reliability. In addition, a solder ball <NUM> is further provided at the bottom of the substrate <NUM>, such that the semiconductor structure may be connected to a peripheral device.

In conclusion, in the embodiments of the present application, an upper side of the memory module <NUM> is connected by using the solder bump <NUM>, such that the stability of connection between the lead frame <NUM> and the memory module <NUM> is higher. A lower side of the memory module <NUM> is connected by using the lead wire <NUM> or the power supply line <NUM>, such that the structure is simple and the flexibility is higher. The two connection modes are matched to cause the wired power supply path to be flexible and stable.

As shown in <FIG>, <FIG> and <FIG>, another embodiment of the present application provides a method for fabricating a semiconductor structure, where this method may be used for fabricating the semiconductor structure provided in the preceding embodiments. Reference may be made to the foregoing embodiments for a detailed description of the semiconductor structure.

Referring to <FIG> and <FIG>, a memory module <NUM> is provided, and the memory module <NUM> includes a plurality of memory chips <NUM> stacked in the first direction X. Each of the plurality of memory chips <NUM> has a power supply signal line <NUM>, at least one of the plurality of memory chips <NUM> has a power supply wiring layer <NUM>, the power supply signal line <NUM> is electrically connected to the power supply wiring layer <NUM>, the power supply wiring layer <NUM> is positioned in the memory module <NUM>, an end surface <NUM> of the power supply wiring layer <NUM> far away from the substrate <NUM> is exposed by the memory module <NUM>, and a solder bump <NUM> is further provided on the end surface <NUM>.

In some embodiments, referring to <FIG>, the plurality of memory chips <NUM> are provided; and the power supply wiring layer <NUM> is formed on at least one of the plurality of memory chips <NUM>, and after the power supply wiring layer <NUM> is formed, the plurality of memory chips <NUM> are stacked. For example, the power supply signal line <NUM> of the memory chip <NUM> of each layer is led out to the edge of the memory chip <NUM> via the power supply wiring layer <NUM>, and the memory chips <NUM> of multiple layers are stacked in the hybrid bonding manner. It is to be noted that the memory chip <NUM> is horizontally placed during bonding.

Referring to <FIG>, the memory module <NUM> is rotated <NUM>°, such that each memory chip <NUM> is perpendicular to the logic chip <NUM>, and the memory chip <NUM> and the logic chip <NUM> are fixed via the DAF. The plurality of memory modules <NUM> are reconstructed by means of a first molding process to form the reconstructed wafer, and the first bump <NUM> is processed on the top surface of the reconstructed wafer by means of a rewiring process. Next, the second bump <NUM> is formed on the first bump <NUM>, the first bump <NUM> and the second bump <NUM> constitute the solder bump <NUM>, and the solder layer <NUM> is formed on the solder bump <NUM>. Next, the reconstructed wafer is diced to form the memory cores, and each memory core includes one memory module <NUM> and one logic chip <NUM>.

Referring to <FIG>, there is provided a substrate <NUM>, which has a power supply port <NUM>. The memory module <NUM> is fixed to the substrate <NUM>, where the first direction X is parallel to the upper surface of the substrate <NUM>. A lead frame <NUM> is provided, and the lead frame <NUM> is electrically connected to the solder bump <NUM> and the power supply port <NUM>.

In some embodiments, the memory core is soldered on the substrate <NUM> by means of flip-chip bonding, and the lead frame <NUM> is soldered on the solder bump <NUM> on a top surface of the memory core. Next, the lead frame <NUM> is connected to the power supply port <NUM> by means of lead wire connection, to implement connection of the power supply signal between the memory chip <NUM> and the substrate <NUM>. Next, the second sealing layer <NUM> covering the structures such as the memory module <NUM> and the lead frame <NUM> is formed by means of a second molding process.

It is worth noting that the molding process are used twice successively because the first molding process may be configured for connecting the plurality of memory modules <NUM> together, so the second sealing layer <NUM> may be simultaneously formed on the plurality of memory modules <NUM> subsequently, which is advantageous to reducing the process steps. In addition, the volume of the single memory module <NUM> is smaller, but the total volume of the plurality of memory modules <NUM> connected together is increased, such that the stability is higher and falling does not easily occur. In addition, the first sealing layer <NUM> formed by means of the first molding process can protect and fix the memory module <NUM> in subsequent steps of forming the solder bump <NUM>, performing flip-chip bonding, etc. to prevent the memory module <NUM> from collapsing or being damaged, which is advantageous to ensuring the performance of the memory module <NUM>. In addition, the molding process performed twice successively can improve the sealing effect.

Claim 1:
A semiconductor structure, the semiconductor structure comprises:
a substrate (<NUM>) having a power supply port (<NUM>);
a memory module (<NUM>) positioned on an upper surface of the substrate (<NUM>), the memory module (<NUM>) comprising a plurality of memory chips (<NUM>) stacked in a first direction (X), the first direction (X) being parallel to the upper surface of the substrate (<NUM>),
each of the plurality of memory chips (<NUM>) having a power supply signal line (<NUM>), at least one of the plurality of memory chips (<NUM>) having a power supply wiring layer (<NUM>), the power supply signal line (<NUM>) being electrically connected to the power supply wiring layer (<NUM>),
the power supply wiring layer (<NUM>) being positioned in the memory module (<NUM>), an end surface (<NUM>) of the power supply wiring layer (<NUM>) far away from the substrate (<NUM>) being exposed by the memory module (<NUM>), a solder bump (<NUM>) being further provided on the end surface (<NUM>); and
a lead frame (<NUM>) electrically connected to the solder bump (<NUM>) and the power supply port (<NUM>), wherein the lead frame (<NUM>) comprises a plurality of frame strips (<NUM>) arranged at intervals, and the plurality of frame strips (<NUM>) being arranged in a second direction (Y); the second direction (Y) is perpendicular to the first direction (X) and is parallel to the upper surface of the substrate (<NUM>);
each of the power supply wiring layers (<NUM>) comprises a plurality of power supply wirings (<NUM>), and different power supply wirings (<NUM>) having different voltages; and
different frame strips (<NUM>) are connected to the power supply wirings (<NUM>) having the different voltages.