Patent Description:
Modern display devices such as a liquid crystal display ("LCD") devices, organic light emitting diode ("OLED") display devices, plasma display panel ("PDP") devices, and electrophoretic display devices, are commonly referred to as flat panel displays, owing to their thinness as compared to traditional cathode ray tube (CRT) display devices.

Flat panel display devices generally include a plurality of layers that are sequentially stacked. In order to fix the plurality of layers together, an adhesive layer may be disposed between two adjacent layers.

One example of a suitable adhesive layer is a photo-curable adhesive layer. Photo-curable adhesive layers may have a stable adhesive force after being cured by a light source. Such a photo-curable adhesive layer, however, has weak adhesive force when it is not sufficiently cured, and may experience degradation of adhesiveness over time.

Us <CIT> discloses a display device comprising a resin member configured to cover all surfaces of a driver for protection of the driver, the resin member created by charging resin through a through hole in the cover substrate.

<CIT> discloses a display device comprising an adhesive layer consisting of a plurality of curable resin parts with different properties to adhere a base and cover plate of the display device together.

<CIT> discloses a display device including a flat transparent plate, a display panel, at least one film, a transparent adhesive layer, and a pattern layer above a metal layer.

According to the invention, there is provided a display device as set out in claim <NUM>.

A more complete appreciation of the present invention and many of the attendant aspects thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:.

In describing exemplary embodiments of the present invention illustrated in the drawings, specific terminology is employed for sake of clarity. However, the present invention is not intended to be limited to the illustrations or any specific terminology, and it is to be understood that each element includes all equivalents.

In the drawings, the size of layers and areas may be exaggerated for clarity and ease of description thereof. When an element such as a layer, area, plate, etc. is referred to as being "on" another element, it may be directly on the other element, or intervening elements may be present therebetween.

The spatially relative terms "below", "beneath", "less", "above", "upper", and the like, may be used herein for ease of description to describe the relations between one element or component and another element or component as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, in the case where a device illustrated in the drawing is turned over, the device positioned "below" or "beneath" another device may be placed "above" another device. Accordingly, the illustrative term "below" may include both the lower and upper positions. The device may also be oriented in the other direction, and thus the spatially relative terms may be interpreted differently depending on the orientations.

Throughout the specification, when an element is referred to as being "connected" to another element, the element may be "directly connected" to the other element, and/or "electrically connected" to the other element with one or more intervening elements interposed therebetween. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Terms such as "about" or "approximately," as used herein, may be inclusive of the stated value and may additionally include a range of deviation for the particular value, as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (e.g., the limitations of the measurement system).

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this invention pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an ideal or excessively formal sense unless clearly defined in the present specification.

Some of the parts which are not associated with the description may not be provided in order to specifically describe embodiments of the present invention. It is to be understood that with respect to some figures, some elements might not be described and that in these cases, it is to be assumed that the elements not described are similar to or identical to corresponding elements that have already been described. Moreover, like reference numerals may refer to like elements throughout the specification.

Hereinafter, an exemplary embodiment of the present invention will be described with reference to <FIG>, <FIG>, <FIG>.

<FIG> is a perspective view illustrating a display device <NUM> according to an exemplary embodiment of the present invention, and <FIG> is a cross-sectional view taken along line I-I' of <FIG>.

The display device <NUM> illustrated in <FIG> includes a window <NUM>, a case <NUM> coupled to the window <NUM> to provide an accommodating space, and a display panel <NUM> disposed in the space defined by the window <NUM> and the case <NUM>.

The display panel <NUM> is mounted within the case <NUM>, along with a support portion <NUM>. The support portion <NUM> may be, for example, a cushion member, but exemplary embodiments of the present invention are not limited thereto. Elements, such as a battery for driving the display panel <NUM> may be disposed at the support portion <NUM>.

The display panel <NUM> has a display area DA and a non-display area NDA. The display area DA is an area in which an image is displayed. The non-display area NDA may surround the display area DA, for example. Examples of the display panel <NUM> may include a liquid crystal display ("LCD") panel, an organic light emitting diode ("OLED") display panel, or the like. The detailed structure of the display panel <NUM> will be described below.

The window <NUM> on the display panel <NUM> may include a light transmitting member such as glass, plastic, or the like.

A bezel portion <NUM> is disposed on the window <NUM> and overlaps the non-display area NDA of the display panel <NUM>. The bezel portion <NUM> may surround the window <NUM> and the bezel portion <NUM> may be disposed above, below, and to the left and right sides of the window <NUM>. Referring to <FIG>, the bezel portion <NUM> is disposed at an edge portion of the window <NUM>. For example, the bezel portion <NUM> may be provided by forming an opaque coating layer at the edge portion of the window <NUM>. The bezel portion <NUM> may protrude from a surface of the window <NUM>.

According to an exemplary embodiment of the present invention, the bezel portion <NUM> may be provided by defining a groove at the edge portion of the window <NUM> and then filling the groove with an opaque coating layer. In such an exemplary embodiment of the present invention, the bezel portion <NUM> might not protrude from the surface of the window <NUM>.

An adhesive layer <NUM> is disposed between the display panel <NUM> and the window <NUM>. In addition, an interlayer <NUM> is disposed between the bezel portion <NUM> and the adhesive layer <NUM>. Referring to <FIG>, a touch panel <NUM> is disposed between the window <NUM> and the adhesive layer <NUM>. The touch panel <NUM> is attached to the display panel <NUM> by the adhesive layer <NUM>.

The touch panel <NUM> is a device configured to recognize a touch. The touch panel <NUM> may include a plurality of sensor electrodes configured for recognizing a touch. The touch panel <NUM> may be a capacitive-type touch panel, a resistive-type touch panel, or any other type of touch panel that may be used in the described manner.

The touch panel <NUM> may be connected to the interlayer <NUM>. According to an exemplary embodiment of the present invention, the interlayer <NUM> may be electrically conductive. The conductive interlayer <NUM> may serve as the ground, for example. The interlayer <NUM> may suppress or otherwise prevent generation of static electricity in the touch panel <NUM>. In addition, the interlayer <NUM> may serve as a wiring for connecting the touch panel <NUM> to another terminal or another device. Exemplary embodiments of the present invention are not limited thereto, the interlayer <NUM> may be a light shielding pattern and include light shielding material. The roles of the interlayer <NUM> may vary depending on, for example, the material and the design of the interlayer <NUM>.

The interlayer <NUM> may include a metal. The interlayer <NUM> may or might not further include an element other than metal. For example, the interlayer <NUM> may include copper (Cu), silver (Ag), gold (Au), aluminum (Al), and/or titanium (Ti).

The interlayer <NUM> may have a monolayer structure or a multilayer structure in which a plurality of layers are stacked. The interlayer <NUM> may include a metal layer such as copper (Cu), silver (Ag), gold (Au), aluminum (Al), and/or titanium (Ti). In addition, the interlayer <NUM> may include a transparent conductive oxide (TCO) such as ITO, IZO, AZO, IGZO, or the like. For example, the interlayer <NUM> may include at least one of a metal layer and a TCO layer.

<FIG> is a plan view illustrating disposition of the window <NUM> and the interlayer <NUM>, and <FIG> is a cross-sectional view taken along line II-II' of <FIG>.

Referring to <FIG> and <FIG>, the interlayer <NUM> is disposed on the bezel portion <NUM>. The interlayer <NUM> does not overlap the display area DA of the display panel <NUM>. The interlayer <NUM> forms a closed loop along the edge of the window <NUM>.

In addition, the interlayer <NUM> may have at least one through hole <NUM> overlapping the bezel portion <NUM>. For example, the interlayer <NUM> may include a base portion <NUM> and the through hole <NUM>. The through hole <NUM> may be defined by removing a portion of the base portion <NUM>. In such an exemplary embodiment of the present invention, the base portion <NUM> may include, for example, a conductive material.

The through hole <NUM> allows ultrasonic waves to pass therethrough. In an ultrasound inspection process for confirming whether or not the adhesive layer <NUM> is properly cured, using ultrasonic waves, the through hole <NUM> becomes an ultrasound inspection area. In one exemplary embodiment of the present invention, the ultrasound inspection area refers to an area through which ultrasonic waves are passed through to carry out the ultrasound inspection. Accordingly, the ultrasound inspection area may be referred to as an ultrasonic wave transmission area.

As such, in the case where the ultrasound inspection area defined by the through hole <NUM> is secured, an ultrasound inspection may be smoothly carried out. Accordingly, the ultrasound inspection may determine whether or not the adhesive layer <NUM> is properly cured or whether or not non-curing defects are present.

The through hole <NUM> may be of a size suitable to allow ultrasonic waves to be passed therethrough. When the size of the through hole <NUM> is too small, the ultrasonic wave might not readily pass through the through hole <NUM>. When the size of the through hole <NUM> is too large, the through hole <NUM> occupies an excessive amount of space, which may lead to an increase in the size of the bezel portion <NUM>. The size of the through hole <NUM> may be represented by a diameter of the through hole <NUM>.

In consideration of the size of an ultrasonic wave generator or the size of a probe for ultrasound inspection, the through hole <NUM> may have a diameter in a range of about <NUM> to about <NUM>, for example.

The shape of the through hole <NUM> is not particularly limited. The through hole <NUM> may have a circular, oval, semicircular, or polygonal planar shape. For example, the through hole <NUM> may have a quadrangular or pentagonal planar shape.

When ultrasonic waves propagate through an interface between layers respectively including different materials, propagation speed of the ultrasonic wave may change and the ultrasonic wave may be reflected from the interface. For example, in the case where the interlayer <NUM> is disposed in the ultrasonic wave transmission area, a propagation speed of ultrasonic waves may change at an interface between the interlayer <NUM> and another layer, and the ultrasonic waves may be reflected from the interface. Accordingly, when there are a plurality of interlayer interfaces in the ultrasonic wave transmission area, the speed and accuracy of the ultrasound inspection may be degraded.

In particular, in the case where a conductor such as a metal is present in the ultrasonic wave transmission area, ultrasound inspection might not be performed accurately. When a conductor such as a metal is present in the ultrasonic wave transmission area, the propagation speed or the reflection characteristics of the ultrasonic waves may be changed, thereby causing signal disturbance in the ultrasound inspection process.

According to an exemplary embodiment of the present invention, the through hole <NUM> does not overlap a conductor in a space between the window <NUM> and the adhesive layer <NUM>. For example, no conductor is disposed in the area of the through hole <NUM> between the window <NUM> and the adhesive layer <NUM>. Accordingly, more accurate ultrasound inspection is possible.

<FIG> is a cross-sectional view illustrating light irradiation and ultrasonic wave irradiation.

The adhesive layer <NUM> is used to attach the display panel <NUM> and the touch panel <NUM>. The adhesive layer <NUM> is formed by disposing an adhesive composition between the display panel <NUM> and the touch panel <NUM> and then the adhesive layer <NUM> is cured by irradiating the adhesive layer <NUM> with light, such that the adhesive layer <NUM> may have stable adhesive force. As such, the adhesive layer <NUM> having a stable adhesive force resulting from photo-curing is also referred to as a photo-curable adhesive layer.

Referring to <FIG>, the adhesive layer <NUM> may be cured by being irradiated by light L1 through the window <NUM>. In such an exemplary embodiment of the present invention, an ultraviolet light (UV) may be the light L1.

However, the light L1 is blocked at a portion below the bezel portion <NUM>, and thus a portion of the adhesive layer <NUM> below the bezel portion <NUM> might not be sufficiently cured. In order to substantially prevent non-curing below the bezel portion <NUM>, a light L2, e.g., a UV light, may irradiate a side surface of the adhesive layer <NUM>. Because there is a limit in a transmittance of the light L2 radiated to the side surface, a portion of the adhesive layer <NUM> below the bezel portion <NUM>, e.g., in area "A" in <FIG>, might not be sufficiently cured. In the case where the adhesive layer <NUM> is not sufficiently cured, the adhesive layer <NUM> might not achieve a strong adhesive force, and the adhesive force of the adhesive layer <NUM> may be degraded over time.

Accordingly, in order to identify whether or not the adhesive layer <NUM> below the bezel portion <NUM> is sufficiently cured, the ultrasound inspection may be carried out. An ultrasonic wave SS is radiated to a portion below the bezel portion <NUM> for the ultrasound inspection. The adhesive layer <NUM> is irradiated by the ultrasonic wave SS through the through holes <NUM>. In the case where the interlayer <NUM>, e.g., a conductor such as a metal in particular, is absent in the through hole <NUM> between the window <NUM> and the adhesive layer <NUM>, the ultrasound inspection may be stably carried out. To this end, the through hole <NUM> does not overlap the interlayer <NUM> or a conductor in the space between the window <NUM> and the adhesive layer <NUM>.

The size and gap of the through holes <NUM> may vary depending on the size of the display device <NUM>. In addition, a distance from one end of the interlayer <NUM> to the through hole <NUM> may vary depending on a width of the interlayer <NUM>. For example, the distance from one end of the interlayer <NUM> to the center of the through hole <NUM> may be in a range of about <NUM> to about <NUM>.

<FIG> is a partial cross-sectional view illustrating a display device <NUM> according to an exemplary embodiment of the present invention. Referring to <FIG>, at least a portion of the adhesive layer <NUM> may be disposed in a space defined by the through hole <NUM>. For example, curing may be performed after an adhesive composition forming the adhesive layer <NUM> is filled in the through holes <NUM>, such that at least a portion of the adhesive layer <NUM> may fill the through hole <NUM>.

Further, referring to <FIG>, the adhesive layer <NUM> may contact the bezel portion <NUM> through the through hole <NUM>.

<FIG> is a plan view illustrating disposition of a window <NUM> and an interlayer <NUM> according to an exemplary embodiment of the present invention, and <FIG> is a cross-sectional view taken along line III-III' of <FIG>.

Referring to <FIG>, the interlayer <NUM> has a concave portion <NUM>, and the concave portion <NUM> overlaps the bezel portion <NUM>. When viewed on a plane, the concave portion <NUM> may have a concave bay shape. For example, the concave portion <NUM> may be defined by removing a portion of a base portion <NUM> constituting the interlayer <NUM>. For example, the concave portion <NUM> may be defined by a curved boundary of the base portion <NUM>.

Referring to <FIG> and <FIG>, the interlayer <NUM> surrounds a display area DA. The interlayer <NUM> forms a closed loop along an edge of the window <NUM>. Referring to <FIG>, the concave portion <NUM> is open toward the display area DA.

The concave portion <NUM> does not overlap a conductor such as a metal in a space between the window <NUM> and the adhesive layer <NUM>.

Referring to <FIG>, a touch panel <NUM> is disposed between the window <NUM> and an adhesive layer <NUM>. In such an exemplary embodiment of the present invention, the concave portion <NUM> may be adjacent to the touch panel <NUM>.

However, exemplary embodiments of the present invention are not limited thereto. The concave portion <NUM> may be open toward a direction opposite to the display area DA.

A size of the concave portion <NUM> may be defined by a diameter. The concave portion <NUM> may have a diameter in a range of about <NUM> to about <NUM>. The concave portion <NUM> may allow ultrasonic waves to pass therethrough to carry out an ultrasound inspection operation.

In <FIG>, a space defined by the concave portion <NUM> is depicted as not filled with the adhesive layer <NUM>. However, exemplary embodiments of the present invention are not limited thereto, and the space defined by the concave portion <NUM> may be filled with the adhesive layer <NUM>.

For example, at least a portion of the adhesive layer <NUM> may be disposed in a space defined by the concave portion <NUM>. For example, curing may be performed after an adhesive composition forming the adhesive layer <NUM> is filled in the concave portion <NUM>, such that at least a portion of the adhesive layer <NUM> fills the concave portion <NUM>.

<FIG> is a plan view illustrating a display device <NUM> according to an exemplary embodiment of the present invention, <FIG> is a detailed plan view illustrating a portion of <FIG>, and <FIG> is a cross-sectional view taken along line IV-IV' of <FIG>.

Referring to <FIG>, <FIG> and <FIG>, a display device <NUM> according to an exemplary embodiment of the present invention includes a display panel <NUM> having a display area DA and a non-display area NDA, a window <NUM> on the display panel <NUM>, a bezel portion <NUM> disposed on the window <NUM> and overlapping the non-display area NDA, and an adhesive layer <NUM> disposed between the display panel <NUM> and the window <NUM>. The display device <NUM> may further include an interlayer <NUM> disposed between the bezel portion <NUM> and the adhesive layer <NUM>. The interlayer <NUM> may be electrically conductive. The interlayer <NUM> includes, for example, a metal.

The display panel <NUM> includes a first substrate <NUM> and a wiring unit <NUM>. The wiring unit <NUM> includes a plurality of wirings on the first substrate <NUM>. In addition, the wiring unit <NUM> includes a wide gap portion <NUM> defined by two neighbouring wirings w1 and w2. A gap between the two wirings w1 and w2 in the wide gap portion <NUM> is larger than a gap between the two wirings w1 and w2 in an area adjacent to the wide gap portion <NUM>. The wide gap portion <NUM> overlaps the bezel portion <NUM>.

The display device <NUM> illustrated in <FIG> may be an LCD device. However, exemplary embodiments of the present invention are not limited thereto, and the structure illustrated in <FIG> may be applied to an OLED display device or another form of display device.

The display device <NUM> illustrated in <FIG> includes the display panel <NUM> for displaying an image and a data driver <NUM> applying a data voltage to the display panel <NUM>. In such an exemplary embodiment of the present invention, the display panel <NUM> may be an LCD panel.

The display panel <NUM> includes a first substrate <NUM>, a second substrate <NUM> facing the first substrate <NUM>, and a liquid crystal layer LC between the first substrate <NUM> and the second substrate <NUM>. In addition, the display panel <NUM> includes a display area DA for displaying an image and a non-display unit NDA within which no image is displayed.

The wiring unit <NUM> is disposed on the first substrate <NUM>. The wiring unit <NUM> includes a plurality of gate lines GL, a plurality of data lines DL, and other signal lines, and further includes a plurality of thin film transistors ("TFT"). A conductive line, as used herein, may describe the gate line GL, the data line DL, other signal lines, a power line, or the like.

For example, the plurality of gate lines GL and the plurality of data lines DL insulated from and intersecting the plurality of gate lines GL are disposed at the display area DA. In addition, a pixel PX connected to the gate line GL and the data line DL to display an image is disposed at the display area DA.

The gate driver <NUM> is connected to the plurality of gate lines GL and is disposed at the non-display area NDA. The gate driver <NUM> is electrically connected to the plurality of gate lines GL to sequentially apply a gate voltage to the plurality of gate lines GL.

The data driver <NUM> is connected to the plurality of data lines DL and is disposed at the non-display area NDA. The data driver <NUM> includes a plurality of driving circuit boards 320a, 320b, 320c, 320d and 320e. For example, the plurality of driving circuit boards 320a, 320b, 320c, 320d and 320e may be a tape carrier package (TCP) or a chip on film (COF). A plurality of data driving integrated circuits ("ICs") 321a, 321b, 321c, 321d and 321e are mounted on the plurality of driving circuit boards 320a, 320b, 320c, 320d and 320e. The plurality of data driving ICs 321a, 321b, 321c, 321d and 321e are electrically connected to the plurality of data lines DL to apply a data voltage to the plurality of data lines DL.

The display device <NUM> may further include a control printed circuit board ("PCB") <NUM> configured to control driving of the gate driver <NUM> and the plurality of data driving ICs 321a, 321b, 321c, 321d and 321e. The control PCB <NUM> outputs image data and a data control signal for controlling the driving of the plurality of data driving ICs 321a, 321b, 321c, 321d and 321e, and outputs a gate control signal for controlling the driving of the gate driver <NUM>.

The control PCB <NUM> may include a timing controller <NUM> that receives image data from an external source and generates the data control signal and the gate control signal, and a gate control circuit <NUM> that generates the gate control signal. However, exemplary embodiments of the present invention are not limited to such structure.

The timing controller <NUM> controls the driving of the plurality of data driving ICs 321a, 321b, 321c, 321d and 321e and the gate driver <NUM>. The gate control circuit <NUM> generates a clock signal for driving the gate driver <NUM>, a start signal for notifying the start of the gate signal, and the like.

The control PCB <NUM> applies the data control signal and the image data to the plurality of data driving ICs 321a, 321b, 321c, 321d and 321e through the plurality of driving circuit boards 320a, 320b, 320c, 320d and 320e. In addition, the control PCB <NUM> applies the gate control signal to the gate driver <NUM> through a driving circuit board 320a that is adjacent to the gate driver <NUM>.

However, exemplary embodiments of the present invention are not limited thereto, and the plurality of data driving ICs 321a, 321b, 321c, 321d and 321e may be directly mounted in the display panel <NUM>, mounted on a flexible printed circuit film to be attached to the display panel <NUM>, or may be mounted on a separate PCB. In an exemplary embodiment of the present invention, the plurality of data driving ICs 321a, 321b, 321c, 321d and 321e may be integrated with the display panel <NUM>, along with the gate line GL and the TFT. According to an exemplary embodiment of the present invention, the plurality of data driving ICs 321a, 321b, 321c, 321d and 321e, the timing controller <NUM>, and the gate control circuit <NUM> may be integrated into a single chip.

Referring to <FIG> and <FIG>, the plurality of gate lines GL, the plurality of data lines DL, and the plurality of pixels PX are disposed on the first substrate <NUM>.

In addition, a data link wiring 114a, a common voltage wiring unit 115a, a gate link portion 116a, and the gate driver <NUM> are disposed at the non-display area NDA on the first substrate <NUM>. The gate driver <NUM> includes a plurality of stages ST. A pixel electrode PE is disposed at the display area DA on the first substrate <NUM>. A light blocking portion BM, a color filter CF, a common electrode CE, and the like are disposed on the second substrate <NUM>.

The data link wiring 114a extends from the data line DL and electrically connects the data driver <NUM> and the data line DL.

The common voltage wiring unit 115a includes a plurality of common voltage wirings <NUM> arranged to have a uniform gap. One end of the plurality of common voltage wirings <NUM> is connected to a common voltage generator through one common voltage extension wiring 115b.

The plurality of common voltage wirings <NUM> are electrically connected to the common electrode CE.

The gate link portion 116a includes a plurality of signal lines <NUM> between the common voltage wiring unit 115a and the gate driver <NUM>. The gate link portion 116a includes various wirings, for example, a gate start signal line, a plurality of clock signal lines, a forward signal line, a reverse signal line, a reset signal line, a base voltage line and the like. One end of each signal line <NUM> of the gate link portion 116a is connected to the timing controller <NUM> or the gate control circuit <NUM>. Further, another end of each signal line <NUM> of the gate link portion 116a is selectively connected to the gate driver <NUM> through a signal connection wiring 116b.

The gate driver <NUM> is formed together with the TFT of the pixel PX. Such a structure in which the gate driver <NUM> is formed on a substantially same substrate as a substrate on which the TFT of the pixel PX is disposed is also referred to as an amorphous silicon gate (ASG) structure.

The gate driver <NUM> generates a gate signal according to a gate start signal, a plurality of clock signals, a forward signal, a reverse signal, a reset signal, and a base voltage applied from the gate link portion 116a, and applies the gate signal to the gate line GL. The gate driver <NUM> includes a plurality of stages ST connected to the gate lines GL, respectively. The plurality of stages ST apply gate signals to the gate lines GL, respectively. Further, adjacent stages ST are connected to each other by a carry line CL for transmitting a carry signal.

For example, in response to the gate start signal applied from the gate start signal line or a previous stage, each of the plurality of stages ST applies, to the gate line GL, a gate signal which is a clock signal applied from one of the plurality of clock signal lines. The gate line GL is connected to the gate driver <NUM> and applies the gate signal to the pixel PX.

The data lines DL are disposed between the stage ST and the pixels PX. Referring to <FIG>, the data line DL extends in a step-like shape between the stage ST and the pixels PX. However, exemplary embodiments of the present invention are not limited thereto, and the data line DL may extend in a slant or curved shape between the stage ST and the pixels PX.

Referring to <FIG>, the display device <NUM> includes a sealing portion <NUM> sealing the first substrate <NUM> and the second substrate <NUM>. The sealing portion <NUM> is disposed to overlap the light blocking portion BM and to partially overlap the stage ST of the gate driver <NUM>. The sealing portion <NUM> may be formed by a conventional method, using materials conventionally used in the art.

Referring to <FIG>, the common voltage wiring unit 115a and the gate link portion 116a are disposed on the first substrate <NUM>, and a gate insulating layer <NUM>, an insulating interlayer <NUM>, and a protective layer <NUM> are disposed thereon. In addition, the carry line CL connecting respective stages ST is also disposed on a substantially same layer as a layer on which the common voltage wiring unit 115a and the gate link portion 116a are disposed.

Referring to <FIG> and <FIG>, the wide gap portion <NUM> is defined among the signal lines <NUM> constituting the gate link portion 116a. As such, the wide gap portion <NUM> may be defined by the wirings.

For example, the wide gap portion <NUM> may be defined by two wirings W1 and W2 opposing each other with the wide gap portion <NUM> interposed therebetween. Referring to <FIG>, the two wirings W1 and W2 defining the wide gap portion <NUM> are the signal lines <NUM> of the gate link portion 116a. In <FIG>, at least two signal lines among the signal lines <NUM> of the gate link portion 116a define the wide gap portion <NUM>.

A gap between two wirings W1 and W2 in the wide gap portion <NUM> is greater than a gap between the two wirings w1 and w2 in an area adjacent to the wide gap portion <NUM>.

The wide gap portion <NUM> may also be formed in the data link wiring 114a and the common voltage wiring unit 115a.

The shape of the wide gap portion <NUM> is not limited to any particular arrangement. For example, the wide gap portion <NUM> may have a circular, oval, semicircular, or polygonal planar shape. For example, the wide gap portion <NUM> may have a quadrangular or pentagonal planar shape.

Ultrasonic waves may pass through the wide gap portion <NUM> such that the ultrasound inspection may be carried out. Accordingly, the wide gap portion <NUM> becomes an ultrasound inspection area. The ultrasound inspection may determine whether or not the adhesive layer <NUM> located above the wide gap portion <NUM> is properly cured and the ultrasound inspection may additionally determine a degree to which the adhesive layer <NUM> has been cured.

The interlayer <NUM> is disposed below the bezel portion <NUM>. When ultrasonic waves are not smoothly radiated through the window <NUM>, the ultrasonic waves may be radiated to a lower portion of the first substrate <NUM> for the ultrasound inspection. In such an exemplary embodiment of the present invention, the ultrasonic wave SS may be radiated through the wide gap portion <NUM> formed between the plurality of wirings on the first substrate <NUM>.

A size of the wide gap portion <NUM> may be defined as a maximum gap between two wirings W1 and W2 that define the wide gap portion <NUM>. The maximum gap between the two wirings W1 and W2 at the wide gap portion <NUM> may be within a range of about <NUM> to about <NUM>.

The wide gap portion <NUM> might not overlap a conductor in a space between the first substrate <NUM> and the adhesive layer <NUM>. This arrangement may reduce or prevent the ultrasound signal from being disturbed by a conductor such as metal.

Referring to <FIG>, the display device <NUM> includes a touch panel <NUM> disposed between the window <NUM> and the adhesive layer <NUM>. The touch panel <NUM> may be connected to the interlayer <NUM>.

<FIG> is a plan view illustrating pixel arrangement of a display panel according to an exemplary embodiment of the present invention, and <FIG> is a cross-sectional view taken along line V-V' of <FIG>.

In detail, <FIG> and <FIG> illustrate an LCD panel.

The LCD panel illustrated in <FIG> and <FIG> includes a display substrate AS, an opposing substrate US, and a liquid crystal layer LC disposed between the display substrate AS and the opposing substrate US.

The display substrate AS includes a first substrate <NUM>, a TFT, a pixel electrode PE, a gate insulating layer <NUM> and a protective layer <NUM>. The TFT includes a semiconductor layer SM, an ohmic contact layer OC, a gate electrode GE, a source electrode SE and a drain electrode DE.

The first substrate <NUM> may include transparent materials such as glass or plastic.

A plurality of gate lines GL and the gate electrode GE are disposed on the first substrate <NUM>. The gate line GL and the gate electrode GE are integrally formed. The gate line GL and the gate electrode GE may include or be formed of aluminum (Al) or alloys thereof, silver (Ag) or alloys thereof, copper (Cu) or alloys thereof, molybdenum (Mo) or alloys thereof, chromium (Cr), tantalum (Ta), and/or titanium (Ti). At least one of the gate line GL and the gate electrode GE may have a multilayer structure including at least two conductive layers that have different physical properties.

The gate insulating layer <NUM> is disposed over an entire surface of the first substrate <NUM> including the gate line GL and the gate electrode GE. The gate insulating layer <NUM> may include silicon nitride (SiNx) or silicon oxide (SiOx). In addition, the gate insulating layer <NUM> may have a multilayer structure including at least two insulating layers having different physical properties.

The semiconductor layer SM is disposed on the gate insulating layer <NUM>. In such an exemplary embodiment of the present invention, the semiconductor layer SM overlaps the gate electrode GE below the gate insulating layer <NUM>. The semiconductor layer SM may include amorphous silicon, polycrystalline silicon, or the like. The semiconductor layer SM may include an oxide semiconductor.

The ohmic contact layer OC is disposed on the semiconductor layer SM. For example, the ohmic contact layer OC is disposed on the semiconductor layer SM in an area other than a channel area.

Further, a plurality of data lines DL are disposed on the gate insulating layer <NUM>. The data line DL intersects the gate line GL. The source electrode SE and the data line DL are integrally formed. The source electrode SE is disposed on the ohmic contact layer OC. The drain electrode DE is disposed on the ohmic contact layer OC and connected to the pixel electrode PE.

At least one of the data line DL, the source electrode SE and the drain electrode DE may include or be formed of a refractory metal, such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof. Further, at least one of the data line DL, the source electrode SE and the drain electrode DE may have a multilayer structure including a refractory metal layer and a low-resistance conductive layer.

An insulating interlayer <NUM> is disposed over the entire surface of the first substrate <NUM> including the gate insulating layer <NUM>, the semiconductor layer SM, the data line DL, the source electrode SE and the drain electrode DE. The insulating interlayer <NUM> may include an insulating material. The insulating layer <NUM> may protect the channel area and other exposed portions of the semiconductor layer SM.

In one exemplary embodiment of the present invention, a portion from a surface of the first substrate <NUM> to the insulating interlayer <NUM> may be referred to as a wiring unit <NUM>.

The protective layer <NUM> is disposed on the insulating interlayer <NUM>. The protective layer <NUM> serves to planarize an upper portion of the wiring unit <NUM>. Accordingly, the protective layer <NUM> is also referred to as a flattening/planarizing layer.

The protective layer <NUM> may include an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx). According to an exemplary embodiment of the present invention, the protective layer <NUM> may include an organic layer. According to an exemplary embodiment of the present invention, the protective layer <NUM> may have a dual-layer structure including a lower inorganic layer and an upper organic layer.

The pixel electrode PE is disposed on the protective layer <NUM>. According to an exemplary embodiment of the present invention, the pixel electrode PE is connected to the drain electrode DE through a contact hole CH defined through the protective layer <NUM> and the insulating interlayer <NUM>. The pixel electrode PE may include a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).

The opposing substrate US includes a second substrate <NUM>, a color filter layer <NUM><NUM><NUM>, and a common electrode CE. Referring to <FIG>, the opposing substrate US further includes a light blocking portion BM and a passivation layer <NUM>. The passivation layer <NUM> may be disposed between the color filter layer <NUM> and the common electrode CE. The passivation layer <NUM> may be omitted.

The second substrate <NUM> may include transparent materials such as glass or plastic.

The light blocking portion BM is disposed on the second substrate <NUM>. The light blocking portion BM has a plurality of openings. The openings correspond to respective pixel electrodes PE of first, second and third pixels PX1, PX2 and PX3. The light blocking portion BM blocks light except for within the openings. For example, the light blocking portion BM is disposed on the TFT, the gate line GL, and the data line DL. The light blocking portion BM blocks light from passing therethrough and directs light outwardly. The light blocking portion BM may be omitted.

The color filter layer <NUM> is disposed on the second substrate <NUM> and selectively blocks a wavelength of light incident from a backlight unit.

The color filter layer <NUM> includes a color filter CF. For example, the color filter layer <NUM> may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

The first, second, and third color filters CF1, CF2, and CF3 may be distinguished from each other by the light blocking portion BM. Respective ones of the color filters CF1, CF2, and CF3 may be disposed so as to overlap the pixels PX1, PX2, and PX3. For example, each of the color filters CF1, CF2, and CF3 may be located at the opening of the light blocking portion BM corresponding to the pixel electrode PE.

Each of the color filters CF1, CF2, and CF3 may overlap each other.

Referring to <FIG>, the first color filter CF1 may correspond to a red pixel PX1, the second color filter CF2 may correspond to a green pixel PX2, and the third color filter CF3 may correspond to a blue pixel PX3. The color filter layer <NUM> may include a white color filter and may include a color filter having a color other than red, green, and/or blue.

The passivation layer <NUM> is disposed on the color filter layer <NUM>.

The common electrode CE is disposed on the passivation layer <NUM>. For example, the common electrode CE may be disposed over an entire surface of the second substrate <NUM>. The common electrode CE may include a transparent conductive material such as ITO or IZO.

The common electrode CE, along with the pixel electrode PE, applies an electric field over the liquid crystal layer LC. As a result, an electric field is formed over the liquid crystal layer LC between the common electrode CE and the pixel electrode PE.

A lower alignment layer may be disposed on the pixel electrode PE. The lower alignment layer may be a vertical alignment layer, and may include a photoreactive material. An upper alignment layer may be disposed on the common electrode CE. The upper alignment layer may include a substantially same material as that included in the lower alignment layer.

The surfaces of the first substrate <NUM> and the second substrate <NUM> that face each other are defined as upper surfaces of the corresponding substrates and the surfaces on opposite sides of the upper surfaces are respectively defined as lower surfaces of the corresponding substrates. Polarizers may be disposed on the lower surface of the first substrate <NUM> and the lower surface of the second substrate <NUM>, respectively.

<FIG> is a plan view illustrating pixel arrangement of a display panel according to an exemplary embodiment of the present invention, and <FIG> is a cross-sectional view taken along line VI-VI' of <FIG>.

For example, the display panel illustrated in <FIG> and <FIG> is an OLED display panel <NUM>. The OLED display panel <NUM> includes a first substrate <NUM>, a driving circuit unit <NUM>, and an OLED <NUM>.

The first substrate <NUM> may include an insulating material such as glass, quartz, ceramic, plastic, and/or the like. In an exemplary embodiment of the present invention, a polymer film may be used as the first substrate <NUM>.

A buffer layer <NUM> is disposed on the first substrate <NUM>. The buffer layer <NUM> may include one or more layers that may include inorganic layers and/or organic layers. The buffer layer <NUM> may be omitted.

The driving circuit unit <NUM> is disposed on the buffer layer <NUM>. The driving circuit unit <NUM> includes a plurality of TFTs <NUM> and <NUM> and drives the OLED <NUM>. For example, the OLED <NUM> may emit light according to a driving signal applied from the driving circuit unit <NUM>, such that an image may be displayed.

<FIG> and <FIG> illustrate an active matrix-type organic light emitting diode (AMOLED) display device <NUM> having a two-transistor, one capacitor ("2Tr-1Cap") structure. For example, the 2Tr-1Cap structure may include two TFTs, e.g., a switching TFT <NUM> and a driving TFT <NUM>, and one capacitor <NUM> in each pixel. However, exemplary embodiments of the present invention are not limited thereto. For example, the OLED display device <NUM> may include three or more TFTs and two or more capacitors in each pixel, and may further include additional wirings. Herein, the term "pixel" refers to a smallest unit for displaying an image, and the OLED display device <NUM> displays an image using a plurality of pixels.

Each pixel PX includes the switching TFT <NUM>, the driving TFT <NUM>, the capacitor <NUM>, and the OLED <NUM>. In addition, a gate line <NUM> extending along one direction, and a data line <NUM> and a common power line <NUM> insulated from and intersecting the gate line <NUM> are also disposed at the driving circuit unit <NUM>. Each pixel PX may be defined by the gate line <NUM>, the data line <NUM>, and the common power line <NUM> as a boundary, but exemplary embodiments of the present invention are not limited thereto. The pixels PX may be defined by a pixel defining layer <NUM> or a black matrix.

The OLED <NUM> includes a first electrode <NUM>, an organic light emitting layer <NUM> disposed on the first electrode <NUM>, and a second electrode <NUM> disposed on the organic light emitting layer <NUM>. The organic light emitting layer <NUM> includes a low molecular organic material or a high molecular organic material. Holes and electrons are injected into the organic light emitting layer <NUM> from the first electrode <NUM> and the second electrode <NUM>, respectively, and combined therein to form an exciton. The OLED <NUM> emits light when the exciton falls from an excited state to a ground state.

The capacitor <NUM> includes a pair of capacitor plates <NUM> and <NUM>, having an insulating interlayer <NUM> interposed therebetween. In such an exemplary embodiment of the present invention, the insulating interlayer <NUM> may be a dielectric element. A capacitance of the capacitor <NUM> is determined by electric charges accumulated in the capacitor <NUM> and a voltage across the pair of capacitor plates <NUM> and <NUM>.

The switching TFT <NUM> includes a switching semiconductor layer <NUM>, a switching gate electrode <NUM>, a switching source electrode <NUM>, and a switching drain electrode <NUM>. The driving TFT <NUM> includes a driving semiconductor layer <NUM>, a driving gate electrode <NUM>, a driving source electrode <NUM>, and a driving drain electrode <NUM>. A gate insulating layer <NUM> is further disposed to insulate the semiconductor layers <NUM> and <NUM> and the gate electrodes <NUM> and <NUM>.

The switching TFT <NUM> may function as a switching element which selects a pixel to perform light emission. The switching gate electrode <NUM> is connected to the gate line <NUM>, and the switching source electrode <NUM> is connected to the data line <NUM>. Spaced apart from the switching source electrode <NUM>, the switching drain electrode <NUM> is connected to one of the capacitor plates, e.g., the capacitor plate <NUM> and is spaced apart from the switching source electrode <NUM>.

The driving TFT <NUM> applies a driving power to the first electrode <NUM> which is a pixel electrode PE. By applying the driving power, the organic light emitting layer <NUM> may emit light within the selected pixel. The driving gate electrode <NUM> is connected to the capacitor plate <NUM> that is connected to the switching drain electrode <NUM>. Each of the driving source electrode <NUM> and the other of the capacitor plates, e.g., the capacitor plate <NUM>, is connected to the common power line <NUM>. The driving drain electrode <NUM> is connected to the first electrode <NUM> of the OLED <NUM> through a contact hole defined in a planarization layer <NUM>.

With the above-described structure, the switching TFT <NUM> is operated based on a gate voltage applied to the gate line <NUM>. The switching TFT <NUM> serves to transmit a data voltage applied to the data line <NUM> to the driving TFT <NUM>. A voltage equivalent to a difference between a common voltage applied to the driving TFT <NUM> from the common power line <NUM> and the data voltage transmitted by (or from) the switching TFT <NUM> is stored in the capacitor <NUM>. A current corresponding to the voltage stored in the capacitor <NUM> flows to the OLED <NUM> through the driving TFT <NUM> such that the OLED <NUM> may emit light.

The first electrode <NUM> may be a transmissive electrode having light transmittance or a reflective electrode having light reflectivity. The second electrode <NUM> may include a semi-transmissive layer or a reflective layer.

Referring to <FIG>, the first electrode <NUM> is a reflective electrode and the second electrode <NUM> is a semi-transmissive electrode. Light generated in the organic light emitting layer <NUM> is emitted through the second electrode <NUM>. However, exemplary embodiments of the present invention are not limited thereto. For example, the first electrode <NUM> may be a light transmissive electrode, the second electrode <NUM> may be a reflective electrode, and light generated in the organic light emitting layer <NUM> may be emitted through the first electrode <NUM>.

A hole injection layer HIL and/or a hole transporting layer HTL may further be disposed between the first electrode <NUM> and the organic light emitting layer <NUM>. An electron transporting layer ETL and/or an electron injection layer EIL may further be disposed between the organic light emitting layer <NUM> and the second electrode <NUM>. The organic light emitting layer <NUM>, the hole injection layer HIL, the hole transporting layer HTL, the electron transporting layer ETL, and the electron injection layer EIL may each include an organic material, and thus may be referred to as an organic layer.

The pixel defining layer <NUM> has an aperture. The aperture of the pixel defining layer <NUM> exposes a portion of the first electrode <NUM>. The organic light emitting layer <NUM> and the second electrode <NUM> are sequentially stacked on the first electrode <NUM> at the aperture of the pixel defining layer <NUM>. In such an exemplary embodiment of the present invention, the second electrode <NUM> may also be formed on the pixel defining layer <NUM> as well as on the organic light emitting layer <NUM>. In addition, the HIL, the HTL, the ETL, and the EIL may also be disposed between the pixel defining layer <NUM> and the second electrode <NUM>. The OLED <NUM> emits light from the organic light emitting layer <NUM> in the aperture of the pixel defining layer <NUM>. As such, the pixel defining layer <NUM> may define a light emission area.

A capping layer may be disposed on the second electrode <NUM> to protect the OLED <NUM> from the external environment.

A second substrate <NUM> is disposed on the second electrode <NUM>. The second substrate <NUM>, along with the first substrate <NUM>, serves to seal the OLED <NUM>. The second substrate <NUM>, similar to the first substrate <NUM>, may include an insulating material such as glass, quartz, ceramic, plastic, and/or the like.

<FIG> is a cross-sectional view illustrating a display panel according to an exemplary embodiment of the present invention. The display panel illustrated in <FIG> is an OLED display panel <NUM>.

The OLED display panel <NUM> illustrated in <FIG> includes a thin film encapsulation layer <NUM> that is disposed on a second electrode <NUM> to protect an OLED <NUM>.

The thin film encapsulation layer <NUM> includes one or more inorganic layers <NUM> and <NUM> and at least one organic layer <NUM>. These inorganic/organic layers <NUM>, <NUM>, <NUM> may prevent outside air, such as moisture or oxygen, from permeating into the OLED <NUM>.

The thin film encapsulation layer <NUM> may have a structure in which the inorganic layers <NUM> and <NUM> and the organic layer <NUM> are alternately stacked. In <FIG>, the thin film encapsulation layer <NUM> includes two inorganic layers <NUM> and <NUM> and one organic layer <NUM>, but the structure of the thin film encapsulation layer <NUM> is not limited thereto.

Each of the inorganic layers <NUM> and <NUM> may include Al2O3, TiO2, ZrO, SiO2, AlON, AlN, SiON, Si3N4, ZnO, and/or Ta2O5. The inorganic layers <NUM> and <NUM> may be formed through methods such as a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. However, exemplary embodiments of the present invention are not limited thereto, and the inorganic layers <NUM> and <NUM> may be formed using various methods known to those skilled in the art.

The organic layer <NUM> may include a polymer-based material. The polymer-based material may include, for example, an acrylic resin, an epoxy resin, polyimide, and/or polyethylene. In addition, the organic layer <NUM> may be formed through a thermal deposition process. The thermal deposition process for forming the organic layer <NUM> may be performed in a temperature range that might not damage the OLED <NUM>. However, exemplary embodiments are not limited thereto, and the organic layer <NUM> may be formed using various other methods known to those skilled in the pertinent art.

The inorganic layers <NUM> and <NUM> may have a high density and may prevent or efficiently reduce infiltration of contaminants such as moisture or oxygen. Infiltration of moisture and oxygen into the OLED <NUM> may be largely prevented by the inorganic layers <NUM> and <NUM>, even though the inorganic layers <NUM> and <NUM> may be formed as thin films.

Moisture and oxygen that have passed through the inorganic layers <NUM> and <NUM> may further be blocked by the organic layer <NUM>. The organic layer <NUM> may have relatively low moisture-infiltration preventing efficacy, as compared to the inorganic layers <NUM> and <NUM>. However, the organic layer <NUM> may also serve as a buffer layer to reduce stress among respective ones of the inorganic layers <NUM> and <NUM> and the organic layer <NUM>, in addition to the moisture-infiltration preventing function. Further, since the organic layer <NUM> has planarization characteristics, an uppermost surface of the thin film encapsulation layer <NUM> may be planarized by the organic layer <NUM>.

The thin film encapsulation layer <NUM> may have a thickness of about <NUM>µm or less. Accordingly, the OLED display device <NUM> may also be relatively thin. By applying the thin film encapsulation layer <NUM> in such a manner, the OLED display device <NUM> may be flexible.

In the case where the second substrate <NUM> is omitted and a flexible substrate is used as the first substrate <NUM>, the OLED display panel <NUM> may be used in a flexible display device.

As set forth herein, in one or more exemplary embodiments of the present invention, the display device has an ultrasonic wave transmission area for confirming whether or not an adhesive layer is cured. Accordingly, curing of the adhesive layer may be confirmed by radiating ultrasonic waves through the ultrasonic wave transmission area.

Claim 1:
A display device comprising:
a display panel (<NUM>) having a display area (DA) and a non-display area (NDA);
a window (<NUM>) disposed on the display panel;
a photocurable adhesive layer (<NUM>) disposed between the display panel (<NUM>) and the window (<NUM>); and
a light shielding pattern (<NUM>) positioned over the non-display area (NDA) and between the window (<NUM>) and the photocurable adhesive layer (<NUM>),
wherein the light shielding pattern (<NUM>) has at least one ultrasound transmitting area (<NUM>, <NUM>),
wherein the at least one ultrasound transmitting area (<NUM>, <NUM>) overlaps the photocurable adhesive layer (<NUM>) in a plan view,
wherein the at least one ultrasound transmitting area (<NUM>, <NUM>) is a through hole (<NUM>, <NUM>), and
characterised in that
the through hole (<NUM>, <NUM>) has a diameter in the range of about <NUM> to about <NUM>.