Patent Description:
High-voltage semiconductor technology is applied to integrated circuits (ICs) with high voltage and high power. Traditional high-voltage semiconductor devices, such as lateral diffused MOSFETs (LDMOSFETs), are mainly used for devices with at least <NUM> volts or higher. The advantages of high-voltage device technology include cost effectiveness and process compatibility, and thus high-voltage device technology has been widely used in display driver IC devices, and power supply devices, and power management, communications, autotronics, and industrial control fields, etc..

<FIG> is a cross section of a conventional n-type LDMOSFET. The n-type LDMOSFET <NUM> includes a p-type semiconductor substrate <NUM> and a p-type epitaxial layer <NUM> thereon. A gate structure <NUM> and a field oxide layer <NUM> are on the p-type epitaxial layer <NUM>. Moreover, a p-type body region <NUM> and an n-type drift region <NUM> are respectively in the p-type epitaxial layer <NUM> on both sides of the gate structure <NUM>. The n-type drift region <NUM> further extends into the underlying p-type semiconductor substrate <NUM>. A p-type contact region <NUM> and an adjacent n-type contact region <NUM> (or both referred to as a source region) are in the body region <NUM> and an n-type contact region <NUM> (or referred to as a drain region) is in the drift region <NUM>. Moreover, a source electrode <NUM> is electrically connected to the p-type contact region <NUM> and the n-type contact region <NUM>. A drain electrode <NUM> is electrically connected to the n-type contact region <NUM>. A gate electrode <NUM> is electrically connected to the gate structure <NUM>.

In such an n-type LDMOSFET <NUM>, however, the source region is electrically connected to the underlying p-type semiconductor substrate <NUM> via the body region <NUM>. Therefore, the body effect is induced to change the threshold voltage of the transistor <NUM> when the source region is coupled to an internal circuit or resistor. As a result, the driving current of the transistor <NUM> is reduced with increasing the voltage applied to the source region, and thus the performance of the transistor <NUM> is reduced.

<CIT> relates to a semiconductor device that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.

<CIT> relates to semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.

<CIT> relates to a device which includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.

<CIT> relates to a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device is formed in a first conductive type substrate, and includes a second conductive type high voltage well, a field oxide region, a gate, a second conductive type source, a second conductive type drain, a first conductive type body region, and a first conductive type deep well. The deep well is formed beneath and adjacent to the high voltage well in a vertical direction. The deep well and the high voltage well are defined by a same lithography process step.

Therefore, there is a need to develop a high-voltage semiconductor device and a method for manufacturing the same that are capable of addressing or mitigating the problems described above.

According to the invention a high-voltage semiconductor device having the features of claim <NUM> is provided. Further, the invention provides a method for fabricating a high-voltage semiconductor device having the features of claim <NUM>.

The present disclosure can be further understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:.

The following description is of the best-contemplated mode of carrying out the disclosure. This description is made for the purpose of illustrating the general principles of the disclosure and should not be taken in a limiting sense. These are, of course, merely examples and are not intended to be limited. In addition, the disclosure may repeat reference numerals and/or letters in the various examples.

An exemplary embodiment of the present disclosure provides a high-voltage semiconductor device, such as an LDMOSFET, which utilizes a doping region having a conductivity type different from that of the body region to isolate the body region from the substrate that has the same conductivity type as that of the body region, thereby reduce or eliminate the body effect.

Refer to <FIG>, which is a cross section of an illustrative example of a high-voltage semiconductor device <NUM>. In the example, the high-voltage semiconductor device <NUM> may be an LDMOSFET. The high-voltage semiconductor device <NUM> includes a semiconductor substrate <NUM>, such as a silicon substrate, a SiGe substrate, a bulk semiconductor substrate, a compound semiconductor substrate, a silicon-on-insulator (SOI) substrate, or another well-known semiconductor substrate, having a first conductivity type.

Moreover, the semiconductor substrate <NUM> includes a first doping region <NUM> (such as a high-voltage well region) therein. The first doping region <NUM> is adjacent to the upper surface of the semiconductor substrate <NUM>. The first doping region <NUM> has a conductivity type different from the first conductivity type. For example, the first conductivity type is p-type and the second conductivity type is n-type. In some embodiments, the first conductivity type is n-type and the second conductivity type is p-type.

In the illustrative example, the high-voltage semiconductor device <NUM> further includes an epitaxial layer <NUM> that is formed on the semiconductor substrate <NUM> and has the first conductivity type. The epitaxial layer <NUM> includes a plurality of field insulating layers <NUM> that serves as an isolation structure. In one embodiment, the field insulating layer <NUM> is a field oxide. In one example, the field insulating layer <NUM> includes a local oxidation of silicon (LOCOS) structure. In some embodiments, the field insulating layer <NUM> includes a shallow trench isolation (STI) structure.

In the illustrative example, the high-voltage semiconductor device <NUM> further includes a body region <NUM> having the first conductivity type and second and third doping regions 212a and 212b having the second conductivity type. The body region <NUM> is in the epitaxial layer <NUM> over the first doping region <NUM> and extends from the upper surface of the epitaxial layer <NUM> to the lower surface thereof, so that the bottom of the body region <NUM> may adjoin to the first doping region <NUM>. Moreover, the second and third doping regions 212a and 212b are in the epitaxial layer <NUM> on both opposite sides of the body region <NUM>, respectively, to adjoin the body region <NUM>. In the illustrative example, the second and third doping regions 212a and 212b are disposed over the first doping region <NUM> and extend from the upper surface of the epitaxial layer <NUM> to the lower surface thereof, so that the bottom of the second and third doping regions 212a and 212b may adjoin to the first doping region <NUM>. In one embodiment, an exterior edge E2 of the third doping region 212b is aligned with a corresponding exterior edge E1 of the first doping region <NUM>. Moreover, the third doping region 212b has a width W in a range of about <NUM> to <NUM>.

According to the invention, the first doping region <NUM> has the same doping concentration as that of the second and third doping regions 212a and 212b. In this case, the first doping region <NUM> and the second and third doping regions 212a and 212b are high-voltage well regions. Moreover, the second and third doping regions 212a and 212b may be formed by separating a high-voltage well region via the body region <NUM> or be individual high-voltage well regions formed in the epitaxial layer <NUM>. According to the invention, the high-voltage well region has a doping concentration in a range of about <NUM> × <NUM><NUM> to <NUM> × <NUM><NUM> ions/cm<NUM>. In different examples not being part of the invention, the first doping region <NUM> has a doping concentration that is the same as that of the second doping region 212a and different from that of the third doping region 212b. In these cases, the first doping region <NUM> and the second doping region 212a are high-voltage well regions and the third doping region 212b is a well region. The well region (i.e., the third doping region 212b) has a doping concentration greater than that of the high-voltage well region (i.e., the first doping region <NUM> or the second doping region 212a). Namely, the second and third doping regions 212a and 212b may be formed by separating a high-voltage well region via the body region <NUM> or be a high-voltage well region and a well region that are respectively formed in epitaxial layer <NUM>. In one example, the high-voltage well region has a doping concentration in a range of about <NUM> × <NUM><NUM> to <NUM> × <NUM><NUM> ions/cm<NUM>, and the well region has a doping concentration in a range of about <NUM> × <NUM><NUM> to <NUM> × <NUM><NUM> ions/cm<NUM>. In the example, the first doping region <NUM>, the second doping region 212a, and the third doping region 212b serve as a drift region of the LDMOSFET.

According to the invention, the high-voltage semiconductor device <NUM> further includes a source region <NUM>, a drain region <NUM>, and a gate structure <NUM>. The source region <NUM> and the drain region <NUM> are respectively disposed in the body region <NUM> and the second doping region 212a. The source region <NUM> is formed of a doping region <NUM> having the second conductivity type and a doping region (which serves as a body contact region) <NUM> having the first conductivity type. Moreover, the drain region <NUM> is merely formed of a doping region having the second conductivity type. Furthermore, the gate structure <NUM> is disposed on the epitaxial layer <NUM> and covers a portion of the field insulating layer <NUM>, in which this field insulating layer <NUM> is formed in the second doping region 212a between the source region <NUM> and the drain region <NUM>. The gate structure <NUM> typically includes a gate dielectric layer <NUM> and a gate layer <NUM> on the gate dielectric layer <NUM>.

According to the invention, the high-voltage semiconductor device <NUM> may include a field reduction region <NUM> having the first conductivity type that is disposed in the second doping region 212a below the field insulating layer <NUM> under the gate structure <NUM>, so as to reduce surface field. The field reduction region <NUM> has a doping concentration of about <NUM> × <NUM><NUM> ions/cm<NUM>.

The high-voltage semiconductor device <NUM> further includes an interlayer dielectric (ILD) layer <NUM>. Interconnect structures <NUM>, <NUM>, and <NUM> are in the ILD layer <NUM>. The interconnect structure <NUM> is electrically connected to the source region <NUM> to serve as a source electrode, the interconnect structure <NUM> is electrically connected to the drain region <NUM> to serve as a drain electrode, and the interconnect structure <NUM> is electrically connected to the gate structure <NUM> to serve as a gate electrode.

Refer to <FIG> and <FIG>, which are cross sections of high-voltage semiconductor devices <NUM> and <NUM>, respectively, according to illustrative examples. Elements in <FIG> and <FIG> that are the same as or similar to those in <FIG> are not described again, for brevity. In <FIG>, the high-voltage semiconductor device <NUM> has a structure that is similar to that of the high-voltage semiconductor device <NUM> (shown in <FIG>). The difference is that the exterior edge E2 of the third doping region 212b in the high-voltage semiconductor device <NUM> is not aligned with the corresponding exterior edge E1 of the first doping region 212a. For example, the exterior edge E2 laterally extends beyond the exterior edge E1.

In <FIG>, the high-voltage semiconductor device <NUM> has a structure that is similar to that of the high-voltage semiconductor device <NUM> (shown in <FIG>). The difference is that the exterior edge E2 of the third doping region 212b in the high-voltage semiconductor device <NUM> is not aligned with the corresponding exterior edge E1 of the first doping region 212a. For example, the exterior edge E1 laterally extends beyond the exterior edge E2.

Refer to <FIG>, which is a cross section of a high-voltage semiconductor device <NUM> according to an embodiment of the present disclosure. Elements in <FIG> that are the same as or similar to those in <FIG> are not described again, for brevity. In the embodiment, the high-voltage semiconductor device <NUM> has a structure that is similar to that of the high-voltage semiconductor device <NUM> (shown in <FIG>). The difference is that the high-voltage semiconductor device <NUM> further includes a buried layer <NUM> having the second conductivity type that is in first doping region <NUM> below the body region <NUM>, so that the bottom of the body region <NUM> adjoins the upper surface of the buried layer <NUM>. Moreover, the buried layer <NUM> has a doping concentration of about <NUM> × <NUM><NUM> ions/cm<NUM>. In the embodiment, the second doping region 212a and the third doping region 212b are high-voltage well regions or a high-voltage well region and a well region, respectively. In one example, the second conductivity type is n-type and the buried layer <NUM> is an n+ buried layer (NBL).

Refer to <FIG>, which is a cross section of a high-voltage semiconductor device <NUM> according to an illustrative example. Elements in <FIG> that are the same as or similar to those in <FIG> are not described again, for brevity. The high-voltage semiconductor device <NUM> has a structure that is similar to that of the high-voltage semiconductor device <NUM> (shown in <FIG>). The difference is that the high-voltage semiconductor device <NUM> utilizes a buried layer <NUM> having the second conductivity type that is disposed below the body region <NUM> to replace the first doping region <NUM> in the high-voltage semiconductor device <NUM>, so that the bottom of the body region <NUM> adjoins the upper surface of the buried layer <NUM>. The second doping region 212a and the third doping region 212b are high-voltage well regions or a high-voltage well region and a well region, respectively.

Next, refer to <FIG>, which are cross sections of a method for fabricating a high-voltage semiconductor device <NUM> according to illustrative examples. In <FIG>, a semiconductor substrate <NUM> having a first conductivity type is provided. The semiconductor substrate <NUM> may be a silicon substrate, a SiGe substrate, a bulk semiconductor substrate, a compound semiconductor substrate, an SOI substrate, or another well-known semiconductor substrate.

Next, a first doping region <NUM>, such as a high-voltage well region, may be formed in the semiconductor substrate <NUM> by an ion implantation process and a thermal process. The first doping region <NUM> is adjacent to the upper surface of the semiconductor substrate <NUM>. The first doping region <NUM> has a second conductivity type different from the first conductivity type. For example, the first conductivity type is p-type and the second conductivity type is n-type. The first conductivity type could be n-type and the second conductivity type could be p-type.

Next, Refer to <FIG>, an epitaxial layer <NUM> having the first conductivity type is formed on the semiconductor substrate <NUM> by an epitaxial growth process. Next, a doping region having the second conductivity type, such as a high-voltage well region <NUM>, may be formed in the epitaxial layer <NUM> by an ion implantation process and a thermal process. The high-voltage well region <NUM> and the first doping region <NUM> have a doping concentration in a range of about <NUM> × <NUM><NUM> to <NUM> × <NUM><NUM> ions/cm<NUM>.

Next, refer to <FIG>, field insulating layers <NUM> serving as isolation structures are formed in the epitaxial layer <NUM>, in which at least one of the field insulating layers <NUM> is formed in the high-voltage well region <NUM>. The field insulating layer <NUM> could include a LOCOS structure or an STI structure. The high-voltage well region <NUM> that has the second conductivity type may be formed in the epitaxial layer <NUM> after the field insulating layers <NUM> are formed.

Next, refer to <FIG>, a body region <NUM> having the first conductivity type may be formed in the high-voltage well region <NUM> of the epitaxial layer <NUM> by an ion implantation process and a thermal process, thereby dividing the high-voltage well region <NUM> into a second doping region 212a and a third doping region 212b that have the second conductivity type and the same doping concentration. As shown in <FIG>, the body region <NUM> is formed in the epitaxial layer <NUM> on the first doping region <NUM> and extends from the upper surface of the epitaxial layer <NUM> to the lower surface thereof, so that the bottom of the second and third doping regions 212a and 212b may adjoin to the first doping region <NUM>. An exterior edge E2 of the third doping region 212b is aligned with a corresponding exterior edge E1 of the first doping region <NUM>. Moreover, the third doping region 212b has a width W in a range of about <NUM> to <NUM>. The second and third doping regions 212a and 212b may be formed by the respective ion implantation processes before or after the body region <NUM> is formed.

In these cases, the second doping region 212a has a doping concentration that is the same as that of the first doping region <NUM> and the third doping region 212b. For example, the first doping region <NUM>, the second doping region 212a, and the third doping region 212b are high-voltage well regions, and have a doping concentration in a range of about <NUM> × <NUM><NUM> to <NUM> × <NUM><NUM> ions/cm<NUM>. Alternatively, the second doping region 212a has a doping concentration that is the same as that of the first doping region <NUM> and is different from that of the third doping region 212b. For example, the first doping region <NUM> and the second doping region 212a are high-voltage well regions and have a doping concentration in a range of about <NUM> × <NUM><NUM> to <NUM> × <NUM><NUM> ions/cm<NUM>. Moreover, the third doping region 212b is a well region and has a doping concentration in a range of about <NUM> × <NUM><NUM> to <NUM> × <NUM><NUM> ions/cm<NUM>. Namely, the doping concentration of the third doping region 212b is higher than that of the first doping region <NUM> and the second doping region 212b.

Refer to <FIG>, a field reduction region <NUM> having the first conductivity type that is formed in the second doping region 212a and below the field insulating layer <NUM>, so as to reduce surface field. The field reduction region <NUM> has a doping concentration of about <NUM> × <NUM><NUM> ions/cm<NUM>. Next, a gate structure <NUM> may be formed by a conventional MOS process, in which the gate structure <NUM> partially covers the field insulating layer <NUM> above the field reduction region <NUM>. The gate structure <NUM> typically includes a gate dielectric layer <NUM> and a gate layer <NUM> on the gate dielectric layer <NUM>.

Next, refer to <FIG>, a source region <NUM> is formed in the body region <NUM>, and a drain region <NUM> is formed in the second doping region 212a. The source region <NUM> is formed of a doping region <NUM> having the second conductivity type and a doping region (which serves as a body contact region) <NUM> having the first conductivity type. Moreover, the drain region <NUM> is merely formed of a doping region having the second conductivity type.

Next, refer to <FIG>, a metallization layer is formed on the epitaxial layer <NUM> by a conventional metallization process to cover the gate structure <NUM>. As a result, the high-voltage semiconductor device <NUM> is completed. The metallization layer may include an ILD layer <NUM> and interconnect structures <NUM>, <NUM>, and <NUM> in the ILD layer <NUM>. The interconnect structure <NUM> is electrically connected to the source region <NUM> to serve as a source electrode, the interconnect structure <NUM> is electrically connected to the drain region <NUM> to serve as a drain electrode, and the interconnect structure <NUM> is electrically connected to the gate structure <NUM> to serve as a gate electrode.

It should be understood that the high-voltage semiconductor devices <NUM>, <NUM>, <NUM>, and <NUM> respectively shown in <FIG> can be fabricated by a method that is the same as or similar the method shown in <FIG>.

Claim 1:
A high-voltage semiconductor device (<NUM>), comprising:
a semiconductor substrate (<NUM>) having a first conductivity type;
a first doping region (<NUM>) having a second conductivity type in the semiconductor substrate (<NUM>);
an epitaxial layer (<NUM>) on the semiconductor substrate (<NUM>);
a body region (<NUM>) having the first conductivity type in the epitaxial layer (<NUM>) on the first doping region (<NUM>) ;
a second doping region (212a) and a third doping region (212b) that have the second conductivity type, respectively in the epitaxial layer (<NUM>) on both opposite sides of the body region (<NUM>), so as to adjoin the body region (<NUM>);
a source region (<NUM>) and a drain region (<NUM>) respectively in the body region (<NUM>) and the second doping region (212a);
a field insulating layer (<NUM>) in the second doping region (212a) between the source region (<NUM>) and the drain region (<NUM>); and
a gate structure (<NUM>) on the epitaxial layer (<NUM>) to cover a portion of the field insulating layer (<NUM>), characterized by
the first doping region (<NUM>), the second region (212a) and the third doping region (212b) having a doping concentration in a range of <NUM>×<NUM><NUM> to <NUM>×<NUM><NUM> ions/cm<NUM>; and
a buried layer (<NUM>) having the second conductivity type in the first doping region (<NUM>) below the body region (<NUM>), so that the bottom of the body region (<NUM>) adjoins the upper surface of the buried layer (<NUM>), wherein the buried layer (<NUM>) has a doping concentration of <NUM>×<NUM><NUM> ions/cm<NUM>.