Patent Description:
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

For example, such scaling has led to a rise in use of directed self-assembly (DSA) semiconductor patterning instead of lithography. DSA patterning enables fine pitches using block copolymers. In DSA, a lithography system forms a pre-defined pattern on a structure, and the pattern is coated with block copolymers, which then self-assemble on the pattern to form the small patterns, such as lines and spaces. One example use of DSA is the formation of transition regions on a semiconductor die that are used to separate active regions containing semiconductor devices. The current layout design of the transition regions when fabricated using DSA typically leads to formation of undesirable horizontal morphology as a result of parallel orientation of BCP microdomain), rather than vertical microdomain orientation. Of major concern is that horizontal morphology (polymer sheets of alternating blocks) lead to left behind polymer on the die/wafer that lead to downstream reliability and defect concerns.

<CIT> describes a pattern including first and second block phases that is formed by self-assembling a block copolymer onto a film to be processed.

Embodiments of the invention are described in the dependent claims.

According to an embodiment, the method according to the invention further comprises configuring the first threshold to be approximately. <NUM> times a grating pitch.

According to an embodiment, the method further comprises configuring the second threshold to be approximately +/-<NUM>% of the BCP pitch for A-B-A type copolymers.

According to an embodiment, the method further comprises after identifying areas having non-uniform gratings the method further comprises at least one of: the modifying the one or more layout designs for the areas, and selectively grafting either PS or PMMA onto a metal of the non-uniform gratings and grafting a neutral polymer component onto an ILD of the non-uniform gratings.

In an example not forming part of the literal wording of the claims granted a method of fabricating an integrated structure (IC) using direct self-assembly (DSA) comprises receiving a substrate with one or more active regions separated by transition regions. Block copolymers are received that are Lamellae-forming. One or more gratings on the substrate, wherein the grating pitch is within <NUM>% of the BCP pitch for A-B type copolymers or <NUM>% of the BCP pitch for A-B-A type copolymers. A block copolymer DSA solution is deposited on the substrate and the gratings. The DSA solution is annealed, and one of the block copolymers is removed. Trenches are etched in the material previously covered by the first copolymer. A metal is deposited in the etched trenches and planarizing to define the structures including traces or interconnects. Further die processing is performed.

According to said example, the method further comprises: utilizing polystyrene-b-polymethylmethacrylate (PS-b-PMMA) as the block copolymer, the block copolymer comprising a PS component and a PMMA component.

According to said example, the PS component is assembled over conductive layers, and wherein the PMMA component is assembled over insulating layers.

According to said example, the PS component is alternatively assembled over the insulating layers, and wherein and the PMMA component is assembled over the conductive layers.

According to said example, alternatively, one of the PS component and the PMMA component is assembled over conductive layers, and wherein a neutral component is assembled over insulating layers to reduce formation of parallel horizontal block copolymer structures.

Materials and layout design options for direct self-assembly (DSA) on transition regions over active die are described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than <NUM> metal layers may be added in the BEOL.

Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

Some semiconductor processing uses photoresist to define conductive traces in the electrically active regions. In such a method, photoresist is applied to the substrate, patterned, and then developed to remove the non-polymerized resist and leave behind a mask pattern for the desired structure. A limitation of some photo-resist methods is that the tightest pitch is generally about <NUM> or greater for lithography utilizing an argon-fluoride (ArF) laser, and about <NUM> for extreme ultraviolet (EUV) lithography. This pitch is disfavored in some situations because it consumes large areas on the die or integrated circuit. One possible approach is to use a directed self-alignment (DSA) copolymer solution to achieve even tighter pitches for conductive traces or interconnects and other structures.

In accordance with one or more embodiments of the present invention, fabrication processes are described for materials and layout design options for direct self-assembly (DSA) on transition regions over active die to eliminate DSA sheets in the transition regions. One or more embodiments described herein are directed to integrated circuit structures formed with DSA approaches in which active regions and transition regions are formed on a die. The active regions comprise uniform gratings of metal and dielectric materials that are DSA compatible and consist of vertically aligned structures, while the transition regions comprise at least one of uniform gratings having vertical aligned structures, and non-uniform gratings having vertical random structures (referred to as fingerprints). Both the active regions and the transition regions have an absence of non-uniform gratings with horizontal parallel polymer sheets thereon, which are known to cause defects. In an embodiment, the uniform gratings are provided by analyzing layout designs for the active regions and the transition regions to identify areas having non-uniform gratings that are not compatible with DSA. The layout designs for the non-uniform gratings are made uniform, and thus DSA compatible, by insertion of dummy structures in the layout designs to convert the non-uniform gratings to DSA compatible uniform gratings in order to form the vertical aligned or vertical random structures, but not horizontal DSA sheets during fabrication. In accordance with one or more embodiments of the present disclosure, such an architecture of the fabrication process enables DSA to solve critical interconnect formation problems in future technology nodes.

To provide context, <FIG> illustrates a perspective view of a die <NUM> having active regions <NUM> separated by a transition region <NUM>. The active regions <NUM> and the transition region <NUM> may be formed in semiconductor material layers <NUM> and/or base <NUM>. Each active region <NUM> may include conductive structures that extend from a metallization layer <NUM> to one or more of the semiconductor material layers <NUM>. The active region <NUM> may contain one or more active semiconductor devices (e.g., transistors, diodes), passive devices (e.g., resistors, capacitors, inductors), and interconnects assembled to form an integrated circuit. The active region <NUM> can include devices and interconnects that are diffused, implanted, deposited, or otherwise formed in layers of semiconductor materials on the base <NUM>. In contrast, the transition region <NUM> contains only inactive structures (e.g., traces). The die <NUM> may optionally include a guard ring structure <NUM>. Via <NUM> layers <NUM> and metallization layers <NUM> are formed on top of the semiconductor material layers <NUM> and generally include a dielectric material. The base <NUM> can comprise, for example, a bulk semiconductor wafer (e.g., silicon) or a substrate material (e.g., sapphire).

<FIG> illustrates that the active regions <NUM> and the transition regions <NUM> are defined by a layout design specifying respective gratings of alternating conductive layers (e.g., metal) and insulating layers (e.g., an interlayer dielectric (ILD)), hereinafter referred to as metal gratings <NUM>. In this example, the active regions <NUM> have different grating pitches, which would break the metal gratings <NUM> if the active regions <NUM> were placed side-by-side, necessitating use of transition region <NUM> to separate the active regions <NUM>.

According to the disclosed embodiments, structures or features are fabricated on the active regions <NUM> and the transition regions <NUM> by utilizing a direct self-assembly (DSA) processing sequence. DSA utilizes principles of chemoepitaxy and graphoepitaxy to deposit a block copolymer (BCP) comprising first and second polymer components onto an incoming metal gratings <NUM>. In one embodiment, the polymer components may comprise A-B type BCP materials, or A-B-A or A-B-C type BCP materials. In one example embodiment, the polymer components may comprise a polystyrene (PS) component and a polymethylmethacrylate (PMMA) component. For a description of A-B-A type BCP materials, refer to <CIT> (<CIT>) titled "GRATING LAYER WITH VARIABLE PITCH FORMED USING DIRECTED SELF-ASSEMBLY OF MULTIBLOCK COPOLYMERS.

<FIG> graphically illustrates that the pattern of the gratings <NUM> may be replicated by DSA components by selectively grafting the first polymer component (e.g., PS) onto the metal and the second polymer component (e.g., PMMA) onto the ILD. Once the two polymer components are annealed, the polymer components will segregate depending on the fractions of the first polymer component relative to the second polymer component, causing the block copolymers to self-align along guide structures, such as metal grating, photoresist or other material. Molecules of the DSA block copolymers consistently align in alternating lines of a single consistent BCP pitch to form a DSA grating <NUM>. In one embodiment, block copolymers can be formulated in a symmetric <NUM>:<NUM> volume ratio that produces Lamellar self-assembled domains. In other embodiments, a <NUM>:<NUM> or <NUM>:<NUM> blend may be used. In one embodiment, the block copolymers are configured to produce alternating lines of PS and PMMA with a BCP pitch of less than <NUM>, for example <NUM>-<NUM>.

Once the DSA grating <NUM> is formed, one of the block copolymers, such as PMMA, is removed from the DSA grating <NUM> and the remaining block copolymer (e.g., PS) can be used as a mask <NUM> for subsequent lithographic processing to replicate the pattern of the DSA grating <NUM>. In one example, the DSA grating <NUM> can be replaced with the mask <NUM>, which can then be replaced with a conductive material for via formation in selected areas. As another example, using the first polymer as a mask, channels can be etched into the substrate and then filled with a metal (or other conductive material) to define structures or features, such as interconnects for example in both the active regions <NUM> and the transition regions <NUM> of <FIG>.

<FIG> illustrate possible BCP orientations that may result from the DSA process. Referring to <FIG>, when the grating pitch <NUM> of the metal grating 120A is close to or otherwise compatible to the BCP pitch <NUM> of the DSA grating, the DSA process provides aligned vertical BCP structures 130A. In one aspect of the present embodiments, aligned vertical BCP structures 130A is the desirable result when forming structures in both the active regions <NUM> and the transition regions <NUM> of <FIG>.

However, a general challenge with DSA is that the molecules of the copolymers orient poorly along wide metal or ILD areas having dimensions that exceed a threshold compared to the self-assembled BCP pitch <NUM> and produce orientations considered defects, as shown in <FIG> and <FIG>.

<FIG> shows that when the grating pitch <NUM> of the metal grating 120B is still uniform, but does not match the BCP pitch <NUM> of the DSA grating and the ratio of metal to ILD is close to <NUM>:<NUM>, the DSA process provides random vertical BCP structures 130B called fingerprints. In one aspect of the present embodiments, random vertical BCP structures130B or fingerprints resulting from the DSA process is acceptable in the transition regions <NUM> of <FIG>.

<FIG> shows that when the surface area of either the metal or the ILD in the metal grating 120C is significantly larger than the other, or has a dimension that exceeds a threshold compared to the BCP pitch <NUM>, then the molecules of the copolymers orient poorly in wide areas, and the copolymers tend to provide parallel horizontal BCP structures 130C, referred to as parallel horizontal polymer sheets or just polymer sheets. In one aspect of the present embodiments, parallel horizontal BCP structures 130B or polymer sheets is a result of DSA that is unacceptable when forming structures in either the active regions <NUM> or the transition regions <NUM> of <FIG>.

<FIG> illustrate uniform gratings that are compatible with the BCP pitch <NUM>, while <FIG> illustrates examples of non-uniform gratings that are incompatible with the BCP pitch <NUM>. The vertical random BCP structure 130B or fingerprints is acceptable because after the DSA process, one of the aligned random PS and PMMA components is removed (e.g., PMMA) to create a PS-only grating. A down flow process is then able to insert a metal or other material between these PS piers to form an IC structure, such as a conductive trace or interconnect. The parallel horizontal BCP structures 130C or polymer sheets of <FIG> are not acceptable because the down flow process can only remove one of the BCP components as the other will be covered. The down flow process simply deposits a nitride or oxide film on top of the remaining horizontal polymer sheet, which remains in the completed IC. An example of a polymer sheet defect within a completed IC is shown in <FIG>.

<FIG> illustrate an IC <NUM> fabricated with DSA in a manner that results in the presence of a polymer sheet defect. <FIG> illustrates a top view of an IC <NUM> and an enlarged view <NUM> shows active regions 502A and 502B (collectively referred to as active regions <NUM>) separated by a transition region <NUM>. <FIG> illustrates a cross-section view of the transition region <NUM>, which includes polymer sheet <NUM>. As can be seen, the active regions <NUM> were designed with uniform gratings <NUM> that were easily replicated by DSA process to create aligned vertical BCP structures used to create a uniform pattern of actual metal/ILD interconnects. However, the transition region <NUM> was designed with a non-uniform grating <NUM> that has relatively large breaks. The breaks are too wide for the DSA process to follow and results in the formation of a polymer sheet <NUM>. Since such horizontal structures are not easily removed, a significant amount of polymer is left on the wafer during down flow processing. Down flow processes are high temperature processes and resultant polymer out flow gases can cause delamination and other problems for the IC.

According to the disclosed embodiments, materials and layout design options for DSA fabrication of integrated circuits in a manner that significantly reduces or eliminates the presence of polymer sheets is described. One or more embodiments described herein are directed to integrated circuit structure (IC) formed with DSA approaches in which active regions and transition regions are formed on a die. The active regions comprise uniform gratings of metal and dielectric materials that are DSA compatible and consist of vertically aligned structures, while the transition regions comprise at least one of uniform gratings having vertical aligned structures, and non-uniform gratings having vertical random structures (referred to as fingerprints). Both the active regions and the transition regions have an absence of non-uniform gratings with horizontal parallel polymer sheets thereon, which are known to cause defects.

<FIG> illustrate IC <NUM> fabricated with DSA in a manner that significantly reduces or eliminates the presence of polymer sheets. <FIG> illustrates a top view of the IC <NUM> through the BCP so that the pattern of underlying metal/ILD grating <NUM> and <NUM> are shown in an active region <NUM> and an adjacent transition region <NUM>. <FIG> illustrates a cross-section of the active region <NUM>, and <FIG> illustrates a cross-section view of the transition region <NUM>.

Vertical aligned structures <NUM> and the vertical random structures <NUM> may result from one of the BCP components being removed and replaced with first a hard mask (e.g., oxide, nitride, carbon hard mask material and the like), which will then be replaced with a metal or other conductive material, such as aluminum, copper, titanium, or other suitable metal for via formation, for example. The present disclosure contemplates the vertical aligned structures <NUM> and the vertical random structures <NUM> being formed in, or including, one or more layers of an integrated circuit architecture. For example, the vertical aligned structures <NUM> and the vertical random structures <NUM> can be formed on a base layer or substrate, formed in a semiconductor material layer common to various semiconductor devices, formed in an inter-layer dielectric (ILD) material layer that is coplanar with or vertically above semiconductor material layers, formed in an interconnect layer, or formed in a metallization layer or via layer vertically above the semiconductor material layer(s), to name a few examples.

In the example shown in <FIG>, the vertical aligned structures <NUM> and the vertical random structures <NUM> are formed in a via layer <NUM> between metallization layers <NUM>, each of which is located vertically above a semiconductor material layer <NUM>. Additional material layers may exist above or below the layers shown in <FIG>. The via layer <NUM> and metallization layers <NUM> each comprise a dielectric material, such as silicon dioxide (SiO<NUM>) titanium nitride (TiN), silicon nitride (Si<NUM>N<NUM>) or other suitable dielectric material.

According to the disclosed embodiments, a first layout design rule constraint is defined requiring that the active regions of IC <NUM> comprise a first grating <NUM> of metal and dielectric materials with only vertically aligned structures thereon. A second layout design rule constraint is defined requiring that the transition region <NUM> adjacent to the active region <NUM> comprise a second grating <NUM> of metal and dielectric materials having at least one of vertical aligned structures <NUM> and vertical random structures thereon <NUM>. Accordingly, both the first grating <NUM> and the second grating <NUM> comprise uniform gratings compatible with DSA. Consequently, the active region <NUM> and the transition region <NUM> have an absence of non-uniform gratings with horizontal parallel polymer sheets thereon, which may be considered a third layout design rule constraint.

According the one aspect of the disclosed embodiments, prior to fabrication of the IC <NUM>, the modified layout design rules are enforced such that a width of the isolated metal or ILD comprising the first grating <NUM> of active region <NUM> is less than approximately <NUM> to <NUM> times a grating pitch of the first grating <NUM> in order for the first grating <NUM> to be considered uniform and DSA compatible, or approximately <NUM> times a grating pitch of the grating <NUM> in a specific embodiment. Alternatively or in addition to, the modified layout design rules are enforced such that dummy structures are inserted into the first grating <NUM> to make the grating pitch within approximately +/-<NUM>% of the BCP pitch, or approximating +/-<NUM>% of the BCP pitch for A-B type copolymers and within approximating +/-<NUM>% of the BCP pitch for A-B-A type copolymers.

Similarly, the modified layout design rules were enforced with respect to the transition region <NUM> such that a width of the isolated metal or ILD comprising the second grating <NUM> is less than approximately <NUM> to <NUM> times a grating pitch of the grating <NUM> or approximately <NUM> times a grating pitch of the grating <NUM> in a specific embodiment. Alternatively or in addition to, the modified layout design rules are enforced such that dummy structures were inserted into the second grating <NUM> to make the grating pitch less than approximating +/-<NUM>% of the BCP pitch for A-B type copolymers and within approximating +/-<NUM>% of the BCP pitch for A-B-A type copolymers.

The layout design rule constraints embodiments disallow polymer sheet defects in both the active regions <NUM> (i.e., "care regions") and transition regions <NUM> (i.e., "don't care regions") of the die arising from non-uniform gratings that are incompatible with BCP pitch. However, the layout design rule constraints optionally allow defects only in the transition regions <NUM> ("don't care regions"), where the defect arises from uniform gratings that cause DSA to form vertical random structures, rendering any such defects harmless. The layout design rule constraints further require active regions <NUM> to have uniform gratings that result only in formation of aligned vertical metal structures. The active regions <NUM> are consequently relatively clean, in that they are defect-free or otherwise free of defects comparable to defects in the don't care regions or that otherwise would be considered problematic with respect to performance and reliability issues. As used in this disclosure, the term defect-free is a relative term, and is not intended to be interpreted as requiring true perfection. In particular, some degree of acceptable or minor defect may be present, but relative to other more severe defects, are a non-issue with respect to factors such as device performance and reliability. Similarly, the word "vertical" with respect to aligned and random aligned structures does not necessarily mean <NUM> degrees with respect to the substrate, but includes a tolerance within +/- <NUM> degrees.

In one aspect of the disclosed embodiments, the goal is to ensure a layout design for an IC only includes uniform gratings compatible with DSA. This may be accomplished by analyzing one or more layout designs for the active regions and the transition regions to identify areas having non-uniform gratings that are incompatible with DSA.

As used herein, a non-uniform grating is one having metal/ILD dimensions and ratios that are not within certain thresholds compared to the BCP pitch <NUM> and produce BCP orientations that result in horizontal polymer sheets, as shown in <FIG>, which are not BCP compatible. A uniform grating is one having metal/ILD dimensions and ratios that are within certain thresholds compared to the BCP pitch <NUM> and produce BCP orientations that result in formation of vertical structures (vertical aligned or vertical random), as shown in <FIG>. Such uniform gratings are considered compatible with BCP pitch.

More specifically, a non-uniform grating capable of polymer sheet formation is found by identifying an area in an active region or transition region having: i) isolated metal or ILD width greater than a first threshold of. <NUM> times a grating pitch <NUM> of the metal grating <NUM>, or ii) a grating pitch that is not within a second threshold of approximately +/-<NUM>% of the BCP pitch for A-B type copolymers and not within approximating +/-<NUM>% of the BCP pitch for A-B-A type copolymers. In other embodiments, the first threshold is. <NUM> times a grating pitch and a non-uniform grating is defined as an area with a grating pitch that is not within approximately +/- <NUM>% or <NUM>% of the BCP pitch.

Once an area is identified having a non-uniform grating, the layout design of that area is modified such that non-uniform grating is made uniform and compatible with DSA. The layout designs for areas identified as having the non-uniform gratings are modified to either: i) reduce the width of metal or ILD comprising the non-uniform grating that is too wide and incompatible with DSA or ii) to insert dummy structures in the layout designs to convert the non-uniform gratings to DSA-compatible uniform gratings. The first option is to redesign structures to reduce width. For example, a metal or ILD line originally designed with a width of <NUM> can be redesigned with a reduced with of less than -<NUM> - <NUM> to accommodate DSA. In the second option, dummy structures such as plugs may be used is to reduce the size of a metal or ILD structure such that the amount of metal and ILD in a particular area are as proportionate as possible, e.g. <NUM>:<NUM>.

The modified layout designs ensure fabrication of an IC having active regions and transitions regions in which: i) the active regions consist of vertical aligned structures, ii) the transition regions consists of at least one of vertical aligned structures and vertical random structures, and iii) no horizontal polymer sheets in either the active regions or the transition regions.

<FIG> illustrates an example of a modification made to a transition region to convert a non-uniform grating into a DSA-compatible uniform grating. A top view of an example transition region <NUM> as it would appear prior to DSA is shown between two active regions <NUM> having different pitches. The transition region <NUM> comprises a metal structure <NUM> that is too wide for compatibility with DSA. To avoid formation of polymer sheets, the layout design for the transition region <NUM> is modified to incorporate a plug mask to pattern resist such that dummy structures referred to as plugs <NUM> are inserted to convert the metal structure <NUM> into a DSA-compatible uniform grating. Plug patterning is also used in fabrication process flow, but typically, process flow designs are not DSA friendly. Here, the use of the plugs <NUM> is to break the wide metal structure <NUM> into smaller metal structure/features that have a pitch within approximately ± <NUM>% BCP pitch for A-B type copolymers and within <NUM>% for A-B-A type copolymers to create a DSA compatible layout design that avoids polymer sheet formation, and results in the formation of vertical random structures <NUM> in this example. In one embodiment, the use of plugs <NUM> is to reduce the size of a metal or ILD structure such that that metal and ILD have approximately the same proportion.

<FIG> illustrate various example plug mask configurations to convert DSA incompatible gratings into DSA compatible gratings. <FIG> shows an example use of plugs <NUM> arranged in an offset formation to form jog structures <NUM> between gratings of different pitch, rather than using a single wide structure. In one embodiment, each plug <NUM> jog structures <NUM> is approximately <NUM>-<NUM> nn in length.

<FIG> shows an example use of plugs <NUM> in a transition region laid out perpendicular between two active regions, where the plugs are parallel narrow rectangles over a wide metal/ILD to reduce the metal/ILD width. If for example, the BCP pitch is <NUM>, then according to an embodiment where DSA can handle a grating pitch within <NUM>% of the BCP pitch for A-B type copolymers. The addition of the plugs <NUM> ensures the transition region has a grating a pitch anywhere between <NUM> and <NUM>.

<FIG> shows an example use of plugs <NUM> in a transition region laid out parallel between two active regions. In this example, the plugs are arranged in a "ladder" formation over a wide metal/ILD region to make the transition region pitch within <NUM>% of the BCP pitch.

<FIG> shows another example use of plugs <NUM> in a transition region laid out parallel between two active regions in which the metal/ILD grating and the plugs to not align exactly with the gratings of the active regions. In this case, DSA may result in formation of fingerprints over the transition region, which is still acceptable as vertical structures can still be formed from DSA fingerprints.

The embodiments above describe a material approach for avoiding formation of parallel horizontal BCP structures. According to a further aspect of the disclosed embodiments, a chemical approach for avoiding formation of parallel horizontal BCP structures is described. In this approach rather than selectively grafting a first polymer component (e.g., PS) onto the metal and the second polymer component (e.g., PMMA) onto the ILD or vice versa, the chemical embodiment selectively grafts either PS or PMMA onto the metal and a neutral polymer component onto the ILD. Such an approach can reduce parallel orientation over wide metal gratings 120C, as shown in <FIG>.

According the disclosed embodiments, the process for fabricating an IC with DSA may begin by receiving a substrate with one or more active regions separated by transition regions. For example, the substrate can be a semiconductor wafer with a plurality of active regions and transition regions distributed across the wafer in a grid, each active region containing devices, integrated circuits, and/or sensors. In another example, the substrate comprises a semiconductor layer with at least one active region containing one or more semiconductor device. Lamellae-forming block copolymers are provided for DSA. In embodiments, the block copolymers are polystyrene and polymethyl methacrylate (PS-b-PMMA) in a solvent or carrier liquid. However, in other examples, any other appropriate type of polymers may also be used. Examples of such polymers include, but are not limited to, poly(styrene)-b-poly(<NUM>-vinylpyridine) (PS-b-P2VP), poly(styrene)-b-poly(<NUM>-vinylpyridine) (PS-b-P4VP), poly(styrene)-b-poly(acrylic acid) (PS-b-PAA), poly(styrene)-b-poly(ethylene glycol) (PS-b-PEG), poly(styrene)-b-poly(imide) (PS-b-PI), and poly(styrene)-b-poly(dimethylsiloxane) (PS-b-PDMS). These systems and their processing may be at least in part analogous to the BCP comprising the PS-b-PMMA system discussed herein. In one example, annealing the block copolymers solution causes molecules of the DSA copolymer solution self-align to form alternating lines of polystyrene and polymethyl methacrylate. In some embodiments, the alternating lines of polymers have a BCP pitch of less than <NUM> or less than <NUM>. Numerous other suitable DSA solutions can be used, as will be appreciated.

The process continues with defining one or more gratings on the substrate, wherein the grating pitch is within <NUM>% of the BCP pitch for A-B type copolymers or <NUM>% of the BCP pitch for A-B-A type copolymers. In one embodiment, the grating includes lines of photoresist that define one or more structures. For example, when the BCP pitch is <NUM>, the grating has a grating pitch of <NUM> - <NUM>. The gratings can be formed using any suitable wet or dry photolithography technique, as will be appreciated. In one example process, photoresist is spin-coated onto the substrate, a mask is used during exposure to ultraviolet light to polymerize certain regions of the photoresist, and the non-polymerized regions of photoresist are removed with a solvent. The lithographic process leaves spaced-apart lines of photoresist on the substrate in a pattern that can be used to guide alignment of molecules of the block copolymer solution. When lines of the pinning stripe structure are spaced to within a threshold <NUM> or <NUM>% of the BCP pitch (depending on the type of copolymers), the block copolymers align consistently to the pinning stripe structure.

The process continues with depositing the block copolymer DSA solution on the substrate and the gratings. In some embodiments, the DSA solution is spin coated onto the substrate. In other embodiments, the DSA solution is sprayed, sputtered, dripped, or otherwise applied to the substrate.

The process continues with annealing the DSA solution. For example, a PS-b-PMMA block copolymer solution can be annealed using a solvent vapor annealing (SVA) process with acetone, tetrahydrofuran (THF), or other suitable solvent. In another example, the PS-b-PMMA block copolymer solution can be annealed by heating at a temperature sufficient to vaporize the solvent, such as about <NUM>° C to about <NUM>° C. During the annealing process, the molecules of the block copolymers align along the gratings to define alternating lines of the block copolymers. For example, in the active regions the polymers consistently define alternating parallel lines of a first polymer (e.g., PS) and a second polymer (e.g., PMMA) that form aligned vertical BCP structures without defects. In the transition regions, when the grating pitch of the grating is still uniform, but does not match the BCP pitch, but the ratio of PS to PMMA is close to <NUM>:<NUM>, the first and second polymers may form random vertical BCP structures. Aligned vertical BCP structures may also be formed in the transition regions. At no point parallel horizontal BCP structures or polymer sheets formed.

The process continues with removing one of the block copolymers. For example, a suitable solvent is selected to remove the first block copolymers (e.g., PS) and leave the second block copolymer (e.g., PMMA) on the substrate. The second block copolymer can be used as a mask for subsequent processing.

The process continues with etching trenches in the material previously covered by the first copolymer. In one embodiment, the block copolymer solution is applied on a dielectric material of a via layer or a metallization layer, such as silicon dioxide or titanium nitride. The trenches can be formed using any suitable wet or dry etching process.

The process continues with depositing a metal, semiconductor, or other material in the etched trenches and planarizing as needed to define the structures such as traces or interconnects. In one embodiment where the structures are formed in a via layer or metallization layer, copper, aluminum, titanium, or other conductive metal is deposited. In other embodiments in which the structures are formed in one or more semiconductor material layers, a doped semiconductor material can be deposited in the trench. For example, n-type semiconductor material is deposited into trenches formed in a p-type semiconductor material layer, or vice versa.

The process may continue with performing down flow die processing, including packaging processes.

In some embodiments, the process can be performed during or after back-end or back-end-of-line (BEOL) processing, for example. In other embodiments, method can be performed in a front-end-of-line (FEOL) processing, such as after or during formation of semiconductor devices, as will be appreciated.

The integrated circuit structures described herein may be included in an electronic device. As an example of one such apparatus, <FIG> are top views of a wafer and dies that include one or more embedded non-volatile memory structures utilizing direct self-assembly process for formation of selector or memory layers, in accordance with one or more of the embodiments disclosed herein.

Referring to <FIG>, a wafer <NUM> may be composed of semiconductor material and may include one or more dies <NUM> having integrated circuit (IC) structures formed on a surface of the wafer <NUM>. Each of the dies <NUM> may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more active regions and transitions having only vertical structures formed by DSA, such as described above. After the fabrication of the semiconductor product is complete, the wafer <NUM> may undergo a singulation process in which each of the dies <NUM> is separated from one another to provide discrete "chips" of the semiconductor product. In particular, structures that include traces or interconnects in active regions and transitions having only vertical structures formed by DSA as disclosed herein may take the form of the wafer <NUM> (e.g., not singulated) or the form of the die <NUM> (e.g., singulated). The die <NUM> may include one or more active regions and transitions having only vertical structures formed by DSA and/or supporting circuitry to route electrical signals, as well as any other IC components. In some embodiments, the wafer <NUM> or the die <NUM> may include an additional memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die <NUM>. For example, a memory array formed by multiple memory devices may be formed on a same die <NUM> as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

<FIG> is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more active regions and transitions having only vertical structures formed by DSA, in accordance with one or more of the embodiments disclosed herein.

Referring to <FIG>, an IC device assembly <NUM> includes components having one or more integrated circuit structures described herein. The IC device assembly <NUM> includes a number of components disposed on a circuit board <NUM> (which may be, e.g., a motherboard). The IC device assembly <NUM> includes components disposed on a first face <NUM> of the circuit board <NUM> and an opposing second face <NUM> of the circuit board <NUM>. Generally, components may be disposed on one or both faces <NUM> and <NUM>. In particular, any suitable ones of the components of the IC device assembly <NUM> may include a number of active regions and transitions having only vertical structures formed by DSA, such as disclosed herein.

In some embodiments, the circuit board <NUM> may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board <NUM>. In other embodiments, the circuit board <NUM> may be a non-PCB substrate.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-interposer structure <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may electrically and mechanically couple the package-on-interposer structure <NUM> to the circuit board <NUM>, and may include solder balls (as shown in <FIG>), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure <NUM> may include an IC package <NUM> coupled to an interposer <NUM> by coupling components <NUM>. The coupling components <NUM> may take any suitable form for the application, such as the forms discussed above with reference to the coupling components <NUM>. Although a single IC package <NUM> is shown in <FIG>, multiple IC packages may be coupled to the interposer <NUM>. It is to be appreciated that additional interposers may be coupled to the interposer <NUM>. The interposer <NUM> may provide an intervening substrate used to bridge the circuit board <NUM> and the IC package <NUM>. The IC package <NUM> may be or include, for example, a die (the die <NUM> of <FIG>), or any other suitable component. Generally, the interposer <NUM> may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer <NUM> may couple the IC package <NUM> (e.g., a die) to a ball grid array (BGA) of the coupling components <NUM> for coupling to the circuit board <NUM>. In the embodiment illustrated in <FIG>, the IC package <NUM> and the circuit board <NUM> are attached to opposing sides of the interposer <NUM>. In other embodiments, the IC package <NUM> and the circuit board <NUM> may be attached to a same side of the interposer <NUM>. In some embodiments, three or more components may be interconnected by way of the interposer <NUM>.

The interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer <NUM> may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer <NUM> may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The interposer <NUM> may further include embedded devices <NUM>, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer <NUM>. The package-on-interposer structure <NUM> may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly <NUM> may include an IC package <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may take the form of any of the embodiments discussed above with reference to the coupling components <NUM>, and the IC package <NUM> may take the form of any of the embodiments discussed above with reference to the IC package <NUM>.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-package structure <NUM> coupled to the second face <NUM> of the circuit board <NUM> by coupling components <NUM>. The package-on-package structure <NUM> may include an IC package <NUM> and an IC package <NUM> coupled together by coupling components <NUM> such that the IC package <NUM> is disposed between the circuit board <NUM> and the IC package <NUM>. The coupling components <NUM> and <NUM> may take the form of any of the embodiments of the coupling components <NUM> discussed above, and the IC packages <NUM> and <NUM> may take the form of any of the embodiments of the IC package <NUM> discussed above. The package-on-package structure <NUM> may be configured in accordance with any of the package-on-package structures known in the art.

<FIG> illustrates a computing device <NUM> in accordance with one implementation of the disclosure. The computing device <NUM> houses a board <NUM>. The board <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> is physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> is also physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the board <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within the processor <NUM>. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more active regions and transitions having only vertical structures formed by DSA, in accordance with implementations of embodiments of the disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more active regions and transitions having only vertical structures formed by DSA, in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device <NUM> may contain an integrated circuit die that includes one or more active regions and transitions having only vertical structures formed by DSA, in accordance with implementations of embodiments of the disclosure.

Claim 1:
An integrated circuit structure, comprising:
an active region (<NUM>) containing more active semiconductor devices, the active region (<NUM>) comprising a first grating (<NUM>) of metal and dielectric materials with only vertically aligned directed self-assembly, DSA, copolymer structures (<NUM>) thereon; and
a transition region (<NUM>) containing inactive structures adjacent to the active region (<NUM>), the transition region (<NUM>) comprising a second grating (<NUM>) of metal and dielectric materials having at least vertical random DSA copolymer structures (<NUM>) thereon,
wherein both the first and the second gratings (<NUM>) are uniform gratings and have an absence of horizontal parallel DSA polymer sheets.