Patent Description:
A non-limiting example of a phase-controlled application is phase-based distance estimation. Phase-based distance estimation (PDE) is becoming of increasing interest in a wide range of use cases such as car and home access, security, asset location and tracking, and the like. PDE using narrowband technologies such as Bluetooth low energy (BLE) is, for example, being considered for inclusion in Bluetooth specifications under IEEE <NUM>.

PDE relies on a reliable measurement of the phase difference between two wireless devices which results from the propagation time between the devices, and scales with the distance between the devices. The phase difference may be absolute or relative, and may be measured using either unilateral (one-way ranging) or bilateral (two-way ranging) exchange of wireless signals.

In two-way ranging (TW PDE) it is required that the transmit (TX) and receive (RX) PLL phases are the same - or at least are phase coherent, that is to say they have a well-controlled phase relationship, over a time period of interest such as a transmit-receive (Tx - Rx) exchange. In some types of transceiver, the TX and RX frequencies are the same, so this becomes relatively straightforward to achieve. Such receivers are called direct conversion receivers or zero-IF receivers. However, use of the same frequency for both transmit and receive introduces its own problems, and so increasingly popular is the use of receivers in which the TX and RX frequencies are offset by a chosen intermediate (IF) frequency - these receivers may be termed low-IF receivers, and in this instance a phase compensation technique is required to enable bilateral coherent phase measurement. Here, "frequency" refers to the frequency of the local oscillator (LO), which corresponds to the PLL operating frequency, divided by the "LO divider" (if any).

In one-way phase-distance estimation ranging, or unilateral measurement, the phase coherence requirement extends to the PLL such that it must maintain its phase coherent irrespective of the frequency. In such ranging methods, a phase difference between transmissions over the same distance at two different frequencies is inversely proportional to difference between the frequencies. Thus at least two frequencies are required, to determine a phase-distance estimation, and in practical applications, typically more than two are used, and the frequencies are switched or hopped randomly, or pseudo-randomly, in order to improve the measurement robustness and provide security against, for instance, malicious jamming.

The problem of phase coherence across frequency has been solved by applying so-called type-II PLLs in the receiver circuit. type II PLLs have a phase-error integration block within the PLL loop. As a result, there is a closed loop for controlling the phase and achieve a null phase offset, even in the event of perturbations to phase or frequency of the incoming input signal.

However, the phase error integration block results in relatively longer lock times, increases the in-band noise, and adds to the power consumption and size of the semiconductor die. It would therefore be desirable to achieve phase coherence, reducing or mitigating at least some of the above disadvantages.

It is known to operate a type I PLL as a "pseudo type-II" PLL. Typically, these are implemented as a fast-locking all-digital ADPLL and appear similar to a type-I PLL having a type-I PLL phase, but they engage a digital integrator to regulate the PLL phase-error around a sampled non-zero phase-error. In such a PLL the samples' phase error value (acquired at the end of type-I phase control) is variable and so the PLL cannot maintain phase coherency across frequency jumps.

International patent application, publication number <CIT> discloses systems for multi-mode phase modulation. Systems provide for direct modulation of a multi-mode voltage controlled oscillator (VCO). A fractional-N counter may be used in a type II phase-locked loop (PLL) to synthesize a radio frequency carrier signal. The multi-mode VCO may be characterized by a first frequency gain during operation in a first mode and by a second frequency gain during operation in a second mode where signals controlling the first and second operating modes are provided by a control circuit. The control circuit may include a switch to provide control signals to the VCO.

According to an Aspect of the present disclosure, there is provided a method of using a type I phase locked loop, PLL, as defined in claim <NUM>. Thus according to this aspect, insight about the phase change, and/or the frequency change which causes the phase change, can be applied, in order to compensate the change. It will be noted that the method does not require a second control loop in the PLL - in other words, it can be applied to a true type-I PLL. Such methods can thereby facilitate use of a type-I PLL in applications for which phase-coherency is required, which application heretofor have required the use of type-II PLLs, or other relatively complex circuitry, in order to maintain phase coherency.

In one or more embodiments in which the method includes the step of adjusting the second relative phase to equal the first relative phase, applying a correction to the PLL comprises inserting the correction signal into the feedback path. Such embodiments may be referred to in general as Low Port Modulation compensation methods, since the LPM input to a PLL loop is included in the feedback path.

In one or more such embodiments the feedback path includes a fractional divider controlled by a Sigma Delta Modulator (SDM), and inserting the correction signal into the feedback path comprises inserting the correction signal into the SDM.

In one or more embodiments, the correction signal is inserted into the feedback path in the form of an impulse signal in a single clock cycle. In other embodiments, the correction signal is inserted into the feedback path through a plurality of partial corrections signal is applied over multiple clock cycles, such that the product of the partial correction signals and the number of clock cycles that that partial crash supplied sums to the correction signal.

In one or more embodiments determining the correction signal effected by: estimating a steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency, and using the estimated steady state phase lag, to determine a total phase shift (ΔΦLO,steady) between the first output signal and the second output signal.

In one or more embodiments, determining the total phase shift (ΔΦLO,steady) comprises further comprises determining a self-resonance frequency, FVCO, of the oscillator, and an offset, FERR, between the self-resonance frequency, and a one of the first and second frequencies FPLL.

In one or more embodiments, determining the total phase shift (ΔΦLO,steady) comprises determining an PLL gain, KPLL. Furthermore, determining the total phase shift (ΔΦLO,steady) may comprise determining an open-loop gain K<NUM> of the oscillator by operating the PLL in an open loop configuration wherein the feedback path is disconnected from the phase detector. Yet further, in one or more embodiments, the PLL gain is equal to the open-loop gain of the oscillator multiplied by a gain, KΦ, of a phase detector of the PLL.

In one or more embodiments, the PLL is operable in an open-loop configuration in which an output of the phase detector is replaced by a predetermined pre-charge signal.

According to a yet further aspect of the present disclosure, the above method includes the step of adjusting the oscillator frequency. Such embodiments may generally be referred to, or considered as, using HPM correction or HPM compensation. In one or more such embodiments, the oscillator includes a control port for receiving an input for tuning the oscillator, and applying a correction to the PLL comprises adjusting a control signal at the control port.

In one or more embodiments, the PLL is an analog PLL comprising a modulation digital-to-analog converter, DAC. In such embodiments, it may be that the control port is a varactor tuning port having an input connected to the output of the modulation DAC, and adjusting a control signal at the control port PLL comprises controlling the modulation DAC. In one or more such embodiments, the modulation DAC includes at least one of a gain stage, and an anti-alias filter.

In one or more embodiments using HPM correction or compensation, the method includes the step of adjusting the oscillator frequency and wherein the oscillator is a digitally controlled oscillator, DCO having a port for high port modulation, the embodiments include applying a correction to the PLL comprises adjusting a control signal at the port for high port modulation.

In one or more embodiments adjusting a control signal at the port for high port modulation comprises adjusting the control signal by an amount corresponding to an intermediate frequency which is a difference between the first frequency and the second frequency, This adjustment to the frequency - in the frequency domain - nullifies the phase offset with the change in PLL frequency from the first to second locked frequencies, and avoid the needs for a second, phase, control loop (i.e. avoids the need for use of a type-II PLL).

In one or more such embodiments, the PLL includes a feedback divider connected between an output of the oscillator, and an output of the PLL, and the method includes adjusting a control signal at the port for high port modulation comprises adjusting the control signal by an amount corresponding to an intermediate frequency which is a difference between the first frequency and the second frequency, divided by a division factor of the feedback divider.

The present disclosure also describes a method of using a type I phase locked loop, PLL, comprising an oscillator and a feedback path to a phase detector, the method comprising: locking a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal; locking a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal, estimating a steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency, using the estimated steady state phase lag (SSPL), to determine a total phase shift (ΔΦLO,steady) between the first output signal and the second output signal, and a one of: compensating the PLL for the phase shift, and using the determined total phase shift in a distance estimation. The distance estimate may generally be referred to as phase-based distance estimation, PDE.

Thus, according to this aspect it may be possible to avoid a requirement to include a phase error integration block in the PLL, such is used in type II PLLs. In particular, the present inventors have appreciated that, in a type I PLL, the phase lag resulting from a frequency change settles down to a steady state, and this fact may be exploited in order to provide well-controlled phase, and effectively provide the equivalence of phase coherent phase memory without requiring the additional circuitry of type II PLL's.

In one or more examples, determining the total phase shift (ΔΦLO,steady) comprises determining a self-resonance frequency, FVCO, of the oscillator, and an offset, FERR, between the self-resonance frequency, and a one of the first and second frequencies FPLL. The oscillator may be a voltage-controlled oscillator (VCO). It has thus been found that the value FERR, where <MAT> is one of the parameters which determines the SSPL and thus the total phase shift.

In one or more examples, determining the total phase shift (ΔΦLO,steady) comprises determining a PLL gain, KPLL. Furthermore, in one or more embodiments, determining the total phase shift (ΔΦLO,steady) comprises determining an open-loop gain Ko of the oscillator by operating the PLL in an open loop configuration wherein the feedback path is disconnected from the phase detector. Moreover, in one or more such embodiments the PLL gain is equal to the open-loop gain of the oscillator multiplied by a gain, KΦ, of a phase detector of the PLL. It can be demonstrated by mathematical analysis that the SSPL depends on the open loop gain of the oscillator.

In one or more examples, the PLL is operable in an open-loop configuration in which an output of the phase detector is replaced by a predetermined pre-charge signal. As will be described in more detail hereinunder, the PLL may be operated in such a so-called "open-loop" configuration, in which the frequency of the oscillator is not determined by a feedback path, but by a predetermined signal. The predetermined signal is used to pre-charge the oscillator. In an analogue PLL the pre-charge signal is typically a pre-charge voltage, and may have a level which is half of supply voltage. In a digital PLL, the pre-charge signal is typically a value of a register held in memory and applied as a digital control word applied to a tuning input of the oscillator, which in this case is typically a digitally controlled oscillator.

Once the total phase shift is known, this may be used for example in calculations in which the phase of the signal is required to be known or to either correct or compensate the PLL directly. Thus, in one or more embodiments the method comprises compensating the PLL for the phase shift.

In one or more such examples, the feedback path comprises a fractional divider controlled by a sigma-delta modulator, and compensating the PLL for the phase shift comprises applying a correction dependant on the total phase shift (ΔΦLO,steady) to the fractional divider by means of sigma-delta modulator. As will be familiar to the skilled person, the feedback path of the PLL typically requires a fractional divider which may be controlled by a Sigma-Delta modulator.

In one or more embodiments, applying a correction dependant on the total phase shift (ΔΦLO,steady) to the sigma-delta modulator comprises applying an impulse signal to the sigma-delta modulator.

In one or more examples, the PLL is a digital PLL and the impulse comprises a frequency control word, FCW.

In one or more other examples, in which the determined total phase shift is used in a phase-based distance estimation (PDE), the method comprises converting the total phase shift into a corresponding distance offset, and using the corresponding distance offset to calculate a distance between a first device comprising the PLL, and a second device. In other words, once known, the SSPL, and thus the total phase lag, can be converted into a corresponding distance offset - which as the skilled person will be familiar depends on the speed of light and the frequency or wavelength of the signal. Phase-based distance estimation methods determine the separation between two objects, such as the first and second devices mentioned above by comparing the phase of an electromagnetic signal transmitted between the two objects at the moment of transmission and the moment of reception. Any phase lag introduced by circuit elements - such as the phase lag from the PLL - is an undesired term which can interfere with this calculation, and thus is preferably removed. Whereas constant elements may be subtracted out by difference calculations, elements which vary introduce additional complexities. By recognising that a change in frequency induces a phase lag which, in steady state, is dependent on analogue parameters which may be estimated, the complexity associated with the PLL may be reduced or eliminated.

In one or more embodiments, the PDE is a one-way PDE, and the second frequency is related to the first frequency by a frequency hop. Herein the phrase "frequency hop" refers equally to the action of hopping between two channels - sometimes as part of a larger frequency sweep - or the separation between those channels, particularly adjacent channels. (Naturally, hopping between non-adjacent channels is also possible resulting in a larger frequency hop. ) The skilled person will appreciate that in one-way PDE, multiples frequencies are used in order to provide differing received phases associated with the differing wavelengths of the two different frequencies, from which the transmitter-receiver separation can be determined. Typically, for communication in the <NUM> range, the minimum frequency hop, between adjacent channels, may be of the order of <NUM>. For other communication frequency ranges, the frequency hop and/or the minimum frequency hop may each have different values.

In one or more other examples, the PDE is a two-way PD, and the first frequency is a receiver local oscillator, LO, frequency for a channel, and the second frequency is a transmitter LO frequency for the channel. The difference between the LO frequencies in receive mode and transmit mode is called the intermediate frequency, IF. Typically, for communication in the <NUM> range, the intermediate frequency is <NUM>. In other embodiments, such as for other communication frequency ranges, the intermediate frequency may have a different value. The skilled person will appreciate that in two-way PDE, multiples frequencies are used, separated by a frequency hop in order to provide differing received phases associated with the differing wavelengths of the two different frequencies. Each frequency hop is performed inin a "there-and-back" communication between the two devices whose spatial separation is to be calculated. The two channel frequencies correspond to two separate wavelengths and thus two separate "roundtrip" received phases back at the transmitter which started the two-way communication, from the combination of which the separation between the two devices can be determined. It will be appreciated that for this measurement to be effective, it is necessary to quantify any impact from the role swap from transmitter-to-receiver, and associated LO frequency change, corresponding to the frequency offset required for the LO in the "receive" mode, in order to provide the heterodyne intermediate frequency from the received signal.

There may be provided a computer program, which when run on a computer, causes the computer to configure any apparatus, including a circuit, controller, sensor, filter, or device disclosed herein or perform any method disclosed herein. The computer program may be a software implementation, and the computer may be considered as any appropriate hardware, including a digital signal processor, a microcontroller, and an implementation in read only memory (ROM), erasable programmable read only memory (EPROM) or electronically erasable programmable read only memory (EEPROM), as non-limiting examples. The software implementation may be an assembly program.

The computer program may be provided on a computer readable medium, which may be a physical computer readable medium, such as a disc or a memory device, or may be embodied as another non-transient signal.

Embodiments will be described, by way of example only, with reference to the drawings, in which.

It should be noted that the figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

As mentioned above, type I PLLs differ from type II PLLs by the absence of a phase-error integration block in the PLL loop, other than the voltage controlled oscillator (VCO). This is axiomatic, since one definition of the "type" of a PLL is that it corresponds to the number of integrators in the loop: for example, there may be just the VCO for a type-I PLL and the VCO plus one other, for a type-II PLL. Thus there can be a variable phase error between the phase detector reference and the output signal - which is returned as the feedback signal. By avoiding a phase-error integration block, the above-mentioned disadvantages associated with using type II PLLs may be reduced or avoided: in particular faster locking times and/or a better trade-off between noise and power may be achievable, and the PLL occupies a small area on a die.

However, there are some applications, such as PDE or narrowband ranging the mentioned above for which a variable phase error is not generally acceptable. For such applications which require "phase coherence" or "phase memory" it would generally be considered that type I PLLs are not appropriate. As a specific example, within PDE it is required to manage a role swap - that is to say the transceiver switching between a receive mode to a transmit mode with associated frequency change - for two-way PDE without introducing a phase error, and similarly for one-way PDE it is required to be able to manage frequency hops again without introducing phase error.

The present inventors have appreciated that it is possible to mitigate or compensate the dynamic frequency error which is introduced when hopping, or role-swapping, between frequencies; thereby it may be possible to reduce or overcome the disadvantages of type-I PLLs, and facilitate their use in a wider range of applications.

In particular, it may thereby be possible to benefit from other advantages of type I PLLs, such as speed of convergence and lower noise. The phase error introduced through a frequency hop may be defined as a "transient phase error", which converges to, and results in a "steady state phase lag" which will be described in more detail hereinbelow, and may be determined or estimated, again as will be detailed hereinbelow.

Considering first <FIG>, this shows a type I PLL configured for initial phase locking. The PLL <NUM> comprises a phase detector (PD) <NUM> into which is input a reference signal (REF) <NUM> during normal operation. An output VPD from the phase detector <NUM> is input into a low pass filter (LPF) <NUM>. However during the initial phase, this connection is opened - such that the loop is not closed. Instead a pre-charge voltage VPCH is input to the lowpass filter <NUM> from a pre-charge unit <NUM>. High frequency components are filtered out by the low-pass filter <NUM>, which passes a tuning voltage VTUNE to a VCO <NUM>. The output from the VCO is both provided as output (OUT) <NUM> and fed back as a feedback signal. The feedback signal is divided by a factor (which may be a factor of <NUM> as shown) in a feedback divider <NUM>, and provided as the second, FBK, input to the phase detector <NUM>.

During the initial phase, known as an open-loop VCO calibration, the VCO is brought to a self-resonance frequency - which is generally designed to be close or as close as possible to the target PLL frequency. The skilled person will appreciate that how this is achieved is dependent on the specific implementation of hardware used. For instance, there may a capacitor bank controlled by a calibration algorithm. In this phase VTUNE= VPCH; this is typically chosen to be half the PLL supply voltage (VDD-PLL), to maximise the PLL acquisition range. Once the open-loop calibration ends, the loop is closed, and the VCO control voltage VTUNE is set by the PLL to drive the VCO to the correct frequency. In normal operation, the phase detector <NUM> produces an output that is proportional to the phase difference between the two inputs signals REF and FBK. Thus VPD = Kϕ·(ϕREF - ϕFBK) where ϕREF and ϕFBK are the phases of the signals REF and FBK respectively and Kϕ is the Phase Detector gain (in V/rad).

At the end of the open loop calibration, the frequency of the VCO will differ from the target PLL by a frequency error: FVCO = FPLL+FERR; where FPLL is the target PLL frequency, FERR is the frequency error with respect to the target PLL output frequency and FVCO the VCO self-resonance frequency. Once the loop is closed, the PLL drives the VCO frequency to the desired value, by acting on the VCO control voltage, until the VCO frequency achieves the locked frequency FVCO-LCK = FPLL. The VCO control voltage then, VTUNE-LCK, will be related to the pre-charge voltage VPCH, through: <MAT> where KVCO is the VCO gain in Hz/V.

Consider the example above in which the pre-charge voltage is half the supply voltage: VPCH = VDD-PLL/<NUM>, and assume that the Phase Detector is implemented by a set-reset (SR) latch: <MAT>.

If the initial frequency error is null (FERR = <NUM>), then VTUNE-LCK = VPCH = VDD-PLL/<NUM> and (ϕREF - ϕFBK) = π. However, is the frequency error is not null, then: <MAT>.

Since the phase of the feedback signal is equal to the phase of the PLL output signal divided by N, then also the phase of the PLL output signal depends on the VCO frequency error.

Now considering a frequency hop of Δf whilst the PLL is operating - i.e. in closed loop; the resulting relative phase shift (in steady state) at the Phase Detector inputs is: <MAT>.

Due to its limited bandwidth, the PLL will take some time to arrive to steady state, but once in steady state a phase shift at the phase detector feedback input is related to a phase shift on the LO (local oscillator - in this example the VCO) signal.

Before returning to a circuit analysis, the reader is directed to <FIG> which is another block diagram depiction of a generic divider-based PLL <NUM>, which can be implemented either as an analog or digital circuit, and illustrates two modulation ports for modulation the frequency of the PLL: a low port modulation and a high port modulation. Similar to the PLL shown in <FIG>, the loop comprises a phase detector <NUM>, the output of which is input to a loop filter <NUM>. The output of the loop filter <NUM> is input to an oscillator <NUM>, in this instance implemented as an RF oscillator. A frequency counter <NUM> counts the oscillator output. There is included between the oscillator and the output <NUM> an optional divide-by-x divider <NUM>. Feedback is provided from the output, through a divide by N fractional divider <NUM>, back to the phase detector <NUM>. Along with the feedback, the phase detector has a second input REF-OSC <NUM>. The fractional divider <NUM> has as an input a (in this case digital) signal output from a Sigma Delta modulator <NUM>. The input and Sigma Delta modulator is the sum of a target frequency <NUM> and a low port modulation input, if any, as shown at <NUM>. The RF oscillator <NUM> can be controlled by a course tuning block <NUM>; it can be further directly by a high port modulation <NUM> provided by a high port modulation input <NUM>.

A theoretical analysis of the transfer function of the PLL, over a Laplace domain s can be made, in conjunction with <FIG>, which shows a generic flow graph of a divider-based analog PLL, such as that shown in <FIG>, including a divide-by-N divider in the feedback path, and the option of providing both "low-port injection" and "high-port injection" - which will be explained in more detail hereinbelow. It can be shown that, considering firstly the effect of controlling using VFM1 corresponding to a frequency modulation control signal through the Low-Port Modulation path <NUM>, <NUM>: <MAT> and secondly the effect of controlling using VFM2 corresponding to a frequency modulation control signal through the High-Port Modulation path <NUM> <MAT> where: s is the Laplace variable; Nin is a fixed division ratio (if any) in front of the feedback divider, and N is the division ratio of the feedback divider. Finally, G is a scaling or gain factor in the Laplace domain.

Since in the present instance VFM1 =VFM2 = VFM, and G<NUM>(s)= G<NUM>(s), this results in an all-pass transfer function (i.e. a transfer function allowing for injections signals from both the low pass modulator and the high pass modulator, VFM1 and VFM2 respectively), for the combination of high port modulation HPM and low port modulation LPM: <MAT>.

In the above relation, Ndiv = Nin · N, <MAT>, and NLoin is the ratio of the (optional) LO divider which is inside the loop between the VCO and the feedback divider, shown as "/x" <NUM> in <FIG> and the block "<NUM>/ NLoin" in <FIG>. It will be appreciated that the above analysis can be broadened to include generic divider-based digital PLL and a generic counter-based digital PLL. In all cases, it results that a similar transfer function exists and a similar dependence on the open-loop gain <MAT> and feedback Ndiv loop exists. Thus the above analysis, and hence embodiments of the present disclosure, are not restricted to one single kind or type of type-I PLL.

Considering next a frequency hop (which, as discussed above, may be either for role swap from receive to transmit, or for a channel change), a Δf step will be applied to VFM1 leading to Δf/s.

The step response of the LPM in the output frequency and phase domains are: <MAT> and <MAT>.

Comparing those responses to an ideal PLL, that is to say one in which the transfer function under low port modulation is unity: LPMideal(s) = <NUM>, it can be written: <MAT>.

Applying the Final Value Theorem to obtain the steady state values gives: <MAT>.

That is to say, the steady state phase lag, SSPLPLL is a function of Ndiv, and <MAT> , since the SSPL may be defined as: <MAT>.

A phase shift, having a value: <MAT> is thus introduced by the frequency hop, and is proportional to the frequency step and inversely proportional to the PLL open loop gain. The present inventors have appreciated that this relationship can be exploited to enable use of a type-I PLL, in application where the phase should be well-controlled.

In the case respectively of a set-reset-latch-based or XOR-gate-based Phase Detector, the above analysis is modified such the phase shift is <MAT> and <MAT> respectively.

Taking as a specific and non-limiting example, a set-reset-latch-based PD, and a <NUM> frequency step, for a Ndiv of <NUM>, KVCO = <NUM>/V, and VDD = <NUM> V, a phase shift of -<NUM>° is obtained. Using these parameters, the PLL SSPL in this case is equal to -<NUM> ns.

Turning now to <FIG> shows the response of an example PLL to a <NUM> frequency step, for an ideal frequency modulator shown at <NUM>, that is to say the open-loop VCO response measured as the relative phase to the initial carrier phase, measured in degrees, on the y-axis or ordinate against time in seconds on the x-axis or abscissa. In addition to the open-loop VCO response <NUM>, the figure shows a simulated response of a real system at <NUM>, and a first order approximation at <NUM>.

<FIG> plots, for the same example, the relative phase shift to the same step response, with the relative phase shift in degrees plotted on the y-axis or ordinate, against time on the x-axis or abscissa. The simulated real circuit is shown at <NUM> along with the first order approximation at <NUM>.

As can be seen in <FIG>, the SSPL PLL for this example is approximately <NUM>, and ΔΦLO,steady can be seen in both <FIG> to be approximately <NUM>°.

Returning to the analysis, and now focussing on the digital part of the PLL implementation: in addition to the steady state phase lag from the PLL, the digital data-path latency or delay to apply the frequency step (Digital Sigma Delta modulator + PLL main divider) must be taken into account. This will be implementation dependent, and denoted -NDig·TPLL,Ref, where NDig is a counter value of the digital path latency or in other words, a number of clock cycles for an input sample to be available at the system output, TPLL,Ref is the PLL reference clock period and is equal to <NUM>/(Mref·fXO), where fxo is the frequency of the crystal oscillator (in embodiments in which one is used), or another clock at the PLL input , and Mref is the PLL input clock multiplication ratio in case of a frequency multiplier is used in front of the phase detector. (it will be appreciated that this could, alternatively, be a divider or even a cascade of one and/or several multipliers/dividers.

Then due to the type I operation, there is a phase offset in between the PLL reference clock running at Mrer·fXO and the feedback clock. Typically, the feedback clock is an image of the clock of the delta-sigma modulator (DSM) in the feedback divider part of the loop, but is NOT directly the DSM clock. The phase offset depends on the initial frequency error in open loop for the pre-charge voltage Vpch, the frequency hop and the nominal phase offset required by the Phase Detector, which is either.

There is also a time delay in between the DSM clock rising edge and feedback clock edge which is also implementation dependent, and denoted by - Δtclk.

And the total corresponding phase shift is: <MAT>.

It can be observed that the first term depends on analog variables and the two last terms are constant and deterministic. Thus the two last terms can be known or removed by performing a so-called "zero-metre distance calibration" of PDE-based algorithm, in other words a calibration ofr the case in which there is no separation between the transmitter and receiver. The first term on the other hand requires a way to estimate the unknowns FERR, KVCO and Kϕ.

FERR can be estimated based on the best-achieved, or best achievable, frequency error during VCO coarse tune calibration (that is to say, when using the coarse tuning bank <NUM> to adjust the oscillator RFOSC <NUM>). Alternatively, it can be estimated based on an acquisition using a ripple counter or similar apparatus which is able to estimate the open-loop VCO frequency.

To estimate the PLL gain (KPLL) several alternatives will be readily appreciated. One is to use a method which directly allows computation of a ratio between a phase delta and a frequency delta, such as <NUM>/(Kϕ · K<NUM>) = Δϕ / Δf.

Another is to use a method which exploits gain estimator results such as, for a DPLL,
<MAT>.

A specific example for an analog PLL is as follows: choose a pair of VCO pre-charge values equally distributed around default pre-charge voltage but not too far away to avoid seeing varactor non-linearity, e.g. V<NUM> = <NUM>·VDD and V<NUM> = <NUM>·VDD for a default of <NUM>·VDD; measure VCO frequencies through a frequency-calibration (FCAL) or Ripple counter for both pre-charge voltages, which yields f<NUM> & f<NUM> respectively for V<NUM> & V<NUM>; and then use the approximate relationship: <MAT> where, α is a constant which depends on the PD implementation: e.g. α = <NUM> for Set-Reset latched-based PD, α= <NUM> for XOR-gate PD).

In digital PLLs: estimators for the PLL gain (Kϕ · K<NUM>) parameter are typically directly available: Time-to-Digital Converters (TDC) and DCO gains can be generally estimated using Least-Mean-Square (LMS)-based or similar algorithms, respectively providing <NUM>/ǨTDC and <NUM>/ǨDCO , leading to a direct availability of the loop gain parameter through:
<MAT>.

From FERR and KPLL estimation, it is possible to compute SSPL as discussed above: <MAT>.

And the total phase shift that needs to be compensated is, correspondingly: <MAT> where Δf is the frequency jump resulting from either the role swap in <NUM>-way PDE, or from a frequency hop for in <NUM>-way PDE.

According to one or more embodiments of the present disclosure, it is possible to compensate for a phase change in the type-I PLL which re-results from a frequency change, by providing compensation into the low port modulator LPM
The PLL fractional frequency may be written as kfrac*(Mref*fXO).

For a single PLL reference period results in a VCO frequency shift ΔfVCO, where: <MAT>.

Which is equivalent to a LO frequency shift: <MAT>.

Over a single reference period, which corresponds, in the phase domain, to a phase shift of <MAT>.

That is to say, the phase shift is perfectly compensated.

<FIG> illustrates a simulation of the impact of such phase correction by an impulse insertion in the LPM, by plotting phase on the Y-axis alternate against time on the x-axis or abscissa. Plot <NUM> shows the change of phase resulting from a frequency step introduced at moment <NUM>, without any correction. In contrast by including an impulse at the same moment that the frequency changes, the phase re-settles to the original value, as shown by plot <NUM>.

This is shown in more detail in <FIG> shows a simulated response of a PLL to a frequency hop. The top row of graphs (i), (ii) and (iii) show the response without any compensation, at <NUM>, <NUM> and <NUM> respectively. The middle row of graphs (iv), (v) and (vi) show the response when a compensation ΔϕL0,shift is applied, delayed after the frequency hop, both for an ideal PLL at <NUM>, <NUM>, <NUM> respectively, and for a real PLL at <NUM>, <NUM> and <NUM> respectively. The lower row of graphs (vii), (viii) and (ix) show the response, <NUM>, <NUM> and <NUM> respectively, when the same compensation ΔϕLO,shift is applied, at the same time as the frequency hop. For each row, the left graph shows the VCO frequency plotted against time. The middle graph shows the normalised phase of an ideal PLL compared with the real PLL, again plotted against time on the same scale, and the right graph shows the normalised phase error, once again plotted against time on the same scale.

Looking first at the frequency response over time (i), (iv) and (vii), the frequency change resulting from the frequency hop is shown at <NUM>, <NUM> and <NUM> respectively. On each plot the phase locking is also shown on the far left at <NUM>, <NUM>, <NUM>, once the open loop calibration discussed above is concluded.

Looking now at the normalised phase response of time, it can be seen that the phase is initially normalised to <NUM>, until the frequency hop is applied. The change in frequency resulting from the frequency hop results in a steadily increasing phase, which is the same for all three plots with respect to the ideal PLL. However, looking at the response of the real PLL with no compensation in plot (ii), it can be seen that the increasing phase lags that of the ideal PLL, shown at <NUM>, by a constant amount. In contrast, looking at the middle plot (v) in which the compensation is applied, delayed with respect to the frequency hop, it can be seen that the phase of the real PLL <NUM> lags that of the ideal PLL <NUM> until the compensation is applied, as shown at A. Thereafter, the compensated phase of the real PLL overlays that of the ideal PLL. Looking now at the lower plot (viii) which shows the normalised phase for a PLL where the conversation is applied at the same time as the frequency hop, here the normalised phase of the real PLL <NUM> overlays that of the ideal PLL <NUM> for the whole period.

Finally, looking at the right graphs which show the normalised phase error, the top plot at (iii) shows, after the phase settles, zero phase error until the frequency hop is applied at <NUM>. Thereafter the phase settles to a steady state phase error (corresponding to the steady state phase lag discussed above). The middle plot(vi) shows the phase error, which again is <NUM> until the frequency hop is applied, at which moment the phase error becomes negative, and settles to a steady state phase error until the compensation is applied at moment A, at which time the phase error arises, as shown at <NUM>, back to a zero phase error. The lower plot (ix) shows the consequence of applying the compensation at the same time as the frequency hop. Again, once the PLL has settled, the phase error <NUM> is <NUM> until the frequency hop is applied. However, in this case the compensation supplied at the same time such that after a short perturbation showed at <NUM>, the phase error returns to <NUM>.

The offset applied to the LPM may be provided as an impulse (that is a <NUM>-cycle correction) or the correction may be applied over multiple cycles provided the product of the correction and the number of clock cycles is equal to the desired correction.

According to one or more embodiments of the present disclosure, it is possible to compensate for a phase change in the type-I PLL which re-results from a frequency change, by providing a frequency offset into the high port modulator HPM. In the example of a digital PLL, the oscillator is a digitally controlled oscillator (DCO), and the HPM frequency offset applied needs to be equal and opposite in polarity at the voltage controlled oscillator (VCO) to the frequency change that has been commanded from the PLL (using the programmed fractional division factor). Also note that this offset may be provided as a step-change, or introduced gradually, for instance as a linear or exponential ramp.

The theory underlying this correction will now be considered:
A PLL frequency is typically applied by changing the applied fractional numerator value to the low port modulation LPM Sigma-Delta modulator, for example, for a low IF receiver, transitioning between TX and RX modes at the same channel frequency, the PLL is offset by the value of the IF frequency. This change in frequency results in a constant phase change at the PLL output (assuming that everything else remains constant), as will now be shown, which can be compensated by providing an offset into the HPM.

In the case where two injection points are well matched in gain and delay, and there is no impact from the low pass filter (in other words the anti-aliasing cut-off frequency can be ignored), then: <MAT> which corresponds to an ideal wideband modulator.

If we apply a step at the HPM after the LPM frequency change step the step response of the HPM transfer function can be studied: <MAT> and <MAT>.

Applying Final Value Theorem to obtain the steady state phase change results in: <MAT>.

From this it is seen that the magnitude of the phase change required to be applied via the HPM is proportional to the frequency shift Δf, and inversely dependent on the open-loop gain K<NUM>KΦ. Seen from another viewpoint, this is equivalent to saying that the PLL phase change introduced by the change in the target frequency may be compensated by effectively changing the fixed VCO tank capacitance which causes the PLL loop to settle at the same operating point as it did before the frequency change. In a two-port PLL modulator, the PLL HPM port is a calibrated input that allows for introduction of a calibrated tank capacitance to the VCO core, that can be used to "perfectly" compensate for the phase change resulting from the LPM instituted PLL frequency. Put another way, the introduced HPM frequency offset compensation results in a PLL phase change (which is a function of Δf, Ndiv, K<NUM>, Kϕ), which nulls another phase change due to a commanded PLL frequency change. It will be appreciated that compensation using this technique is dependent on the programmable range of the HPM - typically this range is limited to a few megahertz which would normally be adequate to compensate for an IF frequency change resulting from a TX to RX transition. It will also be appreciated that the accuracy of the compensation could be impacted by the HPM resolution and calibration accuracy.

A specific example with typical values, will now be considered. In this instance, a <NUM> Bluetooth-LE (BLE) radio with a receiver IF frequency of , FIF of -<NUM>, and a PLL feedback divider, x, of <NUM>. Then for BLE channel <NUM>, the TX LO (or direct launch) frequency is <NUM>, and the (low-IF) RX LO frequency is <NUM>. <FIG> shows, on the left-hand side, case A in which there is no compensation, and case B shown on the left the right-hand side, which includes an impulse modulation on HPM of -<NUM>* FIF that is to say <NUM>*<NUM>.

The upper two traces of case A show the phase <NUM> and <NUM> of the transmit and receive signals at the PLL output. And the lower two traces <NUM> and <NUM> show the frequency of the VCO during transmit and receive, without the compensating HPM modulation. On the right-hand part of the figure, B shows the same transmit and receive frequency that the VCO at <NUM> and <NUM> respectively; however by including the above compensation at the HPM, the transmit and receive phase <NUM> and <NUM> respectively are seen to overlay each other, showing effectively perfect compensation.

The above examples have discussed compensating the PLL for the phase difference introduced (either by a phase-domain correction at LPM, or a frequency correction for HPM) by the frequency changes. In other embodiments, the PLL is not compensated, but the knowledge of the phase difference is used in the PDE calculation itself. This can be done for each of one-way PDE and two-way PDE.

Turning first to two-way PDE:
In two-way PDE between two devices A and B separated by a distance r, the estimated "phase distance", d, can be estimated as: <MAT>.

Since ØTXMn - ØRXMn = -ΔϕLOMn,steady for each of M=A, B and n=<NUM>, <NUM> <MAT>, or <MAT>, which is of the form: d = r + errorΔØ, where the error term errorΔΦ, is expressed in terms of the phase shift, and thus can be estimated using the Steady State Phase Lag concept, discussed above.

A similar analysis applies to one-way PDE. In this case: <MAT>.

Once more, this is of the form: d = r + errorΔØ, where the error terms errorΔΦ, is expressed in terms of the phase shift, and thus can be estimated suing the Steady State Phase Lag concept.

Thus using the determined total phase shift in a phase-based distance estimation process, PDE, it is possible to convert the total phase shift into a corresponding distance offset, and using the corresponding distance offset, to calculate a distance between a first device comprising the PLL, and a second device, for one-way, or two-way, distance estimation.

From reading the present disclosure, other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known in the art of type I PLLs, and which may be used instead of, or in addition to, features already described herein.

Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination. The applicant hereby gives notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claim 1:
A method of using a type I phase locked loop, PLL (<NUM>), comprising an oscillator (<NUM>) and a feedback path to a phase detector, PD (<NUM>), the method comprising:
locking a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal;
locking a second frequency different from the first frequency, and second relative phase different from the first relative phase, of a second output signal to a frequency and a phase of a second input signal; and
adjusting the second relative phase to equal the first relative phase, by a one of:
inserting a correction signal into the feedback path, wherein the feedback path includes a fractional divider (<NUM>) controlled by a Sigma Delta Modulator, SDM (<NUM>), and inserting the correction signal into the feedback path comprises inserting the correction signal into the SDM, and
adjusting the oscillator frequency.