Patent Description:
From the past, a synchronous solid-state image pickup element that picks up image data (frame) in synchronization with a synchronization signal such as a vertical synchronization signal is used in an image pickup apparatus and the like. With this general synchronous solid-state image pickup element, the image data can be acquired only in each cycle (e.g., <NUM>/<NUM> seconds) of the synchronization signal. Therefore, in a case where it is necessary to achieve processing at higher speed in the fields relating to traffic, robots, and the like, it is difficult to cope with it. In view of this, a non-synchronous solid-state image pickup element has been proposed (e.g., see Patent Literature <NUM>). The non-synchronous solid-state image pickup element includes an address event detection circuit that detects, for each pixel address, that the amount of light of that pixel exceeds the threshold as an address event in real time. The address event detection circuit is provided in each pixel. In this solid-state image pickup element, a photodiode and a plurality of transistors for detecting the address event are arranged for each pixel.

PTL <NUM>: Patent Literature <NUM>: <CIT>.

Document <CIT> discloses a solid-state image capturing apparatus that includes: a pixel array in which a plurality of pixels are arranged; a driving circuit for driving each pixel of the pixel array; and a power supply circuit for stepping down an external source voltage supplied from an external power source to generate a pixel source voltage to be supplied to each pixel of the pixel array, where the power supply circuit includes a driver transistor for generating a pixel source voltage from the external source voltage and the driver transistor is operative in a saturated state.

Document <CIT> discloses a solid-state imaging device that has: n first photoelectric conversion elements, each generating a first charge signal in which incident light is photoelectrically converted; n first read circuits corresponding to each of the n first photoelectric conversion elements, each of the n first read circuits outputting, as a first pixel signal, a signal voltage corresponding to the first charge signal generated by the corresponding first photoelectric conversion element; m second photoelectric conversion elements, each generating a second charge signal in which incident light is photoelectrically converted; m second read circuits corresponding to each of the m second photoelectric conversion elements, each successively outputting a second pixel signal based on the changes in the second charge signal generated by the corresponding second photoelectric conversion element; and a read control circuit for controlling the reading of the first pixel signal corresponding to the first photoelectric conversion element disposed in a preset read region, among the first photoelectric conversion elements. Each of the m second read circuits has: a detection circuit for detecting changes over time in the second charge signal generated by the corresponding second photoelectric conversion element, and when changes are detected that exceed a preset threshold value, outputting an event signal showing the changes; and a pixel signal generation circuit for outputting a second pixel signal to which is added address information showing the position in the event signal at which the corresponding second photoelectric conversion element is disposed. The read control circuit: determines, as a read region for reading the first pixel signal, a region based on the position in which is disposed the second photoelectric conversion element that corresponds to the address information included in the second pixel signal; and outputs each of the first pixel signals of the first read circuits corresponding to each of the first photoelectric conversion elements disposed in the determined read regions. n is an integer <NUM> or greater, and m is an integer <NUM> or greater.

Document <CIT> discloses an imaging device including a photodiode, a first transistor, a second transistor, a third transistor, and a fourth transistor. The back gate electrode of the first transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the first transistor and a potential lower than the source potential of the first transistor. The back gate electrode of the second transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the second transistor. The back gate electrode of the third transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the third transistor and a potential lower than the source potential of the third transistor.

With such a non-synchronous solid-state image pickup element, data can be generated and output at much higher speed than the synchronous solid-state image pickup element. Therefore, in the traffic field, for example, the safety can be enhanced by executing image recognition processing for a person or an obstacle at high speed. However, when the reverse bias of the photodiode is lowered due to voltage fluctuations such as lowering of a power supply voltage and raising of a ground voltage, the sensitivity of that photodiode may be lowered and the dark current may increase.

Therefore, there is a problem that the signal quality is lowered due to the insufficient sensitivity and the dark current. The sensitivity can be enhanced and the dark current can be reduced by increasing the area of the photodiode. However, the number of pixels per unit area decreases in that case, and thus it is undesirable. Further, the sensitivity can be enhanced and the dark current can be reduced also by sufficiently increasing the power supply voltage. However, the power consumption increases in that case, and thus it is unfavorable.

The present technology has been produced in view of such circumstances and it is an object to improve the signal quality of the detection signal in the solid-state image pickup element that detects the address event.

Each effective pixel includes: a photodiode configured to convert incident light into a photocurrent; an amplification transistor configured to amplify a voltage between its gate which has potential depending on the photocurrent and its source which is at a reference potential and output the amplified voltage from its drain; and a potential supply section configured to supply an anode of the photodiode and bulk (back-gate) of the amplification transistor with a predetermined potential lower than the reference potential. This configuration provides an effect that the reverse bias of the photodiode and the threshold voltage of the amplification transistor are increased.

Further, in this first aspect, the solid-state image pickup element may further include a conversion transistor configured to convert the photocurrent into a voltage between a gate and a source, in which the conversion transistor may include a source which is connected to a cathode of the photodiode and the gate of the amplification transistor, and the drain of the amplification transistor may be connected to the gate of the conversion transistor. This configuration provides an effect that the photocurrent is converted into the voltage.

Further, in this first aspect, the photodiode and the amplification transistor may be arranged in each of an effective pixel in which light is not shielded and a light-shielding pixel in which light is shielded, and the potential supply section may supply the anode of the photodiode corresponding to the effective pixel with the predetermined potential and supply the anode of the photodiode corresponding to the light-shielding pixel with the reference potential. This configuration provides an effect that a negative potential is supplied only to the effective pixel.

Further, in this first aspect, the solid-state image pickup element may further include a buffer configured to output a voltage signal output from the amplification transistor; a subtractor configured to lower a level of the voltage signal from the buffer; and a comparator configured to compare the lowered voltage signal with a predetermined threshold. This configuration provides an effect that an address event is detected.

Further, in this first aspect, the conversion transistor and the amplification transistor may be arranged in a current-to-voltage conversion circuit configured to convert the photocurrent into the voltage signal, and the current-to-voltage conversion circuit may have a power supply voltage different from a power supply voltage of the buffer, the subtractor, and the comparator. This configuration provides an effect that a current-to-voltage conversion is performed with a power supply voltage lower than the power supply voltage of the buffer and the like.

Further, in this first aspect, the buffer, the subtractor, and the comparator may include at least a part which is arranged in a circuit chip stacked on the light-receiving chip.

This configuration provides an effect that a reverse bias of a photodiode and a threshold voltage of an amplification transistor increase in a solid-state image pickup element having a stacking structure.

Further, in accordance with a second aspect of the present technology, there is provided an image pickup apparatus the solid-state image pickup element and a signal processing circuit configured to process a signal output from the amplification transistor. This configuration provides an effect that the signal from the circuit in which the reverse bias of the photodiode and the threshold voltage of the amplification transistor are increased is processed. [Advantageous.

In accordance with the present technology, an excellent effect that the signal quality of a detection signal can be improved in a solid-state image pickup element that detects an address event can be provided. It should be noted that the effect described here are not necessarily limitative and any effect described in the present disclosure may be provided.

Hereinafter, mode for carrying out the present technology (hereinafter, referred to as embodiment) will be described. Descriptions will be given in the following order.

<FIG> is a block diagram depicting a configuration example of an image pickup apparatus <NUM> according to the embodiment of the present technology. This image pickup apparatus <NUM> includes an image pickup lens <NUM>, a solid-state image pickup element <NUM>, a storage unit <NUM>, and a control unit <NUM>. Examples of provided in can include a camera to be provided in a wearable device, a vehicle-mounted camera, and the like.

The image pickup lens <NUM> condenses incident light and introduces the condensed incident light into the solid-state image pickup element <NUM>.

The solid-state image pickup element <NUM> detects that an absolute value of an amount of change of luminance exceeds a threshold for each of a plurality of pixels, as an address event. This address event includes, for example, an on-event indicating that an amount of luminance increase exceeds an upper-limit threshold and an off-event indicating that an amount of luminance decrease becomes lower than a lower-limit threshold lower than the upper-limit threshold. Then, the solid-state image pickup element <NUM> generates a detection signal indicating the detection result of the address event for each pixel. Each detection signal includes an on-event detection signal VCH indicating the presence/absence of the on-event and an off-event detection signal VCL indicating the presence/absence of the off-event. It should be noted that although the solid-state image pickup element <NUM> detects the presence/absence of both of the on-event and the off-event, the solid-state image pickup element <NUM> may detect the presence/absence of only either one of the on-event and the off-event.

The solid-state image pickup element <NUM> executes predetermined signal processing such as image recognition processing on the image data including the detection signal and outputs the processed data to the storage unit <NUM> via a signal line <NUM>.

The storage unit <NUM> stores the data from the solid-state image pickup element <NUM>. The control unit <NUM> controls the solid-state image pickup element <NUM> to pick up the image data.

<FIG> is a diagram depicting an example of a stacking structure of the solid-state image pickup element <NUM> according to the embodiment of the present technology. This solid-state image pickup element <NUM> includes a circuit board <NUM> and a light-receiving board <NUM> stacked on the circuit board <NUM>. Those boards are electrically connected to each other via a connection such as a via-hole. It should be noted that those boards may be connected to each other by Cu-Cu bonding or with a bump other than the via-hole.

<FIG> is an example of a plan view of the light-receiving board <NUM> according to the embodiment of the present technology. The light-receiving board <NUM> includes a light-receiving section <NUM> and via-hole arrangement sections <NUM>, <NUM>, and <NUM>.

Via-holes to be connected to the circuit board <NUM> are arranged in the via-hole arrangement sections <NUM>, <NUM>, and <NUM>. Further, in the light-receiving section <NUM>, a plurality of light-receiving circuits <NUM> are arranged in a matrix form. The light-receiving circuits <NUM> photoelectrically converts incident light to generate a photocurrent, performs current-to-voltage conversion on that photocurrent, and outputs the resulting voltage signal. A pixel address including a row address and a column address is assigned to each of those light-receiving circuits <NUM>.

<FIG> is an example of a plan view of the circuit board <NUM> according to the embodiment of the present technology. This circuit board <NUM> includes a negative-potential supply section <NUM>, via-hole arrangement sections <NUM>, <NUM>, and <NUM>, a signal processing circuit <NUM>, a row driving circuit <NUM>, a column driving circuit <NUM>, and an address event detection section <NUM>. Via-holes to be connected to the light-receiving board <NUM> are arranged in the via-hole arrangement sections <NUM>, <NUM>, and <NUM>.

The negative-potential supply section <NUM> supplies the light-receiving board <NUM> with a predetermined potential lower than a predetermined reference potential (e.g., ground potential). The predetermined potential is supplied as a negative potential. For example, a charge pump circuit is used as the negative-potential supply section <NUM>. Effects provided by suppling the negative potential will be described later. It should be noted that the negative-potential supply section <NUM> is an example of a potential supply section defined in the scope of claims.

The address event detection section <NUM> generates a detection signal from a voltage signal of each of the plurality of light-receiving circuits <NUM> and outputs the generated detection signal to the signal processing circuit <NUM>.

The row driving circuit <NUM> selects a row address and causes the address event detection section <NUM> to output a detection signal corresponding to that row address.

The column driving circuit <NUM> selects a column address and causes the address event detection section <NUM> to output a detection signal corresponding to that column address.

The signal processing circuit <NUM> executes predetermined signal processing on detection signals from the address event detection section <NUM>. This signal processing circuit <NUM> arranges detection signals as pixel signals in a matrix form and acquires image data including two-bit information for each pixel. Then, the signal processing circuit <NUM> executes signal processing such as image recognition processing on that image data.

<FIG> is an example of a plan view of the address event detection section <NUM> according to the embodiment of the present technology. In this address event detection section <NUM>, a plurality of address event detection circuits <NUM> are arranged in a matrix form. A pixel address is assigned to each of the address event detection circuits <NUM>. Each of the address event detection circuits <NUM> is connected to each of the light-receiving circuits <NUM>, which has the same address as the corresponding address event detection circuit <NUM>.

The address event detection circuit <NUM> quantizes a voltage signal from the corresponding light-receiving circuit <NUM> and outputs the quantized voltage signal as a detection signal.

<FIG> is a diagram for describing a configuration of an effective pixel <NUM> according to the embodiment of the present technology. The effective pixel <NUM> includes the light-receiving circuit <NUM> inside the light-receiving board <NUM> and the address event detection circuit <NUM> inside the circuit board <NUM>, to which the same pixel address is assigned. As described above, in each of the boards, the plurality of light-receiving circuits <NUM> and the plurality of address event detection circuits <NUM> are arranged in a matrix form. Therefore, a plurality of effective pixels <NUM> each including the light-receiving circuit <NUM> and the address event detection circuit <NUM> are arranged in a matrix form in the solid-state image pickup element <NUM>.

<FIG> is a circuit diagram depicting a configuration example of the effective pixel <NUM> according to the embodiment of the present technology. This effective pixel <NUM> includes a photodiode <NUM>, a current-to-voltage conversion circuit <NUM>, a buffer <NUM>, a subtractor <NUM>, a quantizer <NUM>, and a transfer circuit <NUM>.

The photodiode <NUM> photoelectrically converts incident light to generate a photocurrent. This photodiode <NUM> supplies the generated photocurrent to the current-to-voltage conversion circuit <NUM>.

The current-to-voltage conversion circuit <NUM> converts the photocurrent from the photodiode <NUM> into a voltage signal corresponding to the photocurrent. This current-to-voltage conversion circuit <NUM> inputs the voltage signal into the buffer <NUM>.

The buffer <NUM> outputs the input voltage signal to the subtractor <NUM>. With this buffer <NUM>, driving force for driving a post-stage can be increased. Further, with the buffer <NUM>, isolation of noise due to a switching operation at the post-stage can be ensured.

The subtractor <NUM> determines an amount of change of a correction signal by subtraction. This subtractor <NUM> supplies the amount of change to the quantizer <NUM> as a differential signal.

The quantizer <NUM> converts (in other words, quantizes) an analog differential signal into a digital detection signal by comparing the differential signal with a predetermined threshold. This quantizer <NUM> compares the differential signal with each of the upper-limit threshold and the lower-limit threshold and supplies the transfer circuit <NUM> as the comparison results thereof as two-bit detection signals. It should be noted that the quantizer <NUM> is an example of a comparator defined in the scope of claims.

The transfer circuit <NUM> transfers the detection signal to the signal processing circuit <NUM> in accordance with a column driving signal from the column driving circuit <NUM>.

Further, the current-to-voltage conversion circuit <NUM> includes N-type transistors <NUM> and <NUM> and a P-type transistor <NUM>. A metal-oxide-semiconductor (MOS) transistor is used as those transistors, for example.

A source of the N-type transistor <NUM> is connected to a cathode of the photodiode <NUM> and a drain of the N-type transistor <NUM> is connected to a terminal having a power supply voltage VDD1. The P-type transistor <NUM> and the N-type transistor <NUM> are connected in series between a terminal having a power supply voltage VDD2 and a terminal having a reference potential (e.g., ground potential GND). Further, a connection point between the P-type transistor <NUM> and the N-type transistor <NUM> is connected to a gate of the N-type transistor <NUM> and an input terminal of the buffer <NUM>. Further, a predetermined bias voltage Vblog is applied on a gate of the P-type transistor <NUM>.

The drain of the N-type transistor <NUM> and a drain of the N-type transistor <NUM> are connected to a side of a power supply and such a circuit is called source follower. The N-type transistor <NUM> of those transistors converts a photocurrent into a voltage between the gate and the source. The N-type transistor <NUM> amplifies a voltage between a gate having a potential depending on the photocurrent and a source having the reference potential (e.g., ground potential GND) and outputs the amplified voltage from the drain. Further, the P-type transistor <NUM> supplies a constant current to the N-type transistor <NUM>. With such a configuration, the photocurrent from the photodiode <NUM> is converted into the voltage signal.

It should be noted that the N-type transistor <NUM> is an example of a second transistor defined in the scope of claims and the N-type transistor <NUM> is an example of a first transistor defined in the scope of claims.

Further, the photodiode <NUM> and the N-type transistors <NUM> and <NUM> are arranged in the light-receiving board <NUM> and the circuits following the P-type transistor <NUM> are arranged in the circuit board <NUM>.

Then, the negative-potential supply section <NUM> supplies a negative potential Vn lower than the reference potential (e.g., ground potential GND) to a P-well region of the light-receiving board <NUM>. The photodiode <NUM> is embedded in this P-well region. Further, back-gates (bulks) of the N-type transistors <NUM> and <NUM> are formed in that region. Therefore, by supplying the negative potential Vn to the P-well region, the negative potential Vn can be supplied to an anode of the photodiode <NUM> and the respective back-gates of the N-type transistors <NUM> and <NUM>.

By setting the anode of the photodiode <NUM> to have the negative potential Vn, the reverse bias of the photodiode <NUM> is larger as compared to a case where that potential is set to the reference potential. With this setting, the sensitivity of the photodiode <NUM> is increased and the dark current can be reduced. Further, by setting the back-gates of the N-type transistors <NUM> and <NUM> to have the negative potential Vn, a threshold voltage of each transistor is higher due to a board bias effect as compared to the case where those potentials are set to the reference potential. With this setting, it is possible to prevent the voltages between the gates to the sources of those transistors from being equal to or lower than zero. When the voltages between the gates to the sources are equal to or lower than zero, it may be impossible to obtain a normal output because of the circuit configuration of the current-to-voltage conversion circuit <NUM>. Therefore, such a situation can be suppressed by supplying the negative potential Vn. In this manner, the signal quality of the detection signal can be improved due to the increased sensitivity of the photodiode <NUM>, the reduced dark current, and the higher threshold voltage.

The N-type transistors included in the circuits at the post-stage following the buffer <NUM> can also be arranged in the P-well region having the negative potential Vn. Even if such a configuration is employed, it is difficult to obtain the effect in view of the characteristics, which have been described in the context of the current-to-voltage conversion operation. Further, it is typically desirable that the current-to-voltage conversion circuit <NUM> be isolated while the circuits at the post-stage are operated having a large amplitude or a high logic level. It is thus basically favorable to provide a configuration in which the P-well region on the light-receiving side is separated from the circuits at the post-stage.

Further, the buffer <NUM> includes P-type transistors <NUM> and <NUM>. MOS transistors are used as those transistors, for example.

The P-type transistors <NUM> and <NUM> are connected in series between a terminal having the power supply voltage VDD2 and a terminal having the reference potential (e.g., GND). Further, a predetermined bias voltage Vbsf is applied on a gate of the P-type transistor <NUM>. A gate of the P-type transistor <NUM> is connected to an output terminal of the current-to-voltage conversion circuit <NUM>. Then, the voltage signal is output to the subtractor <NUM> from a connection point between the P-type transistors <NUM> and <NUM>.

The subtractor <NUM> includes capacitors <NUM> and <NUM>, P-type transistors <NUM> and <NUM>, and an N-type transistor <NUM>.

The P-type transistor <NUM> and the N-type transistor <NUM> are connected in series between a terminal having the power supply voltage VDD2 and a terminal having the reference potential. By setting a gate of the P-type transistor <NUM> as an input terminal and a connection point between the P-type transistor <NUM> and the N-type transistor <NUM> as an output terminal, the P-type transistor <NUM> and the N-type transistor <NUM> function as an inverter that inverts an input signal.

One end of the capacitor <NUM> is connected to an output terminal of the buffer <NUM> and the other end of the capacitor <NUM> is connected to an input terminal of the inverter (i.e., the gate of the P-type transistor <NUM>). The capacitor <NUM> connected in parallel to the inverter. The P-type transistor <NUM> opens/closes a path for connecting both ends of the capacitor <NUM> to each other in accordance with a row driving signal.

When the P-type transistor <NUM> is turned on, a voltage signal Vinit is input on a side of the capacitor <NUM>, which is closer to the buffer <NUM>, and an opposite side thereof is a virtual ground terminal. For the sake of convenience, the potential of this virtual ground terminal is set to zero. At this time, assuming that the capacitance of the capacitor <NUM> is C1, a potential Qinit accumulated in the capacitor <NUM> is expressed as an expression below. On the other hand, both ends of the capacitor <NUM> are shortcircuited, and thus the accumulated electric charge is zero.

Next, assuming a case where the P-type transistor <NUM> is turned off and a voltage on the side of the capacitor <NUM>, which is closer to the buffer <NUM>, changes and becomes V after, electric charge Qafter accumulated in the capacitor <NUM> is expressed as an expression below.

On the other hand, assuming that an output voltage is Vout, electric charge Q2 accumulated in the capacitor <NUM> is expressed as an expression below.

At this time, a total electric charge amount of the capacitors <NUM> and <NUM> does not change, and thus an expression below is established.

When Expression <NUM> is modified by substituting Expressions <NUM> to <NUM> into Expression <NUM>, an expression below is obtained.

Expression <NUM> expresses a subtraction operation of the voltage signal and the gain which is a subtraction result is C1/C2. It is typically desirable to maximize the gain. Therefore, it is favorable to set C1 to be large and C2 to be small. However, when C2 is too small, kTC noise increases and a noise characteristic may be deteriorated. Therefore, reduction of the capacitance of C2 is limited to such a range that noise can be allowed. Further, the subtractor <NUM> is provided in each effective pixel <NUM>. Therefore, the area for the capacitance C1 and C2 is limited. In view of those circumstances, for example, C1 is set to a value of <NUM> to <NUM> femtofarads (fF) and C2 is set to a value of <NUM> to <NUM> femtofarads (fF).

The quantizer <NUM> includes P-type transistors <NUM> and <NUM> and N-type transistors <NUM> and <NUM>. MOS transistors are used as those transistors, for example.

The P-type transistor <NUM> and the N-type transistor <NUM> are connected in series between a terminal having the power supply voltage VDD2 and a terminal having the reference potential. The P-type transistor <NUM> and the N-type transistor <NUM> are also connected in series between a terminal having the power supply voltage VDD2 and a terminal having the reference potential. Further, gates of the P-type transistors <NUM> and <NUM> are connected to an output terminal of the subtractor <NUM>. A bias voltage Vbon indicating an upper-limit threshold is applied on a gate of the N-type transistor <NUM>. A bias voltage Vboff indicating a lower-limit threshold is applied on a gate of the N-type transistor <NUM>.

A connection point between the P-type transistor <NUM> and the N-type transistor <NUM> is connected to the transfer circuit <NUM> and a voltage of this connection point is output as the on-event detection signal VCH. A connection point between the P-type transistor <NUM> and the N-type transistor <NUM> is also connected to the transfer circuit <NUM> and a voltage of this connection point is output as the off-event detection signal VCL. With such connection, the quantizer <NUM> outputs the on-event detection signal VCH at a high level if the differential signal exceeds the upper-limit threshold and outputs the off-event detection signal VCL at a low level if the differential signal becomes lower than the lower-limit threshold.

It should be noted that although the photodiode <NUM> and a part of the current-to-voltage conversion circuit <NUM> are arranged in the light-receiving board <NUM> and the circuits at the post-stage thereof are arranged in the circuit board <NUM>, the circuits arranged in the respective chips are not limited to this configuration. For example, the photodiode <NUM> and the entire current-to-voltage conversion circuit <NUM> may be arranged in the light-receiving board <NUM> and other circuits may be arranged in the circuit board <NUM>. Further, the photodiode <NUM>, the current-to-voltage conversion circuit <NUM>, and the buffer <NUM> may be arranged in the light-receiving board <NUM> and other circuits may be arranged in the circuit board <NUM>. Further, the photodiode <NUM>, the current-to-voltage conversion circuit <NUM>, the buffer <NUM>, and the capacitor <NUM> may be arranged in the light-receiving board <NUM> and other circuits may be arranged in the circuit board <NUM>. Further, the photodiode <NUM>, the current-to-voltage conversion circuit <NUM>, the buffer <NUM>, the subtractor <NUM>, and the quantizer <NUM> may be arranged in the light-receiving board <NUM> and other circuits may be arranged in the circuit board <NUM>.

<FIG> is an example of a cross-sectional view of the effective pixels <NUM> according to the embodiment of the present technology. In each P-well region of the light-receiving board <NUM>, the photodiode <NUM> is embedded and the back-gates of the N-type transistors <NUM> and <NUM> are formed. The drain of the N-type transistor <NUM> is supplied with the power supply voltage VDD1 and the potential of the source of the N-type transistor <NUM> is the reference potential (e.g., GND). Further, P-well regions of the adjacent effective pixels <NUM> are separated from each other at the long dashed short dashed line.

By supplying the back-gate (bulk) of the N-type transistor <NUM> with the negative potential Vn, a high voltage is applied between the drain and the back-gate as compared to a case where the reference potential is applied. Typically, regarding the output of the current-to-voltage conversion circuit <NUM>, it is desirable to achieve a large-amplitude operation for extending the dynamic range, and it is difficult to lower the power supply voltage VDD2 at the post-stage. However, regarding the power supply voltage VDD1, the dynamic range is not greatly affected. Therefore, it is desirable to set the power supply voltage VDD1 to be lower than the power supply voltage VDD2.

The photocurrent from all the effective pixels <NUM> flows into the negative-potential supply section <NUM>. If IR drop causes a potential gradient in the pixel plane, the pixel characteristics themselves may also be varied in the plane in a manner that depends on the IR-drop. Therefore, it is favorable to eliminate the negative potential gradient in the pixel plane by arranging via-holes at a plurality of positions of the light-receiving board <NUM> and the circuit board <NUM>.

As described above, in accordance with the embodiment of the present technology, the reverse bias of the photodiode <NUM> and the threshold voltage can be increased by supplying the negative potential Vn to the anode of the photodiode <NUM> and the back-gate of the N-type transistor <NUM> or the like. With the increased reverse bias, the sensitivity of the photodiode <NUM> can be enhanced and the dark current can be reduced. Further, with the increased threshold voltage, a situation in which it may be impossible to obtain a normal output can be suppressed. Therefore, the signal quality of the detection signal can be improved.

In the above-mentioned embodiment, the negative-potential supply section <NUM> supplies the negative potential Vn to all the pixels. However, the power consumption may increase as the number of pixels increases. A solid-state image pickup element <NUM> according to this modified example is different from the above-mentioned embodiment in that the light-shielding pixel is not supplied with the negative potential Vn.

<FIG> is an example of a plan view of a pixel array section <NUM> in the modified example of the embodiment of the present technology. This pixel array section <NUM> includes a light-receiving section <NUM> and an address event detection section <NUM> which are stacked on each other. The pixel array section <NUM> includes horizontal light-shielding pixel regions <NUM> and <NUM> and an effective pixel region <NUM>.

The plurality of effective pixels <NUM> are arranged in a matrix form in the effective pixel region <NUM>. Light is not shielded in those pixels.

On the other hand, a plurality of light-shielding pixels <NUM> are arranged in a matrix form each of the horizontal light-shielding pixel regions <NUM> and <NUM>. Light is shielded in those pixels. Further, column addresses different from those of effective pixels <NUM> are assigned to light-shielding pixels <NUM> within the horizontal light-shielding pixel regions <NUM> and <NUM>. Further, a circuit configuration of the light-shielding pixels <NUM> is similar to the effective pixels <NUM>.

The negative-potential supply section <NUM> supplies a negative potential Vn1 to the P-well region of the effective pixel <NUM>. On the other hand, the negative-potential supply section <NUM> supplies a potential Vn2 such as the reference potential (GND) to P-well regions of the light-shielding pixels <NUM>.

The signal processing circuit <NUM> and the circuits at the post-stage thereof determine a dark current amount on the basis of pixel signals from the light-shielding pixels <NUM> and remove the dark current in pixel signals from the effective pixels <NUM>.

It should be noted that although the horizontal light-shielding pixel regions <NUM> and <NUM> are arranged, a vertical light-shielding pixel region <NUM> may be arranged instead of the horizontal light-shielding pixel regions <NUM> and <NUM>, as illustrated in <FIG>. Row addresses different from those of the effective pixels <NUM> are assigned to the light-shielding pixels <NUM> within this vertical light-shielding pixel region <NUM>. Further, both of the horizontal light-shielding pixel regions <NUM> and <NUM> and the vertical light-shielding pixel region <NUM> may be arranged.

As described above, in accordance with the modified example of the embodiment of the present technology, the negative-potential supply section <NUM> supplies the negative potential Vn1 only to the effective pixels <NUM> of all the pixels. The power consumption can thus be reduced as compared to the case where the negative potential Vn1 is supplied to all the pixels.

The technology (present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any kind of movable objects such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobility, an aircraft, a drone, a ship, and a robot.

The vehicle control system <NUM> includes a plurality of electronic control units connected to each other via a communication network <NUM>. In the example depicted in <FIG>, the vehicle control system <NUM> includes a driving system control unit <NUM>, a body system control unit <NUM>, an outside-vehicle information detecting unit <NUM>, an in-vehicle information detecting unit <NUM>, and an integrated control unit <NUM>. In addition, a microcomputer <NUM>, a sound/image output section <NUM>, and a vehicle-mounted network interface (I/F) <NUM> are illustrated as a functional configuration of the integrated control unit <NUM>.

The outside-vehicle information detecting unit <NUM> detects information about the outside of the vehicle including the vehicle control system <NUM>. For example, the outside-vehicle information detecting unit <NUM> is connected with an imaging section <NUM>. The outside-vehicle information detecting unit <NUM> makes the imaging section <NUM> image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit <NUM> may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section <NUM> is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section <NUM> can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section <NUM> may be visible light, or may be invisible light such as infrared rays or the like.

In addition, the microcomputer <NUM> can output a control command to the body system control unit <NUM> on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit <NUM>.

The sound/image output section <NUM> transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of <FIG>, an audio speaker <NUM>, a display section <NUM>, and an instrument panel <NUM> are illustrated as the output device. The display section <NUM> may, for example, include at least one of an on-board display and a head-up display.

The imaging sections <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle <NUM> as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section <NUM> provided to the front nose and the imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle <NUM>. The imaging sections <NUM> and <NUM> provided to the sideview mirrors obtain mainly an image of the sides of the vehicle <NUM>. The imaging section <NUM> provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle <NUM>. The imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, <FIG> depicts an example of photographing ranges of the imaging sections <NUM> to <NUM>. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the front nose. Imaging ranges <NUM> and <NUM> respectively represent the imaging ranges of the imaging sections <NUM> and <NUM> provided to the sideview mirrors. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the rear bumper or the back door. A bird's-eye image of the vehicle <NUM> as viewed from above is obtained by superimposing image data imaged by the imaging sections <NUM> to <NUM>, for example.

At least one of the imaging sections <NUM> to <NUM> may have a function of obtaining distance information. For example, at least one of the imaging sections <NUM> to <NUM> may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer <NUM> can determine a distance to each three-dimensional object within the imaging ranges <NUM> to <NUM> and a temporal change in the distance (relative speed with respect to the vehicle <NUM>) on the basis of the distance information obtained from the imaging sections <NUM> to <NUM>, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle <NUM> and which travels in substantially the same direction as the vehicle <NUM> at a predetermined speed (for example, equal to or more than <NUM>/hour). Further, the microcomputer <NUM> can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

Hereinabove, the example of the vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to the imaging section <NUM> of the above-mentioned configurations. Specifically, the image pickup apparatus <NUM> of <FIG> can be applied to the imaging section <NUM>. By applying the technology according to the present disclosure to the imaging section <NUM>, the signal quality of the detection signal can be improved. Therefore, the accuracy of image recognition or the like using a detection signal can be improved.

Claim 1:
A solid-state image pickup element (<NUM>), comprising:
a circuit chip (<NUM>) and a light-receiving chip (<NUM>) stacked on the circuit chip (<NUM>), the chips (<NUM>, <NUM>) being electrically connected to each other via a connection;
a plurality of effective pixels in the light-receiving chip (<NUM>) arranged in a matrix form and not shielded from light, wherein each of the plurality of effective pixels includes:
a photodiode (<NUM>) configured to convert incident light into a photocurrent;
a first transistor (<NUM>) configured to amplify a voltage between a gate of the first transistor (<NUM>) having a potential depending on the photocurrent and a source of the first transistor (<NUM>) and output the amplified voltage;
and wherein
the solid-state image pickup element (<NUM>) further includes
a potential supply section (<NUM>) in the circuit chip (<NUM>) configured to supply the anode of the photodiode (<NUM>) and the bulk of the first transistor (<NUM>), in each of the plurality of effective pixels, with a predetermined potential lower than a reference potential at the source of the first transistor (<NUM>).