Patent Description:
Metrology systems typically measure the alignment of multiple layers of a sample by characterizing metrology targets having target features located on sample layers of interest. Current systems include dedicated tilt tools for measuring or determining tilt induced by an etch process on a single metrology target, with values generated for the single metrology target between a current layer and a previous layer of the sample, after the etch process has been performed. The current systems may be sensitive to different errors originating from error sources such as process variations, lithography processes, and metrology processes. Etched wafers may not be able to be re-worked should out of specification (OOS) tilts be observed, which may result in an increased throughput time and may require additional calibration to reduce the type and/or number of error sources before the errors are generated.

<CIT> discloses deriving asymmetry information, such as tilt information or overlay information, from zeroth order scattered radiation.

<CIT> discloses determining information on overlay-independent-asymmetry in a target structure from scattering measurements using cross-polarized incident-radiation on the target structure.

Therefore, it would be desirable to provide a system and method to cure the shortfalls of the previous approaches identified above.

A system for tilt calculation is disclosed, in accordance with one or more embodiments of the present disclosure. In one embodiment, the system includes a controller communicatively coupled to one or more metrology tools configured to hold a metrology sample. In another embodiment, the controller includes one or more processors configured to execute program instructions. In another embodiment, the program instructions cause the one or more processors to receive one or more overlay metrology measurements of one or more metrology targets of the metrology sample from the one or more metrology tools. In another embodiment, the one or more overlay metrology measurements are taken following an after develop inspection (ADI) process. In another embodiment, the program instructions cause the one or more processors to determine tilt from the one or more overlay metrology measurements. In another embodiment, the program instructions cause the one or more processors to predict tilt with a simulator based on at least the determined tilt. In another embodiment, the program instructions cause the one or more processors to determine one or more correctables for at least one of one or more lithography tools or the one or more metrology tools to adjust for the predicted tilt. In another embodiment, the one or more correctables are configured to reduce an amount of tilt in the sample or overlay inaccuracy of the one or more overlay metrology measurements.

A system for error reduction in metrology measurements is disclosed, in accordance with one or more embodiments of the present disclosure. In one embodiment, the system includes one or more metrology tools configured to hold a metrology sample. In another embodiment, the system includes a controller communicatively coupled to the one or more metrology tools. In another embodiment, the controller includes one or more processors configured to execute program instructions. In another embodiment, the program instructions cause the one or more processors to receive one or more overlay metrology measurements of one or more metrology targets of the metrology sample from the one or more metrology tools. In another embodiment, the one or more overlay metrology measurements are taken following an after develop inspection (ADI) process. In another embodiment, the program instructions cause the one or more processors to determine tilt from the one or more overlay metrology measurements. In another embodiment, the program instructions cause the one or more processors to predict tilt with a simulator based on at least the determined tilt. In another embodiment, the program instructions cause the one or more processors to determine one or more correctables for at least one of one or more lithography tools or the one or more metrology tools to adjust for the predicted tilt. In another embodiment, the one or more correctables are configured to reduce an amount of tilt in the sample or overlay inaccuracy of the one or more overlay metrology measurements.

A method is disclosed in accordance with one or more embodiments of the present disclosure. In one embodiment, the method may include, but is not limited to, receiving one or more overlay metrology measurements of one or more metrology targets of a metrology sample from one or more metrology tools. In another embodiment, the one or more overlay metrology measurements are taken following an after develop inspection (ADI) process. In another embodiment, the method may include, but is not limited to, determining tilt from the one or more overlay metrology measurements. In another embodiment, the method may include, but is not limited to, predicting tilt with a simulator based on at least the determined tilt. In another embodiment, the method may include, but is not limited to, determining one or more correctables for at least one of one or more lithography tools or the one or more metrology tools to adjust for the predicted tilt. In another embodiment, the one or more correctables are configured to reduce an amount of tilt in the sample or overlay inaccuracy of the one or more overlay metrology measurements.

A system for error reduction in metrology measurements is disclosed, in accordance with one or more embodiments of the present disclosure. In one embodiment, the system includes a controller communicatively coupled to one or more metrology tools configured to hold a metrology sample. In another embodiment, the controller includes one or more processors configured to execute program instructions. In another embodiment, the program instructions cause the one or more processors to receive one or more overlay metrology measurements of one or more metrology targets of the metrology sample from the one or more metrology tools. In another embodiment, the one or more overlay metrology measurements are taken during an after etch inspection (AEI) process. In another embodiment, the program instructions cause the one or more processors to determine tilt from the one or more overlay metrology measurements. In another embodiment, the program instructions cause the one or more processors to predict tilt with a simulator based on at least the determined tilt. In another embodiment, the program instructions cause the one or more processors to determine one or more correctables for at least one of one or more lithography tools or the one or more metrology tools to adjust for the determined tilt. In another embodiment, the one or more correctables are configured to reduce an amount of tilt in the sample or overlay inaccuracy of the one or more overlay metrology measurements.

A system for error reduction in metrology measurements is disclosed, in accordance with one or more embodiments of the present disclosure. In one embodiment, the system includes one or more metrology tools configured to hold a metrology sample. In another embodiment, the system includes a controller communicatively coupled to the one or more metrology tools. In another embodiment, the one or more overlay metrology measurements are taken during an after etch inspection (AEI) process. In another embodiment, the program instructions cause the one or more processors to determine tilt from the one or more overlay metrology measurements. In another embodiment, the program instructions cause the one or more processors to predict tilt with a simulator based on at least the determined tilt. In another embodiment, the program instructions cause the one or more processors to determine one or more correctables for at least one of one or more lithography tools or the one or more metrology tools to adjust for the determined tilt. In another embodiment, the one or more correctables are configured to reduce an amount of tilt in the sample or overlay inaccuracy of the one or more overlay metrology measurements.

A method is disclosed in accordance with one or more embodiments of the present disclosure. In one embodiment, the method may include, but is not limited to, receiving one or more overlay metrology measurements of one or more metrology targets of a metrology sample from one or more metrology tools. In another embodiment, the one or more overlay metrology measurements are taken during an after etch inspection (AEI) process. In another embodiment, the method may include, but is not limited to, determining tilt from the one or more overlay metrology measurements. In another embodiment, the method may include, but is not limited to, predicting tilt with a simulator based on at least the determined tilt. In another embodiment, the method may include, but is not limited to, determining one or more correctables for at least one of one or more lithography tools or the one or more metrology tools to adjust for the determined tilt. In another embodiment, the one or more correctables are configured to reduce an amount of tilt in the sample or overlay inaccuracy of the one or more overlay metrology measurements.

The present disclosure has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein are taken to be illustrative rather than limiting. It should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the scope of the disclosure.

Metrology systems typically measure the alignment of multiple layers of a sample by characterizing metrology targets having target features located on sample layers of interest. Current systems include dedicated tilt tools for measuring or determining tilt induced by an etch process, after the etch process has been performed. The current systems may be sensitive to different errors originating from error sources such as process variations, lithography processes, and metrology processes. Etched wafers may not be able to be re-worked should out of specification (OOS) tilts be observed, which may result in an increased throughput measurement time and may require additional calibration to reduce the type and/or number of error sources before the errors are generated.

Overlay (OVL) metrology tools may utilize a variety of overlay metrology technologies to determine the overlay of sample layers on a single metrology target, with values generated for the single metrology target between a current layer and a previous layer of the sample. For example, the overlay metrology technologies may include, but are not limited to, imaging, scatterometry, or a combination of overlay metrology technologies.

To reduce or minimize tilt and/or allow for the re-work of the wafer, overlay metrology tools may replace the dedicated tilt tools. This replacement may allow for the predicting or calculating of tilt induced by an etching process for a next step, the predicting or calculating of the tilt occurs during an after develop inspection (ADI) process and/or an after etch inspection (AEI) process.

As such, embodiments of the present disclosure are directed to a system and method for tilt calculation based on overlay metrology measurements. Specifically, embodiments of the present disclosure are directed to methods for predicting and/or adjusting tilt signatures, and a corresponding system configured to predict for and/or adjust for tilt signatures.

Advantages of the present disclosure include determining tilt induced by an etching process using overlay AEI data. Advantages of the present disclosure also include calculating etch tilt for a previous layer using overlay ADI data. Advantages of the present disclosure also include predicting tilt for an N+<NUM> etch step using overlay ADI data. Advantages of the present disclosure also include correcting an overlay measurement in an ADI process based on tilt information for a previous layer for better overlay accuracy.

<FIG> in general illustrate a system and method for tilt calculation based on overlay metrology measurements, in accordance with one or more embodiments of the present disclosure.

<FIG> in general illustrate a system <NUM>, in accordance with one or more embodiments of the present disclosure.

As illustrated in at least <FIG>, in one embodiment, the system <NUM> includes one or more lithography sub-systems <NUM> for lithographically imaging one or more pattern elements of a pattern mask (e.g., device pattern elements, metrology target pattern elements, or the like) on a sample. For the purposes of the present disclosure, it is noted herein that a lithography sub-system <NUM> may be referred to as a lithography tool. For example, the lithography sub-system <NUM> may include any lithographic tool known in the art including, but not limited to, an etcher, scanner, stepper, cleaner, or the like. A fabrication process may include fabricating multiple dies distributed across the surface of a sample (e.g., a semiconductor wafer, or the like), where each die includes multiple patterned layers of material forming a device component. Each patterned layer may be formed by lithography tools via a series of steps including material deposition, lithography, etching to generate a pattern of interest, and/or one or more exposure steps (e.g., performed by a scanner, a stepper, or the like). For purposes of the present disclosure, it is noted herein a lithography sub-system <NUM> may be a single lithography tool or may represent a group of lithography tools.

In another embodiment, the system <NUM> includes one or more metrology sub-systems <NUM> to characterize one or more features on the sample. The system <NUM> may incorporate metrology measurements at one or more points during a fabrication process to monitor and control the fabrication of features on a particular sample and/or across multiple samples. For the purposes of the present disclosure, it is noted herein that a metrology sub-system <NUM> may be referred to as a metrology tool. For example, the metrology sub-system <NUM> may include an overlay metrology tool suitable for measuring relative positions of features of a sample. In one embodiment, the metrology sub-system <NUM> includes an image-based metrology tool to measure metrology data based on the generation of one or more images of a sample. In another embodiment, the metrology sub-system <NUM> includes an electron beam-based metrology system. For example, the metrology sub-system <NUM> may include a scatterometry-based metrology system (e.g., a scatterometry overlay (SCOL) metrology system) to measure metrology data based on the scattering (reflection, diffraction, diffuse scattering, or the like) of light from the sample. For purposes of the present disclosure, it is noted herein a metrology sub-system <NUM> may be a single metrology tool or may represent a group of metrology tools.

It is noted herein an adjustment to the system <NUM> based on a characterization of a sample may reduce noise originating from one or more sources of errors including, but not limited to, process variations, lithography processes, and metrology processes. For example, the one or more sources of errors may stem from a lithography flow and include, but are not limited to, mask printability errors, lithography tool errors, process tool errors (e.g., etchers, cleaners, or the like), and metrology tool errors.

In another embodiment, the system <NUM> includes a controller <NUM>. The controller <NUM> may include one or more processors <NUM> configured to execute program instructions maintained on a memory medium <NUM>. In this regard, the one or more processors <NUM> of controller <NUM> may execute any of the various process steps described throughout the present disclosure.

The one or more processors <NUM> of a controller <NUM> may include any processing element known in the art. In this sense, the one or more processors <NUM> may include any microprocessor-type device configured to execute algorithms and/or instructions. For example, the algorithms and/or instructions may include, but are not limited to, calculations using different weighted averages (e.g., where weighting may be generated using metrology target quality), a machine learning algorithm, and/or other algorithmic-based methodology. In one embodiment, the one or more processors <NUM> may consist of a desktop computer, mainframe computer system, workstation, image computer, parallel processor, or any other computer system (e.g., networked computer) configured to execute a program configured to operate the system <NUM>, as described throughout the present disclosure. It is further recognized that the term "processor" may be broadly defined to encompass any device having one or more processing elements, which execute program instructions from a non-transitory memory medium <NUM>. Further, the steps described throughout the present disclosure may be carried out by a single controller <NUM> or, alternatively, multiple controllers. In addition, the controller <NUM> may include one or more controllers housed in a common housing or within multiple housings. In this way, any controller or combination of controllers may be separately packaged as a module suitable for integration into system <NUM>. Further, the controller <NUM> may analyze data received from a detector and feed the data to additional components within the system <NUM> (e.g., the lithography sub-system <NUM>) or external to the system <NUM>.

The memory medium <NUM> may include any storage medium known in the art suitable for storing program instructions executable by the associated one or more processors <NUM>. For example, the memory medium <NUM> may include a non-transitory memory medium. By way of another example, the memory medium <NUM> may include, but is not limited to, a read-only memory, a random-access memory, a magnetic or optical memory device (e.g., disk), a magnetic tape, a solid-state drive and the like. It is further noted that memory medium <NUM> may be housed in a common controller housing with the one or more processors <NUM>. In one embodiment, the memory medium <NUM> may be located remotely with respect to the physical location of the one or more processors <NUM> and controller <NUM>. For instance, the one or more processors <NUM> of controller <NUM> may access a remote memory (e.g., server), accessible through a network (e.g., internet, intranet and the like). Therefore, the above description should not be interpreted as a limitation on the present invention but merely an illustration.

As illustrated in at least <FIG>, in one embodiment, the lithography sub-system <NUM> includes a lithography illumination source <NUM> configured to generate an illumination beam <NUM>. The one or more illumination beams <NUM> may include one or more selected wavelengths of light including, but not limited to, ultraviolet (UV) radiation, visible radiation, or infrared (IR) radiation.

Illumination from the lithography illumination source <NUM> may have any spatial distribution (e.g., illumination pattern). For example, the lithography illumination source <NUM> may include, but is not limited to, a single-pole illumination source, a dipole illumination source, a C-Quad illumination source, a Quasar illumination source, or a free-form illumination source. In this regard, the lithography illumination source <NUM> may generate on-axis illumination beams <NUM> in which illumination propagates along (or parallel to) an optical axis <NUM> and/or any number of off-axis illumination beams <NUM> in which illumination propagates at an angle to the optical axis <NUM>.

It is noted herein that, for the purposes of the present disclosure, an illumination pole of the lithography illumination source <NUM> may represent illumination from a specific location. In this regard, each spatial location of the lithography illumination source <NUM> (e.g., with respect to the optical axis <NUM>) may be considered an illumination pole. Further, an illumination pole may have any shape or size known in the art. In addition, the lithography illumination source <NUM> may be considered to have an illumination profile corresponding to a distribution of illumination poles.

Further, the lithography illumination source <NUM> may generate the illumination beams <NUM> by any method known in the art. For example, an illumination beam <NUM> may be formed as illumination from an illumination pole of the lithography illumination source <NUM> (e.g., a portion of an illumination profile of a lithography illumination source <NUM>, or the like). By way of another example, lithography illumination source <NUM> may include multiple illumination sources for the generation of multiple illumination beams <NUM>.

In another embodiment, the lithography sub-system <NUM> includes a mask support device <NUM>. The mask support device <NUM> is configured to secure a pattern mask <NUM>. In another embodiment, the lithography sub-system <NUM> includes a set of projection optics <NUM> configured to project an image of the pattern mask <NUM> illuminated by the one or more illumination beams <NUM> onto a sample <NUM> disposed on a sample stage <NUM> in order to generate printed pattern elements corresponding to the image of the pattern mask <NUM>. In another embodiment, the mask support device <NUM> may be configured to actuate or position the pattern mask <NUM>. For example, the mask support device <NUM> may actuate the pattern mask <NUM> to a selected position with respect to the projection optics <NUM> of the system <NUM>.

The sample <NUM> may include any number of photosensitive materials and/or material layers suitable for receiving the image of the pattern mask <NUM>. For example, the sample <NUM> may include a resist layer <NUM>. In this regard, the set of projection optics <NUM> may project an image of the pattern mask <NUM> onto the resist layer <NUM> to expose the resist layer <NUM> and a subsequent etching step may remove the exposed material (e.g., positive etching) or the unexposed material (e.g., negative etching) in order to provide printed features on the sample <NUM>. Further, the pattern mask <NUM> may be utilized in any imaging configuration known in the art. For example, the pattern mask <NUM> may be a positive mask (e.g., a bright-field mask) in which pattern elements are positively imaged as printed pattern elements. By way of another example, the pattern mask <NUM> may be a negative mask (e.g., a dark-field mask) in which pattern elements of the pattern mask <NUM> form negative printed pattern elements (e.g., gaps, spaces, or the like).

The sample <NUM> may include one or more fields. Each field of the one or more fields includes one or more overlay metrology targets. For purposes of the present disclosure, it is noted herein that overlay metrology targets may be referred to as metrology targets or overlay targets. For example, a sample <NUM> may include four metrology targets for scatterometry technology. The one or more metrology targets may be of different types, such that different metrology targets have different target designs. The four metrology targets may be allocated near one another on the sample <NUM>, but may be different in one or more of critical dimension (CD), pitch, and/or segmentation size. The four metrology targets may be located in several locations per field on each field of the sample <NUM>, such that a total number of locations of metrology targets may be up to several thousand locations.

The controller <NUM> may be communicatively coupled to any element or combination of elements in the lithography sub-system <NUM> including, but not limited to, the mask support device <NUM> and/or the sample stage <NUM> to direct the transfer of pattern elements on a pattern mask <NUM> to a sample <NUM>, the lithography illumination source <NUM> to control one or more characteristics of the illumination beam <NUM>.

<FIG> is a block diagram view of the metrology sub-system <NUM>, in accordance with one or more embodiments of the present disclosure. The system <NUM> may generate one or more images associated with light emanating from the sample <NUM> (e.g., sample light <NUM>) on at least one detector <NUM> using any method known in the art. In one embodiment, the detector <NUM> is located at a field plane to generate an image of one or more features on the sample <NUM>. In this regard, the system <NUM> may operate as an image-based overlay metrology tool. In another embodiment, the detector <NUM> is located at a pupil plane to generate an image based on angles of light emanating from the sample <NUM> (e.g., based on reflection, diffraction, scattering, or the like). In this regard, the system <NUM> may operate as a scatterometry-based metrology tool.

In one embodiment, the metrology sub-system <NUM> includes a metrology illumination source <NUM> to generate a metrology illumination beam <NUM>. The metrology illumination source <NUM> may be the same as the lithography illumination source <NUM> or may be a separate illumination source configured to generate a separate metrology illumination beam <NUM>. The metrology illumination beam <NUM> may include one or more selected wavelengths of light including, but not limited to, vacuum ultraviolet (VUV) radiation, deep ultraviolet (DUV) radiation, ultraviolet (UV) radiation, visible radiation, or infrared (IR) radiation. The metrology illumination source <NUM> may further generate a metrology illumination beam <NUM> including any range of selected wavelengths. In another embodiment, the metrology illumination source <NUM> may include a spectrally-tunable illumination source to generate a metrology illumination beam <NUM> having a tunable spectrum.

The metrology illumination source <NUM> may further produce a metrology illumination beam <NUM> having any temporal profile. For example, the metrology illumination source <NUM> may produce a continuous metrology illumination beam <NUM>, a pulsed metrology illumination beam <NUM>, or a modulated metrology illumination beam <NUM>. In addition, the metrology illumination beam <NUM> may be delivered from the metrology illumination source <NUM> via free-space propagation or guided light (e.g., an optical fiber, a light pipe, or the like).

In another embodiment, the metrology illumination source <NUM> directs the metrology illumination beam <NUM> to the sample <NUM> via an illumination pathway <NUM>. The illumination pathway <NUM> may include one or more lenses <NUM> or additional illumination optical components <NUM> suitable for modifying and/or conditioning the metrology illumination beam <NUM>. For example, the one or more illumination optical components <NUM> may include, but are not limited to, one or more polarizers, one or more filters, one or more beam splitters, one or more diffusers, one or more homogenizers, one or more apodizers, one or more beam shapers, or one or more shutters (e.g., mechanical shutters, electro-optical shutters, acousto-optical shutters, or the like). By way of another example, the one or more illumination optical components <NUM> may include aperture stops to control the angle of illumination on the sample <NUM> and/or field stops to control the spatial extent of illumination on the sample <NUM>. In one instance, the illumination pathway <NUM> includes an aperture stop located at a plane conjugate to the back focal plane of an objective lens <NUM> to provide telecentric illumination of the sample. In another embodiment, the system <NUM> includes an objective lens <NUM> to focus the metrology illumination beam <NUM> onto the sample <NUM>.

In another embodiment, the sample <NUM> is disposed on a sample stage <NUM>. The sample stage <NUM> may include any device suitable for positioning the sample <NUM> within the system <NUM>. For example, the sample stage <NUM> may include any combination of linear translation stages, rotational stages, tip/tilt stages, or the like.

For purposes of the present disclosure, in some embodiments the sample <NUM> may be considered a metrology sample <NUM>.

In another embodiment, a detector <NUM> is configured to capture radiation emanating from the sample <NUM> (e.g., sample light <NUM>) through a collection pathway <NUM>. For example, the collection pathway <NUM> may include, but is not required to include, a collection lens (e.g., the objective lens <NUM> as illustrated in <FIG>) or one or more additional collection pathway lenses <NUM>. In this regard, a detector <NUM> may receive radiation reflected or scattered (e.g., via specular reflection, diffuse reflection, and the like) from the sample <NUM> or generated by the sample <NUM> (e.g., luminescence associated with absorption of the metrology illumination beam <NUM>, or the like).

The collection pathway <NUM> may further include any number of collection optical components <NUM> to direct and/or modify illumination collected by the objective lens <NUM> including, but not limited to, one or more collection pathway lenses <NUM>, one or more filters, one or more polarizers, or one or more beam blocks. In addition, the collection pathway <NUM> may include field stops to control the spatial extent of the sample imaged onto the detector <NUM> or aperture stops to control the angular extent of illumination from the sample used to generate an image on the detector <NUM>. In another embodiment, the collection pathway <NUM> includes an aperture stop located in a plane conjugate to the back focal plane of an optical element the objective lens <NUM> to provide telecentric imaging of the sample.

The detector <NUM> may include any type of optical detector known in the art suitable for measuring illumination received from the sample <NUM>. For example, a detector <NUM> may include a sensor suitable for generating one or more images of a static sample <NUM> (e.g., in a static mode of operation) such as, but is not limited to, a charge-coupled device (CCD), a complementary metal-oxide-semiconductor (CMOS) sensor, a photomultiplier tube (PMT) array, or an avalanche photodiode (APD) array. By way of another example, a detector <NUM> may include a sensor suitable for generating one or more images of a sample <NUM> in motion (e.g., a scanning mode of operation) including, but not limited to, a line sensor or a time delay and integration (TDI) sensor.

In another embodiment, a detector <NUM> may include a spectroscopic detector suitable for identifying wavelengths of radiation emanating from the sample <NUM>. In another embodiment, the system <NUM> may include multiple detectors <NUM> (e.g., associated with multiple beam paths generated by one or more beam splitters) to facilitate multiple metrology measurements by the system <NUM>.

In one embodiment, the system <NUM> includes a beam splitter <NUM> oriented such that the objective lens <NUM> may simultaneously direct the metrology illumination beam <NUM> to the sample <NUM> and collect radiation emanating from the sample <NUM>. In this regard, the system <NUM> may be configured in an epi-illumination mode.

In another embodiment, as illustrated in <FIG>, the controller <NUM> is communicatively coupled to one or more elements of the system <NUM>. In this regard, the controller <NUM> may transmit and/or receive data from any component of the system <NUM>. For example, the controller <NUM> may be configured to receive data including, but not limited to, one or more images from the detector <NUM> of the sample <NUM>.

In one embodiment, the sample <NUM> may be designed and/or fabricated to be used for the system and method for tilt calculation based on overlay metrology measurements described throughout the present disclosure.

<FIG> is a signature graph <NUM> illustrating a tilt signature induced by a lithography sub-system <NUM>, in accordance with one or more embodiments of the present disclosure. In one embodiment, the lithography sub-system <NUM> is an etcher, and the signature graph <NUM> includes a tilt signature induced by the etcher. In another embodiment, the tilt-induced etch illustrated in the signature graph <NUM> of <FIG> has a unique radial signature due to the etcher methodology of operation. It is noted herein tilt induced by the etcher (or etch process) is one factor for lost product yield, while preventing re-working of any wafer with high tilt (e.g., OOS tilt).

<FIG> illustrates a signature graph <NUM> including an overlay signature measured in an ADI step, in accordance with one or more embodiments of the present disclosure. In one embodiment, the signature graph <NUM> includes a tilt signature induced by the etcher. In another embodiment, the tilt-induced etch illustrated in the signature graph <NUM> of <FIG> impacts the overlay measured during the ADI step. In another embodiment, the tilt-induced etch illustrated in the signature graph <NUM> of <FIG> impacts the overlay performance and accuracy. <FIG> illustrates an example cross-section of an ADI sample <NUM> corresponding to the signature graph <NUM>, in accordance with one or more embodiments of the present disclosure. In one embodiment, the ADI sample <NUM> is fabricated from one or more layers. For example, the ADI sample <NUM> includes a silicon layer <NUM>. By way of another example, the ADI sample <NUM> includes an AEI N-<NUM> layer <NUM>, or a layer fabricated in a previous (e.g., N-<NUM>) AEI step. By way of another example, the ADI sample <NUM> includes a polymer layer <NUM>. By way of another example, the ADI sample <NUM> includes a hard mask layer <NUM>. By way of another example, the ADI sample <NUM> includes a bottom anti-reflective coating (BARC) or layer <NUM>. By way of another example, the ADI sample <NUM> includes a photo resist layer <NUM>.

<FIG> in general illustrate signature graphs and corresponding data tables, in accordance with one or more embodiments of the present disclosure. In one embodiment, tilt induced by the etcher, having a radial signature, is sensitive to cross-polarization. For example, <FIG> illustrates a signature graph <NUM> for a wafer under unpolarized light (Un-Pol), and a corresponding data table <NUM> including information for an overlay mean + <NUM> sigma (σ), and overlay range, in both an X-direction and a Y-direction under Un-Pol. By way of another example, <FIG> illustrates a signature graph <NUM> for a wafer under P-polarized light (P-Pol), and a corresponding data table <NUM> including information for an overlay mean + <NUM>σ, and overlay range, in both an X-direction and a Y-direction under P-Pol. By way of another example, <FIG> illustrates a signature graph <NUM> for a wafer under S-polarized light (S-Pol), and a corresponding data table <NUM> including information for an overlay mean + <NUM>σ, and overlay range, in both an X-direction and a Y-direction under S-Pol. As illustrated in <FIG>, overlay is sensitive to polarization, which may have an impact on overlay mean (or overlay mean + <NUM>σ) and/or overlay range of variation.

<FIG> illustrates a graph <NUM> comparing overlay inaccuracy impacted by polarization, in accordance with one or more embodiments of the present disclosure. In one embodiment, polarization impacts the accuracy of overlay measurements. For example, graph <NUM> compares overlay measurement inaccuracy (in nanometer, or nm) to bar size (in nm) for a wafer under un-polarized light (e.g., line <NUM>), under P-polarized light (e.g., line <NUM>) and under S-polarized light (e.g., line <NUM>). <FIG> illustrates an example cross-section of a pattern material stack sample <NUM> corresponding to the graph <NUM>, in accordance with one or more embodiments of the present disclosure.

In one embodiment, overlay metrology information is used to detect the etch-induced tilt signature in a wafer for the AEI N-<NUM> step. For example, the etch-induced tilt signature may be detected by measuring a previous layer in an ADI process using an imaging metrology target (e.g., an advanced imaging metrology (AIM) target, a box-in-box (BiB) metrology target, a ProAIM™ target, or the like). By way of another example, the etch-induced tilt signature may be detected by measuring a previous layer in an ADI process using cross-polarization. By way of another example, the etch-induced tilt signature may be detected by measuring a previous layer in an ADI process by extraction information from a previous (e.g., N-<NUM>) layer.

In one illustrative example embodiment, extracting the tilt signature may include calculating the ratio between a contrast precision (CP) taken from S-polarization measurements and a contrast precision (CP) taken from P-polarization measurements, as illustrated in EQ. <NUM>: <MAT>.

<NUM>, CP is the contrast precision measurement from a previous layer at different polarizations (e.g., CPS for S-polarization, and CPP for P-polarization), k is an index running on all targets located in a wafer, and n is an upper boundary for the index k.

From the cross-polarization measurements, a module may be calculated for extracting the rotation term or signature, as illustrated in EQ. <NUM>: <MAT>.

<NUM>, anm are coefficients, <MAT> is the overlay value in the X direction, <MAT> is the overlay value in the Y direction, n and m are indexes running on all targets located in a wafer, and Nloc is an upper boundary for the indexes n and m. Also in EQ. <NUM>, bnm is the position on the wafer, <MAT> is the overlay value in the X direction, <MAT> is the overlay value in the Y direction, n and m are indexes running on all targets located in a wafer, and Npos is an upper boundary for the indexes n and m. It is noted herein the coefficient -a<NUM> is related to rotation term or signature.

In another illustrative example embodiment, tilt may be calculated by taking through focus (TF) measurement for a previous layer (e.g., N-<NUM>) and characterizing the AEI N-<NUM> profile. A calibration for TF and/or CP may be completed prior to the ADI measurements using an Optical Critical Dimension (OCD) library to correlate between focus and CP to a stack geometry of the wafer.

It is noted herein this example embodiment may also be performed with additional information taken from overlay measurements such as accuracy matrix (e.g., a Qmerit function, Kernel variation, through focus, or the like), as illustrated in EQ. <NUM>: <MAT>.

<NUM>, CP is the contrast precision measurement from a previous layer at different polarizations (e.g., CPS for S-polarization, and CPP for P-polarization), TF is the through focus measurement from the previous layer at different polarizations (e.g., TFS for S-polarization, and TFP for P-polarization), Qmerit is the Qmerit function measurement from the previous layer at different polarizations (e.g., QmeritS for S-polarization, and QmerítP for P-polarization), k is an index running on all targets located in a wafer, n is an upper boundary for the index k, and N is a coefficient which is normalized per merit quality (e.g., N<NUM> + N<NUM> + N<NUM> = <NUM>).

In one embodiment, the tilt signature may be taken and used with an etch simulator to predict the etch tilt for the N+<NUM> step. <FIG> illustrates a method or process <NUM> for predicting and adjusting for etch tilt, in accordance with one or more embodiments of the present disclosure.

In a step <NUM>, overlay is measured for a wafer. In one embodiment, overlay is measured with a metrology sub-system <NUM> for a previous layer (e.g., N-<NUM>) of a sample <NUM> during an ADI step.

In a step <NUM>, tilt within the measured overlay is determined. In one embodiment, an etch-induced tilt signature for the previous layer is calculated by the controller <NUM> using the overlay ADI measurements.

In a step <NUM>, tilt is predicted with a simulator. In one embodiment, the tilt is predicted for the N+<NUM> etch step using the overlay ADI measurements and the etch-induced tilt signature by the controller <NUM>.

In a step <NUM>, one or more correctables are determined for a lithography sub-system or a metrology sub-system based on the predicted tilt. In one embodiment, the one or more correctables are determined by the controller <NUM> for the lithography sub-system <NUM> and/or the metrology sub-system <NUM>. In another embodiment, the one or more correctables are provided to the lithography sub-system <NUM> and/or the metrology sub-system <NUM> as one or more control signals. For example, utilization of the one or more correctables by the lithography sub-system <NUM> and/or the metrology sub-system <NUM> may reduce or minimize tilt in the sample <NUM>.

In a step <NUM>, the lithography sub-system is adjusted based on the one or more correctables for the next layer (e.g., N+<NUM> step). In one embodiment, the lithography sub-system <NUM> is an etcher. For example, the signature for etch-induced tilt should be robust and stable, being from dedicated etchers used in an integrated circuitry (IC) process. In another embodiment, one or more operational parameters of the etcher are adjusted based on the one or more correctables to offset the predicted tilt in the N+<NUM> layer of the sample <NUM>.

In a step <NUM>, the lithography sub-system is adjusted based on the one or more correctables for the previous layer (e.g., N-<NUM> step) of the wafer. In one embodiment, one or more operational parameters of the lithography sub-system <NUM> are adjusted based on the one or more correctables to re-work the N-<NUM> layer of the sample <NUM>. It is noted herein, however, the one or more operational parameters of the lithography sub-system <NUM> may be adjusted based on the one or more correctables to fabricate an N-<NUM> layer of a second sample <NUM> with the adjustments, instead of re-working the measured sample <NUM>.

It is noted herein having information about etch-induced tilt during the ADI step may improve the yield of a wafer lot and reduce or minimize scrapped wafers by allowing for the performing of re-working on wafers with tilt excursion already in the ADI step. In addition, having information about etch-induced tilt may increase or optimize the operational parameters of the etcher (e.g., length of etch time, amount of etch material, or the like).

In a step <NUM>, the metrology sub-system is adjusted based on the one or more correctables. In one embodiment, the metrology sub-system <NUM> is adjusted to improve the accuracy of the overlay measurements (e.g., the measurements taken in step <NUM>).

Although embodiments of the present disclosure are directed to predicted etch-induced tilt during the ADI step, it is noted herein a similar approach may be taken with the AEI step. <FIG> illustrates a method or process <NUM> for extracting and adjusting for etch tilt, in accordance with one or more embodiments of the present disclosure.

In a step <NUM>, overlay is measured for a wafer. In one embodiment, overlay is measured of a sample <NUM> with a metrology sub-system <NUM> during an AEI step. For example, the same imaging metrology targets used in the ADI step (e.g., as discussed with respect to the method or process <NUM>) may be measured during the AEI step.

In a step <NUM>, tilt within the measured overlay is determined. In one embodiment, an etch-induced tilt signature for the current layer is extracted by the controller <NUM> from the overlay AEI measurements.

In a step <NUM>, one or more correctables are determined for a lithography sub-system or a metrology sub-system based on the determined tilt. In one embodiment, the one or more correctables are determined by the controller <NUM> for the lithography sub-system <NUM> and/or the metrology sub-system <NUM>. In another embodiment, the one or more correctables are provided to the lithography sub-system <NUM> and/or the metrology sub-system <NUM> as one or more control signals. For example, utilization of the one or more correctables by the lithography sub-system <NUM> and/or the metrology sub-system <NUM> may reduce or minimize tilt in the sample <NUM>.

In a step <NUM>, the lithography sub-system is adjusted based on the one or more correctables for the previous layer (e.g., N-<NUM> step) of the wafer. In one embodiment, the lithography sub-system <NUM> is an etcher. For example, the signature for etch-induced tilt should be robust and stable, being from dedicated etchers used in an integrated circuitry (IC) process. In another embodiment, one or more operational parameters of the lithography sub-system <NUM> are adjusted based on the one or more correctables to fabricate an N-<NUM> layer of a second wafer with the adjustments, instead of re-working the measured wafer. It is noted herein, however, the one or more operational parameters of the lithography sub-system <NUM> may be adjusted based on the one or more correctables to re-work the N-<NUM> layer of the wafer.

It is noted herein having information about etch-induced tilt during the AEI step may reduce a number of dedicated tilt metrology tools required, by increasing utilization of overlay metrology tools.

Although embodiments of the present disclosure are directed to determining signatures for etch-induced tilt, it is noted herein signatures may be determined for tilt induced by other lithography processes or sub-systems. Therefore, the above description should not be interpreted as a limitation on the present disclosure but merely an illustration.

It is noted herein the one or more processors <NUM> of the controller <NUM> may be configured to perform one or more steps of the methods or processes <NUM> and <NUM>, as described above.

In addition, it is noted herein the steps of the methods or processes <NUM> and <NUM> may be implemented all or in part by the system <NUM> and/or components of the system <NUM>. It is further recognized, however, that the methods or processes <NUM> and <NUM> are not limited to the system <NUM> and/or components of the system <NUM> in that additional or alternative system-level embodiments may carry out all or part of the methods or processes <NUM> and <NUM>.

Further, it is noted herein the methods or processes <NUM> and <NUM> are not limited to the steps and/or sub-steps provided. The methods or processes <NUM> and <NUM> may include more or fewer steps and/or sub-steps. The methods or processes <NUM> and <NUM> may perform the steps and/or sub-steps simultaneously. For example, steps <NUM>, <NUM>, and <NUM> may be performed simultaneously. The methods or processes <NUM> and <NUM> may perform the steps and/or sub-steps sequentially, including in the order provided or an order other than provided. For example, steps <NUM>, <NUM>, and <NUM> may be performed in a particular order or subset of order. Therefore, the above description should not be interpreted as a limitation on the scope of the disclosure but merely an illustration.

All of the methods or processes described herein may include storing results of one or more steps of the method or process embodiments in memory. The results may include any of the results described herein and may be stored in any manner known in the art. The memory may include any memory described herein or any other suitable storage medium known in the art. After the results have been stored, the results can be accessed in the memory and used by any of the method or system embodiments described herein, formatted for display to a user, used by another software module, method, or system, and the like. Furthermore, the results may be stored "permanently," "semi-permanently," temporarily," or for some period of time. For example, the memory may be random access memory (RAM), and the results may not necessarily persist indefinitely in the memory.

It is noted herein that any language directed to a particular embodiment described in the present disclosure may be applicable to a different embodiment described in the present disclosure, such that the various embodiments described in the present disclosure should not be considered standalone or separate embodiments. For example, the present disclosure may be read as being able to combine any number of one or more metrology targets, one or more layers, one or more cells, one or more target designs, and/or one or more pitches or other parameters or metrics of the target design as described throughout the present disclosure on the sample <NUM>. By way of another example, the present disclosure may be read as being able to combine any number of metrology sample or target design processes, fabrication processes, and/or measurement processes as described throughout the present disclosure. Therefore, the above description should not be interpreted as a limitation on the present disclosure but merely an illustration.

In this regard, the embodiments of the present disclosure illustrate new methods and systems for determining tilt induced by an etching process using overlay AEI data. In addition, the new methods and systems may calculate etch tilt for a previous layer using overlay ADI data. Further, the new methods and systems may predict tilt for an N+<NUM> etch step using overlay ADI data. Further, the new methods and systems may calculate an overlay measurement in an ADI process based on tilt information for a previous layer for better overlay accuracy.

One skilled in the art will recognize that the herein described components (e.g., operations), devices, objects, and the discussion accompanying them are used as examples for the sake of conceptual clarity and that various configuration modifications are contemplated. Consequently, as used herein, the specific exemplars set forth and the accompanying discussion are intended to be representative of their more general classes. In general, use of any specific exemplar is intended to be representative of its class, and the non-inclusion of specific components (e.g., operations), devices, and objects should not be taken as limiting.

Those having skill in the art will appreciate that there are various vehicles by which processes and/or systems and/or other technologies described herein can be effected (e.g., hardware, software, and/or firmware), and that the preferred vehicle will vary with the context in which the processes and/or systems and/or other technologies are deployed. For example, if an implementer determines that speed and accuracy are paramount, the implementer may opt for a mainly hardware and/or firmware vehicle; alternatively, if flexibility is paramount, the implementer may opt for a mainly software implementation; or, yet again alternatively, the implementer may opt for some combination of hardware, software, and/or firmware. Hence, there are several possible vehicles by which the processes and/or devices and/or other technologies described herein may be effected, none of which is inherently superior to the other in that any vehicle to be utilized is a choice dependent upon the context in which the vehicle will be deployed and the specific concerns (e.g., speed, flexibility, or predictability) of the implementer, any of which may vary.

The previous description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. As used herein, directional terms such as "top," "bottom," "over," "under," "upper," "upward," "lower," "down," and "downward" are intended to provide relative positions for purposes of description, and are not intended to designate an absolute frame of reference. Various modifications to the described embodiments will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described. Rather, the invention is defined by the appended claims.

The various singular/plural permutations are not expressly set forth herein for sake of clarity.

All of the methods described herein may include storing results of one or more steps of the method embodiments in memory. The results may include any of the results described herein and may be stored in any manner known in the art. The memory may include any memory described herein or any other suitable storage medium known in the art. After the results have been stored, the results can be accessed in the memory and used by any of the method or system embodiments described herein, formatted for display to a user, used by another software module, method, or system, and the like. Furthermore, the results may be stored "permanently," "semi-permanently," temporarily," or for some period of time. For example, the memory may be random-access memory (RAM), and the results may not necessarily persist indefinitely in the memory.

It is further contemplated that each of the embodiments of the method described above may include any other step(s) of any other method(s) described herein. In addition, each of the embodiments of the method described above may be performed by any of the systems described herein.

The herein described subject matter sometimes illustrates different components contained within, or connected with, other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. Likewise, any two components so associated can also be viewed as being "connected," or "coupled," to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being "couplable," to each other to achieve the desired functionality. Specific examples of couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.

Furthermore, it is to be understood that the invention is defined by the appended claims. It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes but is not limited to," and the like). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to inventions containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and/or "an" should typically be interpreted to mean "at least one" or "one or more"); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of "two recitations," without other modifiers, typically means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to "at least one of A, B, and C, and the like" is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., " a system having at least one of A, B, and C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, and the like). In those instances where a convention analogous to "at least one of A, B, or C, and the like" is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., " a system having at least one of A, B, or C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, and the like). It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms.

Claim 1:
A system (<NUM>) for tilt calculation based on overlay metrology measurements comprising:
a controller (<NUM>) communicatively coupled to one or more metrology tools (<NUM>) configured to hold a metrology sample (<NUM>), wherein the controller includes one or more processors (<NUM>) configured to execute program instructions causing the one or more processors to:
receive one or more overlay metrology measurements of one or more metrology targets of the metrology sample from the one or more metrology tools, wherein the one or more overlay metrology measurements are taken following an after develop inspection (ADI) process;
determine tilt from the one or more overlay metrology measurements;
predict tilt with a simulator based on at least the determined tilt; and
determine one or more correctables for at least one of one or more lithography tools (<NUM>) or the one or more metrology tools to adjust for the predicted tilt, wherein the one or more correctables are configured to reduce an amount of tilt in the sample or overlay inaccuracy of the one or more overlay metrology measurements.