Patent Description:
The present invention generally relates to a clock and data recovery circuit.

A clock serial link receiver must operate to recover both the serially transmitted data and the clock without the assistance of an additional clock input provided by the serial link transmitter. A clock and data recovery (CDR) circuit is typically used. There are many known CDR circuits. These circuits suffer from at least the following concerns: the need to utilize a dedicated phase lock loop (PLL) circuit, a high complexity to implement oversampling, the presence of a feedback loop which introduces a bandwidth limitation, circuitry which occupies a large area and/or consumes a significant amount of power, and a lengthy time to achieve lock for the recovered clock.

Publication <CIT> discloses a circuit for detecting timing errors and for selecting the correct clock edge for mid-point data sampling, sampling an input data signal at a rising and falling edges and generating a first and second interim data signals, generating an error-rise or error-fall signal, outputting the first or second interim data signals to a logic device if the error-fall or error-rise signal is detected. Publication <CIT> discloses a data recovery circuit based on an oversampling technique wherein inter-symbol interference (ISI) is compensated by using a feedback signal that is applied to the decision circuit. Publication <NPL>: "Design and analysis of digital data recovery circuits using oversampling" and publication <CIT> both concerns clock and data recovery techniques.

There is a need in the art to develop a CDR circuit which addresses the foregoing concerns.

In an embodiment, a circuit comprises: a first sampling circuit configured to take a plurality of phase offset first samples of a received serial data stream in response to a first edge of a sampling clock; a second sampling circuit configured to take a plurality of phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, wherein the second edge is opposite the first edge; a first comparator circuit configured to determine whether the plurality of phase offset first samples have a same logic state; a second comparator circuit configured to determine whether the plurality of phase offset second samples have a same logic state; a first selection circuit configured to select one of the first samples or one of the second samples in response to the determinations made by the first and second comparator circuits; and a serial to parallel converter circuit configured to generate an output word including the selected one of the first and second samples.

In an embodiment, a method comprises: sampling a received serial data stream in response to a first edge of a sampling clock to obtain a plurality of phase offset first samples; sampling the received serial data stream in response to a second edge of the sampling clock, wherein the second edge is opposite the first edge, to obtain a plurality of phase offset second samples; determining whether the plurality of phase offset first samples have a same logic state; determining whether the plurality of phase offset second samples have a same logic state; first selecting one of the first samples or one of the second samples in response to results of the determining steps; and including the selected one of the first and second samples for a serial to parallel conversion to generate an output word.

For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:.

Reference is now made to <FIG> which show a block diagram of a clock and data recovery (CDR) circuit <NUM> within a receiver circuit <NUM>. An input <NUM> receives a serial bit stream (SSDATA) generated by a transmit circuit (not shown). The transitions between the high and low logic states in the serial bit stream, which represent the data being transmitted by the transmit circuit, are timed in phase with a transmit clock signal generated by the transmit circuit. However, that transmit clock signal is not itself transmitted to the receiver circuit <NUM>. This makes it difficult for the receiver circuit <NUM> to accurately extract the data from the serial bit stream. The CDR circuit <NUM> operates to extract the data <NUM> (DATA) from the serial bit stream and generate a clock signal (RX-CLK) <NUM> corresponding to the transmit circuit clock signal based on transitions of logic state of the received serial bit stream SSDATA. The CDR circuit <NUM> processes the received serial bit stream SSDATA including bits b0-bx (x indicating the index of the bits in the stream) to recover the transmit clock signal <NUM> and extract the bits for output as DATA <NUM> for use by the receiver circuit <NUM>.

A clock generator <NUM> of the receiver circuit <NUM> generates a sampling clock CLK and an inverter circuit <NUM> generates the logical inverse of the sampling clock (referred to as the inverse sampling clock CLKB). The frequency of the sampling clock is at least twice the data rate of the serial bit stream SSDATA.

A first sampling circuit <NUM> operates in response to the sampling clock CLK to take a first plurality of phase-shifted samples <NUM>(<NUM>)-<NUM>(<NUM>) of the received serial bit stream SSDATA during a first sampling window (reference <NUM> in <FIG>). The first sampling circuit <NUM> is actuated to take the samples <NUM> within the sampling window <NUM> in response to the rising edge (reference <NUM> in <FIG>) of the sampling clock CLK. These rising edge samples <NUM> are latched by a corresponding plurality of flip-flops <NUM> whose data inputs all receive the serial bit stream SSDATA and whose clock inputs receive phase-shifted sampling clock CLK signals which define the length of the first sampling window <NUM>. The phase-shifted sampling clock CLK signals are generated by serially-connected delay circuits D' in response to the sampling clock CLK.

A second sampling circuit <NUM> operates in response to the inverse sampling clock CLKB to take a second plurality of phase-shifted samples <NUM>(<NUM>)-<NUM>(<NUM>) of the received serial bit stream SSDATA during a second sampling window (reference <NUM> in <FIG>). The second sampling circuit <NUM> is actuated to take the samples <NUM> within the sampling window <NUM> in response to the rising edge of the inverse sampling clock CLKB (i.e., in response to the falling edge (reference <NUM> in <FIG>) of the sampling clock CLK). These falling edge samples <NUM> are latched by a corresponding plurality of flip-flops <NUM> whose data inputs all receive the serial bit stream SSDATA and whose clock inputs receive phase-shifted inverse sampling clock CLKB signals which define the length of the second sampling window <NUM>. The phase-shifted inverse sampling clock CLKB signals are generated by serially-connected delay circuits D' in response to the inverse sampling clock CLKB.

A first comparator circuit <NUM> receives the plurality of rising edge samples <NUM>(<NUM>)-<NUM>(<NUM>) from the first sampling window <NUM> as generated by the first sampling circuit <NUM> and performs a comparison of the logic state of the samples <NUM>. If all samples <NUM> within the first sampling window <NUM> have the same logic state, the first comparator circuit <NUM> asserts a first comparison output signal <NUM> to a logic "<NUM>" state. Conversely, if there is a detected change in logic state of the rising edge samples <NUM> within the sampling window <NUM>, the first comparison output signal <NUM> is set to logic "<NUM>".

A second comparator circuit <NUM> receives the plurality of falling edge samples <NUM>(<NUM>)-<NUM>(<NUM>) from the second sampling window <NUM> as generated by the second sampling circuit <NUM> and performs a comparison of the logic state of the samples <NUM>. If all samples <NUM> within the second sampling window <NUM> have the same logic state, the second comparator circuit <NUM> asserts a second comparison output signal <NUM> to logic "<NUM>". Conversely, if there is a change in logic state of the samples <NUM> within the sampling window <NUM>, the second comparison output signal <NUM> is set to logic "<NUM>".

A latch circuit <NUM> (formed by a D-type flip-flop) includes a data input configured to receive a logic "<NUM>" signal, a clock input configured to receive the first comparison output signal <NUM> and a reset input configured to receive the second comparison output signal <NUM>. The latch circuit <NUM> responds to a rising edge of the first comparison output signal <NUM> (caused by the comparison of the samples <NUM> within the first sampling window <NUM> finding that the samples <NUM> do not all have the same logic state) by latching the logic "<NUM>" signal and a data select signal <NUM> is output with a logic "<NUM>" state. The latch circuit <NUM> responds to the rising edge of the second comparison output signal <NUM> (caused by the comparison of the samples <NUM> within the second sampling window <NUM> finding that the samples <NUM> do not all have the same logic state) by resetting the latch so as to output the data select signal <NUM> with a logic "<NUM>" state.

The logic state of the data select signal <NUM> identifies which one of the first sampling circuit <NUM> or second sampling circuit <NUM> has captured a correct value of the received serial bit stream SSDATA. In this regard, if the data select signal <NUM> is logic "<NUM>", then this indicates that the first comparison output signal <NUM> is logic "<NUM>" and a data transition occurred during the first sampling window <NUM>. For this case, the second sampling circuit <NUM> has likely captured the correct value of the received serial bit stream SSDATA during the second sampling window <NUM> with falling edge sample <NUM>. Conversely, if the data select signal <NUM> is logic "<NUM>", then this indicates that the second comparison output signal <NUM> is logic "<NUM>" and a data transition occurred during the second sampling window <NUM>. For this case, the first sampling circuit <NUM> has likely captured the correct value of the received serial bit stream SSDATA during the first sampling window <NUM> with rising edge sample <NUM>.

A latch circuit <NUM> (formed by a flip-flop) includes a data input configured to receive one of the plurality of rising edge samples <NUM>(<NUM>)-<NUM>(<NUM>) and a clock input configured to receive the inverse sampling clock CLKB. In the illustrated implementation, the first sample <NUM>(<NUM>) is received, but it will be understood that any of the samples <NUM> could be used. Because the flip-flop <NUM> latches in response to the rising edge of the inverse sampling clock CLKB, the flip-flop is active in the half-phase of the clock CLK after the samples are taken by the sampling circuit <NUM> (i.e., when the sampling circuit <NUM> is operating to sample). The output from the latch circuit <NUM> is a signal which is a captured current rising edge sample of the serial bit stream SSDATA from the current first sampling window <NUM>. This captured current sample is considered to likely have the correct value of the received serial bit stream SSDATA if the data select signal <NUM> is logic "<NUM>" (due to the comparator <NUM> detecting a logic transition in the second sampling window <NUM>).

An additional latch circuit <NUM> (formed by a flip-flop) is coupled in series with the latch circuit <NUM> and clocked by the inverse sampling clock CLKB. The output of latch <NUM> is coupled to the data input of latch circuit <NUM>. The latch circuits <NUM>, <NUM> form a serial shift register that is clocked by the inverse sampling clock CLKB and configured to store two consecutive rising edge first samples <NUM>(<NUM>) (i.e., samples taken during the current and previous first sampling windows). This implementation with latch circuits <NUM>, <NUM> is needed to match latency with parallel processing of the sampled received serial bit stream SSDATA.

A latch circuit <NUM> (formed by a flip-flop) includes a data input configured to receive one of the plurality of falling edge samples <NUM>(<NUM>)-<NUM>(<NUM>) and a clock input configured to receive the inverse sampling clock CLKB. In the illustrated implementation, the first sample <NUM>(<NUM>) is received, but it will be understood that any of the samples <NUM> could be used. The flip-flop <NUM> latches in response to the rising edge of the inverse sampling clock CLKB (i.e., when the sampling circuit <NUM> is operating to sample). The output from the latch circuit <NUM> is a signal which is a captured current sample of the serial bit stream SSDATA from the current second sampling window <NUM>. This captured current sample is considered to likely have the correct value of the received serial bit stream SSDATA if the data select signal <NUM> is logic "<NUM>" (due to the comparator <NUM> detecting a logic transition in the first sampling window <NUM>).

Two additional latch circuits <NUM> and <NUM> (each formed by a flip-flop) are coupled in series with the latch circuit <NUM>. The output of latch <NUM> is coupled to the data input of latch circuit <NUM> and the output of latch circuit <NUM> is coupled to the input of latch circuit <NUM>. The latch circuits <NUM>, <NUM> and <NUM> form a serial shift register that is clocked by the inverse sampling clock CLKB and configured to store three consecutive falling edge first samples <NUM>(<NUM>) (i.e., samples taken during the current and previous two second sampling windows). This implementation with latch circuits <NUM>, <NUM>, <NUM> is needed to match latency with parallel processing of the sampled received serial bit stream SSDATA.

It will be noted that the shift register for storing first samples <NUM>(<NUM>) stores only two data samples while the shift register for storing first samples <NUM>(<NUM>) stores three data samples. This difference in size of the shift registers is necessary because data processing in the circuit <NUM> is occurring in response to the falling edge of the sampling clock CLK. The rising edge driven flip-flops <NUM> and <NUM> store two rising edge samples of the serial bit stream SSDATA and the falling edge driven flip-flops <NUM>, <NUM> and <NUM> store three falling edge samples of the serial bit stream SSDATA, where the two rising edge samples are interleaved between the three falling edge samples.

The preceding rising edge captured sample <NUM> of the serial bit stream SSDATA output from the latch circuit <NUM> for the first sampling window <NUM> is applied to a first input of a first multiplexer circuit <NUM>. A second input of the first multiplexer circuit <NUM> receives the current falling edge captured sample <NUM> of the serial bit stream SSDATA output from the latch circuit <NUM> for the second sampling window <NUM>. The select (control) input of the first multiplexer circuit <NUM> is coupled to receive the data select signal <NUM> output from the latch circuit <NUM>, and the multiplexer circuit <NUM> functions to selectively pass the sample <NUM> or <NUM> taken from the window <NUM> or <NUM>, respectively, which does not contain a detected logic transition.

When the data select signal <NUM> is logic "<NUM>", which occurs in response to the first comparison output signal <NUM> indicating comparator <NUM> detection of a transition in logic state of the plurality of rising edge samples <NUM>(<NUM>)-<NUM>(<NUM>) within the first sampling window <NUM>, the first multiplexer circuit <NUM> is controlled to select the current captured falling edge sample <NUM>(<NUM>) of the serial bit stream SSDATA as output <NUM> from the latch circuit <NUM> for the second sampling window <NUM> as a likely correct data sample. Conversely, when the data select signal <NUM> is logic "<NUM>", which occurs in response to the second comparison output signal <NUM> indicating comparator <NUM> detection of a transition in logic state of the plurality of falling edge samples <NUM>(<NUM>)-<NUM>(<NUM>) within the second sampling window <NUM>, the first multiplexer circuit <NUM> is controlled to select the previous captured rising edge sample <NUM>(<NUM>) of the serial bit stream SSDATA from the first sampling window <NUM> as output <NUM> from the latch circuit <NUM> as a likely correct data sample.

A combinational logic circuit <NUM> receives: the first comparison output signal <NUM>, the second comparison output signal <NUM>, the preceding rising edge sample <NUM> of the serial bit stream SSDATA as output from the latch circuit <NUM>, and the current falling edge sample <NUM> of the serial bit stream SSDATA as output from the latch circuit <NUM>. The combinational logic circuit <NUM> includes a logical AND gate <NUM> having a first input receiving the first comparison output signal <NUM> and a second input receiving the second comparison output signal <NUM>. A first signal <NUM> output from the logical AND gate <NUM> is logic "<NUM>" only if the first comparison output signal <NUM> and the second comparison output signal <NUM> are both logic "<NUM>". This occurs only when the first comparator circuit <NUM> determines that the samples <NUM> within the first sampling window have different logic states and the second comparator circuit <NUM> determines that the samples <NUM> within the second sampling window also have different logic states. The logic "<NUM>" output of the AND gate <NUM> accordingly indicates detection of the operating scenario <NUM>) referenced below where the serial data SSDATA changes state during both the first sampling window <NUM> and the second sampling window <NUM>.

A logical NOR gate <NUM> has a first input receiving the first comparison output signal <NUM> and a second input receiving the second comparison output signal <NUM>. The output of the logical NOR gate <NUM> is logic "<NUM>" only if the first comparison output signal <NUM> and the second comparison output signal <NUM> are both logic "<NUM>". This occurs only when the first comparator circuit <NUM> determines that all rising edge samples <NUM> within the first sampling window have a same logic state and the second comparator circuit <NUM> determines that all falling edge samples <NUM> within the second sampling window have a same logic state. The logic "<NUM>" output of the NOR gate <NUM> accordingly indicates detection of the operating condition where there is no change of serial data SSDATA state during both the first sampling window <NUM> and the second sampling window <NUM>.

The combinational logic circuit <NUM> further includes a logical exclusive-OR gate <NUM> having a first input receiving the preceding captured rising edge sample <NUM> of the serial bit stream SSDATA as output from the latch circuit <NUM> for the first sampling window <NUM> and a second input receiving the current captured falling edge sample <NUM> of the serial bit stream SSDATA as output from the latch circuit <NUM> for the second sampling window <NUM>. The output of the logical exclusive-OR gate <NUM> is logic "<NUM>" when the previous captured sample from the first sampling window and the current captured sample during the second sampling window have different logic states. Otherwise, the output of the logical exclusive-OR gate <NUM> is logic "<NUM>". The logic "<NUM>" output of the XOR gate <NUM> accordingly indicates detection of the operating condition where the samples <NUM>(<NUM>) and <NUM>(<NUM>) have different logic states.

A logical AND gate <NUM> within the combinational logic circuit <NUM> receives the outputs of the logical NOR gate <NUM> and logical exclusive-OR gate <NUM> to generate a second signal <NUM>. The second signal <NUM> is logic "<NUM>" only if output of the logical NOR gate <NUM> is logic "<NUM>" and the output of the logical exclusive-OR gate <NUM> is logic "<NUM>". Otherwise, the output of the logical AND gate <NUM> is logic "<NUM>". The logic "<NUM>" output of the AND gate <NUM> accordingly indicates detection of the operating scenario <NUM>) referenced below where the serial data SSDATA does not change state in either the first sampling window <NUM> or the second sampling window <NUM> (as detected by NOR gate <NUM>) and the logic state of the samples is different in each window (as detected by XOR gate <NUM>).

The combinational logic circuit <NUM> further includes a logical OR gate <NUM> having a first input receiving the first signal <NUM> and a second input receiving the second signal <NUM>. The output of the logical OR gate <NUM> is a flag signal <NUM>. The flag signal <NUM> output by the logical OR gate <NUM> is logic "<NUM>" only if one of the first signal <NUM> or second signal <NUM> is logic "<NUM>". Otherwise, the output of the logical OR gate <NUM> is logic "<NUM>". Thus, the flag signal <NUM> is logic "<NUM>" whenever the operating scenario <NUM>) or the operating scenario <NUM>) has been detected.

The flag signal <NUM> is latched by a latch circuit <NUM> (formed by a flip-flop) that includes a data input configured to receive the flag signal <NUM> and a clock input configured to receive the inverse clock signal CLKB. The latch circuit <NUM> outputs a latched flag signal <NUM>. The latched flag signal <NUM> has a logic state which follows the flag signal <NUM>. To be clear, the latched flag signal <NUM> is logic "<NUM>" in two conditions. A first condition is when the first comparison output signal <NUM> and the second comparison output signal <NUM> are both logic "<NUM>" and the preceding rising edge sample <NUM> of the serial bit stream SSDATA as output from the latch circuit <NUM> and the current falling edge sample <NUM> of the serial bit stream SSDATA as output from the latch circuit <NUM> have opposite logic states. The logic "<NUM>" value of the latched flag signal <NUM> in this case is accordingly indicative of detection of the operating scenario <NUM>) referenced below where the serial data SSDATA does not change state in either the first sampling window <NUM> or the second sampling window <NUM>, but the logic state of the samples is different in each window. The latched flag signal <NUM> is also logic "<NUM>" in a second condition when the first comparison output signal <NUM> and the second comparison output signal <NUM> are both logic "<NUM>". The logic "<NUM>" value of the latched flag signal <NUM> in this case is accordingly indicative of detection of the operating scenario <NUM>) referenced below where the serial data SSDATA changes state during both the first sampling window <NUM> and the second sampling window <NUM>.

The selected captured sample of the serial bit stream SSDATA output from multiplexer <NUM> is received at a first input of a second multiplexer circuit <NUM>. A second input of the second multiplexer circuit <NUM> receives a feedback signal <NUM> that is generated by a latching inverter circuit <NUM>. Circuit <NUM> includes a latch circuit <NUM> (formed by a flip-flop) that includes a data input configured to receive the output of the second multiplexer circuit <NUM>. The latch circuit <NUM> is clocked by the inverse sampling clock CLKB. An output of the latch circuit <NUM> is passed through a logical inverter <NUM> to generate the feedback signal <NUM>. It will accordingly be understood that the feedback signal <NUM> is a logical inversion of the immediately preceding output of the second multiplexer circuit <NUM> as stored by latch circuit <NUM>.

The logic state of the latched flag signal <NUM> controls whether the second multiplexer circuit <NUM> operates to pass the selected sample of the serial bit stream SSDATA output from multiplexer <NUM> or instead pass the feedback signal <NUM> (which is the logical inversion of the immediately preceding output of the second multiplexer circuit <NUM> as stored by latch circuit <NUM>). The signal passed by the second multiplexer circuit <NUM> in response to the latched flag signal <NUM> is then latched by latch circuit <NUM> at the rising edge of the inverse sampling clock CLKB and output as a correctly detected bit of the serial stream SSDATA during one cycle of the clock CLK. The logic "<NUM>" value of the latched flag signal <NUM> is indicative of the situation where the current data sample may not be correct, but where the correct logic state must be the opposite logic state of the previous data sample. The opposite logic state value is provided by the latching inverter circuit <NUM> and passed through the multiplexer circuit <NUM> in response to assertion logic high of the latched flag signal <NUM>. Otherwise, the logic "<NUM>" value of the latched flag signal <NUM> is indicative of the situation where the current data sample from multiplexer <NUM> is correct.

A serial input parallel output (SIPO) circuit <NUM> receives the previous two captured falling edge samples of the first sample <NUM>(<NUM>) taken during the previous two second sampling windows as output from the latch circuits <NUM>, <NUM> of the serial shift register and the detected bit provided by the signal passed by the second multiplexer circuit <NUM> in response to the latched flag signal <NUM>. From these signals, the SIPO circuit <NUM> performs a serial to parallel conversion in response to the inverse sampling clock CLKB to output an N bit data word as the DATA <NUM> recovered from the serial bit stream SSDATA over a multi-bit data bus for further processing by the receiver circuit <NUM>. The SIPO circuit <NUM> is clocked by the inverse sampling clock CLKB. The N bit data word for the output DATA <NUM> is generated by the SIPO circuit <NUM> from the last N received bit values output from the latches <NUM>, <NUM> and <NUM> (where the data from latches <NUM> and <NUM> is selectively used in constructing the N bit data word as needed to address concerns with accumulated jitter).

The CDR circuit <NUM> operates to identify the following scenarios:.

<NUM>) the serial data SSDATA changes logic state during sampling window <NUM> and is stable during sampling window <NUM> (<FIG>, window <NUM> is shown and window <NUM> is not shown), or vice versa;.

<NUM>) the serial data SSDATA does not change state in either the first sampling window <NUM> or the second sampling window <NUM>, but the logic state of the samples is different in each window (<FIG>);.

<NUM>) the serial data SSDATA changes state during both the first sampling window <NUM> and the second sampling window <NUM> (<FIG>); and.

<NUM>) the serial data SSDATA does not change state during either the first sampling window <NUM> or the second sampling window <NUM>, and the logic state of the samples is the same in both windows (<FIG>).

With respect to scenario <NUM>), this is detected using the first and second sampling circuits <NUM>, <NUM> and the first and second comparator circuits <NUM>, <NUM>. If the samples <NUM>, <NUM> do not all have the same logic value, then there was a logic state change during the sampling window. In this scenario, one of the signals <NUM> or <NUM> will be logic "<NUM>" and the other of the signals <NUM> or <NUM> will be logic "<NUM>". In response to this condition, the control signal <NUM> causes the multiplexer <NUM> to select the latched sample <NUM> or <NUM> taken from the sampling window where no change in logic state was detected, and logic circuit <NUM> will deassert the latched flag signal <NUM> at logic "<NUM>". In response, the multiplexer <NUM> will pass the selected correct sample to be latched by circuit <NUM> and supplied as the detected bit to the SIPO circuit <NUM> for use in generating one bit of the N bit data word for output DATA <NUM>.

The scenario <NUM>) case is illustrated in <FIG> with sampling window <NUM> and the plurality of samples <NUM>(<NUM>)-<NUM>(<NUM>), where sampling window <NUM> is not explicitly shown, but it will be understood that the samples <NUM> in window <NUM> all have the same logic state. The signal <NUM> will be logic "<NUM>" (due to detection of the change of logic state for SSDATA in window <NUM>) and the signal <NUM> will be logic "<NUM>" (due to detection of no change of logic state for SSDATA in window <NUM>). The sample <NUM>(<NUM>) will be logic "<NUM>" and the sample <NUM>(<NUM>) will be logic "<NUM>". In response to the transition of signal <NUM> to logic "<NUM>", the latch <NUM> is set and the data select signal <NUM> will be logic "<NUM>". As a result, the first multiplexer <NUM> will select to pass the sample <NUM>(<NUM>) at logic "<NUM>" as the correct value to the second multiplexer <NUM>. The logic circuit <NUM> will output a logic "<NUM>" for signal <NUM> which is latched by latch <NUM>. The second multiplexer <NUM> is then controlled to pass the correct sample <NUM>(<NUM>) at logic "<NUM>" to the SIPO circuit <NUM> for use as one bit of the N bit word for the output DATA <NUM>.

With respect to scenario <NUM>), this is detected using the first and second sampling circuits <NUM>, <NUM> and the first and second comparator circuits <NUM>, <NUM>. If all the samples <NUM> have the same first value, all the samples <NUM> have the same second value, and the first and second values are different, then there was a logic state change between sampling windows. In this scenario, both of the signals <NUM> and <NUM> will be logic low and the samples <NUM> and <NUM> will have opposite logic states. The logic state of the control signal <NUM> in this scenario is not relevant because selection by the multiplexer <NUM> will be trumped by the selection made by the multiplexer <NUM> in response to the latched flag signal <NUM>. The logic circuit <NUM> will assert the latched flag signal <NUM> at logic "<NUM>" because signal <NUM> from AND gate <NUM> is logic "<NUM>". In response, the multiplexer <NUM> will operate to pass the logical inversion of the immediately preceding output of the second multiplexer circuit <NUM> as stored by latch circuit <NUM>, with the inverted data latched by circuit <NUM> and supplied to the SIPO circuit <NUM> as the detected bit for use in generating one bit of the output DATA <NUM>.

The scenario <NUM>) case is illustrated in <FIG> with sampling window <NUM> and the plurality of samples <NUM>(<NUM>)-<NUM>(<NUM>) and sampling window <NUM> and the plurality of samples <NUM>(<NUM>)-<NUM>(<NUM>). The signal <NUM> will be logic "<NUM>" (due to detection of no change of logic state for SSDATA in window <NUM>) and the signal <NUM> will be logic "<NUM>" (due to detection of no change of logic state for SSDATA in window <NUM>). The sample <NUM>(<NUM>) will be logic "<NUM>" and the sample <NUM>(<NUM>) will be logic "<NUM>". Because there is no transition of signal <NUM> or signal <NUM> to logic "<NUM>", the latch <NUM> remains in the set or reset state it was previously in. In any event, this is a "don't care" scenario with respect signal <NUM> and the operation of multiplexer <NUM>. What is known in this case is that whichever of the samples that could be selected by the first multiplexer <NUM>, the logic state of that sample may be incorrect, but the correct value for the sample is going to be the logical inverse of the previous value of the sample stored by the latch <NUM>. The logic circuit <NUM> will output a logic "<NUM>" for signal <NUM> which is latched by latch <NUM>. The second multiplexer <NUM> is then controlled to pass the logical inverse of the previous stored value through to latch <NUM> for output to the SIPO <NUM> for use as one bit of the N bit word for the output DATA <NUM>.

With respect to scenario <NUM>), this is detected using the first and second sampling circuits <NUM>, <NUM> and the first and second comparator circuits <NUM>, <NUM>. If the samples <NUM> do not have the same first value, and the samples <NUM> do not have the same second value, then there was a logic state change in each sampling window and signals <NUM> and <NUM> will both be logic "<NUM>". The logic state of the control signal <NUM> in this scenario is not relevant because selection by the multiplexer <NUM> will be trumped by the selection made by the multiplexer <NUM> in response to the latched flag signal <NUM>. The logic circuit <NUM> will assert the latched flag signal <NUM> at logic "<NUM>" because signal <NUM> from AND gate <NUM> is logic "<NUM>". In response, the multiplexer <NUM> will operate to pass the logical inversion of the immediately preceding output of the second multiplexer circuit <NUM> as stored by latch circuit <NUM>, with the inverted data latched by circuit <NUM> and supplied to the SIPO circuit <NUM> as the detected bit for use in generating one bit of the output DATA <NUM>.

The scenario <NUM>) case is illustrated in <FIG> with sampling window <NUM> and the plurality of samples <NUM>(<NUM>)-<NUM>(<NUM>) and sampling window <NUM> and the plurality of samples <NUM>(<NUM>)-<NUM>(<NUM>). The signal <NUM> will be logic "<NUM>" (due to detection of the change of logic state for SSDATA in window <NUM>) and the signal <NUM> will be logic "<NUM>" (due to detection of the change of logic state for SSDATA in window <NUM>). The sample <NUM>(<NUM>) will be logic "<NUM>" and the sample <NUM>(<NUM>) will be logic "<NUM>". This is a "don't care" scenario with respect signal <NUM> and the operation of multiplexer <NUM>. What is known in this case is that whichever of the samples that could be selected by the first multiplexer <NUM>, the logic state of that sample may be incorrect, but the correct value for the sample is going to be the logical inverse of the previous value of the sample stored by the latch <NUM>. The logic circuit <NUM> will output a logic "<NUM>" for signal <NUM> which is latched by latch <NUM>. The second multiplexer <NUM> is then controlled to pass the logical inverse of the previous stored value through to latch <NUM> for output to the SIPO <NUM> for use as one bit of the N bit word for the output DATA <NUM>.

With respect to scenario <NUM>), this is detected using the first and second sampling circuits <NUM>, <NUM> and the first and second comparator circuits <NUM>, <NUM>. If the samples <NUM> have the same first value, and the samples <NUM> have the same first value, then there was no logic state change during consecutive sampling windows. In this scenario, both of the signals <NUM> or <NUM> will be logic "<NUM>". In response to this condition, there is no change in the logic state of the control signal <NUM> and the multiplexer <NUM> will continue with selection of the correct value for output, and the logic circuit <NUM> will deassert the latched flag signal <NUM> at logic "<NUM>". In response, the multiplexer <NUM> will pass the selected correct sample to be latched by circuit <NUM> and supplied to the SIPO circuit <NUM> as the detected bit for use in generating one bit of the N bit data word for output DATA <NUM>.

The scenario <NUM>) case is illustrated in <FIG> with sampling window <NUM> and the plurality of samples <NUM>(<NUM>)-<NUM>(<NUM>) and sampling window <NUM> and the plurality of samples <NUM>(<NUM>)-<NUM>(<NUM>). The signal <NUM> will be logic "<NUM>" (due to detection of no change of logic state for SSDATA in window <NUM>) and the signal <NUM> will be logic "<NUM>" (due to detection of no change of logic state for SSDATA in window <NUM>). The sample <NUM>(<NUM>) will be logic "<NUM>" and the sample <NUM>(<NUM>) will be logic "<NUM>". Because there is no transition of signal <NUM> or signal <NUM> to logic "<NUM>", the latch <NUM> remains in the set or reset state it was previously in, with no change in the logic state of the data select signal <NUM>. As a result, the first multiplexer <NUM> will select to pass one of sample <NUM>(<NUM>) at logic "<NUM>" or sample <NUM>(<NUM>) at logic "<NUM>" as the correct value to the second multiplexer <NUM>. The logic circuit <NUM> will output a logic "<NUM>" for signal <NUM> which is latched by latch <NUM>. The second multiplexer <NUM> is then controlled to pass the correct sample <NUM>(<NUM>) at logic "<NUM>" to the SIPO circuit <NUM> for use as one bit of the N bit word for the output DATA <NUM>.

A control circuit <NUM> receives the latched flag <NUM>, a control signal <NUM>, the first comparison output signal <NUM>, the second comparison output signal <NUM>, and the data select signal <NUM>. In operation, the control circuit historically tracks the logic states of the flag <NUM>, the data select signal <NUM> and the signals <NUM> and <NUM>. By monitoring the current and previous logic states of these signals through the stored historical data, the control circuit <NUM> can detect an accumulated jitter condition of the transmit clock from the tracked locations of detected logic transitions in the serial data SSDATA.

For example, the historical data for the logic states of the flag <NUM>, the data select signal <NUM> and the signals <NUM> and <NUM> may show: a transition of the serial data SSDATA within the first sampling window <NUM>, followed by a transition of the serial data SSDATA between sampling windows <NUM> and <NUM>, followed by a transition of the data SSDATA within the second sampling window <NUM>, followed by a transition of the serial data SSDATA between sampling windows <NUM> and <NUM>, followed by a transition of the serial data SSDATA within the first sampling window <NUM>. In this scenario, the control circuit <NUM> will detect existence of jitter of the transmit clock due to the fact that a greater number of bits of the serial data SSDATA being received within a receive window defined by the clock CLKB. In this case of a detected jitter condition, the control circuit <NUM> must control the operation of the SIPO circuit <NUM> to output the N bit word for the output DATA <NUM> over a fewer number of cycles of the clock CLKB and adjust the recovered clock RX-CLK accordingly. The control circuit <NUM> asserts control signal <NUM> to cause a counter circuit <NUM> which is counting cycles of the clock CLKB to advance its count value by one. As a result, the SIPO circuit <NUM> will output the N bit word for the output DATA <NUM> over N-<NUM> cycles of the clock CLKB by using N-<NUM> bits output from the latch <NUM> and an Nth bit output from latch <NUM> or latch <NUM>. The control signal <NUM> is asserted logic high in response to detection of the following operating condition: signal <NUM> transitions from logic "<NUM>" to logic "<NUM>" and flag <NUM> was logic "<NUM>" at the time of a last occurrence of signal <NUM> transitioning to logic "<NUM>".

Conversely, the historical data for the logic states of the flag <NUM>, the data select signal <NUM> and the signals <NUM> and <NUM> may show: a transition of the serial data SSDATA within the first sampling window <NUM>, followed by a transition of the serial data SSDATA between sampling windows <NUM> and <NUM>, followed by a transition of the data SSDATA within the second sampling window <NUM>, followed by a transition of the serial data SSDATA between sampling windows <NUM> and <NUM>, followed by a transition of the serial data SSDATA within the first sampling window <NUM>. In this scenario, the control circuit <NUM> will detect existence of jitter of the transmit clock and that a lesser number of bits are being received within a receive window defined by the clock CLKB. In this case of a detected jitter condition, the control circuit <NUM> must control the operation of the SIPO circuit <NUM> to output the N bit word for the output DATA <NUM> over a greater number of cycles of the clock CLK and adjust the recovered clock RX-CLK accordingly. The control circuit <NUM> asserts control signal <NUM> to cause a counter circuit <NUM> which is counting cycles of the clock CLKB to hold its count value for one clock cycle. As a result, the SIPO circuit <NUM> will output the N bit word for the output DATA <NUM> over N+<NUM> cycles of the clock CLKB by using N bits output from the latch <NUM>. The control signal <NUM> is asserted logic high in response to detection of the following operating condition: signal <NUM> transitions from logic "<NUM>" to logic "<NUM>" and flag <NUM> was logic "<NUM>" at the time of a last occurrence of signal <NUM> transitioning to logic "<NUM>".

The bit counter <NUM> generates a control signal <NUM> in response to the current count value. The signal <NUM> has a first logic state if the count value is less than N, and the SIPO circuit <NUM> responds to the first logic state of signal <NUM> by continuing to shift data bits output from latch <NUM> in response to clock CLKB to form the N bit data word for the DATA output <NUM>. The signal <NUM> has a second logic state if the count value equals N, and the SIPO circuit <NUM> responds to the second logic state of signal <NUM> by outputting the N bit data word for the DATA output <NUM>.

The control signal <NUM> is also received by the SIPO circuit <NUM>. As noted above, the assertion of the control signal <NUM> is made in response to detection of the jitter condition. In this case, the bit counter <NUM> will advance its count by one and thus there will be only N-<NUM> cycles of the clock CLKB for generating N bits of the DATA output <NUM>. The assertion of the signal <NUM> informs the SIPO circuit <NUM> of this case, and the SIPO responds by ensuring that N bits have been shifted in to produce the DATA output <NUM> in response to the second logic state of the signal <NUM>. In this case, the SIPO circuit <NUM> uses the last N-<NUM> bits output from the latch <NUM> plus two additional bits (i.e., the Nth bit and N-1th bit) from latch <NUM> or latch <NUM> to produce the required N bits for the DATA output. In a corner case operating condition, where the signal <NUM> is asserted during the counting of the Nth bit, there is no room left in the data word for adding bits. So, the bit from latch <NUM> is used as the first bit in the next data word and the bit from latch <NUM> is used as the second bit of that data word.

The control signal <NUM> is also received by the SIPO circuit <NUM>. As noted above, the assertion of the control signal <NUM> is made in response to detection of the jitter condition. In this case, the bit counter <NUM> will hold its count by one and thus there will be N+<NUM> cycles of the clock CLKB for N bits of the DATA output <NUM>. The assertion of the signal <NUM> informs the SIPO circuit <NUM> of this case, and the SIPO responds by ensuring that N bits have been shifted in from the latch <NUM> to produce the DATA output <NUM> in response to the second logic state of the signal <NUM>.

<FIG> shows the relationship between the sampling clock CLK, the SIPO output of the recovered DATA and the recovered clock RX-CLK in a scenario where the detected accumulated jitter is within a certain limit. In this scenario, the control circuit <NUM> has determined from the historical data for the logic states of the flag <NUM>, the data select signal <NUM> and the signals <NUM> and <NUM> that the jitter is within the acceptable tolerance. The control signals <NUM> and <NUM> are not asserted and the bit counter <NUM> counts N cycles of the clock CLKB to control the SIPO circuit <NUM> through signal <NUM> to collect N consecutive detected data bits from the data samples output by the latch <NUM> over N cycles of the clock CLKB to generate the N bit data word for the DATA output <NUM> and the control circuit <NUM> generates one clock cycle of the recovered clock RX-CLK <NUM>.

<FIG> shows the relationship between the sampling clock CLK, the SIPO output of the recovered DATA and the recovered clock RX-CLK in a scenario where the detected accumulated jitter exceeds the certain limit (due to the sampling clock having a frequency that is lower (i.e., higher period) than the transmit clock). In this scenario, the control circuit <NUM> has determined from the historical data for the logic states of the flag <NUM>, the data select signal <NUM> and the signals <NUM> and <NUM> that the jitter is not within the acceptable tolerance (because the clock period is smaller than the ideal period). The control signal <NUM> is asserted (and control signal <NUM> is not asserted) and the value of the bit counter <NUM> is advanced by one. As a result, the bit counter <NUM> will count N-<NUM> cycles of the clock CLKB to control the SIPO circuit <NUM> through signal <NUM> to collect N-<NUM> data bits from the data samples output by the latch <NUM> and an Nth bit output from the latch <NUM> or latch <NUM> over N-<NUM> cycles of the clock CLKB to generate the N bit data word for the DATA output <NUM> and one clock cycle of the recovered clock RX-CLK <NUM>. It is important to note here that the data bit represented by the sample stored in the latch <NUM>, <NUM> is needed to perform a bit stuffing providing the N-th bit of the data word, the first through N-1th bits being obtained from latch <NUM>.

With respect to the previously noted corner case in the context of the <FIG> jitter scenario: the control circuit <NUM> receives a signal <NUM> from the bit counter <NUM> which indicates the current bit count. If the control signal <NUM> is asserted during the N-th bit of the SIPO circuit <NUM> operation to generate the data word (i.e., at the Nth count value), then there is not an option to perform bit stuffing in the current frame because the SIPO has already shifted in the required N bits from the latch <NUM>. In this case, the extra data bit must be stuffed into the subsequent data word (i.e., the next frame) of the DATA output. The first bit of the next frame is then stuffed by the SIPO circuit <NUM> with the data value stored in the latch <NUM> and the second bit comes from latch <NUM>.

<FIG> shows the relationship between the sampling clock CLK, the SIPO output of the recovered DATA and the recovered clock RX-CLK in a scenario where the accumulated jitter exceeds the limit (due to the sampling clock having a frequency that is higher (lower period) than the transmit clock). In this scenario, the control circuit <NUM> has determined from the historical data for the logic states of the flag <NUM>, the data select signal <NUM> and the signals <NUM> and <NUM> that the jitter is not within the acceptable tolerance (the clock period is greater than the ideal period). The control signal <NUM> is asserted (control signal <NUM> is not asserted) and the value of the bit counter <NUM> is held by one clock cycle. As a result, the bit counter <NUM> will count N+<NUM> cycles of the clock CLKB to control the SIPO circuit <NUM> through signal <NUM> to collect N data bits from the data samples output by the latch <NUM> over N+<NUM> cycles of the clock CLKB to generate the N bit data word for the DATA output <NUM> and one clock cycle of the recovered clock RX-CLK <NUM>.

The control circuit <NUM> further generates the recovered clock signal RX-CLK <NUM> for further processing by the receiver circuit <NUM>. The recovered clock signal RX-CLK <NUM> is generated as a function of the clock CLKB and the operation to trigger the SIPO circuit <NUM> to generate the N bit data word for the DATA output <NUM>. There will be one cycle of the recovered clock signal RX-CLK <NUM> generated for each data word output as shown in <FIG>. The period of the recovered clock signal RX-CLK <NUM> is shrunk to N-<NUM> cycles of the clock CLKB in response to assertion of signal <NUM> and is stretched to N+<NUM> cycles of the clock CLKB in response to assertion of the signal <NUM>.

Claim 1:
A circuit (<NUM>), comprising:
a first sampling circuit (<NUM>) configured to take a plurality of phase offset first samples of a received serial data stream in response to a first edge of a sampling clock (CLK);
a second sampling circuit (<NUM>) configured to take a plurality of phase offset second samples of the received serial data stream in response to a second edge of the sampling clock (CLK), wherein the second edge is opposite the first edge;
a first comparator circuit (<NUM>) configured to determine whether the plurality of phase offset first samples have a same logic state;
a second comparator circuit (<NUM>) configured to determine whether the plurality of phase offset second samples have a same logic state;
characterized in that the circuit (<NUM>) comprises:
a first selection circuit (<NUM>) configured to select one of the first samples or one of the second samples in response to the determinations made by the first and second comparator circuits; and
a serial to parallel converter circuit (<NUM>) configured to generate an output word including the selected one of the first and second samples.