Patent Description:
Semiconductor devices such as insulated gate power transistor devices, e.g., power MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors), are widely used as electronic switches in various types of electronic applications. In many applications such as high current applications, for example, a current through the semiconductor device is measured. Such current measurements are often performed by determining a voltage over an external shunt resistor. Such an external resistance, however, adds to the overall losses of the arrangement and may reduce the efficiency.

Document <CIT> discloses a semiconductor device comprising a semiconductor portion including first semiconductor layers of a first conduction type and second semiconductor layers of a second conduction type alternately arranged on the surface of a semiconductor substrate to form a striped shape. A main region is formed to arrange a main cell in a well. A current sense cell is arranged in a sense well. A sense region is formed having the direction of the length in a direction that intersects the direction of alternate arrangement of the first semiconductor layers and the second semiconductor layers.

Document <CIT> discloses a semiconductor apparatus including a power MOSFET including a main MOSFET and sensing MOSFET's. The main MOSFET and the sensing MOSFET's are formed on a semiconductor substrate, and a sensing MOSFET is selected for changing the sensing ratio and further for confining the sensing ratio variations within a certain narrow range stably from a low main current range to a high main current range.

Document <CIT> discloses a current detecting cell of a MOS-type semiconductor device with a current detection function, wherein the area of the contact portions of source regions which contact a current detecting electrode is greater than that of that contact portion of a base region which contacts the current detecting electrode.

Document <CIT> discloses a method including partly removing a supporting layer arranged between a first semiconductor layer and a second semiconductor layer using an etching process to form at least one undercut between the first semiconductor layer and the second semiconductor layer, at least partly filling the at least one undercut with a first material having a higher thermal conductivity than the supporting layer, and forming a sensor device in or on the second semiconductor layer.

It is desirable to provide a semiconductor device comprising a current detection element that has low losses and may be operated effectively.

One example relates to a semiconductor device. The semiconductor device includes a semiconductor body including a first surface, a second surface opposite to the first surface in a vertical direction, an active region, and a sensor region arranged adjacent to the active region in a first horizontal direction. The semiconductor device further includes a plurality of transistor cells at least partly integrated in the active region, each transistor cell including a source region, a body region, a drift region separated from the source region by the body region, and a gate electrode dielectrically insulated from the body region. The semiconductor device further includes at least one sensor cell at least partly integrated in the sensor region, each of the at least one sensor cell comprising a source region, a body region, a drift region separated from the source region by the body region, and a gate electrode dielectrically insulated from the body region. The semiconductor device further includes a plurality of first contact plugs, an intermediate layer, and a second contact plug. The source regions of the plurality of transistor cells are coupled to a first source electrode, and the source regions of the at least one sensor cell are coupled to a second source electrode separate and distant from the first source electrode. At least one of the plurality of transistor cells directly adjoins one of the at least one sensor cells. Each of the plurality of first contact plugs extends between one of the source regions of the at least one sensor cell and the intermediate layer, and provides an electrical connection between the respective source region and the intermediate layer, and the second contact plug extends between the intermediate layer and the second source electrode, and provides an electrical connection between the intermediate layer and the second source electrode.

Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so that only aspects necessary for understanding these principles are illustrated. In the drawings the same reference characters denote like features.

<FIG> schematically illustrates a cross sectional view of a semiconductor device according to another example.

It is noted that only <FIG> show examples falling within the scope of the present invention, while the examples of <FIG> do not form part of the claimed invention but are useful to understand it.

In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and for the purpose of illustration show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

Referring to <FIG>, a cross-sectional view of a semiconductor device comprising a semiconductor body <NUM> is schematically illustrated. The semiconductor body <NUM> may include a conventional semiconductor material such as, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like. A transistor device is formed in the semiconductor body <NUM>, the transistor device being arranged in an active region <NUM> of the semiconductor body <NUM>. In <FIG>, only a small section of the transistor device is shown. In its active region <NUM>, the semiconductor body <NUM> includes at least one working transistor cell <NUM> with a gate electrode <NUM> that is dielectrically insulated from a body region <NUM> by a gate dielectric <NUM>. The body region <NUM> is a doped semiconductor region in the active region <NUM> of the semiconductor body <NUM>. In the example illustrated in <FIG>, the body region <NUM> extends from a first surface <NUM> into the semiconductor body <NUM>, and the gate electrode <NUM> is arranged above the first surface <NUM> of the semiconductor body <NUM>. Each of the transistor cells <NUM> further includes at least one source region <NUM> extending from the first surface <NUM> into the body region <NUM>.

The transistor device illustrated in <FIG> further includes a drift region <NUM> formed in the semiconductor body <NUM>. The drift region <NUM> adjoins the body region <NUM> of the at least one transistor cell <NUM> and forms a pn-junction with the body region <NUM>. The drift region <NUM> is arranged between the body region <NUM> of the at least one transistor cell <NUM> and a semiconductor layer <NUM>. The semiconductor layer <NUM> is arranged between a second surface <NUM> of the semiconductor body <NUM> and the drift region <NUM>. The second surface <NUM> is arranged opposite to the first surface <NUM> in a vertical direction y of the semiconductor body <NUM>.

The semiconductor layer <NUM> comprises a drain region <NUM> of the same doping type as the drift region <NUM> and adjoining the second surface <NUM>. Optionally, a vertical field-stop-region (not specifically illustrated in <FIG>) of the same doping type as the drift region <NUM> and the drain region <NUM>, but less highly doped than the drain region <NUM>, may be arranged between the drift region <NUM> and the drain region <NUM>. That is, the semiconductor layer <NUM> may be formed by the drain region <NUM> and the adjoining vertical field-stop-region. Such a vertical field-stop-region may be formed by a single layer or by a plurality of separate sub-layers, e.g., at least two sub-layers. Sub-layers that are arranged closer to the drift region <NUM> may be less highly doped than sub-layers that are arranged further away from the drift region <NUM>. For example, a doping concentration of a sub-layer that is arranged adjacent to the drift region <NUM> may be selected from a range of between 1E15 and 1E16 cm-<NUM> or lower. A doping concentration of a sub-layer that is arranged adjacent to the drain region <NUM> may be higher than a doping concentration of a sub-layer that is arranged horizontally above. The doping concentration of the sub-layer that is arranged adjacent to the drain region <NUM>, however, may be lower than a doping concentration of the drain region <NUM>. Generally speaking, a doping concentration of the different sub-layers may increase from the drift region <NUM> towards the drain region <NUM>.

Still referring to <FIG>, the transistor device includes at least one vertical compensation region <NUM> of a doping type complementary to the doping type of the drift region <NUM>. According to one example, the transistor device includes a plurality of transistor cells <NUM> and each transistor cell <NUM> includes a vertical compensation region <NUM> adjoining the body region <NUM> of the respective transistor cell <NUM>. In a vertical direction y of the semiconductor body <NUM>, which is a direction perpendicular to the first surface <NUM> and to the second surface <NUM>, the at least one vertical compensation region <NUM> extends from the body region <NUM> into the semiconductor body <NUM> towards the semiconductor layer <NUM>.

Still referring to <FIG>, the transistor device further includes a first source electrode <NUM>. The first source electrode <NUM> is electrically connected to the source region <NUM> and the body region <NUM> of the at least one transistor cell <NUM> by means of contact plugs <NUM>. The contact plugs <NUM> may comprise at least one of polysilicon, tungsten, aluminum, copper, and a Ti/TiN barrier liner, for example. This first source electrode <NUM> forms a source node S or is electrically connected to a source node S of the transistor device. The transistor device further includes a drain node D electrically connected to the drain region <NUM>. A drain electrode electrically connected to the drain region <NUM> may form the drain node D.

The transistor device can be an n-type transistor device or a p-type transistor device. The device type is defined by the doping type of the source region <NUM>. In an n-type transistor device, the source region <NUM> is an n-type region, the body region <NUM> is a p-type region, the drift region <NUM>, which has a doping type complementary to the doping type of the body region <NUM>, is an n-type region, and the at least one vertical compensation region <NUM> is a p-type region. In a p-type transistor device, the source region <NUM> is a p-type region, the body region <NUM> is an n-type region, the drift region <NUM> is a p-type region, and the at least one vertical compensation region <NUM> is an n-type region. The transistor device can be implemented as a MOSFET, for example. In a MOSFET, the drain region <NUM> has the same doping type as the drift region <NUM>, as has been described above. For example, a doping concentration of the drain region <NUM> is selected from a range of between 1E18 and 1E19 cm-<NUM>, 1E18 and 1E20 cm-<NUM>, or 1E18 and 1E21 cm-<NUM>, doping concentrations of the drift region <NUM> and the vertical compensation region <NUM> are selected from a range of between 1E15 and 5E16 cm-<NUM>, and a doping concentration of the body region <NUM> is selected from between 5E16 cm-<NUM> and 5E17 cm-<NUM>. The transistor cells <NUM> illustrated in <FIG> are planar transistor cells. Implementing the transistor cells <NUM> as planar transistor cells, however, is only one example. According to another example, as is illustrated in <FIG>, the transistor cells <NUM> are implemented as trench transistor cells. That is, the at least one gate electrode <NUM> is arranged in a trench that extends from the first surface <NUM> into the semiconductor body <NUM>.

In the transistor device explained above, a plurality of transistor cells <NUM> is connected in parallel. That is, the source regions <NUM> of these transistor cells <NUM> are connected to the source node S, the common drain region <NUM> is connected to the drain node D, and the at least one gate electrode <NUM> is connected to a gate node.

The contact plugs <NUM> that are arranged below the first source electrode <NUM> extend from the source and body regions <NUM>, <NUM> through an insulation layer <NUM> that is formed on the top surface <NUM> of the semiconductor body <NUM> to the first source electrode <NUM> to electrically couple the source and body regions <NUM>, <NUM> to the first source electrode <NUM>. In <FIG>, the insulation layer <NUM> is illustrated as a single continuous layer which extends from the first surface <NUM> of the semiconductor body <NUM> to the first source electrode <NUM>. This, however, is only an example. Often, a gate oxide layer with a thickness of, e.g., <NUM> to <NUM> or <NUM> to <NUM>, is arranged on the first surface <NUM> of the semiconductor body <NUM>. The insulation layer <NUM> may comprise this gate oxide layer and an additional layer which is formed on top of this gate oxide layer. This additional layer may comprise an undoped TEOS (tetraethyl orthosilicate) which may have a thickness of about <NUM> to <NUM>, and a doped BPSG (borophosphosilicate glass) having a thickness of about <NUM> to <NUM> or <NUM> to <NUM>, for example. The insulation layer <NUM>, therefore, may comprise several sub-layers.

In many applications such as high current applications, for example, a current through the transistor device <NUM> is measured. Such current measurements are often performed by determining a voltage over an external shunt resistor Rcs, as is schematically illustrated in the circuit diagram of <FIG>. The voltage over the shunt resistor RCS, and the current through the transistor device <NUM> may be determined by means of a controller <NUM>, for example. Such an external shunt resistor RCS, however, adds to the overall losses of the arrangement and may reduce the efficiency.

According to one example, therefore, the current through the transistor device <NUM> is determined by means of a current detection element <NUM>. This is schematically illustrated in the circuit diagram of <FIG>. In this case, an external shunt resistor RCS is no longer required. The current detection element <NUM> may be integrated in the same semiconductor body <NUM> as the transistor device <NUM>, as will be described in more detail further below. The current detection element <NUM> may comprise an additional transistor device. A gate electrode G of the additional transistor device may be electrically coupled to a gate electrode G of the transistor device <NUM>. The gate electrodes G of the transistor device <NUM> and the additional transistor device may be coupled to the controller <NUM>. A drain electrode D of the additional transistor device may be electrically coupled to a drain electrode D of the transistor device <NUM>. A source electrode S of the additional transistor device may be coupled to the controller <NUM>. A source electrode S of the transistor device <NUM> is separate from and not electrically coupled to the source electrode of the additional transistor device.

Now referring to <FIG>, a top view of an exemplary semiconductor arrangement in a semiconductor body <NUM> is schematically illustrated. As has been described with respect to <FIG> above, the transistor device is arranged in an active region <NUM> of the semiconductor body <NUM>. <FIG> illustrate exemplary cross-sectional views of a part of the transistor device along section line A - A' as indicated in <FIG>.

A semiconductor body <NUM> usually comprises not only an active region <NUM>, but also an inactive region, also referred to as passive region or edge (termination) region <NUM>. The semiconductor arrangement, that is, the plurality of transistor cells <NUM>, may be implemented within the active region <NUM> of the semiconductor body <NUM>. An edge region <NUM>, e.g., may be a region adjacent to the horizontal edges (outer edges) of the semiconductor body <NUM> (edge region). The outer edges extend in the vertical direction y between the first surface <NUM> and the second surface <NUM> and are essentially perpendicular to the first surface <NUM> and the second surface <NUM>. A semiconductor body <NUM> having a rectangular or square cross section, for example, generally comprises four outer edges. According to one example and as is schematically illustrated in <FIG>, the active region <NUM> is horizontally surrounded by the edge region <NUM>. The edge region <NUM> generally does not comprise any working transistor cells <NUM>. In particular, an edge region <NUM> may be a region that does not include all active components that are necessary to form a functioning (working) transistor cell <NUM>. Active components are, e.g., gate oxide, source regions <NUM>, body regions <NUM>, gate electrodes <NUM>, or drain regions <NUM>. For example, the edge region <NUM> may be a region within the semiconductor body <NUM> which does not comprise any source regions <NUM>.

The first source electrode <NUM> and a gate electrode <NUM> are arranged on the semiconductor body <NUM> (indicated in dashed lines in <FIG>). The first source electrode <NUM> may be arranged on the active region <NUM> of the semiconductor body <NUM>, for example. In addition to the transistor device comprising a plurality of transistor cells <NUM>, the semiconductor device further comprises at least one sensor cell. The at least one sensor cell may be at least partly arranged in a sensor region <NUM> (crosshatched area in <FIG>). The sensor region <NUM>, therefore, may also comprise at least one working transistor cell, similar to the active region <NUM>. In the example illustrated in <FIG>, the sensor region <NUM> adjoins both the active region <NUM> and the edge region <NUM>. This, however, is only an example. According to another example, the sensor region <NUM> may be surrounded by the active region <NUM> on three or four sides. That is, the sensor region may adjoin the active region <NUM>, but not the edge region <NUM>, or may only adjoin the edge region <NUM> with one of its narrow sides. As will be described in further detail below, the at least one sensor cell arranged in the sensor region <NUM> may be electrically coupled to a second source electrode <NUM>. The second source electrode <NUM> may be arranged on the same side of the semiconductor body <NUM> as the first source electrode <NUM>. The second source electrode <NUM> may be arranged distant from the first source electrode <NUM> such that the first source electrode <NUM> and the second source electrode <NUM> are not electrically coupled to each other and may be contacted individually.

The semiconductor body <NUM> may have a rectangular form, for example. Other forms such as a square form, for example, however are also possible. The active region <NUM> may have a width wa in a first horizontal direction x, and a length la in a second horizontal direction z perpendicular to the first horizontal direction x. The sensor region <NUM> may have a width ws in the first horizontal direction, and a length ls in the second horizontal direction z.

As is schematically illustrated in <FIG>, the width ws of the sensor region <NUM> may correspond to the width ws of a single sensor cell, and the length ls of the sensor region <NUM> may correspond to the length ls of the sensor cell. A sensor cell <NUM> will be described in further detail with respect to <FIG> in the following. In the cross-sectional view of <FIG>, a plurality of transistor cells <NUM><NUM>, <NUM><NUM>, is schematically illustrated. The transistor cells <NUM><NUM>, <NUM><NUM> essentially correspond to the transistor cells <NUM> that have been described with respect to <FIG> above. The semiconductor device illustrated in <FIG> further comprises a sensor cell <NUM>S. In the example illustrated in <FIG>, the sensor cell <NUM>S directly adjoins one of the transistor cells <NUM><NUM> on each side in the first horizontal direction x. That is, at least one working sensor cell <NUM>S of the sensor region <NUM> directly adjoins at least one working transistor cell <NUM><NUM> of the active region <NUM> without any transition zone or intermediate region arranged therebetween, a transition zone or intermediate region being a region without any working transistor cells. The sensor region <NUM> comprising only one sensor cell <NUM>, however, is only an example. The sensor region <NUM> may also comprise more than one sensor cell <NUM>S. Each of the at least one sensor cell <NUM>S may essentially correspond to one of the plurality of transistor cells <NUM><NUM>, <NUM><NUM>. That is, each of the at least one transistor cells <NUM>S comprises a gate electrode <NUM> that is dielectrically insulated from a body region <NUM> by a gate dielectric <NUM>. In the example illustrated in <FIG>, the body region <NUM> extends from the first surface <NUM> into the semiconductor body <NUM>, and the gate electrode <NUM> is arranged above the first surface <NUM> of the semiconductor body <NUM>. According to another example, similar to the transistor cells <NUM> illustrated in <FIG>, the sensor cells <NUM>S may alternatively be implemented as trench transistor cells. That is, the at least one gate electrode <NUM> may be arranged in a trench that extends from the first surface <NUM> into the semiconductor body <NUM>. Each of the at least one sensor cell <NUM> further includes at least one source region <NUM><NUM>, <NUM><NUM> extending from the first surface <NUM> into the body region <NUM>. The source regions of the at least one sensor cell <NUM>S are coupled to the second source electrode <NUM>.

The sensor cell <NUM> illustrated in <FIG> further includes a drift region <NUM> formed in the semiconductor body <NUM>. The drift region <NUM> adjoins the body region <NUM> of the at least one sensor cell <NUM>S and forms a pn-junction with the body region <NUM>. The drift region <NUM> is arranged between the body region <NUM> of the at least one sensor cell <NUM>S and the semiconductor layer <NUM>. Each of the at least one sensor cell <NUM> further comprises a compensation region <NUM> of a doping type complementary to the doping type of the drift region <NUM> and extending from a respective body region <NUM> into the drift region <NUM> in the vertical direction y.

The gate electrodes <NUM> of the plurality of transistor cells <NUM><NUM>, <NUM><NUM> and the gate electrodes <NUM> of the at least one sensor cell <NUM> are coupled to a common gate pad <NUM>, and the drift regions <NUM> of the plurality of transistor cells <NUM><NUM>, <NUM><NUM> and the drift regions <NUM> of the at least one sensor cell <NUM>S are coupled to a common drain region <NUM>. As has been described with respect to <FIG> above, the source regions <NUM><NUM>, <NUM><NUM> of the at least one sensor cell <NUM>S are coupled to a second source electrode <NUM> that is separate and distant from the first source electrode <NUM>.

According to one example, the plurality of transistor cells <NUM><NUM>, <NUM><NUM> comprises a plurality of first transistor cells <NUM><NUM>, each of the at least one first transistor cell <NUM><NUM> comprising two source regions <NUM><NUM>, <NUM><NUM>, and at least one but not more than two second transistor cells <NUM><NUM>, each of the second transistor cells <NUM><NUM> comprising only one source region <NUM><NUM>. As is exemplarily illustrated in <FIG>, each of the second transistor cells <NUM><NUM> directly adjoins one of the at least one sensor cells <NUM>S and is arranged between the at least one sensor cell <NUM>S and at least a subset of the plurality of first transistor cells <NUM><NUM>. That is, each of the second transistor cells <NUM><NUM> may function as a bordering cell that is arranged between one of the first transistor cells <NUM><NUM> and an outermost of the sensor cells <NUM>S. The second transistor cells <NUM><NUM>, however, are working transistor cells and only differ from the first transistor cells <NUM><NUM> in the number of source region <NUM><NUM>, <NUM><NUM> per transistor cell. The single source region <NUM><NUM> of a second transistor cell <NUM><NUM> may be arranged closer to an adjoining first transistor cell <NUM><NUM> than to an adjoining sensor cell <NUM>S. That is, the second source region <NUM><NUM> may be omitted on a side of the second transistor cell <NUM><NUM> that faces the adjoining sensor cell <NUM>.

As has been described with respect to <FIG> above, the sensor region <NUM> may be arranged between the active region <NUM> and the edge region <NUM>. In this example, therefore, there may be only one second transistor cell <NUM><NUM>. If, however, the sensor region <NUM> is surrounded by the active region <NUM> on both sides in the first horizontal direction x, as is exemplarily illustrated in <FIG>, there may be two second transistor cells <NUM><NUM>, one on each side of the sensor region <NUM> in the first horizontal direction x. Such an arrangement may ensure a symmetric heating of the sensor region <NUM>. In the examples described by means of <FIG> and <FIG> above, each first transistor cell <NUM><NUM> comprises two source region <NUM><NUM>, <NUM><NUM>. This, however, is only an example. According to another example, it is also possible that a first transistor cell <NUM><NUM> only comprises one source region <NUM><NUM>. That is, there may not be any difference between the first transistor cells <NUM><NUM> and the second transistor cells <NUM><NUM>.

Still referring to <FIG>, the semiconductor device and, in particular, the sensor region <NUM> further comprises a plurality of first contact plugs <NUM><NUM>, an intermediate layer <NUM>, and a second contact plug <NUM>, wherein each of the plurality of first contact plugs <NUM><NUM> extends between one of the source regions <NUM><NUM>, <NUM><NUM> of the at least one sensor cell <NUM>S and the intermediate layer <NUM>, and provides an electrical connection between the respective source region <NUM><NUM>, <NUM><NUM> and the intermediate layer <NUM>. The second contact plug <NUM> extends between the intermediate layer <NUM> and the second source electrode <NUM>, and provides an electrical connection between the intermediate layer <NUM> and the second source electrode <NUM>. The plurality of first contact plugs <NUM><NUM> may be similar to the contact plugs <NUM><NUM> connecting the first source electrode <NUM> to the source regions <NUM><NUM>, <NUM><NUM> and the body region <NUM> of the at least one transistor cell <NUM><NUM>, <NUM><NUM>. That is, the first contact plugs <NUM><NUM> may comprise at least one of polysilicon, tungsten, aluminum, copper, and a Ti/TiN barrier liner, for example. The intermediate layer <NUM> may comprise tungsten, for example. The second contact plug <NUM> may comprise the same material as the second source electrode <NUM> such as aluminum, for example. The first contact plugs <NUM><NUM> may be narrow contact plugs, while the second contact plug <NUM> may be a broad contact plug. That is, a width of a first contact plug <NUM><NUM> in the first horizontal direction x may be significantly smaller than a width of the second contact plug <NUM> in the first horizontal direction x.

In the example illustrated in <FIG>, the intermediate layer <NUM> comprises a single layer. This, however, is only an example. According to another example, and as is schematically illustrated in <FIG>, the intermediate layer <NUM> may comprise more than one layer. For example, the intermediate layer <NUM> may comprise a first sublayer <NUM><NUM> and a second sublayer <NUM><NUM> that is arranged adjacent to the first sublayer <NUM><NUM> in the vertical direction y. The first sublayer <NUM><NUM> may be arranged between the first contact plugs <NUM><NUM> and the second sublayer <NUM><NUM>, and the second sublayer <NUM><NUM> may be arranged between the first sublayer <NUM><NUM> and the second contact plug <NUM>. The first sublayer <NUM><NUM> in this example comprises a different material than the second sublayer <NUM><NUM>. According to one example, the first sublayer <NUM><NUM> comprises the same material as the first contact plugs <NUM><NUM>, e.g., tungsten, and the second sublayer <NUM><NUM> comprises the same material as the second contact plug <NUM>, e.g., aluminum. Other combinations of materials, however, are also possible.

According to one example, a distance d<NUM> between the intermediate layer <NUM> and the second source electrode <NUM> in the vertical direction y is between <NUM> and <NUM>, or between <NUM> and <NUM>. A thickness d<NUM> of the intermediate layer <NUM> in the vertical direction y may be between <NUM> and <NUM>, for example. A distance d<NUM> between the source regions <NUM><NUM>, <NUM><NUM> and the intermediate layer <NUM> in the vertical direction y may be between <NUM> and <NUM>, or between <NUM> and <NUM>, for example. Other distances and thicknesses, however, are generally also possible.

The number of transistor cells <NUM><NUM>, <NUM><NUM> is generally significantly larger than the number of sensor cells <NUM>. According to one example, a ratio between the number of sensor cells <NUM>S and the number of transistor cells <NUM><NUM>, <NUM><NUM> is between <NUM>:<NUM> and <NUM>:<NUM>. Other ratios, however, are generally also possible. According to one example, the sensor region <NUM> is smaller than the second source electrode <NUM>. This may increase the accuracy of the measurements.

Further, a size of the sensor region <NUM> may be significantly smaller than a size of the active region. According to one example and as is schematically illustrated in <FIG> and <FIG>, each of the plurality of transistor cells <NUM><NUM>, <NUM><NUM> has a first length la in the second horizontal direction z, and a first width s<NUM> in the first horizontal direction x. Each of the at least one sensor cell <NUM>S has a second length ls in the second horizontal direction z, and a second width s<NUM> in the first horizontal direction x. The first length la may be at least three times the second length ls. The first width s<NUM> may equal the second width s<NUM>. However, as the number of transistor cells <NUM><NUM>, <NUM><NUM> is generally larger than the number of sensor cells <NUM>S, an overall width wa of the active region <NUM> is generally larger than an overall width ws of the sensor region <NUM>. There may be a certain number of transistor cells <NUM><NUM>, <NUM><NUM>, however, that have a length in the second horizontal direction z that is shorter than the first length la. Such transistor cells <NUM><NUM>, <NUM><NUM> may be arranged adjacent to the sensor region <NUM> in the second horizontal direction z. The length of such transistor cells <NUM><NUM>, <NUM><NUM> may be shorter in order to allow integration of the sensor region <NUM> in the semiconductor body <NUM>.

Claim 1:
A semiconductor device, comprising:
a semiconductor body (<NUM>) comprising a first surface (<NUM>), a second surface (<NUM>) opposite to the first surface (<NUM>) in a vertical direction (y), an active region (<NUM>), and a sensor region (<NUM>) arranged adjacent to the active region (<NUM>) in a first horizontal direction (x);
a plurality of transistor cells (<NUM><NUM>, <NUM><NUM>) at least partly integrated in the active region (<NUM>), each transistor cell (<NUM><NUM>, <NUM><NUM>) comprising a source region (<NUM>), a body region (<NUM>), a drift region (<NUM>) separated from the source region (<NUM>) by the body region (<NUM>), and a gate electrode (<NUM>) dielectrically insulated from the body region (<NUM>);
at least one sensor cell (<NUM>S) at least partly integrated in the sensor region (<NUM>), each of the at least one sensor cell (<NUM>S) comprising a source region (<NUM>), a body region (<NUM>), a drift region (<NUM>) separated from the source region (<NUM>) by the body region (<NUM>), and a gate electrode (<NUM>) dielectrically insulated from the body region (<NUM>);
a plurality of first contact plugs (<NUM><NUM>);
an intermediate layer (<NUM>); and
a second contact plug (<NUM>), wherein
the source regions (<NUM>) of the plurality of transistor cells (<NUM><NUM>, <NUM><NUM>) are coupled to a first source electrode (<NUM>), and the source regions (<NUM>) of the at least one sensor cell (<NUM>S) are coupled to a second source electrode (<NUM>) separate and distant from the first source electrode (<NUM>),
at least one of the plurality of transistor cells (<NUM><NUM>, <NUM><NUM>) directly adjoins one of the at least one sensor cells (<NUM>),
each of the plurality of first contact plugs (<NUM><NUM>) extends between one of the source regions (<NUM>) of the at least one sensor cell (<NUM>S) and the intermediate layer (<NUM>), and provides an electrical connection between the respective source region (<NUM>) and the intermediate layer (<NUM>), and
the second contact plug (<NUM>) extends between the intermediate layer (<NUM>) and the second source electrode (<NUM>), and provides an electrical connection between the intermediate layer (<NUM>) and the second source electrode (<NUM>).