Patent Description:
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

Memory is also utilized as volatile and non-volatile data storage for a wide range of electronic applications. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged into arrays, with the arrays being used in memory devices.

Memory can be part of a memory system used in computing devices. Memory systems can include volatile, such as DRAM, for example, and/or non-volatile memory, such as Flash memory or RRAM, for example.

<NUM>, <NUM> May <NUM> (<NUM>-<NUM>-<NUM>), pages <NUM>-<NUM>, XP011545752, ISSN: <NUM>-<NUM>, DOI: <NUM>/TED. <NUM> discloses utilising an R-SET technique to boost the SET speed of phase changes materials by overcoming the decrease in crystallization speed caused by GE enrichment.

The present disclosure includes apparatuses and methods related to program operations in memory, as set out in the appended independent claims. An apparatus according to the invention is configured to perform a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state.

In one or more embodiments of the present invention, a controller can be configured to perform a program operation on an array of memory cells by applying an r-set signal and/or an s-reset signal to the array of memory cells. The r-set signal, for example, can include a first portion and a second portion. The first portion can include a signal to program memory cells to a reset state. The second portion can include a signal to program memory cells to a set state. The s-reset signal can include first portion and a second portion, where the first portion can program a memory cell to a set state and the second portion can program a memory cell to a reset state.

In an embodiment of the present invention, the controller can be configured to perform the program operation blind, for example, wherein a pre-read operation is not performed and programming signals are applied to each memory cell based on the desired state for the memory cells. In a number of embodiments, a program signal can be applied to each memory cell of the array of memory cells.

The controller can also be configured to perform a pre-read operation on the memory cells of the array of memory cells before performing the program operation. The pre-read can determine which of the memory cells of the array of memory cells will be programmed during the program operation.

In one or more embodiments of the present invention, the controller is configured to apply the first program signal, for example an r-set signal, to a first portion of the array of memory cells that are to change from the second state to the first state. The controller can also be configured to apply a second program signal, for example a set signal, to a second portion of the array of memory cells that are to change from the second state to the first state. In one or more embodiments, the controller is configured to apply a third program signal, for example a reset signal, to a third portion of the array of memory cells that are to change from the first state to the second state. The controller can also be configured to apply a third program signal , for example a reset signal, to a fourth portion of the array of memory cells that are to remain in the second state.

According to the invention, the first state is a set state and the second state is a reset state. A set state can be a state corresponding to a logic state of <NUM> and a reset state can be a state corresponding to a logic state of <NUM>, although embodiments are not limited to these logic state assignments. Also, according to unclaimed aspects, the first state can be a reset state and the second state can be a set state.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how a number of embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present invention as defined by the appended claims.

As used herein, "a number of" something can refer to one or more of such things. For example, a number of memory devices can refer to one or more of memory devices. Additionally, designators such as "M","N", "S", "T", "X", "Y", as used herein, particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included with a number of embodiments of the present disclosure.

As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate various embodiments of the present disclosure and are not to be used in a limiting sense.

<FIG> is a functional block diagram of a computing system including an apparatus in the form of a number of memory systems <NUM>-<NUM>. <NUM>-N, in accordance with one or more embodiments of the present disclosure. As used herein, an "apparatus" can refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuitry, a die or dice, a module or modules, a device or devices, or a system or systems, for example. In the embodiment illustrated in <FIG>, memory systems <NUM>-<NUM>. <NUM>-N can include one or more memory devices, such as memory devices <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y. Memory devices <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y can include volatile memory and/or non-volatile memory. In a number of embodiments, memory systems <NUM>-<NUM>,. , <NUM>-N can include a multi-chip device. A multi-chip device can include a number of different memory types. For example, a memory system can include a number of chips having non-volatile or volatile memory on any type of a module. In <FIG>, memory system <NUM>-<NUM> is coupled to the host <NUM> via channels <NUM>-<NUM> can include memory devices <NUM>-<NUM>,. For example, memory device <NUM>-<NUM> can be a non-volatile cross-point array memory device and <NUM>-X can be a NAND flash memory device. In this example, each memory device <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y includes a controller <NUM>. Controller <NUM> can receive commands from host <NUM> and control execution of the commands on a memory device. The host <NUM> can send commands to the memory devices <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y. For example, the host can communicate on the same channel (e.g., channel <NUM>-<NUM>) with a non-volatile cross-point array memory device and a NAND flash memory device that are both on the same memory system.

As illustrated in <FIG>, a host <NUM> can be coupled to the memory systems <NUM>-<NUM>. In a number of embodiments, each memory system <NUM>-<NUM>. <NUM>-N can be coupled to host <NUM> via a channel. In <FIG>, memory system <NUM>-<NUM> is coupled to host <NUM> via channel <NUM>-<NUM> and memory system <NUM>-N is coupled to host <NUM> via channel <NUM>-N. Host <NUM> can be a laptop computer, personal computers, digital camera, digital recording and playback device, mobile telephone, PDA, memory card reader, interface hub, among other host systems, and can include a memory access device (e.g., a processor). One of ordinary skill in the art will appreciate that "a processor" can intend one or more processors, such as a parallel processing system, a number of coprocessors, etc..

Host <NUM> includes a host controller <NUM> to communicate with memory systems <NUM>-<NUM>. The host controller <NUM> can send commands to the memory devices <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y via channels <NUM>-<NUM>. The host controller <NUM> can communicate with the memory devices <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y and/or the controller <NUM> on each of the memory devices <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y to read, write, and erase data, among other operations. A physical host interface can provide an interface for passing control, address, data, and other signals between the memory systems <NUM>-<NUM>. <NUM>-N and host <NUM> having compatible receptors for the physical host interface. The signals can be communicated between host <NUM> and memory devices <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y on a number of buses, such as a data bus and/or an address bus, for example, via channels <NUM>-<NUM>.

The host controller <NUM> and/or controller <NUM> on a memory device can include control circuitry (e.g., hardware, firmware, and/or software). In one or more embodiments, the host controller <NUM> and/or controller <NUM> can be an application specific integrated circuit (ASIC) coupled to a printed circuit board including a physical interface. Also, each memory device <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y can include buffer <NUM> of volatile and/or non-volatile memory. Buffer <NUM> can be used to buffer data that is used during execution of read commands and/or write commands. The buffer <NUM> can be configured to store signals, address signals (e.g., read and/or write commands), and/or data (e.g., write data). The buffer can temporarily store signals and/or data while commands are executed.

The memory devices <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y can provide main memory for the memory system or could be used as additional memory or storage throughout the memory system. Each memory device <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y can include one or more arrays of memory cells (e.g., non-volatile memory cells). The arrays can be flash arrays with a NAND architecture, for example. Embodiments are not limited to a particular type of memory device. For instance, the memory device can include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, among others.

The embodiment of <FIG> can include additional circuitry that is not illustrated so as not to obscure embodiments of the present disclosure. For example, the memory systems <NUM>-<NUM>. <NUM>-N can include address circuitry to latch address signals provided over I/O connections through I/O circuitry. Address signals can be received and decoded by a row decoder and a column decoder to access the memory devices <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y. It will be appreciated by those skilled in the art that the number of address input connections can depend on the density and architecture of the memory devices <NUM>-<NUM>,. , <NUM>-X, <NUM>-Y.

<FIG> is a block diagram of an apparatus in the form of a memory device in accordance with a number of embodiments of the present disclosure. In <FIG>, memory device <NUM> includes a controller <NUM> and an array of memory cells <NUM>. The controller <NUM> can include a buffer. The array <NUM> can include one or more arrays of memory cells. The one or more arrays can be non-volatile memory arrays and/or volatile memory arrays.

The controller <NUM> is configured to perform a program operation on the array <NUM>. The controller <NUM> applies a first program signal to a first portion of the array <NUM> that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells of the array <NUM> to a second state and then to the first state.

<FIG> is a block diagram of a portion of an array <NUM> of memory cells <NUM> in accordance with a number of embodiments of the present disclosure. The array <NUM> can be a two terminal cross-point array having memory cells <NUM> located at the intersections of a first plurality of conductive lines (e.g., access lines) <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-T, which may be referred to herein as word lines, and a second plurality of conductive lines (e.g., data/sense lines, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-S) which may be referred to herein as bit lines. The designators T and S can have various values. Embodiments are not limited to a particular number of word lines and/or bit lines. As illustrated, the word lines <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-T are parallel to each other and are orthogonal to the bit lines <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-S, which are substantially parallel to each other; however, embodiments are not so limited. The conductive lines can include conductive material (e.g., a metal material). Examples of the conductive material include, but are not limited to, tungsten, copper, titanium, aluminum, and/or combinations thereof, among other conductive materials.

Each memory cell <NUM> may include a memory element (e.g., a resistive memory element) coupled in series with a select device (e.g., an access device) in accordance with a number of embodiments described herein. The memory element and the select device are discussed further herein.

The select devices can be operated (e.g., turned on/off) to select/deselect the memory element in order to perform operations such as data programming (e.g., writing, and/or data sensing (e.g., reading operations)). The select device can be a diode, a bipolar junction transistor, a MOS transistor, and/or an Ovonic threshold switch, among other devices. In operation, appropriate voltage and/or current signals (e.g., pulses) can be applied to the bit lines and word lines in order to program data to and/or read data from the memory cells <NUM>. The memory cells <NUM> can be programmed to a set state (e.g., low resistance) or a reset state (e.g., high resistance). As an example, the data stored by a memory cell <NUM> of array <NUM> can be determined by turning on a select device and sensing a current through the memory element. The current sensed on the bit line corresponding to the memory cell <NUM> being read corresponds to a resistance level of the memory element (e.g., a resistance level of a resistance variable material) which in turn may correspond to a particular data state (e.g., a binary value). The array <NUM> can have an architecture other than that illustrated in <FIG>, as will be understood by one of ordinary skill in the art.

The array <NUM> can be a two dimensional array. For example, the memory cells <NUM> of the array <NUM> can be arranged between the access lines, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-T and the data/sense lines, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-S in a single level. The array <NUM> can be a three dimensional array. For example, the memory cells of the array can be arranged in multiple levels, where each of the multiple levels has memory cells organized in a cross point architecture. For three dimensional array embodiments of the present disclosure, a vertical string of memory cells can be coupled to a data line and a plurality of access lines coupled to the vertical string of memory cells, for instance.

The access lines <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-T and the data/sense lines <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-S can be coupled to decoding circuits formed in a substrate material (e.g., formed adjacent to or for example below) the array <NUM> and used to interpret various signals (e.g., voltages and/or currents) on the access lines and/or the data/sense lines. As an example, the decoding circuits may include row decoding circuits for decoding signals on the access lines, and column decoding circuits for decoding signals on the data/sense lines.

As used in the present disclosure, the term substrate material can include silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, conventional metal oxide semiconductors (CMOS) (e.g., a CMOS front end with a metal backend) and/or other semiconductor structures and technologies. Various elements (e.g., transistors, and/or circuitry), such as decode circuitry for instance, associated with operating the array <NUM> can be formed in/on the substrate material such as via process steps to form regions or junctions in the base semiconductor structure or foundation.

The memory cells <NUM> can be formed using various processing techniques such as atomic material deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), supercritical fluid deposition (SFD), molecular beam expitaxy (MBE), patterning, etching, filling, chemical mechanical planarization (CMP), combinations thereof, and/or other suitable processes. In accordance with a number of embodiments of the present disclosure, materials may be grown in situ.

<FIG> illustrates a diagram associated with performing program operations in memory in accordance with a number of embodiments of the present disclosure. In one or more embodiments, an r-set signal <NUM> includes a first portion <NUM> and a second portion <NUM>. The first portion <NUM> can include a signal to program memory cells to a reset state. The second portion <NUM> can include a signal to program memory cells to a set state. An r-set signal <NUM> can include a selection-phase <NUM>, a reset peak <NUM>, a reset trough <NUM>, and a set peak <NUM>. In one or more embodiments, the selection-phase <NUM> can include an amount of time to prepare the first portion <NUM> of r-set signal <NUM>. The time associated with preparing the second portion <NUM> of the r-set signal <NUM> can include the time of selection phase <NUM> and the time associated with applying the first portion <NUM> of the r-set signal <NUM>. Therefore, the time associated with the selection phase <NUM> of the r-set signal <NUM> is based on the time to prepare the first portion <NUM> and not the second portion <NUM>.

In one or more embodiments of the present disclosure, a first state is a set state and a second state is a reset state. A first portion <NUM> of r-set signal <NUM> can include programming from the first state to the second state. In one or more embodiments, the first portion <NUM> of r-set signal <NUM> can take approximately <NUM> nanoseconds (ns). A second portion <NUM> of r-set signal <NUM> can include programming from the second state to the first state. In one or more embodiments, the second portion <NUM> of r-set signal <NUM> can take approximately <NUM> nanoseconds (ns). R-set signal <NUM> can be a single, uninterrupted signal or multiple, interrupted signals.

In one or more embodiments of the present disclosure, an s-reset signal could be used during a program operation. In one or more embodiments, an s-reset signal can include a first portion to program memory cells to a set state and a second portion to program memory cells to a reset state. For example, the s-reset can include portion <NUM> from <FIG>, which programs from the second state to the first state, followed by portion <NUM> from <FIG>, which programs from the first state to the second state.

<FIG> is a table illustrating state and signal of a number of portions of a program operation <NUM> in accordance with a number of embodiments of the present disclosure. The state <NUM> illustrates the program state before the program operation and the program state after the program operation. The signal <NUM> illustrates the signal applied to a portion of memory cells of an array of memory cells to maintain or change the program state of the portion of memory cells. A first portion <NUM> of the program operation <NUM> applies an r-set signal to memory cells that remain in a first program state (e.g. a set state corresponding to a logic state of <NUM>). The r-set signal may be applied to memory cells remaining in the set state during program operation <NUM> to counteract drift of set cells. Set-on-set degradation can occur in memory cells where set signals are applied to memory cells that were already programmed to a set state. Set-on-set degradation can occur when memory cells do not change states during program operations. An r-set signal can reduce set-on-set degradation for memory cells that are to remain in a set state after a program operation by programming memory cells to a reset state and then to a set state.

In one or more embodiments of the present disclosure, a second portion <NUM> of the program operation <NUM> applies a reset signal to memory cells that remain in a second program state (e.g. a reset state corresponding to a logic state of <NUM>). A third portion <NUM> of the program operation <NUM> applies a reset signal to memory cells that change from the first program state to the second program state. A fourth portion <NUM> of the program operation <NUM> applies an r-set signal to memory cells that change from the second program state to the first program state.

In one or more embodiments of the present disclosure, the program operation can be performed blind. The program operation can be performed blind by applying a program signal to each memory cell of the array of memory cells.

<FIG> is a table illustrating state and signal of a number of portions of a program operation <NUM> in accordance with a number of embodiments of the present disclosure. The state <NUM> illustrates the program state before the program operation and the program state after the program operation. The signal <NUM> illustrates the signal applied to a portion of memory cells of an array of memory cells to maintain or change the program state of the portion of memory cells. A first portion <NUM> of the program operation <NUM> applies an r-set signal to memory cells that remain in a first program state (e.g. a set state corresponding to a logic state of <NUM>). A second portion <NUM> of the program operation <NUM> applies a reset signal to memory cells that remain in a second program state (e.g. a reset state corresponding to a logic state of <NUM>). A third portion <NUM> of the program operation <NUM> applies a reset signal to memory cells that change from the first program state to the second program state. A fourth portion <NUM> of the program operation <NUM> applies a set signal to memory cells that change from the second program state to the first program state.

In one or more embodiments of the present disclosure, a pre-read operation on memory cells of the array of memory cells can be performed before the program operation. The pre-read can determine which of the memory cells of the array of memory cells will be programmed during the program operation.

<FIG> is a table illustrating state and signal of a number of portions of a program operation <NUM> in accordance with a number of embodiments of the present disclosure. The state <NUM> illustrates the program state before the program operation and the program state after the program operation. The signal <NUM> illustrates the signal applied to a portion of memory cells of an array of memory cells to maintain or change the program state of the portion of memory cells. A first portion <NUM> of the program operation <NUM> applies an r-set signal to memory cells that remain in a first program state (e.g. a set state corresponding to a logic state of <NUM>). A second portion <NUM> of the program operation <NUM> does not apply a signal to memory cells that remain in a second program state (e.g. a reset state corresponding to a logic state of <NUM>). A third portion <NUM> of the program operation <NUM> applies a reset signal to memory cells that change from the first program state to the second program state. A fourth portion <NUM> of the program operation <NUM> applies a set signal to memory cells that change from the second program state to the first program state.

<FIG> is a table illustrating state and signal of a number of portions of a program operation <NUM> in accordance with a number of embodiments of the present disclosure. The state <NUM> illustrates the program state before the program operation and the program state after the program operation. The signal <NUM> illustrates the signal applied to a portion of memory cells of an array of memory cells to maintain or change the program state of the portion of memory cells. A first portion <NUM> of the program operation <NUM> applies an r-set signal to memory cells that remain in a first program state (e.g. a set state corresponding to a logic state of <NUM>). A second portion <NUM> of the program operation <NUM> applies an s-reset signal to memory cells that remain in a second program state (e.g. a reset state corresponding to a logic state of <NUM>). The s-reset signal may be applied to memory cells remaining in the reset state during program operation <NUM> to counteract drift of reset cells. Reset-on-reset degradation can occur in memory cells where reset signals are applied to memory cells that were already programmed to a reset state. Reset-on-reset degradation can occur when memory cells do not change states during program operations. An s-reset can reduce reset-on-reset degradation for memory cells that are to remain in a reset state after a program operation by programming memory cells to a set state and then to a reset state.

In one or more embodiments of the present disclosure, a third portion <NUM> of the program operation <NUM> applies an s-reset signal to memory cells that change from the first program state to the second program state. A fourth portion <NUM> of the program operation <NUM> applies an r-set signal to memory cells that change from the second program state to the first program state.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the present invention is defined by the appended claims.

Claim 1:
An apparatus, comprising:
an array of memory cells (<NUM>), wherein each memory cell includes a resistive memory element; and
a controller (<NUM>) configured to:
perform a program operation on the array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state and to a second portion of the array of memory cells that are to change from a second state to the first state in response to the program operation, wherein the first program signal programs memory cells to the second state and then to the first state, and wherein the first state is a set state and the second state is a reset state,
characterised in that the controller is configured to apply a second program signal to a third portion of the array of memory cells that are to remain in the second state and to a fourth portion of the array of memory cells that are to change from the first state to the second state, wherein the second program signal programs memory cells to the first state and then to the second state.