Patent Description:
A display device may include a plurality of pixels and a plurality of lines providing signals to the pixels. When static electricity flowing into the display device is transmitted to the pixels through the lines, elements included in the pixels may be damaged by the static electricity.

In order to prevent damage to the elements included in the pixels due to the static electricity, the display device may include a discharge diode connected to the lines. The discharge diode may be implemented as a diode-connected transistor. The discharge diode may discharge static electricity flowing into the display device. However, the discharge diode may be damaged when the static electricity passes through the discharge diode.

<CIT> discloses a driver circuit and a method of manufacturing the driver circuit. Further provided are a driver circuit provided with a protection circuit with low leakage current, and a method of manufacturing the driver circuit. A protection circuit in a driver circuit to be electrically connected to a semiconductor element in the driver circuit is provided, and at the same time, a transistor which serves as the semiconductor element in the driver circuit and a transistor included in the protection circuit in the driver circuit is formed. Further, an oxide semiconductor film is used for the transistor included in the protection circuit in the driver circuit.

<CIT> discloses a protection circuit including a plurality of nonlinear elements is provided so as to overlap with each other and so as to be electrically connected in series. At least one nonlinear element in the protection circuit is a diode-connected transistor including an oxide semiconductor in its channel formation region. The other nonlinear element is a diode-connected transistor including silicon in its channel formation region or a diode including silicon in its junction region.

According to an aspect, there is provided a transistor according to claim <NUM>. Additional features are set out in claims <NUM> to <NUM>. According to an aspect, there is provided a display device according to claim <NUM>. Additional features are set out in claims <NUM> to <NUM>.

Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

The display device according to the embodiments may include a transistor which is not damaged by static electricity and discharges the static electricity, so that static electricity may not flow into the pixels of the display device. Accordingly, the display device may not be damaged by static electricity.

Hereinafter, transistors and display devices in accordance with embodiments will be explained in detail with reference to the accompanying drawings.

<FIG> is a block diagram illustrating a display device according to an embodiment.

Referring to <FIG>, the display device includes a display portion DP, a driver <NUM>, and a controller <NUM>.

The display portion DP includes a plurality of pixels PX. The display portion DP may display an image based on light emitted from the pixels PX.

The driver <NUM> provides a driving signal to the display portion DP. The pixels PX may generate light based on the driving signal.

In an embodiment, the driver <NUM> may include a data driver <NUM> and a scan driver <NUM>. The data driver <NUM> may provide a data signal DS to the display portion DP. The scan driver <NUM> may provide a scan signal SS to the display portion DP.

The controller <NUM> provides a control signal to the driver <NUM>. The driver <NUM> may generate the driving signal based on the control signal.

In an embodiment, the controller <NUM> may provide a data control signal DCS to the data driver <NUM>, and may provide a scan control signal SCS to the scan driver <NUM>. The data driver <NUM> may generate the data signal DS based on the data control signal DCS, and the scan driver <NUM> may generate the scan signal SS based on the scan control signal SCS.

A power voltage may be provided to the display portion DP. The power voltage may include a first power voltage VDD and a second power voltage VSS. The first power voltage VDD and the second power voltage VSS may be provided to each of the pixels PX. In an embodiment, a voltage level of the first power voltage VDD may be higher than a voltage level of the second power voltage VSS.

<FIG> is a plan view illustrating a display device according to an embodiment.

Referring to <FIG> and <FIG>, the display device may include a display panel <NUM> and a driving film DF.

The display panel <NUM> may include the display portion DP and a peripheral portion PP. The peripheral portion PP may be adjacent to the display portion DP. In an embodiment, the peripheral portion PP may surround the display portion DP.

The display portion DP may include data lines DL and scan lines SL. The pixels PX may be connected to the data lines DL and the scan lines SL. The data lines DL may transmit the data signal DS, and the scan lines SL may transmit the scan signal SS. In an embodiment, the data lines DL and the scan lines SL may extend in directions intersecting each other.

The peripheral portion PP may include power voltage lines PL. The power voltage lines PL may include a first power voltage line PL1 and a second power voltage line PL2. The first power voltage line PL1 may transmit the first power voltage VDD, and the second power voltage line PL2 may transmit the second power voltage VSS.

The driving film DF may be connected to the peripheral portion PP of the display panel <NUM>. The driving film DF may include a driving chip such as an integrated circuit (IC) chip or the like.

In an embodiment, the scan driver <NUM> may be disposed in the peripheral portion PP of the display panel <NUM>, and the driving film DF may include the data driver <NUM> and the controller <NUM>.

A connection line CL connecting the display portion DP and the driver <NUM> or connecting the driver <NUM> and the controller <NUM> may be disposed in the peripheral portion PP of the display panel <NUM>. In an embodiment, the connection line CL may connect the scan line SL to the scan driver <NUM>, the data line DL to the data driver <NUM>, or the scan driver <NUM> to the controller <NUM>.

<FIG> is a circuit diagram illustrating a pixel PX included in a display device according to an embodiment.

Referring to <FIG>, the pixel PX may be connected to the data line DL and the scan line SL. The pixel PX may include a driving transistor TDR, a switching transistor TSW, a storage capacitor CST, and a light emitting element EE.

A first electrode of the switching transistor TSW may receive the data signal DS, and a second electrode of the switching transistor TSW may be connected to the driving transistor TDR. A gate electrode of the switching transistor TSW may receive the scan signal SS. The switching transistor TSW may provide the data signal DS to the driving transistor TDR in response to the scan signal SS.

A first electrode of the driving transistor TDR may receive the first power voltage VDD, and a second electrode of the driving transistor TDR may be connected to the light emitting element EE. A gate electrode of the driving transistor TDR may be connected to the second electrode of the switching transistor TSW. The driving transistor TDR may generate a driving current corresponding to a voltage stored in the storage capacitor CST using the first power voltage VDD, and may provide the driving current to the light emitting element EE.

In <FIG>, although each of the switching transistor TSW and the driving transistor TDR is illustrated as an NMOS transistor, at least one of the switching transistor TSW and the driving transistor TDR may be a PMOS transistor. The first electrode of each of the switching transistor TSW and the driving transistor TDR may be one of a source electrode and a drain electrode, and the second electrode of each of the switching transistor TSW and the driving transistor TDR may be the other of the source electrode and the drain electrode.

The storage capacitor CST may be connected between the gate electrode of the driving transistor TDR and the second electrode of the driving transistor TDR. The storage capacitor CST may store a voltage corresponding to the data signal DS.

The first electrode of the light emitting element EE may be connected to the second electrode of the driving transistor TDR, and the second electrode of the light emitting element EE may receive the second power voltage VSS. The light emitting element EE may emit light based on the driving current.

In <FIG>, although the pixel PX including two transistors and one capacitor is illustrated, however, components of the pixel PX are not limited thereto. The pixel PX may include three or more transistors and may include two or more capacitors.

<FIG> is a cross-sectional view illustrating the pixel PX in <FIG>.

Referring to <FIG>, the pixel PX may include a substrate <NUM>, transistors disposed on the substrate <NUM> and including the driving transistor TDR, and the light emitting element EE connected to the driving transistor TDR. The driving transistor TDR may include an active layer <NUM>, a gate electrode <NUM>, a first electrode <NUM>, and a second electrode <NUM>. The light emitting element EE may include a pixel electrode <NUM>, an emission layer <NUM>, and an opposite electrode <NUM>.

The substrate <NUM> may include glass, plastic, metal, or the like.

A light blocking layer BML may be disposed on the substrate <NUM>. The light blocking layer BML may block external light from being introduced into the active layer <NUM>. In an embodiment, the light blocking layer BML may include a metal. For example, the metal may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like.

A buffer layer <NUM> may be disposed on the light blocking layer BML. The buffer layer <NUM> may cover the light blocking layer BML on the substrate <NUM>. The buffer layer <NUM> may block impurities from flowing into the active layer <NUM>, and may planarize a portion over the substrate <NUM>. In an embodiment, the buffer layer <NUM> may include an inorganic insulating material. For example, the inorganic insulating material may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

The active layer <NUM> may be disposed on the buffer layer <NUM>. In an embodiment, the active layer <NUM> may include an oxide semiconductor. The oxide semiconductor may include an oxide of at least one selected from the group of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the oxide semiconductor may include at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO), and indium-zinc-tin oxide (IZTO). In another embodiment, the active layer <NUM> may include amorphous silicon, polycrystalline silicon, or the like.

The active layer <NUM> may include a first region 111a, a second region 111b, and a channel region 111c. The second region 111b may be spaced apart from the first region 111a. The channel region 111c may be disposed between the first region 111a and the second region 111b. Each of the first region 111a and the second region 111b may be doped with impurities, and the channel region 111c may not be doped with the impurities. In an embodiment, the impurities may be N-type impurities. For example, the N-type impurities may include phosphorus (P), arsenic (As), antimony (Sb), or the like. In another embodiment, the impurities may be P-type impurities.

A gate insulating layer <NUM> may be disposed on the active layer <NUM>. In an embodiment, the gate insulating layer <NUM> may include an inorganic insulating material. For example, the inorganic insulating material may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

The gate electrode <NUM> may be disposed on the gate insulating layer <NUM>. The gate electrode <NUM> may overlap the channel region 111c of the active layer <NUM>. In an embodiment, the gate electrode <NUM> may include a metal. For example, the metal may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like. The gate electrode <NUM> may have a single-layer structure or a multilayer structure.

An interlayer insulating layer <NUM> may be disposed on the gate electrode <NUM>. The interlayer insulating layer <NUM> may cover the active layer <NUM> and the gate electrode <NUM> on the buffer layer <NUM>. In an embodiment, the interlayer insulating layer <NUM> may include an inorganic insulating material. For example, the inorganic insulating material may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

The first electrode <NUM> may be disposed on the interlayer insulating layer <NUM>. The first electrode <NUM> may be electrically connected to the first region 111a of the active layer <NUM>. In an embodiment, the first electrode <NUM> may contact the first region 111a of the active layer <NUM> through a contact hole penetrating the interlayer insulating layer <NUM>.

The second electrode <NUM> may be disposed on the interlayer insulating layer <NUM>. The second electrode <NUM> may be electrically connected to the second region 111b of the active layer <NUM>. In an embodiment, the second electrode <NUM> may contact the second region 111b of the active layer <NUM> through a contact hole penetrating the interlayer insulating layer <NUM>.

In an embodiment, each of the first electrode <NUM> and the second electrode <NUM> may include a metal. For example, the metal may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like. Each of the first electrode <NUM> and the second electrode <NUM> may have a single-layer structure or a multilayer structure.

A planarization layer <NUM> may be disposed on the first electrode <NUM> and the second electrode <NUM>. The planarization layer <NUM> may cover the first electrode <NUM> and the second electrode <NUM> on the interlayer insulating layer <NUM>. The planarization layer <NUM> may have a flat upper surface. In an embodiment, the planarization layer <NUM> may include an organic insulating material and/or an inorganic insulating material.

The pixel electrode <NUM> may be disposed on the planarization layer <NUM>. The pixel electrode <NUM> may be electrically connected to the second electrode <NUM>. In an embodiment, the pixel electrode <NUM> may contact the second electrode <NUM> through a contact hole penetrating the planarization layer <NUM>.

In an embodiment, the pixel electrode <NUM> may include a transparent conductive oxide. For example, the transparent conductive oxide may include at least one selected from the group including indium-tin oxide (ITO), indium-zinc oxide (IZO), indium oxide (InO), indium-gallium oxide (IGO), and aluminum-zinc oxide (AZO).

In an embodiment, the pixel electrode <NUM> may further include a metal as well as the transparent conductive oxide. For example, the metal may include at least one selected from the group including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), niobium (Nd), iridium (Ir), and chromium (Cr).

A pixel defining layer <NUM> may be disposed on the pixel electrode <NUM>. The pixel defining layer <NUM> may cover the pixel electrode <NUM> on the planarization layer <NUM>. The pixel defining layer <NUM> may have an opening OP exposing at least a portion of the pixel electrode <NUM>. The opening OP may define an area in which the pixel PX is disposed in a plan view. In an embodiment, the opening OP may expose a central portion of the pixel electrode <NUM>, and the pixel defining layer <NUM> may cover an edge of the pixel electrode <NUM>. In an embodiment, the pixel defining layer <NUM> may include an organic insulating material and/or an inorganic insulating material.

The emission layer <NUM> may be disposed on the pixel electrode <NUM>. The emission layer <NUM> may be disposed on the pixel electrode <NUM> exposed by the opening OP of the pixel defining layer <NUM>. The emission layer <NUM> may include at least one of an organic light emitting material and a quantum dot.

In an embodiment, the organic light emitting material may include a low molecular weight organic compound or a high molecular weight organic compound. For example, the low molecular weight organic compound may include copper phthalocyanine, N,N'-diphenylbenzidine, tris-(<NUM>-hydroxyquinoline)aluminum, etc., and the high molecular weight organic compound may include poly(<NUM>,<NUM>-ethylenedioxythiophene), polyaniline, poly-phenylenevinylene, polyfluorene, etc..

In an embodiment, the quantum dot may include a core including a group II-VI compound, a group III-V compound, a group IV-VI compound, a group IV element, a group IV compound, and combinations thereof. In an embodiment, the quantum dot may have a core-shell structure including the core and a shell surrounding the core. The shell may serve as a protective layer for maintaining semiconductor properties by preventing chemical modification of the core and as a charging layer for imparting electrophoretic properties to the quantum dot.

The opposite electrode <NUM> may be disposed on the emission layer <NUM> and the pixel defining layer <NUM>. In an embodiment, the opposite electrode <NUM> may include a metal. For example, the metal may include at least one selected from the group including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), niobium (Nd), iridium (Ir), chromium (Cr), lithium (Li), and calcium (Ca).

<FIG> is a diagram illustrating discharge diodes ED included in a display device according to an embodiment.

Referring to <FIG>, a discharge diode ED may be connected to the connection line CL. When static electricity flows into the display portion DP through the connection line CL from the outside, the static electricity may damage elements in the display portion DP. For example, the gate insulating layer <NUM> of the transistor included in the pixel PX may be damaged by the static electricity. The discharge diode ED may discharge static electricity flowing into the connection line CL.

In an embodiment, one of a first electrode and a second electrode of the discharge diode ED may be connected to the connection line CL, and the other of the first electrode and the second electrode of the discharge diode ED may be connected to the power voltage line PL.

In an embodiment, the discharge diodes ED may include a first discharge diode ED1 and a second discharge diode ED2. A first electrode of the first discharge diode ED1 may be connected to the second power voltage line PL2, and a second electrode of the first discharge diode ED1 may be connected to the connection line CL. A first electrode of the second discharge diode ED2 may be connected to the connection line CL, and a second electrode of the second discharge diode ED2 may be connected to the first power voltage line PL1.

A voltage level of each of the driving signal and the control signal transmitted through the connection line CL may be higher than a voltage level of the second power voltage VSS, and may be lower than a voltage level of the first power voltage VDD. Accordingly, when the driving signal or the control signal is transmitted through the connection line CL, the first discharge diode ED1 and the second discharge diode ED2 may be turned off.

For example, when static electricity having a voltage level higher than the voltage level of the first power voltage VDD is introduced into the connection line CL, the second discharge diode ED2 may be turned on, and the static electricity may be discharged to the first power voltage line PL1 through the second discharge diode ED2. Further, when static electricity having a voltage level lower than the voltage level of the second power voltage VSS is introduced into the connection line CL, the first discharge diode ED1 may be turned on, and the static electricity may be discharged to the second power voltage line PL2 through the first discharge diode ED1.

<FIG> is a circuit diagram illustrating transistors TR included in a display device according to an embodiment.

Referring to <FIG>, the discharge diode ED includes a transistor TR in which a second electrode and a gate electrode are connected. When the second electrode and the gate electrode of the transistor TR are connected, the transistor TR may operate as a diode. The transistor TR in which the second electrode and the gate electrode are connected may be referred to as a diode-connected transistor.

In an embodiment, one of a first electrode and a second electrode of the transistor TR may be connected to the connection line CL, and the other of the first electrode and the second electrode of the transistor TR may be connected to the power voltage line PL.

In an embodiment, the first discharge diode ED1 may include a first transistor TR1, and the second discharge diode ED2 may include a second transistor TR2. A first electrode of the first transistor TR1 may be connected to the second power voltage line PL2, a second electrode of the first transistor TR1 may be connected to the connection line CL, and a gate electrode of the first transistor TR1 may be connected to the second electrode of the first transistor TR1. The first electrode of the second transistor TR2 may be connected to the connection line CL, the second electrode of the second transistor TR2 may be connected to the first power voltage line PL1, and a gate electrode of the second transistor TR2 may be connected to the second electrode of the second transistor TR2.

In <FIG>, although the transistor TR is illustrated as an NMOS transistor, however, the transistor TR may be a PMOS transistor. The first electrode of the transistor TR may be one of a source electrode and a drain electrode, and the second electrode of the transistor TR may be the other of the source electrode and the drain electrode.

<FIG> is a plan view illustrating a transistor according to an embodiment. <FIG> is a cross-sectional view illustrating the transistor taken along a line I-I' in <FIG>.

Referring to <FIG>, the transistor TR includes an active layer <NUM>, a gate electrode <NUM>, a first electrode <NUM>, a second electrode <NUM>, a first connection electrode CE1, and it may include a second connection electrode CE2.

The active layer <NUM> may be disposed on the buffer layer <NUM>. In an embodiment, the active layer <NUM> may include an oxide semiconductor. The oxide semiconductor may include an oxide of at least one selected from the group including indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the oxide semiconductor may include at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO), and indium-zinc-tin oxide (IZTO). In another embodiment, the active layer <NUM> may include amorphous silicon, polycrystalline silicon, or the like.

The active layer <NUM> includes a first region 110a, a second region 110b, and a channel region 110c. The second region 110b may be spaced apart from the first region 110a. The channel region 110c is disposed between the first region 110a and the second region 110b. Each of the first region 110a and the second region 110b may be doped with impurities, and the channel region 110c may not be doped with the impurities. In an embodiment, the impurities may be N-type impurities. For example, the N-type impurities may include phosphorus (P), arsenic (As), antimony (Sb), or the like. In another embodiment, the impurities may be P-type impurities.

The gate electrode <NUM> may be disposed on the gate insulating layer <NUM>. The gate electrode <NUM> may overlap the channel region 110c of the active layer <NUM>. In an embodiment, the gate electrode <NUM> may include a metal. For example, the metal may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like. The gate electrode <NUM> may have a single-layer structure or a multilayer structure.

The first electrode <NUM> is disposed on the interlayer insulating layer <NUM>. The first electrode <NUM> is electrically connected to the first region 110a of the active layer <NUM>. In an embodiment, the first electrode <NUM> may contact the first region 110a of the active layer <NUM> through a first contact hole CH1 penetrating the interlayer insulating layer <NUM>.

The second electrode <NUM> is disposed on the interlayer insulating layer <NUM>. The second electrode <NUM> is electrically connected to the second region 110b of the active layer <NUM>. In an embodiment, the second electrode <NUM> may contact the second region 110b of the active layer <NUM> through a second contact hole CH2 penetrating the interlayer insulating layer <NUM>.

The first connection electrode CE1 may be disposed at the same layer as the active layer <NUM>. In other words, the first connection electrode CE1 may be disposed on the buffer layer <NUM>. The first connection electrode CE1 electrically connects the gate electrode <NUM> and the second electrode <NUM>. In an embodiment, the second electrode <NUM> may contact the first connection electrode CE1 through a third contact hole CH3 penetrating the interlayer insulating layer <NUM>.

In an embodiment, the first connection electrode CE1 may include an oxide semiconductor. The oxide semiconductor may include an oxide of at least one selected from the group including indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the oxide semiconductor may include zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO), and indium-zinc-tin oxide (IZTO). In another embodiment, the first connection electrode CE1 may include amorphous silicon, polycrystalline silicon, or the like.

The first connection electrode CE1 may be doped with impurities. In an embodiment, the impurities may be N-type impurities. For example, the N-type impurities may include phosphorus (P), arsenic (As), antimony (Sb), or the like. In another embodiment, the impurities may be P-type impurities.

A resistance of the first connection electrode CE1 is greater than a resistance of the gate electrode <NUM>. In an embodiment, the first connection electrode CE1 may include an oxide semiconductor, and the gate electrode <NUM> may include a metal. In such an embodiment, since a resistivity of the oxide semiconductor is greater than a resistivity of the metal, the resistance of the first connection electrode CE1 may be greater than the resistance of the gate electrode <NUM>.

The second connection electrode CE2 may be disposed at the same layer as the first electrode <NUM> and the second electrode <NUM>. In other words, the second connection electrode CE2 may be disposed on the interlayer insulating layer <NUM>. The second connection electrode CE2 may contact the first connection electrode CE1 through a fourth contact hole CH4 penetrating the interlayer insulating layer <NUM>, and may contact the gate electrode <NUM> through a fifth contact hole CH5 penetrating the interlayer insulating layer <NUM>.

In an embodiment, the second connection electrode CE2 may include a metal. For example, the metal may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like. The second connection electrode CE2 may have a single-layer structure or a multilayer structure.

In a comparative example of the prior art, as the gate electrode of the transistor, which has a relatively small resistance, is directly connected to the second electrode, static electricity supplied to the second electrode may flow into the active layer through the second electrode, the gate electrode, and the gate insulating layer. In the comparative example, the gate electrode and the active layer may be electrically shorted by the static electricity, and accordingly, the transistor may be damaged by the static electricity.

In an embodiment of the present inventive concept, the gate electrode <NUM> and the second electrode <NUM> of the transistor TR are electrically connected by the first connection electrode CE1, which has a relatively large resistance. If static electricity is supplied to the second electrode <NUM>, the static electricity may not flow into the active layer <NUM> through the second electrode <NUM>, the gate electrode <NUM>, and the gate insulating layer <NUM> because of the relatively large resistance of the first connection electrode CE1. Accordingly, the transistor TR may not be damaged by the static electricity.

<FIG>, <FIG>, <FIG>, <FIG> are diagrams illustrating a method of manufacturing a transistor according to an embodiment. For example, <FIG> may illustrate a method of manufacturing the transistor TR in <FIG>.

Referring to <FIG>, the active layer <NUM> and the first connection electrode CE1 may be formed on the buffer layer <NUM>. The first connection electrode CE1 may be spaced apart from the active layer <NUM>. In an embodiment, an oxide semiconductor layer may be formed on the buffer layer <NUM>, and the oxide semiconductor layer may be patterned to substantially simultaneously form the active layer <NUM> and the first connection electrode CE1.

Referring to <FIG>, the gate insulating layer <NUM> and the gate electrode <NUM> may be formed on the active layer <NUM> and the first connection electrode CE1. In an embodiment, an insulating layer and a metal layer may be sequentially formed on the active layer <NUM> and the first connection electrode CE1, and the insulating layer and the metal layer may be patterned together to substantially simultaneously form the gate insulating layer <NUM> and the gate electrode <NUM>.

Referring to <FIG>, the active layer <NUM> and the first connection electrode CE1 may be doped with impurities. In an embodiment, N-type impurities may be doped into the active layer <NUM> and the first connection electrode CE1 using the gate electrode <NUM> as a mask. The impurities may be doped into the first region 110a and the second region 110b of the active layer <NUM> which do not overlap the gate electrode <NUM>, and the impurities may not be doped into the channel region 110c of the active layer <NUM> which overlaps the gate electrode <NUM>.

Referring to <FIG>, the interlayer insulating layer <NUM> is formed on the gate electrode <NUM>, and the first to fifth contact holes CH1 to CH5 penetrating the interlayer insulating layer <NUM> may be formed. The first contact hole CH1 may expose the first region 110a of the active layer <NUM>, and the second contact hole CH2 may expose the second region 110b of the active layer <NUM>. The third contact hole CH3 may expose a first end of the first connection electrode CE1, and the fourth contact hole CH4 may expose a second end of the first connection electrode CE1. The fifth contact hole CH5 may expose the gate electrode <NUM>.

Referring to <FIG>, the first electrode <NUM>, the second electrode <NUM>, and the second connection electrode CE2 are formed on the interlayer insulating layer <NUM>. The first electrode <NUM> may contact the first region 110a of the active layer <NUM> through the first contact hole CH1. The second electrode <NUM> may contact the second region 110b of the active layer <NUM> through the second contact hole CH2, and may contact the first end of the first connection electrode CE1 through the third contact hole CH3. The second connection electrode CE2 may contact the second end of the first connection electrode CE1 through the fourth contact hole CH4, and may contact the gate electrode <NUM> through the fifth contact hole CH5. In an embodiment, a metal layer may be formed on the interlayer insulating layer <NUM>, and the metal layer may be patterned to substantially simultaneously form the first electrode <NUM>, the second electrode <NUM>, and the second connection electrode CE2.

<FIG> is a plan view illustrating a transistor according to an embodiment. <FIG> is a cross-sectional view illustrating the transistor taken along a line II-II' in <FIG>.

Referring to <FIG>, a transistor TR includes an active layer <NUM>, a gate electrode <NUM>, a first electrode <NUM>, a second electrode <NUM>, a first connection electrode CE1, and it may include a second connection electrode CE2, and a dummy pattern DM. The transistor TR described with reference to <FIG> may be substantially the same as or similar to the transistor TR described with reference to <FIG>, except for further including the dummy pattern DM. Accordingly, descriptions of the overlapping components will be omitted.

The first connection electrode CE1 may include an impurity region CE1a and a non-impurity region CE1b. The impurity region CE1a may be doped with impurities, and the non-impurity region CE1b may not be doped with the impurities. In an embodiment, the impurities may be N-type impurities. For example, the N-type impurities may include phosphorus (P), arsenic (As), antimony (Sb), or the like. In another embodiment, the impurities may be P-type impurities.

A resistance of the non-impurity region CE1b may be greater than a resistance of the impurity region CE1a. As the impurities are doped into the impurity region CE1a, the resistance of the impurity region CE1a may decrease. Accordingly, the resistance of the impurity region CE1a may be less than the resistance of the non-impurity region CE1b into which the impurities are not doped.

The dummy pattern DM may be disposed at the same layer as the gate electrode <NUM>. In other words, the dummy pattern DM may be disposed on the gate insulating layer <NUM>. The dummy pattern DM may overlap a portion of the first connection electrode CE1. Specifically, the dummy pattern DM may overlap the non-impurity region CE1b of the first connection electrode CE1.

In an embodiment, the dummy pattern DM may include a metal. For example, the metal may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like. The dummy pattern DM may have a single-layer structure or a multilayer structure.

In the present embodiment, as the first connection electrode CE1 includes the non-impurity region CE1b having a relatively high resistance, the resistance of the first connection electrode CE1 may increase. Accordingly, as the gate electrode <NUM> and the second electrode <NUM> of the transistor TR are electrically connected by the first connection electrode CE1 having a relatively large resistance, although static electricity is supplied to the second electrode <NUM>, the static electricity may not flow into the active layer <NUM> through the second electrode <NUM>, the gate electrode <NUM>, and the gate insulating layer <NUM>.

<FIG>, <FIG> are diagrams illustrating a method of manufacturing a transistor according to an embodiment. For example, <FIG> may illustrate a method of manufacturing the transistor TR in <FIG>. Descriptions of components of the method of manufacturing the transistor TR described with reference to <FIG>, which are substantially the same as or similar to those of the method of manufacturing the transistor TR described with reference to <FIG>, will be omitted.

Referring to <FIG>, the gate insulating layer <NUM>, the gate electrode <NUM>, and the dummy pattern DM may be formed on the active layer <NUM> and the first connection electrode CE1. In an embodiment, an insulating layer and a metal layer may be sequentially formed on the active layer <NUM> and the first connection electrode CE1, and the insulating layer and the metal layer may be patterned together to substantially simultaneously form the gate insulating layer <NUM>, the gate electrode <NUM>, and the dummy pattern DM.

Referring to <FIG>, the active layer <NUM> and the first connection electrode CE1 may be doped with impurities. In an embodiment, N-type impurities may be doped into the active layer <NUM> and the first connection electrode CE1 by using the gate electrode <NUM> and the dummy pattern DM as a mask. The impurity region CE1a of the first connection electrode CE1, which does not overlap the dummy pattern DM, may be doped with the impurities, and the non-impurity region CE1b of the first connection electrode CE1, which overlaps the dummy pattern DM, may not be doped with the impurities.

<FIG> is a plan view illustrating a transistor according to an embodiment.

Referring to <FIG>, a transistor TR includes an active layer <NUM>, a gate electrode <NUM>, a first electrode <NUM>, a second electrode <NUM>, a first connection electrode CE1, and it may include a second connection electrode CE2, and a plurality of dummy patterns DM. The transistor TR described with reference to <FIG> may be substantially the same as or similar to the transistor TR described with reference to <FIG> except for including the plurality of dummy patterns DM. Accordingly, descriptions of the overlapping components will be omitted.

The dummy patterns DM may be disposed at the same layer as the gate electrode <NUM>. Each of the dummy patterns DM may overlap a portion of the first connection electrode CE1. Impurities may not be doped into portions of the first connection electrode CE1 respectively overlapping the dummy patterns DM, and accordingly, the first connection electrode CE1 may include a plurality of non-impurity regions.

<FIG> is a plan view illustrating a transistor according to an embodiment. <FIG> is a cross-sectional view illustrating the transistor taken along a line III-III' in <FIG>.

Referring to <FIG> and <FIG>, a transistor TR includes an active layer <NUM>, a gate electrode <NUM>, a first electrode <NUM>, a second electrode <NUM>, a first connection electrode CE1, and it may include a second connection electrode CE2. The transistor TR described with reference to <FIG> and <FIG> may be substantially the same as or similar to the transistor TR described with reference to <FIG> except for the position of the second connection electrode CE2. Accordingly, descriptions of the overlapping components will be omitted.

The second connection electrode CE2 may be disposed on the first electrode <NUM> and the second electrode <NUM>. In an embodiment, the second connection electrode CE2 may be disposed at the same layer as the pixel electrode <NUM> in <FIG>. In other words, the second connection electrode CE2 may be disposed on the planarization layer <NUM>. The second connection electrode CE2 may contact the first connection electrode CE1 through a fourth contact hole CH4 penetrating the planarization layer <NUM> and the interlayer insulating layer <NUM>, and may contact the gate electrode <NUM> through a fifth contact hole CH5 penetrating the planarization layer <NUM> and the interlayer insulating layer <NUM>.

In an embodiment, the second connection electrode CE2 may include a transparent conductive oxide. For example, the transparent conductive oxide may include at least one selected from the group including indium-tin oxide (ITO), indium-zinc oxide (IZO), indium oxide (InO), indium-gallium oxide (IGO), and aluminum-zinc oxide (AZO).

In an embodiment, the second connection electrode CE2 may further include a metal as well as the transparent conductive oxide. For example, the metal may include at least one selected from the group including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), niobium (Nd), iridium (Ir), and chromium (Cr).

A resistance of the second connection electrode CE2 may be greater than a resistance of the gate electrode <NUM>. In an embodiment, the second connection electrode CE2 may include a transparent conductive oxide, and the gate electrode <NUM> may include a metal. In such an embodiment, since a resistivity of the transparent conductive oxide is greater than a resistivity of the metal, the resistance of the second connection electrode CE2 may be greater than the resistance of the gate electrode <NUM>.

In the embodiment of the present inventive concept, the gate electrode <NUM> and the second electrode <NUM> of the transistor TR are electrically connected by the first connection electrode CE1 having a relatively large resistance and may be electrically connected by the the second connection electrode CE2 having a relatively large resistance. Therefore, although static electricity is supplied to the second electrode <NUM>, static electricity may not be introduced to the active layer <NUM> through the second electrode <NUM>, the gate electrode <NUM>, and the gate insulating layer <NUM>. Accordingly, the transistor TR may not be damaged by the static electricity.

<FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> are diagrams illustrating a method of manufacturing a transistor according to an embodiment. For example, <FIG> may illustrate a method of manufacturing the transistor TR in <FIG> and <FIG>. Descriptions of components of the method of manufacturing the transistor TR described with reference to <FIG>, which are substantially the same as or similar to those of the method of manufacturing the transistor TR described with reference to <FIG>, will be omitted.

Referring to <FIG> and <FIG>, the interlayer insulating layer <NUM> is formed on the gate electrode <NUM>, and the first to third contact holes CH1 to CH3 penetrating the interlayer insulating layer <NUM> may be formed. The first contact hole CH1 may expose the first region 110a of the active layer <NUM>, and the second contact hole CH2 may expose the second region 110b of the active layer <NUM>. The third contact hole CH3 may expose a first end of the first connection electrode CE1.

Referring to <FIG> and <FIG>, the first electrode <NUM> and the second electrode <NUM> are formed on the interlayer insulating layer <NUM>. The first electrode <NUM> may contact the first region 110a of the active layer <NUM> through the first contact hole CH1. The second electrode <NUM> may contact the second region 110b of the active layer <NUM> through the second contact hole CH2, and may contact the first end of the first connection electrode CE1 through the third contact hole CH3. In an embodiment, a metal layer may be formed on the interlayer insulating layer <NUM>, and the metal layer may be patterned to substantially simultaneously form the first electrode <NUM> and the second electrode <NUM>.

Referring to <FIG> and <FIG>, the planarization layer <NUM> may be formed on the first electrode <NUM> and the second electrode <NUM>, and fourth and fifth contact holes CH4 and CH5 penetrating the planarization layer <NUM> and the interlayer insulating layer <NUM> may be formed. The fourth contact hole CH4 may expose a second end of the first connection electrode CE1, and the fifth contact hole CH5 may expose the gate electrode <NUM>.

Referring to <FIG> and <FIG>, the second connection electrode CE2 may be formed on the planarization layer <NUM>. The second connection electrode CE2 may contact the second end of the first connection electrode CE1 through the fourth contact hole CH4, and may contact the gate electrode <NUM> through the fifth contact hole CH5. In an embodiment, a transparent conductive oxide layer may be formed on the planarization layer <NUM>, and the transparent conductive oxide layer may be patterned to form the second connection electrode CE2.

<FIG> is a plan view illustrating a transistor according to an embodiment. <FIG> is a cross-sectional view illustrating the transistor taken along a line IV-IV' in <FIG>.

Referring to <FIG> and <FIG>, a transistor TR includes an active layer <NUM>, a gate electrode <NUM>, a first electrode <NUM>, a second electrode <NUM>, and a first connection electrode CE1. The transistor TR described with reference to <FIG> and <FIG> may be substantially the same as or similar to the transistor TR described with reference to <FIG> except for the position of the first connection electrode CE1 and the omission of the second connection electrode CE2. Accordingly, descriptions of the overlapping components will be omitted.

The first connection electrode CE1 may be disposed on the first electrode <NUM> and the second electrode <NUM>. In an embodiment, the first connection electrode CE1 may be disposed at the same layer as the pixel electrode <NUM> in <FIG>. In other words, the first connection electrode CE1 may be disposed on the planarization layer <NUM>. The first connection electrode CE1 may contact the second electrode <NUM> through a third contact hole CH3 penetrating the planarization layer <NUM>, and may contact the gate electrode <NUM> through a fourth contact hole CH4 penetrating the planarization layer <NUM> and the interlayer insulating layer <NUM>.

In an embodiment, the first connection electrode CE1 may include a transparent conductive oxide. For example, the transparent conductive oxide may include at least one selected from the group including indium-tin oxide (ITO), indium-zinc oxide (IZO), indium oxide (InO), indium-gallium oxide (IGO), and aluminum-zinc oxide (AZO).

In an embodiment, the first connection electrode CE1 may further include a metal as well as the transparent conductive oxide. For example, the metal may include at least one selected from the group including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), niobium (Nd), iridium (Ir), and chromium (Cr).

A resistance of the first connection electrode CE1 is greater than a resistance of the gate electrode <NUM>. In an embodiment, the first connection electrode CE1 may include a transparent conductive oxide, and the gate electrode <NUM> may include a metal. In such an embodiment, since a resistivity of the transparent conductive oxide is greater than a resistivity of the metal, the resistance of the first connection electrode CE1 may be greater than the resistance of the gate electrode <NUM>.

<FIG> is a plan view illustrating a transistor according to an embodiment. <FIG> is a cross-sectional view illustrating the transistor taken along a line V-V' in <FIG>.

Referring to <FIG> and <FIG>, a transistor TR includes an active layer <NUM>, a gate electrode <NUM>, a first electrode <NUM>, a second electrode <NUM>, a first connection electrode CE1, it may include a second connection electrode CE2. The transistor TR described with reference to <FIG> and <FIG> may be substantially the same as or similar to the transistor TR described with reference to <FIG> and <FIG> except for the addition of the second connection electrode CE2. Accordingly, descriptions of the overlapping components will be omitted.

The second connection electrode CE2 may be disposed at the same layer as the first electrode <NUM> and the second electrode <NUM>. In other words, the second connection electrode CE2 may be disposed on the interlayer insulating layer <NUM>. The second connection electrode CE2 may contact the first connection electrode CE1 through a fourth contact hole CH4 penetrating the planarization layer <NUM>, and may contact the gate electrode <NUM> through a fifth contact hole CH5 penetrating the interlayer insulating layer <NUM>.

As discussed, embodiments provide a transistor including: a substrate; an active layer disposed on the substrate and including a first region, a second region, and a channel region between the first region and the second region; a gate electrode disposed on the active layer, the gate electrode overlapping the channel region; a first electrode disposed on the substrate, the first electrode being electrically connected to the first region; a second electrode disposed on the substrate, the second electrode being electrically connected to the second region; and a first connection electrode disposed on the substrate and electrically connecting the gate electrode and the second electrode.

As discussed, embodiments provide a display device, comprising: a display portion including a substrate and a plurality of pixels disposed on the substrate; a driver configured to provide a driving signal to the display portion; a controller configured to provide a control signal to the driver; and a transistor connected to a connection line connecting the display portion and the driver or connecting the driver and the controller, the transistor being as set out in any of the above embodiments.

In some embodiments of the present invention, the gate electrode and the second electrode of the transistor are electrically connected by a first connection electrode having a relatively large resistance. Thus, although static electricity is supplied to the second electrode, the static electricity may not flow into the active layer through the second electrode, the gate electrode, and the gate insulating layer. Accordingly, the transistor may not be damaged by the static electricity.

The transistor and the display device according to the embodiments may be applied to a display device included in a computer, a notebook, a mobile phone, a smart phone, a smart pad, a PMP, a PDA, an MP3 player, or the like.

Claim 1:
A transistor (TR), comprising:
a substrate (<NUM>);
an active layer (<NUM>) disposed on the substrate and including a first region (110a), a second region (110b), and a channel region (110c) between the first region and the second region;
a gate electrode (<NUM>) disposed on the active layer, the gate electrode overlapping the channel region;
an insulating layer (<NUM>) disposed on the gate electrode;
a first electrode (<NUM>) disposed on the insulating layer, the first electrode being electrically connected to the first region;
a second electrode (<NUM>) disposed on the insulating layer, the second electrode being electrically connected to the second region; and
a first connection electrode (CE1) disposed on the substrate and electrically connecting the gate electrode and the second electrode,
characterized in that
a resistance of the first connection electrode is greater than a resistance of the gate electrode.