Patent Description:
As memory devices are shrinking to smaller die size to reduce manufacturing cost and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. A three-dimensional (3D) memory architecture can address the density and performance limitation in planar memory cells.

In a 3D NAND flash memory, a memory array can include a plurality of memory strings vertically arranged on a substrate, each memory string having a plurality of memory cells that are vertically stacked. As such, storage density per unit area can be greatly increased. The <CIT> describes a non-volatile semiconductor storage device and a method for voltage trimming thereof.

While programming and reading operations can be performed for all the memory cells that share a word line in a memory page, an erase operation is usually performed for all the memory cells in a memory block that share a common source line. During the erase operation, an erase voltage (about <NUM> V) can be applied to the common source line or an n-well in the substrate, while word lines can be grounded. Electrical potentials of the channel layers in the memory strings can be raised gradually from bottom to top.

With the increase of the number of vertically stacked memory cells, the erase voltage can also be applied to the bit lines at top of the memory strings to improve erase speed. Additionally, gate-induced-drain-leakage (GIDL) current can be introduced to assist the erase operation such that the electrical potential of the channel layers in the memory strings can quickly reach the erase voltage. After an erase operation, the GIDL current needs to be removed and high electrical potentials of the common source line and the bit lines need to be discharged. Although discharging can be performed through a discharge transistor connected between the common source line and a corresponding bit line, timing of a discharge operation is critical.

Embodiments of a NAND flash memory with a discharge circuit and a method for discharging a NAND flash memory are described in the present disclosure.

One aspect of the present disclosure provides an erasable memory device according to claim <NUM>.

In some embodiments, the discharge transistor is a metal-oxide-semiconductor field-effect-transistor (MOSFET). A gate terminal of the MOSFET is connected to the gate discharge circuit. A source terminal of the MOSFET is connected to the source line and a drain terminal of the MOSFET connected to the bit line.

In some embodiments, the gate discharge circuit includes a set of diodes connected in series.

In some embodiments, the gate discharge circuit further includes a switching transistor connected in series with the set of diodes.

In some embodiments, the gate discharge circuit further includes a voltage level shifter configured to provide a switching voltage to switch on the switching transistor.

In some embodiments, the set of diodes comprise a MOSFET configured as an effective diode, wherein a gate terminal of the MOSFET is connected to a drain terminal of the MOSFET. In some embodiments, the MOSFET is a p-channel MOSFET.

In some embodiments, the source line detect circuit includes an operational amplifier, a resistive voltage divider, and a capacitor connected in parallel with the resistive voltage divider. First ends of the capacitor and the resistive voltage divider are connected. Second ends of the capacitor and the resistive voltage dividers are grounded.

In some embodiments, the source line detect circuit also includes a pull-up transistor connecting the first ends of the capacitor and the resistive voltage divider to a power supply. The pull-up transistor is controlled by an output of the operational amplifier.

In some embodiments, the resistive voltage divider includes a first resistor connected in series with a second resistor. The second resistor has an adjustable resistance.

In some embodiments, the operational amplifier is configured to set the predetermined value through an electrical potential of the first ends of the capacitor and the resistive voltage divider. A negative input of the operational amplifier is connected to a reference voltage, and a positive input of the operational amplifier is connected to an intermediate point of the resistive voltage divider.

In some embodiments, the operational amplifier is configured to compare the electrical potential of the source line with the predetermined value. A negative input of the operational amplifier is connected to the source line, and a positive input of the operational amplifier is connected to the first ends of the capacitor and the resistive voltage divider.

In some embodiments, the source line is grounded.

In some embodiments, the discharge circuit further includes a current source configured to regulate a discharge current flowing through the source line.

Another aspect of the present disclosure provides a method for discharging a memory device after an erase operation according to claim <NUM>.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology can be understood at least in part from usage in context. For example, the term "one or more" as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as "a," "an," or "the," again, can be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

As used herein, the term "nominal/nominally" refers to a desired, or target, value of a characteristic or parameter for a component or a process step, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. Based on the particular technology node, the term "about" can indicate a value of a given quantity that varies within.

<FIG> illustrates a block diagram of an exemplary system S <NUM> having a memory system <NUM>, according to some embodiments of the present disclosure. System S <NUM> can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. The memory system <NUM> (also referred to as a NAND memory system) includes a NAND flash memory <NUM> and a host controller <NUM> (also referred to as a memory controller). The memory system <NUM> can communicate with a host computer <NUM> through the memory controller <NUM>, where the memory controller <NUM> can be connected to the NAND flash memory <NUM> via a memory channel <NUM>. In some embodiments, the memory system <NUM> can have more than one NAND flash memory <NUM>, while each NAND flash memory <NUM> can be managed by the memory controller <NUM>.

In some embodiments, the host computer <NUM> can include a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host computer <NUM> sends data to be stored at the NAND memory system or memory system <NUM> or retrieves data by reading the memory system <NUM>.

The memory controller <NUM> can handle I/O requests received from the host computer <NUM>, ensure data integrity and efficient storage, and manage the NAND flash memory <NUM>. The memory channel <NUM> can provide data and control communication between the memory controller <NUM> and the NAND flash memory <NUM> via a data bus.

Memory controller <NUM> and one or more NAND flash memory <NUM> can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system <NUM> can be implemented and packaged into different types of end electronic products. In one example as shown in <FIG>, memory controller <NUM> and a single NAND flash memory <NUM> can be integrated into a memory card <NUM>. Memory card <NUM> can include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. Memory card <NUM> can further include a memory card connector <NUM> coupling memory card <NUM> with a host (e.g., the host computer <NUM> in FIG. In another example as shown in <FIG>, memory controller <NUM> and multiple NAND flash memories <NUM> can be integrated into a solid state drive (SSD) <NUM>. SSD <NUM> can further include an SSD connector <NUM> coupling SSD <NUM> with a host (e.g., the host computer <NUM> in <FIG>).

Referring to <FIG>, the NAND flash memory <NUM> (i.e., "flash," "NAND flash" or "NAND") can be a memory chip (package), a memory die or any portion of a memory die, and can include one or more memory planes <NUM>, each of which can include a plurality of memory blocks <NUM>. Identical and concurrent operations can take place at each memory plane <NUM>. The memory block <NUM>, which can be megabytes (MB) in size, is the smallest size to carry out erase operations. Shown in <FIG>, the exemplary NAND flash memory <NUM> includes four memory planes <NUM> and each memory plane <NUM> includes six memory blocks <NUM>. Each memory block <NUM> can include a plurality of memory cells, where each memory cell can be addressed through interconnections such as bit lines and word lines. The bit lines and word lines can be laid out perpendicularly (e.g., in rows and columns, respectively), forming an array of metal lines. The direction of bit lines and word lines are labeled as "BL" and "WL" respectively in <FIG>. In this disclosure, one or more memory block <NUM> can also be referred to as the "memory array" or "array. " The memory array is the core area in a memory device, performing storage functions.

The NAND flash memory <NUM> also includes a peripheral circuit region <NUM>, an area surrounding memory planes <NUM>. The peripheral circuit region <NUM>, also named as peripheral circuits, contains many digital, analog, and/or mixed-signal circuits to support functions of the memory array, for example, page buffers/sense amplifiers <NUM>, row decoders/word line drivers <NUM>, column decoders/bit line drivers <NUM>, and control circuits <NUM>. Control circuits <NUM> include register, active and/or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as would be apparent to a person of ordinary skill in the art. The control circuits <NUM> of the peripheral circuit region <NUM> can be configured to initiate a program operation on a select memory cell of a NAND memory string in the memory block <NUM>. In some implementations, the control circuits <NUM> receives a program command from a memory controller (e.g., memory controller <NUM>) through interface, and in response, sends control signals to at least row decoder/word line driver, column decoder/bit line driver, and voltage generator deposed in the peripheral circuit region <NUM> to initiate the program operation on the select memory cell.

It is noted that the layout of the electronic components in the memory system <NUM> and the NAND flash memory <NUM> in <FIG> are shown as an example. The memory system <NUM> and the NAND flash memory <NUM> can have other layout and can include additional components. For example, The NAND flash memory <NUM> can also have high-voltage charge pumps, I/O circuits, etc. The memory system <NUM> can also include firmware, data scrambler, etc. In some embodiments, the peripheral circuit region <NUM> and the memory array can be formed independently on separate wafers and then connected with each other through wafer bonding.

<FIG> shows a schematic diagram of the NAND flash memory <NUM>, according to some embodiments of the present disclosure. The NAND flash memory <NUM> includes one or more memory blocks <NUM>. Each memory block <NUM> includes memory strings <NUM>. Each memory string <NUM> includes memory cells <NUM>. The memory cells <NUM> sharing the same word line forms a memory page <NUM>. The memory string <NUM> can also include at least one field effect transistor (e.g., MOSFET) at each end, which is controlled by a bottom select gate (BSG) <NUM> and a top select gate (TSG) <NUM>, respectively. The drain terminal of a top select transistor <NUM>-T can be connected to the bit line <NUM>, and the source terminal of a bottom select transistor <NUM>-T can be connected to an array common source (ACS) <NUM>. The ACS <NUM> can be shared by the memory strings <NUM> in an entire memory block, and is also referred to as the common source line.

The NAND flash memory <NUM> can also include a peripheral circuit that includes many digital, analog, and/or mixed-signal circuits to support functions of the memory block <NUM>, for example, a page buffer/sense amplifier <NUM>, a row decoder/word line driver <NUM>, a column decoder/bit line driver <NUM>, a control circuit <NUM>, a voltage generator <NUM> and an input/output buffer <NUM>. These circuits can include active and/or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as would be apparent to a person of ordinary skill in the art. In some embodiments, the peripheral circuit can support an erase operation assisted by a gate-induced drain leakage (GIDL) current.

The memory blocks <NUM> can be coupled with the row decoder/word line driver <NUM> via word lines ("WLs") <NUM>, bottom select gates ("BSGs") <NUM> and top select gates ("TSG") <NUM>. The memory blocks <NUM> can be coupled with the page buffer/sense amplifier <NUM> via bit lines ("BLs") <NUM>. The row decoder/word line driver <NUM> can select one of the memory blocks <NUM> on the NAND flash memory <NUM> in response to an X-path control signal provided by the control circuit <NUM>. The row decoder/word line driver <NUM> can transfer voltages provided from the voltage generator <NUM> to the word lines according to the X-path control signal. During the read and programming operation, the row decoder/word line driver <NUM> can transfer a read voltage Vread and a program voltage Vpgm to a selected word line and a pass voltage Vpass to an unselected word line according to the X-path control signal received from the control circuit <NUM>.

The column decoder/bit line driver <NUM> can transfer an inhibit voltage Vinhibit to an unselected bit line and connect a selected bit line to ground according to a Y-path control signal received from the control circuit <NUM>. In the other words, the column decoder/bit line driver <NUM> can be configured to select or unselect one or more memory strings <NUM> according to the Y-path control signal from the control circuit <NUM>. The page buffer/sense amplifier <NUM> can be configured to read and program (write) data from and to the memory block <NUM> according to the control signal Y-path control from the control circuit <NUM>. For example, the page buffer/sense amplifier <NUM> can store one page of data to be programmed into one memory page <NUM>. In another example, page buffer/sense amplifier <NUM> can perform verify operations to ensure that the data has been properly programmed into each memory cell <NUM>. In yet another example, during a read operation, the page buffer/sense amplifier <NUM> can sense current flowing through the bit line <NUM> that reflects the logic state (i.e., data) of the memory cell <NUM> and amplify small signal to a measurable magnification.

The input/output buffer <NUM> can transfer the I/O data from/to the page buffer/sense amplifier <NUM> as well as addresses ADDR or commands CMD to the control circuit <NUM>. In some embodiments, the input/output buffer <NUM> can function as an interface between the memory controller <NUM> (in <FIG>) and the NAND flash memory <NUM>.

The control circuit <NUM> can control the page buffer/sense amplifier <NUM> and the row decoder/word line driver <NUM> in response to the commands CMD transferred by the input/output buffer <NUM>. During the programming operation, the control circuit <NUM> can control the row decoder/word line driver <NUM> and the page buffer/sense amplifier <NUM> to program a selected memory cell. During the read operation, the control circuit <NUM> can control the row decoder/word line driver <NUM> and the page buffer/sense amplifier <NUM> to read a selected memory cell. The X-path control signal and the Y-path control signal include a row address X-ADDR and a column address Y-ADDR that can be used to locate the selected memory cell in the memory block <NUM>. The row address X-ADDR can include a page index, a block index and a plane index to identify the memory page <NUM>, memory block <NUM>, and memory plane <NUM> (in <FIG>), respectively. The column address Y-ADDR can identify a byte or a word in the data of the memory page <NUM>.

In some implementations, the control circuit <NUM> can include one or more control logic unit. Each control logic unit described herein can be either a software module and/or a firmware module running on a processor, such as a microcontroller unit (MCU), which is part of control circuits <NUM>, or a hardware module of a finite-state machine (FSM), such as an integrated circuit (IC, e.g., application-specific IC (ASIC), field-programmable gate array (FPGA), etc.), or a combination of software module, firmware module, and hardware module.

The voltage generator <NUM> can generate voltages to be supplied to word lines and bit lines under the control of the control circuit <NUM>. The voltages generated by the voltage generator <NUM> include the read voltage Vread, the program voltage Vpgm, the pass voltage Vpass, the inhibit voltage Vinhibit, etc..

In some embodiments, the NAND flash memory <NUM> can be formed based on the floating gate technology. In some embodiments, the NAND flash memory <NUM> can be formed based on charge trapping technology. The NAND flash memory based on charge trapping can provide high storage density and high intrinsic reliability. Storage data or logic states (e.g., threshold voltage Vth of the memory cell <NUM>) depends on the amount of charge trapped in a storage layer. In some embodiments, the NAND flash memory <NUM> can be a three-dimensional (3D) memory device, where the memory cells <NUM> can be vertically stacked on top of each other.

<FIG> illustrates a perspective view of a portion of a 3D NAND flash memory <NUM>, according to some embodiments of the present disclosure. The 3D NAND flash memory <NUM> includes a substrate <NUM>, an insulating film <NUM> over the substrate <NUM>, a tier of bottom select gates (BSGs) <NUM> over the insulating film <NUM>, and tiers of control gates <NUM>, also referred to as "word lines (WLs)," stacking on top of the BSGs <NUM> to form a film stack <NUM> of alternating conductive and dielectric layers. The dielectric layers adjacent to the tiers of control gates are not shown in <FIG> for clarity.

The control gates of each tier are separated by slit structures <NUM>-<NUM> and <NUM>-<NUM> through the film stack <NUM>. The 3D NAND flash memory <NUM> also includes a tier of top select gates (TSGs) <NUM> over the stack of control gates <NUM>. The stack of TSG <NUM>, control gates <NUM> and BSG <NUM> is also referred to as "gate electrodes". The 3D NAND flash memory <NUM> further includes memory strings <NUM> and doped source line regions <NUM> in portions of substrate <NUM> between adjacent BSGs <NUM>. Each memory strings <NUM> includes a channel hole <NUM> extending through the insulating film <NUM> and the film stack <NUM> of alternating conductive and dielectric layers. Memory strings <NUM> also includes a memory film <NUM> on a sidewall of the channel hole <NUM>, a channel layer <NUM> over the memory film <NUM>, and a core filler <NUM> surrounded by the channel layer <NUM>. A memory cell <NUM> (e.g., <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) can be formed at the intersection of the control gate <NUM> (e.g., <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) and the memory string <NUM>. A portion of the channel layer <NUM> responds to the respective control gate is also referred to as the channel layer <NUM> of the memory cell. The 3D NAND flash memory <NUM> further includes bit lines (BLs) <NUM> connected with the memory strings <NUM> over the TSGs <NUM>. The 3D NAND flash memory <NUM> also includes metal interconnect lines <NUM> connected with the gate electrodes through contact structures <NUM>. The edge of the film stack <NUM> is configured in a shape of staircase to allow an electrical connection to each tier of the gate electrodes.

In <FIG>, for illustrative purposes, three tiers of control gates <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> are shown together with one tier of TSG <NUM> and one tier of BSG <NUM>. In this example, each memory string <NUM> can include three memory cells <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, corresponding to the control gates <NUM>-<NUM>,<NUM>-<NUM> and <NUM>-<NUM>, respectively. In some embodiments, the number of control gates and the number of memory cells can be more than three to increase storage capacity. The 3D NAND flash memory <NUM> can also include other structures, for example, TSG cut, common source contact, array common source and dummy memory string. These structures are not shown in <FIG> for simplicity.

In a NAND flash memory, read and programming operations can be performed in a memory page <NUM>, which includes all memory cells <NUM> sharing the same word line. In a NAND memory, the memory cell <NUM> can be in an erased state ER or a programmed state P1. To further increase storage density, a memory cell can store n-bit of data and have <NUM>n states, where n is a whole number. For example, n equals <NUM>, <NUM>, <NUM>, and <NUM> for SLC, MLC, TLC and QLC mode, respectively.

During an erase operation, all memory cells <NUM> in the same memory block <NUM> can be reset to the erased state ER as logic "<NUM>" by implementing a negative voltage difference between the control gates <NUM> and source terminals of the memory cells (e.g., the array common source <NUM>) such that all the trapped electronic charges in the storage layer of the memory cells <NUM> can be removed. For example, the negative voltage difference can be induced by setting the control gates <NUM> of the memory cells <NUM> to ground, and applying a high positive voltage to the array common source <NUM>. In some embodiments, an incremental step pulse erase (ISPE) scheme can be used for the erase operation. In this example, a voltage pulse can be applied to the memory cells in an erase loop, where a magnitude of the voltage pulse, i.e., the erase voltage Verase, can be increased incrementally by an erase step voltage Vstep_ers in subsequent erase loops.

After the erase operation, an erase verification operation can be performed to determine if the memory cells are at the state ER, or if the erase operation is completed successfully. An erase verification voltage EV can be applied to the word lines of the memory cells to compare with the threshold voltages of the memory cells. If the erase verification voltage EV is higher than the threshold voltage of the memory cell, it can be determined that the memory cell is at the state ER. If all the memory cells in the memory block are at the state ER, it can be considered that the memory block passes the erase verification. If a predetermined number of memory cell are not at the state ER, it can be considered that the memory block fails the erase verification. The erase and erase verification operations can be performed for the memory cells again in a next erase loop, where the erase voltage Verase can be increased by the erase step voltage Vstep_ers.

To perform the erase operation, the erase voltage Verase can be applied to an n-well in the substrate that is shared by all the memory cells in the same memory block. In some embodiments, the erase voltage Verase can be applied to the ACS <NUM> as shown in <FIG>. In some embodiments, the NAND flash memory <NUM> can have a three-dimensional structure, for example, as the 3D NAND flash memory <NUM> shown in <FIG>. In this example, the NAND flash memory can also include an additional transistor at each end of the memory string, where the additional transistor introduces gate-induced drain leakage (GIDL) to assist the erase operation.

<FIG> illustrates a 3D NAND flash memory <NUM>, according to some embodiments of the present disclosure. The 3D NAND flash memory <NUM> can be a portion of a memory block <NUM> in <FIG>. Similar to the 3D NAND flash memory <NUM> in <FIG>, the 3D NAND flash memory <NUM> also includes the film stack <NUM> of alternating conductive and dielectric layers and a plurality of memory strings <NUM> having a plurality of vertically stacked memory cells <NUM>. During an erase operation, the word lines <NUM> for all the memory cells <NUM> in the same memory block can be grounded, and the erase voltage Verase can be applied to the bit lines <NUM> on top of the memory strings <NUM> and to a source line (SL) <NUM> at bottom of the memory strings. The SL <NUM> can be shared by all the memory strings <NUM> and all the memory cells <NUM> in the same memory block. In one example, the SL <NUM> can be connected to the ACS <NUM>.

The SL <NUM> can be coupled to the channel layer <NUM> of the memory string <NUM> through a SL contact <NUM>. The bit line (BL) <NUM> can be coupled to the channel layer <NUM> through a BL contact <NUM>. In some embodiments, the SL contact <NUM> and the BL contact <NUM> comprise polycrystalline silicon. In some embodiments, the SL contact <NUM> and the BL contact <NUM> can be doped with an n-type dopant, for example, phosphine or arsenic.

The 3D NAND flash memory <NUM> also includes multiple select gates, for example, BSG <NUM>-<NUM>, BSG <NUM>-<NUM>, TSG <NUM>-<NUM> and TSG <NUM>-<NUM>, where at least one select gate (e.g., BSG <NUM>-<NUM> and TSG <NUM>-<NUM>) at each end of the memory string <NUM> can be controlled such that a GIDL current can be generated and charge carriers (e.g., holes) can be injected from the SL <NUM> and the BL <NUM> to the channel layer <NUM> during an erase operation. As such, electrical potential of the channel layer <NUM> along the memory string <NUM> can be raised to a voltage close to or equal to the erase voltage Verase applied on the SL <NUM> and the BL <NUM>. As described previously, a negative voltage bias between the word line <NUM> and corresponding channel layer <NUM> can remove trapped charge carriers (e.g., electrons) in the memory film <NUM> and thereby reduce the threshold voltage of corresponding memory cell <NUM>. After the erase and erase verification operation complete, i.e., after the memory cell is reset to the erase state ER, the stored data in the memory cell are erased accordingly. In this example, the erase operation can be assisted by the gate-induced-drain-leakage (GIDL) current flowing through the bit line and the source line of the memory device.

<FIG> also illustrates a first discharge circuit <NUM> for a 3D NAND flash memory, according to some embodiments of the present disclosure. The first discharge circuit <NUM> can be a portion of the peripheral circuit shown in <FIG> and can be fabricated in the peripheral region. The first discharge circuit <NUM> can be coupled to the 3D NAND flash memory <NUM> to discharge the 3D NAND flash memory <NUM>, for example, the bit line <NUM> and the SL <NUM>, after an erase operation.

The first discharge circuit <NUM> includes a discharge transistor <NUM>. The discharge transistor <NUM> can be a metal-oxide-semiconductor field-effect-transistor (MOSFET). In some embodiments, the discharge transistor <NUM> can be an n-channel MOSFET. A drain terminal (DS_D) of the discharge transistor <NUM> can be connected to the BL <NUM>, which can be connected to its corresponding page buffer/sense amplifier <NUM>. A source terminal (DS_S) of the discharge transistor <NUM> can be connected to the SL <NUM>, which can be connected to the ACS <NUM> and a current source <NUM> via a first switch <NUM>. The current source <NUM> can be used to regulate a discharge current flowing through to ground. In some embodiments, the current source <NUM> can be a flexible limited current source. A gate terminal (DS_GT) of the discharge transistor <NUM> can be grounded via a second switch <NUM>.

In some embodiments, the discharge transistor <NUM> can be included as a component in the page buffer/sense amplifier <NUM>. In this example, each BL <NUM> is connected to one discharge transistor <NUM> at its drain terminal DS_D. All the discharge transistors <NUM> in the entire memory block can be connected at the source terminals DS_S to the shared SL <NUM>. The gate terminals DS_GT of all the discharge transistors <NUM> in the same memory block can also be connected together to the second switch <NUM>.

<FIG> illustrate waveforms 400A and 400B used for erase and discharge operations of a 3D NAND flash memory, according to some embodiments of the present disclosure. Each erase operation is followed by the discharge operation. During the erase operation, the first switch <NUM> can be switched off, and the erase voltage Verase can be applied to the SL <NUM>. The gate terminal DS_GT of the discharge transistor <NUM> can be applied with a switch-on voltage VGG to switch on the discharge transistor <NUM> such that the source terminal DS_S and the drain terminal DS_D of the discharge transistor <NUM> are electrically connected. Connected to the drain terminal DS_D of the discharge transistor <NUM>, the BL <NUM> is thereby also connected to the source terminal DS_S and the SL <NUM>, and is applied with the erase voltage Verase. In some embodiments, the erase voltage Verase can be in a range between about <NUM> V to about <NUM> V. For an n-type MOSFET, to switch on the discharge transistor <NUM>, the switch-on voltage VGG is higher than the erase voltage Verase applied on the source terminal DS_S. The switch-on voltage VGG can be in a range between about <NUM> V to about <NUM> V. During the erase operation and the discharge operation, word lines <NUM> (not shown in <FIG>) can be grounded. In the example that each BL <NUM> is connected to one discharge transistor <NUM>, the plurality of discharge transistors <NUM> can be switched on during the erase operation such that the plurality of bit lines <NUM> can be connected to the source line <NUM> during the erase operation, where the plurality of bit lines <NUM> and the source line <NUM> can be applied with the erase voltage Verase during the erase operation. The gate-induced-drain-leakage (GIDL) current can flow through each bit line and the source line into the channel layer of each memory string to assist the erase operation.

During the discharge operation, the first switch <NUM> can be switched on such that the source terminal DS_S of the discharge transistor <NUM> can be grounded through the current source <NUM>, for example a flexible limited current source. The current source <NUM> can regulate the discharge current flowing through and thereby regulate the discharge rate of the SL <NUM>. As shown in both waveforms 400A and 400B, at the end of the discharge operation, an electrical potential VSL of the SL <NUM> can be reduced to <NUM> V.

During the discharge operation, the BL <NUM> can be connected to the SL <NUM> and ground when the discharge transistor <NUM> is switched on. Namely, the BL <NUM> can be discharged simultaneously with the SL <NUM> through the discharge transistor <NUM>.

At the end of the discharge operation, the discharge transistor <NUM> can be switched off by switching on the second switch <NUM> to connect the gate terminal DS_GT to ground. However, timing of switching off the discharge transistor <NUM> during the discharge operation can impact the performance and reliability of the discharge transistor <NUM>.

In <FIG>, the second switch <NUM> is switched on at the same time when the first switch <NUM> is switched on. Because the gate terminal DS_GT is grounded when the second switch <NUM> is switched on, the discharge transistor <NUM> can be switched off. In this example, an electrical potential VBL of the BL <NUM> is still at a high level (e.g., close to the erase voltage Verase) when the discharge transistor <NUM> is switched off. Because the fast discharge path through the discharge transistor <NUM> is turned off, the electrical potential VBL of the BL <NUM> remains at the high level, as shown in waveform 400A. Because the drain terminal DS-D of the discharge transistor <NUM> is connected to the BL <NUM>, the drain terminal DS-D of the discharge transistor <NUM> and the BL <NUM> are at the same electrical potential VBL. Therefore, after the SL <NUM> drops to <NUM> V, there is a high electrical potential difference between the drain terminal DS_D and the source terminal DS_S of the discharge transistor <NUM>, which can cause breakdown of source/drain junctions. As the discharge transistor <NUM> is scaled down to a smaller dimension, a source/drain breakdown voltage of the discharge transistor <NUM> is decreasing. Therefore, if switching off the discharge transistor <NUM> too early, the high electrical potential difference between source and drain terminals can cause breakdown of the source/drain junctions of the discharge transistor <NUM>.

In <FIG>, the second switch <NUM> is switched on when the SL <NUM> is dropping to <NUM> V. In this example, the discharge transistor <NUM> remains switching on when the electrical potential VSL of the SL <NUM> is decreasing from the erase voltage Verase to <NUM> V. Because the BL <NUM> is electrically connected to the SL <NUM> through the discharge transistor <NUM> when the discharge transistor <NUM> is switched on, the electrical potential VBL of the BL <NUM> follows the electrical potential VSL of the SL <NUM> and drops to <NUM> V at the same discharge rate. Although the source and drain of the discharge transistor <NUM> are at the same electrical potential in this example, there is a large voltage difference between the gate terminal DS_GT and the source/drain terminal DS_S/DS_D, which can induce Fowler-Nordheim (FN) stress to a gate dielectric of the discharge transistor <NUM>. A threshold voltage of the discharge transistor <NUM> can increase accordingly, and performance and reliability of the discharge transistor <NUM> can decrease as a result.

<FIG> illustrates a second discharge circuit <NUM> for a 3D NAND flash memory, according to some embodiments of the present disclosure. The second discharge circuit <NUM> is similar to the first discharge circuit <NUM>, and can be coupled to the 3D NAND flash memory <NUM>. The difference and improvement of the second discharge circuit <NUM> over the first discharge circuit <NUM> will be described in detail below.

Different from the first discharge circuit <NUM>, the second discharge circuit <NUM> also includes a SL detect circuit <NUM>, which is connected to the SL <NUM> and the source terminal DS_S of the discharge transistor <NUM>. The SL detect circuit <NUM> is further connected to the current source <NUM> (e.g., a flexible limited current source) via the first switch <NUM>.

The second discharge circuit <NUM> also includes a gate discharge circuit <NUM>, which is connected to the gate terminal DS_GT of the discharge transistor <NUM>. The gate discharge circuit <NUM> is also connected to the SL detect circuit <NUM> via a third switch <NUM>.

<FIG> illustrates a waveform <NUM> used for the second discharge circuit <NUM>, according to some embodiments of the present disclosure. The waveform <NUM> depicts the erase and discharge operations performed to the 3D NAND flash memory <NUM> with the support from the second discharge circuit <NUM>. The erase operation represented by the waveform <NUM> is also followed by the discharge operation. The erase operation of the waveform <NUM> is similar to waveforms 400A and 400B, as described with respect to <FIG>.

During the discharge operation, timing for discharging the gate terminal DS_GT of the discharge transistor <NUM> can be controlled through the second discharge circuit <NUM> such that the discharge transistor <NUM> will not suffer FN stress or source/drain junction breakdown.

<FIG> illustrates a method <NUM> for discharging a 3D NAND flash memory after an erase operation, according to some embodiments of the present disclosure. It should be understood that the method <NUM> is not exhaustive and that other operation steps can be performed as well before, after, or between any of the illustrated operation steps. In some embodiments, some operation steps of method <NUM> can be omitted or other operation steps can be included, which are not described here for simplicity. In some embodiments, operation steps of method <NUM> can be performed in a different order and/or vary.

Referring to <FIG>, the following operation steps can be implemented as an example for discharging the 3D NAND flash memory <NUM> through the second discharge circuit <NUM> after the erase operation.

First, during the erase operation and before the discharge operation, all switches, i.e., the first switch <NUM>, the second switch <NUM> and the third switch <NUM> of the second discharge circuit <NUM> are switched off. The erase voltage Verase can be applied to the SL <NUM>. The switch-on voltage VGG can be applied to the gate terminal DS_GT of the discharge transistor <NUM> to switch on the discharge transistor <NUM>. As such, the BL <NUM> can be connected to the SL <NUM> and can also be applied with the erase voltage Verase. At the end of the erase operation, the erase voltage Verase and the switch-on voltage VGG can be removed from the SL <NUM> and the gate terminal DS_GT, respectively.

At the beginning of the discharge operation (i.e., time T0 in <FIG>), as shown at operation step <NUM>, the SL <NUM> can be grounded by switching on the first switch <NUM>. In the other words, a zero volt (<NUM> V) can be applied to the SL <NUM>. The source terminal DS_S of the discharge transistor <NUM> is connected to the SL <NUM> and thereby the source terminal DS_S of the discharge transistor <NUM> is kept at the same electrical potential VSL and is discharged simultaneously with the SL <NUM>. The current source <NUM>, connected between the first switch <NUM> and the ground, can regulate the discharge current flowing through and thereby regulate the discharge rate of the SL <NUM>. In some embodiments, the current source <NUM> can be a flexible limited current source. As shown in <FIG>, the electrical potential VSL of the SL <NUM> drops from the erase voltage Verase at the time T0 to <NUM> V at the end of the discharge operation with a slope representing its discharge rate.

The third switch <NUM> can be switch on at the same time as the first switch <NUM>, i.e., at the time T0, to form an electrical connection from the gate terminal DS_GT of the discharge transistor <NUM> to the SL <NUM> through the gate discharge circuit <NUM>. As shown in operation step S720, a constant voltage difference Vg_Vs can be provided and maintained between the gate terminal DS_GT of the discharge transistor <NUM> and the SL <NUM> by the gate discharge circuit <NUM>. In some embodiments, the constant voltage difference Vg_Vs can be higher than the threshold voltage of the discharge transistor <NUM> such that the discharge transistor <NUM> can be switched on. In some embodiments, the constant voltage difference Vg_Vs can be in a range between about <NUM> V to about <NUM> V. In some embodiments, the constant voltage difference Vg_Vs is <NUM> V. To avoid causing FN stress on the discharge transistor <NUM>, the constant voltage difference Vg_Vs can be selected to remain smaller an FN stress voltage, for example, <NUM> V.

Thus, at operation step S720, the BL <NUM> and the gate terminal DS_GT can be discharged at the same discharge rate as the SL <NUM>. Shown in <FIG>, an electrical potential VGT of the gate terminal DS_GT and the electrical potential VBL of the BL <NUM> drop from the switch-on voltage VGG and the erase voltage Verase, respectively, at the time T0, with the same slope as the SL <NUM>. Because the BL <NUM> and the SL <NUM> are electrically connected at about the same electrical potential, source/drain junction breakdown can also be avoided during this period.

At operation step S740, the electrical potential VSL of the SL <NUM> can be compared with a first predetermined value VF1 by the SL detect circuit <NUM>. In some embodiments, to reduce distress to the gate dielectric of the discharge transistor <NUM>, the first predetermined value VF1 can be selected in a range between, for example, 3V and 5V.

At operation step S740, it is determined whether the electrical potential VSL of the SL <NUM> is smaller or lower than the first predetermined value VF1. If the electrical potential VSL of the SL <NUM> is not lower than the first predetermined value VF1, the operation steps S720 and S730 can be repeated.

When the electrical potential VSL of the SL <NUM> falls below the first predetermined value VF1, for example, at time T1, the third switch <NUM> can be switched off according to operation step S750. As a result, the gate terminal DS_GT of the discharge transistor <NUM> can be floating. Namely, there is no external bias applied on the gate terminal DS_GT. Due to capacitive coupling effect, the electrical potential VGT of the gate terminal DS_GT follows the electrical potential VSL of the SL <NUM>. The gate terminal DS_GT continues discharging, but at a discharge rate slower than the SL <NUM>. In the meantime, the discharge transistor <NUM> remains switched-on such that the BL <NUM> can continue to be discharged through the discharge transistor <NUM>.

At operation step S760, the electrical potential VSL of the SL <NUM> can be compared with a second predetermined value VF2 by the SL detect circuit <NUM>.

At operation step S770, it is determined whether the electrical potential VSL of the SL <NUM> is smaller or lower than the second predetermined value VF2. If the electrical potential VSL of the SL <NUM> is not lower than the second predetermined value VF2, the operation steps S750 and S760 can be repeated.

When the electrical potential VSL of the SL <NUM> falls below the second predetermined value VF2, for example, at time T2, the second switch <NUM> can be switched on according to operation step S780. As a result, the gate terminal DS_GT is grounded, i.e., is applied with 0V. The gate terminal DS_GT can thus be quickly discharged to 0V. The discharge transistor <NUM> is switched off accordingly.

The second predetermined value VF2 can be smaller than the first predetermined valve VF1. In some embodiments, to avoid source/drain junction breakdown, the second predetermined value VF2 can be selected to below a source/drain junction breakdown voltage. In some embodiments, the second predetermined value VF2 can be between <NUM>. 5V and 3V, for example, e.g. the second predetermined value VF2 can be 1V or 2V. Therefore, even after the discharge transistor <NUM> is switched off, without a quick discharge path, the electrical potential VBL of the BL <NUM> can be controlled to below the source/drain junction breakdown voltage.

At the end of the discharge operation, the first, second and third switches <NUM>/<NUM>/<NUM> in the second discharge circuit <NUM> can be switched off.

<FIG> illustrate schematic diagrams 800A and 800B of the gate discharge circuit <NUM>, according to some embodiments of the present disclosure. As described previously, the gate discharge circuit <NUM> can maintain the constant voltage different Vg_Vs between the electrical potential VGT of the gate terminal DS_GT and the electrical potential VSL of the SL <NUM> shown in <FIG>. The gate discharge circuit <NUM> can be designed in the peripheral circuit of a 3D NAND flash memory.

In <FIG>, the gate discharge circuit <NUM> includes a switch transistor <NUM> and a voltage level shifter <NUM>. A source terminal of the switch transistor <NUM> can be connected to the SL <NUM> (not shown in <FIG>) at the electrical potential VSL. As shown in <FIG>, the third switch <NUM> can be inserted between the SL <NUM> and the gate discharge circuit <NUM>. In some embodiments, the switch transistor <NUM> can be implemented as the third switch <NUM>. In some embodiments, the switch transistor <NUM> can be implemented in addition to the third switch <NUM>. The switch transistor <NUM> can be switched on or off through the voltage level shifter <NUM> connected to a gate terminal of the switch transistor <NUM>. The voltage level shifter <NUM> can transform the electrical potential VGT at the gate terminal DS_GT of the discharge transistor <NUM> to a switching voltage Vsw for switching on the switch transistor <NUM>. The voltage level shifter <NUM> can also be controlled by an enablement signal dis_en to determine when the switching voltage Vsw can be provided to the switching transistor <NUM>. A switching current ISW flowing through the switching transistor <NUM> can be determined by the switching voltage Vsw.

In <FIG>, the gate discharge circuit <NUM> also includes a set of MOSFETs <NUM> connected in series. A first end of the set of MOSFETs <NUM> can be connected to a drain terminal of the switching transistor <NUM> and a second end of the set of MOSFETs <NUM> can be connected to the gate terminal DS_GT of the discharge transistor <NUM> at the electrical potential VGT. Each of the set of MOSFETs <NUM> can be configured as an effective diode - a gate terminal can be connected to a drain terminal. As such, each of the set of MOSFETs can operation in its saturation mode. A voltage drop across each of the set of MOSFETs <NUM> depends on the switching current ISW which is controlled by the switching transistor <NUM>. A total voltage drop across the set of MOSFETs <NUM> from the first end to the second end can determine the constant voltage difference Vg_Vs between the electrical potentials VGT and VSL. In addition, each of the set of MOSFETs <NUM> can be bypassed by a parallel switch (e. g, switch S1, S2,. ) such that the constant voltage difference Vg_Vs between the electrical potentials VGT and VSL can be adjusted.

The set of MOSFETs <NUM> can include p-channel MOSFETs or n-channel MOSFETs. In <FIG>, p-channel MOSFETs are illustrated as an example. To reduce body-bias effect, it is preferred that a body of each MOSFET can be tied to a source terminal of the MOSFET. Since the body of a p-channel MOSFET is in an n-well and can be tied to its source terminal easily, it is preferred that p-channel MOSFETs can be used in the set of MOSFETs <NUM> instead of n-channel MOSFETs.

In <FIG>, the gate discharge circuit <NUM> can also include a set of diodes <NUM> connected in series. A first end of the set of diodes <NUM> can be connected to the drain terminal of the switching transistor <NUM>, and a second end of the set of diodes <NUM> can be connected to the gate terminal DS_GT of the discharge transistor <NUM> at the electrical potential VGT. A voltage drop across each of the set of diodes <NUM> depends on the switching current ISW that is controlled by the switching transistor <NUM>. A total voltage drop across the set of diodes <NUM> from its first end to the second end can determine the constant voltage difference Vg_Vs between the electrical potentials VGT and VSL. In addition, each of the set of diodes <NUM> can also be bypassed by the parallel switch (e. g, switch S1, S2,. ) such that the constant voltage difference Vg_Vs between the electrical potentials VGT and VSL can be adjusted. However, because a diode usually occupies larger area than a MOSFET, to reduce cost, it is preferred that p-channel MOSFETs can be used for the gate discharge circuit <NUM> instead of diodes.

<FIG> illustrates a schematic diagram <NUM> of the SL detect circuit <NUM>, according to some embodiments of the present disclosure. As discussed previously, the SL detect circuit <NUM> can compare the electrical potential VSL of the SL <NUM> with a predetermined value (e.g., the first predetermined value VF1 or the second predetermined value VF2).

The SL detect circuit <NUM> includes an operational amplifier <NUM>, which has a negative input and a positive input. The negative input of the operational amplifier <NUM> can be connected to a reference voltage VREF or a input voltage VIN. Switches SS0 and SS1 can be used to select the reference voltage VREF or the input voltage VIN. In some embodiments, the operational amplifier <NUM> is a comparator.

The SL detect circuit <NUM> also includes a resistive voltage divider <NUM> that has a first resistor <NUM> connected in series with a second resistor <NUM>. The first resistor <NUM> has a resistance R0 and the second resistor <NUM> has a resistance R1 that can be adjusted. In some embodiments, the second resistor <NUM> is a potentiometer. The resistive voltage divider <NUM> is connected in parallel with a capacitor <NUM>, where first ends <NUM> of the resistive voltage divider <NUM> and the capacitor <NUM> are connected together to the positive input of the operational amplifier <NUM> via a switch SS4. Second ends of the resistive voltage divider <NUM> and the capacitor <NUM> are both grounded. The capacitor <NUM> has a capacitance C<NUM>. An intermediate point <NUM> between the first resistor <NUM> and the second resistor <NUM> is connected to the positive input of the operational amplifier <NUM> via a switch SS2.

As shown in <FIG>, the SL detect circuit <NUM> also includes a pull-up transistor <NUM>. In some embodiments, the pull-up transistor <NUM> is a p-channel MOSFET, where a drain terminal of the pull-up transistor <NUM> is connected to the first ends of the resistive voltage divider <NUM> and the capacitor <NUM> via a switch SS3, and a source terminal of the pull-up transistor <NUM> is connected to a power supply VDD. A gate terminal of the pull-up transistor <NUM> is connected to an output of the comparator with an output voltage VOUT.

Initially, the predetermined value (e.g., the first predetermined value VF <NUM> and the second predetermined value VF2) used in the method <NUM> for the discharge operation can be set to the SL detect circuit <NUM>. Next, the input voltage VIN, e.g., the electrical potential VSL of the SL <NUM>, can be compared with the first predetermined value VF <NUM> and then the second predetermined value VF2.

<FIG> illustrates a method <NUM> to set the predetermined value (e.g., the first predetermined value VF <NUM> or the second predetermined value VF2) to the SL detect circuit <NUM>, according to some embodiments of the present disclosure. It should be understood that the method <NUM> is not exhaustive and that other operation steps can be performed as well before, after, or between any of the illustrated operation steps. In some embodiments, some operation steps of method <NUM> can be omitted or other operation steps can be included, which are not described here for simplicity. In some embodiments, operation steps of method <NUM> can be performed in a different order and/or vary.

Referring to <FIG> and <FIG>, at operation step <NUM>, the switch SS0 can be switched on, and the switch SS1 can be switched off. As a result, the negative input of the operational amplifier <NUM> is at the reference voltage VREF.

At operation step <NUM>, the switches SS2 and SS3 can be switched on, and the switch SS4 can be switched off. As a result, the positive input of the operational amplifier <NUM> is connected to the intermediate point <NUM> of the resistive voltage divider <NUM>, which is at an electrical potential V<NUM>. An external feedback loop is formed from the output of the operational amplifier <NUM> through the pull-up transistor <NUM> and the resistive voltage divider <NUM> to the positive input of the operational amplifier <NUM>. Due to a high gain of an operational amplifier, the voltage difference between the positive and negative inputs can be about zero. Accordingly, the electrical potential V<NUM> at the intermediate point <NUM> can be set to the reference voltage VREF, i.e., V<NUM>=VREF.

At operation step <NUM>, through the resistive voltage divider <NUM> and the pull-down transistor <NUM>, an electrical potential V<NUM> at the first ends <NUM> of the resistive voltage divider <NUM> and the capacitor <NUM> can be determined as <MAT>. As such, by adjusting the resistance R1 of the second resistor <NUM>, or a resistive ratio between the resistances R1 and R0, the electrical potential V<NUM> can be set to the predetermined value, for example, the first predetermined value VF1 or the second predetermined value VF2.

At operation step <NUM>, the capacitor <NUM>, connected in parallel with the resistive voltage divider <NUM>, is charged to the electrical potential V1 through the pull-up transistor <NUM> and the power supply VDD. Accordingly, the electrical potential V1, i.e., the first predetermined value VF1 or the second predetermined value VF2, can be held by the capacitor <NUM> once the power supper VDD is disconnected.

As described above, in the method <NUM>, the operational amplifier <NUM> is configured as a voltage buffer, where an input voltage can be mirrored or followed at an output.

<FIG> illustrates a method <NUM> to compare the input voltage VIN (e.g., the electrical potential VSL of the SL <NUM>) with the predetermined value (i.e., the electrical potential V1, e.g., the first predetermined value VF1 or the second predetermined value VF2), according to some embodiments of the present disclosure. It should be understood that the method <NUM> is not exhaustive and that other operation steps can be performed as well before, after, or between any of the illustrated operation steps. In some embodiments, some operation steps of method <NUM> can be omitted or other operation steps can be included, which are not described here for simplicity. In some embodiments, operation steps of method <NUM> can be performed in a different order and/or vary.

Referring to <FIG> and <FIG>, at operation step <NUM>, the switches SS2 and SS3 can be switched off, and the switches SS4 can be switched on. After the power supply VDD is disconnected from the resistive voltage divider <NUM> and the capacitor <NUM>, the electrical potential V1 (e.g., the first predetermined value VF1 or the second predetermined value VF2), held by the capacitor <NUM>, can be connected to the positive input of the operational amplifier <NUM>.

At operation step <NUM>, the switch SS0 can be switched off and the switch SS1 can be switched on. Accordingly, the input voltage VIN can be connected to the negative input of the operational amplifier <NUM>.

At operation step <NUM>, the input voltage VIN can be compared with the electrical potential V1 by the operational amplifier <NUM>. Here, the operational amplifier <NUM> is configured as a comparator, where voltages at its two inputs can be compared.

At operation step <NUM>, it is determined whether the input voltage VIN is lower than the electrical potential V1 or not.

At operation step <NUM>, when the input voltage VIN is lower than the electrical potential V1 (e.g., the first predetermined value VF1 or the second predetermined value VF2), the output voltage VOUT can be positive or logic "<NUM>.

At operation step <NUM>, when the input voltage VIN is higher than the electrical potential V1 (e.g., the first predetermined value VF1 or the second predetermined value VF2), the output voltage can be negative or logic "<NUM>.

As described above, by adding the gate discharge circuit <NUM> to provide the constant voltage difference Vg_Vs between the gate terminal DS_GT of the discharge transistor <NUM> and the SL <NUM>, and by introducing the SL detect circuit <NUM> to compare the electrical potential VSL of the SL <NUM> with the first predetermined value VF <NUM> and the second predetermined value VF2, the discharge operation for the 3D NAND flash memory can be optimized. First, the discharge transistor <NUM> remains switched on to discharge the BL <NUM>. By maintaining the constant voltage different Vg_Vs between the gate terminal DS_GT of the discharge transistor <NUM> and the SL <NUM>, a high voltage difference between the source terminal DS_S and the drain terminal DS_D can be avoided. Thus, source/drain junction breakdown of the discharge transistor <NUM> can be avoided. The constant voltage difference Vg_Vs can also be used to avoid causing FN stress to the gate dielectric of the discharge transistor <NUM>. Second, when discharging the gate terminal DS_S of the discharging transistor <NUM>, source/drain junction breakdown or FN stress can also be avoided by comparing the electrical potential VSL of the SL <NUM> with the first predetermined value VF1 and the second predetermined value VF2.

It is noted that the discharging methods and circuits described in the present disclosure are not limited to a three-dimensional NAND flash memory or a NAND flash memory. Any system having a discharge operation can adapt the methods and circuits described above to achieve improved performance and reliability.

In summary, the present disclosure provides a discharge circuit for discharging a memory device after an erase operation. The discharge circuit includes a discharge transistor, connecting a bit line and a source line of the memory device. The discharge circuit also includes a source line detect circuit, connected to the source line and configured to compare an electrical potential of the source line with a predetermined value. The discharge circuit further includes a gate discharge circuit, configured to maintain a constant voltage difference between the discharge transistor and the source line, wherein the constant voltage difference applied to the discharge transistor and the source line switches on the discharge transistor.

The present disclosure also provides a method for discharging a memory device after an erase operation. The method comprises grounding a source line of the memory device; and switching on a discharge transistor to connect a bit line of the memory device to the source line by maintaining a constant voltage difference between a gate terminal of the discharge transistor and the source line. The method also includes comparing an electrical potential of the source line with a first predetermined value; and floating the gate terminal of the discharge transistor when the electrical potential of the source line is lower than the first predetermined value.

The present disclosure further provides a memory device having a memory block and a peripheral circuit. The memory block includes a plurality of memory strings connected to a source line and a plurality of bit lines. The peripheral circuit includes a discharge circuit configured to discharge the memory block after an erase operation. The discharge circuit includes a plurality of discharge transistors. Each discharge transistor is configured to connect the source line to a corresponding bit line. The discharge circuit also includes a source line detect circuit connected to the source line and configured to compare an electrical potential of the source line with a predetermined value. The discharge circuit further includes a gate discharge circuit, configured to maintain a constant voltage difference between gate terminals of the plurality of discharge transistors and the source line.

The foregoing description of the specific embodiments will so fully reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt, for various applications, such specific embodiments, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the disclosure and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the disclosure and guidance.

The Summary and Abstract sections can set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

Claim 1:
An erasable memory device, comprising:
a memory block (<NUM>), comprising a plurality of memory strings (<NUM>) connected to a source line (<NUM>) and a plurality of bit lines (<NUM>); and
a peripheral circuit, comprising:
a discharge circuit (<NUM>, <NUM>) configured to discharge the memory block (<NUM>) after an erase operation, the discharge circuit (<NUM>, <NUM>) comprising:
a plurality of discharge transistors (<NUM>), wherein each of the plurality of discharge transistors (<NUM>) is configured to connect the source line (<NUM>) to a corresponding bit line (<NUM>);
a source line detect circuit (<NUM>) connected to the source line (<NUM>) and comparing an electrical potential (VSL, VGT) of the source line (<NUM>) with a
predetermined value; and
a gate discharge circuit (<NUM>) maintaining a constant voltage difference (Vg_Vs) between gate terminals (DS_GT) of the plurality of discharge transistors (<NUM>) and the source line (<NUM>),
wherein the plurality of discharge transistors are switched on during the erase operation such that the plurality of bit lines are connected to the source line.