Patent Description:
The invention discloses A method for a FMCW radar system, the method comprising: transmitting, by a transmit channel of the radar system, a frame comprising first, second, and third chirps, each chirp having a chirp start frequency, wherein the chirp start frequency of the transmitted chirps is dithered; and receiving, by a receive channel of the radar system, a frame of reflected chirps based on the transmitted frame, and generating a digital intermediate frequency IF signal, wherein each first, second, and third reflected chirp has a sampling window start time, the method further comprising dithering the sampling window start time of the reflected chirps such that the effective start frequency of the sampling window is approximately the same from chirp to chirp. The invention further discloses A FMCW radar system, comprising: a radar transceiver integrated circuit IC, comprising: a timing engine configured to generate one or more chirp control signals for controlling generation of chirps in the radar transceiver IC; a local oscillator coupled to the timing engine, the local oscillator configured to: receive the one or more chirp control signals; and generate a frame comprising first, second, and third chirps, each chirp having a chirp start frequency, wherein the frame further has an idle time between the chirps; and a control module coupled to the timing engine, the control module configured to dither the start frequencies of the chirps and is further configured to dither a sampling window start time of reflected chirps received from an analog-to-digital converter ADC such that the effective start frequency for the ADC sampling window is approximately the same from chirp to chirp.

Frequency-modulated continuous wave (FMCW) radar systems may be embedded in multiple usage applications, such as industrial applications, automotive applications, and the like. For example, an embedded FMCW radar system may be included in a vehicle to provide data for use in adaptive cruise control, collision warning, blind spot assist/warning, lane change assist, and parking assist. In other examples, embedded FMCW radar systems in industrial applications may provide data to aid in navigating autonomous equipment in a factory and in tracking movement.

FMCW radar systems may transmit a frame containing a series of frequency ramps referred to as chirps. These chirps may be reflected by a subject object back to the FMCW radar system. After receipt of a signal containing the reflected chirps, the FMCW radar system may down-convert, digitize, and process the received signal to determine characteristics of the subject object. These characteristics can include range, velocity, angle of arrival, etc., of the subject object when the subject object is in view of the FMCW radar system.

In at least some FMCW radar systems, multiple sequences of chirps (e.g., such as consecutive sequences of equally spaced chirps) are transmitted and reflections of these chirps received to generate radar signals. After each sequence of chirps, there may be some idle time (e.g., inter-frame idle time) to allow for processing the radar signals resulting from the reflected chirps. The acquisition time of a sequence of chirps, and the subsequent inter-frame idle time, together may form a radar frame. In at least one example, the reflected signal received by each antenna of the FMCW radar system is mixed with the transmitted signal to generate an intermediate frequency (IF) signal that is filtered and digitized. Signal processing may then be performed on the resulting digital IF signals (e.g., one per receiving antenna in the FMCW radar system) to extract any one or more of the range, velocity, and/or angle of potential objects in the view of the radar. For example, an IF signal frequency may be proportional to an object's distance, while changes to an IF signal phase across chirps may indicate an object's velocity.

A spurious signal (spur) is an unintended signal that can result from harmonics, intermodulation, frequency conversion, or electromagnetic interference (EMI). A spur is inserted in the transmitter path as a fixed-frequency signal, for example, by a coupling of a higher-order harmonic of a clock signal to a voltage-controlled oscillator (VCO) or a low-noise amplifier (LNA). However, when a reflected, fixed-frequency spur is mixed with the transmitted signal (a chirp) to generate an IF signal, the resultant IF signal frequency changes with time, which may be erroneously construed as multiple targets at different distances. Further, the IF signal corresponding to a spur from a clock signal, for example, undergoes a continuous phase shift between chirps, and thus may also be erroneously construed as a target having a constant velocity. In summary, while the IF component corresponding to an object may have a fixed frequency, indicating an object at a particular distance, the IF component of the spur signal may have a varying frequency, erroneously indicating objects at varying distances. Similarly, while the IF component corresponding to the object may have a fixed phase, indicating a stationary object, the IF component of the spur signal may have a phase that shifts constantly over time, erroneously indicating objects with constant velocities.

In examples of the present disclosure, one or more FMCW transmitting and/or receiving parameters are dithered to reduce or mitigate the impact of spurs on analyzing object(s) in view of the FMCW radar system. According to the invention, the frequency at which the chirp begins (i.e., the frequency at which the frequency ramp begins) or a "chirp start frequency" is dithered from one chirp to the next, which effectively dithers the IF frequency of the spur component and dithers or breaks the consistency of the phase of the IF component of the spur signal. As a result, the IF component of the spur signal, which was already spread across multiple distance bins as explained above, is spread across velocity bins as well. Thus, the influence of the spur on subsequent object distance/velocity determinations is mitigated. However, the IF component corresponding to the object also leaks to different velocities, due to incoherence introduced by differences in the effective frequency at a sampling start time from chirp to chirp.

To address the foregoing, in addition to dithering the chirp start frequency, an analog-to-digital conversion (ADC) sampling window start time is also dithered from one chirp to the next. When the ADC sampling window of the receiver path starts at the same time relative to each chirp transmission, since the chirp frequency itself is being dithered, the effective start frequency for each ADC sampling window varies from chirp to chirp. To avoid signal incoherence, the ADC sampling window start time is dithered as well, such that the effective start frequency for the ADC sampling window is approximately the same from chirp to chirp. As a result, for objects that are stationary relative to the radar, the IF signal does not leak to other velocities. However, for objects that are moving relative to the radar, the IF signal erroneously leaks to other velocities due to a variable inter-chirp time introduced by the variable ADC sampling window start times.

To address the foregoing, in addition to dithering the chirp start frequency and the sampling window start time, in some examples an idle time between chirps (i.e., the time from ceasing transmission of one chirp to beginning transmission of a subsequent chirp) is also dithered. When the idle time between chirps is fixed, since the ADC sampling window start time is changing from chirp to chirp, the effective inter-chirp time (i.e., the time from beginning a first chirp sampling window to beginning a subsequent chirp sampling window) varies between chirps. In such a case, as a result of the variable effective inter-chirp times, the phase of the IF signal corresponding to any moving object becomes incoherent across chirps, rather than changing linearly, which is undesirable. In order to provide a more uniform inter-chirp time, the idle time between chirps is dithered as well. As a result, the erroneous leakage of the IF signal to other velocities is avoided for both stationary and moving objects, and the influence of the spur on subsequent object distance/velocity determinations remains mitigated as above. Further, in examples, the influence of synchronous spurs, asynchronous spurs, a set of multiple spurs, narrow-band noise, and other similar signals on subsequent object distance/velocity determinations is mitigated as well.

<FIG> shows a block diagram of an illustrative FMCW radar system <NUM>. The FMCW radar system <NUM> includes a radar transceiver IC <NUM> and a processing unit <NUM>. In some examples, the FMCW radar system <NUM> further includes a transmit antenna <NUM> and a receive antenna <NUM>, while in other examples, the FMCW radar system <NUM> does not include, but is configured to couple to, the transmit antenna <NUM> and the receive antenna <NUM>. An illustrative architecture of the radar transceiver IC <NUM> is illustrated in <FIG> and described below.

In at least one example, the radar transceiver IC <NUM> may be referred to as the front end of the FMCW radar system <NUM> and the processing unit <NUM> may be referred to as the back end of the FMCW radar system <NUM>. In at least one example, the radar transceiver IC <NUM> and the processing unit <NUM> are implemented separately and may be configured to couple together, while in other examples, the radar transceiver IC <NUM> and the processing unit <NUM> are implemented together, for example, in a single chip package. In at least one example, the processing unit <NUM> is coupled to the radar transceiver IC <NUM> via an interface <NUM> that may facilitate any suitable communication method (e.g., serial interface or parallel interface) and is configured to receive data from and/or transmit data to the radar transceiver IC <NUM>.

In at least one example, the interface <NUM> may be a high speed serial interface such as a low-voltage differential signaling (LVDS) interface. In another example, the interface <NUM> may be a lower speed interface such as a serial peripheral interface (SPI). In at least one example, the radar transceiver IC <NUM> includes functionality to generate one or more digital IF signals (alternatively referred to as de-chirped signals, beat signals, or raw radar signals) from reflected chirps received via the receive antenna <NUM>. Further, in at least one example, the radar transceiver IC <NUM> includes functionality to perform at least a portion of the signal processing of radar signals (e.g., the reflected chirps and/or the digital IF signals) received in the radar transceiver IC <NUM>, and to provide the results of this signal processing to the processing unit <NUM> via the interface <NUM>. In at least one example, the radar transceiver IC <NUM> performs a range fast Fourier transform (FFT) for each received frame (e.g., each sequence of chirps of the frame) of the radar transceiver IC <NUM>. In at least some examples, the radar transceiver IC <NUM> also performs a Doppler FFT for each received frame of the radar transceiver IC <NUM> (e.g., after performing, and on a result of, the range FFTs). The combination of the range FFTs and the Doppler FFTs may be referred to as a two-dimensional (2D) FFT (or 2D FFT processing).

In at least one example, the processing unit <NUM> includes functionality to process data received from the radar transceiver IC <NUM> to, for example, determine any one or more of a distance, velocity, and/or angle of any objects detected by the FMCW radar system <NUM>. In some examples, the processing unit <NUM> may also, or alternatively, include functionality to perform post-processing of information about the detected objects, such as tracking objects, determining rate and direction of movement, etc. In at least one example, the processing unit <NUM> determines a distance and velocity of a detected object, for example, according to aspects of the present disclosure in which parameters of the FMCW radar system <NUM> are dithered. Examples of this disclosure may include dithering a chirp start frequency from one chirp to the next, dithering an ADC sampling window start time from one chirp to the next, and dithering an idle time between chirps. As a result of dithering various parameters of the FMCW radar system <NUM>, IF signal leakage to other velocities is avoided for both stationary and moving objects, which mitigates the influence of spurious signals on object distance/velocity determinations. In various examples, the processing unit <NUM> includes any one or more suitable processors or combinations of processors as needed for processing data received from the radar transceiver IC <NUM> and or providing data to the radar transceiver IC <NUM>. For example, the processing unit <NUM> may include any one or more of a digital signal processor (DSP), a microcontroller, a system-on-a-chip (SOC) combining both DSP and microcontroller processing, a field-programmable gate array (FPGA), or any combination of the foregoing.

Referring now to <FIG>, a block diagram of an illustrative radar transceiver IC <NUM> is shown. In at least some examples, the radar transceiver IC <NUM> is suitable for implementation as the radar transceiver IC <NUM> of the FMCW radar system <NUM> of <FIG>. In other examples, the radar transceiver IC <NUM> is suitable for implementation in other radar systems. In at least one example, the radar transceiver IC <NUM> includes one or more transmit channels <NUM> and one or more receive channels 202A-202N (where N is any positive integer). Each of the transmit channels <NUM> and the receive channels 202A-202N may be individually coupled to a transmit antenna or a receive antenna, respectively, such as a transmit antenna <NUM> or a receive antenna <NUM>, as discussed above with respect to <FIG> and not shown in <FIG>. Although illustrated for the sake of simplicity as including two receive channels 202A and 202N and one transmit channel <NUM>, in various examples, the radar transceiver IC <NUM> may include any suitable number of receive channels 202N and/or any suitable number of transmit channels <NUM>. Additionally, the number of receive channels 202N and the number of transmit channels <NUM> may be different numbers.

In at least one example, a transmit channel <NUM> includes a power amplifier (PA) <NUM> coupled between a transmit antenna (not shown) and an I/Q modulator <NUM> to amplify an output of the I/Q modulator <NUM> for transmission via the transmit antenna. In at least some examples, each additional transmit channel <NUM> may be substantially similar and may couple to its own respective transmit antenna (not shown) or to the same transmit antenna.

In at least one example, a first receive channel 202A includes a low-noise amplifier (LNA) 203A coupled between a receive antenna (not shown) and a mixer 206A to amplify a radio frequency (RF) signal (e.g., reflected chirps) received via the receive antenna prior to providing the amplified signal to the mixer 206A. In at least one example, the mixer 206A is coupled to the clock multiplier <NUM> and configured to receive a clock signal from the clock multiplier <NUM>, for example, to mix with the received RF signal to generate an IF signal. In at least one example, a baseband bandpass filter 210A is coupled to the mixer 206A and configured to filter the IF signal, a variable gain amplifier (VGA) 214A is coupled to the baseband bandpass filter 210A and configured to amplify the filtered IF signal, and an analog-to-digital converter (ADC) 218A is coupled to the VGA 214A and configured to convert the analog IF signal to a digital IF signal. The baseband bandpass filter 210A, VGA 214A, and ADC 218A of a respective receive channel 202A may be collectively referred to as the analog baseband, the baseband chain, the complex baseband, or the baseband filter chain. Further, the baseband bandpass filter 210A and VGA 214A may be collectively referred to as an IF amplifier (IFA). In at least some examples, each additional receive channel 202N may be substantially similar to the first receive channel 202A and may couple to its own respective receive antenna (not shown) or to the same receive antenna. In at least one example, the ADC 218A is coupled to the digital front end (DFE) <NUM>, for example, to provide the digital IF signals to the DFE <NUM>. The DFE <NUM>, which may also be referred to as the digital baseband, includes in at least one example, functionality to perform decimation filtering or other processing operations on the digital IF signals, for example, to reduce the data transfer rate of the digital IF signals. In various examples, the DFE <NUM> may also perform other operations on the digital IF signals such as direct current (DC) offset removal and/or compensation (e.g., digital compensation) of non-idealities in the receive channels 202A-202N such as inter-receiver gain imbalance non-ideality, inter-receiver phase imbalance non-ideality and the like. In at least one example, the DFE <NUM> is coupled to a signal processor <NUM> and configured to provide the output of the DFE <NUM> to the signal processor <NUM>.

In at least one example, the signal processor <NUM> is configured to perform at least a portion of the signal processing on the digital IF signals resulting from a received radar frame and to transmit the results of this signal processing via terminal <NUM> and/or terminal <NUM>. In at least one example, the signal processor <NUM> transmits the results of the signal processing to a processing unit (not shown), such as the processing unit <NUM> described above with respect to <FIG>. In various examples, the results are provided from the signal processor <NUM> to the terminal <NUM> and/or the terminal <NUM> via the high speed interface <NUM> and/or the SPI <NUM>, respectively. In at least one example, the signal processor <NUM> performs the range FFT on each sequence of chirps in the received radar frame to generate a range array. In at least one example, the signal processor <NUM> additionally performs the Doppler FFT on results of the range FFTs to generate a range-Doppler array.

The signal processor <NUM> may include any suitable processor or combination of processors. For example, the signal processor <NUM> may be a DSP, a microcontroller, a FFT engine, a DSP plus microcontroller processor, a FPGA, or an application specific integrated circuit (ASIC). In at least one example, the signal processor <NUM> is coupled to memory <NUM>, for example, to store intermediate results of the portion of the signal processing performed on the digital IF signals in the memory <NUM> and/or to read instructions from the memory <NUM> for execution by the signal processor <NUM>.

The memory <NUM>, in at least one example, provides on-chip storage (e.g., a computer readable medium) which may be used, for example, to communicate data between the various components of the radar transceiver IC <NUM>, to store software programs executed by processors on the radar transceiver IC <NUM>, etc. The memory <NUM> may include any suitable combination of readonly memory (ROM) and/or random access memory (RAM) (e.g., such as static RAM). In at least one example, a direct memory access (DMA) component <NUM> is coupled to the memory <NUM> to perform data transfers from the memory <NUM> to the high speed interface <NUM> and/or the SPI <NUM>.

In at least one example, the SPI <NUM> provides an interface for communication via terminal <NUM> between the radar transceiver IC <NUM> and another device (e.g., a processing unit such as the processing unit <NUM> of <FIG>). For example, the radar transceiver IC <NUM> may receive control information, e.g., timing and frequencies of chirps, output power level, triggering of monitoring functions, etc., via the SPI <NUM>. In at least one example, the radar transceiver IC <NUM> may transmit test data via the SPI <NUM>, for example, to the processing unit <NUM>.

In at least one example, the control module <NUM> includes functionality to control at least a portion of the operation of the radar transceiver IC <NUM>. The control module <NUM> may include, for example, a microcontroller that executes firmware to control the operation of the radar transceiver IC <NUM>. The control may be, for example, providing data parameters to other components of the radar transceiver IC <NUM> and/or providing control signals to other components of the radar transceiver IC <NUM>.

In at least one example, the programmable timing engine <NUM> includes functionality to receive chirp parameter values from the control module <NUM> for a sequence of chirps in a radar frame and to generate chirp control signals that control the transmission and reception of the chirps in a frame based on the parameter values. In some examples, the chirp parameters are defined by the radar system architecture and may include, for example, a transmitter enable parameter for indicating which transmit channels to enable, a chirp frequency start value, a chirp frequency slope, an ADC sampling time, a ramp end time, a transmitter start time, etc. In examples of the present disclosure, the control module <NUM> and programmable timing engine <NUM> are configured to dither the chirp start frequency, the ADC sampling window start time (e.g., when to begin sampling data received from the ADC 218A), and/or the idle time between chirps. For example, when dithering the chirp start frequency, the control module <NUM> causes the programmable timing engine <NUM> to initiate a first chirp at a first chirp frequency start value and a second chirp at a second chirp frequency start value different than the first chirp frequency start value. In another example, when dithering the ADC sampling window start time, the control module <NUM> begins sampling data received from the ADC <NUM> at different times relative to a first chirp and a second chirp, such that the effective start frequency for the ADC sampling window is approximately the same from chirp to chirp, when taking into account the dithered chirp start frequency, explained above. In yet another example, when dithering the idle time between chirps, the control module <NUM> causes the programmable timing engine <NUM> to vary the idle time between chirps such that a first idle time between first and second chirps is different than a second idle time between second and third chirps, such that the effective inter-chirp time is approximately the same from chirp to chirp, when taking into account the dithered chirp start frequency and ADC sampling window start time, explained above.

In at least one example, the radio frequency synthesizer (RFSYNTH) <NUM> includes functionality to generate signals (e.g., chirps and/or chirp sequences) for transmission based on chirp control signals received from the programmable timing engine <NUM>. In some examples, the RFSYNTH <NUM> includes a phase locked loop (PLL) with a voltage controlled oscillator (VCO). In at least one example, the RFSYNTH <NUM> may be referred to as a local oscillator (LO). The control module <NUM> and programmable timing engine <NUM> are configured to control the RFSYNTH <NUM> to dither the chirp start frequency, for example to generate a first chirp having a first chirp frequency start value and to generate a second chirp having a second chirp frequency start value different than the first chirp frequency start value.

In at least one example, the multiplexer <NUM> is coupled to the RFSYNTH <NUM> and the input buffer <NUM> and is configurable to select between signals received from the input buffer <NUM> from an external component (not shown) and signals generated by the RFSYNTH <NUM>. In at least one example, the output buffer <NUM> is coupled to the multiplexer <NUM> and may, for example, provide signals selected by the multiplexer <NUM> to the input buffer of another radar transceiver IC (not shown). In at least one example, the multiplexer <NUM> is controlled by the control module <NUM> via a select signal.

In at least one example, the clock multiplier <NUM> increases a frequency of an output of the multiplexer <NUM> (e.g., such as the output of the RFSYNTH <NUM>) to a frequency of operation of the mixer 206A. In at least one example, the clean-up PLL <NUM> is configured to increase the frequency of the signal of an external low frequency reference clock (not shown) received by the radar transceiver IC <NUM> to the frequency of the RFSYNTH <NUM> and to filter the reference clock phase noise out of the reference clock signal.

In at least one example, the I/Q modulator <NUM> is further coupled to a digital-to-analog converter (DAC) <NUM> and a DAC <NUM>, each of which may be coupled to the control module <NUM>.

<FIG> shows a frequency-versus-time plot <NUM> of a transmitted chirp <NUM> and a spur <NUM>. A corresponding amplitude-versus-frequency plot <NUM> is also shown for the chirp <NUM> (shown at times a-f) and the spur <NUM>. Referring to the plot <NUM>, as explained above, the transmitted chirp <NUM> is a linear frequency ramp as a function of time. On the other hand, the spur <NUM> is a fixed-frequency component. The plot <NUM> reinforces this distinction, in which the spur <NUM> comprises a single frequency component, whereas the transmitted chirp frequency changes over time, denoted as 304a-f, which may correspond to, for example, the amplitude of the transmitted chirp <NUM> frequency at <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, respectively.

As one example, the chirp <NUM> may have a start frequency of <NUM> and a slope of <NUM>/us, while the spur <NUM> may have a fixed frequency of approximately <NUM>. As an example of the mixer <NUM> generating an IF signal in the absence of the spur <NUM>, assume that the chirp <NUM> is reflected off of an object in view of the FMCW radar system <NUM> and that the round trip is <NUM> (e.g., an object distance of approximately <NUM> meters). The difference in the transmitted chirp <NUM> frequency (or transmitter path output frequency) and the reflected chirp <NUM> frequency (the receiver path input frequency) will be <NUM>, or the chirp <NUM> slope of <NUM>/us * the round trip time of <NUM>. Thus, in the absence of a spur <NUM>, an IF signal frequency component of <NUM> corresponds to a <NUM> round trip time, and an object distance of approximately <NUM> meters. However, as noted above, the presence of a fixed-frequency spur <NUM> results in multiple additional frequency components in the resulting IF signal erroneously appearing as objects at different distances.

<FIG> demonstrates the distance-based issues introduced by the spur <NUM> of <FIG> shows a frequency-versus-time plot <NUM> of an IF component <NUM> corresponding to the object (assuming a stationary object) and an IF component <NUM> corresponding to the spur. As explained above, for a stationary object, the IF component <NUM> frequency corresponding to the object is also fixed. On the other hand, the IF component <NUM> frequency corresponding to the spur increases linearly with time, since the transmitter path output frequency (i.e., the generated chirp) is a linear ramp, while the reflected spur component remains at a fixed frequency.

<FIG> also shows an amplitude-versus-frequency plot <NUM> for the IF component <NUM> corresponding to the object and the IF component <NUM> corresponding to the spur (shown at times a-e). The frequency of the IF component <NUM> corresponding to the object represents the distance of the stationary object (<NUM> meters in the example above). However, the presence of IF components 406a-e corresponding to the spur that vary with time results in erroneous determinations or identifications of objects at multiple distances. Further, although the IF components 406a-e corresponding to the spur are shown as discrete, in practice these may actually be continuous as the transmitter path output frequency constantly, linearly increases with time while the receiver path input frequency (i.e., the fixed-frequency spur) remains constant. The IF component <NUM> corresponding to the spur also undergoes a constant phase shift, which as explained above, causes it to appear as an object moving at a constant velocity.

<FIG> shows a range-velocity plot <NUM> as a function of receiver path output power (dB) that further indicates the erroneous distance-based and velocity-based issues introduced by the IF component <NUM> of <FIG> corresponding to the spur <NUM> of <FIG>, discussed above. The range-velocity plot <NUM> includes an object peak <NUM> as a result of the IF component <NUM> corresponding to the object, having a velocity of <NUM>/s at a fixed distance. The range-velocity plot <NUM> also includes spur ridges <NUM>, <NUM> as a result of the IF component(s) <NUM> corresponding to spurs. As explained above, the IF component(s) <NUM> appear as objects at multiple distances, reflected by the ridges <NUM>, <NUM> spanning multiple bins in the range axis. Further, the IF component(s) <NUM> appear as objects having a constant velocity, reflected by the position of the ridges <NUM>, <NUM> along the velocity axis. These erroneous "objects" created by the spurs <NUM> and the IF components <NUM> are problematic in various radar applications.

As explained above, the chirp start frequency is dithered from one chirp to the next, which effectively dithers the frequency of the IF component of the spur signal and dithers or breaks the consistency of the phase of the IF component of the spur signal. <FIG> shows a frequency-versus-time plot <NUM> including a first transmitted chirp <NUM>, a second transmitted chirp <NUM>, and a third transmitted chirp <NUM>, in which the chirp start frequency is dithered from one chirp to the next. In addition, a spur <NUM>, which is a fixed-frequency spur, is shown and explained above.

<FIG> shows a frequency-versus-time plot <NUM> of the receiver path IF signals that result from the dithered chirps <NUM>, <NUM>, <NUM> and the fixed-frequency spur <NUM> of <FIG>. In particular, assuming a static object, the reflected chirps will all have a constant difference from the transmitted chirps <NUM>, <NUM>, <NUM>, and thus a IF component <NUM> corresponding to the chirps is also constant (e.g., <NUM> in the example above). However, since the fixed-frequency spur <NUM> is being compared or mixed (e.g., by mixer <NUM>) with dithered-frequency chirps <NUM>, <NUM>, <NUM>, the resultant IF components <NUM>, <NUM>, <NUM>, respectively, corresponding to the spur are also dithered. As a result of dithering the IF components <NUM>, <NUM>, <NUM>, the consistency of the phase of the IF components <NUM>, <NUM>, <NUM> is also dithered, or broken. For example, dithering the chirp start frequency causes the starting phase of the signal in each range bin to be dithered across the chirps. Since the phase difference of the bin from one chirp to the next is not uniform, it no longer appears as a constant velocity signal, but rather a signal with varying velocity from chirp to chirp. Breaking the consistency of the phase of the IF components <NUM>, <NUM>, <NUM> corresponding to the spur spreads their impact across the velocity bins and thus mitigates the impact of ridges <NUM>, <NUM> shown in <FIG> and described above.

<FIG> and <FIG> show a comparison of a range-velocity plot as a function of receiver path output power (dBm) before chirp start frequency dithering <NUM> and after chirp start frequency dithering <NUM>. The range-velocity plot <NUM> is identical to plot <NUM> in <FIG> and is reproduced here for clarity. <FIG> and <FIG> also shows a comparison of a velocity-versus-output power plot before chirp start frequency dithering <NUM> and after chirp start frequency dithering <NUM>. In the velocity-versus-output power plot before chirp start frequency dithering <NUM>, the peak <NUM> corresponds to the IF component corresponding to the chirp (and is similar to the peak <NUM> in <FIG>, viewed along the velocity axis), while the peaks <NUM>, <NUM> correspond to the IF components corresponding to the spur (and are similar to the ridges <NUM>, <NUM> in <FIG>, viewed along the velocity axis). As demonstrated in the range-velocity plot after chirp start frequency dithering <NUM>, the ridges present in <FIG> (<NUM>, <NUM>) have been mitigated, or spread across various velocity values. However, the velocity-versus-output power plot after chirp start frequency dithering <NUM> demonstrates that the IF component corresponding to the chirp has leaked to other velocity values (e.g., due to the impact of dithering on the phase consistency explained above), despite the fact that the object represented by the IF signal is stationary.

As explained above, in addition to dithering the chirp start frequency, in some examples, an ADC sampling window start time is also dithered from one chirp to the next. <FIG> shows the frequency-versus-time plot <NUM> of <FIG> with different ADC sampling window start times <NUM>, <NUM>, <NUM> for chirps <NUM>, <NUM>, <NUM>, respectively. In particular, the ADC sampling window start times <NUM>, <NUM>, <NUM> are selected relative to each chirp <NUM>, <NUM>, <NUM> such that the effective start frequency for each ADC sampling window is approximately the same, as demonstrated by frequency intercept line <NUM>, which avoids signal incoherence. In examples, by dithering the ADC sampling window start time along with the chirp start frequency, phase coherency is maintained for the IF signal from chirp to chirp even though the chirp start frequency dithers.

<FIG> and <FIG> show a comparison of range-velocity plots <NUM>, <NUM> as a function of receiver path output power (dBm) before (<NUM>) and after (<NUM>) chirp start frequency and sampling window start time dithering. <FIG> and <FIG> also show a comparison of velocity-versus-output power plots <NUM>, <NUM> before (<NUM>) and after (<NUM>) chirp start frequency and sampling window start time dithering. The range-velocity plot <NUM> and the velocity-versus-output power plot <NUM> are identical to those in <FIG> and <FIG>. As demonstrated by the range-velocity plot <NUM> and the velocity-versus-output power plot <NUM>, the influence of the spurs remains mitigated as before. Further, as best depicted in the velocity-versus-output power plot <NUM>, for a stationary object, the chirp component no longer leaks to other velocity values and signal coherence is improved as a result of dithering the sampling start window time as described with respect to <FIG>.

<FIG> shows a comparison of a velocity-versus-output power plot before and after chirp start frequency and sampling window start time dithering <NUM>, <NUM>, respectively, but in this case for a moving object. Dithering both the chirp start frequency and the sampling window start time addresses the leakage to other velocities for a stationary object. However, as can be seen by comparing plot <NUM> to plot <NUM>, this double dithering approach still results in signal leakage to other velocities for a moving object. This signal leakage results from an unintentional modulation of the inter-chirp time, which will be explained more fully below.

<FIG> shows a frequency-versus-time plot of a frame <NUM> (or a portion of a frame) including chirps <NUM>, <NUM>, <NUM>. In the frame <NUM>, the chirp start frequencies and the ADC sampling window start times are dithered, as explained above. For example, the chirp <NUM> starts at a frequency F1, while the chirp <NUM> starts at a frequency F3 and the chirp <NUM> starts at a frequency F2.

Regarding the ADC sampling window start time, which is also dithered, the sampling window of the chirp <NUM> begins at the point <NUM>, which is relatively far in time from the start of the chirp <NUM>, and ends at the point <NUM>. The sampling window of the chirp <NUM> begins at the point <NUM>, which is relatively near in time to the start of the chirp <NUM>, and ends at the point <NUM>. The sampling window of the chirp <NUM> begins at the point <NUM>, which is delayed from the start of the chirp <NUM> approximately between the delays of the points <NUM> and <NUM> from the start of the first two chirps <NUM>, <NUM>, respectively. The sampling window of the chirp <NUM> ends at the point <NUM>. As explained above, the sampling window start times at points <NUM>, <NUM>, <NUM> are selected such that the frequency at those times of the respective chirps <NUM>, <NUM>, <NUM> are approximately equal (e.g., at a frequency F4).

In <FIG>, an idle time between chirps <NUM>, <NUM>, <NUM> is approximately equal. For example, an idle time <NUM> between the end of the chirp <NUM> and the beginning of the chirp <NUM> is approximately equal to an idle time <NUM> between the end of the chirp <NUM> and the beginning of the chirp <NUM>. As a result, an inter-chirp time, or the time from the sampling window start time of one chirp to the sampling window start time of the following chirp, varies between chirps. For example, an inter-chirp time <NUM> between the sampling window start time at point <NUM> of the chirp <NUM> and the sampling window start time at point <NUM> of the chirp <NUM> is less than an inter-chirp time <NUM> between the sampling window start time at point <NUM> of the chirp <NUM> and the sampling window start time at point <NUM> of the chirp <NUM>. This unintentional modulation of the inter-chirp time <NUM>, <NUM> results in the signal leakage to other velocities for a moving object, as explained above. For example, a constant-velocity moving object moves non-uniform distances from one chirp sampling to the next, and thus the phase of an IF signal for the constant-velocity moving object will also vary from one chirp sampling to next, causing leakage in the velocity axis.

<FIG> shows a frequency-versus-time plot of a frame <NUM> (or a portion of a frame) in which the idle time between chirps is dithered as well. The frame <NUM> includes chirps <NUM>, <NUM>, <NUM>. In the frame <NUM>, the chirp start frequencies and the ADC sampling window start times are also dithered, as explained above with respect to <FIG>. In addition, in frame <NUM>, the idle time between chirps is dithered and thus an idle time <NUM> between the chirps <NUM>, <NUM> is longer in duration than an idle time <NUM> between the chirps <NUM>, <NUM>. As a result, despite the dithering of the chirp start frequencies and the ADC sampling window start times, which by themselves lead to unintentional modulation of inter-chirp times, an inter-chirp time <NUM> between the sampling window start time <NUM> of the chirp <NUM> and the sampling window start time <NUM> of the chirp <NUM> is approximately equal to an inter-chirp time <NUM> between the sampling window start time <NUM> of the chirp <NUM> and the sampling window start time <NUM> of the chirp <NUM>.

<FIG> and <FIG> show a comparison of range-velocity plots <NUM>, <NUM>, <NUM>, <NUM> as a function of receiver path output power (dBm) with no dithering (<NUM>); dithering the chirp start frequency (<NUM>, single dithering example); dithering the chirp start frequency and the ADC sampling window start times (<NUM>, double dithering example); and dithering the chirp start frequency, the ADC sampling window start times, and the idle time between chirps (<NUM>, triple dithering example). As explained above with respect to <FIG>, in the no dithering plot <NUM>, spurs appear as ridges spanning multiple range bins at a particular, constant velocity. Further, as described with respect to <FIG> and <FIG>, in the single dithering plot <NUM>, spurs are spread across velocity bins, mitigating their impact on the range-velocity plot. However, the IF component corresponding to the object leaks to other velocities. In the exemplary double dithering plot <NUM> (shown here for a moving object), the IF component corresponding to the object still leaks to other velocities, although this is not the case with a stationary object. Finally, in the exemplary triple dithering plot <NUM>, the spurs remain mitigated, while the IF component corresponding to the object no longer leaks to other velocities. In short, when triple dithering is applied, the IF component corresponding to the object is readily identifiable in the plot <NUM>, without influence from spurs.

<FIG> shows a flow chart of an example method <NUM> for mitigating spurious signals in an FMCW radar system <NUM> including a radar transceiver IC <NUM> as described above in <FIG> and <FIG>. The method <NUM> begins in block <NUM> with transmitting a frame comprising first, second, and third chirps. For example, the transmit channel <NUM> transmits the first, second, and third chirps based on input from the control module <NUM>, the timing engine <NUM>, and the RFSYNTH <NUM>. As explained above, each chirp has a chirp start frequency and the frame includes an idle time between the chirps. The method <NUM> continues in block <NUM> with receiving a frame of reflected chirps based on the transmitted frame, and generating a digital intermediate frequency (IF) signal. For example, the receive channel <NUM> receives the reflected chirps and the mixer <NUM> mixes a clock signal from the clock multiplier <NUM> with the received RF signal corresponding to the reflected chirps generates the IF signal. Each first, second, and third reflected chirp has a sampling window start time.

The method <NUM> continues in block <NUM> with dithering the chirp start frequency of the transmitted chirps. For example, the control module <NUM> causes the programmable timing engine <NUM> to initiate a first chirp at a first chirp frequency start value and a second chirp at a second chirp frequency start value different than the first chirp frequency start value. In some examples, the method <NUM> continues further in block <NUM> with dithering the sampling window start time of the reflected chirps. For example, the control module <NUM> begins sampling data received from the ADC <NUM> at different times relative to a first chirp and a second chirp, such that the effective start frequency for the ADC sampling window is approximately the same from chirp to chirp, when taking into account the dithered chirp start frequency. In another example, the method <NUM> continues in block <NUM> with dithering the idle time between the transmitted chirps. For example, the control module <NUM> causes the programmable timing engine <NUM> to vary the idle time between chirps such that a first idle time between first and second chirps is different than a second idle time between second and third chirps, such that the effective inter-chirp time is approximately the same from chirp to chirp, when taking into account the dithered chirp start frequency and ADC sampling window start time.

Claim 1:
A method for a FMCW radar system, the method comprising:
transmitting, by a transmit channel of the radar system, a frame comprising first, second, and third chirps (<NUM>), each chirp having a chirp start frequency, wherein the chirp start frequency of the transmitted chirps is dithered (<NUM>); and
receiving, by a receive channel of the radar system, a frame of reflected chirps based on the transmitted frame, and generating a digital intermediate frequency. IF, signal;
wherein each first, second, and third reflected chirp has a sampling window start time,
the method being characterized by further comprising:
dithering the sampling window start time of the reflected chirps (<NUM>) such that the effective start frequency of the sampling window is approximately the same from chirp to chirp.