Patent Description:
In a typical single-ended alternating current (AC)-coupled communication receiver, a circuit is used at the receiving end to set the termination voltage and a direct current (DC) level is replicated and used as a reference voltage for the comparator. However, if the start or end of the data transmission is different than the DC balance of the line, the termination voltage and thus the reference voltage will not be centered around the input signal until the line reaches its DC balanced point or steady state. In some communication protocols, such as common-mode eARC communication channel, the time required for the line to settle far exceeds the specified start-up window.

A typical circuit that extracts the DC component of a switching signal uses an RC filter. However, there is a direct tradeoff between the startup time and the ripple due to the switching. The faster the startup time the higher the ripple which translates directly to the higher receiver jitter. The filter also requires a representative density of positive and negative pulses to accurately render an average.

<CIT> describes a data slicer reference generator for multiple burst data signals. <CIT> describes a data extracting circuit.

In a first aspect, there is provided a receiver according to claim <NUM>.

Embodiments of a communication receiver are provided that detect the peak high and low pulses and average the peak detected values to generate a reference voltage for a comparator. The comparator generates the output recovered logic levels. Embodiments of the invention disclosed herein thus allow for reasonable reference values with fewer input data values than other known solutions. An averaging portion of the receiver also acts as second RC filter that controls the relaxation of the peak detection circuit, resulting in lower ripple. Relaxation of the peak detection circuit allows the reference point to track the DC component as the DC component settles during operation of the communication receiver.

<FIG> illustrates a schematic diagram of communication receiver <NUM> in accordance with embodiments of the present invention that includes termination resistive element <NUM>, switches <NUM>, <NUM>, averaging resistive elements <NUM>. <NUM>, capacitive elements <NUM>, <NUM>, <NUM>, comparator <NUM>, and inverter <NUM>. An analog communication signal is coupled as an input to a first terminal of termination resistive element <NUM>, a non-inverting input to comparator <NUM>, and to first terminals of switches <NUM>, <NUM>. Terminating resistive element <NUM> includes a second terminal coupled to ground or other suitable supply voltage. Switch <NUM> includes a control terminal that is coupled to an OUT signal that is generated at the output of comparator <NUM>. The OUT signal is also provided as input to inverter <NUM>. In addition to the first terminal coupled to the analog input signal, switch <NUM> includes a second terminal coupled to a first terminal of capacitive element <NUM>. A second terminal of capacitive element <NUM> is coupled to ground or other suitable supply voltage. Switch <NUM> includes a control terminal that is coupled to the complement of the OUT signal (shown as OUTB), which is generated at the output of inverter <NUM>. In addition to the first terminal coupled to the analog input signal, switch <NUM> includes a second terminal coupled to a first terminal of capacitive element <NUM>. A second terminal of capacitive element <NUM> is coupled to ground or other suitable supply voltage. In some implementations, resistive elements <NUM>, <NUM> have matching resistances, and capacitive elements <NUM>, <NUM> have matching capacitances.

Resistive element <NUM> includes a first terminal coupled between the second terminal of switch <NUM> and the first terminal of capacitive element <NUM>. The conductor coupling the second terminal of switch <NUM>, the first terminal of resistive element <NUM> and the first terminal of capacitive element <NUM> is referred to as Net A. A second terminal of resistive element <NUM> is coupled to a first terminal of resistive element <NUM>. A second terminal of resistive element <NUM> is coupled between the second terminal of switch <NUM> and a first terminal of capacitive element <NUM>. A second terminal of capacitive element <NUM> is coupled to ground or other suitable supply voltage. A conductor coupling the second terminal of switch <NUM>, the second terminal of resistive element <NUM> and the first terminal of capacitive element <NUM> is referred to as Net B.

In addition to a non-inverting input coupled to the analog input signal, comparator <NUM> includes an inverting input coupled between the second terminal of resistive element <NUM> and the first terminal of resistive element <NUM>.

Capacitive element <NUM> includes a first terminal coupled between the second terminal of resistive element <NUM> and the first terminal of resistive element <NUM>, and the inverting input of comparator <NUM>. A second terminal of capacitive element <NUM> is coupled to ground or other suitable supply voltage.

Switches <NUM>, <NUM> are controlled by the signals OUT and OUTB generated by comparator <NUM> and inverter <NUM>, respectively. Analog input signal is a modulated and encoded binary data signal that is suitably AC coupled to receiver <NUM> to facilitate data transmission and yet isolate the DC levels of the channel from the DC levels of receiver <NUM>. Switches <NUM>, <NUM> can be implemented with MOSFET transistors that have resistance that is based on the drain-source voltage and the drain current. When switches <NUM>, <NUM> are implemented with transistors, each transistor has a current electrode coupled to the analog input signal and another current electrode coupled to NET A or NET B that provide data signals to NET A and NET B. During operation, when the analog input signal is positive, the OUT signal is asserted, switch <NUM> is closed, and switch <NUM> is open. Net A tracks the high peak of the analog input signal while Net B is in a relaxation phase. The resistance of switch <NUM> and capacitive element <NUM> are selected to provide the desired response time of the VREF_TRACK signal that is provided to inverting input of comparator <NUM>. Resistive elements <NUM> and <NUM> and capacitive elements <NUM>, <NUM> set the response characteristics of the relaxation phase after the peak value is reached. When the analog input signal is negative, the OUTB signal is asserted, switch <NUM> is closed and switch <NUM> is open. Net B tracks the low peak of the analog input signal while Net A is in a relaxation phase. The resistance of switch <NUM> and capacitive element <NUM> are selected to provide the desired response time of the VREF_TRACK signal that is provided to inverting input of comparator <NUM>. Resistive elements <NUM> and <NUM> and capacitive elements <NUM>, <NUM> set the response characteristics of the relaxation phase after the peak value of the OUTB signal is reached. VREF_TRACK signal is a weighted average of the positive and negative peaks of the analog input signal, subject to the chosen track and relaxation time constants, and allows the recovery of the transmitted waveform.

Referring to <FIG> and <FIG> illustrates examples of voltage versus time graphs for various signals used in the communication receiver <NUM> of <FIG>. Analog input signal <NUM> is a binary encoded input analog signal that can have varying amplitude/logic levels and DC offset over time. For purposes of example only, analog input signal <NUM> has a swing of 200mV with a starting voltage of 200mV set by the termination. Other suitable voltage levels and swing amplitude for analog input signal <NUM> can be used, however. Analog input signal <NUM> is encoded so that logic high and logic low are fairly constant relative to the switching rate of the data and so remains at upper and lower peak values for varying amounts of time. At the start of the time history, at time T0, analog input signal <NUM>, NET A signal, NET B signal, and VREF_TRACK signal are at the lower peak voltage for purposes this example only and do not necessarily start at this voltage. OUT signal <NUM> is de-asserted, and OUTB signal <NUM> is asserted. At time T1, analog input signal <NUM> goes from the lower peak voltage to the upper peak voltage. OUT signal <NUM> is asserted, OUTB signal <NUM> is de-asserted, and NET A signal <NUM> follows analog input signal <NUM> closely to the upper peak value of analog input signal <NUM> while NET B signal <NUM> remains at or close to the lower peak voltage. NET A signal <NUM> has a very slight delay reaching the upper peak voltage, as shown by a small space between NET A signal <NUM> and analog input signal <NUM> at the upper leading edge of the pulse. The delay is determined by the time constant of the resistance of switch <NUM> and capacitive element <NUM>. VREF_TRACK signal <NUM> starts increasing from the lower peak voltage toward a midpoint between the upper and lower peak voltages of approximately <NUM> millivolts at time T1.

At time T2, analog input signal <NUM> goes from the upper peak voltage to the lower peak voltage. NET A signal <NUM> follows to approximately midway between the upper and lower peak voltages, for example, to <NUM> mV, and decays or relaxes to a slightly lower voltage, for example, to <NUM> mV, between times T2 and T3. The amount of decay or relaxation is determined by resistive element <NUM> and capacitive element <NUM> and the delay in non-ideal comparator <NUM>. Until switch <NUM> is switched off, NET A follows the analog input signal down with the fast time constant set by the resistance of switch <NUM>. After switch <NUM> is switched off, then the decay is determined by resistive element <NUM> and capacitive element <NUM>. One can thus appreciate the ability to adjust response and variability of the waveforms depending on component availability and choice. <FIG> is one example of the spectrum of responses that could be chosen. NET B signal <NUM> barely starts to increase between times T1 and T2 and returns to the low peak voltage between times T2 and T3. VREF_TRACK signal <NUM> continues to increase to a value between the upper and lower peak voltages from time T2 to T3.

At time T3, analog input signal <NUM> goes from the lower peak voltage to the upper peak voltage. NET A signal <NUM> again closely follows analog input signal <NUM> to the upper peak value of analog input signal <NUM> while NET B signal <NUM> is at or close to the lower peak voltage. NET A signal <NUM> has a very slight delay reaching the upper peak voltage, as shown by a small space between NET A signal <NUM> and analog input signal <NUM> at the upper leading edge of the pulse. VREF_TRACK signal <NUM> continues increasing from approximately <NUM> mV to <NUM> mV between times T3 and T4. NET A signal <NUM> follows analog input signal <NUM> to less than midway (for example, <NUM> mV) between the upper and lower peak voltages and decays slowly to a slightly lower voltage (for example, <NUM> mV) between times T3 and T4. NET B signal <NUM> increases from the lower peak voltage and rises slightly between times T3 and T4. For example, NET B signal <NUM> rises from <NUM> to <NUM> mV during a relaxation phase based on resistive element <NUM> and capacitive element <NUM>. VREF_TRACK signal <NUM> continues to increase to a value between the upper and lower peak voltages, for example, from approximately <NUM> to <NUM> mV, from time T3 to T4.

Analog input signal <NUM> transitions from upper to lower peak voltage at time T4. NET A signal <NUM> follows analog input signal <NUM> to a point between the upper and lower peak voltages, for example, to <NUM> mV, and decays or relaxes to a slightly lower voltage, for example, to <NUM> mV, between times T4 and T5. The amount of decay or relaxation is determined by resistive element <NUM> and capacitive element <NUM>. NET B signal <NUM> decreases to the lower peak voltage at time T4 and remains at the lower peak voltage between times T4 and T5. VREF_TRACK signal <NUM> decreases slightly between time T4 and time T5.

Analog input signal <NUM> transitions from lower to upper peak voltage at time T5. NET A signal <NUM> follows analog input signal <NUM> to the upper peak voltage and decays slowly to a slightly lower voltage (for example, decays from <NUM> to <NUM> mV) between times T6 and T7. NET B signal <NUM> increases from the lower peak value at time T5 to an intermediate voltage, for example, <NUM> mV at time T5. Between times T5 and T6, NET B signal <NUM> increases slightly during a relaxation phase between times T5 to T6. For example, NET B signal <NUM> rises from <NUM> to <NUM> mV during the relaxation phase based on resistive element <NUM> and capacitive element <NUM>. VREF_TRACK signal <NUM> increases to a value between the upper and lower peak voltages, for example, from approximately <NUM> to <NUM> mV, from time T5 to T6.

For the remaining time, analog input signal <NUM> continues to vary between upper and lower peak voltages. When analog input signal <NUM> increases toward the upper peak voltage, NET A <NUM> signal follows analog input signal <NUM> to the upper peak voltage while NET B signal <NUM> increases to an intermediate value above the lower peak value but below VREF_TRACK signal <NUM>. During relaxation periods, while analog input signal <NUM> and NET A signal <NUM> remain at the upper peak voltage, NET B signal <NUM> increases slightly but remains well below VREF_TRACK signal <NUM>. When analog input signal <NUM> transitions from the upper peak voltage to the lower peak voltage, NET A <NUM> signal follows analog input signal <NUM> to an intermediate value below the upper peak value but above VREF_TRACK signal <NUM> while NET B signal <NUM> decreases with analog input signal to the lower peak value. During relaxation periods, while analog input signal <NUM> and NET B signal <NUM> remain at the lower peak voltage, NET A signal <NUM> decreases slightly but remains well above VREF_TRACK signal <NUM>. VREF_TRACK signal <NUM> increases to a modest extent when analog input signal <NUM> and NET A signal <NUM> are at the upper peak voltage, and decreases a similar amount when analog input signal <NUM> and NET B signal <NUM> are at the lower peak voltage. Note that VREF_TRACK signal <NUM> achieves the majority of the settling by time T7.

VREF_TRACK signal <NUM> gradually increases, in a shallow sawtooth or ripple waveform, to an intermediate average value as receiver begins operating at time T1. After the first several cycles of analog input signal <NUM>, VREF_TRACE signal <NUM> continues with a sawtooth or ripple pattern alternating slightly above and below an average reference track voltage. The upper and lower peak values are shown as decreasing over time because the VREF_TRACK signal <NUM> is not yet charged to its DC balance point, which is determined by the swing and the initial or termination voltage. As an example, with the termination voltage of 200mV and the swing amplitude of 200mV, when the line reaches its DC balance, the high level will settle out at 300mV and the low level will settle out at 100mV. The startup time can be adjusted to meet specified requirements by adjusting the resistance of switches <NUM>, <NUM> and the value of capacitive elements <NUM>, <NUM>. In addition, the amount of ripple can be controlled be adjusting the values of resistive elements <NUM>, <NUM> and capacitive elements <NUM>, <NUM>, <NUM>. Receiver <NUM> thus satisfies two competing requirements, with the ability to decouple the peak tracking and the relaxation phase to achieve fast start up time and low ripple. Receiver <NUM> can also achieve greater noise margins for a specified startup time due to the damping of the amount of ripple in the VREF_TRACK signal <NUM>, as both the upper and lower peak voltages are used to generate the VREF_TRACK signal <NUM>.

A receiver includes an input node coupled to receive an analog signal, a first switch coupled between the input node and a first node, a second switch coupled between the input node and a second node, a first resistive element coupled between the first node and a reference node, a second resistive element coupled between the second node and the reference node, a first capacitive element coupled to the first node, and a second capacitive element coupled to the second node. The receiver also includes a comparator having a first input coupled to the input node to receive the analog signal, and a second input coupled to the reference node to receive a reference voltage, wherein an output of the comparator controls the first and second switches.

Because the apparatus implementing the present disclosure is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present disclosure and in order not to obfuscate or distract from the teachings of the present disclosure.

Moreover, the terms "front," "back," "top," "bottom," "over," "under" and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Although the disclosure is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below.

The term "coupled," as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.

Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to disclosures containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an.

Claim 1:
A receiver (<NUM>) , comprising:
an input node coupled to receive an analog signal;
a first switch (<NUM>) coupled between the input node and a first node (NETA) ;
a second switch (<NUM>) coupled between the input node and a second node (NETB) ;
a first resistive element (<NUM>) coupled between the first node (NETA) and a reference node;
a second resistive element (<NUM>) coupled between the second node (NETB) and the reference node;
a first capacitive element (<NUM>) coupled to the first node (NETA) ;
a second capacitive element (<NUM>) coupled to the second node (NETB) ; and
a comparator (<NUM>) having a first input coupled to the input node to receive the analog signal, a second input coupled to the reference node to receive a reference voltage, wherein an output of the comparator (<NUM>) controls the first (<NUM>) and second (<NUM>) switches;
wherein the first switch (<NUM>) comprises a first transistor having a first current electrode coupled to the input node, a second current electrode coupled to the first node (NETA), and a control electrode coupled to the output of the comparator (<NUM>) , and
the second switch (<NUM>) comprises a second transistor having a first current electrode coupled to the input node, a second current electrode coupled to the second node (NETB) , and a control electrode coupled to receive an inverse of the output of the comparator (<NUM>).