Patent Description:
In particular, described herein are a method for interfacing a first data reading unit with a second data reading unit and a method for interfacing a first data writing unit with a second data writing unit, as well as respective data reading and data writing interface modules.

The present invention is used in a data processing and/or acquisition system that is configured by means of FPGA (Field Programmable Gate Array) units and optionally SoC-FPGA (System on Chip FPGA) units. Several types of FPGA or SoC-FPGA units currently exist which can be used in various data processing and/or acquisition systems, e.g. image and/or video acquisition and coding systems, etc..

Such systems suffer from a number of drawbacks, which will be illustrated below.

A first drawback lies in the fact that such systems suffer from some criticalities in terms of data transfer speed during the data reading and/or writing processes; such criticalities are due to the low storage capacity of the memory buffers, e.g. FIFO memory modules, implemented in FPGA and/or SoC-FPGA units or the like.

A second drawback comes from the fact that poor data transfer speeds impair the performance of the processing and/or acquisition system as a whole.

It is therefore one object of the present invention to solve these and other problems of the prior art, and particularly to provide a method for interfacing a first data reading unit with a second data reading unit and a method for interfacing a first data writing unit with a second data writing unit, as well as respective data reading and data writing interface modules, which permit reducing the criticalities due to low data transfer speeds during the data reading and/or writing processes.

It is a further object of the present invention to provide a method for interfacing a first data reading unit with a second data reading unit and a method for interfacing a first data writing unit with a second data writing unit, as well as respective data reading and data writing interface modules, which make it possible to effectively regulate a flow of data being read and/or written in the functional modules included in FPGA and/or SoC-FPGA units.

In brief, the invention described herein consists of a method for interfacing, for data reading and/or writing purposes, two or more units, configurable as FPGA and/or SoC-FPGA units, which implement two or more functional modules such as, for example, FIFO memory functional modules, DMA (Direct Memory Access) functional modules, data acquisition (DAQ) functional modules, data output functional modules, data processing modules, communication modules, and so forth.

The invention will now be described in detail with particular reference to the annexed drawings, wherein:.

<FIG> schematically shows a data processing and/or acquisition system <NUM>, which comprises first processing means <NUM>, I/O interface means <NUM>, memory means <NUM>, and second processing means <NUM>. These can be interconnected via a communication bus <NUM>, e.g. a PCI bus, etc..

The I/O interface means <NUM> are adapted to receive and transmit input/output information from the system <NUM> to a user, e.g. in order to allow the user to manage the system <NUM>. The I/O interface means <NUM> may comprise, for example, a screen, a keyboard, a touchscreen, etc. In addition, the I/O interface means <NUM> may comprise communication means adapted to establish a communication channel to a server. The communication means may comprise, for example, a USB, CANBUS, ETHERNET, WiFi, Bluetooth, GSM, etc. interface.

The memory means <NUM> are adapted to store the information and the instructions of the system <NUM> according to the present embodiment of the invention, and may comprise, for example, a Flash-type solid-state memory, an SDRAM memory, etc. The information may comprise, for example, data and/or parameters relating to the system <NUM> and necessary for the operation of the same.

The first processing means <NUM> are adapted to process the information and the instructions stored in the memory means <NUM>, with reference to the I/O interface means <NUM> and the second processing means <NUM>, which will be described in further detail hereinafter. The first processing means <NUM> may comprise, for example, a multicore ARM processor, a multicore x86 processor, etc..

With reference to <FIG>, the second processing means <NUM> may comprise, in accordance with the present embodiment of the invention, an SoC-FPGA unit such as, for example, an Altera Cyclon V unit. In particular, the second processing means <NUM> may comprise an HPS (Hard Processor System) unit <NUM> and an FPGA unit <NUM> operatively connected to each other by means of, for example, a first interface <NUM> and a second interface <NUM>.

The HPS unit <NUM> may comprise a microprocessor <NUM>, e.g. an ARM Cortex-A9 MPCore processor, and an SDRAM controller <NUM> operatively connected to each other by means of a connection unit <NUM>, e.g. an L3-Interconnect unit. In particular, the microprocessor <NUM> controls the connection unit <NUM>, which in turn handles a flow of control data that is sent from the HPS unit <NUM> to the FPGA unit <NUM>, and vice versa, via the first interface <NUM>, which may comprise, for example, a Lightweight bridge bus having a <NUM>-bit data width. Moreover, the connection unit <NUM> handles a flow of data from the HPS unit <NUM> to the FPGA unit <NUM>, and vice versa, via the second interface <NUM>, which may comprise, for example, an HPS-to-FPGA bridge bus and an FPGA-to-HPS bridge bus having a configurable <NUM>-bit, <NUM>-bit or <NUM>-bit data width.

The FPGA unit <NUM> comprises a plurality of programmable logic elements and a plurality of reconfigurable interconnections that allow the logic elements to be physically connected to one another. It is therefore possible to configure the logic elements to implement simple functional modules such as, for example, AND and/or OR logic ports. Additionally or alternatively, the logic elements may be configured to implement complex functional modules such as, for example, FIFO memory functional modules, DMA (Direct Memory Access) functional modules, data acquisition (DAQ) functional modules, data output functional modules, data processing modules, communication modules, etc. Such functional modules can be configured, i.e. implemented, in the FPGA unit <NUM> by VHDL (VLSI Hardware Description Language), which permits describing hardware components. In fact, VHDL is not an executable language, and therefore it does not describe operations that a processor has to carry out in order to compute the result of a processing activity; on the contrary, the VHDL language describes the logic elements that constitute the circuit capable of executing the requested processing. Such functional modules, implemented by VHDL, can thus create interconnectable complex units, i.e. such units may comprise one or more functional modules operatively connected to one another.

In particular, according to the present embodiment of the invention, a first data reading unit <NUM> and a second data reading unit 260a, operatively connected to a data reading interface module <NUM>, and a first data writing unit <NUM> and a second data writing unit 260b, operatively connected to a data writing interface module <NUM>, are implemented in the FPGA unit <NUM>, e.g. by VHDL using INTEL's Quartus-prime platform.

The first data reading unit <NUM> may comprise a DMA module for reading the data, hereafter referred to as R-DMA, and the first data writing unit <NUM> may comprise a further DMA module, hereafter referred to as W-DMA, while a second data reading and writing unit <NUM> may comprise both a second data reading unit 260a and a second data writing unit 260b; for example, the second data reading and writing unit <NUM> may comprise a FIFO memory module. In particular, the first data reading unit <NUM> and the first data writing unit <NUM> utilize a bus compliant with the Avalon standard and having a memory-mapped master-slave architecture for communicating with the second data reading and writing unit <NUM>, i.e. for communicating with the FIFO memory module. Furthermore, in order to ensure highly configurable data management in the system <NUM>, the second data reading and writing unit <NUM> may be implemented, for example, by means of a FIFO memory module in showahead mode, having as data Q a number of <NUM> binary words of <NUM> bits each. Thus implemented, however, the second data reading and writing unit <NUM> is not compliant with the Avalon standard. As a matter of fact, the Avalon standard ensures interactive and controlled data transfer management, but its characteristics cannot be fully exploited when a FIFO memory module is used. In particular, the Avalon standard requires that data writing and reading request signals remain unchanged if the master receives a reading or writing waiting (waitrequest) signal, but this would cause a write operation to occur in a full FIFO memory module or a read operation to occur from an empty FIFO memory module; therefore, the FIFO memory module must not receive such data writing and reading request signals while a reading or writing waiting (waitrequest) signal is active.

In accordance with the present invention, advantageously, the data reading interface module <NUM> and the data writing interface module <NUM> allow, respectively, the first data reading unit <NUM> to be interfaced with the second data reading unit 260a and the first data writing unit <NUM> to be interfaced with the second data writing unit 260b, thereby advantageously ensuring highly configurable management of the data Q in the system <NUM>. This advantageously makes it possible to prevent the data Q from being written to a full FIFO memory module or read from an empty FIFO memory module, thus preventing the FIFO memory module from receiving such signals while a reading or writing waiting (waitrequest) signal is active.

In addition or as an alternative to the present embodiment of the invention, the second data reading unit 260a and the second data writing unit 260b may be independent: for example, the second data reading unit 260a may comprise a data acquisition (DAQ) module comprising a first memory buffer, while the second data writing unit 260b may comprise a data output functional module comprising a second memory buffer, which do not comply with the Avalon standard.

Similarly to the above, in accordance with the present invention, the data reading interface module <NUM> and the data writing interface module <NUM> allow, respectively, the first data reading unit <NUM> to be interfaced with the second data reading unit 260a and the first data writing unit <NUM> to be interfaced with the second data writing unit 260b, thereby advantageously ensuring highly configurable management of the data Q in both the first memory buffer and the second memory buffer.

In accordance with the present embodiment of the invention, the data Q are transferred from the memory means <NUM>, i.e. from an SDRAM memory, to the second data reading and writing unit <NUM>, i.e. to the FIFO memory module, and vice versa. For example, the data Q may comprise a predefined total number of binary words, e.g. <NUM>,<NUM> binary words, each one consisting of <NUM> bits. With reference to <FIG>, the data Q can be read from the memory means <NUM> and transferred, over the bus <NUM>, to the SDRAM controller <NUM>, which then, via the connection unit <NUM>, transfers the data Q to the FPGA unit by means of the second interface <NUM>. The second interface <NUM> then sends the data Q to the first data writing unit <NUM>, which, by means of the data writing interface module <NUM>, writes the data Q to the second data reading and writing unit <NUM>, i.e. to the FIFO memory module. In addition, the first data reading unit <NUM> can read the data Q from the second data reading and writing unit <NUM>, i.e. from the FIFO memory module, by means of the data reading interface module <NUM>, and can send the data Q to the SDRAM controller <NUM>, via the connection unit <NUM>, by means of the second interface <NUM>. Thus, the data Q can be transmitted from the SDRAM controller <NUM> to the memory means <NUM>, i.e. to the SDRAM memory, over the bus <NUM>. The first data reading unit <NUM> and the first data writing unit <NUM> are managed by the HPS unit <NUM> by means of the first interface <NUM> operatively connected to a slave control port <NUM> of both the first data reading unit <NUM>, i.e. the R-DMA module, and the first data writing unit <NUM>, i.e. the W-DMA module. For example, the first data reading unit <NUM> and the first data writing unit <NUM> can be managed by the HPS unit <NUM> by using a control algorithm that can be implemented as portions of software code, e.g. written in the C programming language, which can be loaded into the HPS unit <NUM> from the memory means <NUM> via the bus <NUM>.

With reference to <FIG>, the following will describe the data reading interface module <NUM> and the data writing interface module <NUM> implemented in the second processing means <NUM> previously described herein with reference to <FIG>.

In particular, the data reading interface module <NUM> is implemented as a computer program product comprising portions of software code, e.g. VHDL software code, which is loaded into the FPGA unit <NUM>.

The data reading interface module <NUM> (see also <FIG>) is adapted to:.

It should be noted that, in the present description, to assert a signal means to set its logic state to "TRUE", whereas to unassert a signal means to set its logic state to "FALSE".

In addition, the first data reading unit <NUM> may comprise a first data reading port <NUM> adapted to send the data reading request signal R-Req and adapted to receive the data reading waiting signal R-Wait and/or to receive the data Q. In addition, the second data reading unit 260a may comprise a second data reading port <NUM> adapted to receive the data reading request signal R-Req and adapted to send the data reading status signal R-Stat and/or to send the data Q. In addition, the data reading interface module <NUM> may comprise a third data reading port <NUM> adapted to receive, e.g. at a first input IN1, the data reading request signal R-Req and adapted to send the data reading waiting signal R-Wait, e.g. from a second output OUT2, and/or to send the data Q, e.g. from a third output OUT3. In addition, the data reading interface module <NUM> may comprise a fourth data reading port <NUM> adapted to send the data reading request signal R-Req, e.g. from a first output OUT1, and adapted to receive the data reading status signal R-Stat, e.g. at a second input IN2, and/or to receive the data Q, e.g. at a third input IN3. In addition, the first data reading port <NUM> and the fourth data reading port <NUM> may be of the master type, whereas the second data reading port <NUM> and the third data reading port <NUM> may be of the slave type.

In addition, the second data reading and writing unit <NUM> may comprise the second data reading unit 260a; in particular, said second data reading and writing unit <NUM> may comprise the FIFO memory module, wherein the data reading status signal R-Stat comprises an empty FIFO memory signal (Empty).

In addition, the first data reading unit <NUM> may comprise a DMA module, i.e. the R-DMA module, wherein the data reading waiting signal R-Wait comprises a waitrequest signal. Similarly, the data writing interface module <NUM> is implemented as a computer program product comprising portions of software code, e.g. VHDL software code, which is loaded into the FPGA unit <NUM>.

The data writing interface module <NUM> (see also <FIG>) is adapted to:.

For example, the first data writing unit <NUM> may comprise a first data writing port <NUM> adapted to send the data writing request signal W-Req and adapted to receive the data writing waiting signal W-Wait and/or to send the data Q. In addition, the second data writing unit 260b may comprise a second data writing port <NUM> adapted to receive the data writing request signal W-Req and adapted to send the data writing status signal W-Stat and/or to send the data Q. In addition, the data writing interface module <NUM> may comprise a third data writing port <NUM> adapted to receive, e.g. at a fourth input IN4, the data writing request signal W-Req and adapted to send the data writing waiting signal W-Wait, e.g. from a fifth output OUT5, and/or to receive the data Q, e.g. at a sixth input IN6. In addition, the data writing interface module <NUM> may comprise a fourth data writing port <NUM> adapted to send the data writing request signal W-Req, e.g. from a fourth output OUT4, and adapted to receive the data writing status signal W-Stat, e.g. at a fifth input IN5, and/or to send the data Q, e.g. from a sixth output OUT6.

In addition, the first data writing port <NUM> and the fourth data writing port <NUM> may be of the master type, whereas the second data writing port <NUM> and the third data writing port <NUM> may be of the slave type.

In addition, the second data reading and writing unit <NUM> may comprise the second data writing unit 260b; in particular, said second data reading and writing unit <NUM> may comprise the FIFO memory module, wherein the data writing status signal W-Stat comprises a full FIFO memory signal (Full).

In addition, the first data writing unit <NUM> comprises a DMA module, i.e. the W-DMA module, wherein the data writing waiting signal W-Wait comprises a waitrequest signal.

It should be noted that the R-Req, R-Stat, R-Wait, W-Req, W-Stat and W-Wait signals may be binary signals, i.e. they may be binary electric signals for which one can determine a high voltage value, indicated as "<NUM>", and a low voltage value, indicated as "<NUM>". According to a positive logic, the high value "<NUM>" is associated with a "TRUE" logic state, whereas the low value "<NUM>" is associated with a "FALSE" logic state.

Alternatively, according to a negative logic, the high value "<NUM>" is associated with the "FALSE" logic state, whereas the low value "<NUM>" is associated with the "TRUE" logic state. In the present description, to assert a signal means to set its logic state to "TRUE", whereas to unassert a signal means to set its logic state to "FALSE".

With reference to <FIG>, said R-Req, R-Stat, R-Wait, W-Req, W-Stat and W-Wait signals are considered herein in accordance with a positive logic. In particular, the following table describes in more detail the above-mentioned R-Req, R-Stat, R-Wait, W-Req, W-Stat and W-Wait signals.

Advantageously, the data reading interface module <NUM> and the data writing interface module <NUM> make it possible to regulate the flow of data Q by means of the R-Stat, R-Wait, W-Stat and W-Wait signals, so that the control algorithm of the first data reading unit <NUM> and first data writing unit <NUM>, i.e. of the R-DMA and W-DMA modules, can be programmed to allow data transfers Q exceeding the size of the FIFO memory (<NUM>,<NUM> binary words), thus considerably improving the transfer speed of the data Q in the system <NUM>.

In particular, considering that the first data reading unit <NUM> comprises the R-DMA module and that the first data writing unit <NUM> comprises the W-DMA module, for the control algorithm in the HPS unit to be able to manage the first data reading unit <NUM> and the first data writing unit <NUM> it is necessary to know one or more of the following address values: an address value of the second data reading port <NUM>, an address value of the second data writing port <NUM>, an address value of the control port <NUM> of each DMA module, and an address value corresponding to the base of the usable portion of SDRAM memory.

Such addresses can be determined as follows:.

Those addresses which are useful for managing the R-DMA and W-DMA modules, the SDRAM memory and the FIFO memory are listed in the following table.

In Table <NUM>, the LW_BASE value corresponds to a predefined parameter named LT_LWFPGASLVS_OFST, which can be retrieved from the "hps. h" file supplied by Altera in the installation folder of Quartus-prime reserved for the specific libraries of the device in use (a Cyclone V in this case), while the R-DMA _BASE and W-DMA_BASE values can be found in the Qsys screen of the Quartus-prime platform or in the "*. h" files generated in Altera SoC EDS by means of the sopc-create-header-files command (to execute the command, it is necessary to have available the "*. sopcinfo" file relating to the project generated by the Quartus-prime platform during the compilation phase).

For the SDRAM_BASE address, no offset is considered: each DMA module is connected to the HPS unit <NUM> through the second interface <NUM> (FPGA -> HPS), which sees an L3 address-space, wherein the first 2GB are mapped in the SDRAM; it is then sufficient to define a SDRAM portion reserved for data transfer. Lastly, for the SDRAM_BASE address, no offset is considered: such address can be retrieved from the "*. h" files or from the Qsys screen on the Quartus-prime platform. Note that, for simultaneously reading from and writing to the FIFO memory module, it is possible to define two different addresses for the data reading and writing ports, or else to use two different FIFO memory modules. Note also that, in order to be able to use all the above-described addresses, it will first be necessary to map the memory area where they are located in the user-space by using the mmap command, which will return a pointer to the first address of the mapped memory area. In addition, it must be pointed out that the Linux operating system, preinstalled in the development board, normally uses all the SDRAM, and it is therefore necessary to reserve a SDRAM portion for data transfer; this can be done, for example, by executing the following U-BOOT command:
$ setenv mmcboot 'setenv bootargs console=ttyS0,<NUM> mem=<NUM> root=${mmcroot} rw rootwait;bootz ${loadaddr} - ${fdtaddr}' $ saveenv.

In this case, the SDRAM dedicated to the Linux operating system will be reduced to 800MB; therefore, the SDRAM address to be communicated to the R-DMA and W-DMA modules will be 0x32000000 (address of the 800th MB).

In order to execute a bidirectional data transfer from the memory means <NUM>, i.e. from the SDRAM memory, to the second data reading and writing unit <NUM>, i.e. to the FIFO memory module, the control algorithm in the HPS unit <NUM> must be able to write or read one or more of the following registers of the first data reading unit <NUM>, i.e. of the R-DMA module, and of the first data writing unit <NUM>, i.e. of the W-DMA module: a status register, a read register, a write register, a transfer length register, and a control register. Such registers are accessible, for each R-DMA and W-DMA module, by respectively adding to the above-described LW_BASE+R-DMA_BASE and LW_BASE+W-DMA_BASE addresses a further offset value as specified in the following table.

The following will describe such registers in detail; in particular, the status register is described in the following table.

The read register contains the first address from which each R-DMA and W-DMA module reads the data Q to be transferred; the subsequent addresses are obtained by suitably incrementing this address, depending on the size of the individual elements of the transfer. When reading from a constant address is desired (as is the case when reading from the FIFO module), it is necessary to set to <NUM> the RCON bit in the control register. The size of this register is defined when the first reading unit <NUM> and the first writing unit <NUM> are generated, and may be sufficiently large to identify all the slave peripherals connected to the first data reading port <NUM> of each R-DMA and W-DMA module.

The write register contains the first address whereto each R-DMA and W-DMA module writes the data Q to be transferred; the subsequent addresses are obtained by suitably incrementing this address, depending on the size of the individual binary words of the transfer. When writing to a constant address is desired (as is the case when writing to the FIFO module), it is necessary to set to <NUM> the WCON bit in the control register. The size of this register is defined when the system is generated, and is sufficiently large to identify all the slave peripherals connected to the first data writing port <NUM> of each R-DMA and W-DMA module.

The length register contains a number of bytes of the data Q to be transferred, and its value is progressively decremented during the transfer: when it reaches <NUM>, the LEN bit in the status register is set to <NUM> and the transfer ends.

The control register consists of single bits that specify the behaviour of each R-DMA and W-DMA module in accordance with the following table.

It must be pointed out that, of all the bits that define the size of the binary words to be transferred, only one can be set to <NUM>, otherwise the behaviour of the DMA module will be undetermined.

With reference to <FIG>, <FIG>, the following will describe a method for interfacing the first data reading unit <NUM> with the second data reading unit 260a, both of which are operatively connected to the data reading interface module <NUM>, in accordance with the present embodiment of the invention.

At step <NUM>, a data reading request phase is carried out, in which the data reading request signal R-Req is received by the data reading interface module <NUM>. Said data reading request signal R-Req is asserted and sent by the first data reading unit <NUM>.

At step <NUM>, a reading status signalling phase is carried out, in which the data reading status signal R-Stat is received by the data reading interface module <NUM>, wherein the data reading status signal R-Stat is sent by said second data reading unit 260a; the data reading status signal R-Stat is asserted in the absence of data Q in said second data reading unit 260a.

At step <NUM>, a reading status verification phase is carried out, in which the data reading interface module <NUM> verifies if the data reading status signal R-Stat is asserted, in which case the data reading interface module <NUM> will execute step <NUM>, otherwise it will execute step <NUM>.

At step <NUM>, a data reading waiting phase is carried out, in which the data reading request signal R-Req is unasserted and sent to the second data reading unit 260a by the data reading interface module <NUM>, and the data reading waiting signal R-Wait is asserted and sent to the first data reading unit <NUM> by the data reading interface module <NUM>.

At step <NUM>, a data reading phase is carried out, in which the data reading interface module <NUM> sends the data reading request signal R-Req to the second data reading unit 260a, and in which the data reading interface module <NUM> receives the data Q from the second data reading unit 260a and sends said data Q to the first data reading unit <NUM>.

For example, the first data reading unit <NUM> may comprise the first data reading port <NUM>, which sends the data reading request signal R-Req and receives the data reading waiting signal R-Wait and/or receives the data Q.

In addition, the second data reading unit 260a may comprise the second data reading port <NUM>, which receives the data reading request signal R-Req and sends the data reading status signal R-Stat and/or sends the data Q.

In addition, the data reading interface module <NUM> may comprise the third data reading port <NUM>, which receives the data reading request signal R-Req and sends the data reading waiting signal R-Wait and/or sends the data Q.

Lastly, the data reading interface module <NUM> may comprise a fourth data reading port <NUM>, which sends the data reading request signal R-Req and receives the reading status signal R-Stat and/or receives the data Q.

For example, the first data reading port <NUM> and the fourth data reading port <NUM> may be of the master type, whereas the second data reading port <NUM> and the third data reading port <NUM> may be of the slave type.

For example, the second data reading and writing unit <NUM> may comprise the second data reading unit 260a; in particular, said second data reading and writing unit <NUM> may comprise the FIFO memory module, wherein the data reading status signal R-Stat comprises an empty FIFO memory signal (Empty).

For example, the first data reading unit <NUM> may comprise a DMA module, i.e. the R-DMA module, wherein the data reading waiting signal R-Wait comprises the waitrequest signal.

It will be apparent to those skilled in the art that the above-described method for interfacing the first data reading unit <NUM> with the second data reading unit 260a is implemented in the FPGA unit <NUM> by means of a computer program product comprising portions of software code, e.g. VHDL software code, which is loaded into the FPGA unit <NUM> in order to implement the data reading interface module <NUM>. This will allow the system <NUM> to include the FPGA unit <NUM> adapted to implement the data reading interface module <NUM> in accordance with the method for interfacing the first data reading unit <NUM> with the second data reading unit 260a, as described above with reference to steps <NUM> to <NUM>.

Similarly, with reference to <FIG>, <FIG>, the following will describe a method for interfacing the first data writing unit <NUM> with the second data writing unit 260b, both of which are operatively connected to the data writing interface module <NUM>, in accordance with the present embodiment of the invention.

At step <NUM>, a data writing request phase is carried out, in which the data writing request signal W-Req is received by the data writing interface module <NUM>, wherein the data writing request signal W-Req is asserted and sent by the first data writing unit <NUM>.

At step <NUM>, a writing status signalling phase is carried out, in which the data writing status signal W-Stat is received by the data writing interface module <NUM>, wherein the data writing status signal W-Stat is sent by the second data writing unit 260b; the data writing status signal W-Stat is unasserted in the absence of data Q in the second data writing unit 260b.

At step <NUM>, a writing status verification phase is carried out, in which the data writing interface module <NUM> verifies if said data writing status signal W-Stat is asserted, in which case the data writing interface module <NUM> will execute step <NUM>, otherwise it will execute step <NUM>.

At step <NUM>, a data writing waiting phase is carried out, in which the data writing request signal W-Req is unasserted and sent to the second data writing unit 260b by the data writing interface module <NUM>, and the data writing waiting signal W-Wait is asserted and sent to the first data writing unit <NUM> by the data writing interface module <NUM>.

At step <NUM>, a data writing phase is carried out, in which the data writing interface module <NUM> sends the data writing request signal W-Req to the second data writing unit 260b, and the data writing interface module <NUM> receives the data Q from the first data writing unit <NUM> and sends the data Q to the second data writing unit 260b.

For example, the first data writing unit <NUM> may comprise the first data writing port <NUM>, which sends the data writing request signal W-Req and receives the data writing waiting signal W-Wait and/or sends the data Q. In addition, the second data writing unit 260b may comprise the second data writing port <NUM>, which receives the data writing request signal W-Req and sends the data writing status signal W-Stat and/or receives the data Q. In addition, the data writing interface module <NUM> may comprise a third data writing port <NUM>, which receives the data writing request signal W-Req and sends the data writing waiting signal W-Wait and/or receives the data Q. Lastly, the data writing interface module <NUM> may comprise the fourth data writing port <NUM>, which sends the data writing request signal W-Req and receives the data writing status signal W-Stat and/or sends the data Q.

For example, the first data writing port <NUM> and the fourth data writing port <NUM> are of the master type, whereas the second data writing port <NUM> and the third data writing port <NUM> are of the slave type.

For example, the second data reading and writing unit <NUM> may comprise the second data writing unit 260b; in particular, said second data reading and writing unit <NUM> may comprise the FIFO memory module, wherein the data writing status signal W-Stat comprises a full FIFO memory signal (Full).

For example, the first data writing unit <NUM> may comprise a DMA module, i.e. the W-DMA module, wherein the data writing waiting signal W-Wait comprises a waitrequest signal.

It will be apparent to those skilled in the art that the above-described method for interfacing the first data writing unit <NUM> with the second data writing unit 260b is implemented in the FPGA unit <NUM> by means of a further computer program product comprising portions of software code, e.g. VHDL software code, which is loaded into the FPGA unit <NUM> in order to implement the data writing interface module <NUM>. This will allow the system <NUM> to include the FPGA unit <NUM> adapted to implement the data writing interface module <NUM> in accordance with the method for interfacing the first data writing unit <NUM> with the second data writing unit 260b, as described above with reference to steps <NUM> to <NUM>.

The advantages of the present invention are apparent from the above description.

The present invention advantageously provides a method for interfacing a first data reading unit with a second data reading unit and a method for interfacing a first data writing unit with a second data writing unit, as well as respective data reading and data writing interface modules, which ensure highly configurable data management for the memory buffers of the second reading unit and second writing unit.

A further advantage of the present invention lies in the fact that it provides a data reading interface module and a data writing interface module that make it possible to regulate the data flow by means of signals exchanged between the first data reading unit and the second data reading unit and between the first data writing unit and the second data writing unit, so that the control algorithm of the first data reading unit and of the first data writing unit can be programmed in such a way as to allow for data transfers exceeding the size of the memory buffers, thereby considerably improving the data transfer speed of the data processing and/or acquisition system.

Claim 1:
Method for interfacing a first data reading unit (<NUM>) with a second data reading unit (260a) operatively connected to a data reading interface module (<NUM>), said method comprising:
- a data reading request phase, in which a data reading request signal (R-Req) is received by said data reading interface module (<NUM>), said data reading request signal (R-Req) being asserted and sent by said first data reading unit (<NUM>);
- a reading status signalling phase, in which a data reading status signal (R-Stat) is received by said data reading interface module (<NUM>), wherein the data reading status signal (R-Stat) is sent by said second data reading unit (260a), said data reading status signal (R-Stat) being asserted in the absence of data (Q) in said second data reading unit (260a);
- a reading status verification phase, in which said data reading interface module (<NUM>) verifies if said data reading status signal (R-Stat) is asserted, in which case said data reading interface module (<NUM>) will execute a data reading waiting phase, otherwise it will execute a data reading phase, wherein:
- in said data reading waiting phase, the data reading request signal (R-Req) is unasserted and sent to said second data reading unit (260a) by said data reading interface module (<NUM>), and a data reading waiting signal (R-Wait) is asserted and sent to said first data reading unit (<NUM>) by said data reading interface module (<NUM>);
- in said data reading phase, said data reading interface module (<NUM>) sends said data reading request signal (R-Req) to said second data reading unit (260a), and wherein said data reading interface module (<NUM>) receives the data (Q) from said second data reading unit (260a) and sends said data (Q) to said first data reading unit (<NUM>).