Patent Description:
As an example, servers in a data center are increasingly consuming large amounts of power. The consumption of power is partly the result of power loss from the dissipation of energy even when the CMOS circuits are inactive. This is because even when such circuits, such as random-access memories, are inactive and are not consuming any dynamic power, they still consume power because of the need to maintain the state of CMOS transistors. In addition, because CMOS circuits are powered using DC voltage, there is a certain amount of current leakage even when the CMOS circuits are inactive. Thus, even when such circuits are not processing operations, such as read/write, power is wasted not only as a result of the requirement to maintain the state of the CMOS transistors, but also as a result of the current leakage.

An alternative approach to CMOS technology-based memory is a superconducting logic-based memory. <CIT> describes one example includes a memory circuit. The memory circuit includes a memory array in which contiguous rows of the memory array are organized as a write-bypass portion that comprises a first portion of the rows and a main memory portion that includes a remaining portion of the rows. A given data word is stored in each of a row in the write-bypass portion and another row in the main memory portion during a data write operation in response to word-write signals and bit-write signals associated with each of the respective plurality of contiguous columns. The circuit also includes a control logic configured to store data associated with storage locations of the given data word in each of the row in the write-bypass portion and the other row in the main memory portion to facilitate access of the given data word during a data read operation. <CIT> describes one embodiment includes a superconductive gate system. The superconductive gate system includes a Josephson D-gate circuit comprising a bi-stable loop configured to store a digital state as one of a first data state and a second data state in response to an enable single flux quantum (SFQ) pulse provided on an enable input and a respective presence of or absence of a data SFQ pulse provided on a data input. The digital state can be provided at an output. The readout circuit is coupled to the output and can be configured to reproduce the digital state as an output signal.

The present invention is set out in independent claims <NUM> and <NUM>.

Preferred aspects are defined in the dependent claims <NUM>-<NUM>, <NUM>-<NUM>.

The scope of protection of the present invention is defined by appended claims <NUM>-<NUM>.

Examples described in this disclosure relate to superconducting logic based memory systems, including current-based superconductor memory systems and memory cells. Certain examples relate to a memory cell that includes a storage circuit implemented by a differential flip-flop (DFF) and a read superconducting quantum interference device (SQUID). The memory cell is coupled to a read word line and a read bit line that do not use a Josephson transmission line (JTL) to couple signals to the memory cell. This advantageously speed up the memory cell read operation. The memory cell may be implemented using any single flux quantum (SFQ) compatible logic. One example of such logic is the reciprocal quantum logic (RQL). Thus, certain examples further relate to reciprocal quantum logic (RQL) compatible memory cells. Unlike CMOS transistors, the RQL circuits are superconductor circuits that use Josephson junction based devices. An exemplary Josephson junction may include two superconductors coupled via a region that impedes current. The region that impedes current may be a physical narrowing of the superconductor itself, a metal region, or a thin insulating barrier. As an example, the Superconductor-Insulator-Superconductor (SIS) type of Josephson junctions may be implemented as part of the RQL circuits. As an example, superconductors are materials that can carry a direct electrical current (DC) in the absence of an electric field. Such materials have zero resistance. As an example, at temperatures below Tc (e.g., <NUM>), niobium is superconductive; however, at temperatures above Tc, it behaves as a normal metal with electrical resistance. Thus, in the SIS type of Josephson junctions, superconductors may be Niobium superconductors and insulators may be Al<NUM>O<NUM> barriers. In SIS type junctions, the superconducting electrons are described by a quantum mechanical wave-function. A changing phase difference in time of the phase of the superconducting electron wave-function between the two superconductors corresponds to a potential difference between the two superconductors. In RQL circuits, in one example, the SIS type junction may be part of a superconducting loop. When the potential difference between the two superconductors is integrated with respect to time over one cycle of phase change, the magnetic flux through the loop changes by an integer multiple of a single quantum of magnetic flux. The voltage pulse associated with the single quantum of magnetic flux is referred to as a single-flux-quantum (SFQ) pulse. As an example, overdamped Josephson junctions can create individual single-flux-quantum (SFQ) pulses. In RQL circuits, each Josephson junction may be part of one or more superconducting loops. The phase difference across the junction may be modulated by the magnetic flux applied to the loop.

Various RQL circuits, including transmission lines, can be formed by coupling multiple Josephson junctions by inductors or other components, as needed. SFQ pulses can travel via these transmission lines under the control of at least one clock. The SFQ pulses can be positive or negative. As an example, when a sinusoidal bias current is supplied to a junction, then both positive and negative pulses can travel rightward, during opposite clock phases, on a transmission line. The RQL circuits may advantageously have zero static power dissipation because of the absence of bias resistors. In addition, the RQL circuits may be powered using alternating current (AC) power. The AC power supply may also act as a stable clock reference signal for the RQL circuits. In one example, the digital data may be encoded using a pair of positive and negative (reciprocal) SFQ pulses. As an example, a logical one bit may be encoded as a reciprocal pair of SFQ pulses generated in the positive and negative phases of a sinusoidal clock. A logical zero bit may be encoded by the absence of positive/negative pulse pairs during a clock cycle. The positive SFQ pulse may arrive during the positive part of the clock, whereas the negative pulse may arrive during the negative part of the clock.

The building blocks of exemplary RQL circuits may include various types of logic gates. Exemplary logic gates include an AND gate, an OR gate, a logical A- and-not-B (AanB) gate, and a logical AND & OR (AndOr) gate. The AanB gate may have two inputs and one output (Q). An input pulse A may propagate to output Q unless an input pulse B comes first. The AndOr gate may have two inputs and two outputs (Q1 and Q2). The first input pulse, input pulse A or input pulse B, goes to output Q1 and the second input pulse goes to output Q2. The logical behavior of these gates may be based on the reciprocal data encoding mentioned earlier. As an example, a positive pulse changes the internal flux state of the inductive loop, but the trailing negative pulse erases the internal state every clock cycle, which in turn produces combinational logic behavior.

Microwave signals (e.g., SFQ pulses) may be used to control the state of a memory cell. During read/write operations, word-lines and bit-lines may be selectively activated by SFQ pulses arriving via an address bus. These pulses may, in turn, control word-line and bit-line drivers that may provide word-line and bit-line currents to the relevant memory cells. As an example, such a memory cell may be read out using a superconducting quantum interference device (SQUID). The memory cell may include a SQUID and a storage element, which may be configured such that under the application of appropriate amounts of current bias and magnetic flux, the memory cell may be in a logic '<NUM>' state or in a logic '<NUM>' state. In one example, if the memory cell is in the logic '<NUM>' state, under the application of a current via a word-line, the SQUID may transition into a "voltage state. " A sense amplifier coupled to the memory cell may sense the voltage as being representative of the logic '<NUM>' state. The logic '<NUM>' state may correspond to a "substantially zero-voltage state," such that in the logic '<NUM>' state, despite the application of a current via a word-line, the SQUID may stay in the "substantially zero-voltage state. " The sense amplifier may sense this as being representative of the logic '<NUM>' state.

Memory cells may be arranged in rows and columns, such that each row can be activated by a common flux bias (e.g., a read word-line signal) and each bit-line may form a transmission line that may propagate the output of the memory cells in a voltage state to a sense amplifier at one end of the column. Memory cells in a column may be serially biased by a common current source; for example, a flux pump.

<FIG> shows a block diagram of a memory cell <NUM> in accordance with one example. Memory cell <NUM> may include a storage circuit <NUM> and a read superconducting quantum interference device (SQUID) <NUM>. Storage circuit <NUM> may act as a storage element corresponding to memory cell <NUM>. In this example, storage circuit <NUM> may be implemented as a differential flip-flop (DFF). In one example, the DFF may be compatible with RQL logic. In another example, the DFF may be compatible with quantum flux parametron (QFP) logic. Memory cell <NUM> may be coupled to a write word line (WWL) and write bit line (WBL). Memory cell <NUM> may further be coupled to a read word line (RWL) and a read bit line (RBL). In this example, WWL is coupled via a Josephson transmission line (JTL) element <NUM> to storage circuit <NUM>. WWL is further coupled via another JTL element <NUM> to the next memory cell in the row of memory cells. WBL is coupled via a JTL element <NUM> to storage circuit <NUM>. WBL is further coupled via another JTL element <NUM> to the next memory cell in the column of memory cells. RWL is coupled as a transmission line to read SQUID <NUM>. Similarly, RBL is coupled as a transmission line to read SQUID <NUM>. Notably, in this example, neither RWL nor RBL is coupled via a JTL element. The transmission line coupling allows read operations to be performed at a faster speed than would be possible otherwise. Although <FIG> shows a certain number of components of memory cell <NUM> arranged in a certain manner, there could be more or fewer number of components arranged differently.

In terms of the operation of memory cell <NUM>, when the RWL line becomes active additional current is added to the current from storage circuit <NUM>. If the state of memory cell <NUM> is a logic "<NUM>," the sum of the two currents provides enough current to put read SQUID <NUM> into a voltage state and a read pulse is transmitted via the RBL. The read pulse can be detected by a circuit, such as a sense amplifier. Alternatively, if the state of memory cell <NUM> is a logic "<NUM>," despite the RWL line being active, the read SQUID stays in a state such that no pulse is sent out of memory cell <NUM>. In this example, the logic '<NUM>' state may correspond to a "voltage state," in which a sense amplifier coupled to memory cell <NUM> may sense the current as being representative of the logic '<NUM>' state. The logic '<NUM>' state may correspond to a "substantially zero-voltage state," such that the sense amplifier may sense this as being representative of the logic '<NUM>' state.

<FIG> shows a memory circuit <NUM> of a memory cell <NUM> in accordance with one example. In this example, memory circuit <NUM> may include a differential flip-flop (DFF) <NUM> and a read SQUID <NUM>. In one example, the DFF may be compatible with RQL logic. In another example, the DFF may be compatible with quantum flux parametron (QFP) logic. Memory circuit <NUM> may be coupled to a write word line (WWL) and write bit line (WBL). The WWL signals may be received via the terminal labeled WWL_IN. The WWL signals may be output via the terminal labeled WWL_OUT. The WBL signals may be received via the terminal labeled WBL_IN and they may be output via the terminal labeled WBL_OUT. Memory circuit <NUM> may further be coupled to a read word line (RWL) and a read bit line (RBL). The RWL signals may be received via the terminal labeled RWL_IN. The RWL signals may be output via the terminal labeled RWL_OUT. The RBL signals may be received via the terminal labeled RBL_IN and they may be output via the terminal labeled RBL_OUT. In this example, DFF <NUM> is coupled to the WWL_IN terminal via a Josephson transmission line (JTL) element <NUM> and DFF <NUM> is coupled to the WWL_OUT terminal via a JTL element <NUM>. In addition, in this example, DFF <NUM> is coupled to the WBL_IN terminal via JTL element <NUM> and DFF <NUM> is coupled to the WBL_OUT terminal via a JTL element <NUM>. Read SQUID <NUM> is coupled to the RWL via the RWL_IN terminal and the RWL_OUT terminal. Read SQUID <NUM> is coupled to the RBL via the RBL_IN terminal and the RBL_OUT terminal. Notably, in this example falling under the scope of protection of the appended claims, neither RWL nor RBL is coupled via a JTL element to read SQUID <NUM>. The transmission line couplings (e.g., transmission line <NUM> and transmission line <NUM>) allow read operations to be performed at a faster speed than would be possible otherwise. This is because by not including the JTL elements, the signals on the transmission lines need not be phase-aligned with respect to the JTL elements being clocked by a resonator clock. Conversely, pulses travel on the transmission lines at the speed of light in this medium. Notably, in this example, while transmission lines <NUM> and <NUM> are shown as discrete elements, they are designed to incorporate the inductances and capacitances of the devices (e.g. transformers and Josephson junctions) that they are in series with, so that the entire path acts as a single transmission line.

With continued reference to <FIG>, DFF <NUM> may include an inductor <NUM>, a Josephson junction (JJ) <NUM>, and a Josephson junction (JJ) <NUM>. JJ <NUM> may be coupled to one end of inductor <NUM> and an output of JTL element <NUM> may be coupled to the other end of inductor <NUM>. Another inductor <NUM> may be coupled between JJ <NUM> and another Josephson junction (JJ) <NUM>. One end of each of JJ <NUM> and JJ <NUM> may be coupled to ground. Another inductor <NUM> may be coupled to one of end of inductor <NUM> and one end of JJ <NUM>. The other end of inductor <NUM> may be coupled to an input of JTL element <NUM>, which in turn may be coupled to the WBL_OUT terminal. The WWL may extend past memory circuit <NUM> via a coupling to the WWL_OUT terminal through JTL element <NUM>. DFF <NUM> may further include a JTL element <NUM> to provide an output of DFF <NUM>. The output of DFF <NUM> may be a current, whose amount depends on a state of the DFF.

Still referring to <FIG>, read SQUID <NUM> may include transformers <NUM> and <NUM>. Read SQUID <NUM> may further include Josephson junction (JJ) <NUM> and Josephson junction (JJ) <NUM>. Transformer <NUM> may include inductors <NUM> and <NUM> configured to couple the current output by DFF <NUM> to read SQUID <NUM>. Transformer <NUM> may include inductors <NUM> and <NUM> to couple any signals received via the RWL (via the RWL_IN terminal) to read SQUID <NUM>. In terms of the operation of read SQUID <NUM>, when DFF <NUM> has a logic "<NUM>" state, then DFF <NUM> may not provide any current to read SQUID <NUM>, which in turn may keep read SQUID <NUM> in a half-select state. On the other hand, when DFF <NUM> has a logic "<NUM>" state, then DFF <NUM> may provide some current to read SQUID <NUM>. When the RWL has a read signal asserted on it, the current provided by DFF <NUM> when combined with the current from the read signal may put read SQUID <NUM> into a "voltage state. " The sum of the two currents in read SQUID <NUM> is shown as a circular arrow. In any case, similar to as described with respect to <FIG>, a sense amplifier coupled to read SQUID <NUM> may sense a state of memory circuit <NUM>. In one example, the presence or absence of a current pulse, voltage, or another parameter, once amplified by the sense amplifier, may determine the state of memory cell <NUM> as logic '<NUM>' or logic '<NUM>'. As shown in <FIG>, the RWL and the RBL are coupled via transmission lines and do not include any JTL elements; instead they are represented as transmission lines <NUM> and <NUM> respectively.

In terms of the operation of memory circuit <NUM>, DFF <NUM> may act as a storage circuit for storing a state of memory cell <NUM> and read SQUID <NUM> may act as a read circuit for reading out the state of memory cell <NUM>. Additional details regarding the operation of memory circuit <NUM> are explained with the help of <FIG>, which shows a timing diagram <NUM> corresponding to operations associated with memory circuit <NUM>.

In this example, it is assumed that an initial state, represented by the data waveform, of DFF <NUM> is a logic "<NUM>" state. In this example, the rwl waveform corresponds to the signals (e.g., pulses) on the read word line (RWL). The WWL waveform corresponds to the signals (e.g., pulses) on the write word line (WWL). The rbipulse waveform corresponds to the pulses on the read bit line (RBL). The solid line that overlaps the rbipulse waveform corresponds to the phase advance on the read bit line (RBL). As shown in <FIG>, in this example, when the rising edge on the WWL coincides with a logic "<NUM>" DATA state, then the state of DFF <NUM> changes from a logic "<NUM>" state to a logic "<NUM>" state. If DFF <NUM> is in a logic "<NUM>" state, then when a falling edge of WWL coincides with logic "<NUM>" DATA state, the state of DFF <NUM> changes from a logic "<NUM>" state to a logic "<NUM>" state. If the WWL and WBL signals are timed such that the WBL has a logic "<NUM>" when the pulse on the WWL rises and a logic "<NUM>" when the pulse on the WWL falls, the state of the memory remains unchanged. In addition, as shown in <FIG>, in this example, when the pulse on the RWL arrives a state of DFF <NUM> is read out using read SQUID <NUM>. When reading a logic "<NUM>" state, there is phase advance on the RBL (as shown by the rbiphase waveform); on the other hand, when reading a logic "<NUM>" state, there is no phase advance on the RBL. When reading a logic "<NUM>" from the DFF while the RWL is active the SQUID goes into a voltage state sending a voltage pulse up the RBL. This voltage pulse is often measured as an analog phase advance at the sense amp. In addition, in this example, as shown in <FIG>, DFF <NUM> allows for writing of logic "<NUM>" and logic "<NUM>" values and also allows bit-enabled "non-writes. " In this example, writes to DFF <NUM> happen on the rising or falling edges of the WWL signal. If the WBL has a logic "<NUM>" signal on it when the WWL rises, DFF <NUM> is written to a logic "<NUM>" state. If the WBL has a logic "<NUM>" signal on it when the WWL falls, DFF <NUM> is written into a logic "<NUM>" state. If the WBL has a logic "<NUM>" signal when the WWL rises and a logic "<NUM>" when the WWL falls, the state of DFF <NUM> is maintained.

<FIG> shows a diagram of a memory system <NUM> in accordance with one example. Memory system <NUM> may include a memory array <NUM> of memory cells (e.g., memory cell <NUM>) arranged in rows and columns. Memory system <NUM> may further include a row decoder <NUM> that may be configured to decode row control/address signals. Row decoder <NUM> may further be coupled to word-line drivers <NUM>. Word-line drivers <NUM> may include circuitry to provide word-line read/write current to a subset or all of the memory cells associated with a selected word-line for any read or write operations. Word-line drivers <NUM> may provide such current via word-lines <NUM>. Word-lines <NUM> may include both read word-lines and write word-lines. In other words, different word-lines may be used to provide current to the selected memory cells for read or write operations.

Memory system <NUM> may further include column decoder <NUM> that may be configured to decode column control/address signals. Column decoder <NUM> may further be coupled to bit-line drivers <NUM>. Bit-line drivers <NUM> may include circuitry to provide bit-line read current to a subset or all of the memory cells associated with a selected bit-line for any read or write operations. Bit-line drivers <NUM> may provide such current via bit-lines <NUM>. Bit-lines <NUM> may include both read bit-lines and write bit-lines. In other words, different bit-lines may be used to provide current to the selected memory cells for read or write operations. By using row and column addresses, any of the memory cells could be accessed using an address. Each of the bit-lines (e.g., bit-lines <NUM>) may further be coupled to, via signal lines <NUM>, sense amplifier <NUM> for sensing bit-lines to determine the logical state of selected memory cells. The coupling between memory array <NUM> of memory cells and sense amplifier <NUM> may include radio frequency (RF) transmission lines. The memory cells in each column may be serially current-biased by a common current source (e.g., a flux pump). As described earlier, bit-lines <NUM> may be used to couple this current to each of the memory cells in a column. As described with respect to <FIG>, sense amplifier <NUM> may measure the bit-line current or the bit-line voltage to determine a state of a memory cell. Although <FIG> shows a certain number of components of memory system <NUM> arranged in a certain manner, there could be more or fewer number of components arranged differently.

<FIG> shows a computing system <NUM> including a processor <NUM> coupled to a memory <NUM> via bus <NUM> in accordance with one example. Processor <NUM> may perform read or write operations on memory <NUM>. Additionally, processor <NUM> and memory <NUM> may be used along with other superconducting logic-based devices. In general, any superconducting device operating in cryogenic environments and requiring storage of instructions or data may include memory <NUM>. Furthermore, processor <NUM> need not be in a cryogenic environment; instead, it may operate at non-cryogenic temperatures. In this example, memory <NUM> may be in a separate cryogenic environment and may be coupled via connectors to processor <NUM> in a way that the cryogenic environment can be maintained. Memory <NUM> may be used as part of storage in a data center for delivering cloud-based services, such as software as a service, platform as a service, or other services. Memory system <NUM> may include an array of memory cells (e.g., memory cell <NUM>) arranged in rows and columns. Although <FIG> shows a certain number of components of computing system <NUM> arranged in a certain manner, there could be more or fewer number of components arranged differently.

In accordance with one example, <FIG> shows a flow chart corresponding to a method associated with memory cell <NUM>. Step <NUM> may include applying bit-line current, via a read bit-line not including any Josephson transmission line elements, to a read SQUID associated with the memory cell. The read SQUID may be <NUM> of <FIG>, which may be implemented as read SQUID <NUM> of <FIG>. As explained earlier, a bit-line driver may be used to provide the bit-line current. The bit-line driver may be configured to provide current to the bit line (e.g., the RBL of <FIG> or the RBL of <FIG>).

Step <NUM> may include applying word-line current, via a read word-line not including any Josephson transmission line elements, to a read SQUID associated with the memory cell. As explained earlier, a word-line driver may be used to provide word-line current.

Step <NUM> may include using the read SQUID reading a state of the memory cell from a storage circuit associated with the memory cell. The storage circuit may be storage circuit <NUM>, which may be implemented as DFF <NUM> of <FIG>. Although <FIG> shows the steps being performed in a certain order, at least one of the steps may be performed in a different order. In addition, fewer or additional steps may be performed. Moreover, steps <NUM> and <NUM> may be performed simultaneously. In conclusion, the present disclosure describes a memory sytem according to appended claims <NUM>-<NUM> and a method according to appended claims <NUM>-<NUM>.

It is to be understood that the methods, modules, and components depicted herein are merely exemplary. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application-Specific Standard Products (ASSPs), System-on-a-Chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), etc. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or inter-medial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "coupled," to each other to achieve the desired functionality.

The functionality associated with the examples described in this disclosure can also include instructions stored in a non-transitory media. The term "non-transitory media" as used herein refers to any media storing data and/or instructions that cause a machine, such as processor <NUM>, to operate in a specific manner. Exemplary non-transitory media include non-volatile media and/or volatile media. Non-volatile media include, for example, a hard disk, a solid state drive, a magnetic disk or tape, an optical disk or tape, a flash memory, an EPROM, NVRAM, PRAM, or other such media, or networked versions of such media. Volatile media include, for example, dynamic memory, such as, DRAM, SRAM, a cache, or other such media. Non-transitory media is distinct from, but can be used in conjunction with transmission media. Transmission media is used for transferring data and/or instruction to or from a machine. Exemplary transmission media, include coaxial cables, fiber-optic cables, copper wires, and wireless media, such as radio waves.

Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations are merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

Although the disclosure provides specific examples, various modifications and changes can be made without departing from the scope of the disclosure as set forth in the claims below. Any benefits, advantages, or solutions to problems that are described herein with regard to a specific example are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claim 1:
A memory system (<NUM>) comprising:
an array (<NUM>) of memory cells (<NUM>) arranged in rows and columns;a set of read word-lines coupled to a plurality of memory cells in the array of the memory cells, wherein each of the set of the read word-lines comprises a line not including any Josephson transmission line, JTL, elements;
a set of read bit-lines coupled to the plurality of memory cells (<NUM>) in the array (<NUM>) of the memory cells (<NUM>);
a set of write word-lines coupled to the plurality of memory cells (<NUM>) in the array (<NUM>) of memory cells (<NUM>), wherein each of the set of the write word-lines comprises a line including at least one Josephson transmission line, JTL, element (<NUM>) being clocked by a clock, and wherein each of the plurality of the memory cells (<NUM>) comprises:
at least one storage circuit (<NUM>) and at least one read superconducting quantum interference device, SQUID (<NUM>), wherein a read bit-line corresponding to the set of read bit-lines is coupled to the at least one read SQUID, wherein the read bit-line is not coupled to the at least one read SQUID via a JTL, wherein the at least one storage circuit (<NUM>) is configured to maintain a state of the memory cell (<NUM>), and wherein the at least one read SQUID (<NUM>) is configured to read the state of the memory cell (<NUM>) in response to an application of word-line current provided via a read word-line corresponding to the set of read word-lines, wherein the at least one storage circuit comprises a differential flip-flop, DFF, wherein the DFF is configured to provide a first current to the at least one read SQUID (<NUM>) when the memory cell (<NUM>) is in a logic one state and provide a second current to the at least one read SQUID (<NUM>) when the memory cell (<NUM>) is in a logic zero state, wherein an amount of the first current is higher than an amount of the second current, wherein signals on neither the read bit-line nor the read word-line are phase-aligned with respect to the at least one JTL element being clocked by the clock.