Patent Description:
A superjunction transistor device, which may also be referred to as superjunction MOSFET, may receive across a load path a voltage with a first polarity or a voltage with a second polarity opposite the first polarity. When the load path voltage has the first polarity the MOSFET can be operated in an on-state (switched on state) or an off state (switched off state) by applying a suitable drive voltage to a drive input. When the load path voltage has the second polarity the MOSFET is in a conducting state independent off the drive voltage received at the drive input.

When the load path voltage has the second polarity the MOSFET can be operated in the on-state or the off-state. In the off-state, an internal body diode is forward biased. The operating state in which the MOSFET is in the off-state and the load path voltage has the second polarity may also be referred to as diode state of the MOSFET.

When the MOSFET operates in the diode state, there is a charge carrier plasma including both n-type charge carriers (electrons) and p-type charge carriers (holes) in a drift region of the MOSFET. When the polarity of the load path voltage changes such that the body diode is reverse biased these charge carriers have to be removed before the MOSFET blocks. Further, when the charge carriers forming the plasma have been removed, so that the MOSFET blocks, and as the load path voltage increases a depletion region (space charge regions) is formed in the drift region. Forming this depletion region is associated with a removal of free charge carriers in the drift region and the body region and, therefore, a storing of a fixed net charge in the drift and body region. In a superjunction device, the depletion region also expands in a compensation region that adjoins the drift region and has a doping type complementary to a doping type of the drift region.

Removing the charge carriers of the charge carrier plasma from the transistor device and charging the drift, body and the compensation regions is associated with a charging current, which may also be referred to as reverse recovery current. This current is associated with losses. Basically, the losses associated with changing the operating state of the transistor device from the diode state to the blocking state are given by the integral of the reverse recovery current multiplied with the voltage across a current path through which the charging current flows These losses may occur in the transistor device itself, but may also occur in devices connected to the transistor device. For example, the transistor device may be used as one of two switches in a half-bridge and the change of the operating state of the transistor device from the diode state to the blocking state may be caused by a change of the operating state of the other one of the two switches. In this case, the reverse recovery current may not only flow through the transistor device itself, but may also flow through the other one of the switches, where it may cause losses. The overall losses associated with changing the operating state of the transistor device may be referred to as commutation losses.

<CIT> discloses an electronic circuit. The electronic circuit includes a transistor device that can be operated in a reverse operation mode and a control circuit. The transistor device includes a source region, a drain region, a body region and a drift region, a source electrode electrically connected to the source region, a pn junction formed between the body region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region, and a depletion control structure adjacent the drift region. The depletion control structure has a control terminal and is configured to generate a depletion region in the drift region dependent on a drive signal received at the control terminal. The control circuit is coupled to the control terminal of the depletion control structure and configured to drive the depletion control structure to generate the depletion region when the transistor device is operated in the reverse operation mode. The transistor device may be implemented as a superjunction transistor device.

<CIT> discloses a reverse-blocking transistor device that includes at least one transistor cell. The transistor cell includes a drift region, a source region, a body region arranged between the source region and the drift region, and a drain region.

The drift region is arranged between the body region and the drain region. A gate electrode is arranged adjacent to the body region and dielectrically insulated from the body region by a gate dielectric. A channel region of a doping type complementary to a doping type of the drain region is arranged between the drift region and the drain region. A drift control region is arranged adjacent to the drift region and dielectrically insulated from the drift region and the channel region by a drift control region dielectric. A first switch is coupled between the drift control region and the drain region.

There is a need for reducing losses that are associated with a transition of a superjunction transistor device from a diode state to a blocking state.

One example relates to a method according to claim <NUM>. Another example relates to a transistor arrangement according to claim <NUM>.

Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so that only aspects necessary for understanding these principles are illustrated. In the drawings the same reference characters denote like features.

In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and for the purpose of illustration show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

<FIG> schematically illustrates a transistor arrangement <NUM> with a transistor device. More specifically, <FIG> shows a vertical cross sectional view of a semiconductor body <NUM> in which the transistor device is integrated and circuit symbols of further electronic devices of the transistor arrangement. It should be noted that <FIG> schematically illustrates some features of the transistor device in order to explain its functionality. These features may be arranged in the semiconductor body <NUM> in various ways. Thus, <FIG> rather illustrates which features the transistor device includes, than a specific implementation. Examples for implementing the transistor device are explained in detail herein further below.

Referring to <FIG>, the transistor device includes a drift region <NUM> of a first doping type (first conductivity type), a source region <NUM> of the first doping type and a body region <NUM> of a second doping type (second conductivity type) complementary to the first doping type. One of the first doping type and the second doping type is an n-type and the other one of the first doping type and the second doping type is a p-type. The body region <NUM> separates the source region <NUM> from the drift region <NUM>. Further, the body region <NUM> adjoins the drift region <NUM> so that a pn-junction (represented by a diode in <FIG>) is formed between the body region <NUM> and the drift region <NUM>. This pn-junction is referred to as first pn-junction in the following. Each of the source region <NUM> and the body region <NUM> is connected to a source node S of the transistor device.

According to one example, each of the source region <NUM> and the body region <NUM> is connected to the source node S such that an ohmic contact is formed between the source node S and the respective device region <NUM>, <NUM>. The source node S may be formed by a source metallization (not illustrated) so that the ohmic contact between source and body regions <NUM>, <NUM> and the source node S may include an ohmic contact between the source and body regions <NUM>, <NUM> and the source metallization.

A gate electrode <NUM> is arranged adjacent the body region <NUM> and is dielectrically insulated from the body region <NUM> by a gate dielectric <NUM>. The gate electrode <NUM> is connected to a gate node G and serves to control a conducting channel in the body region <NUM> along the gate dielectric <NUM> between the source region <NUM> and the drift region <NUM>.

The transistor device further includes a drain region <NUM> of the first doping type. The drain region <NUM> is connected to a drain node D, is spaced apart from the body region <NUM> in a current flow direction of the transistor device and is separated from the body region <NUM> by the drift region <NUM>. Optionally, a buffer region <NUM> of the first doping type is arranged between the drain region <NUM> and the drift region <NUM>. The buffer region <NUM> has a lower doping concentration than the drift region <NUM>, for example.

The transistor device is implemented as a superjunction transistor device and further includes a compensation region <NUM> of the second doping type. The compensation region <NUM> adjoins the drift region <NUM> and may or may not adjoin the body region <NUM>. More detailed examples with regard to the arrangement of the compensation region <NUM> relative to the body region <NUM> are explained herein further below. As the doping type of the compensation region <NUM> is complementary to the doping type of the drift region <NUM> a further pn-junction (represented by a diode in <FIG>) is formed between the compensation region <NUM> and the drift region <NUM>. This pn-junction is referred to as second pn-junction in the following. Referring to <FIG>, the drift region <NUM> and the compensation region <NUM> may be implemented in such a way that the second pn-junction essentially extends in the current flow direction. Optionally, as illustrated in dashed lines in <FIG>, the compensation region <NUM> is connected to the source node S.

The transistor device further includes a bias region <NUM>. The bias region <NUM> is a doped region of either the first doping type or the second doping and is coupled to the drift region <NUM>. "Coupling the bias region <NUM> to the drift region <NUM>" includes electrically coupling the bias region <NUM> to the drift region <NUM> in any possible way and may include directly coupling the bias region <NUM> to the drift region <NUM> such that the bias region <NUM> adjoins the drift region <NUM> or may include indirectly coupling the bias region <NUM> to the drift region <NUM>. "Indirectly coupling the bias region <NUM> to the drift region <NUM>" may include coupling the bias region <NUM> to the drift region <NUM> via an electronic switch such as a transistor, for example.

Just for the purpose of illustration, in the transistor device shown in <FIG>, the current flow direction of the transistor device corresponds to a vertical direction z of the semiconductor body <NUM>. The "vertical direction z" of the semiconductor body <NUM> is a direction perpendicular to a first surface <NUM> and a second surface <NUM>, wherein the second surface <NUM> is spaced apart from the first surface <NUM>. In addition to the first and second surfaces <NUM>, <NUM>, which may also be referred to as front and rear surfaces, the semiconductor body <NUM> includes side surfaces (edge surfaces) that each extend from the first surface <NUM> to the second surface <NUM>. These side surfaces, however, are out of view in the section of the semiconductor body <NUM> illustrated in <FIG>.

A transistor device of the type shown in <FIG> in which the current flow direction corresponds to the vertical direction of the semiconductor body <NUM> may be referred to as vertical transistor device. Implementing the transistor device as a vertical transistor device, however, is only an example. The principles explained hereinbefore and hereinabove also apply to a lateral transistor device, which is a transistor device in which the current flow direction corresponds to a lateral direction of the semiconductor body <NUM>. The "lateral direction" is a direction parallel to the first and second surfaces <NUM>, <NUM> of the semiconductor body.

According to one example, the semiconductor body <NUM> includes a monocrystalline semiconductor material. Examples of the monocrystalline semiconductor material include, but are not restricted to, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or the like.

According to one example, the semiconductor body <NUM> includes monocrystalline silicon and the individual active device regions are implemented such that a respective doping concentration is in a range as outlined in the following:.

Referring to the above, the bias region <NUM> may be implemented as a doped region of (<NUM>) the first doping type, or (<NUM>) the second doping type. In the first case (<NUM>), the doping concentration of the bias region <NUM> is in a range of between 1E16 cm-<NUM> and 1E21 cm-<NUM>, for example. In the second case (<NUM>), the doping concentration is in a range of between 1E15 cm-<NUM> and 1E18 cm-<NUM>, for example. In the second case, the bias region <NUM> may be formed by the same process that forms the body region <NUM>, so that the doping concentrations of the body region <NUM> and the bias region <NUM> may essentially be the same.

Referring to the above, an ohmic contact may be formed between the body region <NUM> and the source node S. In this case, the body region <NUM> may include a contact region (not shown) of the second doping type, wherein a doping concentration of the contact region is high enough, to achieve an ohmic contact between the source node S (the source metallization) and the body region <NUM>. The doping concentration is between 1E18 cm-<NUM> and 1E21 cm-<NUM>, for example.

Referring to <FIG>, the bias region <NUM> is connected to a bias node Q, which is explained in detail herein further below. According to one example, an ohmic contact is formed between the bias region <NUM> and the bias node Q. In this case, the bias region <NUM> may include a contact region <NUM> (illustrated in dashed lines) that is of the same doping type as the bias region <NUM> and has a doping concentration that is high enough to achieve an ohmic contact between the bias node Q and the body region <NUM>. The doping concentration of the contact region <NUM> is between 1E18 cm-<NUM> and 1E21 cm-<NUM>, for example. Such contact region <NUM> may be included in each of the examples explained below, although the contact region <NUM> is not illustrated in the further examples. The bias node Q may be formed by a metallization (not shown) separate from the source metallization.

The doping type of the source, drift and drain regions <NUM>, <NUM>, <NUM> defines the conductivity type of the superjunction transistor device. These device regions <NUM>, <NUM>, <NUM> are regions of the first doping type so that the superjunction transistor device is a transistor device of the first conductivity type. More specifically, the superjunction transistor device is an n-type transistor device when the semiconductor regions of the first doping type are n-type semiconductor regions and the semiconductor regions of the second doping type are p-type semiconductor regions, and the superjunction transistor device is a p-type transistor device when the semiconductor regions of the first doping type are p-type semiconductor regions and the semiconductor regions of the second doping type are n-type semiconductor regions. Further, the transistor device can be implemented as an enhancement (normally-off) device or as a depletion (normally-on) device. In an enhancement device, the body regions <NUM> adjoin the gate dielectric <NUM>. In a depletion device, there is a channel region <NUM> (illustrated in dashed lines) of the first doping type that extends from the source region <NUM> to the drift region <NUM> along the gate dielectric <NUM> and is arranged between the gate dielectric <NUM> and the body region <NUM>.

In the transistor device shown in <FIG>, a load path is formed between the drain node D and the source node S. A voltage VDS between these nodes is referred to as load path voltage or drain-source voltage in the following. A drive input is formed by the gate node G and the source node S, for example. A voltage VGS received at the drive input is referred to as drive voltage or gate-source voltage in the following. Dependent on a voltage level of the drive voltage VGS a conducting channel is formed along the gate dielectric <NUM> in the body region <NUM> between the drift region <NUM> and the source region <NUM>.

In a n-type enhancement transistor device, for example, a conducting channel is generated along the gate dielectric <NUM> when the voltage level of the drive voltage VGS is higher than a threshold voltage of the transistor device. The threshold voltage is dependent on the conductivity type of the transistor device and dependent on whether the transistor device is an enhancement device or a depletion device. This is commonly known, so that no further explanation is required in this regard.

The superjunction transistor device shown in <FIG> can be operated in four different operating states:.

In the third operating state (diode state) charge carriers of the first conductivity type are injected by the drain region <NUM> into the drift region <NUM> and charge carriers of the second conductivity type are injected by the body region <NUM> into the drift region <NUM> so that there is a charge carrier plasma including charge carriers of the first and second conductivity type primarily in the drift region <NUM>, the compensation region <NUM> and the optional buffer region <NUM>. In an n-type transistor device, the charge carriers injected by the drain region <NUM> are electrons and the charge carriers injected by the body region <NUM> are holes.

When the transistor device changes from the diode state into the (forward biased) blocking state (the fourth operating state), for example, the charge carriers forming the charge carrier plasma need to be removed from the drift region <NUM> before the transistor device blocks, that is, before a current through the transistor device turns to zero. Furthermore, in the blocking state, charge carriers are stored in a junction capacitance that is formed by the first pn-junction (the pn-junction between the body region <NUM> and the drift region <NUM>) and the second pn-junction(the pn-junction between the drift region <NUM> and the compensation region <NUM>. Switching the superjunction transistor device from the diode state to the blocking state is associated with losses, wherein these losses are essentially given by the integral of the current that removes the charge carrier plasma and charges the junction capacitance multiplied with the voltage across a current path through which the current flows. These losses may occur in the transistor device <NUM> itself, but may also occur in an external device such as another transistor device connected in series with the transistor device <NUM>. The latter is explained with reference to <FIG> herein further below.

In the transistor device <NUM> according to <FIG>, losses associated with changing the operating state of the transistor device from the diode state to the blocking state may be reduced by applying a bias voltage VDEP between the bias region <NUM> and at least one of the compensation region <NUM> and the body region <NUM>, wherein the bias voltage VDEP is different from zero. As outlined in further detail herein below, a polarity of the bias voltage VDEP is such that the pn-junction between the drift region <NUM> and the at least one of the compensation region <NUM> and the body region <NUM> is reverse biased, that is at least one of the second pn-junction and the first pn-junction is reverse biased. The bias voltage may be provided by any kind of voltage source that is configured to provide the bias voltage VDEP and is connected between the bias region <NUM> and the at least one of the compensation region <NUM> and the body region <NUM>. A circuit node Q outside the semiconductor body <NUM> and connected between the voltage source providing the bias voltage VDEP and the bias region <NUM> is referred to as bias node Q in the following.

According to one example, the bias voltage VDEP is applied between the bias region <NUM> and only the compensation region <NUM>. According to another example, the bias voltage VDEP is applied between the bias region <NUM> and both the compensation region <NUM> and the body region <NUM>. According to yet another example, the bias voltage VDEP is applied between the bias region <NUM> and only the body region <NUM>.

Optionally, the bias voltage VDEP is selectively applied between the compensation region <NUM> and the bias region <NUM>. This may be achieved by connecting a switch SDEP in series with the voltage source that provides the bias voltage VDEP. The switch SWDEP, which is also referred to as bias switch in the following, is connected between the voltage source and the bias region <NUM> in the example shown in <FIG>. This, however, is only an example. The bias switch SWDEP may be arranged at any position between the compensation region <NUM> and the drift region <NUM>. Some examples for implementing the bias switch SWDEP are explained herein further below.

According to one example, a magnitude of the bias voltage VDEP is less than <NUM>%, less than <NUM>%, or even less than <NUM>% of a voltage blocking capability of the superjunction transistor device. The "voltage blocking capability" is the maximum voltage the superjunction transistor device can withstand in the blocking state before an Avalanche breakdown occurs. According to one example, the voltage blocking capability is between 400V and 1500V. The magnitude of the bias voltage is between <NUM> volts (V) and <NUM> volts, in particular between <NUM> volts and <NUM> volts, for example.

In an n-type transistor device, a polarity of the bias voltage VDEP may be such that (when the optional bias switch SWDEP is in an on-state) the electrical potential of the bias region <NUM> is positive relative to the electrical potential at the compensation region <NUM>.

Applying the bias voltage VDEP between the compensation region <NUM> and the bias region <NUM>, when the transistor device <NUM> is in the diode state, helps to reduce losses when the transistor device changes from the diode state to the blocking state. Losses that occur when the transistor device changes from the diode state to the blocking state include losses that are associated with removing the charge carrier plasma from the drift region <NUM> and the compensation region <NUM> and losses that are associated with storing charge carriers in the junction capacitance explained above (the losses associated with storing charge carriers in the junction capacitance are sometimes referred to as Qoss losses). Storing charge carriers in the junction capacitance is associated with a depletion region (space charge region) expanding in both the drift region <NUM> and the compensation region <NUM>. The charge carrier plasma includes first type charge carriers injected by the drain region <NUM> and second type charge carriers injected by the body region <NUM> and the compensation region <NUM>. In an n-type transistor device, for example, the first type charge carriers are electrons (n-type charge carriers) and the second type charge carriers are holes (p-type charge carriers).

Referring to the above, the depletion voltage VDEP is applied between the bias region <NUM> and at least one of the compensation region <NUM> and the body region <NUM> (the compensation region <NUM> and/or the body region <NUM>). Applying the depletion voltage VDEP between the bias region <NUM> and at least one of the compensation region <NUM> and the body region <NUM> such that at least one of the second pn-junction and the first pn-junction is reverse biased has the effect that first type charge carriers (those resulting from the charge carrier plasma in the drift region <NUM> and the compensation region <NUM> and/or the body region <NUM> and those associated with charging the junction capacitance) are collected by the bias region <NUM> and flow via the bias node Q towards a first node of the voltage source providing the bias voltage VDEP. Equivalently, second type charge carriers (those resulting from the charge carrier plasma in the drift region <NUM> and compensation region <NUM> and/or the body region <NUM> and those associated with charging the junction capacitance) flow via the compensation region <NUM> and/or the body region <NUM> to a second node opposite the first node of the voltage source. In an n-type transistor device, for example, the polarity of the bias voltage VDEP is such that the potential at the first node of the voltage source is higher than the potential at the second node in order to reverse bias the second pn-junction and/or the first pn-junction. In this case, electrons of the charge carrier plasma flow towards the first node of the voltage source and holes flow towards the second node of the voltage source.

Removing charge carriers of the charge carrier plasma from the drift region <NUM> and at least one of the compensation region <NUM> and the body region <NUM> and charging the junction capacitance (that is, forming a depletion region in the drift region <NUM> and the compensation region <NUM>) in the way explained above is associated with losses, wherein these losses are dependent on the current associated with removing the charge carriers of the plasma and forming the depletion region and are dependent on the depletion voltage VDEP. This current is referred to as current associated with a transition from the diode state to the blocking state. By suitably adjusting the voltage level of the depletion voltage VDEP however, these losses can significantly be reduced as compared to losses occurring in a conventional superjunction transistor device with the same voltage blocking capability and the same on-resistance (which is the resistance between the drain node and the source node in the forward conducting state).

The depletion voltage VDEP, at least, is applied between the compensation region <NUM> and the bias region <NUM> when the transistor device is in a transient phase between the reverse conducting state and the blocking state. The transient phase may include that the transistor device is operated in the diode state. It may be desirable to operate the transistor device in the diode state as short as possible and, nevertheless, avoid a cross current. A cross current may occur when the voltage across the transistor has reversed its polarity and the transistor device is still in the on-state.

According to one example, the bias voltage VDEP is applied in the transient phase until the drain-source voltage VDS in the blocking state has reached a predefined threshold. The transistor arrangement may further include a drive circuit (not illustrated) that is configured to drive the bias switch SWDEP such that the bias switch SWDEP is switched on until the drain-source voltage VDS in the blocking state has reached the predefined threshold. The bias voltage VDEP may be applied between the bias region <NUM> and the compensation region <NUM> throughout the time period in which the transistor device is in the diode state or only for a predefined time period, such as less than <NUM> nanoseconds (ns) before the transition from the diode state to the blocking state takes place and, as mentioned above, during the transition. According to one example, the predefined time period is dependent on a load current that flows through the superjunction transistor device when the transistor device is in the diode state, wherein a duration of the time period increases as the load current increases.

According to another example, the bias switch SWDEP is operated synchronously with the superjunction transistor device such that (a) the bias switch SWDEP switches off each time the superjunction transistor device switches on, that is, each time the superjunction transistor device is either in the forward conducting state or the reverse conducting state, and (b) the bias switch SWDEP switches on each time the superjunction transistor device switches off, that is, each time the superjunction transistor device is either in the diode state or the blocking state.

Referring to the above, <FIG> schematically illustrates device regions included in the superjunction transistor device, rather than a specific implementation. More detailed examples of how these device regions may be arranged in the semiconductor body <NUM> and of how the superjunction transistor device may be implemented are explained in the following.

One example of the transistor device is illustrated in <FIG>, wherein <FIG> shows a vertical cross sectional view of a semiconductor body <NUM> in which the transistor device is integrated and <FIG> shows a horizontal cross sectional view. The transistor device according to <FIG> includes a plurality of transistor cells <NUM>, wherein each transistor cell <NUM> includes device regions of the type explained with reference to <FIG>. That is, each transistor cell <NUM> includes: a drift region <NUM>; a source region <NUM>; a body region <NUM> separating the source region <NUM> from the drift region <NUM> and adjoining the drift region <NUM>; a drain region <NUM> spaced apart from the body region <NUM> in a current flow direction; an optional buffer region <NUM>; and a gate electrode <NUM> arranged adjacent to the body region <NUM> and dielectrically insulated from the body region <NUM> by a gate dielectric <NUM>. Further, in the example shown in <FIG> each transistor cell <NUM> further includes a bias region <NUM>. Everything explained above with regard to the doping type and the doping concentration of the device regions illustrated in <FIG> applies accordingly to the corresponding device regions in the transistor device shown in <FIG> and the other transistor devices explained herein further below.

The transistor device shown in <FIG> is a vertical transistor device. This, however, is only an example. A structure of the type illustrated in <FIG> that includes a plurality of transistor cells may be used in a lateral transistor device as well.

Referring to <FIG>, the drift region <NUM> of two neighboring transistor cells <NUM> can be formed by one respective semiconductor region, the compensation region <NUM> of two neighboring transistor cells <NUM> can be formed by one respective semiconductor region, and the body region <NUM> of two neighboring transistor cells <NUM> can be formed by one respective contiguous semiconductor region. Further, the bias region <NUM> of two neighboring transistor cells <NUM> can be formed by one respective semiconductor region. Further, the drain region <NUM> (as well as the optional buffer region <NUM>) of each of the transistor cells <NUM> can be formed by one contiguous semiconductor region.

In the example shown in <FIG>, the gate electrodes <NUM> and the gate dielectrics are located in trenches that extend from the first surface <NUM> into the semiconductor body <NUM>. The trenches with the gate electrodes <NUM> and the gate dielectrics <NUM> are referred to as gate trenches <NUM> in the following.

The transistor cells <NUM> are connected in parallel in that the gate electrodes <NUM> of the transistor cells <NUM> are connected to the gate node G, the source regions <NUM> and the body regions <NUM> of the transistor cells <NUM> are connected to the source node S, and the one or more drain regions <NUM> are connected to the drain node D. Further, each of the bias regions <NUM> is connected to the bias node Q. The gate node G, the source node S, the drain node D, and the bias node Q are only schematically illustrated in <FIG>. Further, connections between the gate node G and the gate electrodes <NUM> and between the source node S, the drain node D and the bias node Q and the respective active device regions (source regions <NUM>, body regions <NUM>, drain regions <NUM>, and bias regions <NUM>) are only schematically illustrated in <FIG>. These connections may include metallizations (not shown) on top of the first and second surfaces <NUM>, <NUM>.

Referring to the above, the body regions <NUM> of the transistor cells <NUM> are connected to the source node S. According to one example, the body region <NUM> includes a contact region <NUM> of the second doping type, wherein the contact region <NUM> is more highly doped than remaining sections of the body region <NUM>. In particular, the contact region <NUM> is more highly doped than those sections of the body region <NUM> adjoining the gate dielectric <NUM>. The contact region <NUM> may serve to provide an ohmic contact between the source node S and the respective body region <NUM>, more specifically, between the body region <NUM> and a source metallization (not illustrated).

In the transistor device shown in <FIG>, the compensation regions <NUM> of the transistor cells <NUM> are connected to the source node S. For this, the compensation region <NUM> of each transistor cell <NUM> adjoins the respective body region <NUM> in the vertical direction of the semiconductor body <NUM>. In lateral directions, the compensation regions <NUM> are spaced apart from the gate trenches <NUM>.

In the transistor device shown in <FIG>, the transistor cells are arranged such that the semiconductor region forming the bias region <NUM> of two neighboring transistor cells <NUM> is located between the gate trenches of these transistor cells. Further, in this example, each transistor cell <NUM> includes a bias region <NUM>. This, however, is only an example. According to another example (not shown), some of the bias regions <NUM> are omitted. In this case, neighboring transistor cells that each do not include a bias region may be implemented with a joint gate electrode.

Referring to <FIG>, the transistor cells <NUM> may be elongated in a lateral direction that is perpendicular to the section plane illustrated in <FIG> shows a horizontal cross sectional view of the semiconductor body <NUM> in a section plane A-A shown in <FIG>. In the following, a lateral direction x, which is a direction in which the body regions <NUM> adjoin the respective gate trenches <NUM> is referred to as first lateral direction x in the following. A lateral direction perpendicular to the first lateral direction x is referred to as second lateral direction y. Referring to <FIG>, the transistor cells <NUM> may be elongated in the second lateral direction y. "Elongated" means, for example, that a dimension of the drift regions <NUM> (or compensation regions <NUM>) in the second lateral direction y is at least one <NUM> (=1E2) times, or at least one <NUM> (=1E3) times, the dimension of the drift regions <NUM> (or the compensation regions <NUM>) in the first lateral direction x.

<FIG> illustrates a modification of the transistor device shown in <FIG>. In the transistor device shown in <FIG>, the body region <NUM> of each transistor cell <NUM> (wherein only one transistor cell is shown in <FIG>) is arranged between a respective gate trench <NUM> and a first isolation trench <NUM>. The compensation region <NUM> adjoins the body region <NUM>, is spaced apart from the gate trench <NUM> and may adjoin the isolation trench <NUM>. The bias region <NUM> of each transistor cell <NUM> is arranged between the gate trench <NUM> of the respective transistor cell <NUM> and the first isolation trench <NUM> of a neighbouring transistor cell (a section of the neighbouring transistor cell is illustrated in <FIG>).

Optionally, the transistor cell <NUM> further includes a field electrode <NUM>. The field electrode <NUM> is arranged in the gate trench <NUM> below the gate electrode <NUM> (as seen from the first surface <NUM>), is arranged adjacent to the drift region <NUM> and is dielectrically insulated from the drift region <NUM> by a field electrode dielectric <NUM>. The field electrode dielectric <NUM> electrically insulates the field electrode <NUM> from the drift region <NUM>. In a way not illustrated in detail in <FIG>, the field electrode <NUM> may be connected to the gate node G, the source node S or the bias node Q. The field electrodes <NUM> are useful to adjust a gate-drain capacitance of the transistor device, wherein the gate-drain capacitance is a capacitance between the gate node G and the drain node D of the transistor device. According to one example, the field electrode <NUM> is connected to the source node S to achieve a low gate-drain capacitance. According to another example, the field electrode <NUM> is connected to the gate node G to achieve a higher gate-drain capacitance.

The first isolation trench <NUM> is a trench extending from the first surface <NUM> into the semiconductor body <NUM> and electrically insulates the bias region <NUM> and the drift region <NUM> of one transistor cell from the body region <NUM> and the optional contact region <NUM> of a neighbouring transistor cell. The first isolation trench <NUM> may include any kind of electrically insulating material. Examples for implementing the first isolation trench <NUM> are explained in detail herein further below.

<FIG> illustrates a modification of the transistor device shown in <FIG>. The transistor device shown in <FIG> is different from the transistor device shown in <FIG> in that the compensation region <NUM> is spaced apart from the body region <NUM>. The compensation region <NUM> is either directly connected to the source node S or is connected to the source node S via a contact region <NUM> (as illustrated in <FIG>), wherein the contact region <NUM> adjoins the compensation region <NUM> and has a higher doping concentration than the compensation region <NUM>. A doping concentration of the contact region <NUM> is high enough to obtain an ohmic contact between the contact region <NUM> and the source node S.

In the example shown in <FIG>, at least one of the compensation region <NUM> and the contact region <NUM> may adjoin the gate trench <NUM> on one side, wherein the body region <NUM> and the source region <NUM> adjoin the gate trench <NUM> on another side opposite the at least one of the compensation region <NUM> and the contact region <NUM>. The field electrode <NUM> in the gate trench <NUM> below the gate electrode <NUM> is optional and may be omitted.

Further, in the transistor device shown in <FIG>, the bias region <NUM> is separated from the body region <NUM> (and the optional contact region <NUM>) by a second isolation trench <NUM>. The bias region <NUM> of one transistor cell is separated from the compensation region <NUM> and the optional contact region <NUM> of a neighbouring transistor cell by the first isolation trench <NUM>.

<FIG> illustrates a modification of the transistor device shown in <FIG>. The transistor device shown in <FIG> is different from the transistor device shown in <FIG> in that it includes a further gate trench <NUM> instead of the second isolation trench <NUM> between the body region <NUM> and the bias region <NUM>. Further, the transistor device shown in <FIG> includes a further source region <NUM> connected to the source node S and adjoining the further gate trench <NUM>.

The first and second isolation trenches <NUM>, <NUM> may be implemented in various ways. Two examples for implementing these isolation trenches <NUM>, <NUM> are illustrated in <FIG>. The first and second isolation trenches <NUM>, <NUM> of one transistor cell <NUM> may be implemented in the same way or in different ways. In context with <FIG>, "isolation trench" relates to any one of the first and second isolation trenches <NUM>, <NUM>.

According to one example illustrated in <FIG>, the isolation trench <NUM>, <NUM> may completely filled with an electrically insulating material <NUM>. Examples of the electrically insulating material include an oxide, a nitride, or combinations thereof. According to another example illustrated in <FIG>, a void <NUM> filled with air or a noble gas, for example, is arranged within the electrically insulating material <NUM>.

Optionally, in the example illustrated in <FIG> as well as in the example illustrated in <FIG>, the isolation trench <NUM>, <NUM> may include an electrode <NUM> in the region of a bottom of the isolation trench <NUM>, <NUM>. The electrode <NUM> is surrounded by the electrically insulating material <NUM> and may be connected to one of the gate node G, the source node S, or the bias node Q. An electric field along the first surface <NUM> in the bias region <NUM> and a current density in a region along the isolation trench <NUM> is dependent on to which of the circuit nodes (G, S, or Q) the field electrode <NUM> is connected to. According to one example, in the transistor device according to <FIG> and <FIG>, the isolation trench <NUM> includes a field electrode <NUM> connected to the bias node Q.

In each of the examples explained above, the bias region <NUM> may be implemented as a doped semiconductor region of the second doping type. In this case, a pn-junction is formed between the bias region <NUM> and the drift region <NUM> in the examples explained above. This pn-junction prevents a current flow from the drain region <NUM> to the bias node Q when the transistor device is in the blocking state and the drain source-voltage VDS increases. On the other hand, when the bias switch SWDEP is switched on, a bias region <NUM> of the second doping type injects second type charge carriers (which are holes in an n-type transistor device) into the drift region <NUM> that flow via the compensation region <NUM> and/or the body region <NUM> to the bias voltage source. This current flow is associated with additional losses.

Such losses can be reduced by suitably selecting the doping concentration of the bias region <NUM>. The bias region <NUM> can be considered as an emitter of a bipolar transistor formed by the bias region <NUM>, the drift region <NUM> and the compensation and body regions <NUM>, <NUM>. According to one example, a doping concentration of the bias region <NUM> is less than 5E18 cm-<NUM> to achieve a rather low efficiency of this emitter, that is, to suitably limit the amount of charge carriers injected into the drift region <NUM> by the emitter. According to one example, the doping concentration of the bias region <NUM> is between 1E16 cm-<NUM> and 2E18 cm-<NUM>.

Furthermore, such losses can be widely prevented when implementing the bias region <NUM> as a doped region of the first doping type. Thus, in each of the examples explained above, the bias region <NUM> may be also implemented as a doped semiconductor region of the first doping type. A current flow between the drain region <NUM> and the bias node Q can be prevented in this case by switching of the bias switch SWDEP in due time when the transistor device is in the blocking state and the drain source-voltage VDS increases or by any other means that interrupt a current flow from the drain region <NUM> to the bias region <NUM> when the transistor device <NUM> is in the blocking state. These other means may include means that interrupt a current path below the bias region <NUM> in the mesa region between the trenches <NUM> or <NUM>, <NUM>.

According to one example illustrated in <FIG>, the bias region <NUM> is a doped region <NUM> of the first doping type. In this example, a diode <NUM> may be connected between the bias region <NUM> and the bias voltage source. In <FIG>, only the circuit symbol of the diode <NUM> is illustrated. Examples for implementing this diode <NUM> are explained herein further below. The diode <NUM> helps to prevent a current flow between the drain node D (not illustrated in <FIG>) and the source node S via the drift region <NUM> and the bias region <NUM> when the transistor device is in the blocking state and the bias switch SWDEP is switched on.

<FIG> only illustrates the bias region <NUM> and two trenches between which the bias region <NUM> is located. These trenches may include two gate trenches <NUM> as illustrated in <FIG>, a gate trench <NUM> and a first isolation trench <NUM> as illustrated in <FIG> or a first isolation trench <NUM> and a second isolation trench <NUM> as illustrated in <FIG>. These trenches are only schematically illustrated in <FIG> and may be implemented in accordance with any of the examples explained above.

Optionally, as illustrated in dashed lines in <FIG> a doped region <NUM> of the second doping type is connected between the diode <NUM> and the drift region <NUM> and adjoins the bias region <NUM>. This region <NUM> of the second doping type may be useful, in addition to the body region <NUM>, to divert minority charge carriers from the drift region <NUM> when the transistor device changes from the diode state to the blocking state. The diode <NUM> may be any kind of external diode connected between the bias voltage source and the bias region <NUM>.

According to one example illustrated in <FIG>, the diode <NUM> is a Schottky diode and is formed by the bias region <NUM> and a Schottky metal layer <NUM> adjoining the bias region <NUM>. The Schottky metal layer <NUM> may include at least one of titanium (Ti), molybdenum (Mo), molybdenum silicide (MoSi), tantalum (Ta), titanium silicide (TiSi), or tantalum silicide (TaSi). The Schottky diode prevents a current flow from the drift region <NUM> to the bias node Q when the transistor device is in the blocking state and the drain-source voltage increases. This is similar to the example in which the bias region <NUM> is of the second doping type so that a pn-junction is formed between the bias region <NUM> and the drift region <NUM>. Unlike a bias region <NUM> of the second doping type, however, the Schottky diode formed by the bias region <NUM> of the first doping type and the Schottky metal does not inject second type charge carriers into the drift region <NUM>.

According to one example, the bias switch SWDEP is integrated in the semiconductor body <NUM>. Examples for integrating the bias switch SWDEP in the semiconductor body <NUM> are explained with reference to <FIG> in the following. In each of these examples, the bias switch SWDEP includes an auxiliary MOSFET integrated in the semiconductor body <NUM>.

In the example illustrated in <FIG>, the auxiliary MOSFET includes a gate electrode <NUM> arranged in a trench of the semiconductor body <NUM> and dielectrically insulated from semiconductor regions of the semiconductor body <NUM> by a gate dielectric <NUM>. The bias region <NUM> is a region <NUM> of the first doping type and forms a first source or drain region of the auxiliary MOSFET. The drift region <NUM> forms a second source or drain region of the auxiliary MOSFET. A body region <NUM> of the second doping type is arranged between the bias region <NUM> and the drift region <NUM>. Optionally, the source node S is connected to the body region <NUM>, wherein an optional contact region <NUM> may provide for an ohmic contact between the source node S and the body region <NUM>.

<FIG> shows a modification of the arrangement shown in <FIG>. In the example illustrated in <FIG>, the diode <NUM> is also integrated in the semiconductor body <NUM>. In this example, the diode <NUM> is formed by a pn-junction between the contact region <NUM> of the second doping type, which is also referred to as first diode region in the following, and a second diode region <NUM> of the first doping type. The bias voltage source is connected between the second diode region <NUM> and the bias region <NUM> in this example. In each of the examples illustrated in <FIG>, the auxiliary MOSFET of the bias switch SWDEP is a MOSFET of the first conductivity type.

<FIG> illustrates another example of the bias switch SWDEP. In this example, the auxiliary MOSFET of the bias switch SWDEP is a lateral MOSFET. The gate electrode <NUM> is arranged on top of the first surface <NUM> of the semiconductor body <NUM> and is dielectrically insulated from the semiconductor body <NUM> by the gate dielectric <NUM>. The MOSFET is of the second conductivity type in this example and includes a body region <NUM> of the first doping type and source and drain regions <NUM>, <NUM> of the second doping type. These source and drain regions <NUM>, <NUM> are spaced apart from each other in a lateral direction of the semiconductor body <NUM>. One of the source and drain regions <NUM>, <NUM> is connected to the bias voltage source. The other one of the source and drain regions <NUM>, <NUM> is connected to the bias region <NUM>, wherein the bias region <NUM> is separated from the semiconductor regions of the bias switch SWDEP by a third isolation trench <NUM>. This third isolation trench <NUM> may be implemented in accordance with one of the examples illustrated in <FIG>.

Referring to <FIG>, a junction region <NUM> of the second conductivity type forms a junction isolation between the body region <NUM> of the auxiliary MOSFET and the drift region <NUM>. This junction region <NUM> extends from the gate trench <NUM> or the second isolation trench <NUM> on one side to the third isolation trench <NUM> on the other side. The junction region <NUM> is connected to the source node, for example. A connection between the junction region <NUM> and the source node S is only schematically illustrated in <FIG>.

In the example illustrated in <FIG>, the source and drain regions <NUM>, <NUM> of the auxiliary MOSFET of the bias switch SWDEP are spaced apart from each other in the first lateral direction x and the bias region <NUM> is spaced apart from the semiconductor regions forming the bias switch SWDEP in the first lateral direction x. This, however, is only an example. <FIG> illustrate a modification of the transistor arrangement shown in <FIG>, wherein <FIG> shows a horizontal cross sectional view of a section of the semiconductor body <NUM> in which the bias switch SWDEP and the bias region <NUM> are integrated, <FIG> shows a vertical cross sectional view of a section in which the bias region <NUM> is integrated, and <FIG> shows a vertical cross sectional view of a section in which one of the source and drain regions <NUM>, <NUM> of the bias switch SWDEP is integrated.

In the example illustrated in <FIG>, the gate trench with the gate electrode <NUM> and the gate dielectric <NUM>, in the horizontal cross sectional view, has the shape of a comb with fingers that, in the first lateral direction x, each extend to the gate trench <NUM> or the second isolation trench <NUM> of the transistor cell <NUM>. Between two of these fingers of the gate structure <NUM>, <NUM> the bias region <NUM> is arranged, and between two of these fingers the source and drain regions <NUM>, <NUM>, the body region <NUM> and the junction region <NUM> of the bias switch SWDEP are arranged. The source and drain regions <NUM>, <NUM> adjoin the gate dielectric <NUM> and are arranged spaced apart from each other in the second lateral direction y, that is, the direction that is essentially parallel to the longitudinal direction of the gate trench <NUM> or the second isolation trench <NUM>. The bias region <NUM> is spaced apart from the semiconductor regions forming the bias switch SWDEP in the second lateral direction y.

<FIG> shows a modification of the arrangement shown in <FIG>. In the example shown in <FIG>, the diode <NUM> is integrated in the semiconductor body <NUM>. More specifically, drain or source region <NUM> of the bias switch SWDEP forms a first diode region and a second diode region <NUM> of the first doping type, which is a doping type complementary to the doping type of the source or drain region <NUM>, is embedded in the source or drain region <NUM>. The diode is formed by the pn-junction between the source or drain region <NUM> and the second diode region <NUM>. The second diode region <NUM> is connected to the bias region <NUM>.

<FIG> illustrate a modification of the arrangement shown in <FIG>. The arrangement shown in <FIG> is different from the arrangement shown in <FIG> in that the diode <NUM> is integrated in the semiconductor body <NUM>. For this, like in the example illustrated in <FIG>, the second diode region <NUM> is embedded in the source or drain region <NUM> and connected to the bias region <NUM>.

In the examples illustrated in <FIG>, <FIG>, <FIG> and <FIG>, connections between the source or drain region <NUM> or the second diode region <NUM> and the bias region <NUM> are only schematically illustrated. These connections may be implemented in a conventional way using metallizations formed on top of the first surface <NUM> of the semiconductor body <NUM>.

<FIG> illustrates one example of an electronic circuit in which a transistor arrangement <NUM> of the type explained above may be used as a rectifier element. In this example, the load path D-S of the superjunction transistor device included in the transistor arrangement <NUM> is connected in series with an electronic switch SW so that a half-bridge is formed by the superjunction transistor device and the electronic switch SW. The superjunction transistor device is referred to as TSJ in the following. Any type of electronic switch, e.g. another transistor arrangement of the same type as transistor arrangement <NUM>, can be used as the electronic switch SW. A series circuit including the electronic switch SW and the transistor arrangement <NUM> is connected between a first supply node and a second supply node, wherein a supply voltage VSUP is available between these supply nodes. Further, an inductive load Z (that is, a load that includes at least one inductor L) is connected in parallel with the drain-source path D-S of the transistor device of the transistor arrangement <NUM>. In this type of circuit arrangement, the electronic switch SW serves as an electronic switch that connects the load Z to the supply voltage VSUP dependent on a drive signal Ssw received by the electronic switch SW. The transistor arrangement <NUM> acts as a rectifier element (or freewheeling element) that takes over a current from the inductive load Z when the switch SW switches off.

The transistor arrangement <NUM> may be operated as a passive rectifier element, so that the superjunction transistor device TSJ only changes between the diode state and the blocking state. The superjunction transistor device TSJ changes to the diode state when the electronic switch SW switches off and the inductive load Z reverse biases the superjunction transistor device of the transistor arrangement <NUM>. When the electronic switch SW again switches on, the electronic switch SW takes over the load current IL and the superjunction transistor device TSJ changes to the blocking state. Operating the transistor arrangement <NUM> in this way is explained below with reference to <FIG>.

<FIG> shows signal diagrams that illustrate one example of operating the electronic circuit shown in <FIG>. More specifically, <FIG> shows signal waveforms of the drain-source voltage VDS, the gate-source voltage VGS, a control signal Ssw of the switch SW connected in series with the transistor arrangement <NUM>, and a control signal SDEP of the bias switch SWDEP connected in series with the bias voltage source. Each of the control signals Ssw, SDEP can have an on-level that switches on the respective switch SW, SWDEP, or an off-level that switches off the respective switch SW, SWDEP. Just for the purpose of illustration, the on-level is a logic high signal level and the off-level is a logic low signal level in this example.

In the example illustrated in <FIG>, the transistor arrangement <NUM> is operated such that the gate-source voltage VGS of the superjunction transistor device TSJ is always below the threshold voltage so that the superjunction transistor device TSJ either operates in the diode state (the third operating state) or the blocking state (the fourth operating state). Just for the purpose of explanation it is assumed that the gate-source voltage VGS is zero in this example. In this case, the operating state of the superjunction transistor device TSJ is only governed by the switch SW.

Referring to <FIG>, the switch SW connected in series with the transistor arrangement <NUM> is switched on before a first time instance <NUM>. Thus, a voltage across the load Z, which equals the drain-source voltage VDS of the transistor arrangement <NUM>, essentially equals the supply voltage VSUP and the superjunction transistor device TSJ of the transistor arrangement <NUM> is in the blocking state. When the switch SW is in the on-state, a load current IL flows through the inductive load Z as indicated in <FIG>.

When the switch SW switches off at the first time instance <NUM>, a commutation process starts, In this commutation process, the inductive load Z forces the load current IL to flow through the transistor arrangement <NUM>, that is, the inductive load Z reverse biases the superjunction transistor device TSJ and operates the superjunction transistor device TSJ in the diode state. Referring to <FIG>, the superjunction transistor device is not immediately reverse biased at the first time instance <NUM>, but there is a transient phase between the first time instance t1 and a time instance t11 after the first time instance. In the transient phase, the operating state of the superjunction transistor device changes from the blocking state (fourth operating state) to the diode state (third operating state). During this transient phase, the drain-source voltage VDS changes its polarity. Referring to <FIG>, when the electronic switch SW again switches on at a second time instance t2 (which is after the first time instance <NUM>), the superjunction transistor device TSJ becomes forward biased and enters the blocking state so that the drain-source voltage VDS again increases to a voltage level that essentially equals the supply voltage level VSUP. More specifically, there is a transient phase between the second time instance t2 and a time instance t21 after the second time instance t2. In this transient phase, the superjunction transistor device TSJ changes from the diode state (third operating state) to the blocking state (fourth operating state). During this transient phase, the drain-source voltage VDS again changes its polarity.

<FIG> illustrates a modification of the drive scheme illustrated in <FIG>. In the example illustrated in <FIG>, the superjunction transistor device TSJ is operated in the reverse conducting state (the second operating state) after switching off the switch SW at the first time instance t1 and before again switching on the switch SW at the second time instance t2. More specifically, there is a first dead time between the first time instance t1 and a time instance <NUM> when the superjunction transistor device is switched on in order to operate in the reverse conducting state, wherein this dead time may be longer than the transient phase between t1 and t1 <NUM> explained above. Further, there is a dead time between a time instance t22 at which the superjunction transistor device is switched off and the second time instance t2 at which the switch SW again switches on. During these dead times, the superjunction transistor device operates in the diode state including the above referenced transient phases. Referring to <FIG>, a magnitude of the drain-source voltage VDS may be lower in the reverse conducting state than in the diode state. Thus, operating the superjunction transistor device in the reverse conducting state may help to reduce conduction losses when the superjunction transistor device conducts the load current IL.

In each of the operating scenarios illustrated in <FIG> and <FIG> there are transient phases in which the superjunction transistor device TSJ of the transistor arrangement <NUM> changes from the diode state to the blocking state. By applying the bias voltage VDEP between the compensation regions <NUM> of the transistor cells <NUM> (not shown in <FIG>) and the bias regions <NUM> (also not shown in <FIG>) at least during the transient phase between the diode state and the blocking state losses associated with this transition can be reduced as explained in the following.

For explanation purposes it is assumed that the bias voltage source and the bias switch SWDEP are omitted or that the bias switch SWDEP is permanently open. In this case, the transistor arrangement <NUM> operates like a conventional transistor. Thus, when the transistor device changes from the diode state to the blocking state the current associated with this transition (that is, the current associated with removing the charge carrier plasma and forming the depletion region) is not absorbed by the depletion voltage source, but flows through a current path that includes the load paths of the transistor device and the electronic switch SW. The voltage across this current path equals the supply voltage VSUP. This supply voltage VSUP is selected dependent on the requirements of the load Z and may be several hundred volts such as between 400V and 1000V. According to one example, the supply voltage is between <NUM>% and <NUM>% of the voltage blocking capabilities of the devices SW, <NUM> in the half-bridge.

The bias voltage VDEP can be adjusted independent of the requirements of the load Z and, as explained above, can be as low as several volts. Thus removing the charge carrier plasma and forming the depletion region governed by the bias voltage VDEP results in much lower losses than removing the charge carrier plasma and forming the depletion region governed by the supply voltage VSUP. Thus, using a transistor arrangement <NUM> explained above instead of a conventional superjunction transistor may help to significantly reduce commutation losses.

Referring to the above, the bias voltage VDEP between the bias node Q and the drift region <NUM> removes charge carriers from the charge carrier plasma and causes the junction capacitances to be charged (that is, causes a depletion region to expand in the drift region <NUM> and the compensation region <NUM>). The junction capacitance may further be charged as the load path voltage VDS increases to voltage levels higher than the bias voltage VDEP. The current associated with this further charging of the junction capacitance does not flow with the bias node Q but flows via the drain and source nodes D, S of the superjunction transistor device so that the losses associated with this current are essentially given by the current level multiplied with the supply voltage VSUP, which may be significantly higher than the bias voltage VDEP. In a superjunction transistor device, however, a capacitance value of the junction capacitance is not linearly on the voltage and significantly decreases as the voltage increases. In an modern superjunction transistor device with a voltage blocking capability of 800V such as Infineon's IPD80R900P7, for example, the capacitance decreases by about two orders of magnitude as the voltage across the junction capacitance increases between about 20V and about 30V. Thus, using the bias voltage VDEP the junction capacitance can be pre-charged to a significant extent causing significant lower losses than charging the junction capacitance via the load path as usual.

Applying the bias voltage VDEP between the bias region <NUM> and the compensation region <NUM> when the superjunction transistor TSJ is not in a transient phase between the diode state and the blocking state may cause losses. Thus, according to one example the bias voltage VDEP is only applied for a rather short time that covers the transient phase. According to one example, applying the bias voltage VDEP starts when the switch SW switches off, or several nanoseconds before the switch SW switches off, and ends when the drain-source voltage VDS of the superjunction transistor TSJ has reached a predefined threshold.

In the examples explained before, the compensation region <NUM> is directly connected to the source node S. Thus, when the transistor device is in the reverse conducting state or the diode state and the bias voltage source is connected between the bias region <NUM> and the compensation region <NUM>, the current between the drain node D and the source node S partially flows via the bias voltage source. The bias voltage source, therefore, has to be adapted to carry the load current in this example.

<FIG> illustrates a modification of the transistor arrangement <NUM> shown in <FIG> in which a current flow via the bias voltage source is prevented when the transistor device is either in the diode state or the reverse conducting state.

The transistor arrangement shown in <FIG> is different from the transistor arrangement shown in <FIG> in that the bias voltage VDEP is provided by a capacitor CDEP connected between the bias region <NUM> and the compensation region <NUM>. This capacitor CDEP is also referred to as bias capacitor in the following. The bias switch SWDEP is represented by its circuit symbol in <FIG>. This bias switch SWDEP may be implemented as an external device or may be integrated in the semiconductor body <NUM> in accordance with any of the examples explained herein before.

Referring to <FIG>, the transistor arrangement <NUM> further includes a charging circuit CH for charging the capacitor CDEP. The charging circuit CH includes a charging voltage source configured to provide a charging voltage VCH and a switch SCH connected in series with the charging voltage source. A series circuit including the voltage source and the switch SCH is connected in parallel with the bias capacitor CDEP. A circuit node between the charging voltage source and the switch SCH is connected to the source node S, so that the switch SCH is connected between the source node S and a first node N1 of the bias capacitor CDEP and the voltage source is connected between the source node S and a second node N2 of the bias capacitor CDEP. In this way, the electrical potential at the second node N2 of the bias capacitor CDEP is kept at a predefined voltage level, wherein this voltage level is essentially given by the electrical potential at the source node S and the charging voltage VCH. The first node N1 of the bias capacitor CDEP which is connected to the compensation region <NUM> is also referred to as second bias node R in the following.

According to one example, the charging switch SWCH is operated in such a way that it is in the on-state to charge the bias capacitor CDEP when the superjunction transistor device is in the forward conducting state or the reverse conducting state and in the off-state when the superjunction transistor device is in the diode state or the blocking state. In this way, a connection between the compensation region <NUM> and the source node S is interrupted when the transistor device is in the diode state. The bias voltage VDEP is provide by the bias capacitor CDEP via the bias switch SWDEP. The bias switch SWDEP may be operated in the same way as explained above. That is, the bias switch SWDEP is switched on at least during a transient phase between the diode state and the blocking state and may be switched on throughout the diode state and the blocking state.

Optionally, a rectifier element DCH such as a diode is connected between the charging voltage source and the second node N2 of the bias capacitor CDEP. This rectifier element is connected such that it prevents a current flow from the bias region <NUM> via the bias switch SWDEP and the voltage source to the source node S.

Optionally, a further rectifier element SD is connected between the source node S and the bias region <NUM>. According to one example, this rectifier element SD is a Schottky diode. This rectifier element serves to limit a voltage between the source node S and the bias region <NUM> to a threshold level that is given by the forward voltage of the rectifier element SD. Alternatively (not illustrated) the optional further rectifier element is connected between the source node S and the circuit node between the bias capacitor CDEP and the bias switch SWDEP.

The circuit topology illustrated in <FIG> with the charging capacitor CDEP, the charging circuit CH and the optional rectifier element SD can be implemented in each of the transistor arrangements explained above. That is, the superjunction transistor device can be implemented in accordance with any of the superjunction transistor devices explained herein before.

<FIG>, for example, shows a transistor arrangement of the type shown in <FIG> that includes a transistor arrangement of the type shown in <FIG>. <FIG> shows a transistor arrangement of the type shown in <FIG> that includes a transistor device of the type shown in <FIG>.

According to one example, the charging switch SWCH is integrated in the semiconductor body <NUM>. One example of a transistor arrangement <NUM> in which the charging switch SCH is integrated in the semiconductor body <NUM> is illustrated in <FIG>. In this example, the charging switch SWCH includes a MOSFET with a gate electrode <NUM> and a gate dielectric <NUM> that are arranged in a trench between the body region <NUM> and the compensation region <NUM>. The trench with the gate electrode <NUM> and the gate dielectric <NUM> extends from the first surface <NUM> adjacent to the body region <NUM> and a section of the compensation region <NUM> into the drift region <NUM>. A first source or drain region <NUM> of the MOSFET is arranged in the body region <NUM>, connected to the source node S and adjoins the trench with the gate electrode <NUM> and the gate dielectric <NUM> on one side. A second source or drain region <NUM> is connected to the first node N1 of the bias capacitor CDEP, adjoins the trench with the gate electrode <NUM> and the gate dielectric <NUM> on a side opposite the side of the first source or drain region <NUM> and is arranged in the compensation region <NUM>. The MOSFET forming the charging switch SWCH switches on or of dependent on a drive signal SCH received at the gate electrode <NUM>. In the on-state of the MOSFET there is a conducting channel in the body region <NUM> between the first source or drain region <NUM> and the drift region <NUM> and another conducting channel in the compensation region <NUM> between the drift region <NUM> and the second source or drain region <NUM>, so that in the on-state of the MOSFET there is a conducting channel between the first and second source or drain regions <NUM>, <NUM>. Thus, the source node S is connected to the second bias node R.

According to one example (illustrated by a dashed line in <FIG>), the gate electrode <NUM> of the charging switch SWCH is connected to the gate node G. In this case, the charging switch SWCH is switched on whenever the transistor device is in an on-state, that is, whenever the transistor device is in the forward conducting state or the reverse conducting state. Thus, the bias capacitor CDEP is charged each time the transistor device is in the on-state. Further, in this case, each time the transistor device switches on, the charging switch SWCH connects the compensation region <NUM> to the source node S and, therefore, causes the compensation region <NUM> to be discharged when the transistor device changes from the blocking state into the forward conducting state, for example. Such discharging of the compensation region <NUM> is useful to achieve a low on-resistance in the forward conducting state of the transistor device.

<FIG> illustrates a modification of the transistor arrangement <NUM> shown in <FIG>. In the transistor arrangement <NUM> according to <FIG>, the charging voltage source is connected between the source node S and the second bias node R, which is connected to the compensation region <NUM>. The charging switch SCH is connected between the source node S and the second circuit node N2 of the bias capacitor CDEP. Further, the transistor arrangement <NUM> includes a discharging switch SWDIS connected between the compensation region <NUM> and the source node S The bias switch SWDEP is connected between the bias region <NUM> and the second circuit node N2 of the bias capacitor CDEP.

When the transistor device is in the blocking state the junction capacitance formed by the drift region <NUM> and the compensation region <NUM> is charged. Via the discharging switch SWDIS the junction capacitance, more specifically, the compensation region <NUM> can be discharged when the transistor device changes from the blocking state to the forward conducting state. Otherwise the on-resistance would be relatively high. According to one example, the discharging switch SWDIS is operated synchronously with the transistor device such that the discharging switch SWDIS switches on each time the transistor device switches on to operate in the forward conducting state or the reverse conducting state, and such that the discharging switch SWDIS switches off when the transistor device is in the diode state or the reverse conducting state. According to one example, the charging switch SWCH only switches on in order to charge the capacitor CDEP when the discharging switch SWDIS is switched off. The charging switch SWCH may be operated complementarily to the discharging switch SWDIS, so that the charging switch SWCH switches on when the discharging switch SWDIS switches off and switches off when the discharging switch SWDIS switches on.

<FIG> shows a vertical cross sectional view of an arrangement of the type shown in <FIG>, wherein the charging switch SWCH and the discharging switch SWDIS are integrated in the semiconductor body <NUM>. Each of these switches SWCH, SWDIS is implemented as a MOSFET and includes a respective gate electrode <NUM>, <NUM> connected to the gate node G of the superjunction transistor device so that operation of these switches SWCH, SWDIS is synchronized with operation of the superjunction transistor device. The discharging switch SWDIS may be implemented such that it switches on and off synchronized with the superjunction transistor device so that this switch SWDIS is in the on-state whenever the superjunction transistor device is in the forward conducting or the reverse conducting state. Referring to the above, the charging switch SWCH may be operated such that it only switches on in order to charge the capacitor CDEP when the discharging switch SWDIS is switched off. Thus, in the example illustrated in <FIG>, the gate electrode <NUM> of the charging switch SWCH is connected to a control node G2 that is different from the gate node G, wherein the gate electrode of the discharging switch SWDIS is connected to the gate node G.

According to another example (not illustrated) the gate electrode <NUM> of the discharging switch SWDIS is connected to a control node that is different from the gate node G. The gate electrode <NUM> of the discharging switch SWDIS may be implemented in this way in addition to connecting the gate electrode <NUM> of the charging switch SWCH to the gate node G2 so that the gate electrodes <NUM>, <NUM> of the charging switch SWCH and the discharging switch SWDIS are connected to different control nodes. Alternatively, the gate electrode of the charging switch SWCH is connected to the gate node G and the gate electrode <NUM> of the discharging switch SWDIS is connected to a control node different from the gate node G.

In the arrangement shown in <FIG>, the charging switch SWCH is implemented as explained with reference to <FIG>, wherein the gate electrode <NUM> of the charging switch SWCH and one gate electrode <NUM> of the of the superjunction transistor device are formed by the same gate electrode. Furthermore, the gate electrode of the charging switch SWCH is arranged between the bias region <NUM> and the body region <NUM>.

The gate electrode <NUM> of the discharging switch SWDIS and one gate electrode <NUM> of the of the superjunction transistor device connected to different gate electrodes G G2. Furthermore, the gate electrode of the discharging switch SWDIS is arranged between the body region <NUM> and the compensation region <NUM>. The discharging switch SWDIS is a MOSFET of the first conductivity type, and includes a source region <NUM> of the first doping type, wherein the source region <NUM> is embedded in the compensation region <NUM> and adjoins the trench with the gate electrode <NUM>. A body region of the discharging switch SWDIS is formed by a section of the compensation region <NUM> that adjoins the gate trench, and a drain region of the discharging switch SWDIS is formed by the drift region of the superjunction transistor device.

The discharging switch SWDIS further includes a charge carrier converter that is configured to "convert" a second type charge carrier current provided by the compensation region <NUM> into a first type charge carrier current that can be conducted by the discharging switch SWDIS to the drift region <NUM> in order to discharge the compensation region <NUM>. The charge carrier converter includes the source region <NUM>, a metal <NUM> adjoining the source region <NUM>, and a region <NUM> of the second doping type. The region of the second doping type adjoins the metal and may adjoin the source region <NUM>. The region of the second doping type <NUM> is embedded in the compensation region <NUM> and has a doping concentration that is higher than the doping concentration of the compensation region <NUM>.

Optionally, an isolation trench <NUM> is arranged between the charge carrier converter <NUM>, <NUM>, <NUM> and the contact region <NUM> of the compensation region. This isolation trench <NUM> may be implemented in accordance with any of the examples explained with regard to isolation trenches <NUM>, <NUM> herein above.

Claim 1:
A method, comprising:
applying a bias voltage (VDEP) different from zero between a drift region (<NUM>) and at least one of a compensation region (<NUM>) and a body region (<NUM>) of at least one transistor cell (<NUM>) of a transistor device when the transistor device is in a diode state,
wherein the compensation region (<NUM>) has a doping type complementary to a doping type of the drift region (<NUM>),
wherein the compensation region (<NUM>) adjoins the drift region (<NUM>),
wherein a polarity of the bias voltage (VDEP) is such that a pn-junction between the drift region (<NUM>) and the at least one of the compensation region (<NUM>) and the body region (<NUM>) is reverse biased,
wherein applying the bias voltage (VDEP) comprises applying the bias voltage (VDEP) between a bias region (<NUM>) that is coupled to the drift region (<NUM>) and the at least one of the compensation region (<NUM>) and the body region (<NUM>),
wherein the bias region (<NUM>) is spaced apart from the body region (<NUM>) and a source region (<NUM>) of the at least one transistor cell,
wherein the bias region (<NUM>) is arranged between two trenches (<NUM>; <NUM>, <NUM>) in a semiconductor body (<NUM>) of the transistor device, and
wherein, in the diode state, a pn-junction between the body region (<NUM>) and the drift region (<NUM>) is forward biased and a charge carrier plasma including charge carriers of a first conductivity type and a second conductivity type is formed in the drift region.