Patent Description:
Semiconductor devices capable of storing high-capacity data may be used in data storage systems. Accordingly, research into a method for increasing the data storage capacity of a semiconductor device is being carried out. For example, as a method for increasing the data storage capacity of a semiconductor device, a semiconductor device including three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed.

Example embodiments provide a semiconductor device having improved integration and mass-productivity.

Example embodiments provide a data storage system including a semiconductor device with improved integration and mass-productivity.

According to one aspect of the present invention, there is provided a semiconductor device in accordance with claim <NUM>. Further aspects and preferred embodiments are set out in claim <NUM> -<NUM>.

The above and other aspects, features, and advantages of the present disclosure will be more apparent from the following description of example embodiments, taken in conjunction with the accompanying drawings, in which:.

Hereinafter, example embodiments will be described with reference to the accompanying drawings. The same reference numerals may refer to the same elements throughout. It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. By contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present.

<FIG> is a schematic plan view of a semiconductor device.

<FIG> is a schematic cross-sectional view of a semiconductor device. <FIG> illustrates cross-sections taken along lines I-I' and II-II' of <FIG>.

Referring to <FIG> and <FIG>, a semiconductor device <NUM> may include a first structure <NUM> including a substrate <NUM>, and a second structure <NUM> including a source structure <NUM>. The second structure <NUM> may be disposed on the first structure <NUM>.

The first structure <NUM> may include the substrate <NUM>, device isolation layers <NUM> defining an active region 15a within the substrate <NUM>, circuit elements <NUM> disposed on the substrate <NUM>, lower interconnections <NUM> electrically connected to the circuit elements <NUM>, and a lower capping insulating layer <NUM> covering the circuit elements <NUM> and the lower interconnections <NUM>.

The second structure <NUM> may include a source structure <NUM> having a first region CR and a second region ER, a stack structure ST including interlayer insulating layers <NUM> and gate electrodes <NUM>, a separation pattern SP passing through the stack structure ST and extending in the X direction, first vertical structures VS1 passing through the stack structure ST, on the first region CR, second vertical structures VS2 passing through the stack structure ST, on the second region ER, an upper capping insulating layer <NUM> on the stack structure ST, and upper interconnections <NUM> on the first vertical structures VS <NUM>. By arranging the second vertical structures VS2 on the second region ER in the same or similar shape as the first vertical structures VS1 on the first region CR, the manufacturing process of semiconductor devices may be simplified, and process dispersion may be improved.

The substrate <NUM> may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate <NUM> may be provided as a bulk wafer or as an epitaxial layer. The device isolation layers <NUM> may be disposed in the substrate <NUM>, and source/drain regions <NUM> including impurities may be disposed in a portion of the active region 15a.

The circuit elements <NUM> may each include a transistor including a source/drain region <NUM> and a circuit gate <NUM>. The source/drain regions <NUM> may be disposed on both sides of the circuit gate <NUM> in the active region 15a. The circuit gate <NUM> may include a dielectric layer on active region 15a and a circuit gate electrode on the dielectric layer.

The lower interconnections <NUM> may be electrically connected to the circuit elements <NUM>. The lower interconnections <NUM> may be disposed at different levels and may include a plurality of interconnection layers connected to each other by vias. The lower interconnections <NUM> may include a conductive material, for example, a metallic material such as tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), or the like.

The lower capping insulating layer <NUM> may cover the substrate <NUM>, the circuit elements <NUM>, and the lower interconnections <NUM>. The lower capping insulating layer <NUM> may be formed of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonate, or the like. The lower capping insulating layer <NUM> may include a plurality of insulating layers.

The source structure <NUM> may be disposed on the first structure <NUM>. At least a portion of the source structure <NUM> may be formed of, for example, polycrystalline silicon having an N-type conductivity. In the source structure <NUM>, a region formed of polycrystalline silicon having an N-type conductivity may be a common source region. The source structure <NUM> may include at least one of doped polycrystalline silicon, a metal, a metal nitride, and a metal-semiconductor compound.

The source structure <NUM> may include a base pattern <NUM>, a first pattern <NUM>, a second pattern <NUM>, and source sacrificial layers <NUM>, <NUM>, and <NUM>. The first pattern <NUM> may be disposed on the base pattern <NUM>, and the second pattern <NUM> may be disposed on the first pattern <NUM>. At least one of the base pattern <NUM>, the first pattern <NUM>, and the second pattern <NUM> may include silicon. The first pattern <NUM> penetrates the gate dielectric layer <NUM> in the first region CR, and may be directly connected to the channel layer <NUM> on the periphery of the channel layer <NUM>. The source sacrificial layers <NUM>, <NUM>, and <NUM> may be disposed in the second region ER and may be disposed at the same level as the first pattern <NUM>. The source sacrificial layers <NUM>, <NUM>, and <NUM> may include an insulating material such as silicon oxide or silicon nitride.

The gate electrodes <NUM> and the channel structures CH may be disposed on the first region CR of the source structure <NUM> to provide memory cells. The gate electrodes <NUM> provide pad regions 130P having a stepped structure, may be disposed on the second region ER of the source structure <NUM>, such that gate contact plugs ('CMC' in <FIG>) and/or through-contact plugs ('THV' in <FIG>) may be provided. The first region CR may be referred to as a 'memory cell array region,' and the second region ER may be referred to as a 'step region' or a `connection area.

The gate electrodes <NUM> may be stacked and spaced apart from each other in the Z direction on the source structure <NUM> to form the stack structure ST. The gate electrodes <NUM> may extend in the X direction. The gate electrodes <NUM> may include lower gate electrodes forming the gates of the ground select transistors, memory gate electrodes forming the plurality of memory cells, and upper gate electrodes forming the gates of the string select transistors. The number of the memory gate electrodes constituting the memory cells may be determined according to the capacity of the semiconductor device <NUM>. The gate electrodes <NUM> may further include a gate electrode disposed above the upper gate electrodes and/or below the lower gate electrodes to form an erase transistor used for an erase operation using a gate induced drain leakage (GIDL) phenomenon.

The gate electrodes <NUM> may extend along the X direction from the first region CR to the second region ER to form a stepped structure in the form of a step. Due to the step structure, the lower gate electrode <NUM> may extend further than the upper gate electrode <NUM> of the gate electrodes <NUM>, and may have pad regions 130P exposed upwards. The pad regions 130P may be regions including ends of the gate electrodes <NUM> along the X direction. The gate electrodes <NUM> may be electrically connected to the gate contact plugs CMC in the pad regions 130P, respectively (refer to <FIG>).

The gate electrodes <NUM> may be disposed to be separated from each other in the Y direction by the separation patterns SP extending in the X direction. The gate electrodes <NUM> between the pair of separation patterns SP may form one memory block, but the scope of the memory block is not limited thereto. Some of the upper gate electrodes <NUM> among the gate electrodes <NUM> may be separated from each other in the Y direction by a string separation pattern, and may provide gates of the string select transistors. In another example, the gates of the string select transistors may be provided as string select gate electrodes extending in the X direction on the stack structure ST. In this case, string select channel structures passing through the string select gate electrodes and connected to upper ends of the channel structures CH may be further disposed on the stack structure ST.

Each of the gate electrodes <NUM> may include a first layer and a second layer, the first layer may cover the upper and lower surfaces of the second layer, and may extend between the channel structures CH and the second layer. The first layer may include a high dielectric material such as aluminum oxide (AlO), and the second layer may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN). The gate electrodes <NUM> may include polycrystalline silicon or a metal-semiconductor compound.

The interlayer insulating layers <NUM> may be disposed between the gate electrodes <NUM>, and may form a stack structure ST. Like the gate electrodes <NUM>, the interlayer insulating layers <NUM> may be spaced apart from each other in the Z direction and may be disposed to extend in the X direction. The interlayer insulating layers <NUM> may include an insulating material such as silicon oxide or silicon nitride. In the stack structure ST the interlayer insulating layer <NUM> and the gate electrodes <NUM> may be alternately and repeatedly provided.

The stack structure ST may include a lower stack structure and an upper stack structure on the lower stack structure. The gate electrodes <NUM> of the lower stack structure may form a first gate stacked group, and the gate electrodes <NUM> of the upper stack structure may form a second gate stacked group. Between the lower stack structure and the upper stack structure, the first vertical structures VS1 and the second vertical structures VS2 may have a shape in which side surfaces are bent.

The separation patterns SP may be disposed to extend in the X direction from the first region CR to the second region ER. The separation patterns SP may penetrate through the entire gate electrodes <NUM> of the stack structure ST and contact the source structure <NUM>. The separation patterns SP may be formed by expanding and merging a plurality of hole patterns, and in a plan view, the side surfaces thereof may have an uneven shape, for example a wavy (undulating) shape or an embossed shape. The separation patterns SP may have a shape in which first portions having a first width W1 in the Y direction and second portions having a second width W2 smaller than the first width W1 in the Y direction are alternately and repeatedly arranged along the X direction.

The separation patterns SP may be spaced apart from a portion of the first vertical structures VS1 and a portion of the second vertical structures VS2 closest to the separation patterns SP, but a portion of the first vertical structures VS1 closest to the separation patterns SP and a portion of the second vertical structures VS2 may be in contact with the separation patterns SP. The separation patterns SP may have curved sides in cross-section, but the structure seen in the cross-section of the separation patterns SP may be variously changed. The separation patterns SP may be formed of an insulating material, for example, silicon oxide.

As illustrated in <FIG>, the first vertical structures VS1(CH) may respectively form one memory cell string, and may be disposed to be spaced apart from each other while forming rows and columns on the first region CR. The first vertical structures VS1(CH) may be disposed between the separation patterns SP. The first vertical structures VS1(CH) may have a lattice arrangement (e.g., a triangular lattice, a hexagonal lattice, or a rhombus lattice). The first vertical structures VS1(CH) may have a columnar shape, and may have inclined sides that become narrower as they get closer to the source structure <NUM> according to an aspect ratio. The first vertical structures VS1(CH) may include channel structures CH.

As illustrated in the enlarged view of <FIG>, the channel structures CH may include a channel layer <NUM>, a gate dielectric layer <NUM>, a core insulating layer <NUM>, and a channel pad <NUM>. The channel layer <NUM> may be disposed in an annular shape surrounding the core insulating layer <NUM>, and the gate dielectric layer <NUM> may be disposed in an annular shape surrounding the channel layer <NUM>. The gate dielectric layer <NUM> may extend to a lower end of the channel structure CH. The channel layer <NUM> may be disposed on the gate dielectric layer <NUM>. A lower portion of the channel layer <NUM> may be connected to the first pattern <NUM>. The channel layer <NUM> may include a semiconductor material such as polycrystalline silicon or single crystal silicon, and may include a region doped with an impurity. The core insulating layer <NUM> may include silicon oxide or silicon oxide having voids formed therein. The channel pad <NUM> may be disposed on the core insulating layer <NUM> and may be connected to an upper portion of the channel layer <NUM>. The channel pad <NUM> may include, for example, doped polycrystalline silicon.

The gate dielectric layer <NUM> may be disposed between the gate electrodes <NUM> and the channel layer <NUM>. The gate dielectric layer <NUM> may contact the gate electrodes <NUM>. The gate dielectric layer <NUM> may include a tunneling layer <NUM>, an information storage layer <NUM>, and a blocking layer <NUM> sequentially stacked from the channel layer <NUM>. The tunneling layer <NUM> may tunnel charges to the information storage layer <NUM>, and may include, for example, silicon oxide or silicon oxide doped with impurities. The information storage layer <NUM> may include a material capable of storing information by trapping electric charges, for example, silicon nitride. The information storage layer <NUM> may include regions capable of storing information in a semiconductor device such as a flash memory device. The blocking layer <NUM> may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or combinations thereof.

As illustrated in <FIG>, the second vertical structures VS2 may be disposed to be spaced apart from each other while forming rows and columns on the second region ER. The second vertical structures VS2 may be disposed between the separation patterns SP and may penetrate through the pad regions 130P of the gate electrodes <NUM>. The second vertical structures VS2 may have the same lattice form (e.g., triangular lattice, hexagonal lattice, or rhombic lattice) as that of the first vertical structures VS1(CH) (for example, the first and second vertical structures may have a common lattice arrangement). The second vertical structures VS2 may have a continuous arrangement on the second region ER. By making the design of the patterns disposed on the second region ER the same as or a similar to the design of the patterns disposed on the first region CR, continuous and uniform patterning is possible, such that a margin of a photolithography process and an etching process may be significantly increased, and process dispersion of semiconductor device manufacturing may be improved. In addition, because patterning may be performed with a certain design, it is possible to reduce the difficulty of a high aspect ratio etching process during a semiconductor device manufacturing process.

The first vertical structures VS1(CH) may be arranged at a first pitch PA in the X-direction and may have a first diameter WA, and the second vertical structures VS2(SS) may be arranged at a second pitch PB in the X-direction and may have a second diameter WB. The second pitch PB may be about <NUM> to about <NUM> times the first pitch PA. For example, the second pitch PB may be substantially the same as the first pitch PA. The second diameter WB may be about <NUM> times to about <NUM> times the first diameter WA. For example, the second diameter WB may be substantially the same as the first diameter WA. In the present specification, "pitch" may mean the minimum length from the center to the center for one configuration, and "diameter", which is relatively described in comparison, means a diameter at the same height, or the maximum diameter.

The second vertical structures VS2 may include support structures SS and contact structures CS1 and CS2. The contact structures CS1 and CS2 will be further described with reference to <FIG>, <FIG>, <FIG> and <FIG>, and the support structures SS will be further described below. As illustrated in region 'A' of <FIG>, the first contact structures CS1 may be arranged at a pitch PBa substantially equal to a second pitch PB of the support structures SS in the X direction, and may have a diameter WBa substantially equal to a second diameter WB of the support structures SS. As illustrated in region 'B' of <FIG>, the second contact structures CS2 may be arranged at a pitch PBb substantially equal to the second pitch PB of the support structures SS in the X direction, and may have a diameter WBb substantially equal to the second diameter WB of the support structures SS.

The support structures SS may be formed in the same process step as the channel structures CH and may have the same or similar internal structure as the channel structures CH. For example, each of the support structures SS may include a support channel layer 140d, a support dielectric layer 145d, a support core insulating layer 147d, and a support channel pad 149d. The support channel layer 140d may be spaced apart from the source structure <NUM>. The support dielectric layer 145d may extend to a lower end of the support structure SS. As illustrated in the enlarged view of <FIG>, the support dielectric layer 145d may include a support tunneling layer 143d, a support information storage layer 142d, and a support blocking layer 141d sequentially stacked from the support channel layer 140d.

The support structures SS may be dummy structures that do not perform a substantial function during the operation of the semiconductor device <NUM>, and may serve to improve structural stability of the stack structure ST. In other examples, the support structures SS may have a structure in which the inside is filled with silicon oxide, unlike the channel structures CH. The number of gate electrodes <NUM> through which any one of the support structures SS passes may be less than the number of gate electrodes <NUM> through which any one of the channel structures CH passes.

The upper capping insulating layer <NUM> may cover the stack structure ST, the separation patterns SP, and the first and second vertical structures VS1 and VS2. The upper capping insulating layer <NUM> may include an insulating material such as silicon oxide, silicon nitride, or silicon oxycarbide. The upper capping insulating layer <NUM> may include a plurality of insulating layers.

The upper interconnections <NUM> may include bit lines BL disposed on the stack structure ST. The bit lines BL may be electrically connected to the channel pads <NUM> of the channel structures CH through connection plugs <NUM>, respectively. The upper interconnections <NUM> may further include interconnections electrically connected to the gate contact plug CMC or the through contact plug THV. The upper interconnections <NUM> may include a metal material, for example, at least one of tungsten (W), titanium (Ti), copper (Cu), and aluminum (Al).

<FIG> is a schematic cross-sectional view of a semiconductor device. <FIG> illustrates cross-sections along the cut lines Ia-Ia' and IIa-IIa' of <FIG>.

<FIG> is a schematic cut-away perspective view of an auxiliary pattern of a semiconductor device. In <FIG>, only the area below the auxiliary channel pad 149a in the auxiliary pattern AP is illustrated.

Referring to <FIG> and <FIG>, the first structures VS1 of the semiconductor device 100a may include channel structures CH and first auxiliary patterns AP1, and the second structures VS2 may include support structures SS and second auxiliary patterns AP2. The first auxiliary patterns AP1 may be disposed between the separation patterns SP and the channel structures CH, on the first region CR, and may be arranged in a line on at least one side of the separation patterns SP. The second auxiliary patterns AP2 may be disposed between the separation patterns SP and the support structures SS on the second region ER, and may be arranged in a line on at least one side of the separation patterns SP.

The channel structure CH may have a first diameter WA, and the first auxiliary pattern AP1 may have a first diameter WC1 smaller than the first diameter WA. The support structure SS may have a second diameter WB, and the second auxiliary pattern AP2 may have a second diameter WC2 smaller than the second diameter WB. The first pitch PC1 of the first auxiliary patterns AP1 may be substantially the same as the first pitch PA of the channel structures CH, and the second pitch PC2 of the second auxiliary patterns AP2 may be substantially the same as the second pitch PB of the support structures SS. The first diameter WC1 of the first auxiliary pattern AP1 may be substantially the same as or different from the second diameter WC2 of the second auxiliary pattern AP2. The first pitch PC <NUM> of the first auxiliary patterns AP1 may be substantially the same as or different from the second pitch PC2 of the second auxiliary patterns AP2.

Lower ends of the first auxiliary patterns AP1 may be located at a higher level than lower ends of the channel structures CH, and lower ends of the second auxiliary patterns AP2 may be located at a higher level than lower ends of the support structures SS. Lower ends of the auxiliary patterns AP including the first and second auxiliary patterns AP1 and AP2 may be disposed inside the stack structure ST. The auxiliary patterns AP may partially penetrate through the gate electrodes <NUM> from the top and may not penetrate some of the lower gate electrodes <NUM>. The Z-direction heights of the first auxiliary patterns AP1 may be smaller than the Z-direction heights of the channel structures CH, and the Z-direction heights of the second auxiliary patterns AP2 may be smaller than the Z-direction heights of the support structures SS. The auxiliary patterns AP may be positioned to be spaced apart from the source structure <NUM> in the Z direction.

As illustrated in <FIG>, each of the auxiliary patterns AP may include an auxiliary dielectric layer 145a, an auxiliary channel layer 140a, and an auxiliary core insulating layer 147a. Because the auxiliary pattern AP has a diameter and a height less than those of the channel structure CH and the support structure SS, at least a portion of the auxiliary dielectric layer 145a, the auxiliary channel layer 140a, and the auxiliary core insulating layer 147a may not extend from the upper end to the lower end of the auxiliary pattern AP. For example, the auxiliary dielectric layer 145a may extend to the lower end of the auxiliary pattern AP, but the auxiliary channel layer 140a may extend to a shorter length than the auxiliary dielectric layer 145a.

In the first region R1 adjacent to the auxiliary channel pad 149a, the auxiliary dielectric layer 145a, the auxiliary channel layer 140a, and the auxiliary core insulating layer 147a may be sequentially disposed in the hole of the auxiliary pattern AP from the outside.

The auxiliary dielectric layer 145a and the auxiliary channel layer 140a may be sequentially disposed in the hole of the auxiliary pattern AP, in the second region R2 below the first region R1, from the outside. The auxiliary core insulating layer 147a may not extend in the second region R2.

In the third region R3 below the second region R2, the first to third auxiliary dielectric layers 141a, 142a, and 143a constituting the auxiliary dielectric layer 145a may be disposed sequentially in the hole of the auxiliary pattern AP from the outside. The auxiliary channel layer 140a and the auxiliary core insulating layer 147a may not extend in the third region R3. For example, the distance between the lower end of the auxiliary channel layer 140a and the lower end of the auxiliary pattern AP may be greater than the distance between the lower end of the channel layer <NUM> and the lower end of the channel structure CH, and may be greater than the distance between the lower end of the support channel layer 140d and the lower end of the support structure SS.

In the fourth region R4 below the third region R3, the first and second auxiliary dielectric layers 141a and 142a forming the auxiliary dielectric layer 145a may be sequentially disposed from the outside in the hole of the auxiliary pattern AP. The third auxiliary dielectric layer 143a, the auxiliary channel layer 140a, and the auxiliary core insulating layer 147a may not extend in the fourth region R4.

In the fifth region R5 including the lower end of the auxiliary pattern AP, the channel hole of the auxiliary pattern AP may be filled with the first dielectric layer 141a constituting the auxiliary dielectric layer 145a. The second and third auxiliary dielectric layers 142a and 143a, the auxiliary channel layer 140a, and the auxiliary core insulating layer 147a may not extend in the fifth region R5.

However, in another example, the auxiliary pattern AP may include only a partial region of the second to fifth regions R2, R3, R4, and R5. For example, the auxiliary pattern AP may include only the first region R1 and the fifth region R5. The internal structure of the auxiliary pattern AP may be variously changed according to the diameter, height, side inclination of the auxiliary pattern AP, the thickness of each layer constituting the auxiliary pattern AP, or the like.

In another example, when the stack structure ST is includes a lower stack structure and an upper stack structure on the lower stack structure, the auxiliary pattern may include a lower auxiliary pattern partially penetrating through the lower stack structure from an upper portion, and an upper auxiliary pattern penetrating through the upper stack structure and connected to the lower auxiliary pattern. The lower auxiliary pattern may have a width smaller than a width of other vertical structures passing through the lower stack structure, and a lower end of the lower auxiliary pattern may be located at a higher level than lower ends of other vertical structures passing through the lower stack structure.

<FIG> is a schematic cross-sectional view of a semiconductor device. <FIG> illustrates cross-sections taken along lines Ib-Ib' and IIb-IIb' of <FIG>.

Referring to <FIG> and <FIG>, separation patterns SP' of a semiconductor device 100b may be formed by merging holes of the auxiliary patterns AP and adjacent separation patterns SP as illustrated in <FIG>. For example, the holes of the auxiliary patterns AP and the separation patterns SP may be expanded and merged with each other. In this case, the side surfaces of the separation patterns SP' may have a double embossed shape in a plane. Two or more types of embossing patterns may be present on the side surfaces of the separation patterns SP', and for example, the side surfaces of the separation patterns SP' may have a first embossing pattern E1 having a first curvature and a second embossing pattern E2 having a second curvature greater than the first curvature.

At a level lower than the lower ends of the auxiliary patterns AP, the lower regions of the separation patterns SP' do not merge with the holes of the auxiliary patterns AP, and thus, the side surfaces thereof may have a single embossed shape in a plane. For example, an upper region of the side surfaces of the separation patterns SP' may have a double embossed shape in a plane, and a lower region of a side surface of the separation patterns SP' may have a single embossed shape in a plane view.

<FIG> is a schematic cross-sectional view of a semiconductor device. <FIG> illustrates cross-sections taken along lines Ic-Ic' and IIc-IIc' of <FIG>.

Referring to <FIG> and <FIG>, in a semiconductor device 100c, patterning may not be performed in the region corresponding to the auxiliary patterns AP illustrated in <FIG> and <FIG>. Accordingly, the semiconductor device 100c may not include the auxiliary patterns AP. For example, compared to the semiconductor device <NUM> of <FIG> and <FIG>, the semiconductor device 100c may have a structure in which a portion of the first vertical structures VS1 disposed in a column closest to the separation patterns SP among the first vertical structures VS1 arranged in the X direction is omitted and a portion of the second vertical structures VS2 disposed in a column closest to the separation patterns SP among the second vertical structures VS2 arranged in the X direction is omitted. <FIG> and <FIG> may correspond to the case in which the mask on the regions corresponding to the auxiliary patterns AP is not completely opened (see <FIG> and <FIG>), and thus, no patterning trace remains in the stack structure ST.

Referring to <FIG>, the separation patterns SP of a semiconductor device 100d may include first separation patterns SP <NUM> continuously extending in the X direction and second separation patterns SP2 intermittently extending in the X direction. The second separation patterns SP2 may intermittently extend on the second region ER, and at least one support structure SS may be disposed between the second separation patterns SP2 (e.g., along the X direction). At least one auxiliary pattern AP may be disposed between the second separation patterns SP2 (e.g., along the X direction).

<FIG> is a schematic partially enlarged plan view of a semiconductor device. <FIG> illustrates an enlarged view of area 'A' of <FIG>.

<FIG> is a schematic cross-sectional view of a semiconductor device. <FIG> illustrates a cross-section taken along line III-III' in <FIG>.

Referring to <FIG> and <FIG>, the second vertical structures VS2 may include first contact structures CS1 between the support structures SS. The first contact structures CS1 may form a group and may be connected together with one of the gate electrodes <NUM> to provide one gate contact plug CMC. For example, one gate contact plug CMC may include a cluster of first contact structures CS1 electrically connected to each other. The first contact structures CS1 may be arranged in a hexagonal shape. The first contact structures CS1 may have a continuous arrangement with the support structures SS. As illustrated in <FIG>, the first contact structures CS1 may be arranged at a pitch PBa substantially equal to a second pitch PB of the support structures SS in the X direction, and may have a diameter WBa substantially equal to a second diameter WB of the support structures SS.

The first contact structures CS1 may extend below a lower surface of the source structure <NUM> to be connected to one of the lower interconnections <NUM>. The first contact structures CS1 may pass through a lower insulating layer <NUM> that penetrates through the source structure <NUM>, in the Z direction. The first contact structures CS1 may be connected to the one gate electrode <NUM> and may be electrically insulated from the gate electrodes <NUM> that are disposed to be lower than the one gate electrode <NUM>. First insulating patterns <NUM> may be disposed between the first contact structures CS1 and the gate electrodes <NUM> may be electrically insulated from the first contact structures CS1.

One gate contact plug CMC may include a contact extension CL extending horizontally between the first contact structures CS1 constituting one group. The one gate electrode <NUM> may include a contact pad region 130RP having a relatively increased thickness, and the contact extension CL may be directly connected to the contact pad region 130RP. In the contact pad region 130RP, the thickness of the gate electrode <NUM> may be increased in a manner that is constant at the level of the lower surface and increases at the level of the upper surface. As illustrated in <FIG>, the gate electrodes <NUM> may extend to a first thickness T1, and may have a second thickness T2 greater than the first thickness T1 in the contact pad region 130RP.

The contact extensions CL may surround the first contact structures CS1 and may electrically connect the first contact structures CS1 to each other. The contact extension CL may expand from the first contact structures CS1 to have a wavy-shaped side surface in plan view. For example, the contact extension CL may have a floral pattern in a plan view.

<FIG> are schematic partial enlarged plan views of semiconductor devices. <FIG> illustrate an enlarged area corresponding to area 'A' in <FIG>.

Referring to <FIG>, first contact structures CS1 constituting one gate contact plug CMC may be arranged in a diamond shape.

Referring to <FIG>, first contact structures CS1 constituting one gate contact plug CMC may be arranged in a triangular shape.

Referring to <FIG>, first contact structures CS1 constituting one gate contact plug CMC may be arranged in a zigzag arrangement in the X direction when viewed in the Y direction. Alternatively, the first contact structures CS1 may be arranged in a 'W' shape.

Referring to <FIG>, first contact structures CS1 constituting one gate contact plug CMC may be arranged in an 'X' shape.

Referring to <FIG>, first contact structures CS1 constituting one gate contact plug CMC may be arranged in a line in the Y direction. The contact extensions CL constituting one gate contact plug CMC may be separated from each other, but may be combined with each other.

In <FIG>, the contact extensions CL may in plan view have wavy (undulating) side surfaces corresponding to the arrangement shape of the first contact structures CS1.

Referring to <FIG>, the second vertical structures VS2 may further include auxiliary patterns AP3 between the support structures SS and the first contact structures CS1. The auxiliary patterns AP3 may have a diameter WD that is less than the diameter WB of the support structures SS, and lower ends of the auxiliary patterns AP3 may be located at a higher level than the lower ends of the support structures SS. The description of the auxiliary patterns AP3 may be the same as or similar to the description of the auxiliary patterns AP of <FIG>.

Referring to <FIG>, a first contact structure CS1' may be formed by expanding a contact hole disposed in the center and merging the expanded contact hole with adjacent contact holes. The first contact structure CS1' may include a first pattern portion P1 having a relatively great diameter, and second pattern portions P2 connected to the first pattern portion P1, around the periphery of the first pattern portion P1, and having a relatively small diameter. The contact extensions CL may have wavy side surfaces in plan view corresponding to the arrangement shape of the first contact structure CS1'.

<FIG> is a schematic partially enlarged plan view of a semiconductor device. <FIG> is an enlarged view of area 'B' of <FIG>.

<FIG> is a schematic cross-sectional view of a semiconductor device. <FIG> illustrates a cross-section taken along line IV-IV' in <FIG>.

<FIG> and <FIG> relate to embodiments not forming part of the invention.

Referring to <FIG> and <FIG>, the second vertical structures VS2 may include second contact structures CS2 between the support structures SS. The second contact structures CS2 form a group and are electrically insulated from the gate electrodes <NUM>, and may be connected together with one lower interconnection <NUM> among the lower interconnections <NUM> to form one through contact plug THV. For example, one through contact plug THV may include a group of second contact structures CS2 electrically connected to each other. The second contact structures CS2 may be arranged in a hexagonal shape, but may have an arrangement or shape similar to the arrangement or shape of the contact structures illustrated in <FIG>. The second contact structures CS2 may have a continuous arrangement with the support structures SS. As illustrated in <FIG>, the second contact structures CS2 may be arranged at a pitch PBb substantially equal to the second pitch PB of the support structures SS in the X direction, and may have a diameter WBb substantially equal to the second diameter WB of the support structures SS.

The second contact structures CS2 may pass through the lower insulating layer <NUM> penetrating through the source structure <NUM>, in the Z direction. The second contact structures CS2 may be electrically insulated from the gate electrodes <NUM>. Second insulating patterns <NUM> may be disposed between the second contact structures CS2 and the gate electrodes <NUM>. In the region in which the second contact structures CS2 are disposed, the contact pad regions 130PR with increased thickness may not be formed in the pad regions 130P of the gate electrodes <NUM>. Accordingly, the second contact structures CS2 may be spaced apart from the gate electrodes <NUM> by the second insulating patterns <NUM>.

A contact stud <NUM> connected to the second contact structures CS2 may be disposed on the second contact structures CS2. The contact stud <NUM> may be connected to the upper interconnection <NUM>. Although the second contact structures CS2 are illustrated as being disposed on the second region ER, the second contact structures CS2 may be disposed on the first region CR, and may also be disposed outside of first and second regions CR and ER to be connected to the lower interconnections <NUM>.

<FIG> are schematic views illustrating a method of manufacturing a semiconductor device. Specifically, <FIG> and <FIG> are schematic plan views illustrating a method of manufacturing a semiconductor device. <FIG> illustrates cross-sections taken along lines I-I' and II-II' of <FIG>, and <FIG> illustrates cross-sections taken along lines I-I' and II-II' of <FIG>. <FIG> and <FIG> illustrate regions corresponding to the cross-sections in <FIG>.

Referring to <FIG> and <FIG>, a first structure <NUM> may be formed, a source structure <NUM> may be formed on the first structure <NUM>, interlayer insulating layers <NUM> and sacrificial layers <NUM> may be alternately stacked on the source structure <NUM>, vertical hole patterns HP penetrating through a mold structure of the interlayer insulating layers <NUM> and the sacrificial layers <NUM> may be formed, and upper portions of separation hole patterns Hs among the vertical hole patterns HP may be opened.

The first structure <NUM> may be formed by forming the circuit elements <NUM> and lower interconnections <NUM> on the substrate <NUM>.

First, device isolation layers <NUM> may be formed in the substrate <NUM>, and circuit gates <NUM> and source/drain regions <NUM> may be formed on an active region 15a on the substrate <NUM>. The device isolation layers <NUM> may be formed by a shallow trench isolation (STI) process. The dielectric layer of the circuit gate <NUM> may include silicon oxide or a high dielectric material, and the circuit gate electrode of the circuit gate <NUM> may include at least one of polycrystalline silicon, a metal, a metal nitride, or a metal-semiconductor compound. Additionally, spacer layers covering both sides of the circuit gate <NUM> may be formed.

The lower interconnections <NUM> may be formed by forming a portion of the lower capping insulating layer <NUM> and then partially etching and removing the same, and by filling with a conductive material or depositing a conductive material and then patterning the same, and then, by filling the area removed by patterning with a portion of the lower capping insulating layer <NUM>.

The source structure <NUM> may be formed on the lower capping insulating layer <NUM>. The source structure <NUM> may include a base pattern <NUM>, source sacrificial layers <NUM>, <NUM>, and <NUM>, and a second pattern <NUM>, and the source sacrificial layers <NUM>, <NUM> and <NUM> in the first region CR may be replaced with the first pattern <NUM> in a subsequent process. The second pattern <NUM> may include a portion bent to contact the base pattern <NUM> in the second region ER.

The interlayer insulating layers <NUM> and the sacrificial layers <NUM> may be alternately stacked to form a mold structure.

The sacrificial layers <NUM> may be at least partially replaced with the gate electrodes <NUM> (refer to <FIG>) in a subsequent process. The sacrificial layers <NUM> may be formed of a material different from that of the interlayer insulating layers <NUM>, and may be formed of a material that may be etched with etch selectivity for the interlayer insulating layers <NUM> under specific etching conditions. For example, the sacrificial layers <NUM> may be formed of silicon nitride, and the interlayer insulating layers <NUM> may be formed of silicon oxide.

The photolithography process and the etching process for the sacrificial layers <NUM> may be repeatedly performed using a mask layer such that the lower sacrificial layers <NUM> extend farther than the upper sacrificial layers <NUM> in the second region ER. Accordingly, the sacrificial layers <NUM> may form a stepped structure in a step shape in a predetermined unit on the second region ER. By further forming sacrificial layers on the sacrificial layers <NUM> forming the step structure, sacrificial pad regions having increased thickness (refer to '128RP' in <FIG>) may be formed. The sacrificial pad regions may be replaced with the contact pads 130RP of <FIG> through a subsequent process. A portion of the upper capping insulating layer <NUM> may be formed on the mold structure.

Vertical hole patterns HP passing through the mold structure may be formed. To form the vertical hole patterns HP, a patterning process may be performed on the entire surface of the substrate <NUM>. The patterning process may include forming a mask layer having a plurality of openings and performing an anisotropic etching process using the mask layer as an etch mask. Examples of the anisotropic etching process include plasma etching, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), or ion beam etching (IBE) process. The vertical hole pattern HP may refer to an empty space that has not yet been filled after patterning, or may refer to a structure in which a sacrificial layer, an insulating layer, or a conductive layer is deposited after patterning.

As illustrated in <FIG>, the vertical hole patterns HP may be formed to be spaced apart from each other while forming rows and columns. The vertical hole patterns HP may have a lattice arrangement. The vertical hole patterns HP may be formed to have a continuous arrangement on the first region CR and the second region ER. For example, the vertical hole patterns HP on the second region ER may have the same lattice configuration as the vertical hole patterns HP on the first region CR (for example, a common lattice arrangement). As the designs of the patterns on the first and second regions CR and ER are the same as each other, a loading effect generated during the etching process may be alleviated, and thus, continuous and uniform patterning may be obtained, thereby improving patterning dispersion.

The vertical hole patterns HP may include first hole patterns H1, second hole patterns H2, separation hole patterns Hs, and contact hole patterns Hc1 and Hc2. The first hole patterns H1, the second hole patterns H2, the separation hole patterns Hs, and the contact hole patterns Hc1 and Hc2 may all have a continuous arrangement.

The first hole patterns H1 may be formed on the first region CR. The channel structures CH may be formed by sequentially forming the gate dielectric layer <NUM>, the channel layer <NUM>, the core insulating layer <NUM>, and the channel pad <NUM> on the first hole patterns H1. The second hole patterns H2 may be formed on the second region ER. Support structures SS may be formed by sequentially forming a support dielectric layer 145d, a support channel layer 140d, a support core insulating layer 147d, and a support channel pad 149d on the second hole patterns H2. Before forming the channel structures CH and the support structures SS, the first and second hole patterns H1 and H2 may be further etched, such that the first and second hole patterns H1 and H2 penetrate through the second pattern <NUM> and the source sacrificial layers <NUM>, <NUM> and <NUM> and the lower ends thereof may be positioned at a level lower than the upper surface of the base pattern <NUM>.

The separation hole patterns Hs may be arranged in a line in the X direction, and the inside thereof may be filled with a sacrificial layer, respectively. The contact hole patterns Hc1 and Hc2 may be formed into the contact structures CS1 and CS2 of <FIG> and <FIG> through the process operations of FIGS. 13A to 13C, in a state in which the inside thereof is respectively filled with a sacrificial layer.

After a portion of the upper capping insulating layer <NUM> is formed, trenches TR extending in the X direction may be formed to expose the separation hole patterns Hs. An upper surface of the sacrificial layer of the separation hole patterns Hs may be exposed by the trenches TR.

Referring to <FIG> and <FIG>, separation openings OP may be formed by expanding the separation hole patterns Hs through the trenches TR. After selectively removing the sacrificial layer in the separation hole patterns Hs, an isotropic etching process may be performed to expand each separation hole pattern Hs. The separation hole patterns Hs arranged in the X direction may be connected to each other due to the isotropic etching process to form the separation openings OP extending in the X direction. The side surfaces of the separation openings OP may in plan view have an uneven shape, for example, a wavy (undulating) shape or an embossed shape. The separation openings OP may contact at least one of adjacent first hole patterns H1 and second hole patterns H2.

After the separation hole patterns Hs are expanded, spacers may be formed on inner walls of the expanded separation hole patterns Hs, and an etching process may be performed between the spacers to remove a portion of the second pattern <NUM> and a portion of the source sacrificial layers <NUM>, <NUM> and <NUM> to expose the base pattern <NUM>.

Referring to <FIG>, after replacing the source sacrificial layers <NUM>, <NUM>, and <NUM> in the first region CR with the first pattern <NUM> and removing the sacrificial layers <NUM>, the gate electrodes <NUM> may be formed by filling the region from which the sacrificial layers <NUM> have been removed with a conductive material.

First, during the process of removing the source sacrificial layers <NUM>, <NUM>, and <NUM>, a portion of the gate dielectric layer <NUM> exposed in the region from which the source sacrificial layer <NUM> has been removed may also be removed. The first pattern <NUM> may be formed by depositing a conductive material in the region in which the source sacrificial layers <NUM>, <NUM>, and <NUM> are removed.

The sacrificial layers <NUM> may be selectively removed with respect to the interlayer insulating layers <NUM>. The selective removal process of the sacrificial layers <NUM> may use a wet etching process. The conductive material forming the gate electrodes <NUM> may include metal, polycrystalline silicon, or a metal-semiconductor compound.

Thereafter, an insulating material may be deposited in the isolation openings OP to form separation patterns SP, an upper capping insulating layer <NUM> may be formed, and upper interconnections <NUM> may be formed, thereby manufacturing the semiconductor device <NUM>.

<FIG> are schematic views illustrating a method of forming contact structures of a semiconductor device. <FIG> illustrate a method of forming the contact structures of <FIG> and <FIG>.

Referring to <FIG>, the sacrificial layer filling the first contact hole patterns Hc1 may be removed. The first contact hole patterns Hc1 may penetrate through the lower insulating layer <NUM> to expose the via pattern <NUM> on the lower interconnections <NUM>.

Referring to <FIG>, the sacrificial layers <NUM> exposed by the first contact hole patterns Hc1 may be partially etched to form expansion spaces G horizontally extending from the first contact hole patterns Hc1, and a buffer insulating layer <NUM> may be formed on the first contact hole patterns Hc1 and the expansion spaces G. An expansion space G_U formed in preliminary contact pad regions 128RP in which the thickness of the sacrificial layers <NUM> is increased among the expansion spaces G may have a thickness greater than that of other expansion spaces G_L formed by removing the other sacrificial layers <NUM> therebelow. Accordingly, the buffer insulating layer <NUM> may not completely fill the expansion space G_U formed in the preliminary contact pad regions 128RP while filling the other expansion spaces G_L.

Referring to <FIG>, an etching process may be performed into the first contact hole patterns Hc1 to leave a portion in which the buffer insulating layer <NUM> fills the other expansion spaces G_L and to remove the remainder, thereby forming the first insulating patterns <NUM> surrounding the first contact hole patterns Hc1. Thereafter, the via patterns <NUM> may be removed, and the expansion spaces formed in the first contact hole patterns Hc1 and the preliminary contact pad regions 128RP may be filled with a conductive material to form the first contact structures CS1 of <FIG>.

Although <FIG> illustrate a method of forming the gate contact plug CMC including the first contact structures CS1, the through contact plug THV including the second contact structures CS2 may also be formed in a manner similar thereto. However, the preliminary contact pad regions 128RP in which the thickness of the sacrificial layers <NUM> is increased are not formed in the region in which the second contact hole patterns Hc2 for formation of the second contact structures CS2 are disposed. Also, the buffer insulating layer <NUM> may be disposed to fill all expansion spaces horizontally extending from the second contact hole patterns Hc2. Accordingly, the second contact structures CS2 of <FIG> and <FIG> may be formed.

<FIG> and <FIG> are schematic views illustrating a method of forming auxiliary patterns of a semiconductor device. <FIG> illustrates a cross-section taken along line V-V' in <FIG>.

Referring to <FIG> and <FIG>, the source structure <NUM> and the mold structure MD may be formed, the mask pattern <NUM> having openings OL may be formed on the mold structure MD, and the mask pattern <NUM> may be used as an etching mask to perform an etching process, thereby forming vertical hole patterns HP.

The vertical hole patterns HP may further include auxiliary hole patterns Ha between the separation hole patterns Hs and the hole patterns H. The openings OL may include a first opening OL1 having a first width W1 and a second opening OL2 having a second width W2 less than the first width W1. Auxiliary hole patterns Ha may be formed in the mold structure MD to correspond to the second opening OL2 having a relatively small width. The auxiliary hole patterns Ha may only partially penetrate through the mold structure MD from the upper portion. Due to the auxiliary hole patterns Ha, a process enhancement function that assists the photolithography process and the etching process to significantly reduce deformation of the shape of the separation hole patterns Hs and the hole patterns H may be performed.

<FIG> and <FIG> are schematic views illustrating a method of forming auxiliary patterns of a semiconductor device. <FIG> illustrates a cross-section taken along line VI-VI' of <FIG>.

Referring to <FIG> and <FIG>, the source structure <NUM> and the mold structure MD may be formed, the mask pattern <NUM> having the openings OL may be formed on the mold structure MD, and the mask pattern <NUM> may be used as an etch mask to perform an etching process, thereby forming the vertical hole patterns HP, but because a width W2' of a second opening OL2' is relatively smaller, patterning may not be performed on the mold structure MD in the region corresponding to the second opening OL2'. Even when the patterning process is not performed on the mold structure MD, the pattern continuity of the openings OL1 and OL2' may be maintained at the mask level, and therefore, the shape deformation of the separation hole patterns Hs and the hole patterns H may be significantly reduced.

<FIG> is a diagram schematically illustrating a data storage system including a semiconductor device.

Referring to <FIG>, a data storage system <NUM> may include a semiconductor device <NUM> and a controller <NUM> electrically connected to the semiconductor device <NUM>. The data storage system <NUM> may be a storage device including one or a plurality of semiconductor devices <NUM> or an electronic device including a storage device. For example, the data storage system <NUM> may be a solid state drive device (SSD), a universal serial bus (USB) device, a computing system, a medical device, or a communication device, including one or a plurality of semiconductor devices <NUM>.

The semiconductor device <NUM> may be a nonvolatile memory device, for example, the NAND flash memory device described above with reference to <FIG>. The semiconductor device <NUM> may include a first structure 1100F and a second structure <NUM> on the first structure <NUM>100F. The first structure 1100F may be disposed next to the second structure <NUM>. The first structure 1100F may be a peripheral circuit structure including a decoder circuit <NUM>, a page buffer <NUM>, and a logic circuit <NUM>. The second structure <NUM> may be a memory cell structure including a bit line BL, a common source line CSL, word lines WL, first and second upper gate lines UL1 and UL2, first and second lower gate lines LL1 and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure <NUM>, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be variously modified.

The upper transistors UT1 and UT2 may include a string select transistor, and the lower transistors LT1 and LT2 may include a ground select transistor. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

The lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 may be used for an erase operation of erasing data stored in the memory cell transistors MCT using the GIDL phenomenon.

The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit <NUM> through first connection interconnections <NUM> extending from the inside of the first structure 1100F to the second structure <NUM>. The bit lines BL may be electrically connected to the page buffer <NUM> through second connection interconnections <NUM> extending from the inside of the first structure 1100F to the second structure <NUM>.

In the first structure 1100F, the decoder circuit <NUM> and the page buffer <NUM> may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit <NUM> and the page buffer <NUM> may be controlled by the logic circuit <NUM>. The semiconductor device <NUM> may communicate with the controller <NUM> through an input/output pad <NUM> electrically connected to the logic circuit <NUM>. The input/output pad <NUM> may be electrically connected to the logic circuit <NUM> through an input/output connection interconnection <NUM> extending from the inside of the first structure 1100F to the second structure <NUM>.

The controller <NUM> may include a processor <NUM>, a NAND controller <NUM>, and a host interface <NUM>. The data storage system <NUM> may include a plurality of semiconductor devices <NUM>, and in this case, the controller <NUM> may control the plurality of semiconductor devices <NUM>.

The processor <NUM> may control the overall operation of the data storage system <NUM> including the controller <NUM>. The processor <NUM> may operate according to a predetermined firmware, and may access the semiconductor device <NUM> by controlling the NAND controller <NUM>. The NAND controller <NUM> may include a controller interface <NUM> that processes communication with the semiconductor device <NUM>. Through the controller interface <NUM>, a control command for controlling the semiconductor device <NUM>, data to be written to the memory cell transistors MCT of the semiconductor device <NUM>, data to be read from the memory cell transistors MCT, and the like may be transmitted. The host interface <NUM> may provide a communication function between the data storage system <NUM> and an external host. When receiving a control command from an external host through the host interface <NUM>, the processor <NUM> may control the semiconductor device <NUM> in response to the control command.

<FIG> is a schematic perspective view of a data storage system including a semiconductor device.

Referring to <FIG>, a data storage system <NUM> may include a main board <NUM>, a controller <NUM> mounted on the main board <NUM>, one or more semiconductor packages <NUM>, and a DRAM <NUM>. The semiconductor package <NUM> and the DRAM <NUM> may be connected to the controller <NUM> by interconnection patterns <NUM> formed on the main board <NUM>.

The main board <NUM> may include a connector <NUM> including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector <NUM> may vary according to a communication interface between the data storage system <NUM> and the external host. The data storage system <NUM> may communicate with an external host according to any one of the interfaces such as a Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), an M-Phy for Universal Flash Storage (UFS), and the like. The data storage system <NUM> may operate by power supplied from an external host through the connector <NUM>. The data storage system <NUM> may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller <NUM> and the semiconductor package <NUM>.

The controller <NUM> may write data to or read data from the semiconductor package <NUM>, and may improve the operating speed of the data storage system <NUM>.

The DRAM <NUM> may be a buffer memory for reducing a speed difference between the semiconductor package <NUM> as a data storage space and an external host. The DRAM <NUM> included in the data storage system <NUM> may also operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package <NUM>. For example, when the data storage system <NUM> includes the DRAM <NUM>, the controller <NUM> may further include a DRAM controller for controlling the DRAM <NUM> in addition to the NAND controller for controlling the semiconductor package <NUM>.

The semiconductor package <NUM> may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be a semiconductor package including a plurality of semiconductor chips <NUM>. Each of the first and second semiconductor packages 2003a and 2003b may include a package substrate <NUM>, the semiconductor chips <NUM> on the package substrate <NUM>, adhesive layers <NUM> disposed on lower surfaces of the semiconductor chips <NUM>, respectively, a connection structure <NUM> electrically connecting the semiconductor chips <NUM> and the package substrate <NUM>, and a molding layer <NUM> covering the semiconductor chips <NUM> and the connection structure <NUM> on the package substrate <NUM>.

The package substrate <NUM> may be a printed circuit board including upper package pads <NUM>. Each semiconductor chip <NUM> may include an input/output pad <NUM>. The input/output pad <NUM> may correspond to the input/output pad <NUM> of <FIG>. Each of the semiconductor chips <NUM> may include gate stack structures <NUM> and channel structures <NUM>. Each of the semiconductor chips <NUM> may include the semiconductor device described above with reference to <FIG>.

The connection structure <NUM> may be a bonding wire electrically connecting the input/output pad <NUM> and the upper package pads <NUM>. Accordingly, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips <NUM> may be electrically connected to each other by a bonding wire method, and may be electrically connected to the upper package pads <NUM> of the package substrate <NUM>. In each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips <NUM> may also be electrically connected to each other by a connection structure including a Through Silicon Via (TSV) instead of the connection structure <NUM> of the bonding wire method.

The controller <NUM> and the semiconductor chips <NUM> may be included in one package. The controller <NUM> and the semiconductor chips <NUM> may be mounted on a separate interposer substrate different from the main board <NUM>, and the controller <NUM> and the semiconductor chips <NUM> may be connected to each other by interconnections formed on the interposer substrate.

<FIG> is a cross-sectional view schematically illustrating a semiconductor package. <FIG> illustrates the semiconductor package <NUM> of <FIG>, and conceptually illustrates a region taken along line VII-VII' of the semiconductor package <NUM> of <FIG>.

Referring to <FIG>, in the semiconductor package <NUM>, the package substrate <NUM> may be a printed circuit board. The package substrate <NUM> may include a package substrate body <NUM>, upper package pads <NUM> (see <FIG>) disposed on an upper surface of the package substrate body <NUM>, lower pads <NUM> disposed on or exposed through the lower surface of the package substrate body <NUM>, and internal interconnections <NUM> electrically connecting the upper package pads <NUM> and the lower pads <NUM> inside the package substrate body <NUM>. The upper package pads <NUM> may be electrically connected to the connection structures <NUM>. The lower pads <NUM> may be connected to the interconnection patterns <NUM> of the main board <NUM> of the data storage system <NUM> as illustrated in <FIG> through conductive connection portions <NUM>.

Each of the semiconductor chips <NUM> may include a semiconductor substrate <NUM>, and a first structure <NUM> and a second structure <NUM> that are sequentially stacked on the semiconductor substrate <NUM>. The first structure <NUM> may include a peripheral circuit region including peripheral interconnections <NUM>. The second structure <NUM> may include a common source line <NUM>, a gate stack structure <NUM> on the common source line <NUM>, channel structures <NUM> passing through the gate stack structure <NUM>, bit lines <NUM> electrically connected to the channel structures <NUM>, and gate contact plugs <NUM> electrically connected to the word lines WL of the gate stack structure <NUM> (see <FIG>). As described above with reference to <FIG>, each of the semiconductor chips <NUM> may include a substrate <NUM>, a source structure <NUM>, a stack structure ST including gate electrodes <NUM>, first vertical structures VS1, and second vertical structures VS2.

Each of the semiconductor chips <NUM> may include a through interconnection <NUM> electrically connected to the peripheral interconnections <NUM> of the first structure <NUM> and extending into the second structure <NUM>. The through interconnection <NUM> may be disposed outside the gate stack structure <NUM>, and may be further disposed to pass through the gate stack structure <NUM>. Each of the semiconductor chips <NUM> may further include an input/output pad <NUM> (refer to <FIG>) electrically connected to the peripheral interconnections <NUM> of the first structure <NUM>.

<FIG> is a cross-sectional view schematically illustrating a semiconductor package. <FIG> illustrates a semiconductor package 2003A in the region corresponding to <FIG>.

Referring to <FIG>, a semiconductor package 2003A may include a first structure <NUM> on a semiconductor substrate <NUM>, and a second structure <NUM> located at the first structure <NUM> to be bonded to the first structure <NUM> by a wafer bonding method.

The first structure <NUM> may include a peripheral circuit region including a peripheral interconnection <NUM> and first bonding structures <NUM>. The second structure <NUM> may include a common source line <NUM>, a gate stack structure <NUM> between the common source line <NUM> and the first structure <NUM>, memory channel structures <NUM> passing through the gate stack structure <NUM>, and second bonding structures <NUM> electrically connected to the memory channel structures <NUM> and the word lines (WL of <FIG>) of the gate stack structure <NUM>, respectively. For example, the second bonding structures <NUM> may be electrically connected to the memory channel structures <NUM> and the word lines (WL of <FIG>) respectively, through bit lines <NUM> electrically connected to the memory channel structures <NUM> and the gate connection wirings <NUM> electrically connected to the word lines (WL in <FIG>). The first bonding structures <NUM> of the first structure <NUM> and the second bonding structures <NUM> of the second structure <NUM> may be bonded while being in contact with each other. Bonded portions of the first bonding structures <NUM> and the second bonding structures <NUM> may be formed of, for example, copper (Cu).

As illustrated in the enlarged view, each of semiconductor chips 2200a may further include a substrate <NUM>, a source structure <NUM>, a stack structure ST including gate electrodes <NUM>, first vertical structures VS1 and second vertical structures VS2. In each of semiconductor chips 2200b, the second structure <NUM> may be vertically inverted on the first structure <NUM> as compared with the semiconductor chips <NUM> of <FIG>, and the first structure <NUM> and the second structure <NUM> may be directly bonded without intervening an adhesive such as a separate adhesive layer. For example, the first bonding pads <NUM> of the first structure <NUM> may be bonded to the second bonding pads <NUM> of the second structure <NUM>. Each of the semiconductor chips 2200b may further include an input/output pad (<NUM> of <FIG>) electrically connected to the peripheral interconnections <NUM> of the first structure <NUM>.

As set forth above, as the design of vertical structures in which the gate electrodes are disposed in the step area having a step structure is the same as or similar to the design of vertical structures disposed in the memory cell array region, a semiconductor device having improved reliability and productivity and a data storage system including the same may be provided.

Claim 1:
A semiconductor device comprising:
a first structure (<NUM>) comprising a substrate (<NUM>), circuit elements (<NUM>) on the substrate, and lower interconnections (<NUM>) on the circuit elements; and
a second structure (<NUM>) on the first structure,
wherein the second structure comprises:
a source structure (<NUM>) having a first region, CR, and a second region, ER;
gate electrodes (<NUM>) provided on the source structure and spaced apart from each other, extending in a first direction parallel to an upper surface of the substrate, and comprising pad regions (130P) forming a step structure on the second region;
separation patterns, SP, passing through the gate electrodes and extending in the first direction;
first vertical structures, VS1, provided between the separation patterns on the first region and extending through the gate electrodes; and
second vertical structures, VS2, provided between the separation patterns, on the second region and extending through the pad regions of the gate electrodes, and
wherein the second vertical structures comprise support structures and contact structures, CS1, provided between the support structures,
characterised in that the second vertical structures and the first vertical structures have a common lattice arrangement;
wherein the contact structures are electrically connected to each other in one group and are commonly connected to a first gate electrode among the gate electrodes to provide one gate contact plug, CMC,
wherein the one gate contact plug comprises a contact extension, CL, that extends between the contact structures constituting the one group,
wherein the first gate electrode comprises a contact pad region, 130RP, having an increased thickness, and
wherein the contact extension is directly connected to the contact pad region of the first gate electrode.