Patent Description:
The aim of a timing recovery circuit or method is to recover the sampling clock, also known as recovered clock, from serial data stream to optimally sample the receiving data with respect to time. This is necessary because only the data signal is transmitted, but not the transmitter clock signal (e. Ethernet examples: 100Base-T1, 1000Base-T1).

The receiving data streams are encoded using Pulse-Amplitude-Modulation (PAM) scheme with <NUM> (PAM <NUM>) or two (PAM <NUM>) levels.

The Task is to sample the data at the receiver input close to an ideal sampling point, which corresponds to the ideal data position in time within the data Unit-Interval (UI) and quantize the receiving data signal to a multi-bit digital signal, e. by means of an Analogue-Digital-Converter (ADC).

Therefore, the task is to detect the timing from a series of received data symbols and to extract the ideal sampling point information.

This is done with a timing recovery circuit or method. A sampling clock signal is generated by a clock generation device which can adjust the sampling clock signal in phase and frequency by a closed control loop. A data sample is taken with this sampling clock signal by a sampling device. The timing error detector (TED) estimates the phase offset of the sample (taken with this sampling clock signal) from the ideal sampling point in receiver circuits. The TED provides the timing recovery loop control with an unambiguous control signal to recover phase and frequency of the sampling clock signal in the receiver.

The timing error detector (TED) can be implemented in different ways:.

Further timing recovery circuits and methods are for example disclosed in <CIT> and <CIT>, wherein <CIT> discloses a timing recovery circuit and method according to the preamble of claims <NUM> and <NUM>.

Furthermore, the following two articles refer to timing recovery circuits and methods:.

It is an object of the present invention to overcome the disadvantages of the prior art and to provide the timing recovery control loop with an unambiguous control signal to recover phase and frequency of the sampling clock signal in the receiver for PAM-<NUM> and PAM-<NUM> serial data stream and to detect a phase offset from the ideal sampling point while operating only with a single data sample.

According to the invention the object is solved by a method according to claim <NUM> and a timing recovery circuit according to claim <NUM>.

The method for recovering a sampling clock from a serial data stream encoded using Pulse-Amplitude-Modulation scheme, comprises the steps of:.

According to the invention the method comprises the further steps of multiplying the estimated phase error with a weight factor to obtain an error signal and adjusting the weights for different states during the initialization procedure of the timing recovery.

For example, the weights can be decreased, when the timing recovery is locked.

Pursuant to a variant of the invention the serial data stream is encoded using Pulse-Amplitude-Modulation scheme with three levels and the estimated phase error is calculated using an equation according to the following table:.

wherein note <NUM> is only applicable if no frequency offset exists, note <NUM> can only detect late sampling (e(k) < <NUM>) and note <NUM> can only detect early sampling (e(k) > <NUM>).

According to an alternative variant of the invention the serial data stream is encoded using Pulse-Amplitude-Modulation scheme with two levels and the estimated phase error is calculated using an equation according to the following table:.

Pursuant to a variant of the invention the serial data stream is encoded using Pulse-Amplitude-Modulation scheme with three levels and the weight factor is defined in the following table for early and late phase adjustment:.

According to an alternative variant of the invention the serial data stream is encoded using Pulse-Amplitude-Modulation scheme with two levels and the weight factor is defined in the following table for early and late phase adjustment:.

In a variant of the invention the method further comprises the step of filtering the data samples before the step of quantizing the data samples. Pursuant to a variant of the invention the filtering is performed by a Feed-Forward Equalizer and/or a Decision Feedback Equalizer. The filtering improves the signal to noise ration or compensates for channel characteristics, e. inter symbol interference.

In an advantageous variant of the invention the method comprises the step of applying the error signal to a bang-bang-detector with adjustable threshold and <NUM>-point control output to quantize the calculated estimated phase error and adjust it to the bit width of the control signal.

Pursuant to a variant of the invention the calculated estimated phase error is quantized by n-Bit.

The object is furthermore solved by a timing recovery circuit for recovering a sampling clock from a serial data stream encoded using Pulse-Amplitude-Modulation scheme, comprising:.

According to the invention the timing recovery circuit multiplies calculated the estimated phase error with a weight factor to obtain an error signal and adjusts the weights of the digital timing error detector for different states during the initialization procedure of the timing recovery.

In a variant of the invention the timing recovery circuit further comprises a digital filter for filtering the data samples before the step of quantizing the data samples. Pursuant to a variant of the invention the digital filter is a Feed-Forward Equalizer and/or a Decision Feedback Equalizer. The filtering improves the signal to noise ration or compensates for channel characteristics, e. inter symbol interference.

In an advantageous variant of the invention the timing recovery circuit comprises a bang-bang-detector with adjustable threshold and <NUM>-point control output to quantize the calculated estimated phase error and adjust it to the bit width of the control signal.

According to a variant of the invention the calculated estimated phase error is quantized by n-Bit.

In the following the invention will be further explained with reference to the embodiments shown in the figures.

<FIG> shows a block diagram of a timing recovery circuit according to the state of the art. According to <FIG> a sampling clock signal <NUM> is generated by a clock generation device <NUM> which can adjust the sampling clock signal <NUM> in phase and frequency by a closed control loop. A data sample <NUM> is taken with this sampling clock signal <NUM> by a sampling device <NUM>. The timing error detector (TED) <NUM> estimates the phase offset of the sample <NUM> (taken with this sampling clock signal <NUM>) from the ideal sampling point in receiver circuits. The TED <NUM> provides the timing recovery loop control <NUM> with an unambiguous control signal <NUM> to recover phase and frequency of the sampling clock signal <NUM> in the receiver. The TED can be implemented in different ways using the above-mentioned Mueller-Müller TED, Early-Late Detector, Gardner TED or Oversampling TED.

<FIG> shows a PAM-<NUM> signal with ideal sampling points, <FIG> a PAM-<NUM> signal with ideal sampling points and <FIG> a PAM-<NUM> signal with early sampling and corresponding detected symbols ŷ(k).

<FIG> shows a block diagram of a timing recovery circuit according to the invention. The block diagram of <FIG> presents the part of the receiver front-end which is responsible for sampling of the receiving data signal and the adjustment of the sampling point. The TED is depicted in detail in <FIG>.

A series of adjacent incoming data samples (ADC output values y(k) <NUM>,<NUM>) and the corresponding detected symbol ŷ(k) <NUM>,<NUM> are stored in registers to preserve data for phase error estimation.

The ADC output values y(k) <NUM> can be optionally processed by a digital filter (like a Feed-Forward Equalizer FFE and/or a Decision Feedback Equalizer DFE) to improve the signal to noise ration or to compensate for channel characteristics <NUM>, e. inter symbol interference.

In each time step k, a digital filter pattern decoder is applied to the current and last symbols to determine if this symbol sequence can be used to estimate the phase offset of the sampling clock signal from the ideal sampling point.

Depending on to the detected symbol pattern of four adjacent samples <NUM>, the estimated phase error is calculated using an equation, implemented in a digital timing error detector TED, as summarized in Table <NUM> below.

An example of incorrect sampling is represented in <FIG>.

The equation in Table <NUM> is a modified version of the Mueller-Müller (MM) algorithm <NUM>. Mueller-Müller only considers two adjacent symbols to estimate the phase error, this invention considers more than two. When applying Mueller-Müller, wrong decisions can be made. At symbol sequences, that cannot be used to derive an unambiguous control signal, no phase correction decision is made in this invention. When applied to PAM-<NUM> signals this method takes advantage of double zero symbols ŷ(k - <NUM>) = ŷ(k) = <NUM>. That means in total <NUM> out of <NUM> symbol sequences can be utilized to estimate the phase error value.

Without any frequency offset, <NUM> more symbol sequences can be utilized for the phase error estimation of a PAM-<NUM> or PAM-<NUM> serial data stream.

If the proposed scheme from Table <NUM> is not applied, only <NUM> out of <NUM> symbol sequences can be used, since <NUM> sequences contain double zero symbols, whereas <NUM> of <NUM> give zero as result and another <NUM> of <NUM> could give a faulty error value e(k).

This error signal e(k) <NUM> is multiplied with a weight factor w depending on the symbol sequence to obtain the error signal <NUM> e*(k) = w * e(k). The pattern dependent weights w are shown in Table <NUM>.

There are different weights w for early and late phase adjustment. This has the benefit to increase/decrease the sensitivity to certain data symbol sequences.

The pattern dependent weights w are adjusted for different states during the initialization procedure of the timing recovery. The timing recovery contains a Finite-State-Machine (FSM) that controls the timing recovery control loop during the initialization procedure. The two main states are lock-in and locked. The FSM is also capable of changing the pattern dependent weights w according to the current state of the lock-in procedure, e. the weights can be increased, when the timing recovery is in the lock-in state, or the weights can be decreased, when the timing recovery is locked.

The phase error e*(k) <NUM> is used to adjust the phase of the sampling clock signal within the timing recovery control loop.

The phase error e*(k)is optionally applied to a bang-bang-detector with adjustable threshold and <NUM>-point control output <NUM> to quantize the error signal and therefore adjust it to the bit width of the control signal <NUM>.

The phase error e*(k) is optionally quantized by n-Bit.

<FIG> shows a block diagram of another embodiment of a timing error detector. The TED shown in <FIG> comprises an optional quantizer, while the TED in <FIG> is shown without a quantizer.

The method according to the invention is applicable to PAM-<NUM> signals. In this case <NUM> symbol sequences out of <NUM> can be used to estimate the error signal e(k) (Table <NUM>).

Without any frequency offset, <NUM> more symbol sequences can be utilized for the phase error estimation. If the proposed scheme from Table <NUM> is not applied, then <NUM> out of <NUM> symbol sequences would be used for phase error estimation, but <NUM> of <NUM> give zero as result and another <NUM> of <NUM> could result in a faulty error value e(k).

The invention mainly refers to:
Apply a filter pattern decoder to detected symbol sequence at more than two adjacent data symbols. Especially to the detected symbol patterns of four adjacent samples ŷ(k - <NUM>);ŷ(k - <NUM>),ŷ(k),ŷ(k + <NUM>), utilize the formula in Table <NUM> to estimate the phase error e(k);.

This error signal e(k) is multiplied with a weight factor depending on the symbol sequence to obtain the weighted error signal e*(k) = w * e(k);.

The weighted error signal e*(k) is quantized and used to adjust the phase of the sampling clock signal within the timing recovery control loop.

Claim 1:
Method for recovering a sampling clock from a serial data stream encoded using Pulse-Amplitude-Modulation scheme, comprising the steps of:
sampling received data signals from the serial data stream by an analog-to-digital converter once per unit-interval using a sampling clock signal provided by a clock generating device providing a timing recovery loop control,
quantizing the incoming data samples with a slicer as corresponding detected symbols,
storing adjacent incoming data samples and the corresponding detected symbols to preserve data for phase error estimation,
applying a digital filter pattern decoder to the current and last detected symbols to determine if this symbol sequence can be used to estimate a phase offset of the sampling clock signal from the ideal sampling point and calculating the estimated phase error depending on the detected symbol pattern of four adjacent samples,
adjusting the phase of the sampling clock signal within the timing recovery loop control using the calculated estimated phase error,
characterized by
the further steps of multiplying the estimated phase error with a weight factor to obtain an error signal and adjusting the weights for different states during the initialization procedure of the timing recovery.