Patent Description:
Many traditional mobile devices (e.g., mobile phones) include one or more cameras for capturing images. To provide for image stabilization and focus, a position of a camera within a plane substantially parallel to a subject of an image as well as a position of a lens of the camera in a direction perpendicular to such plane, may be controlled by a plurality of motors under the control of a camera controller. A control system may be implemented using an applications processor of the mobile device coupled via a communication interface (e.g., an Inter-Integrated Circuit or I2C interface) to a camera controller local to the camera and its various motors. For example, the applications processor may communicate to the camera controller a vector of data regarding a target position for the camera, whereas the camera controller may communicate to the applications processor a vector regarding an actual position of the camera, as sensed by a plurality of magnetic sensors (e.g., Hall sensors) and/or other appropriate sensors.

A camera controller may receive a number of disparate-rate data streams and sub-streams, which it must manage and deliver to other processing components for processing of data in order to control components (e.g., motors) of the camera. Other control systems, including those used in devices other than for cameras, may also receive a number of disparate-rate data streams and sub-streams, which must also be managed and delivered to other processing components for processing of data in order to provide control of one or more components. Effective and flexible systems and methods for facilitating delivery and management of data streams are desired.

<CIT> discloses a mixed signal integrated circuit device.

<NPL>, discloses a hardware modification to a standard digital signal processor.

In accordance with the teachings of the present disclosure, the disadvantages and problems associated with delivery and management of disparate data streams may be reduced or eliminated.

In accordance with embodiments of the present disclosure, a system includes a processing engine and an analog-to-digital conversion interface subsystem communicatively coupled to the processing engine. The processing engine is configured to process feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate, and wherein the sample rate establishes an input sample rate of the plurality of data stream sequences and an output sample rate of digital control signals; and based on processing of the feedback data, generate the digital control signals for controlling a system under control. An analog-to-digital conversion interface subsystem communicatively coupled to the processing engine and is configured to control the processing of the processing engine and the generation of the digital control signals due to the processing engine to reduce latency in the generation of the digital control signals due to processing of the processing engine, wherein the analog-to-digital conversion interface subsystem is further configured to modify the output sample rate from an initial output sample rate to a modified output sample rate.

In accordance with these and other embodiments of the present disclosure, a method includes processing feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate, and wherein the sample rate establishes an input sample rate of the plurality of data stream sequences and an output sample rate of digital control signals, based on processing of the feedback data, generating the digital control signals for controlling a system under control, controlling the processing of a processing engine and the generation of the digital control signals by the processing engine to reduce latency in the generation of the digital control signals due to processing of the processing engine; and modifying the output sample rate from an initial output sample rate to a modified output sample rate.

In accordance with these and other embodiments of the present disclosure, a computer program product includes a computer usable medium having computer readable code physically embodied therein. The computer program product comprising computer readable program code for processing feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate, and wherein the sample rate establishes an input sample rate of the plurality of data stream sequences and an output sample rate of digital control signals, based on processing of the feedback data, generating the digital control signals for controlling a system under control, and controlling the processing of a processing engine and the generation of the digital control signals by the processing engine to reduce latency in the generation of the digital control signals due to processing of the processing engine; and modifying the output sample rate from an initial output sample rate to a modified output sample rate.

Technical advantages of the present disclosure may be readily apparent to one having ordinary skill in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure.

A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:.

<FIG> illustrates a block diagram of selected components of an example mobile device <NUM>, in accordance with embodiments of the present disclosure. As shown in <FIG>, mobile device <NUM> may comprise an enclosure <NUM>, an applications processor <NUM>, a microphone <NUM>, a radio transmitter/receiver <NUM>, a speaker <NUM>, and a camera module <NUM> comprising a camera <NUM> and a camera controller <NUM>.

Enclosure <NUM> may comprise any suitable housing, casing, or other enclosure for housing the various components of mobile device <NUM>. Enclosure <NUM> may be constructed from plastic, metal, and/or any other suitable materials. In addition, enclosure <NUM> may be adapted (e.g., sized and shaped) such that mobile device <NUM> is readily transported on a person of a user of mobile device <NUM>. Accordingly, mobile device <NUM> may include but is not limited to a smart phone, a tablet computing device, a handheld computing device, a personal digital assistant, a notebook computer, a video game controller, or any other device that may be readily transported on a person of a user of mobile device <NUM>.

Applications processor <NUM> may be housed within enclosure <NUM> and may include any system, device, or apparatus configured to interpret and/or execute program instructions and/or process data, and may include, without limitation a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), or any other digital or analog circuitry configured to interpret and/or execute program instructions and/or process data. In some embodiments, applications processor <NUM> may interpret and/or execute program instructions and/or process data stored in a memory (not explicitly shown) and/or other computer-readable media accessible to applications processor <NUM>.

Microphone <NUM> may be housed at least partially within enclosure <NUM>, may be communicatively coupled to applications processor <NUM>, and may comprise any system, device, or apparatus configured to convert sound incident at microphone <NUM> to an electrical signal that may be processed by applications processor <NUM>, wherein such sound is converted to an electrical signal using a diaphragm or membrane having an electrical capacitance that varies based on sonic vibrations received at the diaphragm or membrane. Microphone <NUM> may include an electrostatic microphone, a condenser microphone, an electret microphone, a microelectromechanical systems (MEMs) microphone, or any other suitable capacitive microphone.

Radio transmitter/receiver <NUM> may be housed within enclosure <NUM>, may be communicatively coupled to applications processor <NUM>, and may include any system, device, or apparatus configured to, with the aid of an antenna, generate and transmit radio-frequency signals as well as receive radio-frequency signals and convert the information carried by such received signals into a form usable by applications processor <NUM>. Radio transmitter/receiver <NUM> may be configured to transmit and/or receive various types of radio-frequency signals, including without limitation, cellular communications (e.g., <NUM>, <NUM>, <NUM>, LTE, etc.), short-range wireless communications (e.g., BLUETOOTH), commercial radio signals, television signals, satellite radio signals (e.g., GPS), Wireless Fidelity, etc..

Speaker <NUM> may be housed at least partially within enclosure <NUM> or may be external to enclosure <NUM>, may be communicatively coupled to applications processor <NUM>, and may comprise any system, device, or apparatus configured to produce sound in response to electrical audio signal input. In some embodiments, speaker <NUM> may comprise a dynamic loudspeaker, which employs a lightweight diaphragm mechanically coupled to a rigid frame via a flexible suspension that constrains a voice coil to move axially through a magnetic gap. When an electrical signal is applied to the voice coil, a magnetic field is created by the electric current in the voice coil, making it a variable electromagnet. The voice coil and the driver's magnetic system interact, generating a mechanical force that causes the voice coil (and thus, the attached cone) to move back and forth, thereby reproducing sound under the control of the applied electrical signal coming from the amplifier.

Camera <NUM> may be housed at least partially within enclosure <NUM> (and partially outside of enclosure <NUM>, to enable light to enter a lens of camera <NUM>), and may include any suitable system, device, or apparatus for recording images (moving or still) into one or more electrical signals that may be processed by applications processor <NUM>. As shown in <FIG>, camera <NUM> may include a plurality of motors <NUM>, sensors <NUM>, and image capturing components <NUM>.

Image capturing components <NUM> may include a collection of components configured to capture an image, including without limitation one or more lenses and image sensors for sensing intensities and wavelengths of received light. Such image capturing components <NUM> may be coupled to applications processor <NUM> such that camera <NUM> may communicate captured images to applications processor <NUM>.

Motors <NUM> may be mechanically coupled to one or more of image capturing components <NUM> and each motor <NUM> may include any suitable system, device, or apparatus configured to, based on current signals received from camera controller <NUM> indicative of a desired camera position, cause mechanical motion of such one or more image capturing components <NUM> to a desired camera position.

Sensors <NUM> may be mechanically coupled to one or more of image capturing components <NUM> and/or motors <NUM> and may be configured to sense a position associated with camera <NUM>. For example, a first sensor <NUM> may sense a first position (e.g., x-position) of camera <NUM> with respect to a first linear direction, a second sensor <NUM> may sense a second position (e.g., y-position) of camera <NUM> with respect to a second linear direction normal to the first linear direction, and a third sensor <NUM> may sense a third position (e.g., z-position) of camera <NUM> (e.g., position of lens) with respect to a third linear direction normal to the first linear direction and the second linear direction.

Camera controller <NUM> may be housed within enclosure <NUM>, may be communicatively coupled to camera <NUM> and applications processor <NUM> (e.g., via an Inter-Integrated Circuit (I2C) interface), and may include any system, device, or apparatus configured to control motors <NUM> or other components of camera <NUM> to place components of camera <NUM> into a desired position. Camera controller <NUM> may also be configured to receive signals from sensors <NUM> regarding an actual position of camera <NUM> and/or regarding a status of camera <NUM>. As shown in <FIG>, camera controller <NUM> may include a control subsystem <NUM> and current drivers <NUM>.

Control subsystem <NUM> may be integral to camera controller <NUM>, and may include any system, device, or apparatus configured to interpret and/or execute program instructions and/or process data, and may include, without limitation a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), or any other digital or analog circuitry configured to interpret and/or execute program instructions and/or process data. In some embodiments, control subsystem <NUM> may interpret and/or execute program instructions and/or process data stored in a memory and/or other computer-readable media accessible to control subsystem <NUM>. Specifically, control subsystem <NUM> may be configured to perform functionality of camera controller <NUM>, including but not limited to control of motors <NUM> and receipt and processing of data from sensors <NUM>.

Current drivers <NUM> may comprise a plurality of circuits, each such circuit configured to receive one or more control signals from control subsystem <NUM> (including without limitation a signal indicative of a desired target current for a motor <NUM>) and drive a current-mode signal to a respective motor <NUM> in accordance with the one or more control signals in order to control operation of such respective motor <NUM>.

As may be recognized by those of skill in the art, taken together control subsystem <NUM>, current drivers <NUM>, motors <NUM>, and sensors <NUM> may form a closed-loop feedback control system. <FIG> illustrates a block diagram of selected components of a closed-loop feedback control subsystem <NUM>, in accordance with embodiments of the present disclosure. As shown in <FIG>, closed-loop feedback control subsystem <NUM> may include a processing engine <NUM>, a digital-to-analog converter (DAC) subsystem <NUM>, a system under control <NUM>, an analog-to-digital converter (ADC) subsystem <NUM>, and an ADC interface subsystem <NUM>. In camera module <NUM>, processing engine <NUM> may be implemented by control subsystem <NUM>, system under control <NUM> may be implemented by motors <NUM>, DAC subsystem <NUM> may be implemented by current drivers <NUM>, and feedback signals shown in <FIG> may be provided by sensors <NUM>.

Processing engine <NUM> may include any system, device, or apparatus configured to interpret and/or execute program instructions and/or process data, and may include, without limitation a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), or any other digital or analog circuitry configured to interpret and/or execute program instructions and/or process data. In some embodiments, processing engine <NUM> may interpret and/or execute program instructions and/or process data stored in a memory and/or other computer-readable media accessible to processing engine. Specifically, processing engine <NUM> may be configured to perform control of system under control <NUM>, including the generation of control signals for system under control <NUM> and receipt of feedback signals from sensors associated with system under control <NUM>.

DAC subsystem <NUM> may comprise any suitable system, device, or apparatus configured to receive digital control signals from processing engine <NUM> and convert such digital control signals into equivalent analog control signals for controlling operation of system under control <NUM>.

System under control <NUM> may comprise any suitable system, device, or apparatus configured to operate in accordance with one or more control signals received from processing engine <NUM>. As shown in <FIG>, system under control <NUM> may generate signals (which may be generated by sensors integral to system under control <NUM>), wherein such one or more feedback signals are indicative of a physical quantity (e.g., a position, velocity, temperature, etc.) associated with system under control <NUM>.

ADC subsystem <NUM> may comprise any suitable system, device, or apparatus configured to receive analog feedback signals and convert such analog feedback signals into equivalent digital feedback signals for processing by processing engine <NUM>. In some embodiments, ADC subsystem <NUM> may be implemented using a time-division-multiplexed ADC, wherein each sampling sequence of ADC subsystem <NUM> may be divided into a plurality of sub-sequences or "slots" wherein each sensor of system under control <NUM> may be assigned to one or more of such slots. In some embodiments, a slot may be further time-division multiplexed into a plurality of sub-slots. Accordingly, ADC subsystem <NUM> may generate multiple streams of feedback (e.g., sensor) data at various data rates.

ADC interface subsystem <NUM> may comprise any suitable system, device, or apparatus configured to receive the digital feedback signals generated by ADC subsystem <NUM>, which may be received in the form of multiple streams of feedback (e.g., sensor) data at various data rates. ADC interface subsystem <NUM> may further manage such multiple streams of data to provide for flexibility and minimized latency for processing by processing engine <NUM> to generate outputs (e.g., control signals) that affect system under control <NUM>, as described in greater detail below.

<FIG> illustrates a block diagram of selected components of processing engine <NUM>, ADC subsystem <NUM>, and ADC interface subsystem <NUM>, in accordance with embodiments of the present disclosure embodiments of the present disclosure. As shown in <FIG>, ADC interface subsystem <NUM> may include a highly-programmable controller <NUM> configured to carry out overall management of ADC interface subsystem <NUM>. Such programmability of controller <NUM> that may include, for example, shadow registers integral to or otherwise accessible to controller <NUM> may be used to allow for data configurations to be updated continuously without affecting then-current processing of data.

As depicted in <FIG>, controller <NUM> may communicate a control signal START_SLOT_TIMER to a slot timer <NUM> for indicating the start of a slot (i.e., sub-cycle) of feedback data. Slot timer <NUM> may be configured to communicate a signal SLOT_TIMER_DONE indicating to controller <NUM> that a duration of a slot has expired. Accordingly, conversion time of a single sample may be programmable via slot timer <NUM>.

Also as shown in <FIG>, ADC interface subsystem <NUM> may include a slot configuration block <NUM> configured to receive configuration settings CONFIG and from the configuration settings CONFIG, determine a number of slots per sequence of ADC subsystem <NUM> and communicate one or more signals indicative of such number of slots per sequence to controller <NUM> and a sequence counter <NUM>. Accordingly, slot configuration block <NUM> may serve to configure a number of data streams to be processed by processing engine <NUM>. Further control of each data stream may include configuration settings for selectively enabling and disabling data conversion (e.g., conversion from analog to digital domain), selectively enabling and disabling data processing (e.g., processing by processing engine <NUM>), and/or controlling a sampling rate of each data stream.

Configuration settings for slot configuration block <NUM> may also be set to mitigate effects of data noise. For example, in some instances the interaction between analog to digital conversions of data streams may cause the presence of data noise which may lead to inaccuracies. Accordingly, configuration settings for slot configuration block <NUM> may be modified in order to modify an order of data streams within a data sequence.

Based on a periodic clock signal CLK, the number of slots, and a signal INCR_SEQ, sequence counter <NUM> may control data rates of each data stream, such that the rates of each data stream are configurable. Accordingly, controller <NUM> may communicate control signal INCR_SEQ to sequence counter <NUM>, wherein such control signal INCR_SEQ may be asserted (e.g., pulse high) each time control signal SLOT_TIMER_DONE pulses, in order to increase sequence counter <NUM>. Sequence counter <NUM> may in turn be configured to communicate a signal SEQ_DONE indicating to controller <NUM> that a duration of a sequence has expired.

In some embodiments, various rates may further be configured with programmable sub-slots within each slot. In addition or alternatively, data rates may be controlled after setting a number of slots by either not assigning a data stream to a slot or assigning a data stream to more than one slot.

Based on the control signals received by controller <NUM> from slot timer <NUM>, slot configuration block <NUM>, and sequence counter <NUM>, controller <NUM> may generate various control signals for controlling a time-division multiplexed ADC <NUM>. Such control signals may include a channel identifier CH_ID identifying a data channel of the feedback data to be converted in a particular slot of a sequence (e.g., identifying a sensor for which data is to be converted during the particular slot) and a conversion start indicator causing conversion of data for a particular slot to begin.

ADC <NUM> may comprise any suitable system, device, or apparatus configured to receive analog feedback data and convert data streams within such feedback to digitally equivalent signals ADC_DATA based on control signals received from controller <NUM> which defines slot parameters of the data streams. In some embodiments, ADC <NUM> may comprise a successive approximation ADC or SAR ADC. When ADC <NUM> has finished conversion of a data stream slot, ADC <NUM> may communicate to controller <NUM> a control signal CONV_DONE indicating that conversion of the data stream slot is complete.

As shown in <FIG>, ADC subsystem <NUM> may include a bridge interface <NUM>. Bridge interface <NUM> may comprise any system, device, or apparatus configured to control delivery of data SAMPLE_DATA from ADC subsystem <NUM> to processing engine <NUM>. As data is converted by ADC subsystem <NUM>, bridge interface <NUM> may control delivery of data SAMPLE_DATA to a buffer (e.g., within memory <NUM>) associated with processing engine <NUM>. As data is transferred from ADC subsystem <NUM> to buffers associated with processing engine <NUM>, bridge interface <NUM> may append the converted data with metadata regarding the converted data (e.g., stream identifier, phase information, conversion type, etc.). In some embodiments, each stream may have its own dedicated memory buffer. In other embodiments, multiple streams may be combined into a single buffer. A bridge <NUM> (shown as integral to processing engine <NUM> in <FIG>, but which may be integral to ADC subsystem <NUM> or ADC interface subsystem <NUM>) may communicate a signal SAMPLES_READY to a processing core <NUM> of processing engine <NUM>, in order to alert processing core <NUM> to the presence of data that may be processed. In some instances, bridge <NUM> may provide such alert after a programmable number of buffer writes have occurred, thus setting a decimation rate for the overall system.

As also shown in <FIG>, ADC interface subsystem <NUM> may include a programmable control loop timer <NUM>. Control loop timer <NUM> may be configured to determine an overall control rate for the system. When control loop timer <NUM> expires, it may communicate a control signal LOOP_TIMER_EXPIRE to core <NUM> to begin its control processing algorithm for generating control signals to ADC subsystem <NUM>. Control loop timer <NUM> may also include a programmable phase offset relative to the arrival of data streams. To avoid additional latency in the application of updates to control signals generated by processing engine <NUM>, control loop timer <NUM> may implement a second timer to generate a control signal CONTROL_LOOP_OFFSET_UPDATE to alert digital output drivers <NUM> of processing engine <NUM> of new data to be driven to DAC subsystem <NUM>. This second timer indicated by control signal CONTROL_LOOP_OFFSET_UPDATE may initiate when control loop timer <NUM> expires and the programmable duration of the second timer may be determined by the time needed for processing algorithms of processing engine <NUM>. In operation, processing engine <NUM> may split its processing algorithms into critical and non-critical sections, in order to minimize latency of control updates.

Core <NUM> may, based on sample data stored in memory <NUM> and timing parameters of control signals LOOP_TIMER EXPIRE and SAMPLES_READY, generate CONTROL_DATA for controlling digital output drivers <NUM> to drive digital control signals to DAC subsystem <NUM>.

Using the systems and methods disclosed herein, ADC conversion interface subsystem <NUM> may enable a processing deadline for processing the plurality of data stream sequences in order to generate control signals for DAC subsystem <NUM> independent of the sample rate of ADC <NUM>. Thus, the sample rate used for ADC <NUM> establishes an input sample rate of a plurality of data stream sequences and an output sample rate of digital control signals, and the ADC conversion interface subsystem is configured to modify the output sample rate for driving control signals to DAC subsystem <NUM> to optimally align the digital control signals.

As used herein, when two or more elements are referred to as "coupled" to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, "each" refers to each member of a set or each member of a subset of a set.

Although exemplary embodiments are illustrated in the figures and described below, the principles of the present disclosure may be implemented using any number of techniques. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the drawings and described above.

Unless otherwise specifically noted, articles depicted in the drawings are not necessarily drawn to scale.

Claim 1:
A system (<NUM>) comprising:
a processing engine (<NUM>) configured to:
process feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate, and wherein the sample rate establishes an input sample rate of the plurality of data stream sequences for processing by the processing engine (<NUM>) and an output sample rate of digital control signals generated by the processing engine (<NUM>); and
based on processing of the feedback data, generate the digital control signals for controlling a system under control (<NUM>); and
an analog-to-digital conversion interface subsystem (<NUM>) communicatively coupled to the processing engine (<NUM>) and configured to control the processing of the processing engine (<NUM>) and the generation of the digital control signals by the processing engine (<NUM>) to reduce latency in the generation of the digital control signals due to processing of the processing engine (<NUM>), wherein the analog-to-digital conversion interface subsystem (<NUM>) is further configured to modify the output sample rate from an initial output sample rate to a modified output sample rate,.