Patent Description:
<CIT> relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal.

When designing a system or performing a reset response, metrics such as latency, the response time of the reset, and entry/exit power, the power used during a reset, can be important. There is often a tradeoff between latency and entry/exit power: a reset with a higher voltage has a greater latency, and a reset at a lower voltage has a reduced latency. Typically, digital logic systems are designed to have a fixed latency for all resets, regardless of the power usage.

This specification describes methods and systems for dynamically changing reset latency for a digital logic system. For example, the reset latency can change depending on the voltage required to reset the system. A desired reset latency can be determined using a target voltage for the reset of the digital logic system. Changing the reset latency depending on the voltage can reduce latency in the system overall.

The described methods and systems reduce the latency of resets in digital logic systems. Typically, systems are designed to have a fixed latency for all resets, regardless of the power usage. The described methods and systems allow for a dynamic reset latency depending on the power usage, which overall reduces latency in the system. Also, the described methods and systems can use natural scaling, which makes the latency predictable for further scaling. The described methods and systems can advantageously save power: clock network power can be saved, e.g., by reducing toggle cycles when high latencies are not required, and reset network power can be saved by using natural scaling. The described methods and systems advantageously allow a user to control the latency of their system, e.g., through programming the reset settings. Also, changes in reset latency can increase security of the device, e.g., because a hacker may not know the exact latency of the reset.

<FIG> is a diagram of an example system <NUM>. The system <NUM> can include a number of components <NUM>, <NUM>, <NUM>, <NUM>. Each of the components <NUM>, <NUM>, <NUM>, <NUM> can be any appropriate functional component, e.g., a memory, e.g., a static random access memory (SRAM); a processing device; or a power controller, to name just a few examples. The system includes a reset network <NUM>, which illustrates how a reset signal would propagate throughout the components <NUM>, <NUM>, <NUM>, <NUM>. The system also includes a clock network <NUM> through which a clock signal would propagate to the components <NUM>, <NUM>, <NUM>, <NUM>. Both the reset network <NUM> and the clock network <NUM> include a delay component, in which the signal takes longer to reach the components <NUM>, <NUM> that are further from the source of the signal. The delay component in the networks can cause issues in resetting the components. In some implementations, the reset network can be controlled to run at an inverted clock phase. The inverted clock phase can help synchronize the signal with its arrival at the components, so that the components <NUM>, <NUM>, <NUM>, <NUM> reset at the same time.

<FIG> illustrates plots that show the benefits of dynamic reset latency. For example, a first plot <NUM> illustrates the number of clock cycles required for a reset versus a target voltage for the reset. There is often a tradeoff between latency and entry/exit power: a reset with a higher voltage has a greater latency, and a reset at a lower voltage has a reduced latency. Typically, digital logic systems are designed to have a fixed latency for all resets, regardless of the power usage. As illustrated in the plot <NUM>, latency can be reduced at lower desired voltages. For example, a reset at <NUM> volt requires <NUM> clock cycles; however, resets at lower voltages can use fewer clock cycles. As the desired voltage decreases, the required number of clock cycles also decreases. The number of clock cycles required for a reset can be determined from the target voltage of the reset. For example, the number of clock cycles can be determined by dividing the average reset latency by the functional clock cycle time. The required number of clock cycles can also be determined by dividing a value that is statistically similar to the average, e.g., the median and/or the mean plus sigma, by the functional clock cycle time. In some implementations, the required number of clock cycles is equal to the ceiling of reset latency divided by the operating frequency.

A second plot <NUM> illustrates the cost opportunity of using a fixed latency for all resets. For example, at high voltages, e.g., <NUM> volt, there is a low cost opportunity because a high voltage reset requires more clock cycles. However, at lower voltages, e.g., <NUM> volts, there is a higher cost opportunity because the low voltage reset could use fewer clock cycles. The cost opportunity increases because the reset is using more clock cycles than are necessary.

<FIG> illustrates a reset synchronizer <NUM> that is connected to a system <NUM>. For example, the system can be similar to the system <NUM> of <FIG>. The reset synchronizer can control the reset network and the clock network of the system. For example, the reset synchronizer can run for a determined number of cycles. The determined number of cycles determines the latency of the reset. As illustrated, the reset synchronizer <NUM> controls a clock gate. The clock gate can control the clock network of the system. In some implementations, the reset synchronizer <NUM> can be controlled to run at an inverted clock phase. The inverted clock phase can help synchronize the reset signal to arrive at the numerous components of the system at the same time. In some implementations, the reset synchronizer can be controlled by software. For example, a user could control the reset synchronizer to run for a desired number of cycles. In other implementations, the reset synchronizer is bounded by the design of the system. For example, the desired number of clock cycles could be predetermined for each voltage, and the run synchronizer can be programmed to run accordingly.

<FIG> illustrates an example reset synchronizer <NUM>. For example, the reset synchronizer <NUM> could be connected to a system and control the reset network and the clock network of the system similarly to the reset synchronizer <NUM> of <FIG>. The reset synchronizer <NUM> includes a programmable counter <NUM>. In some implementations, the programmable counter can be configured via a software process, e.g., via a signal generator <NUM>. In some implementations, preconfigured settings, e.g., for various scenarios, stored within the signal generator <NUM> can be applied to program the programmable counter to run for a desired number of cycles. For example, different voltage and latency cycles can be useful for designers who intend to improve latency at given voltage ranges. In some implementations, it can be desirable to lower the number of cycles required at low voltages. In some implementations, the signal generator can dynamically select a value to apply to the programmable counter, e.g., by calculating an optimal value as described above. In other implementations, the counter <NUM> is bounded by the design of the system. For example, the desired number of clock cycles could be predetermined for each voltage, and the counter <NUM> can be programmed to run accordingly. The reset synchronizer also includes a dynamic voltage frequency scaling (DVFS) decoder <NUM>. The DVFS decoder can change the frequency of received signals for processing. For example, the DVFS decoder adjusts the number of cycles to release or disable reset based on a combination of voltage and frequency. The reset synchronizer <NUM> also includes reset pipe slices <NUM>. The reset pipe slices <NUM> can ensure that the reset signal is inverted. Running the reset signal at an inverted phase can help synchronize the reset signal to arrive at the numerous components of the system at the same time. This can be especially advantageous when there is a large reset network, e.g., for a large number of components. The reset synchronizer <NUM> includes a clock enabler <NUM>, which can send a signal to a clock gate. For example, the reset synchronizer <NUM> can control a clock gate, similar to the reset synchronizer <NUM> of <FIG>.

The reset synchronizer can have more or fewer components. For example, <FIG> illustrates an example reset synchronizer <NUM> with fewer components. The reset synchronizer <NUM> includes a programmable counter <NUM>, which can be similar to the programmable <NUM> of <FIG>, and a clock enabler <NUM>, which can be similar to the clock enabler <NUM> of <FIG>. The reset synchronizer <NUM> can be connected to a system and can control the reset network and the clock network of the system, similar to the reset synchronizer <NUM> of <FIG>.

<FIG> illustrates a set of plots <NUM> illustrating reset and clock signals that can be sent to a system. For example, the reset and clock signals can propagate through a reset network and clock network, as discussed above. The clock phase <NUM> illustrates how many clock cycles go by during the process of resetting. As illustrated, a reset signal <NUM> is received. For example, the reset signal can be received by a reset synchronizer. An inverted reset signal <NUM> is inverted relative to the clock phase <NUM>. The inverted reset signal <NUM> can be transmitted in response to the reset signal <NUM> being received. For example, the inverted reset signal <NUM> can be transmitted by a reset synchronizer. Signal <NUM> represents the reset signal being asserted over the reset network. As illustrated, the signal <NUM> is running on an inverted phase similar to inverted reset signal <NUM>. When the signal <NUM> has reached the components of the system, the reset is de-asserted. The de-assertion of the reset is illustrated by the signal <NUM>, which is a de-assertion cycle. Signal <NUM> illustrates the latency of the reset. The latency can be any natural number.

A second plot <NUM> is illustrated and includes signals <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>. The signals <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> can be similar to the signals <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, respectively. The second plot <NUM> illustrates a reset that runs with a different latency, assertion cycle, and de-assertion cycle. The clock phase <NUM> illustrates how many clock cycles go by during the process of resetting. As illustrated, a reset signal <NUM> is received. For example, the reset signal can be received by a reset synchronizer. An inverted reset signal <NUM> is inverted relative to the clock phase <NUM>. The inverted reset signal <NUM> can be transmitted in response to the reset signal <NUM> being received. For example, the inverted reset signal <NUM> can be transmitted by a reset synchronizer. Signal <NUM> represents the reset signal being asserted over the reset network. As illustrated, the signal <NUM> is running on an inverted phase similar to inverted reset signal <NUM>. When the signal <NUM> has reached the components of the system, the reset is de-asserted. The de-assertion of the reset is illustrated by the signal <NUM>, which is a de-assertion cycle. Signal <NUM> illustrates the latency of the reset. In the illustrated plot, the latency is three clock cycles.

Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them.

Claim 1:
A method of resetting a number of functional components (<NUM>, <NUM>, <NUM>, <NUM>) in a computing device, the method comprising:
determining a number of cycles required to reset the functional components (<NUM>, <NUM>, <NUM>, <NUM>) based on a target voltage for the reset;
controlling a reset synchronizer (<NUM>, <NUM>, <NUM>) to run for the determined number of cycles;
wherein the reset synchronizer (<NUM>, <NUM>, <NUM>) controls a reset network (<NUM>) connected to the functional components (<NUM>, <NUM>, <NUM>, <NUM>); and
wherein the determined number of cycles at a first voltage is different than a determined number of cycles at a second voltage.