Patent Description:
A typical radio frequency (RF) system may perform a single RF function. For example, to perform multiple RF functions, several individual devices, systems, or circuits that each perform a single RF function may be used. These individual devices, systems, or circuits generally are implemented using a field programmable gate array (FPGA), which may be relatively expensive, have a relatively high power demand, and may have a lagging node geometry.

<CIT> discloses a software download configurable communication device. The device includes an architecture format referred to as reconfigurable logic. Reconfigurable logic refers to a real-time operating system (RTOS) where the outside source controls the type of state machines that control the dataflow process (i.e. control flow process). With reconfigurable logic, stored-instruction engines rely on shared buses for the transfer of data and instructions. Stored program instructions are used to run on an instruction decoder and controller. In another architecture, a hardware kernel plane provides the capability of reconfigurability for a range of protocols in an application, or within a range of applications. Additionally, the hardware kernel plane is modular, and thus may be designed to operate in groups.

<CIT>is directed to a system for developing an application specific integrated circuit (ASIC). A hardware description, for example, a second hardware description, may be generated and may include modification of a first hardware description to optimize the ASIC. The ASIC may be created or configured and may implement the function of a software program. Configuring or creating the ASIC may include implementing the second hardware description (or the final hardware configuration/plurality of second hardware configurations) on the ASIC. For example, where the hardware description for configuring the ASIC includes a state machine, configuring the ASIC may include implementing the state machine. Furthermore, configuring the ASIC may include implementing one or more portions of the first hardware description on the ASIC.

Document <CIT> discloses software for designing, modelling or performing digital signal processing that comprises a virtual machine layer optimized for communications DSP. The virtual machine layer allows low MIPS, complex code to interface with high MIPS processes by using APIs presented by the virtual machine layer. The present invention enables software to be written for the virtual machine rather than a specific DSP, decoupling engineers from the architecture constraints of DSPs from any one source of manufacture.

Document <CIT> discloses a processing system comprising a processor, memory and RCA module. RCA module may be a reconfigurable system comprising a combination of hardware and software that may be configured to execute different types of applications. RCA module may comprise multiple execution units used to perform complex calculations. The results generated by one execution unit may be used as input to other execution units, stored in memory, or sent to another processing system. Calculations can be divided among hardware elements, such that different parts of a calculation are assigned to the execution units upon which they are most efficiently carried out. For example, the physical layer processing performed by many wireless and wired communications systems often involves a combination of numerically intensive computations and somewhat less intensive, but more general-purpose, computations. RCA module may be configured to perform various types of parallel processing techniques. The configuration of RCA module may be modified by issued by a user, application, device, and so forth. The system may comprise one or more analog RF front end devices. For transmissions from wireless nodes <NUM> and/or <NUM>, AFE <NUM> may convert digitized baseband samples to RF. Similarly, for received RF signals, AFE <NUM> may convert the RF band of interest to a digitized baseband.

A radio frequency (RF) system may include an RF transceiver and a baseband engine, application specific integrated circuit (ASIC) coupled to the RF transceiver and configured to perform a given baseband engine operation from among a plurality of different baseband engine operations. The baseband engine ASIC may include a memory and a state machine coupled thereto and configured to store a respective set of programming instructions for each of the plurality of different baseband engine operations and to permit selection of the given set of programming instructions. The baseband engine ASIC may also include a programmable processing circuit coupled to the memory and the state machine and configured to perform a plurality of butterfly computations responsive to the given set of programming instructions.

The programmable processing circuit may be configured to operate an application programming interface (API) to permit selection of the given set of programming instructions. The plurality of butterfly computations may include a plurality of fast-Fourier transform (FFT) computations, for example.

The plurality of butterfly computations may include a plurality of inverse fast-Fourier transform (IFFT) computations. The plurality of butterfly computations may include a plurality of fast-Hadamard transform (FHT) computations, for example.

The plurality of butterfly computations may include a plurality of Viterbi decoding computations, for example. The plurality of butterfly computations may include a plurality of discrete cosine transform (DCT) computations.

The RF system may include a channelization circuit between the RF transceiver and the baseband engine ASIC. The RF system may include a sample rate conversion circuit between the RF transceiver and the baseband engine ASIC, for example.

The RF system may include an analog-to-digital converter (ADC) coupled between the RF transceiver and the baseband engine ASIC. The RF system may include a digital-to-analog converter (DAC) coupled between the RF transceiver and the baseband engine ASIC, for example.

A method aspect is directed to a method of performing a given baseband engine operation from among a plurality of different baseband engine operations. The method may include operating a memory and state machine of a baseband engine, application specific integrated circuit (ASIC) to permit selection of the given set of programming instructions from among respective sets of programming instructions stored in the memory for each of a plurality of different baseband engine operations. The method may further include operating a programmable processing circuit of the baseband engine ASIC to perform a plurality of butterfly computations responsive to the given set of programming instructions.

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in alternative embodiments.

Referring initially to <FIG>, a radio frequency (RF) system <NUM> includes an RF transceiver <NUM>. The RF transceiver <NUM> may be for use in a radar system, communications system, or other RF system. In other words, the RF transceiver <NUM> may be operable across a range of desired frequencies. The RF system <NUM> also includes a baseband engine, application specific integrated circuit (ASIC) <NUM>. The baseband engine ASIC <NUM> is coupled to the RF transceiver <NUM> and performs a given baseband engine operation from among different baseband engine operations.

The baseband engine ASIC <NUM> includes a memory <NUM> and a state machine <NUM> coupled to the memory. A programmable processing circuit <NUM> is also coupled to the memory <NUM> and the state machine <NUM>.

A respective set of programming instructions are stored in the memory <NUM> for each of the different baseband engine operations. For example, the different operations may include radar operations (e.g., multi-function array) and communications operations. The baseband engine ASIC <NUM> also permits selection of the given set of the programming instructions. More particularly, the programmable processing circuit <NUM> may operate an application programming interface (API) to permit selection of the given set of programming instructions. For example, a user may operate software via a display and an input device to select the given set of programming instructions. Variables may also be stored in the memory <NUM>, for example, for affine sets of instantiations (e.g., node operations, path multipliers, etc.). The variable may be included with or part of the given set of programming instructions.

The programmable processing circuit <NUM> also performs butterfly computations responsive to the given set of programming instructions. As will be understood by those skilled in the art, in the context of fast Fourier transform (FFT) algorithms, butterfly computations are the portion of the FFT computation that combines the results of smaller discrete Fourier transforms (DFTs) into a larger DFT, or vice versa (breaking a larger DFT up into sub-transforms). The name "butterfly" comes from the shape of the data-flow diagram, for example, in the radix-<NUM> case.

For example, branch weights may be provided as inputs to a butterfly structure while control is provided by node functionalities, as will be appreciated by those skilled in the art. An exemplary butterfly structure is illustrated in <FIG>, whereby the Xk are branch kth inputs, W represents a coefficient or weight, and Xk+<NUM> are outputs. The butterfly computations may include fast-Fourier transform (FFT) computations (<FIG>). In particular, a multidimensional DFT transforms an array x(n) with a d-dimensional vector of indices n = (n<NUM>,. , nd) by a set of d nested summations (over nj = <NUM>. Nj-<NUM>) for each j, where the division n/N, is performed element-wise (<FIG>). Equivalently, it is the composition of a sequence of d sets of one-dimensional DFTs, performed along one dimension at a time (in any order).

In other embodiments, the butterfly computations may also include inverse fast-Fourier transform computations (IFFT) as will be appreciated by those skilled in the art.

The butterfly computations may also include fast-Hadamard transform (FHT) computations (<FIG>). Those skilled in the art will recognize that an FHT is a Walsh-Hadamard transform of discrete, periodic data similar to the DFT.

The butterfly computations may also include discrete cosine transform (DCT) computations (<FIG>). A DCT expresses a finite sequence of data points in terms of a sum of cosine functions oscillating at different frequencies (<FIG>).

Referring now additionally to <FIG> and <FIG> the butterfly computations may also include Viterbi decoding computations. A Viterbi decoder, for example, uses the Viterbi algorithm for decoding a bitstream that has been encoded using a convolutional code or trellis code. The Viterbi algorithm is a dynamic programming algorithm for finding the most likely sequence of hidden states-called the Viterbi path-that results in a sequence of observed events, especially in the context of Markov information sources and hidden Markov models (HMM) (<FIG>).

As shown in <FIG>, an exemplary RF system includes programmable processing circuitry for performing Viterbi decoding computations, and includes a code rate look up table <NUM> used with or provided to an associated state machine <NUM>. Hard symbols may be provided to a butterfly structure <NUM>, the output of which may be provided to a traceback unit <NUM> and a survivor path memory <NUM>. The survivor path memory <NUM> provides input to the traceback unit <NUM>, which in turn provides soft symbols as an output.

Referring again to <FIG>, a channelization circuit <NUM> and a sample rate conversion circuit <NUM> are coupled between the RF transceiver <NUM> and the baseband engine ASIC <NUM>. An analog-to-digital converter (ADC) <NUM> and digital-to-analog converter (DAC) <NUM> are also coupled between the RF transceiver <NUM> and the baseband engine ASIC <NUM>. More particularly, the DAC <NUM> is coupled between the channelization circuit <NUM> or the sample rate conversion circuit <NUM> and the RF transceiver <NUM>, and provides input to the RF transceiver. The ADC <NUM> is also coupled between the channelization circuit <NUM> or the sample rate conversion circuit <NUM> and the RF transceiver <NUM>, and provides accepts output from the RF transceiver.

A method aspect is directed to a method of performing a given baseband engine operation from among a plurality of different baseband engine operations. The method may include operating a memory <NUM> and state machine <NUM> of a baseband engine ASIC <NUM> to permit selection of the given set of programming instructions from among respective sets of programming instructions stored in the memory for each of a plurality of different baseband engine operations. The method may further include operating a programmable processing circuit <NUM> of the baseband engine ASIC <NUM> to perform a plurality of butterfly computations responsive to the given set of programming instructions.

The method may also include operating an application programming interface (API) using the programmable processing circuit <NUM> to permit selection of the given set of programming instructions. The plurality of butterfly computations may comprise a plurality of fast-Fourier transform (FFT) computations, a plurality of inverse fast-Fourier transform (IFFT) computations, a plurality of fast-Hadamard transform (FHT) computations, a plurality of Viterbi decoding computations, or a plurality of discrete cosine transform (DCT) computations.

The method may also include operating a channelization circuit <NUM> between a radio frequency (RF) transceiver <NUM> and the baseband engine ASIC <NUM>, and operating a sample rate conversion circuit <NUM> between RF transceiver and the baseband engine ASIC.

Referring now to <FIG>, in another embodiment, the programmable processing circuit <NUM>' may perform, for example, instead of butterfly computations, block coding computations responsive to the given set of programming instructions. Those skilled in the art will appreciate that block codes are a large and important family of error-correcting codes that encode data in blocks.

The block coding computations may include cyclic code computations. A cyclic code is a block code, where the circular shifts of each codeword gives another word that belongs to the code. A cyclic code is an error-correcting code that has algebraic properties that are convenient for efficient error detection and correction. Accordingly, the cyclic code computations may include n-bit cyclic redundancy check (CRC) computations, whereby n may be between <NUM> and <NUM>, for example. Of course, n may be another number outside this range. A CRC code is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. Blocks of data entering these systems get a short checksum value attached, based on the remainder of a polynomial division of their contents. On retrieval, the calculation is repeated and, in the event the checksum values do not match, corrective action can be taken against data corruption. An architecture for generating a CRC may include an input that receives a polynomial (i.e., n-bit polynomial) and is controlled by way of exclusive OR-ing of bits form the generating polynomial (<FIG>).

While the programmable processing circuit <NUM>' performs block coding computations, for example, instead of butterfly computations, those skilled in the art will recognize that the programmable processing circuit of the baseband engine ASIC <NUM>' may perform either butterfly or block coding computations depending on the selected set of programming instructions. Elements illustrated but not specifically described are similar to those described above with respect to <FIG>.

As will be appreciated by those skilled in the art, by being programmable or reprogrammable for different operations the RF system <NUM>, <NUM>' may provide increased RF functionality within a smaller space, using less power, and with a reduced amount of weight. In contrast, conventional RF systems may have discrete circuitry or individual devices for each function, and reusing or reprogramming these individual devices or circuits may not be possible, or, in some cases where reprogramming may be possible, reuse or reprogramming may be relatively costly and/or complex for implementation. In other words, these relatively complex RF systems with individual or discrete device for each function are generally not scalable nor flexible to allow for upgrade or feature addition.

A method aspect is directed to a method of performing a given baseband engine operation from among a plurality of different baseband engine operations. The method may include operating a memory <NUM>' and state machine <NUM>' of a baseband engine, application specific integrated circuit (ASIC) <NUM>' to permit selection of the given set of programming instructions from among respective sets of programming instructions stored in the memory for each of a plurality of different baseband engine operations. The method may also include operating a programmable processing circuit <NUM>' of the baseband engine ASIC <NUM>' to perform a plurality of block coding computations responsive to the given set of programming instructions.

The method may also include operating an application programming interface (API) using the programmable processing circuit <NUM>' to permit selection of the given set of programming instructions. For example, the plurality of block coding computations may comprise a plurality of cyclic code computations, such as n-bit cyclic redundancy check (CRC) computations, wherein n is between <NUM> and <NUM>. Of course, n may be another number, for example, an arbitrary number.

The method may also include operating a channelization circuit <NUM>' between a radio frequency (RF) transceiver <NUM>' and the baseband engine ASIC <NUM>', and operating a sample rate conversion circuit <NUM>' between the RF transceiver and the baseband engine ASIC.

Claim 1:
A radio frequency, hereinafter RF, system (<NUM>) comprising:
an RF transceiver (<NUM>); and
a baseband engine, application specific integrated circuit, hereinafter ASIC, (<NUM>) coupled to the RF transceiver (<NUM>) and configured to perform a given baseband engine operation from among a plurality of different baseband engine operations, said baseband engine ASIC (<NUM>) comprising:
a memory (<NUM>) and a state machine (<NUM>) coupled thereto and configured to store a respective set of programming instructions for each of the plurality of different baseband engine operations and to permit selection of the given set of programming instructions,
a programmable processing circuit (<NUM>) coupled to said memory (<NUM>) and said state machine (<NUM>) and configured to perform a plurality of butterfly computations responsive to the given set of programming instructions
characterized in that the programmable processing circuit (<NUM>) adapted to perform either butterfly or block coding computations depending on the selected set of programming instructions, wherein said programming instructions include variables for affine sets of instantiations stored in the memory (<NUM>).