Patent Description:
Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of the charge carriers. For example, <CIT> discloses strained material layers of silicon, silicon-germanium, and relaxed silicon and also including impurity-free zones that would otherwise cause performance degradation. The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices. Published <CIT> discloses a CMOS inverter also based upon similar strained silicon technology.

<CIT>discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.

discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fractional or binary or a binary compound semiconductor layer, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.

discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Along these lines, <CIT>discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionally present in the silicon lattice at a percentage that places the channel layer under tensile stress.

<CIT>discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO2/Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.

An article entitled "<NPL> discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen. The Si/O superlattice is disclosed as useful in a silicon quantum and light-emitting devices. In particular, a green electroluminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density. One SAS structure included a <NUM> thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon. An article to <NPL>) further discusses the light emitting SAS structures of Tsu.

discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorous, antimony, arsenic or hydrogen to thereby reduce current flowing vertically through the lattice more than four orders of magnitude. The insulating layer/barrier layer allows for low defect epitaxial silicon to be deposited next to the insulating layer.

Published Great Britain Patent Application <CIT>. discloses that principles of Aperiodic Photonic Band-Gap (APBG) structures may be adapted for electronic bandgap engineering. In particular, the application discloses that material parameters, for example, the location of band minima, effective mass, etc., can be tailored to yield new aperiodic materials with desirable band-structure characteristics. Other parameters, such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material.

Furthermore, <CIT>. discloses a method for producing an insulating or barrier layer for semiconductor devices which includes depositing a layer of silicon and at least one additional element on the silicon substrate whereby the deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on the deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite.

<CIT> discloses a method for making semiconductor devices. The method includes forming a plurality of waveguides on a substrate, and forming a superlattice overlying the substrate and waveguides.

<CIT> discloses a method for making a semiconductor device that may include forming an insulating layer on a substrate, and forming a semiconductor layer on the insulating layer on a side thereof opposite the substrate.

<CIT> discloses a semiconductor device that may include a substrate including a first Group IV semiconductor having a recess therein, an active layer comprising a Group III-V semiconductor within the recess, and a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor.

Despite the existence of such approaches, further enhancements may be desirable for using advanced semiconductor materials and processing techniques to achieve improved performance in semiconductor devices.

According to independent claim <NUM> of the invention, a radio frequency (RF) semiconductor device includes a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate comprising a highly doped semiconductor layer and a conductive superlattice above the highly doped semiconductor layer. The conductive superlattice includes a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The RF semiconductor device further includes a body above the RF ground plane layer, spaced apart source and drain regions adjacent the body and defining a channel region in the body, and a gate overlying the channel region.

In an example embodiment, the RF semiconductor device may be an RF switch. The RF semiconductor device may also include a body contact coupled to the body and the RF ground plane layer. By way of example, the body contact may include first and second body contact portions adjacent opposite ends of the channel region.

In accordance with an example implementation, the RF ground plane may have a thickness in a range of <NUM>-<NUM>. Furthermore, the doped base semiconductor portions may have a dopant concentration of at least 5x10<NUM>cm-<NUM>, for example. The gate may include a gate insulator over the channel region, and a gate electrode over the gate insulator.

Also by way of example, the doped base semiconductor monolayers may comprise silicon, and the non-semiconductor monolayers may comprise oxygen. The semiconductor-on-insulator substrate may comprise a silicon-on-insulator (SOI) substrate, for example.

According to independent claim <NUM> of the invention, there is provided a method for making a radio frequency (RF) semiconductor device that includes forming an RF ground plane layer on a semiconductor-on-insulator substrate and comprising a highly doped semiconductor layer and a conductive superlattice above the highly doped semiconductor layer. The conductive superlattice includes a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The method further includes forming a body above the RF ground plane layer, forming spaced apart source and drain regions adjacent the body and defining a channel region in the body, and forming a gate overlying the channel region.

In an example embodiment, the RF semiconductor device may comprise an RF switch. The method may further include forming a body contact coupled to the body and the RF ground plane layer. More particularly, the body contact may include first and second body contact portions adjacent opposite ends of the channel region.

By way of example, the RF ground plane may have a thickness in a range of <NUM>-<NUM>. Also by way of example, the doped base semiconductor portions may have a dopant concentration of at least 5x10<NUM>cm-<NUM>. Forming the gate may include forming a gate insulator over the channel region, and forming a gate electrode over the gate insulator.

In an example implementation, the doped base semiconductor monolayers may comprise silicon, and the non-semiconductor monolayers may comprise oxygen. Moreover, the semiconductor-on-insulator substrate may comprise a silicon-on-insulator (SOI) substrate, for example.

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which the example embodiments are shown. The embodiments may, however, be implemented in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in different embodiments.

Generally speaking, the present disclosure relates to radio frequency (RF) semiconductor-on-insulator (SOI) devices having an enhanced semiconductor superlattice therein to provide performance enhancement characteristics. The enhanced semiconductor superlattice may also be referred to as an "MST" layer or "MST technology" in this disclosure.

More particularly, the MST technology relates to advanced semiconductor materials such as the superlattice <NUM> described further below. Applicant theorizes, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicants use a "conductivity reciprocal effective mass tensor", <MAT> and <MAT> for electrons and holes respectively, defined as: <MAT> for electrons and: <MAT> for holes, where f is the Fermi-Dirac distribution, EF is the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the nth energy band, the indices i and j refer to Cartesian coordinates x, y and z, the integrals are taken over the Brillouin zone (B. ), and the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.

Applicant's definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor. Again Applicant theorizes without wishing to be bound thereto that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport. The inverse of the appropriate tensor element is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.

Applicant has identified improved materials or structures for use in semiconductor devices. More specifically, Applicant has identified materials or structures having energy band structures for which the appropriate conductivity effective masses for electrons and/or holes are substantially less than the corresponding values for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.

Referring now to <FIG> and <FIG>, the materials or structures are in the form of a superlattice <NUM> whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition. The superlattice <NUM> includes a plurality of layer groups 45a-45n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view of <FIG>.

Each group of layers 45a-45n of the superlattice <NUM> illustratively includes a plurality of stacked base semiconductor monolayers <NUM> defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer <NUM> thereon. The energy band-modifying layers <NUM> are indicated by stippling in <FIG> for clarity of illustration.

The energy band-modifying layer <NUM> illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By "constrained within a crystal lattice of adjacent base semiconductor portions" it is meant that at least some semiconductor atoms from opposing base semiconductor portions 46a-46n are chemically bound together through the non-semiconductor monolayer <NUM> therebetween, as seen in <FIG>. Generally speaking, this configuration is made possible by controlling the amount of non-semiconductor material that is deposited on semiconductor portions 46a-46n through atomic layer deposition techniques so that not all (i.e., less than full or <NUM>% coverage) of the available semiconductor bonding sites are populated with bonds to non-semiconductor atoms, as will be discussed further below. Thus, as further monolayers <NUM> of semiconductor material are deposited on or over a non-semiconductor monolayer <NUM>, the newly deposited semiconductor atoms will populate the remaining vacant bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.

Applicant theorizes without wishing to be bound thereto that energy band-modifying layers <NUM> and adjacent base semiconductor portions 46a-46n cause the superlattice <NUM> to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The band modifying layers <NUM> may also cause the superlattice <NUM> to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.

Moreover, this superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice <NUM>. These properties may thus advantageously allow the superlattice <NUM> to provide an interface for high-K dielectrics which not only reduces diffusion of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.

It is also theorized that semiconductor devices including the superlattice <NUM> may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present. In some embodiments, and as a result of the band engineering achieved by the present invention, the superlattice <NUM> may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.

The superlattice <NUM> also illustratively includes a cap layer <NUM> on an upper layer group 45n. The cap layer <NUM> may comprise a plurality of base semiconductor monolayers <NUM>. The cap layer <NUM> may have between <NUM> to <NUM> monolayers of the base semiconductor, and, more preferably between <NUM> to <NUM> monolayers.

Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, the term Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

Each energy band-modifying layer <NUM> may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon and carbon-oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

It should be noted that the term monolayer is meant to include a single atomic layer and also a single molecular layer. It is also noted that the energy band-modifying layer <NUM> provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or <NUM>% coverage). For example, with particular reference to the atomic diagram of <FIG>, a <NUM>/<NUM> repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied in the illustrated example.

In other embodiments and/or with different materials this one-half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments.

Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice <NUM> in accordance with the invention may be readily adopted and implemented, as will be appreciated by those skilled in the art.

It is theorized without Applicant wishing to be bound thereto that for a superlattice, such as the Si/O superlattice, for example, that the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages. The <NUM>/<NUM> repeating structure shown in <FIG> and <FIG>, for Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction. For example, the calculated conductivity effective mass for electrons (isotropic for bulk silicon) is <NUM> and for the <NUM>/<NUM> SiO superlattice in the X direction it is <NUM> resulting in a ratio of <NUM>. Similarly, the calculation for holes yields values of <NUM> for bulk silicon and <NUM> for the <NUM>/<NUM> Si/O superlattice resulting in a ratio of <NUM>.

While such a directionally preferential feature may be desired in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons and holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.

The lower conductivity effective mass for the <NUM>/<NUM> Si/O embodiment of the superlattice <NUM> may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes. Of course, the superlattice <NUM> may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.

Indeed, referring now additionally to <FIG>, another embodiment of a superlattice <NUM>' in accordance with the invention having different properties is now described. In this embodiment, a repeating pattern of <NUM>/<NUM>/<NUM>/<NUM> is illustrated. More particularly, the lowest base semiconductor portion 46a' has three monolayers, and the second lowest base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice <NUM>'. The energy band-modifying layers <NUM>' may each include a single monolayer. For such a superlattice <NUM>' including Si/O, the enhancement of charge carrier mobility is independent of orientation in the plane of the layers. Those other elements of <FIG> not specifically mentioned are similar to those discussed above with reference to <FIG> and need no further discussion herein.

In some device embodiments, all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.

In <FIG>, band structures calculated using Density Functional Theory (DFT) are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Hence all bands above the gap may be shifted by an appropriate "scissors correction. " However the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light.

<FIG> shows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the <NUM>/<NUM> Si/O superlattice <NUM> shown in <FIG> (represented by dotted lines). The directions refer to the unit cell of the <NUM>/<NUM> Si/O structure and not to the conventional unit cell of Si, although the (<NUM>) direction in the figure does correspond to the (<NUM>) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum. The (<NUM>) and (<NUM>) directions in the figure correspond to the (<NUM>) and (-<NUM>) directions of the conventional Si unit cell. Those skilled in the art will appreciate that the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the <NUM>/<NUM> Si/O structure.

It can be seen that the conduction band minimum for the <NUM>/<NUM> Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (<NUM>) direction which we refer to as the Z point. One may also note the greater curvature of the conduction band minimum for the <NUM>/<NUM> Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.

<FIG> shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the <NUM>/<NUM> Si/O superlattice <NUM> (dotted lines). This figure illustrates the enhanced curvature of the valence band in the (<NUM>) direction.

<FIG> shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the <NUM>/<NUM>/<NUM>/<NUM> Si/O structure of the superlattice <NUM>' of <FIG> (dotted lines). Due to the symmetry of the <NUM>/<NUM>/<NUM>/<NUM> Si/O structure, the calculated band structures in the (<NUM>) and (<NUM>) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (<NUM>) stacking direction. Note that in the <NUM>/<NUM>/<NUM>/<NUM> Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.

Although increased curvature is an indication of reduced effective mass, the appropriate comparison and discrimination may be made via the conductivity reciprocal effective mass tensor calculation. This leads Applicant to further theorize that the <NUM>/<NUM>/<NUM>/<NUM> superlattice <NUM>' should be substantially direct bandgap. As will be understood by those skilled in the art, the appropriate matrix element for optical transition is another indicator of the distinction between direct and indirect bandgap behavior.

Referring now additionally to <FIG>, the above-described superlattice structures may advantageously be used to provide radio frequency (RF) semiconductor-on-insulator devices. By way of background, typical RF silicon-on-insulator (SOI) devices have a number of different breakdown mechanisms. NMOS RF-SOI switches may be quite wide (on the order of <NUM>) to handle sufficient current, and the thin silicon on buried oxide (BOX) architecture means that the body tie is placed at the edge of the width. Holes generated by impact ionization and otherwise have to traverse up to half of the width to reach the body contact. For short gate lengths and wide devices, the resistive path to the contact may be significant, causing a rise in body potential toward the middle of the device. If the potential rise is great enough, the body-source junction may be forward biased, and a parasitic n-p-n (source-body-drain) may be triggered, leading to a run-away source-drain current.

In an example embodiment, an RF semiconductor device <NUM> advantageously incorporates an MST layer, such as those described above, to advantageously provide for a more highly doped "ground plane" (GP) above the BOX, yet which is constrained to the lower portion of the silicon-on-BOX such that it does not cause a high threshold voltage (Vt) or otherwise impair the operation of the device. The RF-SOI device <NUM> illustratively includes a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate including a semiconductor (e.g., silicon) substrate layer <NUM>, a BOX layer <NUM> (e.g., SiO<NUM>), and a semiconductor (e.g., silicon) layer <NUM> on the BOX layer. A conductive superlattice <NUM> (such as the MST superlattice layers described further above) is above the semiconductor layer <NUM>. The conductive superlattice <NUM> and semiconductor layer <NUM> below the superlattice are highly doped to define the ground plane <NUM>. It should be noted that in some embodiments, portions of the body <NUM> directly above the superlattice <NUM> may also include ground plane dopant and define a portion of the ground plane <NUM>. Moreover, in the illustrated embodiment the superlattice <NUM> is selectively deposited in the ground plane <NUM> region, but in other embodiments a blanket superlattice deposition across the entire substrate <NUM> may be used, as will be discussed further below.

The RF semiconductor device <NUM> further illustratively includes a body <NUM> above the RF ground plane layer <NUM>, spaced apart source and drain regions <NUM>, <NUM> adjacent the body and defining a channel region <NUM> in the body, and a gate <NUM> overlying the channel region. The gate <NUM> illustratively includes a gate insulator <NUM> (e.g., SiO<NUM>) over the channel region <NUM>, and a gate electrode <NUM> (e.g., polysilicon) over the gate insulator.

An equivalent circuit diagram <NUM> for the RF semiconductor device <NUM> is shown in <FIG>. For the discussion and examples that follow, a SOI device with Si/O superlattices will be used, although those skilled in the art will appreciate that other materials may be used in different embodiments as discussed further above. Generally speaking, a thinner SOI layer <NUM> enables lower Coff due to lower Cds (∝ Tsoi). Yet, SOI thickness scaling is constrained by breakdown characteristics, as a thinner SOI layer <NUM> is more susceptible to hole accumulation to trigger a parasitic BJT effect. Accordingly, SOI layer thicknesses of current state-of-the art RF-SOI devices is typically in the <NUM>-<NUM> (final) range. Furthermore, due to the use of relatively thick gate oxides (tox=<NUM>) for Vdd=<NUM>. 5V, which is necessary to handle RF signals, gate length scaling in typical RF-SOI devices is generally around Lg=<NUM>.

Through simulation, Applicant has determined that a ground plane doping immediately above the BOX layer <NUM> in a range of <NUM>-<NUM> thickness and 5E17cm-<NUM>, and more preferably 1E18cm-<NUM>, doping (or above) may significantly improve the breakdown voltage of RF-SOI devices (e.g., by up to 1V for a 5V device). If other device characteristics are not impaired, this leads to a significant improvement in the key metric of Ron-BV, where Ron is the ON state resistance. It has also been verified through simulation that example RF-SOI devices incorporating an MST film may advantageously maintain or reduce the junction capacitance, and hence the Coff, thus improving another key metric, namely Ron-Coff versus BV.

More particularly, the superlattice <NUM> effectively forms the ground-plane doping layer, confining dopants (e.g., boron for an N channel device) at the interface between the BOX layer <NUM> and SOI layer <NUM>. Furthermore, the ground plane <NUM> also serves as a Vt adjustment doping layer. The illustrated structure also allows for scaling SOI to desirable thicknesses, e.g., down to <NUM> or less. In addition, the approach is also effective in gate length scaling as well, with simulations projecting desirable gate control for Lg=<NUM> devices.

Another consideration with conventional RF-SOI devices is body potential increase due to SOI body pinch-off. More particularly, typical SOI body pinches off at approximately <NUM> from the body contact, and holes may accumulate at the gate oxide interface due to a negative bias. As a result, the rest of the SOI body is depleted, and body potential may be raised due to the pinch off. Yet, the ground plane <NUM> of the device <NUM> advantageously improves breakdown voltage (BV) by accumulating and retaining dopant (e.g., boron) at the SOI/BOX interface, mitigating body potential increase by body resistance reduction. On the other hand, removal of boron from the SOI/BOX interface (counter-GP) degrades BV, as seen in the graph <NUM> of <FIG> illustrating breakdown characteristics for simulations of the illustrated configuration. The graph <NUM> of <FIG> shows the corresponding hole potential along the channel for counter-GP, uniform doping, and GP.

In an example technology computer-aided design (TCAD) simulation of the device <NUM>, the following parameters were used: gate length LG=<NUM>; thickness of the silicon between the BOX <NUM> and gate <NUM> TSOI=<NUM>; thickness of the ground plane <NUM> TGP=<NUM>; n-type dopant concentration of the ground plane NGP=<NUM>. 5E18/cm<NUM>; body <NUM> thickness TSSR=<NUM>; n-type dopant concentration in the channel Nch=1E16/cm<NUM>; n-type dopant concentration in the lightly-doped drain region NLDD=2E19/cm<NUM>; thickness of the lightly-doped drain region XJ=<NUM> (at 4E18/cm<NUM>); and an offset spacer = <NUM>. The projected electrical performance values from the simulation were as follows: RDSON=<NUM> ohm-um (IDLIN=<NUM> uA/um at VDS=<NUM>. 1V); IOFF = <NUM>. 8nA/um; VTLIN=<NUM>. 700V; and VTSAT=<NUM>. These results are shown in the graph <NUM> of <FIG>.

Generally speaking, MST layers may be used to advantageously maintain and/or create the highly doped ground plane <NUM> using various example approaches. In one example embodiment, the entire silicon-on-BOX region is fabricated to have p-doping of the desired ground plane specification (e.g., greater than approximately 1E18cm-<NUM>). MST deposition is then applied either to the whole starting substrate, or selectively to only the NMOS switch devices after an appropriate etch in those regions.

If regular undoped silicon epitaxy is applied to the substrate <NUM>, up-diffusion of the p-type dopant (typically boron) during epitaxy will occur into the whole thickness of the silicon layer <NUM> on the BOX layer <NUM>, and this diffusion will be further enhanced during the gate oxidation process (and any other thermal annealing steps) so that the silicon-on-BOX will be much more uniformly doped at the end of the process and the advantage of the GP doping will be lost. However, this may be advantageous for the creation of other NMOS and PMOS devices such as those required for CMOS low-noise amplifiers and other circuit elements, since the reduced p-type doping of the silicon-on-BOX may be more readily counter-doped to create the PMOS devices.

More particularly, the growth of MST layers will both trap the p-type dopant and inhibit up-diffusion, by absorbing silicon self-interstitials, which mediate diffusion for many dopants, including boron and phosphorus. Thus, where MST is applied, the ground plane doping will be held in place. If needed, the doping close to the BOX may also be enhanced by a subsequent implant. The MST layers will also serve to trap this implanted dopant. In the case where MST is applied in a blanket deposition across the whole wafer on a previously p-doped ground plane, Applicant speculates without wishing to be bound thereto that it will still be possible to create PMOS devices where required by counter-doping, since the MST layer will also strongly trap n-type dopants such as phosphorus.

In an example implementation, a starting silicon-on-insulator substrate with a silicon-on-BOX p-type doping (e.g., above 5E17) may be provided, along with MST layers (as described further above) in the silicon-on-BOX region such that the remainder of the silicon above the MST layers is substantially un-doped (and ><NUM> depth, for example).

In accordance with another example, a starting silicon-on-insulator substrate is provided where the desired ground plane p-type doping (e.g., above 5E17 cm-<NUM>) is implanted. MST layers (as described further above) are also provided in the silicon-on-BOX region such that the remainder of the silicon above the MST layers is substantially un-doped.

Turning to <FIG> and <FIG>, an example NMOS RF switch device <NUM> and associated fabrication steps are now described in greater detail. The cross-sectional views shown in <FIG> are taken along the line A-A of <FIG>. The device <NUM> illustratively includes a body contact with first and second body contact portions 180a, 180b at opposing edges of the device along its width. For an NMOS configuration, the device <NUM> may include a ground plane <NUM> created from the starting substrate <NUM> with p-type doping above the BOX layer <NUM> greater than, e.g., 5E17cm-<NUM> (and, more preferably, greater than 1E18 cm-<NUM>). However, in some embodiments a PMOS device may also be created using the substrate by counter-doping the p-type ground plane <NUM> by implantation into and below the MST region, as will be appreciated by those skilled in the art.

Fabrication of the device <NUM> begins with the growth of a screen oxide <NUM> on the starting SOI substrate or wafer <NUM> (<FIG>), which illustratively includes the silicon layer or substrate <NUM>, BOX layer <NUM>, and SOI layer <NUM>. A photoresist (PR) mask <NUM> is selectively formed over the screen oxide <NUM> exposing the area where the ground plane <NUM> is to be formed, and a ground plane implant is then performed (<FIG>). In this example, the NMOS with the ground plane <NUM> is an RF switch. That is, a gate 171a of the RF switch controls charge carrier flow through the channel region responsive to an RF switching control signal. The mask <NUM> is removed, and then a second PR mask <NUM> is selectively deposited to expose the area where a Vt adjustment implant <NUM> is to be formed in another NMOS RF device as shown in <FIG>. By way of example, P-type doping for the Vt implant <NUM> may be in a range of about E17cm-<NUM>.

After removal of the second PR mask <NUM> and screen oxide <NUM> (<FIG>), a blanket MST growth is performed to define a superlattice <NUM>, followed by the epitaxial growth of a silicon cap layer <NUM> (<FIG>). A shallow trench isolation (STI) module is performed to define STI regions (e.g., SiO2) between the different NMOS devices, followed by a source/drain module to define sources 167a, 167b and drains 168a, 168b in both of the transistors and a gate module to define gates 171a, 171b (<FIG>).

Another example fabrication approach is now described with reference to <FIG>. The finished device will appear the same from a top plan view as the device <NUM> shown in <FIG>, and the cross-sectional views shown in FIGS. 12A-<NUM> are similarly taken along the line A-A of <FIG>. From the starting SOI wafer <NUM>' (<FIG>), the SOI layer <NUM>' is thinned to the desired thickness tSOI by oxidation or wet etching (<FIG>), for example. Generally speaking, the value of tSOI should be thin enough to allow for the ground plane formation, and may be in a range of <NUM>-<NUM> in one example implementation. A blanket MST layer deposition is performed to form the superlattice layer <NUM>', followed by silicon cap layer <NUM>' formation (<FIG>). By way of example, a thickness tMST of the superlattice <NUM>' may be in a range of <NUM>-<NUM>, while a thickness of the silicon cap layer <NUM>' may be in a range of <NUM>-<NUM>, although other thicknesses may be used in different embodiments.

Following an STI module (<FIG>), a first PR mask <NUM>' is formed and the ground plane implant is performed (<FIG>), as similarly described above. Thereafter, the first PR mask <NUM>' is removed, the second PR mask <NUM>' is formed, followed by the Vt implant <NUM>', as discussed further above. It should be noted that, in some embodiments, the order in which the GP implant <NUM>' and the Vt implant <NUM>' are formed may be reversed, if desired. Device fabrication concludes with a source/drain module defining sources 167a', 167b' and drains 168a' and 168b', and a gate module defining gates 171a' and 171b'. Here again, the device with ground plane <NUM>' is an RF switch, although the above-described ground plane configurations may be used in other RF devices as well.

Secondary Ion Mass Spectrometer (SIMS) was used to confirm the viability of ground plane and Vt implant doping by locating an MST film near a BOX layer, as discussed above, and the results are shown in the graph <NUM> of <FIG>. In the example implementation, the SOI layer was thinned down to <NUM>, and a ground plane boron implantation of 10keV at <NUM>. 0E13 was performed before the MST film deposition.

Moreover, SIMS was also used to confirm the viability of ground plane and Vt implant doping after MST film deposition, and the results are shown in the graphs <NUM>, <NUM> of <FIG> and <FIG>. In particular, the graph <NUM> corresponds to a silicon epi control performed on an SOI layer, while the graph <NUM> corresponds to an MST film on an SOI layer. Here again, the SOI layer was thinned to <NUM>, and a boron implantation of 24keV at <NUM>. 0E13 was performed for the ground plane implant. Furthermore, a rapid thermal anneal (RTA) was performed at <NUM> for <NUM>, followed by a full thermal cycle (well RTA + gate oxide (GOX) + poly reox + LDD RTA + source/drain (SD) RTA). In the control epi silicon, boron is lost after a light RTA, and then further reduced after full thermal cycle for CMOS. However, with the MST film present, the structure provides enhanced boron retention at the BOX interface after the initial RTA and subsequent full thermal cycle, as shown.

More particularly, the MST film advantageously provides for the retention of a relatively high dopant concentration in the ground plane layer which, in turn, provides faster RF device switching, lower on resistance and desired breakdown performance. The above-described processes also permit adjustment of the Vt of the other RF devices having a lower dopant concentration than the RF switching devices, as will be appreciated by those skilled in the art.

Further details regarding the dopant retention capabilities of MST films may be found in <CIT>. , both of which are assigned to the present Applicant.

Claim 1:
A radio frequency, RF, semiconductor device (<NUM>) comprising:
a semiconductor-on-insulator substrate (<NUM>);
an RF ground plane layer (<NUM>) on the semiconductor-on-insulator substrate comprising a highly doped semiconductor layer (<NUM>) and a conductive superlattice (<NUM>) above the highly doped semiconductor layer, the conductive superlattice comprising a plurality of stacked groups of layers (45a-45n), each group of layers comprising a plurality of stacked doped base semiconductor monolayers (<NUM>) defining a doped base semiconductor portion (46a-46n), and at least one non-semiconductor monolayer (<NUM>) constrained within a crystal lattice of adjacent doped base semiconductor portions;
a body (<NUM>) above the RF ground plane layer;
spaced apart source and drain regions (<NUM>, <NUM>) adjacent the body and defining a channel region in the body; and
a gate (<NUM>) overlying the channel region.