Patent Description:
Some semiconductor devices include a transistor with a gate in a trench in the semiconductor substrate, and a shield in the trench below the gate. Such a configuration is common in vertical metal oxide semiconductor (MOS) transistors. A portion of the shield extends toward a top of the trench to provide an area for an electrical connection to the shield. Forming the shield and the gate to be electrically isolated from each other has been difficult to achieve in production.

Growing a single layer of a lateral insulator (e.g., gate oxide) directly on the shield (e.g., polysilicon shield) is often insufficient in some designs to provide sufficient gate voltage isolation. As a result, high gate leakage current is observed due to the thin and non-uniform lateral insulator grown on top of the shield. A low level of gate leakage current is generally a design characteristic for semiconductor devices such MOS transistors.

Accordingly, what is needed is a lateral insulator for a semiconductor device, and related method of forming the same, that facilitates low gate leakage current between the gate and shield of the semiconductor device.

In the European Search Report the following documents have been cited: <CIT> relates to a manufacturing method for a trench gate MOSFET with a shield gate; <CIT> discloses a trench-gate semiconductor device; <CIT> relates to a trench MOSFET with a shielded electrode and an avalanche enhancement region; <CIT> discloses a method and structure for a shielded gate trench FET.

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by advantageous examples of the present disclosure which includes methods of forming a semiconductor device according to claim <NUM>. The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated that the specific examples disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. The scope of the present invention is set forth in the appended claims.

For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:.

The figures are drawn to clearly illustrate the relevant aspects of the preferred examples and are not necessarily drawn to scale.

The making and using of the examples are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific examples discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

The present disclosure will be described with respect to examples in a specific context, namely, a lateral insulator for a semiconductor device, and methods of forming the same. The principles of the present disclosure may be applied to all types of semiconductor devices that would benefit from electrical isolation between layers therein.

Referring initially to <FIG>, illustrated is a cross-sectional view of an example semiconductor device <NUM>, useful for understanding the present invention.

The semiconductor device <NUM> includes a substrate <NUM> having a top surface <NUM> and a bottom surface <NUM>, located opposite from the top surface <NUM>. The substrate <NUM> includes a semiconductor material <NUM> such as silicon. The semiconductor material <NUM> may extend from the top surface <NUM> to the bottom surface <NUM>, as depicted in <FIG>. The substrate <NUM> has one or more trenches <NUM> extending from the top surface <NUM> into the semiconductor material <NUM>. References in the singular tense include the plural, and vice versa, unless otherwise noted. The trenches <NUM> may optionally be connected at a point not shown in <FIG> to provide a single trench <NUM>. The semiconductor material <NUM> extends to the trenches <NUM>. The trenches <NUM> may be <NUM> to <NUM> micrometers (µm) wide, for example, and may have ratios of depth to width, referred to as aspect ratios, of <NUM>:<NUM> to <NUM>:<NUM>, for example.

The semiconductor device <NUM> includes an MOS transistor <NUM>. The MOS transistor <NUM> includes a shield (that can be a polysilicon shield) <NUM> disposed in the trenches <NUM>. The shield <NUM> is electrically conductive, and may include, for example, polycrystalline silicon, sometimes referred to as polysilicon. The polycrystalline silicon may be doped during deposition, or may be implanted with dopants after deposition, to reduce an electrical resistivity of the shield <NUM>. The shield <NUM> is separated from the semiconductor material <NUM> by a shield liner <NUM> which is electrically non-conductive. In this example, the shield liner <NUM> may include a first liner <NUM> (e.g., a first dielectric liner) of thermal silicon dioxide, contacting the semiconductor material <NUM>, and a second liner (e.g., a second dielectric liner) <NUM> of a deposited dielectric material, contacting the first liner <NUM>. The thermal silicon dioxide in the first liner <NUM> may be characterized by a stoichiometric composition of silicon dioxide and a hydrogen content less than five atomic percent. The first liner <NUM> may have a thickness of <NUM> to <NUM> nanometers (nm) in the trenches <NUM>, for example. The first liner <NUM> may optionally extend over the top surface <NUM> of the substrate <NUM>, as indicated in <FIG>.

The second liner <NUM> may include silicon dioxide, and may have an etch rate, in aqueous buffered hydrofluoric acid, that is at least twice an etch rate, in the same aqueous buffered hydrofluoric acid, of the first liner <NUM>. The shield liner <NUM> may vary in thickness, having a higher thickness proximate to a bottom of the shield <NUM> than proximate to a top of the shield <NUM>. By way of example, the shield liner <NUM> may have a thickness of <NUM> to <NUM> proximate to the bottom of the shield <NUM>, and may have a thickness of <NUM> to <NUM> proximate to the top of the shield <NUM>. Having a varying thickness of the shield liner <NUM> may advantageously reduce an electric field in the semiconductor material <NUM> between the trenches <NUM> during operation of the MOS transistor <NUM>. In this case, the term "proximate to" is understood in this context to refer to a vertical distance that is less than a lateral width of the trenches <NUM>. The terms "lateral" and "laterally" refer to a direction parallel to the top surface <NUM> of the substrate <NUM>. The terms "vertical" and "vertically" refer to a direction perpendicular to the top surface <NUM>.

The MOS transistor <NUM> includes a gate <NUM> in the trenches <NUM>. The shield <NUM> extends under the gate <NUM> in the trenches <NUM>. The gate <NUM> may include polycrystalline silicon, for example, with appropriate dopants to attain a desired threshold potential during operation of the MOS transistor <NUM>. A gate bottom surface <NUM> of the gate <NUM> is separated from the shield <NUM> by a lateral insulator <NUM>. The lateral insulator <NUM> may include silicon dioxide, for example. The gate <NUM> extends to proximate a top of the trenches <NUM>, that is, proximate to the top surface <NUM> of the substrate <NUM>. Proximate to the top surface <NUM>, in this example, is understood to mean a vertical distance between a top of the gate <NUM> and the top surface <NUM> is less than a lateral width of one of the trenches <NUM>. The gate <NUM> is separated from the semiconductor material <NUM> by a gate dielectric layer <NUM>, which contacts the gate <NUM> and the semiconductor material <NUM>.

One or more contact portions <NUM> of the shield <NUM> extend toward the top of that trench <NUM>, that is, toward the top surface <NUM>. The contact portions <NUM> of the shield <NUM> may be located, for example, at ends <NUM> of the trenches <NUM>. The contact portion <NUM> of the shield <NUM> has an angled surface <NUM> adjacent to the gate <NUM> that extends from below the gate bottom surface <NUM> to proximate to the top of the trench <NUM>. A plane of the angled surface <NUM> intersects the top surface <NUM> of the substrate <NUM> at an angle of <NUM> degrees to <NUM> degrees, with <NUM> degrees being perpendicular to the top surface <NUM>. The angled surface <NUM> of the contact portion <NUM> of the shield <NUM> is separated from the gate <NUM> by a shield isolation layer <NUM>, which is electrically non-conductive. The shield isolation layer <NUM> contacts the gate <NUM> and the angled surface <NUM> of the contact portion <NUM> of the shield <NUM>. The shield isolation layer <NUM> may extend laterally between the gate bottom surface <NUM> and the shield <NUM> for a distance sufficient to provide complete coverage of the angled surface <NUM> of the contact portion <NUM> of the shield <NUM>, but does not extend a length of each of the trenches <NUM>.

By way of example, the shield isolation layer <NUM> may extend laterally between the gate bottom surface <NUM> and the shield <NUM> for one to five µm. The shield isolation layer <NUM> may include silicon dioxide, with a hydrogen content less than <NUM> atomic percent. The shield isolation layer <NUM> may extend over the top surface <NUM> of the substrate <NUM>, as shown in <FIG>. The shield isolation layer <NUM> may be <NUM> to <NUM> thick, for example. The shield isolation layer <NUM> may advantageously reduce leakage current between the gate <NUM> and the contact portion <NUM> of the shield <NUM> during operation of the MOS transistor <NUM>, compared to relying on an extension of the gate dielectric layer <NUM> to isolate the gate <NUM> from the contact portion <NUM> of the shield <NUM>.

The shield isolation layer <NUM> may extend onto a top dielectric layer <NUM>. The top dielectric layer <NUM> may include silicon dioxide, and may be <NUM> to one µm thick, for example. An edge of the top dielectric layer <NUM> adjacent to the contact portion <NUM> of the shield <NUM> may be tapered, as depicted in <FIG>. Contacts <NUM> may extend through the top dielectric layer <NUM> to provide electrical connections to the contact portion <NUM> of the shield <NUM>.

The MOS transistor <NUM> of this example includes a source <NUM> in the semiconductor material <NUM>, contacting the gate dielectric layer <NUM>. The source <NUM> has a first conductivity type, for example, n-type. The MOS transistor <NUM> of this example includes a body <NUM> in the semiconductor material <NUM>, contacting the gate dielectric layer <NUM> and the source <NUM>. The body <NUM> has a second conductivity type, opposite from the first conductivity type; in this example, the body <NUM> may be p-type, as indicated in <FIG>. The MOS transistor <NUM> of this example includes a drain contact region <NUM> in the semiconductor material <NUM> below the trenches <NUM>, which may be formed as a heavily-doped substrate that is partially removed by backgrinding after forming the other components of the MOS transistor <NUM>. The drain contact region <NUM> has the first conductivity type, which is n-type in this example, as indicated in <FIG>, and thus may be a heavily-doped n+ layer. A metal layer (not shown) may be formed on the drain contact region <NUM> for electrical contact. The semiconductor material <NUM> between the body <NUM> and the drain contact region <NUM> may have the first conductivity type, n-type in this example, and may provide a drain drift region for the MOS transistor <NUM>.

Turning now to <FIG>, illustrated are cross-sectional views of an example method of forming a semiconductor device <NUM>, useful for understanding the present invention. Beginning with <FIG>, formation of the semiconductor device <NUM> includes providing a substrate <NUM>. The substrate <NUM> may be implemented as a semiconductor wafer, such as a silicon wafer, optionally with an epitaxial layer, for example. The substrate <NUM> has a top surface <NUM>, a bottom surface <NUM> located opposite from the top surface <NUM>, and an N+ layer <NUM> extending from the bottom surface toward the top surface. The substrate <NUM> includes a semiconductor material <NUM>, such as silicon. The semiconductor material <NUM> may extend from the top surface <NUM> to the bottom surface <NUM>, as depicted in <FIG>.

The substrate <NUM> includes an area for an MOS transistor <NUM>. In the area for the MOS transistor <NUM>, one or more trenches <NUM> are formed in the substrate <NUM>. The trenches <NUM> extend from the top surface <NUM> into the semiconductor material <NUM>. The one or more trenches <NUM> may optionally be connected at a point not shown in <FIG>, to provide a single trench <NUM>. The trenches <NUM> may extend to proximate to the N+ layer <NUM>, as depicted in <FIG>. Alternatively, the trenches <NUM> may extend through the semiconductor material <NUM> to the N+ layer <NUM>. The trenches <NUM> may be <NUM> to <NUM> wide, for example, and may have aspect ratios of <NUM>:<NUM> to <NUM>:<NUM>, for example.

A first liner (e.g., a first dielectric liner) <NUM> is formed on the semiconductor material <NUM> in the trenches <NUM>. The first liner <NUM> of this example is formed by a thermal oxidation process at a temperature above <NUM>, so that the first liner <NUM> includes primarily thermal silicon dioxide having a stoichiometric composition of silicon dioxide, and a hydrogen content less than five atomic percent. The first liner <NUM> may have a thickness of <NUM> to <NUM> in the trenches <NUM>, for example. The first liner <NUM> may extend over the top surface <NUM> of the substrate <NUM>, as depicted in <FIG>.

Referring to <FIG>, a second liner (e.g., a second dielectric liner) <NUM> is formed on the trenches <NUM> on the first liner <NUM>. The second liner <NUM> may be formed by a thermal chemical vapor deposition (CVD) process using tetraethyl orthosilicate (TEOS), Si(OC<NUM>H<NUM>)<NUM>, sometimes referred to as tetraethoxysilane. The thermal CVD process may be implemented as a sub-atmospheric chemical vapor deposition (SACVD) process, for example, or as an atmospheric pressure chemical vapor deposition (APCVD) process. Alternatively, the second liner <NUM> may be formed by a plasma enhanced chemical vapor deposition (PECVD) process, using TEOS.

The second liner <NUM> includes primarily silicon dioxide. The second liner <NUM> is formed at a temperature sufficiently low so that the second liner <NUM> has an etch rate, in aqueous buffered hydrofluoric acid, that is at least twice an etch rate, in the same aqueous buffered hydrofluoric acid, of the first liner <NUM>. By way of example, the second liner <NUM> may be formed below <NUM>. The second liner <NUM> may be formed to have a greater thickness proximate to bottoms of the trenches <NUM> that proximate to tops of the trenches <NUM>, as depicted in <FIG>. The second liner <NUM> may be formed in two or more steps to attain a desired thickness profile in the trenches <NUM>. The second liner <NUM> may be removed from over the top surface <NUM> of the substrate <NUM>, as indicated in <FIG>, or may extend over the top surface <NUM>, similarly to the first liner <NUM>. A combination of the first liner <NUM> and the second liner <NUM> provides a shield liner <NUM> in the trenches <NUM>.

A shield <NUM> is formed in the trenches <NUM> on the shield liner <NUM>, extending to proximate to the top surface <NUM> of the substrate <NUM>. The shield <NUM> is electrically conductive, and is electrically isolated from the semiconductor material <NUM> by the shield liner <NUM>. The shield <NUM> may be formed by thermal or plasma decomposition of silane or disilane, so that the shield <NUM> may include primarily polycrystalline silicon, again sometimes referred to as polysilicon. The shield <NUM> may be formed at a temperature that is sufficiently low so as to maintain the etch rate of the second liner <NUM>, in aqueous buffered hydrofluoric acid, above twice the etch rate of the first liner <NUM>. By way of one example, the shield <NUM> may be formed of undoped polycrystalline silicon at <NUM> to <NUM>, and subsequently implanted with dopants and annealed to provide a desired electrical resistivity in the shield <NUM>. By way of another example, the shield <NUM> may be formed of doped polycrystalline silicon at <NUM> to <NUM> by including dopant reagents with the silane or disilane.

Referring to <FIG>, a top dielectric layer <NUM> is formed over the top surface <NUM> of the substrate <NUM>. The top dielectric layer <NUM> is patterned to expose the shield <NUM> in the trenches <NUM>. The top dielectric layer <NUM> may include silicon dioxide, and may be <NUM> to one µm thick, for example. The top dielectric layer <NUM> may be formed by a thermal CVD process using TEOS, or by a PECVD process using TEOS, at a temperature that is sufficiently low so as to maintain the etch rate of the second liner <NUM>, in aqueous buffered hydrofluoric acid, above twice the etch rate of the first liner <NUM>. An edge of the top dielectric layer <NUM> adjacent to the shield <NUM> may be tapered, as depicted in <FIG>, using an erodable etch mask, and etching the top dielectric layer <NUM> using an isotropic plasma etch process.

Referring to <FIG>, a shield etch mask <NUM> is formed over the top surface <NUM> of the substrate <NUM>, covering one or more contact portions <NUM> of the shield <NUM>, which may be located, for example, at ends <NUM> of the trenches <NUM>, and exposing the shield <NUM> past the contact portion <NUM>. The shield etch mask <NUM> may include photoresist, and may be formed by a photolithographic process. The shield etch mask <NUM> may include hard mask materials, such as silicon nitride or amorphous carbon. In an alternate version of this example, the shield etch mask <NUM> may be used to provide an etch mask for both the top dielectric layer <NUM> and the shield <NUM>, advantageously reducing fabrication cost and complexity of the semiconductor device <NUM>.

A portion of the shield <NUM> is removed where exposed by the shield etch mask <NUM>, leaving the shield <NUM> along a bottom portion of the trenches <NUM>. The portion of the shield <NUM> may be removed by a reactive ion etch (RIE) process using chlorine or bromine. The portion of the shield <NUM> may be removed by a timed etch process, to remove a desired amount of the shield <NUM>. The process of removing the portion of the shield <NUM> leaves the contact portion <NUM> with an angled surface <NUM> extending proximate to the top surface <NUM> of the substrate <NUM>. The process of removing the portion of the shield <NUM> also leaves at least a portion of the shield liner <NUM> in the trenches <NUM>, extending to the top surface <NUM>, as depicted in <FIG>.

Referring to <FIG>, the shield etch mask <NUM> of <FIG> is removed. The shield etch mask <NUM> may be removed by an oxygen plasma process, such as an asher process or a downstream asher process, or an ozone process, followed by a wet clean process using an aqueous mixture of sulfuric acid and hydrogen peroxide. Other methods for removing the shield etch mask <NUM> are within the scope of this example. The shield etch mask <NUM> may be used to provide an etch mask for the top dielectric layer <NUM>, before being removed, as noted above.

Referring to <FIG>, the second liner <NUM> is removed from the trenches <NUM> where exposed by the shield <NUM>. The second liner <NUM> may be removed by a wet etch using an aqueous solution of buffered hydrofluoric acid, for example a one percent solution of buffered hydrofluoric acid. At least a portion of the first liner <NUM> remains in the trenches <NUM>, extending up to the top surface <NUM> of the substrate <NUM>, due to the lower etch rate of the first liner <NUM> in the buffered hydrofluoric acid solution than the second liner <NUM>. The wet etch to remove the second liner <NUM> may be a timed etch process, to remove the second liner <NUM> where exposed by the shield <NUM>, while reducing etching of the second liner <NUM> between the shield <NUM> and the first liner <NUM>.

Forming the second liner <NUM> to have an etch rate at least twice that of the first liner <NUM> may advantageously enable complete removal of the second liner <NUM> where exposed by the shield <NUM> while leaving a continuous portion of the first liner <NUM> on the semiconductor material <NUM> in the trenches <NUM>, preventing erosion of the semiconductor material <NUM>. The process of removing the second liner <NUM> where exposed by the shield <NUM> may result in grooves <NUM> in the second liner <NUM> along the angled surface <NUM> of the contact portion <NUM> of the shield <NUM>, between the contact portion <NUM> and the first liner <NUM>, as depicted in <FIG>. The grooves <NUM> may expose edges of the contact portion <NUM> of the shield <NUM> along the angled surface <NUM>. These edges may be difficult to electrically isolate from a subsequently-formed gate <NUM>, shown in <FIG>, by a subsequently formed gate dielectric layer <NUM>, shown in <FIG>, alone.

Referring to <FIG>, a conformal layer <NUM> is formed over the top dielectric layer <NUM> and the top surface <NUM> of the substrate <NUM>, extending into the trenches <NUM> and covering the shield <NUM>, including the angled surface <NUM> of the contact portion <NUM> of the shield <NUM>. The conformal layer <NUM> fills in the grooves <NUM> of <FIG> in the second liner <NUM> along the angled surface <NUM> of the contact portion <NUM> of the shield <NUM>. The conformal layer <NUM> includes primarily silicon dioxide, and is formed, in this example, by a thermal CVD process using TEOS, such as an SACVD process or an APCVD process, or a PECVD process using TEOS, at a temperature sufficiently low so that the conformal layer <NUM> has an etch rate, in aqueous buffered hydrofluoric acid, that is at least twice an etch rate, in the same aqueous buffered hydrofluoric acid, of the first liner <NUM>. By way of example, the conformal layer <NUM> may be formed at approximately <NUM>. The conformal layer <NUM> is formed to be conformal in the trenches <NUM>, that is, an average thickness of the conformal layer <NUM> on angled surfaces of the trenches <NUM> is <NUM> percent to <NUM> percent of an average thickness of the conformal layer <NUM> on horizontal surfaces in the trenches <NUM>.

Referring to <FIG>, an isolation etch mask <NUM> is formed over the conformal layer <NUM>. The isolation etch mask <NUM> extends over the contact portion <NUM> of the shield <NUM> and into the trenches <NUM> past the angled surface <NUM> of the contact portion <NUM>. The isolation etch mask <NUM> does not cover the shield <NUM> throughout the trenches <NUM>. The isolation etch mask <NUM> may extend over the shield <NUM> past the angled surface <NUM> a lateral distance of one to five µm, for example, to allow for undercut of the conformal layer <NUM> while maintaining complete coverage of the angled surface <NUM>. The isolation etch mask <NUM> may include photoresist, and may be formed by a photolithographic process. Alternatively, the isolation etch mask <NUM> may include a polymer, and may be formed by an additive process, such as an ink jet process or a material extrusion process.

Referring to <FIG>, the conformal layer <NUM> of <FIG> is removed where exposed by the isolation etch mask <NUM> to form a shield isolation layer <NUM> of the conformal layer <NUM> covered by the isolation etch mask <NUM>. The conformal layer <NUM> may be removed by a wet etch using an aqueous solution of buffered hydrofluoric acid, for example a one percent solution of buffered hydrofluoric acid. The conformal layer <NUM> may be removed by a wet etch similar to that used to remove a portion of the second liner <NUM> as disclosed in reference to <FIG>. The process of removing the conformal layer <NUM> is performed so as to leave at least a portion of the first liner <NUM> in the trenches <NUM>, extending up to the top surface <NUM> of the substrate <NUM>, due to the lower etch rate of the conformal layer <NUM> in the buffered hydrofluoric acid solution than the first liner <NUM>. The wet etch to remove the conformal layer <NUM> may be a timed etch process, to reduce undercut of the conformal layer <NUM> and to reduce etching of the second liner <NUM> between the shield <NUM> and the first liner <NUM>. Forming the conformal layer <NUM> to have an etch rate at least twice that of the first liner <NUM> may advantageously enable complete removal of the conformal layer <NUM> where exposed by the isolation etch mask <NUM> while leaving a continuous portion of the first liner <NUM> on the semiconductor material <NUM> in the trenches <NUM>, preventing erosion of the semiconductor material <NUM>.

Referring to <FIG>, the isolation etch mask <NUM> of <FIG> is removed. The isolation etch mask <NUM> may be removed by an oxygen plasma process followed by a wet clean process, such as the process described for removal of the shield etch mask <NUM>, disclosed in reference to <FIG>.

The shield isolation layer <NUM> may optionally be heated after the isolation etch mask <NUM> is removed, to reduce an etch rate of the shield isolation layer <NUM> in an aqueous solution of buffered hydrofluoric acid, prior to removing the first liner <NUM> where exposed by the second liner <NUM> and the shield isolation layer <NUM>. For example, the shield isolation layer <NUM> may be heated to <NUM> to <NUM>, for five minutes to <NUM> minutes. Alternatively, formation of the semiconductor device <NUM> may be continued without heating the shield isolation layer <NUM>.

The shield isolation layer <NUM> covers the angled surface <NUM> of the contact portion <NUM> of the shield <NUM>, and extends into the grooves <NUM> in the second liner <NUM>, as shown in <FIG>, along the angled surface <NUM> of the contact portion <NUM> of the shield <NUM>. The shield isolation layer <NUM> may be formed to extend laterally on the shield <NUM> for a distance sufficient to provide complete coverage of the angled surface <NUM>.

Referring to <FIG>, the first liner <NUM> is removed in the trenches <NUM> where exposed by the second liner <NUM> and by the shield isolation layer <NUM>. The first liner <NUM> may be removed by an aqueous solution of buffered hydrofluoric acid, which may also remove a portion of the second liner <NUM> and a portion of the shield isolation layer <NUM>. The top surface <NUM> of the substrate <NUM> may remain covered by silicon dioxide after the first liner <NUM> is removed in the trenches <NUM>, as depicted in <FIG>. Alternatively, removal of the first liner <NUM> in the trenches <NUM> may result in removal of silicon dioxide from a portion or all of the top surface <NUM> where exposed by the shield isolation layer <NUM> and the top dielectric layer <NUM>. Forming the first liner <NUM> to be thinner than the second liner <NUM> and thinner than the shield isolation layer <NUM> may advantageously enable removal of the first liner <NUM> without significant degradation of the second liner <NUM> and the shield isolation layer <NUM>.

Referring to <FIG>, a gate dielectric layer <NUM> is formed on the semiconductor material <NUM> in the trenches <NUM> where exposed by the first liner <NUM>. The gate dielectric layer <NUM> may be formed by a thermal oxidation process, and may have a thickness of <NUM> to <NUM>, for example. Other methods for forming the gate dielectric layer <NUM> are within the scope of this example. Forming the gate dielectric layer <NUM> may result in forming a dielectric layer, not shown in <FIG>, on the shield <NUM> in the trenches <NUM>.

Referring to <FIG>, a lateral insulator <NUM> may be formed over the shield <NUM> in the trenches <NUM>. The lateral insulator <NUM> electrically isolates the shield <NUM> from a subsequently-formed gate <NUM>, shown in <FIG>. A method of forming the lateral insulator is hereinafter described with respect to <FIG>.

Referring to <FIG>, the gate <NUM> is formed in the trenches <NUM>, contacting the gate dielectric layer <NUM>. The gate <NUM> may include polycrystalline silicon, and may be formed by thermal or plasma decomposition of silane or disilane, for example. The gate <NUM> may be formed by a process similar to that used to form the shield <NUM>. The gate <NUM> is isolated from the contact portion <NUM> of the shield <NUM> by the shield isolation layer <NUM>. The shield isolation layer <NUM> may limit a low leakage current between the gate <NUM> and the shield <NUM> to a desired value during operation of the MOS transistor <NUM>. Formation of the semiconductor device <NUM> is continued by forming a source, body, drain contact region, and contacts, not shown in <FIG>, to provide a structure similar to the semiconductor device <NUM> of <FIG>.

As mentioned above, a low level of gate leakage current is generally a design characteristic for the MOS transistor. The lateral insulator as described provides a level of isolation between the shield and the gate to achieve the low level of gate leakage current. The lateral insulator as described below more specifically describes an example of the lateral insulator <NUM>, <NUM> for the semiconductor device <NUM>, <NUM>, respectively, to achieve the aforementioned intended results.

Turning now <FIG>, illustrated are cross-sectional views of an example method of forming a semiconductor device <NUM> according to the present invention.

The method employs a local oxidation of silicon (LOCOS) process to construct the lateral insulator. LOCOS refers to a microfabrication process wherein silicon dioxide is formed in selected areas on a silicon wafer having a silicon/silicon dioxide interface at a lower point than the rest of the silicon surface. LOCOS generally employs a process of thermally growing silicon dioxide in a furnace, a pad/buffer layer followed by CVD of silicon nitride and a nitride mask. (It is noted that while stoichiometric silicon nitride has the empirical formula Si<NUM>N<NUM>, CVD silicon nitride may depart from this empirical formula, and may include several atomic percent hydrogen. ) The silicon nitride layer (a protective layer) and silicon oxide layer (a pad layer) are etched. The lateral insulator is then thermally grown in the exposed area followed by removal of the nitride mask.

As introduced herein, a lateral insulator provides a higher level of isolation between a shield and a gate in a trench. A wet etch is used to partially remove oxide from upper sidewalls of the trench. A polysilicon soft etch is then used to smooth the shield polysilicon top surface. LOCOS with a thin pad, followed by silicon nitride, and then thick oxidation is employed on top of the shield polysilicon. Gate oxide is then grown followed by deposition of gate polysilicon to form the gate.

Referring initially to <FIG>, a trench <NUM> is formed in a substrate <NUM> (e.g., silicon substrate) extending from a top surface <NUM> thereof toward a bottom surface <NUM> of the substrate <NUM>. An N+ layer <NUM> extends from the bottom surface <NUM> toward the top surface <NUM>. The N+ layer <NUM> may be a portion of a heavily-doped N-type wafer below the trench <NUM>. The substrate <NUM> above the N+ layer <NUM> may be an N-type epitaxial layer to serve as a drift region of the semiconductor device <NUM>. The trench <NUM> may be <NUM> to <NUM> wide, for example, and may have aspect ratios of <NUM>:<NUM> to <NUM>:<NUM>, for example. While the description that follows refers to a single trench <NUM> and related features, the principles as disclosed herein may apply to multiple trenches with the analogous structure(s) or otherwise to form the semiconductor device <NUM>.

Turning now to <FIG>, a first liner (e.g., a (first) dielectric liner, (first) oxide liner) <NUM> is formed over the sidewalls of the trench <NUM> and a surface (e.g., the top surface <NUM>) of the substrate <NUM>. The first liner <NUM> of this example is formed by a thermal oxidation process at a temperature above <NUM>, so that the first liner <NUM> includes primarily thermal silicon dioxide having a stoichiometric composition of silicon dioxide (SiO<NUM>), and a hydrogen content less than five atomic percent. Such a thermally grown silicon dioxide layer may be referred to as "thermal oxide". The first liner <NUM> may have a thickness of <NUM> to <NUM> in the trench <NUM>, for example.

Turning now to <FIG>, a second liner (e.g., a (second) dielectric liner, (second) oxide liner) <NUM> is formed over the first liner <NUM> in the trench <NUM>. The second liner <NUM> may be formed by a chemical vapor deposition (CVD) process using tetraethyl orthosilicate TEOS), Si(OC<NUM>H<NUM>)<NUM>, sometimes referred to as tetraethoxysilane. The CVD process may be implemented as a sub-atmospheric chemical vapor deposition (SACVD) process, for example, or as an atmospheric pressure chemical vapor deposition (APCVD) process. Alternatively, the second liner <NUM> may be formed by a plasma enhanced chemical vapor deposition (PECVD) process, using TEOS. Any dielectric layer formed from one of these processes may be referred to as "CVD oxide".

The second liner <NUM> may primarily include silicon dioxide. The second liner <NUM> may be formed at a temperature sufficiently low so that the second liner <NUM> has an etch rate, in aqueous buffered hydrofluoric acid, that is at least twice an etch rate, in the same aqueous buffered hydrofluoric acid, of the first liner <NUM>. By way of example, the second liner <NUM> may be formed below <NUM>. The second liner <NUM> may be formed to have a greater thickness proximate to bottom of the trench <NUM> than proximate the top of the trench <NUM>, as depicted in <FIG>. The second liner <NUM> may be formed in two or more steps to attain a desired thickness profile in the trench <NUM>. A combination of the first liner <NUM> and the second liner <NUM> provides or forms a shield liner <NUM> in the trench <NUM> having a wider lower portion and a narrower upper portion.

The second liner <NUM> is shown having a thicker portion toward the bottom of the trench <NUM> and a wider portion toward the top of the trench <NUM>. This profile may be formed, e.g., by placing a material, such a photoresist with a lower etch rate than the second liner <NUM> material, in the bottom of the trench <NUM> and removing a portion of the exposed second liner <NUM> material, e.g., by aqueous buffered hydrofluoric acid. Additional details may be found in <CIT> (Attorney Docket No. TI-<NUM>) entitled "Semiconductor Device having Polysilicon Field Plate for Power MOSFETs" filed July <NUM>, <NUM>. While in the illustrated example a portion of the second liner <NUM> remains over the first dielectric liner <NUM>, in other implementations the second liner <NUM> may be completely removed over the first dielectric liner <NUM> in the wider (upper) portion of the trench <NUM>. In such implementations the lower etch rate of the first liner <NUM> may allow the first liner <NUM> to act as an effective etch stop for the hydrofluoric acid etch process.

Turning now to <FIG>, a polysilicon shield <NUM> is formed over the second liner <NUM> in the trench <NUM> extending to proximate to the top surface of the substrate <NUM>. The shield <NUM> is electrically conductive, and is electrically isolated from the semiconductor material of the substrate <NUM> by the shield liner <NUM>. The shield <NUM> may be formed by thermal or plasma decomposition of silane or disilane, so that the shield <NUM> includes primarily polycrystalline silicon, again sometimes referred to as polysilicon. By way of one example, the shield <NUM> may be formed of undoped polycrystalline silicon at <NUM> to <NUM>, and subsequently implanted with dopants and annealed to provide a desired electrical resistivity in the shield <NUM>. By way of another example, the shield <NUM> may be formed of doped polycrystalline silicon at <NUM> to <NUM> by including dopant reagents with the silane or disilane. The aforementioned features of the semiconductor device <NUM> are analogous to the like features of the semiconductor devices <NUM>, <NUM> of <FIG> and <FIG>. The shield <NUM> may be doped in situ or doped by ion implantation to result in a desired conductivity.

Turning now to <FIG>, a portion of the shield <NUM> is removed from the trench <NUM> exposing a portion of the second liner <NUM> employing an anisotropic plasma etch, for example. The anisotropic plasma etch may employ oxygen (O<NUM>) plus fluoromethane (CH<NUM>F) as an etchant. In implementations for which the second liner <NUM> is previously completely removed over the first liner <NUM> in the upper portion of the trench <NUM>, the first liner <NUM> is exposed by the removal of the portion of the shield <NUM>.

Turning now to <FIG>, the second liner <NUM>, if present in the upper portion of the trench <NUM>, is removed on exposed sidewalls of the trench <NUM> between the shield <NUM> and the top surface <NUM> exposing the first liner <NUM> above the polysilicon shield <NUM>. Additionally, a portion of the first liner <NUM> is removed on the exposed sidewalls of the trench <NUM> and the surface of the substrate <NUM>. The second liner <NUM> and portion of the first liner <NUM> may be removed by a wet chemical etch. If the first liner <NUM> is about <NUM>, as an example <NUM> may be removed via the wet chemical etch. A portion of the first liner <NUM> remains to protect top corners <NUM> of the trench <NUM>. The corners <NUM> are exposed by partially removing the first liner <NUM> and the second liner <NUM> as set forth above.

Regarding <FIG>, illustrated is an alternative example, in which the second liner <NUM> is completely removed from the first liner <NUM> in the upper portion of the trench <NUM>. In this example, a space between each of the corners <NUM> and the first liner <NUM> results from the relatively small amount of material removed from the first liner <NUM> by the wet chemical etch as compared to the example of <FIG>.

Turning now to <FIG> following <FIG>, a pad layer (e.g., a pad oxide layer) <NUM> is formed over, and optionally touching, the exposed portions of the shield <NUM>, exposed portions of the second liner <NUM> and a section of exposed portions of the first liner <NUM> (after exposing the first liner <NUM> above the shield <NUM>). The pad layer <NUM> may have a thickness of <NUM> to <NUM> in the trench <NUM>, for example. The pad layer <NUM> of this example is formed by a thermal oxidation process at a temperature above <NUM>, so that the pad layer <NUM> includes primarily thermal silicon dioxide having a stoichiometric composition of silicon dioxide.

Turning now to <FIG>, a protective layer (e.g., a protective nitride layer) <NUM> is formed over exposed portions of the semiconductor device <NUM> including in the trench <NUM> over exposed portions of the first liner <NUM> and the pad layer <NUM>. The protective layer <NUM> may be a shield etch mask including hard mask materials, such as silicon nitride with a thickness of <NUM> to <NUM>.

Turning now to <FIG>, a portion of the protective layer <NUM> above the pad layer <NUM> is removed employing an anisotropic plasma etch, for example, providing an exposed portion of the pad layer <NUM>. The anisotropic plasma etch may employ oxygen (O<NUM>) plus fluoromethane (CH<NUM>F) feedstock as an etchant.

Turning now to <FIG>, the exposed portion of the pad layer <NUM> above the shield <NUM> is removed employing an anisotropic plasma etch, for example. The anisotropic plasma etch may employ oxygen plus fluoromethane feedstock as an etchant.

Turning now to <FIG>, a portion of the shield <NUM> is removed (after removing the exposed pad layer <NUM>) employing an isotropic soft plasma etch, for example. Thus, a top surface of the shield <NUM> is smoothed employing the isotropic soft plasma etch. In particular, relatively sharp features of the shield <NUM> are smoothed or removed by the isotropic soft plasma etch. Removing these features may reduce the opportunity to form high eclectic fields during operation that could reduce device reliability and/or lifetime. The isotropic soft plasma etch may employ oxygen plus carbon tetrafluoride as an etchant to also remove the portion of the shield <NUM> as illustrated.

Turning now to <FIG>, a lateral insulator (e.g., a lateral oxide insulator) <NUM> is formed over the shield <NUM> contacting a portion of the first liner <NUM> and the second liner <NUM>. The lateral insulator <NUM> may have a thickness of <NUM> to <NUM> in the trench <NUM>, for example. The lateral insulator <NUM> of this example is formed by a thermal oxidation process at a temperature above <NUM> - <NUM>, so that the lateral insulator <NUM> includes primarily thermal silicon dioxide having a stoichiometric composition of silicon dioxide. Because the thickness of the lateral insulator <NUM> is independent of the thickness of a gate dielectric layer <NUM> formed at a later stage of formation (see <FIG>, supra), the lateral insulator <NUM> may be formed with a thickness that advantageously provides improved voltage isolation between the shield <NUM> and a gate to be formed later thereover, relative to conventional similar devices.

Turning now to <FIG>, remaining portions of the protective layer <NUM> are removed (after forming the lateral insulator <NUM>) leaving the exposed portions of the first liner <NUM> and the lateral insulator <NUM> in the trench <NUM>. The remaining portions of the protective layer <NUM> are removed employing a wet chemical etch, for example. The wet chemical etch may employ phosphoric acid (H<NUM>PO<NUM>) as an etchant.

Turning now to <FIG>, the exposed portions of the first liner <NUM> on the surface of the substrate <NUM> and in the trench <NUM> between the lateral insulator <NUM> and the top surface <NUM> are removed employing, for example, a wet chemical etch using, for instance, hydrofluoric acid.

Turning now to <FIG>, a gate dielectric layer <NUM> is formed over the surface of the substrate <NUM> and the exposed sidewalls of the trench <NUM>. The gate dielectric layer <NUM> may have a thickness of <NUM> to <NUM>, for example. The gate dielectric layer <NUM> of this example is formed by a thermal oxidation process at a temperature above <NUM>, so that the gate dielectric layer <NUM> includes primarily thermal silicon dioxide having a stoichiometric composition of silicon dioxide. The lateral insulator <NUM> may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer <NUM>.

Turning now to <FIG>, a gate electrode <NUM> is formed over the gate dielectric layer <NUM> and the lateral insulator <NUM> in the trench <NUM>. The gate electrode <NUM> may include polycrystalline silicon, and may be formed by thermal decomposition of silane or disilane, for example. The gate electrode <NUM> may be formed by a process similar to that used to form the shield <NUM>.

Turning now to <FIG>, portions of the gate electrode <NUM> are removed over the gate dielectric <NUM> on the surface of the substrate <NUM> and above the trench <NUM>, e.g., employing an anisotropic plasma etch or chemical-mechanical polishing (CMP). The anisotropic plasma etch may employ oxygen (O<NUM>) plus fluoromethane (CH<NUM>F) as an etchant.

Turning now to <FIG>, source regions <NUM> and body regions <NUM> are formed (e.g., via an ion implant) in the substrate <NUM> on opposing sides of the gate electrode <NUM>. The source regions <NUM> have a first conductivity type, for example, n-type. The body regions <NUM> have a second conductivity type, opposite from the first conductivity type; in this example, a p-type.

Turning now to <FIG>, a portion of the N+ layer <NUM> may be removed, e.g. by backgrinding, to produce a drain contact region <NUM> that extends to a new bottom surface <NUM>'. A metal layer (not shown) may be formed on the surface <NUM>' to form provide an ohmic connection to the drain contact region <NUM>. Thus, if the source regions <NUM> are oriented toward the top surface <NUM> of the semiconductor device <NUM>, the drain contact region <NUM> extends to the bottom surface <NUM>' of the substrate <NUM>. The drain contact region <NUM> has the first conductivity type, which is n-type in this example, and may be heavily doped. The semiconductor material of the substrate <NUM> between the body regions <NUM> and the drain contact region <NUM> may have the first conductivity type, n-type in this example, and may provide a drain drift region for the semiconductor device <NUM>.

As a result of the processes and structures described hereinabove with thick oxide LOCOS in a trench between a conductive trench shield and a gate electrode, an improved semiconductor device consistent with the device <NUM> has been found to exhibit significantly reduced gate leakage current as compared to similar conventional devices. As an example, the improved semiconductor device exhibits two orders of magnitude of reduced gate leakage current at gate voltages of <NUM> volts and <NUM> volts compared to other similar conventional devices. The structure of the lateral insulator provides a high level of voltage isolation between the trench shield and the gate electrode in part by increasing at least partially removing the corners that result from the trench shield etchback (e.g., the corners <NUM>, <FIG>), and by providing control of the lateral insulator thickness independent of the thickness of the gate dielectric layer.

With continuing reference to <FIG>, an example semiconductor device <NUM> includes a trench <NUM> in a substrate <NUM> having a top surface <NUM> (see, e.g., <FIG>), and a shield <NUM> within the trench <NUM> (see, e.g., <FIG>). The semiconductor device <NUM> also includes a first liner <NUM> between a sidewall of the trench <NUM> and the shield <NUM> (see, e.g., <FIG>), and a second liner <NUM> between the first liner <NUM> and the shield <NUM> (see, e.g., <FIG>). The first liner <NUM> and the second liner <NUM> form a shield liner <NUM> having a wider lower portion and a narrower upper portion. The semiconductor device <NUM> also includes a lateral insulator <NUM> over the shield <NUM> contacting the first liner <NUM> (see, e.g., <FIG>).

The semiconductor device <NUM> also includes a gate dielectric layer <NUM> formed on exposed sidewalls of the trench <NUM> between the lateral insulator <NUM> and the top surface <NUM> (see, e.g., <FIG>). The lateral insulator <NUM> may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer <NUM>. The semiconductor device <NUM> also includes a gate electrode <NUM> over the gate dielectric layer <NUM> and the lateral insulator <NUM> in the trench <NUM> (see, e.g., <FIG>), as well as source regions <NUM> and body regions <NUM> in the substrate <NUM> on opposing sides of the gate electrode <NUM> (see, e.g., <FIG>). The semiconductor device <NUM> also includes a drain contact region <NUM> with an opposing surface (the bottom surface <NUM>') of the substrate <NUM> from the source regions <NUM> (see, e.g., <FIG>).

With continuing reference to <FIG>, an example method of forming a semiconductor device <NUM> includes forming the trench <NUM> in the substrate <NUM> having the top surface <NUM> (see, e.g., <FIG>), forming the first (dielectric) liner <NUM> over sidewalls of the trench <NUM> (see, e.g., <FIG>), and forming the shield <NUM> over a second (dielectric) liner <NUM> (see, e.g., <FIG>). The first liner <NUM> and the second liner <NUM> may form a shield liner <NUM> having a wider lower portion and a narrower upper portion. (See, e.g., <FIG>. ) The method also includes removing a portion of the polysilicon shield <NUM> (see, e.g., <FIG>), and forming the lateral insulator <NUM> over the polysilicon shield <NUM> contacting the first liner <NUM> (see, e.g., <FIG>). The method also includes removing the first liner <NUM> between the lateral insulator <NUM> and the top surface <NUM> providing an exposed sidewall(s) of the trench <NUM> (see, e.g., <FIG>), and forming the gate dielectric layer <NUM> over the exposed sidewall(s) of the trench <NUM> (see, e.g., <FIG>). The lateral insulator <NUM> may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer <NUM>.

With respect to forming the lateral insulator <NUM> the method may include forming the pad layer <NUM> over the polysilicon shield <NUM> (see, e.g., <FIG>), and forming the protective layer <NUM> over the first liner <NUM> (see, e.g., <FIG>). The method further includes removing the pad layer <NUM> by a process selective to the protective layer <NUM> (see, e.g., <FIG>), and removing a portion of the polysilicon shield <NUM> (see, e.g., <FIG>).

The method also includes forming the gate electrode <NUM> over the gate dielectric layer <NUM> and the lateral insulator <NUM> in the trench <NUM> (see, e.g., <FIG>), and forming source regions <NUM> in the substrate <NUM> on opposing sides of the gate electrode <NUM> (see, e.g., <FIG>). The method further includes forming a drain contact region <NUM> extending from the bottom surface <NUM>' of the substrate <NUM> toward the top surface <NUM>. (See, e.g., <FIG>.

For a better understanding of semiconductor devices that may employ a lateral insulator as described herein and/or vertical metal oxide semiconductor transistors, see <CIT> (Attorney Docket No. TI-<NUM>) entitled "Trench Shield Isolation Layer" filed August <NUM>, <NUM>.

It is noted that terms such as top, bottom, over, and below may be used in this disclosure. These terms should not be construed as limiting the position or orientation of a structure or element, but should be used to provide spatial relationship between structures or elements.

Thus, a semiconductor device including a lateral insulator, and related methods of forming the same, has been introduced. It should be understood that the previously described examples of the semiconductor device, and related methods, are submitted for illustrative purposes only and that other examples that facilitate low gate leakage current between the gate and shield of the semiconductor device are well within the scope of the present disclosure.

Although the present disclosure has been described in detail, various changes, substitutions and alterations may be made without departing from the scope of the disclosure as defined in the appended claims.

Claim 1:
A method of forming a semiconductor device (<NUM>), comprising in the following order:
forming a trench (<NUM>) in a substrate (<NUM>) having a top surface (<NUM>);
forming a first dielectric liner (<NUM>) over sidewalls of the trench (<NUM>);
forming a second dielectric liner (<NUM>) over the first dielectric liner (<NUM>);
forming a polysilicon shield (<NUM>) over the second dielectric liner (<NUM>);
removing a portion of the polysilicon shield (<NUM>);
removing the second liner (<NUM>) on the sidewalls of the trench (<NUM>) exposed by the removal of the portion of the polysilicon shield (<NUM>), at least a portion of the first liner (<NUM>) remaining to protect top corners (<NUM>) of the trench (<NUM>);
forming an insulator (<NUM>) over the polysilicon shield (<NUM>) contacting the first dielectric liner (<NUM>) such that the first dielectric liner (<NUM>) is located laterally between the insulator (<NUM>) and the substrate (<NUM>);
removing the first dielectric liner (<NUM>) between the insulator (<NUM>) and the top surface (<NUM>) providing an exposed sidewall of the substrate (<NUM>);
forming a gate dielectric layer (<NUM>) over the exposed sidewall of the substrate (<NUM>); and forming a gate electrode (<NUM>) over the gate dielectric layer (<NUM>) and said insulator (<NUM>).