Patent Description:
A bipolar junction transistor is a three-terminal electronic device that includes an emitter, a collector, and an intrinsic base defining respective junctions with the emitter and collector. In a PNP bipolar junction transistor, the emitter and collector are comprised of p-type semiconductor material, and the intrinsic base is comprised of n-type semiconductor material. In an NPN bipolar junction transistor, the emitter and collector are comprised of n-type semiconductor material, and the intrinsic base is comprised of p-type semiconductor material. In operation, the base-emitter junction is forward biased, the base-collector junction is reverse biased, and the collector-emitter current may be controlled with the base-emitter voltage.

A heterojunction bipolar transistor is a variant of a bipolar junction transistor in which the semiconductor materials have different energy bandgaps, which creates heterojunctions. For example, the collector and emitter of a heterojunction bipolar transistor may be constituted by silicon, and the intrinsic base of a heterojunction bipolar transistor may be constituted by silicon-germanium, which is characterized by a narrower band gap than silicon. Heterojunction bipolar transistors may exhibit improvements in high frequency performance as a result of the introduction of heterojunctions.

A resistive random-access memory device provides one type of embedded non-volatile memory technology. A bitcell of a resistive random-access memory device includes a resistive memory element and an access transistor that controls operations used to write, erase, and read the resistive memory element. Because resistive memory elements are non-volatile, bits of data are retained as stored content by the resistive memory elements when the resistive random-access memory device is not powered. The non-volatility of a resistive random-access memory device contrasts with volatile memory technologies, such as a static random-access memory device in which the stored content is eventually lost when unpowered and a dynamic random-access memory device in which the stored content is lost unless periodically refreshed.

Field-effect transistors are commonly used as access transistors in a resistive random-access memory device. Reliable operation of the bitcell of a resistive random-access memory device imposes restrictions on the field-effect transistors. For example, the minimum voltage and drive current requirements imposed on the field-effect transistors restrict the ability to shrink the bitcell dimensions. As a result, the scalability of the bitcell is restricted.

<CIT> and <CIT> describe memory device structures comprising bipolar junction transistor selectors formed by patterning a stack of layers on a substrate. Improved structures that include bipolar junction transistors and methods of forming such structures are needed.

According to an embodiment of the invention, a structure comprises a semiconductor layer including a first section, a substrate, and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer positioned between the first collector and the first emitter. The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer positioned between the second collector and the second emitter. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by the first section of the semiconductor layer to define a first base line. The first collector is a portion of a first well in the substrate, and the second collector is a portion of a second well in the substrate.

The first collector, the first emitter, the second collector, and the second emitter may have n-type conductivity, and the first base layer and the second base layer may have p-type conductivity.

The first well may be separated from the second well by a portion of the substrate. Moreover, the first well and the second well may have n-type conductivity, and the portion of the substrate may have p-type conductivity.

The structure may further comprise a trench isolation region extending through the semiconductor layer and the dielectric layer into the substrate. The trench isolation region may be positioned between the first well and the second well.

The structure may further comprise: a third bipolar junction transistor including a third collector in the substrate, a third emitter, and a third base layer, the third base layer extending through the dielectric layer from the third emitter to the third collector; and a trench isolation region positioned between the first base layer and the third base layer. The trench isolation region may extend into the first well. Additionally or alternatively, the trench isolation region may be positioned in a lateral direction between the first emitter and the third emitter.

The first well and the second well of the structure may be longitudinally aligned orthogonal to the first base line.

Additionally, the structure may further comprise an alignment structure positioned between the first emitter and the second emitter. For instance, the alignment structure may be a dummy gate structure. The alignment structure may be positioned on the first section of the semiconductor layer.

The above structure may further comprise a first memory element connected to the first emitter of the first bipolar junction transistor, and a second memory element connected to the second emitter of the second bipolar junction transistor. The first memory element and the second memory element may each include a first electrode, a second electrode, and a switching layer positioned between the first electrode and the second electrode.

Additionally, the structure may comprise an interconnect structure over the first bipolar junction transistor and the second bipolar junction transistor. The interconnect structure may include a plurality of dielectric layers in a layer stack. The first memory element and the second memory element may be positioned in the interconnect structure.

The semiconductor layer may include a second section, and the above structure may further comprise: a third bipolar junction transistor positioned adjacent to the first bipolar junction transistor, the third bipolar junction transistor including a third collector in the substrate, a third emitter, and a third base layer, the third base layer extending through the dielectric layer from the third emitter to the third collector; and a fourth bipolar junction transistor including a fourth collector in the substrate, a fourth emitter, and a fourth base layer positioned between the fourth collector and the fourth emitter, the fourth base layer extending through the dielectric layer from the fourth emitter to the fourth collector, and the fourth base layer connected to the third base layer by the second section of the semiconductor layer to define a second base line. The first collector and the third collector may be portions of the first well, and the second collector and the fourth collector may be portions of the second well. Optionally, a trench isolation region may be positioned between the first base line and the second base line.

According to an embodiment of the invention, a method comprises forming a first bipolar junction transistor including a first collector in a substrate, a first emitter, and a first base layer positioned between the first collector and the first emitter. A dielectric layer is disposed between the substrate and an overlying semiconductor layer, and the first base layer extends through the dielectric layer from the first emitter to the first collector. The method further comprises forming a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer positioned between the second collector and the second emitter. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line. The first collector is a portion of a first well in the substrate, and the second collector is a portion of a second well in the substrate.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.

With reference to <FIG>, <FIG>, <FIG>, <FIG> and in accordance with embodiments of the invention, a structure <NUM> for a resistive random-access memory device includes an array of bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM> that may be fabricated using a silicon-on-insulator substrate that includes a semiconductor layer <NUM>, a substrate <NUM>, and a dielectric layer <NUM> disposed between the semiconductor layer <NUM> and the substrate <NUM>. The semiconductor layer <NUM> may be comprised of a semiconductor material, such as single-crystal silicon, and may be lightly doped with a p-type dopant. The dielectric layer <NUM> may be comprised of a dielectric material, such as silicon dioxide, that is an electrical insulator. The substrate <NUM> may be comprised of a semiconductor material, such as silicon, and the substrate <NUM> may be lightly doped with a p-type dopant. The dielectric layer <NUM> has an upper interface <NUM> with the semiconductor layer <NUM>, the dielectric layer <NUM> has a lower interface <NUM> with the substrate <NUM>, and the upper and lower interfaces <NUM>, <NUM> may be separated by the thickness of the dielectric layer <NUM>. Field-effect transistors (not shown) may be fabricated by CMOS processes in a region of the silicon-on-insulator substrate different from the region including the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM>. In an embodiment, the semiconductor layer <NUM> may have a thickness suitable to fabricate fully-depleted silicon-on-insulator (FDSOI) field-effect transistors. In an embodiment, the semiconductor layer <NUM> may have a thickness in a range of about <NUM> nanometers (nm) to about <NUM>. In an embodiment, the dielectric layer <NUM> may have a thickness in a range of about <NUM> to about <NUM>.

Wells <NUM>, <NUM> may be formed as doped regions in the substrate <NUM> that are positioned in a vertical direction beneath the interface <NUM> between the dielectric layer <NUM> and the substrate <NUM>. In an embodiment, the wells <NUM>, <NUM> may adjoin the interface <NUM> between the dielectric layer <NUM> and the substrate <NUM>. In an embodiment, the wells <NUM>, <NUM> may longitudinally extend as stripes of doped semiconductor material, and the well <NUM> may be aligned parallel to the well <NUM>. The semiconductor material constituting the wells <NUM>, <NUM> may have an opposite conductivity type from the semiconductor material constituting the substrate <NUM>. A portion of the substrate <NUM> is arranged in a lateral direction between the well <NUM> and the well <NUM>, and the oppositely-doped portion of the substrate <NUM> may electrically isolate the well <NUM> from the well <NUM>. The wells <NUM>, <NUM> may be contacted at an edge of the transistor array.

The wells <NUM>, <NUM> may be formed in the substrate <NUM> by introducing a dopant by, for example, ion implantation with given implantation conditions. A patterned implantation mask may be formed to define selected areas that are exposed for the implantation of ions. The implantation mask may include a layer of an organic photoresist that is applied and patterned to form openings exposing the selected areas and determining, at least in part, the location and horizontal dimensions of the wells <NUM>, <NUM>. The implantation mask has a thickness and stopping power sufficient to block the implantation of ions in masked areas. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the electrical and physical characteristics of the wells <NUM>, <NUM>. In an embodiment, the wells <NUM>, <NUM> may be doped with a concentration of an n-type dopant (e.g., arsenic or phosphorus) such that the wells <NUM>, <NUM> have n-type conductivity.

The bipolar junction transistor <NUM> includes a base layer <NUM> that adjoins an underlying portion of the well <NUM>, and the adjoined portion of the well <NUM> may define a collector of the bipolar junction transistor <NUM>. The bipolar junction transistor <NUM> includes a base layer <NUM> that adjoins an underlying portion of the well <NUM>, and the adjoined portion of the well <NUM> may define a collector of the bipolar junction transistor <NUM>. The base layer <NUM> is connected to the base layer <NUM> by a section of the semiconductor layer <NUM>, and the base layers <NUM>, <NUM> may be connected to adjacent base layers (not shown) by respective sections of the semiconductor layer <NUM> to define a base line <NUM> that may be contacted at an edge of the array. The bipolar junction transistor <NUM> includes a base layer <NUM> that adjoins an underlying portion of the well <NUM>, and the adjoined portion of the well <NUM> may define a collector of the bipolar junction transistor <NUM>. The bipolar junction transistor <NUM> includes a base layer <NUM> that adjoins an underlying portion of the well <NUM>, and the adjoined portion of the well <NUM> may define a collector of the bipolar junction transistor <NUM>. The base layer <NUM> is connected to the base layer <NUM> by a section of the semiconductor layer <NUM>, and the base layers <NUM>, <NUM> may be connected to adjacent base layers (not shown) by respective sections of the semiconductor layer <NUM> to define a base line <NUM> that may be contacted at an edge of the array. The base layers <NUM>, <NUM> may define intrinsic bases of the bipolar junction transistors <NUM>, <NUM> that adjoin the respective intersected portions of the well <NUM> along interfaces defining p-n junctions, and the base layers <NUM>, <NUM> may define intrinsic bases of the bipolar junction transistors <NUM>, <NUM> that adjoin the respective intersected portions of the well <NUM> along interfaces defining p-n junctions.

The base layers <NUM>, <NUM>, <NUM>, <NUM> may be formed by patterning trenches that penetrate through the semiconductor layer <NUM> and dielectric layer <NUM> with lithography and etching processes, depositing and planarizing a semiconductor layer to fill the trenches, and forming trench isolation regions <NUM> positioned between the base layer <NUM>, <NUM> in one row and the base layers <NUM>, <NUM> in an adjacent row. In an embodiment, the base layers <NUM>, <NUM>, <NUM>, <NUM> may be comprised of a semiconductor material that is doped to have an opposite conductivity type from the doped regions providing the wells <NUM>, <NUM>. In an embodiment, the base layers <NUM>, <NUM>, <NUM>, <NUM> may be comprised of silicon. In an embodiment, the base layers <NUM>, <NUM>, <NUM>, <NUM> may be comprised of silicon-germanium. In an embodiment, the base layers <NUM>, <NUM>, <NUM>, <NUM> may be comprised of silicon-germanium containing a germanium content of less than or equal to than <NUM> atomic percent and the balance silicon. In an embodiment, the base layers <NUM>, <NUM>, <NUM>, <NUM> may be doped with a concentration a p-type dopant (e.g., boron) such that the base layers <NUM>, <NUM>, <NUM>, <NUM> have p-type conductivity.

The base layers <NUM>, <NUM> extend through the semiconductor layer <NUM> and the dielectric layer <NUM> to adjoin the well <NUM>, and the base layers <NUM>, <NUM> extend through the semiconductor layer <NUM> and the dielectric layer <NUM> to adjoin the well <NUM>. In an embodiment, the base layers <NUM>, <NUM>, <NUM>, <NUM> may extend in a vertical direction fully through the dielectric layer <NUM> from the level of the interface <NUM> to the level of the interface <NUM>. In an embodiment, lower portions of the base layers <NUM>, <NUM>, <NUM>, <NUM> may be coplanar or substantially coplanar with the interface <NUM>. As best shown in <FIG>, the wells <NUM>, <NUM> may be longitudinally aligned orthogonal to the base line <NUM> including the base layer <NUM>, the base layer <NUM>, and the sections of the semiconductor layer <NUM> connected to the base layers <NUM>, <NUM>. As best shown in <FIG>, the wells <NUM>, <NUM> may be longitudinally aligned orthogonal to the base line <NUM> including the base layer <NUM>, the base layer <NUM>, and the sections of the semiconductor layer <NUM> connected to the base layers <NUM>, <NUM>. The sections of the semiconductor layer <NUM> in the base lines <NUM>, <NUM> may be doped to have the same conductivity type (e.g., p-type) as the base layers <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and the sections of the semiconductor layer <NUM> in the base lines <NUM>, <NUM> are isolated from the substrate <NUM> by the dielectric layer <NUM>.

The trench isolation regions <NUM> electrically isolate the base layers <NUM>, <NUM> in the base line <NUM> from the base layers <NUM>, <NUM> in the base line <NUM>. The trench isolation regions <NUM> may be formed by patterning shallow trenches with lithography and etching processes, depositing a dielectric material, such as silicon dioxide, to fill the shallow trenches, and planarizing and/or recessing the dielectric material. One of the trench isolation regions <NUM> is positioned between the base layer <NUM> and the base layer <NUM>, and another of the trench isolation regions <NUM> is positioned between the base layer <NUM> and the base layer <NUM>.

Alignment structures <NUM> are formed that may be aligned parallel to each other and that may extend parallel to the wells <NUM>, <NUM>. In an embodiment, the alignment structures <NUM> may be dummy gate structures formed by a CMOS process and that may include a layer of polysilicon stacked on a layer of a dielectric material, such as silicon dioxide. The alignment structures <NUM> are positioned on the semiconductor layer <NUM> and, in particular, on the sections of the semiconductor layer <NUM> participating in the base lines <NUM>, <NUM>. The alignment structures <NUM> may be electrically non-functional in the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM>.

The bipolar junction transistor <NUM> includes an emitter <NUM> that adjoins the base layer <NUM> along an interface defining a p-n junction. The bipolar junction transistor <NUM> includes an emitter <NUM> that adjoins the base layer <NUM> along an interface defining a p-n junction. The bipolar junction transistor <NUM> includes an emitter <NUM> that adjoins the base layer <NUM> along an interface defining a p-n junction. The bipolar junction transistor <NUM> includes an emitter <NUM> that adjoins the base layer <NUM> along an interface defining a p-n junction. One of the trench isolation regions <NUM> is positioned in a lateral direction between the emitter <NUM> and the emitter <NUM>, and one of the trench isolation regions <NUM> is positioned in a lateral direction between the emitter <NUM> and the emitter <NUM>.

The emitters <NUM>, <NUM>, <NUM>, <NUM> may be respectively formed as raised semiconductor layers on the base layers <NUM>, <NUM>, <NUM>, <NUM> at the intersections between the base lines <NUM>, <NUM> and the wells <NUM>, <NUM>. The base layers <NUM>, <NUM>, <NUM>, <NUM> are positioned in a vertical direction between the portions of the wells <NUM>, <NUM> defining the collectors and the emitters <NUM>, <NUM>, <NUM>, <NUM>. In an embodiment, the emitters <NUM>, <NUM>, <NUM>, <NUM> may be formed by epitaxially growing semiconductor material. The alignment structures <NUM> and the trench isolation regions <NUM> may function to self-align the formation of the emitters <NUM>, <NUM>, <NUM>, <NUM> in a selective epitaxial growth process. In an embodiment, the respective surface areas of the base layers <NUM>, <NUM>, <NUM>, <NUM> contacted by the emitters <NUM>, <NUM>, <NUM>, <NUM> are constrained by the alignment structures <NUM> and the trench isolation regions <NUM> such that the cross-sectional areas of the emitters <NUM>, <NUM>, <NUM>, <NUM> in a vertical perspective are equal to the contacted surface areas of the base layers <NUM>, <NUM>, <NUM>, <NUM>. In an embodiment, the semiconductor material of the emitters <NUM>, <NUM>, <NUM>, <NUM> may be doped to have the same conductivity type as the wells <NUM>, <NUM> and an opposite conductivity type from the base layers <NUM>, <NUM>, <NUM>, <NUM>. In an embodiment, the semiconductor material of the emitters <NUM>, <NUM>, <NUM>, <NUM> may be doped (e.g., heavily doped) with a concentration of an n-type dopant (e.g., arsenic or phosphorus) such that the emitters <NUM>, <NUM>, <NUM>, <NUM> have n-type conductivity.

Spacers <NUM> may be positioned between the alignment structures <NUM> and the emitters <NUM>, <NUM>, <NUM>, <NUM>. The spacers <NUM> may be formed on the alignment structures <NUM>, before forming the emitters <NUM>, <NUM>, <NUM>, <NUM>, by depositing a layer comprised of a dielectric material, such as silicon nitride, that is an electrical insulator and etching the deposited layer with an anisotropic etching process.

The structure <NUM> may be formed in a BiCMOS process with a minimal number of added masks. For example, the formation of the emitters <NUM>, <NUM>, <NUM>, <NUM> may be shared with the formation of raised sources and drains of field-effect transistors formed on the same chip as the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM>. The bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM>, which have a vertical arrangement of p-n junctions, can be formed with a more compact size than field-effect transistors, which may permit downward scaling in the dimensions of an associated resistive random-access memory device due to the elimination of field-effect transistors as access transistors.

With reference to <FIG>, <FIG> in which like reference numerals refer to like features in <FIG> and at a fabrication stage subsequent to <FIG>, an interconnect structure may be formed over the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM>. The interconnect structure may include dielectric layers <NUM>, <NUM>, <NUM> arranged in a layer stack defining multiple metallization levels. The dielectric layers <NUM>, <NUM>, <NUM> may be comprised of a dielectric material, such as silicon dioxide or a low-k dielectric material, that is an electrical insulator.

Resistive memory elements <NUM>, <NUM>, <NUM>, <NUM> may be formed as representative non-volatile memory elements in the interconnect structure. The resistive memory elements <NUM>, <NUM>, <NUM>, <NUM> are respectively coupled to the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM> to define different bitcells of the resistive random-access memory device, and the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM> provide access transistors for accessing the bitcells. The well <NUM> may define a word line of the resistive random-access memory device for accessing the bipolar junction transistors <NUM>, <NUM>, and the well <NUM> may define another word line of the resistive random-access memory device for accessing the bipolar junction transistors <NUM>, <NUM>. The wells <NUM>, <NUM> may be connected by a bus to peripheral circuits that include, for example, word line drivers. The base lines <NUM>, <NUM> may define bit lines of the resistive random-access memory device. The base lines <NUM>, <NUM> may be connected by a bus to peripheral circuits that include, for example, bit line drivers, a multiplexer, and a sense amplifier. The bit lines defined by the base lines <NUM>, <NUM> may be aligned orthogonal to the word lines defined by the wells <NUM>, <NUM>, which enables connections to be established to the bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM> at edges of the array for reading, writing, and erasing the resistive memory elements <NUM>, <NUM>, <NUM>, <NUM>.

The resistive memory elements <NUM>, <NUM>, <NUM>, <NUM> may arranged in an array that is characterized by rows and columns and that may be spatially coordinated with the array of bipolar junction transistors <NUM>, <NUM>, <NUM>, <NUM>. Each of the resistive memory elements <NUM>, <NUM>, <NUM>, <NUM> includes a bottom electrode <NUM>, a top electrode <NUM>, and a switching layer <NUM> positioned between the bottom electrode <NUM> and the top electrode <NUM>. The bottom electrodes <NUM> may define respective cathodes of the resistive memory elements <NUM>, <NUM>, <NUM>, <NUM>, and the top electrodes <NUM> may define respective anodes of the resistive memory elements <NUM>, <NUM>, <NUM>, <NUM>. Each bottom electrode <NUM> comprised of a metal, such as tantalum, titanium nitride, tantalum nitride, or a combination thereof. Each switching layer <NUM> may be comprised of a metal oxide, such as hafnium oxide, magnesium oxide, tantalum oxide, titanium oxide, or aluminum oxide, or a dielectric material, such as silicon nitride or silicon dioxide. Each top electrode <NUM> may be comprised of a metal, such as tungsten, titanium nitride, tantalum nitride, or platinum. The interconnect structure may include vertical interconnections <NUM> defined by a stack of contacts, via plugs, and metal features that physically and electrically connect the emitter <NUM> of the bipolar junction transistor <NUM> to the bottom electrode <NUM> of the resistive memory element <NUM>, the emitter <NUM> of the bipolar junction transistor <NUM> to the bottom electrode <NUM> of the resistive memory element <NUM>, the emitter <NUM> of the bipolar junction transistor <NUM> to the bottom electrode <NUM> of the resistive memory element <NUM>, and the emitter <NUM> of the bipolar junction transistor <NUM> to the bottom electrode <NUM> of the resistive memory element <NUM>.

The structure <NUM> for the resistive random-access memory device may be expanded to include additional bipolar junction transistors and additional resistive memory elements. In that regard, the expanded array may include additional wells arranged adjacent to the wells <NUM>, <NUM>, additional base lines arranged adjacent to the base lines <NUM>, <NUM>, and additional emitters at the intersections of the additional base lines and additional wells. The number of resistive memory elements in the expanded array may be increased commensurate with the increased number of bipolar junction transistors. In an alternative embodiment, the resistive memory elements <NUM>, <NUM>, <NUM>, <NUM> may be replaced by a different non-volatile memory elements, such as magnetoresistive memory elements.

With reference to <FIG> and in accordance with alternative embodiments of the invention, trench isolation regions <NUM> may be formed in the spaces between the wells <NUM>, <NUM>. The trench isolation regions <NUM> may extend to a greater depth in the substrate <NUM> than the wells <NUM>, <NUM>. The trench isolation regions <NUM>, which are comprised of a dielectric material, such as silicon dioxide, may be formed along with the trench isolation regions <NUM>. One of the trench isolation regions <NUM> is positioned in a lateral direction between the well <NUM> and the well <NUM> to electrically isolate the well <NUM> from the well <NUM>.

The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.

References herein to terms modified by language of approximation, such as "about", "approximately", and "substantially", are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of +/- <NUM>% of the stated value(s).

References herein to terms such as "vertical", "horizontal", etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term "horizontal" as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction in the frame of reference perpendicular to the horizontal, as just defined. The term "lateral" refers to a direction in the frame of reference within the horizontal plane.

A feature "connected" or "coupled" to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to or with another feature if intervening features are absent. A feature may be "indirectly connected" or "indirectly coupled" to or with another feature if at least one intervening feature is present. A feature "on" or "contacting" another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be "directly on" or in "direct contact" with another feature if intervening features are absent. A feature may be "indirectly on" or in "indirect contact" with another feature if at least one intervening feature is present. Different features may "overlap" if a feature extends over, and covers a part of, another feature.

Claim 1:
A structure comprising:
a semiconductor layer (<NUM>) including a first section;
a substrate (<NUM>);
a dielectric layer (<NUM>) disposed between the semiconductor layer (<NUM>) and the substrate (<NUM>); and
a first bipolar junction transistor (<NUM>) including a first collector in the substrate (<NUM>), a first emitter (<NUM>), and a first base layer (<NUM>) positioned between the first collector and the first emitter (<NUM>), the first base layer (<NUM>) extending through the dielectric layer (<NUM>) from the first emitter (<NUM>) to the first collector; and
a second bipolar junction transistor (<NUM>) including a second collector in the substrate (<NUM>), a second emitter (<NUM>), and a second base layer (<NUM>) positioned between the second collector and the second emitter (<NUM>), the second base layer (<NUM>) extending through the dielectric layer (<NUM>) from the second emitter (<NUM>) to the second collector, and the second base layer (<NUM>) connected to the first base layer (<NUM>) by the first section of the semiconductor layer (<NUM>) to define a first base line (<NUM>),
wherein the first collector is a portion of a first well (<NUM>) in the substrate (<NUM>), and the second collector is a portion of a second well (<NUM>) in the substrate (<NUM>).