Patent Description:
Time-sensitive networking (TSN) is a set of standards which define mechanisms for transmitting time-sensitive data over Ethernet networks. One of these standards, IEEE <NUM> Qbv-<NUM> entitled "Enhancements for Scheduled Traffic", specifies time-aware queue-draining procedures that enable nodes, such as bridges and end stations, to schedule transmission of frames based on IEEE <NUM>. 1AS timing, according to a common time in the whole network. Virtual Local Area Network (VLAN) priority values are used to enable simultaneous support of scheduled traffic, credit-based shaper (CBS) traffic and other bridged traffic over Local Area Networks (LANs). It defines a scheduling scheme involving reservation of time windows for different types of streams.

<FIG> schematically illustrates transmission selection using a time-aware shaper (TAS) defined in IEEE <NUM> Qbv-<NUM> for a set of eight queues having different traffic classes. The transmission gates (herein simply referred to as "gates") are used to control the transmission of frames in each traffic class: when a gate is open, frames in a traffic class can be transmitted and when the gate is closed, frames in that traffic class are blocked. The gates are controlled by a programmable common gate control list which specifies which traffic queue is permitted to transmit at a given point in time within a cycle.

<FIG> schematically illustrates a hardware implementation of an Ethernet controller which includes queues, gates controlled by a gate control list in accordance with IEEE <NUM> Qbv-<NUM>, credit-based shaping logic and prioritised transmission selection logic. The gate control list and corresponding logic for controlling gate list execution can be implemented using registers and hardware logic.

As the gate control list becomes longer, significant computational effort is required to calculate the next gate-close event time. When an application employs unfavourable repetition periods, for example, many short overlapping gate open times, then this can result in very long lists.

<FIG> illustrates a very simple example of gate control involving three gates whose individual and collective repetition patterns are straightforward. Gate repetition is the time after which behaviour of a gate repeats. TAS cycle time is the smallest multiple of all gate individual repetition rates. Gate <NUM> is open for time t1, is closed for times t2 and t3, open for time t4, and closed for times t5 and t6. Gate <NUM> is closed for time t1, open for time t2, closed for times t3 and t4, open for time t5 and closed for time t6. Gate <NUM> open for times t1 and t2, open for time t3, closed during time t4 and open for times t5 and t6. As illustrated, the common gate control list has six entries.

<FIG> illustrates a more complicated (but still quite simple) example of gate control involving three gates. The example still involves the same number of gate-open and gate-close events as that shown in <FIG>, but where the events are not aligned so well. In particular, there are overlaps between gates <NUM> and gate <NUM> being open and gates <NUM> and <NUM> being open. As illustrated, the common gate control list now has eleven entries.

These two simple examples help show how the common gate control list can become very long.

Moreover, even for well-aligned gate-open and gate-close events, such as that shown in <FIG>, the lists can still become very long. For example, if a frame size is <NUM> and repetition time is either <NUM> and <NUM>, then this may require <NUM> entries in the table (i.e., <NUM> × lowest common multiple of <NUM> and <NUM>). If an application requires repetition rates with inconvenient periods, such as <NUM>, <NUM>, and <NUM>, then <NUM> entries may be required (i.e., <NUM> × lowest common multiple of <NUM>, <NUM> and <NUM>).

There is also another aspect to time-aware shaping that can make gate control more complicated.

A time-aware shaper is defined such that a gate can only transmit a frame associated for its queue if there is sufficient time, i.e., time between a gate-start event and a gate-end event. This imposes a requirement for the gate to know the timing of the gate-end event to calculate whether is sufficient time available to transmit the entirety of the frame before the next gate-close event. The common gate control list is not particularly suited to achieve this.

While software-based control can accommodate complex cycles, and calculate gate open times, it is more difficult and expensive to realise in hardware (i.e., using registers and fixed logic). Therefore, when there is a large spread of gate-open event and gate-close event times, distributed across many entries, there is a need to determine an accumulated time for consecutive list entries with same gate-open and gate-close event times. This requires more logic and/or, if the list is stored RAM, time consuming to compute. One solution is to limit the minimum slot size to the maximum size of frame, but this is unacceptable in many applications.

Ideally, a hardware-implemented time-aware shaper should be able to handle many patterns of gate-open and gate-close events as possible involving a wide range of overlaps and so allow the time-aware shaper to be used in as many applications as possible without application-specific modification or adaptation.

<NPL> describes fog nodes interconnected via Time-Sensitive Networking (TSN) in which frames are transmitted using periodic flows. In a switch, Time Aware Shaper (TAS) controls a gate for each queue and queued frames are only eligible for transmission if the associated gate is open and a Gate-Control List (GCL) for each egress port defines when queue gates are open and closed. The GCLs can define a deterministic schedule of when to forward critical frames on links. Because of the periodic nature of flows, the GCLs have a certain cycle time after which they start over from the beginning. Consequently, the corresponding schedule repeats after this cycle duration, denoted the hyperperiod. The hyperperiod is the Least Common Multiple (LCM) of all the flow periods.

<NPL> describes an Electric/Electronic (E/E) Architecture which employs Time-Sensitive Networking (TSN).

According to a first aspect of the present invention there is provided a network device for time-sensitive networking comprising a set of queues and a time-aware shaper which comprises a set of transmission gates, a set of gate controllers and gate control instructions. The gate control instructions comprise a set of individual queue gate lists, each individual queue gate list configured to control a respective gate, each gate corresponding to a queue in the set of queues. Each individual gate control list comprising: a sequence of entries beginning with an initial entry (10i) set to empty, and followed by a first entry for the respective gate; each subsequent entry comprising: a control field which specifies a gate state of either open or closed for the respective gate; and an accumulated duration of time comprising one or more timeslots for the gate state, wherein, at least one entry in the sequence of entries comprises a plurality of timeslots, and wherein when the first and last gate states are the same, each entry in the sequence of entries is moved by one entry position such that the first entry becomes the initial entry and the duration of the last entry is modified by adding the duration that was specified in the first entry; and each gate controller of the set of gate controllers is configured to read an individual gate control list, to generate a gate control signal and to issue the gate control signal to a respective gate, wherein each gate controller is configured, in a first cycle, to read each entry in the sequence of entries starting from the initial entry and to toggle the state of the gate in response to reading each entry and, in a second, subsequent cycle, to read entries in the sequence starting from the first entry and to toggle the state of the gate in response to reading each entry.

Using individual queue gate lists (as opposed to a common gate control list) can make open time calculation easier, simplify gate control and can reduce the number of entries.

An entry in the sequence of entries may include a control field which indicates end of list. A registry may be provided with includes the number of entries (or "length of list").

The network device may further comprise configuration data associated with each individual queue gate list. The individual queue gate list and the configuration data may be stored in the same location, for example, a special function register or memory.

The network device may further comprise a data handler for allocating data to the set of queues. The network device may further comprise a media access controller. The network device may further comprise transmission selection logic.

The network device is preferably an Ethernet controller. The network device is preferably implemented in hardware.

According to a second aspect of the present invention there is provided a monolithic integrated circuit comprising the network device.

The monolithic integrated circuit may further comprise at least one central processing unit. The monolithic integrated circuit may be a microcontroller or a system-on-a-chip (SoC). The network device may be a peripheral module of a microcontroller or SoC. The monolithic integrated circuit may further comprise random-access memory. The monolithic integrated circuit may further comprise a routing engine and so provide, for example, a bridge (or "switch"). The monolithic integrated circuit may further comprise a physical layer transceiver (i.e., PHY). The monolithic integrated circuit may further comprise an interface to an external (i.e., off-chip) physical layer transceiver. The transceiver may comprise a media-independent interface (Mil) module.

According to a third aspect of the present invention there is provided an end station comprising the network device of the first aspect of the invention or the monolithic integrated circuit of second aspect of the invention.

According to a fourth aspect of the present invention there is provided a switch or bridge comprising the network device of the first aspect of the invention or the monolithic integrated circuit of second aspect of the invention.

According to a fifth aspect of the present invention there is provided a network comprising a bus system and at least one network device of the first aspect of the invention, at least one monolithic integrated circuit of the second aspect of the invention, at least one end station of the third aspect of the invention and/or at least one switch of the fourth aspect of the invention in wired communication with the bus system.

According to a sixth aspect of the present invention there is provided a motor vehicle comprising at least one network device of the first aspect of the invention, at least one monolithic integrated circuit of the second aspect of the invention, at least one end station of the third aspect of the invention and/or at least one switch of the fourth aspect of the invention.

The motor vehicle may be a motorcycle, an automobile (sometimes referred to as a "car"), a minibus, a bus, a truck or lorry. The motor vehicle may be powered by an internal combustion engine and/or one or more electric motors.

According to a seventh aspect of the present invention there is provided a system comprising at least one network device of the first aspect of the invention, at least one monolithic integrated circuit of the second aspect of the invention, at least one end station of the third aspect of the invention and/or at least one switch of the fourth aspect of the invention.

The system may be an industrial system, such as a plant. The plant may include one or more robots and/or controllers for the robots connected by a time-sensitive network.

According to an eighth aspect of the present invention there is provided a method. The method comprises receiving data describing operation of a set of gates (or "gate operation database"), converting the data into a set of individual gate control lists each individual gate control list configured to control a respective gate and which comprises a sequence of entries (<NUM>) beginning with an initial entry (10i) set to empty, and followed by a first entry, each subsequent entry comprising a control field (<NUM>) which specifies a gate state of either open or closed for the respective gate, and an accumulated duration of time comprising one or more timeslots for the gate state, wherein, at least one entry in the sequence of entries comprises a plurality of timeslots, and wherein when the first and last gate states are the same, each entry in the sequence of entries is moved forward by one entry position such that the first entry becomes the initial entry and the duration of the last entry is modified by adding the duration that was specified in the first entry; writing the set of individual gate control lists into memory or set of registers; in a first cycle, reading each entry in the sequence of entries starting from the initial entry and toggling the state of the gate in response to reading each entry and, in a second, subsequent cycle, reading entries in the sequence starting from the first entry and toggling the state of the gate in response to reading each entry; generating a gate control signal (<NUM>) for each entry read; and issuing the gate control signal to the gate.

According to a ninth aspect of the present invention there is provided a computer program which, when executed by a processor, causes the processor to perform the method of seventh aspect of the present invention.

According to a tenth aspect of the present invention there is provided a computer program product comprising a computer-readable medium (for example, a non-transitory computer readable medium) carrying or storing the computer program of the ninth aspect of the present invention.

The method is preferably a hardware-implemented method.

Certain embodiments of the present invention will now be described, by way of example, with reference to <FIG> of the accompanying drawings, in which:.

Referring to <FIG>, a hardware-implemented network device <NUM> supporting time-sensitive networking (TSN) in accordance with IEEE <NUM> Qbv -<NUM> is shown. The device <NUM> is comprises a set of queues <NUM> and a time-aware shaper <NUM> which complies with IEEE <NUM> Qbv -<NUM>. The time-aware shaper <NUM> includes, among other things, a set of transmission gates <NUM> and gate control instructions <NUM>. The gate control instructions <NUM> control transmission of data frames <NUM> by the transmission gates <NUM>. Thus, the time-aware shaper <NUM> allows transmission of data frames <NUM> from a queue <NUM> to be scheduled.

The gate control instructions <NUM> comprises a set of individual gate control lists <NUM> (or "queue gate lists" or "QGLs"), each individual gate control list <NUM> arranged to control a respective gate <NUM>. Each individual gate control list <NUM> includes a series or sequence of one or more entries <NUM> which may specify an open time or close time <NUM> (<FIG>). Here, each time <NUM> indicates the time (or "duration") for which a gate is open or closed. Each individual gate control list <NUM> can have a different number of entries <NUM>. In other words, the individual gate control lists <NUM> do not need to have the same number of entries <NUM>.

Each individual gate control list <NUM> can be small (for example, containing between <NUM> to <NUM> entries) since each list <NUM> need only handle repetition of one gate <NUM>. Moreover, a set of individual gate control lists <NUM> can handle gates <NUM> whose open times are not well aligned, for example, involving overlapping open gate times, where the identity of the overlapping gates can vary throughout the cycle and the overlapping open gate times vary in duration. Furthermore, control using individual gate control lists <NUM> can be simpler and quicker than using a common gate control list since open and close times are predetermined and can be simply read out from each list <NUM>, rather than being computed on-the-fly during operation.

Referring to <FIG>, a simple example of time-aware shaper gate control is shown. This pattern of gate states is the same as that shown in <FIG>.

<FIG> also shows a common gate control list for providing gate control and a set of three individual gate control lists <NUM> for achieving the same outcome as the common gate control list.

An individual gate control list <NUM> for gate <NUM> includes two entries <NUM>, namely a first entry <NUM> indicating that the gate <NUM> should be open for time t1 and a second entry <NUM> indicating that the gate should be closed for time t2+t3. An individual gate control list <NUM> for gate <NUM> includes three entries <NUM>, namely a first entry <NUM> indicating that the gate <NUM> should be closed for time t1 and a second entry <NUM> indicating that the gate should be open for time t2 and a third entry <NUM> indicating that the gate should be closed for time t3. An individual gate control list <NUM> for gate <NUM> includes four entries <NUM>, namely a first entry <NUM> indicating that the gate <NUM> should be closed for time t1+t2 and a second entry <NUM> indicating that the gate should be open for time t3, a third entry <NUM> indicating that the gate should be closed for time t4 and a fourth entry <NUM> indicating that the gate should be open for time t5+t6.

Referring to <FIG>, a more complex example of time-aware shaper gate control is shown. This pattern of gate states is the same as that shown in <FIG>.

An individual gate control list <NUM> for gate <NUM> includes two entries <NUM>, namely a first entry <NUM> indicating that the gate <NUM> should be open for time t1+t2 and a second entry <NUM> indicating that the gate should be closed for time t3+t4+t5+t6. An individual gate control list <NUM> for gate <NUM> includes three entries, namely a first entry <NUM> indicating that the gate <NUM> should be closed for time t1 and a second entry <NUM> indicating that the gate should be closed for time t2+t3+t4 and a third entry <NUM> indicating that the gate should be closed for time t5+t6. An individual gate control list <NUM> for gate <NUM> includes four entries <NUM>, namely a first entry <NUM> indicating that the gate <NUM> should be closed for time t1+t2+t3, a second entry <NUM> indicating that the gate should be open for time t4+t5, a third entry <NUM> indicating that the gate should be closed for time t6+t7+t8 and a fourth entry <NUM> indicating that the gate should be open for time t9+t10+t11.

From the example shown in <FIG>, it is clear that the individual gate control lists <NUM> together can control the gates using fewer entries <NUM> than a common gate control list.

Comparing the examples shown in <FIG> and <FIG>, it is also clear that a slight increase in complexity of the gate state pattern to include overlapping open gates does not increase the number of entries <NUM> in the individual gate control lists <NUM> or at least does not increase the number of entries <NUM> compared to a common gate control list.

The use of individual gate control lists <NUM> can take advantage of the fact that the state of the gate alternates (or "toggles") between open and closed states.

One approach to gate control is simply to go through an individual gate control list <NUM> and, having gone through the list, to start going through the list from the start of the list. However, if the first and last entries in a list are in same state, i.e., both open or both closed, then this can interfere with toggling. It can result in inversion of gate state and so requires hardware and/or software to check the states of the first and last entries and, if necessary, to prevent toggling after the last entry or take other appropriate action.

Referring to <FIG>, to address this, the individual gate control lists <NUM> can include an initial entry (or "one-time entry") <NUM>i which is read once when an individual gate control list <NUM> is read for the first time. Thus, in cases where the first and last entries might otherwise be in the same state, when preparing the list (before operation), the list <NUM> is adapted such that the first entry <NUM> becomes an initial entry <NUM>i and the duration of the last entry <NUM> is modified by adding the duration that was specified in the first entry <NUM>.

For example, a first entry <NUM> indicates that gate <NUM> is open for t1 and a last entry <NUM> indicates that gate <NUM> is open for t3. The initial entry <NUM>i is set to indicate that gate <NUM> is closed for t1, then the following entries are shifted such that entry <NUM> becomes entry o, entry <NUM> becomes entry <NUM> and the last entry <NUM> is modified by adding the time t1, i.e., to become t1+t3.

In cases where the first and last entries are in different states, no such adaptation of the list is required.

Other algorithms for handling lists where the first and last entries are the same can be used. For example, it is possible to have an initial entry where the first and last entries are not same. For example, it is possible to append the first entry of the list to the end of list.

Referring to <FIG>, an integrated circuit <NUM> supporting time-sensitive networking (TSN) is shown. The integrated circuit <NUM> takes the form of a microcontroller, system-on-a-chip or other similar microprocessor-based system. However, the integrated circuit <NUM> need not include a microprocessor and may, for example, include an interface to a microprocessor (not shown) on a different chip (not shown).

The integrated circuit <NUM> includes a CPU sub-system <NUM> which includes at least one CPU <NUM>, user RAM <NUM> (which may also be referred to as system RAM or simply RAM), and a TSN-compliant network device <NUM> in the form of an Ethernet controller interconnected by a bus system <NUM>. The integrated circuit <NUM> may include a routing engine (not shown) for providing Ethernet switch functionality. The integrated circuit <NUM> may provide Ethernet end station functionality. The integrated circuit <NUM> may include other peripheral modules such as a timer, an interrupt controller and other types of communications controller. The integrated circuit <NUM> may also include physical layer (PHY) transceiver module(s) (not shown). In this case, however, external PHY transceiver IC (not shown) is used.

As will be explained in more detail hereinafter, a CPU <NUM> loads and executes application software <NUM> for transforming time-aware shaper control data <NUM> into individual gate control list data <NUM>. The control data <NUM> takes the form of management information base (MIB) and is stored, for example, in the user RAM <NUM>. The user RAM <NUM> may also store data <NUM>, for example in the form of frames, for transmission by the Ethernet controller <NUM>.

Referring also to <FIG>, the TSN-compliant Ethernet controller <NUM> is shown in greater detail.

The Ethernet controller <NUM> includes a receive path (not shown) and a transmit path <NUM> which includes a transmit handler <NUM>, a set of N transmit queues <NUM> (where N ≥ <NUM>, e.g., <NUM>), transmission selection and traffic shaping logic <NUM> which includes a set of N gates <NUM> and transmission media access controller (MAC) <NUM>.

In the case of an end station, the transmit handler <NUM> fetches frames <NUM> from user RAM <NUM> or other memory or buffer which may receive the data from a source, such as digital camera (not shown). In the case of a switch, the transmit handler <NUM> receives frames <NUM> from the routing engine (not shown).

The transmission selection and traffic shaping logic <NUM> may implement credit-based shaping (CBS), strict priority round robin (SRR), round robin (RR), and/or time-aware shaping (TAS).

Individual gate control lists <NUM> are stored either in special function register (SFRs) <NUM> or in RAM (not shown) in the Ethernet controller <NUM>. A set of shadow individual gate control lists <NUM>' and shadow configuration data (not shown) may be provided to enable dynamic TAS schedule reconfiguration. Different lists <NUM>, <NUM>' and configuration data can be written to and accessed using respective base addresses.

The Ethernet controller <NUM> also includes a set of gate controllers <NUM>, each controller <NUM> arranged to read a respective individual gate control list <NUM> and issue a control signal <NUM> to a corresponding gate <NUM>. The gate controllers <NUM> implement a set of state machines (not shown) including a cycle timer state machine (not shown), a list execute state machine (not shown) and a list configuration state machine (not shown) as specified in Clause <NUM>. <NUM> of IEEE <NUM> Qbv -<NUM>.

The control signal <NUM> may be a time, for example, in microseconds. The control signal <NUM> may be a remaining time, for example, in microseconds, before the gate changes state, or before the gate opens or closes (in the case that the state is defined). The control signal <NUM> be expressed in terms of number of bytes before the gate changes state, or before the gate opens or closes.

Gate close time is used if the time aware shaper supports implicit guard band. This is hardware support to ensure that frames do not cross gate close time. In some cases, this can be monitored and controlled by application software.

Referring also to <FIG>, an individual gate control list <NUM> and associated configuration data <NUM>, <NUM> is shown. The configuration data <NUM>, <NUM> can include configuration data <NUM> which is specific to a respective individual gate control list <NUM> and configuration data <NUM> which shared amongst the individual gate control list <NUM>. A shadow individual gate control list <NUM>' has the same structure. Likewise, a shadow configuration data (not shown) has the same structure.

The individual gate control list <NUM> includes M entries <NUM> (where M ≥ <NUM>), each entry comprising a gate time <NUM> and control data <NUM>. The control data <NUM> can indicate a gate state, i.e., open or closed, and/or whether the entry is the end of the list (EOL). Closed and open may be represented by logical '<NUM>' and '<NUM>' respectively. End of list may be represented by '<NUM>'.

The individual gate control list <NUM> or the configuration data <NUM> may include a flag or field <NUM> indicating an initial start state i.e., open or closed.

The configuration data <NUM> may include a gate list offset <NUM> which can be used to access entry <NUM> (i.e., the first entry <NUM> after the initial entry <NUM>i), and an optional gate list length <NUM> (which may be omitted if the last entry is masked in control field <NUM> of list).

As part of shared configuration data <NUM>, a flag <NUM> for signaling re-configuration, e.g. switching to an alternative list, i.e., to the shadow list <NUM>' or vice versa for all queues and a cycle start time <NUM> can be specified. The switch to an alternative list can be triggered in hardware or by software.

Referring to <FIG>, the start time <NUM> is an absolute time at which a cycle of gate operations for a given list <NUM>, <NUM>' begins.

The cycle start time <NUM> is not directly defined in IEEE <NUM> Qbv -<NUM> ibid. The start time <NUM> is a pre-calculated number which may be calculated by software (i.e., by application software running on the CPU) and then written to hardware (i.e. to the cyrcle start time field <NUM> in the SFR <NUM>). Clause <NUM>. <NUM> of IEEE <NUM> Qbv -<NUM> specifies a CycleStartTime. Software can calculate the CycleStartTime and provide the result to hardware. However, the software may be too slow to provide the result in time and, thus, may end up providing a cycle start time in the past. Therefore, a margin allowing for a delay in software execution may be needed to avoid or prevent this from happening. Hardware can observe times in the past. However, the hardware can be limited such that it only accepts a cycle start time in a given window in the future (for example to a two-second window). In this case, software handles bigger offsets using a software timer (not shown).

The cycle start time <NUM> defines the start of a first cycle. The TAS cycle time is defined by the sum of the times in the common gate control list. Thus, the sum should equal OperCycleTime defined in IEEE <NUM> Qbv-<NUM>. Thus, before converting a common gate control list in MIB <NUM> (<FIG>) into individual gate control lists (step <NUM> in <FIG>), the common gate control list may be shortened or lengthen to meet this requirement. For example, an entry in the common gate control list having a long period (say, <NUM>) may be discarded and replaced by one with a shorter period (say, <NUM>). However, the sum of the times in the common gate control list is likely to be equal to OperCycleTime and so this may not be required.

The reconfiguration flag <NUM> can be triggered by a timer (not shown) in hardware. The timer may set a time, for example, in the last slot of the common gate control list before the ConfigChangeTime (see clause <NUM>.

A margin allowing for a delay in calculating a configuration change time may be included, similar to that used for the cycle start time.

Examples of individual gate control lists <NUM> are shown in <FIG>.

<FIG> shows an individual gate control list <NUM> for a toggling gate.

An initial entry <NUM>i is found using the base address without applying the offset <NUM> (<FIG>). The initial entry <NUM>i defines an initial gate state and an initial time. After the initial entry <NUM>i, the entries <NUM> come in pairs <NUM>. The end of the list <NUM> is signaled in the control data <NUM>. The cycle starts again with a second entry <NUM>.

<FIG> shows an individual gate control list <NUM> for a gate whose state does not change.

In this case, the initial entry <NUM>i is marked as the end of list. This is taken as indicating that the gate does not toggle and that its state does not change during a cycle.

Referring to <FIG>, <FIG>, <FIG> and <FIG>, the application software <NUM> reads the control data <NUM> (step S0. <NUM>) and transforms the control data <NUM> into a set of individual gate control lists <NUM> or a set of shadow gate individual control lists <NUM>' (step S0. <NUM> to S0. This can be performed before operations begin, i.e., before frame transmission begins. If shadow lists <NUM>' are available, then writing of one set of gate control lists <NUM>, <NUM>', while the another set of gate control lists <NUM>, <NUM>' is being used. As explained earlier, the application software <NUM> inspects each gate individual control list <NUM> to determine if the first and last entries are in the same state (steps S0. <NUM> & S0. If so, a new entry <NUM> is generated (step So. <NUM>), time is added from the first entry to the last entry (step S0. <NUM>) and a non-zero offset <NUM> is set (step So.

Referring to <FIG>, <FIG>, <FIG> and <FIG>, during operation in toggle mode, the gate controller <NUM> sets an initial state (step S1. <NUM>) and waits until the start time (step S1. The gate controller <NUM> goes through the list of entries <NUM> starting from the initial entry. If there is a gate state transition, then the gate controller <NUM> reads out the state and gate time (step S1. <NUM>), generates a control signal and waits the specified time (step S1. The gate controller <NUM> goes through the list of entries <NUM> (step S1. <NUM> to S1. <NUM>) reading the time (step S1. <NUM>) and generating a control signal for the gate (step S1. <NUM>) until it reaches the end of the list (step S1. At the end of list, the gate controller <NUM> checks the configuration change flag <NUM> (step S1. If the flag <NUM> is set, then the process of gate control ends and the controller <NUM> waits for a new start time (step S1. If the flag <NUM> is not set, then the controller <NUM> starts the cycle again either at the initial entry <NUM>i or at the next entry <NUM>, depending on the offset <NUM> (step S1.

The reconfiguration flag is requested in a way that reconfiguration becomes active at the end of a TAS cycle of the common gate control list. The request can be triggered either by software or by hardware based on a `reconfiguration time' or 'last cycle time'. The 'new cycle start' time defines when the TAS schedule re-starts with a new configuration. The configuration state machine (not shown) switches between active and shadow configuration. It is possible to make reuse of the SFR of the 'Cycle start time' configuration.

Time-aware shapers can be used in a variety of time-sensitive networking, such as audio/video streaming and real-time control in automotive or industrial control applications.

Referring to <FIG>, a motor vehicle <NUM> is shown in which a time-sensitive network <NUM> is deployed. The network <NUM> comprises a plurality of end stations <NUM> and bridges <NUM> interconnecting the end stations <NUM>. One or more of the end stations <NUM> and bridges <NUM> may perform transmission of data <NUM> using a time-aware shaper as defined in IEEE <NUM> Qbv using individual control gate lists as herein described.

It will be appreciated that various modifications may be made to the embodiments hereinbefore described. Such modifications may involve other features which are already known in the design, manufacture and use of time-sensitive networking systems and component parts thereof and which may be used instead of or in addition to features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment.

Toggling need not be used. Instead, each individual gate control list <NUM> may explicitly specify a gate state (i.e., open or closed) and a time.

Claim 1:
A network device (<NUM>) for time-sensitive networking comprising:
a set of queues (<NUM>); and
a time-aware shaper (<NUM>) which comprises:
a set of gates (<NUM>), a set of gate controllers (<NUM>), and
gate control instructions (<NUM>);
the gate control instructions comprise:
a set of individual gate control lists (<NUM>), each individual gate control list configured to control a respective gate, each gate corresponding to a queue in the set of queues;
characterised in that each individual gate control list comprising:
a sequence of entries (<NUM>) beginning with an initial entry (<NUM>i) set to empty, and followed by a first entry for the respective gate, each subsequent entry comprising:
a control field (<NUM>) which specifies a gate state of either open or closed for the respective gate, and an accumulated duration of time comprising one or more timeslots for the gate state, wherein, at least one entry in the sequence of entries comprises a plurality of timeslots, and wherein when the first and last gate states are the same, each entry in the sequence of entries is moved by one entry position such that the first entry becomes the initial entry and the duration of the last entry is modified by adding the duration that was specified in the first entry; and each gate controller of the set of gate controllers (<NUM>) is configured to read an individual gate control list (<NUM>), to generate a gate control signal (<NUM>) and to issue the gate control signal to a respective gate (<NUM>), wherein each gate controller is configured, in a first cycle, to read each entry in the sequence of entries starting from the initial entry and to toggle the state of the gate in response to reading each entry and, in a second, subsequent cycle, to read entries in the sequence starting from the first entry and to toggle the state of the gate in response to reading each entry.