Patent Description:
With the shrink in size of the geometric pattern in a semiconductor device, higher requirements are needed for the precision of a patterning treatment during a semiconductor process. In a process for manufacturing a semiconductor structure, factors that affect the precision of the patterning treatment include the alignment precision between a mask layer and a photomask, and the etching selectivity between the mask layer and a substrate to be etched. The greater the etching selectivity between the mask layer and the substrate, the more favorable the pattern is to be transferred to the substrate through the mask layer during the etching process. In addition, the optical properties of the mask layer itself may affect the alignment precision between the mask layer and the photomask. Background may be found in <CIT> and <CIT>.

Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial for improving the patterning precision of a substrate and an initial mask layer.

One or more embodiments are exemplarily descripted by the corresponding figures in the drawings. These exemplary descriptions do not constitute the limitation to the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the technical solutions of the embodiments of the disclosure and the technical solutions of the related art, the drawings used in the description of the embodiments will be briefly descripted herein below. Apparently, the drawings in the following description only relate to some embodiments of this disclosure. For an ordinary person skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Embodiments of the disclosure provide a method for manufacturing a semiconductor structure. On the one hand, P-type doping a semiconductor layer is beneficial to improving the optical properties of the initial mask layer, and then is beneficial to improving the alignment precision between the initial mask layer and the photomask when an irradiation alignment is subsequently performed on the initial mask layer by using the photomask. In addition, the improvement of the alignment precision between the initial mask layer and the photomask is beneficial to improving the precision of the first patterning when the first patterning treatment is subsequently performed on the initial mask layer. That is, the pattern of the photomask can be more accurately transferred to the initial mask layer, so as to form the mask layer that meets the requirements. On the other hand, the mask layer is also the P-type doped semiconductor layer, which is beneficial to reducing the etching rate of the mask layer during an etching process when the substrate is subsequently etched. As a result, in the step of performing the second patterning on the substrate by taking the mask layer as the mask and using the etching process, on the premise of ensuring that the etching rate of the substrate is greater than the etching rate of the mask layer in the etching process, it is beneficial to increase the difference between the etching rate of the substrate and the etching rate of the mask layer during the etching process, which facilitates the accurate transfer of the pattern to the substrate through the mask layer, thereby improving the precision of the second patterning treatment. In this way, the patterning precision of the initial mask layer and the substrate can be improved, so that the accuracy of final transfer of the pattern in the photomask to the substrate can be increased, thereby forming a semiconductor structure with a higher dimensional precision.

The embodiments of the disclosure are described in detail below with reference to the accompanying drawings. However, an ordinary person skilled in the art can understand that in the embodiments of the disclosure, many technical details are provided in order to make readers better understand the embodiments of the disclosure. However, even without these technical details, and variations and modifications based on the following embodiments, the technical solutions claimed by the embodiments of the disclosure can be realized.

Embodiments of the disclosure provide a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure provided by the embodiments of the disclosure is described in detail below with reference to the accompanying drawings. <FIG> shows a flowchart of a method for manufacturing a semiconductor structure provided by embodiments of the disclosure. <FIG> schematically show structures corresponding to operations of a method for manufacturing a semiconductor structure provided by embodiments of the disclosure. <FIG> shows a relationship between a content of boron and an extinction coefficient of the initial mask layer in a method for manufacturing a semiconductor structure provided by embodiments of the disclosure. It should be noted that, in order to facilitate description and clearly illustrate the operations of the method for manufacturing a semiconductor structure, <FIG> schematically show partial structures of the semiconductor structure in the embodiments.

Referring to <FIG>, the method for manufacturing a semiconductor structure may include the following operations.

At S101, referring to <FIG>, a substrate <NUM> is provided.

In some embodiments, referring to <FIG>, providing the substrate <NUM> may include the following operations. A base <NUM> is provided. A stacked structure <NUM> is formed on the base <NUM>, and is configured to form a capacitor contact hole <NUM> (referring to <FIG>). Performing a second patterning treatment on the substrate <NUM> may include an operation of etching the stacked structure <NUM> by taking the mask layer <NUM> as a mask and using an etching process, so as to form the capacitor contact hole <NUM>.

In some embodiments, after forming the capacitor contact hole <NUM>, the method for manufacturing a semiconductor structure further includes an operation of forming a capacitor structure on the basis of the capacitor contact hole <NUM>. It should be noted that, a process for manufacturing the capacitor structure is not specifically limited in the embodiments of the disclosure. In an example, the base <NUM> includes a transistor structure and the capacitor contact hole <NUM> exposes the source or the drain of the transistor structure, such that the capacitor structure is contacted with and electrically connected with the source or the drain of the transistor.

It can be understood that, the capacitor structure formed subsequently by using the capacitor contact hole <NUM> generally needs to have a greater aspect ratio to ensure that the capacitor structure has a higher capacitance. Therefore, forming the stacked structure <NUM> on the substrate <NUM> on the one hand, is beneficial to increasing the depth of the capacitor structure formed subsequently in the direction from the substrate <NUM> to the stacked structure <NUM>, thereby improving the aspect ratio of the capacitor structure; on the other hand, part of film layers of the stacked structure <NUM> can be used subsequently as a support layer when the capacitor contact hole <NUM> is used to form the capacitor structure, so as to avoid a collapse of the capacitor structure with the greater aspect ratio and improve the stability of the semiconductor structure.

In some embodiments, the base <NUM> may be a silicon base, a germanium base, a silicon germanium base, a silicon carbide base, or a silicon-on-insulator base, etc..

In some embodiments, still referring to <FIG>, forming the stacked structure <NUM> may include an operation of forming a bottom support layer <NUM>, a first dielectric layer <NUM>, an intermediate support layer <NUM>, a second dielectric layer <NUM> and a top support layer <NUM> stacked in sequence on the base <NUM>.

In an example, the bottom support layer <NUM>, the intermediate support layer <NUM> and the top support layer <NUM> may have the same the materials. For example, the materials of the bottom support layer <NUM>, the intermediate support layer <NUM>, and the top support layer <NUM> may all be silicon nitride. The materials of the first dielectric layer <NUM> and the second dielectric layer <NUM> may be the same. For example, the materials of the first dielectric layer <NUM> and the second dielectric layer <NUM> may all be silicon oxide.

It should be noted that, the bottom support layer <NUM>, the intermediate support layer <NUM> and the top support layer <NUM> are shown in the same shaded manner in <FIG> and <FIG> to <FIG>, which does not mean that the bottom support layer <NUM>, the intermediate support layer <NUM> and the top support layer <NUM> have the same materials. In practical applications, the materials of the bottom support layer <NUM>, the intermediate support layer <NUM> and the top support layer <NUM> may be different.

At S102, referring to <FIG>, a semiconductor layer <NUM> is formed on the substrate <NUM>.

In some embodiments, forming the semiconductor layer <NUM> may include the following operations. Referring to <FIG>, an initial semiconductor layer <NUM> is formed on the substrate <NUM>. Referring to <FIG>, N-type doping or P-type doping is performed on the initial semiconductor layer <NUM> to transform the initial semiconductor layer <NUM> into the semiconductor layer <NUM>.

In some embodiments, the material of the initial semiconductor layer <NUM> may be silicon.

In an example, N-type doping is performed on the initial semiconductor layer <NUM>. That is, an N-type doping element is implanted into the initial semiconductor layer <NUM>. The N-type doping element may be at least one of arsenic, phosphorus or antimony.

In another example, P-type doping is performed on the initial semiconductor layer <NUM>. That is, a P-type doping element is implanted into the initial semiconductor layer <NUM>. The P-type doping element may be at least one of boron, indium or gallium.

At S103, referring to <FIG>, P-type doping is performed on the semiconductor layer <NUM> to transform the semiconductor layer <NUM> into an initial mask layer <NUM>. Performing P-type doping on the semiconductor layer <NUM> means implanting the P-type doping element into the semiconductor layer <NUM>.

In an example, P-type doping of the semiconductor layer <NUM> may be performed by implanting boron into the semiconductor layer <NUM>.

It should be noted that, for the simplicity of the illustration, <FIG> just show the substrate <NUM>, while the structure included in the substrate <NUM> is shown in <FIG>.

The material of the initial mask layer <NUM> includes a boron-silicon compound, and an atomic percent of boron atoms and silicon atoms in the boron-silicon compound is in a range of <NUM>:<NUM> to <NUM>:<NUM>.

It can be understood that, referring to <FIG>, the extinction coefficient of the boron-silicon compound decreases with the increase of the content of boron atoms in the boron-silicon compound. Therefore, increasing the content of boron atoms in the initial mask layer <NUM> is beneficial to reducing the extinction coefficient of the initial mask layer <NUM>. That is, the initial mask layer <NUM> is rendered more light-transmitting. In addition, the content of boron atoms in the initial mask layer <NUM> determines the content of boron atoms in the mask layer <NUM> formed subsequently. The content of boron atoms in the mask layer <NUM> may have influence on the etching rate of the mask layer <NUM> during the etching process for etching the substrate <NUM>. Therefore, it is necessary to comprehensively consider the influence of the content of boron atoms in the mask layer <NUM> on the extinction coefficient of the mask layer <NUM> and the etching rate of the mask layer112 during the etching process. By controlling the atomic ratio between silicon atoms and boron atoms in the borosilicate compound in the range of <NUM>:<NUM> to <NUM>:<NUM>, it is beneficial to reduce the extinction coefficient of the initial mask layer <NUM>, while reducing the etching rate of the mask layer <NUM> in the etching process for etching the substrate <NUM>.

In some embodiments, still referring to <FIG>, the extinction coefficient of the initial mask layer <NUM> may be less than <NUM>. It can be understood that, when the extinction coefficient of the initial mask layer <NUM> is less than <NUM>, the initial mask layer <NUM> has good light-transmitting. In some embodiments, the initial mask layer <NUM> and the substrate <NUM> are provided with a photolithography mark, respectively to increase the light-transmitting of the initial mask layer <NUM>, so as to facilitate that the photolithography mark of the initial mask layer <NUM> is overlapped with the lithography mark of the substrate <NUM> through the initial mask layer <NUM> in step of irradiating, achieving the alignment precision between the initial mask layer <NUM> and the substrate <NUM>. It can be understood that, the extinction coefficient of the initial mask layer <NUM> is less than <NUM>, which is beneficial to improving the alignment precision between the initial mask layer <NUM> and the substrate <NUM>, and is beneficial to forming the capacitor contact hole <NUM> at a preset position (referring to <FIG>) when performing subsequently the second patterning treatment, i.e., improving the precision of the second patterning treatment.

In some embodiments, the extinction coefficient of the initial mask layer may be in a range of <NUM> to <NUM>. According to the above analysis, when the extinction coefficient of the initial mask layer <NUM> is in the range of <NUM> to <NUM>, the extinction coefficient of the initial mask layer <NUM> is low, and under this range, the content of boron atoms in the boron-silicon compound is beneficial to reducing the etching rate of the mask layer <NUM> in the etching process for etching the substrate <NUM>. Therefore, while ensuring that the initial mask layer <NUM> has a low the extinction coefficient, the ratio of the etching rate of the substrate to the etching rate of the mask layer <NUM> in the same etching process is increased, thereby improving the precision of the first patterning treatment and the second patterning treatment.

In one example, the material of the initial mask layer <NUM> is the boron-silicon compound, and the atomic percent of boron atoms and silicon atoms in the boron-silicon compound is <NUM>:<NUM>, and the extinction coefficient of the initial mask layer <NUM> is <NUM>.

In some embodiments, the initial mask layer <NUM> is provided with the photolithography mark. In the operation of performing the first patterning treatment on the initial mask layer <NUM> by using a first etching process, the method for manufacturing a semiconductor structure further includes an operation of providing a photomask with an opening and a photolithography mark. The photolithography mark of the photomask is overlapped with the photolithography mark of the initial mask layer <NUM>.

It can be understood that, when the extinction coefficient of initial mask layer <NUM> is less than <NUM>, the initial mask layer <NUM> has good light-transmitting, which is beneficial for an operator to observe the photolithography mark of the initial mask layer <NUM> and the photolithography mark of the photomask, thereby facilitating the alignment between the photolithography mark of the initial mask layer <NUM> and the photolithography mark of the photomask. That is, the orthographic projection of the photolithography mark of the initial mask layer <NUM> on the substrate <NUM> is overlapped with the orthographic projection of the photolithography mark of the photomask on the substrate <NUM>. In this way, an opening <NUM> is aligned with part of the initial mask layer <NUM> that needs to be etched, thereby improving the precision of the first patterning treatment on the initial mask layer <NUM>.

In some embodiments, the initial mask layer <NUM> has a thickness in a range of <NUM> to <NUM> along a direction X from the substrate <NUM> to the initial mask layer <NUM>.

It can be seen from the foregoing description that, the initial mask layer <NUM> is formed by the P-type doped semiconductor layer, and the mask layer <NUM> formed by the initial mask layer <NUM> upon the first patterning treatment subsequently is also formed by the P-type doped semiconductor layer. In this way, it is beneficial to reduce the etching rate of the mask layer <NUM> in the etching process for etching subsequently the substrate <NUM>. It can be understood that, in order to increase the capacitance of the capacitor structure formed subsequently, the substrate <NUM> has a greater thickness along the direction X from the substrate <NUM> to the initial mask layer <NUM>, so the etching time required for the second patterning treatment on the substrate <NUM> is relatively long. Under this situation, the mask layer <NUM> used as a mask may also be consumed due to etching in the step of the second patterning treatment. Therefore, reducing the etching rate of the mask layer <NUM> in the etching process is beneficial to reducing the etching thickness of the mask layer <NUM> in the step of the second patterning treatment.

It can be understood that, referring to <FIG>, on the premise of reducing the etching thickness of the mask layer <NUM> in the step of the second patterning treatment, the initial mask layer <NUM> may have a lower thickness in the direction X when forming, and then the mask layer <NUM> formed subsequently may also have a lower thickness in the direction X. In this way, the aspect ratio of the opening <NUM> of the mask layer <NUM> can be reduced, so that etching materials used in the etching process is more prone to etch the substrate <NUM> via the opening <NUM>. Therefore, in the step of the second patterning treatment, the aspect ratio of the formed trench can be reduced, so that the second patterning treatment on the substrate <NUM> by the etching process can be improved, thereby increasing the precision of the second patterning treatment. It should be noted that, the final morphology of the trench formed in the step of the second patterning treatment is composed of the opening <NUM> of the mask layer <NUM> and the capacitor contact hole <NUM> of the substrate <NUM>.

In an example, when performing a second patterning treatment on a substrate <NUM> having the same size, in order to form a capacitor contact hole <NUM> with the same size, an initial mask layer formed by a semiconductor layer without P-type doping is required to have the thickness of <NUM>. In contrast, the thickness of the initial mask layer <NUM> formed by the P-type doped semiconductor layer may be <NUM> in the embodiment of the disclosure. It can be seen that, the initial mask layer <NUM> formed by P-type doped semiconductor layer can reduce the etching rate of the mask layer <NUM> in the subsequent etching process for etching the substrate <NUM>, which facilitates to reduce the thickness of the initial mask layer <NUM> to be formed, thereby reducing the difficulty and improving the precision of second patterning treatment.

At S104, referring to <FIG>, <FIG> and <FIG>, a first patterning treatment is performed on the initial mask layer <NUM> to form a mask layer <NUM> with an opening <NUM>.

It can be understood that, the step of performing the first patterning on the initial mask layer <NUM> further includes the following operations. A photomask with an opening is provided. The initial mask layer <NUM> is irradiated through the photomask to form the mask layer <NUM> with the opening <NUM>. Performing P-type doping on the semiconductor layer is beneficial to reducing the extinction coefficient of the initial mask layer <NUM>, which improves the alignment precision between the initial mask layer <NUM> and the photomask, thereby improving the precision of the first patterning treatment. That is, the pattern of the photomask is more accurately transferred to the initial mask layer <NUM>, to form the mask layer <NUM> that meets the requirements. It should be noted that the pattern of the photomask refers to the pattern formed by openings of the photomask.

In some embodiments, after forming the initial mask layer <NUM> on the substrate <NUM> and prior to performing the first patterning treatment on the initial mask layer <NUM>, the method for manufacturing a semiconductor structure may further include the following operations.

Referring to <FIG>, a first mask layer <NUM> and a second mask layer <NUM> stacked on a side, away from the substrate <NUM> of the initial mask layer <NUM> are formed in sequence. The second mask layer <NUM> includes a first region <NUM> and a second region <NUM> adjacent to each other. The second region <NUM> is used to form the opening <NUM> via a subsequent etching.

In an example, the material of the first mask layer <NUM> may be silicon oxide, and the material of the second mask layer <NUM> may be amorphous carbon.

It should be noted that, the first mask layer <NUM> and the second mask layer <NUM> are provided with a lithography mark, and have good light-transmitting respectively. Therefore, on the basis of improving the light-transmitting of the initial mask layer <NUM> in the embodiments of the disclosure, it is beneficial for an operator to align the photolithography mark of the first mask layer <NUM>, the photolithography mark of the second mask layer <NUM> and the photolithography mark of the initial mask layer on <NUM>, thereby improving the precision of the first patterning treatment.

Referring to <FIG> and <FIG> in combination, the second region <NUM> is irradiated with the photomask to change the film properties of the irradiated second region <NUM>. The first region <NUM> and the second region <NUM> are etched by the same etching process, and the etching rate of the first region <NUM> is less than the etching rate of the second region <NUM> during the etching process. Therefore, when removing the region <NUM>, part of the second region <NUM> is retained, so as to form the second mask layer <NUM> with the opening <NUM>.

It should be noted that, in the step of etching the second mask layer <NUM>, both the first region <NUM> and the second region <NUM> are etched. However, because the second region <NUM> has been subjected with the irradiating treatment, the etching rate of the first region <NUM> is less than the etching rate of the second region <NUM> during the etching process, thereby forming the second mask layer <NUM> with the opening <NUM>.

In some embodiments, the step of performing the first patterning treatment on the initial mask layer <NUM> includes the following operations. Referring to <FIG> in combination, the first mask layer <NUM> is etched by taking the second mask layer <NUM> with the opening <NUM> as a mask to form the first mask layer <NUM> with the opening <NUM>. The initial mask layer <NUM> is etched by taking the first mask layer <NUM> with the opening <NUM> as a mask.

It should be noted that, in some embodiments, in the step of etching the first mask layer <NUM> by taking the second mask layer <NUM> with the opening <NUM> as the mask, the second mask layer <NUM> is also etched. When the first mask layer <NUM> with the opening <NUM> is formed, the second mask layer <NUM> is completely etched. In other embodiments, in the step of etching the first mask layer <NUM> by taking the second mask layer <NUM> with the opening <NUM> as the mask, the second mask layer <NUM> is completely etched and part of the first mask layer <NUM> not exposed by the opening <NUM> of the second mask layer <NUM> is etched, so that the thickness of the first mask layer <NUM> with the opening <NUM> in the direction X is less than the thickness of the first mask layer <NUM> before performing the first patterning treatment.

In addition, in some embodiments, in the step of etching the initial mask layer <NUM> by taking the first mask layer <NUM> with the opening <NUM> as the mask, the first mask layer <NUM> is also etched. When the mask layer <NUM> with the opening <NUM> is formed, the first mask layer <NUM> is completely etched. In other embodiments, in the step of etching the initial mask layer <NUM> by taking the first mask layer <NUM> with the opening <NUM> as the mask, the first mask layer <NUM> is completely etched away and part of the initial mask layer <NUM> not exposed by the opening <NUM> of first mask layer <NUM> is etched, so that the thickness of the mask layer <NUM> with the opening <NUM> in the direction X is less than the thickness of the initial mask layer <NUM> before performing the first patterning treatment.

At S105, referring to <FIG> and <FIG>, a second patterning treatment is performed on the substrate <NUM> by using an etching process with the mask layer <NUM> as a mask. The etching rate of the substrate <NUM> is greater than the etching rate of the mask layer <NUM> during the etching process.

It can be understood that, in the step of performing the second patterning treatment on the substrate <NUM> by using the etching process, the mask layer <NUM> is also etched in the etching process. As the mask layer <NUM> is formed by the P-type doped semiconductor layer, the etching rate of the mask layer <NUM> during the etching process can be reduced when the substrate <NUM> is etched. As a result, in the step of performing the second patterning treatment on the substrate <NUM> by using the etching process with the mask layer <NUM> as the mask, on the premise of ensuring that the etching rate of the substrate <NUM> is greater than the etching rate of the mask layer <NUM> during the etching process, the difference between the etching rate of the substrate <NUM> and the etching rate of the mask layer <NUM> can be increased during the etching process, so that it is beneficial to accurately transfer the pattern formed by the opening <NUM> of the mask layer <NUM> to the substrate through the mask layer <NUM>, thereby improving the precision of the second patterning treatment.

In addition, the manufacturing method provided by the embodiments of the disclosure is beneficial to increasing the difference between the etching rate of the substrate <NUM> and the etching rate of the mask layer <NUM> during the etching process, which facilitates to avoid over-etching of the mask layer <NUM> at a sidewall of the opening <NUM> of the formed mask layer <NUM>, and thus to avoid the change of the size of capacitor contact hole <NUM> formed on the basis of the opening <NUM> is avoided, thereby ensuring the precision of the second patterning performed on the substrate <NUM>.

In some embodiments, after performing the second patterning treatment on the substrate <NUM> by using the etching process, part of the mask layer <NUM> is retained, and a ratio of the thickness of the retained mask layer <NUM> and the thickness of the initial mask layer <NUM> along the direction from the substrate <NUM> to the initial mask layer <NUM> is in a range of <NUM> to <NUM>. It can be understood that, in practical applications, after forming the capacitor contact hole <NUM> by etching the substrate <NUM>, the remaining mask layer <NUM> may be removed.

It can be understood that, in the step of performing the second patterning treatment on the substrate <NUM> by adopting the etching process, it is necessary to retain part of the mask layer <NUM> to protect the substrate <NUM> that does not need to be etched, so as to improve the precision of the formed capacitor contact hole <NUM>.

In addition, in the step of transforming the formed initial mask layer <NUM> into the mask layer <NUM> with the opening <NUM>, the initial mask layer may be consumed with part of its thickness. In the step of etching the substrate <NUM>, the mask layer <NUM> composed of the retained initial mask layer <NUM> may also be consumed. In this case, along the direction X from the substrate <NUM> to the initial mask layer <NUM>, the thickness of the initial mask layer is in a range of <NUM> to <NUM>, which is beneficial that after performing the first patterning treatment on the initial mask layer <NUM> and the second patterning treatment on the mask layer <NUM>, the ratio of the thickness of the retained mask layer <NUM> to the thickness of the initial mask layer <NUM> is in the range of <NUM> to <NUM>. On the one hand, when the thickness of the initial mask layer <NUM> is less than <NUM>, in the step of performing the second patterning on the substrate <NUM>, the mask layer <NUM> may be completely etched before the capacitor contact hole <NUM> is formed, so that the substrate <NUM> that does not need to be subjected to the second patterning treatment is etched, which affects the size of the finally formed capacitor contact hole <NUM>. On the other hand, when the thickness of the initial mask layer <NUM> is less than <NUM>, the formed trench would have a greater aspect ratio of greater in the step of performing the second patterning on the substrate <NUM>, which increases the difficulty of performing the second patterning treatment on the substrate <NUM> and reduces the precision of the second patterning treatment. Therefore, in the embodiments of the disclosure, the thickness of the initial mask layer <NUM> is controlled in the range of <NUM> to <NUM>, and the ratio of the thickness of the retained mask layer <NUM> to the thickness of the initial mask layer <NUM> is controlled in the range of <NUM> to <NUM>, which reduces the difficulty of the second patterning treatment, while ensuring that when the capacitor contact hole <NUM> is formed, the mask layer with part of its thickness is retained.

In some embodiments, the retained mask layer <NUM> may have the thickness of <NUM> to <NUM> along the direction X from the substrate <NUM> to the initial mask layer <NUM>. In an example, the retained mask layer <NUM> has the thickness of <NUM> along the direction X from the substrate <NUM> to the initial mask layer <NUM>.

Claim 1:
A method for manufacturing a semiconductor structure, comprising:
providing a substrate (<NUM>);
forming a semiconductor layer (<NUM>) on the substrate (<NUM>);
performing P-type doping on the semiconductor layer (<NUM>) to transform the semiconductor layer (<NUM>) into an initial mask layer (<NUM>);
performing a first patterning treatment on the initial mask layer (<NUM>) to form a mask layer (<NUM>) with an opening;
and performing a second patterning treatment on the substrate (<NUM>) by using an etching process with the mask layer (<NUM>) as a mask, wherein an etching rate of the substrate (<NUM>) is greater than an etching rate of the mask layer (<NUM>) during the etching process; wherein
a material of the initial mask layer (<NUM>) comprises a boron-silicon compound, and an atomic percent of boron atoms and silicon atoms in the boron-silicon compound is in a range of <NUM>:<NUM> to <NUM>:<NUM>;
wherein providing the substrate (<NUM>) comprises:
providing a base (<NUM>);
forming a stacked structure (<NUM>) on the base (<NUM>), wherein the stacked structure (<NUM>) includes a bottom support layer (<NUM>), a first dielectric layer (<NUM>), an intermediate support layer (<NUM>), a second dielectric layer (<NUM>) and a top support layer (<NUM>) stacked in sequence on the base (<NUM>); and
performing the second patterning treatment on the substrate (<NUM>) comprises:
etching the stacked structure (<NUM>) by taking the mask layer (<NUM>) as a mask and using the etching process to form a capacitor contact hole (<NUM>).