Patent Description:
A sensor often comprises a sensor resistor, whereas a resistance value of the sensor resistor depends on a parameter to be measured. A temperature sensor may comprise a sensor resistor having a resistance value depending on the temperature. Such a sensor resistor may comprise e.g. platinum as a temperature sensitive material. Also a gas sensor may comprise a sensor resistor, wherein the resistance value of the sensor resistor depends on a concentration of a gas. An example of such a sensor resistor is a metal oxide semiconductor resistor comprising SnO<NUM> or ZnO as a gas sensitive material. The resistance value of the sensor resistor may obtain a high value depending on the gas concentration to be measured. There may be a leakage current from or to terminals of the sensor resistor resulting in an error of the gas sensor measurement.

It is object to provide a sensor arrangement and a method for sensor measurement that reduces the influence of a leakage current.

These objects are achieved by the subject-matter of the independent claims. Further developments and embodiments are described in dependent claims.

The definitions as described above also apply to the following description unless otherwise stated.

The sensor arrangement comprises a switchable voltage source having a source output for alternatively providing a first and a second excitation voltage, an integrator having an integrator input, a sensor resistor having a first terminal coupled to the source output, a reference resistor having a first terminal coupled to a second terminal of the sensor resistor and a second terminal coupled to the integrator input and a comparator having a first comparator input coupled to an integrator output of the integrator.

Advantageously, the source output of the switchable voltage source is directly connected to the first terminal of the sensor resistor. Thus, the first and the second excitation voltage are directly applied to the first terminal of the sensor resistor. The switchable voltage source is configured to provide the first and the second excitation voltage to the first terminal of the sensor resistor, optionally with a low output resistance. Thus, a leakage current flowing from the first terminal of the sensor resistor to any node of the sensor arrangement is directly provided by the switchable voltage source and has no influence on values of the first and the second excitation voltage and thus on the measurement of the resistance value of the sensor resistor.

In an embodiment, the sensor arrangement comprises a switch that couples the first terminal of the sensor resistor to the second terminal of the sensor resistor.

In an embodiment, the integrator comprises an amplifier having a first amplifier input coupled to the integrator input and an amplifier output coupled to the integrator output. The integrator comprises an integrating capacitor coupling the first amplifier input to the amplifier output.

In an embodiment, the switchable voltage source provides the first excitation voltage in a first phase and the second excitation voltage in a second phase. An integrator input current flows to the integrator input. The integrator input current has a different direction in the first phase in comparison to the second phase. The integrator input current changes its direction at transition from the first phase to the second phase and at transition from the second phase to a further first phase. The integrator input current is positive in one phase of the first and the second phase and is negative in the other phase of the first and the second phase.

The comparator comprises a second comparator input to which a first and a second comparator reference voltage is alternatively provided. The second comparator input may be coupled to a further source output of the switchable voltage source.

The sensor arrangement comprises a latch having a first latch input coupled to a comparator output of the comparator. The latch comprises a first latch output.

The sensor arrangement comprises a logic circuit having an output. An input of the logic circuit is coupled to the first latch output of the latch.

The sensor arrangement comprises a calculation circuit that is coupled to the output of the logic circuit. The calculation circuit may comprises a counter counting pulses provided at the first latch output. The calculation circuit comprises an output for providing a result signal, e.g. a first digital signal and/or a second digital signal as a function of a value of the counter. The value of the counter may be named counter value.

In an embodiment, the sensor arrangement comprises a synchronous counter having a first counter input coupled to an output side of the latch and/or of the logic circuit. The first counter input may be coupled to the first latch output of the latch and/or to the output of the logic circuit. The synchronous counter may be configured to count pulses of a second clock signal starting from a pulse provided at the first latch output. An output of the synchronous counter may be coupled to the calculation circuit. Thus, the calculation circuit may comprises the output for providing the result signal, e.g. the first digital signal and/or the second digital signal as a function of a value of the counter of the calculation circuit and of a value of the synchronous counter.

In an embodiment, the sensor arrangement comprises a control logic coupled on its input side to an output side of the latch or the logic circuit and on its output side to the switchable voltage source. The input side of the control logic may be connected to the first latch output. The control logic may control or drive the switchable voltage source.

In an embodiment, the switchable voltage source comprises a buffer having an output coupled to the source output. The output of the buffer may be directly connected to the source output.

In an embodiment, the switchable voltage source comprises a voltage divider, a first switch that couples a first tap of the voltage divider to an input of the buffer and a second switch that couples a second tap of the voltage divider to the input of the buffer. The first excitation voltage is provided at the first tap and the second excitation voltage is provided at the second tap. When the first switch is set in a conducting state, then the first excitation voltage is provided via the buffer and the source output to the first terminal of the sensor resistor. When the second switch is set in a conducting state, then the second excitation voltage is provided via the buffer and the source output to the first terminal of the sensor resistor.

In an embodiment, the sensor arrangement comprises a bandgap circuit. The switchable voltage source comprises an amplifier circuit having an input coupled to an output of the bandgap circuit and an output coupled via the voltage divider to a reference potential terminal.

The method for sensor measurement comprises.

In an embodiment, this method is performed in a measurement mode of operation. A first digital signal is generated by the sensor arrangement in the measurement mode of operation. The first digital signal depends on the resistance value of the sensor resistor and the resistance value of the reference resistor. The first digital signal depends on the parameter to be measured such as a gas concentration.

The first and the second excitation voltage is provided by a switchable voltage source to a first terminal of the sensor resistor. The reference resistor has a first terminal coupled to a second terminal of the sensor resistor and a second terminal coupled to the integrator input. A first comparator input of the comparator is coupled to an integrator output of the integrator.

In an embodiment, the first excitation voltage is provided to the sensor resistor in a first phase and the second excitation voltage is provided to the sensor resistor in a second phase. The integrator input current has a different direction in the first phase in comparison to the second phase.

In an embodiment, in a reference mode of operation, a switch is set in a conducting state that connects a first terminal of the sensor resistor to a second terminal of the sensor resistor. The first and the second excitation voltage is alternatively provided via the switch to the reference resistor. The integrator input current flows through the switch and the reference resistor to the integrator input.

In an embodiment, a second digital signal is generated by the sensor arrangement in the reference mode of operation. The second digital signal depends on the resistance value of the reference resistor. The second digital signal is independent of the resistance value of the sensor resistor. The resistance value of the sensor resistor can be determined as a function of the first and the second digital value.

The method for sensor measurement is implemented by the sensor arrangement according to one of the embodiments defined above. The method for sensor measurement may be realized as method for operating the sensor arrangement.

In an embodiment, the sensor arrangement realizes a leakage compensated gas sensor. The sensor arrangement is implemented as a circuit that cancels the impact of an electrostatic discharge event, abbreviated ESD, and pad leakage for each measurement. A pad leakage is e.g. leakage current flowing at a bond pad, bond wire, flip-chip connection etc.. This technique enables a wide-range gas-sensor front-end where the leakage current becomes e.g. comparable to (but less than) the signal current. Leakage cancellation is performed for each measurement. The method cancels leakage for process variation of leakage and temperature drift of the leakage. The sensor arrangement is e.g. a solution for a gas sensor. When the requirements are for a wide-range sensor resistance (><NUM> MΩ), the sensor current becomes smaller and smaller. The pad and ESD leakage may become comparable e.g. to the signal current. Also in this case, the sensor arrangement obtains a high measurement accuracy for a wide-range gas-sensor resistance where the leakage currents needs.

The following description of figures of embodiments may further illustrate and explain aspects of the sensor arrangement and the method for sensor measurement. Devices and circuit parts with the same structure and the same effect, respectively, appear with equivalent reference symbols. In so far as devices or circuit parts correspond to one another in terms of their function in different figures, the description thereof is not repeated for each of the following figures.

<FIG> shows an example of an embodiment of a sensor arrangement <NUM> comprising a sensor resistor <NUM>, a switchable voltage source <NUM>, an integrator <NUM> and a comparator <NUM>. The sensor resistor <NUM> is arranged between a source output <NUM> of the switchable voltage source <NUM> and an integrator input <NUM> of the integrator <NUM>. Moreover, the sensor arrangement <NUM> comprises a reference resistor <NUM>. The sensor resistor <NUM> comprises a first and a second terminal <NUM>, <NUM>. The first terminal <NUM> of the sensor resistor <NUM> is directly and permanently connected to the source output <NUM>. The second terminal <NUM> of the sensor resistor <NUM> is directly and permanently connected to a first terminal of the reference resistor <NUM>. A second terminal of the reference resistor <NUM> is directly and permanently connected to the integrator input <NUM>. The connection of the second terminal <NUM> of the sensor resistor <NUM> to the first terminal of the reference resistor <NUM> may comprise at least one of a group consisting of a connection line, a bond wire, a bond pad, a bump and a flip-chip connection. The connection of the first terminal <NUM> of the sensor resistor <NUM> to the source output <NUM> may comprise at least one of a group consisting of a connection line, a bond wire, a bond pad, a bump and a flip-chip connection.

The sensor resistor <NUM> and the reference resistor <NUM> form a series circuit <NUM>. The series circuit <NUM> of the sensor resistor <NUM> and the reference resistor <NUM> is arranged between the source output <NUM> and the integrator input <NUM>.

Furthermore, the sensor arrangement <NUM> comprises a switch <NUM> that connects the first terminal <NUM> of the sensor resistor <NUM> to the second terminal <NUM> of the sensor resistor <NUM>. Thus, the series circuit <NUM> comprises the reference resistor <NUM> and a parallel circuit of the sensor resistor <NUM> and the switch <NUM>.

The integrator <NUM> comprises an amplifier <NUM> having a first amplifier input coupled to the integrator input <NUM>. The first amplifier input is directly and permanently connected to the integrator input <NUM> and thus to the second terminal of the reference resistor <NUM>. Moreover, an amplifier output of the amplifier <NUM> is coupled to an integrator output <NUM>. The integrator <NUM> comprises an integrating capacitor <NUM> that couples the integrator input <NUM> to the integrator output <NUM>. The amplifier <NUM> comprises a control input <NUM>. Moreover, the sensor arrangement <NUM> comprises a digital-to-analog converter <NUM> connected on its output side to the control input <NUM> of the amplifier <NUM>. The integrator output <NUM> of the integrator <NUM> is coupled to a first comparator input <NUM> of the comparator <NUM>. A second comparator input <NUM> of the comparator <NUM> may be coupled to a further source output <NUM> of the switchable voltage source <NUM>.

The sensor arrangement <NUM> comprises a latch <NUM> having a first latch input <NUM> coupled to a comparator output <NUM> of the comparator <NUM>. The first latch input <NUM> may be realized as a D-input. Moreover, the latch <NUM> may comprise a second latch input <NUM> that is connected to a clock generator, not shown. The second latch input <NUM> may be a clock input. The latch <NUM> comprises a first latch output <NUM>. The first latch output <NUM> may be a Q output. The latch <NUM> may be realized as a D-latch, a D-flip-flop, and/or a transparent D-flip-flop.

The sensor arrangement <NUM> comprises a synchronous counter <NUM> having a first counter input <NUM> connected to the first latch output <NUM>. The first counter input <NUM> may be realized as a reset input. The synchronous counter <NUM> has a second counter input <NUM> which is connected to a further clock oscillator, not shown. The synchronous counter <NUM> may be realized as a synchronized counter or a synchronization counter or, alternatively, be replaced by a counter.

Additionally, the sensor arrangement <NUM> comprises a calculation circuit <NUM>. The calculation circuit <NUM> is connected on its input side to the first latch output <NUM>. Moreover, the calculation circuit <NUM> is connected on its input side to an output of the synchronous counter <NUM>. The calculation circuit <NUM> comprises a counter <NUM> which may be coupled to the first latch output <NUM>.

Additionally, the sensor arrangement <NUM> comprises a control logic <NUM>. The control logic <NUM> is connected on its input side to the first latch output <NUM>. A further input of the control logic <NUM> is connected to a clock generator, not shown. The control logic <NUM> may comprise a clock generator. The control logic <NUM> is connected on its output side to a control terminal of the switch <NUM>. The control logic <NUM> is connected on its output side to a control terminal of the digital-to-analog converter <NUM>. Moreover, the control logic <NUM> is connected on its output side to the switchable voltage source <NUM>.

The switchable voltage source <NUM> alternatively provides a first and a second excitation voltage V1, V2 at the source output <NUM>. In a first phase A, the switchable voltage source <NUM> provides the first excitation voltage V1. In a second phase B, the switchable voltage source <NUM> provides the second excitation voltage V2. The first and the second excitation voltage V1, V2 are applied to the first terminal <NUM> of the sensor resistor <NUM>. The first and the second excitation voltage V1, V2 are provided to the series circuit <NUM> of the sensor resistor <NUM> and the reference resistor <NUM>.

In a measurement mode of operation, the switch <NUM> is set in a non-conducting state by a switch control signal Φ3. The control logic <NUM> generates the switch control signal Φ3. Thus, an integrator input current IN flows from the source output <NUM> to the integrator input <NUM> via the sensor resistor <NUM> and the reference resistor <NUM>. At the integrator input <NUM> an integrator input voltage VIN can be tapped. The integrator input voltage VIN is applied to the first input of the amplifier <NUM>.

During a reference mode of operation, the switch <NUM> is set in a conducting state by the switch control signal Φ3. Thus, the integrator input current IN flows from the source output <NUM> to the integrator input <NUM> via the switch <NUM> and the reference resistor <NUM>.

A common mode voltage VCM is provided to the second input of the amplifier <NUM>. The amplifier <NUM> generates an integrator output voltage OPOUT at the integrator output <NUM>. The integrator output voltage OPOUT is a function of the integrator input current IN that flows through the reference resistor <NUM> to the integrator input <NUM>. Due to the operation of the amplifier <NUM>, the integrator input voltage VIN is approximately equal to the common mode voltage VCM. The control logic <NUM> provides a trim signal OSTRIM to the input of the digital-to-analog converter <NUM>. The digital-to-analog converter <NUM> generates a control signal SC and provides it to the control input <NUM> of the amplifier <NUM> that is a function of the trim signal OSTRIM. A threshold of the amplifier <NUM> is set as a function of the control signal SC.

The integrator <NUM> provides the integrator output signal OPOUT to the first comparator input <NUM> of the comparator <NUM>. A first and a second comparator reference voltage VH, VL is alternatively provided to the second comparator input <NUM>. The first and the second comparator reference voltage VH, VL are generated by the switchable voltage source <NUM>. The first comparator reference voltage VH is provided during the second phase B and the second comparator reference voltage VL is provided during the first phase A.

An output signal SCO of the comparator <NUM> is provided to the first latch input <NUM> of the latch <NUM>. A first clock signal CLK1 is applied to the second latch input <NUM> of the latch <NUM>. The latch <NUM> generates a first latch signal QL as a function of the comparator output signal SCO and of the first clock signal CLK1. The first latch signal QL may be equal to an output signal C1.

The output signal C1 is provided to the synchronous counter <NUM>, the control logic <NUM> and the calculation circuit <NUM>. The output signal C1 is provided to the first counter input <NUM> of the synchronous counter <NUM>. A second clock signal CLK2 is applied to the second counter input <NUM> of the synchronous counter <NUM>. The synchronous counter <NUM> generates a counter output signal C2 as a function of the second clock signal CLK2 and of the output signal C1. The output signal C1 performs a reset of the synchronous counter <NUM>. The counter output signal C2 is provided to the calculation circuit <NUM>. The synchronous counter <NUM> stops counting after receiving a signal SAT indicating the end of a conversion time Atime. Thus, the counter output signal C2 is generated at the end of the conversion time Atime. The counter output signal C2 is a function of or is equal to the number of pulses of the second clock signal CLK2 between a pulse of the output signal C1 and the end of a conversion time Atime.

The calculation circuit <NUM> calculates a first and/or second digital signal SD1, SD2. The first and/or second digital signal SD1, SD2 can also be called analog-to-digital converter counter result, abbreviated ADC_Count.

The output signal C1 and the first clock signal CLK1 are provided to the control logic <NUM>. The control logic <NUM> generates control signals Φ1 to Φ3. The control signals Φ1 to Φ3 can also be called clock signals. The first and the second control signal Φ1, Φ2 are provided to the switchable voltage source <NUM>. The switch control signal Φ3 is provided to the control terminal of the switch <NUM>. The signals are further explained by <FIG>.

The sensor arrangement <NUM> is fabricated as a circuit for pad/ESD leakage compensation for wide-range gas-sensor resistance measurement. The sensor arrangement <NUM> may operate with high accuracy as long as the leakage is less than a signal current ISIG or when the ESD/pad leakage becomes comparable to the signal current ISIG. The sensor resistance measurement has no significant error due to leakage current (not as much as the leakage is the percentage of the signal current ISIG).

Parts of the sensor arrangement <NUM> such as the reference resistor <NUM>, the integrator <NUM> and the comparator <NUM> are fabricated on exactly one semiconductor body. The sensor resistor <NUM> may be realized separate from this semiconductor body. The sensor arrangement <NUM> can also be named sensor device or sensor apparatus. The sensor resistor <NUM> may be realized off-chip with respect to the semiconductor body.

In an alternative embodiment, not shown, the sensor arrangement <NUM> comprises a logic circuit that is directly connected to the first latch output <NUM> of the latch <NUM> or is coupled to the first latch output <NUM> of the latch <NUM> e.g. by a further latch or another circuit, e.g. as shown in <FIG> and <FIG>. The logic circuit generates the output signal C1. The logic circuit provides the output signal C1 by transferring a single pulse of the first clock signal CLK1 after a rising edge and additionally after a falling edge of the comparator output signal SCO. The output signal C1 is equal to a single pulse of the first clock signal CLK1 after a rising edge and after a falling edge of the comparator output signal SCO.

Alternatively, the input of the logic circuit may be coupled or directly connected to the comparator output <NUM> of the comparator <NUM>. In this case the latch <NUM> may be omitted.

Alternatively, the switch <NUM> is omitted. Thus, the sensor resistor <NUM> is continuously measured in series connection with the reference resistor <NUM>.

In an alternative embodiment, not shown and not being part of the present invention, the sensor arrangement <NUM> comprises a further comparator. The integrator output <NUM> of the integrator <NUM> is coupled to a first comparator input of the further comparator. The comparator <NUM> and the further comparator form a window comparator. The latch <NUM> or the logic circuit is coupled on its input side to a comparator output of the further comparator. A second comparator input of the further comparator may be coupled to an additional source output of the switchable voltage source <NUM>. The second comparator reference voltage VL is continuously provided to the second comparator input of the further comparator. The first comparator reference voltage VH is continuously provided to the second comparator input <NUM> of the comparator <NUM>. Thus, the integrator output voltage OPOUT is compared with the first and the second comparator reference voltage VH, VL either by the comparator <NUM> and the further comparator or only by the comparator <NUM> (as shown in <FIG>). Thus, the sensor arrangement <NUM> may be realized without switching the second comparator input <NUM> of the comparator <NUM> to different reference voltages. The second comparator input <NUM> receives a non-zero voltage.

<FIG> shows an example of an embodiment of the sensor arrangement <NUM> shown in <FIG> in the first phase A. In the first phase A, the first excitation voltage V1 is provided to the sensor resistor <NUM>. The first excitation voltage V1 can be calculated according to the equation: <MAT> wherein VCM is the common mode voltage and VF is a distance voltage. In the first phase A, the integrator input current IN is equal to a current Ifall. The integrator output voltage OPOUT falls during the first phase A. There may be a first leakage current IL1 at the first terminal <NUM> of the sensor resistor <NUM> and a second leakage current IL2 at the second terminal <NUM> of the sensor resistor <NUM>. In <FIG>, the first and the second leakage current IL1, IL2 are indicated as arrows. Since the sensor resistor <NUM> is in contact with gas, such as air, and since air usually has a humidity content, leakage currents IL1, IL2 may flow from the terminals <NUM>, <NUM> to other parts of the sensor arrangement <NUM>. These leakage currents IL1, IL2 cannot be completely avoided, since an encapsulation of the sensor resistor <NUM> would result in an insensitive gas sensor.

The integrator input voltage VIN is approximately equal to the common mode voltage VCM. When there is no leakage, a signal current ISIG flows through the sensor resistor <NUM> and the reference resistor <NUM> that is given by: <MAT> wherein RS is a resistance value of the sensor resistor <NUM> and RREF is a resistance value of the reference resistor <NUM>. The above equation is valid in the measurement mode of operation. In the reference mode of operation, a resistance value of the switch <NUM> can be assumed as zero. Thus, the signal current ISIG follows the equation: <MAT> wherein ISIG' is the value of the signal current in the reference mode of operation.

<FIG> shows an example of an embodiment of the sensor arrangement <NUM> in the second phase B. In the second phase B, the integrator input current IN has a negative value such that the integrator output voltage OPOUT rises. The second excitation voltage V2 can be calculated according to the following equation: <MAT>.

The first and the second excitation voltage V1, V2 are different. The first excitation voltage V1 is higher than the second excitation voltage V2. The common mode voltage VCM is between the first and the second excitation voltage V1, V2. The first and the second excitation voltage V1, V2 are forced on the first terminal <NUM> by a buffer <NUM> shown in <FIG> that can drive the first leakage current IL1 and maintain the excitation voltage forced. The other side of the sensor resistor <NUM> is an intermediate node that has the second leakage current IL2. The buffer <NUM> is realized as a voltagereference operational amplifier. The currents Ifall and Irise (with the directions shown by arrows in <FIG>) can be calculated according to the equations: <MAT> wherein ISIG is the signal current flowing through the sensor resistor <NUM>. The direction of the signal current ISIG changes from the first to the second phase A, B.

<FIG> shows an example of signals of the sensor arrangement <NUM> of <FIG>. The first clock signal CLK1 has a smaller frequency value than the second clock signal CLK2. The first clock signal CLK1 has a first period T1. The second clock signal CLK2 has a second period T2. The second period T2 is smaller than the first period T1. The first clock signal CLK1 e.g. may have a value of <NUM>, whereas the second clock signal CLK2 may have a value of <NUM>. The measurement of the resistance value of the sensor resistor <NUM> may be performed in the predetermined conversion time Atime, also called integration time.

A measurement may start with the second phase B. The first phase A and the second phase B alternate. A period consists of one first phase A and one second phase B. In the second phase B, the integrator output voltage OPOUT starts at the value of the second reference voltage VL at a first point of time t1. During the second phase B, the first comparator reference voltage VH is provided to the second comparator input <NUM>. The comparator output signal SCO may have a first logical value, e.g. the value <NUM>. The integrator output voltage OPOUT rises from the second comparator reference voltage VL to the first comparator reference voltage VH. At a second point of time t2 (or shortly before), the rising integrator output voltage OPOUT obtains the value of the first comparator reference voltage VH. Thus, the comparator output signal SCO changes its value. The comparator output signal SCO may have a second logical value, e.g. the value <NUM>, at the second point of time t2. The latch <NUM> generates a pulse of the first latch signal QL (not shown) that results from the change of the value of the comparator output signal SCO and from the pulse of the first clock signal CLK1. A pulse of the output signal C1 is equal to or depends on the pulse of the first latch signal QL.

The synchronous counter <NUM> may be reset by the pulse of the output signal C1. The synchronous counter <NUM> may start counting pulses of the second clock signal CLK2. The synchronous counter <NUM> is reset e.g. at the first, second, third and fourth point of time t1, t2, t3, t4. Alternatively, the synchronous counter <NUM> may be reset optionally at some of these points of time, e.g. the first and the third point of time t1, t3. In one embodiment, the synchronous counter <NUM> may e.g. generate a pulse of the counter output signal C2 at the second point of time t2.

At the second point of time t2, the control logic <NUM> starts the first phase A and sets the phase signals Φ1, Φ2 such that the first excitation voltage V1 is provided to the series circuit <NUM> resulting in a fall of the integrator output voltage OPOUT. In the first phase A, the second comparator reference voltage VL is provided to the second comparator input <NUM>. The integrator output voltage OPOUT is higher than the second comparator reference voltage VL up to a third point of time t3. The comparator output signal SCO may have the second logical value, e.g. the value <NUM>, in the first phase A up to the third point of time t3 (or until shortly before the third point of time t3). At the third point of time t3 (or shortly before), the integrator output voltage OPOUT falls below the second comparator reference voltage VL such that the comparator output signal SCO changes its value, and may obtain e.g. the first logical value, e.g. the value <NUM>. The latch <NUM> generates a pulse of the first latch signal QL that results from the change of the value of the comparator output signal SCO and from the pulse of the first clock signal CLK1. The pulse of the first latch signal QL triggers a pulse of the output signal C1. The pulse of the output signal C1 may rise with the rising edge of the pulse of the first clock signal CLK1. The pulses of the output signal C1 may rise with the rising edge of the pulses of the first clock signal CLK1.

The synchronous counter <NUM> may be reset by the pulse of the output signal C1. The synchronous counter <NUM> may start counting pulses of the second clock signal CLK2 after the reset. In an embodiment, the synchronous counter <NUM> may e.g. generate a pulse of the counter output signal C2. The first and the second comparator reference voltage VH, VL are different. The first comparator reference voltage VH is higher than the second comparator reference voltage VL. The second comparator reference voltage VL may be higher than the first excitation voltage V1. The first and the second comparator reference voltages VH, VL are different from the first and the second excitation voltages V1, V2.

A further second phase B' follows the first phase A and ends at a fourth point of time t4. The operation during the further second phase B' is equal to the operation in the previously described second phase B. A further first phase A' follows the further second phase B' and is between the fourth point of time t4 and a fifth point of time t5. The integrator output voltage OPOUT has a triangle form having a frequency depending on the resistance value of the sensor resistor <NUM>.

In the example shown in <FIG>, the conversion time Atime ends during the further first phase A'. At the end of the conversion time Atime, the integrator output voltage OPOUT is between the first and the second comparator reference voltage VH, VL. The number of the first phases A, A' and the number of the second phases B, B' depends on the resistance value of the sensor resistor <NUM>. <FIG> shows an example with two completed second phases B, B', one completed first phase A and one first phase A' stopped by the end of the conversion time Atime.

The counter <NUM> generates a counter value C3 which may be named course counter signal. In an embodiment, the counter <NUM> of the calculation circuit <NUM> counts the number of completed phases. The counter <NUM> of the calculation circuit <NUM> may count the number of the completed first phases A and the number of the completed second phases B, B', optionally in separate manner or in total. Alternatively, the counter <NUM> of the calculation circuit <NUM> may count only the number of completed periods.

The synchronous counter <NUM> may count the pulses of the second clock signal CLK2 from the start of the last phase up to the end of the conversion time Atime. The synchronous counter <NUM> may count the pulses of the second clock signal CLK2 from the start of the last second phase B, B' up to the end of the conversion time Atime, in case the conversion time starts with the second phase B. The synchronous counter <NUM> may count the pulses of the second clock signal CLK2 from the end of the last completed period up to the end of the conversion time Atime. The second clock signal CLK2 may be a function of or may be equal to the number of pulses of the second clock signal CLK2 during the uncompleted period. The uncompleted period ends with the end of the conversion time Atime.

In the measurement mode of operation, the switch <NUM> is set in a non-conducting state and the first digital signal SD1 is calculated using the counter value or values C3 of the counter <NUM> of the calculation circuit <NUM> and the counter output signal C2 of the synchronous counter <NUM>. The counter value C3 of the counter <NUM> of the calculation circuit <NUM> represents a course result. The counter output signal C2 of the synchronous counter <NUM> represents a fine count, a residual count or a residual value of the integrator output voltage OPOUT. The first digital signal SD1 may be calculated using the number of the completed first phases A, A', the number of the completed second phases B, B' and the numbers of pulses in the last phase which is stopped by the end of the conversion time Atime. The first digital signal SD1 represents the resistance value of the series circuit <NUM> of the sensor resistor <NUM> and of the reference resistor <NUM>. Thus, the first digital signal SD1 is a function of the counter value C3 and the counter output signal C2 determined in the measurement mode of operation: SD1 = f(C3; C2).

In the reference mode of operation, the switch <NUM> is set in a conducting state and the second digital signal SD2 is determined such as the first digital signal SD1. Thus, the second digital signal SD2 is a function of the counter value C3 and the counter output signal C2 determined in the reference mode of operation: SD2 = f(C3; C2). The function f is the same in both modes.

In <FIG>, the signal of the system or the architecture of <FIG> is shown. In the following, only the first phases A, A' are considered and the second phases B, B' are neglected (for example in case of an alternative sensor arrangement in which the integrator output voltage OPOUT is set from the second comparator reference voltage VL to the first comparator reference voltage VH at the end of each of the first phases A, A' using a charge package QP provided to the integrator input <NUM>). The charge package QP may e.g. have the value: <MAT> wherein Cref is a capacitance value of the integrating capacitor <NUM> and Vref is the difference between the first comparator reference voltage VH and the second comparator reference voltage VL. Considering the currents shown in <FIG>, a charge conservation at the integrator input <NUM> during the conversion time Atime results into the following equation: <MAT> wherein Atime is a value of the conversion time, ISIG is a value of the signal current, IL2 is a value of the second leakage current, Ctfall is a value of a system count (such as SD1 or SD2) and QP is a value of the charge package. Using the above written equation, the system count Ctfall based on only the current Irise can be calculated according to the following equation: <MAT> wherein ISIG is a value of the signal current, IL2 is a value of the second leakage current and Atime is a value of the conversion time. Here only first phases A are used.

Alternatively, only second phases B may be used and the first phases A, A' are neglected (for example in case of an alternative sensor arrangement in which the integrator output voltage OPOUT is set from the first comparator reference voltage VH to the second comparator reference voltage VL at the end of each of the second phases B, B' using the charge package QP defined above). Considering the currents shown in <FIG>, charge conservation results into the equation: <MAT> wherein Ctrise is a value of a system count (such as SD1 or SD2) and Atime, ISIG, IL2 and QP are as defined above. Thus, the system count Ctrise using only the current Ifall can be calculated according to the following equation: <MAT>.

If a system count Ctperiod is based on a period (rise+fall), the impact of leakage is cancelled. The system count corresponds to the first digital signal SD1. The first phases A, A' each may have a duration TA and the second phases B, B' each may have a duration TB. The conversion time Atime can be calculated for complete periods each consisting of one first phase A and one second phase B: <MAT>.

The integrator input current IN that flows during one duration TA results in the charge package QP. The integrator input current IN that flows during one duration TB also results in the charge package QP (or in -QP): <MAT>.

Inserting TA and TB in the equation above results in: <MAT>.

Thus, the system count Ctperiod can be approximately calculated according to the following equation: <MAT>.

Since IL2<NUM> can be neglected in respect to ISIG<NUM>, the system count Ctperiod and the digital signals SD1, SD2 are approximately independent from the leakage current IL2. Since the conversion time Atime and the charge package QP have predetermined values, the system count Ctperiod and the digital signals SD1, SD2 only depend on the signal current ISIG.

Moreover, the sensor arrangement <NUM> may be configured to realize a ratiometric measurement where.

The first digital signal SD1 is generated by the calculation circuit <NUM> in the measurement mode of operation. The second digital signal SD2 is generated by the calculation circuit <NUM> in the reference mode of operation. A resistance value of the sensor resistor <NUM> can be calculated as a function of the first and the second digital signal SD1, SD2. The ratiometric measurement cancels other sources of error arising from the process errors and drifts e.g. of the switchable voltage source <NUM>, the integrating capacitor <NUM> and the first and the second clock signal CLK1, CLK2 etc..

For the measurement of the sensor resistor <NUM> and the reference resistor <NUM>, the impact of pad/ESD leakage is cancelled for count measurement Ctperiod,RS+RREF in the above suggested manner. The first and the second excitation voltage V1, V2 can be realized as VCM +/- VF. For the measurement of the reference resistor <NUM>, the first and the second excitation voltage V1, V2 is directly forced on the second terminal <NUM> by the buffer <NUM> that can supply the leakage and maintain the first and the second excitation voltage V1, V2. Hence, there is no impact of ESD/pad leakage for the count measurement Ctperiod,RREF.

In case different values AtimeS and AtimeR for the conversion time are set for the measurement mode of operation and for the reference mode of operation, the resistance value RS of the sensor resistor <NUM> may be calculated, e.g. by the calculation circuit <NUM>, using: <MAT> wherein RREF is the resistance value of the reference resistor <NUM>, Ctperiod,RREF is the value of the second digital signal SD2 at the end of a conversion time AtimeR of the reference mode of operation, Ctperiod,RS+RREF is the value of the first digital signal SD1 at the end of a conversion time AtimeS of the measurement mode of operation, AtimeS is the duration of the conversion time of the measurement mode of operation and AtimeR is the duration of the conversion time of the reference mode of operation. Ctperiod,RREF has to be weighted with AtimeR and Ctperiod,RS+RREF has to be weighted by AtimeS to eliminate the influence of the different conversion times AtimeR, AtimeS.

In case AtimeR is equal to AtimeS, the system count Ctperiod,RREF may be much higher than the system count Ctperiod,RS+RREF. Thus, the conversion time AtimeR in reference mode of operation can be set on a lower value in comparison to the conversion time AtimeS in the measurement mode of operation. Thus, a similar accuracy may be obtained for the determination of both system count values Ctperiod,RREF and Ctperiod,RS+RREF. The above mentioned equation can be obtained as follows, wherein the leakage current IL2 is set to zero:
In the measurement mode of operation, the system count Ctperiod,RS+RREF can be calculated as follows using the above explained equation for Ctperiod and the equation ISIG=VF/(RS+REF): <MAT>.

In the reference mode of operation, the system count Ctperiod,RREF can be calculated using the above explained equation for Ctperiod and the equation ISIG'=VF/REF: <MAT>.

Dividing the second equation through the first equation results in (QP and VF have the same values in the measurement mode and in the reference mode of operation): <MAT>.

This results in the above mentioned equation for the resistance value RS of the sensor resistor <NUM>.

In case the same value Atime for the conversion time is set for the measurement mode of operation and for the reference mode of operation, the resistance value RS of the sensor resistor <NUM> may be calculated, e.g. by the calculation circuit <NUM>, using: <MAT> wherein RREF is the resistance value of the reference resistor <NUM>, Ctperiod,RREF is the value of the second digital signal SD2 resulting from the reference mode of operation and Ctperiod,RS+RREF is the value of the first digital signal SD1 resulting from the measurement mode of operation. In the above equation, the conversion time Atime is fixed or predetermined or identical for the measurement mode and for the reference mode of operation. The same value for the conversion time Atime is set for the measurement mode of operation and for the reference mode of operation.

Advantageously, the sensor arrangement <NUM> realizes a widedynamic range gas-sensor architecture that can operate from <NUM> kΩ to <NUM> MΩ of the gas sensor. The ESD/pad leakage cannot introduce a significant measurement error for high resistance values of the sensor resistor <NUM>. The sensor arrangement <NUM> can cancel the impact of ESD/pad leakage (as long as leakage is less than signal current) and process variations in leakage current or drift of signal/leakage current.

<FIG> shows an example of details of the sensor arrangement <NUM> shown in <FIG>. The latch <NUM> and the control logic <NUM> are shown in detail. The latch <NUM> has a second latch output <NUM>. The second latch output <NUM> is an inverse Q output. The control logic <NUM> comprises several logic gates. The control logic <NUM> comprises two inputs <NUM>, <NUM> that are connected to the two latch outputs <NUM>, <NUM>. The control logic <NUM> comprises a flip-flop <NUM>. A first NAND gate <NUM> of the flip-flop <NUM> is arranged between the first input <NUM> and a first terminal <NUM> of the control logic <NUM>. Similarly, a second NAND gate <NUM> of the flip-flop <NUM> is arranged between the second input <NUM> and a second terminal <NUM>. A first AND gate <NUM> of the control logic <NUM> couples the first input <NUM> to a first input of the first NAND gate <NUM>. Correspondingly, a second AND gate <NUM> couples the second input <NUM> to a first input of the second NAND gate <NUM>. A first signal S1 is applied to a second input of the first AND gate <NUM>. A second signal S2 is provided to a second input of the second AND gate <NUM>. The second input of the first AND gate <NUM> and the second input of the second AND gate <NUM> are connected to appropriate nodes of the sensor arrangement <NUM>. The first and the second signal S1, S2 are signals to enable or disable this block, e.g. to enable or disable the flip-flop <NUM>.

An output of the first NAND gate <NUM> is coupled by a series circuit of inverters <NUM> to <NUM> to the first terminal <NUM> of the control logic <NUM>. The series circuit of inverters comprises three inverters <NUM> to <NUM>. An output of the second NAND gate <NUM> is coupled e.g. by a series circuit of further inverters <NUM> to <NUM> to the second terminal <NUM> of the control logic <NUM>. The series circuit of further inverters comprises three inverters <NUM> to <NUM>. The output of the first NAND gate <NUM> is coupled via two inverters <NUM>, <NUM> to a first node <NUM>. The first node <NUM> is coupled via a third inverter <NUM> to the first terminal <NUM> of the control logic <NUM>. The output of the second NAND gate <NUM> is coupled via two further inverters <NUM>, <NUM> to a second node <NUM>. The second node <NUM> is coupled via a further third inverter <NUM> to the second terminal <NUM> of the control logic <NUM>.

The first node <NUM> is connected to a second input of the second NAND gate <NUM>. The second node <NUM> is connected to a second input of the first NAND gate <NUM>. A third signal S3 is provided at the first terminal <NUM> of the control logic <NUM>. A fourth signal S4 is provided at the second terminal <NUM> of the control logic <NUM>. The flip-flop <NUM> comprises the first and the second NAND gate <NUM>, <NUM>, the two inverters <NUM>, <NUM>, the two further inverters <NUM>, <NUM> and the first and the second node <NUM>, <NUM> together with the connections. The third and the fourth signal S3, S4 are used to generate the first and the second control Φ1, Φ2. The first and the second control Φ1, Φ2 are a function of the third and the fourth signal S3, S4. The third and the fourth signal S3, S4 realize non-overlap times for the sensor arrangement <NUM>.

<FIG> shows an example of details of the sensor arrangement <NUM> shown in <FIG> and <FIG>. The sensor arrangement <NUM> comprises a bandgap circuit <NUM>. An output of the bandgap circuit <NUM> is coupled to an input of the switchable voltage source <NUM>. Moreover, the sensor arrangement <NUM> comprises a current source <NUM> that is connected to the bandgap circuit <NUM> and has an output for providing a bias current IB.

The switchable voltage source <NUM> comprises a buffer <NUM>. The buffer <NUM> has an output directly connected to the source output <NUM>. Thus, the output of the buffer <NUM> is directly and permanently connected to the first terminal <NUM> of the sensor resistor <NUM>. The buffer <NUM> is realized as an amplifier. An output of the amplifier forms the output of the buffer <NUM> and is directly connected to an inverting input of the amplifier. The buffer <NUM> may provide an amplification factor of <NUM>.

Moreover, the switchable voltage source <NUM> comprises a voltage divider <NUM>, a first switch <NUM> and a second switch <NUM>. The first switch <NUM> couples a first tap <NUM> of the voltage divider <NUM> to an input of the buffer <NUM> that is connected to a non-inverting input of the amplifier of the buffer <NUM>. The second switch <NUM> connects a second tap <NUM> of the voltage divider <NUM> to the input of the buffer <NUM>. The voltage divider <NUM> is realized as a resistive voltage divider. The voltage divider <NUM> comprises a first and a second resistor <NUM>, <NUM>. The first resistor <NUM> couples the second tap <NUM> to a reference potential terminal <NUM>. The second resistor <NUM> couples the first tap <NUM> to the second tap <NUM>.

The voltage divider <NUM> may comprise a third resistor <NUM> such that the series circuit of the second and the third resistor <NUM>, <NUM> couples the first tap <NUM> to the second tap <NUM>. A third tap <NUM> is between the second and the third resistor <NUM>, <NUM>. The third tap <NUM> is connected to the second input of the amplifier <NUM> of the integrator <NUM>. The voltage divider <NUM> at least comprises a fourth resistor <NUM> arranged between the first tap <NUM> and the output of the bandgap circuit <NUM>.

Furthermore, the switchable voltage source <NUM> comprises an amplifier circuit <NUM>. The amplifier circuit <NUM> is connected on its input side to the output of the bandgap circuit <NUM>. An output of the amplifier circuit <NUM> is coupled via the voltage divider <NUM> to the reference potential terminal <NUM>. The output of the amplifier circuit <NUM> is coupled via at least the fourth resistor <NUM> to the first tap <NUM>. The voltage divider <NUM> may comprise a fifth to a seventh resistor <NUM> to <NUM>. The series circuit of the fourth to the seventh resistor <NUM>, <NUM> to <NUM> couples the first tap <NUM> to the output of the amplifier circuit <NUM>. The voltage divider <NUM> comprises a fourth to a sixth tap <NUM> to <NUM>. The fourth tap <NUM> is between the fourth resistor <NUM> and the fifth resistor <NUM>. Similarly, the fifth tap <NUM> is between fifth resistor <NUM> and the sixth resistor <NUM>. The sixth tap <NUM> is between the sixth resistor <NUM> and the seventh resistor <NUM>. The fourth tap <NUM> is coupled via a third switch <NUM> to second comparator input <NUM>. The sixth tap <NUM> is coupled via a fourth switch <NUM> to the second comparator input <NUM>.

The amplifier circuit <NUM> comprises an operational amplifier <NUM> having a non-inverted input connected to the output of the bandgap circuit <NUM>. An output of the operational amplifier <NUM> is connected to the output of the amplifier circuit <NUM>. The amplifier circuit <NUM> comprises a further voltage divider <NUM>. A tap <NUM> of the further voltage divider <NUM> is connected to an inverting input of the operational amplifier circuit <NUM>. The further voltage divider <NUM> comprises a first resistor <NUM> and at least a second resistor <NUM>. The first resistor <NUM> couples the output of the operational amplifier <NUM> to the tap <NUM>. The second resistor <NUM> couples the tap <NUM> to the reference potential terminal <NUM>. The further voltage divider <NUM> may comprise a third and a fourth resistor <NUM>, <NUM> such that a series circuit of the second to the fourth resistor <NUM> to <NUM> couples the tap <NUM> to the reference potential terminal <NUM>. Alternatively, the third and the fourth resistor <NUM>, <NUM> of the further voltage divider <NUM> are replaced by connection lines.

The bandgap circuit <NUM> provides a bandgap voltage VBG that is applied to the input of the amplifier circuit <NUM> and such to the input of the operational amplifier <NUM>. The amplifier circuit <NUM> generates an output voltage VOUT. The output voltage VOUT is a function of the bandgap voltage VBG and of the resistance values of the resistors of the further voltage divider <NUM>. Thus, the output voltage VOUT has a higher voltage value than the bandgap voltage VBG. The amplification factor of the amplifier circuit <NUM> is higher than <NUM>. The first resistor <NUM> and/or the second resistor <NUM> of the further voltage divider <NUM> can be realized as a trimmable resistor. A reference potential VSS is tapped at the reference potential terminal <NUM>.

The output voltage VOUT drops across the voltage divider <NUM>. Thus, at the first tap <NUM> of the voltage divider <NUM>, the first excitation voltage V1 is generated. The first excitation voltage V1 is provided via the first switch <NUM> and the buffer <NUM> to the source output <NUM> in the first phase A. Correspondingly, at the second tap <NUM>, the second excitation voltage V2 is generated. The second excitation voltage V2 is provided via the second switch <NUM> and the buffer <NUM> to the source output <NUM> in the second phase B. Advantageously, the buffer <NUM> supplies the first leakage current IL1 at the first terminal <NUM> of the sensor resistor <NUM>. The common mode voltage VCM is tapped at the third tap <NUM> and provided to the second input of the amplifier <NUM> of the integrator <NUM>.

At the fourth tap <NUM> of the voltage divider <NUM>, the second comparator reference voltage VL is tapped and provided via the third switch <NUM> to the second comparator input <NUM> in the first phase A. Similarly, the first comparator reference voltage VH is tapped at the sixth tap <NUM> of the voltage divider <NUM> and provided via the fourth switch <NUM> to the second comparator input <NUM>. At the fifth tap <NUM> of the voltage divider <NUM>, a reference voltage VREF is tapped.

The values of the first and the second comparator reference voltage VH, VL are configured such that the gain of the conversion of the resistance value of the series circuit <NUM> into a digital value is set. A high gain results from a small difference between the first and the second comparator reference voltage VH, VL. Advantageously, different voltage values can be tapped from the same voltage divider <NUM>. The voltage divider <NUM> is fabricated as a resistor divider.

<FIG> shows an example of a table illustrating simulation results of the sensor arrangement <NUM> shown above. A first column shows resistance values in MΩ that are selected for the sensor resistor <NUM>. A second to a fourth column shows calculated resistance values of the sensor resistor <NUM> in MΩ. In the simulation for calculating the values of the second column the first phase A and the second phase B are used alternatively. In the third column and in the fourth column, the first phases A or the second phases B are omitted. Due to the high influence of the second leakage current IL2 the resistance values in the third and the fourth column deviate from the input resistance value shown in the first column and also from the resistance values in the second column. By using the measurement method shown above, the deviation from the calculated resistance values of the sensor resistor <NUM> to the input resistance values can be kept small.

The above described sensor arrangement <NUM> was simulated for the measurement mode of operation and the reference mode of operation. The values the Trise, Tfall and Tperiod were measured for various resistance values of the sensor resistor <NUM> (<NUM> MΩ, <NUM> MΩ, <NUM> MΩ, <NUM> MΩ and <NUM> MΩ). The chosen value of the leakage current IL2 was <NUM>% of the signal current ISIG (leakage is modelled using a resistor Rleak that is five times the resistance value of the sensor resistor <NUM>). The resistance value RS of the sensor resistor <NUM> is calculated by: <MAT>.

Equations are the same since for a chosen integration time AtimeS (RS+RREF) and AtimeR (RS). <MAT> <MAT> <MAT> and <MAT> wherein RS is the resistance value of the sensor resistor <NUM>, RREF is the resistance value of the reference resistor <NUM>, SD1 is the value of the first digital signal, SD2 is the value of the second digital signal, AtimeS is the conversion time in the measurement mode of operation and AtimeR is the conversion time in the reference mode of operation.

The simulated results for the various resistance values of the sensor resistor <NUM> are shown in <FIG>. According to the simulation, calculated resistance values of the sensor resistor <NUM> have less than <NUM>% error when using Tperiod for calculation. Using Trise or Tfall introduces an error comparable to the fraction of the IL2/ISIG. In the above results, the error is ~<NUM>% that is same fraction of IL2/ISIG.

A change of the parameter to be measured (e.g. a gas concentration) is converted into a change of the resistance value RS of the sensor resistor <NUM> that is converted into a change of a frequency of the triangles of the integrator output voltage OPOUT that is converted into a change of the first digital signal SD1.

Thus, the sensor arrangement <NUM> realizes a high-accuracy gas sensor for wide dynamic range of operation (<NUM> kΩ to <NUM> MΩ and higher). Pad/ESD leakage is compensated (ISIG > IL2) for/with the sensor arrangement <NUM>. Leakage drift with temperature and other factors (supply, process) can also be compensated in the sensor arrangement <NUM>.

<FIG> shows a further example of an embodiment of the sensor arrangement <NUM> that is a further development of the above shown embodiments, especially as shown in <FIG>. The sensor arrangement <NUM> comprises a logic circuit <NUM>. An input of the logic circuit <NUM> is coupled to the first latch output <NUM> of the latch <NUM>. An output <NUM> of the logic circuit <NUM> is connected to the calculation circuit <NUM>, to the first counter input <NUM> of the synchronous counter <NUM> and to the control logic <NUM>. The first clock signal CLK1 may be provided to the logic circuit <NUM>. The logic circuit <NUM> provides the output signal C1 at the output <NUM> of the logic circuit <NUM>.

The sensor arrangement <NUM> comprises a further latch <NUM>. A first latch input <NUM> of the further latch <NUM> is coupled to the first latch output <NUM> of the latch <NUM>. The first latch input <NUM> of the further latch <NUM> receives the first latch signal QL. A second latch input <NUM> of the further latch <NUM> receives the first clock signal CLK1. A latch output <NUM> of the further latch <NUM> is connected to a further input of the logic circuit <NUM>. The further latch <NUM> generates a further latch signal QR at the latch output <NUM> of the further latch <NUM>. The further latch <NUM> may be implemented as a D-latch, a D-flip-flop, and/or a transparent D-flip-flop. The further latch <NUM> may be realized such as the latch <NUM>. The two latches <NUM>, <NUM> may form a master-slave D flip-flop.

In an alternative embodiment, not shown, the further latch <NUM> is omitted. An input side of the logic circuit <NUM> is connected to the latch <NUM>.

In an example not shown, and not being part of the present invention, the latch <NUM> and the further latch <NUM> are omitted. An input side of the logic circuit <NUM> may be connected to the comparator <NUM> and, optionally, also to the further comparator.

<FIG> shows an example of signals of the sensor arrangement <NUM> of <FIG> which is a further development of the signals shown in <FIG>. The further latch signal QR is a function of the first latch signal QL and of the first clock signal CLK1. The logic circuit <NUM> receives the further latch signal QR of the further latch <NUM> and generates the output signal C1. The logic circuit <NUM> may receive the first latch signal QL of the latch <NUM>. Thus, the logic circuit <NUM> may generate the output signal C1 using the first latch signal QL and the further latch signal QR.

The output signal C1 is generated after the rising edge and after the falling edge of the first latch signal QL by the logic circuit <NUM>. Thus, the output signal C1 is generated at the rising edge and at the falling edge of the further latch signal QR by the logic circuit <NUM>. A pulse of the output signal C1 may be generated e.g. by inverting the further latch signal QR and by performing a logical AND function of the inverted further latch signal QR and the first latch signal QL. For example, the pulses of the output signal C1 at the second and the fourth point of time t2, t4 may be generated in this manner. Optionally, a further pulse of the output signal C1 may be generated e.g. by inverting the first latch signal QL and by performing a logical AND function of the inverted first latch signal QL and the further latch signal QR. For example, the pulse of the output signal C1 at the third point of time t3 may be generated in this manner. The logic circuit <NUM> uses the information provided by the two AND functions and shapes the output signal C1 according to the first clock signal CLK1.

The output signal C1 may have a pulse duration of <NUM> T1. A pulse of the output signal C1 may be between two pulses of the first clock signal CLK1, as shown in <FIG>. A pulse of the output signal C1 may rise with the falling edge of a pulse of the first clock signal CLK1. The logic circuit <NUM> may comprise not-shown NOR gates, NAND gates, inverters, delay circuits and other gates for performing the AND functions and for shaping the pulse of the output signal C1.

Alternatively, a pulse of the modified latch output signal C1 may be simultaneous to a pulse of the first clock signal CLK1. Thus, a pulse of the output signal C1 may rise with the rising edge of a pulse of the first clock signal CLK1. <FIG> shows an example of details of the sensor arrangement <NUM> that is a further development of the above shown embodiments especially as shown in <FIG> and <FIG>. The logic circuit <NUM> comprises a further output <NUM> that is coupled to the control logic <NUM>. The first input <NUM> of the control logic <NUM> is connected to the output <NUM> of the logic circuit <NUM>. The second input <NUM> of the control logic <NUM> is connected to the further output <NUM> of the logic circuit <NUM>. The further output <NUM> is realized as an inverted output and provides a signal C1I. The signal C1I is the inverted signal of the output signal C1.

Claim 1:
A sensor arrangement, comprising
- a switchable voltage source (<NUM>) having a source output (<NUM>) for alternatively providing a first and a second excitation voltage (V1, V2),
- an integrator (<NUM>) having an integrator input (<NUM>) and an integrator output (<NUM>),
- a sensor resistor (<NUM>) having a first terminal (<NUM>) coupled to the source output (<NUM>),
- a reference resistor (<NUM>) having a first terminal coupled to a second terminal (<NUM>) of the sensor resistor (<NUM>) and a second terminal coupled to the integrator input (<NUM>),
- a comparator (<NUM>) having a first comparator input (<NUM>) coupled to the integrator output (<NUM>), wherein the comparator (<NUM>) comprises a second comparator input (<NUM>) to which a first and a second comparator reference voltage (VH, VL) is alternatively provided,
- a latch (<NUM>) having a first latch input (<NUM>) coupled to a comparator output (<NUM>) of the comparator (<NUM>) and a first latch output (<NUM>),
- a logic circuit (<NUM>) having an output (<NUM>) and having an input coupled to the first latch output (<NUM>) of the latch,
- a calculation circuit (<NUM>) that is coupled to the output (<NUM>) of the logic circuit (<NUM>), wherein the calculation circuit (<NUM>) comprises an output for providing a result signal.