Patent Description:
A particular advantageous application of the present invention is for the production of photovoltaic cells intended for generating electrical energy, but the invention also applies, more generally, to any structure in which an incoming radiation is converted into an electrical signal, such as photodetectors and ionizing radiation detectors.

Interdigitated back-contact silicon heterojunction solar cells (IBC-SHJ) currently hold the world-record efficiency for crystalline silicon solar cells. See: <NPL>. However, the successful spread of IBC-SHJ devices is hindered by their highly complex processing. Indeed, the realization of IBC-SHJ devices requires patterning the rear a-Si:H layers and TCO/metal stacks into interdigitated combs, with an accuracy of ~<NUM>. Most of the techniques known from the state-of-the-art rely on the extensive use of photolithography and wet-etching steps, which result in a complex and costly process, see for example:.

In another example, the document <CIT> describes a device requiring two patterning steps needing an insulating layer between the charge carrier collecting structures also defined as fingers. One of the charge collecting structures is of the n-doped type or the p-doped type and the other charge carrier collecting structure, is of the other doped type. The device described in <CIT> is not cost effective because of the extensive use of photolithography.

Document <CIT> describes another device requiring two patterning steps, but it needs an insulating layer between the n-and p-fingers which makes the process complex. Alternatively, laser ablation can be used, see <NPL>. However, in this technique, to prevent severe damages to the a-Si:H layers, due to the absorption of the laser radiation, buffer layers must be deposited on top of them, which makes this process very complex.

In still another document <CIT>, two patterning steps are used, and a buffer layer to insulate the n- and the p-type charge collecting structures is required. This buffer layer is afterwards laser-patterned, therefore damages to the a-Si:H layers are difficult to avoid, leading to a device with limited lifetime.

Regardless of the chosen patterning technique, all the afore-mentioned approaches require to pattern both the electron- and the hole-collecting structures. <FIG> shows a typical design of a prior art IBC-SHJ solar cell in which both the n-type and the p-type a-Si:H layers <NUM>, <NUM> are patterned. This makes the realization of all of the IBC-SHJ devices lengthy, delicate, and thus strongly cost-ineffective.

To tackle this issue, some other alternatives propose to pattern only a first silicon layer <NUM> which is an n-doped layer or a p-doped layer, i.e. an electron- or a hole-collecting structure. A second silicon layer <NUM> of a second type is, in these alternative devices, fully deposited on top of the patterned charge-collecting structures <NUM>, as illustrated in <FIG>. Said second silicon layer <NUM> is of the opposite type as the type of the first silicon layer <NUM>, i.e. if the first silicon layer <NUM> is of the n-doped type, said second silicon layer <NUM> is of the p-doped type and vice-versa. The resulting device, illustrated in <FIG>, is called a "tunnel IBC-SHJ device". In an exemplary realization of the device of prior art illustrated in <FIG>, the first type of the charge collecting structure is an n-type a-Si:H finger, and only this n-type a-Si:H is patterned. In said exemplary realization of the device of <FIG>, a p-type a-Si:H layer covers both the intrinsic a-Si:H buffer layer <NUM> as well as the patterned n-type a-Si:H fingers, i.e. said first silicon layer <NUM>. As one patterning step is saved in the prior art device of <FIG>, such a process flow results in a simpler and thus cost-effective process. In addition, said second silicon layer <NUM> generates a self-aligned collecting structure, which is of the opposite doped type with respect to the doped type of said first silicon layer <NUM>. The types of devices illustrated in <FIG> have reduced efficiencies compared to devices illustrated in <FIG> in which both of the charge carrier collecting finger types are structured. For example, in the document <CIT> there are FF and Voc losses compared to devices in which the two charge carrier collecting finger types are patterned. This is due to the fact that the tunnel layer used in <CIT> is homogeneous and has the same properties when situated on the intrinsic buffer layer <NUM> and on the patterned hole-collecting fingers.

Other examples of prior art cells are disclosed in <CIT> and <CIT>.

The present invention relates to a method for manufacturing a photovoltaic device according to claim <NUM> comprising the steps of:.

In an embodiment of the method, said second silicon layer is a microcrystalline type silicon layer and said intrinsic buffer layer is amorphous.

In an embodiment of the method said first layer is deposited so as to be amorphous to a distance of between <NUM> and <NUM> from its side facing said silicon-based substrate.

In an embodiment of the method said third layer is deposited so as to be amorphous to a distance of between <NUM> and <NUM> from its side facing said silicon-based substrate.

In an embodiment of said method, said first is deposited such that it is microcrystalline at its side away from said silicon-based substrate.

In an embodiment of the method said first and/or third layer is deposited so as to be microcrystalline to a distance of between <NUM> and <NUM> from their side away from said silicon-based substrate.

In an embodiment the method comprises further the following step between said step d) and said step e):.

The present invention will now be described in reference to the enclosed drawings where:.

<FIG> shows the basic configuration of the layers of the photovoltaic device <NUM> manufactured by a method according to the invention.

The photovoltaic device <NUM> comprises a silicon-based substrate <NUM> which may have an n-type doping or a p-type doping. The silicon based substrate <NUM> has a first face 2a situated to the opposite side of the incoming light (hv in <FIG>). On said first face 2a an intrinsic buffer layer <NUM> is situated. This intrinsic buffer layer <NUM> is an amorphous layer. The role of this intrinsic buffer layer <NUM> is to reduce the recombination rate of carriers at the rear surface of said silicon-based substrate <NUM>.

On said intrinsic buffer layer <NUM> a first silicon layer <NUM> is situated to the opposite side of the incoming light. Said first silicon layer <NUM> is a silicon layer having a doping of a first type which may be a p-type doping or an n-type doping. The role of said first silicon layer <NUM> is to collect electrons when it is of the n-type and to collect holes when it is of the p-type. Said first silicon layer <NUM> is a patterned layer situated on predetermined regions 4a of the intrinsic buffer layer <NUM>, as illustrated in <FIG>. Otherwise said, the first silicon layer <NUM> forms a plurality of regions, also defined as islands, of p-type doped or n-type doped silicon, situated on the intrinsic buffer layer <NUM>. Said islands are also defined as charge-collecting structures, or also defined as fingers. Said first silicon layer <NUM> is preferably made out of n-type amorphous silicon (a-Si:H) or proto-crystalline silicon (pc-Si:H) or nano-crystalline silicon (nc-Si:H) or micro-crystalline silicon (µc-Si:H) or any combination or stack of these layers or any alloys made using these layers (such as oxygen or carbon alloying).

In an embodiment the first silicon layer <NUM> comprises an at least partially microcrystalline layer at its side away from said silicon-based substrate <NUM> so as to assure a good contact with the second silicon layer <NUM> and the electrically conducting pads <NUM> which are further described. In an embodiment the first silicon layer <NUM> is entirely a microcrystalline layer.

The wording microcrystalline is defined by the Raman crystallinity of the concerned layer. The Raman crystallinity (χc) of a silicon layer is defined as follow (see e.g. <NPL>): <MAT> where A<NUM> , A<NUM> and A<NUM> denotes the area below the Gaussian peak at <NUM>-<NUM> (resp. <NUM>-<NUM> and <NUM>-<NUM>).

In the present document, a microcrystalline silicon layer is hence defined as a silicon layer whose Raman crystallinity is higher than <NUM> %. Conversely, an amorphous silicon layer is defined as a layer with χc < <NUM> %.

Between said predetermined regions 4a are located interstices <NUM> which are free of said first silicon layer material. In these interstices <NUM>, a third silicon layer <NUM> is situated to the side opposite to the incident light side, as further described in detail.

It has been remarked that when trying to deposit a microcrystalline layer on an amorphous intrinsic buffer layer <NUM> this microcrystalline layer presents a crystalline modification in the first nm from that intrinsic buffer layer <NUM> that leads to a thin amorphous portion 10a. This crystalline modification depends on the deposition parameters. In particular, said third silicon layer <NUM>, facing said intrinsic buffer layer <NUM>, is amorphous to the side of said intrinsic buffer layer <NUM> and comprises preferably a microcrystalline portion 10b to the side away from said intrinsic buffer layer <NUM>, as described in more detail further. The amorphous nature of the third silicon layer <NUM> to the side of said intrinsic buffer layer <NUM> allows reducing the carrier recombination rate at the interface between said third silicon layer <NUM> and said intrinsic buffer layer <NUM>. Said microcrystalline portion 10b of said third silicon layer <NUM> allows at least to improve the contact with electrical conducting pads, and so the charge collection efficiency.

A second microcrystalline silicon layer <NUM> is situated on said first silicon layer <NUM> to the side opposite to said intrinsic buffer layer <NUM>, as shown in <FIG> and <FIG>. Said second silicon layer <NUM> has a doping of a second type being the other of the p-type doping or the n-type doping with respect to said first type doping of said first silicon layer <NUM>. For example if the first silicon layer <NUM> has a p-type doping, the second silicon layer <NUM> has an n-type doping and vice versa.

In all embodiments of the invention said first silicon layer <NUM> and said third silicon layer <NUM> are both microcrystalline at their side away from said silicon-based substrate <NUM>. This ensures a good contact with respectively said second silicon layer <NUM> and said electrically conducting pads <NUM>.

In an embodiment said first silicon layer <NUM> is entirely microcrystalline. Entirely is defined as being over the entire volume of the layer.

In an embodiment said first silicon layer <NUM> and said third silicon layer <NUM> are both amorphous to their side facing said silicon substrate <NUM>, allowing to maintain a good passivation at the interface with said intrinsic buffer layer <NUM>. The thickness, defined perpendicular to the plane of the silicon layers, of the amorphous portion of said first silicon layer <NUM> and said third silicon layer <NUM> may be different.

In an embodiment, said third layer <NUM> is amorphous to a distance of between <NUM> and <NUM> from its side facing said silicon-based substrate <NUM>. Other distances are possible as well, such as a distance of <NUM> or a distance of <NUM>.

In another embodiment, said third silicon layer <NUM> is microcrystalline to a distance of between <NUM> and <NUM> from its side away from said silicon based substrate. Other distances are possible as well such as a distance of <NUM> or a distance of <NUM>.

As further described in the essential step of the manufacturing method of the invention, said second silicon layer <NUM> and said third silicon layer <NUM> are realized in a single process step. By realizing said second silicon layer <NUM> and said third silicon layer <NUM> in a single process step, said second silicon layer <NUM> and said third silicon layer <NUM> constitute a single layer, defined as the tunnel layer, whose properties are different when present on said intrinsic buffer layer <NUM> or on said first silicon layer <NUM>, for the reasons described before.

Said single tunnel layer ensures a good contact with electrically-conducting pads, preferably TCO/metal conducting pads as illustrated in <FIG> and <FIG>.

Otherwise said, the tunnel layer comprises a first portion and a second portion: a first portion, i.e. said second silicon layer <NUM>, situated on said first silicon layer <NUM>, and a second portion, i.e. said third silicon layer <NUM>, situated on said intrinsic buffer layer <NUM>, comprising an amorphous layer portion 10a to the side of said intrinsic buffer layer <NUM>, and a microcrystalline layer portion 10b to the side away from said intrinsic buffer layer <NUM>. The fact that said second silicon layer <NUM> covers said first silicon layer <NUM> does not impede the charge collecting operation of the device provided that the doping and the thickness of the tunnel layer is carefully chosen. A detailed example is described further.

To summarize, the portion of said tunnel layer which is situated on said interstices <NUM>, i.e. said third silicon layer <NUM>, has unique properties which cannot be achieved by IBC-SHJ photovoltaic devices of prior art. Indeed, the amorphous portion of said tunnel layer ensures a good passivation to the intrinsic buffer layer <NUM> and on the other hand, the microcrystalline nature of said tunnel layer, to the side away from said intrinsic buffer layer <NUM>, ensures a good contact to the electrically conducting pads <NUM>, and ensures also substantially similar and elevated charge collection efficiencies of the two types of charge collecting structures, i.e. said first silicon layer <NUM> and said third silicon layer <NUM>.

The different properties of said first and said second portion of the tunnel layer, depend on whether said first and second portion is situated on said intrinsic buffer layer <NUM> or on said first silicon layer <NUM>, and are achieved by the fabrication method which is described further. Said tunnel layer is an important aspect of the present invention and alleviates most of the limitations of IBC-SHJ photovoltaic devices of prior art because it allows to realize electron and hole collecting structures in a single process step, which makes the device very efficient and cost effective.

The different possible doping combinations of the silicon-based substrate <NUM>, the first silicon layer <NUM>, the second silicon layer <NUM> and the third silicon layer <NUM> are summarized in the table <NUM> :.

For example, a preferred embodiment (example <NUM> of table <NUM>) of the photovoltaic device <NUM> (example <NUM> of table <NUM>) comprises an n-type silicon based substrate <NUM>, an n-type first silicon layer <NUM>, a p-type second silicon layer <NUM> and a p-type third silicon layer <NUM>. In this preferred embodiment, the tunnel layer, which comprises said second silicon layer <NUM> and said third silicon layer <NUM>, constitutes a single p-type tunnel layer. More precisely, in this preferred embodiment, holes are collected by the p-type third silicon layer <NUM> and the electrons are collected by the n-type first silicon layer <NUM>, and then tunnel to an electrode <NUM> through the p-type silicon layer <NUM>. In this example the portion of the tunnel layer covering the n-type first silicon layer <NUM> is of the p-type, i.e. a p-type second silicon layer <NUM>. This p-type second silicon layer <NUM> does not impede the electron collecting operation of the device, provided that the doping and the thickness of the p-type tunnel layer is correctly chosen, as electrons will tunnel through that portion of the tunnel layer corresponding to said p-type second silicon layer <NUM>.

It should be clear that different variants of the crystallographic transition of the amorphous side to the microcrystalline side of said third silicon layer <NUM> are possible. This crystallographic transition may be a substantially linear transition or may be another transition such as an exponential transition, or a substantial step-like transition.

The thickness of said tunnel layer, i.e. the thickness of said second silicon layer <NUM> and said third silicon layer <NUM> is preferably between <NUM> and <NUM>, more preferably between <NUM> and <NUM>, even more preferably between <NUM> and <NUM>.

The Raman crystallinity of the portion 10b of said third silicon layer <NUM>, is preferably between <NUM>% and <NUM>%, preferably between <NUM>% and <NUM>%, more preferably between <NUM>% and <NUM>%.

In the case the second silicon layer <NUM> is partially crystalline, its crystalline portion has a Raman crystallinity between <NUM>% and <NUM>%, preferably between <NUM>% and <NUM>%, more preferably between <NUM>% and <NUM>%.

In any embodiment the microcrystallinity of the second <NUM> and third layer <NUM> may be different.

In an embodiment a metal oxide layer may be situated between the silicon layers <NUM> and <NUM> and the electrodes <NUM>. The metal oxide layer may be made of MoOx, or VaOx, or HfOx and acts as a carrier selective contact. Said metal oxide layer may be patterned with any method known from prior art.

It is generally understood that the photovoltaic device <NUM> made by the method of the invention may comprise several different layers situated to the incident light side of the silicon-based substrate <NUM>. Typical layers, illustrated in <FIG>, are a buffer layer <NUM>, which may be different than said intrinsic buffer layer <NUM>, a front layer <NUM> which is preferably an amorphous layer of the same type as the type of said silicon-based substrate <NUM>, and an anti-reflection layer <NUM>. It is understood that other layers than the ones described above may be situated in the photovoltaic device <NUM>.

The invention is achieved by a method of manufacturing of a photovoltaic device according to claim <NUM>, illustrated in <FIG>, comprising the steps of:.

The advantage of the method of the invention is that said second silicon layer <NUM> and the portion of said third silicon layer <NUM> situated to the side away from said intrinsic buffer layer <NUM>, are both micro-crystalline which improves considerably the device performances due to reduced transport losses. Another advantage of the method is that the contact of said second silicon layer <NUM> and said third silicon layer <NUM> with a TCO layer of the conducting pads <NUM> is improved and is less sensitive to process variations of the deposition of a standard TCO layer.

An important advantage of the method of the invention is that a fast and easily up-scalable process may be used to make BC-SHJ devices, as only one patterning step is required. In a preferred method, the single patterning step is performed to realize electron collecting structures, i.e. an n-type first silicon layer <NUM>.

In a preferred embodiment of the method, said intrinsic buffer layer <NUM> is an amorphous layer.

In an embodiment of the method said third silicon layer <NUM> is deposited so as to be substantially amorphous to a distance of between <NUM> and <NUM> from its side facing said silicon-based substrate <NUM>.

In another embodiment of the method said third silicon layer <NUM> is deposited so as to be microcrystalline to a distance of between <NUM> and <NUM> from its side away from said silicon-based substrate <NUM>.

In an embodiment of the method said first silicon layer <NUM> is deposited so as to be amorphous to a distance of between <NUM> and <NUM> from its side facing said silicon-based substrate <NUM>.

In another embodiment of the method said first silicon layer <NUM> is deposited so as to be microcrystalline to a distance of between <NUM> and <NUM> from its side away from said silicon-based substrate <NUM>. In variants of the method, the deposited thickness of said first <NUM> and said third <NUM> silicon layer may be different. Also, the thickness of the crystalline portion of said first <NUM> and said third <NUM> silicon layer may be different in the case that said first silicon layer <NUM> is not entirely microcrystalline and comprises a microcrystalline layer to the side away from said intrinsic buffer layer (<NUM>).

It is generally understood that the lateral dimensions of said first, second and third silicon layers <NUM>, <NUM>,<NUM>, defined in their planes, may be different.

In another embodiment of the method the following step is performed between said step d) and said step e):
d1) depositing a metal oxide layer on at least one of said second silicon layer <NUM> and said third silicon layer <NUM>. Said metal oxide layer may be a MoOx layer, a VaOx layer or a HfOx layer but not necessarily so. The metal oxide layer acts as a carrier selective contact and may be patterned with any method known from prior art.

In order to complete the disclosure of the method of fabrication, the detailed fabrication process of a preferred embodiment comprising a n-type Si substrate <NUM>, n-type first Si-layer <NUM>, p-type second Si-layer <NUM>, p-type third Si-layer <NUM>, is described in more details here below:.

The first, second and third silicon layers <NUM>, <NUM>, and <NUM> are deposited using a plasma-enhanced chemical vapor deposition (PECVD) reactor. For the n-type said first silicon layer <NUM>, a gas mixture of SiH<NUM>, H<NUM>, and PH<NUM> is used. For the p-type said second silicon layer <NUM> and said third silicon layer <NUM>, a gas mixture of SiH<NUM>, H<NUM>, and B(CH<NUM>)<NUM> is used. Note that in both cases D<NUM> gas can also be added to increase the gas dilution. The preferred deposition temperature is <NUM>° C. All first, second and third silicon layers <NUM>, <NUM> and <NUM> can, preferably, comprise in their first nanometer deposition thickness an intrinsic "seed layer". This seed layer is a amorphous layer and helps controlling the transition to the micro-crystalline growth regime within said first, second and third silicon layers <NUM>, <NUM>, and <NUM>. More precisely, the thicker said seed layer, the steeper the transition to the micro-crystalline regime will be in the first, second and third silicon layers <NUM>, <NUM>, and <NUM>.

If no seed layer is used at all, then the deposited first, second and third silicon layers <NUM>, <NUM> and <NUM> will be amorphous over most of their thickness; in contrast, if a thick seed layer is used, then said first, second and third silicon layers <NUM>, <NUM> and <NUM> will be at least partially micro-crystalline over their whole thickness. In other words, the thickness of said seed layer, said seed layer being part of said first, second or third silicon layers <NUM>, <NUM>, <NUM>, controls the depth of the amorphous-to-micro-crystalline transition within said first, second and third silicon layers <NUM>, <NUM> and <NUM>. More precisely, in a preferred embodiment of the invention, said first silicon layer <NUM> is micro-crystalline: therefore a rather thick seed layer is used (<NUM> to <NUM>-nm-thick) for the deposition of the first silicon layer <NUM>, so as to obtain a rapid transition to the micro-crystalline regime on the amorphous buffer layer <NUM>.

In contrast, the amorphous layer 10a (which is part of said third silicon layer <NUM>) is obtained through the use of a thin seed layer, typically <NUM>-nm-thick. The use of a amorphous layer 10a allows to maintain a good passivation at the interface between said intrinsic buffer layer <NUM> and the third silicon layer <NUM>, therefore resulting in better efficiency of the final device. As explained before, said second silicon layer <NUM> and third silicon layer <NUM> altogether constitute said tunnel layer as described before. Therefore, said tunnel layer is realized by the deposition at the same time of the second silicon layer <NUM> and the third silicon layer <NUM>, i.e. both layers <NUM>,<NUM> are deposited with the same parameters. Said silicon layer <NUM>, having a thin seed layer as said third silicon layer <NUM>, will be however completely micro-crystalline, because it is grown on top of said first silicon layer <NUM>, which comprises always, to the side away from <NUM>, a microcrystalline layer Overall, the seed layer can have thicknesses ranging from <NUM> (i.e. no seed layer at all) to <NUM>. The total thickness of said first, second and third silicon layers <NUM>, <NUM> and <NUM>, including the thickness of said seed layer, ranges typically between <NUM> and <NUM>.

For the seed layer and the doped layers required for the first, second and third silicon layers <NUM>, <NUM> and <NUM>, two deposition regimes have been identified. In a first preferred regime called the "high power/high pressure" regime, the PECVD is operated at <NUM>, the pressure is set between <NUM> and <NUM> mbar during the layer deposition, and the power density is preferentially close to <NUM> W/cm<NUM>. In a second regime called "low power/low pressure", the PECVD is operated at <NUM>, the pressure is set between <NUM> and <NUM> mbar, and the power density is preferentially close to <NUM> W/cm<NUM>. Note that usually, the same regime is used for the seed layer and the doped layer: e.g., if the "high power/high pressure" regime is used for the seed layer of layer <NUM>, then the same regime will be used for the doped part of layer <NUM>. Combinations of the two regimes within the first, second and third silicon layers <NUM>, <NUM> and <NUM> are however possible.

In the "high power/high pressure" regime, the (H<NUM>+D<NUM>)/SiH<NUM> ratio for the seed layer is <NUM>, whereas it is <NUM> in the "low power/low pressure" regime. These parameters are the same regardless if the seed layer is used in the first silicon layer <NUM> or in the second and third silicon layers <NUM> and <NUM>.

For the n-type first silicon layer <NUM>, the (H<NUM>+D<NUM>)/SiH<NUM> and the (H<NUM>+D<NUM>)/PH<NUM> ratios are <NUM> and <NUM>, respectively, in the "high power/high pressure" regime, whereas it is <NUM> and <NUM>, respectively, in the "low power/low pressure" regime.

For the p-type second and third silicon layers <NUM> and <NUM>, the (H<NUM>+D<NUM>)/SiH<NUM> and the (H<NUM>+D<NUM>)/B(CH<NUM>)<NUM> ratios are <NUM> and <NUM>, respectively, in the "high power/high pressure" regime. Note that the "low power/low pressure" regime is not favorable for the deposition of the doped part of the second and third silicon layers <NUM> and <NUM>.

The experimental parameters of the explained detailed process steps described above are summarized in the table <NUM> below.

Note that the deposition parameters presented above for said preferred embodiment comprising an n-type first silicon layer <NUM> can also be used to realize the other embodiments of the present invention, provided that the correct doping combinations are used (see [<NUM>]).

The method of manufacturing and the description of the structural features of the following exemplary tunnel IBC device illustrates an example not forming the present invention.

Description of the process flow of an exemplary tunnel IBC-SHJ device not forming the present invention:
In order to realize the exemplary photovoltaic device <NUM> according to the invention, the following steps are performed:.

Description of the structural features of an exemplary tunnel IBC-SHJ device manufactured according to an example not forming the present invention.

An exemplary realization of the photovoltaic device <NUM>, realized with the above-described process steps has the following structural characteristics:.

The typical performances that are obtained with the exemplary device according to the invention are shown in Table <NUM>:.

Table <NUM> shows that, compared to the photovoltaic device manufactured according to the invention, the device described in <CIT> has a <NUM>% lower fill factor (FF) and a 30mV lower open-circuit voltage (Voc).

In <FIG> the relation between the measured current density in function of the operation voltage of the exemplary photovoltaic device <NUM> manufactured according to the invention is shown.

Claim 1:
Method for manufacturing of a photovoltaic device (<NUM>) comprising the steps of:
a. providing a silicon-based substrate (<NUM>) having a first face (2a), said silicon-based substrate (<NUM>) having a p-type or n-type doping;
b. depositing an intrinsic buffer layer (<NUM>) on said first face (2a);
c. depositing a patterned first silicon layer (<NUM>) on predetermined regions of said intrinsic buffer layer (<NUM>) thereby leaving interstices (<NUM>) between said predefined regions (4a), said first silicon layer (<NUM>) having a doping of a first type being one of p-type or n-type, said first silicon layer (<NUM>) comprising an at least partially microcrystalline layer at its side away from said silicon-based substrate (<NUM>);
d. simultaneously depositing a microcrystalline silicon layer (<NUM>) which forms said second silicon layer (<NUM>) on said first silicon layer (<NUM>) such that the second silicon layer (<NUM>) is in contact with the first silicon layer (<NUM>), and said third silicon layer (<NUM>) on said intrinsic buffer layer (<NUM>) exclusively at said interstices, said second silicon layer (<NUM>) having a doping of a second type being the other of p-type or n-type with respect to the doping of said first silicon layer (<NUM>), said third silicon layer (<NUM>) being amorphous at least at its side facing said silicon-based substrate (<NUM>) and being at least partially microcrystalline at its side away from said silicon-based substrate (<NUM>) and having a doping of said second type, said second silicon layer (<NUM>) and said third silicon layer (<NUM>) each defining a tunnel layer, with the doping and the thickness of said tunnel layer being chosen so that the second silicon layer (<NUM>) does not impede the charge collecting operation of the photovoltaic device.
e. depositing electrically conducting pads (<NUM>) on said second silicon layer (<NUM>) and said third silicon layer (<NUM>).