Patent Description:
In electronic devices, the power consumption is a function of the processing power. That is, increasing the processing power of a computer system often results in an increase in the power consumed by a computer system. However, for electronic devices, such as internet of things (loT) devices, it is important to keep the power consumption at a minimum. Low power consumption of electronic devices is critical when the power source is from energy harvesting.

To minimize power consumption of such devices, available solutions typically offer providing multiple processors or "execution functions" in a single device, each of which operates in a different power domain. Computing function may include basic arithmetic gates, logical gates, control units, and/or input/output devices. Some of the computing function may be trigged based on power events or scheduling events to further minimize the power consumption.

Conventional power consumption solutions and the architectures of the electronic devices assume that power may be limited, but is always available. For example, the power source may be a battery. As such, the conventional power consumption solutions are designed to complete a processing task at minimum utilization of power, without considering the power and energy required to perform each processing task. That is, the assumption is that there is always available power to complete a processing task. As such, the conventional power consumption solutions are not designed to consider the available energy at any given time, and in particular before executing a computing task.

In devices that operate at ultra-low power, e.g., loT devices that are based on energy harvesting, the conventional power consumption solutions may not be viable as energy is not always available and available power to perform a processing task may be sporadic.

<CIT> teaches an apparatus that has a signal processing system for executing a plurality of pre-determined signal processing tasks, and an energy source for powering the signal processing system in operational use of the apparatus. The energy source supplies an amount of energy that varies over the service life of the energy source. The signal processing system determines an amount of energy available from the energy source and selects for execution a specific one of the pre-determined signal processing tasks in dependence on the amount determined. <CIT> teaches a data processing device is configured to deploy, in response to an intermittent source of power, opportunistic power management strategies to manage harvested energy based on an expected amount of energy available to the data processing device and on expected energy expenditures defined by data processing and memory content control writing per formed by the data processing device. <CIT> teaches task processing based on power availability for mobile computing platforms including laptops, tablets, netbooks, cell phones, as well as for other devices or systems that are not mobile such as desktop computers and server systems. <CIT> teaches a task scheduling method and energy management device for a self energy supply system, and relates to the task scheduling field. The method comprises that risk coefficients of tasks in a preset task information table in the present moment are calculated according to execution time of the tasks; energy collected by the self energy supply system within a preset future period is predicted, and average power of the self energy supply system within the preset future period is obtained; self-adaptive voltage thresholds of the tasks in the present moment are calculated according to the risk coefficients, average power, average execution power and execution time of the tasks respectively; the self-adaptive voltage thresholds of the tasks are compared with a voltage value of an energy-storage capacitor in the present moment, and a task set in which the self-adaptive voltage thresholds are lower than the voltage value is obtained; and a task to be executed in the present moment is selected from the task set according to priorities of the tasks,.

It would therefore be advantageous to provide a solution that would overcome the challenges noted above.

A summary of several example embodiments of the disclosure follows. This summary is provided for the convenience of the reader to provide a basic understanding of such embodiments and does not wholly define the breadth of the disclosure. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later. For convenience, the term "some embodiments" or "certain embodiments" may be used herein to refer to a single embodiment or multiple embodiments of the disclosure.

An energy-aware computing system according to the invention is claimed in claim <NUM>. Certain embodiments disclosed include an energy-aware computing system comprising:
a microcontroller; an energy storage; a plurality of execution functions integrated in a system on chip (SoC); and a scheduler configured to schedule execution of operations based on available energy at the energy storage and energy required to complete each of the operations.

Certain embodiments disclosed also include a wireless internet of things (IoT) device, comprising: a radio frequency (RF) transceiver; and an energy-aware computing system configured to schedule execution of operations based on available energy and energy requires to complete each of the operations.

Certain embodiments disclosed herein also include a method for operating an energy-aware computing system. The method comprises determining if a current voltage level at an energy storage included in the energy-aware computing system is higher than a start voltage level; and scheduling an execution of at least one operation, by energy-aware computing system, when the operation's start voltage level is lower than the current voltage level.

The subject matter disclosed herein is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the disclosed embodiments will be apparent from the following detailed description taken in conjunction with the accompanying drawings.

It is important to note that the embodiments disclosed herein are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various embodiments. Moreover, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be in plural and vice versa with no loss of generality. In the drawings, like numerals refer to like parts through several views.

By way of example of the disclosed embodiments, an energy-aware computing system, and a method thereof are disclosed. In an embodiment, computing operations to be performed by the computing system are scheduled based on currently available power. The disclosed embodiments may be utilized in any computing system that operates on ultra-low power. In an example embodiment, such a computing system may include an loT device having an energy harvester as a power source.

<FIG> shows an example schematic diagram of an energy-aware computing system <NUM> according to an embodiment. The energy-aware computing system <NUM> includes a microcontroller unit (MCU) <NUM>, an energy storage <NUM>, a system on chip (SoC) <NUM>, a retention memory <NUM>, and a scheduler <NUM>.

The MCU <NUM> is a small computer on a single integrated circuit (IC). In some configurations, the MCU <NUM> contains one or more processor cores <NUM> and a program memory <NUM>. The program memory <NUM> may be in the form of RAM, flash or ROM. The MCU <NUM> is configured to execute embedded applications or processes. That is, each of the processor cores <NUM> may carry out the instructions of a computer program, stored in the program memory <NUM>, in order to perform the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions. Any process carried out by the MCU <NUM> has a state as described herein, and processes can communicate with each other through inter-process communication (IPC) protocol.

It should be appreciated that a process may be at a 'create' state when loaded from the program memory <NUM> or retention memory <NUM>. Then, the process is scheduled into a 'wait' state. In this state, the process waits for a context switch and loads the process into the processor core(s) <NUM>. The process's state then changes to a 'run' state, and the processor core(s) <NUM> execute the process's instructions.

If a process needs to wait for a resource (e.g., wait for a packet reception), it is assigned with a 'blocked' state. The process state is changed back to 'wait' when the process no longer needs to wait (in a blocked state). Once the process finishes execution, or is terminated, the process is removed instantly or is moved into the 'terminated' state.

In an embodiment, the MCU <NUM> consumes power required to execute one or more instructions of a process from the energy storage <NUM>. The power consumption is limited to only the actual power required to execute a certain process.

The energy storage <NUM> is charged with energy provided by an energy harvester (not shown). The energy can be harvested from any external sources (or over-the-air signals), such as radio signals, and the like. The harvested energy is stored in the energy storage <NUM>. The storage <NUM> may be realized as a capacitor, a battery, an on-die capacitor, and the like. An on-die capacitor is part of the integrated system, i.e., die on which the energy-aware computing system <NUM> is fabricated. In a semi-conductor fabrication, a die is a small block of semiconductor material, on which a given functional integrated circuit (IC) is fabricated. In an example implementation, the on-die capacitor is a metal capacitor formed using the metal layers as the "metallic plates" and dielectric layers as the dielectric medium of the die.

In an embodiment, the SoC <NUM> includes a number of execution functions realized as analog circuits, digital circuits, or both. Examples for such execution functions are provided below. The SoC <NUM> is also configured to carry out processes independently or under the control of the MCU <NUM>. Each process carried out by the SoC <NUM> also has a state, and processes can communicate with other processes through an IPC protocol. In the configuration illustrated in <FIG>, the SoC <NUM> loads the context of processes and read data from the retention memory <NUM>.

In an embodiment, the SoC <NUM> is partitioned into multiple power domains. Each power domain is a collection of gates powered by the same power and ground supply. To reduce the power consumption, only one power domain is turn on during execution.

Following are non-limiting example execution functions that may be implemented by the SoC <NUM>. A sequencer that can read from and write to memory, e.g., of peripherals and can execute simple logic operations. An asynchronous combinatorial logic for tracking power level of the SoC <NUM>.

Accelerators may be utilized to generate and prepare data packets for transmission. This may include CRC generation, packet whitening, an encryption/decryption engine, and a random number generator.

Digital logic for converting data from parallel to serial and staging the packet bits to the analog transmitter path for transmission. This function may also include calibration logic, e.g., FLL calibration.

It should be noted that the SoC's <NUM> functions discussed above are only examples, and other or different functions can be implemented by the SoC <NUM>. The disclosed embodiments required multiple power domains in the SoC <NUM>, where at each execution cycle only one power domain is on.

The retention memory <NUM> is a centralized area in the system <NUM> that is constantly powered. In an embodiment, data meant to be retained during low power states are located in the retention memory <NUM>. In an embodiment, the retention area is optimized to subthreshold or near threshold voltage, e.g., <NUM>. 3V - <NUM>. This allows for the reduction the leakage of the retention cells.

According to the disclosed embodiments, a process executed by the MCU <NUM> or the SoC <NUM> can load its state (or context) from the retention memory <NUM>. Further, a process executed by the MCU <NUM> or the SoC <NUM> can load its state (or context) and can write its context or processed data in the retention memory <NUM>. Always powering the retention memory <NUM> ensures that data is retained, even in the event the other components of the system <NUM> are powered off. The retention memory <NUM> can be realized using flip-flop, latches, or SRAM optimized for minimized power leakage.

In an example embodiment, the retention memory <NUM> is divided into retention domains (banks). Each such retention domain contains only needed values kept in retention cells (e.g., latches). The partitioning allows for banks to be powered on per configuration. Further, the logic of writing into the banks is power gated to minimize any overall power leakage.

In an example embodiment, the retention banks contain the following types of retention data: software retention maintaining static calibration and information needed for the full flow execution; hardware retention maintaining dynamic parameters temporary variables, and data packet to retain until data transmission; and MCU retention to maintain data utilized by the MCU <NUM>. It should be noted that the retention memory <NUM> may not be divided into retention banks, or can be divided to any number of banks, without departing from the scope of the disclosed embodiments.

The energy-aware computing system's <NUM> architecture allows executing a portion of a complete processing flow on several subroutines of a process based on the available energy. In an embodiment, before executing a process, or a portion thereof, the available energy at the energy storage <NUM> is checked to determine if there is enough available energy to execute and complete the process. If there is sufficient energy, the process or portion thereof is schedule for execution. To this end, the MCU <NUM> may be configured with energy requirements for each function and operation to be executed. The energy requirements may indicate, for example, an upper bound of energy that would be consumed by the function or operation.

In an embodiment, the check is performed for each computing block in the SoC <NUM> configured to run a process. This allows to better estimate the power consumption for running a process prior to its execution. As noted above, the computing blocks are operable in different power domains, and during each execution cycle only one such domain is power. The execution cycle is a time period where there is enough energy to complete at least one operation and writes the execution's results (context) to the retention memory.

In another embodiment, the scheduler <NUM> is configured to automatically save the context of any executed operation to the retention memory <NUM> when the voltage level at the storage <NUM> reaches a predefined threshold, e.g., VSTOP. In the next execution cycle for the same process, its context is retrieved from the retention memory <NUM>, and execution continues from where it stops.

Once a process completes its execution, the results and/or output are written to the retention memory <NUM>, and the MCU <NUM> and SoC <NUM> are powered off to enable maximal power saving. However, as noted above, the retention memory <NUM> always consumes power through static leakage. The energy storage <NUM> is charged with harvested energy, and a new execution cycle begins when there is sufficient energy. Then, a new process, or portion thereof, is scheduled for execution. Thus, the processing performed by the energy-aware computing system <NUM> is at the pace of charging the energy storage <NUM>.

It should be noted that a process may be any function, procedure, method, and the like executed either by the MCU <NUM> or blocks of the SoC <NUM> configured to perform a certain computing task, a controlling task, and the like. The process may be part of a program, application, and the like. A process may include one or more instructions. In an example implementation, instructions to be executed by the computing system <NUM> may be divided into one or more atomic operations. The instructions may be part of software, firmware, middleware, microcode, hardware description language, and the such. Instructions may include code (e.g., in source code format, binary code format, executable code format, or any other suitable format of code).

In an embodiment, the scheduling processes or atomic operations for execution in response to the available energy is managed by the scheduler <NUM>. The scheduling may be triggered by trigger signals, examples of which are provided below.

The scheduler <NUM>, in an embodiment, may break a process into multiple atomic operations (or sub-processes), each of which may be executed during a different execution cycle. Pointers to the subsequence atomic operations to be executed are saved in the retention memory <NUM>.

In one embodiment, the scheduler <NUM> is configured to schedule processes or atomic operations in a specific predefined order. Such an order of execution is determined by the application (e.g., receive or transmit wireless signals). An example of a sequence of operations is provided below.

In one embodiment, the scheduler <NUM> may be implemented in software, hardware, firmware, or any combination thereof. In one configuration, the operation of the scheduler <NUM> may be implemented by the MCU <NUM>. In another embodiment, the scheduler <NUM> may be part of the SoC <NUM>.

In an embodiment, the energy-aware computing system <NUM> may operate in two different energy-aware modes: an energy segmented software (ESS) mode and an MCU retention mode. The ESS mode allows for a device (e.g., an loT sensor) implementing the system <NUM> to operate in an environment with sparser energy available for harvesting. However, such a mode requires power efficient code with a predefined power budget. The MCU retention mode does not require a power budget, but rather the device implementing the system <NUM> should operate in an environment richer with available energy for harvesting.

Specifically, the energy segmented software (ESS), a process's code is segmented into atomic operations. The atomic operation includes a set of instructions where execution is completed during a single execution cycle. That is, there should enough energy in the storage <NUM> to complete execute of an atomic operation. In an embodiment, each atomic operation has a known and relatively small energy budget required for its execution and requires a small context, saved in the retention memory <NUM>, to define its initial state.

The MCU retention mode defines an additional and dedicated retention domain which retains the core logical flops (CM0p), core registers, control parameters and temporary parameters. This mode allows for seamlessly powering down the MCU <NUM> completely when the energy is not sufficient, and waking up the MCU <NUM> and enable the software to continue running from the point it halted when sufficient power becomes available.

It should be noted that the particular architecture shown in <FIG> is merely an example and that other architectures may be equally utilized without departing from the scope of the invention. In particular, the techniques for energy-aware computing disclosed herein may be implemented for computing systems other than SoCs such as shown in <FIG>.

<FIG> is an example simulation <NUM> illustrating the execution cycles of an energy-aware computing system designed according to the disclosed embodiments. In the example simulation <NUM>, three atomic operations <NUM>, <NUM>, and <NUM> are to be performed.

The graph <NUM> demonstrates the energy level at the energy storage <NUM> (<FIG>). The energy level in the storage <NUM> changes over time and increases as energy from external sources is received and harvested. The energy reception is demonstrated in graph <NUM>.

The first execution cycle starts at 't<NUM>' and ends at 't<NUM>', where operation <NUM> is executed (see graph <NUM>). The results of operation <NUM> are then written to the retention memory <NUM> (see graph <NUM>). The second execution cycle starts at 't<NUM>' and ends at 't<NUM>', where operations <NUM> and <NUM> are executed (see graphs <NUM> and <NUM>). Then, the results of operations <NUM> and <NUM> are written to the retention memory <NUM> (see graph <NUM>).

The next execution cycle starts at 't<NUM>' and ends at 't<NUM>', where operation <NUM> is executed (see graph <NUM>). Again, the results of operation <NUM> are written to the retention memory <NUM> (see graph <NUM>). The next execution cycle starts at 't<NUM>' and ends at 't<NUM>', where operation <NUM> is executed (see graph <NUM>). Again, the results of operation <NUM> are written to the retention memory <NUM> (see graph <NUM>). The next execution cycle starts at 't<NUM>' and ends at 't<NUM>', where operation <NUM> is executed (see graph <NUM>). Then, the results of operation <NUM> are written to the retention memory <NUM> (see graph <NUM>). This type of "wave" processing continues at the pace of the energy input.

As demonstrated the duration of an execution cycle may differ from one cycle to another. Further, in each execution cycle one or more operations, processes, or sub-processed can be executed, as long as there is sufficient energy available.

In an embodiment, a number of trigger signals are utilized to schedule execution. Such trigger signals may include, VSTART, VSTOP, a wake-up event, a timeout event. The VSTART signal defines a voltage level at the energy storage <NUM> to start an operation. The VSTOP signal defines a minimum voltage level at the energy storage <NUM> to end an operation. The VSTOP may be also triggered when there is no sufficient energy to start a task.

The VSTART and VSTOP signals may be set to respective predefined values. The VSTART and VSTOP signals may be dynamically adjusted. Specifically, the VSTART may be set to an initial value. If the voltage level at the energy storage <NUM> is above the VSTART initial value and the operation starts and immediately stops (upon receiving VSTOP trigger), the VSTART is increased by a predefined delta value. If an execution cycle is completed and no timeout signal is received, the VSTART is decreased by a predefined delta value. The VSTOP value is adjusted in a similar manner. It should be noted that the delta values may be different for the VSTART and VSTOP signals. It should be also noted that each VSTART and VSTOP signals may be different or the same for each of the operations. In an embodiment, the VSTOP is set to a voltage value allowing to write to the retention memory <NUM> after completion of execution.

A wake-up signal is an event that indicates that a specific operation or process should be performed in the next execution cycle. For example, calibration of a transmitter should start upon receiving a wake-up signal. The wake-up signal can be trigged by external events, such as energy detection, constant envelope detection, frequency detection, and the like.

<FIG> is an example flowchart <NUM> of a method for scheduling execution of operations in an energy-aware computing system according to an embodiment. At S310, the power level at the energy storage (e.g., energy storage <NUM>) is determined. This may include sensing or measuring the power level or voltage level at the energy storage.

At S320, the determined power level is compared to a minimum power level required to execute at least one operation. In an example embodiment, S320 may include comparing the voltage level (VDD) at the energy storage to a VSTART signal. The various embodiments to set a value of the VSTART signal are discussed above. If S320 results with a Yes answer (there is sufficient energy to execute a process), the method continues with S330; otherwise, execution returns to S310. It should be noted that S310 and S320 can be implemented through a single step, e.g., by using a comparator.

At S330, the operation to be executed is determined. In an example embodiment, the determination may be based on a predefined order of operations that should be performed. The order of operations may be designated in a routine descriptor record (RDR) maintained in the scheduler. That is, such a table indicates in-order operations (defined in the RDRs) to be executed consecutively. Each RDR record lists processor core command to call an operation and a physical address of the operation. The address may be a physical address either in the program memory (<NUM>, <FIG>) or retention memory (<NUM>, <FIG>). Each RDR may further define a power schema index (such as clock frequency and power/clock gating information) and a power voltage level (energy budget required to complete the operation).

At S340, the context and/or state of the operation to be executed is loaded from the memory. The memory may be the program memory and/or retention memory discussed above. Thereafter, the S350, the operation is executed during a current execution cycle. At S360, once the operation completes its execution, the results are saved in the retention memory. Then, execution returns to S310.

It should be noted that the method continues as new energy is harvested. It should be further noted that an operation as discussed with reference to <FIG> includes an atomic operation, a process, a sub-process, a routine, and the like.

<FIG> is an example block diagram of a wireless loT device <NUM> implementing the energy-aware computing system according to an embodiment. The wireless loT device <NUM> includes a harvester circuity <NUM> coupled to an antenna <NUM>. The harvester circuity <NUM> is also coupled to an energy-aware computing system (EACS) <NUM>, and a radio frequency (RF) transceiver <NUM>. The harvester circuity <NUM> serves as the power source of the wireless loT device <NUM> designed to communicate using a low power communication protocol. Examples for such a protocol includes, but are not limited to, Bluetooth low energy (BLE), Bluetooth®, LoRa, Wi-Gi®, nRF, DECT®, Zigbee®, Z-Wave, EnOcean®, and the like. The loT device <NUM> may further include a sensor (not shown). The sensor may be of various types including, but not limited to, temperature, humidity, weight, oxygen, CO2, pressure, location, bio-feedback, water, acoustic, light, and so on.

The wireless loT device <NUM> can operate at different modes (e.g., scan, sleep, receive, transmit, etc.), each such mode may require a different voltage level to power the EACS <NUM> and RF transceiver of the wireless loT device <NUM>. In an embodiment, the harvester circuity <NUM> is configured to provide multiple voltage levels to the wireless loT device <NUM>, while maintaining a low loading DC dissipation value. Specifically, the harvester circuity <NUM> may provide multi-level voltage level indications to the EACS <NUM>. These indications allow the EACS <NUM> (and in particular the scheduler) to determine the state of a voltage supply (VDD) at any given moment when the energy storage charges or discharges.

The antenna <NUM> may be implemented as a receive/transmit antenna of the wireless loT device <NUM>. That is, in such a configuration, the antenna <NUM> is primarily designed to receive/transmit wireless signals according to the respective communication protocol of the wireless loT device <NUM> (e.g., <NUM>-<NUM> signal for BLE). In another embodiment , falling outside of the scope of the claims but useful for understanding the invention, the antenna <NUM> may be designed solely for the energy harvesting and operate in a different frequency band, direction, or both, then those defined in the standard of the respective communication protocol. It should be noted that in both configurations, energy can be harvested from any wireless signals received in the air.

The EACS <NUM> may be implemented and operate as discussed in detail above. That is, the EACS <NUM> is configured to schedule operations according to the power budget and the available energy. The transceiver <NUM> is configured to transmit and receive wireless signals under the control of the EACS <NUM>. In an embodiment, the transceiver <NUM> is a BLE transceiver.

According to some embodiments, the EACS <NUM> schedules operations in a specify sequential order to allow for proper transmission and reception of packets. An example sequence of operations in a BLE transceiver is now described.

Once sufficient energy has been harvested (e.g., VDD > VSTART), a sensing operation is performed, followed by a BLE packet preparation (e.g., CRC generation, packet whitening). In an embodiment, the preparation is trigger by BLE advertisement packets detected by the loT device <NUM>. The next operation is encryption of the packet.

Then, the EACS <NUM> waits for a wake-up event that may be triggered by energy detection, constant envelope detection, or frequency detection of external wireless signals. Such signals may include, for example, a BLE advertisement packet signal, an ultra-wideband (UWB) RFID reader signal in the <NUM> bands, a <NUM> RFID reader signal, a single tone reference at any of the industrial, scientific and medical (ISM) bands, a modulated reference at any of the ISM bands, and an RF signal in the Wi-Fi spectrum (<NUM> or <NUM> bands). Then, a calibration operation to calibrate the various oscillators in the transceiver <NUM> is performed. Finally, when there is sufficient energy the packet is transmitted. It should be noted that a timer has to elapse before allowing transmission of the data packets.

The various embodiments disclosed herein can be implemented as hardware, firmware, software, or any combination thereof. Moreover, the software is preferably implemented as an application program tangibly embodied on a program storage unit or computer readable medium consisting of parts, or of certain devices and/or a combination of devices. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. Preferably, the machine is implemented on a computer platform having hardware such as one or more central processing units ("CPUs"), a memory, and input/output interfaces. The computer platform may also include an operating system and microinstruction code. The various processes and functions described herein may be either part of the microinstruction code or part of the application program, or any combination thereof, which may be executed by a CPU, whether or not such a computer or processor is explicitly shown. In addition, various other peripheral units may be connected to the computer platform such as an additional data storage unit and a printing unit. Furthermore, a non-transitory computer readable medium is any computer readable medium except for a transitory propagating signal.

It should be understood that any reference to an element herein using a designation such as "first," "second," and so forth does not generally limit the quantity or order of those elements. Rather, these designations are generally used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed there or that the first element must precede the second element in some manner. Also, unless stated otherwise, a set of elements comprises one or more elements.

As used herein, the phrase "at least one of" followed by a listing of items means that any of the listed items can be utilized individually, or any combination of two or more of the listed items can be utilized. For example, if a system is described as including "at least one of A, B, and C," the system can include A alone; B alone; C alone; A and B in combination; B and C in combination; A and C in combination; or A, B, and C in combination.

Claim 1:
An energy-aware computing system (<NUM>, <NUM>), comprising:
a microcontroller (<NUM>);
an energy storage (<NUM>);
the system being CHARACTERIZED BY:
an antenna (<NUM>) adapted for communication and to convert external wireless signals that impinge on the antenna into electrical energy;
an energy harvester (<NUM>) coupled to the antenna and the energy storage, wherein the energy harvester harvests energy from the external wireless signals that impinge upon the antenna and supplies the harvested energy to the energy storage which stores the harvested energy therein;
a plurality of execution functions integrated in a system on chip (SoC) (<NUM>); and
a scheduler (<NUM>) configured to schedule execution of operations based on available energy at the energy storage, wherein the scheduler is further configured to determine if a current voltage level at the energy storage is higher than a start voltage level, the start voltage level being a minimum required voltage level required to start an operation, and wherein the start voltage level for at least one of the operations is dynamically adjusted.