Patent Description:
The field relates to mounting structures (e.g., mounting films or tapes) for integrated device packages.

Various types of integrated device packages include an integrated device die mounted to a carrier, which may comprise a second integrated device die. Stacking the integrated device die on the carrier may introduce stresses on the carrier, or vice versa. Furthermore, in some packages, the carrier (e.g., an integrated device die) can be wire bonded to another structure, such as a package substrate. In such packages, it can be challenging to provide adequate electrical isolation between portions of the carrier and portions of the integrated device die. Furthermore, stacking the integrated device die on the carrier may induce stresses in the carrier and/or in the die. Accordingly, there remains a continuing need for improved integrated device packages that include a die stacked or mounted on a carrier. <CIT> discloses a method for fabricating a large die package with a leadframe having leads and a paddle. An interposer is attached onto the leadframe with the interposer extending over at least a portion of the paddle and at least a portion of the leads of the leadframe. The interposer is insulated from the leads. A die is attached to the interposer. <CIT> discloses an integrated circuit package in package system. A first wire bonded die with an active side is mounted above a substrate and the active side of the first wire-bonded die is connected to the substrate with a bond wire. A wire-in-film adhesive, including an isolation barrier, is mounted over the first wire-bonded die. <CIT> discloses a low profile semiconductor package with a first and second stacked semiconductor die mounted to a substrate. The first and second semiconductor die are separated by a low profile intermediate adhesive layer in which the wire bond loops from the first semiconductor die are embedded. After the intermediate layer is applied, the second semiconductor die may be stacked on top of the intermediate layer. A dielectric layer may be formed on a back surface of the second semiconductor die. <CIT> discloses a technique to integrate passive components in a die assembly. A capacitor, inductor, or resistor is integrated on a spacer between upper and lower dies in stacked dies. Conductors are attached to the capacitor, inductor or resistor to connect the capacitor, inductor, or resistor to at least one of the upper and lower dies. <CIT> discloses a first die comprising a first array of light emitting units for emitting light, a second layer comprising a second array of via holes and a third die comprising a third array of light detecting units for detecting light from the first array of light emitting units. Light from the light emitting units passes through the second array of via holes and is detected by the third array of light detecting units.

Specific implementations will now be described with reference to the following drawings, which are provided by way of example, and not limitation.

It is to be noted that the embodiments throughout the description which are not explicitly indicated as being "according to (or in accordance with) the claimed invention" are to be understood as to be embodiments which do not form part of the claimed invention but are useful for understanding the invention.

Various embodiments disclosed herein relate to integrated device packages in which an integrated device die is stacked or mounted to a carrier. The carrier comprises another integrated device die. The die is mounted to the carrier by way of a mounting structure (such as a multi-layer mounting structure) that comprises a first layer of a first insulating material and a spacer of a second insulating material, with the second element disposed between the first layer and a back side of the integrated device die. In some embodiments, the first adhesive layer can comprise a flowable die attach film (DAF) that has a flowable state and a cured or hardened state. The spacer can comprise a solid insulating layer that can physically and electrically isolate at least a portion of the carrier from the back side of the integrated device die.

The carrier comprises a second integrated device die that is electrically connected by bond wires to a package substrate (such as a leadframe substrate, a laminate or printed circuit board substrate, a ceramic substrate, a hybrid substrate, glass, etc.). A portion of the wire bonds (or bond wires) is disposed between the carrier and the back side of the die. The portion of the wire bonds is embedded in the first layer, but the portion of the wire bonds does not penetrate the spacer. The spacer can therefore serve to physically and electrically isolate the bond wires from the back side of the integrated device die, which can beneficially reduce the risk of shorting out the signals transmitted through the bond wires.

In some embodiments, the spacer can comprise a solid back side coating applied to the back side of the integrated device die. In some embodiments, the second layer can be disposed or embedded between the first layer and a third layer comprising a third insulating material. In some embodiments, the third insulating material can comprise the same insulating adhesive material as the first insulating adhesive material of the first layer (e.g., a DAF). For example, in some embodiments, the third insulating material can comprise a first flowable state and a second cured or hardened state. In other embodiments, the third and first insulating materials may differ. In various embodiments, therefore, the first, second, and third layers can comprise a multi-layer mounting structure or tape for attaching a die to a carrier and for electrically isolating a back side of the die from the carrier.

The spacer (e.g., a floating spacer) is disposed between the integrated device die and the first layer. In various embodiments, the spacer can comprise a material that has a coefficient of thermal expansion (CTE) closely matched to the CTE of the integrated device die and/or the carrier. Beneficially, therefore, the spacer can serve to reduce or eliminate stresses imposed by the die on the carrier, and vice versa. In some embodiments, the spacer can also serve to electrically isolate the back side of the die from at least a portion of the carrier. In some embodiments, the spacer can comprise a material that can serve as an inductor or coil (or another structure), or a patterned material that can enhance the electrical characteristics of the package. For example, in some embodiments, the spacer can have energy-harvesting devices, sensing devices, etc. For example, in some embodiments, the spacer can comprise a material that is clear, visually transparent, opaque, etc. For example, in some embodiments, the spacer can comprise a band pass filter that filters certain wavelengths of light. For example, in some embodiments, the spacer can comprise a laminate substrate.

<FIG> is a schematic side view of an integrated device package <NUM> prior to mounting an integrated device die <NUM> to a carrier <NUM>. The integrated device die <NUM> can comprise any suitable type of device die that includes active circuitry or components, for example, a processor die with integrated circuitry formed or defined therein, a microelectromechanical systems (MEMS) die, a memory die, a sensor die, etc. The die <NUM> can comprise a front side <NUM> and a back side <NUM> opposite the front side <NUM>. In some embodiments, the active components or circuitry can be provided at or near the front side <NUM>. In other embodiments, the active components or circuitry can be provided at or near the back side <NUM>. As shown in <FIG>, an insulating layer <NUM> can be provided over the back side <NUM> of the integrated device die <NUM>. In some arrangements, the insulating layer <NUM> can comprise a die attach film (DAF) that is deposited, printed (e.g., screen printed), or laminated on the back side <NUM> of the die <NUM>. In some arrangements, the insulating layer <NUM> can be spread as a paste or epoxy over the die <NUM> or the carrier <NUM>. In some arrangements, the insulating layer <NUM> can comprise a sheet of insulating material that is applied to the back side <NUM> of the die <NUM>.

In <FIG>, the carrier <NUM> comprises a second integrated device die having active circuitry or other components, such as integrated circuitry, microelectromechanical systems (MEMS) components, etc. As with the integrated device die <NUM>, the carrier <NUM> can comprise a front side <NUM> and a back side <NUM> opposite the front side <NUM>. In the embodiment shown in <FIG>, the carrier <NUM> can be mounted to a package substrate (not shown), such as a leadframe substrate, a laminate or printed circuit board (PCB) substrate, a ceramic substrate, a hybrid substrate, glass, etc. One or more bond wires <NUM> can electrically connect bond pads on the front side <NUM> of the carrier <NUM> to another packaging structure, such as to corresponding leads or pads of the package substrate, or to another integrated device die. In other embodiments, however, the carrier <NUM> can comprise another packaging structure, such as a package substrate (see, e.g., Examples <NUM> and <NUM> of <FIG>).

<FIG> is a schematic side view of an integrated device package <NUM> after the integrated device die <NUM> is mounted to or stacked on the carrier <NUM>. In the arrangement shown in <FIG>, the die <NUM> and carrier <NUM> can be physically brought together. The insulating layer <NUM> can comprise a flowable state (e.g., when heated) and a hardened state (e.g., when cured, or after settling naturally into the cured state). In some arrangements, the insulating layer <NUM> can be heated or melted, for example, to cause the insulating layer <NUM> to be flowable. In some arrangements, for example, the insulating layer <NUM> can change to the flowable state upon heating the package <NUM>, for example, heating to a temperature in a range of <NUM> to <NUM> in some embodiments. The insulating layer <NUM> in the flowable state can flow around the bond wires <NUM> such that a portion of the bond wires <NUM> is embedded in the insulating layer <NUM>. The insulating layer <NUM> can change to the hardened or solid state. In some arrangements, the insulating layer <NUM> can harden as it cools. In other arrangements, the insulating layer <NUM> can be baked to harden the layer <NUM>. The hardened insulating layer <NUM> can thereby mechanically couple the die <NUM> to the carrier <NUM>.

One problem associated with the package of <FIG> is that the bond wires <NUM> may contact the back side <NUM> of the integrated device die <NUM>. For example, during assembly and/or use of the package <NUM>, the back side <NUM> of the die may shift downwardly and contact the bond wire(s) <NUM> in a region <NUM> shown in <FIG>. Contact between the back side <NUM> of the die and the bond wires <NUM> can cause an electrical short, which can reduce the performance of the package <NUM> and/or its components. In addition, the insulating layer <NUM> may electrically break down without any physical contact, e.g., in arrangements in which the physical thickness of the layer <NUM> or the separation between the die <NUM> and carrier <NUM> is not large enough relative to the applied voltage.

Accordingly, various embodiments herein can beneficially reduce or eliminate the risk of electrical shorting between the bond wires <NUM> and the die <NUM>. <FIG> is a schematic side view of a wafer <NUM>' temporarily mounted to a wafer mount <NUM> by way of a wafer tape having a structural layer <NUM> and an insulating adhesive layer <NUM>, according to various embodiments. The wafer <NUM>' can comprise a semiconductor wafer that is patterned or formed to comprise a plurality of the integrated device dies, which may be similar to the dies <NUM> shown in <FIG>. As shown in <FIG>, the insulating adhesive layer <NUM> can be applied over the back side of the wafer <NUM>', and the insulating layer <NUM> and structural layer <NUM> can couple the wafer <NUM>' to the wafer mount <NUM>. The wafer mount <NUM> can support the wafer <NUM>' during processing. Examples of the wafer tape include Adwill LE tape manufactured by Lintec Corporation of Japan, and Dicing Die Attach Film manufactured by Henkel AG & Co. of Germany.

<FIG> is an enlarged schematic side view of a portion of the wafer <NUM>' coupled with the structural layer <NUM> of the wafer tape by way of the insulating adhesive layer <NUM>. After dicing the wafer <NUM>' into a plurality of diced integrated device dies (e.g., the die <NUM> of <FIG>) and removing the structural layer <NUM>, the arrangement shown in <FIG> can be the same as or similar to the package <NUM> shown in <FIG>. For example, as explained above, utilizing the single insulating adhesive layer <NUM> to mount the die <NUM> to the carrier <NUM> may result in shorting of the bond wires <NUM> and the back side <NUM> of the die <NUM>.

<FIG> is an enlarged schematic side view of a portion of the wafer <NUM>' coupled with the wafer tape by way of a mounting structure <NUM>, according to some embodiments. Unlike the arrangement shown in <FIG>, in the embodiment of <FIG>, multiple insulating elements or layers can be used to couple the wafer <NUM>' with the wafer tape. In some embodiments, the mounting structure <NUM> can comprise a first layer <NUM> of a first insulating adhesive material and a second isolating film or layer <NUM> of insulating material between the first layer <NUM> and the wafer <NUM>'. As explained herein, the second layer <NUM> can serve to electrically isolate at least a portion of the carrier <NUM> (e.g., the bond wires <NUM>) from the back side <NUM> of the die <NUM>.

The second layer <NUM> can comprise a back side coat (BSC) layer that is deposited on the back side of the wafer <NUM>', e.g., by way of lamination, dispensing, screen printed, molded, etc. The second layer <NUM> can comprise any suitable insulating material that is solid or hard enough such that the bond wires <NUM> do not penetrate the layer <NUM>, and that electrically isolates the wires <NUM> from the die <NUM>. In various embodiments, the second layer <NUM> can comprise a polymer, e.g., a thermoset polymer, a polyimide film or tape, etc. Unlike the first layer <NUM>, in some embodiments, the second layer <NUM> may not have a flowable state, e.g., the second layer <NUM> may comprise a solid material without causing the layer <NUM> to flow or melt during assembly or manufacturing. In other embodiments, the second layer <NUM> can have a flowable state when it is applied to the wafer <NUM>', but can be hardened such that the layer <NUM> is not flowable after mounting the wafer <NUM>' to the wafer tape. In some embodiments, the second layer <NUM> (which, as explained above, can serve as an electrically isolating layer for the package) can comprise a non-penetrating tape which can be applied to the back side <NUM> of the wafer <NUM>', such as Adwill LC tape manufactured by Lintec Corporation of Japan.

<FIG> is a flow chart illustrate a method <NUM> for manufacturing an integrated device package, according to some embodiments. <FIG> illustrates a series of schematic side views of the package <NUM> at various stages of the method <NUM> shown in <FIG>, according to one embodiment. <FIG> illustrates a series of schematic side views of the package <NUM> at various stages of the method <NUM> shown in <FIG>, according to another embodiment. In <FIG>, the method <NUM> begins in a block <NUM>, in which a wafer <NUM>' having a plurality of integrated device regions is thinned from a back side of the wafer <NUM>' to define the back sides <NUM> of the dies <NUM> once the wafer <NUM>' is singulated or diced. The wafer <NUM>' can be thinned in any suitable way, for example, by etching, polishing, etc. Moving to a block <NUM>, the second back side coat (BSC) or isolating layer <NUM> can be applied or deposited on the back side <NUM> of the wafer <NUM>'. As explained above, the second layer <NUM> can comprise a non-conductive or insulating material that is applied over the back side <NUM> of the wafer <NUM>' in any suitable way. For example, the second isolating layer <NUM> can be deposited, laminated, screen-printed, molded, or otherwise provided on the back side <NUM> of the wafer <NUM>'.

For the embodiment of <FIG>, the method <NUM> moves to a block <NUM>. In the block <NUM>, and as shown in <FIG>, the method <NUM> includes applying the first insulating adhesive layer <NUM> (e.g., a die attach film, or DAF) over the second isolating layer <NUM> of the wafer <NUM>'. The first layer <NUM> can be applied over the second layer <NUM> in any suitable manner, e.g., deposited or screen printed onto the second isolating layer <NUM>. For example, as explained above in connection with <FIG>, the first insulating adhesive layer <NUM> can form part of the wafer tape (e.g., the layer <NUM> may be attached to the structural layer <NUM> of the wafer tape). The wafer <NUM>' can be mounted to the wafer tape, and the structural layer <NUM> can be removed to leave the insulating adhesive layer <NUM> attached to the isolating layer <NUM> on the back side <NUM> of the wafer <NUM>'.

In a block <NUM>, the wafer <NUM>' with layers <NUM>, <NUM> can be diced, e.g., sawed, punched, etc., to define a plurality of the integrated device dies <NUM>. Moving to a block <NUM>, each diced die <NUM> can be stacked or mounted to the carrier <NUM>. For example, the diced die <NUM> can be brought together with the carrier <NUM>, which can comprise another integrated device die in some embodiments. As shown in <FIG>, the carrier <NUM> can comprise a plurality of bond wires <NUM> configured to electrically connect bond pads on the front surface <NUM> of the carrier <NUM> to a packaging structure (such as a package substrate), which is not illustrated in <FIG>. The package <NUM> can be heated (e.g., to a temperature in a range of <NUM> to <NUM>) to cause the first insulating layer <NUM> to change to the flowable state. However, the heating may not cause the second isolating layer <NUM> to melt or otherwise be flowable. Thus, the second layer <NUM> can have a higher melting point than the first layer <NUM> in some embodiments. In other embodiments, however, the second layer <NUM> may not have a higher melting point than the first layer <NUM>. For example, once the second layer <NUM> is applied to the back side <NUM> and hardened, the second layer <NUM> may become a thermoset and may no longer melt. Accordingly, when the first layer <NUM> is heated and caused to flow, the second layer <NUM> may not be flowable but may remain solid.

As shown in step <NUM> of <FIG>, the first layer <NUM> can flow around the bonding wires <NUM> such that portions of the wires <NUM> are between the die <NUM> and the carrier <NUM> and such that the portions of the wires <NUM> are embedded in the first layer <NUM>. In the embodiment of <FIG>, the first layer <NUM> can comprise a sheet of insulating material (e.g., a DAF) applied over the second layer <NUM>. The first layer <NUM> can change to the hardened or cured state to mount or stack the die <NUM> to the carrier <NUM>. For example, in some embodiments, the first layer <NUM> may naturally harden or cure as it cools down. In other embodiments, the first layer <NUM> can be baked to cause the layer <NUM> to harden or cure.

Returning to <FIG>, after applying the BSC in the block <NUM>, in an alternative process, the method <NUM> can move to a block <NUM> including a block <NUM>. In the block <NUM>, the wafer <NUM>' with the second BSC isolating layer <NUM> can be diced to define a plurality of the integrated device dies <NUM>, e.g., by sawing, punching, laser etching, plasma etching, or any other suitable manner. Moving to a block <NUM>, the first layer <NUM> can be dispensed on the front side <NUM> of the carrier <NUM>. For example, the first layer <NUM> can comprise a flowable epoxy paste or adhesive in the flowable state, and can be dispensed around and/or over the bond wires <NUM> in any suitable manner. In some embodiments, for example in embodiments that provide a dispensed material with a syringe or other delivery vessel, the syringe can be heated and the dispensed epoxy material provided in any suitable pattern to control the flow and/or coverage of the epoxy. In various embodiments, the epoxy or other flowable material can be dispensed between the wires, e.g., in the middle portion of the die in the area inside or within the wire bond pads. Moving to the block <NUM>, the die <NUM> can be mounted to the carrier <NUM>. For example, the die <NUM> can be brought together against the first layer <NUM>. The first layer <NUM> can harden (e.g., by cooling) to mount the die <NUM> to the carrier <NUM>. In some embodiments, the die <NUM> can contact the first layer <NUM> when the first layer <NUM> is in the flowable state so as to improve adhesion between the die <NUM> and the first layer <NUM>.

Thus, in <FIG>, the first flowable layer <NUM> can be applied to the wafer <NUM>' prior to dicing the wafer <NUM>' into the plurality of dies <NUM>. By contrast, in <FIG>, the wafer <NUM>' can be diced after applying the second layer <NUM> and without applying the first layer <NUM> to the wafer <NUM>'. Instead, as explained above, in <FIG>, the first layer <NUM> can be applied to the carrier <NUM> and flowed around the wires <NUM> (e.g., by way of an epoxy paste). In the package <NUM> shown at step <NUM> in <FIG>, the multi-layer mounting structure <NUM> can comprise a first sidewall <NUM> at a side surface of the first layer <NUM> and a second sidewall <NUM> at a side surface of the second layer <NUM>. In some embodiments, the first sidewall <NUM> can have a profile that is generally similar to the profile of the second sidewall <NUM>, because both the first and second layers <NUM>, <NUM> were diced in the block <NUM>, which create markings indicative of the dicing procedure. However, some differences in the surfaces of the sidewalls <NUM>, <NUM> may results due to the heating and cooling (and the resulting flowing and hardening) of the first layer <NUM>. For example, because the first layer <NUM> flows when heated, the sidewall <NUM> of the first layer <NUM> may have a curved profile (e.g., concave or convex) due to the flowing of the insulating material of the layer <NUM>. By contrast, because the second layer <NUM> may not flow when heated (or the melting may be significantly less pronounced than in the first layer <NUM>), the second sidewall <NUM> may be more planar or straighter than the first sidewall <NUM> (for example, due to the dicing operation). Similarly, in the embodiment of <FIG>, at the step <NUM>, the first and second sidewalls <NUM>, <NUM> may likewise differ. As with <FIG>, the second sidewall <NUM> can comprise markings representative of the dicing procedure and may be generally planar or straight. By contrast, the first sidewall <NUM> can comprise a curved surface due to the flowable nature of the first layer <NUM>.

The thickness of the first layer <NUM> can be any suitable thickness sufficient to embed the wire bonds <NUM>. In some embodiments, the thickness of the first layer <NUM> can be in a range of <NUM> microns to <NUM> microns. The thickness of the second isolating layer <NUM> can be any suitable thickness sufficient to prevent penetration of the layer <NUM> by the bond wires <NUM> and/or to prevent shorting to the integrated device die <NUM>. In various embodiments, for example, the thickness of the second layer <NUM> can be in a range of <NUM> microns to <NUM> microns, in a range of <NUM> microns to <NUM> microns, in a range of <NUM> microns to <NUM> microns, in a range of <NUM> microns to <NUM> microns, or in a range of <NUM> microns to <NUM> microns. In some embodiments, the first layer <NUM> and the second isolating layer <NUM> may have different material compositions and an identifiable interface in the final product to indicate the application of multiple layers to form the structure <NUM>.

Advantageously, the embodiments of <FIG> can reduce the risk of, or can prevent, the shorting of the wires <NUM> and the integrated device die <NUM>. The second layer <NUM> can physically and electrically isolate the wires <NUM> from the die <NUM>. For example, although the wires <NUM> may be embedded in the first layer <NUM>, the wires <NUM> may not penetrate the second layer <NUM> such that the wires <NUM> do not contact the back side <NUM> of the die <NUM>. Furthermore, in some embodiments, the second layer <NUM> can advantageously enable the use of increased voltages as compared with other packages (e.g., when higher voltage breakdown is desired). The second isolating layer <NUM> can reduce electromigration into the die <NUM>. The layer <NUM> also provides a desired vertical separation distance or spacing between the die <NUM> and carrier <NUM>.

In addition, the isolating layer <NUM> may also be tuned in various embodiments to improve radio frequency (RF) performance of various types of systems. For example, the dielectric material of the layer <NUM> (and/or of other layers in the package) between the wires and the die <NUM> can be selected and/or dimensioned to improve system RF performance. In various embodiments, the layer <NUM> (and/or other components) can be patterned or formed to target specific frequencies or wavelengths (or ranges thereof), for example, to act as a filter for attenuating, passing, or enhancing electromagnetic signals at those frequencies or wavelengths. Such embodiments can facilitate communications between the dies. In addition, various embodiments can improve inductive and/or capacitive performance of the package. For example, in various embodiments, the layers (e.g., including layer <NUM>) can be patterned to achieve the aforementioned advantages. Moreover, in various embodiments, microfluidic channels can be patterned in the layers (e.g., including layer <NUM>) so as to provide fluidic communication within the package. The layers (e.g., layer <NUM>) can also be patterned to provided locking features and/or to improve adhesion. In some embodiments, a layer (such as the isolating layer <NUM>) may be selected and/or dimensioned to have magnetic properties that can enhance performance, provide shielding capabilities, or other suitable functionality. In some embodiments, the layer <NUM> can include an optical component to allow for communication between the die <NUM> and other components of the package or larger system.

<FIG> is a schematic side view of a wafer <NUM>' temporarily mounted to a wafer mount <NUM> by way of a wafer tape <NUM>, according to various embodiments. <FIG> is an enlarged schematic side view of a portion of the wafer <NUM>' coupled with the wafer <NUM> by way of a mounting structure <NUM>, according to some embodiments. Unless otherwise noted, the components of <FIG> may be similar to or the same as like numbered components of <FIG>, respectively. For example, as with <FIG>, in <FIG>, the undiced wafer <NUM>' can comprise a plurality of device regions that, when diced, define a plurality of the integrated device dies. Unlike the embodiment of <FIG>, however, the mounting structure or tape <NUM> shown in <FIG> can include at least three insulating layers that comprise an adhesive-insulator-adhesive stack. As with <FIG>, the mounting structure <NUM> can comprise a first insulating adhesive layer 4a that has a flowable state and a hardened or cured state (e.g., a DAF or epoxy), and a second, solid isolating layer <NUM> disposed above the layer 4a between the wafer tape <NUM> and the wafer <NUM>'. As above, in some embodiments, the second layer <NUM> can have a higher melting point than the first layer 4a, which may be similar to or the same material as the first layer <NUM> of <FIG>. In other embodiments, the second layer <NUM> may not have a higher melting point than the first layer 4a. In some embodiments, the second layer <NUM> can comprise a thermoset material that hardens, and does not re-melt, after curing.

Unlike <FIG>, in <FIG> the mounting structure or tape <NUM> can comprise a third insulating adhesive layer 4b over the second layer <NUM> and between the second layer <NUM> and the wafer <NUM>' (and therefore between the second layer <NUM> and the die <NUM> after dicing as shown in <FIG>). As shown in <FIG>, the second layer <NUM> can be embedded or sandwiched between the first and third layers 4a, 4b. In the illustrated embodiment, the third layer 4b can comprise the same material (or a generally similar material) as the first layer 4a. For example, the third layer 4b can comprise a third insulating adhesive material that has a flowable state and a hardened or cured state. In other embodiments, the first and third layers 4a, 4b may comprise different materials. Beneficially, as explained herein, providing the first and third layers 4a, 4b that have respective flowable states on opposite sides of the second layer <NUM> can enable adhesion to both, opposite sides of the structure or tape <NUM>. Thus, in some embodiments, heating the tape <NUM> of <FIG> can cause the first and third layers 4a, 4b to flow, and the flowable layers 4a, 4b can contact a carrier and the die <NUM>, respectively. Once the layers 4a, 4b are cured or hardened, the hardened layers 4a, 4b can beneficially improve the adhesion of the die <NUM>' and the carrier to the structure <NUM>.

In some embodiments, the tape <NUM> can be formed by applying or depositing the films or layers 4a, 4b on the opposite sides of the second insulating layer <NUM>. In some embodiments, the second layer <NUM> can be embedded within a flowable material (such as the first flowable layer <NUM> discussed above) and cut to define the first layer 4a on one side of the second layer <NUM> and the third layer 4b on the other side of the second layer <NUM>. In some embodiments, the first layer 4a, the second isolating layer <NUM>, and the third layer 4b may have different material compositions and an identifiable interface in the final product to indicate the application of multiple layers to form the structure <NUM>. For example, the thickness of the tape <NUM> can be in a range of <NUM> microns to <NUM> microns, or in a range of <NUM> microns to <NUM> microns. The thickness of the first insulating adhesive layer 4a can be any suitable thickness, as explained above, for example in a range of <NUM> microns to <NUM> microns. Similarly, the thickness of the third layer 4b can be in a range of <NUM> microns to <NUM> microns. The thickness of the second isolating layer <NUM> can be in a range of <NUM> microns to <NUM> microns, in a range of <NUM> microns to <NUM> microns, in a range of <NUM> microns to <NUM> microns, in a range of <NUM> microns to <NUM> microns, or in a range of <NUM> microns to <NUM> microns. In various embodiments, the thickness of the second isolating layer <NUM> can be tuned according to various desired electrical characteristics, e.g., the layer <NUM> can be made thicker for packages that operate at high voltages so that the thickness can be sufficient so as to avoid electrical breakdown.

<FIG> is a flowchart illustrating a method <NUM> for manufacturing an integrated device package <NUM>, according to some embodiments. <FIG> illustrates a series of schematic side views of the package <NUM> at various stages of the method <NUM> shown in <FIG>, according to one embodiment. As with the embodiment of <FIG>, in <FIG>, the method <NUM> can begin in a block <NUM> to thin the wafer <NUM>'. The wafer <NUM>' can be thinned by way of, for example, etching, polishing, etc. Turning to a block <NUM> , the mounting structure or tape <NUM> can be applied to the back side <NUM> of the wafer <NUM>'. The multi-layered tape <NUM> can comprise the three layers 4a, <NUM>, 4b described above in connection with <FIG>, such that the layers 4a, <NUM>, 4b form a multi-layered structure that can be applied to the back side <NUM> of the entire (or portions of the) wafer <NUM>'. The third layer 4b of the multi-layer tape <NUM> can be attached to the back side <NUM> of the wafer <NUM>' in any suitable manner to connect the multi-layer mounting structure or tape <NUM> to the wafer <NUM>'.

Turning to block <NUM>, the wafer <NUM>' can be diced in any suitable way (e.g., sawed, punched, etc.) to define a plurality of the integrated device dies <NUM>. Moving to a block <NUM>, the diced die <NUM> can be stacked or mounted to the carrier <NUM> by way of the mounting structure or tape <NUM>. For example, as explained above, the first layer 4a can be brought into contact with the bonding wires <NUM> of the carrier <NUM>. The package <NUM> can be heated to cause the first layer 4A to flow around the bonding wires <NUM>. Once the first layer 4a is cured or hardened, the die <NUM> can be securely adhered to the carrier <NUM>. Furthermore, as explained above in connection with <FIG>, the second layer <NUM> can serve to electrically isolate the back side <NUM> of the die <NUM> from the carrier <NUM>, e.g., from the bonding wires <NUM>. The use of the three layers 4a, <NUM>, 4b in <FIG> can beneficially improve adhesion of the die <NUM> to the multi-layer tape <NUM> (by way of the adhesion of the third layer 4b to the back side <NUM> of the die <NUM>), and the adhesion of the multi-layer tape <NUM> to the carrier <NUM> (by way of the adhesion of the first layer 4a to the front side <NUM> of the carrier <NUM>), while preventing or reducing the risk of shorts of the wires <NUM> to the die <NUM>.

<FIG> illustrates four (<NUM>) example implementations of the embodiments of the multi-layer mounting structure or tape <NUM> disclosed herein. Example <NUM> illustrates the embodiments of the integrated device package <NUM> formed in the process shown in <FIG>. Example <NUM> illustrates the embodiment of the integrated device package <NUM> formed in the process shown in <FIG>. As explained above, in Examples <NUM> and <NUM>, the carrier <NUM> can comprise an additional integrated device die that is electrically connected to a package substrate (not shown) by bond wires <NUM>.

However, in Examples <NUM> and <NUM>, the carrier <NUM> can instead comprise a package substrate upon which the integrated device die <NUM> is mounted. In Example <NUM>, the die <NUM> is mounted to the carrier <NUM> (package substrate) using the multi-layer mounting structure or tape <NUM> shown in <FIG>. In Example <NUM>, the die <NUM> is mounted to the carrier <NUM> (package substrate) using the multi-layer mounting structure or tape <NUM> shown in <FIG>. In Examples <NUM> and <NUM>, the carrier <NUM> can comprise a leadframe package substrate having a die pad and/or a plurality of leads. In other embodiments, however, the carrier <NUM> can comprise other types of package substrates or packaging structures, such as a PCB substrate, a ceramic substrate, etc. Beneficially, the embodiments of Examples <NUM> and <NUM> can securely adhere the die <NUM> to the carrier <NUM>, and may reduce processing costs as compared with other processes that mount the die <NUM> to the package substrate (for example, may obviate the use of other, multi-step mounting processes). For example, current processes may utilize multiple (e.g., two) layers of a screen-printed epoxy paste for mounting the die <NUM> to the leadframe substrate. Screen-printing may incorporate multiple mechanical and thermal cycles, and may incur substantial processing costs. Utilizing the tape <NUM> in the devices of Examples <NUM> and <NUM> can reduce these manufacturing complexities and costs.

<FIG> is a schematic side sectional view of an integrated device package <NUM> in which the carrier <NUM> is mounted to a package substrate. The package substrate shown in <FIG> comprises a leadframe substrate having a die pad <NUM> electrically spaced from a plurality of leads <NUM>. The package <NUM> of <FIG> illustrates the integrated device die <NUM> mounted to the carrier <NUM> (another integrated device die) by way of the multi-layer mounting structure <NUM> shown and described above in connection with <FIG> and/or 3C. However, it should be appreciated that the die <NUM> can instead be mounted to the carrier <NUM> by way of the multi-layer mounting structure <NUM> shown and described in connection with <FIG>. The carrier <NUM> can be mounted to the die pad <NUM> by way of a suitable die attach material <NUM>. In <FIG>, first bonding wires 5a can electrically connect the carrier <NUM> to the leads <NUM>. Second bonding wires 5b can electrically connect the die <NUM> to the leads <NUM>. In other embodiments, the die <NUM> can be flip chip mounted to the carrier <NUM>. In some embodiments, a molding compound or encapsulant <NUM> can be provided over upper surfaces of the die pad <NUM> and leads <NUM>, over the bonding wires 5a, 5b, and over the stacked die <NUM> and carrier <NUM>. The leadframe substrate (e.g., the leads <NUM> and die pad <NUM>) can be mounted to a system board or motherboard to connect the package to the larger electronic device or system.

<FIG> illustrate various packages <NUM> in which an integrated device die <NUM> is stacked or mounted to a carrier <NUM> that comprises another integrated device die. Unless otherwise noted, components of <FIG> may include the same or similar components as like-numbered components shown in <FIG>. <FIG> is a schematic side view of an integrated device package <NUM> in which the die <NUM> is mounted to the carrier <NUM> by only the intervening insulating adhesive layer <NUM>. In <FIG>, the lateral footprint of the die <NUM> is smaller than the lateral footprint of the carrier <NUM>. <FIG> is a schematic side view of an integrated device package <NUM> in which the die <NUM> is mounted to the carrier <NUM> by way of an intervening spacer <NUM>, which may comprise silicon or any other suitable material. The spacer <NUM> can be attached to the carrier <NUM> by a die attach material <NUM>, and the die <NUM> can be attached to the spacer <NUM> by a die attach material <NUM>.

The arrangements of <FIG> may experience various shortcomings as compared with various other embodiments disclosed herein. In <FIG>, the bonding wires 5a may not be disposed between the die <NUM> and the carrier <NUM>, such that there may be a line of sight or open gap between the wires 5a and the die <NUM>. Such a line of sight may cause arcing between the wires 5a and the wires 5b, and/or between the wires 5a and the die <NUM>. Furthermore, in <FIG>, the die <NUM> may tilt during assembly and/or use, which can further increase the risk of arcing. Similarly, in the arrangement of <FIG>, a gap X may be provided between the spacer <NUM> and the bond wire 5a, but such an arrangement may nevertheless risk arcing or shorting if the die <NUM> tilts downwardly, and/or if there is bleedout of the die attach material <NUM>. Furthermore, in the arrangements shown in <FIG>, mounting the die <NUM> to the carrier <NUM> with the illustrated intervening structures may induce stresses on the carrier <NUM>, and/or vice versa. For example, in <FIG>, attaching the spacer <NUM> to the carrier <NUM> may induce localized stresses in the carrier <NUM> (and/or in the die <NUM>) around the perimeter of the spacer <NUM>. Further, if the materials of the spacer <NUM>, the die <NUM>, and/or the carrier <NUM> have different CTEs, and the package <NUM> is heated, stresses may also be induced in the package <NUM>. When an enacapsulant or molding compound is provided over the die <NUM> and carrier <NUM>, these induced stresses may be effectively locked into the package <NUM>.

Accordingly, there remains a continuing need for improved integrated device packages that reduce the risk of electrical shorting or arcing, and that reduce stresses in the package components. <FIG> is a schematic side view of an integrated device package <NUM>, in accordance with the claimed invention except that it does not include the features relating to the pathway in the spacer, comprising an integrated device die <NUM> mounted to a carrier <NUM> by way of a mounting structure <NUM> comprising a first insulating layer <NUM> and a second insulating element comprising a second spacer layer <NUM> between the first layer <NUM> and the die <NUM>. <FIG> is a schematic plan view of the integrated device package <NUM> shown in <FIG>. Unless otherwise noted, the components of <FIG> are the same as or generally similar to like-numbered components of <FIG>. As shown in <FIG>, the carrier <NUM> (which comprises an integrated device die) can be mounted to the die pad <NUM> of a leadframe substrate, for example, by way of the die attach material <NUM>. One or more wire bonds 5a are be provided to electrically connect bond pads at the front side <NUM> of the carrier <NUM> with corresponding leads <NUM> of the leadframe substrate.

As discussed above with respect to the embodiments of <FIG>, the die <NUM> is mounted or stacked to the carrier <NUM> by way of a mounting structure <NUM>. In the embodiment shown in <FIG>, the mounting structure <NUM> comprises a first insulating adhesive layer <NUM> (which may be the same as or similar to the layers <NUM> and 4A described above) having a flowable state and a hardened or cured state. The mounting structure <NUM> further comprises a second insulating element comprising a spacer <NUM> disposed between the die <NUM> and the first layer <NUM>. In <FIG>, the mounting structure <NUM> includes the spacer <NUM> and insulating layer <NUM>, but in other embodiments, the mounting structure <NUM> can include the third layer 4a described in <FIG> and <FIG>. The mounting structure <NUM> can be brought into contact with the bond wires 5a and can be changed into the flowable state (e.g., by heating the package <NUM>). The first layer <NUM> can flow around and over the bond wires 5a. The first layer <NUM> can cure to securely attach the mounting structure <NUM> to the carrier <NUM>.

In various embodiments, the mounting structure <NUM> can be formed by attaching or depositing the spacer <NUM> to the insulating adhesive layer <NUM>, and the mounting structure <NUM> can subsequently be attached to the carrier <NUM>. In some embodiments, the insulating adhesive layer <NUM> can be attached to the carrier <NUM> (e.g., flowed around the wire bonds <NUM> and cured), and the spacer <NUM> can be applied, deposited or attached to the insulating layer. Still other ways of forming the mounting structure <NUM> may be suitable. The integrated device die <NUM> can be mounted to the spacer <NUM> of the mounting structure by way of a die attach material <NUM>. Bond pads at the front side <NUM> of the die <NUM> can be connected to corresponding leads <NUM> of the leadframe substrate. The bond pads at the front side <NUM> of the die <NUM> can be connected to corresponding leads <NUM> by way of the bond wires 5b. In the arrangement shown in <FIG>, each layer may comprise any suitable thickness. For example, the thickness of the first insulating layer <NUM> can be in a range of <NUM> microns to <NUM> microns. The thickness of the spacer <NUM> can be any suitable thickness for reducing stresses and/or for providing electrical isolation of the die, e.g., the thickness can be in a range of <NUM> microns to <NUM> microns. The thickness of the die attach material <NUM> that attaches the carrier <NUM> to the die attach pad <NUM> can be in a range of <NUM> microns to <NUM> microns, or any other suitable thickness. The thickness of the die attach material <NUM> that attaches the die <NUM> to the spacer <NUM> can be in a range of <NUM> microns to <NUM> microns, or any other suitable thickness.

Advantageously, the embodiment shown in <FIG> may prevent or reduce the risk of shorting the bond wires <NUM> to the die <NUM>, as explained above. The spacer <NUM> comprises a material that prevents penetration of the bond wires <NUM>. In addition, the material of the spacer may be selected so as to closely match a coefficient of thermal expansion (CTE) of the die <NUM> and/or the carrier <NUM>. For example, in various embodiments, the CTE of the spacer <NUM> can be within at least +/- <NUM>% of the CTE of the integrated device die <NUM>, within at least +/- <NUM>% of the CTE of the integrated device die <NUM>, within at least +/- <NUM>% of the CTE of the integrated device die <NUM>, or within at least +/- <NUM>% of the CTE of the integrated device die <NUM>. In some embodiments, the CTE of the spacer <NUM> can be substantially the same as the CTE of the die <NUM>. The CTE of the spacer can be within at least +/- <NUM>% of the CTE of the carrier <NUM>, within at least +/- <NUM>% of the CTE of the carrier <NUM>, within at least +/- <NUM>% of the CTE of the carrier <NUM>, or within at least +/- <NUM>% of the CTE of the carrier <NUM>. In some embodiments, the CTE of the spacer <NUM> can be substantially the same as the CTE of the carrier <NUM>. Beneficially, therefore, matching the CTE of the spacer <NUM> with the CTE of the carrier <NUM> and/or die <NUM> can reduce overall stresses in the package <NUM>. Furthermore, in <FIG>, by providing the spacer <NUM> over a lateral footprint that is wider than the die <NUM>, the spacer <NUM> can spread any stresses induced by the die <NUM> over a larger area, reducing local stress concentrations, such as those created around the perimeter of the spacer <NUM> shown in <FIG>. The spacer <NUM> can comprise any suitable material, including, for example, a semiconductor (e.g., silicon), a polymer, etc. In some embodiments, the spacer <NUM> can comprise a tunable structure, e.g., a bimetallic strip which can be tuned to achieve a desired CTE. In still other embodiments, the spacer <NUM> can be tuned to have a desired, predetermined CTE mismatch to induce a particular stress for a particular electrical reaction and/or behavior.

Furthermore, as shown in <FIG>, multiple integrated device dies 2a, 2b (which may comprise the same or different type of integrated device die) can be mounted laterally side-by-side on the spacer <NUM>. Beneficially, including multiple dies 2a, 2b on the spacer <NUM> may improve redundancy for the package <NUM>, for example, if the dies 2a, 2b perform at least some overlapping functions. The spacer <NUM> can create the same stress conditions for the dies 2a, 2b, which may improve the electrical performance of the dies 2a, 2b. In some embodiments, multiple (e.g., two, three, four, etc.) spacers <NUM> may be provided. For example, multiple dies 2A, 2B, etc. can be mounted to corresponding multiple spacers. In some embodiments, more than two integrated device dies may be mounted on the spacer <NUM>.

<FIG> illustrate embodiments that incorporate a multi-layer mounting structure that comprises the first insulating layer and the spacer <NUM>. <FIG> is a side view of a package <NUM>, in accordance with the claimed invention except that it does not include the features relating to the pathway in the spacer, in which the integrated device die <NUM> can be approximately the same lateral size or footprint (in at least one horizontal dimension) as the spacer <NUM>. The spacer <NUM> in <FIG> may be approximately the same lateral size or footprint (in at least one horizontal dimension) as the carrier <NUM>. <FIG> is a side view of a package <NUM> that includes two integrated device dies <NUM>, <NUM>' and a carrier <NUM> (which may also comprise an additional, third integrated device die). In the illustrated embodiment, the integrated device die <NUM> is mounted to the carrier <NUM> by way of the adhesive <NUM>, the spacer <NUM>, and the die attach material <NUM>. A second integrated device die <NUM>' can be mounted to the integrated device die <NUM> by way of a second adhesive <NUM>', a second spacer <NUM>', and a second die attach material <NUM>'. As with the package <NUM> illustrated in <FIG>, and the package <NUM> illustrated in <FIG>, the lateral size of the integrated device dies <NUM>, <NUM>' can be the same as the lateral size of the spacer <NUM>. However, unlike the carrier <NUM> of <FIG>, the carrier <NUM> illustrated in <FIG> can be connected to the die pad <NUM> via conductive bumps <NUM>. The integrated device dies <NUM>, <NUM>' can be wire bonded to the leads <NUM> by way of bonding wires 5b, 5b'.

In contrast to <FIG> and <FIG>, in <FIG>, the integrated device die <NUM> may have a lateral size or footprint that is smaller than the lateral size or footprint of the spacer <NUM> and/or the carrier <NUM>. In <FIG>, in accordance with the claimed invention except that it does not include the features relating to the pathway in the spacer, the spacer <NUM> may have a lateral size or footprint in at least one lateral dimension that is approximately the same as the lateral size of the carrier <NUM>. In <FIG>, in accordance with the claimed invention except that it does not include the features relating to the pathway in the spacer, the integrated device die <NUM> may have a lateral size or footprint that is smaller than the lateral size or footprint of the spacer <NUM>. The lateral size or footprint of the spacer <NUM> may be smaller than the lateral size or footprint of the carrier <NUM>. In <FIG>, in accordance with the claimed invention except that it does not include the features relating to the pathway in the spacer, by contrast, the integrated device die <NUM> may have a lateral size or footprint that is larger than the lateral size or footprint of the spacer <NUM> and/or the carrier <NUM>. In <FIG>, the spacer <NUM> is illustrated as being about the same lateral size or footprint as the carrier <NUM>, but in other embodiments, the spacer <NUM> may have a smaller lateral size than the carrier <NUM>. Still other combinations of lateral size and/or footprint of the die <NUM>, the spacer <NUM>, and the carrier <NUM> may be suitable for the embodiments disclosed herein. As with the embodiment of <FIG>, each of the embodiments of <FIG> may reduce the risk of electrical shorting or arcing and reduce the overall stresses of the package <NUM>.

<FIG> is a schematic top view of a spacer <NUM> according to an embodiment. The spacer <NUM> of <FIG> may be implemented in any of the packages <NUM> disclosed herein. The spacer <NUM> illustrated in <FIG> includes an opening <NUM>. The opening <NUM> can enable the use of functionality for other integrated circuit and/or packaging applications. The opening <NUM> may be pattered or formed as desired for the specific application. For example, the opening <NUM> may comprise a hole through a portion of the spacer <NUM> as illustrated in <FIG>, or comprise a cavity formed partially through a portion of the spacer <NUM>. In some embodiments, an insert (e.g., an optical insert such as a lens or a filter) may be disposed within the opening <NUM>. For example, the insert may enable optical communication through the spacer <NUM> between the die <NUM> and the carrier <NUM>, or between other stacked components between which the spacer <NUM> is disposed.

<FIG> is a schematic top view of a spacer <NUM> according to another embodiment. The spacer <NUM> of <FIG> may be implemented in any of the packages <NUM> disclosed herein. The spacer <NUM> illustrated in <FIG> includes a plurality of openings <NUM>. The openings <NUM> may be filled with a filler material or inserts (e.g., lens or filters). The openings <NUM> can be vertically integrated in the system so as to provide optical or electrical communication between the die <NUM> and the carrier <NUM>. The filler material can be, for example, an epoxy, such as SU-<NUM>. In some embodiments, the spacer <NUM> can be modified by, for example, using a laser to modify the property of the filler material. For example, SU-<NUM> filler material can be modified to allow/prohibit light to pass therethrough. There are twenty-four (<NUM>) openings <NUM> equally spaced from one another in <FIG>. However, the spacer <NUM> may comprise any number of openings <NUM> with suitable spacings between the openings <NUM>. The openings <NUM> may have any suitable shape and/or size. Further, different openings 103a, 103b of the openings <NUM> can include different filler materials and/or inserts. For example, one or more first openings 103a can include a first type of filler material or insert, and one or more second openings 103b can include a second type of filler material or insert. Beneficially, the use of different filler materials or inserts in different regions of the spacer <NUM> (e.g., in different openings 103a, 103b) can enable different functionalities across the spacer <NUM>. Different materials/inserts can be incorporated within the same space, enabling (for example) light of different wavelengths to transmit through different portions of the same spacer/substrate - therefore though the different planes of the vertically integrated structure linking up different components within the system.

<FIG> is a schematic top view of a spacer <NUM> according to another embodiment. The spacer <NUM> of <FIG> may be implemented with any of the packages <NUM> disclosed herein. The spacer <NUM> illustrated in <FIG> includes a pattern of material <NUM>. The patterned material <NUM> may be dispensed on and/or embedded into the spacer <NUM>. The pattern of material <NUM> can comprise a metallic pattern, conductive pattern, insulator pattern, etc. In the illustrated embodiment, the patterned material <NUM> can comprise a spiral or curved pattern. In some embodiments, the patterned material <NUM> may be beneficial for use with magnetic sensor or magnetic switch applications. In some embodiments, the patterned material <NUM> may be used as a band pass filter. In still other embodiments, the patterned material <NUM> may be used in conjunction with packages that harvest energy by, for example, harnessing vibration, light, and/or heat to collect and store energy for other uses.

<FIG> is a schematic top view of a spacer <NUM> according to another embodiment. The spacer <NUM> of <FIG> may be implemented with any of the packages <NUM> disclosed herein. The spacer <NUM> illustrated in <FIG> includes an optical filter <NUM> formed through at least a portion of a thickness of the spacer <NUM>. The filter <NUM> may be disposed on or into the thickness of the spacer <NUM>, and can be configured to pass or attenuate light at selected optical frequency ranges. The spacer <NUM> illustrated in <FIG> may be beneficial for use with biomedical applications and/or optical applications, in some embodiments. The filter <NUM> may comprise a wavelength filter, band pass filter, etc..

<FIG> is a schematic top view of a spacer <NUM> according to another embodiment. The spacer <NUM> of <FIG> may be implemented with any of the packages <NUM> disclosed herein. The spacer <NUM> illustrated in <FIG> can be used in fluidic applications, and can includes a fluid pathway <NUM> patterned or otherwise defined in the spacer <NUM>. The fluid pathway <NUM> may be disposed on or into the spacer <NUM>. The fluid pathway <NUM> can comprise a channel, a via, a track, a microfluidic channel, etc. for conveying fluid through the spacer <NUM>. Fluid can be driven through the fluid pathway <NUM> along a lateral direction of the spacer <NUM> (as shown in <FIG>) or vertically through the spacer <NUM>. The spacer <NUM> can also include a valve <NUM> along the fluid pathway <NUM>. The valve <NUM> can be configured to control a flowrate of fluid along the fluid pathway <NUM>. In various embodiments, the valve <NUM> can comprise a piezoelectric material. The spacer <NUM> with the fluid pathway <NUM> may be used in various types of fluidic applications, including, e.g., a pH sensor, a blood sensor, medical fluids therapy, pharmaceutical tests and devices, food industry tests and devices, polymeric chain reaction (PCR) devices, etc. The fluid pathway <NUM> may be suitably patterned for the desired application.

Alternatively, in some embodiments, the valve <NUM> may not be incorporated in the spacer <NUM>. In such embodiments, fluid may flow through the spacer <NUM> and/or between the spacer <NUM> and an adjacent layer in the package, without being controlled by the valve <NUM>. The fluid pathway <NUM> (e.g., a microfluidic channel) can be used to remove heat from the package, in some embodiments. The fluid pathway <NUM> can interact with the fluid flowing through the spacer and other layers, in some embodiments. For example, one of the layers in a package (e.g., a layer integrated above or below the spacer <NUM>) may monitor the temperature of the fluid and/or extrapolate some other property of the fluid (e.g., magnetic structures detecting some magnetic property, flow rate, and/or an optical property of the fluid). In some embodiments, the valve <NUM> can include an optical component (e.g., an optical sensor) to detect an optical property of the fluid.

<FIG> is a schematic top view of a spacer <NUM> according to another embodiment. The spacer <NUM> of <FIG> may be implemented with any of the packages <NUM> disclosed herein. The spacer <NUM> illustrated in <FIG> includes a sensor <NUM>. The sensor <NUM> may be disposed on or into the spacer <NUM>. In some embodiments, the sensor <NUM> can comprise a radio frequency identification (RFID) device. The sensor <NUM> may enable a wireless communication between the package <NUM> and an external device, or between device dies within the package <NUM>. The sensor <NUM> may enable the package for use with an internet of things (IoT) system by wirelessly receiving and/or transmitting information to external devices. The sensor <NUM> may also provide data encryption capabilities for the package <NUM>.

<FIG> is a schematic top view of a spacer <NUM> according to another embodiment. The spacer <NUM> of <FIG> may be implemented with any of the packages <NUM> disclosed herein. The spacer <NUM> illustrated in <FIG> includes a patterned void <NUM>. The patterned void <NUM> may be formed on or into the spacer <NUM>. The void <NUM> may comprise, for example, a trench <NUM> or a channel <NUM> as illustrated in <FIG>, respectively. The spacer <NUM> with the patterned profile can be beneficial for use a band pass filter, which can filter light of various wavelengths. The spacer <NUM> can comprise silicon, polymer, or any suitable material.

<FIG> is a side view of the spacer <NUM> that includes a plurality of trenches <NUM> according to an embodiment. The spacer <NUM> of <FIG> may be implemented with any of the packages <NUM> disclosed herein. The trenches <NUM> may be formed (e.g., etched) into a portion of a thickness of the spacer <NUM>. The trenches <NUM> may be suitably spaced from one another, for example, to provide optical filtering functionality at desired wavelength ranges. The trenches <NUM> may be configured to enable media to traverse laterally and/or vertically through layers of a package. Also, the spacer <NUM> and/or any layer(s) of the package can be connected to an external system and/or component. For example, a specific layer of the package can communicate with an external optical network or the fluid to be analyzed and/or modified can ingress from, for example, the external environment.

<FIG> is a schematic side sectional view of an integrated device package <NUM>, in accordance with the claimed invention, that includes the spacer <NUM> of <FIG>. The carrier <NUM> of package <NUM> is mounted to a package substrate. The package <NUM> of <FIG> comprises a leadframe substrate having a die pad <NUM> electrically spaced from a plurality of leads <NUM>. The package <NUM> of <FIG> illustrates a integrated device die <NUM> mounted to a carrier <NUM> (another integrated device die) by way of a multi-layer mounting structure <NUM> that comprises the spacer <NUM>. As with <FIG> and/or 5B, the multi-layer mounting structure <NUM> illustrated in <FIG> includes a first insulating adhesive layer 4a between the carrier <NUM> and the spacer <NUM>, and a third insulating adhesive layer 4b between the die <NUM> and the spacer <NUM>. However, it should be appreciated that the die <NUM> can instead be mounted to the carrier <NUM> by way of the multi-layer mounting structure <NUM> that comprises a spacer and any number of insulating adhesion layer(s). The carrier <NUM> can be mounted to the die pad <NUM> by way of a suitable die attach material <NUM>. In <FIG>, first bonding wires 5a electrically connect the carrier <NUM> to the leads <NUM>. Second bonding wires 5b can electrically connect the die <NUM> to the leads <NUM>. In other embodiments, the die <NUM> can be flip chip mounted to the carrier <NUM>. In some embodiments, a molding compound or encapsulant (for example, the encapsulant <NUM> of <FIG>) can be provided over upper surfaces of the die pad <NUM> and leads <NUM>, over the bonding wires 5a, 5b, and over the stacked die <NUM> and carrier <NUM>. The leadframe substrate (e.g., the leads <NUM> and die pad <NUM>) can be mounted to a system board or motherboard to connect the package to the larger electronic device or system.

<FIG> is a side view of the spacer <NUM> that includes a plurality of channels <NUM> according to an embodiment. The spacer <NUM> of <FIG> may be implemented with any of the packages <NUM> disclosed herein. As shown in <FIG>, the channels <NUM> can comprise channels disposed laterally through the spacer <NUM>, e.g., parallel to major surfaces of the spacer <NUM>. In other embodiments, the channels <NUM> can comprise discrete voids or spaces within the spacer <NUM>. As with <FIG>, the size and spacing of the channels <NUM> can be selected to provide optical filtering or other suitable types of functionality.

<FIG> is a schematic side sectional view of an integrated device package <NUM>, in accordance with the claimed invention, that includes the spacer <NUM> of <FIG>. The carrier <NUM> of package <NUM> is mounted to a package substrate. The package <NUM> of <FIG> comprises a leadframe substrate having a die pad <NUM> electrically spaced from a plurality of leads <NUM>. The package <NUM> of <FIG> illustrates an integrated device die <NUM> mounted to a carrier <NUM> (another integrated device die) by way of a multi-layer mounting structure <NUM> that comprises the spacer <NUM>. As with <FIG> and/or 5B, the multi-layer mounting structure <NUM> illustrated in <FIG> includes a first insulating adhesive layer 4a between the carrier <NUM> and the spacer <NUM>, and a third insulating adhesive layer 4b between the die <NUM> and the spacer <NUM>. However, it should be appreciated that the die <NUM> can instead be mounted to the carrier <NUM> by way of the multi-layer mounting structure <NUM> that comprises a spacer and any number of insulating adhesion layer(s). The carrier <NUM> can be mounted to the die pad <NUM> by way of a suitable die attach material <NUM>. In <FIG>, first bonding wires 5a electrically connect the carrier <NUM> to the leads <NUM>. Second bonding wires 5b can electrically connect the die <NUM> to the leads <NUM>. In other embodiments, the die <NUM> can be flip chip mounted to the carrier <NUM>. In some embodiments, a molding compound or encapsulant (for example, the encapsulant <NUM> of <FIG>) can be provided over upper surfaces of the die pad <NUM> and leads <NUM>, over the bonding wires 5a, 5b, and over the stacked die <NUM> and carrier <NUM>. The leadframe substrate (e.g., the leads <NUM> and die pad <NUM>) can be mounted to a system board or motherboard to connect the package to the larger electronic device or system.

The channels <NUM> may be constructed to enable fluid and/or optical signals to travel along the spacer <NUM>, in some embodiments. The trenches <NUM> may be configured to enable media to traverse laterally and/or vertically through layers of the package <NUM>. Also, the spacer <NUM> and/or any layer(s) of the package <NUM> can be connected to an external system and/or component. For example, a specific layer of the package <NUM> can communicate with an external optical network. For example, a microfluidic channel that is included in the package <NUM> (e.g., within the stacked module/vertically integrated system) can also be connected to an external environment.

<FIG> is a schematic side sectional view of an integrated device package <NUM> according to another embodiment of the claimed invention. The carrier <NUM> of the package <NUM> is mounted to a package substrate. The package <NUM> of <FIG> comprises a leadframe substrate having a die pad <NUM> electrically spaced from a plurality of leads <NUM>. In other embodiments, the package substrate can comprise a laminate substrate. The package <NUM> of <FIG> illustrates a integrated device die <NUM> mounted to a carrier <NUM> (another integrated device die) by way of a multi-layer mounting structure <NUM> that comprises the spacer <NUM>.

As with <FIG> and/or 5B, the multi-layer mounting structure <NUM> illustrated in <FIG> includes a first insulating adhesive layer 4a between the carrier <NUM> and the spacer <NUM>, and a third insulating adhesive layer 4b between the die <NUM> and the spacer <NUM>. However, it should be appreciated that the die <NUM> can instead be mounted to the carrier <NUM> by way of the multi-layer mounting structure <NUM> that comprises a spacer and any number of insulating adhesion layer(s).

The spacer <NUM> illustrated in <FIG> includes a pathway <NUM> disposed laterally along or within the spacer <NUM>. The pathway <NUM> can comprise any suitable type of pathway, such as a fluidic pathway, a microfluidic pathway, an optical pathway, or an electronic pathway. The pathway <NUM> can accordingly provide fluid, optical, and/or electronic communication along a lateral direction parallel to and between the die <NUM> and the carrier <NUM>, for example, between input terminal 116a and output terminal 116b. As explained herein, in optical applications, the pathway <NUM> can comprise a fluid piping tube or channel.

The carrier <NUM> can be mounted to the die pad <NUM> by way of a suitable die attach material <NUM>. In some embodiments, as illustrated in <FIG>, a molding compound or encapsulant <NUM> can be provided over upper surfaces of the die pad <NUM> and leads <NUM>, over the stacked die <NUM> and carrier <NUM>, and over upper and lower surfaces of the spacer <NUM>. Thus, in <FIG>, the spacer <NUM> can be disposed between portions of the encapsulant <NUM>. The leadframe substrate (e.g., the leads <NUM> and die pad <NUM>) can be mounted to a system board or motherboard to connect the package to the larger electronic device or system. Although <FIG> does not illustrate bonding wires, it should be appreciated that, according to the claimed invention and as explained above, bonding wires are be provided within the layer 4a to connect the carrier <NUM> to the leads <NUM>. The spacer <NUM> can serve to isolate the bonding wires from other components of the package <NUM>.

The pathway <NUM> (e.g., a microfluidic channel) can be used to remove heat from the package <NUM>, in some embodiments. The pathway <NUM> can interact with the fluid flowing through the spacer and other layers, in some embodiments. For example, one of the layers in a package (e.g., a layer integrated above or below the spacer <NUM>) can monitor the temperature of the fluid and/or extrapolate some other property of the fluid (e.g., magnetic structures detecting some magnetic property, flow rate, an optical property of the fluid flowing through etc.).

<FIG> illustrate schematic side sectional views of various embodiments of a spacer <NUM> having a pathway <NUM>. The spacer <NUM> illustrated in <FIG> includes a pathway <NUM> that comprises a fiber optic channel <NUM>. In <FIG>, therefore, the pathway <NUM> of the spacer <NUM> can be used to enable optical communication laterally through the spacer <NUM> along the fiber optic channel <NUM>. The spacer <NUM> illustrated in <FIG> includes a pathway <NUM> having a tapered channel <NUM>, which may be used with fluidic applications, for example. In <FIG>, fluid can be driven through the tapered channel <NUM> laterally along the spacer <NUM>. The spacer <NUM> illustrated in <FIG> includes the tapered channel <NUM> with fluidic device <NUM> (e.g., a filter or pump) disposed in or along the tapered channel <NUM>. The fluidic device <NUM> can interact with the fluid to filter materials from the fluid or to drive the liquid through the pathway <NUM>. For <FIG>, the spacer <NUM> connects to external networks or devices by way of the terminals 116a, 116b to provide optical, electrical, or fluidic communication with those external networks or devices.

<FIG> illustrates a schematic top view of the package <NUM> of <FIG>. In <FIG>, first bonding wires 5a electrically connect the carrier <NUM> to the leads <NUM>. Second bonding wires 5b can electrically connect the die <NUM> to the leads <NUM>. In other embodiments, the die <NUM> can be flip chip mounted to the carrier <NUM>. As explained above, the spacer <NUM> is provided over the bonding wires so as to prevent shorting.

<FIG> is a schematic side sectional view of an integrated device package <NUM>, in accordance with the claimed invention, that includes two integrated device dies <NUM>, <NUM>', and a carrier <NUM> stacked vertically. The carrier <NUM> is mounted to a die pad <NUM> by way of an adhesive <NUM>, and the carrier <NUM> is electrically connected to leads <NUM> by way of bonding wires 5a.

A multi-layer mounting structure <NUM> includes a spacer 35a, a first insulating adhesive layer 4a between the carrier <NUM> and the spacer 35a, and a third insulating adhesive layer 4b between the die <NUM> and the spacer 35a. The spacer 35a illustrated in <FIG> can be the same or generally similar to the spacer <NUM> illustrated in <FIG>. For example, lateral channels <NUM> can be provided through the spacer 35a. In various embodiments, the channels <NUM> can provide optical, electrical, or fluidic pathways through the spacer 35a.

The two integrated device dies <NUM>, <NUM>' are spaced from one another by a spacer 35b that includes a plurality of openings <NUM>. The spacer 35b illustrated in <FIG> can be the same or generally similar to the spacer <NUM> illustrated in <FIG>. The openings <NUM> can be filled or unfilled with a filler material. In some embodiments, the openings <NUM> can comprise vertical vias, optical pathways, etc. As illustrated, there can be an adhesive layer 4a' between the spacer 35b and the integrated device die <NUM>. In some embodiments, the two dies <NUM>, <NUM>' can electrically, optically, and/or fluidly communicate through the openings <NUM>. The integrated device die <NUM> illustrated in <FIG> is electrically connected to the leads <NUM> by way of bonding wires 5b.

A spacer 35c that can be the same or generally similar to the spacer <NUM> illustrated in <FIG> is disposed over the integrated device die <NUM>'. The spacer 35c can include an opening <NUM>. The opening can be filled or unfilled with a filling material. The opening <NUM> can comprise a via, an optical path, etc. The opening <NUM> can be larger than the opening <NUM>, in some embodiments.

A molding compound or encapsulant <NUM> can be provided about the stacked spacers 35a-35c, dies <NUM>, <NUM>', and carrier <NUM>. The encapsulant <NUM> can have an opening <NUM> over the opening <NUM> of the spacer 35c. In some embodiments, there may be no encapsulant <NUM> over the spacer 35c. In certain applications, the opening <NUM> and the opening <NUM> can allow the integrated device die <NUM>' to communicate with outside environs and/or another device, for example, optically and/or fluidly. The integrated device package <NUM> illustrated in <FIG> may be suitable for fiber optic communications. The spacers 35a, 35b, 35c can comprise any other suitable structures, such as those illustrated in <FIG>, for the use of the integrated device package <NUM>.

<FIG> illustrates a schematic side sectional view of a laminate substrate <NUM>. The laminate substrate <NUM> includes a plurality of alternating patterned conductive and non-conductive layers. In various embodiments, the laminate substrate <NUM> can comprise a printed circuit board (PCB) substrate. Further, in <FIG>, the laminate substrate <NUM> can include various electronic components therein. The laminate substrate <NUM> can include vias, lens, filters, modified areas, voids, cavities, etc. <FIG> shows interconnection terminals 124a, 124b (such as fluid and/or fiber optic connections) coupled to openings 126a, 126b. A terminal 124a, 124b and/or an opening 126a, 126b may be provided to any spacer disclosed herein. The laminate substrate can communicate (e.g., receive an input or transmit an output), for example, electrically, fluidly, and/or optically, with the outside environment and/or an external system or a device.

<FIG> illustrates a schematic side sectional view of the laminate substrate <NUM> that is mounted on a carrier <NUM>. The carrier <NUM> has a top side or a back side 128a and a bottom side or a front side 128b. The front side can comprise an active surface. The carrier <NUM> can include vias <NUM> extending from the back side 128b to the front side 128b. As illustrated in <FIG>, the front side 128b of the carrier can have solder balls <NUM> to provide electrical communication between the vias <NUM> and an external device. The laminate substrate <NUM> and the carrier <NUM> can be in electrical connection. In some embodiments, the carrier <NUM> can comprise an application specific integrated circuit (ASIC) with through substrate vias TSVs. For example, active circuitry of the ASIC can control or manage functions of the laminate substrate <NUM>.

<FIG> illustrate a schematic side sectional view of an integrated device package <NUM> that includes the laminate substrate <NUM> and the carrier <NUM> of <FIG>, according to an embodiment. The integrated device package <NUM> has a generally similar structure as the integrated device package <NUM> illustrated in <FIG> except that the package <NUM> of <FIG> includes the laminate substrate <NUM> and the carrier <NUM> and a molding compound or encapsulant <NUM>. The solder balls <NUM> of the carrier <NUM> can electrically connect to corresponding contact pads on the die <NUM>. As shown, the carrier laminate substrate <NUM> can be exposed through, and positioned above, the encapsulant <NUM>. Additional devices or dies (not shown) can electrically connect to the top surface of the substrate <NUM>.

<FIG> illustrate a schematic side sectional view of an integrated device package <NUM> that includes the laminate substrate <NUM> and the carrier <NUM> of <FIG>, according to an embodiment. The package <NUM> illustrated in <FIG> is generally similar to the package <NUM> illustrated in <FIG> except that the encapsulant <NUM> in <FIG> covers side walls of the laminate substrate <NUM>.

Claim 1:
An integrated device package (<NUM>) comprising:
a carrier (<NUM>), comprising a second integrated device die;
an integrated device die (<NUM>) having a front side (<NUM>) and a back side (<NUM>);
a mounting structure (<NUM>) that serves to mount the back side of the integrated device die (<NUM>) to the carrier (<NUM>), the mounting structure (<NUM>) comprising a first adhesive layer (<NUM>) over the carrier (<NUM>) and a spacer (<NUM>) between the back side of the integrated device die (<NUM>) and the first adhesive layer (<NUM>);
a package substrate; and
a die attach material (<NUM>) arranged between the integrated device die (<NUM>) and the spacer (<NUM>);
one or more bonding wires (<NUM>), wherein the second integrated device die is wire bonded to the package substrate by the bonding wires (<NUM>), wherein a portion of the bonding wires (<NUM>) are disposed between the spacer (<NUM>) and the second integrated device die, the portion of the bonding wires (<NUM>) being embedded within the first adhesive layer (<NUM>)
wherein the first adhesive layer (<NUM>) comprises a first insulating material that adheres to the carrier (<NUM>),
wherein the spacer (<NUM>) comprises a material that prevents penetration of the bonding wires (<NUM>) connected to the carrier (<NUM>);
wherein the spacer (<NUM>) is attached to the first adhesive layer (<NUM>), characterised in that the spacer comprises a pathway to provide at least one of electrical, optical, and fluidic communication between an input terminal and an output terminal of the spacer.