Patent Description:
Page tables are data structures used by modem processor-based devices to provide virtual memory functionality. A page table provides page table entries (PTEs) that store mappings between virtual memory addresses and corresponding physical memory addresses (i.e., addresses of memory locations in a system memory). When a processor-based device needs to translate a virtual memory address into a physical memory address, the processor-based device accesses the page table using a hardware table walker (HTW) to locate the page table entry associated with the virtual memory address, and then reads the corresponding physical memory address from the page table entry. PTEs that have been recently accessed by an HTW or by software may also be cached by the processor-based device in a translation lookaside buffer (TLB) for subsequent reuse without the need to repeat the translation process. By using page tables to implement virtual memory functionality, the processor-based device enables software processes to access secure memory spaces that are isolated from one another, and that together may be conceptually larger than the available physical memory.

Each PTE includes fields that are used by hardware, such as bits representing pointers to other page tables, permission bits, memory attributes, and the like, as non-limiting examples. Other fields within the PTEs (referred to herein as "special PTE (SP-PTE) fields") are used only by software, and may include bits for tracking page counts and/or page age, managing page table updates, and the like, as non-limiting examples. Thus, maintenance and management of page tables by the processor-based device may involve reading and writing to SP-PTE fields that are not used by HTWs and/or that are not relevant to virtual-to-physical address translation.

As long as local copies of a particular PTE are present in a TLB of the processor-based device, the HTWs are oblivious to modifications to the SP-PTE fields, and the PTE continues to be accessed as needed. However, a performance issue may arise if the TLB is too small to hold a working set of PTEs. While updates to the SP-PTE fields are transparent to the HTW, PTEs that are held in a local cache may be invalidated from the local cache when software modifies the SP-PTE fields. Consequently, if a PTE required for virtual-to-physical address translation is not present in the TLB and the cache has invalidated its copy of the PTE due to a modification of an SP-PTE field, the processor-based device must perform a memory read operation to obtain a copy of the PTE from the system memory. This performance issue may be exacerbated in processor-based devices that include multiple processing elements (PEs) that are all attempting to access the same coherence granule (i.e., the smallest memory block for which coherence is maintained, corresponding to a cache line) containing the PTE within their local caches.

Accordingly, a more efficient mechanism for maintaining PTEs while avoiding excessive cache contention is desirable. <NPL>, describes how to improve system performance, operating systems (OSes) often undertake activities that require modification of virtual-to-physical address translations. For example, the OS may migrate data between physical pages to manage heterogeneous memory devices. The authors refer to such activities as page remappings. Unfortunately, page remappings are expensive. The authors show that a big part of this cost arises from address translation coherence, particularly on systems employing virtualization. In response, we propose hardware translation invalidation and coherence or HATRIC, a readily implementable hardware mechanism to piggyback translation coherence atop existing cache coherence protocols. The authors perform detailed studies using KVM-based virtualization, showing that HATRIC achieves up to <NUM>% performance and <NUM>% energy benefits, for per-CPU area overheads of <NUM>%. The authors also quantify HATRIC's benefits on systems running Xen and find up to <NUM>% performance improvements.

Embodiments disclosed herein include facilitating page table entry (PTE) maintenance in processor-based devices. In one embodiment, a processor-based device includes multiple processing elements (PEs) that are each configured to support two new coherence states: walker-readable (W) and modified walker accessible (Mw). The W coherence state indicates that the corresponding coherence granule is coherent for the purposes of being read by hardware table walkers (HTWs), but is not to be considered coherent for other purposes. Accordingly, read access by hardware table walkers (HTWs) to a coherence granule having a W coherence state is permitted, but all write operations and all read operations by non-HTW agents to the coherence granule are disallowed. The Mw coherence state indicates that cached copies of the coherence granule that are only visible to the HTW (i.e., that have a coherence state of W) may exist in other caches. Additionally, the Mw coherence state indicates that the PE holding the corresponding coherence granule is responsible for updating system memory when the coherence granule is later evicted from the PE's local cache. In some embodiments, each PE may be configured to support the use of a special page table entry (SP-PTE) field store instruction for modifying SP-PTE fields of a PTE, and to indicate to the PE's local cache that the corresponding coherence granule should transition to the Mw state and to remote local caches that copies of the corresponding coherence granule should update their coherence state. In such embodiments, the Mw coherence state indicates that the PE is allowed to execute the SP-PTE field store instruction to update SP-PTE fields without needing to make an additional bus request.

In some embodiments, the SP-PTE field store instruction may be a custom store instruction, or may be a custom compare-exchange instruction. Some embodiments may provide that the SP-PTE field store instruction is a conventional memory store instruction that is directed to an address range that is associated with a page table, and that modifies only SP-PTE fields. In such embodiments, the processor-based device may automatically detect and handle the conventional memory store instruction as an SP-PTE field store instruction as described herein. Some embodiments also provide that each PE is also configured to support new bus requests, including an rd_e_w (read for exclusive, walker) bus request indicating that an SP-PTE field is being updated and the PE does not hold a coherent copy of the corresponding coherence granule; an rd_x_w (read for any, walker) bus request indicating that the PE is performing a read on behalf of an HTW and can accept a copy of the corresponding coherence granule in the W coherence state if necessary; and a prex_w (promote to exclusive, walker) bus request indicating that the PE has a shared copy of the corresponding coherence granule and wants to manage the SP-PTE fields.

In another embodiment, a processor-based device is provided. The processor-based device includes a plurality of PEs that are communicatively coupled to each other via an interconnect bus. Each PE comprises an execution pipeline comprising a decode stage and an execute stage, a system memory comprising a page table, and a local cache. A first PE of the plurality of PEs is configured to decode, using the decode stage of the execution pipeline, a special page table entry (SP-PTE) field store instruction. The first PE is further configured to execute, using the execute stage of the execution pipeline, the SP-PTE field store instruction to modify SP-PTE fields of a PTE cached in a coherence granule corresponding to the PTE in the local cache of the first PE. A second PE of the plurality of PEs is configured to receive, via the interconnect bus, a bus request from the first PE for the coherence granule. The second PE is further configured to update a coherence state of a copy of the coherence granule in the local cache of the second PE to a coherence state of walker-readable (W) to indicate that the copy of the coherence granule can only be read by a hardware table walker (HTW) of the second PE.

In another embodiment, a method for facilitating PTE maintenance is provided. The method comprises decoding, using a decode stage of an execution pipeline of a first processing element (PE) of a plurality of PEs of a processor-based device, a special page table entry (SP-PTE) field store instruction. The method further comprises executing the SP-PTE field store instruction to modify SP-PTE fields of a PTE of a page table in a system memory of the processor-based device, wherein the PTE is cached in a coherence granule corresponding to the PTE in a local cache of a first PE. The method also comprises receiving, via an interconnect bus by a second PE of the plurality of PEs, a bus request from the first PE for the coherence granule. The method additionally comprises updating, by the second PE, a coherence state of a copy of the coherence granule in the local cache of the second PE to a coherence state of walker-readable (W) to indicate that the copy of the coherence granule can only be read by a hardware table walker (HTW) of the second PE.

In another embodiment, a non-transitory computer-readable medium is provided. The computer-readable medium has stored thereon computer-executable instructions which, when executed by a processor, cause the processor to decode a special page table entry (SP-PTE) field store instruction. The computer-executable instructions further cause the processor to execute the SP-PTE field store instruction to modify SP-PTE fields of a PTE of a page table in a system memory, wherein the PTE is cached in a coherence granule corresponding to the PTE in a local cache of a first PE of a plurality of PEs. The computer-executable instructions also cause the processor to receive, via an interconnect bus by a second PE of the plurality of PEs, a bus request from the first PE for the coherence granule. The computer-executable instructions additionally cause the processor to update, by the second PE, a coherence state of a copy of the coherence granule in the local cache of the second PE to a coherence state of walker-readable (W) to indicate that the copy of the coherence granule can only be read by a hardware table walker (HTW) of the second PE.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional embodiments thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several embodiments of the disclosure, and together with the description serve to explain the principles of the disclosure.

Embodiments disclosed herein include facilitating page table entry (PTE) maintenance in processor-based devices. In one embodiment, a processor-based device includes multiple processing elements (PEs) that are each configured to support two new coherence states: walker-readable (W) and modified walker accessible (Mw). The W coherence state indicates that the corresponding coherence granule is coherent for purposes of being read by hardware table walkers (HTWs), but is not to be considered coherent for other purposes. Accordingly, read access by hardware table walkers (HTWs) to a coherence granule having a W coherence state is permitted, but all write operations and all read operations by non-HTW agents to the coherence granule are disallowed. The Mw coherence state indicates that cached copies of the coherence granule that are only visible to the HTW (i.e., that have a coherence state of W) may exist in other caches. Additionally, the Mw coherence state indicates that the PE holding the corresponding coherence granule is responsible for updating system memory when the coherence granule is later evicted from the PE's local cache. In some embodiments, each PE is configured to support the use of a special page table entry (SP-PTE) field store instruction for modifying SP-PTE fields of a PTE, and to indicate to the PE's local cache that the corresponding coherence granule should transition to the Mw state and to remote local caches that copies of the corresponding coherence granule should update their coherence state. In such embodiments, the Mw coherence state indicates that the PE is allowed to execute the SP-PTE field store instruction to update SP-PTE fields without needing to make an additional bus request.

In this regard, <FIG> illustrates an exemplary processor-based device <NUM> that provides a plurality of PEs <NUM>(<NUM>)-<NUM>(P) for concurrent processing of executable instructions. Each of the PEs <NUM>(<NUM>)-<NUM>(P) may comprise a central processing unit (CPU) having one or more processor cores, or may comprise an individual processor core comprising a logical execution unit and associated caches and functional units. In the example of <FIG>, the PEs <NUM>(<NUM>)-<NUM>(P) are communicatively coupled via an interconnect bus <NUM>, over which inter-processor communications (such as snoop requests and snoop responses, as non-limiting examples) are communicated. In some embodiments, the interconnect bus <NUM> may include additional constituent elements (e.g., a bus controller circuit and/or an arbitration circuit, as non-limiting examples) that are not shown in <FIG> for the sake of clarity. The PEs <NUM>(<NUM>)-<NUM>(P) are also communicatively coupled to a system memory <NUM> and a shared cache <NUM> via the interconnect bus <NUM>.

The system memory <NUM> of <FIG> stores a page table <NUM> containing PTEs <NUM>(<NUM>)-<NUM>(T). Each of the PTEs <NUM>(<NUM>)-<NUM>(T) represents a mapping of a virtual memory address to a physical memory address in the system memory <NUM>, and is used for virtual-to-physical address translations. The PTEs <NUM>(<NUM>)-<NUM>(T) include corresponding SP-PTE fields <NUM>(<NUM>)-<NUM>(T) that are used only by software, and that may include bits for tracking page counts and/or page age, managing page table updates, and the like, as non-limiting examples. It is to be understood that the PTEs <NUM>(<NUM>)-<NUM>(T) in some embodiments may include additional fields not illustrated in <FIG>, and further that the page table <NUM> according to some embodiments may be a multilevel page table comprising a plurality of page tables. Each PE <NUM>(<NUM>)-<NUM>(P) of <FIG> also includes a corresponding HTW <NUM>(<NUM>)-<NUM>(P), which embodies logic for searching the page table <NUM> to locate a PTE of the plurality of PTEs <NUM>(<NUM>)-<NUM>(T) needed to perform a virtual-to-physical address translation. The HTWs <NUM>(<NUM>)-<NUM>(P) include corresponding translation lookaside buffers (TLBs) <NUM>(<NUM>)-<NUM>(P) for caching recently accessed PTEs <NUM>(<NUM>)-<NUM>(T).

The PEs <NUM>(<NUM>)-<NUM>(P) of <FIG> further include corresponding execution pipelines <NUM>(<NUM>)-<NUM>(P) that are configured to execute corresponding instruction streams comprising computer-executable instructions. In the example of <FIG>, the execution pipelines <NUM>(<NUM>)-<NUM>(P) respectively include fetch stages <NUM>(<NUM>)-<NUM>(P) for retrieving instructions for execution, decode stages <NUM>(<NUM>)-<NUM>(P) for translating fetched instructions into control signals for instruction execution, and execute stages <NUM>(<NUM>)-<NUM>(P) for actually performing instruction execution. It is to be understood that some embodiments of the PEs <NUM>(<NUM>)-<NUM>(P) may include fewer or more stages than those illustrated in the example of <FIG>.

The PEs <NUM>(<NUM>)-<NUM>(P) of <FIG> also include corresponding local caches <NUM>(<NUM>)-<NUM>(P) that each store respective pluralities of coherence granules <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) (each captioned as "COGRAN" in <FIG>). The coherence granules <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) represent the smallest memory block for which coherence is maintained, and may also be referred to as "cache lines <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C). " As seen in <FIG>, the coherence granules <NUM>(<NUM>), <NUM>'(<NUM>) each has a corresponding coherence state <NUM>, <NUM>' (each captioned as "CS" in <FIG>) that indicates the coherence state for the respective coherence granules <NUM>(<NUM>), <NUM>'(<NUM>). Although not shown in <FIG>, it is to be understood that every coherence granule <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) includes a coherence state corresponding in functionality to the coherence states <NUM>, <NUM>'.

The coherence granules <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) are configured to hold copies of previously fetched data, including coherence granules corresponding to a PTE of the plurality of PTEs <NUM>(<NUM>)-<NUM>(T). Thus if a PTE needed by the HTW <NUM>(<NUM>) to perform a virtual-to-physical address translation is not found in the TLB <NUM>(<NUM>), the HTW <NUM>(<NUM>) may next attempt to retrieve the PTE from one of the coherence granules <NUM>(<NUM>)-<NUM>(C) of the local cache <NUM>(<NUM>) before fetching the PTE from the system memory <NUM>. In some embodiments, local caches <NUM>(<NUM>)-<NUM>(P) and the shared cache <NUM> may represent different levels in a cache hierarchy. The local caches <NUM>(<NUM>)-<NUM>(P) in such embodiments may represent Level <NUM> (L2) caches, while the shared cache <NUM> may represent a Level <NUM> (L3) cache.

The processor-based device <NUM> of <FIG> may encompass any one of known digital logic elements, semiconductor circuits, processing cores, and/or memory structures, among other elements, or combinations thereof. Embodiments described herein are not restricted to any particular arrangement of elements, and the disclosed techniques may be easily extended to various structures and layouts on semiconductor sockets or packages. It is to be understood that some embodiments of the processor-based device <NUM> may include elements in addition to those illustrated in <FIG>. For example, the PEs <NUM>(<NUM>)-<NUM>(P) may further include cache controller circuits for each of the local caches <NUM>(<NUM>)-<NUM>(P) and/or additional memory devices, caches, and/or controller circuits.

As noted above, as long as local copies of a particular PTE <NUM>(<NUM>)-<NUM>(T) needed by one of the HTWs <NUM>(<NUM>)-<NUM>(P) are present in the corresponding TLBs <NUM>(<NUM>)-<NUM>(P), the HTW <NUM>(<NUM>)-<NUM>(P) is oblivious to modifications to the SP-PTE fields <NUM>(<NUM>)-<NUM>(T) of the PTEs <NUM>(<NUM>)-<NUM>(T), and the PTE <NUM>(<NUM>)-<NUM>(T) continues to be accessed as needed. However, a performance issue may arise if the TLBs <NUM>(<NUM>)-<NUM>(P) are too small to hold a working set of PTEs. While updates to the SP-PTE fields <NUM>(<NUM>)-<NUM>(T) are transparent to the HTWs <NUM>(<NUM>)-<NUM>(P), PTEs that are held in the local caches <NUM>(<NUM>)-<NUM>(P) may be invalidated from the local caches <NUM>(<NUM>)-<NUM>(P) when software modifies the SP-PTE fields <NUM>(<NUM>)-<NUM>(T). Consequently, if one of the PTEs <NUM>(<NUM>)-<NUM>(T) required for virtual-to-physical address translation is not present in a TLB of the TLBs <NUM>(<NUM>)-<NUM>(P) and the corresponding local cache <NUM>(<NUM>)-<NUM>(P) has invalidated its copy of the PTE <NUM>(<NUM>)-<NUM>(T) due to a modification of an SP-PTE field <NUM>(<NUM>)-<NUM>(T), the corresponding HTW <NUM>(<NUM>)-<NUM>(P) must perform a memory read operation to obtain a copy of the PTE <NUM>(<NUM>)-<NUM>(T) from the system memory <NUM>. This performance issue may be exacerbated in processor-based devices that include multiple PEs <NUM>(<NUM>)-<NUM>(P) that are all attempting to access the same coherence granule containing the PTE <NUM>(<NUM>)-<NUM>(T) (e.g., the coherence granules <NUM>(<NUM>) and <NUM>'(<NUM>)) within their local caches <NUM>(<NUM>)-<NUM>(P).

In this regard, the PEs <NUM>(<NUM>)-<NUM>(P) are each configured to support two new coherence states: walker-readable (W) and modified walker accessible (Mw). The W coherence state indicates that read access to the corresponding coherence granule (e.g., the coherence granules <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C)) by the HTWs <NUM>(<NUM>)-<NUM>(P) is permitted, but all write operations and all read operations by non-HTW agents, such as a non-HTW agent <NUM> of the PE <NUM>(P), to the coherence granule are disallowed. The Mw coherence state indicates that cached copies of the coherence granule that are only visible to the HTWs <NUM>(<NUM>)-<NUM>(P) (i.e., that have a coherence state of W) exist in other local caches <NUM>(<NUM>)-<NUM>(P). Additionally, the Mw coherence state indicates that the PE holding the corresponding coherence granule is responsible for updating system memory when the coherence granule is later evicted from the PE's local cache. Each PE <NUM>(<NUM>)-<NUM>(P) is also configured to support the use of an SP-PTE field store instruction <NUM> for modifying the SP-PTE fields <NUM>(<NUM>)-<NUM>(T) of the PTEs <NUM>(<NUM>)-<NUM>(T), and to indicate to the corresponding local cache <NUM>(<NUM>)-<NUM>(P) that the corresponding coherence granule (e.g., one of the corresponding coherence granules <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C)) should transition to the Mw coherence state and to remote local caches <NUM>(<NUM>)-<NUM>(P) that copies of the corresponding coherence granule <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) should update their coherence states (e.g., the coherence states <NUM>, <NUM>'). In some embodiments, the SP-PTE field store instruction <NUM> may be a custom store instruction or a custom compare-exchange instruction, or may be a conventional memory store instruction that is directed to an address range that is associated with the page table <NUM>, and that modifies only SP-PTE fields such as the SP-PTE fields <NUM>(<NUM>)-<NUM>(T). In the latter case, hardware of the corresponding PE <NUM>(<NUM>)-<NUM>(P) may determine that the conventional memory store instruction is modifying only SP-PTE fields of a PTE of the page table <NUM>, and in response may process the conventional memory store instruction as described herein.

In one operation, the decode stage <NUM>(<NUM>) of the execution pipeline <NUM>(<NUM>) of the PE <NUM>(<NUM>) (the "first PE <NUM>(<NUM>)") decodes the SP-PTE field store instruction <NUM>, which is then executed by the execute stage <NUM>(<NUM>) of the execution pipeline <NUM>(<NUM>) to modify SP-PTE fields of a PTE (e.g., the SP-PTE fields <NUM>(<NUM>) of the PTE <NUM>(<NUM>)). In some embodiments, the first PE <NUM>(<NUM>) updates a coherence state of a coherence granule corresponding to the PTE <NUM>(<NUM>) (e.g., the coherence state <NUM> of the coherence granule <NUM>(<NUM>) in the local cache <NUM>(<NUM>) to a coherence state of Mw. This indicates that cached copies of the coherence granule <NUM>(<NUM>) that are visible only to the HTWs <NUM>(<NUM>)-<NUM>(P) exist in one or more of the local caches <NUM>(<NUM>)-<NUM>(P).

In some embodiments, the coherence state <NUM> may be updated to Mw in response to the first PE <NUM>(<NUM>) determining that the coherence granule <NUM>(<NUM>) corresponding to the PTE <NUM>(<NUM>) in the local cache <NUM>(<NUM>) is shared by one or more local caches <NUM>(<NUM>)-<NUM>(P) of other PEs <NUM>(<NUM>)-<NUM>(P) (e.g., the local cache <NUM>(P) of the PE <NUM>(P)). For example, if the coherence state <NUM> of the coherence granule <NUM>(<NUM>) is in a coherence state of shared modified (O), recent shared (R), or shared clean (S), the PE <NUM>(<NUM>) may transmit a prex_w (promote to exclusive, walker) bus request <NUM> via the interconnect bus <NUM> to indicate that the first PE <NUM>(<NUM>) has a shared copy of the coherence granule <NUM>(<NUM>) and seeks to manage the SP-PTE fields <NUM>(<NUM>) of the PTE <NUM>(<NUM>). The first PE <NUM>(<NUM>) may then determine if the coherence granule <NUM>(<NUM>) is shared by another local cache <NUM>(<NUM>)-<NUM>(P) based on a response <NUM> ("PREX_W RESP") to the prex_w bus request <NUM>. Similarly, if the coherence state <NUM> of the coherence granule <NUM>(<NUM>) is in a coherence state of walker-readable (W) or invalid (I), the PE <NUM>(<NUM>) may transmit an rd_e_w (read for exclusive, walker) bus request <NUM> via the interconnect bus <NUM> to indicate that the first PE <NUM>(<NUM>) is updating the SP-PTE fields <NUM>(<NUM>) of the PTE <NUM>(<NUM>) and does not hold a coherent copy of the coherence granule <NUM>(<NUM>). The first PE <NUM>(<NUM>) may then determine if the coherence granule <NUM>(<NUM>) is shared by another local cache <NUM>(<NUM>)-<NUM>(P) based on a response <NUM> ("RD_E_W RESP") to the rd_e_w bus request <NUM>.

In some embodiments, the coherence granules <NUM>(<NUM>)-<NUM>(C), <NUM>'(<NUM>)-<NUM>'(C) further include HTW installation indicators such as the HTW installation indicators <NUM> and <NUM>' (captioned as "HTWIP" in <FIG>). The HTW installation indicators <NUM>, <NUM>' indicate whether the corresponding coherence granules <NUM>(<NUM>), <NUM>'(<NUM>) were installed in the respective local caches <NUM>(<NUM>)-<NUM>(P) as a result of an HTW request. The first PE <NUM>(<NUM>) in such embodiments may update the coherence state <NUM> of the coherence granule <NUM>(<NUM>) responsive to determining that the HTW installation indicator <NUM> is set and that the SP-PTE field store instruction <NUM> is a conventional memory store instruction that modifies only the SP-PTE fields <NUM>(<NUM>) of the PTE <NUM>(<NUM>).

The second PE <NUM>(P), upon receiving a bus request from the first PE <NUM>(<NUM>) (e.g., the prex_w bus request <NUM> or the rd_e_w bus request <NUM>), may transmit a response (e.g., the response <NUM> or the response <NUM>) indicating that a copy of the coherence granule (i.e., the coherence granule <NUM>'(<NUM>) or "copy <NUM>'(<NUM>)") is cached in the local cache <NUM>(P). The second PE <NUM>(P) then updates the coherence state <NUM>' of the copy <NUM>'(<NUM>) to a coherence state of W to indicate that the copy <NUM>'(<NUM>) can only be read by the HTW <NUM>(P) of the second PE <NUM>(P).

Subsequently, the second PE <NUM>(P) may determine that the HTW <NUM>(P) is seeking to read the copy <NUM>'(<NUM>), and further may determine that the copy <NUM>'(<NUM>) has a coherence state of W. The second PE <NUM>(P) may then allow the HTW <NUM>(P) to read the copy <NUM>'(<NUM>). However, if the second PE <NUM>(P) determines that a non-HTW agent is seeking to read the copy <NUM>'(<NUM>) (or any agent, HTW or non-HTW, is seeking to write the copy <NUM>'(<NUM>)) and the copy <NUM>'(<NUM>) has a coherence state of W, the second PE <NUM>(P) will invalidate the copy <NUM>'(<NUM>) in the local cache <NUM>(P), and will process the request to read the copy <NUM>'(<NUM>) as a cache miss on the local cache <NUM>(P).

<FIG> shows a flowchart <NUM> that illustrates exemplary logic applied by a PE, such as the first PE <NUM>(<NUM>) of the processor-based device <NUM> of <FIG>, for executing an SP-PTE field store instruction and updating the coherence state of a coherence granule according to some embodiments. As seen in <FIG>, the PE executes the SP-PTE field store instruction to the coherence granule <NUM>(<NUM>) (block <NUM>). The local cache of the PE then determines whether the coherence state of the coherence granule is exclusive clean (E) or modified (M) (block <NUM>). If so, the PE can conclude that no shared copies of the coherence granule exist (block <NUM>). The PE can further conclude that no bus request is needed (block <NUM>). Thus, the coherence granule transitions to a next coherence state of Mw or M (block <NUM>). Whether the coherence granule transitions to a coherence state of Mw or M may depend on the particular implementation of the processor-based device <NUM>. In some embodiments, the processor-based device <NUM> may opt to transition the coherence state of the coherence granule to M so that any subsequent modification of a non-SP-PTE field of the coherence granule would not require a bus request to change the coherence state back to M to complete the write to the non-SP-PTE field. Other embodiments may opt to always transition to a coherence state of Mw.

If the local cache of the PE determines at decision block <NUM> that the coherence state of the coherence granule is not E or M, the local cache next determines whether the coherence state of the coherence granule is Mw (block <NUM>). If so, the PE can conclude that no copies of the coherence granule having a coherence state of O, R, or S exist (block <NUM>). The PE can further conclude that no bus request is needed (block <NUM>). Accordingly, the coherence granule transitions to a next coherence state of Mw (block <NUM>).

If, at decision block <NUM>, the coherence state of the coherence granule is determined not to be Mw, the local cache determines whether the coherence state of the coherence granule is O, R, or S (block <NUM>). If so, the PE concludes that the coherence state of the coherence granule should be upgraded to Mw (block <NUM>). Thus, the PE sends a prex_w bus request to any other PEs to indicate that the first PE has a shared copy of the coherence granule and seeks to manage the SP-PTE fields that are not visible to HTWs (block <NUM>). Once a response is received, the PE determines whether the response indicates that the coherence granule is shared (block <NUM>). If so, the coherence granule transitions to a coherence state of Mw (block <NUM>). Otherwise, the coherence granule transitions to a coherence state of M (block <NUM>).

If the local cache determines at decision block <NUM> that the coherence state of the coherence granule is not O, R, or S, the local cache next determines whether the coherence state is W or I (block <NUM>). If so, the PE can conclude that it is necessary to obtain a copy of the coherence granule with a coherence state of Mw (block <NUM>). Accordingly, the PE sends an rd_e_w bus request to any other PEs to indicate that the PE is updating SP-PTE fields that are not visible to HTWs and does not hold a coherent copy of the coherence granule (block <NUM>). Processing then resumes at block <NUM> as described above. Note that the scenario in which the local cache determines at decision block <NUM> that the coherence state of the coherence granule is not W or I is an illegal scenario that should never occur in embodiments in which the only valid coherence states are M, Mw, E, O, R, S, W, and I (block <NUM>). Note that some embodiments may include different, more, or fewer coherence states than those described herein.

To illustrate logic applied by a PE, such as the second PE <NUM>(P) of the processor-based device <NUM> of <FIG>, for responding to a bus request and updating the coherence state of a shared copy of a coherence granule on which an SP-PTE field store instruction has operated, <FIG> provides a flowchart <NUM>. In some embodiments, the PE receives an rd_e_w bus request for the coherence granule (block <NUM>). The local cache of the PE then determines whether the coherence state of the coherence granule is M or Mw (block <NUM>). If so, the PE passes responsibility to update memory to the new master (block <NUM>). The PE indicates in its snoop response that the coherence granule is shared (block <NUM>). The PE also changes the coherence state for the coherence granule to W (block <NUM>). If the local cache determines at decision block <NUM> that the coherence state of the coherence granule is not M or Mw, the local cache next determines whether the coherence state of the coherence granule is E (block <NUM>). If so, processing continues at block <NUM> as discussed above. If the coherence state is not E, processing resumes at block <NUM>.

The local cache next determines whether the coherence state of the coherence granule is R, S, or W (block <NUM>). If so, processing continues at block <NUM> as discussed above. If the local cache determines at decision block <NUM> that the coherence state is not R, S, or W, the local cache determines if the coherence state of the coherence granule is O (block <NUM>). If so, the PE passes responsibility to update memory to the new master (block <NUM>). Processing then continues at block <NUM> as discussed above. If the local cache determines at decision block <NUM> that the coherence state of the coherence granule is not O, the local cache next determines whether the coherence state of the coherence granule is I (block <NUM>). If so, processing continues in conventional fashion (block <NUM>). Note that the scenario in which the local cache determines at decision block <NUM> that the coherence state of the coherence granule is not I is an illegal scenario that should never occur in embodiments in which the only valid coherence states are M, Mw, E, O, R, S, W, and I (block <NUM>). Note that some embodiments may include different, more, or fewer coherence states than those described herein.

In some embodiments, the PE may receive a prex_w bus request for the coherence granule (block <NUM>). If so, processing continues at block <NUM> as discussed above.

<FIG> shows a flowchart <NUM> that illustrates exemplary logic applied by a PE, such as the second PE <NUM>(P) of the processor-based device <NUM> of <FIG>, for performing a read operation by an HTW on a shared copy of a coherence granule. As seen in <FIG>, the PE performs an HTW memory read access operation for the coherence granule (block <NUM>). The local cache of the PE then determines whether the coherence state of the coherence granule is E, M, Mw, O, R, S, or W (block <NUM>). If so, the PE satisfies the HTW read with data from the local cache (block <NUM>). There is also no change to the coherence state of the coherence granule (block <NUM>).

If the local cache determines at decision block <NUM> that the coherence state of the coherence granule is not E, M, Mw, O, R, S, or W, the local cache next determines whether the coherence state of the coherence granule is I (block <NUM>). If so, the PE sends an rd_x_w (read for any, walker) bus request indicating that the PE is performing a read operation on behalf of an HTW and can accept the coherence granule in the W coherence state if necessary (block <NUM>). Based on the response to the rd_x_w bus request, the PE determines whether the coherence granule will be obtained with a coherence state of W (block <NUM>). If so, the PE sets the coherence granule's coherence state to W (block <NUM>). If not, the PE follows conventional rules to set the coherence granule's coherence state to one of E, M, O, R, or S (block <NUM>). Note that the scenario in which the local cache determines at decision block <NUM> that the coherence state of the coherence granule is not I is an illegal scenario that should never occur (block <NUM>).

<FIG> is a diagram <NUM> illustrating exemplary coherence state transitions for a coherence granule, such as the coherence granule <NUM>(<NUM>), in response to the first PE <NUM>(<NUM>) of the processor-based device <NUM> of <FIG> executing the SP-PTE field store instruction <NUM>. As seen in <FIG>, if the coherence state <NUM> of the coherence granule <NUM>(<NUM>) is in an initial state of Mw, no bus request is sent, and the coherence state <NUM> of the coherence granule <NUM>(<NUM>) transitions to Mw as indicated by arrow <NUM>. If the coherence state <NUM> of the coherence granule <NUM>(<NUM>) is in an initial state of M or E, no bus request is sent, and the coherence state <NUM> of the coherence granule <NUM>(<NUM>) transitions to Mw or M, as indicated by arrows <NUM>, <NUM>, <NUM>, and <NUM>. As discussed above with respect to <FIG>, whether the coherence granule <NUM>(<NUM>) transitions to a coherence state of Mw or M may depend on the particular implementation of the processor-based device <NUM>.

If the coherence state <NUM> of the coherence granule <NUM>(<NUM>) is in an initial state of O, R, or S, the first PE <NUM>(<NUM>) sends a prex_w bus request to the other PEs of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) to indicate that the first PE <NUM>(<NUM>) has a shared copy of the coherence granule <NUM>(<NUM>) and seeks to manage the SP-PTE fields that are not visible to the HTWs <NUM>(<NUM>)-<NUM>(P). If the response to the prex_w bus request indicates that shared copies of the coherence granule <NUM>(<NUM>) are held by other PEs of the plurality of PEs <NUM>(<NUM>)-<NUM>(P), the coherence state <NUM> transitions to Mw, as indicated by arrows <NUM>, <NUM>, and <NUM>. Otherwise, the coherence state <NUM> transitions to M, as indicated by arrows <NUM>, <NUM>, and <NUM>.

Finally, if the coherence state <NUM> of the coherence granule <NUM>(<NUM>) is in an initial state of W or I, the first PE <NUM>(<NUM>) sends an rd_e_w bus request to the other PEs of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) to indicate that the first PE <NUM>(<NUM>) is updating the SP-PTE fields that are not visible to the HTWs <NUM>(<NUM>)-<NUM>(P) and does not hold a coherent copy of the coherence granule <NUM>(<NUM>). If the response to the rd_e_w bus request indicates that shared copies of the coherence granule <NUM>(<NUM>) are held by other PEs of the plurality of PEs <NUM>(<NUM>)-<NUM>(P), the coherence state <NUM> transitions to Mw, as indicated by arrows <NUM> and <NUM>. Otherwise, the coherence state <NUM> transitions to M, as indicated by arrows <NUM> and <NUM>.

To illustrate coherence state transitions for a coherence granule, such as the coherence granule <NUM>(<NUM>) of <FIG>, in response to the first PE <NUM>(<NUM>) of the processor-based device <NUM> of <FIG> executing a conventional memory store operation, <FIG> provides a diagram <NUM>. If the coherence state <NUM> of the coherence granule <NUM>(<NUM>) is in an initial state of Mw, the first PE <NUM>(<NUM>) sends a prex (promote to exclusive) bus request to the other PEs of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) to indicate that the first PE <NUM>(<NUM>) has a shared copy of the coherence granule <NUM>(<NUM>). The coherence state <NUM> then transitions to M, as indicated by arrow <NUM>. If the coherence state <NUM> of the coherence granule <NUM>(<NUM>) is in an initial state of M or E, no bus request is sent, and the coherence state <NUM> transitions to M, as indicated by arrows <NUM> and <NUM>.

If the coherence state <NUM> of the coherence granule <NUM>(<NUM>) is in an initial state of O, R, or S, the first PE <NUM>(<NUM>) sends a prex bus request to the other PEs of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) to indicate that the first PE <NUM>(<NUM>) has a shared copy of the coherence granule <NUM>(<NUM>). The coherence state <NUM> then transitions to M, as indicated by arrow <NUM>, <NUM>, and <NUM>. Finally, if the coherence state <NUM> of the coherence granule <NUM>(<NUM>) is in an initial state of W or I, the first PE <NUM>(<NUM>) sends an rd_e (read for exclusive) bus request to indicate that the first PE <NUM>(<NUM>) does not hold a coherent copy of the coherence granule <NUM>(<NUM>). The coherence state <NUM> then transitions to M, as indicated by arrows <NUM> and <NUM>.

<FIG> shows a diagram <NUM> illustrating coherence state transitions for a coherence granule, such as the coherence granule <NUM>(<NUM>) of <FIG>, in response to the HTW <NUM>(<NUM>) of the first PE <NUM>(<NUM>) of the processor-based device <NUM> of <FIG> performing a read operation. In the example of <FIG>, if the coherence state <NUM> of the coherence granule <NUM>(<NUM>) is in an initial state of Mw, M, E, O, R, S, or W, no bus request is sent and the coherence state <NUM> remains the same, as indicated by arrows <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. If the coherence state <NUM> of the coherence granule <NUM>(<NUM>) is in an initial state of I, the first PE <NUM>(<NUM>) sends an rd_x_w bus request, and the coherence state <NUM> transitions to M, E, O, R, S, or W as appropriate, as indicated by arrow <NUM>.

<FIG> provides a diagram <NUM> illustrating coherence state transitions for a coherence granule, such as the coherence granule <NUM>'(<NUM>) of <FIG>, in response to a read operation by a non-HTW agent, such as the non-HTW agent <NUM> of the second PE <NUM>(P) of the processor-based device of <FIG>. As seen in <FIG>, if the coherence state <NUM>' of the coherence granule <NUM>'(<NUM>) is in an initial state of Mw, M, E, O, R, or S, no bus request is sent and the coherence state <NUM>' remains the same, as indicated by arrows <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. If the coherence state <NUM>' of the coherence granule <NUM>'(<NUM>) is in an initial state of W or I, an rd_x bus request is sent, and the coherence state <NUM>' transitions to M, E, O, R, or S as appropriate, as indicated by arrows <NUM> and <NUM>.

To illustrate exemplary operations of the first PE <NUM>(<NUM>) of the processor-based device <NUM> of <FIG> for facilitating PTE maintenance using the Mw coherence state, <FIG> and <FIG> provide a flowchart <NUM>. For the sake of clarity, elements of <FIG> are referenced in describing <FIG> and <FIG>. In some embodiments, operations in <FIG> begin with the first PE <NUM>(<NUM>) of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) installing the coherence granule <NUM>(<NUM>) corresponding to the PTE <NUM>(<NUM>) to the local cache <NUM>(<NUM>) of the first PE <NUM>(<NUM>) (block <NUM>). The first PE <NUM>(<NUM>) may then set the HTW installation indicator <NUM> for the coherence granule <NUM>(<NUM>) to indicate whether the coherence granule <NUM>(<NUM>) was installed as a result of an HTW request (block <NUM>). The decode stage <NUM>(<NUM>) of the execution pipeline <NUM>(<NUM>) of the first PE <NUM>(<NUM>) of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) of the processor-based device <NUM> next decodes the SP-PTE field store instruction <NUM> (block <NUM>). The first PE <NUM>(<NUM>) then executes the SP-PTE field store instruction <NUM> to modify the SP-PTE fields <NUM>(<NUM>) of the PTE <NUM>(<NUM>) of the page table <NUM> in the system memory <NUM> of the processor-based device <NUM> using the execute stage <NUM>(<NUM>) of the execution pipeline <NUM>(<NUM>), wherein the PTE <NUM>(<NUM>) is cached in the coherence granule <NUM>(<NUM>) corresponding to the PTE <NUM>(<NUM>) in the local cache <NUM>(<NUM>) of the first PE <NUM>(<NUM>) (block <NUM>).

The second PE <NUM>(P) receives, via the interconnect bus <NUM>, a bus request (such as the prex_w bus request <NUM> or the rd_e_w bus request <NUM>, as non-limiting examples) from the first PE <NUM>(<NUM>) for the coherence granule <NUM>(<NUM>) (block <NUM>). The second PE <NUM>(P), in some embodiments, transmits, to the first PE <NUM>(<NUM>) via the interconnect bus <NUM>, a response (e.g., the response <NUM> or the response <NUM>, as non-limiting examples) to the bus request indicating that the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) is cached in the local cache <NUM>(P) of the second PE <NUM>(P) (block <NUM>). Processing then resumes at block <NUM> of <FIG>.

Referring now to <FIG>, the second PE <NUM>(P) next updates the coherence state <NUM>' of the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) in the local cache <NUM>(P) of the second PE <NUM>(P) to the coherence state of W to indicate that the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) can only be read by an HTW (such as the HTW <NUM>(P)) of the second PE <NUM>(P) (block <NUM>). In some embodiments, the first PE <NUM>(<NUM>) may determine whether the coherence granule <NUM>(<NUM>) corresponding to the PTE <NUM>(<NUM>) in the local cache <NUM>(<NUM>) of the first PE <NUM>(<NUM>) is shared by the one or more local caches <NUM>(<NUM>)-<NUM>(P) of the one or more other PEs <NUM>(<NUM>)-<NUM>(P) of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) (block <NUM>). If the coherence granule <NUM>(<NUM>) is not shared by the one or more local caches <NUM>(<NUM>)-<NUM>(P), processing continues in conventional fashion (block <NUM>). However, if the first PE <NUM>(<NUM>) determines at decision block <NUM> that the coherence granule <NUM>(<NUM>) is shared by the one or more local caches <NUM>(<NUM>)-<NUM>(P) (or the embodiment of the first PE <NUM>(<NUM>) does not perform the operations of decision block <NUM>), the first PE <NUM>(<NUM>) updates the coherence state <NUM> of the coherence granule <NUM>(<NUM>) corresponding to the PTE <NUM>(<NUM>) in the local cache <NUM>(<NUM>) of the first PE <NUM>(<NUM>) to the coherence state of Mw to indicate that cached copies of the coherence granule <NUM>(<NUM>) that are visible only to HTWs may exist in one or more local caches <NUM>(<NUM>)-<NUM>(P) of the corresponding one or more other PEs <NUM>(<NUM>)-<NUM>(P) of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) (block <NUM>). In some embodiments, the operations of block <NUM> for updating the coherence state <NUM> to the coherence state of Mw are performed responsive to determining that the HTW installation indicator <NUM> for the coherence granule <NUM>(<NUM>) is set, and that the SP-PTE field store instruction <NUM> is a conventional memory store instruction that modifies only the SP-PTE fields <NUM>(<NUM>) of the PTE <NUM>(<NUM>) (block <NUM>).

<FIG> provides a flowchart <NUM> to illustrate further exemplary operations of the first PE <NUM>(<NUM>) of the processor-based device <NUM> of <FIG> for sending bus commands to determine whether a shared copy of the coherence granule <NUM>(<NUM>) that is the target of the SP-PTE field store instruction <NUM> exists in other PEs <NUM>(<NUM>)-<NUM>(P) (and thus the other PEs <NUM>(<NUM>)-<NUM>(P) need to set the coherence state of their shared copies to W), according to some embodiments. Elements of <FIG> are referenced in describing <FIG> for the sake of clarity. In <FIG>, operations begin with the first PE <NUM>(<NUM>) determining the coherence state <NUM> of the coherence granule <NUM>(<NUM>) corresponding to the PTE <NUM>(<NUM>) in the local cache <NUM>(<NUM>) of the first PE <NUM>(<NUM>) (block <NUM>). If the first PE <NUM>(<NUM>) determines at decision block <NUM> that the coherence granule <NUM>(<NUM>) corresponding to the PTE <NUM>(<NUM>) in the local cache <NUM>(<NUM>) of the first PE <NUM>(<NUM>) is in a coherence state of O, R, or S, the first PE <NUM>(<NUM>) transmits, via the interconnect bus <NUM> of the processor-based device <NUM>, the prex_w bus request <NUM> indicating that the first PE <NUM>(<NUM>) has a shared copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) and seeks to manage the SP-PTE fields <NUM>(<NUM>) of the PTE <NUM>(<NUM>) (block <NUM>). However, if the first PE <NUM>(<NUM>) determines at decision block <NUM> that the coherence granule <NUM>(<NUM>) corresponding to the PTE <NUM>(<NUM>) in the local cache <NUM>(<NUM>) of the first PE <NUM>(<NUM>) is in a coherence state of W or I, the first PE <NUM>(<NUM>) transmits the rd_e_w bus request <NUM> indicating that the first PE <NUM>(<NUM>) is updating the SP-PTE fields <NUM>(<NUM>) of the PTE <NUM>(<NUM>) and does not hold a coherent copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) (block <NUM>). In the scenarios represented by blocks <NUM> and <NUM>, the bus request received by the second PE <NUM>(P) as described above with respect to block <NUM> of <FIG> may comprise the prex_w bus request <NUM> or the rd_e_w bus request <NUM>, respectively.

<FIG> provides a flowchart <NUM> to illustrate further exemplary operations of the second PE <NUM>(P) of the processor-based device <NUM> of <FIG> for allowing HTW reads to the shared copy <NUM>'(<NUM>) of the coherence granule <NUM>'(<NUM>) having the coherence state of W, according to some embodiments. Elements of <FIG> are referenced in describing <FIG> for the sake of clarity. In <FIG>, operations begin with the local cache <NUM>(P) of the second PE <NUM>(P) determining that the HTW <NUM>(P) of the second PE <NUM>(P) seeks to read the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) (block <NUM>). The local cache <NUM>(P) of the second PE <NUM>(P) next determines that the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) has a coherence state of W (block <NUM>). Responsive to determining that the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) has a coherence state of W, the local cache <NUM>(P) of the second PE <NUM>(P) allows the HTW <NUM>(P) to read the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) (block <NUM>).

To illustrate further exemplary operations of the second PE of the processor-based device of <FIG> for disallowing reads by non-HTW agents to the shared copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) having the coherence state of W, <FIG> provides a flowchart <NUM>. For the sake of clarity, elements of <FIG> are referenced in describing <FIG>. Operations in <FIG> begin with the local cache <NUM>(P) of the second PE <NUM>(P) determining that the non-HTW agent <NUM> of the second PE <NUM>(P) seeks to read the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) (block <NUM>). The local cache <NUM>(P) of the second PE <NUM>(P) determines that the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) has a coherence state of W (block <NUM>). Responsive to determining that the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) has a coherence state of W, the local cache <NUM>(P) performs a series of operations (block <NUM>). The local cache <NUM>(P) invalidates the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) (block <NUM>). The local cache <NUM>(P) then processes the request to read the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) as a cache miss (block <NUM>). It is to be understood that, in some embodiments, the local cache <NUM>(P) also disallows all memory store operations to the copy <NUM>'(<NUM>) of the coherence granule <NUM>(<NUM>) having the coherence state of W.

<FIG> is a block diagram of an exemplary processor-based device <NUM>, such as the processor-based device <NUM> of <FIG>, that provides facilitated PTE maintenance. The processor-based device <NUM> may be a circuit or circuits included in an electronic board card, such as, a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based device <NUM> includes a processor <NUM>. The processor <NUM> represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, or the like, and may correspond to the PEs <NUM>(<NUM>)-<NUM>(P) of <FIG>. The processor <NUM> is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor <NUM> includes an instruction cache <NUM> for temporary, fast access memory storage of instructions and an instruction processing circuit <NUM>. Fetched or prefetched instructions from a memory, such as from a system memory <NUM> over a system bus <NUM>, are stored in the instruction cache <NUM>. The instruction processing circuit <NUM> is configured to process instructions fetched into the instruction cache <NUM> and process the instructions for execution.

The processor <NUM> and the system memory <NUM> are coupled to the system bus <NUM> (corresponding to the interconnect bus <NUM> of <FIG>) and can intercouple peripheral devices included in the processor-based device <NUM>. As is well known, the processor <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the processor <NUM> can communicate bus transaction requests to a memory controller <NUM> in the system memory <NUM> as an example of a peripheral device. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus constitutes a different fabric. In this example, the memory controller <NUM> is configured to provide memory access requests to a memory array <NUM> in the system memory <NUM>. The memory array <NUM> is comprised of an array of storage bit cells for storing data. The system memory <NUM> may be a read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), etc., and a static memory (e.g., flash memory, static random access memory (SRAM), etc.), as non-limiting examples.

Other devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include the system memory <NUM>, one or more input devices <NUM>, one or more output devices <NUM>, a modem <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The modem <NUM> can be any device configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem <NUM> can be configured to support any type of communications protocol desired. The processor <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display(s) <NUM> can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc..

The processor-based device <NUM> in <FIG> may include a set of instructions <NUM> that may be encoded with the reach-based explicit consumer naming model to be executed by the processor <NUM> for any application desired according to the instructions. The instructions <NUM> may be stored in the system memory <NUM>, processor <NUM>, and/or instruction cache <NUM> as examples of a non-transitory computer-readable medium <NUM>. The instructions <NUM> may also reside, completely or at least partially, within the system memory <NUM> and/or within the processor <NUM> during their execution. The instructions <NUM> may further be transmitted or received over the network <NUM> via the modem <NUM>, such that the network <NUM> includes the computer-readable medium <NUM>.

While the computer-readable medium <NUM> is shown in an exemplary embodiment to be a single medium, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions <NUM>. The term "computer-readable medium" shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by a processing device and that cause the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term "computer-readable medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical medium, and magnetic medium.

The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

The embodiments disclosed herein may be provided as a computer program product, or software, that may include a machine-readable medium (or computer-readable medium) having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: a machine-readable storage medium (e.g., ROM, random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, flash memory devices, etc.), and the like.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The components of the distributed antenna systems described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

Claim 1:
A processor-based device (<NUM>) comprising a plurality of processing elements, PEs, (<NUM>(<NUM>)-<NUM>(P)) communicatively coupled to each other via an interconnect bus (<NUM>), each PE comprising a hardware table walker, HTW, and :
an execution pipeline (<NUM>(<NUM>)-<NUM>(P)) comprising a decode stage (<NUM>(<NUM>)-<NUM>(P)) and an execute stage (<NUM>(<NUM>)-<NUM>(P));
a system memory (<NUM>) comprising a page table (<NUM>); and
a local cache (<NUM>(<NUM>)-<NUM>(P));
a first PE (<NUM>(<NUM>)) of the plurality of PEs configured to:
decode (<NUM>), using the decode stage of the execution pipeline, a special page table entry, SP-PTE, field store instruction (<NUM>); and
execute (<NUM>), using the execute stage of the execution pipeline, the SP-PTE field store instruction to modify SP-PTE fields (<NUM>(<NUM>)-<NUM>(T)) of a PTE (<NUM>(<NUM>)-<NUM>(T)) cached in a cache line (<NUM>(<NUM>)) corresponding to the PTE in the local cache (<NUM>(<NUM>)) of the first PE; and
a second PE (<NUM>(P)) of the plurality of PEs configured to:
receive (<NUM>), via the interconnect bus, a bus request (<NUM>, <NUM>) from the first PE for the cache line; and
update (<NUM>) a coherence state (<NUM>') of a copy (<NUM>'(<NUM>)) of the cache line in the local cache of the second PE to a coherence state of walker-readable, W, to indicate that the copy of the cache line can only be read by a hardware table walker, HTW, (<NUM>(P)) of the second PE to perform virtual to physical address translation, and wherein the modification of the SP-PTE fields is not visible to hardware table walkers.