Patent Description:
An image sensing device may be a semiconductor element that converts optical information into an electric signal. Examples of such an image sensing device may include a charge coupled device (CCD) image sensing device and a complementary metal-oxide semiconductor (CMOS) image sensing device.

The CMOS image sensor may be abbreviated as a CIS (CMOS image sensor). The CIS may include a plurality of pixels arranged two-dimensionally. Each of the pixels may include, e.g., a photodiode (PD). The photodiode may serve to convert incident light into electrical signals.

Recently, with development of the computer industry and the telecommunication industry, demands for image sensors with improved performance in various fields, such as a digital camera, a video camera, a smart phone, a game console, a security camera, a medical micro camera, a robot, and a vehicle have increased.

<CIT> discloses a pixel cell including a plurality of subpixels to generate image charge in response to incident light. The subpixels include an inner subpixel laterally surrounded by outer subpixels. A first plurality of transfer gates disposed proximate to the inner subpixel and a first grouping of outer subpixels. A first floating diffusion is coupled to receive the image charge from the first grouping of outer subpixels through a first plurality of transfer gates. A second plurality of transfer gates disposed proximate to the inner subpixel and the second grouping of outer subpixels. A second floating diffusion disposed in the semiconductor material and coupled to receive the image charge from each one of the second grouping of outer subpixels through the second plurality of transfer gates. The image charge in the inner subpixel is received by the first, second, or both floating diffusions through respective transfer gates.

<CIT> discloses a pixel cell having a large and small photodiode, transfer transistors, a reset transistor, a dynamic range enhancement capacitor, a capacitor control transistor, a storage capacitor, a storage capacitor control transistor, an amplifier transistor in a source follower configuration and a rolling shutter row select transistor and a readout circuit block. The small and large photodiodes are exposed simultaneously, the large photodiode having a constant exposure while the small photodiode has a chopped exposure and charge transfer to a storage capacitor.

<CIT> discloses a dual pixel-size color image sensor, including an imaging surface, for imaging of incident light, and a plurality of color pixels, each color pixel including (a) four large photosites, including two large first-color photosites sensitive to a first color of the incident light, and (b) four small photosites including two small first-color photosites sensitive to the first color of the incident light. The large and small first-color photosites are arranged such that connected regions of the imaging surface, not associated with large and/or small first-color photosites, are not continuous straight lines. A method for manufacturing a color filter array on an imaging surface of a dual pixel-size image sensor includes forming a first-color coating on first portions of the imaging surface to form large and small first-color photosites sensitive to a first color, wherein connected portions of the imaging surface, different from the first portions, are not continuous straight lines.

<CIT> discloses image sensors including an array of pixels each having nested sub-pixels. Nested sub-pixels may include an inner photosensitive region and an outer photosensitive region. Inner photosensitive regions of pixels in an array may be provided with a respective local vertical transfer gate structure formed in a trench that laterally surrounds the inner photosensitive region. A trench structure may be formed in a grid-like pattern having gaps in which the nested sub-pixels are formed. The trench structure may be coupled to outer photosensitive regions of each of the pixels in the array. The trench structure may be a global vertical transfer gate structure. The vertical transfer gate structures provided to the pixels may allow for accumulated charges to be transferred to respective charge storage nodes associated with the photosensitive regions in any given pixel. Image sensors formed in this way may be used in rolling shutter or global shutter configurations.

According to a first aspect there is provided an image sensor according to claim <NUM>.

Features will become apparent to those of skill in the art by describing in detail example embodiments with reference to the attached drawings in which:.

<FIG> is a block diagram for explaining an image sensing device according to some example embodiments.

Referring to <FIG>, an image sensing device <NUM> according to some example embodiments may include an image sensor <NUM> and an image signal processor <NUM>.

The image sensor <NUM> may generate an image signal IS by sensing an image to be sensed using light. The generated image signal IS may be, e.g., a digital signal.

The image signal IS may be provided to the image signal processor <NUM> and processed therein. The image signal processor <NUM> may receive the image signal IS that is output from a buffer <NUM> of the image sensor <NUM>, and may process or treat the received image signal IS to display the image signal.

The image signal processor <NUM> may perform digital binning on the image signal IS that is output from the image sensor <NUM>. The image signal IS that is output from the image sensor <NUM> may be a raw image signal from the pixel array <NUM> without analog binning, and may also be the image signal IS on which the analog binning has already been performed.

The image sensor <NUM> and the image signal processor <NUM> may be disposed separately from each other, e.g., the image sensor <NUM> may be mounted on a first chip and the image signal processor <NUM> may be mounted on a second chip to communicate with each other through a predetermined interface. In another implementation, the image sensor <NUM> and the image signal processor <NUM> may be implemented as a single package, e.g., a multi-chip package (MCP).

The image sensor <NUM> may include a pixel array <NUM>, a control register block <NUM>, a timing generator <NUM>, a row driver <NUM>, a readout circuit <NUM>, a ramp signal generator <NUM>, and a buffer <NUM>.

The control register block <NUM> may generally control the operation of the image sensor <NUM>. For example, the control register block <NUM> may directly transmit an operating signal to the timing generator <NUM>, the ramp signal generator <NUM>, and the buffer <NUM>.

The timing generator <NUM> may generate a signal that serves as a reference for the operating timing of various components of the image sensor <NUM>. An operating timing reference signal generated by the timing generator <NUM> may be sent to the ramp signal generator <NUM>, the row driver <NUM>, the readout circuit <NUM>, and the like.

The ramp signal generator <NUM> may generate and transmit the ramp signal that is used in the readout circuit <NUM>. The readout circuit <NUM> may include a correlated double sampler (CDS), a comparator, or the like. The ramp signal generator <NUM> may generate and transmit the ramp signal that is used in the correlated double sampler (CDS), the comparator, or the like.

The row driver <NUM> may selectively activate the rows of the pixel array <NUM>.

The pixel array <NUM> may sense an external image. The pixel array <NUM> may include a plurality of pixels.

The readout circuit <NUM> may sample the pixel signal provided from the pixel array <NUM>, compare the pixel signal to the ramp signal, and then convert an analog image signal (data) into a digital image signal (data) on the basis of the comparison results.

The buffer <NUM> may include, e.g., a latch. The buffer <NUM> may temporarily store the image signal IS to be provided to the outside, and may transmit the image signal IS to an external memory or an external device.

<FIG> is a diagram that shows a conceptual layout of the image sensor according to some example embodiments.

Referring to <FIG>, an image sensor <NUM>-<NUM> according to some example embodiments may include a first layer <NUM> and a second layer <NUM> which are stacked. The first layer <NUM> may be disposed above the second layer <NUM> and may be electrically connected to the second layer <NUM>.

The first layer <NUM> may include a pixel array <NUM> in which a plurality of pixels are arranged in a two-dimensional array structure. The pixel array <NUM> may correspond to the pixel array <NUM> of <FIG>.

The second layer <NUM> may include a logic region <NUM> in which logic elements are located. The logic elements included in the logic region <NUM> may be electrically connected to the pixel array <NUM> and may provide a signal to the pixel or process the signal output from the pixel. The logic region <NUM> may include, e.g., the control register block <NUM>, the timing generator <NUM>, the ramp signal generator <NUM>, the row driver <NUM>, the readout circuit <NUM>, and the like of <FIG>.

<FIG> is a diagram for explaining a pixel array according to some example embodiments.

Referring to <FIG>, a pixel array PA-<NUM> according to some example embodiments may include a plurality of pixel groups, e.g., a first pixel group PG1, a second pixel group PG2, a third pixel group PG3, and a fourth pixel group PG4. The plurality of pixel groups PG1, PG2, PG3, and PG4 may be regularly arranged in a first direction X and a second direction Y. The first direction X and second direction Y may be perpendicular to each other. The first direction X and second direction Y may be parallel to a font or rear surface of a substrate (e.g. first side 110a of or second side 11b of first substrate <NUM> shown in <FIG> and <FIG>) of the image sensor <NUM>-<NUM>. The first pixel group PG1 and the second pixel group PG2 may be arranged along the first direction X, and the third pixel group PG3 and the fourth pixel group PG4 may be arranged along the first direction X. The third pixel group PG3 and the first pixel group PG1 may be arranged along the second direction Y, and the fourth pixel group PG4 and the second pixel group GP2 may be arranged along the second direction Y.

A color filter having the same color may be disposed on each of the pixel groups PG1, PG2, PG3, and PG4. In another implementation, a color filter having a first color may be disposed on the first pixel group PG1, a color filter having a second color may be disposed on the second pixel group PG2, a color filter having a third color may be disposed on the third pixel group PG3, and color filter having a fourth color may be disposed on the fourth pixel group PG4. The first color may be red, the second and third colors may be green, the fourth color may be blue, and the color filters may be arranged in a Bayer pattern. In another example, the color filter may include a yellow filter, a magenta filter, and a cyan filter, and may further include a white filter. This may reduce the difficulty of the fabricating process of the image sensor.

<FIG> is a diagram for explaining the first pixel group of <FIG>.

Since the second to fourth pixel groups PG2, PG3, and PG4 of <FIG> may be similar to the first pixel group PG1, the first pixel group PG1 will be mainly described below.

Referring to <FIG>, a first pixel group PG1-<NUM> according to some example embodiments may include a first region REG1 and a second region REG2.

The first region REG1 may include at least one first pixel including at least one first photodiode, e.g., first-<NUM>, first-<NUM>, first-<NUM>, and first-<NUM> pixels LPX1, LPX2, LPX3, and LPX4 each including at least one first photodiode. The first-<NUM> to first-<NUM> pixels LPX1 to LPX4 may be referred to respectively or collectively as first pixels.

The second region REG2 may include at least one second pixel including a second photodiode, e.g., second-<NUM>, second-<NUM>, second-<NUM>, and second-<NUM> pixels SPX1, SPX2, SPX3, and SPX4 each including a second photodiode. The second-<NUM> to second-<NUM> pixels SPX1 to SPX4 may be referred to respectively or collectively as second pixels.

At least one of at least one first pixel LPX1, LPX2, LPX3, and LPX4 and at least one second pixel SPX1, SPX2, SPX3, and SPX4 may be arranged in an m*n arrangement (m and n are natural numbers of <NUM> or more). For example, at least one first pixel and at least one second pixel may be paired and arranged in an m*n arrangement, wherein m and n are natural numbers of <NUM> or more. For example, the first region REG1 may include first pixels LPX1, LPX2, LPX3, and LPX4 arranged in a <NUM>*<NUM> arrangement, and the second region REG2 may include the second pixels SPX1, SPX2, SPX3, and SPX4 arranged in a <NUM>*<NUM> arrangement. The at least one first pixel LPX1, LPX2, LPX3, and LPX4 may form a first set comprising one or more first pixels LPX1, LPX2, LPX3, and LPX4. The at least one second pixel SPX1, SPX2, SPX3, and SPX4 may form a second set comprising one or more second pixels SPX1, SPX2, SPX3, and SPX4. At least one of the first set and the second set may comprise pixels (e.g. first pixels LPX1, LPX2, LPX3, and LPX4, or second pixels SPX1, SPX2, SPX3, and SPX4) that are arranged in an m*n arrangement. That is, the first set may comprise first pixels LPX1, LPX2, LPX3, and LPX4arranged in an m*n arrangement and/or the second set may comprise second pixels SPX1, SPX2, SPX3, and SPX4 arranged in an m*n arrangement.

In plane view, referring to <FIG>, the first region REG1 may surround, e.g., completely surround the second region REG2. In plane view, the first pixel group PG1-<NUM> may have a rectangular shape, and the second region REG2 may have a rectangular shape. In plane view, the first pixels LPX1, LPX2, LPX3, and LPX4 may have a "∧" or notched shape (or "L" shape), and the second pixels SPX1, SPX2, SPX3, and SPX4 may have a rectangular shape.

In plane view, an area of the first region REG1 may be greater than an area of the second region REG2. In plane view, a total area of the first photodiode(s) included in the first region REG1 may be greater than a total area of the second photodiode(s) included in the second region REG2.

<FIG> is an example circuit diagram for explaining the first pixel and the second pixel of <FIG>. <FIG> is an example layout diagram for explaining the first pixel and the second pixel of <FIG>. <FIG> and <FIG> are example cross-sectional views taken along A-A' of <FIG>. <FIG> is a diagram for explaining the microlens according to some example embodiments.

Referring to <FIG> and <FIG>, the first pixel LPX1 includes a first photodiode LPD, a first floating diffusion region FD1, a first transfer transistor LTX between the first photodiode LPD and the first floating diffusion region FD1, and a connecting transistor DRX. The second pixel SPX1 includes a second photodiode SPD, a third floating diffusion region FD3, and a second transfer transistor STX between the second photodiode SPD and the third floating diffusion region FD3. The connecting transistor DRX connects the first floating diffusion region FD1 and the third floating diffusion region FD3.

Referring to <FIG>, the first pixel LPX1 may include a grounded region GND, the first photodiode LPD, the first transfer transistor LTX, a source follower transistor SX, a selection transistor AX, the connecting transistor DRX, a reset transistor RX, and a first switch transistor SWX. The second pixel SPX2 may include the grounded region GND, a second switch transistor TSWX, the second photodiode SPD, and the second transfer transistor STX.

The first photodiode LPD may generate electric charges in proportion to the amount of light incident from the outside. The first photodiode LPD may convert the light incident on the first pixel LPX1 into electric charges. One end of the first photodiode LPD may be connected to a ground voltage.

The first transfer transistor LTX may be connected between the first photodiode LPD and the first floating diffusion region FD1. One end of the first transfer transistor LTX may be connected to the first photodiode LPD, and the other end of the first transfer transistor LTX may be connected to the first floating diffusion region FD1. The first transfer transistor LTX may be driven by a first transfer signal applied through a first transfer gate LTG of the first transfer transistor LTX. The first transfer transistor LTX may transfer the electric charges generated by the first photodiode LPD to the first floating diffusion region FD1.

A source follower gate SF of the source follower transistor SX may be connected to the first floating diffusion region FD1. The source follower gate SF may be connected to the first floating diffusion region FD1 to receive electric charges. The source follower transistor SX may amplify a change in electric potential of the first floating diffusion region FD1 and output it to an output voltage VOUT. When the source follower transistor SX is turned on, the source follower transistor SX may transfer a first voltage VPIX to the selection transistor AX.

The selection transistor AX may be connected to the source follower transistor SX and the output voltage VOUT. The selection transistor AX may select a pixel region to be read in row units. The selection transistor AX may be driven by a row selection signal applied to a selection gate SEL of the selection transistor AX.

The connecting transistor DRX connects the first floating diffusion region FD1 and the second floating diffusion region FD2. The connecting transistor DRX may be driven by a connection signal to be applied to a connecting gate DRG of the connecting transistor DRX.

The reset transistor RX may be driven by a reset signal to be applied to the reset gate RG of the reset transistor RX. When the reset transistor RX is turned on, the reset transistor RX may transfer a second voltage VRD to the second floating diffusion region FD2. Accordingly, the first pixel LPX1 and the second pixel SPX1 may be reset.

The first switch transistor SWX may be located between the second floating diffusion region FD2 and the third floating diffusion region FD3. The first switch transistor SWX may be driven by a first switch signal to be applied to a first switch gate SW of the first switch transistor SWX. When the first switch transistor SWX is turned on, the first switch transistor SWX may connect the second floating diffusion region FD2 and the third floating diffusion region FD3.

A capacitor C and the second switch transistor TSWX may be located between a third voltage VSC and the third floating diffusion region FD3. The second switch transistor TSWX may be driven by a second switch signal to be applied to a second switch gate TSW of the second switch transistor TSWX. When the second switch transistor TSWX is turned on, the second switch transistor TSWX may connect the third floating diffusion region FD3 and the capacitor C. The second switch transistor TSWX may send electric charges that overflow from the second photodiode SPD to the capacitor C. The capacitor C may store the electric charges that overflow from the second photodiode SPD. The capacitor C may not be disposed in the first region REG1 and the second region REG2. For example, the capacitor C may be disposed in the second layer <NUM> of <FIG>.

At least a selection of the first to third voltages VPIX, VRD, and VSC may be equal to each other. Alternatively, the first to third voltages VPIX, VRD, and VSC may be different from each other.

The second photodiode SPD may generate electric charges in proportion to the amount of light incident from the outside. The second photodiode SPD may convert the light incident on the second pixel SPX1 into electric charges. One end of the second photodiode SPD may be connected to the ground voltage.

The second transfer transistor STX may be connected between the second photodiode SPD and the second floating diffusion region FD2. One end of the second transfer transistor STX may be connected to the second photodiode SPD, and the other end of the second transfer transistor STX may be connected to the third floating diffusion region FD3. The second transfer transistor STX may include a second transfer gate STG. The second transfer transistor STX may be driven by a second transfer signal, and the second transfer signal may be applied through the second transfer gate STG. The second transfer transistor STX may transmit electric charges generated by the second photodiode SPD to the third floating diffusion region FD3. The first floating diffusion region FD1 and the third floating diffusion region FD3 may be connected by the first switch transistor SWX and the connecting transistor DRX.

The first pixel LPX1 may further include a dummy transistor. Referring to <FIG>, a dummy gate DTG of the dummy transistor may be disposed in the first pixel LPX1.

Referring to <FIG>, <FIG>, and <FIG>, the image sensor may include a first substrate <NUM>, the first photodiode LPD, the second photodiode SPD, an element separation film <NUM>, a pixel separation pattern <NUM>, a surface insulating film <NUM>, a grid pattern <NUM>, a first protective film <NUM>, a color filter <NUM>, a microlens <NUM>, and a second protective film <NUM>.

The first substrate <NUM> may include a first side 110a and a second side 110b that are opposite to each other. In the description below, the first side 110a may be referred to as a front side of the first substrate <NUM>, and the second side 110b may be referred to as a back side of the first substrate <NUM>. The second side 110b of the first substrate <NUM> may be a light-receiving surface on which light is incident, e.g., the image sensor may be implemented as a backside illumination (BSI) image sensor.

The first substrate <NUM> may be a semiconductor substrate. For example, the first substrate <NUM> may be bulk silicon or silicon-on-insulator (SOI). The first substrate <NUM> may be a silicon substrate or may include other materials, e.g., silicon germanium, indium antimonide, lead tellurium compounds, indium arsenic, indium phosphide, gallium arsenide or gallium antimonide. In an implementation, the first substrate <NUM> may have an epitaxial layer formed on a base substrate.

The first substrate <NUM> may have a first conductive type. For example, the first substrate <NUM> may include p-type impurities (e.g., boron (B)). Although the first conductive type will be described as a p-type in the following description, this is merely by way of example, and the first conductive type may be an n-type.

The first pixel LPX1 and the second pixel SPX1 may be formed on the first substrate <NUM>. The first photodiode LPD may be formed inside the first substrate <NUM> of the first pixel LPX1. The second photodiode SPD may be formed inside the first substrate <NUM> of the second pixel LPX2. The first photodiode LPD and the second photodiode SPD may have a second conductive type different from the first conductive type. Although the second conductive type will be described as an n-type in the following description, this is merely by way of example, and the second conductive type may be a p-type. The first photodiode LPD and the second photodiode SPD may be formed, e.g., by ion-implantation of an n-type impurity (e.g., phosphorus (P) or arsenic (As)) into the p-type first substrate <NUM>. The first photodiode LPD and the second photodiode SPD may have a potential gradient in a direction (e.g., a vertical direction) that intersects the first side 110a and the second side 110b of the first substrate <NUM>, e.g., the impurity concentrations of the first photodiode LPD and the second photodiode SPD may decrease from the first side 110a toward the second side 110b.

The area of the first pixel LPX1 may be greater than the area of the second pixel SPX1 in plane view. The area of the first photodiode LPD may be greater than the area of the second photodiode SPD in plane view.

The first floating diffusion region FD1 may be formed inside the first substrate <NUM> of the first pixel LPX1. The third floating diffusion region FD3 may be formed inside the first substrate <NUM> of the second pixel SPX1.

The first floating diffusion region FD1 and the third floating diffusion region FD3 may have the second conductive type. For example, the first floating diffusion region FD1 and the third floating diffusion region FD3 may be formed by ion-implantation of n-type impurities into the p-type first substrate <NUM>.

Each of the first floating diffusion region FD1 and the third floating diffusion region FD3 may have the second conductive type at an impurity concentration higher than those of each of the first photodiode LPD and the second photodiode SPD. For example, the first floating diffusion region FD1 and the third floating diffusion region FD3 may be formed by ion-implantation of n-type impurities of a high concentration (n+) into the p-type first substrate <NUM>.

The first transfer transistor LTX and the second transfer transistor STX may be formed on the first side 110a of the first substrate <NUM>. The first transfer transistor LTX may include the first transfer gate LTG, a first gate insulating film, and a first gate spacer. The first gate insulating film may be disposed between the first transfer gate LTG and the first substrate <NUM>. The first gate spacer may be disposed on both side walls of the first transfer gate LTG. The second transfer transistor STX may include the second transfer gate STG, a second gate insulating film, and a second gate spacer. The second gate insulating film may be disposed between the second transfer gate STG and the first substrate <NUM>. The second gate spacer may be disposed on both side walls of the second transfer gate STG. The first transfer gate LTG and the second transfer gate STG may be vertical transfer gates, and at least a part of the gates of the first transfer gate LTG and the second transfer gate STG may be embedded in the first substrate <NUM>. For example, a trench extending from the first side 100a of the first substrate <NUM> may be formed in the first substrate <NUM>, and at least a part of the gates of the first transfer gate LTG and the second transfer gate STG may be formed to fill the trench. Therefore, lower surfaces of the first transfer gate LTG and the second transfer gate STG may be disposed inside the first substrate <NUM>. Widths of the first transfer gate LTG and the second transfer gate STG may each decrease in a direction going away from the first side 110a of the first substrate <NUM>, e.g., due to the features of the etching process for forming the trenches.

A first wiring structure IS1 may be formed on the first substrate <NUM>. The first wiring structure IS1 may be formed, e.g., on the first side 110a of the first substrate <NUM>. Further, the first wiring structure IS1 may cover, e.g., the first side 110a of the first substrate <NUM>.

The first wiring structure IS1 may be made up of one or more wirings. For example, the first wiring structure IS1 may include a first wiring insulation film <NUM>, and a plurality of first wirings <NUM>, a plurality of first contacts <NUM>, and a plurality of second contacts <NUM> inside the first wiring insulation film <NUM>. The illustrated number of layers of the wiring <NUM> and the first contacts <NUM> and the second contacts <NUM> constituting the first wiring structure IS1 and the arrangement thereof are merely an example, and may be varied.

The first wiring <NUM> may be electrically connected to the first pixel LPX1 and the second pixel SPX1. For example, the first wiring <NUM> may be connected to the first substrate <NUM> through the first contact <NUM>, and may be connected to the first transfer gate LTG of the first transfer transistor LTX or the second transfer gate STG of the second transfer transistor STX through the second contact <NUM>.

The first wiring insulation film <NUM> may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant (low-k) material having a lower dielectric constant than silicon oxide. The first wiring <NUM>, the first contact <NUM>, and the second contact <NUM> may include a conductive material, e.g., the first wiring <NUM>, the first contact <NUM>, and the second contact <NUM> may include tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or alloys thereof.

The pixel separation pattern <NUM> may be formed to surround the first pixel LPX1 and the second pixel SPX1 in plane view. The pixel separation pattern <NUM> may separate, e.g., define, the first pixel LPX1 and the second pixel SPX1. The pixel separation pattern <NUM> may be formed inside the first substrate <NUM>. The pixel separation pattern <NUM> may be formed, e.g., by being embedded in a deep trench formed by patterning the first substrate <NUM>.

Referring to <FIG>, in some example embodiments, the pixel separation pattern <NUM> may penetrate the first substrate <NUM>. For example, the pixel separation pattern <NUM> may extend from the first side 110a to the second side 110b.

A width of the pixel separation pattern <NUM> may be the same or constant in a direction going away from the first side 110a of the first substrate <NUM>. In the present specification, the meaning of term "same" includes not only completely identical but also minute differences that may occur due to process margins and the like.

Alternatively, the width of the pixel separation pattern <NUM> may decrease in a direction going away from the first side 110a of the first substrate <NUM>, e.g., due to the features of the etching process for forming the pixel separation pattern <NUM>. The process of etching the first substrate <NUM> to form the pixel separation pattern <NUM> may be performed on the first side 110a of the first substrate <NUM>.

Referring to <FIG>, in some example embodiments, the pixel separation pattern <NUM> may penetrate a part of the first substrate <NUM>, e.g., only partially penetrate. For example, the pixel separation pattern <NUM> may penetrate a part of the first substrate <NUM> from the second side 110b of the first substrate <NUM>. A bottom surface of the pixel separation pattern <NUM> may be disposed inside the first substrate <NUM>. The bottom surface of the pixel separation pattern <NUM> may be based on a third direction DR3, which is a direction from the first side 110a to the second side 110b of the first substrate <NUM>.

The pixel separation pattern <NUM> may include a conductive filling pattern <NUM> and an insulating spacer film <NUM>. The insulating spacer film <NUM> may extend along the side surfaces of the trench inside the first substrate <NUM>. The conductive filling pattern <NUM> may be disposed on the insulating spacer film <NUM> and may fill the rest of the trench. The insulating spacer film <NUM> may separate the conductive filling pattern <NUM> from the first substrate <NUM>.

Referring to <FIG>, the element separation film <NUM> may be formed inside the first substrate <NUM>. The element separation film <NUM> may be formed, e.g., by embedding an insulating material in a shallow trench formed by patterning the first substrate <NUM>. The element separation film <NUM> may be adjacent to the first side 110a of the first substrate <NUM>. For example, the element separation film <NUM> may extend from the first side 110a of the first substrate <NUM>. The element separation film <NUM> may surround the active region ACT, and may define the active region ACT.

Referring to <FIG> and <FIG>, the source follower gate SF, the selection gate SEL, the first switch gate SW, the first transfer gate LTG, the dummy gate DTG, the first floating diffusion region FD1, the reset gate RG, and the connecting gate DRG may be formed on the active region ACT inside the first pixel LPX1. The second switch gate TSW, the second transfer gate STG, and the third floating diffusion region FD3 may be formed on the active region ACT inside the second pixel SPX1.

Referring to <FIG>, a width of the element separation film <NUM> may decrease in a direction going away from the first side 110a of the first substrate <NUM>. This may be due to the features of the process of etching the element separation film <NUM>. For example, the process of etching the first substrate <NUM> to form the element separation film <NUM> may be performed on the first side 110a of the first substrate <NUM>. In another implementation, the width of the element separation film <NUM> may be constant in the direction going away from the first side 110a of the first substrate <NUM>.

The element separation film <NUM> may overlap the pixel separation pattern <NUM>. A part of the pixel separation pattern <NUM> may be formed inside the element separation film <NUM>. The pixel separation pattern <NUM> may penetrate the element separation film <NUM>.

The element separation film <NUM> may include an insulating material. The element separation film <NUM> may include, e.g., at least one of silicon nitride, silicon oxide, and silicon oxynitride.

The surface insulating film <NUM> may be formed on the second side 110b of the first substrate <NUM>. The surface insulating film <NUM> may cover the second side 110b of the first substrate <NUM>.

The surface insulating film <NUM> may include an insulating material. For example, the surface insulating film <NUM> may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and a combination thereof. Also, in some embodiments, the surface insulating film <NUM> may be formed of a multi-film. For example, the surface insulating film <NUM> may include an aluminum oxide film, a hafnium oxide film, a silicon oxide film, a silicon nitride film, and a hafnium oxide film which are sequentially stacked on the first side 110a of the first substrate <NUM>.

The surface insulating film <NUM> may function as an antireflection film to prevent reflection of the light that is incident on the first substrate <NUM>, thereby improving the light-receiving rate of the photodiode <NUM>. Further, the surface insulating film <NUM> may function as a flattening film to form a color filter <NUM> and a microlens <NUM>, which will be described below, at a uniform height.

The color filter <NUM> may be formed on the surface insulating film <NUM>. The color filter <NUM> may be arranged to correspond to each of the first pixel LPX1 and the second pixel SPX1. For example, the plurality of color filters <NUM> may be arranged two-dimensionally (for example, in the form of a matrix) in a plane including the first direction X and the second direction Y. The color filter <NUM> may have various color filters depending on the pixel groups (PG1, PG2, PG3, and PG4 of <FIG>).

The grid pattern <NUM> may be formed between the color filters <NUM>. The grid pattern <NUM> may be formed on the surface insulating film <NUM>. The grid pattern <NUM> is formed in a grid pattern in plane view and may be interposed between the color filters <NUM>.

The grid pattern <NUM> may include a conductive pattern <NUM> and a low refractive index pattern <NUM>. The conductive pattern <NUM> and the low refractive index pattern <NUM> may be sequentially stacked on, e.g., the surface insulating film <NUM> such that the conductive pattern <NUM> is between the low refractive index pattern <NUM> and the surface insulating film <NUM>.

The conductive pattern <NUM> may include a conductive material, e.g., at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and a combination thereof. The conductive pattern <NUM> may prevent electric charges generated by electrostatic discharge (ESD) or the like from accumulating on the surface of the first substrate <NUM> (for example, the first side 110a) to effectively prevent an ESD bruise defect.

The low refractive index pattern <NUM> may include a low refractive index material having a lower refractive index than silicon (Si) (e.g. as measured at a corresponding frequency of light, such as visible light), e.g., at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. The low refractive index pattern <NUM> may improve the light collection efficiency by refracting or reflecting the obliquely incident light, and may improve the quality of the image sensor.

The first protective film <NUM> may be formed on the surface insulating film <NUM> and the grid pattern <NUM>. For example, the first protective film <NUM> may conformally extend along the profiles of the upper surface of the surface insulating film <NUM>, and the side surface and the upper surface of the grid pattern <NUM>, interposed between the upper surface of the surface insulating film <NUM> and the side surface and the upper surface of the grid pattern <NUM> and the color filter <NUM>.

The first protective film <NUM> may include, e.g., aluminum oxide. The first protective film <NUM> may prevent damage to the surface insulating film <NUM> and the grid pattern <NUM>.

The microlens <NUM> may be formed on the color filter <NUM>. The microlens <NUM> may have a convex shape and may have a predetermined radius of curvature, and may collect the light incident on the first photodiode LPD and the second photodiode SPD. The microlens <NUM> may include, e.g., a light transmissive resin.

A plurality of microlenses <NUM> may be arranged two-dimensionally (for example, in the form of a matrix) in a plane including the first direction X and the second direction Y. One microlens <NUM> may be arranged to correspond to each of the first pixel LPX1 and the second pixel SPX1. Specifically, referring to <FIG>, a first microlens ML1 may be arranged to correspond to each of the first pixels LPX1, LPX2, LPX3, and LPX4, and a second microlens ML2 may be arranged to correspond to each of the second pixels SPX1, SPX2, SPX3, and SPX4. The first microlens ML1 may have a polygonal shape and the second microlens ML2 may have a nearly circular shape in plane view. The first microlens ML1 may have an "∧" or notched shape (e.g. an "L" shape) in plane view.

Referring to <FIG> and <FIG>, the second protective film <NUM> may be formed on the microlens <NUM>. The second protective film <NUM> may extend along the surface of the microlens <NUM>. The second protective film <NUM> may include, e.g., an inorganic oxide film. For example, the second protective film <NUM> may include at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and combinations thereof. The second protective film <NUM> may include a low temperature oxide (LTO).

The second protective film <NUM> may protect the microlens <NUM> from the outside. For example, the second protective film <NUM> may protect the microlens <NUM> including an organic material by including an inorganic oxide film. Further, the second protective film <NUM> may improve the quality of the image sensor by improving the light collection efficiency of the microlens <NUM>. For example, the second protective film <NUM> may reduce reflection, refraction, scattering, and the like of incident light that reaches the space between the microlenses <NUM> by filling the space between the microlenses <NUM>.

<FIG> is a diagram for explaining the microlens according to some example embodiments. For convenience of explanation, points different from those described using <FIG> will be mainly described.

Referring to <FIG>, according to some example embodiments, for each of the first pixels LPX1, LPX2, LPX3, and LPX4, a plurality of first microlenses ML1 may be provided, whereas, for each of the second pixels SPX1, SPX2, SPX3, and SPX4, a respective second microlens ML2 may be provided. That is, a plurality of first microlenses ML1 may be disposed on each of the first pixels LPX1, LPX2, LPX3, and LPX4, and one first second microlens ML2 may be disposed on each of the second pixels SPX1, SPX2, SPX3, and SPX4.

In plane view, the first microlens ML1 and the second microlens ML2 may have a nearly circular shape. In plane view, the area of each first microlens ML1 may be the same as or greater than that of each second microlens ML2.

<FIG> and <FIG> are diagrams for explaining the first pixel group of <FIG> according to some example embodiments. <FIG> is an example circuit diagram for explaining a first pixel and a second pixel of <FIG>.

For convenience of explanation, points different from those described using <FIG> will be mainly described.

Referring to <FIG>, a first pixel group PG1-<NUM>' according to some example embodiments may have a rectangular shape, e.g., overall, and the second region REG2 may have a rhombic (e.g. diamond) shape in plane view. The second pixels SPX1, SPX2, SPX3, and SPX4 may each have a triangular shape in plane view.

Referring to <FIG>, according to an embodiment according to the claimed invention, each of the first pixels LPX1, LPX2, LPX3, and LPX4 arranged in <NUM>*<NUM> in the first pixel group PG1 (e.g., PG1-<NUM> in <FIG>, PG1-<NUM> in <FIG>, and PG1-<NUM> in <FIG>) includes a plurality of sub-pixels SLPX. Each sub-pixel SLPX includes a first photodiode LPD, a first floating diffusion region FD1, and a first transfer transistor LTX between the first photodiode LPD and the first floating diffusion region FD1. The is, the first subpixels SLPX may be connected to the first floating diffusion region FD1, parallel to each other.

Referring to <FIG> and <FIG>, according to an embodiment according to the claimed invention, each of the first pixels LPX1, LPX2, LPX3, and LPX4 in the first pixel group PG1-<NUM> may include three sub-pixels SLPX. The sub-pixel SLPX may be the same as each of the second pixels SPX1, SPX2, SPX3, and SPX4. That is, the first photodiode LPD may be the same as the second photodiode SPD. In plane view, the area of one first photodiode LPD may be the same as the area of one second photodiode SPD.

For example, referring to the first pixel LPX1 and the second pixel SPX1, a part of the sub-pixels SLPX arranged in <NUM>*<NUM> and each including the first photodiode LPD may be the second pixel SPX1, and the rest may be the first pixel LPX1 (that is, three first subpixels SLPX and one second pixel SPX1 may be in a <NUM>*<NUM> arrangement). For example, the second pixel SPX1 may include one second photodiode SPD, and the first pixel LPX1 may include three first photodiodes LPD. In an implementation, the second pixel SPX1 may include one first photodiode LPD, and the first pixel LPX1 may include three first photodiodes LPD. Although the sizes of the sub-pixel SLPX and the second pixel SPX1 are shown to be different in the drawing, this is only for distinguishing the first pixel LPX1 and the second pixel SPX1 from each other, and the sub-pixel SLPX and the second pixel SPX1 may have the same size.

Referring to <FIG>, according to some example embodiments, each of the first pixels LPX1, LPX2, LPX3, and LPX4 arranged in <NUM>*<NUM> in the first pixel group PG1-<NUM> may include eight sub-pixels SLPX. The sub-pixel SLPX may be the same as each of the second pixels SPX1, SPX2, SPX3, and SPX4. That is, the first photodiode LPD may be the same as the second photodiode SPD. In plane view, the area of one first photodiode LPD may be the same as the area of one second photodiode SPD.

For example, referring to the first pixel LPX1 and the second pixel SPX1, a part of the sub-pixels SLPX which are arranged in <NUM>*<NUM> and each include the first photodiode LPD may be the second pixel SPX1, and the rest may be the first pixel LPX1. For example, the second pixel SPX1 may include one second photodiode SPD, and the first pixel LPX1 may include eight first photodiodes LPD. In an implementation, the second pixel SPX1 may include one first photodiode LPD, and the first pixel LPX1 may include eight first photodiodes LPD. The ratio of the sub-pixel SLPX that is the second pixel SPX1 among the sub-pixels SLPX arranged in <NUM>*<NUM> may vary.

Referring to <FIG>, according to some example embodiments, each of the first pixels LPX1, LPX2, LPX3, and LPX4 arranged in <NUM>*<NUM> in the first pixel groups PG1-<NUM> may include fifteen sub-pixels SLPX. The sub-pixel SLPX may be the same as each of the second pixels SPX1, SPX2, SPX3, and SPX4. The first photodiode LPD may be the same as the second photodiode SPD. In plane view, the area of one first photodiode SPD may be the same as the area of one second photodiode SPD.

For example, referring to the first pixel LPX1 and the second pixel SPX1, a part of the sub-pixels SLPX which are arranged in <NUM>*<NUM> and each include the first photodiode LPD may be the second pixel SPX1, and the rest may be the first pixel LPX1. For example, the second pixel SPX1 may include one second photodiode SPD, and the first pixel LPX1 may include fifteen first photodiodes LPD. In an implementation, the second pixel SPX1 may include one first photodiode LPD, and the first pixel LPX1 may include fifteen first photodiodes LPD. The ratio of the second pixel SPX1 among the sub-pixels SLPX arranged in <NUM>*<NUM> may vary.

<FIG> is a diagram for explaining the pixel array according to some example embodiments. For convenience of explanation, points different from those described using <FIG> will be mainly described.

Referring to <FIG>, a pixel array PA-<NUM> according to some example embodiments may include a plurality of pixel groups PG1, PG2, PG3, and PG4. A color filter having the same color may be disposed on each of the pixel groups PG1, PG2, PG3, and PG4. For example, the color filter disposed on the first pixel group PG1 may have a blue color, the color filter disposed on the second and third pixel groups PG2 and PG3 may have a green color, and a color filter disposed on the fourth pixel group PG4 may have a red color. This is merely an example, and the color filter may include a yellow filter, a magenta filter, and a cyan filter, and may further include a white filter.

<FIG> is a diagram for explaining the first pixel group of <FIG>. <FIG> and <FIG> are example circuit diagrams for explaining the first pixel group of <FIG>. <FIG> and <FIG> are example layout diagrams for explaining the first pixel group of <FIG>.

Referring to <FIG>, in a first pixel group PG1-<NUM> according to some example embodiments, the first region REG1 may include first pixels LPX1, LPX2, LPX3, and LPX4 arranged in m*n (m and n are natural numbers of <NUM> or more), and the second region REG2 may include one second pixel SPX. The first region REG may include, e.g., the first pixels LPX1, LPX2, LPX3, and LPX4 arranged in <NUM>*<NUM>.

In plane view, the first region REG1 may surround the second region REG2. In plane view, the first pixel group PG1-<NUM> may have a rectangular shape, and the second region REG2 may have a rhombic (e.g. diamond) shape. In plane view, the second pixel SPX may have a rhombic (e.g. diamond) shape.

In plane view, the area of the first region REG1 may be greater than the area of the second region REG2. In plane view, the total area of the first photodiodes included in the first region REG1 may be greater than the total area of the second photodiode included in the second region REG2.

Referring to <FIG>, in the first pixel group PG1-<NUM> according to some example embodiments, the first-<NUM> to first-<NUM> pixels LPX1, LPX2, LPX3, and LPX4 (e.g. the first to fourth first pixels) may share the second pixel SPX. The first-<NUM> to first-<NUM> pixels LPX1, LPX2, LPX3, and LPX4 (e.g. the first to fourth first pixels) may each include first-<NUM> to first-<NUM> photodiodes LPD1, LPD2, LPD3, and LPD4 (e.g. first to fourth first photodiodes), and first-<NUM> to first-<NUM> floating diffusion regions FD11, FD12, FD13, and FD14 (e.g. the first to fourth first floating diffusion regions).

The first-<NUM> pixel LPX1 (e.g. the first first pixel) may include the grounded region GND, the first-<NUM> photodiode LPD1 (e.g. the first first photodiode), a first-<NUM> transfer transistor LTX1 (e.g. a first first transfer transistor), a first source follower transistor SX1, a first selection transistor AX1, a first connecting transistor DRX1, a first reset transistor RX1, and a first switch transistor SWX1. The first-<NUM> pixel LPX2 may include the grounded region GND, the first-<NUM> photodiode LPD2 (e.g. the second first photodiode), a first-<NUM> transfer transistor LTX2 (e.g. a second first transfer transistor), a second source follower transistor SX2, a second selection transistor AX2, a second connecting transistor DRX2, a second reset transistor RX2, and a second switch transistor SWX2. The first-<NUM> pixel LPX3 (e.g. the third first pixel) may include the grounded region GND, the first-<NUM> photodiode LPD3 (e.g. the third first photodiode), a first-<NUM> transfer transistor LTX3 (e.g. a third first transfer transistor), a third source follower transistor SX3, a third selection transistor AX3, a third connecting transistor DRX3, a third reset transistor RX3, and a third switch transistor SWX3. The first-<NUM> pixel LPX4 (e.g. the fourth first pixel) may include the grounded region GND, the first-<NUM> photodiode LPD4 (e.g. the fourth first photodiode), a first-<NUM> transfer transistor LTX4 (e.g. a fourth first transfer transistor), a fourth source follower transistor SX4, a fourth selection transistor AX4, a fourth connecting transistor DRX4, a fourth reset transistor RX4, and a fourth switch transistor SWX4. The second pixel SPX2 may include the grounded region GND, the second switch transistor TSWX, the second photodiode SPD, and the second transfer transistor STX.

The first connecting transistor DRX1 may connect the first-<NUM> floating diffusion region (e.g. the first first floating diffusion region) FD11 and the third floating diffusion region FD3. The second connecting transistor DRX2 may connect the first-<NUM> floating diffusion region FD12 (e.g. the second first floating diffusion region) and the third floating diffusion region FD3. The third connecting transistor DRX3 may connect the first-<NUM> floating diffusion region FD13 (e.g. the third first floating diffusion region) and the third floating diffusion region FD3. The fourth connecting transistor DRX4 may connect the first-<NUM> floating diffusion region FD14 (e.g. the fourth first floating diffusion region) and the third floating diffusion region FD3.

Each of the first-<NUM> pixels to the first-<NUM> pixels LPX1, LPX2, LPX3, and LPX4 may further include a dummy transistor. Referring to <FIG>, the first-<NUM> pixels to the first-<NUM> pixels LPX1, LPX2, LPX3, and LPX4 may include the first to fourth dummy gates DTG1, DTG2, DTG3, and DTG4 of the first to fourth dummy transistors, respectively.

Referring to <FIG>, <FIG>, and <FIG>, in a first pixel group PG1-<NUM>' according to some example embodiments, the first-<NUM> pixel to first-<NUM> pixels LPX1, LPX2, LPX3, and LPX4 may share the first floating diffusion region FD1. The first-<NUM> to first-<NUM> transfer transistors LTX1, LTX2, LTX3, and LTX4 may each be connected to the first floating diffusion region FD1. The first-<NUM> pixel to first-<NUM> pixels LPX1, LPX2, LPX3, and LPX4 may share the first switch transistor SWX, the reset transistor RX, the connecting transistor DRX, the source follower transistor SX, and the selection transistor AX.

Also, the first-<NUM> pixel LPX1 may include the dummy gate DTG (not shown in <FIG>), the first-<NUM> pixel LPX2 may include the reset gate RG, the first-<NUM> pixel LPX3 may include the connecting gate DRG, and the first-<NUM> pixel LPX4 may include the first switch gate SW.

<FIG> are diagrams for explaining alternative arrangements for the first pixel group of <FIG>. For convenience of explanation, points different from those described using <FIG> will be mainly described.

Referring to <FIG>, each of the first pixels LPX1, LPX2, LPX3, and LPX4 arranged in <NUM>*<NUM> may include a plurality of sub-pixels SLPX (see <FIG>).

Referring to <FIG> and <FIG>, each sub-pixel SLPX may include, e.g., the first photodiode LPD1, the first-<NUM> floating diffusion region FD11, and the first transfer transistor LTX1 between the first photodiode LPD1 and the first-<NUM> floating diffusion region FD <NUM>. In another implementation, referring to <FIG> and <FIG>, each sub-pixel SLPX may include, e.g., the first photodiode LPD1, the first floating diffusion region FD1, and the first transfer transistor LTX1 between the first photodiode LPD1 and the first floating diffusion region FD1.

Referring to <FIG>, according to some example embodiments, each of the first pixels LPX1, LPX2, LPX3, and LPX4 in the first pixel groups PG1-<NUM> may include three sub-pixels SLPX, and the second pixel SPX may include four sub-pixels SLPX, i.e., a part of the sub-pixels SLPX arranged in <NUM>*<NUM> may form a respective part of the second pixel SPX, and the rest may be the first pixel LPX1. Stated another way, the second pixel SPX may be formed from four sub-pixels SLPX adjacent to each other.

The second pixel SPX may include four second photodiodes SPD, and the first pixel LPX1 may include three first photodiodes LPD. That is, the second pixel SPX may include four first photodiodes LPD, and the first pixel LPX1 may include three first photodiodes LPD. The first photodiode LPD may be the same as the second photodiode SPD. In plane view, the area of one first photodiode SPD may be the same as the area of one second photodiode SPD.

The above description of <FIG> will now be applied to <FIG> and <FIG>.

Referring to <FIG>, according to some example embodiments, each of the first pixels LPX1, LPX2, LPX3, and LPX4 in the first pixel group PG1-<NUM> may include eight sub-pixels SLPX. The second pixel SPX may include four sub-pixels SLPX. The first photodiode LPD may be the same as the second photodiode SPD. In plane view, the area of one first photodiode SPD may be the same as the area of one second photodiode SPD.

For example, a part of the sub-pixels SLPX arranged in <NUM>*<NUM> may form a part of the second pixel SPX, and the rest may be the first pixel LPX1. The ratio of the sub-pixels SLPX provided as the second pixel SPX1 among the sub-pixels SLPX arranged in <NUM>*<NUM> may vary. The four sub-pixels SLPX adjacent to each other may be the second pixel SPX. The second pixel SPX may include four second photodiodes SPD, and the first pixel LPX1 may include eight first photodiodes LPD. That is, the second pixel SPX may include four first photodiodes LPD, and the first pixel LPX1 may include eight first photodiodes LPD. The ratio of the sub-pixel SLPX that is the second pixel SPX1 among the sub-pixels SLPX arranged in <NUM>*<NUM> may vary.

Referring to <FIG>, according to some example embodiments, each of the first pixels LPX1, LPX2, LPX3, and LPX4 in the first pixel group PG1-<NUM> may include fifteen sub-pixels SLPX. The second pixel SPX may include four sub-pixels SLPX. The first photodiode LPD may be the same as the second photodiode SPD. In plane view, the area of one first photodiode SPD may be the same as the area of one second photodiode SPD.

For example, a part of the sub-pixel SLPX arranged in <NUM>*<NUM> may form a part of the second pixel SPX, and the rest may be the first pixel LPX1. The ratio of the sub-pixel SLPX provided as the second pixel SPX1 among the sub-pixels SLPX arranged in <NUM>*<NUM> may vary. The four sub-pixels SLPX adjacent to each other may be the second pixel SPX. The second pixel SPX may include four second photodiodes SPD, and the first pixel LPX1 may include fifteen first photodiodes LPD. That is, the second pixel SPX may include four first photodiodes LPD, and the first pixel LPX1 may include fifteen first photodiodes LPD. The ratio of the second pixel SPX1 among the sub-pixels SLPX arranged in 4x4 may vary.

<FIG> is a diagram for explaining the pixel array according to some example embodiments. <FIG> is a diagram for explaining the first pixel group of <FIG>. <FIG> is an example circuit diagram for explaining the first pixel group of <FIG>. <FIG> is an example layout diagram for explaining the first pixel group of <FIG>. For convenience of explanation, points different from those described using <FIG> will be mainly described.

Referring to <FIG>, according to some example embodiments, a pixel array PA-<NUM> may include a plurality of pixel groups PG1, PG2, PG3, and PG4. A color filter having the same color may be disposed on each of the pixel groups PG1, PG2, PG3, and PG4.

Referring to <FIG>, in a first pixel group PG1-<NUM>, the first region REG1 may include one first pixel LPX, and the second region REG2 may include second pixels SPX1, SPX2, SPX3, and SPX4 arranged in m*n (m and n are natural numbers of <NUM> or more). The second region REG2 may include, e.g., the second pixels SPX1, SPX2, SPX3, and SPX4 arranged in <NUM>*<NUM>.

In plane view, the second region REG2 may be disposed on one side of the first region REG1. In plane view, the first region REG1 may have a cross shape, and the second region REG2 may have a rectangular shape. In plane view, the first region REG1 may include a central portion having a rectangular shape, a first portion protruding from the central portion in the first direction X, and a second portion protruding from the central portion in the second direction Y. In plane view, the second region REG2 may be disposed in either the first portion or the second portion.

In plane view, the area of the first region REG1 may be greater than the area of the second region REG2. In plane view, the total area of the first photodiode included in the first region REG1 may be greater than the total area of the second photodiodes included in the second region REG. In plane view, the area of the first photodiode LPD may be greater than the area of the second photodiode SPD.

Referring to <FIG>, in the first pixel group PG1-<NUM>, second-<NUM> to second-<NUM> pixels SPX1, SPX2, SPX3, and SPX4 (e.g. first to fourth second pixels) may share a first pixel LPX. The second-<NUM> to second-<NUM> pixels SPX1, SPX2, SPX3, and SPX4 may include second-<NUM> to second-<NUM> photodiodes SPD1, SPD2, SPD3, and SPD4 (e.g. first to fourth second photodiodes), respectively. The second-<NUM> to second-<NUM> pixels SPX1, SPX2, SPX3, and SPX4 may share the third floating diffusion region FD3. Second-<NUM> to second-<NUM> transfer transistors STX1, STX2, STX3, and STX4 (e.g. first to fourth second transfer transistors) may be connected to the third floating diffusion region FD3. At least two of the second pixels SPX, e.g., the second-<NUM> to second-<NUM> pixels SPX1, SPX2, SPX3, and SPX4, may share the connecting transistor DRX.

For example, the first pixel LPX may include the grounded region GND, the first photodiode LPD, the first transfer transistor LTX, the source follower transistor SX, the selection transistor AX, the connecting transistor DRX, the reset transistor RX, the first switch transistor SWX, and the second switch transistor TSWX. The second pixel SPX2 may include the grounded region GND, the second photodiode SPD, and the second transfer transistor STX.

<FIG> and <FIG> are diagrams for explaining a first pixel group of <FIG> according to some example embodiments. For convenience of explanation, points different from those described using <FIG> will be mainly described.

Referring to <FIG> and <FIG>, according to some example embodiments, the first pixel LPX may include a plurality of sub-pixels SLPX (see <FIG>).

Referring to <FIG>, <FIG> and <FIG>, each sub-pixel SLPX may include, e.g., the first photodiode LPD, the first floating diffusion region FD1, and the first transfer transistor LTX1 between the first photodiode LPD and the first floating diffusion region FD1.

Referring to <FIG>, according to some example embodiments, in a first pixel group PG1-<NUM>, the first pixel LPX may include five sub-pixels SLPX. The sub-pixels SLPX may be the same as each of the second pixels SPX1, SPX2, SPX3, and SPX4. That is, the first photodiode LPD may be the same as the second photodiode SPD. In plane view, the area of one first photodiode SPD may be the same as the area of one second photodiode SPD.

For example, a part of the sub-pixels SLPX arranged in <NUM>*<NUM> may form a part of the second pixels SPX1, SPX2, SPX3, and SPX4, and the rest may be the first pixel LPX. The four sub-pixels SLPX adjacent to each other may be the second pixels SPX1, SPX2, SPX3, and SPX4. The second pixel SPX1, SPX2, SPX3, and SPX4 may include four second photodiodes SPD, and the first pixel LPX may include five first photodiodes LPD. That is, the second pixels SPX1, SPX2, SPX3, and SPX4 may include four first photodiodes LPD, and the first pixel LPX may include five first photodiodes LPD. The ratio of the sub-pixel SLPX that is the second pixel SPX1 among the sub-pixels SLPX arranged in <NUM>*<NUM> may vary.

Referring to <FIG>, according to some example embodiments, in a first pixel group PG1-<NUM>, the first pixel LPX may include twelve sub-pixels SLPX. The sub-pixel SLPX may be the same as each of the second pixels SPX1, SPX2, SPX3, and SPX4. That is, the first photodiode LPD may be the same as the second photodiode SPD. In plane view, the area of one first photodiode SPD may be the same as the area of one second photodiode SPD.

For example, a part of the sub-pixels SLPX arranged in <NUM>*<NUM> may form a part of the second pixels SPX1, SPX2, SPX3, and SPX4, and the rest may be the first pixel LPX. The four sub-pixels SLPX adjacent to each other may be the second pixels SPX1, SPX2, SPX3, and SPX4. The second pixels SPX1, SPX2, SPX3, and SPX4 may include four second photodiodes SPD, and the first pixel LPX may include twelve first photodiodes LPD. That is, the second pixels SPX1, SPX2, SPX3, and SPX4 may include four first photodiodes LPD, and the first pixel LPX may include twelve first photodiodes LPD. The ratio of the sub-pixel SLPX that is the second pixel SPX1 among the sub-pixel SLPX arranged in <NUM>*<NUM> may vary.

<FIG> and <FIG> are diagrams showing a conceptual layout of an image sensor according to some example embodiments. Points different from those described with reference <FIG> will be mainly described.

Referring to <FIG>, according to some example embodiments, an image sensor <NUM>-<NUM> may include a first-<NUM> layer <NUM>, a first-<NUM> layer <NUM>, and a second layer <NUM>. The first-<NUM> layer <NUM> may include a first pixel array <NUM>-<NUM>, and the first-<NUM> layer <NUM> may include a second pixel array <NUM>-<NUM>. The first pixel array <NUM>-<NUM> may be a part of the pixel array <NUM> of <FIG>, and the second pixel array <NUM>-<NUM> may be the rest of the pixel array <NUM> of <FIG>.

The first pixel array <NUM>-<NUM> may include a photodiode and a transfer transistor, and the second pixel array <NUM>-<NUM> may include transistors other than the photodiode and the transfer transistor.

For example, referring to <FIG>, the first photodiode SPD, the second photodiode LPD, the first transfer transistor STX, and the second transfer transistor LTX may be disposed in the first pixel array <NUM>-<NUM>. The first switch transistor SWX, the second switch transistor TSWX, the reset transistor RX, the connecting transistor DRX, the source follower transistor SX, and the selection transistor AX may be disposed in the second pixel array <NUM>-<NUM>. For example, referring to <FIG> and <FIG>, the first-<NUM> to first-<NUM> photodiodes LPD1, LPD2, LPD3, and LPD4, the second photodiode SPD, the first-<NUM> to first-<NUM> transfer transistors LTX1, LTX2, LTX3, and LTX4, and the second transfer transistor STX may be disposed in the first pixel array <NUM>-<NUM>, and the remaining transistors may be disposed in the second pixel array <NUM>-<NUM>. Referring to <FIG>, the first photodiode LPD, the second-<NUM> to second-<NUM> photodiodes SPD1, SPD2, SPD3, and SPD4, the first transfer transistor LTX, and the second-<NUM> to the second-<NUM> transfer transistors STX1, STX2, STX3, and STX4 may be disposed in the first pixel array <NUM>-<NUM>, and the remaining transistors may be disposed in the second pixel array <NUM>-<NUM>.

Referring to <FIG>, an image sensor <NUM>-<NUM> according to some example embodiments may include a first layer <NUM>, a second layer <NUM>, and a third layer <NUM>. The first layer <NUM> may be disposed over the second layer <NUM>, and the second layer <NUM> may be disposed over the third layer <NUM>.

The third layer <NUM> may include a memory device. For example, the third layer <NUM> may include a volatile memory device such as a DRAM or SRAM. The third layer <NUM> may receive signals from the first layer <NUM> and the second layer <NUM>, and process the signals through the memory device. That is, the image sensor <NUM>-<NUM> may be a three-stack image sensor including three layers, i.e., the first layer <NUM>, the second layer <NUM>, and the third layer <NUM>.

<FIG> is an example layout diagram for explaining an image sensor according to some example embodiments. <FIG> is the schematic cross-sectional view for explaining the image sensor according to some example embodiments. For convenience of explanation, points different from those described using <FIG> will be mainly described. In <FIG>, the cross-sectional view of <FIG> is shown as an example cross-sectional view of the sensor array region SAR.

Referring to <FIG> and <FIG>, the image sensor according to some example embodiments may include a sensor array region SAR, a connecting region CR, and a pad region PR.

The sensor array region SAR may include a region corresponding to the pixel array <NUM> of <FIG>. The sensor array region SAR may include the pixel array <NUM> and a light-shielding region OB. Active pixels that receive light and generate an active signal may be arranged in the pixel array <NUM>. Optically black pixels that block light and generate an optically black signal may be disposed in the light-shielding region OB. The light-shielding region OB may be formed, e.g., along the periphery of the pixel array <NUM>. Dummy pixels (not shown) may be formed in the pixel array <NUM> adjacent to the light-shielding region OB.

The connecting region CR may be formed around the sensor array region SAR. The connecting region CR may be formed on one side of the sensor array region SAR. Wirings formed in the connecting region CR may be configured to transmit and receive electrical signals of the sensor array region SAR.

The pad region PR may be formed around the sensor array region SAR. The pad region PR may be formed to be adjacent to the edge of the image sensor. The pad region PR may be connected to an external device or the like, and configured to transmit and receive electrical signals between the image sensor and the external device.

In <FIG>, although the connecting region CR is shown to be interposed between the sensor array region SAR and the pad region PR, this is merely an example and the arrangement of the sensor array region SAR, the connecting region CR, and the pad region PR may be changed as needed.

Referring to <FIG>, the first substrate <NUM> and the first wiring structure IS1 may form the first substrate structure <NUM>. The first wiring structure IS1 may include a first wiring <NUM> in the sensor array region SAR and a second wiring <NUM> in the connecting region CR. At least a part of the second wiring <NUM> may extend from the sensor array region SAR. For example, at least a part of the second wiring <NUM> may be electrically connected to at least a part of the first wiring <NUM>.

The image sensor may include a second substrate <NUM> and a second wiring structure IS2.

The second substrate <NUM> may be bulk silicon or silicon on insulator (SOI). The second substrate <NUM> may be a silicon substrate, or may include other materials, e.g., silicon germanium, indium antimonide, lead tellurium compounds, indium arsenic, indium phosphide, gallium arsenide, or gallium antimonide. In an implementation, the second substrate <NUM> may have an epitaxial layer formed on the base substrate.

The second substrate <NUM> may include a third side 210a and a fourth side 210b that are opposite to each other. The fourth side 210b of the second substrate <NUM> may be a side that faces the first side 110a of the first substrate <NUM>.

A plurality of electronic elements may be formed on the second substrate <NUM>. For example, a transistor Tr' may be formed on the fourth side 210b of the second substrate <NUM>. The transistor Tr' may be electrically connected to the sensor array region SAR, and may transmit and receive electrical signals to and from the sensor array region SAR. For example, the transistor Tr' may form part of electronic elements that constitute the control register block <NUM>, the timing generator <NUM>, the ramp signal generator <NUM>, the row driver <NUM>, the readout circuit <NUM>, and the like of <FIG>.

The second wiring structure IS2 may be formed on the second substrate <NUM>. The second wiring structure IS2 may be formed on the fourth side 210b of the second substrate <NUM>. The second substrate <NUM> and the second wiring structure IS2 may form a second substrate structure <NUM>. The second wiring structure IS2 may be attached to the first wiring structure IS1. For example, as shown in <FIG>, the upper surface of the second wiring structure IS2 may be attached to the lower surface of the first wiring structure IS1.

The second wiring structure IS2 may be made up of one wiring or a plurality of wirings. For example, the second wiring structure IS2 may include a second wiring insulation film <NUM>, and plurality of wirings <NUM>, <NUM>, and <NUM> inside the second wiring insulation film <NUM>. In <FIG>, the number of layers of wiring constituting the second wiring structure IS2 and the arrangement thereof are merely example.

At least a part of the wirings <NUM>, <NUM>, and <NUM> of the second wiring structure IS2 may be connected to the transistor Tr'. The second wiring structure IS2 may include a third wiring <NUM> in the sensor array region SAR, a fourth wiring <NUM> in the connecting region CR, and a fifth wiring <NUM> in the pad region PR. The fourth wiring <NUM> may be the uppermost wiring of the plurality of wirings in the connecting region CR, and the fifth wiring <NUM> may be the uppermost wiring of the plurality of wirings in the pad region PR.

The image sensor may include a first connecting structure <NUM>, a second connecting structure <NUM>, and a third connecting structure <NUM>.

The first connecting structure <NUM> may be formed inside the light-shielding region OB. The first connecting structure <NUM> may be formed on the surface insulating film <NUM> of the light-shielding region OB. The first connecting structure <NUM> may be in contact with the pixel separation pattern <NUM>. For example, a first trench 355t that exposes the pixel separation pattern <NUM> may be formed inside the first substrate <NUM> and the surface insulating film <NUM> of the light-shielding region OB, and the first connecting structure <NUM> may be formed in the first trench 355t to be in contact with the pixel separation pattern <NUM> inside the light-shielding region OB. The first connecting structure <NUM> may extend along profiles of the side surfaces and the lower surface of the first trench 355t.

The first connecting structure <NUM> may be electrically connected to the pixel separation pattern <NUM> to apply a ground voltage or a negative voltage to the pixel separation pattern <NUM>.

The first connecting structure <NUM> may include, e.g. at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu) and a combination thereof.

A first pad <NUM> that fills the first trench 355t may be formed on the first connecting structure <NUM>. The first pad <NUM> may include, e.g. at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof.

The first protective film <NUM> may cover the first connecting structure <NUM> and the first pad <NUM>. For example, the first protective film <NUM> may extend along the profiles of the first connecting structure <NUM> and the first pad <NUM>.

The second connecting structure <NUM> may be formed inside the connecting region CR. The second connecting structure <NUM> may be formed on the surface insulating film <NUM> of the connecting region CR. The second connecting structure <NUM> may electrically connect the first substrate structure <NUM> and the second substrate structure <NUM>. For example, a second trench 455t that exposes the second wiring <NUM> and the fourth wiring <NUM> may be formed inside the first substrate structure <NUM> and the second substrate structure <NUM> of the connecting region CR, and the second connecting structure <NUM> may be formed inside the second trench 455t to connect the second wiring <NUM> and the fourth wiring <NUM>. The second connecting structure <NUM> may extend along profiles of the side surfaces and the lower surface of the second trench 455t.

The second connecting structure <NUM> may include, e.g. at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu) and a combination thereof. The second connecting structure <NUM> may be formed at the same level as the first connecting structure <NUM>.

The first protective film <NUM> may cover the second connecting structure <NUM>. For example, the first protective film <NUM> may extend along the profile of the second connecting structure <NUM>.

A first filling insulation film <NUM> that fills the second trench 455t may be formed on the second connecting structure <NUM>. The first filling insulation film <NUM> may include, e.g. at least one of silicon oxide, aluminum oxide, tantalum oxide, and a combination thereof.

A third connecting structure <NUM> may be formed inside the pad region PR. The third connecting structure <NUM> may be formed on the surface insulating film <NUM> of the pad region PR. The third connecting structure <NUM> may electrically connect the second substrate structure <NUM> to an external device or the like. For example, a third trench 550t that exposes the fifth wiring <NUM> may be formed inside the first substrate structure <NUM> and the second substrate structure <NUM> of the pad region PR, and the third connecting structure <NUM> may be formed inside the third trench 550t to contact with the fifth wiring <NUM>. Further, a fourth trench 555t may be formed inside the first substrate <NUM> of the pad region PR, and the third connecting structure <NUM> may be formed inside the fourth trench 555t and exposed. The third connecting structure <NUM> may extend along the profiles of side surfaces and lower surface of the third trench 550t and the fourth trench 555t.

The third connecting structure <NUM> may include, e.g. at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu) and a combination thereof. The third connecting structure <NUM> may be formed at the same level as the first connecting structure <NUM> and the second connecting structure <NUM>.

A second filling insulation film <NUM> that fills the third trench 550t may be formed on the third connecting structure <NUM>. The second filling insulation film <NUM> may include, e.g. at least one of silicon oxide, aluminum oxide, tantalum oxide, and a combination thereof. The second filling insulation film <NUM> may be formed at the same level as the first filling insulation film <NUM>.

A second pad <NUM> that fills the fourth trench 555t may be formed on the third connecting structure <NUM>. The second pad <NUM> may include, e.g. at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. The second pad <NUM> may be formed at the same level as the first pad <NUM>.

The first protective film <NUM> may cover the third connecting structure <NUM>. For example, the first protective film <NUM> may extend along the profile of the third connecting structure <NUM>. The first protective film <NUM> may expose the second pad <NUM>.

A light-shielding color filter 170C may be formed on the first connecting structure <NUM> and the second connecting structure <NUM>. For example, the light-shielding color filter 170C may be formed to cover a part of the first protective film <NUM> inside the light-shielding region OB and the connecting region CR. The light-shielding color filter 170C may include, e.g. a blue color filter.

The third protective film <NUM> may be formed on the light-shielding color filter 170C. For example, the third protective film <NUM> may be formed to cover a part of the first protective film <NUM> inside the light-shielding region OB, the connecting region CR, and the pad region PR. The second protective film <NUM> may extend along the surface of the third protective film <NUM>. The third protective film <NUM> may include, e.g. a light-transmitting resin. The third protective film <NUM> may include the same material as the microlens <NUM>.

The second protective film <NUM> and the third protective film <NUM> may expose the second pad <NUM>. For example, an exposure opening ER that exposes the second pad <NUM> may be formed inside the second protective film <NUM> and the third protective film <NUM>. Therefore, the second pad <NUM> may be connected to an external device or the like and configured to transmit and receive electrical signals between the image sensor according to some example embodiments and the external device. That is, the second pad <NUM> may be an input/output pad of the image sensor.

An element separation film <NUM> may be formed inside the first substrate <NUM>. For example, an element separation trench 115t may be formed inside the first substrate <NUM>. The element separation film <NUM> may be formed inside the element separation trench 115t.

In <FIG>, although the element separation film <NUM> is shown to be formed only around the second connecting structure <NUM> of the connecting region CR and around the third connecting structure <NUM> of the pad region PR, this is only an example, and the element separation film <NUM> may also be formed around the first connecting structure <NUM> of the light-shielding region OB.

<FIG> is a diagram of a vehicle including an image sensor according to some example embodiments. For convenience of explanation, repeated parts of contents of those described using <FIG> will be briefly described or omitted.

Referring to <FIG>, a vehicle <NUM> may include a plurality of electronic control units (ECU) <NUM> and a storage device <NUM>, e.g., a memory device.

Each electronic control unit of the plurality of electronic control units <NUM> may be electrically, mechanically, and communicatively connected to at least one of the plurality of devices provided in the vehicle <NUM>, and may control the operation of at least one device on the basis of any one function execution command.

The plurality of devices may include an image sensor <NUM> that acquires information used to perform at least one function, and a driving unit <NUM> that performs at least one function.

The image sensor <NUM> may be the image sensor <NUM> described referring to <FIG>. The image sensor <NUM> may be implemented as an automotive image sensor.

The driving unit <NUM> may include a fan and a compressor of an air conditioner, a fan of a ventilation device, an engine and a motor of a power device, a motor of a steering device, a motor and a valve of a brake device, an opening/closing device of a door or a tailgate, and the like.

The plurality of electronic control units <NUM> may communicate with the image sensor <NUM> and the driving unit <NUM>, e.g., using at least one of an Ethernet, a low voltage differential signaling (LVDS) communication, and a LIN (Local Interconnect Network) communication.

The plurality of electronic control units <NUM> may determine whether there is a need to perform a function on the basis of information acquired through the image sensor <NUM>. When it is determined that there is a need to perform the function, the plurality of electronic control units <NUM> may control the operation of the driving unit <NUM> that performs the function, and may control an operation on the basis of the acquired information. The plurality of electronic control units <NUM> may store the acquired information in the storage device <NUM>, or may read and use the information stored in the storage device <NUM>.

The plurality of electronic control units <NUM> may control the operation of the driving unit <NUM> that performs the function on the basis of a function execution command that is input through the input unit <NUM>, and may check a setting amount corresponding to the information that is input through the input unit <NUM> and control the operation of the driving unit <NUM> that performs the function on the basis of the checked setting amount.

Each electronic control unit <NUM> may control any one function independently, or may control any one function in cooperation with other electronic control units. For example, when a distance to an obstacle detected through a distance detection unit is within a reference distance, an electronic control unit of a collision prevention device may output a warning sound for a collision with the obstacle through a speaker.

An electronic control unit of an autonomous driving control device may receive navigation information, road image information, and distance information to obstacles in cooperation with the electronic control unit of the vehicle terminal, the electronic control unit of the image acquisition unit, and the electronic control unit of the collision prevention device, and control the power device, the brake device, and the steering device using the received information, thereby performing the autonomous driving.

A connectivity control unit (CCU) <NUM> may be electrically, mechanically, and communicatively connected to each of the plurality of electronic control units <NUM>, and may communicate with each of the plurality of electronic control units <NUM>. Thus, the connectivity control unit <NUM> may directly communicate with a plurality of electronic control units <NUM> provided inside the vehicle, may communicate with an external server, and may communicate with an external terminal through an interface.

The connectivity control unit <NUM> may communicate with the plurality of electronic control units <NUM>, and may communicate with the server <NUM>, using an antenna (not shown) and a RF communication.

The connectivity control unit <NUM> may communicate with the server <NUM> by wireless communication. The wireless communication between the connectivity control unit <NUM> and the server <NUM> may be performed through various wireless communication methods such as a GSM (global System for Mobile Communication), a CDMA (Code Division Multiple Access), a WCDMA (Wideband Code Division Multiple Access), a UMTS (universal mobile telecommunications system), a TDMA (Time Division Multiple Access), and an LTE (Long Term Evolution), in addition to a Wi-Fi module and a Wireless broadband module.

As described above, example embodiments may provide an image sensor having improved product reliability.

Various embodiments are described above in which the arrangements of a first pixel and a second pixel are explained. It will be appreciated that, where embodiments include multiple first pixels or multiple second pixels, that the descriptions of the arrangement of "the first pixel" and/or "the second pixel" may equally apply to other first pixels and/or second pixels (e.g. may apply to each first pixel or each second pixel). The same applies to first sub-pixels and second sub-pixels. Whilst some embodiments discuss multiple first sub-pixels, each having a first floating diffusion region, or multiple second sub-pixels, each having a second floating diffusion region, it will be appreciated that in one pixel region, the multiple first floating diffusion regions and/or multiple second floating diffusion regions may be connected, and therefore may all form the same floating diffusion region (e.g. the multiple first or second floating diffusion regions may be one combined first or second floating diffusion region).

Claim 1:
An image sensor (<NUM>), comprising:
a pixel group including a first region (REG1) and a second region (REG2); and
a color filter having a first color on the pixel group, wherein:
the first region (REG1) includes a plurality of first pixels (LPX1, LPX2, LPX3, LPX4) a first floating diffusion region (FD1), each of the plurality of first pixels (LPX1, LPX2, LPX3, LPX4) including a plurality of first sub-pixels (SLPX), each of the plurality of first sub-pixels (SLPX) including a first photodiode (LPD) and a first transfer transistor (LTX) connected to the first photodiode and the first floating diffusion region (FD1),
the second region (REG2) includes a plurality of second pixels (SPX1, SPX2, SPX3, SPX4) including a second photodiode (SPD), a second floating diffusion region (FD2), and a second transfer transistor (STX) connected to the second photodiode (SPD) and the second floating diffusion region (FD2),
each first pixel (LPX1, LPX2, LPX3, LPX4) further includes a connecting transistor (DRX) connecting the first floating diffusion region (FD1) and the second floating diffusion region (FD2) of one of the plurality of second pixels (SPX1, SPX2, SPX3, SPX4),
the first pixels (LPX1, LPX2, LPX3, LPX4) and the second pixels (SPX1, SPX2, SPX3, and SPX4) are each arranged in an m*n arrangement, wherein m and n are natural numbers of <NUM> or more, such that at least four first pixels (LPX1, LPX2, LPX3, LPX4) are in the first region (REG1) and at least four second pixels (SPX1, SPX2, SPX3, SPX4) are in the second region (REG2),
in plane view, a total first photodiode area in the first region (REG1) is greater than a total second photodiode area in the second region (REG2).