Patent Description:
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile flash memory cells.

<FIG> illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows, and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning. Typically, neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses.

One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e. a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses required.

Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in <CIT>, published as <CIT>. The non-volatile memory arrays operate as an analog neural memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. An array of memory cells used in this manner can be referred to as a vector by matrix multiplication (VMM) array.

Each non-volatile memory cells used in the analog neural memory system must be erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, in the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>.

Precision and accuracy are extremely important in operations involving VMM arrays, as each individual memory cell can store one of N different levels, where N can be greater than <NUM>, as opposed to a traditional memory cell where N is always <NUM>. This makes testing an extremely important operation. For example, verification of a programming operation is required to ensure that each individual cell or a column of cells is accurately programmed to the desired value. As another example, it is critical to identify bad cells or groups of cells so that they can be removed from the set of cells used to store data during operation of the VMM array.

What is needed are improved testing circuits and methods for use with VMM arrays.

<CIT> discloses that techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed. <CIT> discloses a method for massive parallel stress testing of resistive type memories.

<CIT> discloses a method for operating a data storage device including obtaining test data from a target region of a memory block by applying a test bias simultaneously to all word lines of the memory block; and estimating a state of the memory block based on the test data.

The present invention is defined in appended independent method claim <NUM> to which reference should be made.

Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile flash memory cells. The testing circuitry and methods can be utilized during sort tests, cycling tests, high temperature operating life (HTOL) tests, qualification tests, and other tests and to verify the characteristics and operability of one or more cells.

One embodiment comprises a method of verifying values programmed into a plurality of non-volatile memory cells in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, a bit line in the array; sensing, by a sense amplifier, a current received from the bit line; and comparing the current to a reference current to determine if the non-volatile memory cells coupled to the bit line contain the desired values.

Another embodiment comprises a method of measuring current drawn by a plurality of non-volatile memory cells in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, a bit line in the array; and measuring a current received from the bit line.

Another method comprises a method of testing a plurality of analog neural non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on all non-volatile memory cells in the array; and measuring a total current received from the bit lines.

Another embodiment comprises a method of testing an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising: programming a plurality of cells coupled to a bitline; measuring, K different times, a current drawn by the plurality of cells and storing a measured value each of the K different times, where K is an integer; calculating an average value based on the K measured values; and identifying the bitline as a bad bitline if any of the K measured values is less than the average value by more than a first threshold or is more than the average value by more than a second threshold.

Another embodiment comprises a method of testing an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising: programming a plurality of cells coupled to a bitline; measuring, K different times, a voltage on a control gate line coupled to a control gate terminal of a plurality of cells and storing a measured value each of the K different times, where K is an integer; calculating an average value based on the K measured values; and identifying the bitline as a bad bitline if any of the K measured values is less than the average value by more than a first threshold or is more than the average value by more than a second threshold.

Another embodiment comprises a method of testing an analog neural non-volatile memory cell for storing N different values, where N is an integer, the method comprising: programming the cell to a target value representing one of the N values; verifying that the value stored in the cell is within an acceptable window of values around the target value; repeating the programming and reading steps for each of the N values; and identifying the cell as bad if any of the verifying steps indicates a value stored in the cell outside of the acceptable window of values around the target value.

Another embodiment comprises a method of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising: measuring leakage for a column of non-volatile memory cells coupled to a bitline; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of non-volatile memory cells to compensate for the leakage.

Another embodiment comprises a method of testing a selected non-volatile memory cell in an array of analog neural non-volatile memory cells, the method comprising: determining a logarithmic slope factor for the selected non-volatile memory cell while the selected non-volatile memory cell is operating in a sub-threshold region; storing the logarithmic slope factor; determining a linear slope factor for the selected non-volatile memory cell while the selected non-volatile memory cell is operating in a linear region; storing the linear slope factor; and utilizing one or more of the logarithmic slope factor and the linear slope factor when programming the selected cell to a target current.

Another embodiment comprises a method of measuring current drawn by a column of non-volatile memory cells in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, a bit line in the array to select a column of non-volatile memory cells; and measuring a current received from the bit line.

Another embodiment comprises a method of testing an array of analog neural non-volatile memory cells, the method comprising: erasing the non-volatile memory cells in the array by applying a sequence of voltages on a terminal of each of the non-volatile memory cells in the array, wherein the voltages in the sequence of voltages increase over time in a fixed step size; and reading all of the non-volatile memory cells to determine the effectiveness of the erasing step.

Another embodiment comprises a method of testing an array of analog neural non-volatile memory cells, the method comprising: programming the non-volatile memory cells in the array by applying a sequence of voltages on a terminal of each non-volatile memory cell in the array, wherein the voltages in the sequence of voltages increase over time in a fixed step size; and reading all of the non-volatile memory cells to determine the effectiveness of the programming step.

Another embodiment comprises a method of testing a plurality of analog neural non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: programming a plurality of the non-volatile memory cells to store one of N different values, where N is the number of different levels that can be stored in any of the non-volatile memory cells; measuring a current drawn by the plurality of non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of the non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold.

Another embodiment comprises a method of testing a plurality of analog neural non-volatile memory cells in an array of non-volatile memory cells, wherein the memory array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: programming a first selection of cells among the plurality of non-volatile memory cells with a level corresponding to the smallest cell current among the N levels; programming a second selection of cells among the plurality of non-volatile memory cells with a level corresponding to the largest cell current among the N levels, wherein each of the cells in the second selection of cells is adjacent to one or more of the cells in the first selection of cells; measuring a current drawn by the plurality of non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of the non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold.

Digital non-volatile memories are well known. For example, <CIT> ("the '<NUM> patent") discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell <NUM> is shown in <FIG>. Each memory cell <NUM> includes source region <NUM> and drain region <NUM> formed in semiconductor substrate <NUM>, with channel region <NUM> there between. Floating gate <NUM> is formed over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM>, and over a portion of the source region <NUM>. Word line terminal <NUM> (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>, and a second portion that extends up and over the floating gate <NUM>. The floating gate <NUM> and word line terminal <NUM> are insulated from the substrate <NUM> by a gate oxide. Bitline terminal <NUM> is coupled to drain region <NUM>.

Memory cell <NUM> is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal <NUM>, and a positive voltage on the source region <NUM>. Electron current will flow from the source region <NUM> (source line terminal) towards the drain region <NUM>. The electrons will accelerate and become heated when they reach the gap between the word line terminal <NUM> and the floating gate <NUM>. Some of the heated electrons will be injected through the gate oxide onto the floating gate <NUM> due to the attractive electrostatic force from the floating gate <NUM>.

"Read <NUM>" is a read mode in which the cell current is output on the bit line. "Read <NUM>" is a read mode in which the cell current is output on the source line terminal.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> with the addition of control gate (CG) terminal <NUM>. Control gate terminal <NUM> is biased at a high voltage, e.g., 10V, in programming, low or negative in erase, e.g., 0v/-8V, low or mid range in read, e.g., 0v/<NUM>. Other terminals are biased similarly to that of <FIG>.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> except that memory cell <NUM> does not contain an erase gate EG terminal. An erase is performed by biasing the substrate <NUM> to a high voltage and biasing the control gate CG terminal <NUM> to a low or negative voltage. Alternatively, an erase is performed by biasing word line terminal <NUM> to a positive voltage and biasing control gate terminal <NUM> to a negative voltage. Programming and reading is similar to that of <FIG>.

<FIG> depicts a three-gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is identical to the memory cell <NUM> of <FIG> except that memory cell <NUM> does not have a separate control gate terminal. The erase operation (whereby erasing occurs through use of the erase gate terminal) and read operation are similar to that of the <FIG> except there is no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage must be applied on the source line terminal during a program operation to compensate for a lack of control gate bias.

<FIG> depicts stacked gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is similar to memory cell <NUM> of <FIG>, except that floating gate <NUM> extends over the entire channel region <NUM>, and control gate terminal <NUM> (which here will be coupled to a word line) extends over floating gate <NUM>, separated by an insulating layer (not shown). The erase, programming, and read operations operate in a similar manner to that described previously for memory cell <NUM>.

"Read <NUM>" is a read mode in which the cell current is output on the bit line. "Read <NUM>" is a read mode in which the cell current is output on the source line terminal. Optionally, in arrays comprising rows and columns of memory cells <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>, source lines can be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, source line terminals can be shared by adjacent rows of memory cells.

The methods and means described herein may apply to other non-volatile memory technologies such as SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), OTP (bi-level or multi-level one time programmable), and CeRAM (correlated electron ram), without limitation. The methods and means described herein may apply to volatile memory technologies used for neural network such as SRAM, DRAM, and volatile synapse cell, without limitation.

S0 is the input layer, which for this example is a 32x32 pixel RGB image with <NUM> bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being <NUM> bit precision). The synapses CB1 going from input layer S0 to layer C1 apply different sets of weights in some instances and shared weights in other instances, and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by <NUM> pixel (or more than <NUM> pixel as dictated by the model). Specifically, values for <NUM> pixels in a 3x3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, where these <NUM> input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the layers of feature map C1. The 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the <NUM> pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of C1, until all the features maps of layer C1 have been calculated.

<FIG> is a block diagram of a system that can be used for that purpose. Vector-by-matrix multiplication (VMM) system <NUM> includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in <FIG>) between one layer and the next layer. Specifically, VMM system <NUM> includes VMM array <NUM> comprising non-volatile memory cells arranged in rows and columns, erase gate and word line gate decoder <NUM>, control gate decoder <NUM>, bit line decoder <NUM> and source line decoder <NUM>, which decode the respective inputs for the non-volatile memory cell array <NUM>. Input to VMM array <NUM> can be from the erase gate and wordline gate decoder <NUM> or from the control gate decoder <NUM>. Source line decoder <NUM> in this example also decodes the output of VMM array <NUM>. Alternatively, bit line decoder <NUM> can decode the output of VMM array <NUM>.

VMM array <NUM> serves two purposes. First, it stores the weights that will be used by the VMM system <NUM>. Second, VMM array <NUM> effectively multiplies the inputs by the weights stored in VMM array <NUM> and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, VMM array <NUM> negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.

The output of VMM array <NUM> is supplied to a differential summer (such as a summing op-amp or a summing current mirror) <NUM>, which sums up the outputs of VMM array <NUM> to create a single value for that convolution. The differential summer <NUM> is arranged to perform summation of both positive weight and negative weight inputs to output the single value.

The summed up output values of differential summer <NUM> are then supplied to an activation function circuit <NUM>, which rectifies the output. The activation function circuit <NUM> may provide sigmoid, tanh, ReLU functions, or any other non-linear function. The rectified output values of activation function circuit <NUM> become an element of a feature map of the next layer (e.g. C1 in <FIG>), and are then applied to the next synapse to produce the next feature map layer or final layer. Therefore, in this example, VMM array <NUM> constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summer <NUM> and activation function circuit <NUM> constitute a plurality of neurons.

The input to VMM system <NUM> in <FIG> (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, digital pulses (in which case a pulses-to-analog converter PAC may be needed to convert pulses to the appropriate input analog level) or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level, binary level, digital pulses, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).

The output generated by input VMM system 32a is provided as an input to the next VMM system (hidden level <NUM>) 32b, which in turn generates an output that is provided as an input to the next VMM system (hidden level <NUM>) 32c, and so on. The various layers of VMM system <NUM> function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be a stand-alone, physical system comprising a respective non-volatile memory array, or multiple VMM systems could utilize different portions of the same physical non-volatile memory array, or multiple VMM systems could utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time multiplexed for various portion of its array or neurons. The example shown in <FIG> contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e). One of ordinary skill in the art will appreciate that this is merely exemplary and that a system instead could comprise more than two hidden layers and more than two fully connected layers.

The non-volatile reference memory cells and the non-volatile memory cells described herein are biased in weak inversion: <MAT> where <MAT> where Ids is the drain to source current; Vg is gate voltage on the memory cell; Vth is threshold voltage of the memory cell; Vt is thermal voltage = k*T/q with k being the Boltzmann constant, T the temperature in Kelvin, and q the electronic charge; n is a slope factor = <NUM> + (Cdep/Cox) with Cdep = capacitance of the depletion layer, and Cox capacitance of the gate oxide layer; Io is the memory cell current at gate voltage equal to threshold voltage, Io is proportional to (Wt/L)*u*Cox* (n-<NUM>) * Vt<NUM> where u is carrier mobility and Wt and L are width and length, respectively, of the memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current Ids, into an input voltage, Vg: <MAT>
Here, wp is w of a reference or peripheral memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current Ids, into an input voltage, Vg: <MAT>.

Here, wp is w of a reference or peripheral memory cell.

For a memory array used as a vector matrix multiplier VMM array, the output current is: <MAT> namely <MAT> <MAT> <MAT>
Here, wa = w of each memory cell in the memory array.

Alternatively, the non-volatile memory cells of VMM arrays described herein can be configured to operate in the linear region:.

Alternatively, the memory cells of VMM arrays described herein can be configured to operate in the saturation region:.

Alternatively, the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation).

Other embodiments for VMM array <NUM> of <FIG> are described in <CIT>. As described in that application, a sourceline or a bitline can be used as the neuron output (current summation output).

VMM array <NUM> implements uni-directional tuning for non-volatile memory cells in memory array <NUM>. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be performed, for example, using the precision programming techniques described below. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell must be erased and the sequence of partial programming operations must start over. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (which is known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

In VMM array <NUM>, the inputs INPUT<NUM>. , INPUTN are received on bit lines BL<NUM>,. BLN, respectively, and the outputs OUTPUT<NUM>, OUTPUT<NUM>, OUTPUT<NUM>, and OUTPUT<NUM> are generated on source lines SL<NUM>, SL<NUM>, SL<NUM>, and SL<NUM>, respectively.

In this example, the inputs INPUT<NUM>, INPUT<NUM>, INPUT<NUM>, and INPUT<NUM> are received on source lines SL<NUM>, SL<NUM>, SL<NUM>, and SL<NUM>, respectively, and the outputs OUTPUT<NUM>,. OUTPUTN are generated on bit lines BL<NUM>,.

In this example, the inputs INPUT<NUM>,. , INPUTM are received on word lines WL<NUM>,. , WLM, respectively, and the outputs OUTPUT<NUM>,. OUTPUTN are generated on bit lines BL<NUM>,.

In this example, the inputs INPUT<NUM>,. , INPUTn are received on vertical control gate lines CG<NUM>,. , CGN, respectively, and the outputs OUTPUT<NUM> and OUTPUT<NUM> are generated on source lines SL<NUM> and SL<NUM>.

In this example, the inputs INPUT<NUM>,. , INPUTN are received on the gates of bit line control gates <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(N-<NUM>), and <NUM>-N, respectively, which are coupled to bit lines BL<NUM>,. , BLN, respectively. Exemplary outputs OUTPUT<NUM> and OUTPUT<NUM> are generated on source lines SL<NUM> and SL<NUM>.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG>, memory cells <NUM> as shown in <FIG>, and memory cells <NUM> as shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT<NUM>,. , INPUTM are received on word lines WL<NUM>,. , WLM, and the outputs OUTPUT<NUM>,. , OUTPUTN are generated on bit lines BL<NUM>,. , BLN, respectively.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG>, memory cells <NUM> as shown in <FIG>, and memory cells <NUM> as shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT<NUM>,. , INPUTM are received on control gate lines CG<NUM>,. Outputs OUTPUT<NUM>,. , OUTPUTN are generated on vertical source lines SL<NUM>,. , SLN, respectively, where each source line SLi is coupled to the source lines of all memory cells in column i.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG>, memory cells <NUM> as shown in <FIG>, and memory cells <NUM> as shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. In this example, the inputs INPUT<NUM>,. , INPUTM are received on control gate lines CG<NUM>,. Outputs OUTPUT<NUM>,. , OUTPUTN are generated on vertical bit lines BL<NUM>,. , BLN, respectively, where each bit line BLi is coupled to the bit lines of all memory cells in column i.

<FIG> depicts VMM system <NUM>. VMM system <NUM> comprises VMM array <NUM> (which can be based on any of the VMM array designs discussed previously, such as VMM array <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> or other VMM array designs), low voltage row decoder <NUM>, high voltage row decoder <NUM>, column decoder <NUM>, column driver <NUM>, control logic <NUM>, bias circuit <NUM>, output circuit block <NUM>, input VMM circuit block <NUM>, algorithm controller <NUM>, high voltage generator block <NUM>, analog circuit block <NUM>, control logic <NUM>, and test control logic <NUM>.

Input circuit block <NUM> serves as interface from an external input to the input terminals of the memory array <NUM>. Input circuit block <NUM> can comprise a DAC (Digital-to-Analog Converter), DPC (Digital-to-Pulse Converter), APC (Analog-to-Pulse Converter), IVC (Current-to-Voltage Converter), AAC (Analog-to-Analog Converter such as voltage to voltage scaler), or FAC (Frequency-to-Analog Converter), without limitation. Output circuit block <NUM> serves as an interface from the memory array output to an external interface (not shown). Output circuit block <NUM> can comprise an ADC (Analog-to-Digital Converter), APC (Analog-to-Pulse Converter), DPC (Digital-to-Pulse Converter), IVC (Current-to-Voltage Converter), or IFC (Current-to-Frequency Converter), without limitation. Output circuit block <NUM> may include activation functions, normalization circuitry, and/or re-scaling circuitry, without limitation.

Low voltage row decoder <NUM> provides a bias voltage for read and program operations and provides a decoding signal for high voltage row decoder <NUM>. High voltage row decoder <NUM> provides a high voltage bias signal for program and erase operations.

Algorithm controller <NUM> provides a controlling function for bit lines during program, verify, and erase operations.

High voltage generator block <NUM> comprises charge pump <NUM>, charge pump regulator <NUM>, and high voltage generation circuitry <NUM> that provides the multiple voltages needed for the various program, erase, program verify, and read operations.

Test control logic <NUM> contains various test control circuits for performing the testing described below with reference to <FIG>.

<FIG> depicts reference current source <NUM> for use during verify operations following a program operation of one or more non-volatile memory cells, or for use during other types of testing. For example, reference current source <NUM> can be used for a verify operation of a single non-volatile memory cell, or for a verify operation for a column of non-volatile memory cells (e.g., all cells connected to a particular bit line) or some other grouping of non-volatile memory cells.

Reference current source <NUM> comprises buffer mirror <NUM> (which comprises buffer operation amplifier <NUM> with output IREF <NUM> and PMOS transistor <NUM>), adjustable bias source <NUM>, and two-dimensional array <NUM> comprising an array of i rows and j columns of devices <NUM>, where a particular device <NUM> is noted by the label <NUM>-(row)(column). Here, various combinations of devices <NUM> can be activated, such that the amount of reference current IREF <NUM> output by buffer mirror <NUM> can be adjusted. As shown, there are <NUM> devices <NUM> in the array <NUM>, each of which may be implemented by a current mirror. Reference current source <NUM> basically converts <NUM> digital inputs into a reference current bias with value from <NUM> to <NUM> times Ibiasunit, where Ibiasunit is provided from the bias source <NUM>. Reference current source <NUM> is basically a thermometer-coded Digital-to-Current Converter, whose buffered output IREF <NUM> is of a value that corresponds to <NUM> of <NUM> levels, the particular level responsive to the <NUM> digital inputs, that can be stored by memory cells in any of the VMM arrays discussed previously.

For example, bias source <NUM> can provide current Ibiasunit of 1nA, which is mirrored into devices <NUM>. Here, the first row consists of devices <NUM>-<NUM> to <NUM>-1j and is enabled sequentially from left to right, one device <NUM> at a time. Then the next row is enabled in a sequential manner from left to right to add to the first row, meaning <NUM> then <NUM> then <NUM> then <NUM> devices <NUM> are enabled. By sequentially enabling devices <NUM>, transistor mismatch issues associated with conventional binary decoding can be avoided. The sum of the enabled devices <NUM> is then mirrored by the buffer mirror <NUM> and output as current IREF <NUM>. The bias source <NUM> can provide a trimmable range of current Ibiasunit such as 50pA/100pA/200pA/. Array <NUM> here is shown as a 4x4 array, but it is to be understood that array <NUM> could have other dimensions, such as <NUM> x <NUM> or <NUM> x <NUM>.

<FIG> depicts reference sub-circuit <NUM>, which can be used for any of the devices <NUM> in <FIG>. Reference sub-circuit <NUM> comprises NMOS transistors <NUM> and <NUM>, configured as shown. Transistor <NUM> is a current mirror bias transistor that receives current Ibiasunit (discussed above with reference to <FIG>) on its gate, and transistor <NUM> is an enabling transistor (to enable the current mirror bias transistor <NUM> to be connected to output node OUTPUT). The current Ibiasunit is provided such as from a diode connected NMOS transistor (similar to transistor <NUM>) (not shown).

<FIG> depicts sense amplifier <NUM> to be used with reference current source <NUM> during a verify operation following a programming operation of a non-volatile memory cell, a column of non-volatile memory cells, or some other grouping of non-volatile memory cells, or during another type of testing. Sense amplifier <NUM> receives current IREF <NUM> discussed above with reference to <FIG>. IREF <NUM> can be modeled as PMOS transistor <NUM> with gate controlled by VIREF <NUM>. Sense amplifier <NUM> further comprises inverter <NUM>, current source <NUM>,which is used to limit the current in inverter <NUM>, switches <NUM> and <NUM>, capacitor <NUM>, and cascoding NMOS transistor <NUM> (to impose a fixed voltage on a memory bitline). Sense amplifier <NUM> receives current IREF <NUM> from reference current source <NUM>, which can be, for example, one of sixteen possible levels to be stored in a non-volatile memory cell of a VMM array. Sense amplifier <NUM> is coupled to cell <NUM>, which is the non-volatile memory cell whose contents is to be verified. Cell <NUM> draws current ICELL when NMOS transistor <NUM> is turned on. Alternatively, cell <NUM> can be replaced with column <NUM> (which, for convenience of the drawings, will draw a current that will still be referred to as ICELL, which would be the neuron current drawn by column <NUM>).

In one embodiment, IREF <NUM> begins at the lowest possible value (e.g., the lowest of <NUM> possible levels that can be stored in cell <NUM> or in column <NUM>) and then increases sequentially to each subsequent level for verify operation. Switch <NUM> can be closed to create an initial state for capacitor <NUM> (such as ground or a precharge voltage to provide offset cancellation). Switch <NUM> can be closed to equalize the input and output of inverter <NUM>, which removes the offset from the inverter <NUM> for comparison in the verify operation. During the verify operation, switches <NUM> and <NUM> are opened. If ICELL >= IREF <NUM>, then voltage on node <NUM> will decrease, which in turns couples capacitively through the capacitor <NUM> causing the voltage on node <NUM> to decrease, resulting in the inverter output switching to '<NUM>', meaning the input of inverter <NUM> will be a "<NUM>' value, and the output of inverter <NUM> will be a "<NUM>" value. If ICELL < IREF <NUM>, then the voltage on node <NUM> will rise, which in turns couples capacitively through the capacitor <NUM> causing the voltage on the node <NUM> to rise, resulting in the inverter output switching to a '<NUM>', meaning the input of inverter <NUM> will switch to a "<NUM>" value and the output of inverter <NUM> will switch to a "<NUM>" value. The value of IREF <NUM> at which that occurs corresponds to the value that is stored in cell <NUM>.

<FIG> depicts verification sloped analog-to-digital converter (ADC) <NUM> to be used with reference current source <NUM> during a verify operation of non-volatile memory cell <NUM> or column <NUM> following a program pulse operation, such as to verify whether the memory cell reaches a target current during a weight tuning process, or during another type of testing, such as to verify the tailed memory bits (e.g. aberrant bits) in the memory array which cannot meet the cell current requirement. ICELL <NUM> is an output current from cell <NUM> or column <NUM>. Verification ADC <NUM> converts ICELL <NUM> into a series of digital output bits that are output as output <NUM>, where output <NUM> indicates the value stored in cell <NUM> or column <NUM>.

Verification ADC <NUM> comprises op-amp <NUM>, adjustable capacitor <NUM>, op-amp <NUM>, counter <NUM>, and switches <NUM>, <NUM>, and <NUM>. Adjustable capacitor <NUM> integrates ICELL <NUM> versus a current IREF provided by an adjustable current source <NUM>. During an initialization phase, switch <NUM> is closed. Vout <NUM> of op-amp <NUM> and the input to the inverting input of operational amplifier <NUM> then will become equal to the value of the reference voltage VREF applied to the non-inverting input of op-amp <NUM>. Thereafter, switch <NUM> is opened and during a fixed time period tref, switch <NUM> is closed and the neuron current ICELL <NUM> is up-integrated. During the fixed time period tref, Vout <NUM> rises, and its slope is reflective of the value of ICELL <NUM>. Thereafter, during a period tmeas, the constant reference current IREF provided by adjustable current source <NUM> is down integrated, during which period Vout falls, by opening switch <NUM> and closing switch <NUM> where tmeas is the time required to down integrate Vout to VREF.

Output EC <NUM> of op-amp <NUM> will be high when VOUT <NUM> > VREF and will be low otherwise. EC <NUM> therefore generates a pulse whose width reflects the period tmeas, which in turn is proportional to the current ICELL <NUM>.

Optionally, output EC <NUM> is input to counter <NUM>, which counts the number of clock pulses <NUM> received while output EC2905 is high, and will generate output <NUM>, which will be a set of digital bits representing a digital count of the number of clock pulses <NUM> occurring while EC <NUM> is high, which number is directly proportional to ICELL <NUM>, which corresponds to the value stored in cell <NUM> or column <NUM>.

<FIG> depicts verification ramp analog-to-digital converter <NUM>, which comprises current source <NUM> (which represents a received neuron current, Ineu or a single memory cell current), switch <NUM>, variable capacitor <NUM>, and comparator <NUM>, which receives the voltage developed across variable capacitor <NUM>, denoted Vneu, at the non-inverting input thereof and configurable reference voltage Vreframp at the inverting input thereof and generates output Cout. A circuit to clear the voltage across variable capacitor <NUM> is not shown. Vreframp is ramped (stepped) up in discrete levels with each comparison clock cycle. Comparator <NUM> compares Vneu against Vreframp, and as a result output Cout will be "<NUM>" when Vneu>Vreframp and will be "<NUM>" otherwise. Thus, output Cout will be a pulse, whose width varies in response to the value of Ineu. A larger Ineu will cause Cout to be "<NUM>" for a longer period of time, i.e. a wider pulse for output Cout. A digital counter <NUM> converts the output Cout into digital output bits DO [n:<NUM>] <NUM>, which bits reflect the number of clock cycles <NUM> for which Cout was a "<NUM>" value. Alternatively ramp voltage Vreframp is a continuous ramp voltage. A multi-ramp embodiment can be done for reducing the conversion time by utilizing a coarse-fine ramp conversion algorithm. First coarse reference ramp reference voltage is ramped in a fast manner to figure out the sub range for each Ineu. Next, fine reference ramp reference voltages are used respectively for each sub-range for converting Ineu currents within the respective sub-range. More than two coarse/fine steps or two sub-ranges are possible.

Other ADC architecture can be used as verification ADC such as flash ADC, SAR (Successive Approximation Register) ADC, Algorithmic ADC, Pipelined ADC, Sigma Delta ADC, without limitation.

<FIG> depicts an embodiment of high voltage generation circuit <NUM> described previously with reference to <FIG>. High voltage generation circuit <NUM> can be used with any of the VMM arrays discussed previously. High voltage generation circuit <NUM> comprises charge pump <NUM> and high voltage generation circuitry <NUM>. Charge pump <NUM> receives input <NUM> and generates high voltage <NUM>, which in turn is provided to high voltage generators <NUM> and <NUM>. High voltage (HV) generator (HVDAC_EG) <NUM> is a HV Digital-to-Analog Converter that provides voltages, denoted VEG <NUM>, such as incremental voltages, suitable for application to the erase gate terminal of a split-gate flash memory cell in response to digital bits <NUM> and received high voltage <NUM>. High voltage generator (HVDAC CGSL) <NUM> is a HV Digital-to-Analog Converter that provides voltages, respectively denoted VCG <NUM> and VSL <NUM>, such as incremental voltages, suitable for application to the control gate terminal and source line terminal of a split-gate flash memory cell in response to digital bits <NUM> and received high voltage <NUM>.

<FIG> depicts VMM system <NUM> described previously with reference to <FIG>, but here shown in a testing configuration. Test control logic <NUM> provides control signals to the other components of VMM system <NUM> (shown in <FIG> but not in <FIG>), such as VMM array <NUM>, row decoder <NUM>, column decoder <NUM>, input block <NUM>, high voltage decoder <NUM>, column driver <NUM>, high voltage generation block <NUM>, analog block <NUM>, algorithm controller <NUM>, and output circuit block <NUM> to implement one or more testing algorithms <NUM>. VMM array <NUM> receives control signals from row decoder <NUM>, whereby one or more rows are asserted within VMM array <NUM>. VMM array <NUM> provides signals from one or more bit lines to column decoder <NUM>, which then provides outputs from one or more bit lines to output circuit block <NUM>. Output circuit block <NUM> can comprise an analog-to-digital converter block (such as verification ADC <NUM> described previously with reference to <FIG> or verification ramp ADC <NUM> described previously with reference to <FIG>) that provides a digital output representing the analog current received by output circuit block <NUM> from VMM array <NUM>.

Table No. <NUM> contains exemplary values to be applied to word lines, control gate lines, erase gate lines, source gate lines, and bitlines within VMM array <NUM> during program, erase, read, and verify operations performed on an individual memory cell; verify neuron and read neuron operations performed on a selected bit line coupled to a column of memory cells; and a read array operation whereby every bit line is read, where each bit line is coupled to a column of memory cells.

Further detail will now be provided on the types of tests that can be performed with reference to testing algorithms <NUM> depicted in <FIG> and described in further detail in <FIG>, which are implemented by test control logic <NUM> and other components of VMM system <NUM>.

With reference to <FIG>, bitline neural read test <NUM> measures the values in all memory cells coupled to a bitline at the same time. That is, bitline neural read test <NUM> reads a neuron in a VMM array. First, row decoder <NUM> asserts all word lines in the array (step <NUM>). Second, a bit line is selected (asserted) by column decoder <NUM> (step <NUM>). Third, a read is performed on that bit line, such as by sense amplifier <NUM> sensing a current received from the bit line (step <NUM>). Fourth, the value of selected bit line can be determined by comparison to reference currents generated by reference current source <NUM> to determine if the non-volatile memory cells, i.e. neuron, coupled to the selected bit line contains the desired value(s) (step <NUM>).

With reference to <FIG>, bitline neural measurement test <NUM> is similar to a bitline neural read test <NUM>. Row decoder <NUM> asserts all word lines (step <NUM>). A bit line is selected by column decoder <NUM> (step <NUM>). The current drawn by that bit line during a read operation is measured (step <NUM>). Here, unlike in bitline neural read test <NUM>, the current from a selected bitline is measured without comparison to reference currents.

With reference to <FIG>, during LSB screen test <NUM>, row decoder <NUM> asserts all word lines (step <NUM>), and column decoder <NUM> asserts all bit lines (step <NUM>). A deep programming is performed on all memory cells in VMM array <NUM> (step <NUM>). Deep programming will program all memory cells beyond the normal program states used for inference reading. It is done with longer program timing or higher program voltages than are normally used in operation. The total current received from all bit lines is then measured (step <NUM>). The expectation is that the total current of the deep programmed array will be much less than the LSB value. In addition, each individual cell is checked to make sure the current from the individual cell is also lower than an LSB value, such as <NUM>-<NUM> pA. This type of test is suitable for testing during the manufacturing process to quickly identify bad die.

With reference to <FIG>, during bitline sampling screen test <NUM>, a memory cell or set of memory cells are programmed to a particular level, for example, Lx, where x ranges from <NUM> to N, where N is the total number of levels that can be stored in a cell (e.g., N=<NUM>) (step <NUM>). Bitline current (meaning the current drawn by a cell or set of cells in the selected bitline, referred to as IBL) is then measured K times (step <NUM>). For example, if K=<NUM>, then the bit line current is measured <NUM> times. The average value (IAVG) is then calculated based on the K measured values of step <NUM> (i.e., IBL1. IBLK) (step <NUM>).

Next, each of the K current measurements, IBL1. IBLK, is checked against IAVG (step <NUM>). If IBLi (where i ranges from i to K) > (IAVG + threshold <NUM>) or IBLi < (IAVG - - threshold <NUM>), then the bitline is considered bad. Each cell in a bad bitline is then checked, and bad cells are replaced with redundant cells (such cells from a redundant row or redundant column).

Another embodiment of bitline sampling screen test <NUM> is depicted in <FIG>. Voltage VCG is measured by forcing the current Iref into the bitline K different times (step <NUM>). For example, the voltage VCG can be swept until the bitline current matches the fixed Iref, and that particular VCG can be measured and stored. The fixed Iref can be provided by the reference current source <NUM>, and the operation of verifying whether bitline current matches the fixed Iref can be performed by sense amplifier <NUM>. Then, the average value, VAVG, is calculated from the K different VCG values. Next, each of the K measured VCG voltages is checked against VAVG (step <NUM>). If VcG, (where i ranges from i to K) > (VAVG + threshold <NUM>) or VCGi < (VAVG - threshold <NUM>), then the bitline is considered bad. Each cell in the bad bit line is then checked, and bad cells are replaced with redundant cells (redundant row or redundant column).

During read tripoint test <NUM>, coarse and fine read reference current trimming are performed using different levels of Iref in read operation. The purpose of read trip point test <NUM> is to figure out the whether a selected memory cell can pass a predetermined current percentage target such as ~<NUM>% of fully erased cell for erased cells or ~<NUM>% of fully programmed cell for programmed cells. This is such as to ensure the memory cell is within main distribution, not tailed memory cells or tailed bits (i.e., a statistical outlier), as tailed memory cells or tailed bits can cause potential reliability issues over an operating lifetime.

With reference to <FIG>, during read window check test <NUM>, a cell is tested to ensure it is able to store each of the N possible levels. First, a cell is programmed to a target value representing one of the N values (step <NUM>). Next, a verifying operation is performed to determine if the value stored in the cell is within an acceptable window <NUM> of values around the target value (step <NUM>). Steps <NUM> and <NUM> are repeated for each of the N values (step <NUM>). The acceptable window <NUM> may be different for each N value. The cell is identified as bad if any of the instances of step <NUM> being performed indicate a value stored in the cell outside of the acceptable window of values around the target value. Read window check test <NUM> can be performed by sense amplifier <NUM>, ADC <NUM>, ADC <NUM>, or another component. This can be useful for performing weight tuning for memory cells. The above has been explained in an embodiment wherein a fixed window is used for each of the N values centered on a nominal value, it being understood that in another embodiment an upper threshold and lower threshold is utilized for each of the N values, and these thresholds need not be identical among all the N values, without exceeding the scope.

With reference to <FIG>, during read calibration test <NUM>, leakage is measured for a cell or group of cells such as cells coupled to a bit line (step <NUM>), the measured leakage (ILEAKAGE)is stored (step <NUM>), and the measured leakage value is later used during a read operation to compensate for the leakage over various combinations of process/voltage/temperature (PVT) (step <NUM>). In one embodiment, a plurality of cells are each programmed with known values. The word lines and control gate lines are set to ground, and the bit lines are set to a read bias voltage. A sequence of different reference currents are injected into the array, and the resulting data read out is read by sense amplifiers such as ADC circuits <NUM> or <NUM> or sense amplifier <NUM>. The injected current that yields the best results (compared to the known values that were programmed into the cells) is stored as ILEAKAGE. Thereafter, ILEAKAGE is applied during a read operation of the same cells, such as by subtracting the stored leakage level from conversion data during a read operation to compensate for leakage occurring within the selected cells.

With reference to <FIG>, during read slope test <NUM>, the I-V slope factor is determined for the control gate voltage against two reference currents, CG1 at current IR1 and CG2 at current IR2. The first step is determining a logarithmic slope factor for the selected non-volatile memory cell while the selected non-volatile memory cell is operating in a sub-threshold region (step <NUM>). The second step is storing the logarithmic slope factor (step <NUM>). The third step is determining a linear slope factor for the selected non-volatile memory cell while the selected non-volatile memory cell is operating in a linear region (step <NUM>). The fourth step is storing the linear slope factor (step <NUM>). The fifth step is utilizing one or more of the logarithmic slope factor and the linear slope factor when programming the selected cell to a target current (step <NUM>).

With reference to <FIG>, during read neuron qualification test <NUM>, a neuron (bit line) is read without checking the value against a desired value. The first step is measuring currents in the bitlines and storing the measured values (step <NUM>). The second step is performing the read dummy neuron test <NUM>, to be described below, for a pre-determined amount of time, such as the burn-in time during the qualification process. The third step is measuring currents from the bitlines (step <NUM>). The fourth step is comparing the measured currents to the stored measured currents from step <NUM> (step <NUM>). If the difference is more than or less than a certain amount, then the bitline is deemed to be a bad bitline.

Read dummy neuron test <NUM> comprises a series of steps. The first step is asserting, by the row decoder, all word lines in the array (step <NUM>). The second step is asserting, by the column decoder, all bit lines in the array to select all column of non-volatile memory cells (step <NUM>). The third step is performing a read operation (read condition) on the array without checking the read output (step <NUM>). The read dummy neuron test <NUM> is used as a read stress on the array for burn-in purposes.

With reference to <FIG>, during soft erase test <NUM>, the entire array or a sector is tested to check for erase performance of the memory array. The first step is erasing the non-volatile memory cells in the array by applying a sequence of voltages on a terminal of each of the non-volatile memory cells in the array, wherein the voltages in the sequence of voltages increase over time in a fixed step size (step <NUM>). This erases the cells in an incremental manner, for example, by increasing the voltage on erase gates in a stepped manner between <NUM>-<NUM> volts in steps of for example <NUM> or <NUM> volts. Erasing in this manner reduces stress on the memory cells. The second step is reading all of the non-volatile memory cells to determine the effectiveness of the erasing step (step <NUM>), for example by determining that the cell current after the erasing of step <NUM> is within an acceptable window around a nominal value. Optionally, endurance testing can be performed to determine how many program/erase cycles can be sustained, or background testing can be performed to cause the array to transition into an erased state.

With reference to <FIG>, during soft program test <NUM>, the entire array or a row or cell is tested. The first step is programming the non-volatile memory cells in the array by applying a sequence of voltages on a terminal of each non-volatile memory cell in the array, wherein the voltages in the sequence of voltages increase over time in a fixed step size (step <NUM>). The cells are programmed in an incremental manner, for example, between <NUM>-<NUM> volts in <NUM> mV or <NUM> V or <NUM> V steps to check for program performance of the memory array. Programming in this manner reduces stress on the memory cells. The second step is reading all of the non-volatile memory cells to determine the effectiveness of the programming step (step <NUM>) ), for example by determining that the cell current after the programming of step <NUM> is within an acceptable window around a nominal value. Optionally, endurance testing or background testing can be utilized.

With reference to <FIG>, read verification test <NUM> can be performed. The first step is programming a plurality of the non-volatile memory cells to store one of N different values, where N is the number of different levels that can be stored in any of the non-volatile memory cells (step <NUM>). The second step is measuring a current drawn by the plurality of non-volatile memory cells (step <NUM>). The third step is comparing the measured current to a target value (step <NUM>). The fourth step is storing the identifying the plurality of the non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold factor (step <NUM>).

With reference to <FIG>, checkerboard verification test <NUM> can be performed, whereby a test pattern is implemented using a checkerboard or pseudo-checkerboard pattern and sampled levels, rather than all possible levels, (e.g. <NUM> levels, L0, Ln, Ln/<NUM>, Ln*<NUM>/<NUM> instead of all N levels), are measured. For example, a pattern can be used to check for the worst-case electric field stress (meaning one cell is at a high electric field level and an adjacent cell is at low electric field level) within the memory array.

In one embodiment, the first step is programming a first group of cells among the plurality of non-volatile memory cells with a level corresponding to the smallest cell current among the N levels (step <NUM>). The second step is programming a second group of cells among the plurality of non-volatile memory cells with a level corresponding to the largest cell current among the N levels (step <NUM>) Each of the cells in the second group of cells is adjacent one or more of the cells in the first group of cells. The third step is measuring a current drawn by the plurality of non-volatile memory cells (step <NUM>). The fourth step is comparing the measured current to a target value (step <NUM>). The fifth step is identifying the plurality of the non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold (step <NUM>).

Table No. <NUM> contains other exemplary test patterns of a physical array map that can be used during checkerboard verification test <NUM>:.

Sort test <NUM>, final test <NUM>, qualification test <NUM>, and data retention test <NUM> are test suites that can be performed during the manufacturing and qualification process of a wafer, die, or packaged device containing a VMM system disclosed herein.

Sort test <NUM> can be performed on a wafer during the manufacturing process. In one embodiment, sort test <NUM> comprises the following test suite: First, relatively fasts tests are performed to quickly identify bad wafers or die, such as soft erase test <NUM>, soft program test <NUM>, and various stress mode tests (such as erase gate oxide gox, coupling gate oxide cox, source line oxide sol, reverse disturb tunneling rtsts (tunneling from floating gate to wordline, disturb on un-selected rows), mass punchthrough mpt (disturb from source to drain of unselected rows), read disturb rdist (disturb from read condition)). Second, neural test modes such as LSB screen test <NUM> and bitline sampling screen <NUM> for top and bottom sectors are performed. Neural testmodes are much more time consuming than the testing performed during the first step, and some time is saved due to bad wafers or die being screened identified during the first set of less time-consuming tests.

Final test <NUM> can be performed on a packaged device. In one embodiment, final test <NUM> comprises the performance of soft erase test <NUM> and soft program test <NUM>. Optionally, test patterns for neural application can be utilized to reduce test time rather than comprehensive testing, such as testing K of N levels of M sectors, or testing all N levels for certain sectors (such as the top and bottom sectors).

During qualification test <NUM>, dummy bitline read cycling (which is the performance of a read action without actually determining the content of the read data) is performed and endurance testing is done by applying soft erase test <NUM> and soft program test <NUM>. Bitline tests are performed, instead of individual memory cell tests, since bitline reads are used instead of individual memory reads during neural memory applications.

Data retention test <NUM> can comprise, for example, baking a programmed wafer at an elevated temperature such as <NUM> degrees C for <NUM>-<NUM> hours. In one embodiment, a checkerboard or pseudo-checkerboard test pattern is imposed, rather than comprehensive testing as for digital memory test. Data retention is checked on the bitline current in the neural mode (instead of each memory cell as done for a digital memory) with read bitline current mode. For example, one inquiry is to check if delta IBL < +/-p%, where delta IBL is defined as the difference of the measured bit line current from the expected bit line current. (WholeBLmeas mode, percentage error p% allowed from software neural net modeling for a target accuracy for a neural network). Delta IBL is tested for neural mode to identify if bitline output current exceeds or goes below a target, defined herein as a predetermined percentage "p" of the target. Alternatively, each cell can be checked/tested with a +/- delta of the target.

Other testing can be performed using the hardware and algorithms described herein.

Claim 1:
A method (<NUM>) of verifying values programmed into a plurality of non-volatile memory cells in a vector-by-matrix multiplication array (<NUM>) of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising:
asserting, by the row decoder in response to control signals from test control logic (<NUM>), all word lines in the array simultaneously (<NUM>);
asserting, by the column decoder in response to control signals from the test control logic, a bit line in the array (<NUM>);
sensing, by a sense amplifier, a current received from the bit line (<NUM>); and
generating, by a reference current source (<NUM>) a reference current (IREF <NUM>) , the generating comprising: (i) receiving a reference current bias (Ibiasunit); (ii) receiving a digital input; (iii) mirroring the reference current bias into a plurality of devices (<NUM>), each of the plurality of devices comprising a first NMOS transistor (<NUM>) comprising a first terminal providing an output current, a second terminal, and a gate receiving an enable signal; and a second NMOS transistor (<NUM>) comprising a first terminal coupled to the second terminal of the first NMOS transistor, a second terminal coupled to ground, and a gate receiving the reference current bias; (iv) enabling one or more of the plurality of devices in response to the digital input by asserting the enable signal for the enabled devices; (v) mirroring the enabled devices by a buffer mirror (<NUM>) to generate the reference current equal to the sum of the output currents generated by the enabled devices;
comparing, by the test control logic, the current to the reference current to determine if the non-volatile memory cells coupled to the bit line contain the desired neuron value (<NUM>).