Patent Description:
In many electronics applications, an analog input signal is converted to a digital output signal (e.g., for further digital signal processing). For instance, in precision measurement systems, electronics are provided with one or more sensors to make measurements, and these sensors can generate an analog signal. The analog signal can then be provided to an analog-to-digital converter (ADC) circuit as input to generate a digital output signal for further processing. In another instance, in a mobile device receiver, an antenna can generate an analog signal based on the electromagnetic waves carrying information/signals in the air. The analog signal generated by the antenna can then be provided as input to an ADC to generate a digital output signal for further processing.

Publication <NPL> presents an autofocus (AF) sensor with global shutters using offset-free frame memory. The proposed offset-free frame memories consist of flip-around sample-and-hold amplifiers with correlated double sampling.

This disclosure is directed to, among other things, techniques to reduce the on-time of a multi-stage ADC circuit by combining the settling time of a signal conditioning circuit, e.g., buffer circuit, and the setting time of a residue amplifier when cancelling the offset of the signal conditioning circuit. The techniques of this disclosure can allow the signal conditioning circuit and the residue amplifier to settle together.

In some aspects, this disclosure is directed to a method of canceling an offset of a signal conditioning circuit coupled to an input of a multi-stage analog-to-digital converter (ADC) circuit. The method comprises sampling an analog input signal and the offset; performing, by a first stage of the ADC circuit, a first conversion on the sampled analog input signal and offset; shorting an input of the signal conditioning circuit to determine its offset before it is subtracted from the sum of the sampled analog input signal and the offset; concurrently canceling the offset by subtracting the offset from the sum of the sampled analog input signal and the offset and amplifying a residue of the sampled analog input signal; performing, by a second stage of the ADC circuit, a second conversion on the residue of the sampled analog input signal; and generating a digital output signal representing the sampled analog input signal.

In some aspects, this disclosure is directed to a multi-stage analog-to-digital converter (ADC) circuit having an input coupled to a signal conditioning circuit having an offset. The ADC circuit comprises a sample-and-hold circuit configured to sample an analog input signal and the offset from the signal conditioning circuit; a first stage including a first ADC sub-circuit configured to perform a first conversion on the sampled analog input signal and offset; a control circuit configured to operate a plurality of switches to generate the residue of the first conversion and eliminate the offset from the residue by subtracting the offset from the sum of the sampled analog input signal and the offset, the control circuit being further configured to short an input of the signal conditioning circuit to determine its offset before it is subtracted from the sum of the sampled analog input signal and the offset; a residue amplifier configured to amplify a residue of the sampled analog input signal concurrently with the control circuit eliminating the offset; a second stage including a second ADC sub-circuit configured to perform a second conversion on the residue of the sampled analog input signal; and an encoder circuit configured to combine first and second conversion results and generate a digital output signal representing the sampled analog input signal.

In a comparative example, this disclosure is directed to a multi-stage analog-to-digital converter (ADC) circuit having an input coupled to a signal conditioning circuit having an offset. The ADC circuit comprises a sample-and-hold circuit configured to sample an analog input signal and the offset; means for performing, by a first stage of the ADC circuit, a first conversion on the sampled analog input signal and offset, the means being further configured to short an input of the signal conditioning circuit to determine its offset before it is subtracted from the sum of the sampled analog input signal and the offset; means for canceling the offset and amplifying a residue of the sampled analog input signal; means for performing, by a second stage of the ADC circuit, a second conversion on the residue of the sampled analog input signal; and means for generating a digital output signal representing the sampled analog input signal.

Multi-stage analog-to-digital converters can utilize a successive series of stages (or cycles of operation) each arranged to develop a digital output of limited scope, e.g., one or more bits, and to produce from each stage (or cycle of operation) an analog residue signal as the input for the next stage (or cycle). In this way, a high-resolution output can be developed by combining the digital outputs of the several stages or cycles.

Multi-stage ADC architectures can use inter-stage amplification, e.g., using a residue amplifier, particularly when the overall resolution exceeds about nine bits. Such amplification is for the purpose of raising the residue of one conversion to a level that can be digitized by the next subsequent stage.

Multi-stage ADC architectures can use various analog-to-digital converter (ADC) topologies, including delta-sigma, flash, and successive approximation register (SAR) data converters. One of the attractive characteristics of SAR data converters is their ability to scale power consumption with conversion rate. The data converter only requires power during a conversion and can be powered down between conversions. Hence, the shorter the duty cycle the converter is on, the less power is consumed.

Zero-drive data converters, e.g., converters that do not draw current from the input, can incorporate a buffer amplifier at the input, such that they can be driven by sources with a high impedance. Zero-drive converters can include buffer circuits, e.g., buffer amplifiers, or other signal conditioning circuitry, e.g., instrumentation amplifiers, transimpedance amplifiers, and filters, coupled to their inputs. To eliminate offset and <NUM>/f noise generated by the signal conditioning circuitry, it can be chopped or auto-zeroed, for example. Both chopping and auto-zeroing can extend the time that the data-converter is powered up, and hence increase the duty cycle.

In an existing approach to offset cancellation in a multi-stage ADC circuit, the offset of the signal conditioning circuit, e.g., buffer circuit, coupled to an input of the multi-stage ADC circuit can be auto-zeroed. Then, the analog input signal can be sampled.

The first stage of the multi-stage ADC circuit can perform a coarse conversion on the sampled analog input signal to generate an output, e.g., the most significant bits (MSBs) and a residue signal. The residue signal is the difference between a feedback DAC output, which converts the coarse conversion output (MSBs) to an analog signal, and the sampled analog input signal. The residue signal can be amplified by a residue amplifier and transferred to the second stage of the multi-stage ADC circuit and the second stage can perform a fine conversion on the amplified residue signal to generate the remaining bits, e.g., the least significant bits (LSBs).

In the case of chopping, the two sampling phases can include the sum of two half samples, each with an opposite polarity of the offset of the signal conditioning circuit. As such, the total conversion time would be similar to the approach described above.

For a continuous running ADC, the signal conditioning circuit can perform auto-zeroing during one conversion (while the ADC is performing either a coarse conversion or a fine conversion, for example), and next apply the auto-zeroed signal conditioning circuit during the sampling phase of the next conversion. Hence, the algorithm can measure offset in one conversion, and correct for it in the next conversion. The offset therefore should be substantially constant between any two subsequent samples. Due to drift and <NUM>/f noise, this condition fails when the time between two subsequent samples is too long, like in the case of convert on demand. In that case, the offset should be measured and eliminated within a conversion.

The present inventors have recognized a need to eliminate the extra time needed for offset cancellation in a multi-stage ADC circuit. Using various techniques of this disclosure, the on-time of the multi-stage ADC circuit can be reduced by combining the settling time of a signal conditioning circuit, e.g., buffer circuit, and the setting time of a residue amplifier when cancelling the offset of the signal conditioning circuit. As described in detail below, the techniques of this disclosure can allow the signal conditioning circuit and the residue amplifier to settle together.

<FIG> is a conceptual block diagram of an example of a multi-stage ADC circuit <NUM> during a first phase of an operation that can implement various techniques of this disclosure. A signal conditioning circuit <NUM>, e.g., buffer circuit, having an offset voltage VOFF is coupled to an input of the multi-stage ADC circuit <NUM> and is configured to receive and condition an analog input signal VIN. The multi-stage ADC circuit <NUM> shown in <FIG> can include two stages. The first stage can include a first sample-and-hold circuit (S/H) <NUM>, a first ADC sub-circuit <NUM>, a first digital-to-analog converter (DAC) circuit <NUM>, and a residue amplifier circuit <NUM>. The second stage can include a second S/H circuit <NUM>, a second ADC sub-circuit <NUM>, and an encoder circuit <NUM>. A control circuit <NUM> can control various operations of ADC circuit <NUM>, including closing and opening switches S1-S5. The control circuit <NUM> can operate the switches S1-S5 to generate or establish a residue of the first conversion and eliminate, e.g., concurrently, the signal conditioning circuit offset from that residue.

Operation of the multi-stage ADC circuit <NUM> will now be briefly described, without specific reference to the first phase of operation. The first ADC sub-circuit <NUM> of the first stage can perform a first conversion, e.g., coarse conversion, on the sampled analog input signal to generate an output, e.g., the MSBs. A residue signal can be generated by subtracting the output of the first DAC circuit <NUM> from the sampled analog input signal VIN. The residue signal can be amplified by the residue amplifier <NUM> and transferred to the second S/H circuit <NUM> of the second stage of the multi-stage ADC circuit <NUM>. The second ADC sub-circuit <NUM> of the second stage can perform a second conversion, e.g., fine conversion, on the amplified residue signal to generate an output containing the remaining bits, e.g., the LSBs. The encoder circuit <NUM> can receive the output of the first ADC sub-circuit <NUM> (a first conversion result) and the output of the second ADC sub-circuit <NUM> (a second conversion result) and generate a digital output signal DOUT.

During the first phase of operation, a control circuit <NUM> can close the switches S1 and S4, open the switches S2, S3, and S5, and the first S/H circuit <NUM>, e.g., including one or more capacitors, can sample the analog input signal VIN. The offset voltage VOFF of the signal conditioning circuit <NUM> is added to the analog input signal VIN and sampled. During sampling, the remaining circuitry of the multi-stage ADC circuit <NUM> can be inactive and, as such, consuming little to no power.

<FIG> is a conceptual block diagram of the multi-stage ADC circuit of <FIG> during a second phase of operation. During the second phase of operation, the control circuit <NUM> can open the switch S1 and close the switch S2 to couple the input of the signal conditioning circuit <NUM> to ground (if single-ended) to establish the offset VOFF of the signal conditioning circuit <NUM>, and close the switch S5 to couple the first S/H circuit <NUM> to the first ADC sub-circuit <NUM>. The first stage of the multi-stage ADC circuit <NUM> can perform a conversion, e.g., coarse conversion, on the combination of the sampled analog input signal VIN and the offset voltage VOFF associated with that sample and generate a first stage output. During this phase, one or more of the signal conditioning circuit <NUM>, the residue amplifier <NUM>, the second S/H circuit <NUM>, the second ADC sub-circuit <NUM>, and the encoder circuit <NUM> can be inactive and, as such, consume little to no power.

<FIG> is a conceptual block diagram of the multi-stage ADC circuit of <FIG> during a third phase of operation. During this phase, the signal conditioning circuit <NUM>, the first S/H circuit <NUM>, the first DAC circuit <NUM>, the residue amplifier <NUM>, and the second S/H circuit <NUM> can be active, and the first ADC sub-circuit <NUM>, the second ADC sub-circuit <NUM>, and the encoder circuit <NUM> can be inactive. During the third phase of operation, the control circuit <NUM> can close the switch S3 to apply the offset voltage VOFF to the summing node <NUM>. The offset voltage VOFF can be canceled by subtracting the offset voltage VOFF (from coupling the input of the signal conditioning circuit <NUM> to ground) from the sum of the sampled analog input signal VIN and the offset voltage VOFF. For example, the summing node <NUM> can be configured to invert the offset input and the inverted offset voltage VOFF can be combined with the sum of the sampled analog input signal VIN and the offset voltage VOFF. Then, the residue amplifier <NUM> can amplify the residue of the sampled analog input signal VIN.

In this manner, the offset voltage VOFF can be canceled while the multi-stage ADC circuit <NUM> performs the residue amplification. The residue amplifier <NUM> takes time to amplify and the signal conditioning circuit takes time to settle. However, using the techniques described in this disclosure, the speed of the multi-stage ADC circuit can be improved because the time for the residue amplifier to amplify and the time for the signal conditioning circuit to settle happen concurrently rather than sequentially (as in other approaches). As such, the net time is the time of the residue amplifier to amplify.

<FIG> is a conceptual block diagram of the multi-stage ADC circuit of <FIG> during a fourth phase of operation. During this phase, the second S/H circuit <NUM> and the second ADC sub-circuit <NUM> can be active while the other circuitry can be powered off. During the fourth stage of operation, the control circuit <NUM> can open the switch S3 and the second stage of the multi-stage ADC circuit <NUM> can perform a conversion, e.g., a fine conversion, on the residue of the sampled analog input signal VIN (and generate a second stage output). The encoder circuit <NUM> can receive the first stage output and the second stage output and generate a digital output DOUT that represents the sampled analog input signal VIN. It should be noted that in some implementations, the second ADC sub-circuit <NUM> can be configured to accommodate an extra correction range for the offset that was added during the first stage of operation.

Although <FIG> were described with respect to a two-stage ADC circuit, the techniques of this disclosure are applicable to multi-stage ADC circuits having more than two stages. In multi-stage converters, there can be a second, a third, and more stages. There can be a second residue amplifier, that amplifies the second residue from the second stage. And a third ADC sub-circuit can perform a third conversion on the residue from the second stage. An encoder combines the outputs of all ADC sub-circuits stages and generates the digital output.

The first ADC sub-circuit <NUM> of the first stage can be implemented using various ADC circuit topologies. For example, the first ADC sub-circuit <NUM> can be a SAR ADC circuit configured to perform a conversion using a SAR algorithm. In other example implementations, the first ADC sub-circuit <NUM> can be a delta-sigma ADC circuit configured to perform a conversion using a delta-sigma algorithm. In other example implementations, the first ADC sub-circuit <NUM> can be a flash converter.

Similarly, the second ADC sub-circuit <NUM> of the second stage can be implemented using various ADC circuit topologies. For example, the second ADC sub-circuit <NUM> can be a SAR ADC circuit configured to perform a conversion using a SAR algorithm. In other example implementations, the second ADC sub-circuit <NUM> can be a delta-sigma ADC circuit configured to perform a conversion using a delta-sigma algorithm. In other example implementations, the second ADC sub-circuit <NUM> can be a flash converter.

In other example configurations, the first ADC sub-circuit <NUM> can be a hybrid ADC circuit configured to perform at least two algorithms selected from a group consisting of a successive approximation register (SAR) algorithm, a delta-sigma algorithm, and a flash algorithm. For example, the first ADC sub-circuit <NUM> can include both flash converter circuitry and SAR circuitry. Alternatively, or additionally, the second ADC sub-circuit can be configured as a hybrid ADC circuit.

<FIG> depicts a specific non-limiting multi-stage ADC circuit that can implement various techniques in this disclosure. In particular, the multi-stage ADC circuit of <FIG> utilizes SAR ADC sub-circuits.

<FIG> is a conceptual block diagram of another example of a multi-stage ADC circuit that can implement various techniques of this disclosure. The multi-stage ADC circuit <NUM> shown in <FIG> includes two stages, but the techniques are applicable to more than two stages. The multi-stage ADC circuit <NUM> of <FIG> can include components similar to those shown in <FIG> and are depicted with similar reference numbers.

The first stage can include a first sample-and-hold circuit (S/H) <NUM>, a first SAR ADC sub-circuit including a first comparator circuit <NUM> and a first SAR register circuit <NUM>, a first DAC circuit <NUM>, and a residue amplifier circuit <NUM>. The second stage can include a second S/H circuit <NUM>, a second SAR ADC sub-circuit including a second comparator circuit <NUM> and a second SAR register circuit <NUM>, and an encoder circuit <NUM>. A buffer circuit <NUM>, having an offset voltage VOFF and coupled to an input of the multi-stage ADC circuit <NUM>, is configured to receive and buffer an analog input signal VIN.

The multi-stage ADC circuit <NUM> shown in <FIG> can operate in several phases, such as described above with respect to <FIG>. In general, the phases can include sampling the analog input signal VIN without auto-zeroing the buffer circuit <NUM>, performing a first conversion, e.g., coarse conversion, using the first SAR ADC sub-circuit, performing residue amplification of the sampled residue while cancelling the buffer offset, and performing a second conversion, e.g., fine conversion, using the second SAR ADC sub-circuit.

<FIG> is a flowchart of an example of a method <NUM> of canceling an offset of a signal conditioning circuit coupled to an input of a multi-stage analog-to-digital converter (ADC) circuit using various techniques of this disclosure. At block <NUM>, the method <NUM> can include sampling an analog input signal and the offset. For example, the control circuit <NUM> of <FIG> can close the switch S1 and the first S/H circuit <NUM> can sample the analog input signal VIN and the offset voltage VOFF of the signal conditioning circuit <NUM>.

At block <NUM>, the method <NUM> can include performing, by a first stage of the ADC circuit, a first conversion on the sampled analog input signal and offset VOFF. For example, the control circuit <NUM> of <FIG> can open the switch S1 and close the switch S2 to couple the input of the signal conditioning circuit <NUM> to ground (if single-ended) to establish the offset VOFF of the signal conditioning circuit <NUM>. The first stage of the multi-stage ADC circuit <NUM> can perform a conversion, e.g., coarse conversion, on the combination of the sampled analog input signal VIN and the offset voltage VOFF associated with that sample.

At block <NUM>, the method <NUM> can include canceling the offset and amplifying a residue of the sampled analog input signal. For example, the offset voltage VOFF can be canceled by subtracting the offset voltage VOFF (from coupling the input of the signal conditioning circuit <NUM> to ground) from the sum of the sampled analog input signal VIN and the offset voltage VOFF. Then, the residue amplifier <NUM> can amplify the residue of the sampled analog input signal VIN.

At block <NUM>, the method <NUM> can include performing, by a second stage of the ADC circuit, a second conversion on the residue of the sampled analog input signal. For example, the second stage of the multi-stage ADC circuit <NUM> of <FIG> can perform a conversion, e.g., a fine conversion, on the residue of the sampled analog input signal VIN (and generate a second stage output, or conversion result).

At block <NUM>, the method <NUM> can include generating a digital output signal representing the sampled analog input signal. For example, the encoder circuit <NUM> of <FIG> can receive the first stage output (first stage conversion result) and the second stage output (second stage conversion result) and generate a digital output DOUT that represents the sampled analog input signal VIN.

Using the techniques described above, the speed of the multi-stage ADC circuit can be improved because the time for the residue amplifier to amplify and the time for the signal conditioning circuit to settle happen concurrently rather than sequentially (as in other approaches). Thus, the net time is the time of the residue amplifier to amplify.

Each of the non-limiting aspects or examples described herein may stand on its own or may be combined in various permutations or combinations with one or more of the other examples.

The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. " Such examples may include elements in addition to those shown or described.

Method examples described herein may be machine or computer-implemented at least in part. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods may include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code may include computer readable instructions for performing various methods. Further, in an example, the code may be tangibly stored on one or more volatile, non-transitory, or nonvolatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.

Claim 1:
A method (<NUM>) of canceling an offset of a signal conditioning circuit coupled to an input of a multi-stage analog-to-digital converter, ADC, circuit, the method comprising:
sampling (<NUM>) an analog input signal and the offset;
performing (<NUM>), by a first stage of the ADC circuit, a first conversion on the sampled analog input signal and offset;
shorting an input of the signal conditioning circuit to determine its offset before it is subtracted from the sum of the sampled analog input signal and the offset;
concurrently canceling (<NUM>) the offset by subtracting the offset from the sum of the sampled analog input signal and the offset and amplifying a residue of the sampled analog input signal;
performing (<NUM>), by a second stage of the ADC circuit, a second conversion on the residue of the sampled analog input signal; and
generating (<NUM>) a digital output signal representing the sampled analog input signal.