Patent Description:
Semiconductor lasers are expected as high-intensity next-generation light sources. Among others, semiconductor lasers using nanostructures (nanocolumns) are expected to realize high-power light emission at narrow radiation angles due to the effect of photonic crystal by the nanostructures. The semiconductor lasers are applied as e.g. light sources of projectors.

For example, in PTL <NUM>, a semiconductor light emitting element in which a reflection layer of a metal film is formed on a substrate and a plurality of nanocolumns are formed on the reflection layer is described.

However, in PTL <NUM>, a switching element for flowing or not flowing a current (for turning ON/OFF the current to be injected) in the semiconductor light emitting element (light emitting unit) is not described.

One of the purposes according to several aspects of the invention is to provide a light emitting device including a switching element. Or, one of the purposes according to the several aspects of the invention is to provide a projector including the light emitting device.

A light emitting device according to the invention is defined in claim <NUM>.

In the light emitting device of the invention, a possibility that dislocation generated due to a difference between the lattice constant of the base and the lattice constant of the first semiconductor layer exists in regions at a fixed height or more of the nanostructures may be reduced.

In the light emitting device, a possibility that dislocation generated due to a difference between the lattice constant of the base and the lattice constant of the first semiconductor layer exists in the light emitting layer may be reduced.

In the light emitting device according to the invention, the transistor may have a source region and a drain region, a channel region between the source region and the drain region, and a gate that controls a current flowing in the channel region, and the source region and the drain region may be provided in the first semiconductor layer.

In the light emitting device, the transistor and the light emitting unit may be formed on the same substrate (single base). Therefore, in the light emitting device, downsizing may be realized compared to the case where the transistor and the light emitting unit are provided on separate substrates.

In the light emitting device according to the invention, the source region or the drain region may be electrically coupled to the second semiconductor layer.

In the light emitting device, the amount of current injected in the light emitting unit may be controlled and the amount of emitted light of the light emitting unit may be controlled by the transistor.

Note that, in the description according to the invention, the phrase "electrically coupled" is used as e.g. a specific member (hereinafter, referred to as "A member") "electrically coupled" to another specific member (hereinafter, referred to as "B member") or the like. In the description according to the invention, in the case of the example, the phrase "electrically coupled" is used to include the case where the A member and the B member are in direct contact and electrically coupled and the case where the A member and the B member are electrically coupled via another member.

In the light emitting device according to the invention, the light emitting unit has a light propagation layer provided between the adjacent nanostructures and propagating the light generated in the light emitting unit, wherein the light propagation layer has a lower refractive index than the light emitting layer, so that the light generated in the light emitting layer propagates in the in-plane direction of the base, is gained in the light emitting layer, and laser-oscillates.

In the light emitting device according to the invention, an insulating layer is provided on a side wall of the light emitting unit, so that leakage of the current injected in the light emitting unit from the side wall may be suppressed by the insulating layer.

The light emitting device according to the invention includes a metal layer provided on a surface of the insulating layer.

In the light emitting device, the resistance to the current injected in the third semiconductor layer is made smaller.

In the light emitting device according to the invention, the first semiconductor layer may be a GaN layer, InGaN layer, AlGaN layer, AlGaAs layer, InGaAs layer, InGaAsP layer, InP layer, GaP layer, or AlGaP layer.

In the light emitting device, for example, stress generated due to a difference between the lattice constant of the first semiconductor layer and the lattice constant of the second semiconductor layer is suppressed.

In a preferred embodiment of the invention, the light emitting units are provided in an array form.

In a preferred embodiment of the invention, a self-emitting imager that forms a picture with the single light emitting unit as a pixel is configured.

A projector according to a preferred embodiment of the invention includes the light emitting device according to the invention.

In a preferred embodiment of the invention, the projector includes the light emitting device according to the invention.

As below, preferred embodiments of the invention will be explained in detail using the drawings.

First, a light emitting device according to a first embodiment, useful for understanding the invention, will be explained with reference to the drawings. <FIG> is a plan view schematically showing a light emitting device <NUM> according to the first embodiment. <FIG> is a sectional view along II-II line in <FIG> schematically showing the light emitting device <NUM> according to the first embodiment. <FIG> is a sectional view along III-III line in <FIG> schematically showing the light emitting device <NUM> according to the first embodiment. <FIG> is a circuit diagram of the light emitting device <NUM> according to the first embodiment. Note that, in <FIG> and <FIG> and <FIG>, which will be described later, an X-axis, a Y-axis, and a Z-axis are shown as three axes orthogonal to one another.

As shown in <FIG>, the light emitting device <NUM> includes e.g. a base <NUM>, semiconductor layers <NUM>, <NUM>, an element isolation layer <NUM>, transistors <NUM>, light emitting units <NUM>, first insulating layers <NUM>, a second insulating layer <NUM>, conducting layers <NUM>, interconnections <NUM>, and drive circuits <NUM>, <NUM>. For convenience of explanation, the illustration of the second insulating layer <NUM> is omitted in <FIG>.

As shown in <FIG>, the base <NUM> has e.g. a first substrate <NUM>, a second substrate <NUM>, and a semiconductor layer <NUM>. The first substrate <NUM> is e.g. a printed board. The second substrate <NUM> is provided on the first substrate <NUM>. The second substrate <NUM> is e.g. a sapphire substrate, Si substrate, GaN substrate, or the like. The semiconductor layer <NUM> is provided on the second substrate <NUM>. The semiconductor layer <NUM> is e.g. an i-type GaN layer.

The semiconductor layers (first semiconductor layers) <NUM> are provided on the base <NUM> (on the semiconductor layer <NUM> in the illustrated example). The semiconductor layer <NUM> is e.g. an n-type GaN layer (specifically, a GaN layer doped with Si).

The semiconductor layers <NUM> are provided on the semiconductor layer <NUM>. The semiconductor layers <NUM> are provided between the semiconductor layers <NUM>. The semiconductor layers <NUM> are provided under gates <NUM> of the transistors <NUM>. The semiconductor layer <NUM> is e.g. a p-type GaN layer (specifically, a GaN layer doped with Mg).

The element isolation layer <NUM> is provided on the semiconductor layer <NUM>. As shown in <FIG>, the element isolation layer <NUM> is provided around the semiconductor layers <NUM> in the plan view (as seen from a direction of the Z-axis, as seen from a stacking direction of a semiconductor layer 42a and a light emitting layer 42b of the light emitting unit <NUM>). The element isolation layer <NUM> is e.g. an i-type GaN layer, a silicon oxide layer, a silicon nitride layer, or the like. The element isolation layer <NUM> electrically isolates the light emitting units <NUM> adjacent to each other in the X-axis direction.

As shown in <FIG>, the transistor <NUM> has a source region <NUM>, a drain region <NUM>, a channel region <NUM>, and the gate <NUM>. The source region <NUM> and the drain region <NUM> are provided in the semiconductor layer <NUM>. The channel region <NUM> is a region between the source region <NUM> and the drain region <NUM>. The channel region <NUM> is provided in the semiconductor layer <NUM>. For example, capacitance is formed in the channel region <NUM>.

The gate <NUM> is provided on the semiconductor layer <NUM>. The gate <NUM> controls the current flowing in the channel region <NUM>. The gate <NUM> has a gate insulating layer 38a provided on the semiconductor layer <NUM> and a gate electrode 38b provided on the gate insulating layer 38a. The gate insulating layer 38a is e.g. a silicon oxide layer. The material of the gate insulating layer 38a is e.g. copper, aluminum, or the like.

A plurality of the transistors <NUM> are provided. The transistors <NUM> are provided in an array form. That is, the transistors <NUM> are provided side by side in predetermined directions. In the example shown in <FIG>, the transistors <NUM> are provided side by side in the X-axis direction and the Y-axis direction (in a matrix form). The transistors <NUM> arranged in the X-axis direction have e.g. the common gate insulating layers 38a and gate electrodes 38b. In the illustrated example, the gate electrodes 38b extend in the X-axis direction from pads <NUM> provided on the element isolation layer <NUM>. The plurality of gate electrodes 38b are arranged in the Y-axis direction. As shown in <FIG>, the transistors <NUM> adjacent to each other in the Y-axis direction have e.g. the common source regions <NUM>.

The transistors <NUM> are provided in correspondence with the light emitting units <NUM>. In the embodiment, the number of the transistors <NUM> and the number of the light emitting units <NUM> are the same, and the transistors <NUM> are electrically coupled to the light emitting units <NUM>. Specifically, the source region <NUM> or drain region <NUM> of the transistor <NUM> is electrically coupled to the semiconductor layer 42a of the light emitting unit <NUM>. That is, even when the transistor <NUM> is OFF (no current flows in the channel region <NUM>), the source region <NUM> or drain region <NUM> is electrically coupled to the semiconductor layer 42a. In the illustrated example, the drain region <NUM> is electrically coupled to the semiconductor layer 42a. The transistor <NUM> controls amounts of currents injected in nanostructures <NUM> of the light emitting unit <NUM>. Further, the transistor <NUM> is controlled, and thereby, a time of light emission may be controlled with respect to each light emitting unit <NUM>. Or, the amount of current injected in the light emitting unit <NUM> may be controlled by control of the transistor <NUM>.

In this embodiment, not falling under the scope of the invention, the sentence that the transistors <NUM> are provided in correspondence with the light emitting units <NUM> represents that at least one transistor <NUM> is provided in correspondence with the light emitting unit <NUM>. In the embodiment, the number of transistors provided in correspondence with the light emitting unit <NUM> is not limited to one, but a plurality of transistors may be provided in correspondence with the light emitting unit <NUM>.

The light emitting units <NUM> are provided on the semiconductor layers <NUM>. A plurality of the light emitting units <NUM> are provided. The light emitting units <NUM> are provided in an array form. That is, the light emitting units <NUM> are provided side by side in predetermined directions. In the example shown in <FIG>, the light emitting units <NUM> are provided side by side in the X-axis direction and the Y-axis direction (in a matrix form). Here, <FIG> is a plan view schematically showing the light emitting unit <NUM>. <FIG> is a sectional view along VI-VI line in <FIG> schematically showing the light emitting unit <NUM>.

As shown in <FIG> and <FIG>, the light emitting unit <NUM> has the nanostructures <NUM> and a light propagation layer <NUM>. For convenience of explanation, illustration of the conducting layer <NUM> and the second insulating layer <NUM> is omitted in <FIG>.

Note that, "upper" refers to a direction away from the base <NUM> as seen from the nanostructures <NUM> in the Z-axis direction (the stacking direction of the semiconductor layer 42a and the light emitting layer 42b of the nanostructure <NUM>), and "lower" refers to a direction closer to the base <NUM> as seen from the nanostructures <NUM> in the Z-axis direction.

The nanostructures <NUM> are provided on the semiconductor layer <NUM>. The nanostructures <NUM> have columnar shapes. The nanostructures <NUM> are columnar portions projecting from the semiconductor layer <NUM>. A plurality of the nanostructures <NUM> are provided. In the example shown in <FIG>, the planar shape (the shape as seen from the Z-axis direction) of the nanostructure <NUM> is a rectangular shape. The diameter of the nanostructure <NUM> (in the case of a polygon, the diameter of the inscribed circle) is on the order of nanometers (less than <NUM>), and specifically <NUM> or more and <NUM> or less. The nanostructure <NUM> is also called e.g. a nanocolumn, nanowire, nanorod, or nanopillar. The size of the nanostructure <NUM> in the Z-axis direction is e.g. <NUM> or more and <NUM> or less. The plurality of nanostructures <NUM> are separated from one another. The distance between the adjacent nanostructures <NUM> is e.g. <NUM> or more and <NUM> or less.

Note that the planar shape of the nanostructure <NUM> is not particularly limited, but may be e.g. a hexagonal shape as shown in <FIG>, rectangular shape, another polygonal shape than the hexagonal shape, circular shape, elliptical shape, or the like. In the illustrated examples, the nanostructures <NUM> have fixed diameters in the Z-axis direction, but may have different diameters in the Z-axis direction.

The plurality of nanostructures <NUM> are arranged in predetermined directions at predetermined pitches in the plan view. In the periodical structure, an optical confinement effect is obtained at a photonic band edge wavelength λ determined by the pitch, the diameters of the respective parts, and the refractive indexes of the respective parts. In the light emitting device <NUM>, the light generated in the light emitting layer 42b of the nanostructure <NUM> contains the wavelength λ, and thereby, may express the effect of the photonic crystal. In the example shown in <FIG>, the nanostructures <NUM> are provided side by side in the X-axis direction and the Y-axis direction (in a matrix form).

As shown in <FIG>, the nanostructure <NUM> has the semiconductor layer (second semiconductor layer) 42a, the light emitting layer 42b, and a semiconductor layer (third semiconductor layer) 42c.

The semiconductor layer 42a is provided on the semiconductor layer <NUM>. The semiconductor layer 42a is provided between the base <NUM> and the light emitting layer 42b. The semiconductor layer 42a is e.g. an n-type GaN layer (specifically, a GaN layer doped with Si).

The light emitting layer 42b is provided on the semiconductor layer 42a. The light emitting layer 42b is provided between the semiconductor layer 42a and the semiconductor layer 42c. The light emitting layer 42b is a layer configured to emit light with injection of a current. The light emitting layer 42b has e.g. a quantum well structure including a GaN layer and an InGaN layer. The numbers of the GaN layers and the InGaN layers forming the light emitting layer 42b are not particularly limited.

The semiconductor layer 42c is provided on the light emitting layer 42b. The semiconductor layer 42c is a layer having a different conductivity type from that of the semiconductor layer 42a. The semiconductor layer 42c is e.g. a p-type GaN layer (specifically, a GaN layer doped with Mg). The semiconductor layers 42a, 42c are cladding layers having a function of confining light in the light emitting layer 42b (suppressing leakage of light from the light emitting layer 42b).

In the light emitting device <NUM>, a pin diode is formed by the p-type semiconductor layer 42c, the light emitting layer 42b doped with no impurity, and the n-type semiconductor layer 42a. The semiconductor layers 42a, 42c are layers having larger band gaps than the light emitting layer 42b. In the light emitting device <NUM>, when a forward bias voltage of the pin diode is applied (a current is injected) between the conducting layer <NUM> and the semiconductor layer <NUM>, recombination between the electron and the hole occurs in the light emitting layer 42b. A light is emitted by the recombination. The light generated in the light emitting layer 42b propagates in a direction orthogonal to the Z-axis direction (planar direction) by the semiconductor layers 42a, 42c. The propagated light forms standing wave, is gained in the light emitting layer 42b, and laser-oscillates. Then, the light emitting device <NUM> outputs a +1st order diffracted light and a -1st order diffracted light as laser beams in the stacking directions (toward the conducting layer <NUM> side and the base <NUM> side).

In the light emitting device <NUM>, the refractive indexes and the thicknesses of the semiconductor layers 42a, 42c and the light emitting layer 42b are designed so that intensity of the light propagating in the planar direction may be the highest in the light emitting layer 42b in the Z-axis direction.

Though not shown in the drawings, a reflection layer may be provided between the base <NUM> and the semiconductor layer <NUM> or under the base <NUM>. The reflection layer is e.g. a DBR (Distributed Bragg Reflector) layer. The light generated in the light emitting layer 42b may be reflected by the reflection layer, and the light emitting device <NUM> may output the light only from the conducting layer <NUM> side.

In the illustrated example, third insulating layers <NUM> are provided on the semiconductor layer <NUM>. The third insulating layers <NUM> are provided between the light propagation layers <NUM> and the semiconductor layer <NUM> and between the first insulating layers <NUM> and the semiconductor layer <NUM>. The third insulating layers <NUM> function as masks for formation of the nanostructures <NUM>. The third insulating layers <NUM> may be formed in the same process as that of the gate insulating layers 38a. Accordingly, the material and the thickness of the third insulating layers <NUM> may be the same as those of the gate insulating layers 38a.

The light propagation layer <NUM> is provided between the adjacent nanostructures <NUM>. The light propagation layer <NUM> is provided on the third insulating layer <NUM>. The light propagation layers <NUM> are provided to surround the nanostructures <NUM> in the plan view. The refractive index of the light propagation layer <NUM> is lower than the refractive index of the light emitting layer 42b. The light propagation layer <NUM> is e.g. a GaN layer or titanium oxide (TiO<NUM>) layer. The GaN layer as the light propagation layer <NUM> may be of i-type, n-type, or p-type. The light propagation layer <NUM> may propagate the light generated in the light emitting layer 42b in the planar direction. In the example shown in <FIG>, the planar shape of the light emitting unit <NUM> is a square shape.

Note that, when "specific member (A member)" is formed from a plurality of materials, "refractive index of A member" refers to an average refractive index of the plurality of materials forming the A member.

As shown in <FIG>, the first insulating layer <NUM> is provided on a side wall <NUM> of the light emitting unit <NUM>. The first insulating layer <NUM> is provided in the planar direction of the light emitting layer 42b. The first insulating layer <NUM> is a side wall provided on the side wall <NUM> of the light emitting unit <NUM>. In the illustrated example, the side wall <NUM> is formed by the light propagation layer <NUM>. For example, as shown in <FIG>, the side wall <NUM> has a first side surface 41a and a second side surface 41b facing each other, and a third side surface 41c and a fourth side surface 41d coupled to the side surfaces 41a, 41b and facing each other.

As shown in <FIG>, the first insulating layer <NUM> is provided on the third insulating layer <NUM>. The first insulating layer <NUM> is provided to surround the light emitting unit <NUM> in the plan view. The refractive index of the first insulating layer <NUM> is lower than the refractive index of the light propagation layer <NUM>. The material of the first insulating layer <NUM> is e.g. silicon oxide (SiO<NUM>), silicon nitride (SiN), or the like. The first insulating layer <NUM> is formed by e.g. a single layer.

The first insulating layer <NUM> may reflect the light generated in the light emitting layer 42b. The light generated in the light emitting layer 42b forms standing wave between the first side surface 41a and the second side surface 41b. Further, the light generated in the light emitting layer 42b forms standing wave between the third side surface 41c and the fourth side surface 41d.

As shown in <FIG>, the second insulating layer <NUM> is provided on the semiconductor layer <NUM>. The second insulating layer <NUM> is provided to cover the gates <NUM> and surfaces <NUM> of the first insulating layers <NUM>. The second insulating layer <NUM> is e.g. a silicon oxide layer. The second insulating layer <NUM> has a function of protecting the transistors <NUM> and the light emitting units <NUM> from impact or the like.

The conducting layer <NUM> is provided on the light emitting unit <NUM>. In the illustrated example, the conducting layer <NUM> is provided on the nanostructures <NUM> and the light propagation layers <NUM>. A plurality of the conducting layers <NUM> are provided in correspondence with the number of the light emitting units <NUM>. The conducting layer <NUM> is electrically coupled to the semiconductor layers 42c of the nanostructures <NUM>. The conducting layer <NUM> is e.g. an ITO (Indium Tin Oxide) layer. The light generated in the light emitting layer 42b is transmitted and output through the conducting layer <NUM>.

Though not shown in the drawings, a contact layer may be provided between the conducting layer <NUM> and the light emitting unit <NUM>. The contact layer may be in ohmic contact with the conducting layer <NUM>. The contact layer may be a p-type GaN layer.

As shown in <FIG>, the interconnection <NUM> is provided on the second insulating layer <NUM>. As shown in <FIG>, the interconnection <NUM> extends in the Y-axis direction from a pad <NUM> provided on the element isolation layer <NUM>, branches according to the number of the conducting layers <NUM>, and coupled to the conducting layers <NUM>. The interconnection <NUM> is electrically coupled to the semiconductor layers 42c via the conducting layers <NUM>. A plurality of the interconnections <NUM> are provided. The plurality of interconnections <NUM> are arranged in the X-axis direction. The interconnection <NUM> crosses the gate electrodes 38b in the plan view. The material of the interconnection <NUM> is e.g. copper, aluminum, ITO, or the like. Though not illustrated, when the material of the interconnection <NUM> is ITO, the interconnection <NUM> may be provided to cover the entire surface of the conducting layers <NUM>.

The first drive circuit <NUM> and the second drive circuit <NUM> are provided on the first substrate <NUM>. In the example shown in <FIG>, in the plan view, the first drive circuit <NUM> is provided on the negative side in the X-axis direction of the second substrate <NUM>, and the second drive circuit <NUM> is provided on the negative side in the Y-axis direction of the second substrate <NUM>. The drive circuits <NUM>, <NUM> may inject currents in the light emitting layers 42b.

The first drive circuit <NUM> is electrically coupled to the gate electrodes 38b. In the illustrated example, the first drive circuit <NUM> has pads 80a and is electrically coupled to the gate electrodes 38b via wires <NUM> and the pads <NUM>. Further, the first drive circuit <NUM> is electrically coupled to the semiconductor layers <NUM>. In the illustrated example, the first drive circuit <NUM> has pads 80b and is electrically coupled to the semiconductor layers <NUM> via wires <NUM>.

The second drive circuit <NUM> is electrically coupled to the interconnections <NUM>. In the illustrated example, the second drive circuit <NUM> has pads 82a and is electrically coupled to the interconnections <NUM> via wires <NUM> and the pads <NUM>. The materials of the wires <NUM>, <NUM>, <NUM> and the pads <NUM>, <NUM>, 80a, 80b, 82a are not particularly limited as long as the materials have conductivity. For example, the pad <NUM> is integrally provided with the gate electrode 38b. For example, the pad <NUM> is integrally provided with the interconnection <NUM>. Note that, though not illustrated, the drive circuits <NUM>, <NUM> may be formed on the second substrate <NUM>.

The light emitting device <NUM> has e.g. the following features.

The light emitting device <NUM> includes the light emitting units <NUM> having the plurality of nanostructures <NUM> configured to emit light with injection of currents, and the transistors <NUM> provided in correspondence with the light emitting units <NUM> and controlling the amounts of currents injected in the nanostructures <NUM>. Accordingly, in the light emitting device <NUM>, amounts of emitted lights of the light emitting units <NUM> may be controlled. Further, in the light emitting device <NUM>, the transistors <NUM> are controlled, and thereby, times of light emission may be controlled with respect to each light emitting unit <NUM>.

The light emitting device <NUM> includes the base <NUM> and the first semiconductor layers <NUM> provided on the base <NUM>, and the nanostructures <NUM> are columnar portions projecting from the first semiconductor layers <NUM>. Accordingly, in the light emitting device <NUM>, the possibility that dislocation generated due to the difference between the lattice constant of the base <NUM> and the lattice constant of the semiconductor layer <NUM> exists in regions at a fixed height or more of the nanostructures <NUM> may be reduced. Further, the first semiconductor layers <NUM> may function as e.g. cladding layers and suppress leakage of the lights generated in the light emitting units <NUM> toward the base <NUM> side.

In the light emitting device <NUM>, the nanostructure <NUM> has the second semiconductor layer 42a, the third semiconductor layer 42c having the different conductivity type from that of the second semiconductor layer 42a, and the light emitting layer 42b that is provided between the second semiconductor layer 42a and the third semiconductor layer 42c and can emit a light with injection of a current. Accordingly, in the light emitting device <NUM>, the possibility that dislocation generated due to the difference between the lattice constant of the base <NUM> and the lattice constant of the semiconductor layer <NUM> exists in the light emitting layers 42b may be reduced.

In the light emitting device <NUM>, the source regions <NUM> and the drain regions <NUM> are provided in the first semiconductor layers <NUM>. As described above, in the light emitting device <NUM>, the transistors <NUM> and the light emitting units <NUM> may be formed on the same substrate (the single substrate <NUM>). Therefore, in the light emitting device <NUM>, downsizing may be realized compared to the case where the transistors <NUM> and the light emitting units <NUM> are provided on separate substrates.

In the light emitting device <NUM>, the drain regions <NUM> are electrically coupled to the second semiconductor layers 42a. Accordingly, in the light emitting device <NUM>, the amounts of currents injected in the light emitting units <NUM> may be controlled and the amounts of emitted lights of the light emitting units may be controlled by the transistors <NUM>.

In the light emitting device <NUM>, the light emitting units <NUM> have the light propagation layers <NUM> provided between the adjacent nanostructures <NUM> and propagating the lights generated in the light emitting layers 42b. Accordingly, in the light emitting device <NUM>, the lights generated in the light emitting layers 42b may propagate in the in-plane direction (planar direction) of the base <NUM>, be gained in the light emitting layers 42b, and laser-oscillate.

In the light emitting device <NUM>, the first insulating layers <NUM> are provided on the side walls <NUM> of the light emitting units <NUM>. Accordingly, in the light emitting device <NUM>, leakage of the currents injected in the light emitting units <NUM> from the side walls <NUM> may be suppressed by the first insulating layers <NUM>.

In the light emitting device <NUM>, the first semiconductor layer <NUM> is the GaN layer. Accordingly, in the light emitting device <NUM>, when the second semiconductor layer 42a is the GaN layer, stress generated due to the difference between the lattice constant of the first semiconductor layer <NUM> and the lattice constant of the second semiconductor layer <NUM> may be suppressed.

In the light emitting device <NUM>, the light emitting units <NUM> are provided in the array form. Therefore, in the light emitting device <NUM>, a self-emitting imager that may form a picture with the single light emitting unit <NUM> as a pixel may be configured.

In the light emitting device <NUM>, the refractive index of the light propagation layer <NUM> is lower than the refractive index of the light emitting layer 42b. Accordingly, in the light emitting device <NUM>, the light generated in the light emitting layer 42b may readily propagate in the light propagation layer <NUM> in the planar direction.

In the light emitting device <NUM>, the first insulating layers <NUM> are provided to surround the light emitting units <NUM>. Accordingly, in the light emitting device <NUM>, leakage of the currents injected in the light emitting units <NUM> to the interconnections <NUM> may be suppressed more reliably. In the light emitting device <NUM>, the standing wave may be formed between the first side surface 41a and the second side surface 41b of the light emitting unit <NUM> and between the third side surface 41c and the fourth side surface 41d of the light emitting unit <NUM>. Therefore, in the light emitting device <NUM>, laser oscillation may be realized with lower threshold current density.

Note that, in the above description, the InGaN-containing light emitting layer 42b is explained, however, various materials configured to emit light with injection of currents may be used as the light emitting layer 42b. For example, semiconductor materials containing AlGaN, AlGaAs, InGaAs, InGaAsP, InP, GaP, AlGaP, or the like may be used. The semiconductor layers <NUM>, <NUM>, 42a, 42c are not limited to the GaN layers, but formed from materials adapted to the above described materials. The semiconductor layers <NUM>, <NUM>, 42a, 42c may be e.g. InGaN layers, AlGaN layers, AlGaAs layers, InGaAs layers, InGaAsP layers, InP layers, GaP layers, AlGaP layers, or the like.

Further, in the light emitting device <NUM>, the plurality of light emitting layers 42b are not necessarily formed using the same semiconductor materials. For example, the semiconductor materials forming the light emitting layers 42b are varied, and thereby, the light emitting units <NUM> that output red lights, the light emitting units <NUM> that output green lights, and the light emitting units <NUM> that output blue lights may be provided on the same base <NUM>.

Further, in the above description, the form in which the source regions <NUM> and the drain regions <NUM> of the transistors <NUM> are provided in the semiconductor layers <NUM> is explained, however, in the light emitting device according to the embodiment not falling under the invention, the transistors corresponding to the light emitting units may be provided in a drive circuit. Or, the transistors corresponding to the light emitting units may be provided in another base than the base <NUM>.

Next, a manufacturing method of the light emitting device <NUM> according to the first embodiment will be explained with reference to the drawings. <FIG> are sectional views schematically showing a manufacturing process of the light emitting device <NUM> according to the first embodiment.

As shown in <FIG>, the second substrate <NUM> is joined to the first substrate <NUM> using e.g. a joining member (not shown). Then, the semiconductor layer <NUM> and the semiconductor layer <NUM> are epitaxially grown on the second substrate <NUM> in this order. Then, the semiconductor layer <NUM> is patterned and a plurality of opening portions are formed in predetermined locations. Then, the semiconductor layers <NUM> are epitaxially grown in the opening portions, and the element isolation layer <NUM> is epitaxially grown in the other opening portion. The epitaxial growth method includes e.g. an MOCVD (Metal Organic Chemical Vapor Deposition) method and MBE (Molecular Beam Epitaxy) method. The patterning is performed using e.g. photolithography and etching.

As shown in <FIG>, a third insulating layer 43a is formed on the semiconductor layers <NUM>, <NUM> and the element isolation layer <NUM>. The third insulating layer 43a is formed by deposition using e.g. a CVD (Chemical Vapor Deposition) method or sputtering method and patterning using photolithography and etching (hereinafter, also simply referred to as "patterning").

Then, the gate electrodes 38b are formed on the third insulating layer 43a. The gate electrodes 38b are formed by e.g. deposition using a sputtering method or vacuum evaporation method and patterning.

Then, the semiconductor layers 42a, the light emitting layers 42b, and the semiconductor layers 42c are epitaxially grown on the semiconductor layers <NUM> in this order using the third insulating layer 43a as a mask by e.g. the MOCVD method or MBE method. At the step, the nanostructures <NUM> may be formed.

Then, the light propagation layers <NUM> are formed around the nanostructures <NUM>. The light propagation layers <NUM> are formed by e.g. an ELO (Epitaxial Lateral Overgrowth) method including the MOCVD method and the MBE method. At the above described step, the light emitting units <NUM> may be formed. Note that the order of the step of forming the light emitting units <NUM> and the step of forming the gate insulating layers 38a is not particularly limited.

As shown in <FIG>, the first insulating layers <NUM> are formed on the side walls <NUM> of the light emitting units <NUM>. The first insulating layers <NUM> are formed by e.g. deposition of an insulating layer (not shown) on the entire surface of the substrate (the substrate having the semiconductor layers <NUM>, <NUM>, the element isolation layer <NUM>, and the light emitting units <NUM>) and etch back of the insulating layer. At the step, for example, the third insulating layer 43a may be etched, and the third insulating layers <NUM> and the gate insulating layers 38a are formed. As described above, in the manufacturing method of the light emitting device <NUM>, the third insulating layers <NUM> and the gate insulating layers 38a may be formed at the same step, and the manufacturing process may be shortened compared to the case where the third insulating layers <NUM> and the gate insulating layers 38a are formed at separate steps.

As shown in <FIG>, the second insulating layer <NUM> is formed on the semiconductor layers <NUM> and the element isolation layer <NUM> to cover the gates <NUM> and the first insulating layers <NUM>. The second insulating layer <NUM> is formed by e.g. deposition using a spin coating method or CVD method and patterning.

Then, the conducting layers <NUM> are formed on the light emitting units <NUM>. The conducting layers <NUM> are formed by e.g. deposition using a sputtering method or vacuum evaporation method and patterning.

As shown in <FIG> and <FIG>, the interconnections <NUM> are formed on the second insulating layer <NUM> and the conducting layers <NUM>. The interconnections <NUM> are formed by e.g. deposition using a sputtering method or vacuum evaporation method and patterning.

As shown in <FIG>, the drive circuits <NUM>, <NUM> are mounted on the first substrate <NUM> using e.g. joining members (not shown). Then, the electrical couplings are made by the wires <NUM>, <NUM>, <NUM>.

In the above described process, the light emitting device <NUM> may be manufactured.

Next, a light emitting device according to a first modified example useful for understanding the invention will be explained with reference to the drawings. <FIG> is a sectional view schematically showing a light emitting device <NUM> according to the first modified example. Note that, in <FIG>, an X-axis, a Y-axis, and a Z-axis are shown as three axes orthogonal to one another.

As below, in the light emitting device <NUM> according to the first modified example, members having the same functions as the component members of the above described light emitting device <NUM> have the same signs and the detailed explanation thereof will be omitted. This applies to a light emitting device according to a second modified example of the first embodiment useful for understanding the invention.

In the above described light emitting device <NUM>, as shown in <FIG>, the first insulating layer <NUM> is formed by e.g. the single layer. On the other hand, in the light emitting device <NUM>, as shown in <FIG>, the first insulating layer <NUM> is formed by a plurality of layers.

The light emitting device <NUM> may have the same effects as the above described light emitting device <NUM>.

In the light emitting device <NUM>, the first insulating layer <NUM> is formed by the plurality of layers. Accordingly, in the light emitting device <NUM>, for example, compared to the case where the first insulating layer <NUM> is formed by a single layer, the resistance or capacitance of the first insulating layer <NUM> may be easily adjusted.

Next, a light emitting device according to a second modified example useful for understanding the invention will be explained with reference to the drawings. <FIG> is a sectional view schematically showing a light emitting device <NUM> according to the second modified example.

In the above described light emitting device <NUM>, as shown in <FIG>, the single transistor <NUM> is provided in correspondence with the light emitting unit <NUM>. On the other hand, in the light emitting unit <NUM>, as shown in <FIG>, a plurality of the transistors <NUM> are provided in correspondence with the light emitting unit <NUM>. In the illustrated example, the two transistors <NUM> are provided in correspondence with the light emitting unit <NUM>. Note that, though not illustrated, in the light emitting unit <NUM>, the transistors <NUM> in the same number as that of the nanostructures <NUM> may be provided in correspondence with each light emitting unit <NUM>.

The light emitting unit <NUM> may have the the same effects as the above described light emitting device <NUM>.

Next, a light emitting device according to a second embodiment, which is the embodiment of the invention, will be explained with reference to the drawings. <FIG> is a sectional view schematically showing a light emitting device <NUM> according to the second embodiment. Note that, in <FIG>, which will be described later, an X-axis, a Y-axis, and a Z-axis are shown as three axes orthogonal to one another.

As below, in the light emitting device <NUM> according to the second embodiment, members having the same functions as the component members of the above described light emitting device <NUM> have the same signs and the detailed explanation thereof will be omitted.

As shown in <FIG>, the light emitting device <NUM> is different from the above described light emitting device <NUM> in that metal layers <NUM> are provided.

The metal layers <NUM> are provided on surfaces <NUM> of the first insulating layers <NUM>. The metal layer <NUM> is provided in the planar direction of the light emitting layer 42b. In the illustrated example, the metal layer <NUM> is provided between the first insulating layer <NUM> and the second insulating layer <NUM>. The metal layer <NUM> is provided separately from the semiconductor layer <NUM>. In the illustrated example, the third insulating layer <NUM> is located between the metal layer <NUM> and the semiconductor layer <NUM>. The third insulating layer <NUM> electrically isolates between the metal layer <NUM> and the semiconductor layer <NUM>. The metal layer <NUM> is e.g. a silver layer, copper layer, aluminum layer, or the like.

The light emitting device <NUM> includes the metal layers <NUM> provided on the surfaces <NUM> of the first insulating layers <NUM>. Here, though not illustrated, if the metal layer <NUM> is provided directly on the side wall <NUM> of the light emitting unit <NUM>, the metal layer <NUM> absorbs visible light at a predetermined rate. Thus, it is not preferable that the metal layer <NUM> is provided directly on the side wall <NUM>. When the metal layer <NUM> absorbs light, the metal layer <NUM> generates heat and the temperature characteristics of the light emitting device may be deteriorated. In the light emitting device <NUM>, the first insulating layer <NUM> is provided between the light emitting unit <NUM> and the metal layer <NUM>, and the above described problem may be avoided.

Note that, in the light emitting device <NUM>, as shown in <FIG>, the metal layer <NUM> may be integrally provided with the conducting layer <NUM>. In this case, the manufacturing process may be shortened compared to the case where the metal layer <NUM> and the conducting layer <NUM> are formed at separate steps.

Next, a manufacturing method of the light emitting device <NUM> according to the second embodiment will be explained. The manufacturing method of the light emitting device <NUM> according to the embodiment of the invention is basically the same as the manufacturing method of the light emitting device <NUM> according to the above described first embodiment except that the metal layers <NUM> are formed by e.g. deposition using a sputtering method or vacuum evaporation method and patterning. Therefore, the detailed explanation thereof will be omitted.

Next, a light emitting device according to a preferred embodiment will be explained with reference to the drawings. <FIG> is a plan view schematically showing a light emitting device <NUM> according to the preferred embodiment. <FIG> is a sectional view along XVI-XVI line in <FIG> schematically showing the light emitting device <NUM> according to the preferred embodiment. Note that, in <FIG> and <FIG>, an X-axis, a Y-axis, and a Z-axis are shown as three axes orthogonal to one another.

As below, in the light emitting device <NUM> according to preferred embodiment, members having the same functions as the component members of the above described light emitting devices <NUM>, <NUM> have the same signs and the detailed explanation thereof will be omitted.

In the above described light emitting device <NUM>, as shown in <FIG>, the metal layer <NUM> is provided directly on the surface <NUM> of the first insulating layer <NUM>. On the other hand, in the light emitting device <NUM>, as shown in <FIG>, the metal layer <NUM> is provided on the surface <NUM> of the first insulating layer <NUM> via the second insulating layer <NUM>.

As shown in <FIG>, the metal layer <NUM> is coupled to the interconnection <NUM>. In the illustrated example, the metal layer <NUM> is integrally provided with the interconnection <NUM>. The metal layer <NUM> has e.g. a frame-like shape in the plan view. In the plan view, the outer edge of the light emitting unit <NUM> and the outer edge of the conducting layer <NUM> overlap with the metal layer <NUM>.

In the light emitting device <NUM>, the metal layer <NUM> is coupled to the interconnection <NUM> electrically coupled to the third semiconductor layers 42c. Accordingly, in the light emitting device <NUM>, the resistance to the currents injected in the third semiconductor layers 42c may be made smaller.

In the light emitting device <NUM>, the metal layer <NUM> is integrally provided with the interconnection <NUM>. Accordingly, in the light emitting device <NUM>, the manufacturing process may be shortened compared to the case where the metal layer <NUM> and the interconnection <NUM> are formed at separate steps.

Next, a projector according to a preferred embodiment will be explained with reference to the drawings. <FIG> schematically shows a projector <NUM> according to the preferred embodiment. Note that, for convenience, in <FIG>, the housing forming the projector <NUM> is omitted.

The projector <NUM> includes the light emitting device according to the invention. As below, as shown in <FIG>, the projector <NUM> including the light emitting devices <NUM> (light emitting devices 100R, <NUM>, 100B) will be explained.

The projector <NUM> includes a housing (not shown), the light emitting devices 100R, <NUM>, 100B provided in the housing, a cross dichroic prism (color combining means) <NUM>, and a projection lens (projection device) <NUM>. Note that, for convenience, in <FIG>, the housing forming the projector <NUM> is omitted and the light emitting devices 100R, <NUM>, 100B are simplified.

The light emitting devices 100R, <NUM>, 100B output a red light, a green light, and a blue light, respectively. The light emitting devices 100R, <NUM>, 100B control (modulate) the respective light emitting units <NUM> as picture pixels according to image information, and thereby, may directly form a picture without using e.g. liquid crystal light valves (light modulation devices).

The lights output from the light emitting devices 100R, <NUM>, 100B enter the cross dichroic prism <NUM>. The cross dichroic prism <NUM> combines and guide the lights output from the light emitting devices 100R, <NUM>, 100B to the projection lens <NUM>. The projection lens <NUM> enlarges and projects the picture formed by the light emitting devices 100R, <NUM>, 100B on a screen (display surface) (not shown).

Specifically, the cross dichroic prism <NUM> is formed by bonding of four rectangular prisms in which a dielectric multilayer film reflecting the red light and a dielectric multilayer film reflecting the blue light are placed in a cross shape on the inner surfaces. The three color lights are combined by these dielectric multilayer films and a light representing a color image is formed. Then, the combined light is projected on the screen by the projection lens <NUM> as the projection system and the enlarged image is displayed.

The projector <NUM> includes the light emitting devices <NUM>. Accordingly, in the projector <NUM>, a picture may directly be formed without using e.g. liquid crystal light valves (light modulation devices). Therefore, in the projector <NUM>, transmission loss (parts of the lights are not transmitted through the liquid crystal light valves) in the liquid crystal light valves may be suppressed and higher brightness may be realized. Further, in the projector <NUM>, the number of components may be reduced and the lower cost may be realized. Furthermore, in the projector <NUM>, the light emitting devices <NUM> outputting laser beams are provided, and thereby, projection can be performed from a distant location compared to the case where LED (Light Emitting Diode) lights are output.

Note that, for example, when the light emitting device <NUM> in which the light emitting units <NUM> (40R) outputting red lights, light emitting units <NUM> (<NUM>) outputting green lights, and light emitting units <NUM> (40B) outputting blue lights are provided on the same base <NUM> is used, in the projector <NUM>, as shown in <FIG>, the lights output from the light emitting device <NUM> directly enter the projection lens <NUM>, do not enter the cross dichroic prism. In this case, full-color image display can be performed with the single light emitting device <NUM> and downsizing may be realized compared to the example shown in <FIG>.

The usage of the light emitting device according to the invention is not limited to the above described embodiments, but the device can be used as a light source of indoor and outdoor illumination lights, back lights of displays, laser printers, scanners, lights for automobiles, sensing apparatuses using lights, communication apparatuses, etc. in addition to the projector.

Moreover, the invention includes configurations formed by addition of known techniques to the the configurations described in the embodiments.

Claim 1:
A light emitting device (<NUM>) comprising:
a light emitting unit (<NUM>) having a plurality of nanostructures (<NUM>) configured to emit light with injection of currents;
a transistor (<NUM>) provided in correspondence with the light emitting unit (<NUM>) and controlling amounts of the currents injected in the nanostructures (<NUM>);
a conducting layer (<NUM>) through which light emitted from a light emitting layer (42b) is transmitted and output;
an insulating layer (<NUM>) is provided on a side wall (<NUM>) of the light emitting unit (<NUM>); and
a metal layer (<NUM>) provided on a surface (<NUM>) of the insulating layer (<NUM>);
wherein the light emitting device (<NUM>) further comprises:
a base (<NUM>); and
a first semiconductor layer (<NUM>) provided on the base (<NUM>), and
the nanostructures (<NUM>) are columnar portions projecting from the first semiconductor layer (<NUM>);
the nanostructure (<NUM>) further comprises:
a second semiconductor layer (42a);
a third semiconductor layer (42c) having a different conductivity type from that of the second semiconductor layer (42a); and
a light emitting layer (42b) provided between the second semiconductor layer (42a) and the third semiconductor layer (42c) and configured to emit light with injection of a current,
the second semiconductor layer (42a) is provided between the base (<NUM>) and the light emitting layer (42a);
the conducting layer (<NUM>) is electrically coupled to the third semiconductor layer (42c);
the metal layer (<NUM>) is electrically coupled to the conducting layer (<NUM>);
wherein
the light emitting unit (<NUM>) has a light propagation layer (<NUM>) provided between the adjacent nanostructures (<NUM>) and propagating a light generated in the light emitting layer (42b),
wherein the refractive index of the light propagation layer (<NUM>) is lower than the refractive index of the light emitting layer (42b).