Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For 3D memory devices it is quite common to comprise a substrate, a peripheral device disposed on the substrate, a peripheral interconnect layer disposed above the peripheral device, a first source plate disposed above and electrically connected to the peripheral interconnect layer, a first memory stack disposed on the first source plate, a first memory string extending vertically through the first memory stack and in contact with the first source plate, and a first bit line disposed above and electrically connected to the first memory string and the peripheral device. Two of such memory devices are described by the following two US patents. The <CIT> discloses a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The <CIT> discloses a memory device including a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers.

3D memory devices and fabrication methods thereof according to the invention are presented in the independent claims. Embodiments of the invention are presented in the dependent claims.

In one example, a 3D memory device includes a substrate, a peripheral device, comprising a multiplexer, disposed on the substrate, a peripheral interconnect layer disposed above the peripheral device, a first source plate disposed above and electrically connected to the peripheral interconnect layer, a first memory stack disposed on the first source plate, a first memory string extending vertically through the first memory stack and in contact with the first source plate, a first bit line disposed above and electrically connected to the first memory string and the multiplexer of the peripheral device, a second source plate disposed above the first bit line and electrically connected to the peripheral interconnect layer, a second memory stack disposed on the second source plate, a second memory string extending vertically through the second memory stack and in contact with the second source plate, and a second bit line disposed above and electrically connected to the second memory string and the multiplexer of the peripheral device, and wherein the multiplexer is configured to select one of the first and second memory strings.

In a further example, a method for forming a 3D memory device is disclosed. A peripheral device, comprising a multiplexer, is formed on a substrate. A peripheral interconnect layer is formed above the peripheral device. A first source plate is formed above and electrically connected to the peripheral interconnect layer. A first memory string extending vertically through a first memory stack is formed. The first memory string is above and in contact with the first source plate. A first bit line is formed above and electrically connected to the first memory string and the multiplexer of the peripheral device. A second source plate is formed above the first bit line and electrically connected to the peripheral interconnect layer. A second memory string extending vertically through a second memory stack is formed, the second memory string being above and in contact with the second source plate. A second bit line is formed above and electrically connected to the second memory string and the multiplexer of the peripheral device and the multiplexer is configured to select one of the first and second memory strings.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

Various embodiments in accordance with the present disclosure provide 3D memory devices and methods for forming the 3D memory devices with smaller die size, higher cell density, and improved performance compared with some other 3D memory devices. By vertically stacking memory array devices above peripheral devices, the cell density and array efficiency of the resulting 3D memory device can be increased, and the die size and bit cost can be reduced. In some embodiments, 3D memory devices disclosed herein can implement a "multi-memory stack" architecture, which enables continuing scaling of 3D memory devices to further increase cell density and lower bit cost. In some embodiments, a source plate including a conductive plate and a semiconductor plate can be used as the common source of "floating gate" type of NAND memory strings in the same memory stack, thereby reducing the source line resistance.

<FIG> illustrates a cross-section of an exemplary 3D memory device <NUM>, according to some embodiments of the present disclosure. 3D memory device <NUM> represents an example of a monolithic 3D memory device. The term "monolithic" means components of the 3D memory device are formed on a single substrate. 3D memory device <NUM> includes a substrate <NUM>, which can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable materials.

3D memory device <NUM> includes a peripheral device <NUM> on substrate <NUM>. Peripheral device <NUM> can be formed "on" substrate <NUM>, in which the entirety or part of peripheral device <NUM> is formed in substrate <NUM> (e.g., below the top surface of substrate <NUM>) and/or directly on substrate <NUM>. Peripheral device <NUM> can include a plurality of transistors formed on substrate <NUM>. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of the transistors) can be formed in substrate <NUM> as well.

Peripheral device <NUM> can include any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM>. Peripheral device <NUM> includes one or more of a data buffer (e.g., a bit line page buffer), a decoder (e.g., a row decoder or a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors). In some embodiments, peripheral device <NUM> is formed on substrate <NUM> using complementary metal-oxide-semiconductor (CMOS) technology.

Peripheral device <NUM> includes a multiplexer <NUM>. A multiplexer (also known as "MUX") is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. Multiplexer <NUM> is configured to select one of multiple memory strings (or memory stacks) and forward the input from the selected memory string (or memory stack) into a data buffer and/or a driver, such as a bit line page buffer and/or a word line driver. That is, the data buffer and driver of peripheral device <NUM> is shared by multiple memory strings (or memory stacks) through multiplexer <NUM>. The details of sharing peripheral device <NUM> using multiplexer <NUM> will be described below.

3D memory device <NUM> includes an interconnect layer (referred to herein as a "peripheral interconnect layer" <NUM>) above peripheral device <NUM> to transfer electrical signals to and from peripheral device <NUM>. Peripheral interconnect layer <NUM> can include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines <NUM> and vertical interconnect access (via) contacts <NUM>. As used herein, the term "interconnects" can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Peripheral interconnect layer <NUM> can further include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which interconnect lines <NUM> and via contacts <NUM> can form. That is, peripheral interconnect layer <NUM> can include interconnect lines <NUM> and via contacts <NUM> in multiple ILD layers. Interconnect lines <NUM> and via contacts <NUM> in peripheral interconnect layer <NUM> can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in peripheral interconnect layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

3D memory device <NUM> includes one or more memory array devices above peripheral device <NUM> and peripheral interconnect layer <NUM>. It is noted that x and y axes are added in <FIG> to further illustrate the spatial relationship of the components in 3D memory device <NUM>. Substrate <NUM> includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (the lateral direction). As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D memory device <NUM>) is determined relative to the substrate of the semiconductor device (e.g., substrate <NUM>) in the y-direction (the vertical direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing spatial relationship is applied throughout the present disclosure.

In some embodiments, 3D memory device <NUM> is a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings. Each array of NAND memory strings can be formed in a memory stack. As shown in <FIG>, <FIG> memory device <NUM> can include multiple memory array devices stacked vertically above peripheral device <NUM> and peripheral interconnect layer <NUM>. Each memory array device can include a source plate, a memory stack on the source plate, and an array of NAND memory strings each extending vertically through the memory stack and in contact with the source plate. It is understood that in some embodiments, 3D memory device <NUM> includes a single memory array device above peripheral device <NUM> and peripheral interconnect layer <NUM>.

As shown in <FIG>, <FIG> memory device <NUM> includes a first memory array device above peripheral device <NUM> and peripheral interconnect layer <NUM>. The first memory array device includes a first source plate <NUM>, a first memory stack <NUM>, and an array of first NAND memory strings <NUM>. First source plate <NUM> is disposed above and electrically connected to peripheral interconnect layer <NUM>. In some embodiments, first source plate <NUM> includes a conductive plate <NUM> in contact with peripheral interconnect layer <NUM>, e.g., the interconnects in the upper ILD layer of peripheral interconnect layer <NUM>. First source plate <NUM> can further include a semiconductor plate <NUM> disposed on conductive plate <NUM> and in contact with the lower end of first NAND memory strings <NUM>. First source plate <NUM> can function as the common source of array of first NAND memory strings <NUM>. In some embodiments, semiconductor plate <NUM> includes a semiconductor material including, but not limited to silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. Conductive plate <NUM> can reduce the electrical resistance between semiconductor plate <NUM> and peripheral interconnect layer <NUM>. In some embodiments, conductive plate <NUM> includes conductive materials, including metals (e.g., W, Co, Cu, and Al), metal alloys, and metal silicide (e.g., tungsten silicide, cobalt silicide, copper silicide, and aluminum silicide). In one example, semiconductor plate <NUM> includes polysilicon, and conductive plate <NUM> includes tungsten silicide (WSix).

In some embodiments, the first memory array device includes first NAND memory string <NUM> that extends vertically through a plurality of pairs each including a semiconductor layer <NUM> and a dielectric layer <NUM> (referred to herein as "semiconductor/dielectric layer pairs"). The stacked semiconductor/dielectric layer pairs are also referred to herein as first memory stack <NUM>. Interleaved semiconductor layers <NUM> and dielectric layers <NUM> in first memory stack <NUM> alternate in the vertical direction, according to some embodiments. In other words, except the ones at the top or bottom of first memory stack <NUM>, each semiconductor layer <NUM> can be adjoined by two dielectric layers <NUM> on both sides, and each dielectric layer <NUM> can be adjoined by two semiconductor layers <NUM> on both sides. Semiconductor layers <NUM> can each have the same thickness or a different thickness. Similarly, dielectric layers <NUM> can each have the same thickness or a different thickness. Semiconductor layers <NUM> can include semiconductor materials, such as polysilicon. Dielectric layers <NUM> can include dielectric materials, such as silicon oxide.

<FIG> illustrates a cross-section of an exemplary NAND memory string <NUM> having floating gates <NUM>, according to some embodiments of the present disclosure. NAND memory string <NUM> is one example of first NAND memory string <NUM> illustrated in <FIG>. NAND memory string <NUM> can include a dielectric filling layer <NUM>, a semiconductor channel <NUM>, a tunneling layer <NUM>, floating gates <NUM>, and a blocking layer <NUM>. In some embodiments, dielectric filling layer <NUM> includes silicon oxide, and semiconductor channel <NUM> includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, tunneling layer <NUM> includes silicon oxide, silicon oxynitride, or a combination thereof. Floating gates <NUM> can include semiconductor materials, such as polysilicon. Blocking layer <NUM> can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. NAND memory string <NUM> can have a cylinder shape (e.g., a pillar shape). Dielectric filling layer <NUM>, semiconductor channel <NUM>, tunneling layer <NUM>, floating gates <NUM>, and blocking layer <NUM> are arranged along the radial direction from the center toward the outer surface of the pillar in this order, according to some embodiments.

NAND memory string <NUM> can also include multiple control gates <NUM> and gate dielectrics <NUM>. Control gates <NUM> can be parts of semiconductor layers <NUM> illustrated in <FIG> that abut first NAND memory string <NUM>. Control gates <NUM> thus can include semiconductor materials, such as polysilicon. In some embodiments, control gates <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. Gate dielectrics <NUM> can be parts of dielectric layers <NUM> illustrated in <FIG> that abut first NAND memory string <NUM>. Gate dielectrics <NUM> thus can include dielectric materials, such as silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof.

Referring back to <FIG>, it is understood that first NAND memory strings <NUM> are not limited to the "floating gate" type of NAND memory strings (e.g., NAND memory strings <NUM>), and first memory stack <NUM> is not limited to the "semiconductor/dielectric layer pairs" type of memory stack. In some embodiments, first memory stack <NUM> includes a plurality of pairs each including a conductor layer <NUM> and dielectric layer <NUM> (referred to herein as "conductor/dielectric layer pairs"). Interleaved conductor layers <NUM> and dielectric layers <NUM> in first memory stack <NUM> alternate in the vertical direction, according to some embodiments. In other words, except the ones at the top or bottom of first memory stack <NUM>, each conductor layer <NUM> can be adjoined by two dielectric layers <NUM> on both sides, and each dielectric layer <NUM> can be adjoined by two conductor layers <NUM> on both sides. Conductor layers <NUM> can each have the same thickness or a different thickness. Similarly, dielectric layers <NUM> can each have the same thickness or a different thickness. Conductor layers <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. Dielectric layers <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

In some embodiments, each first NAND memory string <NUM> is a "charge trap" type of NAND memory string, which includes a semiconductor channel and a composite dielectric layer (also known as a "memory film"). In some embodiments, the semiconductor channel includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, the composite dielectric layer includes a tunneling layer, a storage layer (also known as "charge trap layer"), and a blocking layer. Each first NAND memory string <NUM> can have a cylinder shape (e.g., a pillar shape). The semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are arranged along the radial direction from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, the blocking layer can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO). In another example, the blocking layer can include a high-k dielectric layer, such as an aluminum oxide (Al<NUM>O<NUM>), or hafnium oxide (HfO<NUM>) or tantalum oxide (Ta<NUM>O<NUM>) layer, and so on.

In some embodiments, first NAND memory strings <NUM> further include a plurality of control gates (each being part of a word line). Each conductor layer or semiconductor layer <NUM> in first memory stack <NUM> can act as a control gate for each memory cell of first NAND memory string <NUM>. Each first NAND memory string <NUM> can include a source select gate at its lower end and a drain select gate at its upper end. As used herein, the "upper end" of a component (e.g., first NAND memory string <NUM>) is the end farther away from substrate <NUM> in the y-direction, and the "lower end" of the component (e.g., first NAND memory string <NUM>) is the end closer to substrate <NUM> in the y-direction. As shown in <FIG>, array of first NAND memory strings <NUM> can share a common source, i.e., first source plate <NUM>, by contacting the respective lower end with semiconductor plate <NUM>.

3D memory device <NUM> further includes a first bit line <NUM> disposed above and electrically connected to first NAND memory string <NUM> and peripheral device <NUM>. In some embodiments, the drain at the upper end of first NAND memory string <NUM> is electrically connected to first bit line <NUM> through a first bit line contact <NUM>. First bit line contact <NUM> and first bit line <NUM> can include conductive materials, such as W, Co, Cu, and Al, formed in one or more ILD layers above first memory stack <NUM>. First bit line <NUM> is electrically connected to peripheral device <NUM>, such as multiplexer <NUM>, through the interconnects in peripheral interconnect layer <NUM>. As a result, first NAND memory string <NUM> is one of the inputs of multiplexer <NUM> through first bit line <NUM>.

As described above, 3D memory device <NUM> includes multiple memory array devices stacked vertically, such as a second memory array device stacked above the first memory array device. The second memory array device includes a second source plate <NUM> disposed above first bit line <NUM> and electrically connected to peripheral interconnect layer <NUM>, a second memory stack <NUM> disposed on second source plate <NUM>, and an array of second NAND memory strings <NUM> each extending vertically through second memory stack <NUM> and in contact with second source plate <NUM>.

Similar to the counterparts in the first memory array device, second source plate <NUM> can include a conductive plate <NUM> electrically connected to (not shown) peripheral interconnect layer <NUM>, and a semiconductor plate <NUM> disposed on conductive plate <NUM> and in contact with the lower end of second NAND memory string <NUM>. Second source plate <NUM> can function as the common source of array of second NAND memory strings <NUM>. In some embodiments, semiconductor plate <NUM> includes a semiconductor material including, but not limited to silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, conductive plate <NUM> includes conductive materials, including metals (e.g., W, Co, Cu, and Al) and metal silicide (e.g., tungsten silicide, cobalt silicide, copper silicide, and aluminum silicide). In one example, semiconductor plate <NUM> includes polysilicon, and conductive plate <NUM> includes tungsten silicide (WSix).

Similar to the counterparts in the first memory array device, second memory stack <NUM> can include a plurality of semiconductor/dielectric layer pairs or a plurality of conductor/dielectric layer pairs, and second NAND memory string <NUM> can be a "floating gate" type of NAND memory string or a "charge trap" type of NAND memory string as described above in detail. Nevertheless, 3D memory device <NUM> can also include a second bit line <NUM> disposed above and electrically connected to second NAND memory string <NUM> and peripheral device <NUM>. In some embodiments, the drain at the upper end of second NAND memory string <NUM> is electrically connected to second bit line <NUM>. Second bit line <NUM> is electrically connected to peripheral device <NUM>, such as multiplexer <NUM>, through the interconnects in peripheral interconnect layer <NUM>. As a result, second NAND memory string <NUM> is another input of multiplexer <NUM> through second bit line <NUM>. Multiplexer <NUM> thus is configured to select one of first NAND memory string(s) <NUM> in the first memory array device and second NAND memory string(s) <NUM> in the second memory array device. First NAND memory string(s) <NUM> in the first memory array device and second NAND memory string(s) <NUM> in the second memory array device can share the same data buffer (e.g., the bit line page buffer) and/or driver (e.g., the word line driver) in peripheral device <NUM> by multiplexer <NUM>.

As shown in <FIG>, in some embodiments, 3D memory device <NUM> further includes a third memory array device including a third source plate <NUM> disposed above second bit line <NUM> and electrically connected to peripheral interconnect layer <NUM>, a third memory stack <NUM> disposed on third source plate <NUM>, and an array of third NAND memory strings <NUM> each extending vertically through third memory stack <NUM> and in contact with third source plate <NUM>. Third source plate <NUM> can include a conductive plate <NUM> electrically connected to (not shown) peripheral interconnect layer <NUM>, and a semiconductor plate <NUM> disposed on conductive plate <NUM> and in contact with the lower end of third NAND memory string <NUM>. Third source plate <NUM>, third memory stack <NUM>, and third NAND memory strings <NUM> are similar to their counterparts in the first and second memory array devices and thus, will not be repeated.

3D memory device <NUM> can further include a third bit line <NUM> disposed above and electrically connected to third NAND memory string <NUM> and peripheral device <NUM>. Third bit line <NUM> can be electrically connected to peripheral device <NUM>, such as multiplexer <NUM>, through the interconnects in peripheral interconnect layer <NUM>. As a result, third NAND memory string <NUM> can be still another input of multiplexer <NUM> through third bit line <NUM>. Multiplexer <NUM> thus can be configured to select one of first NAND memory string(s) <NUM> in the first memory array device, second NAND memory string(s) <NUM> in the second memory array device, and third NAND memory string(s) <NUM> in the third memory array device. First NAND memory string(s) <NUM> in the first memory array device, second NAND memory string(s) <NUM> in the second memory array device, and third NAND memory string(s) <NUM> in the third memory array device can share the same data buffer (e.g., the bit line page buffer) and/or driver (e.g., the word line driver) in peripheral device <NUM> by multiplexer <NUM>.

It is understood that the number of memory array devices is not limited by the example shown in <FIG> and can be n, where n is any positive integer. Although not shown, it is also understood that each of the n memory array devices can include any suitable additional components, such as gate line slits (GLSs) and other local contacts, such as word line contacts, the detail of which can be readily appreciated and thus, is not described herein.

<FIG> illustrate an exemplary fabrication process for forming a 3D memory device, according to some embodiments of the present disclosure. <FIG> is a flowchart of an exemplary method for forming a 3D memory device, according to some embodiments of the present disclosure. Examples of the 3D memory device depicted in <FIG> and <FIG> include 3D memory device <NUM> depicted in <FIG>. <FIG> and <NUM> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which a peripheral device is formed on a substrate. The substrate can be a silicon substrate. Operation <NUM> includes forming a multiplexer configured to select one of multiple memory strings, and forming a data buffer and a driver shared by the multiple memory strings through the multiplexer. As illustrated in <FIG>, a peripheral device <NUM> is formed on a silicon substrate <NUM>. Peripheral device <NUM> can include a plurality of transistors formed on silicon substrate <NUM>. The transistors can be formed by a plurality of processes including, but not limited to, photolithography, dry and/or wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions are formed in silicon substrate <NUM> by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of the transistors. In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate <NUM> by dry and/or wet etching and thin film deposition. The transistors of peripheral device <NUM> can form a variety types of circuits, such as a multiplexer <NUM>, a data buffer (not shown), and a driver (not shown).

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a peripheral interconnect layer is formed above the peripheral device. The peripheral interconnect layer can include a plurality of interconnects in one or more ILD layers. As illustrated in <FIG>, a peripheral interconnect layer <NUM> can be formed on silicon substrate <NUM> and above peripheral device <NUM>. Peripheral interconnect layer <NUM> can include interconnects, including interconnect lines <NUM> and via contacts <NUM> of MEOL and/or BEOL in a plurality of ILD layers, to make electrical connections with peripheral device <NUM>.

In some embodiments, peripheral interconnect layer <NUM> includes multiple ILD layers and interconnects therein formed in multiple processes. For example, interconnect lines <NUM> and via contacts <NUM> can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. Fabrication processes to form interconnect lines <NUM> and via contacts <NUM> can also include photolithography, CMP, dry and/or wet etching, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in <FIG> can be collectively referred to as an "interconnect layer" (e.g., peripheral interconnect layer <NUM>).

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first source plate is formed above and electrically connected to the peripheral interconnect layer. Operation <NUM> can include forming a conductive plate in contact with the peripheral interconnect layer, and forming a semiconductor plate on the conductive plate. In some embodiments, the conductive plate includes metal silicide, and the semiconductor plate includes polysilicon.

As illustrated in <FIG>, a first source plate <NUM> including a conductive plate <NUM> and a semiconductor plate <NUM> is formed on the top surface of peripheral interconnect layer <NUM>. The conductive materials in conductive plate <NUM> can include, but not limited to, metals, metal alloys, and metal silicides. In some embodiments, conductive plate <NUM> includes one or more metals, such as Cu, Co, Al, nickel (Ni), titanium (Ti), W, or any other suitable metals. In some embodiments, conductive plate <NUM> includes one or more metal alloys, each of which is an alloy of at least two of Cu, Co, Ni, Ti, W (e.g., TiNi alloy or a combination of TiNi alloy and TiW alloy), or any other suitable metal alloys. In some embodiments, conductive plate <NUM> includes one or more metal silicides, such as copper silicide, cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, or any other suitable metal silicides.

Conductive plate <NUM> can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Depending on the conductive materials in conductive plate <NUM>, the deposition of conductive plate <NUM> may involve multiple processes. In some embodiments, the deposition of a metal silicide conductive film involves deposition of a silicon film, deposition of a metal film, and silicidation of the silicon and metal films by a thermal treatment (e.g., annealing, sintering, or any other suitable processes).

As illustrated in <FIG>, semiconductor plate <NUM> can be formed on conductive plate <NUM>. Semiconductor plate <NUM> can include semiconductor materials including, but not limited to, silicon, such as amorphous silicon or polysilicon. Semiconductor plate <NUM> can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. In one example, first source plate <NUM> is formed by first depositing a tungsten film, then depositing a polysilicon film on the tungsten film, followed by silicidation of the polysilicon and tungsten films by a thermal treatment (e.g., annealing, sintering, or any other suitable processes). As a result, conductive plate <NUM> can be made from tungsten silicide, and semiconductor plate <NUM> can be made from polysilicon.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first memory string extending vertically through a first memory stack is formed. The first memory string can be above and in contact with the first source plate. In some embodiments, the first memory stack is formed by depositing interleaved polysilicon layers and silicon oxide layers.

As illustrated in <FIG>, interleaved polysilicon layers <NUM> and silicon oxide layers <NUM> are formed on semiconductor plate <NUM> of first source plate <NUM>. Interleaved polysilicon layers <NUM> and silicon oxide layers <NUM> can form a memory stack <NUM>. In some embodiments, polysilicon layers <NUM> can each have the same thickness or a different thickness. Similarly, silicon oxide layers <NUM> can each have the same thickness or a different thickness. Memory stack <NUM> can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

As illustrated in <FIG>, first source plate <NUM> is patterned by photolithography and etching processes to remove part that is above peripheral device <NUM> for interconnections between peripheral device <NUM> and memory array device(s). Memory stack <NUM> can also be patterned by the "trim-etch" processes to form one or more staircase structures <NUM> on the side(s) in the lateral direction for word line fan-out. As illustrated in <FIG>, openings (channel holes) <NUM> are etched through interleaved polysilicon layers <NUM> and silicon oxide layers <NUM> in memory stack <NUM> by wet etching and/or dry etching. In some embodiments, channel holes <NUM> are etched using deep reactive-ion etching (DRIE).

As illustrated in <FIG>, first NAND memory strings <NUM> are formed through memory stack <NUM> by depositing various layers into channel holes <NUM> (as shown in <FIG>). In some embodiments, fabrication processes to form first NAND memory string <NUM> include forming a plurality of lateral recesses to leave space for floating gates by wet etching and/dry etching of parts of silicon oxide layers <NUM> that abut channel holes <NUM>. In some embodiments, fabrication processes to form first NAND memory string <NUM> further include forming a blocking layer, floating gates, a tunneling layer, a semiconductor channel, and a dielectric filling layer by subsequently depositing, for example, a silicon oxide layer, a polysilicon layer, a silicon oxide layer, a polysilicon layer, and a silicon oxide layer using one or more thin film deposition processes, such as PVD, CVD, ALD, or any combination thereof.

It is understood that in some embodiments in which memory stack <NUM> includes a plurality of conductor/dielectric layer pairs and first NAND memory string <NUM> is a "charge trap" type of NAND memory string, different fabrication processes are used. For example, a dielectric stack including interleaved sacrificial layers (e.g., silicon nitride layers) and dielectric layers (e.g., silicon oxide layers) can be first deposited on first source plate <NUM>. "Charge trap" type of NAND memory string can be formed through the dielectric stack by first etching a channel hole extending vertically through the dielectric stack, followed by subsequently depositing a memory film (e.g., including a tunneling layer, a storage layer, and a blocking layer) and a semiconductor channel into the channel hole. A memory stack including interleaved conductor layers (e.g., tungsten layers) and dielectric layers (e.g., silicon oxide layers) then can be formed using the "gate replacement" processes, i.e., replacing the sacrificial layers in the dielectric stack with the conductor layers through slits extending vertically through the dielectric stack.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first bit line is formed above and electrically connected to the first memory string and the peripheral device. As illustrated in <FIG>, first bit line contact <NUM> is formed through one or more ILD layers and in contact with the upper end of first NAND memory string <NUM>, such that first bit line contact <NUM> is electrically connected to first NAND memory string <NUM>. First bit line <NUM> then can be formed through the one or more ILD layers and in contact with both first bit line contact <NUM> and the interconnects in peripheral interconnect layer <NUM>, such that first NAND memory string <NUM> is electrically connected to peripheral device <NUM>, such as multiplexer <NUM>.

In some embodiments, fabrication processes to form first bit line contact <NUM> and first bit line <NUM> include forming openings (e.g., via holes or trenches) using dry etching and/or wet etching, followed by filling the openings with conductive materials and other materials (e.g., a barrier layer, an adhesion layer, and/or a seed layer) for conductor filling, adhesion, and/or other purposes. First bit line contact <NUM> and first bit line <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The openings of first bit line contact <NUM> and first bit line <NUM> can be filled with conductive materials and other materials by ALD, CVD, PVD, electroplating, any other suitable processes, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second source plate is formed above the first bit line and electrically connected to the peripheral interconnect layer. Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second memory string extending vertically through a second memory stack is formed. The second memory string can be above and in contact with the second source plate. Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second bit line is formed above and electrically connected to the second memory string and the peripheral device.

As illustrated in <FIG>, a second source plate <NUM> including a conductive plate <NUM> and a semiconductor plate <NUM> is formed above first bit line <NUM> and electrically connected to (not shown) peripheral interconnect layer <NUM>. A second NAND memory string <NUM> extending vertically through a second memory stack <NUM> can be formed. Second NAND memory string <NUM> can be above and in contact with second source plate <NUM>. A second bit line <NUM> can be formed above and electrically connected to second NAND memory string <NUM> and peripheral device <NUM>, such as multiplexer <NUM>. The fabrication details of second source plate <NUM>, second memory stack <NUM>, second NAND memory string <NUM>, and second bit line <NUM> are similar to their counterparts in the first memory array device and thus, are not repeated. It is understood that similar fabrication processes can be used to form additional memory array device(s) stacked vertically above the second memory array device.

According to one aspect of the present disclosure, a 3D memory device includes a substrate, a peripheral device, comprising a multiplexer, disposed on the substrate, a peripheral interconnect layer disposed above the peripheral device, a first source plate disposed above and electrically connected to the peripheral interconnect layer, a first memory stack disposed on the first source plate, a first memory string extending vertically through the first memory stack and in contact with the first source plate, a first bit line disposed above and electrically connected to the first memory string and the multiplexer of the peripheral device, a second source plate disposed above the first bit line and electrically connected to the peripheral interconnect layer, a second memory stack disposed on the second source plate, a second memory string extending vertically through the second memory stack and in contact with the second source plate, and a second bit line disposed above and electrically connected to the second memory string and the multiplexer of the peripheral device, and wherein the multiplexer is configured to select one of the first and second memory strings.

In some embodiments, the first source plate includes a conductive plate in contact with the peripheral interconnect layer, and a semiconductor plate disposed on the conductive plate and in contact with a lower end of the first memory string. The conductive plate can include metal silicide, and the semiconductor plate can include polysilicon.

In some embodiments, the first memory stack includes interleaved polysilicon layers and silicon oxide layers. In some embodiments, the first memory string includes a plurality of floating gates.

In some embodiments, the second source plate includes a conductive plate in contact with the peripheral interconnect layer, and a semiconductor plate disposed on the conductive plate and in contact with a lower end of a respective first or second memory string. The conductive plate can include metal silicide, and the semiconductor plate can include polysilicon.

According to still another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A peripheral device, comprising a multiplexer, is formed on a substrate. A peripheral interconnect layer is formed above the peripheral device. A first source plate is formed above and electrically connected to the peripheral interconnect layer. A first memory string extending vertically through a first memory stack is formed. The first memory string is above and in contact with the first source plate. A first bit line is formed above and electrically connected to the first memory string and the multiplexer of the peripheral device. A second source plate is formed above the first bit line and electrically connected to the peripheral interconnect layer. A second memory string extending vertically through a second memory stack is formed, the second memory string being above and in contact with the second source plate. A second bit line is formed above and electrically connected to the second memory string and the multiplexer of the peripheral device and the multiplexer is configured to select one of the first and second memory strings.

In some embodiments, to form the first source plate, a conductive plate is formed in contact with the peripheral interconnect layer, and a semiconductor plate is formed on the conductive plate and in contact with a lower end of the first memory string. The conductive plate can include metal silicide, and the semiconductor plate can include polysilicon.

In some embodiments, to form the peripheral device, a data buffer and a driver shared by the first and second memory strings through the multiplexer are formed.

In some embodiments, the first memory stack is formed by depositing interleaved polysilicon layers and silicon oxide layers. In some embodiments, to form the first memory string, a plurality of floating gates are formed.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Claim 1:
A three-dimensional (3D) memory device (<NUM>), comprising:
a substrate (<NUM>);
a peripheral device (<NUM>), comprising a sense amplifier and a multiplexer (<NUM>), disposed on the substrate (<NUM>);
a peripheral interconnect layer (<NUM>) disposed above the peripheral device (<NUM>);
a first source plate (<NUM>) disposed above and electrically connected to the peripheral interconnect layer (<NUM>);
a first memory stack (<NUM>) disposed on the first source plate (<NUM>);
a first memory string (<NUM>) extending vertically through the first memory stack (<NUM>) and in contact with the first source plate (<NUM>); and
a first bit line (<NUM>) disposed above and electrically connected to the first memory string (<NUM>) and to the multiplexer (<NUM>) of the peripheral device (<NUM>);
a second source plate (<NUM>) disposed above the first bit line (<NUM>) and electrically connected to the peripheral interconnect layer (<NUM>);
a second memory stack (<NUM>) disposed on the second source plate (<NUM>);
a second memory string (<NUM>) extending vertically through the second memory stack (<NUM>) and in contact with the second source plate (<NUM>); and
a second bit line (<NUM>) disposed above and electrically connected to the second memory string (<NUM>) and to the multiplexer (<NUM>) of the peripheral device (<NUM>), and wherein the multiplexer (<NUM>) is configured to select one of the first and second memory strings (<NUM>, <NUM>),
and wherein the peripheral device (<NUM>) further comprises a data buffer and/or a driver, with the data buffer and/or the driver being shared by the first and second memory strings (<NUM>, <NUM>) through the multiplexer (<NUM>).