Patent Description:
The technology of the disclosure relates generally to side channel attack mitigation in a processor, and specifically to the mitigation of side channel attacks on return stack buffers based on branch behavior in the processor.

Processors may execute complex programs, which may include numerous changes in the execution flow of the code. Conventionally, these changes in execution flow may be accomplished through the use of varying types of branch instructions. Some of the branch instructions may be unconditional (meaning that their behavior is always the same). Other branch instructions may be conditional (meaning that they may or may not cause branching, based on some condition). Because modern processors are conventionally pipelined, it is important to accurately predict the direction of the execution of a program, so that the needed younger instructions in the resolved instruction flow path following the conditional branch instruction can be fetched ahead of time from a memory system. In this manner, the pipeline does not have to be stalled until the conditional branch instruction is executed and its condition actually resolved. If the needed younger instructions are not already in a cache of the processor, where they can be quickly accessed, the processor may need to stall until they have been retrieved, which compromises performance.

In an effort to predict the direction of execution of a program in which branch instructions are involved, processors conventionally employ one or more branch predictors. The function of a branch predictor is to attempt to predict the direction of one or more branch instructions, in which a branch (e.g., change to instruction flow) may be unconditional (e.g., always taken) or conditional (e.g., taken only if a condition is met). The branch predictor attempts to predict the direction to be taken so that the processor may fetch instructions in the predicted instruction flow path based on the prediction, and speculatively process those instructions. The processing is speculative because the branch prediction may turn out to be incorrect. Where the prediction is incorrect, the processor will take corrective action, such as flushing the incorrect speculatively processed instructions out of the pipeline and retrieving the correct instructions in the resolved instruction flow path before proceeding with further processing of such instructions.

Certain security attacks have been developed to take advantage of the relationship between the branch instructions and the behaviors of branch predictors. Branch predictors conventionally base their predictions on recent instruction flow. One security attack involves "training" a branch predictor using one software context, such that the predictor will make predictions in another software context based on that training. These predictions may cause privileged code to be speculatively executed and information can be obtained from the speculative activity. In order to combat these kinds of attacks, some processor architectures have adopted requirements that the branch predictor must be context-aware (i.e., predictions made in one context may not be allowed to influence predictions in another context). For some types of branch predictors which operate based on tag lookups, this requirement may be met by simply including context information with the tag. However, some types of branch predictors (e.g., return stack buffers, which track function calls and returns) do not conventionally include a tag lookup, and thus it is impractical to address these kind of attacks simply by adding context information to them, as doing so would involve management and storage of an impractical amount of additional information (and resultant silicon area). Thus, a solution that addresses decoupling software context from such branch predictors while remaining efficient from an information and physical design perspective would be desirable.

<CIT> discloses apparatuses and methods relating to mitigations for speculative execution side channels. It discloses preventing the branch predictor to predict the target instruction when a transition to a more privileged predictor mode has taken place.

Aspects disclosed in the detailed description include mitigation of return stack buffer side channel attacks in a processor. In response to a software function call in a processed fetched instruction, the processor stores a return address indicator in a first entry of a return stack buffer. The return address indicator points to (i.e., "indicates") a predicted next instruction (e.g., next sequential instruction in a sequence of instructions) to which execution is predicted to return after the function call. In exemplary aspects, a call exception level indication indicating an exception level associated with the return address of the function call is also stored. Detecting a side channel attack or a fault in a return from a function call in the processor includes receiving a return exception level indication indicating the exception level associated with a return from the function call and comparing the exception level associated with the return to the stored exception level associated with the return address. The return exception level indicator is received in conjunction with a return indication. The processor accesses the first entry of the return stack buffer, which indicates the return address of the function call, and also accesses an exception level associated with the return address. The processor then compares the exception level associated with the return address to the exception level associated with the return. When the exception level associated with the return address matches the exception level associated with the return, the return address is used in a prediction of instruction flow (e.g., to determine instructions to be fetched for speculative execution). When the exception level associated with the return address does not match the exception level associated with the return, the return address is not used in the prediction of instruction flow.

In this regard, in one exemplary aspect, a processing circuit in a processor is disclosed. The processing circuit is configured to receive a return indication indicating a return from a function call; receive a return exception level indication indicating an exception level associated with the return; access a first entry of a return stack buffer comprising a return address indication indicating a return address; access a call exception level indication indicating an exception level associated with the return address; compare the exception level associated with the return to the exception level associated with the return address; and in response to the exception level associated with the return matching the exception level associated with the return address, use the return address for a prediction of instruction flow.

In another exemplary aspect, a method of returning from a function call in a processing circuit in a processor is disclosed. The method comprises receiving a return indication indicating a return from a function call; receiving a return exception level indication indicating an exception level associated with the return; accessing a first entry of a return stack buffer comprising a return address indication indicating a return address; accessing a call exception level indication indicating an exception level associated with the return address; comparing the exception level associated with the return to the exception level associated with the return address; and in response to the exception level associated with the return matching the exception level associated with the return address, using the return address for a prediction of instruction flow.

In another exemplary aspect, a non-transitory computer-readable medium comprising instructions which, when executed by a processor, cause the processor to receive a return indication indicating a return from a function call; receive a return exception level indication indicating an exception level associated with the return; access a first entry of a return stack buffer comprising a return address indication indicating a return address; access a call exception level indication indicating an exception level associated with the return address; compare the exception level associated with the return to the exception level associated with the return address; and in response to the exception level associated with the return matching the exception level associated with the return address, use the return address for a prediction of instruction flow.

In another exemplary aspect, a processing circuit in a processor is disclosed. The processing circuit comprises a means for receiving a return indication indicating a return from a function call; a means for receiving a return exception level indication indicating an exception level associated with the return; a means for accessing a first entry of a return stack buffer comprising a return address indication indicating a return address; a means for accessing a call exception level indication indicating an exception level associated with the return address; a means for comparing the exception level associated with the return to the exception level associated with the return address; and a means for using the return address for a prediction of instruction flow in response to the exception level associated with the return matching the exception level associated with the return address.

Aspects disclosed in the detailed description also include a return stack buffer comprising a plurality of entries, each entry having a return address portion and an exception level portion. The return stack buffer is configured to receive a return from a function call having an associated exception level and compare the exception level associated with a return with an exception level stored in a current entry of the return stack buffer. The return stack buffer is further configured to use the current entry for prediction if the exception level associated with the return matches the exception level stored in the current entry, and not to use the current entry for prediction if the exception level associated with the return does not match the exception level stored in the current entry.

Before discussing examples of mitigating return stack buffer side channel attacks in a processor starting at <FIG>, an exemplary processor <NUM> in a processor-based system <NUM> is first discussed below with regard to <FIG>.

In this regard, <FIG> is a diagram of an exemplary processor <NUM> that is part of a processor-based system <NUM>. The processor <NUM> may be an in-order or an out-of-order processor (OoP) as non-limiting examples. The processor <NUM> includes an instruction processing circuit <NUM> that includes an instruction fetch circuit <NUM> configured to fetch instructions <NUM> from an instruction memory <NUM>. The instruction memory <NUM> may be provided in or as part of a system memory in the processor-based system <NUM> as an example. The instruction fetch circuit <NUM> in this example is configured to provide the fetched instructions 108F to be decoded in a decode circuit <NUM> to generate decoded instruction 108D that are executed in an execution circuit <NUM>. A produced value 108E generated by the execution circuit <NUM> from executing the decoded instruction 108D is committed (i.e., written back) to a storage location indicated by the destination of the decoded instruction 108D. This storage location could be memory <NUM> in the processor-based system <NUM> or a physical register P<NUM>-PX in a physical register file (PRF) <NUM>, as examples.

With continuing reference to <FIG>, once fetched instructions 108F are decoded into decoded instructions 108D, the decoded instructions 108D are provided to a rename / allocate circuit <NUM> in the instruction processing circuit <NUM>. The rename / allocate circuit <NUM> is configured to determine if any register names in the decoded instructions 108D need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing.

The processor <NUM> also includes a speculative prediction circuit <NUM> that is configured to speculatively predict a value associated with an operation in the processor <NUM>. In an example, the speculative prediction circuit <NUM> is configured to predict a condition of a conditional control instruction <NUM>, such as a conditional branch instruction, that will govern in which instruction flow path next instructions <NUM> are fetched by the instruction fetch circuit <NUM> for processing. For example, if the conditional control instruction <NUM> is a conditional branch instruction, the speculative prediction circuit <NUM> can predict whether a condition of the conditional branch instruction <NUM> will be later resolved in the execution circuit <NUM> as either "taken" or "not taken. " The speculative prediction circuit <NUM> makes a prediction of the instruction flow based on information including, for example, a prediction history indicator <NUM>.

The instruction flow in the processor <NUM> includes executing a user application, functions, an operating system, etc., that can have different restrictions and privileges. In some examples, exception levels are used to identify a privilege level that indicates a level of authority, for example, of a program, which may determine what information and functions are available to the program. Security levels are another type of indicator that can be used to distinguish privilege or access limits of a program. A function call is an instruction in a calling program to call a function program to perform a particular function. In some examples, functions are called by a user application to execute privileged code that accesses data that is off limits to the user application. When the function program is complete, operation can return to the calling program. In response to the CALL instruction, the instructions of the function are fetched and executed. Typically, the last instruction in a function is a RETURN instruction that tells the speculative prediction circuit that instruction execution may return back to the calling program and resume at the next instruction after the CALL in the calling program. That next instruction is located at a memory address referred to as a return address <NUM>. A return may be enabled by saving the return address <NUM> in response to the CALL instruction and retrieving the return address <NUM> in response to the RETURN instruction. In one example, the return address <NUM> is saved by "pushing" (i.e., storing) the return address on a return stack buffer <NUM> in response to the CALL instruction, and "popping" (i.e., reading) the return address <NUM> off the return stack buffer <NUM> in response to the RETURN instruction. In another example, the return address <NUM> may be stored in a storage location (e.g., a register that holds the most recent return address). In a RETURN situation, the speculative prediction circuit <NUM> makes a prediction of instruction flow based on the return address <NUM> and other information, such as the prediction history indicator <NUM>. The prediction of instruction flow will be used to determine the next instructions <NUM> that will be fetched by the instruction fetch circuit <NUM>.

Attacks on processor-based systems have been developed to recognize predictive behavior and manipulate instruction flow based on the recognized predictive behavior. Such manipulation can expose sensitive data or make the processor-based system vulnerable to external control. The return address <NUM> stored in the return stack buffer <NUM> has been the focus of malicious attacks to alter the direction of instruction flow for purposes of obtaining information and gaining control of a processor. The return stack buffer <NUM> includes features for mitigating such attacks, as described in further detail with reference to <FIG>.

An exemplary return stack buffer circuit <NUM> ("return stack buffer <NUM>") used in a processing circuit <NUM> configured to mitigate such attacks is shown in <FIG> and described below. <FIG> is a block diagram of the processing circuit <NUM> including the return stack buffer <NUM>. The return stack buffer <NUM> comprises an array <NUM> of entries <NUM> coupled to a management block <NUM>. The management block <NUM> (MGMT. BLOCK in <FIG>) comprises hardware circuits. In this regard, the management block <NUM> may also be referred to herein as the management circuit <NUM>. The array <NUM> of entries <NUM> comprises a first entry <NUM>(<NUM>), a second entry <NUM>(<NUM>), and a third entry <NUM>(N). Although only three entries <NUM> are shown, the array <NUM> of entries <NUM> may comprise any number of entries <NUM> based on, for example, a maximum number of nested function calls supported in the processing circuit <NUM> or limitations on storage resources in the processing system <NUM>. The entries <NUM>(<NUM>)-<NUM>(N) comprise return address portions <NUM>(<NUM>)a, <NUM>(<NUM>)a, and <NUM>(N)a, respectively, and exception level portions <NUM>(<NUM>)b, <NUM>(<NUM>)b, and <NUM>(N)b, respectively. The management block <NUM> includes circuitry for controlling operations in the return stack buffer <NUM>, including reading and writing to the entries <NUM>, and further operations of the return stack buffer <NUM> as described below.

The return stack buffer <NUM> receives a call indication <NUM> indicating a function call, a return address indication <NUM>, and a call exception level indication <NUM>. Specifically, the management block <NUM> receives the call indication <NUM> in response to a CALL instruction being executed in a calling program, such as a user application. The management block <NUM> controls the return stack buffer <NUM> to respond to the call indication <NUM>, which includes storing the return address indication <NUM> in the return address portion <NUM>(<NUM>)a of the entry <NUM>(<NUM>) and storing the call exception level indication <NUM> in the exception level portion <NUM>(<NUM>)b of the entry <NUM>(<NUM>). The return stack buffer <NUM> may be implemented as a stack, such as a Last-In-First-Out (LIFO) buffer, that stores return address indications <NUM> of nested function calls in the order in which the functions are called, with the return address indication <NUM> of the most recent function call in one of the array <NUM> of entries <NUM> corresponding to the "top" of the array <NUM>.

The return address indication <NUM> and the call exception level indication <NUM> are received in conjunction with (e.g., simultaneous with or immediately before or after, and associated with) receiving the call indication <NUM>. The call indication <NUM> indicates that the return address indication <NUM> and the call exception level indication <NUM> are to be stored in the return stack buffer <NUM> until a corresponding return indication is received.

The return address indication <NUM> may comprise a return address <NUM>, comprising a memory address of a predicted next instruction. The term predicted next instruction refers to an instruction predicted to be executed next after a return from the function call. The predicted next instruction may be an instruction stored in a next sequential memory location adjacent to a memory location storing the function call instruction. Alternatively, the return address indication <NUM> may comprise an indication of a storage location <NUM>, such as a register or other storage location in which the return address <NUM> of the next predicted instruction is stored. In this regard, the return address indication <NUM> may be a direct indicator of the return address or an indirect indicator of the return address.

The call exception level indication <NUM> may comprise a value indicating an exception level <NUM> associated with the return address <NUM>. The exception level <NUM> corresponds to an application, program, or instruction stream that included the function call (e.g., called the function). As an example, a user application may have a different exception level <NUM> than an operating system. Alternatively, the call exception level indication <NUM> may comprise an indication of a storage location <NUM>, which may be a register or other storage location in which the exception level <NUM> is stored. In this regard, the call exception level indication <NUM> may be a direct indication or an indirect indication of the exception level <NUM> associated with the return address <NUM>.

The return stack buffer <NUM> keeps the return address indication <NUM> and the call exception level indication <NUM> stored in one of the entries <NUM> of the array <NUM> until the function call is completed, or they are no longer useful. To indicate the function is complete, the return stack buffer <NUM> receives a return indication <NUM>, indicating a return from a function call. The return stack buffer <NUM> responds to a return indication <NUM> by reading the "top" entry <NUM> from the return stack buffer <NUM>, which is also known as "popping" the entry <NUM> off the stack. In response to the return indication <NUM>, the return stack buffer <NUM> accesses the entry <NUM> in the return stack buffer <NUM> and accesses the call exception level indication <NUM>. As an example, accessing the entry <NUM> in response to a return indication <NUM> includes reading the return address indication <NUM> from the return address portion <NUM>(<NUM>)a of the first entry <NUM>(<NUM>), and reading the call exception level indication <NUM> from the exception level portion <NUM>(<NUM>)b of the first entry <NUM>(<NUM>). Reading the return address indication <NUM> includes either reading the return address <NUM> from the first entry <NUM>(<NUM>) or reading an indication of the storage location <NUM> in which the return address <NUM> is stored. In the latter case, accessing the return address indication <NUM> would further include accessing the storage location <NUM> to read the return address <NUM>.

Accessing the call exception level indication <NUM> includes reading the exception level <NUM> associated with the return address <NUM> from the first entry <NUM>(<NUM>) (e.g., from the exception level portion <NUM>(<NUM>)b) or reading, from the first entry <NUM>(<NUM>), an indication of the storage location <NUM> in which the exception level <NUM> associated with the return address <NUM> is stored. In the latter case, accessing the call exception level indication <NUM> may further include accessing the storage location <NUM> to read the exception level <NUM> associated with the return address <NUM>.

The entries <NUM> in the return stack buffer <NUM> may no longer be useful in the case of a software context change because, for example, the return indications <NUM> corresponding to the entries <NUM> in the return stack buffer <NUM> never occur, or the entries <NUM> of the return stack buffer <NUM> are overwritten by new function calls in the new software context before returning back to the previous software context.

In conjunction with receiving the return indication <NUM>, the return stack buffer <NUM> also receives a return exception level indication <NUM> indicating an exception level <NUM> associated with the return. For example, when a function is called, an exception level <NUM> associated with the return address <NUM>, which is based on the calling application, program, or function, may be forwarded to the function. In some examples, the function stores the exception level <NUM> provided in association with the function call and returns the exception level <NUM> as the exception level <NUM> associated with the return from the function call. In this regard, the exception level <NUM> associated with the return should match the exception level <NUM> associated with the return address <NUM>. In an exemplary aspect, the return stack buffer <NUM> compares the exception level <NUM> associated with the return to the exception level <NUM> associated with the return address <NUM>. Based on the comparison, the processing circuit <NUM> makes a prediction of instruction flow to determine a next instruction to be fetched for speculative execution. In some examples, a speculative prediction circuit <NUM> as shown in <FIG> makes a prediction of instruction flow and an instruction is fetched for speculative execution based on the prediction. In response to the exception level <NUM> associated with the return matching the exception level <NUM> associated with the return address <NUM>, the processing circuit <NUM> may use the return address <NUM> for a prediction of instruction flow. On the other hand, in response to the exception level <NUM> associated with the return not matching the exception level <NUM> associated with the return address <NUM>, the processing circuit <NUM> will not use the return address <NUM> for the prediction of instruction flow.

The management block <NUM> monitors software context changes as described with reference to <FIG> and may initiate corrective action in the return stack buffer <NUM> if the context change was not related to the exception level. For example, the management block <NUM> may be configured to detect an address space identifier (ASID) or virtual machine identifier (VMID) change in software context, and to initiate a flush of the return stack buffer <NUM> in response to such a software context change. In response to the exception level <NUM> associated with the return not matching the exception level <NUM> associated with the return address <NUM>, the processing circuit <NUM> may generate a signal indicating a mismatch (e.g., return fault), which may indicate that a return stack buffer side channel attack has been attempted or an error has occurred. Instead of or in addition to generating a signal indicating a return fault, the management block may initiate corrective action.

In this regard, <FIG> is a block diagram of a method <NUM> of mitigating side channel attacks on a return stack buffer. The method <NUM> includes receiving a return indication <NUM> indicating a return from a function call (block <NUM>) and receiving a return exception level indication <NUM> indicating an exception level <NUM> associated with the return (block <NUM>). The method includes accessing a first entry <NUM>(<NUM>) of a return stack buffer <NUM> comprising a return address indication <NUM> indicating a return address <NUM> (block <NUM>) and accessing a call exception level indication <NUM> indicating an exception level <NUM> associated with the return address <NUM> (block <NUM>). The method further includes comparing the exception level <NUM> associated with the return to the exception level <NUM> associated with the return address <NUM> (block <NUM>) and, in response to the exception level <NUM> associated with the return matching the exception level <NUM> associated with the return address <NUM>, using the return address <NUM> for a prediction of instruction flow (block <NUM>). The method may further include, in response to the exception level <NUM> associated with the return not matching the exception level <NUM> associated with the return address <NUM>, not using the return address <NUM> for the prediction of instruction flow (block <NUM>). The method may further include, in response to the exception level <NUM> associated with the return not matching the exception level associated with the return address <NUM>, at least one of generating a signal indicating the mismatch and initiating corrective action (block <NUM>).

In this regard, <FIG> illustrates an example of a processor-based system <NUM> that can mitigate return stack buffer side channel attacks. In this example, the processor-based system <NUM> includes a processor <NUM> including a cache <NUM>. The processor <NUM> corresponds to the processing circuit <NUM> in <FIG>, which includes the return stack buffer <NUM> to mitigate return stack buffer side channel attacks. The processor <NUM> is coupled to a system bus <NUM> and can communicate with other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the processor <NUM> can communicate bus transaction requests to a memory controller <NUM> in a memory system <NUM>. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus <NUM> constitutes a different fabric.

Other devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include one or more input devices <NUM>, one or more output devices <NUM>, one or more network interface devices <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) <NUM> can be any devices configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) <NUM> can be configured to support any type of communications protocol desired. The memory system <NUM> can include the memory controller <NUM> coupled to one or more memory array <NUM>.

The processor <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display controller(s) <NUM> sends information to the display(s) <NUM> to be displayed via one or more video processors <NUM>, which process the information to be displayed into a format suitable for the display(s) <NUM>. The display(s) <NUM> can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc..

The exemplary processing circuit <NUM> configured to mitigate return stack buffer side channel attacks according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a server, a computer, a portable computer, a desktop computer, a mobile computing device, a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system.

It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

In another exemplary aspect, an apparatus is provided that includes a return stack buffer comprising a plurality of entries, each entry having a return address portion and an exception level portion. The return stack buffer is configured to receive a return from a function call having an associated exception level and compare the exception level associated with a return with an exception level stored in a current entry of the return stack buffer. The return stack buffer is further configured to, in response to the exception level associated with the return matching the exception level stored in the current entry of the return stack buffer, use the current entry for prediction. The return stack buffer is further configured to, in response to the exception level associated with the return not matching the exception level stored in the current entry of the return stack buffer, not use the current entry for prediction.

In another exemplary aspect, a method is provided that includes, on a function call, storing a return address associated with the function call and an exception level associated with that return address in an entry of a return stack buffer. The method also comprises receiving a return from a function call having an associated exception level. The method also comprises comparing the exception level associated with the return with the exception level stored in a current entry of the return stack buffer. The method also comprises, in response to the exception level associated with the return matching the exception level stored in the current entry of the return stack buffer, using the current entry for prediction. The method also comprises, in response to the exception level associated with the return not matching the exception level stored in the current entry of the return stack buffer, not using the current entry for prediction.

Claim 1:
A processor (<NUM>) including an instruction processing circuit (<NUM>, <NUM>), the processing circuit (<NUM>, <NUM>) configured to:
receive a return indication (<NUM>) indicating a return from a function call;
receive a return exception level indication (<NUM>) indicating an exception level (<NUM>) associated with the return;
access a first entry (<NUM>(<NUM>)) of a return stack buffer (<NUM>) comprising a return address indication (<NUM>) indicating a return address (<NUM>);
access a call exception level indication (<NUM>) indicating an exception level (<NUM>) associated with the return address (<NUM>);
compare the exception level (<NUM>) associated with the return to the exception level (<NUM>) associated with the return address (<NUM>); and
in response to the exception level (<NUM>) associated with the return matching the exception level (<NUM>) associated with the return address (<NUM>), use the return address (<NUM>) for a prediction of instruction flow.