Patent Description:
In order to ensure the continued miniaturization and multi-functionality of electronic products and communication devices, it is desired that semiconductor packages be small in size, support multi-pin connection, operate at high speeds, and have high functionality.

In such semiconductor packages, the integrated circuit chips incorporated therein may be subject to disturbance by electromagnetic interference (EMI). EMI may cause the semiconductor packages to exhibit abnormal operation and poor performance. To shield the semiconductor package from EMI, a metal shielding layer is embedded in an encapsulant of the semiconductor package. However, once fabrication is complicated, package thickness is increased, package warpage may occur, and the shielding layer may become delaminated when the shielding layer is embedded in the structure of the semiconductor package.

Another approach to EMI shielding is to coat a metal on the surface of the encapsulant of the semiconductor package. However, since the metal is typically formed after a singulation process, the package structure is not suitable for mass production.

Semiconductor package structures comprising a layer providing EMI shielding and electrically connected to conductive structures arranged on an uppermost surface of an underlying substrate are known from <CIT>, <CIT>, and <CIT>. A further semiconductor package is known from <CIT>. Said document discloses, in details, the following features:
A semiconductor package structure, comprising:.

Thus, a novel semiconductor package structure is desirable.

Semiconductor package structures and a method for forming a semiconductor package structure according to aspects of the invention are respectively defined in the appended independent claims <NUM>, <NUM> and <NUM>.

An exemplary semiconductor package structure not falling under the scope defined in the claims but useful for the understanding thereof includes an encapsulating layer and a package substrate having a device region covered by the encapsulating layer and an edge region surrounding the device region and exposed from the encapsulating layer. The package substrate includes an insulating layer and a first patterned conductive layer in a first layer-level of the insulating layer. The package substrate includes a plurality of first conductors in and along the edge region. The edge region is partially exposed from the plurality of first conductors, as viewed from a top-view perspective. A semiconductor die is disposed on the device region of the package substrate and surrounded by the encapsulating layer. A conductive shielding layer covers and surrounds the encapsulating layer and electrically connected to the plurality of first conductors.

Another exemplary semiconductor package structure not falling under the scope defined in the claims but useful for the understanding thereof includes an encapsulating layer and a package substrate having a device region covered by the encapsulating layer and an edge region surrounding the device region and exposed from the encapsulating layer. The package substrate includes an insulating layer and a first patterned conductive layer in a first layer-level of the insulating layer. The first patterned conductive layer includes a conductive continuous layer in and extending along the edge region. A semiconductor die is disposed on the device region of the package substrate and surrounded by the encapsulating layer. A conductive shielding layer covers and surrounds the encapsulating layer and is electrically connected to the conductive continuous layer.

An exemplary method for forming a semiconductor package structure not falling under the scope defined in the claims but useful for the understanding thereof includes providing a package substrate having a scribe line region and a plurality of device regions defined by the scribe line region. The package substrate includes an insulating layer and a first patterned conductive layer in a first layer-level of the insulating layer. The first patterned conductive layer includes a plurality of first conductors in and along the scribe line region. The scribe line region is partially exposed from the plurality of first conductors, as viewed from a top-view perspective. A semiconductor die is mounted onto each of the plurality of device regions of the package substrate. The package substrate is covered with an encapsulating material. An opening is formed in the encapsulating material to expose the scribe line region of the package substrate and form a plurality of encapsulating layers corresponding to the plurality of device regions. A conductive shielding layer is formed on the plurality of encapsulating layers and fills the opening, so as to be electrically connected to the plurality of first conductors.

The scope of the invention is determined by reference to the appended claims.

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure <NUM> not falling under the scope defined in the claims but useful for the understanding thereof. <FIG>, <FIG> are plan views of various arrangements of first conductors in the semiconductor package structure <NUM> in accordance with some examples. In some embodiments, the semiconductor package structure <NUM> is a wafer-level semiconductor package structure, for example, a flip-chip semiconductor package structure.

Referring to <FIG>, the semiconductor package structure <NUM> may be mounted on a base (not shown). In some embodiments, the semiconductor package structure <NUM> may include a system-on-chip (SOC) package structure. Moreover, the base may include a printed circuit board (PCB) and may be formed of polypropylene (PP). In some embodiments, the semiconductor package structure <NUM> is mounted on the base by a bonding process. For example, the semiconductor package structure <NUM> may include a conductive bump structure (not shown), such as a copper bump or a solder bump structure, a conductive pillar structure, a conductive wire structure, or a conductive paste structure that may be mounted on and electrically coupled to the base by the bonding process.

The semiconductor package structure <NUM> includes a package substrate <NUM> having a device region 100b and an edge region 100a' surrounding the device region 100b. Moreover, the package substrate <NUM> has a first surface 101a and a second surface 101b opposite to the first surface 101a.

In some embodiments, the package substrate <NUM> includes a redistribution layer (RDL) structure (which is also referred to as a fan-out structure) therein. The package substrate <NUM> includes an insulating layer <NUM> (e.g., an inter-metal dielectric (IMD) layer) and one or more patterned conductive layers serving as conductive traces and disposed in the insulating layer <NUM>. For example, a first conductive patterned layer <NUM> is disposed in a first layer-level of the insulating layer <NUM>. Moreover, a second conductive patterned layer <NUM> is disposed in a second layer-level of the insulating layer <NUM> lower than the first layer-level. A third conductive patterned layer <NUM> is disposed in a third layer-level of the insulating layer <NUM> lower than the second layer-level and a fourth conductive patterned layer <NUM> is disposed in a fourth layer-level of the insulating layer <NUM> lower than the third layer-level. Those conductive patterned layer may be formed of metal. In some embodiments, the insulating layer <NUM> (i.e., the IMD layer) may include sub-dielectric layers successively stacked from the second surface 101b of the package substrate <NUM> toward the first surface 101a of the package substrate <NUM>. In some embodiments, the insulating layer <NUM> may be formed of organic materials, which include a polymer base material, non-organic materials, which include silicon nitride (SiNX), silicon oxide (SiOX), or the like. For example, those sub-dielectric layers are made of a polymer base material. In some embodiments, the insulating layer <NUM> is a high-k dielectric layer (k is the dielectric constant of the dielectric layer). It should be noted that the number of patterned conductive layers and the number of sub-dielectric layers of the package substrate <NUM> shown in <FIG> is only an example and is not a limitation to the present invention.

In some examples not falling under the scope defined in the claims but useful for the understanding thereof, the first patterned conductive patterned layer <NUM> is in the uppermost layer-level of the insulating layer <NUM> and adjacent to the first surface 101a, so that the first patterned conductive patterned layer <NUM> has a top surface that is substantially level with the first surface 101a. The first patterned conductive patterned layer <NUM> may include a plurality of first conductors 102a disposed in and along the edge region 100a' of the package substrate <NUM>. Moreover, the edge region 100a' is partially exposed from the plurality of first conductors 102a, as viewed from a top-view perspective.

For example, as shown in 2A, the first conductors 102a are L-shaped metal layers that are arranged at corners of the edge region 100a' and spaced apart from each other. Alternatively, the first conductors 102a spaced apart from each other are bar-shaped metal layers that are arranged at four sides of the edge region 100a' and the edge region 100a' corresponding to corners of the device region 100b are exposed from the bar-shaped metal layers, as viewed from a top-view perspective.

In some examples, as shown in <FIG>, the first conductors 102a of the first patterned conductive layer <NUM> are metal vias that are spaced apart from each other and the edge region 100a' corresponding to corners of the device region 100b are exposed from the metal vias (i.e., the first conductors 102a), as viewed from a top-view perspective.

In some examples, as shown in <FIG>, the first patterned conductive patterned layer <NUM> in the uppermost layer-level of the insulating layer <NUM> and adjacent to the first surface 101a includes a conductive continuous layer 102a' (e.g., a metal ring) in and extending along the edge region 100a', so as to surround the device region 100b without exposing the edge region 100a' corresponding to corners of the device region 100b, as viewed from a top-view perspective.

The semiconductor package structure <NUM> further includes one or more semiconductor devices mounted onto the first surface 101a of the package substrate <NUM> and corresponding to the device region 100b of the package substrate <NUM>. The semiconductor devices include a semiconductor die <NUM> and <NUM> that is disposed on the first surface <NUM> of the package substrate <NUM>. In some embodiments, the semiconductor die <NUM> or <NUM> may include a microcontroller (MCU), a microprocessor (MPU), a random access memory (RAM), a base-band device, an artificial intelligence processing unit(APU), a power management integrated circuit (PMIC), a flash memory, a global positioning system (GPS) device, or a radio frequency (RF) device or any combination thereof. In some embodiments, at least one of the semiconductor dies <NUM> and <NUM> is a SOC die. For example, the semiconductor dies <NUM> and <NUM> are SOC dies. Alternatively, the semiconductor die <NUM> is a SOC die, and the semiconductor die <NUM> is a memory die. In some other embodiments, the semiconductor die <NUM> is a SOC die, and the semiconductor die <NUM> is a base-band die. However, the number and the arrangement of semiconductor dies are not limited to the disclosed embodiment.

In some embodiments, the semiconductor dies <NUM> and <NUM> are electrically connected to the package substrate <NUM>. As shown in <FIG>, the semiconductor dies <NUM> and <NUM> are fabricated by flip-chip technology. The semiconductor dies <NUM> and <NUM> includes pads (not shown) are in contact with the corresponding conductive structures <NUM> and <NUM> (for example, conductive bumps, posts or solder pastes), respectively. It should be noted that the number of semiconductor dies integrated in the semiconductor package structure <NUM> is not limited to that disclosed in the embodiment. The pads of the semiconductor dies <NUM> and <NUM> are mounted onto the first patterned conductive layer <NUM> of the package substrate <NUM> via conductive structures <NUM> and <NUM>, respectively.

In some embodiments, the semiconductor package structure <NUM> further includes one or more electronic components <NUM> mounted onto the first surface 101a of the package substrate <NUM> and corresponding to the device region 100b of the package substrate <NUM>. In some embodiments, the electronic component <NUM> may include a passive device that is electrically coupled to the semiconductor die <NUM> or <NUM> through the conductive traces of the package substrate <NUM>. In some embodiments, the passive device includes a capacitor, an inductor, a resistor, or a combination thereof. Moreover, the passive device includes at least one electrode <NUM> electrically coupled to the first conductive patterned layer <NUM>. For example, the passive device may be a capacitor that includes electrode layers <NUM> respectively electrically coupled to the semiconductor die <NUM> through the first patterned conductive layer <NUM> of the package substrate <NUM>.

The semiconductor package structure <NUM> further includes an encapsulating layer 130a, covering the first surface 101a of the package substrate <NUM>, corresponding to the device region 100b of the package substrate <NUM>, and surrounding the semiconductor dies <NUM> and <NUM> and the electronic component <NUM>. In some embodiments, the encapsulating layer 130a may be formed of a molding compound layer, such as an epoxy, a resin, a moldable polymer, or the like. In some embodiments, an optional underfill material (not shown) is disposed in the gaps between the conductive structures <NUM> and <NUM> and surrounded by the encapsulating layer 130a.

The semiconductor package structure <NUM> further includes a conductive shielding layer <NUM>, such as a metal layer, covering and surrounding the encapsulating layer 130a and electrically connected to the first conductors 102a shown in <FIG> and <FIG> (or the conductive continuous layer 102a, as shown in <FIG>), so as to serve as an EMI shielding layer. In such cases, the first conductors 102a or the conductive continuous layer 102a are connected to ground and have a top surface in direct contact with the conductive shielding layer <NUM>. In some embodiments, the top surface of the first conductors 102a or of the conductive continuous layer 102a is substantially level with the first surface 101a of the package substrate <NUM>, so that the sidewalls 101c of the package substrate <NUM> are entirely exposed from the conductive shielding layer <NUM>, as shown in <FIG>. Namely, the sidewalls 101c of the package substrate <NUM> are not covered by the conductive shielding layer <NUM>. Alternatively, the first patterned conductive layer <NUM> having first conductors 102a or a conductive continuous layer 102a is embedded in a layer-level of the insulating layer <NUM> below the first surface 101a, so that the conductive shielding layer <NUM> extends to and the covers the sidewalls of the package substrate <NUM> above the top surface of the first conductors 102a or the conductive continuous layer 102a.

In some other examples, the first patterned conductive layer <NUM> does not have the first conductors 102a or the conductive continuous layer 102a and one of the second and third patterned conductive layers <NUM> and <NUM> has conductors or a conductive continuous layer with a structure and arrangement that are similar to those of the first conductors 102a or the conductive continuous layer 102a. Similarly, the conductors or the conductive continuous layer also has a top surface in direct contact with the conductive shielding layer <NUM>, so that the conductive shielding layer <NUM> extends to and the covers sidewalls of the package substrate <NUM> above the top surface of those conductors.

In some embodiments, the encapsulating layer 130a has tapered sidewalls <NUM>. Moreover, portions of the conductive shielding layer <NUM> that surround the tapered sidewalls <NUM> of the encapsulating layer 130a have sidewalls <NUM> tilted with respect to sidewalls 101c of the package substrate <NUM>, as shown in <FIG>.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure <NUM> in accordance with some examples not falling under the scope defined in the claims but useful for the understanding thereof. <FIG> respectively show plan views of arrangements of first conductors and second conductors in the semiconductor package structure <NUM> in accordance with some examples. <FIG> respectively show plan views of arrangements of first conductors and second conductors in the semiconductor package structure <NUM> in accordance with some examples. Descriptions of elements of the examples hereinafter that are the same as or similar to those previously described with reference to <FIG>, <FIG> are omitted for brevity. Referring to <FIG>, the semiconductor package structure <NUM> is similar to the semiconductor package structure <NUM> shown in <FIG>. Unlike the semiconductor package structure <NUM> shown in <FIG>, the second patterned conductive layer <NUM> of the semiconductor package structure <NUM> includes second conductors 104a disposed in and along the edge region 100a' of the package substrate <NUM>. Moreover, the second conductors 104a are staggered with the first conductors 102a, as viewed from a top-view perspective.

In some examples, as shown in <FIG>, the first conductors 102a of the first patterned conductive layer <NUM> are bar-shaped metal layers that are spaced apart from each other and the edge region 100a' corresponding to corners of the device region 100b are exposed from the bar-shaped metal layers (i.e., the first conductors 102a), as viewed from a top-view perspective. Moreover, the second conductors 104a of the second patterned conductive layer <NUM> include bar-shaped and L-shaped metal layers that are spaced apart from each other and located at the edge region 100a' exposed from the first conductors 102a, as viewed from a top-view perspective. As a result, the second conductors 104a are staggered with the first conductors 102a, as viewed from a top-view perspective. It should be noted that, although the first and second conductors 102a and 104a have a staggered arrangement, the first conductors 102a may partially overlap with the second conductors 104a, as viewed from a top-view perspective.

Alternatively, the first conductors 102a are arranged the same way as the second conductors 104a shown in <FIG>. In this embodiment, the second conductors 104a are arranged the same way as the first conductors 102a shown in <FIG>.

In some other examples, the second patterned conductive layer <NUM> includes a conductive continuous layer (e.g., a metal ring) in and extending along the edge region 100a', so as to surround the device region 100b without exposing the edge region 100a' corresponding to corners of the device region 100b, as viewed from a top-view perspective. In such cases, the first conductors 102a are arranged as shown in <FIG>, or in the same way as the second conductors 104a shown in <FIG>.

In some examples, as shown in <FIG>, the first conductors 102a of the first patterned conductive layer <NUM> and the second conductors 104a of the second patterned conductive layer <NUM> are metal vias that are spaced apart from each other. As shown in FIS. 5A and 5B, the arrangements of the first conductors 102a and the second conductors 104a may be similar to those of the first conductors 102a and the second conductors 104a shown in <FIG>, so that the second conductors 104a are staggered with the first conductors 102a, as viewed from a top-view perspective. Alternatively, the first conductors 102a are arranged the same way as the second conductors 104a shown in <FIG>. In this case, the second conductors 104a are arranged the same way as the first conductors 102a shown in <FIG>.

Although it is not shown in <FIG>, similar to the first conductors 102a, the second conductors 104a has a top surface in direct contact with the conductive shielding layer <NUM>, so that the conductive shielding layer <NUM> also covers sidewalls 101c of the package substrate <NUM> above the top surface of the second conductors 104a. Moreover, the first conductors 102a or the second conductors 104a may be connected to ground.

<FIG> are cross-sectional views of an exemplary method for forming the semiconductor package structure <NUM> shown in <FIG>, in accordance with some examples not falling under the scope defined in the claims but useful for the understanding thereof. Descriptions of elements of the examples hereinafter that are the same as or similar to those previously described with reference to <FIG> and <FIG> are omitted for brevity. Referring to <FIG>, a package substrate <NUM> is provided. The package substrate <NUM> has a first surface 101a and a second surface 101b opposite to the first surface 101a. Moreover, the package substrate <NUM> has a scribe line region 100a and device regions 100b defined by the scribe line region 100a, so that those device regions 100b are surrounded by the scribe line region 100a. In order to simplify the diagram, only one entire device region 100b and two adjacent and partial device regions 100b are depicted.

The package substrate <NUM> includes an insulating layer <NUM> (e.g., an inter-metal dielectric (IMD) layer). In some examples, a first conductive patterned layer <NUM>, a second conductive patterned layer <NUM>, a third conductive patterned layer <NUM>, and a fourth conductive patterned layer <NUM> are respectively disposed in a first layer-level, a second layer-level, a third layer-level, and a fourth layer-level of the insulating layer <NUM>. It should be noted that the number of patterned conductive layers shown in <FIG> is only an example and is not a limitation to the present invention.

The first conductive patterned layer <NUM> may include first conductors 102a disposed in and along the scribe line region 100a or include a conductive continuous layer (not shown) in and extending along the scribe line region 100a. The first conductors 102a may bridge the first conductive patterned layers <NUM> disposed in adjacent device regions 100b of the package substrate <NUM>.

For a single device region 100b of the package substrate <NUM>, the shape, the structure, and the arrangement of the first conductors 102a in the scribe line region 100a are the same as or similar to those of the first conductors 102a in the edge region 100a' shown in <FIG> or <FIG>. As a result, the scribe line region 100a is partially exposed from the first conductors 102a, as viewed from a top-view perspective. The exposed scribe line region 100a (e.g., the portions of the scribe line region 100a corresponding to corners of each device region 100b) may serve as a buffer region for stress release.

Also, the shape, the structure, and the arrangement of the conductive continuous layer are the same as or similar to those of the conductive continuous layer 102a' in the edge region 100a' shown in <FIG>.

Referring to <FIG>, one or more semiconductor devices such as semiconductor dies <NUM> and <NUM>, and one or more electronic components <NUM> such as passive devices are mounted onto each device region 100b of the package substrate <NUM> by one or more bonding processes.

Afterwards, as shown in <FIG>, the package substrate <NUM> having the semiconductor dies <NUM> and <NUM> and the electronic component <NUM> thereon is covered with an encapsulating material <NUM>. In some examples, the encapsulating material <NUM> may be formed of a molding compound layer, such as an epoxy, a resin, a moldable polymer, or the like, and formed by a molded underfill (MUF) process. The encapsulating material <NUM> may be applied while it is substantially liquid, and then may be cured through a chemical reaction, such as in an epoxy or resin. In some other examples, the encapsulating material <NUM> may be an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid capable of being disposed around the first semiconductor die <NUM>, and then may be cured through a UV or thermal curing process. The encapsulating material <NUM> may be cured with a mold (not shown). In some examples, the encapsulating material <NUM> may be formed by a capillary underfill (CUF) process, so that an underfill material (not shown) is disposed in the gaps between the conductive structures <NUM> of the semiconductor die <NUM> and the conductive structures <NUM> of the semiconductor die <NUM> and surrounded by the encapsulating material <NUM>.

Referring to <FIG>, an opening <NUM> is formed in the encapsulating material <NUM> to expose the scribe line region 100a of the package substrate <NUM>, thereby separating the encapsulating material <NUM> into encapsulating layers 130a that correspond to the device regions 100b and are spaced apart from each other. In some examples, the opening <NUM> is formed by a laser ablation process, so that the formed encapsulating layer 130a has tapered sidewalls <NUM>. After the encapsulating material <NUM> is formed, the opening <NUM> has a bottom that is substantially level with the first surface 101a of the package substrate <NUM> or the interface between the package substrate <NUM> and the encapsulating layer 130a, so that the first conductors 102a or the conductive continuous layer in the scribe line region 100a of the package substrate <NUM> are also exposed by the opening <NUM>.

In some examples, the first patterned conductive layer <NUM> having first conductors 102a or a conductive continuous layer is embedded in a layer-level of the insulating layer <NUM> below the first surface 101a. In such cases, the opening <NUM> that is formed may extend into the insulating layer <NUM>, thereby exposing the first conductors 102a or the conductive continuous layer.

Referring to <FIG>, after the opening <NUM> is formed, a conductive shielding layer <NUM>, such as a metal layer (e.g., copper or stainless steel), is formed on the encapsulating layers 130a and conformally fills the opening <NUM> by, for example, a sputtering process, so as to be electrically connected to the first conductors 102a or the conductive continuous layer exposed by the opening <NUM>. The conductive shielding layer <NUM> may be in direct contact with the top surface of the first conductors 102a or the conductive continuous layer through the opening <NUM>, so as to serve as an EMI shielding layer.

Afterwards, a singulation process is performed by cutting the scribe line region 100a of the package substrate <NUM> through the opening <NUM>, so as to form semiconductor package structures <NUM> (as shown in <FIG>). In some examples, a conductive bump structure (not shown), such as a copper bump or a solder bump structure, a conductive pillar structure, a conductive wire structure, or a conductive paste structure may be formed on the second surface 101b of the package substrate <NUM> prior to the singulation process.

It should be understood that the methods for forming the semiconductor package structure <NUM> shown in <FIG> can be the same as or similar to the methods shown in <FIG>. In the fabrication of the semiconductor package structure <NUM>, the second patterned conductive layer <NUM> in the package substrate <NUM> may include second conductors 104a in and along the scribe line region 100a. The second conductors 104a are staggered with the first conductors 102a, as viewed from a top-view perspective. For example, for a single device region 100b of the package substrate <NUM>, the shape, the structure, and the arrangement of the first conductors 102a in the scribe line region 100a are the same as or similar to those of the first conductors 102a in the edge region 100a' shown in <FIG> and the shape, the structure, and the arrangement of the second conductors 104a in the scribe line region 100a are the same as or similar to those of the second conductors 104a in the edge region 100a' shown in <FIG>. As a result, the scribe line region 100a is partially exposed from the first conductors 102a, as viewed from a top-view perspective. For example, the scribe line region 100a corresponding to corners of each device region 100b is exposed from the corresponding first conductors 102a, as viewed from a top-view perspective. In some embodiments, the second conductors 104a may serve as a reflect layer or a resist layer during performing a laser ablation process that is used for forming the opening in the encapsulating material and extending into the package substrate <NUM>, so as to expose the second conductors 104a.

Alternatively, the shape, the structure, and the arrangement of the first conductors 102a in the scribe line region 100a are the same as or similar to those of the first conductors 102a in the edge region 100a' shown in <FIG> and the shape, the structure, and the arrangement of the second conductors 104a in the scribe line region 100a are the same as or similar to those of the second conductors 104a in the edge region 100a' shown in <FIG>.

In the fabrication of the semiconductor package structure <NUM>, the opening formed in the encapsulating material extends into the insulating layer <NUM>, so that the second conductors 104a have a top surface that is in direct contact with the conductive shielding layer <NUM> through the opening.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure <NUM> in accordance with some embodiments of the invention. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to <FIG> are omitted for brevity. In the embodiment, the semiconductor package structure <NUM> is similar to the semiconductor package structure <NUM> shown in <FIG>. The difference is the first patterned conductive layer <NUM> does not have the first conductors 102a. However, the fourth patterned conductive patterned layer <NUM> includes a plurality of fourth conductors 108a disposed in and along the edge region 100a' of the package substrate <NUM>. The conductive shielding layer <NUM>, such as a metal layer, covering and surrounding the encapsulating layer 130a and electrically connected to the fourth conductors 108a shown in <FIG> (or a conductive continuous layer 108a), so as to serve as an EMI shielding layer. In such cases, the fourth conductors 108a or the conductive continuous layer 108a are connected to ground and have a top surface in direct contact with the conductive shielding layer <NUM>. According to the invention, the sidewalls 101c of the package substrate <NUM> are entirely or partially covered by the conductive shielding layer <NUM>, as shown in <FIG>.

According to the invention, the fourth patterned conductive patterned layer <NUM> is in the lowermost layer-level of the insulating layer <NUM> and adjacent to the second surface 101b. In some embodiments, the shape, the structure, and the arrangement of the fourth conductors 108a in the edge region 100a' are the same as or similar to those of the first conductors 102a in the edge region 100a' shown in <FIG> or <FIG>. As a result, the edge region <NUM> a' is partially exposed from the plurality of fourth conductors 108a, as viewed from a top-view perspective. Alternatively, the fourth patterned conductive patterned layer <NUM> may include a conductive continuous layer (not shown) and the shape, the structure, and the arrangement of the conductive continuous layer in the edge region <NUM> a' are the same as or similar to those of the second conductors 104a in the edge region 100a' shown in <FIG>.

It should be understood that the methods for forming the semiconductor package structure <NUM> shown in <FIG> can be the same as or similar to the methods shown in <FIG>. In the fabrication of the semiconductor package structure <NUM>, the fourth patterned conductive layer <NUM> in the package substrate <NUM> may include fourth conductors 108a or a conductive continuous layer in and along the scribe line region of the package substrate <NUM>. In the fabrication of the semiconductor package structure <NUM>, the opening formed in the encapsulating material extends into the insulating layer <NUM>, so that the fourth conductors 108a has a top surface in direct contact with the conductive shielding layer <NUM> through the opening.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure <NUM> in accordance with some examples not falling under the scope defined in the claims but useful for the understanding thereof. Descriptions of elements of the examples hereinafter that are the same as or similar to those previously described with reference to <FIG> are omitted for brevity. In the example, the semiconductor package structure <NUM> is similar to the semiconductor package structure <NUM> shown in <FIG>. The difference is portions of the conductive shielding layer <NUM> that surround the sidewalls <NUM> of the encapsulating layer 130a have sidewalls <NUM> that are substantially level with those of the package substrate <NUM>.

It should be understood that the methods for forming the semiconductor package structure <NUM> shown in <FIG> can be the same as or similar to the methods shown in <FIG>. In the fabrication of the semiconductor package structure <NUM>, the opening formed in the encapsulating material <NUM> may be entirely filled with the conductive shielding layer <NUM>, so that portions of the conductive shielding layer <NUM> that surround the sidewalls <NUM> of the encapsulating layer 130a have sidewalls <NUM> that are substantially level with those of the package substrate <NUM> after the singulation process has been performed. In such cases, the conductive shielding layer <NUM> may be formed by a plating process or a spray deposition process.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure <NUM> in accordance with some examples not falling under the scope defined in the claims but useful for the understanding thereof. Descriptions of elements of the examples hereinafter that are the same as or similar to those previously described with reference to <FIG> are omitted for brevity. In the example, the semiconductor package structure <NUM> is similar to the semiconductor package structure <NUM> shown in <FIG>. The difference is the encapsulating layer 130a has sidewalls <NUM> that are substantially vertical.

It should be understood that the methods for forming the semiconductor package structure <NUM> shown in <FIG> can be the same as or similar to the methods shown in <FIG>. In the fabrication of the semiconductor package structure <NUM>, the opening in the encapsulating material <NUM> may be formed by a blade sawing process, so that the formed encapsulating layer 130a has sidewalls <NUM> that are substantially vertical after the singulation process has been performed. Moreover, the conductive shielding layer <NUM> may be formed by a plating process or a spray deposition process.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure <NUM> in accordance with some examples not falling under the scope defined in the claims but useful for the understanding thereof. Descriptions of elements of the examples hereinafter that are the same as or similar to those previously described with reference to <FIG> are omitted for brevity. In the embodiment, the semiconductor package structure <NUM> is similar to the semiconductor package structure <NUM> shown in <FIG>. The difference is the semiconductor package structure <NUM> further includes a heat spreader <NUM> over the conductive shielding layer <NUM>. In some examples, the heat spreader <NUM> is formed over the conductive shielding layer <NUM> via an attached film <NUM>.

It should be understood that the methods for forming the semiconductor package structure <NUM> shown in <FIG> can be the same as or similar to the methods shown in <FIG>. In the fabrication of the semiconductor package structure <NUM>, the attached film <NUM> and the heat spreader <NUM> are successively formed on the conductive shielding layer <NUM>, so that the heat spreader <NUM> is attached onto the conductive shielding layer <NUM>.

Moreover, it should be understood that the package substrate <NUM> shown in <FIG>, <FIG> can be replaced by package substrate <NUM> shown in <FIG>.

According to the foregoing embodiments and examples, the semiconductor package structure is designed to fabricate an EMI shielding layer integrated into the semiconductor package(s). The EMI shielding layer provides the function of reducing electrical noise and electromagnetic radiation and a compatible process for the semiconductor package structure. Accordingly, there is no need to perform an additional process for forming the shielding device. As a result, reliability, yield, and throughput of the semiconductor package structure are increased and the manufacturing cost of the semiconductor package structure is reduced.

Additionally, the integrated EMI shielding layer can provide design flexibility for the system integration of the semiconductor package structure. Moreover, the thickness of the EMI shielding layer formed by metal sputtering, plating, or spray deposition can be reduced, thereby reducing the size of the semiconductor package structure and preventing package warpage and delamination of the EMI shielding layer.

According to the foregoing embodiments and examples , the conductive continuous layer/the conductors formed in the scribe line region of the package substrate is/are exposed prior to the singulation process, so that the EMI shielding layer can also be formed prior to the singulation process. Since the EMI shielding layer is formed prior to the singulation process, additional tape mounting process and package rearrangement in the conventional fabrication for the EMI shielding can be omitted, thereby reducing the manufacturing cost and the process time for the semiconductor package structure and preventing pad of the package substrate from being contaminated due to the tape mounting process.

Claim 1:
A semiconductor package structure, comprising:
an encapsulating layer (130a);
a package substrate (<NUM>) having a device region (100b) covered by the encapsulating layer (130a) and an edge region (100a') surrounding the device region (100b) and exposed from the encapsulating layer (130a), wherein the package substrate (<NUM>) has a first surface (101a) and a second surface (101b) opposite to the first surface (101a), wherein the package substrate (<NUM>) comprises:
an insulating layer (<NUM>); and
a plurality of patterned conductive layers (<NUM>; <NUM>; <NUM>; <NUM>) in respective layer-levels of the insulating layer (<NUM>), wherein one conductive layer (<NUM>) of the plurality of patterned conductive layers (<NUM>; <NUM>; <NUM>; <NUM>) comprises a plurality of exposed conductors (108a) in and along the edge region (100a') and an embedded portion in the device region (100b);
a semiconductor die (<NUM>, <NUM>) disposed on the device region (100b) of the package substrate (<NUM>) onto the first surface (101a) of the package substrate (<NUM>) and surrounded by the encapsulating layer (130a); and
a conductive shielding layer (<NUM>) covering and surrounding the encapsulating layer (130a) and electrically connected to the plurality of exposed conductors (108a), wherein the plurality of exposed conductors (108a) has a top surface in direct contact with the conductive shielding layer (<NUM>), wherein said embedded portion of said one conductive layer (<NUM>) of the plurality of patterned conductive layers (<NUM>; <NUM>; <NUM>; <NUM>) is embedded in the insulating layer (<NUM>) below the first surface (101a) of the package substrate (<NUM>), so that the conductive shielding layer (<NUM>) extends to and covers sidewalls (101c) of the package substrate (<NUM>) above the top surface of the plurality of exposed conductors;
characterised in that said one conductive layer (<NUM>) of the plurality of patterned conductive layers (<NUM>; <NUM>; <NUM>; <NUM>) is in a lowermost layer-level of the insulating layer (<NUM>) and is adjacent to the second surface (101b) of the package substrate (<NUM>).