Patent Description:
Non-Volatile Memory express (NVMe) is an open, logical-device interface specification for accessing a non-volatile storage device attached via a PCI Express (PCIe) bus. NVMe, as a logical-device interface, has been designed to capitalize on the low latency and internal parallelism of solid-state storage devices. When NVMe is used to access a non-volatile storage device included in a Solid-State Drive (SSD), the SSD may be referred to as an NVMe SSD.

An abort command may be used to abort a target command in the NVMe SSD. When the NVMe SSD receives an abort command, the NVMe SSD will wait for a specific number of commands or for a specific amount of time. After waiting for the specified number of commands or the specific amount of time, if the target command to be aborted has not been received in the NVMe SSD, then no abort of the target command is performed in response to the abort command. Furthermore, there is no mechanism to abort a target command that is still in a host Input/Output (I/O) submission queue and has not been fetched by the NVMe SSD. Consequently, this procedure leads to uncertainty in performing an abort operation of the target command. <CIT> discloses an alternative method addressing the problem of aborting commands in the submission queue in an PCIe based NVMe SSD interface at the host.

In an embodiment, the present disclosure relates to a method for aborting a command in Peripheral Component Interconnect express (PCIe) based Non-Volatile Memory express (NVMe) Solid-State Drive (SSD). The method includes receiving an abort command in an Admin submission queue of a host to abort a target command present in an Input/output (I/O) submission queue of the host or an I/O queue of the NVMe SSD and updating a tail doorbell of NVMe doorbell registers of the NVMe SSD after receiving the abort command in the Admin submission queue. The abort command includes slot information of the target command to be aborted. Thereafter, the method includes placing the abort command into an Admin queue of the NVMe SSD after updating the tail doorbell of the NVMe doorbell registers by the host and executing the abort command using the slot information of the target command to be aborted by updating an I/O completion queue of the host with the target command to be aborted. Subsequently, the method includes updating a head doorbell of the doorbell registers of the NVMe SSD after completing execution of the abort command by the NVMe SSD and updating a response for the abort command in an Admin completion queue of the host upon completion of aborting of the target command in the NVMe SSD.

In an embodiment, the present disclosure relates to a system for aborting a command in Peripheral Component Interconnect express (PCIe) based Non-Volatile Memory express (NVMe) Solid-State Drive (SSD). The system includes a processor, and a memory communicatively coupled to the processor. The memory stores processor-executable instructions, which on execution, cause the processor to receive an abort command in an Admin submission queue of a host to abort a target command present in an Input/Output (I/O) submission queue of the host or an I/O queue of the NVMe SSD and update a tail doorbell of NVMe doorbell registers of the NVMe SSD after receiving the abort command in the Admin submission queue. The abort command includes slot information of the target command to be aborted. Thereafter, the system is configured to place the abort command into an Admin queue of the NVMe SSD after updating the tail doorbell of the NVMe doorbell registers by the host and execute the abort command using the slot information of the target command to be aborted by updating an I/O completion queue of the host with the target command to be aborted. In a subsequent step, the system is configured to update a head doorbell of the doorbell registers of the NVMe SSD after completing execution of the abort command by the NVMe SSD and update a response for the abort command in an Admin completion queue of the host upon completion of aborting of the target command in the NVMe SSD.

The features of the invention are set out in the claims.

The embodiments of the disclosure are illustrated in the accompanying drawings, throughout which like reference letters indicate corresponding parts in the various figures. The embodiments herein will be better understood from the following description with reference to the drawings, in which:.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described in detail below.

<FIG> shows an example environment for aborting a command in a PCIe based NVMe SSD in accordance with an embodiment of the present disclosure.

The environment for performing an abort command in PCIe based NVMe SSD includes a host <NUM> (e.g., a host device) and a NVMe SSD <NUM> as shown in <FIG>. The host <NUM> may, also, be referred as a host central processing unit (CPU). In one embodiment, the host <NUM> referred to here may be a standalone computer or a laptop including a CPU with a PCIe slot, standard I/O device and memory and the NVMe SSD <NUM> may be connected to the host <NUM> through a PCIe slot. In another embodiment, the host <NUM> may be a server class machine including multiple CPUs and multiple PCIe slots, a standard I/O device and memory and the NVMe SSD121 may be connected to the host <NUM> through one of the PCIe slots. The NVMe SSD <NUM> may, also, be referred as a target device or a device or a PCIe based NVMe SSD. The host <NUM> may be communicatively coupled to the NVMe SSD <NUM>. The host <NUM> may include a processor <NUM><NUM>, a memory <NUM><NUM> and an I/O interface <NUM><NUM>. The I/O interface <NUM><NUM> may be configured to communicate commands and/or data with the NVMe SSD <NUM>. The commands and/or data received by the I/O interface <NUM><NUM> may be stored in the memory <NUM><NUM>. The memory <NUM><NUM> may be communicatively coupled to the processor <NUM><NUM> of the host <NUM>. The memory <NUM><NUM> may, also, store processor instructions which may cause the processor <NUM><NUM> to execute instructions for aborting a command in the PCIe based NVMe SSD <NUM>. The processor <NUM><NUM> may include at least one data processor for aborting a command in the PCIe based NVMe SSD <NUM>.

<FIG> show diagrams illustrating an example operation for aborting a command in a PCIe based NVMe SSD in accordance with an embodiment of the present disclosure.

With reference to <FIG>, the host <NUM> may include an Admin Completion Queue (CQ), namely Admin CQ Id0 <NUM>. The host <NUM> may further include an Admin Submission Queue (SQ), namely Admin SQ Id0 <NUM>. The host <NUM> may additionally include an Input/Output Completion Queue (I/O CQ), namely I/O CQ Id1 <NUM>. Further, the host <NUM> may include an Input/Output Submission Queue (I/O SQ), namely I/O SQ Id1 <NUM>. The NVMe SSD <NUM> may include NVMe Doorbell Registers <NUM>, an I/O queue <NUM> and an Admin queue <NUM>. The NVMe Doorbell Registers <NUM> may include <NUM> registers: namely a Submission Queue <NUM> Tail DoorBell (SQ0TDB <NUM><NUM>), a Completion Queue <NUM> Head DoorBell (CQ0HDB <NUM><NUM>), a Submission Queue <NUM> Tail DoorBell (SQ1TDB <NUM><NUM>), and a Completion Queue <NUM> Head DoorBell (CQ1HDB <NUM><NUM>).

Hereafter, an operation for aborting a command in a PCIe based NVMe SSD in accordance with an embodiment of the disclosure is explained below with reference to <FIG>. In the embodiment, the command to be aborted is present in the I/O SQ (e.g., I/O SQ Id1 <NUM>) of the host <NUM>.

When the host <NUM> receives a command (e.g., Cmd1) for execution from a user, the host <NUM> places the command Cmd1 in the I/O SQ Id1 <NUM> of the host <NUM> as shown in <FIG>. In a subsequent step, the host <NUM> updates the SQ1TDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> present in the NVMe SSD <NUM> to <NUM> as shown in <FIG>. The updating of the SQ1TDB <NUM><NUM> is an indication to the NVMe SSD <NUM> that there is one command to be executed. Thereafter, the NVMe SSD <NUM> fetches the command Cmd1 into the I/O queue <NUM> for execution. For example, the NVMe SSD <NUM> may extract the command Cmd1 from the I/O SQ Id1 <NUM> and place the extracted command into the I/O queue <NUM>. There may be more commands, say Cmd2 to Cmd7, that may be received by the host <NUM> for execution from the user, as shown in <FIG>. The host <NUM> receives the commands Cmd2 to Cmd7 after Cmd1 and places the received commands in the I/O SQ Id1 <NUM> of the host <NUM> as shown in <FIG>. In a next step, the host <NUM> updates the SQ1TDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> present in the NVMe SSD <NUM> from <NUM> to <NUM>. The updating of the SQ1TDB <NUM><NUM> is an indication to the NVMe SSD <NUM> that there are <NUM> commands in total to be executed. Thereafter, the NVMe SSD <NUM> fetches the commands Cmd2 to Cmd5 into the I/O queue <NUM> for execution as shown in <FIG>. At this stage, the host <NUM> may receive an abort command in an Admin submission queue <NUM> to abort a target command in an I/O submission queue <NUM> of the host <NUM>. In detail, the host <NUM> may receive an abort command from the user in the Admin SQ Id0 <NUM> to abort a target command (e.g., Cmd6) in the I/O SQ Id1 <NUM> of the host <NUM>, as shown in <FIG>. In an embodiment, the abort command includes slot information of the target command to be aborted. In this case, the abort command includes slot information of the target command Cmd6 to be aborted. In an embodiment, the slot information includes a slot index of the I/O submission queue (e.g., the I/O SQ Id1 <NUM>) of the host <NUM> where the target command Cmd6 to be aborted is placed in the I/O submission queue (e.g., I/O SQ Id1 <NUM>) of the host <NUM>. For example, suppose I/O SQ Id1 <NUM> of the host <NUM> has <NUM> slots to submit commands and Cmd1 resides in Slot <NUM> of the I/O SQ Id1 <NUM>, Cmd2 resides in Slot <NUM> of the I/O SQ Id1 <NUM>, Cmd3 resides in Slot <NUM>, Cmd4 resides in Slot <NUM>, Cmd5 resides in Slot <NUM> and Cmd6 resides in Slot <NUM>. If Cmd6 is the target command to be aborted which is in I/O SQ Id1 <NUM> of the host <NUM>, then the abort command includes slot information (i.e., slot <NUM>) of the I/O SQ Id1 <NUM> Cmd Id (i.e., Cmd <NUM>). For example, the slot information may be a numerical value that indicates a location within the I/O submission queue of the target command to abort or cancel. Thereafter, the host <NUM> updates a tail doorbell of NVMe doorbell registers <NUM> of the NVMe SSD <NUM> after receiving the abort command in the Admin submission queue. In detail, the host <NUM> updates the SQ0TDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> of the NVMe SSD <NUM> after the host <NUM> receives the abort command in the Admin SQ Id0 <NUM> as shown in <FIG>. For example, the <NUM>' in the SQ0TDB <NUM><NUM> may indicate that one command is to be aborted.

In a next step, the NVMe SSD <NUM> fetches/receives the abort command in the Admin queue <NUM> of the NVMe SSD <NUM> after the host <NUM> updates the tail doorbell of the NVMe doorbell registers <NUM>. In detail, the NVMe SSD <NUM> places the abort command into the Admin queue <NUM> of the NVMe SSD <NUM> after determining that the SQ0TDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> has been updated to <NUM> by the host <NUM> as shown in <FIG>. Prior to executing the abort command using the slot information of the target command, the NVMe SSD <NUM> may complete execution of an I/O command which is being executed currently. For instance, in this case, the NVMe SSD <NUM> completes execution of command Cmd1 which is being executed currently before executing the abort command. Thereafter, the NVMe SSD <NUM> updates the I/O completion queue of the host <NUM> upon completion of the I/O command in the NVMe SSD <NUM>. In detail, the NVMe SSD <NUM> updates the I/O CQ Id1 <NUM> of the host <NUM> upon completion of the Cmd1 in the NVMe SSD <NUM> as shown in <FIG>. For example, the I/O CQ Id1 <NUM> may indicates that the first command Cmd1 has been completed by the NVMe SSD <NUM>. In a next step, the host <NUM> updates the head doorbell of the doorbell registers <NUM> of the NVMe SSD <NUM> after the completion of the I/O command. In detail, after the completion of Cmd1, the host <NUM> updates the CQ1HDB <NUM><NUM> of NVMe Doorbell Registers <NUM> of the NVMe SSD <NUM> to <NUM> as shown in <FIG>. Once the NVMe SSD <NUM> completes execution of an ongoing I/O command, the NVMe SSD <NUM> proceeds to execute the abort command. In a situation when the NVMe SSD <NUM> is not executing any I/O command, the NVMe SSD <NUM> proceeds to execute the abort command on receipt of the abort command. The NVMe SSD <NUM> executes the abort command using the slot information of the target command (e.g., Cmd6) to be aborted by updating an I/O completion queue (e.g., I/O CQ Id1 <NUM>) of the host <NUM> with the target command (e.g., Cmd6) to be aborted as shown in <FIG>. The host <NUM> updates the head doorbell of doorbell registers <NUM> of the NVMe SSD <NUM> after execution of the abort command by the NVMe SSD <NUM> has completed. In detail, the host <NUM> updates the CQ1HDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> of the NVMe SSD <NUM> from <NUM> to <NUM> after execution of the abort command by the NVMe SSD <NUM> has completed as shown in <FIG>. For example, the host <NUM> may update the CQ1HDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> of the NVMe SSD <NUM> from <NUM> to <NUM> upon determining that the target command to be aborted has been placed in I/O CQ Id1 <NUM>. Thereafter, the NVMe SSD <NUM> updates a response for the abort command in an Admin completion queue of the host <NUM> upon completion of aborting of the target command in the NVMe SSD <NUM>. In detail, the NVMe SSD <NUM> places information indicating completion of the abort command in the Admin CQ Id0 <NUM> of the host <NUM> upon completion of aborting of the Cmd6 in the NVMe SSD <NUM> as shown in <FIG>. Subsequently, the host <NUM> updates the head doorbell of the doorbell registers <NUM> of the NVMe SSD <NUM> after the host <NUM> receives the information indicating completion of the abort command in the Admin completion queue. In detail, the Host <NUM> updates the CQ0HDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> of the NVMe SSD <NUM> to <NUM> after the host <NUM> receives the abort command in the Admin CQ Id0 <NUM> as shown in <FIG>. This completes the operation for aborting the command Cmd6. After the abort command is executed on priority, the NVMe SSD <NUM> continues with the execution of commands Cmd2 to Cmd5 and then Cmd7 in a similar way as explained above for execution of the command Cmd1. For example, if another I/O command (e.g., Cmd2) is scheduled to be performed next while the abort command is received, but has not currently started to be executed, execution of this other I/O command can be delayed until the abort command has completed.

<FIG> show diagrams illustrating an example operation for aborting a command in PCIe based NVMe SSD in accordance with an embodiment of the present disclosure.

The environment for performing an abort command in a PCIe based NVMe SSD as per this embodiment is the same as the environment shown in <FIG>, which includes the host <NUM> and the NVMe SSD <NUM>. The host <NUM> may, also, be referred as a host CPU. In one embodiment, the host <NUM> referred here may be a standalone computer or a laptop with a CPU including a PCIe slot, standard I/O device and memory and the NVMe SSD <NUM> may be connected to the host <NUM> through a PCIe slot. In another embodiment, the host <NUM> may be a server class machine with multiple CPUs and multiple PCIe slots, standard I/O device and memory and the NVMe SSD <NUM> may be connected to the host <NUM> through one of the PCIe slots. The NVMe SSD <NUM> may, also, be referred as a target device or a device or a PCIe based NVMe SSD. The host <NUM> may be communicatively coupled to the NVMe SSD <NUM>. The host <NUM> may include a processor <NUM><NUM>, a memory <NUM><NUM> and an I/O interface <NUM><NUM>. The I/O interface <NUM><NUM> may be configured to communicate commands and/or data with the NVMe SSD <NUM>. The commands and/or data received by the I/O interface <NUM><NUM> may be stored in the memory <NUM><NUM>. The memory <NUM><NUM> may be communicatively coupled to the processor <NUM><NUM> of the host <NUM>. The memory <NUM><NUM> may, also, store processor instructions which may cause the processor <NUM><NUM> to execute the instructions for aborting a command in the PCIe based NVMe SSD <NUM>. The processor <NUM><NUM> may include at least one data processor for aborting a command in PCIe based NVMe SSD <NUM>. The processor <NUM><NUM> may include specialized processing units such as integrated system (bus) controllers, memory management control units, floating point units, graphics processing units, digital signal processing units, etc..

With reference to <FIG>, the host <NUM> may include an Admin CQ Id0 <NUM>, an Admin SQ Id0 <NUM>, I/O CQ Id1 <NUM> and I/O SQ Id1 <NUM>. The NVMe SSD <NUM> may include NVMe Doorbell Registers <NUM>, an I/O queue <NUM> and an Admin queue <NUM>. The NVMe Doorbell Registers <NUM> may include <NUM> registers: SQ0TDB <NUM><NUM>, CQ0HDB <NUM><NUM>, SQ1TDB <NUM><NUM>, and CQ1HDB <NUM><NUM>.

Hereafter, an operation for aborting a command in a PCIe based NVMe SSD in accordance with an embodiment of the disclosure is explained below with reference to <FIG>. In this embodiment, the command to be aborted is present in the I/O queue (e.g., I/O queue <NUM>) of the NVMe SSD <NUM>.

When the host <NUM> receives a command or commands, say Cmd1 to Cmd <NUM>, for execution from a user, the host <NUM> places the commands Cmd1 to Cmd <NUM> in the I/O SQ Id1 <NUM> of the host <NUM> as shown in <FIG>. In a subsequent step, the host <NUM> updates the SQ1TDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> present in the NVMe SSD <NUM> to <NUM> as shown in <FIG>. The updating of the SQ1TDB <NUM><NUM> is an indication to the NVMe SSD <NUM> that there are seven commands to be executed. Thereafter, the NVMe SSD <NUM> fetches the commands Cmd1 to Cmd7 into the I/O queue <NUM> for execution. At this stage, the host <NUM> may receive an abort command in an Admin submission queue <NUM> to abort a target command in an I/O queue of the NVMe SSD <NUM>, wherein the abort command includes slot information of the target command to be aborted. In detail, the host <NUM> may receive an abort command from the user in the Admin SQ Id0 <NUM> to abort a target command (e.g., Cmd6) in the I/O SQ id1 <NUM> of the host <NUM>, as shown in <FIG>. In an embodiment, the abort command includes slot information of the target command to be aborted. In this case, the abort command includes slot information of the target command Cmd6 to be aborted. The slot information includes a slot index of the I/O queue (e.g., an NVMe I/O queue <NUM>) of the Host <NUM> where the target command Cmd6 to be aborted is placed. For example, suppose I/O SQ Id1 <NUM> of the host <NUM> has <NUM> slots to submit commands and Cmd1 resides in Slot <NUM> of the I/O SQ Id1 <NUM>, Cmd2 resides in Slot <NUM> of the I/O SQ Id1 <NUM>, Cmd3 resides in Slot <NUM>, Cmd4 resides in Slot <NUM>, Cmd5 resides in Slot <NUM> and Cmd6 resides in Slot <NUM>. If Cmd6 is the target command to be aborted which is in I/O SQ Id1 <NUM> of the host <NUM>, then, the abort command includes slot information (i.e., slot <NUM>) of the I/O SQ Id1 <NUM> Cmd Id (i.e., Cmd <NUM>). Thereafter, the host <NUM> updates a tail doorbell of NVMe doorbell registers <NUM> of the NVMe SSD <NUM> after receiving the abort command. In detail, the host <NUM> updates the SQ0TDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> of the NVMe SSD <NUM> when the host <NUM> receives the abort command in the Admin SQ Id0 <NUM>, as shown in <FIG>. For example, the host <NUM> may update the SQ0TDB <NUM><NUM> to <NUM> to indicate that one command is to be aborted in response to determining that the Admin submission queue <NUM> includes an abort command.

In a next step, the NVMe SSD <NUM> places the abort command into an Admin queue of the NVMe SSD <NUM> after the host <NUM> updates the tail doorbell of the NVMe doorbell registers <NUM>. In detail, the NVMe SSD <NUM> places the abort command in Admin queue <NUM> of the NVMe SSD <NUM> after the SQ0TDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> has been updated to <NUM> by the host <NUM>. Prior to executing the abort command using the slot information of the target command, the NVMe SSD <NUM> may complete execution of an I/O command which is being executed currently. For instance, in this case, the NVMe SSD <NUM> completes execution of command Cmd1 which is being executed currently before executing the abort command. For example, execution of the abort command may be delayed until the NVMe SSD <NUM> completes execution of command which is being executed currently. Thereafter, the NVMe SSD <NUM> updates the I/O completion queue of the host <NUM> upon completion of the I/O command in the NVMe SSD <NUM>. In detail, the NVMe SSD <NUM> updates the I/O CQ Id1 <NUM> of the host <NUM> upon completion of the Cmd1 in the NVMe SSD <NUM> as shown in <FIG>. In a next step, the host <NUM> updates the head doorbell of the doorbell registers <NUM> of the NVMe SSD <NUM> after the completion of I/O command. In detail, the host <NUM> updates the CQ1HDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> of the NVMe SSD <NUM> to <NUM> after the completion of Cmd1 as shown in <FIG>. Once the NVMe SSD <NUM> completes execution of ongoing I/O command, the NVMe SSD <NUM> proceeds to execute the abort command. In a situation when the NVMe SSD <NUM> is not executing any I/O command, the NVMe SSD <NUM> proceeds to execute the abort command on receipt of the abort command. The NVMe SSD <NUM> executes the abort command using the slot information of the target command (e.g., Cmd6) to be aborted by updating an I/O completion queue (e.g., I/O CQ Id1 <NUM>) of the host <NUM> with the target command (e.g., Cmd6) to be aborted as shown in <FIG>. The host <NUM> updates a head doorbell of the doorbell registers <NUM> of the NVMe SSD <NUM> after completing execution of the abort command by the NVMe SSD <NUM>. In detail, the host <NUM> updates the CQ1HDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> of the NVMe SSD <NUM> from <NUM> to <NUM> after completing execution of Cmd6 as shown in <FIG>. Thereafter, the NVMe SSD <NUM> updates a response for the abort command in an Admin completion queue of the host <NUM> upon completion of aborting of the target command in the NVMe SSD <NUM>. For example, the NVMe SSD <NUM> may store information in the Admin CQ Id0 <NUM> indicating that the target command has been aborted. In detail, the NVMe SSD <NUM> updates the abort command in the Admin CQ Id0 <NUM> of the host <NUM> upon completion of aborting of the Cmd6 in the NVMe SSD <NUM> as shown in <FIG>. Subsequently, the host <NUM> updates the head doorbell of the doorbell registers <NUM> of the NVMe SSD <NUM> after the host <NUM> determines completion of the abort command from the Admin completion queue. In detail, the host <NUM> updates the CQ0HDB <NUM><NUM> of the NVMe Doorbell Registers <NUM> of the NVMe SSD <NUM> to <NUM> after the host <NUM> receives the abort command in the Admin CQ Id0 <NUM> as shown in <FIG>. This completes the operation for aborting the command Cmd6. After the abort command is executed on priority, the NVMe SSD <NUM> continues with the execution of commands Cmd2 to Cmd5 and then Cmd7 in a similar way as explained above for execution of the command Cmd1.

<FIG> illustrates a flowchart showing a method for aborting a command in PCIe based NVMe SSD in accordance with a first and a second embodiment of the present disclosure.

As illustrated in <FIG>, the method <NUM> includes one or more steps for aborting a command in a PCIe based NVMe SSD in accordance with an embodiment of the present disclosure. The method <NUM> may be described in the general context of computer executable instructions. Generally, computer executable instructions can include routines, programs, objects, components, data structures, procedures, units, and functions, which perform particular functions or implement particular abstract data types.

The order in which the method <NUM> is described is not intended to be construed as a limitation, and any number of the described method steps can be combined in any order to implement the method. Additionally, individual steps may be deleted from the method without departing from the scope of the subject matter described herein. Furthermore, the method can be implemented in any suitable hardware, software, firmware, or combination thereof.

At step <NUM>, the host <NUM> receives an abort command in an Admin submission queue <NUM> to abort a target command in an I/O submission queue <NUM> of the host <NUM> or abort a target command in an I/O queue <NUM> of the NVMe SSD <NUM> or abort a target command in an Admin queue <NUM> of the NVMe SSD <NUM>. The abort command may include slot information of the target command to be aborted. The slot information may include a slot index of the I/O submission queue <NUM> of the host <NUM> where the target command to be aborted is placed.

At step <NUM>, the host <NUM> updates a tail doorbell <NUM><NUM> of NVMe doorbell registers <NUM> of the NVMe SSD <NUM> after receiving the abort command in the Admin submission queue <NUM>.

At step <NUM>, the NVMe SSD <NUM> places the abort command into an Admin queue <NUM> of the NVMe SSD <NUM> after the tail doorbell <NUM><NUM> of the NVMe doorbell registers <NUM> is updated by the host <NUM>.

At step <NUM>, the NVMe SSD <NUM> executes the abort command using the slot information of the target command to be aborted by updating an I/O completion queue <NUM> of the host <NUM> with the target command to be aborted.

At block <NUM>, the host <NUM> updates a head doorbell <NUM><NUM> of the doorbell registers <NUM> of the NVMe SSD <NUM> after completing execution of the abort command by the NVMe SSD <NUM>.

At block <NUM>, the NVMe SSD <NUM> updates a response for the abort command in an Admin completion queue <NUM> of the host <NUM> upon completion of aborting of the target command in the NVMe SSD <NUM>.

The use of the slot index in the present disclosure allows a target command to be aborted immediately after receiving the abort command when the target command is in the NVMe SSD or is still in the host. This approach may reduce abort response time significantly.

Typically, when the NVMe SSD receives an abort command, the NVMe SSD will wait for a specific number of commands or for a specific amount of time. After waiting for the specified number of commands or the specific amount of time, if the target command to be aborted is not received in the NVMe SSD, then the target command is not aborted. So, there is no guarantee that the abort command will be executed. However, in at least one embodiment of the present disclosure, a device can determine the existence of the target command using the slot index when the abort command is received. As a result, at least one embodiment of the NVMe SSD guarantees an abort operation of the target command and at least one embodiment of the method of the present disclosure guarantees consistency of a response time for an abort command.

Due to the slot index, a look-up method for a target command may be optimized. Hence, an abort command implementation in an NVMe SSD as provided in the present disclosure is very useful.

A description of an embodiment above with several components in communication with each other does not imply that all such components are required. On the contrary, a variety of optional components are described to illustrate a wide variety of possible embodiments of the disclosure.

When a single device or article is described herein or above, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein or above (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article, or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device described herein or above may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the invention need not include the device itself.

The illustrated operations of <FIG> show certain events occurring in a certain order. In alternative embodiments, certain operations may be performed in a different order, modified or removed. Moreover, steps may be added to the above-described logic and still conform to the described embodiments. Further, operations described herein may occur sequentially or certain operations may be processed in parallel. Yet further, operations may be performed by a single processing unit or by distributed processing units.

The language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by any claims that issue on an application based here on. Accordingly, the disclosure of the embodiments of the invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

Claim 1:
A method for aborting a command in a Peripheral Component Interconnect express - PCIe based Non-Volatile Memory express - NVME Solid-State Drive - SSD (<NUM>) the method comprising:
receiving, by a host, an abort command in an Admin submission queue of the host to abort a target command present in an Input/Output - I/O submission queue of the host or in an I/O queue of the NVMe SSD, wherein the abort command comprises slot information of the target command to be aborted;
updating, by the host, a tail doorbell of NVMe doorbell registers of the NVMe SSD after receiving the abort command in the Admin submission queue;
placing, by the NVMe SSD, the abort command into an Admin queue of the NVMe SSD after updating the tail doorbell of the NVMe doorbell registers by the host;
executing, by the NVMe SSD, the abort command using the slot information of the target command to be aborted by updating an I/O completion queue of the host with the target command to be aborted;
updating, by the host, a head doorbell of the doorbell registers of the NVMe SSD after completing execution of the abort command by the NVMe SSD; and
updating, by the NVMe SSD, a response for the abort command in an Admin completion queue of the host upon completion of aborting of the target command in the NVMe SSD.