Patent Description:
A Sigma-Delta ADC encodes an analog signal into a digital output signal. The first step in converting the analog signal with the Sigma-Delta ADC is to form a "delta" or difference between the analog input and the digital output converted back to analog form by a Digital-to-Analog Converter (DAC). This feedback of the digital output through the DAC introduces a significant source of nonlinearity in the converter system, which limits the overall system performance.

<CIT> discloses a method of reducing switching error in data converters in which, to reduce second order distortion, the DAC is supplied with additional or redundant unary DAC elements so that the DAC can be optimized or calibrated to have the least or lesser amount of injected error distortion attributed to the non-linearly dependent part of the switching induced error. Prior to data conversion, a subset of DAC elements having a lesser sum of switching errors is selected during calibration and other redundant DAC elements are not used at all or shut off permanently.

<NPL>, disclose a pipelined ADC self-configuration scheme for a multiplying digital-to-analog converter (MDAC) capacitor array for best matching from many trial combinations of smaller capacitive sub-elements, in which sub-elements having opposite error magnitudes are grouped together to form matched elements thus permitting an accurate multi-bit MDAC to be created without using an explicit trimming network. A random search algorithm enables the self-configuration process by quickly regrouping the sub-elements to reduce the spread between the reconstructed elements.

In accordance with the invention there is provided a method and system for Signal-to-Noise and Distortion Ratio improvement through optimal Digital-to-Analog-Converter element selection, as defined by the appended claims.

Embodiments described herein provide for SNDR improvement by optimizing the linearity of a DAC in a Sigma-Delta ADC. Specifically, the linearity of the DAC is improved by optimally selecting the order in which DAC unary current sources (e.g., elements) are selected to convert the time variant digital output of the ADC. The DAC output (e.g., an analog output) is comprised of the sum of the individual unit element currents, which each have a random offset current in which the cumulative offset current, and therefore the linearity, are minimized through optimal element ordering.

The distortion due to nonlinearity in a Sigma-Delta ADC, (either continuous or discrete), is dominated by how well the feedback DAC elements match each other. Solutions to this include using a single bit feedback DAC, which implies linearity because only two element states are possible. One problem with using a single bit feedback DAC is that to obtain the same dynamic range as a multi-bit DAC, a higher oversampling ratio is required. Consequently, a higher clock rate is required, which increases power consumption.

Another approach to reducing the nonlinearity of a Sigma-Delta ADC is to compensate for the element mismatch in the DAC with a mismatch shaping algorithm. This approach shapes the error from the DAC nonlinearity, due to the element mismatch, out of the signal band. However, this approach increases the in-band noise floor, and also adds delay to the ADC feedback loop, thus degrading loop stability. In discrete time Sigma-Delta conversion this is not as problematic, but in continuous time Sigma-Delta conversion special attention must be paid to the glitch energy that occurs with implementing shaped randomization of the DAC element choices. Shaping increases glitch energy due to the switching of the DAC elements. This glitch energy occurs at the summing junction of the integrator as the analog input and the DAC feedback are integrated. Consequently, the integration of this glitch energy can significantly degrade the conversion performance.

Another option to reduce the DAC nonlinearity is to increase the size of the DAC elements to improve the matching between the elements. This approach increases area and power consumption, which is particularly undesirable for converters in an embedded design (e.g., on a monolithic integrated circuit).

Embodiments described herein overcome the limitations of the aforementioned approaches requiring higher oversampling ratios for a given SNR, shaping or increasing the layout area. By executing a series of analog to digital conversions with a Sigma-Delta ADC and observing the SNDR with a Fourier transform (e.g., a Fast Fourier Transform), an optimized ordering of the elements is determined to maximize the SNDR. Each conversion permutes the order of the DAC elements resulting in a different SNDR. The optimized ordering yielding the largest SNDR, is then stored in a lookup table accessible by the DAC during data conversion operations with the Sigma-Delta ADC.

While various embodiments of this disclosure are directed towards improving SNDR of a Sigma-Delta ADC by optimizing element ordering of a feedback DAC within the converter, similar SNDR advantages are realized by applying the teaching of this disclosure to a standalone unit element DAC. Similarly in other embodiments, SNDR improvement of a unit element DAC is advantageous in systems comprising the unit element DAC.

<FIG> shows an embodiment <NUM> of a system for SNDR improvement though optimal DAC element selection in accordance with an example embodiment of the present disclosure. A summing circuit <NUM> subtracts a DAC output <NUM> from an analog input <NUM> to determine a delta value <NUM>. The delta value <NUM> is filtered by a filter <NUM> to determine a filtered value <NUM>. In one embodiment, the filter <NUM> is a low pass filter. In another embodiment, the filter <NUM> is a band pass filter. A multi-bit ADC converts the filtered value <NUM> into a multi-bit digital output <NUM> of width "N. " In one embodiment, the ADC <NUM> is a flash ADC and the digital output <NUM> is coded as a thermometer code. For example, a <NUM>-bit ADC <NUM> has a digital output of <NUM> bits, which are input to the DAC <NUM>. In another embodiment, the digital output <NUM> is converted to a <NUM>-bit binary code and fed into a decimation filter (not shown), thus converting the system <NUM>, (based on a Sigma-Delta modulator) into a Sigma-Delta ADC.

Other bit widths are envisioned within by this disclosure. Increasing the bit width of the ADC <NUM> beneficially reduces quantization noise. The multi-bit digital output <NUM> is converted into a DAC output <NUM> output by a unit element DAC <NUM>. The DAC <NUM> accesses a lookup table <NUM> over a connection <NUM>, to define connections between the digital inputs of the DAC <NUM> and the respective unit elements included therein.

The lookup table <NUM> holds the values that determine an optimized ordering of the DAC elements, as further discussed with reference to <FIG>. The lookup table <NUM> is outside of the control loop formed by the summing circuit <NUM>, the low pass filter <NUM>, the multi-bit ADC and the multi-bit unit element DAC <NUM>. Accordingly, the lookup table <NUM> does not add control loop delay, nor affect loop stability. In various embodiments, the lookup table <NUM> is formed with a Non-Volatile Memory, include one or more of a laser fuse, and EPROM, a One Time Programmable memory, and the like. The teachings of this disclosure are also applicable to higher order Sigma-Delta ADCs having a plurality of feedback paths from one or more DACs to one or more summing circuits between the analog input <NUM> and the multi-bit digital output <NUM>. For embodiments including higher order Sigma-Delta ADCs, each of the DACs may have an optimized ordering of their respective unary current sources. However, most of the reduction in distortion is obtained by optimizing the DAC whose output feeds the first summing circuit connected directly to the analog input <NUM>.

<FIG> is an embodiment <NUM> of the filter <NUM> of <FIG>, configured as an integrator. An amplifier <NUM> includes a positive input connected to a ground <NUM>. The delta value <NUM> of <FIG> is connected to a negative input <NUM> through a resistor <NUM>. The amplifier <NUM> generates the filtered value <NUM> of <FIG>, which is further connected to the negative input <NUM> through a feedback capacitor <NUM>. Glitch energy caused by switching of the elements of the multi-bit unit element DAC <NUM> is fed directly into the summing circuit <NUM> of <FIG> and integrated at the negative input <NUM>, thus undesirably contributing to system noise.

Turning now to <FIG> with reference to <FIG>, an embodiment <NUM> of the multi-bit unit element DAC <NUM> will be further described. In the DAC <NUM> used in the feedback path of the embodiment <NUM>, in one embodiment the number of required elements is equal to <NUM>N * LSB, where N is the number of bits used by the DAC <NUM> (e.g., the width of the multi-bit digital output <NUM>) and LSB is the Least Significant Bit of the multi-bit path. In other embodiments, any number of elements can be used, not necessarily constrained to being a multiple of two. For illustration purposes, the width of the example embodiment <NUM> of <FIG> is two bits, thus requiring four unary weighted elements, wherein each element represent one LSB current relative to a full scale current. Other bit widths are envisioned with the scope of this disclosure.

The embodiment <NUM> includes a bias source <NUM> and a DAC output <NUM>. A plurality of switches 54a, 54b, 54c and 54d (generally <NUM>), are connected in series with respective unary weighted current sources 56a, 56b, 56c and 56d (generally <NUM>). Each of the current sources <NUM> is connected to the ground <NUM>. Each switch <NUM> and a respective current source <NUM> (e.g. switch 54a and current source 56a) is referred to as an "element. " For the embodiment <NUM>, a digital input of "<NUM>" (e.g., three) is represented by connecting the DAC output <NUM> to three elements by activating three of the four switches <NUM>, having respective current sources <NUM>. If the next digital input is "<NUM>" (e.g., four), then the DAC output <NUM> will be connected to the remaining element.

Each of the current sources <NUM>, includes a nominal current plus a respective random offset current, where the respective random offset current either adds to or subtracts from the nominal current. Randomizing the order of the unit elements can be accomplished by any of the randomization methods that are well known in the art such as applying a power to the memory, which has been designed to come up in a random state at power up or using a linear feedback shift register. As the digital input to the multi-bit unit element DAC <NUM> of <FIG> changes, one or more elements are connected to the DAC output <NUM>. Each of the unary weighted elements have the same nominal current, hence there are a plurality of combinations of selecting elements to achieve the same value of the DAC output <NUM> in response to a change in the digital output <NUM>. The embodiment <NUM> of <FIG> is one of many unit element DACs that can be used with the system of <FIG>. The embodiment <NUM> is a current output DAC, which is used with an embodiment <NUM> where the analog input <NUM> is represented by a current. In another embodiment, the multi-bit unit element DAC <NUM> supplies a voltage output (e.g., a Kelvin Divider) to the summing circuit <NUM> and the analog input <NUM> is represented by a voltage.

<FIG> shows the nonlinear characteristics of the DAC output <NUM> of <FIG>, before optimizing the ordering of the selectable elements of the multi-bit unit element DAC <NUM>. In contrast, <FIG> shows the nonlinear characteristics of the DAC output <NUM> of <FIG>, after optimizing the ordering of the selectable elements of the multi-bit unit element DAC <NUM>. Due to the mismatch between each of the current sources <NUM> of <FIG>, each element will have an offset, either positive or negative relative to the ideal or average value. For example, if the digital input (e.g., or the digital output <NUM>) to the multi-bit unit element DAC <NUM> is ramped from zero to full scale, the multi-bit unit element DAC <NUM> would use the first element, then sequentially add additional elements until all of the elements are used. The analog output of the DAC <NUM> will ideally represent a staircase with equal steps. However, due to offsets each step will be change based on the cumulative offsets of the respective elements.

If the layout of the elements of the multi-bit unit element DAC <NUM> follows best practices and no layout skew exists, the mismatch of each element follows a normal Gaussian distribution. Therefore, as the number of elements approaches infinity, the mean of the summation of offsets would yield a zero mean with equal probabilistic weighting of positive and negative offsets. Therefore, in the limit of such a large selection of elements, the relationship the digital input to the analog output shown in <FIG> approaches a straight line. It is not practical to design an infinite numbers of elements. However, with proper permutation of the existing elements a significant improvement in linearity and thus SNDR is achieved.

Returning to <FIG> and with reference to <FIG>, the output of the multi-bit unit element DAC <NUM> is shown based on a two-bit binary system with four elements. As the digital input to the DAC <NUM> (e.g., the digital output <NUM>) progresses from "<NUM>" to "<NUM>" the DAC output <NUM>, (or analog output) would ideally follow the equal current steps <NUM>, <NUM>, <NUM> and <NUM>. Due to mismatch induced offsets in the current sources <NUM>, step <NUM> is increased by an offset <NUM> due to the first current source 56a to yield a step <NUM>. Step <NUM> is increased by an offset <NUM> from the first selected current source 56a and an offset <NUM> from the second selected current source 56b to yield a step <NUM>. The cumulative offset is equal to <NUM> plus <NUM>. Similarly, step <NUM> is increased by offsets <NUM> and <NUM> and decreased by <NUM> (the offset from the third current source 56c) to yield a step <NUM>. Lastly, Step <NUM> is altered by offsets <NUM>, <NUM>, <NUM> and <NUM> (from the fourth current source 56d) to yield a step <NUM>. As shown by <FIG>, the linearity of steps <NUM>, <NUM>, <NUM> and <NUM> is poor, thus causing distortion and thereby leading to low SNDR.

In contrast to <FIG> shows an improved linearity of the DAC <NUM> due to optimized ordering of elements. Rather than progressively combining the first, second, third, and fourth current sources 56a, 56b, 56c and 56d respectively, as was done in <FIG>, an optimized element order is chosen. Specifically, the first current source 56a is chosen for input "<NUM>" because the offset <NUM> is the smallest of the four offsets. For input "<NUM>" the fourth current source 56d is chosen so that the cumulative offset <NUM> and <NUM> largely cancel each other. Subsequently, for input "<NUM>" the second current source 56b is chosen, so that the cumulative offsets <NUM>, <NUM> and <NUM> still remain close to zero. Lastly, for input "<NUM>" the third current source 56c is chosen so that the cumulative offsets <NUM>, <NUM>, <NUM> and <NUM> yield a small negative offset. As can be seen from <FIG>, the DAC output <NUM> with the optimized ordering shown by <NUM>, <NUM>, <NUM> and <NUM> closely approximates the ideal output shown by <NUM>, <NUM>, <NUM>, and <NUM>.

<FIG> shows a Fast Fourier Transform of an output of a Sigma-Delta ADC system employing a <NUM>-bit quantizer ADC and a <NUM>-bit feedback DAC showing decibels relative to full scale for a range of frequencies, and using no DAC linearity correction technique such as optimized element ordering or data weighted averaging. In <FIG>, the fundamental signal peak is <NUM> is shown in relation to a plurality of significant distortion components <NUM>. Shaped noise <NUM> is shown to be shifted to a higher frequency band, which can be filtered with a digital low pass filter in a post processing step, however the SNDR is only 67dB with an SNR of 84dB.

<FIG> shows measured SNDR and SNR for a series of tests (numbered <NUM> through <NUM>) of one ADC, where the DAC element ordering is randomly defined for each test of the system of <FIG>. In one embodiment, the DAC elements are randomly defined upon application of power to the DAC <NUM>. In another embodiment, the randomization of the DAC elements is performed by a random number generator, (e.g., a linear feedback shift register). As shown, the SNR variation is only approximately 3dB due to quantization and other system noise. <FIG> shows a significant improvement in SNDR from 57dB measured from the first test run to 72dB measured from the sixth test run for the same ADC with different ordering of the DAC elements, or a 15dB improvement. In one embodiment, the SNDR is measured with an external tester used for production testing of semiconductor components. In another embodiment, the SNDR is measured with a wafer probe tester.

Extensive measurements have consistently demonstrated that six to eight test runs have yielded significant improvements in SNDR. The term "optimized ordering" as used throughout this disclosure includes an ordering of the DAC unit elements determined from a series of tests that include randomization of the unit elements that comprise the DAC that is used in the Sigma-Delta ADC of <FIG>. In one embodiment, the tests to determine the optimized element ordering are performed during wafer probe testing. In another embodiment, the tests to determine the optimized ordering of the DAC unit elements are performed during post assembly (packaging) testing. In another embodiment, a full determination of all possible unit element ordering combinations of a subset of the most critical of the unit elements that comprise the DAC is determined by only considering the elements that will be used the most often (e.g. those in the center of the DAC output range) by applying an input to the ADC that only uses a limited range of the quantizer's (e.g., ADC <NUM>) digital output <NUM>. In another embodiment, the optimal element ordering is defined through randomization wherein the digital output <NUM> is limited to a high slope region, such as zero crossing of a sinusoidal waveform. Accordingly, this limited range exceeds a slope threshold where changes to the DAC output <NUM> of <FIG> are of a greater magnitude than in low slope regions.

<FIG> shows a method <NUM> for SNDR improvement through optimal DAC element selection. At <NUM>, an order of a plurality of unit element of a DAC is randomized. At <NUM>, a plurality of digital inputs, controlling the unit elements, is ramped to generate analog outputs. At <NUM>, a first SNDR of the DAC is measured from the analog outputs. At <NUM>, a maximum SNDR is determined from the first SNDR and at least one previously measured SNDR, using the same method as used to determine the first SNDR, to determine an optimal order of the unit elements. At <NUM>, the optimal order is stored in a memory to define the connections between the digital inputs and the unit elements.

<FIG> shows another method <NUM> for SNDR improvement through optimal DAC element selection. At <NUM>, an SNDR of a Sigma-Delta ADC is determined for a plurality of test runs. In one embodiment, the Sigma-Delta ADC comprises the system <NUM> of <FIG> followed by a digital filter. Determining the SNDR at <NUM> comprises at <NUM>, randomizing an order of the unit elements of a DAC within the Sigma-Delta ADC; at <NUM>, ramping a time-variant analog input of the Sigma-Delta ADC, and at <NUM>, measuring an SNDR of the Sigma-Delta ADC. At <NUM>, a maximum SNDR is determined from each of the test runs, wherein the maximum SNDR corresponds to an optimal order of the unit elements. At <NUM>, the optimal order is stored in a memory.

As will be appreciated, embodiments as disclosed include at least the following. In one embodiment, a method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection comprises randomizing an order of a plurality of unit elements of a DAC, wherein each of the unit elements is controlled by a respective one of a plurality of digital inputs of the DAC. The plurality of digital inputs are sequentially asserted over at least a subset of a full set of the digital inputs to generate a plurality of analog values of an analog output of the DAC. A first SNDR of the DAC is measured from the plurality of analog values. A maximum SNDR is determined from the first SNDR and at least one previously measured SNDR, the maximum SNDR corresponding to an optimal order of the unit elements. The optimal order of the unit elements of the DAC is stored in a memory to define connections between the digital inputs and the respective unit elements based on the optimal order.

Alternative embodiments of the method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection include one of the following features, or any combination thereof. The optimal order of the unit elements is accessed from the memory by the DAC, for subsequently converting the digital inputs to the respective analog values. The subset is centered within the full set. The subset is equal to the full set. The at least one previously measured SNDR comprises at least five measured SNDR. Randomizing the order of the unit elements comprises applying a power to the memory, wherein the memory is designed to comprise random states in response to applying the power. Randomizing the order of the unit elements comprises defining the order with a plurality of outputs of a linear feedback shift register. The full set of the digital inputs is determined by quantizing a sine wave. The full set of the digital inputs is determined by quantizing a periodic signal. Each of the analog values comprises a cumulative offset current formed by a summation of a respective random offset current of each unit element selected by the optimal order.

In another embodiment, a system for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection comprises a plurality of unit elements of a DAC, wherein an order of the unit elements is configured to be randomized. Each of a plurality of digital inputs of the DAC is configured to control a respective unit element based on the order of the unit elements. An analog output of the DAC is switchably connected to one or more of the unit elements based on a respective value of each of the respective digital inputs. A memory is configured to store the optimal order of the unit elements of the DAC to define connections between the digital inputs and the respective unit elements, wherein the optimal order is determined from an optimal test run of a plurality of test runs, each of the test runs determine a respective SNDR, and the optimal test run comprises a maximum SNDR.

Alternative embodiments of the system for a system for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection include one of the following features, or any combination thereof. A tester is configured to determine the respective SNDR of each of the test runs by sequentially asserting the plurality of digital inputs over at least a subset of a full set of the digital inputs to generate a plurality of analog values of the analog output, and measuring the SNDR of the DAC from the plurality of analog values. Each of the unit elements comprise a switchable current source comprising a nominal current having a respective random offset current. The analog output comprises a cumulative offset current formed by a summation of a respective random offset current of each unit element selected by the optimal order. A Sigma-Delta Analog-to-Digital Converter (ADC) comprises an ADC configured to quantize a filtered sum of the analog output of the DAC subtracted from a time-variant analog input of the Sigma-Delta ADC.

In another embodiment, a method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection comprises determining an SNDR of a Sigma-Delta Analog-to-Digital Converter (ADC) for a plurality of test runs, wherein each test run comprises: randomizing an order of a plurality of unit elements of a DAC, the Sigma-Delta ADC comprising an ADC configured to quantize a filtered sum of an output of the DAC subtracted from a time-variant analog input of the Sigma-Delta ADC, asserting the time-variant analog input over at least a subset of a full range of the analog signal, and measuring an SNDR of the Sigma-Delta ADC. A maximum SNDR is determined from a respective SNDR of each of the test runs, wherein the maximum SNDR corresponds to an optimal order of the unit elements. The optimal order of the unit elements is stored in a memory.

Alternative embodiments of the method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection include one of the following features, or any combination thereof. The optimal order of the unit elements is accessed from the memory by the DAC, for subsequently generating a plurality of analog values of the output of the DAC. Randomizing the order of the unit elements comprises applying a power to the memory, wherein the memory is designed to comprise random states in response to applying the power. Randomizing the order of the unit elements comprises defining the order with a plurality of outputs of a linear feedback shift register. The time-variant analog input is a sine wave.

A method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection includes randomizing an order of a plurality of unit elements of a DAC, wherein each of the unit elements is controlled by a respective one of a plurality of digital inputs of the DAC. The plurality of digital inputs is sequentially asserted over at least a subset of a full set of the digital inputs to generate a plurality of analog values of an output of the DAC. A first SNDR of the DAC is measured from the plurality of analog values. A maximum SNDR, corresponding to an optimal order, is determined from the first SNDR and at least one previously measured SNDR. The optimal order of the unit elements of the DAC is stored in a memory to define connections between the digital inputs and the respective unit elements based on the optimal order.

Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense.

Claim 1:
A method for Signal-to-Noise and Distortion Ratio, SNDR, improvement through Digital-to-Analog-Converter, DAC, element selection, comprising:
performing a plurality of test runs, each test run comprising:
randomizing an order of a plurality of unary weighted unit elements (54a-d, 56a-d) of a DAC (<NUM>, <NUM>), wherein each of the unit elements (54a-d, 56a-d) is controlled by a respective one of a plurality of digital inputs of the DAC (<NUM>, <NUM>) based on the order of the plurality of unit elements (54a-d, 56a-d);
sequentially asserting the plurality of digital inputs over at least a subset of a full set of the digital inputs to the randomized order of the plurality of unit elements to generate a plurality of analog values of an analog output (<NUM>) of the DAC (<NUM>, <NUM>); and
measuring an SNDR of the DAC (<NUM>, <NUM>) from the plurality of analog values; selecting from the plurality of test runs an order of the unit elements (54a-d, 56a-d) corresponding to a maximum SNDR; and
storing the selected order of the unit elements (54a-d, 56a-d) of the DAC (<NUM>, <NUM>) in a memory (<NUM>) to define connections between the digital inputs and the respective unit elements (54a-d, 56a-d) based on the selected order.