Patent Description:
Today, there is an increasing trend to include sophisticated semiconductor devices in products and systems that are used every day. These sophisticated semiconductor devices may include features for specific applications which may impact the configuration of the semiconductor device packages, for example. For some features and applications, the configuration of the semiconductor device packages may be susceptible to lower reliability which could impact performance and system costs. Accordingly, significant challenges exist in accommodating these features and applications while minimizing the impact on semiconductor devices' reliability while minimizing impact on performance and costs.

<CIT> discloses a semiconductor die with a bond pad.

Generally, there is provided, a semiconductor device with an under-bump metallization (UBM) structure. The semiconductor device includes a semiconductor die partially encapsulated with an encapsulant. An active side of the semiconductor die is exposed and coplanar with a surface of the encapsulant. A non-conductive layer is formed over an active side of semiconductor die and surface of the encapsulant. An opening in the non-conductive layer is formed to expose a bond pad. A laser ablated trench is formed at the surface of the non-conductive layer near a perimeter of the opening. By using a low energy laser to form the trench, a bottom surface of the trench is roughened. The UBM structure is formed by plating over the trench and exposed pad region. The rough texture of the trench allows for superior adhesion of the UBM structure at the trench. By forming the UBM in this manner, potential stress induced delamination is minimized thus improving overall reliability of the semiconductor device.

<FIG> illustrates, in a simplified cross-sectional view, a portion of an example semiconductor device <NUM> having a UBM structure at a stage of manufacture in accordance with an embodiment. At this stage of manufacture, the semiconductor device <NUM> includes a semiconductor die <NUM> partially encapsulated with an encapsulant <NUM> such as an epoxy molding compound (EMC). The semiconductor device <NUM> portion depicted in <FIG> at stages of manufacture is shown in a bottom side up orientation.

The semiconductor die <NUM> has an active side (e.g., major side having circuitry) and a backside (e.g., major side opposite of the active side). In this embodiment, the active side of the semiconductor die <NUM> is exposed (e.g., not encapsulated) and substantially coplanar with a first surface <NUM> of the encapsulant <NUM>. The semiconductor die <NUM> includes a substrate (e.g., bulk) portion <NUM>, a conductive interconnect trace <NUM> (e.g., copper, aluminum, or other suitable metal), a bond pad <NUM> conductively connected to the trace, and a final passivation layer <NUM> formed over the active side of the die. The bond pad <NUM> is configured for conductive connection to printed circuit board (PCB) by way of a UBM structure formed at a subsequent stage, for example. The term "conductive," as used herein, generally refers to electrical conductivity unless otherwise noted.

The semiconductor die <NUM> may be formed from any suitable semiconductor material, such as silicon, germanium, gallium arsenide, gallium nitride, silicon nitride, silicon carbide, and the like. The semiconductor die <NUM> may further include any digital circuits, analog circuits, RF circuits, memory, signal processor, MEMS, sensors, the like, and combinations thereof. The semiconductor die <NUM> may include any number of conductive interconnect layers and passivation layers. For illustration purposes, the interconnect layer forming trace <NUM> and the final passivation layer <NUM> are depicted.

<FIG> illustrates, in a simplified cross-sectional view, the example semiconductor device <NUM> at a subsequent stage of manufacture in accordance with an embodiment. At this stage of manufacture, a non-conductive layer <NUM> is deposited or otherwise formed over the active side of the semiconductor die <NUM> and the first surface <NUM> of the encapsulant <NUM>. The non-conductive layer <NUM> may be formed from suitable non-conductive materials such as EMC, Ajinomoto build-up film (ABF), photosensitive dielectric material, and the like.

<FIG> illustrates, in a simplified cross-sectional view, the example semiconductor device <NUM> at a subsequent stage of manufacture in accordance with an embodiment. At this stage of manufacture, an opening <NUM> is formed in the non-conductive layer <NUM>. The opening <NUM> is formed through the non-conductive layer <NUM> and located over the bond pad <NUM> such that a substantial portion of a top surface of the bond pad <NUM> is exposed. Sidewalls <NUM> of the opening <NUM> surround the exposed portion of the bond pad <NUM> and form a perimeter of the opening. In this embodiment, the opening <NUM> is formed by way of high energy laser ablation. By forming the opening <NUM> in this manner, sidewalls of the opening may result with a rough texture thus providing improved adhesion with the UBM structure formed at a subsequent stage, for example. In some embodiments, the opening <NUM> may be formed by using known mask patterning and wet or dry chemical etch process methods.

<FIG> and <FIG> illustrate, in simplified plan and cross-sectional views, the example semiconductor device <NUM> at a subsequent stage of manufacture in accordance with an embodiment. For example, <FIG> depicts a bottom-side-up plan view <NUM> of the portion of the semiconductor device <NUM> and <FIG> depicts a cross-sectional view corresponding with <FIG>. At this stage, a laser ablated trench <NUM> is formed in the non-conductive layer <NUM> proximate to a perimeter of the opening <NUM> and substantially surrounding (e.g., encircling) the opening.

In this embodiment, the laser ablated trench <NUM> is formed at a first (e.g., outermost) surface <NUM> of the non-conductive layer <NUM>. The laser ablated trench <NUM> is configured to enhance adhesion between the non-conductive layer <NUM> and the UBM structure formed at a subsequent stage, for example. The laser ablated trench <NUM> may be formed by way of a low energy laser, for example, configured to remove material at the first surface <NUM> of the non-conductive layer <NUM>. By forming the laser ablated trench <NUM> in this manner, a bottom surface of the trench may result with a substantially roughened texture configured for improved adhesion. The laser ablated trench <NUM> may be formed having desired cross-sectional depth <NUM> and width <NUM> dimensions sufficient for enhancing adhesion between the non-conductive layer <NUM> and the subsequent UBM. For example, it may be desirable to form the laser ablated trench <NUM> with a predetermined cross-sectional depth <NUM> in a range of <NUM>% to <NUM>% of the thickness dimension <NUM> of the non-conductive layer <NUM>. In this embodiment, a portion of the first surface <NUM> of the non-conductive layer <NUM> remains between the inner side wall of the laser ablated trench <NUM> and the perimeter of the opening <NUM>.

<FIG> and <FIG> illustrate, in simplified plan and cross-sectional views, the example semiconductor device <NUM> at an alternate stage of manufacture in accordance with an embodiment. For example, <FIG> depicts a bottom-side-up plan view <NUM> of the portion of the semiconductor device <NUM> and <FIG> depicts a cross-sectional view corresponding with <FIG>. At this stage, a laser ablated trench <NUM> is formed in the non-conductive layer <NUM> extending into the opening <NUM> and substantially surrounding (e.g., encircling) the opening. The laser ablated trench <NUM> depicted in <FIG> and <FIG> is an alternative to the laser ablated trench <NUM> depicted in <FIG> and <FIG>.

In this embodiment, the laser ablated trench <NUM> is formed at the first surface <NUM> of the non-conductive layer <NUM> in a somewhat similar manner as the laser ablated trench <NUM>. However, the laser ablated trench <NUM> includes an outer sidewall without an inner sidewall thus having a cross-sectional depth continuous from the outer sidewall through to the opening <NUM> as depicted in <FIG>. By forming the laser ablated trench <NUM> in this manner, a larger bottom surface area of the trench results with the substantially roughened texture configured for further improved adhesion between non-conductive layer <NUM> and the subsequent UBM structure. In this embodiment, no portion of the first surface <NUM> of the non-conductive layer <NUM> remains between the outer sidewall of the laser ablated trench <NUM> and the opening <NUM>.

<FIG> illustrates, in a simplified cross-sectional view, the example semiconductor device <NUM> at a subsequent stage of manufacture in accordance with an embodiment. At this stage of manufacture, a seed layer <NUM> is formed over the non-conductive layer <NUM> and exposed bond pad <NUM> to expose a portion of the surface of the bond pad. In this embodiment, the seed layer <NUM> is sputtered, deposited, or otherwise applied on the first surface <NUM> of the non-conductive layer <NUM>, the sidewalls and bottom surface of the laser ablated trench <NUM>, the sidewalls of the opening <NUM>, and the exposed surface of the bond pad <NUM>. The seed layer <NUM> may be formed as a relatively thin layer (e.g., ~<NUM>-<NUM> microns) and may include titanium, tungsten, palladium, copper, or suitable combinations thereof suitable for plating an UBM structure with a conductive material such as copper. The seed layer <NUM> may also serve as a barrier layer to avoid diffusion into the bond pad <NUM> and enhance adhesion to underlying non-conductive layer <NUM>.

<FIG> illustrates, in a simplified cross-sectional view, the example semiconductor device <NUM> at a subsequent stage of manufacture in accordance with an embodiment. At this stage of manufacture, a conductive layer <NUM> is formed on the seed layer <NUM> to form the UBM structure <NUM>. In this embodiment, a plating mask layer <NUM> is applied on the seed layer <NUM> and patterned to define predetermined areas to be plated (e.g., UBM structures). After the plating mask layer <NUM> is patterned, the semiconductor device <NUM> is subjected to a plating process. In this embodiment, the conductive layer <NUM> includes a copper material and is formed by utilizing the seed layer <NUM> in a copper plating process. The copper plating process may be characterized as an electroless process or an electroplating process. The plated conductive layer <NUM> forms a conformal conductive layer over the exposed bond pad <NUM> as well as the laser ablated trench <NUM> of the UBM structure <NUM>. In some embodiments, the conductive layer <NUM> may be incorporated a redistribution layer (RDL) of a package substrate.

<FIG> illustrates, in a simplified cross-sectional view, the example semiconductor device <NUM> at a subsequent stage of manufacture in accordance with an embodiment. At this stage of manufacture, a conductive connector <NUM> (e.g., solder ball) is attached to the UBM structure <NUM>. The conductive connector <NUM> is placed onto the UBM structure <NUM> and reflowed. A flux material may be applied to the surface of UBM structure <NUM> before placing the conductive connector <NUM> onto the UBM structure to improve wetting and adhesion. In this embodiment, the conductive connector <NUM> is formed as a solder ball. In other embodiments, the conductive connector <NUM> may be in the form of a suitable conductive structure such as a solder bump, gold stud, copper pillar, or the like. After attaching the conductive connector <NUM> to the UBM structure <NUM>, an anti-tarnish or preservative material may be applied over exposed portions of the conductive layer <NUM>. The anti-tarnish or preservative material may bond with the conductive layer <NUM> in a manner that protects exposed surfaces of the conductive layer <NUM> from oxidation or corrosion, for example.

In one embodiment, there is provided, a method including forming a non-conductive layer over an active side of a semiconductor die, the semiconductor die partially encapsulated with an encapsulant; forming an opening in the non-conductive layer, the opening exposing a portion of a bond pad of the semiconductor die; forming a laser ablated trench at a first surface of the non-conductive layer proximate to a perimeter of the opening, a bottom surface of the laser ablated trench substantially roughened; and plating to form an under-bump metallization (UBM) structure over the bond pad and laser ablated trench. The laser ablated trench may be formed at least partially surrounding the perimeter of the opening. The substantially roughed bottom of the laser ablated trench may be continuous into the opening. The method may further include affixing a conductive connector to the UBM structure. The method may further include after forming the laser ablated trench, applying a seed layer on the non-conductive layer and the exposed portion of the bond pad. The method may further include patterning a mask layer on the seed layer before plating to form the UBM structure. The method may further include after plating to form the UBM structure, removing the mask layer and the seed layer portion underlying the mask layer. The laser ablated trench may have a depth in a range of <NUM>% to <NUM>% of a thickness of the non-conductive layer. The opening may be formed by way of laser ablation at a higher energy level than that of the formation of the laser ablated trench.

In another embodiment, there is provided, a semiconductor device including a semiconductor die partially encapsulated with an encapsulant, an active side of the semiconductor die exposed and substantially coplanar with a first surface of the encapsulant; a non-conductive layer formed over the active side of the semiconductor die and the first surface of the encapsulant; an opening formed in the non-conductive layer exposing a portion of a bond pad of the semiconductor die; a laser ablated trench formed at a first surface of the non-conductive layer proximate to a perimeter of the opening, a bottom surface of the laser ablated trench substantially roughened; and an under-bump metallization (UBM) structure formed over the bond pad and laser ablated trench. The laser ablated trench may be formed at least partially surrounding the perimeter of the opening. The substantially roughed bottom of the laser ablated trench may be continuous into the opening. The semiconductor device may further include a conductive connector affixed to the UBM structure, the conductive connector configured for connection to a printed circuit board. The non-conductive layer may be formed as an Ajinomoto build-up film (ABF). The laser ablated trench may have a depth in a range of <NUM>% to <NUM>% of a thickness of the non-conductive layer.

In yet another embodiment, there is provided, a method including forming a non-conductive layer over an active side of a semiconductor die and a first surface of an encapsulant, the encapsulant partially encapsulating the semiconductor die; forming a laser ablated opening in the non-conductive layer exposing a portion of a bond pad of the semiconductor die; forming a laser ablated trench at a first surface of the non-conductive layer proximate to a perimeter of the opening, a bottom surface of the laser ablated trench substantially roughened; and plating to form an under-bump metallization (UBM) structure over the bond pad and laser ablated trench. The laser ablated trench may be formed at least partially surrounding the perimeter of the laser ablated opening. The substantially roughed bottom of the laser ablated trench may be continuous into the laser ablated opening. The method may further include affixing a conductive connector to the UBM structure. The laser ablated trench may have a depth in a range of <NUM>% to <NUM>% of a thickness of the non-conductive layer.

By now, it should be appreciated that there has been provided a semiconductor device with an under-bump metallization (UBM) structure. The semiconductor device includes a semiconductor die partially encapsulated with an encapsulant. An active side of the semiconductor die is exposed and coplanar with a surface of the encapsulant. A non-conductive layer is formed over an active side of semiconductor die and surface of the encapsulant. An opening in the non-conductive layer is formed to expose a bond pad. A laser ablated trench is formed at the surface of the non-conductive layer near a perimeter of the opening. By using a low energy laser to form the trench, a bottom surface of the trench is roughened. The UBM structure is formed by plating over the trench and exposed pad region. The rough texture of the trench allows for superior adhesion of the UBM structure at the trench. By forming the UBM in this manner, potential stress induced delamination is minimized thus improving overall reliability of the semiconductor device.

The terms "front," "back," "top," "bottom," "over," "under" and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Claim 1:
A method comprising:
forming a non-conductive layer over an active side of a semiconductor die, the semiconductor die partially encapsulated with an encapsulant;
forming an opening in the non-conductive layer, the opening exposing a portion of a bond pad of the semiconductor die;
forming a laser ablated trench at a first surface of the non-conductive layer proximate to a perimeter of the opening, a bottom surface of the laser ablated trench being substantially roughened; and
plating to form an under-bump metallization, UBM, structure over the bond pad and laser ablated trench.