Patent Description:
<NPL>" relates to mitigating row-locality interference from host to near data accelerators (NDAs), reducing read/write-turnaround overhead caused by fine-grain interleaving of host and NDA requests, architecting a memory layout that supports the locality required for NDAs and sophisticated address interleaving for host performance, and supporting both packetized and traditional memory interfaces.

Double-data rate (DDR) type dynamic random access memories (DRAMs) are organized into multiple memory banks that enable successive read or write accesses to an activated row, within a particular bank or bank group, at a frequency that is in the <NUM>-<NUM> range. This maximum frequency of successive accesses may also be known as the core frequency (abbreviated herein as CF. ) However, as integrated circuit fabrication technology advances, the input/output interface frequencies and bandwidths of these DRAMs are increasing from generation to generation in order to keep up with increasing application performance requirements and system clock frequencies/bandwidths.

In an embodiment, the memory banks of a memory device are arranged and operated in groups (i.e., bank groups) and the groups are further arranged and operated as clusters of these groups (i.e., bank group clusters. ) In this arrangement, successive accesses to banks that are within different bank group clusters may be issued at a first (i.e., minimum) time interval (e.g., tmin=[<NUM>×CF]-<NUM>. ) Successive accesses to banks that are within different bank groups within the same cluster can be issued no faster than a second (i.e., intermediate that is greater than the minimum) time interval (e.g., tintmd=[<NUM>×CF]-<NUM>. ) And, successive accesses to banks that are within the same bank group may be issued no faster than a third (i.e., maximum that is greater than the intermediate) time interval (e.g., tmax=CF-<NUM>.

In an embodiment, the memory banks of a memory device may have multiple rows open at the same time. When a row shares a sense amplifier with another row that is already open, the row may not be opened until the other row is closed. Thus, at any given time, some rows may be 'blocked' from being opened based on which rows are presently open. The memory banks are arranged and operated in groups (i.e., bank groups). Successive accesses to banks that are within different bank groups may be issued at a first (i.e., minimum) time interval (e.g., tmin=[<NUM>×CF]-<NUM>. ) Successive accesses to banks that are within the same bank group can be issued no faster than a second (i.e., intermediate that is greater than the minimum) time interval (e.g., tintmd=[<NUM>×CF]-<NUM>. ) And, successive accesses to simultaneously open rows of the same bank may be issued no faster than a third (i.e., maximum that is greater than the intermediate) time interval (e.g., tmax=CF-<NUM>.

<FIG> is a block diagram of a memory system. In <FIG>, memory system <NUM> comprises controller <NUM>, and memory component <NUM>. Memory component <NUM> includes memory banks 151a-151c, 152a-152c, 153a-153c, 154a-154c, multiplex/demultiplex (MUX/DEMUX) function <NUM>, and data interface <NUM>. Memory banks 151a-151c, 152a-152c, 153a-153c, 154a-154c are arranged and coupled as members of bank groups <NUM>, <NUM>, <NUM>, <NUM>, respectively. Bank groups <NUM>-<NUM> are arranged and coupled as members of bank group cluster 131a. Bank groups <NUM>-<NUM> are arranged and coupled as members of bank group cluster 131b. Additional memory banks, bank groups, and/or bank group clusters (not shown in <FIG> for the sake of brevity) may be included as parts of memory device <NUM>.

Bank group <NUM> includes MUX/DEMUX function 145a. MUX/DEMUX function 145a is operatively coupled to memory banks 151a-151c and MUX/DEMUX function 135a of bank group cluster 131a. Bank group <NUM> includes MUX/DEMUX function 145b. MUX/DEMUX function 145b is operatively coupled to memory banks 152a-152c and MUX/DEMUX function 135a of bank group cluster 131a.

Bank group <NUM> includes MUX/DEMUX function 145c. MUX/DEMUX function 145c is operatively coupled to memory banks 153a-153c and MUX/DEMUX function 135b of bank group cluster 131b. Bank group <NUM> includes MUX/DEMUX function 145d. MUX/DEMUX function 145d is operatively coupled to memory banks 154a-154c and MUX/DEMUX function 135b of bank group cluster 131b.

MUX/DEMUX functions 135a-135b are operatively coupled to MUX/DEMUX function <NUM>. MUX/DEMUX function <NUM> is operatively coupled to data interface <NUM>. Data interface <NUM> is operatively coupled to controller <NUM>.

Controller <NUM> and memory component <NUM> may be integrated circuit type devices, such as are commonly referred to as "chips". A memory controller, such as controller <NUM>, manages the flow of data going to and from memory devices and/or memory modules. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller may be included on a single die with a microprocessor, or included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC).

Controller <NUM> is operatively coupled to memory component <NUM> via at least one command address (CA) interface. Controller <NUM> is operatively coupled to memory component <NUM> to send commands to memory component <NUM>. Memory component <NUM> receives the commands (and addresses) via a corresponding command address interface.

It should be understood that MUX/DEMUX functions <NUM>, 135a-135b, and 145a-145d operate to steer data to/from their respective inputs and outputs. MUX/DEMUX functions <NUM>, 135a-135b, and 145a-145d may be or comprise shared signal busses with local, intermediate, and/or global routing, pass-gates, multiplexors, demultiplexers, other logic, and/or tri-state buffers operatively coupled to drive and steer data to/from memory banks 151a-151c, 152a-152c, 153a-153c, 154a-154c and data interface <NUM>.

The memory banks 151a-151c, 152a-152c, 153a-153c, 154a-154c of memory device <NUM> are arranged and operated in bank groups <NUM>-<NUM>. Bank groups <NUM>-<NUM> are further arranged and operated as bank group clusters 131a-131b. Thus, memory device <NUM> is configured as a three-level hierarchical grouping of banks (<NUM>st level) into bank groups (<NUM>nd level), and bank groups into bank group clusters (<NUM>rd level.

In an embodiment, the hierarchical grouping of banks determines the minimum successive access timing between different banks. In particular, successive accesses to different banks that are within the same bank group require a longer time between accesses than successive accesses to banks that are in a different bank group. Also, successive accesses to different banks that are within the same bank group cluster require a longer time between accesses than successive accesses to banks that are in a different bank group cluster.

As set forth herein, it should be understood that the column to column minimum delay intervals described herein are merely an example. The hierarchical grouping of banks also affect the command to like (or same) command timing minimum delay intervals Some example command to command delay interval parameters are given in Table <NUM>.

It should also be understood that a similar set of hierarchical timing constraints, with different values, may be specified for devices that have different back-to-back delay intervals for read as compared to write operations (e.g., tCCD_RD_L ≠ tCCD_WR_L, tCCD_RD_M ≠ tCCD_WR_M, etc.) However, for the sake of brevity, the discussion herein is limited read operation and write operation timings that are assumed to be equal (i.e., (e.g., tCCD_RD_L = tCCD_WR_L, tCCD_RD_M = tCCD_WR_M, etc.) Memory devices that that have internal error correction code circuitry are an example of memory devices that may have different read operation and write operation timings.

For example, when successive accesses are to bank 151a and then bank 151c, the data associated with the second access (i.e., to/from bank 151c) needs to propagate through MUX/DEMUX function 145a, MUX/DEMUX function 135a, and MUX/DEMUX function <NUM> to reach or be sourced from interface <NUM>. However, when successive accesses are to bank 151a (in bank group <NUM> of bank group cluster 131a) and then bank 152b (in bank group <NUM> of bank group cluster 131a), the data associated with the second access (i.e., to/from bank 152b) can be waiting at the input/output of MUX/DEMUX function 145b and therefore does not need to propagate through MUX/DEMUX function 145a before propagating through MUX/DEMUX function 135a, and MUX/DEMUX function <NUM> to reach or be sourced from interface <NUM>. Thus, the timing between successive accesses to different banks that are within the same bank group is specified as a longer time than successive accesses to different banks that are in different bank groups.

Using column to column operations as an example, the interval between back-to-back column accesses to different banks that are both within the same bank group (a. , "long" tCCD_L which may be in the range of <NUM>-<NUM> ns) is specified as a longer time than successive column accesses to banks that are not in the same bank group (e.g., tCCD_M in the range of <NUM>-<NUM> ns). In another example, the interval between back-to-back row accesses to different banks that are both within the same bank group (a. , "long" tRRD_L) is specified as a longer time than successive row accesses to banks that are not in the same bank group (e.g., tRRD_M).

The hierarchical grouping of banks also determines the minimum back-to-back access timing between banks that are in different bank group clusters. In particular, successive accesses to banks that are within the same bank group cluster require a longer time between accesses than successive accesses to banks that are in a different bank group cluster.

For example, when successive accesses are to bank 151a (in bank group <NUM> of bank group cluster 131a) and then bank 152b (in bank group <NUM> of bank group cluster 131a), the data associated with the second access (i.e., to/from bank 152b) needs to propagate through MUX/DEMUX function 135a before propagating through MUX/DEMUX function <NUM> to reach or be sourced from interface <NUM>. However, when successive accesses are to bank 151a (in bank group <NUM> of bank group cluster 131a) and then bank 154b (in bank group <NUM> of bank group cluster 131b), the data associated with the second access (i.e., to/from bank 154b) can be waiting at the input/output of MUX/DEMUX function <NUM> and therefore does not need to propagate through MUX/DEMUX function 135a before propagating through MUX/DEMUX function <NUM> to reach or be sourced from interface <NUM>. Thus, the timing between successive accesses to different banks that are within the same bank group cluster (e.g., tCCD_M) is specified as a longer time than successive accesses to banks that are in different a bank group cluster (e.g., tCCD_S in the range of <NUM>-<NUM> ns).

Put another way, successive accesses to different bank group clusters may be issued at a first (i.e., minimum) time interval (e.g., tmin=[<NUM>×CF]-<NUM> as governed by tCCD_S. ) Successive accesses to banks that are within different bank groups within the same cluster can be issued no faster than a second (i.e., intermediate that is greater than the minimum) time interval (e.g., tintmd=[<NUM>×CF]-<NUM> as governed by tCCD_M. ) And, successive accesses to banks that are within the same bank group may be issued no faster than a third (i.e., maximum that is greater than the intermediate) time interval (e.g., tmax=CF-<NUM> as governed by tCCD_L. ) These timings are further illustrated with reference to <FIG>.

Controller <NUM> includes scheduling logic (not shown in <FIG>) to issue, to memory device <NUM>, accesses to memory banks 151a-151c, 152a-152c, 153a-153c, 154a-154c. Again, using column to column minimum delay as an example, the scheduling logic of controller <NUM> may use first column to column delay (tCCD_S) for successive column accesses to memory banks 151a-151c, 152a-152c, 153a-153c, 154a-154c that are members of different bank group clusters 131a-131b. The scheduling logic of controller <NUM> may use a second column to column delay (tCCD_M) for successive column accesses to memory banks 151a-151c, 152a-152c that are members of the same bank group cluster (e.g., 131a) but different bank groups of that bank group cluster (e.g., bank group <NUM> and bank group <NUM> of bank group cluster 131a). The scheduling logic of controller <NUM> may use a third column to column delay (tCCD_L) for successive column accesses to memory banks 151a-151c that are members of the same bank group (e.g., bank group <NUM>) and same bank group cluster (e.g., 131a.

In another example using row to row operations, the scheduling logic of controller <NUM> may use first row to row delay (tRRD_S) for successive row accesses to memory banks 151a-151c, 152a-152c, 153a-153c, 154a-154c that are members of different bank group clusters 131a-131b. The scheduling logic of controller <NUM> may use a second row to row delay (tRRD_M) for successive row accesses to memory banks 151a-151c, 152a-152c that are members of the same bank group cluster (e.g., 131a) but different bank groups of that bank group cluster (e.g., bank group <NUM> and bank group <NUM> of bank group cluster 131a). The scheduling logic of controller <NUM> may use a third row to row delay (tRRD_L) for successive row accesses to memory banks 151a-151c that are members of the same bank group (e.g., bank group <NUM>) and same bank group cluster (e.g., 131a.

It should be understood that memory components (e.g. memory component <NUM>) may receive a clock signal that serves as a timing reference. The intervals described herein may thus be expressed as a number of cycles of the reference clock frequency. Because memory components may be operated at different reference clock frequencies, the intervals described herein may be expressed in terms of intervals that are rounded up to an integer number of clock cycles (or phases) of the timing reference.

<FIG> is an illustration of multiple command to command delays. In <FIG>, column accesses are used as example commands for illustration purposes. However, other types of commands and delays (e.g., those detailed in Table <NUM>) may follow a similar or equivalent pattern. A first example read command (RD1) is issued by controller <NUM> and received by memory component <NUM>. The address associated with the RD1 command specifies the bank group cluster address as BC1 <NUM>, the bank group address as BG1 <NUM>, the bank address as BA1 <NUM>, and the column address as COL1. If, for a subsequent command, a new bank group cluster address is provided (e.g., BC2 where BC1 ≠ BC2) the subsequent command may be issued/received in the shortest amount of time later (i.e., tCCD_S) or greater after the first command. This timing is illustrated in <FIG> by the tCCD_S delay from the first read command (RD1) to the second read command (RD2) and the change in bank group cluster address from BC1 <NUM> to BC2 <NUM>. Note that as long as BC1 ≠ BC2, there are no additional constraints on the subsequent bank group (BG2), bank address (BA2), and/or column (COL2) addresses in order to issue/receive the successive command in the shortest amount of time later (i.e., tCCD_S).

If, for a subsequent command (RD3) after the second command (RD2), the bank group cluster address is the same as the second command (BC2), but a new bank group address is provided (e.g., BG3 ≠ BG2) the subsequent (RD3) command may be issued/received at the intermediate amount of time (i.e., tCCD_M) or greater after the second command. This timing is illustrated in <FIG> by the tCCD_M delay from the second read command (RD2) to the third read command (RD3), the same bank group cluster address BC2 <NUM> and <NUM>, and the change in bank group address from BG2 <NUM> to BG3 <NUM>. Note that when the bank group cluster address is the same as the previous command, and a new bank group address is provided (e.g., BG3), there are no additional constraints on the bank address (BA3), and/or column (COL3) addresses in order to issue/receive the successive command in the intermediate amount of time later (i.e., tCCD_M).

If, for a subsequent command (RD4) after the third command (RD3), the bank group cluster address and the bank group are the same as the third command, but a new bank address is provided (e.g., BA4 ≠ BA3) the subsequent command may be issued/received the longest amount of time later (i.e., tCCD_L) or greater after the third command. This timing is illustrated in <FIG> by the tCCD_L delay from the third read command (RD3) to the fourth read command (RD4), the same bank group cluster address BC2 <NUM> and <NUM>, the same bank group address BG3 <NUM> and <NUM>, and the change in the bank address from BA3 <NUM> to BA4 <NUM>. Note that when the bank group cluster address and the bank group are the same as the previous command, and a new bank address is provided (e.g., BA4), there are no additional constraints on the column (COL) address in order to issue/receive the successive command in the longest amount of time later (i.e., tCCD_L). Table <NUM> summarizes the timing constraints described herein with reference to <FIG>.

In an embodiment, the scheduling logic of controller <NUM>, and/or memory component <NUM>, may be configured (e.g., by registers or commands) to use the longest timings for all back-to-back accesses. When in this mode, the scheduling performed by controller <NUM>, and the internal timings of memory device <NUM>, are simplified. However, when in the hierarchical (i.e., bank group cluster) mode described herein with reference to <FIG>, the better optimized multi-level timings may be used based on the accesses.

<FIG> is a notional illustration of a physical arrangement of banks in a memory device and example signal paths. In <FIG>, arrays of memory banks are hierarchically grouped into bank groups and the bank groups grouped into bank group clusters. A first signal path runs between bank 351a to interface and serializer <NUM>. Data is transferred between bank 351a and datapath circuitry shared within a bank group (e.g., MUX/DEMUX functions, buffers, common signal lines, logic, etc.). This is illustrated in <FIG> by lines <NUM> (between bank 351a and line <NUM>) and <NUM> (between bank 351b and line <NUM>). The datapath circuitry shared within the same bank group may run at a core frequency governed by the longest column to column delay timing (e.g., tCCD_L = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency.

Data is transferred between datapath circuitry shared within a bank group and datapath circuitry shared within a bank group cluster. This is illustrated in <FIG> by lines <NUM> (between bank 351a's bank group and line <NUM>) and <NUM> (between bank 352a's bank group and line <NUM>). The datapath circuitry shared within the same bank group cluster may run at a frequency governed by the intermediate column to column delay timing (e.g., tCCD_M = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle core frequency.

Data is transferred between datapath circuitry shared within a bank group cluster and datapath circuitry shared between all bank group clusters. This is illustrated in <FIG> by lines <NUM> (between bank 351a's bank group cluster and serializer <NUM>) and <NUM> (between bank 354a's bank group cluster and serializer <NUM>). The datapath circuitry shared between bank group clusters may run at a frequency governed by the shortest column to column delay timing (e.g., tCCD_S = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency.

<FIG> is an illustration of a memory system. In <FIG>, memory system <NUM> comprises controller <NUM>, and memory component <NUM>. Memory component <NUM> includes memory banks <NUM>-<NUM>, multiplex/demultiplex (MUX/DEMUX) function <NUM>, and data interface <NUM>. Memory banks <NUM>-<NUM> are arranged and coupled as members of bank group 431a. Memory banks <NUM>-<NUM> are arranged and coupled as members of bank group 431b. Additional memory banks, bank groups, and/or bank group clusters (not shown in <FIG> for the sake of brevity) may be included as parts of memory device <NUM>.

Bank group 431a also includes MUX/DEMUX function 435a. MUX/DEMUX function 435a is operatively coupled to memory banks <NUM>-<NUM>. Memory bank <NUM> includes MUX/DEMUX function 445a. Memory bank <NUM> includes MUX/DEMUX function 445b. MUX/DEMUX functions 445a-445b are operatively coupled to MUX/DEMUX function 435a.

Bank group 431b also includes MUX/DEMUX function 435b. MUX/DEMUX function 435b is operatively coupled to memory banks <NUM>-<NUM>. Memory bank <NUM> includes MUX/DEMUX function 445c. Memory bank <NUM> includes MUX/DEMUX function 445d. MUX/DEMUX functions 445c-445d are operatively coupled to MUX/DEMUX function 435b.

MUX/DEMUX functions 435a-435b are operatively coupled to MUX/DEMUX function <NUM>. MUX/DEMUX function <NUM> is operatively coupled to data interface <NUM>. Data interface <NUM> is operatively coupled to controller <NUM>.

Controller <NUM> and memory component <NUM> may be integrated circuit type devices, such as are commonly referred to as a "chips". A memory controller, such as controller <NUM>, manages the flow of data going to and from memory devices and/or memory modules A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller may be included on a single die with a microprocessor, or included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC).

Controller <NUM> is operatively coupled to memory <NUM> via at least one command address (CA) interface. Controller <NUM> is operatively coupled to memory <NUM> to send commands to memory <NUM>. Memory <NUM> receives the commands (and addresses) via a corresponding command address interface.

It should be understood that MUX/DEMUX functions <NUM>, 435a-435b, and 445a-445d operate to steer data to/from their respective inputs and outputs. MUX/DEMUX functions <NUM>, 435a-435b, and 445a-445d may be or comprise shared signal busses with local, intermediate, and/or global routing, pass-gates, multiplexors, demultiplexers, other logic, and/or tri-state buffers operatively coupled to drive and steer data to/from rows of memory banks <NUM>-<NUM> and data interface <NUM>.

Memory device <NUM> may have multiple rows in the same bank <NUM>-<NUM> open concurrently. Controller <NUM> divides the address space of banks <NUM>-<NUM> into segments 451a-451b, 452a-452b, 453a-453b, 454a-454b based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's <NUM>-<NUM> subarrays (a. memory array tiles - MATs). When a command is sent to open a row, controller <NUM> marks a plurality of the segments (i.e., row address ranges) as blocked. Controller <NUM> thereby tracks address ranges in a bank <NUM>-<NUM> where it will not open a second row unless and until the first row is closed. In an embodiment, memory device <NUM> may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by controller <NUM> during initialization.

Because more than one row in a bank may be open concurrently, column access operations sent to memory <NUM> specify which row is the subject of the column access. In an embodiment, the entire row address is used to specify the subject row. In another embodiment, a map of open rows to tag values is maintained by memory <NUM>. Controller <NUM> sends a tag value to specify the subject row. These tag values may be generated, for example, using a function (e.g., hash) of the row address, using a count of the open rows, or using a priority encoder.

In an embodiment, memory <NUM> is configured such that multiple rows in the same bank <NUM>-<NUM> may be open concurrently as long as the open rows are in segments 451a-451b, 452a-452b, 453a-453b, 454a-454b that do not interfere with each other. Thus, for example, when memory <NUM> activates a row in bank <NUM>, the sense amplifier stripes surrounding the row are used to activate the addressed row and the rest of the sense amplifier stripes in the bank <NUM> do not participate in the activation.

Controller <NUM> may include a scheduler. The scheduler selects transactions/commands to be sent to memory <NUM>. This scheduler may maintain respective address tables for banks <NUM>-<NUM> that indicate which address ranges (i.e., segments 451a-451b, 452a-452b, 453a-453b, 454a-454b) are blocked due to open rows. The entries in the address tables may correspond to respective address ranges (i.e., segments) and hold one or more indicators of whether the address range is available or unavailable for opening a row in that address range. The entries in the address tables may comprise a single bit or other value corresponding to whether or not the address range is available for opening a row. The entries in the address tables may comprise a value that tracks when an address range will become available. For example, when memory <NUM> is configured to auto-precharge, a timer value may be incremented or decremented under certain conditions to track when the precharge will be complete and therefore the address range becomes available.

Further discussion of segments 451a-451b, 452a-452b, 453a-453b, 454a-454b, memory device <NUM>, and their operation and control by controller <NUM> is provided in <CIT>, titled "MEMORY SYSTEM WITH MULTIPLE OPEN ROWS PER BANK".

The memory banks <NUM>-<NUM> of memory device <NUM> are arranged and operated in bank groups 431a-431b. Thus, memory device <NUM> may be viewed as a three-level hierarchical grouping of segments (1st level) into banks (2nd level), and banks into bank groups (3rd level.

In an embodiment, the hierarchical grouping of segments, banks, and bank groups determines the minimum successive access timing between different segments. In particular, successive accesses to different (non-blocked) segments that are within the same bank require a longer time between accesses than successive accesses to segments that are in a different bank group.

As set forth herein, it should be understood that the column to column minimum delay intervals described herein are merely an example. The hierarchical grouping of segments, banks, and bank groups also affect the command to like (or same) command timing minimum delay intervals Some example command to command delay interval parameters are given in Table <NUM>.

It should also be understood that a similar set of set of hierarchical timing constraints, with different values, may be specified for devices that have different back-to-back delay intervals for read as compared to write operations (e.g., tCCD_RD_L ≠ tCCD_WR_L, tCCD_RD_M ≠ tCCD_WR_M, etc.) However, for the sake of brevity, the discussion herein is limited read operation and write operation timings that are assumed to be equal (i.e., (e.g., tCCD_RD_L = tCCD_WR_L, tCCD_RD_M = tCCD_WR_M, etc.).

Using column to column operations as an example, when successive accesses are to segment 451a and then segment 451b, the data associated with the second access (i.e., to/from segment 451b) needs to propagate through MUX/DEMUX function 445a, MUX/DEMUX function 435a, and MUX/DEMUX function <NUM> to reach or be sourced from interface <NUM>. However, when successive accesses are to segment 451a (in bank <NUM> of bank group 431a) and then segment 452b (in bank <NUM> of bank group 431a), the data associated with the second access (i.e., to/from segment 452b) can be waiting at the input/output of MUX/DEMUX function 445b and therefore does not need to propagate through MUX/DEMUX function 445a before propagating through MUX/DEMUX function 435a, and MUX/DEMUX function <NUM> to reach or be sourced from interface <NUM>. Thus, the timing between successive accesses to different segments that are within the same bank (e.g., tCCD_L in the range of <NUM>-<NUM> ns) is specified as a longer time than successive accesses to segments that are in a different bank (e.g., tCCD_M in the range of <NUM>-<NUM> ns).

The hierarchical grouping of segments also determines the minimum column to column access timing between segments that are in different bank groups. In particular, successive accesses to segments that are within the same bank group require a longer time between accesses than successive accesses to segments that are in a different bank group.

Continuing with using column to column operations as an example, when successive accesses are to segment 451a (in bank group 431a) and then to segment 452a (in bank group 431a), the data associated with the second access (i.e., to/from segment 452a) needs to propagate through MUX/DEMUX function 435a before propagating through MUX/DEMUX function <NUM> to reach or be sourced from interface <NUM>. However, when successive accesses are to segment 451a (in bank group 431a) and then segment 454b (in bank group 431b), the data associated with the second access (i.e., to/from segment 454b) can be waiting at the input/output of MUX/DEMUX function <NUM> and therefore does not need to propagate through MUX/DEMUX function 435a before propagating through MUX/DEMUX function <NUM> to reach or be sourced from interface <NUM>. Thus, the timing between successive accesses to different banks that are within the same bank group (e.g., tCCD_M) is specified as a longer time than successive accesses to banks that are in different a bank groups (e.g., tCCD_S in the range of <NUM>-<NUM> ns).

Put another way, successive accesses to segments that are in different bank groups may be issued at a first (i.e., minimum) time interval (e.g., tmin=[<NUM>×CF]-<NUM> as governed by tCCD_S. ) Successive accesses to segments that are in different banks within the same bank group can be issued no faster than a second (i.e., intermediate that is greater than the minimum) time interval (e.g., tintmd=[<NUM>×CF]-<NUM> as governed by tCCD_M. ) And, successive accesses to (non-blocked) segments that are within the same bank may be issued no faster than a third (i.e., maximum that is greater than the intermediate) time interval (e.g., tmax=CF-<NUM> as governed by tCCD_L. ) These timings are further illustrated with reference to <FIG>.

The scheduling logic of controller <NUM> issues, to memory device <NUM>, accesses to segments 451a-451b, 452a-452b, 453a-453b, 454a-454b. Again using column to column minimum delay as an example, the scheduling logic of controller <NUM> may use a first column to column delay (tCCD_S) for successive accesses to segments 451a-451b, 452a-452b, 453a-453b, 454a-454b that are parts of banks that are part of different bank groups 431a-431b, and a second column to column delay (tCCD_M) for successive accesses to memory segments 451a-451b, 452a-452b, 453a-453b, 454a-454b that are members of a first bank group (e.g., 131a) and different banks of the first bank group (e.g., bank <NUM> and bank <NUM> of bank group 431a). The scheduling logic of controller <NUM> uses a third column to column delay (tCCD_L) for successive accesses to segments 451a-451b that are members of a first bank (e.g., bank <NUM>) of the first bank group (e.g., 431a.

As discussed herein, the scheduler of controller <NUM> may issue commands that result in a plurality of rows of one or more memory banks <NUM>-<NUM> being open concurrently. Thus, controller <NUM> may include circuitry to associate indicators with a respective row address segments (ranges) of one or more banks. Circuitry of controller <NUM> may set the respective indicators to a first value that is associated with the respective row address segment of the first memory bank being unavailable (i.e., blocked) for opening a row in the associated respective row address range. A plurality of the respective indicators may be set to the first value in response to at least memory controller <NUM> processing a command to memory device <NUM> to open a row in the respective row address range of the memory bank <NUM>-<NUM> associated with at least one of the respective indicators. In other words, the opening of a row in one segment (e.g., 451a) in a bank <NUM> may cause other segments (e.g., 451b) to become unavailable (blocked).

<FIG> is an illustration of multiple command to command delays. In <FIG>, column accesses are used as example commands for illustration purposes. However, other types of commands and delays (e.g., those detailed in Table <NUM>) may follow a similar or equivalent pattern. A first example read command (RD1) is issued by controller <NUM> and received by memory component <NUM>. The address associated with this command specifies the bank group address as BG1 <NUM>, the bank address as BA1 <NUM>, the segment address as SEG1 <NUM>, and the column address as COL1. If, for a subsequent command, a new bank group address is provided (e.g., BG2 where BG1 ≠ BG2) the subsequent command may be issued/received in the shortest amount of time later (i.e., tCCD_S) or greater after the first command. This timing is illustrated in <FIG> by the tCCD_S delay from the first read command (RD1) to the second read command (RD2) and the change in bank group address from BG1 <NUM> to BG2 <NUM>. Note that as long as BG1 ≠ BG2, there are no additional constraints on the subsequent bank (BA), segment (SEG), and/or column (COL) addresses in order to issue/receive the successive command in the shortest amount of time later (i.e., tCCD_S).

If, for a subsequent command (RD3) after the second command (RD2), the bank group address is the same as the second command, but a new bank address is provided (e.g., BA3 ≠ BA2) the subsequent (RD3) command may be issued/received at the intermediate amount of time (i.e., tCCD_M) or greater after the first command. This timing is illustrated in <FIG> by the tCCD_M delay from the second read command (RD2) to the third read command (RD3), the same bank group address BG2 <NUM> and <NUM>, and the change in bank address from BA2 <NUM> to BA3 <NUM>. Note that when the bank group address is the same as the first command, and a new bank address is provided (e.g., BA3), there are no additional constraints on the segment (SEG), and/or column (COL) addresses in order to issue/receive the successive command in the intermediate amount of time later (i.e., tCCD_M).

If, for a subsequent command (RD4) after the third command (RD3), the bank group address and the bank address are the same as the first command, but a new segment address is provided (e.g., SEG4) the subsequent command may be issued/received the longest amount of time later (i.e., tCCD_L) or greater after the first command. This timing is illustrated in <FIG> by the tCCD_L delay from the third read command (RD3) to the fourth read command (RD4), the same bank group address BG2 <NUM> and <NUM>, the same bank address BA3 <NUM> and <NUM>, and the change in the segment address from SEG3 <NUM> to SEG4 <NUM>. Note that when the bank group address and the bank address are the same as the previous command, and a new segment address is provided (e.g., SEG4 ≠ SEG3), there are no additional constraints on the column (COL) address in order to issue/receive the successive command in the longest amount of time later (i.e., tCCD_L). Table <NUM> summarizes the timing constraints described herein with reference to <FIG>.

It should be understood that the foregoing description assumes tCCD_L applies for both subsequent accesses to different columns within the same bank group, same bank address, and same segment, and for subsequent accesses to different segments within the same bank group and same bank address. In an embodiment, different timings may apply for accesses to different columns within the same bank group, same bank address, and same segment, and for subsequent accesses to different segments within the same bank address.

In an embodiment, the scheduling logic of controller <NUM>, and/or memory component <NUM>, may be configured (e.g., by registers or commands) to use the longest timings for all back-to-back accesses. When in this mode, the scheduling performed by controller <NUM>, and the internal timings of memory device <NUM>, are simplified. However, when in the hierarchical (i.e., segment/bank/bank group) mode described herein with reference to <FIG>, the better optimized multi-level timings may be used based on the accesses.

<FIG> is an illustration of a first example of signal paths for bank group cluster accesses. In <FIG>, memory component <NUM> includes bank group cluster #<NUM> (BC1) 631a and bank group cluster #<NUM> (BC2) 631b. BC1 631a includes bank group #<NUM> (BG1) <NUM> and bank group #<NUM> (BG2) <NUM>. BC2 631b includes bank group #<NUM> (BG3) <NUM> and bank group #<NUM> (BG4) <NUM>. BG1 includes memory bank 651a and memory bank 651b. BG2 includes memory bank 652a and memory bank 652b. BG3 includes memory bank 653a and memory bank 653b. BG4 includes memory bank 654a and memory bank 654b.

Bank 651a and bank 651b are operatively coupled to datapath circuitry 635a (e.g., MUX/DEMUX functions, buffers, common signal lines, logic, etc.) Bank 652a and bank 652b are operatively coupled to datapath circuitry 635b. Datapath circuitry 635a is operatively coupled to datapath circuitry 635b. Bank 654a and bank 654b are operatively coupled to datapath circuitry 635c. Bank 653a and bank 653b are operatively coupled to datapath circuitry 635d. Datapath circuitry 635c is operatively coupled to datapath circuitry 635d. Datapath circuitry 635b and datapath circuitry 635d are operatively coupled to datapath circuitry 635e. Thus, to access a row in either bank 651a or 651b, data flows via datapath circuitry 635a, 635b, and 635e. Likewise, to access a row in either of bank 654a or 654b, data flows via datapath circuitry 635c, 635d, and 635e. To access a row in either of bank 652a or 652b, data flows via datapath circuitry 635b, and 635e. To access a row in either of bank 653a or 653b, data flows via datapath circuitry 635d, and 635e.

The datapath circuitry 635a shared by bank 651a and bank 651b may run at a frequency governed by the core column to column delay timing (e.g., tCCD_L = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency. ) Likewise, the datapath circuitry 635c shared by bank 654a and bank 654b may run at a frequency governed by the core column to column delay timing (e.g., tCCD_L = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency. ) The datapath circuitry 635b shared by bank 652a, bank 652b, and datapath 635a may run at a frequency governed by the intermediate column to column delay timing (e.g., tCCD_M = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency. ) Likewise, the datapath circuitry 635d shared by bank 653a, bank 653b, and datapath 635c may run at a frequency governed by the intermediate column to column delay timing (e.g., tCCD_M = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency. ) Finally, the datapath circuitry 635e which carries data for all of the banks 651a, 651b, 652a, 652b, 653a, 653b, 654a, and 654b may run at a frequency governed by the shortest column to column delay timing (e.g., tCCD_s = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency.

In example access operation, four units (e.g., byte, word, etc.) of data are transferred in to, or out of, a respectively addressed row in a respective bank 651a-654a. This is illustrated in <FIG> by lines 661a-664a. A first unit of data is transferred between a row in bank 651a via datapath 661a and 635a. Similarly, a second unit of data is transferred between a row in bank 654a via datapath 664a and 635c. The first unit of data is time multiplexed with a third unit of data to/from a row in bank 652a on datapath 635b. The second unit of data is time multiplexed with a fourth unit of data to/from a row in bank 653a on datapath 635d. All four units of data are time multiplexed on datapath 635e. Datapath 635e may operatively couple to input/output logic for memory component <NUM>. The multiplexing of data to/from banks 651a-654a is further described by way of example in <FIG>.

<FIG> is a timing diagram illustrating a bank group cluster access. In <FIG>, banks 651a-654a are being clocked by the signals CK-<NUM> to CK-<NUM>, respectively. CK-<NUM> is delayed by <NUM>° from CK-<NUM>. CK-<NUM> is delayed by <NUM>° from CK-<NUM>. CK-<NUM> is delayed by <NUM>° from CK-<NUM>.

On a rising edge of CK-<NUM>, a first unit of data is read out of bank 651a via datapath 661a and carried via datapath 635a. This is illustrated by arrow <NUM>. Datapath 635a couples the first unit of data to datapath 635b. This is illustrated by arrow <NUM>. Datapath 635b couples the first unit of data to datapath 635e. This is illustrated by arrow <NUM>.

On the next rising edge of CK-<NUM> a second unit of data is read out of bank 654a via datapath 664a and carried via datapath 635c. This is illustrated by arrow <NUM>. Datapath 635c couples the second unit of data to datapath 635d. This is illustrated by arrow <NUM>. Datapath 635d couples the second unit of data to datapath 635e. This is illustrated by arrow <NUM>.

On the next rising edge of CK-<NUM> a third unit of data is read out of bank 652a via datapath 662a. This is illustrated by arrow <NUM>. Datapath 662a couples the third unit of data to datapath 635b. This is illustrated by arrow <NUM>. Datapath 635b couples the third unit of data to datapath 635e. This is illustrated by arrow <NUM>.

On the next rising edge of CK-<NUM> a fourth unit of data is read out of bank 653a via datapath 663a. This is illustrated by arrow <NUM>. Datapath 663a couples the fourth unit of data to datapath 635d. This is illustrated by arrow <NUM>. Datapath 635d couples the fourth unit of data to datapath 635e. This is illustrated by arrow <NUM>.

<FIG> is an illustration of a second example of signal paths for bank group cluster accesses. In <FIG>, memory component <NUM> include bank group cluster #<NUM> (BC1) 731a and bank group cluster #<NUM> (BC2) 731b. BC1 731a includes bank group #<NUM> (BG1) <NUM> and bank group #<NUM> (BG2) <NUM>. BC2 731b includes bank group #<NUM> (BG3) <NUM> and bank group #<NUM> (BG4) <NUM>. BG1 <NUM> includes memory bank 751a and memory bank 751b. BG2 <NUM> includes memory bank 752a and memory bank 752b. BG3 <NUM> includes memory bank 753a and memory bank 753b. BG4 <NUM> includes memory bank 754a and memory bank 754b.

Bank 751a and bank 751b are operatively coupled to datapath circuitry 735a (e.g., MUX/DEMUX functions, buffers, common signal lines, logic, etc.) Bank 752a and bank 752b are operatively coupled to datapath circuitry 735b. Datapath circuitry 735a is operatively coupled to datapath circuitry 735b. Bank 754a and bank 754b are operatively coupled to datapath circuitry 735c. Bank 753a and bank 753b are operatively coupled to datapath circuitry 735d. Datapath circuitry 735c is operatively coupled to datapath circuitry 735d. Thus, to access a row in either bank 751a or 751b, data flows via datapath circuitry 735a and 735b. Likewise, to access a row in either of bank 754a or 754b, data flows via datapath circuitry 735c and 735d. To access a row in either of bank 752a or 752b, data flows via datapath circuitry 735b. To access a row in either of bank 753a or 753b, data flows via datapath circuitry 735d.

The datapath circuitry 735a shared by bank 751a and bank 751b may run at a frequency governed by the core column to column delay timing (e.g., tCCD_L = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency. ) Likewise, the datapath circuitry 735c shared by bank 754a and bank 754b may run at a frequency governed by the core column to column delay timing (e.g., tCCD_L = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency. ) The datapath circuitry 735b shared by bank 752a, bank 752b, and datapath 735a may run at a frequency governed by the intermediate column to column delay timing (e.g., tCCD_M = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency. ) Likewise, the datapath circuitry 735d shared by bank 753a, bank 753b, and datapath 735c may run at a frequency governed by the intermediate column to column delay timing (e.g., tCCD_M = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency.

In example access operation, four units (e.g., byte, word, etc.) of data are transferred in to, or out of, a respectively addressed row in a respective bank 751a-754a. This is illustrated in <FIG> by lines 761a-764a. A first unit of data is transferred between a row in bank 751a via datapath 761a and 735a. Similarly, a second unit of data is transferred between a row in bank 754a via datapath 764a and 735c. The first unit of data is time multiplexed with a third unit of data to/from a row in bank 752a on datapath 735b. The second unit of data is time multiplexed with a fourth unit of data to/from a row in bank 753a on datapath 735d. Datapaths 735b and 735d may operatively couple to input/output logic for memory component <NUM>. The multiplexing of data to/from banks 751a-754a is further described by way of example in <FIG>.

<FIG> is a timing diagram illustrating a bank group cluster access. In <FIG>, banks 751a-754a are being clocked by the signals CK-<NUM> to CK-<NUM>, respectively. CK-<NUM> is delayed by <NUM>° from CK-<NUM>. CK-<NUM> is delayed by <NUM>° from CK-<NUM>. CK-<NUM> is delayed by <NUM>° from CK-<NUM>.

On a rising edge of CK-<NUM>, a first unit of data is read out of bank 751a via datapath 761a and carried via datapath 735a. This is illustrated by arrow <NUM>. Datapath 735a couples the first unit of data to datapath 735b. This is illustrated by arrow <NUM>.

On the next rising edge of CK-<NUM> a second unit of data is read out of bank 754a via datapath 764a and carried via datapath 735c. This is illustrated by arrow <NUM>. Datapath 735c couples the second unit of data to datapath 735d. This is illustrated by arrow <NUM>.

On the next rising edge of CK-<NUM> a third unit of data is read out of bank 752a via datapath 762a. This is illustrated by arrow <NUM>. Datapath 762a couples the third unit of data to datapath 735b. This is illustrated by arrow <NUM>.

On the next rising edge of CK-<NUM> a fourth unit of data is read out of bank 753a via datapath 763a. This is illustrated by arrow <NUM>. Datapath 763a couples the fourth unit of data to datapath 735d. This is illustrated by arrow <NUM>.

It should be understood that the data carried by datapath 735b and datapath 735d may be further time-multiplexed together by additional circuitry not shown in <FIG> (e.g., data I/O circuitry such as data interface <NUM>). This time-multiplexing may result in a column to column delay visible to a memory controller that is governed by tCCD_S.

<FIG> is an illustration of a first example of signal paths for bank group accesses. In <FIG>, memory component <NUM> includes bank group #<NUM> (BG1) 831a and bank group #<NUM> (BG2) 831b. BG1 831a includes memory bank <NUM> and memory bank <NUM>. BG2 831b includes memory bank <NUM> and memory bank <NUM>. Memory bank <NUM> includes (non-blocked) segment <NUM>. Memory bank <NUM> includes (non-blocked) segment <NUM>. Memory bank <NUM> includes (non-blocked) segment <NUM>. Memory bank <NUM> includes (non-blocked) segment <NUM>.

Bank <NUM> and bank <NUM> are operatively coupled to datapath circuitry 835a (e.g., MUX/DEMUX functions, buffers, common signal lines, logic, etc.) Bank <NUM> and bank <NUM> are operatively coupled to datapath circuitry 835b. Datapath circuitry 835a is operatively coupled to datapath circuitry 835b. Thus, to access a row in either bank <NUM> or <NUM>, data flows via datapath circuitry 835a and 835b. Likewise, to access a row in either of bank <NUM> or <NUM>, data flows via datapath circuitry 835b.

The row access datapaths <NUM>-<NUM> may run at a frequency governed by the core column to column delay timing (e.g., tCCD_L = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency. ) The datapath circuitry 835a shared by bank <NUM> and bank <NUM> may run at a frequency governed by the intermediate column to column delay timing (e.g., tCCD_M = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency. ) The datapath circuitry 835b shared by bank <NUM>, bank <NUM>, and datapath 835a may run at a frequency governed by the shortest column to column delay timing (e.g., tCCD_S = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency.

In example access operation, four units (e.g., byte, word, etc.) of data are transferred in to, or out of, a respectively addressed row in a respective bank <NUM>-<NUM>. This is illustrated in <FIG> by lines <NUM>-<NUM>. A first unit of data is transferred between a row in segment <NUM> via datapath <NUM> and 835a. A second unit of data is transferred between a row in segment <NUM> via datapath 835b. The first unit of data is time multiplexed with the second unit of data on datapath 835b. A third unit of data is transferred between a row in segment <NUM> via datapath <NUM> and 835a. The third unit of data is time multiplexed with the first unit of data on datapath 835a. The third unit of data is time multiplexed with the first and second units of data on datapath 835b. A fourth unit of data is transferred between a row in segment <NUM> via datapath <NUM>. The fourth unit of data is time multiplexed with the first, second, and third units of data on datapath 835b. Thus, all four units of data are time multiplexed on datapath 835b. Datapath 835b may operatively couple to input/output logic for memory component <NUM>. The multiplexing of data to/from segments <NUM>-<NUM> is further described by way of example in <FIG>.

<FIG> is a timing diagram illustrating a bank group access. In <FIG>, banks <NUM>-<NUM> are being clocked by the signals CK-<NUM> to CK-<NUM>, respectively. CK-<NUM> is delayed by <NUM>° from CK-<NUM>. CK-<NUM> is delayed by <NUM>° from CK-<NUM>. CK-<NUM> is delayed by <NUM>° from CK-<NUM>.

On a rising edge of CK-<NUM>, a first unit of data is read out of segment <NUM> via datapath <NUM> and carried via datapath 835a. This is illustrated by arrows <NUM> and <NUM>, respectively. Datapath 835a couples the first unit of data to datapath 835b. This is illustrated by arrow <NUM>.

On the next rising edge of CK-<NUM> a second unit of data is read out of segment <NUM> via datapath <NUM> and carried via datapath 835b. This is illustrated by arrows <NUM> and <NUM>, respectively.

On the next rising edge of CK-<NUM>, a third unit of data is read out of segment <NUM> via datapath <NUM> and carried via datapath 835a. This is illustrated by arrows <NUM> and <NUM>, respectively. Datapath 835a couples the third unit of data to datapath 835b. This is illustrated by arrow <NUM>.

On the next rising edge of CK-<NUM>, a fourth unit of data is read out of segment <NUM> via datapath <NUM> and carried via datapath 835b. This is illustrated by arrows <NUM> and <NUM>, respectively.

<FIG> is an illustration of a second example of signal paths for bank group accesses. In <FIG>, memory component <NUM> includes bank group #<NUM> (BG1) 931a and bank group #<NUM> (BG2) 931b. BG1 931a includes memory bank <NUM> and memory bank <NUM>. BG2 931b includes memory bank <NUM> and memory bank <NUM>. Memory bank <NUM> includes (non-blocked) segment <NUM>. Memory bank <NUM> includes (non-blocked) segment <NUM>. Memory bank <NUM> includes (non-blocked) segment <NUM>. Memory bank <NUM> includes (non-blocked) segment <NUM>.

Bank <NUM> and bank <NUM> are operatively coupled to datapath circuitry 935a (e.g., MUX/DEMUX functions, buffers, common signal lines, logic, etc.) Bank <NUM> and bank <NUM> are operatively coupled to datapath circuitry 935b. Thus, to access a row in either bank <NUM> or <NUM>, data flows via datapath circuitry 935a. Likewise, to access a row in either of bank <NUM> or <NUM>, data flows via datapath circuitry 935b.

The datapath circuitry <NUM>-<NUM> to access a respective row in segments <NUM>-<NUM> may run at a frequency governed by the core column to column delay timing (e.g., tCCD_L = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency. ) The datapath circuitry 935a shared by bank <NUM> and bank <NUM> may run at a frequency governed by the intermediate core column to column delay timing (e.g., tCCD_M = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency. ) The datapath circuitry 935b shared by bank <NUM>, bank <NUM>, and datapath 935a may run at a frequency governed by the shortest column to column delay timing (e.g., tCCD_S = <NUM>-<NUM> ns for a <NUM>-<NUM> cycle frequency.

In example access operation, four units (e.g., byte, word, etc.) of data are transferred in to, or out of, a respectively addressed row in a respective bank <NUM>-<NUM>. This is illustrated in <FIG> by lines <NUM>-<NUM>. A first unit of data is transferred between a row in segment <NUM> via datapath <NUM> and 935a. A second unit of data is transferred between a row in segment <NUM> via datapath 935b. A third unit of data is transferred between a row in segment <NUM> via datapath <NUM> and 935a. The third unit of data is time multiplexed with the first unit of data on datapath 935a. A fourth unit of data is transferred between a row in segment <NUM> via datapath <NUM>. The fourth unit of data is time multiplexed with the second units of data on datapath 935b. Datapaths 935a and 935b may operatively couple to input/output logic for memory component <NUM>. The multiplexing of data to/from segments <NUM>-<NUM> is further described by way of example in <FIG>.

On a rising edge of CK-<NUM>, a first unit of data is read out of segment <NUM> via datapath <NUM> and carried via datapath 935a. This is illustrated by arrows <NUM> and <NUM>, respectively. On the next rising edge of CK-<NUM> a second unit of data is read out of segment <NUM> via datapath <NUM> and carried via datapath 935b. This is illustrated by arrows <NUM> and <NUM>, respectively. On the next rising edge of CK-<NUM>, a third unit of data is read out of segment <NUM> via datapath <NUM> and carried via datapath 935a. This is illustrated by arrows <NUM> and <NUM>, respectively. On the next rising edge of CK-<NUM>, a fourth unit of data is read out of segment <NUM> via datapath <NUM> and carried via datapath 935b. This is illustrated by arrows <NUM> and <NUM>, respectively.

It should be understood that the data carried by datapath 935a and datapath 935b may be further time-multiplexed together by additional circuitry not shown in <FIG> (e.g., data I/O circuitry such as data interface <NUM>). This time-multiplexing may result in a column to column delay visible to a memory controller that is governed by tCCD_S.

<FIG> is a flowchart illustrating a method of operating a memory device with hierarchical bank group timing. The steps illustrated in <FIG> may be performed by system <NUM>, and/or its components. To a memory device, a first command is sent that accesses a first memory bank of a first bank group that is a member of a first bank group cluster (<NUM>). For example, controller <NUM> may send a command to memory component <NUM> that accesses bank 151a of bank group <NUM>, which is a member of bank group cluster 131a.

After at least a first time interval from sending the first command, a second command is sent to the memory device that accesses the first memory bank (<NUM>). For example, after tCCD_L has elapsed from sending the first command that accesses bank 151a, controller <NUM> may send, to memory component <NUM>, a second command that accesses bank 151a.

A third command is sent to the memory device that accesses a memory bank of the first bank group (<NUM>). For example, controller <NUM> may send a command to memory component <NUM> that accesses bank 151c of bank group <NUM>, which is a member of bank group cluster 131a.

After at least a second time interval from sending the third command, a fourth command is sent to the memory device that accesses a fourth memory bank of a second bank group that is a member of the first bank group cluster (<NUM>). For example, after tCCD_M has elapsed from sending the third command that accesses memory bank 151c of the first bank group <NUM>, controller <NUM> may send to memory component <NUM> a fourth command that accesses bank 152a of bank group <NUM>, which is a member of bank group cluster 131a.

A fifth command is sent to the memory device that accesses a memory bank of the first bank group (<NUM>). For example, controller <NUM> may send a command to memory component <NUM> that accesses bank 151a of bank group <NUM>, which is a member of bank group cluster 131a. After at least a third time interval from sending the fifth command, a sixth command is sent to the memory device that accesses a fifth memory bank of a third bank group that is a member of a second bank group cluster (<NUM>). For example, after tCCD_S has elapsed from sending the fifth command that accesses bank 151a of bank group <NUM>, which is a member of bank group cluster 131a, controller <NUM> may send to memory component <NUM> a sixth command that accesses bank 153a of bank group <NUM>, which is a member of bank group cluster 131b.

<FIG> is a flowchart illustrating a method of operating a memory device. The steps illustrated in <FIG> may be performed by system <NUM>, and/or its components. To a memory device, a first command is sent that accesses a first row in a first memory bank that is a member of a first bank group (<NUM>). For example, controller <NUM> may send a command to memory component <NUM> that accesses a row in segment 451a of bank <NUM>, which is a member of bank group 431a.

After at least a first time interval from sending the first command, a second command is sent to the memory device that accesses a second row in the first memory bank (<NUM>). For example, after tCCD_L has elapsed from sending the first command that accesses a row in segment 451a of bank <NUM>, controller <NUM> may send, to memory component <NUM>, a second command that accesses a row in segment 451b of bank <NUM>.

A third command is sent to the memory device that accesses a row in the first memory bank (<NUM>). For example, controller <NUM> may send a command to memory component <NUM> that accesses a row in segment 451a of memory bank <NUM>.

After at least a second time interval from sending the third command, a fourth command is sent to the memory device that accesses a row of a second memory bank that is a member of the first bank group (<NUM>). For example, after tCCD_M has elapsed from sending the third command that accesses that accesses a row in segment 451a of memory bank <NUM>, controller <NUM> may send to memory component <NUM> a fourth command that accesses a row in segment 452a of memory bank <NUM>, which is a member of bank group 431a.

A fifth command is sent to the memory device that accesses a row of a memory bank in the first bank group (<NUM>). For example, controller <NUM> may send a command to memory component <NUM> that accesses a row in segment bank 451a of memory bank group <NUM>, which is a member of bank group 431a. After at least a third time interval from sending the fifth command, a sixth command is sent to the memory device that accesses a row in a memory bank of a second bank group (<NUM>). For example, after tCCD_S has elapsed from sending the fifth command that accesses a row in segment bank 451a of memory bank group <NUM>, which is a member of bank group cluster 431a, controller <NUM> may send to memory component <NUM> a sixth command that accesses a row in segment 453a of memory bank <NUM>, which is a member of bank group 431b.

The methods, systems and devices described above may be implemented in computer systems or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of memory system <NUM>, memory <NUM>, memory system <NUM>, memory component <NUM>, memory component <NUM>, memory component <NUM>, memory component <NUM>, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: <NUM> magnetic tape, <NUM> magnetic tape, <NUM>-<NUM>/<NUM> inch floppy media, CDs, DVDs, and so on.

<FIG> is a block diagram illustrating one embodiment of a processing system <NUM> for including, processing, or generating, a representation of a circuit component <NUM>. Processing system <NUM> includes one or more processors <NUM>, a memory <NUM>, and one or more communications devices <NUM>. Processors <NUM>, memory <NUM>, and communications devices <NUM> communicate using any suitable type, number, and/or configuration of wired and/or wireless connections <NUM>.

Processors <NUM> execute instructions of one or more processes <NUM> stored in a memory <NUM> to process and/or generate circuit component <NUM> responsive to user inputs <NUM> and parameters <NUM>. Processes <NUM> may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and/or verify electronic circuitry and/or generate photomasks for electronic circuitry. Representation <NUM> includes data that describes all or portions of memory system <NUM>, memory <NUM>, memory system <NUM>, memory component <NUM>, memory component <NUM>, memory component <NUM>, memory component <NUM>, and their components, as shown in the Figures.

Representation <NUM> may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation <NUM> may be stored on storage media or communicated by carrier waves.

Data formats in which representation <NUM> may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email.

User inputs <NUM> may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters <NUM> may include specifications and/or characteristics that are input to help define representation <NUM>. For example, parameters <NUM> may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and/or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

Memory <NUM> includes any suitable type, number, and/or configuration of non-transitory computer-readable storage media that stores processes <NUM>, user inputs <NUM>, parameters <NUM>, and circuit component <NUM>.

Communications devices <NUM> include any suitable type, number, and/or configuration of wired and/or wireless devices that transmit information from processing system <NUM> to another processing or storage system (not shown) and/or receive information from another processing or storage system (not shown). For example, communications devices <NUM> may transmit circuit component <NUM> to another system. Communications devices <NUM> may receive processes <NUM>, user inputs <NUM>, parameters <NUM>, and/or circuit component <NUM> and cause processes <NUM>, user inputs <NUM>, parameters <NUM>, and/or circuit component <NUM> to be stored in memory <NUM>.

Claim 1:
A memory device (<NUM>), comprising:
a command address interface (CA)
a plurality of bank group clusters (131a, 131b);
each of the bank group clusters (131a, 131b) comprising a plurality of respective bank groups (<NUM>, <NUM>, <NUM> ,<NUM>); each of the bank groups comprising a plurality of respective memory banks (151a, 151b, 151c, 152a, 152b, 152c, 153a, 153b, 153c, ); wherein successive accesses to different memory banks (151a, 151b, 151c, 152a, 152b, 152c,) that are members of the same bank group have a first command to command delay interval for a first type of command received via the command address interface (CA);
successive accesses to memory banks (151a, 153a) that are members of different bank groups (<NUM>, <NUM>) and of the same bank group cluster have a second command to command delay interval for the first type of command received via the command address interface (CA); and characterized by successive accesses to memory banks (151c, 153c) that are members of different bank group clusters (131a, 131b) have a third command to command delay interval for the first type of command received via the command address interface (CA), wherein the first command to command delay interval, the second command to command delay interval, and the third command to command delay interval are all not equal.