Patent Description:
In the prior art, methods for manufacturing non-flat electronics and circuits are known. For example, using printed circuit board (PCB) based techniques semi-rigid electronic circuits having a non-flat shape may be fabricated by interconnecting flat rigid assembled boards using flexible circuitry. Such techniques may be used to manufacture arbitrarily shaped circuits, but has limitations in terms of shapes that can be realized.

Another approach based on PCB technology is disclosed by <NPL>). The approach comprises the steps of encapsulating stretchable interconnects in thermoplastic polymer, and thermoforming the polymer into the shape of a semi-sphere such that the embedded interconnects are stretched. Due to the stretchable nature of the interconnects it may be challenging to control the final position of the electric components in a repeatable manner.

In <CIT>, a method for manufacturing non-flat devices comprising elements such as electronic components and mechanical interconnects by thermoforming a flat device is disclosed. Designing the layout of the flat device includes inserting mechanical interconnections between pairs of elements to unambiguously define the position of the elements on a surface of the non-flat device, thus leaving zero or less than zero degrees of freedom for the location of the components. Based on the layout of a flat device thus obtained, the flat device is manufactured and next transformed into the shape-retaining non-flat device by means of a thermoforming process, thereby accurately and reproducibly positioning the elements at a predetermined location on a surface of the non-flat device. This approach hence relies on designing the layout of the flat device such that forces originating from the flow of thermoformable material and the mechanical interconnections connected to each element at the end of the thermoforming process reach an equilibrium. Although this approach may enable precise control over the final positions of the circuit elements the design process of the flat device laminate may be challenging due to a required calculation of interconnect parameters relating to the force balance during deformation.

<CIT> relates to a method for designing a pattern of a stress relief layer for a flat device to be transformed into a shape-retaining non-flat device by deformation of the flat device. The flat device (and thus also the non-flat device) may comprise at least two components and at least one electrical interconnection between two components.

<CIT> discloses an In-Mold Electronics (IME) device and method of manufacturing the IME device introduce a stretchable substrate laminated to a thermoplastic layer. The stretchable substrate has a screen printable surface for receiving printed conductive interconnects.

<CIT> provides methods for manufacturing shape-retaining non-flat devices comprising components integrated on a device surface, the non-flat devices being made by deformation of a flat device.

<CIT> discloses method involving introducing a film piece resting on a conveying device into a heating zone. A heated film piece is introduced into a deformation zone and subjected with a fluid pressure medium. The heated film piece is isostatically formed to a desired thermoformed part. Film areas of the film piece are strongly heated before deformation.

<CIT> relates to a method and a thermoforming or joining system for embedding an embedding element in a product.

In view of the above, it is an objective of the present inventive concept to provide a method for manufacturing a non-flat device by deformation of a flat device laminate, which facilitates an accurate and reproducible positioning of circuit elements in the non-flat device. It is further an objective to achieve this aim without the need for complex and time-consuming calculations or simulations during design. Further and alternative objectives may be understood from the following.

According to an aspect of the present inventive concept there is provided a method for manufacturing a shape-retaining non-flat device, comprising:.

It is a benefit of the present inventive concept, that there is no uncertainty in the length of the second portion of the carrier layer after forming the non-flat device, as it is equal to the length of the second portion of the carrier layer prior to the step of deforming the flat device laminate. Accordingly, the length of the second portion may remain constant prior to and after the step of deforming the flat device laminate as instead of being stretched by the flow of thermoformable material during the thermoforming, the thermoformable material may flow along the non-stretchable carrier layer. This facilitates an accurate and reproducible positioning of the circuit element in the non-flat device.

A further advantage associated with the non-stretchable design of the carrier layer is that the length and shape of the conductive traces arranged thereon may remain unchanged after the thermoforming, thus mitigating a variability in resistance of the conductive traces.

Hence, the length of the carrier layer and the electrical resistance of the conductive traces in the non-flat device may be controlled precisely. This implies that the method enables accuracy and repeatability in the sense that when repeated, the method is able to consistently produce the same accurate results.

In view of the above, the method facilitates correctly predicting the final position of the circuit element in the non-flat device. Thus, the method may simplify a design process of the provided flat device laminate, reducing the need for estimations or simulations of parameters relating to the non-flat device. This is beneficial in comparison to the use of an intrinsically stretchable carrier layer or a carrier layer fabricated in a stretchable pattern, where the stretchable carrier layers dimensions after the step of deforming may vary and are complex to determine. In order to determine the relationship between the distance between the circuit element and the first portion, prior to and after the step of deforming the flat device laminate in such a case, one would need to rely on estimates or simulations, taking many parameters and uncertainties into account.

According to some embodiments, the flat device laminate may further comprise a second layer of thermoformable material and the carrier layer, the conductive traces and the circuit element may be embedded between the first and second layer.

Thereby, the carrier layer, the conductive traces, and the circuit elements may be protected from exposure by the layers of thermoformable material. They may be isolated, and shielded from for instance moist or dust.

According to some embodiments, the second portion may be adapted to extend along a sidewall of the shape-retaining non-flat device after the thermoforming.

Thereby, the second portion may provide structural support to the sidewall of the non-flat device, thus contributing to the mechanical stability of the non-flat device.

According to some embodiments, the first portion may extend along the entire periphery of the device region of the flat device laminate to define a frame enclosing the device region.

Thereby the first portion may define a structural support along the device region in the non-flat device, thus contributing to the mechanical stability of the non-flat device.

According to some embodiments, the step of deforming the flat device laminate may comprise aligning the device region of the flat device laminate with a mold such that the second portion is positioned over an opening in the mold and the first portion extends along a periphery of the opening of the mold. More specifically, the step of deforming the flat device laminate may comprise first aligning the device region of the flat device laminate with the mold and thereafter deforming the flat device laminate by thermoforming.

By aligning the flat device laminate with a mold in this manner, a predictable and reproducible shaping of the flat device laminate into the non-flat device during the step of deforming is allowed.

The thermoformable material of the first (and second) layer(s) may be allowed to expand and line the inside of the mold (e.g. completely) and thereby obtain the non-flat shape. The first portion of the carrier layer may remain undeformed, extending along the opening of the mold. The second portion of the carrier layer may, due to its non-stretchable properties, be deformed by bending to follow the shape of the mold without being elongated or shortened, thus resulting in an exact and predictable position of the free end within the device region of the non-flat device.

According to some embodiments, the non-flat device may have a shape of a developable surface, a semi-sphere, a cylinder, a truncated pyramidical or a conical shape. The shapes listed facilitates thermoforming from a flat device laminate.

According to some embodiments, the second portion of the carrier layer of the flat device laminate may extend past a centerline of the opening of the mold by a distance such that the free end of the second portion may be positioned at a bottom of the mold after the step of deforming.

Thereby, a circuit element arranged at / supported by the free end may be positioned at a bottom surface of the non-flat device, e.g. at a central position of the bottom surface.

The circuit element may alternatively be arranged at an area of the second portion excluding the free end.

The flat device laminate may comprise more than one circuit element, distributed on the second portion.

As the non-stretchable carrier layer leaves only one possible spatial configuration for the circuit elements relative to each other, manufacturing of a non-flat device comprising more than one circuit element with accurate, predictable, and reproducible positioning of the circuit elements is facilitated.

According to some embodiments, the circuit element may comprise one or more discrete electrical/electronic components, electrically connected to the conductive traces. Additionally or alternatively, the circuit element may comprise one or more electrical components integrally formed with the conductive traces. Examples of discrete electrical components include typical active and passive circuit components like resistors, capacitors, inductors and transistors, as well as optical or opto-electrical components (e.g. photonic components), and sensors. Examples of integrally formed electrical components include capacitive and/or inductive components, e.g. antenna elements.

According to some embodiments, the circuit element may be or comprise a light emitting diode.

According to some embodiments, the circuit element may comprise two or more electrical components interconnected to form a sub-circuit electrically connected to the conductive traces. The circuit element may e.g. comprise a PCB supporting the two or more electrical components, arranged on the second portion, and electrically connected to the conductive traces. The two or more electrical components may be selected from any of the aforementioned examples of electrical components.

According to some embodiments, the flat device laminate may comprise a plurality of device regions and the carrier layer may comprise a plurality of first portions and a plurality of second portions, wherein each first portion may be arranged to extend along a periphery of a respective device region and each second portion may protrude from a respective first portion into a respective device region to define a free end,
and wherein the step of deforming may comprise deforming the plurality of device regions of the flat device laminate into a respective shape-retaining non-flat device by thermoforming.

Thereby parallel processing of a plurality of device regions may be facilitated, making the method more time- and cost-effective.

According to some embodiments, each of the device regions may be deformed simultaneously.

According to some embodiments, the method may further comprise, after the step of deforming, cutting away non device regions of the flat device laminate.

Thereby a plurality of individual devices may be produced from one flat device laminate, making the method more time- and cost effective.

The above, as well as additional objects, features, and advantages of the present inventive concept, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings.

As disclosed herein there is provided a method for manufacturing a shape-retaining non-flat device from a flat device laminate. As used herein, the term" shape-retaining" is used to refer to that the non-flat device is ensured to retain its intended shape in absence of external forces. According to the method, the flat device laminate comprises a device region which is deformed into the shape-retaining non-flat device by thermoforming. The flat device laminate comprises a carrier layer having a first portion arranged to extend along a periphery of the device region of the flat device laminate in which the shape-retaining non-flat device is to be formed, and a second portion protruding from the first portion into the device region to define a free end. The carrier layer is non-stretchable such that the respective shortest distance, along a second portion of the carrier layer, between the circuit element and the first portion, prior to and after the step of deforming the flat device laminate, are equal. As used herein, the term "non-stretchable" with reference to the carrier layer should accordingly be understood as the carrier layer not being able to be stretched, expanded, or compressed during the thermoforming, but instead being mechanically stable and keeping the same length during and after the step of thermoforming is applied.

Referring now to the flow chart of <FIG> in conjunction with <FIG>, embodiments of a method for manufacturing a non-flat device by deformation of a flat device laminate will now be described. In the following, the method will be described in relation to forming a non-flat device of a shape and design suitable for use e.g. as a luminaire in an indoor or outdoor lighting application. It is however to be understood that this merely represents an example and that the method has a general applicability in terms of product design and application. Non-flat devices formed by the method may for instance be suitable for use as capacitive touch sensors on curved surfaces in home appliances or automotive interior.

The method comprises a step of providing S10 a flat device laminate <NUM>. The flat device laminate <NUM> according to an embodiment is illustrated in <FIG> and a cross section thereof is illustrated in <FIG>. The flat device laminate <NUM> comprises a carrier layer <NUM>. Conductive traces <NUM> and a circuit element <NUM> are arranged on the carrier layer <NUM>. The flat device laminate <NUM> further comprises a first and second layer <NUM>, <NUM> of thermoformable material arranged on opposite sides of the carrier layer <NUM> to embed the carrier layer. The thermoformable material of the first and second layers <NUM>, <NUM> may be provided as a single material or a stack of at least two materials, as indicated by dashed lines in <FIG>. If the thermoformable material is provided as a single material, it may comprise TPU. If the thermoformable material is provided as a stack, it may comprise an adhesive material 210a, 220a and a structural material 210b, 220b. The adhesive material 210a, 220a may be arranged closest to the carrier layer <NUM> and may comprise a polymer such as TPU. The structural material 210b, 220b may be arranged on the side of the adhesive material 210a, 220a, opposite to the carrier layer <NUM> and may comprise a polymer such as polycarbonate, PETG, PP or TPU, or another conventional thermoformable material suitable for the present application. The thermoformable material may be selected with regard to the temperature during the step of deforming such that the material does not melt during thermoforming. The first layer <NUM> and the second layer <NUM> may for example each have a thickness in the range of <NUM> to a few mm.

It should be realized that although the illustrated embodiment comprises a first and second layer <NUM>, <NUM> of thermoformable material, the flat device laminate <NUM> may alternatively comprise a single layer of thermoformable material, e.g. corresponding to e.g. the first layer <NUM> which is illustrated as the bottom layer in <FIG>.

Further, the flat device laminate <NUM> may comprise multiple layers of thermoformable material and multiple conductive traces <NUM> and circuit elements <NUM> arranged on multiple carrier layers <NUM>. As an example (not illustrated), the flat device laminate <NUM> may comprise a first and second layer <NUM>, <NUM> of thermoformable material, embedding a first carrier layer <NUM> with conductive traces <NUM> and a circuit element <NUM> arranged thereon. The flat device laminate <NUM> may on top of the second layer <NUM> comprise a further carrier layer <NUM> with conductive traces <NUM> and a circuit element <NUM> arranged thereon, and a top of that a third layer of thermoformable material. Further layers of carrier <NUM>, conductive traces <NUM>, circuit element <NUM> and thermoformable material may be added on top.

The carrier layer <NUM> has a first portion <NUM> arranged to extend along a periphery of a device region <NUM> of the flat device laminate <NUM>. The device region <NUM> denotes a region in which the shape-retaining non-flat device <NUM> is to be formed. The carrier layer <NUM> further has a second portion <NUM> protruding from the first portion <NUM> into the device region <NUM> to define a free end therein. The second portion <NUM> may as shown be provided in a narrowing shape, having a widest portion where it protrudes from the first portion <NUM>, and a most narrow portion at the free end. Other shapes of the second portion <NUM> are however also possible, such as a second portion <NUM> having the same width along its entire length. The second portion <NUM> may have a ratio between the narrowest width and the distance between the first portion <NUM> and the free end of at least <NUM>/<NUM>.

As may be appreciated from the following, the second portion <NUM> may extend along a sidewall of the non-flat device <NUM> after the thermoforming S22.

The first portion <NUM> may as shown extend along the entire periphery of the device region <NUM> of the flat device laminate <NUM> to define a frame enclosing the device region <NUM>. In other words, the first portion <NUM> defines a frame enclosing an opening or cut-out in the carrier layer <NUM>, wherein the second portion <NUM> protrudes from the first portion / frame <NUM> into the opening to define a free end therein.

The carrier layer <NUM> may comprise a polymer such as Polyimide, PEN, or PET. The carrier layer <NUM> may comprise other materials, or a combination of different materials. The carrier layer <NUM> may have a thickness in the range of <NUM> to <NUM>, or in the range of <NUM> to <NUM>.

The conductive traces <NUM> (in <FIG>, <FIG>, <FIG> schematically indicated by pairs of dashed lines) are arranged on the carrier layer <NUM>, more specifically on the second portion <NUM>. The conductive traces <NUM> may as shown extend from the first portion <NUM> of the carrier layer, along the second portion <NUM>, and to the circuit element <NUM>. Although not shown in <FIG>, the conductive traces <NUM> may further extend along the first portion <NUM>, e.g. to form conductive terminals or leads of the non-flat device <NUM> for connection with peripheral circuitry such as driving circuitry for the circuit element <NUM>.

The conductive traces <NUM> may as shown be adapted to extend between the circuit element <NUM> and the first portion <NUM> in two parallel segments being separate from each other. The method is however not limited to the particular layout illustrated in <FIG>, <FIG> and <FIG> but is generally applicable to form other layouts of the conductive traces <NUM>.

The conductive traces <NUM> may be attached or adhered to the carrier layer <NUM>. The conductive traces <NUM> may comprise a metal such as silver or copper, an alloy comprising any thereof, or other metals suitable for the present application. The conductive traces <NUM> may comprise a conductive ink material and/or a plated material and/or patterned material from a metal sheet. The material may be laminated on the carrier layer <NUM> or deposited through electroplating, vapor deposition under vacuum, sputter deposition or other techniques. The conductive traces <NUM> may be etched into desired dimensions. The conductive traces <NUM> may comprise copper. The conductive traces <NUM> may have a thickness in the range of a few micrometers to <NUM>, or in the range of <NUM> to <NUM>.

As may be appreciated from the above, the view of the flat device laminate <NUM> in <FIG> represents the cross-section along a portion of the laminate <NUM> comprising the first and second layers <NUM>, <NUM>, the carrier layer <NUM> and conductive traces <NUM>. However, as may be seen e.g. in <FIG> the laminate <NUM> may further comprises portions including the first and second layers <NUM>, <NUM> and the carrier layer <NUM> but not conductive traces <NUM>, and portions including the first and second layers <NUM>, <NUM> but neither the carrier layer <NUM> nor conductive traces <NUM>.

In the illustrated embodiment, the circuit element <NUM> of the flat device laminate <NUM> is provided in the form of an LED. The LED <NUM> is arranged on the second portion <NUM> and electrically connected to the conductive traces <NUM>. Specifically, an anode of the LED <NUM> may be connected to one segment of the conductive traces <NUM>, and a cathode of the LED <NUM> may be connected to another segment of the conductive traces <NUM>.

The LED <NUM> (or more generally circuit element <NUM>) may as illustrated in <FIG>, <FIG>, <FIG> be arranged at the free end of the second portion <NUM> such that the LED <NUM> (circuit element <NUM>) becomes positioned at a bottom surface of the non-flat device <NUM>. The LED <NUM> may as shown be positioned at an approximately centered position of the bottom surface of the non-flat device <NUM>, however an off-center position is also possible. However, also other positions of the LED <NUM> in the non-flat device <NUM> are possible, such as along a sidewall of the non-flat device.

The non-flat device <NUM> is illustrated in <FIG> and <FIG> is provided in the shape of a truncated pyramid. The LED <NUM> may as shown be positioned at an approximately centered position of a bottom surface of the truncated pyramid, however an off-center position is also possible. By the non-flat device <NUM> being provided with a LED <NUM> at a bottom surface of a truncated pyramid, a high amount of forward emission from the LED <NUM> is allowed, facilitating a high level of light output from the non-flat device.

Alternatively, other positionings of the LED <NUM> in the non-flat device <NUM> are possible, such as along a sidewall of the non-flat device.

Alternatively to being provided in the form of a LED, the circuit element <NUM> may be another type of discrete electrical component, such as resistor, transistor, capacitor, or other types of diodes. The circuit element <NUM> may be an optical component, an opto-electronic component and/or a photonic component. The circuit element <NUM> may be a sensor, e.g. a capacitive sensor. Alternatively, the circuit element <NUM> may be an antenna element integrally formed with the conductive traces <NUM>.

The circuit element <NUM> may comprise a plurality of components. The circuit element <NUM> may for instance be a PCB or PCB module comprising multiple electrical components, e.g. a PCB comprising an LED and a driver circuit, or some other sub-circuit suitable for the intended application.

The method is not limited to a pyramidical shape but is generally applicable to form other shapes of a non-flat device. Other examples than the ones disclosed above, such as for instance semi-spherical, cylindrical, conical or a shape of a developable surface are equally possible within the scope of the inventive concept, as defined by the appended claims. The first portion <NUM> of the carrier layer <NUM> may extend along the periphery of the device region <NUM> of the flat device laminate <NUM> in a rectangular or ellipsoidal shape, or any other polygonal shape, depending on the predetermined shape of the non-flat device <NUM>. The second portion <NUM> of the carrier layer <NUM> in the non-flat device <NUM> may protrude from the first portion <NUM> in a rounded or bent manner, following the shape of the non-flat device <NUM>.

As illustrated in <FIG>, the flat device laminate <NUM> may comprise a plurality of device regions <NUM> and the carrier layer <NUM> may comprise a plurality of first portions <NUM> and a plurality of second portions <NUM>, wherein each first portion <NUM> is arranged to extend along a periphery of a respective device region <NUM> and each second portion <NUM> protrudes from a respective first portion <NUM> into a respective device region <NUM> to define a free end. In the following, the method will be described in relation to forming a non-flat device <NUM> from a flat device laminate <NUM> comprising a plurality of device regions.

The method as illustrated in <FIG> comprises a step of deforming S20 by thermoforming S22 the plurality of device regions <NUM> of the flat device laminate <NUM> into the shape-retaining non-flat device <NUM>.

The step of deforming S20 by thermoforming S22 may comprise heating the flat device laminate to a temperature above the glass transition temperature of the thermoformable material <NUM>, <NUM>.

The step of deforming S20 the flat device laminate <NUM> may further comprise aligning S21 the plurality of device regions <NUM> of the flat device laminate <NUM> with a mold <NUM> comprising a plurality of openings <NUM> such that each second portion <NUM> is positioned over an opening <NUM> in the mold <NUM> and each first portion <NUM> extends along a periphery of respective opening of the mold <NUM>. The mold <NUM> is illustrated in <FIG> and may be provided with a shape corresponding to a predetermined shape of the non-flat device <NUM>.

The flat device laminate <NUM> may be pushed into the mold, e.g. to be pressed against the interior walls of the mold, e.g. using vacuum and cooling. During the step of thermoforming S22, the thermoformable material <NUM>, <NUM> is stretched while the carrier layer <NUM>, due to its non-stretchable properties, is deformed by bending to follow the shape of the mold <NUM> without being elongated or shortened. Owning to the adherence of the conductive traces <NUM> to the carrier layer <NUM>, the length and shape of the conductive traces <NUM> may remain unchanged after the step of thermoforming S22. As illustrated in <FIG> and <FIG>, the respective shortest distance d, along a surface of the second portion <NUM> of the carrier layer <NUM>, between the circuit element <NUM> and the first portion <NUM>, prior to and after the step of deforming S20 the flat device laminate <NUM>, are equal.

The second portion <NUM> of each device region <NUM> may extend past a centerline of respective opening of the mold <NUM> by a distance such that the free end of each second portion <NUM> is positioned at a bottom of the mold <NUM> after the step of deforming S20.

The method may further comprise, after the step of deforming S20, cutting away non device regions of the flat device laminate <NUM>.

Each of the device regions <NUM> may be deformed simultaneously or separately.

It should be realized that although the illustrated embodiment comprises a plurality of device regions <NUM>, the flat device laminate <NUM> and the non-flat device <NUM> may alternatively comprise only a single device region <NUM>, corresponding to e.g. the device area <NUM> which is illustrated in <FIG>.

Claim 1:
A method for manufacturing a shape-retaining non-flat device (<NUM>), comprising:
providing (S10) a flat device laminate (<NUM>) comprising:
a first layer of thermoformable material (<NUM>);
a carrier layer (<NUM>) having:
a first portion (<NUM>) arranged to extend along a periphery of a device region (<NUM>) of the flat device laminate (<NUM>) in which the shape-retaining non-flat device (<NUM>) is to be formed, wherein the first portion (<NUM>) defines a frame enclosing an opening in the carrier layer (<NUM>); and
a second portion (<NUM>) protruding from the first portion (<NUM>) into the opening in the device region (<NUM>) to define a free end in the device region (<NUM>);
conductive traces (<NUM>) arranged at least on the second portion (<NUM>) of the carrier layer (<NUM>); and
a circuit element (<NUM>) arranged at the free end of the second portion (<NUM>) and electrically connected to the conductive traces (<NUM>);
deforming (S20) the device region (<NUM>) of the flat device laminate (<NUM>) into the shape-retaining non-flat device (<NUM>) by thermoforming (S22) the flat device laminate (<NUM>), wherein the carrier layer (<NUM>) is non-stretchable such that the length and shape of the conductive traces (<NUM>) remain unchanged after the step of deforming (S20), and the respective shortest distance (d), along the second portion (<NUM>) of the carrier layer (<NUM>), between the circuit element (<NUM>) and the first portion (<NUM>), prior to and after the step of deforming (S20) the flat device laminate (<NUM>), are equal.