Patent Description:
Methods of incorporating leaker-devices into capacitor configurations to reduce cell disturb, and capacitor configurations incorporating leaker-devices.

Computers and other electronic systems (for example, digital televisions, digital cameras, cellular phones, etc.), often have one or more memory devices to store information. Increasingly, memory devices are being reduced in size to achieve a higher density of storage capacity. Even when increased density is achieved, consumers often demand that memory devices also use less power while maintaining high speed access and reliability of data stored on the memory devices.

Charge buildup within memory cells can be problematic for at least the reasons that such may make it difficult to reliability store data. Charge buildup may be become increasingly difficult to control as circuitry is scaled to increasingly smaller dimensions.

It would be desirable to develop architectures which alleviate, or even prevent, undesired charge buildup; and to develop methods for fabricating such architectures. <CIT> discloses a memory cell comprising a capacitor having a first conductive capacitor electrode having laterallyspaced walls that individually have a top surface. <CIT> discloses a method of forming an array of capacitors and access transistors there-above comprising forming access transistor trenches partially into insulative material. <NPL> discloses leakage current and dielectric properties of integrated ferroelectric capacitor etched in non-crystalline phase.

Some embodiments include utilization of leaker-devices to reduce charge buildup along bottom electrodes of capacitors. The leaker-devices may couple the bottom electrodes to a conductive plate. The conductive plate may be along top electrodes of the capacitors, and may be utilized to electrically couple the top electrodes to one another. The leaker-devices may have conductivity (or alternatively, resistance) tailored to enable excess charge to drain from the bottom electrodes to the conductive plate, while not enabling problematic shorting between the bottom electrodes and the conductive plate.

Many, if not most, primary memory cell disturb mechanisms are due to a buildup of potential at cell bottom (CB) electrode nodes. As discussed in more detail below, this disturb mechanism is applicable for ferroelectric RAM (FERAM). However, other types of electronic devices may benefit from the disclosed subject matter as well.

In an embodiment, each of the memory cells in a memory array can be programmed to one of two data states to represent a binary value of "<NUM>" or "<NUM>" in a single bit. Such a cell is sometimes called a single-level cell (SLC). Various operations on these types of cells are independently known in the semiconductor and related arts.

Regardless of the memory cell arrangement, the primary disturb mechanisms discussed above can arise due to different factors. For example, charge on the cell bottom-node can rise due to factors such as plate glitch, access transistor leakage, cell-to-cell interactions, and/or other factors. If a dielectric material in a memory cell leaks significantly, the state of the cell may be adversely affected.

In various embodiments described herein, leaker-devices are introduced into a memory array to prevent build-up of potential at bottom nodes of capacitors associated with individual memory cells. Example embodiments are described with reference to <FIG>.

Referring to <FIG>, an assembly (i.e. apparatus, construction, etc.) <NUM> comprises a structure <NUM> over a base <NUM>.

The base <NUM> may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base <NUM> may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base <NUM> may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc..

A gap is shown between the base <NUM> and the structure <NUM> to indicate that there may be additional materials, components, etc., provided between the base <NUM> and the structure <NUM>.

The structure <NUM> is shown to comprise first and second materials <NUM> and <NUM>. The first material <NUM> may be a sacrificial material; and in some embodiments may comprise, consist essentially of, or consist of silicon (e.g., polycrystalline silicon or polysilicon).

The second material <NUM> may be considered to form an insulative lattice, and may be referred to as an insulative-lattice-material. In some embodiments, the second material <NUM> may comprise, consist essentially of, or consist of silicon nitride.

In the shown embodiment, the insulative-lattice-material <NUM> includes a horizontal beam <NUM> over the sacrificial material <NUM>. The horizontal beam <NUM> has an upper surface (i.e., top surface) <NUM>.

The horizontal beam <NUM> will provide support to conductive pillars (discussed below) which are formed through the structure <NUM>. In some embodiments (not shown) additional beams of the lattice material <NUM> may pass through the sacrificial <NUM> to provide additional support to the conductive pillars. In some embodiments, the structure <NUM> may be referred to as a supporting structure, in that such structure will provide support to the conductive pillars formed therein.

In some embodiments, the first material <NUM> may be selectively etchable relative to the second material <NUM>. The term "selectively etchable" means that the first material may be removed faster than the second material with appropriate etching conditions; and may include, but is not limited to, applications in which the conditions are <NUM>% selective for removal of the first material relative to the second material.

Although the materials <NUM> and <NUM> are shown to be homogeneous in the illustrated embodiment, in other embodiments one or both of the materials <NUM> and <NUM> may be a heterogeneous combination of two or more compositions.

The material <NUM> is shown provided in segments under the sacrificial material <NUM>, as well as being in the beam <NUM> above the sacrificial material <NUM>. In other embodiments, an insulative material different from the material <NUM> may be provided below the sacrificial material <NUM> in place of the illustrated segments of material <NUM>.

Conductive structures (i.e., conductive contacts) <NUM> are shown within a bottom region of the structure <NUM>. Processing described herein forms capacitors (e.g., capacitors shown in <FIG>), and the conductive structures <NUM> may be utilized to couple electrodes of such capacitors with additional circuitry (e.g., transistors).

The conductive structures <NUM> comprise conductive material <NUM>. Such conductive material may comprise any suitable composition or combination of compositions; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, ruthenium, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the conductive material <NUM> may comprise tungsten.

Referring to <FIG>, openings <NUM> are formed in the supporting structure <NUM>. The openings <NUM> extend through materials <NUM> and <NUM>, and expose upper surfaces of the conductive structures <NUM>. The openings <NUM> may be formed with any suitable processing. For instance, a patterned mask (not shown) may be provided over supporting structure <NUM> and utilized to define locations of openings <NUM>, and then the openings <NUM> may be extended into the supporting structure <NUM> with one or more suitable etches. Subsequently, the patterned mask may be removed to leave the assembly of <FIG>.

It is noted that the base <NUM> (<FIG>) is not shown in <FIG>, or in any of the other figures which follow, in order to reduce the overall sizes of the drawings. It is to be understood, however, that the base would be present at the process stages of such figures.

The openings <NUM> may have any suitable shape. <FIG> shows an example application in which the openings are circular-shaped when viewed from above. In other embodiments, the openings <NUM> may have other shapes, including, for example, elliptical shapes, polygonal shapes, etc..

Referring to <FIG>, conductive material <NUM> is formed within the openings <NUM>. The conductive material <NUM> is ultimately utilized to form electrodes of capacitors; and may be referred to as electrode material or as first-electrode-material. The electrode material <NUM> may comprise any suitable composition or combination of combinations; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, ruthenium, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the electrode material <NUM> may comprise, consist essentially of, or consist of titanium nitride.

The conductive material <NUM> is patterned into pillars <NUM> (which may be referred to herein as conductive pillars, as vertically-extending pillars, as first electrodes, as first-capacitor-electrodes, or as first-electrode-pillars). The conductive pillars <NUM> extend vertically through the supporting structure <NUM> to the conductive contacts <NUM>. Each of the pillars <NUM> comprises a top surface <NUM> and a bottom surface <NUM>. Each of the pillars also comprises a sidewall surface <NUM> extending from the top surface <NUM> to the bottom surface <NUM>. Each of the pillars <NUM> comprises a pair of opposing sidewall surfaces <NUM> along the cross-section of <FIG>; but the top view of <FIG> shows that such opposing sidewall surfaces actually merge into a single sidewall surface of each of the pillars. In the shown embodiment, the pillars <NUM> are solid (specifically, are not hollow or container-shaped).

The bottom surfaces <NUM> of the pillars <NUM> are directly against the conductive material <NUM> of the contacts <NUM> in the shown embodiment.

The conductive material <NUM> may be formed within the opening <NUM> utilizing any suitable processing; including, for example, one or more of physical vapor deposition (PVD), atomic layer deposition (ALD) and chemical vapor deposition (CVD). In some embodiments, the conductive material <NUM> may be formed to overfill the openings <NUM>, and subsequently planarization (e.g., chemical-mechanical polishing (CMP)) may be utilized to remove excess material <NUM> and to form the planarized upper surface <NUM> which extends across the top surface <NUM> of the insulative-lattice-material <NUM>, and across the top surfaces <NUM> of the pillars <NUM>.

The vertically-extending pillars <NUM> of <FIG> are horizontally spaced from one another along the illustrated cross-section; and specifically are spaced from one another by intervening spaces <NUM> (only one of which is labeled in <FIG>). The vertically-extending pillars <NUM> of <FIG> may be considered to be laterally supported by the horizontal beam <NUM> of the lattice structure comprising the lattice material <NUM>. The horizontal beam extends between the sidewall surfaces <NUM> of neighboring pillars.

Referring to <FIG>, the top surfaces <NUM> of the conductive pillars <NUM> are recessed relative to the top surface <NUM> of the insulative-lattice-material <NUM>. Such forms recesses <NUM> over the conductive pillars <NUM>. The top surfaces <NUM> are recessed to a depth D such that the top surfaces are still along the insulative-lattice-material <NUM> (i.e., the sacrificial material <NUM> is not exposed). In some embodiments, the depth D may be within a range of from at least about <NUM>% of the thickness of the insulative-lattice-material <NUM> to at least about <NUM>% of the thickness of the insulative-lattice-material <NUM>. In some embodiments, the depth D may be at least about <NUM> angstroms (Å). In some embodiments, the material <NUM> may have a thickness within a range of from about <NUM>Å to about <NUM>Å, and the depth D may be within a range of from about <NUM>Å to about <NUM>Å.

The top surfaces <NUM> of the pillars <NUM> may be recessed with any suitable processing, including, for example, utilization of an etch selective for the conductive material <NUM> relative to the insulative material <NUM>. The etch may be timed so that the recesses <NUM> are formed to the desired depth.

Referring to <FIG>, leaker-device-material <NUM> is formed within the recesses <NUM> and over the upper surface <NUM> of the insulative-lattice-material <NUM>. The leaker-device-material may comprise any suitable composition or combination of compositions. In some embodiments, the leaker-device-material <NUM> may comprise, consist essentially of, or consist of one or more of titanium, nickel and niobium in combination with one or more of germanium, silicon, oxygen, nitrogen and carbon. In some embodiments, the leaker-device-material may comprise, consist essentially of, or consist of one or more of Si, Ge, SiN, TiSiN, TiO, TiN, NiO, NiON and TiON; where the chemical formulas indicate primary constituents rather than particular stoichiometries. In some embodiments, the leaker device material may comprise, consist essentially of, or consist of titanium, oxygen and nitrogen. In some embodiments, the leaker-device-material may comprise amorphous silicon, niobium oxide, silicon-rich silicon nitride, etc.; either alone or in any suitable combination.

Referring to <FIG>, the assembly <NUM> is subjected to planarization (e.g., CMP) to form a planarized upper surface <NUM> extending across the insulative-lattice-material <NUM> and the leaker-device-material <NUM>.

Referring to <FIG>, openings <NUM> are formed to extend through materials <NUM>, <NUM> and <NUM>, and to thereby expose regions of the sacrificial material <NUM>. The openings <NUM> may be formed with any suitable combination of patterning and etches.

Referring to <FIG>, the sacrificial material <NUM> (<FIG>) is removed to form voids <NUM> and expose the sidewall surfaces <NUM> of the conductive pillars <NUM>. The voids <NUM> may be considered to be openings between neighboring conductive pillars <NUM>.

Referring to <FIG>, the voids (openings) <NUM> are lined with insulative material <NUM> to form the insulative material <NUM> along the sidewall surfaces <NUM> of the conductive pillars <NUM>. The insulative material <NUM> may be referred to as insulative-capacitor-material, as it is ultimately utilized in a capacitor configuration. At least some of the insulative-capacitor-material <NUM> may comprise ferroelectric insulative material, and in some embodiments an entirety of the insulative-capacitor-material is ferroelectric insulative material.

The ferroelectric insulative material may comprise any suitable composition or combination of compositions; and in some example embodiments may include one or more of transition metal oxide, zirconium, zirconium oxide, niobium, niobium oxide, hafnium, hafnium oxide, lead zirconium titanate, and barium strontium titanate. Also, in some example embodiments the ferroelectric insulative material may have dopant therein which comprises one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and a rareearth element.

The insulative-capacitor-material <NUM> may be formed to any suitable thickness; and in some embodiments may have a thickness within a range of from about <NUM>Å to about <NUM>Å.

Referring to <FIG>, conductive material <NUM> is formed within the lined voids (openings) <NUM>. The conductive material <NUM> is ultimately utilized to form electrodes of capacitors; and may be referred to as electrode material, as capacitor-electrode-material, as second-capacitor-electrode-material, or as second-electrode-material. The electrode material <NUM> may comprise any suitable composition or combination of combinations; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, ruthenium, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the electrode material <NUM> may comprise, consist essentially of, or consist of one or more of molybdenum silicide, titanium nitride, titanium silicon nitride, ruthenium silicide, ruthenium, molybdenum, tantalum nitride, tantalum silicon nitride and tungsten.

Referring to <FIG>, the assembly <NUM> is subjected to planarization (e.g., CMP) to form a planarized surface <NUM> extending across the materials <NUM>, <NUM>, <NUM> and <NUM>. Such patterns the material <NUM> into capacitor electrodes <NUM>. In some embodiments, the pillars <NUM> may be referred to as first-capacitor-electrodes (or as first electrodes), and the electrodes <NUM> may be referred to as second-capacitor-electrodes (or as second electrodes). The second-capacitor-electrodes are laterally between the first-capacitor-electrodes (i.e., are laterally between the vertically-extending pillars <NUM>), and are spaced from the first-capacitor-electrodes by the insulative material <NUM>.

The first-capacitor-electrodes <NUM> and second-capacitor-electrodes <NUM>, together with the insulative-capacitor-material <NUM>, form a plurality of capacitors <NUM>. Each capacitor has a single pillar <NUM>, and shares a second-capacitor-electrode <NUM> with other neighboring capacitors.

Referring to <FIG>, conductive-plate-material <NUM> is formed across the planarized upper surface <NUM>. The conductive-plate-material <NUM> is electrically coupled with the capacitor-electrode-material <NUM>, and with the leaker-device-material <NUM>.

The conductive-plate-material <NUM> may comprise any suitable electrically conductive materials, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, ruthenium, platinum, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). According to the invention, conductive-plate-material <NUM> comprises a different composition than the electrodes <NUM>. For instance, in some embodiments the electrodes <NUM> may comprise, consist essentially of, or consist of TiSiN and/or TiN (where the chemical formulas list primary compositions rather than specific stoichiometries), and the conductive-plate-material <NUM> may comprise, consist essentially of, or consist of tungsten.

The leaker-device-material <NUM> is configured as leaker-devices <NUM> which electrically couple the first electrodes <NUM> of the capacitors <NUM> with the conductive-plate-material <NUM> to enable discharge of at least a portion of any excess charge from the first electrodes <NUM> to the conductive-plate-material <NUM>. In some embodiments, electrical resistance of the leaker-devices <NUM> is tailored so that the leaker-devices <NUM> have appropriate conductivity to remove excess charge from the first electrodes <NUM> while having low enough conductivity (e.g., high enough resistance) so that the leaker-devices <NUM> do not undesirably electrically short the first electrodes <NUM> to the conductive-plate-material <NUM>. In the embodiment of <FIG>, the leaker-devices <NUM> are horizontally elongated. For instance, the pillars <NUM> may be considered to extend along (i.e., to be elongated along) a vertical axis shown as an axis <NUM>, and the leaker-devices <NUM> may be considered to be elongated along a horizontal axis shown as an axis <NUM>. According to the invention, each of the leaker-devices <NUM> has a bottom surface <NUM> directly against the conductive material <NUM> of a first electrode, and has an upper surface <NUM> directly against the conductive-plate-material <NUM>. In the shown embodiment, the upper surfaces <NUM> of the leaker-devices <NUM> are substantially coplanar with the upper surface <NUM> of the horizontally-extending beam <NUM> of insulative-lattice-material <NUM>; with the term "substantially coplanar" meaning coplanar to within reasonable tolerances of fabrication and measurement.

In some embodiments, the capacitors <NUM> may be incorporated into memory cells <NUM> (such as, for example, ferroelectric memory cells) by coupling the capacitors with appropriate circuit components. For instance, access transistors <NUM> are diagrammatically illustrated in <FIG> as being coupled to the first electrodes <NUM> through the conductive contacts (i.e., conductive interconnects) <NUM>. The transistors <NUM>, and/or other suitable components, may be fabricated at any suitable process stage. For instance, in some embodiments the transistors <NUM> may be fabricated at a process stage prior to the illustrated process stage of <FIG>.

The memory cells <NUM> may be part of a memory array <NUM>; such as, for example, a FeRAM (Ferroelectric Random Access Memory) array.

In some embodiments, the leaker-devices <NUM> may be considered to be resistive interconnects coupling electrodes <NUM> within memory cells <NUM> to the conductive-plate-material <NUM> (which may be referred to as a plate line or as a plate structure). If the leaker-devices are too leaky, then one or more memory cells may experience cell-to-cell disturb. If the leaker-devices <NUM> are not leaky (conductive) enough, then excess charge from the electrodes <NUM> will not be drained. Persons of ordinary skill in the art will recognize how to calculate the resistance needed for the leaker-devices <NUM> for a given memory array. In some embodiments, the leaker-devices <NUM> may have resistance within a range of from about <NUM> megaohms to about <NUM> megaohms. Factors such as separation between adjacent memory cells, the insulative (dielectric) material used between the memory cells, physical dimensions of the memory cells, the amount of charge placed in the memory cells, a size of the memory array, a frequency of operations conducted by the memory array, etc., may be considered when making a determination of the resistance appropriate for the leaker-devices <NUM>.

<FIG> describe an example method for fabricating example capacitors. Another example method for fabricating example capacitors is described with reference to <FIG>.

Referring to <FIG>, the assembly <NUM> is shown at a process stage which may be follow that of <FIG>. The upper surfaces <NUM> of the conductive pillars <NUM> have then recessed relative to the upper surface <NUM> of the insulative-lattice-material <NUM> to form the recesses <NUM>. An undulating topography extends into the recesses <NUM> and across the top surface of the insulative-lattice-material <NUM>. A material <NUM> is formed across the undulating topography. The material <NUM> may comprise leaker-device-material identical to the material <NUM> described above with reference to <FIG>. Alternatively, the material <NUM> may comprise a precursor of the leaker-device-material; and in some embodiments may comprise a material which will become leaker-device-material upon oxidation. For instance, the material <NUM> may be a precursor which comprises, consist essentially of, or consist of titanium and nitrogen (for instance, titanium nitride); and which upon oxidation becomes a leaker-device-material <NUM> comprising, consisting essentially of, or consisting of titanium, nitrogen and oxygen. In the embodiment described herein, the material <NUM> will be referred to as a precursor material.

The precursor material <NUM> may be formed to any suitable thickness. In some embodiments, the precursor material <NUM> may be a continuous layer having a thickness within a range of from about <NUM>Å to about <NUM>Å. The precursor material <NUM> may be continuous (as shown), or may be discontinuous.

Referring to <FIG>, openings 34a are formed to expose regions of the sacrificial material <NUM>. In some embodiments, the formation of the openings 34a may be considered to comprise punching through regions of the precursor material <NUM> and the insulative-lattice-material <NUM>. Segments of the precursor material <NUM> remain over the pillars <NUM> after the formation of the openings 34a.

In the shown embodiment of <FIG>, the conductive pillars <NUM> may be considered to be arranged in pairs; with two of the pillars being labeled as 26a and 26b, and being in a paired relationship with one another. The paired pillars 26a and 26b may be considered together to form a paired-neighboring-pillar-structure 62a. Portions of other paired-neighboring-pillar-structures 62b and 62c are shown in <FIG> to be proximate the structure 62a, and to be spaced from the structure 62a by intervening gaps 64a and 64b. The processing stage of <FIG> has removed regions of the precursor material <NUM> and the insulative-lattice-material <NUM> from the intervening gaps 34a and 34b, while leaving regions of the precursor material <NUM> and the insulative-lattice-material <NUM> between the conductive pillars of the paired-neighboring-pillar-structures (e.g., between the conductive pillars 26a and 26b). The remaining regions of the precursor material <NUM> and the insulative-lattice-material <NUM> may be considered to be part of the paired-neighboring-pillar-structures. For instance, the paired-neighboring-pillar-structure 62a comprises a portion <NUM> which includes precursor material <NUM> and insulative-lattice-material <NUM>.

Referring to <FIG>, the sacrificial material <NUM> is removed to leave the voids (openings) <NUM>.

Referring to <FIG>, the insulative material <NUM> is formed to line the voids <NUM> with processing analogous that described above with reference to <FIG>. The insulative material may be formed utilizing oxidizing conditions (e.g., utilizing one or more of O<NUM>, Os, H<NUM>O<NUM>, etc., with or without plasma) In the shown embodiment, the formation of the insulative material <NUM> oxidizes the precursor material <NUM> (<FIG>) to convert such material to the leaker-device-material <NUM>. In some embodiments, the resulting leaker-device-material <NUM> may be a continuous layer having a thickness within a range of from about <NUM>Å to about <NUM>Å. In some embodiments, the leaker-device-material <NUM> may be a continuous layer having a thickness within a range of from about <NUM>Å to about <NUM>Å. In some embodiments, the leaker-device-material <NUM> of <FIG> may be discontinuous.

Referring to <FIG>, the electrode material <NUM> is formed to fill the lined voids <NUM> with processing analogous that described above with reference to <FIG>.

Referring to <FIG>, planarization is conducted to form the planarized surface <NUM> with processing analogous that described above with reference to <FIG>. Such forms capacitors 44a analogous to the capacitors <NUM> described above with reference to <FIG>.

Referring to <FIG>, the conductive-plate-material <NUM> is formed across upper surfaces of the capacitors 44a. The capacitors 44a are incorporated into memory cells 50a analogous to the memory cells <NUM> described above with reference to <FIG>; and such memory cells 50a are incorporated into a memory array 52a.

The leaker-device-material <NUM> of <FIG> is similar to that of <FIG>, and forms leaker-devices 48a which couple the electrodes <NUM> to the conductive-plate-material <NUM>. The leaker-devices 48a of <FIG> differ from devices <NUM> of <FIG> in that the devices 48a include vertically-elongated structures <NUM> which extend upwardly from the top surfaces of the pillars <NUM>.

The memory arrays described above (memory array <NUM> of <FIG> and memory array 52a of <FIG>) may be ferroelectric memory arrays, and may have any suitable configuration. An example ferroelectric memory array is described with reference to <FIG>. The memory array of <FIG> is specifically described as a memory array <NUM>, but could alternatively be a memory array 52a. The memory array of <FIG> includes a plurality of substantially identical ferroelectric capacitors <NUM> (which would be capacitors 44a if the memory array were the memory array 52a). Wordlines <NUM> extend along rows of the memory array, and digit lines <NUM> extend along columns of the memory array. Each of the capacitors <NUM> is within a memory cell <NUM> which is uniquely addressed utilizing a combination of a wordline and a digit line. The wordlines <NUM> extend to driver circuitry <NUM>, and the digit lines <NUM> extend to detecting circuitry <NUM>. In some applications, the memory array <NUM> may be configured as ferroelectric random access memory (FeRAM).

The memory cells <NUM> may include the transistors <NUM> (described above with reference to <FIG>) in combination with the ferroelectric capacitors. For instance, in some applications each of the memory cells <NUM> may include one of the transistors <NUM> in combination with a ferroelectric capacitor <NUM>, as shown in <FIG>. The memory cell <NUM> is shown coupled with a wordline <NUM> and a digit line <NUM>. Also, one of the electrodes of the capacitor <NUM> is shown coupled with a plate line comprising the plate material <NUM>. The plate line may be utilized in combination with the wordline <NUM> for controlling an operational state of the ferroelectric capacitor <NUM>.

The assemblies and structures discussed above may be utilized within integrated circuits (with the term "integrated circuit" meaning an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc..

Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, ALD, CVD, PVD, etc..

The terms "dielectric" and "insulative" may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term "dielectric" in some instances, and the term "insulative" (or "electrically insulative") in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The descriptions provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

When a structure is referred to above as being "on", "adjacent" or "against" another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on", "directly adjacent" or "directly against" another structure, there are no intervening structures present. The terms "directly under", "directly over", etc., do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

Structures (e.g., layers, materials, etc.) may be referred to as "extending vertically" to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material.

The leaker-devices may extend from the top surfaces of the first electrodes to the conductive-plate-material. The leaker-devices may be horizontally-elongated structures extending along the top surfaces of the first electrodes. The leaker-devices may include vertically-elongated structures extending upwardly from the top surfaces of the first electrodes.

The first electrodes, insulative material, second electrodes, and leaker-devices together may comprise capacitors; and wherein each of the capacitors is comprised by a memory cell of a memory array.

The leaker-devices may comprise one or more of Ti, Ni and Nb, in combination with one or more of Ge, Si, O, N and C. The leaker-devices may comprise one or more of Si, Ge, SiN, TiSiN, TiO, TiN, NiO, NiON and TiON; where the chemical formulas indicate primary constituents rather than particular stoichiometries. The leaker-devices may comprise titanium, oxygen and nitrogen.

The insulative material may be ferroelectric insulative material.

Some embodiments include an integrated assembly having first electrodes which are horizontally-spaced from one another, and which are configured as vertically-extending pillars. Each of the vertically-extending pillars has sidewall surfaces along a cross-section, has a bottom surface, and has a top surface, with the sidewall surfaces extending from the bottom surface to the top surface. Insulative material is along the sidewall surfaces of the vertically-extending pillars. Second electrodes are laterally between the vertically-extending pillars and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices extend from the top surfaces of the vertically-extending pillars to the conductive-plate-material. The leaker-devices are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material.

The leaker-devices may be horizontally-elongated structures extending along the top surfaces of the vertically-extending pillars. The leaker-devices may include vertically-elongated structures extending upwardly from the top surfaces of the vertically-extending pillars.

The first electrodes, insulative material, second electrodes, and leaker-devices together comprise capacitors; and wherein each of the capacitors is comprised by a memory cell of a memory array. The bottom surface of each of the first electrodes may be along a conductive contact which is coupled with an access transistor.

The vertically-extending pillars may be laterally supported by horizontal beams of a lattice-structure; and wherein said horizontal beams extend between sidewall surfaces of neighboring vertically-extending pillars.

The horizontal beams may have upper surfaces; wherein the leaker-devices have upper surfaces; and wherein the upper surfaces of the horizontal beams are substantially coplanar with the upper surfaces of the leaker-devices.

The leaker-devices may be horizontally-elongated. The leaker-devices may include vertically-elongated structures. The horizontal beams may comprise silicon nitride.

Some embodiments include a method of forming an apparatus. An assembly is provided which includes conductive pillars extending vertically through a supporting structure to conductive contacts. The supporting structure comprises an insulative-lattice-material over a sacrificial material. A planarized upper surface of the assembly extends across top surfaces of the conductive pillars and across a top surface of the insulative-lattice-material. The top surfaces of the conductive pillars are recessed relative to the top surface of the insulative-lattice-material. Leaker-device-material is formed along the recessed top surfaces of the conductive pillars. The sacrificial material is removed to expose sidewall surfaces of the conductive pillars and to leave openings between the conductive pillars. The openings are lined with insulative-capacitor-material to form the insulative-capacitor-material along the sidewall surfaces of the conductive pillars. Capacitor-electrode-material is formed within the lined openings. The capacitor-electrode-material, insulative-capacitor-material and conductive pillars together form a plurality of capacitors. Conductive-plate-material is formed to extend across the capacitor-electrode-material and the leaker-device-material. The conductive-plate-material is electrically coupled with the capacitor-electrode-material and with the leaker-device-material. The leaker-device-material electrically couples the conductive pillars to the conductive-plate-material.

The sacrificial material may comprise polycrystalline silicon. The insulative-lattice-material may comprise silicon nitride. The insulative-capacitor-material may be ferroelectric insulative material.

The leaker-device-material may comprise one or more of Ti, Ni and Nb, in combination with one or more of Ge, Si, O, N and C. The leaker-device-material may comprise one or more of Si, Ge, SiN, TiSiN, TiO, TiN, NiO, NiON and TiON; where the chemical formulas indicate primary constituents rather than particular stoichiometries. The leaker-device-material may comprise titanium, oxygen and nitrogen.

The recessing of the top surfaces of the conductive pillars may form recesses over the conductive pillars; and comprise: forming the leaker-device-material within the recesses and over the insulative-lattice-material; and removing the leaker-device-material from over the insulative-lattice-material with a planarization process which forms a planarized surface extending across the leaker-device-material and the insulative-lattice-material.

The recessing of the top surfaces of the conductive pillars may form recesses over the conductive pillars; wherein an undulating topography extends into the recesses and across the top surface of the insulative-lattice-material; and comprising: forming a precursor of the leaker-device-material along the undulating topography to line the recesses and to extend along the top surface of the insulative-lattice-material; punching through regions of the precursor and the insulative-lattice-material between the conductive pillars to expose the sacrificial material, and then conducting the removing of the sacrificial material; the punching through said regions of the precursor removing some of the precursor while leaving segments of the precursor remaining over the conductive pillars; and forming the insulative-capacitor-material over the remaining segments of the precursor while conducting the lining of the openings with the insulative-capacitor-material; the forming of the insulative-capacitor-material over the remaining segments of the precursor oxidizing the remaining segments of the precursor to convert said remaining segments into the leaker-device-material. The precursor may comprise titanium and nitrogen; and wherein the leaker-device-material comprises titanium, nitrogen and oxygen. The conductive pillars, along a cross-section, may comprise paired-neighboring-pillar-structures and intervening gaps between the paired-neighboring-pillar-structures; wherein some of the regions of the precursor and the insulative-lattice-material between the conductive pillars are over the intervening gaps, and some of the regions of the precursor and the insulative-lattice-material between the conductive pillars are part of the paired-neighboring-pillar-structures; and wherein the punching through the regions of the precursor and the insulative-lattice-material comprises punching through the regions of the precursor and the insulative-lattice-material that are over the gaps, and not punching through the regions of the precursor and the insulative-lattice-material that are part of the paired-neighboring-pillar-structures.

Claim 1:
An integrated assembly, comprising:
first electrodes (<NUM>) having top surfaces and sidewall surfaces (<NUM>) extending downwardly from the top surfaces; the first electrodes being solid pillars;
insulative material (<NUM>) along the sidewall surfaces (<NUM>) of the first electrodes (<NUM>);
second electrodes (<NUM>) extending along the sidewall surfaces (<NUM>) of the first electrodes (<NUM>) and being spaced from the sidewall surfaces (<NUM>) by the insulative material (<NUM>);
conductive-plate-material (<NUM>) comprising a different composition to the electrodes and extending across the first (<NUM>) and second electrodes (<NUM>), and coupling the second electrodes (<NUM>) to one another; and
leaker-device-material (<NUM>) configured as leaker-devices (<NUM>) electrically coupling the first electrodes (<NUM>) to the conductive-plate-material (<NUM>) and being configured to discharge at least a portion of excess charge from the first electrodes (<NUM>) to the conductive-plate-material (<NUM>),, and wherein each of the leaker devices (<NUM>) has a bottom surface (<NUM>) directly against the conductive material (<NUM>) of the first electrodes (<NUM>), and has an upper surface (<NUM>) directly against the conductive-plate-material (<NUM>), the leaker-devices (<NUM>) extending from the top surfaces of the first electrodes (<NUM>) to the conductive-plate-material (<NUM>).