Patent Description:
Mobile electronic devices such as cellular phones, PDAs, and gaming devices have gained wide popularity recently. Today, these devices have become more of a necessity than a luxury. As a result, electronic devices have been decreasing in size to meet consumer demand for smaller, easier-to-carry devices. Also, the devices have become more complex and offer a multitude of functionalities to the consumer. The different functionalities, however, require more parts in the electronic device and increasing the device size (in the Z axis - as well as the X and Y axes). Consequently, engineers usually must balance the choice of more functionality versus smaller device size. Therefore, engineers constantly are seeking ways to minimize the size of the electrical components that comprise electronic devices.

Electronic devices usually include various integrated circuits that are coupled together on a circuit board. Each integrated circuit performs functions in conjunction with the other integrated circuits in the electronic device. Advances in material sciences have led to decrease in transistor sizes in integrated circuits leading to smaller and more complex electronic devices entering the market place. It would be ideal for electronic devices to provide all circuit systems within integrated circuit chips to minimize space. Unfortunately, modern manufacturing techniques do not provide such capabilities. Accordingly, electronic devices often include a plurality of chips and additional "discrete" devices. Discrete devices are components such as resistors, capacitors, inductors, etc., that are fabricated separately from the semiconductor die. The discrete components are often provided external to the chip but are electrically connected to some circuit within the chip. The discrete component often is mounted on a printed circuit board (PCB) adjacent to the chip, which increases the electronic device size.

Accordingly, there is a need in the art to incorporate discrete passive components in electronic parts without the discrete passive components taking up costly space.

Patent Publication No. <CIT> describes techniques for placement of active and passive devices within a chip. Here, a semiconductor die includes one or more active devices in an active layer on the first side of the semiconductive substrate layer and a passive device on the second side in electrical communication with the active layer.

Patent Publication No. <CIT> describes a fluidic MEMS device. This disclosure provides a mechanism by which a variety of fluidic MEMS devices can be fabricated as a unitary polymer layer structure formed within a polymer layer located on a substrate.

It is an object of the invention to overcome the shortcomings in the prior art. This object of the invention is solved by an integrated circuit system as defined in claim <NUM>, which substantially corresponds to the description of <FIG> and <FIG>. The other embodiments serve merely as illustrative examples to provide a better understanding of the invention.

Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Embodiments of the present invention provide an electronic device comprising a circuit board and a vertically integrated circuit. The vertically integrated circuit is disposed on the circuit board and comprises a first active layer fabricated on a front side of a semiconductor die; a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component; and at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Embodiments of the present invention provide a vertically integrated circuit comprising an active layer having an active circuit, and a component layer disposed on a back side of the active layer, and having a plurality of discrete passive components and links, wherein the discrete passive components are electrically connected to the active circuit.

<FIG> is a simplified block diagram of an integrated system <NUM> according to an embodiment of the present invention. The integrated system <NUM> may include a semiconductor die <NUM> with two opposed sides, an active side <NUM> and a back side <NUM>. The integrated system may also include passive components <NUM>, <NUM> disposed on the back side <NUM> that are coupled to the active side <NUM> by an electrical connector such as a thru silicon via (TSV) <NUM>. The TSV <NUM> may be coupled to the active side <NUM> with a terminator <NUM>.

The semiconductor die <NUM> may be a silicon wafer or other known semiconductor die material. The active side <NUM> may be located on the front side of the semiconductor die and may include an active circuit that is fabricated thereon during a fabrication process. The active circuit may be etched on to the silicon carrier using known techniques in the art. The active circuit may include semiconductor devices such as transistors that may define functionality of the integrated system <NUM>.

The back side <NUM> may be located on an opposite side of the semiconductor from the active side <NUM> on the semiconductor die <NUM>. Passive components <NUM>, <NUM> may be mounted directly on the back side <NUM>. The passive components <NUM>, <NUM> may be discrete components that may be pre-fabricated separately from the semiconductor die <NUM> fabrication process. The passive components <NUM>, <NUM> may be components that are too big to be made by integrated circuit techniques. The passive components <NUM>, <NUM> may be components that do not require an operating power source thus are passive such as resistors, capacitors, and inductors. The passive components <NUM>, <NUM> may be comprised of ceramic, silicon, or other suitable materials. <FIG> shows two passive components <NUM>, <NUM> for illustration purposes only, and embodiments of the present invention may include a different number of passive components of less than or greater than two. For example, an integrated circuit according to the present invention may include one passive component or may include four passive components.

The passive components <NUM>, <NUM> may be attached or electrically coupled to the back side <NUM> of the semiconductor die <NUM> using a conductive adhesive or paste, anisotropic conductive film or any other suitable method depending on the specific materials involved. The passive components <NUM>, <NUM> may also be fabricated using a different fabrication process than for the semiconductor die <NUM>. The passive component fabrication process may be a lower cost fabrication type process as compared to the semiconductor die fabrication process, which may enable passive discrete components with greater performance characteristics to be fabricated than on a finer geometry fabrication process that may be used for more complex structures. The fabricated substrates, the die substrate and the passive component substrate, may be joined using a number of different processes such as gold bonding, glass bonding, anodic bonding or any other suitable bonding method.

TSVs <NUM> may be vias that are etched or laser-drilled through the semiconductor die <NUM>. After the vias are etched or laser drilled, the vias may then be plated or filled with conductive material to provide an electrical connection between the active side <NUM> and back side <NUM>. Subsequent processing steps such as bumping or patterning may be provided to make the electrical connection between the TSV <NUM> and the passive components <NUM>, <NUM>. The passive components may also be fabricated within or on top of the back side of the silicon (as part of the TSV fabrication process). For example inductive coils or resistors may be fabricated and linked to the TSVs. Also, the TSVs geometries and openings may be modified to facilitate optimum electrical properties of the coupled passive components because different passive components may require different TSV shapes, openings, depths, patterns, etc. For example, an inductive spiral or coil may be fabricated within a TSV. Also, a particular aspect ratio may be required to retain or store charges in a capacitor. So, for example, a recess within the backside of the silicon that is fabricated at the same time as the TSVs may be modified to enhance the electrical properties required. Furthermore, terminators <NUM> may complete the electrical connection between the TSV <NUM> and the active circuit on the active side <NUM>. The terminators <NUM>, for example, may be solder bumps and also provide electrical connections to the next packaging level.

In operation, the active circuit on the active side <NUM> may control the passive components on the back side. The active circuit may access the passive components on the back side <NUM> as necessary. Therefore, the active circuit may operate as the "brain" of the integrated system <NUM>.

Integrated system <NUM> may incorporate passive components <NUM>, <NUM> on the back side <NUM> in a vertical manner; therefore, passive components that were previously mounted on the circuit board can now be placed on the back side of semiconductor die thus saving valuable space on the circuit board. Mounting passive components within the semiconductor die may also reduce the vertical height (the Z height) occupied by the vertically integrated system. Also, the use of pre-fabricated components enables different technologies to be mixed. For example, a thin film ceramic substrate that enables passive components such as capacitors may be incorporated into a silicon base die thus producing a single integrated solution.

<FIG> is a simplified block diagram of an integrated system <NUM> according to another embodiment of the present invention. The integrated system <NUM> may include a semiconductor die <NUM> with two opposed sides, an active side <NUM> and a back side <NUM>. The integrated system may also include passive components <NUM>, <NUM> disposed on the back side <NUM> that are coupled to the active side <NUM> by an electrical connector such as a conducting trace <NUM>. The conducting trace <NUM> may be coupled to the active side <NUM> with a terminator <NUM>. Also, the conducting trace <NUM> may run along the side edges of the semiconductor die <NUM>. The integrated system <NUM> may not require vias to be drilled through the silicon semiconductor die <NUM> while still incorporating passive components <NUM>, <NUM> on the back side <NUM> in a vertical manner because the conducting trace <NUM> may couple the two opposing sides along the edges of the semiconductor die.

The other parts of integrated system <NUM> are similar as those in embodiment shown in integrated system <NUM> of <FIG>. Therefore, detailed description thereof will not be repeated here. Moreover, for clarity and brevity, some parts that are common to the above embodiment will not be further shown and described in the following embodiments. For example, terminators to the active side will not be further shown or described because it will be well understood by person of ordinary skill in the art that those are present in the following embodiments.

<FIG> is a simplified block diagram of an integrated system <NUM> according to another embodiment of the present invention. The integrated system <NUM> may include wire bonds <NUM> that couple passive components <NUM>, <NUM> and TSVs <NUM>. Wire bonding may be desired when the passive components <NUM>, <NUM> and the semiconductor die are made of different materials with different coefficients of expansion that would lend themselves to standard assembly processes as used for, say, multichip modules (where chip capacitors may be electrically connected using standard wirebonding techniques). If so, the semiconductor die and passive components may expand and contract at different rates in different temperatures leading to cracks in the connections between the two parts. This may be alleviated through the mounted components and wirebonds being encapsulated with an epoxy (or another suitable material) that would protect the relevant joints/interfaces and enable the stresses caused by the thermal coefficient of expansion/material mismatches to be minimized and prevent electrical disconnection through mechanical damage.

Having passive components mounted on the back side of a chip may also allow for more customization in the chip design. The vertically integrated design may provide a chip that may be easily tuned and calibrated to fit a variety of different applications. According to an embodiment of the present invention, an integrated system may be provided that is tunable after assembly of all vertically integrated layers. <FIG> shows a component layer <NUM> that may be mounted on the back side of a semiconductor device with passive components such as a resistor <NUM>, a capacitor <NUM>, and an inductor <NUM>, links <NUM>, and TSVs <NUM>. The component layer <NUM> may be a pre-fabricated substrate such as a thin silicon wafer, ceramic, or glass substrate. For example, the component layer may be a thin silicon wafer that is six, eight, or <NUM> inches in material. The component layer <NUM> may be a silicon substrate, ceramic substrate, or a printed circuit board (PCB) type substrate, and may be pre-fabricated at a different site than the active silicon carrier. Furthermore, the pre-fabricated substrate may be made by sputtering, plating, or depositing structures on the base silicon. If the component layer <NUM> is a separate pre-fabricated layer, it may be joined to the active layer (carrier silicon) using, for example, anodic bonding, gold bonding, anisotropic conductive film or another suitable method.

The component layer <NUM>, for example, may be manufactured on silicon using a less complex process than that used for the carrier silicon. The different silicon substrates may ease the fabrication of some passive component performance characteristics. For example, the component layer <NUM> may have a thinner geometry than compared to the carrier silicon die. The incorporation of the passive components onto or within the component layer <NUM> may be further optimized depending on the performance characteristics required. For example, if fabricating a capacitor, the depth and surface area of the two parallel plates deliver a better capacity to store charge. This may be reflected in different shapes/combinations used to maximize the area of the parallel plates as described below in the descriptions of <FIG>.

Different manufacturing processes may be mixed together to maximize desired performance characteristics of a specific passive component. The component layer <NUM> may be electrically connected to the carrier silicon, and the component layer <NUM> may include links to the passive components incorporated therein. The links may be capable of being broken or modified such that the performance characteristics of the passive components incorporated therein are modified. Thus, the integrated system may be tunable after singulation.

As shown further in blow out portion <FIG>, the component layer <NUM> may include basic building block arrays of passive components. The component layer <NUM> may include passive components such as resistor <NUM>, capacitor <NUM>, and inductor <NUM>. For illustration purposes, <FIG> shows the passive components as their respective circuit schematic symbols. The arrays of passive components in component layer <NUM> may be modified such that the specific number and type of passive components that are electrically connected to the carrier silicon below (for example, through electrically blowing fused links or laser trimming) are set when the whole system is electrically connected (before singulation). Therefore, thewhole vertically integrated system may be tuned or calibrated.

The passive components may be modifiable or tunable for specific applications. <FIG>illustrate different techniques that may be used to tune passive components. <FIG> shows a resistor component in schematic symbol form that may have a total resistance value of R3. In this example, the resistance may depend directly on the resistor's length. Thus, the resistor may be laser-trimmed to produce a smaller resistance value. For example, the resistor may be trimmed to produce smaller resistances R2 and R1 as shown. Alternatively, the width of the passive component may be modified as the length remains constant such that the resistance may directly depend on the passive component's width. The modification may be carried out by laser trimming, physical modification of relevant links or structures, or other suitable techniques.

<FIG> shows another method of tuning a resistance value. In this example, three resistors, R1, R2, and R3, may be coupled in series. Different links, L1, L2, L3 and L4, also may be provided in between the resistors' connections. Depending on which resistance value is preferable, the links may be selectively fused or broken. For example, if resistance value of R2 is preferable, links L1 and L4 may be broken thus leaving only links L2 and L3 that are coupled to each end of resistor R2. In another example, if resistance value of R1+R2 is preferable, links L2 and L4 may be broken thus leaving only links L1 and L3 that provide R1 and R2 in series. Moreover, the resistors may be arranged in a parallel fashion with the links arranged accordingly. Alternatively, the different links L1, L2, L3 and L4 may be connected together on a common track, which may be subsequently modified to break or modify connections as designed.

<FIG> shows another method of tuning a resistance value. In this example, three resistors may be provided so that each of the resistors may be coupled to the TSVs. Depending on which resistance value is preferable, the resistors may be selectively coupled to the TSVs through wire bonding. In another embodiment, all resistors may be coupled to the TSV and, subsequently, bonds to all but one resistor may be broken. Also, electrical structures within layers of the vertically integrated system may be connected through fused links, which can be electrically blown in order to tune the system.

<FIG> illustrates a method of tuning a capacitance value. <FIG> shows a cross section view and a top view of a passive discrete capacitor. The capacitor may have two parallel sides, A and B, that store charge, and the two parallel sides may be separated by a dielectric. One side of the capacitor may include electrical links that may be modifiable. For example, the links may be broken reducing the size of the capacitor plates and, thus, reducing the capacitance.

In the case of an inductor, the properties may be influenced by the number of turns in the inductor coil. Links between layers, which contain different numbers of turns, may be modified by blowing fuses that connect the turns on each layer. Multiple turns and links may be connected on each layer and these links may be fused (and then blown electrically) or physically modified.

Moreover, component layer <NUM> may also include links <NUM> between the passive components and TSVs <NUM> that electrically connect to the active layer underneath. Consequently, the links <NUM> may be broken or altered to also tune or modify the integrated system. As a result, the integrated system as a complete stack may be electrically tested and the components in the component layer on the back side may be tuned, modified, or calibrated subsequently. Since the vertically integrated system allows tuning, modification, or calibration in wafer sandwich form after assembly of all layers, the vertically integrated system is easily customizable for different applications. Also, different individual systems can be singulated after a complete stack is assembled, electrically tested, and tuned leading to easy incorporation into the next packaging level on (or within) the circuit board.

<FIG> is a simplified block diagram of an integrated system <NUM> according to another embodiment of the present invention. The integrated system <NUM> may include a semiconductor die with an active side <NUM> and a back side <NUM> that incorporates passive components <NUM>, <NUM>. TSVs <NUM> may couple the passive components <NUM>, <NUM> to an active circuit on the active side <NUM>. The integrated system may include a cavity <NUM> on the back side <NUM> in where the passive components <NUM>, <NUM> are mounted. Also, the integrated system <NUM> may include a protective layer <NUM>.

Cavity <NUM> may be recess etched into the back side or formed within the back side of the semiconductor die. By having the passive components <NUM>, <NUM> mounted within the cavity, the overall system height of the vertically integrated system is greatly reduced leading to further reduction in component size.

Protective layer <NUM> may be coupled to the layers below such as the active side <NUM> by vias and may offer protective covering to the passive components <NUM>, <NUM>. The protective layer <NUM> may be an electromagnetic field (EMF) shielding. Also, the protective layer <NUM> may include a ground plane or a power plane for the integrated system <NUM>. Since the protective layer <NUM> is on top of the other layers, the protective layer <NUM> may dissipate heat produced by the layers below. The protective layer <NUM> may also contain passive components. Therefore, the protective layer <NUM> may provide EMF shielding and provide an additional component layer at the same time. Also, protective layer <NUM> may be modifiable to tune or calibrate the integrated system <NUM>, for example when all the layers are assembled together before singulation. The protective layer <NUM> may be modifiable electrically through laser trimming, blowing fuses, or other known techniques.

<FIG> is a simplified block diagram of an integrated system <NUM> according to another embodiment of the present invention that is similar to integrated system <NUM> of <FIG>. Integrated system <NUM> may include an encapsulant <NUM> that fills the cavity. The encapsulant <NUM> when hardened may mold around the passive components locking them in place.

According to another embodiment of the present invention, the integrated system may include multiple cavities. Integrated system <NUM> in <FIG> may include two cavities <NUM>, <NUM> where a passive component <NUM>, <NUM> may be mounted in each cavity respectively. Also, each cavity may have more than one passive component mounted therein. <FIG> shows an integrated system <NUM> that may include multiple cavities with an encapsulant <NUM>, <NUM> that fills the cavities respectively. The encapsulant <NUM>, <NUM>, when hardened, may mold around the passive components locking them in place.

Passive components may be mounted or embedded within the semiconductor die in different manners depending on the size of the passive component and the electrical properties of the passive component. <FIG> illustrates three passive component devices mounted in different manners on the back side of a semiconductor die according to an embodiment of the present invention. Passive component <NUM> may be mounted directly onto the back side with no cavity and having a vertical height of Z<NUM>. On the other hand, passive component <NUM> may be mounted entirely within a cavity where filling the depth and width of the cavity may improve the electrical properties of the passive component <NUM>. For example, increasing the depth of the cavity may allow more resistive material to be incorporated into the cavity and, thus, increasing the overall resistance properties.

Embedding the passive component <NUM> entirely within the cavity reduces the vertical height of the integrated system because the passive component <NUM> does not add a z height of its own. Passive component <NUM> may be mounted on the back side such that it fills a cavity and also overlaps the cavity. The total volume achieved by filling the depth and width of the cavity and the additional overlap may improve the electrical properties of the passive component <NUM>. For example, overlapping material around a cavity may increase the total volume of the resistive material and, thus, may increase the overall resistance properties. Furthermore, Z<NUM>, the z height of the passive component <NUM>, is less than Z<NUM>, which is the vertical height of the passive component <NUM> that is mounted directly on the back side. Therefore, the vertical height of the system may be reduced by employing different mounting techniques described herein.

The cavity or recess, into which the passive component is mounted, may be shaped and modified to optimize the performance required. For example, <FIG> shows an integrated system <NUM> with a capacitor <NUM> as a passive component mounted on the back side within a cavity entirely according to an embodiment of the present invention. The cavity and the TSVs are shaped so that the top plate <NUM> and bottom plate <NUM> of the capacitor <NUM> fit the cavity. Moreover, the cavity may be further modified to allow for higher valued capacitors to be used. <FIG> shows an integrated system <NUM> with a capacitor <NUM> as a passive component mounted on the backside in a cavity according to an embodiment of the present invention. The cavity in this embodiment may be stepped to maximize the surface area of the parallel plates, the top plate <NUM> and bottom plate <NUM> of the capacitor <NUM>. Since the capacitance is directly related to the surface area of the parallel plates, the capacitance increases and, thus, the amount of charge stored increases.

<FIG> is a simplified block diagram of an integrated system <NUM> according to another embodiment of the present invention. Integrated system <NUM> may include multiple passive components stacked on top of each other with each passive component being mounted in respective recess. First recess <NUM> may have passive component <NUM> mounted therein; second recess <NUM> may have passive component <NUM> mounted therein; and third recess <NUM> may have passive component <NUM> mounted therein. Each passive component may be electrically connected to an active circuit on the active side by TSVs as shown in <FIG>. The passive component <NUM> may be connected to the active circuit by the pair of TSVs <NUM>, the passive component <NUM> may be connected to the active circuit by the pair of TSVs <NUM>, and the passive component <NUM> may be connected to the active circuit by the pair of TSVs <NUM>. Each recess may be etched into the back side or formed within the back side of the semiconductor die with a stepped profile. The "stepping" of the recesses or cavities within the back side of the semiconductor die may enable many different passive components to be incorporated into the integrated system <NUM> while minimizing both the horizontal length and vertical height of the integrated system <NUM>.

The passive components <NUM>, <NUM>, <NUM> may be pre-fabricated together on substrates yet still separate from the semiconductor die. The pre-fabricated substrates may then be inserted into the stepped recesses of the semiconductor die for assembly.

<FIG> is a simplified block diagram of an integrated system <NUM> according to another embodiment of the present invention that is similar to integrated system <NUM> of FIG. Integrated system <NUM> may include an encapsulant <NUM> that fills the cavity. The encapsulant <NUM> when hardened may mold around the passive components in each recess locking them in place.

Moreover, a protective layer <NUM> as shown in <FIG> may be placed on top of the passive components. Protective layer <NUM> may be coupled to the layers below such as the active side by vias and may offer protective covering to the passive components. The protective layer <NUM> may be an electromagnetic field (EMF) shielding. Also, the protective layer <NUM> may include a ground plane or a power plane for the integrated system <NUM>. Since the protective layer <NUM> is on top of the other layers, the protective layer <NUM> may dissipate heat produced by the layers below. The protective layer <NUM> may also contain passive components. Therefore, the protective layer <NUM> may provide EMF shielding and provide an additional component layer at the same time. Also, the protective layer <NUM> may be modifiable to tune or calibrate the integrated system <NUM>, for example, when all the layers are assembled together before singulation. The protective layer <NUM> may be modifiable electrically through laser trimming, blowing fuses, or other known techniques.

<FIG> is a simplified block diagram of an integrated system <NUM> according to another embodiment of the present invention. Integrated system <NUM> may use inductor coils placed on the back side to isolate and couple electrical signals from dies of different voltage domains. Integrated system <NUM> may include a low voltage die <NUM> and a high voltage die <NUM> separated by an isolation barrier <NUM>. The integrated system also may include passive components <NUM>, <NUM>, and a pair of inductor coils <NUM>, <NUM>.

The low voltage die <NUM> and high voltage die <NUM> operate on different voltage domains that are electrically separated. Isolation barrier <NUM> may electrically separate the two dies and may be made of a non-conducting material. The passive components <NUM>, <NUM> may be incorporated into (or deposited on top of) the back side and may be directly coupled to an active circuit of the low voltage die <NUM>. The passive components <NUM>, <NUM> may also be coupled to one of the inductor coils <NUM>, <NUM> while the other coil may be coupled to an active circuit of the high voltage die <NUM>. Consequently, integrated system <NUM> may use the inductor coils <NUM>, <NUM> to isolate and magnetically couple electrical signals between the two dies, low voltage die <NUM> and high voltage die <NUM>, through the pre-fabricated substrate including passive components <NUM>, <NUM>. The pre-fabricated substrate layer may also contain a protective layer as described above.

Ferromagnetic materials may also be included within the coils. <FIG> is a simplified block diagram of an inductor incorporated into an integrated system according to an embodiment of the present invention. The inductor may have a ferromagnetic core <NUM> and a coil <NUM> wrapped around the ferromagnetic core <NUM>. The inductor may be pre-fabricated and mounted onto the back side of the semiconductor die. Also, the inductor may be connected to the active side with conductive paths such as a TSV.

<FIG> is a simplified block diagram of an inductor into an integrated system according to an embodiment of the present invention. The inductor may have a ferromagnetic core <NUM> and a coil <NUM> wrapped around the ferromagnetic core <NUM>. In this embodiment, the inductor may be pre-fabricated and inserted within a cavity on the back side of semiconductor die. Also, the inductor may be connected to the active side with conductive paths such as a TSV.

<FIG> is a simplified block diagram of an inductor into an integrated system according to an embodiment of the present invention. The inductor may have a ferromagnetic core <NUM> and a coil <NUM> wrapped around the ferromagnetic core <NUM>. In this embodiment, the inductor may be fabricated within the back side of semiconductor die. Also, the inductor may be connected to the active side with conductive paths such as a TSV.

The ferromagnetic materials may be used to form transformers within the layers of the integrated system. The transformer may be a step up or step down transformer. For example, a transformer formed within the layers may be used as an RF transformer. <FIG> illustrates a transformer forming method according to an embodiment of the present invention. A pre-fabricated layer A <NUM> may contain a coil <NUM> wrapped around a ferromagnetic core <NUM>. The layer A <NUM> may be a fabricated PCB, ceramic, or other suitable substrate. The layer A <NUM> may also contain other passive components, shielding, power plane, and ground planes. The layer A <NUM> may also contain connections to other layers. Another layer B <NUM> may be the back side of the semiconductor die. The layer B <NUM> may contain a coil <NUM> wrapped around a ferromagnetic core <NUM> that is mounted within a cavity in the semiconductor die back side. The two layers, layer A <NUM> and layer B <NUM>, may be joined and the ferromagnetic cores <NUM>, <NUM> of each respective layer may connected to form a transformer with coil <NUM> being a top coil and coil <NUM> being a bottom coil of the transformer. Moreover, an encapsulant may fill the cavity. Alternatively, the transformer may be mounted directly onto the back side of the semiconductor die.

<FIG> illustrates a transformer forming method according to an embodiment of the present invention. The transformer in <FIG> may contain a pair of coils wrapped around a ferromagnetic core as shown. The transformer may be formed on a substrate that is mounted with a thick dielectric onto the back side of the die. The dielectric may deform and heat and pressure, leaving the core endings exposed that may be mounted on the back side of the die.

<FIG> is a simplified block diagram of an integrated system <NUM> according to another embodiment of the present invention. Integrated system <NUM> also may use inductor coils placed on the back side to isolate and couple electrical signals to and from different voltage dies that cannot be directly coupled similar to the integrated system <NUM> of <FIG>; however, in integrated system <NUM> the substrate that includes the passive component is also used as an isolation circuit between the differing voltage dies. Integrated system <NUM> may include a low voltage die <NUM>, a high voltage die <NUM>, an isolation barrier <NUM>, passive component <NUM> and a pair of inductor coils <NUM>, <NUM>. In this embodiment, the high voltage die <NUM> may be stacked on top of the low voltage die <NUM> with the isolation barrier <NUM> in between the two dies to electrically isolate the two dies. The isolation circuit may be a pre-fabricated substrate as described in the present invention that includes passive components.

In another aspect of integrated system <NUM>, the active circuit in the low voltage die <NUM> may control operations of the other layers including the passive component <NUM> and high voltage die <NUM> circuits. The low voltage die <NUM> may access the other layers.

<FIG> is a simplified block diagram of an integrated system <NUM> according to another embodiment of the present invention that is similar to integrated system <NUM> of FIG. Integrated system <NUM> may further include microelectromechanical systems (MEMS) <NUM>, <NUM> on the high voltage die <NUM>. For example, the low voltage die <NUM> may contain a memory portion that stores a mechanical position for the MEMS <NUM>, <NUM> such as an initial position for a gyroscope. When the integrated system <NUM> is in operation, the sensitivity and output of the MEMS may be normalized to an initial mechanical position. Other application examples may include RF MEMS switches, arranged in series or parallel, for antenna tuning in different frequency bands.

The isolation barrier <NUM> may also contain ferromagnetic materials positioned between the coils. The ferromagnetic materials may deliver a step up or step down transformer as required within the integrated system.

According to another embodiment of the present invention, an optics system may isolate and couple electrical signals from different dies that operate in different isolated domains. <FIG> is a simplified block diagram of an integrated system <NUM> that includes an optics system. The integrated system <NUM> may include may include a low voltage die <NUM>, a high voltage die <NUM>, an isolation barrier <NUM>, and a passive component <NUM>. The integrated system <NUM> may also include an optics system with a phototransistor <NUM>, an LED <NUM>, and a waveguide <NUM>. In this embodiment, the high voltage die <NUM> may be stacked on top of the low voltage die <NUM> with the isolation barrier <NUM> in between the two dies to electrically isolate the two dies. The isolation circuit may be a pre-fabricated substrate as described above that includes passive components.

In this embodiment, the optics system may isolate and optically couple the electrical signals between two differing operating voltage dies, <NUM> and <NUM>. A phototransistor <NUM> may be placed on one of the dies, for example the high voltage die, and a corresponding LED <NUM> may be placed on the other die. A waveguide <NUM> may also be placed in between the phototransistor <NUM> and LED <NUM> in order for optic waves to be able to travel. The waveguide <NUM> may be formed within the isolation barrier <NUM>. In operation, the active circuit on the low voltage die <NUM> may turn on the LED <NUM>, on one end of the waveguide <NUM>, as a communication signal. The phototransistor <NUM>, at the other end of the waveguide <NUM>, will sense when the LED <NUM> is turned "ON" and transmit the information to the circuit on the high voltage die <NUM> circuits. Consequently, the active circuit in the low voltage die <NUM> may control operations of the other layers including the passive component <NUM> and high voltage die <NUM> circuits. The low voltage die <NUM> may access the other layers as necessary.

Alternatively, the optic system may be a bi-directional communication system between layers as shown in <FIG> according to an embodiment of the present invention. In a bi-directional communication system, each die may include a phototransistor <NUM>, <NUM> and an LED <NUM>, <NUM> allowing communication in both directions.

Furthermore, an optic system may be used when the two dies are placed side by side on a layer. <FIG> is a simplified block diagram of an integrated system <NUM> according to an embodiment of the present invention. The low voltage die <NUM> and high voltage die <NUM> may be on a same layer and may be separated by isolation barrier <NUM>. An optic system may be mounted on the two dies. The optics system may include a phototransistor <NUM>, an LED <NUM>, and a waveguide <NUM>.

Integrated system <NUM> of <FIG> shows an embodiment according to the present invention of how the active circuit on the active side can access different passive components. Integrated system <NUM> may include passive components <NUM>, <NUM> and inductor coils <NUM>-<NUM> placed in a top substrate that is coupled to passive components and the active circuit. The inductor coils <NUM>-<NUM> may switch on/off to activate/deactivate the passive components <NUM>, <NUM>. For example, the active circuit may send a voltage to inductor coils <NUM>, <NUM> when it needs to access passive component <NUM>. A pair of inductor coils may also control access to a block of passive components and not just one passive component.

The integration of different layers/materials on the back side of a semiconductor die may lead to structural instability. The adhesion between the different layers may be crucial to keep structural integrity (during the operation/lifetime of the vertically integrated system and also during the singulation of the individual vertically integrated systems). Coefficients of thermal expansion (CTE) between dissimilar material layers in a multi-layer system generate stresses which are concentrated on the edges. In other words, stresses that can lead to shearing and peeling of the bonds between layers are strongest on the edges, which can be exacerbated when a multi-layer system contains many thin layers of different materials. Therefore, according to the present invention, different embodiments described below are provided that maximize adhesion at the edge of the embedded component and, therefore, improve the mechanical robustness of the vertically integrated system.

<FIG> shows an integrated system <NUM> according to an embodiment of the present invention. Integrated system <NUM> may include tracks in the semiconductor die perimeter. The top section of <FIG> shows a plan view of the die with two tracks, and the bottom section shows a cross section view with the two tracks. The tracks may be formed on the back side of the semiconductor die with laser cuts or by an etching or some other process capable of providing the required deformation. The tracks form ridges for an encapsulant to be embedded within thus more securely attaching the multiple layers to each other.

<FIG> shows an integrated system <NUM> according to an embodiment of the present invention. Integrated system <NUM> may include squares in the semiconductor die perimeter. The top section of <FIG> shows a plan view of the die with the squares, and the bottom section shows a cross section view with the squares. The squares may be formed on the back side of the semiconductor die with laser cuts or by an etching or some other process capable of providing the required deformation. The squares form ridges for an encapsulant to be embedded within thus more securely attaching the multiple layers to each other.

<FIG> shows an integrated system <NUM> according to an embodiment of the present invention. Integrated system <NUM> may include co-centric circles in the semiconductor die perimeter. The top section of <FIG> shows a plan view of the die with two co-centric circles, and the bottom section shows a cross section view with the two co-centric circles. The co-centric circles may be formed on the back side of the semiconductor die with laser cuts or by an etching or some other process capable of providing the required deformation. The co-centric circles form ridges for an encapsulant to embed within thus more securely attaching the multiple layers to each other.

<FIG> shows an integrated system <NUM> according to an embodiment of the present invention. Integrated system <NUM> may include staggered steps in the semiconductor die perimeter. The top section of <FIG> shows a plan view of the die with the staggered steps, and the bottom section shows a cross section view with the staggered steps. The steps may be formed on the back side of the semiconductor die with laser cuts or by an etching or some other process capable of providing the required deformation. The steps form ridges for an encapsulant to embed within thus more securely attaching the multiple layers to each other.

The patterns and shapes employed may be optimized as necessary to improve adhesion and locking between layers. This may be achieved by increasing the surface area and also by providing a recess/trench/area (depending on pattern or shape used) into which a portion of the material to be joined fills/cures/hardens such that it is mechanically locked. The patterns and shapes used may be optimized to maximize the robustness of the complete vertically integrated structure (through the singulation process as well as through the operating life time of the system).

The integrated system according to the present invention may be embedded within a PCB type structure. Accordingly, the integrated system may incorporate further locking features to ensure that the integrated system may be securely embedded within a PCB type structure or other structures. <FIG> illustrates the edge of an integrated system according to an embodiment of the present invention. Both a semiconductor die <NUM> and a component layer <NUM> may have a serrated edge as shown or another shape profile to improve adhesion and thus allowing more securely embedding within a final substrate. The edge finish may be formed during the singulation process as described in further detail below.

<FIG> further illustrates the edge finish in an integrated system <NUM> in a plan view and cross-section view according to an embodiment of the present invention. Integrated system <NUM> may include a semiconductor die <NUM>, metal pads <NUM> in the active region, and scribe street <NUM>. The metal pads <NUM> may be used for connection to another layer. The scribe street <NUM> may include an edge finish such as a serrated edge producing gaps which may be subsequently filled by an encapsulant.

<FIG> illustrates how the edge finish may be formed. A scribe street <NUM> may be fabricated with openings <NUM>. The openings <NUM> may be formed by laser cutting or other known techniques, and the openings <NUM> may be circular as shown or another shape. A final cut <NUM> for singulation of integrated systems may be made in the openings <NUM> to produce the serrated edge finish shown in <FIG>. The final cut <NUM> may be made by a laser, dicing saw, or other known device.

<FIG> is a simplified block diagram of an integrated system <NUM> according to another embodiment of the present invention. Integrated system <NUM> shows the inter-connection of the two layers using locking features that improve adhesion between the two layers according to the present invention. Integrated system <NUM> may include locking grooves <NUM>, <NUM>, a locking step <NUM>, and an encapsulant <NUM>.

The locking grooves <NUM>, <NUM> may be located on the edges of the die similar to the embodiments shown in <FIG>. The locking step <NUM> may be a raised step from the surface where the passive components are mounted. The locking grooves <NUM>, <NUM> may improve the robustness of the integrated system's construction because they secure the protected back side coating more firmly. As a result, the possibility of delamination or separation of the edge layers is greatly reduced. Since the back side layer is more securely adhered to die this also translates into the passive devices incorporated on the back side to be more securely adhered.

The locking grooves <NUM>, <NUM> may formed by etching on the back side of the die. Moreover, encapsulant may be filled into the groove and the encapsulant may fill the opening and then harden to mechanically lock within the die. The locking groove <NUM> adds more surface area of contact as compared to a flat surface thus improving adhesion. The same concept is true for the locking step <NUM>.

<FIG> shows a magnified view of a locking groove <NUM> in order to illustrate how locking grooves improve adhesion. According to an embodiment of the present invention, adhesion may be further improved by etching a recess as shown in <FIG> where the widest portion of the groove, "b" is larger than the opening on the surface, "a". Since b > a, the surface area of contact is increased even further leading to improved adhesion.

<FIG> is a simplified diagram of an integrated system <NUM> according to another embodiment of the present invention that improves adhesion. Integrated system <NUM> may include locking grooves <NUM>, an encapsulant <NUM>, and a locking layer <NUM>. In assembly, the locking layer <NUM> may be added to a first set of grooves. Then the encapsulant <NUM> may be added to a second set of grooves and also within the locking layer <NUM>. As the material at the interfaces between the layers deforms through heat, pressure, etc., and fills the grooves, the material will harden, which may mechanically lock and secure the entire integrated system as well as increasing the surface area which will also maximize adhesion. Opening features and surface patterns may be modified such as altering the shapes of the recesses/openings and staggering the locations within different layers for optimization to make the entire integrated system more robust.

According to an embodiment of the present invention, modifications may also be made on the active side the semiconductor die to improve adhesion. Integrated system <NUM> of <FIG> illustrates such modifications. Integrated system <NUM> may include a semiconductor die <NUM>, a dielectric layer <NUM>, metal pads <NUM>, <NUM>, and locking cuts <NUM>. The metal pads <NUM>, <NUM> may be exposed metal contacts that are used to connect to the next packaging level such as a PCB. In between the metal pads <NUM>, <NUM>, the dielectric layer <NUM> may include locking cuts <NUM> that increase the surface area of contact thus improving adhesion. The locking cuts <NUM> may be made as part of the bumping/wafer processing.

<FIG> shows a plan view of an active side that includes locking cuts or grooves that are capable of trapping or locking an encapsulant according to an embodiment of the present invention. Integrated system <NUM> may include locking cuts <NUM>, <NUM> and metal pad <NUM>. As shown, locking cuts <NUM>, <NUM> may be co-centric circles etched in a top layer dielectric. The metal pad <NUM> may be an exposed metal contact that is used to connect to the next packaging level such as a PCB.

In another embodiment of the present invention, the shapes of the TSVs may be modified in order to improve adhesion of the conductive material contained within. For example, TSV opening on the back side of the semiconductor die may be modified so that the terminations of the passive components may be more securely embedded in the die making the entire integrated system more robust. <FIG> shows plan view of a TSV <NUM> with a circular opening, and <FIG> shows a plan view of a TSV <NUM> with an irregularly shaped opening. Both TSV <NUM> and TSV <NUM> may have the same radius r. In a plating process step, the TSV <NUM> with the irregularly shaped opening has less volume within the via to be filled with conductive material as compared to the TSV <NUM> with the circular opening. The TSV <NUM> opening has a surface area less than the surface area of TSV <NUM>, which is π*r<NUM> for a circular opening. Therefore, TSV opening shapes may be modified to produce optimized adhesion effects for the conductive material within the via, making the integrated system more robust.

Moreover, separation and delamination of conductive layers within a via can cause serious issues for an integrated system. However, via construction according to embodiments of the present invention as described herein may hold conductive material more securely and, therefore, making the integrated system more robust.

As discussed below in more detail, an integrated system according to embodiments of the present invention may also be used in the analysis of fluids, gases, etc., and the vias may be used as conduit for movement between layers. Depending on the specific application, the vias may be constructed to optimize the flow of material through an opening to an optimal rate. <FIG> shows a cross section view of a TSV <NUM> according to an embodiment of the present invention. TSV <NUM> may include different stepped concentric openings such that the physical flow through the layer may be controlled to a specific rate. For example, the flow of material from the top of the layer to the bottom of the layer may be reduced because of TSV <NUM>'s narrowing profile. <FIG> shows a cross section view of a TSV <NUM> according to an embodiment of the present invention. TSV <NUM> may include different sloped concentric openings such that the physical flow through the layer may be controlled to a specific desired rate. Alternatively, vias may be modified to produce a spiral of other optimized shapes in order to facilitate a desired rate of movement of fluid between levels. For example, the vias may be modified to act as part of a filtering or reduction of flow rate process so that pH levels may be monitored such as where the fluid passing through a specific layer or area within the vertically integrated system shows a discernible measured electrical value, and the layers are physically constructed to deliver a desired flow rate such that a fluid's pH may be continuously monitored.

According to an embodiment of the present invention, TSVs may be placed in non-active areas of the semiconductor die because certain circuitry may have issues with TSVs directly above the active circuit. For example, the incorporation of vias above certain types of circuitry may cause mechanical stresses that could affect the performance of the system and cause parametric shift issues. <FIG> shows a plan view of the active side and a cross section view of an integrated system <NUM> with an active circuit <NUM> and a TSV array <NUM>. The TSV array <NUM> may be located on the perimeter of the active circuit <NUM> thus on the non-active area of the semiconductor die. Area "d" is the minimum distance between the active circuit <NUM> and the closest TSV <NUM> in order to minimize interference between the two parts.

Moreover, in another embodiment, TSVs may not be filled with conductive material depending on their application. For example, optical systems or cooling systems may employ TSVs that do not require conductive material to be filled therein. Therefore, non-conductive TSVs may still connect different layers of a vertically integrated system.

Heating issues may arise with vertically integrated systems. The active circuit, as well as the passive components, may produce thermal heat when operating. Excessive heat can damage electrical parts and deteriorate overall performance of the integrated system. <FIG> is a simplified diagram of an integrated system <NUM> according to another embodiment of the present invention. Integrated system <NUM> may include a heat sink <NUM> and thermal TSVs <NUM>. The heat sink <NUM> may be a heat slug or a block of highly thermally conductive material. The heat sink <NUM> in <FIG> is shown to be attached to a locking step; however, the heat sink <NUM> may be attached to a cooling plate or other interfaces. The thermal TSVs <NUM> may conduct heat from the active side to the back side of the die. Consequently, the heat sink <NUM> and the thermal TSVs <NUM> in conjunction dissipate heat produced from the active side preventing over-heating thus improving overall performance of the integrated system. Alternatively, the heat created by the system may be used to improve the overall efficiency of the integrated system (i.e., through using a thermoelectric generating layer) as described below. Moreover, the thermal TSVs <NUM> used to transfer heat may be modified (e.g., enlarged) to optimize the thermal efficiency.

<FIG> is a simplified diagram of an integrated system <NUM> according to another embodiment of the present invention. Integrated system <NUM> may include a heat sink <NUM> and thermal TSVs <NUM>. The heat sink <NUM> may be a heat slug or a block of highly thermally conductive material. The heat sink <NUM> in <FIG> is shown to be attached to a locking step; however, the heat sink <NUM> may be attached to a cooling plate or other interfaces. The thermal TSVs <NUM> may conduct heat from the active side to the back side of the die. The heat sink <NUM> may cover the active circuit on the active side entirely and may be more thermally efficient in dissipated heat than a heat sink that partially covers the active circuit. As the size of the heat sink increases, so does the heat sink's thermal efficiency because thermal efficiency is directly proportional to the heat sink's size.

According to another embodiment of the present invention, cooling layers may also be employed in dissipating heat generated in a vertically integrated system. <FIG> is a simplified diagram of an integrated system <NUM> according to another embodiment of the present invention. Integrated system <NUM> may include a semiconductor die <NUM>, TSVs <NUM>, a cooling layer <NUM>, and a component layer <NUM> with passive components <NUM>, <NUM>. The component layer <NUM> may be electrically coupled to an active circuit on the active side of the semiconductor die <NUM> by TSVs <NUM>. The cooling layer <NUM> may also include a via to support the electrical connection between component layer <NUM> and the active circuit. The via in the cooling layer <NUM> may or may not be thru silicon depending on the cooling layer material. The cooling layer <NUM> may be a cooling plate or a micro fluidic system to optimize heat dissipation.

<FIG> is a simplified diagram of one embodiment of cooling layer <NUM>. The cooling layer <NUM> may include micro channels through which coolant material may be passed. The cooling layer <NUM> may also accommodate a micro fluidic pump system to circulate coolant thus removing heat. The coolant may be inserted in one end and pumped through to the other end. As a result, the coolant circulation may lower the temperature in the integrated system.

<FIG> is a simplified diagram of another embodiment of a cooling layer <NUM>. The cooling layer <NUM> may include peltier or thermoelectric type cooling system. The cooling layer <NUM> may include a hot side <NUM>, a cold side <NUM>, and channels <NUM>-<NUM>. The cooling layer <NUM> may also be coupled to underneath layers by vias <NUM>. The vias <NUM> may be thermal vias, and the vias <NUM> may couple the cooling layer <NUM>, for example, to a heat sink or a PCB. The channels <NUM>-<NUM>. n may be selectively used to dissipate heat to specific areas in the hot side <NUM> and the vias <NUM> coupled to the hot side in the specific area. The heat may then be dissipated through the vias <NUM> preventing over-heating. In this embodiment, target heat dissipation into specific areas may be optimized. The system may be further optimized by directing the heat through these vias towards a thermoelectric layer. This layer may also be configured to apply cooling to specific areas within the vertically integrated system.

In addition to dissipating heat, the cooling layer may be used as a thermoelectric generating layer, where heat (for example generated from other components or layers within the vertically integrated system) is converted into electrical charge. <FIG> is a simplified diagram of an embodiment of a thermoelectric generating layer <NUM>. The thermoelectric generating layer <NUM> may include a hot side <NUM>, a cold side <NUM>, and channels <NUM>-<NUM>. The thermoelectric generating layer <NUM> may also be coupled to underneath heat producing layers <NUM>, which may contain passive components or other high power components. The thermoelectric generating layer <NUM> may use heat generated from within the system to generate electrical current, which can then be stored or redistributed within the system. The thermoelectric layer may be incorporated to maximize the amount of charge generated. For example, the hot side <NUM> may be thermally connected to hot spots from within the system, and the cold side <NUM> may also be connected to a cooling layer or to other structures such that the temperature differential between the hot and cold side <NUM>, <NUM> respectively may be maximized and, thus, the maximum current may be generated). Therefore, the integrated system may harvest energy dissipated as heat and recycle it to power the integrated system and thus conserve power.

Moreover, lateral channels may be employed for heat dissipation needs. The lateral channels may also maximize the temperature differential between the hot and cold faces of the thermoelectric layers and, hence, maximize the generated charge. <FIG> is a simplified diagram of an integrated system <NUM> according to another embodiment of the present invention. <FIG> shows a plan view of the active side and a cross section view of the integrated system <NUM>. The integrated system <NUM> may include an active circuit <NUM>, a TSV array <NUM>, and lateral channels <NUM>. The lateral channels <NUM> may be disposed in the semiconductor die above the active circuit <NUM> and run parallel with front and back sides. The lateral channels <NUM> may also be used to incorporate micro fluidic cooling, optical transmission systems, etc. Heat generated by the active circuit underneath the lateral channels may be dissipated by the lateral channels.

Lateral channels may also be located in different layers of a vertically integrated system such as a cooling layer. <FIG> is a simplified diagram of an integrated system <NUM> according to another embodiment of the present invention. Integrated system <NUM> may include a semiconductor die <NUM>, TSVs <NUM>, a cooling layer <NUM> with lateral channels <NUM>, and a component layer <NUM> with passive components <NUM>, <NUM>. The component layer <NUM> may be electrically coupled to an active circuit on the active side of the semiconductor die <NUM> by TSVs <NUM>. The cooling layer <NUM> may also include a via <NUM> filled with conductive material to support the electrical connection between component layer <NUM> and the active circuit. The via <NUM> may or may not be thru silicon depending on the cooling layer material.

<FIG> is a simplified diagram of one embodiment of cooling layer <NUM> that incorporates a micro fluidic cooling system. The cooling layer <NUM> may include lateral channels <NUM> through which coolant material may be passed. The cooling layer <NUM> may also accommodate a micro fluidic pump system to circulate coolant thus removing heat.

Moreover, lateral channels may be used for other purposes than cooling systems. For example, optical transmission lines may be located in the lateral channels in order to provide communication links. <FIG> is a simplified diagram of an integrated system <NUM> according to another embodiment of the present invention that is similar to integrated system <NUM> of <FIG>. Integrated system <NUM> may include a cooling layer <NUM> with lateral channels that operate as optical channels <NUM> as shown in <FIG>. The optical channels <NUM> may include light pipes, fiber optics, etc. The optical isolation may also be utilized in energy harvesting applications. For example, when energy may be recycled back to a battery supply, boosted voltage levels (in excess of the applied supply voltage on the device) may be shuffled to the supply via an optically isolated link to avoid any potential negative effects of overloading the battery with any current or voltage surges. The optical channels may also be employed to actually boost voltages and create a secondary supply using a light source and a photodiode array to boost to desired voltage levels.

For some applications (e.g., haptics or touch screen technologies) a large voltage may be generated by the touching of a screen to access a function on the screen. As the different options are chosen, a charge is generated and has to be "dumped". An integrated system according to an embodiment of the present invention may provide a layer that contains structures (e.g., capacitors) that can store this "dumped" charge and then re-circulate it through the system. Therefore, the integrated system according to the present invention may harvest energy generated by different facets of the system to improve overall power efficiency and provide an important safety feature in avoiding "lithium events" as well.

Some integrated circuit applications may require analysis of materials such as fluids, gases, etc. Conventionally, a separate part outside the integrated circuit is usually required for the holding and measuring of the material that needs to be analyzed. According to an embodiment of the present invention, a measuring layer may be incorporated on the back side of a semiconductor die thus reducing the number of separate parts needed for a given application.

<FIG> is a simplified diagram of an integrated system <NUM> according to an embodiment of the present invention. Integrated system <NUM> may include a semiconductor die <NUM>, TSVs <NUM>, a measuring layer <NUM>, and a component layer <NUM> with passive components <NUM>, <NUM>. The measuring layer <NUM> may include channels that can manipulate or analyze fluids or other materials being passed through it as shown in <FIG>. For example, the measuring layer may monitor pH levels of a fluid, monitor the rate of flow for a liquid, monitor gas concentrations, etc..

The measuring layer <NUM> may include electrical connections for coupling to above and underneath layers. The electrical connections may be vias filled with conducting material. The measuring layer <NUM> may also include other electronic circuitry to provide an electrical signal representing the monitoring quantity and providing the signal to the other layers in the integrated system <NUM>. For example, the measuring layer <NUM> may include electronic circuitry to produce an analog signal representing the pH level of a liquid being analyzed. Moreover, the measuring layer may further include electronic circuitry to provide filtration, separation, and analysis capability. For example, MEMS devices may be incorporated into the measuring layer. The measurement layer may also incorporate mechanical features and structures that optimize manipulation of a fluid, gas, etc..

<FIG> is a simplified diagram of an integrated system <NUM> according to an embodiment of the present invention. Integrated system <NUM> may include a cooling layer <NUM> and a measuring layer <NUM>. The cooling layer <NUM> may be similar to the cooling layers described above, and the measuring layer <NUM> may be similar to the measuring layers described above. The cooling layer <NUM> and measuring layer <NUM> may work in conjunction to measure a material while cooling the integrated system <NUM> because of the interaction between the layers. For example, the cooling layer <NUM> may include heating elements that absorb heat from the active circuit.

The heating elements may also accelerate the processing of the material that is passing through the measuring layer <NUM>. Therefore, integrated system <NUM> uses heat generated by one layer that is usually detrimental to the system to better operate another layer such as the measuring layer. For example, measuring layer <NUM> may include channels for a liquid that is to be analyzed. Heat transported from the cooling layer <NUM> may accelerate the movement of the liquid through the channels in the measuring layer leading to faster operations. Other analysis operations such as separation, filtration, etc., may also be accelerated by heat. Moreover, both the cooling layer <NUM> and measuring layer <NUM> may include other electronic circuitry that can communicate with the other layers in the integrated system <NUM>.

According to another embodiment of the present invention, a via through different layers of a vertically integrated system may be used as a channel for analysis. <FIG> is a simplified diagram of an integrated system <NUM> according to an embodiment of the present invention. Vias <NUM>, <NUM> may pass thru some or all the layers of integrated system <NUM>. The vias <NUM>, <NUM> may manipulate or analyze fluid or other materials such as gases that pass through the vias. One layer in integrated system <NUM> may include electronic circuitry, for example MEMS, that provide analysis operations such as separation, filtration, etc..

One benefit of the via design is that it conserves power. Gravity may transport the material in the vias within the integrated system. Therefore, less power will be required by the integrated system. <FIG> illustrates how a material may pass through the vias <NUM>, <NUM>. The arrows show how gravity may move the material through the integrated system <NUM> from the top layer to the bottom layer. The specific design of these vias may be modified as required to suit specific applications.

Other power saving techniques may be employed in vertically integrated systems according to the present invention. <FIG> is a simplified diagram of an integrated system <NUM> according to an embodiment of the present invention. Integrated system <NUM> may include a semiconductor die <NUM> with an active side <NUM> and a back side <NUM>, a photo-voltaic layer <NUM>, and TSVs <NUM>. The photo-voltaic layer <NUM> may be formed or mounted on the back side <NUM> and may be modifiable with laser trimming. The photo-voltaic layer <NUM> may include organic photo-voltaic cells that transform solar rays into electrical energy. The cells may include transparent conductive electrodes that allow light to couple to active materials thus creating electrical energy. The electrical energy may then power the integrated system <NUM> thus providing a self-powered system.

<FIG> is a simplified diagram of an integrated system <NUM> according to an embodiment of the present invention. Integrated system may include a photo-voltaic layer <NUM>, a light resistant layer <NUM> with openings <NUM>, and electrical storage components <NUM>. The light resistant layer <NUM> may be disposed on top of the photo-voltaic layer and may include strategically placed openings <NUM>. The light resistant layer <NUM> may serve several purposes. The light resistant may protect other electrical parts in the integrated system <NUM> that can be damaged by light exposure. The light resistant layer <NUM> through the openings <NUM> may also be patterned to control the flow of light and current. The openings <NUM> may be optimized to maximize the current flow from the photo-voltaic layer <NUM> to other layers underneath. Moreover, electrical storage components <NUM> may be located in the regions underneath the openings <NUM> in order to store and manipulate electrical charges produced by the photo-voltaic layer <NUM>. The active circuit may control the operation of the electrical storage components <NUM>. For example, the active circuit may access certain electrical storage components when the application requires the use of certain components. Therefore, power usage may be efficiently controlled by the active circuit. Alternatively, a light resistant layer may incorporate strategically placed photo-voltaic cells to generate charge in specific areas. Furthermore, light pipes and other light transmitting devices may be used to divert, channel and concentrate light from external sources to specific photo-voltaic cells within the integrated system and, thus, maximize the charge generated.

The photo-voltaic layer and light resistant layer may be transposed with the photo-voltaic layer being on top of the light resistant layer. <FIG> is a simplified diagram of an integrated system <NUM> according to an embodiment of the present invention. Integrated system <NUM> may include a photo-voltaic layer <NUM>, a light resistant layer <NUM> with openings <NUM>, and electrical storage components <NUM>. In this embodiment, the photo-voltaic layer <NUM> may be on top of the light resistant layer <NUM> and may be the top-most layer. Charge produced by the photo-voltaic layer <NUM> is proportional to the area exposed to light. Thus, positioning the photo-voltaic layer <NUM> on top may maximize the amount of charge produced. Also, selective patterning of the light resistant layer <NUM> may protect some areas of the integrated circuit from light exposure.

Vertically integrated systems may be arranged in different manners depending on their applications. <FIG> is a simplified diagram of an integrated system <NUM> according to an embodiment of the present invention. The integrated system <NUM> may include a photo-voltaic layer <NUM>, a light resistant layer <NUM> with openings <NUM>, a component layer <NUM>, and electrical storage components <NUM>. The component layer <NUM> may include passive components. The light resistant layer <NUM> may be underneath the component layer <NUM>, and the photo-voltaic layer <NUM> may be underneath the light resistant layer <NUM>. Since the photo-voltaic layer <NUM> is underneath a few layers, the openings <NUM> may be strategically patterned to maximize the current flow from the photo-voltaic layer <NUM> to other layers underneath. Also, the component layer <NUM>, in this embodiment, also may be strategically positioned so as to not cover the openings. Moreover, electrical storage components <NUM> may be located in the regions underneath the openings <NUM> in order to store and manipulate electrical charges produced by the photo-voltaic layer <NUM>. The active circuit may control the operation of the electrical storage components <NUM>.

In other embodiments, a photo-voltaic layer may be placed as top-most layer in a vertically integrated system. <FIG> is a simplified diagram of an integrated system <NUM> according to an embodiment of the present invention. In integrated system <NUM>, a component layer <NUM> with passive components, may be underneath a photo-voltaic layer <NUM>. Since the photo-voltaic <NUM> layer is the top-most layer, it increases the surface area for light exposure. Thereby, increasing the amount of electrical energy produced.

In other embodiments, a photo-voltaic layer may work in conjunction with a thermoelectric layer. <FIG> is a simplified diagram of an integrated system <NUM> according to an embodiment of the present invention. In integrated system <NUM>, a photo-voltaic layer <NUM> may be provided on top of a thermoelectric layer <NUM> and a component layer <NUM> with passive components. The thermoelectric generating layer <NUM> may include a hot side, a cold side, and channels. The thermoelectric generating layer <NUM> may use heat generated from within the system to generate electrical current (harvest charge), which can then be stored or redistributed within the system. In addition, the thermoelectric generating layer <NUM> may also harvest charge from the photo-voltaic layer <NUM>. The integrated system <NUM> may include components such as capacitors to store the harvested charge. Furthermore, the links between the layers carrying the charge may be modified to improve rate of movement of current. The energy efficiency of the integrated system may be greatly improved through harvesting the heat produced within the system and also the charge produced form other sources such as a photo-voltaic layer. The harvested charge may be stored and redistributed throughout the system, for example, to charge a battery.

In one application of an integrated system according to the present invention, the integrated system may be employed in a monitoring system such as an alarm system. <FIG> is a simplified diagram of an integrated system <NUM> according to an embodiment of the present invention. The integrated system <NUM> may include a signal transmission layer <NUM> and a component layer <NUM>. The integrated system <NUM> may also include other components described herein in other embodiments. The signal transmission layer <NUM> may include coils <NUM>, such as inductor coils, and vias <NUM> that may connect to other layers within the integrated system. Upon measuring a certain condition, coils <NUM> may generate a resultant signal. The resultant signal may then be transmitted from the integrated system to another remote location, for example an alarm command center. For example, the integrated system may monitor the pH level of a fluid and if the monitored pH level exceeds a predetermined level, the integrated system may transmit the resultant signal.

In another embodiment, an integrated system according to the present invention may include an inductor in one layer that is capable of receiving a remote signal. The reception of the remote signal may activate the integrated system or a portion thereof. Inductive coils may be strategically positioned throughout the integrated system to activate/deactivate different portions and functionalities of the integrated system.

Additionally, an integrated system according to the present invention may incorporate remote sensing conduits such as thermocouples or fiber optic links. The remote sensing conduits may allow remote input feed to a layer within the integrated system. For example, a thermocouple with a sensing element may be placed in a harsh environment such as a high temperature environment. The thermocouple may then communicate with a layer within the integrated system and provide important information that would otherwise be unattainable.

The integrated system according to the present invention may be used in a variety of electronic devices and applications. <FIG> is a simplified block diagram of an electronic device <NUM> according to an embodiment of the present invention. The electronic device <NUM> may include a circuit board <NUM> that may have an integrated system <NUM> mounted on or within the circuit board <NUM>. The integrated system <NUM> may include components described herein in other embodiments. The circuit board <NUM> may be coupled to other components of the electronic device <NUM> such as a processor <NUM>, a user interface <NUM>, and other suitable electrical components.

The processor <NUM> may control the operations of the electronic device <NUM> and its components. The processor <NUM> may be any of a, or combination of, conventional processing systems, including microprocessors, digital signal processors, and field programmable logic arrays.

The user interface <NUM> may include a display such as an LCD screen, a CRT, a plasma screen, an LED screen or the like. The user interface <NUM> may be a keyboard, a mouse, touch screen sensors or any other user input device that would allow a user to interact with the electronic device <NUM>. The user interface <NUM> may include hard keys and/or soft keys. The user interface <NUM> may be integrated with a display in the form of a touch screen display, for example. The electronic device <NUM> may include other components depending on the electronic device application. The electronic device <NUM> may be a portable electronic device such as a digital camera, a cellular phone, an alarm system, a gaming device, or the like that may benefit from incorporation of an integrated system according to the present invention. The incorporation of an integrated system according to the present invention may reduce the size of the electronic device while maximizing performance.

It will be appreciated that different components from different embodiments may be used in combination. In other instances, well-known operations, components and circuits have not been described in detail so as not to obscure the embodiments.

Claim 1:
An integrated circuit system (<NUM>), comprising:
a semiconductor die (<NUM>);
an active layer (<NUM>) fabricated on a front side of the semiconductor die (<NUM>);
a measuring layer (<NUM>) disposed on the back side of the semiconductor die and having channels formed therein, the measuring layer being configured to analyse a fluid being passed through the channels, the integrated circuit system comprising conductive vias that connect the measuring layer (<NUM>) to other layers within the integrated circuit system (<NUM>);
an electrical component layer (<NUM>, <NUM>) disposed on the measuring layer, the electrical component layer including one or more passive components (<NUM>, <NUM>); and
a signal transmission layer (<NUM>) disposed on the electrical component layer (<NUM>, <NUM>) and comprising coils (<NUM>) for transmitting a signal to a location remote from the integrated circuit system (<NUM>), and conducive vias (<NUM>) that connect to other layers within the integrated circuit system (<NUM>), wherein the coils are adapted to transmit the signal based on a measurement reading performed by the measuring layer (<NUM>).