Patent Description:
Agricultural vehicles have become increasingly automated. Agricultural vehicles may semi-autonomously or fully-autonomously drive and perform operations on fields using implements for planting, spraying, harvesting, fertilizing, stripping/tilling, etc. These autonomous agricultural vehicles include multiple sensors (e.g., Global Navigation Satellite Systems (GNSS), Global Positioning Systems (GPS), Light Detection and Ranging (LIDAR), Radio Detection and Ranging (RADAR), Sound Navigation and Ranging (SONAR), telematics sensors, Computer Vision (CV) with mono-cameras and/or stereo-cameras, etc.) to help navigate without assistance, or with limited assistance, from human users.

<CIT> describes a turn path controller configured to select a K-turn in which a vehicle also moves rearwards between a number of possible turns based on different environmental conditions including the orientation of the vehicle and the contour of field, number of skipped rows/way-lines, limits on the size of headland area, and other conditions specific to field applications.

<CIT> describes another path planner that plans curves based on the minimal turning radius of the vehicle and thus inserts curves with the minimum turning radius into the path, thus producing gaps in the overall coverage pattern for the field.

An apparatus, according to claim <NUM>, disclosed herein includes means for obtaining a guidance path for a vehicle, means for identifying a turn in the guidance path, and means for selecting, from a plurality of predetermined turn patterns, a turn pattern for the turn, where the turn pattern satisfies a condition. The means for selecting is to select a first turn pattern and second turn pattern from the plurality of predetermined turn patterns; determine a first coverage of the first turn pattern and a second coverage of the second turn pattern; and select one of the first turn pattern or the second turn pattern corresponding to a greater one of the first coverage or the second coverage.

The figures are not to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to Earth. A first part is above a second part, if the second part has at least one part between Earth and the first part. Likewise, as used herein, a first part is "below" a second part when the first part is closer to the Earth than the second part. As noted above, a first part can be above or below a second part with one or more of: other parts therebetween, without other parts therebetween, with the first and second parts touching, or without the first and second parts being in direct contact with one another. As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween. As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in "contact" with another part is defined to mean that there is no intermediate part between the two parts.

Unless specifically stated otherwise, descriptors such as "first," "second," "third," etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. " In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name. As used herein, "approximately" and "about" refer to dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections. As used herein "substantially real time" refers to occurrence in a near instantaneous manner recognizing there may be real world delays for computing time, transmission, etc. Thus, unless otherwise specified, "substantially real time" refers to real time +/- <NUM> second. As used herein, the phrase "in communication," including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events. As used herein, "processor circuitry" is defined to include (i) one or more special purpose electrical circuits structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmed with instructions to perform specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of processor circuitry include programmed microprocessors, Field Programmable Gate Arrays (FPGAs) that may instantiate instructions, Central Processor Units (CPUs), Graphics Processor Units (GPUs), Digital Signal Processors (DSPs), XPUs, or microcontrollers and integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of processor circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and/or a combination thereof) and application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of the processing circuitry is/are best suited to execute the computing task(s).

Automation of agricultural vehicles is commercially desirable because automation can improve the accuracy with which operations are performed, reduce operator fatigue, improve efficiency, and accrue other benefits. Some automated vehicles include and/or are otherwise enabled for automation functionality, but the user may need to engage and/or disengage the automation functionality. For example, a user could switch a vehicle into an autonomous mode of operation, but the vehicle would not autonomously drive until the user presses a button or toggles a switch to "engage" automation. As such, the vehicle can be referred to as being in a "standby" autonomous mode of operation when automation is enabled but not engaged and in a "fully" autonomous mode of operation when automation is enabled and engaged. In either standby autonomous mode or fully autonomous mode, a user may be present within the vehicle.

Whether in standby autonomous mode or fully autonomous mode, autonomous vehicles include one or more controllers to ensure that the autonomous vehicles traverse terrain properly. In examples disclosed herein, automated vehicles follow guidance paths when in fully autonomous mode. A controller may have many different modes of operation including an acquisition mode of operation and a tracking mode of operation. As used herein, "tracking," "tracking mode," "tracking mode of operation," and/or their derivatives refer to following and/or tracking a guidance path (e.g., in a fully autonomous mode). As used herein, "acquisition," "acquisition mode," "acquisition mode of operation," and/or their derivatives refer to operation when the vehicle is travelling to a guidance path, a path, and/or acquiring a position that is substantially similar to (e.g., within one meter of, within a half meter of, within two meters of, etc.) a guidance path. The path a vehicle takes or may take during acquisition mode is referred to herein as "an acquisition path," and "an acquisition line," among others.

Guidance paths (e.g., target paths) are used by a navigation and/or location apparatus (e.g., a Global Positioning System (GPS) receiver) and a controller in tracking mode to cause a vehicle to follow a prescribed path. In some examples, the prescribed path includes turns, curves, etc., for the vehicle to follow when operating in a field. Conventional controllers, sometimes referred to as guidance systems, allow users of a vehicle to specify a guidance path for the vehicle in the cab.

Some known guidance systems generate steering commands to automatically steer a vehicle along a guidance path. In some locations along the guidance path, the guidance path includes sharp turns and/or corners that may not be easily traversed by the vehicle. In some cases, a turn radius of a turn along the guidance path is less than a minimum turn radius of the vehicle, the implement, and/or a combination of the vehicle and the implement. Thus, in some such cases, the vehicle is unable to accurately track the guidance path at the turn. As such, some known guidance systems require a backup of the vehicle at the turn and/or require an operator of the vehicle to manually steer the vehicle around the turn, and the guidance systems may resume automated tracking after completion of the turn. In some cases, manual operation of the vehicle may result in inefficiencies such as repeated operations over portions of a field and/or gaps in coverage of the field. Furthermore, requiring manual operation of the vehicle reduces convenience for the operator.

Examples disclosed herein enable automatic detection of a sharp turn along a guidance path, selection of a turn pattern for the sharp turn, generation of turn paths for executing the turn pattern at the sharp turn, and tracking of the turn paths by a vehicle and/or an implement of the vehicle. In some examples, the turn paths may include one or more backup paths (e.g., along which the vehicle travels in a reverse direction) and locations at which the vehicle is to raise and/or lower the implement to prevent and/or other reduce gaps in coverage of the implement. Example vehicle control circuitry disclosed herein obtains a guidance path for the vehicle and/or an implement of the vehicle, and obtains other vehicle data associated with the vehicle (e.g., a current position of the vehicle, a threshold turn radius of the vehicle and/or the implement, etc.). In some examples, the vehicle control circuitry identifies one or more sharp turns in the guidance path. In examples disclosed herein, a sharp turn refers to a portion of the guidance path at which a curvature of the guidance path is greater than a minimum turn radius (e.g., a threshold turn radius) of the vehicle, the implement, and/or a combination of the vehicle and the implement. The example vehicle control circuitry selects a turn pattern from a plurality of predetermined turn patterns that satisfies a condition. For example, the vehicle control circuitry determines that the turn pattern satisfies the condition by determining that the turn pattern is within a boundary of a headland region of a field, the turn pattern does not include a turn radius less than the threshold turn radius of the vehicle, and/or the turn pattern does not include a curved backup path. In some examples, the vehicle control circuitry generates navigation instructions based on the selected turn pattern to steer the vehicle thereupon. Advantageously, by automating selection and/or tracking of predetermined turn patterns, examples disclosed herein reduce gaps in coverage along a guidance path and/or reduce input required by a user, thus improving efficiency of operation of the vehicle.

<FIG> is a schematic illustration of an example environment <NUM> including a first example vehicle 102A and a second example vehicle 102B. In the illustrated example of <FIG>, the first vehicle 102A utilizes first example vehicle control circuitry 104A, and the second vehicle 102B utilizes second example vehicle control circuitry 104B. In this example, the vehicle control circuitry 104A, 104B guides the first vehicle 102A and the second vehicle 102B, respectively, along one or more guidance paths (e.g., travel paths). The first vehicle 102A includes an example Global Positioning System (GPS) receiver 112A, an example user interface 114A, front wheels (one of which is shown at reference numeral 116A), and rear wheels (one of which is shown at reference numeral 118A). The second vehicle 102B includes an example Global Positioning System (GPS) receiver 112B, an example user interface 114B, front wheels (one of which is shown at reference numeral 116B), and rear wheels (one of which is shown at reference numeral 118B).

As illustrated and described herein, the structure and/or function of any one of the vehicle control circuitry 104B, the GPS receiver 112B, the user interface 114B, the front wheels (e.g., the front wheel 116B), and/or the rear wheels (e.g., the rear wheel 118B), may be the same as the corresponding component on the first vehicle 102A. Therefore, for example, description and/or illustration associated with the first vehicle control circuitry 104A of the first vehicle 102A can be considered to apply equally to the second vehicle control circuitry 104B of the second vehicle 102B.

As used herein, when referring to "the vehicle <NUM>," it is to be understood that the description and/or illustration applies to both the first vehicle 102A and the second vehicle 102B. Similarly, when referring to any one or more of the components of the first vehicle 102A or the second vehicle 102B, if a component is discussed (e.g., the vehicle control circuitry <NUM>, the GPS receiver <NUM>, the user interface <NUM>, the front wheel <NUM>, the rear wheel <NUM>, etc.), it is to be understood that the illustration and/or description applies to these respective parts on both of the first vehicle 102A and the second vehicle 102B.

In the example illustrated in <FIG>, the first vehicle 102A is a tractor and the second vehicle 102B is a cotton stripper. However, the first vehicle 102A and the second vehicle 102B may be any type of vehicle (e.g., a tractor, front loader, harvester, cultivator, or any other suitable vehicle) configured to track a projected path and/or curved path. For example, the first vehicle 102A may be a tractor capable of automatically tracking a row of crops to harvest the row of crops. The first vehicle 102A and/or the second vehicle 102B may be a front wheel steer vehicle or a rear wheel steer vehicle. As used herein, a front wheel steer vehicle steers by pivoting its front wheels (such as the front wheel 116A) with respect to a vehicle frame, while a rear wheel steer vehicle steers by pivoting its rear wheels (such as the rear wheel 118B) with respect to a vehicle frame.

In some examples, the vehicle <NUM> may be implemented as an articulated vehicle that includes a different steering system as compared to front wheel and/or rear wheel steer vehicles. In examples disclosed herein, the vehicle <NUM> is equipped with the vehicle control circuitry <NUM> to control and/or otherwise command the vehicle <NUM> to track a predetermined path. For example, the vehicle control circuitry <NUM> controls steering of the vehicle <NUM> by adjusting a rotation speed and/or direction of the front and/or rear wheels <NUM>, <NUM>.

In the illustrated example of <FIG>, the first vehicle 102A is implemented as a front wheel steer vehicle. As such, the first vehicle 102A turns in response to pivoting of the front wheel 116A. For example, if the user or an autonomous driving system decides to turn left, the front wheel 116A is pivoted to the left. The second vehicle 102B is implemented as a rear wheel steer vehicle. As such, the second vehicle 102B turns in response to pivoting of the rear wheel 118B. In examples disclosed herein, the front wheels 116A, 116B are located on a front wheel axle with one or more additional corresponding front wheels. Likewise, in examples disclosed herein, the rear wheels 118A, 118B are located on a rear wheel axle with one or more additional corresponding rear wheels.

In the illustrated example of <FIG>, the GPS receiver <NUM> communicates with the vehicle control circuitry <NUM> to provide and/or otherwise transmit position data (e.g., a current position of the vehicle <NUM>) thereto. In some examples, the GPS receiver <NUM> samples the current position of the vehicle <NUM> at a threshold interval. For example, every <NUM> seconds, the GPS receiver <NUM> may send the current position to the vehicle control circuitry <NUM> for use in selecting one or more turn patterns for the vehicle <NUM>.

In the illustrated example of <FIG>, the user interface <NUM> enables an operator of the vehicle <NUM> to provide inputs to the vehicle control circuitry <NUM>. In some examples, the user interface <NUM> is implemented by a liquid crystal display (LCD) touch screen such as a tablet, a computer monitor, etc. In the example of <FIG>, the user interface <NUM> is an interactive display on which the operator may select and/or enter desired inputs (e.g., select a screen display, enter desired vehicle speed, select a sampling interval, power on and/or off the vehicle, etc.) before, during, and/or after operation of the vehicle <NUM>. In some examples, the user interface <NUM> enables the operator to select a desired turn pattern from among one or more turn pattern preloaded in the vehicle control circuitry <NUM>. In some examples, the user interface <NUM> displays a map that illustrates one or more guidance paths to be traversed by the vehicle <NUM> and/or by an implement of the vehicle <NUM>.

<FIG> is a block diagram of the example vehicle control circuitry <NUM> of <FIG>. The example vehicle control circuitry <NUM> is configured to select one or more turn pattern for the vehicle <NUM> of <FIG> and steer the vehicle <NUM> along the one or more turn pattern. In the illustrated example of <FIG>, the vehicle control circuitry <NUM> includes example input interface circuitry <NUM>, example turn identification circuitry <NUM>, example turn pattern selection circuitry <NUM>, example condition determination circuitry <NUM>, example guidance control circuitry <NUM>, example turn path generation circuitry <NUM>, and example path database circuitry <NUM>. In the example of <FIG>, any of the input interface circuitry <NUM>, the turn identification circuitry <NUM>, the turn pattern selection circuitry <NUM>, the condition determination circuitry <NUM>, the guidance control circuitry <NUM>, the turn path generation circuitry <NUM>, and/or the path database circuitry <NUM> can communicate via an example communication bus <NUM>.

In examples disclosed herein, the communication bus <NUM> may be implemented using any suitable wired and/or wireless communication. In additional or alternative examples, the communication bus <NUM> includes software, machine readable instructions, and/or communication protocols by which information is communicated among the input interface circuitry <NUM>, the turn identification circuitry <NUM>, the turn pattern selection circuitry <NUM>, the condition determination circuitry <NUM>, the guidance control circuitry <NUM>, the turn path generation circuitry <NUM>, and/or the path database circuitry <NUM>.

In the illustrated example of <FIG>, the path database circuitry <NUM> stores data utilized and/or obtained by the vehicle control circuitry <NUM>. In some examples, the path database circuitry <NUM> stores a current position of the vehicle <NUM>, one or more guidance paths to be traversed by the vehicle <NUM>, and/or one or more predetermined turn paths. The example path database circuitry <NUM> of <FIG> is implemented by any memory, storage device and/or storage disc for storing data such as, for example, flash memory, magnetic media, optical media, solid state memory, hard drive(s), thumb drive(s), etc. Furthermore, the data stored in the example path database circuitry <NUM> may be in any data format such as, for example, binary data, comma delimited data, tab delimited data, structured query language (SQL) structures, etc. While, in the illustrated example, the example path database circuitry <NUM> is illustrated as a single device, the example path database circuitry <NUM> and/or any other data storage devices described herein may be implemented by any number and/or type(s) of memories.

In the illustrated example of <FIG>, the input interface circuitry <NUM> provides data to the turn identification circuitry <NUM>, the turn pattern selection circuitry <NUM>, the condition determination circuitry <NUM>, the guidance control circuitry <NUM>, and/or the path database circuitry <NUM>. In this example, the input interface circuitry <NUM> is communicatively coupled to the user interface <NUM> and/or the GPS receiver <NUM> of <FIG> to receive and/or otherwise obtain example input data <NUM> therefrom. For example, the input interface circuitry <NUM> obtains the current position of the vehicle <NUM> from the GPS receiver <NUM>, and/or obtains a guidance path of the vehicle <NUM> selected by a user via the user interface <NUM>. In some examples, the guidance path is preloaded in the input interface circuitry <NUM> and/or the path database circuitry <NUM>. In some examples, the input interface circuitry <NUM> receives and/or otherwise obtains, from the user interface <NUM>, a desired turn pattern selected by the user from a plurality of turn patterns preloaded in the path database circuitry <NUM>.

In some examples, the vehicle control circuitry <NUM> includes means for obtaining. For example, the means for obtaining may be implemented by the input interface circuitry <NUM>. In some examples, the input interface circuitry <NUM> may be implemented by machine executable instructions such as that implemented by at least block <NUM> of <FIG> executed by processor circuitry, which may be implemented by the example processor circuitry <NUM> of <FIG>, the example processor circuitry <NUM> of <FIG>, and/or the example Field Programmable Gate Array (FPGA) circuitry <NUM> of <FIG>. In other examples, the input interface circuitry <NUM> is implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the input interface circuitry <NUM> may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

In the illustrated example of <FIG>, the turn identification circuitry <NUM> identifies turns and/or corners in the guidance path to be traversed by the vehicle <NUM>. In some examples, the turn identification circuitry <NUM> obtains the guidance path from the input interface circuitry <NUM> and/or from the path database circuitry <NUM>, and identifies locations along the guidance path at which a turn radius of the guidance path is less than a threshold turn radius. In some examples, the threshold turn radius corresponds to a minimum turn radius that can be traversed by the vehicle <NUM> and/or by an implement of the vehicle <NUM>. In some examples, the turn identification circuitry <NUM> determines the threshold turn radius based on the input data <NUM> from the GPS receiver <NUM> of <FIG>. For example, the minimum turn radius of the vehicle <NUM> can be determined by an operator of the vehicle <NUM> manually turning the vehicle <NUM> fully to the left or fully to the right, and the GPS receiver <NUM> measuring positions of the vehicle <NUM> and/or the implement of the vehicle <NUM> during travel. In such examples, the turn identification circuitry <NUM> obtains the measured positions of the vehicle <NUM> and/or the implement of the vehicle <NUM> from the input data <NUM>, and calculates and/or otherwise determines the threshold turn radius based on the measured positions. In other examples, a value of the threshold turn radius is input by the operator via the user interface <NUM> and/or is preloaded in the turn identification circuitry <NUM>.

In some examples, the locations along the guidance path that are less than the threshold turn radius correspond to sharp turns and/or corners in the guidance path. In some examples, the turn identification circuitry <NUM> stores the locations (e.g., turn locations) as GPS coordinates in the path database circuitry <NUM>. Additionally or alternatively, the turn identification circuitry <NUM> provides the locations to the turn pattern selection circuitry <NUM> for use in selecting turn patterns. In some examples, the turn identification circuitry <NUM> monitors the current position of the vehicle <NUM> when it traverses the guidance path. In such examples, when the turn identification circuitry <NUM> determines that the current position of the vehicle <NUM> is less than a threshold distance from a turn, the turn identification circuitry <NUM> directs the turn pattern selection circuitry <NUM> to select a turn pattern for the turn.

In some examples, the turn identification circuitry <NUM> modifies the guidance path of the vehicle <NUM> by placing and/or generating a minimum turn circle at each of the turn locations, where a radius of the minimum turn circle corresponds to the threshold turn radius. In some such examples, as shown in <FIG> below, the turn identification circuitry <NUM> breaks the guidance path into two segments at each of the turn locations, and extends the two segments along directions that are tangent to the minimum turn circle. In some examples, the turn identification circuitry <NUM> provides the modified guidance path to the turn pattern selection circuitry <NUM> for use in selecting and/or generating turn patterns.

In some examples, the vehicle control circuitry <NUM> includes means for identifying. For example, the means for identifying may be implemented by the turn identification circuitry <NUM>. In some examples, the turn identification circuitry <NUM> may be implemented by machine executable instructions such as that implemented by at least block <NUM> of <FIG> executed by processor circuitry, which may be implemented by the example processor circuitry <NUM> of <FIG>, the example processor circuitry <NUM> of <FIG>, and/or the example Field Programmable Gate Array (FPGA) circuitry <NUM> of <FIG>. In other examples, the turn identification circuitry <NUM> is implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the turn identification circuitry <NUM> may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

In the illustrated example of <FIG>, the turn pattern selection circuitry <NUM> selects and/or generates a turn pattern to be traversed by the vehicle <NUM>. In some examples, one or more predetermined turn pattern are preloaded in the turn pattern selection circuitry <NUM> and/or stored in the path database circuitry <NUM>. In some examples, the turn pattern selection circuitry <NUM> selects the turn pattern from the predetermined turn pattern shown in <FIG> below. However, in other examples, other turn pattern may be used instead of or in addition to the turn pattern shown in <FIG>. In examples disclosed herein, the predetermined turn pattern satisfy the threshold turn radius of the vehicle <NUM> and/or a threshold backup speed (e.g., <NUM> miles per hour). In some examples, the threshold turn radius and/or the threshold backup speed are preloaded in the turn pattern selection circuitry <NUM> and/or obtained via user input from the user interface <NUM>.

In some examples, the turn pattern selection circuitry <NUM> selects the turn pattern based on a predetermined sequence of the turn patterns, and provides the selected turn pattern to the condition determination circuitry <NUM> for use in determining whether the selected turn pattern satisfies a condition. Alternatively, in some examples, the turn pattern selection circuitry <NUM> selects the turn pattern based on user input obtained in the input data <NUM> from the user interface <NUM>. For example, the user interface <NUM> can display the predetermined turn pattern, and an operator of the vehicle <NUM> may select the turn pattern via the user interface <NUM>.

In some examples, the turn pattern selection circuitry <NUM> selects the turn pattern based on coverage of the predetermined turn patterns. For example, the turn pattern selection circuitry <NUM> determines the coverage for each of the predetermined turn pattern, and selects the turn pattern corresponding to the largest area of coverage. In other examples, the turn pattern selection circuitry <NUM> selects the turn pattern corresponding to the fewest and/or smallest gaps in coverage. Additionally or alternatively, the turn pattern selection circuitry <NUM> determines a length and/or coverage of tire tracks to be made by the vehicle <NUM> when traversing each of the predetermined turn pattern, and selects the turn pattern corresponding to the smallest length and/or coverage of the tire tracks.

In some examples, the vehicle control circuitry <NUM> includes means for selecting. For example, the means for selecting may be implemented by the turn pattern selection circuitry <NUM>. In some examples, the turn pattern selection circuitry <NUM> may be implemented by machine executable instructions such as that implemented by at least block <NUM> of <FIG> executed by processor circuitry, which may be implemented by the example processor circuitry <NUM> of <FIG>, the example processor circuitry <NUM> of <FIG>, and/or the example Field Programmable Gate Array (FPGA) circuitry <NUM> of <FIG>. In other examples, the turn pattern selection circuitry <NUM> is implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the turn pattern selection circuitry <NUM> may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

In the illustrated example of <FIG>, the turn path generation circuitry <NUM> generates one or more turn paths for the selected turn pattern. For example, the one or more turn paths can be traversed by the vehicle <NUM> to traverse the selected turn pattern. Additionally, in some examples, the turn path generation circuitry <NUM> determines locations along the one or more turns paths at which the vehicle <NUM> is to raise and/or lower the implement. In some examples, the turn path generation circuitry <NUM> causes storage of the one or more turns paths and/or the locations for raising and/or lowering of the implement in the path database circuitry <NUM>.

In some examples, the vehicle control circuitry <NUM> includes means for generating turn paths. For example, the means for generating turn paths may be implemented by the turn path generation circuitry <NUM>. In some examples, the turn path generation circuitry <NUM> may be implemented by machine executable instructions such as that implemented by at least block <NUM> of <FIG> executed by processor circuitry, which may be implemented by the example processor circuitry <NUM> of <FIG>, the example processor circuitry <NUM> of <FIG>, and/or the example Field Programmable Gate Array (FPGA) circuitry <NUM> of <FIG>. In other examples, the turn path generation circuitry <NUM> is implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the turn path generation circuitry <NUM> may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

In the illustrated example of <FIG>, the condition determination circuitry <NUM> determines whether the selected turn pattern satisfies one or more conditions. In some examples, the condition is based on whether the one or more turn paths of the turn pattern are within a boundary of a headland region of a field (e.g., a work area). In some such examples, the turn pattern satisfies the condition when the one or more turn paths are within the boundary of the headland region, and the turn pattern does not satisfy the condition when at least one of the one or more turn paths crosses the boundary of the headland region. In other examples, the condition determination circuitry <NUM> determines whether coverage by an implement of the vehicle <NUM> is within the boundary of the headland region when the vehicle <NUM> traverses the turn pattern, and determines that the turn pattern satisfies the condition when the coverage by the implement is within the boundary. In some examples, the condition determination circuitry <NUM> determines that the turn pattern satisfies the condition when the vehicle <NUM> does not cross the boundary of the headland region when traversing the turn pattern.

In some examples, in response determining that the selected turn pattern does not satisfy the condition, the condition determination circuitry <NUM> directs the turn pattern selection circuitry <NUM> to select a different turn pattern from the predetermined turn patterns. Alternatively, in response to determining that the turn pattern satisfies the condition, the condition determination circuitry <NUM> provides the turn pattern to the guidance control circuitry <NUM> for use in generating example navigation instructions <NUM>.

In some examples, the vehicle control circuitry <NUM> includes means for determining. For example, the means for determining may be implemented by the condition determination circuitry <NUM>. In some examples, the condition determination circuitry <NUM> may be implemented by machine executable instructions such as that implemented by at least block <NUM> of <FIG> executed by processor circuitry, which may be implemented by the example processor circuitry <NUM> of <FIG>, the example processor circuitry <NUM> of <FIG>, and/or the example Field Programmable Gate Array (FPGA) circuitry <NUM> of <FIG>. In other examples, the condition determination circuitry <NUM> is implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the condition determination circuitry <NUM> may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

In the illustrated example of <FIG>, the guidance control circuitry <NUM> generates the navigation instructions <NUM> based on the turn pattern. In some examples, the navigation instructions <NUM> include one or more path paths generated by the turn path generation circuitry <NUM> for the turn pattern, and include directions (e.g., forward or backward) in which the vehicle <NUM> is to travel along the one or more turn paths. Furthermore, the navigation instructions <NUM> include one or more first locations at which an implement of the vehicle <NUM> is to be raised and/or one or more second locations at which the implement of the vehicle <NUM> is to be lowered. In some examples, the navigation instructions <NUM> include speeds at which the vehicle <NUM> is to traverse the one or more turn paths. In some examples, the navigation instructions <NUM> cause steering of wheels (e.g., the front wheel <NUM> and/or the rear wheel <NUM>) of the vehicle <NUM>. For example, the navigation instructions <NUM> control an angle at which the wheels turn and/or a rotation speed of the wheels to move the vehicle <NUM> along the turn path.

In some examples, the vehicle control circuitry <NUM> includes means for generating instructions. For example, the means for generating instructions may be implemented by the guidance control circuitry <NUM>. In some examples, the guidance control circuitry <NUM> may be implemented by machine executable instructions such as that implemented by at least block <NUM> of <FIG> executed by processor circuitry, which may be implemented by the example processor circuitry <NUM> of <FIG>, the example processor circuitry <NUM> of <FIG>, and/or the example Field Programmable Gate Array (FPGA) circuitry <NUM> of <FIG>. In other examples, the guidance control circuitry <NUM> is implemented by other hardware logic circuitry, hardware implemented state machines, and/or any other combination of hardware, software, and/or firmware. For example, the guidance control circuitry <NUM> may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware, but other structures are likewise appropriate.

<FIG> illustrates an example guidance path <NUM> for the example vehicle <NUM> of <FIG>. In some examples, the guidance path <NUM> is preloaded on the vehicle control circuitry <NUM> of <FIG> and/or stored in the path database circuitry <NUM> of <FIG>. In the illustrated example of <FIG>, the turn identification circuitry <NUM> of <FIG> obtains the guidance path <NUM> from the path database circuitry <NUM> and identifies example turns (e.g., sharp turns, corners) 302A, 302B, 302C, 302D in the guidance path <NUM>. For example, the turn identification circuitry <NUM> identifies the turns 302A, 302B, 302C, 302D by identifying locations in the guidance path <NUM> at which a turn radius of the guidance path <NUM> is less than a threshold turn radius of the vehicle <NUM> and/or an implement of the vehicle <NUM>.

In the illustrated example of <FIG>, the turn identification circuitry <NUM> modifies the guidance path <NUM> at each of the turns 302A, 302B, 302C, 302D. For example, the turn identification circuitry <NUM> generates example minimum turn circles <NUM> at the turns 302A, 302B, 302C, 302D, where a radius of the minimum turn circles <NUM> corresponds to the threshold turn radius of the vehicle <NUM>. In some examples, as shown at the first turn 302A, the turn identification circuitry <NUM> breaks the guidance path <NUM> into first and second example path sections <NUM>, <NUM>, and extends the first and second path sections <NUM>, <NUM> in directions tangent to the minimum turn circle <NUM> at the first turn 302A. In some such examples, the turn pattern selection circuitry <NUM> of <FIG> selects a turn pattern for the first turn 302A that enables the vehicle <NUM> to travel from the first path section <NUM> to the second path section <NUM> without requiring a turn radius less than the threshold turn radius of the vehicle <NUM>. In some examples, the turn pattern selection circuitry <NUM> selects the turn pattern from the example turn patterns illustrated in <FIG> below.

<FIG> illustrates a first example turn pattern <NUM>. In some examples, the first turn pattern <NUM> is stored in the path database circuitry <NUM> of <FIG>. In some examples, the turn pattern selection circuitry <NUM> of <FIG> selects the first turn pattern <NUM> for guiding the vehicle <NUM> of <FIG> along the first turn 302A of <FIG> from the first path section <NUM> to the second path section <NUM>. In the illustrated example of <FIG>, the vehicle <NUM> traverses an example field <NUM> including an example headland region <NUM> and an example interior boundary <NUM> separating the headland region <NUM> from an example work area <NUM> of the field <NUM>.

In the illustrated example of <FIG>, to traverse the first turn pattern <NUM>, the vehicle <NUM> travels forward along a first example forward turn path <NUM> of the first path section <NUM>, then travels backward along a first example rearward turn path <NUM> of the first path section <NUM>. The vehicle <NUM> travels forward from the first path section <NUM> to the second path section <NUM> along an example inner curved turn path <NUM>, where a turn radius of the inner curved turn path <NUM> is greater than the threshold turn radius of the vehicle <NUM>. Furthermore, the vehicle <NUM> travels backward along a second example rearward turn path <NUM> of the second path section <NUM>, and travels forward along a second example forward turn path <NUM> of the second path section <NUM>. Upon completion of the first turn pattern <NUM>, the vehicle <NUM> can traverse a remainder of the guidance path <NUM> of <FIG>.

<FIG> illustrates a second example turn pattern <NUM>. In some examples, the second turn pattern <NUM> is stored in the path database circuitry <NUM> of <FIG>. In some examples, the turn pattern selection circuitry <NUM> of <FIG> selects the second turn pattern <NUM> for guiding the vehicle <NUM> of <FIG> along the first turn 302A of <FIG> from the first path section <NUM> to the second path section <NUM>. In some examples, the turn pattern selection circuitry <NUM> selects the second turn pattern <NUM> in response to the first turn pattern <NUM> of <FIG> not satisfying a condition. For example, the turn pattern selection circuitry <NUM> selects the second turn pattern <NUM> in response to the first turn pattern <NUM> crossing the interior boundary <NUM> of the headland region <NUM>. In some examples, the turn pattern selection circuitry <NUM> selects the second turn pattern <NUM> in response to determining that a first coverage of the first turn pattern <NUM> is less than a second coverage of the second turn pattern <NUM>.

In the illustrated example of <FIG>, to traverse the second turn pattern <NUM>, the vehicle <NUM> travels forward from the first path section <NUM> to the second path section <NUM> along the inner curved turn path <NUM>, then travels rearward along the second rearward turn path <NUM> and forward along the second forward turn path <NUM>. Upon completion of the second turn pattern <NUM>, the vehicle <NUM> can traverse a remainder of the guidance path <NUM> of <FIG>.

<FIG> illustrates a third example turn pattern <NUM>. In some examples, the third turn pattern <NUM> is stored in the path database circuitry <NUM> of <FIG>. In some examples, the turn pattern selection circuitry <NUM> of <FIG> selects the third turn pattern <NUM> for guiding the vehicle <NUM> of <FIG> along the first turn 302A of <FIG> from the first path section <NUM> to the second path section <NUM>. In some examples, the turn pattern selection circuitry <NUM> selects the third turn pattern <NUM> in response to the first turn pattern <NUM> of <FIG> and/or the second turn pattern <NUM> of <FIG> not satisfying a condition. For example, the turn pattern selection circuitry <NUM> selects the third turn pattern <NUM> in response to the first turn pattern <NUM> and/or the second turn pattern <NUM> crossing the interior boundary <NUM> of the headland region <NUM>.

In the illustrated example of <FIG>, to traverse the third turn pattern <NUM>, the vehicle <NUM> travels forward from the first path section <NUM> to the second path section <NUM> along an example outer curved turn path <NUM>, where a turn radius of the outer curved turn path <NUM> is greater than the threshold turn radius of the vehicle <NUM>. The vehicle <NUM> then travels backward along the second rearward turn path <NUM> and forward along the second forward turn path <NUM>. Upon completion of the third turn pattern <NUM>, the vehicle <NUM> can traverse a remainder of the guidance path <NUM> of <FIG>.

<FIG> illustrates a fourth example turn pattern <NUM>. In some examples, the fourth turn pattern <NUM> is stored in the path database circuitry <NUM> of <FIG>. In some examples, the turn pattern selection circuitry <NUM> of <FIG> selects the fourth turn pattern <NUM> for guiding the vehicle <NUM> of <FIG> along the first turn 302A of <FIG> from the first path section <NUM> to the second path section <NUM>. In some examples, the turn pattern selection circuitry <NUM> selects the fourth turn pattern <NUM> in response to the first turn pattern <NUM> of <FIG>, the second turn pattern <NUM> of <FIG>, and/or the third turn pattern <NUM> of <FIG> not satisfying a condition. For example, the turn pattern selection circuitry <NUM> selects the fourth turn pattern <NUM> in response to the first turn pattern <NUM>, the second turn pattern <NUM>, and/or the third turn pattern <NUM> crossing the interior boundary <NUM> of the headland region <NUM>.

In the illustrated example of <FIG>, to traverse the fourth turn pattern <NUM>, the vehicle <NUM> travels forward along the first forward turn path <NUM> of the first path section <NUM>, and travels forward from the first path section <NUM> to the second path section <NUM> along an example looped turn path <NUM>, where a turn radius of the looped turn path <NUM> is greater than the threshold turn radius of the vehicle <NUM>. The vehicle <NUM> then travels forward along the second forward turn path <NUM>. Upon completion of the fourth turn pattern <NUM>, the vehicle <NUM> can traverse a remainder of the guidance path <NUM> of <FIG>.

<FIG> illustrates a fifth example turn pattern <NUM>. In some examples, the fifth turn pattern <NUM> is stored in the path database circuitry <NUM> of <FIG>. In some examples, the turn pattern selection circuitry <NUM> of <FIG> selects the fifth turn pattern <NUM> for guiding the vehicle <NUM> of <FIG> along the first turn 302A from the first path section <NUM> to the second path section <NUM>. In some examples, the turn pattern selection circuitry <NUM> selects the fifth turn pattern <NUM> in response to the first turn pattern <NUM> of <FIG>, the second turn pattern <NUM> of <FIG>, the third turn pattern <NUM> of <FIG>, and/or the fourth turn pattern <NUM> of <FIG> not satisfying a condition. For example, the turn pattern selection circuitry <NUM> selects the fifth turn pattern <NUM> in response to the first turn pattern <NUM>, the second turn pattern <NUM>, the third turn pattern <NUM>, and/or the fourth turn pattern <NUM> crossing the interior boundary <NUM> of the headland region <NUM>.

In the illustrated example of <FIG>, to traverse the fifth turn pattern <NUM>, the vehicle <NUM> travels forward along the first forward turn path <NUM> of the first path section <NUM>, and travels backward from the first path section <NUM> to the second path section <NUM> along an example backward curved turn path <NUM>, where a turn radius of the backward curved turn path <NUM> is greater than the threshold turn radius of the vehicle <NUM>. The vehicle <NUM> then travels forward along the second forward turn path <NUM>. Upon completion of the fifth turn pattern <NUM>, the vehicle <NUM> can traverse a remainder of the guidance path <NUM> of <FIG>. In some examples, the vehicle <NUM> can traverse the backward curved turn path <NUM> when an implement of the vehicle <NUM> is fixed such that the implement does not pivot and/or otherwise rotate relative to the vehicle <NUM>. In other examples, when the implement is not fixed relative to the vehicle <NUM>, the turn pattern selection circuitry <NUM> selects a different turn pattern (e.g., the first turn pattern <NUM>, the second turn pattern <NUM>, the third turn pattern <NUM>, or the second turn pattern <NUM>) for the vehicle <NUM>.

<FIG> illustrates a top view of the example vehicle <NUM> of <FIG>. In the illustrated example of <FIG>, an example implement <NUM> is coupled to the vehicle <NUM>. In some examples, the implement <NUM> is movable between a raised position and a lowered position, where the implement <NUM> in the lowered position can perform an operation (e.g., planting, spraying, harvesting, fertilizing, stripping/tilling, etc.) on the field <NUM> of <FIG>. For example, the guidance control circuitry <NUM> of <FIG> can cause the vehicle <NUM> to raise and/or lower the implement <NUM> via the navigation instructions <NUM> of <FIG>. In this example, the implement <NUM> is rotationally coupled to the vehicle <NUM> such that the implement <NUM> can pivot and/or otherwise rotate relative to the vehicle <NUM> about an example pivot point <NUM>. In other examples, the implement <NUM> is fixed relative to the vehicle <NUM>. In some examples, the vehicle <NUM> can travel backward along a curved turn path (e.g., the backward curved turn path <NUM> of <FIG>) when the implement <NUM> is fixed relative to the vehicle <NUM>.

In the illustrated example of <FIG>, the condition determination circuitry <NUM> of <FIG> defines an example buffer zone <NUM> around the vehicle <NUM> and/or the implement <NUM>. In some examples, the condition determination circuitry <NUM> determines whether a turn pattern (e.g., the first turn pattern <NUM> of <FIG>, the second turn pattern <NUM> of <FIG>, the third turn pattern <NUM> of <FIG>, the fourth turn pattern <NUM> of <FIG>, and/or the fifth turn pattern <NUM> of <FIG>) satisfies a condition based on whether the buffer zone <NUM> of the vehicle <NUM> overlaps the headland region <NUM> of <FIG> when the vehicle <NUM> traverses the turn pattern. In some examples, the turn pattern selection circuitry <NUM> selects lengths and/or positions of the turn pattern to ensure that the buffer zone <NUM> does not overlap the headland region <NUM>. Additionally or alternatively, the turn pattern selection circuitry <NUM> selects locations at which to raise and/or lower the implement <NUM> to reduce and/or prevent operation of the implement <NUM> on the headland region <NUM>. In some such examples, the turn pattern selection circuitry <NUM> selects the locations to reduce and/or prevent repeat operations of the implement <NUM> on the work area <NUM>.

In some examples, the vehicle <NUM> includes an example implement sensor <NUM> communicatively coupled to the vehicle control circuitry <NUM> of <FIG>. In some examples, the implement sensor <NUM> measures an angular position of the implement <NUM> relative to the vehicle <NUM>. For example, the vehicle control circuitry <NUM> can determine, based on the angular position, whether the implement <NUM> is substantially aligned (e.g., within <NUM> degrees) with the vehicle <NUM>, and/or whether the implement <NUM> is rotated relative to the vehicle <NUM>.

<FIG> illustrates a first example maneuver executed by the example vehicle <NUM> of <FIG> when travelling along the first example turn pattern <NUM> of <FIG>. In the illustrated example of <FIG>, during the first maneuver, the guidance control circuitry of <FIG> generates the navigation instructions <NUM> to steer the vehicle <NUM> forward along the first path section <NUM>. In some examples, the input interface circuitry <NUM> of <FIG> periodically obtains GPS data from the GPS receiver <NUM> of <FIG> and provides the GPS data to the guidance control circuitry <NUM> of <FIG> for use in generating the navigation instructions <NUM>.

In some examples, the guidance control circuitry <NUM> determines, based on the GPS data, whether the buffer zone <NUM> of the vehicle <NUM> crosses the interior boundary <NUM> of the headland region <NUM>. In this example, in response to determining that the buffer zone <NUM> crosses the interior boundary <NUM> at an example first point <NUM>, the guidance control circuitry <NUM> causes the vehicle <NUM> to stop at a first example stop position <NUM>. In some examples, the guidance control circuitry <NUM> instructs, via the navigation instructions <NUM>, the vehicle <NUM> to raise the implement <NUM> when the vehicle <NUM> is at the first stop position <NUM>.

<FIG> illustrates a second example maneuver executed by the example vehicle <NUM> of <FIG> when travelling along the first example turn pattern <NUM> of <FIG>. In some examples, the second maneuver of <FIG> is executed in response to the vehicle <NUM> completing the first maneuver of <FIG>. In the illustrated example of <FIG>, during the second maneuver, the guidance control circuitry <NUM> of <FIG> steers the vehicle <NUM> backward along the first path section <NUM>. In some examples, the guidance control circuitry <NUM> determines, based on GPS data from the GPS receiver <NUM> of <FIG>, whether the vehicle <NUM> is at a second example stop position <NUM>. In this example, the second stop position <NUM> corresponds to a point at which the inner curved turn path <NUM> crosses the first path section <NUM>. In this example, the guidance control circuitry <NUM> causes the vehicle <NUM> to stop at the second stop position <NUM>.

<FIG> illustrates a third example maneuver executed by the example vehicle <NUM> of <FIG> when travelling along the first example turn pattern <NUM> of <FIG>. In some examples, the third maneuver of <FIG> is executed in response to the vehicle <NUM> completing the second maneuver of <FIG>. In the illustrated example of <FIG>, during the third maneuver, the guidance control circuitry <NUM> of <FIG> steers the vehicle <NUM> forward along the inner curved turn path <NUM> from the first path section <NUM> to the second path section <NUM>.

In some examples, when the vehicle <NUM> reaches the second path section <NUM>, the guidance control circuitry <NUM> steers the vehicle <NUM> forward along the second path section <NUM> until the implement <NUM> and the vehicle <NUM> are substantially aligned. In some examples, the guidance control circuitry <NUM> obtains, from the implement sensor <NUM> of <FIG>, angular position data associated with the implement <NUM> and determines whether the implement <NUM> and the vehicle <NUM> are substantially aligned (e.g., within <NUM> degrees) based on the angular position data. In the illustrated example of <FIG>, the vehicle <NUM> and the implement <NUM> are substantially aligned when the vehicle <NUM> is at an example third stop position <NUM>. As such, the guidance control circuitry <NUM> causes the vehicle <NUM> to stop at the third stop position <NUM>.

<FIG> illustrates a fourth example maneuver executed by the example vehicle <NUM> of <FIG> when travelling along the first example turn pattern <NUM> of <FIG>. In some examples, the fourth maneuver of <FIG> is executed in response to the vehicle <NUM> completing the third maneuver of <FIG>. In the illustrated example of <FIG>, during the fourth maneuver, the guidance control circuitry <NUM> of <FIG> steers the vehicle <NUM> backward along the second path section <NUM>.

In some examples, the guidance control circuitry <NUM> determines, based on GPS data from the GPS receiver <NUM> of <FIG>, whether the buffer zone <NUM> of the vehicle <NUM> and/or the implement <NUM> crosses the interior boundary <NUM> of the headland region <NUM>. In this example, in response to determining that the buffer zone <NUM> crosses the interior boundary <NUM> at an example second point <NUM>, the guidance control circuitry <NUM> causes the vehicle <NUM> to stop at a fourth example stop position <NUM>. In some examples, the guidance control circuitry <NUM> instructs the vehicle <NUM>, via the navigation instructions <NUM>, to lower the implement <NUM> when the vehicle <NUM> is at the fourth stop position <NUM>. In some examples, in response to the vehicle <NUM> completing the fourth maneuver of <FIG>, the guidance control circuitry <NUM> steers the vehicle <NUM> forward along the second path section <NUM> and enables the vehicle <NUM> to continue traversing the guidance path <NUM> of <FIG>.

<FIG> illustrates an alternative first example maneuver executed by the example vehicle <NUM> of <FIG> when travelling along the first example turn pattern <NUM> of <FIG>. In some examples, the vehicle <NUM> executes the alternative first maneuver of <FIG> instead of the first maneuver of <FIG>. For example, the vehicle <NUM> executes the alternative first maneuver when the vehicle control circuitry <NUM> is configured to reduce gaps in coverage of the field <NUM> by the implement <NUM>. In the illustrated example of <FIG>, a first example area <NUM> is covered by the implement <NUM> during a first pass in the field <NUM>, and an example second area <NUM> is to be covered by the vehicle <NUM> in a second pass. In this example, the first area <NUM> is defined by a first example boundary <NUM> and a second example boundary <NUM>, and the second area <NUM> is defined by the second boundary <NUM> and a third example boundary <NUM>. In the illustrated example of <FIG>, the guidance control circuitry <NUM> determines that the vehicle <NUM> is at an example fifth stop position <NUM> when the vehicle <NUM> is at the second boundary <NUM> between the first area <NUM> and the second area <NUM>. In some examples, the guidance control circuitry <NUM> causes the vehicle <NUM> to stop at the fifth stop position <NUM>, and causes the vehicle <NUM> to execute the second, third, and fourth maneuvers of <FIG>, <FIG>, and <FIG>, respectively, from the fifth stop position <NUM>. In some examples, by causing the vehicle <NUM> to stop at the fifth stop position <NUM> of <FIG>, the guidance control circuitry <NUM> reduces overlapping of coverage during the first and second passes in the field <NUM>.

While an example manner of implementing the vehicle control circuitry <NUM> of <FIG> is illustrated in <FIG>, one or more of the elements, processes, and/or devices illustrated in <FIG> may be combined, divided, re-arranged, omitted, eliminated, and/or implemented in any other way. Further, the example input interface circuitry <NUM>, the example turn identification circuitry <NUM>, the example turn pattern selection circuitry <NUM>, the example condition determination circuitry <NUM>, the example guidance control circuitry <NUM>, the example turn path generation circuitry <NUM>, the example path database circuitry <NUM>, and/or, more generally, the example vehicle control circuitry <NUM> of <FIG>, may be implemented by hardware, software, firmware, and/or any combination of hardware, software, and/or firmware. Thus, for example, any of the example input interface circuitry <NUM>, the example turn identification circuitry <NUM>, the example turn pattern selection circuitry <NUM>, the example condition determination circuitry <NUM>, the example guidance control circuitry <NUM>, the example turn path generation circuitry <NUM>, the example path database circuitry <NUM>, and/or, more generally, the example vehicle control circuitry <NUM>, could be implemented by processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), and/or field programmable logic device(s) (FPLD(s)) such as Field Programmable Gate Arrays (FPGAs). When reading any of the apparatus or system claims of this patent to cover a purely software and/or firmware implementation, at least one of the example input interface circuitry <NUM>, the example turn identification circuitry <NUM>, the example turn pattern selection circuitry <NUM>, the example condition determination circuitry <NUM>, the example guidance control circuitry <NUM>, the example turn path generation circuitry <NUM>, and/or the example path database circuitry <NUM> is/are hereby expressly defined to include a non-transitory computer readable storage device or storage disk such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc., including the software and/or firmware. Further still, the example vehicle control circuitry <NUM> of <FIG> may include one or more elements, processes, and/or devices in addition to, or instead of, those illustrated in <FIG>, and/or may include more than one of any or all of the illustrated elements, processes and devices.

A flowchart representative of example hardware logic circuitry, machine readable instructions, hardware implemented state machines, and/or any combination thereof for implementing the vehicle control circuitry <NUM> of <FIG> is shown in <FIG>. The machine readable instructions may be one or more executable programs or portion(s) of an executable program for execution by processor circuitry, such as the processor circuitry <NUM> shown in the example processor platform <NUM> discussed below in connection with <FIG> and/or the example processor circuitry discussed below in connection with <FIG> and/or <NUM>. The program may be embodied in software stored on one or more non-transitory computer readable storage media such as a CD, a floppy disk, a hard disk drive (HDD), a DVD, a Blu-ray disk, a volatile memory (e.g., Random Access Memory (RAM) of any type, etc.), or a non-volatile memory (e.g., FLASH memory, an HDD, etc.) associated with processor circuitry located in one or more hardware devices, but the entire program and/or parts thereof could alternatively be executed by one or more hardware devices other than the processor circuitry and/or embodied in firmware or dedicated hardware. The machine readable instructions may be distributed across multiple hardware devices and/or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a user) or an intermediate client hardware device (e.g., a radio access network (RAN) gateway that may facilitate communication between a server and an endpoint client hardware device). Similarly, the non-transitory computer readable storage media may include one or more mediums located in one or more hardware devices. Further, although the example program is described with reference to the flowchart illustrated in <FIG>, many other methods of implementing the example vehicle control circuitry <NUM> may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware. The processor circuitry may be distributed in different network locations and/or local to one or more hardware devices (e.g., a single-core processor (e.g., a single core central processor unit (CPU)), a multi-core processor (e.g., a multi-core CPU), etc.) in a single machine, multiple processors distributed across multiple servers of a server rack, multiple processors distributed across one or more server racks, a CPU and/or a FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings, etc.).

The machine readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. Machine readable instructions as described herein may be stored as data or a data structure (e.g., as portions of instructions, code, representations of code, etc.) that may be utilized to create, manufacture, and/or produce machine executable instructions. For example, the machine readable instructions may be fragmented and stored on one or more storage devices and/or computing devices (e.g., servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, in edge devices, etc.). The machine readable instructions may require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., in order to make them directly readable, interpretable, and/or executable by a computing device and/or other machine. For example, the machine readable instructions may be stored in multiple parts, which are individually compressed, encrypted, and/or stored on separate computing devices, wherein the parts when decrypted, decompressed, and/or combined form a set of machine executable instructions that implement one or more operations that may together form a program such as that described herein.

In another example, the machine readable instructions may be stored in a state in which they may be read by processor circuitry, but require addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine readable instructions on a particular computing device or other device. In another example, the machine readable instructions may need to be configured (e.g., settings stored, data input, network addresses recorded, etc.) before the machine readable instructions and/or the corresponding program(s) can be executed in whole or in part. Thus, machine readable media, as used herein, may include machine readable instructions and/or program(s) regardless of the particular format or state of the machine readable instructions and/or program(s) when stored or otherwise at rest or in transit.

As mentioned above, the example operations of <FIG> may be implemented using executable instructions (e.g., computer and/or machine readable instructions) stored on one or more non-transitory computer and/or machine readable media such as optical storage devices, magnetic storage devices, an HDD, a flash memory, a read-only memory (ROM), a CD, a DVD, a cache, a RAM of any type, a register, and/or any other storage device or storage disk in which information is stored for any duration (e.g., for extended time periods, permanently, for brief instances, for temporarily buffering, and/or for caching of the information). As used herein, the terms non-transitory computer readable medium and non-transitory computer readable storage medium is expressly defined to include any type of computer readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media.

Thus, whenever a claim employs any form of "include" or "comprise" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. The term "and/or" when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (<NUM>) A alone, (<NUM>) B alone, (<NUM>) C alone, (<NUM>) A with B, (<NUM>) A with C, (<NUM>) B with C, or (<NUM>) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase "at least one of A and B" is intended to refer to implementations including any of (<NUM>) at least one A, (<NUM>) at least one B, or (<NUM>) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase "at least one of A or B" is intended to refer to implementations including any of (<NUM>) at least one A, (<NUM>) at least one B, or (<NUM>) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase "at least one of A and B" is intended to refer to implementations including any of (<NUM>) at least one A, (<NUM>) at least one B, or (<NUM>) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase "at least one of A or B" is intended to refer to implementations including any of (<NUM>) at least one A, (<NUM>) at least one B, or (<NUM>) at least one A and at least one B.

The term "a" or "an" object, as used herein, refers to one or more of that object. The terms "a" (or "an"), "one or more", and "at least one" are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements or method actions may be implemented by, e.g., the same entity or object.

<FIG> is a flowchart representative of example machine readable instructions and/or example operations <NUM> that may be executed and/or instantiated by processor circuitry to select a turn pattern for the example vehicle <NUM> of <FIG>. The machine readable instructions and/or operations <NUM> of <FIG> begin at block <NUM>, at which the example vehicle control circuitry <NUM> of <FIG> obtains a guidance path. For example, the example input interface circuitry <NUM> of <FIG> obtains the example guidance path <NUM> of <FIG> from the example path database circuitry <NUM> of <FIG> and/or from the example user interface <NUM> of <FIG>. In some examples, the guidance path <NUM> is preloaded in the path database circuitry <NUM> and/or is selected via the user interface <NUM> by an operator of the vehicle <NUM>.

At block <NUM>, the example vehicle control circuitry <NUM> identifies one or more turns (e.g., sharp turns) in the guidance path <NUM>. For example, the example turn identification circuitry <NUM> of <FIG> identifies the turns 302A, 302B, 302C, 302D of <FIG> by identifying locations in the guidance path <NUM> at which a turn radius of the guidance path <NUM> is less than a threshold turn radius of the vehicle <NUM> and/or the implement <NUM>.

At block <NUM>, the example vehicle control circuitry <NUM> selects a turn pattern from one or more predetermined turn pattern stored in the path database circuitry <NUM>. For example, the example turn pattern selection circuitry <NUM> of <FIG> selects the turn path from the first turn pattern <NUM> of <FIG>, the second turn pattern <NUM> of <FIG>, the third turn pattern <NUM> of <FIG>, the fourth turn pattern <NUM> of <FIG>, and/or the fifth turn pattern <NUM> of <FIG>. In some examples, the turn pattern selection circuitry <NUM> selects the turn path based on a predetermined sequence of the one or more predetermined turn paths. In some examples, the example turn path generation circuitry <NUM> generates one or more turn paths corresponding to the selected turn pattern.

At block <NUM>, the example vehicle control circuitry <NUM> determines whether the selected turn pattern satisfies one or more conditions. For example, the example condition determination circuitry <NUM> determines whether the selected turn pattern satisfies the one or more conditions based on whether at least one of the turn paths of the selected turn pattern overlaps the headland region <NUM> of <FIG>. In response to the condition determination circuitry <NUM> determining that the selected turn pattern satisfies the one or more conditions (e.g., block <NUM> returns a result of YES), control proceeds to block <NUM>. Alternatively, in response to the condition determination circuitry <NUM> determining that the selected turn pattern does not satisfy the one or more conditions (e.g., block <NUM> returns a result of NO), control returns to block <NUM>.

At block <NUM>, the example vehicle control circuitry <NUM> generates the example navigation instructions <NUM> of <FIG> based on the selected turn pattern. For example, the example guidance control circuitry <NUM> generates the navigation instructions <NUM> to steer the vehicle <NUM> along the selected turn pattern.

<FIG> is a block diagram of an example processor platform <NUM> structured to execute and/or instantiate the machine readable instructions and/or operations of <FIG> to implement the vehicle control circuitry <NUM> of <FIG>. The processor platform <NUM> can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad™), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing device.

The processor platform <NUM> of the illustrated example includes processor circuitry <NUM>. The processor circuitry <NUM> of the illustrated example is hardware. For example, the processor circuitry <NUM> can be implemented by one or more integrated circuits, logic circuits, FPGAs microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The processor circuitry <NUM> may be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, the processor circuitry <NUM> implements the example input interface circuitry <NUM>, the example turn identification circuitry <NUM>, the example turn pattern selection circuitry <NUM>, the example condition determination circuitry <NUM>, the example guidance control circuitry <NUM>, and the example turn path generation circuitry <NUM>.

The processor circuitry <NUM> of the illustrated example includes a local memory <NUM> (e.g., a cache, registers, etc.). The processor circuitry <NUM> of the illustrated example is in communication with a main memory including a volatile memory <NUM> and a non-volatile memory <NUM> by a bus <NUM>. The volatile memory <NUM> may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. Access to the main memory <NUM>, <NUM> of the illustrated example is controlled by a memory controller <NUM>.

The processor platform <NUM> of the illustrated example also includes interface circuitry <NUM>. The interface circuitry <NUM> may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a PCI interface, and/or a PCIe interface.

In the illustrated example, one or more input devices <NUM> are connected to the interface circuitry <NUM>. The input device(s) <NUM> permit(s) a user to enter data and/or commands into the processor circuitry <NUM>. The input device(s) <NUM> can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system.

One or more output devices <NUM> are also connected to the interface circuitry <NUM> of the illustrated example. The output devices <NUM> can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, and/or speaker. The interface circuitry <NUM> of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip, and/or graphics processor circuitry such as a GPU.

The interface circuitry <NUM> of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and/or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) by a network <NUM>. The communication can be by, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular telephone system, an optical connection, etc..

The processor platform <NUM> of the illustrated example also includes one or more mass storage devices <NUM> to store software and/or data. Examples of such mass storage devices <NUM> include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid state storage devices such as flash memory devices, and DVD drives.

The machine executable instructions <NUM>, which may be implemented by the machine readable instructions of <FIG>, may be stored in the mass storage device <NUM>, in the volatile memory <NUM>, in the non-volatile memory <NUM>, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.

<FIG> is a block diagram of an example implementation of the processor circuitry <NUM> of <FIG>. In this example, the processor circuitry <NUM> of <FIG> is implemented by a microprocessor <NUM>. For example, the microprocessor <NUM> may implement multi-core hardware circuitry such as a CPU, a DSP, a GPU, an XPU, etc. Although it may include any number of example cores <NUM> (e.g., <NUM> core), the microprocessor <NUM> of this example is a multi-core semiconductor device including N cores. The cores <NUM> of the microprocessor <NUM> may operate independently or may cooperate to execute machine readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores <NUM> or may be executed by multiple ones of the cores <NUM> at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more of the cores <NUM>. The software program may correspond to a portion or all of the machine readable instructions and/or operations represented by the flowchart of <FIG>.

The cores <NUM> may communicate by an example bus <NUM>. In some examples, the bus <NUM> may implement a communication bus to effectuate communication associated with one(s) of the cores <NUM>. For example, the bus <NUM> may implement at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the bus <NUM> may implement any other type of computing or electrical bus. The cores <NUM> may obtain data, instructions, and/or signals from one or more external devices by example interface circuitry <NUM>. The cores <NUM> may output data, instructions, and/or signals to the one or more external devices by the interface circuitry <NUM>. Although the cores <NUM> of this example include example local memory <NUM> (e.g., Level <NUM> (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessor <NUM> also includes example shared memory <NUM> that may be shared by the cores (e.g., Level <NUM> (L2_ cache)) for high-speed access to data and/or instructions. Data and/or instructions may be transferred (e.g., shared) by writing to and/or reading from the shared memory <NUM>. The local memory <NUM> of each of the cores <NUM> and the shared memory <NUM> may be part of a hierarchy of storage devices including multiple levels of cache memory and the main memory (e.g., the main memory <NUM>, <NUM> of <FIG>). Typically, higher levels of memory in the hierarchy exhibit lower access time and have smaller storage capacity than lower levels of memory. Changes in the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.

Each core <NUM> may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core <NUM> includes control unit circuitry <NUM>, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU) <NUM>, a plurality of registers <NUM>, the L1 cache <NUM>, and an example bus <NUM>. Other structures may be present. For example, each core <NUM> may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load/store unit (LSU) circuitry, branch/jump unit circuitry, floating-point unit (FPU) circuitry, etc. The control unit circuitry <NUM> includes semiconductor-based circuits structured to control (e.g., coordinate) data movement within the corresponding core <NUM>. The AL circuitry <NUM> includes semiconductor-based circuits structured to perform one or more mathematic and/or logic operations on the data within the corresponding core <NUM>. The AL circuitry <NUM> of some examples performs integer based operations. In other examples, the AL circuitry <NUM> also performs floating point operations. In yet other examples, the AL circuitry <NUM> may include first AL circuitry that performs integer based operations and second AL circuitry that performs floating point operations. In some examples, the AL circuitry <NUM> may be referred to as an Arithmetic Logic Unit (ALU). The registers <NUM> are semiconductor-based structures to store data and/or instructions such as results of one or more of the operations performed by the AL circuitry <NUM> of the corresponding core <NUM>. For example, the registers <NUM> may include vector register(s), SIMD register(s), general purpose register(s), flag register(s), segment register(s), machine specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. The registers <NUM> may be arranged in a bank as shown in <FIG>. Alternatively, the registers <NUM> may be organized in any other arrangement, format, or structure including distributed throughout the core <NUM> to shorten access time. The bus <NUM> may implement at least one of an I2C bus, a SPI bus, a PCI bus, or a PCIe bus.

Each core <NUM> and/or, more generally, the microprocessor <NUM> may include additional and/or alternate structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more converged/common mesh stops (CMSs), one or more shifters (e.g., barrel shifter(s)) and/or other circuitry may be present. The microprocessor <NUM> is a semiconductor device fabricated to include many transistors interconnected to implement the structures described above in one or more integrated circuits (ICs) contained in one or more packages. The processor circuitry may include and/or cooperate with one or more accelerators. In some examples, accelerators are implemented by logic circuitry to perform certain tasks more quickly and/or efficiently than can be done by a general purpose processor. Examples of accelerators include ASICs and FPGAs such as those discussed herein. A GPU or other programmable device can also be an accelerator. Accelerators may be on-board the processor circuitry, in the same chip package as the processor circuitry and/or in one or more separate packages from the processor circuitry.

<FIG> is a block diagram of another example implementation of the processor circuitry <NUM> of <FIG>. In this example, the processor circuitry <NUM> is implemented by FPGA circuitry <NUM>. The FPGA circuitry <NUM> can be used, for example, to perform operations that could otherwise be performed by the example microprocessor <NUM> of <FIG> executing corresponding machine readable instructions. However, once configured, the FPGA circuitry <NUM> instantiates the machine readable instructions in hardware and, thus, can often execute the operations faster than they could be performed by a general purpose microprocessor executing the corresponding software.

More specifically, in contrast to the microprocessor <NUM> of <FIG> described above (which is a general purpose device that may be programmed to execute some or all of the machine readable instructions represented by the flowchart of <FIG> but whose interconnections and logic circuitry are fixed once fabricated), the FPGA circuitry <NUM> of the example of <FIG> includes interconnections and logic circuitry that may be configured and/or interconnected in different ways after fabrication to instantiate, for example, some or all of the machine readable instructions represented by the flowchart of <FIG>. In particular, the FPGA <NUM> may be thought of as an array of logic gates, interconnections, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnections, effectively forming one or more dedicated logic circuits (unless and until the FPGA circuitry <NUM> is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on data received by input circuitry. Those operations may correspond to some or all of the software represented by the flowchart of <FIG>. As such, the FPGA circuitry <NUM> may be structured to effectively instantiate some or all of the machine readable instructions of the flowchart of <FIG> as dedicated logic circuits to perform the operations corresponding to those software instructions in a dedicated manner analogous to an ASIC. Therefore, the FPGA circuitry <NUM> may perform the operations corresponding to the some or all of the machine readable instructions of <FIG> faster than the general purpose microprocessor can execute the same.

In the example of <FIG>, the FPGA circuitry <NUM> is structured to be programmed (and/or reprogrammed one or more times) by an end user by a hardware description language (HDL) such as Verilog. The FPGA circuitry <NUM> of <FIG>, includes example input/output (I/O) circuitry <NUM> to obtain and/or output data to/from example configuration circuitry <NUM> and/or external hardware (e.g., external hardware circuitry) <NUM>. For example, the configuration circuitry <NUM> may implement interface circuitry that may obtain machine readable instructions to configure the FPGA circuitry <NUM>, or portion(s) thereof. In some such examples, the configuration circuitry <NUM> may obtain the machine readable instructions from a user, a machine (e.g., hardware circuitry (e.g., programmed or dedicated circuitry) that may implement an Artificial Intelligence/Machine Learning (Al/ML) model to generate the instructions), etc. In some examples, the external hardware <NUM> may implement the microprocessor <NUM> of <FIG>. The FPGA circuitry <NUM> also includes an array of example logic gate circuitry <NUM>, a plurality of example configurable interconnections <NUM>, and example storage circuitry <NUM>. The logic gate circuitry <NUM> and interconnections <NUM> are configurable to instantiate one or more operations that may correspond to at least some of the machine readable instructions of <FIG> and/or other desired operations. The logic gate circuitry <NUM> shown in <FIG> is fabricated in groups or blocks. Each block includes semiconductor-based electrical structures that may be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., And gates, Or gates, Nor gates, etc.) that provide basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the logic gate circuitry <NUM> to enable configuration of the electrical structures and/or the logic gates to form circuits to perform desired operations. The logic gate circuitry <NUM> may include other electrical structures such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc..

The interconnections <NUM> of the illustrated example are conductive pathways, traces, vias, or the like that may include electrically controllable switches (e.g., transistors) whose state can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuitry <NUM> to program desired logic circuits.

The storage circuitry <NUM> of the illustrated example is structured to store result(s) of the one or more of the operations performed by corresponding logic gates. The storage circuitry <NUM> may be implemented by registers or the like. In the illustrated example, the storage circuitry <NUM> is distributed amongst the logic gate circuitry <NUM> to facilitate access and increase execution speed.

The example FPGA circuitry <NUM> of <FIG> also includes example Dedicated Operations Circuitry <NUM>. In this example, the Dedicated Operations Circuitry <NUM> includes special purpose circuitry <NUM> that may be invoked to implement commonly used functions to avoid the need to program those functions in the field. Examples of such special purpose circuitry <NUM> include memory (e.g., DRAM) controller circuitry, PCIe controller circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special purpose circuitry may be present. In some examples, the FPGA circuitry <NUM> may also include example general purpose programmable circuitry <NUM> such as an example CPU <NUM> and/or an example DSP <NUM>. Other general purpose programmable circuitry <NUM> may additionally or alternatively be present such as a GPU, an XPU, etc., that can be programmed to perform other operations.

Although <FIG> and <FIG> illustrate two example implementations of the processor circuitry <NUM> of <FIG>, many other approaches are contemplated. For example, as mentioned above, modern FPGA circuitry may include an on-board CPU, such as one or more of the example CPU <NUM> of <FIG>. Therefore, the processor circuitry <NUM> of <FIG> may additionally be implemented by combining the example microprocessor <NUM> of <FIG> and the example FPGA circuitry <NUM> of <FIG>. In some such hybrid examples, a first portion of the machine readable instructions represented by the flowchart of <FIG> may be executed by one or more of the cores <NUM> of <FIG> and a second portion of the machine readable instructions represented by the flowchart of <FIG> may be executed by the FPGA circuitry <NUM> of <FIG>.

In some examples, the processor circuitry <NUM> of <FIG> may be in one or more packages. For example, the processor circuitry <NUM> of <FIG> and/or the FPGA circuitry <NUM> of <FIG> may be in one or more packages. In some examples, an XPU may be implemented by the processor circuitry <NUM> of <FIG>, which may be in one or more packages. For example, the XPU may include a CPU in one package, a DSP in another package, a GPU in yet another package, and an FPGA in still yet another package.

Claim 1:
An apparatus (<NUM>) comprising:
means for obtaining (<NUM>) to obtain a guidance path for an agricultural vehicle (<NUM>);
means for identifying (<NUM>) a turn in the guidance path; and
means for selecting (<NUM>), from a plurality of predetermined turn patterns, a turn pattern for the turn, wherein the turn pattern satisfies a condition,
characterized in that the means for selecting (<NUM>) is to:
select a first turn pattern and second turn pattern from the plurality of predetermined turn patterns;
determine a first coverage of the first turn pattern and a second coverage of the second turn pattern; and
select one of the first turn pattern or the second turn pattern corresponding to a greater one of the first coverage or the second coverage.