Patent Description:
Aspects of the present disclosure relate to silicon-on-insulator devices, and more particularly, to structures and methods for connecting body of a silicon-on-insulator MOSFET.

Silicon-on-insulator (SOI) technology refers to the use of a layered silicon-insulator-silicon substrate in place of a conventional silicon substrate in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance. An integrated circuit built using SOI devices may show processing speed that is <NUM>% faster than a comparable bulk-based integrated circuit and power consumption being reduced by as much as <NUM>%, which makes it ideal for mobile devices. SOI chips also reduce the soft error rate, which is data corruption caused by cosmic rays and natural radioactive background signals. SOI transistors offer a unique opportunity for CMOS architectures to be more scalable. The buried oxide layer limits the punch-through that may exist on deep sub-micron bulk devices.

Due to the existence of the buried oxide layer, the body of an SOI MOSFET is often floating in circuit design, meaning no connection of the body to a bias voltage. Floating body of an SOI MOSFET results in an effect called floating body effect, a dependency of the body potential on the history of the SOI MOSFET's biasing and the carrier recombination processes. For many applications, leaving body floating causes undesired effects such as kinks in the output characteristics, leading to non-linearity, reduced breakdown voltage, and degraded reliability. For such application, body connection may be needed. However, conventional body connection approaches often comes at a cost of reduced device performance and/or increased device size. Accordingly, it would be beneficial to provide a body connection scheme without substantial performance or area penalty.

<CIT> discloses an SOI device with a semiconductor layer with source and channel regions having both a front surface and a back surface plus a back silicidation layer on a portion of the back channel surface;and a back metal connection system including vias and connected to the back silicidation layer.

The following presents a simplified summary of one or more implementations to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key nor critical elements of all implementations nor delineate the scope of any or all implementations. The sole purpose of the summary is to present concepts relate to one or more implementations in a simplified form as a prelude to a more detailed description that is presented later.

In one aspect, a silicon-on-insulator device is defined according to claim <NUM>.

In another aspect, a method is defined according to claim <NUM>.

To accomplish the foregoing and related ends, one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed.

The detailed description set forth below, in connection with the appended drawings, is intended as a description of various aspects and is not intended to represent the only aspects in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing an understanding of the various concepts.

Semiconductor-on-insulator (SOI) devices are widely used for their excellent electrical properties including lower threshold voltage, smaller parasitic capacitance, less current leakage and good switching property, etc. Conventionally, the silicon film in the channel region (body) is electrically floating. Leaving the body floating complicates device behavior due to floating body effect, such as parasitic bipolar effect, kink effect, history-dependent characteristics, etc. The floating body effect causes use of SOI devices in certain applications, such as RF, mixed signal, or high speed circuit design, challenging. The traditional remedy to the floating body effect is to provide body connection. However, the efficiency of the conventional body connection is limited and such connection often degrades device performance and consumes significant device area.

<FIG> illustrates an example body connection for an SOI MOSFET according to certain aspects of the present disclosure. From top-down view, the SOI MOSFET 100a comprises an H-shape gate having main gate 108a and gate extensions 108e, a source 114a, a drain 124a, and a body connection 104a in one or both sides of main gate 108a. As illustrated in <FIG>, to accommodate the body connection 104a, the main gate 108a is extended through the gate extensions 108e. Such extensions increase device size and add extra parasitic gate capacitance.

<FIG> illustrates another example body connection for an SOI MOSFET according to certain aspects of the present disclosure. From top-down view, the SOI MOSFET 100b comprises a gate 108b, a source 114b, a drain 124b, and a body connection 104b inside the source 114b. Such placement of body connection increases the size of the source thus increase the device size. It also reduces source to channel edge and increases source resistance. As a result, the device performance is degraded. Therefore, it would be beneficial to provide a body connections scheme that minimizes area and performance impact.

In many circuit designs, the body of an NMOS transistor is connected to a ground while the body of a PMOS transistor is connected to a supply voltage. For an NMOS transistor whose source is connected to the ground or a PMOS transistor whose source is connected to the supply voltage, the body and the source of the transistor are electrically coupled. <FIG> illustrates such an example. The circuit <NUM> is a two-input NAND gate with two inputs IN1 and IN2 and an output OUT. Both sources and both bodies of the PMOS transistors <NUM> and <NUM> are electrically coupled and connected to a supply voltage Vdd. While the source of NMOS transistor <NUM> is not electrically coupled to the body of the NMOS transistor <NUM>, the source and the body of the NMOS transistor <NUM> are electrically coupled and connected to a ground. In an SOI circuit where the body connection is needed, for a transistor whose body and source are electrically coupled, certain body connection arrangement may be made to minimize the effect on device size or performance.

<FIG> illustrates an exemplary SOI MOSFET with body connection according to certain aspects of the present disclosure. The MOSFET <NUM> comprises a back insulating layer <NUM> and a semiconductor layer on the back insulating layer <NUM>. The semiconductor layer includes a source region <NUM>, a channel region <NUM>, and a drain region <NUM>. The conductive type of the source region <NUM> and the drain region <NUM> are opposite to the conductive type of the channel region <NUM>. The source region <NUM> and the drain region <NUM> may be of a first conductive type and the channel region <NUM> may be of a second conductive type. For example, for an N-MOSFET, the source region <NUM> and the drain region <NUM> are N-type while the channel region <NUM> is P-type. For a P-MOSFET, the source region <NUM> and the drain region <NUM> are P-type while the channel region <NUM> is N-type. The source region <NUM> has a front source surface 314f and a back source surface 314b. The back source surface 314b is opposite to the front source surface 314f. The back source surface 314b is closer to the back insulating layer <NUM> than the front source surface 314f. Similarly, the channel region <NUM> has a front channel surface 304f and a back channel surface 304b. The back channel surface 304b is opposite to the front channel surface 304f. The back source channel 314b is closer to the back insulating layer <NUM> than the front channel surface 304f. A gate insulating layer <NUM> is on the front channel surface 304f of the channel region <NUM>. A gate conducting layer <NUM> is on the gate insulating layer <NUM>.

The MOSFET <NUM> further comprises a back silicidation layer <NUM> on at least a portion of the back source surface 314b of the source region <NUM> and a portion of back channel surface 304b of the channel region <NUM>. The back silicidation layer <NUM> electrically couples the channel region <NUM> to the source region <NUM>. Thus, through source region <NUM>, the channel region <NUM> may be connected to a supply voltage for a PMOS transistor or a ground for an NMOS transistor. A separate body connection or body contact is not needed.

The back silicidation layer <NUM> is formed through a silicidation process, an anneal process resulting in the formation of metal-silicon alloy (silicide) to act as a contact or contact interface for low contact resistance. For example, Titanium may be deposited on silicon to form TiSi<NUM> as a result of silicidation. Other suitable materials are possible, such as CoSi<NUM>, NiSi, etc..

The MOSFET <NUM> may further comprise a front silicidation layer <NUM> on the front source surface 314f and a front silicidation layer <NUM> on the drain region <NUM>. The front silicidation layer <NUM> provides an interface for connection of the source region <NUM>, and thus the channel region <NUM>, to a front metal connection system <NUM>. The front metal connection system <NUM> may include contacts, vias, and multi-level metal layers. The front metal connection system <NUM> may connect the source region <NUM> to a supply voltage for a PMOS transistor or a ground for an NMOS transistor. The front metal connection system <NUM> may connect the source region <NUM> to other signals.

The MOSFET <NUM> according to the present invention also comprises a back metal connection system <NUM>. The back metal connection system <NUM> includes contacts to the back silicidation layer <NUM> and also includes vias and one or more other metal layers. The source region <NUM> and/or the channel region <NUM> may be connected to a supply voltage or a ground or a signal through the back metal connection system <NUM>.

The MOSFET <NUM> may further comprise a spacer <NUM>. The spacer <NUM> electrically isolates the source region <NUM> and the front silicidation layer <NUM> from the gate conducting layer <NUM>.

<FIG> illustrate an exemplary process flow in making a body connection for an SOI MOSFET according to certain aspects of the present disclosure. In <FIG>, an SOI wafer with MOSFETs is provided. The SOI wafer comprises a sacrificial substrate <NUM>, a back insulating layer <NUM>, at least a MOSFET, and a front metal connection system <NUM>. The MOSFET comprises a source region <NUM>, a channel region <NUM>, and a drain region <NUM>, all on the back insulating layer <NUM>. In addition, the MOSFET may comprise a front silicidation layer <NUM> on the source region <NUM> and a front silicidation layer <NUM> on the drain region <NUM>. The source region <NUM> has a front source surface 414f and a back source surface 414b. The channel region <NUM> has a front channel surface 404f and a back channel surface 404b. The MOSFET also comprises a gate insulating layer <NUM> on the channel region <NUM>, a gate conducting layer <NUM> on the gate insulating layer <NUM>, and a spacer <NUM> at the sides of the gate conducting layer <NUM>. Further, the front metal connection system <NUM> provides supply voltage, ground, and/or signal connection for the MOSFET.

In <FIG>, the SOI wafer is bonded to a handle wafer <NUM>. After the bonding of the handle wafer <NUM>, the sacrificial substrate <NUM> is removed, exposing the back insulating layer <NUM>.

In <FIG>, the back insulating layer <NUM> is patterned and etched with an opening <NUM>. The opening <NUM> exposes a portion or all of the back source surface 414b and a portion or all of the back channel surface 404b.

In <FIG>, a back silicidation layer <NUM> is formed over the exposed portion of the back source surface 414b and the exposed portion of the back channel surface 404b. The back silicidation layer <NUM> electrically couples the channel region <NUM> to the source region <NUM>. Thus, through source region <NUM>, the channel region <NUM> may be connected to a supply voltage for a PMOS transistor or a ground for an NMOS transistor.

In <FIG>, a back metal connection system <NUM> is formed. The back metal connection system <NUM> includes contacts to the back silicidation layer <NUM>, vias, and one or more other metal layers. The source region <NUM> and/or the channel region <NUM> may be connected to a supply voltage, a ground, or a signal through the back metal connection system <NUM>.

<FIG> illustrates an exemplary method <NUM> in making a body connection for an SOI MOSFET according to certain aspects of the present disclosure. At <NUM>, an SOI wafer with MOSFETs is provided. The SOI wafer comprises a sacrificial substrate (e.g., the sacrificial substrate <NUM>), a back insulating layer (e.g., the back insulating layer <NUM> or <NUM>), at least a MOSFET, and a front metal connection system (e.g., the front metal connection system <NUM> or <NUM>). The MOSFET comprises a source region (e.g., the source region <NUM> or <NUM>), a channel region (e.g., the channel region <NUM> or <NUM>), and a drain region (e.g., the drain region <NUM> or <NUM>), all on the back insulating layer. In addition, the MOSFET may comprise a front silicidation layer (e.g., the front silicidation layer <NUM> or <NUM>) on the source region and a front silicidation layer (e.g., the front silicidation layer <NUM> or <NUM>) on the drain region. The MOSFET also comprises a gate insulating layer (e.g., the gate insulating layer <NUM> or <NUM>) on the channel region, a gate conducting layer (e.g., the gate conducting layer <NUM> or <NUM>) on the gate insulating layer, and a spacer (e.g., the spacer <NUM> or <NUM>) at the sides of the gate conducting layer. Further, The front metal connection system provides supply voltage, ground, and/or signal connection for the MOSFET.

At <NUM>, the SOI wafer is bonded to a handle wafer (e.g., the handle wafer <NUM>). After the bonding of the handle wafer, the sacrificial substrate is removed, exposing the back insulating layer.

At <NUM>, the back insulating layer is patterned and etched with an opening (e.g., the opening <NUM>). The opening exposes a portion or all of the back source surface and a portion or all of the back channel surface.

At <NUM>, a back silicidation layer (e.g., the back silicidation layer <NUM> or <NUM>) is formed in the exposed back source surface and the exposed back channel surface. The back silicidation layer electrically couples the channel region to the source region. Thus, through source region, the channel region may be connected to a supply voltage for a PMOS transistor or a ground for an NMOS transistor.

At <NUM>, a back metal connection system (e.g., the back metal connection system <NUM> or <NUM>) may be formed. The back metal connection system may include contacts to the back silicidation layer, vias, and one or more metal layers. The source region and/or the channel region may be connected to a supply voltage or a ground or a signal through the back metal connection system.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art.

Claim 1:
A silicon-on-insulator device, comprising:
a back insulating layer (<NUM>);
a semiconductor layer on the back insulating layer (<NUM>), wherein the semiconductor layer includes a source region (<NUM>) of a first conductive type having a front source surface and a back source surface, a channel region (<NUM>) of a second conductive type having a front channel surface and a back channel surface, and a drain region (<NUM>) of the first conductive type;
a gate insulating layer (<NUM>) on the front channel surface of the channel region;
a gate conducting layer (<NUM>) on the gate insulating layer (<NUM>); and
a back silicidation layer (<NUM>) on at least a portion of the back source surface and at least a portion of the back channel surface;
a back metal connection system (<NUM>) connected to the back silicidation layer (<NUM>), wherein the back metal connection system includes vias and one or more metal layers, wherein the one or more metal layers are located on a surface of the back insulating layer opposite to the semiconductor layer, and wherein the vias are located between the back silicidation layer (<NUM>) and the one or more metal layers.