Patent Description:
Many IC layout designs route common clock lines to both the IP block and the CSRs, such that the CSRs operate at the same clock speed as the IP blocks. This results in higher power dissipation, additional latency in accessing the CSRs, more constraints on the physical placement of retention power rails, and the inability of software to update the CSRs without also powering up the IP blocks. Other layout designs run the CSRs of an IP block on a slower dedicated clock with custom clock domain crossing (CDC) synchronizers. However, these custom CDC synchronizers can require significant design effort, incur a significant design area penalty, and increase power consumption. Document <CIT> discloses a method and system for performing an operation such as programming or reading registers and/or counters in a CSR/ RMON block to reduce power consumption by providing a clock signal to a CSR/RMON block substantially only when the CSR/RMON block is having an operation performed thereon.

This document describes systems and techniques that enable independent clocking for CSRs. The described systems and techniques provides a clock signal to a CSR set of an IP block with a derived clock rate that is an integer division slower than a clock rate of another clock signal that enables operations of the IP block, which includes communication between the IP block and an application processor. The derived clock rate is synchronous to but independent of the clock rate. In this way, the application processor and other entities access the CSR set independent of clocking of the IP block. For example, the application processor can read from or write to the CSR set without waking the IP block from an Auto Clock Gated (ACG) mode. The described aspects of independent clocking may also be implemented with a minimal increase in IC design area (e.g., less complexity) and reduce the power dissipation associated with the CSR set.

An integrated circuit (IC) includes an IP block, an asynchronous bridge, and a clock manager. The IP block includes at least one IP subsystem and a CSR set associated with the at least one IP subsystem. The asynchronous bridge operatively couples the CSR set of the IP block to an application processor associated with the IC. The clock manager is operatively coupled to the asynchronous bridge, the IP block, and the CSR set together. The clock manager generates a first clock signal and provide it to the IP block to enable communication between the IP subsystems and the application processor. The clock manager also generates a second clock signal. The second clock signal has a derived clock rate that is an integer division slower than the clock rate of the first clock signal. The second clock signal is selectively gated independent of the first clock signal. The clock manager also provides the second clock signal to the CSR set and the asynchronous bridge to enable communication between the application processor and the CSR set at the derived clock rate.

This document also describes other methods, configurations, and systems that enable independent clocking for CSRs.

This Summary introduces simplified concepts for an independent clocking for CSRs, which is further described below in the Detailed Description and Drawings. This Summary is not intended to identify essential features of the claimed subject matter, nor is it intended for use in determining the scope of the claimed subject matter.

The details of one or more aspects of an independent clocking for CSRs are described in this document with reference to the following drawings. The same numbers are used throughout multiple drawings to reference like features and components:.

This document describes aspects of independent clocking for CSRs. In various aspects, IP blocks of an SoC include IP subsystems with an associated CSR set. The IP blocks can be spread across the SoC and located within different power domains or clock domains. The IP blocks generally support a configuration access port or channel that is accessible by an application processor or host of the SoC. The described aspects provide a configuration access channel that generally runs at a different clock rate than the clock rate of the IP block (e.g., core of the IP block). This document describes embodiments and examples in the context of an SoC that includes IP blocks and IP subsystems for convenience. The principles of this document may be applied generally to functional blocks, IP blocks, or subsystems of an SoC or IC that include CSRs and to enable operation of the CSR set on a different and independent clock domain than the blocks and subsystems.

As described above, the CSR set can provide control elements and status updates associated with the IP blocks and IP subsystems. The CSR set can configure the hardware of the IP blocks to perform in a specified manner. The application processor or software routines can also use the CSRs to read the current status of events occurring in the IP subsystems and IP blocks. A particular CSR set can include several attributes, including control only (e.g., read and write operations available for the application processor and read-only operations available for the IP subsystems), monitoring only (e.g., read-only operations available for the application processor, and read and write operations available for the IP subsystems), or a combination of both.

The clocking and placement of CSRs usually involve consideration of several issues. For example, engineers may consider the power dissipation from the CSRs, circuit-routing ease, and whether to retain CSR values during a power-down of the IP block. Design engineers may also consider whether the IP block should be powered up from an ACG mode before the application processor can read or write to the CSRs of the IP block. The ACG feature can gate the core clock at the root level to save clock routing and power when the IP block is inactive (e.g., powered down or placed in a low-power sleep state). In addition, design engineers may consider the generation of Register Transfer Level (RTL) code for the CSR design.

The described systems and techniques enable independent clocking for CSRs that uses a derived clock rate that is synchronous to and an integer division slower than the clock rate of the core clock signal. The described independent clocking aspects allow an application processor to read from and write to the CSRs seamlessly. Because a clock manager or a clock gate controller can selectively gate the derived clock signal independent of the core clock signal, the application processor can access the CSR set even when the IP block is in ACG mode. Aspects of the described independent clocking also allows engineers to place the CSR set near the retention power rail without negatively impacting chip timing.

The SoC or integrated circuit includes an IP block, an asynchronous bridge, and a clock manager. The IP block includes at least one IP subsystem and a CSR set associated with the IP subsystems. The asynchronous bridge operatively couples the CSR set to an application processor. The clock manager operatively couples the asynchronous bridge, the IP block, and the CSR set together. The clock manager generates a first clock signal and provide it to the IP block to enable communication between the IP subsystems and the application processor. The clock manager generates a second clock signal. The second clock signal has a derived clock rate that is an integer division slower than the clock rate of the first clock signal. The second clock signal is selectively gated independent of the first clock signal. The clock manager also provides the second clock signal to the CSR set and the asynchronous bridge to enable communication between the application processor and the CSR set at the derived clock rate.

This example is just one illustration of independent clocking for CSRs to improve the clocking and placement of CSRs in SoCs. Other example configurations and methods are described throughout this document. This document now describes additional example methods, configurations, and components for the described independent clocking for CSRs.

<FIG> illustrates an example device diagram <NUM> of a user device <NUM> in which aspects of independent clocking for CSRs can be implemented. The user device <NUM> may include additional components and interfaces omitted from <FIG> for the sake of clarity.

The user device <NUM> can be implemented as a variety of consumer electronic devices. As non-limiting examples, the user device <NUM> can be a mobile phone <NUM>-<NUM>, a tablet device <NUM>-<NUM>, a laptop computer <NUM>-<NUM>, a desktop computer <NUM>-<NUM>, a computerized watch <NUM>-<NUM>, a wearable computer <NUM>-<NUM>, a video game console <NUM>-<NUM>, or a voice-assistant system <NUM>-<NUM>.

The user device <NUM> can include one or more radio frequency (RF) transceivers <NUM> for communicating over wireless networks. The user device <NUM> can tune the RF transceivers <NUM> and supporting circuitry (e.g., antennas, front-end modules, amplifiers) to one or more frequency bands defined by various communication standards.

The user device <NUM> also includes the integrated circuit <NUM>. The integrated circuit <NUM> can include, as non-limiting examples, an SoC, a central processing unit, a graphics processing unit, an ASIC, a field-programmable gate array (FPGA), a media controller, a memory controller, a tensor processing unit, or any other hardware circuit that supports a configuration access channel. The integrated circuit <NUM> generally integrates several components of the user device <NUM> into a single chip, including a central processing unit, memory, and input and output ports. The integrated circuit <NUM> can include a single core or multiple cores. In the depicted implementation, the integrated circuit <NUM> includes one or more IP blocks <NUM>, an application processor <NUM>, a clock manager <NUM>, and computer-readable storage media (CRM) <NUM>. The integrated circuit <NUM> can include other components, including communication units (e.g., modems), input/output controllers, and system interfaces.

Each IP block <NUM> includes one or more IP subsystems <NUM> and a CSR set <NUM>. The IP blocks <NUM> represent a collection of the IP subsystems <NUM> within a particular power domain or clock domain of the integrated circuit <NUM>. The IP blocks <NUM> can be implemented as another processor, engine, or co-processor of the integrated circuit <NUM> that enables certain functionalities of the user device <NUM>. This document identifies and describes various example IP blocks <NUM> with respect to <FIG>. The CSR set <NUM> includes a collection of CSRs that each provides information to hardware or software of the IC <NUM> about the status of events and configuration values associated with the IP block <NUM> or the IP subsystems <NUM>. The CSR set <NUM> can be saved and restored across a power-cycle event for the corresponding IP block <NUM> or power domain.

The application processor <NUM> can include a combined processor and memory system that executes computer-executable instructions stored on computer-readable storage media (e.g., CRM <NUM> or CRM <NUM>) to control the operation of the integrated circuit <NUM> and enable functionalities of the user device <NUM>. Generally, the application processor <NUM> may be implemented at least partially in hardware. For example, the application processor <NUM> can execute firmware, an operating system, or other computer-executable instructions to read from or write to the CSR set <NUM> associated with an IP subsystem <NUM> of a particular IP block <NUM>.

The clock manager <NUM> generates one or more derived clock signals (e.g., a derived core clock signal or a second clock signal) with a derived clock rate that is synchronous to the clock rate of a core clock signal (e.g., a first clock signal). In some implementations, the derived clock rate is an integer division slower (e.g., two, three, four, five, or six) than the clock rate of the core clock signal. In other implementations, the derived clock rate is an integer multiplication faster (e.g., two, three, four, five, or six) than the clock rate of the core clock signal. The core clock signal enables the communication between the IP subsystems <NUM> and the application processor <NUM>. The derived clock signal enables the communications between the application processor <NUM> and the CSR set <NUM> at the derived clock rate. The described independent clocking can selectively gate the derived clock signal independent of the core clock signal (and vice versa), enabling software updates (e.g., write operations) and readouts (e.g., read operations) to occur seamlessly and without additional latencies. The clock manager <NUM> can be implemented with or include hardware, firmware, software, or a combination thereof. The clock manager <NUM> is operably coupled to the IP blocks <NUM> and the CSR set <NUM>.

The CRM <NUM> is a suitable storage device (e.g., static random access memory (SRAM), dynamic RAM (DRAM), non-volatile RAM (NVRAM), synchronous dynamic RAM (SDRAM)) to store data accessible by the application processor <NUM> and/or IP blocks <NUM>. The CRM <NUM> enables persistent or non-transitory data storage of system data, which can include firmware, an operating system, applications, and any other types of information or data related to operational aspects of the integrated circuit <NUM>. In other implementations, the CRM <NUM> can be located outside the integrated circuit <NUM>.

The user device <NUM> also includes computer-readable storage media (CRM) <NUM>. The CRM <NUM> is a suitable storage device (e.g., random-access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NVRAM), read-only memory (ROM), Flash memory) to store device data of the user device <NUM>. The device data can include an operating system, one or more applications, user data, and multimedia data. In other implementations, the CRM <NUM> can store the operating system and a subset of the applications, user data, and multimedia data of the integrated circuit <NUM>. The operating system generally manages hardware and software resources of the user device <NUM> and provides common services. The operating system and the applications are generally executable by the integrated circuit <NUM> to enable communications and user interaction with the user device <NUM>, which may require accessing data in the CRM <NUM> or the CRM <NUM>.

<FIG> illustrates an example device diagram <NUM> of an SoC <NUM> in which aspects of independent clocking for CSRs can be implemented. In this example, the SoC <NUM> includes similar components to those shown in the integrated circuit <NUM> of <FIG>, with some additional detail. The SoC <NUM> can include additional components, which are not illustrated in <FIG>.

The SoC <NUM> includes multiple IP blocks <NUM>, the application processor <NUM>, the clock manager <NUM>, and the CRM <NUM>. The IP blocks <NUM> include an IP block (A) <NUM>-<NUM> and one or more additional IP blocks, including an IP block (n) <NUM>-n, where n represents a positive integer greater than one.

Each of the IP blocks <NUM> includes one or more IP subsystems <NUM> and a CSR set <NUM>. In this example, the IP block (A) <NUM>-<NUM> includes IP subsystem (A1) <NUM>-<NUM> and IP subsystem (A2) <NUM>-<NUM> operably connected to a CSR set (A) <NUM>-<NUM>. The IP block (n) <NUM>-n includes IP subsystem (n<NUM>) <NUM>-n1 and IP subsystem (nm) <NUM>-nm operably connected to a CSR set (n) <NUM>-n, where m represents a positive integer greater than one.

The CSR sets <NUM> store configuration and registration values of or associated with the IP subsystems <NUM>. The CSR sets <NUM> are generally always on and sufficiently numerous to store configuration and registration values of the IP subsystems <NUM> of the SoC <NUM>.

The clock manager <NUM> includes one or more clock gate controllers <NUM>. The clock manager <NUM> is operatively coupled to the IP blocks <NUM> and the CSR sets <NUM>. The clock gate controllers <NUM> can "gate" or turn off a clock signal (e.g., a first clock signal or a second clock signal) for a particular IP block <NUM> when the clock signal is not needed to save dynamic power. For example, one of the clock gate controllers <NUM> can selectively gate the core clock signal provided to the IP blocks <NUM> independent of the derived clock signal. The core clock signal enables operation of the IP block and subsystems thereof, such as the communication between the at least one IP subsystems <NUM> (e.g., the IP subsystem A1 <NUM>-<NUM>) and the application processor <NUM>.

Similarly, one or more other clock gate controllers <NUM> can selectively gate the derived clock signal provided to the CSR set <NUM> independent of the core clock signal. The derived clock signal enables communication between the application processor <NUM> and the CSR set <NUM> at the derived clock rate. The clock gate controllers <NUM> can include hardware, firmware, software, or a combination thereof. The clock gate controllers <NUM> can be included as a part of the clock manager <NUM> or separate from the clock manager <NUM>.

This document describes the arrangement and operation of the independent clocking for the CSR set <NUM>, specifically the arrangement and operation of the IP block <NUM>, IP subsystems <NUM>, the CSR set <NUM>, the application processor <NUM>, the clock manager <NUM>, and the clock gate controllers <NUM>, in greater detail with respect to <FIG> and/or the SoC of <FIG>. This document also describes an example method performed by aspects of the independent clocking for the CSR set <NUM> in greater detail with respect to <FIG>.

This section illustrates example configurations of independent clocking for CSRs, which may occur separately or together in whole or in part. This section describes the example configurations in relation to drawings for ease of reading.

<FIG> illustrates a diagram <NUM> of independent clocking for CSRs. Aspects of the independent clocking can be implemented in the SoC <NUM> and include additional components, which are not illustrated in <FIG>. The diagram <NUM> illustrates a configuration for providing a derived clock signal <NUM> that is synchronous to, but has a derived clock rate that is an integer division slower or an integer multiplication faster than a clock rate of a core clock signal <NUM>. Generally, the aspects described herein enable independent clocking of the IP block and CSRs with separate clocks that operate at different frequencies and/or gating to facilitate independent operation or access to the IP subsystem or the CSRs. By so doing, an application processor or host of an SoC may access the CSRs or IP subsystem while the other entity is clocked at a slower frequency or inactive, thereby reducing power consumed by the IP block, IP subsystems, or CSR circuits.

Any coupling or connection between various components may be direct or indirect, such as made through one or more intervening components.

Similar to <FIG>, the SoC <NUM> includes the IP block (A) <NUM>-<NUM> with the IP subsystem (A1) <NUM>-<NUM>, the IP subsystem (A2) <NUM>-<NUM>, and the IP subsystem (A3) <NUM>-<NUM>, and the CSR set <NUM>. The SoC <NUM> can also includes the application processor <NUM>, an asynchronous bridge <NUM>, a retention power rail <NUM>, the clock manager <NUM>, and multiple clock gate controllers <NUM> (e.g., a clock gate controller <NUM>-<NUM>, clock gate controller <NUM>-<NUM>, and clock gate controller <NUM>-<NUM>).

The asynchronous bridge <NUM> enables communication (e.g., data transmission) between different clock domains. For example, the asynchronous bridge <NUM> can enable buffered synchronization of communications between the different clock domains associated with the core clock signal <NUM>, the derived clock signal <NUM>, and a configuration clock signal <NUM>. In the depicted implementation, the application processor <NUM> can utilize a configuration access channel <NUM> to read or write a configuration value to the CSR set <NUM>. The configuration access channel <NUM> can operate on a configuration clock signal <NUM>, which can have a clock rate the same as or different than the core clock signal <NUM> or the derived clock signal <NUM>. The application processor <NUM> operatively couples to the asynchronous bridge <NUM> via the configuration access channel <NUM>. The asynchronous bridge <NUM> is operatively coupled to the CSR set <NUM> via the configuration access channel <NUM>.

In aspects, the IP block (A) <NUM>-<NUM> is operably connected to the retention power rail <NUM>. The retention power rail <NUM> provides power to the registers (e.g., flops) within the CSR set <NUM>. The described independent clocking allows the retention power rail <NUM> to operatively couple to the CSR set <NUM> that can operate at a slower clock rate than the core clock signal <NUM>. This design may also enable the CSR set <NUM> to be placed near the retention power rail <NUM> without negatively impacting the timing of the SoC <NUM>.

The clock manager <NUM> generates the core clock signal <NUM> and the derived clock signal <NUM>. The clock manager <NUM> is operatively coupled to the asynchronous bridge <NUM>, the IP block (A) <NUM>-<NUM>, and the CSR set <NUM>. The clock manager <NUM> is also operatively coupled to the clock gate controller <NUM>-<NUM>, the clock gate controller <NUM>-<NUM>, and the clock gate controller <NUM>-<NUM>. In aspects, the clock manager <NUM> provides the core clock signal <NUM> to the IP block (A) <NUM>-<NUM> to enable operation of the IP block, which may include communication between the IP subsystems <NUM> and the application processor <NUM>. The clock manager also provides the derived clock signal <NUM> to the CSR set <NUM> and the asynchronous bridge <NUM> to enable communications between the application processor <NUM> and the CSR set <NUM> at a derived clock rate.

The derived clock signal <NUM> has the derived clock rate that is an integer division slower or an integer multiplication faster than the core clock signal <NUM>. The clock manager <NUM> can dynamically adjust the derived clock rate to different integer divisions or different integer multiplications of the clock rate of the core clock signal <NUM>. For example, the different integer divisions of the derived clock rate can be equal to two, three, four, five, six, or another integer. The different integer multiplications of the derived clock rate can be equal to two, three, four, five, six, or another integer. In this way, the derived clock signal <NUM> can operate at a slower or faster rate than the core clock signal <NUM>. As described above, the derived clock signal <NUM> is an integer division slower (e.g., two, four, or six times slower) than the core clock signal <NUM>. The clock manager <NUM> can also ensure that the derived clock signal <NUM> is synchronous to the core clock signal <NUM>.

One or more circuit paths that terminate at the CSR set <NUM> can be configured as multi-cycle paths. The derived clock rate scales along with the clock rate of the core clock signal <NUM> to support various dynamic voltage and frequency scaling (DVFS) frequency values. As such, aspects of the independent clocking enables clock adjustment for any potential integer division value or potential integer multiplication value without a loss of the phase relationship between the core clock signal <NUM> and the derived clock signal <NUM>. In this way, aspects of the described independent clocking provide synchronous clocking and avoids violation of the multi-cycle path phasing for the SoC <NUM>.

The derived clock signal <NUM> is selectively gated independent of the core clock signal <NUM> and the core clock signal <NUM> can be selectively gated independent of the derived clock signal <NUM>. In this way, a performance point of the derived clock signal <NUM> is independent of a performance point of the core clock signal <NUM>. For example, the clock gate controller <NUM>-<NUM> is operatively coupled between the clock manager <NUM> and the CSR set <NUM> and can selectively gate the derived clock signal <NUM> independent of whether the core clock signal <NUM> is gated. In this way, the application processor <NUM> can write a configuration value to the CSR set <NUM> at the derived clock rate when the core clock signal <NUM> is gated (e.g., during enabling of an ACG mode for the IP block (A) <NUM>-<NUM>). Similarly, the clock gate controller <NUM>-<NUM> is operatively coupled between the clock manager <NUM> and the IP subsystems <NUM> and can selectively gate the core clock signal <NUM> independent of whether the derived clock signal <NUM> is gated. The clock gate controller <NUM>-<NUM> can, for example, gate the core clock signal <NUM> to enable an ACG mode for the IP block (A) <NUM>-<NUM> or the IP subsystems <NUM>. The clock gate controller <NUM>-<NUM> may be operatively coupled between the clock manager <NUM> and the asynchronous bridge <NUM> and can selectively gate the configuration clock signal <NUM>.

In the depicted implementation, the SoC <NUM> includes a single IP block <NUM>, a single asynchronous bridge <NUM>, and a single clock manager <NUM>. In other implementations, the SoC <NUM> can include multiple IP blocks <NUM>. Each of the multiple IP blocks <NUM> can include respective IP subsystems <NUM> and a respective CSR set <NUM> associated with the IP subsystem <NUM>. The SoC <NUM> can also include multiple respective asynchronous bridges <NUM>. Each of the multiple asynchronous bridges <NUM> is operatively coupled between the application processor <NUM> and the respective CSR sets <NUM> of the multiple IP blocks <NUM>. The SoC <NUM> can also include multiple respective clock managers <NUM>, each of which is operatively coupled to the respective asynchronous bridge <NUM>, the respective IP block <NUM>, and the respective CSR set <NUM>.

<FIG> illustrates an example timing diagram <NUM> of clock signals for the independent clocking. In this example, the SoC <NUM> includes similar components and signals to those shown in the SoC <NUM> of <FIG>, with some additional detail for the core clock signal and derived clock signals.

Generally, the clock manager <NUM> can generate a core clock signal <NUM> with a core clock rate, such as for an IP block subsystem or IP block core. The core clock signal <NUM> may be similar to the core clock signal <NUM> illustrated in <FIG>. The clock manager <NUM> can provide the core clock signal <NUM> to enable communication between the IP subsystems <NUM> of an IP block <NUM> and the application processor <NUM>.

The clock manager <NUM> can also generate a derived clock signal <NUM>, <NUM>, or <NUM>. In the depicted implementation, the derived clock signal <NUM>, <NUM>, or <NUM> has a derived clock rate that is an integer division slower than the core clock rate of the core clock signal <NUM>. For example, the derived clock rate of the derived clock signal <NUM> is two times slower (e.g., division of two) than the core clock rate. The derived clock rate of the derived clock signal <NUM> is four times slower (e.g., division of four) than the core clock rate. And the derived clock rate of the derived clock signal <NUM> is six times slower (e.g., division of six) than the core clock rate. The derived clock signals <NUM>, <NUM>, and <NUM> are synchronous with the core clock signal <NUM>, as illustrated by the alignment of their respective phases. By synchronous, it is meant that the rising edge of the derived clock signals <NUM>, <NUM>, and <NUM> coincide with a rising edge of the core clock signal <NUM>. While the duty cycle of each of the derived clock signals <NUM>, <NUM>, and <NUM> is shown as being similar (e.g., fifty percent) to the duty cycle of the core clock signal <NUM>, this is not necessarily true in all implementations.

<FIG> illustrates an example diagram <NUM> to enable the described aspects of independent clocking for CSRs for a monitoring-only attribute (e.g., a read-only attribute). In this example, the SoC <NUM> includes similar components and signals to those shown in the SoC of <FIG> with some additional detail. The CSR set <NUM> supports a monitoring-only attribute, in which the application processor <NUM> has read-only operations available, and the IP subsystems <NUM> have read and write operations available.

The diagram <NUM> includes multiplexers <NUM>, <NUM>, and <NUM> and latches <NUM>, <NUM>, <NUM>, and <NUM>. The multiplexer <NUM> is operatively coupled to the latch <NUM>. The inputs to the multiplexer <NUM> include an HW_Data signal <NUM> and a Data signal <NUM>. The HW_Data signal <NUM> can convey, for example, a read or write command. The Data signal <NUM> can, for example, convey the data value associated with the write command. The selection between the HW_Data signal <NUM> and the Data signal <NUM> is directed by a data write-enable signal <NUM> (Data_Wen <NUM>).

The latch <NUM> includes inputs of the core clock signal (Core_Clk) <NUM> and the output of the multiplexer <NUM>. The output of the latch <NUM> is the Data signal <NUM> that is provided to the multiplexer <NUM>. The multiplexer <NUM> is operatively coupled between the latch <NUM> and the latch <NUM>. The inputs to the multiplexer <NUM> include the Data signal <NUM> and a quadrature-phase data signal (Data_Q) <NUM>. The selection between the Data signal <NUM> and the Data_Q signal <NUM> is directed by an En_Xor <NUM> signal.

The latch <NUM> includes inputs of the core clock signal (Core_Clk) <NUM> and the output of the multiplexer <NUM>. The output of the latch <NUM> is the Data_Q signal <NUM> that is provided to the multiplexer <NUM> and the latch <NUM>. The multiplexer <NUM> is operatively coupled to the latch <NUM>. The inputs to the multiplexer <NUM> include an HW_En signal <NUM> and the Data_Q signal <NUM>. The selection between the HW_En signal <NUM> and the Data_Q signal <NUM> is directed by the En_Xor <NUM> signal.

The latch <NUM> includes inputs of the core clock signal (Core_Clk) <NUM> and the output of the multiplexer <NUM>. The output of the latch <NUM> is the HW_En signal <NUM>. And the latch <NUM> is operatively coupled to the latch <NUM>. The latch <NUM> includes inputs of the Clock_Div_Value signal <NUM> (e.g., values two, three, four, five, or six) and the Data_Q signal <NUM>. The output of the latch <NUM> is a Data_CSR signal <NUM>. In aspects, use of the Clock_Div_Value signal <NUM> may enable independent monitoring of the CSRs by the application processor <NUM> and read and write operations by the IP subsystems <NUM> of the IP block <NUM> independent of the core clock signal or power state of the IP block.

<FIG> illustrates an example timing diagram <NUM> depicting aspects of the described independent clocking for CSRs for a monitoring-only attribute. The descriptions related to <FIG> reference the hardware and techniques described above with respect to <FIG>. Nonetheless, the timing diagram <NUM> may be implemented with different hardware, techniques, schemes, or a combination thereof. Generally, the timing diagram <NUM> indicates example signaling between the IP subsystems <NUM> and the CSR set <NUM> that supports a monitoring-only attribute, in which the application processor <NUM> has read-only operations available, and the IP subsystems <NUM> have read and write operations available.

The clock manager <NUM> can provide the Core_Clk signal <NUM> to the IP block <NUM> to enable communication between the IP subsystems <NUM> and the application processor <NUM>. The clock manager <NUM> can also provide the Core_Derived_Clk signal <NUM> to the CSR set <NUM> and the asynchronous bridge <NUM> to enable communication between the application processor <NUM> and the CSR set <NUM>. The derived clock rate of the Core_Derived_Clk signal <NUM> is four times slower than the clock rate of the Core_Clk signal <NUM>. The Core_Derived_Clk_En signal <NUM> is synchronous with a rising edge of the Core_Derived_Clk signal <NUM>. The Core_Derived_Clk_En_Q signal <NUM> is ninety degrees out-of-phase with the Core_Derived_Clk_En signal <NUM>. The En_Xor signal conveys a true or high output if either, and only one of, the Core_Derived_Clk_En signal <NUM> or the Core_Derived_Clk_En_Q signal <NUM> is high or true.

The Data_Wen signal <NUM> conveys true or high when the HW_Data signal <NUM> conveys a read or write command. The HW_Data signal indicates whether the IP subsystems include a read or write command for the CSR set <NUM>. The Data signal <NUM> conveys the data associated with the read or write commands. The Data_Q signal <NUM> is synchronous with the Core_Derived_Clk_En_Q signal <NUM>. The HW_En signal <NUM> is synchronous with the Data_Q signal <NUM>. The Data_CSR signal <NUM> conveys when the values of the Data signal <NUM> are written to or read from the CSR set <NUM>. In aspects, use of the Core_Derived_Clk signal <NUM> may enable independent monitoring of the CSRs by the application processor <NUM> and read and write operations by the IP subsystems <NUM> of the IP block <NUM> independent of the Core_Clk signal <NUM> or power state of the IP block. The slower clock rate of the Core_Derived_Clk signal <NUM> may also reduce the power dissipation associated with the CSR set <NUM>.

<FIG> illustrates an example diagram <NUM> to enable the described aspects of independent clocking for CSRs for a control and monitoring attribute. In this example, the SoC <NUM> includes similar components and signals to those shown in the SoC of <FIG> with some additional detail. The CSR set <NUM> supports control and monitoring attributes, in which the application processor <NUM> and the IP subsystems <NUM> have read and write operations available.

The diagram <NUM> includes multiplexers <NUM>, <NUM>, and <NUM>, latches <NUM>, <NUM>, <NUM>, and <NUM>, a falling edge detector <NUM>, and an OR logic gate <NUM>. The multiplexer <NUM> is operatively coupled to the multiplexer <NUM> and the OR logic gate <NUM>. The inputs to the multiplexer <NUM> include a Data signal <NUM> and a Data_CSR signal <NUM>. The Data signal <NUM> can convey the data value associated with a read or write command. The selection between the Data signal <NUM> and the Data_CSR signal <NUM> is directed by the output of the OR logic gate <NUM>.

The multiplexer <NUM> is operatively coupled to the latch <NUM> and the multiplexer <NUM>. The inputs to the multiplexer <NUM> include the Data signal <NUM> and the output of the multiplexer <NUM>. The selection between the Data signal <NUM> and the output of the multiplexer <NUM> is directed by a Data_Wen signal <NUM>.

The latch <NUM> is operatively coupled between the multiplexer <NUM> and the multiplexer <NUM>. The latch <NUM> includes inputs of a Clk signal <NUM> (e.g., a core clock signal) and the output of the multiplexer <NUM>. The output of the latch <NUM> is the Data signal <NUM>.

The multiplexer <NUM> is operatively coupled between the latch <NUM> and the latch <NUM>. The inputs to the multiplexer <NUM> include the Data signal <NUM> and a Data_Q signal <NUM>. The selection between the Data signal <NUM> and the Data_Q signal <NUM> is directed by an En_Xor signal <NUM>.

The latch <NUM> is operatively coupled between the multiplexer <NUM> and the latch <NUM>. The latch <NUM> includes inputs of the Clk signal <NUM> and the output of the multiplexer <NUM>. The output of the latch <NUM> is the Data_Q signal <NUM>.

The latch <NUM> is operatively coupled to the latch <NUM> and the multiplexer <NUM>. The latch <NUM> includes inputs of the Data_Q signal <NUM> and a Clk_Div_Value signal <NUM>. The output of the latch <NUM> is the Data_CSR signal <NUM>.

The latch <NUM> is operatively coupled to the falling edge detector <NUM>. The latch <NUM> includes inputs of the Clk signal <NUM> and a SW_Wen signal <NUM>. The output of the latch <NUM> is provided to the falling edge detector <NUM>. The falling edge detector <NUM> is operatively coupled to the OR logic gate <NUM>. Another input to the falling edge detector <NUM> is the SW_Wen signal <NUM>. The output of the falling edge detector <NUM> is an input to the OR logic gate <NUM>. Another input to the OR logic gate <NUM> is a Core_ACG_Wake_Pulse signal <NUM>. In aspects, use of the Clock_Div_Value signal <NUM> may enable independent monitoring of the CSRs by the application processor <NUM> and read and write operations by both the application processor <NUM> and the IP subsystems <NUM> of the IP block <NUM> independent of the core clock signal or power state of the IP block <NUM>.

<FIG> is a flowchart illustrating operations <NUM> of independent clocking for CSRs. The operations <NUM> are described in the context of the integrated circuit <NUM> or the SoC <NUM> of <FIG> or the SoC <NUM> of <FIG>. The operations <NUM> may be performed in a different order or with additional operations.

At <NUM>, a first clock signal is generated by a clock manager. The clock manager is operatively coupled to an asynchronous bridge, an IP block, and a CSR set. The IP block includes one or more IP subsystems and the CSR set associated with the one or more IP subsystems. The asynchronous bridge is operatively coupled between the CSR set and the application processor. For example, the clock manager <NUM> generates the core clock signal <NUM>. The clock manager <NUM> is operatively coupled to the asynchronous bridge <NUM>, the IP block <NUM>, and the CSR set <NUM>. One or more respective clock gate controllers <NUM> may be operatively coupled between the clock manager <NUM> the asynchronous bridge <NUM>, the IP block <NUM>, or the CSR set <NUM> (e.g., the clock gate controllers <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> of <FIG>).

At <NUM>, the first clock signal is provided to the IP block to enable operation of the IP block or core of the IP block, which may include communication between the one or more IP subsystems of the IP block and the application processor. For example, the clock manager <NUM> provides the core clock signal <NUM> to the IP block <NUM>. The core clock signal <NUM> enables communication between the IP subsystems <NUM> and the application processor <NUM>.

At <NUM>, a second clock signal is generated. The second clock signal has a derived clock rate that is an integer division slower or an integer multiplication faster than a clock rate of the first clock signal. The second clock signal is also capable of being selectively gated independent of the first clock signal. The clock manager <NUM> generates the derived clock signal <NUM>. The derived clock signal <NUM> has a derived clock rate that is an integer division slower (e.g., two times slower) than the clock rate of the core clock signal <NUM>. The derived clock rate can also be three, four, five, or six times slower than the clock rate of the core clock signal <NUM>. In other implementations, the derived clock rate can be two, three, four, five, or six times faster than the clock rate of the core clock signal <NUM>. The derived clock signal <NUM> is selectively gated independent of the core clock signal <NUM>. Thus, the second clock signal may enable CSR access while the clock signal to the IP block is gated and/or the IP block is in a state of inactivity. Alternatively, the second clock signal may be gated or disabled when the CSRs are not accessed, enabled CSR-related power savings while the IP block operates to provide its respective functionality to the AP or SoC.

At <NUM>, the second clock signal is provided to the CSR set and the asynchronous bridge to enable communication between the application processor and the CSR set at the derived clock rate. The clock manager <NUM> provides the derived clock signal <NUM> to the CSR set <NUM> and the asynchronous bridge <NUM> to enable communication between the application processor <NUM> and the CSR set <NUM> at the derived clock rate. By using the derived clock rate, the CSRs may operate at a lower frequency and/or while the IP block is inactive, enabling the SoC to conserve power while accessing the CSRs independently from a core clock of the IP block.

<FIG> illustrates an example SoC <NUM> that may implement aspects of independent clocking for CSRs. The SoC <NUM> may be embodied as or within any type of user device <NUM>, user equipment, apparatus, other device, or system as described with reference to <FIG> to implement aspects of the independent clocking for CSRs. Although described with reference to chip-based packaging, the components illustrated in <FIG> may also be embodied as other systems or component configurations, such as an FPGA, ASIC, application-specific standard product (ASSP), digital signal processor (DSP), complex programmable logic device (CPLD), system-in-package (SiP), package-on-package (PoP), processing and communication chip set, communication co-processor, sensor co-processor, or the like.

In this example, the SoC <NUM> includes one or more application processors <NUM> (e.g., processor cores), which process various computer-executable instructions to control the operation of the SoC <NUM> and to enable techniques for the described independent clocking for CSRs (e.g., the CSR set <NUM>). Alternatively or additionally, the SoC <NUM> can be implemented with any one or combination of hardware, firmware, or fixed logic circuitry that is implemented in connection with processing and control circuits (not illustrated in <FIG>). Although not shown, the SoC <NUM> may also include a bus, interconnect, crossbar, or fabric that couples the various components within the system.

The SoC <NUM> also includes a memory <NUM> (e.g., computer-readable storage media), such as one or more memory circuits that enable persistent or non-transitory data storage, and thus do not include transitory signals or carrier waves. Examples of the memory <NUM> include RAM, non-volatile memory (e.g., ROM, EPROM, EEPROM, etc.), or flash memory. The memory <NUM> provides data storage for system data <NUM>, as well as for firmware <NUM>, applications <NUM>, and any other types of information or data related to operational aspects of the SoC <NUM>. For example, the firmware <NUM> can be maintained as processor-executable instructions of an operating system (e.g., real-time OS) within the memory <NUM> and executed on the application processor <NUM>.

The applications <NUM> may include a system manager, such as any form of a control application, software application, signal-processing and control module, code that is native to a particular system, an abstraction module or gesture module and so on. The memory <NUM> may also store system components or utilities for implementing aspects of the described independent clocking for CSRs.

The SoC <NUM> also includes a clock manager <NUM>, clock gate controllers <NUM>, and asynchronous bridges <NUM> implemented in accordance with one or more aspects of independent clocking for CSRs as described herein. Generally, the clock manager <NUM>, clock gate controllers <NUM>, and asynchronous bridges <NUM> are coupled between the application processor <NUM> and functional blocks of the SoC <NUM> to enable independent clocking of respective CSRs of components (e.g., function blocks or IP blocks) of the SoC <NUM>. In this example, the SoC <NUM> also includes a variety of function blocks or processors <NUM> through <NUM>, any of which may be implemented as an IP block with a corresponding IP subsystem to provide a respective described function and a CSR set accessible by the application processor <NUM> as described herein.

As shown in <FIG>, the SoC <NUM> includes communication transceivers <NUM> and a wireless modem <NUM> that enable wired or wireless communication of the system data <NUM> (e.g., received data, data that is being received, data scheduled for broadcast, packetized, or the like). In some aspects, the wireless modem <NUM> is a multi-mode multi-band modem or baseband processor that is configurable to communicate in accordance with various communication protocols or in different frequency bands. The wireless modem <NUM> may include a transceiver interface (not shown) for communicating encoded or modulated signals with transceiver circuitry (e.g., the RF transceiver <NUM>).

The SoC <NUM> can include one or more data inputs <NUM> via which any type of data, media content, or inputs can be received, such as user input, user-selectable inputs (explicit or implicit), or any other type of audio, video, or image data received from a content or data source. Alternatively or additionally, the data inputs <NUM> may include various data interfaces, which can be implemented as any one or more of a serial or parallel interface, a wireless interface, a network interface, and as any other type of communication interface enabling communication with other devices or systems.

The SoC <NUM> also includes additional processors or co-processors (e.g., the IP blocks <NUM> of <FIG>) to enable other functionalities, such as a graphics processor <NUM>, audio processor <NUM>, and image sensor processor <NUM>. The graphics processor <NUM> may render graphical content associated with a user interface, operating system, or applications of the SoC <NUM>. In some cases, the audio processor <NUM> encodes or decodes audio data and signals, such as audio signals and information associated with voice calls or encoded audio data for playback. The image sensor processor <NUM> may be coupled to an image sensor and provide image data processing, video capture, and other visual media conditioning and processing functions. The SoC can also include a sensor interface <NUM>. The sensor interface <NUM> enables the SoC <NUM> to receive data from various sensors, such as capacitance and motion sensors.

Claim 1:
A system-on-chip, SoC (<NUM>) comprising:
an intellectual property, IP block (<NUM>) including at least one IP subsystem (<NUM>), the one IP block (<NUM>) including a configuration and status register, CSR set (<NUM>) associated with the at least one IP subsystem (<NUM>);
an asynchronous bridge (<NUM>) operatively coupled between the CSR set (<NUM>) and an application processor (<NUM>); and
a clock manager (<NUM>) operatively coupled to the asynchronous bridge (<NUM>), the IP block (<NUM>), and the CSR set (<NUM>), the clock manager (<NUM>) configured to:
generate a first clock signal (<NUM>);
provide the first clock signal (<NUM>) to the IP block (<NUM>) to enable communication between the at least one IP subsystem (<NUM>) and the application processor (<NUM>);
generate a second clock signal (<NUM>), the second clock signal (<NUM>) having a derived clock rate that is an integer division slower or an integer multiplication faster than a clock rate of the first clock signal (<NUM>) and capable of being selectively gated independent of the first clock signal (<NUM>); and
provide the second clock signal (<NUM>) to the CSR set (<NUM>) and the asynchronous bridge (<NUM>) to enable communication between the application processor (<NUM>) and the CSR set (<NUM>) at the derived clock rate.