Patent Description:
In semiconductor wafer processing, integrated circuits are formed on a wafer (also referred to as a substrate) composed of silicon or other semiconductor material. In general, layers of various materials which are either semiconducting, conducting or insulating are utilized to form the integrated circuits. These materials are doped, deposited and etched using various well-known processes to form integrated circuits. Each wafer is processed to form a large number of individual regions containing integrated circuits known as dice.

Following the integrated circuit formation process, the wafer is "diced" to separate the individual die from one another for packaging or for use in an unpackaged form within larger circuits. The two main techniques that are used for wafer dicing are scribing and sawing. With scribing, a diamond tipped scribe is moved across the wafer surface along pre-formed scribe lines. These scribe lines extend along the spaces between the dice. These spaces are commonly referred to as "streets. " The diamond scribe forms shallow scratches in the wafer surface along the streets. Upon the application of pressure, such as with a roller, the wafer separates along the scribe lines. The breaks in the wafer follow the crystal lattice structure of the wafer substrate. Scribing can be used for wafers that are about <NUM> mils (thousandths of an inch) or less in thickness. For thicker wafers, sawing is presently the preferred method for dicing.

With sawing, a diamond tipped saw rotating at high revolutions per minute contacts the wafer surface and saws the wafer along the streets. The wafer is mounted on a supporting member such as an adhesive film stretched across a film frame and the saw is repeatedly applied to both the vertical and horizontal streets. One problem with either scribing or sawing is that chips and gouges can form along the severed edges of the dice. In addition, cracks can form and propagate from the edges of the dice into the substrate and render the integrated circuit inoperative. Chipping and cracking are particularly a problem with scribing because only one side of a square or rectangular die can be scribed in the <<NUM>>direction of the crystalline structure. Consequently, cleaving of the other side of the die results in a jagged separation line. Because of chipping and cracking, additional spacing is required between the dice on the wafer to prevent damage to the integrated circuits, e.g., the chips and cracks are maintained at a distance from the actual integrated circuits. As a result of the spacing requirements, not as many dice can be formed on a standard sized wafer and wafer real estate that could otherwise be used for circuitry is wasted. The use of a saw exacerbates the waste of real estate on a semiconductor wafer. The blade of the saw is approximate <NUM> microns thick. As such, to insure that cracking and other damage surrounding the cut made by the saw does not harm the integrated circuits, three to five hundred microns often must separate the circuitry of each of the dice. Furthermore, after cutting, each die requires substantial cleaning to remove particles and other contaminants that result from the sawing process.

Plasma dicing has also been used, but may have limitations as well. For example, one limitation hampering implementation of plasma dicing may be cost. A standard lithography operation for patterning resist may render implementation cost prohibitive. Another limitation possibly hampering implementation of plasma dicing is that plasma processing of commonly encountered metals (e.g., copper) in dicing along streets can create production issues or throughput limits. Document <CIT> describes a method of dicing a semiconductor wafer having a plurality of integrated circuits, that involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

In a first aspect of the present invention, a method of dicing a semiconductor wafer is defined in claim <NUM>, comprising: forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a uniform rotating beam laser scribing process to provide a patterned mask with gaps exposing regions of the semiconductor wafer between the integrated circuits, the uniform rotating laser beam laser scribing process involving passing the laser beam through a rotating telescope or a rotating prism. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

In a second aspect of the present invention, a method of dicing a semiconductor wafer including a plurality of integrated circuits is defined in claim <NUM>, comprising laser scribing the semiconductor wafer with a uniform rotating beam laser scribing process to singulate the integrated circuits, the uniform rotating laser beam laser scribing process involving passing the laser beam through a rotating telescope or a rotating prism.

In a third aspect of the present invention, a system for dicing a semiconductor is defined in claim <NUM>, comprising: a factory interface. The system also includes a laser scribe apparatus coupled with the factory interface and having a laser assembly configured to provide a uniform rotating laser beam. The laser assembly includes a rotatable telescope or a rotating prism. The system also includes a plasma etch chamber coupled with the factory interface.

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon, are described. In the following description, numerous specific details are set forth, such as rotating beam laser scribing approaches and plasma etching conditions and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known aspects, such as integrated circuit fabrication, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

A hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch may be implemented for die singulation. The laser scribe process may be used to cleanly remove a mask layer, organic and inorganic dielectric layers, and device layers. The laser etch process may then be terminated upon exposure of, or partial etch of, the wafer or substrate. The plasma etch portion of the dicing process may then be employed to etch through the bulk of the wafer or substrate, such as through bulk single crystalline silicon, to yield die or chip singulation or dicing. More specifically, one or more embodiments are directed to implementing a uniform rotating beam laser scribing process for, e.g., dicing applications. Such a process can provide a uniform laser profile by rotating a laser beam.

It is to be appreciated that a laser is a critical component for scribing device-patterned silicon (Si) wafers by fabricating grooves for subsequently dicing the wafer with a plasma etching process. Typically, a laser beam has a fundamentally Gaussian profile as a TEM00 mode. Such a beam mode may lead to beam waste since there is often an associated asymmetry of more than <NUM>% in state-of-the-art short-pulse high-power lasers. In accordance with an embodiment of the present disclosure, rotating a delivered laser beam can be implemented to improve an otherwise asymmetric trench profile and improve product quality.

In accordance with one or more embodiments of the present disclosure, an etched profile can be dictated by a laser scribed trench profile. In one embodiment, a laser scribe profile that has increased uniformity can enable achieving singulation uniformity and sidewall smoothness associated with a subsequent plasma etch process. During a laser scribing process, an asymmetric trench profile may be formed on the case of a non-rotating beam. The asymmetric laser scribe profile may adversely affect final product quality for a hybrid dicing process. In an embodiment, a symmetric conic shape is achieved for a laser scribed trench by rotating a laser beam while delivering the laser beam onto a target surface. Embodiments described herein may be implemented to address laser scribed trench uniformity issues by providing an approach based on a precisely controlled mechanical apparatus for rotating a laser beam collimator unit or beam transfer unit, such as prism or mirrors, during a laser scribing process.

Advantages for implementing embodiments described herein may include (<NUM>) the fabrication of a precisely controlled and refined trench profile (in particular, with concentric alignment of laser beam positioning to a wafer, a laser machined profile can be used to generate clean and uniformly straightened lines), (<NUM>) enablement of a flexible configuration (e.g., a rotating tool can be readily installed in a beam path and can be exchangeable with other optics), (<NUM>) the flexibility of an optical configuration can provide for improved laser process productivity and adaptability, and/or (<NUM>) achievement of high product quality by improving a scribed trench profile.

In accordance with one or more embodiments of the present disclosure, a symmetric conic shape of a scribed trench is achieved by rotating a laser beam while delivering the laser beam onto a target surface. Embodiments may include a precisely controlled laser scribed profile generated by a mechanical apparatus for rotating a laser beam collimator unit or beam transfer unit, such as a prism or mirrors. In one embodiment, a precisely controlled apparatus is used to obtain a symmetric and flat (or gently rounded) bottom trench for a laser scribe process. Further, by combining a rotating beam with a variety of control factors, such as laser spot size control, spatial and temporal control between consecutive laser spots, etc., further laser scribe trench profile can be achieved. In addition, surface roughness following a scribing process can be smoothed out by additional cleaning operations, such as described herein. Embodiments described herein may be implemented to advantageously provide for quality and cost-effectiveness by using a mechanical apparatus that rotates a laser beam concentrically.

To provide context, in a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch of a coated wafer, a femtosecond laser may be applied to remove the mask and device layers on the dicing street until the silicon substrate is exposed. A plasma etch follows to separate dies to realize die singulation. Typically, a non-rotated beam is used for the scribing process. However, a non-rotated beam may shows its limitation with the following two different situations: (<NUM>) when a smooth sidewall is needed for a typical narrow kerf width or (<NUM>) when a wide kerf is demanded.

In accordance with one or more embodiments of the present disclosure, a scribing laser beam is rotated for improving laser scribing process in hybrid laser dicing. A laser scribing trench profile can be improved by using a laser beam rotation mechanism. In an embodiment, a laser beam rotation rate is matched with a laser beam repetition rate in a ratio between <NUM> to <NUM> % of the laser beam repetition rate. In other embodiments, a lower repetition rate is matched, e.g., a rate of rotation that is <NUM>% to <NUM>% of the laser speed. In a particular such embodiment for <NUM>% matching, e.g., a rotating beam has a <NUM> repetition rate and <NUM> rotational rate. It is to be appreciated that by applying a rotating beam process, symmetrical (on-axis, or centralized) or asymmetrical (off-axis, or off-center) rotation can be applied to achieve a scribed kerf width variation without changing the optics. In the latter case, off-axis rotation can be used to generate a desired shape to fit for specific applications.

As such, in an aspect of the present disclosure, a combination of a uniform rotating beam laser scribing process with a plasma etching process may be used to dice a semiconductor wafer into singulated integrated circuits. <FIG> is a Flowchart <NUM> representing operations in a method of dicing a semiconductor wafer including a plurality of integrated circuits, in accordance with an embodiment of the present disclosure. <FIG> illustrate cross-sectional views of a semiconductor wafer including a plurality of integrated circuits during performing of a method of dicing the semiconductor wafer, corresponding to operations of Flowchart <NUM>, in accordance with an embodiment of the present disclosure.

Referring to operation <NUM> of Flowchart <NUM>, and corresponding <FIG>, a mask <NUM> is formed above a semiconductor wafer or substrate <NUM>. The mask <NUM> is composed of a layer covering and protecting integrated circuits <NUM> formed on the surface of semiconductor wafer <NUM>. The mask <NUM> also covers intervening streets <NUM> formed between each of the integrated circuits <NUM>.

In accordance with an embodiment of the present disclosure, forming the mask <NUM> includes forming a layer such as, but not limited to, a photo-resist layer or an I-line patterning layer. For example, a polymer layer such as a photo-resist layer may be composed of a material otherwise suitable for use in a lithographic process. In one embodiment, the photo-resist layer is composed of a positive photo-resist material such as, but not limited to, a <NUM> nanometer (nm) resist, a <NUM> resist, a <NUM> resist, an extreme ultra-violet (EUV) resist, or a phenolic resin matrix with a diazonaphthoquinone sensitizer. In another embodiment, the photo-resist layer is composed of a negative photo-resist material such as, but not limited to, poly-cis-isoprene and poly-vinyl-cinnamate.

In another embodiment, forming the mask <NUM> involves forming a layer deposited in a plasma deposition process. For example, in one such embodiment, the mask <NUM> is composed of a plasma deposited Teflon or Teflon-like (polymeric CF<NUM>) layer. In a specific embodiment, the polymeric CF<NUM> layer is deposited in a plasma deposition process involving the gas C<NUM>F<NUM>.

In another embodiment, forming the mask <NUM> involves forming a water-soluble mask layer. In an embodiment, the water-soluble mask layer is readily dissolvable in an aqueous media. For example, in one embodiment, the water-soluble mask layer is composed of a material that is soluble in one or more of an alkaline solution, an acidic solution, or in deionized water. In an embodiment, the water-soluble mask layer maintains its water solubility upon exposure to a heating process, such as heating approximately in the range of <NUM> - <NUM> degrees Celsius. For example, in one embodiment, the water-soluble mask layer is soluble in aqueous solutions following exposure to chamber conditions used in a laser and plasma etch singulation process. In one embodiment, the water-soluble mask layer is composed of a material such as, but not limited to, polyvinyl alcohol, polyacrylic acid, dextran, polymethacrylic acid, polyethylene imine, or polyethylene oxide. In a specific embodiment, the water-soluble mask layer has an etch rate in an aqueous solution approximately in the range of <NUM> - <NUM> microns per minute and, more particularly, approximately <NUM> microns per minute.

In another embodiment, forming the mask <NUM> involves forming a UV-curable mask layer. In an embodiment, the mask layer has a susceptibility to UV light that reduces an adhesiveness of the UV-curable layer by at least approximately <NUM>%. In one such embodiment, the UV layer is composed of polyvinyl chloride or an acrylic-based material. In an embodiment, the UV-curable layer is composed of a material or stack of materials with an adhesive property that weakens upon exposure to UV light. In an embodiment, the UV-curable adhesive film is sensitive to approximately <NUM> UV light. In one such embodiment, this sensitivity enables use of LED light to perform a cure.

In an embodiment, semiconductor wafer or substrate <NUM> is composed of a material suitable to withstand a fabrication process and upon which semiconductor processing layers may suitably be disposed. For example, in one embodiment, semiconductor wafer or substrate <NUM> is composed of a group IV-based material such as, but not limited to, crystalline silicon, germanium or silicon/germanium. In a specific embodiment, providing semiconductor wafer <NUM> includes providing a monocrystalline silicon substrate. In a particular embodiment, the monocrystalline silicon substrate is doped with impurity atoms. In another embodiment, semiconductor wafer or substrate <NUM> is composed of a III-V material such as, e.g., a III-V material substrate used in the fabrication of light emitting diodes (LEDs).

In an embodiment, semiconductor wafer or substrate <NUM> has disposed thereon or therein, as a portion of the integrated circuits <NUM>, an array of semiconductor devices. Examples of such semiconductor devices include, but are not limited to, memory devices or complimentary metal-oxide-semiconductor (CMOS) transistors fabricated in a silicon substrate and encased in a dielectric layer. A plurality of metal interconnects may be formed above the devices or transistors, and in surrounding dielectric layers, and may be used to electrically couple the devices or transistors to form the integrated circuits <NUM>. Materials making up the streets <NUM> may be similar to or the same as those materials used to form the integrated circuits <NUM>. For example, streets <NUM> may be composed of layers of dielectric materials, semiconductor materials, and metallization. In one embodiment, one or more of the streets <NUM> includes test devices similar to the actual devices of the integrated circuits <NUM>.

Referring to operation <NUM> of Flowchart <NUM>, and corresponding <FIG>, the mask <NUM> is patterned with a uniform rotating laser beam laser scribing process to provide a patterned mask <NUM> with gaps <NUM>, exposing regions of the semiconductor wafer or substrate <NUM> between the integrated circuits <NUM>. As such, the laser scribing process is used to remove the material of the streets <NUM> originally formed between the integrated circuits <NUM>. In accordance with an embodiment of the present disclosure, patterning the mask <NUM> with the uniform rotating laser beam laser scribing process includes forming trenches <NUM> partially into the regions of the semiconductor wafer <NUM> between the integrated circuits <NUM>, as depicted in <FIG>.

In a first example, trepanning optics may be implemented to provide a uniformed trench profile. As an exemplary arrangement, <FIG> illustrates generation of a uniform rotating beam with a rotating telescope, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, an input beam <NUM> is input into a telescope <NUM>. Telescope <NUM> includes a first optical element <NUM> and a second optical element <NUM>. Telescope <NUM> is rotated <NUM> to provide a rotated beam <NUM>'. Rotated beam <NUM>' can be directed through a lens <NUM>.

In a second example, rotation of a prism can be generated to provide a beam rotated about a spinning axis of a prism at a prism exit. As an exemplary arrangement, <FIG> illustrates generation of a uniform rotating beam with a rotating prism, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, an input beam <NUM> is input into a prism <NUM>. Prism <NUM> is rotated <NUM> to provide a rotated beam <NUM>'. Rotated beam <NUM>' can be directed through a lens <NUM>. Trepanning (beam rotation) can be implemented to assist in overcoming pulse to pulse angular instability typically associated with a non-rotating beam. As a result, a laser scribing trench profile can be improved. As a comparative example, <FIG> illustrate a comparison of an uncontrolled laser process and a controlled rotating beam laser scribing process, respectively, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, an uncontrolled laser process without a rotating beam involves formation of a scribe line <NUM> composed of individual pulses <NUM>. By contrast, referring to <FIG>, a controlled laser process involves rotating a laser beam for form a scribe line <NUM> composed of individual pulses <NUM>.

In an embodiment, a femtosecond-based laser is used as a source for a uniform rotating laser beam laser scribing process. For example, in an embodiment, a laser with a wavelength in the visible spectrum plus the ultra-violet (UV) and infra-red (IR) ranges (totaling a broadband optical spectrum) is used to provide a femtosecond-based laser pulse, which has a pulse width on the order of the femtosecond (<NUM> - <NUM> seconds). In one embodiment, ablation is not, or is essentially not, wavelength dependent and is thus suitable for complex films such as films of the mask <NUM>, the streets <NUM> and, possibly, a portion of the semiconductor wafer or substrate <NUM>.

<FIG> illustrates the effects of using a laser pulse width in the femtosecond range, picosecond range, and nanosecond range, in accordance with an embodiment of the present disclosure. Referring to <FIG>, by using a laser beam in the femtosecond range, heat damage issues are mitigated or eliminated (e.g., minimal to no damage 602C with femtosecond processing of a via 600C) versus longer pulse widths (e.g., significant damage 602A with nanosecond processing of a via 600A). The elimination or mitigation of damage during formation of via 600C may be due to a lack of low energy recoupling (as is seen for picosecond-based laser ablation of 600B/602B) or thermal equilibrium (as is seen for nanosecond-based laser ablation), as depicted in <FIG>. Laser parameters selection, such as beam profile, may be critical to developing a successful laser scribing and dicing process that minimizes chipping, microcracks and delamination in order to achieve clean laser scribe cuts. The cleaner the laser scribe cut, the smoother an etch process that may be performed for ultimate die singulation. In semiconductor device wafers, many functional layers of different material types (e.g., conductors, insulators, semiconductors) and thicknesses are typically disposed thereon. Such materials may include, but are not limited to, organic materials such as polymers, metals, or inorganic dielectrics such as silicon dioxide and silicon nitride.

A street between individual integrated circuits disposed on a wafer or substrate may include the similar or same layers as the integrated circuits themselves. For example, <FIG> illustrates a cross-sectional view of a stack of materials that may be used in a street region of a semiconductor wafer or substrate, in accordance with an embodiment of the present disclosure. Referring to <FIG>, a street region <NUM> includes the top portion <NUM> of a silicon substrate, a first silicon dioxide layer <NUM>, a first etch stop layer <NUM>, a first low K dielectric layer <NUM> (e.g., having a dielectric constant of less than the dielectric constant of <NUM> for silicon dioxide), a second etch stop layer <NUM>, a second low K dielectric layer <NUM>, a third etch stop layer <NUM>, an undoped silica glass (USG) layer <NUM>, a second silicon dioxide layer <NUM>, and a layer of photo-resist <NUM>, with relative thicknesses depicted. Copper metallization <NUM> is disposed between the first and third etch stop layers <NUM> and <NUM> and through the second etch stop layer <NUM>. In a specific embodiment, the first, second and third etch stop layers <NUM>, <NUM> and <NUM> are composed of silicon nitride, while low K dielectric layers <NUM> and <NUM> are composed of a carbon-doped silicon oxide material.

Under conventional laser irradiation (such as nanosecond-based irradiation), the materials of street <NUM> behave quite differently in terms of optical absorption and ablation mechanisms. For example, dielectrics layers such as silicon dioxide, is essentially transparent to all commercially available laser wavelengths under normal conditions. By contrast, metals, organics (e.g., low K materials) and silicon can couple photons very easily, particularly in response to nanosecond-based irradiation. In an embodiment, a uniform rotating laser beam laser scribing process is used to pattern a layer of silicon dioxide, a layer of low K material, and a layer of copper by ablating the layer of silicon dioxide prior to ablating the layer of low K material and the layer of copper. In case that the uniform rotating laser beam is a femtosecond-based laser beam, in an embodiment, suitable femtosecond-based laser processes are characterized by a high peak intensity (irradiance) that usually leads to nonlinear interactions in various materials. In one such embodiment, the femtosecond laser sources have a pulse width approximately in the range of <NUM> femtoseconds to <NUM> femtoseconds, although preferably in the range of <NUM> femtoseconds to <NUM> femtoseconds. In one embodiment, the femtosecond laser sources have a wavelength approximately in the range of <NUM> nanometers to <NUM> nanometers, although preferably in the range of <NUM> nanometers to <NUM> nanometers. In one embodiment, the laser and corresponding optical system provide a focal spot at the work surface approximately in the range of <NUM> microns to <NUM> microns, though preferably approximately in the range of <NUM> microns to <NUM> microns or between <NUM> - <NUM> microns.

In an embodiment, the laser source has a pulse repetition rate approximately in the range of <NUM> to <NUM>, although preferably approximately in the range of <NUM> to <NUM>. In an embodiment, the laser source delivers pulse energy at the work surface approximately in the range of <NUM> uJ to <NUM> uJ, although preferably approximately in the range of 1uJ to 5uJ. In an embodiment, the laser scribing process runs along a work piece surface at a speed approximately in the range of <NUM>/sec to <NUM>/sec, although preferably approximately in the range of <NUM>/sec to <NUM>/sec.

The scribing process may be run in single pass only, or in multiple passes, but, in an embodiment, preferably <NUM>-<NUM> passes. In one embodiment, the scribing depth in the work piece is approximately in the range of <NUM> microns to <NUM> microns deep, preferably approximately in the range of <NUM> microns to <NUM> microns deep. In an embodiment, the kerf width of the laser beam generated is approximately in the range of <NUM> microns to <NUM> microns, although in silicon wafer scribing/dicing preferably approximately in the range of <NUM> microns to <NUM> microns, measured at the device/silicon interface.

Laser parameters may be selected with benefits and advantages such as providing sufficiently high laser intensity to achieve ionization of inorganic dielectrics (e.g., silicon dioxide) and to minimize delamination and chipping caused by underlayer damage prior to direct ablation of inorganic dielectrics. Also, parameters may be selected to provide meaningful process throughput for industrial applications with precisely controlled ablation width (e.g., kerf width) and depth. In an embodiment, a uniform rotating laser beam laser scribing process is suitable to provide such advantages.

It is to be appreciated that the dicing or singulation process could be stopped after the above described laser scribing in a case that the laser scribing is used to pattern the mask as well as to scribe fully through the wafer or substrate in order to singulate the dies. Accordingly, further singulation processing would not be required in such a case. However, the following embodiments may be considered in cases where laser scribing alone is not implemented for total singulation.

Referring now to optional operation <NUM> of Flowchart <NUM>, an intermediate post mask-opening cleaning operation is performed. In an embodiment, the post mask-opening cleaning operation is a plasma-based cleaning process. In a first example, as described below, the plasma-based cleaning process is reactive to the regions of the substrate <NUM> exposed by the gaps <NUM>. In the case of a reactive plasma-based cleaning process, the cleaning process itself may form or extend trenches <NUM> in the substrate <NUM> since the reactive plasma-based cleaning operation is at least somewhat of an etchant for the substrate <NUM>. In a second, different, example, as is also described below, the plasma-based cleaning process is non-reactive to the regions of the substrate <NUM> exposed by the gaps <NUM>.

In accordance with a first embodiment, the plasma-based cleaning process is reactive to exposed regions of the substrate <NUM> in that the exposed regions are partially etched during the cleaning process. In one such embodiment, Ar or another non-reactive gas (or the mix) is combined with SF<NUM> for a highly-biased plasma treatment for cleaning of scribed openings. The plasma treatment using mixed gases Ar +SF<NUM> under high-bias power is performed for bombarding mask-opened regions to achieve cleaning of the mask-opened regions. In the reactive breakthrough process, both physical bombardment from Ar and SF<NUM> along with chemical etching due to SF<NUM> and F-ions contribute to cleaning of mask-opened regions. The approach may be suitable for photoresist or plasma-deposited Teflon masks <NUM>, where breakthrough treatment leads to fairly uniform mask thickness reduction and a gentle Si etch. Such a breakthrough etch process, however, may not be best suited for water soluble mask materials.

In accordance with a second embodiment, the plasma-based cleaning process is non-reactive to exposed regions of the substrate <NUM> in that the exposed regions are not or only negligible etched during the cleaning process. In one such embodiment, only non-reactive gas plasma cleaning is used. For example, Ar or another non-reactive gas (or the mix) is used to perform a highly-biased plasma treatment both for mask condensation and cleaning of scribed openings. The approach may be suitable for water-soluble masks or for thinner plasma-deposited Teflon <NUM>. In another such embodiment, separate mask condensation and scribed trench cleaning operations are used, e.g., an Ar or non-reactive gas (or the mix) highly-biased plasma treatment for mask condensation is first performed, and then an Ar +SF<NUM> plasma cleaning of a laser scribed trench is performed. This embodiment may be suitable for cases where Ar-cleaning is not sufficient for trench cleaning due to too thick of a mask material. Cleaning efficiency is improved for thinner masks, but mask etch rate is much lower, with almost no consumption in a subsequent deep silicon etch process. In yet another such embodiment, three-operation cleaning is performed: (a) Ar or non-reactive gas (or the mix) highly-biased plasma treatment for mask condensation, (b) Ar +SF<NUM> highly-biased plasma cleaning of laser scribed trenches, and (c) Ar or non-reactive gas (or the mix) highly-biased plasma treatment for mask condensation. In accordance with another embodiment of the present disclosure, a plasma cleaning operation involves first use of a reactive plasma cleaning treatment, such as described above in the first aspect of operation <NUM>. The reactive plasma cleaning treatment is then followed by a non-reactive plasma cleaning treatment such as described in association with the second aspect of operation <NUM>.

Referring to operation <NUM> of Flowchart <NUM>, and corresponding <FIG>, the semiconductor wafer <NUM> is etched through the gaps <NUM> in the patterned mask <NUM> to singulate the integrated circuits <NUM>. In accordance with an embodiment of the present disclosure, etching the semiconductor wafer <NUM> includes ultimately etching entirely through semiconductor wafer <NUM>, as depicted in <FIG>, by etching the trenches <NUM> initially formed with the uniform rotating laser beam laser scribing process.

In an embodiment, patterning the mask with the laser scribing process involves forming trenches in the regions of the semiconductor wafer between the integrated circuits, and plasma etching the semiconductor wafer involves extending the trenches to form corresponding trench extensions. In one such embodiment, each of the trenches has a width, and each of the corresponding trench extensions has the width.

In accordance with an embodiment of the present disclosure, the resulting roughness of mask opening from laser scribing can impact die sidewall quality resulting from the subsequent formation of a plasma etched trench. Lithographically opened masks often have smooth profiles, leading to smooth corresponding sidewalls of a plasma etched trench. By contrast, a conventional laser opened mask can have a very rough profile along a scribing direction if improper laser process parameters are selected (such as spot overlap, leading to rough sidewall of plasma etched trench horizontally). Although the surface roughness can be smoothened by additional plasma processes, there is a cost and throughput hit to remedying such issues. Accordingly, embodiments described herein may be advantageous in providing a smoother scribing process from the laser scribing portion of the singulation process.

In an embodiment, etching the semiconductor wafer <NUM> includes using a plasma etching process. In one embodiment, a through-silicon via type etch process is used. For example, in a specific embodiment, the etch rate of the material of semiconductor wafer <NUM> is greater than <NUM> microns per minute. An ultra-high-density plasma source may be used for the plasma etching portion of the die singulation process. An example of a process chamber suitable to perform such a plasma etch process is the Applied Centura® Silvia™ Etch system available from Applied Materials of Sunnyvale, CA, USA. The Applied Centura® Silvia™ Etch system combines the capacitive and inductive RF coupling which gives much more independent control of the ion density and ion energy than was possible with the capacitive coupling only, even with the improvements provided by magnetic enhancement. This combination enables effective decoupling of the ion density from ion energy, so as to achieve relatively high density plasmas without the high, potentially damaging, DC bias levels, even at very low pressures. This results in an exceptionally wide process window. However, any plasma etch chamber capable of etching silicon may be used. In an exemplary embodiment, a deep silicon etch is used to etch a single crystalline silicon substrate or wafer <NUM> at an etch rate greater than approximately <NUM>% of conventional silicon etch rates while maintaining essentially precise profile control and virtually scallop-free sidewalls. In a specific embodiment, a through-silicon via type etch process is used. The etch process is based on a plasma generated from a reactive gas, which generally a fluorine-based gas such as SF<NUM>, C<NUM> F<NUM>, CHF<NUM>, XeF<NUM>, or any other reactant gas capable of etching silicon at a relatively fast etch rate. In an embodiment, the mask layer <NUM> is removed after the singulation process, as depicted in <FIG>. In another embodiment, the plasma etching operation described in association with <FIG> employs a conventional Bosch-type dep/etch/dep process to etch through the substrate <NUM>. Generally, a Bosch-type process consists of three sub-operations: deposition, a directional bombardment etch, and isotropic chemical etch which is run through many iterations (cycles) until silicon is etched through.

Accordingly, referring again to Flowchart <NUM> and <FIG>, wafer dicing may be preformed by initial ablation using a uniform rotating laser beam laser scribing process to ablate through a mask layer, through wafer streets (including metallization), and partially into a silicon substrate. Die singulation may then be completed by subsequent through-silicon deep plasma etching. A specific example of a materials stack for dicing is described below in association with <FIG>, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a materials stack for hybrid laser ablation and plasma etch dicing includes a mask layer <NUM>, a device layer <NUM>, and a substrate <NUM>. The mask layer, device layer, and substrate are disposed above a die attach film <NUM> which is affixed to a backing tape <NUM>. In an embodiment, the mask layer <NUM> is a water soluble layer such as the water soluble layers described above in association with mask <NUM>. The device layer <NUM> includes an inorganic dielectric layer (such as silicon dioxide) disposed above one or more metal layers (such as copper layers) and one or more low K dielectric layers (such as carbon-doped oxide layers). The device layer <NUM> also includes streets arranged between integrated circuits, the streets including the same or similar layers to the integrated circuits. The substrate <NUM> is a bulk single-crystalline silicon substrate.

In an embodiment, the bulk single-crystalline silicon substrate <NUM> is thinned from the backside prior to being affixed to the die attach film <NUM>. The thinning may be performed by a backside grind process. In one embodiment, the bulk single-crystalline silicon substrate <NUM> is thinned to a thickness approximately in the range of <NUM> - <NUM> microns. It is important to note that, in an embodiment, the thinning is performed prior to a laser ablation and plasma etch dicing process. In an embodiment, the photo-resist layer <NUM> has a thickness of approximately <NUM> microns and the device layer <NUM> has a thickness approximately in the range of <NUM> - <NUM> microns. In an embodiment, the die attach film <NUM> (or any suitable substitute capable of bonding a thinned or thin wafer or substrate to the backing tape <NUM>) has a thickness of approximately <NUM> microns.

Referring to <FIG>, the mask <NUM>, the device layer <NUM> and a portion of the substrate <NUM> are patterned with a uniform rotating laser beam laser scribing process <NUM> to form trenches <NUM> in the substrate <NUM>. Referring to <FIG>, a through-silicon deep plasma etch process <NUM> is used to extend the trench <NUM> down to the die attach film <NUM>, exposing the top portion of the die attach film <NUM> and singulating the silicon substrate <NUM>. The device layer <NUM> is protected by the mask layer <NUM> during the through-silicon deep plasma etch process <NUM>.

Referring to <FIG>, the singulation process may further include patterning the die attach film <NUM>, exposing the top portion of the backing tape <NUM> and singulating the die attach film <NUM>. In an embodiment, the die attach film is singulated by a laser process or by an etch process. Further embodiments may include subsequently removing the singulated portions of substrate <NUM> (e.g., as individual integrated circuits) from the backing tape <NUM>. In one embodiment, the singulated die attach film <NUM> is retained on the back sides of the singulated portions of substrate <NUM>. Other embodiments may include removing the mask layer <NUM> from the device layer <NUM>. In an alternative embodiment, in the case that substrate <NUM> is thinner than approximately <NUM> microns, the uniform rotating laser beam laser scribing process <NUM> is used to completely singulate substrate <NUM> without the use of an additional plasma process.

A single process tool may be configured to perform many or all of the operations in a hybrid uniform rotating laser beam ablation and plasma etch singulation process. For example, <FIG> illustrates a block diagram of a tool layout for laser and plasma dicing of wafers or substrates, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a process tool <NUM> includes a factory interface <NUM> (FI) having a plurality of load locks <NUM> coupled therewith. A cluster tool <NUM> is coupled with the factory interface <NUM>. The cluster tool <NUM> includes one or more plasma etch chambers, such as plasma etch chamber <NUM>. A laser scribe apparatus <NUM> is also coupled to the factory interface <NUM>. The overall footprint of the process tool <NUM> may be, in one embodiment, approximately <NUM> millimeters (<NUM> meters) by approximately <NUM> millimeters (<NUM> meters), as depicted in <FIG>.

In an embodiment, the laser scribe apparatus <NUM> houses a laser assembly configured to provide a uniform rotating laser beam. In one such embodiment, the laser assembly includes a rotatable telescope, such as described in association with <FIG>. In another such embodiment, the laser assembly includes a rotatable prism, such as described in association with <FIG>. In an embodiment, the laser assembly is configured to rotate a laser beam around an on-axis of an input laser beam. In another embodiment, the laser assembly is configured to rotate a laser beam around an off-axis of an input laser beam. In either case, in a particular embodiment, the laser beam is a femto-second based laser beam.

In an embodiment, the laser is suitable for performing a laser ablation portion of a hybrid laser and etch singulation process, such as the laser ablation processes described above. In one embodiment, a moveable stage is also included in laser scribe apparatus <NUM>, the moveable stage configured for moving a wafer or substrate (or a carrier thereof) relative to the laser. In a specific embodiment, the laser is also moveable. The overall footprint of the laser scribe apparatus <NUM> may be, in one embodiment, approximately <NUM> millimeters by approximately <NUM> millimeters, as depicted in <FIG>.

In an embodiment, the one or more plasma etch chambers <NUM> is configured for etching a wafer or substrate through the gaps in a patterned mask to singulate a plurality of integrated circuits. In one such embodiment, the one or more plasma etch chambers <NUM> is configured to perform a deep silicon etch process. In a specific embodiment, the one or more plasma etch chambers <NUM> is an Applied Centura® Silvia™ Etch system, available from Applied Materials of Sunnyvale, CA, USA. The etch chamber may be specifically designed for a deep silicon etch used to create singulate integrated circuits housed on or in single crystalline silicon substrates or wafers. In an embodiment, a high-density plasma source is included in the plasma etch chamber <NUM> to facilitate high silicon etch rates. In an embodiment, more than one etch chamber is included in the cluster tool <NUM> portion of process tool <NUM> to enable high manufacturing throughput of the singulation or dicing process.

The factory interface <NUM> may be a suitable atmospheric port to interface between an outside manufacturing facility with laser scribe apparatus <NUM> and cluster tool <NUM>. The factory interface <NUM> may include robots with arms or blades for transferring wafers (or carriers thereof) from storage units (such as front opening unified pods) into either cluster tool <NUM> or laser scribe apparatus <NUM>, or both.

Cluster tool <NUM> may include other chambers suitable for performing functions in a method of singulation. For example, in one embodiment, in place of an additional etch chamber, a deposition chamber <NUM> is included. The deposition chamber <NUM> may be configured for mask deposition on or above a device layer of a wafer or substrate prior to laser scribing of the wafer or substrate. In one such embodiment, the deposition chamber <NUM> is suitable for depositing a photo-resist layer. In another embodiment, in place of an additional etch chamber, a wet/dry station <NUM> is included. The wet/dry station may be suitable for cleaning residues and fragments, or for removing a mask, subsequent to a laser scribe and plasma etch singulation process of a substrate or wafer. In yet another embodiment, in place of an additional deep silicon etch chamber, a plasma etch chamber is included and is configured for performing a plasma-based cleaning process. In an embodiment, a metrology station is also included as a component of process tool <NUM>.

Embodiments of the present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to embodiments of the present disclosure. In one embodiment, the computer system is coupled with process tool <NUM> described in association with <FIG>. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), etc..

<FIG> illustrates a diagrammatic representation of a machine in the exemplary form of a computer system <NUM> within which a set of instructions, for causing the machine to perform any one or more of the methodologies described herein, may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a Local Area Network (LAN), an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies described herein.

The exemplary computer system <NUM> includes a processor <NUM>, a main memory <NUM> (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory <NUM> (e.g., flash memory, static random access memory (SRAM), MRAM, etc.), and a secondary memory <NUM> (e.g., a data storage device), which communicate with each other via a bus <NUM>. Processor <NUM> represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processor <NUM> may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processor <NUM> may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. Processor <NUM> is configured to execute the processing logic <NUM> for performing the operations described herein. The computer system <NUM> may further include a network interface device <NUM>. The computer system <NUM> also may include a video display unit <NUM> (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device <NUM> (e.g., a keyboard), a cursor control device <NUM> (e.g., a mouse), and a signal generation device <NUM> (e.g., a speaker).

The secondary memory <NUM> may include a machine-accessible storage medium (or more specifically a computer-readable storage medium) <NUM> on which is stored one or more sets of instructions (e.g., software <NUM>) embodying any one or more of the methodologies or functions described herein. The software <NUM> may also reside, completely or at least partially, within the main memory <NUM> and/or within the processor <NUM> during execution thereof by the computer system <NUM>, the main memory <NUM> and the processor <NUM> also constituting machine-readable storage media. The software <NUM> may further be transmitted or received over a network <NUM> via the network interface device <NUM>.

While the machine-accessible storage medium <NUM> is shown in an exemplary embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

In accordance with an embodiment of the present disclosure, a machine-accessible storage medium has instructions stored thereon which cause a data processing system to perform a method of dicing a semiconductor wafer having a plurality of integrated circuits. The method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a uniform rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Claim 1:
A method of dicing a semiconductor wafer (<NUM>) comprising a plurality of integrated circuits (<NUM>), the method comprising:
forming a mask (<NUM>) above the semiconductor wafer (<NUM>), the mask comprising a layer covering and protecting the integrated circuits (<NUM>);
patterning the mask with a uniform rotating laser beam laser scribing process to provide a patterned mask (<NUM>) with gaps (<NUM>) exposing regions of the semiconductor wafer (<NUM>) between the integrated circuits (<NUM>), the uniform rotating laser beam laser scribing process comprising passing the laser beam through a rotating telescope (<NUM>) or a rotating prism (<NUM>); and
plasma etching the semiconductor wafer (<NUM>) through the gaps (<NUM>) in the patterned mask (<NUM>) to singulate the integrated circuits.