Patent Description:
High breakdown voltage and high electron mobility has made GaN an ideal candidate for high-power transistor applications. Furthermore, the large bandgap of GaN means that the performance of GaN transistors may be maintained at much higher temperatures than other conventional semiconductor options. Applications include, but are not limited to, microwave radio-frequency amplifiers, high voltage switching devices, and power supplies. One mass market application is the microwave source from microwave ovens (to replace magnetrons).

Despite their potential for ubiquitous use in consumer electronics, GaN based devices still suffer from several limitations as a result of the high-voltage environments they are used in. Device layers in GaN transistors may build up charge during use, resulting in changing device performance due to electric field redistribution, and thermal stressing. In the worst case, HFET devices may critically fail due to dielectric breakdown or cracking of device layers. <CIT> describes high-electron-mobility transistors that include field plates. In a first implementation, a HEMT includes a first and a second semiconductor material disposed to form a heterojunction at which a two-dimensional electron gas arises and source, a drain, and gate electrodes. The gate electrode is disposed to regulate conduction in the heterojunction between the source electrode and the drain electrode. The gate has a drain-side edge. A gate-connected field plate is disposed above a drain-side edge of the gate electrode and extends laterally toward the drain. A second field plate is disposed above a drain-side edge of the gate-connected field plate and extends laterally toward the drain. <CIT> describes a semiconductor device that includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress. <CIT> describes electrode configurations for semiconductor devices. <CIT> describes a micro-heater and airflow sensor that uses a micro-heater. The present application is directed to a HFET according to claim <NUM>, and to a corresponding method according to claim <NUM>. The preferred embodiments are found in the dependent claims.

Non-limiting and non-exhaustive examples of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Corresponding reference characters indicate corresponding components throughout the several views of the drawings. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.

Examples of an apparatus and method for a protective insulator for high-voltage field effect transistors (HFETs) are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize; however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "one example" or "one embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

Throughout this specification, several terms of art are used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise. It should be noted that element names and symbols may be used interchangeably through this document (e.g., Si vs. silicon); however, both have identical meaning.

<FIG> is a cross-sectional view of an example HFET <NUM> with a composite passivation layer <NUM>. HFET <NUM> includes first semiconductor material <NUM>, second semiconductor material <NUM>, and heterojunction <NUM>. Gate dielectric <NUM> is disposed on second semiconductor material <NUM>. Heterojunction <NUM> is disposed between first semiconductor material <NUM> and second semiconductor material <NUM>. When the device is turned on, a two-dimensional electron gas <NUM> arises at heterojunction <NUM>, due to the material properties of semiconductor materials <NUM>, <NUM>.

Plurality of composite passivation layers <NUM> is disposed above second semiconductor material <NUM>. A first composite passivation layer is disposed in plurality of composite passivation layers <NUM>, and the first composite passivation layer includes first insulation layer <NUM> and first passivation layer <NUM>. Plurality of composite passivation layers <NUM> also includes a second composite passivation layer with second insulation layer <NUM> and second passivation layer <NUM>, where second passivation layer <NUM> is disposed between first insulation layer <NUM> and second insulation layer <NUM>. In one example, gate dielectric <NUM> and first insulation layer <NUM> include the same material composition. In another or the same example, first passivation layer <NUM> and second passivation layer <NUM> include SiN, and gate dielectric <NUM> and first insulation layer <NUM> include a metal oxide. In the depicted example, gate dielectric <NUM> is disposed between first passivation layer <NUM> and second semiconductor material <NUM>, and gate electrode <NUM> is disposed between gate dielectric <NUM> and first passivation layer <NUM>. The selective biasing of gate electrode <NUM> regulates the conductivity between source electrode <NUM> and drain electrode <NUM>. First gate field plate <NUM> is disposed between first passivation layer <NUM> and second passivation layer <NUM>. In one example, first gate field plate <NUM> is coupled to the gate electrode <NUM>. Source electrode <NUM> and drain electrode <NUM> are coupled to second semiconductor material <NUM>, and source field plate <NUM> is coupled to source electrode <NUM>. In one example, drain electrode <NUM> extends from second semiconductor material <NUM> through at least one of the composite passivation layers in plurality of composite passivation layers <NUM>.

In the illustrated example, gate electrode <NUM>, first gate field plate <NUM>, and source field plate <NUM> have generally rectangular cross-sections. Gate electrode <NUM> includes a first edge <NUM>. First edge <NUM> is disposed a lateral distance d0 from the source electrode <NUM> and a vertical distance d5 above second semiconductor material <NUM>. First edge <NUM> is vertically separated from second semiconductor material <NUM> by gate dielectric <NUM> and first passivation layer <NUM>.

In one example, the HFET includes third passivation layer <NUM>. Second insulation layer <NUM> is disposed between second passivation layer <NUM> and third passivation layer <NUM>. In another or the same example, source field plate <NUM> may be disposed between second insulation layer <NUM> and third passivation layer <NUM>. Furthermore, first gate field plate <NUM> may be disposed between first insulation layer <NUM> and second passivation layer <NUM>.

First gate field plate <NUM> includes second edge <NUM>. Second edge <NUM> is disposed a lateral distance d0+d1 towards drain electrode <NUM> and a vertical distance d5+d6 above second semiconductor material <NUM>. Second edge <NUM> is vertically separated from second semiconductor material <NUM> by gate dielectric <NUM>, first passivation layer <NUM>, and first insulation layer <NUM>. Source field plate <NUM> includes a third edge <NUM>. Third edge <NUM> is disposed a lateral distance d0+d1+d3 towards drain electrode <NUM> from a side of source electrode <NUM>, and a vertical distance d5+d6+d7 above second semiconductor material <NUM>. Third edge <NUM> is vertically separated from second semiconductor material <NUM> by gate dielectric <NUM>, first passivation layer <NUM>, first insulation layer <NUM>, second passivation layer <NUM>, and second insulation layer <NUM>. It should be noted that electric fields between each of gate electrode <NUM>, first gate field plate <NUM>, source field plate <NUM>, and heterojunction <NUM> are highest at their respective edges <NUM>, <NUM>, <NUM> under certain bias conditions.

Gate electrode <NUM> can be electrically connected to first gate field plate <NUM> in a variety of ways. In the illustrated example, the connection between gate electrode <NUM> and first gate field plate <NUM> is outside of the cross-sectional view. However, gate electrode <NUM> and first gate field plate <NUM> can be formed by a unitary member having a generally L-shaped cross-section.

Source electrode <NUM> can be electrically connected to source field plate <NUM> in a variety of ways. In the illustrated example, source electrode <NUM> is electrically connected to source field plate <NUM> by a source via member <NUM>. In other examples, source electrode <NUM> can be electrically connected to source field plate <NUM> outside of the illustrated cross-section.

In the depicted example, drain electrode <NUM> is electrically connected to a pair of drain via members <NUM>, <NUM>. Drain via members <NUM>, <NUM> extend through second passivation layer <NUM> to a same vertical level as source field plate <NUM>, thus acting as extensions of drain electrode <NUM>. Via member <NUM>, by virtue of being on the same vertical level as source field plate <NUM>, is the nearest extension of drain electrode <NUM> to source field plate <NUM>. The side of source field plate <NUM> that includes a third edge <NUM> is disposed a lateral distance d4 away from the drain via member <NUM> at the same vertical level. In some examples, lateral distance d4 is no greater than that needed to maintain a device-specific lateral dielectric breakdown voltage. In the illustrated example, source field plate <NUM> and drain via member <NUM> are covered by a third passivation layer <NUM>.

In the illustrated example, source electrode <NUM> and drain electrode <NUM> may both rest directly on an upper surface of second semiconductor material <NUM> to make electrical contact with second semiconductor material <NUM>. However, in some examples, source electrode <NUM> and/or drain electrode <NUM> penetrate into second semiconductor material <NUM>. In some examples, this penetration is deep enough that source electrode <NUM> and/or drain electrode <NUM> contact or even pass through heterojunction <NUM>. In another or the same example, one or more interstitial glue metals or other conductive materials are disposed between source electrode <NUM> and/or drain electrode <NUM> and one or both of semiconductor materials <NUM>, <NUM>.

In the depicted example, gate electrode <NUM> is electrically insulated from second semiconductor material <NUM> by a single electrically-insulating layer (gate dielectric <NUM>) having a uniform thickness d5. However, in other examples not depicted, a multi-layer can be used to insulate gate electrode <NUM> from second semiconductor material <NUM>. In another example, a single or multi-layer having a non-uniform thickness can be used to insulate gate electrode <NUM> from second semiconductor material <NUM>.

It is worth noting that the various features of lateral-channel HFET <NUM> can be made from a variety of different materials. For example, first semiconductor material <NUM> may include GaN, InN, AlN, AlGaN, InGaN, AlInGaN. In some examples, first semiconductor material <NUM> can also include compound semiconductors containing arsenic such as, for example, GaAs, InAs, AlAs, InGaAs, AlGaAs, InAlGaAs. Second semiconductor material <NUM> can be, for example, AlGaN, GaN, InN, AlN, InGaN, AlInGaN. Second semiconductor material <NUM> can also include compound semiconductors containing arsenic such as one or more of GaAs, InAs, AlAs, InGaAs, AlGaAs, InAlGaAs. The compositions of first and second semiconductor materials <NUM>, <NUM>-which also can be referred to as "active layers"-are tailored such that a two-dimensional electron gas <NUM> forms at heterojunction <NUM>. For example, the compositions of first and second semiconductor materials <NUM>, <NUM> can be tailored such that a sheet carrier density of <NUM><NUM> to <NUM><NUM> cm-<NUM> arises at heterojunction <NUM> (more specifically, a sheet carrier density of <NUM> x <NUM><NUM> to <NUM> x <NUM><NUM> cm-<NUM> or <NUM> x <NUM><NUM> to <NUM> x <NUM><NUM> cm-<NUM> may arise at heterojunction <NUM>). Semiconductor materials <NUM>, <NUM> can be formed above a substrate. In one example the substrate may include gallium nitride, gallium arsenide, silicon carbide, sapphire, silicon, or the like. First semiconductor material <NUM> can either be in direct contact with such a substrate or one or more intervening layers may be present.

Source electrode <NUM>, drain electrode <NUM>, and gate electrode <NUM> can be made from various electrical conductors including, for example, metals such as Al, Ni, Ti, TiW, TiN, TiAu, TiAlMoAu, TiAlNiAu, TiAlPtAu, or the like. Insulating layers, <NUM>, <NUM>, and gate dielectric <NUM> can be made from various dielectrics suitable for forming a gate insulator (e.g., aluminum oxide (Al<NUM>O<NUM>), zirconium dioxide (ZrO<NUM>), aluminum nitride (AlN), hafnium oxide (HfO<NUM>), silicon dioxide (SiO<NUM>), silicon nitride (Si<NUM>N<NUM>), aluminum silicon nitride (AlSiN), or other suitable gate dielectric materials).

Passivation layers <NUM>, <NUM>, <NUM> can be made from various dielectrics including, silicon nitride, silicon oxide, silicon oxynitride, or the like. The composite passivation layers may mitigate or prevent charging of surface states in underlying second semiconductor material <NUM> or layers <NUM>, <NUM>, <NUM>.

In some examples passivation layers <NUM>, <NUM>, <NUM> have a composition such that-after extended operation at steady state operational parameters-the number of charge defects per area in passivation layers <NUM>, <NUM>, <NUM> is less than the sheet carrier density at the heterojunction. In other words, the sum of the products of each three-dimensional defect density in passivation layers <NUM>, <NUM>, <NUM> and the respective thickness of that layer is less than the (two-dimensional) sheet carrier density at heterojunction <NUM>. For example, the number of charge defects per area in passivation layers <NUM>, <NUM>, <NUM> may be less than <NUM>%, or less than <NUM>%, of the sheet carrier density at heterojunction <NUM>.

Source electrode <NUM> is disposed a lateral distance d2 from drain electrode <NUM>. In some examples, lateral distance d2 is between <NUM> and <NUM> micrometers (more specifically between <NUM> and <NUM> micrometers). In some examples, lateral distance d1 is between <NUM> and <NUM> micrometers (more specifically between <NUM> and <NUM> micrometers). In some examples, the thickness of second passivation material <NUM> is between <NUM> and <NUM> micrometers (more specifically between <NUM> and <NUM> micrometers). In some examples, lateral distance d4 is between <NUM> and <NUM> micrometers (more specifically between <NUM> and <NUM> micrometers). In some examples, the thickness of third passivation layer <NUM> is between <NUM> and <NUM> micrometers (more specifically between <NUM> and <NUM> micrometers). In some examples, lateral distance d3 is between <NUM> and <NUM> micrometers (more specifically between <NUM> and <NUM> micrometers).

In operation, the insulation layers (e.g., first insulation layer <NUM> and second insulation layer <NUM>) and gate dielectric <NUM> are disposed to prevent charging of passivation layers (e.g., passivation layers <NUM>, <NUM> and <NUM>) in plurality of composite passivation layers <NUM>. Field distribution and charge shield metallization may be used in GaN-based electronic devices (such as high voltage, and/or high frequency transistors and diodes) to achieve high performance metrics. One promising passivation material for GaN electronic devices is silicon nitride (SiN). Accordingly, the above mentioned metallization is often formed over the SiN passivation layers. However, SiN has a relatively narrow band gap among dielectrics, which may lead to charge injection into the silicon nitride from the adjacent materials under electric field stress. As a result of charging, the material properties of both the passivation material (SiN) and the metallization pattern may change with time. This may lead to drifting performance, and under some conditions, irreversible failure of the device. Accordingly, by including a gate dielectric (e.g., gate dielectric <NUM>) and insulation layers (e.g., insulation layers <NUM> and <NUM>) in the passivation layer of the GaN based device, charging in the passivation layers may be reduced, since in some examples, the insulation layers have a wider bandgap than the passivation layers. Reduced charging in the passivation layers results in a lower probability of device failure/performance drift. Furthermore, since the insulation layers may be made out of the same material as the gate dielectric, additional process steps/materials may be avoided.

<FIG> is a cross-sectional view of an example HFET <NUM> with composite passivation layer <NUM>. In many ways HFET <NUM> is similar to (or the same as) HFET <NUM> of <FIG>. However, one noteworthy distinction is that in HFET <NUM>, the area of insulation layers <NUM>, <NUM> does not occupy the entire composite passivation layer. In other words, the lateral bounds of first insulation layer <NUM> are substantially coextensive with the lateral bounds of source field plate <NUM>, and the lateral bounds of the second insulation layer <NUM> are also substantially coextensive with the lateral bounds of source field plate <NUM>. In one example, the lateral bounds of first insulation layer <NUM> may extend past the first gate field plate <NUM> and end before via member <NUM>. In another or the same example, the length of second insulation layer <NUM> may extend past the source field plate <NUM> and end before via member <NUM>.

<FIG> is a cross-sectional view of an example HFET <NUM> with composite passivation layer <NUM>. HFET <NUM> is similar in many respects to HFETs <NUM> and <NUM> of <FIG>. However, HFET <NUM> includes a third composite passivation layer including third passivation layer <NUM> and third insulation layer <NUM>. HFET <NUM> also includes fourth passivation layer <NUM>. Third insulation layer <NUM> is disposed between third passivation layer <NUM> and fourth passivation layer <NUM>. Second gate field plate <NUM> is disposed between second insulation layer <NUM> and third passivation layer <NUM>, and is coupled to the first gate field plate <NUM>. As illustrated, source field plate <NUM> is disposed between third insulation layer <NUM> and fourth passivation layer <NUM>.

HFET <NUM> also includes first gate field plate <NUM>, source field plate <NUM>, and second gate field plate <NUM>. Second gate field plate <NUM> is electrically connected to gate electrode <NUM>. In some examples, source field plate <NUM> acts as a so-called "shield wrap. " As discussed above, some GaN devices suffer from parasitic DC-to-RF dispersion that is believed to arise-at least in part-due to the exchange of surface charges with the environment during high-voltage operation. In particular, surface states charge and discharge with relatively slow response times. Subsequently, performance of GaN devices suffer at high frequency operation. Metallic shield wraps can mitigate or eliminate these effects by improving shielding and preventing the movement of surface charges. In some examples, source field plate <NUM> may reduce the peak values of electric fields in HFET <NUM> (e.g., the electric field between heterojunction <NUM> and third edge <NUM> of second gate field plate <NUM>). In some examples, source field plate <NUM> also acts to deplete heterojunction <NUM> of charge carriers, as discussed further below. In some examples, source field plate <NUM> serves in multiple capacities, i.e., acting as a shield wrap, a field plate, and/or to deplete heterojunction <NUM>. The particular use of source field plate <NUM> in a device will be a function of any of a number of different geometric, material, and operational parameters. Because of the possibility for source field plate <NUM> to perform one or more roles, it is referred to herein simply as a "source field plate.

In the illustrated examples, source field plate <NUM> has a generally rectangular cross-section. Source field plate <NUM> includes a fourth edge <NUM>. Fourth edge <NUM> is disposed a lateral distance d0+d1+d3+d11 towards drain electrode <NUM> from a side of source electrode <NUM> and a vertical distance d5+d6+d7+d8 above second semiconductor material <NUM>. In some examples, lateral distance d0+d1+d3+d11 is greater than or equal to twice the vertical distance d5+d6+d7+d8. For example, lateral distance d0+d1+d3+d11 can be greater than or equal to three times d5+d6+d7+d8. Fourth edge <NUM> is vertically separated from second semiconductor material <NUM> by gate dielectric <NUM>, first passivation layer <NUM>, first insulation layer <NUM>, second passivation layer <NUM>, second insulation layer <NUM>, third passivation layer <NUM>, and third insulation layer <NUM>. As discussed further below, the electric field between source field plate <NUM> and heterojunction <NUM> are highest at fourth edge <NUM> under certain bias conditions.

Source field plate <NUM> can be electrically connected to source electrode <NUM> in a variety of ways. In the illustrated examples, source electrode <NUM> is electrically connected to source field plate <NUM> by a source via member <NUM>. In other examples, source electrode <NUM> can be electrically connected to source field plate <NUM> outside of the illustrated cross-section.

As shown, drain electrode <NUM> is electrically connected to another drain via by way of via members <NUM>, <NUM>. Drain via member <NUM> extends through third passivation layer <NUM> to a same vertical level as second gate field plate <NUM>, thus acting as an extension of drain electrode <NUM>. Via member <NUM>, by virtue of being on the same vertical level as source field plate <NUM>, is the nearest extension of drain electrode <NUM> to source field plate <NUM>. The fourth composite passivation material has a thickness d10.

In some examples, d1+d3+d4 is between <NUM> and <NUM> micrometers (more specifically between <NUM> and <NUM> micrometers). In some examples, lateral distance d9 is between <NUM> and <NUM> micrometers (more specifically between <NUM> and <NUM> micrometers). In some examples layers <NUM>, <NUM>, <NUM>, <NUM> have a composition and quality such that-after extended operation at steady state operational parameters-the number of charge defects per-area in layers <NUM>, <NUM>, <NUM>, <NUM> is less than the sheet carrier density at the heterojunction. In other words, the sum of the products of each three-dimensional defect density of passivation layers <NUM>, <NUM>, <NUM>, <NUM> and the respective thickness of that layer is less than the (two-dimensional) sheet carrier density at heterojunction <NUM>. For example, the number of charge defects per area in insulating material layers <NUM>, <NUM>, <NUM>, <NUM> is less than <NUM>%, (more specifically, less than <NUM>%, of the sheet carrier density at heterojunction <NUM>).

<FIG> is a cross-sectional view of an example HFET <NUM> with a composite passivation layer <NUM>. HFET <NUM> is similar to HFET <NUM>; however, the lateral bounds of first insulation layer <NUM> are substantially coextensive with the lateral bounds of first gate field plate <NUM>, the lateral bounds of second insulation layer <NUM> are substantially coextensive with the lateral bounds of second gate field plate <NUM>, and the lateral bounds of third insulation layer <NUM> are substantially coextensive with the lateral bounds of the source field plate <NUM>. In other words, HFET <NUM> is similar to HFET <NUM> except the area of insulation layers <NUM>, <NUM>, <NUM> in HFET <NUM> does not occupy the entire passivation layer. In one example, the length of first insulation layer <NUM> may extend past first gate field plate <NUM> and end before via member <NUM>. In one example, the length of second insulation layer <NUM> may extend past the second gate field plate <NUM> and end before via member <NUM>. In one example, the length of third insulation layer <NUM> may extend past source field plate <NUM> and end before the drain <NUM>.

<FIG> is a flow chart illustrating an example method <NUM> of HFET fabrication. The order of process blocks <NUM> - <NUM> in method <NUM> should not be deemed limiting. As one skilled in the pertinent art will appreciate, process blocks <NUM> - <NUM> may occur in any order and even in parallel. Furthermore, process blocks may be added to/removed from method <NUM>, as process blocks <NUM> - <NUM> depict a highly simplified version of method <NUM> in order to prevent obscuring certain aspects of the instant disclosure.

Process block <NUM> depicts depositing a semiconductor layer (e.g., first <NUM> and second semiconductor material <NUM>) on a substrate. In one example, the semiconductor layer and substrate may be comprised of any of the materials listed in the discussion of <FIG>. In one example, a heterojunction may be formed between a first semiconductor material and second semiconductor material (e.g., first semiconductor material <NUM> and second semiconductor material <NUM>). In another or the same example, source electrode and drain electrode are coupled to the second semiconductor material. Furthermore, a gate dielectric may be deposited proximate to second semiconductor material such that the second semiconductor material is disposed between the gate dielectric and the first semiconductor material.

Process block <NUM> illustrates depositing one or more composite passivation layers on the semiconductor layer. In one example, this may include depositing a plurality of composite passivation layers, where a first composite passivation layer in the plurality of composite passivation layers includes a first insulation layer and a first passivation layer. In the aforementioned example, the first passivation layer is disposed between the gate dielectric and the first insulation layer, and a gate may be formed between the gate dielectric and the plurality of composite passivation layers. In another or the same example, a second composite passivation layer in the plurality of composite passivation layers may be deposited. The second composite passivation layer may include a second insulation layer and a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. In one example, the first insulation layer has a larger bandgap than the first passivation layer. In another or the same example, the first passivation layer includes SiN, and the gate dielectric and the first insulation layer include a metal oxide
In one example, depositing the plurality of composite passivation layers includes depositing the first insulation layer and the second insulation layer such that lateral bounds of the first insulation layer and the second insulation layer are less than a lateral distance between the source electrode and drain electrode. In another or the same example, a third composite passivation layer is deposited and includes a third insulation layer and third passivation layer. In this example, the second insulation layer is disposed between the second passivation layer and the third passivation layer.

Process block <NUM> shows forming ohmic contacts by recess etching, metal deposition, metal patterning, and rapid thermal annealing. The ohmic contacts are in contact with the top surface of the semiconductor layer such as in <FIG>.

Process block <NUM> depicts patterning one or more field plates on the one or more composite passivation layers. In one example, a first gate field plate is formed between the first passivation layer and the second passivation layer. In another or the same example, the first gate field plate is coupled to the gate electrode. Furthermore, a source field plate may be deposited on the second insulation layer. In one example, the first gate field plate is disposed between the first insulation layer and the second passivation layer. In another example, a second gate field plate (coupled to the first gate field plate) is formed, and the second gate field plate is disposed between the second insulation layer and a third passivation layer. The source field plate may be coupled to the source electrode and formed on the third insulation layer.

Process block <NUM> shows depositing an encapsulation layer on the top most composite passivation layer. In one example, depositing an encapsulation layer includes a fourth passivation layer, where the fourth passivation layer is disposed on the source field plate and third insulation layer.

In block <NUM>, a semiconductor layer is deposited on the substrate. In one example, the semiconductor layer and substrate may comprise of any of the materials listed in the discussion of <FIG>.

Process block <NUM> depicts depositing one or more composite passivation layers on the semiconductor layer. It should be appreciated that the insulation materials and passivation material in composite passivation layers may include the same or different material compositions.

Block <NUM> shows that footprints for ohmic contacts are formed via plasma etching. The footprints may be formed by using the composite passivation layers as an etch stop. As mentioned previously, the composite passivation layers include a gate dielectric layer and a passivation layer. In one example, the gate dielectric layer may be made of aluminum oxide and the passivation layer may be made of silicon nitride (SiN). The plasma etch rate of the passivation material is greater than the etch rate of the gate dielectric material. In one example, the plasma etch rate of passivation material is substantially greater than the etch rate of gate dielectric. In one example, the etch rate of the passivation layers may be up to <NUM> times greater than the etch rate of the gate dielectric and isolation layers. This allows for precise control of the thickness of device layers under each field plate (i.e., gate field plates, source field plates, drain field plates). In one example, the gate dielectric and insulation layers may be used as etch stop layers.

In process block <NUM>, ohmic contacts are created by recess etching, metal deposition, metal patterning, and high temperature annealing.

Optional process block <NUM> shows that additional composite passivation layers are deposited.

In block <NUM>, a gate contact is formed by metal deposition and metal patterning. An optional field plate may also be created in this step.

Process blocks <NUM>-<NUM> are optional in example method <NUM>. Block <NUM> depicts depositing additional composite passivation layers. In block <NUM>, additional footprints for field plates can be created by plasma etching with an etch stop. Block <NUM> shows depositing and patterning additional metal field plates.

In block <NUM>, an encapsulation layer is deposited on the top most composite passivation layer.

<FIG> is a cross-sectional view of an example HFET <NUM> with composite passivation layer <NUM>. In many ways HFET <NUM> is similar to (or the same as) HFET <NUM> of <FIG>. However, one noteworthy distinction is that in HFET <NUM> includes second gate field plate <NUM> that is coupled to the first gate field plate <NUM> and is disposed between second insulation layer <NUM> and third passivation layer <NUM>. It is appreciated that in another example of HFET <NUM>, the area of insulation layers <NUM>, and <NUM>, does not occupy the entire composite passivation layer. In this example, the lateral bounds of first insulation layer <NUM> may be substantially coextensive with the lateral bounds of first gate field plate <NUM>, and the lateral bounds of second insulation layer <NUM> may be substantially coextensive with second gate field plate <NUM>. In other words, the insulation layers <NUM>, and <NUM>, do not extend the entire distance between source electrode <NUM> and drain electrode <NUM>.

<FIG> is a cross-sectional view of an example HFET <NUM> with composite passivation layer <NUM>. HFET <NUM> is similar in many respects to the HFETs shown in the previous figures. However, HFET <NUM> includes a third composite passivation layer including third passivation layer <NUM> and third insulation layer <NUM>. HFET <NUM> also includes fourth passivation layer <NUM>. Third insulation layer <NUM> is disposed between third passivation layer <NUM> and fourth passivation layer <NUM>. Second gate field plate <NUM> is disposed between second passivation layer <NUM> and third passivation layer <NUM> and is coupled to the first gate field plate <NUM>. As illustrated, third gate field plate <NUM> is disposed between the third insulation layer <NUM> and fourth passivation layer <NUM>. The third gate field plate <NUM> is coupled to the second gate field plate <NUM>. It is appreciated that in another embodiment of HFET <NUM>, the area of insulation layers <NUM>, <NUM>, and <NUM> does not occupy the entire composite passivation layer <NUM>. In this example, the lateral bounds of third insulation layer <NUM> are substantially coextensive with third gate field plate <NUM>. In other words, the insulation layers <NUM>, <NUM>, and <NUM> do not extend the entire distance between source electrode <NUM> and drain electrode <NUM>.

<FIG> is a cross-sectional view of a HFET <NUM> with composite passivation layer <NUM> according to the present invention. HFET <NUM> is similar in many respects to the HFETs shown in <FIG>, <FIG>and <FIG>. However, according to the present invention, HFET <NUM> includes a second gate connected field plate <NUM>. The second gate field plate <NUM> is coupled to first gate field plate <NUM>. It is appreciated that in another embodiment of HFET <NUM>, the area of insulation layers <NUM>, <NUM>, <NUM> does not occupy the entire composite passivation layer. In other words, like in the other HFET embodiments, insulation layers <NUM>, <NUM>, <NUM> do not extend the entire distance between source electrode <NUM> and drain electrode <NUM>.

HFET <NUM> includes first semiconductor material <NUM>, second semiconductor material <NUM>, and heterojunction <NUM> (disposed between them). HFET <NUM> also has a plurality of composite passivation layers. First composite passivation layer includes first insulation layer <NUM> and first passivation layer <NUM>, and first passivation layer <NUM> is disposed between second semiconductor material <NUM> and first insulation layer <NUM>. Second composite passivation layer includes second insulation layer <NUM> and second passivation layer <NUM>, and second passivation layer <NUM> is disposed between first insulation layer <NUM> and second insulation layer <NUM>. Third composite passivation layer includes third insulation layer <NUM> and third passivation layer <NUM>. Third passivation layer <NUM> is disposed between second insulation layer <NUM> and third insulation layer <NUM>. According to the present invention, first gate field plate <NUM> is disposed between first passivation layer <NUM> and second passivation layer <NUM>. Furthermore, gate dielectric <NUM> is disposed between first passivation layer <NUM> and second semiconductor material <NUM>. Gate electrode <NUM> is disposed between gate dielectric <NUM> and first passivation layer <NUM>. HFET <NUM> includes fourth passivation layer <NUM> and third insulation layer <NUM> is disposed between fourth passivation layer <NUM> and third passivation layer <NUM>.

According to the present invention, second gate field plate <NUM> extends from second passivation layer <NUM>, through second insulation layer <NUM>, through third passivation layer <NUM>, and into fourth passivation layer <NUM>. It is worth noting that in the depicted embodiment, second gate field plate <NUM> has a large continuous bulk metal component disposed in third passivation layer <NUM>. In one embodiment, the lateral dimension of the bulk component of second gate field plate <NUM> occupies less than <NUM>% of the distance between source electrode <NUM> and drain electrode <NUM> in third passivation layer <NUM>. In another embodiment, the lateral dimension of the bulk component of second gate field plate <NUM> occupies less than <NUM>% of the distance between source electrode <NUM> and drain electrode <NUM> in third passivation layer <NUM>. In the illustrated embodiment, second gate field plate <NUM> has a larger lateral cross sectional diameter than first gate field plate <NUM>, and second gate field plate <NUM> is disposed above first gate field plate <NUM>. As depicted, second gate field plate <NUM> has a component that is disposed between third passivation layer <NUM> and fourth passivation layer <NUM>. In the depicted embodiment, this component is segmented; however, in other embodiments this component may be continuous. It should be noted that second gate field plate <NUM> may take any of the shapes of the first gate field plates, second gate field plates, and/or third gate field plates in any of the examples depicted in <FIG>, <FIG>, and <FIG>. These shapes may be achieved via fabrication of a single continuous gate field plate (e.g., second gate field plate <NUM>), rather than dividing the gate field plate fabrication process into many steps to form individual gate field plates.

In one embodiment, HFET <NUM> may be fabricated by the following method. It should be noted that these steps may be completed in any order and even in parallel. Furthermore, as will be appreciated by one skilled in the relevant art, the following method may omit steps, or alternatively, may include steps that are not necessary.

A first semiconductor material and a second semiconductor material are provided. A heterojunction is disposed between the first semiconductor material and the second semiconductor material. In one embodiment, first and/or second semiconductor materials may include GaN.

Source and drain electrodes are formed on the second semiconductor material. In one example, source and drain electrodes may extend into the second semiconductor material and may even contact the first semiconductor material.

A gate dielectric is formed on the second semiconductor material. In one example, the gate dielectric includes AlOx, HfOx, or other suitable dielectric materials (high-k or otherwise).

A gate electrode is formed proximate to the surface of the second semiconductor material, and the gate dielectric is disposed between the gate electrode and the second semiconductor material.

A plurality of composite passivation layers is deposited proximate to the gate dielectric, and the gate dielectric is disposed between the plurality of composite passivation layers and the second semiconductor material. In one example, a first composite passivation layer in the plurality of composite passivation layers includes a first passivation layer and a first insulation layer. The first passivation layer is disposed between the gate dielectric and the first insulation layer. In another or the same example, a second composite passivation layer in the plurality of composite passivation layers includes a second passivation layer and a second insulation layer. The second passivation layer is disposed between the first insulation layer and the second insulation layer.

Patterned trenches are then etched into the plurality of composite passivation layers to form one or more gate field plates. The geometry of these patterned trenches may be controlled by depositing and resolving a photoresist (positive or negative) on appropriate layers of device architecture. The trench geometry may match the shape of the field plates to be formed (for details about trench geometry, see description of first, second, and third, gate field plates as discussed above in connection with <FIG>, and <FIG>). In one example, etching of first composite passivation layer may occur prior to forming the second composite passivation layer. However, in another example the plurality of composite passivation layers may be formed and then etched all together. Etching may include wet and/or dry etching. It should be noted that the passivation layers may include SiN and etch up to <NUM> times faster than the insulation layers, depending on the etchant used and the process employed. Accordingly, insulation layers and/or the gate dielectric may be used as etch stop layers to precisely control the geometry of gate field plates.

The etched patterns/holes may then be backfilled with a metal or other conductive material to form gate field plates (such as first gate field plate, second gate field plate, and third gate field plate from <FIG>, and <FIG>and associated discussion). The field plates may be deposited in one or many steps, and their geometry may include one continuous layer or multiple structures independent of one another. In the example depicted in <FIG>, the bulk of second gate field plate <NUM> may have been formed in one metal deposition step, by depositing metal in a trench etched into third passivation layer <NUM>. After this, the portion of second gate field plate <NUM> disposed on third passivation layer <NUM> may have been patterned and deposited.

It should be noted that after the gate field plates have been formed, excess metal/deposition flux may be removed by chemical mechanical polishing or the like. Additional isolation and/or passivation layers may be deposited after forming the various field plate architectures. Furthermore, the process above may be used to fabricate any of the geometric structures depicted in the figures and described in the specification.

The above description of illustrated examples of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

Claim 1:
A high-voltage field effect transistor (<NUM>), comprising:
a first semiconductor material (<NUM>), a second semiconductor material (<NUM>), and a heterojunction (<NUM>), wherein the heterojunction is disposed between the first semiconductor material and the second semiconductor material;
a plurality of composite passivation layers (<NUM>), including
a first composite passivation layer with a first insulation layer (<NUM>) and a first passivation layer (<NUM>), wherein the first passivation layer is disposed between the second semiconductor material and the first insulation layer and the first insulation layer is made from a dielectric suitable for forming a gate insulator,
a second composite passivation layer with a second insulation layer (<NUM>) and a second passivation layer (<NUM>), wherein the second passivation layer is disposed between the first insulation layer and the second insulation layer and the second insulation layer is made from a dielectric suitable for forming a gate insulator, and
a third composite passivation layer with a third insulation layer (<NUM>) and a third passivation layer (<NUM>), wherein the third passivation layer is disposed between the second insulation layer and the third insulation layer;
a fourth passivation layer (<NUM>), wherein the third insulation layer is disposed between the fourth passivation layer and the third passivation layer;
a first gate field plate (<NUM>) disposed between the first passivation layer and the second passivation layer, wherein the first gate field plate is coupled to a gate electrode (<NUM>);
a second gate field plate (<NUM>) coupled to the first gate field plate, wherein the second gate field plate extends from the second passivation layer, through the second insulation layer, through the third passivation layer, through the third insulation layer, and into the fourth passivation layer; and
the high-voltage field effect transistor further comprises a gate dielectric (<NUM>) disposed between the first passivation layer and the second semiconductor material,
wherein the gate electrode (<NUM>) is disposed between the gate dielectric and the first passivation layer.