Patent Description:
An oscilloscope has typically several input channels that can be used for analyzing appropriate signals inputted. For the analyzing, the oscilloscope has an internal signal analyzing circuit that receives the appropriate signals to be analyzed. There are signal analyzers for a long time which are able to acquire an input signal at a first channel, to acquire another input signal at a second channel and to analyze the input signals simultaneously in an oscilloscope-like manner in the time domain and in a spectrum analyzer-like manner in the frequency domain, respectively. In addition, known signal analyzers are able to acquire the first input signal and analyze the same in time and frequency domain. Spectrum analyzer-like manner means to down-convert the frequency of the input signal.

In contrast, other signal analyzers are known to offer time and direct FFT-like frequency domain analysis wherein FFT is an abbreviation for Fast Fourier Transform. FFT-like frequency domain analysis means processing a digitized input signal according to a FFT algorithm to generate frequency data without any frequency down-conversion. This is also called a simple FFT mode.

However, the simple FFT mode has a limited bandwidth as well as a limited resolution compared to down-converting the input signal as it is done in the spectrum analyzer-like manner.

Nowadays, modern multi-domain oscilloscopes make use of these longstanding concepts. They process signals both in the time domain and in the frequency domain. Accordingly, it is possible to provide information to a user regarding a time domain and a frequency domain. Other modern oscilloscopes have a built-in dedicated spectrum analyzer.

In the state of the art, oscilloscopes are known that have dedicated channels with regard to the analyzing purposes. Such conventional oscilloscopes comprise two or four time so called time-domain channels and one frequency-domain channel. This means that the time-domain channels are configured to only perform a time domain analysis whereas the frequency-domain channel is configured to only perform a frequency domain analysis. However, this limits the capability or rather the flexibility of the oscilloscope.

Moreover, oscilloscopes are known that perform the time domain analysis and the frequency domain analysis for each channel simultaneously wherein the analyzing results are stored in a subsequent acquisition memory. However, this results in an oscilloscope requiring a lot of storage capacity of the acquisition memory since both the frequency domain analysis results and the time domain analysis results are stored appropriately. For instance, <CIT> inter alia shows such an oscilloscope.

Furthermore, <CIT> describes an oscilloscope with a cross domain trigger unit that identifies a respective trigger condition in the analog input signal processed.

<CIT> shows a method and apparatus for selectively providing bandwidth extension and channel matching for acquired signals under test (SUT), wherein a stream of acquired signals is provided and processed.

<CIT> describes a digital oscilloscope that provides information concerning the significance of peak information.

Accordingly, there is a need for an oscilloscope providing a high capability or flexibility, which is efficient with regard to the usage of the storage capacity of the acquisition memory.

Embodiments of the invention provide a signal analyzing circuit as defined in independent claim <NUM>.

Accordingly, it is ensured that the appropriate channel can be used for analyses in the time domain as well as for analyses of the spectrum of the signal depending on the switching unit, in particular its status. In fact, a time domain operation mode as well as a spectrum view mode are provided wherein the spectrum view mode differs from a frequency domain mode in that the signal processed by the respective channel corresponds to a time-and-value-discrete signal instead of frequency data. Hence, the channel used for the spectrum view mode corresponds to a time domain channel rather than a frequency domain channel that does not exist.

Furthermore, the storage capacity of the acquisition memory is not limited since the switching unit connects the acquisition memory with either said decimator unit or said digital down converter unit appropriately ensuring that only the decimated time-and-value-discrete signal or the down-converted time-and-value-discrete signal is stored in the acquisition memory which saves a lot of storage capacity. Thus, the storage capacity stored can be used appropriately. For instance, there is more free memory for spectrum analysis in the digital down conversion mode (also called spectrum view mode) if no decimated time-and-value-discrete signal data has to be stored in the acquisition memory. The additional storage capacity due to the saving can also be used for applying higher acquisition rates compared to the prior art, namely the acquisition rates used by oscilloscopes acquiring data of the time domain analysis and the spectrum view analysis simultaneously.

As either said decimator unit or said digital down converter unit is coupled to said acquisition memory, said acquisition memory is adapted to store only either said decimated time-and-value-discrete signal or said down-converted time-and-value-discrete signal. However, said acquisition memory is not adapted to store said decimated time-and-value-discrete signal and said down-converted time-and-value-discrete signal since it is not connected to said decimator unit and said digital down converter unit, simultaneously.

In said time-domain operation mode, said switching unit may couple said digitizer to said decimator unit wherein said digitizer is not coupled to said digital down converter unit.

In said spectrum view operation mode, said switching unit may couple said digitizer to said digital down converter unit wherein said digitizer is not coupled to said decimator unit.

Accordingly, decimating and down-converting does not take place simultaneously.

In addition, the storage capacity saved can be used to increase the persistence of the data provided, in particular in a digital persistence mode.

However, the respective channel does not process any frequency domain data as time-and-value-discrete signals are processed by the channel and stored in the acquisition memory, in particular decimated time-and-value-discrete signals or down-converted time-and-value-discrete signals.

In general, the signal analyzing circuit may be part of a test and measurement instrument, such as an oscilloscope. In fact, the signal analyzing circuit is integrated in the instrument appropriately.

The time-and-value-discrete signal relates to a time-discrete signal (also called discrete-time signal), namely signal points at equidistant times or a time series consisting of a sequence of quantities, as well as a value-discrete signal such as a digital signal. Therefore, the time-and-value-discrete signal is obtained after the digitizing step done by the digitizer. As the switching unit is connected to the digitizer, the switching unit receives the time-and-value-discrete signal provided by the digitizer. Depending on the operation mode, the time-and-value-discrete signal is processed by the decimator unit or rather the digital down converter unit.

The decimator unit receives the time-and-value-discrete signal in a certain operation mode (time domain mode). Generally, the decimator unit is used to reduce the sample rate and the amount of data related thereto. The reducing of the sample rate is also called decimation. For instance, only one sample of several samples in a certain interval is used wherein the other samples in this interval are discarded. The reduction to one sample per interval is also called simple decimation.

The digital down converter unit receives the time-and-value-discrete signal in an appropriate operation mode, namely the spectrum view mode. In general, the digital down converter unit down-converts the time-and-value-discrete signal obtained into the baseband or to an intermediate frequency. The digital down conversion may also provide decimation in addition to the frequency translation. This is called tune and zoom.

For instance, the data obtained is translated to <NUM> using a quadrature mixer for tuning wherein this translated data is then filtered and decimated for zooming. As the digital down conversion provides complex In-phase and Quadrature data (IQ data), center frequency translation down to <NUM> and filtering as well as data decimation afterwards are enabled to remove unwanted frequency components and reduce the data size for the respective bandwidth. In fact, digital down conversion provides multiple advantages as it reduces both on-board memory and data transfer requirements. In addition, the filtering and the decimation reduce the wideband integrated noise and improves the overall signal to noise ratio. In summary, the digital down conversion allows bandwidth and data reduction without concern of aliasing products.

Another embodiment which is not encompassed by the wording of the claims but is considered as useful for understanding the invention provides a signal analyzing circuit with at least a first channel, said first channel comprising:.

In this embodiment, two different acquisition memories are provided wherein the first one stores only said decimated time-and-value-discrete signal processed by said decimator unit previously. The respective data is accessed for being processed by said digital down converter unit located after said first acquisition memory to down-convert said decimated time-and-value-discrete signal appropriately in order to provide a down-converted and decimated time-and-value-discrete signal.

Thus, said first acquisition memory is positioned between said decimator unit and said down converter unit. Accordingly, said first acquisition memory is not configured to store signals from said decimator unit and said down converter unit as it only receives a signal from said decimator unit and provides the respective data for said down converter unit.

According to an aspect either said decimator unit or said digital down converter unit is operated at a certain time. This means that an input signal processed by the channel is not decimated and down-converted simultaneously since only one both units is active at the same time. Using only one of the units, namely the decimator unit and the digital down convert unit, at the same time saves resources and costs.

Another aspect provides that said switching unit comprises a first switching member and a second switching member, said first switching member being positioned in front of said decimator unit and said digital down converter unit, said second switching member being positioned after said decimator unit and said digital down converter unit. The two switching members ensure that the time-and-value-discrete signal is processed appropriately. Both switching members may be controlled simultaneously or they control each other such that it is ensured that both switching members have the corresponding switch state ensuring that the digitizer as well as the acquisition memory both are connected to either said decimator unit or said digital down converter unit.

Generally, depending on the mode activated, the decimator unit or the digital down conversion unit is activated, for instance via the switching unit, for processing the time-and-value-discrete signal.

According to another aspect, a Fourier transform unit is provided, said Fourier transform unit being adapted to convert said down-converted time-and-value-discrete signal into data used for spectrum analysis. In another embodiment, the Fourier transform unit may be adapted to convert said down-converted and decimated time-and-value-discrete signal into data used for spectrum analysis. The Fourier transform unit is associated to the digital down converter unit such that the down-converted (and decimated) time-and-value-discrete signal is Fourier transformed by the Fourier transform unit such that the respective data used for spectrum analysis is obtained. Hence, the ability is provided to analyze the respective signal with regard to its spectrum.

Particularly, said Fourier transform unit is coupled with said acquisition memory, in particular said second acquisition memory, accessing only data directed to said down-converted (and decimated) time-and-value-discrete signal. Accordingly, the respective down-converted time-and-value-discrete signal data is read out of the acquisition memory by the Fourier transform unit in order to obtain the respective data used to perform the analysis with regard to the spectrum of the signal.

In general, the acquisition memory acquires only signals in the time domain, namely the decimated time-and-value-discrete signal, the down-converted time-and-value-discrete signal or the down-converted and decimated time-and-value-discrete signal. In other words, only time-and-value-discrete signals, namely decimated ones or rather down-converted ones, are stored in the acquisition memory, but no data relating to the frequency domain.

In fact, the Fourier transform unit reads out the down-converted (and decimated) time-and-value-discrete signal for transforming the data appropriately to obtain data for further processing and analyzing purposes with regard to the spectrum of the signal.

For instance, said Fourier transform unit is a Fast Fourier transform unit. The Fast Fourier transformation (FFT) ensures transformation of the appropriate data in an efficient manner, in particular the calculation of the Discrete Fourier transformation (DFT).

Another aspect provides that said switching unit comprises a multiplexer unit. Thus, different switch states can be applied providing a greater diversity with regard to signal processing.

Generally, each of the switch members may be established by a multiplexer unit. Thus, the multiplexer unit provided as the first switching member may be located between said digitizer and said decimator unit as well as between said digitizer and said digital down converter unit.

The multiplexer unit provided as the second switching member may be provided between said decimator unit and said acquisition memory as well as between said digital down converter unit and said acquisition memory.

According to a certain embodiment, said decimator unit comprises at least two decimators, said at least two decimators being assigned to said switching unit. The signal processed via the decimator unit, in the corresponding operation mode, can be processed by different decimators ensuring a greater variety with regard to signal processing. For instance, both decimators are coupled to a multiplexer unit.

Particularly, said at least two decimators are configured to pass signals of a different bandwidth. For instance, the first decimator is set to pass signals of a certain bandwidth to the acquisition memory whereas the second decimator is set to pass signals of a bandwidth being lower. This results in a zoom function.

Another aspect provides that said digital down converter unit comprises at least two digital down converters, said at least two digital down converters being assigned to said switching unit. A multi (Fast) Fourier transform mode (FFT mode) may be established by converting the signal processed by the digital down converter unit differently wherein the down-converted time-and-value-discrete signals are transformed differently by the Fourier transform unit. The at least two digital down converters may also be coupled to a multiplexer unit.

For instance, said digitizer comprises an analog to digital converter and a sampler. The analog input signals are sampled using the sampler and digitized using the analog to digital converter such that the time-and-value-discrete signals are obtained for further processing. Hence, the sampler reduces the continuoustime signals into discrete time-signals that are digitized in order to obtain the time-and-value-discrete signals.

According to another aspect, at least one of said digital down-converter unit and said decimator unit is established by a field-programmable gate array. The field-programmable gate array (FGPA) may be established in a more cost-efficient manner as only one of both units, namely said digital down-converter unit and said decimator unit, is active at the same time.

Hence, said switching unit may be established by a field-programmable gate array, said field-programmable gate array being configured to implement either said decimator unit or said digital down-converter unit selectively depending on the operation mode. Accordingly, the field-programmable gate array comprises two different configurations assigned to said operation modes. In general, this embodiment corresponds to a signal analyzing circuit having two different field-programmable gate array configurations as either said decimator unit or said digital down-converter unit is implemented.

According to a certain embodiment which is not convered by the subject-matter of the claims, said signal analyzing circuit comprises several channels, each of said several channels is established like said first channel. Different signal sources may be analyzed simultaneously due to the fact that each channel can be used for time domain analysis and spectrum analysis. The respective analysis results of the different signal sources can be outputted simultaneously, in particular displayed. However, as each channel can only perform a time domain analysis or a spectrum analysis at the same time, the same signal source cannot be analyzed with regard to the spectrum and the time domain simultaneously by a single channel.

In the second embodiment which is not convered by the subject-matter of the claims, at least one of a multiplexer unit and a plurality of channels is provided. The plurality of channels may be coupled to said first acquisition memory that is coupled to said multiplexer unit. Accordingly, the data stored in said first acquisition memory can be accessed in different manner due to the multiplexer unit. Moreover, several signals may be stored in the same first acquisition memory as the plurality of channels is coupled to said first acquisition memory.

Each of said plurality of channels comprises a digitizer configured to digitize an input signal into a time-and-value-discrete signal as well as a decimator unit coupled to said digitizer to decimate said time-and-vale-discrete signal to a decimated time-and-value-discrete signal.

Embodiments of the present disclosure further provides an oscilloscope comprising a signal analyzing circuit as mentioned above. The oscilloscope can be used for time domain and spectrum analyses, in particular simultaneous analyses of different signal sources.

According to an aspect, said oscilloscope is a portable oscilloscope. A compact device is provided that may be handheld device. The display size of the portable oscilloscope is typically limited such that the different information to be displayed can be selected by the user appropriately.

Further, a method for auto setting an oscilloscope with a signal analyzing circuit is described, said method not being encompassed by the wording of the claims but being considered as useful for understanding the invention. Said method comprises the following steps:.

This auto setting method ensures that no aliasing effects occur since the decimator unit is set appropriately due to the power analysis done previously. Thus, it is ensured that no manual input is required as the appropriate channel is operated in two different modes subsequently, namely the spectrum view mode for determining the maximum frequency and then the time domain mode for analyzing the input signal in the time domain without any aliasing effects.

Particularly, the signal analyzing circuit of the oscilloscope is established as mentioned above or the oscilloscope is established as mentioned above.

The foregoing aspects and many of the attended advantages of the claimed subject matter will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:.

In <FIG>, an oscilloscope <NUM> is shown that comprises a housing <NUM> and a display <NUM> that is provided on at least one side of the oscilloscope <NUM>.

The oscilloscope <NUM> according to the shown embodiment comprises four inputs <NUM>, <NUM>, <NUM>, <NUM> that are configured to receive input signals of signal source(s) to be processed by the oscilloscope <NUM> appropriately, in particular analyzed by the oscilloscope <NUM> as will be described hereinafter.

In general, the oscilloscope <NUM> is a test and measurement instrument that can process or rather analyze signals.

The oscilloscope <NUM> shown in <FIG> is a handheld device such that the oscilloscope <NUM> is portable which means that it can be grabbed by a user easily and carried to a certain location for performing the tests intended.

As already indicated by the dashed lines in <FIG>, the oscilloscope <NUM> comprises an internal signal analyzing circuit <NUM> which is shown in more detail in <FIG> for a certain embodiment.

The signal analyzing circuit <NUM> is connected with the first input <NUM> that is connected to a digitizer <NUM> that comprises inter alia a sampler <NUM> and an analog to digital converter <NUM> for providing a time-and-value-discrete signal when processing the analog input signal fed to the first input <NUM>.

The digitizer <NUM> is coupled to a switching unit <NUM> that receives the time-and-value-discrete signal obtained after being processed by the digitizer <NUM>.

In the shown embodiment, the switching unit <NUM> has two switching members 33a, 33b wherein the first switching member 33a is connected directly to the digitizer <NUM>.

The first switching member 33a may have two different switch states that are assigned to two different operation modes of the signal analyzing circuit <NUM>, namely a spectrum view mode and a time domain mode as will be described later. Thus, the incoming line is split into two branch lines wherein only one of both branch lines can be coupled to the incoming line originating from the digitizer <NUM>.

Further, the first switching member 33a is directly coupled to a decimator unit <NUM> such that the decimator unit <NUM> receives the time-and-value-discrete signal from the digitizer <NUM> via the switching unit <NUM>, in particular the first switching member 33a, in a first switch state of the first switching member 33a assigned to the time domain operation mode.

In the time domain operation mode, the decimator unit <NUM> receives the time-and-value-discrete signal via the first switching member 33a and reduces the sample rate as well as the amount of data related thereto. The reducing of the sample rate is also called decimation.

Accordingly, the time-and-value-discrete signal processed by the decimator unit <NUM> corresponds to a decimated time-and-value-discrete signal.

In addition, the first switching member 33a is also directly coupled to a digital down converter unit <NUM> such that the digital down converter unit <NUM> receives the time-and-value-discrete signal from the digitizer <NUM> via the first switching member 33a in a second switch state of the first switching member 33a assigned to the spectrum view operation mode.

In the spectrum view operation mode, the digital down converter unit <NUM> receives the time-and-value-discrete signal and down-converts the time-and-value-discrete signal obtained into the baseband or to an intermediate frequency. The digital down conversion may also provide decimation in addition to the frequency translation. This is generally called tune and zoom.

Accordingly, the time-and-value-discrete signal processed by the digital down converter unit <NUM> corresponds to a down-converted time-and-value-discrete signal.

The decimator unit <NUM> as well as the digital down converter unit <NUM> both are directly coupled to the second switching member 33b which also has two different switch states that correspond to the ones of the first switching member 33a.

Accordingly, the first and second switching members 33a, 33b establishing the switching unit <NUM> are located up- and downstream of the decimator unit <NUM> as well as the digital down converter unit <NUM>, respectively. Hence, the first switching member 33a is positioned in front of said decimator unit <NUM> and said digital down converter unit <NUM> whereas the second switching member 33b is positioned after said decimator unit <NUM> and said digital down converter unit <NUM>. In other words, the switching unit <NUM> accommodates both the decimator unit <NUM> and the digital down converter unit <NUM>.

Both switching members 33a, 33b are linked such that it is ensured that both switching members 33a, 33b have the same switching position that relates to the respective operation mode, namely the time domain operation mode or rather the spectrum view operation mode. Accordingly, both switching members 33a, 33b may be controlled simultaneously, for instance by a separate processing unit.

Alternatively, the first switching member 33a may control the second switching member 33b or vice versa.

In addition, the switching unit <NUM>, , in particular its second switching member 33b, is connected to an acquisition memory <NUM> that receives a time-and-value-discrete signal, namely the decimated time-and-value-discrete signal or the down-converted time-and-value-discrete signal depending on the operation mode of the signal analyzing circuit <NUM>.

In other words, the switching unit <NUM>, accommodating both switching members 33a, 33b, connects the digitizer <NUM> with the acquisition memory <NUM> via the decimator unit <NUM> or the digital down converter unit <NUM>.

In fact, the switching unit <NUM> is configured to selectively activate the decimator unit <NUM> or the digital down converter unit <NUM> depending on the switch states of the respective switching members 33a, 33b. Thus, either the decimator unit <NUM> or the digital down converter unit <NUM> is operated at a certain time as only one of both units is actively connected with the digitizer <NUM> and the acquisition memory <NUM>.

In other words, the acquisition memory <NUM> depending on the operation mode is only coupled to the decimator unit <NUM> or the digital down converter unit <NUM>.

Thus, the acquisition memory <NUM> is not coupled to the decimator unit <NUM> and the digital down converter unit <NUM> due to the switching unit <NUM>, in particular the second switching member 33b.

In a first operation mode, namely the time domain operation mode, the second switching member 33b connects the acquisition memory <NUM> with the decimator unit <NUM> and establishes an interruption between the acquisition memory <NUM> and the digital down converter unit <NUM>. Hence, the acquisition memory <NUM> is not coupled to the digital down converter unit <NUM> in the time domain operation mode.

In a second operation mode, namely the spectrum view operation mode, the second switching member 33b connects the acquisition memory <NUM> with the digital down converter unit <NUM> and establishes an interruption between the acquisition memory <NUM> and the decimator unit <NUM>. Hence, the acquisition memory <NUM> is not coupled to the decimator unit <NUM> in the spectrum view operation mode.

Thus, only the decimator unit <NUM> or rather the digital down converter unit <NUM> is coupled to the acquisition memory <NUM>.

In a similar manner, the first switching member 33a establishes a connection or an interruption with the decimator unit <NUM> or rather the digital down converter unit <NUM> such that only one of both units is coupled to the digitizer <NUM>.

In the time domain operation mode, the first switching member 33a connects the digitizer <NUM> with the decimator unit <NUM> and establishes an interruption between the digitizer <NUM> and the digital down converter unit <NUM>. Hence, the digitizer <NUM> is not coupled to the digital down converter unit <NUM> in the time domain operation mode.

In the spectrum view operation mode, the first switching member 33a connects the digitizer <NUM> with the digital down converter unit <NUM> and establishes an interruption between the digitizer <NUM> and the decimator unit <NUM>. Hence, the digitizer <NUM> is not coupled to the decimator unit <NUM> in the spectrum view operation mode.

Moreover, the signal analyzing circuit <NUM> has a Fourier transform unit <NUM> that is directly coupled to the acquisition memory <NUM>. The Fourier transform unit <NUM> is configured to transform the down-converted time-and-value-discrete signal into a data that can be processed and analyzed with regard to the spectrum.

For this purpose, the Fourier transform unit <NUM> accesses the acquisition memory <NUM> to read the down-converted time-and-value-discrete signal stored in the acquisition memory <NUM> for transforming purposes or the data assigned thereto. Hence, the Fourier transform unit <NUM> accesses only data directed to said down-converted time-and-value-discrete signal.

The Fourier transform unit <NUM> may be a Fast Fourier transform unit (FFT unit) that provides a Discrete Fourier transform (DFT) in an efficient manner.

In general, <FIG> shows a single channel <NUM> that is assigned to one input, namely the first input <NUM>.

Furthermore, at least one signal conditioning unit <NUM> is provided which is shown and described in more detail with regard to <FIG>.

The at least one signal conditioning unit <NUM> is positioned in front of the switching unit <NUM>, in particular in front of the first switching member 33a. However, the at least one signal conditioning unit <NUM> may also be provided between the first switching member 33a and the decimator unit <NUM> or between the first switching member 33a and the digital down converter unit <NUM>.

Alternatively or additionally, such a signal conditioning unit <NUM> may be provided after the switching unit <NUM>, in particular after the second switching member 33b. However, the signal conditioning unit <NUM> may also be provided between the second switching member 33b and the decimator unit <NUM> (as indicated by the dashed lines) or between the second switching member 33b and the digital down converter unit <NUM>.

In general, the signal conditioning unit <NUM> may comprise gain, offset, coupling, filtering and/or other signal conditioning functions on the input signals received and processed appropriately.

Moreover, the signal conditioning unit <NUM> may be a filter.

In <FIG>, the same schematic overview is shown for a signal analyzing circuit <NUM> comprising k channels <NUM> each having a respective digitizer <NUM>.

The digitizers <NUM> of each channel <NUM> are coupled to a common multiplexer unit <NUM> acting as the first switching member 33a of the switching unit <NUM>. The multiplexer unit <NUM> is assigned to several decimators <NUM>, in particular m decimators <NUM>, as well as several digital down converters <NUM>, in particular n digital down converters <NUM>.

As already indicated by the indices, the numbers of the channels <NUM>, the decimators <NUM> as well as the digital down converters <NUM> may be different.

In general, each decimator unit <NUM> assigned to a single channel <NUM> may have at least two decimators <NUM> as shown in <FIG>.

Thus, the switching unit <NUM> assigned to a single channel <NUM> may comprise a multiplexer unit <NUM> as it connects one input (from the respective digitizer <NUM>) with two outputs assigned to both decimators <NUM>.

In other words, the respective switching member 33a, 33b may be established each by a multiplexer unit <NUM>.

For instance, the decimators <NUM> are set to pass different bandwidths of the time-and-value-discrete signal obtained from the digitizer <NUM> via the switching unit <NUM>, in particular the first switching member 33a, such that two different decimated time-and-value-discrete signals are provided. This is depicted on the right side of <FIG> since the upper decimator <NUM> is set to a pass a signal with a higher bandwidth compared to the lower decimator <NUM>. Therefore, a zoom function is possible as shown in <FIG>.

Accordingly, the decimator unit <NUM> is configured to provide two decimated time-and-value-discrete signals that can be stored in the acquisition memory <NUM> having a different bandwidth or rather zoom factor.

The decimated time-and-value-discrete signals are directed via the second switching member 33b to the acquisition memory <NUM> in the respective operation mode as discussed with regard to the embodiment of <FIG>. The second switching member 33b is established by a multiplexer unit <NUM>, namely a second multiplexer unit <NUM>.

In a similar manner, each digital down converter unit <NUM> may have at least two digital down converters <NUM> as shown in <FIG>.

Thus, the first switching member 33a assigned to a single channel <NUM> may comprise or rather be established by a multiplexer unit <NUM> as it connects one input (from the respective digitizer <NUM>) with two outputs assigned to both digital down converters <NUM>. Hence, the digital down converter unit <NUM> assigned to a single channel <NUM> is configured to provide two down-converted time-and-value-discrete signals due to the two digital down converters <NUM> wherein both down-converted time-and-value-discrete signals are stored in the acquisition memory <NUM>.

As also indicated in <FIG>, the Fourier transform unit <NUM> is configured to process both down-converted time-and-value-discrete signals differently.

Accordingly, the signal analyzing circuit <NUM> provides a multi Fourier transform mode, for instance a multi Fast Fourier transform mode (Multi FFT Mode). This becomes also obvious in <FIG> due to the different frequencies assigned to both down-converted time-and-value-discrete signals transformed into two data sets assigned to the spectrum after the (Fast) Fourier transform.

In a similar manner with regard to <FIG>, the down-converted time-and-value-discrete signals are directed via the second switching member 33b to the acquisition memory <NUM> in the respective operation mode.

In <FIG> and <FIG>, a single channel <NUM> is illustrated that is assigned to a first switching member 33a being a multiplexer unit <NUM>.

Since the signal analyzing circuit <NUM> may comprise several channels <NUM> as shown in <FIG>, the several first multiplexer units <NUM>, acting as first switching members 33a, may be summarized in a common first multiplexer. The same applies for the several second multiplexer units <NUM> acting as second switching members 33b which may be summarized in a common second multiplexer.

In a similar manner, a common decimator unit <NUM> as well as a common digital down converter unit <NUM> may be provided being assigned to all channels <NUM>.

In general, the second switching members 33b for each channel <NUM> ensure that only one channel is connected to the acquisition memory <NUM>, in particular only one sub-channel assigned to the respective decimator <NUM> or down-converter <NUM>.

In <FIG>, an implementation of at least a major part of the signal analyzing circuit <NUM> is shown.

As shown in this embodiment, the common first and second multiplexers <NUM>, the decimator unit <NUM> and the digital down converter unit <NUM> are established by a first field programmable gate array (FPGA) <NUM>. Hence, the first FPGA <NUM> comprises the switching unit <NUM>. In fact, the switching unit <NUM> is established by the first FPGA <NUM>.

The (Fast) Fourier transform unit <NUM>, a processing unit <NUM> and a visualization unit <NUM> (that may be connected to the display <NUM> of the oscilloscope <NUM> shown in <FIG>) are established by a second field programmable gate array (FPGA) <NUM>.

In addition, the acquisition memory <NUM> is established by a random access memory (RAM), for instance a double data rate random access memory (DDR RAM) such as a DDR3 RAM.

The acquisition memory <NUM> is connected to the first FPGA <NUM> that in turn is connected to the second FPGA <NUM> so that a data connection between the second FPGA <NUM> and the acquisition memory <NUM> is ensured (via the first FPGA <NUM>). Alternatively, a direct connection between the second FPGA <NUM> and the acquisition memory <NUM> is provided.

In <FIG>, a schematic overview of a part of the signal analyzing circuit <NUM> according to an embodiment of the present disclosure is shown.

The four inputs <NUM> - <NUM> are assigned to four channels <NUM> each comprising a digitizer <NUM> illustrated by the analog to digital converters <NUM>. The samplers <NUM> are not shown for illustrative purposes.

The front end of each channel <NUM> comprises signal conditioning units <NUM>. These signal conditioning units <NUM> provide gain, offset, coupling, filtering and/or other signal conditioning functions on the input signals received.

Generally, the signal conditioning units <NUM> may be provided in each embodiment as shown in and already discussed with regard to <FIG>, for instance.

The digitizers <NUM> provide the respective time-and-vale-discrete signals of the analog input signals inputted at the inputs <NUM> - <NUM>.

The time-and-vale-discrete signals are forwarded to the first FPGA <NUM> comprising several units, in particular the multiplexer unit <NUM> with several acquisition control units <NUM>, the decimator unit(s) <NUM> as well as the digital down converter unit(s) <NUM> of the respective channels <NUM> which are illustrated in a simplified manner for illustrative purposes.

The several acquisition control units <NUM> assigned to the multiplexer unit <NUM> comprise pre-trigger, path delay compensation and post-trigger functions.

Moreover, a triggering system <NUM> and a memory packer unit <NUM> are illustrated wherein the memory packer unit <NUM> is connected with the acquisition memory <NUM>.

Moreover, deserializing and deskewing units <NUM> as well as interleaving and inversing units <NUM> are provided which are shown in more detail in <FIG> and <FIG>.

In addition thereto, a filter <NUM> (as a signal conditioning unit) is shown that is positioned after a respective analog to digital converter <NUM> as shown in <FIG> for the first channel. This may also apply in a similar manner for the other channels.

The switching unit <NUM> is not shown in detail for reasons of simplicity. However, the switching unit <NUM> may comprise two switching members 33a, 33b in a similar manner as discussed previously, in particular two switching members 33a, 33b established by first and second multiplexer units <NUM> positioned prior and after the respective decimator unit(s) <NUM> as well as the digital down converter unit(s) <NUM>.

In <FIG>, the interface of the signal analyzing circuit <NUM> with the front end is shown in more detail that illustrates the data flow from the digitizers <NUM> to the decimator unit <NUM>. In the embodiment shown in <FIG>, no interleaving is shown.

The respective first switching members 33a is not shown here for reasons of simplicity.

in <FIG>, the same illustration is provided showing the interface with an interleaved fourth channel <NUM>.

In <FIG>, the memory packer unit <NUM> is shown in more detail. Particularly, it is shown that the data of the frequency shifted time data path comprising the digital down converter unit <NUM> as well as the other path comprising the decimator unit <NUM> are assigned to a respective buffer <NUM>, <NUM>.

Both buffers <NUM>, <NUM> are checked by an arbiter <NUM> that controls a multiplexer unit <NUM> appropriately to forward the respective data to the memory controller <NUM> for being written to the acquisition memory <NUM>.

As already mentioned previously, the data processed by the memory packer unit <NUM> does not comprise any frequency domain signal even though the data processed by the frequency shifted time data path relates to data that will be stored in the acquisition memory <NUM> for being transformed afterwards.

In general, a method for auto setting the oscilloscope <NUM> shown in <FIG> can be provided appropriately using the signal analyzing circuit <NUM> shown in <FIG>, for instance.

Initially, the maximum frequency of an input signal is determined by analyzing the power of the respective signal above a predetermined noise threshold value in a spectrum view mode. Thus, the analog input signal is digitized into the time-and-value-discrete signal as described above wherein the time-and-value-discrete signal is forwarded via the first switching member 33a of the switching unit <NUM> towards the digital down-converter unit <NUM>.

The digital down-converter unit <NUM> may down-convert the time-and-value-discrete signal appropriately such that a down-converted time-and-value-discrete signal is obtained which is forwarded to the acquisition memory <NUM> via the second switching member 33b of the switching unit <NUM> and stored in the acquisition memory <NUM>.

In the respective operation mode, namely the spectrum view operation mode, both switching members 33a, 33b have the appropriate switch state ensuring the signal flow as described above. For this purpose, both switching members 33a, 33b, namely the switching unit <NUM>, are controlled appropriately, for instance by a separate processing unit or by themselves.

The (Fast) Fourier transform unit <NUM> accesses the acquisition memory <NUM> for transforming the down-converted time-and-value-discrete signal into data that can be analyzed appropriately with regard to the spectrum, in particular the maximum frequency of the input signal can be determined.

Then, the oscilloscope <NUM>, in particular the signal analyzing circuit <NUM>, is switched from the spectrum view operation mode to a time domain mode. Thus, the first switching member 33a of the switching unit <NUM> is switched such that the digitizer <NUM> of the respective channel <NUM> is connected to the decimator unit <NUM> which is set to the maximum frequency determined previously. Simultaneously, the digitizer <NUM> is no more coupled to the digital down-converter unit <NUM>.

In a similar manner, the second switching member 33b of the switching unit <NUM> is switched in its second switch state such that the decimator unit <NUM> is coupled to the acquisition memory <NUM> wherein the acquisition memory <NUM> is no more coupled to the digital down-converter unit <NUM>. Hence, the decimated time-and-value-discrete signal can be stored in the acquisition memory <NUM> in an optimized manner while being automatically set.

This auto setting method ensures that no aliasing effects occur since the decimator unit <NUM> is set appropriately due to the power analysis done previously.

As already mentioned, the oscilloscope <NUM> has several inputs <NUM> - <NUM> wherein the oscilloscope <NUM>, in particular the signal analyzing circuit <NUM>, is configured to provide data used for the spectrum view (spectrum view data) as well as time domain data of different signal sources simultaneously. This can be done by setting the switching unit <NUM> assigned to the first channel <NUM> into a first switch state whereas the switching unit <NUM> assigned to the second channel <NUM> into a second switch state, for instance.

The data obtained may be displayed on the display <NUM> (simultaneously) if set by the user of the oscilloscope <NUM> appropriately.

As two different signal sources are provided simultaneously with regard to the time domain and the spectrum view, the time domain settings remain the same when the user changes settings like center frequency or span which would affect time domain settings. These two analyses are clearly separated.

This clear separation also reduces the number of operation elements required, for instance graphical user interface operation elements such that the size of the display <NUM> can be minimized correspondingly.

In this embodiment, the switching unit <NUM> is established by a field-programmable gate array (FPGA), for instance the first FPGA <NUM>.

The FPGA <NUM> is positioned between the digitizer <NUM> and the acquisition memory <NUM> wherein the FPGA <NUM> comprises two different configurations that are shown in <FIG>.

In the first configuration, the FPGA <NUM> implements the decimator unit <NUM> (<FIG>) whereas the FPGA <NUM> implements the digital down converter unit <NUM> in the second configuration (<FIG>). Thus, the first configuration of the FPGA <NUM> corresponds to the second operation mode, namely the spectrum view mode, whereas the second configuration of the FPGA <NUM> corresponds to the first operation mode, namely the time domain mode.

In general, the FPGA <NUM> is adapted to implement either said decimator unit <NUM> or said digital down-converter unit <NUM> selectively depending on the operation mode.

Thus, the switching unit <NUM> is adapted to selectively activate either said decimator unit <NUM>, in the time-domain operation mode, or said digital down-converter unit <NUM>, in the spectrum view operation mode.

In a similar manner with regard to the previous embodiments, the acquisition memory <NUM> is coupled to said decimator unit <NUM> or rather said digital down converter unit <NUM>.

In said time-domain operation mode (second configuration of the FPGA <NUM>), the acquisition memory <NUM> is coupled to said decimator unit <NUM> to store said decimated time-and-value-discrete signal wherein said acquisition memory <NUM> is not coupled to said digital down converter unit <NUM> as it is not implemented.

In said spectrum view operation mode (first configuration of the FPGA <NUM>), the acquisition memory <NUM> is coupled to said digital down converter unit <NUM> to store said down-converted time-and-value-discrete signal wherein said acquisition memory <NUM> is not coupled to said decimator unit <NUM> as it is not implemented.

Hence, the resources needed by the FPGA <NUM> can be reduced appropriately as only either said decimator unit <NUM> or said digital down converter unit <NUM> is operated at a certain time since only one of both is implemented or rather activated for signal processing.

In <FIG>, a third embodiment of the signal analyzing circuit <NUM> is shown, which third embodiment is not encompassed by the wording of the claims but is considered useful for understanding the invention.

Three different channels <NUM> are shown that each comprise a digitizer <NUM> configured to digitize an input signal into a time-and-value-discrete signal. The three different channels <NUM> are connected to a respective decimator unit <NUM> that is coupled to the respective digitizer <NUM> of each channel <NUM> to decimate said time-and-vale-discrete signal to a decimated time-and-value-discrete signal.

The decimated time-and-value-discrete signal of each channel <NUM> is then forwarded to a first acquisition memory <NUM> that might be provided by a random access memory, in particular in a similar manner as the acquisition memory shown in the previous embodiments.

In the first acquisition memory <NUM>, the decimated time-and-value-discrete signal or the associated data is stored.

As shown in <FIG>, a single digital down converter unit <NUM> is provided that is connected to said first acquisition memory <NUM> for accessing the decimated time-and-value-discrete signal of at least one channel <NUM> in order to down-convert said decimated time-and-value-discrete signal to a down-converted and decimated time-and-value-discrete signal.

The single digital down converter unit <NUM> is assigned to the first acquisition memory <NUM> via switching unit <NUM>, in particular a multiplexer.

The down-converted and decimated time-and-value-discrete signal provided by the single digital down converter unit <NUM> is then forwarded to a second acquisition memory <NUM> and stored therein for being processed by a (F)FT unit <NUM>. Thus, the FFT unit <NUM> is configured to convert said down-converted and decimated time-and-value-discrete signal into data used for spectrum analysis.

In the shown embodiment, the switching unit <NUM>, in particular the multiplexer, ensure that only the decimated time-and-value-discrete signal assigned to the first channel <NUM> (bold line) is forwarded to the single digital down converter unit <NUM> for being processed further, in particular being down-converted and stored as a down-converted and decimated time-and-value-discrete signal in the second acquisition memory <NUM>.

In this embodiment, the digital down converter unit <NUM> is provided after the first acquisition memory <NUM> in which the decimated time-and-value-discrete signals are stored for being acquired when providing data in the time domain.

For providing data of an input channel <NUM> in the spectrum view operation mode, the respective signal, being decimated previously, is read out of the acquisition memory <NUM> and down-converted by the digital down converter unit <NUM> and then stored in the second acquisition memory <NUM> that can be accessed by the (F)FT unit <NUM> for generating the respective data used for spectrum analysis.

Claim 1:
A signal analyzing circuit (<NUM>) with at least a first channel (<NUM>), said first channel (<NUM>) comprising:
- a digitizer (<NUM>) configured to digitize an input signal into a time-and-value-discrete signal;
- a decimator unit (<NUM>);
- a digital down converter unit (<NUM>); and
- an acquisition memory (<NUM>),
characterized in that
said first channel (<NUM>) further comprises a switching unit (<NUM>),
wherein the switching unit (<NUM>) is coupled to the digitizer (<NUM>), said switching unit (<NUM>) being adapted to receive said time-and-value-discrete signal;
wherein the switching unit (<NUM>) is coupled to said acquisition memory (<NUM>); and
wherein said switching unit (<NUM>) is adapted to connect said acquisition memory (<NUM>) with either said decimator unit (<NUM>) or said digital down converter unit (<NUM>) such that said switching unit (<NUM>) is adapted to selectively:
activate said decimator unit (<NUM>) in a time-domain operation mode, said decimator unit (<NUM>) decimating said time-and-vale-discrete signal to a decimated time-and-value-discrete signal, wherein said acquisition memory (<NUM>) is coupled to said decimator unit (<NUM>) in said time-domain operation mode to store said decimated time-and-value-discrete signal, said acquisition memory (<NUM>) being not coupled to said digital down converter unit (<NUM>) in said time-domain operation mode, or
activate said digital down converter unit (<NUM>) in a spectrum view operation mode, said digital down converter unit (<NUM>) down-converting said time-and-value-discrete signal to a down-converted time-and-value-discrete signal, wherein said acquisition memory (<NUM>) is coupled to said digital down converter unit (<NUM>) in said spectrum view operation mode to store said down-converted time-and-value-discrete signal, said acquisition memory (<NUM>) being not coupled to said decimator unit (<NUM>) in said spectrum view operation mode.