Patent Description:
<CIT> describes a LIDAR sensor including a photodetector. The anode of the photodetector can be measured directly providing a signal, and is further connected to a downstream resistor and a downstream diode in parallel. <CIT> describes a flash LIDAR system and a corresponding method for its operation. The system includes a light detector array, each comprising a photodiode, a multiplexer and a trans-impedance amplifier. <CIT> describes a system and method for operating a high dynamic range LIDAR receiver. The system includes a trans-impedance amplifier to convert a current into a voltage, and a clipping circuit configured to limit a maximum value of an input voltage.

According to one aspect of the disclosure, a light detection and ranging (LIDAR) sensor includes an optical pulsed transmitter and an optical receiver. The receiver includes a plurality of pixels. Each pixel includes a receiver circuit. Each receiver circuit includes a photosensitive input circuit having at least two terminals, wherein a first terminal is coupled to a detector voltage supply and a second terminal is coupled to a pulse voltage node. Each receiver includes a logarithmic-signal circuit including at least one PN junction, wherein the P-type terminal is coupled to the pulse voltage node and the N-type terminal is coupled to a constant potential.

The LIDAR sensor includes an impedance-reducing circuit electrically coupled to the photosensitive input circuit and to the logarithmic-signal circuit, the impedance-reducing circuit including at least a common-gate transistor coupled to the pulse voltage node. The impedance-reducing circuit includes a bias transistor wherein the bias transistor provides DC bias current to the common-gate transistor. The LIDAR sensor may include a common-mode noise-rejection circuit that includes a capacitor coupled between the gate of the common-gate transistor and the detector voltage supply and adapted to reject common-mode noise on the detector voltage supply. The common-mode noise-rejection circuit may include a selectively-actuatable switch coupled between the gate of the common-gate transistor and a reference voltage, wherein the switch is in a closed position, when no photocurrent pulse is expected and wherein the switch is in an open position, when a photocurrent pulse is expected. The LIDAR sensor may include a bypass circuit electrically coupled to the logarithmic-signal circuit and including at least a bypass transistor having a terminal coupled to the pulse voltage node, wherein, the bypass circuit is adapted to reduce the bias current delivered to the logarithmic-signal circuit. The LIDAR sensor may include a servo loop circuit including an amplifier having a first and a second input and an output, wherein the first amplifier input is coupled to the pulse voltage node, the second amplifier input is a reference voltage, and the amplifier output is coupled to the gate of the bypass transistor of the bypass circuit and adapted to control the current at the logarithmic-signal circuit. The LIDAR sensor may include a servo loop circuit including an amplifier having a first and a second input and an output, wherein the first amplifier input is coupled to the pulse voltage node, the second amplifier input is a reference voltage, and the amplifier output is coupled to the gate of the bias transistor of the impedance-reducing circuit.

The LIDAR sensor may include a linear-signal circuit including a resistor coupled between the pulse voltage node and a constant potential. The LIDAR sensor may include a square-root-signal circuit including a transistor including a first terminal coupled to the pulse voltage node and a second terminal coupled to a constant potential. The source of the transistor of the square-root-signal circuit may be coupled to the pulse voltage node, the drain of the transistor may be coupled to a constant potential, and the gate of the transistor may be coupled to a control voltage. A photocurrent may predominantly flow: through the linear-signal circuit when the photocurrent is less than a first threshold; through the square-root-signal circuit when the photocurrent is greater than the first threshold and less than a second threshold; and through the logarithmic-signal circuit when the photocurrent is greater than the second threshold.

The LIDAR sensor may include an analog memory circuit coupled to the pulse voltage node, wherein the analog memory circuit includes a plurality of sequentially selected capacitive circuits which store voltage samples of a return pulse received by the photosensitive input circuit, wherein each of the plurality of sequentially selected capacitive circuits is readable by a computer.

The LIDAR sensor may include an adjustable low-pass filter circuit coupled to the pulse voltage node, wherein the bandwidth of the filter circuit is adjusted by a computer control output. The bandwidth of the filter circuit may be varied by adjusting a resistance value.

The LIDAR sensor may include a computer including a digital processor and digital memory storing instructions executable by the digital processor to determine a range associated with a return pulse by: selecting and actuating each of a plurality of capacitive circuits, wherein the plurality of capacitive circuits is coupled to the photosensitive input circuit via the pulse voltage node; and wherein the actuation includes moving a switch from an open position to a closed position and to the open position again; and thereafter, reading a voltage stored in each of the capacitive circuits.

The LIDAR sensor may include a common-mode noise-rejection circuit that includes a capacitor coupled between the gate of the common-gate transistor and the detector voltage supply and adapted to reject common-mode noise on the detector voltage supply.

The LIDAR sensor may include a servo loop circuit including an amplifier having a first and a second input and an output, wherein the first amplifier input is coupled to the pulse voltage node, the second amplifier input is a reference voltage, and the amplifier output is coupled to the gate of the bias transistor of the impedance-reducing circuit.

The LIDAR sensor may include a current pulse injection circuit coupled to the pulse voltage node, wherein the current pulse injection circuit is adapted to provide a test of functionality or performance.

According to the at least one example, a computer is disclosed that is programmed to execute any combination of the examples set forth above.

According to the at least one example, a computer is disclosed that is programmed to execute any combination of the examples of the method(s) set forth above.

According to the at least one example, a computer program product is disclosed that includes a computer readable medium storing instructions executable by a computer processor, wherein the instructions include any combination of the instruction examples set forth above.

According to the at least one example, a computer program product is disclosed that includes a computer readable medium that stores instructions executable by a computer processor, wherein the instructions include any combination of the examples of the method(s) set forth above.

Various examples of a receiver circuit for a sensor are described. According to a non-limiting example, the sensor is a light detection and ranging (LIDAR) sensor; accordingly, the receiver circuit thereof receives and processes reflected light pulses emitted by the sensor so that a range between the sensor and an object may be determined. The examples of the receiver circuit improve the dynamic range of the receiver thereby allowing accurate range determination over a wide range of incident optical power.

In the present context and throughout the specification, "coupled to" means "electrically coupled directly to" or "electrically coupled indirectly to. " "Electrically coupled directly to" means that given two electrical components, there are no electrical components therebetween-only electrical conductors, e.g., wires, traces, etc. And "electrically coupled indirectly to" means that given two electrical components, an electrical path exists between the two electrical components wherein one or more electrical components, e.g., resistor, switch, transistor, etc., may be connected along the path and therebetween.

<FIG> is a schematic view of an example vehicle <NUM> and an object <NUM>. The vehicle <NUM> shown in the <FIG> is a passenger automobile comprising at least one computer <NUM> and an object detection sensor <NUM>; collectively used to detect the object <NUM>. However, as other examples, the vehicle <NUM> may be of any suitable manned or unmanned vehicle including a truck, motorcycle, plane, satellite, drone, watercraft, robot, etc. The object <NUM> may be a moving or stationary object such as another vehicle, pedestrian, vegetation, building, etc., located outside the vehicle <NUM>.

The computer <NUM> may include any suitable computing device programmed to operate the sensor <NUM> and/or other vehicle components. In at least one example, computer <NUM> includes a processor <NUM> and memory <NUM>. The processor <NUM> and the memory <NUM> are digital. Non-limiting examples of processor <NUM> include a microprocessor, a microcontroller or controller, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), one or more electrical circuits comprising discrete digital and/or analog electronic components arranged to perform predetermined tasks or instructions, etc..

Memory <NUM> may include any non-transitory computer usable or readable medium, which may include one or more storage devices or articles. Exemplary non-transitory computer usable storage devices include conventional hard disk, solid-state memory, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), as well as any other volatile or non-volatile media. Non-volatile media include, for example, optical or magnetic disks and other persistent memory, and volatile media, for example, also may include dynamic random-access memory (DRAM). These storage devices are non-limiting examples; e.g., other forms of computer-readable media exist and include magnetic media, compact disc ROM (CD-ROMs), digital video disc (DVDs), other optical media, any suitable memory chip or cartridge, or any other medium from which a computer can read. In general, memory <NUM> may store one or more computer program products which may be embodied as software, firmware, or other programming instructions executable by the processor <NUM>.

Computer <NUM> may include other hardware elements (not shown) such as an analog-to-digital converter (ADC), digital-to-analog converter (DAC) and one or more discrete circuits for controlling or otherwise enabling various switches or the like in electronic circuits of sensor <NUM>. In one example, the sensor <NUM> may include the computer <NUM>, e.g., the computer <NUM> physically located within a housing of sensor <NUM>. In another example, the computer <NUM> may be a component distinct from the sensor <NUM> and located at any suitable location in the vehicle <NUM>.

While not portrayed in the illustrations, sensor <NUM> and computer <NUM> may be communicatively coupled via any suitable wired and/or wireless communication network (e.g., in vehicle <NUM>)-e.g., permitting computer <NUM> to send and/or receive instructions and/or data between it, vehicle <NUM> components, and/or sensor <NUM>.

<FIG> is a system block diagram showing the relationship and connections of the major functional blocks of the vehicle electrical systems and central processing unit (CPU) with the LIDAR sensor system. A LIDAR system controller <NUM> communicates with all of the LIDAR sensors <NUM> mounted on the vehicle <NUM>. In an example installation, two long-range units, LRU <NUM><NUM> and LRU <NUM><NUM> connect to LIDAR system controller <NUM> through a set of bidirectional electrical connections <NUM>. The electrical connections may also have an optical waveguide and optical transmitters and receivers to transfer data, control, and status signals bidirectionally between long-range LIDAR sensors <NUM>, <NUM> and LIDAR system controller <NUM>. LIDAR system controller <NUM> also communicates with the four short-range units, SRU <NUM><NUM>, SRU <NUM><NUM>, SRU3 <NUM>, and SRU4 <NUM>, each through a set of bidirectional electrical connections <NUM>. The electrical connections may also have an optical waveguide and optical transmitters and receivers to transfer data, control, and status signals bidirectionally between short-range LIDAR sensors <NUM>-<NUM> and LIDAR system controller <NUM>. Each of the LIDAR sensors may include data processors to reduce the processing load; for example, developing the point cloud and isolating/segmenting objects in the field of view and object speed from the point cloud. Conventional 2D visible light or infrared viewing cameras <NUM> may be embedded within the LIDAR sensor subsystem and may be part of a sub-assembly containing a LIDAR sensor. These cameras <NUM> may share the same connections <NUM> or <NUM> to the LIDAR system controller <NUM>. A number (n) of other visible light 2D still or video cameras <NUM> may connect directly to the vehicle collision processor <NUM> and produce scene data complementary to the 3D data generated by the various LIDAR sensors mounted to the vehicle. The 2D still or video cameras <NUM> may also operate at either visible or infrared wavelengths. The fields of view of the 2D still or video cameras <NUM> may be designed to overlap the fields of view of the LIDAR sensors (<NUM>, <NUM>, and <NUM>-<NUM>) installed on the vehicle <NUM>. Bidirectional electrical connections <NUM> also serve to transfer 3D data maps, status, and control signals between LIDAR system controller <NUM> and the vehicle electrical systems and central processing unit (CPU) <NUM>. At the core of the vehicle <NUM>, an electronic brain may control all functioning of the vehicle <NUM>, and typically controls all other subsystems and co-processors. The electronic brain, or central processing unit (CPU <NUM>) is here lumped together with the basic electrical systems of the vehicle, including battery, headlights, wiring harness, etc. Additionally or alternatively, computer <NUM>, as shown in <FIG> is a central computer of the vehicle <NUM>. The vehicle suspension system <NUM> receives control commands and returns status through bidirectional electrical connections, and is capable of modifying the ride height, spring rate, and damping rate of each of the vehicle's wheels independently. An inertial reference <NUM> also has a vertical reference, or gravity sensor as an input to the CPU <NUM>. A global positioning system (GPS) reference <NUM> may also be connected to the vehicle CPU <NUM>. The GPS reference <NUM> may also have a database of all available roads and conditions in the area which may be updated periodically through a wireless link. A duplex radio link <NUM> may also be connected to CPU <NUM> and may communicate directly with other vehicles in close range, sharing position, speed, direction, and vehicle specific information to facilitate collision avoidance and the free flow of traffic. The duplex radio link may also receive local positional references, road data, weather conditions, and other information important to the operations of the vehicle <NUM> from a central road conditions database through roadside antennas or cellular stations. The vehicle <NUM> may also provide vehicle status and road conditions updates to the central road conditions database via radio uplink <NUM>, allowing the central road conditions database to be augmented by any and all vehicles which are equipped with LIDAR sensors and a radio link <NUM>. A collision processor and airbag control unit (ACU) <NUM> connects bidirectionally to CPU <NUM> as well, receiving inputs from a number of accelerometers, brake sensors, wheel rotational sensors, LIDAR sensors, etc. ACU <NUM> makes decisions on the timing and deployment of airbags and other restraints. Though the system of <FIG> is shown with the vehicle <NUM> on which the system is nominally installed, and which is typically an automobile, the system, and any of the described components and subsystems are designed to be installed on any number of moving vehicles which may be actively piloted, semi-autonomously navigated, or fully autonomously steered and controlled, and which may be manned or unmanned, including planes, trains, automobiles, motorcycles, helicopters, boats, ships, spacecraft, hovercraft, airships, jeeps, trucks, robotic crawlers, gliders, utility vehicles, street sweepers, submersibles, amphibious vehicles, and sleds.

<FIG> is a block diagram of a LIDAR sensor which describes both long-range LIDAR sensors <NUM>, <NUM> and short-range LIDAR sensors <NUM>-<NUM> typical of the preferred embodiment. Adaptations of the pulsed laser transmitter <NUM>, transmit optics <NUM>, receive optics <NUM>, and in some cases, programmable changes to the sampling circuitry of readout integrated circuit <NUM> may be effected to provide range enhancement, wider or narrower field of view, and reduced size and cost. The first embodiment provides a <NUM> X <NUM> or <NUM> X <NUM> detector array <NUM> of light detecting elements situated on a single insulating sapphire substrate which is stacked atop a readout integrated circuit <NUM> using a hybrid assembly method. In other embodiments of the design, M X N focal plane arrays of light detecting elements with M and N having values from <NUM> to <NUM> and greater are anticipated. The functional elements depicted in <FIG> may first be described with respect to the elements of a typical long-range LIDAR sensor <NUM>. A control processor <NUM> controls the functions of the major components of the LIDAR sensor <NUM>. Control processor <NUM> connects to pulsed laser transmitter <NUM> through bidirectional electrical connections (with interface logic, analog to digital (A/D) and digital to analog (D/A) converters <NUM>) which transfer commands from control processor <NUM> to pulsed laser transmitter <NUM> and return monitoring signals from pulsed laser transmitter <NUM> to the control processor <NUM>. The interface logic, including analog to digital (A/D) and digital to analog (D/A) converters <NUM>, may reside completely or in part on the readout integrated circuit <NUM>. A light sensitive diode detector (Flash Detector) <NUM> is placed at the back facet of the laser so as to intercept a portion of the laser light pulse produced by the pulsed laser transmitter <NUM>. An optical sample of the outbound laser pulse taken from the front facet of pulsed laser transmitter <NUM> is routed to a corner of the detector array <NUM> as an automatic range correction (ARC) signal, typically over a fiber optic cable. The pulsed laser transmitter <NUM> may be a solid-state laser, monoblock laser, semiconductor laser, fiber laser, or an array of semiconductor lasers. It may also employ more than one individual laser to increase the data rate. In a preferred embodiment, pulsed laser transmitter <NUM> is an array of vertical cavity surface emitting lasers (VCSELs). In an alternative embodiment, pulsed laser transmitter <NUM> is a disc-shaped solid-state laser of erbium-doped phosphate glass pumped by <NUM> nanometer semiconductor laser light.

In operation, the control processor <NUM> initiates a laser illuminating pulse by sending a logic command or modulation signal to pulsed laser transmitter <NUM>, which responds by transmitting an intense burst of laser light through transmit filter <NUM> and transmit optics <NUM>. In the case of a Q-switched solid-state laser based on erbium glass, neodymium-YAG, or other solid-state gain medium, a simple bi-level logic command may start the pump laser diodes emitting into the gain medium for a period of time which will eventually result in a single flash of the pulsed laser transmitter <NUM>. In the case of a semiconductor laser which is electrically pumped, and may be modulated instantaneously by modulation of the current signal injected into the laser diode, a modulation signal of a more general nature is possible, and may be used with major beneficial effect. The modulation signal may be a flat-topped square or trapezoidal pulse, or a Gaussian pulse, or a sequence of pulses. The modulation signal may also be a sinewave, gated or pulsed sinewave, chirped sinewave, or a frequency-modulated (FM) sinewave, or an amplitude-modulated (AM) sinewave, or a pulse-width-modulated (PWM) series of pulses. The modulation signal is typically stored in on-chip memory <NUM> as a lookup table of digital memory words representative of analog values; this lookup table is read out in sequence by control processor <NUM> and converted to analog values by an onboard digital-to-analog (D/A) converter <NUM>, and passed to the pulsed laser transmitter <NUM> driver circuit. The combination of a lookup table stored in memory <NUM> and a D/A converter, along with the necessary logic circuits, clocks, and timers <NUM> resident on control processor <NUM>, together comprise an arbitrary waveform generator (AWG) circuit block. The AWG circuit block may alternatively be embedded within a laser driver as a part of pulsed laser transmitter <NUM>. Transmit optics <NUM> diffuse the high-intensity spot produced by pulsed laser transmitter <NUM> substantially uniformly over the desired field of view to be imaged by the LIDAR sensor <NUM>. Transmit filter <NUM> acts to constrain the laser light output to the design wavelength, removing any spurious emissions outside the design wavelength of the pulsed laser transmitter <NUM>. An optical sample of the transmitted laser pulse, (termed an ARC signal) is also sent to the detector array <NUM> via optical fiber. A few pixels in a corner of detector array <NUM> are illuminated with the ARC signal, which establishes a zero time reference for the timing circuits in the readout integrated circuit (ROIC) <NUM>. Each unit cell of the readout integrated circuit <NUM> has an associated timing circuit which is started counting by an electrical pulse derived from the ARC signal. Alternatively, the flash detector <NUM> signal may be used as a zero reference in a second timing mode. Though the ARC signal neatly removes some of the variable delays associated with transit time through the detector array <NUM>, this results in additional cost and complexity. Given digital representations of the image frames, the same task may be handled in software/firmware by a capable embedded processor such as data reduction processor <NUM>. When some portion of the transmitted laser pulse is reflected from a feature in the scene in the field of view of the LIDAR sensor <NUM>, it may be incident upon receive optics <NUM>, typically comprising the lens of a headlamp assembly and an array of microlenses atop detector array <NUM>. Alternative embodiments use enhanced detectors which may not require the use of microlenses. Other alternative embodiments of receive optics <NUM> employ diffractive arrays to collect and channel the incoming light to the individual elements of detector array <NUM>. Pulsed laser light reflected from a feature in the scene in the field of view of receive optics <NUM> is collected, filtered through receive filter <NUM>, and focused onto an individual detector element of the detector array <NUM>. This reflected laser light optical signal is then detected by the affected detector element and converted into an electrical current pulse which is then amplified by an associated unit cell electrical circuit of the readout integrated circuit <NUM>, and the time of flight measured. Thus, the range to each reflective feature in the scene in the field of view is measurable by the LIDAR sensor <NUM>. Transmit optics <NUM> consisting of a spherical lens, cylindrical lens, holographic diffuser, diffractive grating array, or microlens array condition the output beam of the pulsed laser transmitter <NUM> into a proper conical, elliptical, or rectangular shaped beam for illuminating a central section of a scene or objects in the path of vehicle <NUM>, as illustrated in <FIG>.

Continuing with <FIG>, receive optics <NUM> may be a convex lens, spherical lens, cylindrical lens or diffractive grating array. Receive optics <NUM> collect the light reflected from the scene and focus the collected light on the detector array <NUM>. Receive filter <NUM> restricts the incoming light to the proper wavelength band associated with the transmitter of the same LIDAR sensor <NUM>. In a preferred embodiment, detector array <NUM> is formed in a thin film of indium gallium arsenide deposited epitaxially atop an indium phosphide semiconducting substrate. Typically, detector array <NUM> would have a set of cathode contacts exposed to the light and a set of anode contacts electrically connected to the supporting readout integrated circuit <NUM> through a number of indium bumps deposited on the detector array <NUM>. The cathode contacts of the individual detectors of detector array <NUM> would then be connected to a high-voltage detector bias grid on the illuminated side of the array. Each anode contact of the detector elements of detector array <NUM> is thus independently connected to an input of a unit cell electronic circuit of readout integrated circuit <NUM>. This traditional hybrid assembly of detector array <NUM> and readout integrated circuit <NUM> may still be used, but new technology may reduce inter-element coupling, or crosstalk, and reduce leakage (dark) current and improve efficiency of the individual detector elements of detector array <NUM>. In a preferred embodiment, the elements of detector array <NUM> may be formed atop a substantially monocrystalline sapphire wafer. Silicon-on-sapphire (SOS) substrates with a thin layer of substantially monocrystalline silicon grown epitaxially thereon are available in the marketplace, and are well known for their superior performance characteristics. Germanium and silicon-germanium detectors are also compatible with monolithic silicon integrated circuit processes and may alternatively be employed. A detector array <NUM> of APD, PIN, or PN junction detectors may be formed of a sequence of layers of p-type and n-type silicon via epitaxial regrowth on the SOS wafers. Boron and aluminum may be used as dopants for any of the p-type silicon epitaxial layers. Phosphorus, arsenic, and antimony may be used as dopants for any of the n-type silicon epitaxial layers. Sapphire substrates with a thin layer of epitaxially grown monocrystalline gallium nitride are also available in the marketplace (gallium nitride on sapphire, or GNOS), and are widely known as substrates well suited to the fabrication of high brightness blue LEDs. A detector array <NUM> of APD, PIN, or PN junction detectors may be formed of a sequence of layers of p-type and n-type gallium nitride (GaN) or indium gallium nitride (InGaN) via epitaxial regrowth on the GNOS wafers. Silicon and germanium may be used as dopants for any of the n-type GaN layers. In some cases, magnesium may be used as a dopant for p-type layers in GaN. In a further development, detector array <NUM> may be fabricated monolithically directly atop readout IC <NUM>. Detector array <NUM> may also be formed in a more conventional manner from compounds of indium gallium arsenide, indium aluminum arsenide, silicon carbide, diamond, mercury cadmium telluride, zinc selenide, or other well-known semiconductor detector materials. Readout integrated circuit <NUM> comprises a rectangular array of unit cell electrical circuits. Each unit cell or pixel has the capability of receiving a photocurrent pulse generated by an optoelectronic detector element of detector array <NUM>, converting this photocurrent pulse into a voltage pulse and sampling this voltage pulse. Typically, the unit cell is also capable of detecting the presence of an electrical pulse associated with a light pulse reflected from the scene and intercepted by the detector element of detector array <NUM>. The detector array <NUM> may be an array of avalanche photodiodes, capable of photoelectron amplification, and modulated by an incident light signal at the design wavelength. The detector array <NUM> elements may also be a P-intrinsic-N design or N-intrinsic-P design with the dominant carrier being holes or electrons, respectively; in which case the corresponding ROIC <NUM> would have the polarity of the bias voltages and amplifier inputs adjusted accordingly. The hybrid assembly of detector array <NUM> and readout integrated circuit <NUM> of the preferred embodiment is mounted to a supporting circuit assembly, typically on a FR-<NUM> substrate or ceramic substrate. The circuit assembly typically provides support circuitry which supplies conditioned power, a reference clock signal, calibration constants, and selection inputs for the readout column and row, among other support functions, while receiving and registering range and intensity outputs from the readout integrated circuit <NUM> for the individual elements of the detector array <NUM>. Many of these support functions may be implemented in Reduced Instruction Set Computer (RISC) processors which reside on the same circuit substrate. A detector bias converter circuit <NUM> applies a time-varying detector bias to the detector array <NUM> which provides optimum detector bias levels to reduce the hazards of saturation in the near field of view of detector array <NUM>, while maximizing the potential for detection of distant objects in the field of view of detector array <NUM>. The contour of the time-varying detector bias supplied by detector bias converter <NUM> is formulated by control processor <NUM> based on feedback from the data reduction processor <NUM>, indicating the reflectivity and distance of objects or points in the scene in the field of view of the detector array <NUM>. Control processor <NUM> also provides several clock and timing signals from a timing core <NUM> to readout integrated circuit <NUM>, data reduction processor <NUM>, analog-to-digital converters <NUM>, object tracking processor <NUM>, and their associated memories. Control processor <NUM> relies on a temperature-stabilized or temperature-compensated frequency reference <NUM> to generate a variety of clocks and timing signals. Temperature-stabilized frequency reference <NUM> may be a temperature-compensated crystal oscillator (TCXO), dielectric resonator oscillator (DRO), or surface acoustic wave device (SAW). Timing core <NUM> resident on control processor <NUM> may include a high-frequency tunable oscillator, programmable pre-scaler dividers, phase comparators, and error amplifiers.

Continuing with <FIG>, control processor <NUM>, data reduction processor <NUM>, and object tracking processor <NUM> each have an associated memory for storing programs, data, constants, and the results of operations and calculations. These memories, each associated with a companion digital processor, may include ROM, EPROM, or other non-volatile memory such as flash. They may also include a volatile memory such as SRAM or DRAM, and both volatile and non-volatile memory may be integrated into each of the respective processors. A common frame memory <NUM> serves to hold a number of frames, each frame being the image resulting from a single laser transmission sequence. A laser transmission sequence may be a single pulse, or a sequence of pulses, depending on the laser type employed. The operational mode in a preferred embodiment using a single laser illuminating pulse is described in this section. Both data reduction processor <NUM> and object tracking processor <NUM> may perform 3D image processing to reduce the load on a scene processing unit (not shown)normally associated with LIDAR system controller <NUM>. There are two modes of data collection, the first being SULAR, or a progressive scan in depth. Each laser pulse typically results in <NUM> "slices" of data, similar to a CAT scan, and each "slice" may be stored as a single page in the common frame memory <NUM>. With each pixel sampling at a <NUM> nanosecond interval, the slices are each a layer of the image space at roughly <NUM> foot differences in depth. The <NUM> slices represent a frame of data, and the sampling for a succeeding laser pulse may be started at <NUM> feet further in depth, so that the entire image space up to <NUM> feet in range or depth may be swept out in a succession of <NUM> laser pulses. In some cases, the frame memory may be large enough to hold all <NUM> frames of data. The number of slices stored could be enough to map out any relevant distance, with no trigger mode operation required. The reduction of the data might then take place in an external computer, as in the case of data taken to map an underwater surface, or a forest with tree cover, or any static landscape, where sophisticated post-processing techniques in software may yield superior accuracy or resolution. A second data acquisition mode is the TRIGGER mode, where the individual pixels each look for a pulse response, and upon a certain pulse threshold criteria being met, the <NUM> analog samples bracketing the pulse time of arrival are retained in the pixel analog memories, and a running digital counter is frozen with a nominal range measurement. The <NUM> analog samples are output from each pixel through the "A" and "B" outputs <NUM> of readout integrated circuit <NUM>. The "A" and "B" outputs <NUM> are analog outputs, and the analog samples presented there are converted to digital values by the dual-channel analog-to-digital (A/D) converter <NUM>. Larger detector arrays <NUM> and readout ICs <NUM> may have more than two analog outputs. The digital outputs <NUM> of the A/D converters <NUM> connect to the inputs of the data reduction processor <NUM>. A/D converters <NUM> may also be integrated into readout integrated circuit <NUM>. The digital outputs are typically <NUM>- or <NUM>-bit digital representations of the uncorrected analog samples measured at each pixel of the readout IC <NUM>, but other representations with greater or fewer bits may be used, depending on the application. The rate of the digital outputs depends upon the frame rate and number of pixels in the array. In TRIGGER mode, a great deal of data reduction has already transpired, since the entire range or depth space may be swept out in the timeframe of a single laser pulse, and the data reduction processor <NUM> would only operate on the <NUM> analog samples stored in each unit cell in order to refine the nominal range measurement received from each pixel (unit cell) of the array. The data reduction processor <NUM> refines the nominal range measurements received from each pixel by curve fitting of the analog samples to the shape of the outgoing laser illuminating pulse, which is preserved by the reference ARC pulse signal. These pulses are typically Gaussian, but may be square, trapezoidal, haversine, sine function, etc., and the fitting algorithms may employ Fourier analysis, Least Squares analysis, or fitting to polynomials, exponentials, etc. The range measurements may also be refined by curve fitting to a well-known reference pulse characteristic shape. In TRIGGER acquisition mode, the frame memory <NUM> only needs to hold a "point cloud" image for each illuminating laser pulse. The term "point cloud" refers to an image created by the range and intensity of the reflected light pulse as detected by each pixel of the pixel array. In TRIGGER mode, the data reduction processor <NUM> serves mostly to refine the range and intensity (R&I) measurements made by each pixel prior to passing the R&I data to the frame memory <NUM> over data bus <NUM>, and no "slice" data or analog samples are retained in memory independently of the R&I "point cloud" data in this acquisition mode. Frame memory <NUM> provides individual or multiple frames, or full point cloud images, to control processor <NUM> over data bus <NUM>, and to an optional object tracking processor <NUM> over data bus <NUM> as required.

Referring to <FIG>, data reduction processor <NUM> and control processor <NUM> may be of the same type, a reduced instruction set (RISC) digital processor with hardware implementation of integer and floating-point arithmetic units. Object tracking processor <NUM> may also be of the same type as RISC processors <NUM> and <NUM>, but may in some cases be a processor with greater capability, suitable for highly complex graphical processing. Object tracking processor <NUM> may have, in addition to hardware implemented integer and floating-point arithmetic units, a number of hardware implemented matrix arithmetic functions, including but not limited to; matrix determinant, matrix multiplication, and matrix inversion. In operation, the control processor <NUM> controls readout integrated circuit <NUM>, A/D converters <NUM>, frame memory <NUM>, data reduction processor <NUM> and object tracking processor <NUM> through a bidirectional control bus <NUM> which allows for the control processor <NUM> to pass commands on a priority basis to the dependent peripheral blocks; readout IC <NUM>, A/D converters <NUM>, frame memory <NUM>, data reduction processor <NUM>, and object tracking processor <NUM>. Bidirectional control bus <NUM> also serves to return status and process parameter data to control processor <NUM> from readout IC <NUM>, A/D converters <NUM>, frame memory <NUM>, data reduction processor <NUM>, and object tracking processor <NUM>. Data reduction processor <NUM> refines the nominal range data and adjusts each pixel intensity data developed from the digitized analog samples received from A/D converters <NUM>, and outputs a full image frame via unidirectional data bus <NUM> to frame memory <NUM>, which is a dual-port memory having the capacity of holding several frames to several thousands of frames, depending on the application. Object tracking processor <NUM> has internal memory with sufficient capacity to hold multiple frames of image data, allowing for multi-frame synthesis processes, including video compression, single-frame or multi-frame resolution enhancement, statistical processing, and object identification and tracking. The outputs of object tracking processor <NUM> are transmitted through unidirectional data bus <NUM> to a communications port <NUM>, which may be resident on control processor <NUM>. All slice data, range and intensity data, control, and communications then pass between communications port <NUM> and a centralized LIDAR system controller <NUM> through bidirectional connections <NUM>. Power and ground connections (not shown) may be supplied through an electromechanical interface. Bidirectional connections <NUM> may be electrical or optical transmission lines, and the electromechanical interface may be a DB-<NUM> electrical connector, or a hybrid optical and electrical connector, or a special automotive connector configured to carry signals bidirectionally for the LIDAR sensor <NUM>. Bidirectional connections <NUM> (see <FIG>) would connect to LIDAR system controller <NUM> for an auxiliary lamp assembly which may have a short-range LIDAR sensor <NUM> embedded therein. Bidirectional connections <NUM> (<NUM>) may be high-speed serial connections such as Ethernet, Universal Serial Bus (USB), or Fibre Channel, or may also be parallel high-speed connections such as Infiniband, etc., or may be a combination of high-speed serial and parallel connections, without limitation to those listed here. Bidirectional connections <NUM> (<NUM>) also serve to upload information to control processor <NUM>, including program updates for data reduction processor <NUM>, object tracking processor <NUM>, and global position reference data, as well as application-specific control parameters for the remainder of the LIDAR sensor's <NUM> functional blocks. Inertial and vertical reference <NUM> (see <FIG>) also provides data to the short-range LIDAR sensors <NUM>-<NUM> and long-range LIDAR sensors <NUM>-<NUM> from the host vehicle <NUM> through the vehicle electrical systems and CPU <NUM> and the LIDAR system controller <NUM> as needed. Likewise, any other data from the host vehicle <NUM>, which may be useful to the LIDAR sensor <NUM>, may be provided in the same manner as the inertial and vertical reference data. Inertial and vertical reference data may be utilized in addition to external position references by control processor <NUM>, which may pass position and inertial reference data to data reduction processor <NUM> for adjustment of range and intensity data, and to object tracking processor <NUM> for utilization in multi-frame data synthesis processes. The vertical reference commonly provides for measurement of pitch and roll, and is adapted to read out an elevation angle, and a twist angle (analogous to roll) with respect to a horizontal plane surface normal to the force of gravity. The short-range LIDAR sensors <NUM>-<NUM> typically employ a semiconductor laser, which may be modulated in several different ways. The long-range LIDAR sensors <NUM>-<NUM> typically employ a Q-switched solid-state laser, which produces a single output pulse with a Gaussian profile if properly controlled. The pulse shape of a solid-state laser of this type is not easily modulated, and therefore must be dealt with "as is" by the receiver section of a long-range LIDAR sensor <NUM>-<NUM>. The operations of short-range LIDAR sensors <NUM>-<NUM> of the type which are typically embedded in an auxiliary lamp assembly such as a taillight, turn signal, or parking light are the same as the operations of the long-range LIDAR sensors <NUM>-<NUM> with some exceptions. The long-range LIDAR sensors <NUM>-<NUM> and short-range LIDAR sensors <NUM>-<NUM> may differ only in the type of laser employed and the type of laser modulation. The transmit optics <NUM> and receive optics <NUM> may also differ, owing to the different fields of view for long-range LIDAR sensors <NUM>-<NUM> and short-range LIDAR sensors <NUM>-<NUM>. Differences in the transmitted laser pulse modulation between the long-range LIDAR sensors <NUM>-<NUM> and short-range LIDAR sensors <NUM>-<NUM> may be accommodated by the flexible nature of the readout IC <NUM> sampling modes, and the data reduction processor <NUM> programmability. The host vehicle <NUM> may have a number of connector receptacles generally available for receiving mating connector plugs from USB, Ethernet, RJ-<NUM>, or other interface connection, and which may alternatively be used to attach long-range LIDAR sensors <NUM>-<NUM> or short-range LIDAR sensors <NUM>-<NUM> of the type described herein.

In a short-range LIDAR sensor <NUM>, considerably less transmit power is required, allowing for the use of a semiconductor laser and multi-pulse modulation schemes. One example of a semiconductor laser is the vertical cavity surface emitting laser (VCSEL), used in a preferred embodiment because of a number of preferential characteristics. A VCSEL typically has a circular beam profile, and has lower peak power densities at the aperture. VCSELs also require fewer secondary mechanical operations, such as cleaving, polishing, etc., and may be formed into arrays quite easily. The use of a semiconductor laser allows for the tailoring of a drive current pulse so as to produce a Gaussian optical pulse shape with only slight deviations. The VCSEL response time is in the sub-nanosecond range, and the typical pulse optical width might be <NUM>-<NUM> nanoseconds at the half power points. In the diagram of <FIG>, the VCSEL and laser driver would be part of the pulsed laser transmitter <NUM>, and the desired pulse or waveshape is itself produced by a digital-to-analog converter <NUM> which has a typical conversion rate of <NUM>-<NUM>, so any deviations in the output pulse shape from the Gaussian ideal may be compensated for in the lookup table in memory <NUM> associated with control processor <NUM>, which serves as the digital reference for the drive current waveform supplied to the laser driver within pulsed laser transmitter <NUM> by the D/A converter <NUM>. A Gaussian single-pulse modulation scheme works well at short ranges, given the limited optical power available from a VCSEL. Extending the range of a VCSEL transmitter may be done using more sophisticated modulation schemes such as multi-pulse sequences, sinewave bursts, etc. The VCSEL and modulation schemes as described herein with reference to short-range LIDAR sensor <NUM> are an alternative to the solid-state laser typically used in a pulsed laser transmitter <NUM> of a long-range LIDAR sensor <NUM>. The use of a VCSEL array in pulsed laser transmitter <NUM> has the potential to reduce cost, size, power consumption, and/or enhance reliability. LIDAR sensors may be mounted at many points on the vehicle <NUM>: headlamps, auxiliary lamps, door panels, rear view mirrors, bumpers, etc. When equipped with a more sensitive detector array <NUM> such as an APD array, SPAD array, or image tube FPA, a LIDAR sensor of the type described herein may use a VCSEL array as an illuminating source, and much longer ranges may be supported. When referring to the major functions of the LIDAR sensor of <FIG>, it is sometimes convenient to refer to the "optical transmitter" as those functions which support and/or create the burst of light for illuminating the scene in the field of view. These elements would typically be the control processor <NUM> which starts the process, pulsed laser transmitter <NUM>, transmit filter <NUM>, and transmit optics <NUM>. The term "optical receiver" may be used to refer to those elements necessary to collect the light reflected from the scene in the field of view, filter the received light, convert the received light into a plurality of pixelated electrical signals, amplify these pixelated electrical signals, detect the pulses or modulation thereon, perform the range measurements, and refine or reduce the received data. These functions would include the receive optics <NUM>, receive filter <NUM>, detector array <NUM>, readout IC <NUM>, A/D converters <NUM>, and the data reduction processor <NUM>.

With reference to <FIG>, the object detection sensor <NUM> in the illustrated example may be any suitable light detection and ranging (LIDAR) sensor, e.g., long-range sensor units LRU <NUM><NUM> and LRU <NUM><NUM>, short-range sensor units, SRU <NUM><NUM>, SRU <NUM><NUM>, SRU3 <NUM>, and SRU4 <NUM>. For example, the sensor <NUM> may be a solid-state sensor (e.g., a flash LIDAR sensor). Sensor <NUM> may emit pulses of light into the field of illumination, and when an object <NUM> is within the sensor's field of view, sensor <NUM> may detect an object <NUM> based on receiving reflections of light-reflected from object <NUM>.

According to at least the illustrated example in <FIG>, the sensor <NUM> includes one or more optical pulsed transmitters <NUM> (hereinafter "transmitters <NUM>"), e.g., including pulsed laser transmitter <NUM>, transmitter optics <NUM>, etc., and one or more receivers <NUM> (e.g., including receive optics <NUM>, receive filter <NUM>, detector array <NUM>, readout IC <NUM>). According to one example, each of the transmitters <NUM> are identical and each of the receivers <NUM> are identical; therefore, only one of each will be described below.

Transmitter <NUM> may be any suitable electronically-actuatable device for emitting light. For example, it may be a semiconductor laser such as a vertical-cavity surface-emitting laser (VCSEL), an edge emitting laser diode, or a diode-pumped solid-state laser (DPSSL), to name a few non-limiting examples. The transmitter <NUM> may be designed to emit a pulsed flash of light (e.g., a pulse beam) according to any suitable power and wavelength, i.e., the transmitter <NUM> may be a pulsed laser transmitter. According to one example, the pulse beam is in the infrared spectrum; however visible light and ultraviolet light may also be used in some applications.

Receiver <NUM> may include any suitable electronic device for detecting light transmitted by transmitter <NUM> and reflected from object <NUM>. With reference to <FIG> and <FIG>, according to one example, receiver <NUM> includes one or more pixels <NUM>. In the illustrated example receiver <NUM> includes an array of pixels <NUM> (see <FIG>). In at least one example, each pixel <NUM> may be identical; therefore, only one will be described. Pixel <NUM> may include a receiver circuit <NUM>, a filter circuit <NUM>, a buffer circuit <NUM>, and an analog memory circuit <NUM>.

In the example illustrated in <FIG>, the receiver circuit <NUM> includes a photosensitive input circuit <NUM> (or photodetector) and a logarithmic-signal circuit <NUM>. The photosensitive input circuit <NUM> may include a photosensitive element <NUM> having a built-in capacitance <NUM>(shown in <FIG> as a capacitor coupled in parallel (dashed lines) to element <NUM>). In one example, the photosensitive element <NUM> is a PIN photodiode, but may be an APD or other type. A photodiode is a semiconductor device designed to convert received light into an electrical current. The photodiode may have attached an optical filter for selecting an incoming wavelength of light. The photodetector may also employ a lens designed to collect and focus incoming light. As alluded to above, capacitor <NUM> represents built-in capacitance formed in the photodiode solid-state junction. According to an example, the built-in capacitance is typically in the range of <NUM> to <NUM> femto-Farads (fF).

In <FIG>, photosensitive element <NUM> includes an input <NUM> coupled to a voltage supply Vdet, e.g., <NUM> V DC, and an output <NUM> coupled to a node <NUM>. A light input <NUM> to the photosensitive element <NUM> is also shown-thus, when the light input <NUM> is received at element <NUM>, an electric current ipe is induced at the output <NUM>. The configuration shown enables a photoconductive mode of operation for photodiode <NUM>. The logarithmic-signal circuit <NUM> may include a forward-biased PN junction, hereinafter referred to as diode <NUM>. An anode (e.g., a p-type terminal of a PN junction) of the forward-biased diode <NUM> may be coupled to node <NUM> via a pulse voltage node <NUM> (node <NUM> having a voltage Vp) (in this example, nodes <NUM>, <NUM> and <NUM> are identical). A terminal <NUM> of the logarithmic-signal circuit <NUM>, e.g., a cathode (e.g., an n-type terminal of a PN junction) of the diode <NUM>, may be coupled to ground. The term "ground" is used in this context to describe a reference point (i.e., having a constant potential) in an electrical circuit from which voltages are measured and which is a common return path for electric current; in some examples receiver circuit <NUM> may include local and/or global grounds. In at least one example, the logarithmic circuit <NUM> does not include an amplifier directly coupled to the photosensitive input circuit <NUM>. The receiver circuit <NUM> may be coupled to the filter circuit <NUM> via node <NUM>.

Shown in <FIG>, filter circuit <NUM> may be any suitable circuit for filtering undesirable noise from the system. According to one example, filter circuit <NUM> includes an adjustable low-pass filter. In the present context, "adjustable filter" means having a variable bandwidth. According to the illustrated example, the adjustable low-pass filter circuit <NUM> includes an optional buffer <NUM> (e.g., a buffer amplifier) coupled to an RC filter that may include an adjustable resistor circuit <NUM>. In the embodiment shown in the Figures, resistor circuit <NUM> may be a selectable resistor, but may alternatively be a potentiometer or other adjustable resistor. The adjustable resistor circuit <NUM> is connected to a first terminal of capacitor <NUM>, and the second terminal of capacitor <NUM> is connected to a constant potential such as ground. More particularly, an input <NUM> of filter circuit <NUM> (and to buffer <NUM>) may be connected to node <NUM> (voltage Vp), and an output of the buffer <NUM> may be connected to resistor circuit <NUM> at node <NUM>. An output <NUM> of the filter circuit <NUM> is produced at node <NUM> (voltage Vf). In this embodiment node <NUM> is located between resistor circuit <NUM> and capacitor <NUM>. Illustrative values of resistor circuit <NUM> include a resistive range of <NUM> kohm to <NUM> kOhms, and illustrative values of capacitor <NUM> include <NUM> fF to <NUM> fF. The buffer <NUM> (when included in circuit <NUM>) may increase electrical isolation between input node <NUM> (Vp) and filter output Vf at node <NUM> and may minimize the undesirable reduction of an electrical signal source by a lower impedance load. Buffer amplifier <NUM> therefore serves the well-known purpose of driving a lower impedance load from a higher impedance source without loss of signal. By adjusting the resistance of resistor circuit <NUM>, filter circuit <NUM> may adjust a bandwidth of the circuit <NUM>.

As shown in <FIG>, other examples of the filter circuit also exist. For instance, a filter circuit <NUM>' is shown including a resistor circuit <NUM>'; other elements of the filter circuit may be similar or identical to those described with respect to <FIG> (thus, they will not be re-described here).

Resistor circuit <NUM>' may include a first resistor 64a connected in parallel with a first bypass switch 66a and a second resistor 64b connected in parallel with a second bypass switch 66b. Resistors 64a, 64b and switches 66a, 66b each are connected to one another at node <NUM>. Switches 66a, 66b may be selectively actuated via an electronic control unit or computer (e.g., including but not limited to computer <NUM>) to control resistance and thereby control the bandwidth of the filter circuit <NUM>'. Switch 66a is controlled by an electrical input 67a, and switch 66b is controlled by a control input 67b. Consider for example the illustrative total resistances of filter circuit <NUM>' (shown in Table I), wherein the resistance of resistor 64a is represented as "R1" and wherein the resistance of resistor 64b is represented as "R2. " The resistance of switches 66a and 66b when closed is Rs and is normally much lower than R1 and R2. According to at least one example, R1 may be <NUM> kOhm, R2 may be <NUM> kOhm and Rs may be <NUM> kOhm; however, these resistance values are merely examples.

Thus, by selectively controlling the switches 66a, 66b of the resistor circuit <NUM>', the bandwidth of the filter circuit <NUM>' may be adjusted. It should be appreciated that other examples of resistor circuit <NUM>' also exist-e.g., including use of additional arrangements of resistors coupled in series and/or parallel.

<FIG> illustrates the analog sampling circuit including buffer circuit <NUM> and analog memory circuit <NUM>. Buffer circuit <NUM> may be a source follower, push-pull, amplifier in unity-gain feedback or other suitable electronic buffer amplifier. These other implementations of buffer circuit <NUM> will be appreciated by those skilled in the art. Output <NUM> (voltage Vf) of the filter circuit <NUM> is connected to an input <NUM> of buffer circuit <NUM>, and an output <NUM> (voltage Vb) of the buffer circuit <NUM> is connected to an input <NUM> of the analog memory circuit <NUM> at node <NUM>.

<FIG> also illustrates an example implementation of analog memory circuit <NUM>. According to at least the illustrated example, the analog memory circuit <NUM> includes a plurality of analog sampling circuits <NUM>. Each analog sampling circuit <NUM> includes a capacitor <NUM> with a first terminal connected to the output of a switch <NUM>, and a second terminal connected to a constant potential such as ground. Switch <NUM> has an input connected to node <NUM> and has a control input <NUM> actuated by a digital sample clock signal. Analog memory circuit <NUM> includes a plurality of these sequentially-clocked analog sampling circuits <NUM> each coupled to node <NUM> as well. According to a non-limiting example, analog memory circuit <NUM> may include between <NUM> and <NUM> sequentially-clocked analog sampling circuits <NUM>-thereby having a suitable quantity to store data regarding several return pulses. Shown in <FIG> are only three exemplary analog sampling circuits <NUM> for the sake of clarity. According to at least one example, each of the analog sampling circuits <NUM> may be identical; therefore, only one will be explained.

Sequentially-clocked analog sampling circuit <NUM> typically includes a switch <NUM> and a capacitor <NUM>, wherein the switch <NUM> is connected between node <NUM> and a node <NUM> (voltage Vi), and wherein capacitor <NUM> is coupled between node <NUM> and ground. (Each circuit <NUM> may have a different input voltage as a function of time; thus, "i" of Vi may be designated <NUM>, <NUM>,. As will be explained more below, by selectively actuating switches <NUM> (i.e., closing one of the switches <NUM>), each of the circuits <NUM> may be used to store a 'time sample' (e.g., a sample voltage) of a portion of an electrical signal received via node <NUM>.

Voltages V<NUM>, V<NUM>,. , Vn of analog memory circuit <NUM> may be digitized by an analog to digital converter (not shown) and received as digitized voltage samples by computer <NUM>, as best shown in <FIG>. In some cases, the processor <NUM> will have on-board ADCs for the analog-to-digital conversion, a common feature on many signal processing microcomputer integrated circuits. Thus, computer <NUM> is coupled to the analog memory circuit <NUM>. More particularly, computer <NUM> may be coupled to each of the nodes <NUM> so that it may read the stored time slices.

Other examples of the receiver circuit <NUM> of pixel <NUM> exist as well. However, before describing some of these examples, an example operation of sensor <NUM> will be described. According to a non-limiting example, the computer <NUM> may be programmed to control a plurality of transmitter/receiver pairs <NUM>, <NUM> of the sensor <NUM> to detect objects (such as object <NUM>) within a sensor field of view. As operation of each pair <NUM>, <NUM> may be similar, the operation of only one transmitter/receiver pair <NUM>, <NUM> will be described.

A general operation of the sensor <NUM> may include the sensor <NUM> and computer <NUM> being powered by a power source (not shown) onboard the vehicle <NUM>. At a suitable time prior to moving the vehicle, the power source is activated. Thereafter, computer <NUM> may start the sampling clock and command a laser transmit pulse from transmitter <NUM>. The light may be reflected from a surface of object <NUM>, and the receiver <NUM>, in an active state, may receive the reflected beam (also called a return, a return beam, or a return pulse). As used herein, an active state means the sensor <NUM> is powered and the receiver <NUM> (and its components such as the receiver circuit <NUM>) are ready to receive the return pulse. After receiving the return pulse, computer <NUM> may determine a range (e.g., a distance) between the sensor <NUM> and the surface of the object <NUM> using a time of flight (TOF) calculation. A typical TOF calculation would be the speed of light multiplied by the measured change in time (Δt) of a return pulse; wherein Δt equals a time of return after the time of the initiated clock. Typically, a sensor installation <NUM> includes multiple transmitter/receiver pairs <NUM>, <NUM>; thus, numerous range measurements from various fields of view are received, and using these measurements, computer <NUM> determines a so-called three-dimensional (3D) point cloud. A point cloud is the common term for a collection of points which may define one or more surfaces of object <NUM>. Point cloud data may be used by computer <NUM> to generate a 3D map of an area around the sensor <NUM>, e.g., various sides of building, trees, road surface, etc. Thereafter, computer <NUM> or other computers onboard vehicle <NUM> may control vehicle propulsion, braking, and/or steering based on detection of object <NUM> or the like.

A more specific description of the operation of the receiver <NUM> follows. Referring again to <FIG>, powering the receiver <NUM> may include providing a predetermined detector voltage supply (e.g., 8V) at Vdet. In some examples, switches 66a, 66b, inputs <NUM>, etc. (<FIG>, <FIG>) may also be powered by a digital logic voltage level of <NUM>. 5V or other suitable voltage. In this manner, when a return pulse is received at pixel <NUM>, photosensitive element <NUM> may provide via output <NUM> a photocurrent pulse (ipe) that corresponds with a magnitude of the received and transduced light. Herein, current ipe is also referred to as a photoelectric pulse current, as it is created by reception of the return pulse.

At node <NUM>, pulse current ipe is converted into a voltage pulse Vp by passing through logarithmic-signal circuit <NUM> to ground. Circuit <NUM> is referred to as a logarithmic-signal circuit based on the gradual (e.g., logarithmic) change of voltage (Vp) with current ipe. In general, the logarithmic voltage compression of the logarithmic-signal circuit <NUM> improves the dynamic range of the receiver circuit <NUM>. Dynamic range refers to the ratio of the maximum photoelectric pulse current to the minimum photoelectric pulse current that can be received by receiver circuit <NUM>. The maximum photoelectric pulse current is the highest photoelectric pulse current that does not cause saturation in the photosensitive element <NUM> or the voltage at nodes <NUM>, <NUM> or <NUM>. The minimum photoelectric pulse current is M times higher than the input-referred noise of the receiver. The factor M depends on the required probability of detection of a return pulse. For higher probability of detection, the factor M would be higher, and therefore the calculated dynamic range somewhat less. Therefore, dynamic range is a somewhat subjective characteristic of a pulse receiver subsystem.

The filter circuit <NUM> may suppress noise frequencies of the voltage pulse Vp that exceed a predetermined filter cutoff frequency so that node <NUM> measures the filtered voltage Vf. According to at least one example, resistor circuit <NUM> is tuned suitably to adjust a filter bandwidth, as described above. The choice of bandwidth may be calculated dynamically, or set in a factory calibration sequence, and may depend on various factors such as the rise/fall time of the transmitted laser pulse, the frequency and amplitude response of the photodiodes, the dark current or background noise level of the photodetectors and the sampling frequency of the analog memory circuit <NUM>. According to another bandwidth adjustment example, computer <NUM> determines whether to actuate (and thereby close) switch 66a, switch 66b, or both.

The buffer circuit <NUM> receives voltage Vf at input <NUM> (<FIG>). Thereafter, buffer amplifier circuit <NUM> replicates the input signal and provides a low-impedance drive capability to output <NUM> (voltage Vb) without loading the input signal at node <NUM>. Buffering techniques and the electrical circuits employed to execute such buffering techniques are known to those skilled in the art.

According to the illustrated example, analog memory circuit <NUM> receives voltage Vb at node <NUM>, which is sampled consecutively by one of the sampling circuits <NUM>. According to one example, only one of the switches <NUM> may be actuated to a closed position at a time-as controlled by computer <NUM> via respective input <NUM>. Further, the switches <NUM> may be moved selectively, one at a time, to a closed position according to a predetermined sequence in order to capture voltage information regarding a pulse return. When switch <NUM> of one of the circuits <NUM> is in the closed position, the respective capacitor <NUM> charges to the voltage present at node <NUM>. Once respective switch <NUM> is actuated to the open position again, the sampled voltage value is stored on the capacitor <NUM> until computer <NUM> reads out the value. For example, by sequentially repeating this operation, voltage values of the return pulse may be sampled at <NUM> nanosecond intervals (e.g., as multiple time slices), and computer <NUM> may be able to reconstruct a shape and profile of the return pulse having a width of <NUM> nanoseconds. Further, computer <NUM> may be able to determine a peak of the return pulse and that peak may be used to accurately calculate Δt and thereby determine a range of the respective return pulse.

As discussed above, other examples of the receiver circuit <NUM> of pixel <NUM> exist as well. In each of the examples which follow like or identical elements are designated with like reference numerals. For example, <FIG> illustrates an example receiver circuit <NUM><NUM>. According to this example, the photosensitive input circuit <NUM> and logarithmic-signal circuit <NUM> may be coupled to an impedance-reducing circuit <NUM> (also called a common-gate amplifier circuit) and a current bypass circuit <NUM>. Some aspects of receiver circuit <NUM><NUM> may be identical to receiver circuit <NUM> (of <FIG>).

According to the invention, the impedance-reducing circuit <NUM> is coupled between the photosensitive input circuit <NUM> and node <NUM>. Impedance-reducing circuit <NUM> may include two transistors: a common-gate transistor <NUM>, and a bias transistor <NUM> connected as shown. For example, common-gate transistor <NUM> may be a p-channel metal-oxide-semiconductor field effect transistor (MOSFET), and bias transistor <NUM> may also be a p-channel MOSFET. Common-gate transistor <NUM> includes a first terminal <NUM>, a second terminal <NUM>, and a third terminal <NUM> (e.g., a gate , a source, and a drain, respectively), and bias transistor <NUM> includes a first terminal <NUM>, a second terminal <NUM>, and a third terminal <NUM> (e.g., a gate, a source, and a drain, respectively). Second terminal <NUM> is connected to a power supply (e.g., <NUM>. 5V), first terminal <NUM> may be coupled to a reference voltage, typically a digital-to-analog converter (DAC) output programmed by computer <NUM>. Computer <NUM> may be a controller type of microprocessor which has several onboard DACs. Computer/controller <NUM> is able to adapt a reference voltage (Vpbias) to actuate bias transistor <NUM> to provide through third terminal <NUM> a bias current to common-gate transistor <NUM>. Common-gate transistor <NUM> requires a minimum level of bias current to be provided at second terminal <NUM>. First terminal <NUM> is connected to a reference voltage (Vcg) to set up common-gate transistor <NUM> for proper operation. The reference voltage (Vcg) is typically provided by a DAC output, also driven by computer/controller <NUM>. The common-gate transistor <NUM> is connected to the node <NUM>, specifically, the third terminal <NUM> is connected to node <NUM>.

Current bypass circuit <NUM> includes a bypass transistor <NUM> (e.g., an n-channel MOSFET) having a first terminal <NUM>, a second terminal <NUM>, and a third terminal <NUM> (e.g., a gate, a drain, and a source, respectively). First terminal <NUM> is connected to a bias voltage (Vnbias). The bias voltage (Vnbias) is typically generated by a DAC. The DAC in the embodiment shown in the Figures is integral to computer/controller <NUM> which calculates the optimum voltage (Vnbias) to the gate terminal <NUM> of bypass transistor <NUM>. Bypass transistor <NUM> acts to shunt the bias current provided by bias transistor <NUM> to ground, as second terminal <NUM> is connected to node <NUM>, and third terminal <NUM> is connected to ground. In this manner, the bypass transistor <NUM> is adapted to reduce the bias current delivered to the logarithmic-signal circuit <NUM> thereby ensuring that diode <NUM> exhibits large dynamic resistance for small photocurrent pulses.

During operation of receiving circuit <NUM><NUM>, common-gate transistor <NUM> may reduce the impedance as seen by the photosensitive input circuit <NUM>, thereby reducing the effect of photodiode built-in capacitance <NUM>. Photodiode built-in capacitance <NUM> acts to limit the frequency response of the pulse receiver circuit <NUM>. This effect would be much greater were impedance-reducing circuit <NUM> not installed. The effect is basically the same as a lowpass filter, reducing the high-frequency content in the received pulse. Excessive lowpass filtering acts to reduce the received pulse amplitude and increase the received pulse width. Any reduction in received pulse amplitude is undesirable, as it negatively impacts the maximum range of the LIDAR system. Therefore, the impedance reducing circuit <NUM> acts to improve frequency response, amplitude response, and thereby maximum range of the LIDAR system. The bias current supplied by bias transistor <NUM> adds to the photocurrent from the detector element <NUM>, and is input to node <NUM> as icg = (ipe + ibp), wherein ibp represents the bias current of the impedance reducing-circuit <NUM>. Accordingly, current bypass circuit <NUM> is configured to correspondingly reduce that current. Current bypass circuit <NUM> is designed to divert to ground the bias current necessary for the operation of the impedance-reducing circuit <NUM> as well as the dark current and DC background photocurrent received from the photosensitive input circuit <NUM>. Dark current is a relatively small electric current that flows through a photosensitive element such as a photodiode even when no photons are entering the element; it arises from the charges generated in the photosensitive element when no outside radiation is entering the photosensitive element. The DC background photocurrent may be due to light received via receiver <NUM> that is emitted by sources of light other than transmitter <NUM> (e.g., street lighting, sunlight, vehicle light, etc.).

Equation (<NUM>) shows a relationship of current idiode passing through the diode <NUM> and the currents ipe, ibp and ibn. Here ibn is the bypass current generated by bypass transistor <NUM>. The voltage value Vnbias (and thus the bypass current ibn) is typically selected to set up a current idiode which is equal to ipe minus any dark current and DC background photocurrent.

Equations (<NUM>)-(<NUM>) show a relationship of voltage Vp at the node <NUM> and the current idiode passing through the logarithmic-signal circuit <NUM>, wherein k = <NUM>×<NUM>-<NUM> J/K is Boltzmann constant, T is absolute temperature (in K), q = <NUM>×<NUM>-<NUM> C is the charge of the electron Is represents a reverse saturation current (in A) of the diode <NUM>, and operator ln is a natural logarithm operator which is logarithm to the base of a mathematical constant e. Thus, as shown in Equation (<NUM>), the voltage Vp may have a logarithmic relationship to the current idiode which provides a high dynamic range. Equation (<NUM>) defines a transimpedance rm of the receiver circuit <NUM><NUM> as the dynamic resistance of diode <NUM> at the operating point defied by current idiode. As shown in Equation (<NUM>), the transimpedance rm of the receiver circuit <NUM><NUM> increases as the current idiode reduces. Hence, in order to keep idiode small and thus rm large, it is important to offset the common-gate bias current ibp with the bypass current ibn. Having large transimpedance rm is beneficial for detecting small photocurrent pulses. <MAT> <MAT> <MAT> <MAT>.

<FIG> illustrates yet another example of a receiver circuit which includes a servo loop circuit-receiver circuit <NUM><NUM>. Some aspects of the receiver circuit <NUM><NUM> may be identical to those shown in <FIG>.

<FIG> illustrates a buffer circuit <NUM> and a servo loop circuit <NUM> connected to receiver circuit <NUM> shown in <FIG>. The buffer circuit <NUM> may include any suitable buffer amplifier. Buffer circuit <NUM> has an input <NUM> and an output <NUM>. In the embodiment shown in the Figures, it is similar to buffer circuit <NUM>. In this instance buffer circuit <NUM> is connected between node <NUM> and a node <NUM> (voltage Vp).

Servo loop circuit <NUM> includes an amplifier <NUM>, which may be an operational amplifier, having a reference input <NUM> supplied by voltage Vref, a feedback input <NUM> connected to node <NUM>, and an output <NUM> (control voltage Vnbias) connected to first terminal <NUM> of bypass transistor <NUM>.

Thus, in operation, servo loop circuit <NUM> controls the current ibn of the current bypass circuit <NUM>. When a reference voltage Vref is provided to input <NUM> and the voltage (Vp) at node <NUM> is fed back into amplifier <NUM>, a control voltage Vnbias at the amplifier output <NUM> is produced which controls bypass current ibn. The net effect of servo loop circuit <NUM> is to hold the DC portion of voltage Vp equal to the voltage Vref. This DC bias level may be maintained regardless of the dark current of the photosensitive element <NUM> and/or any DC background photocurrent detected by the sensor <NUM>. The servo loop circuit <NUM> acts as a lowpass filter with a <NUM>-dB corner frequency typically below <NUM>. The selection of the <NUM>-dB corner frequency is chosen to avoid any interaction with the high-frequency content of the return pulse.

<FIG> illustrates yet another example of a receiver circuit (receiver circuit <NUM><NUM>) which includes a logarithmic-signal circuit <NUM> and two other signal circuits: a linear-signal circuit <NUM> and a square-root-signal circuit <NUM>. As discussed above with respect to logarithmic-signal circuit <NUM>, the linear-signal and square-root-signal circuits <NUM>, <NUM> describe the voltage response characteristics of the receiver circuit <NUM> to the photocurrent from a detected return pulse. For example, the linear-signal circuit <NUM> yields a linear curve when voltage is plotted against photocurrent; similarly, the square-root-signal circuit <NUM> yields a square-root curve when voltage is plotted against incoming photocurrent. Some aspects of the receiver circuit <NUM><NUM> may be identical to those shown in previous examples.

In <FIG>, the photosensitive input circuit <NUM> and logarithmic-signal circuit <NUM> are shown connected to node <NUM>. In at least one example, the diode <NUM> of logarithmic-signal circuit <NUM> is coupled between node <NUM> and a predetermined voltage Vclamp, instead of between node <NUM> and ground as in the previous example.

Linear-signal circuit <NUM> may include a resistor <NUM> that may be coupled between node <NUM> and ground. The value of the resistor is typically in the range of <NUM> to <NUM> Ohms.

Square-root-signal circuit <NUM> is a p-channel MOSFET <NUM> comprising a first terminal <NUM>, a second terminal <NUM>, and a third terminal <NUM> (gate, drain, and source, respectively). First terminal <NUM> is connected to computer <NUM> which has an output DAC providing a threshold voltage (Vknee). Second terminal <NUM> is connected to node <NUM>, and third terminal <NUM> is connected to a constant potential such as ground.

An example of operation of receiver circuit <NUM><NUM> follows. As discussed above, the logarithmic-signal, linear-signal, and square-root-signal circuits <NUM>, <NUM>, <NUM> may yield electrical signals (at node <NUM>) characterized by a logarithmic profile, a linear profile, and a square-root profile, respectively. More particularly, receiver circuit <NUM><NUM> may be designed so photocurrent predominantly flows through one of circuits <NUM>, <NUM>, <NUM> depending on the input signal level. <FIG> plots the simulated amplitude of the voltage pulse at node <NUM> (Vp) as a function of the amplitude of the photocurrent pulse generated by photosensitive element <NUM>. It is obtained using the receiver circuit <NUM><NUM> of <FIG>. Regions <NUM>, <NUM> and <NUM> are the linear, square-root and logarithmic regions, respectively. It should be noted that this is a semi-log plot wherein the x-axis is logarithmic but the y-axis is linear; this explains why the linear region <NUM> is not visually linear.

Current may flow through one of the three circuits <NUM>, <NUM>, <NUM> based on the magnitude of current (ipe). For example, when the current (ipe) is less than a first threshold, it flows predominantly through the linear-signal circuit <NUM> (see region <NUM>, <FIG>). When the current (ipe) is greater than the first threshold and less than a second threshold, it flows predominantly through the square-root-signal circuit <NUM> (see region <NUM>, <FIG>). And when the current (ipe) is greater than the second threshold, it flows predominantly through the logarithmic-signal circuit <NUM> (see region <NUM>, <FIG>). The voltage Vp is less than Vknee for the linear region <NUM>, between Vknee and Vclamp for the square-root region <NUM>, and greater than Vclamp for the logarithmic region <NUM>. In other words, voltage Vknee controls the first threshold and voltage Vclamp controls the second threshold. Thus, the voltage Vp pulse amplitude as a function of the photocurrent pulse amplitude has: a substantially linear profile when current ipe levels are at low levels (region <NUM>); a substantially square-root profile when current ipe levels are in a middle range (region <NUM>); and a substantially logarithmic profile when current ipe levels are in the upper range (region <NUM>). By having three regions <NUM>, <NUM>, <NUM>, the receiver circuit <NUM><NUM> achieves a voltage compression and thus high dynamic range.

<FIG> shows a graph having a plurality of plots <NUM> of simulated return pulses, the graph being voltage Vp (with the DC component removed) versus time in nanoseconds and the plots being electrical signals processed by receiver circuit <NUM><NUM> of <FIG>. The plots are for photocurrent pulse amplitudes from <NUM> nA to <NUM> mA. Depending on the amplitude of the photocurrent, the return pulses may have passed through any one, two, or all three regions of, linear-signal profile, square-root-signal profile or logarithmic-signal profile. It can be seen from the plots that the shapes of the voltage pulses are substantially consistent, and the voltage pulse amplitudes are not saturated. Accordingly, plots <NUM> are intended to illustrate that consistently-shaped and non-saturated voltage pulses can be produced over a wide range of input photocurrent signal amplitudes.

Other examples of receiver circuit also exist which may yield similar plots. For instance, according to another example, diode <NUM> may be a source-to-bulk PN junction of a p-channel MOSFET transistor (<NUM>). Such a configuration may yield results similar to those shown in <FIG>.

<FIG> illustrates yet another example of a receiver circuit (receiver circuit <NUM><NUM>) which includes linear-signal circuit <NUM>, square-root signal circuit <NUM>, and a logarithmic signal circuit <NUM>' combined with impedance-reducing circuit <NUM>. Some aspects of the receiver circuit <NUM><NUM> may be identical to those shown in previous examples.

More particularly, impedance-reducing circuit <NUM> is connected to the photosensitive input circuit <NUM> in a way identical to <FIG> (receiver circuit <NUM><NUM>). Further, linear-signal circuit <NUM> and square-root-signal circuit <NUM> may be connected to node <NUM> in a way identical to <FIG> (receiver circuit <NUM><NUM>). Logarithmic-signal circuit <NUM>' may be coupled to node <NUM> (indirectly coupled to node <NUM>); more specifically, it may be connected between node <NUM> and a voltage (Vclamp). Receiver circuit <NUM><NUM> may also include some parasitic capacitance represented in <FIG> as capacitor <NUM> connected between node <NUM> and ground. The capacitance value of capacitor <NUM> is typically much less than the capacitance value of photodiode built-in capacitance <NUM> (e.g., <NUM> times smaller).

A non-limiting example of operation of the receiver circuit <NUM><NUM> follows. For a current ipe within the linear region <NUM>, the current ipe develops a voltage Vp which grows substantially linearly with ipe. The shape of the voltage pulse at Vp and the transimpedance of the receiver circuit <NUM><NUM> are determined primarily by the resistor <NUM> and the capacitor <NUM>.

For a current ipe within the square-root region <NUM>, voltage Vp is greater than voltage Vknee, the transistor <NUM> turns on and conducts most of the current ipe, resulting in a square-root profile, as discussed above. The shape of voltage pulse at Vp and the transimpedance of the receiver circuit <NUM><NUM> are determined primarily by the drain-to-source resistance of transistor <NUM> and the capacitor <NUM>.

For a current ipe within the logarithmic region <NUM>, the voltage at node <NUM> is greater than the voltage Vclamp and the diode <NUM> becomes forward-biased and conducts most of the current ipe. As a result, the voltage at node <NUM> grows logarithmically with the current ipe. In the logarithmic region <NUM>, the voltage Vp at node <NUM> is substantially equal to the voltage at node <NUM> because transistor <NUM> operates in the triode region. Thus, in this region, the voltage pulse amplitude at Vp versus current ipe has a substantially logarithmic profile. The shape of the voltage pulse at Vp and the transimpedance of the receiver circuit <NUM><NUM> are determined primarily by the resistance of the diode <NUM> and the capacitance at node <NUM>. The latter is typically dominated by the photodiode built-in capacitance <NUM>. The fact that the logarithmic-signal circuit <NUM>' is directly coupled to node <NUM> instead of node <NUM> has the following advantages: the transimpedance in the logarithmic region <NUM> is not limited by the source impedance of transistor <NUM>, and the receiver circuit <NUM><NUM> is more latch-up resistant since the large photocurrent pulse ipe in the logarithmic region <NUM> is shunted directly to Vclamp.

<FIG> illustrates yet another example of a receiver circuit (receiver circuit <NUM><NUM>) which includes the receiver circuit <NUM><NUM> plus an AC test circuit <NUM> (i.e., current pulse injection circuit <NUM>) and/or a DC test circuit <NUM>. Some aspects of the receiver circuit <NUM><NUM> may be identical to those shown in previous examples.

AC test circuit <NUM> typically includes a transistor <NUM> (e.g., a p-channel MOSFET) and a switch <NUM>. Transistor <NUM> has a first terminal <NUM>, a second terminal <NUM>, and a third terminal <NUM> ( a gate, a source, and a drain, respectively). First terminal <NUM> is connected to a DAC output of computer <NUM> which provides a bias voltage (Vpbias-pulse) to actuate transistor <NUM>. Second terminal <NUM> is connected to a voltage supply (e.g., <NUM>. 5V), and third terminal <NUM> is connected to switch <NUM>. Switch <NUM> is connected between the third terminal <NUM> and node <NUM>. Thus, when switch <NUM> is actuated to a closed position by a control signal (en_actest) via an input <NUM>, then third terminal <NUM> is connected to node <NUM>.

In operation of the AC test circuit <NUM>, computer <NUM> actuates the switch <NUM> to the closed position and provides voltage Vpbias_pulse to first terminal <NUM>. The duration of switch <NUM> in the closed position may simulate the width of a photocurrent pulse, and an amplitude of the simulated photocurrent pulse may be determined by the current produced by transistor <NUM> when biased with voltage Vpbias_pulse. The current pulse injection circuit <NUM> is adapted to provide a test of functionality or performance of receiver circuit <NUM><NUM>.

DC test circuit <NUM> includes a pair of switches <NUM>, <NUM>. Switch <NUM> is connected between a terminal of resistor <NUM> (node <NUM>) and ground. Switch <NUM> is connected between node <NUM> and first terminal <NUM> of transistor <NUM> (of square-root-signal circuit <NUM>). During normal operation of receiver circuit <NUM><NUM>, switch <NUM> is closed and switch <NUM> is open. During a DC test, switch <NUM> is actuated to an open position by a control signal (~en_dctest, where "~" denotes logic negation) via an input <NUM> and switch <NUM> is actuated to a closed position by a control signal (en_dctest) via an input <NUM>.

According to at least one example, during a DC test, computer <NUM> may turn off the common-gate transistor <NUM> by providing a voltage (Vcg) at terminal <NUM> equal to the supply voltage. Concurrently, computer <NUM> may provide control signals to inputs <NUM>, <NUM> thereby opening switch <NUM> and closing switch <NUM>. In this state, computer <NUM> may perform a sweep of bias voltage Vknee at terminal <NUM> to test the functionality, DC offset, gain, and voltage range of the analog signal chain downstream of the receiver circuit <NUM><NUM>. As shown in <FIG>, the analog signal chain may include filter circuit <NUM>, buffer circuit <NUM> and analog memory circuit <NUM>.

<FIG> illustrates a receiver circuit <NUM><NUM> which includes a receiver circuit (e.g., such as receiver circuit <NUM><NUM> shown in <FIG>) coupled to a servo loop circuit <NUM>. The schematic diagram shown in <FIG> also illustrates receiver circuit <NUM><NUM> coupled to filter circuit <NUM>, buffer circuit <NUM>, and analog memory circuit <NUM> as previously described. Servo loop circuit <NUM> includes an amplifier <NUM> which controls the bias current of impedance reducing circuit <NUM>, a switch <NUM>, and a switch <NUM>. Some aspects of the receiver circuit <NUM><NUM> may be identical to those shown in previous examples.

Amplifier <NUM> has a reference voltage input <NUM> (Vref), a feedback input <NUM> coupled to node <NUM> (the output of buffer circuit <NUM>), and an output <NUM> coupled to node <NUM> via switch <NUM>. Switch <NUM> is connected between output <NUM> and first terminal <NUM> of bias transistor <NUM>. When a control signal (~pd_servo, where "~" denotes logic negation) is provided via an input <NUM> of switch <NUM>, switch <NUM> moves from a closed position to an open position.

Switch <NUM> is connected between node <NUM> and an input <NUM> which provides voltage Vpbias, as discussed above. When a control signal (pd_servo) is provided to an input <NUM> of switch <NUM>, switch <NUM> moves from a closed position to an open position.

Thus, when the servo loop is disabled or powered down (control signal pd_servo is set to logic high), switch <NUM> is in the open position, switch <NUM> is in the closed position, and voltage Vpbias is provided to first terminal <NUM> of bias transistor <NUM> thereby establishing a DC bias current ibp. When the servo loop is enabled (control signal pd_servo is set to logic low), switch <NUM> is in the closed position, switch <NUM> is in the open position, and the output of amplifier <NUM> is connected to first terminal <NUM> of bias transistor <NUM>. Other aspects of operation may be similar to those described above with respect to the servo loop circuit shown in receiver circuit <NUM><NUM> (<FIG>). For example, the output <NUM> of the amplifier <NUM> adjusts the transistor <NUM> DC bias current ibp thereby changing the DC voltage at the node <NUM> and consequently the DC voltage at the node <NUM> until the latter becomes equal to the reference voltage Vref.

In the embodiment shown in <FIG>, the bandwidth of the servo loop circuit <NUM> may be sufficiently low so the servo loop circuit <NUM> is relatively insensitive to the voltage pulse resulting from a return pulse (e.g., insensitive to a photocurrent pulse ipe of the photosensitive input circuit <NUM>). The servo loop comprising amplifier <NUM> and feedback connection to node <NUM> is designed to establish a DC voltage level at node <NUM> equal to the reference voltage Vref, regardless of the dark current and/or DC background photocurrent of photosensitive input circuit <NUM>.

<FIG> illustrates another example of a receiver circuit (receiver circuit <NUM><NUM>) which includes a receiver circuit connected to a noise-rejection circuit <NUM> (also called a static gate decoupling circuit). Some aspects of the receiver circuit <NUM><NUM> may be identical to those shown in previous examples.

Noise-rejection circuit <NUM> includes a capacitor <NUM>, a resistor <NUM> connected to a reference voltage source <NUM> (Vcg). Capacitor <NUM> is coupled between node <NUM> and node <NUM>. Node <NUM> is the detector voltage supply Vdet and input <NUM> of photosensitive input circuit <NUM>. Node <NUM> is at first terminal <NUM> of common-gate transistor <NUM>. Resistor <NUM> is connected between node <NUM> and reference voltage source <NUM>. Reference voltage source <NUM> is connected between resistor <NUM> and ground. Resistor <NUM> may represent a physical resistor. Alternatively, resistor <NUM> may represent the output impedance of an amplifier generating reference voltage Vcg.

The capacitor <NUM> is adapted to reject common-mode noise on the detector voltage supply such that, in operation, noise-rejection circuit <NUM> couples a voltage disturbance on the detector voltage supply Vdet via capacitor <NUM> to the first terminal <NUM> of common-gate transistor <NUM>. Since the Vdet voltage disturbance is also coupled to the second terminal <NUM> of common-gate transistor <NUM> via the photodiode built-in capacitance <NUM>, the net effect is that the drain current of common-gate transistor <NUM>, and hence the voltage Vp at node <NUM>, is largely unaffected by the Vdet voltage disturbance. A dip in the detector voltage supply at node <NUM> can be caused by a sudden increase in current ipe due to photosensitive input circuit <NUM> receiving a return pulse, or by any number of neighboring pixels receiving a strong return pulse. The product of the resistance of resistor <NUM> and the capacitance of capacitor <NUM> establish a time-constant. In a preferred embodiment, this time-constant is much longer than the width of the Vdet voltage dip.

<FIG> illustrates another example of a receiver circuit (receiver circuit <NUM><NUM>) which includes a receiver circuit having a noise-rejection circuit <NUM>' (also called a dynamic gate decoupling circuit). In the embodiment shown in <FIG>, receiver circuit <NUM><NUM> may be identical to receiver circuit <NUM><NUM> except switch <NUM> is substituted for resistor <NUM>. Aspects of receiver circuit <NUM><NUM> which are identical to previous examples will not explained again.

Computer <NUM> controls via a control signal switch <NUM> to move from an open position to a closed position. Actuating switch <NUM> to the closed position resets the noise-rejection circuit <NUM>' by setting the voltage at first terminal <NUM> of the common-gate transistor <NUM> to the reference votage Vcg. For example, this may occur before the laser pulse is transmitted or when computer <NUM> anticipates no incoming return pulses.

A sensor is described that includes a transmitter and a receiver. The receiver may include one or more pixels. At least one pixel includes a receiver circuit which includes at least a photosensitive input circuit and a logarithmic-signal circuit. Various examples of the receiver circuit have been described which may improve sensor performance.

With regard to the processes, systems, methods, etc. described herein, it should be understood that, although the steps of such processes, etc. have been described as occurring according to a certain ordered sequence, such processes could be practiced with the described steps performed in an order other than the order described herein. It further should be understood that certain steps could be performed simultaneously, that other steps could be added, or that certain steps described herein could be omitted. In other words, the descriptions of processes herein are provided for the purpose of illustrating certain embodiments, and should in no way be construed so as to limit the claims.

Claim 1:
A light detection and ranging, LIDAR, sensor (<NUM>), comprising:
an optical pulsed transmitter (<NUM>); and
an optical receiver (<NUM>), wherein the receiver (<NUM>) includes:
a plurality of pixels (<NUM>), wherein each pixel (<NUM>) includes a receiver circuit (<NUM>),
wherein each receiver circuit (<NUM>) includes:
a photosensitive input circuit (<NUM>) having at least two terminals (<NUM>, <NUM>), wherein a first terminal (<NUM>) is coupled to a detector voltage supply and a second terminal (<NUM>) is coupled to a pulse voltage node;
a logarithmic-signal circuit (<NUM>) including at least one PN junction (<NUM>), wherein the P-type terminal (<NUM>) of the PN junction(<NUM>) is coupled to the pulse voltage node and the N-type terminal (<NUM>) of the PN junction (<NUM>) coupled to a constant potential, and
an impedance-reducing circuit (<NUM>) connected between the photosensitive input circuit (<NUM>) and the pulse voltage node, wherein the impedance-reducing circuit (<NUM>) is electrically coupled to the photosensitive input circuit (<NUM>) and to the logarithmic-signal circuit (<NUM>), the impedance-reducing circuit (<NUM>) including at least a common-gate transistor (<NUM>) coupled to the pulse voltage node,
wherein the impedance-reducing circuit (<NUM>) includes a bias transistor (<NUM>) wherein the bias transistor (<NUM>) provides DC bias current to the common-gate transistor (<NUM>).