Patent Description:
In a network switch engine, due to an expectation for improving performance indicators and limitations of area of a chip, resources and industry, the chip cannot meet the expectation for improving performances by increasing dominant frequency and stacking resources without a limitation, and a method to achieve low redundancy of space of the chip and low consumption of area of the chip is desired to improve performances of the chip.

In chip designs of existing arts, a resource space of the chip is used in different ways in different application scenarios, in a big data processing scene, since a packet with a small packet length is generated and the chip can only store the packet with the small packet length according to a row address, during the chip processing the packet with the small packet length, each row can only store one packet with the small packet length, a large amount of storage space is wasted, and the storage area of the chip is designed to be relatively large to process the packet with the small packet length, thereby a problem of excessive power consumption is caused.

Patent Application <CIT> discloses a method and apparatus for controlling memory access operations of a pipelined processor using a "write queue", wherein the write queue temporarily stores addresses of writes not yet made in memory, the use of a "write queue" for delaying the reading of memory locations into which data will be written by write operations waiting in the write queue.

Patent Application <CIT> discloses that the bitmap table is divided into a plurality of areas each containing at least one bit; an idleness status of each of the areas is determined and recorded in accordance with an unoccupied status of the bit in the area; and a management on a buffer address pointer is performed in accordance with the recorded idleness status of each of the areas, in the case that as a few as possible resources are consumed, the capability in buffer management is improved to a maximal extent, and the demand of a large bandwidth for a large buffer can satisfied.

Patent Application <CIT> discloses that free resource blocks of a buffer memory are added into the resource block queue, whether a free resource block exists in the resource block queue is determined when a request arrives, if the free resource block exists in the resource block queue, buffer memory data of the request are write into the free resource block, and the free resource block is moved out of the resource block queue, when a resource block releasing condition is met, buffer memory data in a corresponding resource block is released, the released resource block is added into the resource block queue.

With regard to the above and other aspects of the present application and implementations thereof, further explanation is provided in the brief description of drawings, the detailed description of embodiments and the claims.

In order to make purposes, technical solutions, and advantages of the present application clearer, embodiments of the present application are described below with reference to the accompanying drawings. It should be noted that the embodiments of the present application and characteristics in the embodiments may be combined with each other if no conflict is incurred.

Since a memory in a chip stores a packet according to a row address, each row in the memory can store only one packet, during the chip being applied to big data processing, a packet with a small packet length is generated in the processing process, the length of the packet is smaller than a length of a common packet, during the chip writing and reading the packet with the small packet length, a large amount of storage space of the memory is wasted, accordingly, a relatively large memory is desired to be configured for the chip, so that an area of the chip is relatively large and a power consumption thereof is excessive. According to the present application, a row address and a column address in a cache are used for caching a plurality of packets with small packet lengths or caching small packet fragments, and then packets in the cache are stored in the memory at one time, a problem that each packet with a small packet length occupies one address in the memory is solved, a utilization rate of the storage space is improved, the area of the chip is reduced, and the power consumption of the chip is reduced.

<FIG> is a structural schematic diagram of an on-chip cache apparatus according to the present application, and referring to <FIG>, the on-chip cache apparatus provided in the present application is suitable for processing packets in a chip, the apparatus may be implemented by software and/or hardware, and may generally be integrated in the chip. The on-chip cache apparatus provided in the present application may include a read/write processing module <NUM>, a cache module <NUM>, and a memory module <NUM>.

In some implementations, the on-chip cache apparatus in the chip mainly includes the read/write processing module <NUM>, the cache module <NUM>, and the memory module <NUM>, the read/write processing module <NUM> may be a hardware processing circuit configured to acquire packets from an access source and read packets to the access source, the cache module <NUM> may be a cache queue formed by one or more cache registers configured to cache packets, and the memory module <NUM> may be a random access memory (RAM) configured to exchange packets with the access source in the chip.

The read/write processing module <NUM> is connected with the cache module <NUM> and the memory module <NUM> respectively, and is configured to store packets into the cache module <NUM> and the memory module <NUM>, read packets stored in the cache module <NUM> and the memory module <NUM>, and transfer packets cached in the cache module <NUM> to the memory module <NUM> for storing.

In some implementations, the read/write processing module <NUM> is configured to write packets into the chip and read packets from the chip, and is connected with the cache module <NUM> and the memory module <NUM>, so as to write packets into the cache module <NUM> and the memory module <NUM>. For example, the packets may be written into the cache module <NUM> first, and in response to that the number of the packets stored in the cache module <NUM> exceeds a threshold value or a number of occupied cache registers <NUM> in the cache module <NUM> exceeds a threshold value, the packets stored in the cache module <NUM> may be transferred and written into the memory module <NUM>, so as to simultaneously write a plurality of packets into the memory module <NUM>, and improve an utilization rate of the storage space. The read/write processing module <NUM> is further configured to read packets stored in the cache module <NUM> and the memory module <NUM>, for example, the read/write processing module <NUM> may read packets from the cache module <NUM>, and then read packets from the memory module <NUM>; or may read packets from the memory module <NUM> first, and then read packets from the cache module <NUM>.

The cache module <NUM> may be connected with the cache module <NUM> through the read/write processing module <NUM>, and may include at least one cache register <NUM> configured to temporarily cache packets.

In some implementations, the cache module <NUM> is a cache register group, and includes at least one cache register <NUM>, a packet may be cached in the cache register <NUM>, and further, after the packet is cached, a descriptor of the cache register <NUM> may be generated, the descriptor may include a row address and a column address of storing the packet, the row address and the column address can identify a position of the cache register <NUM> in the cache module <NUM>. In the on-chip cache apparatus provided in the present application, the cache module <NUM> can perform a temporary storage function, the packet may be stored in one or more cache registers <NUM>, in response to that the packet is a common packet, a length of the packet may exceed a bit width of the cache register <NUM>, a plurality of cache registers <NUM> may be used to store one packet, and in response to that the packet is a packet with a small packet length, the length of the packet may be smaller than or equal to the bit width of the cache register <NUM>, and the packet may be cached in one cache register <NUM>.

The memory module <NUM> is connected to the read/write processing module <NUM>, and is configured to store the packets cached by the cache module <NUM>.

In some implementations, the memory module <NUM> stores packets received by the read/write processing module <NUM>, and the memory module <NUM> can simultaneously store one or more packets, for example, the read/write processing module <NUM> can store a threshold number of packets cached in the cache module <NUM> into the memory module <NUM>, and the threshold number can ensure that a length of the one or more packets stored simultaneously does not exceed a bit width corresponding to a row address of the memory module <NUM>, so as to ensure that packets are successfully stored.

The on-chip cache apparatus provided in the present application includes the read/write processing module, the cache module, and the memory module, the read/write processing module writes packets into the cache module, and then writes packets cached in the cache module into the memory module, the read/write processing module reads packets stored in the cache module and the memory module, and caches a plurality of packets through the cache module, so that a plurality of packets can be written into the memory module simultaneously, an utilization rate of the storage space is improved, a storage area of the chip is reduced, and a power consumption of the chip is reduced.

<FIG> is a structural schematic diagram of an on-chip cache apparatus according to the present application, which is embodied based on that shown in <FIG>, a read processing component and a write processing component are respectively used in the read/write processing module to perform read and write operations on packets, and configuration parameters of the cache module and the memory module are detailed. Referring to <FIG>, the on-chip cache apparatus includes a write processing component <NUM>, a read processing component <NUM>, a cache module <NUM>, and a memory module <NUM>.

In some implementations, the on-chip cache apparatus further includes an idle address management module <NUM> connected with the write processing component <NUM> and the read processing component <NUM>, and configured to manage idle row addresses in the memory module <NUM>, each first-in-first-out buffer (FIFO) in the idle address management module <NUM> stores the idle row addresses, a depth of the FIFO in the idle address management module <NUM> is same as a depth of a random access memory (RAM) in the memory module <NUM>, and the depth of the RAM is determined according to a packet transmission rate (a read/write bandwidth) and a reserved speed-up ratio of the RAM in the memory module <NUM>.

That is, in order to improve efficiency for processing the packets, the idle address management module <NUM> may be configured to uniformly manage the idle row addresses in the memory module <NUM>, the idle row addresses may be row addresses of unoccupied storage spaces in the memory module <NUM>. In the idle address management module <NUM>, the idle row addresses may be stored in a form of FIFO queues, the idle address management module <NUM> may include at least one FIFO queue, and in order to meet an expectation that the idle address management module <NUM> manages all addresses of the memory module <NUM>, the depth of the FIFO in the idle address management module <NUM> may be same as the depth of the RAM in the memory module <NUM>. The depth of the FIFO may indicate a number of FIFO queues storing idle addresses in the idle address management module <NUM>, and the depth of the RAM in the memory module <NUM> may indicate a capability of processing packets simultaneously by the memory module <NUM>, and may indicate a number of RAMs.

In some implementations, the depth of the RAM is related to expectations for a chip, and may be determined by the packet transmission rate (the read/write bandwidth) of the chip and the reserved speed-up ratio, for example, assuming that the number of the packets to be processed per beat is <NUM>, and the speed-up ratio is <NUM>%, the depth of the RAM in the apparatus is <NUM>+<NUM>×<NUM>%=<NUM>. <FIG> is a schematic diagram of a depth relationship according to the present application, and referring to <FIG>, the idle address management module <NUM> may include q FreeFiFo queues, correspondingly, a number of the RAMs in the memory module <NUM> may be q, and the depth of the FIFO in the idle address management module <NUM> is same as the depth of the RAM in the memory module <NUM>.

In some implementations, the write processing component <NUM> is connected to the cache module <NUM>, the memory module <NUM> and the idle address management module <NUM> respectively, and the write processing component <NUM> is configured to receive packets, acquire idle row addresses from the idle address management module <NUM>, store the packets into the cache module <NUM> according to the idle row addresses, and in response to that all the cache registers <NUM> corresponding to the idle row addresses in the cache module <NUM> are occupied, transfer the packets stored in the cache registers <NUM> corresponding to the idle row addresses to the memory module <NUM> for storing.

In some implementations, the write processing component <NUM> is configured to write the packets into the memory module <NUM>, and packet fragments or packets with small packet lengths are cached. The write processing component <NUM> may apply for idle row addresses in the idle address management module <NUM> according to the packets, and cache the packets into the cache module <NUM> according to the idle row addresses, each idle row address may correspond to a plurality of cache registers in the cache module <NUM>, and each cache register in the cache module <NUM> may store one packet fragment or one packet with a small packet length. In response to that a cache register corresponding to one idle row address in the cache module <NUM> stores a packet fragment or a packet with a small packet length, a column address of the cache register <NUM> may be marked as <NUM>, and in response to that all column addresses corresponding to the idle row address are marked as <NUM>, all packet fragments or packets with small packet lengths corresponding to the idle row address may be written into the memory module <NUM> through the write processing component <NUM>. In some implementations, in response to that the write processing component <NUM> determines that all cache registers <NUM> corresponding to the idle row address are occupied, the row address and the column address for caching the packets may be simultaneously stored.

In some implementations, the on-chip cache apparatus may further include a linked list module <NUM>, connected with the read processing component <NUM> and the write processing component <NUM> respectively, and configured to store addresses for storing the packets, the linked list module <NUM> stores the addresses in a form of linked list, and a number of nodes in the linked list is determined according to a number of read delay beats of the memory for storing the addresses when the linked list retrieves a next address.

That is, a storage address of a packet (i.e., an address storing a packet) may be stored by the linked list module <NUM>, the storage address may include a row address and a column address, and the packet may be read from the cache module <NUM> and/or the memory module <NUM> according to the row address and the column address. The linked list module <NUM> may include registers, and may store a head of a linked list, a tail of the linked list and a pointer of the linked list, contents of each linked list may include row addresses and column addresses of stored packets. It should be understood that, considering an influence on a performance of the chip for processing packets and an area of the chip, in order to improve an utilization rate of area of the chip, a number of nodes of the linked list in the linked list module <NUM> may be configured according to a number of read delay beats of the memory module when the linked list retrieves a next address.

The read processing component <NUM> is connected to the cache module <NUM>, the memory module <NUM>, and the idle address management module <NUM> respectively, and is configured to read a packet stored in the cache module <NUM> and/or the memory module <NUM> according to a row address of the packet, and after reading the packet, store the row address of the packet into the idle address management module <NUM>.

In some implementations, the read processing component <NUM> is configured to read a packet, and read packets from the cache module <NUM> and the memory module <NUM> respectively according to addresses of the packets, after each packet is read, a column address in the addresses of the packets may be identified as <NUM>. Further, after all packets corresponding to a row address in the addresses of the packets are read, the read processing component <NUM> may store the row address as an idle row address into the idle address management module <NUM>. Since a storage space corresponding to each row address can store a plurality of packets with small packet lengths or packet fragments, a pointer to the row address is to be released only after all the packets with small packet lengths corresponding to the row address are read, after a descriptor corresponding to the row address is obtained from the linked list in each read operation, the cache module <NUM> is retrieved first, if no row address corresponding to the descriptor is retrieved, then the packets are to be read from the memory module <NUM>, so that a frequency of reading/writing for the memory module <NUM> can be reduced, a power consumption is reduced, and access conflicts can be reduced.

In some implementations, a number of storage components in the memory module <NUM> is determined according to a bit width of a read/write bus of an access source and a length of each packet, and the memory module <NUM> includes a memory with a single-access bus.

In some implementations, an area of the memory is to be reduced by replacing a memory with multiple read/write buses with the memory with the single-access bus, the memory in the memory module <NUM> may be the memory with the single-access bus, a space size of each row address of the RAM in the memory module <NUM> may be determined by a bit width of a bus of the access source, and according to a length of each packet, it is determined how many storage components, for storing packets with small packet lengths or packet fragments, may be divided from each row address. For example, assuming that a length of the packet with a small packet length is <NUM> bytes, and a width of each row address is <NUM> bytes, in a case where a maximum of six packets with small packet lengths can be written in each period, the row address in the memory module <NUM> is desired to be divided into six storage components for storing the packets with the small packet lengths or the packet fragments.

In some implementations, the cache module <NUM> includes at least one cache register group, the cache register group includes at least one cache register, a number of cache register groups in the cache module <NUM> may be determined according to a number of read delay beats of a descriptor of the cache register and a number of reserved bursts to be processed, a number of cache registers in each cache register group is determined based on a number of storage components corresponding to an address space of a row address in the memory module <NUM>.

In some implementations, the cache module <NUM> includes a plurality of cache register groups, each cache register group includes a plurality of cache registers, a storage space of each cache register corresponds to a column address of the RAM of the memory module <NUM>, a storage space corresponding to the row address of the memory module <NUM> may be divided by caching the packets with small packet lengths or the packet fragments in the cache registers, the packets with the small packet lengths or the packet fragments in multiple cache registers may be stored into one row address of the RAM in the memory module <NUM>, a storage space of each cache register is same as a storage space corresponding to one storage component in the memory module <NUM>, and the cache register may correspond to a column address of the storage component. The number of cache registers in the cache module <NUM> may be related to hardware parameters of the memory module <NUM>, and may be determined by the number of the read delay beats of the descriptor of the cache register and the number of the reserved bursts to be processed.

In some implementations, the on-chip cache apparatus further includes a conflict handling module connected with the read processing component <NUM> and the write processing component <NUM> respectively, and configured to process an abnormal conflict for reading and/or writing a packet in the cache module <NUM> and/or the memory module <NUM>.

In the existing art, the conflict in a cache RAM may include three types, including a read-write conflict between reading and writing, a write-write conflict between writings and a read-read conflict between readings, and in the on-chip cache apparatus provided in the present application, the cache module <NUM> is configured to cache the packets with the small packet lengths or cache packets fragments, the idle address management module <NUM> can ensure that different idle row addresses are issued, thereby it is ensured that the write-write conflict between writings would not occur. In response to the read-write conflict between reading and writing occurs, only a case where a read operation and a write operation are simultaneously performed on one row address occurs, and in such case, the idle address management module <NUM> removes the row address to be read first, and meanwhile, the write operation is to be performed on the memory module <NUM> after one register group is full, so as to reduce a probability of conflict; in response to the read-read conflict between readings occurs, priority scheduling may be used to ensure that an access source with a higher priority reads data first. For a conflict of accessing the cache register, the conflict is handled according to priorities. A conflict handling mechanism for handling conflicts is implemented in the read/write processing module.

For example, <FIG> is an example diagram of a configuration of an on-chip cache apparatus according to the present application, and referring to <FIG>, in the on-chip cache apparatus provided in the present application, parameters in the read/write processing module, the cache module, and the memory module are configured according to a number of read-write access sources, a product expectation, a read-write bandwidth expectation, a bit width of a read-write bus, a size of a minimum packet length, etc. of the chip, and a conflict type, a conflict handling mode, an implementation mode of the idle address management module, a number of the RAMs, a number of the cache registers, a number of nodes of the linked list, and the like are respectively determined, so that an efficient on-chip cache apparatus is implemented, a utilization rate of a storage space of the chip is improved, an area of the chip is reduced, and a power consumption of the chip is reduced.

<FIG> is a schematic flowchart of an on-chip cache read/write method according to the present application, the on-chip cache read/write method provided in the present application is suitable for processing packets in the chip, and the method may be executed by the on-chip cache apparatus provided in the present application, the on-chip cache apparatus may be implemented by software and/or hardware, and generally may be integrated in the chip, and the method provided in the present application includes the following operations <NUM> to <NUM>.

At operation <NUM>, storing an acquired packet into a cache register of a cache module according to a row address.

The packet may be a packet generated during big data processing, and may include a packet with a common length or a packet with a small packet length, and the packet may be read and written by the on-chip cache apparatus.

In some implementations, the acquired packet may be first cached in the cache register of the cache module, and the packet may be cached according to the row address. In response to that the packet is a common packet (i.e., with a common length), a length of the packet may exceed a storage space of each cache register, the packet may be fragmented into packet fragments, the packet fragments are respectively stored in the cache registers corresponding to the row address in the cache module, each cache register may store one packet fragment; and in response to that the packet is the packet with the small packet length, the packet with the small packet length may be stored in one cache register in the cache module.

At operation <NUM>, in response to that all the cache registers corresponding to the row address are determined to be occupied, transferring packets corresponding to the row address in the cache module to a memory module for storing.

In some implementations, each row address in the cache module may correspond to one cache register group, each cache register group may include a plurality of cache registers, whether the cache register corresponding to the row address is occupied may be determined by determining whether the column address corresponding to the row address is identified as <NUM>, and in response to that all the cache registers corresponding to the row address are occupied, packets stored in the cache registers corresponding to the row address may be transferred to the memory module for storing, and the packets stored in the cache registers may be simultaneously written into one row in a RAM of the memory module. It should be understood that the row address in the cache module may be the same as the row address in the memory module, or row addresses in the cache module and row addresses in the memory module have a corresponding relationship therebetween.

At operation <NUM>, reading a packet stored in at least one of the cache module or the memory module according to an address for reading the packet.

The address for reading the packet may be an address for reading the stored packet, for example, may be a descriptor, and at least includes a row address and a column address of the stored packet.

That is, the stored packet may be read according to the address for reading the packet, and in the present application, packets may be stored in the cache module and the memory module, and may be respectively read from the cache module and the memory module according to addresses for reading the packets, for example, the stored packet may be read from the cache module first, in response to that no packet corresponding to the address for reading the packet exists in the cache module, the stored packet is read from the memory module, and it should be understood that the stored packet may also be simultaneously read from the cache module and the memory module according to the address for reading the packet.

In the on-chip cache read/write method provided in the present application, the acquired packets are stored into the cache registers in the cache module according to the row address, in response to that all the cache registers corresponding to the row address are determined to be occupied, the packets corresponding to the row address in the cache module are transferred to the memory module for storing, and the stored packets in at least one of the cache module or the memory module are read according to the addresses for reading the packets, so that multiple packets can be simultaneously written into the memory module, an utilization rate of the storage space is improved, a storage area of the chip can be reduced, and a power consumption of the chip can be reduced.

<FIG> is a schematic flowchart of an on-chip cache read/write method according to the present application, based on the above, processes of writing and reading packets are further detailed, and referring to <FIG>, the on-chip cache method includes operations <NUM> to <NUM>.

At operation <NUM>, applying for a row address from an idle address management module based on an acquired packet.

The idle address management module may be a module performing unified management on idle row addresses, and row addresses of unoccupied storage spaces may be stored in the idle address management module.

In the operation <NUM>, in response to that a packet from a read-write access source is received, a row address for storing the packet may be applied from the idle address management module, the row address may correspond to a storage space of the cache module and/or the memory module.

At operation <NUM>, for each packet, in response to that cache registers corresponding to the row address are determined to be not completely occupied, storing the packet into the cache register unoccupied.

That is, packets may be cached in the cache module first, and since all the cache registers corresponding to the row address in the cache module are occupied, the packets are desired to be transferred from the cache module to the memory module for storing, and before each packet is stored, whether all the cache registers corresponding to the row address are occupied may be determined, in response to that there is any unoccupied cache register, the packet may be stored in the unoccupied cache register corresponding to the row address.

At operation <NUM>, in response to that all the cache registers corresponding to the row address are determined to be occupied, generating a write descriptor of each cache register, storing the write descriptor as an address for reading the packet into a linked list module, and storing packets cached in the cache registers into storage components in the memory module, a number of the cache registers corresponds to a number of the storage components.

The write descriptor may be information which describes a storage location of the packet, and in particular, may include a row address and a column address of the packet.

In some implementations, in response to that all the cache registers corresponding to any row address are occupied in the cache module, for example, in response to that all column addresses corresponding to the row address are marked as <NUM>, it may be considered that the cache register group in the cache module is fully stored with packets, the packets stored in the cache register group may be transferred from the cache module to the memory module for storing. In order to facilitate a search for stored packets, write descriptors corresponding to the packets may be stored in the linked list module. In the present application, for transferring the packets from the cache module to the memory module for storing, the packets stored in each cache register in the cache module may be stored in one storage component in the memory module, a number of cache registers corresponding to each row address is same as a number of storage components corresponding to the row address, with the cache registers, packets may be stored in the memory module according to column addresses, so that a space occupancy of the packets is improved.

At operation <NUM>, acquiring the address for reading the packet from the linked list module, with the address for reading the packet including at least a row address and a column address.

The address for reading the packet may be a storage address of the packet (i.e., an address storing the packet), and may be used to read the packet.

That is, the storage address of the packet in the cache module and the memory module may be located in the linked list module, a desired address for reading the packet may be acquired by searching linked list information in the linked list module. Further, each address for reading the packet may include a row address and a column address, and in particular, may correspond to one cache register in the cache module or one storage component in the memory module.

At operation <NUM>, determining whether the cache register in the cache module corresponding to the address for reading the packet caches the packet according to the address for reading the packet, in response to that the cache register in the cache module caches the packet, reading the packet stored in the cache module, in response to that the packet is not cached in the cache register of the cache module, determining whether the packet is stored in the memory module according to the address for reading the packet.

In the on-chip cache read/write method provided in the present application, the stored packet may be read from the cache module first, and then read from the memory module, so that the frequency of reading the memory module can be reduced, a power consumption can be reduced, and an occurrence probability of an access conflict can be reduced. That is, the cache register corresponding to the address for reading the packet may be searched according to the address of reading the packet, if the cache register does not store data, the packet is not stored in the cache module, the packet may be searched from the memory module, and if the cache register stores data, the data in the cache register is read out as the packet.

At operation <NUM>, in response to that the memory module is determined to store the packet, reading the packet stored in the memory module.

That is, the storage component in the memory module may be searched according to the address for reading the packet, and in response to that there is data stored in the storage component, the data is read out as the packet, and it should be understood that in response to that no data is stored in the storage component, the packet is determined to be not stored, and an error may be reported.

At operation <NUM>, after all packets stored in any cache register group in the cache memory are read, storing a row address corresponding to the cache register group into the idle address management module.

That is, after the stored packets are read, the storage space is desired to be released, in the on-chip cache read/write method provided in the present application, after all the packets stored in any cache register group in the cache module are read, i.e., after all the packets stored in the cache registers corresponding to any row address are read, the cache registers corresponding to the row address may be cleared, and the row address is stored as an idle address into the idle address management module.

At operation <NUM>, after all the packets stored in storage components in the memory module corresponding to any row address are read, storing the row address into the idle address management module.

That is, since each row address in the memory module may store a plurality of packets with small packet lengths or packet fragments, only after all the packets with the small packet lengths or the packet fragments corresponding to the row address are read, a pointer to the row address in the memory module may be released, and then, by using a mark based on a cache depth, for recovering each column address, the mark of the column address may be set to <NUM>, after marks of all column addresses corresponding to the row address are set to <NUM>, the row address is stored in the idle address management module.

In the on-chip cache read/write method provided in the present application, the row address corresponding to the acquired packet is applied from the idle address management module, the packet is firstly cached in the cache module according to the row address, after all the cache registers corresponding to the row address are occupied, the packet is transferred from the cache register in the cache module to the storage component in the memory module for storing, and the address for reading the packet is stored into the linked list module, for performing a read operation, the address for reading the packet stored in the linked list module is acquired, and the packet is sequentially read from the cache module and the memory module according to the address for reading the packet, after all packets stored in any cache register group or in the storage components corresponding to any row address are read, the row address is stored into the idle address management module, so that an unified management of idle addresses is implemented, a frequency of reading and/or writing the memory module is reduced, a power consumption of the chip is reduced, and a conflict for accessing the packet is reduced.

In some implementations, the on-chip cache read/write method further includes: in response to that the read-write conflict occurs, clearing the idle row address with the conflict in the idle address management module, so that the read processing component in the read/write processing module does not read packets based on the idle row address, and the write processing component in the read/write processing module writes packets based on the idle row address; and in response to that the read-read conflict occurs, reading, by an access source, packets in the read/write processing module according to a priority order.

In the existing art, a conflict in a cache RAM may include three types, including a read-write conflict between reading and writing, a write-write conflict between writings and a read-read conflict between readings, and in the on-chip cache apparatus provided in the present application, the cache module is configured to cache the packets with the small packet lengths or the packets fragments, the idle address management module can ensure that different idle row addresses are issued, thereby it is ensured that the write-write conflict does not occur. In response to that the read-write conflict between reading and writing occurs, only a case where a read operation and a write operation are simultaneously performed on one row address occurs, and in such case, the idle address management module removes the row address to be read first, and meanwhile, the write operation is to be performed on the memory module after one register group is full, so as to reduce a probability of conflict; in response to that the read-read conflict between readings occurs, priority scheduling may be used to ensure that an access source with a higher priority reads data first. For a conflict of accessing the cache register, the conflict is handled according to priorities.

The above description is merely a schematic explanation of the present application, rather than limiting the protection scope of the present application.

The present application may be implemented in hardware or dedicated circuits, software, logics, or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, a microprocessor or other computing devices, although the present application is not limited thereto.

The present application may be implemented by a data processor executing computer program instructions, for example, in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object codes written in any combination of one or more programming languages.

The block diagram of any logical flowchart in the accompanying drawings of the present application may represent program operations; or represent interconnected logic circuits, modules, and functions; or represent a combination of program operations and logic circuits, modules and functions. The computer program instructions may be stored in a computer readable medium such as a storage device. The storage device may be of any type suitable for the local technical environment and may be implemented by using any suitable data storage technology, includes, but is not limited to, a Random Access Memory (RAM), a Read-Only Memory (ROM), an optical storage device and system (a digital video disc (DVD) or a compact disc(CD)) and the like. The computer-readable medium may include a non-transitory storage medium. The data processor may be of any type suitable for the local technical environment, includes, but is not limited to, a general computer, a specific computer, a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and a processor based on a multi-core processor architecture.

Claim 1:
An on-chip cache apparatus, comprising:
a read-write processing module (<NUM>), a cache module (<NUM>) and a memory module (<NUM>),
wherein the read-write processing module (<NUM>) is connected with the cache module (<NUM>) and the memory module (<NUM>) respectively, and is configured to store packets into the cache module (<NUM>) and the memory module (<NUM>), read packets stored in the cache module (<NUM>) and the memory module (<NUM>), and transfer packets cached in the cache module (<NUM>) to the memory module (<NUM>) for storing;
the cache module (<NUM>) is connected with the memory module (<NUM>) through the read-write processing module (<NUM>), and comprises at least one cache register configured to temporarily cache the packets; and
the memory module (<NUM>) is connected with the read-write processing module (<NUM>), and is configured to store the packets cached in the cache module (<NUM>);
characterized by:
the on-chip cache apparatus further comprises: an idle address management module (<NUM>) configured to manage idle row addresses in the memory module (<NUM>), and
wherein the read-write processing module (<NUM>) comprises a write processing component (<NUM>) connected to the cache module (<NUM>), the memory module (<NUM>) and the idle address management module (<NUM>) respectively, and configured to receive the packet, acquire the idle row address from the idle address management module (<NUM>), store the packet into the cache module (<NUM>) according to the idle row address, and in response to that all cache registers corresponding to the idle row address in the cache module (<NUM>) are occupied, transfer packets stored in the cache registers corresponding to the idle row address to the memory module (<NUM>) for storing.