Patent Description:
An integration scale of a system on chip (system on chip, SoC) is increasingly large, and one SoC chip may include hundreds or even thousands of cores (Cores), for example, a circuit module or an intellectual property (intellectual property, IP) module. Each core needs to be tested to ensure normal functions. Specifically, each core includes a test circuit and a tested circuit. The tested circuit generally includes a plurality of input channels (input channels) and a plurality of output channels (output channels). Test circuits of a plurality of cores are coupled through a shared test bus, and the test circuit outputs test excitation from the test bus to the input channel of the tested circuit and outputs a test response from the output channel of the tested circuit to the test bus. Finally, a test objective of the tested circuit is achieved by observing whether the test response meets an expectation.

The test excitation and test response of each core are transmitted through the shared test bus. A test circuit in a current core transparently transmits a test response from another core, or test excitation to be output to a tested circuit in another core. This takes a very short time. The test circuit spends a long time processing test excitation to be input to a tested circuit in the current core, or a test response generated by the tested circuit in the current core. When a transmission distance of the test bus is long, inconsistency in time causes inconsistency of timing of data transmission on each test bus. A transmission rate of the test bus has to be reduced to avoid a data transmission error. Document <CIT> discloses converting scan output (SO) testing data after scan input (SI) testing data is obtained by an internal logic circuit of an IP core. Primary output (PO) testing data is obtained after primary input (PI) test data is passed through the circuit. The SO testing data is compared with an IP core testing pattern. Primary output (PO) testing data is compared with the IP core testing pattern. The SO testing data is output to an output port by scan chains. The PO testing data is obtained by a WBR unit for transmitting from the output port of the IP core to the output port of a testing shell.

Embodiments of this application provide a test circuit, an integrated circuit, an electronic device, and a method for generating a test circuit, to implement consistency of timing of data transmission on a test bus and improve a transmission rate of the test bus.

According to a first aspect, a test circuit is provided, including: a first input bus, a second input bus, a first output bus, a second output bus, a first dynamic routing unit DRU, and a first register. The first input bus is configured to be coupled to an input channel of a tested circuit through the first DRU, and the first output bus is configured to be coupled to an output channel of the tested circuit through the first DRU. The second input bus is configured to be coupled to the second output bus through the first register. In a clock cycle: the first DRU is configured to output test excitation from the first input bus to the input channel of the tested circuit, and output a test response from the output channel of the tested circuit to the first output bus; or the first DRU is configured to output data from the first input bus to the first output bus; and the first register is configured to output data from the second input bus to the second output bus.

According to the foregoing test circuit provided in this embodiment of this application, a quantity of DRUs coupled to each first input bus is the same as a quantity of registers coupled to each second input bus, so that a delay of outputting test excitation to a tested circuit in a current core through a DRU and outputting a test response through the DRU, a delay of transparently transmitting data through the DRU, and a delay of transparently transmitting data through a register coupled to the second input bus in are the same. This implements consistency of timing of data transmission on the test bus, and improves a transmission rate of the test bus.

In a possible implementation, the test circuit further includes a second DRU, a second register, and a selection circuit. The first input bus is configured to be coupled to the input channel of the tested circuit through the first DRU, the second DRU, and the selection circuit, and the first output bus is configured to be coupled to the output channel of the tested circuit through the first DRU and the second DRU. The second input bus is configured to be coupled to the second output bus through the first register and the second register; and the selection circuit is configured to select the first DRU or the second DRU to be coupled to the input channel of the tested circuit. This application does not pose a limitation on one first input bus being coupled to one or two DRUs, and one second input bus is coupled to one or two registers. A quantity of DRUs coupled to the first input bus is the same as a quantity of registers coupled to the second input bus, so that each input bus has a same delay in transmitting data. When a transmission distance of the test bus is long, inconsistency of timing of data transmission on each input bus can be avoided. In this way, a transmission speed of the test bus is improved.

In a possible implementation, in a first clock cycle, the first DRU is configured to output the test excitation to the second DRU; and in a second clock cycle, the selection circuit selects the second DRU to be coupled to the input channel of the tested circuit, and the second DRU is configured to output the test excitation to the input channel of the tested circuit, and output the test response to the first output bus; or in a second clock cycle, the selection circuit selects the first DRU to be coupled to the input channel of the tested circuit, and the first DRU is configured to output the test excitation to the input channel of the tested circuit, and output the test response to the first output bus. In a conventional technology, because a quantity of pins (namely, bus bandwidths) of a chip for inputting test excitation and outputting test responses is limited, to make full use of the bus bandwidths, complete test excitation output to a core may be split into a plurality of parts and transmitted to the bus in a time-sharing manner. If these parts are input to an input channel of a tested circuit, an incorrect test response is generated. However, for the test circuit provided in this embodiment of this application, one test cycle may include two clock cycles. No matter in which clock cycle the test excitation is input, and no matter whether the test excitation is separately input in two clock cycles, the test excitation may be output to the input channel of the tested circuit in the second clock cycle, so that all parts of the test excitation that are input in a time-sharing manner are input to the input channel of the tested circuit at the same time, and this avoids generating an incorrect test response.

In a possible implementation, the selection circuit includes a first AND gate, a second AND gate, and a second selector, where a first input of the second AND gate performs phase inversion on an input signal. An output of the first AND gate is coupled to the first DRU to output a first signal to the first DRU, an output of the second AND gate is coupled to the second DRU to output a second signal to the second DRU, a first input of the first AND gate and the first input of the second AND gate are coupled to a control end of the second selector and are configured to input a third signal, a second input of the first AND gate and a second input of the second AND gate are coupled and are configured to input a fourth signal. Two inputs of the second selector are respectively coupled to the first DRU and the second DRU, and an output of the second selector is configured to be coupled to the input channel of the tested circuit. The first signal is used to control the first DRU whether to output the test excitation to the input channel of the tested circuit, the second signal is used to control the second DRU whether to output the test excitation to the input channel of the tested circuit, the third signal is used to control the selection circuit to select the first DRU or the second DRU to be coupled to the input channel of the tested circuit, and the fourth signal is used to control the first DRU or the second DRU whether to output the test excitation to the input channel of the tested circuit. This implementation provides a possible structure of the selection circuit.

In a possible implementation, the first DRU includes a third register and a third selector. A data input of the third register is configured to be coupled to the first input bus, a data output of the third register is configured to be separately coupled to a second input of the third selector and the input channel of the tested circuit, a first input of the third selector is configured to be coupled to the output channel of the tested circuit, an output of the third selector is configured to be coupled to the first output bus, a control end of the third selector is configured to input a fifth signal, and the fifth signal is used to control the third selector to connect the first input or the second input to the output. When the third selector selects that the first input is connected to the output, the third selector may output the test excitation to the input channel of the tested circuit in one clock cycle, and output the test response from the output channel of the tested circuit.

In a possible implementation, the test circuit further includes: a reset input bus, a reset output bus, and a plurality of fourth registers. A quantity of the fourth registers is equal to a quantity of registers coupled to the second input bus; the reset input bus is coupled to the reset output bus through the plurality of fourth registers, the reset input bus is configured to input a reset signal, and the reset output bus is configured to output, to the test circuit, the reset signal delayed by the plurality of fourth registers. A difference between a time at which the reset signal is input from the reset input bus and a time at which the reset signal is output from the reset output bus is equal to a difference between a time at which data is input from the input bus and a time at which the data is output from the output bus. For each core, a difference between a time at which the test circuit is started and a time at which the data arrives is the same, which facilitates calculation of a time at which the state machine of the test circuit in each core starts to output a capture enable signal.

In a possible implementation, the test circuit further includes a plurality of fifth registers, where the first input bus and the second input bus each are coupled to A fifth registers, and A is a positive integer. In this way, data input by each input bus is input to the test circuit after a same delay. When a transmission distance of the test bus is long, inconsistency of timing of data transmission on each input bus can be avoided. In this way, a transmission speed of the test bus is improved.

In a possible implementation, the test circuit further includes a plurality of sixth registers, where the first output bus and the second output bus each are coupled to B sixth registers, and B is a positive integer. In this way, the data output by each output bus is transmitted to a next core after a same delay. When the transmission distance of the test bus is long, inconsistency of timing of data transmission on each output bus can be avoided. In this way, the transmission speed of the test bus is improved.

In a possible implementation, the test circuit further includes a first selector. An output of the first selector is configured to be coupled to one first output bus or one second output bus; two inputs of the first selector are respectively coupled to one first input bus and one second input bus; or configured to be respectively coupled to two first input buses, or configured to be respectively coupled to two second input buses. The first selector may implement that the test circuit is in a pass-through mode, that is, a sequence number of the output bus is the same as a sequence number of the coupled input bus; or may implement that the test circuit is in a shift mode, that is, a sequence number of the output bus is in a shift relationship with a sequence number of the coupled input bus.

According to a second aspect, an integrated circuit is provided, including a plurality of cores. Each core includes a tested circuit and the test circuit according to the first aspect and any implementation of the first aspect, and test circuits of the plurality of cores are coupled through a test bus.

According to a third aspect, an electronic device is provided, including a printed circuit board and the integrated circuit according to the second aspect that is disposed on the printed circuit board.

According to a fourth aspect, a method for generating a test circuit is provided. The method includes: obtaining a bandwidth of an input bus or a bandwidth of an output bus of a test bus, and a bandwidth of an input channel and a bandwidth of an output channel of a tested circuit in each core; and determining, based on the bandwidth of the input bus or the bandwidth of the output bus of the test bus, and the bandwidth of the input channel and the bandwidth of the output channel of each tested circuit, a quantity of dynamic routing units DRUs or registers coupled to each input bus in each test circuit, and generating the test circuit according to the first aspect and any implementation of the first aspect.

In a possible implementation, a quantity K of dynamic routing units or registers coupled to each input bus in a test circuit in each core is obtained in the following manner: <MAT>, where CI represents a bandwidth of an input channel of a tested circuit in a core, CO represents a bandwidth of an output channel of the tested circuit in the core, and n represents the bandwidth of the input bus or the bandwidth of the output bus.

According to a fifth aspect, a circuit test method is provided, and is used to test a tested circuit by using the test circuit according to the first aspect and any implementation of the first aspect. The method includes: generating configuration information and test excitation, where the configuration information is used to configure a frequency division ratio of the test circuit and select an input channel for coupling a first dynamic routing unit DRU or a second DRU to the tested circuit, to input the test excitation to the tested circuit; inputting the configuration information and the test excitation into the tested circuit; receiving a test response of the tested circuit; and determining, based on the test response, whether the tested circuit is normal.

According to a sixth aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores instructions, and when the instructions are executed by a processor, the method according to the second aspect is performed.

According to a seventh aspect, a computer program product including instructions is provided. When the instructions are executed by a processor, the method according to the second aspect is performed.

For technical effects of the second aspect to the seventh aspect, refer to technical effects of any one of the first aspect and the implementations of the first aspect.

The terms "first", "second" and the like in embodiments of this application are merely intended for description, and shall not be understood as an indication or implication of relative importance or an implicit indication of a quantity of indicated technical features. Therefore, features defined with "first", "second", and the like may explicitly or implicitly include one or more such features.

It should be noted that, in this application, terms such as "an example" or "for example" are used to represent giving an example, an illustration, or a description. Any embodiment or design scheme described as an "example" or "for example" in this application should not be explained as being more preferred or having more advantages than another embodiment or design scheme. Exactly, use of the term "example", "for example", or the like is intended to present a related concept in a specific manner.

In this application, unless otherwise specified and limited, the terms "coupling" and "connection" should be understood in a broad sense. For example, the terms "coupling" and "connection" may refer to a physical direct connection, or may refer to an electrical connection implemented through an intermediate medium, for example, a connection implemented through a resistor, an inductor, a capacitor, or another electronic component.

An embodiment of this application provides an electronic device. The electronic device includes a printed circuit board and an integrated circuit disposed on the printed circuit board. The electronic device may be electronic products such as a mobile phone (mobile phone), a tablet computer (pad), a computer, an intelligent wearable product (for example, a smartwatch or a smart band), a virtual reality (virtual reality, VR) terminal device, and an augmented reality (augmented reality, AR) terminal device. A specific form of the electronic device is not limited in embodiments of this application.

As shown in <FIG>, the integrated circuit in the electronic device includes a plurality of cores, each core includes a tested circuit <NUM> and a test circuit <NUM> corresponding to the tested circuit <NUM>, and the tested circuit <NUM> and the corresponding test circuit <NUM> may be disposed separately or integrated together. Different tested circuits <NUM> in each integrated circuit may implement a same function or different functions. Test circuits <NUM> of the plurality of cores are coupled through a test bus <NUM> of the test circuit <NUM>, test excitation input by the test bus <NUM> is input to the corresponding tested circuit <NUM> through the test circuit <NUM>, and a test response of the tested circuit <NUM> is output through the test bus <NUM> of the test circuit <NUM>, to test functions of a plurality of tested circuits <NUM>.

As shown in <FIG>, in a core, the foregoing tested circuit <NUM> may include a scan structure <NUM>. The foregoing test bus <NUM> may include a plurality of input buses (for example, in[<NUM>] to in[<NUM>]), a plurality of output buses (for example, out[<NUM>] to out[<NUM>]), an internal joint test action group (internal joint test action group, IJTAG) (IEEE <NUM> standard) bus ijtag, a reset input bus rst_in, a reset output bus rst_out, and a clock bus clk. In addition to the test bus <NUM>, the foregoing test circuit <NUM> further includes a plurality of first dynamic routing units (dynamic routing units, DRUs) <NUM>, a plurality of first registers <NUM>, a plurality of first selectors <NUM>, a debugging interface <NUM>, a frequency divider (divider, DIV) <NUM>, a state machine (also referred to as a finite state machine (finite state machine, FSM)) <NUM>, and a plurality of fourth registers <NUM>.

Optionally, as shown in <FIG> or <FIG>, the foregoing test circuit <NUM> further includes a plurality of second DRUs <NUM> coupled to a plurality of first DRUs <NUM>, a plurality of selection circuits <NUM>, and a plurality of second registers <NUM> coupled to a plurality of first registers <NUM>. Optionally, as shown in <FIG>, the test circuit <NUM> further includes a plurality of fifth registers <NUM>, a plurality of sixth registers <NUM>, and a plurality of seventh registers <NUM>.

As shown in <FIG>, a tested circuit (the scan structure <NUM>) includes a plurality of input channels channel_in and a plurality of output channels channel_out. Each input channel channel_in is used to input one bit of test excitation. After the test excitation is run in the tested circuit (the scan structure <NUM>), a test response is output through the output channel channel_out, and each output channel channel_out is used to output one bit of the test response. Bandwidths of the input channel channel_in and the output channel channel_out may be the same or different. An example in which a bandwidth of the input channel channel_in and a bandwidth of the output channel channel_out each are <NUM> is used in this application, but is not intended to limit this application.

As shown in <FIG>, a plurality of inputs of the frequency divider <NUM> are separately coupled to an IJTAG bus ijtag, a clock bus clk, and a reset output bus rst_out, and an output of the frequency divider <NUM> is coupled to a tested circuit (the scan structure <NUM>). A debugging signal from the IJTAG bus ijtag is used to control a frequency division ratio of the frequency divider <NUM>, and a reset signal from the reset output bus rst_out is used to control start and stop of the frequency divider <NUM>. The frequency divider <NUM> obtains a frequency division clock signal by performing frequency division on a clock signal from the clock bus clk, and outputs the frequency division clock signal to the tested circuit (the scan structure <NUM>) through a scanning clock bus scan_clk, to drive the tested circuit (the scan structure <NUM>) to run. A formula for calculating the frequency division ratio K of the frequency divider <NUM> is: <MAT>. CI represents a bandwidth of an input channel channel_in of a tested circuit (the scan structure <NUM>) in a core, CO represents a bandwidth of an output channel channel_out of a tested circuit (the scan structure <NUM>) in a core, and n represents a bandwidth of an input bus in or a bandwidth of an output bus out. It should be noted that K values of cores calculated according to the formula may be different. When a plurality of cores are coupled through a test bus, a greatest value among K values of all cores is selected as a final K value of each core, to ensure that transmission delays of the cores are the same, and reduce complexity of test excitation. An example in which K is <NUM> is mainly used to describe this application, but is not intended to limit this application.

As shown in <FIG>, an input of a debugging interface <NUM> is coupled to the IJTAG bus ijtag, and an output of the debugging interface <NUM> is coupled to a control end of the plurality of first selectors <NUM> through a bus twist bus bus_twist. The debugging interface <NUM> outputs a twist control signal to the control end of the first selector <NUM> based on the debugging signal from the IJTAG bus ijtag through the bus twist bus bus_twist. As shown in <FIG> and <FIG>, a plurality of other outputs of the debugging interface <NUM> are separately coupled to a control end of a second selector <NUM>, a first input of a first AND gate <NUM>, and a first input of a second AND gate <NUM> of each selection circuit <NUM> through selection lines sel (for example, sel <NUM> to sel <NUM>). The debugging interface <NUM> outputs a selection signal to the first input of the first AND gate <NUM>, the first input of the second AND gate <NUM>, and the control end of the second selector <NUM> through selection lines sel (for example, sel <NUM> to sel <NUM>) based on the debugging signal from the IJTAG bus ijtag.

As shown in <FIG>, a plurality of inputs of an FSM <NUM> are separately coupled to the IJTAG bus ijtag and the reset output bus rst_out, the FSM <NUM> is coupled to a tested circuit (the scan structure <NUM>) through a control line ctrl and a scanning enable line en, and the FSM <NUM> is coupled to the first DRU <NUM> through a capture enable line cap_en. As shown in <FIG> and <FIG>, the FSM <NUM> is coupled to a second input of the first AND gate <NUM> and a second input of the second AND gate <NUM> of the selection circuit <NUM> through the capture enable line cap_en, and is further coupled to the first DRU <NUM> and the second DRU <NUM>.

The debugging signal from the IJTAG bus ijtag is used to control state transition of the FSM <NUM>, and the reset signal from the reset output bus rst_out is used to control start and stop of the FSM <NUM>. The FSM <NUM> outputs a control signal to the tested circuit (the scan structure <NUM>) through the control line ctrl, to control a scanning test state of the tested circuit (the scan structure <NUM>). The FSM <NUM> outputs a scanning enable signal to the tested circuit (the scan structure <NUM>) through the scanning enable line en, to enable or disable a scanning test mode of the tested circuit (the scan structure <NUM>).

The FSM <NUM> outputs a capture enable signal through the capture enable line cap_en. For the structure shown in <FIG>, the capture enable signal controls the first DRU <NUM> to transparently transmit data from the input bus in, or inputs stored test excitation to an input channel channel_in of the tested circuit (the scan structure <NUM>) and outputs a test response from an output channel channel_out of the tested circuit (the scan structure <NUM>). For <FIG> or <FIG>, the capture enable signal is used to output capture enable signals to the second input of the first AND gate <NUM> and the second input of the second AND gate <NUM> of each selection circuit <NUM>, to control, by using the selection circuit <NUM>, the first DRU <NUM> or the second DRU <NUM> to transparently transmit data from the input bus in, or input the stored test excitation to the input channel channel_in of the tested circuit (the scan structure <NUM>) and output the test response from the output channel channel_out of the tested circuit (the scan structure <NUM>). Therefore, there are two states of the capture enable signal output by the FSM <NUM>. For example, when the capture enable signal is at a low level ("<NUM>"), the first DRU <NUM> or the second DRU <NUM> is controlled to transparently transmit the data from the input bus in. When the capture enable signal is at a high level ("<NUM>"), the first DRU <NUM> or the second DRU <NUM> is controlled to output the stored test excitation to the input channel channel_in of the tested circuit (the scan structure <NUM>), and outputs the test response from the output channel channel_out of the tested circuit (the scan structure <NUM>) to the output bus out. The capture enable signal output by the FSM <NUM> changes periodically, so that a DRU and the tested circuit (the scan structure <NUM>) may periodically exchange data at a toggle edge of the frequency division clock signal. This cycle is called a test cycle, and a length of the test cycle is equal to K*CLK, where K is the foregoing frequency division ratio, and CLK is a cycle of the clock signal of the clock bus clk. Timing of inputting the test excitation into the input channel channel_in of the tested circuit (the scan structure <NUM>) from the first DRU <NUM> or the second DRU <NUM> matches the toggle edge of the frequency division clock signal. For details, refer to the following descriptions about the first DRU <NUM> and the second DRU <NUM>.

Each selection circuit <NUM> includes the first AND gate <NUM>, the second AND gate <NUM>, and the second selector <NUM>, where the first input of the second AND gate <NUM> performs phase inversion on the input signal. The first input of the first AND gate <NUM> and the first input of the second AND gate <NUM> are coupled to the control end of the second selector <NUM>, and are configured to input a selection signal (a third signal) from the debugging interface <NUM>. The second input of the first AND gate <NUM> and the second input of the second AND gate <NUM> are coupled, and are configured to input a capture enable signal (a fourth signal) from the FSM <NUM>. An output of the first AND gate <NUM> is coupled to the first DRU <NUM>, to output the first signal to the first DRU <NUM>. An output of the second AND gate <NUM> is coupled to the second DRU <NUM>, to output a second signal to the second DRU <NUM>. Two inputs of the second selector <NUM> are respectively coupled to the first DRU <NUM> and the second DRU <NUM>, and an output of the second selector <NUM> is configured to be coupled to an input channel channel_in of the tested circuit (the scan structure <NUM>), to select the first DRU <NUM> or the second DRU <NUM> to be coupled to an input channel channel_in of the tested circuit (the scan structure <NUM>).

The selection circuit <NUM> is configured to select, based on the selection signal from the debugging interface <NUM>, the first DRU <NUM> or the second DRU <NUM> to be coupled to the input channel channel_in of the tested circuit (the scan structure <NUM>). <FIG> or <FIG> is used as an example. When a capture enable signal output by the FSM <NUM> through the capture enable line cap_en is at a high level ("<NUM>"), if the selection signal output by the debugging interface <NUM> through the selection line sel is at a high level ("<NUM>"), the first AND gate <NUM> outputs a high level ("<NUM>"), and the second AND gate <NUM> outputs a low level ("<NUM>") because the first input performs phase inversion, the second selector <NUM> selects the first input to be connected to the output, so that a data output of a third register <NUM> (shown in <FIG>) in the first DRU <NUM> is coupled to an input channel channel_in of the tested circuit. When a capture enable signal output by the FSM <NUM> through the capture enable line cap_en is at a high level ("<NUM>"), if the selection signal output by the debugging interface <NUM> through the selection line sel is at a low level ("<NUM>"), the first AND gate <NUM> outputs a low level ("<NUM>"), the second AND gate <NUM> outputs a high level ("<NUM>") because the first input performs phase inversion, and the second selector <NUM> selects the second input to be connected to the output, so that a data output of a third register <NUM> (shown in <FIG>) in the second DRU <NUM> is coupled to an input channel channel_in of the tested circuit.

Bandwidths of the input bus in and the output bus out are the same. For example, an example in which the bandwidth is <NUM> bits is used in this application, but is not intended to limit this application. The input bus in is configured to input test excitation or input a test response from a tested circuit in another core, and the output bus out is configured to output a test response of a tested circuit in the current core or transparently transmitted test excitation or test response. In this application, an input bus in coupled to a DRU (for example, the first DRU <NUM> and the second DRU <NUM>) may be referred to as a first input bus in, for example, input buses in[<NUM>] to in[<NUM>] in <FIG>. An output bus out coupled to a DRU (for example, the first DRU <NUM> and the second DRU <NUM>) may be referred to as a first output bus out, for example, output buses out[<NUM>] to out[<NUM>] in <FIG> when the first selector <NUM> connects the first input to the output. An input bus in that is not coupled to the DRU is referred to as a second input bus in, for example, input buses in[<NUM>] to in[<NUM>] in <FIG>. An output bus out that is not coupled to the DRU is referred to as a second output bus out, for example, output buses out[<NUM>] to out[<NUM>] in <FIG> when the first selector <NUM> connects the first input to the output. A ratio of the first input bus in to the second input bus in is not limited in this application. There may be a plurality of first input buses in and a plurality of second input buses in. A ratio of the first output bus out to the second output bus out is not limited. There may be a plurality of first input buses in and a plurality of second input buses in.

The first selector <NUM> includes a first input, a second input, and an output, where the output of the first selector <NUM> is coupled to one first output bus out or one second output bus out. Two inputs of the first selector <NUM> are respectively coupled to one first input bus in and one second input bus in; or are respectively coupled to two first input buses in; or are respectively coupled to two second input buses in. The first selector <NUM> is configured to connect the first input or the second input to the output.

The first input bus in is coupled to an input channel channel_in of the tested circuit (the scan structure <NUM>) through the first DRU <NUM> (and the second DRU <NUM> and the selection circuit <NUM>). An output channel channel_out of the tested circuit (the scan structure <NUM>) is coupled to the first input of the first selector <NUM> through the first DRU <NUM> (and the second DRU <NUM>), and then coupled to the first output bus out. From another perspective, the first input bus in is coupled to the first output bus out through the first DRU <NUM> (and the second DRU <NUM>) and the first selector <NUM>. The second input bus in is coupled to the second input of the first selector <NUM> through the first register <NUM> (and the second register <NUM>), and then coupled to the second output bus out.

In one clock cycle: a bit of test excitation from the first input bus in is output to one input channel channel_in of the tested circuit (the scan structure <NUM>) through the first DRU <NUM> (and one second DRU <NUM>), and a bit of a test response from one output channel channel_out of the tested circuit (the scan structure <NUM>) is output to the first output bus through the first DRU <NUM> (and one second DRU <NUM>); or a bit of data (test excitation or a test response) from the first input bus in is output (that is, transparently transmitted) to the first output bus out through the first DRU <NUM> (and one second DRU <NUM>), and a bit of data (test excitation or a test response) from the second input bus in is output (that is, transparently transmitted) to the second output bus out through the first register <NUM> (and one second register <NUM>).

As shown in <FIG>, when a twist control signal output by the debugging interface <NUM> to the control end of the first selector <NUM> through the bus twist line bus_twist is at low level ("<NUM>"), the first selector <NUM> in a first group (for example, as shown in the "first group") selects the first input to be connected to the output, so that the first DRUs <NUM> (and the second DRUs <NUM>) coupled to the first input buses in (for example, input buses in[<NUM>] to in[<NUM>]) are coupled to the output buses out[<NUM>] to out[<NUM>] (namely, the first output buses out). The first selector <NUM> in a second group (for example, as shown in the "second group") selects the second input to be connected to the output, so that the first registers <NUM> and the second registers <NUM> coupled to the second input buses (for example, the input buses in[<NUM>] to in[<NUM>] in <FIG> or <FIG>) are coupled to the output buses out[<NUM>] to out[<NUM>] (namely, the second output buses out). In this case, the mode is a pass-through mode, that is, a sequence number of the output bus out is the same as a sequence number of the coupled input bus in.

Further, <FIG> or <FIG> is used as an example. When a twist control signal output by the debugging interface <NUM> to the control end of the first selector <NUM> through the bus twist line bus_twist is at a high level ("<NUM>"), the first selector <NUM> in a first group (for example, as shown by the "first group" in <FIG> or <FIG>) selects the second input to be connected to the output, so that the first registers <NUM> and the second registers <NUM> coupled to the second input buses (for example, the input buses in[<NUM>] to in[<NUM>] in <FIG> or <FIG>) are coupled to the output buses out[<NUM>] to out[<NUM>] (namely, the second output buses out). The first selector <NUM> in a second group (for example, the "second group" in <FIG> or <FIG>) selects the second input to be connected to the output, so that the first DRUs <NUM> and the second DRUs <NUM> coupled to the first input buses in (for example, the input buses in[<NUM>] to in[<NUM>] in <FIG> or <FIG>) are coupled to the output buses out[<NUM>] to out[<NUM>] (namely, the first output buses out). In this case, the mode is a shift mode, that is, a shift relationship exists between a sequence number of the output bus out and a sequence number of the coupled input bus in.

As shown in <FIG>, the first DRU <NUM> or the second DRU <NUM> described above includes a third register <NUM> and a third selector <NUM>. A data input of the third register <NUM> is configured to be coupled to a first input bus in, a data output of the third register <NUM> is configured to be separately coupled to a second input of the third selector <NUM> and an input channel channel_in of a tested circuit (a scan structure <NUM>). The third register <NUM> is configured to store data input from the first input bus in, and a first input of the third selector <NUM> is configured to be coupled to an output channel channel_out of the tested circuit (the scan structure <NUM>). A control end of the third selector <NUM> is configured to be coupled to a capture enable line cap_en of an FSM <NUM>. When applied to the first DRU <NUM> in <FIG>, the control end of the third selector <NUM> may be directly coupled to the capture enable line cap_en of the FSM <NUM>. When applied to the first DRU <NUM> in <FIG> and <FIG>, the control end of the third selector <NUM> is indirectly coupled to the capture enable line cap_en of the FSM <NUM> by coupling to the output of the first AND gate <NUM> described above, and inputs a first signal from the first AND gate <NUM>. When applied to the second DRU <NUM> in <FIG> and <FIG>, the control end of the third selector <NUM> is indirectly coupled to the capture enable line cap_en of the FSM <NUM> by coupling to the output of the second AND gate <NUM> described above, and inputs a second signal from the second AND gate <NUM>. The first signal or the second signal is used to control the third selector <NUM> to connect the first input or the second input to the output. The output of the third selector <NUM> is configured to be coupled to an output bus out. When a low level ("<NUM>") is input to the control end of the third selector <NUM>, the third selector <NUM> connects the second input to the output, so that the data stored in the third register <NUM> is output to an output bus out. When a high level (for example, "<NUM>") is input to the control end of the third selector <NUM>, the third selector <NUM> connects the first input to the output, so that a bit of a test response from an output channel channel_out of the tested circuit (the scan structure <NUM>) is output to the first output bus out.

Specifically, when the DRU is used as the first DRU <NUM> in <FIG>, the data input of the third register <NUM> is coupled to a first input bus in, and the data output of the third register <NUM> is coupled to both the second input of the third selector <NUM>, and the first input of a second selector <NUM>, to be coupled to an input channel channel_in of the tested circuit (the scan structure <NUM>) through the second selector <NUM>. The third register <NUM> is configured to store the data input from the first input bus in. The first input of the third selector <NUM> is coupled to an output channel channel_out of the tested circuit (the scan structure <NUM>), the control end of the third selector <NUM> is coupled to the capture enable line cap_en of the FSM <NUM>, and the output of the third selector <NUM> is coupled to the data input of the third register <NUM> in the second DRU <NUM>, to be coupled to a first output bus out.

When the DRU is used as the first DRU <NUM> in <FIG> and <FIG>, the data input of the third register <NUM> is coupled to a first input bus in, and the data output of the third register <NUM> is coupled to both the second input of the third selector <NUM> and the first input of the second selector <NUM>, to be coupled to an input channel channel_in of the tested circuit (the scan structure <NUM>) through the second selector <NUM>. The third register <NUM> is configured to store the data input from the first input bus in. The first input of the third selector <NUM> is coupled to an output channel channel_out of the tested circuit (the scan structure <NUM>), the control end of the third selector <NUM> is coupled to an output of the first AND gate <NUM>, and an output of the third selector <NUM> is coupled to the data input of the third register <NUM> in the second DRU <NUM>, to be coupled to an output bus out through the second DRU <NUM>.

When the DRU is used as the second DRU <NUM> in <FIG> and <FIG>, the data input of the third register <NUM> is coupled to an output of a third selector in the first DRU <NUM>, to be coupled to a first input bus in through the first DRU <NUM>. The data output of the third register <NUM> is coupled to both a second input of the third selector <NUM> and a second input of the second selector <NUM>, to be coupled to an input channel channel_in of the tested circuit (the scan structure <NUM>) through the second selector <NUM>. The third register <NUM> is configured to store data input from the first DRU <NUM>. A first input of the third selector <NUM> is coupled to an output channel channel_out of the tested circuit (the scan structure <NUM>), a control end of the third selector <NUM> is coupled to an output of the second AND gate <NUM>, and an output of the third selector <NUM> is coupled to the first selector <NUM>, to be coupled to an output bus out through the first selector <NUM>.

The following describes a working principle of a first DRU <NUM> coupled to a first input bus in in <FIG>.

When the capture enable signal output by the FSM <NUM> through the capture enable line cap_en is at a low level ("<NUM>"), the first DRU <NUM> is in a pass-through mode, and in each clock cycle, the first DRU <NUM> outputs data (for example, a bit of test excitation or a bit of a test response) from one first input bus in. When the capture enable signal output by the FSM <NUM> through the capture enable line cap_en is at a high level ("<NUM>"), in each clock cycle, the first DRU <NUM> outputs a bit of test excitation from one first input bus in to one input channel channel_in of the tested circuit (the scan structure <NUM>), and outputs one bit of a test response from one output channel channel_out of the tested circuit (the scan structure <NUM>).

In addition, for the first register <NUM> coupled to the second input bus in, in each clock cycle, the first register <NUM> outputs data (for example, a bit of test excitation or a bit of a test response) from one second input bus in. Therefore, data transmitted by the first input bus is consistent with data transmitted by the second input bus in terms of timing. This implements consistency of timing of data transmission on the test bus, and improves a transmission rate of the test bus.

The following describes working principles of the first DRU <NUM>, the second DRU <NUM>, and the selection circuit <NUM> that are coupled to one first input bus in in <FIG> and <FIG>.

In a first clock cycle, when the capture enable signal output by the FSM <NUM> through the capture enable line cap_en is at a low level ("<NUM>"), the first DRU <NUM> and the second DRU <NUM> are in a pass-through mode, and the selection circuit <NUM> does not output, to an input channel of the tested circuit (the scan structure <NUM>), a bit of test excitation stored in the first DRU <NUM> or the second DRU <NUM>. The second DRU <NUM> outputs stored data (for example, a bit of test excitation or a bit of a test response) to the output bus out, and the first DRU <NUM> outputs data (for example, a bit of test excitation or a bit of a test response) from one first input bus in to the second DRU <NUM> for storage.

In a second clock cycle, when the capture enable signal output by the FSM <NUM> through the capture enable line cap_en is at a high level ("<NUM>"), if a selection signal output by the debugging interface <NUM> through the selection line sel is at a low level ("<NUM>"), a first signal output by the output of the first AND gate <NUM> is at a low level ("<NUM>"), that is, a low level ("<NUM>") is input to the control end of the third selector <NUM> of the first DRU <NUM>. One bit of test excitation that is from the first input bus in and that is stored in the third register <NUM> of the first DRU <NUM> is output, through the third selector <NUM> of the first DRU <NUM>, to the third register <NUM> of the second DRU <NUM> for storage. A second signal output by the second AND gate <NUM> is at a high level ("<NUM>") because the first input performs phase inversion, that is, the high level ("<NUM>") is input to the control end of the third selector <NUM> of the second DRU <NUM>. The third selector <NUM> of the second DRU <NUM> outputs a bit of a test response from an output channel channel_out of the tested circuit (the scan structure <NUM>) to the first selector <NUM>, so that the bit is output to an output bus out through the first selector <NUM>. A bit that is of test excitation from the first input bus in and that is stored in the third register <NUM> of the second DRU <NUM> is output to the second input of the second selector <NUM>. A low level ("<NUM>") is input to the control end of the second selector <NUM>, and the second selector <NUM> outputs a bit of test excitation stored in the second DRU <NUM> to an input channel channel_in of the tested circuit (the scan structure <NUM>).

In other words, in the second clock cycle, the selection circuit <NUM> selects the second DRU <NUM> to be coupled to an input channel channel_in of the tested circuit (the scan structure <NUM>), the second DRU <NUM> outputs one bit of the stored test excitation to one input channel channel_in of the tested circuit (the scan structure <NUM>), receives a bit of the test response from an output channel channel_out of the tested circuit (the scan structure <NUM>), and outputs the bit to an output bus out.

Alternatively, in the second clock cycle, when the capture enable signal output by the FSM <NUM> through the capture enable line cap_en is at a high level ("<NUM>"), if a selection signal output by the debugging interface <NUM> through the selection line sel is at a high level ("<NUM>"), a first signal output by the output of the first AND gate <NUM> is at a high level ("<NUM>"), that is, a high level ("<NUM>") is input to the control end of the third selector <NUM> of the first DRU <NUM>. The third selector <NUM> of the first DRU <NUM> outputs one bit of the test response from the output channel channel_out of the tested circuit (the scan structure <NUM>) to the data input of the third register <NUM> in the second DRU <NUM>. A bit that is of test excitation from the first input bus in and that is stored in the third register <NUM> of the first DRU <NUM> is output to the first input of the second selector <NUM>. A high level ("<NUM>") is input to the control end of the second selector <NUM>, and the second selector <NUM> outputs a bit of test excitation stored in the first DRU <NUM> to an input channel channel_in of the tested circuit (the scan structure <NUM>). The second AND gate <NUM> outputs a low level ("<NUM>") of a second signal because the first input performs phase inversion, that is, the low level ("<NUM>") is input to the control end of the third selector <NUM> of the second DRU <NUM>, and the third selector <NUM> of the second DRU <NUM> connects the second input to the output, and outputs, to an output bus out, a bit of the test response that is from the first DRU <NUM> and that is stored in the third register <NUM> of the second DRU <NUM>.

In other words, in the second clock cycle, the selection circuit <NUM> selects the first DRU <NUM> to be coupled to an input channel channel_in of the tested circuit (the scan structure <NUM>), the first DRU <NUM> outputs one bit of the test excitation from one first input bus in to one input channel channel_in of the tested circuit (the scan structure <NUM>), receives one bit of the test response from an output channel channel_out of the tested circuit (the scan structure <NUM>), and outputs the bit to the second DRU <NUM> for storage.

The following describes working principles of the first DRU <NUM>, the second DRU <NUM>, and the selection circuit <NUM> that are coupled to N first input buses in, and describes how to input N-bit test excitation to N input channels channel_in of the tested circuit (the scan structure <NUM>) through the first DRU <NUM>, the second DRU <NUM>, and the selection circuit <NUM> that are coupled to the N first input buses in.

When the N bits of test excitation are input from the N first input buses in in the first clock cycle, in the first clock cycle, the capture enable signal output by the FSM <NUM> through the capture enable line cap_en is at a low level ("<NUM>"), and the first DRU <NUM> coupled to the N first input buses in may respectively output the N bits of test excitation to the second DRU <NUM> coupled to the N first input buses in for storage. In the second clock cycle, the capture enable signal output by the FSM <NUM> through the capture enable line cap_en is at a high level ("<NUM>"), N selection signals output by the debugging interface <NUM> through N selection lines sel are at low levels ("<NUM>"), and second DRUs <NUM> coupled to the N input buses are coupled to N input channels channel_in of the tested circuit (the scan structure <NUM>), and N bits of stored test excitation are output to the N input channels channel_in of the tested circuit (the scan structure <NUM>), receive N bits of a test response from N output channels channel_out of the tested circuit (the scan structure <NUM>), and output the N bits to the N output buses out.

When the N bits of the test excitation are input from the N first input buses in in the second clock cycle, in the second clock cycle, the capture enable signal output by the FSM <NUM> through the capture enable line cap_en is at a high level ("<NUM>"), and N selection signals output by the debugging interface <NUM> through the N selection lines sel are at a high level ("<NUM>"). The first DRU <NUM> coupled to the N first input buses in outputs the N bits of the test excitation to the N input channels channel_in of the tested circuit (the scan structure <NUM>), receives the N bits of the test response from the N output channels channel_out of the tested circuit (the scan structure <NUM>), and outputs the N bits to the second DRU <NUM> coupled to the N first input buses in for storage.

When the first n bits of the test excitation are input from the first n first input buses in in the first clock cycle, and the last N-n bits of the test excitation are input from the last N-n first input buses in in the second clock cycle, in the first clock cycle, the capture enable signal output by the FSM <NUM> through the capture enable line cap_en is at a low level ("<NUM>"). The first DRUs <NUM> coupled to the first n first input buses in may respectively output the first n bits of test excitation to the second DRUs <NUM> coupled to the n first input buses in for storage. In the second clock cycle, the capture enable signal output by the FSM <NUM> through the capture enable line cap_en is at a high level ("<NUM>"), N selection signals output by the debugging interface <NUM> through the first n selection lines sel are at low levels ("<NUM>"), and the second DRU <NUM> coupled to the n input buses outputs n bits of stored test excitation to n input channels channel_in of the tested circuit (the scan structure <NUM>), receives n bits of a test response from n output channels channel_out of the tested circuit (the scan structure <NUM>), and outputs the n bits to n output buses out. N-n selection signals output by the debugging interface <NUM> through the last N-n selection lines sel are at high levels ("<NUM>"), and the first DRU <NUM> coupled to the N-n first input buses in outputs the last N-n bits of test excitation to a remaining N-n input channel channel_in of the tested circuit (the scan structure <NUM>). The last N-n bits of the test response are received from the remaining N-n output channels channel_out of the tested circuit (the scan structure <NUM>), and are output to the second DRU <NUM> coupled to the N-n first input buses in for storage.

In a conventional technology, because a quantity of pins (namely, bus bandwidths) of a chip for inputting test excitation and outputting test responses is limited, to make full use of the bus bandwidths, complete test excitation output to a core may be split into a plurality of parts and transmitted to the bus in a time-sharing manner. If these parts are input to an input channel of a tested circuit, an incorrect test response is generated. For the test circuit shown in <FIG> and <FIG>, one test cycle may include two clock cycles. No matter in which clock cycle the test excitation is input, and no matter whether the test excitation is separately input in two clock cycles, the test excitation may be output to the input channel channel_in of the tested circuit (the scan structure <NUM>) in the second clock cycle, so that all parts of the test excitation that are input in a time-sharing manner are input to the input channel of the tested circuit at the same time, and this avoids generating an incorrect test response.

An example in which each first input bus in is coupled to two DRUs and each second input bus is coupled to two registers is used in this application, but is not intended to limit this application. A frequency division ratio <MAT> of the frequency divider <NUM> may be used as a quantity of DRUs coupled to each first input bus in and a quantity of registers coupled to each second input bus.

A plurality of fourth registers <NUM> are coupled between a reset input bus rst_in and a reset output bus rst_out. The reset input bus rst_in is configured to input a reset signal, and the reset output bus rst_out is configured to output, to the test circuit, a reset signal delayed by the plurality of fourth registers <NUM>. A quantity of the fourth registers <NUM> is the same as a quantity of registers coupled to the second input bus in (or a quantity of DRUs and registers coupled to the first input bus in). For example, in <FIG> and <FIG>, the quantity of fourth registers <NUM> is <NUM>. The frequency division ratio of the frequency divider <NUM> is adjusted, so that a difference between a time at which the reset signal is input from the reset input bus rst_in and a time at which the reset signal is output from the reset output bus rst_out is equal to a difference between a time at which data is input from the input bus in and a time at which the data is output from the output bus out. For each core, a difference between a time at which the test circuit is started and a time at which the data arrives is the same, which facilitates calculation of time at which the FSM <NUM> of the test circuit in each core starts to output a capture enable signal. The frequency divider <NUM> and the FSM <NUM> are in a reset state when the reset signal is effective. When the reset signal is ineffective, the frequency divider <NUM> and the FSM <NUM> start to work at the same time. Correspondingly, the driven first DRU <NUM>, second DRU <NUM>, and selection circuit <NUM> also start to work.

As shown in <FIG>, the input buses in (the first input bus in and the second input bus in) each may be coupled to A fifth registers <NUM>, where A is a positive integer. As a result, data input by each input bus in is input to the test circuit after a same delay. When a transmission distance of the test bus is long, inconsistency of timing of data transmission on each input bus can be avoided. In this way, a transmission speed of the test bus is improved. The fifth register <NUM> may be located inside a core or outside a core. It should be noted that, a quantity of fourth registers <NUM> coupled between the reset input bus rst_in and the reset output bus rst_out also needs to be increased by A accordingly, so that the difference between the time at which the reset signal is input from the reset input bus rst_in and the time at which the reset signal is output from the reset output bus rst_out is equal to the difference between the time at which the data is input from the input bus in and the time at which the data is output from the output bus out.

As shown in <FIG>, the output buses out (the first output bus out and the second output bus out) each may be coupled to B sixth registers <NUM>, and the reset output bus rst_out may further be coupled to B seventh registers <NUM>, where B is a positive integer. As a result, data output by each output bus and a reset signal are transmitted to a next core after a same delay. When the transmission distance of the test bus is long, inconsistency of timing of data transmission on each output bus and the reset output bus can be avoided. In this way, the transmission speed of the test bus is improved. The sixth register <NUM> and the seventh register <NUM> may be located inside or outside the core.

According to the foregoing test circuit provided in this embodiment of this application, a quantity of DRUs coupled to each first input bus in is the same as a quantity of registers coupled to each second input bus, so that a delay of outputting test excitation to a tested circuit in a current core through a DRU and outputting a test response through the DRU, a delay of transparently transmitting data through the DRU, and a delay of transparently transmitting data through a register coupled to the second input bus in are the same. This implements consistency of timing of data transmission on the test bus, and improves a transmission rate of the test bus.

With reference to <FIG>, an example in which an output bus of a test circuit in a previous core is serially coupled to an input bus of a test circuit in a next core is used below to describe a working principle of the integrated circuit shown in <FIG>. For a timing diagram of <FIG>, refer to <FIG>.

As shown in <FIG>, it is assumed that a core A includes a scan structure A, a core B includes a scan structure B, and a core C includes a scan structure C. Bandwidths of an input channel channel_in and an output channel channel_out of the scan structure A each are <NUM>, bandwidths of an input channel channel_in and an output channel channel_out of the scan structure B each are <NUM>, and bandwidths of an input channel channel_in and an output channel channel_out of the scan structure C each are <NUM>. Input buses of the core A are in1[<NUM>] to in1[<NUM>], output buses of the core A are out1[<NUM>] to out1[<NUM>], the input buses in1[<NUM>] to in1[<NUM>] of the core A are coupled to a first DRU 301A and a second DRU 302A, and the input buses in1[<NUM>] to in1[<NUM>] of the core A are coupled to a first register 303A and a second register 304A. Input buses of the core B are in2[<NUM>] to in2[<NUM>], output buses of the core B are out2[<NUM>] to out2[<NUM>], the input buses in2[<NUM>] to in2[<NUM>] of the core B are coupled to a first DRU 301B and a second DRU 302B, and the input buses in2[<NUM>] to in2[<NUM>] of the core B are coupled to a first register 303B and a second register 304B. Input buses of the core C are in3[<NUM>] to in3[<NUM>], output buses of the core C are out3[<NUM>] to out3[<NUM>], the input buses in3[<NUM>] to in3[<NUM>] of the core C are coupled to a first DRU 301C and a second DRU 302C, and the input buses in3[<NUM>] to in3[<NUM>] of the core C are coupled to a first register 303C and a second register 304C.

For example, as shown in Table <NUM>, it is assumed that scan structure A to scan structure C are tested, AI1 represents test excitation input by the scan structure A in the <NUM>st test cycle, BI1 represents test excitation input by the scan structure B in the <NUM>st test cycle, and CI1 represents test excitation input by the scan structure C in the <NUM>st test cycle. AI2 represents test excitation input by the scan structure A in the <NUM>nd test cycle, BI2 represents test excitation input by scan structure B in the <NUM>nd test cycle, and CI2 represents test excitation input by the scan structure C in the <NUM>nd test cycle. AI3 represents test excitation input by the scan structure A in the <NUM>rd test cycle, BI3 represents test excitation input by the scan structure B in the <NUM>rd test cycle, and CI3 represents test excitation input by the scan structure C in the <NUM>rd test cycle.

It should be noted that, when tested circuits in some cores do not participate in a scanning test, the tested circuits may be configured to be in a pass-through mode, so that transparently transmitted test excitation or test responses are continuously transmitted. In addition, no transmission resource is reserved for the test excitation of the tested circuit on the test bus, to make full use of the transmission bandwidth of the test bus.

The following uses the first group of test excitation AI1, BI1, and CI1 as an example to describe how to check test excitation. The methods for checking other test excitation are similar.

As shown in <FIG>, in a first clock cycle of a <NUM>st test cycle, test excitation AI1 is input to input buses in1[<NUM>] to in1[<NUM>] of a core A. In order to fully occupy buses as much as possible, the first four bits of test excitation BI1 are input to input buses in1[<NUM>] to in1[<NUM>] of the core A. In the core A, a first DRU 301A coupled to the input buses in1[<NUM>] to in1[<NUM>] outputs the test excitation AI1 to a second DRU 302A coupled to the input buses in1[<NUM>] to in1[<NUM>] for storage. A first register 303A coupled to the input buses in1[<NUM>] to in1[<NUM>] outputs the first four bits of the test excitation BI1 to a second register 304A coupled to the input buses in1[<NUM>] to in1[<NUM>] for storage.

As shown in <FIG>, in a second clock cycle of a <NUM>st test cycle, a fifth bit of test excitation BI1 is input to an input bus in1[<NUM>] of a core A, and test excitation CI1 is input to input buses in1[<NUM>] to in1[<NUM>] of the core A. In the core A, a first selector 305A couples input buses in1[<NUM>] to in1[<NUM>] and output buses out1[<NUM>] to out1[<NUM>] respectively, and couples input buses in1[<NUM>] to in1[<NUM>] and output buses out1[<NUM>] to out1[<NUM>] respectively. A second DRU 302A coupled to the input buses in1[<NUM>] to in1[<NUM>] outputs the previously stored test excitation AI1 to an input channel channel_in of a scan structure A, and transmits the previous test response AO1 of the core A to a first DRU 301B of a core B coupled to input buses in2[<NUM>] to in2[<NUM>] and a first register 303B through the output buses out1[<NUM>] to out1[<NUM>] (that is, the input buses in2[<NUM>] to in2[<NUM>] of the core B) for storage. A second register 304A coupled to the input buses in1[<NUM>] to in1[<NUM>] transmits, through the output buses out1[<NUM>] to out1[<NUM>] (that is, input buses in2[<NUM>] to in2[<NUM>] of the core B), the first four bits of the previously stored test excitation BI1 to the first DRU 301B that is of the core B and that is coupled to the input buses in2[<NUM>] to in2[<NUM>] for storage. A first DRU <NUM> coupled to the input bus in1[<NUM>] transmits a fifth bit of the test excitation BI1 to a second DRU 302A coupled to the input bus in1[<NUM>] for storage. A first register 303A coupled to the input buses in1[<NUM>] to in1[<NUM>] transmits the test excitation CI1 to the second register 304A coupled to the input buses inl[<NUM>] to in1[<NUM>] for storage.

As shown in <FIG>, in a first clock cycle of a <NUM>nd test cycle, in a core B, a first DRU 301B coupled to input buses in2[<NUM>] to in2[<NUM>] outputs the first four bits of the previously stored test excitation BI1 to a second DRU 302B for storage, and a first register 303B coupled to input buses in2[<NUM>] to in2[<NUM>] outputs the previously stored test response AO1 to a second register 304B coupled to the input buses in2[<NUM>] to in2[<NUM>] for storage. In a core A, a second DRU 302A coupled to an input bus in1[<NUM>] transmits, through an output bus out1[<NUM>] (that is, an input bus in2[<NUM>] of the core B), the fifth bit of the previously stored test excitation BI1 to the first DRU 301B that is of the core B and that is coupled to the input bus in2[<NUM>] for storage. A second DRU 302A coupled to input buses inl[<NUM>] to in1[<NUM>] transmits, through output buses out1[<NUM>] to out11[<NUM>] (that is, input buses in2[<NUM>] to in2[<NUM>] of the core B), the first three bits of the previously stored test excitation CI1 to the first register 301B that is of the core B and that is coupled to the input buses in2[<NUM>] to in2[<NUM>] for storage. A second register 304A coupled to an input bus in1[<NUM>] transmits, through an output bus out1[<NUM>] (that is, an input bus in2[<NUM>] of the core B), the fourth bit of the previously stored test excitation CI1 to the first DRU 301B that is of the core B and that is coupled to the input bus in2[<NUM>] for storage.

As shown in <FIG>, in a second clock cycle of a <NUM>nd test cycle, in a core B, a first selector 305B couples input buses in2[<NUM>] to in2[<NUM>] and output buses out2[<NUM>] to out2[<NUM>] respectively. A second DRU 302B coupled to input buses in2[<NUM>] to in2[<NUM>] outputs the first four bits of the previously stored test excitation BI1 to an input channel channel_in of a scan structure B, and transmits the first four bits of the previous test response BO1 of the core B to a first DRU 301C that is of a core C and that is coupled to input buses in3[<NUM>] to in3[<NUM>] through output buses out2[<NUM>] to out2[<NUM>] (that is, the input buses in3[<NUM>] to in3[<NUM>] of the core C) for storage. A first DRU 302B coupled to an input bus in2[<NUM>] outputs the fifth bit of the previously stored test excitation BI1 to the input channel channel_in of the scan structure B, and transmits the fifth bit of the previous test response BO1 of the core B to the second DRU 302B for storage. The second DRU 302B coupled to input buses in2[<NUM>] to in2[<NUM>] transmits the previously stored test response AO1 to a first register 303C that is of the core C and that is coupled to input buses in3[<NUM>] to in3[<NUM>] through output buses out2[<NUM>] to out2[<NUM>] (that is, the input buses in3[<NUM>] to in3[<NUM>] of the core C) for storage. A first register 303B coupled to input buses in2[<NUM>] to in2[<NUM>] transmits the first three bits of the previously stored test excitation CI1 to a second register 304B coupled to the input buses in2[<NUM>] to in2[<NUM>] for storage. A first DRU 301B coupled to an input bus in2[<NUM>] transmits the fourth bit of the previously stored test excitation CI1 to the second register 304B coupled to the input bus in2[<NUM>] for storage.

As shown in <FIG>, in a first clock cycle of a <NUM>rd test cycle, in a core C, a first DRU 301B coupled to input buses in3[<NUM>] to in3[<NUM>] outputs the first four bits of the previously stored test response BO1 to a second DRU 302C for storage. A first register 303C coupled to input buses in3[<NUM>] to in3 [<NUM>] outputs the previously stored test response AO1 to a second register 304C coupled to the input buses in3[<NUM>] to in3[<NUM>] for storage. In a core B, a first selector 305B couples input buses in2[<NUM>] to in2[<NUM>] with output buses out2[<NUM>] to out2[<NUM>], and couples input buses in2[<NUM>] to in2[<NUM>] with output buses out2[<NUM>] to out2[<NUM>]. A second register 304B coupled to the input buses in2[<NUM>] to in2[<NUM>] transmits, through the output buses out2[<NUM>] to out2[<NUM>] (that is, input buses in3[<NUM>] to in3[<NUM>] of the core C), the first three bits of the previously stored test excitation CI1 to a first DRU 301C that is of the core C and is coupled to the input buses in3[<NUM>] to in3[<NUM>] for storage. A second DRU 302B coupled to an input bus in2[<NUM>] transmits, through an output bus out2[<NUM>] (that is, an input bus in3[<NUM>] of the core C), the fourth bit of the previously stored test excitation CI1 to the first DRU 301C that is of the core C and that is coupled to the input bus in3[<NUM>] for storage. The second DRU 302B coupled to an input bus in2[<NUM>] transmits, through an output bus out2[<NUM>] (that is, an input bus in3[<NUM>] of the core C), a fifth bit of the previously stored test response BO1 to the first register 303C that is of the core C and that is coupled to the input bus in3[<NUM>] for storage.

As shown in <FIG>, in a second clock cycle of a <NUM>rd test cycle, in a core C, a first selector 305C couples input buses in3[<NUM>] to in3[<NUM>] and output buses out3[<NUM>] to out3[<NUM>] respectively. A second DRU 302C coupled to input buses in3[<NUM>] to in3[<NUM>] outputs the first four bits of the previously stored test response BO1 through output buses out3[<NUM>] to out3[<NUM>]. A second register 304C coupled to input buses in3[<NUM>] to in3[<NUM>] outputs the previously stored test response AO1 through output buses out3[<NUM>] to out3[<NUM>]. A first register 303C coupled to an input bus in3[<NUM>] outputs the fifth bit of the previously stored test excitation BI1 to the second register 304C coupled to the input bus in3[<NUM>] for storage. A first DRU 301C coupled to the input buses in3[<NUM>] to in3[<NUM>] outputs the previously stored test excitation CI1 to an input channel channel_in of a scan structure C, and outputs the previous test response CO1 of the core C to the second DRU 302C coupled to the input buses in3[<NUM>] to in3[<NUM>] for storage.

In addition, in a next clock cycle, the second register 304C coupled to the input bus in3[<NUM>] outputs the previously stored fifth bit of the test excitation BI1 through the output bus out3[<NUM>]. The second DRU 302C coupled to the input buses in3[<NUM>] to in3[<NUM>] outputs the previously stored test response CO1 through the output buses out3[<NUM>] to out3[<NUM>].

Compared with other star structure solutions such as the SRF and the DBM, the test circuit provided in this embodiment of this application is more conducive to place and route, and does not have a problem of difficulty in winding. In addition, control logic is simple, an added circuit scale is small, and a test configuration is simpler. On the premise of reducing an area increase and physical design difficulty, bus resources are properly allocated to maximize utilization. A bottom-up design process is supported, and bus resource allocation is flexible and adjustable. A same hardware connection structure can implement a plurality of test solutions, making test plan flexible. Because only two clock cycles are required to complete data interaction with the tested circuit, transmission efficiency is improved. Data transmitted in each test bus can still be consistent in timing after passing through a plurality of cores. This improves the transmission rate of the bus.

An embodiment of this application further provides a generation method for the foregoing test circuit, and the method may be executed by a processor in a computer.

S1401: Obtain a bandwidth of an input bus in or a bandwidth of an output bus out of a test bus, and a bandwidth of an input channel channel_in and a bandwidth of an output channel channel _out of a tested circuit in each core.

Data can be entered by a user or imported from a configuration. The bandwidth of the input bus in is generally equal to the bandwidth of the output bus out. A bandwidth of an input channel channel _in and a bandwidth of an output channel channel_out of a same tested circuit may be the same or different.

S1402: Determine, based on the bandwidth of the input bus or the bandwidth of the output bus of the test bus, and the bandwidth of the input channel and the bandwidth of the output channel of each tested circuit, a quantity of DRUs or registers coupled to each input bus in each test circuit, and generate the test circuit.

For example, a frequency division ratio K is calculated as follows: <MAT>. CI represents a bandwidth of an input channel channel_in of a tested circuit in a core, CO represents a bandwidth of an output channel channel_out of a tested circuit in a core, and B represents the bandwidth of the input bus in or the bandwidth of the output bus out. The K value may be used as a quantity of DRUs or registers coupled to each input bus in each core, to generate a test circuit of a plurality of cores.

An embodiment of this application further provides a circuit test method, which may be executed by a processor in a computer, and is used to test a tested circuit by using the foregoing test circuit.

S1501: Generate configuration information and test excitation.

The configuration information is used to configure a frequency division ratio of a frequency divider <NUM>, and the configuration information is further used to configure a selection signal of a debugging interface <NUM> in the foregoing test circuit, to select a first DRU <NUM> or a second DRU <NUM> to be coupled to an input channel channel_in of the tested circuit, to input the test excitation into the tested circuit through the first DRU <NUM> or the second DRU <NUM>.

S1502: Input the configuration information and the test excitation into a tested circuit of each core.

The configuration information is used to be input to the tested circuit of each core through an ijtag bus of a test bus, and the test excitation is used to be input to the tested circuit of each core through an input bus in of the test bus.

S1503: Receive a test response of each tested circuit.

Specifically, the test response of each tested circuit is received through an output bus out in the test bus.

S1504: Determine, based on the test response, whether the tested circuit is normal.

If a test response output by a tested circuit does not meet an expected result, it may be determined that the tested circuit functions abnormally; otherwise, it is determined that the tested circuit functions normally.

An embodiment of this application further provides a computer-readable storage medium. The computer-readable storage medium includes instructions. When the instructions are executed by a processor, functions or steps in the foregoing method embodiments are performed. For example, the computer-readable storage medium may be a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), a tape, a floppy disk, an optical data storage device, or the like.

An embodiment of this application further provides a computer program product including instructions. When the instructions are executed by a processor, functions or steps in the foregoing method embodiments are performed.

The execution sequences of the processes should be determined according to functions and internal logic of the processes, and should not be construed as any limitation on the implementation processes of embodiments of this application.

A person of ordinary skill in the art may be aware that, in combination with the examples described in embodiments disclosed in this specification, modules and algorithm steps may be implemented by electronic hardware or a combination of computer software and electronic hardware.

It may be clearly understood by a person skilled in the art that, for the purpose of convenient and brief description, for a detailed working process of the foregoing system, apparatus, and module, refer to a corresponding process in the foregoing method embodiments, and details are not described herein again.

In the several embodiments provided in this application, it should be understood that the disclosed system, device and method may be implemented in other manners. For example, the described device embodiment is merely an example. For example, division into the modules is merely logical function division and may be other division in an actual implementation. For example, a plurality of modules or components may be combined or integrated into another device, or some features may be ignored or not performed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections may be implemented through some interfaces. The indirect couplings or communication connections between the devices or modules may be implemented in electronic, mechanical, or other forms.

The modules described as separate components may or may not be physically separate, and components displayed as modules may or may not be physical modules, may be located in one device, or may be distributed on a plurality of devices. Some or all the modules may be selected according to actual needs to achieve the objectives of the solutions of embodiments.

In addition, functional modules in embodiments of this application may be integrated into one device, or each of the modules may exist alone physically, or two or more modules are integrated into one module.

All or some of the foregoing embodiments may be implemented by using software, hardware, firmware, or any combination thereof. When a software program is used to implement embodiments, embodiments may be implemented completely or partially in a form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the procedure or functions according to embodiments of this application are all or partially generated. The computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable apparatuses. The computer instructions may be stored in a computer-readable storage medium or may be transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center in a wired (for example, a coaxial cable, an optical fiber, or a digital subscriber line (Digital Subscriber Line, DSL)) or wireless (for example, infrared, radio, or microwave) manner. The computer-readable storage medium may be any usable medium accessible by a computer, or a data storage device, such as a server or a data center, integrating one or more usable media. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, a DVD), a semiconductor medium (for example, a solid-state drive (solid state disk, SSD)), or the like.

Claim 1:
A test circuit, comprising: a first input bus, a second input bus, a first output bus, a second output bus, a first dynamic routing unit DRU, and a first register, wherein
the first input bus is configured to be coupled to an input channel of a tested circuit through the first DRU, and the first output bus is configured to be coupled to an output channel of the tested circuit through the first DRU;
the second input bus is configured to be coupled to the second output bus through the first register; and
in a clock cycle: the first DRU is configured to output test excitation from the first input bus to the input channel, and output a test response from the output channel to the first output bus; or the first DRU is configured to output data from the first input bus to the first output bus; and the first register is configured to output data from the second input bus to the second output bus.