Patent Description:
In a transistor, an ohmic contact structure including a metal silicide may be formed in order to reduce a resistance between a source/drain layer including a semiconductor material and a contact plug including a metal on the source/drain layer. A material of the ohmic contact structure may be optimized so that the resistance between the source/drain layer and the contact plug may be effectively reduced according to the specific type of the semiconductor material included in the source/drain layer. Patent document <CIT> indicates the possibility of having in a semiconductor device such as a transistor having two different materials when creating a silicide pattern in a plug.

According to example embodiments, there is provided a semiconductor device. according to claim <NUM>.

The semiconductor device includes a substrate including a first region and a second region; a first gate structure on the first region of the substrate, a first source/drain layer on a portion of the substrate adjacent to the first gate structure; a second gate structure on the second region of the substrate; a second source/drain layer on a portion of the substrate adjacent to the second gate structure; a first contact plug including, a first metal silicide pattern on the first source/drain layer, the first metal silicide pattern including a silicide of a first metal and a silicide of a second metal different from the first metal, and a first conductive pattern on the first metal silicide pattern; and a second contact plug including, a second metal silicide pattern on the second source/drain layer, the second metal silicide pattern including a silicide of the first and second metals, and a second conductive pattern on the second metal silicide pattern, wherein a first ratio of the first metal to the second metal included in the first metal silicide pattern is different from a second ratio of the first metal to the second metal included in the second metal silicide pattern.

According to another embodiment, there is provided a semiconductor device according to claim <NUM>.

The semiconductor device includes a substrate including a first region and a second region; a first epitaxial layer on the first region of the substrate; a second epitaxial layer on the second region of the substrate; a first contact plug including, a first metal silicide pattern on the first epitaxial layer, the first metal silicide pattern including a silicide of a first metal and a silicide of a second metal different from the first metal, and a first conductive pattern on the first metal silicide pattern; and a second contact plug including a second metal silicide pattern on the second epitaxial layer, the second metal silicide pattern including a silicide of the first and second metal and a second conductive pattern on the second metal silicide pattern, wherein a work function of the first metal silicide pattern and a work function of the second metal silicide pattern are different from each other.

According to example embodiments, there is provided a semiconductor device. The semiconductor device may include a substrate, a first active fin, a second active fin, a first transistor, a second transistor, a first contact plug and a second contact plug. The substrate may include a first region and a second region. The first active fin and the second active fin may be disposed on the first and second regions of the substrate, respectively. The first transistor may include a first gate structure on the first active fin of the first region of the substrate; and a first source/drain layer on a portion of the first active fin adjacent to the first gate structure, the first source/drain layer including silicon-germanium doped with a p-type impurity. The second transistor may include a second gate structure on the second active fin of the second region of the substrate; and a second source/drain layer on a portion of the second active fin adjacent to the second gate structure, the second source/drain layer including silicon doped with a n-type impurity. The first contact plug may include a first metal silicide pattern on the first source/drain layer, the first metal silicide pattern including a silicide of a first metal having a work function equal to or more than about <NUM>. 6eV; a first conductive pattern on the first metal silicide pattern, the first conductive pattern including a third metal; and a first metal layer between the first metal silicide pattern and the first conductive pattern, the first metal layer including a second metal having a work function in a range of about <NUM>. 0eV to about <NUM>. The second contact plug may include a second metal silicide pattern on the second source/drain layer, the first metal silicide pattern including a silicide of the first metal; and a second conductive pattern on the second metal silicide pattern, the second conductive pattern including the third metal. In the semiconductor device, a first ratio of the first metal to the second metal included in the first metal silicide pattern may be greater than a second ratio of the first metal to the second metal included in the second metal silicide pattern.

In the semiconductor device in accordance with example embodiments, a first contact plug on a source/drain layer of an NMOS transistor may include a first ohmic contact structure, and a second contact plug on a source/drain layer of a PMOS transistor may include a second ohmic contact structure. The first and second ohmic contact structure may have different work functions from each other, and thus, a contact resistance between the first source/drain layer and the first contact plug and a contact resistance between the second source/drain layer and the second contact plug may be reduced.

In addition, the first and second ohmic contact structures may be formed not by separate processes but by the same etching processes and the same deposition processes, and thus, stages and cost of processes may be reduced.

A semiconductor device and a non-claimed method of manufacturing the same in accordance with example embodiments will be described more fully hereinafter with reference to the accompanying drawings. Hereinafter in the specifications (and not necessarily in the claims), two directions substantially parallel to an upper surface of a substrate and crossing each other may be referred to as first and second directions D1 and D2, respectively, and a direction substantially perpendicular to the upper surface of the substrate may be referred to as a third direction D3. In example embodiments, the first and second directions D1 and D2 may be substantially perpendicular to each other.

<FIG> are a plan view and cross-sectional views illustrating a semiconductor device in accordance with example embodiments. Particularly, <FIG> is the plan view, and <FIG>, <FIG> and <FIG> are the cross-sectional views. <FIG> is a cross-sectional view taken along line A-A' of <FIG>, <FIG> is a cross-sectional view taken along line B-B' of <FIG>, and <FIG> includes cross-sectional views taken along lines C-C' and D-D', respectively, of <FIG>. <FIG> is an enlarged cross-sectional view of regions X and Y of <FIG>.

Referring to <FIG>, the semiconductor device may include a first active pattern <NUM>, a first isolation pattern <NUM>, first and second gate structures <NUM> and <NUM>, first and second source/drain layers <NUM> and <NUM>, first and second gate spacers <NUM> and <NUM>, a fin spacer <NUM>, first and second contact plug structures <NUM> and <NUM>, and first and second insulating interlayers <NUM> and <NUM> on a substrate <NUM>.

The substrate <NUM> may include a semiconductor material, e.g., silicon, germanium, silicon-germanium, etc., or III-V semiconductor compounds, e.g., GaP, GaAs, GaSb, etc. In some embodiments, the substrate <NUM> may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

The substrate <NUM> may include first and second regions I and II. The first region I may be a region on which PMOS transistors are disposed, and the second region II may be a region on which NMOS transistors are disposed.

<FIG> show that the first and second regions I and II of the substrate <NUM> are disposed in the first direction D1, however, the inventive concept may not be limited thereto, and in some embodiments, the first and second regions I and II of the substrate <NUM> may be disposed in the second direction D2. For convenience below, an active pattern (or fin) <NUM> in the first region I is referred to as a first active pattern (or fin) <NUM>, and an active pattern (or fin) <NUM> in the second region II is referred to as a second active pattern (or fin) <NUM>. Likewise, an isolation pattern <NUM> in the first region I is referred to as a first isolation pattern <NUM>, and an isolation pattern <NUM> in the second region II is referred to as a second isolation pattern <NUM>. Other elements may be similarly described as a first element in the first region I and a corresponding second element in the second region II.

The first active pattern <NUM> may have a fin-like shape protruding from an upper surface of the substrate <NUM>, and thus may also be referred to as a first active fin. A lower surface of the first active pattern <NUM> may be covered by the first isolation pattern <NUM>. The substrate <NUM> may include a field region on which the first isolation pattern <NUM> is formed and an active region on which the first active pattern <NUM> is formed.

The first active pattern <NUM> may include a first lower active pattern 105a of which a sidewall is covered by the first isolation pattern <NUM> and a first upper active pattern 105b of which a sidewall is not covered by the first isolation pattern <NUM>. In example embodiments, the first active pattern <NUM> may extend in the first direction D1, and a plurality of first active patterns <NUM> may be spaced apart from each other in the second direction D2.

The first active pattern <NUM> may include a material which is the same or substantially the same as that of the substrate <NUM>, and the first isolation pattern <NUM> may include an oxide, e.g., silicon oxide.

In example embodiments, the first gate structure <NUM> may extend in the second direction D2 on the first active pattern <NUM> and the first isolation pattern <NUM> on the first region I of the substrate <NUM>, and a plurality of first gate structures <NUM> may be spaced apart from each other in the first direction D1. Additionally, the second gate structure <NUM> may extend in the second direction D2 on the first active pattern <NUM> and the first isolation pattern <NUM> on the second region II of the substrate <NUM>, and a plurality of second gate structures <NUM> may be spaced apart from each other in the first direction D1.

In example embodiments, the first gate structure <NUM> may include a first gate insulation pattern <NUM> and a first gate electrode <NUM> stacked on the first active pattern <NUM> and the first isolation pattern <NUM>, and a first capping pattern <NUM> on the first gate insulation pattern <NUM> and the first gate electrode <NUM>. The second gate structure <NUM> may include a second gate insulation pattern <NUM> and a second gate electrode <NUM> stacked on the second active pattern <NUM> and the second isolation pattern <NUM>, and a second capping pattern <NUM> on the second gate insulation pattern <NUM> and the second gate electrode <NUM>.

In example embodiments, the first gate insulation pattern <NUM> may cover a lower surface and a sidewall of the first gate electrode <NUM>, and the first capping pattern <NUM> may contact upper surfaces of the first gate electrode <NUM> and the first gate insulation pattern <NUM>. Additionally, the second gate insulation pattern <NUM> may cover a lower surface and a sidewall of the second gate electrode <NUM>, and the second capping pattern <NUM> may contact upper surfaces of the second gate electrode <NUM> and the second gate insulation pattern <NUM>.

In an example embodiment, the first gate structure <NUM> may further include a first interface pattern between the first gate insulation pattern <NUM> and the first active pattern <NUM> and/or the first isolation pattern <NUM>. Additionally, the second gate structure <NUM> may further include a second interface pattern between the second gate insulation pattern <NUM> and the first active pattern <NUM> and/or the first isolation pattern <NUM>. The first and second interface patterns may include an oxide, e.g., silicon oxide.

Each of the first and second gate insulation patterns <NUM> and <NUM> may include a metal oxide having a high dielectric constant, e.g., hafnium oxide, tantalum oxide, zirconium oxide, etc..

Each of the first and second gate electrodes <NUM> and <NUM> may include a metal nitride (e.g., titanium nitride, titanium aluminum nitride, tantalum nitride, tantalum aluminum nitride, etc.), a metal alloy (e.g., titanium aluminum, titanium aluminum carbide, titanium aluminum oxynitride, titanium aluminum carbonitride, titanium aluminum oxycarbonitride, etc.), a metal carbide, a metal oxynitride, a metal carbonitride, a metal oxycarbonitride, or a low resistance metal (e.g., tungsten, aluminum, copper, tantalum).

The first gate spacer <NUM> may be formed on each of opposite sidewalls in the first direction D1 of the first gate structure <NUM>, and thus an outer sidewall of the first gate insulation pattern <NUM> and a sidewall of the first capping pattern <NUM> may contact an inner sidewall of the first gate spacer <NUM>. Additionally, the second gate spacer <NUM> may be formed on each of opposite sidewalls in the first direction D1 of the second gate structure <NUM>, and thus an outer sidewall of the second gate insulation pattern <NUM> and a sidewall of the second capping pattern <NUM> may contact an inner sidewall of the second gate spacer <NUM>.

The fin spacer <NUM> may be formed on each of opposite sidewalls in the second direction D2 of the first active pattern <NUM>.

The first and second gate spacers <NUM> and <NUM> and the fin spacer <NUM> may include an insulating nitride, e.g., silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc..

The first source/drain layer <NUM> may be formed at each of opposite sides in the first direction D1 of the first gate structure <NUM>, and may be interposed between ones of the first gate spacers <NUM> facing each other in the first direction D1. The second source/drain layer <NUM> may be formed at each of opposite sides in the first direction D1 of the second gate structure <NUM>, and may be interposed between ones of the second gate spacers <NUM> facing each other in the first direction D1.

The first source/drain layer <NUM> may include single crystalline silicon-germanium doped with a p-type impurity, and thus may serve as a source/drain region of a PMOS transistor. The second source/drain layer <NUM> may include single crystalline silicon or single crystalline silicon carbide doped with n-type impurities, and thus may serve as a source/drain region of an NMOS transistor.

Each of the first and second source/drain layers <NUM> and <NUM> may be covered by the first insulating interlayer <NUM>. The second insulating interlayer <NUM> may be formed on the first insulating interlayer <NUM>, the first and second gate structures <NUM> and <NUM> and the first and second gate spacers <NUM> and <NUM>.

Each of the first and second insulating interlayers <NUM> and <NUM> may include an insulating material, e.g., silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc..

The first and second contact plug structures <NUM> and <NUM> may extend through the first and second insulating interlayers <NUM> and <NUM>, and may contact upper surfaces of the first and second source/drain layers <NUM> and <NUM>, respectively. The first and second contact plug structures <NUM> and <NUM> may partially extend through upper portions of the first and second source/drain layers <NUM> and <NUM>, respectively.

The first contact plug structure <NUM> may include a first metal silicide pattern <NUM>, a first metal layer <NUM> and a first conductive pattern <NUM> sequentially stacked in the third direction D3.

The first metal silicide pattern <NUM> may be disposed on the upper surface of the first source/drain layer <NUM>, and includes a silicide of a first metal and may include a germanide of the first metal. The first metal layer <NUM> may be disposed on the first metal silicide pattern <NUM>, and may include a second metal. The first conductive pattern <NUM> may be disposed on the first metal layer <NUM>.

In example embodiments, the first metal may include at least one metal having a work function that is greater than about <NUM>. 6eV, such as molybdenum (Mo), tungsten (W), ruthenium (Ru), nickel (Ni), cobalt (Co), platinum (Pt), etc..

In example embodiments, the second metal may include at least one metal having a work function that is in a range of about <NUM>. 0eV to about <NUM>. 5eV, such as, titanium (Ti), yttrium (Y), lanthanum (La), hafnium (Hf), zirconium (Zr), scandium (Sc), manganese (Mn), aluminum (Al), erbium (Er), etc..

In example embodiments, the first conductive pattern <NUM> may include a third metal. The third metal may include, for example, molybdenum (Mo), cobalt (Co), tungsten (W), etc..

In embodiments, the first metal silicide pattern <NUM> further includes a silicide of the second metal and may include a germanide of the second metal. In an example embodiment, a concentration of the second metal of a first portion of the first metal silicide pattern <NUM> that is nearer to the first metal layer <NUM> may be greater than a concentration of the second metal of a second portion of the first metal silicide pattern <NUM> that is farther from the first metal layer <NUM>.

The second contact plug structure <NUM> may include a second metal silicide pattern <NUM> and a second conductive pattern <NUM> sequentially stacked in the third direction D3.

The second metal silicide pattern <NUM> may be disposed on the upper surface of the second source/drain layer <NUM>, and may include a silicide of the first and second metals. The second conductive pattern <NUM> may be disposed on the second source/drain layer <NUM>.

In an example embodiment, a concentration of the second metal of a first portion of the second metal silicide pattern <NUM> that is farther from the second source/drain layer <NUM> may be greater than a concentration of the second metal of a second portion of the second metal silicide pattern <NUM> that is nearer to the second source/drain layer <NUM>.

In example embodiments, a first ratio R1 (molar ratio), which is a ratio of the first metal to the second metal in the first metal silicide pattern <NUM> is greater than a second ratio R2 (molar ratio), which is a ratio of the first metal to the second metal in the second metal silicide pattern <NUM>. Accordingly, a work function of the first metal silicide pattern <NUM> on the first source/drain layer <NUM> may be greater than a work function of the second metal silicide pattern <NUM> on the second source/drain layer <NUM>.

In other words, a work function of a first ohmic contact structure, that is, the first metal silicide pattern <NUM>, which may be disposed between the first source/drain layer <NUM> and the first conductive pattern <NUM>, may be different from a work function of a second ohmic contact structure, that is, the second metal silicide pattern <NUM>, which may be disposed between the second source/drain layer <NUM> and the second conductive pattern <NUM>.

Specifically, the first metal silicide pattern <NUM> on the first source/drain layer <NUM>, which may include silicon-germanium doped with a p-type impurity and serve as a source/drain of a PMOS transistor, may include a higher proportion of the first metal with a relatively large work function than the second metal with a relatively small work function. The second metal silicide pattern <NUM> on the second source/drain layer <NUM>, which may include silicon or silicon carbide doped with n-type impurities and serve as a source/drain of an NMOS transistor, may include a lower proportion of the first metal with a relatively large work function than the second metal with a relatively small work function. Accordingly, the work function of the first metal silicide pattern <NUM> may be greater than the work function of the second metal silicide pattern <NUM>.

Accordingly, a contact resistance between the first source/drain layer <NUM> and the first contact plug structure <NUM> and a contact resistance between the second source/drain layer <NUM> and the second contact plug structure <NUM> may decrease.

The semiconductor device may include the first gate structure <NUM> on the first active fin <NUM> serving as a channel and the first source/drain layers <NUM> on portions of the first active fin <NUM> adjacent to the first gate structure <NUM>, and may include the second gate structure <NUM> on the first active fin <NUM> and the second source/drain layers <NUM> on portions of the first active fin <NUM> adjacent to the second gate structure <NUM>. Thus, the semiconductor device may include a finFET.

Vias and wirings that may apply electrical signals to the first and contact plugs <NUM> and <NUM> may be further formed thereon.

<FIG> are plan views and cross-sectional views for reference in describing a method of manufacturing a semiconductor device in accordance with example embodiments. Particularly, <FIG>, <FIG>, <FIG> and <FIG> are the plan views, and <FIG>, <FIG>, <FIG> and <FIG> are the cross-sectional views.

<FIG> and <FIG> are cross-sectional views taken along lines A-A' of corresponding plan views, respectively, <FIG>, <FIG>, <FIG>, <FIG> and <FIG> are cross-sectional views taken along lines B-B' of corresponding plan views, respectively, and <FIG> includes cross-sectional views taken along lines C-C' and D-D', respectively, of <FIG>. <FIG> are enlarged cross-sectional views of regions X and Y of <FIG>.

Referring to <FIG>, an upper portion of a substrate <NUM> including first and second regions I and II may be removed to form a first trench, and an isolation pattern <NUM> may be formed in a lower portion of the first trench.

<FIG> show that the first and second regions I and II are arranged in the first direction D1, however, the inventive concept is not limited thereto, and, for example, the first and second regions I and II of the substrate <NUM> may be arranged in the second direction D2.

In example embodiments, the isolation pattern <NUM> may be formed by forming a first isolation layer on the substrate <NUM> to fill the first trench, planarizing the first isolation layer until an upper surface of the substrate <NUM> is exposed, and removing an upper portion of the first isolation layer to expose an upper portion of the first trench. As the isolation pattern <NUM> is formed on the substrate <NUM>, an active pattern <NUM> may be defined on the substrate <NUM>.

The planarization process may include, e.g., a chemical mechanical polishing (CMP) process and/or an etch back process.

In example embodiments, the active pattern <NUM> may extend in the first direction D1, and a plurality of active patterns (or fins) <NUM> may be spaced apart from each other in the second direction D2.

First and second dummy gate structures <NUM> and <NUM> may be formed on the first and second regions I and II, respectively, of the substrate <NUM> having the active pattern <NUM> and the isolation pattern <NUM> thereon. Each of the first and second dummy gate structures <NUM> and <NUM> may include a first dummy gate insulation pattern <NUM>, a first dummy gate electrode <NUM> and a first dummy gate mask <NUM> sequentially stacked.

The first dummy gate insulation pattern <NUM> may include an oxide, e.g., silicon oxide, the first dummy gate electrode <NUM> may include, e.g., polysilicon, and the first dummy gate mask <NUM> may include an insulating nitride, e.g., silicon nitride.

In example embodiments, each of the first and second dummy gate structures <NUM> and <NUM> may extend in the second direction D2. A plurality of first dummy gate structures <NUM> may be spaced apart from each other in the first direction D1 on the first region I of the substrate <NUM>, and a plurality of second dummy gate structures <NUM> may be spaced apart from each other in the first direction D1 on the second region II of the substrate <NUM>.

Referring to <FIG>, a first gate spacer <NUM> may be formed on each of opposite sidewalls in the first direction D1 of the first dummy gate structure <NUM>, and a second gate spacer <NUM> may be formed on each of opposite sidewalls in the first direction D1 of the second dummy gate structure <NUM>. Additionally, a fin spacer <NUM> may be formed on each of opposite sidewalls in the second direction D2 of the active pattern <NUM>.

The first and second gate spacers <NUM> and <NUM> and the fin spacer <NUM> may be formed by forming a first spacer layer on the substrate <NUM> having the active pattern <NUM>, the first isolation pattern <NUM> and the first and second dummy gate structures <NUM> and <NUM> thereon, and anisotropically etching the first spacer layer. The first and second gate spacers <NUM> and <NUM> and the fin spacer <NUM> may include an insulating nitride, e.g., silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc..

Upper portions of the active pattern <NUM> may be etched using the first and second dummy gate structures <NUM> and <NUM> and the first and second gate spacers <NUM> and <NUM> as an etching mask to form first and second recesses <NUM> and <NUM>, respectively.

<FIG> shows that each of the first and second recesses <NUM> and <NUM> is formed by partially removing the upper active pattern 105b. However, the inventive concept is not limited thereto, and, for example, each of the first and second recesses <NUM> and <NUM> may be formed by partially removing the lower active pattern 105a as well as the upper active pattern 105b.

The anisotropic etching process of the first spacer layer and the etching process for forming the first and second recesses <NUM> and <NUM> may be performed in-situ.

First and second selective epitaxial growth (SEG) processes may be performed using respective upper surfaces of the active pattern <NUM> exposed by the first and second recesses <NUM> and <NUM> as a seed to form first and second source/drain layers <NUM> and <NUM>, respectively, on portions of the active pattern <NUM> on the first and second regions I and II, respectively, of the substrate <NUM>.

The first SEG process may be performed using a silicon source gas, e.g., dichlorosilane (SiH<NUM>Cl<NUM>) gas, a germanium source gas (e.g., germane (GeH<NUM>) gas), and a p-type impurity source gas (e.g., diborane (B<NUM>H<NUM>) gas), so that a single crystalline silicon-germanium layer doped with p-type impurities may be formed as the first source/drain layer <NUM>.

The second SEG process may be performed using a silicon source gas, e.g., disilane (Si<NUM>H<NUM>) gas and an n-type impurity source gas, e.g., PH<NUM>, POCl<NUM>, P<NUM>O<NUM>, etc., so that a single crystalline silicon layer doped with n-type impurities or a single crystalline silicon carbide layer doped with n-type impurities may be formed as the second source/drain layer <NUM>.

The first and second source/drain layers <NUM> and <NUM> may fill the first and second recesses <NUM> and <NUM>, respectively, and may further grow to contact lower sidewalls of the first and second gate spacers <NUM> and <NUM>, respectively. Each of the first and second source/drain layers <NUM> and <NUM> may grow in a horizontal direction as well as a vertical direction. The first source/drain layer <NUM> may have a cross-section in the second direction D2 having a shape of a pentagon or a rhombus, and the second source/drain layer <NUM> may have a cross-section in the second direction D2 having a shape of a rectangle with rounded corners or a circle.

If a distance between ones of the first active patterns <NUM> neighboring in the second direction D2 on the first region I of the substrate <NUM> is small, ones of the first source/drain layers <NUM> grown from upper surfaces of the neighboring ones of the first active patterns <NUM> may be merged with each other. Likewise, if a distance between ones of the second active patterns <NUM> neighboring in the second direction D2 on the second region II of the substrate <NUM> is small, ones of the second source/drain layers <NUM> grown from upper surfaces of the neighboring ones of the second active patterns <NUM> may be merged with each other.

Referring to <FIG>, a first insulating interlayer <NUM> may be formed on the substrate <NUM> having the first and second dummy gate structures <NUM> and <NUM>, the first and second gate spacers <NUM> and <NUM>, the fin spacer <NUM>, the first and second source/drain layers <NUM> and <NUM> and the first isolation pattern <NUM> thereon to have an upper surface higher than upper surfaces of the first and second dummy gate structures <NUM> and <NUM> and the first and second gate spacers <NUM> and <NUM>.

A planarization process may be performed until an upper surface of the first dummy gate electrode <NUM> included in each of the first and second dummy gate structures <NUM> and <NUM> is exposed to remove an upper portion of the first insulating interlayer <NUM> and the first dummy gate mask <NUM> included in each of the first and second dummy gate structures <NUM> and <NUM>, and upper portions of the first and second gate spacers <NUM> and <NUM> may also be removed.

The first dummy gate electrode <NUM> and the first dummy gate insulation pattern <NUM> may be removed to form first and second openings <NUM> and <NUM> on the first and second regions I and II, respectively, of the substrate <NUM>, which may expose upper surfaces of the active pattern <NUM> and the isolation pattern <NUM>.

In example embodiments, the first dummy gate electrode <NUM> and the first dummy gate insulation pattern <NUM> may be removed by sequentially performing a dry etching process and a wet etching process. The wet etching process may be performed using, e.g., hydrofluoric acid (HF) as an etching solution.

Referring to <FIG>, a first gate insulation layer may be formed on bottoms and sidewalls of the first and second openings <NUM> and <NUM> and an upper surface of the first insulating interlayer <NUM>, a first gate electrode layer may be formed on the first gate insulation layer to fill remaining portions of the first and second openings <NUM> and <NUM>, and the first gate electrode layer and the first gate insulation layer may be planarized until the upper surface of the first insulating interlayer <NUM> is exposed.

Thus, a first gate electrode <NUM> and a first gate insulation pattern <NUM> covering a lower surface and a sidewall of the first gate electrode <NUM> may be formed in the first opening <NUM>, and a second gate electrode <NUM> and a second gate insulation pattern <NUM> covering a lower surface and a sidewall of the second gate electrode <NUM> may be formed in the second opening <NUM>.

In an example embodiment, the first gate electrode layer may include a barrier layer and a gate conductive layer, and in this case, each of the first and second gate electrodes <NUM> and <NUM> may include a barrier pattern and a conductive pattern.

Upper portions of the first gate electrode <NUM> and the first gate insulation pattern <NUM> may be removed to form a third recess, and upper portions of the second gate electrode <NUM> and the second gate insulation pattern <NUM> may be removed to form a fourth recess. Additionally, first and second capping patterns <NUM> and <NUM> may be formed in the third and fourth recesses, respectively.

Thus, a first gate structure <NUM> including the first gate insulation pattern <NUM> on upper surfaces of the first active pattern <NUM> and the first isolation pattern <NUM> and a lower inner sidewall of the first gate spacer <NUM> in the first opening <NUM>, the first gate electrode <NUM> on the first gate insulation pattern <NUM> in a lower portion of the first opening <NUM>, and the first capping pattern <NUM> on the first gate insulation pattern <NUM> and the first gate electrode <NUM> in an upper portion of the first opening <NUM> and contacting an upper inner sidewall of the first gate spacer <NUM> may be formed on the first region I of the substrate <NUM>.

Additionally, a second gate structure <NUM> including the second gate insulation pattern <NUM> on upper surfaces of the second active pattern <NUM> and the second isolation pattern <NUM> and a lower inner sidewall of the second gate spacer <NUM> in the second opening <NUM>, the second gate electrode <NUM> on the second gate insulation pattern <NUM> in a lower portion of the second opening <NUM>, and the second capping pattern <NUM> on the second gate insulation pattern <NUM> and the second gate electrode <NUM> in an upper portion of the second opening <NUM> and contacting an upper inner sidewall of the second gate spacer <NUM> may be formed on the second region II of the substrate <NUM>.

Referring to <FIG>, a second insulating interlayer <NUM> may be formed on the first and second gate structures <NUM> and <NUM>, the first and second gate spacers <NUM> and <NUM>, and the first insulating interlayer <NUM>, and portions of the first and second insulating interlayers <NUM> and <NUM> between the first gate structures <NUM> may be partially removed to form a third opening <NUM> exposing an upper surface of the first source/drain layer <NUM>, and portions of the first and second insulating interlayers <NUM> and <NUM> between the second gate structures <NUM> may be partially removed to form a fourth opening <NUM> exposing an upper surface of the second source/drain layer <NUM>.

The third and fourth openings <NUM> and <NUM> may partially extend through upper portions of the first and second source/drain layers <NUM> and <NUM>, respectively.

Referring to <FIG>, a first chemical vapor deposition (CVD) process may be performed so that a first metal silicide pattern <NUM> may be formed on the upper surface of the first source/drain layer <NUM> exposed by the third opening <NUM>, and a second preliminary metal silicide pattern 281a may be formed on the upper surface of the second source/drain layer <NUM> exposed by the fourth opening <NUM>.

The first CVD process may be performed by using a source gas containing a first metal, and the first metal may be reacted with each of the first and second source/drain layers <NUM> and <NUM> containing silicon. Thus, the first metal silicide pattern <NUM> and the second preliminary metal silicide pattern 281a including a silicide of the first metal may be formed on the first and second source/drain layers <NUM> and <NUM>, respectively. However, the first source/drain layer <NUM> may also include germanium, and thus the first metal silicide pattern <NUM> may also include a germanide of the first metal.

In example embodiments, the first CVD process may be selectively performed depending on a material and an impurity concentration of a layer on which the first CVD process is performed. Accordingly, a thickness of the first metal silicide pattern <NUM> that may be formed on the first source/drain layer <NUM> including silicon-germanium and a thickness of the second preliminary metal silicide patterns 281a that may be formed on the second source/drain layer <NUM> including silicon carbide or silicon may be different from each other.

In an example embodiment, the thickness of the first metal silicide pattern <NUM> may be greater than the thickness of the second preliminary metal silicide pattern 281a. Specifically, the thickness of the first metal silicide pattern <NUM> may be about <NUM> to about <NUM> times the thickness of the second preliminary metal silicide pattern 281a.

Referring to <FIG>, a second CVD process may be performed so that a first metal layer <NUM> may be formed on the first metal silicide pattern <NUM> and the second preliminary metal silicide pattern 281a may be converted into a second metal silicide pattern <NUM>.

In example embodiments, the second CVD process may be performed using a source gas including a second metal having a work function smaller than a work function of the first metal.

The second CVD process may be performed selectively or non-selectively. If the second CVD process is performed selectively, for example, an amount of the second metal deposited on the second preliminary metal silicide pattern 281a may be greater than an amount of the second metal deposited on the first metal silicide pattern <NUM>.

The second metal provided in the second CVD process may be deposited on the first metal silicide pattern <NUM> to form the first metal layer <NUM>, and the second metal may partially diffuse into the first metal silicide pattern <NUM> by heat generated during the CVD process and/or by a separate annealing process. Accordingly, at least a portion of the first metal silicide pattern <NUM> may include the second metal. However, the first metal silicide pattern <NUM> may have a relatively large thickness, and thus the second metal may not diffuse into an entire portion of the first metal silicide pattern <NUM>. In other words the concentration of the second metal in the first metal silicide pattern <NUM> may be greater nearer to the metal layer <NUM>.

In an example embodiment, a concentration of the second metal of a first portion of the first metal silicide pattern <NUM> that is nearer to the first metal layer <NUM> may be greater than a concentration of the second metal of a second portion of the first metal silicide pattern <NUM> that is farther from the first metal layer <NUM>.

The second metal provided in the second CVD process may be deposited on the second preliminary metal silicide pattern 281a. The second metal may be diffused into an entire portion of the second preliminary metal silicide pattern 281a, which may have a relatively small thickness, by the heat generated during the CVD process and/or by a separate annealing process. Accordingly, instead of a separate metal layer including the second metal remaining on the second preliminary metal silicide pattern 281a, the second preliminary metal silicide pattern 281a may be converted into the second metal silicide pattern <NUM> including not only the first metal but also the second metal.

As described above, the thickness of the first metal silicide pattern <NUM> may be greater than the thickness of the second preliminary metal silicide pattern 281a, which may be formed by the first CVD process. Thus, an amount of the first metal included in the silicide pattern <NUM> may be greater than an amount of the first metal included in the second preliminary metal silicide pattern 281a. In addition, an amount of the second metal diffused into the second preliminary metal silicide pattern 281a may be greater than an amount of the second metal diffused into the first metal silicide pattern <NUM> in the second CVD process.

Accordingly, a first ratio R1, which is a ratio of the first metal to the second metal in the first metal silicide pattern <NUM>, may be greater than a second ratio R2, which is a ratio of the first metal to the second metal in the second metal silicide pattern <NUM>. Accordingly, a work function of the first metal silicide pattern <NUM> may be greater than a work function of the second metal silicide pattern <NUM>.

Referring back to <FIG>, a third CVD process may be performed using a source gas including a third metal to form first and second conductive layers on the second insulating interlayer <NUM> to fill the third and fourth openings <NUM> and <NUM>, respectively, and the first and second conductive layers may be planarized until an upper surface of the second insulating interlayer <NUM> is exposed. Accordingly, first and second conductive patterns <NUM> and <NUM> may be formed to fill remaining portions of the third and fourth openings <NUM> and <NUM>, respectively.

The first metal silicide pattern <NUM>, the first metal layer <NUM> and the first conductive pattern <NUM> in the third opening <NUM> may collectively form a first contact plug structure <NUM>, and the second metal silicide pattern <NUM> and the second conductive pattern <NUM> in the fourth opening <NUM> may collectively form a second contact plug structure <NUM>.

Manufacturing of the semiconductor device may be completed by performing the above-described processes.

As described above, the first and second contact plug structures <NUM> and <NUM> on the first and second source/drain layers <NUM> and <NUM>, respectively, may be formed by the same processes, that is, the first to third CVD processes. However, the first ohmic contact structure between the first source/drain layer <NUM> and the first conductive pattern <NUM> and the second ohmic contact structure between the second source/drain layer <NUM> and the second conductive pattern <NUM> may have different work functions from each other.

That is, the first CVD process may be selectively performed using the source gas including the first metal with a relatively large work function, so that the first metal silicide pattern <NUM> may be formed on the first source/drain layer <NUM> to have a relatively large thickness, and the second preliminary metal silicide pattern 281a may be formed on the second source/drain layer <NUM> to have a relatively small thickness. Thereafter, the second CVD process may be performed using the source gas including the second metal with a relatively small work function, so that the second metal may be partially diffused only into a portion of the first metal silicide pattern <NUM>, but may be entirely diffused into the second preliminary metal silicide pattern 281a.

Accordingly, the first metal silicide pattern <NUM> on the first source/drain layer <NUM>, which may include silicon-germanium doped with a p-type impurity and serve as a source/drain of a PMOS transistor, may include a higher proportion of the first metal with a relatively large work function than the second metal with a relatively small work function. The second metal silicide pattern <NUM> on the second source/drain layer <NUM>, which may include silicon or silicon carbide doped with n-type impurities and serve as a source/drain of an NMOS transistor, may include a lower proportion of the first metal with a relatively large work function than the second metal with a relatively small work function. Accordingly, the work function of the first metal silicide pattern <NUM> may be greater than the work function of the second metal silicide pattern <NUM>.

Hence, a contact resistance between the first source/drain layer <NUM> and the first contact plug structure <NUM> and a contact resistance between the second source/drain layer <NUM> and the second contact plug structure <NUM> may decrease.

The first and second ohmic contact structures may be formed by separate deposition processes so that the first and second ohmic contact structures may have optimized work functions to reduce the contact resistance. However, such an approach increases the number of deposition processes so that the overall process may become complicated and costly. In example embodiments, the first and second ohmic contact structures may be formed by the same etching processes and the same deposition processes, and thus, the overall process may be simplified and costs reduced.

Additionally, the first to third CVD processes may be performed in-situ. Thus, each of the first and second contact plug structures <NUM> and <NUM> need not include a barrier pattern, and accordingly, may have a relatively low resistance.

<FIG> and <FIG> are cross-sectional views illustrating a semiconductor device in accordance with example embodiments, and may correspond to <FIG> and <FIG>, respectively.

This semiconductor device may be substantially the same as or similar to that of <FIG>, except for the first and second contact plug structures <NUM> and <NUM>, and thus repeated explanations of already described elements are omitted herein.

Referring to <FIG> and <FIG>, the first contact plug structure <NUM> need not include the first metal layer <NUM>, and thus, an upper surface of the first metal silicide pattern <NUM> may contact a lower surface of the first conductive pattern <NUM>.

The first metal silicide pattern <NUM> includes a silicide of the first and second metals and a germanide of the first and second metals. In an example embodiment, a concentration of the first metal of a first portion of the first metal silicide pattern <NUM> that is farther from the first source/drain layer <NUM> may be greater than a concentration of the first metal of a second portion of the first metal silicide pattern <NUM> that is nearer to the first source/drain layer <NUM>.

The second contact plug structure <NUM> may further include a second metal layer <NUM> disposed between the second metal silicide pattern <NUM> and the second conductive pattern <NUM>. The second metal layer <NUM> may include the first metal.

The second metal silicide pattern <NUM> may include a silicide of the first and second metals. In an example embodiment, a concentration of the first metal of a first portion of the second metal silicide pattern <NUM> that is nearer to the second metal layer <NUM> may be greater than a concentration of the first metal of a second portion of the second metal silicide pattern <NUM> that is farther from the second metal layer <NUM>.

In embodiments, a ratio of the first metal to the second metal included in the first metal silicide pattern <NUM> may be greater than a ratio of the first metal to the second metal included in the second metal silicide pattern <NUM>, and accordingly, a work function of the first metal silicide pattern <NUM> may be greater than a work function of the second metal silicide pattern <NUM>. Thus, a contact resistance between the first source/drain layer <NUM> and the first contact plug structure <NUM> and a contact resistance between the second source/drain layer <NUM> and the second contact plug structure <NUM> may be reduced.

<FIG> and <FIG> are cross-sectional views for reference in describing a method of manufacturing the semiconductor device of <FIG> and <FIG>, and may correspond to <FIG> and <FIG>, respectively.

This method of manufacturing the semiconductor device of <FIG> and <FIG> may include processes substantially the same as or similar to those of <FIG> and <FIG>, and thus repeated explanations of already described elements are omitted herein.

Referring to <FIG>, unlike the processes illustrated with reference to <FIG>, the first CVD process may be performed using a source gas containing the second metal.

Accordingly, a first preliminary metal silicide pattern 280a including a silicide of the second metal may be formed on the upper surface of the first source/drain layer <NUM> exposed by the third opening <NUM>, and the second metal silicide pattern <NUM> including a silicide of the second metal may be formed on the upper surface of the second source/drain layer <NUM> exposed by the fourth opening <NUM>. The first preliminary metal silicide pattern 280a may also include a germanide of the second metal.

In an example embodiment, the first CVD process may be performed selectively, and a thickness of the second metal silicide pattern <NUM> may be formed to be greater than a thickness of the first preliminary metal silicide pattern 280a.

Referring to <FIG>, unlike the processes illustrated with reference to <FIG>, the second CVD process may be performed using a source gas containing the first metal.

Accordingly, a second metal layer <NUM> including the first metal may be formed on the second metal silicide pattern <NUM>, and the first preliminary metal silicide pattern 280a may be converted into a first metal silicide pattern <NUM> including a silicide of the first and second metals and a germanide of the first and second metals.

The first metal may diffuse into the second metal silicide pattern <NUM>. However, the second metal silicide pattern <NUM> may have a relatively large thickness, and thus, the first metal may not diffuse into an entire portion of the second metal silicide pattern <NUM>. Accordingly, a portion of the first metal may remain on the second metal silicide pattern <NUM> to form the second metal layer <NUM>.

The first metal may be diffused into an entire portion of the first preliminary metal silicide pattern 280a, and thus the first preliminary metal silicide pattern 280a may be converted into the first metal silicide pattern <NUM>. Accordingly, a ratio of the first metal to the second metal included in the first metal silicide pattern <NUM> may be greater than a ratio of the first metal to the second metal included in the second metal silicide pattern <NUM>.

In an example embodiment, a concentration of the first metal of a first portion of the first metal silicide pattern <NUM> that is farther from the first source/drain layer <NUM> may be greater than a concentration of the first metal of a second portion of the first metal silicide pattern <NUM> that is nearer to the first source/drain layer <NUM>. In addition, a concentration of the first metal of a first portion of the second metal silicide pattern <NUM> that is nearer to the second metal layer <NUM> may be greater than a concentration of the first metal of a second portion of the second metal silicide pattern <NUM> that is farther from the second metal layer <NUM>.

This semiconductor device may be substantially the same as or similar to that of <FIG>, except that the first contact plug structure <NUM> do not include the first metal layer <NUM>, and thus repeated explanations of already described elements are omitted herein.

Referring to <FIG> and <FIG>, the first metal layer <NUM> need not be formed on the first metal silicide pattern <NUM>, and thus, an upper surface of the first metal silicide pattern <NUM> may contact a lower surface of the first conductive pattern <NUM>.

When the semiconductor device shown in <FIG> and <FIG> is manufactured, the second metal may be diffused into an entire portion of the first metal silicide pattern <NUM> so that the first metal layer <NUM> including the second metal may not remain on the first metal silicide pattern <NUM> during the second CVD process described with reference to <FIG>.

However, by adjusting the selectivity of the first CVD process and/or performing the second CVD process selectively, a ratio of the first metal to the second metal included in the first metal silicide pattern <NUM> may be greater than a ratio of the first metal to the second metal in the second metal silicide pattern <NUM>.

In an example embodiment, a concentration of the second metal of a first portion of the first metal silicide pattern <NUM> that is nearer to the first conductive pattern <NUM> may be greater than a concentration of the second metal of a second portion of the first metal silicide pattern <NUM> that is farther from the first conductive pattern <NUM>, and a concentration of the second metal of a first portion of the second metal silicide pattern <NUM> that is nearer to the second conductive pattern <NUM> may be greater than a concentration of the second metal of a second portion of the second metal silicide pattern <NUM> that is farther from the second conductive pattern <NUM>.

The first and second CVD processes may be performed using the source gases including the first and second metals, respectively, however, the inventive concept is not limited thereto. That is, for example, the first and second CVD processes may also be performed using source gases including the second and first metals, respectively.

In this case, a concentration of the first metal of a first portion of the second metal silicide pattern <NUM> that is nearer to the second conductive pattern <NUM> may be greater than a concentration of the first metal of a second portion of the second metal silicide pattern <NUM> that is farther from the second conductive pattern <NUM>, and a concentration of the first metal of a first portion of the first metal silicide pattern <NUM> that is nearer to the first conductive pattern <NUM> may be greater than a concentration of the first metal of a second portion of the first metal silicide pattern <NUM> that is farther from the first conductive pattern <NUM>.

This semiconductor device may be substantially the same as or similar to that of <FIG>, except for the first and second silicide patterns <NUM> and <NUM>, and thus repeated explanations of already described elements are omitted herein.

Referring to <FIG> and <FIG>, the first metal silicide pattern <NUM> may include a first lower portion 280c and a first upper portion 280d sequentially stacked, and the second metal silicide pattern <NUM> may include a second lower portion 281c and a second upper portion 281d sequentially stacked.

In example embodiments, the first lower portion 280c may include a silicide of the first metal and a germanide of the first metal, and the first upper portion 280d may include a silicide of the second metal. However, the first lower portion 280c may further include a silicide of the second metal and a germanide of the second metal, and the first upper portion 280d may further include a silicide of the first metal. In an example embodiment, a concentration of the second metal of a first portion of the first lower portion 280c that is nearer to the first upper portion 280d may be greater than a concentration of the second metal of a second portion of the first lower portion 280c that is farther from the first upper portion 280d.

In example embodiments, the second lower portion 281c may include a silicide of the first metal, and the second upper portion 281d may include a silicide of the second metal. However, the second lower portion 281c may further include a silicide of the second metal, and the second upper portion 281d may further include a silicide of the first metal. In an example embodiment, a concentration of the second metal of a first portion of the second lower portion 281c that is nearer to the second upper portion 281d may be greater than a concentration of the second metal of a second portion of the second lower portion 281c that is farther from the second upper portion 281d.

In example embodiments, a thickness of the first lower portion 280c included in the first metal silicide pattern <NUM> may be greater than a thickness of the second lower portion 281c included in the second metal silicide pattern <NUM>.

When the semiconductor device illustrated in <FIG> and <FIG> is manufactured, the second CVD process described with reference to <FIG> may be performed using a silicon source gas together with the source gas including the second metal.

That is, the first CVD process may be performed to form the first lower portion 280c including a silicide of the first metal and a germanide of the first metal on the upper surface of the first source/drain layer <NUM>, and to form the second lower portion 281c including a silicide of the first metal on the upper surface of the second source/drain layer <NUM>.

The first CVD process may be performed selectively, and a thickness of the first lower portion 280c may be formed to be greater than a thickness of the second lower portion 281c.

Thereafter, the second CVD process described with reference to <FIG> may be performed by using a silicon source gas such as silane (SiH<NUM>) together with the source gas containing the second metal. Accordingly, the first upper portion 280d including a silicide of the second metal may be formed on the first lower portion 280c, and the second upper portion 281d including a silicide of the second metal may be formed on the second lower portion 281c may be formed.

However, in example embodiments, the first metal included in the first and second lower portions 280c and 281c may be diffused into the first and second upper portions 280d and 281d by a heat accompanying the second CVD process and/or a subsequent annealing process. Similarly, the second metal included in the first and second upper portions 280d and 281d may be diffused into the first and second lower portions 280c and 281c.

Accordingly, concentrations of the second metal of first portions of the first and second lower portions 280c and 281c that are nearer to the first and second upper portions 280d and 281d, respectively, may be greater than concentrations of the second metal of second portions of the first and second lower portions 280c and 281c that are farther from the first and second upper portions 280d and 281d, respectively, and concentrations of the first metal of first portions of the first and second upper portions 280b and 281b that are nearer to the first and second lower portions 280c and 281c, respectively, may be greater than concentrations of the first metal of second portions of the first and second upper portions 280b and 281b that are farther from the first and second lower portions 280c and 281c, respectively.

The first and second CVD processes may be performed using the source gas of the first and second metals, respectively, however, the inventive concept is not limited thereto, and, for example, the first and second CVD processes may also be performed using source gases of the second and first metals, respectively.

In this case, in an example embodiment, concentrations of the first metal of first portions of the first and second lower portions 280c and 281c that are nearer to the first and second upper portions 280d and 281d, respectively, may be greater than concentrations of the first metal of second portions of the first and second lower portions 280c and 281c that are farther from the first and second upper portions 280d and 281d, respectively, and concentrations of the second metal of first portions of the first and second upper portions 280b and 281b that are nearer to the first and second lower portions 280c and 281c, respectively, may be greater than concentrations of the second metal of second portions of the first and second upper portions 280b and 281b that are farther from the first and second lower portions 280c and 281c, respectively.

This semiconductor device may be substantially the same as or similar to that of <FIG>, except that the first and second contact plug structures <NUM> and <NUM> may further include first and second barrier patterns <NUM> and <NUM>, respectively, and thus repeated explanations of already described elements are omitted herein.

Referring to <FIG> and <FIG>, the first barrier pattern <NUM> may be formed on the first metal layer <NUM> to cover a lower surface and sidewalls of the first conductive pattern <NUM>, and the second barrier pattern may be formed on the second metal silicide pattern <NUM> to cover a lower surface and sidewalls of the second conductive pattern <NUM>.

Each of the first and second barrier patterns <NUM> and <NUM> may include, for example, a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, etc..

<FIG> are a plan view and cross-sectional views illustrating a semiconductor device in accordance with example embodiments. Particularly, <FIG> is the plan view, <FIG> is a cross-sectional view taken along line E-E' of <FIG>, <FIG> is a cross-sectional view taken along line F-F' of <FIG>, and <FIG> includes cross-sectional views taken along lines G-G' and H-H' of <FIG>, respectively.

This semiconductor device may include elements substantially the same as or similar to those illustrated with reference to <FIG>, and thus repeated explanations of already described elements are omitted herein.

As illustrated below, the semiconductor device may be a multi-bridge channel field effect transistor (MBCFET) including semiconductor patterns <NUM> that may be spaced apart from each other in the third direction D3 and serve as channels, respectively. Other elements except for the semiconductor patterns <NUM> may have similar functions and structures as corresponding elements included in the finFET of <FIG>, and thus repeated explanations of already described elements are omitted herein.

Referring to <FIG>, the semiconductor device may include a second active pattern <NUM>, a second isolation pattern <NUM>, third and fourth gate structures <NUM> and <NUM>, the semiconductor patterns <NUM>, third and fourth source/drain layers <NUM> and <NUM>, third and fourth gate spacers <NUM> and <NUM>, third and fourth contact plug structures <NUM> and <NUM>, and third and fourth insulating interlayers <NUM> and <NUM> on a substrate <NUM>.

The second active pattern <NUM> and the second isolation pattern <NUM> may correspond to the first active pattern <NUM> and the first isolation pattern <NUM>, respectively, of <FIG>.

In example embodiments, a plurality of semiconductor patterns <NUM> may be formed at a plurality of levels, respectively, and may be spaced apart from each other in the third direction D3 from an upper surface of the second active pattern <NUM>. Each of the plurality of semiconductor patterns <NUM> may extend in the first direction D1. <FIG> and <FIG> show three semiconductor patterns <NUM> at three levels, respectively, however, the inventive concept is not limited thereto.

In example embodiments, the semiconductor pattern <NUM> may be a nano-sheet or nano-wire including a semiconductor material, e.g., silicon, germanium, etc. In example embodiments, the semiconductor pattern <NUM> may serve as a channel in a transistor, and thus may also be referred to as a channel.

The third gate structure <NUM> and the third gate spacer <NUM> may correspond to the first gate structure <NUM> and the first gate spacer <NUM>, respectively, of <FIG>, and the fourth gate structure <NUM> and the fourth gate spacer <NUM> may correspond to the second gate structure <NUM> and the second gate spacer <NUM>, respectively, of <FIG>.

Thus, the third gate structure <NUM> may extend in the second direction D2 on the second active pattern <NUM> and the second isolation pattern <NUM>, and may include a third gate insulation pattern <NUM> and a third gate electrode <NUM>, and a third capping pattern <NUM> on the third gate insulation pattern <NUM> and the third gate electrode <NUM>. Additionally, the fourth gate structure <NUM> may extend in the second direction D2 on the second active pattern <NUM> and the second isolation pattern <NUM>, and may include a fourth gate insulation pattern <NUM> and a fourth gate electrode <NUM>, and a fourth capping pattern <NUM> on the fourth gate insulation pattern <NUM> and the fourth gate electrode <NUM>.

Each of the third and fourth gate structures <NUM> and <NUM> may surround a central portion in the first direction D1 of each of the semiconductor patterns <NUM>, and may cover lower and upper surfaces and opposite sidewalls in the second direction D2 of each of the semiconductor patterns <NUM>.

Thus, the third gate insulation pattern <NUM> may be formed on a surface of each semiconductor pattern <NUM>, upper surfaces of the second active pattern <NUM> and the second isolation pattern <NUM>, a sidewall of the third source/drain layer <NUM> and an inner sidewall of the third gate spacer <NUM>, and each of the third gate electrode <NUM> may fill a space between the semiconductor patterns <NUM> spaced apart from each other in the third direction D3, a space between the second active pattern <NUM> and a lowermost one of the semiconductor patterns <NUM>, and a space between the third gate spacers <NUM> on an uppermost one of the semiconductor patterns <NUM>.

Additionally, the fourth gate insulation pattern <NUM> may be formed on a surface of each semiconductor pattern <NUM>, upper surfaces of the second active pattern <NUM> and the second isolation pattern <NUM>, a sidewall of the fourth source/drain layer <NUM> and an inner sidewall of the fourth gate spacer <NUM>, and each of the fourth gate electrode <NUM> may fill a space between the semiconductor patterns <NUM> spaced apart from each other in the third direction D3, a space between the second active pattern <NUM> and a lowermost one of the semiconductor patterns <NUM>, and a space between the fourth gate spacers <NUM> on an uppermost one of the semiconductor patterns <NUM>.

The third and fourth source/drain layers <NUM> and <NUM> may correspond to the first and second source/drain layers <NUM> and <NUM>, respectively, of <FIG>. The third and fourth source/drain layers <NUM> and <NUM> may be formed in fifth and sixth openings <NUM> and <NUM>, respectively, that may be formed on portions of the second active pattern <NUM> adjacent to the third and fourth gate structures <NUM> and <NUM>, respectively.

The third and fourth contact plug structures <NUM> and <NUM> may correspond to the first and second contact plug structures <NUM> and <NUM>, respectively, of <FIG>. Accordingly, the third and fourth contact plug structures <NUM> and <NUM> may extend through the third and fourth insulating interlayer <NUM> and <NUM> to contact upper surfaces of the third and fourth source/drain layers <NUM> and <NUM>, respectively. The third and fourth contact plug structures <NUM> and <NUM> may partially extend though upper portions of the third and fourth source/drain layers <NUM> and <NUM>, respectively.

A third metal silicide pattern <NUM>, a third metal layer <NUM> and a third conductive pattern <NUM> included in the third contact plug structure <NUM> may correspond to the first metal silicide pattern <NUM>, the first metal layer <NUM> and the first conductive pattern <NUM>, respectively, of <FIG>. A fourth metal silicide pattern <NUM> and a fourth conductive pattern <NUM> included in the fourth contact plug structure <NUM> may correspond to the second metal silicide pattern <NUM> and the second conductive pattern <NUM>, respectively, of <FIG>.

<FIG>, <FIG> and <FIG> are cross-sectional views taken along lines E-E' of corresponding plan views, respectively, <FIG>, <FIG>, <FIG> and <FIG> are cross-sectional views taken along lines F-F' of corresponding plan views, respectively, and <FIG> is a cross-sectional view taken along line G-G' and H-H' of <FIG>.

This method may include processes substantially the same as or similar to those illustrated with reference to <FIG> and <FIG>, and thus repeated explanations of already described elements are omitted herein.

Referring to <FIG> and <FIG>, a sacrificial layer and a semiconductor layer may be alternately and repeatedly stacked on a substrate <NUM>, a first etching mask extending in the first direction D1 may be formed on an uppermost one of the semiconductor layers, and the semiconductor layers, the sacrificial layers and an upper portion of the substrate <NUM> may be etched using the third etching mask.

Thus, a second active pattern <NUM> extending in the first direction D1 may be formed on the substrate <NUM>, and a fin structure including sacrificial lines <NUM> and semiconductor lines <NUM> alternately and repeatedly stacked in the third direction D3 may be formed on the second active pattern <NUM>. In example embodiments, a plurality of fin structures may be spaced apart from each other in the second direction D2 on the substrate <NUM>.

<FIG> shows three sacrificial lines <NUM> at three levels, respectively, and three semiconductor lines <NUM> at three levels, respectively, however, the inventive concept may not be limited thereto. The sacrificial lines <NUM> may include a material having an etching selectivity with respect to the substrate <NUM> and the semiconductor lines <NUM>, e.g., silicon-germanium.

A second isolation pattern <NUM> may be formed on the substrate <NUM> to cover a sidewall of the second active pattern <NUM>.

Referring to <FIG>, third and fourth dummy gate structures <NUM> and <NUM> may be formed on the first and second regions I and II, respectively, of the substrate <NUM> to partially cover the fin structure and the second isolation pattern <NUM>.

Particularly, a second dummy gate insulation layer, a second dummy gate electrode layer and a second dummy gate mask layer may be sequentially formed on the substrate <NUM> having the fin structure and the second isolation pattern <NUM> thereon, a second etching mask extending in the second direction D2 may be formed on the second dummy gate mask layer, and the second dummy gate mask layer may be etched using the second etching mask to form a second dummy gate mask <NUM>.

The second dummy gate electrode layer and the second dummy gate insulation layer may be etched using the second dummy gate mask <NUM> as an etching mask to form a second dummy gate electrode <NUM> and a second dummy gate insulation pattern <NUM>, respectively, on the substrate <NUM>.

The second dummy gate insulation pattern <NUM>, the second dummy gate electrode <NUM> and the second dummy gate mask <NUM> sequentially stacked in the third direction D3 on the second active pattern <NUM> and a portion of the second isolation pattern <NUM> adjacent thereto on the first region I of the substrate <NUM> may form a third dummy gate structure <NUM>, and the second dummy gate insulation pattern <NUM>, the second dummy gate electrode <NUM> and the second dummy gate mask <NUM> sequentially stacked in the third direction D3 on the second active pattern <NUM> and a portion of the second isolation pattern <NUM> adjacent thereto on the second region II of the substrate <NUM> may form a fourth dummy gate structure <NUM>.

In example embodiments, each of the third and fourth dummy gate structures <NUM> and <NUM> may extend in the second direction D2 on the fin structure and the second isolation pattern <NUM>, and may cover an upper surface and opposite sidewalls in the second direction D2 of the fin structure.

In example embodiments, a plurality of third dummy gate structures <NUM> may be spaced apart from each other in the first direction D1 on the first region I of the substrate <NUM>, and a plurality of fourth dummy gate structures <NUM> may be spaced apart from each other in the first direction D1 on the second region II of the substrate <NUM>.

Referring to <FIG>, third and fourth gate spacers <NUM> and <NUM> may be formed on sidewalls of the third and fourth dummy gate structures <NUM> and <NUM>, respectively.

Particularly, a second spacer layer may be formed on the substrate <NUM> having the fin structure, the second isolation pattern <NUM> and the third and fourth dummy gate structures <NUM> and <NUM> thereon, and may be anisotropically etched to form the third and fourth gate spacers <NUM> and <NUM> covering each of opposite sidewalls in the first direction D1 of the third and fourth dummy gate structures <NUM> and <NUM>, respectively.

The fin structure and an upper portion of the second active pattern <NUM> on the first region I of the substrate <NUM> may be etched using the third dummy gate structure <NUM> and the third gate spacer <NUM> as an etching mask to form a fifth opening <NUM>, and the fin structure and an upper portion of the second active pattern <NUM> on the second region II of the substrate <NUM> may be etched using the fourth dummy gate structure <NUM> and the fourth gate spacer <NUM> as an etching mask to form an sixth opening <NUM>.

Thus, the sacrificial lines <NUM> and the semiconductor lines <NUM> under the third and fourth dummy gate structures <NUM> and <NUM> and the third and fourth gate spacers <NUM> and <NUM> may be transformed into sacrificial patterns <NUM> and semiconductor patterns <NUM>, respectively, and the fin structure extending in the first direction D1 may be divided into a plurality of portions spaced apart from each other in the first direction D1.

Hereinafter, the third dummy gate structure <NUM>, the third gate spacers <NUM> on respective opposite sidewalls of the third dummy gate structure <NUM> and the fin structure may be referred to as a first stack structure, and the fourth dummy gate structure <NUM>, the fourth gate spacers <NUM> on respective opposite sidewalls of the fourth dummy gate structure <NUM> and the fin structure may be referred to as a second stack structure.

In example embodiments, each of the first and second stack structures may extend in the second direction D2. In example embodiments, a plurality of first stack structures may be spaced apart from each other in the first direction D1 on the first region I of the substrate <NUM>, and a plurality of second stack structures may be spaced apart from each other in the first direction D1 on the second region II of the substrate <NUM>.

A portion of each of the sacrificial patterns <NUM> adjacent to the fifth and sixth openings <NUM> and <NUM> may be removed to form a gap, and an inner spacer (not shown) may be formed in the gap.

A selective epitaxial growth (SEG) process may be performed using the upper surface of the second active pattern <NUM> and the sidewalls of the semiconductor patterns <NUM> and the sacrificial patterns <NUM> exposed by the fifth and sixth openings <NUM> and <NUM> as a seed to form third and fourth source/drain layers <NUM> and <NUM> in the fifth and sixth openings <NUM> and <NUM>, respectively.

In an example embodiment, a single crystalline silicon-germanium layer doped with p-type impurities may be formed as the third source/drain layer <NUM>, and a single crystalline silicon layer doped with n-type impurities or a single crystalline silicon carbide layer doped with n-type impurities may be formed as the fourth source/drain layer <NUM>.

Referring to <FIG>, a third insulating interlayer <NUM> may be formed on the substrate <NUM> to cover the first and second stack structures and the third and fourth source/drain layers <NUM> and <NUM>, and a planarization process may be performed until upper surfaces of the second dummy gate electrodes <NUM> included in the first and second stack structures, respectively, are exposed so that an upper portion of the third insulating interlayer <NUM> and the second dummy gate masks <NUM> included in the third and fourth dummy gate structures <NUM> and <NUM>, respectively.

The second dummy gate electrodes <NUM>, the second dummy gate insulation patterns <NUM> and the sacrificial patterns <NUM> may be removed by, e.g., a wet etching process and/or a dry etching process. Thus, a seventh opening <NUM> exposing an inner sidewall of the third gate spacer <NUM> and an upper surface of an uppermost one of the semiconductor patterns <NUM>, and an eighth opening <NUM> exposing a sidewall of the third source/drain layer <NUM>, surfaces of the semiconductor patterns <NUM> and an upper surface of the second active pattern <NUM> may be formed on the first region I of the substrate <NUM>. Additionally, a ninth opening <NUM> exposing an inner sidewall of the fourth gate spacer <NUM> and an upper surface of an uppermost one of the semiconductor patterns <NUM>, and a tenth opening <NUM> exposing a sidewall of the fourth source/drain layer <NUM>, surfaces of the semiconductor patterns <NUM> and an upper surface of the second active pattern <NUM> may be formed on the second region II of the substrate <NUM>.

Referring to <FIG>, processes substantially the same as or similar to those illustrated with reference to <FIG> may be performed.

Thus, a third gate structure <NUM> including a third gate insulation pattern <NUM> on the upper surface of the second active pattern <NUM>, the upper surface of the second isolation pattern <NUM>, the sidewall of the third source/drain layer <NUM>, the surfaces of the semiconductor patterns <NUM> and an inner lower sidewall of the third gate spacer <NUM> in the seventh and eighth openings <NUM> and <NUM>, a third gate electrode <NUM> on the third gate insulation pattern <NUM> and filling a lower portion of the seventh opening <NUM> and the eighth opening <NUM>, and a third capping pattern <NUM> on the third gate insulation pattern <NUM> and the third gate electrode <NUM> and filling an upper portion of the seventh opening <NUM> to contact an inner upper sidewall of the third gate spacer <NUM> may be formed.

Additionally, a fourth gate structure <NUM> including a fourth gate insulation pattern <NUM> on the upper surface of the second active pattern <NUM>, the upper surface of the second isolation pattern <NUM>, the sidewall of the fourth source/drain layer <NUM>, the surfaces of the semiconductor patterns <NUM> and an inner lower sidewall of the fourth gate spacer <NUM> in the ninth and tenth openings <NUM> and <NUM>, a fourth gate electrode <NUM> on the fourth gate insulation pattern <NUM> and filling a lower portion of the ninth opening <NUM> and the tenth opening <NUM>, and a fourth capping pattern <NUM> on the fourth gate insulation pattern <NUM> and the fourth gate electrode <NUM> and filling an upper portion of the ninth opening <NUM> to contact an inner upper sidewall of the fourth gate spacer <NUM> may be formed.

In an example embodiment, an interface pattern (not shown) including, e.g., silicon oxide may be further formed on the upper surface of the second active pattern <NUM> and the surfaces of the semiconductor patterns <NUM>.

Referring to <FIG> again, processes substantially the same as or similar to those illustrated with reference to <FIG> and <FIG> may be performed.

Accordingly, a fourth insulating interlayer <NUM> may be formed on the third and fourth gate structures <NUM> and <NUM>, the third and fourth gate spacers <NUM> and <NUM> and the third insulating interlayer <NUM>, and third and fourth contact plug structures <NUM> and <NUM> may be formed to extend through the third and fourth insulating interlayers <NUM> and <NUM> to contact upper surfaces of the third and fourth source/drain layers <NUM> and <NUM>, respectively.

The third contact plug structure <NUM> may include a third metal silicide pattern <NUM>, a third metal layer <NUM> and a third conductive pattern <NUM>, and the fourth contact plug structure <NUM> may include a fourth metal silicide pattern <NUM> and a fourth conductive pattern <NUM>.

<FIG> are cross-sectional views illustrating semiconductor devices in accordance with example embodiments, and may correspond to <FIG>.

These semiconductor devices are applications of the semiconductor devices including finFETs shown in <FIG>, <FIG>, <FIG> and <FIG>, respectively, to the semiconductor device of <FIG> including an MBCFET, and thus, repeated explanations of already described elements are omitted herein.

Referring to <FIG>, the third contact plug structure <NUM> may not include the third metal layer <NUM>, and thus an upper surface of the third metal silicide pattern <NUM> may contact a lower surface of the third conductive pattern <NUM>.

The third metal silicide pattern <NUM> may include a silicide of the first and second metals and a germanide of the first and second metals. In an example embodiment, a concentration of the first metal of a first portion of the third metal silicide pattern <NUM> that is farther from the third source/drain layer <NUM> may be greater than a concentration of the first metal of a second portion of the third metal silicide pattern <NUM> that is nearer to the third source/drain layer <NUM>.

The fourth contact plug structure <NUM> may further include a fourth metal layer <NUM> disposed between the fourth metal silicide pattern <NUM> and the fourth conductive pattern <NUM>, and the fourth metal layer <NUM> may include the first metal.

The fourth metal silicide pattern <NUM> may include a silicide of the first and second metals. In an example embodiment, a concentration of the first metal of a first portion of the fourth metal silicide pattern <NUM> that is nearer to the fourth metal layer <NUM> may be greater than a concentration of the first metal of a second portion of the fourth metal silicide pattern <NUM> that is farther to the fourth metal layer <NUM>.

Referring to <FIG>, the third contact plug structure <NUM> need not include the third metal layer <NUM>, and thus an upper surface of the third metal silicide pattern <NUM> may contact a lower surface of the third conductive pattern <NUM>.

In an example embodiment, a concentration of the second metal of a first portion of the third metal silicide pattern <NUM> that is nearer to the third conductive pattern <NUM> may be greater than a concentration of the second metal of a second portion of the third metal silicide pattern <NUM> that is farther from the third conductive pattern <NUM>. Also, in an example embodiment, a concentration of the second metal of a first portion of the fourth metal silicide pattern <NUM> that is nearer to the fourth conductive pattern <NUM> may be greater than a concentration of the second metal of a second portion of the fourth metal silicide pattern <NUM> that is farther from the fourth conductive pattern <NUM>.

In contrast, in an example embodiment, a concentration of the first metal of a first portion of the fourth metal silicide pattern <NUM> that is nearer to the third conductive pattern <NUM> may be greater than a concentration of the first metal of a second portion of the fourth metal silicide pattern <NUM> that is farther from the third conductive pattern <NUM>, and a concentration of the first metal of a first portion of the third metal silicide pattern <NUM> that is nearer to the third conductive pattern <NUM> may be greater than a concentration of the first metal of a second portion of the third metal silicide pattern <NUM> that is farther from the third conductive pattern <NUM>.

Referring to <FIG>, the third contact plug structure <NUM> may include a third metal silicide pattern and a third conductive pattern <NUM>, and the third metal silicide pattern may include a third lower portion 630c and a third upper portion 630d that may be sequentially stacked.

The fourth contact plug structure <NUM> may include a fourth metal silicide pattern and a fourth conductive pattern <NUM>, and the fourth metal silicide pattern may include a fourth lower portion 631c and a fourth upper portion 631d that may be sequentially stacked.

In example embodiments, the third lower portion 630c may include a silicide of the first metal and a germanide of the first metal, and the third upper portion 630d may include a silicide of the second metal. However, the third lower portion 630c may further include a silicide of the second metal and a germanide of the second metal, and the third upper portion 630d may further include a silicide of the first metal. In an example embodiment, a concentration of the second metal of a first portion of the third lower portion 630c that is nearer to the third upper portion 630d may be greater than a concentration of the second metal of a second portion of the third lower portion 630c that is farther from the third upper portion 630d.

In example embodiments, the fourth lower portion 631c may include a silicide of the first metal, and the fourth upper portion 631d may include a silicide of the second metal. However, the fourth lower portion 631c may further include a silicide of the second metal, and the fourth upper portion 631d may further include a silicide of the first metal. In an example embodiment, a concentration of the second metal of a first portion of the fourth lower portion 631c that is nearer to the fourth upper portion 631d may be greater than a concentration of the second metal of a second portion of the fourth lower portion 631c that is farther from the fourth upper portion 631d.

Referring to <FIG>, the third contact plug structure <NUM> may further include a third barrier pattern <NUM> disposed on the third metal layer <NUM> and covering a lower surface and sidewalls of the third conductive pattern <NUM>. The fourth contact plug structure <NUM> may further include a fourth barrier pattern <NUM> disposed on the fourth metal silicide pattern <NUM> and covering a lower surface and sidewalls of the fourth conductive pattern <NUM>.

The above-described semiconductor device may be used in various memory devices and systems including contact plugs. For example, the semiconductor device may be applied to a logic device such as a central processing unit (CPU), an application processor (AP), etc. As alternative examples, the semiconductor device may be applied to a volatile memory device such as a DRAM device, an SRAM device, etc., or to a non-volatile memory device such as a flash memory device, a PRAM device, an MRAM device, an RRAM device, etc..

Claim 1:
A semiconductor device, comprising:
a substrate (<NUM>) including a first region and a second region;
a first gate structure (<NUM>) on the first region of the substrate,
a first source/drain layer (<NUM>) on a portion of the substrate adjacent to the first gate structure;
a second gate structure (<NUM>) on the second region of the substrate;
a second source/drain layer (<NUM>) on a portion of the substrate adjacent to the second gate structure;
a first contact plug (<NUM>) including:
a first metal silicide pattern (<NUM>) on the first source/drain layer, the first metal silicide pattern including a silicide of a first metal and a silicide of a second metal different from the first metal; and
a first conductive pattern (<NUM>) on the first metal silicide pattern; and
a second contact plug (<NUM>) including:
a second metal silicide pattern (<NUM>) on the second source/drain layer, the second metal silicide pattern including a silicide of the first metal and a silicide of the second metal; and
a second conductive pattern (<NUM>) on the second metal silicide pattern,
wherein a first ratio of the first metal to the second metal included in the first metal silicide pattern is different from a second ratio of the first metal to the second metal included in the second metal silicide pattern.