Patent Description:
Power transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) are used for selectively delivering current to and from a load in a power electronics system. In some situations, the load may cause a short circuit across a power transistor or otherwise cause a very high current to run through the power transistor. Absent overcurrent protection mechanisms, the power transistor will fail after an overcurrent withstand time.

State of the art mechanisms for overcurrent protection have focused on providing overcurrent protection circuitry that is integrated into the semiconductor die of the power transistor. While such overcurrent protection circuitry may be effective in increasing the overcurrent withstand time of the power transistor, it also takes up active area on the semiconductor die. Accordingly, there is less active area to devote to the current carrying portion of the power transistor, and thus a current carrying capacity of the power transistor will be reduced unless a total area of the semiconductor die is increased. Often, power transistors for power electronics will be provided using a wide bandgap semiconductor material system such as gallium nitride or silicon carbide. These materials are often valuable, and thus increasing the area of the semiconductor die is generally undesirable. <CIT> discloses a power module which has a self arc-suppression type semiconductor device such as an IGBT and a function for protecting the above semiconductor device in order to, in particular, prevent an improper detection of an overcurrent in the IGBT. A resistance value of the resistor is determined taking into consideration the amount of an abrupt change of a sense emitter current. Also, a time constant is determined based on the capacitance of the capacitor such that it is equal to an attenuation time constant after an abrupt rise of the sense emitter current. Thus, the improper detection of the overcurrent due to the abrupt rise of the sense emitter current can be prevented.

There remains a present need for improved systems and methods for protecting power transistors from overcurrent events.

In one embodiment, support circuitry for a power transistor includes a feedback switching element and switching control circuitry. The power transistor includes a control node, a Kelvin connection node, a first power switching node, a second power switching node, and a semiconductor structure between the nodes such that a resistance between the first power switching node and the second power switching node is based on a control signal provided between the control node and the Kelvin connection node. The feedback switching element is coupled between the Kelvin connection node and the second power switching node. The switching control circuitry is configured to cause the feedback switching element to couple the Kelvin connection node to the second power switching node after the power transistor is switched from a blocking mode of operation to a conduction mode of operation and cause the feedback switching element to isolate the Kelvin connection node from the second power switching node before the power transistor is switched from the conduction mode of operation to the blocking mode of operation. By coupling the Kelvin connection node to the second power switching node after the power transistor is switched from the blocking mode of operation to the conduction mode of operation, an inherent feedback mechanism is introduced to protect the power transistor against overcurrent events. By isolating the Kelvin connection node from the second power switching node before the power transistor is switched from the conduction mode of operation to the blocking mode of operation, the switching speed of the power transistor is maintained.

In one embodiment, a sense resistor is coupled between the Kelvin connection node and the feedback switching element. Sense circuitry is configured to measure a voltage across the sense resistor to detect overcurrent events. Since the feedback switching element, when closed, provides a current path parallel to a power loop of the power transistor but with much lower current, overcurrent events may be easily detected in a fast manner without requiring resistive elements that are tolerant of extremely high voltages and/or currents and power dissipation.

In one embodiment, a first overcurrent protection switching element is coupled in series with an overcurrent protection diode (or a predetermined voltage) between the sense resistor and the control node. A second overcurrent protection switching element is coupled between the control node and a predetermined voltage. On detection of an overcurrent event when the power transistor is operating in a first quadrant mode of operation, the first overcurrent protection switch is closed to clamp a voltage at the control node and partially or fully turn off the power transistor. On detection of an overcurrent event when the power transistor is operating in a third quadrant mode of operation, the second overcurrent protection switch is closed to provide the predetermined voltage at the control node and thus partially or fully turn on the power transistor. In either case, the overcurrent withstand time of the power transistor is significantly increased, sometimes indefinitely.

<FIG> shows a conventional gate drive system <NUM>. The conventional gate drive system <NUM> includes gate drive circuitry <NUM> configured to drive a power transistor Q<NUM> to selectively deliver power to a load (not shown). The power transistor Q<NUM> is shown as a metal-oxide-semiconductor field-effect transistor (MOSFET) including a control node C, a first power switching node PS<NUM>, a second power switching node PS<NUM>, and a Kelvin connection node K. The MOSFET includes a semiconductor structure between the control node C, the first power switching node PS<NUM>, the second power switching node PS<NUM>, and the Kelvin connection node K. The semiconductor structure is configured such that a control signal CNT provided between the control node C and the Kelvin connection node K varies a resistance between the first power switching node PS<NUM> and the second power switching node PS<NUM>. The control node C is coupled to a gate region in the semiconductor structure, the first power switching node PS<NUM> is coupled to a drain region in the semiconductor structure, and the second power switching node PS<NUM> and the Kelvin connection node K are coupled to a source region in the semiconductor structure. By varying a resistance between the first power switching node PS<NUM> and the second power switching node PS<NUM>, a current through the power transistor Q<NUM> and a voltage across the power transistor Q<NUM> may similarly be varied to selectively deliver power to a load. Those skilled in the art will readily appreciate the structure and functionality of the power transistor Q<NUM> and thus it is not discussed in detail herein.

In some embodiments, a freewheeling diode Dfw is coupled in antiparallel with the power transistor Q<NUM> for bidirectional current conduction. The freewheeling diode Dfw may be external to the power transistor Q<NUM> or may be internal to the power transistor Q<NUM> (i.e., an internal body diode).

As discussed above, both the second power switching node PS<NUM> and the Kelvin connection node K are coupled to a source region in the semiconductor structure of the power transistor Q<NUM>. Providing a separate connection to the source region effectively isolates a control loop (between the control node CNT and the Kelvin connection node K) of the power transistor Q<NUM> from a power switching loop (between the first power switching node PS<NUM> and the second power switching node PS<NUM>). In particular, doing so reduces the impact that a stray inductance of the connection to the second power switching node PS<NUM> may otherwise have on the control loop to avoid feedback between the power loop and the control loop.

The control signal CNT may switch the power transistor Q<NUM> between a blocking mode of operation and a conduction mode of operation. In the blocking mode of operation, the power transistor Q<NUM> is turned off such that minimal current flows from the first power switching node PS<NUM> and the second power switching node PS<NUM>. Current may still flow from the second power switching node PS<NUM> to the first power switching node PS<NUM> through the freewheeling diode Dfw. In the conduction mode of operation, the power transistor Q<NUM> may be turned on such that current flows between the first power switching node PS<NUM> and the second power switching node PS<NUM>. The conduction mode of operation may include a first quadrant mode of operation in which current flows from the first power switching node PS<NUM> to the second power switching node PS<NUM> and a third quadrant mode of operation in which current flows in the opposite direction from the second power switching node PS<NUM> to the first power switching node PS<NUM>. The control signal CNT may thus be grounded or provided as a negative voltage (with reference to the supply voltage VSUPP) to switch the power transistor Q<NUM> into the blocking mode of operation and as a positive voltage above a threshold voltage of the power transistor Q<NUM> (e.g., 15V) to switch the power transistor Q<NUM> into a conduction mode of operation. However, these values are merely exemplary and will be different based on the specifications of the power transistor Q<NUM> (e.g., enhancement mode vs. depletion mode, threshold voltage, etc.).

While the conventional gate drive system <NUM> may effectively drive the power transistor Q<NUM> to selectively deliver power to a load, it does not provide any protection for the power transistor Q<NUM> against overcurrent events. Accordingly, should an overcurrent event occur, the power transistor Q<NUM> will fail after an overcurrent withstand time, which may be quite short, especially if the power transistor Q<NUM> has a small die area, which is often the case with wide bandgap semiconductor devices.

<FIG> shows a gate drive system <NUM> according to one embodiment of the present disclosure. The gate drive system <NUM> includes gate drive circuitry <NUM> configured to drive a power transistor Q<NUM> to selectively deliver power to a load (not shown). The gate drive system <NUM> shown in <FIG> is substantially similar to that shown in <FIG>, but further includes a feedback switching element SWfb coupled between the Kelvin connection node K and the second power switching node PS<NUM>. Further, the gate drive system <NUM> includes switching control circuitry <NUM>, which is shown included in the gate drive circuitry <NUM> but could also be external to the gate drive circuitry <NUM>. The switching control circuitry <NUM> is configured to selectively couple the Kelvin connection node K to the second power switching node PS<NUM>. In particular, after the control signal CNT is provided to switch the power transistor Q<NUM> from the blocking mode of operation to the conduction mode of operation, the switching control circuitry <NUM> is configured to couple the Kelvin connection node to the second power switching node PS<NUM>, and before the control signal CNT is provided to switch the power transistor Q<NUM> from the conduction mode of operation to the blocking mode of operation, the switching control circuitry <NUM> is configured to isolate the Kelvin connection node K from the second power switching node PS<NUM>.

When the Kelvin connection node K is isolated from the second power switching node PS<NUM>, the voltage between the control node C and the Kelvin connection node K Vc-k is provided according to Equation (<NUM>): <MAT> where Vcnt is the voltage provided by the gate drive circuitry <NUM> at the control node C. When the Kelvin connection node K is coupled to the second power switching node PS<NUM>, the voltage between the control node C and the Kelvin connection node K Vc-k is provided according to Equation (<NUM>): <MAT> where Vls is a voltage across the stray inductance of the connection from the second power switching node PS<NUM> and the power transistor Q<NUM>. Notably, Equation (<NUM>) is essentially the same voltage response that occurs when a power transistor without a Kelvin connection is used. The inductance of the connection from the second power switching node PS<NUM> to the power transistor Q<NUM> is directly in the power switching path of the power transistor Q<NUM>, and thus a significant voltage is formed across this inductance. This provides a feedback mechanism between the power loop and the control loop.

In the first quadrant mode of operation, the voltage formed across the stray inductance is positive and reduces the voltage between the control node C and the Kelvin connection node K Vc-k such that the power transistor Q<NUM> is partially turned off. During normal operation of the power transistor Q<NUM>, the voltage across the stray inductance is minimal and thus does not interfere with the operation thereof. During an overcurrent event, a voltage across the stray inductance is much larger and thus will significantly reduce the voltage between the control node C and the Kelvin connection node K Vc-k such that an overcurrent withstand time of the power transistor Q<NUM> is significantly extended. In the third quadrant mode of operation, the voltage formed across the stray inductance is negative and thus increases the voltage between the control node C and the Kelvin connection node K Vc-k such that the power transistor Q<NUM> is turned partially on or kept on. This will cause current to flow not only through the freewheeling diode Dfw but also through the channel of the power transistor Q<NUM>. This increases the current carrying capacity of the power transistor Q<NUM> in the reverse direction and thus increases the overcurrent withstand time. In short, during an overcurrent event during the first quadrant mode of operation, the feedback switching element SWfb, when operated as described above, reduces the amount of current flowing through the power transistor Q<NUM> and thus increases the overcurrent withstand time thereof. During an overcurrent event in the third quadrant of operation, the feedback switching element SWfb, when operated as described above, increases the I<NUM>t or amperes squared per second of the freewheeling diode Dfw (i.e., the current carrying capacity) and thus increases the overcurrent withstand time thereof.

The above benefits of increasing the overcurrent withstand time of the power transistor Q<NUM> are achieved without sacrificing the performance of the power transistor Q<NUM> with respect to switching time. This is because the switching control circuitry <NUM> is configured to isolate the Kelvin connection node K from the second power switching node PS<NUM> after the control signal CNT is provided to switch the power transistor Q<NUM> from the blocking mode of operation to the conduction mode of operation and before the control signal CNT is provided to switch the power transistor Q<NUM> from the conduction mode of operation to the blocking mode of operation. Accordingly, the feedback discussed above provided by the stray inductance between the second power switching node PS<NUM> and the power transistor Q<NUM> does not affect the control loop during turn on and turn off of the power transistor Q<NUM>, and therefore does not reduce a switching time thereof. Accordingly, the gate drive system <NUM> provides overcurrent protection while maintaining the switching performance of the power transistor Q<NUM>.

The feedback switching element SWfb may be any suitable switching element such as a MOSFET, IGBT, junction field-effect transistor (JFET), or the like. The switching control circuitry <NUM> may be any suitable circuitry for accomplishing the tasks discussed herein, and as discussed above may be a part of the gate drive circuitry <NUM> or separate from the gate drive circuitry <NUM>.

<FIG> shows the gate drive system <NUM> according to an additional embodiment of the present disclosure. The gate drive system <NUM> shown in <FIG> is substantially similar to that shown in <FIG>, but further includes a sense resistor Rs coupled between the Kelvin connection node K and an intermediate node IN, an additional sense resistor Rsa coupled between the intermediate node IN and a control return node Cr, and sense circuitry <NUM> coupled to the Kelvin connection node K. The sense circuitry <NUM> is configured to measure a voltage across the sense resistor Rs and the additional sense resistor Rsa to detect an overcurrent event. As discussed above, the feedback switching element SWfb is closed when the power transistor Q<NUM> is operating in a conduction mode of operation. Accordingly, a current proportional to the current in the power loop of the power transistor Q<NUM> will flow through the sense resistor Rs and create a sense voltage across the sense resistor Rs. Notably, this current will be much smaller than the one flowing through the power loop. Accordingly, the sense resistor Rs does not have to be extremely tolerant of high voltages and/or currents or power dissipation. The additional sense resistor Rsa is provided to ensure that current does not flow from intermediate node IN to the gate drive circuitry <NUM> and vice versa. Accordingly, a resistance of the additional sense resistor Rsa may be significantly higher than that of the sense resistor (e.g., one, two, three or more orders of magnitude higher). Conventionally, measuring a current through the power loop has required a resistive element in the power loop (e.g., coupled to the second power switching node PS<NUM>). Due to the high currents that flow in the power loop, such a resistive element has to be extremely tolerant to high power, and thus is expensive or impractical to implement. The feedback switching element SWfb, when operated as described above, provides a parallel current path with a current that is proportional to the power loop without being nearly as high. Accordingly, current in the power path can be measured using normal resistors. This enables the fast detection of overcurrent events, thus enabling further protection mechanisms to be implemented. The sense circuitry <NUM> may be configured to detect an overcurrent event based on a magnitude of a voltage across the sense resistor Rs. For example, when a voltage across the sense resistor Rs is above a threshold value, the sense circuitry <NUM> may detect an overcurrent event.

While the sense circuitry <NUM> is shown included in the gate drive circuitry <NUM>, the sense circuitry <NUM> may also be external to the gate drive circuitry <NUM> without departing from the principles described herein. As discussed above, the purpose of the additional sense resistor Rsa is to prevent current from flowing from the gate drive circuitry <NUM> into the power loop. Accordingly, the functionality of the additional sense resistor Rsa could also be accomplished by a sense switching element SWs as shown in <FIG>. The switching control circuitry <NUM> may operate the sense switching element SWs in a complementary fashion to the feedback switching element SWfb such that when the feedback switching element SWfb is closed, the sense switching element SWs is open, and vice versa.

The sense circuitry <NUM> shown in <FIG> and <FIG> is merely exemplary. In general, the present disclosure proposes providing a parallel current path to the power loop with a much smaller current than the power loop and measuring the current in the parallel current path to detect overcurrent events. This may be accomplished in many different ways, all of which are contemplated herein. On detection of an overcurrent event, external circuitry may be provided and operated to protect the power transistor. In other embodiments, the gate drive circuitry <NUM> may change the control signal CNT based on the detection of an overcurrent event. For example, on detection of an overcurrent event when the power transistor Q<NUM> is operating in the first quadrant mode of operation, the control signal CNT may be provided to cause the power transistor Q<NUM> to partially or fully enter a blocking mode of operation. Accordingly, the current through the power transistor Q<NUM> will be significantly reduced or eliminated, thereby extending the overcurrent withstand time of the power transistor Q<NUM>, sometimes indefinitely. On detection of an overcurrent event when the power transistor Q<NUM> is operating in the third quadrant mode of operation, the control signal CNT may be provided to cause the power transistor Q<NUM> to enter a conduction mode of operation. This may enable the reverse current through the freewheeling diode Dfw to be partially or entirely shared by the power transistor Q<NUM>, thereby increasing current carrying capacity in the reverse direction and reducing power dissipation such that the overcurrent withstand time of the power transistor Q<NUM> and the freewheeling diode Dfw (and other paralleled devices that are not shown) is increased, sometimes indefinitely.

<FIG> shows the gate drive system <NUM> according to an additional embodiment of the present disclosure. The gate drive system <NUM> shown in <FIG> is substantially similar to that shown in <FIG>, but further includes a first overcurrent protection switching element SWop1, a second overcurrent protection switching element SWop2, and an overcurrent protection diode Dop. The overcurrent protection diode Dop is coupled between the intermediate node IN and an additional intermediate node INa. The first overcurrent protection switching element SWop1 is coupled between the additional intermediate node INa and the control node CNT. The second overcurrent protection switching element SWop2 is coupled between the control node CNT and a predetermined voltage Vpd. The switching control circuitry <NUM> is coupled to the first overcurrent protection switching element SWop1 and the second overcurrent protection switching element SWop2.

In operation, when an overcurrent event is detected by the sense circuitry <NUM> and the power transistor Q<NUM> is operating in the first quadrant mode of operation, the switching control circuitry <NUM> may cause the first overcurrent protection switching element SWop1 to close and the second overcurrent protection switching element SWop2 to open, thus coupling the intermediate node IN to the control node CNT via the overcurrent protection diode Dop. This effectively clamps the voltage between the control node C and the Kelvin connection node K Vc-k and partially or fully turns off the power transistor Q<NUM>. This significantly reduces the amount of current flowing through the power transistor Q<NUM> and thus further increases the overcurrent withstand time, sometimes indefinitely.

When an overcurrent event is detected by the sense circuitry <NUM> and the power transistor Q<NUM> is operating in the third quadrant mode of operation, the switching control circuitry <NUM> may cause the first overcurrent protection switching element SWop1 to open and the second overcurrent protection switching element SWop2 to close, thus coupling the control node CNT to the predetermined voltage Vpd. The predetermined voltage Vpd may be configured to ensure that the power transistor Q<NUM> is in a conduction mode of operation such that current can be conducted through a channel thereof. Accordingly, a current from the second power switching node PS<NUM> to the first power switching node PS<NUM> can flow through both the freewheeling diode Dfw and the channel of the power transistor Q<NUM>. This effectively increases the current carrying capacity of the power transistor Q<NUM> and the freewheeling diode Dfw from the second power switching node PS<NUM> to the first power switching node PS<NUM>, reducing power dissipation and thus extending the overcurrent withstand time, sometimes indefinitely.

While the principles of the present disclosure are discussed above with respect to a MOSFET, the power transistor Q<NUM> may be any suitable type of power transistor such as an insulated gate bipolar transistor (IGBT). Specifically, the power transistor Q<NUM> may be a reverse conducting IGBT (RC-IGBT). <FIG> shows the gate drive system <NUM> wherein the power transistor Q<NUM> is an IGBT. The gate drive system <NUM> is substantially similar to that shown in <FIG>. While not shown, the power transistor Q<NUM> includes a semiconductor structure between the control node, the first power switching node PS<NUM>, the second power switching node PS<NUM>, and the Kelvin connection node K such that a control signal CNT provided between the control node C and the Kelvin connection node K varies a resistance between the first power switching node PS<NUM> and the second power switching node PS<NUM>. The control node C is coupled to a gate region in the semiconductor structure, the first power switching node PS<NUM> is coupled to a collector region and a cathode region in the semiconductor structure, and the second power switching node PS<NUM> and the Kelvin connection node are coupled to an emitter region and an anode region in the semiconductor structure.

The various embodiments of the gate drive system <NUM> herein are merely exemplary. Any number of different systems can be used to carry out the principles described herein. <FIG> is a flow diagram illustrating a method for providing overcurrent protection for a power transistor according to one embodiment of the present disclosure. First, a control signal is provided between a control node and a Kelvin connection node of a power transistor (step <NUM>). As discussed above, a resistance between a first power switching node and a second power switching node of the power transistor is based on the control signal. Next, the Kelvin connection node is coupled to the second power switching node after the control signal is provided such that the power transistor is switched from a blocking mode of operation to a conduction mode of operation (step <NUM>). Before providing the control signal such that the power transistor is switched from the conduction mode of operation to the blocking mode of operation, the Kelvin connection node is isolated from the second power switching node (step <NUM>). As discussed above, coupling the Kelvin connection node to the second power switching node introduces feedback between the control loop and the power loop that partially turns off the power transistor in the event of an overcurrent event and thus increases a short circuit withstand time of the power transistor. Isolating the Kelvin connection node from the second power switching node before switching the power transistor from the conduction mode of operation to the blocking mode of operation maintains the switching speed of the power transistor. Further as discussed above, the power transistor may be a MOSFET, an IGBT, or any other suitable power transistor. The conduction mode of operation may include a first quadrant mode of operation or a third quadrant mode of operation. In some embodiments, the conduction mode may include a second quadrant mode of operation or a fourth quadrant mode of operation. In one embodiment, the Kelvin connection node is coupled to the second power switching node at least <NUM> picoseconds after the control signal is provided such that the power transistor is switched from the blocking mode to the conduction mode. Generally, the Kelvin connection node may be coupled to the second power switching mode anywhere between <NUM> picoseconds and <NUM> microseconds after the control signal is provided such that the power transistor is switched from the blocking mode to the conduction mode. Notably, these timing values are merely exemplary. In one embodiment, the Kelvin connection node is isolated from the second power switching node at least <NUM> picoseconds before the control signal is provided such that the power transistor is switched from the conduction mode to the blocking mode. Generally, the Kelvin connection node may be isolated from the second power switching node anywhere between <NUM> picoseconds and <NUM> microseconds before the control signal is provided such that the power transistor is switched from the conduction mode to the blocking mode. As stated above, these timing values are merely exemplary.

Claim 1:
Support circuitry for a power transistor (Q1), the power transistor (Q1) comprising a control node (C), a Kelvin connection node (K), a first power switching node (PS1), a second power switching node (PS2), and a semiconductor structure between the control node (C), the Kelvin connection node (K), the first power switching node (PS1), and the second power switching node (PS2) such that a resistance between the first power switching node (PS1) and the second power switching node (PS2) is based on a control signal provided between the control node (C) and the Kelvin connection node (K), the support circuitry comprising:
a feedback switching element (SWfb) coupled between the Kelvin connection node (K) and the second power switching node (PS2); and
switching control circuitry (<NUM>) coupled to the feedback switching element (SWfb), the switching control circuitry (<NUM>) configured to:
cause the feedback switching element (SWfb) to couple the Kelvin connection node (K) to the second power switching node (PS2) after the power transistor (Q1) is switched from a blocking mode of operation to a conduction mode of operation; and
cause the feedback switching element (SWfb) to isolate the Kelvin connection node (K) from the second power switching node (PS2) before the power transistor (Q1) is switched from the conduction mode of operation to the blocking mode of operation.