Patent Description:
Designing mobile radio frequency (RF) chips (e.g., mobile RF transceivers) is complicated by added circuit functions for supporting communication enhancements. Designing these mobile RF transceivers may include using semiconductor on insulator technology. Semiconductor on insulator (SOI) technology replaces conventional semiconductor (e.g., silicon) substrates with a layered semiconductor-insulator-semiconductor substrate for reducing parasitic capacitance and improving performance. SOI-based devices differ from conventional, silicon-built devices because a silicon junction is above an electrical isolator, typically a buried oxide (BOX) layer. A reduced thickness BOX layer, however, may not sufficiently reduce artificial harmonics caused by the proximity of an active device on the SOI layer and an SOI substrate supporting the BOX layer.

For example, high performance complementary metal oxide semiconductor (CMOS) radio frequency (RF) switch technologies are currently manufactured using SOI substrates. While SOI substrates may provide some protection against artificial harmonics in mobile RF transceivers, SOI substrates are very expensive. Furthermore, increasing device isolation and reducing RF loss may involve expensive handle wafers. For example, a CMOS switch device may be physically bonded to a high resistivity (HR) handle wafer, such as HR-silicon or sapphire. While the increased spatial separation of the switch device from the underlying substrate dramatically improves the RF performance of the CMOS switch, using HR-silicon or sapphire handle wafer dramatically drives up cost. That is, using SOI wafers and handle substrates is quite expensive relative to the cost of a bulk semiconductor wafer. Document <CIT> describes such a device and the corresponding method for manufacturing a radio frequency switch device that improves performance through multi sided biased shielding.

A radio frequency integrated circuit (RFIC) may include a bulk semiconductor die. The RFIC may include a first active/passive device on a first-side of the bulk semiconductor die, and a first deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die. The RFIC may also include a contact layer on the second-side of the bulk semiconductor die. The RFIC may further include a second-side dielectric layer on the contact layer. The first deep trench isolation region may extend through the contact layer and into the second-side dielectric layer.

A method of constructing a radio frequency (RF) integrated circuit may include fabricating a first transistor on a first-side of a bulk semiconductor wafer. The method may also include forming a first deep trench isolation region in the bulk semiconductor wafer, proximate the first transistor. The method may also include depositing a first-side dielectric layer on the first transistor. The method may further include bonding a handle substrate to the first-side dielectric layer. The method may also include exposing the first deep trench isolation region at a second-side of the bulk semiconductor wafer. The method may further include depositing a contact layer on the second-side of the bulk semiconductor wafer and on exposed sidewalls of the first deep trench isolation region.

A radio frequency (RF) front end module may include a wireless transceiver. The wireless transceiver may include a bulk semiconductor die including a first transistor on a first-side of the bulk semiconductor die, and a first deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die. The wireless transceiver may also include a contact layer on the second-side of the bulk semiconductor die, and a second-side dielectric layer on the contact layer. The first deep trench isolation region may extend through the contact layer and into the second-side dielectric layer. The RF front end module may also include an antenna coupled to an output of the wireless transceiver.

This has outlined, rather broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the present disclosure will be described below. It should be appreciated by those skilled in the art that this present disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the present disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

It will be apparent, however, to those skilled in the art that these concepts may be practiced without these specific details.

As described herein, the use of the term "and/or" is intended to represent an "inclusive OR", and the use of the term "or" is intended to represent an "exclusive OR". As described herein, the term "exemplary" used throughout this description means "serving as an example, instance, or illustration," and should not necessarily be construed as preferred or advantageous over other exemplary configurations. As described herein, the term "coupled" used throughout this description means "connected, whether directly or indirectly through intervening connections (e.g., a switch), electrical, mechanical, or otherwise," and is not necessarily limited to physical connections. Additionally, the connections can be such that the objects are permanently connected or releasably connected. The connections can be through switches. As described herein, the term "proximate" used throughout this description means "adjacent, very near, next to, or close to. " As described herein, the term "on" used throughout this description means "directly on" in some configurations, and "indirectly on" in other configurations.

Designing mobile radio frequency (RF) transceivers may include using semiconductor on insulator technology. Semiconductor on insulator (SOI) technology replaces conventional silicon substrates with a layered semiconductor-insulator-semiconductor substrate for reducing parasitic capacitance and improving performance. While SOI-based devices differ from conventional, silicon-built devices by including a silicon junction above an electrical isolator, typically a buried oxide (BOX) layer, SOI-based devices are more expensive than conventional, silicon-built devices. Furthermore, a reduced thickness BOX layer may not sufficiently reduce artificial harmonics caused by the proximity of an active device on an SOI layer and an SOI substrate supporting the BOX layer.

The active devices on the SOI layer may include high performance complementary metal oxide semiconductor (CMOS) transistors. For example, high performance CMOS RF switch technologies are currently manufactured using SOI substrates. A radio frequency front end (RFFE) module may rely on these high performances CMOS RF switch technologies for successful operation. A process for fabricating an RFFE module, therefore, involves the costly integration of an SOI wafer for supporting these high performances CMOS RF switch technologies. Furthermore, supporting future RF performance enhancements involves increasing device isolation while reducing RF loss.

One technique for increasing device isolation and reducing RF loss is fabricating an RFFE module using SOI wafers having trap rich regions. For example, an RF device (e.g., an RF switch device) may be fabricated using an SOI wafer having a trap rich region. Unfortunately, SOI wafers with trap rich regions cost about twice as much as regular SOI wafers. Alternatively, a layer transfer process may physically bond an RF switch device (e.g., fabricated using an SOI wafer) to a high resistivity (HR) handle wafer (e.g., such as HR-silicon or sapphire). The increased spatial separation, due to numerous layers of insulating dielectric, isolates the RF switch device from the underlying substrate, which dramatically improves the RF performance of the RF switch device. Unfortunately, using a HR handle wafer including, for example, a HR-silicon or sapphire wafer, is quite expensive relative to the cost of a bulk semiconductor wafer.

Various aspects of the present disclosure provide techniques for bulk layer transfer processing with backside silicidation. The process flow for semiconductor fabrication of the integrated RF circuit may include front-end-of-line (FEOL) processes, middle-of-line (MOL) processes, and back-end-of-line (BEOL) processes. It will be understood that the term "layer" includes film and is not to be construed as indicating a vertical or horizontal thickness unless otherwise stated. As described herein, the term "substrate" may refer to a substrate of a diced wafer or may refer to a substrate of a wafer that is not diced. Similarly, the terms chip and die may be used interchangeably.

Aspects of the present disclosure include using a bulk semiconductor (e.g., silicon) wafer for replacing SOI wafers. That is, aspects of the present disclosure employ inexpensive bulk semiconductor wafers for forming a semiconductor device layer without using an expensive SOI wafer. According to this aspect of the present disclosure, a radio frequency integrated circuit (RFIC) includes a semiconductor device layer on a front-side of a bulk semiconductor die. A deep trench isolation region may extend from the front-side to a backside opposite the front-side of the bulk semiconductor die.

A silicide layer is deposited on the backside of the bulk semiconductor die as a contact layer. In addition, the back side of the bulk semiconductor die may be supported by a backside dielectric layer (e.g., a second-side dielectric layer) distal from a front-side dielectric layer (e.g., a first-side dielectric layer) on the semiconductor device layer. The RFIC may also include a handle substrate on the front-side dielectric layer. The front-side and backside may each be referred to as a first-side or a second-side. In some cases, the front-side will be referred to as the first-side. In other cases, the backside will be referred to as the first-side.

<FIG> is a schematic diagram of a wireless device (e.g., a cellular phone or a smartphone) having a wireless local area network module and a radio frequency (RF) front end module for a chipset. The wireless device <NUM> may include a wireless local area network (WLAN) (e.g., WiFi) module <NUM> and an RF front end module <NUM> for a chipset <NUM>, which may be fabricated using a bulk semiconductor die, according to aspects of the present disclosure. The WiFi module <NUM> includes a first diplexer <NUM> communicably coupling an antenna <NUM> to a wireless local area network module (e.g., WLAN module <NUM>). The RF front end module <NUM> includes a second diplexer <NUM> communicably coupling an antenna <NUM> to the wireless transceiver <NUM> (WTR) through a duplexer <NUM> (DUP).

The wireless transceiver <NUM> and the WLAN module <NUM> of the WiFi module <NUM> are coupled to a modem (MSM, e.g., a baseband modem) <NUM> that is powered by a power supply <NUM> through a power management integrated circuit (PMIC) <NUM>. The chipset <NUM> also includes capacitors <NUM> and <NUM>, as well as an inductor(s) <NUM> to provide signal integrity. The PMIC <NUM>, the modem <NUM>, the wireless transceiver <NUM>, and the WLAN module <NUM> each include capacitors (e.g., <NUM>, <NUM>, <NUM>, and <NUM>) and operate according to a clock <NUM>. The geometry and arrangement of the various inductor and capacitor components in the chipset <NUM> may reduce the electromagnetic coupling between the components.

The wireless transceiver <NUM> of the wireless device <NUM> generally includes a mobile RF transceiver to transmit and receive data for two-way communication. A mobile RF transceiver may include a transmit section for data transmission and a receive section for data reception. For data transmission, the transmit section may modulate an RF carrier signal with data to obtain a modulated RF signal, amplify the modulated RF signal using a power amplifier (PA) to obtain an amplified RF signal having the proper output power level, and transmit the amplified RF signal via the antenna <NUM> to a base station. For data reception, the receive section may obtain a received RF signal via the antenna <NUM> and may amplify the received RF signal using a low noise amplifier (LNA) and process the received RF signal to recover data sent by the base station in a communication signal.

The wireless transceiver <NUM> may include one or more circuits for amplifying these communication signals. The amplifier circuits (e.g., LNA/PA) may include one or more amplifier stages that may have one or more driver stages and one or more amplifier output stages. Each of the amplifier stages includes one or more transistors configured in various ways to amplify the communication signals. Various options exist for fabricating the transistors that are configured to amplify the communication signals transmitted and received by the wireless transceiver <NUM>.

The wireless transceiver <NUM> and the RF front end module <NUM> may be implemented using a layer transfer process to separate the active device from a substrate as shown in <FIG>.

<FIG> shows a cross-sectional view of a radio frequency (RF) integrated circuit <NUM>, including an RF semiconductor on insulator (SOI) device, which may be fabricated using a layer transfer process. As shown in <FIG>, an RF device includes an active device <NUM> on an insulator layer <NUM>, which is initially supported by a sacrificial substrate <NUM>. The RF device also includes interconnects <NUM> coupled to the active device <NUM> within a first dielectric layer <NUM>. In the layer transfer process, a handle substrate <NUM> is bonded to the first dielectric layer <NUM> of the RF device for enabling removal of the sacrificial substrate <NUM>. Removal of the sacrificial substrate <NUM> using the layer transfer process enables high-performance, low-parasitic RF devices by increasing the dielectric thickness of, for example, the first dielectric layer <NUM>. That is, a parasitic capacitance of the RF device is proportional to the dielectric thickness, which determines the distance between the active device <NUM> and the handle substrate <NUM>.

The active device <NUM> on the BOX layer <NUM> may be a complementary metal oxide semiconductor (CMOS) transistor. The RFFE module <NUM> (<FIG>) may rely on these high performance CMOS RF technologies for successful operation.

<FIG> is a cross-sectional view of a radio frequency integrated circuit (RFIC) fabricated using a bulk semiconductor layer transfer process according to aspects of the present disclosure. Representatively, an RF integrated circuit <NUM> includes an active device <NUM> having a gate, source/drain (S/D) regions, and a channel region between the source/drain regions, each formed on a front-side of a bulk semiconductor wafer <NUM>. In contrast to SOI implementations, an active device layer including the source/drain and channel regions is not supported by a buried oxide (BOX) layer. Although shown as an active device, it should be recognized that the active device <NUM> may be a first active/passive device, as well as a second active/passive device.

The RF integrated circuit <NUM> also includes middle-of-line (MOL)/back-end-of-line (BEOL) interconnects coupled to the source/drain regions of the active device <NUM>. As described, the MOL/BEOL layers may be referred to as first-side (e.g., front-side) layers. By contrast, the layers supporting the bulk semiconductor wafer <NUM> may be referred to as second-side (e.g., backside) layers. In this example, a front-side metallization layer M1 is coupled to the source/drain regions of the active device <NUM> and arranged in a front-side dielectric layer <NUM>. In addition, a handle substrate <NUM> is coupled to the front-side dielectric layer <NUM>. A backside dielectric <NUM> is adjacent to and possibly supports the bulk semiconductor wafer <NUM>. In addition, a backside metallization layer (e.g., a second-side metallization layer) is coupled to the front-side metallization layer M1 with a trench interconnect <NUM> through a deep trench isolation (DTI) region <NUM> extending from the front-side to the backside of the bulk semiconductor wafer <NUM>, as further illustrated in <FIG>.

<FIG> is a cross-sectional view of a radio frequency integrated circuit (RFIC) having a bulk semiconductor die including a contact layer on a backside of the bulk semiconductor die, according to aspects of the present disclosure. Representatively, an RF integrated circuit <NUM> includes a first active device <NUM>, a second active device <NUM>, and a third active device <NUM>, each having a gate (G), source/drain (S/D) regions, and a channel (C) region between the source/drain regions, each formed on a front-side of a bulk semiconductor wafer <NUM> (e.g., a bulk silicon wafer). In contrast to SOI implementations, an active device layer including the source/drain and channel regions of the active devices (e.g., <NUM>, <NUM>, and <NUM>) is not supported by a buried oxide (BOX) layer.

Although shown as a first active device, it should be recognized that the first active device <NUM> may be a first active/passive device, as well as a second active/passive device, such as the second active device <NUM>. In addition, although shown as planar devices, it should be recognized that the active devices (e.g., <NUM>, <NUM>, and <NUM>) are not limited to planar devices. For example, the active devices s (e.g., <NUM>, <NUM>, and <NUM>) may include, but are not limited to, planar field effect transistors (FETs), fin-type FETs (FinFETs), nanowire FETs, or other like FETs.

The RF integrated circuit <NUM> also includes MOL interconnects (M0) as well as BEOL interconnects (M1) coupled to the gate as well as the source/drain regions of the active devices (e.g., <NUM>, <NUM>, and <NUM>). The MOL interconnects may include trench interconnects (e.g., CA, CB) and vias (e.g., V0) for coupling active devices formed during a front-end-of-line to metallization layers formed during the back-end-of-line processing. In this example, an MOL interconnect M0 is coupled to a gate contact (e.g., a poly contact) of the gate of the first active device <NUM> and arranged in a front-side dielectric layer <NUM>. In addition, a handle wafer <NUM> (handle substrate) is coupled to the front-side dielectric layer <NUM>. A backside dielectric layer <NUM> is adjacent to and possibly supports the bulk semiconductor wafer <NUM>.

In this configuration, a backside metallization layer (e.g., a second-side metallization layer) is coupled to the front-side MOL zero interconnect M0 through a trench interconnect <NUM>. The trench interconnect <NUM> extends through a first deep trench isolation (DTI) region <NUM>, from the front-side to the backside of the bulk semiconductor wafer <NUM>. The backside metallization may also be coupled to a backside contact layer <NUM>.

According to aspects of the present disclosure, the first DTI region <NUM> extends though the backside contact layer <NUM> and into the backside dielectric layer <NUM>. Similarly, a second deep trench isolation (DTI) region <NUM> extends though the backside contact layer <NUM> and into the backside dielectric layer <NUM>. In this example, the backside contact layer <NUM> is deposited along the backside of the bulk semiconductor wafer <NUM>. The backside contact layer <NUM> may be composed of a silicide material or other like conductive material. The backside contact layer <NUM> also contacts a portion of the first DTI region <NUM> that extends from the backside of the bulk semiconductor wafer <NUM>. In addition, the backside dielectric layer <NUM> contacts the remaining portion of the first DTI region <NUM> that extends from the backside of the bulk semiconductor wafer <NUM>.

The layer transfer process shown in <FIG> may be used with bulk semiconductor wafers to create CMOS products (e.g., a CMOS transistor) without using expensive SOI substrates, as shown in <FIG>. Various aspects of the present disclosure provide techniques for bulk layer transfer processing with backside silicidation, as described in <FIG>. One aspect of the present disclosure uses a bulk layer transfer process with backside silicidation (<FIG>) to form an RF integrated circuit, for example, as shown in <FIG>.

<FIG> illustrate a process for fabricating the RF integrated circuit <NUM> of <FIG>, according to aspects of the present disclosure. <FIG> illustrates an initial step for forming the RF integrated circuit <NUM> of <FIG>. This process may begin with a complementary metal oxide semiconductor (CMOS) wafer, such as a bulk silicon wafer. Next, CMOS front-end-of-line integration is performed on the bulk semiconductor wafer <NUM> to form the first active device <NUM>, the second active device <NUM>, and the third active device <NUM>. In this example, the first active device <NUM> and the second active device <NUM> are separated by a shallow trench isolation (STI) region. By contrast, the second active device <NUM> and the third active device <NUM> are separated by the second DTI region <NUM>. It should be recognized that the first active device <NUM> and the second active device <NUM> by be separated by a DTI region to simplify the fabrication process of the RF integrated circuit <NUM>.

According to aspects of the present disclosure, STI regions are used for active device separation, whereas the DTI regions are used for post layer transfer separation. A depth of the first DTI region <NUM> and the second DTI region <NUM> may be in the range of <NUM> to <NUM> micrometers, although the depth of the first DTI region <NUM> and the second DTI region <NUM> may be reduced for future processes. The DTI regions as well as the STI regions may be filed with a similar dielectric material, such as silicon dioxide (SiO<NUM>) and formed prior to the active devices.

Once the active devices are formed, MOL processes connect the active devices to BEOL interconnect layers. In this example, a zero-layer interconnect M0 is coupled to the gate G of the first active device <NUM>. In addition, a first BEOL interconnect M1 is coupled to the zero-layer interconnect M0. The first BEOL interconnect M1 is formed as part of a front-side BEOL process. This process is followed by depositing the front-side dielectric layer <NUM>. Once the front-side dielectric layer <NUM> is deposited, the handle wafer <NUM> is bonded to the front-side dielectric layer <NUM>. The handle wafer <NUM> can be a processed wafer or a bare wafer.

<FIG> illustrates a backgrind process of the bulk semiconductor wafer <NUM>. This initial backgrind process is applied to the backside of the bulk semiconductor wafer <NUM>, distal from the active device layer. This initial backgrind process may leave a surface variation of about <NUM> to <NUM> micrometers. The backgrind process continues in <FIG>, in which a chemical mechanical polish (CMP) process is applied to the backside of the bulk semiconductor wafer <NUM>. This CMP process may reduce the surface variation of the backside of the bulk semiconductor wafer <NUM> to a range of <NUM> micrometers to <NUM> micrometers, but preferably to <NUM> micrometers. This CMP process does not expose the first DTI region <NUM> or the second DTI region <NUM>.

As shown in <FIG>, the backgrind process may be applied to the backside of the bulk semiconductor wafer <NUM> with a surface variation of <NUM>-<NUM> microns. The surface variation may be reduced by polishing the backside of the bulk semiconductor wafer <NUM> to a predetermined surface variation (e.g., less than <NUM> microns), as shown in <FIG>. In addition, a silicon etch (e.g., potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH)), a CMP (chemical mechanical polish), or combination of CMP and etching may be performed to reduce a thickness of the bulk semiconductor wafer to a thickness equal to or less than a thickness of the DTI regions.

As shown in <FIG>, the silicon etch/CMP is performed on the backside of the bulk semiconductor wafer <NUM> for exposing a portion of the first DTI region <NUM> as well as the second DTI region <NUM>. In a further aspect of the present disclosure, an etch stop layer may be formed in the bulk semiconductor wafer <NUM> for improving a planarity of the backside of the bulk semiconductor wafer <NUM>. Once the first DTI region <NUM> and the second DTI region <NUM> are exposed, a post-layer transfer silicide layer is deposited on an entire length of the backside of the bulk semiconductor wafer <NUM> for forming the backside contact layer <NUM>, which is further described in <FIG>.

As shown in <FIG> a trench interconnect <NUM> is formed through the first DTI region <NUM>. In this example, the trench interconnect <NUM> is coupled to the front-side zero interconnect M0 in the front-side dielectric layer <NUM>. As shown in <FIG>, the RF integrated circuit <NUM> is completed by forming a backside BEOL interconnect <NUM> and depositing the backside dielectric layer <NUM>. The backside dielectric layer <NUM> is deposited on the backside of the bulk semiconductor wafer <NUM> and exposed sidewalls of the first DTI region <NUM> that extend from the backside of the bulk semiconductor wafer <NUM>. In this example, the backside dielectric layer <NUM> is distal from the front-side dielectric layer <NUM>. In this example, the backside BEOL interconnect <NUM> is coupled to the front-side zero interconnect M0 through the trench interconnect <NUM>.

<FIG> is a process flow diagram illustrating a method <NUM> of a bulk layer transfer process with second-side (e.g., backside) silicidation for constructing a radio frequency integrated circuit (RFIC) according to an aspect of the present disclosure. In block <NUM>, a first transistor is fabricated on a first-side of a bulk semiconductor wafer. For example, as shown in <FIG>, a first active device <NUM> is fabricated on a first-side of a bulk semiconductor wafer <NUM>. In block <NUM>, a first deep trench isolation region is formed in the bulk semiconductor wafer, proximate the first transistor. For example, as shown in <FIG>, the first DTI region <NUM> extends from the first-side to the second-side of the bulk semiconductor wafer <NUM>.

The method <NUM> may further include fabricating a second transistor on the first-side of the bulk semiconductor wafer. For example, as shown in <FIG>, a second active device <NUM> is fabricated adjacent to the first active device <NUM>. An STI region may be formed on the first-side of the bulk semiconductor wafer <NUM>, between the first active device <NUM> and the second active device <NUM>, prior to forming the active devices. Next, a second DTI region <NUM> may be formed, extending from the first-side to the second-side of the bulk semiconductor wafer <NUM>, proximate the second active device <NUM>. For example, as shown <FIG>, the second DTI region <NUM> is formed between the second active device <NUM> and the third active device <NUM>.

Referring again to <FIG>, in block <NUM>, a first-side dielectric layer is deposited on the first transistor. For example, as shown in <FIG>, the front-side dielectric layer <NUM> is deposited on the first active device <NUM>. Referring again to <FIG>, in block <NUM>, a handle substrate is bonded to the first-side dielectric layer. For example, as shown in <FIG>, the handle wafer <NUM> is bonded to the front-side dielectric layer <NUM>. In block <NUM>, the first deep trench isolation region is exposed at a second-side of the bulk semiconductor wafer.

For example, as shown in <FIG>, the first DTI region <NUM> is exposed at a second-side of the bulk semiconductor wafer <NUM>. The exposure of the first DTI region <NUM> may be performed by backgrinding the second-side of the bulk semiconductor wafer and polishing the second-side of the bulk semiconductor wafer to a predetermined surface variation. Referring again to <FIG>, In block <NUM>, a contact layer is deposited on the second-side of the bulk semiconductor wafer and on exposed sidewalls of the first deep trench isolation region. For example, as shown in <FIG>, the backside contact layer <NUM> is deposited on the backside of the bulk semiconductor wafer <NUM> using a backside silicide process.

Aspects of the present disclosure relate to using a bulk semiconductor (e.g., silicon) wafer for replacing SOI wafers. That is, aspects of the present disclosure employ inexpensive semiconductor wafers for forming a semiconductor device layer without the use of an expensive SOI wafer. One aspect of the present disclosure uses a backside silicidation process with layer transfer to form a bulk semiconductor wafer including an active device layer on a first-side and a contact layer on a second-side of the bulk semiconductor wafer. In addition, a post-layer transfer metallization process enables the formation of a second-side metallization coupled to a first-side metallization with a trench interconnect extending through a deep trench isolation region in the bulk semiconductor wafer.

According to a further aspect of the present disclosure, an RF integrated circuit, including a bulk semiconductor die having an active/passive device on a first-side and a deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die, is described. The RF integrated circuit includes a first-side dielectric layer on the active/passive device. The RF integrated circuit structure also includes means for handling the RF integrated circuit on the first-side dielectric layer. The handling means may be the handle wafer, shown in <FIG>. In another aspect of the present disclosure, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

<FIG> is a block diagram showing an exemplary wireless communication system <NUM> in which an aspect of the present disclosure may be advantageously employed. For purposes of illustration, <FIG> shows three remote units <NUM>, <NUM>, and <NUM> and two base stations <NUM>. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units <NUM>, <NUM>, and <NUM> include IC devices 725A, 725C, and 725B that include the disclosed RFIC. It will be recognized that other devices may also include the disclosed RFIC, such as the base stations, switching devices, and network equipment. <FIG> shows forward link signals <NUM> from the base station <NUM> to the remote units <NUM>, <NUM>, and <NUM> and reverse link signals <NUM> from the remote units <NUM>, <NUM>, and <NUM> to base stations <NUM>.

In <FIG>, remote unit <NUM> is shown as a mobile telephone, remote unit <NUM> is shown as a portable computer, and remote unit <NUM> is shown as a fixed location remote unit in a wireless local loop system. For example, a remote unit may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit such as a personal digital assistant (PDA), a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit such as a meter reading equipment, or other communications device that stores or retrieves data or computer instructions, or combinations thereof. Although <FIG> illustrates remote units according to the aspects of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Aspects of the present disclosure may be suitably employed in many devices, which include the disclosed RFIC.

<FIG> is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the RF devices disclosed above. A design workstation <NUM> includes a hard disk <NUM> containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation <NUM> also includes a display <NUM> to facilitate a circuit design <NUM> or an RFIC design <NUM>. A storage medium <NUM> is provided for tangibly storing the circuit design <NUM> or the RFIC design <NUM>. The circuit design <NUM> or the RFIC design <NUM> may be stored on the storage medium <NUM> in a file format such as GDSII or GERBER. The storage medium <NUM> may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation <NUM> includes a drive apparatus <NUM> for accepting input from or writing output to the storage medium <NUM>.

Data recorded on the storage medium <NUM> may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium <NUM> facilitates the design of the circuit design <NUM> or the RFIC design <NUM> by decreasing the number of processes for designing semiconductor wafers.

For a firmware and/or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. A machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein. For example, software codes may be stored in a memory and executed by a processor unit. Memory may be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" refers to types of long term, short term, volatile, nonvolatile, or other memory and is not to be limited to a particular type of memory or number of memories, or type of media upon which memory is stored.

If implemented in firmware and/or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be an available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

In addition to storage on computer readable medium, instructions and/or data may be provided as signals on transmission media included in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

Claim 1:
A radio frequency integrated circuit, RFIC, comprising:
a bulk semiconductor die comprising a first active/passive device on a first-side of the bulk semiconductor die, a first deep trench isolation region (<NUM>) extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die;
a contact layer (<NUM>) on the second-side of the bulk semiconductor die; and
a second-side dielectric layer (<NUM>) on the contact layer, in which the first deep trench isolation region extends through the contact layer and into the second-side dielectric layer;
in which the contact layer (<NUM>) comprises a silicide layer on an entire length of the second-side of the bulk semiconductor die.