Patent Description:
Integrated circuits with a large number of external connections or "pins" are often limited in their ability to be assembled into small packages with traditional wire bonding techniques. The sizes of these packages are deemed to be pin-limited rather than die-size limited. Accordingly, FC assemblies are often used for high Input/Output (I/O) IC devices. FC assemblies enable a high density of joints (e.g., solder joints), with low pitch distances. System on Chip (SoC) devices integrate additional functionality, thereby increasing the need to provide more I/O on the IC. One approach to increasing package I/O density is to reduce the diameter of a pillar connecting a semiconductor IC to the package substrate, however this approach is to the detriment of signal quality and/or current capacity. <CIT> discloses a semiconductor package that includes a package substrate and a semiconductor chip mounted on the package substrate. The package substrate includes a signal bump land and an anchoring bump land, and the semiconductor chip includes a signal bump and an anchoring bump. The signal bump is bonded to the signal bump land and the anchoring bump is disposed to be adjacent to the anchoring bump land, and a bottom surface of the anchoring bump is located at a level which is lower than a top surface of the anchoring bump land with respect to a surface of the package substrate. <CIT> a discloses flip chip package that includes a chip having a surface, main bumps disposed on a first region of the surface of the chip, dummy bumps disposed on a second region of the surface of the chip, a substrate having a surface, dams disposed on the surface of the substrate, connection pads disposed on the surface of the substrate and electrically connected to respective ones of the main bumps, and adhesion patterns attaching the dummy bumps to respective ones of the dams.

According to the invention there is provided an apparatus as defined by the appended claims.

Embodiments described herein provide for improvements in pin limited FC package density by using different pillar designs dependent upon electrical signal categories. Pillars having a small cross-sectional area support less solder volume than pillars with a larger cross-sectional area. Throughout this disclosure, references to low solder volume pillars and high solder volume pillars refer to pillars with different cross-sectional areas having correspondingly different capacities to support a volume of solder. In various embodiments, the solder is used in attachment points between the pillars and a substrate, to which the pillars are subsequently attached. High solder volume pillars are used for signals requiring high current density or having high signal frequencies, while low solder volume pillars are used for signals having lower current density or lower signal frequencies. The low solder volume pillars are smaller than the high solder volume pillars, thus improving package density. Specifically, in one embodiment, cylindrical pillars are used for high solder volume connections between the semiconductor and package substrate, while rectangular pillars are used for signals that can tolerate a lower solder volume. One or more rectangular pillars are disposed around a shorter cylindrical pillar. The cylindrical pillar is soldered to a matching assembly substrate through a vertical connection, orthogonal to a surface of the semiconductor, while the one or more rectangular pillars are connected horizontally to the assembly substrate, or parallel to the surface of the semiconductor.

<FIG> shows a perspective view of an example embodiment <NUM> of an IC, modified for a space efficient FC joint design. A substrate <NUM>, such as a printed circuit board, a semiconductor substrate or an IC, is subsequently processed to include a first pillar <NUM>. In one embodiment, the first pillar <NUM> has a cylindrical shape with a circular cross-sectional end attached to the substrate <NUM>. The example embodiment <NUM> further includes second pillars 16a, 16b, 16c and 16d (generally <NUM>) surrounding the first pillar <NUM> and being taller than the first pillar <NUM>. In one example embodiment, the second pillars <NUM> each have a rectangular shape with a rectangular cross-sectional end attached to the substrate <NUM>. In other embodiments, the number of second pillars <NUM> surrounding the first pillar <NUM> is <NUM>, <NUM>, <NUM>, <NUM> or <NUM>. In another embodiment, the number of second pillars <NUM> surrounding the first pillar <NUM> is any even or odd number up to a practical manufacturing limit defined by the cross-sectional areas of the first pillar <NUM> and the second pillar <NUM>. For example, a larger first pillar <NUM> will accommodate more second pillars <NUM>. In one embodiment, the second pillars <NUM> are symmetrically disposed around the first pillar <NUM>. In other example embodiments the first pillar <NUM> and the second pillars <NUM> have shapes that differ from cylindrical and rectangular respectively, limited by the ability to efficiently surround the first pillar <NUM> with the second pillars <NUM> and to match the pillar structures to a corresponding assembly substrate. Similarly, in one embodiment, the second pillars <NUM> surrounding a first pillar <NUM> is a combination of alternative shapes and/or cross-sections.

In the example embodiment <NUM>, the substrate <NUM> includes the combination of the first pillar <NUM> and second pillars <NUM> as well as additional third pillars 18a to 18f(generally <NUM> or "tall cylindrical pillars"). In example embodiments, the signals generated or received at the substrate <NUM> are assigned to pillars based on requirements of current density or frequency characteristics (e.g., average or peak frequency components). In one example, a high frequency and/or high current signal will be electrically coupled to either the first pillar <NUM> or one of the third pillars <NUM>, while a lower frequency and/or lower current density signal will use the more compact - lower solder volume second pillars <NUM>. In one embodiment, the formation of a group of signals defined by a first pillar <NUM> surrounded by one or more second pillars <NUM> is replicated uniformly across the substrate <NUM>. In another embodiment, the formation of a group of signals defined by a first pillar <NUM> surrounded by one or more second pillars <NUM> is replicated only in areas of the substrate <NUM> based on signal requirements.

<FIG> shows a side view of an example embodiment <NUM> similar to the embodiment <NUM> of <FIG>. In the embodiment <NUM>, each of the pillars <NUM>, <NUM> and <NUM> have "attachment points" formed by solder deposited on the tip of the respective pillar, for example by an electroplating process. Specifically, the first pillar <NUM> includes an attachment point22, each of the third pillars <NUM> include a respective attachment point 24a to 24d (generally <NUM>), and each of the second pillars <NUM> include a respective attachment point 26a, 26b (not shown), 26c and 26d (not shown), (generally <NUM>). The attachment points <NUM> and <NUM> are collinear with a central axis of the respective first pillar <NUM> and the third pillars <NUM>, and on a respective end of each pillar. Conversely, the attachment points <NUM> are on a side of the second pillars <NUM> facing the first pillar <NUM>. In the example embodiment <NUM>, the first pillar <NUM> has a diameter <NUM> being greater than the width <NUM> of each of the second pillars <NUM>. A spacing <NUM> between a pair of attachment points <NUM> is wider than the diameter <NUM> and is also defined by a matching assembly substrate to which to embodiment <NUM> is subsequently attached. The first pillar <NUM> has a first length <NUM> measured between a first end <NUM> and a second end <NUM>. The second pillars <NUM> each have a second length <NUM> measured between a third end <NUM> and a fourth end <NUM>. The third pillars <NUM> each have a third length <NUM> measured between a fifth end <NUM> and a sixth end <NUM>. In one embodiment, the third length <NUM> is the same as the second length <NUM>. During the assembly process of attaching the embodiment <NUM> to a corresponding assembly substrate, small dimensional and shape variations are accommodated by deformation and flowing of the solder tips on respective attachment points.

<FIG>, show the progressive manufacturing steps used to form the embodiment <NUM> of <FIG> or similar example embodiments of the present disclosure. In <FIG>, a substrate <NUM> includes a photoresist (PR) layer <NUM> deposited thereon. At <FIG>, the PR layer <NUM> is patterned, developed and selectively stripped to form openings <NUM>. At <FIG>, the openings <NUM> are filled with a conductive material <NUM> used to form the pillars <NUM>, <NUM> and <NUM> (e.g., Copper). At <FIG>, an additional PR layer <NUM> is deposited, spun-on or otherwise applied. At <FIG>, the PR layer <NUM> is developed and stripped to form an opening <NUM>. At <FIG>, an attachment point <NUM> (e.g., solder) fills the opening <NUM>. At <FIG>, a PR layer <NUM> is deposited and subsequently developed and stripped to form openings <NUM>. At <FIG>, additional conductive material <NUM> is added to file the openings <NUM> and thereby increase the height of resulting pillars. At <FIG>, a PR layer <NUM> is deposited and subsequently developed and stripped to form openings <NUM>. At <FIG>, attachment points <NUM> (e.g., solder) fills the openings <NUM>. At <FIG>, openings <NUM> are formed. At <FIG>, the openings <NUM> are filled with conductive material <NUM>, thereby increasing a pillar height. At <FIG>, openings <NUM> are formed in the PR. At <FIG>, the openings <NUM> are filled with solder to form attachment points <NUM>. At <FIG>, the remaining PR <NUM> of <FIG> is removed, thereby forming a structure similar to the example embodiment <NUM> of <FIG>.

<FIG> shows an example embodiment <NUM> of an assembly substrate forming a counterpart to an embodiment of a substrate with pillars, similar to that shown in <FIG>. The embodiment <NUM> includes a substrate <NUM> with substrate pads 114a, 114b, 114c, 114d and 114e (generally <NUM>). With reference to <FIG>, in one embodiment the substrate pads <NUM> of <FIG> are arranged so that a single substrate pad 114e will align with the first pillar <NUM>. The plurality of substrate pads 114a, 114b, 114c and 114d will surround the central substrate pad 114e with a distance defined by the spacing <NUM> and to align with the second pillars <NUM>. Specifically, an area outside of the region <NUM> is subsequently modified through milling, drilling or the like, so that the attachment points 26a and 26c contact the remaining portions of the respective substrate pads 114a and 114c, while the attachment point <NUM> contacts the larger substrate pad 114e. A similar process occurs for the substrate pads 114b and 114d. In alternate embodiments, having <NUM> or <NUM> second pillars <NUM>, the shape of the substrate pad 114e is correspondingly a hexagon or octagon so that that attachment points <NUM> of the second pillars <NUM> "face" the first pillar <NUM>. As shown in the example embodiment <NUM>, a second cluster of substrate pads 118a to 118e (generally <NUM>) defines a second grouping of substrate pads arranged to receive a group of a first pillar <NUM> surrounded by second pillars <NUM>. The substrate pads <NUM> also have the defined region <NUM> similar to that used for subsequent milling of the substrate pads <NUM>. In addition to the combination of first pillars <NUM> and second pillars <NUM>, one or more substrate pads 120a to 120r (generally <NUM>) are placed as required on the substrate <NUM> to align with respective third pillars <NUM>.

<FIG> shows a cross-sectional view of <FIG> taken along A-A'. The example embodiment <NUM> of <FIG> includes a bottom section <NUM> and a top section <NUM> of the substrate <NUM> of <FIG>. The bottom section <NUM> includes a plurality of routing layers <NUM> and vias <NUM> defining circuit connections. Sections <NUM> and <NUM> define areas to be removed from the top section <NUM> (e.g., the area outside of the region <NUM> shown in <FIG>). Removal of sections <NUM> and <NUM> is accomplished through a process that selectively removes the conductive material <NUM> (e.g., Copper) and insulation layers therebetween. Non-limiting examples of a process to remove the sections <NUM> and <NUM> include, but are not limited to, drilling, milling and chemical and/or ion etching.

<FIG> shows an example embodiment <NUM> of a side view of <FIG> after removal of the sections <NUM> and <NUM>. With reference to <FIG>, the substrate pads 114a and 114c (and similarly 114b and 114d) are modified with portions removed to form modified substrate pads <NUM> and <NUM> respectively. The resulting width <NUM> is designed to be the same as the spacing <NUM> between the attachment points 26a and 26c, shown in <FIG>. As previously discussed, minor manufacturing variances between the width <NUM> (<FIG>) and the spacing <NUM> (<FIG>) are readily accommodated with the conformity of the solder used on the respective attachment points 26a and 26c. <FIG> shows a perspective view of an example embodiment <NUM> after the removal of sections <NUM> and <NUM> shown in <FIG> and <FIG>. An assembly substrate <NUM> includes one or more pad blocks <NUM> combined with one or more substrate pads <NUM>.

<FIG> is an exploded view of an example embodiment <NUM> of An IC, (similar to <FIG>) aligned for attachment to an example embodiment <NUM> of an assembly substrate, (similar to <FIG>). Specifically, attachment points <NUM>, <NUM>, <NUM> and <NUM> of respective third pillars are aligned to attach to the top of respective substrate pads <NUM>, <NUM>, <NUM> and <NUM>. The attachment point <NUM> of a first pillar is aligned to attach to the top of a substrate pad <NUM>. Attachment points <NUM> and <NUM> of respective second pillars are aligned to attach to the sides of respective substrate pads <NUM> and <NUM>. In example embodiments, prior to attaching the substrate and assembly substrate, shown by embodiments <NUM> and <NUM> respectively, the solder included in each attachment point <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> is coated with flux. In various embodiments, the flux is added to the solder by spraying, pin transfer or a combination of spraying and pin transfer.

<FIG> show alternate embodiments to the example embodiment shown in <FIG>, where pad blocks <NUM> are placed at any desired location on the assembly substrate <NUM> in combination with substrate pads <NUM>. Specifically, <FIG> shows an example embodiment <NUM> of pad blocks <NUM> placed only at the periphery of the assembly substrate <NUM>. <FIG> shows an example embodiment <NUM> of pad blocks <NUM> placed selectively at the periphery and at the core of the assembly substrate <NUM>. <FIG> shows an example embodiment <NUM> of pad blocks <NUM> placed uniformly across the assembly substrate <NUM>, with no substrate pads <NUM> present. <FIG> shows an example embodiment <NUM> of pad blocks <NUM> placed only at the core of the assembly substrate <NUM>.

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as defined by the claims below.

Claim 1:
An apparatus comprising:
an Integrated Circuit (IC) and/or a semiconductor substrate (<NUM>, <NUM>, <NUM>); the apparatus further comprising:
a first pillar (<NUM>) comprising a first end (<NUM>) and a second end (<NUM>), the first end (<NUM>) connected to the IC and/or the semiconductor substrate (<NUM>, <NUM>, <NUM>), wherein the second end (<NUM>) comprises a first attachment point (<NUM>, <NUM>) collinear with a first central axis of the first pillar (<NUM>), wherein the first attachment point (<NUM>, <NUM>) comprises a first solder volume capacity;
a second pillar (16a-d) comprising a third end (<NUM>) and a fourth end (<NUM>), the third end (<NUM>) connected to the IC and/or the semiconductor substrate (<NUM>, <NUM>, <NUM>), wherein the fourth end (<NUM>) comprises
a second attachment point (26a-d, <NUM>, <NUM>) disposed on a side of the second pillar (16a-d) facing the first pillar (<NUM>), wherein the second attachment point (26a-d, <NUM>, <NUM>) comprises a second solder volume capacity being less than the first solder volume capacity, and a first distance (<NUM>) between the first end (<NUM>) and the second end (<NUM>) is less than a second distance (<NUM>) between the third end (<NUM>) and the fourth end (<NUM>), and characterized by
an assembly substrate (<NUM>, <NUM>, <NUM>) comprising a pad block (<NUM>) having a top facet and a side facet, wherein the top facet is parallel to the assembly substrate (<NUM>, <NUM>, <NUM>) and the side facet is orthogonal to the top facet, wherein the first attachment point (<NUM>, <NUM>) is connected to the top facet and the second attachment point (26a-d, <NUM>, <NUM>) is connected to the side facet.