Patent Description:
Among flat panel display devices proposed to replace the conventional cathode ray tube, an organic light-emitting diode (OLED) display has a characteristic that a light-emitting diode provided at a display panel has high brightness and a low operation voltage. Such OLED display has advantages that a contrast ratio is large because it is a spontaneous light-emission type, and a very thin display can be implemented. The OLED display can easily implement moving images because a response time is several microseconds (µs). Further, the OLED display has an unlimited viewing angle, and is stably operated even at a low temperature.

In the OLED display device, display devices are formed on a substrate such as glass. Recently, a flexible organic light-emitting diode (OLED) display device, which is capable of maintaining a display function even when rolled (or bent) like paper due to its flexible material such as plastic or metal foil rather than a non-flexible substrate, has been developed.

<FIG> is a planar view schematically illustrating a flexible organic light-emitting diode (OLED) display device in accordance with the conventional art, and <FIG> is an enlarged view of part 'A' in <FIG>.

Referring to <FIG> and <FIG>, the conventional flexible OLED display device <NUM> is formed on a flexible substrate <NUM> including an active area (A/A) and a non-active area (N/A).

The active area (A/A) is a region where an image is substantially displayed. A plurality of pixels (P) is arranged in the active area (A/A), in the form of matrices. Each of the pixels (P) includes a switching transistor (ST1), a driving transistor (DT), a sensing transistor (ST2), a capacitor (C), and an organic light-emitting diode (OLED).

The switching transistor (ST1) of the pixel (P) is connected to a gate line (GL) and a data line (DL) which are formed in the active area (A/A) so as to cross each other. The driving transistor (DT) is connected to a driving voltage line 14b for supplying a driving voltage (VDD) to the pixel (P) in the active area (A/A). The sensing transistor (ST2) is connected to a reference voltage line 14a for supplying a reference voltage (Vref) to the pixel (P) in the active area (A/A).

The non-active area (N/A) is a region formed around the active area (A/A), and is covered by a bezel portion, etc. Driving circuitry for driving the pixels (P) in the active area (A/A) and wires may be formed in the non-active area (N/A).

The driving circuitry includes a data driving portion <NUM>, a gate driving portion <NUM> and a light-emitting controller (not shown). The data driving portion <NUM> is mounted at a lower end non-active area (N/A) in the form of a chip. The gate driving portion <NUM> and the light-emitting controller are formed at one or more sides of the non-active area (N/A), in the form of a gate in panel (GIP).

Wires include power lines 14a~14c, and signal lines GSL, DSL. The power lines 14a~14c includes a driving voltage line 14a, a reference voltage line 14b and a ground line 14c. Also, the signal lines GSL, DSL include a gate signal line (GSL), a data signal line (DSL) and a light-emitting signal line (not shown).

The driving voltage line 14a outputs a driving voltage (VDD) provided from the data driving portion <NUM> to the pixel (P) in the active area (A/A). The reference voltage line 14b outputs a reference voltage (Vref) provided from the data driving portion <NUM> to the pixel (P) in the active area (A/A). The ground line 14c outputs a ground voltage (GND) provided from the data driving portion <NUM> to the pixel (P) in the active area (A/A).

The driving voltage line 14a, the reference voltage line 14b and the ground line 14c include a region vertically extending from the data driving portion in the lower end non-active area (N/A), and a region formed in parallel to the data driving portion <NUM>.

That is, the driving voltage line 14a, the reference voltage line 14b and the ground line 14c are extending from the data driving portion <NUM> in a vertical direction, at a region adjacent to the data driving portion <NUM> in the lower end non-active area (N/A). The driving voltage line 14a, the reference voltage line 14b and the ground line 14c are formed as bars, in parallel to the data driving portion <NUM>, at a region adjacent to the active area (A/A) in the lower end non-active area (N/A).

The gate signal line (GSL) outputs a gate signal provided from the data driving portion <NUM> to the gate driving portion <NUM>. The data signal line (DSL) outputs a data signal provided from the data driving portion <NUM> to the data line (DL) in the active area (A/A). The light-emitting signal line outputs a light-emitting signal provided from the data driving portion <NUM> to the light-emitting controller.

In accordance with one embodiment, these wires may be formed to cross each other at least once, in the lower end non-active area (N/A). Thus, the power lines 14a~14c and the signal lines GSL, DSL are formed on different layers, in order to prevent short-circuiting when the wires cross each other.

In the conventional flexible OLED display device <NUM>, the lower end non-active area (N/A) is formed to have a larger width than the rest of the non-active area (N/A). A bending area (B/A) is formed in the lower end non-active area (N/A), and part of the lower end non-active area (N/A) is bent to a rear surface of the flexible OLED display device <NUM>. Under such configuration, the width of the lower end non-active area (N/A) can be reduced.

<FIG> is a cross-sectional view of the flexible OLED display device of <FIG>, which illustrates a bent state.

Referring to <FIG>, reference numeral <NUM> denotes an organic light-emitting diode (OLED) formed in an active area (A/A), and reference numeral <NUM> denotes an encapsulation layer for encapsulating an OLED.

Referring to <FIG>, in the conventional flexible OLED display device <NUM>, the lower end non-active area (N/A) is bent based on a bending area (B/A), so that part of the lower end non-active area (N/A) can be positioned on a rear surface of the flexible OLED display device <NUM>. A curvature radius (R) of the bending area (B/A) is about <NUM>.

As mentioned above with reference to <FIG>, in the lower end non-active area (N/A) of the conventional flexible OLED display device <NUM>, wires are formed to cross each other. Thus, the power lines 14a~14c and the signal lines GSL, DSL are formed on different layers.

However, because the wires are formed to cross each other even in the bending area (B/A), the wires may be disconnected from each other due to bending stress in the bending area (B/A).

<FIG> is a cross-sectional view taken along line III-III in <FIG>.

Referring to <FIG>, the signal lines GSL, DSL and the power lines 14a~14c are formed on different layers to thus be insulated from each other.

For instance, a gate signal line (GSL) and a data signal line (DSL) are formed on a flexible substrate <NUM> with a distance therebetween. A first insulating layer <NUM> is formed on the gate signal line (GSL) and the data signal line (DSL).

A driving voltage line 14a and a ground line 14c are formed on the first insulating layer <NUM> with a predetermined gap therebetween. The driving voltage line 14a and the ground line 14c are formed to overlap the gate signal line (GSL) and the data signal line (DSL), respectively. A second insulating layer <NUM> is formed on the driving voltage line 14a and the ground line 14c.

When the bending area (B/A) is bent with more than a predetermined curvature radius, cracks/breaks may occur at wires due to bending stress as shown in <FIG> (indicated by "a" and "b"). This may cause the wires to be disconnected from each other, or the insulating layer may be damaged to cause short-circuiting of the wires.

Such disconnection or short-circuiting of the wires may cause a malfunction of the flexible OLED display device <NUM>.

<CIT> relates to using plastic film in vacuum sealing an OLED. In-organic insulating films which can prevent oxygen or water from being penetrated therein and an organic insulating film which has a smaller internal stress than that of the inorganic insulating films are laminated on an inside of the plastic film. By sandwiching the organic insulating film between the inorganic insulating films, a stress can be relaxed. Further, by laminating a plurality of inorganic insulating films, even if one of the inorganic insulating films has a crack, the other inorganic insulating films can effectively prevent oxygen or water from being penetrated into an organic light emitting layer. Further, the stress of the entire sealing film can be relaxed and cracking due to the stress takes place less often.

<CIT> discloses a flexible display panel that includes a flexible panel including a first region including a display region and oriented on a first plane and a second region including a non-display region and oriented on a second plane different from the first plane; and a flexible encapsulation member disposed on the flexible panel so as to encapsulate at least the display region.

Therefore, an aspect of the detailed description is to provide a flexible display device capable of preventing disconnection or short-circuiting of wires, by forming wires in a bending area of a non-active area, on the same layer so as not to cross each other.

The above-identified problem is solved by the features of the independent claim. Advantageous embodiments can be derived from the respective dependent claims. The present invention can have the following advantages.

In the bending area of the non-active area, wires are formed on the same layer in parallel to each other, so as not to overlap or cross each other. As a result, disconnection or short-circuit of the wires, which occurs when the bending area is bent, can be prevented. Thus a malfunction of the flexible display device can be prevented.

Further scope of applicability of the present application will become more apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the disclosure, are given by way of illustration only, since various changes and modifications within the scope of the disclosure will become apparent to those skilled in the art from the detailed description.

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments and together with the description serve to explain the principles of the disclosure.

Description will now be given in detail of the exemplary embodiments of the present invention, with reference to the accompanying drawings. For the sake of brief description with reference to the drawings, the same or equivalent components will be provided with the same reference numbers, and description thereof will not be repeated.

Hereinafter, a flexible display device and a method for fabricating the same according to the present invention will be explained in more detail.

<FIG> is a planar view of a flexible organic light-emitting diode (OLED) display device according to a first embodiment of the present invention.

Referring to <FIG>, the flexible OLED display device <NUM> according to a first embodiment of the present invention may be formed on a flexible substrate <NUM> including an active area (display area) (A/A) and a non-active area (non-display area) (N/A).

The active area (A/A) is a region where an image is substantially displayed. On the active area (A/A), a plurality of gate lines (GL) and a plurality of data lines (DL) may be formed to cross each other, thereby defining pixel regions. A plurality of sensing lines (SL) may be formed in parallel to the plurality of gate lines (GL).

Power lines for supplying a driving voltage (VDD), a reference voltage (Vref) and a ground voltage (GND) to pixel regions, e.g., a driving voltage line 146b, a reference voltage line 147b and a ground line 145b may be formed in the active area (A/A).

A pixel (P) having a plurality of switching devices may be formed at the pixel region. The pixel (P) may operate by being connected to each of the gate line (GL), the data line (DL) and the sensing line (SL).

<FIG> is an equivalent circuit diagram for a single pixel in the flexible OLED display device of <FIG>.

Referring to <FIG> and <FIG>, the pixel (P) in the active area (A/A) may have a structure where three switching devices (ST1, DT, ST2), one capacitor (C) and one organic light emitting diode (OLED) are formed. However, the present invention is not limited to this configuration. That is, the pixel (P) may be formed to have various structures such as 2T1C, 4T1C, 5T1C and 6T1C.

The switching devices (ST1, DT, ST2) may include a switching transistor (ST1), a driving transistor (DT) and a sensing transistor (ST2). The switching device (ST1, DT, ST2) may be thin film transistors (TFT), for example, formed of amorphous silicon or poly-crystalline silicon.

The switching transistor (ST1) of the pixel (P) may include a gate electrode connected to the gate line (GL) of the active area (A/A), a source electrode connected to the data line (DL), and a drain electrode connected to the driving transistor (DT). The switching transistor (ST1) may output a data signal supplied from the data line (DL) to the driving transistor (DT), according to a gate signal supplied from the gate line (GL).

The driving transistor (DT) of the pixel (P) may include a gate electrode connected to the drain electrode of the switching transistor (ST1), a source electrode connected to an OLED, and a drain electrode connected to driving voltage lines 146a, 146b for supplying a driving voltage (VDD). The driving transistor (DT) may control the size of current applied to the OLED from the driving voltage (VDD), according to a data signal supplied from the switching transistor (ST1).

The capacitor (C) of the pixel (P) may be connected between the gate electrode of the driving transistor (DT) and the OLED. The capacitor (C) may store therein a voltage corresponding to a data signal supplied to the gate electrode of the driving transistor (DT). Also, the capacitor (C) may constantly maintain an 'ON' state of the driving transistor (DT) for a single frame, with the voltage stored therein.

The sensing transistor (ST2) of the pixel (P) may include a gate electrode connected to the sensing line (SL), a source electrode connected to the source electrode of the driving transistor (DT), and a drain electrode connected to reference voltage lines 147a, 147b for supplying a reference voltage (Vref). The sensing transistor (ST2) may sense a threshold voltage (Vth) of the driving transistor (DT), thereby preventing a malfunction of the OLED.

The switching transistor (ST1) of the pixel (P) may be turned on by a gate signal supplied to the gate line (GL), and the capacitor (C) of the pixel (P) may be charged with charges by a data signal supplied to the data line (DL). The amount of current applied to the channel of the driving transistor (DT) may be determined according to a potential difference between a voltage charged at the capacitor (C) and the driving voltage (VDD). The amount of light emitted from the OLED may be determined based on such amount of current. As the OLED emits light, an image is displayed.

The sensing transistor (ST2) may be turned on earlier than the switching transistor (ST1), according to a sensing signal supplied through the sensing line (SL). Under such configuration, electroluminescence of the OLED by the driving voltage (EVDD), which occurs before a data signal is charged at the capacitor (C) during an initial operation of the switching transistor (ST1), can be prevented.

Referring back to <FIG>, the non-active area (N/A) of the flexible OLED display device <NUM> is formed around the active area (A/A). Driving circuitry for driving the pixels (P) in the active area (A/A) and wires may be formed in the non-active area (N/A).

The driving circuitry may include a data driving portion <NUM>, a gate driving portion <NUM> and a light-emitting controller <NUM>.

The data driving portion <NUM> may be mounted at the non-active area (N/A) below the active area (A/A), in the form of a chip. The data driving portion <NUM> may generate a data signal by receiving a signal from an external printed circuit board (not shown). The generated data signals may be output to the plurality of data lines (DL) in the active area (A/A) through wires.

The data driving portion <NUM> may output a gate signal and a light-emitting signal provided from external circuitry, to the gate driving portion <NUM> and the light-emitting controller <NUM> through wires, respectively. The data driving portion <NUM> may output power signals provided from external circuitry, e.g., power signals including a driving voltage (VDD), a reference voltage (Vref), a ground voltage (GND), etc., to driving voltage lines 146a, 146b, reference voltage lines 147a, 147b, and ground lines 145a, 145b, respectively.

The gate driving portion <NUM> may be formed at one side of the non-active area (N/A) outside the active area (A/A), in the form of a gate in panel (GIP). The gate driving portion <NUM> may sequentially output gate signals provided from the data driving portion <NUM> through wires (e.g., gate signal lines 141a), to the plurality of gate lines (GL) in the active area (A/A).

The light-emitting controller <NUM> may be formed at another side of the non-active area (N/A) outside the active area (A/A), in the form of a gate in panel (GIP) so as to correspond to the gate driving portion <NUM>. The light-emitting controller <NUM> may sequentially output light-emitting signals provided from the data driving portion <NUM> through wires (e.g., light-emitting lines 141c), to the plurality of sensing lines (SL) in the active area (A/A).

The wires may include power lines and signal lines formed between the data driving portion <NUM> and the active area (A/A). The power lines may include driving voltage lines 146a, 146b, reference voltage lines 147a, 147b, and ground lines 145a, 145b. Also, the signal lines may include a gate signal line 141a, a data signal line 141b, and a light-emitting signal line 141c.

The power lines may supply power signals provided from the data driving portion <NUM>, to the active area (A/A). The signal lines may supply driving signals provided from the data driving portion <NUM>, e.g., a gate signal, a data signal and a light-emitting signal, to the active area (A/A), the gate driving portion <NUM> and the light-emitting controller <NUM>.

The driving voltage lines 146a, 146b may be formed in the lower end non-active area (N/A), and may output a driving voltage (VDD) provided from the data driving portion <NUM> to the pixel (P) in the active area (A/A).

The driving voltage lines 146a, 146b may include a first driving voltage line 146a and a second driving voltage line 146b. The first driving voltage line 146a connected to the data driving portion <NUM>. The second driving voltage line 146b may be connected to the first driving voltage line 146a and formed as a bar in a direction parallel to the data driving portion <NUM>. The second driving voltage line 146b may be formed such that one side thereof is connected to the first driving voltage line 146a, and another side thereof is extending to the pixel (P) in the active area (A/A). Based on this configuration, the second driving voltage line 146b may output a driving voltage (VDD) provided through the first driving voltage line 146a to each pixel (P).

The reference voltage lines 147a, 147b may be formed in the lower end non-active area (N/A), and may output a reference voltage (Vref) provided from the data driving portion <NUM> to the pixel (P) in the active area (A/A).

The reference voltage lines 147a, 147b may include a first reference voltage line 147a and a second reference voltage line 147b. The first reference voltage line 147a connected to the data driving portion <NUM>. The second reference voltage line 147b may be connected to the first reference voltage line 147a and formed as a bar in parallel to the second driving voltage line 146b. The second reference voltage line 147b may be formed such that one side thereof is connected to the first reference voltage line 147a, and another side thereof is extending to the pixel (P) in the active area (A/A). Based on this configuration, the second reference voltage line 147b may output a reference voltage (Vref) provided through the first reference voltage line 147a to each pixel (P).

The ground lines 145a, 145b may be formed in the lower end non-active area (N/A), and may output a ground voltage (GND) provided from the data driving portion <NUM> to the pixel (P) in the active area (A/A).

The ground lines 145a, 145b may include a first ground line 145a and a second ground line 145b. The first ground line 145a connected to the data driving portion <NUM>. The second ground line 145b may be connected to the first ground line 145a, and formed as a bar in parallel to the second driving voltage line 146b and the second reference voltage line 147b. The second ground line 145b may be formed such that one side thereof is connected to the first ground line 145a, and another side thereof is extending to the pixel (P) in the active area (A/A). By this configuration, the second ground line 145b may output a ground voltage (GND) provided through the first ground line 145a to each pixel (P).

The gate signal line 141a may be formed between the data driving portion <NUM> and the gate driving portion <NUM> in the lower end non-active area (N/A). The gate signal line 141a may output a gate signal provided from the data driving portion <NUM> to the gate driving portion <NUM>. The gate signal may be output to the plurality of gate lines (GL) in the active area (A/A), through the gate driving portion <NUM>.

The data signal line 141b may be formed in the lower end non-active area (N/A), between the data driving portion <NUM> and the data line (DL) in the active area (A/A). The data signal line 141b may output a data signal provided from the data driving portion <NUM> to the plurality of data lines (DL) in the active area (A/A).

The light-emitting signal line 141c may be formed in the non-active area (N/A) between the data driving portion <NUM> and the light-emitting controller <NUM>. The light-emitting signal line 141c may output a light-emitting signal provided from the data driving portion <NUM>, to the light-emitting controller <NUM>. The light-emitting signal may be output to the plurality of sensing lines (SL) in the active area (A/A), by the light-emitting controller <NUM>.

In the flexible OLED display device <NUM> according to this embodiment of the present invention, the lower end non-active area (N/A) includes a bending area (B/A). The bending area (B/A) may be a region which has a predetermined curvature when part of the lower end non-active area (N/A) is bent to the rear or front surface of the flexible OLED display device <NUM>. That is, the bending area (B/A) is a flexible portion including flexible materials that is provided between one end of the display device <NUM> and the other part of the device <NUM> and allows the one end to be bent or rotated around the bending area (B/A) toward the front or rear surface of the other part. In accordance with one embodiment, the lower end non-active area (N/A) may be bent around the bending area (B/A) toward the front or rear surface of the flexible OLED display device <NUM>. As an example, the lower end non-active area (N/A) may be attached to the rear surface of the flexible OLED display device <NUM> by the rotation around the bending area (B/A). Although <FIG> shows only one bending area formed adjacent one end of the flexible OLED display device <NUM>, it will be readily appreciable to one skilled in the art that the bending area (B/A) may be formed adjacent any side of the flexible OLED display device <NUM> (e.g. <NUM> bending areas formed adjacent <NUM> sides of the flexible OLED display device <NUM> in rectangular shape).

The lower end non-active area (N/A) is divided into three regions by the bending area (B/A). The lower end non-active area (N/A) is divided into a first area between the bending area (B/A) and the active area (A/A), the bending area (B/A), and a second area between the bending area (B/A) and an area where the data driving portion <NUM> has been mounted.

The first area of the lower end non-active area (N/A) may be a region covered by a bezel portion, etc., together with the rest of the non-active area (N/A). Also, the second area may be a region that is positioned on a rear surface of the flexible OLED display device <NUM>, by bending of the bending area (B/A).

Power lines, which include the second driving voltage line 146b, the second reference voltage line 147b and the second ground line 145b, may be formed in the first area of the lower end non-active area (N/A).

Signal lines, which include the gate signal line 141a, the data signal line 141b and the light-emitting signal line 141c, may be formed in the first area so as to cross the power lines. The signal lines and the power lines in the first area may be formed to overlap each other at different layers on the flexible substrate <NUM>.

Power lines, which include the first driving voltage line 146a, the first reference voltage line 147a and the first ground line 145a, may be formed in the bending area (B/A) of the lower end non-active area (N/A).

Signal lines, which include the gate signal line 141a, the data signal line 141b and the light-emitting signal line 141c, may be formed in the bending area (B/A) in parallel to the power lines so as not to cross the power lines. The signal lines and the power lines in the bending area (B/A) may be formed to be spaced from each other on the same layer on the flexible substrate <NUM>.

The power lines, which include the first driving voltage line 146a, the first reference voltage line 147a and the first ground line 145a, may be formed in the second area of the lower end non-active area (N/A).

The signal lines, which include the gate signal line 141a, the data signal line 141b and the light-emitting signal line 141c, may be formed in the second area in parallel to the power lines so as not to cross the power lines. The signal lines and the power lines may be formed to be extending from the data driving portion <NUM> in parallel to each other. In this case, the signal lines and the power lines may be formed to be in parallel to each other by being bent at least twice in the second area. The signal lines and the power lines in the second area may be formed to be spaced from each other on the same layer.

As mentioned above, in the flexible OLED display device <NUM> according to this embodiment, wires are formed on the same layer in parallel to each other, in the bending area (B/A) of the lower end non-active area (N/A) where bending is performed. Accordingly, unlike in the conventional art, the occurrence of disconnection of the wires due to bending stress can be prevented.

In the second area and the bending area (B/A) of the lower end non-active area (N/A), wires are formed on the same layer. However, in the first area, wires are formed on different layers. By such configuration, wires formed in the bending area (B/A) may be connected to wires formed on different layers in the first area, through holes (not shown).

<FIG> is a cross-sectional view taken along line VIa~VIa' and VIb~VIb' in the flexible OLED device of <FIG>.

Referring to <FIG> and <FIG>, the flexible OLED display device <NUM> includes pixels (P) formed in the active area (A/A), and wires formed in the non-active area (N/A) (e.g., lower end non-active area (N/A)). The lower end non-active area (N/A) where wires have been formed may be the bending area (B/A).

A thin film transistor (TFT) and an organic light emitting diode (OLED) may be formed on the flexible substrate <NUM> in the active area (A/A).

For instance, a passivation layer <NUM> may be formed on the entire surface of the flexible substrate <NUM>. A semiconductor layer <NUM> formed of amorphous or poly-crystalline silicon may be formed on the passivation layer <NUM>.

A gate insulating layer <NUM> may be formed on the semiconductor layer <NUM>, and a gate electrode <NUM> may be formed on the gate insulating layer <NUM> at a position corresponding to a predetermined region of the semiconductor layer <NUM>.

An interlayer insulating layer <NUM> may be formed on the gate electrode <NUM>, and a source electrode 125a and a drain electrode 125b may be formed on the interlayer insulating layer <NUM>.

The source electrode 125a and the drain electrode 125b may be connected to the semiconductor layer <NUM>, through contact holes (not shown) formed at the interlayer insulating layer <NUM> and the gate insulating layer <NUM>.

The semiconductor layer <NUM>, the gate electrode <NUM>, the source electrode 125a and the drain electrode 125b may constitute a thin film transistor in the active area (A/A) of the flexible substrate <NUM>. The TFT may be, for example, a driving transistor of the flexible OLED display device <NUM>. However, the present invention is not limited to this example.

A planarization layer <NUM> may be formed on the TFT. A first electrode <NUM>, connected to the drain electrode 125b through a contact hole (not shown), may be formed on the planarization layer <NUM>.

A pixel defining layer <NUM>, through which part of the first electrode <NUM> is exposed to the outside, may be formed on the first electrode <NUM>. A light-emitting layer <NUM> may be formed on the pixel defining layer <NUM>. The light-emitting layer <NUM> may be formed on the first electrode <NUM> which has been exposed to the outside by the pixel defining layer <NUM>. A second electrode <NUM> may be formed on the light-emitting layer <NUM>.

The first electrode <NUM>, the light-emitting layer <NUM> and the second electrode <NUM> may constitute an OLED in the active area (A/A) of the flexible substrate <NUM>.

Signal lines and power lines are formed on the flexible substrate <NUM> in the bending area (B/A). The signal lines may include the gate signal line 141a and the data signal line 141b. The power lines may include the first ground line 145a and the first driving voltage line 146a.

For instance, the passivation layer <NUM> may be formed on the entire surface of the flexible substrate <NUM>. The gate signal line 141a, the data signal line 141b, the first ground line 145a and the first driving voltage line 146a may be formed commonly on the passivation layer <NUM>, such that they are spaced from each other with a predetermined distance therebetween, for example, in parallel to each other.

In accordance with one embodiment, the signal lines and the power lines formed in the bending area (B/A) may be formed of the same metallic material as the source electrode 125a and the drain electrode 125b formed in the active area (A/A), at the same processing stage.

Like in the active area (A/A), the planarization layer <NUM> is formed, e.g. as an insulating layer, on the signal lines and the power lines formed in the bending area (B/A).

As mentioned above, in the flexible OLED display device <NUM> according to one embodiment, wires are formed on the same layer in the bending area (B/A), e.g. with the same metallic material. Accordingly, even if the planarization layer <NUM> is damaged by bending stress in the bending area (B/A), the wires in the bending area (B/A) are not disconnected or cracked. This can prevent a malfunction of the flexible OLED display device <NUM>.

<FIG> are views illustrating processes of fabricating a flexible OLED display device according to a first embodiment of the present invention.

A passivation layer <NUM> may be formed on the entire surface of a substrate divided into an active area (A/A) and a non-active area (N/A), e.g., a glass substrate <NUM>. The passivation layer <NUM> is provided so that thin film transistors, organic light-emitting diodes and wires can be prevented from being damaged during the process of detaching the glass substrate <NUM>, as described below in more detail.

The non-active area (N/A) includes a bending area (B/A) formed below the active area (A/A), i.e., a bending area (B/A) of a lower end non-active area (N/A).

Amorphous silicon or poly-crystalline silicon is deposited in the active area (A/A) on the glass substrate <NUM> where the passivation layer <NUM> has been formed. Then the amorphous silicon or the poly-crystalline silicon is selectively patterned, thereby forming a semiconductor layer <NUM>. The semiconductor layer <NUM> may include a source region and a drain region each including impurities, and a channel region including no impurities.

A gate insulating layer <NUM> may be formed on the entire surface of the glass substrate <NUM> where the semiconductor layer <NUM> has been formed. The gate insulating layer <NUM> may be formed as a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multi-layer thereof.

The gate insulating layer <NUM> may not be formed in the non-active area (N/A) of the glass substrate <NUM>.

A gate electrode <NUM> may be formed on the gate insulating layer <NUM>, at a position corresponding to a channel region of the semiconductor layer <NUM>. The gate electrode <NUM> may be formed by depositing a metallic material such as molybdenum (Mo), aluminum (Al), chrome (Cr), titanium (Ti) and copper (Cu), or an alloy thereof, on the gate insulating layer <NUM>, and then by selectively patterning the metallic material or the alloy.

An interlayer insulating layer <NUM> may be formed on the entire surface of the active area (A/A) of the glass substrate <NUM> where the gate electrode <NUM> has been formed. The interlayer insulating layer <NUM> may be formed as a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multi-layer thereof.

Contact holes (not shown) may be formed by etching part of the interlayer insulating layer <NUM> and the gate insulating layer <NUM>, thereby exposing part of the semiconductor layer <NUM>, e.g., a source region and a drain region to the outside therethrough.

A source electrode 125a and a drain electrode 125b may be formed on the interlayer insulating layer <NUM>. The source electrode 125a may be formed so as to be connected to the source region of the semiconductor layer <NUM> through the contact hole, and the drain electrode 125b may be formed so as to be connected to the drain region of the semiconductor layer <NUM> through the contact hole.

The source electrode 125a and the drain electrode 125b may be formed by depositing a metallic material such as Ti, Al and Mo, or an alloy thereof such as Ti/Al/Ti and Mo/Al, on the interlayer insulating layer <NUM>, and then by selectively patterning the metallic material or the alloy.

A thin film transistor (TFT) including the semiconductor layer <NUM>, the gate electrode <NUM>, the source electrode 125a and the drain electrode 125b, which is, e.g., a driving transistor of the flexible OLED display device <NUM>, may be formed in the active area (A/A) of the glass substrate <NUM>.

Wires, e.g., a gate signal line 141a, a data signal line 141b, a first ground line 145a and a first driving voltage line 146a may be formed on the passivation layer <NUM>, in the non-active area (N/A) of the glass substrate <NUM>. Such wires may be formed on the passivation layer <NUM> so as to be spaced from each other with a predetermined interval.

The gate signal line 141a, the data signal line 141b, the first ground line 145a and the first driving voltage line 146a may be formed of the same metallic material as the source electrode 125a and the drain electrode 125b, at the same processing stage.

Referring to <FIG>, a planarization layer <NUM> may be formed on the entire surface of the active area (A/A) where a thin film transistor has been formed, and the non-active area (N/A) where wires have been formed.

The planarization layer <NUM> may be formed by a spin coating method, for example, the method for coating an organic material or an inorganic material such as polyimide, benzocyclobutene series resin and acrylate, in the form of a liquid phase, and then hardening the material.

A contact hole (not shown) may be formed by etching part of the planarization layer <NUM> in the active area (A/A), thereby exposing the drain electrode 125b to the outside therethrough.

A first electrode <NUM> may be formed on the planarization layer <NUM> in the active area (A/A). The first electrode <NUM> may be connected to the drain electrode 125b through the contact hole of the planarization layer <NUM>.

The first electrode <NUM> may be formed of a transparent conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide) or ZnO (Zinc Oxide), which may form the anode of an OLED.

A pixel defining layer <NUM> may be formed on the first electrode <NUM>. The pixel defining layer <NUM> may have an opening through which part of the first electrode <NUM> is exposed to the outside, and may define a pixel region.

The pixel defining layer <NUM> may be formed by a spin coating method, for example, the method for coating an organic material or an inorganic material such as polyimide, benzocyclobutene series resin and acrylate, in the form of a liquid phase, and then hardening the material.

Referring to <FIG> and <FIG>, a light-emitting layer <NUM> may be formed on the pixel defining layer <NUM>. The light-emitting layer <NUM> may be formed on the opening of the pixel defining layer <NUM>, i.e., may be formed on the first electrode <NUM> exposed to the outside by the pixel defining layer <NUM>.

A second electrode <NUM> may be formed on the light-emitting layer <NUM>. The second electrode <NUM> may be formed of aluminum (Al), silver (Ag), magnesium (Mg), or an alloy thereof by deposition.

An OLED including the first electrode <NUM>, the light-emitting layer <NUM> and the second electrode <NUM> may be formed on a TFT of the glass substrate <NUM> in the active area (A/A).

When a TFT and an OLED have been formed in the active area (A/A) and wires have been formed in the non-active area (N/A), the glass substrate <NUM> may be detached from the passivation layer <NUM>. Then, a flexible substrate <NUM> may be attached to the passivation layer <NUM>.

The flexible substrate <NUM> may have the same active area (A/A) and non-active area (N/A) as the glass substrate <NUM>.

The flexible substrate <NUM> may be formed, for example, of one of polycarbon, polyimide, polyether sulfone (PES), polyarylate, polyethylene naphthalate (PEN) or polyethyleneterephthalate (PET).

The glass substrate <NUM> may be detached from the passivation layer <NUM> through irradiation of laser, etc., and the flexible substrate <NUM> may be attached to the passivation layer <NUM> by an adhesive tape such as an optically clear adhesive (OCA), with reference to <FIG>.

<FIG> is a planar view of a flexible OLED display device according to a second embodiment of the present invention.

Referring to <FIG>, the flexible OLED display device according to the second embodiment is formed on a flexible substrate <NUM> having an active area (A/A) and a non-active area (N/A).

A pixel (P) having a plurality of switching devices may be formed at the pixel region. The pixel (P) may be the same pixel as described above with reference to <FIG>.

The non-active area (N/A) of the flexible OLED display device <NUM> is formed around the active area (A/A), which may be defined by the dotted line. Driving circuitry for driving the pixels (P) in the active area (A/A) and wires may be formed in the non-active area (N/A).

The data driving portion <NUM> may be mounted in the non-active area (N/A) positioned below the active area (A/A), i.e., the lower-end non-active area (N/A). The gate driving portion <NUM> and the light-emitting controller <NUM> may be formed in the non-active area (N/A), i.e., at two sides outside the active area (A/A), in the form of a gate in panel (GIP).

The data driving portion <NUM> may generate a data signal by receiving a signal from an external circuit. The generated data signal may be output to the plurality of data lines (DL) in the active area (A/A) through wires. The gate driving portion <NUM> may output a gate signal provided from the data driving portion <NUM>, to the plurality of gate lines (GL) in the active area (A/A), through wires. The light-emitting controller <NUM> may output a light-emitting signal provided from the data driving portion <NUM>, to the plurality of sensing lines (SL) in the active area (A/A), through wires.

Wires may include power lines including driving voltage lines 146a, 146b, reference voltage lines 147a, 147b, and ground lines 145a, 145b, and signal lines including a gate signal line 141a, a data signal line 141b, and a light-emitting signal line 141c.

The driving voltage lines 146a, 146b may include a first driving voltage line 146a and a second driving voltage line 146b. The first driving voltage line 146a connected to the data driving portion <NUM>. The second driving voltage line 146b may be connected to the first driving voltage line 146a, and formed as a bar in a direction parallel to the data driving portion <NUM>. The second driving voltage line 146b may be formed such that one side thereof is connected to the first driving voltage line 146a, and another side thereof is extending to the pixel (P) in the active area (A/A). Based on this configuration, the second driving voltage line 146b may output a driving voltage (VDD) provided through the first driving voltage line 146a to each pixel (P).

The reference voltage lines 147a, 147b may include a first reference voltage line 147a and a second reference voltage line 147b. The first reference voltage line 147a connected to the data driving portion <NUM>. The second reference voltage line 147b may be connected to the first reference voltage line 147a, and formed as a bar in parallel to the second driving voltage line 146b. The second reference voltage line 147b may be formed such that one side thereof is connected to the first reference voltage line 147a, and another side thereof is extending to the pixel (P) in the active area (A/A). Based on this configuration, the second reference voltage line 147b may output a reference voltage (Vref) provided through the first reference voltage line 147a to each pixel (P).

The ground lines 145a, 145b may include a first ground line 145a and a second ground line 145b. The first ground line 145a may be connected to the data driving portion <NUM>. Further, the second ground line 145b may be connected to the first ground line 145a, and formed as a bar in a direction parallel to the second driving voltage line 146b and the second reference voltage line 147b. The second ground line 145b may be formed such that one side thereof is connected to the first ground line 145a, and another side thereof is extending to the pixel (P) in the active area (A/A). Based on this configuration, the second ground line 145b may output a ground voltage (GND) provided through the first ground line 145a to each pixel (P).

The gate signal line 141a may be formed in the lower end non-active area (N/A), between the data driving portion <NUM> and the gate driving portion <NUM>. The gate signal line 141a may output a gate signal provided from the data driving portion <NUM> to the gate driving portion <NUM>. The gate signal may be output to the plurality of gate lines (GL) in the active area (A/A), through the gate driving portion <NUM>.

The data signal line 141b may be formed in the lower end non-active area (N/A), between the data driving portion <NUM> and the data line (DL) in the active area (A/A). The data signal lines 141b may output data signals provided from the data driving portion <NUM> to the plurality of data lines (DL) in the active area (A/A).

The light-emitting signal line 141c may be formed in the non-active area (N/A), between the data driving portion <NUM> and the light-emitting controller <NUM>. The light-emitting signal line 141c may output a light-emitting signal provided from the data driving portion <NUM>, to the light-emitting controller <NUM>. The light-emitting signal may be output to the plurality of sensing lines (SL) in the active area (A/A), by the light-emitting controller <NUM>.

In the flexible OLED display device <NUM> according to the second embodiment of the present invention, the lower end non-active area (N/A) includes a bending area (B/A). The bending area (B/A) may be a region which has a predetermined curvature when part of the lower end non-active area (N/A) is bent to the front or rear surface of the flexible OLED display device <NUM>.

The first area of the lower end non-active area (N/A) may be a region covered by a bezel portion, etc., together with the rest of the non-active area (N/A). Also, the second area is a region positioned on the rear surface of the flexible OLED display device <NUM>, by bending of the bending area (B/A).

The plurality of data signal lines 141b and the plurality of power lines may be formed in the first area. The plurality of power lines include the second driving voltage line 146b, the second reference voltage line 147b and the second ground line 145b. The plurality of data signal lines 141b may be connected to the plurality of data lines (DL) in the active area (A/A). The plurality of data signal lines 141b and the plurality of power lines may be formed in the first area in parallel with each other.

In the bending area (B/A) of the lower end non-active area (N/A), the plurality of data signal lines 141b and the plurality of power lines formed in the first area, may be formed in parallel with each other.

In the bending area (B/A) of the lower end non-active area (N/A), the plurality of lines extending from the power lines toward the active area (A/A), the plurality of data signal lines 141b, the gate signal lines 141a and the light-emitting signal lines 141c may be formed so as to be spaced from each other on the same layer on the flexible substrate <NUM>.

In the second area of the lower-end non-active area (N/A), signal lines including the gate signal lines 141a, the data signal lines 141b and the light-emitting signal lines 141c may be formed to cross power lines. The power lines, which may have a bar shape, may include first and second driving voltage lines 146a, 146b, first and second reference voltage lines 147a, 147b, and first and second ground lines 145a, 145b. The signal lines and the power lines in the second area may be formed to overlap each other on different layers on the flexible substrate <NUM>.

The signal lines and the power lines may be formed to be in parallel to each other in the first area and the bending area (B/A), by being bent at least twice in the second area.

That is, in the flexible OLED display device <NUM> according to the second embodiment, a plurality of signal lines and a plurality of power lines may be formed to cross each other in the second area positioned on the rear surface of the flexible OLED display device <NUM> when the bending area (B/A) of the lower end non-active area (N/A) is bent toward the rear surface of the device <NUM>. Thus, in the flexible OLED display device <NUM> according to the second embodiment, the width of the lower end non-active area (N/A) can be more reduced than in the conventional flexible OLED display device. As a result, the flexible OLED display device <NUM> according to the second embodiment can have a narrow bezel portion.

As mentioned above, in the flexible OLED display device <NUM> according to the second embodiment, a plurality of signal lines and a plurality of power lines are formed on the same layer in parallel to each other, in the bending area (B/A) of the lower end non-active area (N/A). Accordingly, unlike in the conventional art, disconnection of the wires can be prevented even if an insulating layer is damaged due to bending stress.

In the first area and the bending area (B/A) of the lower end non-active area (N/A), wires are formed on the same layer in accordance with one embodiment of the invention. However, in the second area, wires may be formed on different layers. Based on this configuration, wires formed on different layers in the second area may be connected to wires formed on the same layer in the bending area (B/A), through holes (not shown).

<FIG> is a cross-sectional view taken along line VIII~VIII' in the flexible OLED display device of <FIG>.

Referring to <FIG> and <FIG>, in the bending area (B/A) of the lower end non-active area (N/A) of the flexible OLED display device <NUM>, a plurality of wires are formed on the same layer, e.g. in a spaced manner from each other.

For instance, in the bending area (B/A), a passivation layer <NUM> is formed on a flexible substrate <NUM>. A gate signal line 141a, a data signal line 141b, a second ground line 145b and a second driving voltage line 146b may be formed on the passivation layer <NUM>, such that they are spaced from each other with predetermined distances, in parallel to each other.

A first insulating layer 117a may be formed on the gate signal line 141a, the data signal line 141b, the second ground line 145b and the second driving voltage line 146b.

A plurality of wires may be formed to overlap each other on different layers, in the second area positioned on the rear surface of the flexible OLED display device <NUM> when the bending area (B/A) of the lower end non-active area (N/A) is bent.

For instance, in the second area, a passivation layer <NUM> is formed on a flexible substrate <NUM>. A gate signal line 141a and a data signal line 141b may be formed on the passivation layer <NUM>, such that they are spaced from each other in parallel to each other.

A first insulating layer 117a may be formed on the gate signal line 141a and the data signal line 141b. A second ground line 145b and a second driving voltage line 146b may be formed on the first insulating layer 117a, with a predetermined distance therebetween in parallel to each other. In this case, the second ground line 145b and the second driving voltage line 146b may be formed to overlap the gate signal line 141a and the data signal line 141b.

A second insulating layer 117b may be formed on the second ground line 145b and the second driving voltage line 146b.

In the flexible OLED display device <NUM> according to the second embodiment, the pixel region in the active area (A/A) has the same cross-sectional profile as the pixel region described above with reference to <FIG>, of which description is not repeated.

A plurality of wires formed in the non-active area (N/A) may be formed of the same metallic material as a source electrode (not shown) and a drain electrode (not shown) in the pixel region, at the same processing stage. The plurality of wires indicates power lines including the second ground line 145b and the second driving voltage line 146b, and signal lines including the gate signal line 141a and the data signal line 141b. For instance, the plurality of wires may be formed of a metallic material such as Ti, Al and Mo or an alloy thereof such as Ti/Al/Ti and Mo/Al.

<FIG> is a view illustrating a wire structure in a bending area in a flexible OLED display device according to the present invention, and <FIG> is a view illustrating various embodiments of <FIG>.

In this embodiment, the flexible OLED display device <NUM> of <FIG> will be explained for convenience. However, this embodiment may be also applicable to the flexible OLED display device <NUM> of <FIG>.

Referring to <FIG> and <FIG>, in the flexible OLED display device <NUM>, wires may be formed to have a large width for prevention of disconnection thereof due to bending stress in the bending area (B/A) of the lower end non-active area (N/A).

For instance, as shown in <FIG>, the width (d2) of wires in the bending area (B/A) of the lower end non-active area (N/A) may be greater than the width (d1) of wires in the first area and the second area of the lower end non-active area (N/A).

As shown in <FIG>, wires are formed, in the bending area (B/A), with a shape such as a triangle, a diamond, a semi-circle and a circle. Thus, disconnection of the wires, due to bending stress occurring when the bending area (B/A) is bent, can be prevented.

That is, in the flexible OLED display device <NUM>, disconnection of wires, which occurs when the bending area (B/A) is bent, can be prevented by various shape changes of the wires in the bending area (B/A). In order to prevent resistance increase of the wires due to the shape changes of the wires, the wires may be formed such that the width in the bending area (B/A) is larger than that in the other regions. As a result, disconnection of the wires, which occurs when the bending area (B/A) is bent, can be prevented.

Claim 1:
A display device comprising:
a flexible substrate (<NUM>) including an active area (A/A), and a non-active area (N/A) around the active area (A/A), wherein a lower end of the non-active area (N/A) is divided into a first area, a bending area (B/A), and a second area, wherein the first area is between the bending area (B/A) and the active area (A/A), wherein the second area is between the bending area (B/A) and a circuit mount area, wherein the bending area (B/A) is configured to be bent flexibly, wherein by bending of the bending region (B/A), the first area is positioned on a front surface in top view of the display device while the second area is positioned on a rear surface in top view of the display device;
a plurality of pixels (P) disposed to display an image in the active area (A/A), each of the plurality of pixels (P) including an organic light emitting diode, OLED, configured to receive a signal from at least one signal line (141a, 141b, 141c) and power from at least one power line (145a, 146a, 147a) to display the image;
the at least one signal line (141a, 141b, 141c) and the at least one power line (145a, 146a, 147a) disposed on the flexible substrate (<NUM>), the at least one signal line (141a, 141b, 141c) and the at least one power line (145a, 146a, 147a) being disposed on a same layer in the bending area (B/A);
a planarization layer (<NUM>) covering the at least one signal line (141a, 141b, 141c) and the at least one power line (145a, 146a, 147a) in the bending area (B/A) .