Patent Description:
Power semiconductor module arrangements often include at least one semiconductor substrate arranged in a housing. A semiconductor arrangement including a plurality of controllable semiconductor elements (e.g., two IGBTs in a half-bridge configuration) is arranged on each of the at least one substrate. Each substrate usually comprises a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer and a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor elements are mounted, for example, on the first metallization layer. The second metallization layer may optionally be attached to a base plate or heat sink.

There is a need for a substrate arrangement that allows to securely mount elements thereon in a simple manner.

A substrate arrangement comprises a first metallization layer, a plurality of nanowires arranged on a surface of the first metallization layer, and at least one component arranged on the first metallization layer such that a first subset of the plurality of nanowires is arranged between the first metallization layer and the at least one component, wherein the plurality of nanowires is evenly distributed over a section such a manner that the conductive nanotubes fixed to the electrodes remain on the electrodes formed on the semiconductor substrate.

Document <CIT> discloses a composite conductive film that is formed of a polymer-matrix and a plurality of nano-sized conductive lines. The composite conductive film has low resistance, to connect between a fine-pitch chip and a chip in a low temperature and low pressure condition. The conductive lines are parally arranged and spaced apart from each other, to provide anisotropic conductivity. The conductive film can be served as an electrical connection between a fine-pitch chip and a chip or a fine-pitch chip and a substrate.

A substrate arrangement comprises a first metallization layer, a plurality of nanowires arranged on a surface of the first metallization layer, and at least one component arranged on the first metallization layer such that a first subset of the plurality of nanowires is arranged between the first metallization layer and the at least one component, wherein the plurality of nanowires is evenly distributed over a section of the surface area or over the entire surface area of the first metallization layer, each of the plurality of nanowires includes a first end and a second end, wherein the first end of each of the plurality nanowires is inseparably connected to the surface of the first metallization layer, the second end of each nanowire of the first subset is inseparably connected to a surface of one of the at least one component such that the first subset of nanowires forms a permanent connection between the first metallization layer and the at least one component, the at least one component comprises at least one semiconductor body, and the number of nanowires comprised in the first subset of nanowires is less than the number of nanowires comprised in the plurality of nanowires. The substrate arrangement further includes an encapsulant, wherein the encapsulant consists of or includes a silicone gel and directly adjoins the second ends of a second subset of the plurality of nanowires and fills any gaps and spaces between the nanowires of the second subset.

A method includes forming a first metallization layer, forming a plurality of nanowires on a surface of the first metallization layer, and arranging at least one component on the first metallization layer such that a first subset of the plurality of nanowires is arranged between the first metallization layer and the at least one component, wherein the plurality of nanowires is evenly distributed over a section of the surface area or over the entire surface area of the first metallization layer, each of the plurality of nanowires includes a first end and a second end, wherein the first end of each of the plurality nanowires is inseparably connected to the surface of the first metallization layer, the second end of each nanowire of the first subset is inseparably connected to a surface of one of the at least one component such that the first subset of nanowires forms a permanent connection between the first metallization layer and the at least one component, the at least one component comprises at least one semiconductor body, and the number of nanowires comprised in the first subset of nanowires is less than the number of nanowires comprised in the plurality of nanowires. The method further includes forming an encapsulant, wherein the encapsulant consists of or includes a silicone gel and directly adjoins the second ends of a second subset of the plurality of nanowires and fills any gaps and spaces between the nanowires of the second subset.

In the following detailed description, reference is made to the accompanying drawings. The drawings show specific examples in which the invention may be practiced. It is to be understood that the features and principles described with respect to the various examples may be combined with each other, unless specifically noted otherwise. In the description, as well as in the claims, designations of certain elements as "first element", "second element", "third element" etc. are not to be understood as enumerative. Instead, such designations serve solely to address different "elements". That is, e.g., the existence of a "third element" does not require the existence of a "first element" and a "second element". An electrical line or electrical connection as described herein may be a single electrically conductive element, or include at least two individual electrically conductive elements connected in series and/or parallel. Electrical lines and electrical connections may include metal and/or semiconductor material, and may be permanently electrically conductive (i.e., non-switchable). A semiconductor body as described herein may be made from (doped) semiconductor material and may be a semiconductor chip or be included in a semiconductor chip. A semiconductor body has electrically connecting pads and includes at least one semiconductor element with electrodes.

Referring to <FIG>, a cross-sectional view of a power semiconductor module arrangement <NUM> is schematically illustrated. The power semiconductor module arrangement <NUM> includes a housing <NUM> and a substrate <NUM>. The substrate <NUM> includes a dielectric insulation layer <NUM>, a (structured) first metallization layer <NUM> attached to the dielectric insulation layer <NUM>, and a (structured) second metallization layer <NUM> attached to the dielectric insulation layer <NUM>. The dielectric insulation layer <NUM> is disposed between the first and second metallization layers <NUM>, <NUM>.

Each of the first and second metallization layers <NUM>, <NUM> may consist of or include one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; any other metal or alloy that remains solid during the operation of the power semiconductor module arrangement. The substrate <NUM> may be a ceramic substrate, that is, a substrate in which the dielectric insulation layer <NUM> is a ceramic, e.g., a thin ceramic layer. The ceramic may consist of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulation layer <NUM> may consist of or include one of the following materials: Al<NUM>O<NUM>, AIN, SiC, BeO or Si<NUM>N<NUM>. For instance, the substrate <NUM> may, e.g., be a Direct Copper Bonding (DCB) substrate, a Direct Aluminum Bonding (DAB) substrate, or an Active Metal Brazing (AMB) substrate. Further, the substrate <NUM> may be an Insulated Metal Substrate (IMS). An Insulated Metal Substrate generally comprises a dielectric insulation layer <NUM> comprising (filled) materials such as epoxy resin or polyimide, for example. The material of the dielectric insulation layer <NUM> may be filled with ceramic particles, for example. Such particles may comprise, e.g., SiO<NUM>, Al<NUM>O<NUM>, AIN, or BN and may have a diameter of between about <NUM> and about <NUM>. The substrate <NUM> may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulation layer <NUM>. For instance, a non-ceramic dielectric insulation layer <NUM> may consist of or include a cured resin.

The substrate <NUM> is arranged in a housing <NUM>. In the example illustrated in <FIG>, the substrate <NUM> is arranged on a base plate <NUM> which forms a ground surface of the housing <NUM>, while the housing <NUM> itself solely comprises sidewalls and a cover or lid. This is, however, only an example. It is also possible that the housing <NUM> further comprises a ground surface and the substrate <NUM> and the base plate <NUM> be arranged inside the housing <NUM>. In some power semiconductor module arrangements <NUM>, more than one substrate <NUM> is arranged on a single base plate <NUM> or on the ground surface of a housing <NUM>. It is, however, also possible that the power semiconductor module arrangement <NUM> does not comprise a base plate <NUM> at all. For example, the substrate <NUM> may form a ground surface of the housing <NUM> instead. It is also possible that the housing <NUM> comprises a ground surface, sidewalls and a cover, and one or more substrates <NUM> are arranged on the ground surface and inside the housing <NUM>. That is, the power semiconductor module arrangement may be an arrangement comprising a base plate <NUM>, or a base plate-less power semiconductor module arrangement <NUM>.

One or more semiconductor bodies <NUM> may be arranged on the at least one substrate <NUM>. Each of the semiconductor bodies <NUM> arranged on the at least one substrate <NUM> may include a diode, an IGBT (Insulated-Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a JFET (Junction Field-Effect Transistor), a HEMT (High-Electron-Mobility Transistor), and/or any other suitable semiconductor element.

The one or more semiconductor bodies <NUM> may form a semiconductor arrangement on the substrate <NUM>. In <FIG>, only two semiconductor bodies <NUM> are exemplarily illustrated. The second metallization layer <NUM> of the substrate <NUM> in <FIG> is a continuous layer. The first metallization layer <NUM> is a structured layer in the example illustrated in <FIG>. "Structured layer" means that the first metallization layer <NUM> is not a continuous layer, but includes recesses between different sections of the layer. Such recesses are schematically illustrated in <FIG>. The first metallization layer <NUM> in this example includes three different sections. This, however, is only an example. Any other number of sections is possible. Different semiconductor bodies <NUM> may be mounted to the same or to different sections of the first metallization layer <NUM>. Different sections of the first metallization layer <NUM> may have no electrical connection or may be electrically connected to one or more other sections using electrical connections <NUM> such as, e.g., bonding wires. Electrical connections <NUM> may also include connection plates or conductor rails, for example, to name just a few examples. The one or more semiconductor bodies <NUM> may be electrically and mechanically connected to the substrate <NUM> by an electrically conductive connection layer <NUM>. Such an electrically conductive connection layer <NUM> may be a solder layer, a layer of an electrically conductive adhesive, or a layer of a sintered metal powder, e.g., a sintered silver powder, for example.

According to other examples, it is also possible that the second metallization layer <NUM> is a structured layer. It is further possible to omit the second metallization layer <NUM> altogether. It is generally also possible that the first metallization layer <NUM> is a continuous layer, for example.

The power semiconductor module arrangement <NUM> illustrated in <FIG> further includes terminal elements <NUM>. The terminal elements <NUM> are electrically connected to the first metallization layer <NUM> and provide an electrical connection between the inside and the outside of the housing <NUM>. The terminal elements <NUM> may be electrically connected to the first metallization layer <NUM> with a first end <NUM>, while a second end <NUM> of each of the terminal elements <NUM> protrudes out of the housing <NUM>. The terminal elements <NUM> may be electrically contacted from the outside at their respective second ends <NUM>. A first part of the terminal elements <NUM> may extend through the inside of the housing <NUM> in a vertical direction y. The vertical direction y is a direction perpendicular to a top surface of the substrate <NUM>, wherein the top surface of the substrate <NUM> is a surface on which the at least one semiconductor body <NUM> is mounted. The terminal elements <NUM> illustrated in <FIG>, however, are only examples. Terminal elements <NUM> may be implemented in any other way and may be arranged anywhere within the housing <NUM>. For example, one or more terminal elements <NUM> may be arranged close to or adjacent to the sidewalls of the housing <NUM>. Terminal elements <NUM> could also protrude through the sidewalls of the housing <NUM> instead of through the cover. The first end <NUM> of a terminal element <NUM> may be electrically and mechanically connected to the substrate <NUM> by an electrically conductive connection layer, for example (not explicitly illustrated in <FIG>). Such an electrically conductive connection layer may be a solder layer, a layer of an electrically conductive adhesive, or a layer of a sintered metal powder, e.g., a sintered silver (Ag) powder, for example. The first end <NUM> of a terminal element <NUM> may also be electrically coupled to the substrate <NUM> via one or more electrical connections <NUM>, for example. For example, the second ends <NUM> of the terminal elements <NUM> may be connected to a printed circuit board that is arranged outside of the housing <NUM> (not illustrated in <FIG>).

The power semiconductor module arrangement <NUM> further includes an encapsulant <NUM>. The encapsulant <NUM> consists of or includes a silicone gel for example. The encapsulant <NUM> may at least partly fill the interior of the housing <NUM>, thereby covering the components and electrical connections that are arranged on the substrate <NUM>. The terminal elements <NUM> may be partly embedded in the encapsulant <NUM>. At least their second ends <NUM>, however, are not covered by the encapsulant <NUM> and protrude from the encapsulant <NUM> through the housing <NUM> to the outside of the housing <NUM>. The encapsulant <NUM> is configured to protect the components and electrical connections of the power semiconductor module <NUM>, in particular the components arranged on the substrate <NUM> inside the housing <NUM>, from certain environmental conditions and mechanical damage.

As has been described above, different components (e.g., semiconductor bodies <NUM>, terminal elements <NUM> or any other components) may be mounted to the substrate <NUM> (i.e. the first metallization layer <NUM>) by means of an electrically conductive connection layer <NUM>. Such an electrically conductive connection layer <NUM>, however, may have several drawbacks. For example, a plurality of different steps may have to be performed when forming an electrically conductive connection layer <NUM> (e.g., solder layer, a layer of an electrically conductive adhesive, or a layer of a sintered metal powder).

Now referring to <FIG>, a first connection partner <NUM> and a second connection partner <NUM> are schematically illustrated. The first connection partner <NUM> may be a substrate for a power semiconductor module, for example. The second connection partner <NUM> may be a semiconductor body, a terminal element, or any other component that is to be mounted to the substrate, for example. It is, however, also possible that the first connection partner <NUM> is a heat sink or base plate, and the second connection partner <NUM> is a substrate. A plurality of nanowires <NUM> is formed on a surface of the first connection partner <NUM> which faces the second connection partner <NUM>. A second plurality of nanowires <NUM> is formed on a surface of the second connection partner <NUM> which faces the first connection partner <NUM>. Each of the plurality of nanowires <NUM> has a first end and a second end. A first end of each of the plurality of nanowires <NUM> is inseparably connected to the surface of the first connection partner <NUM>. A first end of each of the second plurality of nanowires <NUM> is inseparably connected to the surface of the second connection partner. The first and second connection partners <NUM>, <NUM> are arranged at a certain distance from each other. The second ends of the plurality of nanowires <NUM> and the second ends of the second plurality of nanowires <NUM> are free ends. The surface of the first connection partner <NUM> on which the plurality of nanowires <NUM> is formed and the surface of the second connection partner <NUM> on which the second plurality of nanowires <NUM> is formed may consist of the same material such as, e.g., Al, an Al alloy, Cu, a Cu alloy, Ag, an Ag alloy, Au, or an Au alloy.

The first connection partner <NUM> and the second connection partner <NUM> are then moved towards each other such that the second ends of the plurality of nanowires <NUM> contact the surface of the second connection partner <NUM>, and the second ends of the second plurality of nanowires <NUM> contact the surface of the first connection partner <NUM>. Under the influence of pressure and heat, the second ends of the plurality of nanowires <NUM> may be inseparably connected to the surface of the second connection partner <NUM>, and the second ends of the second plurality of nanowires <NUM> may be inseparably connected to the surface of the first connection partner <NUM>. In this way, a permanent connection between the first connection partner <NUM> and the second connection partner <NUM> may be formed by means of the nanowires <NUM>.

The term nanowires <NUM> as used herein designates any element having the form of a wire, i.e. a length that is several times larger than its diameter, wherein the dimensions of the element are in the nanometer range. For example, so-called nanotubes or nanorods may also be used and are considered to fall under the term nanowire as used herein. Generally speaking, a nanowire <NUM> is a nanostructure in the form of a wire having a nanorange diameter. For example, a diameter of a nanowire <NUM> may be between <NUM> and <NUM>. The nanowires <NUM> may have a length between their first end and their second end of between <NUM> and <NUM>, for example. The nanowires <NUM> generally extend perpendicular to the surface on which they are formed. Therefore, all nanowires <NUM> may have the same length such that the second ends of all of the nanowires <NUM> extend all the way to the surface of the other connection partner. The nanowires <NUM> may comprise or consist of carbon, cobalt, copper, silicon, or gold, for example.

Nanowires <NUM> may be formed by any suitable process such as, e.g., (chemical) vapor deposition, suspension, electrochemical deposition, VLS growth (VLS = Vapor-liquid-solid method), and ion track technology.

In the example illustrated in <FIG>, the first and the second connection partners <NUM>, <NUM> are each provided with nanowires <NUM>. This, however, is only an example. As is schematically illustrated in <FIG>, it is also possible to form nanowires <NUM> only on one of the two connection partners. In the example illustrated in <FIG>, the plurality of nanowires <NUM> formed on the first connection partner <NUM> and the second plurality of nanowires <NUM> formed on the second connection partner <NUM> can be considered to intertwine when the first and second connection partner <NUM>, <NUM> are arranged close enough to each other and a permanent connection is formed between the two connection partners <NUM>, <NUM>. This is not the case in the example of <FIG>, because no nanowires <NUM> are formed on the surface of the second connection partner <NUM>. However, with the plurality of nanowires <NUM> formed on the first connection partner <NUM>, it is still possible to form a permanent connection between the first connection partner <NUM> and the second connection partner <NUM>. The stability of the connection, however, may be further improved if nanowires <NUM> are provided on both surfaces.

Now referring to <FIG>, a substrate arrangement according to one example is schematically illustrated. The substrate arrangement may comprise a substrate <NUM>, similar to what has been described with respect to <FIG> above. The dielectric insulation layer <NUM>, however, may also be omitted. The metallization layer <NUM>, for example, may also be a so-called lead frame (die pad). That is, the substrate arrangement may solely comprise a metallization layer <NUM> and no dielectric insulation layer <NUM>. The substrate <NUM> that is schematically illustrated in <FIG> comprises a dielectric insulation layer <NUM> and a first metallization layer <NUM> attached to a first side of the dielectric insulation layer <NUM>. The substrate <NUM>, optionally, may further comprise a second metallization layer (not specifically illustrated in <FIG>). The substrate arrangement further comprises a plurality of nanowires <NUM> arranged on a surface of the first metallization layer <NUM>. If the metallization layer <NUM> is arranged on a dielectric insulation layer <NUM>, the plurality of nanowires <NUM> is arranged on a surface of the first metallization layer <NUM> that faces away from the dielectric insulation layer <NUM>. The plurality of nanowires <NUM> is evenly distributed over a section of the surface area or over the entire surface area of the first metallization layer <NUM>. That is, the number of nanowires <NUM> per unit area is the same over at least a section of the entire surface area of the first metallization layer <NUM>. According to one example, the section of the surface area of the first metallization layer <NUM> covered by the plurality of nanowires <NUM> is between <NUM>% and <NUM>%, or between <NUM>% and <NUM>% of the entire surface area of the first metallization layer <NUM>. In the example illustrated in <FIG>, the first metallization layer <NUM> is a structured layer. All of the different sections of the first metallization layer <NUM> may be entirely covered by nanowires <NUM>. It is, however, also possible that one or more, but not all sections of the first metallization layer <NUM> remain free of nanowires <NUM>. Additionally or alternatively it is also possible that one or more sections are only partly covered by nanowires <NUM>.

The nanowires <NUM> are generally formed on the first metallization layer <NUM> before any components (e.g., semiconductor bodies <NUM>, terminal elements <NUM>, or any other components) are arranged on the substrate <NUM>. By covering at least a (large) section or even the entire surface area of the first metallization layer <NUM> with nanowires <NUM>, the substrate <NUM> may be equipped with components very flexibly. The section that is covered by the nanowires <NUM> is larger than the area required for mounting the components <NUM>, <NUM> to the metallization layer <NUM>. In this way, the components that are to be arranged on the substrate <NUM> do not have to be mounted to any specifically dedicated areas. That is, the substrate arrangement can be sold to different customers, irrespective of the specific design of the customer. Or the same customer may use the same substrate for different designs without the need for any adaptions or customizations. After any semiconductor bodies <NUM> and/or other components have been mounted to the substrate <NUM>, a different subset of the plurality of nanowires <NUM> is arranged between each of the at least one component <NUM>, <NUM> and the first metallization layer <NUM>, wherein the second end of each nanowire <NUM> of the at least one subset is inseparably connected to a surface of the respective component <NUM>, <NUM> such that each subset of nanowires <NUM> forms a permanent connection between the respective component <NUM>, <NUM> and the first metallization layer <NUM>.

The number of nanowires <NUM> comprised in the at least one subset of nanowires <NUM>, however, is less than the number of nanowires <NUM> comprised in the plurality of nanowires <NUM>. That is, the second ends of at least one other subset of nanowires <NUM> are free ends that are not connected to any component <NUM>, <NUM>.

A method for producing a substrate arrangement according to one example comprises forming a first metallization layer <NUM>, forming a plurality of nanowires <NUM> on a surface of the first metallization layer <NUM>, and arranging at least one component <NUM>, <NUM> on the first metallization layer <NUM> such that a first subset of the plurality of nanowires is arranged between the first metallization layer and the at least one component, wherein the plurality of nanowires <NUM> is evenly distributed over a section of the surface area or over the entire surface area of the first metallization layer <NUM>, each of the plurality of nanowires <NUM> comprises a first end and a second end, wherein the first end of each of the plurality nanowires <NUM> is inseparably connected to the surface of the first metallization layer <NUM>, the second end of each nanowire of the first subset is inseparably connected to a surface of one of the at least one component <NUM>, <NUM> such that the first subset of nanowires forms a permanent connection between the first metallization layer <NUM> and the at least one component <NUM>, <NUM>, the at least one component comprises at least one semiconductor body <NUM>, and the number of nanowires <NUM> comprised in the first subset of nanowires <NUM> is less than the number of nanowires <NUM> comprised in the plurality of nanowires <NUM>.

In the example illustrated in <FIG>, a substrate <NUM> comprising a dielectric insulation layer <NUM> and a continuous first metallization layer <NUM> is provided (<FIG>), and the plurality of nanowires <NUM> is formed on the continuous first metallization layer <NUM> (<FIG>). The first metallization layer <NUM> in this example is only structured after forming the plurality of nanowires <NUM>, as is schematically illustrated in <FIG>.

According to another example, however, and as is schematically illustrated in <FIG>, it is alternatively also possible to provide a substrate <NUM> comprising a dielectric insulation layer <NUM> and a continuous first metallization layer <NUM> (<FIG>), and to structure the first metallization layer <NUM> (<FIG>) before forming the plurality of nanowires <NUM> (<FIG>). When structuring the first metallization layer <NUM>, two or more separate sections and recesses between different sections of the first metallization layer <NUM> are formed.

As has been described above, different methods can be used to form the nanowires <NUM>. With most methods, nanowires <NUM> can only be formed on metallic surfaces. Therefore, if the first metallization layer <NUM> is structured first, as is exemplarily illustrated in <FIG>, generally no nanowires <NUM> will form on those sections of the dielectric insulation layer <NUM>, which are no longer covered by the first metallization layer <NUM>. As has been described with respect to <FIG> above, the dielectric insulation layer <NUM> generally does not comprise any metallic surfaces. Therefore, no nanowires <NUM> will grow on the surfaces of the dielectric insulation layer <NUM>.

According to another example, however, it is also possible to form a masking layer <NUM> after structuring the first metallization layer (see <FIG>) and before forming the plurality of nanowires <NUM>, as is schematically illustrated in <FIG>. In particular, the masking layer <NUM> may be formed on those sections of the dielectric insulation layer <NUM> that are not covered by the first metallization layer <NUM>, thereby preventing nanowires <NUM> from being formed on the dielectric insulation layer <NUM>. Once the nanowires <NUM> have been formed, the masking layer <NUM> may be removed (not specifically illustrated).

Now referring to <FIG>, components such as, e.g., semiconductor bodies <NUM>, may be mounted on the surface of the first metallization layer <NUM>. Such components <NUM> may be fitted with nanowires <NUM> as well, as has been described with respect to <FIG> above and as is exemplarily illustrated for the semiconductor body on the right hand side of <FIG>. This, however, is not mandatory. As has been described with respect to <FIG> above and as is exemplarily illustrated on the left hand side of <FIG>, it is also possible that no nanowires <NUM> are formed on a surface of the component that is to be mounted to the substrate <NUM>. As has been described with respect to <FIG> above, the components may be mounted to the substrate <NUM> under the influence of heat and pressure. No additional solder pastes or sinter pastes are generally required. However, it is also possible to form an additional electrically conductive connection layer <NUM> between one or more of the components <NUM>, <NUM> and the first metallization layer <NUM>, similar to what has been described with respect to <FIG> above and as is schematically illustrated for the semiconductor body <NUM> on the left hand side of <FIG>. Such an electrically conductive connection layer <NUM> may be formed only regionally. In particular, electrically conductive connection layers <NUM> may only be formed in those areas that are arranged between the first metallization layer <NUM> and one of the components <NUM>, <NUM> mounted thereon. The material of the electrically conductive connection layer <NUM> fills any gaps or spaces between the respective ones of the nanowires <NUM> and may even further increase the strength of the connection formed between the first metallization layer <NUM> and the respective component <NUM>, <NUM>. This, however, is only optional. The strength of the connection is generally sufficient even without an additional electrically conductive connection layer <NUM>.

Optionally, as is schematically illustrated in <FIG>, the substrate arrangement may further comprise a second metallization layer <NUM> attached to a second side of the dielectric insulation layer <NUM> opposite the first side, and a second plurality of nanowires <NUM> arranged on a surface of the second metallization layer <NUM> that faces away from the dielectric insulation layer <NUM>, wherein the second plurality of nanowires <NUM> is evenly distributed over the entire surface of the second metallization layer <NUM> (the number of nanowires <NUM> per unit area is the same over the entire surface of the second metallization layer <NUM>), and each of the second plurality of nanowires <NUM> comprises a first end and a second end, wherein the first end of each of the second plurality nanowires <NUM> is inseparably connected to the surface of the second metallization layer <NUM>. The second plurality of nanowires <NUM> may be used to form a permanent connection between the substrate <NUM> and a heat sink or base plate <NUM>, for example.

As has been described above, forming nanowires <NUM> over a (large) section or over the entire surface area of the first metallization layer <NUM> allows using the substrate <NUM> very flexibly, as it is not limited to specific designs. The nanowires <NUM>, however, provide further advantages. As has been described with respect to <FIG> above, power semiconductor modules often comprise an encapsulant <NUM> configured to protect the components and electrical connections of the power semiconductor module, in particular the components arranged on the substrate <NUM> inside a housing, from certain environmental conditions and mechanical damage. A substrate arrangement comprising a substrate <NUM> with nanowires <NUM> formed thereon and an encapsulant <NUM> is schematically illustrated in <FIG>.

Claim 1:
A substrate arrangement comprises,
a first metallization layer (<NUM>);
a plurality of nanowires (<NUM>) arranged on a surface of the first metallization layer (<NUM>); and
at least one component (<NUM>, <NUM>) arranged on the first metallization layer (<NUM>) such that a first subset of the plurality of nanowires (<NUM>) is arranged between the first metallization layer (<NUM>) and the at least one component (<NUM>, <NUM>), wherein
the plurality of nanowires (<NUM>) is evenly distributed over a section of the surface area or over the entire surface area of the first metallization layer (<NUM>),
each of the plurality of nanowires (<NUM>) comprises a first end and a second end, wherein the first end of each of the plurality nanowires (<NUM>) is inseparably connected to the surface of the first metallization layer (<NUM>),
the second end of each nanowire of the first subset is inseparably connected to a surface of one of the at least one component (<NUM>, <NUM>) such that the first subset of nanowires (<NUM>) forms a permanent connection between the first metallization layer (<NUM>) and the at least one component (<NUM>, <NUM>),
the at least one component (<NUM>, <NUM>) comprises at least one semiconductor body (<NUM>),
the number of nanowires (<NUM>) comprised in the first subset of nanowires (<NUM>) is less than the number of nanowires (<NUM>) comprised in the plurality of nanowires (<NUM>), and
the substrate arrangement further comprises an encapsulant (<NUM>), wherein the encapsulant (<NUM>) consists of or includes a silicone gel and directly adjoins the second ends of a second subset of the plurality of nanowires (<NUM>) and fills any gaps and spaces between the nanowires of the second subset.