Patent Description:
Phase-change memory (PCM) is a type of non-volatile random-access memory. A PCM cell utilizes chalcogenide glass as a resistive element between electrodes. In operation, an electric current is passed through a heating element for each PCM cell, which heats the glass. The glass may then be quenched or held in a temperature range for a certain amount of time. Quenching the glass leaves the resistive element in an amorphous state with one resistance, while on the other hand, holding the glass within a temperature range gives the resistive element a crystalline state with a different resistance. A PCM cell may also be heated and cooled to achieve distinct intermediary states, thereby having the ability to hold multiple bits in a single cell, but the difficulties in programming cells in this way has prevented these capabilities from being implemented in other technologies with the same capability. <CIT> describes a method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) formed over and coupled to the heater resistor, and a top electrode coupled to the phase change material. <CIT> describes a phase-change material switch. The switch includes a first terminal that receives an input signal and a second terminal. The switch includes an actuation portion that receives a control signal in one of a first state to emit a first heat profile and a second state to emit a second heat profile. <CIT> describes a reconfigurable circuit comprising a phase-change material switch. The phase-change material switch includes an actuation portion configured to receive a control signal having one of a first state and a second state and to emit a first heat profile in response to the first state of the control signal and a second heat profile in response to the second state of the control signal. <CIT> describes a reduced parasitic capacitance radio frequency (RF) switch including a phase-change material (PCM) and a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM. A PCM contact connects a PCM routing interconnect with a passive segment of the PCM, wherein the passive segment extends outward and is transverse to the heating element.

According to an aspect of the present invention, there is provided a phase change memory (PCM) array. The PCM array may include a plurality of PCM cells. Each PCM cell in the plurality of PCM cells may include a top electrode, a resistive element, and a bottom electrode. The PCM array may also include a global heater surrounding the plurality of PCM cells having a thermally conductive material contacting each of the plurality of PCM cells. The global heater may be configured to receive an electric signal to heat the plurality of PCM cells simultaneously.

According to another aspect of the present invention, there is provided a method of forming a phase change memory array. The method may include forming a plurality of phase change memory (PCM) cells. Each PCM cell in the plurality of PCM cells may include a top electrode, a resistive element, and a bottom electrode. The method may also include forming a global heater having a thermally conductive material surrounding the plurality of PCM cells. The global heater may be configured to receive an electric signal to heat the plurality of PCM cells simultaneously.

Embodiments of the present invention may also include a method. The method may include signaling a global heater to heat a phase change memory (PCM) array, storing machine learning values in the PCM array by propagating a signal through PCM cells of the PCM array to change resistance of the PCM cells, signaling the global heater to cease heating the PCM array; and inferencing the PCM array.

Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the invention as defined by the claims. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present disclosure is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer "A" over layer "B" include situations in which one or more intermediate layers (e.g., layers "C" and "D") are between layer "A" and layer "B" as long as the relevant characteristics and functionalities of layer "A" and layer "B" are not substantially changed by the intermediate layer(s).

In addition, any numerical ranges included herein are inclusive of their boundaries unless explicitly stated otherwise.

For purposes of the description hereinafter, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms "overlying," "atop," "on top," "positioned on" or "positioned atop" mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements. It should be noted, the term "selective to," such as, for example, "a first element selective to a second element," means that a first element can be etched, and the second element can act as an etch stop.

For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.

In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography.

Deposition can be any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Another deposition technology is plasma enhanced chemical vapor deposition (PECVD), which is a process which uses the energy within the plasma to induce reactions at the wafer surface that would otherwise require higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the film's electrical and mechanical properties.

Removal/etching can be any process that removes material from the wafer. Examples include etch processes (either wet or dry), chemical mechanical planarization (CMP), and the like. One example of a removal process is ion beam etching (IBE). In general, IBE (or milling) refers to a dry plasma etch method which utilizes a remote broad beam ion/plasma source to remove substrate material by physical inert gas and/or chemical reactive gas means. Like other dry plasma etch techniques, IBE has benefits such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). In general, RIE uses chemically reactive plasma to remove material deposited on wafers. With RIE the plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the RIE plasma attack the wafer surface and react with it to remove material.

Semiconductor doping can be the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing ("RTA"). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device.

The present invention will now be described in detail with reference to the Figures.

<FIG> is a cross-sectional view of a semiconductor structure <NUM>, in accordance with one embodiment of the present invention. <FIG> provides only an illustration of one implementation and does not imply any limitations with regard to the different embodiments that may be implemented. Many modifications to the depicted embodiment may be made by those skilled in the art without departing from the scope of the invention as recited by the claims. The semiconductor structure <NUM> may include a phase change memory (PCM) array <NUM> having a plurality of PCM cells <NUM>. In the illustrated embodiment, only two PCM cells <NUM> are shown (i.e., a first PCM cell 104a and a second PCM cell 104b), but the PCM array <NUM> may include thousands or millions of PCM cells <NUM> for use in, for example, machine learning. In the illustrated embodiment, PCM cells <NUM> include a bottom wire <NUM>, bottom electrodes 108a, b, a substrate <NUM>, insulator <NUM>, PCM materials 114a, b, spacers 116a, b, global heater <NUM>, interlayer dielectric (ILD) <NUM>, top electrodes 122a, b, top wires 124a, b, and heater wire <NUM>.

In the illustrated embodiment, the bottom of bottom electrode <NUM> is in direct contact with and electrically connected to the top of bottom wire <NUM>, which can receive electrical signals from other components (not shown) of the integrated circuit. The bottom of the PCM materials 114a, b are in direct contact with and electrically and thermally connected to the top of the bottom electrodes 108a, b. The bottom of the top electrodes 122a, b are in direct contact with and electrically and thermally connected to the top of the PCM materials 114a, b. The bottom of the top wires 124a, b are in direct contact with and electrically connected to the top of the top electrodes 122a, b, and the top wires 124a, b can deliver electrical signals from the PCM cells 104a, b to other components (not shown) of the semiconductor structure <NUM>.

In the illustrated embodiment, the spacers 116a, b are in direct contact with and laterally surround the outer sides of PCM materials 114a, b and at least a portion of the top electrodes 122a, b. As such, the spacers <NUM> enclose the PCM materials 114a, b on all parallel sides in at least one direction (e.g., the sides that extend vertically, as shown in <FIG>). In some embodiments, the spacers 116a, b laterally surround all of the sides of top electrode <NUM>, although in other embodiments, the spacers 116a, b are coterminous with the top of PCM material <NUM>.

In the illustrated embodiment, the substrate <NUM>, the insulator <NUM>, and the ILD <NUM> structurally support and electrically isolate the other components of PCM cell <NUM>, selectively, and fill in the space therebetween, as appropriate. Thus, the outer side of the bottom electrodes 108a, b are in direct contact with and laterally surrounded by the insulator <NUM>, and the outer sides of the bottom wire <NUM> are in direct contact with and laterally surrounded by the substrate <NUM>. In the illustrated embodiment, a cross-sectional of the PCM cells 104a, b (i.e., looking down from above the PCM cells 104a, b) can be circular, although in other embodiments, it can be rectangular, square, oval, or any other suitable shape.

In the illustrated embodiment, the substrate <NUM>, the insulator <NUM>, and the ILD <NUM> may include dielectric (electrical insulating) material, such as, for example, silicon nitride (SiN), silicon oxide (SiO<NUM>), silicon nitride carbide (SiNC), or tetraethyl orthosilicate (TEOS). In some embodiments, all of the substrate <NUM>, the insulator <NUM>, and the ILD <NUM> may include the same material, and in other embodiments, different materials are used for some or all of the substrate <NUM>, the insulator <NUM>, and the ILD <NUM>. In addition, the spacers 116a, b may be fabricated using a reactive-ion-etching-resistant (RIER) material, such as, for example, aluminum nitride (AIN), aluminum oxide (Al<NUM>O<NUM>), or aluminum oxynitride (AlOxNy).

In the illustrated embodiment, the PCM materials 114a, b are composed essentially of a phase change material such as a germanium-antimony-tellurium (GST), gallium-antimony-tellurium (GaST), or silver-iridium-antimony-telluride (AIST) material, although other materials can be used as appropriate. Examples of other PCM materials can include, but are not limited to, germanium-tellurium compound material (GeTe), silicon-antimony-tellurium (Si-Sb-Te) alloys, gallium-antimony-tellurium (Ga-Sb-Te) alloys, germanium-bismuth-tellurium (Ge-Bi-Te) alloys, indium-tellurium (In-Se) alloys, arsenic-antimony-tellurium (As-Sb-Te) alloys, silver-indium-antimony-tellurium (Ag-In-Sb-Te) alloys, Ge-In-Sb-Te alloys, Ge-Sb alloys, Sb-Te alloys, Si-Sb alloys, Ge-Te alloys and combinations thereof. The PCM materials 114a, b may be undoped or doped (e.g., doped with one or more of oxygen (O), nitrogen (N), silicon (Si), carbon (C), or titanium (Ti)). The terms "composed essentially" and "consist essentially," as used herein with respect to materials of different layers, indicates that other materials, if present, do not materially alter the basic characteristics of the recited materials. For example, if the PCM materials 114a, b consist essentially of GST material, then the PCM materials 114a, b do not include other materials that materially alter the basic characteristics of the GST material.

In the illustrated embodiment, the bottom electrode 108a, b, the global heater <NUM>, and the top electrode <NUM> may include an electrically conductive material, such as metal or metallic compound. Specific examples may include titanium nitride (TiN) or tungsten (W). The bottom electrode <NUM> and the global heater <NUM> may include compounds of a higher resistance metal, such as, for example, titanium tungsten (TiW), tantalum nitride (TaN), or titanium aluminide (TiAl). The bottom electrodes 108a, b may also be fabricated with a relatively narrow cross-sectional area <NUM>, which focuses electrical current that is run through PCM cell <NUM>. This allows the bottom electrodes 108a, b to generate heat through resistive heating during a pulse of electricity, which can be used to selectively change the temperature of the PCM materials 114a, b, for example, above the crystallization temperature and the melting temperature of the PCM materials 114a, b. In addition, the bottom electrodes 108a, b may include multiple different electrically conductive materials that can be arranged in multiple layers.

The global heater <NUM> may include a thermally conductive material that improves the ability of the bottom electrodes 108a, b to change the temperature of the PCM material 114a, b by heating the PCM array <NUM> globally. The global heater <NUM> receives a current through the global heater wire <NUM>, and heats the insulator <NUM> and the spacers 116a, b due to the resistance of the metal compound. The heating may be carefully controlled such that the PCM materials 114a, b are heated to a temperature that is close to, but still below, the melting point of the PCM materials 114a, b. Therefore, rather than heating the PCM materials 114a, b from room temperature to the melting point, the bottom electrodes 108a, b are only required to raise the temperature a few degrees, which can be accomplished with a signal having a lower current. The lower current requirement means that the PCM cells 104a, b can perform at faster processing speeds and with reduced power consumption.

After the melting signal is passed through the PCM cells 104a, b, the PCM materials 114a, b will cool and solidify with resistance values that depends on the signal strength and the material properties of the PCM materials 114a, b. The semiconductor structure <NUM> may utilize these resistance values to operate the PCM cells 104a, b as a memory cell: for example by passing an electrical current pulse from the bottom electrodes 108a, b to the top electrode 122a, b to program the PCM cells 104a, b. This can be done at a variety of voltages and/or for a variety of durations to read or write a value on the PCM cells 104a, b. For example, to write, a high voltage can be used (e.g., <NUM> volt (V) to <NUM> V) for a short duration, which can cause the bottom electrodes 108a, b to locally heat the PCM materials 114a, b beyond its melting point. Once the flow of current ceases, PCM material <NUM> can cool down rapidly, which forms an amorphous zone in a process called "resetting". The creation of the amorphous zone can cause the electrical resistance across the PCM cells 104a, b to increase as compared to a solely polycrystalline configuration. These resistance values of the PCM cells 104a, b can be read without changing the state of the PCM materials 114a, b or the resistance value of the PCM cells 104a, b, for example, by sending a current pulse at a low voltage (e.g., <NUM> V) from bottom electrodes 108a, b to the top electrodes 122a, b.

In addition, the PCM materials 114a, b can be rewritten and returned back to a solely polycrystalline configuration by "setting" the PCM cells 104a, b. One way to rewrite the PCM materials 114a, b uses a high voltage electrical pulse (e.g., <NUM> V to <NUM> V) for a short period of time (e.g., <NUM> nanoseconds (ns)), which can cause the PCM materials 114a, b to heat up beyond its crystallization point but not to its melting point. Since the crystallization temperature is lower than the melting temperature, once the flow of current ceases, the PCM materials 114a, b can anneal and form crystals. Another way to rewrite the PCM materials 114a, b uses an electrical pulse with a relatively long trailing edge (e.g., <NUM> microsecond) (as opposed to a square pulse with a relatively short trailing edge on the order of nanoseconds) that is strong enough to heat the PCM materials 114a, b beyond its melting point, after which, the PCM materials 114a, b are cooled down slowly, allowing crystals to form. Either of these processes cause the electrical resistance across the PCM cells 104a, b to decrease as compared to having an amorphous zone. This new resistance value can then be read using current at a low voltage (e.g., <NUM> V) without changing the state of the PCM materials 114a, b or the resistance value of the PCM cell 104a, b.

In some embodiments, the melting temperature of the PCM materials 114a, b is about <NUM>. In some embodiments, the crystallization temperature of the PCM materials 114a, b is about <NUM>. In addition, the process of setting and resetting the PCM cells 104a, b can occur repeatedly, and in some embodiments, different zones with different resistances can be created in the PCM materials 114a, b (e.g., due to having different sizes of the amorphous zone and/or amounts of crystallization nuclei in the amorphous zone). This allows for the PCM cells 104a, b to have various distinct resistances that can be created by varying the resetting parameters. Thereby, if the PCM cells 104a, b are considered to represent information digits, these digits can be non-binary (as opposed to traditional bits). However, in some embodiments, the PCM cells 104a, b can be used as a bit by either having or not having a uniform zone in the PCM materials 114a, b. In such embodiments, the PCM cells 104a, b can have a high resistance (a. , low voltage output or "<NUM>") or low resistance (a. , high voltage output or "<NUM>").

<FIG> is a flowchart of workflow depicting a method for using a PCM array in training a machine learning (ML) algorithm. An ML lifecycle can be broken up into two main, distinct parts. The first is the training phase, in which an ML model is created or "trained" by running a specified subset of data into the model. ML inference is the second phase, in which the model is put into action on live data to produce actionable output. The data processing by the ML model is often referred to as "scoring," so one can say that the ML model scores the data, and the output is a score.

The method of the workflow is performed on a semiconductor structure having a global heater like the semiconductor structure <NUM> illustrated in <FIG>. In an embodiment, the workflow is performed by a training program that controls the signals to the wires (e.g., bottom wire <NUM>, top wires 124a, b, and global heater wire <NUM> of <FIG>) of the semiconductor structure. The training program signals a global heater to heat a phase change memory (PCM) array (block <NUM>). As described above, the training program may control the heating of the PCM array so that the PCM materials have a temperature that is close to, but not above, a melting temperature for the PCM materials. The PCM array may be heated to a training temperature of <NUM>, <NUM>, or other temperature close to the crystallization temperature of the PCM materials. In certain embodiments, the training temperature may be <NUM>, <NUM>, or other temperature close to the melting temperature (<NUM>) of the PCM materials.

The training program may also store ML values in the PCM array (block <NUM>). The stored ML values are derived from training the ML algorithm, and are stored by propagating signals through each cell in the PCM array to melt the PCM materials and change a resistance of the cell. Training is the process of teaching a ML algorithm to perform a desired artificial intelligence task (e.g., image classification, converting speech into text) by feeding it data, resulting in a trained deep learning model. During the training process, known data is fed to the algorithm, and the algorithm makes a prediction about what the data represents. Any error in the prediction is used to update the strength of the connections between the artificial neurons, as stored by the resistance values of the PCM array. As the training process continues, the resistance values are further adjusted until the ML algorithm makes predictions with sufficient accuracy. The resistance values of each PCM cell in the PCM array may be adjusted with a lower current/voltage than would be required if the global heater did not heat the PCM array to the training temperature.

When the training completes, the training program signals the global heater to cease heating the PCM array (block <NUM>). The heating is controlled by signals to the global heater wire, and when the training program ceases sending the heating signal, the global temperature of the semiconductor structure falls back down from the heated training temperature. The resistance values that are stored in the PCM array are more resistant to noise when the global temperature is reduced, due to the greater energy required to change the phase state of the PCM materials. With the lowered temperature, the training program inferences the PCM array (block <NUM>). ML inference is the process of running live data points into the machine learning algorithm to calculate an output. When the ML is running in production, it is often then described as artificial intelligence (Al) since it is performing functions similar to human thinking and analysis. Machine learning inference basically entails deploying a software application into a production environment, as the ML model is typically just software code that implements a mathematical algorithm.

<FIG> depict cross-sectional side views of a process of fabricating a semiconductor device <NUM>, in accordance with an embodiment of the present invention. <FIG> is a cross-sectional view of an embodiment of a semiconductor structure <NUM> in mid-manufacture, such as after formation of a plurality of PCM cells <NUM>. Each PCM cell in the plurality of PCM cells may include a top electrode <NUM>, a resistive element <NUM>, and a bottom electrode <NUM>. The PCM cells <NUM> are formed on a substrate <NUM> and a bottom wire <NUM>. The bottom electrodes <NUM> may be formed by etching a hole in an insulator <NUM> and filling in the hole with a high-resistivity metal. The high-resistivity metal may include, for example, titanium nitride, tantalum nitride, or combinations thereof. The resistive element <NUM> and the top electrode <NUM> may be formed as blanket layers followed by patterning and etching.

<FIG> is a cross-sectional view of the semiconductor structure <NUM> in mid-manufacture, such as after formation of spacers <NUM> surrounding the PCM cells <NUM>. The spacers <NUM> insulate and protect the PCM cells <NUM> during subsequent steps of the fabrication of the semiconductor structure <NUM>. The spacers <NUM> are formed using a deposition and etch back technique whereby a blanket of spacer material (e.g., silicon nitride) is deposited as a blanket layer over the semiconductor structure <NUM> and then etched from the more horizontal portions such that only the more vertical portions of the semiconductor structure <NUM>.

<FIG> is a cross-sectional view of the semiconductor structure <NUM> in mid-manufacture, such as after the formation of a global heater <NUM>. The global heater <NUM> may be formed of a high-resistivity metal that warms when a current is applied and flows through the global heater <NUM>. The high-resistivity metal may include, for example, titanium nitride, tantalum nitride, or combinations thereof. The global heater <NUM> may be formed by applying a blanket layer on the insulator <NUM>. After application of the blanket layer, the top surface of the global heater <NUM> may be recessed below a top surface of the spacers <NUM>.

<FIG> is a cross-sectional view of the semiconductor structure <NUM> in mid-manufacture, such as after patterning and etching away at least part of the layer of high-resistivity metal of the global heater <NUM>. Semiconductor lithography can be the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and gradually the conductors, insulators and selectively doped regions are built up to form the final device.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the invention as defined by the claims.

Claim 1:
A phase change memory, PCM, array, comprising:
a plurality of PCM cells (<NUM>), wherein each PCM cell in the plurality of PCM cells comprises a top electrode (122a, 122b), a resistive element (114a, 114b), and a bottom electrode (108a, 108b);
a global heater (<NUM>) comprising a thermally conductive materia contacting each of the plurality of PCM cells, wherein the global heater is configured to receive an electric signal to heat the plurality of PCM cells simultaneously
characterised by
the global heater (<NUM>) surrounding the plurality of PCM cells (<NUM>).