Patent Description:
Mobile communication devices may include a variety of components including circuit boards, integrated circuit (IC) devices and/or System-on-Chip (SoC) devices. These components can include processing circuits, user interface components, storage and other peripheral components that communicate through a serial bus. Many protocols used to operate a serial bus define specific roles and functions for the devices that are coupled through the serial bus. A device frequently referred to as a bus master or bus master device is configured to control timing of transmissions and to provide control signaling used to manage other devices coupled to the serial device. The other devices are frequently referred to as slave devices and are configured to respond to control signaling provided by the bus master device and to transmit or receive data in accordance with timing defined by the bus master device. Bus master devices may be referred to using alternative terms such as "bus controller," "bus host," "bus manager" or the like. Slave devices may be referred to using alternative terms such as "peripheral device," "subordinate device," "target device" or the like.

The serial bus may be operated in accordance with a standardized or proprietary protocol. In one example, a serial bus operated in accordance with an Inter-Integrated Circuit (I2C bus or I<NUM>C). The I2C bus was developed to connect low-speed peripherals to a processor, where the I2C bus is configured as a multidrop bus. A two-wire I2C bus includes a Serial Data Line (SDA) that carries a data signal, and a Serial Clock Line (SCL) that carries a clock signal.

In another example, Improved Inter-Integrated Circuit (I3C) protocols may be used to control operations on a serial bus. I3C protocols are defined by the Mobile Industry Processor Interface Alliance (MIPI) and derive certain implementation aspects from the I2C protocol. Original implementations of the I2C protocol supported data signaling rates of up to <NUM> kilobits per second (<NUM> kbps) in standard-mode operation, with more recent standards supporting speeds of <NUM> kbps in fast-mode operation, and <NUM> megabit per second (Mbps) in fast-mode plus operation. In some examples, a multi-master protocol may be used such that one or more devices can serve as a bus master or as a slave device in different transactions conducted over the serial bus.

As applications have become more complex, it has become desirable to increase performance and throughput provided by serial buses used to couple two or more devices while minimizing interconnections between IC devices.

The document <CIT> is disclosing a crossbar switch to determine access to slave ports with respect to master ports.

The invention is as defined by the independent claims <NUM>, <NUM> and <NUM>. Preferred embodiments are set out by the dependent claims.

Several aspects of the invention will now be presented with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements").

Devices that include multiple SoC and other IC devices often employ a serial bus to connect an application processor or other host device with modems and other peripherals. The serial bus may be operated in accordance with specifications and protocols defined by a standards body. In various examples illustrated in this disclosure, the serial bus may be operated in accordance with a standard or protocol that defines timing relationships between signals and transmissions, such as an I2C and/or I3C protocol. In certain applications, a multidrop serial bus may be used to connect a pair of devices in a point-to-point architecture. The point-to-point architecture may be employed when an application requires or calls for a secure connection between the pair of devices. In some instances, the use of a point-to-point architecture may yield performance benefits measurable in higher throughput, lower latency, and/or faster bus turnaround. However, the use of a point-to-point configuration increases the number of general purpose input/output (GPIOs) pads or pins necessary to support multiple point-to-point links, which can increase the complexity and cost of the SoC or other IC devices.

Certain aspects of this disclosure enable a host device or application processor to support point-to-point communication with multiple devices in accordance with an I2C or I3C protocol while restraining the number of additional GPIO pads or pins needed to implement the point-to-point architecture. In one aspect, multiple serial data links can be configured to share a single clock signal generated by the host device.

According to certain aspects, a serial data link may be used to interconnect electronic devices that are subcomponents of an apparatus such as a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a laptop, a notebook, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a global positioning system (GPS) device, a smart home device, intelligent lighting, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a game console, an entertainment device, a vehicle component, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), an appliance, a sensor, a security device, a vending machine, a smart meter, a drone, a multicopter, or any other similar functioning device.

<FIG> illustrates an example of an apparatus <NUM> that employs a data communication bus. The apparatus <NUM> may include a processing circuit <NUM> having multiple circuits or devices <NUM>, <NUM> and/or <NUM>, which may be implemented in one or more ASICs or in an SoC. In one example, the apparatus <NUM> may be a mobile communication device and the processing circuit <NUM> may include a processing device provided in an ASIC <NUM>, one or more peripheral devices <NUM>, and a transceiver <NUM> that enables the apparatus to communicate through an antenna <NUM> with a radio access network, a core access network, the Internet and/or another network.

The ASIC <NUM> may have one or more processors <NUM>, one or more modems <NUM>, on-board memory <NUM>, a bus interface circuit <NUM> and/or other logic circuits or functions. The processing circuit <NUM> may be controlled by an operating system having an application programming interface (API) layer that enables one or more processors <NUM> to execute software modules residing in the on-board memory <NUM> or other processor-readable storage <NUM> provided on the processing circuit <NUM>. The software modules may include instructions and data stored in the on-board memory <NUM> or processor-readable storage <NUM>. The ASIC <NUM> may access its on-board memory <NUM>, the processor-readable storage <NUM>, and/or storage external to the processing circuit <NUM>. The on-board memory <NUM>, the processor-readable storage <NUM> may include read-only memory (ROM) or random-access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. The processing circuit <NUM> may include, implement, or have access to a local database or other parameter storage that can maintain operational parameters and other information used to configure and operate the apparatus <NUM> and/or the processing circuit <NUM>. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, soft or hard disk, or the like. The processing circuit <NUM> may also be operably coupled to external devices such as the antenna <NUM>, a display <NUM>, operator controls, such as switches or buttons <NUM>, <NUM> and/or an integrated or external keypad <NUM>, among other components. A user interface module may be configured to operate with the display <NUM>, external keypad <NUM>, etc. through a dedicated communication link or through one or more serial data interconnects.

The processing circuit <NUM> may provide one or more buses 118a, 118b, <NUM> that enable certain devices <NUM>, <NUM>, and/or <NUM> to communicate. In one example, the ASIC <NUM> may include a bus interface circuit <NUM> that includes a combination of circuits, counters, timers, control logic and other configurable circuits or modules. In one example, the bus interface circuit <NUM> may be configured to operate in accordance with communication specifications or protocols. The processing circuit <NUM> may include or control a power management function that configures and manages the operation of the apparatus <NUM>.

<FIG> illustrates a system <NUM> in which multiple devices 204a-<NUM> are connected through a multidrop serial bus <NUM>. In one example, the devices 204a-<NUM> may be adapted or configured to communicate over the serial bus <NUM> in accordance with an I2C protocol. In some instances, one or more of the devices 204a-<NUM> may alternatively or additionally communicate using other protocols, including an I3C protocol, for example.

Communication over the serial bus <NUM> may be controlled by a bus master <NUM>, which is provided in an application processor <NUM> in the illustrated system <NUM>. In one mode of operation, the bus master <NUM> may be configured to provide a clock signal that controls timing of a data signal. The wire that carries the clock signal on a serial bus may be interchangeably referred to herein as "SCLK" or "SCL" and a wire that carries a data signal on a serial bus may be interchangeably referred to herein as "SDATA" or "SDA" or the like. In certain modes of operation, two or more of the devices 204a-<NUM> may be configured to exchange data encoded in symbols, where timing information is embedded in the transmission of the symbols.

<FIG> illustrates certain aspects of an apparatus <NUM> that includes multiple devices <NUM>, and <NUM><NUM>-<NUM>N coupled to a serial bus <NUM>. The devices <NUM> and <NUM><NUM>-<NUM>N may be implemented in one or more semiconductor IC devices, such as an applications processor, SoC or ASIC. In various implementations the devices <NUM> and <NUM><NUM>-<NUM>N may include, support or operate as a modem, a signal processing device, a display driver, a camera, a user interface, a sensor, a sensor controller, a media player, a transceiver, and/or other such components or devices. In some examples, one or more of the slave devices <NUM><NUM>-<NUM>N may be used to control, manage or monitor a sensor device. Communications between devices <NUM> and <NUM><NUM>-<NUM>N over the serial bus <NUM> is controlled by a bus master device <NUM>. Certain types of bus can support multiple bus master devices <NUM>.

In one example, a bus master device <NUM> may include an interface controller <NUM> that can manage access to the serial bus, configure dynamic addresses for slave devices <NUM><NUM>-<NUM>N and/or generate a clock signal <NUM> to be transmitted on a clock line <NUM> of the serial bus <NUM>. The bus master device <NUM> may include configuration registers <NUM> or other storage <NUM>, and other control logic <NUM> configured to handle protocols and/or higher-level functions. The control logic <NUM> may include a processing circuit such as a state machine, sequencer, signal processor or general-purpose processor. The illustrated bus master device <NUM> includes a transceiver <NUM> and line drivers/receivers 314a and 314b. The transceiver <NUM> may include receiver, transmitter and common circuits, where the common circuits may include timing, logic and storage circuits and/or devices. In one example, the transmitter encodes and transmits data based on timing in the clock signal <NUM> provided by a clock generation circuit <NUM>. Other timing clocks <NUM> may be used by the control logic <NUM> and other functions, circuits or modules.

At least one device <NUM><NUM>-<NUM>N may be configured to operate as a slave device on the serial bus <NUM> and may include circuits and modules that support a display, an image sensor, and/or circuits and modules that control and communicate with one or more sensors that measure environmental conditions. In one example, a slave device <NUM><NUM> configured to operate as a slave device may provide a control function, module or circuit <NUM> that includes circuits and modules to support a display, an image sensor, and/or circuits and modules that control and communicate with one or more sensors that measure environmental conditions. The slave device <NUM><NUM> may include configuration registers <NUM> or other storage <NUM>, control logic <NUM>, a transceiver <NUM> and line drivers/receivers 344a and 344b. The control logic <NUM> may include a processing circuit such as a state machine, sequencer, signal processor or general-purpose processor. The transceiver <NUM> may include receiver, transmitter and common circuits, where the common circuits may include timing, logic and storage circuits and/or devices. In one example, the transmitter encodes and transmits data based on timing in a clock signal <NUM> provided by clock generation and/or recovery circuits <NUM>. The clock signal <NUM> may be derived from a signal received from the clock line <NUM>. Other timing clocks <NUM> may be used by the control logic <NUM> and other functions, circuits or modules.

The serial bus <NUM> may be operated in accordance with I2C, I3C, RFFE, SPMI, or another protocols. At least one device <NUM>, <NUM><NUM>-<NUM>N may be configured to operate as both a bus master device and a slave device on the serial bus <NUM>. Two or more devices <NUM>, <NUM><NUM>-<NUM>N may be configured to operate as a bus master device on the serial bus <NUM>.

In some implementations, the serial bus <NUM> may be operated in accordance with an I3C protocol. Devices that communicate using the I3C protocol can coexist on the same serial bus <NUM> with devices that communicate using I2C protocols. The I3C protocols may support different communication modes, including a single data rate (SDR) mode that is compatible with I2C protocols. High-data-rate (HDR) modes may provide a data transfer rate between <NUM> megabits per second (Mbps) and <NUM> Mbps, and some HDR modes may be provide higher data transfer rates. I2C protocols may conform to de facto I2C standards providing for data rates that may range between <NUM> kilobits per second (kbps) and <NUM> Mbps. I2C and I3C protocols may define electrical and timing aspects for signals transmitted on the <NUM>-wire serial bus <NUM>, in addition to data formats and aspects of bus control. In some aspects, the I2C and I3C protocols may define direct current (DC) characteristics affecting certain signal levels associated with the serial bus <NUM>, and/or alternating current (AC) characteristics affecting certain timing aspects of signals transmitted on the serial bus <NUM>. In some examples, a <NUM>-wire serial bus <NUM> transmits data on a data line <NUM> and a clock signal on the clock line <NUM> In some instances, data may be encoded in the signaling state, or transitions in signaling state of the data line <NUM> and the clock line <NUM>.

Examples of data transfers, including control signaling, command and payload transmissions are provided by way of example. The examples illustrated relate to I2C and I3C communication for convenience. However, certain concepts disclosed herein are applicable to other bus configurations and protocols, including RFFE and SPMI configurations. Certain concepts are applicable to serial buses that are operated in accordance with various I3C protocols. In one example, these concepts may be implemented when the serial bus is operated in accordance with an I3C HDR double data rate (HDR-DDR) protocol, where timeslots may be defined in HDR-DDR words or in the number of clock pulses. In another example, these concepts may be implemented when the serial bus is operated in accordance with a protocol that supports multiple data lanes.

<FIG> includes timing diagrams <NUM> and <NUM> that illustrate the relationship between the SDA wire <NUM> and the SCL wire <NUM> when the serial bus is operated in an I2C or I3C mode. The first timing diagram <NUM> illustrates the timing relationship between the SDA wire <NUM> and the SCL wire <NUM> while data is being transferred over a conventionally configured I2C bus. The SCL wire <NUM> provides a series of pulses that can be used to sample data in the SDA wire <NUM>. The pulses (including the pulse <NUM>, for example) may be defined as the time during which the SCL wire <NUM> is determined to be in a high logic state at a receiver. When the SCL wire <NUM> is in the high logic state during data transmission, data on the SDA wire <NUM> is required to be stable and valid; the state of the SDA wire <NUM> is not permitted to change when the SCL wire <NUM> is in the high logic state.

In one example, specifications for conventional I2C protocol implementations (which may be referred to as "I2C Specifications") define a minimum duration <NUM> (tHIGH) of the high period of the pulse <NUM> on the SCL wire <NUM>. The I2C Specifications also define minimum durations for a setup time <NUM> (tsu) before occurrence of the pulse <NUM>, and a hold time <NUM> (tHold) after the pulse <NUM> terminates. The signaling state of the SDA wire <NUM> is expected to be stable during the setup time <NUM> and the hold time <NUM>. The setup time <NUM> defines a maximum time period after a transition <NUM> between signaling states on the SDA wire <NUM> until the arrival of the rising edge of the pulse <NUM> on the SCL wire <NUM>. The hold time <NUM> defines a minimum time period after the falling edge of the pulse <NUM> on the SCL wire <NUM> until a next transition <NUM> between signaling states on the SDA wire <NUM>. The I2C Specifications also define a minimum duration <NUM> for a low period (tLOW) for the SCL wire <NUM> The data on the SDA wire <NUM> is typically stable and/or can be captured for the duration <NUM> (tHIGH) when the SCL wire <NUM> is in the high logic state after the leading edge of the pulse <NUM>.

The second timing diagram <NUM> of <FIG> illustrates signaling states on the SDA wire <NUM> and the SCL wire <NUM> between data transmissions on a serial bus. Certain protocols provide for transmission of <NUM>-bit data (bytes) and <NUM>-bit addresses. A receiver may acknowledge transmissions by driving the SDA wire <NUM> to the low logic state for one clock period. The low signaling state represents an acknowledgement (ACK) indicating successful reception and a high signaling state represents a negative acknowledgement (NACK) indicating a failure to receive or an error in reception.

A start condition <NUM> is defined to permit the current bus master to signal that data is to be transmitted. The start condition <NUM> occurs when the SDA wire <NUM> transitions from high to low while the SCL wire <NUM> is high. The bus master initially transmits the start condition <NUM>, which may be also be referred to as a start bit, followed by a <NUM>-bit address of an I2C slave device with which it wishes to exchange data. The address is followed by a single bit that indicates whether a read or write operation is to occur. If no slave device responds, the bus master may interpret the high logic state of the SDA wire <NUM> as a NACK. The addressed slave device, if available, responds with an ACK bit after which the bus master and slave devices may exchange bytes of information in data frames. Bytes of data are serialized in the in data frames such that the most significant bit (MSB) is transmitted first. The transmission of the byte is completed when a stop condition <NUM> is transmitted by the bus master device. The stop condition <NUM> occurs when the SDA wire <NUM> transitions from low to high while the SCL wire <NUM> is high.

<FIG> includes diagrams <NUM> and <NUM> that illustrate timing associated with data transmissions on a serial bus operated in accordance with an I2C or I3C protocol. As illustrated in the first diagram <NUM>, an idle period <NUM> may occur between a stop condition <NUM> and a next start condition <NUM>. In the illustrated example, the SDA line <NUM> and SCL line <NUM> may be held and/or driven to a high voltage state during the idle period <NUM>. This idle period <NUM> may be prolonged and may result in reduced data throughput when the serial bus remains idle between the stop condition <NUM> and the next start condition <NUM>. In operation, a busy period <NUM> commences when the I2C bus master transmits a first start condition <NUM>, followed by data. The busy period <NUM> ends when the bus master transmits a stop condition <NUM> and the idle period <NUM> ensues. The idle period <NUM> ends when the next start condition <NUM> is transmitted.

The second timing diagram <NUM> illustrates a method by which the number of occurrences of an idle period <NUM> may be reduced. In the illustrated example, data is available for transmission before a first busy period <NUM> ends. The bus master device may transmit a repeated start condition <NUM> (Sr) rather than a stop condition. The repeated start condition <NUM> terminates the preceding data transmission and simultaneously indicates the commencement of a next data transmission. The state transition on the SDA wire <NUM> corresponding to the repeated start condition <NUM> is identical to the state transition on the SDA wire <NUM> for a start condition <NUM> that occurs after an idle period <NUM>. For both the start condition <NUM> and the repeated start condition <NUM>, the SDA wire <NUM> transitions from high to low while the SCL wire <NUM> is high. When a repeated start condition <NUM> is used between data transmissions, a first busy period <NUM> is immediately followed by a second busy period <NUM>.

<FIG> is a diagram <NUM> that illustrates an example of the timing associated with an address word sent to a slave device in accordance with certain I2C and/or I3C protocols. The address word is transmitted using drivers that are operated in an open-drain mode. In the example, a master device initiates the transaction with a start condition <NUM>, whereby the SDA wire <NUM> is driven from high to low while the SCL wire remains high. The master device then transmits a clock signal on the SCL wire <NUM>. The seven-bit address <NUM> of a slave device is then transmitted on the SDA wire <NUM>. The seven-bit address <NUM> is followed by a Write/Read command bit <NUM>, which indicates "Write" when low and "Read" when high. The slave device may respond in the next clock interval <NUM> with an acknowledgment (ACK) by driving the SDA wire <NUM> low. If the slave device does not respond, the SDA wire <NUM> is pulled high and the master device treats the lack of response as a NACK. The master device may terminate the transaction with a stop condition <NUM> by driving the SDA wire <NUM> from low to high while the SCL wire <NUM> is high. This transaction can be used to determine whether a slave device with the transmitted address coupled to the serial bus is in an active state.

<FIG> includes a timing diagram <NUM> that illustrates signaling on a serial bus when the serial bus is operated in an SDR mode of operation defined by I3C specifications. Data transmitted on a first wire of the serial bus, which may be referred to as the Data wire <NUM>, SDA or SDATA, may be captured using a clock signal transmitted on a second wire of the serial bus, which may be referred to as the Clock wire <NUM> or SCL. During data transmission, the signaling state <NUM> of the Data wire <NUM> (SDA) is expected to remain constant for the duration of the pulses <NUM>, defined as the interval in which the Clock wire <NUM> is at a high voltage level. Transitions on the Data wire <NUM> when the Clock wire <NUM> is at the high voltage level indicate a START condition <NUM>, a STOP condition <NUM> or a Repeated Start <NUM>.

On an I3C serial bus, a START condition <NUM> is defined to permit the current bus master to signal that data is to be transmitted. The START condition <NUM> occurs when the Data wire <NUM> transitions from high to low while the Clock wire <NUM> is high. The bus master may signal completion and/or termination of a transmission using a STOP condition <NUM>. The STOP condition <NUM> is indicated when the Data wire <NUM> transitions from low to high while the Clock wire <NUM> is high. A Repeated Start <NUM> may be transmitted by a bus master that wishes to initiate a second transmission upon completion of a first transmission. The Repeated Start <NUM> is transmitted instead of a STOP condition <NUM> and has the significance of a STOP condition <NUM> followed immediately by a START condition <NUM>. The Repeated Start <NUM> occurs when the Data wire <NUM> transitions from high to low while the Clock wire <NUM> is high.

<FIG> illustrates transmission of a Common Command Code (CCC) by the bus master. A CCC transmission <NUM> may occur when the serial bus is operated in an SDR mode of operation defined by I3C specifications. The bus master transmits an initiator <NUM> that may be a START condition or a Repeated Start prior to transmitting an address of a slave device, a command, and/or data. The initiator <NUM> may be followed in transmission by an address header <NUM> and a command code <NUM>. The command code <NUM> may, for example, cause the serial bus to transition to a desired mode of operation. In some instances, data <NUM> may be transmitted. The CCC transmission <NUM> may be followed by a terminator <NUM> that may be a STOP condition <NUM> or a Repeated Start <NUM>.

Certain serial bus interfaces support signaling schemes that provide higher data rates. In one example, I3C specifications define multiple high data rate (HDR) modes, including a high data rate, double data rate (HDR-DDR) mode in which data is transferred at both the rising edge and the falling edge of the clock signal. A bus master may transmit CCCs to switch the mode of operation of an I3C bus between SDR and HDR modes.

<FIG> includes an example of signaling <NUM> transmitted on the Data wire <NUM> and the Clock wire <NUM> to initiate a restart, exit and/or break from I3C HDR modes of communication. The signaling <NUM> includes an HDR Exit <NUM> that may be used to cause an HDR break or exit. The HDR Exit <NUM> commences with a falling edge <NUM> on the Clock wire <NUM> and ends with a rising edge <NUM> on the Clock wire <NUM>. While the Clock wire <NUM> is in a low signaling state, four pulses are transmitted on the Data wire <NUM>. I2C devices ignore the Data wire <NUM> when no pulses are provided on the Clock wire <NUM>.

In-band interrupts may be used to gain access to an I3C serial bus through an enumeration process in which a bus master device can identify slave devices coupled to the I3C serial bus. The enumeration process may be used during system initialization to assign dynamic addresses to slave devices. The bus master device may use system initialization to permit the bus master device to determine capabilities of the slave devices and/or to configure one or more of the slave devices. In-band interrupts may also be used by slave devices to transmit high-priority and/or low-latency messages.

A device other than the current bus master may assert an in-band interrupt during transmission of certain address fields to initiate an arbitration process that enables the asserting device to gain access to a serial bus. The serial bus may be operated in a mode in which data is transmitted on a data line in accordance with timing provided by a clock signal transmitted on a clock line. <FIG> illustrates a non-arbitrable address header <NUM> and an arbitrable address header <NUM> that may be transmitted on the SDA line <NUM> of the serial bus in accordance with I3C protocols. I3C protocols provide for different types of request to be transmitted using an I3C arbitrable address header I3C arbitrable address headers <NUM> can be transmitted after a START condition <NUM>. An address header <NUM> transmitted after a Repeated Start <NUM> is not arbitrable. A device may use an 13C arbitrable address header to assert an In-Band Interrupt, make a secondary bus master request, or indicate a hot-join request.

A non-arbitrable address header <NUM> is transmitted using push-pull drivers, while open-drain drivers are enabled during transmission of an arbitrable address header <NUM>. Rising edges <NUM> in a push-pull transmission provide a shorter bit interval <NUM> than the bit interval <NUM> available during an open-drain transmission, due to the slow rise time of the pulled-up edges <NUM> in a non-arbitrable address header <NUM>. In <FIG>, the bit intervals <NUM>, <NUM> are not depicted on a common scale.

A clock signal transmitted on the SCL line <NUM> provides timing information that is used by a slave device to control transmission of bits on the SDA line <NUM>, where the clock signal may be used by a receiving device for sampling and/or capturing bits of data transmitted on the SDA line <NUM>. A bus master device may read one or more registers on a slave device or secondary bus master device that wins arbitration. In conventional systems, the bus master device may provide clock pulses in a clock signal that have a period sufficient to successfully read the slowest possible device coupled to the serial bus. Each slave device has different operating characteristics and limitations that affect the response time of the slave device. In one example, the response time of a slave device may be affected by the physical distance between the slave device and the bus master device. In another example, the response time of a slave device may be affected by the processing capabilities of the slave device, where a slower controller, state machine or other processor in the slave device may delay responses transmitted by the slave device during in-band interrupt handling and/or processing.

In many examples, I2C, I3C and other such protocols are used to operate a two-wire data communication link as a serial, hierarchical, multi-master, multidrop , serial bus. I2C and I3C protocols support transactions in which data payloads bookended by bus management commands can be addressed to one or more devices coupled to the serial bus. In some examples, the I2C and I3C protocols may be used to operate a data communication link that has been configured to couple a pair of devices in a two-wire serial, point-to-point topology In one example, a point-to-point serial bus may be configured when one or more applications are expected to demand low latency access to the data communication link or when one or more applications are expected to generate high data throughput.

<FIG> illustrates a system <NUM> in which multiple devices 904a-<NUM> are configured to connect to a host device <NUM> using dedicated point-to-point serial buses. The host device <NUM> may include at least one application processor and multiple bus interfaces. In one example, each device 904a-<NUM> is coupled in a point-to-point configuration with a corresponding bus master 910a-<NUM> provided by the host device <NUM>. In some examples, the devices 904a-<NUM> may be adapted or configured to communicate with corresponding bus masters 910a-<NUM> in accordance with an I2C protocol or an I3C protocol. In these examples, each device 904a-<NUM> is coupled to a corresponding bus master 910a-<NUM> through respective pairs of wires configured as SCLK 906a-<NUM> and SDATA 908a-<NUM> in a point-to-point serial data communication link. In some examples, one or more of the devices 904a-<NUM> may communicate over their corresponding point-to-point data communication links using other protocols. In some examples, one of devices 904a-<NUM> may communicate with its corresponding or assigned bus master 910a-<NUM> using an I2C protocol while other devices communicate with their corresponding or assigned bus masters 910a-<NUM> using an I3C or other different protocol.

The system <NUM> of <FIG> and the system <NUM> of <FIG> may be indistinguishable from an application's perspective when lower-level the management and control functions are configured to adapt to the topology and configuration of the serial bus and to manage the addressing of devices coupled to each serial bus. However, applications that use a system <NUM> configured for multidrop operation may need to accommodate latencies associated with unavailability of the serial bus due to competition between multiple devices 204a-<NUM> for access to the serial bus <NUM>, as well as latencies attributable to bus busy conditions when transmissions are already in progress. Latencies affecting applications that use the system <NUM> configured for point-to-point operation may be limited to delays associated with competition between application for a single one of the devices 904a-<NUM>, as well as delays associated with transmissions in progress. The use of a point-to-point configuration, such as the system <NUM> illustrated in <FIG>, can be used to secure communication during transmission between sources of data and sinks or consumers of data. The use of a point-to-point configuration, such as illustrated in the system <NUM> in <FIG>, can provide maximized bandwidth and improved data throughput by reducing or eliminating overheads associated with bus arbitration and other bus management facilities required for multidrop operation. However, the use of a point-to-point configuration increases the required number of GPIO pads or pins, which can increase the complexity and cost of the host device <NUM>.

Certain aspects of this disclosure enable a host device or application processor to support point-to-point communication with multiple devices in accordance with an I2C or I3C protocol using a reduced number of GPIO pads or pins with respect to the system <NUM> of <FIG>. In one aspect, multiple serial data links can be configured to share a single clock signal generated by the host device.

<FIG> illustrates a system <NUM> that implements multiple point-to-point serial links configured to share a clock signal in accordance with the invention as defined in the independent claims. A host device <NUM> provides one or more clock signals that is provided as an internal clock signal <NUM> and transmitted over the shared or common SCLK <NUM> and used to control timing of data transmissions over each of the SDAs 1008a-<NUM> of the point-to-point serial links. The host device <NUM> may include at least one application processor and includes a clock generation circuit <NUM> that is coupled to SCLK <NUM>. The internal clock signal <NUM> provided by the clock generation circuit <NUM> is used by point-to-point bus master circuits 1010a-<NUM> to control timing of transmitters and receivers coupled to respective data lines (SDAs 1008a-<NUM>). The data lines are configured as point-to-point connections between the point-to-point bus master circuits 1010a-<NUM> and correspondent devices 1004a-<NUM>.

The clock generation circuit <NUM> is configured to provide a clock signal that is transmitted over SCLK <NUM> when a transaction is initiated for any of the correspondent devices 1004a-<NUM>. An active correspondent device 1004a-<NUM> uses the clock signal transmitted over SCLK <NUM> to control timing of a transmitter and receiver coupled to its SDA 1008a-<NUM>.

The clock generation circuit <NUM> may supplant or augment the clock generation functions provided in conventional bus masters when point-to-point mode is configured for the system <NUM>. In the illustrated example, each point-to-point bus master circuit 1010a-<NUM> provided in accordance with certain aspects of this disclosure can be used to manage communication between the host device <NUM> and one of the correspondent devices 1004a-<NUM>. Each point-to-point bus master circuit 1010a-<NUM> may generate control signaling that is transmitted over a corresponding SDA 1008a-<NUM> in accordance with timing provided by the internal clock signal <NUM> and the clock signal transmitted on SCLK <NUM>. Each point-to-point bus master circuit 1010a-<NUM> may request enablement of clock generation by the clock generation circuit <NUM> during transactions with the respective correspondent device 1004a-<NUM>.

In one example, a point-to-point bus master circuit 1010a-<NUM> may cooperate with data management circuits to format and frame data to be transmitted to a correspondent device 1004a-<NUM> over the respective SDA 1008a-<NUM>. In another example, a point-to-point bus master circuit 1010a-<NUM> may cooperate with data management circuits to format and frame data received from a correspondent device 1004a-<NUM>. In some instances, a point-to-point bus master circuit 1010a-<NUM> may cooperate with data management circuits that can monitor transactions and other communication activity to determine when clock generation by the clock generation circuit <NUM> is to be enabled.

<FIG> provides a schematic illustration of an architecture for a system <NUM> that implements multiple point-to-point serial links using a shared clock signal in accordance with certain aspects of this disclosure. In some aspects, the system <NUM> may correspond to the system <NUM> illustrated in <FIG>. An IC <NUM> operates as a host device <NUM> and may include an application processor or other processing element. The host device <NUM> generates or provides a clock signal <NUM> that is transmitted over a common SCLK <NUM> and that is configured to control timing of transmissions over the multiple point-to-point serial links. The clock signal <NUM> may be used internally by a peripheral control circuit <NUM> pad interface and/or a driver circuit <NUM> to control transmissions over the SDATAs 1124a-<NUM>. Each peripheral device 1122a-<NUM> is coupled to the IC <NUM> through SCLK <NUM> and a respective SDATA 1124a-<NUM>. In some examples, the point-to-point serial links are operated in accordance with an I2C or I3C protocol.

In the illustrated example, the host device <NUM> includes a peripheral control circuit <NUM> that serves as an interface between internal components or applications of the IC <NUM> and the physical point-to-point serial links. The peripheral control circuit <NUM> may include a clock generation circuit that provides the clock signal <NUM> used to control timing of transmissions over each SDATA 1124a-<NUM>. The peripheral control circuit <NUM> may include circuits or modules that implement or apply protocols selected for managing communication with the peripheral devices 1122a-<NUM> over the point-to-point serial links. In one example, the peripheral control circuit <NUM> may include circuits or modules configured to format and frame data to be transmitted to a peripheral device 1122a-<NUM> over the corresponding SDATA 1124a-<NUM>. In another example, the peripheral control circuit <NUM> may include circuits or modules configured to extract data from frames received from a peripheral device 1122a-<NUM> over the corresponding SDATA 1124a-<NUM>. The peripheral control circuit <NUM> may generate the START, STOP and/or Repeated START signaling defined by I2C protocols based on timing and state of the clock signal <NUM>. The peripheral control circuit <NUM> may enable clock generation circuits to support execution of asynchronous transactions that can be initiated with respect to multiple peripheral devices 1122a-<NUM>.

In some examples, the peripheral control circuit <NUM> includes interface circuits that couple the peripheral control circuit <NUM> to an internal system bus <NUM> through which internal components of the IC <NUM> interact with the point-to-point serial links. The peripheral control circuit <NUM> may also include or interact with a pad interface and driver circuit <NUM> to amplify, attenuate or otherwise buffer signals communicated across the physical edge <NUM> of the IC <NUM>. In one example, the pad interface and driver circuit <NUM> includes a set of transceivers <NUM>. Each transceiver in the set of transceivers <NUM> is coupled to a corresponding SDATA 1124a-<NUM> through an I/O pad 1112a-<NUM> and responds to the clock signal <NUM> and control signals provided by the peripheral control circuit <NUM>. The control signals may enable or disable a line driver or receiver. The control signals may select a high-impedance state for the corresponding I/O pad 1112a-<NUM>.

<FIG> illustrates certain aspects of a system <NUM> that implements multiple point-to-point serial links that share a clock signal in accordance with certain aspects of this disclosure. An interface control circuit <NUM> may implement various functions of the host device <NUM> illustrated in <FIG>. The interface control circuit <NUM> includes an I/O driver circuit <NUM> that corresponds to the pad interface and driver circuit <NUM> of <FIG>, a data control circuit <NUM> and a clock generation and control circuit <NUM>. In one aspect, the data control circuit <NUM> operates as a router that can direct a data stream received from each of a plurality of sources to a destination for the data stream. In the illustrated example, one or more applications 1204a-1204c may be configured as sources and/or sinks for data exchanged over multiple SDATA lines <NUM> that, together with a single SCLK <NUM>, provide the point-to-point serial links. The applications 1204a-1204c may communicate securely through corresponding data managers 1224a-1224c in the data control circuit <NUM>. The data managers 1224a-1224c may be configured or configurable to route or direct individual data streams to identified target devices 1206a-1206b. The data managers 1224a-1224c may operate as point-to-point bus masters on respective serial links. In the illustrated example, the target devices 1206a-1206b include a camera, a sensor and a secure touch panel, while the applications 1204a-1204c include handlers or controllers for the camera, sensor or secure touch panel. Other types of peripheral devices may be coupled through point-to-point serial links. In some examples, the target devices 1206a-1206b may include one or more application processors.

The clock generation and control circuit <NUM> may be configured to generate a clock signal <NUM> used to control timing of transmissions over each of the SDATA lines <NUM>. The clock signal <NUM> is used by the I/O driver circuit <NUM> and may be transmitted on SCLK <NUM>. The clock signal <NUM> may be included in a feedback clock signal <NUM> provided to the data control circuit <NUM>. The clock generation and control circuit <NUM> may respond to clock request signals <NUM> provided by the data control circuit <NUM> to determine when SCLK <NUM> is to be idled and when the clock signal <NUM> is to be actively transmitted on SCLK <NUM>. In some examples, each of the clock request signals <NUM> indicates that one of the data managers 1224a-1224c has received a command or request to read or write a corresponding target devices 1206a-1206b and/or that such a command or request is pending or being executed In one example, the clock generation and control circuit <NUM> may implement a voting scheme to determine when SCLK <NUM> is to be idled or activated. In another example, the clock generation and control circuit <NUM> may activate SCLK <NUM> when any of the data managers 1224a-1224c wishes to initiate a transaction. In another example, the clock generation and control circuit <NUM> may idle SCLK <NUM> after completion of a transaction. In another example, the clock generation and control circuit <NUM> may delay idling SCLK <NUM> for a fixed number of clock periods after completion of a transaction.

The I/O driver circuit <NUM> may encompass or include portions of the peripheral control circuit <NUM> and/or the pad interface and driver circuit <NUM> illustrated in <FIG>. In one example, the I/O driver circuit <NUM> may include circuits or modules configured to format and frame data to be transmitted to a target device 1206a-1206b over the corresponding SDATA <NUM>. In another example, the I/O driver circuit <NUM> may include circuits or modules configured to extract data from frames received from a target device 1206a-1206b over the corresponding SDATA <NUM>. In another example, the I/O driver circuit <NUM> may generate Start, Stop and/or Repeated Start signaling defined by I2C protocols based on timing and state of the clock signal <NUM>. In another example, the I/O driver circuit <NUM> may include, or interact with pad interface and driver circuits that are configured to amplify, attenuate or otherwise buffer signals communicated across the boundary of an IC.

In some examples, the data control circuit <NUM> can maintain separate channels for data streams between applications 1204a-1204c and respective target devices 1206a-1206b. The data managers 1224a-1224c in the data control circuit may be configured to use separate and distinct processing services, memory and registers to route data between the applications 1204a-1204c and identified target devices 1206a-1206b. It one example, the data control circuit <NUM> provides a protected, independent data path <NUM> for secure data transfer between a target device 1206c that includes a secure touch input device and a handling application 1204c. The protected, independent data path <NUM> can be effectively detached from the other data paths <NUM> through the interface control circuit <NUM>. In some instances, the protected, independent data path <NUM> can be established using encryption. In some examples, data streams may be originated by applications. In some instances, a data stream includes unidirectional data sourced from an originating application 1204a-1204c or target device 1206a-1206b.

According to one aspect, the clock signal <NUM> is generated and/or provided to SCLK <NUM> based on the start time required for a transmission initiated by data managers 1224a-1224c. The number of pulses provided on SCLK <NUM> or the duration of active transmission of the clock signal <NUM> over SCLK <NUM> may be determined by calculating or estimating the number of bits or bytes that are to be transferred during a transaction. In some instances, SCLK consolidation is performed. For example, the number of pulses provided on SCLK <NUM>, or the duration of active transmission of the clock signal <NUM> over SCLK <NUM> may reflect at least partially concurrent transmissions on two point-to-point serial links. For example, the total number of pulses provided on SCLK <NUM> may be calculated based on the number of pulses required for a first transmission on a first point-to-point serial link and the number of additional pulses required to complete a transmission on a second first point-to-point serial link that starts after the first transmission has started but before the first transmission has ended.

In some examples, SCLK consolidation may be accomplished using clock sensing and a mechanism that is based on voting. Clock sensing may involve monitoring the feedback clock signal <NUM> received from the clock generation and control circuit <NUM>. A voting circuit or module may respond to the request signals <NUM> generated by the data control circuit <NUM> to determine whether clock pulses are to be provided on SCLK <NUM>.

The example illustrated in <FIG> relates to a system that provides three data paths <NUM>, <NUM> through the interface control circuit <NUM> and over separate point-to-point serial links, where each point-to-point serial link includes one SDATA <NUM> and SCLK <NUM>. The concepts disclosed herein are not limited to three data paths <NUM>, <NUM>, and a lower or greater number of data paths may be provided to support a desired number of point-to-point serial links.

<FIG> is a state diagram <NUM> that illustrates certain aspects of the operation of each data manager 1224a-1224c illustrated in <FIG>. In some examples, the data manager 1224a-1224c for each data path can be in one two states. In a first state (illustrated as State-A <NUM>), a data manager 1224a-1224c can send or receive data. In one example, the data manager 1224a-1224c may request activation and/or transmission of the clock signal <NUM> on SCLK <NUM>. The data manager 1224a-1224c may operate as a conventional bus master while controlling and communicating with one slave device in accordance with an I2C or I3C protocol.

In a second state (illustrated as State-B <NUM>), a data manager 1224a-1224c is placed in an idle or wait state. In one example, the data manager 1224a-1224c may signal that it has no need for activation and/or transmission of the clock signal <NUM> on SCLK <NUM>. The clock signal <NUM> may be transmitted on SCLK <NUM> when one or more data managers 1224a-1224c is in an idle or wait state if another data manager 1224a-1224c is active. Accordingly, an inactive data manager 1224a-1224c may be configured to drive its SDATA to a high signaling state to maintain its associated slave device in an idle state.

<FIG> is a timing diagram <NUM> that illustrates certain aspects of control signaling that may be transmitted by a data manager using pulses or transitions on SDATA <NUM> while an active clock signal is being transmitted on SCLK <NUM>. The ability of a slave device to recognize a start condition <NUM> or a stop condition <NUM> can depend on timing of transitions <NUM>, <NUM> with respect to the next negative transition <NUM>, <NUM> in SCLK <NUM>.

The START condition <NUM> is provided by driving SDATA <NUM> to a low signaling state while SCLK <NUM> is in a high signaling state. For example, the START condition <NUM> may be validly signaled when the data manager provides a negative transition <NUM> in SDATA while SCLK <NUM> is in a high signaling state and a protocol-specified minimum time <NUM> before the next negative transition <NUM> in SCLK <NUM>. In one example, I2C protocols require that the negative transition <NUM> in SDATA occurs while SCLK <NUM> is in the high signaling state and at least <NUM> nanoseconds before SCLK <NUM> next transitions to the low signaling state. A STOP condition <NUM> is provided by driving SDATA <NUM> to a high signaling state while SCLK <NUM> is in a high signaling state. The STOP condition <NUM> may be validly signaled when the data manager provides a negative transition <NUM> in SDATA while SCLK <NUM> is in a high signaling state and a protocol-specified minimum time <NUM> before the next negative transition <NUM> in SCLK <NUM> is expected.

<FIG> is a timing diagram <NUM> that illustrates signaling on SCLK <NUM> while overlapping transmissions are transmitted on point-to-point serial links. A first transaction is initiated at a first point in time <NUM> when a START condition is transmitted on SDATA0 <NUM>. SDATA0 <NUM> provides a first point-to-point serial link in combination with SCLK <NUM>. If not already active, SCLK <NUM> becomes active <NUM> as the start condition is indicated on SDATA0 and remains active for at least the duration of the data transfer <NUM> associated with the first transaction. In the illustrated example, no other transaction is initiated before the completion of the first transaction and the second point in time <NUM> at which a STOP condition is provided. SCLK <NUM> enters an idle state <NUM> and SDATA0 <NUM> is maintained in a high signaling state while the first point-to-point serial link is in an idle state <NUM>.

A second point-to-point serial link is initially in an idle state <NUM> until, at a third point in time <NUM>, a START condition is transmitted on SDATA1 <NUM>. SDATA1 <NUM> is included in the second point-to-point serial link together with SCLK <NUM>. SCLK <NUM> leaves the idle state <NUM> and enters the active state <NUM> as the START condition is transmitted on SDATA1 <NUM>. SCLK <NUM> remains active for at least the duration of the data transfer <NUM> associated with a second transaction conducted over the second point-to-point serial link. In the illustrated example, a third transaction is initiated at a fourth point in time <NUM> before the completion of the second transaction. SDATA1 <NUM> may be maintained in a high signaling state <NUM> after the STOP condition provided at a fifth point in time <NUM>. The latter STOP condition does not terminate the active state <NUM> of SCLK <NUM> while the third transaction is in progress. The active state <NUM> of SCLK <NUM> is extended to include the data transfer <NUM> associated with the third transaction. SDATA1 <NUM> is maintained in a high signaling state after completion of the data transfer <NUM> associated with the second transaction.

The third transaction is conducted over a third point-to-point serial link. The third point-to-point serial link is initially in an idle state <NUM> until, at the fourth point in time <NUM>, a START condition is transmitted on SDATA2 <NUM>. SDATA2 <NUM> is included in the third point-to-point serial link together with SCLK <NUM>. SCLK <NUM> is already in the active state <NUM> as the START condition is transmitted on SDATA2 <NUM>. SCLK <NUM> remains active for at least the duration of the data transfer <NUM> associated with the third transaction. The active state <NUM> of SCLK <NUM> is extended to complete the data transfer <NUM> associated with the third transaction. SDATA1 <NUM> is maintained in a high signaling state after completion of the data transfer <NUM> associated with the second transaction. In the illustrated example, no other transaction is initiated before the completion of the third transaction and a STOP condition is provided at a sixth point in time <NUM>. SCLK <NUM> enters an idle state <NUM> and SDATA2 <NUM> is maintained in a high signaling state while the third point-to-point serial link is in an idle state <NUM>.

A common clock signal provided in accordance with certain aspects of this disclosure may be used to control data transmissions over a combination of point-to-point and multidrop serial data links. <FIG> illustrates a system <NUM> that includes multiple point-to-point serial links 1618a-1618e and a multidrop serial link <NUM> that are configured to share the clock signal <NUM> in accordance with certain aspects of this disclosure. In the illustrated example, a host device <NUM> provides an internal clock signal <NUM> that is used to control multiple bus master circuits 1610a-1610e, <NUM>. A clock signal representative of the internal clock signal <NUM> may be transmitted over a shared or common SCLK <NUM>. The clock signal transmitted on SCLK <NUM> is used to control timing of data transmissions over each SDA 1608a-1608e of the point-to-point serial links and over the SDA <NUM> of the multidrop serial link <NUM>. The host device <NUM> may include at least one application processor and a clock generation circuit <NUM> that is coupled to SCLK <NUM>. The internal clock signal <NUM> provided by the clock generation circuit <NUM> is used by point-to-point bus master circuits 1610a-1610e and the multidrop bus master circuit <NUM> to control timing of transmitters and receivers coupled to respective data lines (SDA 1608a-1608e and <NUM>). Some data lines (SDA 1608a-1608e) may be configured as point-to-point connections between the point-to-point bus master circuits 1610a-1610e and correspondent devices 1604a-1604e. In the illustrated example, one data line (SDA <NUM>) is configured as a multidrop link that couples the multidrop bus master circuit <NUM> to one or more multidrop correspondent devices 1624a-1624c.

According to one aspect, the point-to-point serial links 1618a-1618e may be configurable to support multidrop communication and the multidrop serial link <NUM> may be configurable to support point-to-point communication. In one example, the system <NUM> may be deployed for use in an IC device in which one or more of the bus master circuits 1610a-1610e, <NUM> are each coupled to a single slave device and one or more other bus master circuits 1610a-1610e, <NUM> are each coupled to multiple slave devices. In this example, the host device <NUM> may be configured during manufacture, assembly, system initialization and/or by application to define modes of operation for each of the bus master circuits 1610a-1610e, <NUM>. In some instances, each of the bus master circuits 1610a-1610e, <NUM> may be configured to automatically detect and implement a suitable mode of operation. In some instances, a common configuration for the bus master circuits 1610a-1610e, <NUM> inherently supports point-to-point and multidrop modes of operation using a shared or common SCLK <NUM>. In another example, the system <NUM> may be deployed for use in an IC device in which one or more bus master circuits 1610a-1610e and/or <NUM> is coupled to multiple slave devices that are capable or prone to entering an idle or sleep state, and the bus master circuits 1610a-1610e, <NUM> may be configured for a mode of operation that seamlessly supports transitions between point-to-point and multidrop communication modes.

The clock generation circuit <NUM> may be configured to provide a clock signal that is transmitted over SCLK <NUM> when a transaction is initiated for any of the correspondent devices 1604a-1604e, 1624a-1624c. An active correspondent device 1604a-1604e or 1624a-1624c may use the clock signal transmitted over SCLK <NUM> to control timing of a transmitter and receiver coupled to its SDA 1608a-1608e, <NUM>.

The clock generation circuit <NUM> may supplant or augment the clock generation functions provided in conventional bus masters. In the illustrated example, each point-to-point bus master circuit 1610a-1610e and multidrop bus master circuit <NUM> may be configured in accordance with certain aspects of this disclosure to manage communication between the host device <NUM> and correspondent devices 1604a-1604e or 1624a-1624c. Each point-to-point bus master circuit 1610a-1610e may generate control signaling that is transmitted over a corresponding SDA 1608a-1608e in accordance with timing provided by the internal clock signal <NUM> and the clock signal transmitted on SCLK <NUM>. Each multidrop bus master circuit <NUM> may generate multidrop-compatible control signaling that is transmitted over its SDA <NUM> in accordance with timing provided by the internal clock signal <NUM> and the clock signal transmitted on SCLK <NUM>. Each point-to-point bus master circuit 1610a-1610e may request enablement of clock generation by the clock generation circuit <NUM> during transactions with the respective correspondent device 1604a-1604e. Each multidrop bus master circuit <NUM> may request enablement of clock generation by the clock generation circuit <NUM> during transactions with multidrop correspondent devices 1624a-1624c.

In one example, a point-to-point bus master circuit 1610a-1610e or multidrop bus master circuit <NUM> may cooperate with data management circuits to format and frame data to be transmitted to a correspondent device 1604a-1604e or 1624a-1624c over the respective SDA 1608a-1608e or <NUM>. In another example, a point-to-point bus master circuit 1610a-1610e or multidrop bus master circuit <NUM> may cooperate with data management circuits to format and frame data to be received from a correspondent device 1604a-1604e or 1624a-1624c. In some instances, a point-to-point bus master circuit 1610a-1610e or multidrop bus master circuit <NUM> may cooperate with data management circuits that can monitor transactions and other communication activity to determine when clock generation by the clock generation circuit <NUM> is to be enabled.

<FIG> is a diagram illustrating an example of a hardware implementation for an apparatus <NUM> employing a processing circuit <NUM> that may be configured to perform one or more functions disclosed herein. In accordance with various aspects of the disclosure, an element, or any portion of an element, or any combination of elements as disclosed herein may be implemented using the processing circuit <NUM>. The processing circuit <NUM> may include one or more processors <NUM> that are controlled by some combination of hardware and software modules. Examples of processors <NUM> include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. The one or more processors <NUM> may include specialized processors that perform specific functions, and that may be configured, augmented or controlled by one of the software modules <NUM>. The one or more processors <NUM> may be configured through a combination of software modules <NUM> loaded during initialization, and further configured by loading or unloading one or more software modules <NUM> during operation. In various examples, the processing circuit <NUM> may be implemented using a state machine, sequencer, signal processor and/or general-purpose processor, or a combination of such devices and circuits.

In the illustrated example, the processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The bus <NUM> links together various circuits including the one or more processors <NUM>, and storage <NUM>. Storage <NUM> may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and/or processor-readable media. The bus <NUM> may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A bus interface <NUM> may provide an interface between the bus <NUM> and one or more transceivers <NUM>. A transceiver <NUM> may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in a transceiver <NUM>. Each transceiver <NUM> provides a means for communicating with various other apparatus over a transmission medium. Depending upon the nature of the apparatus <NUM>, a user interface <NUM> (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and may be communicatively coupled to the bus <NUM> directly or through the bus interface <NUM>.

One or more processors <NUM> in the processing circuit <NUM> may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the storage <NUM> or in an external computer-readable medium. The external computer-readable medium and/or storage <NUM> may include a non-transitory computer-readable medium. A non-transitory computer-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a "flash drive," a card, a stick, or a key drive), RAM, ROM, a programmable read-only memory (PROM), an erasable PROM (EPROM) including EEPROM, a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The computer-readable medium and/or storage <NUM> may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. Computer-readable medium and/or the storage <NUM> may reside in the processing circuit <NUM>, in the processor <NUM>, external to the processing circuit <NUM>, or be distributed across multiple entities including the processing circuit <NUM>. The computer-readable medium and/or storage <NUM> may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

The storage <NUM> may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules <NUM>. Each of the software modules <NUM> may include instructions and data that, when installed or loaded on the processing circuit <NUM> and executed by the one or more processors <NUM>, contribute to a run-time image <NUM> that controls the operation of the one or more processors <NUM>. When executed, certain instructions may cause the processing circuit <NUM> to perform functions in accordance with certain methods, algorithms and processes described herein.

Some of the software modules <NUM> may be loaded during initialization of the processing circuit <NUM>, and these software modules <NUM> may configure the processing circuit <NUM> to enable performance of the various functions disclosed herein. For example, some software modules <NUM> may configure internal devices and/or logic circuits <NUM> of the processor <NUM>, and may manage access to external devices such as the transceiver <NUM>, the bus interface <NUM>, the user interface <NUM>, timers, mathematical coprocessors, and so on. The software modules <NUM> may include a control program and/or an operating system that interacts with interrupt handlers and device drivers, and that controls access to various resources and processing services provided by the processing circuit <NUM>. The resources may include memory, processing time, access to the transceiver <NUM>, the user interface <NUM>, and so on. The processing services may include commonly used functions including memory access functions, stack and memory management functions, scheduling services and communication functions and features such as data packetizers, data interleavers, data encryption algorithms, buffers and the like.

<FIG> is a flowchart <NUM> illustrating method for data communication that may be performed at a host device that has been adapted in accordance with certain aspects of this disclosure. The host device may be configured to communicate with each of a plurality of peripheral devices through a point-to-point serial bus reserved for coupling the respective peripheral device to the host device. In one example, the peripheral devices include a serial bus interface configured for operation as a slave device in accordance with an I2C, I3C or other serial bus protocol.

At block <NUM>, the host device may configure a plurality of bus master circuits to control point-to-point communication with a corresponding slave device. At block <NUM>, the host device may determine a current operating mode for a serial bus clock signal based on the state of each bus master circuit. At block <NUM>, the host device may configure a clock generation circuit to provide pulses in the serial bus clock signal when the host device determines that the operating mode for the serial bus clock signal is an active mode at block <NUM>. The host device may determine that the operating mode for the serial bus clock signal is an active mode when one or more of the plurality of bus master circuits are in an active state and communicating with its corresponding slave device. At block <NUM>, the host device may configure a clock generation circuit to idle the serial bus clock signal when each of the plurality of bus master circuits is in an idle state. In one example, the serial bus clock signal may be idled by suppressing clock pulses on the serial bus clock signal or by refraining from generating such clock pulses. In some examples, serial bus protocols such as the I2C and I3C protocols provide that the serial bus clock signal be held in a high signaling state when the serial bus clock signal is idle. The serial bus clock signal may be transmitted over a common clock line to each slave device coupled to one of the plurality of bus master circuits. Each bus master circuit may be further configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal.

In some examples, each of a plurality of serial data I/O pads is configured to couple one of the plurality of bus master circuits to its corresponding slave device through a point-to-point data line. The host device may cause a first bus master circuit in the plurality of bus master circuits to maintain its corresponding serial data I/O pad in a high signaling state when the first bus master circuit is in the idle state and cause the first bus master circuit to initiate each transaction with its corresponding slave device by providing a start condition using signaling states of the serial data I/O pad and the common clock line. The host device may provide the start condition by driving the serial data I/O pad from the high signaling state to a low signaling state while the common clock line is in the high signaling state. The common clock line may be in the high signaling state when the serial bus clock signal is idle. The host device may provide the start condition by transmitting a pulse on the serial bus clock signal in implementations where the common clock line may be in the high signaling state while the pulse is on the serial bus clock signal, and then driving the data I/O pad from the high signaling state to the low signaling state at least a protocol-specified minimum time before a next negative transition in the serial bus clock signal.

In some examples, the host device may terminate each transaction with its corresponding slave device by providing a stop condition using signaling states of the serial data I/O pad and the common clock line. The host device may provide the stop condition by driving the serial data I/O pad from the low signaling state to the high signaling state while the common clock line is in a high signaling state.

In some examples, the host device may route a first data stream between a first application and a first slave device using a first bus master circuit in the plurality of bus master circuits hat is configured to control communication with the first slave device, route a second data stream between a second application and a second slave device using a second bus master circuit that is configured to control communication with the second slave device, and enforce data stream security by maintain separation between the first data stream and the second data stream. The separation between the first data stream and the second data stream may be maintained by providing separate processing services, memory or registers to route data for the respective applications and slave devices.

In some examples, the host device may configure at least one multidrop bus master circuit to control communication with a plurality of multidrop slave devices over a common data line in accordance with the timing provided by the serial bus clock signal.

In some examples, the host device may configure at least one of the plurality of bus master circuits to communicate with its corresponding slave device in accordance with an I2C protocol. The host device may configure at least one of the plurality of bus master circuits to communicate with its corresponding slave device in accordance with an I3C protocol.

<FIG> illustrates an example of a hardware implementation for an apparatus <NUM> employing a processing circuit <NUM>. In one example, the apparatus <NUM> is configured for operation as a host device that can support multiple point-to-point serial connections. The point-to-point serial connections may be operated in accordance with an I2C, I3C or other multidrop serial bus protocol. In some examples, the processing circuit <NUM> may be included in the systems <NUM>, <NUM>, <NUM> and/or <NUM> illustrated in <FIG> and <NUM>.

In some examples, the processing circuit <NUM> has a controller or processor <NUM> that includes one or more microprocessors, microcontrollers, digital signal processors, sequencers and/or state machines represented by the controller or processor <NUM>. The processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The bus <NUM> links together various circuits including the processor <NUM>, the modules or circuits <NUM>, <NUM>, <NUM> and <NUM> and the processor-readable storage medium <NUM>. The bus <NUM> may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The apparatus <NUM> may be coupled to multiple (N) data lines <NUM> that are used to implement multiple point-to-point serial links that each includes a serial bus clock line <NUM>. That is, each point-to-point serial link is includes the serial bus clock line <NUM> and one of the data lines <NUM>. The processing circuit <NUM> includes or is coupled to multiple (N) bus master circuits <NUM>, each of which controls operations over one of the point-to-point serial links. The bus master circuits <NUM> may be configured to operate its corresponding point-to-point serial link in accordance with a multidrop serial bus protocol such as an I2C or I3C protocol. The processing circuit <NUM> may include a clock generation circuit <NUM> that is configurable to provide a clock signal used by all of the bus master circuits <NUM> to control timing of transmissions over its corresponding point-to-point serial link.

The processor <NUM> is responsible for general processing, including the execution of software, code and/or instructions stored on the processor-readable storage medium <NUM>. The computer-readable storage medium may include a non-transitory storage medium. The software, when executed by the processor <NUM>, causes the processing circuit <NUM> to perform the various functions described supra for any particular apparatus. The computer-readable storage medium may be used for storing data that is manipulated by the processor <NUM> when executing software. The processing circuit <NUM> further includes at least one of the modules <NUM>, <NUM> and <NUM>. The modules <NUM>, <NUM> and <NUM> may be software modules running in the processor <NUM>, resident/stored in the processor-readable storage medium <NUM>, one or more hardware modules coupled to the processor <NUM>, or some combination thereof. The modules <NUM>, <NUM> and <NUM> may include microcontroller instructions, state machine configuration parameters, or some combination thereof. The processing circuit <NUM> may include other modules or circuits that provide various processing services, including services provided by timing functions, mathematical functions, encryption functions, memory management functions, among other functions.

In one configuration, the bus master circuits <NUM> include or are coupled to interface and driver circuits, including transceivers and line driver circuits each coupled to the serial bus clock line <NUM> or one of the data lines <NUM>. The processing circuit <NUM> may include modules or circuits <NUM> that manage, configure the bus master circuits <NUM> to implement one or more serial bus protocols. The processing circuit <NUM> may include modules or circuits <NUM> that manage dataflows between applications and peripheral devices coupled to the apparatus through the bus master circuits <NUM>. In some examples, the modules or circuits <NUM> that manage dataflows may implement or support the functions of the data control circuit <NUM> illustrated in <FIG>. In some instances, the modules or circuits <NUM> that manage dataflows may enable the processing circuit <NUM> to operate as a router that can direct a data stream received from each of a plurality of sources to a destination for the data stream.

In one example, the apparatus <NUM> includes a processor <NUM> and a plurality of bus master circuits <NUM>, each bus master circuit <NUM> being configured to control point-to-point communication with a corresponding slave device. The apparatus <NUM> may include a clock generation circuit <NUM> configured to provide pulses in a serial bus clock signal when one or more of the plurality of bus master circuits are in an active state and communicating with its corresponding slave device. The clock generation circuit <NUM> may be further configured to idle the serial bus clock signal when each of the plurality of bus master circuits is in an idle state. The serial bus clock signal may be transmitted over a common clock line <NUM> to each slave device coupled to one of the plurality of bus master circuits <NUM>. Each bus master circuit <NUM> may be further configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal.

In some examples, the apparatus <NUM> includes a plurality of serial data I/O pads. Each serial data I/O pad may be configured to couple one of the plurality of bus master circuits <NUM> to its corresponding slave device through a point-to-point data line. A first bus master circuit in the plurality of bus master circuits may be further configured to maintain its corresponding serial data I/O pad in a high signaling state when the first bus master circuit is in the idle state, and initiate each transaction with its corresponding slave device by providing a start condition using signaling states of the serial data I/O pad and the common clock line <NUM>. The start condition may be provided when the serial data I/O pad is driven from the high signaling state to the low signaling state while the common clock line <NUM> is in the high signaling state. The common clock line <NUM> may be in the high signaling state when the serial bus clock signal is idle. The common clock line <NUM> may be in the high signaling state when a pulse is provided in the serial bus clock signal. The first bus master circuit may be further configured to drive the data I/O pad from the high signaling state to the low signaling state at least a protocol-specified minimum time before a next negative transition in the serial bus clock signal.

In some examples, the first bus master circuit is further configured to terminate each transaction with its corresponding slave device by providing a stop condition using signaling states of the serial data I/O pad and the common clock line <NUM>. The stop condition may be provided when the serial data I/O pad is driven from a low signaling state to the high signaling state while the common clock line <NUM> is in a high signaling state.

In some examples, the apparatus <NUM> includes a data control circuit configured to route a first data stream between a first application and a first slave device using a first bus master circuit in the plurality of bus master circuits hat is configured to control communication with the first slave device, route a second data stream between a second application and a second slave device using a second bus master circuit that is configured to control communication with the second slave device, and enforce data stream security by maintain separation between the first data stream and the second data stream. The separation between the first data stream and the second data stream may be maintained by providing separate processing services, memory or registers to route data for the respective applications and slave devices.

In some examples, the apparatus <NUM> includes at least one multidrop bus master circuit configured to control communication with a plurality of multidrop slave devices over a common data line in accordance with the timing provided by the serial bus clock signal.

In one example, at least one of the plurality of bus master circuits <NUM> is further configured to communicate with its corresponding slave device in accordance with an I2C protocol or an I3C protocol.

In some examples, the processor-readable storage medium <NUM> may store, maintain or otherwise include code which, when executed by the processor <NUM>, causes the processor <NUM> to configure a plurality of bus master circuits <NUM> to control point-to-point communication with a corresponding slave device, and configure a clock generation circuit to provide pulses in a serial bus clock signal when one or more of the plurality of bus master circuits <NUM> are in an active state and communicating with its corresponding slave device and idle the serial bus clock signal when each of the plurality of bus master circuits <NUM> is in an idle state. The serial bus clock signal may be transmitted over a common clock line <NUM> to each slave device coupled to one of the plurality of bus master circuits <NUM>. Each bus master circuit <NUM> may be further configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal.

In some examples, each of a plurality of serial data I/O pads is configured to couple one of the plurality of bus master circuits <NUM> to its corresponding slave device through a point-to-point data line. The code may cause the processor <NUM> to cause a first bus master circuit in the plurality of bus master circuits to maintain its corresponding serial data I/O pad in a high signaling state when the first bus master circuit is in the idle state and cause the first bus master circuit to initiate each transaction with its corresponding slave device by driving the serial data I/O pad from the high signaling state to the low signaling state while the common clock line <NUM> is in the high signaling state. The common clock line <NUM> is in the high signaling state when the serial bus clock signal is idle or when a pulse is provided on the serial bus clock signal.

In some examples, the code further causes the processor <NUM> to terminate each transaction with its corresponding slave device by driving the serial data I/O pad from the low signaling state to the high signaling state while the common clock line <NUM> is in a high signaling state. The code may cause the processor <NUM> to route a first data stream between a first application and a first slave device using a first bus master circuit in the plurality of bus master circuits hat is configured to control communication with the first slave device, route a second data stream between a second application and a second slave device using a second bus master circuit that is configured to control communication with the second slave device, and enforce data stream security by maintain separation between the first data stream and the second data stream by providing separate processing services, memory or registers to route data for the respective applications and slave devices.

In certain examples, the code further causes the processor <NUM> to configure at least one multidrop bus master circuit to control communication with a plurality of multidrop slave devices over a common data line in accordance with the timing provided by the serial bus clock signal.

Claim 1:
An apparatus for data communication, comprising:
a plurality of bus master circuits (1010a-<NUM>), each bus master circuit being configured to control point-to-point communication with a corresponding slave device (1004a - <NUM>); and
a clock generation circuit (<NUM>) characterised in that
the clock generation circuit is configured to provide pulses in a serial bus clock signal when one or more of the plurality of bus master circuits are in an active state and communicating with its corresponding slave device, and further configured to idle the serial bus clock signal when each of the plurality of bus master circuits is in an idle state,
wherein the serial bus clock signal is transmitted over a common clock line (<NUM>) to each slave device coupled to one of the plurality of bus master circuits, and
wherein each bus master circuit is further configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal.