Patent Description:
Accordingly, it should be noted that these statements are to be read in this light, and not as admissions of any kind.

Virtualized datacenters are used extensively to provide digital services including web hosting, streaming services, remote computing, and more. Virtualized datacenters are highly scalable. Virtualization allows the creation of multiple simulated environments, operating systems (OS), or dedicated resources from a single, physical hardware system. Virtualization is implemented using software, such as a virtual machine manager (VMM), which is also sometimes referred to as a hypervisor, to manage software known as a "guest" or virtual machine (VM). A virtual machine is software that, when executed on appropriate hardware, creates an environment allowing for the abstraction of an actual physical computer system also referred to as a "host" or "host machine. " In other words, a virtual machine is software that simulates a physical computer system. There may be multiple virtual machines running on a single host machine. Like physical computer systems, each virtual machine may run its own guest operating system (OS) and applications, as well as interact with peripheral devices such as Peripheral Component Interconnect express (PCIe) devices.

Some peripheral devices may interact with virtual machines using Single Root-Input/Output Virtualization (SR-IOV) or Scalable Input/Output Virtualization (SIOV) and may access memory of the virtual machines using a form of Direct Memory Access (DMA) through Address Translation Service (ATS). When the peripheral device attempts to access memory of the virtual machine and there is a page fault, the peripheral device may wait while the host resolves the page fault. When the peripheral device is to perform a DMA to system memory, and if the page isn't mapped in by the OS, the peripheral device needs to first fault the page in, then obtain the translation, then restart the DMA. On high speed network devices, this can introduce substantial delay before the fault is resolved and restarting the DMA operation. One way to avoid page faults is to "pin" memory to the virtual machine. Pinned memory is part of a physical memory that is defined to be used exclusively by certain software, such as by a particular virtual machine. While this protects against page faults in the memory of the virtual machine, pinning the memory prevents other virtual machines from using the same underlying physical memory. Accordingly, this may limit the number of virtual machines that can be accommodated by a single host machine.

The article "<NPL> describes On-Demand-Paging in the context of InfiniBand. The article states that ODP has to appropriately handle packets that result in page faults and that RNICs rely on a retransmission mechanism without storing pending packets locally. Specifically, RNICs leverage RNR NAK for suspending senders of a packet that causes a page fault. Receivers do not have to store any dropped packets until RNR NAK reaches either because the reliability of InfiniBand guarantees to leave them on the sender side.

The subject-matter for which protection is sought is defined by the appended claims.

The terms "including" and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to "some embodiments," "embodiments," "one embodiment," or "an embodiment" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. Furthermore, the phrase A "based on" B is intended to mean that A is at least partially based on B. Moreover, the term "or" is intended to be inclusive (e.g., logical OR) and not exclusive (e.g., logical XOR). In other words, the phrase A "or" B is intended to mean A, B, or both A and B. Moreover, this disclosure describes various data structures, such as instructions for an instruction set architecture. These are described as having certain domains (e.g., fields) and corresponding numbers of bits. However, it should be understood that these domains and sizes in bits are meant as examples and are not intended to be exclusive. Indeed, the data structures (e.g., instructions) of this disclosure may take any suitable form.

This disclosure describes systems and methods that allow a peripheral device to perform direct memory access (DMA) to a pre-allocated page, communicating with the device driver to work with the OS to resolve a fault using the page that has the data. By using a configurable set of buffers to manage this pre-faulting, some of the latencies involved can be eliminated or reduced significantly.

These features may be implemented using any suitable integrated circuit devices that may be used as physical processing devices on which a virtual datacenter may run. The following architecture discussed below with respect to <FIG> is intended to represent one example that may be used.

<FIG> is a block diagram of a register architecture <NUM>, in accordance with an embodiment. In the embodiment illustrated, there are a number (e.g., <NUM>) of vector registers <NUM> that may be a number (e.g., <NUM>) of bits wide. In the register architecture <NUM>; these registers are referenced as zmm0 through zmmi. The lower order (e.g., <NUM>) bits of the lower n (e.g., <NUM>) zmm registers are overlaid on corresponding registers ymm. The lower order (e.g., <NUM> bits) of the lower n zmm registers that are also the lower order n bits of the ymm registers are overlaid on corresponding registers xmm.

Write mask registers <NUM> may include m (e.g., <NUM>) write mask registers (k0 through km), each having a number (e.g., <NUM>) of bits. Additionally or alternatively, at least some of the write mask registers <NUM> may have a different size (e.g., <NUM> bits). At least some of the vector mask registers <NUM> (e.g., k0) are prohibited from being used as a write mask. When such vector mask registers are indicated, a hardwired write mask (e.g., 0xFFFF) is selected and, effectively disabling write masking for that instruction.

General-purpose registers <NUM> may include a number (e.g., <NUM>) of registers having corresponding bit sizes (e.g., <NUM>) that are used along with x86 addressing modes to address memory operands. These registers may be referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15. Parts (e.g., <NUM> bits of the registers) of at least some of these registers may be used for modes (e.g., <NUM>-bit mode) that is shorter than the complete length of the registers.

Scalar floating-point stack register file (x87 stack) <NUM> has an MMX packed integer flat register file <NUM> is aliased. The x87 stack <NUM> is an eight-element (or other number of elements) stack used to perform scalar floating-point operations on floating point data using the x87 instruction set extension. The floating-point data may have various levels of precision (e.g., <NUM>, <NUM>, <NUM>, <NUM>, or more bits). The MMX packed integer flat register files <NUM> are used to perform operations on <NUM>-bit packed integer data, as well as to hold operands for some operations performed between the MMX packed integer flat register files <NUM> and the XMM registers.

Alternative embodiments may use wider or narrower registers. Additionally, alternative embodiments may use more, less, or different register files and registers.

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: <NUM>) a general purpose in-order core suitable for general-purpose computing; <NUM>) a high performance general purpose out-of-order core suitable for general-purpose computing; <NUM>) a special purpose core suitable for primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: <NUM>) a CPU including one or more general purpose in-order cores suitable for general-purpose computing and/or one or more general purpose out-of-order cores suitable for general-purpose computing; and <NUM>) a coprocessor including one or more special purpose cores primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: <NUM>) the coprocessor on a separate chip from the CPU; <NUM>) the coprocessor on a separate die in the same package as a CPU; <NUM>) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and <NUM>) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Example core architectures are described next, followed by descriptions of example processors and computer architectures.

<FIG> is a block diagram illustrating an in-order pipeline and a register renaming, out-of-order issue/execution pipeline according to an embodiment of the disclosure. <FIG> is a block diagram illustrating both an embodiment of an in-order architecture core and an example register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments. The solid lined boxes in <FIG> illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

In <FIG>, a pipeline <NUM> in the processor includes a fetch stage <NUM>, a length decode stage <NUM>, a decode stage <NUM>, an allocation stage <NUM>, a renaming stage <NUM>, a scheduling (also known as a dispatch or issue) stage <NUM>, a register read/memory read stage <NUM>, an execute stage <NUM>, a write back/memory write stage <NUM>, an exception handling stage <NUM>, and a commit stage <NUM>.

<FIG> shows a processor core <NUM> including a front-end unit <NUM> coupled to an execution engine unit <NUM>, and both are coupled to a memory unit <NUM>. The processor core <NUM> may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the processor core <NUM> may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front-end unit <NUM> includes a branch prediction unit <NUM> coupled to an instruction cache unit <NUM> that is coupled to an instruction translation lookaside buffer (TLB) <NUM>. The TLB <NUM> is coupled to an instruction fetch unit <NUM>. The instruction fetch unit <NUM> is coupled to a decode circuitry <NUM>. The decode circuitry <NUM> (or decoder) may decode instructions and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode circuitry <NUM> may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. The processor core <NUM> may include a microcode ROM or other medium that stores microcode for macroinstructions (e.g., in decode circuitry <NUM> or otherwise within the front-end unit <NUM>). The decode circuitry <NUM> is coupled to a rename/allocator unit <NUM> in the execution engine unit <NUM>.

The execution engine unit <NUM> includes a rename/allocator unit <NUM> coupled to a retirement unit <NUM> and a set of one or more scheduler unit(s) <NUM>. The scheduler unit(s) <NUM> represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) <NUM> is coupled to physical register file(s) unit(s) <NUM>. Each of the physical register file(s) unit(s) <NUM> represents one or more physical register files storing one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, statuses (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit(s) <NUM> includes the vector registers <NUM>, the write mask registers <NUM>, and/or the x87 stack <NUM>. These register units may provide architectural vector registers, vector mask registers, and general-purpose registers. The physical register file(s) unit(s) <NUM> is overlapped by the retirement unit <NUM> to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.).

The retirement unit <NUM> and the physical register file(s) unit(s) <NUM> are coupled to an execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution units <NUM> and a set of one or more memory access circuitries <NUM>. The execution units <NUM> may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform multiple different functions. The scheduler unit(s) <NUM>, physical register file(s) unit(s) <NUM>, and execution cluster(s) <NUM> are shown as being singular or plural because some processor cores <NUM> create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster. In the case of a separate memory access pipeline, a processor core <NUM> for the separate memory access pipeline is the only the execution cluster <NUM> that has the memory access circuitry <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest perform in-order execution.

The set of memory access circuitry <NUM> is coupled to the memory unit <NUM>. The memory unit <NUM> includes a data TLB unit <NUM> coupled to a data cache unit <NUM> coupled to a level <NUM> (L2) cache unit <NUM>. The memory access circuitry <NUM> may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit <NUM> in the memory unit <NUM>. The instruction cache unit <NUM> is further coupled to the level <NUM> (L2) cache unit <NUM> in the memory unit <NUM>. The L2 cache unit <NUM> is coupled to one or more other levels of caches and/or to a main memory.

By way of example, the register renaming, out-of-order issue/execution core architecture may implement the pipeline <NUM> as follows: <NUM>) the instruction fetch unit <NUM> performs the fetch and length decoding stages <NUM> and <NUM> of the pipeline <NUM>; <NUM>) the decode circuitry <NUM> performs the decode stage <NUM> of the pipeline <NUM>; <NUM>) the rename/allocator unit <NUM> performs the allocation stage <NUM> and renaming stage <NUM> of the pipeline; <NUM>) the scheduler unit(s) <NUM> performs the schedule stage <NUM> of the pipeline <NUM>; <NUM>) the physical register file(s) unit(s) <NUM> and the memory unit <NUM> perform the register read/memory read stage <NUM> of the pipeline <NUM>; the execution cluster <NUM> performs the execute stage <NUM> of the pipeline <NUM>; <NUM>) the memory unit <NUM> and the physical register file(s) unit(s) <NUM> perform the write back/memory write stage <NUM> of the pipeline <NUM>; <NUM>) various units may be involved in the exception handling stage <NUM> of the pipeline; and/or <NUM>) the retirement unit <NUM> and the physical register file(s) unit(s) <NUM> perform the commit stage <NUM> of the pipeline <NUM>.

The processor core <NUM> may support one or more instructions sets, such as an x86 instruction set (with or without additional extensions for newer versions); a MIPS instruction set of MIPS Technologies of Sunnyvale, CA; an ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, CA). Additionally or alternatively, the processor core <NUM> includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by multimedia applications to be performed using packed data.

It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof, such as a time-sliced fetching and decoding and simultaneous multithreading in INTEL® Hyperthreading technology.

While register renaming is described in the context of out-of-order execution, register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes a separate instruction cache unit <NUM>, a separate data cache unit <NUM>, and a shared L2 cache unit <NUM>, some processors may have a single internal cache for both instructions and data, such as, for example, a Level <NUM> (L1) internal cache, or multiple levels of the internal cache. In some embodiments, the processor may include a combination of an internal cache and an external cache that is external to the processor core <NUM> and/or the processor. Alternatively, some processors may use a cache that is external to the processor core <NUM> and/or the processor.

<FIG> illustrate more detailed block diagrams of an in-order core architecture. The processor core <NUM> includes one or more logic blocks (including other cores of the same type and/or different types) in a chip. The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed function logic, memory I/O interfaces, and other I/O logic, depending on the application.

<FIG> is a block diagram of a single processor core <NUM>, along with its connection to an on-die interconnect network <NUM> and with its local subset of the Level <NUM> (L2) cache <NUM>, according to embodiments of the disclosure. In one embodiment, an instruction decoder <NUM> supports the x86 instruction set with a packed data instruction set extension. An L1 cache <NUM> allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit <NUM> and a vector unit <NUM> use separate register sets (respectively, scalar registers <NUM> (e.g., x87 stack <NUM>) and vector registers <NUM> (e.g., vector registers <NUM>) and data transferred between them is written to memory and then read back in from a level <NUM> (L1) cache <NUM>, alternative embodiments of the disclosure may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

The local subset of the L2 cache <NUM> is part of a global L2 cache unit <NUM> that is divided into separate local subsets, one per processor core. Each processor core <NUM> has a direct access path to its own local subset of the L2 cache <NUM>. Data read by a processor core <NUM> is stored in its L2 cache <NUM> subset and can be accessed quickly, in parallel with other processor cores <NUM> accessing their own local L2 cache subsets. Data written by a processor core <NUM> is stored in its own L2 cache <NUM> subset and is flushed from other subsets, if necessary. The interconnection network <NUM> ensures coherency for shared data. The interconnection network <NUM> is bi-directional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. Each data-path may have a number (e.g.,<NUM>) of bits in width per direction.

<FIG> is an expanded view of part of the processor core in <FIG> according to embodiments of the disclosure. <FIG> includes an L1 data cache 106A part of the L1 cache <NUM>, as well as more detail regarding the vector unit <NUM> and the vector registers <NUM>. Specifically, the vector unit <NUM> may be a vector processing unit (VPU) (e.g., a vector arithmetic logic unit (ALU) <NUM>) that executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit <NUM>, numeric conversion with numeric convert units 122A and 122B, and replication with replication unit <NUM> on the memory input. The write mask registers <NUM> allow predicating resulting vector writes.

<FIG> is a block diagram of a processor <NUM> that may have more than one processor core <NUM>, may have an integrated memory controller unit(s) <NUM>, and may have integrated graphics according to embodiments of the disclosure. The solid lined boxes in <FIG> illustrate a processor <NUM> with a single core 54A, a system agent unit <NUM>, a set of one or more bus controller unit(s) <NUM>, while the optional addition of the dashed lined boxes illustrates the processor <NUM> with multiple cores 54A-N, a set of one or more integrated memory controller unit(s) <NUM> in the system agent unit <NUM>, and a special purpose logic <NUM>.

Thus, different implementations of the processor <NUM> may include: <NUM>) a CPU with the special purpose logic <NUM> being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 54A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination thereof); <NUM>) a coprocessor with the cores 54A-N being a relatively large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and <NUM>) a coprocessor with the cores 54A-N being a relatively large number of general purpose in-order cores. Thus, the processor <NUM> may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including <NUM> or more cores), an embedded processor, or the like. The processor <NUM> may be implemented on one or more chips. The processor <NUM> may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units <NUM>, and external memory (not shown) coupled to the set of integrated memory controller unit(s) <NUM>. The set of shared cache units <NUM> may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While a ring-based interconnect network <NUM> may interconnect the integrated graphics logic <NUM> (integrated graphics logic <NUM> is an example of and is also referred to herein as special purpose logic <NUM>), the set of shared cache units <NUM>, and/or the system agent unit <NUM>/integrated memory controller unit(s) <NUM> may use any number of known techniques for interconnecting such units. For example, coherency may be maintained between one or more cache units 142A-N and cores 54A-N.

In some embodiments, one or more of the cores 54A-N are capable of multithreading. The system agent unit <NUM> includes those components coordinating and operating cores 54A-N. The system agent unit <NUM> may include, for example, a power control unit (PCU) and a display unit. The PCU may be or may include logic and components used to regulate the power state of the cores 54A-N and the integrated graphics logic <NUM>. The display unit is used to drive one or more externally connected displays.

The cores 54A-N may be homogenous or heterogeneous in terms of architecture instruction set. That is, two or more of the cores 54A-N may be capable of execution of the same instruction set, while others may be capable of executing only a subset of a single instruction set or a different instruction set.

<FIG> are block diagrams of embodiments of computer architectures. These architectures may be suitable for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices. In general, a wide variety of systems or electronic devices capable of incorporating the processor <NUM> and/or other execution logic.

Referring now to <FIG>, shown is a block diagram of a system <NUM> in accordance with an embodiment. The system <NUM> may include one or more processors 130A, 130B that is coupled to a controller hub <NUM>. The controller hub <NUM> may include a graphics memory controller hub (GMCH) <NUM> and an Input/Output Hub (IOH) <NUM> (which may be on separate chips); the GMCH <NUM> includes memory and graphics controllers to which are coupled memory <NUM> and a coprocessor <NUM>; the IOH <NUM> couples input/output (I/O) devices <NUM> to the GMCH <NUM>. Alternatively, one or both of the memory and graphics controllers are integrated within the processor <NUM> (as described herein), the memory <NUM> and the coprocessor <NUM> are coupled to (e.g., directly to) the processor 130A, and the controller hub <NUM> in a single chip with the IOH <NUM>.

The optional nature of an additional processor 130B is denoted in <FIG> with broken lines. Each processor 130A, 130B may include one or more of the processor cores <NUM> described herein and may be some version of the processor <NUM>.

The memory <NUM> may be, for example, dynamic random-access memory (DRAM), phase change memory (PCM), or a combination thereof. For at least one embodiment, the controller hub <NUM> communicates with the processor(s) 130A, 130B via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection <NUM>.

In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like. In an embodiment, the controller hub <NUM> may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources of the processors 130A, 130B in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In some embodiments, the processor 130A executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor 130A recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor <NUM>. Accordingly, the processor 130A issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to the coprocessor <NUM>. The coprocessor <NUM> accepts and executes the received coprocessor instructions.

Referring now to <FIG>, shown is a more detailed block diagram of a multiprocessor system <NUM> in accordance with an embodiment. As shown in <FIG>, the multiprocessor system <NUM> is a point-to-point interconnect system, and includes a processor <NUM> and a processor <NUM> coupled via a point-to-point interface <NUM>. Each of processors <NUM> and <NUM> may be some version of the processor <NUM>. In one embodiment of the disclosure, processors <NUM> and <NUM> are respectively processors 130A and 130B, while coprocessor <NUM> is coprocessor <NUM>. In another embodiment, processors <NUM> and <NUM> are respectively processor 130A and coprocessor <NUM>.

Processors <NUM> and <NUM> are shown including integrated memory controller (IMC) units <NUM> and <NUM>, respectively. The processor <NUM> also includes point-to-point (P-P) interfaces <NUM> and <NUM> as part of its bus controller units. Similarly, the processor <NUM> includes P-P interfaces <NUM> and <NUM>. The processors <NUM>, <NUM> may exchange information via a point-to-point interface <NUM> using P-P interfaces <NUM>, <NUM>. As shown in <FIG>, IMCs <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM> that may be different portions of main memory locally attached to the respective processors <NUM>, <NUM>.

Processors <NUM>, <NUM> may each exchange information with a chipset <NUM> via individual P-P interfaces <NUM>, <NUM> using point-to-point interfaces <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> may optionally exchange information with the coprocessor <NUM> via a high-performance interface <NUM>. In an embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like.

A shared cache (not shown) may be included in either processor <NUM> or <NUM> or outside of both processors <NUM> or <NUM> that is connected with the processors <NUM>, <NUM> via respective P-P interconnects such that either or both processors' local cache information may be stored in the shared cache if a respective processor is placed into a low power mode.

The chipset <NUM> may be coupled to a first bus <NUM> via an interface <NUM>. In an embodiment, the first bus <NUM> may be a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

As shown in <FIG>, various I/O devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> that couples the first bus <NUM> to a second bus <NUM>. In an embodiment, one or more additional processor(s) <NUM>, such as coprocessors, high-throughput MIC processors, GPGPUs, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processors, are coupled to the first bus <NUM>. In an embodiment, the second bus <NUM> may be a low pin count (LPC) bus. Various devices may be coupled to the second bus <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage unit <NUM> such as a disk drive or other mass storage device which may include instructions/code and data <NUM>, in an embodiment. Further, an audio I/O <NUM> may be coupled to the second bus <NUM>. Note that other architectures may be deployed for the multiprocessor system <NUM>. For example, instead of the point-to-point architecture of <FIG>, the multiprocessor system <NUM> may implement a multi-drop bus or other such architectures.

Referring now to <FIG>, shown is a block diagram of a system <NUM> in accordance with an embodiment. Like elements in <FIG> and <FIG> contain like reference numerals, and certain aspects of <FIG> have been omitted from <FIG> to avoid obscuring other aspects of <FIG>.

<FIG> illustrates that the processors <NUM>, <NUM> may include integrated memory and I/O control logic ("IMC") <NUM> and <NUM>, respectively. Thus, the IMC <NUM>, <NUM> include integrated memory controller units and include I/O control logic. <FIG> illustrates that not only are the memories <NUM>, <NUM> coupled to the IMC <NUM>, <NUM>, but also that I/O devices <NUM> are also coupled to the IMC <NUM>, <NUM>. Legacy I/O devices <NUM> are coupled to the chipset <NUM> via interface <NUM>.

Referring now to <FIG>, shown is a block diagram of a SoC <NUM> in accordance with an embodiment. Similar elements in <FIG> have like reference numerals. Also, dashed lined boxes are optional features included in some SoCs <NUM>. In <FIG>, an interconnect unit(s) <NUM> is coupled to: an application processor <NUM> that includes a set of one or more cores 54A-N that includes cache units 142A-N, and shared cache unit(s) <NUM>; a system agent unit <NUM>; a bus controller unit(s) <NUM>; an integrated memory controller unit(s) <NUM>; a set or one or more coprocessors <NUM> that may include integrated graphics logic, an image processor, an audio processor, and/or a video processor; a static random access memory (SRAM) unit <NUM>; a direct memory access (DMA) unit <NUM>; and a display unit <NUM> to couple to one or more external displays. In an embodiment, the coprocessor(s) <NUM> include a special-purpose processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, an embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the disclosure may be implemented as computer programs and/or program code executing on programmable systems including at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Program code, such as data <NUM> illustrated in <FIG>, may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices. For purposes of this application, a processing system includes any system that has a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system. The program code may also be implemented in an assembly language or in a machine language. In any case, the language may be a compiled language or an interpreted language.

One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium that represents various logic within the processor that, when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as "IP cores," may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that make the logic or processor.

Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic cards, optical cards, or any other type of media suitable for storing electronic instructions.

Accordingly, embodiments of the embodiment include non-transitory, tangible machine-readable media containing instructions or containing design data, such as designs in Hardware Description Language (HDL) that may define structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert instructions to one or more other instructions to be processed by the core. The instruction converter may be implemented on processor, off processor, or part on and part off processor.

<FIG> is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the disclosure. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or any combinations thereof. <FIG> shows a program in a high-level language <NUM> may be compiled using an x86 compiler <NUM> to generate x86 binary code <NUM> that may be natively executed by a processor with at least one x86 instruction set core <NUM>. The processor with at least one x86 instruction set core <NUM> represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (<NUM>) a substantial portion of the instruction set of the Intel x86 instruction set core or (<NUM>) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler <NUM> represents a compiler that is operable to generate x86 binary code <NUM> (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core <NUM>.

Similarly, <FIG> shows the program in the high-level language <NUM> may be compiled using an alternative instruction set compiler <NUM> to generate alternative instruction set binary code <NUM> that may be natively executed by a processor without at least one x86 instruction set core <NUM> (e.g., a processor with processor cores <NUM> that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, CA). An instruction converter <NUM> is used to convert the x86 binary code <NUM> into code that may be natively executed by the processor without an x86 instruction set core <NUM>. This converted code is not likely to be the same as the alternative instruction set binary code <NUM> because an instruction converter capable of this is difficult to make; however, the converted code may accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter <NUM> represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code <NUM>.

Software running on a processing device such as discussed above with reference to <FIG> may be used to create a virtualized datacenter, which may provide web hosting, streaming services, remote computing, and more. As mentioned above, virtualization allows the creation of multiple simulated environments, operating systems (OS), or dedicated resources from a single, physical hardware system. <FIG> illustrates one example use case of a virtualized datacenter <NUM>, in which a client device <NUM> may interact with a virtual machine (VM) <NUM> that is running on a processing device <NUM>. The virtualized data center <NUM> may provide on-demand computing for any suitable number of client devices <NUM>. Additional virtual machines (VMs) <NUM> may be brought online or dismissed in response to changing demands for computing resources. While the virtual machine (VM) <NUM> shown in the virtualized datacenter <NUM> of <FIG> is illustrated interfacing with a client device <NUM>, virtual machines (VMs) <NUM> may interface with other types of clients, including other virtual machines (VMs) <NUM> or applications.

The virtual machine (VM) <NUM> may interact with any suitable number and types of peripheral devices <NUM>. In the particular example shown in <FIG>, the peripheral device <NUM> is a smart network interface card (NIC) that allows the client device <NUM> to communicate with the virtual machine (VM) <NUM>. Other example peripheral devices <NUM> may include any suitable Peripheral Component Interconnect express (PCIe) devices, including a network interface card (NIC), a storage device such as non-volatile memory (e.g., an NVM Express device), a cryptographic engine (e.g., Look-Aside Crypto), a compression engine, or a remote direct memory access (RDMA) device, among others.

The peripheral device <NUM> may access memory <NUM> of the virtual machine (VM) <NUM> using a form of Direct Memory Access (DMA) through Address Translation Service (ATS). Because the virtualized datacenter <NUM> uses on-demand paging, which will be discussed in greater detail below, even if an attempt to access the memory <NUM> of the virtual machine (VM) <NUM> results in an I/O page fault, it may be detected and recovered from gracefully.

Because the on-demand paging of this disclosure reduces the negative impacts of I/O page faults, the virtualized datacenter <NUM> may undertake several strategies that may substantially increase efficiency even though doing so may increase a likelihood of page faults. For example, as shown in <FIG>, the virtualized datacenter <NUM> may perform live migration of virtual machines (VMs) <NUM>. The term "live migration" refers to moving a running virtual machine (VM) <NUM> between different processing devices <NUM> without disconnecting the client device <NUM> or application from communication with the virtual machine (VM) <NUM> for long enough to be noticeable.

In <FIG>, a virtual machine (VM) <NUM> has been selected to move from a processing device 306A to a processing device 306B in the virtualized datacenter <NUM>. There are many reasons to potentially move a virtual machine (VM) <NUM>, such as to consolidate the virtual machines (VMs) <NUM> to reduce the number of processing devices <NUM> that are currently running, to perform maintenance on a processing device or its peripheral devices, to group the virtual machine (VM) <NUM> with other complementary virtual machines (VMs) <NUM>, to provide access to different physical resources, and so forth. <FIG> illustrates a start of live migration. Here, memory <NUM> and the state of the virtual machine (VM) <NUM> (e.g., CPU state, registers, network connectivity details) may begin to be copied from the processing device 306A to the processing device 306B. At this point, the virtual machine (VM) <NUM> remains running on the processing device 306A.

As shown in <FIG>, a final state of the virtual machine (VM) <NUM> may be copied from the processing device 306A to the processing device 306B and the virtual machine (VM) <NUM> may briefly enter a "blackout period. " At this point, the virtual machine (VM) <NUM> is briefly disconnected from the client device <NUM>. As shown in <FIG>, the blackout period may be substantially reduced by reactivating the virtual machine (VM) <NUM> on the processing device 306B before all the memory <NUM> has been transferred from the processing device 306A to the processing device 306B. This allows the client device <NUM> or other application with which the virtual machine (VM) <NUM> is interacting to avoid lengthy downtime. However, because the memory <NUM> is still being copied over, it is possible for a peripheral device <NUM> to attempt to access memory that is not yet on the processing device 306B, resulting in an I/O page fault.

Once all the memory <NUM> has been transferred over to the processing device 306B, as shown in <FIG>, the virtual machine (VM) <NUM> may be understood to be fully migrated. The processing device 306A may no longer be running the virtual machine (VM) <NUM>. In some cases, to save power, the processing device 306A may be powered down or otherwise taken offline.

Another strategy that may increase efficiency at the cost of more page faults is to overcommit the memory <NUM>. As utilization varies and more or fewer virtual machines (VMs) <NUM> are active on a processing device <NUM>, it may be useful to dynamically overcommit memory across the virtual machines (VMs) <NUM>. In a simplified example shown in <FIG>, there may be multiple virtual machines (VMs) 304A and 304B residing on a processing device <NUM>. The virtual machine (VM) 304A may have memory 310A and the virtual machine (VM) 304B may have memory 310B. From the perspective of the respective virtual machines (VMs) 304A and 304B, the memory 310A and 310B appears to correspond directly to an equivalent amount of physical memory located in a physical memory device. However, in this example at least some of the memory 310A and 310B may correspond to the same physical memory. This may enable more virtual machines (VMs) <NUM> to operate on a single processing device <NUM>, but at the cost of potential page faults if one virtual machine (VM) <NUM> (e.g., the virtual machine (VM) 304A) attempts to access a page of memory (e.g., memory 310A) that corresponds to physical memory currently in use by another virtual machine (VM) <NUM> (e.g., the virtual machine (VM) 304B). With dynamic random-access memory (DRAM) costs becoming more and more of the overall total cost of operation, providing this flexibility to overcommit VM memory space enables a path to better overall utilization of a system's total DRAM capacity and an increased VM density on a given processing device <NUM>.

<FIG> illustrates a block diagram of a processing device <NUM> in communication with a peripheral device <NUM> showing the various components that provide on-demand device-assisted paging with any suitable number of virtual machines (VMs) <NUM> running on the processing device <NUM>. The processing device <NUM> may represent any suitable processor or CPU. As used in this disclosure, the terms "processor" and "CPU" refer to a device that can execute instructions encoding arithmetic, logical, or I/O operations to carry out the systems and methods of this disclosure. For example, the processing device <NUM> may include an arithmetic logic unit (ALU), a control unit, and registers, and may operate in the manner discussed above with reference to <FIG>. The processing device <NUM> includes processing core(s) <NUM> that may run software such as an operating system (OS) upon which other software components may run. These other software components will be discussed further below. They include the virtual machine (VM) <NUM>, a virtual machine manager (VMM) <NUM>, as well as a variety of drivers to enable the virtual machine (VM) <NUM> to interact with devices and applications such as the peripheral device <NUM> and to gracefully recover from I/O page faults.

The processing device <NUM> may be a single-core processor having one processing core <NUM> that processes a single instruction pipeline or a multi-core processor having multiple processing cores <NUM> that may simultaneously process multiple instruction pipelines. The processing device <NUM> may include various commercially available processors, including without limitation Intel® Atom®, Celeron®, Core (<NUM>) Duo®, Core i3, Core i5, Core i7, Itanium®, Pentium®, Xeon® or Xeon Phi® processors, ARM processors, and similar processors. In some cases, the processing device <NUM> may be implemented as a single integrated circuit, two or more integrated circuits, or may be a component of a multi-chip module (e.g., in which individual microprocessor dies are included in a single integrated circuit package and hence share a single socket). The processing device <NUM> may be part of a computing system such as a datacenter server, a desktop computer, a tablet computer, a laptop computer, a netbook, a notebook computer, a personal digital assistant (PDA), a workstation, a cellular telephone, a mobile computing device, an Internet appliance or any other type of computing device. In some cases, the processing device <NUM> may be used in a system-on-a-chip (SoC) system or system-in-package (SiP) system.

In one example, the processing device <NUM> is a disaggregated server. A disaggregated server is a server that breaks up components and resources into subsystems and connects them through network connections (e.g., network sleds). Disaggregated servers can be adapted to changing storage or compute loads as needed without replacing or disrupting an entire server for an extended period of time. A server could, for example, be broken into modular compute, I/O, power, and storage modules that can be shared among other nearby servers. The processing device <NUM> may include any other suitable components to support the operation of the virtual machine (VM) <NUM>, such as a communication bus between components of the processing device <NUM>, a graphics controller, local cache memory (e.g., L4, L3, L2, L1 cache), and other supporting circuitry and software.

Virtualization is implemented using software, such as the virtual machine manager (VMM) <NUM>, which may monitor and manage the virtual machine (VM) <NUM>. The virtual machine manager (VMM) <NUM> may represent a hypervisor such as such as Kernel-based virtual machine (KVM), Xen, VMware ESXI, or the like. The virtual machine manager (VMM) <NUM> may abstract a physical layer of the processing device <NUM>, presenting this abstraction to the virtual machines (VMs) <NUM> (sometimes referred to as the "guests"). The virtual machine manager (VMM) <NUM> may provide a virtual operating platform for the virtual machines (VMs) <NUM>. In some implementations, more than one virtual machine manager (VMM) <NUM> may support different virtual machines (VMs) <NUM>. Each virtual machine (VM) <NUM> may be a software implementation of a machine that executes programs as though it were an actual physical machine. For example, the virtual machine (VM) <NUM> illustrated in <FIG> may include a guest memory management unit (MMU) <NUM> that may manage guest memory <NUM>. A guest device driver <NUM> may allow the virtual machine (VM) <NUM> to interface with the peripheral device <NUM>. A virtual input/output memory management unit (vIOMMU) <NUM> may act as a virtual model of a guest input/output memory management unit (IOMMU).

The peripheral device <NUM> may interact with each virtual machine (VM) <NUM> as if it were a physical machine using a protocol engine (PE) <NUM>. The protocol engine (PE) <NUM> may operate as a direct memory access (DMA) engine for a virtual function (VF) or physical function (PF) of the peripheral device <NUM>. There may be multiple protocol engines <NUM> to enable interaction with multiple virtual machines (VMs) <NUM>. The protocol engines <NUM> may interface with the guest device drivers <NUM> through a host interface (HIF) <NUM>. The protocol engines <NUM> may directly access hardware components of the processing device <NUM>, such as to read from or write to the physical memory corresponding to the guest memory <NUM> of the virtual machine (VM) <NUM>, using a virtualization management protocol on the processing device <NUM> such as a virtualization technology-direct (VT-d) driver <NUM> that allows authorized technology direct I/O access.

To provide one particular example, the peripheral device <NUM> may receive incoming data <NUM> into an external interface <NUM> that may be destined for the virtual machine (VM) <NUM>. In some cases, the peripheral device <NUM> may be a network interface card (NIC) that receives networking data into a local area network (LAN) interface. The protocol engine (PE) <NUM> corresponding to the virtual machine (VM) <NUM> that the data <NUM> is intended for may transfer the data <NUM> into the guest memory <NUM> of that virtual machine (VM) <NUM> using direct memory access (DMA).

Before continuing, it should be understood that, while data is stored at a physical memory address representing an actual location in physical memory (e.g., an actual physical location on a memory device <NUM> that may be accessed through a memory controller <NUM>, managed by a memory management unit (MMU) <NUM>), software running on the processing device <NUM> and the peripheral device <NUM> may operate using a virtual memory address that is translated to the physical memory address when the memory is accessed. A structure known as a translation lookaside buffer (TLB) stores recently used mappings of virtual memory addresses to their corresponding physical memory addresses. There may be multiple TLBs used by the processing device <NUM> and peripheral device <NUM> for memory for specific domains. The peripheral device <NUM> may maintain a local cache of recently accessed mappings between virtual memory addresses and physical memory addresses for I/O access in the form of a device translation lookaside buffer (devTLB) <NUM> and associated page tables <NUM>. The device translation lookaside buffer (devTLB) <NUM> and associated page tables <NUM> may be used and maintained by a device memory management unit (devMMU) <NUM>.

To transfer the data <NUM> to the guest memory <NUM> of the virtual machine (VM) <NUM>, the device translation lookaside buffer (devTLB) <NUM> may rapidly translate the virtual memory address to its corresponding physical memory address. The protocol engine (PE) <NUM> may use DMA to store the data <NUM> in the physical memory of the processing device <NUM> corresponding to the guest memory <NUM> of the virtual machine (VM) <NUM>.

If the device translation lookaside buffer (devTLB) <NUM> does not currently have an entry corresponding to the request, however, this may be referred to as a "cache miss" or "TLB miss. " A TLB miss handling process is used to obtain the corresponding entry by conducting a search known as a "page walk" through the page tables <NUM>. If the page walk does not identify the physical memory address that corresponds to the requested virtual memory address, the peripheral device <NUM> may request the translation from the processing device <NUM>. For example, an address translation engine (ATE) <NUM> may send an Address Translation Service (ATS) message requesting the translation.

In the processing device <NUM>, I/O memory management blocks <NUM> may respond to the ATS request from the peripheral device <NUM>. The I/O memory management blocks <NUM> may include an input/output translation lookaside buffer (IOTLB) <NUM> that can be used by an input/output memory management unit (IOMMU) <NUM> to provide the physical memory address that corresponds to a desired virtual memory address indicated by the ATS request. If the requested translation is in the input/output translation lookaside buffer (IOTLB) <NUM>, the physical memory address may be provided in response and the protocol engine (PE) <NUM> may use DMA to store the data <NUM> in the proper physical address on the processing device <NUM>, making it accessible to the virtual machine (VM) <NUM> by way of its guest memory <NUM>. If the input/output translation lookaside buffer (IOTLB) <NUM> does not currently have an entry corresponding to the request, however, a TLB miss handling process is used to obtain the corresponding entry by conducting a page walk through page tables <NUM>. If the page walk is successful, an ATS response may provide the translation to the peripheral device <NUM>, which may store the translation as an entry in the device translation lookaside buffer (devTLB) <NUM>.

When the protocol engine (PE) <NUM> is able to obtain the translation from virtual memory to physical memory (from the device translation lookaside buffer (devTLB) <NUM> or the I/O memory management blocks <NUM>), the protocol engine (PE) <NUM> may use DMA to write the data <NUM> to the proper physical address. The protocol engine (PE) <NUM> may populate entries to a work queue <NUM> for a protocol engine (PE) driver <NUM>, which may populate a completion queue <NUM> to indicate that the memory transfer is complete. Different protocol engines <NUM> may have different respective sets of work queue <NUM>, protocol engine (PE) driver <NUM>, and completion queue <NUM>.

If a translation is unavailable even after a page walk (e.g., the page walk does not identify the physical memory address that corresponds to the requested virtual memory address), the result is a page fault. A corresponding ATS response may be returned that indicates that a page fault has occurred. In the case of a page fault, the location in memory to which the data <NUM> is intended does not currently exist. The peripheral device <NUM> could discard the data <NUM> while awaiting the resolution of the page fault on the processing device <NUM>, but this may introduce substantial latency since the data <NUM> may need to be retransmitted into the peripheral device <NUM> after the page fault is resolved. The peripheral device <NUM> could alternatively store the data <NUM> temporarily in a local buffer on the peripheral device <NUM> while awaiting the resolution of the page fault on the processing device <NUM>, but this could increase the cost of the peripheral device <NUM> because this would entail adding large enough buffers to store the data <NUM>. Indeed, in some cases, the peripheral device <NUM> may not have enough memory to store the data <NUM>.

These challenges may be reduced or eliminated by performing on-demand device-assisted paging. When an indication of a page fault is received at the peripheral device <NUM>, the protocol engine (PE) <NUM> transfers the data by DMA to pre-allocated fault buffers of a fault buffer queue <NUM> on the processing device <NUM>. The protocol engine (PE) <NUM> by way of the address translation engine (ATE) <NUM> also writes an entry into an I/O page fault (IPF) queue <NUM> that indicates a descriptor for a DMA operation that has encountered a page fault. The fault buffer queue <NUM> provides a set of descriptors and data buffers for temporarily storing data from faulting DMA writes until a page fault has been resolved. A pointer to these buffers is provided to steer the faulting payloads for temporarily storing payloads while the page fault is being resolved. The I/O page fault (IPF) queue <NUM> is a queue with entries that contain a descriptor for a DMA operation that has encountered a page fault. The descriptor contains information for an address translation engine on-demand paging (ATE ODP) driver <NUM> to successfully resolve the page fault. Logically, this is similar to PCIe Address Translation Service - Page Request Interface (ATS-PRI) as a mechanism to request the host for page fault resolution.

The fault buffer queue <NUM> and the I/O page fault (IPF) queue <NUM> may be memory that is "pinned" and therefore not subject to a page fault. They may reside in host memory that is pinned in the host operating system and, as such, able to store data that is sent by multiple different protocol engines <NUM> and/or for multiple different virtual machines (VMs) <NUM>. In some embodiments, these may, additionally or alternatively, be pinned in guest memory <NUM> of each virtual machine (VM) <NUM> or for a subset of the virtual machines (VMs) <NUM>, and thus may be accessible to one protocol engine (PE) <NUM> and/or for that virtual machine (VM) <NUM>. Transferring the data <NUM> to buffers corresponding to the fault buffer queue <NUM> does not immediately place the data <NUM> into the guest memory <NUM>, but does allow the data <NUM> to avoid being discarded or being stored for an extended time on the peripheral device <NUM>.

The fault buffer queue <NUM>, I/O page fault (IPF) queue <NUM>, and address translation engine on-demand paging (ATE ODP) driver <NUM> may support multiple protocol engines <NUM> associated with multiple virtual machines (VMs) <NUM>. <FIG> shows an example where there are two work queue entries <NUM> and <NUM> (e.g., descriptors) associated to different protocol engines (PEs) <NUM> represented as PE A and PE X, respectively. The work queue entries <NUM> and <NUM> may be used for a DMA write I/O operation (e.g., LAN receive). In the example of <FIG>, the work queue entry <NUM> includes a scatter gather list (SGL) with four scatter gather elements (SGEs) <NUM>, <NUM>, <NUM>, and <NUM> and the work queue entry <NUM> includes a scatter gather list (SGL) with four scatter gather elements (SGEs) <NUM>, <NUM>, <NUM>, and <NUM>. In the example shown, the scatter gather element (SGE) <NUM> and scatter gather element (SGE) <NUM> in the work queue entry <NUM> of PE A encounter a write fault and the scatter gather element (SGE) <NUM> in the work queue entry <NUM> of PE X encounters a write fault. These faults can occur in arbitrary order and therefore may be posted to the I/O page fault (IPF) queue <NUM> in an interleaved fashion as I/O page fault (IPF) queue <NUM> entries <NUM>, <NUM>, and <NUM>. Note that there may be a <NUM>:<NUM> correlation between each I/O page fault (IPF) queue <NUM> entry <NUM>, <NUM>, and <NUM> (e.g., each page fault) and an associated fault buffer queue <NUM> entry <NUM>, <NUM>, and <NUM> pointing to the data buffers where data corresponding to the page fault have been temporarily stored.

<FIG> is a flowchart <NUM> describing a process for device-assisted on-demand paging. The flowchart <NUM> starts as the peripheral device <NUM> attempts to store data in memory of the processing device <NUM>, but memory lookup has failed. Thus, the protocol engine (PE) <NUM> of peripheral device <NUM> that experienced memory lookup failure may issue an Address Translation Service (ATS) translation request through the address translation engine (ATE) <NUM> (process block <NUM>). In response, the host input/output memory management unit (IOMMU) <NUM> may look for the translation in the input/output translation lookaside buffer (IOTLB) <NUM> and, finding it missing, perform a page walk. If the page walk shows that the page is not in the I/O memory, the host input/output memory management unit (IOMMU) <NUM> may respond with an ATS completion message indicating a page fault (e.g., success with R=W=<NUM>) (process block <NUM>). Based on the ATS translation response indicating a page fault, the protocol engine (PE) <NUM> performs a direct memory access (DMA) operation to store the data into a pre-allocated fault buffer (block <NUM>). The protocol engine (PE) <NUM> also issues (e.g., by way of the address translation engine (ATE) <NUM>) an indication of an I/O page fault (IPF) with a descriptor indicating the location of the buffer into which the data is stored to the address translation engine on-demand paging (ATE ODP) driver <NUM> (process block <NUM>). The address translation engine on-demand paging (ATE ODP) driver <NUM> may receive an event to handle a read or write fault with the associated buffer and may issue a request to the host MMU and/or VT-D driver <NUM> to handle the page fault (process block <NUM>). For example, the address translation engine on-demand paging (ATE ODP) driver <NUM> may issue a Page Request Service (PRS) request using a non-blocking call to handle_mm_fault(). The address translation engine on-demand paging (ATE ODP) driver <NUM> may pass (Physical RID (Bus, Device, Function), PASID, Page-Group Index, Permissions for access) via the host MMU and/or VT-D driver <NUM>, or via an IOMMU kernel application programming interface (API). Here, it may be noted that the VT-D driver <NUM> may expect the same format as the PRS message, as defined in the PCIe Specification Chapter <NUM>.

Upon receipt of the request to handle the page fault, the host may handle the page fault (process block <NUM>). This may be done in a variety of ways. In some embodiments, the input/output memory management unit (IOMMU) <NUM> may be used to resolve the page fault. For example, the IOMMU driver may walk page-tables and determine if the protocol engine (PE) <NUM> is owned by a guest (e.g., a virtual machine (VM) <NUM>) or the host (e.g., a host operating system running on the processing device <NUM>), and whether this is a first level fault. If the page fault is a guest fault, the IOMMU may inject a fake PRS message into a virtual page request queue (vPRQ) of the virtual input/output memory management unit (vIOMMU) <NUM> of the virtual machine (VM) <NUM>, collect the results after the virtual machine (VM) <NUM> returns a page response, and send the result to the address translation engine on-demand paging (ATE ODP) driver <NUM>. If the fault is a shared virtual memory (SVM) fault, the host operating system running on the processing device <NUM> may perform a native page fault resolution and return the results back to the address translation engine on-demand paging (ATE ODP) driver <NUM>. In another example, the host may handle the page fault using the host MMU and/or VT-D driver <NUM>. For instance, the host MMU and/or VT-D driver <NUM> may determine whether this is a first or second level fault and where to steer the page fault. First level faults may be handled using the virtual input/output memory management unit (vIOMMU) <NUM> of the virtual machine (VM) <NUM> (e.g., via the VT-D driver <NUM>), while second level faults may be handled directly via the VT-D driver <NUM>.

In either case, the fault handler resolves the fault and returns a successful fault-handling event to the address translation engine on-demand paging (ATE ODP) driver <NUM> (process block <NUM>). The response may be analogous to a Page Request Service (PRS) response that would be made to the peripheral device <NUM>. The response may contain an indication of success along with PRS fields according to the PRS specification, though there may be no host physical address (HPA) returned. Indeed, the address translation engine on-demand paging (ODP ATE) driver <NUM> may have only the guest physical address (GPA) since the page fault has been handled.

Using the guest physical address (GPA), the address translation engine on-demand paging (ATE ODP) driver <NUM> causes the faulted payload stored in the fault buffer to be directly written to the memory <NUM> (process block <NUM>). For example, the address translation engine on-demand paging (ATE ODP) driver <NUM> may make a call to the virtual machine manager (VMM) <NUM> such as, or similar to, kvm_write_guest(). This may directly write the faulted payload and/or completions to the buffer and completion queue <NUM> as allocated by the protocol engine (PE) driver <NUM> corresponding to that virtual machine (VM) <NUM>. The virtual machine manager (VMM) <NUM> may respond to the address translation engine on-demand paging (ATE ODP) driver <NUM> with an indication of success. Thereafter, the address translation engine on-demand paging (ATE ODP) driver <NUM> may respond to the address translation engine (ATE) <NUM> to indicate resolution with respect to the I/O page fault (IPF) handling. In some cases, the address translation engine on-demand paging (ATE ODP) driver <NUM> may also issue interrupts on behalf of the protocol engine (PE) <NUM> to the virtual machine (VM) <NUM> to process completions once the data has been stored in the newly allocated physical memory.

This process is shown visually by way of communication between components in a flow diagram in <FIG>. When the device memory management unit (devMMU) <NUM> identifies a TLB miss in the device translation lookaside buffer (devTLB) <NUM> as well as the associated local device page tables <NUM>, the address translation engine (ATE) <NUM> may issue an ATS translation request message <NUM> to the input/output memory management unit (IOMMU) <NUM>. In response, the input/output memory management unit (IOMMU) <NUM> may check the input/output translation lookaside buffer (IOTLB) <NUM> and walk the page tables <NUM>. Finding no translation, the input/output memory management unit (IOMMU) <NUM> may respond with an ATS completion message <NUM> indicating a page fault (e.g., success with R=W=<NUM>). After a direct memory access (DMA) operation stores the data into a pre-allocated fault buffer (not shown), an I/O page fault (IPF) indication <NUM> may be sent from the address translation engine (ATE) <NUM> on the peripheral device <NUM> to the address translation engine on-demand paging (ATE ODP) driver <NUM> on the processing device <NUM>.

The address translation engine on-demand paging (ATE ODP) driver <NUM> may issue a page fault handle request <NUM> to the VT-D driver <NUM>. For example, the address translation engine on-demand paging (ATE ODP) driver <NUM> may issue a Page Request Service (PRS) request using a non-blocking call to handle_mm_fault(). If the page fault is a second-level fault, the VT-D driver <NUM> may handle it directly. If the page fault is a first-level fault, the VT-D driver <NUM> may issue a page fault request message <NUM> to the virtual input/output memory management unit (vIOMMU) <NUM> by way of the virtual machine manager (VMM) <NUM>. The virtual input/output memory management unit (vIOMMU) <NUM> may resolve the page fault and provide a response <NUM> with the resulting guest physical address (GPA). The VT-D driver <NUM> may issue a response <NUM> returning a successful fault-handling event to the address translation engine on-demand paging (ATE ODP) driver <NUM>. The response <NUM> may contain an indication of success along with PRS fields specified by the PRS specification and indicating the guest physical address (GPA).

Using the guest physical address (GPA), the address translation engine on-demand paging (ATE ODP) driver <NUM> issues a message <NUM> to the virtual machine manager (VMM) <NUM> to cause the faulted payload stored in the fault buffer to be directly written to memory. The message <NUM> may be a call that is, or is similar to, kvm_write_guest(). Once the operation is complete, the virtual machine manager (VMM) <NUM> may issue a response <NUM> to the address translation engine on-demand paging (ATE ODP) driver <NUM> with an indication of success. Thereafter, the address translation engine on-demand paging (ATE ODP) driver <NUM> may issue a page fault response <NUM> to the address translation engine (ATE) <NUM> to indicate that the I/O page fault has been handled. Furthermore, the address translation engine on-demand paging (ATE ODP) driver <NUM> may also issue interrupts to the virtual machine (VM) <NUM> to process completions once the data has been stored in the newly allocated physical memory. In addition, the address translation engine on-demand paging (ATE ODP) driver <NUM> or a component of the peripheral device <NUM> (e.g., the device memory management unit (devMMU) <NUM>) may issue a further request (not shown) to the input/output memory management unit (IOMMU) <NUM> to pre-populate the page information into the input/output translation lookaside buffer (IOTLB) <NUM>. This may avoid a possible page walk due to a TLB miss in the future.

This process may be applied in numerous use cases with different types of peripheral devices. These include a network interface card (NIC), a storage device such as non-volatile memory (e.g., an NVM Express device), a cryptographic engine (e.g., Look-Aside Crypto), a compression engine, a remote direct memory access (RDMA) device, to name just a few. One specific use case is shown by a communication diagram <NUM> in <FIG>, which illustrates the use of on-demand device-assisted paging upon receipt of a data packet by a smart network interface card (NIC). The communication diagram <NUM> illustrates an example set of interactions between the peripheral device (physical network wiring <NUM>, the device translation lookaside buffer (devTLB) <NUM>, the address translation engine (ATE) <NUM>, local area network (LAN) interface circuitry <NUM>, and the host interface (HIF) <NUM>), hardware of the processing device (the input/output memory management unit (IOMMU) <NUM>), an embedded core (an accessory driver <NUM>), the virtual machine (the guest device driver <NUM>, the guest virtual input/output memory management unit (vIOMMU) <NUM>, and the guest MMU <NUM>) and the host kernel (the address translation engine on-demand paging (ATE ODP) driver <NUM> and the memory management unit (MMU) <NUM>).

The communication diagram <NUM> begins as the virtual machine begins an operation <NUM> prepares to receive a packet or stream of packets from the smart NIC. The guest device driver <NUM> (e.g., a guest LAN driver) may allocate DMA memory for the receipt of the packet and may pin, in the guest MMU <NUM>, the guest virtual address (GVA) to the guest physical address (GPA) (message <NUM>). The guest device driver <NUM> may also map the GVA to GPA in the guest virtual input/output memory management unit (vIOMMU) <NUM> (message <NUM>). The guest virtual input/output memory management unit (vIOMMU) <NUM> may issue a request to the input/output memory management unit (IOMMU) <NUM> to create an extended page table (EPT) page table entry that may be unpinned without a physical page allocation (message <NUM>). The guest device driver <NUM> may post the GPA (e.g., a tail bump) at the LAN interface circuitry <NUM> (message <NUM>).

To handle the incoming packet, a receive (RX) write operation <NUM> may begin as the packet arrives on the physical network wiring <NUM> from which it is taken in by the LAN interface circuitry <NUM> (message <NUM>). The LAN interface circuitry <NUM> may issue an address translation request to the device translation lookaside buffer (devTLB) <NUM> (message <NUM>). In this example, the device translation lookaside buffer (devTLB) <NUM> does not have the translation, so the device translation lookaside buffer (devTLB) <NUM> generates a cache miss (message <NUM>). The device translation lookaside buffer (devTLB) <NUM> therefore issues an address translation request via Address Translation Service (ATS) to the input/output memory management unit (IOMMU) <NUM> (message <NUM>). If the input/output memory management unit (IOMMU) <NUM> also lacks the translation, the input/output memory management unit (IOMMU) <NUM> replies with an indication that a page fault has been detected (although the hardware may be unable to identify which type of page fault has been detected (e.g., entry missing, page missing or access violation)) (message <NUM>).

When the page fault is due to true overprovisioning (e.g., rather than due to malicious activity or a missing entry), the device translation lookaside buffer (devTLB) <NUM> may indicate the page fault to the address translation engine (ATE) <NUM> (message <NUM>). The address translation engine (ATE) <NUM> or other components of the peripheral device (e.g., a protocol engine (PE) <NUM> as shown in <FIG>) post the payload in fault buffers and write corresponding descriptors into the fault buffer queue and I/O page fault queue. The address translation engine (ATE) <NUM> may notify the address translation engine on-demand paging (ATE ODP) driver <NUM> with an indication of an I/O page fault (IPF) event (message <NUM>).

The address translation engine on-demand paging (ATE ODP) driver <NUM> may issue a request to the memory management unit (MMU) <NUM> to handle the page fault (e.g., to find a host physical address (HPA) for the corresponding guest physical address (GPA) that has been allocated in the virtual machine but which resulted in a page fault due to not being allocated in host physical memory) (message <NUM>). Once the memory management unit (MMU) <NUM> handles the page fault, the memory management unit (MMU) <NUM> may respond with an indication that the page fault has been successfully handled (message <NUM>). The address translation engine on-demand paging (ATE ODP) driver <NUM> writes the contents of the fault buffer to the physical memory corresponding to the guest physical address (GPA) that has now been allocated (message <NUM>). For instance, the address translation engine on-demand paging (ATE ODP) driver <NUM> may issue a call on behalf of the virtual machine manager (VMM) <NUM> or to the virtual machine manager (VMM) <NUM> such as kvm_write_user() using the GPA. The address translation engine on-demand paging (ATE ODP) driver <NUM> may reply to the address translation engine (ATE) <NUM> when this is complete to indicate that the I/O page fault (IPF) has been resolved and the page fault has been handled (message <NUM>). The address translation engine on-demand paging (ATE ODP) driver <NUM> may also generate a packet receive event (e.g., by writing to a Message Signaled Interrupt- Extensions (MSIX) register such as SW_triggered_MSIX_Interrupt_Register) to the HIF <NUM> to indicate that the packet has been written to its proper destination (message <NUM>). The HIF <NUM> may issue a packet receive event handling message to the guest device driver <NUM> (message <NUM>), allowing the guest device driver <NUM> to process the packet (message <NUM>).

The system may also be able to respond appropriately in the case of a malicious device activity when an access violation is detected at operation <NUM>. Under these conditions, the device translation lookaside buffer (devTLB) <NUM> may indicate the page fault to the address translation engine (ATE) <NUM> and noting that it is due to an access violation (which could be due to malicious activity) (message <NUM>). The address translation engine (ATE) <NUM> or other components of the peripheral device (e.g., a protocol engine (PE) <NUM> as shown in <FIG>) post the payload in fault buffers and write corresponding descriptors into the fault buffer queue and I/O page fault queue. The address translation engine (ATE) <NUM> may notify the address translation engine on-demand paging (ATE ODP) driver <NUM> with an indication of an I/O page fault (IPF) event (message <NUM>).

The address translation engine on-demand paging (ATE ODP) driver <NUM> may issue a request to the memory management unit (MMU) <NUM> to handle the page fault (e.g., to find a host physical address (HPA) for the corresponding guest physical address (GPA) that resulted in a page fault) (message <NUM>). When the memory management unit (MMU) <NUM> attempts to handle the page fault, the memory management unit (MMU) <NUM> may identify that the page fault is due to an access violation and may respond with such an indication (message <NUM>). The address translation engine on-demand paging (ATE ODP) driver <NUM> may issue a request to log the potential malicious activity and trigger a PCIe function reset (message <NUM>).

On-demand device-assisted paging may also be performed with peripheral devices with enhanced security features. In an example shown in <FIG>, the peripheral device <NUM> may interface securely with a secure virtual machine such as a trust domain (TD) <NUM>. In <FIG>, all elements illustrated but not described here should be understood to function in a manner discussed above. Regarding the trust domain (TD) <NUM>, any suitable trusted virtual machine security schemes may be used, such as Intel® Trust Domain Extensions (TDX) by Intel Corporation. These security features may isolate TDs <NUM> from each other, other virtual machines (VMs) <NUM>, the virtual-machine manager (VMM) <NUM>, and any other non-TD software on the platform to protect TDs <NUM> from a broad range of software. The peripheral device <NUM> may interface with the trust domain (TD) <NUM> through a trusted intermediary <NUM> (e.g., a TDX Module by Intel Corporation, a TDXio (a trusted execution environment (TEE) Security Manager) module). Trusted virtual machine security schemes may be used with on-demand device-assisted paging by the peripheral device <NUM> maintaining context information (e.g., process address space ID (PASID) and/or bus/device/function (BDF)) per interface (e.g., different protocol engines <NUM> or different host interfaces (HIFs) <NUM>) on whether the interface belongs to a trust domain (TD) <NUM> or not. This may be configured by a Device Security Manager (DSM) <NUM> running on the peripheral device <NUM>. The peripheral device <NUM> may not be aware of which trust domain (TD) <NUM> that a particular interface belongs to as that may be handled by the trusted intermediary <NUM>. Even so, the peripheral device <NUM> may segregate the page faults into sets corresponding to TDs <NUM> and to virtual machines (VMs) <NUM>.

Claim 1:
A system comprising:
a peripheral device (<NUM>);
a processing device (<NUM>) to run a virtual machine (<NUM>), and
guest memory (<NUM>) allocated to the virtual machine (<NUM>),
wherein the processing device (<NUM>) comprises a buffer allocated to receive a payload from the peripheral device (<NUM>) that attempts to access a page of the guest memory (<NUM>) of the virtual machine (<NUM>) using direct memory access, DMA, in case that the DMA results in an input/output page fault,
wherein the buffer stores the payload while the input/output page fault corresponding to the page of the guest memory (<NUM>) of the virtual machine is resolved,
wherein the processing device (<NUM>) is configured to
receive, from the peripheral device (<NUM>), a descriptor indicating a location of the buffer into a fault buffer queue; and
cause the payload to be copied from the buffer to a newly allocated page of the guest memory (<NUM>) after the input/output page fault is resolved by using the descriptor from the fault buffer queue.